1988_Motorola_Power_MOSFET_Transistor_Data 1988 Motorola Power MOSFET Transistor Data
User Manual: 1988_Motorola_Power_MOSFET_Transistor_Data
Open the PDF directly: View PDF 
.
Page Count: 978
| Download | |
| Open PDF In Browser | View PDF |
Theory and Applications
Chapters 1 through 15
1
Selector Guide
2
Data Sheets
3
I
I
The information in this book has been carefully
checked and is believed to be accurate; however, no
responsibility is assumed for inaccuracies.
Motorola reserves the right to make changes without further notice to any products herein to improve
reliability, function or design. Motorola does,not assume any liability arising out of the application or use
of any product or circuit described herein; neither
does it convey any license under its patent rights nor
the rights of others. Motorola and @ are registered
trademarks of Motorola, Inc. Motorola, Inc. is an
Equal Employment Opportunity/Affirmative Action
Employer.
Motorola, Inc. general policy does not recommend
the use of its components in life support applications
wherein a failure or malfunction of the component
may directly threaten life or injury. Per Motorola
Terms and Conditions of Sale, the user of Motorola
components in life support applications assumes all
risks of such use and indemnifies Motorola against
all damages.
Index and Cros
eference
4
Designer's, GEMFET, SENSEFET, E-FETs,
ICePAK, SMARTMOS, Switchmode, Thermopad, Thermowatt, TMOS and
are trademarks of Motorola Inc.
MOTOROLA TMOS POWER MOSFET DATA
LII
MOTOROLA
POWER MOSFET TRANSISTOR DATA
Prepared by
Technical Information Center
Preface
After several years of development, Motorola introduced its first power MOSFETs in 1980. Several technologies
were evaluated and the final choice was the double diffused (DMOS) process which Motorola has acronymed
TMOS. This process is highly manufacturable and is capable of producing devices with the best characteristics
for product needed for power control. Most suppliers of power MOSFETs use the basic DMOS process.
The key to success of power MOSFETs is the control of vertical current flow, which enables suppliers to
reduce chip siz.es comparable to bipolar transistors. This development opens a new dimension for designers
of power control systems.
This manual is intended to give the users of power MOSFETs the basic information on the product, application
ideas of power MOSFETs and data sheets of the broadest line of power MOSFETs with a variety of package
configurations. The product offering is far from complete. New products will be introduced and old products will
be improved, offering designers an even beUer selection of products for their designs.
Motorola has a long history of supplying high quality power transistors in large volume to the military, automotive, consumer, industrial and computer markets. Being the leading supplier of power transistors in the world,
we strive to serve our customers' needs to maintain our leadership pOSition.
Printed in U.S.A.
Third Edition
First Printing
©MOTOROLA INC., 1988
"All Rights Reserved"
TABLE OF CONTENTS
CHAPTER 1:
CHAPTER 9:
Introduction to Power MOSFETs
Spin-off Technologies of TMOS
Symbols, Terms and Definitions . . . . . . . . . . . . . 1-1-1
Basic TMOS Structure, Operation and Physics.... 1-1-6
Distinct Advantages of Power MOSFETs........ 1-1-9
SENSEFETs . . . . . . . . . . . . . . . . . . . . . . . . , 1-9-1
TMOS II and III . . . . . . . . . . . . . . . . . . . . . . . . 1-9-8
The GEMFET - A New Option for Power
Control . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-9-16
CHAPTER 2:
CHAPTER 10:
Basic Characteristics of Power MOSFETs
Output Characteristics. . . . . . . . . . . . . . . . . . ..
Basic MOSFET Parameters . . . . . . . . . . . . . . . .
Temperature Dependent Characteristics ........
Drain-Source Diode. . . . . . . . . . . . . . . . . . . . . .
1-2-1
1-2-1
1-2-2
1-2-3
CHAPTER 3:
Relative Efficiencies of TMOS
and Other Semi-conductor Power Switches
Temperature Testing High Voltage Devices TMOS versus Bipolar Switchmode I and II .... , 1-10-1
Low Voltage Devices - TMOS versus Bipolar,
Darlington and GTO Devices......, ........ 1-10-6
The GEMFET versus the MOSFET and
Bipolar . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-1 0-10
Using the TMOS Power MOSFET Designer's Data Sheet 1-3-1
CHAPTER 11:
CHAPTER 4:
Hybrid Packaging ofTMOS Die. . . . . . . . . . . . . . . 1-11-1
Design Considerations in Using Power MOSFETs
Safe Operating Areas . . . . . . . . . . . . . . . . . . ..
Drain-Source Overvoltage Protection ........ "
dv/dt Limitations in Power MOSFETs ..........
Protecting the Gate . . . . . . . . . . . . . . . . . . . . "
1-4-1
1-4-3
1-4-5
1-4-7
CHAPTER 5:
Avalanche and dv/dt limitations of the Power
MOSFETs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5-1
CHAPTER 6:
Gate Drive Requirements
Input Capacitance . . . . . . . . . . . . . . . . . . . . . . .
Gate Charge Requirements . . . . . . . . . . . . . . . .
Common Source Switching. . . . . . . . . . . . . . . . .
High Side Switching . . . . . . . . . . . . . . . . . . . . .
1-6-1
1-6-3
1-6-8
1-6-17
CHAPTER 12:
Characterization and Measurements
FBSOA Testing of Power MOSFETs..........
Switching Safe Operating Area (SSOA) ........
Characterizing Drain-to-Source Diodes of
Power MOSFETs for Switchmode
Applications. . . . . . . . . . . . . . . . . . . . . . . ..
Commutating SOA in Monolithic Freewheeling
Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Measurements . . . . . . . . . . . . . . . . . .
Measuring Power MOSFET Capacitances. . . . . .
Characterizing Power MOSFETs for Unspecified
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . .
Power MOSFET Measurement Techniques for
the Curve Tracer. . . . . . . . . . . . . . . . . . . . ..
1-12-1
1-12-5
1-12-10
1-12-16
1-12-20
1-12-24
1-12-26
1-12-28
CHAPTER 13:
Rellabllitr and Qualitr
CHAPTER 7:
Paralleling Power MOSFETs
Paralleling Power MOSFETs in Switching
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7-1
Paralleling Power MOSFETs in Linear
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7-14
Applications of Paralleling MOSFETs .......... 1-7-18
Reliability Tests . . . . . . . . . . . . . . . . . . . . . . .
Audit Program and AOQ Monitors ...........
Essentials of Reliability . . . . . . . . . . . . . . . . . .
Mll- Qualified TMOS . . . . . . . . . . . . . . . . . .
1-13-1
1-13-6
1-13-7
1-13-10
CHAPTER 14:
Mounting Techniques for Power MOSFETs . . . . . . . . 1-14-1
CHAPTER 8:
CHAPTER 15:
TMOS Applications
100 kHz Switchmode Power Supply. . . . . . . . . . .
20 kHz Switchmode Power Supply. . . . . . . . . . . .
Automotive DC-DC Converter. . . . . . . . . . . . . . .
High Voltage Flyback Converter . . . . . . . . . . . . .
Switchmode Power Supply Configurations .......
Motor Controls. . . . . . . . . . . . . . . . . . . . . . . . .
Horizontal Deflection Circuits . . . . . . . . . . . . . . .
Fast, High Current MOSFET Device ...........
1-8-1
1-8-5
1-8-5
1-8-6
1-8-8
1-8-13
1-8-23
1-8-25
Electrostatic Discharge and Power MOSFETs . . . . . . 1-15-1
References
References . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15-5
Theory and Applications Chapters 1 through 15
Ch:g~~J+!~~~~.~~~t~~.~ .t.~ .~~~~~.....
Chapter 2: Basic Characteristics of
Power MOSFETs ..................•..
Chapter 3: Using the TMOS Power
MOSFET Designer's Data Sheet ..•.
1
•
•
Chapter 6: Gate Drive
Requirements ....................... .
••
Ch:g~~l+:'~~~~~~I.i~~. ~~~~~..........
•
Chapter 4: Design Considerations in
Using Power MOSFETs............. .
Chapter 5: Avalanche and dv/dt
Limitations of the Power
MOSFET ............................. .
Chapter 8: TMOS Applications ....... .
Chapter 9: Spin-Off Technologies of
TMOS ....•..•.........................
Chapter 10: Relative Efficiencies of
•
TMOS and Other Semiconductor
Power Switches .......•....•..••..•..
Chapter 11: Hybrid Packaging of
TMOS Die ..•............•..•.....•...
Chapter 12: Characterization and
•
Measurements •......................
Chapter 13: Reliability and Quality ...
•
Chapter 14: Mounting Techniques for
Power MOSFETs •.••.................
•
Chapter 15: Electrostatic Discharge
and Power MOSFETs ........••....•.
•
MOTOROLA TMOS POWER MOSFET DATA
Chapter 1: Introduction to Power MOSFETs
Symbols, Terms and Definitions
The following are the most commonly used letter symbols, terms and definitions associated with Power MOSFETs.
Symbol
Term
Definition
Cds
drain-source capacitance
The capacitance between the drain and source terminals
with the gate terminal connected to the guard terminal of
a three-terminal bridge.
Cdg
drain-gate capacitance
The same as Crss -
Cgs
gate-source capacitance
The capacitance between the gate and source terminals
with the drain terminal connected to the guard terminal of
a three-terminal bridge.
Ciss
short-circuit input capacitance,
common-source
The capacitance between the input terminals (gate and
source) with the drain short-circuited to the source for
alternating current. (Ref. IEEE No. 255)
Coss
short-circuit output capacitance,
common-source
The capacitance between the output terminals (drain and
source) with the gate short-circuited to the source for
alternating current. (Ref. IEEE No. 255)
C rss
short-circuit reverse transfer
capacitance, common-source
The capacitance between the drain and gate terminals with
the source connected to the guard terminal of a threeterminal bridge.
9FS
common-source large-signal
transconductance
The ratio of the change in drain current due to a change
in gate-to-source voltage
10
drain current, dc
The direct current into the drain terminal.
10(on)
on-state drain current
The direct current into the drain terminal with a specified
forward gate-source voltage applied to bias the device to
the on-state.
lOSS
zero-gate-voltage drain current
The direct current into the drain terminal when the gatesource voltage is zero. This is an on-state current in a
depletion-type device, an off-state in an enhancement-type
device.
gate current, dc
The direct current into the gate terminal.
reverse gate current, drain short-circuited
to·source
The direct current into the gate terminal of a junction-gate
field-effect transistor when the gate terminal is reverse biased with respect to the source terminal and the drain terminal is short-circuited to the source terminal.
MOTOROLA TMOS POWER MOSFET DATA
1-1-1
See C rss .
Symbol
Term
Definition
IGSSF
forward gate current, drain short-circuited
to source
The direct current into the gate terminal of an insulatedgate field-effect transistor with a forward gate-source voltage applied and the drain terminal short-circuited to the
source terminal.
IGSSR
reverse gate current, drain short-circuited
to source
The direct current into the gate terminal of an insulatedgate field-effect transistor with a reverse gate-source voltage applied and the drain terminal short-circuited to the
source terminal.
IS
source current, dc
The direct current into the source terminal.
PT,Po
total nonreactive power input to all
terminals
The sum of the products of the dc input currents and
voltages.
Og
total gate charge
The total gate charge required to charge the MOSFETs
input capacitance to VGS(on)'
rOS(on)
static drain-source on-state resistance
The dc resistance between the drain and source terminals
with a specified gate-source voltage applied to bias the
device to the on state.
thermal resistance, case-to-ambient
The thermal resistance (steady-state) from the device case
to the ambient.
thermal resistance, junction-to-ambient
The thermal resistance (steady-state) from the semiconductor junction(s) to the ambient.
thermal resistance, junction-to-case
The thermal resistance (steady-state) from the semiconductor junction(s) to a stated location on the case.
thermal resistance, junction-to-mounting
surface
The thermal resistance (steady-state) from the semiconductor junction(s) to a stated location on the mounting
surface.
ambient temperature or free-air
temperature
The air temperature measured below a device, in an environment of substantially uniform temperature, cooled only
by natural air convection and not materially affected by
reflective and radiant surfaces.
case temperature
The temperature measured at a specified location On the
case of a device.
turn-off crossover time
The time interval during which drain voltage rises from 10%
of its peak off-state value and drain current falls to 10% of
its peak on-state value, in both cases ignoring spikes that
are not charge-carrier induced.
TJ
channel temperature
The temperature of the channel of a field-effect transistor.
Tstg
storage temperature
The temperature at which the device, without any power
applied, may be stored.
Iei(off)
turn-off delay time
Synonym for current turn-off delay time (see Note 1)*.
1cI(0ff)i
current tum-off delay time
The interval during which an input pulse that is switching
the transistor from a conducting to a nonconducting state
falls from 90% of its peak amplitude and the drain current
waveform falls to 90% of its on-state amplitude, ignoring
spikes that are not charge-carrier induced.
Iei(off)v
voltage turn-off delay time
The time interval during which an input pulse that is switching the transistor from a conducting to a nonconducting
state falls from 90% of its peak amplitude and the drain
voltage waveform rises to 10% of its off-state amplitude,
ignoring spikes that are not charge-carrier induced.
Iei(on)
turn-on delay time
Synonym for current turn-on delay time (see Note 1)*.
R8JC
TC
MOTOROLA TMOS POWER MOSFET OATA
'-'-2
Symbol
Term
Definition
td(on)i
current turn-on delay time
The time interval during which an input pulse that is switching the transistor from a nonconducting to a conducting
state rises from 10% of its peak amplitude and the drain
current waveform rises to 10% of its on-state amplitude,
ignoring spikes that are not charge-carrier induced.
id(on)v
voltage turn-on delay time
The time interval during which an input pulse that is switching the transistor from a nonconducting to a conducting
state rises from 10% of its peak amplitude and the drain
voltage waveform falls to 90% of its oft-state amplitude,
ignoring spikes that are not charge-carrier induced.
tf
fall time
Synonym for current fall time (See Note 1)*.
tli
current fall time
The time interval during which the drain current changes
from 90% to 10% of its peak oft-state value, ignoring spikes
that are not charge-carrier induced.
tfv
voltage fall time
The time interval during which the drain voltage changes
from 90% to 10% of its peak off-state value, ignoring spikes
that are not charge-carrier induced.
toft
turn-oft time
Synonym for current turn-oft time (see Note 1)*.
toft(i)
current turn-oft time
The sum of current turn-oft delay time and current fall time,
i.e., td(oft)i + tfi·
toft(v)
voltage turn-oft time
The sum of voltage turn-oft delay time and voltage rise
time, i.e., td(off)v + trv·
ton
turn-on time
Synonym for current turn-on time (See Note 1)*.
ton(i)
current turn-on time
The sum of current turn-on delay time and current rise time,
i.e., td(on)i + trio
ton(v)
voltage turn-on time
The sum of voltage turn-on delay time and voltage fall time,
i.e., id(on)v + ttv·
tp
pulse duration
The time interval between a reference point on the leading
edge of a pulse waveform and a reference point on the
trailing edge of the same waveform.
Note: The two reference points are usually 90% of the steady-state am·
plitude of the waveform existing after the leading edge, measured with
respect to the steady-state amplitude existing before the leading edge. If
the reference points are 50% pOints, the symbol tw and term average
pulse duration should be used.
tti
rise time
Synonym for current rise time (See Note 1)*.
current rise time
The time interval during which the drain current changes
from 10% to 90% of its peak on-state value, ignoring spikes
that are not charge-carrier induced.
voltage rise time
The time interval during which the drain voltage changes
from 10% to 90% of its peak oft-state value, ignoring spikes
that are not charge-carrier induced.
current tail time
The time interval following current fall time during which
the drain current changes from 10% to 2% of its peak onstate value, ignoring spikes that are not charge-carrier
induced.
MOTOROLA TMOS POWER MOSFET DATA
1-1-3
Symbol
•
Term
Definition
average pulse duration
The time interval between a reference point on the leading
edge of a pulse waveform and a reference pOint on the
trailing edge of the same waveform, with both reference
points being 50% of the steady-state amplitude of the waveform existing after the leading edge, measured with respect
to the steady-state amplitude existing before the leading
edge.
Nole: If the reference pOints are not 50% pOints, the symbol
pulse duration should be used.
V(BR)DSR
drain-source breakdown voltage with
(resistance between gate and source)
!p and term
The breakdown voltage between the drain terminal and the
source terminal when the gate terminal is (as indicated by
the last subscript letter) as follows:
R = returned to the source terminal through a specified
resistance.
V(BR)DSS
gate short-circuited to source
S = short-circuited to the source terminal.
V(BR)DSV
voltage between gate and source
V = returned to the source terminal through a specified
voltage.
V(BR)DSX
circuit between gate and source
X = returned to the source terminal through a specified
circuit.
V(BR)GSSF
forward gate-source breakdown voltage
The breakdown voltage between the gate and source terminals with a forward gate-source voltage applied and the
drain terminal short-circuited to the source terminal.
V(BR)GSSR
reverse gate-source breakdown voltage
The breakdown voltage between the gate and source terminals with a reverse gate-source voltage applied and the
drain terminal short-circuited to the source terminal.
VDD,VGG
VSS
supply voltage, dc (drain, gate, source)
voltage
The dc supply voltage applied to a circuit or connected to
the reference terminal.
VDG
VDS
VGD
VGS
VSD
VSG
drain-to-gate
drain-to-source
gate-to-drain
gate-to-source
source-to-drain
source-to-gate
The dc voltage between the terminal indicated by the first
subscript and the reference terminal indicated by the second subscript (stated in terms of the polarity at the terminal
indicated by the first subscript).
VDS(on)
drain-source on-state voltage
The voltage between the drain and source terminals with
a specified forward gate-source voltage applied to bias the
device to the on state.
VGS(th)
gate-source threshold voltage
The forward gate-source voltage at which the magnitude
of the drain current of an enhancement-type field-effect
transistor has been increased to a specified low value.
ZOJA(t)
transient thermal impedance,
junction-to-ambient
The transient thermal impedance from the semiconductor
junction(s) to the ambient.
ZOJC(t)
transient thermal impedance,
junction-to-case
The transient thermal impedance from the semiconductor
junction(s) to a stated location on the case.
Note 1: As names of time intervals for characterizing switching transistors, the terms "fall time" and "rise time" always refer to the change that is taking
place in the magnitude of the output current even though measurements may be made using voltage waveforms. In a purely resistive circuit, the
(current) rise time may be considered equal and coincident to the voltage fall time and the (current) fall time may be considered equal and coincident
to the voltage rise time. The delay times for current and voltage will be equal and coincident. When significant amounts of inductance are present in
a circuit, these equalities and coincidences no longer exist, and use of the unmodified terms delay time, fall time, and rise time must be avoided.
MOTOROLA TMOS POWER MOSFET DATA
1-1-4
-------------
- - - - - - - - 90%
I
I
I
I
Input Voltage
(Idealized wave shape)
---------------1------- 10%
ton "'Ion(i)
I
I. . .1
Itd(on)=td(onli
toll '" tolllil I ..
_,
ltd(oll)=td(ollii I
I
iltr"'tril
~tf"'tfi:
1
I
1
1
1
1
1
~I
I
-------
I
1
1
t ()
I.. on v
Itd(on)vl
I
--1"""-90%
I Drain
I Current
: (Idealized wave shape)
:
I
~tfvl
including spikes caused
by currents that are
not charge-carrier
induced)
+ ____ _
I
toll(v)
I..
I td(oll)v
_I
(Practical wave shape
~-..!+----ID(on)
I
I
___________
Drain
Current
10(011)
.1
I
rtrv:
~
~
--~ ---+------------1--I
I
I
I
1
I
1
I
-----------
FIGURE 1-1 - WAVEFORMS FOR RESISTIVE-LOAD SWITCHING
Input
Voltage
td(off)i
Drain
Current
10%--2% --I~-----ID(off)
I..
_I
I tc (or t xo ) I
1
~..-j
,-tti
,trvl - - - - - - - - - - VDSM
, 1
- - Vclamp or V(BR)DSX
1
- - 90%
(See Note)
--~
1
1
td(oll)v
Drain
I..
Voltage
~
1
1
-,
.. 1,0%--
1
1
~VDD
VDS(on) --'--1:l--;I---~
1
toll(v)
I"
NOTE: Vcl amp (in a clamped inductive-load switching circuit) or V(BR)DSX (in an unclamped circuit) is the peak off-state voltage
excluding spikes.
FIGURE 1-2 - WAVEFORMS FOR INDUCTIVE LOAD SWITCHING, TURN-OFF
MOTOROLA TMOS POWER MOSFET DATA
1-1-5
•
Basic TMOS Structure, Operation and Physics
GATE
+
VG
Structures:
Motorola's TMOS Power MOSFET family is a matrix of
diffused channel, vertical, metal-oxide-semiconductor
power field-effect transistors which offer an exceptionally
wide range of voltages and currents with low rOS(on). The
inherent advantages of Motorola's power MOSFETs include:
• Nearly infinite static input impedance featuring:
- Voltage driven input
- Low input power
- Few driver circuit components
• Very fast switching times
- No minority carriers
- Minimal turn-off delay time
- Large reversed biased safe operating area
- High gain bandwidth product
DRAIN METAL
+ VDD
FIGURE 1-3 - CONVENTIONAL SMALL-8IGNAL MOSFET HAS
LONG LATERAL CHANNEL RESULTING IN RELATIVELY HIGH
DRAIN-Ta-SOURCE RESISTANCE.
• Positive temperature coefficient of on-resistance
- Large forward biased safe operating area
- Ease in paralleling
S
G
D
• Almost constant transconductance
• High dv/dt immunity
• LowCost
Motorola's TMOS power MOSFET line is the latest step
in an evolutionary progression that began with the conventional small-signal MOSFET and superseded the intermediate lateral double diffused MOSFET (LOMOSFET)
and the vertical V-groove MOSFET (VMOSFET).
The conventional small-signal lateral N-channel
MOSFET consists of a lightly doped P-type substrate into
which two highly doped N + regions are diffused, as
shown in Figure 1-3. The N + regions act as source and
drain which are separated by a channel whose length is
determined by photolithographic constraints. This configuration resulted in long channel lengths, low current capability, low reverse blocking voltage and high rOS(on).
Two major changes in the small-signal MOSFET structure were responsible for the evolution of the power
MOSFET. One was the use of self aligned, double diffusion techniques to achieve very short channel lengths,
which allowed higher channel packing denSities, resulting
in higher current capability and lower rOS(on). The other
was the incorporation of a lightly doped N + region between the channel and the N + drain allowing high reverse
blocking voltages.
These changes resulted in the lateral double diffused
MOSFET power transistor (LOMOS) structure shown in
Figure 1-4, in which all the device terminals are ·still on
the top surface of the die. The major disadvantage of this
configuration is its inefficient use of silicon area due to
the area needed for the top drain contact.
T
T
FIGURE 1-4 - LATERAL DOUBLE DIFFUSED MOSFET STRUCTURE FEATURING SHORT CHANNEL LENGTHS AND HIGH PACKING DENSITIES FOR LOWER ON RESISTANCE.
The next step in the evolutionary process was a vertical
structure in which the drain contact was on the back of
the die, further increasing the channel packing density.
The initial concept used a V-groove MOSFET power transistor as shown in Figure 1-5. The channels in this device
are defined by preferentially etching V-grooves through
double diffused N + and P - regions. The requirements
of adequate packing density, efficient silicon usage and
adequate reverse blocking voltage are all met by this configuration. However, due to its non-planar structure, process consistency and cleanliness requirements resulted
in higher die costs.
The cell structure chosen for Motorola's TMOS power
MOSFET's is shown in Figure 1-6. This structure is similar
to that of Figure 1-4 except that the drain contact is
dropped through the N - substrate to the back of the die.
The gate structure is now made with polysilicon sandwiched between two oxide layers and the source metal
MOTOROLA TMOS POWER MOSFET DATA
1-1-6
applied continuously over the entire active area. This two
layer electrical contact gives the optimum in packing density and maintains the processing advantages of planar
LOMOS. This results in a highly manufacturable process
which yields low rOS(on) and high voltage product.
As the drain voltage is increased, the drain current saturates and becomes proportional to the square of the
applied gate-to-source voltage, VGS, as indicated in
Equation (2).
(2)
S
Z
10 = 2L /LCO [VGS-VGS(th)12
Where /L = Carrier Mobility
Co = Gate Oxide Capacitance per unit area
Z = Channel Width
L = Channel Length
These values are selected by the device design engineer to meet design requirements and may be used in
modeling and circuit simulations. They explain the shape
of the output characteristics discussed in Chapter 2 .
•... •.. s ..
J
D
FIGURE 1-5- V-GROOVE MOSFET STRUCTURE HAS SHORT VERTICAL CHANNELS WITH lOW DRAIN-TO-SOURCE RESISTANCE.
Transconductance, 9FS:
The transconductance or gain of the TMOS power
MOSFET is defined as the ratio of the change in drain
current and an accompanying small change in applied
gate-to-source voltage and is represented by Equation (3).
(3) gFS =
~~~~~t)
=
~ /LCO [VGS-VGS(th)l
The parameters are the same as above and demonstrate that drain current and transconductance are directly
related and are a function of the die design. Note that
transconductance is a linear function of the gate voltage,
an important feature in amplifier design.
FIGURE 1-6 - TMOS POWER MOSFET STRUCTURE OFFERS VERTICAL CURRENT FLOW, lOW RESISTANCE PATHS AND PERMITS
COMPACT METALIZATION ON TOP AND BOTTOM SURFACES TO
REDUCE CHIP SIZE.
Operation:
Transistor action and the primary electrical parameters
of Motorola's TMOS power MOSFET can be defined as
follows:
Drain Current, 10:
When a gate voltage of appropriate polarity and magnitude is applied to the gate terminal, the polysilicon gate
induces an inversion layer at the surface of the diffused
channel region represented by rCH in Figure 1-7 (page
A-8). This inversion layer or channel connects the source
to the lightly doped region of the drain and current begins
to flow. For small values of applied drain-to-source voltage, VOS, drain current increases linearly and can be
represented by Equation (1).
(1)
10 =
Z
L /LCO [VGS-VGS(th)l VOS
Threshold Voltage, VGS(th)
Threshold voltage is the gate-to-source voltage required to achieve surface inversion of the diffused channel
region, (rCH in Figure 1-7 page A-8) and as a result,
conduction in the channel.
As the gate voltage increases the more the channel is
"enhanced," or the lower its resistance (rCH) is made,
the more current will flow. Threshold voltage is measured
at a specified value of current to maintain measurement
correlations. A value of 1.0 mA is common throughout the
industry. This value is primarily a function of the gate oxide
thickness and channel doping level which are chosen during the die design to give a high enough value to keep
the device off with no bias on the gate at high temperatures. A minimum value of 1.5 volts at room temperature
will guarantee the transistor remains an enhancement
mode device at junction temperatures up to 150°C.
On-Resistance, rOS(on)=
On-resistance is defined as the total resistance encountered by the drain current as it flows from the drain
terminal to the source terminal. Referring to Figure 1-7,
rOS(on) is composed primarily of four resistive components associated with:
The Inversion channel, rCH; the Gate-Orain Accumulation Region, rACC; the junction FET Pinch region,
rJFET; and the lightly doped Orain Region, rO, as indicated in Equation (4).
(4) rOS(on) = rCH
+
MOTOROLA TMOS POWER MOSFET OATA
1-1-7
rACC
+
rJFET
+
rO
•
S
G
the on-resistance continues to decrease as VGS is increased toward the maximum rating of the device.
Note: rOS(on) is inversely proportional to the carrier mObility. This
means that the rOS(on) of the P-Channel MOSFET is approximately 2.5
to 3.0 times that of a similar N-Channel MOSFET. Therefore, in order
to have matched complementary on characteristics, the ZlL ratio of the
P-Channel device must be 2.5-3.0 times that of the N-Channel device.
This means larger die are required for P-Channel MOSFET's with the
same rOS(on) and same breakdown voltage as an N·Channel device
and thus device capacitances and costs will be correspondingly higher.
•
o
FIGURE 1-7 - TMOS DEVICE ON-RESISTANCE
S
G
Breakdown Voltage, V(BRJOSS:
Breakdown voltage or reverse blocking voltage of the
TMOS power MOSFET is defined in the same manner as
V(BR)CES in the bipolar transistor and occurs as an avalanche breakdown. This voltage limit is reached when
the carriers within the depletion region of the reverse
biased P-N junction acquire suffficient kinetic energy to
cause ionization or when the critical electric field is
reached. The magnitude of this voltage is determined
mainly by the characteristics of the lightly doped drain
region and the type of termination of the die's surface
electric field.
Figure 1-9 shows a schematic representation of the
cross-section in Figure 1-8 and depicts the bipolar transistor built in the epi layer. Point A shows where the emitter
and base of the bipolar is shorted together. This is why
V(BR)OSS of the power FET is equal to V(BR)CES of the
bipolar. Also note the short brings the base in contact with
the source metal allowing the use of the base-collector
junction. This is the diode across the TMOS power
MOSFET.
o
FIGURE 1-8 - TMOS DEVICE PARASITIC CAPACITANCES
Whereas the channel resistance increases with channel
length, the accumulation resistance increases with poly
width and the JFET pinch resistance increases with epi
resistivity and all three are inversely proportional to the
channel width and gate-to-source voltage. The drain resistance is proportional to the epi resistivity, poly width
and inversely proportional to channel width. This says that
the on-resistance of TMOS power FETs with the thick and
high resistivity epi required for high voltage parts will be
dominated by rD.
Low voltage devices have thin, low resistivity epi and
rCH will be a large portion of the total on-resistance. This
is why high voltage devices are "full on" with moderate
voltages on the gate, whereas with low voltage devices
o
o
s
S
FIGURE 1-9 - SCHEMATIC DIAGRAM OF ALL THE COMPONENTS
OF THE CROSS SECTION OF FIGURE 1-7.
MOTOROLA TMOS POWER MOSFET DATA
'-'-8
TMOS Power MOSFET Capacitances:
Two types of intrinsic capacitances occur in the TMOS
power MOSFET - those associated with the MOS structure and those associated with the P-N junction.
The two MOS capacitances associated with the MOSFET cell are:
Gate-Source Capacitance, Cgs
Gate-Drain Capacitance, Cgd
The magnitude of each is determined by !he die geometry
and the oxides associated with the silicon gate.
The P-N junction formed during fabrication of the power
MOSFET results in the drain-to-source capacitance, Cds.
This capacitance is defined the same as any other planar
junction capacitance and is a direct function of the channel
drain area and the width of the reverse biased junction
depletion region.
The dielectric insulator of Cgs and Cgd is basically a
glass. Thus these are very stable capacitors and will not
vary with voltage or temperature. If excessive voltage is
placed on the gate, breakdown will occur through the
glass, creating a resistive path and destroying MOSFET
operation.
Optimizing TMOS Geometry:
The geometry and packing density of Motorola's
MOSFETs vary according to the magnitude of the reverse
blocking voltage.
The geometry of the source site, as well as the spacing
between source sites, represents important factors in efficient power MOSFET design. Both parameters determine the channel packing density, i.e.: ratio of channel
width per cell to cell area.
For low voltage devices, channel width is crucial for
minimizing rOS(on), since the major contributing component of rOS(on) IS rCH. However, at high voltages, the
major contributing component of resistance is rO and thus
minimizing rOS(on) is dependent on maximizing the ratio
of active drain area per cell to cell area. These two conditions for minimizing rOS(on) cannot be met by a single
geometry pattern for both low and high voltage devices.
Distinct Advantages of Power MOSFETs
Power MOSFETs offer unique characteristics and capabilities that are not available with bipolar power transistors. By taking advantage of these differences, overall
systems cost savings can result without sacrificing
reliability.
Speed
Power MOSFETs are majority carrier devices, therefore
their switching speeds are inherently faster. Without the
minority carrier stored base charge common in bipolar
transistors, storage time is eliminated. The high switching
speeds allow efficient switching at higher frequencies
which reduces the cost, size and weight of reactive
components.
MOSFET switching speeds are primarily dependent on
charging and discharging the device capacitances and are
essentially independent of operating temperature.
rating of power handling capability as a function of applied
voltage. The phenomena of second breakdown does not
occur within the ratings of the device. Depending on the
application, snubber circuits may be eliminated or a
smaller capacitance value may be used in the snubber
circuit. The safe operating boundaries are limited by the
peak current ratings, breakdown voltages and the power
capabilities of the devices.
On-Voltage
The minimum on-voltage of a power MOSFET is determined by the device on-resistance rOS(on). For low
voltage devices the value of rOS(on) is extremely low, but
with high voltage devices the value increases. rOS(on)
has a positive temperature coefficient which aids in paralleling devices.
Input Characteristics
The gate of a power MOSFET is electrically isolated
from the source by an oxide layer that represents a dc
resistance greater than 40 megohms. The devices are
fully biased-on with a gate voltage of 10 volts. This significantly simplifies the drive circuits and in many instances the gate may be driven directly from logic integrated circuits such as CMOS and TTL to. control high
power circuits directly.
Since the gate is isolated from the source, the drive
requirements are nearly independent of the load current.
This reduces the complexity of the drive circuit and results
in overall system cost reduction.
Safe Operating Area
Power MOSFETs, unlike bipolars, do not require de-
Examples of Advantages Offered by
MOSFETs
High Voltage Flyback Converter
An obvious way of showing the advantages of power
MOSFETs over bipolars is to compare the two devices in
the same system. Since the drive requirements are not
the same, it is not a question of simply replacing the bipolar with the FET, but one of designing the respective
drive circuits to produce an equivalent output, as described in Figures 1-10 and 1-11.
For this application, a peak output voltage of about 700
V driving a 30 kG load (PO(pk) = 16 W) was required.
With the component values and timing shown, the inductor/device current required to generate this flyback voltage
would have to ramp up to about 3.0 A.
MOTOROLA TMOS POWER MOSFET DATA
1-1-9
+voo" 36V
MR510
vo .. aoov
MTM2N90
01
15V
oJL
68
PW .. 350 JLS
f= 1.7 kHz
1.0 k
FIGURE 1-10 -
TMOS OUTPUT STAGE
Vo "700V
0.01 p,F
0.5 p,F
270
lN914
FIGURE 1-11 -
BIPOLAR DRIVER AND OUTPUT STAGE
FIGURES 1-10 AND I-II - CIRCUIT CONFIGURATIONS FOR A TMOS AND
BIPOLAR OUTPUT STAGE OF A HIGH VOLTAGE FLYBACK CONVERTER
Figure 1-10 shows the TMOS version. Because of its
high input impedance, the FET, an MTM2N90, can be
directly driven from the pulse width modulator. However,
the PWM output should be about 15 volts in amplitude
and for relatively fast FET switching be capable of sourcing and sinking 100 mA. Thus, all that is required to drive
the FET is a resistor or two. The peak drain current of 3.2
A is within the MTM2N90 pulsed current rating of 7.0 A
(2.0 A continuous), and the turn-off load line of 3.2 A, 700
V is well within the Switching SOA (7.0 A, 900 V) of the
device. Thus, the circuit demonstrates the advantages of
TMOS:
• High input impedance
• Fast Switching
• No Second breakdown
Compare this circuit with the bipolar version of Figure
1-11.
To achieve the output voltage, using a high voltage
Switchmode MJ8505 power transistor, requires a rather
complex drive circuit for generating the proper IB1 and
IB2. This circuit uses three additional transistors (two of
which are power transistors), three Baker clamp diodes,
eleven passive components and a negative power supply
for generating an off-bias Voltage. Also, the RBSOA
capability of this device is only 3.0 A at 900 V and 4.7 A
at 800 V, values below the 7.0 A, 900 V rating of the
MOSFET. A detailed description of these circuits is shown
in Chapter 7, TMOS applications.
20 kHz Switcher
An example of TMOS advantage over bipolar that ii-
MOTOROLA TMOS POWER MOSFET DATA
1-1-10
+170V
lN4933
VCC
+10 p.F
MC34060
MC3406
01
MTP4N50
02
'--_ _.... 200
PWM
47
MJE13005
MPSA55
FIGURE 1-13 - BIPOLAR VERSION
FIGURE 1-12 - TMOS VERSION
FIGURES 1-12 AND 1-13 - COMPARISON OF TMOS versus
BIPOLAR IN THE POWER OUTPUT STAGE OF A
20 kHz SWITCHER
lustrates its superior switching speed is shown in the
power output section of Figures 1-12 and 1-13. In addition
to the drive simplicity and reduced component count, the
faster switching speed offers better circuit efficiency. For
this 35 W switching regulator, using the same small heatsink for either device, a case temperature rise of only 18°C
was measured for the MTP4N50 power MOSFET compared to a 46°C rise for the MJE13005 bipolar transistor.
Although the saturation losses were greater for the TMOS,
its lower switching losses predominated, resulting in a
more efficient switching device. A more detailed description of this Switcher is shown in Chapter 9.
In general, at low switching frequencies, where static
losses predominate, bipolars are more efficient. At higher
frequencies, above 30 kHz to 100 kHz, the power MOSFETs are more efficient.
MOTOROLA TMOS POWER MOSFET DATA
,-,-"
•
MOTOROLA TMOS POWER MOSFET DATA
1-1-12
Chapter 2: Basic Characteristics of Power MOSFETs
Output Characteristics
One of the three obvious differences between Figures
2-1 and 2-2 is the family of curves for the power MOSFET
is generated by changes in gate voltage and not by base
current variations. A second difference is the slope of the
curve in the bipolar saturation region is steeper than the
slope in the ohmic region of the power MOSFET indicating
that the on-resistance of the MOSFET is higher than the
effective on-resistance of the bipolar.
The third major difference between the output characteristics is that in the active regions the slope of the bipolar
curve is steeper than the slope of the TMOS curve, making the MOSFET a better constant current source. The
limiting of 10 is due to pinch-off occurring in the MOSFET
channel.
.
Perhaps the most direct way to become familiar with
the basic operation of a device is to study its output characteristics. In this case, a comparison of the MOSFET
characteristics with those of a bipolar transistor with similar ratings is in order, since the curves of a bipolar device
are almost universally familiar to power circuit design engineers.
As indicated in Figures 2-1 and 2-2, the output characteristics of the power MOSFET and the bipolar transistor can be divided similarly into two basic regions. The
figures also show the numerous and often confusing terms
assigned to those regions. To avoid possible confusion,
this section will refer to the MOSFET regions as the "on"
(or "ohmic") and "active" regions and bipolar regions as
the "saturation" and "active" regions.
Basic MOSFET Parameters
On-Resistance
POWER MOSFET
The on-resistance, or rOS(on), of a power MOSFET is
an important figure of merit because it determines the
amount of current the device can handle without excessive power dissipation. When switching the MOSFET from
off to on, the drain-source resistance falls from a very high
value to rOS(on), which is a relatively low value. To minimize rOS(on) the gate voltage should be large enough
for a given drain current to maintain operation in the ohmic
region. Oata sheets usually include a graph, such as Figure 2-3, which relates this information. As Figure 2-4 indicates, increasing the gate voltage above 12 volts has a
diminishing effect on lowering on-resistance (especially in
high voltage devices) and increases the possibility of spurious gate-source voltage spikes exceeding the maximum
gate voltage rating of 20 volts. Somewhat like driving a
bipolar transistor deep into saturation, unnecessarily high
gate voltages will increase turn-off time because of the
excess charge stored in the input capacitance. All
Motorola TMOS FETs will conduct the rated continuous
drain current with a gate voltage of 10 volts.
As the drain current rises, especially above the continuous rating, the on-resistance also increases. Another
important relationship, which is addressed later with the
other temperature dependent parameters, is the effect
that temperature has on the on-resistance. Increasing TJ
and 10 both effect an increase in rOS(on) as shown in
Figure 2-5.
10
iii
~
9.0
8.0
~ 7.0
...~
6.0
0:
§
u
5.0
z 4.0
~
c
E
3.0
2.0
1.0
o
o
4.0
8.0
12
16
VDS DRAIN-SOURCE VOLTAGE (VOLTS)
FIGURE 2-1 - ID-VDS TRANSFER CHARACTERISTICS OF
MTPBNI5. REGION A IS CALLED THE OHMIC, ON, CONSTANT RESISTANCE OR LINEAR REGION. REGION B IS CALLED THE ACTIVE, CONSTANT CURRENT, OR SATURATION REGION.
BIPOLAR POWER TRANSISTOR
10
[f
~
9.0
8.0
~ 7.0
w
~ 6.0
Transconductance
::::>
~ 5.0
§
Since the transconductance, or gFS, denotes the gain
of the MOSFET, much like beta represents the gain of
the bipolar transistor, it is an important parameter when
the device is operated in the active, or constant current,
region. Oefined as the ratio of the change in drain
current corresponding to a change in gate voltage
(9FS = dIO/dVGS), the transconductance varies with operating conditions as seen in Figure 2-6. The value of 9FS
is determined from the active portion of the VOS-IO transfer characteristics where a change in VOS no longer significantly influences 9FS' Typically the transconductance
rating is specified at half the rated continuous drain current
and at a VOS of 15 V.
4.0
~ 3.0
8
2.0
9
1 .0
·0
o
4.0
8.0
12
16
VCE. COLLECTOR-EMITIER VOLTAGE (VOLTS)
FIGURE 2-2 - IC-VCE TRANSFER CHARACTERISTICS OF
MJE15030 (NPN, Ic CONTINUOUS = B.O A, VCEO = 150 V) REGION
A IS THE SATURATION REGION. REGION B IS THE LINEAR OR
AcnVE REGION.
MOTOROLA TMOS POWER MOSFET OATA
1-2-1
•
.0
1.25
~
VOS=30V
.0
J
1.20
I'
w1.15
i;i~ 1.10
~ 1.05
~
;/"
TJ = 100DC i--
0
WI-
2.0
4.0
6.0
MTP25N~
a:
~0.85
25A,60V
0.80
8.0
10
4
VGSo GATE-TO-SOURCE VOLTAGE (VOLTS)
,.....,
::E
:J::
Q
~ 0.4
TJ = 100D C
>!'
!!l
TJ = 25 D C
~ 0.3
~
:::>
~
- --
I
MTP5N40
5A,fV-
.............
8
10
12
14
16
VGS. GATE-TO-SOURCE VOLTAGE (VOLTS)
-
--18
20
3.0
VDS= 15V
!--
Tc = 250C
,./
Curve F aU. a.
Device Enters
Ohmic Region
(VDS Dependent)
.--
TJ = -55 D C
0.2
-
FIGURE 2-4 - THE EFFECT OF GATE·T0-50URCE
VOLTAGE ON ON·RESISTANCE VARIES WITH A DEVICE'S
VOLTAGE RATING
FIGURE 2-3 - TRANSFER CHARACTERISTICS OF MTP4N50
iii 0.5
"-
MTP1Nl00_
1 A. 1000 V
~
~0.95
0.75
\
~\
:!j 0.90
D
....::: ~
"-
o
_25 D C
J. IIf- --55 C
0
.........
~ 1.00
L\
\
z
«
25 o. 1
c
~
0
o
5.0
10
15
20
o~~~~~~~~~~~~~~
4.0
5.0 6.0
7.0 8.0 9.0 10
11
12
25
VGS. GATE-TO-SOURCE VOLTAGE (VOLTS)
10. DRAIN CURRENT (AMPS)
FIGURE 2·5 - VARIATION OF 'DS(o") WITH DRAIN
CURRENT AND TEMPERATURE FoA MTM15N45
FIGURE 2--6 - SMALL·SIGNAL TRANSCONDUCTANCE
versus VGS OF MTP8Nl0
Temperature Dependent Characteristics
For designers interested only in switching the power
MOSFET between the on and off states, the transconductance is often an unused parameter. Obviously when
the device is switched fully on, the transistor will be op·
erating in its ohmic region where the gate voltage will be
high. In that region, a change in an already high gate
voltage will do little to increase the drain current; therefore,
gFS is almost zero.
rOS(on)
Junction temperature variations and their effect on the
on-resistance, rDS(on), should be considered when de·
signing with power MOSFETs. Since rOS(on) varies ap·
proximately linearly with temperature, power MOSFETs
can be assigned temperature coefficients that describe
this relationship.
Figure 2-7 shows that the temperature coefficient of
rDS(on) is greater for high voltage devices than for low
voltage MOSFETs. A graph showing the variation of
rDS(on) with junction temperature is shown on most data
sheets.
Threshold Voltage
Threshold Voltage, VGS(th), is the lowest gate voltage
at which a specified small amount of drain current begins
to flow. Motorola normally specifies VGS(th) at an 10 of
one milliampere. Device designers can control the value
of the threshold voltage and target VGS(th) to optimize
device performance and practicality. A low threshold voltage is desired so the TMOS FET can be controlled by
low voltage chips such as CMOS and TTL. A low value
also speeds switching because less current needs to be
transferred to charge the parasitic input capacitances. But
the threshold voltage can be too low if noise can trigger
the device. Also, a positive-going voltage transient on the
drain can be coupled to the gate by the gate-to-drain
parasitic capacitance and can cause spurious turn-on of
a device with a low VGS(th)'
Switching Speeds are Constant with Temperature
High junction temperatures emphasize one of the most
desirable characteristics of the MOSFET, that of low dy·
namic or switching losses. In the bipolar tranSistor, temperature increases will increase switching times, causing
greater dynamic losses. On the other hand, thermal var·
iations have little effect on the switching speeds of the
power MOSFET. These speeds depend on how rapidly
the parasitic input capacitances can be charged and discharged. Since the magnitudes of these capacitances are
MOTOROLA TMOS POWER MOSFET DATA
1-2-2
essentially temperature invariant, so are the switching
speeds. Therefore, as temperature increases, the dynamic losses in a MOSFET are low and remain constant,
while in the bipolar transistors the switching losses are
higher and increase with junction temperature.
Importance of TJ(max) and Heat Sinking
Two of the packages that commonly house the TMOS
die are the TO-220AB and the TO-204. The power ratings
of these packages range from 40 to 250 watts depending
on the die size and the type of materials used in construction. These ratings are nearly meaningless, however,
unless some heat sinking is provided. Without heat sinking
the TO-204 and the TO-220 can dissipate only about 4.0
and 2.0 watts respectively, regardless of the die size.
Because long term reliability decreases with increasing
junction temperature, TJ should not exceed the maximum
rating of 150°C. Steady-state operation above 150°C also
invites abrupt and catastrophic failure if the transistor experiences additional transient thermal stresses. Excluding
the possibility of thermal transients, operating below the
rated junction temperature can enhance reliability. A
TJ(max) of 150°C is normally chosen as a safe compromise between long term reliability and maximum power
dissipation.
In addition to increasing the reliability, proper heat sinking can reduce static losses in the power MOSFET by
decreasing the on-resistance. rDS(on), with its positive
temperature coeffiCient, can vary significantly with the
quality of the heat sink. Good heat sinking will decrease
the junction temperature, which further decreases
rDS(on) and the static losses.
Drain-To-Source Breakdown Voltage
The drain-to-source breakdown voltage is a function of
the thickness and resistivity of a device's N-epitaxial
region. Since that resistivity varies with temperature, so
does V(BR)DSS. As Figure 2-8 indicates, a 100°C rise in
junction temperature causes a V(BR)DSS to increase by
about 10%. However, it should afso be remembered that
the actual V (BR)DSS falls at the same rate as T J
decreases.
2.0
~
z
/
1.8
/
/
~
V
ff3 1.6
a;
z
o
400 v MOSFET/
~ 1.4
i
V
~ 1.2
./
/
/
...... V
60 V MOSFET
V
,/
1.0 ~ ~
25
50
/
./
/
Drain-Source Diode
100
75
TJ, JUNCTION TEMPERATURE
Inherent in most power MOSFETs, and all TMOS transistors, is a "parasitic" drain-source diode. Figure 2-9, the
illustration of cross section of the TMOS die, shows the
P-N junction formed by the P-well and the N-Epi layer.
Because of its extensive junction area, the current ratings
of the diode are the same as the MOSFET's continuous
and pulsed current ratings. For the N-Channel TMOS FET
shown in Figure 2-10, this diode is forward biased when
the source is at a positive potential with respect to the
drain. Since the diode may be an important circuit element, Motorola Designer's Data Sheets specify typical
values of the forward on-voltage, forward turn-on and reverse recovery time. The forward characteristics of the
drain-source diodes of several TMOS power MOSFETs
are shown in Figure 2-11.
150
125
FIGURE 2-7 - THE INFLUENCE OF JUNCTION
TEMPERATURE ON ON-RESISTANCE VARIES WITH
BREAKDOWN VOLTAGE
Threshold Voltage
The gate voltage at which the MOSFET begins to conduct, the gate-threshold voltage, is temperature dependent. The variation with TJ is linear as shown on most
data sheets. Having a negative temperature coefficient,
the threshold voltage falls about 10% for each 45°C rise
in the junction temperature.
ttl 1.20
«
~1,15
>
~ 1.10
; 1.05
............
~ 1,00
.......... V
=>
5l 0.95
~
...............
-- ---
V
~
:Z 0.90
~
:; 0.85
!i;l
~ 0.80
~ -50
oz
-25
25
50
75
100
TJ, JUNCTION TEMPERATURE lOCI
125
150
FIGURE 2-8 - TYPICAL VARIATION OF DRAIN-TO-SOURCE
BREAKDOWN VOLTAGE WITH JUNCTION TEMPERATURE
FIGURE 2-9 - CROSS SECTION OF TMOS CELL
MOTOROLA TMOS POWER MOSFET DATA
1-2-3
•
I
I
play an important and useful role. Each transistor is protected from excessive flyback voltages, not by its own
drain-source diode, but by the diode of the opposite transistor. As an illustration, assume that 02 of Figure 2-13
is turned on, 01 is off and current is flowing up from
ground, through the load and into 02. When 02 turns off,
current is diverted into the drain-source diode of 01 which
clamps the load's inductive kick to V + . By similar reasoning, one can see that 02 protects 01 during its turnoff.
As a note of caution, it should be realized that diode
recovery problems may arise when using MOSFETs in
multiple transistor configurations. A treatment of the subject in Chapter 5 gives greater details.
TMOS power MOSFET intrinsic diodes also have forward recovery times, meaning that they do not insfantaneously conduct when they are forward biased. However,
since those times are so brief, typically less than 10 ns,
their effect on circuit operation can almost always be ignored. Package, lead and wiring inductance are often at
least as great a factor in limiting current rise time.
Drain
Gate~
Source
FIGURE 2-10 - N-CHANNEL POWER MOSFET SYMBOL
INCLUDING DRAIN-SOURCE DIODE
Most rectifiers, a notable exception being the Schottky
diode, exhibit a "reverse recovery" characteristic as depicted in Figure 2-12. When forward current flows in a
standard diode, a carrier gradient is formed in the high
resistivity side of the junction resulting in an apparent
storage of charge. Upon sudden application of a reverse
bias, the stored charge temporarily produces a negative
current flow during the reverse recovery time, or t rr , until
the charge is depleted. The circuit conditions that influence trr and the stored charge are the forward current
magnitude and the rate of change of current from the
forward current magnitude to the reverse current peak.
When tested under the same circuit conditions, the parasitic drain-source diode of a TMOS transistor has a trr
similar to that of a fast recovery rectifier.
In many applications, the drain-source diode is never
forward biased and does not influence circuit operation.
However, in multi-transistor configurations, such as the
totem pole network of Figure 2-13, the parasitic diodes
o
~
!ffi
MTP25NO~./"~
MTP1SN15
MTM1SN06E
MTP8N10
/i
/ /
~
"I
10
~
fJ
1.0
~o;
a
~;1N60
I, /'
li/!
~
I
r:i ~
+v
/,
/
'/
1:111
I
01
TC = 25'C
300 I'S Pulse 60 pps
(
, I
I
I
ID, Continuous
MTP1N60:
MTP5N06:
MTP8Nl0:
MTP15N06E:
MTP15N15:
MTP25N06:
02
-v
FIGURE 2-13 - TMOS TOTEM POLE NETWORK
WITH INTEGRAL DRAIN-SOURCE DIODES
FIGURE 2-11 - FORWARD CHARACTERISTICS
OF POWER MOSFETs D-S DIODES
MOTOROLA TMOS POWER MOSFET DATA
1-2-4
.,.
REVERSE RECOVERY CHARACTERISTICS OF
MTP15N15 DRAIN-SOURCE DIODE
W/,'
~
8o
.~
,. , /
' MTPSN06',./
/
/11
~jI
f,
a~ s.o
IiII1!
t = 100 ns/div
FIGURE 2-12 -
100
SO
~
Is = o.s A/div
Chapter 3: Using the TMOS Power MOSFET Designer's
Data Sheets
Motorola Designer's Data Sheets are user oriented
guides that provide information concerning all the basic
TMOS parameters and characteristics needed for successful circuit design. An example of the MTM4N45 data
sheet is shown on the following pages. Helpful comments
and explanations have been added to clarify some of the
parameter definitions and device characteristics.
Designer's Data Sheet
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
These TMOS Power FETs are designed for high voltage, high
speed power switching applications such as line operated switching
regulators. converters, solenoid and relay drivers.
•
Silicon Gate for Fast Switching Speeds Specified at 1QODe
•
Designer's Data -lOSS, VDS(on}, SOA and VGS(th} Specified at
Elevated Temperature
•
Rugged -
I
I
~
Switching Times
SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive Loads
MAXIMUM RATINGS
• Represent the extreme capabilities of the de-
vice.
0
1r
l--
• Not to be used as design condition.
vGS
• Most Motorola TMOS power MOSFETs feature a rated VGS(max} of ±20 V. Logic level
devices are the exception.
• Exceeding VJ!s(max) may result in permanent device egradation.
• Limit gate voltage spikes with a small 20 V
zener diode if required. (10 V for l2 devices)
-
10 - MAXIMUM CONTINUOUS DRAIN
CURRENT
10M - MAXIMUM PULSED DRAIN
CURRENT MAY BE LIMITED BY
•
•
•
•
Po
rOS(on)
Wire size and metallization
Combination of the above
"-
TJ(max) - MAXIMUM JUNCTION
TEMPERATURE
• Reflects a minimum acceptable device service lifetime.
• Presently specified at 15O"C for all Motorola
_MOSFETs.
• Operating at conditions that guarantee a
junction temperature less than TJ(max) may
enhance long term operating life.
to
~
S
MAXIMUM RATINGS
Symbot
MTM4N46
MTP4N46
MTM4N60
MTP4N60
Unit
Drain-Source Voltage
VOSS
450
500
Vdc
Drain -Gate Voltage
(RGS = 1.0 ;"0)
VOGR
450
500
Vdc
Rating
L.....,
Po - MAXIMUM POWER AT A CASE
TEMPERATURE OF 25°C
• Limit Po and TC so that TC + PO· R8JC
< TJ(max}
G
TMDS
Gate-Source Voltage
Drain Current
Continuous
Pulsed
VGS
±20
Vdc
Adc
10
10M
Total Power
Dissipation @ TC = 25°C
Derate above 25°C
Operating and Storage
4.0
10
75
Watts
0.6
WIDC
TJ, Tstg
-65 to 150
?C
R9JC
1.67
DC/W
TL
275
DC
Po
Temperature Range
THERMAL CHARACTERISTICS
'-
Thermal Resistance
Junction to Case
Maximum Lead Temp. for
Soldering Purposes, 1 IS"
from case tor 5 seconds
O••igner'. Data for "Worst
ea.... Condition.
The Designer's Data Sheet permits the design of most circuits entirely from the
information presented. limit data - representing device C(haracteristics boundaries - are
given to facilitate "worst case" design.
TMOS and Designer's are trademarks of Motorola Inc.
MOTOROLA TMOS POWER MOSFET DATA
1-3-1
Designer's Data Sheets
Motorola TMOS Power FETs are characterized on "Designer's Data Sheets." These data sheets permit the design of
most circuits entirely with the information provided. Key parameters are specified at elevated temperature to provide
practical circuit designs.
I
rII-
ELECTRICAL CHARACTERISTICS (Tc = 25°C unless otherwise noted)
I
Characteristic
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = O. 10 = 5.0 mAl
Symbol
Min
Max
450
500
-
-
0.25
2.5
V(BR)OSS
MTM4N45/MTP4N45
MTM4N50/MTP4N50
Zero Gate Voltage Drain Current
(VOS = 0.85 Rated VOSS. VGS = 0)
Tc= lOOOC
Gate-Body Leakage Current
(VGS = 20 Vde. VOS = 0)
lOSS
Unit
Vde
-
mAde
500
IGSS
nAde
V(BR)OSS (BVOSS)
• Maximum sustaining voltage
• No "negative resistance" region in the I·V
characteristic
• Positive temperature coefficient, as shewn in Figure 3-1
I •lOSSSpecified at 25'C and l00'C
I
I
• Gate must be terminated to source
I
IGSS
• Specified at max. rated VGS
ON CHARACTERISTICS·
r-
Gate Threshold Voltage
(10= 1.0mA. VOS=VGS)
TJ= 100°C
VGS(th)
VOS(on)
I-
prain·Souree On-Voltage (VGS = 10 V)
(10 = 2.0 Ade)
(10 = 4.0 Ade)
(10 = 2.0 Ade, TJ = 100°C)
.... Static Drain-Source On-Resistance
(VGS = 10 Vdc, 10 = 2.0 Adc)
Vde
rOS(on)
... Forwar~ Transconductance
(VOS = 15 V, 10= 2.0 A)
2.0
1.5
4.5
4.0
-
-
3.0
7.5
6.0
-
1.6
1.5
9FS
Vdc
Ohms
mhos
VGS(th)
• Tho gate voltage that must be applied to initiate con·
duction (Figure 3-3).
• Specified at 25'C and l00'C
• Negative temperature ccefflclant of about - 6.7 mVi
'C (Agure 3·4).
VOS(on). rOS(on)
• rOS(on)
=~
10
• AnaIogcus to tho VCE(sat) of a bipolar device
• SpecifIed with a maximum VGS of 10 V for Motorola
TMOS powar MOSFET•.
• Specified at 25'C and 10O'C
• PosItIve temperature ccefflclent promoles current
shoring when devices are paralleled.
9FS
• Tho MOSFET "gain" parameter - analogous to hFE
• Equal to the slope of the transler characteristic
(Figure 2-7).
d.10
9FS = d.VGS
• In current saturation region (Rgure 3-3).
Id = 9FS [VGS - VGS(th)1
• Relatively constant for VGS(th) < VGS < VOS +
VGS(th)
MOTOROLA TMOS POWER MOSFET DATA
1-3-2
2.5
VGS = 0
I--- -10 = 0.25mA
,....
V
.....- V
-
100
150
-SO
50
NORMALIZED BREAKDOWN VOLTAGE
versus TEMPERATURE
- f--.
o
o
1.1
//,
~
Vos = VGS
10 = lmA
~
"-..
~
ll!
25"C
""
0.9
:I:
'II
"'"
>
....
:I:
h r;- --55'C
..6
'"
!!:l
~
0
.I
= lOWC
1.2
0
~
//1
TJ
0-
~
:;;
I'
J
= 30V
150
FIGURE 3-2 - NORMALIZED ON-RESISTANCE
versus TEMPERATURE
IA
VOS
100
TJ, JUNCTION TEMPERATURE I'CI
TJ, JUNCTION TEMPERATURE I'CI
FIGURE 3-1 -
i-"
./
-
o
200
/'
V
......
-
so
-50
c-- f-- VGS = 10V
10 = 2mA
~
~
~
0.8
'"
0.7
~
'"
10
8
VGS, GATE-TCJ.SOURCE VOLTAGE IVOLTSI
-SO
>
i'-,
"-
".........
-25
SO
25
100
75
125
TJ, JUNCTION TEMPERATURE I"CI
FIGURE 3-4 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
FIGURE 3-3 - TRANSFER CHARACTERISTICS
DYNAMIC CHARACTERISTICS
Symbol
Characteristic
Input Capacitance (VOS
=
Output Capacitance (VOS
25 V, VGS
=
=
25 V, VGS
Reverse Transfer Capacitance (VOS
=
0, f
=
1 MHz)
= 0, f =
25 V, VGS
1 MHz)
=
0, f
Min
-
Ciss
Coss
=
1 MHz)
Crss
Max
Unit
1200
pF
300
pF
80
pF
2500
MOSFET CAPACITANCES
-
The physical structure of a MOSFET results in capacitors between the terminals. The metal oxide gate
structure determines the capacitors from gate-to-drain
(Cgd) , and gate-to-source (C~s). The PN junction
formed during the fabrication of he TMOS FET results
in a junction capacitance from drain-to-source (Cds)'
These capacitances are characterized as input (Ciss),
output (Coss) and reverse transfer (C rss) capacitances
on data sheets.
Specification of MOSFET capacitance at a VDS of
25 V has become somewhat of a standard, so that
information is provided in aU TMOS data sheets.
"'
2000
~
~ 1500
-
TJ
= 25"C
VGS
~
=0
~
~
5u
1000
500
00
vos
0
Ciss
~
-5
vGS-
I-vos
5
GATE-TO-50URCE OR ORAIN-TO-50URCE VOLTAGE (VOLTS)
(continued)
MOTOROLA TMOS POWER MOSFET DATA
1-3-3
15
COBS >-crs•
25
35
FIGURE 3-5
lSO
MOSFET CAPACITANCE (continued)
However, its usefulness in determining or comparing
switching speeds or input or output capacitance is diminished since the magnitude of the capacitances vary
significantly during the switching transition. Curves
showing capacitance versus voltage are more indicative of device performance since the curves clearly
show the capacitance variation.
The capacitance curves shown in Figure 3-5 are an
extension of those originally published in data sheets.
The portion of the graph to the right of zero is equivalent
to the traditional representation. The additional section
to the left of zero gives an indication of the input capacitance when the MOSFET is "on" or entering into
its "on" state.
A graph of gate charge versus gate voltage is another
and often more descriptive means of relating the magnitude of the input impedance.
In driving a MOSFET, the input capacitance, Ciss
is an important parameter. This capacitance must be
charged and discharged by the drive circuit to effect
the switching function. The impedance of the drive
source strongly affects the switching speed of a
MOSFET. The lower the driving source impedance,
the faster the switching speeds. Temperature variations have little effect on the device capacitances;
therefore, switching times are affected very little by
temperature variations.
SWITCHING CHARACTERISTICS' (TJ = 100"C)
Characteristic
,--.
Turn-On Delay Time (VOS = 25 V. 10 = 2.0 A. Roen = 50 ohms)
Rise Time (VOS = 25 V. 10 = 2.0 A. Raen = 50 ohms)
Turn-Off Delay Time (VOS = 25 V. 10 = 2.0 A. Rllen = 50 ohms)
Symbol
Min
Max
Idlon)
Ir
-
50
100
Iel(off)
If
Fall Time (VOS = 25 V. 10 = 2.0 A. Rgen = 50 ohms)
200
100
Unit
ns
ns
ns
ns
Switching Characteristics
MOSFET switching speeds are very fast. relative to comparably sized bipolar transistors. Since they are majority carrier
devices. there is no storage time associated with the turn-off time; consequently. the switching waveform components
are associated with the charging and discharging of the interelectrode capacitances. Driving a MOSFET through a switching
cycle involves driving these non-linear capacitances. Switching times. therefore. will strongly depend on the impedances
of the driving source and drain load. Maximum limits are specified at elevated temperature.
Motorola normally uses a terminated, 50 n generator in the gate drive to specify switching speeds. Note that the
generator and termination impedance combine to make a 25 n gate drive impedance. Using this gate drive as a standard
helps facilitate correlation of test results. Typical switching times for various gate drive impedances. are shown in Figure
3-8.
For Resistive Switching:
• During !d(on) - The drive circuit charges Ciss to VG~th). No drain current flows; VDS remains essentially at VDD.
• During tr
- Ciss is charged by the drive circuit to GS(on). Coss discharges from VDD to approach VDS(on) and
ID increases from zero. approaching its maxImum. As VDS approaches VDS~n). the rapid rise of
Coss at low drain voltages delays the rise of ID. likewise the increase of Ciss in ibits the rise of VGS
through the drive impedance.
• During !d(ol!) - Ciss begins to discharge through the gate circuit impedance. The transistor turns off and the drain
supply charges Coss through the load. The initial rise of VDS is slowed by the high value of Coss at
low drain voltages.
- Coss diminishes rapidly as the drain voltage rises. Virtually no additional charge is required to be
• During tf
sourced by the drain supply; VDS rises rapidly to VDD (and beyond if inductance is present in the
load).
-
Resistive Switching
Voo
RJ
~Vout
PULSE GENERATOR
r------.,
OUT
tdlonl
OUTPUT. VOUI
INVERTED
I Rgen ...---'INI..--+-+ I
I
I
INPUT. Vin
IL _____ _
FIGURE 3-6 - SWITCHING ·TEST CIRCUIT
FIGURE 3-7 - SWITCHING WAVEFORMS
MOTOROLA TMOS POWER MOSFET DATA
1-3-4
·cr4':T·
~
!;!;j
>=
. tir4N50
TJ ~ 25"C
ID ~ 2.5A
VDO ~ 25 V
. VGS ~ 10 V
200 ._' -
1300
1000
..
f--
0=.'
-=
Idl,offl
-.
I,I~I
.
I~{~~\
100
:::..
_.
. .-
20
...--
10
50
100
250
500
RG, GATE RESISTANCE {OHMSI
FIGURE 3-8
GATE CHARGE CHARACTERISTICS
Characteristic
Symbol
Min
Max
Unit
Qg
27 (typ)
32
nC
Qas
17 (typ)
-
Qqd
10 (typ)
-
Total Gate Charge
(VOS ~ 0.8 Rated VOSS,
10 ~ 4 Amps, VGS ~ 10 V)
Gate-Source Charge
Gate-Drain Charge
Gate Charge Characteristics
-
Fundamentally, the gate charge versus gate-to-source voltage curves are used to determine the amount of charge,
defined as Qg, required to bring Ciss from zero volts to 10 V. Typically, the maximum rating is specified at an 10 equal
to the device's continuous rating at 25°C and at a supply voltage of 80% of maximum rated VOS. Gate charge is essentially
independent of load current, but it does vary with supply voltage.
In addition to typical and maximum values of Q~, the data sheets also specify typical values of Qgd and QBs , Qgd is
the charge required by Crss (Cgd) during the fall 0 VOS. This occurs during the plateau region of Figure 3-9. gs refers
to the total charge required by Ciss during the two intervals characterized by ramping up of VGS before and after the
plateau. Ouring the first interval most of this charge flows into C!)S but during the second interval Crss takes on the
majority of the charge. Hence, the term uQgs" is somewhat of a misnomer.
A substantial amount of other data may e extracted from the curve. Estimation of the required average gate current
for a given switching speed, energy transferred to the gate, and magnitude of the input capacitance are some of its other
uses.
16
~
0
2~
14
MTP4N45
12 f--- TJ ~ 25"C
10 ~ 4A
~ 10
~
0
>
~
::::>
~V
0
'"w
<
'".;,
>'"
VX
0
..&~
i' 360 V
"225 V
VOS=150V
/
i.
II
10
20
30
40
ag, TOTAL GATE CHARGE (nCI
FIGURE 3-9 -
Q g TOTAL GATE CHARGE (nC)
MOTOROLA TMOS POWER MOSFET DATA
1-3-5
50
SOURCE-DRAIN DIODE CHARACTERISTICS'
Characteristic
Forward On-Voltage
Symbol
Typ
Unit
VSO
1.1
Vdc
trr
420
ns
IS = 4.0A
VGS = 0
Reverse Recovery Time
Forward tum-on time is primarily limited by parasitic package and lead inductance.
·Pulse Test: Pulse Width" 300 ,.s, Duty Cycle" 2%.
•
• An integral feature of all power
MOSFET structures.
• Reverse recovery times are comparable
with those of fast recovery rectifiers.
• Rated current equal to that of the MOSFET
• May be used as a commutator in complementary
totem-pole or H-bridge configurations with
inductive loads, or in a "Synchronous
Rectifier" mode.
+ VOD
THE POWER MOSFET
SOURCE-DRAIN DIODE
L
EQUIVALENT TEST CIRCUIT
L
o
trr
ton
-IRM
OUT WAVEFORM
TOTEM-POLE
N-CHANNEL
COMPLEMENTARY
P-CHANNELlNCHANNEL
DURING TURN-OFF OF aI, D2 PROTECTS
01; LIKEWISE
DURING TURN-OFF OF 02, Dl PROTECTS
02
TMOS power MOSFET intrinsic diodes also have forward recovery times, meaning that they do not instantaneously
conduct when they are forward biased. However, since those times are 50 brief, typically less than 10 ns, their effect on
circuit operation can almost always be ignored. Package, lead and wiring inductance are often at least as great a factor
in limiting current rise time.
FIGURE 3-10 -
SOURCE-Ta-DRAIN DIODE TEST CIRCUIT AND WAVEFORM
MOTOROLATMOS POWER MOSFET DATA
1-3-6
, - - - - - - - - - - - - - . . . SAFE OPERATING AREA INFORMATION
lD_~.
12r--1---r--+---r--1---r--+---r--1--~
~
~ lDr-~~-+---t---r--~--+_~r_-+--_+--~
~
~
I--
z
~
=>
I--
~
cc
~
.0.5 - - - -
~
~ 6 1--1- TJ '" 150'C -+--f---r--i---j----;----t
~~~~b~~,I~IT
~
I--r- THERMAL LIMIT H-+-'~~--l"':>"d--+-H-+-If+-H
Eo .0.2 I
I
I
Eo
I I I
t::jE:~~JM~T~M~IM~T~P4~N~45~~~~~~~~~~
MTMIMTP4N50
TC - 25'C
VGS = 2.0 V. SINGLE PULSE
.0.1
100
D
VDS. DRAIN-TO-SOURCE VOLTAGE IVOLTSI
W
W
~
~
.0 ~
.0
1.0.0.0
~
~
D
~
~
VDS. DRAIN-TO-SOURCE VOLTAGE IVOLTSI
FIGURE 3-11 - MAXIMUM RATED FORWARD BIASED
SAFE OPERATING AREA
FIGURE 3-12 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
THERMAL RESPONSE
~
u
D
.0.5
.0.5
-
~z
>;! .0.3
1=",
~~
.0.2
.0.2
w~
0«
~::;;
.0.1
~~
«",
~ 0.05
!>Icc
.om
~
Plpkl
V
.0..01
.0..02
~~I
--
I-
f.--
' 2DUTY CYCLE. D = '1112
.0..01.
-Isnmr
.0 ..05
.0.1
----
I
.0.2
ROJCIII = rill ROJC
ROJC = 1.67'CiW MAX
DCURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ nME AT tl
TJlpkl - TC = Plpkl R8JCIII
r~
.0 ..02
:=
Oz
:; ~ 0.03 I-I--'
-E ~ .0..02
I--
....
----=:::
.0.1
.0..05
.0.5
11111
1.0
2.0
111111
1.0.0
5.0
200
~
100.0
t. TIMElmsl
FIGURE 3-13 - MTM4N45IMTM4N50
Guaranteed Safe Operating Area
FBSOA
SSOA
The FBSOA curves define the maximum drain-Io-source
voltage and drain currenl thai a device can safely handle
when il is forward biased. or when it is on. or being turned
on. Because these curves include the limitations of simultaneous high voltage and high current. up to the rating of the
device. they are especially useful to designers of linear systems. The curves are based on a case temperature of 25'C
and a maximum junction temperature of 150'C. Limitations
for repetitive pulses at various case temperatures can be
determined by using the thermal response curves. Motorola
Application Nole, AN569. "Transient Thermal ResistanceGeneral Data and Its Use" provides detailed instructions.
The switching safe operating area in Figure 3-12 is the
boundary that the load line may traverse without incurring
damage to the device. The fundamental limits are the maximum rated peak drain current 10M, the minimum drain to
source breakdown voltage V(BR)DSS and the maximum
rated junction temperature. The boundaries are applicable
for both turn-on and turn-off of the devices for rise and fall
times of less than one microsecond.
MOTOROLA TMOS POWER MOSFET DATA
1-3-7
•
•
MOTOROLA TMOS POWER MOSFET DATA
1-3-8
Chapter 4: Design Considerations in Using Power MOSFETs
Protecting the Power MOSFET
50
Safe Operating Areas
-:-tIO~s
To provide the designer with Safe Operating Area information for the various modes of operation the TMOS
transistor may encounter, two different Safe Operating
Areas are defined on the TMOS data sheets: the Forward
Biased Safe Operating Area, or FBSOA (often referred to
as simply SOA) , and the Switching SOA or SSOA. The
SSOA curves of MOSFETs describe the voltage and current limitations during turn-on and turn-off and are normally used in the same manner as the RBSOA curves of
bipolar transistors.
I- -1-
f-
Z
r~
r.
rj-
!=
line B
line C
line 0
-
20 V
I-- Single Pulse
o lI--TC= 25°C
10
FBSOA:
An FBSOA curve defines the maximum drain voltage
and currents that a device can safely handle when forward
biased, or while it is on or being turned on. Of the four
limits dictated by the boundaries 0, the FBSOA curve, the
most unforgiving is the maximum drain-source voltage
rating which is indicated by boundary A in Figure 4-1. If
this rating is exceeded, even momentarily, the device can
be damaged permanently. Thus, precautions should be
taken if there may be transients in the drain supply voltage.
Maximum allowable drain current is time or pulse-width
dependent and defines the second boundary of the
FBSOA curve, represented by line O. The limit is determined by the bonding wire diameter, the size of the source
bonding pad, device characteristics and thermal resistance. Even though MOSFETs show rugged overcurrent
capabilities, devices should not conduct more than their
rated drain current for a given pulse duration. This includes transient currents such as the high in-rush current
drawn by a cold incandescent lamp or the reverse recovery current required by a diode.
The third boundary, line B is fixed by the drain-tosource on-resistance and limits the current at low drainsource voltages. Simply a manifestation of Ohm's Law,
the limitation states that with a given on-resistance, current is limited by the applied voltage. The boundary does
not describe a linear relationship, however, because the
on-resistance increases gradually with increasing current.
The fourth limit, shown as Line C in Figure 4-1, is set
by the package thermal limit. This power limited portion
of the FBSOA curve is generated from the device thermal
response curve, maximum allowable junction temperature
and maximum RruC rating. Operation inside this curve
insures that the maximum junction temperature does not
exceed the 150°C maximum rating.
Since the transient thermal resistance decreases dramatically for shorter pulse durations, the peak power handling capability increases accordingly. For example,
Figure 4-2 shows that at 100 JLs the normalized single
pulse transient resistance of the MTM8N40 is 0.033. Multiplication by RruC (0.033 x 0.83°CIW) results in the effective thermal impedance for a single 100 JLS pulse. From
the definition of thermal resistance ( ROJC = TJ-TC)
~s
~ms
10 ms
de
-
1= VGS
100
.......
~
MTH8N35
M,TM/MTH8N40 =
10
100
"" Line
1~lr
400
Vas. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
FIGURE 4-1 - MAXIMUM RATED FORWARD BIAS
SAFE OPERATING AREA OF THE MTMBN40
TJ of 150°C and a TC of 25°C is easily determined. In this
150 - 25°C
.
case, (0.033 x 0.83°CIW =
Po
), Po IS 4564 W.
Therefore, at a VOS of 200 V, the MTM8N40 can conduct
about 23 A during a 100 JLS pulse without exceeding the
.
TJ(max) rating of 150°C.
Normally the portion of the FBSOA curves that IS determined by the package thermal limit is only of interest
to designers who foresee a condition of simultaneous high
voltage and high current for periods greater than 10 JLs.
This situation can occur in linear applications or in switching applications that experience a fault condition such as
a shorted load. For those applications the information contained in Figure 4-1 is incomplete since the data is based
on single pulse testing at a case temperature of 25°C. For
multiple pulses and case temperatures other than 25°C,
the maximum allowable power dissipation can be computed as shown in AN569, "Transient Thermal Resistance
General Oata And Its Use."
To a large extent, thermal limitations determine the SOA
boundaries for MOSFETs used in linear applications. The
maximum allowable junction temperature TJ(max) also
affects the pulsed current ratings applicable when the
MOSFET is used as a switch. With respect to current
ratings, MOSFETs are more like rectif.iers than bipol~r
transistors in that their peak current ratings are not gain
limited, but thermally limited. Since rOS(on), on-state
power dissipation, switching losses, pulse width, duty
cycle and junction to ambient thermal impedance all influence TJ, they also affect the maximum allowable pulsed
drain current.
In switching applications the total power dissipation is
comprised of switching losses and on-state losses. At low
frequencies, the MOSFETs switching losses are small
enough to ignore. However, as frequency increases t~e
losses eventually become significant and force an Increase in T J. The break pOint between what is considered
low and high frequencies depends on the gate drive
impedance. With a low impedance gate-drive, switching
losses are small below 40 to 50 kHz.
---po-
the magnitude of the power pulse that coincides with a
MOTOROLA TMOS POWER MOSFET DATA
1-4-1
~
1.0
0.7
0.5
:-=
0.3
.
l3
0
~~
o. 1
0.0 7
~ ~O.05
~
I--::
;.". -~
-101
~
:1;1>1
-
0.2
~6 0.2
ffi ~
0.5
=
0.05
-
0.02
0.03
0.0
.".
0.0
:~
0.01
002
-
P(pkl
~~~
......
s:n u\,
01
02
0.5
1.0
I Illl
I 1
10
20
5.0
t. TIMElm'1
20
'0' Powe,
Pulse Train Shown
Read Time at '1
TJ(pkl - TC = P(pkl ReJclt1
Duty Cycle. D= '1/'2
r"I'j
0.05
R8JC(11 = ,(II f1eJC
R8JC = 0.83°C/W Max
o Curve. Apply
tJUl
L 1 LllLll
50
100
1 J
L LU
200
500
1.0k
FIGURE 4-2 - THERMAL RESPONSE CURVE OF THE MTM8N40
•
Since the magnitude of the MOSFET capacitances and,
therefore, switching speeds are nearly constant as TJ
varies, power MOSFET switching losses are nearly temperature invarient. Without the additional complexity of
temperature dependence, losses during the relatively high
dissipation turn-on and turn-off intervals are easily modeled and estimated. These techniques are also shown in
Motorola Application Note AN569.
Because on-state losses are often the bulK of the total
power dissipation, they greatly affect the MOSFET's maximum allowable pulsed current capability. The computation of these losses is somewhat involved due to the variation of rOS(on) with temperature and drain current. After
computing the heating component of the drain current
(RMS value), an iterative technique is used to determine
. the on-state power dissipation. The following example
illustrates how on-state losses and junction temperature
can be determined.
Assume the drain current waveform of an MTMsN40 is
trapezoidal with the current riSing from S.O A to 16 A in
25 p..S. The duty cycle is 50% and the frequency is 20
kHz. Heat sinking will be provided to keep the case temperature at sO°C. From Figure 4-2, the normalized transient thermal impedance for a 25 p..S pulse and 50% duty
cycle is 0.5, yielding an effective thermal impedance of
0.415°CIW. [r(t) x ROJC = 0.5 x 0.s3°CIW).
Before proceeding, the on-resistance and the RMS
value of the 10 waveform must be determined. Since
rOS(on) is temperature dependent, the junction temperature must be roughly estimated. A TJ of 110°C seems
appropriate in this case. From Figure 4-3, rOS(on) at
110°C is 1.02 n.
u; 1.0
:;
'"
~
u
~
~
TJ = 100°C
0.8
0.6
~
r---
25°C
~
r---
~55OC
~ 0.4
z
~
Q
0.2
V
- ---
./
/"
....-
VGS= 10V
~
~ 0
I--- ~
o
4.0
8.0
12
10. DRAIN CURRENT (AMPSI
20
16
FIGURE 4-3 - ON-RESISTANCE versus DRAIN
CURRENT FOR THE MTM8N40
o =~
IRMS =
oJa +a:+b2
2
o=~
IRMS =
This value of rOS(on) is derived from a typical curve
and does not represent a worst case value. To obtain a
worst case estimate, the ratio between the maximum rated
rOS(on) and the typical rOS(on) under the same operating
conditions can be used as a multiplier. In this situation,
an rOS(on) maximum of 0.55 ohms is specified at an 10
of 4.0 A and a TC of 25°C. At these same conditions,
rOS(on) is typically at 0.45 ohms (Figure 4-3). Assuming
the ratio between typical and worst case values remains
a~
FIGURE 4-4 - RMS VALUES OF SOME COMMON
CURRENT WAFEFORMS
MOTOROLA TMOS POWER MOSFET OATA
1-4-2
fairly constant, the multiplier is 1.22, (ros(on) ~~ =
rOS(on)
-'- . Therefore, the worst case rOS(on) at 12 A, 110°C
50
o 55)
40
0.45
'"
0-
~ 30
is approximately 1.22 x 1.02 ohms, or 1.24 ohms.
IRMS
= 0
/a2
'1/
+
ab
3
_ J8 2+
- 0.5
+
f--oo
MTM/MTH8N40
~
MTM/MTH7N45
~ 20
;2
b2
MTM/MTH7N50
c
.!? 10
8· 16
3
MTH8N35 -
!;;;
From the trapezoid waveform in Figure 4-4:
+
162
o
o
= 6.11 A
and Po = 12 RMS rOS(on)
= (6.11)2 1.24
TJ'; 150°C
400
100
200
300
Vos. DRAIN·TO·SOURCE VOLTAGE (VOLTSI
500
FIGURE 4-5 - MAXIMUM RATED SWITCHING
SAFE OPERATING ARE OF THE MTM8N40
= 46.3 W
If switching losses are significant, they should be
included at this step. Proceeding with the computation
of TJ,
IlTJC = Po RruC
= (46.3) (0.415) = 19.2°C
TJ = TC + IlTJC
= 80 + 19.2°C = 99.2°C
stroy the device if it begins to avalanche. Transients on
the drain supply voltage can also destroy the power
MOSFET.
Fortunately, if there is any danger of these destructive
transients, the solutions to the problems are fairly Simple.
Figure 4-6 illustrates a FET switching an inductive load
in a circuit which provides no protection from excessive
flyback voltages. The accompanying waveform depicts
the turn-off voltage transient due to the load and the parasitic lead and wiring inductance. The MTM20N10 experiences the unrecommended avalance condition for
about 300 ns at its breakdown voltage of 122 volts.
One of the simplest methods of protecting devices from
flyback voltages is to place a clamping diode across the
inductive load. Using this method, the diode will clamp
most, but not all, of the voltage transient. VOS will still
overshoot VDO by the sum of the effects of the forward
recovery characteristic of the diode, the diode lead inductance and the parasitic series inductances as shown
in Figure 4-7.
then the calculated TJ of 99.2°C replaces the original
110°C estimate and rOS(on)' Po and TJ are recomputed.
The initial guess was close, and 97.3°C is the final solution. Therefore the transistor is operating within its thermal
limitations and its current handling capabilities.
SSOA:
Switching Safe Operating Area defines the MOSFETs
voltage and current limitations during switching transitions. Although an SSOA curve also outlines turn-on
boundaries, it is normally used as a turn-off SOA. As such,
it is the MOSFET equivalent of the Reverse Biased SOA
(RBSOA) of bipolars.
Like RBSOA ratings, turn-off SOA curves are generated
by observing device performance as it switches a clamped
inductive load. An inductive load is used because it causes
the greatest turn-off stress, but it must be clamped so as
not to avalanche the transistor with an uncontrolled drainsource "flyback voltage." Switching speeds, which directly
determine crossover times and switching losses, also in'
fluence the turn-off SOA.
As shown in Figure 4-5, the SSOA curve of the
MOSFET is bounded by its maximum pulsed drain current, 10M, and the maximum drain-source voltage, VOSS,
as long as switching times are less than 1.0 JJ-s. If
MOSFETs are operated within their 10M, VOSS and
TJ(maxl ratings, their SSOA curves guarantee that a secondary breakdown derating is unnecessary.
in
!:i
~
+V
>'"
~~
0
ul
"~
§/
w
u
::>
0
'"
"I
z
;;:
'"
0
0
FIGURE 4-6 - VDS TRANSIENT DUE TO UNCLAMPED
INDUCTIVE LOAD
Drain-Source Overvoltage Protection
The most common cause of failure in a power MOSFET
is due to an excursion across an SOA boundary. A good
portion of these failures are a result of exceeding the
maximum rated drain-source voltage, V(BR)OSS. Drain
voltage transients caused by switching high currents
through load or stray inductances can force VOS to exceed V(BR)OSS and may contain enough energy to de-
If the series resistance of the load is small compared
to its inductance, a simple diode clamp may allow current
to circulate through the load-diode loop for a significant
amount of time after the MOSFET is turned off. When this
lingering current is unacceptable, a resistor can be inserted in series with the diode at the expense of increasing
the peak flyback voltage seen at the drain.
MOTOROLA TMOS POWER MOSFET DATA
1-4-3
that the RC clamp network must absorb. From the power
and the desired clamp voltage, the resistance can be
sized. Finally, the magnitude of the capacitance may be
determined by relating the RC time constant to the period
of the waveform.
As an example, a similar circuit has the following characteristics:
'"
;;;
!:i
~
>"'
0
w
"~
g
w
u
a:
"0
"'z
L
= 10 /LH
= 3.0 A (load current just before turn-off
~
0
= 25 kHz
FIGURE 4-7 - VDS TRANSIENT WITH CLAMPING DIODE
•
Vc
= 60
V (desired clamp voltage)
The power to be absorbed by the clamp network is:
Protecting the drain-source from voltage transients with
a zener diode, which is a wide band device, is another
simple and effective solution. Except for the effects of the
lead and wiring inductances and the virtually negligible
time required to avalanche, the zener will clip the voltage
transient at its breakdown voltage. A transient with a slow
dVDS/dt will be clipped completely while a transient with
a rapid dv/dt might momentarily exceed the zener breakdown voltage.· These effects are shown in Figure 4-8.
Even though it is a very simple remedy, the zener diode
is one of the most effective means of transient suppression. Obviously, the power rating of the zener should be
scaled so that the clipped energy is safely dissipated.
= 1/2U2
P
xf = 1.125W
The component values can be determined:
V~
= R = 3.2K "'" 3.3K
P
Let T = RC = 5.0 + f = 200 /LS
C = 0.061 /LF "'" 0.05 /LF
While this is a common and efficient cricuit, the switching speeds of MOSFETs may produce transients that are
too rapid to be attentuated by this method. If the flyback
voltage reaches its peak during the first 50 ns, the effectiveness of the circuit will be undermined due to the forward recovery characteristic of the clamp diode and any
stray circuit inductance. It may be prudent in these cases
to include a zener with a breakdown voltage slightly higher
than the clamp voltage. When placed directly across the
drain and source terminals, the lead lengths are short
enough and the zener is fast enough to catch most transients. Since the zener's only purpose is to Clip the initial
flyback peak and not to absorb the entire energy stored
in the inductor, the zener power rating can be smaller than
that needed when one is used as the sole clamping element.
A fourth way to protect power MOSFETs from large
drain-source voltage transients is to use an RC snubber
network like that of Figure 4-10. Although it effectively
reduces the peak drain voltage, the snubber network is
not as efficient as a true clamping scheme. Whereas a
clamping network only dissipates energy during the tranSient, the RC snubber also absorbs energy during portions
of the switching cycle that are not overstressing the transistor. This configuration also slows turn-on due to the
additional drain-source capacitance that must be discharged.
6.0 #ls/d,v
FIGURE 4-8 - Vos TRANSIENT WITH ZENER CLAMP
Figure 4-9 shows an RC clamp network that suppresses
flyback voltages greater than the potential across the capacitor. Sized to sustain a nearly constant voltage during
the entire switch cycle, the capacitor absorbs energy only
during transients and dumps that energy into the resistance during the remaining portion of the cycle. Component values may be computed by considering the power
_ 20V/div
"'
!:i
~
:§
u1
";:$
~w
Clamp Voltage, Vc
V DS
~
~z
~
o
10,us/d,v
500 ns/dlv
FIGURE 4-9 - VDS TRANSIENT AND RC CLAMP VOLTAGE WITH RC CLAMP NETWORK
MOTOROLA TMOS POWER MOSFET DATA
1-4-4
No matter which scheme is used, very rapid inductive
turn-off can cause transients during the first tens of nanoseconds that may be overlooked unless a wideband
oscilloscope (B.W. ;;;. 200 MHz) is used to observe the
VOS waveform.
FIGURE 4-10 -
power MOSFETs recently have increased rapidly and,
consequently, their maximum di/dt capabilities have also
risen. The MTM60N06, with its pulsed current rating of
300 A, falls into the category of such a device. The very
large di/dt capabilities that accompany these current ratings can produce significant VOS stress in addition to that
observed at the drain-source terminals.
To assure that the peak VOS at the chip does not exceed the maximum VOSS rating of the device, the following equation can be used:
VOS(max) = V(BR)OSS - L(di/dt)
where VOS(max) is the maximum allowable voltage appearing across the drain-source terminals, V(BR)OSS is
the maximum device rating, L is the parasitic source inductance and di/dt is the rate of change in 10 coincident
with VOS(max)'
Voltages appearing across the package source inductance also affect the magnitude of the gate-source voltage
at the chip and are of such polarity that they slow both
the turn-on and turn-off transitions. If large currents are
being switched, the parasitic package inductance is large
enough to be the factor that limits the MOSFET's switching
speeds.
Except for circuits that produce very large di/dt's, the
proceeding discussion of package inductance is of academic interest only. However, wiring inductance is often
much larger than the package inductance and its effects
are proportionately greater. Therefore, the above considerations may become very practical problems in applications in which the dildt's are not extreme. The quality
of the circuit layout dictates the degree of concern.
VDS TRANSIENT WITH RC SNUBBER
Package and Lead Inductance Considerations
The drain and source parasitic package inductance can
influence the magnitude of VOS during rapid switching of
very large currents. In Figure 4-11, the drain and source
package inductance has been combined and placed in
the source because that wirebond and lead length accounts for the bulk of the inductance. The magnitudes of
LS in the TO-204, (TO-3) and the TO-220 packages are
around 12 and 8 nH, which are large enough to produce
appreciable voltage during a very rapid rate of change in
drain current. The polarity of the induced voltage is such
that the drain-source voltage appearing at the chip is
greater than that appearing at the device terminals.
As an example, assume that an MTP25N06 is turned
off in 50 ns after conducting 50 A. A di/dt of this magnitude
will produce about 8.0 volts across the parasitic package
inductance (v = L di/dt = 8.0 nH 50 Al50 ns). If the drainsource voltage at the terminals is 50 V, then VOS at the
die is 58 volts.
Avalanche and dv/dt Limitations of Power MOSFETs
Until recently a MOSFET's maximum drain-to-source
voltage specification prohibited even instantaneous
excursions beyond that voltage, since the first power
MOSFETs were never intended to be operated in avalanche. As is still the case with most bipolar transistors,
capability was simply not specified. Some devices happened to be quite rugged, while others were not. Now it
is known that a power MOSFET can be constructed to
sustain substantial currents in avalanche at elevated junction temperatures, so newly designed MOSFETs are
replacing the original devices. "Ruggedized" is the term
being used to refer to devices that carry some form of
rating to define avalanche capability.
The MOSFET's ability to withstand rapid changes in
drain-to-source voltage, especially during reverse recovery of the MOSFET's intrinsic diode, is another issue that
has received much attention lately. In this case the first
devices were very rugged except for the case of diode
recovery. Again the latest devices show performance
improvements and carry ratings to inform designers of
their new strength.
Because of the interest in avalanche and dv/dt issues
and their importance, a discussion of these topics is provided in Chapter 5, "Avalanche and dv/dt Limitations of
the Power MOSFET."
""'"T~r
Gate
Terminal
~
.
VDsatdie =
VDS at terminals + VL
LS = 8.0 nH
+
Source Terminal
FIGURE 4-11 - VERY RAPID TURN-OFF INCREASES
DRAIN-SOURCE VOLTAGE STRESS
Although all power MOSFETs experience some inter. nally generated voltages during rapid switching, peak
di/dt's are usually not extreme and the associated voltages are generally small. However, the current ratings of
MOTOROLA TMO~ POWER MOSFET OATA
1-4-5
I
I
I
I
~
I
Protecting the Gate
•
The gate of the MOSFET, which is electrically isolated
from the rest of the die by a very thin layer of Si02, may
be damaged if the power MOSFET is handled or installed
improperly. Exceeding the 20 V maximum gate-to-source
voltage rating, VGS(max), can rupture the gate insulation
and destroy the FET. TMOS FETs are not nearly as susceptible as CMOS devices to damage due to static discharge because the input capaCitances of power
MOSFETs are much larger and absorb more energy before being charged to the gate breakdown voltage. However, once breakdown begins, there is enough energy
stored in the gate-source capacitance to ensure the complete perforation of the gate oxide. To avoid the possibility
of device failure caused by static discharge, precautions
similar to those taken with small-signal MOSFET and
CMOS devices apply to power MOSFETs.
When shipping, the devices should be transported only
in antistatic bags or conductive foam. Upon removal from
the packaging, careful handling procedures should be adhered to. Those handling the devices should wear grounding straps and devices not in the antistatic packaging
should be kept in metal tote bins. MOSFETs should be
handled by the case and not by the leads, and when
testing the device, all leads should make good electrical
contact before voltage is applied. As a final note, when
placing the FET into the system it is designed for, soldering should be done with a grounded iron.
The gate of the power MOSFET could still be in danger
after the device is placed in the intended circuit. If the
gate may see voltage transients which exceed VGS(max),
the circuit designer should place a 20 V zener across the
gate and source terminals-to clamp any potentially destructive spikes. Using a resistor to keep the gate-tosource impedance low also helps damp transients and
serves another important function. Voltage transients on
the drain can be coupled to the gate through the parasitic
gate-drain capacitance. If the gate-to-source impedance
and the rate of voltage change on the drain are both high,
then the signal coupled to the gate may be large enough
to exceed the gate-threshold voltage and turn the device
on.
MOTOROLA TMOS POWER MOSFET DATA
1-4-6
Chapter 5: Avalanche and dv/dt
Limitations of the Power
MOSFET
The power MOSFET's ability to withstand voltage and
current transients inside and outside published safe operating areas is often of concern to design engineers. Since
anticipating every possible fault condition that can occur
in the field is very difficult, the use of a device that has
some tolerance to transients is highly desirable.
By nature the power MOSFET is resistant to failure in
certain modes. Its ability to withstand overcurrent stresses
is a good example of one of its strengths. However, ruggedness in other modes is not a given, and device design
and processing must target those types of failures if a
MOSFET is to be robust in those modes, too.
Motorola's development of the E-FET, a "ruggedized"
device sometimes referred to as TMOS IV, is a significant
step toward extending the MOSFET's ruggedness to
include several of the most common fault induced
stresses. Designed-in ruggedness, combined with the
MOSFET's ability to withstand forward bias stress, make
the E-FET a very fault tolerant device in all major areas
of concern, including what has been called the "commutating dv/dt" mode. The issues surrounding these significant modes of stress are discussed in detail below.
The recent development of the E-FET has made available MOSFETs with the ability to survive both types of
overvoltage transients. These new devices are sufficiently
rugged to carry ratings that guarantee an avalanche current capability for the two types of overvoltage transients
discussed above.
An energy rating alone is a poor indication of a device's
ability to survive overvoltage transients. Manufacturers
can easily fabricate high energy values by carefully choosing test conditions that allow dissipation of energy over a
long pulse width. An extreme example is the 12 A, 60 V
MTP3055E that can dissipate 75 joules if allowed to conduct 1 A in avalanche for 1 second. However, one of these
devices is likely to fail with very little energy dissipation if
it is forced to conduct more than 40 A in avalanche.
The bottom line is that the propensity for failure is almost
exclusively a function of two parameters: peak current in
avalanche and peak (not average) junction temperature.
Except for raising the average junction temperature thereby enhancing the chance of hotspot failure - the
total energy dissipated has only secondary effects.
Avalanche Test Methods and Ratings
The Power MOSFET in
Drain-to-Source Avalanche
Understanding the causes of overvoltage transients
and the conditions that determine the propensity for failure
provide a foundation for defining the most appropriate
avalanche test methods. There are two viable tests: each
offers its own benefits. The most common test circuit and
its associated current and voltage waveforms are shown
in Figures 1 and 2. Testing in this circuit is appropriately
referred to as Unclamped Inductive Switching, or UIS, as
there is no diode clamp across the coil to limit the flyback
voltage appearing at the drain.
Although there is controversy surrounding some of the
test conditions (such as coil size, initial and final junction
temperatures and peak current), circuit operation is very
straightforward. The gate drive is turned on and current
in the coil is allowed to ramp up to the desired test current,
which is primarily set by the coil size, the supply voltage
and the on time of the gate drive (AI = (VOO/L)At). When
the load current reaches the desired value, the MOSFET
is abruptly turned off. Since the load current cannot
change instantaneously, the inductive energy drives the
drain-to-source voltage to V(BR)OSS; the MOSFET then
dissipates the stored energy in avalanche.
In this circuit the total energy diSSipated by the MOSFET
may not be equal to that stored in the coil. During avalanche, additional energy is transferred from the VOO supply to the MOSFET. For low test currents «10 A) the
total energy diSSipated is approximately equal to 1/2U2
times the multiplier, V(BR)OSS/(V(BR)OSS-VOO), which
accounts for the additional transferred energy. For higher
test currents the energy dissipated in the coil's resistance
may also become Significant, subtracting from what is
diSSipated in the device. In such cases, the exact amount
of energy transferred to the test unit is somewhat difficult
The MOSFET's unique capability of high speed switching can lead to stresses that are not encountered with
slower devices. Often gate drive circuits are designed for
very fast switching speeds to lower switching times and
increase circuit efficiency. These speeds may be so fast
that the inductive kick occurring at turn off produces an
extremely rapid rise in the drain-to-source voltage - perhaps so rapid that parasitic circuit elements and turn-on
times undermine a protection clamp's ability to respond
in time to protect the MOSFET. Such parasitics that diminish response times include the inductance in the wiring,
leads, and packages. Forward recovery time of protection
diodes may also delay response time.
Voltage transients of this type are usually brief, lasting
only until the voltage clamp or snubber reacts. Nevertheless, for a short time the MOSFET is forced to conduct
what may be a high avalanche current. Although the total
energy that the device sees in breakdown is fairly small,
failures may occur since ruggedness in avalanche is a
strong function of the peak avalanche current. At high
switching speeds such brief transients are a common
source of overvoltage spikes.
Another cause of overvoltage transients is voltage spiking on the drain supply voltage. When this occurs, the
peak magnitude of the associated avalanche current is
difficult to predict since it depends on the nature of the
transient. Pulse duration and energy may vary widely;
consequently, the MOSFET's ability to survive high avalanche currents lasting for extended pulse widths is
important.
MOTOROLA TMOS POWER MOSFET DATA
1-5-1
to calculate, but it can be accurately estimated by integrating the product of the drain-to-source voltage waveform and drain current waveform over the interval of
avalanche.
VOO > V(BR)OSS of O J
OUT
L
Driver
VOS
vOO
Pulsed
Gate
Source
+12V
InputLru
100.JL.,JL
FIGURE 5-1 - TYPICAL TEST CIRCUIT FOR UNCLAMPED
INDUCTIVE SWITCHING
"::"
10
Set
VOSoJL..JL V(BR)OSS
FIGURE 5-3 - ALTERNATE ASC TEST CIRCUIT THAT FORCES A
CONSTANT CURRENT IN AVALANCHE
0-----1
I
~
o
:
:10
I
I
I
I
Stresses expected in the field should be used to guide
the setting of UIS test conditions. Test currents should be
equal to or greater than the continuous rating of the
device. Junction temperatures should be elevated, bound
only by the maximum rating.
There are two ways to achieve the elevated junction
temperature specified in a UIS rating. The first is simply
to externally heat the case of the device and the second
is to begin the test at room temperature and raise the
junction temperature by controlling the energy that the
device under test must dissipate. However, in avalanche
the many FET cells of the die may not share current
evenly. This may cause the peak junction temperature to
be much higher than the average. Consequently, forcing
an elevated junction temperature with self heating tends
to detect devices prone to hotspotting and is a more rigorous test.
t
I
I
I
I
"""""'-11 'os
I
L-voo
---"----FIGURE 5-2 - WAVEFORMS ASSOCIATED WITH TEST CIRCUIT
IN FIGURE 1
A second test circuit is shown in Figure 3, and again
circuit operation is simple. In this case, the MOSFET conducts a fixed, controllable current in avalanche. Since
there is no inductor in this circuit, results are independent
of the series resistance of the test coil and the magnitude
of VDD. An important feature of this method is that the
junction temperature continually increases during the time
of avalanche. Therefore, it is clear that the greatest stress
occurs at the end of the avalanche pulse when the avalanche current and junction temperature are at their maximum values.
Determining the moment of maximum stress during a
UIS test is difficult since peak current occurs at the beginning of the avalanche period when the junction temperature is at its minimum. Because the relationship between
failure, instantaneous current, degree of hotspotting, and
average junction temperature is not well understood, it is
difficult to pinpoint the moment of maximum stress or to
compare the stress in the UIS test to the stress in the
constant current test. Nevertheless, the UIS test is preferred over other methods since it is easy to implement
and already enjoys wide acceptance as a meaningful test
method.
Motorola's Avalanche Ratings
Motorola's E-series MOSFETs, which carry an "E" suffix, are designed to withstand the stress of drain-to-source
avalanche. For E-FETs introduced to date, UIS failure can
only be induced by either exceeding the device's pulsed
current rating or its maximum junction temperature rating.
With such a capability, an appropriate method of rating
avalanche energy becomes clear. Current in avalanche
is bounded by the pulsed current rating and energy dissipation is limited by thermal impedance and maximum
junction temperature. The following example shows how
the energy rating of the MTP3055E is calculated.
Consider the UIS rating of the MTP3055E specified at
its continuous current rating of 12 A, a duty cycle of 1%
and a case temperature of 25°C. For a typical V(BR)DSS
of 70 V, peak power in avalanche is 840 W. For a maximum junction temperature rating of 150°C and a case
MOTOROLA TMOS POWER MOSFET DATA
1-5-2
temperature of 25°C the allowable 6.TJC is 125°C.
CSOA. The converse is also true; devices with fairly broad
CSOA may fail immediately in avalanche because of inadequate die design or layout.
From PD (ZruC) = 6.TJC = 125°C, and
Zruc = RruC (r(t)),
the transient thermal impedance Zruc is calculated to be
O.149°CIW. From the thermal resistance rating of the
MTP3055E (ROJC = 3.12°CIW), r(t) is found to be equal
to 0.048, a dimensionless number. The next step is to use
the r(t) curve on the MTP3055E data sheet to determine
the pulse width corresponding to an r(t) of 0.048. That
pulse width, which is the time required to attain a 150°C
junction temperature, is 38 /Ls. The device rating, 32 mJ,
is obtained by computing the avalanche energy corresponding to 840 W dissipated for 38 /Ls. Similar computations yield ratings for other conditions such as elevated
case temperature, other drain currents or multiple pulses.
E-FETs introduced in the future are expected to have
ratings that can be determined in a similar manner.
The above calculations are based on a constant current
during avalanche, which is quite unlike the decaying avalanche current present in UIS testing. One way to determine coil size for UIS testing is to set the energy stored
in the unknown coil equal to the energy rating calculated
above. In this case the equation, W = 1/2 U 2 [V(BR)DSSI
V(BR)DSS - VDD], yields a inductance of 143 /LH for W
= 32 mJ, I = 12 A, V(BR)DSS = 70 V, and VDD = 25 V.
Although the energies are the same, the UIS test is slightly
less rigorous since the avalanche interval is roughly twice
as long as the time of avalanche during a constant current
test.
Four pOints regarding UIS testing are worth mentioning
here. First, a UIS rating per se does not guarantee the
ultimate goal, system reliability. Several other variables
such as average and peak junction temperature, the quality of system design and reliability of system components
also affect Mean Time Between Failure (MTBF). Millions
of bipolar and MOSFET circuits have very satisfactory
MTBFs even though the UIS capability of their power
devices is unspecified.
Second, UIS ratings apply to only a specific set of test
conditions and predictions of ruggedness outside those
conditions are speculative. For example, in some devices
elevated junction temperature or higher avalanche currents may substantially reduce energy handling capability.
Third, although excessive VDS is a common cause of
MOSFET failure, the incidence of overvoltage transients
should not be blamed for all power MOSFET failures. The
list of potential causes is long and investigations into the
reason for failure should not be limited to the one that is
currently receiving all the attention in the press. A similar
situation occurred in recent years when two other prevailing scapegoats - electrostatic discharge and dv/dtwere faulted for causing many more problems than they
probably deserved.
Finally, some have stated that a UIS test is a guarantee
of a device's ability to handle diode recovery stress, which
is discussed in detail below. Although a device that is
rugged with respect to avalanching usually has a broad
"Commutating Safe Operating Area," there are exceptions to this rule. In some devices, areas of the die other
than those associated with the parasitic bipolar affect
Drain-to-Source dv/dt Ratings
Static dv/dt
Power MOSFET performance is eventually limited by
extremely rapid changes in drain-to-source voltage.
These very high dv/dts can disturb proper circuit performance and even cause device failure in certain situations.
High dv/dts occur under three conditions, and each has
its own dv/dt threshold before problems arise. The first is
called "static dv/dt" and occurs when the device is off and
is intended to remain off. A voltage transient across the
drain and source can be coupled to the gate via the drainto-gate parasitic capacitance, Crss . Depending on the
magnitude of the gate-to-source impedance and the displacement current flowing into the gate node (i = C dvl
dt), VGS may rise above VGS(th), causing false turn-on.
Obviously, for this case dv/dt immunity depends to a
large extent on the gate-to-source impedance. This
dependence underscores the importance of proper gate
termination to promote good noise immunity and is one
of several reasons why operation of power MOSFETs with
the gate open circuited is a poor practice. With its gate
shorted to its source, all Motorola TMOS devices will withstand static dVDS/dts of greater than 30 V/ns, which is
well in excess of values encountered in typical
applications.
If the gate-to-source impedance is high and a voltage
transient occurs between drain and source, false turn-on
is more likely than device failure. Typically the transient
will be coupled to the gate and cause the MOSFET to
begin its turn-on. But as VGS rises and the MOSFET
begins to turn on, the rise in VDS falters and the dv/dt is
reduced. Thus, the phenomena is self-extinguishing and
generally is not destructive to any circuit element.
~urn-on of the MOSFET's parasitic bipolar transistor,
which is shown in Figure 4, is a potential route to device
destruction due to static dv/dt. If the base-emitter shorting
resistance is too large, displacement current flowing
through Ccb will lower the parasitic BJT's ability to sustain
collector-emitter voltage. Although such a scenario is
plausible, concerns about spurious BJT turn-on are generally unnecessary because the resistance of Rbe is kept
Parasitic
BJT
S
FIGURE 5-4 -
INHERENT IN EVERY POWER MOSFET IS A
PARASITIC BJT
MOTOROLA TMOS POWER MOSFET DATA
1-5-3
low. Additionally, displacement current is lower at high
voltage, when stand-off capability is most critical, because
the magnitude of Ccb falls with increasing VDS. So, the
dv/dt turn-on threshold cited above (greater than 30 V/ns)
also applies to the MOSFET's parasitic BJT.
has forward and reverse recovery times due to the storage
of minority carrier charge.
The second condition required to induce failure due to
commutating stress is that charge stored during reverse
recovery must be removed rapidly. Faster removal of
charge increases current densities and peak electric
fields. Since the turn-on speed of the transistor in the
opposite leg of the half bridge has the greatest effect on
the speed of commutation, it has a great influence on
device stress.
The third and final requirement is that the stored charge
must be extracted through a reapplied voltage of at least
30 to 50% of the device's maximum VDS rating. During
reverse recovery, as the diode is driven from forward to
reverse conduction, the rapidly rising drain voltage forces
the stored charge into the base of the parasitic bipolar
transistor. If the resulting emitter current is suffiCiently
high, it can, in conjunction with the re-applied drain voltage, induce the phenomenon of avalanche injection(3),
the cause of bipolar transistor "second breakdown."
The criteria above excludes most circuits as candidates
for diode recovery problems. All single transistor topologies are immune, and many multiple transistor topologies
are not subjected to commutation stress because the third
condition is not met. The following examples help define
which multiple transistor applications may develop problems. The first circuit is representative of the most commonly cited problem; the second is one in which commutating dv/dt is not normally a concern.
Consider the bidirectional DC motor speed controller
illustrated in Figure 5. The direction of rotation depends
upon which transistor receives the PWM signal at its gate;
varying the duty cycle provides speed control. When one
transistor is controlling motor speed, the oppOSite one is
inactive as a MOSFET, but its diode serves as a commutating rectifier. To reduce audible noise, designers
often operate their systems at frequencies greater than
20 kHz, so switching speeds are also high.
Reviewing the motor controller operation shows how
turn-on of the drive tranSistor, in this case 01, impresses
commutating dv/dt stress on 02's diode. A cycle begins
with the turn on of 01, which delivers current to the load.
01 then turns off and remains off for the rest of the cycle,
Dynamic dv/dt
The second mode in which dv/dt may be a concern
occurs when the MOSFET abruptly interrupts current in
an inductive load and an extremely rapidly-rising flyback
voltage is generated. Since the vast majority of loads
appear inductive at very high switching speeds, the device
experiences simultaneous stresses imposed by high drain
current, high VDS and displacement currents in the parasitic capacitances. Problems associated with this
"dynamic dv/dt" (so named because the device is being
switched off and is generating its own dv/dt) are evidenced
by device failure.
Unless extraordinary circuit layout techniques are
used (for example, hybrid circuits that minimize package
and lead inductance) maximum attainable dv/dts in the
dynamic mode range from 10 to 50 V/ns, depending on
the VOSS rating of the device. Among the various
MOSFET types, maximum turn-off speeds do not differ
widely and maximum attainable dv/dt is largely determined by the magnitude of the voltage that the drain
can be switched through. Consequently, a 1000 V MOSFET can generate a greater dynamic dv/dt than a 60 V
device, regardless of die size.
MOSFETs fabricated from all TMOS mask sets are
tested and have been found to be immune to self generated dv/dts during very rapid, clamped inductive turnoff. The test circuit used has an extremely tight RF layout,
and the switching speeds and dv/dts generated are
assumed to be practical limits.
Diode recovery "dv/dt"
The third instance in which rapidly rising drain-to-source
voltage has been thought to cause failure is during the
reverse recovery of the MOSFET's intrinsic diode. Those
that first studied this problem believed that dv/dt was the
prime cause of failure, but more recent work has shown
that dv/dt is only one of several factors that induce stress
in a source-drain diode during reverse recovery.!1 ,2) Consequently, in this text these stresses are not classified
strictly as dv/dt induced problems and the mode of stress
is referred to as "diode recovery stress." Unlike the dv/dt
modes discussed above, diode recovery stress is an occasional cause of system failure, but only when three specific
conditions are met.
The first prerequisite is that the MOSFET's diode must
conduct during the switching cycle. This is a necessary
but not a sufficient condition for device failure. Although
the MOSFET is virtually immune to dv/dt related failures,
its area of safe operation may decrease greatly during
reverse recovery of its diode. This dichotomy of capabilities is caused by a change in the means of conduction
from minority to majority current carrier.
When a MOSFET operates as a transistor, it is not
troubled by storage times or stored charge, since the
MOSFET is a majority carrier device. Its diode, on the
other hand, is a minority carrier device. Consequently, it
10V "
"
0 11
0-1 W
L- VGS1o----J
-v
FIGURE 5-5 - A PWM DC MOTOR CONTROLLER IMPRESSES
DIODE RECOVERY STRESS ON THE POWER TRANSISTORS
MOTOROLA TMOS POWER MOSFET DATA
1-5-4
and the inductive load draws current from the negative
supply through 02. When Q1 turns on at the beginning
of the next cycle, load current begins to be supplied by
Q1 instead of Q2's diode. But of greater importance, Q1
also supplies the reverse recovery charge for 02. Current
in 02 and Q2's drain-to-source voltage are shown in Figure 6. The time thought to be most stressful is also
depicted in the figure. Note that the three elements
required for diode recovery stress are present. The diode
of Q2 is experiencing the combined stress of reapplied
high voltage, presence of minority carriers, and rapid
extraction of charge, as evidenced by high di/dt and dv/
dt.
A second example, although it is in many ways similar
to the first, is not usually subjected to commutating diode
stress. It is the 1/2 bridge switch mode power supply,
whose basic configuration is shown in Figure 7. The crucial difference between this system and the motor control
circuit in Figure 5 is that the transistors are switching
alternatively. Under normal operation one transistor will
not turn on into a diode that is conducting current (which
is a second, abbreviated, way to state the criteria for
failure).
The idealized waveforms in Figure 8 show that output
rectifiers 01 and 02 are the primary freewheeling rectifiers
and the MOSFET diodes are essentially inactive. In reality,
however, each intrinsic diode must clamp the energy in
the transformer's leakage inductance when the oppOSite
transistor turns off. Generally this is an acceptable situation since energies involved are small, diode conduction
is brief, reapplied voltage is only a fraction of the device
rating, and reverse recovery is slowed by parasitic inductance. Consequently, in these circumstances the intrinsic
diode's commutation characteristics are usually not an
issue.
For applications satisfying the three requirements, there
are circuit solutions that deal with the problem if it occurs.
One such approach is shown in Figure 9. Obviously, the
intent of this circuit is to circumvent the MOSFET's limitations by not allowing the intrinsic diode to conduct and
thereby accumulate stored charge. However, the higher
parts count, additional cost and the voltage drop due to
the diode in series with the FET are undesirable. Another
solution is to limit dv/dt and voltage stress by using snubbers or by slowing the turn-on of the MOSFET in the
opposite leg of the 1/2 bridge.
The optimum solution is to use devices that are indifferent to recovery stress and that have safe operating
area curves that define and guarantee their capability.
With the introduction of the E-FET, Motorola is making
strides in both of these areas.
Time of greatest
stress
FIGURE 5-6 -
TYPICAL WAVEFORMS IN A PWM DC MOTOR
CONTROLLER
Output
Filter
rOutput
Rectifier
Line {
Input
10 2
L
-,
I
-1
I 1M ~'E~I
E:.r-31
IQ2
Input
Rectifier
FIGURE 5-7 - ALTHOUGH THE MOSFETs INTRINSIC DIODES
ACT AS FREEWHEELING RECTIFIERS IN THE 1/2 BRIDGE
SMPS, THEY GENERALLY DO NOT EXPERIENCE DIODE
RECOVERY STRESS
MOTORGLA TMOS POWER MOSFET DATA
1-5-5
DC
Output
•
o
n n
102
101
102
+v
J1,
J
A
Ultrafast
Rectifier
G~
r
S
A rfl
-=
•
s
-v
FIGURE 5-9 - ONE WAY TO AVOID REVERSE RECOVERY
STRESS IN THE MOSFET's INTRINSIC DIODE IS TO USE A
SCHOTTKY IN SERIES WITH THE MOSFET AND AN
ULTRAFAST RECTIFIER IN PARALLEL WITH THE MOSFET
AND THE SCHOTTKY
FIGURE 5-8 - TYPICAL WAVEFORMS OF A 1/2 BRIDGE
SWITCHED-MODE POWER SUPPLY
VOS(PK) > VR), and speed of commutation.
An example of a CSOA specification for a 15 A, 60 V
device is shown in Figure 11. This representation has the
advantage of using voltage and current axes, which are
common in other SOA curves. The third variable, di/dt
during the first part of reverse recovery, provides the measure of commutation speed.
Establishing the format shown in Figure 11 was a key
step toward quantifying the CSOA of many device families. With that information design engineers were able
to identify device features that give a broad CSOA, and
they are now implementing improvements in device
design and processing to enhance performance in the
com mutating mode. An example of such a device is the
recently introduced MTP3055E, a 12 A, 60 V replacement for the MTP3055A. Within its voltage, current, and
temperature ratings it is virtually indestructible during
rapid commutation, as shown by the square SOA of
Figure 12. The practical limit of reverse recovery di/dt
is bounded by the parasitic inductance of the test circuit
and the voltage that is applied to the diode to force
reverse recovery. For example, a supply voltage of 50
V in a circuit with 100 nH of stray inductance allows a
maximum dildt of 500 A/lLs (dildt = VOO/L). For a point
of "reference, total O-S package inductance of the TO220 is about 10 nH.
Proposed CSOA Specification
One of the tasks before the power electronics community is to eliminate commutation problems associated
with the MOSFET's intrinsic diode. The necessary steps
are: 1) develop devices that are more resistant to commutation stress, 2) define a test method to determine
device capability, and 3) provide ratings that detail the
safe operating area for the diode recovery mode. The
suggested rating is a Commutating Safe Operating Area,
or CSOA.
Motorola has already introduced the E-FET, which has
greater CSOA than its predecessors. But even with the
introduction of improved devices, users will remain cautious, unless the new capability is defined and guaranteed.
Lack of a universally accepted test method to standardize
CSOA specifications is now the major hindrance in this
effort. Although this is unfortunate, it is understandable
since specifying CSOA is fairly complex.
Figure 10 shows the relationships between the various
parameters that influence CSOA. Upon inspection choosing the most meaningful and convenient independent variables for testing is not obvious. Motorola's test results
indicate that the best approach is to use the three most
critical circuit dependent parameters. They are the forward
current in the diode just before commutation (lFM), reapplied voltage (or peak drain-to-source voltage when
MOTOROLA TMOS POWER MOSFET OATA
1-5-6
Device Dependent Parameters
Softness of
Beta of Parasitic
•
Temperature
Circuit Dependent Parameters
FIGURE 5-10 -
5
I
I
I
-~ildt ,!, 200 IAl,..
~
I
M
""-
\
I'-.
5
.........
.......
'"o
m
w
dild~ 4~OAl~S- I--
dildt = 100 AI,..
\ I\,
\
o
DURING COMMUTATION MANY PARAMETERS
AFFECT TOTAL DEVICE STRESS
~
~
-- W
o
o
60
REAPPLIED DRAIN-TO-SOURCE VOLTAGE (VOLTS)
m
w
~
~
W
60
REAPPLIED DRAIN-TO-SOURCE VOLTAGE (VOLTS)
FIGURE 5-11 - TYPICAL COM MUTATING SAFE OPERATING
AREA OF A 15 A, 60 V DEVICE NOT DESIGNED TO WITHSTAND
DIODE RECOVERY STRESSES
FIGURE 5-12 - COMMUTATING SAFE OPERATING AREA OF
THE MTP3055E IS MUCH BROADER THAN ITS PREDECESSORS
Other methods of specifying diode recovery stress have
been proposed. Using a single dv/dt value was the initial
favorite because of its simplicity and the suspicion that
failures are predominantly dv/dt induced. This idea was
discarded for several reasons. First, devices do not fail
solely due to dv/dt. In fact, when failures occur, they are
rarely noted during peak dv/dt but are found later during
maximum voltage stress and reduced dv/dt. Second, dvl
dt varies considerably during reverse recovery and selecting a single representative value is difficult and too simplistic. Third, dv/dt during commutation is a funciion of
device characteristics and circuit conditions and is not
something that the user can easily control, except with
snubbers. Fourth, displacement current caused by diode
recovery dv/dt is dwarfed by reverse recovery current,
making the rate of extraction of stored charge much more
important. Finally, some intrinsic diodes are much snappier than others (that is, the return of the diode current
from the reverse recovery peak to zero is very abrupt and
the rise in VDS to VR is very fast), and those diodes should
have to withstand the dv/dts that they inherently create.
MOTOROLA TMOS POWER MOSFET DATA
1-5-7
high gate drive impedance will consequently limit voltage
during reverse recovery.)
An important assumption that influenced circuit design
is that test results are independent of duty cycle, or that
failures are caused by peak instantaneous stresses and
not by multiple exposures to lower levels of stress. (This
is not to say, however, that propensity for failure is in~e
pendent of TJ.) If this assumption is true, and testing
indicates that it is, then circuit simplicity is vastly improved.
Also the layout can be much tighter and speeds much
faster if the Oevice Under Test, the OUT, requires very
little heatsinking.
The circuit's timing waveforms are also illustrated in
Figure 13, and circuit operation is as follows. Nor gates
A 1 and A2 are connected as an astable multivibrator to
generate a relatively low clock frequency of 10 to 1000
Hz. The clock's riSing edge triggers two monostable multivibrators formed by A3 and A4 and B1 and B2. The signal
from A3 and A4 ultimately controls the on-time of the
MJE13009, which acts as a constant current source to
deliver the forward current, IFM, to the MOSFET's intrinsic
diode. IFM is set by varying R1.
A High Voltage, High Speed
CSOA Test Fixture
Several CSOA test circuits have been built at Motorola.
One was targeted for high current, high speed testing; in
another the layout and associated slower switching
speeds were intended to be similar to those of a typical
motor control circuit; and a third was designed to handle
a wide range of voltages and currents. A fourth fixture,
the one described here, has as its strength the ability to
switch the OUT into voltages up to 450 V at very fast
commutation speeds.
This CSOA tester, whose schematic is shown in Figure
13, is designed to impart maximum OUT stress for. a given
IFM, VR and di/dt. Circuit features include a well blpassed
reapplied voltage to allow maximum dv/dt and vol~ge
stress, a drive transistor with a very low ROS(on) for high
IRM, and a complementary emitter follower gate driv~ for
Q2 to reduce dv/dt effects on the driver when the diode
under test snaps off. (The drive transistor must support
a dv/dt of equal magnitude and opposite polarity of the
dv/dt that appears at the OUT. A drive transistor with a
•
Voo
~
15to20V
VCC1
0.01 "F
ton of Diode Forward
Current-5 to 50 /LS
Frequency Control
10 to 1000 Hz
Va
~~----~:~
V1o-.-l Clock
~
~--~f~
....
I -----fff-f_ _........
On time of
+MJElaOO9
ff
==------------~:·~r---.L.J
Va O~-~ ........ Oelay of N-Channel turn on
V4
01
_ _ _-+fl----I N-Channel on time
if
nL-_________
Current in
IDIODE
o
device under test
RGURE 5-13 - SCHEMATIC AND TIMING WAVEFORMS OF A
HIGH VOLTAGE, HIGH SPEED CSOA TEST CIRCUIT
MOTOROLA TMOS POWER MOSFET OATA
1-5-8
track those seen in the CSOA testers. Therefore, the test
method and circuit are appropriate for simultating stress
in common applications. Nevertheless, designers should
be aware of how important circuit parameters can skew
the comparison.
Three other circuit parameters can degrade CSOA.
They are solely under the control of the design engineer
and are therefore difficult to include in a CSOA specification. The first is the gate to source impedance of the
OUT. If RGS or LGS is high during reverse recovery, VGS
can exceed V GS(th) due to the large dv/dt that the intrinsic
diode generates. This dv/dt does not fully turn-on the
MOSFET but forces it into the active region and slows the
reverse recovery process, as seen in Figure 14. Since
operating in this mode increases commutation power
losses and clearly involves dv/dt turn-on (of the MOSFET,
not the parasitic BJT), decreasing ZGS is normally the
best approach. However, slowing reverse recovery with
higher gate-to-source impedance can reduce VOS peaks
and may even keep the device from avalanching, which
is also shown in Figure 14.
Junction temperature is the second parameter that
degrades CSOA. Although one might intuitively suspect
that TJ has a first order effect on CSOA, test results to
date indicate that it does not. These results are easier to
believe when one recalls that RBSOA (Reversed Biased
Safe Operating Area) of bipolars is also relatively independent of TJ. Another indication that TJ has a secondary
effect is that OUT voltage and current waveforms are fairly
constant as TJ changes. Varying other more dominant
parameters often causes waveform changes that signal
impending OUT failure.
The final parameter over which the circuit designer has
strict control is the parasitic circuit inductance between
the positive and negative rails of the 1/2 bridge. This
inductance is unclamped and is likely to briefly avalanche
the OUT at very high commutation speeds. In all cases
this inductance should be minimized. The practical lower
limit is in the 100 to 200 nH range.
The second monostable, B1 and B2, provides a delay
before 02 is turned on. Minimum delay is set to 10 p,s to
allow accumulation of stored charge in the diode's junction. After that delay the monostable formed by B3 and
B4 sends a turn-on signal for 2 to 10 p,s. For the duration
of the turn-on pulse, 02 applies reverse voltage to the
OUT's source-drain diode and forcefully extracts reverse
recovery charge. During reverse recovery the current burden of 02 includes the current delivered by the current
source. After 02 turns off the current source is also gated
off and the system remains at rest until the next cycle.
A few circuit features make device testing easier. First,
the drain of the OUT is attached directly to the system
groundplane. This greatly simplifies monitoring VOS and
improves measurement accuracy since using a differential
measurement technique or floating an oscilloscope is
unnecessary with this layout. Additionally, this method
allows use of a probe tip adaptor that provides an excellent
ground connection for the oscilloscope. These pains are
needed because the magnitude of VOS is the most important CSOA parameter and its rate of change can be
greater than 10 V/ns.
A second mundane but very necessary feature is the
capability of the circuit to withstand OUT failure. Current
surges at failure are principally limited by the rOS(on)
of the drive transistor 02 or its cut off current at the
gate-to-source voltage that is applied. In either case the
MOSFET's ruggedness with respect to current surges
and the low duty cycle and limited on-time give the driver
the margin of safety it needs to survive.
Using the CSOA Specification
The CSOA format was chosen to make the rating easy
to relate to operating conditions in an application. The
designer must only maintain VOS and IFM within specified
limits and remember that di/dt is specified as a maximum
allowable value. Pushing devices to their limit in a 1/2
bridge PWM DC motor controller produces failures that
VDS
20 VlDIV
IDiODE
5 AlDIV
0-
0-
(148)
(14A)
FIGURE 5-14 -IF THE MOSFET OF THE REVERSE
RECOVERING RECTIFIER HAS A HIGH GATE-TO-SOURCE
IMPEDANCE, REVERSE RECOVERY TIME IS LONG AND PEAK
VOLTAGE STRESS IS LESS
MOTOROLA TMOS POWER MOSFET DATA
1-5-9
•
OUT normally fails. Therefore, the magnitude of the supply
voltage can have a great effect on a device's energy handling capability. Improving the present UIS test method to
detect devices that exhibit V(BR)CEO snapback is relatively simple. Instead of checking only for device failure,
the VOS waveform in avalanche can be sampled to ensure
that it remains above the transistor's maximum VDS
rating.
As switching speeds and test currents increase in the
commutating dv/dt mode, the device under test is likely
to see overvoltage transients. During the final phase of
reverse recovery the diode current is returning from its
negative peak toward zero. This current can be thought
of as decreasing drain current. If the diode recovers
abruptly, or snappily, the associated dildt can be extremely
large, perhaps greater than 1000 AI/Ls .. !h~se rates of
change in current are opposed by parasitic Inductances,
and the polarity of the induced voltages is such that they
add to the reapplied voltage and increase the voltage
stress on the OUT.
Relationship Between CSOA and UIS
It is tempting to believe that a UIS test (Unclamped
Inductive Switching) is an adequate substitute for a CSOA
test. The argument given is that the common cause of
device failure in the two modes is activation of the parasitic
bipolar transistor due to high RBE, or base-emitter shorting resistance. Although this reasoning seems to make
sense, it is flawed in two ways.
The first is that some devices may pass a UIS test and
then fail in the commutating dv/dt mode due to device
deficiencies other than high RBE. With its voltage termination rings, gate feeds, bonding pads and cell interconnections, the power MOSFETis much more than a few
thousand paralleled cells. In some manufacturer's devices
it is clear that these secondary structural features can limit
performance in one test and not the other.
The second problem with correlation of UIS and CSOA
test results is caused by a flaw in the present UIS test
method. A study of UIS waveforms clarifies this point. As
evidenced by different voltage waveforms in Figure 15, a
device may react to overvoltage stress in at least three
ways. Some devices fail immediately in avalanche and
VOS collapses to about zero volts. Other MOSFETs can
maintain their V(BR)OSS during the entire transient - if
the current and pulse duration are not too great. In the
third case, the drain-to-source voltage of some devices
may collapse to a lower level. The lower voltage in avalanche is associated with activation of the MOSFET's parasitic bipolar transistor. Thus, the magnitude of VDS during avalanche is the transistor's V(BRlCEO.
If the UIS supply voltage is increased above V(BR)CEO,
there is no mechanism to limit avalanche current and the
Figure 16 shows the reverse recovery waveforms of a
10 A, 50 V device from manufacturer "A." The effect of
the device's V\BR)CEO is clearly evident. The clipping of
the VOS wave orm at the device's V (BR)CEO (which corresponds to the value observed in UIS testing) and the
coincident drain current show that the device is in avalanche. Even though the device passes this test, reliability
in this mode of operation is uncertain since the parasitic
bipolar is clearly being activated. If VR is increased to
greater than V(BR)CEO, failure is likely. Because of its
tendency to break back to a V(BR)CEO, this device could
fail in the commutating dv/dt mode, yet survive a UIS test.
']
V(BR)OSS-
IL~~OUT
10
Y
vos
(a)
VOO
(b)
I "'--.,;:::...".,.-----,-V(BR)CEO
voo
(e)
FIGURE 5-15 - A MOSFET CAN HAVE ONE OF THREE
RESPONSES TO AN OVERVOLTAGE TRANSIENT
MOTOROLA TMOS POWER MOSFET DATA
1-5-10
References:
V(BR)DSS
l
V(BR)CEO
VDS
20V/DIV
RlapPliL vOILge-
--- -- - - 1"
. . . W'
-.I
o
.......
IDIODE
5 AlDIV
\
o
I\.
\
-- --~
500mV
-1
1987.
3. S. Krishna, and P. L. Hower, "Second Breakdown of
AA
I
TC = 100·C
-- -- -- --- --- --- ---
V 20V
---I 1-
1. D. W. Berning and D. L. Blackburn, "Power MOSFET
Failure During Turn-Off: The Effect of Forward Biasing
the Drain-Source Diode," Proceedings of the 1986
IEEE Industrial Applications Society Annual Meeting,
October 1986 .
2. K. Gauen, W. Schultz, "Proper Testing Can Maximize
Performance in Power MOSFETs," EON, May 14,
50 ns
Transistors During Inductive Turn Off," Proc. of IEEE,
Vol. 62, March 1973.
4. W. Schultz, K. Gauen, "Commutating SOA in Monolithic Freewheeling Diodes," Powertechnics, January
1986.
DUT in Avalanche
5. The Power Transistor in Its Environment, ThompsonCSF, 1979.
FIGURE 5-16 - COMMUTATION AT VERY HIGH SPEEDS CAN
CAUSE AVALANCHING OF THE OUT
•
MOTOROLA TMOS POWER MOSFET DATA
1-5-11
•
MOTOROLA TMOS POWER MOSFET DATA
1-5-12
Chapter 6: Gate Drive Requirements
Power MOSFET Gate Drive
Requirements
Input Capacitance
Bipolar power transistors have been around for decades
drive circuits for these devices abound. Power
MOSFETs are new arrivals. They differ from their bipolar
counterparts especially in their input characteristics.
These differences and their implications must be understood in order to insure that the MOSFET is operated in
an optimum fashion.
Oriving a power MOSFET is tantamount to driving a
capacitive reactance network. Oepending on the region
of operation, the input "sees" either Ciss, the CommonSource Input capacitance, or Crss , the Common-Source
Reverse Transfer capacitance. Ciss is the sum of the
gate-to-source capacitance, C gs ' and the drain-to-gate
capacitance, Cdg. Cgs is made up of a voltage independent capacitance between the gate structure and the
source metallization and a gate-to-channel capacitance
which varies significantly with operating conditions. Crss
(Cdg) on the other hand, is mainly the MOS capacitance
between gate and drain regions. Its value increases
sharply during the latter stages of turn-on.
The device capacitances, especially the reverse transfer capacitance, and the gate-drive source impedance
largely determine the device switching speed. Since the
MOSFET input capacitances vary significantly with the
die area, a given gate-drive will switch a smaller device
such as the MTP5N06 more rapidly than the larger
MTM15N40. However, two considerations complicate the
task of estimating switching times. First, since the magnitude of the input capacitance, Ciss, varies with VOS,
the RC time constant determined by the gate-drive impedance and Ciss changes during the switching cycle. Consequently, computation of the rise time of the gate voltage
by using a specific gate-drive impedance and input capacitance yields only a rough estimate. The second consideration is the effect of the "Miller" capacitance, Crss ,
which is referred to as Cdg in the following discussion.
An example best explains why it influences switching
times.
When a high voltage device is "on," VOS is fairly small
and VGS is about 15 V. Cdg is charged to VOS(on) VGS, which is a small negative potential if the drain is
considered the positive electrode. When the drain is "off"
and is blocking a relatively high drain-to-source voltage,
Cdg is charged to quite a different potential. In this case
the voltage across Cdg is a high positive value since the
potential from gate-to-source is near or below zero volts
and VOS is essentially the drain supply voltage.
Ouring turn-on and turn-off, these large swings in gateto-drain voltage tax the current sourcing and sinking capabilities of the gate-drive. In addition to charging and
discharging Cgs , the gate-drive must also supply the displacement current required by Cdg (ill ate = Cdg dVOGI
dt). Unless the gate-drive impedance IS very low, the VGS
waveform commonly plateaus during rapid changes in the
drain-source Voltage.
The traditional capacitance curves as shown in Figure
6-1 are somewhat meaningful, but they are not complete.
Unfortunately, because they are incomplete, they can also
be misleading. The fallacy of that presentation is that each
capacitance is shown as a function of VOS and not as a
function of the voltage across that capacitor. For Coss ,
Figure 6-1 is correct as shown because the independent
voltage is VOS with VGS = 0 V. However, these curves
are normally used to determine input impedance, and for
Ciss and Crss the curves omit important information. A
discussion of the variation of Crss with VOG best illusirates this point.
5000
4000
;--~TH6N6J
TJ = 25'C
vGs=ovf=IMHz_
~
.e 3000
\ij
;5
~
<3
2000
1000
Ciss
'~
crss
o
o
Coss
10
15
20
25
30
DRAIN·TO·SOURCE VOLTAGE (VOLTS)
35
40
FIGURE 6-1 - THIS TRADITIONAL REPRESENTATION
OF POWER MOSFET CAPACITANCES IS ACCURATE
BUT NOT COMPLETE.
The first step towards understanding the variation of
Crss with voltage is to study the change in VOG during
the switching transition. When the device 'is off, VOS is
essentially at the drain supply voltage. At that same time
VGS is at or near zero volts, which means that VOG is a
high positive value. When the device is in the "on" state,
a quite different situation occurs. VGS is at roughly 10 V
and VOS is at VOS(on). Therefore VOG is equal to
VOS(on) - VGS(on), which is normally a negative value.
It is this negative sWing in VOG that the traditional curves
do not address.
Now the importance of this additional information becomes evident. One possible presentation of the complete
curve is given in Figure 6-2. The variables plotted on the
abscissa (VGS and VOS) and the test conditions (VOS
= 0 and VGS = 0) reflect the common source test circuit
and the test conditions used to generate the two sections
of the curves. Consequently, this is the format shown on
Motorola's data sheets. A Crss (or Ciss) versus VOG
curve is identical except that the voltage axis is simply
VOG, where VOG takes on negative values to the left of
zero and positive values to the right of zero. The dramatic
MOTOROLA TMOS POWER MOSFET OATA
1-6-1
•
5000
-
4000
-
TJ - 25°C
1- 1 MHz
f-...
MT~6N60
~
VOS - OV
(480 V x 50 pF), and to the left the figure is 23 nC (7 V
x 3300 pF). In this case the traditional approach of only
specifying capacitances at positive voltages omits nearly
half of the required gate charge and can lead to underestimation of required gate drive.
Estimation of the amount of charge transferred to the
gate-to-source capacitance is also enlightening. In this
case a VGS is roughly 10 V and CIlS (= Ciss - Crss )
is about 1100 pF. The charge in this Instance is 11 nC ( =
1100 pF x 10 V). Interestingly, even though Cgs is much
larger than C rss at a VOS of 25 V, Crss under these
conditions requires about four times as much charge.
Also, integrating each of the two input capacitance curves
over the change in voltage that each one sees as the
MOSFET switches theoretically yields the required gate
charge. From the numbers computed above (24 + 23 +
11), the required Og is 58 nC, which closely tracks with
the 10 V value (52 nC) shown in Figure 6-3.
One other problem area may arise when using capacitance measurements to compare input impedance of devices from different manufacturers. Typically, Ciss and
Crss are specified at a VOS of 25 V, and comparisons at
that value may be a poor indication of the relative sizes
at other voltages. For instance, Figure 6-4 shows the Crss
curves of two 500 V, 4.5 A devices from different manufacturers. At a VOS of 25 V the device from manufacturer
r---
VGS - OV
I ' Ciss
Coss
~
Crss
10
5
0
5
10
15
20
25
30
35
VGS ~ VOS
(or - VOG)
(or VOG)
GATE-TO-SOURCE OR ORAIN-TO-SOURCE VOLTAGE (VOLTS)
o
40
FIGURE 6-2 - EXPANDING THE TRADmONAL CAPACITANCE
CURVES TO SHOW THE VALUES OF Ciss AND Crss AS THE
MOSFET MOVES INTO THE "ON" STATE GIVES A COMPLETE
PICTURE OF THE CAPACITANCE VARIATION.
•
rise in Crss of the MTH6N60 (Figure 6-2) from around 50
pF at positive voltages to about 3300 pF at negative voltages simply cannot be ignored_ This larger capacitance
dominates the input impedance during the latter stages
of turn-on and the first stages of turn-off_
Also it becomes apparent that the curves of Crss and
Ciss as traditionally represented often lull the user into a
misconception. He might mistakenly assume that since
VOS never falls below VOS(on) in his system, then Crss
never becomes greater than its value at a VOS equal to
VOS(on)' Again, the problem with this reasoning is that
the voltage across Crss when the device is "on" is not
VOS(on) but VOS(on) - VGS(on)'
Integrating the rss curve over the entire variation in
VOG to determine the amount of stored charge required
by Crss is another convincing way to show the importance
of providing the complete capacitance curves. A rough
piece-wise linear approximation suffices to illustrate this
point. For the two regions above and below VOG = 0 V,
the charge required is roughly the change in VOG times
the average value of Crss in each region. For a 480 V
bus, for example, the charge to the right of zero is 24 nC
10,000
5000
Crss versus VOG for 4.5 A, 500 V MOSFETs-
2000
~
~
1000
500
, .......
MANUFACTURER "8"
z
e
g
~
200
"i-. '"
MANUFACTURER "A"
100
50
I.......
20
10
-10
-5
0
;-
5
10
15
20
25
30
VOG, ORAIN-TO-GATE VOLTAGE (VOLTS)
35
40
2000
20
i!!
~ 16 -MJ6N60
~
~
::>
~ 1200
,/"
~ 14
;::!O
12
./
10
i
~
./
./
~ B
a
~ 6
<3
./
~
'" 4
{;? 2
"'
-r--..
\
BOO
400
,\
, \ MANUFACTURER "8"
'--"k
MANUFACTURER "A"
5
10
15
20
25
30
-10 -5
VOG, ORAIN-TO-GATE VOLTAGE (VOLTS)
o
I
o
o
Crss versus VOG lor ~
4.5 A. 500 V MOSFETs
1600
VOS - 4BO V
10 - 6A
lB
10
20
30
40
50
ag, TOTAL GATE CHARGE (nC)
60
70
BO
35
40
FIGURE 6-4 - SINCE CAPACITANCE CURVES OF DEVICES FROM
DIFFERENT MANUFACTURERS SOMETIMES CROSS. USING A
SINGLE VALUE OF CAPACITANCE TO COMPARE INPUT
IMPEDANCE IS NOT A GOOD IDEA. IN THESE TWO FIGURES
THE SAME INFORMATION IS SHOWN IN TWO DIFFERENT
FORMATS.
FIGURE 6-3 - INTEGRATING THE CAPACITANCE versus
VOLTAGE CURVES GIVES ACCURATE VALUES OF GATE
CHARGE
MOTOROLA TMOS POWER MOSFET OATA
1-6-2
"8" has a Crss about 50% less than that of the device
from manufacturer" A". However, the difference is actually
pretty insignificant when compared to the large differences
between values at other voltages. Note too that the curves
cross and that overall the device from manufacturer "A"
actually has the lower Crss .
Photographs of switching times in Figure 6-5 confirm
what might be expected from a study of the complete
capacitance curves - device "A" is the faster switch. The
gate charge waveforms shown in Figure 6-6 are a more
dependable means of judging relative switching speed.
For these reasons manufacturers are de-emphasizing the
importance of capacitance specifications at a single value
of VDS, namely 25 V. Circuits for testing the MOSFETs
inter-terminal capacitances are given in Chapter 12.
TURN·ON OF DEVICE A
VDS
50 VIDIV
VDS
50 VIDIV
TURN·ON OF DEVICE B
-_l!I!
~ !:I ~
+
VGS
2 VIDIV
~
VGS
2VIDIV
£!!!!!
50 ns!
- •-.
I
~=
---
I
50 ns!
FIGURE 6-5 - ALTHOUGH DEVICE "8" HAS THE LOWER Crss AT A VOS OF 25 V, DEVICE "A" IS THE FASTER SWITCH
250,10
5 A. Voo
300 V
SINCE ITS CAPACITANCE IS LOWER AT OTHER VOLTAGES. RGS
=
=
=
~
I
VGS
2VIDIV
5 ,",' OR 5 nCiDIV
FIGURE 6-6 - GATE CHARGE WAVEFORMS ARE A MORE ACCURATE MEANS OF PREDICTING SWITCHING
5 A, Voo
300 V, IG
1 mA
SPEEDS THAN CAPACITANCE SPECIFICATIONS. 10
=
=
=
Gate Charge Specifications
Understanding the gate charge test circuit aids in the
interpretation of the gate charge waveforms. All gate
charge test circuits, such as the one shown in Figure 67, employ a constant current source to charge the
MOSFET's input capacitance. A constant IG ensures
that Ciss is charged at a fixed rate (i = q/t). The VGS
waveform then, is a representation of VGS versus gate
charge as well as VGS versus time.
Another means of specifying the size of the input impedance of a power MOSFET is to provide a gate charge
curve. As the name suggests, such a curve indicates the
amount of charge that must be supplied to the gate to
effect the various stages of tum-on. These curves and
the associated gate charge ratings are gradually replacing
input capacitance specifications because of their simple
format, ease of use, and the wealth of information they
contain.
MOTOROLA TMOS POWER MOSFET DATA
1-6·3
VOO
+18V
2N3904
100 k
47k
100
Vin = 15 Vpk; PULSE WIOTH '" 100 p.s, OUTY CYCLE", 10%
FIGURE 6-7 -
GATE CHARGE TEST CIRCUIT
A second current source is usually used in the drain to
set the desired drain test current. As will be discussed
shortly, using a current source as a load helps sharpen
the inflection points of the VGS waveform. Gate charge
waveforms can be used to show turn-off behavior, but
they are normally used to describe turn-on characteristics.
•
Figure 6-8 shows the gate-to-source voltage, the drainto-source voltage and the drain current waveforms during
turn-on of the MTP15N06. In this instance, the gate drive
is a 1 mA current source and a 15 A current source is the
load in the drain.
Each inflection point on the gate charge waveform defines the beginning or end of a distinct interval during the
turn-on process. The time required to deliver charge 01
to the gate is the turn-on delay time. At 02 the drain-tosource voltage has fallen to VDS(on) and all switching is
complete. When a charge equal to 03 is supplied, the
gate is charged to VGS(on) and no'more gate charge is
required. The magnitude of VGS(on) is somewhat arbitrary, but in this case a VGS(on) of 10 V requires 15.5
nC of gate charge. During turn-off the amount of time
required to remove 03 minus 02 is the delay time. Removal of 02 minus 01 allows the drain-to-source voltage
to rise to the supply voltage, and discharging 01 brings
VGS back to zero volts. Obviously, to satisfy conservation
of charge, the charge supplied to the gate during turn-on
is equal to and opposite that required for turn-off.
The slope of curve at any point can be interpreted as
being the reciprocal of the capacitance during that portion
of the switching interval (i = C dv/dt yields C = A OgiA
VGS). Even a brief look at a typical gate charge waveform
reveals that the slope or input capacitance takes on at
least three different values. As VGS rises from zero volts,
Ciss is relatively small, which makes charging rather easy.
During the next portion of the curve, the capacitance appears to be infinite since additional charge brings little, if
any, change in VGS. When the plateau ends, VGS is free
to rise again, but not nearly as fast as it did during the
first interval. The capacitance curves and a description of
the change in VDG during the switching transition aid in
explaining why there are three distinct slopes during the
switching interval.
vos
10 V/OIV
10
5 AlOIV
VGS
2 ViplV
o
6
12
16
ag, TOTAL GATE CHARGE InCI OR TIME l!Lsl
AGURE 6-8 - GATE CHARGING WAVEFORMS ARE RIPE
WITH INFORMATION REGARDING MOSFET SWITCHING
VOG
10V/0IV
10
5 AlOIV
o
TIME 2 /LslOIV
AGURE 6-9 - AS VDG APPROACHES ZERO VOLTS.
SWITCHING SLOWS CONSIDERABLY DUE TO A
DRAMATIC INCREASE IN Crss'
MOTOROLA TMOS POWER MOSFET DATA
1-6-4
The drain-to-gate voltage waveform associated with
Figure 6-8 is shown in Figure 6-9. This photograph clearly
shows that just before VOG changes polarity the slope
changes and switching slows due to an abrupt increase
in Crss .
A look at the gate-to-source capacitance and its variation with VGS completes the analysis of how the input
impedance varies during the switching cycle. From Figure
6-10 and the equation Cgs = Ciss-Crss, Cgs is easily
determined. It is commonly assumed that C gs is an invariant capacitor formed by the polysilicon gate and the
source metallization. This belief is supported by the traditional representation of the capacitance curves. However, for many devices a large portion of Cgs is the capacitance between the gate and the channel, and this
capacitance varies considerably as the device turns on.
The now familiar pattern of modeling the capacitor with
two values reappears. From Figure 6-10 the value of Cgs
before and during turn-on is nearly 500 pF whereas after
turn-on it falls to less than 200 pF. As was previously
shown for the MTH6N60, integrating these curves over
the correct voltage ranges yields gate charge figures that
are very close to data on gate charge curves.
There is some confusion regarding the slope of the VGS
waveform during the plateau region. It is often stated that
during the plateau the slope is an indication of the gain
of the device. This is true for resistive loads, but the reactive nature of the load also strongly affects the magnitude .of the slope.
In many gate charge test circuits a MOSFET that is the
same device type as the device under test is used as a
constant current source in the drain. For an ideal current
source the turn-on load line is capacitive, that is, the drain
current reaches its steady state value just as the drain
voltage begins to fall. Except for the premature dip in VOS
due to the MOSFET being an imperfect current source,
Figure 6-8 illustrates this phase relationship quite nicely.
Figure 6-8 also clearly shows that the slope of the VGS
waveform in the plateau region is zero. This should be
expected from the load line shown in Figure 6-11. First
10 rises to 15 A before any appreciable change in VOS.
Then during the entire VOS transition 10 is constant, requiring no change in VGS.
Once the basic concepts of gate charge characterization are mastered, understanding the effect of varying load
The slopes of the gate charge waveform in the first and
third intervals can be directly related to capacitance values
shown on the capacitance curves. In the first interval the
slope of the gate charge curve indicates that Ciss is equal
to 4 nCf7 V or about 570 pF. The similarity between this
value and the magnitude of Ciss in Figure 6-10 at higher
voltages is not a coincidence. Until VGS rises beyond
VGS(th), the MOSFET remains off and VOS remains constant and equal to the supply voltage. Consequently, during this interval Ciss is also constant.
2000
1600
f
= 1 MHz
~1200
u
:z
g
~
\
800
'"' "-
400
o
.......
-15 -10
-5
~
Ciss
erss
10
15
20
25
VDG. DRAIN·TO·GATE VOLTAGE (VOLTS)
FIGURE 6-10 -
30
35
COMPLETE Ciss AND cros CURVES
OF THE MTP15N06
On the other side of the plateau, Ciss takes on a much
larger value. There the change in charge divided by the
change in VGS yields a capacitance of around 1300 pF.
This corresponds to the value of Ciss at drain-to-gate
voltages below - 5 V. Therefore, for circuit modeling in
the first and third intervals of turn-on the magnitude of
Ciss can be estimated by measuring slopes of the gate
charge waveform or by selecting values of Ciss from opposite ends of the capacitance curve.
Estimation of Ciss during the plateau is also possible.
Even though the slope of the curve is near zero, Ciss is
not infinite as it may first appear. In this region the delta
VGS is approximately zero, so no charge enters Cgs . All
the charge instead enters Crss , which makes the magnitude of Crss and its variation with VOG the parameters
of importance. The analysis is simplified somewhat if it is
recognized that since Il VGS = 0, Il VOG = Il VOS. That
allows computation of Crss from Il QIIl VOS instead of Il
QIIl VOG.
Ouring the the VGS plateau there is a distinct change
in the slope of the VOS waveform as the voltage nears
VOS(on). In the first portion of the plateau Crss is approximately 100 pF (4 nC/40 V), which appropriately corresponds to the highest drain-to-gate voltage in Figure 610. After that inflection point the turn-on process slows
considerably, hinting of a much larger capacitance.
Indeed, Crss during the second portion of the plateau is
roughly 7 nC/10 V or 700 pF. That value corresponds to
a VOG of around -5 V on the Crss versus VOG curve.
So although Crss varies throughout its entire range during
the VOS transition, it could be modeled as taking on only
a pair of values. One value would correspond to positive
drain-to-gate voltages and a second figure for negative
voltages.
20
OUTPU~ CHARA~TERISTlhs
OF AN MTP15N06
16
/'
/
I
LOAD LINE DURING
SWITCHING OF A
CONSTANT CURRENT SOURCE
.....
\
//
o
.0
FIGURE 6·11 -
10
20
30
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
CURRENT SOURCE YIELDS A CAPACITIVE
LOAD LINE AT TURN-ON
MOTOROLA TMOS POWER MOSFET OATA
1-6-5
40
current and supply voltage is simple. As 10 increases, the
required gate-to-source voltage, which is dictated by the
transfer characteristics, also increases. As Figure 6-12
shows, this causes the plateau to occur at higher voltages.
Figure 6-13 shows the effect of changing VOO. Varying
VOO changes the potential through which Crss must be
charged. The increased charge requirements account for
the lengthening of the plateau at greater supply voltages.
Of course, the most straightforward use of gate charge
data is to help determine the amount of charge that must
be supplied to the gate to fully turn-on a device. That
charge can be separated into three parts, each of which
coincides with the requirements of a portion of the switching interval. The first portion defines the charge needed
during the turn-on delay; the second indicates the charge
necessary to effect the rise or fall of VOS; and the charge
in the third region is associated with the turn-off delay.
Also the curve clearly defines the penalty of additional
charge exacted for using an unnecessarily large gate-tosource voltage.
Once the amount of charge is known, determining the
current required to obtain a desired switching speed is an
exercise in basic algebra (q = it). In Figure 6-8 the voltage
fall time occurs while a charge equal to 02 - 01, or 8
nC, is being supplied. Therefore, a100 ns transition requires an average IG of 8 nC/100 ns, or 80 mA.
The major limitation of this type of analysis is that gate
drives are rarely constant current sources. Most are more
accurately represented as a voltage source in series with
a fixed internal resistance. Therefore, what is normally of
interest to a designer is the value of resistance required
for a given switching speed.
With a few reasonable assumptions, gate charge concepts can be successfully applied in this instance, too.
The basic concepts here are (1) except for extraordinarily
fast switching speeds «50 ns) the rise of the gate-tosource voltage stalls in a plateau region, regardless of the
type of gate drive and (2) the drain-to-source voltage excursions occur during the plateau of VGS.
When the gate voltage stalls during turn-on, the voltage
across the gate drive resistance is simply VGG
- VGS(plateau) and IG is equal to this voltage drop divided by the drive impedance (Figure 6-14c). The nearly
constant IG during the fall of VOS is shown in Figure 614b. This provides the link to the use of gate charge data.
Suppose, for example, that the desired VOS fall time
during turn-on of the MTP15N06 is 2 /Ls. This time and
the 8 nC of required gate charge, which is the charge
during the plateau of Figure 6-12, fix the necessary gate
drive current at 4 mA (8 nC/2 /Ls). For a 10 A load the
plateau occurs at a VGS of 7.5 V, and with a 10 V gate
drive the potential across the gate drive internal impedance is only 2.5 V. These figures yield a gate resistance
of 620 ohms (= 2.5 V/4 mAl, As the oscilloscope waveforms of Figure 6-14 show, this method of selecting gate
drive impedance is fairly accurate. As expected, decreasing the gate drive impedance by a factor of ten brings a
tenfold decrease in switching time.
It is also enlightening to pursue the reason for the more
rapid turn-off in Figure 6-14 even though the gate drive
impedance at turn-on and turn-off are the same. The answer is simple; the gate current is greater due to a higher
potential across the internal impedance. The current during the turn-off plateau is VGS(plateau) - VGS(off) divided by RG. In this case the numbers are (7.5 - b V)
+ 620 ohms, or about 12 mA, instead of the 4 mA at turnon. As it should be, the ratio of currents is proportional to
the switching speed.
The second major benefit of the concept of gate charge
is that it enhances understanding of the MOSFET's
switching behavior. Three examples prove this point. First,
VGS
2 VlOIV
Og. TOTAL GATE CHARGE (2 nClOIVj OR TIME (2 /LslDIVj
FIGURE 6-12 -
INCREASING DRAIN CURRENT RAISES THE
HEIGHT OF THE PLATEAU
VGS
2V/DIV
Og. TOTAL GATE CHARGE (2 nClDIVj OR TIME (2/LslDlVj
FIGURE 6-13 -INCREASING THE SUPPLY VOLTAGE CAUSES
THE PLATEAU TO LENGTHEN
Uses of Gate Charge Data
Sometimes gate charge is politely thought of as an interesting, but not particularly useful, parameter. Often engineers do not develop an interest in the parameter simply
because using gate charge is not the conventional method
of determining input impedance. Although using gate
charge may be· somewhat different from typical approaches, it is not difficult, and it certainly is a useful and
informative specification.
MOTOROLA TMOS POWER MOSFET DATA
1-6-6
understanding that the MOSFET is controlled by gate
charge helps in predicting the effect of the gate drive
impedance on switching speeds. Theoretically, halving the
impedance of the gate drive should double the rate of
charging and halve the switching times. This has been
shown to hold true over a five decade change in gate drive
current.
Second, the concepts reveal the weakness of using or
specifying only the values of capacitance at a single point
on the capacitance versus voltage curves. And third, they
show that even though CGS is the larger of the input
capacitances at a VDS of 25 V, Crss has the greater effect
during most of the switching interval.
A more subtle benefit of the gate charge curve is that
it provides the data required for accurate device modeling.
As was shown earlier, the input impedance and the switching behavior of the MOSFET can be modeled by selecting
values of Crss and Cgs from the slopes of the gate charge
waveform. Using these values yields results that are much
more meaningful than those obtained by using a single
value of each capacitor at VDS of 25 V.
The trend towards the use of higher switching frequencies in such applications as the series resonant power
supply make estimation of required gate charge and transferred energy of increasing importance. As operating frequencies increase, the MOSFETs "high input impedance" eventually consumes substantial drive current.
Charging and discharging Ciss (and Cos s) every cycle
can result in an energy loss large enough to affect overall
efficiency. In addition to its other more common uses, the
gate charge curve also helps in estimating the energy
consumed by the gate.
The familiar formulas, E = 1/2 CV2 and 1/2 QV, apply
only to fixed values of capacitance. For voltage dependent
capacitors such as the Ciss of the power MOSFET, the
gate voltage versus gate charge curve must be integrated
between VGS(off) and VGS(on) to determine transferred
energy. This energy is stored in Ciss during turn-on and
is normally lost when the gate is clamped to the source
at turn-off. Multiplication of this energy by the switching
frequency gives the associated power loss.
For example, consider the energy stored in the input
capacitance of the MTM15N50. For a VGG of 10 V the
area under the curve in Figure 6-15 is 0.625~. This loss
VDS
5VIDIV
VGS
5VIDIV
1J.'S/DIV
(a) GATE-TO-SOURCE AND DRAIN-TO-SOURCE VOLTAGE
WAVEFORMS DURING RESISTIVE SWITCHING
VR
5V/DIV
OR 0
IG
- SmA/DIV
1J.'S/DIV
(b) GATE CURRENT
VGS!on)
IrI
f-l ..~
~DD
T
.~-
~1~~
u;!:;
o
~12~-+--~--~-+--~--~-+--~--b-~
'"~
§;
~
';;0_
5
~
~
'"v,
(e) SWITCHING SPEED TEST CIRCUIT
o
FIGURE 6-14 - BECAUSE THE GATE-TO-SOURCE VOLTAGE
AND GATE CURRENT ARE RELATIVELY CONSTANT DURING
THE VDS EXCURSIONS, GATE CHARGE CAN BE USED TO
ESTIMATE GATE DRIVER IMPEDANCE FOR A DESIRED
SWITCHING SPEED.
40
SO
120
160
200
Qg. TOTAL GATE CHARGE InCI
FIGURE 6-15 - THE GATE CHARGE CURVE OF THE
MTM15N50 GIVES INFORMATION REGARDING THE ENERGY
CONSUMED WHILE DRIVING THE MOSEFET's GATE.
MOTOROLA TMOS POWER MOSFET DATA
1-6-7
normally goes unnoticed even though this device is one
of the largest available. Even at a switching frequency of
1 MHz, the dissipated energy is only 0.625 watts. Note,
however, that if the gate is driven to a VGG of 16 V then
the losses rise to 1.275 p.J and 1.275 W.
Yet to be included in this analysis of drive losses is the
energy consumed by the gate drive as it delivers the required gate charge. Figure 6-16 shows the equivalent circuit of an idealized gate drive network in which S1 completes the charging path and S2 controls discharging.
r<
The open-collector TTL device, when used with a pullup resistor tied to a separate 10 to 15 V supply, can
guarantee rapid gate turn-off and ensure sufficient gate
voltage to turn the MOSFET fully on (Figure 6-17). Turnon is not as rapid because the pull-up resistor must be
sized to limit power diSSipation in the lower TTL output
transistor. However, when concerned about dynamic
losses incurred while switching an inductive load, the gate
fall time is more critical than the rise time due to the phase
relationship between the drain current and drain-source
voltage. Figure 6-18 shows a configuration providing fast
turn-on, yet reducing power diSSipation in the TTL device.
·
~
--'1 ",
C
lL-.--"_G_ _
--1--_
FIGURE 6-16 -
IDEALIZED GATE DRIVE CIRCUIT
Regardless of the magnitude of the equivalent resistance
and the rate of charging, the size of Ciss and VGS(on)
determine the energy transferred during turn-on and disSipated at turn-off. Likewise, the energy dissipated in Ron
is also independent of the size of Ron and the gate drive
current. Again, integration of a Q versus V curve gives
energy, but this time the appropriate voltage is VGG VGS. This integration is equivalent to finding the area
between the gate charge curve and VGS = VGG.
Now the picture of the gate drive losses is complete.
Total losses are simply VGS(on) times the required gate
charge.
FIGURE 6-17 -
DRIVING TMOS WITH OPEN COLLECTOR TTL
+15V
Common Source Switching
TTL Gate-Drives
Driving a TMOS power transistor directly from a CMOS
or open-collector TTL device is pOSSible, but this circuit
simplicity is obtained at the cost of slower switching
speeds due to the charging current required by the
MOSFET's parasitic input capacitance and the limited
source and sink capabilities of these drivers.
A TIL device with a totem pole output and no additional
circuitry is generally not an acceptable gate-drive network.
In this case, the output voltage available is approximately
3.5 volts, which is insufficient to ensure the MOSFET will
be driven into the ohmic region. A, slightly more promising
situation would be to use a pull-up resistor on the TTL
output to utilize the entire 5.0 V supply, but even the full
5.0 V on the gate would not guarantee the MOSFET will
conduct even half of its rated continuous drain current.
FIGURE 6-18 - OPEN COLLECTOR TTL-TMOS INTERFACE FOR
FASTER TURN-ON AND REDUCED POWER DISSIPATION
When the lower transistor in the TTL output stage is
turned on, shunting the MOSFET input capacitance to
ground, modeling the bipolar as a saturated device may
not be appropriate. The current sinking capabilities of TTL
devices in the low output state is limited by the beta of
the pull-down transistor and its available base current,
which varies with the product line and TTL family. Table
1 shows the current source and sink capabilities of various
TTL families.
MOTOROLA TMOS POWER MOSFET DATA
1-6-8
Although the TTL peak current sinking capability might
be twice the continuous rating, faster turn-off can be
achieved by using an outboard transistor to clamp the
gate-to-ground (Figure 6-19). In this configuration, the bipolars are operating as emitter followers. As such, they
are never driven into saturation and their associated storage times do not significantly affect the switching frequency limit.
As an illustration, with a VDS of 15 V, a standard CMOS
gate can typically source 8.8 mA in the HIGH state without
its output falling below 13.5 volts.
I! the switching speeds of CMOS buffers are not rapid
enough, the discrete buffers suggested for use with TTL
devices (Figures 6-18 and 6-19) can also be used to interface CMOS to TMOS. The only difference is the pullup resistors are unnecessary for CMOS. Another difference in the two technologies that may affect the maximum
switching frequency limit is that the TTL gates typically
have faster switching times.
Other Gate Drives
In certain situations pulse transformers are an effective
means of driving the gate of a power MOSFET. They
provide the isolation needed to drive bridge configurations
or to control an N-Channel MOSFET driving a grounded
load. One of the simplest examples of such a circuit is
the first circuit in Table 3 where the rise, fall, and delay
times for this and the other circuits to be discussed are
tabulated.
The diode in Circuit 1 is present simply to limit the
flyback voltage appearing across the drive transistor Q1.
A transformer turns ratio of one-to-one was chosen to
provide an appropriate voltage at the secondary given the
15 volt primary supply voltage. A potential problem with
this circuit is that the duty cycle influences the magnitude
of VGS because the volt-seconds produced during the on
and off intervals at the secondary must sum to zero. Figure 6-20 indicates that increasing the duty cycle decreases the maximum gate-source voltage. As the duty
cycle increases above 33%, for the given primary voltage
of 15 volts, the peak gate voltage falls below 10 volts and
may eventually drop to a point where the device is no
longer operating in the ohmic region. Increasing the primary voltage to 20 volts would increase the maximum
allowable duty cycle.
AGURE 6-19 - OPEN COLLECTOR TTL DRIVING
COMPLEMENTARY EMITTER FOLLOWER
CMOS Gate Drives
Driving the power MOSFET directly from CMOS presents a different set of advantages and disadvantages.
Perhaps most important, CMOS 'and power MOSFETs
can be operated from the same 10 to 15 volt supply. A
gate voltage of at least 10 volts will ensure the MOSFET
is operating in its ohmic region when conducting its rated
continuous current. This benefit allows the designer to
directly interface CMOS and TMOS without any additional
circuitry including external pull-up resistors. Again, however, circuit simplicity results in slower MOSFET switching
due to the limited current source and sink capabilities of
CMOS devices. Table 2 compares the output current capabilities of standard CMOS gates to that of the CMOS
buffers (MC14049, 14050). Note that while the current
sinking capacity of the buffers is improved significantly
over that of the standard CMOS gate, the current sourcing
capacity is not. The figures in Tables 1 and 2 indicate the
current at which the device can still maintain its output
voltage within the proper logic level for a given logic state.
'13.5V
Duty Cvcle ; 10%
0-----f~~~~n7.~~7n~~_i----
-1.5 V
'10V
VGS
TABLE 1 - TTL Output Current Source
and Sink Capabilities
0--~~~~~n7n7n7.n7.n7.n7.~----~--
-5.0 V
Output Drive
Family
High (Source)
Low (Sink)
74LSOO
0.4mA
8.0mA
7400
0.8mA
16mA
9000
0.8mA
16mA
74HOO
1.0mA
20mA
74500
1.0mA
20mA
FIGURE 6-20 - VARIATION OF VGS WITH DUTY CYCLE
IN PULSE TRANSFORMER GATE-DRIVE
The basic pulse transformer topology of Circuit 1 also
has both maximum and minimum pulse width limitations
in addition to those imposed by the volt-seconds requirements. The current in the primary winding may ramp-up
to excessive levels due to magnetic saturation, especially
MOTOROLA TMOS POWER MOSFET DATA
1-6-9
TABLE 2 -
CMOS Current Source and Sink Capabilities
B-Serie. Gate. (MC14001 CPI
Current
Source
Capability
Current
Sink
Capability
•
CMOS Buffers IMC14049. 14060CPI
MinimA)
Typ(mAI
Min (mA)
TyplmA)
VOH = 2.5 V
5.0V
-2.1
-4.2
-1.25
-2.5
VOH =9.5V
10V
-1.1
-2.25
-1.25
-2.5
VOH = 13.5 V
15V
-3.0
-8.8
-3.75
-10
VOL =O.4V
5.0V
0.44
0.88
3.2
6.0
VOO
VOL =0.5V
10V
1.1
2.25
8.0
16
VOL =1.5V
15V
3.0
8.8
24
40
in the smaller pulse transformers, if the pulse width is too
wide. On the other hand, very short pulse widths may
cause two different problems. First, transformer leakage
inductance may limit current sourcing capability during a
significant portion of the turn-on interval of a very small
pulse width. Second, the pulse width must be wide enough
to allow the magnetizing current (1m) to ramp-up significantly, because the stored energy (defined by the current
in the magnetizing inductance) provides turn-off drive to
the MOSFET gate. To eliminate the problem of 1m varying
with pulse width and to improve turn-off drive, the circuit
shown in Figure 6-21 may be used.
+v
JL
FIGURE 6-21 - CIRCUIT TO ELIMINATE THE VARYING OF 1m
WITH PULSE WIDTH
A modification to the basic transformer gate-drive circuit
described above is the addition of a zener diode in series
with the clamping diode (Circuit 2). The zener allows additional flyback voltage to appear across the primary terminal, when 01 is turned off. When this additional potential is induced across the secondary, it initially provides
greater reset voltage levels and, thus, more rapid gate
turn-off. Naturally, inherent in this circuit are the same duty
cycle, pulse width and frequency limitations that accompanied Circuit 1.
Circuit 3 is very similar to Circuit 1 except the gate
resistances are scaled upward and one is shunted by a
diode. The purpose of this configuration is to speed up
the MOSFET turn-on while leaving the turn-off slow in
comparison. While the MOSFET input capacitance can
charge rapidly through the diode, it must discharge
through the two relatively high impedance gate resistances. This might be done to minimize inductive flyback
voltage or any other undesired phenomena occurring during very rapid turn-off.
A variation of the push-pull converter is used to drive
the gate of the MOSFET in Circuit 4. When 01 is turned
on, the 10 volts across the lower of the two primary windings induces the same potential in N2. The voltage seen
at the secondary, due to the 2:1 step-down ratio (N1 +
N2/N3), equals the primary supply voltage. At turn-off, the
potential across N2 reverses and is clamped to the 10 V
supply by D1. Now N2 induces its voltage in N1 and the
potential appearing at the secondary reverses in polarity
but the magnitude is still 10 volts. If the pulse width is long
enough to generate sufficient magnetizing current, this
circuit yields good current sinking capabilities.
Two opto-coupled drive circuits are shown in Circuits 5
and 6. Circuit 5 is one of the most straightforward ways
of developing a low impedance gate-drive from the output
of the optocoupler. This circuit, however, is plagued by
long switching delays that limit the useful operating frequency. These delays are inherent in the optocoupler and
their magnitudes are affected by the phototransistor's output load impedance. If this impedance is lowered, as accomplished with Circuit 6, the gate-drive turn-off delay is
significantly lower. Besides the complexity of these circuits, especially Circuit 6, the gate-drive's bipolar output
transistor, 02, must remain on the entire time that the
MOSFET is off. The energy dissipated in these two drivers
during low duty cycle operation may be critical if efficiency
is a major concern.
Circuits 7 and 8 are similar versions of a circuit that can
be used as a high performance gate-drive. The base currents for the bipolar drives must be push-pulled as shown
in Figure 6-22. MOSFET turn-on is initiated during a positive transition of the input pulse. 01 is turned on, supplying the required base current for 03, which is Baker
clamped to minimize its turn-off storage time. Both circuits
have excellent turn-on times because of the low impedance path provided between the supply and the gate of
the MOSFET.
MOTOROLA TMOS POWER MOSFET DATA
1-6-10
TABLE 3 - Switching Speeds
of Various TMOS Gate Drives
Drain Switching Times (nl)
Gate Switching Times (nl)
Turn-on
Delay
(V in vaV,)
Turn-on
Rise
Time
Turn-off
Delay
(Vin vs V,)
15
85
35
Turn-off
Fall
Time
Turn-on
Delay
(V in va V 2 )
Turn-on
Fall
Time
25
25
Turn-off
Delay
(V in VSV 2 )
Turn-off
Ri••
Time
-I
s:
.v
1
0
en
-c
0
~
..... ::E
m
:xl
s:
0
en
"m
.'5V
,
I
J;Gj "
Circuit 2
Pulse
Transformer
w/Flyback
Zener
,
15
90
25
190
30
25
125
35
I
I
v,n
n-
I
I
01
-I
0
~
~
~
I
.!. 0
N3
v,"
JL
~
~
~
i'V
':.11
V2
t15k
m
:Xl
s:
@
"
~
o
~
:I>
Vee
Circuil6
HighB.W.
Oplo-Coupling
Circuit
lV2
lt-
Circuit 7
High
Performance
-u-
Push-Pull
Circuit
2~v
JL
Q2
.70
TABLE 3 - Switching Speeds
of Various TMOS Gate Drives (continued)
Drain Switching Tim"lnl)
Gate Switching Times Ins)
Turn-off
Fan
Time
Turn-on
Delay
IVinvsV2)
Turn-on
Fan
Time
Turn-off
Delay
IVinvsV,)
Time
Tum-off
Delay
IV in vsV 2 )
Tum-off
Ri..
Tima
20
60
45
70
40
25
85
15
110
5000
60
600
480
1000
375
150
45
1800
30
210
180
310
140
50
25
710
30
140
60
60
130
30
Turn-on
Delay
IV in vs V,)
Turn-on
Ri ••
1
+15V
N
s::
~
o
V,n
CircuitS
High
Performance
Push-Pull
Circuit
01
L.r 22
Vl
Q2
470
V2
q
Jl.
"
-v
~
>
~
oC/l
~ C3
(,)
::E
'V
lOV
Circuit 9
1/6 SN74LS05
Low Power
Schottky
lV2
12k
q
v,n
ITL
Jl.
m
Vl
Jl
s::
g
m
o
~
:l>
1
'V
"TI
-I
3/6SN74LS05
~
Circuit 10
Paralleled
Low Power
Schottky
V,n
ITL
Jl.
390
8
V2
~
Vl
1
N
Circuit 11
Paralleled
SN7407
8uffers with
Pull-Up
Resistance
15V
::~"
q
Vl
2/6SN7407
I
TABLE 3 - Switching Speeds
of Various TMOS Gate Drives (continued)
1
Gate Switching Times (ns)
Orain Switching Times (na)
Turn-on
Turn-off
Fall
Time
Turn-on
Delay
(V in VSV 2 )
Fall
Time
Delay
(V in vsV2)
Tum-off
Rise
Time
20
20
50
20
40
10
430
20
20
110
40
40
10
30
920
20
130
100
160
90
30
370
100
170
80
280
50
230
15
Turn-on
Delay
(VinVSV,)
Turn-on
Rile
Time
Turn-off
Delay
(V in vs V,)
Turn-off
Rl ; 2.0 k
30
140
Rl ; 5.1 k
so
>V
Circuit 12
SN7407 Buffer
Driving a
Complementary
Emitter-Follower
15V
JL
.,
Vl
v"
q
V2
SN7407
s::
~
oJJ
o
!;
-;
~
Ul
0, \l
.:.. 0
..,. ~
m
Circuit 13
Six Paralleled
CMOS Inverters
(MCl4049UB)
iJ
6;6MC1~~~~,l'V
v"
200
q
V2
V1
JJ
s::
o
Ul
"T1
~
o
»~
+50V
Circuit 14
Dual
Peripheral
Driver
(MC1472)
:r·'f';}··
q
, 1,472:
JL ~_
1
V1
ltTransformer Specs:
Ferroxcube 3019P3CB
Nl ; N2 ; N3 ; 10Turns
#19 Trifilar Wound
Lp=O.S mH
+15 V
+v
270
1.0 k
680
J
~q
+15V
R1
15k
1N914
FIGURE 6-22 -
PUSH-PULL BASE DRIVE FOR CIRCUITS 7 AND 8
Turn-off occurs when the falling edge of the input pulse
is differentiated by the series combination of R1 and C1
thus turning on 02. Base current is then free to flow int~
04, clamping the gate-to-ground or a negative potential.
The duration of the clamping interval may be adjusted by
varying the RC network. Before the occurrence of another
input pulse, the MOSFET will remain off due to the 470 n
gate-source resistance.
Circuits 9 through 12 are examples of how TTL devices
may interface with the TMOS power MOSFET. The first
of the circuits, number 9, has a very simple interface be-
tween the open collector, Low Power Schottky SN74LS05
hex inverter and the MTP12N10. Turn-off speed is fair,
considering the circuit simplicity, but turn-on speed is poor
because of the large value of R1 needed to protect the
inverter from excessive power dissipation when the TTL
output is low. Putting three such buffers in parallel, Circuit
10, reduces all the associated switching times by a factor
of nearly two-thirds.
Another TTL device with an open collector output is
utilized in Circuit 11. Two of the six buffers in the SN7407
operate in parallel with only a pull-up resistor and the gate
of the MOSFET connected to the collector of the high
voltage (30 volts) output transistors. The associated
switching times are quite respectable given the Simplicity
of the drive circuit.
Another application of the SN7407, as mentioned earlier, is to use it to drive a discrete complementary emitterfollower buffer (Circuit 12). Lowering the pull-up resistor,
R1, increases the turn-on speed at the expense of increasing gate turn-off power dissipation.
Figure 6-23 shows an MTM12N10 being driven by a
CMOS MC14050CL Hex Buffer. To obtain the maximum
output current source and sink capability, all six buffer
elements are paralleled.
While the pull-up resistor is not a necessity (as it is with
open-collector TTL devices), it does balance the current
source and sink capabilities of the CMOS buffer. Without
that resistor, one could expect slower turn-on but the drive
circuit would be more efficient because the CMOS device
no longer must sink the current drawn through R1 when
the CMOS outputs are low. Of course, fewer than the six
paralleled inverters could be used at the cost of slower
switching. Figure 6-24 shows the switching waveforms
without a pull-up resistor. For the six buffer elements in
parallel the peak IG during turn-on is about 350 mA and
900 mA during turn-off.
While not as fast as other more elaborate drive circuits,
the MC14050CL offers an inexpensive single power supply device that interfaces directly to CMOS and MHTL
circuitry.
r--_----Q 25 V
10Vo--rL.
r
0.1
FIGURE 6-23 -
MC14050CL HEX BUFFER AS A DRIVER
FOR POWER MOSFET
MOTOROLA TMOS POWER MOSFET DATA
1-6-15
1------0.4 A
IG---O
~-----20V
VOS--l0V
1------0
1------l0V
VGS--5.0V
~-----O
100 n./div
•
FIGURE 6-24 -
POWER MOSFET SWITCHING WAVEFORMS
WITH MC14050CL HEX BUFFER
(6 BUFFER ELEMENTS IN PARALLEL)
~-----+0.1 A
IG---O
~-----O.IA
1------20 V
VOS--l0V
~----O
f------l0V
VGS--5.0V
1------0
200 ns/div
FIGURE 6·25 -
POWER MOSFET SWITCHING WAVEFORMS
WITH MC14050CL HEX BUFFER
(SINGLE BUFFER ELEMENT)\,
MOTOROLA TMOS POWER MOSFET DATA
1·6·16
Figure 6-25 shows the results of the MTM12N1 0 being
driven by a single MC14050CL buffer element. Note the
time scale has been doubled to allow VGS to rise to its
upper rail. The gate current scale is a factor of four smaller:
peak gate currents of about 70 mA during turn-on and
240 mA during turn-off are seen.
Several ICs that were originally intended for other applications have been adopted by some circuit designers
looking for fast, yet simple and efficient MOSFET gatedrive schemes. One such device is the MC1472, a dual
peripheral driver, designed to interface MOS logic to high
current loads such as relays, lamps and printer hammers.
Because each of the two output transistors can sink 300
mA, MOSFET turn-off times are short when this device
is used in a gate-drive network. Turn-on times are also
short in Circuit 14 because the value of R1 is so low that
it only minimally impedes the current during the charging
of the MOSFET input capacitances. The advantage of this
large current sourcing capability is once again offset by
the significant currents that will flow whenever the
MC1472 output is low to turn the MOSFET off. In fact, for
the 25 ohm pull-up resistor and a VCC1 of 15 volts, that
current approaches the combined sinking capabilities of
the two output transistors in that package.
The OS0026 Clock Oriver has been designed to drive
high capacitance loads. It features a peak output current
of 1.5 A and transition times of about 30 ns when driving
capacitance loads equivalent to the Ciss of a power
MOSFET. Input drive voltages for the OS0026 are compatible with Series 54174 TTL devices, such as the
MC7405 Hex Inverter (OC). Detailed information regarding transition times versus load capacitance and power
dissipation can be found in the OS0026 data sheet.
Figure 6-26 identifies the OS0026 driving an
MTM12N10. To illustrate the high peak gate currents that
can be sourced by the OS0026, no resistance was included between driver output and MOSFET gate. It is
important to remember that, with gate current transitions
occurring in the low nanosecond range, any lead inductance between driver and gate will add (URg) delay to the
gate circuit. Keep the distance between driver output and
gate terminal as short as possible when fast switching
times are important.
.----.
TJ
100'C
I
on
CT 10 ~8.0 A = 'O;4 ) ~ ---'------;,"'00""C"..."'25::::'C,,--------
P
25'C
0.400 + (100-25) 0.002
V2
TJ = l1TJC
FIGURE 7-1 - ON-RESISTANCE versus
DRAIN CURRENT - MTP8N18
•
~
~
- - ~ - - ~ 16.36W
rOS(on)
0.550
l1TJC ~ Po * RIIJC ~ 16.36 *1.67 ~ 27.33'C
Po
c
~ 0o
ITJ = 100'C ~ rOS(on) ITJ
~ 3.0 Volis
A point essential to the above calculations is that the
steady state thermal resistance was employed to compute
the junction temperatures. For pulsed conditions RIIJC
can vary significantly. and the transient thermal resistance
obtained from the thermal response curves must be used
to make this calculation. During switching transitions.
there is insufficient time to establish differences in junction
temperature and power MOSFETs may not current share
in the same manner.
MOTOROLA TMOS POWER MOSFET DATA
1-7-2
Dynamic Current Sharing Design
Considerations
The term "dynamic" is broadened here to include not
only current during turn-on and turn-off, but also peak
current during narrow pulses and small duty cycles. Under
these conditions, not enough RMS current is present to
cause differential heating of the junctions which triggers
the tendencies of the devices to share current. Since the
argument supporting current sharing under static conditions is based on differences in junction temperature due
to an imbalance of power dissipation and drain currents,
that reasoning does not support the concept of current
sharing during dynamic conditions. However, even without
the benefit of the positive temperature coefficient, power
MOSFETs can current share reasonably well with simple
and efficient gate-drive circuitry.
The issues of greatest concern to those interested in
dynamic current sharing of paralleled MOSFETs are listed
and described in order below.
50 ns/div
FIGURE 7-28 -
PARALLELED TURN-ON
1. Device parameters that influence dynamic current
sharing.
2. Variation of pertinent device parameters from lot to
lot.
10
2.0 Aldiv
3. Required device parameter matching to achieve
safe levels of current distribution.
4. The effects of switching speed on dynamic current
sharing.
VGS
10 Vldiv
5. The requirements and effects of circuit layout.
6. The possibility of self-induced oscillations.
50 nsldiv
Device Parameters That Influence Dynamic
Current Sharing
The device parameters that influence the degree of dynamic current sharing are the transconductance (9FS),
gate-source threshold voltage [VGS(th)], input capacitance, and the on-resistance rOS(on). However, the device characteristic that most accurately predicts how well
paralleled MOSFETs will current share during turn-on or
turn-off is the transconductance curve, i.e., the relationship between the drain current and the gate-source voltage. To obtain optimum current distribution during turnon and turn-off, the ideal situation is to have all gatesource voltages rising (or falling) simultaneously on devices with identical transconductance curves. This combination would ensure that as the devices switch through
the active region, none would be overstressed by a current
imbalance. Figures 7-2a, 7-2b and 7-2c show the nearly
perfect degree of current sharing obtainable solely by
matching the 9fs curves. The current probe used induced
a 20 ns delay in the current waveform in the oscillograms
shown.
Since plotting the entire 9fs curve of each device is very
time consuming, matching VGS(th) or 9FS at some drain
current has been suggested as a simpler criterion for
matching paralleled MOSFETs. While much of the literature suggests the importance of matching VGS(th),
which is normally defined as the minimum gate voltage
at which a small drain current (usually specified as 1.0
mAl begins to flow, this does not accurately indicate the
shape of the 10 versus VGS curve at higher currents.
FIGURE 7-2b -
PARALLELED TURN-OFF
10
2.0 Aldiv
20 p.sldiv
FIGURE 7-2c - COMPOSITE 10 WAVEFORM FOR
TURN-ON AND TURN-OFF
FIGURE 7-2 - INDIVIDUAL 10 WAVEFORMS OF
FOUR PARALLELED MTP8N18 WITH MATCHED
TRANSCONDUCTANCE CURVES RESISTIVE LOAD (DRAIN CURRENT WAVEFORMS
ARE DELAYED 20 ns)
MOTOROLA TMOS POWER MOSFET DATA
1-7-3
20
Devices with 1.0 mA thresholds that vary by as much as
2.0 volts do not usually, but can, have nearly identical
transconductance curves above 100 mAo Conversely,
those devices out of a group of one hundred MTP8N20
found to have the widest variation of 9FS curves had
thresholds that varied by only 4%. Therefore, for optimum
current sharing, the ideal solution is to use devices with
identical curves, and comparing thresholds may not be
the best way to achieve this.
Another simple, yet more consistent, method is to match
devices by comparing the maximum drain current they will
conduct at a gate voltage higher than VGS(th)' For example, all four devices shown in Figure 7-2 conduct an
10 of 4.0 A at a VGS of 6.0 volts and were found to have
nearly identical 9FS curves (Figure 7-3). Though similar
to matching thresholds, this method matches points on
the 9fs curve that are more germane to the intended application of the devices.
VDS=15V
Pulse Width = 80 ~
TJ = 25°C
t8
I
16
I
14
Device #33/
t2
VII!
u;
!!E 10
~
g§ 8.0
z
6.0
.9
2.0
Before any definitive statement may be made concerning the degree or type of matching required for safe
dynamic current sharing, the variation of pertinent device
parameters from lot to lot must be known. Two wafer lots
of the MTP8N20, with sample sizes of 100 and 50 units
respectively, were characterized for this pupose. The
maximum and minimum values of threshold voltage,
transconductance, and on-resistance are shown in Table
1. Figure 7-4 illustrates the widest variation in 9FS curves
within Wafer Lot I and is similar to the results obtained
from Wafer Lot II.
o
FIGURE 7-4 -
VDS = 15 V
Pulse Width = 80 ~
TJ = 25°C
10
;z
~
0
11
WIDEST VARIATION IN TRANSCONDUCTANCE
CURVES FOUND IN WAFER LOT I
After characterization and determining the degree of
variation possible, the effects of matching or mismatching
the critical device characteristics can be observed. The
circuit used for this study is shown in Figure 7-5. Some
of the possible modifications of the circuit include adding
resistors in series with the gate to slow the turn-on and
turn-Off, and a second MOSFET may be included to clamp
the gate bus to ground to observe the effects of very rapid
turn-off.
In this discussion of resistive switching, Figure 7-2 will
serve as a standard for comparisons since matching transconductance curves has achieved such good performance. Extreme care was taken to provide as pure a
resistive load as possible. The 1.6 ohm load was constructed from 39, 62-ohm carbon composition resistors
connected in parallel between two copper plates. Though
the drain wiring and load inductances were very small,
during rapid turn-on, the UR time constant of the circuit
may be the factor that limits the current rise times and not
the switching speed of the MOSFETs.
One of the worst case situations is to parallel devices
with greatly mismatched 9FS curves. Representing the
/
/
1/
12
ii'i
g§
6.0
7.0
8.0
9.0
10
VGS, GATE·TO·SOURCE VOLTAGE (VOLTS)
Required Matching for Safe Levels of Current
Distribution
14
u
5.0
Obviously, the possibility of larger than expected variations in these pertinent parameters diminishes as the
number of sampled wafer lots increases. To get an adequate sampling of available devices, the user could characterize devices with different date codes or obtain units
from several distributors.
16
:::>
~~
4.0
20
ie
:e
sI-
Device #55
//J/
W
JIf
:::>
u
~
t
/W
S
4.0
18
J
J. .J
/1 Device #78
Device #64
Variation of Pertinent Device Parameters
from Lot to Lot
•
-
8.0
.9
6.0
/
4.0
2.0
o
4.0
./
/
Curves for Devices
#35, #52, #53, and #70 are nearly identical
I
/
5.0
6.0
7.0
8.0
9.0
10
11
VGS, GATE·TO·SOURCE VOLTAGE (VOLTS)
FIGURE 7-3 -
TRANSCONDUCTANCE CURVES OF
MATCHED MTP8N20
MOTOROLA TMOS POWER MOSFET DATA
1-7-4
0.02/LF
+20 V
Pulse
Generator
47
51
10
+20 V
51
100
0.001
1.0 k
FIGURE 7-5 -
DYNAMIC CURRENT SHARING TEST CIRCUIT
matched devices in the given circuit poses no significant
reliability hazard.
Matching the 1.0 rnA thresholds does not guarantee the
nearly perfect results of matching the 9FS curves, as
shown in Figure 7-7. Although their thresholds were
matched to within 2%, these devices exhibited a fairly wide
variation in 9FS curves (Figure 7-8) which resulted in
device #45 beginning its turn-off slightly sooner than the
widest variation in the 9FS curves in Wafer Lot I, Figure
7-4 shows the curve of a device that will begin to turn on
with a rising VGS slightly sooner than the other three
devices. It may be expected that device #33 will turn on
first and possibly fail due to current overload. However,
since the variation in the ID versus VGS curves of these
mismatched devices is small, the failure will not occur. As
shown in Figure 7-6, parallel operation of these mis-
ID
2.0 Aldiv
ID
2.0 Aldiv,
50 nsldiv
FIGURE 7-68 -
50 nsldiv
FIGURE 7-6b -
PARALLELED TURN-ON
FIGURE 7-6 - INDIVIDUAL ID WAVEFORMS OF FOUR PARALLELED
MTP8N18 WITH MISMATCHED TRANSCONDUCTANCE CURVES
- RESISTIVE LOAD
MOTOROLA TMOS POWER MOSFET DATA
1-7-5
PARALLELED TURN-OFF
10
5.0 Aldiv
10
5.0 Aldiv
100 nsldiv
100 nsldiv
FIGURE 7-78 - PARALLELED TURN-ON
FIGURE 7-7b - PARALLELED TURN-OFF
FIGURE 7-7 - INDIVIDUAL 10 WAVEFORM OF FOUR PARALLELED
MTPBN1B WITH ~A:i:'~~,J;~~~~OLD VOLfAGES
Waveform/Curve Relations
Note: The order of the device numbers shown in all the current waveforms is important. The first number indicates the upper current waveform
in each group with succeeding curves corresponding to the following device numbers. The order of waveforms is identified to enable the reader
to correlate the devices' performance in the current waveforms to the devices' 9FS curves provided.
•
rest. The waveform photos again indicate that the performance of this group is also quite adequate, For comparison, the devices in Figures 7-9 and 7-10 have fairly
similar 9FS curves even though their 1.0 rnA threshold
voltages vary by as much as 33%. Turn-on times for this
group are almost simultaneous while the turn-off is just
short of ideal.
Because the MTP8N20 of the two wafer lots were so
close in characteristics, the worst conceivable mismatch
that might occur could not be found. In order to study the
effects of such a wide disparity between parameters, an
MTP12N 10 was paired with three closely matched
ID
5.0 Aldiv
VGS
10V/div
50 nsldiv
FIGURE 7-9a - PARALLELED TURN-ON
14~--4----r--~---+~~+----r--~
12
I 10~~--~~~+--+--+-~
~
a
I---~----t--+Af---+--~----t-~
5.0 Aldiv
I 6.0 ~--4----r-Hf-t----+---+----r--~
VGS
5.0 Vldiv
'" 8.0
ID
.P
4.0
~--+----H:f--+----+----t---+---l
Vos ~ 15V
2,0 ~--+--I74----+----l Pulse Width ~ 80 ILS
TJ ~ 25"C
OL-~~
U
U
__-L__ ____L -__
U
M
U
U
~
~
50 nsldiv
__-L__~
m
FIGURE 7-9b - PARALLELED TURN-OFF
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
FIGURE 7-11- TRANSCONDUCTANCE CURVES OF MTPBN20 WITH
MATCHED THRESHOLD VOLTAGES
FIGURE 7-9 - INDIVIDUAL ID WAVEFORMS OF FOUR MTPBN20 WITH
MATCHED TRANSCONDUCTANCE CURVES AND MISMATCHED
THRESHOLD VOLTAGES
MOTOROLA TMOS POWER MOSFET DATA
1-7-6
TABLE 3 -
Parameter Comparison of One MTP12N10 and Three MTP8N20s
VGS(th)
10
1.0 mA
(Volts)
9fs
10
4.0 A
VGS
15V
(Volts)
Crss
(pF)
=
=
Device
Number
Oevice
Type
rOS(on)
10
4.0 A
(Ohm)
#122
MTP12N10
0.145
3.600
4.300
#52
MTP8N20
0.238
3.955
4.762
#53
MTP8N20
0.256
3.900
#70
MTP8N20
0.255
3.930
=
J
12
10
j
t-
Z
g§
=>
8.0
z
:;;:
Cl
1/
}
u
'"
.'"
6.0
.9
VDS = 15 V
Pulse Width = 80 ~
TJ = 25°C
I
r.J.
4.0
j
2.0
o
4.0
o = Device #108
l
6.0
I
I
I
I
7.0
8.0
9.0
10
/
14
MTP12N10
Device #122
12
~
8.0
=>
u
z
~
6.0
4.0
4.0
5.0
220
4.444
45
700
245
4.444
45
700
235
6.0
ID
2.0 Aldiv
50 nsldiv
FIGURE 7·12a - PARALLELED TURN·ON
/
Coincident 9FS Curves
of the MTP8N20
_
Devices #52, #53, and #70
ID
2.0 Aldiv
VGS
5.0 V/div
VI
V
lh
o
395
700
/
//
Cl
1.0
:/
I
II
/
10
5
::
685
45
VGS
5.0 V/div
FIGURE 7-10 - TRANSCONDUCTANCE CURVES OF MTP8N20 WITH
THRESHOLD VOLTAGE VGS(th) MISMATCH
~
90
~.750
VGS, GATE·TO·SOURCE VOLTAGE IVOLTSI
0
U)
z
~
6.0
11//
0
.9
4.0
I) V
1.0
o
u
~V
U
TJ
U
Protecting the Circuit From Self-Induced
Oscillations
VDS=15V
Pulse Width = 80 IJoS
M
U
=rc
U
Two of the most highly esteemed characteristics of the
power MOSFET can combine to cause a problem in paralleled devices. Their high input impedance and very high
frequency response may cause parasitic oscillations at
frequencies greater than 100 MHz. This problem occurs
when all gates are driven directly from a common node
as in the circuit in Figure 7-19. Without individual gate
I
W
VGS. GATE·TO·SOURCE VOLTAGE IVOLTS)
FIGURE 7-16 - WIDEST VARIATION IN TRANSCONDUCTANCE
CURVES OF 250 ADDITIONAL MTP8N20
10
2.0 Aldiv
10
2.0 Aldiv
VGS
10V/div
VGS
5.0 V/div
100ns/div
200ns/div
FIGURE 7·178 - RAPID TURN-ON SUPPLYING REVERSE
RECOVERY CURRENT OF FREEWHEELING DIODE
10
2.0 Aldiv
FIGURE 7-17b - SLOW TURN-ON SUPPLYING REVERSE
RECOVERY CURRENT OF FREEWHEELING DIODE
10
2.0 Aldiv
VGS
5.0 Vldiv
VGS
5.0 V/div
20ns/div
FIGURE 7-17c -
200ns/div
RAPID INDUCTIVE TURN-OFF
FIGURE 7-17d -
FIGURE 7-17 - INDIVIDUAL ID WAVEFORMS OF MISMATCHED
MTP8N20 SWITCHING AN INDUCTIVE LOAD
MOTOROLA TMOS POWER MOSFET DATA
1-7-10
SLOW INDUCTIVE TURN-OFF
ID
2.0 Aldiy
ID
2.0 Aldiy
VGS
10Vldiy
VGS
5.0Vldiy
50 nsldiy
50 nsldiy
FIGURE 7-188 - TURN-ON
FIGURE 7-18b - TURN-OFF
FIGURE 7-18 - EFFECTS OF IMBALANCED SOURCE INDUCTANCES ON
PARALLELED PERFORMANCE
resistances a high-Q network (Figure 7-20) is established
that may cause the device to oscillate when operating in
or switching through the active region. The device trans'conductance, gate-to-drain parasitic capacitance, and
drain and gate parasitic inductances have all been shown
to influence the stability of the circuit.
Although potentially serious, this problem is easily
averted. By decoupling the gates of each device with lossy
elements such as resistors or ferrite beads, the Q of the
circuit can be sufficiently degraded to the point that oscillations are no longer possible (note dotted resistors
shown in Figure 7-19). For the maximum switching
speeds, the value of gate decoupling resistors should be
kept as low as safely allowable. A value in the range of
10 to 20 ohms is generally sufficient.
A Practical Application Load
shown in Figure 7-21. At a 50% duty cycle and a VOO of
44 V, the MOSFETs delivered about 450 W to the RC
load. To minimize the power that the drain-source zener
clamp must dissipate, MOSFET turn-off speed was limited
by the placement of an 82 0 resistor in series with each
gate.
Again, the performance of interest is that of mismatched
devices. In this case, fifty units from a newly designed
mask set were tested for the widest variation in onresistance (0.255 0 to 0.230 0). The three highest
rOS(on) devices were grouped with the lowest rOS(on)
unit. Since a low fOS(on) usually indicates a high 9FS,
the transconductance curves of these devices were also
mismatched.
The degree of current sharing among these four units
was well within safe operating limits. As expected, the
lowest rOS(on) device carried the greatest on-state current. For clarity, only the on-state currents of the lowest
and highest rOS(on) units are shown in Figure 7-22. The
currents of the other two devices were nearly identical to
device #8. As Figure 7-23 shows, the drain current of the
lowest rOS(on) device, #11, peaked slightly due to its
different 9FS curve.
An Inductive
To show the feasibility of paralleling power MOSFETs
in an application that imposes stresses typical of an inductive load, four MTP8N20's were paralleled in the circuit
Drain Bus
voo
Gate
Drive
Input
Source Bus
FIGURE 7-20 - PARASITIC HIGH-Q EQUIVALENT CIRCUIT
OF PARALLELED MOSFETs WITHOUT GATE DECOUPLING
RESISTORS
FIGURE 7-19 - METHOD FOR DRIVING PARALLELED MOSFETs
USING GATE DECOUPLING RESISTORS
MOTOROLA TMOS POWER MOSFET OATA
1-7-11
•
+12 Volts
68
+~
Pulse
Generator
MUR830A
150 pF
75!l
2.7 k
.,..
MTP
8N20
82!l
(4)
2.2 k
510 pF
2.7
.,..
15!l
1.0kW
1500
I'F
1.0 k
.,..
470
(4)
VZ=150V
.,..
18!l.2.0W
MJE200
,
MDS51A
lN914
56
1.0 k
+ 12 Volts
FIGURE 7-21 -
•
CURRENT SHARING TEST CIRCUIT WITH AN INDUCTIVE LOAD
1. For static current sharing, the current mismatches
are determined by the rOS(on) mismatch. A small
degree of guardbanding or rOS(on) matching will
ensure safe operation.
Each device was mounted on a separate heat sink. and
the case temperatures were monitored to detect any thermal imbalances. Because of its low rOS(on). theory predicts that the case temperature of device #11 will be
higher than the others. However, since the operating frequency was fairly high (40 kHz), the difference in switching
losses may haVe also influenced the temperature comparison. Whether it was due to a variation in rOS(on) or
9fs curves, the temperature difference was very small
(54.3°e for device #11 and 52.3°e for device #8) and did
not significantly affect device performance, i.e., the degree
of current sharing.
The following is a summary of recommendations and
findings concerning static and dynamic current, sharing
in paralleled power MOSFETs.
2. For dynamic current sharing, the turn-on and turnoff waveforms are largely determined by the transconductance curves. If matching is deemed necessary in a particular application, selecting devices
by comparing 9FS curves is the most accurate approach. A simple, yet adequate, substitute is to
match a single point on the 9FS curves at which the
devices conduct significant drain currents.
3. Increasing the switching speeds in symmetrical circuits tends to equalize the rate of current rise and
#8
#8
#11
#11
#8
#8
100 ns
5.0 p.S
FIGURE 7-23 - ID TURN-OFF WAVEFORMS OF LOW
AND HIGH rDS(on) DEVICES - INDUCTIVE LOAD
PlQURE 1-22 - ID WAVEFORMS OF LOW AND HIGH
rDS(on) DEVICES - INDUCTIVE LOAD
MOTOROLA TMOS POWER MOSFET OATA
1-7-12
fall in paralleled devices due to the ballasting effect
of the parasitic source inductance.
voo
4. The circuit layout should be as symmetrical as possible with respect to the gate-drive and the source,
gate, and drain parasitic inductances.
5. In all applications, the gates should be decoupled
with small resistors or ferrite beads to eliminate parasitic oscillations.
Drain-to-Source Diodes
The previous text on paralleling power MOSFETs has
shown the effects of parameter matching (or unmatching)
on the degree of current sharing when the FETs are operating in either switching or linear applications. However,
it has not described the effects on the paralleled drainsource diodes when these diodes are used as clamp or
free-wheeling diodes in practical applications. These
diodes can be used in multi-MOSFET switching applications (see Chapter 12 on characterizing D-S Diodes) when
the diode switching speeds are commensurate with the
application. In a half bridge, as an example, the diode of
one FET protects the drain-source of the second FET and,
conversely, the diode of the second FET protects the first
FET. Whatever the circuit configuration, the equivalent
circuit reduces to that of a clamped inductive load,
whereby the drain-source diode is effectively across the
load inductance (Figure 7-24).
When power MOSFETs are paralleled in switching applications, the question arises as to how well their intrinsic
diodes share the clamped current. To determine this, three
MOSFETs were paralleled in the circuit shown in Figure
7-25. The test circuit (a complete schematic is shown in
Figures 12-19 of Chapter 12) was duty cycle controlled
to produce a continuous load current; thus, the commutated diode current indicated both the reverse recovery
time trr and turn-on time ton. The individual and total diode
currents, as well as the driver drain current, were
monitored.
o':s-LJ
FIGURE 7-24 - INTRINSIC D-S DIODE
CLAMPING AN INDUCTIVE LOAD
To obtain some indication of a worst case condition, a
modest sample (20 pieces) of MTM20N15 were characterized for parameters that affect their paralleled perlormance. The forward on-voltage of the diodes at 10 A
ranged from 1.05 to 1.20 volts, and trr varied from 0.25
to 0.32 JLs. Devices with the widest mismatch in parameters were grouped and tested in the circuit shown in Figure
7-25.
Testing indicated that current mismatches were small,
even in devices with the greatest difference in D-S diode
on-voltage. Figure 7-26 shows the current waveforms of
voo
FIGURE 7-25 - TEST CIRCUIT TO OBSERVE
CURRENT SHARING OF PARALLELED D-S DIODES
MOTOROLA TMOS POWER MOSFET DATA
1-7-13
•
Paralleling Power MOSFETs in
Linear Applications
5.0/Lsldiv
FIGURE 7-26 - DRAIN-SOURCE DIODE ON
CHARACTERISTICS OF THREE MTM20N15
WITH MISMATCHED e.S DIODE ON-VOLTAGES
three paralleled diodes and the expected mild mismatch.
Also shown is a representation of ITOTAL, which is somewhat distorted due to the saturation of the current transformer that was used.
Current waveforms of devices with the widest variation
in trr are shown in Figure 7-27. Again, even though the
diodes are mismatched, the synchronized turn-on and
turn-off transitions illustrate the high degree of current
sharing that occurs as the load current is commutated
between the freewheeling diodes and the drive transistor.
Often lauded for their efficient high frequency switching
capability, power MOSFETs are ideally suited for a myriad
of switching applications. However, some of their other
less renowned characteristics also make them attractive
to designers of linear systems. Often the reason cited for
their use is the inherent ruggedness of the MOSFET as
evidenced by the lack of a second breakdown derating.
Another characteristic that is appealing is the high input
impedance that results in simplified gate-drive circuitry.
Also, the transconductance is nearly linear over a wide
operating range and its variation among devices in a given
product line is small.
Although these benefits are significant, a method of
predicting and stabilizing the operating point is necessary
before linear operation can be successful. In the following
sections a product line is characterized for the parameters
pertinent to Q-point variation in the linear mode. The effects of a source reSistor on the operating point and the
small-signal transconductance are then discussed for single device operation. Finally, these concepts are extended
to include the case of paralleled devices with special attention paid to the degree of current sharing.
Device Characteristics Important for Operating
Point Stability
When developing a system that operates in the linear
mode, it is often either desirable or imperative to accurately fix the system quiescent operating point (Q-point).
The most pertinent graphs describing the operation of
TMOS Power MOSFETs in the linear mode are those
showing the output characteristics (Figure 7-28) and the
transfer characteristics, or transconductance curves (Figure 7-29). However, since these are typical curves, they
16
VGS" 20 V lOV.
TJ
IDIDDE
~ ~vGS" 8.0 V
hI"
/h Y
=25°C
5.0 Aldiv
-/ /
-T ~ , /
/r
~
,.
o
). ~
FIGURE 7-27 - PARALLELED DIODE TURN-ON AND
TURN-OFF OF MTM15N20 WITH MISMATCHED trr
66 v-
2.0
40
60
80
Vos. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
FIGURE 7-28 -
0.5 iLsIdiv
I
5L-
TF
o
T
70V
10
TYPICAL OUTPUT CHARACTERISTICS
OF AN MTPBN20
relate no information concerning how the operating point
may vary within a given product line. For example, on the
transfer characteristics curve a desired quiescent drain
current of 4.0 amps may correspond to a gate-source
voltage of 5.75 volts in a typical device. This gate voltage
applied to an atypical device of the same product line may
result in a drain current that ranges from 2.5 to 4.5 A.
MOTOROLA TMOS POWER MOSFET DATA
1-7-14
Matching device parameters is often proposed as a
means of ensuring some minimum variation in the Q-point.
This approach, especially using the threshold voltage, is
not the optimum solution. The gate-threshold voltage is
defined as the minimum gate-source voltage at which the
MOSFET conducts some small drain current, usually
specified as 1.0 mAo On the scale that the transfer characteristics are usually drawn, this 1.0 mA drain current is
very small and the exact threshold voltage is indiscernable. It is not difficult to find two devices with nearly identical transfer characteristics that have thresholds that vary
by nearly 2.0 volts. Conversely, devices with matched
thresholds can have significantly different transfer curves,
usually due to a 9FS mismatch. Attempting to match devices by comparing transconductance or on-resistance
also gives little assurance that the transfer curves will be
similar.
If component screening is desired, the most direct
method is to actually compare each 10 versus VGS curve.
Since this is often impractical, one of two other courses
may be taken. The criteria for matching could be the drain
current at the gate voltage that is typical of the desired
quiescent current. Referring back to the previous example, one may select devices on the basis of 10 at a VGS
of 5.75 volts. The other solution, which completely eliminates any device screening, involves the use of source
resistors and is detailed in the next section.
Junction temperature is another important variable that
influences the quiescent operation point. Figure 6-25
shows that the 9FS curve of the MOSFET can be divided
into two regions. Below a VGS of 6.1 volts, an increase
in TJ increases '0. This is due to the negative temperature
coefficient of VGS(th) dominating the positive coefficient
of rOS(on)' As TJ rises, the threshold voltage falls and 10
increases despite an increase in rOS(on)'
16
Vos= 10V
r-
TJ = -55°C
Using a Source Resistor to Stabilize the Q-Point
Operating point stability can be improved without preselecting devices by using a source resistor. The placement of such a resistor provides degenerative feedback
to the gate by decreasing VGS by an amount proportional
to the drain current (Figure 7-30). Equations for the smallsignal transconductance and voltage gain with and without
the source resistor are derived in Table 4.
Determining the effect of a source resistor on the operating point of a power MOSFET is a simple geometric
exercise. The first step is to obtain, usually with a curve
tracer, the transconductance curve of the device in question. With no source resistance (RS = 0 0), a vertical
vGS = vGG - IDRS
FIGURE 7-30 -
TABLE 4 - Equations for the Small-Signal
Transconductance and Voltage Gain With and
Without a Source Resistor
With No
Source RHIitor
II :/
I/o
Smail-Signal
Transconductance
II;
9FS=~
<1VGS
<1VGG
A _ -<1VOS
y- <1VGS
A
/II
20
Small-8ignal
Voltage
Gain
40
6.0
8.0
VGS, GATE-TO-SOURCE VOLTAGE (VOLTSI
9FS I<1VGG-<110RS)=<110
9FS <1VGG = <11011 + RS9FS)
9'FS=~=~
1/1
~~
WrthA
Source Re.istor
9FS=~
<1VGS
100'oc
irf. If
25°C
SOURCE RESISTOR SUPPLIES NEGATIVE
FEEDBACK TO THE GATE
10
= -<110 Rl
<1lo19FS
:.Ay = -9FS Rl
VOOJ Rl
FIGURE 7-29 - TYPICAL TRANSCONDUCTANCE
CURVES OF AN MTP8N20
Circuits
At gate-to-source voltages greater than 6.1 volts, the
temperature dependence of rOS(on) governs the change
in '0. Even though VGS(th) is failing as TJ rises, the effect
of the increase in rOS(on) begins to dominate, causing
ID to decrease. The temperature dependence of ID necessitates the consideration of the effect that TJ has on
the Q-point, especially at low drain currents where the
percentage change in 10 is high.
VGG=v~q
I+RSg'FS
A'y= -9FSRl
= -Rl9FS
1+9FS RS
'A'=~
y 119FS+RS
..
VOOJ
VGGJ
+
Rl
1
VGS-~
RS
Primed numbers indicate the effective values for the MOSFET and
source resistor combination.
line through the 9FS curve will indicate the drain current
at a given VGS- For instance, the device depicted in Figure 7-31 will conduct 0_375 A at a VGS of 4.7 volts.
MOTOROLA TMOS POWER MOSFET DATA
1-7-15
If a source resistor is included, the abscissa represents
the gate-to-ground voltage (VGG). The relationship between VGG and 10 is determined by an RS load line
through a given VGG with a slope of -1/RS. Figure 7-31
shows that for an RS of 2.0 n and a VGG of 5.45 V,
the a-point is fixed so that 10 is still 0.375 A. The effects
of varying the gate-to-ground voltage can be determined
by constructing parallel lines through the gate voltages of
interest. Changing the slope of the line graphically models
changes in RS.
To use the technique of employing a source resistor to
improve a-point stability, the worst case variation in the
9FS curves needs to be determined for the product line
in question. For this study, 350 MTPBN1B's from the same
wafer lot were checked for the greatest difference in transconductance curves. The results are shown in Figure
7-32. With these curves, actually sizing RS and determining the gate voltage for a desired operating point (with
a defined allowable variation) is a very simple geometric
exercise.
Assume that the desired conditions are as follows:
1.4
1.3
r-
DEJICE ~loi
TJ = 100'C J
I
I
DEVICE #108
251'C 1-
1.2
I TJ
1.1
I
1.0
~
0.9
I
~
!z 0.8
a
~
I
I
~ 0.6
~ 0.5
U
I
I
/
J
I
I
;<
m~
-O.375~
-lIRS
~RS = 2.6711
A'/
/'u
DEVICE #106_
I TJ = 25'C
II/
"R
/
0.3
o
I dEVIC~ #1106II TJ = l00'C r-
I
~I
0.4
0.1
r-
I
0.7
0.2
I
I
I
i
/
u
u
N
~
M
VGG, GATE-TO-GROUND VOLTAGE (VOLTS)
10 quiescent = 0.4 A
FIGURE 7-32 - USING A SOURCE RESISTOR
TO STABILIZE THE QUIESCENT OPERATING POINT
Allowable 100 variation from 0.4 A is 0.05 A
•
TJ = 100°C
An RS load line drawn through paints A and Band
extending down to the gate voltage axis determines both
the required magnitude of RS and the quiescent gate
voltage. The figure could also be used to show the effects
of swinging the gate voltage above and below the quiescent VGG. The dashed curves in Figure 7-32 represent
the transfer characteristics at a junction temperature of
25°C. Obviously, the curves vary enough to influence the
selection of RS if the device experiences large swings in
TJ.
1.4
I I
1.3
VDD
1.2
= 15 VOLTS
I
1.1
I
1.0
II
u;
~
DEVICE #10~ _
TJ = l00'C
0.9
~
... 0.8
~
§
u
z
~
.9
I
0.7
/
0.6
II
0.5
0.4
0.3
L
0.2
O. 1
o V
4.0
'\
m = -1/2 = -I/R
,)lR = 2.on
RS = on
I '\l5.45V
4.8
5.2
5.6
r
4.4
6.0
VGG, GATE-TO-GROUND VOLTAGE (VOLTS)
FIGURE 7-31 - GRAPHICAL METHOD OF
PREDICTING THE EFFECT OF A SOURCE RESISTOR
ON THE QUIESCENT OPERATING POINT
Paralleling MOSFETs in the Linear Mode
In many applications using MOSFETs in the linear
mode, the quest is to obtain large swings in the load
voltage and utilize as much of the maximum drain-tosource voltage rating as possible. With a large quiescent
drain voltage, 100 must be fairly small to keep the
MOSFET power dissipation within manageable levels_
Unfortunately, paralleling in the linear mode at a low
100 and a high Vosa is not as straightforward as paralleling in switching applications, for instance. Since this
is the most difficult and most common case of paralleling
in the linear mode, it is the one that is addressed here.
One problem is that at low currents the potential 10
mismatches, as a percent of the total load current are
much greater. As an illustration, one device may conduct
0.3 A at a VGS of 5.0 V, whereas a second device may
conduct 1.25 A at the same VGS. If these two devices
are operated in parallel in the linear mode, the second
would dissipate far more power than the first. Unlike
MOSFETs that are paralleled in switching applications,
the difference in junction temperature forces an even
greater disparity in the amount of current each device
conducts.
As explained earlier, at low drain currents the temperature dependence of the drain current is dominated by
the negative temperature coefficient of VGS(th) rather
than the positive coefficient of rOS(on)' Consequently, the
device that is dissipating the most power will heat up,
carry more current and diSSipate even more power.
Although the situation appears to be hopeless - very
wide variations in 9FS curves causing even greater differences in power dissipation - the use of source resistors can minimize the differences and dramatically improve the chance of success_
MOTOROLA TMOS POWER MOSFET OATA
1-7-16
Using a source resistor to stabilize the operating point
of devices with widely differing 9FS curves is also applicable to improving current sharing among MOSFETs operated in the linear mode. If the Q-points are closely
matched, then the paralleled devices will, by definition,
carry nearly the same drain currents and incur approximately the same power dissipation.
In this study, the devices with widest variation in 9FS
curves were paralleled in the circuit shown in Figure
7-33. Individual source resistances of 3.3 n were chosen
as a good compromise between a stable Q-point and the
lower system gain are poorer efficiency attributable to an
increase in RS. Table 5 establishes the equations for 9fs
and small signal voltage gain of paralleled MOSFETs with
and without source resistors.
Figure 7-34 shows the results of pairing the devices
with the widest mismatch in 9FS curves. Note how the
drain currents can be predicted by relating the 9FS curves
(Figure 7-35) to the instantaneous gate voltage. Case
temperatures were also monitored, but the difference was
not as great as expected. While the device that carried
the most current ran hotter, it did so by only a couple of
degrees (83 versus 85°C). A difference of 5 to 10°C was
expected but did not materialize, most likely due to slight
variations in the heat sinks. The MOSFETs were mounted
on separate heat sinks, again to simulate a worst case
condition. Close thermal coupling by placing units on the
same heat sink is recommended to minimize variations in
TC and TJ and therefore decrease any thermally induced
differences in 9FS curves.
The benefits of device matching are shown in Figure
7-36. The nearly identical drain currents were obtained
by matching devices by comparing the drain currents they
would conduct at a VGS of 4.7 volts and a junction temperature of 25°C. The slight mismatch at higher drain currents is mainly due to a small difference in 9FS curves at
a TJ of 100°C. The case temperatures of these two devices were essentially identical. The 20 n gate resistors
Voo =
62.5
110V
n
100W
VGSQAdjust
FIGURE 7-33 - CIRCUIT TO TEST CURRENT SHARING IN PARALLELED
MOSFETs OPERATING IN THE LINEAR MODE
TABLE 5 - Equations for the Small-Signal Transconductance and Voltage Gain of Two
Paralleled MOSFETs With and Without Individual Source Resistances.
With No
Source Resistors
With Individual Source
Resistors, RS
9FS1(£1VGS1) = £1I01,9FS2(£1VGS2) = £1102
£11
Small-Si9nal
Transconductance
= 9FSI £11
= 9FS2
01
£1VGS' 02
£1VGS
£1101 + £1102 =
9FSH 9FS2
£1VGS
9FSI + 9FS2 = £1101 + £1102
£1VGS
Av =
Small-Si9nal
Voltage Gain
9FSI (£1VGG - £1101 RS) + 9FS2(£1VGG - £1102 RS) =
£1101 + £1102
9FSI (£1VGG) +9FS2 (£1VGG) = £1101 11 +9FSI RS)
+ £1102 (1.0 +9FS2RS)
(9FS1+9FS2)(£1VGG)=(£1101 + £1102)(1.0 +9FSRS),
9FSI + 9FS2
where 9FS=
2
:. 9FST = 9FSI + 9FS2
.
£1IT. 9FSI + 9FS2
:.9 FST= £1VGG = 1.0 +9FSRS
-£1VOS
£1VGS
A'vT = - 9'FST RL
-R!.(9FSI +9FS2)
=
1.0 +gFS RS
= -£1IDTR!.
£1IDTi9FST
:. AvT = - 9FST RL
Pnmed variables indicate the effective value for the MOSFET and source reSistor combmatlon.
Subscript "T" indicates the total value for aU MOSFETs in parallel.
MOTOROLA TMOS POWER MOSFET DATA
1-7-17
In conclusion, the same method used to stabilize the
operating quiescent point of small signal MOSFETs can
be easily extended to linear applications of power
MOSFETs. After sampling a product line to obtain the
widest expected variation in 9FS curves, a simple graphical
technique can be used to accurately predict the o-point associated with a given source resistor and gate-to-ground voltage.
Since small variations in a-point limit possible variations
in drain current, successful paralleling is also achievable
with this same method. The only additional consideration
is the need to limit potential self-induced oscillations with
individual gate suppression resistors.
VGG
1.0Vldiv
10
0.1 Aldiv
Vos
VGG
1.0 Vldiv
20 Vldiv
10
0.1 Aldiv
2Op.S
FIGURE 7-34 - VGG, 10 AND VDS WAVEFORMS OF MISMATCHED
MTP8N20 PARALLED IN THE LINEAR MODE RS
3.3 0
=
1.0
09 c-- DEVICE
.
#108
0.8
0.7
'0] '0]-
./
0.1
0
4.0
DEVICE #106
-[--I. 11
-Ii· .~
...
/
0.3
0.
Ves
II
;~
"'
4.4
...
r--.
J
I'-.
...
4.8 •
5.2
TJ = l00'C
RS = 3.3!l
...
20 p.S
...
......
5.6
20 Vldiv
-
6.0
FIGURE 7-36 - VGG, 10 AND VDS WAVEFORMS OF MATCHED
MTPBN20 PARALLELED IN THE LINEAR MODE RS = 3.3 0
...
6.4
'~~~
I
6.8
I
I
FIGURE 7-35 - TRANSFER CHARACTERISTICS AND
RS LOADLINE OF MISMATCHED MTP8N18
in Figure 7-33 serve an important function. The high input
impedance and high frequency capabilities of the
MOSFET present the possibility of self-induced oscillations in paralleled devices. .Inserting small resistances in
series with each gate defuses the problem by degrading
the a of the LC network formed by the gate-and-drain
inductances and the MOSFETs gate-to-drain capacitance. The magnitude of RS necessary to allow troublefree operation depends on the value of each of the circuit
parasitics. The circuit in Figure 7-33 oscillated with series
gate resistances of 10 n, but stabilized with 20 n. Increasing RS results in a more stable circuit at the expense
of lower bandwidth.
Applications of Paralleling MOSFETs
Paralleling Power MOSFETs in a Very Fast, High
Voltage High Current Switch
There are many applications requiring an extremely fast
high voltage, high current semiconductor switch, especially for device characterization, where the switch must
be much faster than the device under test (OUT). Power
MOSFETs serve this function extremely well, but they are
presently limited in current capability. However, they can
be readily paralleled to increase the current, without using
current sharing ballast resistors, due to the inherent positive temperature coefficient of the drain-source ON-resistance rOS(on). For example, if the transconductance
9FS of the FETs are unmatched, the FET with the highest
9FS would tend to take initially the largest drain current,
but due to the greater dissipation (l 2 rOS (on)) and resuiting temperature rise, rOS(on) would increase, thus,selflimiting the current. This process tends to equalize the
drain currents of the respective devices.
o
MOTOROLA TMOS POWER MOSFET OATA
1-7-18
A circuit for generating this fast pulse is shown in Figure
7-38. It uses 15 N-Channel power MOSFETs in llfarallel
as the output power switch to achieve the system capability of 150 A of peak, pulsed current. The FETs used
were unmatched TO-220 MTP5N40(2.7 V < VGS(th) <
3.9 V) with 400 V blocking capability V(BR)DSS, 5.0 A
continuous drain current rating (lOA pulsed) and specified
rDS(on) of 1.0 n max. The TO-220 devices lend themselves to efficient circuit layout and packaging (Figure
7-37).
The particular application for which this circuit was designed required the DUT to be referenced to ground (drain
circuit); consequently, the switch is powered with a negative, high voltage supply (- Vss) tied to the FETs
sources. Thus, the ground referenced pulse generator
output must be level translated to this negative supply.
For fast switching, this translator must have the current
drive capability for quickly charging the power MOSFETs
input capacitances Ciss and reverse transfer capacitance
Crss . To accomplish this, two P-Channel MTP2P45's are
PARALLELED MOSFETs
FIGURE 7-37 - BREADBOARD LAYOUT OF THE SWITCH
ILLUSTRATING TIGHT PACKAGING CONCEPTS
220
20V
1.0W
1 N4747
MTP2P45
017
(216)
200 II
2.0W
100
"t J"
RL
0.9 II
430W
0001
C2
005
100
R2
-160V
RO
~
01
MTP
5N40
MTP5N40
alB
20V
1.0W
1 N4747
-------
I-
015
MTP5N40
(2)
20V
lOW
lN4747
001
270
-Vss
0.01
60 I'F::r: +
350V _
::r:
-
FIGURE 7-38 -
6Ol'F
350 v::r:+
PARALLELEtl POWER MOSFETs 150 A SWITCH
MOTOROLA TMOS POWER MOSFET DATA
1-7-19
-160V
::r: +
-
•
configured as a parallel connected, series switch. These
FETs are turned on by the negative going input pulse
derived from a 50 V, 10 ns rise time pulse generator. A
20 V zener diode is used to protect the gate-source and
still allows adequate gate-drive for rapid switching of the
drain circuit. Connected to the drain is a current limiting
resistor R2 (with speed-up capacitor C2) feeding the 15
respective gate circuits (only circuits 1 and 15 are shown);
each circuit consists of a direct-coupled resistor, speedup capacitor and protection zener diodes. The zener
diodes come into operation when high VSS (-160 V) is
used. When VSS is reduced to as low as 40 V, the gatedrive voltage dividers still provide adequate drive. For low
duty cycles « 1.0%), the resistors can be relatively low
wattage. The circuit can be operated within the blocking
voltage capability of the FETs (to 400 V), but the passive
circuit elements should be scaled up accordingly.
To improve the turn-off switching times of the power
switch, the FET capacitance must be quickly discharged.
This is accomplished by the N-channel FET clamp 018
which, when turned on, supplies the reverse gate voltage
to the power switch through the voltage storing effect of
C3 across R3. FET 018 is turned on coincident with the
trailing edge of the input pulse by means of the differentiating network C1-R1, the derived positive-going pulse
supplying the gate-drive and duration for the clamp action.
The complete pulse-width voltage and current waveforms are shown in Figure 7-38 with the time expanded
turn-on and turn-off waveforms shown in Figures 7-39 and
7-40.
For these test conditions (VSS = -160 V, R1 = 0.93 n),
approximately 150 A at 140 V (21 kW peak) was switched
in extremely fast times; the voltage turn-on time was less
than 10 ns and the current rise time being circuit inductance limited to about 250 ns.
Without the turn-off clamp circuit of 018 the drain voltage (and resistive load drain current) turn-off time was
about 1.0 J.Ls (Figure 7-41 a) due to the time required to
discharge the FET's capacitances.
With the clamp, this time can be substantially reduced
(0.2 J.Ls) as shown in the photos of Figures 7-41b and
7-41c, the capacitance discharge limiting resistance RD
being 10 nand 5.0 n respectively. As this resistor value
is decreased, the FET will turn~off faster, but consequently
be subjected to greater switching perturbations (Figure
7-40, RD = 0). Thus, the turn-off characteristics can be
somewhat tailored to the requirements.
Care should be exercised in the layout of the fifteen
parallel FET's, especially with the gate-source drive circuitry. The fifteen FET's are mounted side-by-side with
the gates and sources tied to their two respective, parallel
run busses (Figure 7-37). Device lead lengths should be
made as short as possible and the source buss should
be RF by-passed at several pOints along its length to
minimize reactive effects.
Obtaining high power resistive loads with low inductance is a problem. For a pulsed current of 150 A and a
low resistance of about 0.93 n, the peak power would be
about 21 kW. Obviously, the duty cycle has to be very low
for this application to avoid overheating the load resistor.
This resistor was fashioned with 216,200 n, 2.0 W, metal
oxide resistors sandwiched in parallel. This resulted in a
load resistor of approximately 430 W capability. Therefore,
0-
Vo
50V
Div
10
50A
Div
0-
FIGURE 7-38 -
SWITCHED VOLTAGE AND CURRENT
0-
Vo
50V
Div
10
50A
O,v
50 ns/O,v
FIGURE 7-39 -
TURN-ON DRAIN VOLTAGE AND CURRENT
0-
Vo
50V
O,v
10
50A
Div
0-
50 ns/O,v
FIGURE 7-40 -
MOTOROLA TMOS POWER MOSFET DATA
1-7-20
TURN-OFF WITH CLAMP, RD
= 0
-
FIGURE 7-418 -
TURN-OFF DRAIN VOLTAGE RD
=
0
-
FIGURE 7-41b -
00
TURN-OFF DRAIN VOLTAGE RD
0
= 10 n
-0
Vert. = 500 V! D,v
Honz ::; 500 ns/Dlv
FIGURE 7-41c -
TURN-OFF DRAIN VOLTAGE RD
duty cycles of less than 1.0% should be used to ensure
operation within the load rating while still offering good
oscilloscope viewing.
= 5.0 {)
critical, especially for some power MOSFETs. This complementary switch, with dv/dt adjustment and control of
the dead time, can help determine the capability of power
FETs in circuits when the above conditions are important.
Fast, Complementary Power MOSFET
Switch
Circuit Configuration and Operation
Two CMOS Quad 2 input NOR gates (MC14001) are
used for pulse generation and signal delay. Gates A1 and
A2 are configured as an astable multivibrator (MV), clocking the respective delay and pulse width monostable
MV's. The turn-on pulse is frequency (R1) and width adjustable (R4) whose output feeds, in order, cascaded
bipolar transistors QS, Q6, power FET Q7 and the NChannel output switch Q8.
Pulse delay (R2) and width control (R3) for the PChannel switch (Q4) are obtained with Gates 61, 62, 63
and 64 which drives two cascaded bipolar transistors Q1,
Q2 and power FET Q3.
Transistor Q9 drives power FET Q10 as an optional
clamp to tum-off Q8 rapidly by discharging gate capacitance through a low impedance path. Duration of the
clamp interval is dictated by the RC differentiating circuit
in the base of Q9.
The complementary output FETs Q4 and Q8 consist of
four P-Channel (MTP8P10's) in parallel and four NChannel (MTP20N10's) in parallel. A limiting resistor RD
is shown in the drain of Q8 but may be in the drain of Q4
or in both drains. The external load may be a test rectifier
or any other load requiring the unique drive characteristics
of this tester: fast, adjustable, complementary waveforms.
Many present day semiconductors require test circuits
that can supply large pulsed currents and fast voltage
transitions.
In today's real world circuits, rectifiers are vital components in motor controls and in switching power supplies
as the operating frequency and power level increases.
Rectifier characteristics and selection can be critical for
these applications.
Due to its fast switching speed, the complementary
power FET switch, shown in Figure 7-42, is useful in measuring forward (tfr) and reverse (t rr) recovery times of fast
recovery rectifiers, as well as for general uses requiring
a complementary power signal.
The internal collector-emitter diode in power Darlington
transistors and the drain-source diode in power FETs can
be of great interest to the circuit designer. Rectifier operation is dependent on several conditions, two of which
are the tum-off rate (dildt) of forward current and the rate
of rise (dv/dt) of the reapplied blocking voltage.
In some switching power supplies, a designed-in dead
time is required between the switching transistors to avoid
simultaneous conduction. The duration of the dead time
and the dv/dt of the reapplied blocking voltage can be
MOTOROLA TMOS POWER MOSFET DATA
1-7-21
I
V+ '" 50V
20V
+15V
220
+15V
R3
Q2
Q40
100
200 pF
~I+15V 10 k
s::
- - - , OUT
4,.-
I
tp(off)MV
lOkI
1
4,.
100
470
2N
*
RL
f
~
u~
@
~
6
s;
B2
IFM
4
+15 V
-I
s::
,
,
-=-
oen
~
Delay MV
470
RO
"U
..... 0
N ::E
N m
Q7
+15 V
:D
5
s::
oen
Off
1ampcr
"'T1
~
-=-
C
»~
200 pF
10 k
MTP8Pl0
27
*Ferrite
Beads
1.0 k
On
Q6
2N3735
100
Q80
470 pF
Freq
Control
510 pF
10 k
220
(4)
MTP20Nl0
-15V
-=MCI4001
A2(Clock)
Bl(Oelay)
B4(toff)
A3(ton )
V- '" -50V
I
-.I
I
+
~
Ql0
MTP10Nl0
L
_----'T"lL...-_ _ __
*Ferrite Beads
IN4747
1.0 k
tp(ON) MV
10 k
IN5932
Turn-Off Clamp
FIGURE 7-42 -
FAST, COMPLEMENTARY POWER FET SWITCH
V-
The negative output switch 08 (N-Channel) is capable of
switching at least 100 A, whereas the positive switch 04
(P-Channel) is limited to about 50 A due to the differences
in the respective on-resistances. Additional devices can
be paralleled for either switch for higher currents, if so
required. Also, power FETs with higher VOSS ratings may
be used.
Output Waveforms
The negative and positive switched output waveforms
are shown in Figures 7-43a and 7-43b, with the positive
voltage delayed about 2.0 J.LS, in Figure 7-43a. The externalload resistor RL is about 2.0 ohms, with the switched
voltages of about ± 42 volts.
In Figure 7-43a, the switched negative and positive voltages have very fast leading edges (about 10 ns) and slow
trailing edges (about 3.0 /Ls and 1.0 /Ls, respectively).
Figure 7-43b shows the same switched voltages but with
the clamp transistor (010) switched on. This discharges
08 gates through a low impedance path and speeds up
the trailing edge of the negative voltage to about 25 ns
instead of 3.0 /Ls.
In Figure 7-45, a MR821 fast recovery rectififer is shown
as the load, with IFM = 40 A, di/dt = 300 A//LS, and the
dv/dt of the applied blocking voltage about 2500 V//Ls.
Adjustment of dv/dt is accomplished with R5 for the
positive switched voltage and with R6 for the negative
voltage.
Figure 7-44 shows the transition time of about 35 ns
between the negative and positive voltages, with both the
clamp on and with 04 diverting current from 08.
04
04
Vout
20V
Vout
20 V
diV
dlV
as
08
5.0 p.Sldiv
5.0 ",sldiv
FIGURE 7-438 -
FIGURE 7-43b - FAST TRAILING EDGE, NEG.
VOLTAGE, TURN-OFF CLAMP 010 "ON"
FAST LEADING EDGE
fiGURE 7-43 - NEGATIVE AND POSITIVE SWITCHED OUTPUT VOLTAGE
WITH RL - 2.00, V- AND v+ = 42 V, DRAIN 08
'FM
20 A
Q4
dlV
Vout
~O
div
08
50 nsldiv
50 nsldiv
FIGURE 7-44 - NEGATIVE AND POSITIVE
TRANSITION, DRAIN 08,
TURN-OFF CLAMP 010 "ON"
FIGURE 7-45 - REVERSE RECOVERY (trrl
OF MR821 FAST RECOVERY RECTIFIER
MOTOROLA TMOS POWER MOSFET DATA
1-7-23
•
MOTOROLA TMOS POWER MOSFET DATA
1-7-24
Chapter 8: TMOS Applications
100 kHz Switch Mode Power
Supply
Power FETs have proven themselves to be performance competitive and cost effective in flyback regulators
operating at 100 kHz to 200 kHz.
The circuit described here proves the point. It is a
60 W 100 kHz FET switcher with four output voltages
± 5.0 V and ± 12 V. It operates from 120 Vac, has an
efficiency of 75% and the total parts cost is approximately
$35.
Components unique to this high frequency design include the following:
of ripple occurs at the outputs. Power loss is less
than 0.5 W.
Circuit Design
The goal of most low-power flyback designs is for reduced parts count (or size) and reduced cost. The 60 W
100 kHz switcher shown schematically in Figure 8-1, met
these requirements. At 100 kHz, the transformer size and
cost are reduced by about 30% compared with a 20 kHz
design. Also, at 100 kHz, a FET can be driven directly
from logic circuits (100 to 200 mAl and still switch very
efficiently. This eliminates the need for drive interface circuits. The output caps used are about 50% smaller and
they cost less as well. Finally, a relatively new three-chip
control system is used. It replaces an expensive and performance limited drive transformer with a lower-cost
optocoupler.
The FET is the control element for the flyback transformer and is directly driven from the MC34060 linear IC.
A rather standard off line starter circuit is used to initially
power the control circuit and this is also lower in cost than
the filament transformer supply which is often used to
power a single-chip system. The design procedure followed here was:
• Motorola's MTP5N40 power FET. This 5.0 A, 400 V
device has only one ohm of on-resistance and is
driven directly from a linear IC. It not only switches
in less than 50 ns but has enough RBSOA to eliminate the need for snubbers.
• Pulse Engineering's PE63133 power transformer.
This is a continuous mode flyback transformer Which
is ideally suited to high frequency operation. Zener
clamps are not required because the clamp winding
is interleaved with primary halves. Regulation of the
auxiliary outputs is within ± 10% under varying conditions of line and load.
• Motorola's MC34060 Switchmode control IC, 4N27
optoisolator, and MC1723 linear regulator. These
devices are used in a practical demonstration of a
low-cost, three-chip control system. The MC1723 is
the error amplifier, the MC34060 is a fixed frequency
PWM, and the 4N27 couples the feedback signal
from the MC1723 to the MC34060.
1. Design and test the power stage.
2. Add and stabilize the control loop.
3. Change from dc to ac power.
The FET waveforms obtained with the design are
shown in Figure 8-2. The exceptional switching speed of
the FET can be varified here (less than 50 ns) and ringing
on the current waveform is due to the layout which includes a current-sense loop and noise pickup on the
scope probe.
The input capacitor does not reduce in size like the
outputs because it is needed for energy storage which
still occurs at 60 Hz. Noise filters used here include a
toroid from PE and the economical 41 GS series of tan-
• Motorola's MBR1 035 (TO-220) Schottky rectifier was
used to rectify the + 5.0 V output at half the cost of
a comparable 00-4. Similar cost savings result from
using the TO-220 fast recovery rectifiers, i.e., the
MUR805 in the ± 12 Voutputs.
• Mepco/Electra's 3428 series of output capacitors.
These high frequency electrolytics feature low I;SR
and high RMS current ratings. Only 50 to 70 mV (PP)
Bridge
+
r----..,
160 Vdc
Flyback
Transformer
+12V
120
Vac
Start
Circuit
-1
L..-_ _......
I
I
I
'------
-=
I
I
IL ___________ _
FIGURE 8-1 -
REGULATOR BLOCK DIAGRAM
MOTOROLA TMOS POWER MOSFET DATA
1-8-1
I
I
I
I
__________ JI
Figure 8-3. The first chip is an MC1723 linear regulator.
It is used here to provide a 5.0 V reference and an error
amplifier. It is powered from the + 12 V output winding
and receives feedback or control signal from the + 5.0 V
output. The MC1723 drives the second chip, a 4N27 optocoupler. The coupler maintains isolation between the
primary and secondary windings and couples the dc control signal to the input of the third chip, a MC34060. The
MC34060 performs a fixed frequency pulse width modulator (PWM) function and is used to directly drive the
FET power switch which is connected to the primary or
energy storage winding.
The key regulating blocks are the 0 to 3.0 V sawtooth
oscillator and the feedback comparator. As the feedback
signal is raised from 0 to 3.0 V, it gradually narrows the
on time of output pulse coming from the comparator. During start up, the feedback is missing and resistor divider
network controls the second or dead-time comparator ,to
ensure that on time cannot exceed 45%. This, and the
soft start capacitor, prevents transformer saturation problems during start-up. Pull down of the gate voltage is
accomplished as shown in Figure 8-3 with the addition of
a low cost TO-92 PNP transistor (Q3). In this deSign, the
MC34060 is started off line with the addition of a 200 V
transistor (Q2) and 12 V zener as shown in Figure 8-4. It
ultimately (at normal line voltage) runs off the 12 V auxiliary winding which back biases this transistor. Because
it and the FET gate draw so little current from the line,
about 20 mA, undervoltage inhibiting common to bipolar
deSigns was not required here and this current becomes
functional and runs safely when the input reaches 40 Vac.
The performance of this 100 kHz switcher is similar to
most others. It is relatively easy to keep output ripple, both
talum capacitor from M/E. The 12 V output rectifiers were
Motorola's MUR805 ultrafast recovery button rectifiers
which are housed in a TO-220 package. They were ideally
suited to this relatively high current (10-15 A peak) application because the correct amount of heat sinking was
easily attained by simply bolting a fin to the tab.
The relatively new MBR1035 TO-220 Schottky rectifier
is the best choice for rectifying the 5.0 V output. It is about
half the cost of the equivalent 00-4 version, a 1N6095.
The overall efficiency of this regulator (including the
control circuits) is 75%. As usual, most of the losses are
associated with the power handling components as noted
in Table 1.
TABLE 1 -
Efficiency Data
1. Input Power
Vln
lin
PPRMS
160 Vdc
0.6 A
96
120 Vac
1.4A
170
'Note using Clark-Hess wattmeter.
2. Output Power
Winding
Load (ohms)
Voltage
Power
3. Efficiency
Elf. = Po/Pin
5.0
1.0
5.1
2.5
PF
100%
56%
+12.0
8.0
13.2
21.5
-12.0
8.0
13.3
22.0
Fast Recovery (both)
Misc.
8.0 W
5.0 W
-5.0
10.0
5.1
2.6
= 72 W/95 W = 75%
4. Estlmsted Losses
FET
4.0 W
Schottky
4.0 W
Transformer
2.0 W
•
PA
96
95'
The control loop contains three chips as noted earlier.
The functional diagram of this arrangement is shown in
10
11.0 AlDIVI
10
11.0 AlDIVI
vos
1100VI0IVI
Vos
VGS
15.0 VIOIVI
1100 VIDIVI
VOS
1100 VIDIVI
0.5 AlOIV
10
11.0 AlDIVI
~
t
10
VGS
15.0V101VI
I
I
VOS--
50 VlOIV
AGURE 8-2 - FET WAVEFORMS - 120 Vac, FULL LOAD
MOTOROLA TMOS POWER MOSFET DATA
'-8-2
Secondaries
160 Vdc
+ 12 V
r- -----.,
I
I
I
I
T1
I
.....'lNIr-H7.0 V
Ref
I
I
I
I
I
:
I
I
I
_______ .J
L ______________ J I
MC1723
Error
Amplifier
Pulse Width
'Control I,C.
4N27
-=
Oplacoupler
FIGURE 8·3 -
Output Capacitors
all 720 & 1000 p,F
ll-PE51590 -12~, 5,0 A
L2,13 - PE51591 -20 #H, 2.0 A
01
MIE 3428 Series
alil0pFTantelum
MIE 41GS Senes
MOA
202
THREE CHIP CONTROL SYSTEM
T1 Pulse Englneerlns
#PE63133
AllernateTl
Ferroxcube Ec.41
Gap 30 mils, 1 3 mH
Prim
70T #24 (2 layers)
Clamp
70T #28 (1 layer)
:!:12V
8T #20 Btfylar
:!: 5 0 V
4T #20 Quadfylar
12 VAux
8T #20
T1
D6
r---M-""?""-rY"v"\'_~--<> -12V
MURB05
C7
lN4937
D2
"',60V
...._ _ _~_-o +12V
L_~_""_.r;-v-,_
220 pF C2
Rl
310p f
R2
lOOk
1.0W
200 V
120 Vae
2.0W
+12VAux
MTP
C8
5N40
C12
R5
O~
lOOk
lOW
20 kV
T
C1 •
R16
'="
T
1k
IC2
lN5242
D8
12V
R13
C19
01
lOOk
A11
Al0
5"
C14
01
.-----~
22k
~--------------------~
FIGURE 8-4 -
100 kHz FET REGULATOR
MOTOROLA TMOS POWER MOSFET DATA
1~8-3
5"
R15
10}&F
1.0 A
I
115 Vac
±20%
i
,.!Q:
r •. f \
...
T1
..
"
MBR1035
1N4003
1N4002
~111r--+lH--+---------'
+
470
)1
, :;;330 +;;;, 200
V
h
~ ·l
'Q
II'
0'.~1
t-----,
~+
10
VCC
I
..
+ 10
0
33 k ;:"
lO'V
Vo .........""'~
_ _ _~ 5.0 V
RET
~L3
+
1000"
+ 12 V/0.5 A
+
'!' 10
~ ,1000
·1N4934
I
ir,t-'
_~......,T"'L"'43""1"'C:=LP'--
1N4934
It
It
•
6 ':} 4N35
33 k
10 V
kt
100
~/~~1'0
+ 1.0
1I ...._ _ _............
II
•
51//
Y 1/2
4.7k
+
2200;:~
T3 •
35 V
15.0
<1.0 JLH
~L2
1/24N36
~
--L4
C~
±12 V
RET
+
,[,10
-12 V/0.5 A
2
;:
3
22 k
0.1
I
MC
34060P
~+
r
13
4.7 k
4.7 k
r-------,
U1
..
K 'A55
II'
I
E~
25 k
200:>
47 k
1N4933L---:+-tt---t----l
R.
10
L13)
27kt--J~_-+---'
+
+!
I ~ . .JMPS, f.. i
12 Vref
G~
DT CT RT
'----,.---+---t--'r
1.0
510
I
I.
~_ _ _,
1N4933
E 8
iI
Pout
-,r
I
I
'"-
L ____ ,
,~g~5
~
I
!
1N4937
47
I
1/2W:
I
IL _____________ .JI
•
FIGURE 8-5 -
20 kHz SWITCHING POWER SUPPLY USING A BIPOLAR SWITCH
Unless otherwise noted:
All resistors are 1/2 W
All capacitors rated 25 V
Transformer Data
Tl:
Intemal power supply transformer for switching regulator
TRAID F90X Primary -
T2:
Black·red and black green. Secondary -
Core:
Ferroxcube 768T183-3C8
Windings:
Primary
-
Secondary T3:
L2:
1 turn, #26 Awg. lead from primary of T3 looped through
center of T2, note dots.
100 turns, #28 Awg.
High frequency output transformer
Core:
Coilcraft 11-464-16, 0.025 gap in each leg.
Bobbin:
Coilcraft 37-573
Windings:
Primary
-
Secondary L 1:
Blue and green
Collector current sense transformer Coilcraft D1870
2 windings 75 turns each, #26 Awg, bitilar wound.
One winding is connected to the MJE 13005 and
the second is connected to the 1N4937, note dots.
5.0 V, 6 turns, #16 Awg.
12 V, 14 turns, #22 Awg, bifilar wound.
,---j-'
Base drive inductor
Core:
None
Bobbin:
Ferroxcube 1408Fl D
Winding:
39 tums, #28 Awg., 10.5 JLH
U1
i
}1
5.0 Volt output filter inductor
I
I
Coilcraft Z7156, 15 JLH at 5.0 A
IL _______ .J
I'::"
L3,L4: 12 V output filter inductors
Coilcraft Z7257, 25 JLH at 1.0 A
FIGURE 8-6 -
MOTOROLA TMOS POWER MOSFET DATA
1-8-4
POWER MOSFET VERSION
providing a good relative measure of its efficiency as a
switching element.
When an MTP4N50 FET is substituted for the bipolar
transistor, the drive circuit is greatly simplified as illustrated in Figure 8-7. Now the MC34060 control circuit is
capable of directly driving the FET, eliminating the complex base drive circuitry required for the bipolar. The end
result is that the FET can be substituted for the bipolar
by removing five components and changing one resistor
value. Thus, the FET substitution results in a reduced
components count.
Performance wise, the FET is the better choice, with a
considerably improved crossover time, Figure 8-8, and a
case temperature rise of only 18°C.
60 Hz and 100 kHz, below 100 mV on all outputs. (See
Table 2.) Line regulation here was excellent, less than
0.1%, but load reg (2.0%) could have been better. Normally tight layouts and higher loop gain can get this down
to 0.1 to 0.5% as well. Efficiency (75%) and cross regulation (± 10%) are also similar to other multiple output
switcher designs.
TABLE 2 -
Output Data
1. Ripple Voltages (120 Vac, Full Load)
Winding
100 k Ripple (PP)
60 Hz Ripple (PP)
Noise Spikes (PP)
+5.0
60mV
20mV
2.0 V
-5.0
300mV
50 mV
2.0 V
+12
70 mV
70 mV
2.0 V
-12
50 mV
60 mV
2.0 V
2. + 5.0 V Regulation
Automotive DC-DC Converter
100 Vac 100 Vac 130 Vac 130 Vac
Full
Half"
Full
Half
5.21
5.10
5.21
5.10
Line
Load
Voltage
In the previous example, FET drive circuitry was maximally simplified. The penalty for this simplification is that
turn-on gate-source voltage, applied across a relatively
low gate-source resistor, draws approximately as much
drive power as a bipolar would. This example illustrates
how the FET's low drive power requirements can be used
advantageously. The circuit, shown in Figure 8-9, is a 25
watt DC-DC converter that is designed for automotive use.
It uses the same control IC as the previous example. The
significant difference is the addition of Ql, 03, & 06 to
the drive loop. This arrangement provides a low impedance loop for fast turn-off, while drawing a negligible
amount of current from the IC after the FET is turned-on.
The FET and this circuit work well together. Efficiency
was measured at 78% with Vin at 13.6 volts, load regulation at O.4%/Amp., and line regulation at O.Ol%/volt.
In general, the comparatively low rOS(on) of FETs with
100 V (or less) ratings makes the FET a particularly good
choice for this type of application.
°Note: +5.0 V Load Increased to 2.0 ohms and -12 V load removed.
Load Reg. ~ !J.voNo ~ 0.11/5.1 ~ 2.2%.
Line Reg. !J.VoNo ~ 0.005/5.1 ~ 1.0%.
20 kHz Switcher
A less novel 20 kHz flyback switcher provides a good
illustration of the interchangeability of FETs and bipolar
transistors. The 35 watt supply shown in Figure 8-5 was
originally designed around the MJE13005 bipolar output
transistor. With the bipolar, crossover time and case temperature rise were measured with Vin at 160 Vdc and
outputs fully loaded.
A view of the crossover waveforms is shown in Figure
8-7. At the full load case temperature of 71°C, the
MJE13005 is turning on in a crossover time of slightly
under one microsecond, (46°C case temperature rise),
o
o
FIGURE 8-7 -
FIGURE 8-8 -
BIPOLAR CROSSOVER TIME
MOTOROLA TMOS POWER MOSFET DATA
1-8-5
FET CROSSOVER TIME
...
Input
~±
9-24 V
0.1
Ll
151'h
01
lN5821
'~
05
lN4935
~20
t
02
' lN4148
331 f O
0.Q1 '"
r-l
2.7
n_
M
10 k
10
-1.
•
L-_-=.2\_
8.2 k
i'
14 +
r!-!-
~0-.9-V---,\N\,-22-2t~~~~-_~=-:-,.
27
k
GNO
75
,?_
OT CT RT
6
4
5
03
lN4148
k
10 k
.!'
MTP
~....
251~~
1~Q2
all
MPS~~
1.35 V
1.8 k
I'F
8.2
,;~~t n
E 8
12 VREF
, F' o. 1
I
13
8.2 k
,;;;;l00I'F ~
1.0 k
73T'"
#26
ICl
MC34060P
3
.-.----+-'-"-i,
k
+
·~~+----~COMP
0.1
8.2
~
6T
#18
33 k
54V
Tl)""
~dt
Uk
'h W
100 k
470I'F
A5~t-'
"
04
lN4148
lOon
IN
~ 4746
18 V
'fo.05
~~--------------------------------~
T1:
CORE - FERROXCUBE 3019·LOO·3CB
BOBBIN - FERROXCUBE 3019F·10
GAP - 0-015"
T2:
COILCRAFT 01871 CURRENT SENSE XFMR.
T3:
CORE - COILCRAFT 11-464-41 EE·19
BOBBIN - COILCRAFT 37·612·001
GAP - 0,0075"
FIGURE 8-9 -
L1:
COILCRAFTZ7158.15I'H
L2:
COILCRAFT Z7157. 251'H
AUTOMOTIVE DC·DC CONVERTER
High Voltage Flyback Converter
The advantages of power MOSFETs over bipolars high input impedance (low drive power), fast switching,
freedom from second breakdown - have been cited
many times and can clearly be shown when the two technologies are used in the same application. Such is the
case when a HV flyback converter, initially designed with
a bipolar, was redesigned for the power MOSFET.
The first design used a Switchmode high-voliage bipolar
MJ8505 output transistor in a PWM flyback converter,
Figure 8-10c. This transistor has breakdown voltage ratings VCEO(sus) and VCEV of 800 V and 1400 V, respectively, and a continuous collector current of 10 A. But,
most important, it has a reverse bias safe operating area
(RBSOA) curve, shown in Figure 8·11 a, which allows a
peak flybac'k voltage of about 700 V, generated by a peak
collector current in the 3.0 to 4.0 A range.
To achieve this RBSOA capability an off-bias voltage,
VBE(off), of about - 5.0 V is required. Also, since there
MOTOROLA TMOS POWER MOSFET DATA
1-8-6
is a trade-off of 13 with high-voltage transistors (I3min =
7.5 at IC = 1.5 A), a low forced beta I3F of about 2.5 (lSI
= 1.5 A) was chosen to ensure device saturation. To
produce clean, monotonic, relatively fast clamped inductive turn-off waveforms, the Saker Clamp network of
diodes (02-04) is suggested. Consequently, a power amplifier consisting of an lSI forward base current circuit
(transistors Q1 and Q2) and an off-bias circuit (transistors
Q3 and Q4) is required to interface the low level PWM
with the MJ8505. The PWM (U1), for this example, need
only provide a + 5.0 V pulse to the power Amp with about
20 rnA sourcing and sinking capability.
If, however, the output device is a comparably rated
power MOSFET, MTM2N90 the drive circuitry can be
greatly simplified, with the resulting savings in cost and
improved reliability. Moreover, the faster switching
<36 V
L2 = 2.0 mH
lOOT #20
Pot Core: 42293C8
Gap: 65 mil
+VDD
+VDD
Ll = 1.6 mH
lOOT #24
Pot Core: 3019P387
...- -....f-.---t--()Va
Ll MR510
DI Va
......t - _ - _ - o V o
68
+15
1.0 k
UI
1.0 k
O.IJJ-F
1.0 kV
PWM
(2)
MTM2N90
68
1.0 k
PWM
FIGURE 8-10a -
FIGURE 8-10b -
SINGLE MOSFET OUTPUT
TWO PARALLEL MOSFET OUTPUT
•
+5.0 V
Power
Amp
220
150 pF
PWM
02
MJE210
100
V,W
01
2.0
2N
2222
5.0W
9
Ul
4.7 k
+VCC
lN4007
D2
MR510
D
Vo
0.01 JJ-F
RL
Cl
60 k
-=
-=
IN914
-=
FIGURE B-l0e -
FIGURE 8-10 -
-5.0 V
DRIVER WITH BIPOLAR OUTPUT
HIGH VOLTAGE FLYBACK CONVERTER WITH POWER MOSFET " BIPOLAR OUTPUTS
MOTOROLA TMOS POWER MOSFET DATA
1-8-7
a
0
\
0
.0
\
VBE(off) ~ 2.0 to 7.0 V
Or- rf - r-
a
\
IcIIB~2.0
TJS100·C
1\
0
\
",...~-
200
400
600
BOO
TJ
.0
~
MTM2N85
MTP21N85
150°C
MTM2N90
MTP2N90
"-
1000
0
r--. -
1200
a
1400
400
800
200
600
Vas. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
VCE. COLLECTOR·EMITTER VOLTAGE (VOLTS)
1000
FIGURE 8-11& - RBSOA, REVERSE BIAS SWITCHING
SAFE OPERATING AREA
FIGURE 8-11b - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
MOSFET improves system efficiency and as subsequently described, greater RBSOA or turn-off switching
SOA is achieved (see Figure 8-11 for comparison of the
MTM2N90 with the MJ8505).
The PWM can be any of the 15 V powered I.C.'s with
source and sink capability in the 100 mA range. This current level is amendable to driving power MOSFETs at a
relatively fast switching speed, the current sourcing,
charging up the FET input capacitance Ciss and the sinking, discharging the capacitance for fast turn-off switching.
Also, the near 15 V PWM output ensures that the FET is
well turned on.
This is exactly what was done for the second version
of the high voltage Switch mode power supply; the PWM
directly drives the FET gate. Using a single N-channel,
high-voltage TMOS MTM2N90 transistor V(BR)OSS =
900 V, 10 = 2.0 A), a high-voltage output of 750 V peak,
capable of driving a 60 k load was achieved. With the
illustrated load inductor L1 and switching frequency, the
peak drain current was about 2.5 A (limited by the magnetic saturation of the inductor) and the flyback voltage
was about 750 V.
Atlhough this current exceeds the continuous 2.0 A
drain current rating of the device, it is well within the
7.0 A pulsed current rating. But, of even greater interest,
since the FET has no second breakdown limitations as do bipolars - it can sustain simultaneous high switching voltages and currents. Thus, the 750 V, 2.5 A load
line is well within the SOA rating.
To produce even higher output power levels, two parallel connected power MOSFETs can be driven, as illustrated in Figure 8-10b. Using a larger inductor L2, the
circuit was capable of easily producing an 800 V output
into a 30 k load. The total peak drain current was 3.5 A
with each driver sharing current inversely proportional to
its rOS(onj= i.e., matched on-resistance of 5.0 n produced
about equal values of 10 of 1.75 A, unmatched 5.0 and
8.0 n, about 2.1 A and 1.4 A respectively. Reducing the
load resistance even further, resulted in greater power
output, with the individual device drain current being well
within spec limits, as shown in Table 3:
TABLE 3
RL
VOO
Vo
Total
IO(pk)
Po
30 k
25 k
21 k
28 V
31 V
34 V
800 V
800 V
800 V
3.6A
3.8 A
4.2A
21.3 W
25.6W
30.5W
And finally, to make a direct comparison between the
two devices, the loads and the stored energy inductor
should be the same. Since the bipolar originally was tested
with the larger inductor and a 30 k load to produce as
great as a 700 V output from a peak collector current of
3.2 A, the single TMOS was also tested to these conditions. Not only did the power MOSFET reach this energy
level, it also reached 800 V at 3.6 A. To achieve the
required inductor stored energy and power output for this
application, the switching frequency was about 1.7 kHz.
Even at this low frequency, the relatively high static losses
[VOS(on) = rOS(on) 10 = 8.0 n (max) (3.2 A) "" 25 VI
contributed little to the total device loss.
Admittedly, power MOSFETs are still more expensive
than a comparably die sized bipolar, but, as progression
along the learning curve is achieved, the FET will become
more cost competitive. Nevertheless,- it has been shown
that the single power FET circuit is much simpler and cost
effective to drive in this example than the bipolar and offers
the second breakdown free rectangular SOA curve that
allows full V(BR)OSS, 10 switching capabilities.
SWIl'CHMODE Power Supply
(SMPS) Configurations
The implementation of switching power supplies by the
non-specialist is becoming increasingly easy due to the
availability of power devices and control ICs especially
developed for this purpose by the semiconductor manufacturer.
This section is meant to help in the preliminary selection
of the devices required for the implementation of the listed
switching power supplies.
MOTOROLA TMOS POWER MOSFET OATA
1-8-8
Flyback Switching Power Supplies:
50Wto250W
• Input line variation: Vin
+
• Converter efficiency: 1/ = 80%
10%, - 20%
• Maximum FET working voltage:
VDSW = 2.0' Vin(max) • v'2.O
• Output regulation by duty cycle (8) variation:
Bmax = -0.4
• Minimum FET drain-source voltage:
VDS;;;' 1.2' VDSW
• Maximum MOSFET working current:
I =
2.0 Pout
= 5.5 Pout
w
1/' 8max • vTri(min) • v'2.O
Vin
• Working frequency: f = 20 to 200 kHz
Output
Rectifier
DC Output
.
Line
Input
/
/
/
Input
Rectifier
Control
Circuitry
FIGURE 8-12 -
BASIC FLYBACK CONFIGURATION
TABLE 4 - Flyback Semiconductor Selection Chart
Output Power
50W
100W
175W
250W
Input Line Voltage, Vin
120 V
220 V
or
240 V
120 V
220 V
or
240 V
120 V
220 V
or
240 V
120 V
MOSFET Requirements
. Max Working Current, Iw
Max Working Voltage, VDSW
2.25 A
380 V
1.2 A
750 V
4.0 A
380 V
2.5A
750 V
8.0A
380 V
4.4 A
750 V
11.4 A
380 V
Power MOSFETs Recommended
Metal (TO-204AA) (TO-3)
MTM4N45 MTM2N90 MTM4N45 MTM2N90 MTM7N45 MTM4N90
Plastic (TO-220AB)
MTP4N45 MTP2N90 MTP4N45 MTP2N90
Plastic (TO-218AC)
MTH7N45
Input Rectifiers
Max Working Current, 'DC
Recommended Types
Output Rectifiers
Recommended types for
Output Voltage of: S.OV
10V
20V
SO V
100 V
Recommended Control Circuits
0.4 A
0.25 A
0.4 A
MDA104A MDA106A MDA206
MBR3035PT
MUR3010PT
MUR1615CT
MUR161SCT
MUR440, MUR840A
0.5A
MDA210
MBR3035PT
MUR3010PT
MUR1615CT
MUR161SCT
MUR840A
2.35 A
MDA970
1.25 A
MDA210
MBR1203SCT
MUR1 001 OCT
MUR301SPT
MUR1615CT
MUR840A
SG152SA, SG1526, TL494; Inverter Control Circuit
MC3423, MC3424; Overvoltage Detector
Error Amplifier: SINGLE TL431; DUAL-MC3438, LM358;
QUAD - MC3403, LM324, LM2902
MOTOROLA TMOS POWER MOSFET DATA
1-8-9
MTM15N45
4.6 A
MDA3S06
MBR20035CT
MUR1 001 OCT
MUR10015CT
MUR3015PT
MUR840A
Push-Pull Switching Power Supplies:
100Wto 500 W
• Input line variation: Yin + 10%, - 20%
• Maximum FET working voltage:
VOSW = 2.0· Vin(max) • V2.O
• Converter efficiency: 't/ = 80%
• Output regulation by duty cycle (8) variation:
8rnax = 0.8
• Minimum FET drain-source voltage:
VOS '" 1.2' VOSW
• Working frequency: f = 20 to 200 kHz
• Maximum MOSFET working current:
I Pout
_ 1.4 Pout
Yin
w - 't/' 8max' Vin(min) • V2.O -
Output
Filter
Output
Rectifier
rI
DC Output
L
Line
Input
Control
Circuitry
Input
Rectifier
•
Power
Inverter
FIGURE 8-13 -
TABLE 5 -
BASIC PUSH-PULL CONFIGURATION
Push·Pull Semiconductor Selection Chart
100W
Output Power
500W
250W
Input Line Voltage, Yin
120 V
220 V
240 V
120 V
220 V
240 V
120 V
220 V
240 V
MOSFET Requirements
Max Working Current, Iw
Max Working Voltage, VOSW
1.2 A
380 V
0.6A
750 V
2.9A
380 V
1.6 A
750 V
5.7 A
380 V
3.1 A
750 V
MTM2N50
MTP2N45
MTM2N90
MTP2N90
MTM4N45
MTP4N45
MTM2N90
MTP2N94
MTM7N45
MTM4N90
Power MOSFETs Recommended
Metal (TO-204AA) (TO-3)
Plastic (TO-220AB)
Plastic (TO-218AC)
Input Rectifiers
Max Working Current, IOC
Recommended Types
Output Rectifiers:
Recommended types
for output voltages of:
5.0V
10 V
20 V
50V
100 V
-
0.9 A
MOA206
0.5A
MOA21 0
MBR3035PT
MBR3045PT
MUR3010PT
MUR1615CT
MUR1615CT
MUR840A, MUR440
Recommended Control Circuits
-
2.35 A
MOA970-5
1.25 A
MOA210
MTH7N45
4.6 A
MOA3506
-
2.5 A
MOA3510
MBR12035CT
MUR1 001 OCT
MBR20035CT
MUR10010CT
MUR3015PT
MUR1615CT
MUR840A
MUR10015CT
MUR3015PT
MUR840A
See Table 4
MOTOROLA TMOS POWER MOSFET DATA
1-8-10
-
Half-Bridge Switching Power Supplies:
100 Wto 500 W
• Input line variation: Vin
+
10%, - 20%
• Maximum FET working voltage:
VOSW = Vin(max)· v'2.O
• Converter efficiency: T/ = 80%
• Output regulation by duty cycle (Il) variation:
Ilmax = 0.8
• Minimum FET drain-source voltage:
VOS;;' 1.2·VOSW
• Working frequency: f = 20 to 200 kHz
• Maximum MOSFET working current:
I _
2.0 Pout
_ 2.8 Pout
Vin
w - T/. Ilmax • Virl(min) • v'2.O -
Output
Rectifier
r-
--,
L_
_.J
I
Output
Filter
DC Output
I
---,I
r---~----~-+--~-.
Line
Input
W-rl
I
Control
I
Circuitry
I
I
Input
Rectifier
l01
I
FIGURE 8-14 -
TABLE 6 -
BASIC HALF-BRIDGE CONFIGURATION
Half-Bridge Semiconductor Selection Chart
100 W
Output Power
350W
500W
Input Voltage, Vin
120 V
220 V
240 V
120 V
220 V
240 V
120 V
220 V
240 V
MOSFET Requirements
Max Working Current, Iw
Max Working Voltage, VOSW
2.3 A
190 V
1.25 A
380 V
5.7 A
190 V
3.1 A
380 V
11.5 A
190 V
6.25 A
380 V
MTM5N35
MTP3N40
MTM2N45
MTP2N45
MTM8N40
MTM4N45
MTP4N45
MTM10N25
MTP10N25
MTM7N45
Power MOSFETs Recommended
Metal (TO-204AA) (TO-3)
Plastic (TO-220AB)
Plastic (TO-218AC)
Input Rectifiers
Max Working Current, IOC
Recommended Types
Output Rectifiers:
Recommended types
for output voltage of:
5.0V
10 V
20V
50 V
100 V
-
0.9 A
MOA206
-
0.5 A
MOA210
MBR3035PT
MBR3045PT
MUR3010PT
MUR1615CT
MUR1615CT
MUR840A, MUR440
Recommended Control Circuits
-
-
MTH8N40
2.3A
MOA970-5
1.25 A
MDA210
MTH7N45
4.6 A
MDA3506
2.5A
MDA3510
MBR12035CT
MUR1 001 OCT
MBR20035CT
MUR1 001 OCT
MUR3015PT
MUR1615CT
MUR840A
MUR10015CT
MUR3015PT
MUR840A
See Table 4
MOTOROLA TMOS POWER MOSFET DATA
'-8-"
-
•
Full-Bridge Switching Power Supplies:
500 W to 1000 W
+
• Converter efficiency: 1/ = 80%
• Maximum MOSFET working voltage:
VOSW = Vi~(max)' V2.O
• Output regulation by duty cycle (8) variation:
8max = 0.8
• Minimum FET drain-source voltage:
VOS ;;. 1.2' VOSW
• Maximum MOSFET working current:
• Working frequency: f = 20 to 200 kHz
• Input line variation: Yin
Iw
=
10%, - 20%
Pout
1/ • 8max • Vin(min) • V2.O
= 1.4 Pout
Yin
Output
Filter
Output
Rectifier
Line
Input
Input
Rectifier
r - - - - --,
L_____ J
DC Output
~}-----J
Control
Circuitry
~I
Power
Inverter
I
FIGURE 8-15 -
TABLE 7 -
BASIC FULL-BRIDGE CONFIGURATION
Full Bridge Semiconductor Selection Chart
Output Power
500W
1000 W
750W
Input Voltage, Yin
120 V
220 V
240 V
120 V
220 V
240 V
120 V
220 V
240 V
MOSFET Requirements
Max Working Current, Iw
Max Working Voltage, VOSW
5.7 A
190 V
3.1 A
380 V
8.6A
190 V
4.7 A
380 V
11.5 A
190 V
6.25 A
380 V
MTM8N20
MTP8N20
MTM4N45
MTP4N45
MTM10N25
MTP10N25
MTM7N45
MTP4N45
MTH7N45
MTM15N20
MTP12N20
MTH15N20
MTM7N45
3.8A
9.25 A
5.0A
Power MOSFETs Recommended
Metal (TO-204AA) (TO-3)
Plastic (TO-220AB)
Plastic (TO-218AC)
Input Rectifiers
Max Working Current, IOC
Recommended Types
Output Rectifiers:
Recommended types
for output voltages of:
5.0
10
20
50
100
-
4.6A
MOA3506
V
V
V
V
V
2.5A
MOA3510
MBR20035CT
MUR10010CT
MUR10015CT
MUR3015PT
MUR804PT
Recommended Control Circuits
7.0 A
MBR30035CT
MUR1 001 ocr
MUR10015CT
MUR3015pr
MUR3040pr
See Table 4
'More than one deVIce per leg, matched.
MOTOROLA TMOS POWER MOSFET DATA
1-8-12
MTH7N45
MBR30035Cr
MUR10010CT*
MUR10015cr
MUR10015CT
MUR3040PT
Motor Controls
Power MOSFETs are interesting devices for motor drive
applications. The advantages and disadvantages are si~
ilar to those discussed for switching power supplies. With
motor drives, however, there is more of a distinction.
Whereas FETs are not yet a match for bipolar Darlingtons
in off-line multiple horsepower drives, they are an excellent choice for fractional horsepower drives and drives
that are operated off busses less than 100 V.
Three examples are illustrated. They include a stepping
motor drive, a high efficiency H bridge, and a onetransistor PM motor speed control.
Using Power MOSFETs in Stepping
Motor Control
Stepping motors are used extensively in electromechanical positioning systems. Applications range from
printers to tape drivers, floppy disk drives, numerically
controlled machinery and other digitally controlled positioning systems. The task of the stepping motor controller
is to drive the rotation generating sequential current flows
in the field winding of the motor on command from an
external device.
The use of TMOS Power MOSFETs and CMOS logic
simplifies the drive circuitry while allowing considerable
flexibility of control. This section describes several types
of stepping motor control circuits including an 88.0% efficient switching drive. Stepping motor logic sequencing,
power requirements and dynamics are briefly examined.
DRIVE TECHNIQUES
Stepping Motor Characteristics
A basic understanding of stepping motors is desirable.
A permanent magnet stepping motor consists of a series
of permanent magnets distributed radially on a rotor shaft
surrounded by electromagnets attached to the stationary
housing. Energizing the electromagnets with the proper
polarities generates a magnetic field pattern to which the
motor magnets try to align producing torque. A simplified
representation of a stepping motor is shown in Figure
8-16. Initially, Poles A and 8 are both energized with north
up, drawing the rotor's south pole to the up position. ~e
versing the polarity of Pole A draws the rotor Soo clockwise
to its final position; this is known as a full step. If pole A
had been turned off instead of reversed, the rotor would
have rotated only 45° clockwise to line up with the field
created by Pole 8; this is known as a half step. Stepping
motors obtain small angle step increments by using large
numbers of poles. Stator pole reversal can be accomplished by reversing the current flow direction in the winding or by using alternate halves of a center-tapped
winding.
An external block diagram of a center-tapped stepping
motor plus control switches, inductive clamp diodes, resistive current limiting and power supply is shown in Figure
8-1? Pole A, for instance, can be energized to one polarity
by turning Switch 1 on and Switch 2 off; the opposite
polarity is generated by turning Switch 1 off and Switch
2 on.
I! follows that the proper magnetic polarity sequence
for stepping can be generated by controlling Switches
1-4. Clamp diodes prevent the voltage across the inductive winding from flying up and destroying the switches
as they are turned off. The required switching sequences
for full and half step operation are shown in Figure 8-18.
Reversing the sequences of Figure 8-18 will reverse the
direction of motor rotation.
Rapid stepping requires high dildt in the motor windings.
Since dildt is a function of supply voltage, a high supply
voltage is desirable. The average winding current is limited by the motor manufacturer's specification. As an example, Superior Electric's SLO-SYN model MOS3-FCO?
has a current rating of 3.5 ampslwinding with 1.23 01
winding resistance and ?S4 mHlwinding inductance. The
recommended power supply is 24 volts; currents are limited to the maximum rating by a 6.5 0, 100 W resistorl
winding. This yields a dc current of about 3.0 A and an
UR time constant of 1.0 ms. Higher supply voltages and
Protection Diode
FIGURE 8-16 -
SIMPLIFIED STEPPING MOTOR
'Colors are for Superior Electric
SLO-SYN dc Stepping Motors
FIGURE 8-17 -
SIMPLIFIED STEPPING MOTOR AND CONTROL
BLOCK DIAGRAM"
MOTOROLA TMOS POWER MOSFET DATA
1-8-13
the resulting larger current limiting resistor will decrease
UR and increase the obtainable stepping rate.
Depending on rotor inertia, torque requirements and
winding currents, a stepping motor may exhibit oscillatory
behavior including vibration, lost steps and/or stalling near
self-resonant stepping frequencies. Oscillatory behavior
may be lessened or eliminated by adjusting winding currents, by adjusting interial and/or torque loading or by the
use of mechanical dampers.
I
~
A Full Step Center-Tapped Drive
Figure 8-19 illustrates a full step center-tapped stepping
motor controller using one CMOS 4-bit presettable shift
register to drive four N-Channel TMOS Power FETs. Examining the full-step sequence of Figure 8-18, shows that
the sequences for the various gate signals are the same
except for a phase shift. Therefore, the desired control
sequence of two on-time periods followed by two off-time
periods may be preset into the 4-bit shift register
(MC14194) of Figure 8-19. The required phasings are
obtained by tapping the appropriate shift register outputs.
Clockwise stepping is obtained by right shifting the
MC14194; left shifting yields counterclockwise stepping.
Control signals SO and S1 plus a clock line control stepping. On power-up, the MC14194 requires a preset obtained by setting SO, S1 = 1,1 and supplying a leading
edge clock; this puts the logic in a known state. The remainder of the control functions are illustrated in the control table of Figure 8-19; stepping occurs in a leading edge
clock. Diodes 1-4 prevent the inductive turn-off spike from
avalanching the TMOS Power FETs. Resistor R3 creates
a back voltage which halts winding current rapidly on turnoff. R3 is selected to limit the voltage spike to the TMOS
SoD voltage rating. TMOS power FETs switch extremely
fast, and the turn-on delay of the diodes may not be short
enough to prevent SoD avalanche. A small capacitor (0.01
to 0.1 /LF) placed across the motor winding will usually
lower dv/dt sufficiently to prevent SoD avalanche. Resistors R1 and R2 limit motor winding currents.
winding drive sections plus the complete control logic is
shown in Figure 8-21. The total drive consists of four
N-Channel and four P-Channel TMOS Power FETs arranged in two push-pull drives per winding (the M093FC07 center tap leads were floated, inductancelfull winding = 31.76 /LH, resistancelfull winding = 2.46 nand
rated current = 2.0 amps/winding).
Phasing signals are obtained with the shift register technique described earlier. The circuit of Figure 8-21 will provide a full or half step sequence as clocked into the two
CMOS shift registers during a preset (a full step only controller can be implemented with one 4-bit CMOS shift register). Gate signals for the N-Channel FETs are taken
directly from the CMOS registers. Gate signals for the
P-Channel FETs are translated and referenced to the motor power rail through Q9-Q10.
Sufficient capacitance across the sources of the bridge
FETs must be used to limit P-Channel gate-source voltage
transients to below the pass frequency of the collector
resistor and the P-Channel gate capaCitance. During
switching transients, it is possible that both FETs in a given
complementary pair could briefly be on at once. This condition could short power to ground through the complementary pair. To avoid exceeding peak drain current rating, the gate-drive on the P-Channel FET is restricted to
10 V.
TMOS Power FETs are constructed with internal
source-to-drain diodes. The circuit of Figure 8-21 uses
these diodes to shunt turn-off transient currents from the
ground plane to the power rail; thus, a given FET is protected from winding turn-off energy by the source-drain
diode of its complement. The source-drain diode, how-
Full-Step Sequence
A Full or Half Step Center-Tapped Drive
Figure 8-20 illustrates a full or half step controller. As
in the full step sequence, the gate control signals for the
half step sequence are identical except for a phase shift.
Similarly, the desired pattern of three on-time periods followed by five off-time periods can be preset on a leading
edge clock into an eight-bit shift register formed by two
MC14194's. The full step sequence can be generated by
setting the half step line high and performing a preset.
Right shifting and left shifting control the motor shaft's
direction of rotation as before. A full step will be executed
for every two rising clock pulses independent of stepping
sequence. piodes D1-D4 and resistor R3 form the overvoltage protection for the TMOS Power FETs. R1 and R2
limit motor winding currents.
STEP
SWl
SW2
SW3
SW4
1
OFF
ON
OFF
ON
2
OFF
ON
ON
OFF
3
ON
OFF
ON
OFF
4 "-
ON
OFF
OFF
ON
1
OFF
ON
OFF
ON
STEP
SWl
SW2
SW3
SW4
1
OFF
ON
OFF
ON
2
OFF
ON
OFF
OFF
3
OFF
ON
ON
OFF
4
OFF
OFF
ON
OFF
5
ON
OFF
ON
OFF
6
ON
OFF
OFF
OFF
7
ON
OFF
OFF
ON
8
OFF
OFF
OFF
ON
1
OFF
ON
OFF
ON
Half-Step Sequence
Push-Pull Drive
Figure 8-21 illustrates a complementary push-pull drive
for a non-center tapped stepping motor driven from a 24
volt motor supply and a 15 volt logic supply. One of two
FIGURE 8-18 - STEPPING SEQUENCES"
"Clockwise Rotation as Viewed from the
Nameplate End of the Motor
MOTOROLA TMOS POWER MOSFET DATA
1-8-14
ever, requires about 300 ns of turn-on time. A 0.1 p.F
capacitor is placed across each winding so that the windings dv/dt is low enough to allow for diode turn-on without
avalanching the FETs. Winding currents are limited by the
9.0 ohm 5.0 watt resistors.
Switched Current Limiting
The circuit of Figure 8-21 uses resistive current limiting.
With 2.0 amps flowing in each winding, 4.0 amps will be
drawn off of the 24 volt supply yielding 96 watts of draw
with only 25% of that power being delivered to the motor.
Some form of switched current limiting is clearly desirable.
Figure 8-22 illustrates a simple switching scheme.
Starting with zero current flow, let the desired current
flow be left to right through the motor winding. Let the
referenced voltage Vref be 0.2 volts. Assuming RH > >
Rref, the positive comparator inputs will be approximately
0.2 volts. With no current flow, the sense resistors will
have no voltage across them and the comparators will
have high outputs; this enables the C1 and C2 inputs to
drive the P-Channel Power FETs. The proper C1, C2 input
for left to right current flow is 1,0. This turns the upper left
P-Channel and the lower right N-Channel on placing the
full power supply across the motor winding. Current 11
increases with di/dt = V/L. When 11 increases to 2.0
amps, the voltage across the lower right 0.1 sensing resistor will be 0.2 volts, and the lower right comparator will
go low after a short filter delay shutting off the upper left
P-Channel FET. The current through the motor winding
begins to decay around the 12 current path.
When the comparator went low, it shifted its positive
input reference down by about 70 mY. 12 decays until the
voltage across the 0.1 sense resistor falls below the hysteresis determined level; at that point, the comparator will
go high turning on the upper left P-Channel FET and
recharging the winding current along the 11 current path.
The winding current within the C1, C2 control envelope
increases to the reference level and oscillates around that
level at a value set by RH, Rref and the logic supply
voltage. The frequency of oscillation is set by V/L, the
hysteresis value and the current path resistances.
The circuit of Figure 8-22 places a negative voltage on
24Volts
24 Volts
R3
R2
Blsck
White
Green/While
Red/White
Green
Black
White
Green/White
Red/White
Green
so ===Ff1H
04
51
soo:====~J
Clock
(leading Edge)
51 0
Result
0.0
Hold
0.1
Shift Right
1,0
Shift Left
1,1
Motor
(leading Edge)
j
SO.Sl
Stepping
Clock
Control Signals
Control Signals
Preset
LogiC Levels are Standard
15V, CMOS
MC14194 Is a Standard 16 Pin DIP.
SO. Sl
Result
0.0
Hold
0,1
Shift Right
1.0
Shift Left
1,1
Preset
Parts:
1. Example Motor is M093·FC07 Manufactured
By Superior Electric
2. Diodes, 01-04, 1 N4002
3. R3.10n lOW
4. Rl. R2. 6.5 n 100 W
5. Integrated Circuit. MC14194 (CMOS)
6. Ql-Q4. MTM12N08 or MTP12N08
PARTS:
1. Example Motor is Superior Electric's
Model M093-FC07
2. Diodes. 01-04. 1 N4002 or Equivalent
3. R3,10nl0W
4. R1. R2. 6.5 n looW
5. Integrated Circuits, MC14194 (2 Required)
6. Q1-Q4, MTM12N080r MTP12N08
FIGURE 8-19 - CENTER-TAPPED
STEPPING MOTOR DRIVE
FIGURE 8-20 - HALF- OR FULL-STEP DRIVE
FOR CENTER-TAPPED STEPPING MOTORS
MOTOROLA TMOS POWER MOSFET DATA
1-8-15
•
the negative input terminal of the comparators during the
12 current path. This is not detrimental to the comparator
provided that the terminal current doesn't exceed a few
milliamps.
The complete logic circuit plus one of two required winding drive sections for a push-pull stepping motor with
switched current limiting is shown in Figure 8-23. Figure
8-24 is the corresponding parts list for the complete circuit.
The circuit of Figure 8-23 is limited to 8.0 amps continuous
with a motor power supply voltage of about 70 volts by
the specified P-Channel TMOS Power FETs. Thus, the
controller can handle up to 560 watts delivered to each
winding. Changes in RH, Rref and the sensing resistor
may be desirable for motors other than the example motor.
For low inductance motors driven from high voltage supplies with low levels of hysteresis, faster components in
the switched feedback loop may be required.
delivered to the M093-FC07. Calculations indicated that
greater than 50.0% of the control circuit power consumption was due to the S-D diode drop during the 12 current
loop (Figure 8-22). This drop could be lowered by operating the lower N-Channel Power FETs as synchronous
rectifiers. The additional logic required for synchronous
rectification amounts to three CMOS integrated circuits.
A complete logic circuit plus one of the two required winding drive sections is shown in Figure 8-25. Essentially, the
lower N-Channel is turned on when the upper complementary P-Channel is turned off by the comparator or
when the N-Channel control signal is high. The circuit of
Figure 8-25 yielded 88.4% efficiency at 2.0 amps/winding.
Further Possibilities
Shaping of the applied current waveform is often desirable. If a large stepping torque followed by a low holding
torque is desired, the required current waveform can be
applied to the positive comparator input. Within the comparator hystereSiS and the circuit's current response
speed, the current in the motor will follow the comparator
reference. The di/dt circuit response is limited by approximately Vmotor supply/Lmotor, provided that the series
resistance drops only a few percent of the supply voltage.
If current is allowed to decay without applying a reverse
supply voltage, current decay time will be set by the
Lmotor/Rdecay loop time constant.
In summary, the switching circuit of Figure 8-23 yields
79.0% efficiency at 2.0 amps/winding with faster current
response than the 25.0% efficient resistive current limited
circuit of Figure 8-20. Adding three CMOS integrated circuits to the circuit of Figure 8-23 yields the 88.0% efficient
circuit of Figure 8-25. The use of TMOS Power FETs and
CMOS logic in the designs of Figures 8-23 and 8-25 allowed high efficiency and considerable control flexibility
to be achieved without excessive parts count or undue
complexity.
Utilizing Synchronous Rectification
The circuit of Figure 8-23 required 26.4 watts to maintain 2.0 amps/winding with 78.8% of the drawn power
•
SO.SI
Result
0.0
Hold
0.1
Shift Right
1.0
Shift Left
1.1
Preset
Parts:
1.
2.
2xMCI4194(CMOS)
01-04. 4 x MTP8P08 or MTM8P08
(TMOS Power FETs)
3. 05-08, 4 x MTP12N08 or MTM12N08
(TMOS Power FETs)
4. 09-012,4 x MPS8099 (NPN Small Signal)
5. 2 x 9 Ohm 50 Watt Resistors
6. 4 x 0.6S kO 1/4 W Resistors
7. 4x 1.0kO 1/4WResistors
Example Motor: Superior Electric SLO·SYN Model
M093-1U07
FIGURE 8-21 - HALF- OR FULL-STEP RESISTIVE CURRENT
LIMITED DRIVE FOR STEPPING MOTORS WITHOUT CENTER-TAP
FIGURE 8-22 - COMPARATOR SWITCHED CURRENT LIMITING
MOTOROLA TMOS POWER MOSFET DATA
1-8-16
Integrated Circuits
1.
2.
3.
2 x MC14194B. CMOS 4·Bit Shift Register
1 x MC14081B. CMOS Ouad "AND" Gate
1 x LM339N. Quad Comparator
TMOS Power FET.
1.
01-04. 4x MTP8P080r MTM8P08. P·Chennel
Power FET
2.
05-08. 4x MTP12N08 or MTMI2N08. N·Channel
Power FET
Transistors
1
09-012.4 x MPS8099. NPN Small Signal
Transistors
Resistors
1. 4 x 0.1 n 2.0 W
2. 4 x 6BO n 114 W
3. 5x 1.0kn 1/4W
4. 2 x 10 kn 1/4 W
5. 1 x 30 kn 1/4 W
6. 1 x 30 kn Adjustable. 1/4 W
7. 6x l00kn 1/4W
8.
2 x 22 Mn 1/8 W
Zener Diode
1
SO. 51
Capacitors
1. 3xO.l
Result
0.0
Hold
0.1
Shift Right
1.0
Shift Left
1.1
Preset
1 x IN, 2 V Reference
2.
FIGURE 8-24 -
FIGURE 8-23 - HALF- OR FULL-STEP SWITCHED CURRENT DRIVE
FOR STEPPING MOTORS WITHOUT CENTER-TAP
H Bridge Performance Comparisons
Power MOSFETs are excellent candidates for low voltage H Bridges. In this example, MOSFETs are compared
with two other popular alternatives, bipolar discretes and
bipolar Darlingtons. Circuits were designed for all three
types of output power devices. Each circuit design is optimized for the output device used.
General "H" Switch Design Considerations:
• P.M. DC Motor, 2.0 A run, 15 A stall/start.
• 12 V protected bus, 32 V max peak, 14 V nominal.
• "H" switch input, 2.0 mA max sink reqlolirement.
• Discrete driver stages (for comparison of designs).
• Maximum ambient temperature of 100°C, maximum
junction temperature = 150°C.
• Off the shelf type output power devices using maximum data sheet limits to calculate drive requirements and forward "on" voltage levels. The power
output devices were chosen such that die sizes for
the three types are approximately equal.
~F
l00V
4 x 50 pF 50 V
PARTS LIST FOR CIRCUIT OF FIGURE 8-23
Discrete Bipolar "H" Switch
TlP35 and TIP36 power transistors were selected for
their low cost and high current capacity. The high currentgain specification for these units results in base drive requirement of 1.5 amperes to switch a 15-ampere load
current. It may be that base drive can be reduced by 30
percent if the units are screened for high-current hfe, but
for this design comparison, only "off-the-shelf" standard
devices with the regular data-sheet specifications are under consideration.
The bipolar "H" switch design requires medium size
driver transistors and large-wattage voltage-dropping resistors in the base-drive circuit. A buffer stage is also
required. The control lines are shown tied to a SPOT
center off switch. In an actual circuit, this switch would be
a logic array or a microcontroller output network. A protective counter-EMF voltage clamp is provided by the
back-to-back Zener rectifiers. The Darlington and TMOS
units have built-in clamp diodes and for many applications
would not require the zeners. CapaCitor and resistor snubbing networks may be required with all three types output
devices.
As indicated in the performance table, the bipolar design is not very practical because of the large base drive
requirement. Of the three power devices, it is the least
efficient by a wide margin. In most situations, FETs or
Darlingtons are a better choice.
MOTOROLA TMOS POWER MOSFET DATA
1-8-17
50,51
Result
0,0
Hold
0,1
Shift Right
1,0
Shift Left
1,1
Preset
Parts in Addition to Figure 8, 1 x MC14049UB,
1 x MCI4081B, 1 x MC14071B
FIGURE 8-25 - HALF· OR FULL-5TEP SWITCHED CURRENT DRIVE WITH SYNCHRONOUS RECTIRCATION
VCE(sat) = 1,8 V @ 15 A, IB = 1,5 A
VCE(sat) = 0,4 V @ 2,0 A, IB = 1,5 A
Base Drive PD = 14 V x 1,5 A
= 21 W
MTRPO = 10.4Vx15A
= 156W
MTR PD = 13.2 V x 2,0 A
= 26.4W
EFF
= 75 ~6156' 75 = SW Po +
Base Drive Po
= 67.5% at stall condition
EFF
=
26.4
22.6 + 26.4
= 53.8% at nominal run condition
+14V
0.002 A
~2.0k
2.0 k
6.2 k
6.2 k
OFF
4
1
R
5
FIGURE 8-26 - "H" SWITCH BIPOLAR CONTROL CIRCUIT
MOTOROLA TMOS POWER MOSFET DATA
1-8-18
Discrete Darlington "H" Switch
peres for this dc control, and can be derived from a single
voltage pump-up circuit using TMOS gates and voltage
doubling networks.
Motorola MJ4030 and MJ4033 power TO-204 (TO-3)
Darlingtons were chosen for the Darlington version of the
H bridge. As the chart shows, the drive-power requirements are substantially reduced from the bipolar power
design. The tradeoff is that the forward "on" voltage is
raised to such a high level that this particular motor will
no longer be within its terminal voltage specification during
stall or start-up. Also, the Darlington's dissipation will require a larger heat sink than the bipolar design. The Darlington does provide internal clamp diodes.
The Darlington "H" switch design works best in highvoltage, low-current load control circuits where the Darlington's high saturation power loss is not significant.
Test Measurement Calculations
The following equations were used to determine the
circuit performance values for this example,
1. MOTOR POWER CONSUMPTION - The applied
voltage across the motor load-terminals multiplied
times the normal motor current.
PD(MTR) = 1.0 x (VBATT - 2.0 x VF(on))
1= 2.0 AMPS RUN MODE 1= 15 AMPS STALL
MODE
VF(on) = VCE(sat) or VDS per data sheet
Power TMOS "H" Switch
An MTP25N05 Power FET was chosen for this design.
Since the die size falls somewhat shy of the bipolar and
Darlington device die sizes, an adjustment was made in
the conduction loss calculation. Actual VDS(on) measurements were scaled according to the area ratio In order
to arrive at the numbers presented here. As the comparison chart reveals, the TMOS design is clearly superior
to the bipolar and Darlington designs. Its only technical
drawback is the 34 volt bias supply requirement. This
supply only has to source approximately 200 microam-
VCE(sat) = 3.0 V @ 15 A, IB = 0.08 A
vCE(satl = 1.1 V @ 2.0 A, IB = 0.08 A
Base Orive Po = 1.12 W
MTR Po = 8.0 V x 15 A
= 120W
MTR Po = 11.8 V x 2.0 A
2. OUTPUT DEVICE POWER DISSIPATION
PD(sw) = (I x VF(on)) x 2.0
3. "H" SWITCH CONTROL EFFICIENCY
EFF = Power Out
Power In
Power Out = PD(MTR)
Power In = PD(sw)
EFF =
+
PD(MTR)
120
91.1 + 120
57% stall mode
=
EFF=~
5.3
+ 23.6
= 81% run mode
= 23.6W
+14V
Y
MJ4030
2.0 k
2k
MPSA70
0.002A
(
I
-I-"
6.2 k
0.007 A')
"
2.0W
100
3.9 k
---t::
,IIIPSA70
1
r
(0.08
~
"
MJ4030
2N3903
AII'
II'
~
12 k
~., I
MJ4033
2N3903
MJ4033
OFF
F
FIGURE 8-27 -
1
R
"H" SWITCH DARLINGTON CIRCUIT
MOTOROLA TMOS POWER MOSFET DATA
1-8-19
100
2.0W
MJ4030
1
-
"",....,
I
3.9 k
>-
-
12 k
6.2k
183
VOS(on) = 0.9 V @ 15 A, VGS = 20 V
VOS(on) = 0.12 V @ 2.0 A. VGS = 20 V
BIAS CIRCUIT Po = 0.01 W MAX
MTR Po = 12.2,2.0 V x 15 A
= 183W
MTR Po = 13.76 V x 2.0 A
= 27.5W
EFF = 27
=
EFF
+ 183
87% STALL MODE
27.5
0.48 + 27.5
=
= 98% RUN
MODE
-<
+34V>-......-""'\.
. r - -......
+34 V
680 k
+34V-+f)
200 k
~ :a~; I
200 k
100 k
100 k
i
fl
o-R_ _
FIGURE 8-28 - "H" SWITCH POWER TMOS CIRCUITS
"H" SWITCH DESIGN COMPARISON CHART FOR AUTOMOTIVE MOTOR LOAD
54%
68%
13.2 V 10.4 V High base current required
Darlington
200
SOV
16A
1.1 V
3.0V
1.1 W 4.2W
90W
81%
57%
11.8V
TMOS
176
40 V
20 A
0.12 V
0.9 V
0.01 W 0.48 W
27 W
98%
87%
13.8V 12.2V 34 V 200 pA Bias supply
required
Bipolar
NOTES:
1)
2)
3)
4)
Bipolar devices are TIP35 and TIP36 TO-218 plastic NPN and PNP
Darlington devices are MJ4030 and MJ4033 TO-204 (TO-3) metal NPN and PNP.
TMOS devices are MTP25N05.
Figures shown above are the worst case data sheet ccndition for the parameter calculated.
MOTOROLA TMOS POWER MOSFET DATA
1-8-20
8.0 V.
Large forward voltage drop
Bidirectional Control of Fractional
Horsepower Motors
The Darlington transistors sense the motor's counter
EMF (via the 20 V snubber zeners that become forward
biased when the motor's back EMF appears) and shunt
the drive-reversal signal to ground until the back EMF
decays. The transistors will hold the gate-drive line low
until the counter EMF drops below the base-to-emitter
threshold voltage. This action causes the circuit to wait
until the motor nearly stops rotating before applying reverse voltage. If faster response times are needed, the
Darlingtons can be eliminated while connecting the 1.0
Mil base resistors to ground - this change, however,
would necessitate higher current MOSFETs because of
the large peak-reversal currents that would ensue.
Figure 8-30 shows the dramatic difference in the peak
currents that occur with and without the back-EMFsensing feature. With the sensing circuit disabled (a), the
currents exceed 50 A; the resulting MOSFET dissipation
is approximately 140 W. Enabling the circuit (b) reduces
the currents to approximately 30 A and the MOSFETs'
dissipation to about 14 W. A 16 V zener diode limits the
input voltage to the flyback inverter in case the supply
By using power MOSFETs in Figure 8-29b's circuit,
fractional-horsepower motors can be driven bidirectionally
with only a small percentage of the base-drive power that
bipolars require. Moreover, by sensing the motor's back
EMF and delaying drive-voltage reversal, the circuit
reduces the peak currents encountered during motor
reversal. This feature allows the use of lower current
MOSFETs than an instantaneous-reversal method would
dictate.
A basic H switch, Figure 8-29a reverses the motor's
supply voltage for bidirectional control. In Figure 8-29b's
circuit, two pairs of N-channel MOSFETs serve as the CW
(clockwise) and CCW (counterclockwise) switches. A
flyback-type dc/dc inverter, composed of a CMOS hex
inverter and a small signal MOSFET, drives the FET
switches. The 3-inverter oscillator operates at 240 kHz;
the three remaining inverter's average output tracks the
power-supply input, ensuring adequate gate-bias voltage
even for input-supply voltages as low as 6.0 V.
+1
r-----------..-:==:-:::::::--.--......--o Supply
1+
CW~M
CCW
"'v---'I-"
Motor
fCW
CCWi
MR2530L
28 V Suppressor
lOOk
..-'2\11
0
lN5250
(a)
1.0 M
2N6427
1.0 M
2N6427
CWoffCCW
100 k
DPDT (Center Off)
0.1 JJoF
14 V, 0.01 A
~--------~JYrr~~----------~ICVCC
Flyback Inv. Waveforms
(b)
FIGURE 8-29 - DRIVE FRACTIONAL-HORSEPOWER MOTORS
EFFICIENTLY WITH THIS POWER-MOSFET H-BRIDGE CIRCUIT. 11:
DISSIPATES MUCH LESS POWER THAN A BIPOLAR-TRANSISTOR
DRIVER - MOREOVER, IT ALLOWS THE USE OF LOW-CURRENT
MOSFETs BY DELAYING REVERSAL VOLTAGE UNTIL THE MOTOR
COASTS TO A STOP.
MOTOROLA TMOS POWER MOSFET DATA
1-8-21
rises higher than 16 V; the transient suppressor protects
the MOSFETs from supply spikes greater than 28 V.
In this design, the MOSFETs require heat sinking to
keep their junction temperatures less than 150°C in worstcase conditions (that could occur, for example, with a
16 V supply, 100°C ambient temperature and a stalled
motor). As an option, a current-sensing circuit can be
added to gate-off the power FETs after detecting a stall
condition.
PWM Motor Speed Control
FETs can be used to considerable advantage for simplifying permanent-magnet motor speed control. The circuit shown in Figure 8-31 provides efficient pulse-width
modulated control with a minimum number of components. The key feature is direct drive of the power FET
from a CMOS control IC. The result is a control system
with minimized parts count.
The control system is based upon the MC145288 dual
monostable multivibrator. One-half of the monostable is
connected in an astable mode, producing a pulse oscillator. The remaining half is then used as a one-shot, with
its adjustable pulse-width determining the duty cycle and,
therefore, motor speed.
In addition to its simplicity, the circuit of Figure 8-31 is
notable for its low standby power drain. The combination
CMOS control and TMOS power gives a very low quiescent current drain that is desirable in battery operated
applications.
BACK EMF SENSE
CIRCUIT DISABLED
PEAK CURRENTS> 50 A
POWER DIS. = 140 W
10 AlDIV
BACK EMF SENSE
CKTENABLED
PEAK CURRENT
~
30 A
POWER DIS. = 14 W
10 AIDIV
(b)
1.0 SECIDIV
VERTICAL
HORIZONTAL
10 AlDIV
1.0 SECIDIV
, FIGURE 8-30 - COMPARISON OF "H" SWITCH PEAK CURRENTS
DURING MAXIMUM FORWARD TO REVERSE SWITCHING WITH
MANUAL TOGGLE SWITCH
MOTOROLA TMOS POWER MOSFET DATA
1-8-22
Horizontal Deflection Circuits
be added to compensate for the storage-time delays in
the horizontal output stage. The active video data time
may also be cut back, accordingly, to allow for internal
horizontal timing delay.
Based upon these considerations, effective use of the
bipolar transistor at high scan frequencies requires a complex base drive circuit, custom selection of the bipolar
device for minimum storage-time variation, and an accurate phase locked loop to compensate for saturation
time delays. Power MOSFETs, on the other hand, can be
driven from a CMOS IC, do not require critical parameter
screening, exhibit minimal turn-off delay, and do not require a phase locked loop for correcting device-induced
timing errors.
Power MOSFETs can be a good alternative to bipolars
in high resolution CRT sweep circuits. The most obvious
advantage is simplicity. However, MOSFET horizontal
outputs also offer significant benefits in terms of increased
reliability and faster switching times.
Drive simplification with the MOSFET is even more significant than in the preceeding switching power supply
examples. In most cases, a base-drive transformer is eliminated, as well as di/dt wave shaping networks.
The reliability issue is a little more complex, and relates
to differences in SOA characteristics. It is normal design
practice to exceed bipolar collector-emitter breakdown ratings during the retrace pulse transition. This is permissible
if the base-emitter voltage is held negative during the
retrace period. If, however, a positive noise pulse occurs
during the retrace period, the bipolar base-emitter junction
can become forward biased when collector-emitter voltage is greater than VCEO(sus). The bipolar's safe operating area is then violated, creating a substantial risk of
failure. MOSFETs, on the other hand, will handle this type
of stress quite readily, since their FBSOA capability extends beyond peak retrace voltage. Therefore, increased
reliability with the MOSFET horizontal output is directly
related to the probability of noise occurring in the drive
circuitry.
Speed is also an important issue. At a 30 kHz scan
rate, 1.0 j.LS of bipolar sto~age-time delay represents 3%
of the horizontal line period, or a loss of 30 lines of data
in a field of 1024 lines. In addition, bipolar storage time
is not a fixed constant, but changes from device to device
and with temperature. A horizontal phase locked loop can
Design Example
The power MOSFET, until recently, could not handle
much current at voltages above 500 V. Recent technology
developments have pushed this limit up to the 1000 V
range with increased current ratings. Therefore, a power
MOSFET can now be selected for computer CRT display
systems with power supply requirements ranging from
12 V to 75 V.
The standard horizontal raster scan system is used in
this design. That is, the horizontal yoke and flyback transformer are both switched by one output device. It should
be pOinted out that the power MOSFET has been switched
up to 120 kHz scan rates, but due to other device constraints, the CRT anode high voltage network's performance is very marginal at this high frequency rate. Even
a scan frequency of 30 kHz is pushing the limits of the
high-voltage rectifier and associated components.
On/Off
lN5246 16 V
-=
1.0 k
2.0 k
,,
+14V
I
, adj
50kl sPd
0.1/L F
10 k
1.0 M
MR2525L 28 V
MC14528B
+--+0lIl1--.....,
lN918
Power MOSFET
15 k
S
FIGURE 8-31 - POWER
MOSFET MOTOR SPEED CONTROL CIRCUIT
MOTOROLA TMOS POWER MOSFET DATA
1-8-23
MTP5N05
2.0 A MTR
MTP15N05E
6.0 A MTR
MTP25N05E
15 A MTR
The design concept is shown in the block diagram of
Figure 8-32. The horizontal drive signal can be supplied
by a free running synchronous clocked oscillator or by
external computer logic. The safest method is to use a
free running synchronous oscillator to insure the horizontal frequency is held within safe limits. There are several
horizontal processor linear integrated circuits containing
a phase detector, oscillator and predriver available. A partial list includes SGS TDA1180 and Motorola MC1391.
None of these devices are presently designed to drive a
MOSFET power unit directly; so some type of an interface
or buffer circuit is required. Three power MOSFET drive
circuits are shown in Figure 8-33. These circuits perform
adequately in the horizontal system described here.
..
Circuit Description
The design presented in Figure 8-34 eliminates the
driver transformer, driver transistor, and associated passive components that would normally be found in a bipolar
design. A MLM311 comparator is used to invert and levelshift the incoming positive going synchronous pulse. The
comparator output is ac coupled to the MC1391 horizontal
processor which consists of a phase comparator and voltage controlled oscillator with adjustable duty cycle. The
phase comparator of the MC1391 is connected to the
incoming conditioned horizontal synchronous pulse and
the output of the MC1391 's internal oscillator. An error
voltage is applied to the oscillator timing control voltage
to lock in the external synchronous pulse and the ,oscillator. The duty cycle of the MC1391 oscillator output is
set to provide a 63% "ON" time to the power MOSFET
gate.
'
Essentially, the prime requirement for driving the power
MOSFET for this horizontal scan output design is to insure
sufficient gate on-voltage and low enough impedance for
a fast turn-off transition. Since the power MOSFET has a
high gate input impedance, the gate voltage requirement
is easily met, with little wasted power. The off transition
requires that the power MOSFET's internal 1000 pF gate
capaCitance be discharged very quickly. This is accomplished by using a single hex inverter IC, with all the gates
wired in parallel. As mentioned before, other devices can
be used to drive the MOSFET. The CMOS inverter was
chosen to show that CMOS technology is sufficient to
drive the MOSFET.
The system described above provides excellent performance. The gate-drive voltage of the power MOSFET
was purposely pulsed during the peak retrace drain voltage pulse to simulate destructive transients due to anomalies such as arcing.
It was found that a controlled drain-to-source current
occurred, with no catastrophic failures, as long as the total
power dissipation was held within the limits of the power
FET's safe operating area ratings. Figure 8-34 shows the
waveforms associated with the retrace pulse test. Since
the MOSFET is a high input impedance device, it is important to insure the gate of the power MOSFET is at a
low impedance during the retrace period. The gate should
not be driven negative, to minimize the possibility of voltage spikes causing gate avalanche. The gate cannot withstand an avalanche condition of any measurable current
intensity and survive. Since the power MOSFET device
selected for this design exhibits at least a 2.0 volt threshQ,ld, a negative gate-drive is not important.
+
+12V
.--1--"'-<1 H.V.
Power
MOSFET
Sync
Horiz. Processor
Gate
Driver
Ly
Horiz.
Phasing
FIGURE 8-32 -
POWER MOSFET HORIZONTAL OUTPUT SYSTEM
MOTOROLA TMOS POWER MOSFET DATA
1-8-24
Figure 8-35 shows a comparison of the key horizontal
output circuit waveform patterns between a bipolar and
MOSFET design. Note the large reduction in the horizontal output drive power and lack of storage time in the
MOSFET design.
such transistors require power transistors as drivers and,
when driven by a low-voltage source, sacrifice switching
speed.
Yet a third possible solution - paralleling fast, lowcurrent transistors - presents two problems: current sharing and physical layout.
The MOSFET driver circuit in Figure 8-36 uses two
N-channel devices with positive and negative polarities.
Fast transitions are possible, even when a low-voltage
source is used. The circuit returns to 0 V between pulses,
an important feature when driving high-power Darlington
transistors with base-bias resistors and speed-up diodes.
In this case, excessive heating would otherwise occur
during the off-time interval.
Small size, simple configuration, and minimum component count join with ease of operation to make this driver
circuit very useful for applications in variable-frequency
switched-mode power supplies, and inverters.
In operation, a single-polarity, negative-going pulse
from a pulse generator is applied to the input. The pulse,
whose width can vary anywhere from 5.0 !JS to 3.0 ms,
turns on PNP predriver transistors Q2 for the positivepolarity output.
Fast High-Current MOSFET
Driver
A totem-pole MOSFET driver circuit shines when highcurrent, fast-transition pulses must be generated from lowvoltage sources. Its MOSFETs sidestep a number of problems that their bipolar counterparts present in the same
circuit.
High-speed transistors and high-current transistors intended for PWM applications have created a need for
high-current, fast-drive circuits. Transistors that demand
20 to 35 A of reverse base current for rapid turn-off and
can be driven by as little as 5.0 V of off-voltage are a
common requirement. Bipolar devices switch in nanoseconds but are limited to 5.0 to 10 A when driven from lowvoltage collector supplies. With higher current capability,
+12V
+12V
8
1.0 k
VCC
5.0 V Pulse
2.0 k
>---"oJ.......---......;.
MPS5172
Out
1-3'--_---I~
1.0 k
Discrete
Linear Bipolar IC
MC1455
+12V
Horiz.
r - - - - i Output
D
Circuit
MOSFET Output
MTM8N20 thru
MTM5N100, etc.
5.0 V Pulse
S
FIGURE 8-33 -
MOSFET DRIVE CIRCUITS
MOTOROLA TMOS POWER MOSFET DATA
1-8-25
+24V
"--------------------:2-------------------------------------------,
I
I
.
I
I
In
G
I
I
-=
I
12 V I MC78L12
Out
+12~
+12V
I
:t
I
L
I
I
160
I
§
I
Freq. Adj.
2.0 k
20 k
s::
t
0)
1.0 k
0
CJl
"U
7
0
::m
I
I
~
-=
CJl
"T1
»?:i
~ CRT Anode V.
~
I--- CRT Control V.
7
3
4
6
~1.0k
0
0
t'
MCI391
4
s::
-l
Horiz. Flyback
& High Voltage
Network
0.01 p.F
:II
m
I
I
I
I
I
I
2.7 k
s;:
....
10p.F
MLM311
0
:II
0
-l
+75V
I
I
II
I
I
I
I
tr
O.o1.L
p.F
500
5.1 k
TV Horizontal
Processor
Phase Adj.
2.4,6
10,12,15
3,5,7
9,11,14
MCI4049B
10
-=
-=
(All Inverters
Wired in Parallel)
II
-I
I
,------------------------------------------------------------------~
1
Power MOSFET
Select Device Type
Per Voltage & Current
Requirements.
FIGURE 8-34 - POWER MOSFET HORIZONTAL SWEEP DESIGN
/=.
Horiz. Yoke
Network
~
. . - - - - - - - - - - - - - E X T R A IINJECTED) HORIZ. DRIVE PULSE
GATE DRIVE
VGS
10VIDIV
VDS
100 VIDIV
HORIZ. FlYBACK PULSE
10
10 A1D1V
HORIZ. OUTPUT DEVICE CURRENT
t
2.0 I'SiDIV
, . . - - - - - - - - - - - - - - - - - - PULSE ADJUSTED TO COINCIDE
DURING PEAK OF FLYBACK PULSE
VGS
10VIDIV
VDS
500 VIDIV
10 AIDIV
t
2.0 I'SiDIV
. - : : - - - - - - - - - - - - - - - - - - A S A B O V E . EXCEPT PULSE WIDTH
EXTENDED TO 1.0 1"
VGS
10 V1DIV
VDS
500 VIDIV
I
10 A1DIV I
t
2.0 I'SiDIV
FIGURE 8-35 - HORIZONTAL DEFLECTION RETRACE PULSE TEST WAVEFORMS
MOTOROLA TMOS POWER MOSFET DATA
1-8-27
BIPOLAR
toft = 3.5 JLS
MOSFET
toft = 155 ns
versus
Video
Video
18
. 1.0 AlDIV
IG
1.0 AlDIV
IC
5.0 AlDIV
10
5.0 AlDIV
VDS
500 VlDIV
VCE ,
500 VIDIV
10!'SiDIV
Complete Waveforms
I
Video
Video
-
__
:
I
I
I:
18
IG
•
IC
1.0 !'SfD1V
1.0!'SiDiV
Time Expanded
IG
0.5 AlDIV
Note:
External Damper
Rectifier left
in ckt to minimize
ringing during start
of negative yoke current
10
1.0 AlDIV
MOSFET CURRENTS EXPANDED
TURN·OFF WAVEFORMS
FIGURE 8-36 - BIPOLAR versus MOSFET
MOTOROLA TMOS POWER MOSFET DATA
1-8-28
I
I
+ - _I
_
ration of the negative drive. The negative voltage remains
for about 10 J1S and then returns to zero, completing a
single cycle.
The circuit can be used with FETs by replacing Rb with
a short and the positive and negative voltages applied to
the devices' gates. For controlled gate-impedance drive,
resistors can be inserted in series with the gates. Similarly,
a resistor added in series with the base of the bipolar
transistor ~esults in controlled base-current drive.
Resistor Rb, inserted in series with the drain lead of 02
and the supply, sets the positive drive level. The resistor
should be selected for a drive of 10 V or greater as well
as the amount of desired current.
After the required on-time of the positive output current,
the pulse generator returns to zero. Then, the RC differentiator network applies a positive voltage to the gate of
MOSFET 03, which supplies the negative polarity output.
The values shown can be changed to lengthen the du-
+v
10
0-,
-v U
+
r
10 Il-F
10
Output
Input
50
'::'JU+v
Q3
MTM 0
r-________~--I~-t12N10
R
500
2.0 Il-F
-V
100
-v
FIGURE 8-37 -
MOSFET DRIVER CIRCUIT
MOTOROLA TMOS POWER MOSFET DATA
1-8-29
MOTOROLA TMOS POWER MOSFET DATA
1-8-30
Chapter 9: Spin-Off Technologies of TMOS
SENSEFETs ™
This concept is illustrated in Figure 9-1a, where sense
current and load current are related by the ratio 1 :n, provided that the sense terminal and the source terminal are
returned to the same potential. When a sense resistor is
placed between these two terminals, the ratio is disturbed
somewhat, but remains quite predictable for low values
of RSENSE. A shorthand symbol for the SENSEFET, and
a connection for RSENSE are shown in Figure 9-1b.
Some of the more exciting developments in discrete
power semiconductors are arising from power Ie concepts. Integrated circuit design engineers, with fine geometries and ratioing techniques as standard tools of the
trade, are applying these concepts to discrete power semiconductor design with great success. One notable example is SENSEFETs.
By splitting drain current into power and sense components, these new devices feature a "Iossless" current
sensing technique for discrete designs. The intention of
this chapter is to explore the concept, device characteristics, and the state-of-the-art performance that SENSEFETs can provide.
The circuit model and equations shown in Figure 9-2
describe SENSEFET behavior during fully switched on \
operation. From the equations, one can easily calculate
the sense resistance required for a given sense voltage.
Although any value of sense resistance can be used, two
considerations are worth noting: (1) as RSENSE
increases, VSENSE asymptotically approaches a maximum voltage magnitude equal to 10· rA(on)' and
(2) sense voltage accuracy over the operating temperature range severely degrades with increasing sense resistance. From a practical point of view, relatively good accuracy is maintained when RSENSE < rM(on)/2.
Lossless Current Sensing
"Lossless" current sensing is a technique that arises
from integrated circuit ratioing concepts. It is based upon
the tendency of individual source cells in a monolithic
power MOSFET to match. Therefore, if one or two out of
several thousand cells are returned to a separate sense
or mirror connection, a ratio between load current and
sense current is developed.
Drain
Drain (D)
1:n
Gate (G)
0--_----'
Mirror
Sense (M)
Source (S)
RSENSE
+
Kelvin
VSENSE
(a) Schematic Representation
r-1orain
rw
S
Source
Gate 0 - - - - - - - - - '
Sense
+--..----------'
VSENSEj
Source
rb Cl! bulk resistance
rA(on) Cl! source cells on-resistance
rM(on) Cl! sense cells on-resistance
~ source wire bond resistance
RSENSE Cl! external sense resistance
(1) rM(on) = n rA(on) where n Cl! geometriC current mirror ratio
(2) VSENSE = 10' rA(on)' RSENSE I [RSENSE + rM(on)]
(3) RSENSE = vSENSE' rM(an) I [10' rA(on) - VSENSE]
(4) 10 = VSENSE' (RSENSE + 'M(on)) I rA(on) • RSENSE
rw
RSENSE
+ - -.....- - - - - - - - - .
(b) Typical Connection
FIGURE 9-2 FIGURE 9-1 -
FUNCTIONAL REPRESENTATION
SENSEFET ON-RESISTANCE MODEL AND
ASSOCIATED EQUATIONS
MOTOROLA TMOS POWER MOSFET DATA
1-9-1
In linear operation, RSENSE is in series with a current
source, .and does not directly attenuate sense current.
Instead it is likely to have a first order influence on gatesource bias voltage. Since sense voltage subtracts from
the sense cell's gate source voltage, sense cell current is
reduced with respect to current in power section cells.
Therefore, there is a debiasing effect which alters the 1:n
sense .ratio as a function of RSENSE. Similar to switchmode operation, moderate values of sense resistance alter the sense ratio in a predictable way, resulting in a
useful measurement.
Accuracy
Accuracy for a current sensing technique can be looked
at in a number of different ways. Of most concern in
switching applications are the linearity, temperature coefficient, and unit to unit variations that occur when the
power device is fully switched on. These parameters are
illustrated for the MTP10N10M, a 10 Al100 V SENSEFET.
LINEARITY: At any given drain current, a corresponding
sense voltage can be chosen by scaling RSENSE. As
drain current, 10, changes from this baseline, linearity
measures the accuracy with which the VSENSE/10 ratio
holds at other currents. For example, at 10 A a 20 n sense
resistor typically sets VSENSE at 116 mV for the
MTP10N10M. A linear response would suggest a reading
of 58 mV at 5 A, which corresponds very nicely to a
measured value of 58 mV. On the other hand, if RSENSE
Sense Vo"age
@20mV/div
•
(8) RSENSE
= 20 0
TC = 25"C Upper Trace
TC = 125"C Lower Trace
Peak Drain Current = lOA
is increased to 2 kn the results turn out somewhat different. At 10 A VSENSE measures 1420 mV, implying a
5 A reading of 71 0 mV. However, measuring sense voltage
at 5 A results in a 618 mV data point. The difference
amounts to 15%, and points to a more accurate measurement with lower values of RSENSE.
TEMPERATURE COEFFICIENT: A graphic representation
of temperature stability is shown in Figure 9-3. For this
figure drain current is ramped from 0 to 10 A. The photos
are double exposures with one shot taken at 25°C and
the other at 125°C. As with linearity, the best results are
obtained with a sense resistor that is small with respect
to the sense cell's on resistance, rOM(on). With 20 n,
temperature tracking is essentially within a trace width,
and the two values diverge by only 4% at 10 A. As
RSENSE is increased, temperature coefficient becomes
less dependent upon matching and more a function of the
power device's on voltage. In the limit where RSENSE is
very large, sense voltage approximates the power device's VOS(on) and tracks its temperature coefficient. This
tendency IS quite evident in Figure 9-3b, where at
RSENSE = 2 k the two measurements diverge by 45%
for a 100°C change in temperature.
TOLERANCE: The parameter that describes tolerance for
a SENSEFET is the cell ratio, n. It is defined for RSENSE
= 0 and measures the ratio of source current to sense
current without the attenuation of a sense resistor. First
generation specifications guarantee that n will fall within
a ±10% window.
As sense resistance is increased from zero, the apparent cell ratio increases by approximately the ratio of
RSENSE to the sense cell's on-resistance, rOM(on). Tolerance also increases with increasing values of RSENSE,
as sense current becomes increasingly dependent upon
VOS(on) and less upon ratioing. In the limit, large values
of RSENSE produce an initial tolerance which varies
directly with VOS(on). In this situation tolerance degrades
from better than 10% with RSENSE <
I
I
N+
I
I
Polysilicon Gate
Gate Oxide
JRCHANNEL ~.--RACC
1-----RACC
Source Metallization
I
I
N+
RCHANNEL\..
~
J
!
RJFET
P
----
P
r-----
"-
RORAIN
)
N - Epitaxial
(
)
I
N+
I
FIGURE 9-10 - THE COMPONENTS OF ON-RESISTANCE IN A HIGH- OR LOW-VOLTAGE MOSFET ARE CHANNEL RESISTANCE
(RCHANNEL), DRAIN RESISTANCE (RDRAIN), JFET RESISTANCE (RJFET), AND RESISTANCE OF THE ACCUMULATION REGION
(RACC)' LOWER ON -RESISTANCE VALUES ARE EASIER TO ACHIEVE IN LOW-VOLTAGE DEVICES, WHERE CHANNEL RESISTANCE
MAKES UP ABOUT 70% OF THE TOTAL RESISTANCE IN A POWER-MOSFET CELL.
The lower maximum VDS rating of low voltage devices
allows using an n-epi with a much lower resistivity. Although there is no clear definition of what constitutes a
"high" or "low" voltage device, at a maximum VDS rating
of about 200 volts, the significance of the drain resistance
begins to dwindle and the importance of the channel resistance, the resistance of the accumulation region, and
the JFET resistance begins to dominate. Especially for
MOSFETs with voltage ratings less than 100 V, efforts
directed at reducing these resistances pay big dividends.
These dramatic changes in the silicon area necessary
to provide a given on-resistance are a bonanza for power
MOSFET users. Designers now have the pleasant task
of deciding how to use the device improvements. They
may, for instance, choose to greatly minimize on-state
losses by replacing first or second generation devices with
second or third generation units that have the same die
size. With the conductivity of a given chip size increasing
nearly fourfold in some cases, designers can drastically
reduce heat-sinking requirements and greatly improve
system efficiency.
The second option open to the designer is to select
replacements on the basis of their on-resistance or current
ratings. This entails using a device with a much smaller
die. Since much of the cost of a power transistor is associated with processing of silicon wafers, the use of
smaller chips means lower component cost.
One very enlightening illustration (Figure 9-11) allows
easy comparison of the typical on-resistance associated
with a TMOS I, II, III and IV chip. The original TMOS
MTP15N05 requires 150 x 150 mil2 of silicon to yield a
typical 135 MO on-resistance. With TMOS II technology,
on-resistances are pushed down to 125 mO, with only
115 x 115 mil2 , about a 40% savings in silicon. Even with
a 60% reduction in the original TMOS die area, TMOS III
technology makes possible the added bonus of a 30%
drop in rDS(on).
Almost as impressive as the performance gains is the
rapid pace at which these changes are occurring. At the
beginning of 1984, few realized that such dramatic
improvements were possible, and virtually no one predicted the introduction of radically superior devices. Since
each new generation delivered much greater perfor-
Comparison of On-Resistance
In 1986, TMOS IV was introduced with a series of products called E-FETs. This product had all the advantages
of TMOS III products but ruggedness was added.
Much has already been said about greater conductivity
per unit area of silicon being the strength of the newest
generation of power MOSFETs. But an appreciation of
just how far device designers have furthered their art in
this respect comes only after a review of some of the
rDS(on) versus die size data.
FIGURE 9-11 - FOR A GIVEN DIE SIZE, ON-RESISTANCE HAS
FALLEN DRAMATICALLY DURING 1984
MOTOROLA TMOS POWER MOSFET DATA
1-9-9
mance, the year was marked with the need for an almost
continuous re-evaluation of the utility of low voltage power
MOSFETs.
A second way to demonstrate the greater efficiency of
the latest chip designs is to monitor case temperature rise
in a typical application. This type of empirical evaluation
is useful because it automatically includes the effect of
practical considerations such as the influence that TJ has
on rOS(on) (Figure 9-12). Since the intent of this exercise
is to compare on-state losses in a typical application, a
good test vehicle is a resistive load switched at a relatively
low frequency (4 kHz). Table 1 lists die size information,
typical rOS(on) values at 25°C, and steady state temperature readings during the 10 A, 14% duty cycle load test.
The purpose of the table is not only to show that the case
temperature rise predictably tracks the on-resistance
data, but also to illustrate that even though the TMOS III
die is much smaller, its power consumption is very moderate compared to the other devices. Advances of that
proportion are normally restricted to the discovery of entirely new technologies and are not usually associated
with improvements in existing techniques.
200r--,--r--r-;r-,--,--,--,
175
Several other parameters of power MOSFETs vary from
generation to generation. Most notable are lower overall
capacitance and junction-to-case thermal impedance. Because a change in either can alter circuit operation, performance comparisons between MOSFETs of different
generations should address the effect of both these characteristics on design practices.
150
a-
that of the TMOS I chip. Note that the third generation onresistance is less than one third that of the first generation
devices.
A final comparison involving one of the TMOS III
devices and its bipolar namesake underscores the newly
found strength of the low voltage MOSFET. The very popular MJE3055T (a 10 A, 60 V, 100 x 100 mil 2 bipolar) and
the MTP3055A (a 12 A, 60 V, 96 x 96 mil 2 MOSFET) are
the representatives of their respective technologies. (The
MTP3055A is a one time deviation from Motorola's standard identification procedures. All other TMOS III units
follow the standard numbering system but include an "A"
suffix, e.g., MTP16N05A is a 16 A, 50 V device.) The first
difference, one that may be surprising to some, is the
lower on-voltage speCification of the MOSFET. At a load
current of 10 A, the MOSFET's maximum on-voltage rating is 1.5 V, and at a TJ of 125°C, the specification is
2.3 V. In comparison, the collector-emitter saturation voltage rating of the MJE3055T is 3 V, which is specified with
a base drive of 3.3 A.
The other advantages of the MOSFET are numerous
and familiar to most. They are greater speed, more extensive forward biased and switching safe operating
areas, simpler and much more efficient drive, higher
pulsed current rating, and greater ease of paralleling.
125
~
'g"
Sen
An added bonus; faster switching
.0;
"C
a:
75
0
50
25
0
25
50
75
100
125
FIGURE 9-12 - THIRD GENERATION MOSFETs ALSO HAVE
LOWER ON-RESISTANCE AT ELEVATED JUNCTION
TEMPERATURES
TABLE 1 -
ON-RESISTANCE COMPARISON OF FIRST, SECOND
AND THIRD GENERATION MOSFETs
TMOSI
MTP15N06
Die Area (kmil2)
TMOSII
MTP15N06
TMOSIII
MTP14N06A
22.5
12.5
9.2
Typical rDS(on)
@ 10 A, TJ = 25°C
135 M.!l
125 Mil
85 Mil
Case Temperature
During 10 A Test
74'C
71°C
eeoc
1.0
0.54
0.26
Normalized roS(on)
Die Area = 22.5 kmil2
The last row of Table 1 offers another means of comparing device technologies. Those entries show the onresistance of each device with all die sizes normalized to
Switching speeds, gate-charge reqUirements, and input
capacitance - all closely related parameters - are improving. Although the switching-speed comparison is not
quite as straightforward as the on-resistance comparison,
the end result is good news for those concerned about
switching losses and gate-drive efficiencies. For example,
the switching speed of the MTP14N05A, a TMOS III device, is about 35% faster than that of the TMOS I version
of the MTP15N05.
Changes in device design actually increase parasitic
capacitance per unit of silicon area - about 35% for the
same die size from TMOS I to TMOS III. However, because input capacitance (Ciss) is directly proportional to
die size, die-size reductions of as much as 75% more
than offset the effect of the greater parasitic capacitance
per unit of area. Clearly then, the capacitance, switching
speeds, and gate charge for a given current rating are
much improved. Of the three parameters, the gate-charge
requirements tend to be the spec that most clearly defines
the device's switching speed, for it is independent of gatedrive impedance.
It's difficult to predict switching speeds using values of
input capacitance (specified at a VOS of 25 V) or curves
that relate capacitance to VOS or VGO. The results could
also be wrong. The simplest and most accurate way to
compare potential switching speeds is to use gate-charge
waveforms. If the gate drive is a constant-current source,
you can use the expression
= It to relate charge to
switching time.
a
MOTOROLA TMOS POWER MOSFET OATA
1-9-10
Figure 9-13 shows the gate charge waveforms of the
MTP14N06A and the similarly rated TMOS I and II
MTP15N06. Properly interpreted, the curves contain
much information regarding potential switching speeds
and input capacitances. The curves can be divided into
three regions, each of which corresponds to a specific
interval of the turn-on transition. The first interval consists
of the initial ramp of the gate-to-source voltage. During
this period the input capacitance is charging, but there
are no significant changes in the drain current or drainto-source voltage. Since IG is constant in gate charge test
circuits, the slope of the curve is inversely proportional to
Ciss (i = C dv/dt). Note that the slope of the TMOS III
curve in this region is the steepest, indicating relative ease
of charging and lowest input capacitance.
VGS
2 V/div
4 ne/div
FIGURE 9-13 - GATE CHARGE REQUIREMENTS OF THE
TMOS III MTP14N06A (s) AND THE TMOS II MTP15N06 (b) ARE
MUCH IMPROVED OVER THAT OF THE TMOS I VERSION
OF THE MTP15N06 (e)
During the second interval, the one in which the rise of
the VGS waveform falters and is stalled at a plateau, the
drain voltage falls from the supply voltage to VDS(on).
Such a large change in VDS brings a large swing in VGD
and requires substantial charging of Crss (or Cgd, the
Miller capacitance). Therefore, the amount of time spent,
or the amount of charge required, when moving through
this region depends on the magnitudes of Crss and the
supply voltage. Here again, the TMOS III device delivers
the best performance, needing only about 7 nC of gate
charge compared to 8 and 11 nC for the TMOS II and I
units.
Although switching is completed in Region 2, Ciss continues charging until the gate-to-source voltage reaches
the desired VGS(on)' As in the first region, the slope of
the waveform in this third region indicates the size of the
input capacitance. Interestingly, all waveforms are now
rising more gradually than they did in the first region. The
magnitude of Ciss, which is a function of the gate-to-drain
voltage, is much higher now that the device is in the onstate, VDS is relatively low and VGD is positive.
Since the concept of required gate charge is based on
a constant current gate drive, it applies directly to only
those few gate drive topologies that can be modeled as
constant current sources. Nevertheless, gate charge information does allow easy prediction of relative switching
speeds, regardless of the type of gate drive.
As an example, consider driving a power MOSFET
directly from a standard CMOS logic gate. The CMOSMOSFET combination is especially important due to its
simplicity and reduced parts cost. Based on the gate
charge data in Figure 9-13, the drain voltage fall time
of the MTP14N06A should be about 60% of that of the
MTP15N06 - its TMOS I counterpart. That is indeed
the case as shown in the turn-on and turn-off waveforms
in Figures 9-14 a and b. The marked difference in transition times is directly attributable to the variation in gate
charge requirements. The fact that TMOS III devices
switch almost twice as fast as earlier units makes the
use of a standard CMOS gate as a MOSFET driver more
feasible.
This near doubling of switching speeds renews the possibility of using a standard CMOS gate as a MOSFET
driver. Of course, although direct drive approaches are
enticing, their associated switching losses limit operating
frequency. A couple of assumptions and some recommendations from CMOS applications engineers allow a
rough calculation of the operating frequency limits.
1 ",sldiv
FIGURE 9-14b -
FIGURE 9-14a - GATE VOLTAGE RISE AND DRAIN-TO-SOURCE
VOLTAGE FALL DURING TURN-oN.
GATE VOLTAGE FALL AND DRAIN CURRENT
FALL DURING TURN-OFF.
FIGURE 9-14 - IN A COMPARISON OF FIRST AND THIRD GENERATION MOSFETs OF SIMILAR CURRENT RATINGS, TMOS III
OUTCLASSES ITS PREDECESSOR BY SWITCHING NEARLY TWICE AS FAST WHEN DRIVEN BY A SINGLE CMOS GATE. IN THIS
CASE A 1.5 kG SERIES GATE RESISTOR HOLDS PEAK GATE CHARGING CURRENT TO LESS THAN 10 rnA.
MOTOROLA TMOS POWER MOSFET DATA
1-9-11
VDS
5V/
div
o
VGS
5 V/div
o
FIGURE 9-158 - GATE VOLTAGE RISE AND DRAIN-TO-SOURCE
VOLTAGE FALL DURING TURN-ON.
FIGURE 9-15b -
GATE VOLTAGE FALL AND DRAIN CURRENT
FALL DURING TURN-OFF.
FIGURE 9-15 - THE NEWEST MOSFETs. BECAUSE OF THEIR REDUCED GATE CHARGE REQUIREMENTS. CAN OPERATE AT
HIGHER FREQUENCIES WHEN GATE DRIVE CURRENT IS LIMITED. HERE THREE PARALLELED CMOS INVERTERS ARE DRIVING
THE MOSFET GATE THROUGH A SERIES RESISTANCE OF 100 O. EVEN AT FREQUENCIES APPROACHING 20 kHz. TOTAL
TMOS III SWITCHING TIME IS ONLY 1% OF THE ENTIRE PERIOD.
To a large extent. switching speeds are strongly dependent on how hard one is willing to push the capabilities
of the CMOS gate. The recommended maximum continuous output current is 10 mA per pin. Since these devices
are not designed to drive highly capacitive loads such as
a MOSFET gate. their pulsed current ratings are not
specified.
Rigid adherence to the continuous specification results
in the switching speeds shown in Figure 9-14. In this case,
the TMOS I and TMOS III devices are driven from a single
inverter of an MC14572. a hex gate IC. A 1.5 k series
resistance between the output of the IC and the gate of
the MOSFET limits peak charging and discharging to less
than the 10 mA specification. Since the RMS value of the
TMOS III gate current at 20 kHz is less than one milliampere. decreasing the magnitude of the series gate
resistance is tempting.
Either paralleling CMOS gates, which must be from the
same chip to guarantee good current sharing. or decreasing the value of the series gate resistance improves
switching times. Figures 9-15 a and b illustrate the effect
of both of these adjustments. With three inverters in parallel and a 100 n. series reSistance, transition times fall
well below the 1 JLS. Peak gate current rises to 40 mA, or
about 13 mA per gate. This brief excursion beyond the
10 mA specification is harmless because of its short duration «300 ns).
Translating these current and voltage fall times and the
associated switching losses into an upper limit of operating frequency is a subjective exercise. Many factors,
including available heatsinking, current and voltage magnitudes. on-state losses and duty cycle, dictate the
amount of acceptable switching losses.
One rule of thumb is to limit the sum of the turn-on and
turn-off transition times to less than 1% of the period.
Using this criterion. the TMOS I device driven from a single
CMOS inverter is limited to 1.3 kHz and the TMOS III
equivalent is bounded by 2.4 kHz. With the three gates
in parallel, 9 and 17 kHz are the upper limits.
Although faster switching and lower gate charge are
normally desirable traits. they can be a mixed blessing.
Since switching speeds may be almost twice as fast, the
possibility of excessive voltage transients must be reconsidered. The design of all power MOSFET circuits should
include rigorous monitoring of the drain-to-source voltage
to preclude the possibility of excessive voltage transients
during the turn-off transition. With the faster TMOS III
devices this concern becomes more critical. Speeding the
response time of the overvoltage protection circuitry may
be needed if the device is switched more rapidly. When
greater speeds are unnecessary, a higher gate drive
impedance in the form of a resistance in series with the
gate slows the switching transitions and simplifies the design of overvoltage protection circuitry.
~tJ1
loon
I
U-10--15 V
FIGURE 9-15c - THREE STANDARD CMOS INVERTERS OF AN
MC14572 DRIVING A MOSFET GATE WITHOUT THE AID OF A
BUFFER STAGE.
MOTOROLA TMOS POWER MOSFET DATA
'-9-12
Let IRMS
Thermal considerations are important
It's also important that you understand the thermal implications of the smaller die sizes of third-generation MOSFETs. A lower rOS(on), value per unit area increases the
power-handling capability of a given die size, but the ability
to dissipate power is still tied to the thermal resistance of
the device. The newer, smaller devices - sometimes less
than a third the size of their predecessors - have less
area in contact with their cases, which increases their
thermal resistance and decreases the power they can
dissipate. It's therefore not a good idea to select replacements for first-generation MOSFETs solely on the basis
'of ,on-resistance and drain-to-source breakdown voltage.
Because junction temperatures directly affect long-term
reliability, the TJ value is an important indicator of a transistor's exposure to stress. Where junction temperature
is such a major concern, the junction-to-case thermal
impedance also becomes critical. In fact, when it comes
to minimizing junction temperature, the magnitude of the
thermal impedance is almost as important as the value
of on-resistance. The following example shows why.
Assume that Device A is a first generation MOSFET
that is being replaced with Device B, a third generation
unit. With the RMS value of the drain current held constant
in each instance, a requirement of Device B is that its
operating junction temperature must be less than or equal
to that of Device A.
IITJl = TJ2
then POl (ROJCl + ROCA) = P02(RIJJC2 + ROCA)
or IRMs2rOS(on)1 (RIJJCl + ROCA) =
IRMs2rOS(on)2(RIJJC2 + ROCA)
II, for a moment, ROCA is assumed to be zero, the
equation simplifies to:
(rOS(on) x ROJC)l = (rOS(on) x ROJC)2
This equation states that if the case temperatures are
held constant, which is assured when ROCA = 0 (infinite
heat sink); then equating the product of the thermal resistance and the on-resistance guarantees that the junction temperatures will be the same. Therefore, this product, referred to as the "resistance product," is a useful
tool for comparing devices from different technologies or
manufacturers.
The best way to elaborate on the concept of the resistance product is with a numerical example. Table 2 contains the ratings of Motorola's IRF531 and the
MTP14N06A. On the basis of their similar resistance products, they might be considered to be direct replacements.
TABLE 2 -
CHARACTERISTICS OF DEVICES WITH SIMILAR
RESISTANCE PRODUCT RATINGS
Device A
Oevice Type
Device B
IRF531
MTP14N06A
Technology
TMOSI
rOS(on)
0.18 fi
TMOS "'
0.10 fi
RWC
1.67°CfW
3.12°CfW
PO(max)
75W
40W
Resistance Product
0.30°C/A2
0.31°C/A2
Then POl
=
=
=
10 A
and ROCA
(100A2 x O.18!l)
18W
= 3°CIW
P02
=
=
(100A2 x o.l0n)
lOW
dTJCl = POl ROJCl
dTJC2 = P02RIIJC2
= 18 W x 1.67°CIW
= 10 W x 3.12°CIW
= 30°C
= 31°C
As expected, the junction to case temperature rise in
each instance is nearly the same because the resistance
products are so closely matched. But here the similarity
ends due to the greater efficiency of the smaller chip.
Depending on the magnitude of the case to ambient thermal resistance, the case to ambient temperature differential, TCA, might vary considerably. When ROCA
3.0°CIW, then
dTCAl = 3.0°CIW x 18 Wand dTCA2 = 3.0°CI W x 10 W
= 54°C
= 30°C
For
TA
=
25°C,
TJl = dTJCl +dTCAl + TA and TJ2 = dTJC2+ dTCA2+ TA
= 30+54+25°C
= 31 +30+25°C
= 109°C
= 86°C
As the numbers illustrate, a constant resistance product
does not always guarantee identical junction temperatures - it only forces the same ~TJC. In fact, if the case
to ambient thermal resistance is high, junction temperatures may be quite different. However, the product can
still be used as a comfort factor when designing in the
newer power MOSFET generations. II the resistance
product is held constant, the on-resistance of the more
efficient device must be lower even though its junction to
case thermal impedance is higher. Therefore, the newer
device will dissipate less power for a given load current
by virtue of its lower on-resistance. The lower power dissipation then results in a smaller case to ambient temperature differential and a lower junction temperature.
The preceding analysis ignores how TJ affects onreSistance, a very important consideration. The interdependence of the magnitude of rOS(on), TJ and power
dissipation makes the resistance product an inexact tool.
Also, the concept of the resistance product is based on
the steady state thermal resistance and is, therefore, not
appropriate for transient analysis. In spite of these inadequacies, the concept is useful for first order approximations, and it does illuminate some of the considerations
that must be thought through to safely utilize the advantages of the new technology. For a more detailed thermal
analysis, Motorola's AN569, "Transient Thermal Resistance - General Data and Its Use" is an excelle(lt guide.
Fortunately for the designer, die size, steady state and
transient thermal impedance, on-resistance, maximum allowable junction temperature and package limitations are
all factored in when a device's maximum pulsed and continuous current ratings are assigned. Consequently, the
MTP16N05A (which is a 16 A, 50 V device of the TMOS
III vintage) is almost always a drop in replacement for any
other 16 A, 50 V power MOSFET. The lower maximum
on-resistance specification compensates for the smaller
die and increased junction-to-case thermal impedance.
Linear applications are an exception to this rule since the
main concern in those circuits is power dissipation capability. Die area and thermal impedance must remain
unchanged in those cases since improvements in onresistance oiten do not reduce power dissipation.
MOTOROLA TMOS POWER MOSFET DATA
1-9-13
Expanding Range of Applications
Already the expansion of the MOSFET into the power
transistor market is outpacing the predictions of many. But
the steady expansion is likely to turn into an explosion
when the potential of the latest MOSFETs are fully appreciated. The new efficiency and economy of the low
voltage MOSFETs foreshadows their dominance of that
section of the power transistor market.
The automotive industry is among those likely to welcome a means of cost effectively controlling large continuous and pulsed currents. Specific applications involve
the control of the many small motors found under the dash
and hood and in the doors, the replacement of mechanical
relays, and the switching of many lamps and solenoids.
Interestingly, auto makers often have little use for the
MOSFET's most proclaimed attribute, its tremendous
switching speed. Instead, they are impressed by its low
on-VOltages, extensive SOA, and modest gate drive
requirements.
The use of MOSFETs for synchronous rectification is
an example of an application that deserves reconsideration. Previously, MOSFETs had trouble competing with
Schottky diodes, for example, because the MOSFET required much more silicon area to deliver the same performance. With the precipitous drop in per unit area onresistance, the MOSFET is now much more competitive
(Figure 9-16).
Several other applications come to mind, for example,
solid state relays, hammer drivers for printers, telecommunications equipment, and output stages for programmable controllers. But the application primed for the introduction of such a switch is the brush less DC motor
controller. As the cost of the semiconductor control circuitry continues to fall, the benefits of the electronically
com mutated motor - high efficiencies, linear speed/
torque characteristics, long service life, the potential for
speed control, etc. - will become more affordable.
Figure 9-17 illustrates one such control circuit. The design is tailored for a blower motor, so it is limited to single
speed, unidirectional operation. After processing the signals from the three Hall effect sensors, the MC14028B (a
binary to decimal decoder) and the six OR gates provide
the proper logic sequence to control the output tranllistors.
The relatively low commutation frequency is strictly a function of the motor speed, because the Hall effect sensors
ultimately determine the firing sequence.
For simplicity, a P-channel MOSFET, an MTP5P20, was
used as the power switch in the upper legs of the bridge.
With a few drive circuit modifications, a PNP bipolar or
even an NPN Darlington could also fill that socket. The
most qualified candidate to serve as the low side switch
is one of the third generation MOSFETs, again a 96 x 96
mil2 chip. This device has a drain-to-source voltage rating
of 200 V and a typical rOS(on) of only 0.3 n. A continuous
motor load current of about 2 A causes negligible power
dissipation in this device.
In the open loop system shown in Figure 9-17, motor
speed is unregulated and is a function of the motor characteristics, the type of load and the magnitude of the DC
supply voltage. Changing the supply voltage or using
pulse width modulation allows regulation of motor speed.
In this case, the best place for a speed control network
is between the OR gates and the hex buffer.
There are three ways to control the effective motor voltage with pulse width modulation. The designer may PWM
only the bottom three transistors, or only the top devices.
The third option, pulse width modulation of both the upper
and lower devices, also controls motor speed. The simplest approach is to pulse width modulate MOSFETs in
the lower legs of the bridge. In that position, the MOSFET
shows off several of its most advantageous attributes. It
is fast, cost effective, efficient and very easy to drive.
D
Vo
--
ID
FIGURE 9-16 - USING POWER MOSFETs AS "SYNCHRONOUS RECTIFIERS" IN THE
OUTPUT STAGE OF A SMPS CAN REDUCE RECTIFICATION LOSSES. WHEREAS MOSFETs
ONCE REQUIRED TOO MUCH SILICON TO RIVAL THE SCHOTTKY DIODE NORMALLY USED,
THE NEWEST MOSFETs ARE MUCH MORE COMPETITIVE.
MOTOROLA TMOS POWER MOSFET DATA
1-9-14
MCI471B(2)
VCC
VCC
1C2A
Switch
CKTI
r------------- -,
I
I
I
I
I
6
SI
15
1C4
S2
14
Hall-Effect
Sensor
Outputs
-=
2
-=
I
I
---:
2
3
5 ID 4
7 5l 6
9 ~ 10
11 ~ 12
14
15
7
S3
MPSA42
I
I
L
MTP5P20
:
I
=
L________
I
I
_-1
c
A
Switch
CKT4
r---------- --,
8
I
I
I
200 V
TMOSIII
I
I
I
I
10 k
I
I
IL _____________
_ ..lI
1k
B
10 k
NOTE:
Switch circuits 2 and 3 are the same as switch circuit 1.
Switch circuits 5 and 6 are the same as switch cIrcuit 4.
Timing Waveforms
of Logic Circuitry
SI
I
S2
--.J
S3
'1-__
----1
02 - - - - -.....
03
04 _ _ _---'
05
06
FIGURE 9-17 -
TO SIMPLIFY THE DESIGN OF THIS BLOWER-MOTOR CONTROL CIRCUIT, THE UPPER LEGS OF THE BRIDGE
EMPLOY A P-CHANNEL MOSFET FOR THE POWER SWITCH
Pulse width modulation of only the lower devices also
circumvents one other potential problem. Even in these
third generation devices, the MOSFET's diode is still sensitive to high dv/dt's (in the range of 1 volt per nanosecond)
during its reverse recovery time. Use of a bipolar, in parallel with a discrete diode, is a tidy solution. The discrete
diode doesn't mind the commutation stresses imposed by
the fast switching MOSFETs. Also, rapid turn-on of the
bipolars is unnecessary because their switching frequency, which is tied to the motor speed, is much lower.
Therefore, the MOSFET's intrinsic diode need not endure
the rigors of very high dv/dt.
MOTOROLA TMOS POWER MOSFET DATA
1-9-15
Even Greater ExPectations
Although recent performance improvements have been
startling, they are only one point on a continuum of
advances. Soon TMOS III w.ill be superseded by an even
more efficient version of the third generation product. The
logical extension of certain changes in design philosophy
from TMOS I to III suggest that even lower on-resistances
are within reach. Photolithographic tools and techniques
w.ill also continue to improve, allowing yet finer cell geometries and even greater packing densities.
Another forthcoming change is the introduction of new
packaging to compliment the greater current handling capability of the newest devices. Even now, moderately
sized 50 and 60 V chips can cause excessive 12R losses
and high temperatures in the leads of the popular TO220, TO-3 and TO-218 packages. Since the problems with
the present packaging are associated with undesirable
lead resistance and not insufficient power dissipation ratings, the solution entails enlarging the leads of the popular
package types.
At the other end of the spectrum, smaller packaging w.ill
become more important. The trend toward surface mount
technology and the development of small MOSFET die
with low on-resistance meld together quite conveniently.
The new chips are so efficient that packages such as the
D-pack w.ill have unconventionally high current capabilities for surface mount devices. In the surfaCe mountable
D-pack the 96 x 96 mil 2 TMOS III die can easily conduct
2.5 A of continuous drain current with less than one watt
of power diSSipation. Drain currents can reach at least
10 A under pulsed conditions.
The GEMFET - A New Option
for Power Control
•
The world of power switching is constantly searching
for the ideal switch. Such a switch would have infinite
resistance in the off-state, zero resistance in the on-state,
instantaneous switching times, and require zero input
power to operate. In a real switching application, one must
choose the device that most closely approximates the
ideal switch for that particular application. The choice involves considerations such as voltage, current, switching
frequency, drive circuitry, inductive loads, temperature effects, etc. Every switching device has its strong pOints
and weak points and the designer is always forced to
make trade-offs to find the best switch for a given situation.
For ~ solid state switch, the three characteristics that
are most desirable are fast switching speeds, simple drive
reqUirements and low on-state losses. In low voltage applications, the new generations of power MOSFETs have
very low on-resistance and closely model the ideal switch.
But in high voltage devices, comparatively high onresistance st.ill limits the MOSFETs efficiency. Furthermore, future advances in decreasing rDS(on) will become
more difficult as on-resistances fall closer to the theoretical minimum, which is determined by the optimum cell
geometry and the resistivity of the N-epi layer. Therefore,
subsequent large reductions in rDS(on) of high voltage
MOSFETs will require new technologies.
The GEMFET (gain J;nhanced MOSFED, also called
an insulated gate bipolar transistor (IGBT), is the result
of one such technological advance. It is a relatively new
high voltage power semiconductor device with a combination of characteristics previously unavailable to the
designer of power circuitry. Closely related to the power
MOSFET in structure, this new device has forward voltage
drop comparable to bipolars while maintaining the high
input impedance and fast turn-on associated with the isola:ted gate of the MOSFET. Although turn-on speeds are
very fast, current fall times of approximately 4.0 ILs are
quite slow, and may restrict the use of at least the first
generation of these devices to lower frequency
applications.
At switching frequencies below about 10kHz, however,
the GEMFET is an attractive alternative to the more tra-
ditional bipolars, power MOSFETs and thyristors. Compared to a standard thyristor, the GEMFET is faster and
has a higher input impedance, better dv/dt immunity and,
above all, gate turn-off capability. While some thyristors,
e.g. GTOs, can be turned off at the gate, this requires
substantial reverse gate-drive current, whereas, turning
off the GEMFET requires only that the gate capacitance
be discharged. On the other hand, thyristors generally
have a slightly lower forward drop and a higher surge
current rating than a comparable GEMFET.
In a comparison of drive requirements, the GEMFET
clearly outperforms bipolar transistors. In a lOA application, for instance, the bipolar requires 2.0 A of base
drive (assuming a beta of 5.0) while the GEMFET requires
only nanoamperes of gate current to remain in the "on"
state. Without the large base-drive current required by the
bipolar, the GEMFET gate-drive circuit can be much simpler and more efficient. Darlingtons also simplify drive
requi~ents, but on-VOltage is compromised in doing so.
Sometimes MOSFETs are used in low frequency applications because of their simple gate-drive requirements. In many low frequency, high voltage circuits, replacement of the MOSFET with a GEMFET improves
efficiency or reduces the cost of the switch. Because their
structures and gate-drive considerations are so similar,
the change usually entails no significant circuit modifications. Substitution of a GEMFET with approximately the
same die area dramatically improves on-state efficiency
and current ratings.
If cost is a major concern, another option is to replace
the power MOSFET with a GEMFET that has a smaller
die area. The result can be a device with a similar current
rating and comparable on-state losses. Except at higher
frequencies, the cosVperformance tradeoffs are substantially in favor of the GEMFET.
The GEMFET is suitable for high current, high voltage,
low frequency applications because of its low forward drop
and relatively long turn-off time. Appropriate applications
for the GEMFET include motor drive circuits, automotive
switches, programmable controllers, robotics, home appliances, machine tools, etc.
MOTOROLA TMOS POWER MOSFET DATA
1-9-16
Emitter Metalization
Device Structure
The GEMFET is very similar to the double-diffused
power MOSFET. Simply by varying starting materials and
by altering certain process steps, a GEMFET may be
produced from a power MOSFET mask set. Figure 9-18
illustrates that the two structures are identical except for
the P + layer adjacent to the drain metalization. Additional
current carriers in the form of holes are injected from the
P + substrate into the normally high resistivity N-epi layer
and markedly reduce the on-voltage. The resulting four
layer structure (P-N-P-N) allows current densities much
greater than those attainable in power MOSFETs and
comparable to those of bipolars.
Like the power MOSFET, the gate of the GEMFET is
electrically isolated from the rest of the chip by a thin layer
of Si02. Accordingly, the GEMFET is also a high input
impedance device and exhibits the associated advantages of modest gate-drive requirements and excellent
gate-drive efficiencies. The uniqueness of the GEMFET
is that low on-voltages as well as high input impedances
are now available in high voltage power semiconductors.
The symbols and equivalent circuits of the GEMFET
and MOSFET are shown in Figure 9-19. Because of its
four layer structure, the GEMFET lacks the parasitic drainsource diode common to nearly all power MOSFETs.
Device Characteristics
Output Characteristics
In the forward conduction mode, the GEMFET closely
resembles a power MOSFET. The equivalent circuit is
best modeled as shown in Figure 9-19 in which a low
voltage, low rOS(on)' N-Channel MOSFET is driving a
PNP transistor in a compound configuration. The PNP
device not only helps lower the effective rOS(on), but also
enhances the device gain (transconductance) at high
drain currents. Except at excessive drain currents or junction temperatures, the NPN device is considered to be a
parasitic and does not influence circuit operation.
The output characteristics of a popular power MOSFET
(MTP4N50) and a GEMFET (MGP20N50) of identical die
dimensions and similar breakdown voltages are shown in
Figures 9-20a and 9-20b. The two major differences between the curves are:
Gate Oxide
Polysilicon Gate
Collector
FIGURE 9-18b -
-
CROSS SECTION OF GEMFET CELL
The GEMFET has a much lower on-resistance at
currents greater than 2.0 A.
2 -
Before the GEMFET can conduct current, the P-N
junction formed by the P + substrate and the
N-epi layer must be forward biased. Consequently, the GEMFET curves are offset from the
origin by a diode drop, similar to SCRs or
Oarlingtons.
Figure 9-2~ indicates that at 25°C the 20 A, 500 V
MGP20N50 gives no hint of a propensity to latch at currents up to 62 A, which is much larger than the pulsed
current rating of the MOSFET.
Source
MOSFET Symbol
Source
MOSFET
C
~
G~~ od
Source Metalization
Gate Oxide
Polysilicon Gate
E
IGBTSymbol
Emitter
IGBT
Equivalent Circuit
FIGURE 9-19 - MOSFET AND GEMFET
SYMBOLS AND EQUIVALENT CIRCUITS
N + Substrate
Switching Speeds
Drain
FIGURE 9-188 -
CROSS SECtiON OF TMOS CELL
Presently, the feature that limits the GEMFET from serving a very wide range of applications is its relatively slow
turn-off speed. While turn-on is fairly rapid, current fall
times at turn-off can exceed 4.0 JLs.
MOTOROLA TMOS POWER MOSFET OATA
1-9-17
i
!z
~
::>
8.0
7.0
6.0
5.0
z
~ 4.0
u.
.9 3,0
2.0
1.0
2.0
4.0
6.0
8.0
10
12
14
16
18
20
Vos, ORAIN·TO-SOURCE VOLTAGE (VOLTS)
As the electron concentration in the N-region decreases, the electron injection decreases, leaving the rest
of the holes and electrons to recombine. The turn-off of
the GEMFET should then have two phases: the injection
phase where the drain current falls very quickly; and a
recombination phase where the drain current decreases
more slowly. Figure 9-22 shows the clamped inductive
turn-off waveforms of the MGP20N50 .
Although turn-off speeds are not impressive, this is the
first generation of these devices and improvements in
switching speeds can be expected. For GEMFETs, there
is an rCE(on) - switching speed trade-off. Theoretically,
turn-off times can be decreased without large increases
in rDS(on) by contrOlling carrier lifetimes or by other proprietary methods.
FIGURE 9-208 - OUTPUT CHARACTERISTICS
OF POWER MOSFET (MTP4N50)
Ic
1.0 AlDIV
VCE
50 V/OIV
0.5 !'8iDIV
FIGURE 9-22 -
U
U
M M W U
M g
g
CLAMPED INDUCTIVE TURN-OFF
OFGEMFET
Even though MOSFETs are championed for their simple
gate-drive requirements, at high operating frequencies
sizable peak gate currents must be supplied to ensure
rapid switching_ Since this first generation GEMFET is, by
comparison, much slower, the gate drive-impedance can
be fairly high without affecting turn-off speeds_ In the circuit shown in Figure 9-23, RG was varied from 0 to 1.0 kO,
but the current fall time essentially remained constant at
3.75 p,s (Table 3).
ro
VCE, COLLECTOR-TO-EMlmRVOLTAGE (VOLTS)
FIGURE 9-20b - OUTPUT CHARACTERISTICS
OF GEMFET (MGP20NSO)
I
"-
olL
2.0
4.0
6.0
8.0
10
12
14
16
RG
~
. =
FIGURE 9-23 - CIRCUIT TO TEST
VARIATIONS IN CURRENT FALL TIMES WITH
CHANGES IN GATE DRIVE IMPEDANCE
18
VCE, COLLECTOR-TO-EMlmR VOLTAGE (VOLTS)
TABLE 3 - Effect of Series Gate
Resistance on Turn-off Speeds
FIGURE 9-21 - OUTPUT CHARACTERISTICS
OF GEMFET AT HIGH DRAIN CURRENTS
Series Gate
Resistance
The turn-off of the GEMFET is rather slow because
many minority carriers are stored in the N-epi region.
When the gate is initially brought below threshold, the
N-epi contains a very large concentration of electrons,
consequently, there will be significant electron injection
into the P + substrate and a corresponding hole current
into N-epi.
00
1000 2000 SOOO 10000
140 ns 140 ns 150 ns 180 ns 350 ns 810 ns
Collector
Current Fall
Time
3.75p.s 3.75p.s 3.75p.s 3.75p.s 3.75p.s 3.75p.s
MOTOROLA TMOS POWER MOSFET DATA
1-9-18
500
Collector
Voltage Rise
Time
Comparison of On-State Losses
The most pronounced advantage of the GEMFET over
the power MOSFET is its lower on-resistance. The
VDS(on) of a high voltage MOSFET is fairly large and
rises with increasing junction temperature and drain current. Conversely, the VCE(on) of a GEMFET decreases
with increasing TJ and is not greatly affected by IC. Figure
9-24 compares the on-voltages of the two technologies
at various drain currents and at aTJ of 25°C and 100°C.
Since the MOSFET does not have the GEMFET's offset
voltage in its output characteristics, at low currents the
MOSFET on-voltage is slightly lower. However, as the
illustration suggests, at high currents and temperatures
the difference is dramatic. For comparison, a bipolar transistor was also included in Figure 9-24. Its on-voltage is
14
3
2f-11--
ft
POWER
MOSFET
TJ= :OO°C
v;
9.0
~
8. 0
':;
f--
~
0;~
5. 0
4.0
3. 0
2. o
1.
1/
r-;
TJ 1=
J5"C
1/
1
~ 7. 0
6. 0
L
11
0
a function of the transistor's high current beta and the
magnitude of the base current.
On-state efficiencies are not solely determined by onvoltages. Gate or base-drive currents are also contributing
factors. Its high input impedance allows the GEMFET to
rival the on-state efficiency of the bipolar transistor, even
though its on-voltages are comparable to those of SCRs
(one diode drop in addition to a bipolar saturation voltage).
The bipolar device chosen for this comparison had a
forced beta so low (about 5) at the desired collector current
that the base current losses were important.
To illustrate the variation in the on-state efficiencies of
each technology, a bipolar transistor, MOSFET and
GEMFET were used as the switching element in an open
loop PWM dc motor control circuit. The bipolar
(MJE13007) was a 156 x 156 mil chip rated at 8.0 A, 400
volts. The 20 A, 500 volt GEMFET (MGM20N50) and the
4.0 A, 500 volt MOSFET (MTP4N50) had areas equivalent
to a die size of 150 x 150 mil. To keep switching losses
to a minimum, the frequency was held constant at about
90 Hz as the duty cycle was varied from 9% to 71 %. Since
/
II
so
-'-
~
I
\
MJE13007
BIPOLAR
IC/IB = 5.0
TJ = 25°C
I
GEMFET
Ll
O~~TJ=I~_
BIPOLAR
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
'0. DRAIN CURRENT OR IC, COLLECTOR CURRENT IAMPSI
30
FIGURE 9-24 - ON-VOLTAGE versus DRAIN OR COLLECTOR
CURRENT FOR A GEMFET, MOSFET AND BIPOLAR OF
EQUIVALENT DIE SIZE
V
Outy
Cycle
%
8.0
6.0
4.0
2.0
1.0
71
11.2 ms
20
GE~FET
40
60
DUTY CYCLE 1%1
80
100
FIGURE 9-25 - ON-STATE EFFICIENCY COMPARISON PULSE WIDTH MODULATION OF DC MOTOR
IC(max)
or
IO(max)
(A)
Case
Temp
Relative
Power
Out
(Speed)
Relative
Power
In
(OC)
Power
Oissipation
(W)
On
Voltage
(Volts)
VOSor
VCE(pk)
(Volts)
36
18
9.0
0.75
1.0
1.6
2.75
4.50
37.2
37.4
38.5
39
40.9
0.69
0.70
0.75
0.79
0.86
1.0
1.1
1.1
1.5
2.0
1.75
2.0
2.5
4.0
6.5
49
2.0
2.0
2.0
2.0
2.0
8.0
6.0
4.0
2.0
1.0
71
54
36
18
9.0
0.75
0.80
1.25
. 2.25
3.50
38.6
42.1
49.4
62
77.4
0.76
0.91
1.22
1.77
2.44
1.0
1.3
2.0
4.5
7.5
1.75
2.25
3.25
6.50
11.00
78
77
70
48
18
2.0
2.0
2.0
2.0
2.0
8.0
6.0
4.0
2.0
1.0
71
54
36
18
9.0
0.80
49.7
45.7
40.7
34.8
32.6
1.24
1.06
0.85
0.59
0.50
0.1
0.2
0.2
0.3
0.5
0.8
1.0
1.5
3.0
5.0
82
81
78
70
59
140
104
72
36
20
I
~
I
BIPOLAR
(MJE13007)
=
o
V
On-State Efficiency Testing: Pulse Width Modulation of OC Motor
Pulse
Width
(ms)
TMOS
(MTP4N50)
T
"' .,,--t---..-r
..........
.,J. i=='
!-- f'
o
GEMFET
(MTM20N50)
\
I\.
0
TABLE 4 -
MOSFET
TA = 21.2°C
54
f=90Hz
1.1
1.5
2.75
4.5
Voo = 14V
ROHS
= 23°CIW
MOTOROLA TMOS POWER MOSFET DATA
1-9-19
78
77
73
64
a motor is a nonlinear load and conditions such as motor
speed and back EMF change with pulse width, the results
of the comparison (Table 4 and Figure 9-25) should be
carefully interpreted.
The "relative power out" referred to in Table 4 is simply.
a measurement proportional to the motor speed and is
inversely related to the saturation voltage. If the onvoltage is high, the potential across the motor is diminished and the speed is decreased. The "relative power
in," a measure of forward base (or gate) current, is useful
for comparing the required base or gate power necessary
to control a five ampere load.
The following generalizations can be drawn from Table
4 and Figure 9-25:
1. Even though its on-voltage is very low, the bipolar
is not the most efficient device at high duty cycles.
The power consumed by the device due to its large
base current is great enough to be reflected in an
increase in case temperature. Because of the bipolar's low beta, the case temperature and power
dissipation closely track the relative power in.
polar, its input power is very small and does not
significantly affect the power dissipation at high duty
cycles. At lower duty cycles and higher currents, the
GEMFET on-voltage is much lower than the
MOSFET's. Again, the result is cooler case
temperatures.
While the GEMFET looks quite respectable in this comparison, the peak current chosen influences the relative
efficiencies. If the motor supply voltage had been increased to obtain larger peak currents, the comparison
would have been even more in favor of the GEMFET. The
MOSFET would have performed more poorly due to its
ID-rDS(on) relationship, and the bipolar's base drive
losses, due to forced betas' less than 5.0, would further
reduce its efficiencies at large pulse widths.
Switching Losses
The present maximum operating frequency of the
GEMFET is limited by its turn-off speed. Defining a specific upper limit could be misleading because the frequency limitation depends on heat sinking, drain current,
drain supply voltage, gate-drive impedance, and drainsource flyback voltage. To set a benchmark for a specific
set of conditions, the following test circuit and procedure
was developed to compare the switching efficiencies of a
GEMFET (MGP20N50), MOSFET (MTP4N50), and bipolar (MJE13007).
2. The bipolar invariably results in the highest motor
speed for a given pulse width because its saturation
voltage is always lowest.
3. For the MOSFET, high on-resistance, especially at
higher currents and temperatures, influences the
performance. As the duty cycle decreases, the motor
speed and back EMF also decline. With the lower
back EMF, the effective motor voltage is higher, allowing higher currents. The increasing current and
on-resistance combine to elevate the case temperature at low duty cycles.
4. The case temperature of the GEMFET remains almost unchanged as conditions vary. Unlike the bi-
In the test procedure, the independent variable was
switching frequency, which was varied by changing the
timing capacitor C1 in the test circuit shown in Figure 9-26.
By adjusting potentiometer R1 and by properly sizing the
inductive load, the load current waveform was fixed to a
25% duty cycle and a peak of 5.0 A.
v+
•
v+ =
12 V
17.5 V FOR BIPOLAR)
':"
100 k
47
V2W
10
2.2 k
1.0 k
O.Ol,...f
lN914
':"
1.5 k
-5.0V
FIGURE 9-26 - CIRCUIT TO COMPARE SWITCHING EFFICIENCIES
OF GEMFET, MOSFET AND BIPOLAR
MOTOROLA TMOS POWER MOSFET DATA
1-9-20
VCE
100 V/OIV
VOS
l00V/OIV
Ie
2.0 AlOrY
10
2.0 AlOIV
20 p.S/OIV
20p.S/01V
FIGURE 9-278 - CLAMPED INDUCTIVE
SWITCHING WAVEFORMS AT 7.0 kHz - GEMFET
FIGURE 9-27b - CLAMPED INDUCTIVE SWITCHING
WAVEFORMS AT 7.0 kHz - MOSFET
200
180
E
VeE
100 VIOIV
~
::>
~
120 >- HEAT SINK
~
2
100
~
60
I:!!
IC
2.0 AlDIV
20 p.S/OIV
GEMFET
j;J..<
V
MTP4N50
MOSFET
V
~
40
trrJE13007
20
jlPOIj
o
1.0
0.1
FIGURE 9-27c - CLAMPED INDUCTIVE SWITCHING
WAVEFORMS AT 7.0 kHz - BIPOLAR
r',;;GM~~50
= 4' x 4" x ~' COPPER PLATE
80
~
III
111111
180 >-IOM = icM = 5.0 A
OUTY CYCLE = 25%
140 ~TA = 25'C
10.0
100
SWITCHING FREQUENCY IkHzl
FIGURE 9-28 - COMPARISON OF CASE TEMPERATURE
versus FREQUENCY FOR A GEMFET, MOSFET AND BIPOLAR
For the MJE13007, the forced beta of S.O required a
base current of 1.0 A. Turn-off of all three types of devices
was initiated by clamping the base (or gate) to - S.O volts.
The oscillograms in Figure 9-27 show the drain (or collector) current and drain-source (or collector-emitter) voltage of each device at 7.0 kHz.
Again, the test results were quite predictable, and the
case temperature versus frequency for this specific case
is plotted in Figure 9-28. The efficiency of the heat sink,
in this instance a 4W' x 4W' x Va" copper plate (ROCA =
SOCfW), markedly influences the temperature rise results.
A larger or smaller heat sink would have decreased or
increased, the noted temperature differences. The tesiing
was restricted to lower frequencies because above 40 kHz
secondary effects began to influence and distort the
comparison.
The GEMFET switching losses rose rapidly with frequency, illustrating its high-frequency limitations. By comparison, the bipolar's case temperature increased only
slightly while the MOSFET proved its high frequency capability with virtually no case temperature rise.
All previous thermal resistance testing of the TMOS
power MOSFET was based on the temperature dependence of the on-voltage of its drain-source diode. For the
MTP4NSO, the results were typically about 0.79°CfW.
Because the GEMFET has no parasitic diode, this method
was inappropriate for the MGP20NSO. Instead, Rruc of
the GEMFET was determined by using a second circuit
that detects variations in the gate-source threshold voltage due to changes in TJ. Before testing the GEMFET,
correlation between the two test methods was obtained
by comparing the results of testing the MOSFET in each
circuit. By testing for variations in threshold voltage, the
RruC of thw MTP4NSO and the MGP20NSO were both
typically 0.67°CfW. This suggests that the two methods
are in fairly close agreement and that the thermal resistances of a MOSFET and GEMFET of equal die area are
essentially the same.
Safe Operating Areas
Important ratings of any solid state switching element
are its Safe Operating Areas. For the GEMFET, these
include its Forward Biased SOA, or FBSOA, and Reverse
Biased SOA, or RBSOA. Since non-destructive fixtures
"';ere used to determine both of these SOA limitations, an
entire curve could be drawn with each device tested. With
this capability, device trends readily became apparent.
Figure 9-29 shows the dc FBSOA limits of an MTPSN40
and an MGP20NSO. Even though the curves are quite
similar, at either end there are significant differences. At
Thermal Resistance, R9JC
As expected, GEMFETs and power MOSFETs produced from the same mask set have very similar junctionto-case thermal resistances. R8JC of a power MOSFET
can be determined by testing for variations in one of the
following temperature sensitive parameters, or TSPs:
1. Drain-source diode on-voltage
2. Gate-source threshold voltage
3. Drain-source on-resistance
MOTORGLA TMOS POWER MOSFET DATA
1-9-21
100
GEMFET
VCElon)
h UMIT
I.....
1/
~
MAXIMUM PULSED CURRENT
RATING OF GEMFET
10.-
fflm
MAXIMUM PULSED CURRENT
RATING OF MOSFET
I
l'.
"FAIL" POINTS GENERATED BY
NON-DESTRUCT FBSOA TESTER
400 V POWER MOSFET
o - 550 V GEMFET
-- - PROJECTED DATA ,
~TMOS"'"
~ 'DSlon)
~,X 0.1
1.0
Il\)"
10
100
1000
VCE. COLLECTOR-EMITTER OR VDS. DRAIN-SOURCE VOLTAGE IVOLTS)
FIGURE 9-29 - COMPARISON OF FBSOA CURVES OF A
400 V MOSFET AND 550 V GEMFET OF EQUAL DIE AREA
high voltages and low current\!, the GEMFET's curve begins to roll off somewhat like the curve of a bipolar that
is approaching a second breakdown limitation. This is not
surprising since the parasitic PNP bipolar is instrumental
in sustaining its unique mode of current conduction.
At the low voltage, high current portion of the FBSOA
curve, the effect of on-resistance is evidenced in two different ways. First, at very low voltages, on-resistance can
limit the current. This is simply a manifestation of Ohm's
Law and does not indicate a stress-related limit. As Figure
9-29 suggests, the wide difference in on-resistances
between MOSFET and GEMFET is reflected in the onresistance limit of their respective FBSOA curves. Second, a lower on-resistance also increases a device's peakcurrent rating by virtue of its more efficient current conduction. This limit is stress related and also is illustrated
for both devices in Figure 9-29.
•
600
An RBSOA rating details the maximum drain-current
and drain-source voltage stress allowable during clamped
inductive turn-off_ If a device undergoes second breakdown at. some combination of VOS and 10 that is within
its pulsed power dissipation capability, an RBSOA derating curve is in order. In essence, an RBSOA derating
indicates that a device may fail due to localized hotspotting
even though its average junction temperature is within its
TJ(max) rating. Second breakdown of the MOSFET only
occurs when its maximum junction temperature is exceeded. Therefore, operation of the MOSFET is only limited by its TJ(max), 10M and VOSS ratings.
As for the GEMFET, special RBSOA considerations are
necessary to ensure optimum reliability. Junction temperature and turn-off speed are especially noteworthy parameters since they can dramatically alter the GEMFET
RBSOA capability. With all other conditions fixed, an increase in TJ can lessen the reverse-biased safe operating
area if the drain current is high. At turnoff, lower gatedrive impedances are also more stressful, as explained
below.
Figures 9-30 and 9-31 outline the operating limits of
typical MGM20N50 (20 A, 500 V GEMFET in a TO-204
Package). The figures are typical of the devices used in
this evaluation and do not represent a guaranteed RBSOA
rating. A more thorough evaluation is being conducted to
provide guaranteed curves for the data sheet. The gatedrive circuit used (Figure 9-32) allows adjustment of the
gate-drive output impedance at turn-off simply by varying
RGE·
To generate each "fail" point, a resistor, collector current and temperature were selected, then the magnitude
of the clamp voltage was increased until the device either
dissipated the coil's energy in avalanche or entered second breakdown. If the test device experienced a rapid
collapse of its collector-emitter voltage (which is charac-
600
IC = 15A
IC = 20A
RGE = 5.0 k
550
550
~\
\1\
;
RGE=1.0k- ~
\~\
500
r\\ .\
w
IA ~
RGE =
I\V\
~
~
~ .\
!::i 450
~
500n \
\~
,\, RGE = 5.0 k
~
~400
.
'\
\' l\
z
~
~
w 350
~
~
300
RGE=1.0k300
250
I I
~
RGE =
500 n '\
250
25
50
75
100
125
Tc. CASE TEMPERATURE
150
25
FIGURE 9-30 - EFFECT OF GATE DRIVE IMPEDANCE
AND CASE TEMPERATURE ON GEMFET RBSOA
50
75
100
125
TC. CASE TEMPERATURE
150
FIGURE 9-31 - EFFECT OF GATE DRIVE IMPEDANCE
AND CASE TEMPERATURE ON GEMFET RBSOA
MOTOROLA TMOS POWER MOSFET DATA
1-9-22
FIGURE 9-32 -
Presently, high voltage Darlingtons are the most commonly used switch in automotive ignition systems. The
advantage of using a GEMFET as its replacement is the
elimination of the Darlington's base drive circuitry. Since
the required switching frequency is below 1.0 kHz, the
GEMFET's high input impedance and low drive requirements make it ideally suited to be driven directly from
CMOS logic.
When the transistor - whether it be a Darlington, GEMFET, or Power MOSFET - turns on, the primary current
ramps up to 3.0 to 7.0 A (6.0 A peak for this exercise).
At turn-off, the inductive kick, or flyback voltage, is allowed
to rise as high as practical to produce the very high transformer secondary voltages (20 kV) required to generate
a spark. In the present systems that employ high voltage
Darlingtons, voltage is often clamped to about 400 V by
a zener placed from collector to base. As soon as the
collector-base voltage exceeds the nominal zener voltage,
the zener supplies the base current to the Darlington,
turning it on and thus clamping VCE to VZ. In this mode
the zener carries only a small fraction of the load current
and its power dissipation rating can be sized accordingly
(a collector-emitter zener must carry the full peak primary
current). On the other hand, the transistor is acting as its
own voltage clamp and must dissipate the energy contained in the inductive kick.
When a GEMFET is used in place of a Darlington, the
same clamping scheme can be used. If the zener is placed
across the drain and gate terminals, any zener avalanche
current soon charges the GEMFET's input capacitance
and initiates turn-on. With this clamping method, the GEMFET experiences the same high power dissipation interval
as the Darlington. One additional component is needed
in the GEMFET version of the clamp. A diode in series
with the zener is needed to block any current that would
otherwise flow if the gate were more positive than the
collector [high VGE, low VCEl·
Since the GEMFET performed very well in this evaluation, the question arises as to the applicability of the
power MOSFET in this same circuit. Again the comparison
is of the MGM20N50 and the MTM4N50, which are a
GEMFET and a MOSFET of identical die size. The first
consideration is that a peak drain current of 6.0 A exceeds
the MOSFET's 4.0 A continuous rating. This in itself is
not a problem, but thermal limitations are possible at
higher duty cycles and elevated case temperatures.
GEMFET RBSOA GATE DRIVE CIRCUIT
teristic of second breakdown), the non-destruct fixture rapidly (150 ns) removed energy from the OUT before its die
suffered damage.
Interestingly, the failure mechanism is not simply power
related, i.e., slower switching speeds and greater crossover times tend to increase its RBSOA. This is clearly
shown in the turn-off waveforms of Figures 9-33a and
9-33b. Even though the device enjoys lower switching
losses with an RGE of 51 n, its RBSOA is lessened. This
phenomena may be due to a very rapid MOSFET turnoff that places a dv/dt stress on the PNP bipolar.
If the GEMFET is turned off more slowly, the MOSFET
carries a greater portion of the load current and lessens
the strain on the bipolar during this critical portion of the
switching cycle.
The GEMFET is pOised to alter the options available to
power circuit designers. While its slow turn-off speeds limit
its potential applications at this point, the GEMFET's low
rCE(on) and high input impedance make it the technology
of choice for many applications requiring low frequency
switching.
An Application of the GEMFET
An ideal example of a GEMFET application would highlight its three strongest features. It would require a switch
with high blocking voltage capability, a large current rating
and simple drive requirements. The switching element in
an automotive electronic ignition control system is one of
many such applications in which the GEMFET deserves
consideration as an alternative to the switches currently
in use.
VCE
VCE
100 VIDIV
100 VIDIV
IC
IC
5.0 AlDIV
10 AlDIV
1.0 JLS
1.01'8
FIGURE 9-33a -
CLAMPED INDUCTIVE TURN-OFF WAVEFORMS
OF MGM20NSO - RGE
51 0
=
RGURE 9-33b -
CLAMPED INDUCTIVE TURN-oFF WAVEFORMS
OF MGM20NSO - RGE = 5100
MOTOROLA TMOS POWER MOSFET DATA
'-9-23
IC
2.0 AlDIV
VCE
100 VrolV 0
01
5.0,.slOIV
FIGURE 9-34 - AN AUTOMOTIVE ELECTRONIC IGNITION SYSTEM
IS AN APPLICATION FOR WHICH THE GEMFET SHOWS GREAT
PROMISE. THE SIMPLE GATE DRIVE CIRCUITRY (b) IS ONE OF
THE MAJOR ADVANTAGES IN THIS SYSTEM. BECAUSE OF THE
COLLECTOR-TO-GATE ZENER, CURRENT FALL TIME IS DICTATED
BY THE AMOUNT OF ENERGY STORED IN THE INDUCTIVE KICK.
Although the greatest stress on the switch occurs during
the clamping of the inductive kick and generation of the
spark, that clamping interval does not necessarily contribute more to the average power dissipation than does
the interval in which the switch is on and current ramps
up in the primary. This is especially true of the power
MOSFET due to its high rDS(on).
The difference between the on-resistance of the
MOSFET and the GEMFET becomes evident during the
monitoring of the case temperatures. Under the same
conditions (using a Thermalloy heat sink #60168), the
GEMFET's Te is 37°e, while the MOSFET's is 59°e,
representing a 2.5 W difference in power dissipation.
A second problem, again related to the, MOSFET's
higher rDS(on), also complicates its use in an electronic
ignition control system. Due to the limited battery potential,
especially during engine startup in very cold weather, the
rDS(on) of the switch must remain low so as not to limit
the peak current in the primary of the ignition coil. Therefore, the 1.5 n maximum specification for the MTM4N50
is probably too high for this application. In this test the
"battery" voltage must be increased by about 30% to
achieve the same primary current that the GEMFET
conducted.
In addition to its higher on-state efficiency, the GEMFET
can also offer a cost advantage over the power MOSFET.
A large portion of a power transistor's cost is associated
with its die area. Since the GEMFET can operate at.current densities at least five times that of a high voltage
MOSFET, significant savings can result from using a
GEMFET with a smaller die size.
MOTOROLA TMOS POWER MOSFET DATA
1-9-24
Chapter 10: Relative Efficiencies of TMOS and
Other Semiconductor Power Switches
which, in switch mode circuits, consists primarily of switching losses, both turn-off and turn-on, and saturation
losses. Since switching losses are a function of the switching frequency and saturation losses are relatively constant, a point is reached in the frequency spectrum where
one loss predominates over the other. Thus, in low frequency applications, devices with low saturation or onvoltage would show lower losses as measured by the
device case temperature, and at high frequencies, the fast
switchers would run cooler. This applies to all types of
semiconductors, be they power MOSFETs, Bipolars, Darlingtons, GTO (Gate Turn Off) SCRs or a GEMFET (Gain
Enhanced MOSFET) (A standard SCR can also be used
wiith com mutating circuitry; however, it is not included in
this evaluation due to the additional circuit requirements
and associated costs.)
The prime requisite of a power switch (semiconductor
or mechanical) is to transfer the maximum power to the
load. A comparison of the relative efficiencies of various
power semicond'uctor switches will be demonstrated with
three different switching loads: resistive, inductive and a
dc motor.
There are four factors that contribute to the system
losses: input or driving power losses due to the input
current and/or voltage required to turn on the device; saturation or static losses when the device is ON (a product
of the on-voltage and current); switching or dynamic
losses that result from the transition times when the device
is turned ON and OFF; and off losses due to the product
of leakage current and the power supply voltage. Generally off losses are by far the least significant since modern semiconductors have low leakage currents and can
be ignored in system loss calculations.
The variation of input power losses can be substantial
for the various semiconductors. As an example, a high
voltage switching transistor would have relatively low current gain and, consequently, requires relatively high input
base current to turn it fully on whereas a MOSFET, with
its extremely high static input impedance, would require
very little input power to turn it on.
. The output power losses are illustrated in Figure 10-1.
It is apparent that the switching losses, depending on the
switching frequency and transition times, can contribute
a large share of the total system losses. Thus, for high
frequency applications, where switching losses predominate, fast switching devices should be used. Conversely,
for low switching frequency applications, low on or saturation losses are more important.
Power MOSFETs are recognized as being extremely
fast switching devices, but are they more efficient than
bipolars in all or many switching applications? The answer
is - it depends. Efficiency is a measure of diSSipation,
1:
Temperature Testing High
Voltage Devices
TMOs versus Bipolar
Switch mode I and III
On Current
~
1.0
u
.
."
.s
.;,
Switching Losses
iii
~ c
d:o
:; t 0.25
s'~
°5
~
o~~~~~~~~~~~~~~~~~
FIGURE 10-1 -
NORMALIZED SWITCHING WAVEFORMS
FOR A RESISTIVE LOAD
A simple way of measuring the relative efficiencies of
the OUTs, one that measures the total device losses, is
by measuring the case temperature. This is accomplished
by attaching a thermocouple to the mounting flange of a
TO-204 (TO-3) package or tab of a plastic (TO-220) package. The first evaluation was to compare the switching
efficiency of three high voltage switching transistors the 2N6545, one of the first transistors characterized for
switchmode applications, called Switchmode I, (SMI); the
MJ16004, a state-of-the-art Switchmode III transistor
(SMIII) designed for higher frequencies; and the power
MOSFET MTM5N40. All these devices are of similar die
size and have similar ratings (Table 1). All were tested
with nearly identical loads and were driven by the same
test circuit, except that the forward input current (lBl) and
input resistance were scaled for the particular OUT). Reverse current or turn-off current was derived from the
same input clamp transistor switch and the magnitude of
this current (IB2) was dictated by the stored charge of the
device under test (OUT).
Since the input drive for both turn-on and turn-off can
be chosen to optimize the switching speed, the drives
selected were those generally shown on the data sheet;
Le., forced gains of 5.0 and 7.0, respectively, for the
2N6545 and the MJ16004; off-bias voltages of -5.0 V
and - 2.0 V for the above; and a gate-drive of greater
than 10 V for the MTM5N40 .
Resistive loads were chosen for the temperature riseversus-frequency test since the load current could be
maintained at a constant 2.5 A as the frequency was
varied. Recognizing that the "real world" load is usually
inductive and that inductive turn-off switching losses are
greater than turn-on due to the rectangular load line, a
single frequency (75 kHz) inductive test was also run. Due
to the different on-voltages and turn-off times for bipolar
and MOSFET devices, the load inductances had to be
slightly different to achieve the same peak collector (drain)
MOTOROLA TMOS POWER MOSFET DATA
'-10-1
•
TABLE 1 - Specifications of OUTs
Oie Size
(Area)
SMI
2N6545
SMIII
MJ16004
16Ox160 mil
(25600 mli2)
157x175 mil
(24649 mil:!)
TMOS
MTM5N40
126x182 mil
(22932 mil2)
5.0 A
IC.IO
8.0 A
5.0A
VCEO. VOSS
400 V
450'V
VCE(sal)max.
VOS(sal)max
1.5V@5.0A
2.5V@3.0A
2.5V@2.5A.
rOS(on) max =
1.0 (l
VCE(sal)typ.
VOS(sal)tYp
0.3 V
0.3 V
2.2V@0.90
7.0@5.0A
7.0@5.0A
hFE(min).
glslmin),
400 V
2.0 mhos@
2.5A
currents for a normalized test. For the 75 kHz test, the
peak ramp current of about 3.0 A peak was achieved with
inductances of 32 JLH and 27 JLH respectively when VCC
and VDD were + 16 V.
The temperature rise test fixture (Figure 10-2) consists
of a clocked, three-phase counter sequentially driving the
three respective switching circuits; thus, each device un-
der test is driven at a 33% duty cycle. However, at high
frequencies (Iowan times), OUTs with greater storage
times will effectively be powered for longer duty cycles
and therefore have greater saturation losses contributing
to the device temperature rise. As an example, at 150
kHz (period of 6.7 JLS) the 33% dc drive on-time of about
2.2 JLS would result in about 48% power on-time with only
1.0 JLS of storage time.
The clocks for this system, one for the resistive load
.case and the other for the inductive load, consist of two
CMOS gate configured RC astable multivibrators. Switchable timing capacitors set the frequencies for the resistive
load at 5.0, 25, 75 and 150 kHz respectively; the inductive
load clock is set at a fixed frequency of 75 kHz. The output
of these MV's clock the MC14002 Octal Counter Divider
connected as a three-phase ring counter whose respective emitter-follower, positive-going outputs control the
three virtually identical drivers.
Forward base current for the bipolar transistors is set
by turning on the NPN transistors 02 and 07 and the
following PNP transistors 03 and 08. To minimize storage
time, 03 and 08 are fashioned as constant-current generators, supplying the base currents to the 2N6545
SWS3A
+ 10 V
InductIVe
SWS3C
Load Sel
•
~4r-+~r+--~+-4r~~VO
VClamp
Inductive load
AstableMV
O.68",F
400 V
Vos
270
0.001 ",F
FIGURE 19-2 -
TEMPERATURE RISE FIXTURE SWITCHMODE I,
SWITCHMODE III, TMOS
MOTOROLA TMOS POWER MOSFE;T DATA
1-10-2
(~F=5.0, IS1 =600 mAl and MJ16004 (~F=7.0,
IS1 = 430 mAl for the inductive load current of 3.0 A peak.
Forward gate voltage for the ~ower MOSFET is generated
by turning on PNP transistor 013 (Saker clamped to minimize ts) and thereby applying nearly the full 15 V rail
voltage to the gate. The 15 ohm current limiting resistor
provides the low source impedance for quickly charging
(and thus switching) the MOSFET input capacitance Ciss.
Reverse bias voltage VSE(off) or VGS(off) for rapidly
turning off the OUTs, are derived by differentiating the
input pulse with the resistor-capacitor networks in the
base circuits of 04,09 and 014. The resulting negative
going pulses, which are coincident with the trailing edge
of the input pulse, then turns on the following respective
PNP transistors 04, 08 and 013 for about 3.0 JLS. These
transistors then turn on NPN transistors 05, 010 and 015
whose emitters are referenced to a negative Power supply; thus, the reverse bias voltages and resulting reverse
bias currents (lS2 for bipolars) are applied to the OUT for
the 3.0 JLS immediately following the turn-on pulse. This
reverse bias voltage can then be varied to determine its
effect on switching speeds, power dissipation and case
temperature rise. For the following described temperature
.tests the bias voltages were set for - 2.0 V and - 5.0 V
respectively, the presumed optimum values that are listed
in the respective data sheets.
The resistive loads, being somewhat inductive wirewound resistors, have turn-on switching current rise times
limited by the UR time constant (Figure 10-3) and thus
independent of input drive. However, the turn-off voltage
and current switching times are affected by off-bias (Figure 10-4); thus at optimum bias voltage, the switching
losses and therefore case temperature can be minimized.
This is quite evident in the curves of Figure 10-5 showing
temperature rise versus frequency at two off-bias voltages. All three devices showed slightly lower case temperatures (1.0 to 3.0°C) when the optimum off-bias was
used at the higher frequencies where switching losses
predominate.
The power MOSFET also runs cooler at higher off-bias
voltage. This is due to the charged input capacitance Ciss
being discharged more quickly when clamped to a greater
negative voltage; thus the turn-off switching speeds are
improved.
As expected at low frequencies, where on losses predominate both the 2N6545 (SMI) and the MJ16004 (SMIIi)
have temperature rises proportional to VCE(sat), both
being about 0.3 V at 2.5 A. The power MOS transistor
(TMOS), with a typical on-resistance rOS(on) of about 0.9
ohm [1.0 ohm(max)] has an on-voltage of about 2.2 V at
VCE ~ VDS
~ l00V/DIV
SMIIi vCE
SMI
VCE
TMOS
VOS
CONDITIONS;
VCC~
50V
50V
RL ~ 20 n
VOO~
f~
75 kHz
VeE(off) ~ -2.0 v
VGS(off) ~ -2.0 v
SMIiI IC
IC ~ 2.0 A/DIV
t
FIGURE 10-3 -
~
2.0 /ls/OIV
RESISTIVE LOAD SWITCHING OF
OUTs AT 75 kHz
VGS(off) ~ -2.0 v
VCE~
t
~
VGS(off) = -5.0
v
20V/OIV
1.0 !'SIDIV
IC = 0.5 A/OIV
t ~ 1.0i-
<
a:
w
45
~UOS
c..
:;
w
>w
...en
40
u
U
>-
,/
MTMtO
"I'
~~
. .1
1
VBE(ofI)
15.0
I
SM12N6545
I
.-e
35
f'
V
J
II
1 ~!.!
= - 2.0 V
SMI
lV
I I =Li-5.0
~ VBE(off)
~2.0 V.
F-74l VGS(off)
5.0 V
,..-:
I I II
= - 2.0 V
TMOS
SMIII MJ16004
30
25
1.0
5.0
10
25
50
75 100 150
500
1000
1. FREOUENCY (kHz)
FIGURE 10-5 - TEMPERATURE RISE OF SWITCHMODE
DEVICES AS A FUNCTION OF FREQUENCY
CONDITIONS:
VDS= l00V/DIV
0-
VDD= 16 V
L= 27 I'H
ID = 1.0 A/DIV
VGS(offl = -5.0 V
0FIGURE 10-6 - CLAMPED INDUCTIVE LOAD SWITCHING
WAVEFORMS OF TMOS MTM5N40
•
2.5 A, resulting in the higher case temperature. As the
frequency is increased, the extremely fast switching
MOSFET introduces little additional switching losses, resulting in a relatively constant case temperature.
The first generation SMI transistor shows the expected
increasing temperature rise with increasing frequencies
due to its relatively slow switching speed (the device was
designed for 20 kHz applications). By contrast, the Switchmode III transistor, MJ16004, which was designed for improved operation at higher frequencies with improved reverse bias safe operating area, shows a much lower case
temperature rise; in fact, it typically operated cooler than
the power MOSFET up to the 75-100 kHz range.
The illustrated temperature rise curves were derived
with typical devices. Testing of about ten sets of devices
produced similar results, although in some cases the effects of off-bias were not as pronounced due to slight
differences in device processing, temperature measurement repeatability and accuracy, particularly where small
differences in temperature had to be determined.
Although the curves show defined temperatures, the
magnitude of the rise is only relative as it is obviously a
function of the size and efficiency of the heat sink chosen.
For this exercise, small heat sinks were chosen to raise
the case temperature for higher differential temperature
measuremeflls. Secondly, the heat sinks (both the small
ones for the OUTs and the large ones for the resistive
and inductive loads) were thermally isolated from each
other to minimize mutual thermal coupling effects; (the
OUT heat sinks were mounted on ceramic standoffs and
the load sinks on plastiC washers to reduce thermal conduction to the chassis and hence to each device).
The vertical temperature axis of Figure 10-5 could have
been labeled Power Oissipation (PO), knowing the thermal
resistance of the heat sink (ROSA) used and the relationship between case temperature and thermal resistance
(PO =
Te- TA
Roes
+
). However, for relative efficiency
ROSA
conSiderations, measuring the device case temperature
will suffice.
For clamped inductive loads, the greatest switching dissipation generally occurs during turn-off where the device,
due to the rectangular load line, can be stressed simultaneously with both high current and voltage. The illustrated inductive loads simulate a flyback switching regu-
MOTOROLA TMOS POWER MOSFET OATA
1-1·0-4 .
VBE(off) =
-2.0 V
-5.0 V
-2.0V
-5.0 V
VCEM
vee=
IC=
0.5A/DIV
50V/DIV
1=
50 nslDIV
FIGURE 10-7 - CLAMPED INDUCTIVE LOAD TURN-OFF
TIMES OF SWiTCHMODE I 2N6545 WITH TWO OFF-BIAS VOLTAGES
ure 10-8 describe the turn-off times when the off-bias is
varied from 0 V, -2.0 V and -5.0 V respectively. As
mentioned previously, the greater off-bias results in the
lowest turn-off times.
The average temperature rise measurements of the
three OUTs for the inductive load case (Table 2) illustrates
the effect of off-bias on device efficiency.
A direct point-by-point comparison between the inductive load and resistive load tests at 75 kHz can't be made
since the respective load currents, and thus power dissipation are not the same. However, the trends can be
compared; Le., for the inductive load test, a greater temperature differential resulted between the optimum offbias voltage and the second tested voltage, being as high
as about 15°C for 8MI. By comparison, the resistive load
test showed only a few degrees difference. This is due to
the change in turn-off switching time having a greater
effect on the more energy stressful inductive load switching than on the resistive load.
-'
In addition to driving the bipolar devices with the recommended forced beta, f3F of about 5.0 and 7.0 respec-
lator where the energies stored in the inductors when the
OUTs are turned on are transferred via their respective
clamp diodes to the resistor-capacitor load during turn-off
time. By proper selection of this load, the resulting clamp
voltage was set for about 250 Vdc. The actual peak collector-to-emitter voltage VCEM overshoot can be somewhat higher, being dependent on the rate of collector current fall time tfi, the forward recovery time of the clamp
diode and the degree of proper RF layout (Figure 9-7). It
is not uncommon for this overshoot to exceed the clamp
supply voltage by 100 Volts.
An example of how reverse bias affects the switching
speed, and thus efficiency, of the 2N6545 is shown in the
photos of Figure 10-7. Note the difference in t s , tfi, VCEM
and collector-emitter voltage rise time t rv . At the optimum
bias of about - 5.0 V, the device turns off faster, there is
less energy to be dissipated and a lower case temperature
results. This is also true of the other two OUTs.
Although there is no "storage time" associated with
FETs, there is a turn-off delay time tdCoff) due to device
capacitances having to be discharged. The photos of Fig-
CONDITIONS:
f = 75 kHz
VDD= 50 V
VGS(off)=OV
RL = 20 n
01 = 1.0 psi DIV
VDS
0VGS(off) = -5.0 V
VGS(off) = -2.0 v
FIGURE 10-8 - THE EFFECT OF OFF-BIAS VOLTAGE
VGS(olf) ON TURN-OFF TIMES OF TMOS MTM5N40,
RESISTIVE LOAD
MOTOROLA TM08 POWER M08FET OATA
'-10-5
parably sized first generation power MOSFETs.
Technology advancements of Motorola power MOSFETs have been made to significantly reduce the onresistance, rDS(on) to make these devices competitive with the bipolars.
TABLE 2
Temperature Rise of an Inductive Load
f
75 kHz, ICM
3.0 A, VCEM '" 250 V
=
=
Case Temperature
Off-Bias
Voltage
SMI
SM'"
TMOS
-2.0V
58°C
34°C
. 42°C
-5.0 V
43°C
39°C
38°C
• Switch mode III MJ16004 compares favorably to
power MOSFET MTM5N40 at 75 kHz with an offbias of - 5.0 V and generally runs cooler at the optimum bias of - 2.0 V (relative to - 5.0 V for TMOS).
Although not described in this text, the SOA of SMI
& SM'" is not as large as TMOS.
• For "real world" inductive loads, where the tum-off
switching losses predominate, insufficient off-bias
can produce higher case temperature rise for SMI
transistors due to slower tum-off switching speeds
(e.g., @ 75 kHz TC = 58°C for VBE(off) = -2.0 V
compared with 43°C for -5.0 V).
tively for the 2N6545 and MJ16004, a brief test was conducted by reversing f3F (7.0 and 5.0 respectively).
Although the dynamic saturation characteristic of the bipolars changed subtly due to different base drive, and the
tum-off switching time (even with off-bias) changed by
only a second order, the change in power dissipation was
minimal, if any. Within measurement repeatability, the resultant case temperatures were about the same, suggesting no great requirement of maintaining a defined f3F.
Examination of the above test results, the resistive temperature curves and the photos of the switching waveforms lead to the following conclusions about the switching efficiency of the test devices:
• Optimum off-bias will reduce tum-off switching times
and thus switching losses for the bipolars and FET,
but does not necessarily minimize the storage time
(e.g., for SM'" tfi(min) and ts(min) occur at about
- 2.0 V and - 5.0 respectively.
• Under optimum off-bias voltage condition, the tf of
SM'" approaches that of the very fast TMOS, however, drive power is high.
• The temperature rise results are a measure of total
device dissipation, including the input drive loss.
• Switchmode I 2N6545 can be comparably operated
to 75 kHz when there is sufficient off-bias voltage (or
reverse base current), approximately - 5.0 V.
• The fast switching speeds of TMOS coupled with the
low drive power requirements and relatively simple
drive circuitry make the MOSFET an attractive high
frequency device.
• Storage time, when it is not compensated for by circuit feedback techniques, somewhat affects efficiency at high frequencies due to increased ON
losses.
• Power MOSFETs become 11'\0re efficient at frequencies beyond about 100 kHz when compared to the
new generation of switch mode bipolar transistors.
• Specified force beta f3F of the bipolars are not too
critical for efficiency considerations as the tum-on
times are partially dictated by the load. Off-bias tends
to minimize the storage time effects as f3F is varied;
however, excessive overdrive can cause IC tail lifts
during tum-off which may contribute to larger temperature rise.
• Power MOSFETs have lower td(off) when sufficiently
reverse biased than bipolar ts , thus allowing a higher
operating frequency.
• At low frequencies, ON (static) losses predominate;
thus bipolars are presently more efficient than com-
Low Voltage Devices: TMOS versus
Bipolar, Darlington and GTO Devices
PWM DC Motor Controller Test
Due to the motor time constant, the switching frequency
was set for about 100 Hz and the min/max duty cycles
were about 8% and 70% respectively. At this low frequency, the use of off-bias for the bipolar, Darlington and
TMOS produces negligible improvement in efficiency as
the decrease in tum-off time is extremely small for the
time frame involved. However, the GTO does require offbias which for this test circuit and OUT was as much as
2.2 A lasting for about 10 /JS. This tum-off power should
The load used in this test is a dc motor whose speed
is controlled by PWM. Consequently, when narrow pulse
widths are applied - low speed - the back emf is low
and the load current (collector, drain or anode current) is
high, about 11 A. To ensure device saturation under this
worst case condition, adequate input current must be applied. For the devices tested, the forward input current for
the bipolar, Darlington, TMOS and GTO were about 700
mA, 100 mA, 1.0 mA, and 120 mA, respectively.
MOTOROLA TMOS POWER MOSFET DATA
1-10-6
lington transistor 01 furnishes the buffered output to drive
the two channels of the power amplifier, with transistors
02 and 03 supplying the positive input current to the OUT
and 04 and 05 the negative current. When the OUT Selector Switch S1 is in positions 1, 2, or 3, the full pulse
width will be applied to the OUTs as differentiating capaCitor C1 is shorted out. Thus, positive input current is
generated by the direct coupled pulse turning on the NPN
transistor 02 and the following PNP transistor 03 connected, in positions 1, 2, and 4, as a constant current
source. The respective emitter resistors set the current
IB1 or IGT for the OUTs. Negative current is derived by
differentiating the input pulse with C2, R2 and using the
negative going, trailing edge pulse for turning on the following PNP transistors 04 and NPN clamp transistor 05.
Thus, an off-bias voltage (clamped by diodes 01 and 02)
is supplied to the selected OUT. If required, the off-bias
can be removed by the Negative Bias Switch S2.
The GTO requires only a relatively narrow positive gate
current pulse to turn it on. This pulse is derived from the
differentiating network C1, R1 (switch S1A open), with the
positive going, leading edge pulse turning on 02 and 03.
For the component values shown, a turn-on, positive drive
current pulse IGT of about 120 mA in amplitude and 40
be considered in the efficiency calculations. At low frequencies, it is relatively small, but as frequency increases,
it can become substantial (refer to Figure 10-10 for drive
circuits and input power equations).
The bipolar, Darlington, and TMOS are turned on by
the input pulse whose width is a function of the required
motor speed, whereas the GTO is turned on by a relatively
narrow, positive gate current pulse and turned off by a
narrow, negative gate current pulse. As the frequency is
increased it is apparent that the GTO input power increases and will reach a point where its input power is
greater than that of the bipolar or Darlington. This crossover frequency is a function of the power supplies used
and the particular duty cycle chosen. As an example, for
a 50% duty cycle with the illustrated power supplies, this
crossover point between the Darlington and GTO would
be about 2.0 kHz.
Test Circuit Analysis
The test circuit, shown in Figure 10-9, consists of a two
gate CMOS, astable multivibrator (MV) clocking a CMOS
configured monostable multivibrator (MV) to produce the
approximate 100 Hz, variable pulse width output. Dar-
PULSE
WIDTH
+12 V
CONTROL
f", 100 Hz
MC 14001
OUT +12V 0 - + - - - ,
SEL SW
V+
4 0 S1A
METER
SWS3A
OJ
82
M
MOTOR: PHOTO CIRCUITS
TYPE U9M4H/US
30 v, 4.S A, 3250 RPM
TACHOMETER: IV/1000 RPM
+14V
IN
MR750
OUTS MOUNTED ON
THERMALLOY G107
HEAT SINK
02
C2
10
25W
MJE
200
IN914
04
05
01
4
as
1N
4001
33
39
SWS2
NEG BIAS
4.7 V
1.5W
1N5917A
-12V
BIPOLAR
2N6487
v-
FIGURE 10.9 -
DARLINGTON
TIP 100
TEST CIRCUIT FOR MEASURING RELATIVE EFFICIENCY OF OUT
MOTOROLA TMOS POWER MOSFET DATA
1-10-7
TMOS
MTP 12N06
GTO
THYRISTOR
p,s wide is generated, followed by an approximate - 6.0
V, 35 p,s wide turn-off voltage pulse that is coincident with
the trailing edge of the input pulse. This voltage pulse
produces a reverse current IGR of about 2.2 A for 10 p,s .
(anode current of about 11 A) when the stored charge is
depleted. Obviously, if no reverse bias is applied (Switch
S2 open), the GTO will lose control, always being on, and
the motor will run at its maximum speed.
Relative Efficiency Measurement of OUTs
In order to measure the relative efficiencies of the OUTs,
both input power and output power are recorded. This is
simply done by switching in a current meter to measure
the average input current, or a voltmeter to measure out-
put RPM by means of a tachometer coupled to the motor.
The output voltmeter, in effect, measures the relative saturation loss of the OUT since this voltage is subtracted
from the applied motor voltage and, consequently, the
motor speed will be indicative of this loss. Only the relative
positive input current is measured as the reverse currents
at this low frequency contribute very little additional drive
power. However, as the power equations note in Figure
10-10, with increased operating frequency, this off-bias
power can be substantial.
The relative efficiency measurements for the four OUTs
are listed in Table 3. Of interest, in regard to efficiency,
are the measured Input currents (both pulsed and relative
average), and tachometer outputs, on-voltages and case
BIPOLAR, DARLINGTON
10~N_
t:F1
~tOFF2
102
•
TMOS
I~~
~tOFF
IGR
v-
GTO
FIGURE 10-10 - OUT DRIVE AND INPUT POWER CALCULATION
MOTOROLA TMOS POWER MOSFET DATA
1-10-8
temperatures. Within measurement repeatability, the
OUTs with the highest on-voltage had the lowest relative
output power due to reduced motor voltage and the case
temperature rise correlated with the total power dissipation (input plus output). These readings g~nerally confirmed what was expected:
TABLE 3 - Relative Efficiency Measurement of OUTs
DUT
mos"
Bipolar
2N6487
Darlington
TIP 100
MTP12N06
GTO
Thyristor
110 x 130
12()2
1202
la02
Voltage
Rating
60V
SOV
60V
300 V
Current
Rating
15A
8.0A
12A
lOA
Switching Speeds
(Relative)
Medium
Medium
Fast
Slow
Input Current,
(Forward/(P'W.)
700mA
100mA
1.0 mA
120 mA (40 I's)
Input Current,
Reversa/(P.W.)
1.0 A @ IMAX (0.2 I's)
Die Size (MIL)
0.4 A @ IMAX (0.1 I's)
0.2 @ IMAX (0.1 I's)
2.2 @ IMAX (10 I's)
Duty Cycle
8%
12%
56%'
8%
12%
81%'
8%
12%
74%'
8%
12%
68%'"
Load Current, Peak
11 A
5.0A
0.9A
11 A
5.0 A
0.9 A
11 A
5.0 A
0.9A
11 A
5.0A
0.9 A
Power In (Relative)
5.0
13
75
3.0
4.0
11
1.0
2.0
2.0
1.0
2.0
2.0
Power Out (Relative)
20
59
85
16
57
84
17
59
87
17
55
84
1.9 V
1.3V
1.0V
2.8 V
2.0 V
1.6V
12V
12 V
12V
1.4 V
1.2V
0.85 V
VConllN
VConlOUT
Case Temp
1.2V
0.4 V
0.12V
2.1 V
1.3 V
0.78 V
1.7V
0.9 V
0.15 V
2.0 V
1.5V
1.0V
36.6'C
32.9'C
38.3'C
43.6'C
41.3·C
40.4·C
42.3'C
36.0·C
29.5·C
39.5·C
41.1'C
38.2·C
·Clock varied with temperature
**Oata was taken on first generation TMOS devices. Later device designs give a dramatic improvement In on-state efficiency of low voltage devices.
mos
MTP12N06
At low frequency and low motor current, the TMOS is the most
efficient device. Its input drive power is extremely low and its On
voltage, due to the zero offset, relatively linear rDS(on) is low.
DARLINGTON TIP100
Total device dissipation and thus case temperature rise is due to
input and output dissipation. The Darlington, with Its high VCE(sat),
can still have lower case temperature than the bipolar at some peak
collector currents, due to Its low drive power.
BIPOLAR 2N6487
The bipolar, with its low VCE(sat), has low output dissipation but
Its input power is the highest to satisfy high collector current- forced
(3 conditions.
At medium and high loed currents, the bipolar has the lowest On
voltage followed by the TMOS with the Darlington and GTO being
about equal in third place.
GTO THYRISTOR (Experimental)
The GTO is extremely efficient at low frequencies from a drive
point of view since It requires only narrow turn-on and tum-off current
pulses, but becomes less efficient as the frequency increases due
to the higher duty cycles involved.
Efficiency as a Function of Frequency Tests
The PMW Motor Control Circuit was tested at a constant, low frequency, so the relative efficiencies measured
were primarily due to static (saturation) losses. To determine the effect of the dynamic (switching) losses, which
increase with increasing frequencies, the four different
devices were tested with a resistive load, using a variable
frequency, constant duty cycle (50%) input signal. The
load current was set for about 4.0 A (VCC = 28 V,
AI =7.0 0) and the same basic test circuit shown in Figure 9-9 was used. Most of the modifications were in the
reverse bias circuit, with the off-bias voltage being either
o V or - 5.0 V for the bipolar, Darlington and TMOS tests
and -12 V for the GTO.
Transistor 04 emitter resistor (2.0 0) was shorted out
to form an off-bias voltage source; 03 emitter was tied to
the + 12 V bus to furnish drive to 04 when VBE(off) was
oV; and differentiating capacitor C2 was increased to 0.02
p,F to allow greater turn-off time for the GTO. Also, the
bipolar forward base current was set fo 600 mA, resulting
in a f3F of about 7.0.
Test Results
The results of this efficiency versus frequency test, as
measured by the case temperature rise using a small
heatsink, are shown in Figure 10-11.
TMOS MTP12NO&
As expected, the TMOS device ran the coolest at higher
frequencies, being very constant in temperatures up to
about 10 kHz and then rising slightly thereafter. At low
frequencies, where static losses predominate, the TMOS
MTP12N06 case temperature was only about 2"C warmer
than the bipolar 2N6487, due to the respective saturation
voltages of about 0.6 V (rDS(on) Typ= 0.150) and 0.4 V.
Although not shown, increasing the off-bias voltage
(VGS(off)) from 0 V to -5.0 V showed only about a 2"C
improvement at 33 kHz, due to slightly faster turn-off time;
otherwise, at lower frequencies, the difference in turn-off
I1me had little effect in case temperatu~e.
Bipolar 2N6487
The bipolar transistor 2N6487 showed marked improve-
MOTOAOLA TMOS POWER MOSFET DATA
1-10-9
140.-----------r------------r-----------r------------r----------,r-----------~
VBE(off) = 0 V
RESISTIVE LOAD
120
r--------
LOAD CURRENT = 4.0 A
DARLINGTON
DUTY CYCLE = 50% -+-----------+------------+-----------.J----=.~::::.......:..:...::.:.:.._l
VBE(off) = 5.0 V
TA=25"C
HEAT SINK: THERMALLOY
6061B
100
e
GTO
w
a:
0----0
::l
!;(
a:
80
1------------+6.--.....06.
o----{]
it
::!i
\J----"SV
I:!!
BIPOLAR 2N6487
V GR =-12V
DARLINGTON TIP 100
~
/
TMOS MTP 12N06
/
VBE(off)
/.
GTO THYRISTOR
= -5.0 V
w
CI)
()
,...u
60
o
~
________- L__________
0.1
0.3
~
__________ _ L_ _ _ _ _ _ _ _ _ __ L_ _ _ _ _ _ _ _
--~----------~
3.0
1.0
10
30
f. FREOUENCY 1kHz)
FIGURE 10-11 -
TEMPERATURE RISE OF POWER SEMICONDUCTOR AS A FUNCTION OF FREQUENCY
ments in efficiency at the higher frequencies when the
VBE(off) was increased from 0 V (base-emitter clamp) to
- 5.0 V. Without off-bias, the case temperature approached 115°C at 33 kHz, whereas, with - 5.0 V, it was
only about 70°C.
Darlington TIP100
•
The low voltage TIP100 Darlington does not have a
speed-up diode across its input emitter-base resistor and
thus the stored charge of the output transistor cannot be
efficiently removed. Consequently, there is no improvement in case temperature at low or nominal frequencies and only some moderate improvement at 33 kHz
(117°C r~lative to 133°C) when the off-bias was increased
to -5.0 V.
The Darlington, with the highest saturation voltage of
the four devices, not surprisingly, had the highest case
temperature at low frequencies and, beyond 5.0 kHz, was
about as inefficient as the GTO.
GTO (Experimental)
The experimental GTO exhibited static losses somewhere between the bipolar and the Darlington due to its
on-voltage of about 1.2 V at 4.0 A. The device did perform
at 33 kHz, however, its case temperature rose to about
125°C. This was due to its relatively slower switching
times, as shown by the oscillograms in Figure 10-12. Figure 10-12 (a), (b) and (c) show the 33 kHz waveforms of
anode current, anode-cathode voltage and gate current,
respectively, relative to the TMOS drain current (Figure
10-12d) and drain-source voltage (Figure 10-12e). Note
that the load current rise time is limited by the inductance
of the wire-wound load resistor and that the TMOS
switches much faster. Second, to ensure turn-off of the
GTO at elevated temperatures, the peak reverse gate
current with VGR of -12 V was about 6.0 A with a pulse
width of about 1.0 JLS at the 50% point.
THE GEMFET versus THE
MOSFET AND BIPOLAR
The GEMFET (Gain Enhanced MOSFET) is a new
power semiconductor device with a combination of characteristics that were previously unavailable to the designer
of power circuitry. Closely related to the power MOSFET
in structure, this device has a forward voltage drop comparable to bipolars while maintaining the high input impedance and fast turn-on of its isolated gate. While turn-on
speeds are very fast, turn-off is presently relatively slow
and will restrict the use of at least the first generation of
these devices to lower frequency applications.
The most pronounced advantage of the GEMFET over
the power MOSFET is its lower on-resistance. The
rDS(on) of a high voltage MOSFET is fairly large and rises
with increasing junction ,temperature and drain current.
Conversely, the rCE(on) of a GEMFET decreases with
increasing TJ and is not greatly affected by IC' Since the
MOSFET does not have the GEMFETs offset voltage in
its output transfer characteristics, at low currents the
MOSFET on-resistance is slightly lower. However, at high
currents and temperatures, the difference is dramatically
in favor of the GEMFET.
MOTOROLA TMOS POWER MOSFET DATA
1-10-10
IA =lA/DIV
t = Sl's/DIV
0-
FIGURE 10-12a -
FIGURE 10-12b -
GTO ANODE CURRENT
GTO ANODE-CATHODE VOLTAGE
MCR SOSO
0RL~7n
WIREWOUND
RESISTOR
IG = 2A/DIV
t= SI's/DIV
FIGURE 10-12c -
GTO GATE CURRENT
ID= lA/DIV
t = Sl's/DIV
0-
FIGURE 10-12d -
TMOS DRAIN CURRENT
FIGURE 10-12 -
FIGURE 10-12& -
TMOS DRAIN-SOURCE VOLTAGE
COMPARATIVE SWITCHING OF A GTO AND TMOS AT 33 kHz
To illustrate the relative efficiencies of these two
TO-220 devices - MGP20N50 GEMFET and MTP4N50
MOSFET - with that of a comparable die size, TO-220,
high voltage Switchmode bipolar MJE13007, the low frequency, PWM motor controller test described in the previous section was performed. The results of a duty cycle
versus case temperature rise test is shown in Figure 1013. Note that at his low frequency test, where saturation
losses predominate, the GEMFET is much more efficient
than the MOSFET at low duty cycles (high motor armature
currents), and even runs cooler than the bipolar device
as the pulse width increases (motor current decreases).
The second test, comDaring the three devices with an
inductive load at sever&1 frequencies (the inductances
were changed to maintain the same peak currents for all
frequencies) is illustrated in Figure 10-14. Now, at the
higher frequencies, the GEMFET runs the hottest - due
to its slow turn-off switching time - and the MOSFET
becomes more efficient than the bipolar at about 25 kHz.
For more information on the GEMFET, please refer to
Chapter 9, the Spin-off Technologies of TMOS.
MOTOROLA TMOS POWER MOSFET DATA
1-10-11
80
70
E
w
co
~
~
'"
I!!
III
50
!ll
5
~
40
E
120
w
co
=>
\
60
=>
150
!;;:
90
~
::;;
I!!
~
\ "'"[> /
V --r--..
./
V
~
30
0.2
0.5
FIGURE 111-13 -
30
40
50
DUTY CYCLE 1%)
-.
GEMJT
60
MGP20N50
MOSFET
MTP4N50
2.0
5.0
10
f, FREQUENCY 1kHz)
1-....
... -
BIPOLAR
MJE13007
20
50
100
FIGURE 111-14 - COMPARISON OF CASE TEMPERATURE
versus FREQUENCY FOR A GEMFET, MOSFET
AND BIPOLAR TRANSISTOR
30
20
1.0
A'
~EM~ETI
--- -
,,/
10
A
-C._
-
--
0.1
.
/
60
~
BIPOLAR TRANSISTOR
INDJCTI~E ILJA~ IIII
10M = ICM = 5.0A
DUTY CYCLE = 25%
TA = 25'C
HEAT SINK: 4" x 4" x Yo"
COPPER PLATE
70
BO
ON-STATE EFFICIENCY COMPARISONPWM OF DC MOTOR
MOTOROLA TMOS POWER MOSFET DATA
1-10-12
Chapter 11 : TMOS Die for Hybrid Packaging
Using TMOS Die for Hybrid Assembly
Wire Bonding
Electrical connection to the gate and source bond pads
can be accomplished by ultrasonic wire bonding, using
AIMg' wire having an elongation of 10%. Caution should
be exercised during wire bonding to insure that the bonding footprint remains within the bonding pad area. Wire
bond settings should be optimized and a wire pull test
performed (see Method 2037, Mil Standard 750B) to monitor wire bond strength uniformity. Destructive sample testing and 100% non-destructive testing is recommended.
'Wire sizes of 15 mils and greater are pure AI.
Substantial savings in weight and volume can be
achieved by hybrid packaging techniques. Selected Motorola TMOS packaged devices are available in die form for
custom hybrid assembly. The same advanced MOS processing techniques and silicon-gate structure available in
packaged form is available in die form. The unique TMOS
design utilizes thousands of source sites, interconnected
in parallel, on a single die. This structure minimizes onstate voltage drop. The TMOS processing techniques
result in an extremely reliable device which is highly
reproducible in various die sizes.
Die Characteristics
Several die sizes are available with voltages ranging
from 50 to 500 volts. All die are individually probed, at
room temperature, to the dc electrical specifications of
their equivalent packaged device.
Due to limitations when probing in wafer form, some of
the specifications of the equivalent packaged device cannot be tested and guaranteed in die form. These parameters are safe-operating area (SOA), thermal resistance
(R6JC), and on-voltage at full rated current. The above
parameters depend on the assembly techniques of the
individual user.
Visual Inspection of Die
All Motorola TMOS dice meet the visual inspection criteria of Mil-Standard 750B, Method 2072, with the exception of specific criteria listed below. All TMOS dice are
visually screened to a 0.1 % AQL level.
Die Backing
All standard TMOS dice come with Titanium-NickelSilver drain metallization. This metallization is suitable for
solder pre-form mounting with solders such as 95/5 PbSn
or 92.5/5.0/2.5 PblnAg. Commonly used header or substrate materials such as copper, nickel plated copper, gold
plated molybdenum, beryllia and alumina are acceptable.
The substrate material must be free of all oxides prior to
assembly. Mounting is generally accomplished in a profiled belt furnace (hydrogen atmosphere is recommended). The use of solder fluxes is not recommended.
Encapsulation
Before encapsulation, the assembly must be kept in a
moisture free environment. IGSS and VGS(th) are sensitive to surface moisture. For a non-hermetic package,
a high grade electronic coating such as Dow Corning
RTV3140 should be applied (coating is optional with a
hermetic package). Before encapsulation, a 150°C twohour bake should be performed to remove any surface
moisture and any capping of hermetic packages must be
performed in a dry, nitrogen atmosphere.
,I
1
'I
Handling and Shipping
TMOS Dice are available packaged several ways:
1. Anti-static MultiPak vidual die package.
Waffle type carrier with indi-
2. Scribed and Broken Wafers - Wafer on Mylar and
vacuum sealed in plastic, with rejects inked.
3. Wafer Pak -
Whole wafers, with rejects inked.
4. Circle Pak - Whole wafer is placed on sticky film
before being sawed and broken. Special equipment
is needed to remove die from sticky film, with rejects
inked.
Upon opening the plastiC container, dice should be
stored in a nitrogen atmosphere to prevent oxidation of
bond areas prior to assembly. All dice should be handled
with teflon tipped probes to prevent any mechanical damage and the probe needles should be dipped in a conductive solution as teflon can cause ESD problems.
MOTOROLA TMOS POWER MOSFET DATA
1-11-1
"
.J
•
MOTOROLA TMOS POWER MOSFET DATA
1-11-2
Chapter 12: Characterization and Measurements
FBSOA Testing of Power
MOSFETs
trois the desired drain-source voltage, VDS, drain current,
ID, and pulse width in order to provide a defined energy
to the DUT. Second, it protects the device just as it starts
to fail; and third, once an overstress is detected, it removes
power from the system.
The N-channel circuit is shown in Figure 12-1 and will
be described. (The P-channel circuit is virtually identical
except for inversion of power supplies, logic outputs and
complementary transistors.) Controlled drain current is
applied to the common source connected power MOSFET
by means of the feedback loop around its gate-source
with op-amp Ul being the error amplifier. The loop will
force the source voltage (developed across the drain current sense-resistor Rt) to be equal to the reference voltage that is applied to the non-inverting input of Ul. The
gate-source voltage will automatically assume that value
required to produce the required drain current. Thus, by
varying the reference voltage by means of the ID Adjust
control, a defined, accurate drain currel}t can be chosen.
Drain-source voltage is applied to the DUT through a
current-limiting inductor L1 (to reduce short-circuit current) and a series-connected Darlington NPN switch, 09.
Thus the drain voltage is approximately equal to the VDD
power supply (neglecting the VCE(sat) of 09).
The series Darlington, configured as an emitter-follower, is controlled by level translating NPN high voltage
transistor, 07, and the following PNP high voltage transistor, 08. Transistors 08 and 09 are in effect a compound Darlington and 07 acts as a current source to
minimize drive variations when VDD is varied. System
operation begins by applying a positive-going pulse by
means of an external pulse generator to the base of 07,
thus turning on the switched drain supply. The gate is also
turned on, but is slightly delayed by the R3Cl base integrating circuit of the unclamped transistor 01 to minimize turn-on stress on the DUT.
A fast video amplifier, U2, also monitors the DUT
source, looking for a current spike. This amplifier, connected to produce a voltage gain of 200 with a bandwidth
of 40 MHz, will quickly detect the advent of the destructive
current spike and amplify it to a level to trigger a fast
discrete RIS flip-flop.
To "lock-out" false signals that may occur due to device
turn-on, an N-channel FET series switch, 02, is connected
between the video amp and the flip-flop. This FET is controlled by PNP driver, 010, NAND Gate, G3, and inputpulse-triggered monostable multivibrator Gl and G2.
Thus, by varying the Pulse Width Adjust, R4, the first 5.0
to 50 ms of the switched drain current can be blanked to
prevent false triggering of the circuit.
A "true" trigger will turn on PNP transistor 03 of the
flip-flop whose output is buffered by NPN transistor 05.
The positive-going signal will then turn on the fast crowbar
power MOSFET 06, thus quickly diverting the energy from
the DUT. The high level flip-flop output from 03 will also
turn on the LED - indicating a crowbar occurrence and clamp off the input pulse generator by means of
turned on transistor all. Consequently, Darlington 09 is
Power MOSFETs are essentially free of second breakdown; at least in the sense that second breakdown is
defined for bipolar transistors. If second breakdown is
defined as a region in which total allowable power dissipation decreases as drain-source voltage increases, the
power MOSFETs do exhibit a second breakdown behavior. However, this phenomena occurs at power levels in
excess of the device rating. In terms of measured safearea capabilities, power FETs commonly show higher
power dissipation capability at lower voltages than they
do at voltages approaching V(BR)DSS.
The phenomena which causes apparent second breakdown in FETs is similar to bipolar second breakdown in
that increasing drain-source voltage widens depletion regions, allowing less of the silicon area to be used for
current conduction. In FETs, higher voltages constrict the
vertical channel somewhat, reducing the total area for
current conduction and the maximum power dissipation
capacity. Unlike bipolar transistors, there is no regenerative action associated with the current constriction. Its
effects, therefore, are much less severe; so much so that
FETs are generally regarded as being free of second
breakdown. In general, consideration of the thermal ratings is all that is required when devices are operated within
their current and voltage ratings.
To ensure that the power MOSFETs do not exhibit any
limitation within the thermally limited portion of the FBSOA
curve (the theoretical locus of constant power based on
the thermal resistance), the DUTs were subjected to energy levels beyond the curve. As in turn-off switching
SOA, a non-destruct tester would be advantageous, allowing one DUT to be used to generate a complete curve.
An important advantage of a non-destruct fixture is that
it can give individual device trends and, from that, clues
to the actual failure mechanism. Some have indicated that
a steepening of the SOA slope at high-voltage, low-current
indicates breakdown due to negative resistance effects
(43,44).
The non-destruct fixture is also safer and is easier on
larger power supplies. If a destructive tester were to short
out a device, there is nothing to limit the current flow until
the device heats to the point of opening up. This nondestruct fixture turns off the power supply and harmlessly
dissipates the energy in the circuit.
Basic Theory
When a power MOSFET is operated just outside its
SOA, the drain current, ID, will suddenly increase very
rapidly as the device breaks down. Unless the energy can
be removed very quickly, the device will be destroyed.
The basic idea of the non-destruct fixture is to sense this
current surge and divert the energy from the Device Under
Test as rapidly as possible. The fixture reacts within approximately 100 ns and usually saves the device.
Circuit DesQription
The circuit performs three main functions. First, it con-
MOTOROLA TMOS POWER MOSFET DATA
1-12-1
FIGURE 12-1 -
N-CHANNEL POWER MOSFET NON-DESTRUCT FBSOA TESTER
also turned off. To protect the crowbar FET and 09, which
are both on for about 30 J.£s due to propagation delays,
current limiting inductor L1 is placed in series with the
power loop.
The system is reset by depressing push-button S1, thus
placing the flip-flop in the proper state. The resistor R5,
capacitor C2 and diode 01 network in the base circuit of
04 ensure that the flip-flop will be in the proper state when
power is first applied.
The circuit also has over-current protection. A second
current sensing resistor R6 in the return bus of the VOO
supply monitors the input current and activates the flipflop if more than 10 A is sensed. This is accomplished by
comparator U4 and its associated pulse steering cir<::uitry.
The P-channel fixture shown in Figure 12-2 is nearly
identical to the N-channel except that it contains its own
pulse generator and its supplies and transistors are inverted. The pulse generator uses a quad, two input NOR
gate to produce the required astable multivibrator (A1 and
A2) that clocks the following monostable multi-vibrator (A3
and A4).
indicating that the crowbar was only being activated when
the device was beginning to fail.
Normally, a one second pulse was used, but other pulse
durations were investigated. Time was allowed between
pulses for cooling. A two second pulse did not significantly
change the FBSOA curve. Tl'\e device would handle about
20.0% more power during a 0.1 second pulse and the
slope of the FBSOA curve remained the same (Figure
12-3).
Ouring a 10 ms pulse, the device handled another
20.0% more power before failing. Since the blanking period lasts at least the first 5.0 ms of the 10 ms pulse, the
fixture had difficulty saving units at this high energy level.
The implication of this test is that the mechanism causing
crpwbarring is energy (time) dependent, tracking somewhat the thermal response of the device. Presumably, the
junction temperature when the fixture crowbars is about
the same for all pulse width variations.
Careful testing, I.e., slowly increasing the energy level,
can ensure multiple crowbar activations of the OUT. One
N-channel device went through 30 crowbars with no degradation in rOS(on), leakage current or drain-source
breakdown voltage. Parts were either saved without degradation or destroyed, usually shorted from drain-tosource.
The case temperature of the TO-220 MTP5N20 (RIJJC
= 1.67°CIW), using a large finned, air cooled heat sink,
rose to about 120°C when the OUT activated the crowbar.
The applied power of 150 W thus produced a calculated
junction temperature of about 370°C. At first glance, the
Motorola parts appear to be rated with a fair amount of
guardband. The actual FBSOA guardband is even larger
since the rated curve assumes a case temperature of
Testing Mechanics
The intended use of the FBSOA test fixture is to ensure
that device operation is limited only by its specified power
rating based on a measured RIJJC and not a second
breakdown of the parasitic bipolar transistor or any other
phenomena.
To determine if the device was actually facing failure
when the fixture crowbarred, VOS was held constant and
10 was gradually increased with successive pulses until
the fixture crowbarred. Then the crowbar was disabled
and the device was pulsed again. JtJe device would fail
MOTOROLA TMOS POWER MOSFET OATA
1-12-2
121
20 F
JOV
180
112W
MR750
-20 v .....I-HiO,..j~..,:::"'O-15 v
+20 V o-......._~,...,,~_+6.0 V
-20 Vo-......._~~~::"'O-6 V
-15V
r---;-------------------------------------+-----~.4Do------~
{45} MC14572
O.5/1of
FIGURE 12-2 -
P-CHANNEL POWER MOSFET NON-DESTRUCT FBSOA TESTER
strate resistance or increasing the channel length. This
negative resistance effect on SOA is illustrated in Figure
12-5. The intent is to compare slopes and not to compare
power handling capabilities of equivalent die sizes
(43,44,45).
Testing indicates that the Motorola Power MOSFETs
are not influenced by the negative resistance effect even
though they utilize very short channels to decrease onresistance. This is because of the additional P + plug that
is diffused beneath the source contact. When the device
goes into avalanche breakdown, as illustrated in Figure
12-6b, the preferred avalanche current path is from N
substrate through the P + plug and into the source. This
keeps the forward voltage drop of the source junction low,
or below turn on. This avalanche current is quite possibly
the current surge that the FBSOA tester detects when the
fixture activates the crowbar.
At still higher power levels current may flow, as in Figure
12-6c, increasing the voltage in the P region. The forward
voltage drop across the source junction may rise to above
turn-on, establishing the negative resistance phenomena.
This produces a positive feedback mechanism because
the source is now injecting electrons into the substrate
and thus intensifying the avalanching, effectively turning
on the parasitic transistor. Such an avalanche injection
would most likely destroy the device.
25°C and the measured curve was derived at an elevated
case temperature. Nevertheless, to ensure reliability, the
user must operate the power MOSFET within the specified
thermally limited curve.
Results of Testing One Part Along the Entire Curve
Many of the N-channel curves turned out to be very
linear when plotted on log-log paper (Figures 12-3, 12-4).
Within the same product line, the slope was very similar
from device to device and always steeper than the - 1.0
slope of the constant power dissipation curve. The plots
from product line to product line also tended to be tighlly
clustered, with slopes varying from about -1.2 to -1.5
over the eight different lines tested.
Some have reported a steepening of the SOA curve at
higher voltage and that this is due to a negative resistance
phenomena. This occurs when avalanche breakdown
takes place in the drain junction which increases 10. Because of the finite resistance of the substrate, the increase
in ID causes an increase in the potential in the substrate.
If 10 and the substrate resistance are large enough, the
source junction can become forward biased, which would
intensify the avalanche multiplication. N-channel devices
with short channels are susceptible to this phenomena,
but the problem can be alleviated by decreasing the sub-
MOTOROLA TMOS POWER MOSFET DATA
1-12-3
r---0ne and two
r---second Pulse
S.O ,~C>120·C'\.
.....
100 ms Pulse
.....
VI
Q.
E
"
2.0
S
Rated DC FBSOA
TC = 2S'C
rn
.9 1.0
\
"",r\'
.....
",
1\
~msrse
~,
i
\. \.m
\.
~
"
u
c:
"i!!
-',,
O.S I
1.~7
,
0
0.2
0.1
10
20
100
Drain Source Voltage, VDS (Voltsl
FIGURE 12-3 -
200
DC FBSOA OF MTM5N20
The questions "Why does the empirical FBSOA slope
deviate from the - 1.0 slope of constant power?" and
"What is the significance of the slope on the SOA curves?"
still remain. Since thermal resistance of bipolars de10
'. ,
S.O
'\.
,
'\.
\
,.....
"
VI
Q.
2.0
S
rn
.9
~
1.0
Rated DC FBSOA
TC
2S'C
=
,
TC> 120'C
One Second Pulse
I~
,
-
r\.
.....
\
1\
k?=
1.3
"I"
[',
\
\
\~[\.
'\.
.~
O.S
Bipolar Transistor
.. ~'I-'
'. \. ,
"c:
u
0
",
/
E
i
r\
creases with increasing current at a constant power level,
it was thought that the same may be true for power MOSFETs and that this could steepen the SOA slope (46). If
RruC increases with voltage (decreasing current), the device would not be able to dissipate as much power at the
high voltage, low current end of the curve .
To investigate this premise, many thermal resistance
measurements were taken on the OUTs, all at a constant
power level, but varying 10 and VOS (VOS1 101 = VOS2
102, etc.). A thermal resistance fixture that used a switching technique to measure the voltage drop across the
parasitic drain-to-source diode was used initially. The inherent measurement error in this method tended to suppress any trends in the variation of RruC with 10.
A second method that measures the junction temperature of a decapped device with an infrared microradiometer proved to be more accurate. The instrument read
out an average temperature of about 10.0% of the die
area that was located in the center or the hottest part of
the chip. Again, 10 and VOS were varied while Po was
held constant. As shown in Figure 12-7, ROJC does decrease with increasing 10 at a constant PO, like bipolars,
but the 10.0% change in ROJC is not enough to account
for the approximate 30.0% change in power handling capabilities (m = 1.4). Although RruC varies and does steepen the FBSOA slope, it has only a partial effect under
these test conditions. These results must be qualified because the equipment did not allow the measurement of
RruC at a power level near the FBSOA limits where the
change in ROJC could be more or less significant.
The failure mechanism and thus the slope of the curves
obtained from the FBSOA test fixture, is a function of
junction temperature, VOS, 10 and a variable thermal resistance. Because the junction temperature rose so high,
the device could be going into avalanche breakdown
which would be a strong function of VOS, as the curves
indicate. This temper~ture at failure is above TJ(max} ratings and demonstrates why users must not exceed published SOA curves.
/p..:
",
I
N-Channel
MOSFET
1\
Line of Constant
/power Dissipation
.....
'\.
\,\. I"
\\
0.2
k ~ "~
WithlWithout
Negative Resistance
Effect
,
0.1
10
so
100
20
Drain-Source Voltage, VDS (Volts)
FIGURE 12-4 -
200
i'
Log of Drain Voltage (Volts)
DC FBSOA TEST ON MTP7N20
FIGURE 12-5 -
COMPARISON OF TYPICAL FBSOA SLOPES
MOTOROLA TMOS POWER MOSFET OATA
1-12-4
N
Drain
N
~~
FIGURE 12-6a -
TYPICAL CURRENT FLOW IN TMOS
POWER MOSFET
FIGURE 12-6b -
N
FIGURE 12-6c -
..
CURRENT FLOW DURING AVALANC4
Drain
CURRENT FLOW DURING NEGATIVE RESISTANCE BREAKDOWN
Since power MOSFETs or, for that matter, bipolar transistors, do change their thermal resistance as operating
conditions vary, this could warrant a change in the published SOA curves. The thermally limited portion of the
curve is presently based on one thermal resistance reading taken at a single operating condition. If this is a worst
case reading (taken at low current, high voltage), this
could significantly underrate the device at the highcurrent, low-voltage portion of the curve. Conversely, if
the reading is taken at the high-current end, this could
overrate the device at the low-current end. Further study
needs to be done to determine if the change in RruC is
significant enough to alter the way manufacturers derive
published SOA curves.
The significance of the slope greater than minus one,
as accurately derived from the non-destruct FBSOA
tester, is that a simple power limit of, say, 75 W may not
be appropriate because it could overrate a device under
certain conditions and underrate the same device at the
same power level but lower voltage and higher current.
Motorola establishes conservative derating of RruC to
ensure reliable operation under all bias conditions.
Switching Safe Operating Area
(SSOA)
(tum-off switching SOA) capability of the MOSFET due to
the injected current into the Crss capacitance inadvertently
biasing-on the MOSFET.
Many practical power loads are inductive which can
cause severe stress on the power switching device during
tum-off. Due to the nature of an inductive load line, the
switch, be it a power MOSFET or bipolar transistor, can
simultaneously experience a high current and high
voltage. Depending on whether the switch is unclamped
(Figure 12-9a) or protected with a clamp circuit (Figure
12-9b) will determine the two energy limitations during
0.900
"
~evice#l
~
0.850,
u
~
a:
2i
lii
1
0.800I
OJ
'i
One of the advantages of power MOSFETs over bipolars is its superior reverse bias safe operating area
(RBSOA) performance. Power MOSFET RBSOA curves
are generally "square" at ID(max) and V(BR)DSS, (Figure
12-8) indicating that performance is bounded only by maximum voltage and maximum pulsed current ratings. In
other words, MOSFETs are not generally RBSOA limited.
There are possible exceptions to this rule, however. As
noted in the dv/dt section outlined earlier in Chapter 4,
rapid changes in drain-source voltages can limit the RBSOA
~ r----.
(ij
E
"
~
0.750
I
0.700
0.0
~ r--
----.
-., ~ce#2
a:
TURN-OFF SWITCHING SOA OF POWER
MOSFETS
~
2.0
1.0
Drain Current, 10 (Amps)
~
.........,
3.0
FIGURE 12-7'1- THERMAL RESISTANCE OF MTM12N10 versuS
DRAIN CURRENT AT PD = 50 W
MOTOROLA TMOS POWER MOSFET DATA
1-12-5
•
20
18
ie
:IE
~ 12
I
B 8.0
z
MTP5N20
:
CI
9 4.0
TJ" 150°C
o
o
40
80
120
160
200
Vos. ORA1N·TO·SOURCE VOLTAGE (VOLTS)
FIGURE 12-8 - MAXIMUM RATED SWITCHING
SAFE OP£RAl1NG AREA
inductive turn-off: Second Breakdown Energy (Es/b) and
RBSOA.
t
Second Breakdown Energy (Es/bl
Power transistors were originally characterized with an
unclamped inductive load (Figure 12-9a). The Device Under Test (OUT), typically a low voltage, extremely rugged
tranSistor, is turned on by applying a positive pulse to its
base through a resistive network terminated in a reverse
bias voltage VBB2. Collector current then ramps up at a
FIGURE 12-98 - UNCLAMPED,
Es/b
rate alctated by the time-constant of the relatively large
Inductance in the collector circuit. When the OUT turns
off, the energy stored in the inductor (E= 1/2L1CM2) has
to be dissipated in the transistor since there is no external
circuit, or clamp, to "catch" this energy as the current
ramps down. Also, immediately at tum-off, the collectoremitter voltage flies back up due to the "inductive kick"
(v = L di/dt). If the stored energy is great enough and the
transistor turn-off time fast enough, this voltage will fly
back to the breakdown voltage of the device (V(BR)CEX),
causing the transistor to avalanche. The transistor thus
has to dissipate the energy due to this unclamped operation by sustaining its breakdown voltage until the collector current falls to zero and the inductor discharges. The
maximum energy that the-device can sustain, defined as
Second Breakdown Energ~(Es/b), is determined by increasing the collector current until the device fails. Usually
this current is below the nominal operating current of the
device since the transistor has to absorb the relatively
high inductor energy and generally cannot sustain its maximum specified current. Theory and practice have shown
that most low-voltage transistors have decreasing Es/b
capability with increasing reverse-bias voltage due to current crowding.
The unclamped inductive loads stress the power
MOSFET in a similar manner. Now, the falling drain current will cause the flyback voltage to avalanche the drainsource of the MOSFET (VCBR)DSS).
The problem with this Es/b rating is that the derived
energy is only related to that particular inductance and is
highly dependent on its Q (quality factor, i.e., series re-
voo
FIGURE 12-9b - CLAMPED,
RBSOA
Vcc
L<1.0 mH
L>1.0 mH
n,G~(Onlq
-VBB2
VI~
V
vcc
,
--I VCE(satl'
I
ICM
I
I
(Vcd
VGS(off)
Clamp
VOO
:
I
~I----I
I
C,
I
I
o
o
IFM
IF:
OUT"
-
VD1-(BRICEX
vCE
VClamp
1..- - - - - - -
,
,
I
I
IJL~---I
II
,
o
FIGURE 12-9c - TURN-OFF TIMES EXPANDED
"Waveforms shown for MOSFET OUT.
Bipolar Terms in Parentheses.
FIGURE 12-9 - INDUCTIVE LOAD SWITCHING
MOTOROLA TMOS POWER MOSFET DATA
1-12-6
sistance). Additionally, the inductance specified to achieve
Es/b is generally quite large, 10 mH or greater, and does
not represent the real world inductance seen in Switchmode applications. Finally, and most important, most applications use some form of clamping to prevent drainvoltage breakdowns. For this reason, most high voltage
switching transistors are specified with a clamped inductive load.
RBSOA
A more precise and definitive inductive turn-off rating
is the clamped inductive turn-off rating labeled RBSOA.
In the simplified test circuit of Figure 12-9b, the OUT is
subjected to a real world clamped condition. The inductance need be only large enough to ensure that the flyback
time is greater than the drain current fall time, generally
resulting in inductances from 100 lotH to 1.0 mHo These
values also more accurately represent the leakage inductances encountered in switching applications.
To subject the device to the greatest stress during turnoff, the inductance should be of high Q to ensure that the
peak drain current, 10M, and flyback voltage, VOSM, are
simultaneously presented to the OUT, Figure 12-9c, resulting in a turn-off load line that approximates a rectangle.
Under these conditions, 10 will start to fall when VOS
forward biases the clamp diode, at which time the stored
inductor energy (current) will be transferred to the external
diode circuit.
To determine the RBSOA capability of the device, IDM
is set to a typical operating current and the clamp voltage
is increased until the transistor goes into second breakdown. Then other current levels are tested until the complete RBSOA curve is established. These second breakdown points relate to the energy dissipated in the device
during turn-off, specifically the crossover time Ie, (Figure
12-9c) and represents the energy encountered in inductive switching applications, (whereas, the lower 10M for
the unclamped Es/b mode does not). Reverse biasing in
this example is provided by a transistor clamp from the
gate of the N-Channel MOSFET to either a negative voltage or ground.
Switching Safe Operating Area (SSOA)
The term Switching Safe Operating Area is the generalized SOA limitation during turn-on and turn-off of the
power MOSFET. Turn-off switching SOA is equivalent to
RBSOA for bipolar devices and will henceforth be used
to describe this characteristic.
The straightforward method of determining the turn-off
switching SOA is through destructively testing the power
MOSFET in the clamped inductive turn-off circuit. This is
accomplished by setting the drain current to a specified
value by either adjusting the applied input pulse width
(tpW) or the drain supply voltage VOO since 10 '"
voolt pw. Then the clamp supply voltage is gradually
increased until one of two conditions occurs. If the specified 10 is less than the 10M rating, the clamp voltage can
be increased until the device avalanches and begins dissipating the inductor's energy. Since the MOSFET is operating in an Es/b mode at this point, failures may occur.
At drain currents greater than 10M, the device is operating outside its current ratings and the MOSFET may
fail at clamp voltages less than V(BR)OSS. In short, the
MOSFET's SSOA curves guarantee that the locus of failures is outside the 10M - V(BR)OSS boundaries. The
SSOA curve shown in Figure 12-8 is applicable for both
turn-on and turn-off of devices with switching times less
than one microsecond.
Normally a destructive fixture is used to ensure that the
fail pOints lie outside the turn-off SOA boundaries. This
requires testing of many devices and device trends are
difficult to determine. The use of a non-destructive fixture
greatly simplifies establishing the SSOA ratings since usually only one OUT can be used to generate a complete
turn-off switching SOA curve.
N-Channel Non-Destruct Turn-Off Switching SOA
Test Fixture
In order to save the OUT from the normally destructive
second breakdown energy, the stored inductive energy
must be quickly diverted from the transistor to an external
crowbar circuit. A test fixture, based on the work done at
the United States National Bureau of Standards,31 was
designed to have the capability of crowbarring as much
as 50 A and blocking as much as 1000 V. The 10 A
crowbarred propagation delay was about 70 ns and the
current rise time was about 40 ns. Triggering of the crowbar was accomplished by detecting the fast rate of change
of the collapsing drain-source voltage once the device
went into second breakdown. Using this test fixture, a
complete SOA curve can often be formed using only one
OUT; consequently, the OUT must sustain as many as 30
or 40 crowbars (second breakdowns) to establish the
curve. Not all devices will survive so many crowbars without degradation or failure, but a large percentage do, allowing a relatively simple and non-ambiguous curve to be
generated. Degradation is measured by a relatively large
change in drain leakage current, lOSS, after testing. For
this magnitude of leakage current change, subsequent
retesting will usually show a decrease in device turn-off
SOA capability.
The main elements of the non-destruct SOA test fixture
are illustrated in the block diagram of Figure 12-10. Of
these blocks the most important are the Drive Circuit consisting of the VGS(on) and VGS(off) Transistor Switches,
the Detector/Crowbar and a Pulse Generator capable of
being inhibited when crowbarring occurs. Of secondary
importance are the VOO Switch, and a Greater than 10%
Duty Cycle Lockout circuit. Also required is an externally
connected inductor, typically about 200 lotH.
Referring to Figure 12-10, the circuit operates as follows: An input pulse, Yin, is applied to the input of the
Drive Circuit controlling the three respective switches,
VGS(on), VGS(off), and VOO· The VGS(on) switch supplies the positive turn-on gate voltage and concurrent with
its turn-off, the VGS(off) switch is turned on. The drain
supply is also turned on (VOO switch) when positive gate
voltage is applied and, to ensure proper system operation,
will remain on for several microseconds (due to drive transistor storage time) after removal of the input pulse. During
this on-time, the collector current ramps-up and, upon
MOTOROLA TMOS POWER MOSFET DATA
1-12-7
•
VClamp
OUT
Oifferentiator
FIGURE 12-10 - BLOCK DIAGRAM OF THE N-CHANNEL NON-DESTRUCT
TURN-OFF SWITCHING SOA TEST FIXTURE
values chosen, is about 10 /LB. Also, due to the trailing
edge coincidence of the two pulses (plus approximately
equal propagation delays through the two respective
switches), the transition time between VGS(on) and
VGS(off) can be relatively fast for some OUTs and operating conditions, approaching less than 200 ns.
The drain switch is used as a safety device, removing
current from the inductor if the OUT were to fail short.
This circuit utilizes two cascaded Baker-clamped monolithic Oarlingtons (NPN Q6 and PNP Q7) to reach the 50
A capability of the fixture. The Baker-clamp diodes (03,
04 and 05, 06) minimize the storage time of this switch
after the OUT is turned off.
Once the OUT is turned off, the inductor-stored energy
is dissipated through the two clamp diodes (07 and 08
for high-voltage capability), the clamp supply and filter
network, and Q7 clamp diode 09. Diodes 010 and 011
in the drain circuit of the OUT are used to prevent reverse
drain currents from flowing and also to ensure that the
crowbar saturation voltage is lower than the parasitic transistor second breakdown voltage, thus diverting the drain
current.
Drain current can be monitored by the current loop as
shown. Additionally, the current-sense resistor, R2, can
be used to monitor 10, but care must be taken in the layout
to minimize ground loops which can distort this current
replica. As in any high-speed, high-current switch, good
RF techniques should be used in the layout.
tum-off, the drain voltage flies back. When the flyback
voltage reaches the clamp voltage, the inductor current
is transferred to the clamp circuit. The drain voltage will
then fall at a relatively slow rate, typically a couple of
hundred nanoseconds, as the energy stored in the inductor is completely discharged.
If, however, excessive energy is applied to the OUT
during this switching time, the FET can go into second
breakdown. Then the drain voltage falls very rapidly, possibly in less than 10 ns. When this occurs, the low R-C
time-constant Oifferentiator detects this fast falling waveform - discriminating against the normal slow falling waveform - and produces a negative-going pulse which ultimately triggers the crowbar. The crowbar fires and the
current in the OUT is quickly diverted to the crowbar,
removing the tum-off energy stress from the transistor.
The Pulse Generator is also disabled, preventing any successive pulses from being reapplied until the system is
reset.
Drive Circuit
The drive circuit for the SOA test fixture is shown in
Figure 12-11 and consists of the three aforementioned
switches. A Darlington transistor, Q1, is used to buffer the
CMOS-derived input pulse of 15 V from the drive circuit.
Positive gate voltage is generated by turning on the
NPN tranSistor, Q2, with the positive going· input pulse.
This stage supplies drive to the PNP Baker-clampconfigured tranSistor, Q3, whose output feeds the gate of
the OUT, turning it on.
Reverse bias is derived by differentiating the input pulse
with the R1C1 network. The generated negative-going
pulse, which is coincident with the trailing edge of the
input pulse, then turns on PNP tranSistor, Q4, and the
follOWing NPN tranSistor, Q5.
This off-bias voltage pulse is set by R1C1 and, for the
Detector/Crowbar Circuit
As previously mentioned, an RC differentiator is used
to discriminate between the normal VOS fall time and
second breakdown fall time; the components used are a
1.0 kV capacitor, C2, fixed resistor R3, and Sensitivity
Control R4.
Originally, the output pulse from this network fired a 25 A
MOTOROLA TMOS POWER MOSFET DATA
1-12-8
SCR as a crowbar, but the turn-on time of about 600 ns
proved to be too long to save the OUT. What is required
is a fast latching crowbar. This is now achieved by using
a common-base-connected NPN transistor, 010, as a
level detector-pulse amplifier, triggering a fast, discrete
monoslable multivibrator (MV) consisting of PNP transistors 011 and 012. This 25 !J-S MV, which allows adequate
time for the inductor stored energy to be dissipated, then
drives the direct-coupled NPN transistor, 013, and following PNP transistor, 014, to a power level capable of turning on the crowbar. Diode 012 is used to block any noise
pulses on the VDD line from false triggering the monostable MV.
The crowbar consists of four parallel MJ10011 monolithic Darlington transistors (015-018) selected for VCEO
greater than 1000 V. This transistor, designed for horizontal deflection circuits, offers the best blocking vOltageswitching speed tradeoff of the several different devices
tested. By using fast, wide-band transistors throughout,
propagation delay and rise time of 70 ns and 40 ns, respectively, were measured at an IC of 10 A.
Diode 013 and resistor RS prevent possible high dv/dt
+1SV
+15V
10k
Rep RIte Cont
0.001 p,F
Control Circuit
ResetSW
53
OrarnSwitch
04
(2)
00
LED Indicator,
PulaeJnhlblt
MJE3302
lN4433
~l.ED
II,
01.
D3
i
2N6060
0.1
.F
10k
-==-1.01t
100 k
4rok
>10% Duty Cycle
Loclcout
,~2
12 pF
',OkV
R3
Uk
Q15-o18
R4
r-:,-:--t----,-----'
Senstthrity
Controf
100
FIGURE 12-11 -
N-CHANNEL POWER MOSFET NON-DESTRUCT TURN-OFF SWITCHING SOA TESTER 1000 V, 50 A
MOTORGLA TMOS POWER MOSFET DATA
1-12-9
•
flyback voltages from falsely turning on the crowbar.
The resistor-diode networks (R6-9, 014-21) in the respective Darlington emitter circuits serve both as a ballasting-voltage clipping circuit and a crowbar indication
source for the second breakdown LED indicator circuit.
Pulse Generator
The timing functions for the Non-Destruct Turn-off SOA
Test Fixture are generated by a quad, 2-input NOR gate,
MC14001. These gates are configured as an astable MV
(gates A 1 and A2) clocking a monostable MV (gates A3
and A4) for pUlse-width generation. By setting the RepRate Control and the Pulse-Width Control, periods of from
90 iJS to 1.4 ms and pulse-widths of 4.0 iJS to 180 iJS are
achievable.
The Control Circuit produces free running pulses whose
duty cycle should be maintained at less than 10% (limited
by the driver circuit resistor power ratings). One-shot operation can also be generated by simply setting switch S2
to the one shot position and depressing the pushbutton
start switch S1, thus providing a trigger to the Pulse-Width
Mono MV.
Complete N-Channel Non-Destruct SOA System
Included in Figure 11-11 , the complete N-channel NonDestruct Turn-off Switching Tester, are two other circuits
not previously described. They are:
V-.
1. The Greater Than 10% Duty Cycle Lockout Circuit.
•
breakdown voltage of the switch. Various types of suppressors or "snubber" circuits such as Zeners, MOVs, RC
networks and clamp or "free-wheeling" diodes are generally used. The energy stored in the inductor is diverted
from the transistor at turn-off and is harmlessly dissipated
in the snubber, thus protecting the transistor switch.
To protect single power MOSFET switches, the snubber
can be placed across either the inductor or the MOSFET.
A Zener diode or RC snubber circuit can protect the drainsource of the power MOSFET but a simple clamp diode
across these terminals will not, as it will only come into
operation if its reverse blocking voltage is exceeded. However, in the multitransistor configurations commonly used
for switching regulators, inverters and motor controllers,
clamp diodes across the semiconductor switches are frequently used (Figure 12-12). The diodes do not protect
their respective FETs but rather the complementary FET.
As an example, in the totem-pole configuration of Figure
12-12c, diode 02 protects 01 and 01 protects 02.
To illustrate this, assume 02 is initially conducting,
causing load current to flow up through the inductor from
ground. When 02 turns off, the inductive current will continue but now through 01, through the power supply V +
and return to the ground side of the inductor. Consequently, the fly-back voltage will be clamped to V+ (from
V -), resulting in an amplitude of 2.0 V + when V + equals
2. The LED Indicator/Pulse Inhibit Circuit.
The 1'0% Duty Cycle circuit integrates the input pulse
train with an RC network in the base circuit of the smallsignal PNP Darlington MPSA65 (08). The resultant dc
base voltage is compared with the emitter reference voltage derived from a 1N914 diode (020). At duty cycles
greater than about 15-20%, the Darlington will turn-on,
lighting a LED indicator and turning on the NPN 2N3904
(09) transistor clamp across the input of the MPSU45
emitter follower (01). This effectively limits the duty cycle
. and the power diSSipated in the drive circuit.
The LED Indicator/Pulse Inhibit circuit is enabled when
the crowbar fires. The control signal is derived from the
emitters of the Darlington crowbars and fed to the gate of
the second breakdown SCR (019), turning it on. Placed
in the anode circuit of this SCR are the series-connected
second breakdown LED, reset switch (S3) and base biasing resistors for the 2N3906 pulse inhibit transistor (020).
Thus, when the SCR fires, the LED will turn on, indicating
second breakdown. The inhibit transistor will also turn on,
placing the input to astable MV (A1) high, thereby disabling the pulse train. The system is enabled by opening
(depressing) the normally closed pushbutton. reset switch,
thus unlatching the SCA.
Characterizing Drain-To-Source
Diodes of Power MOSFETs For
Switch mode Applications
When turning off inductive loads with a semiconductor
switch, some means must be used to suppress, limit or
clamp the resulting "inductive kick" from exceeding the
If the output power devices are power MOSFETs with
D-S diodes, the question arises as to whether these
diodes are capable of adequately clamping the turn-off
inductive load current. In other words, do the diodes switch
fast enough and can they take the commutated load
current?
The following discussion characterizes the D-S diode
of a number of power MOSFETs so that the circuit designer can make the performance/cost comparisons between using these internal diodes or discrete outboard
ones.
Switching Characteristics
The important switching characteristics of clamp diodes
in switchmode applications are reverse recovery time, t rr ,
and turn-on time, Ion. Diodes with long trr times can cause
excessive turn-on stress on the FET they should be protecting as both the diode and the FET will be conducting
during this time interval. The result will be a feed through
drain current spike which could exceed the forward bias
SOA of the FET. If the diode has relatively slow Ion times
or high overshoot voltage - modulation voltage
VFM(DYN) - then, in a similar manner, the FET might
not adequately be protected during inductive turn-off.
In the past, most semiconductor manufacturers would
characterize and specify (if they did it at all) the internal
diodes for switching, using the JEDEC suggested circuits
of Figure 12-13a and 12-13b. There are several problems
associated with these circuits; for one, they were originally
developed for sine-wave rectifier applications. As such,
the trr test circuit would produce a half sine-wave of controllable current amplitude, IFM, and di/dt of the current
fall time. However, since the current waveform was derived from a capaCitor dump, tuned circuit, the resulting
MOTOROLA TMOS POWER MOSF.ET DATA
1-12-10
Ql
J
J
01
Q2
FIGURE 12-128 -
FIGURE 12-12b -
COMMON SOURCE
COMMON DRAIN [).S
FIGURE 12-12c -
02
TOTEM-POLE
Complementary Push-Pull
FIGURE 12-12d -1/2 BRIOGE
FIGURE 12-12 -
FIGURE 12-12e -
1:1
di/dt Adjust
03
C2 +
01
Second, since trr is dependent on IFM and di/dt, what
should these variables be set to? IFM is obvious: it should
be the diverted drain current, but di/dt could be anything,
be it 25 AI p,S or 100 AI p,S, etc. In reality, this diode current
turn-off time is controlled by the complementary FET turnon time.
Ll
Rl
120V·~11
60Hz
FIGURE 12-121- TRANSFORMER PUSH-PULL
MULTIPLE POWER FET DRIVE CONFIGURATIONS USING D-S DIODES
current duration tp was dictated by IFM and dildt. Under
some high di/dt conditions, tp can become relatively short
compared to the trr of the device under test (OUT) and
consequently the diode is not fully turned on, thus producing inaccurate trr measurements. To ensure adequate
OUT turn-on, tp should exceed five times t rr .
'
Tl' T2
H BRIDGE
Cl + I(PK) Adjust
R2 - 02
TL
FIGURE 12-138 -
OUT
REVERSE RECOVERY TEST CIRCUIT AND WAVEFORM
Switch
Oscilloscope
Channel B
O.IIFM
ton
Time
OUT
Common
OSCilloscope
Channel A
Inverted
FIGURE 12-13b FIGURE 12-13 -
Time
DIODE TURN-ON TEST CIRCUIT AND WAVEFORMS
JEDEC SUGGESTED DIODE SWITCHING TEST CIRCUITS
MOTOROLA TMOS POWER MOSFET DATA
1-12-11
•
"J9P
2 V+
v+
V+
~--JL
V+--ill:
o
2 V+
J9
J9
v-
v-
vFIGURE 12-14aTOTEM-POLE
FIGURE 12-14b COMPLEMENTARY
FIGURE 12-14 -
•
--u-
V+
FIGURE 12-14c FIGURE 12-1411SIMPLIFIED CLAMP CIRCUIT LEVEL TRANSLATED
FIGURE 12-14eTEST CIRCUIT
EVOLUTION OF INDUCTIVE CLAMP TEST CIRCUIT
The problem with the Ion test circuit was the difficulty
in defining and controlling the rise time of the current pulse
applied to the OUT. Since this current pulse affects the
measured VFM(OYM) and ton of the OUT, its shape
should be related to the real world conditions.
This is what t/"tfl proposed test circuit does. Its configuration is derived from a typical two transistor Switchmode
application, be it a totem-pole for characterizing N-channel
O-S diodes or a complementary common source for characterizing P-channel O-S diodes (Figure 12-14). These
configurations reduce to the simple, single-ended inductive clamp cirCuit (Figure 12-14e) whereby the clamp
diode would be the O-S diode of either the N-channel FET
(totem-pole) or the complementary P-channel FET.
The reverse recovery time is of greatest significance
for continuous load currents common in switching inductive loads. Figure 12-15a describes the idealized current
waveforms when a continuous inductive load current IL
is com mutated between the FET (10) and clamp diode
FIGURE 12-158 -
o
IDEALIZED CURRENT WAVEFORMS
(IF). Figure 12-15b shows the time expansion of both the
leading and trailing edges of 10 and IF. Note that the drain
current fall time tnc controls the diode current rise time
tflO (or ton) and in a similar manner, the dlO/dt (or triO)
of the drain current turn-on time dictates the dlF/dt of the
diode current turn-off time. Thus, the faster the FET
switches, the greater is the di/dt applied to the diode. The
diode di/dt then dictates the magnitude of the reverse
recovery time trr and current IRM(REC). Since the current
through the inductor is equal to 10 plus IF the peak drain
current 10M at turn-on will consequently have the magnitude of 10M impressed on it. This is illustrated in Figure
12-16 whereby the switching times of 10 and IF are the
mirror image of each other; the sum of the two waveforms
would yield the inductor current, whose ripple magnitude
is dependent on the switching frequency and load
inductance.
An example of discontinuous and continuous load current waveforms are shown in Figures 12-17a and 12-17b
respectively. Note that for the discontinuous case, where
the inductor current IL is allowed to completely discharge,
the di/dt of IF is extremely low, thus producing no IRM or
t rr . For the continuous cumlnt case, the resultant di/dt
produces significant IRM and t rr .
The size of the inductor used has little, if any, effect on
the trr measurements as shown in Figures 12-18a and
12-18b; Figure 12-18a shows the full cycle and time
expanded waveform of diode current for inductances of
Turn·On
I
D-S Diode
Turn-Off
FIGURE 12-15b -
I
~
2.5 AJdiv
WAVEFORMS TIME EXPANSION
FIGURE 12·15 - CONTINUOUS LOAD CURRENT
SWITCHING WAVEFORMS
FIGURE 12·16 - SWITCHING CURRENTS OF A
CLAMPED INDUCTIVE LOAD
MOTOROLA TMOS POWER MOSFET DATA
1-12-12
I
FIGURE 12-178 -
L = 100!£H
100 !£sldiv
= 2.0 A/div, t =
FIGURE 12-17b -
DISCONTINUOUS LOAD CURRENT
FIGURE 12-17 -
CONTINUOUS LOAD CURRENT
THE EFFECT OF SWITCHING INDUCTIVE LOAD CURRENT ON I" AND IRM(REC) OF D-S DIODE
100 ,..,H (air core) and Figure 12-18b for a 10 mH (iron
core) inductor. The major difference is the magnitude of
the ripple current, the larger inductor producing a more
constant current source.
Test Circuit
The test circuit used for generating the diode switching
characteristics, a translation of the "real world" circuit of
Figure 12-14e, is shown in Figure 12-19. It consists of a
CMOS, astable multivibrator (Gates G1 and G2) driving
two parallel connected Gates 3 and 4 as a buffer. Potentiometer R1 varies the duty cycle of the approximately 25
kHz output which therefore sets the magnitude of the OUT
current (along with VOO). The positive-going output from
the buffer is direct-coupled to turn on the NPN transistor
01 and the following Baker-clamped PNP transistor 02.
To produce an off-bias to the driver, which can shape
its turn-off time and consequently the diode turn-on time,
the negative going edge of the output pulse from the buffer
is used. Capacitor C1 and resistor R2 form a differentiating
circuit to produce the negative pulse for turning on PNP
transistor 03 and the following NPN transistor 04. This
transistor acts as the off-bias switch, applying to the driver
a negative voltage pulse (approximately V -) coincident
with the trailing edge of the input pulse and lasting as long
as the R2C1 time constant, about 5.0 ,..s for the component values shown.
Switching Test Results
TMOS O-S diodes are usually tested at the rated continuous drain current. The supply voltage VOO should be
greater than 10 V to ensure that the OUT driver is operating with typical transconductance. Since the OUT current is a function of duty cycle and/or VOO, reducing the
input pulse width will allow a greater VOO to be used, if
so required.
Although it is not always possible to test the OUT with
its real world supply voltage (i.e., high voltage devices
with higher VOOs than low voltage devices), the results
would be more indicative if it were poSSible, since 9fs and
switching speeds will vary somewhat with VOO.
10 = 2.0 A/div
L= l00pH
FIGURE 12-18a -l00!£H INDUCTOR
10 = 2.0 A/div
L = 10 mH
t = 5.0 ps/div
FIGURE 12-18 -
FIGURE 12-18b -10 mH INDUCTOR
t = 1.0 ps/div
THE EFFECTS OF LOAD INDUCTANCE ON D-S DIODE REVERSE RECOVERY CHARACTERISTICS
MOTOROLA TMOS POWER MOSFET OATA
1-12-13
VDD
100 p.H. 30A
(2)200 p.H. 15 A Inductors
in Parallel
J. W. MILLER: 07828
270 K
Rl: Duty Cycle
Control
f~25kHz
OUT
DRIVER
To Set D-S Diode Current IS.
Adjust Rl and/or VCC
-V", -5.0 V
NOTE: OUT is Shown as an N-Channel TMOS but can also be
a P-Channel when appropriately connected. OUT
Driver is the same device as OUT Diode (or Complement for P-Channel OUT Diode)
FIGURE 12-19 -
TMOS D-S DIODE SWITCHING TIME TESTER
Testing of several different FETs as a function of VDD
showed a second order variation in trr measurements. At
any rate, to ensure measurement repeatability, VDD, frequency, duty cycle and inductor specification should be
listed. For most of the TMOS FETs tested, the inductor
was either one 200 p.H, 15 A rated air core or two in
parallel (100 /tH, 30 A). Whatever the conditions, the OUT
driver and diode under test should be adequately heat
sunk to minimize excessive case temperature rise.
The switching characteristics of an MTM15N15 as
shown in Figure 12-20, and the complete switching results
for'the TMOS FETs tested are compiled in Table 1.
Also shown (Figure 12-21) for comparison, are switching photos of discrete rectifiers. Note that the fast recovery
rectifier, as expected, had the lowest trr and that the standard rectifier, the largest t rr . But of even more interest,
the TMOS D-S diode had the lowest trr of all diodes tested
(Table 1).
From this data, the circuit designer can now decide if
the switching characteristics of the diode are adequate
for his application.
•
Surge
MTM15N15
D-S Diode Current IS' (IF)
FIGURE 12-208 FULL CYCLE
IS = 2.0 A/div
t = 5.0 I's/div
FIGURE 12-20bD-S DIODE Irr
Characteri~tics
FIGURE 12-20cD-S DIODE Ion
An equally important consideration is whether the diode
can handle the commutated load current in which, under
continuous load current, high duty cycle conditions, the
energy can be quite high.
The TMOS D-S diode is the result of the parasitic NPN
transistor across the FET and as such, actually has more
die area available to conduct diode current than the FET
has for drain current. For data sheet purposes, the drainsource diode current, labeled IS, is made equal to the
drain current 10.
To verify these current ratings, the D-S diodes were
subjected to two different pulse width surge tests, a one
IS = 2.0 A/div
t = 60 ns/div
FIGURE 12-20 -
MOTOROLA TMOS POWER MOSFET DATA
1-12-14
SWITCHING CHARACTERISTICS OF A
TMOS D-S DIODE
TABLE 1 - Switching and Surge Current Characteristics of TMOS o-S Diodes
Switching
Surge Current
SpeclD
Cont
IFM
di/dt
IRM
trr
ton
10ppi
1.0.
1 Shot
(A)
(A)
(AIl's)
(A)
(1'1)
(1'1)
(A)
(A)
3001'"
Device
Type
(Chan)
MTM8Nl0
N
8.0
6.0
8.5
1.0
0.20
0.20
30
11
MTM15N06
N
15
10
9.0
1.0
0.24
0.29
80
24
MTM15N15
N
15
10
5.0
0.8
0.28
0.05
120
19
MTP1N60
N
1.0
1.0
10
0.3
2.0
0.03
25
6.0
MTP5N06
N
5.0
5.0
3.7
0.24
0.14
0.09
50
12
MTP25N06
N
25
25
10
1.0
0.20
1.0
140
35
second, one-shot pulse and a 300 p,S, 1.8% duty cycle
(60 Hz rep rate) pulse train. The one second test, which
approximates a dc test, was run with the OUT bolted to
a four inch square copper heat sink, initially water cooled
and then in free air. The OUT forward current was then
increased until the device was destroyed. The test results
on one product line for the water cooled versus free air
cooled were virtually identical so all subsequent tests were
done in free air. The results of these tests are shown in
the surge current sections of Table 1.
For power dissipation purposes and clamping efficiency
determination, the typical forward characteristics of the
diodes were also taken, as shown in Figure 12-22. These
VF-IF curves were derived from a curve tracer using a
300 /Ls current pulse at 60 PPS; the low duty cycle en-
Diode Current IF
sured low case temperature readings. For comparison
purposes, Figure 12-23 describes the forward characteristics of discrete diodes under the same test conditions.
Knowing the voltage drop and current, the diode dissipation can be calculated. For any combination of power
dissipation, the total diode and FET dissipations should
not exceed the rating of the devices. After determining
the switching characteristics and the power handling capability of the diodes, a cost/performance trade-off can be
made. If the switcher is in the development phase, it is
relatively simple to determine the effects of using the internal monolithic diode over a discrete, outboard diode,
I.e. measuring case temperature rise, current and voltage
waveforms, load lines to ensure safe SOA, device and
system efficiency, etc.
= 0.5 Aldiv. t =
1.0 /LS/div
"
FIGURE 12-218 -IN4001 STANDARD RECTIFIER
FIGURE 12-21b -IN4935 FAST RECOVERY RECTIFIER
FIGURE 12-21 - COMPARISON OF WITH DISCRETE RECTIFIERS
FOR REVERSE RECOVERY CHARACTERISTICS
MOTOROLA TMOS POWER MOSFET DATA
1-12-15
300 1" Pulse. 60 pp.
ie
100 MTP25N06~'<_ _ MTM15N06E
50 MTP15N15 /,/MTP5N06/,
:;
S
MTP8Nl0
~
a:
10
«
5.0
~
~
1?
_ 50
I
~
....
z
//
I
/1, 1/
,"I,
'II
0.5
"
30
w
a:
a:
::J
I
II
C-E DIODE
MJ10007
~
u
~ 10
TC=250C
300 ~s Pulse. 60 pps
~
a:
1?w
I. /
Ci 1.0
!lJ
I
,~,
,II /'
8
i
' ,//
~/i / ~~P1N60
'.
/
a
a:::
I
100
/
TC
5.0
Cl
o
1/1
i5 3.0
.!:f.
' I:
0.1 0'-":-"'---2'-.0-3-'.-0-4.'-0-5--'.-0---:-'6.0
= 25°C
MJ10007:
MR756:
lN1202A:
MR826:
lN3892:
lN4935:
lN4oo7:
lOA Darlington C-E Diode
6.0 A Rectifier
12 A Rectifier
5.0 A Fast Recovery Rectifier
12 A Fast Recovery Rectifier
1.0 A Fast Recovery Rectifier
1.0 A Rectifier
IIsD. D-S DIODE FORWARD ON-VOLTAGE (VOLTS)
5.0 6.0 7.0
VF. DIODE FORWARD VOLTAGE (VOLTS)
FIGURE 12-22 - FORWARD CHARACTERISTICS OF
POWER MOSFETs D-S DIODES
FIGURE 12-23 - FORWARD CHARACTERISTICS OF
DISCRETE RECTIFIERS
Thermal Measurements
Steady State Thermal Resistance Measurements
It is a well known fact that, for reliable operation of a semiconductor, junction temperature is of great concern. All
semiconductor die have a critical temperature which must
not be exceeded or failure will occur. Also, semiconductor
operating life can be either extended or shortened by its
operating temperature.
The usual semiconductor die is enclosed in some type
of package which prevents a direct temperature measurement Due to the inaccessibility of the die, an indirect
method must be used to determine the junction temperature. A common method is to use a temperature sensitive
electrical parameter. The parameter used can vary, depending upon the type of semiconductor measured.
A basic block diagram for steady-state thermal resistance measurements for bipolar transistors is shown in
Figure 12-24. The forward biased base-emitter-junction is
used as the temperature sensitive parameter. This junction is calibrated at an elevated temperature in the forward
direction, with a low calibration current (1M), and should
be in the linear region above the diode knee. Also, 1M
should not contribute significantly to junction temperature
nor turn-on the transistor; typical values are 2.0 to 10 mA.
The calibration procedure can be performed in a temperature chamber, with the temperature set for a normal
operating temperature value for the semiconductor being
measured. A typical temperature for a silicon die is around
1OO°C_ The base-emitter forward voltage is measured and
recorded at 1M and at the calibration temperature.
After calibration, a power switching fixture (Figure
12-24) is used to alternately apply and interrupt the power
to the test device. The transistor is operated in the active
region and power dissipation can be adjusted by varying
IE and/or VCE until the junction is at the calibration tem-
perature. This condition is known by monitoring the baseemitter voltage during the time when 1M only is flowing,
with either an oscilloscope or a sample-and-hold circuit
When VBE is equal to the value obtained in the calibration
procedure, the junction temperature is known. The case
temperature is noted at this time, as well as IE and VCE.
¥
VEE
0-----------
VMM-IvBE with_
-=
Switching
Transient
-=
'M only
VBE_
with
Power
Dissipation
ms
FIGURE 12-24 - BASIC BLOCK DIAGRAM OF STEADY STATE
THERMAL RESISTANCE TEST CIRCUIT FOR BIPOLAR
TRANSISTORS
The heating period is long, so the temperature of the
transistor case is stabilized and the interval of power interruption short, usually 300 !LS, so junction cooling will be
minimal. .
The steady state thermal resistance can be easily calculated from the information obtained. in the calibration
and power dissipation procedures. The simple formula is
derived from the basic thermal resistance model (Figure
12-25) showing the thermal to electrical analogy for a
semiconductor.
MOTOROLA TMOS POWER MOSFET DATA
1-12-16
Steady state thermal resistance, junction-to-case, is as
follows:
ROJC -
_
T,,-J_-_TC><.
VCE x IE
AT
orPD
Temperatures
TJ. Junction -~------,
Rruc
Po
Roes
Ts.Sink_
technique is also applicable to TMOS power MOSFETs.
When measuring the thermal resistance of power
MOSFETs, the gate-source threshold voltage or the drainsource on-resistance rDS(on) can be used in addition to
the on-voltages of the drain-source diode. Knowing the
temperature characteristics of these parameters - by
measuring the voltage or resistance variations with temperature in an oven, as an example - the device temperature, when powered, can be determined and the thermal resistance can be calculated.
These temperature sensitive parameters (TSP) of a
power MOSFET with their approximate temperature coefficients are listed as follows:
Drain-Source Diode = -2.0 mVf'C
Gate-Source Threshold Voltage
ROJA
= -2.0 to
Drain-Source On-Resistance =
rDS(on) = 1.0 0
TA. Ambient _ _
For junction-to-case measurements, sufficient heat
sinking should be provided to prevent excessive junction
temperature. Measurement accuracy is improved with a
large temperature delta between the junction and case.
This delta can be achieved by using an efficient heat sink
permitting a power dissipation (IE VCE) of sufficient magnitude to reach the calibration temperature.
Using Temperature Sensitive Parameters for
Measuring Power MOSFETs Thermal Resistance
In order to determine the thermal resistance of any semiconductor device, an accurate and repeatable method of
measuring the device temperature is required. The linear
temperature dependence of the on-VOltage of a forward
biased semiconductor junction has proven to be a reliable
parameter and is consequently used for bipolar transistors
(emitter-base or collect-base junctions). rectifiers, zeners
and thyristors. Because of their intrinsic D-S diode, this
D-S Diode TSP
Generally, the most often used circuit for measuring
ROJC of power MOSFETs uses the D-S diode. When
electronic switches S1 and S2 are in position 1, the FET
is biased on and the heating power (VDSID) is applied to
the FET for a relatively long period. Then the switches
are thrown to position 2 for a short period of time (sense
time) so that the FET temperature will not change appreciably. Next, the FET is turned off and a constant current
1M (the same sense current at which the TSP was temperature calibrated) is applied to the forward biased D-S
diode. By measuring the forward voltage drop of the diode
and comparing it to the calibration curve, the FET junction
temperature can be ascertained. Knowing the input power
and the junction temperature, the thermal resistance can
be calculated. In practice, the input power, either voltage
or current, is varied until the D-S diode drop is equal to
a calibration pOint, thus simplifying the test procedure by
not having to generate a complete calibration curve.
¥DD
¥DD
FIGURE 12-26b - GATE-SOURCE
THRESHOLD VOLTAGE
FIGURE 12-268 - DRAIN-SOURCE
DIODE VOLTAGE
FIGURE 12-26 -
-6.0 mVf'C
mOrC when
How these TSP can be measured is described in the
simplified schematics of Figure 12-26, with Figure 12-26a
using the D-S diode, Figure 12-26b, the VGS(th) and Figure 12-26c, the rDS(on).
FIGURE 12-25 - BASIC THERMAL RESISTANCE MODEL
SHOWING THERMAL TO ELECTRICAL ANALOGY FOR
A SEMICONDUCTOR
¥DD
+ 7.0
FIGURE 12-26c - DRAIN-SOURCE
ON RESISTANCE
CIRCUIT CONFIGURATIONS FOR MEASURING TSP
MOTOROLA TMOS POWER MOSFET DATA
1-12-17
Gate-Source Threshold Voltage TSP
This thermal resistance test circuit is extremely useful
for measuring R8JC of GEMFETs since this device has
no parasitic diode. As in the O-S diode tester, heating
power is applied to the OUT when switch S1 is in position
1. Then, switch S 1 is briefly thrown to position 2, applying
the sense current to the FET (10 at VGS(th)) and the gatesource threshold voltage is measured. Input power (VOSIS) is varied to make VGS(th) equal to the elevated temperature, calibration reading resulting in a known junction
temperature and thus R8JC.
Drain-Source On-Resistance
This circuit is conceptually similar to the O-S diode
tester. However, now when the switch is in poSition 2
(Sense Time), a positive constant current 1M and + 15 V
gate bias are applied to the device, turning it orr. 1M should
be of a value to produce about 0.5 V VOS. The voltage
VOS measured (VM) is related to rOS(on) by:
rOS(on) = VM/IM
Thermal Test Fixtures
D-S Diode Thermal Fixture
R8.lC
The O-S diode Thermal Fixture, shown in Figure
12-27, is partially an implementation of the simplified circuit of Figure 12-26. It also contains circuitry for measuring
transient thermal resistance r(t) and the analogue circuits
for reading out the drain-source diode forward voltage and
input power (VOS and 10). Thermal resistance is measured when the Mode Selector Switch S1 is in position 1,
R8JC. System timing is line synchronized and is derived
from the Schmitt trigger (gates G1A and G1B) shaping
circuit clocking the 300 /LS Sense Time Monostable Multivibrator (gates G2A and G2B). Thus, the power MOSFET
OUT is turned on via the Orain Switch circuit (cascade
transistor Q1 and Q2) and unclamped gate transistor Q3
for 8.0 ms (full-wave rectified line rate minus 300 /Ls) and
off for the 300 /Ls sense time. Orain current is set and
readily controlled by 10 Control potentiometer R1 in the
gate-source, closed loop, regulator circuit (op-amp U5).
"""""
ModeSel
S1A
sw
2
r(1I
Delay Control
+ 15 'II
1N914
120 V
DelayMV
C1 130pF
C2 0.001".F
C3 0.01,u
C4 O.1j1.F
C5 1.0jJ.F
CI 12) 20#. 20 'II
MC14001
U,
22SecMV
FIGURE 12-27 - POWER MOSFET D-S DIODE THERMAL FIXTURE
MOTOROLA TMOS POWER MOSFET OATA
1-12-18
During the sense interval, OUT power is turned off (02
is off, 03 is on) and the sense current IS is applied to the
now forward biased O-S diode by means of turned on
transistors 04 and as. The resultant O-S diode voltage
can be observed by a scope or measured by the Sample
and Hold circuit consisting of series FET switch 06, buffer
amp U6, sample driver 07 and line synchronized, Delay
Monostable MV gates G2C and G20. The Delay Control
of this MV allows the sample pulse to be positioned some
time after the start of the Sense time so as to measure
the settled voltage of the O-S diode, ignoring the possible
thermal and/or electrical switching transients on the leading edge of the sense pulse. This delay time is typically
50 p,S to 150 p.S.
Using similar sample-and-hold circuitry, the applied
power (VOSI10 and 10/10) can be measured. This is accomplished by the respective FETs 08 and 09, sample
driver 010, buffer U3A and U3B and difference connected
op-amps U4A and U4B.
Transient Thermal Resistance r(t)
Transient thermal resistance, r(t), is measured when
switch S1 is in position 2. Now the system timing is derived
by the 22 second astable MV (gates G1 C and G 1D) which
tums the OUT on and off for about 11 seconds each.
During the off time, cooling cycle, the voltage of the O-S
diode can be measured at any selected period of time.
This is accomplished by selecting the various resistorcapaCitor timing components of the Delay MV, thus positioning the sample pulse accordingly. The six switchable
capacitors, by means of Selector Switch S2, will produce
the six time decades of control (100 p,S to 10 s) and the
three resistors (switch S3), the multipliers within the decade, e.g., 0.2, 0.5 and 1.0.
Gate Threshold Voltage VGS(th) Thermal Fixture
The Gate-Source Threshold Voltage (VGS(th)) Thermal
Fixture, Figure 12-28, was specifically designed for measuring the thermal resistance of GEMFETs as this device
does not have a O-S diode. Since it detects temperature
+15V
U2
(V,IMCI458
Voo
U2
(V,IMCI458
OUT
VGS(thl
U3
11f2IMC1458
SlH
lN914
15 k
+15V
160 k
Q2
R4
470 k
560
0.01 ~Fl
250 p.S max
Delay
MV
R2
10mA
Set
(211N914
Ul
MC14572
>-_"""~-~-,,,,--o+15 V
lN5352
15V.5.0W
100 ~F
20 V
-=
FIGURE 12-28 - POWER MOSFET VGS(th)
THERMAL FIXTURE
MOTOROLA TMOS POWER MOSFET DATA
1-12-19
1M
R6
induced variations in the gate-source threshold voltage,
it can also be used for power MOSFETs. Its line synchronization and current regulator loop around the gate
and source make it very similar to D-S Diode Thermal
Fixture. The major difference is the setting of the two
different drain currents (or source currents), the power
current, IS, and sense current 1M. This is accomplished
by switching two different reference voltages to the positive input of the loop regulator op-amp U3. As in any
regulator loop of this type, the voltage at the negative
input of the op-amp, as derived from the voltage drop
across the source sense resistor R1, will be driven by the
closed loop to a value equal to the reference input. Thus,
if a heating current, IS, of say 10 A is required, the reference voltage should be 3.0 V (10 A x 0.3 0). If a sense
current 1M ~f 10 mA is specified, VREF should be 3.0 mV.
Although most power MOSFETs are specified for a 1.0
mA drain current at VGS(th), the 10 mA level was chosen
for measurement simplicity; in reality, there is negligible
difference in the test results at either currents.
As in the D-S Diode Fixture, the system timing is line
synchronized by Schmitt Trigger U1 A and U1 B, whose
complementary outputs are used to clock the 370 p,s
sense MV (U1C and U1D), and the variable delay MV
(U1E and U1F) for the sample pulse. This type of line
synchronization offers several advantages: at high power
heating drain currents, it simplifies the oscilloscope viewing, particularly when the external power supplies are not
well regulated, and it is easily derived from one hex gate
CMOS IC MC14572.
During the 370 /L5 sense time, the output of U1D is
high; thus, PNP Darlington, Q1 is Off and the reference
voltage is determined solely by the voltage divider R2 (the
10 mA Set Control), R4 and R5. To set R2, switch S2 is
opened and the drain current is monitored for the required
10 mAo
When U1D goes low for the approximate 8.0 ms power
cycle, Q1 is turned on, placing R3, the IS control, into the
reference voltage circuit. Consequently, the reference
voltage will be switched from the 3.0 mV sense voltage
to the IS control voltage.
During the sense time the magnitude of the gate-source
voltage, can be monitored with a scope or read out with
the sample-and-hold circuit consisting of FET series
switch Q3, buffer amps U2A and U2B, sample driver Q2
and delay MV U1E and U1F. Power to the OUT is then
varied, either VDS or 10, to make VGS(th) equal to the
calibrated value; thus, TJ and PIN are known and ROJC
•
D
Cds
Cgs
5
FIGURE 12-29 -
DEVICE CAPACITANCES
For the Common Source configuration, the device capacitances are combined to reflect the capacitive reactances presented to the drive source and load. These composite capacitances are:
Crss - Reverse Transfer Capacitance
Ciss - Common Source Input Capacitance
Cos s - Common Source Output Capacitance
Crss is the capacitance between the drain and gate
terminals with the source ac-guarded. Ciss is the capacitance between the gate and source with the drain acshort-circuited to the source. Cos s is the capacitance between drain and source with the gate ac-short-circuited
to the source. Table 2 summarizes the relation between
the Common Source and device capacitances.
TABLE 2
COMMON SOURCE
Crss
Ciss
Coss
can be calculated (ROJC = (TJ - TC).
PIN
Measuring Power MOSFET
Capacitances
The internal capacitances of a power MOSFET are
viewed from the outside world as the three device capacitances, Cgs , Cgd and Cds (Figure 12-29).
I
DEVICE
Cgd
Cgd + Cgs
Cgd + Cds
Crss , measured between gate and drain of the MOSFET, consists primarily of a MOS capacitance between
the polysilicon gate and the accumulation section of the
MOSFET's drain region. The major component of C gs is
between the polysilicon gate and the source metallization.
An additional component of Cgs is a MOS capacitance
between the gate structure and the "back-gate" regions
(channel capacitance). Cds is the PN junction capacitance
between the drain and the "back-gate" regions. Cgd and
Cds (and, to a lesser extent, Cgs) are strongly voltage
dependent.
Modern capacitance meters (e.g. Boonton 74BD,
HP4275A) are "guarded" and have provisions for superimposing dc bias on the measurement loop to the component being tested.
Guarded meters are shielded and so configured that
the displacement current (1m) detector circuitry is above
ground (Figure 12-30). Any leakage current (or current
through a three-terminal composite capacitor) is bypassed around the detector, thus only current through the
capacitance under test is detected and measured. A more
thorough discussion of guard circuitry can be found in
(1-2).
MOTOROLA TMOS POWER MOSFET DATA
1-12-20
r---,
r---'
: r-..J
L_, I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
_.J
:
I
CAP. METER
I
:I L_,
r
DETECTOR
L---i
FIGURE 12-30 -
I
t
I
---I
"GUARDED" CAPACITANCE MEASUREMENT
A guarded arrangement is seen in Figure 12-31, the
test configuration for C rss . As shown, the measurement
loop encloses only Cgd. Any displacement current through
Cgs or Cds is bypassed around the measurement loop;
only Cgd displacement current enables the measurement
circuitry. Dc bias voltage, however, may be placed in the
"L" bus appearing between drain and source, and allowing measurement of C rss at various voltages.
To measure Ciss, the displacement current through C gs
must be included in the measurement loop. One easy way
to accomplish this would be to "hard-wire" the source to
the drain, however, such an arrangement would preclude
measurement at any drain-source voltage other than zero.
A better way is illustrated in Figure 12-32. In this arrangement the source is ac shorted to the drain by C1, thus
including Cgs in the measurement loop. RFC1 provides
a dc return from ground to the source, enabling measurement of Ciss versus VDS.
Measurement of Cos s is similarly straightforward. The
Simplest way to include the Cds displacement current in
the C rss measurement loop is to "hard-wire" the source
to the gate (Figure 12-33). Such an arrangement still
allows the desirable feature of measurement at various
drain-source voltages.
An inspection of the measurement configurations of Figures 12-31, 12-32 and 12-33 shows that they differ only
in termination of the device source terminal. Figure 12-34
embodies Figures 12-31, 12-32 and 12-33 in one test setup. A two-pole, three position rotary switch connects the
source terminal to the appropriate nodes for the three
common-source capacitance measurements. The 50 kO
resistor between gate and source insures proper termination of the MOSFET in case of capacitance meter failure. A pushbutton enables the drain-source bias voltages.
P-Channel devices may be measured simply by inverting
the connections of the biasing power supply.
--L-~~----~~~
B
S
+
S
VDS
FIGURE 12-31 -
+
Crss TEST CONFIGURATION
VDS
FIGURE 12-33 -
Coss TEST CONFIGURATION
--LB
I
CAP.
A METER
S
ML
EO
AO
S. P
--H--
D
- - L - --1--------0------,
0.1
JLF
CAP.
METER
Cl
1M
GUARD
- - H
Coss
•
--.I----4:>-....J
S
GUARD
50 kG
+
VDS
+
VDS
RGURE 12-32 -
Ciss TEST CONFIGURATION
FIGURE 12-34 -
COMMON SOURCE CAPACITANCE TEST SET-UP
MOTOROLA TMOS POWER MOSFET DATA
1-12-21
CHARACTERIZING POWER MOSFETs FOR
UNSPECIFIED PARAMETERS
Figure 12-35 shows a typical family of Common Source
Capacitance curves derived with use of the test set-up of
Figure 12-34.
For reasons detailed in Chapter 6, Figure 12-35 is not
a complete picture of the variation of Crss and Ciss. In
brief, the missing data are the changes that occur as the
device moves deep into the on-state. The circuit shown
in Figure 12-36 provides a means of measuring the additional capacitance variation, which is shown to the left of
zero in Figure 12-37.
Although many modern data sheets characterize power
MOSFETs specifically for operation in power conversion
equipment, it is not practical to guarantee operation for
every conceivable set of operating conditions. Therefore,
equipment design frequently requires the use of power
MOSFETs in conditions for which they are not specified.
To compensate for the unknowns, use of a relatively large
design sample is common practice. A relatively large sample gives a feeling of statistical security. All too often, the
sample comes from transistors purchased in a single
group, with predictably unfortunate results. A common
scenario goes something like this.
5000
-~THSNsJ
4000
TJ ~ 25'C
vGS ~OVf~lMHz._
~
;;; 3000
u
z
Design Scenario
;0;
u
11': 2000
<3
,,-
Ciss
1000
crss
~
coss
o
o
10
15
20
25
30
35
40
DRAlN·TO·SOURCE VOLTAGE IVOLTS)
FIGURE 12-35 - Clss, Crss AND Coss VARIATION OF THE
MTH6N60
B
I
A
S
--L--~-----------------------,
ML
CAP.' EO
METER A 0 r---,.------.
S.P
Cdg
GATE
50 kG
FIGURE 12-36 - CIRCUIT USED TO MEASURE Clss AND Crss
OF A POWER MOSFET WHEN IT IS IN OR ENTERING INTO
ITS ON-STATE
,
5000
The designer orders as many as 100 of each of the key
components to try in this equipment. He may simply verify
that the equipment performs satisfactorily, or he may attempt to do a worst case analysis based upon parametriC
variations. Either way, it is believed that the 100 pieces
constitute a statistically conservative sample.
With performance and worst case analysis indicating
satisfactory performance, the design is finalized. Preproduction begins with components from the initial 100
piece order. Except for routine debugging, all goes well.
Hard tooling is committed. Initially, or months, or even
years later, the equipment begins to fail as it comes off
the production line. Perhaps with less fortune, the eqUipment fails in the field. The reason, which is at first elusive,
boils down to the equipment requiring a combination of .
non-reproducible characteristics in one or more of the key \
components.
All too many people have been adversely affected by
just this kind of scenario. Yet, minimizing the risks associated with component selection is considerably easier
than might be expected. Guidelines for minimizing the
risks, with respect to power MOSFETs, are presented
here. In addition to general guidelines, a straightforward
method for determining safe operating safety margin is
highlighted. The discussion begins with statistical
concepts.
Semiconductor components have three statistical popul'ations which are relevant to the equipment designer.
They are:
1) Wafer lot
TJ ~ 25'C
f ~ 1 MHz f - -
,........,
4000 E, 3000
i~
2000
~
VDS
2) Wafer
3) Individual component
MJSNSO
'""
~
OV
VGS
~
OV
. , Ciss
1000
Coss
Crss .........
10
5
0
5
10
15
20
25
30
35
VGS
VDS
lor - VDG)
(or YOGI
GATE·TO-SOURCE OR DRAIN·TO·SOURCE VOLTAGE (VOLTS)
o
--t-
FIGURE 12-37 - COMPLETE REPRESENTATION OF
CAPACITANCE VALUATION OF THE MTH6N60
40
A wafer lot is a group of wafers which are processed
together. A typical example for switching power supply
output transistors is fifty wafers per lot and 100 transistors
per wafer, for a total of roughly 5,000 transistors per wafer
lot. The statistical considerations arise from the way semiconductors are batch processed in wafer lots. The cookie
analogy is a helpful illustration.
Suppose a baker has three groups of raw cookies. Each
group is sufficiently large to fully use available space in
the baking oven. The three groups are therefore baked
sequentially. The first group is slightly overdone and relatively dark. The second group comes out slightly underdone and very light. The third group turns out medium.
MOTOROLA TMOS POWER MOSFET DATA
1-12-22
Design Samples
Lightness or darkness of the individual cookies will vary
somewhat within each group, but probably not by very
much. Variations in color are much more dependent upon
which group a cookie was baked in than which individual
cookie was chosen from a given group. A sample of cookies chosen from anyone group will poorly predict the
variations expected from the baking process.
Semiconductor characteristics vary in much the same
way. Many characteristics are far more dependent upon
the wafer lot in which a device is processed than upon
which individual device is chosen from a given wafer lot.
An illustration is shown in Figure 12-38.
A
A key factor in top notch design work is obtaining statistically relevant samples of key components. With respect to power transistors, this means including a number
of different wafer lots in the design sample. This task can
be seemingly difficult since, in general, the number of
wafer lots in a given sample is not known. However, the
minimum number of wafer lots in a sample can be determined by assuming that each date code consists of separate wafer lots. There may be many wafer lots in a date
code, but usually two date codes will not contain transistors from the same wafer lot.
Often, transistors have two date codes, one which corresponds to the time period in which they are tested and
the other which denotes the time period in which they
were assembled. The assembly date code is by far the
more valuable of the two. As an example, Motorola TO204 transistors have a three-digit assembly date code
stamped on the ear. The first digit is coded to the year.
The second and third digits correspond to workweek. A
transistor built in the last workweek of 1987 would read
752.
Sample selection, then, hinges on being able to obtain
transistors from a number of different date codes. Here
are some suggestions.
1) Place several small orders sequentially in time.
2) Order from several different distributors, preferably
in more than one geographic location. Five 20 piece
shipments from five different distributors will cost
more than a single shipment of 100 pieces, but the
benefits dwarf the added expense.
3) Ask the manufacturer for assistance.
A'
FIGURE 12-38 - EXAMPLE PROBABILITY DISTRIBUTIONS
Population densities for transistors in two different wafer
lots, curves A and A'. are plotted on the same scale as
the wafer lot distribution for the same parameter. It is clear
that a sample selected, from wafer lot A will poorly predict
the performance expected from transistors in lot A'. These
curves are typical of the way many transistor parameters
vary. They are also descriptive of batch processed components in general.
From an equipment design point of view, these characteristics have serious implications. The validity of a 100
piece design sample becomes questionable, when .the
possibility that all 100 devices may be from the same wafer
lot is considered. In fact, the validity of using 100 devices,
which are purchased all in one group, is more than questionable. For those parameters which are highly wafer lot
dependent, such a sample is, in effect, not a 100 piece
sample, but a one piece sample, since there is a very
high probability that only one wafer lot is represented.
The unfortunate circumstances in the opening scenario
are a direct result of a one piece wafer lot sample. The
one piece sample does not buy much statistical insurance.
Surprises are likely, since a false sense of security is
generated when it is believed that 100 physical units in a
design sample represent a 100 piece statistical sample.
The results are predictable and unpleasant for all
concerned.
As a practical matter, it will generally be rather difficult
to obtain a sample with more than four or five wafer lots
represented. Since this is a relatively small sample, a
working knowledge of parameter variations is very helpful.
This is particularly true of Safe Operating Area (SOA)
which is presented here as a special case.
Safe Operating Area
Safe Operating Area is probably the most troublesome
of the unspecified parameters. Operation in unspecified
regions is difficult to avoid since it is not practical to guarantee the transistor for all conditions in which it can be
used. Usually, unspecified operation is related to the fact
that SOA curves are drawn for given circuit configurations
and bias conditions. Operation in conditions other than
specified is not necessarily guaranteed. Therefore, it is
often easy to operate fully within the boundaries of an
SOA curve, yet be in an unspecified region because of
differences in circuit configuration or bias.
At times like this, a straightforward test can be very
effective. The steps are as follows:
1. Starting with the equipment in which the transistor
will operate, or a suitable test circuit, raise the)nput
bus voltage to 1.25 x its worst case value. Test the
equipment for survivability. If any transistors in the
design sample fail, there is not enough safety margin. Future trouble is almost guaranteed. If none fail,
proceed to Step 2.
2. Raise the bus voltage to 1.33 x its worst case value.
Repeat the testing. If more than 50% of the sample
transistors survive, then SOA safety margin is probably more than adequate.
MOTOROLA TMOS POWER MOSFET DATA
1-12-23
3. Recognize that worst case SOA stress. in switching
power conversion systems. will often occur at conditions other than full load and high temperature. It
is important to either choose conditions which maximize transistor stress. or cycle the equipment
through its mini-max load and temperature ranges.
Successful results will depend largely on attention
to test conditions. An example is noteworthy.
SOA stress is often maximized in the first or last
switching cycle. when the equipment is turned-on or
turned-off. Load lines for the first or last cycle often
have larger excursions than steady-state full load
operation. A single excursion to a high voltage is
usually more hazardous than operating at a lower
voltage on a continuous basis.
Power MOSFET Measurement
Techniques For The Curve
Tracer
The curve tracer is an extremely useful tool in measuring the pertinent power MOSFET parameters. The
techniques are not dissimilar to those used for measuring
bipolar transistors. Table 4 lists the equivalent parameters
between the two.
TABLE 4
Transistor
These steps are very effective at eliminating unwanted
surprises. provided transistors from at least three wafer
lots are included in the test. They form the same basic
procedure that is used to generate data sheet SOA
curves.
General Guidelines
It is often of interest to obtain reasonable limits for parameters other than SOA. A discussion of expected variations is a good place to start.
Variations within a given sample are obvious. Of interest
here is the expected worst case variations over the life of
a multi-year production run. Table 3 gives an indication
of what can generally be expected for various parameters.
Measured mean values come from data taken on transistors in the design sample. They are normalized to 1.0
for ease of comparison. It is important to note that Table
3 applies only if at least three wafer lots are included in
the sample data.
MOSFET
Collector
Emitter
Base
V(BR)CES
VCBO
IC
ICES
lEBO
VBE(on)
VCE(sat)
Cib
Cob
hFE
Drain
Source
Gate
V(BR)OSS
VOGR
10
lOSS
IGSS
VGS(th)
VOS(on)
Ciss
Coss
9fs
VCE(sat)
RCE(sat) = -I-C-
VOS(on)
rOS(on) = -1-0-
VEC
VSO
No FET parameters are measured in an open gate
condition. To prevent damage to the part. the gate
should always be terminated with a resistor (typically RGS
= 1.0 MO) or a short for the appropriate test condition.
TABLE 3
Parameter
•
Leakage Currents
Breakdown Voltages
Gain
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Crossover Time
Gate Threshold Voltage
rOS(on)
VOS(on)
Ciss
Coss
Crss
Measured
Mean
Value
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Expected
Min
10-3
0.7
0.5
0.7
0.5
0.5
0.5
0.5
0.6
0.5
0.5
0.7
0.5
0.6
Expected
Max
10+ 3
1.5
4.0
1.5
2.0
2.0
2.0
2.0
1.5
2.0
2.0
1.5
2.0
1.6
DEFINITIONS OF ELECTRICAL
CHARACTERISTICS
Off Characteristics
V(BR)OSS. Drain-Source Breakdown Voltage - Maximum sustaining voltage between the drain and source.
measured at a specific drain current. 10; Gate shorted to
the source.
lOSS. Drain-Current With Zero Gate Voltage - Drain
leakage current at a specified drain-source voltage.
VOSS; Gate shorted to source.
Although some of the resulting tolerances may seem
rather large. they are realistic when production runs spanning a number of years are considered. It is far better to
face these numbers up front. than be surprised downstream with equipment failures.
Conclusion
The risk of equipment failure can be significantly reduced by straightforward improvements in the selection
of design samples. Risks are further minimized with realistic estimation of worst case parameter variations. and
the proper choice of test conditions for maximum stress.
IGSS. Gate Body Leakage Current - Gate leakage current for a specified gate-source voltage; Drain shorted to
source.
On Characteristics .
VGS(th). Gate Threshold Voltage - Value of the gate
voltage that must be applied to initiate conduction. It has
a negative temperature coefficient of about -6.7 mVrC.
VOS(on). Drain-Source On-Voltage - Voltage drop measured between the drain and source at a specified drain
current and specified gate-source voltage.
MOTOROLA TMOS POWER MOSFET DATA
1-12-24
rDS(on), Drain-Source On-Resistance - Value of the resistance measured between drain and source at a specified drain current and a specified gate-source voltage. It
is defined as:
Set-up is the same as V(BR)DSS/except:
1 - Set Mode Switch to Leakage.
VDS(on)
rDS(on) = -1-09fs, Forward Transconductance - The MOSFET gain
parameter. It is the ratio between the change in drain
current, 10, for a given change in gate-source voltage, at
a specified drain-source voltage and specified drain
curreNt. In algebraic fOrm:
2 -
Set Vertical to 50 /LA/Division
3 -
Adjust variable collector supply to 85 volts and
read leakage. If Leakage reads 0, adjust Vertical
to desired level (This increases sensitivity on low
leakage devices).
IGSS - Specified at V GS = ± 20 volts, maximum allowable leakage is 500 nA at TC - 25°C.
Test Set-Up
1 -
61 0
9fs = 6VGS
2 -
VSD, Diode Forward On-Voltage - The forward voltage
drop between the source and drain at a specified SoD
diode current IS.
3 -
Polarity to NPN and Mode Switch to Leakage.
4 -
Vertical on 50 nA/Division, Display Offset on 0,
Horizontal on 2.0 Volts/Division.
5 -
Step generator is not used for this measurement.
Curve Tracer Measurements
The following explains how to measure the parameters
listed above on a curve tracer. Although the set-up charts
correspond to the Tektronic Type 576 Curve Tracer, the
same measurements can be performed on a Tektronix
Type 577 Curve Tracer.
Before applying power to MOSFETs on a curve tracer,
the following precautions should be observed:
1 -
Test stations should be protected from ElectroStatic Discharge.
2 -
When inserting parts into a curve tracer, voltage
should not be applied until all terminals are solidly
connected in the socket.
A resistor of 100 n should be connected in series
with the gate to damp spurious oscillations that
can occur on the tracer.
3 -
4 -
V(BR)DSS - Also known as BVDSS. Specified at an 10
of 5.0 rnA at TC = 25°C.
Test set-up and Source Trace (See Figure 12-39).
6 -
Emitter grounded; Base Term on short.
7 -
With device in socket, adjust variable collector
supply to 20 volts and read Leakage. If leakage
reads 0, adjust vertical to desired level.
VGS(th) - Specified at 1.0 rnA with limits of 2.0 volts
minimum and 4.5 volts maximum at TC = 25°C.
(Figure 12-40)
1 -
When switching from one test range to another,
voltage settings should be reduced to zero to
avoid generation of potentially destructive voltage
surges during switching.
The test set-ups to follow are for the Motorola
MTP12N10 Power MOSFET, which is a 12 Amp, 100 volt
N-Channel device in the TO-220 package.
Drain and gate connections on socket are reversed so drain is shorted to source.
Set maximum peak volts to 75, and Series Resistors to 140 n.
Set Maximum Peak Volts to 15, Series Resistors
to 0.3 n.
2 -
Polarity to NPN, Mode Switch on Normal.
3 -
Vertical on 0.2 rnA/Division, Display Offset on 0,
Horizontal on 2.0 Volts/Division.
4 -
Step Generator; number of steps = 1, Offset Mult
on 0, Offset on Aid, Steps Button in, Step Family
on Single, Rate on Norm, Step offset amplitude
= 1.0 V.
Emitter grounded; Base Term on Step Generator.
5 6 -
With device in socket, adjust variable collector
supply to 10 volts, then adjust Offset Mult until
trace reaches 1.0 rnA. Read VGS(th) directly from
Offset Mult Control.
VDS(on) - Specified at VGS = 10 volts and at one half
rated 10. rDS(on) is calculated from measured VDS(on)
value.
1 -
Set maximum peak volts on 350, Series Resistors
on 3.0 k.
2 -
Polarity to NPN, Mode to Norm.
3 -
Vertical on 1.0 rnA/Division, Display Offset on 0,
Horizontal on 20 volts/Division.
2 -
Polarity on NPN, Mode to Norm.
4 -
Step Generator is not used for this measurement.
3 -
Vertical on 1.0 A/Division, Display Offset on 0,
Horizontal on 0.5 Volts/Division.
Step Generator; number of steps - 10, Offset on
zero, pulsed steps on 300 /LS, Step Family on Rep,
rate on Norm, Step OffseVAmplitude = 1.0 V.
Emitter grounded; Base Term on Step Gen.
(Figure 12-41)
1 -
5 -
Emitter grounded; Base Term on short.
6 -
With device in socket, adjust variable collector
supply until trace breaks and reaches 5.0 rnA.
4 -
lOSS - Specified at 85% of rated V(BR)DSS. Maximum
allowable leakage is 250 /LA at TC = 25°C.
5 -
Test Set-Up
6 -
Set Maximum Peak Volts on 15, Series Resistors
on 0.3 n.
With device in socket, adjust variable collector
supply until the top left dot on trace reaches 6.0
Amps then read VDS(on) off horizontal scale.
MOTOROLA TMOS POWER MOSFET DATA
1-12-25
TYPE 578
CURVE TRACER
""""'.UIIC..
Not Used
For
V(BR)DSS
•
~
.-
.~-
. .._ '*'
........
.-_
,..........
'eOUlc
... .
n_
o
000
0
FIGURE 12-39 - TEST SET-UP CHART TYPE 576 FOR MEASURING POWER MOSFET PARAMETERS
MOTOROLA TMOS POWER MOSFET DATA
1-12-26
II
I
I
V
IV
r
II
,,
/
y
~
9FS
\
1///
,,/
~
ArJ
,-f"I
,
FIGURE 12-42 -
FIGURE 12-40 - CURVE TRACER PRESENTATION
FOR VGS(th) - MTP12N10
VSD -
CURVE TRACER FOR 9fs
Specified at rated ID with VGS = O.
(Figure 12-43)
1 -
,
FIGURE 12-41 -
9fs -
~/
Set Maximum Peak Volts on 15 and Series Resistors on 0.3 n.
2 -
Polarity on PNP, Mode on Norm.
3 -
Vertical on 2.0 Amps/Division, Display Offset on
0, Horizontal on 0.5 Volts/Division.
4 5 -
Push Display Invert in.
Step Generator is not used for this measurement.
6 -
With device in socket, adjust variable collector
supply until trace reaches 12 Amps and read
voltage.
CURVE TRACER PRESENTATION FOR VOS(on)
I
Specified at one half rated ID at VDS = 15 volts.
I
(Figure 12-42)
1 -
Maximum Peak Volts on 15, Series Resistors on
0.3 n.
2 3 -
Polarity on NPN, Mode to Norm.
Vertical on 1.0 Amp/Division/Display Offset on
zero, Horizontal on 2.0 Volts/Division.
Step Generator; number of steps = 10, Offset on
zero, Pulsed Steps on 300 p's, Step Family on
Rep, rate on Norm, Step Offset Amplitude - 1.0 V.
4 -
5 -
I
V
/
----
FIGURE 12-43 -
CURVE TRACER PRESENTATION FOR VSO
Emitter grounded; Base Term on Step Gen.
6 -
Readout ilium turned fully clockwise.
7 -
With device in socket, adjust variable collector
supply until trace with steps closest to 6.0 Amps
reaches 15 volts. 9fs is the number of divisions
between those two steps, as designated by the
right hand corner of the screen labeled gm per
Division.
REFERENCES
1. Fink, Electronic Engineers' Handbook, 1 ed 1975,
McGraw Hill, pp17-31 to 17-32.
2. Henny, Radio Engineering Handbook, 5 ed, 1959,
McGraw Hill, pp14-36 to 14-37.
Additional Reference Material: Measurement Concepts
From Tektronix.
MOTOROLA TMOS POWER MOSFET DATA
1-12-27
•
MOTOROLA TMOS POWER MOSFET DATA
1-12-28
Chapter 13: Reliability and Quality
Introduction
In today's semiconductor marketplace two important
elements for the success of a company are product quality
and reliability. Both are interrelated - reliability is the
quality extended over the expected life of the product. For
any manufacturer to remain in business, their products
must meet and/or exceed the basic quality and reliability
standards. Motorola, as a semiconductor supplier, has
successfully achieved these standards by supplying product for the most strenuous applications to perform in the
most adverse environments.
It is recognized that the best way to accomplish an
assured quality performance is by moving away from the
previous methods of "testing in" quality and embracing
the newer concept of "building in" quality. At Motorola,
we use a twofold approach toward reaching the ultimately
achievable level of quality and reliability. First, we develop
and implement a process that is inherently reliable. Then
we exercise meticulous care in adhering to the specifications of the process every step of the way - from start
to finish. This allows the development and application of
inspections and procedures that will uncover potentially
hidden failure modes. It is this dedication to long-term
reliability that will ultimately lead to the manufacture of the
"perfect product."
Motorola approaches the ideal in TMOS product reliability by instigating a four-step program of quality and
reliability:
1. Stringent in-process controls and inspections.
2. Thoroughly evaluated designs and materials.
3. Process average testing, including 100% QA redundant testing.
4. Ongoing reliability verifications through audits and reliability studies.
These quality and reliability procedures, coupled with
rigorous incoming inspections and outgoing quality control
inspections add up to a product with quality built in from raw silicon to delivered service.
For TMOS devices, voltage is applied between the drain
and source with the gate shorted to the source. IDSS,
V(BR)DSS, IGSS, VGS(th), and VDS(on) are the dc
parameters monitored. A failure will occur when the leakage achieves such a high level that the power dissipation
causes the devices to go into a thermal runaway. The
leakage current of a stable device should remain relatively
constant, only increasing slightly over the testing period.
Typical conditions:
VDS = 100% of maximum VDS rating
VGS = 0 (shorted)
TA = 150°C
Duration: 1000 hrs for qualification
High Temperature Gate Bias (HTGB):
Per MIL-STD-750, Method 1039:
The HTGB test is designed to electrically stress the gate
oxide at the maximum rated dc bias voltage at high temperature. The test is designed to detect for drift caused
by random oxide defects and ionic oxide contamination.
For TMOS devices, voltage is applied between the gate
and source with the drain shorted to the source. IGSS,
VGS(th), and VDS(on) are the dc parameters monitored.
Any oxide defects will lead to early device failures.
Typical conditions:
VGS = ±20 V
VDS = 0 (shorted)
TA = 150°C
Duration: 1000 hrs for qualification
High Temperature Storage Life (HTSL) Test:
Per MIL-STD-750, Method 1032.
The HTSL test is designed to indicate the stability of
the devices, their potential to withstand high temperatures
and the internal manufacturing integrity of the package.
Although devices are not exposed to such extreme high
temperatures in the field, the purpose of this test is to
accelerate any failure mechanisms that could occur during
long periods at storage temperatures.
The test is performed by placing the devices in a mesh
basket, then placed in a high temperature chamber at a
controlled ambient temperature, as a function of time.
Typical conditions:
TA = 150°C on Plastic package
Duration: 1000 hrs for qualification
Reliability Tests
Motorola TMOS products are subjected to a series of
extensive reliability tests to verify conformance. These
tests are designed to accelerate the failure mechanisms
encountered in practical applications, thereby ensuring
satisfactory reliable performance in "real world"
applications.
The following describes the reliability tests that are routinely performed on Motorola's TMOS devices.
High Humidity High Temperature Reverse Bias
(H3TRB) Test: Per MIL-STD-750, Method 1039.
The H3TRB test is designed to determine the resistance
of component parts and constituent materials to the combined deteriorative effects of prolonged operation in a high
temperature/high humidity environment. This test only applies to nonhermetic devices.
Humidity has been a traditional enemy of semiconductors, particularly plastic packaged devices. Most moisture
related degradations result, directly or indirectly, from penetration of moisture vapor through passivating materials,
High Temperature Reverse Bias (HTRB) Per
MIL-STD-750, Method 1039:
The HTRB test is designed to check the stability of the
device under "reverse bias" conditions of the main blocking junction at high temperature, as a function of time.
The stability and leakage current over a period of time,
for a given temperature and voltage applied across the
junction, is indicative of junction surface stability. It is
therefore a good indicator of device quality and reliability.
MOTOROLA TMOS POWER MOSFET DATA
'-'3-'
and from surface corrosion. At Motorola, this former problem has been effectively addressed and controlled
through use of junction "passivation" process, die coating,
and proper selection of package materials.
Typical conditions:
VDS = 100% of maximum VDS rating up to 200 V
VGS = 0 (shorted)
TA = 85°C
RH = 85%
Duration: 1000 hrs for qualification
Autoclave Test (Pressure Cooker).
The Autoclave Test is designed to determine the moisture resistance of devices by subjecting them to high
steam pressure levels. This test is only performed on plastic/epoxy encapsulated devices and not on hermetic packages (i.e., metal can devices). Within the pressure cooker
a wire mesh tray is constructed inside to keep the devices
approximately two inches above the surface of deionized
water and to prevent condensed water from collecting on
them. After achieving the proper temperature and atmospheric pressure, these test conditions are maintained for
a minimum of 24 hours. The devices are then removed
and air dried. Parameters that are usually monitored are
leakage currents and voltage.
Typical Conditions:
TA = 121°C
P = 14.7 psi
RH = 100%
Duration: 72 hrs for qualification
Intermittent Operating Life:
(IOL or Power Cycling) Per MIL-STD-750,
Method 1037.
The purpose of the 10L test is to determine the integrity
of the chip and/or package assembly by cycling on (device
thermally heated due to power dissipation) and cycling off
(device thermally cooling due to removal of power applied)
as is normally experienced in a "real world" environment.
DC power is applied to the device until the desired
function temperature is reached. The power is then
switched off, and forced air cooling applied until the junction temperature decreases to ambient temperature.
aTJ = aTc + R(JJCPd
aTJ = 100°C
(typically, which is an accelerated condition)
•
aTC = TC HIGH - TC LOW
The sequence is repeated for the specified number of
cycles. The temperature excursion is carefully maintained
for repeatability of results.
The Intermittent Operating Life test indicates the degree
of thermal fatigue of the die bond interface between the
chip and the mounting surface and between·the chip and
the wire bond interface.
For TMOS devices, parameters used to monitor performance are thermal resistance, threshold voltage, onresistance, gate-source leakage current and drain-source
leakage current.
A failure occurs when thermal fatigue causes the thermal resistance or the on-resistance to increase beyond
the maximum value specified by the manufacturer's data
sheets.
Typical conditions:
VDS;;;.10V
a TJ = 100°C
ROJC = Device dependent
Ton, Toff ;;;. 30 seconds
Duration: 15K cycles for qualification
TEMPERATURE CYCLE (TC) PER MIL-STD-750,
METHOD 1051:
The purpose of the Temperature Cycle Test is to determine the resistance of the device to high and low temperature excursions in an air medium and the effects of
cycling at these extremes.
The test is performed by placing the devices alternatively in separate chambers set for high and low temperatures. The air temperature of each chamber is evenly
maintained by means of circulation. The chambers have
sufficient thermal capacity so that the specified ambient
is reached after the devices have been transferred to the
chamber.
Each cycle consists of an exposure to one extreme
temperature for 15 minutes minimum, then immediately
transferred to the other extreme temperature for 15 minutes minimum; this completes one cycle. Note that it is
an immediate transfer between temperature extremes and
thereby stressing the device greater than non-immediate
transfer.
Typical Extremes
-65/+ 150°C
The number of cycles can be correlated to the severity
of the expected environment. It is commonly accepted in
the industry that ten cycles is sufficient to determine the
quality of the device.
Typical Cycles for Evaluations
TO-204 and TO-220 devices: Minimum 100 cycles
TO-204 and TO-220 devices: Maximum 1000 cycles
Temperature cycling identifies any excessive strains set
up between materials within the device due to differences
in coefficients of expansion.
A failure occurs when there is a change in the device's
parameters beyond specified levels, or when a device
checks electrically as "open" or "short".
Thermal Shock (TC) Per MIL-STD-750,
Method 1056:
The purpose of this test is to determine the resistance
of the device to sudden exposure to extreme changes in
temperature.
The test is performed by placing the devices in a mesh
basket, then alternatively immerse in baths of liquid (maintained at - 55°C and + 150°C). They are kept for thirty
seconds in each bath and immediately transferred to the
alternate bath.
This test produces sudden heating and cooling of the
device, and produces unusual stresses due to the short
term temperature gradients that are set up. It is commonly
accepted in the industry that five cycles is sufficient to
determine the quality of the device.
A failure occurs when there is a change in the device's
parameters beyond specified levels, or when a device
checks electrically as "open" or "short".
MOTOROLA TMOS POWER MOSFET DATA
1-13-2
6-
o-
OXIDATION
P+
PHOTORESIST
P+
DIFFUSION
RESISTIVITY!
THICKNESS
POLY
DEPOSITION
GATE OXIDE
EVALUATION
GATE
OXIDE
P+ PROTECT
PHOTORESIST
POLY
PHOTORESIST
CHANNEL
DIFFUSION
SOURCE
DIFFUSION
PRE-OHMIC
PHOTORESIST
UNIT
PROBE
WAFER THINNING!
BACKMETAL
PASSIVATION
DEPOSITION
PHOTORESIST
FRONT METAL
DEPOSITION!
PHOTORESIST
DENOTES OA INSPECTION POINT
DENOTES PROCESS STEP
TMOS WAFER FABRICATION
UNIT
PROBE"
O.A. VISUAL
5WAFERILOT
100%
SAW
THRU
OA VISUAL
10!2HR ACC=O
12MRB78713A
DIE
BOND
O.A. VISUAL
32!HR ACC=O
DIE
COAT
O.A. VISUAL
321HR ACC=O
DESTRUCTIVE WIRE
PULL" 5!HR ACC=O
WIRE
BOND
OA VISUAL
32!HRACC=0
12M504596
FINAL TEST
100% DC ELECT.
TEST""
O.A. OUTGOING
FINAL
INSPECTION
SHIPPING
GROUPAOA
OUTGOING INSP.
"100% NON-DESTRUCTIVE WIRE PULL AFTER WIRE BOND
""100% DC ELECTRICAL TESTING
MARKING
6 - DENOTES OA INSPECTION POINT
DENOTES PROCESS STEP
o-
ASSEMBLY PROCESS FLOW
MOTOROLA TMOS POWER MOSFET DATA
1-13-3
100%
OA ELECT:"
•
Environmental Package Related Test Programs:
A. Physical Dimensions - Mil-Sld-750, Melhod 2066.
This lesl is performed 10 delermine Ihe conformance 10 device outline drawing specifications.
B. Visual and mechanical examination - Mil-Std-750
Method 2071. A test to determine the acceptabilitY
of product to certain cosmetic and functional criteria
such as marking legibility, stains, etc.
C. Resistance to Solvents - Mil-Std-202, Method
2025.3. A tesl to determine the solderability of device terminals.
D. Terminal Strength - Mil-Std-750, Method 2036.
This test is a lead bend test to check for lead
strength.
'.
50
~
>=.
90
100
110
120
130
140
150
10K
~
w
a:
:::
~
Accelerated Stress Testing
The nature of some tests in this report is such that they
far exceed that which the devices would see in normal
operating conditions. Thus, the test conditions "accelerate" the failure mechanisms in question and allow
Motorola to predict failure rates in a much shorter amount
of time than otherwise possible. Failure modes that are
temperature dependent are characterized by the Arrhenius model.
(..!.._..!..
)
T2
T1
AF = Acceleration Factor
EA = Activation Energy (ev)
K = Boltzman's Constant (8.62 x 10- 5 ev/oK)
T2 = Operating Temperature (OK)
T 1 = Test Temperature (OK)
Therefore, the equivalent device hours are equal to the
acceleration factor (as determined by the Arrhenius
Model) times the actual device hours.
With the following charts (13-1, 13-2), one can determine a temperature oependent failure rate for our power
MOSFETs under reverse and gate bias conditions when
establishing their design circuits. For example, if the
established operating temperature is set at 50°C, the
charts show the failure rates to be 1 and 680 fits for high
temperature reverse bias and high temperature gate bias,
respectively.
Review of Data
High Temperature Reverse Bias (HTRB) indicates the
stability of leakage current, which is related to the field
80
lOOK
Every manufacturing process exhibits a quality and reliability distribution. This distribution must be controlled to
assure a high mean value, a narrow range and a consistent shape. Through proper design and process control
this can be accomplished, thereby reducing the task of
screening programs which attempt to eliminate the lower
tail of the distribution.
•
70
FIGURE 13-1 - HIGH TEMPERATURE REVERSE BIAS FAILURE
RATE VERSUS JUNCTION TEMPERATURE
Vibration Variable Frequency - Mil-Sld-750,
Method 2056. Parts are vibrated in different planes
and at different frequencies to check for loose particles or ruptured wire or die bonds.
AF=e EA
K
60
TJ, JUNCTION TEMPERATURE 'C
E. Constant Acceleration - Mil-Std-750 Method
2006. The paris are accelerated to 20,000 G's and
higher to check for defects that would show up in
this environment.
F.
102+-----.--.,---r-----.--r---r-----.--r--~__l
..;.-
1K
100
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE ('C)
140
160
FIGURE 13-2 - HIGH TEMPERATURE GATE BIAS FAILURE
RATE VERSUS JUNCTION TEMPERATURE
distortion of TMOS devices. HTRB enhances the failure
mechanism by high temperature reverse bias testing, and
therefore is a good indicator of device quality and reliability, along with verification that process controls are
effective.
. High Temperature Gate Bias (HTGB) checks the stability of the device under "gate bias" forward conditions
at accelerated high temperature, as a function of time.
This test is performed to electrically stress the gate oxide
to detect for drift caused by random oxide defect. This
failure mechanism appears in the infant and random
zones of the reliability "bath tub curve" at a very low rate
of defect.
Intermittent Operating Life (IOL) is an excellent accelerated stress test to determine the integrity of the chip
and/or package assembly to cycling on (device thermally
heated due to power dissipation) and cycling off (device
thermally cooling due to removal of power applied). This
test is perhaps the most important test of all, along with
simulating what is normally experienced in a "real world"
environment. IOL exercises die bond, wire bonds, turning
on the device, turning off the device, relates the device
performance, and verifying the thermal expansion of all
materials are compatible. Motorola performs extensive
MOTOROLA TMOS POWER MOSFET DATA
1-13-4
temperature cycle stresses the "device system" thermally
from external environment conditions.
High Temperature Storage Life (HTSl), High Humidity
Temperature Reverse Bias (H3TRB), Thermal Shock (TC)
and "Pressure Cooker" (Autoclave) are routinely tested,
however it is felt by Motorola Reliability Engineering that
HTRB, HTGB, IOl and TC are of primary importance.
Motorola has been in the semiconductor industry for many
years and will remain there as a leader with continued
reliability, quality and customer relations.
IOl testing as a continual process control monitor that
best relates to the "device system·· .. as a whole. Motorola
also performs extensive analysis and comparison of delta
junction temperatures. Motorola has determined that to
effectively stress the device a delta TJ of 100°C is necessary which far exceeds many customers' application
and determines the reliability modeling of the device.
Temperature Cycling (TC) is also an excellent stress
test to determine the resistance of the device to high and
low temperature excursions in an air medium. Where IOl
electrically stresses the "device system" from internally,
Test Results Summaries
TABLE 1
SUMMARY OF TIME DEPENDENT TESTS
Test
Type
Test Conditions
Devices
Failed
Device Hrs.
(Actual)
Equivalent
Device Hrs.
@90'C
Failure Rate
% Per 1000 Hrs.
HTRB
VOS = 80% of Max. Rating'
VGS = 0 (Shorted)
TA = 150'C
43
7 x 106
6.51 x 108
.0068
HTGB
VGS=±20V
VOS = 0 (Shorted)
TA = 1SO'C
24
3.11 x 106
1.21 x 109
.2063
HTSL
TA = 1SO'C
1
8.9 x 105
8.3 x 107
0.0025
H3TRB
TA = 85'C
R.H. = 85%
VGS = 0 (Shorted)
VOS = 80% of Max. Rating up to 200 V
0
3.2 x 105
-
0.28
Failure Unit (FIT):
Modem electronic system reliability utilizing today's semiconductor devices requires quite low component failure rates, and therefore requires a workable number. This
number called a FIT (~ailure Un~) is defined as: FIT = one failure on 109 device hours.
Mean Time Between Fajlures (MTBF):
The significant distribution properties of electronic system reliability is expressed as MTBF, which is defined, as:
t
= til.
Where, t = time. hours
~ = failure rate
.. (changed to 100% of max rating 2087)
TABLE 2
SUMMARY OF CYCLE DEPENDENT TESTS
Test
Type
Test Conditions
Devices
Failed
Device Cycles
(Actual)
Equivalent
Device Hrs.
@9O"C
Failure Rate
% Per 1000
Cycles
IOL
aTJ = 100'C
VOS '" 10V
lon, Ioff '" 30 s
9
4.3 x 107
-
.023
TC
Tlow = -6S'C
Thigh = 150"C (Plastic)
Thiah = 200'C (Metal)
18
2.44 x 106
-
0.74
'ActlVa~on
energy for HTRB, HTSL
•
= 1 eV; for HTGB = 0.3 eV.
MOTOROLA TMOS POWER MOSFET DATA
1-13-5
Reliability Audit Program
At Motorola reliability is assured through the rigid implementation of a reliability audit program. All TMOS products
are grouped into generic families according to voltage
ranges and package types. These families are sampled
weekly from the raw stock at final test, then submitted for
audit testing. The extreme stress testing, in real-time for
each product run, may uncover process abnormalities that
are detectable by the in-process controls. Typical reliabilityaudit tests include high temperature reverse bias,
high temperature gate bias, intermittent operating life,
temperature cycling, and autoclave. To uncover any hidden failure modes, the reliability tests are designed to
exceed the testing conditions of normal quality and reliability testing.
Audit failures which are detected are sent to the product
analysis laboratory for real-time evaluations. This highly
specialized area is equipped with a variety of analytical
capabilities, including electrical characterizations, wet
chemical and plasma techniques, metallurgical crosssectioning, scanning electron microscope, dispersive,
x-ray, auger spectroscopy, and micro/macro photography.
Together, these capabilities allow the prompt and accurate
analysis of failure mechanisms - ensuring that the results
of the evaluations can be translated into corrective actions
and directed to the appropriate areas of responsibility.
The Motorola reliability audit program provides a pow, erful method for uncovering even the slightest hint of potential process anomalies in the TMOS product line. It is
this stringent and continuing concern with the reliability
audits that gives positive assurance that customer satisfaction will be achieved.
Power FET
TMOS Reliability Audit Program
SIS
Frequency
HTRB
VDS = 100% Max Rating
VGS = 0
TA = lS0'C
Duration = 72 Hours (short).
1000 Hours (long)
SO/Family
Weekly
HTGB
VGSS = ± 20V
VDS = 0
TA = lSO'C
Duration = 72 Hours (short).
1000 Hours (long)
SO/Family
Weekly
IOL
Metal Products
36/Family
Weekly
...J
~
Reliability Mechanics
Since reliability evaluations usually involve only samples of an entire population of devices, the concept of the
central limit theorem applies and a failure rate is calculated
using the 11. 2 distribution through the equation:
11. 2
(a, 2r
+
X
a
w
IE
I
I
/tS(
5
FIGURE 13-4 -
A, FAILURE RATE
CONFIDENCE LIMITS AND THE DISTRIBUTION
OF SAMPLE FAILURE RATES
the definition of rejects often differs between manufacturers. Due to the increaSing chance of a test not being
representative of the entire population as sample size and
test time are decreased, the 11. 2 calculation produces surprisingly high values of II. for short test durations even
though the true long term failure rate may be quite low.
For this reason relatively large amounts of data must be
gathered to demonstrate the real long term failure rate.
Since this would require years of testing on thousands of
devices, methods of accelerated testing have been
developed.
Years of semiconductor device testing has shown that
temperature will accelerate failures and that this behavior
fits the form of the Arrhenius equation:
R(t) = Ro (t)e- 0/KT
Where R(t) = reaction rate as a function of time and
temperature
Ro = A constant
t = Time
T = Absolute temperature, °Kelvin rC
273°)
Activation energy in electron volts (ev)
K = Boltzman's constant = 8.62 x 10 - 5 ev/oK
This equation can also be put in the form:
= chi squared distribution
AF = Acceleration factor
100 - cl
where a = ~
T2 = User temperature
II.
Failure rate
T1 = Actual test temperature
cl
Confidence limit in percent
The Arrhenius equation states that reaction rate increases exponentially with the temperature. This produces a straight line when plotted on log-linear paper with
a slope physically interpreted as the energy threshold of
a particular reaction or failure mechanism.
Number of rejects
n
+
o=
2)
II. ,,;; --'--'2=-nt,----'11.2
50%CL
t
zw
Number of devices
Duration of tests
The confidence limit is the degree of conservatism desired in the calculation. The central limit theorem states
that the values of any sample of units out of a large population will produce a normal distribution. A 50% confidence limit is termed the best estimate, and is the mean
of this distribution. A 90% confidence limit is a very conservative value and results in a higher II. which represents
the pOint at which 90% of the area of the distribution is to
the left of that value (Figure 13-4).
The term (2r + 2) is called the degrees of freedom and
is an expression of the number of rejects in a form suitable
to 11.2 tables. The number of rejects is a critical factor since
Reliability Qualifications/Evaluations Outline:
Some of the functions of Motorola Reliability and Quality
Assurance Engineering is to evaluate new products for
introduction, process changes (whether minor or major),
and product line updates to verify the integrity and reliability of conformance, thereby ensuring satisfactory performance in the field. The reliability evaluations may be
subjected to a series of extensive reliability testing, such
as those outlined in the "Tests Performed" section, or
special tests, depending on the nature of the qualification
requirement.
MOTOROLA TMOS POWER MOSFET DATA
•
High Reliability Power MOSFET Products
Motorola has the broadest line of MIL-qualified discrete
and integrated circuits for the widest range of designs.
Power MOSFETs are being processed at this time to join
the qualified products portfolio available from Motorola.
Complete facilities are available to conduct all three
product levels of testing on Power MOSFETs in
TO-204M and TO-205AF hermetic packages. DeviceS
designated as "JTX" and "JTXV" devices or equivalents
receive 100% screening.
Motorola offers Power MOSFETs of a custom nature
which have been processed to the specific high reliability
requirements of a critical scientific or industrial application.
Figure 13-5 illustrates the processing flow for JAN, JTX,
and JTXV and their equivalent Power MOSFETs in accordance with MIL-S-19500.
Wafer Processing
Wafer
Saw
100% Electrical
Wafer Probe
Q.A./Gov't.
Source Inspection
(JTXV Only)
Die Bond
Q.A.lGov't.
Source Inspection
(JTXV Only)
100% High Power
Die Inspect
(JTXV Only)
100% Visual
Low Power Inspection
(JTXV Only)
Wire Bond
Clean
100% Wire Pull
Pre-Cap Visual
Q.A.lGov't.
Source Inspection
(JTXV Only)
•
(continued)
FIGURE 13-5 -
JTX, JTXV ANDIOR EQUIVALENT PROCESS FLOW:
MOTOROLA TMOS POWER MOSFET DATA
1-13-8
QA Visual
Gate
(continued)
100% Process Conditioning:
1) High Temp. Storage
2) Thermal Shock
3) Acceleration
4) Hermetic Seal Tests
5) HTGB
100% Power Conditioning:
1)
2)
3)
4)
Parameter Measurement
HTRB
Parameter Readout
Lot Disposition
Inspection Tests:
Group A
Group B
Group C
Product
Delivery
JTX, JTXV
FIGURE 13-5 -
JTX, JTXV ANDIOR EQUIVALENT PROCESS FLOW (continued)
MOTOROLA TMOS POWER MOSFET DATA
1-13-9
•
Motorola High Reliability Parts Pending QUAL as of JAN 1984
MIL-S
DevIce Type
195001
Package
0.
"QUAL
Status
1'T(w)
10 (A)
V(BR)OSS (V)
rOS(on)
2N6756
JTX
5426
TO-204M
TO-3
Q
75
14
100
0.18
2N6756
JTXV
5426
TO-204M
TO-3
Q
75
14
100
0.18
2N6758
JTX
5426
TO-204M
TO-3
Q
75
9.0
200
0.4
2N6758
JTXV
5426
TO-204M
TO-3
Q
75
9.0
200
0.4
2N6760
JTX
5426
TO-204M
TO-3
Q
75
5.5
400
1.0
2N6760
JTXV
5426
TO-204M
TO-3
Q
75
5.5
400
1.0
2N6762
JTX
5426
TO-204M
TO-3
Q
75
4.5
500
1.5
2N6762
JTXV
5426
TO-204M
TO-3
Q
75
4.5
500
1.5
2N6764
JTX
5436
TO-204AE
TO-3
Q
150
38
100
0.055
2N6764
JTXV
5436
TO-204AE
TO-3
Q
150
3B
100
0.055
2N6766
JTX
5436
TO-204AE
TO-3
Q
150
30
200
0.085
2N6766
JTXV
5436
T0-204AE
T0-3
Q
150
30
200
0.085
2N676B
JTX
5436
TO-204M
TO-3
Q
150
14
400
0.3
2N676B
JTXV
5436
TO-204M
TO-3
Q
150
14
400
0.3
2N6770
JTX
5436
TO-204M
TO-3
Q
150
12
500
0.4
2N6770
JTXV
5436
TO-204M
TO-3
Q
150
12
500
0.4
2N6B23
JTX
T6D
TO-204M
TO-3
P
100
3.0
600
2.8
2N6B23
JTXV
TBD
TO-204M
TO-3
P
100
3.0
600
2.8
2N6B26
JTX
T6D
TO-204M
TO-3
P
150
B.O
600
0.9
•
MOTORGLA TMOS POWER MOSFET DATA
Motorola High Reliability Parts Pending QUAL as of JAN 1984 (Continued)
MIL-S
Device Type
195001
Package
-QUAL
Status
PT(W)
10 (A)
V(BR)OSS (V)
rOS(on)
(}
2N6826
JTXV
TBD
TO-204AA
TO-3
P
150
B.O
600
0.9
2N6782
JAN
556
TO-205AF
TO-39
P
15
3.5
100
0.6
JTX
556
TO-205AF
TO-39
P
15
3.5
100
0.6
JTXV
556
TO-205AF
TO-39
P
15
3.5
100
0.6
JAN
556
TO-205AF
TO-39
P
15
2.25
200
1.5
JTX
556
TO-205AF
TO-39
P
15
2.25
200
1.5
JTXV
556
TO-205AF
T0-39
P
15
2.25
200
1.5
JAN
556
TO-205AF
T0-39
P
15
1.25
400
3.6
JTX
556
TO-205AF
T0-39
P
15
1.25
400
3.6
JTXV
556
TO-205AF
T0-39
P
15
1.25
400
3.6
JAN
555
TO-205AF
T0-39
P
20
6.0
100
0.3
JTX
555
TO-205AF
T0-39
P
20
6.0
100
0.3
JTXV
555
TO-205AF
TO-39
P
20
6.0
100
0.3
JAN
555
TO-205AF
TO-39
P
20
3.5
200
0.8
JTX
555
TO-205AF
TO-39
P
20
3.5
200
0.8
JTXV
555
TO-205AF
TO-39
P
20
3.5
200
0.8
JAN
555
TO-205AF
TO-39
P
20
2.0
400
1.8
JTX
555
TO-205AF
TO-39
P
20
2.0
400
1.8
JTXV
555
TO-205AF
TO-39
P
20
2.0
400
loB
JAN
555
TO-205AF
TO-39
P
20
1.5
500
3.0
JTX
555
TO-205AF
TO-39
P
20
1.5
500
3.0
JTXV
555
TO-2OSAF
TO-39
P
20
1.5
SOO
3.0
JAN
557
TO-205AF
TO-39
P
2S
B.O
100
0.18
JTX
557
TO-205AF
TO-39
P
2S
B.O
100
0.18
JTXV
557
TO-205AF
TO-39
P
25
B.O
100
0.18
JAN
557
TO-205AF
TO-39
P
25
5.S
200
0.4
JTX
557
TO-205AF
TO-39
P
25
5.5
200
0.4
JTXV
557
TO-2OSAF
TO-39
P
25
5.5
200
0.4
JAN
557
TO-205AF
TO-39
P
25
3.0
400
1.0
2N67B4
2N6786
2N6788
2N6790
2N6792
f
2N6794
2N6796
2N6798
2N6800
l
:I
I.
:!
I'
MOTOROLA TMOS POWER MOSFET DATA
1-13-11
I
•
Motorola High Reliability Parts Pending QUAL as of JAN 1984 (Continued)
·QUAL
Status
Pr(w)
10 (A)
V(BR)OSS (V)
'OS(on)
TO-205AF
TO-39
P
25
3.0
400
1.0
557
T0-205AF
TO-39
P
25
3.0
400
1.0
2N6802 JAN
557
TO-205AF
TO-39
P
25
2.5
500
1.5
JTX
557
TO-205AF
TO-39
P
25
2.5
500
1.5
JTXV
557
TO-205AF
TO-39
P
25
2.5
500
1.5
MIL-5
Device Type
195001
Package
JTX
557
JTXV
0
*.p denotes proposed qualifications
***0 denotes qualified
MOTOROLA TMOS POWER MOSFET DATA
1-13-12
Chapter 14: Mounting Techniques For Power MOSFETs
Current and power ratings of semiconductors are inseparably linked to their thermal environment. Except for
lead-mounted parts used at low currents, a heat exchanger is required to prevent the junction temperature from
exceeding its rated limit, thereby running the risk of a high
failure rate. Furthermore, semiconductor-industry field
history indicates that the failure rate of most silicon semiconductors decreases approximately by one-half for a decrease in junction temperature from 160°C to 135°C.'
Many failures of power semiconductors can be traced
to faulty mounting procedures. With metal packaged devices, faulty mounting generally causes unnecessarily
high junction temperature, resulting in reduced component lifetime, although mechanical damage has occurred
on occasion from mountihg securely to a warped surface.
With the widespread use of various plastic-packaged semiconductors, the dimension of mechanical damage becomes very significant.
Figure 14-1 shows an example of doing nearly everything wrong. In this instance, the device to be victimized
is in the TO-220 package. The leads are bent to fit into a
socket - an operation which, if not properly done, can
crack the package, break the bonding wires, or crack the
dice. The package is fastened with a sheet-metal screw
through a '/4"-hole containing a fiber-insulating sleeve.
The force used to tighten the screw pulls the package into
the hole, causing enough distortion to crack the dice. Even
if the dice were not cracked, the contact area is small
because of the area consumed by the large hole and the
bowing of the package; the result is a much higher junction
temperature than expected. If a rough heat sink surface
and some burns around the hole are present, many but unfortunately not all - poor mounting practices are
covered.
Proper mounting procedures necessitate attention to
the following areas:
1. Mounting surface preparation
2. Application of thermal compounds
3. Installation of the insulator
4. Fastening of the assembly
5. Lead bending and soldering
In this Chapter, the procedures are discussed in general
terms. Specific details for each class of packages are
given in the figures and in Table 1. Appendix A contains
a brief review of thermal resistance concepts, and Appendix B lists sources of supply for accessories. Motorola
supplies hardware for most power packages. It is detailed
on separate data sheets for each package type.
Mounting Surface Preparation
In general, the heat-sink mounting surface should have
a flatness and finish comparable to that of the semiconductor package. In lower power applications, the heatsink surface is satisfactory if it appears flat against a
straight edge and is free from deep scratches. In highpower applications, a more detailed examination of the
surface is required.
Surface Flatness
Surface flatness is determined by comparing the variance in height (~h) of the test specimen to that of a reference standard as indicated in Figure 14-2. Flatness is
normally specified as a fraction of the Total Indicator
Reading (TIR). The mounting surface flatness, i.e. ~h/
TIR, is satisfactory in most cases if less than 4.0 mils per
inch, which is normal for extruded aluminum - although
disc type devices usually require 1.0 mil per inch.
Surface Finish
Surface finish is the average of the deviations both
above and below the mean value of surface height. For
minimum interface resistance, a finish in the range of 50
to 60 microinches is satisfactory'; a finer finish is costly
to achieve and does not significantly lower contact resistance. Most commercially available cast or extruded heat
sinks will require spotfacing when used in high-power applications. In general, milled or machined surfaces are
satisfactory if prepared with tools in good working condition.
Mounting holes generally should only be large enough
to allow clearance of the fastener. The larger packages
having mounting holes removed from the semiconductor
die location, such as TO-204AA (TO-3), may successfully
be used with larger holes to accommodate an insulating
bushing, but Thermopad plastic packages are intolerant
of this condition. For these packages, a smaller screw
size must be used such that the hole for the bushing does
not exceed the hole in the package.
Punched mounting holes have been a source of trouble
because if not properly done, the area around a punched
hole is depressed in the process. This "crater" in the heat
sink around the mounting hole can cause two problems.
Sheet Metal Screw
FIGURE 14-1 - EXTREME CASE OF IMPROPERLY MOUNTING
A SEMICONDUCTOR (DISTORTION EXAGGERATED)
In many situations the case of the semiconductors must
be isolated electrically from its mounting surface. The isolation material is, to some extent, a thermal isolator as
well, which raises junction operating temperatures. In addition, the possibility of arc-over problems is introduced if
high voltages are being handled. Electrical isolation thus
places additional demands upon the mounting procedure.
MOTOROLA TMOS POWER MOSFET DATA
1-14-1
•
•
TIR = Total Indicator Reading
~h
I
Reference Piece
Device Mounting Area
FIGURE 14-2 -
•
The device can be damaged by distortion of the package
as the mounting pressure attempts to conform it to the
shape of the heat sink indentation, or the device may only
bridge the crater and leave a significant percentage of its
heat-dissipating surface out of contact with the heat sink.
The first effect may often be detected immediately by
visible cracks in the package (if plastic), but usually an
unnatural stress is imposed, which results in an early-life
failure. The second effect results in hotter operation and
is not manifested until much later.
Although punched holes are seldom acceptable in the
relatively thick material used for extruded aluminum heat
sinks, several manufacturers are capable of properly utilizing the capabilities inherent in both fine-edge blanking
or sheared-through holes when applied to sheet metal as
commonly used for stamped heat sinks. The holes are
pierced using Class A progressive dies mounted on fourpost die sets equipped with proper pressure pads and
holding fixtures.
When mounting holes are drilled, a general practice with
extruded aluminum, surface cleanup is important. Chamfers must be avoided because they reduce heat transfer
surface and increase mounting stress. The edges should
be broken to remove burrs which cause poor contact between device and heat sink and may puncture isolation
material.
Many aluminum heat sinks are black-anodized to improve radiation ability and prevent corrosion. Anodizing
results in significant electrical but negligible thermal insulation. It need only be removed from the mounting area
when electrical contact is required. Another treated aluminum finish is iridlte, or chromate-acid dip, which offers
low resistance because of its thin surface, yet has good
electrical properties because it resists oxidation. It need
only be cleaned of the oils and films that collect in the
manufacture and storage of the sinks, a practice which
should be applied to all heat sinks. For economy, paint is
sometimes used for sinks; removal of the paint where the
semiconductor is attached is usually required because of
paint's high thermal resistance. However, when it is necessary to insulate the semiconductor package from the
heat sink, anodized or painted surfaces may be more
effective than other insulating materials which tend to
creep (i.e., they flow), thereby reducing contact pressure.
It is also necessary that the surface be free from all
SURFACE FLATNESS
foreign material, film, and oxide (freshly bared aluminum
forms an oxide layer in a few seconds). Unless used immediately after machining, it is a good practice to polish
the mounting area with No. 000 steel wool, followed by
an acetone or alcohol rinse. Thermal grease should be
immediately applied thereafter and the semiconductor attached as the grease readily collects dust and metal particles.
Thermal Compounds
To improve contacts, thermal joint compounds or
greases are used to fill air voids between all mating surfaces. Values of thermal resistivity vary from 0.1 OCC-inlW
for copper film to 1200cC-inlW for air, whereas satisfactory
joint compounds will have a resistivity of approximately
60cC-inlW. Therefore, the voids, scratches, and imperfections which are filled with a joint compound, will have
a thermal resistance of about 1/20th of the original value
which makes a significant reduction in the overall interface
thermal resistance.
Joint compounds are a formulation of fine zinc particles
in a silicon oil which maintains a grease-like consistency
with time and temperature. Since some of these compounds do not spread well, they should be evenly applied
in a very thin layer using a spatula or Iintless brush, and
wiped lightly to remove excess material. Some cyclic rotation of the package will help the compound spread
evenly over the entire contact area. Experience will indicate whether the quantity is suffiCient, as excess will appear around the edges of the contact area. To prevent
accumulation of airborne particulate matter, excess compound should be wiped away using a cloth moistened with
acetone or alcohol. These solvents should not contact
plastic-encapsulated devices, as they may enter the package and cause a leakage path or carry in substances
which might attack the assembly.
Data showing the effect of compounds on several package types under different mounting conditions is shown
in Table 1. The rougher the surface, the more valuable
the grease becomes in lowering contact resistance; therefore, when mica insulating washers are used, use of
grease is generally mandatory. The joint compound also
improves the breakdown rating of the insulator and is
therefore highly desirable despite the handling problems
'Tests run by Thermalloy (Catalog #74-INS-3. page 14) using a copper TO·204AA (T()'3) package with a typical 32-mlcrolnch finish. showed that finishes between
16 and 64 win caused less than ± 2.5% difference in interface thermal resistance.
MOTOROLA TMOS POWER MOSFET DATA
1-14-2
TABLE 1 -
Approximate Values for Interface Thermal Resistance and Other Package Data
(See Table 2 for Case Number to JEDEC Outline Cross-Reference)
Dry interface values are subject to wide variation because of extreme dependence upon surface conditions. Unless othelWise noted the case temperature
is monitored by a thermocouple located directly under the die reached through a hole in the heat sink. (See Note 3)
~
Package Type and Data
Interlace Thermal Resistance ("CIW)
Metal-to-Metal
With Insulator
Description
Recommended
Mounting Hole
and Drill Size
Machine
Screw Size2
Torque
In-Lb
Dry
Lubed
Dry
Lubed
Type
Note
TO-204AA
Diamond Flange
0.140, #28
6-32
6.0
0.5
0.2
1.3
0.36
3mi!
Mica
1
TO-213AA
Diamond Flange
0.140, #28
6-32
6.0
1.5
0.5
2.3
0.9
2mi!
Mica
TO-218AC
5/8" x 1/2"
0.140, #28
6-32
6.0
0.75
0.40
1.60
0.7
2mil
Mica
TO-220AB
Thermowatt
0.140, #28
6-32
B.O
1.2
1.0
3.4
1.6
2 mil
Mica
TO-225AA
Thermopad
0.113, #33
4-40
6.0
2.0
1.3
4.3
3.3
2 mil
Mica
JEDEC
Outline
See
1/4" x 3/8"
Note 1:
1,2
See Figures 14-3 and 14-4 for additional data on To-204AA and TO-220 packages.
Note 2: Screw not insulated.
Note 3: Measurement of Interface Thermal Resistance. Measuring the lnterface thermal resistance R8CS appears deceptively slmple. All that's apparently needed is a
thermocouple on the device, a thermocouple on the heat sink. and a means 01 applying and measuring de power. However. Recs is proportional to the amount of contact
area between the surfaces and consequently is affected by the surface flatness and finish and the amount of pressure on the surfaces. In addition, placement of the
thermocouples can have a significant influence upon the results. Consequently, values for intertace thermal resistance presented by different manufacturers are in poor
agreement.
created by its affinity for foreign matter. Some sources of
supply for joint compounds are shown in Appendix B.
Some users and heat-sink manufacturers prefer not to
use compounds. This necessitates use of a heat sink with
lower thermal resistance which imposes additional cost,
but which may be inconsequential when low power is
being handled. Others design on the basis of not using
grease, but apply it as an added safety factor, so that if
improperly applied, operating temperatures will not exceed the design values.
Consider the TO-220 package shown in the accompanying figure. The mounting pressure at one end causes
the other end - where the die is located - to lift off the
mounting surface slightly.
The thermocouple locations are shown:
a. The Motorola location is directly under the die
reached through a hole in the heat sink. The thermocouple
is held in place by a spring which forces the thermocouple
into intimate contact with the bottom of the semi's case.
b. The EIA location is close to the die on the top surface
of the package base reached through a blind hole drilled
through the molded body. The thermocouple is swaged
in place.
c. The Thermalloy location is on the top portion of the
tab between the molded body and the mounting screw.
The thermocouple is soldered into position.
Temperatures at the three locations are generally not
the same. Consider the situation depicted in the figure.
Because the only area of direct eontact is around the
mounting screw, nearly all the heat travels horizontally
along the tab from the die to the contact area. Conse-
quently, the temperature at the EIA location is hotter than
at the Thermalloy location and the Motorola location is
even hotter. Since junction-to-sink thermal resistance is
constant for a given setup, junction-to-case values decrease and case-to-sink values increase as the case thermocouple readings become warmer.
There are examples where the relationship between the
thermocouple temperatures are different from the previous situation. If a mica washer with grease is installed
between the semiconductor package and the heat sink,
tightening the screw will not bow the package; instead,
the mica will be deformed. The primary heat conduction
path is from the die through the mica to the heat sink. In
this case, a small temperature drop will exist across the
vertical dimension of the package mounting base so that
the thermocouple temperature at the Thermalloy location
could be close to the temperature at the EIA location as
the lateral heat flow is generally small.
The EIA location is chosen to obtain the highest temperature on the case. It is of significance because power
ratings are supposed to be based on this reference point.
Unfortunately, the placement of the thermocouple is tedious and leaves the semiconductor in a condition unfit
for sale.
The Motorola location is chosen to obtain the higher
temperature of the case at a point where, hopefully, the
device is making contact to the heat sink, since heat sinks
are measured from the point of device contact to the ambient. Once the special heat sink to accommodate the
thermocouple has been fabricated, this method lends itself
to production testing and does not mark the device. How-
MOTOROLA TMOS POWER MOSFET DATA
1-14-3
•
TABLE 2 - Cross Reference Chart
Motorola Case Number to JEDEC
Outline Number and Table 1 Reference
E.I.A.
Motorola
ever, this location is not easily accessible to the user.
The Thermalloy location is convenient and is often chosen by equipment manufacturers. However, it also blemishes the case and may yield results differing up to
1.0°C/W for a TO-220 package mounted to a heat sink
without thermal grease and no insulator. This error is small
when compared to the heat dissipators often used with
this package, since power diSSipation is usually a few
watts. When compared to the specified junction-to-case
values of some of the higher power semiconductors becoming available, however, the difference becomes significant, and it is important that the semiconductor manufacturer and equipment manufacturer use the same
reference point.
Another method of establishing reference temperatures
utilizes a soft copper washer (thermal grease is used)
between the semiconductor package and the heat sink.
The washer is flat to within 1.0 mil/inch, has a finish better
than 63 winch, and has an imbedded thermocouple near
its center. This reference includes the interface resistance
under nearly ideal conditions and is therefore applicationoriented. It is also easy to use and yields reproducible
results. At this printing, however, sufficient data to compare results to other methods is not available.
The only way to get accurate measurements of the
interface resistance is to also test for junction-to-case thermal resistance at the same time. If the junction-to-case
values remain relatively constant as insulators are
changed, torque varied, etc., then the case reference point
is satisfactory.
Motorola
Number
JEDEC
Number
Reference in
Table 1
1
TO-204M
TO-204M
77
TO-225M
TO-225M
BO
TO-213M
TO-213M
197
TO-204AE
TO-204AE
221A
TO-220AB
TO-220AB
340
TO-21BAC
TO-21BAC
where a chassis serves as a heat sink or where a heat
sink is common to several devices, insulators are used to
isolate the individual components from the heat sink.
When an insulator is used, thermal grease assumes
greater importance than with a metal-to-metal contact,
because two interfaces exist instead of one and some
materials, such as mica, have a markedly uneven surface.
Reduction of interface thermal resistance of between 2 to
1 and 3 to 1 are typical when grease is used.
Data obtained by Thermalloy, showing interface resistance for different insulators and torque applied to TO204AA and TO-220 packages, are shown in Figure 14-3
for bare surfaces and Figure 14-4 for greased surfaces.
It is obvious that with some arrangements, the interface
thermal resistance exceeds that of the semiconductor
(junction to case). When high power is handled, beryllium
oxide is unquestionably the best choice. Thermafilm is
Thermalloy's trade name for a polyimide material which
is also commonly known as Kapton; this material is fairly
popular for low power applications because it is low cost,
withstands high temperatures and is easily handled, in
contrast to mica which chips and flakes easily.
When using insulators, care must be taken to keep the
mating surfaces clean. Small particles of foreign matter
can puncture the insulation, rendering it useless or seriously lowering its dielectric strength. In addition, particularly when voltages higher than 300 V are encountered,
problems with creepage may occur. Dust and other foreign
material can shorten creepage distances significantly so
that having a clean assembly area is important. Surface
roughness and humidity also lower insulation resistance.
Use of thermal grease usually raises the breakdown voltage of the insulation system. Because of these factors,
which are not amenable to analYSiS, high potential testing
should be done on prototypes and a large margin of safety
employed. In some situations, it may be necessary to
substitute "empty" packages for the semiconductor to
avoid shorting them or to prevent the semiconductors from
limiting the voltage applied during the hi-pot test.
Insulation Considerations
Since it is most expedient to manufacture power MOSFETs with drains electrically common to the case, the
problem of isolating this terminal from ground is a common
one. For lowest overall thermal resistance, it is best to
isolate the entire heat sink/semiconductor structure from
ground, rather than to use an insulator between the semiconductor and the heat sink. Where heat sink isolation is
not pOSSible, because of safety reasons or in instances
MOTOROLA TMOS POWER MOSFET DATA
1-14-4
(aITO-3
8
!,11,\ 1-
II
Thermalfilm, 0.002"-....
~
z
~
~jtJ~:~eU;u~:~~~o~o~~:',/
....
BeryJimm OXide. 0.062"
~
~
..--- 250 PSI
0.6
--
(al TO-3
r--
-
V~ilicone, RUbber.l
Thermalfilm 11,0.0112"_
Thermal1film 1,0.~02"-
~
No Insulator
2
~
~
/'
6
0.8
w
~
Mica, 0.003""
Hard Anodize, 0.020"/
~
IInterface Pressure
500 PSI - - -
""z
5
~
/
0.4
Hard Anodize, 0.020"-
Beryllium Oxide, 0.062"
No Insu(ator
t-0.2
_250 PSI
0
MOUNTING SCREW TORQUE (IN-L8S)
Mica, 0.003" ,I,
~~IUmjn~m OXide"D.062"
'"
Interface Pressure
I
500 P S I -
MOUNTING SCREW TORQUE (IN·LBS)
(bl TO-220AB
(bl TO-220AB
2.5
Thermalfilm:;.....
/"""
Thermalfilm I
~
~ 2.0
---..:
/'
Mica, 0.003"/
//
Mica, ~.002" ....
Hard AtOdlze
p....
!-- Mica, 0.003"
~
~
,; Mica, 0.002"
~
.", Hard AnodIZe
~ 1.5
....
'"
No Insulator
~ 1.0
No Insulator/
I
~
....
~
0.5
2
MOUNTING SCREW TORQUE (IN-L8S)
MOUNTING SCREW TORQUE (IN·L8S)
FIGURE 14-3 - INTERFACE THERMAL RESISTANCE
WITHOUT THERMAL GREASE AS A FUNCTION OF
MOUNTING SCREW TORQUE USING VARIOUS
INSULATING MATERIALS
FIGURE 14-4 - INTERFACE THERMAL RESISTANCE
USING THERMAL GREASE AS A FUNCTION OF
MOUNTING SCREW TORQUE USING VARIOUS
INSULATING MATERIALS
in mounting the various packages. Since many problems
have arisen because of improper choices, the basic characteristics of several types of hardware are discussed
next,
Motorola washers designed for use with the Thermopad
package maintain the proper force when properly secured.
They are used with the large face contacting the packages.
Compression Washers
Machine Screws
A very useful piece of hardware is the bell-type
compression washer. As shown in Figure 14-5, it has the
ability to maintain a fairly constant pressure over a wide
range of physical deflection - generally 20% to 80% thereby maintaining an optimum force on the package.
When installing, the assembler applies torque until the
washer depresses to half its original height. (Tests should
be run prior to setting up the assembly line to detennine
the proper torque for the fastener used to achieve 50%
deflection,) The washer will absorb any cyclic expansion
of the package or insulating washer caused by temperature changes, Bell type washers are the key to successful
mounting of devices requiring strict control of the mounting
force or when plastic hardware is used in the mounting
scheme.
Machine screws and nuts form a trouble-free fastener
system for all types of packages which have mounting
holes. Torque ratings apply when dry; therefore, care must
be exercised when using thermal grease to prevent it from
getting on the threads as inconsistent torque readings
result. Machine screw heads should not directly contact
the surface of any of the Thermopad plastic package types
as the screw heads are not sufficiently flat to provide
properly distributed force.
Self-Tapping Screws
Under some conditions, sheet-metal screws are acceptable. However, during the tapping process with a
standard screw, a volcano-like protrusion will develop in
MOTOROLA TMOS POWER MOSFET DATA
1-14-5
•
a
280
240
TO-127
~ 200
/'
1/
I
I,
w
80
0.
40
~
TO-126
.../'
160
~
~ 120
o
'"
/
~
~
Manufacturers which provide heat sinks for general use
and other associated hardware are listed in Appendix B_
Manufacturer's catalogs should be consulted to obtain
more detailed information. Motorola also has mounting
hardware available for a number of different packages .
Consult the Hardware Data Sheet for dimension of the
components and part numbers.
Specific fastening techniques are discussed in the
remainder of this section for the following categories of
semiconductor packages.
L
./
~
/I
II
I
o
o
20
40
60
80
1. Flange Mount: TO-204AA, TO-204AE,
TO-213AA.
2. Plastic Packages: TO-218AC, TO-220AB,
TO-225AA, TO-225AB.
100
DEFLECTION OF WASHER DURING MOUNTING 1%)
FIGURE 14-5 - CHARACTERISTICS OF THE BELL
COMPRESSION WASHERS DESIGNED FOR USE WITH
THERMOPAD SEMICONDUCTORS
Flange Mount
Few known mounting difficulties exist with this type of
package. The rugged base and distance between dice
and mounting holes combine to make it extremely difficult
to cause any warpage unless mounted on a surface which
is badly bowed or unless one side is tightened excessively
before the other screw is started. A typical mounting installation is shown in Figure 14-6. Machine screws, selftapping screws, eyelets, or rivets may be used to secure
the package.
Fastener and Hardware Characteristics
Characteristics of fasteners, associated hardware, and
the tools to secure them determine their suitability for use
the metal being threaded; a very unsatisfactory surface
results. When used, a speed-nut must be used to secure
a standard screw, or the type of screw must be used which
rOil-forms machine screw threads.
Eyelets
Successful mounting can also be accomplished with
hollow eyelets provided an adjustable, regulated pressure
press is used such that a gradually increasing pressure
is used to pan the eyelet. Use of sharp blows could damage the semiconductor die.
Thermopad: TO-225AA and TO-225AB
The Motorola Thermopad plastic power packages have
been designed to feature minimum size with no compromise in thermal resistance. This is accomplished by diebonding the silicon chip on one side of a thin copper sheet;
the opposite side is exposed as a mounting surface. The
copper sheet has a hole for mounting, i.e., plastic is
molded enveloping the chip but leaving the mounting hole
open. The benefits of this construction are obtained at the
expense of a requirement that strict attention be paid to
the mounting procedure. Success in mounting Thermopad
devices depends largely upon using a compression
washer which provides a controllable pressure across a
large bearing surface. Having a small hole with no chamfer
and a flat, burr-free, well-finished heat sink are also important requirements.
Several types of fasteners may be used to' secure the
Thermopad package; machine screws, eyelets, or clips
are preferred. With screws or eyelets, a bell compression
washer should be used which applies the proper force to
the package over a fairly wide range of deflection. Screws
should not be tightened with any type of air,-driven torque
gun or equipment which may cause high impact. Characteristics of the recommended washers are shown in
Figure 14-5.
Figure 14-7 shows details of mounting TO-225AA and
TO-225AB devices. Use of the clip requires that caution
be exercised to insure that adequate mounting force is
applied. When electrical isolation is required, a bushing
inside the mounting hole will insure that the screw threads
do not contact the metal base.
Rivets
When a metal flange-mount package is being mounted
directly to a heat sink, rivets can be used. Rivets are not
a recommended fastener for any of the plastic packages
except for the tab-mount type. Aluminum rivets are preferred over steel because less pressure is required to set
the rivet and thermal conductivity is improved.
Insulators and Plastic Hardware
Because of its relatively loW cost and low thermal resistance, mica is still widely used to insulate semiconductor packages from heat sinks despite its tendency to
chip and flake. It has a further advantage in that it does
not creep or flow so that the mounting pressure will not
reduce with time in use. Plastic materials, particularly Teflon, will flow. When plastiC materials form parts of the
fastening system, a compression washer is a valuable
addition which assures that the assembly will not loosen
with time.
-
Fastening Techniques
Each of the various types of packages in use requires
different fastening techniques. Details pertaining to each
type are discussed in the following sections. Some general considerations follow.
To prevent galvanic action from occurring when devices
are used on aluminum heat sinks in a corrosive atmosphere, many devices are nickel- or gOld-plated. Consequently, precautions must be taken not to mar the finish.
MOTOROLA TMOS POWER MOSFET DATA
1-14-6
tt--
Eyelet
Compression Washer
Heat Sink
Thermopad Package
=
~
Mica Washer
(Optional)
Mica Washer (Optional)
Spring Lock Washer
Machine or Speed
Nut
(a) Machine Screw Mounting
(b) Eyelet Mounting
r
~
Part C52825-01 1
PartsC50272·011andC51451-011
Material: Heat-Treated Spring
Steel 0.011 Thickness
~
Materiel : Heat-Treated Spring
Steel 0.011 Thickness
0.500
TO-225A8 Clip
FIGURE 14-6 -
Range
{el Tinnarrn8n Clips {Eaton Corp.1
TO-225M Clip
RECOMMENDED MOUNTING ARRANGEMENTS FOR T()'225M (T()'l26)
Thermowatt: T0-220
The popular TO-220 Thermowatt package also requires
attention to mounting details. Figure 14-8 shows suggested mounting arrangements and hardware. The rectangular washer shown in Figure 14-8a is used to minimize distortion of the mounting flange; excessive
distortion could cause damage to the semiconductor Chip.
Use of the washer is only important when the size of the
mounting hole exceeds 0.140 inch (6-32 clearance).
Larger holes are needed to accommodate insulating bushings when the screw is electrically connected to the case;
however, the holes should not be larger than necessary
to provide hardware clearance and should never exceed
a diameter of 0.250 inch. Flange distortion is also possible
if excessive torque is used during mounting. A maximum
torque or 8 inch-pounds is suggested when using a 6-32
screw.
Care should be exercised to assure that the tool used
to drive the mounting screw never comes in contact with
the plastic body during the driving operation. Such contact
can result in damage to the plastiC body and internal device connections. To minimize this problem, Motorola TO220 packages have a chamfer on one end. TO-220 packages of other manufacturers may need a spacer or combination spacer and isolation bushing to raise the screw
head above the top surface of the plastiC.
In situations where the Thermowatt package is making
direct contact with the heat sink, an eyelet may be used,
provided sharp blows or impact shock is avoided.
Mounting T0-218AC
Non-isolated and isolated mounting hardware and procedures are shown in Figure 14-9. Generally, the precautions listed for the TO-220AB package are applicable to
the TO-218AC package.
MOTOROLA TMOS POWER MOSFET DATA
1-14-7
•
~
a) Preferred Arrangement
for Isolated or Non-isolated
Mounting. Screw is at Semiconductor Case Potential.
6-32 Hardware is Used.
b) Alternate Arrangement
for Isolated Mounting
when Screw must be at
Heat Sink Potential.
4-40 Hardware is Used.
Choose from Parts Listed
Below.
Use Parts Listed Below.
..
~
_ _ 4-40 Hex Head Screw
..
6-32 Hex .....Head Screw
I!
6-32 Hex Head
Screw
--~
1) _ _
I
___
22\2C:2=l::::~=)=*I=I:='~~
.-Jt-->
!
I
",
'\.
Heat Sink
Retangular
Mica Insulator
"c=J I,
L1!:rl
L,
~~l.L.,i"'--"r
Heat Sink
or
Chas~s
(1)
/'
Compression Washer
/'
i
1
I
!
\-r====»
I
r
=='C:~i=:C:======:;:'='
CI
(1) Used with thin chassis andlor large hole.
(2) Used when isolation is required.
(3) Required when nylon bushing and lock washer are used.
(4) Compression washer preferred when plastic insulating
material is used.
Torque Requirements
LJii
Compression
Nut or
Lock Washer
r'
I
Free Air Power DiSSipation
Frequently it is asked, "What is the maximum power
dissipation capability of a particular semiconductor package without heat sinking?" The question arises more often
for plastic encapsulated packages than for metal ones.
Unfortunately, there is no exact maximum power dissipation for any semiconductor package without known heat
sinking properties.
Power dissipation capability of a semiconductor is
based upon the maximum junction temperature specification.
/
Compression Washer
/
-\L.-Li_...i --'{
I
6-32 Hex Nut -
( T
I
~
) _ _ _ _ 4-40 Hex Nut
L..,A..c...-:-"".6.~.
-
I
I
Torque Requirements
0.68 NM (6 in.llbs.) max.
Recommended Torque: 0.57 Nm/5 in.llbs. - 5.5 kg/em.
Insulated 0.68 N-M (6 in-Ibs) max
Noninsulated 0.9 N-M (8 in-Ibs) max
FIGURE 14-7 - MOUNTING ARRANGEMENTS FOR
THERMOWATT PACKAGES (10-220)
Standard
Mica Insulator
FlatWash~
4-40 Hex Nut
"- U: , OX)----
•
I
I
'\.
====~
6-32 Hex Nut
I
~
Heat Sink
(3)Flat Washer
(4)Compression,
or Lock Washer
~
Motorola
Semiconductor
Case 340-01
TO-218AC
'\.
I
~ :I !
,.", I
Standard
r -;---'--..,---, _ _ Nylon Insulating Bushing
(2)Rectangular Mica
Insulator
:
(2)Nylon Bushing
4-40 Hex Head Screw
I
semicondu~or: ! : I ~f---------.,
(Case
r
I
Semiconductor
(Case 221, 221A)
I
..
Insulating Mounting
From Screw
I,
I
Nylon Insulating Bushing
~/
(l)Rectangular Steel!
Washer
\
..
Non-Isolated
Mounting
(1) Use with Lock Washer
FIGURE 14-B -
MOUNTING METHODS FOR TO-21BAC PACKAGE
Typical junction-to-ambient (ROJA) thermal resistance
values and the resulting power dissipation capability is
shown in Table 3 for some popular package types. These
values are typical when there is no heat sink attached to
the case. Obviously, electrical connections have to be
made to the package and this is one of the several variables.
There are seven factors which determine the power
dissipation capability of a given package and they are:
Attachment, Power Dissipation, Package Orientation, Still
Free Air, Ambient Temperature, Lead Length (if applicable), and TJ(max).
MOTOROLA TMOS POWER MOSFET DATA
1-14-8
One of the chief variables is mounting attachments. For
maximum power dissipation, it is helpful if the electrical
connection to the terminal which will permit the greatest
heat removal be as massive as possible. For a metal
package, it would be the case and for a plastic package
lead mounted, it would be the drain lead for a power
MOSFET.
small heat sink, it is good practice to have the sink rigidly
mounted such that the sink or the board is providing total
support for the semiconductor. Two possible arrangements are shown in Figure 14-9. The arrangement of part
(a) could be used with any plastic package, but the
scheme of part (b) is more practical with Case 77. With
the other package types, mounting the transistor on top
of the heat sink is more practical.
In certain situations, in particular where semiconductor
testing is required, sockets are desirable. Manufacturers
have provided sockets for all the packages available from
Motorola. The user is urged to consult manufacturers'
catalogs for specific details.
Free Air and Socket Mounting
In applications where average power dissipation is of
the order of a watt or so, power semiconductors may be
mounted with little or no heat sinking. The leads of the
various metal power packages are not designed to support the packages; their cases must be firmly supported
to avoid the possibility of cracked glass-to-metal seals
around the leads. The plastic packages may be supported
by their leads in applications where high shock and vibration stresses are not encountered and where no heat sink
is used. The leads should be as short as possible to
increase vibration resistance and reduce thermal
resistance.
In many situations, because its leads are fairly heavy,
the TO-225AB package has supported a small heat sink;
however, no definitive data is available. When using a
Handling Pins, Leads, and Tabs
The pins and lugs of metal-packaged devices are not
designed for any bending or stress. If abused, the glassto-metal seals could crack. Wires may be attached using
sockets, crimp connectors, or solder, provided the data
sheet ratings are observed.
The leads and tabs of the plastic packages are more
flexible and can be reshaped, although this is not a recommended procedure for users to do. In some cases, a
heat sink can be chosen which makes lead-bending unnecessary. Numerous lead- and tab-forming options are
available from Motorola. Preformed leads remove the risk
of device damage caused by bending from the users.
If, however, lead-bending is done by the user, several
basic considerations should be observed. When bending
the lead, support must be placed between the point of
bending and the package. For forming small quantities of
units, a pair of pliers may be used to clamp the leads at
the case, while bending with the fingers or another pair
of pliers. For production quantities, a suitable fixture
should be made.
The following rules should be observed to avoid damage to the package.
Thermopad
Heat Sink Surface
Twist Locks
or
Solderable
Legs
(0) Simple Plate. Vertically Mounted
Heat Sink
Circuit Board
1. A lead-bend radius greater than 1/16 inch's advisable for the TO-225AA and 1/32 inch for -,0-220.
2. No twisting of leaels should be done at the case.
3. No axial motion of the lead should be allowed with
respect to the case.
The leads of plastic packages are not designed to withstand excessive axial pull. Force in this direction greater
than four pounds may result in permanent damage to the
device. If the mounting arrangement imposes axial stress
on the leads, a condition which may be caused by thermal
cycling, some method of strain relief should be devised.
An acceptable lead-forming method that provides this relief is to incorporate an S-bend into the lead. Wire wrapping of the leads is permissible, provided that the lead is
restrained between the plastic case and the point of the
wrapping. The leads may be soldered; the maximum soldering temperature, however, must not exceed 275°C and
must be applied for not more than five seconds at a distance greater than 1/8 inch from the plastic case. When
wires are used for connections, care should be exercised
to assure that movement of the wire does not cause movement of the lead-to-plastic junctions.
Circuit Board
(b), Commercial Sink. Horizontally Mounted
RGURE 14-9 - METHODS OF USING SMALL HEAT SINKS
WITH PLASTIC SEMICONDUCTOR PACKAGES
MOTOROLA TMOS POWER MOSFET DATA
1-14-9
•
•
Cleaning Circuit Boards
. It is important that any solvents or cleaning chemicals
used in the process of degreasing or flux removal do not
affect the reliability of the devices.
Alcohol and unchlorinated Freon solvents are generally
satisfactory for use with plastic devices, since they do not
damage the package. Hydrocarbons such as gasoline
may cause the encapsulant to swell, possibly damaging
the transistor die. Ukewise, chlorinated Freon solvents are
unsuitable, since they may cause the outer package to
dissolve and swell.
When using an ultrasonic cleaner for cleaning circuit
boards, care should be taken with regard to ultrasonic
energy and time of application. This is particularly true if
the packages are free-standing without support.
Thermal System Evaluation
Assuming that a suitable method of mounting the semiconductor without incurring damage has been achieved,
it is important to ascertain whether the junction temperature is within bounds.
In applications where the power dissipated in the semiconductor consists of pulses at a low duty cycle, the instantaneous or peak junction temperature, not average
temperature, may be the limiting condition. In this case,
use must be made of transient thermal resistance data.
For a full explanation of its use, see Motorola Application
Note, AN-569.
Other applications including switches driving highly reactive loads, may create severe current crowding conditions which render the traditional concepts of thermal resistance or transient thermal impedance invalid. In this
case, transistor safe operating area must be observed.
Fortunately, in many applications, a calculation of the
average junction temperature is sufficient. It is based on
the concept of thermal resistance between the junction
and a temperature reference point on the case. (See Appendix A) A fine thermocouple should be used, such as
#32AWG, to determine case temperature. Average operating junction temperature can be computed from the
TABLE 3 -
following equation:
TJ = TC + R6JC x Po
where
TJ = junction temperature (0C)
T C '7 case temperature (OC)
R6JC = thermal resistance junction-to-case as
specified on the data sheet rCIW)
Po = power dissipated in the device (W).
The difficulty in applying the equation often lies in determining the power dissipation. Two commonly used empirical methods are graphical integration and substitution.
Graphical Integration
Graphical integration may be performed by taking oscilloscope pictures of a complete cycle of the voltage and
current waveforms, using a limit device. The pictures
should be taken with the temperature stabilized. Corresponding points are then read from each photo at a suitable number of time increments. Each pair of voltage and·
current values are multiplied together to give instantaneous values of power. The results are plotted on linear
graph paper, the number of squares within the curve
counted, and the total divided by the number of squares
along the time axis. The quotient is the average power
dissipation.
Substitution
This method is based upon substituting an easily measurable, smooth dc source for a complex waveform. A
switching arrangement is provided which allows operating
the load with the device under test, until it stabilizes in
temperature. Case temperature is monitored. By throwing
the switch to the "test" position, the device under test is
connected to a dc power supply, while another pole of the
switch supplies the normal power to the load to keep it
operating at full power level. The dc supply is adjusted so
that the semiconductor case temperature remains approximately constant when the switch is thrown to each
poSition for about 10 seconds. The dc voltage and current
values are multiplied together to obtain average power. It
is generally necessary that a Kelvin connection be used
for the device voltage measurement.
Typical Junction-to-Ambient Thermal Resistance and Typical Power Dissipation
for Various Transistor Packages Without Heat Sinking
Without Heat Sink in Free Air
•
Motorola
Case Number
JEDEC
Number
Typical
R9JA (OCIW)
Typical Power
Dissipation (Watts)
1
TO-204M
50
3.5
77
TO-225M
83
1.5
80
TO-213M
60
2.9
197
TO-204AE
50
3.5
221A
TO-220AB
62
2.0
340
TO-218AC
45
2.8
MOTOROLA TMOS POWER MOSFET OATA
1-14-10
APPENDIX A
The equivalent electrical circuit may be analyzed by
using Kirchoff's Law and the following equation results:
THERIII!AL RESISTANCE CONCEPTS
The basic equation for heat transfer under steady-state
conditions is generally written as:
q = hMT
(1)
where
where
q = rate of heat transfer or power dissipation
(PO),
h = heat transfer coefficient,
A = area involved in heat transfer,
~ T = temperature difference between regions
of heat transfer.
However, electrical engineers generally find it easier to
work in terms of thermal resistance, defined as the ratio
of temperature to power. From Equation 1, thermal resistance, RO, is
RO = ~T/q = 1/hA
(2)
The coefficient (h) depends upon the heat transfer mechanism used and various factors involved in that particular
mechanism.
An analogy between Equation (2) and Ohm's Law is
often made to form models of heat flow. Note that ~T
could be thought of as a voltage; thermal resistance corresponds to electrical resistance (R); and, power (q) is
analogous to current (I). This gives rise to a basic thermal
resistance model for a semiconductor as indicated by Figure A1.
TJ = PO(RruC + RoeS + ROSA) + TA
(3)
TJ = junction temperature,
Po = power dissipation,
R8JC = semiconductor thermal resistance
Ounction to case),
RoeS = interface thermal resistance (case to
heat sink),
ROSA = heat sink thermal resistance (heat
sink to ambient),
TA = ambient temperature.
The thermal resistance junction to ambient is the sum
of the individual components. Each component must be
minimized if the lowest junction temperature is to result.
The value for the interface thermal reSistance, RoeS, is
affected by the mounting procedure and may be significant compared to the other thermal-resistance terms.
The thermal resistance of the heat sink is not constant;
it decreases as ambient temperature increases and is
affected by orientation of the sink. The thermal resistance
of the semiconductor is also variable; it is a function of
biasing and temperature. In some applications such as in
RF power amplifiers and short-pulse applications, the concept may be invalid because of localized heating in the
semiconductor chip.
Plastic Package
T J. Junction Temperature
~
Te, Ca. Temperature
.----=-.,
~
Roes
TS. Heat Sink _ _
Temperature
TA.Ambient~
Temperature
J
Reference Temperature
FIGURE A1 - BASIC THERMAL RESISTANCE MODEL SHOWING THERMAL TO ELECTRICAL ANALOGY FOR A SEMICONDUCTOR
•
MOTOROLA TMOS POWER MOSFET OATA
1-14-11
APPENDIX B
SUPPLIERS ADDRESSES
Aavid Engineering, Inc., 30 Cook Court, Laconia, New
Hampshire 03246
(603) 524-4443
AHAM Heat Sinks, 27901 Front Street, Rancho, California
92390
(714) 676-4151
Astrodyne, Inc., 353 Middlesex Avenue, Wilmington,
Massachusetts 01887
(617) 272-3850
Delbert Blinn Company, P.O. Box 2007, Pomona, California 91766
(714) 623-1257
Dow Corning, Savage Road Building, Midland, Michigan
48640
(517) 636-8000
Dayton Corporation, Engineered Fasteners Division,
Tinnerman Plant, P.O. Box 6688, Cleveland, Ohio 44101
(216) 523-5327
Emerson &Cuming, Inc., Dielectric Materials Division, 869
Washington Street, Canton, Massachusetts 02021
(617) 828-3300
International Electronics Research Corporation, 135 West
Magnolia Boulevard, Burbank, California 91502
(213) 849-2481
The Staver Company, Inc., 41-51 North Saxon Avenue,
Bay Shore, Long Island, New York 11706
(516) 666-8000
Thermalloy, Inc., P.O. Box 34829, 2021 West Valley View
Lane, Dallas, Texas 75234
(214) 243-4321
Tor Corporation, 14715 Arminta Street, Van Nuys,
California 91402
(213) 786-6524
Tran-tec Corporation, P.O. Box 1044, Columbus,
Nebraska 68601
(402) 564-2748
Wakefield Engineering, Inc., Wakefield, Massachusetts
01880
(617) 245-5900
Wei Corporation, 1405 South Village Way, Santa Ana,
California 92705
(614) 834-9333
SOURCES OF ACCESSORIES
Insulators
Manufacturer
Aavid Eng.
AHAM
Astrodyne
Delbert Blinn
Ther·o·link 1000
-
-
-
-
X
-
-
-
Tran-tec
Wakefield Eng.
Wei Corp.
-
-
X
X
-
X
-
-
-
X
-
-
X
X
-
-
X
X
X
X
X
-
X
X
X
X
X
X
-
-
-
-
X
TJC
X
-
XL500
X
-
Type 120
X
-
-
RF
Strlpllne
-
X
-
UnttiDuo
Wall
-
Thermacote
-
Stud Flange Disc Thermowall
-
-
Thermat.
Silicone
Rubber
-
- -
IERC
Tor
- - -
#829
Staver
Thermalloy
Heat Sinks
Plastic
Joint Compound &eO AI02 Anodize Mica Film
-
-
-
X
X
-
X
X
X
-
X
-
X
X
X
X
-
X
X
-
X
X
X
X
X
X
X
X
X
-
X
X
-
X
-
-
-
-
X
X
X
X
X
X
X
X
X
-
-
-
X
X
X
l(
X
-
-
X
X
-
-
-
Other sources for JOint Compounds: Dow Coming. Type 340
Emerson & Cuming. Eccoshield - SO (Electrically Conducting)
Emerson & Cuming. Eccothenn - TC-4 (Electrically Insulating)
MOTOROLA TMOS POWER MOSFET DATA
1-14-12
-
-
Chapter 15: Electrostatic Discharge and Power MOSFETs
TABLE 3 -
One of the major problems plaguing electronics components today is damage by electrostatic discharge
(ESD). ESD can cause degradation or complete component failure. Shown in Table 1 are the susceptibility
ranges of various devices to ESD. As circuitry becomes
more complex and dense, device geometries shrink, making ESD a major concern of the electronics Industry.
Electrostatic Voltages
Electrostatic potential is a function of the separation of
non-conductors on the list of materials known as the Triboelectric Series. (See Table 2.) Additional factors in
charge generation are the intimacy of contact, rate of separation and humidity, which makes the material surfaces
partially conductive. Whenever two non-conductive materials are flowing or moving with respect to each other,
an electrostatic potential is generated.
Device Type
Range of ESD
Susceptibility (Volts)
100-200
JFET
140-10,000
CMOS
250-2,000
Schottky Diodes, TTL
300-2,500
Bipolar Transistors
380-7,000
ECl
500
SCR
680-1,000
Air
Human Skin
Glass
Human Hair
Wool
Fur
Paper
Cotton
Wood
Hard Rubber
Acetate Rayon
Polyester
Polyurethane
PVC (Vinyl)
Teflon
65 to 90
Percent
Relative
Humidity
Walking across carpet
35,000
1,500
Walking over vinyl floor
12,000
250
Worker at bench
6,000
100
Vinyl envelopes per
work instructions
7,000
600
Common poly bag
picked up from bench
20,000
1,200
Work chair padded with
polyurethane foam
18,000
1,500
Susceptibility to ESD
Power MOSFET
TABLE 2 -
10 to 20
Percent
Relative
Humidity
Means of
Static Generation
Generation of ESC
TABLE 1 -
Typical Electrostatic Voltages
From the Tables, it is apparent that sensitive electronic
components can be easily damaged or destroyed if precautions are not taken.
ESD and Power MOSFETs
Being MOS devices, TMOS transistors can be damaged
by ESD due to improper handling or installation. However,
TMOS devices are not as susceptible as CMOS. Due to
their large input capacitances, they are able to absorb
more energy before being charged to the gate-breakdown
voltage. Nevertheless, once breakdown begins, there is
enough energy stored in the gate-source capacitance to
cause complete perforation of the gate oxide. With a gateto-source rating of VGS = ± 20 V maximum and electrostatic voltages typically being 100-25,000 volts, it
becomes very clear that these devices require special
handling procedures. Figure 15-1 shows curve tracer photos of a good device, and the same device degraded by
ESD.
Triboelectric Series
Static Protection
Increasingly
Positive
The basic method for protecting electronic components
combines the prevention of static build up with the removal
of existing charges. The mechanism of charge removal
from charged objects differs between insulators and conductors. Since charge cannot flow through an insulator, it
cannot be removed by contact with a conductor. If the
item to be discharged ;s an insulator (plastic box, person's
clothing, etc.), ionized air is required. If the object to be
discharged is a conductor (metal tray, conductive bag,
person's body, etc.), complete discharge can be accomplished by grounding it.
A complete static-safe work station should include a
grounded conductive table top, floor mats, grounded operators (wrist straps), conductive containers, and an ionized
air blower to remove static from non-conductors. All soldering irons should be grounded. All non-conductive items
such as styrofoam coffee cups, cellophane wrappers,
paper, plastic handbags, etc. should be removed from the
work area. A periodic survey of the work area with a static
Increasingly
Negative
From Table 2, it can be seen that cotton is relatively
neutral. The materials that tend to reject moisture are the
most significant contributors to ESD. Table 3 gives examples of the potentials that can be generated under various conditions.
..
-------------------------MOTOROLA TMOS POWER MOSFET DATA
1-15-1
r--~~-r~-.--r-.--r-'--r-'--,
I
I
r--
--~
I
r
;
~
~
~
-~
I-H-I+
+H' H
I
I
.9
I
I
I
I
I
I
I
r-I
r-
--~
I
~
I
I
r-
--~
r-
-~
L
_~
I
I
I
~
I
L
VDS
Normal Device
Vertical = 1.0 rnA/Division
Horizontal = 20 V/Division
VDS
Same Device Degraded by ESD
Vertical = 1.0 rnA/Division
Horizontal = 20 V/Division
FIGURE 15-1 - CURVE TRACER DRAWINGS OF A GOOD DEVICE AND A DEVICE
WITH A DEGRADED GATE DEVICE IS A 100 VOLT, 12 AMP POWER MOSFET
meter is good practice and any problems detected should
be corrected immediately. Above all, education of all personnel in the proper handling of static-sensitive devices
is key to preventing ESD failures. Figure 15-2 shows a
typical manufacturing work station.
NOTES: 1. 1/16 inch conductive sheet stock covering bench top work
area
2. Ground strap
3. Wrist strap in contact with skin
4. Static neutralizer (Ionized air blower directed at wOrk) Primarily for use in aress where direct grounding is impractical
Test Method:
Military specifications MIL-STD-883B Method 3015.1,
DOD-HDBK263, and DOD-STD-1686 classify the sensitivity of semiconductor devices to electrostatic discharge
as a function of exposure to the output of a charged network (Table 4). Through measurements and general
agreement, the "human-body model" was specified as a
network that closely approximated the charge storage
capability (100 pF) and the series resistance (1.5 k) of a
typical individual (Figure 15-3). Discharge of this network
directly into a device indicates that the model assumes a
"hard" ground is in contact with the part. Although all pin
combinations should be evaluated in both polarities (a
total of six combinations for a TMOS Power MOSFET),
preliminary tests usually show that gate-oxide breakdown
is most likely, and that reverse-biased junctions are about
an order of magnitude more sensitive than forward-biased
ones. The amount of testing, and components required,
can therefore be reduced to sensible levels, yet still yield
statistically sound data. The damage mechanism, which
can be identified through failure analysis of shorted or
degraded samples, is usually oxide puncture or junction
melllhrough.
R1
1.5 k
C1
FIGURE 15-2 - TYPICAL MANUFACTURING WORK STATION
100 pF
DUT
By following the above procedures, and using the
proper equipment, ESD sensitive devices can be handled
without being damaged. The key items to remember are:
1 - Handle all static sensitive components at a static
safeguarded work area.
2 - Transport all static sensitive components in static
3 •
shielding containers or packages.
Education of all personnel in proper handling of
static sensitive components
FIGURE 15-3 - THE HUMAN-BODY EQUIVALENT NETWORK
Significance of Sensitivity Data
Assuming that corrective measures cannot be immediately applied in a manufacturing area, or that products
manufactured using MOSFET components are likely to
1111111111111111111111111111·1111111111111111111111111111111111111111111111111111111111.......
MOTOROLA TMOS POWER MOSFET DATA
1-15-2
be exposed to ESD events in the field, the sensitivity of
the device can be used as a general indicator of the
likelihood of failure. Additionally, the extent and cost of
Sensitivity of Semiconductors to ESD from a Charged Network
TABLE 4 Device
Sensitivity
(C1 Peak Voltage)
protective measures increases as device susceptibility
increases.
MIL-STD-883
Class
0-1000
1000-2000
A
(Sensitive)
A
2000-4000
B
t
J
DOD-HDBK-263
Class
C....., ea...
Class 1 }
Class 2
Class 3
B
-
D"",,".
Wrist Straps, Ionized Air,
Conductive Flooring, Conductive
Clothing, etc. Field-Strength Alarm.
( Antistatic Carpet Spray, Wrist Straps,
Conductive Packaging Materials.
Humidity Adjustment
(Nonsensitive)
4000-15,000(1)
Typical
Preventive Measures(2)
Class 3
Notes: 1. Dala collected in many applicalions have shown that under special conditions voltages considerably in excess of 15 kV can be generated
with certain materials in the Triboelectric Series.
2. These examples are intended only as very general guidelines. The actual accuracy of a given method is highly variable, as a large number
of interdependent factors influence electrostatic field generation. Operator awareness, complemented with a high quality hand-held electrostatic field-strength meter referenced to ground, can be very effective in controlling profit losses due to ESD.
A Simple ESD Pulser
A simple electrostatic discharge circuit, which simulates
the human body model, is shown in Figure 15-4.
The high voltage supply consists of a 20 mA constantcurrent luminous-tube transformer and a half-wave voltage doubler circuit. Adjustment of the high voltage is accomplished with a 1.0 Amp Variac. (An OSCillator-type supply may also be constructed, using a flyback transformer.)
Voltage is monitored by a microammeter, using a 600
megohm current resistor, constructed from 30-1/2 watt,
20 MO carbon composition resistors connected in series.
A low voltage supply powers a 555 I.C. timer to provide
trigger pulses. This circuit fires a C106 SCR, discharging
the 0.033 JLF capacitor into an ordinary photoflash trigger
coil. This provides a narrow, high-voltage pulse to fire the
C.P. Clare TA-15.0
T1
Power
'4
I
1.0 A.
Variac
5000 pF
20 kV
0--0-"<>-1-..--,
15 kV Triggered Gap
5.1 M
(3) MR250-5
2.0W
5000 pF
600M
(3)
MR250-5
120V
120kv
10 kV
(50 "A)
I
30 kV
Meter
Peak
Voltage
1,00
-=
pF
15 kV
Centralab
857.-100N
-=
Jefferson
Electric
(3) MR250-5 (Series)
1.2 M
2.0 W
RI
1.5 k
HV Output
250 V
720-351
Current
Pulse Out
T4
RS
MOA920A2
0.01 p.F
270
Pulse
Rep
Rate
1.0
k
0:-
LEO
0:-
FIGURE 15-4 - ESD (ELECTRO STATIC DISCHARGE) PULSER
MOTOROLA TMOS POWER MOSFET DATA
1-15-3
•
triggered gap. The + 250 V across the 0.033 JLF capacitor
is derived by a separate rectifier string, and is regulated
by the V(BR)CEO of an NPN power transistor, used as a
high-voltage Zener. This voltage quickly saturates as the
output control is advanced.
The high voltage supply charges a 100 pF ceramic
transmitting-type capacitor, which has extremely low
equivalent series inductance. This capacitor, along with
the 1.5 kO series resistance, forms the standard humanbody equivalent circuit specified by MIL-STD-883.
Discharge of the 100 pF capacitor into the OUT is accomplished by means of a triggered spark gap. This device, although somewhat expensive ("" $100), is nearly
an ideal switch, without the voltage limitations, contact
bounce, and drive requirements of reed relays. The trigger
pulse initiates a plasma discharge between the probe and
one electrode. This plasma is swept across the gap by
the electric field, initiating arc breakdown.
Warning:
Caution is advised in the construction and operation of
this circuit, as the potentials and stored energies in this
circuit may be lethal. Every effort should be made to
shield operators from the possibility of contact. Motorola
cannot be responsible for claims resulting from the use,
or misuse, of this circuit.
Test Results
Measurement of ESD sensitivity thresholds using the
100 pF-1.5 k circuit has produced the results shown below. An important conclusion from this data is that the
ESD sensitivity decreases as the die size (and powerhandling capability) increase. Also, these devices fall at
or below the 2,000 volt limit defined by Mil-Std-883 as
that which classifies a device as static-sensitive. Power
MOSFETs, then, should be handled with proper precautions.
TABLE 5 Device
Test Results
Sensitivity
. (Volts)
Ciss
(pF)
Ratings
Die Size (Mils2)
MTP5N05(1)
5.0 A, 50 V, N-CH,
Plastic
76 2
150
520
MTP15N05
15 A, 50 V, N-CH,
Plastic
1502
700
880
MTM6N60
6.0 A, 600 V, N-CH,
Metal
1992
1400
1350
MTM8N60
8.0 A, 600 V, N-CH,
Metal
2502
2000
1500
..
(1) Tests were conducted With deVices which were of the onglnal TMOS technology. Newer deVIces have smaller Input capacItances.
prominant mechanism is puncturing of the thin gate oxide,
followed by melting of the silicon.
The scanning electron microscope (SEM) photos of Figure 15-5 illustrate the typical damage caused to power
MOSFETs by electrostatic discharge (ESD). The most
Low Power (7DX)
FIGURE 15-5 -
High Power (12DDX)
RESULTS OF ESD TESTING A 6.0 A POWER MOSFET MTM6N6D AT 1000
MOTOROLA TMOS POWER MOSFET DATA
1-15-4
v.
REFERENCES
1. K. Gauen, A. Pshaenich, "Investigation of Power
MOSFET FBSOA Using a Non-destructTester," 14th
Annual IEEE Power Electronics Specialists Conference, 1983.
2. K. Gauen, "Designing With TMOS Power.
MOSFETs," Motorola Application Note AN-913,
1983.
3. K. Gauen, "Paralleling Power MOSFETs in Switching
Applications," Motorola Application Note AN-918,
1983.
20. T. Lee, "Construction and Application of a Tester for
Measuring EOS-ESD Thresholds to 15 KV," EOSESD Symposium Proceedings, September, 1983.
21. R. Valentine, "FETs Improve Motor-Drive Efficiency,"
EDN, September 15,1983.
22. W. Roehr, "Mounting Techniques for Power Semiconductors," Motorola Application Note AN-778,
1978.
23. T. Suva and B. Haver, "Flyback Switching Power Supplies," Motorola Engineering Bulletin EB-87A, 1982.
4. A. Pshaenich, "Characterizing C-E and D-S Diodes
for Switchmode Applications," Powerconversion
International, April, 1982, Motorola TDT-101A.
24. J. Alberkrack, "Theory and Applications of the
MC34063 and JLA78540," Motorola AN-920, 1984.
5. R. Haver, "A 100 kHz FET Switcher," Powerconversion International, April, 1982.
25. A. Pshaenich, "New Power Bipolars compare Favorably with FETs for Switching Efficiency," Motorola
Application Note AN-845, 1982.
6. C. Moyer, "Using Power MOSFETs in Stepping Motor
Control," Motorola Application Note AN-876, 1982.
7. J. Schroeder, "MOSFETs Best Bipolars In Fast High
Current Driver," Electronic DeSign, October 28, 1982.
8. A. Pshaenich, "The MOS SCR, A New Thyristor
Technology," Motorola Engineering Bulletin EB-103,
1982.
9. A. Pshaenich, "MOS Thyristor Improves PowerSwitching Circuits," Electronic Design, May 12, 1983.
10. H. Saladin, "Fast Power FET Switch," Electronic
DeSign, December 22, 1983.
11. J. Phipps, "Two Integrated Circuit Drivers for Power
MOSFETs," Motorola TMOS Power FET Design Tips
TDT-102,1982.
12. J. Phipps, "Drive Considerations
MOSFETs," Motorola TDT-103, 1982.
for
Power
13. H. Saladin and A. Pshaenich, "Paralleling Power
MOSFETs," Motorola TDT-104, 1982.
14. "Using the Motorola TMOS DeSigners Data Sheet,
TDT-105, 1982.
15. J. Takesuye and G. Fay, "MOSFETs Replace Bipolars and Circuits Are Better For It," Electronic Design,
December 20, 1980.
16. A. Pshaenich, "The Effects of Base Drive Considerations on RBSOA," Motorola Application Note
AN-828, 1981.
17. A. Pshaenich, "Relative Efficiencies of Motorola
Power Semiconductors in a PWM DC Motor ContrOller," Motorola Engineering Bulletin EB-108, 1983.
18. K. Gauen, "Special Design Considerations for High
Power Multiple Die MOSFET Circuits," Powerconversion International, November-December, 1983.
19. A. Pshaenich, "Dual Timer Supplies High Voltage
26. W. Roehr, "Avoiding Second Breakdown," Motorola
Application Note AN-415A, 1972.
27. W. Roehr and B. Shiner, "Transient Thermal Resistance General Data and Use," Motorola Application
Note AN-569, 1972.
28. W. Schultz, "A Method of Characterizing Power Transistors for Unspecified Parameters," Proceedings of
Powercon 10, March, 1983.
29. D. Blackbum and D. Berning, "Power MOSFET Temperature Measurements," 13th Annual IEEE Power
Electronics Specialists Conference, 1982.
30. D. Blackburn, "An Electrical Technique for the Measurement of the Peak Junction Temperature of Power
Transistors," 13th Annual Proceedings Reliability
Physics.
31. D. Berning, "A Reverse Bias Safe Operating Area
Transistor Tester," NBS Special Publication 500-54,
U.S. Department of Commerce/National Bureau of
Standards.
32. R. Severns, "dv/dt Effects in MOSFET and Bipolar
Junction Transistor Switches," PESC, 1981.
33. W. J. Slusark et ai, "Catastrophic Burn Out in Power
VDMOS Field Effect Transistors," Reliability Physics
Symposium, April, 1983, Phoenix, Arizona.
34. E. Hebenstreit, "Overcoming the dv/dt Problem in
Power MOSFET Switching Stages During Commutation," PCI, September, 1982 Proceedings.
35. S. Clemente, B. R. Pelly and B. Smith, "The
HEXFETs Integral Body-Diode - Its Characteristics
and Limitations," AN-934A, International Rectifier.
36. J. G. Kassakian, "Some Issues Related to the Behavior of Multiple Paralleled Power MOSFETs," Electrical Power Systems Engineering Laboratory, M.I.T.,
Cambridge, Massachusetts 02139.
R.a.m.p.,.".£.re.c.m.on.~.s.,.O.ct.o.b.e.r.2.0,.1.9.8.3...................................................... ~
......
MOTOROLA TMOS POWER MOSFET DATA
1-15-5
37. B. J. Baliga et ai, "The Insulated Gate Rectifier (IGT):
A New Power Switching Device," IEDM Technical
Digest, 1982, P. 264.
49. W. Schultz, "Lossless Current Sensing with
SENSEFETS Enhances Motor Drive Design," PCIM,
April,1986.
38. K. Gauen, "Paralleling Power MOSFETs in Linear
Applications," Proceedings of PCI/Motorocon, 1984.
50. W. Schultz, J. Alberkrack, "Current Sensing Power
MOSFETs Team Up With A New IC For Current Mode
Control," Powertechnics, May 1986.
39. W. Schultz, "High Current FETs - A New Level of
Performance," PowercQnversion International,
..:.:
Ma~~h, 1984.
40. K: Bauen, "Power"MOSFET Variant Excells At High
Loads," Electronic Design, April 5, 1984.
41 ~ K. Gauen, "MOSFETs Aid In Switch-Mode Power
Supply Growth," Electronic Engineering Times, April
23,1984.
42. I. Yoshida, T. Okabe, M. Katsueda, S. Ochi and M.
Nagata, "Thermal Stability and Secondary Breakdown in Planar Power MOSFETs," IEEE Transactions
in Electron Devices, Vol. ED-27, No.2, February,
1980.
43. D. P. Kennedy, A. Phillips, Jr., "Source-Drain Breakdown in an IGFET," Int. Elec. Dev. Meet, Tech Dig,
pp. 160-163, paper 8.5, December, 1973.
44. T. Toyabe, K. Yamaguchi, A. Asai and M. Mock,
"A Numerical Model of. Avalanche Breakdown in
MOSFETs," IEEE Transactions on Electron Devices,
Vol. ED-25, p. 825,1978.
45. F. Oettinger, D. Blackburn, S. Rubin, "Thermal Characteriziation of Power TranSistors," IEEE Transactions on Electron Devices, Vol. ED-23, No.8, August,
1976.
46. W. Schultz, K. Gauen, "Commutating SOA in Monolithic Freewheeling Diodes," Powertechnics, January, 1986.
47. K. Gauen, "New MOSFETs Revise Power Transistor
Performance Specs," EON, September 19, 1985.
48. K. Gauen, "New Power MOSFETs Require Special
Thermal Considerations," PCIM, March, 1986.
51. "Gate Charge and Input CapaCitance - Complementary Specifications of MOSFET Input Impedance," Powertechnics, July 1986.
52. D. W. Berning and D. L. Blackburn, "Power MOSFET
Failure During Turn-Off: The Effect of Forward Biasing the Drain-Source Diode," Proceedings of the 1986
IEEE Industrial Applications Society Annual Meeting,
October 1986.
53. K. Gauen, W. Schultz, "Proper Testing Can Maximize
Performance in Power MOSFETs," EON, May 14,
1987.
54. S. Krishna, and P. L. Hower, "Second Breakdown of
Transistors During Inductive Turn Off," Proc. of IEEE,
Vol. 62, March 1973.
55. The Power Transistor in Its EnVironment, ThompsonCSF, 1979.
56. W. Schultz, "Drive Techniques for High Side N-Channel MOSFETs," PCIM, June 1987.
57. K. Gauen, "Understanding the Power MOSFET's
Input Characteristics," Proceedings of the Power
Electronics Conference/87.
58. D. Artusi, W. Schultz, "Solid-State Devices Ease Task
of DeSigning Brushless DC Motors," EON, September
3,1987.
59. W. Schultz, "Sense-Cell MOSFET Eliminates Losses
in Source Circuit," EON, June 26, 1986.
60. J. Alberkrack, W. Schultz, "A New High Performance
Current-Mode Controller Teams Up with Current Sensing Power MOSFETs," Motorola Application Note
AN976.
Kapton® and Teflon are trademarks of E.I. DuPont.
MOTOROLA TMOS POWER MOSFET DATA
1-15-6
Selector Guide
2
TMOS Power MOSFETs
Metal Packaged Table 1 Table 2 -
Plastic Packaged Table 3 Table 4 -
T0-220
P-Channel. ••••••••••••• 2-5
N-channel •••••••••••••• 2-5
Plastic Packaged Table 5 Table 6 -
TO-204
P-Channel •••••••••.•••• 2-3
N-Channel •••••••••••••• 2-3
TO-218
P-Channel. ••••••••••••• 2-7
N-Channel .•••.•.••••••• 2-7
Logic Level MOSFETs
Table 7 -
N-Channel To.204AA and
To.220AB •••••••.•••••• 2-8
Insulated Gate Bipolar Transistors
Table 8 - To.204AA •••••.•••••••• 2-9
Table 9 - TO-220AB .••.•••••••••• 2-9
TMOS SENSEFETs
Table 10 -
Case 314B•••••••••••••• 2-9
DPAK
Table 11 -
i:)
I
I
Case 369-03 - TO-251,
Insertion Mountable
case 369A-03 - To.252,
Surface Mount .•.•.•.••. 2-9
Small-Signal MOSFETs
Table 12 -
Switches and Choppers
To.205AD ••••••••••••••
Table 13 - 4-Pln Dip
(case 370-01) •••••••••••
Table 14 - Plastic - To.226AA,
Style 22 •••••••••.••••••
Table 15 - Surface Mount
-case 318-02, Style 10 •••
Table 16 - TMOS Product
Matrix •.•••••••••••••••
2-10
2-10
2-11
2-11
2-12
TO-220 Leadforms .............. 2-14
2·1
I.I.!
If
Power MOSFETs
are a Reality
I
MOTOAOI.A INC.
lr
TMDS
Dear Valued Motorola Customer:
Prior to introducing TMOS Power FETs in 1980, Motorola spent three years in developing what was considered at that time the industry's most advanced powsr MOSFETs, but
we weren't satisfied with that. We kept working on the product and since that time,
maJor advancements in our technology were made. Now high volume and advanced
tschnology allows us to offer you the broadest line of power MOSFETs of the highest
quality possible at the best price. With voltage capability to 1000 Volts and current ratings as high as 100 Amperes, you can select exactly what you need.
Our latsst technology utiliZes high source site or cell density (over 1 million cells per'
square inch) for effiCient utiliZation of silicon. This results in a smaller chip for a given
mS(on) or a lower mS(on) for a given chip size - either way, price or performance is
enhanced and our customers receive the benefits.
Motorola's commitment to quality is continuing to show significant results. The AOQ of
TMOS Power FETs has been consistently reduced and now we guarantee an AOQ of 100
ppm, although currently the AOQ is well under 100 ppm. How we accomplish this is
included in this manual.
As the world's largest manufacturer of power transistors we have the equipment, know-
how, and capacity to serve your needs.
Power MOSFETs are a reality and Motorola is dedicated to becoming a leading supplier
of power MOSFETs just as it has become the leading source for bipolar power - we
intend to attain this leadership position by earning it.
It is our intent to offer superior performance, value, service, quality, and reliability.
We invite your inquiries.
Paul V. White,
Vice President and Director of Product Marketing,
Discrete and Special Technologies Group
':",
•
MOTOROLA T
MOS POWER MOSFET DATA
&
TMOS Power MOSFETs
Metal Packages -
©
TO-204
o
0
10
0
TO-204
CASE 1-04 and CASE 1-0&
Table 1 -
P-Channel
Table 2 10
V(BR)DSS 'OS(on)@IO
(Volts)
(Ohms) (Amps)
Min
Max
Device
,6
500
1-
450
200
180
I~
4
1.5
MTM3P25
3
2.5
MTM5P25
5
,2
'4
'~'"
13
1
2.5
0.7
4
1
0.7
MTM5P2O
"
5
,8
12?
2.5
MTM5P18
5
75
4
MTM8P18
6
"'~>
8
125
,I};;.
"
0.5
MTM1Nl00
1
75
1.5
MTM3Nl00
3
125
>tso
850
.MTM5N~
·ft:
10
0.5
MTM1N95
1
75
4
1.5
MTM3N95
3
125
3
2.5
MTM5N95
5
150
8
1
MTM2N90
2
75
4
2
MTM4N90
4
125
150
3
3
MTM6N90
6
8
1
MTM2N85
2
75
4
2
MTM4N85
4
125
150
~
MTM12Pl0
"1il ' ~Jl}
900
12
"
>fi&
~s:
3
3
MTM6N85
6
7
1.5
MTM3N80
3
75
2
3
5.3
125
4
MTM8P08
8
0.3
6
MTM12P08
12
0.15
10
MTM2OP08
20
125
0.3
6
MTM12P06
12
75
750
7
1.5
.:t26 '
600
2.8
3
,~t~·~t ~:: "
Po'
4
r<7;lf" , I"~).
950
10
(Amps) (Watts)
Max
Max
10
0.4
,0.1~.
50
1000
75
~~~."
.M. ;~:
0 ..1$'
60
2
3
0.3
80
(Amps) (Watts)
Max
Max
~
N-Channel
V(BRIDSS 'OS(on)@IO
(Vots) (Ohms) (Ampe)
Min
Max
Devica
MTM2P45
250
100
Po'
.;~
800
75
-
1.5
"
BUZ84
BUZ84A
6
MTM3N75
3
75
6
150
2N6823
0.3
6
MTM12P05
12
75
2.5
1.5
0.2
10
MTM2OP05
20
100
1.6
6
2N6826
0.14
12.5
MTM25P05
25
125
1.2
3
MTM6N60
0.5
4
MTM8N60
'@25"C
'@25"C
Device types shadad in Tables 1 through 6 are key industry standard devices recommendad for n_ dallgns.
MOTOROLA TMOS POWER MOSFET DATA
2-3
MTM3N60
8
Table 2 - N-Channel - continued
V(BR)DSS l'I)5(on) @ 10
(VaHs) (Ohms) (Amps)
Min
Max
Device
Table 2 -
N-Channel - continued
10
PO"
(Amps) (Watts)
Max
Max
"Available at JTX and JTXV levels
t Indicales E-FET device. whh avalanche energy specified.
Device typa shaded in Tables 1 through 6 ore key industry atandllrd devices recommended for new designs.
• @ 25"C
MOTOROLA TMOS POWER MOSFET DATA
2-4
TMOS Power MOSFETs
Plastic Packages - TO-220
G
0
TD-220AB
CASE 221A-04
s
Table 3 DSS
V(B:lt.
IV
)
Min
P-Channel
rDS(on)@IO
(Ohms) (Amps)
Max
Device
,~
500
)$,
l'
450
200
100
Table 4 -
MTP2f'5O
4
1.5
MTP3P25
3
3
2.5
MTP5P25
5
2
4
MTP8P25
8
1
2.5
MTP5P20
,~'"
5
.
:~~.
: '~
,:M:rP8Pl0:: .
0.5
6
MTP12Pl0
12
0.4
4
MTP8P08
8
6
MTP12P08
12
3.5
MTP7P06
7
"
V(BRIDSS rOS(on) @ 10
(Volts) (Ohms) (Amps)
Device
Min
Max
1
75
..,f,~~ '~;6.""~i»:;',!~;~~;J7;\;:S0T~
950
900
10
0.5
MTPl N95
1
4
1.5
MTP3N95
3
MTP2N90
2
8
4
850
800
2
8
600
500
MTP4N90
4
MTP2N85
2
4
2
MTP4N85
4
7
1.5
MTP3N80
3
450
MTP3N75
750
12
0.5
MTP1N60
2.5
1.5
MTP3N55
3
1.2
3
MTP6N55
6
125
8
0.5
MTPl N50
1
50
1~·.1':"'iK \'~1i';:<~,:';">
75
50
:8,',
10
Po'
(Amps) (Walla)
Max
Max
MTP1Nl00
0.3
80
0.3
N-Channel
10
PO'
10
(Amps) (W8It8)
Max
Max
100
60
MTP5P18
V(BRlDSS rDS(on) @ 10
(Volts) (Ohms) (Amps)
Device
Min
Max
1000
2
V(BRIOSS rOS(on)@IO
(Vats) (Ohms) (Amps)
Device
Min
Max
MTP2P45
250
180
10
Po'
(Amps) (WSItS)
Max
Max
400
,f22"~A
'@25"C
Device typH . _ in Tables 1 through a are key Industry standard devices recommendad for new daolgn.>
MOTOROLA TMOS POWER MOSFET DATA
2·5
10
PO'
(Amps) (W8It8)
Max
Max
Table 4 -
N-Channel -
continued
• @ 25"<;
t Indicates E-FET devices with avalanche energy specified.
D _ types shaded in Tobl.. 1 through 6 aro key Industry standard davie. rocommended for new doeigns.
MOTOROLA TMOS POWER MOSFET DATA
2-6
Plastic Packages - TO-220AB (continued)
Table 4 -
N-Channel -
continued
Po'
10
(Amps) (Watts)
Max
Max
V(BR)OSS rOS(on)@IO
(Volts) (Ohms) (Amps)
Min
Max
Device
60
0.085
15
0.08
12.5
IRF541
27
125
MTP25N06
25
100
I---
'{j;Q5li
'17.5
0.6
2.5
MTP5N05
5
50
0.28
5
MTP10N05
10
75
0.16
7.5
MTP15N05
15
0.12
6
BUZ71A
12
50
50
125
MTP25N06Et
, MTP35N06Et
V(BRIOSS rOS(on) @ 10
(Vots) (Ohms) (Amps)
Min
Max
Device
-
35
PO'
10
(Amps) (Watts)
Max
Max
0,1
7
MTP14N05A
14
0.08
8
MTP16N05A
16
MTP25N05
25
12.5
MTP25N05Et
0.07
40
100
r---75
IRFZ32
0.06
15
BUZllA
'---
0.05
40
-
MTP12N05Et
r---0.1
,
IRFZ22
14
BUZ71
12
MTP15N05!;t
15
MTP30N05Et
30
IRFZ30
0.04
BUZ11
Q.1l35 ,
29 "W~t
45
IRFZ42
46
"
,r.5
!l.~:
','
;";i5.':: ~',;
IRFZ40
IRFZ20
, 125
',150
51
'@250(;
t Indicates E-FET devices with avalanche energy specified.
Plastic Packages -
TO-218
Table 6 -
N-Channel
V(BR)DSS rOS(on) @ 10
(Volts) (Ohms) (Amps)
Min
Max
Device
G
D
, '<(so ,
1000
S
950
MTH5N95
900
3
600
P-Channel
Po'
10
(Amps) (Walts)
Max
Max
V(BRIDSS rOS(on)@ 10
(Vots) (Ohms) (Amps)
Min
Max
Device
' O:r~:; :,::;1-. '
200
,
,:~
, ();lIL,
.",
50
126',',;
1,2
MTH6N60
4
MTH8N60
8
1.2
3
MTH6N55
6
0.5
4
MTH8N55
500
MTH2OP10
20
450
','
MTH2OP08
80
60
8
''0.1.4,':, ·:',12.$,'
,MT1't25P()8
25
',',
400
MTH25P05
'@25°C
'@25°C
Devtce type••h _ In Tables 1 through 6 are key Industry standard davlces recommended for new design••
MOTOROLA TMOS POWER MOSFET DATA
2-7
6
0.5
MTH8P18
180
100
.MTH8P20,
550
MTH6N90
MTH6N85
850
Table 5 -
10
PO'
(Amps) (Walts)
Max
Max
Plastic Packages -- TO-218 (continued)
Table 6 - N-Channel - continued
l'OS(on)@IO
(Ohms) (Amps)
Max
200
150
100
Da¥lce typee shaded In Tables 1 through 6 are key Industry 8tandard device. recommended lor new designs.
Logic Level MOSFETs
TO-204AA
Table 7 -
N-Channel Logic Level Power MOSFETs (TO-204AA and TO-220AB)
V(SR!:!SS
(Vo )
Min
roS(onl
(Ohms
150
0.3
@,
10
(Amps)
Max
Davies
5
120
MTM10N15L
10(cont)
Amps
Po @ TC = 25"<:
Watts
Package
TO-
10
75
204AA
MTP10N15L
220AB
MTM10N12L
204AA
MTP10N12L
MTP12N10L
220AB
12
100
0.18
0.8
2
MTP3N10L
3
80
0.18
6
MTP12N08L
12
0.8
2
60
0.08
12.5
6
MTP3N08L
3
MTM25N06L
25
100
15
75
MTP4N06L
4
25
MTM25N05L
25
100
15
75
4
25
MTP25N06L
0.15
7.5
MTM15N06L
220AB
MTP15N06L
50
0.6
2
0.08
12.5
•..if.
7.5
MTM15N05L
2
MTP4N05L
204AA
220AB
MOTOROLA TMOS POWER MOSFET DATA
2-8
204AA
220AB
MTP15N05L
0.6
204AA
220AB
MTP25N05L
0.15
204AA
Insulated Gate Bipolar Transistors
(GEMFETs)
1r
This relatively new series of power transistors combines
the high input resistance of a MOSFET with the low internal
on-resistance of a bipolar transistor to provide more efficient performance than either a MOSFET or bipolar device
in low-frequency switching service. Recommended for
motor drive circuits, home appliances, and other applications where high switching speed is not a requirement. All
are N-Channel.
Table 8 -
TMDS
Table 9 -
To-204AA
500
450
0.27
10
MGM20N50
20
100
1.6
2.5
MGM5N50
5
50
0.27
10
MGM20N45
20
100
1.6
2.5
MGM5N45
5
50
Po"
IC
(Amps) (Watts)
Max
Max
rCElon)@IC
VaRICES)
(Volts) (Ohmsl (Amps)
Device
Max
Min
Po"
IC
(Ampsl (Watts)
Max
Max
vaRICES) rCE(on) @IC
(Volts) (Ohms) (Ampsl
Max
Device
Min
TO-220AB
500
450
100
0.27
10
MGP2ON50
20
1.S
2.5
MGP5N50
5
50
0.27
10
MGP20N45
20
100
1.S
2.5
MGP5N45
5
50
·@25'C
·@25'C
TMOS SENSEFETs
DPAK
TM
CASE 3148
(5 PIN T0-2201
CASE 369A-03
TO-252
SENSEFETs are conventional power
MOSFETs with an option provided to
sense the drain current by measuring a
small proportion of the total drain currant. These devices are ideal for current
mode switching ragulators and motor
controls.
Table 10 V(BR~
(Yo)
Min
Table 11 -
SOURCE
Case 314B
Po"
10
(Amps) (Watts)
Max
Max
rDS(on)@IO
(Ohms) (Amps)
Max
Device
4
1
MTD2N50
2
400
5
0.5
MTD1N40
1
200
0.7
2
MTD4N2O
4
150
0.3
3
MTDBN15
S
0.25
MTP50N05M
50
125
100
60
0.04
20
MTP40N06M**
40
125
SO
100
0.25
5
MTP10N10M**
10
75
60
0.065
12.5
MTP25N10M
25
1.5
4
MTP4N25M
0.45
2
1.5
0.85
500
Po"
10
(Amps) (Watts)
Max
Max
500
25
250
Case 369A-03 Surface Mount
Case 369-03 Insertion Mountable""
Y(BR)DSS rOS(on)@IO
(Volts) (Ohms) (Amps)
DevIce
Max
Min
0.028
50
CASE 3&9-03
TO-2S1
MTDSN10
MTDSNOB
0.6
2
MTD4P06t
4
125
0.4
2.5
MTD5N06
5
4
75
0.15
4
MTD3055E
8
MTP10N25M
10
100
0.6
2
MTD4P05t
4
2.5
MTP4N50M
5
75
0.4
2.5
MTD5N05
5
4
MTP8N50M
8
125
0.1
5
MTD10N05E
10
50
·@25'C
·@25'C
•• Add ·1 to part number to order insertion mountable package
t Indicates P-Channel
··Avallable from stock.
These devices are planned for Introduction,
MOTOROLA TMOS POWER MOSFET DATA
2-9
20
Small-Signal MOSFETs
~
lIT
ro-..... _
(TO·39)
Table 12 - Switches and Choppers - TO·205AD
'OS(on)@IO
(Ohms)
(Amps)
V(OSS)
(VoHs)
Device
ID(Cont)
(Amps)
PO@TC = 2S"C
(WailS)
240
6
10
0.5
0.5
VN2406B
VN2410B
0.63
0.63
2.5
2.5
200
0.8
0.8
1.5
6.4
2.25
2
1.5
0.25
2N6790
IRFF220
2N6784
MFE9200
3.5
3.5
2.25
0.4
20
20
15
1.8
170
6
10
0.5
0.5
VN1706B
VN1710B
0.63
0.63
2.5
2.5
150
12
0.1
MFE4150
0.250
6.25
100
0.3
3
IRFF1
"-..,
<5 090
~
VOS-IOV
~W
0
II
§;
I
1
1
J
10
~
~
~
10
I2
§
// /
V/
I
50
"--
~
...
1
1
I
I'--..
080
~
:E
6.0
40
8.0
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
r--
I
I
I
FIGURE 6 - GATE THRESHOLD VOLTAGE
VARIATION
FIGURE 5 - TRANSFER CHARACTERISTICS
30
I
I
I
;. 004
3.5 V
1
1
~J = looo~- -
J---
~ 012
I
o
.A"
~
M'bV"'"
UIJV
,
.A
_....
VGS=10V
u
5.0V
I/" ~ ,-1--"
50
I
-
~o 70
12
lO
-50
>
-25
25
50
75
"
100
125
..........
150
TJ. JUNCTION TEMPERATURE (OCI
FIGURE 7 - THERMAL RESPONSE
10
w
>
~:il
N
:;
D· 0.5
0.5
0.2
~
:g
-
0.1
0.05
0.1
0.02
<
z
-1-""-'"
-I-""
U
0.3
0.05
0.03"-
0.0 2~
0.02
0.05
0.1
~ f:=
F=I
Plp1Hl
=
tilt2
- ~
DUTY CYCLE, o· tI/t2 - I -
P·9 1,
frrmr
ROJcltl rltl ROJC
ROJC = I 67°C/W Max
~
,..,..
,-f-""
V
0.0 I
0.01
.....
~ ...
I 1I1111
0.5
1.0
2.0
t. TIME
II III
5.0
10
20
1m')
MOTOROLA TMOS POWER MOSFET DATA
3-8
I
Read trme at IJ
TJlpkl - TC = Plpk) ROJClt)
I I I ) 1111
0.2
I
D curves apply for power
Pulse tram shown
50
IIII
lOa
I
200
I
500
1000
2N6756, JTX, JTXV
OPERATING AREA INFORMATION
FIGURE 9 - MAXIMUM RATED FORWARD BIAS
SAFE OPERAnNG AREA, 2N6756
FIGURE 8 - MAXIMUM RATED SWITCHING
SAFE OPERAnNG AREA
40
,..,
40
20
- 10
~6.0
~
!Z
~
II:
10ms
2.01--
a 1.O~ ~--~~
c
.9
TJ .. l5O"C
o
o
20
40
60
80
VOS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
6F
O.4F=
o.
o.21== t=
f--
lOS(on) limit -
+--
de "'"
PacbgeUmit
Thermal Umit
VGS - 20 V. Single Pulse
I- TC - 25"C
O. 1
0.06
0.04
2.0
100
O.lms
tOms
$4-0
0
101'.5-
"'10::
....
4.0
".-
6.0
10
20
40 60
VOS. DRAlN·TO-SOURCE VOLTAGE (VOLTS)
100
SWITCHING SAFE OPERAnNG AREA
FORWARD BIASED SAFE OPERAnNG AREA
The switching safe operating area (SOA) of Figure 8,
is the boundary that the load line may traverse without
incurring damage to the MOSFET. Thefundamentallimits are the peak current, 10M and the breakdown voltage,
V(BR)OSS' The switching SOA shown in Figure 8 is
applicable for both turn-on and turn-off of the device
for switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
TJmax - TC
RruC
The dc data of Figure 9 is based on a case temperature
(Tel of 25°C and a maximum junction temperature
(TJmax) of 150"C. The actual junction temperature
depends on the power dissipated in the device and its
case temperature. For various pulse widths, duty cycles,
and case temperatures, the peak allowable drain current
(10M) may be calculated with the aid of the following
equation:
10M
=IO(25°C) [TJmax - TC]
PO' RruC' r(t)
Where
IO(25~C)
TJmax
TC
Po
RruC
r(t)
FIGURE 10 - CAPACITANCE VARIAOON
=dc drain current at TC = 25°C from Figure 9
= Rated maximum junction temperature
=Oevice case temperature
= Rated power dissipation at TC = 25°C
= Rated ateady state thermal resiatance
= Normalized thermal response from Figure 7.
2000
I
TJ = 25"C
VGS = 0
f = 1 MHz
1600
L\
~\
400
0
t-...
Gss
\\
'\ ~
Cass
Cr..........
10
20
30
40
Ves. DRAlN·TO-SOURCE VOlTAGE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
3-9
50
MOTOROLA
• SEMICONDUCTOR -
-
_ _ _ __
TECHNICAL DATA
2N6758
lh'sign~'r's
Data Shpet
9.0 AMPERE
N·CHANNEL ENHANCEMENT·MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
,N·CHANNEL TMOS
POWER FET
These TMOS Power FETs are designed for medium voltage,
high speed power switching applications such as switching
regulators, converters, solenoid and relay drivers.
rDS(on) = 0.4 OHM
200 VOLTS
• Silicon Gate for Fast Switching Speeds - SWitching Times
Specified at 100°C
• Designer's Data - lOSS, VDS(on), VGS(th) and SOA
Specified at Elevated Temperature
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
• 2N6758 is Qualified to Mil-S 19500/542A
,r
G
TMDS
MAXIMUM RATINGS
Symbol
Valuet
Unit
Drain-Source Voltage
Rating
VOSS
200"
Vdc
Drain-Gate Voltage
(RGS = 1.0 MI'l)
VDGR
200"
Vdc
~l
v
(
, I
Gate-Source Voltage
Drain Current
Continuous TC
TC
Pulsed
J
Q
±20
VGS
Vdc
Adc
=
=
25°C
100°C
Total, Power Dissipation @ TC
Derate above 25°C
9.0"
6.0"
15"
ID
10M
=
25°C
Operating and Storage Temperature Range
STYlH
PIN 1. GATE
:Z.SOURtE
Maximum Lead Temp. for Soldering
Purposes, 1,16" from case for seconds
,
R
T
U
S
G
CASEOAAIN
PD
75"
0.6'
Watts
Wf'C
TJ, Tsta
-55" to 150'
°c
NOTES:
1 DIAMETER VAND SURFACE WARE DATUMS.
2. POSmONAl TOLERANce FOR HOlf 0;
If I +01510,0101 ®Iwlv ®I
3. POSmONAL TOLERANCE FOR LEADS:
Ifl+o,301O,0121®lwlv®1 Q®l
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Junction to Ambient
-
H
°CIW
RI/JC
R9JA
1.67'
TL
300'
30'
°C
DIM
A
•
,
C
0
F
G
H
*JEDEC ~eglstered values.
tJTX. JTXV available.
J
•
Q
R
U
V
Designer's Data for "Worst Case" Conditions
The Designer's Data Sheet permits the design of mast circuits entirely from
the information presented. Limit data - representing device characteristics
boundaries - are given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
3·10
MlUMETERS
MIN
MAX
39.37
21.08
7.62
.35
0.97
1,09
1AO
1.78
3O.1SBSC
10.92BSC
5.46BSC
16.89BSC
11.18
12.19
3.81
4.19
26.67
2.54 3.05
3.81
.,9
WCHfS
!tIN
MAX
1,550
0.250
o.
0.065
0,830
0,'"
.043
0.070
1.187 BSC
Q.43QBSC
O.215BSC
O.666BSC
0.440
0.480
0.151
0.166
1.050
0.120
0.166
0.100
0.151
CASE 1-04
TO-204AA
2N6758, JTX, JTXV
ELECTRICAL CHARACTERISTICS (TC
= 25·C unless otherwise noted)
I
Symbol
Min
Typ
Max
Unit
Drain-Source Breakdown Voltage
(VGS = 0,10 = 1.0 mAl
VBR(OSS)
200
-
-
Vdc
Zero Gate Voltage Drain Current
(VOSS = Rated VOSS)
TJ = 125·C
lOSS
-
-
1.0"
4.0"
Characteristic
OFF CHARACTERISTICS
mAdc
Gate-Body Leakage Current, Forward
(VGSF = 20 V)
IGSSF
-
-
100*
nAdc
Gate-Body Leakage Current, Reverse
(VGSR = 20V)
IGSSR
-
-
100"
nAdc
2.0"
1.5
-
4.0*
3.5
-
-
ON CHARACTERISTICS
Gate Threshold Voltage
(10 = 1.0 mA. VOS = VGS)
TJ = 100·C
VGS(th)
Static Drain-Source On-Resistance (1)
(VGS = 10 Vdc, 10 = 6.0 Adc)
TC = 125·C
rOS(on)
=
Drain-Source On-Voltage (VGS
(10 = 9.0 Adc)
10 V) (1)
Forward Transconductance (1)
(VOS = 15 V, 10 = 6.0 A)
Vdc
Ohms
-
VOS(on)
-
0.4*
0.75"
-
3.6*
Vdc
9FS
3.0*
-
9.0'
mhos
pF
CAPACITANCE
Ciss
350"
-
800"
Coss
100"
-
450"
Crss
40*
-
150*
-
-
td(off)
-
tf
-
-
40*
VF
0.8"
-
1.6"
Vdc
-
9.0'
Adc
trr
-
Internal Drain Inductance (Measured from the contact screw on
the header closer to the source pin and the center of the die)
Ld
Internal Source Inductance (Measured from the source pin
0.25" from the package to the source bond pad)
Ls
Input Capacitance
(VDS
Output Capacitance
f
= 25 V, VGS = 0
= 1.0 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
Turn-On Delay Time
td(on)
(VGS '" 90, 10 = 6.0 A
Zo = 15 {l)
See Figs. 1 and 2
Rise Time
Turn-Off Delay Time
tr
Fall Time
30"
ns
50*
50*
SOURCE-DRAIN DIODE CHARACTERISTICS
Diode Forward Voltage (VGS
IS = 9.0 A
=
0)
Continuous Source Current, Body Diode
IS
Pulsed Source Current, Body Diode
Forward Turn-On Time
Reverse Recovery Time
I
I
(IS
ISM
=
Rated IS, VGS
ton
= 0)
15
A
65
-
ns
325
-
-
5.0
-
-
12.5
-
INTERNAL PACKAGE INDUCTANCE (10-204)
*JEDEC registered values.
(1) Pulse Test: Puis. Width", 300 p.s, Duty Cycle" 2.0%.
MOTOROLA TMOS POWER MOSFET DATA
3-11
nH
2N6758, JTX, JTXV
RESISTIVE SWITCHING
FIGURE 1 - SWITCHING TEST CIRCUIT
FIGURE Z - SWITCHING WAVEFORMS
td(on)
Pulse Generator
...-----------,
:
Zo
I
Output. Vout
Inverted
I
I
I
I
120
VL-.....:.---_4-_-4
____..
L __________
.J
TYPICAL CHARACTERISTICS
FIGURE 3 - ON·REGION CHARACTERISTICS
16
-y"V
10 V.-T ~ V
<~I /'
/~ ~
....... fo-
VGS-20V I -
~ 12
:;;
::.
!2:
TJ = 25°C
~ 80
~
I
), ~
25°C
-55°C
5~ Vso
o
-r
I
6L-
'/
o IF
TJ = 100°C
I
10
4.0
v
r----
II II
25°C
12
~
11
S.O
10 DRAIN CURRENT (AMPS)
'"~
10
~
16
"-.,
"-.,
Q
>
~
Q
If
5
'" 090
~
A
i5
/II
i!!
;;
"",d ~
12
VOS = VGS
lo=1.0mA
"-.,
~
/I;
0
§
!:l
""
If. ~IIOOOC
'rf If
TJ = -55°C
,...-
FIGURE 6 - GATE THRESHOLD VOLTAGE
VARIA110N
FIGURE 5 - TRANSFER CHARACTERISTICS
VOS = 10
--
---- - V
L
2.0
4.0
6.0
VOS ORAIN·TO·SOURCE VOLTAGE IVOLTS)
16
,./
..----
70V
~
Q
.9 4.0
VGS= 10 V
SOV
/r
az
FIGURE 4 - ON·RESISTANCE VARIATION
.........
"- . . . . r-...
o SO
..........
:2
so
20
4.0
60
VGS ORAIN·TO·SOURCE VOLTAGE (VOLTS)
~ 0 70
~
10
-50
25
-25
100
75
50
125
150
TJ. JUNCTION TEMPERATURE (OC)
FIGURE 7 - THERMAL RESPONSE
10
0"05
~
0.5
~~
03
wz
~l
tt ~ 02
C""
002
"ca: z........ 0.0 5
",,'"
:g;
zw
e:
00
-
0.05
~ ~ 0.1
3w
3'---
0.02 - -
~
0.0 1
0.0'
,.--
....- ,......
0.02
--
--
0.1
w~
~
p-
PIPkl
lJUl
r.j
0.05
0.1
'I
!
~ 12·j
t::-ra,
...
{rrmr
RI/JCI'I riO RI/JC
RI/JC . 1 67"C/W M..
o tUfVes apply tor power
Pulse tram shown
DUTY CYCLE D:"
Read tIme at 11
TJIPkl - TC
'2
IIII
0.2
0.5
1.0
20
5.0
10
PIPkl RI/JCIO
II II
20
t. TIME Imsl
MOTOROLA TMOS POWER MOSFET DATA
3·1,2
E
50
100
200
500
1000
2N6758, JTX, JTXV
OPERATING AREA INFORMATION
FIGURE 8 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
FIGURE 9 - MAXIMUM RATED FORWARD BIAS
SAFE OPERATING AREA, 2N6758
30
20
10
Ie 7.0
~ 5.0
3.0
!Z 2.0
18
15
Ie
~
12
~
~
!is 9.0
u
z
a o.~:SI=
;;!;
'1lS(onl Lim~
.9 O.21-
Thermal Lim~
0
7
O.110.07
0.05
0.03
3.0 5.0 7.0 10
20 30
50 70 100
Ves. DRAINJfO-SOURCE VOLTAGE (VOLTSI
3.0
40
tOms
10m.
de
~ O.3f-- ---- Package Limit
~ 6.0 r-- r- TJ "'50'C
o
o
10 p.s
0.1~E==
80
120
160
200
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTSI
240
200300
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 8,
is the boundary that the load line may traverse without
incurring damage to the MOSFET. The fundamentallimits are the peak current, 10M and the breakdown voltage.
V(BR)OSS. The switching SOA shown in Figure 8 is
applicable for both turn-on and turn-off of the devices
for switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
FORWARD BIASED SAFE OPERATING AREA
The dc data of Figure 9 is based on a case temperature
(TC) of 25°C and a maximum junction temperature
(TJmax) of 150°C. The actual junction temperature
depends on the power dissipated in the device and its
case temperature. For various pulse widths, duty cycles,
and case temperatures, the peak allowable drain current
(10M) may be calculated with the aid of the following
equation:
TJmax - TC
RruC
=IO(250C) [TJmax - TC]
PO'RruC'r(t)
FIGURE 10 - CAPACITANCE VARIATION
Where
'O(25°C) =dc drain current at TC = 25°C from Figure 9
TJmax = Rated maximum junction temperature
= Device case temperature
TC
= Rated power dissipation at TC = 25°C
= Rated steady state thermal resistance
RruC
r(t)
= Normalized thermal response from Figure 7.
2000
TJ =1 2soC
vGS = 0
f=IMHz
1600
Po
~
'"",
Ciss
\\
\\
'\ l'.
400
o
o
Coso
C,..s-....
10
20
30
40
VOS. DRAlN·T(}SOURCE VOLTAGE (VOLTSI
MOTOROLA TMOS POWER MOSFET DATA
3-13
50
-
MOTOROLA
-
SEMICONDUCTOR - - - - - -
2N6759
2N6760
TECHNICAL DATA
4.5 and 5.5 AMPERE
N-CHANNEL TMOS
POWER FETs
N-CHANNEL ENHANCEMENT-MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
rDS(on) = 1.5 OHM
350 VOLTS
These TMOS Power FETs are designed for high voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds - Switching Times
SpeCified at 100°C
rOS(on) = 1.0 OHM
400 VOLTS
• Designer's Data - lOSS, VDS(on), VGS(th) and SOA Specified
at Elevated Temperature
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
• 2N6760 is Qualified to MiI-S 19500/542A
G
MAXIMUM RATINGS
Symbol
2N6759
2N676Ot
Unit
Drain-Source Voltage
Rating
VOSS
350*
400'
Vdc
Drain-Gate Voltage
(RGS = 1.0 MO)
VDGR
350*
400*
Vdc
Gate-Source Voltage
Drain Current
Continuous
Vdc
±20
VGS
u
Adc
TC
TC
= 25·C
= 100·C
Pulsed
10
10M
Total Power
Dissipation @ TC = 25·C
Derate above 25·C
Operating and Storage
Temperature Range
4.5*
3.0*
7.0
5.5*
3.5*
8.0
2. SOURCE
CASE DRAIN
Watts
Po
TJ, Tstg
STYLE 3:
PIN 1. GATE
75*
0.6*
wrc
-55* to 150*
·C
iNOTES,
'
! 1. DIMENSIONING AND TOlERANClNG PER ANSI
i
I
Y14.5M,1982.. •
2. CONTROlUNG DIMENSION: INCH.
, 3. ALL RULES AND NOTES ASSOCIATED WITH
REFERENCED TO-204M OURINE SHALL APPLY
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Junction to Ambient
Maximum Lead Temp. for Soldering
Purposes. Y,e" from case for
seconds
·CIW
R8JC
R8JA
1.67'
30'
TL
300'
·C
ON
A
8
C
0
E
F
G
H
J
•
*JEDEC registered values.
t JTX, JTXV available.
Q
R
U
V
Designer's Data for "Worst Case" Conditions
The Designer's Data Sheet permits the design of most circuits entirelv from the
information presented. Limit data - representing device characteristics boundaries
- are given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFEl' DATA
3-14
MlUMETERS
MIN
MAX
39.37
21..
6,35
8,25
1.09
0.97
1.77
tOO
3O.158SC
, ,92iISC
•
,U.8SC
11.18
3.84
<83
3.84
12.19
4.19
26.67
5,33
4.19
INCHES
1M
MAX
1.550
0S30
0250 0,325
0,038 0,043
0,055 0.070
1.187
0-430 BSe
0.215 sse
O.665BSC
0-440 0,480
0.165
0.151
tOSO
0.190
0.151
CASE 1-06
TO-204AA
0.210
OJ ..
2N6759,60
I
ELECTRICAL CHARACTERISTICS (TC
= 25"C unless otherwise noted)
I
Characteristic
Symbol
Min
Typ
Max
350
400
-
-
-
-
-
Unit
OFF CHARACTERISTICS
Orain-Source Breakdown Voltage
(VGS = 0,10 = 1.0 mAl
VBRIOSS)
2N6759
2N6760
Vdc
,
.Zero Gate Voltage Drain Current
IVOSS = Rated VOSS, 10 = 1.0 mAl
TJ = 125"C
lOSS
-
Gate-Body Leakage Current, Forward
IVGSF = 20V)
IGSSF
-
4.0'
-
100'
nAdc
Gate-Body Leakage Current, Reverse
(VGSR = 20V)
IGSSR
-
-
100'
nAdc
2.0·
1.5
-
-
-
-
-
mAde
1.0*
ON CHARACTERISTICS
Gate Threshold Voltage
(10 = 1.0 mA, VOS = VGS)
TJ = l00"C
VGS(th)
Static Orain-Source On-Resistance 11)
IVGS = 10 Vdc, 10 = 3.0 Adc)
TC = 125"C
(VGS = 10 Vdc, 10 = 3.5 Adc)
TC = 125"C
Orain-Source On-Voltage IVGS
(10 = 4.5 Adc)
(10 = 5.5Adc)
'OS(on)
2N6759
2N6760
= 10 VI 11)
VOSlon)
2N6759
2N6760
Forward Transconductance (11
IVoS = 15 V, 10 = 3.5 A)
3.5
Ohms
1.5'
3.3-
1.0'"
2.2*
Vdc
-
7.0·
-
9.0·
mhos
-
600'
pF
-
60'
-
-
30'
-
-
3.0·
9FS
Vdc
4.0·
6.7*
CAPACITANCE
I
I
I
Input Capacitance
Output capacitance
Reverse Transfer Capacitance
(VOS = 25 V,
VGS = 0
f = 1.0 MHz)
I
I
I
Ciss
Coss
Crss
I
I
I
350*
50'
20'
I
I
I
300*
SWITCHING CHARACTERISTICS
IVos = 175 V,
10 = 3.5 Adc
Zo = 15 {})
See Figs. 1 and 2
Turn-On Oelay Time
Rise Time
Turn-Off Delay Time
'd(on)
I,
Id(offl
Fall Time
If
-
ns
35'
55'
35'
SOURCE-DRAIN DIODE CHARACTERISTICS
Oiode Forward Voltage IVGS
IS = 4.5 A
IS = 6.6A
= 0)
VSO
0.70"
0.75"
2N6759
2N6760
Continuous Source Current, Body Diode
IS
2N6759
2N6760
-
Vdc
1.40·
1.50'
Adc
-
-
4.5"
5.5'
-
7.0
8.0
A
ns
2N6759
2N6760
ISM
= Rated IS,
VGS = 0)
Ion
-
250
-
Irr
-
420
-
Internal Drain Inductance (Measured from the contact
screw on the header closer to the source pin and the
center olthe die)
Ld
-
5
-
)nternal Source Inductance (Measured from the source
pin 0.25" from the package to the source bond pad)
Ls
-
12.5
-
Pulsed Source Current, Body Oiode
Forward Turn-On Time
J
Reverse Recovery Time
I
(IS
INTERNAL PACKAGE INDUCTANCE (TO-204)
*JEDEC registered values.
(1) Pulse Test
= Pulse Width =0; 300 lAS. Duty Cycle .... 2.0%.
MOTOROLA TMOS POWER MOSFET DATA
3-15
nH
2N6758,80
RESISTIVE SWITCHING
RGURE 1 "' SWITCHING TEST CIRCUIT
RGURE 2 - SWITCHING WAVEFORMS
td(on)
Pulse Generator
,...----------,
Zo
Output, Vout
I
I
Inverted
150
I
I .rt. PRF = 1.0 kHz I
120V
tp=1.0p.S
I
L __________ .J
150
Zo
TYPICAL CHARACTERISTICS
RGURE 4 - ON-RESISTANCE VARIATION
RGURE 3 - ON-REGION CHARACTERISTICS
10
8.0 V ~
/
~
25·~
t - T}
~
;::: 6.0
J
7:0 V
~
6.0 V
-
;.V
5.0 V
//
~
is
.s? 2.0
25°C
-
8
r
/
4.0
J
I--
4.0
6.0
10. ORAIN CURRENT lAMPS)
;. 60
z
I
~
I " "'"'"
I
III
;5
f--- _125°C
I
o
2.0
~
"'-.
0.90
~ 080
"'- K
r-....
~
-55°C
~V
10
8.0
VOS ; VGS
10;10mA
'"
1/1
VI/"
Q
.s? 2.0
9
...L.
TJ ; 25°C
10
§!
II
ii!
-
12
C
11
~
:=;
o
I--- :.-
V
FIGURE 6 - GATE-THRESHOLD VOLTAGE VARIATION
II
1/
.1
.~
VOS; 30 V
az 4.0
~
.-'"
VGS; 10 V
2.0
20
8.0
12
16
VOS. ORAIN-TO·SOURCE VOLTAGE IVOLTS)
RGURE 5 - TRANSFER CHARACTERISTICS
r--
../
V
0
o
80
-55o
4
4.0V
o IF
--
J1000~
-;.--
1. 2
IV'
4.0
TJ
6
I/~ V
15
~
1/
V
.?-"
VGS = 10V
8.0
.0
I
4.0
60
80
VG.)!... GATE·TO·SOURCE VOLTAGE IVOlTS)
~0.70
10
~
"-
'-
-50
25
-25
50
75
100
125
150
TJ. JUNCTION TEMPERATURE 1°C)
RGURE 7 - THERMAL RESPONSE
1.0
O· 0.5
0.5
-
~l
0.3
0.2
I-
0.1
0.05
0.1
3-
10"
::;;..0'
I--~
P1pk)
0.05
0.0
t--
0.02~
0.0 1
V-
0.01
I--"
0.05
0.1
Pulse tram shown
Read rime at 11
TJlpk) _. TC; Plpk) R8JCI1)
DUTY CYCLE D = '\ ']
I I I 1lIT
IIIII
0.2
0.5
1.0
2.0
5.0
10
20
t, TIME (ms)
MOTOROLA TMOS POWER MOSFET DA1.'A
3-16
F
o curves apply tor power
'"r r-'] •I
I<'"
p.Ql.
-- 'Isrrmr
0.02
R9JCIII - rill R.JC
R8JC - 1.67°C/W Ma,
lJUl
0.02
50
100
200
500
1000
2N6759. fO
OPERATING AREA INFORMATION
FIGURE 9 - MAXIMUM RATED swrTCHING
SAFE OPERAnNG AREA
FIGURE 8 - MAXIMUM RATED FORWARD BIAS
SAFE OPERAnNG AREA. 2NI759
10
10
10,..
i -
0.1 ms
5.0
3.0
... 2.0
~
~
1.0
c..>
z
tOms r......
"
10ms
=----
~ 0.5 - '
PACKAGE LIMn:
lHERMAI. UMIT
90.3 -VGS :. 20 V. SlNGl.E PULSE
0.2 -TC=25"C
2N6759_
de
2N6760TJ '" 15O"C
II
0.1
20
10
30
50
100
200 300
500
Vos. DRAlN·TO-SOURCE VOLTAGE (VOLTSI
o
o
1000
-
100
200
300
400
Vos. ORAIN·TO-SOURCE VOlTAGE (VOLTSI
500
RGURE 10 - MAXIMUM RATED FORWARD BIAS
SAFE OPERAnNG AREA. 2N6760
10
10,..
in
i
!Z
3.0
2.0
a
1.0
""I..
......
tOms
Il!
I
90.3
O.2
r.....
10ms r......
~--- PACKAGE UMIT
0.5
swrrCHING SAFE OPERAnNG AREA
The switching safe operating area (SOA) of Figure 9,
is the boundary that the (oad line may traverse without
incurring damage to the MOSFET. The fundamental limits are the peak current, 10M and the breakdown voltage,
V(BR)OSS. The switching SOA shown in Figure 9 is applicable for both turn-on and turn-off of the devicas for
switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
0.1 ms
5.0
r-
de
lHERMAL UMIT
I- VGS = 20 V. SINGLE PULSE
r- TC = 25"C
TJmax - TC
R/lJC
II
O. 1
10
20 30
50
100
200 300
Vos. ORAIN·TO-SOURCE VOLTAGE (VOLTSI
500
FORWARD BIASED SAFE OPERATING AREA
The dc data of Figures 8 and 10 are based on a case
temperature (Td of 26"C and a maximum junction temperature (TJmax) of 150"C. The actual junction temperature depends on the power dissipated in the device
and its case temperature. For various pulse widths, duty
cycles, and case temperatures, the peak allowable drain
current (10M) may be calculated with the aid of the following equation:
10M
FIGURE 11 - CAPACITANCE VARIATION
2000
TJ =125"C
vGS = 0
f= 1 MHz
1600
= 10(25°C) [ TJmax - TC ]
Po . R/IJC . r(t)
.\
Where
10 (25°C) = dc drain current at TC = 25°C from
Figure 8 or 10
TJmax = Rated maximum junction temperature
= Oevica case temperature
TC
= Rated power dissipation at TC = 25°C
Po
= Rated steady state thermal resistance
R/lJC
r(t)
= Normalized thermal response from Figure 7.
C;ss
400
l\
\\
'\ '-
o
o
.Cn..
C..........
W
20
30
~
Vos. ORAIN·T()'SOURCE VOLTAGE (VOLTSI
MOTOROLA TMOS POWER MOSFET DATA
3-17
50
-
MOTOROLA
•
SEMICONDUCTOR - - - - - _
TECHNICAL DATA
2N6762
4.5 AMPERE
N-CHANNEL ENHANCEMENT-MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
N-CHANNEL TMOS
POWER FET
These TMOS Power FETs are designed for high voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
rOSlon) = 1.5 OHMS
500 VOLTS
• Silicon Gate for Fast Switching Speeds Specified at 100°C
Switching Times
• Designer's Data -lOSS, VDS(on), VGS(th) and SOA
Specified at Elevated Temperature
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
,r
• 2N6762 is Qualified to 19500/542A
G
L~:4~
TMDS
MAXIMUM RATINGS
Rating
Drain-Source Voltage
Drain-Gate Voltage
(RGS = 1.0 MO)
Gate-Source Voltage
Drain Current
Continuous TC = 2SoC
TC = 100"C
Pulsed
Symbol
Valuet
Unit
VOSS
SOO"
Vdc
VDGR
SOO"
Vdc
VGS
±20
Vdc
10
10M
4.S"
3.0*
7.0*
Operating and Storage Temperature Range
.
=c~
K
1.. 10.1310.0051® rlv®la®1
F
u
1STYI.E3:
PIN 1. GAlE
Po
7S*
0.6"
Watts
WFC
TJ, Tsta
-55* to 150'
"C
THERMAL CHARACTERISTICS
Maximum Lead Temp. for Soldering
Purposes, 1/16" from case for seconds
--II--D '"
Adc
Total Power Dissipation @ TC = 2S"C
Derate above 2S"C
, Thermal Resistance
Junction to Case
Junction to Ambient
T
r:-
"C/W
R8JC
R6JA
1.67"
30"
TL
300"
2. SOURCE
CASE DRAIN
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M.1982.
2. CONTROLLING DIMENSION: INCH.
3. ALL RULES AND NOTES ASSOCIATED WITH
REFERENCED TO-204M OURINE SHAll APPLY.
DI!
•
"C,
:
:
JEDEC registered values .
t JTX. JTXV available.
B
C
0
E
F
G
H
J
K
Q
,
Design..... Data for "Worst Cas." Conditions
The Designer's Data Sheet permits the design of most circuits entirely from
the information presented. Limit data - representing device characteristics
boundaries - are given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
3-18
R
U
V
MIUMTEAS
!IN
MAX
39.37
21.08
B.35
INCES
MIN
MAX
I.""
0830
a25
0.250
0.97
1.09
lAO
1.77
3Il.15BSC
10.92BSC
5.46BSC
16.898SC
11.18
12.19
3.64
4.19
26.67
0.038
4."
3.64
5.33
4.19
0.005
0.325
0.043
0.070
1.187BSC
O.430BSC
0.215BSC
0.665 BSC
0.440
0.480
0.151
0.166
0.190
0.151
0.210
0.166
1.1150
CASE '-06
TO-Z04AA
2N6762, JTX, JTXV
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise notedl
I
Characteristic
Symbol
Min
Typ
Max
Unit
VBR(OSSI
500
-
-
Vdc
-
-
OFF CHARACTERISTICS
Orain-Source Breakdown Voltage
(VGS = 0, 10 = 4.0 mAl
Zero Gate Voltage Orain Current
(VOSS = Rated VOSS, 10 = 1.0 mAl
TJ = 125°C
lOSS
Gate-Body Leakage Current, Forward
(VGSF = 20 Vdcl
IGSSF
-
Gate-Body Leakage Current, Reverse
(VGSR = 20 Vdcl
IGSSR
mAde
1.0*
4.0*
-
100*
nAdc
-
-
100*
nAdc
2.0*
1.5
2.7
2.2
4.0*
3.5
-
-
7.7*
Vdc
7.5*
mhos
pF
ON CHARACTERISTICS
Gate Threshold Voltage
(10 = 1.0 rnA, VOS = VGSI
TJ = 100"C
VGS(thl
Static Orain-Source On-Resistance (11
(VGS = 10 Vdc, 10 = 3.0 Adcl
TC = 125°C
rOS(onl
=
Orain-Source On-Voltage (VGS
(10 = 4.5 Adc)
10 VI (1)
Forward Transconductance (1)
(VOS = 15 V, 10 = 3.0 A)
Vdc
VOS(on)
-
9FS
2.5*
Ohms
1.5*
3.3*
CAPACITANCE
Input Capacitance
(VOS = 25 V, VGS = 0
f = 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
Ciss
350*
-
800*
Coss
25*
-
200'
Crss
15"
-
60*
-
-
30*
tr
-
30"
Id(off)
-
-
55*
tf
VSO
0.7*
SWITCHING CHARACTERISTICS
Turn-On Oelay Time
td(on)
(VOS
Rise Time
Turn-Off Oelay Time
=
225 V, 10 = 3.0 Adc
Zo=150)
See Figs. 1 and 2
Fall Time
ns
30*
SOURCE-DRAIN DIODE CHARACTERISTICS
Oiode Forward Voltage (VGS = 0)
IS = 4.5A
1.15"
1.4"
Vdc
-
4.5*
Adc
-
7.0
A
ns
IS
-
ISM
-
ton
-
250
trr
-
-
420
-
Internal Orain Inductance (Measured from the contact screw on
the header closer to the source pin and the center of the die)
Ld
-
5.0
-
Internal Source Inductance (Measured from the source pin
0.25" from the package to the source bond pad)
ls
-
12.5
-
Continuous Source Current, Body Oiode
Pulsed Source Current, Body Oiode
Forward Turn-On Time
Reverse Recovery Time
I
I
(Is = Rated IS, VGS = 0)
INTERNAL PACKAGE INDUCTANCE (TO-204)
*JEDEC registered values.
(11 Pulse Test: Pulse Width" 300
p.O,
Duty Cycle" 2.0%.
MOTOROLA TMOS POWER MOSFET DATA
3-19
nH
2N6762, JTX, JTXV
RESISTIVE SWITCHING
RGURE 1 - SWITCHING .TEST CIRCUIT
FIGURE 2 - SWITCHING WAVEFORMS
. 'd(on)
Pulse Generator
Output, Vout
Inverted
r - - - r ..... - - - - - - ,
I
I
I
I
150
Zo
..J1... PRF = 1.0 kHz I
I
120V
150
I
tp=I.0ps
L __________ ..J
TYPICAL CHARACTERISTICS
FIGURE 3 - ON-REGION CHARACTERISTICS
80
T~ = 251c
-
VGS= 10V~
/~
~
I
~
~
I
I
V-
I
I
25°C
8
4.0 V
0
2.0
20
,
C
/J
VOS=30V
l12
i1!
./1..
TJ = 100°C
~
~
l- r;-. ~
0
2.0
8.0
10
VOS = VGS
10=10mA
""" "'" "'-..
10
'"
~ 0.90
25°C
H
VGS= 10V
~
S!
III
So
I
4.0
6.0
10. ORAIN CURRENT (AMPS)
............
11
'"'!!:.
1.1
...z
:'" 2.0
-I-- r-
12
::::
;j!
~
4.0
,...- .-
RGURE 6 - GATE THRESHOLD VOLTAGE
VARIATION
FIGURE 5 - TRANSFER CHARACTERISTICS
in 6.0
/"
:..-" I-'"
-55°C
4
8.0
./
I
5.0J
40
80
12
16
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)
..- ./"
~
6.0 V
L
o
~
1000~
2
Lv
o
I
T)
6
7.0 V
.LV ~
~
FIGURE 4 - ON-RESISTANCE VARIATION
.0
oz:
i!'
"'"-
~ 080
f---55°C
to
4.0
6.0
8.0
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
:c
~ 0 70
10
-50
>
25
-25
50
15
'"
100
....,
.........
125
150
TJ. JUNCTION TEMPERATURE (0C)
RGURE 7 - THERMAL RESPONSE
1.0
0·0.5
0.5
w
>
~
..
~j
O.J
0.2
N
0.1
~
0.05
:::;
'"z
-
0.1
'"w
0.05
rr-::
f-f--
0.02
P'"
~
P1pkl
~'I~
~
............
0.02~
~.01
0.0Jt""":
V
0.0 1
0.01
- ....
-lJUl
0.02
f-- ']
...
fITlllf
0.05
0.1
R9JC(I) = ~I) R9JC
R9JC = 1.67"CIW Max
Dcurves apply for power
Pulse lrain shown
Read lime at 11
TJ(pk) - TC = P(pk) R9JC(I)
!
·1
DUTY CYCLE 0 = 'I ']
0.2
0.5
10
so
20
t,
TIME
I Jl
10
20
(ms)
MOTOROLA TMOS POWER MOSFET DATA
3-20
so
I "100
200
500
1000
2N6762, JTX, JTXV
OPERATING AREA INFORMAnoN
FIGURE 8 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
FIGURE 9 - MAXIMUM RATED FORWARD BIAS
SAFE OPERATING AREA, 2N6762
10
0
10 p.s
-
I'.
1.0ms r-....
""" "
0
0
Or--
0.1 ms
Tj"" l5O"C
10ms~
- - - Package Limit
Thermal Limit
0
.....
t-.....
VGS = 20 V, Single Pulse
TC
O. 1
0
100
200
300
400
VOS. DRAIN-TD-SOURCE VOLTAGE (VOLTSI
~ 2~OC
20
10
500
~
'-
~
11. _1.1..1
30
50
100
200 300
Vos. DRAIN-TO-SOURCE VOLTAGE (VOLTSI
500
1000
SWITCHING SAFE OPERAnNG AREA
FORWARD BIASED SAFE OPERAnNG AREA
The switching safe operating area (SOA) of Figure 8,
is the boundary that the load line may traverse without
incurring damage to the MOSFET. The fundamental limits are the peak current, 10M and the breakdown voltage,
V(BR)OSS. The switching SOA shown in Figure ~ is
applicable for both turn-on and turn-off of the deVices
for switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
The dc data of Figure 9 is based on a case temperature
(Tel of 25°C and a maximum junction temperature
(TJmax) of 150°C_ The actual junction temperature
depends on the power dissipated in the device and its
case temperature_ For various pulse widths, duty cycles,
and case temperatures, the peak allowable drain current
(10M) may be calculated with the aid of the following
equation:
10M
Where
IO(25OC)
TJmax
TC
Po
Rruc
r(t)
TJmax - TC
RruC
=1 (25°C) [TJmax - TC]
o
Po-Rruc-r(t)
=dc drain current at TC = 25°C from Figure 9
= Rated maximum junction temperature
= Device case temperature
=Rated power dissipation at TC = 25°C
= Rated steady state thermal resistance
= Normalized thermal response from Figure 7_
RGURE 10 - CAPACITANCE VARIATION
2000
TJ =1 2S0C
VGS = 0
f = 1 MHz
1600
1\
Ciss
~\
400
\\
"\ I'..
o
o
Coss
C........
10
20
30
40
Vos. DRAIN-TO-SOURCE VOLTAGE (VOLTSI
MOTOROLA TMOS POWER MOSFET DATA
3-21
50
MOTOROLA
• SEMICONDUCTOR
TECHNICAL DATA
Designer's Data Sheet
2N6764
Power Field Effect Transistor
N-Channel Enhancement-Mode
Silicon Gate TMOS
TMOS POWER FET
38 AMPERES
'OS(on)
0.055 OHM
This TMOS Power FET is designed for low
voltage, high speed power switching applications
such as switching regulators, converters, solenoid
and relay drivers.
=
100 VOLTS
• Silicon Gate for Fast Switching SpeedsSwitching Times Specified at 100'C
• Designer's Data -lOSS, VOS(on}, VGS(th} and
SOA Specified at Elevated Temperature
• Rugged - SOA is Power Dissipation limited
• Source-to-Orain Diode Characterized for Use With
Inductive Loads
• 2N6764 is Qualified to Mil-S 19500/543A
G
CASE 197A-02
TO-204AE
MAXIMUM RATINGS
Symbol
Valuet
Unit
Drain-Source Voltage
VOSS
100"
Vdc
Drain-Gate Voltage
(RGS = 1 MOl
VOGR
100"
Vdc
VGS
±20
Vdc
10
10M
38*
24"
70*
Rating
Gate-Source Voltage
Drain Current
Continuous TC
TC
Pulsed
Adc
= 25'C
= 100'C
Total Power
Dissipation @ Tc = 25'C
TC = 100'C
Derate above 25'C
Watts
Po
Operating and Storage Temperature Range
150*
60*
1.2*
wrc
TJ, Tstg
-55* to 150'
'c
R8JC
R8JA
0.83'
30'
TL
300'
J
THERMAL CHARACTERISTICS
'CIW
Thermal Resistance
Junction to Case
Junction to Ambient
Maximum Lead Temp. for Soldering Purposes,
1/16" from case for seconds
'c
*JEDEC registered values.
t JTX, JTXV available.
Deaigner'a Data for "Worst Cue" Conditions - The Designer's Data Sheet permits the design of most circuits entirely from the information presented.
Limit curves - representing boundaries on device characteristics - are given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
3-22
2N6764, JTX, JTXV
ELECTRICAL CHARACTERISTICS (TC = 25"C unless otherwise noted)
I
I
Symbol
Min
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 1 mAl
VBR(OSS)
100
-
Zero Gate Voltage Drain Current
(VOSS = Rated VOSS)
TJ = 125"C
lOSS
-
100'
nAdc
100"
nAdc
Characteristic
Typ
Max
Unit
OFF CHARACTERISTICS
Gate-Body Leakage Current, Forward
(VGSF = 20 V)
IGSSF
-
Gate-Body Leakage Current, Reverse
(VGSR = 20 V)
IGSSR
-
-
2"
1.5
-
-
Vdc
mAde
1"
4"
ON CHARACTERISTICS
Gate Threshold Voltage
(10 = 1 mA, VOS = VGS)
TJ = 100"C
VGS(th)
Static Drain-Source On-Resistance(l)
(VGS = 10 Vdc, 10 = 24 Adc)
TC = 125"C
rOS(on)
=
Drain-Source On-Voltage (VGS
(10 = 38 Adc)
VOS(on)
-
-
9FS
9"
Ciss
-
-
10 V)(l)
Forward Transconductance(l)
(VOS = 15 V, 10 = 24 A)
-
Vdc
4"
3.5
Ohms
0.055'
0.094'
2.09"
Vdc
-
27'
mhos
1000'
-
3000'
pF
Coss
500'
-
1500'
Crss
150'
-
500'
-
100'
CAPACITANCE
Input Capacitance
(VOS
Output Capacitance
=
25 V, VGS
f = 1 MHz)
=
0
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
Turn-On Delay TIme
!d(on)
(VOS = 24 V, 10 = 24 Adc
Zo = 4.7 il)
See Figs. 9 and 10
Rise Time
Turn-Off Delay Time
tr
Fall Time
-
35'
ns
td(off)
-
-
125'
tf
-
-
100'
VF
0.95"
-
1.9"
Vdc
-
-
38"
Adc
SOURCE-DRAIN DIODE CHARACTERISTICS
Diode Forward Voltage (VGS
IS = 38A
=
0)
Continuous Source Current, Body Diode
IS
Pulsed Source Current, Body Diode
Forward Turn-On Time
Reverse Recovery Time
I
I
(IS
ISM
= Rated IS, VGS =
ton
0)
trr
70
200
-
5
-
12.5
-
85
A
ns
INTERNAL PACKAGE INDUCTANCE (TO-204)
Internal Drain Inductance (Measured from the contact screw on
the header closer to the source pin and the center of the die)
ld
Internal Source Inductance (Measured from the source pin
0.25" from the package to the source bond pad)
Ls
-
*JEOEC registered values.
(1)
Puis. Test: Pulse Width" 300 1'8. Duty Cycle" 2.0%.
MOTOROLA TMOS POWER MOSFET DATA
3-23
nH
2N6764, JTX, JTXV
TYPICAL CHARACTERISTICS
iJvl.
10~"'"
1/ /
I
I
'II
//
,
7{
25'C
I
55'C
6V
~
I
I.
o
o'
TJ = 125'C
8V
VGS 1 5V
TJ = 25'C
2
4
6
VOS, DRAIN·TO·SOURCE VOLTAGE IVOLTS)
10
10
Figure 1. On-Region Characteristics
32
v~=lL
i
/I
If
~
o
o
25~ "r//
55~0 /
~
2
4
1.20
............
1.10
~
""'" """
w
~9
VI
j
V
~ 0.90
~
8
10
J0.7~50
Figure 3. Transfer Characteristics
~
""" r--...
r--......
"-
..... ~
.......
o
-25
25
50
75
100
TJ, JUNCTION TEMPERATURE I'C)
Vm;, GATE·TO·SOURCE VOLTAGE IVOLTS)
125
150
Figure 4. Gate Threshold Voltage Variation
0.30
0.20
I
'"
I--+-+-+ 0.10
i
O.OS
!!1
>!'
I
6
15
Figura 4. On-Resistance Variatfon
'/
28
0
= 10V
0.08
~
.4f.
2
\25OC
~
1//
If
§
g
...........
""" '-....
~
~
m0.90
!ii
VJ/
VDS = VGS
ID = lmA
~
r-....
0.80
......i'...
C>
~~
4
6
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
.........
!0.70
10
>
Figure 5. Transfer Characteristics
- 50
-25
0
25
50
75
100
TJ. JUNCTION TEMPERATURE I"C)
125
Figure 6. Gate-Threshold Voltage Variation
MOTOROLA TMOS POWER MOSFET DATA
3-29
1~
2N1788, JTX, JTXV
TYPICAL CHARACTERISTICS
/
Ii
0.20
Iil
Ii! 0.10
0.10
I
0.05
~
PrlPklJUl R8JC(t) rill R8JC
R8JC 0.83'CIW MAX
DCURVES APPLY FOR POWER
i.-
I
~±:t::ts~'GtE~tffl,...-:J---=±=t::J:±±±lli=Cf=±=[±±±±H:
J:.
SI~G'TLE ~U,U:~t--t-t--+-H+++++-H-Hf+++1+I-
~
0.01
I
0.01
I I II
~~~I
~~~
I--t2--1
READ TIME ATt,
DUTY CYCLE. D = tln2 TJlpkl - TC = p(pIt) R8JC(tl
I I
I I
f I 111I
10
0.10
I I
I I I I I
1k
100
t. TIME Imsl
Figure 7. Thermal Response
OPERATING AREA INFORMATION
80
10/LS
V
100•
le
:0
,
10
5
~
:::>
u
~
0
1
r=:tc.
.!?
40
80
120
160
VOS. ORAIN·TO.sOURCE VOLTAGE IVOLTSI
O. 1
0.5
200
oi\
\
~
I
"
=
Ciss
\ '\:
o
o
25°C
25°CVGS = 0
f= 1 MHz-
I'
"-
10
.....
5 7 10
20
50 70 100 200
VDS. DRAIN-TO·SOURCE VOLTAGE (VOLTSI
JTJ
4000
\
10/LS
Figure 9. Maximum Rated Forward Biased
Safe Operating Area
F1ture t. Maximum Rated Switching
Safe Operating Area
300
THERMAL LIMIT
20 V. SINGLE PULSE
~VGS
c
TJ'" 15O"C
.......
=
. - 'OS(onl LIMIT
_-------PACKAGE LIMIT, =J:d'tCm1It:t1=t:t1
z>-
0
lm~ O.lm.
•
t--- Coss
r-- f--
Crss
20
30
40
VDS. DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 10. Capacitance Variation
MOTOROLA TMOS POWER MOSFET DATA
3·30
50
500
2N6766, JTX, JTXV
TYPICAL CHARACTERISTICS (continued)
OPERATING AREA INFORMATION (continued)
FORWARD BIASED SAFE OPERATING AREA
The dc data of Figure 9 is based on a case temperature
(Tel of 25°C and a maximum junction temperature
(TJmax) of 150°C. The actual junction temperature
depends on the power dissipated in the device and its
case temperature. For various pulse widths, duty cycles,
and case temperatures, the peak allowable drain current
(lDM) may be calculated with the aid of the following
equation:
L~:~
T
lei
[W:"
I
--II-- D "..
10M
= I (25°C) [TJ(max) - TC]
D
K
1+1<1>0,3010,0121
PD-ROJc-r(t)
r------F-
r-
Where
ID(25°C) = dc drain current at TC = 25°C from Figure
9.
TJmax = Rated maximum junction temperature
= Device case temperature
TC
= Rated power dissipation at TC = 25°C
PD
= Rated steady state thermal resistance
R9JC
r(t)
= Normalized thermal response from Figure 7
J-
/.
HVt~
{~--.! - ~
H
,
®ITI Q ®I u ®I
rOO
G
~
t
1+1<1>0,2510,0101
t
1
l"
®ITI u ®I
NOTES:
1, DIMENSIONING AND TOlfRANCING P£R ANSI
YI4,5M,1982,
2, CONTROLLING DJMENSION: INCH,
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 8,
is the boundary that the load line may traverse without
incurring damage to the MOSFET. The fundamental limits
are the peak current, 10M and the breakdown voltage,
V(BR)DSS. The switching SOA shown in Figure 8 is applicable for both turn-on and turn-off of the devices for
switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
STYLE 2:
~N 1. EMlnER
2, BASE
CASE, COLLECTOR
DIM
A
TJmax - TC
ROJC
B
C
0
E
F
G
H
J
K
Q
R
U
MlWMETERS
MIN
MAX
38,36 39,37
21,08,
1931
6,35
8,25
1,60
1.45
1.77
1.53
JQ,15BSC
10,92BSC
5,45 BSC
16,B9BSC
l1.1B 12,19
3,84
4,19
25,15 26,67
3,84
4,19
INCHES
MIN
MAX
1,510 1.550
0.760 0,830
0,250 0,325
0,057 0,063
0,060 0,070
1.187 BSC
0,430 BSC
0,215BSC
O,66!iBSC
0,440 0,480
0,151 0,165
0,990 1.060
0,151 0,165
CASE 197A-ClZ
TO-204AE
MOTOROLA TMOS POWER MOSFET DATA
3-31
• MOTOROLA
SEMICONDUCTOR -
_ _ _ _ _ _ _ _ _ _ __
TECHNICAL DATA
2N6768
Designer's Data Sheet
Power Field Effect Transistor
N-Channel Enhancement-Mode
Silicon Gate TMOS
TMOS POWER FET
14 AMPERES
..oS(on) = '0.3 OHM
400 VOLTS
,
These TMOS Power FETs are designed for high
voltage, high speed power switching applications
such as switching regulators, converters, solenoid
and relay drivers.
• Silicon Gate for Fast Switching Speeds Switching Tim.es Specified at lOO°C
• Designer's Data -lOSS, VDS(on), VGS(th) and
SOA Specified at Elevated Temperature
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With
Inductive loads
• 2N6768 is Qualified to Mil-S 19500/543A
CASE 1-0&
TO·204AA
MAXIMUM RATINGS
Symbol
Valuet
Unit
Orain·Source Voltage
Rating
VOSS
400*
Vdc
Orain·Gate Voltage
(RGS = 1 MO)
VOGR
400*
Vdc
VGS
±20
Gate·Source Voltage
Drain Current
Continuous TC
TC
Pulsed
Vdc
Adc
= 25°C
= 1000C
10
10M
Total Power
Dissipation @ TC = 25°C
TC = 100°C
Derate above 25°C
14*
9*
25*
Watts
Po
Operating and Storage Temperature Range
150*
60*
1.2*
Wf'C
TJ, Tstg
-55* to 150'
°c
R8JC
R8JA
0.83*
30'
TL
300*
THERMAL CHARACTERISTICS
OC/W
Thermal Resistance
Junction to Case
Junction to Ambient
Maximum Lead Temp. for Soldering Purposes,
1/16" from case for seconds
°c
*JEDEC registered values.
t JTX, JTXV available.
Designe"s DatIl for "Worst c.,se" Conditions - The Designer's Data Sheet permits the design of most circuits entirely from the information presented.
Umit curves - representing boundaries on device characteristics - are given to facilitate "worst case" design.
MOTOROLA.TMOS POWER MOSFET DATA
3·32
2N6768, JTX, JTXV
ELECTRICAL CHARACTERISTICS (TC = 25"<: unless otherwise noted)
I
I
Characteristic
Symbol
Min
Typ
Max
Unit
VBR(OSS)
400
-
-
Vdc
-
I"
4"
-
100*
nAdc
nAdc
OFF CHARACTERlSncs
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 1 mAl
Zero Gate Voltage Drain Current
(VOSS = Rated VOSS, VGS = 0)
TJ = 125°C
lOSS
Gate-Body Leakage Current, Forward
(VGSF = 20 V)
IGSSF
-
Gate-Body Leakage Current, Reverse
(VGSR = 20 V)
IGSSR
-
-
100*
2*
1.5
-
4*
3.5
mAdc
ON CHARACTERISTICS
Gate Threshold Voltage
(10 = 1 mA, VOS = VGS)
TJ = lOO"C
VGS(th)
Static Drain-Source On-Resistance(l)
(VGS = 10 Vdc, 10 = 9 Adc)
TC = 125'C
'OS (on)
Drain-Source On-Voltage (VGS = 10 V)(I)
(10 = 14 AdcL
Forward Transconductance(l)
(VOS = 15 V, 10 = 9 A)
VOS(on)
-
9FS
8*
Vdc
Ohms
-
-
0.3*
O.SS*
-
5.S·
Vdc
-
24*
mhos
3000*
pF
CAPACITANCE
Input Capacitance
(VOS = 25 V, VGS = 0
f=IMHz)
Output Capacitance
Reverse Transfer Capacitance
Ciss
1000*
Coss
200*
Crss
50*
-
tr
-
-
S5*
td(off)
-
-
150*
tf
-
-
75*
VSO
0.85*
IS
-
-
ISM
-
-
SOO*
200*
SWITCHING CHARACTERISTICS
Turn-On Delay Time
Id(on) .
(VOS = 180 V, 10 = 9 Adc
Zo = 4.70)
See Figs. 1 and 2
Rise Time
Tum-Off Delay Time
Fall Time
35*
ns
SOURCE-DRAIN DIODE CHARACTERISTICS
Diode Forward Voltage (VGS = 0)
(IS = 14)A
Continuous Source Current, Body Diode
Pulsed Source Current, Body Diode
Forward Turn-On Time
Reverse Recovery Time
I
I
ton
(IS = Rated IS, VGS = 0)
trr
-
1.7*
Vdc
14*
Adc
25
A
ns
SOO
-
5
-
nH
12.5
-
175
INTERNAL PACKAGE INDUCTANCE (TO-204)
Internal Drain Inductance (Measured from the contact screw on
the header closer to the source pin and the center of the die)
Ld
Internal Source Inductance (Measured from the source pin
0.25' from the package to the source bond pad)
Ls
-
*JEDEC registered values.
(1) Pulse rest: Pulse Width .. 300 I'S, Duty Cycle .. 2.0%.
MOTOROLA TMOS POWER MOSFET DATA
3-33
2N6768, JTX, JTXV
RESISTIVE SWITCHING
RJ :~D
'd(on)
~ut
DUT
PULSE GENERATOR
r- -- -- ---,
I
Zo
I
I
OUTPUT. Vout
INVERTED
4.7{}:
Zo
: .I1.
PRF = 1 kHz!
I
1p=1!'S I
L.:
I 20_______
V
..JI
4.7 {}
Figure 1. Switching Test Circuit
Figure 2. Switching Waveforms
TYPICAL CHARACTERISTICS
20
~
VGS = 20V_ ~
10V8VA
TJ ='25"<:
,
W~
f-/""
/
7V
~
z
W
6V
lib . /
'"""~
~
0.50
r-- -VG~ = lov
TJ
0.40
~
5V
II.
~
Z
4
5
7
I
20
14
,,; 12
!Z
~
IX:
a
~
o
J5°C
V
V
,
,
8
12
10. DRAIN CURRENT
20
16
24
Figura 4. On-Resistance Variation
II /I
T = -55°clI
10
8
I
6
""'" ~ ~
l1000C
III
VII
II I
VDS = VGS
10= 1 rnA
:""-..
""'-
/1
.9 4
o
o
V
f 1/25°CV
18
16
V
i5°C
~~
0.20
10
Figure 3. On-Rag ion Characteristics
,/
--r-
~ 0.10
o
4V
.,.-
= 125°C
~ 0.30
.4"
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
~
V
z
o
~~
o IY
o
0.60
§
"-.
i'......
I}'
~
2345678
VGS. GATE·TO-SOURCE VOLTAGE (VOLTS)
o
25
50
75
100
TJ. JUNCTION TEMPERATURE (OC)
10
FiguraS. Transfer Characteristics
',,125
Figure 6. Gate-Threshold Voltage Variation
MOTOROLA TMOS POWER MOSFET DATA
3-34
.......
150
2N6768, JTX, JTXV
~ ~ D 0.5
-
0.3
0.2
~V
.....
0.1
-~
Plpkl
R8JCltl ritl R8JC
R8JC 0.83'CWMAX
DCURVES APPLY FOR POWER
PULSE 'TRAIN SHOWN
READ TIME AT tl
DUTY CYCLE, D = tlh2 TJlpkl - TC = Plpkl R8JCltl
O.OS
~ I-"'
I
=
f.JlJ1.
....
-tG'=l
SliGiE IUIL~EI
I I
I I I I II"
I I
I I I II
100
10
0.1
1k
t, TIMElmsl
Figure 7. Thermel Response
OPERATING AREA INFORMATION
25
100
r-.
0
lr;;;..,
10~t
0.1 ms
10 ms
.£..
-
roSlonl LIMIT - - - - - PACKAGE LIMIT
THERMALUMIT
1
TJ"" 151rC
----
._-
_. -
de
......
=yG~ ,20,V, SINGLE PULSE
-TC - 2S'C
100
200
300
VDS, DRAIN·TO-SOURCE VOLTAGE IVOLTSI
O. 1
400
1,
Figure 8. Maximum Rated Switching
Safe Operating Area
3
5
10
30 50 100
300 SOO
VOS, DRAIN-TO·SOURCE VOLTAGE (VOLTSI
1000
Figure 9. Meximum Rated Forward Biased
Safe Operating Area
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 8,
is the boundary that the load line may traverse without
incurring damage to the MOSFET. Thefundamentallimits
are the peak current, 10M and the breakdown voltage,
V(BR)OSS' The switching SOA shown in Figure 8 is appli-
cable for both turn-on and turn-off of the devices for
switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
TJmax - TC
R8JC
MOTOROLA TMOS POW{::R MOSFET DATA
3·35
2N6768. JTX. JTXV
2500
\.
1\
\
500
r--
\
\ f'....
"-
FORWARD BIASED SAFE OPERATING AREA
The dc data of Figure 9 is based on a case temperature
(Tel of 25°C and a maximum junction temperature
(TJmax) of 150°C. The .actual junction temperature
depends on the power dissipated in the device and its
case temperature. For various pulse widths, duty cycles,
and case temperatures, the peak allowable drain current
(10M) may be calculated with the aid of the following
equation:
Ciss
-
=
Coss
C...
16
24
32
VOS. DRAIN·TO-SOURCE VOLTAGE (VOLTSI
I (250C) [TJ(max) - TC]
o
Po'R8Jc'r(t)
Where
IO(25°C) = dc drain current at TC = 25°C from Figure
9.
TJmax = Rated maximum junction temperature
= Device case temperature
= Rated power dissipation at TC = 25°C
Po
= Rated steady state thermal resistance
R8JC
r(t)
= Normalized thermal response from Figure 7
40
rC
Figure 10. Capacitance Variation
CASE 1-0&
TO-204AA
STYlE"
AN 1. GATE
2. SOUftCE
CASe DRAIN
...
liN
NOTES,
1. DIMENSiONING AND TOLERANClNG PER AN~
-.iliiIi
OJ
2.
~=NG DIMENSION, INCH.
"
,. AU RULES AND NOTES ASSDClATED WlTH
REFERENCED TO-2D4AA OuruNE SHALl _Y.
-
----
--=-
J
UJii)
MOTOROLA TMOS POWER MOSFET DATA
3-36
MOTOROLA
•
SEMICONDUCTOR - - - - - - - - - - - - - -
TECHNICAL DATA
Designer's Data Sheet
2N6770
Power Field Effect Transistor
N-Channel Enhancement-Mode
Silicon Gate TMOS
TMOS POWER FET
12 AMPERES
rDSlon)
0.4 OHM
500 VOLTS
These TMOS Power FETs are designed for high voltage, high speed power switching applications such
as switching regulators, converters, solenoid and relay drivers.
=
• Silicon Gate for Fast Switching SpeedsSwitching Times Specified at 100·C
• Designer's Data -lOSS, VOS(on), VGS(th) and
SOA Specified at Elevated Temperature
• Rugged - SOA is Power Dissipation Limited
• Source-to-Orain Diode Characterized for Use With
Inductive Loads
• 2N6770 is Qualified to MiI-S 19500/543A
CASE 1-06
TO-2D4AA
MAXIMUM RATINGS
Symbol
Valuet
Unit
Drain-Source Voltage
VOSS
500'
Vdc
Drain-Gate Voltage
IRGS = 1 MO)
VDGR
500'
Vdc
VGS
±20
Rating
Gate-Source Voltage
Drain Current
Continuous TC
TC
Pulsed
Vdc
Adc
= 25·C
= l00·C
10
10M
Total Power
Dissipation @ TC = 25·C
TC = 100·C
Derate above 25·C
12"
7.75'
25'
Watts
Po
Operating and Storage Temperature Range
150'
60'
1.2"
wrc
TJ, Tstg
-55* to 150'
·C
ROJC
R6JA
0.83'
30'
TL
300'
THERMAL CHARACTERISTICS
·CIW
Thermal Resistance
Junction to Case
Junction to Ambient
Maximum Lead Temp. for Soldering Purposes,
1/16' from case for seconds
·C
*JEDEC registered values.
t JTX. JTXV available.
DaBlgne"s Dati for "Worst Case" Conditions - The Designer's Data Sheet permits the design of most circurts entirely from the information presented.
limit curves - representing device characteristics - are given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
3-37
r'
2N6770, JTX, JTXV
ELECTRICAL CHARACTERISTICS (TC = 25·C unless otherwise noted)
I
I
Characteristic
I'
Min
Typ
Max
Unit
VBR(OSS)
500
-
-
Vdc
lOSS
-
-
I"
4*
-
100"
nAdc
-
100*
nAdc
2*
1.5
2.7
2.2
4"
3.5
-
0.4"
O.SS*
VOS(on)
-
-
6"
Vdc
9FS
S"
-
24*
mhos
-
3000"
pF
Symbol
OFF CHARACTERISncs
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 4 mAl
Zero Gate Voltage Drain Current
(VOSS = Rated VOSS, VGS = 0)
TJ = 125"C
Gate-Body leakage Current, Forward
(VGSF = 20 V)
IGSSF
Gate-Body leakage Current, Reverse
(VGSR = 20 V)
IGSSR
mAdc
ON CHARACTERISTICS
Gate Threshold Voltage
(10 = 1 mA, VOS = VGS)
TJ = 1OO·C
VGS(th)
Static Drain-Source On-Resistance(l)
(VGS = 10 Vdc, 10 = 7.75 Adc)
TC = 125·C
rOS(on)
Drain-Source On-Voltage (VGS
(10 = 12 Adc)
=
10 V)(l)
Forward Transconductance(l)
(VOS = 15 V, 10 = 7.75 A)
Vdc
Ohms
CAPACITANCE
Input Capacitance
(VOS
Output Capacitance
= 25 V, VGS = 0
f = 1 MHz)
Reverse Transfer Capacitance
Ciss
1000"
Coss
200'
Crss
50'
-
600'
200"
SWITCHING CHARACTERISncs
Turn-On Delay Time
(VOS = 210 V, 10 = 7.75 Adc
Zo = 4.70)
See Figs. 1 and 2
Rise Time
Turn-Off Delay Time
Fall Time
td(on)
-
-
35'
tr
-
-
50'
td(oft)
-
-
150'
tf
-
-
70*
ns
SOURCE-DRAIN DIODE CHARACTERISTICS
ISM
-
-
ton
-
trr
Internal Drain Inductance (Measured from the contact screw on
the header closer to the source pin and the center of the die)
Internal Source Inductance (Measured from the source pin
0.25" from the package to the source bond pad)
Diode Forward Voltage (VGS = 0)
(IS = 12)A
VSO
Continuous Source Current, Body Diode
IS
Pulsed Source Current, Body Diode
Forward Turn-On Time
Reverse Recovery Time
I
I
(IS = Rated IS, VGS
= 0)
O.S·
1.6*
Vdc
12"
Adc
25
A
200
-
ns
-
700
-
ld
-
5
-
ls
-
12.5
-
INTERNAL PACKAGE INDUCTANCE (TO-204)
*JEDEC registered values.
(1) Pulse Test: Pulse Width" 300 )J.s, Duty Cycle" 2.0%.
"
MOTOROLA TMOS POWER MOSFET DATA
3-38
nH
2N6770, JTX, JTXV
RESISTIVE SWITCHING
!dIan'
PULSE GENERATOR
OUTPUT, Vaut
INVERTEO
r---~---l
I
4.Hl:
:
J1. PRF = 1kHz:
Zo
4.7!l
I
tp=lp.s I
I lOV
L..:
_______ .JI
Figure 2. Switching Waveforms
Figure 1. Switching Test Circuit
TYPICAL CHARACTERISTICS
20
VGS
18
16 f--- TJ
14
'25'C
ia
~
c
~
~
10
8
6
9 4
10 V
8V
ie
~ 12
iii' 1.2
::;;
~ ~I-""
20 V
~
~
::J:
Q
7V
tl
z
-
~
o
~ 0.4
z
~ 0.2
5V -
8
II
I
I 25'C V
TJ = -55"<:
ie 14
10
I
-
~ 6
9 4
o
o
TJ - 125'C
25'C
55'C
-
!--
V
:;,..;;.;;
l...- F"
I
16
az
10V
~
2345678
Vos. ORAIN·TO·SOURCE VOLTAGE (VOLTS)
18
g§
.!
::::>
20
~12
I-
=
~ O.S
~
z
~ 0.6
6V
/
ffi
~
::;;
v
!5
1.20
1.10
~
./100·C
~
'"~
/
"'" "-.. '-......
~
9
,
~
Vos = VGS
10 = 1 rnA
...........
""- ...........
0.90
F
!:i1 0.80
J
1$
r-.....
'":s
10
:>
-SO
~
..........
~0.70
5
7
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
24
Figure 4. On-Resistance Variation
II /
1/1
1/
VOS = 10V
20
8
12
16
10. ORAIN CURRENT (AMPS)
10
Figure 3. On-Region Characteristics
il"i
I
VGS
i'"
~
o~
o
1
-25
o
25
SO
75
100
TJ, JUNCTION TEMPERATURE ('C)
125
Figure 6. Gate Threshold Voltage Variation
Figure 5. Transfer Characteristics
MOTOROLA TMOS POWER MOSFET DATA
3-39
ISO
2N6770, JTX, JTXV
! ~~
D
~
O.5q
O.~
i
~
_~
0.20
I?"'
~ li~fi~01·!.10~~~~~~~~~~~if~~~~~~~~~:l~
.....
Iif! 0.10
~
0.05
L..--
Pt(Pk1n.n. R/JJC(tl rttl R/JJC
R/JJC 0.83'CiW MAX
DCURVES APPLY FOR POWER
-
I-~±±:::j~'~~~EL..-::jl--j=±tl±±±tt=±=±=tfJ±ffi~
SI~GL,E ~U,L~~t--t-+--++-+++tl+--++--+-+++-++f+
i
~
*
!:: 0.D1
I I I I II
0.10
0.01
~~~I
~~~
I-t2-1
READ TIME
DUTY CYCLE,
D = tlh2 TJ(pkl
- TCATtl
= P(pkl R/JJcltl
I ( I I I II Iii
I I
i I I II
100
lk
10
t, TIMElm.1
Figure 7. Thermal Response
OPERATING AREA INFORMATION
30
100
25
r-.:
r-- -
1--
I......
10",
0.1 m.
1m.
5
10ms
§
51-- f-TJ
~
I'" '5fC
I
0
100
I- -
0.1
200
300
400
500
VOS, DRAIN·TO·SOURCE VOLTAGE (VOLTSI
600
......
I-- VGS = 20 V, SINGLE PULSE
I-- TC = 25'C
1
Figura 8. Maximum Rated SWitching
Safe Operating Area
E- -
'DS(onl LIMIT
- - PACKAGE LIMIT
THERMAL LIMIT
de
5
10
30 50 100
300 500 1000
VOS, DRAIN·T()'SOURCE VOLTAGE (VOLTSI
Figure 9. Maximum Rated Forward Biased
Safe Operating Araa
'\
S\MTCHlI\IG SAFE OPERATING AREA
cable for both turn-on and turn-off of the devices for
switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
The switching safe operating area (SOAI of Figure 8,
is the boundary that the load line may traverse without
incurring damagetothe MOSFET:Thefundamentallimits
are the peak current, 10M and the breakdown voltage,
V(BIUDSS. The switching SOA shown in Figure 8 is appli-
TJ(maxl - Te
R9JG
MOTOROLA TMOS POWER MOSFET DATA
3-40
2500
2000
FORWARD BIASED SAFE OPERAnNG AREA
"- i'--.
The de data of Figure 9 is based on a case temperature
(TC) of 25°C and a maximum junction temperature
(TJmax) of 150°C_ The actual junction temperature
depends on the power dissipated in the device and its
case temperature_ For various pulse widths, duty cycles,
and case temperatures, the peak allowable drain current
(lDM) m<1Y be calculated with the aid of the following
equation:
Ciss
1\
\
\
500
\
""-
= I (250C) [TJ(max) - TC]
Cess
I-
D
Crss
8
16
24
32
PD'R9JC'r(t)
Where
ID(25°C) = de drain current at TC = 25°C from Figure
9_
TJmax = Rated maximum junction temperature
= Device case temperature
TC
= Rated power dissipation at TC = 25°C
PD
= Rated steady state thermal resistance
RruC
r(t)
= Normalized thermal response from Figure 7
40
VOS, ORAIN-TO-SOURCE VOLTAGE (VOLTSI
Figure 10_ Capacitance Variation
CASE 1-0&
TO·204M
STYLE 3:
PIN 1. GATE
2. SOURCE
CASE DRAIN
011
A
B
IIIU.IME1BIS
MIN
MAX
:JI
21.oa
c
6.35
D
E
F
G
H
J
K
0
Q
R
U
V
INCHES
MIN
1.~
,.
8.25
1.09
1.n
3O.1SBSC
C
5.46BSC
16.89BSC
11.18 12.19
4.19
184
26,67
4.
5.33
3.84
4.19
NOTES:
1. DIMENSIONING AND TOLERANClNG PER ANSI
Y14.5M.1982,
2. CONTROLLING DIMENSION: INCH.
3. ALL RULES AND NOll:S ASSOCIATED WITH
REFERENCED ro-2_ OUlUNE SHAU API'LY.
0.190
0,151
MOTOROLA TMOS POWER MOSFET DATA
3·41
MOTOROLA
- TECHNICAL
SEMICONDUCTOR
------------DATA
2N6182
Advance Information
Power Field Effect Transistor
N-Channel Enhancement-Mode
Silicon Gate TMOS
· .. designed for high voltage, high speed power switching
applications such as switching regulators, converters, solenoids, relay drivers, inverters, choppers, audio amplifiers, and high energy pulse circuits.
•
•
•
•
•
,r
N-CHANNEL
TMOS POWER FETs
rOSlon) = 0.6 OHM
100 VOLTS
TMDS
Silicon Gate for Fast Switching Speeds
Low Drive Current Required
Easy Paralleling
No Second Breakdown
Excellent Temperature Stability
G
MAXIMUM RATINGS
Symbol
Value
Unit
Drain-Source Voltage
Rating
VOSS
100
Vdc
Drain-Gate Voltage (RGS = 1 mfl)
VOGR
100
Vdc
Gate-Source Voltage
VGS
±20
Vdc
Drain Current
Continuous
Pulsed
10
10M
3.5
14
Po
15
0.12
Watts
TJ. Tstg
-55to 150
°c
°CIW
Adc
Total Power Dissipation @ TC = 25°C
Derate above 25°C
Operating and Storage Temperature Range
wroc
THERMAL CHARACTERISTICS
Thermal Resistance - Junction to Case
- Junction to Ambient
Maximum Lead Temperature
1.6 mm from Case for 10 seconds
ELECTRICAL CHARACTERISTICS (TC
I
=
ROJC
8.33
ROJA
175
TL
300
°C
25°C unless otherwise noted)
Characteristic
Symbol
Min
V(BR)OSS
100
Max
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 0.25 mAl
Zero Gate Voltage Drain Current
(VOS = 100 V, VGS = 0 V)
(VOS = 80 V, VGS = 0 V, TJ = 125°C)
lOSS
-
Vdc
/LAde
-
250
1000
(continued)
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MOTOROLA TMOS POWER MOSFET DATA
3-42
2N6782
ELECTRICAL CHARACTERISTICS -
I
continued
(TC = 25°C unless otherwise noted)
I
Characteristic
Symbol
I
Min
Max
Unit
OFF CHARACTERISTICS
Gate-Body Leakage Current, Forward
(VGS = 20 Vdc, VOS = 0)
IGSSF
-
100
nAdc
Gate-Body Leakage Current, Reverse
(VGS = -20 Vdc, VOS = 0)
IGSSR
-
-100
nAdc
4
Vdc
, ON CHARACTERISTICS·
Gate Threshold Voltage
(VOS = VGS, 10 = 0.5 mAl
Static Orain-Source On-Resistance
(VGS = 10 Vdc, 10 = 2.25 Adc)
Orain-Source On-Voltage (VGS
(10 = 3.5 Adc)
2
VGS(th)
=
TA
TA
Ohm
rOS(on)
= 25°C
= 125°C
10 V)
-
VOS(on)
Forward Transconductance
(VOS = 5 V, 10 = 2.25 Adc)
0.6
1.08
2.1
Vdc
gFS
1
3
mhos
pF
DYNAMIC CHARACTERISTICS
Input Capacitance
= 25 V, VGS = 0,
f = 1 MHz)
(VOS
Output Capacitance
Reverse Transfer Capacitance
Ciss
60
200
Coss
40
100
Crss
10
25
SWITCHING CHARACTERISTICS·
Turn-On Oelay Time
Rise Time
(VOO = 34 V, 10 = 2.25 Rated ID
Rgen = 50 ohms)
Turn-Off Oelay Time
Fall Time
td(on)
-
15
tr
-
25
td(off)
-
25
tf
-
20
VSO
0.75
1.5
Vdc
ton
-
Negligible
ns
trr
-
200
ns
'ns
SOURCE DRAIN DIODE CHARACTERISTICS·
Oiode Forward Voltage
(IS = Rated 10(on)
VGS = 0)
Forward Turn-On Time
Reverse Recovery Time
*Pulse Test Pulse Width ,s;;; 300 '""s, Duty Cycle ,s;;; 2%.
ounlNE DIMENSIONS
~
-re- -
:I
L
~K
--~
......
.......J
DIM
--ii-a
a~Nr= N
X"VJ
1
M
A
B
C
CASE 79-03
STYLES,
PIN 1. SOURCE
2. GATE
3. DftAiN
12\
-+-3
ICASEI
0/
0
E
F
_5
MIN
0.355
0.315
0.165
MAX
0.366
0.335
0.180
0017
K
M
~33
'83
0.71
0.86
0.7.
1.02
12.70
45°NOM
0.021
0017 0.035
0.016 0.019
0.190 0.210
0.028 0.034
0.029 0.040
0.500
'S"NOM
N
2.54 TYP
O.100TYP
Q
90" NOM
90" NOM
G
H
J
MOTOROLA TMOS POWER MOSFET DATA
3-43
MlLUMETEIIS
MIN
MAX
9.30
9.02
800
8.51
.57
"9
043
053
0.43
0.89
0.41
0.48
-
MOTOROLA
-
SEMICONDUCTOR
-------------TECHNICAL
DATA
2N6784
Advance Information
Power Field Effect Transistor
N-Channel Enhancement-Mode
Silicon Gate TMOS
N-CHANNEL
TMOS POWER FET
rOSlon) = 1.5 OHMS
200 VOLTS
• .. designed for high voltage. high speed power switching
applications such as switching regulators. converters. solenoids. relay drivers. inverters. choppers. audio amplifiers. and high energy pulse circuits.
•
•
•
•
•
Silicon Gate for Fast Switching Speeds
Low Drive Current Required
Easy Paralleling
No Second Breakdown
Excellent Temperature Stability
G
MAXIMUM RATINGS
Symbol
Value
Unit
Drain-Source Voltage
Rating
VOSS
200
Vdc
Drain-Gate Voltage (RGS = 1 mO)
VOGR
200
Vdc
VGS
±20
Vdc
10
10M
2.25
9
Po
15
0.12
Watts
TJ. Tstg
-55to 150
°c
°CIW
Gate-Source Voltage
\
Adc
Drain Current
Continuous
Pulsed
Total Power Dissipation @TC = 25°C
Derate above 25°C
Operating and Storage Temperature Range
wrc
THERMAL CHARACTERISTICS
Thermal Resistance - Junction to Case
- Junction to Ambient
Maximum Lead Temperature
1.61l)m from Case for 10 seconds
ELECTRICAL CHARACTERISTICS (TC
I
=
25°C unless otherwise noted)
Characteristic
,I
Rf/JC
8.33
ROJA
175
TL
300
°C
Symbol
Min
Max
Unit
V(BR)OSS
200
-
Vdc
-
250
1000
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = O. 10 = 0.25 mAl
Zero Gate Voltage Drain Current
NOS = Rated VOSS. VGS = 0)
NOS = 0.8 Rated VOSS. VGS = O. TJ
lOSS
=
-
125~C)
"Adc
(continued)
This document contains information on a new product. Specifications and Information herein are subject to change without notice.
MOTOROLA TMOS POWER MOSFET DATA
3-44
2N6784
ELECTRICAL CHARACTERISTICS - continued
I
ITC = 25°C unless otherwise noted)
I
Characteristic
Symbol
I
Min •
Max
Unit
OFF CHARACTERISTICS
100
nAdc
IG~SR
-
-100
nAdc
VGS(th)
2
4
Vdc
rOSlon)
VOS(on)
-
3.37
Vdc
gFS
0.9
2.7
mhos
Ciss
60
200
pF
Coss
20
60
Crss
5
25
Gate-Body Leakage Current, Forward
(VGS = 20 Vdc, VOS = 0)
IGSSF
Gate-Body Leakage Current, Reverse
(VGS = -20 Vdc, VOS = 0)
ON CHARACTERlsncs*
Gate Threshold Voltage
(VOS = VGS, 10 = 0.5 mAl
Static Drain-Source On-Resistance
(VGS = 10 Vdc, 10 = 1.5 Adc)
Drain-Source On-Voltage (VGS
liD = 2.25 Adc)
=
TA
TA
=
=
25°C
125°C
10 V)
Forward Transconductance
(VOS = 5 V, 10 = 1.5 Adc)
Ohms
1.5
2.81
DYNAMIC CHARACTERISTICS
Input Capacitance
(VOS
Output Capacitance
= 25 V, VGS = O.
f = 1 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERIS11CS*
Tum-On Delay Time
tf
-
VSO
0.7
1.5
Vdc
ton
-
Negligible
ns
trr
290 (Typ)
td(on)
Rise TIme
(VOO = 75 V, 10 = 1.5 A.
Rgen = 50 ohms)
Turn-Off Delay Time
FaUTIme
tr
td(off)
15
ns
20
30
20
SOURCE DRAIN DIODE CHARACTERISTICS'
Diode Forward Voltage
liS
Forward Tum-On Time
=
Rated 10(on)
VGS = 0)
Reverse Recovery TIme
-
ns
."
'Pulse Test Pulse Width", 300 1'8. Duty Cvcle '" 2%.
OUTLINE DIMENSIONS
~
-----
~
-
:-IF
--11-0
, ~!~.:
~
M
C
D
E
F
G
G
N
tK
DIM
A
B
CASE 79-03
Q~
P
--~
.......
..... J
c
STYlf6:
PIN 1. SOURCE
2. GATE
3. OftAIN
ICASEI
N
3
~~J
H
J
K
M
N
Q
MOTOROLA TMOS POWER MOSFET DATA
3-45
MLUMETERS
MIN
MAX
9.02
9.30
8.51
800
4.19
.57
0.43
0.53
0.43
0.89
OAl
0.48
5.33
UI3
0.71
0.86
0.74
1.02
12.70
45"NOM
.54TYP
9O"NOM
INCHES
MIN
MAX
0.355 0.366
0.315 0.335
0165 0.180
0.017 0.021
0.017 0.035
0.Q16 0.019
0.190 0.210
0.028 0.034
0.029 0.040
0.500
45"NOM
0.100 TIP
9O"NOM
• MOTOROLA
SEMICONDUCTOR _ _ _ _ _ _ _ _ _ _ _ __
TECHNICAL DATA
2N6788
Advance Information
Power Field Effect Transistor
N-Channel Enhancement-Mode
Silicon Gate TMOS
· .. designed for high voltage, high speed power switching
applications such as switching regulators, converters, solenoids, relay drivers, inverters, choppers, audio amplifiers, and high energy pulse circuits.
•
•
•
•
•
,r
N-CHANNEL
TMOS POWER FET
roS(on) = 0.3 OHM
100 VOLTS
TMDS
Silicon Gate for Fast Switching Speeds
Low Drive Current Required
Easy Paralleling
No Second Breakdown
Excellent Temperature Stability
G
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VOSS
100
Vdc
VOGR
100
Vdc
VGS
±20
Vdc
10
10M
6
24
Po
20
0.16
Watts
WI"C
TJ, Tstg
-55 to 150
·C
Junction to Case
R8JC
6.25
·C/w
Junction to Ambient
R8JA
175
TL
300
Orain-Source Voltage
Orain-Gate Voltage (RGS
~
1 mCl)
Gate-Source Voltage
Drain Current
Adc
Continuous
Pulsed
Total Power Oissipation @ TC
Oerate above 25·C
~
25·C
Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
Thermal Resistance -
Maximum Lead Temperature
1.6 mm from Case for 10 seconds
ELECTRICAL CHARACTERISTICS (Tc
I
·C
~ 25·C unless otherwise noted)
Characteristic
Symbol
Min
Max
Unit
V(BR)OSS
100
-
Vdc
OFF CHARACTERISTICS
Orain-Source Breakdown Voltage
(VGS ~ 0, 10 ~ 0.25 mAl
Zero Gate Voltage Orain Current
(VOS ~ Rated VOSS, VGS ~ 0)
(VOS ~ 80 V, VGS ~ 0, TJ ~ 125·C)
lOSS
!lAdc
-
250
1000
(continued)
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MOTOROLA TMOS POWER MOSFET DATA
3-46
2N6788
continued
ELECTRICAL CHARACTERISTICS -
I
(TC
=
25°C unless otherwise noted)
I
Characteristic
Svmbol
I
,
OFF CHARACTERISTICS
Min
Max
Unit
Gate-Body Leakage Current, Forward
(VGS = 20 Vdc, VOS = 0)
IGSSF
-
100
nAdc
Gate-Body Leakage Current, Reverse
(VGS = -20 Vdc, VOS = 0)
IGSSR
-
-100
nAdc
4
Vdc
ON CHARACTERISTICS·
Gate Threshold Voltage
(VOS = VGS, 10 = 1 mAl
Static Orain-Source On-Resistance
(VGS = 10 Vdc, 10 = 3.5 Adc)
2
VGS(th)
rOS(on)
VOS(on)
-
gFS
1.5
TA = 25°C
TA = 125°C
Orain-Source On-Voltage (VGS = 10 V)
(10 = 6 Adc)
Forward Transconductance
(VOS = 5 V, 10 = 3.5 Adc)
Ohm
0.3
0.54
1.8
Vdc
4.5
mhos
pF
DYNAMIC CHARACTERISTICS
Input Capacitance
(VOS = 25 V, VGS = 0,
f = 1 MHz)
Output Capacitance
Reverse Transfer Capacitance
Ciss
200
600
Coss
100
400
Crss
20
100
td(on)
-
40
tr
-
70
td(off)
-
40
tf
-
70
SWITCHING CHARACTERISTICS·
Turn-On Oelay Time
Rise Time
(VOO = 35 V, 10 = 3.5 A
Rgen = 50 ohms)
Turn-Off Oelay Time
Fall Time
ns
SOURCE DRAIN DIODE CHARACTERISTICS·
Oiode Forward Voltage
(IS = Rated 10(on)
VGS = 0)
Forward Turn-On Time
VSO
0.8
1.8
Vdc
ton
-
Negligible
ns
trr
-
230
ns
Reverse Recovery Time
'Pulse Test Pulse Width" 300 I'S, Duty Cycle" 2%.
OUTLINE DIMENSIONS
~
-- =-t.
....... )
.....
--li--D
DIM
0/"1
G
N
smE6:
~N 1. SOURCE
2. GATE
3. DRAIN
ICASEI
N
, ~!~, ,
~
M
A
B
C
CASE 79-03
TO-Z05AF TYPE
'(~J
D
E
F
G
H
J
K
M
N
Q
MOTOROLA TMOS POWER MOSFET DATA
3-47
MlLUMETEfIS
MIN
MAX
9.02
9.30
8.00
8.51
4.19
.57
0.43
0.53
0.43
0.89
0.41
0.48
4.83
5.33
0.71
0.86
0.74
1.02
12.70
45'NOM
2.54 TYI'
90" NOM
INCHES
MAX
0.366
0.335
0180
0.021
0.035
0.019
loIN
0355
0.315
0166
0.017
0017
0.016
0.''11)
~
0.034
O.O"d
0.029 0.040
0.500
45"NOM
O.l00TYl'
90" NOM
-
MOTOROLA
• SEMICONDUCTOR _ _ _ _ _ _- - - - - - TECHNICAL DATA
2N6823
Designer's Data Sheet
Power Field Effect Transistor
N-Channel Enhancement-Mode
Silicon Gate TMOS
These TMOS Power FETs are designed for high voltage,
high speed power switching applications such as switching regulators, converters, solenoid and relay drivers.
,r
TMOS POWER FETs
3 AMPERES
roSlon) = 2.8 OHMS
600 VOLTS
TMOS
• Silicon Gate for Fast Switching Speeds - Swjtching Times
Specified at 100"C
• Designer's Data - lOSS, VDS(on), VGS(th) and SOA Specified
at Elevated Temperature
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive Loads
G
MAXIMUM RAnNGS
Symbol
2N6823
Unit
Drain-Source Voltage
VOSS
600
Vdc
Drain-Gate Voltage (RGS = 1 MOl
VOGR
600
Vdc
VGS
±20
Vdc
10
3
10M
2.5
15
Po
100
Rating
Gate-Source Voltage
Drain Current
Continuous @ TC = 25'C
TC = 1OO'C
Pulsed
Adc
Total Power Dissipation @TC = 25'C
Derate above 25'C
0.8
Operating Junction Temperature Range
Storage Temperature Range
TJ
-65 to 150
Tstg
-65 to 175
R8JC
R8JA
1.25
TL
275
Watts
W/'C
CASE 1-116
T()"204AA
'c
'c
THERMAL CHARACTERISTICS
'c/w
Thermal Resistance
Junction to Case
Junction to Ambient
Maximum Lead Temperature for Soldering
Purposes, 1/8" from case for 5 seconds
30
'c
-w..
DeoIg...... DellI for
C-" Condltlono -The Designer's Data Sheet permits the deaisn of most circuits entirely from the information presented.
SOA Lim~ curves - repreoenting boundorleo on device characterletlco - are given to flcil_ ''worst caoe" doslgn.
MOTOROLA TMOS POWER MOSFET DATA
3-48
2N6823
ELECTRICAL CHARACTERISTICS (TC = 25"C unless otherwise noted)
I
Characteristic
Symbol
Min
Max
Unit
V(BR)OSS
600
-
Vdc
OFF CHARACTERlS11CS
Drain-Source Breakdown Voltage
(VGS = O. 10 = 0.25 mAl
.
Zero Gate Voltage Drain Current
(VOS = Rated VOSS. VGS = 0)
(VOS = 0.8 Rated VOSS. VGS = O. TJ
lOSS
= 125"C)
Gate-Body Leakage Current. Forward
(VGSF = 20 Vdc. VOS = 0)
IGSSF
Gate-Body Leakage Current, Reverse
(VGSR = 20 Vdc, VOS = 0)
IGSSR
mAdc
-
0.25
2.5
500
nAdc
500
nAdc
ON CHARACTERISTICSGate Threshold Voltage
(VOS = VGS, 10 = 1 mAl
TJ = l00'C
VGS(th)
Static Drain-Source On-Resistance
(VGS = 10 Vdc, 10 = 3 Adc)
rOS(on)
Drain-Source On-Voltage (VGS
(10 = 3 Adc)
(10 = 2.5 Adc, TJ = 10O"C)
= 10 V)
4.5
4
-
2.8
-
8.4
15
9FS
1.5
7.5
mhos
pF
VOS(on)
Forward Transconductance
(VOS = 15V,I0 = 2A)
Vdc
2
1.5
Ohms
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
(VOS = 25 V, VGS = 0,
f = 1 MHz)
See Figure 11
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS- (TJ
=
Ciss
400
1000
Coss
40
200
Crss
10
100
l00'C)
Fall Time
If
-
TOlal Gate Charge
Og
16 (Typ)
20
Ogs
8 (Typ)
-
Ogd
8 (Typ)
-
VSD
0.7
Turn-On Delay TIme
Id(on)
(VOO = 125 V, 10 = 2A
R~en = 50 ohms)
See igures 9, 13 and 14
Rise Time
Turn-Off Delay Time
Gate-Source Charge
"Gate-Drain Charge
(VOS = 0.8 Rated VOSS,
10 = Rated 10, VGS = 10 V)
See Figure 12
tr
Id(off)
50
ns
100
180
80
nC
SOURCE DRAIN DIODE CHARACTERIS11CSForward On-Voltage
(IS = 3 A.
VGS = 0)
Forward Turn-On TIme
Reverse Recovery TIme
trr
INTERNAL PACKAGE INDUCTANCE
I
1.5
I
Vdc
Limited by stray inductance
ton
-
I
500
I
ns
(
Internal Drain Inductance
(Measured from the contact screw on the header closer
to the source pin and the center of the die)
Ld
5 (Typ)
-
Internal Source Inductance
(Measured from the source pin, 0.25" from the package
to the source bond pad)
Ls
12.5 (Typ)
-
'Pulse Test: Pulse Width'" 300 /loS, Duty Cycle'" 2%.
MOTOROLA TMOS POWER MOSFET DATA
3-49
nH
2N6823
TYPICAL ELECTRICAL CHARACTERISTICS
10
V
TJ = 25"C
VGS-8V~
V
10~ ~
.....
ie
~
!Z
w
~
a'"'"
V
-' V
v. . . . . ......
...-:::
A ~V
z
~
I--
--
o/'
~
i!!
1.1
~
1
~
tlI
7V
g
i
6V
...........
~
'-....
~
0.9
I'-....
~ 0.8
8
12
16
Vos. DRAIN·TO-SOURCE VOLTAGE (VOLTS)
'I-....
§0.7
~ -50
>
20
// f/
,
J~
U
o
o
1//.
L, ~
-
.-"""
I--'"
./'
25'C
10
5
./
50
100
150
TJ. JUNCTION TEMPERATURE I'C)
2.2
TJ = 10O"C
J
............-
-
1
--
/
25"C
./
1
-55"C
VGS =11OV-
~
4
0.06
./
./
I
il
V
VGS = 10V_
10 = 1.5A
-
V
i?
0
3
200
Figure 4. Breakdown Voltage Variation
With Temperature
./
----
2
/'
/p'
-SS'C
Figure 3. Transfer Characteristics
3
150
./
• VGS. GATE·TO-SOURCE VOLTAGE (VOLTS)
4
125
/'
,
/
l00"C
50
75
100
25
TJ. JUNCTION TEMPERATURE I'C)
VGS = 0
-10 = 0.25mA
-
1///
TJ
.........
-25
Figure 2. Gate-Threshold Voltage Variation
With Temperature
Figure 1. On-Region Characteristics
VOS = lOV
f"'.....
~
4V
10
VOS = VGS
10= lmA
..........
9
5V
~ f-""
o
-
I--
~
9
S 12
0.2
-50
5
10. ORAIN CURRENT (AMPS)
50
100
TJ. JUNCTION TEMPERATURE I'C)
Figure 6. On-Resistance Variation
With Temperature
Figure 5. On-Resistance versus Drain Current
MOTOROLA TMOS POWER MOSFET DATA
3-50
150
200
2N6823
SAFE OPERATING AREA INFORMATION
16
100
10,..
1 mo
de
TJ '" 15O"C
1 ETC 25·C
VGS 20 V, SINGLE PULSE
F
O. 1
'-- - - - - PACKAGE UMIT
THERMAL UMIT
2 3 5 7 10
20 30 50 70 100 200 300 500 700 lK
1
VOS, DRAIN·TO-SOURCE VOLTAGE (VOLTS)
o
o
Figure 7. Maximum Rated Forward Biased
Safe Operating Area .
The power averaged over a complete switching cycle
must be less than:
The FBSOA curves define the maximum dra.in-tosource voltage and drain current that a device can safely
handle when it is forward biased, or when it is on, or
being turned on. Because these curves include the limitations of simultaneous high voltage and high current,
up to the rating of the device, they are especially useful
to designers of linear systems. The curves are based on
a case temperature of 25·C and a maximum junction temperature of 150·C. Limitations for repetitive pulses at various case temperatures can be determined by using the
thermal response curves. Motorola Application Note,
AN569, "Transient Thermal Resistance-General Data and
Its Use" provides detailed instructions.
TJ{max) R8JC
5K
3K
2K
6~
fa!ox:
It lil
0.3
0.2
!::!
0.1
i~
!Z
0.05
i! ~
0.03
~
Z!!!
I!O 0.02
w
::E
;:::
0.01
--
0.01
0.02
10
20 30
50
100
200 300 500
"
F""'"
-l-
...-1-
rJUl
~~I
p(pk)
II III
ISlrrlllr
0.1
R/iJClt) = rft) R/iJC
R/IJC = 1.25"CIW MAX
DCURVES APPLY FOR POWEll
PUlSE TRAIN SHOWN
READ TIME ATtl
TJ(pk) - Te = P/pk) R/IJC(I)
t2DUTY CYCLE, 0 = tln2
...
0.05
!dlon)
V-
Figure 9. Resistive Switching Time
Variation versus Gate ResIstIlllCB
~.01
~
V-
RG, GATE RESISTANCE (OHMS)
.---:
0.1
0.0
0.02
..... r-
m
t,
300 -TJ 25·C
200 -10 = 2A
100 -VOO - 25V
~VGS 10V
50
30
20
10
1
2 3
0.5
0.2
-.....-
!dloll
lK
.s 500
The switching safe operating area (SOA) of Figure 8 is
the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits
are the peak current, 10M and the breakdown voltage,
V(BR)DSS. The switching SOA shown in Figure 8 is applicable for both turn-on and turn-off of the devices for
switching times less than one microsecond.
0
TC
10K
SWITCHING SAFE OPERATING AREA
~ 0.5
800
Figure 8. Maximum Rated Switching
Safe Operating Area
FORWARD BIASED SAFE OPERATING AREA
w
200
~
~O
VOS, DRAIN·TO·SOURCE VOLTAGE IVOLTS)
0.2
0.5
2
10
II II
20
t TIME Imo)
Figure 10. Thermal Response
MOTOROLA TMOS POWER MOSFET DATA
3-51
50
100
200
500
1000
lK
2N6823
2000
1600
v/
10
I
I
TJ = 25'C VGS = 0 _
f = 1 MHz
~
r-r--
g
Y'/ ~
I - - TJ = 25'C
10 = 3A
~
h X
;:j
I'-
,\
\\
\ f'...
400
o
o
IX
~
\
V/ V
l:::>i1
CiSS
0
~
f'?
~
'".n
Coss
'"
/
>
Crss" '
10
20
30
Vos. DRAIN-Ta-SOURCE VOLTAGE IValTS)
40
50
/
VOO
VOO
VOO - 100
/
o
o
8
16
12
ag• TOTAL GATE CHARGE InC)
Figure 12. Gate Charge versus
Gate-to-Source Voltage
Figure 11. Capacitance Variation
RESISTIVE SWITCHING
Von
RJ
~VOu!
PULSE GENERATOR
OUTPUT. VOU!
INVERTED
OUT
r-------,
I Rgen ;---'IM,.--+-+)
I
I
INPUT. V,n
IL _____ _
Figure 13. SWitching Test Circuit
Figure 14. Switching Waveforms
OUTLINE DIMENSIONS
STYlf3:
PIN 1. GATE
2. SOURCE
CASE DRAIN
011
A
B
C
0
NOleS:
1. DlMeN~ONING AND TOl.ERANClNG "'R ANSI
Yl4.5M,1982.
2. CONTROWNG DIMENSION; INCH.
1 ALL RULES AND NOlES ASSOCIAlED WITH
RfFERENCED TO-204M OUltlNE SHALL APPLY.
E
F
G
H
J
K
Q
R
IIWMEI&RS
MIN
MAX
39.37
21.08
.35
&25
1.09
1.40
tn
3O.158SC
I
V
CASE 1-0&
TO-204AA
MOTOROLA TMOS POWER MOSFET DATA
SC
5.4I!BSC
16.89BSC
tNCItElI
lIN
MAX
1.560
0.830
a2!O 0.325
0
aD43
0.070
1.187
O.430BSC
G.215jiC
a
t1.18
12.19
O.
.
1!0
~
~
oF
o
'f'
I~
'-..
ill"
0.9
~
0.8
[g
0.7
-50
'"'"
i!:
4V
'"~
I12
8
16
20
>
-25
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTSI
10
TJ = -55"<:
I I 1/
A
If -£25JC
ifl/ I
2
f----- -
50
75
100
125
'-150
VGS = 0
10 = 0.25 mA
--
1
100"CI
......- f--
J
~
'(II
/JI
25
"r-..
Figure 2. Gate-Threshold Voltage Variation
With Temperature
~I
VI"
o
'--
TJ. JUNCTION TEMPERATURE (OCI
Figure ,. On-Region Characteristics
o
o
~
!:i
~
I'
.9
VOS = VGS
10 = 1 rnA
~
$?
~V
z
~
1.1
III
5V
bV
~
1.2
:;:
......-
Vos - 20V
i::Y.
10
4
VGS. GATE·TO-SOURCE VOLTAGE (VOLTSI
-50
Figure 3. Transfer Characteristics
-- --
~
150
200
2.5
z
--
100
Figure 4. Breakdown Voltage Variation
With Temperature
-~J = Joooc
f----- f--- 25"<:
50
TJ. JUNCTION TEMPERATURE (OC)
f---
-
~
ill
~
00
~~
-
I
I
I- VGS = 10V
-
r- 1O=3A
1.5
~~
~i1
00
'7~
z
r-- f- J5"<:
«
'"0
c
VGS = 10V
'*
E'
10
4
10. ORAIN CURRENT (AMPSI
./
/"
0.5
V
/'
./'
o
-so
V
50
/'
100
TJ. JUNCTION TEMPERATURE lOCI
Figure 6. On-Resistance Variation
With Temperature
Figure 5. On-Resistance versus Drain Current
MOTOROLA TMOS POWER MOSFET DATA
3-55
150
200
2N6826
SAFE OPERATING AREA INFORMATION
40
35
10 I'S
30
l00~
.........
0
~
:E
l~iE
I-
z
VGS
= iov
SINGLE PULSE
o.1
TC
I mC~GEI LIMIT
10
TJ '" 15O"C
15
10
~
--
= 25'C
1
I.!?
"de
'OS(oni LIMIT
'THERMAL LIMIT
25
~
::> 20
u
10';s"'~
1
30
~
-j
100
200
400
600
VOS, ORAIN·TO-SOURCE VOLTAGE (VOLTSI
600
VOS, ORAIN-TO·SOURCE VOLTAGE (VOLTSI
Figllre 7, Maximum Rated Forward Biased
Safe Operating Area
Figure 8. Maximum Rated Switching
Safe Operating Area
The power averaged over a complete switching cycle'
must be less than:
FORWARD BIASED SAFE OPERATING AREA
The FBSOA curves define the maximum drain-tosource voltage and drain current that a device can safely
handle when it is forward biased, or when it is on, or
being turned on. Because these curves include the limitations of simultaneous high voltage and high current,
up to the rating of the device, they are especially useful
to designers of linear systems. The curveS are based on
a case temperature of 25·C and'a maximum junction temperature of 150·C. limitations for repetitive pulses at various case temperatures can be determined by using the
thermal response curves. Motorola Application Note,
AN569, "Transient Thermal Resistance-General Data and
Its Use" provides detailed instructions.
TJ(maxi - TC
RruC
2800 I---- TJ 25'C
-;;; 2000
10 = 3A
~ 1000 ~ VOO 25 V
:E
VGS 10 V
F
'":i:z
~
==
!d(onl
200
v
100
10
30
50
100
300 500
1k
RG GATE RESISTANCE (OHMSI
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
-
f-:
0.2
_::;;0-~
1---0.02
~
....n0.02
....
-
0.1
R6Jc!11 rill R6JC
R6JC 0.83'CIW MAX
DCURVES APPLY.FOR POWER
PULSE TRAIN SHOWN
READ TIME ATtl
TJ(pk) - TC = P(pkl R6JC(II
~~~
DUlY CYCLE, D = 11~2
SlrGret~m
0.05
P(pkl
tSlIl
1==0.06
0.01
If
I,
0.5
I-- 0.1
0.01
!dloffl
'=
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 8 is
the boundary that the load line may traverse without
incurring damagetothe MOSFET. Thefundamentallimits
are the peak current, 10M and the breakdown voltage,
V(BR)OSS. The switching SOA shown in Figure 8 is applicable for both turn-on and turn-off of the devices for
switching times less than one microsecond.
D
800
0.2
0.5
10
~
20
TIME (m.I
Figure 10. Thermal Response
MOTOROLA TMOS POWER MOSFET DATA
50
100
200
500
1000
2N6826
5000
4000
1000
16
-,
TJ = 25°C
~
VOS
in
!::;
14
0
2:~
VGS = 0
~
g
-
10
~
i=>:1
0
-
0
12
TJ =1 250C
10 = 6A
U>
!;(
Ciss
~
Coss
C,ss
"-
'"
>
-10 -5
0
5
10
15
20
25
VGS·-I-Vos
GATE·TO-SOURCE OR ORAlN·TO·SOURCE VOLTAGE (VOLTS)
' \ VOS = 200 V
"300V
'\ 480 V
I
.;;
-
~
'\.
~ '\
b
w
~
~
1
00
10
20
30
40
50
70
60
80
ag. TOTAl GATE CHARGE (nC)
Figure 11. Capacitance Variation
Figure 12. Gate Charge versus
Gate-to-Source Voltage
RESISTIVE SWITCHING
VOO
Yin
RJ
rl----
I
..,.s
8.0 V
Vi
6.0 V
'/
'f//
5.0 V
80
~
z 60
~
7.0 V
rl
CAPACITANCE versus DRAIN-TO-SOURCE VOLTAGE
VGS - OV
9.0V
V-
4.0
100
VGS = 10V
1/
1.6
z
~ 0.8
~
t.e- ;...- i""""
r-- r--
2.0
B
9.0 V
IoiI!II"""
-50
~ 1.2
r--- '1Ov'
.... ~
o
~
!z
~
~ po-
!;? 0.4
~
L.
13
£=
' 20
,
.-
I'\.
"'-..1 m,
~j~
I>'
:::>
l;
u
z
« 107
----- rDSlon) LIMIT
PACKAGE LIMIT
THERMAL LIMIT
-
I>'
'"
.9
3
,tVGS
= 20 Vdc, SINGLE PULSE
2 _ TC = 25'C
1.5
0.1
ndc
'"
LL
1
10
VDS, DRAIN·TO-SOURCE VOLTAGE IVOLTS)
"
0.1
100
1
10
VDS, DRAIN-TO·SOURCE VOLTAGE (VOLTS)
100
Figure 2. Maximum Rated Forward Biased
Safe Operating Area
Figure 1. Maximum Rated Forward Biased
Safe Operating Area
FORWARD BIASED SAFE OPERATING AREA
The de data of Figures 1 and 2 is based on a case
temperature (TC) of 25'C and a maximum junction temperature (TJmax) of 150'. The actual junction temperature depends on the power dissipated in the device and
its case temperature. For various pulse widths, duty
cycles, and case temperatures, the peak allowable drain
current (10M) may be calculated with the aid of the following equation:
= I (25'C)[TJ(max) - TC]
10M
o
Po • R8JC • r(t)
1.0
0.7
0.5
C/. ffi 0.3
::e ~ 0.2
~ ~ 0.1
~ ~ 0.07
w-
D
0.5
D
0.2
D
~~
1-1>'
§
~ ~ 0.05
0,05
--
:---
,..
0.1
-1-0
0.01
I--
SINGLE PULSE
0.03
0.02
0.01
0.01
,
~
HLrL
~~
--
1-",
:g ~
Where
IO(25'C) = the de drain current at TC = 25'C from
Figure 1 or 2
TJ(max) = rated maximum junction temperature
TC
= device case temP-llrature
Po
= rated power dissipation at TC = 25°C
R8JC
= rated steady state thermal resistance
r(t)
= normalized thermal response from Figure 3
DUTY CYCLE, 0 t,lI,
1
0.02 0.03
0.05
0.1
0.2
0.3
0.5
1.0
Uilil
2.0 3.0 5.0
nlME(msl
10
F= F
Rrucll) r(l) RruC
Rruc 1.67"CWMax
~
ocurve. apply for power
~ I::t
Pul.e lrain shown
Read lime at I,
TJ(pk) - Te = P(pk) Rl/JC(I)
~
r--
ttt-I
20
30
I ill'
50
100
i
200 300
Figure 3. Thermal Response
RESISTIVE SWITCHING
Figure 4. Switching Test Circuit
Figure 5, Switching Waveforms
MOTOROLA TMOS POWER MOSFET DATA
3-71
SOD
1000
MOTOROLA
_ TECHNICAL
SEMICONDUCTOR
-------------DATA
BUZ71
BUZ71A
Power Field Effect Transistor
N-Channel Enhancement-Mode
Silicon Gate
These TMOS III Power FETs are designed for low
voltage, high speed, low loss power switching applications such as switching regulators, converters,
solenoid and relay drivers.
TMOS POWER FETs
12 AMPERES
'DSlon) = 0.10 and
0.12 OHMS
50 VOLTS
•
•
•
•
Silicon Gate for Fast Switching Speeds
Low rDS(on} - 0.10 0 max and 0.12 0 max
Rugged - SOA is Power Dissipation Limited
Source-to-Drain Diode Characterized for Use With
Inductive Loads
• Low Drive Requirement - VGS(thl = 4 V max
G
CASE 221A-04
, TO-220AB
MAXIMUM RATINGS
Symbol
Rating
Drain-Source Voltage
BUZ71
1
BUZ71A
Unit
VDSS
50
Vdc
VDGR
50
Vdc
Gate-Source Voltage
VGS
±20
Vdc
Drain Current - Continuous
-Pulsed
ID
IDM
12
Adc
48
PD
40
0.32
Watts
TJ, Tstg
-55 to 150
°C
R8JC
R8JA
3.12
62.5
°CIW
TL
275
°C
Drain-Gate Voltage (RGS
=
20 kCl)
Total Power Dissipation @ TC
Derate above 25°C
=
250(;
Operating and Storage Temperature Range
WI"C
THERMAL CHARACTERISTICS
Thermal Resistance - Junction to Case
- Junction toAmbient
Maximum Lead Temp. for Soldering Purposes,
118" from case for 5 seconds
ELECTRICAL CHARACTERISTICS (TC = 250(; unless otherwise noted)
I
I Symbol
Characteristic
Min
Typ
Max
50
-
-
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage NGS
Zero Gate Voltage Drain Current
(VDS = 50 Volts, VGS = 0)
(VDS = 50 Volts, VGS = 0, TJ
= 0, ID = 1 mAl
V(BR)DSS
IDSS
= 125°C)
Gate-Body Leakage Current, Forward (VGSF
Gate-Body leakage Current, Reverse (VGSR
= 20 Vdc, Vos = 0)
= 20 Vdc, VDS = 0)
IGSSF
IGSSR
-
-
Vdc
pAdc
-
-
250
1000
10
100
10
100
nAdc
nAdc
(continued)
MOTOROLA TMOS POWER MOSFET DATA
3-72
BUZ71, A
ELECTRICAL CHARACTERISTICS - continued (TC = 25°C unless otherwise noted)
I
Characteristic
I Symbol I
Min
Typ
Max
Unit
VGS(th)
2.1
3.1
4
Vdc
-
0.08
0.10
0.10
0.12
ON CHARACTERISTICS·
Gate Threshold Voltage
(VOS = VGS, 10 = 10 rnA)
Static Orain-Source On-Resistance
(VGS = 10 Vdc, 10 = 6 Adc)
Orain-Source On-Voltage (VGS
(10 = 6 Adc)
(10 = 6 Adc)
=
rOSlon)
BUZ71
BUZ71A
10 V)
VOS(on)
BUZ71
BUZ71A
Forward Transconductance
NOS = 25 V, 10 = 6 A)
Ohm
-
0.48
0.60
Vdc
-
mhos
pF
9FS
3
5.5
Ciss
-
-
650
Coss
450
Crss
-
-
Og
-
14
td(on)
-
tr
-
td(off)
-
-
tf
-
-
110
VSO
-
-
2.2
ton
-
120
-
ns
trr
-
110
-
ns
DYNAMIC CHARACTERISTICS
Input Capacitance
(VOS
Output Capacitance
= 25 V, VGS = 0,
f = 1 MHz)
Reverse Transfer Capacitance
Total Gate Charge
(VOS
= 40 V, VGS =
10 = 12A)
10 Vdc,
280
-
nC
30
ns
See Figures 6 and 12
SWITCHING CHARACTERISTICS·
Turn-On Oelay Time
(VOO = 30 V, 10 = 3 A,
Rgen = 50 ohms)
See Figures 11 and 12
Rise Time
Turn-Off Oelay Time
Fall Time
85
90
SOURCE ORAIN OIODE CHARACTERISTICS·
Forward On-Voltage
(IS = 24 A,
VGS = 0)
Forward Turn-On 'Time
Reverse Recovery Time
Vdc
INTERNAL PACKAGE INDUCTANCE
Internal Orain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25" from package to center of die)
lei
Internal Source Inductance
(Measured from the source lead 0.25" from package to source bond pad)
Ls
*Pulse Test: Pulse Width os:;: 300 IJ.S, Duty Cycle
os:;;
-
3.5
4.5
-
7.5
TO-220AB
DIM
A
B
LL
fJ]
nH
2%.
CASE 221A-04
Q
-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
YI4.5M, 1982.
2. CONTROlliNG DIMENSION: INCH.
3. DIM Z DEFINES AZONE WHERE All BODY AND.
LEAD IRREGUlARITIES ARE AllOWED.
C
D
F
G
H
J
K
L
N
Q
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MOTOROLA TMOS POWER MOSFET DATA
3-73
R
S
T
U
V
Z
MlLlIMmRS
MIN
MAX
15.75
10.28
9.66
4.62
~07
0.64
0.88
3.61
3.73
2.42
2.66
3.93
2.60
0.36
0.55
14.27
12.70
1.15
1.39
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
6.47
5.97
1.27
0.00
1.15
2.04
1~48
INCHES
MIN
MAX
0.570 0.620
0.380 0.405
0.190
0.160
0.025 0.035
0.142 0.147
0.095 0.105
0.110 0.155
0.014 0.022
0.500 0.562
0.045 0.055
0.190 0.210
0.100 0.120
0.060 0.110
0.045
0.055
0.255
0.235
0.000
0.050
0.045
0.080
BUZ71, A
TYPICAL CHARACTERISTICS
20
8
6
4
2
0
8
6
ru
,.1--"
2
rt:-. R 2010VV
If. C- 8V
7V
'1
TJ = 25'C
""" ""'"
1
6V
1//
II
1
VDS = VGS
10 = lmA
""'" ["-..., f"-,
5V
~
V
I'-
4
VGS - 4'V
2
0
2345678
VOS. DRAIN-TO-SOURCE VOLTAGE (VOLTS)
~O.70
10
......
-50
>
14
TJ = -55'C_ -,
25'C
loo'C-
800
~
TJ
\\
\
\
If
6
\ "'-
VDS = 10V
......
lL
2
L.:2~
0
4
6
8
10
VGS. GATE-TO-SOURCE VOLTAGE (VOLTS)
12
0
14
~ 0.14
fl
I
I
0
I
f--- f8
I
~
-55'C
4
~O.04
e
t--t-VGS =
-
Crss
50
~
VD~ = 2Jv r-- ~
~
30V
W
~V-
/
ID = RATED ID -
/
I
2 I
~0.06
IS
Cos.
r--,...
6
25'C
~0.08
r--...
20
~
~
VOS. ORAIN·TO-SOURCE VOLTAGE (VOLTS)
~
00.1 0
r-...
Ciss
Figure 4. Capacitance Variation
ITJ = 1100'CI
2
.........
= 25'C
ro
Figure 3. Transfer Characteristics
:z
~
150
VGS' = 0
f = 1 MHz
"- ..............
J
4
125
1000
Ji V
'I
j
25
50
75
100
TJ. JUNCTION TEMPERATURE ('C)
Figure 2. Gate-Threshold Voltage
Variation With Temperature
~~
8
o
-25
Figure ,_ On-Region CIl,aracteristics
16
......
10 V
I
I
r--
011
4
6
8
10
12
8
ID. DRAIN CURRENT (AMPS)
12
QQ. TOTAL GATE CHARGE (nC)
Figure 6. Gate Charge versus
Gate-To-Source Voltage
Figure 5. On-,Resistance versus Drain Current
MOTOROLA TMOS POWER MOSFET DATA
3-74
16
20
BUZ71, A
RATED SAFE OPERATING AREA INFORMATION
100
-
'"---
iC
~
z>-
-
10
~
=>
-
~
- ...... l -
~-
-
FORWARD BIASED SAFE OPERATING AREA
The de data of Figure 7 is based on a case temperature
(TC) of 25°C and a maximum junction temperature
(TJ(max)) of 150°. The actual junction temperature depends on the power dissipated in the device and its case
temperature. For various pulse widths, duty cycles, and
case temperatures, the peak allowable drain current
(10M) may be calculated with the aid of the following
equation:
......... 10 p.S
0.1 ms
.......
lms
10ms
r- - - - PACKAGE LIMIT
r- ----- TDSlon) LIMIT
THERMAl LIMIT
1== E
u
~
z
~
C
Eo
~ ~ VGS
) - - I - TC
0."
~c .......
......
10M
20 V, SINGLE PULSE
25"<:
3
5 7 10
20 30
VDS, DRAIN·TO·SOURCE VOLTAGE IVOLTS)
50
50
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 8 is
the boundary that the load line may traverse without
incurring damagetothe MOSFET. The fundamental limits
are the peak current, 10M and the breakdown voltage,
V(BR)OSS' The switching SOA shown in Figure 8 is applicable for both turn-on and turn-off of the devices for
switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
0
0
r---- _
TJ""5O"C
"1
j
50
10
20
30
40
VOS, DRAIN·TO·SOURCE VOLTAGE IVOLTS)
I (250C)[TJ(max) - TC]
o
PO. R9JC • r(t)
where
IO(25°C) = the dc drain current at TC = 25°C from
Figure 7
TJ(max) = rated maximum junction temperature
TC
= device case temperature
Po
= rated power dissipation at TC = 2SoC
R9JC
= rated steady state thermal resistance
= normalized thermal response from Figure 9
r(t)
70 100
Figure 7. Maximum Rated Forward Biased
Safe Operating Area
0
=
TJ(max) - TC
Figure 8. Maximum Rated Switching
Safe Operating Area
1
0.70 D
~_ 0.50
~
w C
~ ~ 0.30
!z:;i
~~
0.20
0.5
:=
0.2
c-
0.1
G~
0.07 E: 0.02
0.05
'E'
0.03
0.02
z
~~
R8JCII) rll) R9JC
R9JC(I) 3.12"CIW MAX
DCURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT 11
TJlpk) - TC = P(pk) ROJCII)
l - i-'"
~~
0.05
f=
~ 0.10 f=
~
R9JC
pBlil
0.01
-
0.01
0.01
-~f----
0.02\ 0.03
0.05
I
12I I DUTY CYCLE, D = tl~2 LI
r- SI~~LE rU~f
0.1
0.2 0.3
0.5
1
2
3
10
20
~ TlMElms)
Figure 9. Thermal Response
MOTOROLA TMOS POWER MOSFET DATA
3-75
30
50
100
200 300
500
1000
BUZ71, A
+18V
p
Vin
n~
l5V
~
2N3904
100 k
47k
Vin ~ 15 Vpk; PULSE WIDTH", 100 p.S, DUTY CYCLE", 10%
figure 10. Gate Charge Test Circuit
RESISTIVE SWITCHING
tdlonl
OUTPUT, Vout
INVERTED
PULSE WIDTH
Figure". Switching Test CIrcuit
Figure 12. Switching Waveforms
MOTOROLA TMOS POWER MOSFET DATA
3-76
-
MOTOROLA
SEMICONDUCTOR
_ _ _ _ _ _ _ _ _ _ _ __
TECHNICAL DATA
BUZ73
Power Field Effect Transistor
N-Channel Enhancement-Mode
Silicon Gate
This TMOS Power FET is designed for high speed, low
loss power switching applications such as switching regulators, converters, motor controls, solenoid and relay
drivers.
TMOS POWER FET
7 AMPERES
'DSlon) = 0.4 OHMS
200 VOLTS
•
•
•
•
Silicon Gate for Fast Switching Speeds
Low rDSlon) - 0.4 n max
Rugged - SOA is Power Dissipation Limited
Source-to-Drain Diode Characterized for Use With
Inductive Loads
• Low Drive Requirement - VGSlth) = 4 V max
G
TO-2ZOAB
MAXIMUM RATINGS
Rating
Drain-Source Voltage
Drain-Gate Voltage (RGS
=
20 k!l)
Gate-Source Voltage
Drain Current -
Continuous ITC
Pulsed
Total Power Dissipation @ TC
Derate above 25'C
= 25'C)
= 25'C
Symbol
Value
VOSS
200
Vdc
VOGR
200
Vdc
VGS
±20
Vdc
10
10M
7
28
Adc
40
Watts
Po
Operating and Storage Temperature Range
Unit
0.32
wrc
TJ, Tstg
-65 to +150
'C
R8JC
R8JA
3.12
62.5
'CIW
275
'c
THERMAL CHARACTERISTICS
Thermal Resistance -
Junction to Case
Junction to Ambient
Maximum Lead Temperature for Soldering Purposes,
1/8" from case for 5 seconds
TL
,
ELECTRICAL CHARACTERISTICS (TC = 25'C unless otherwise noted)
I
Symbol
Min
Typ
Max
Unit
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 1 mAl
V(BR)OSS
200
-
-
Vdc
Zero Gate Voltage Drain Current
(VOS = 200 Volts, VGS = 0)
(VOS = 200 Volts. VGS = 0, TJ
lOSS
-
-
250
Characteristic
OFF CHARACTERISTICS
=
125'C)
Gate-Body Leakage Current, Forward (VGSF
= 20 Vdc, VOS
= 0)
IGSSF
Gate-Body Leakage Current, Reverse (VGSR = 20 Vdc, VOS = 0)
IGSSR
/'Adc
-
1000
10
100
10
100
nAdc
nAdc
(ClIntlnued)
MOTOROLA TMOS POWER MOSFET DATA
3-77
IUZ73
ELECTRICAL CHARACTERISTICS -
I
continued (TC
=
25·C unless otherwise noted)
I
Cheracteristlc
Typ
Symbol
Min
Max
VGS(th)
2.1
3
4
Vdc
-
0.4
Ohm
VOS(on)
-
3.2
-
Vdc
9FS
2.2
3.5
-
mhos
Crss
-
-
Og
-
15
td(on)
-
-
td(off)
-
-
90
If
-
-
55
-
-
1.7
Vdc
120
-
ns
Unit
ON CHARACTERISTICS"
Gate Threshold Voltage (VOS
=
VGS, 10
Static Drain-Source On-Resistance (VGS
Drain-Source On-Voltage (VGS
(10 = 7 Adc)
=
Forward Transconductance (VOS
= 10 mAl
= 10 Vdc, 10 = 3.5 Adc)
rOS(on)
10 V)
=
25 V, 10
=
3.5 A)
DYNAMIC CHARACTERISTICS
Input Capacitance
(VOS
Output Capacitance
Ciss
= 25 V, VGS = 0,
f = 1 MHz)
Coss
Reverse Transfer Capacitance
Total Gate Charge
(VOS ;" 160 V, VGS
=
10 Vdc, 10
= 7 Al
600
pF
160
80
-
nC
20
ns
SWITCHING CHARACTERISTICS"
Turn-On Delay Time
Rise Tiln.
Turn-Off Delay Time
(VOO
= 30V,10 = 3A,VGS =
Rgen = 50 ohms)
Ir
10V,
Fall Time
SOURCE
60
DRAIN DIODE CHARACTERISTICS"
Forward On-Voltage
VSD
(IS = 14A,
VGS = 0)
Forward Turn-On Time
ton
Reverse Recovery Time
Irr
325
ns
·Pul•• T••t: Pul•• Width" 300 p,s, Duty Cycl. " 2%.
CASE 221A-04
TO-220AB
NOTES:
1. DIMENSIONING AND TOlERANCING PER ANSI
YI4.5M, 1982.
2. CONTROLUNG DIMENSION: INCH.
3. DIM Z DEFINES AZONE WHERE ALL BODY AND
LEAD IRREGULARITIES ARE ALLOWED.
MlLLlM£TERS
DIM
STYLE 5:
~N 1. GATE
2. DRAIN
3. SOURCE
~DRAIN
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
MOTOROLA TMOS POWER MOSFET DATA
3-78
MIN
14.48
9.66
4.07
0.64
3.61
2.42
2.80
0.36
12.70
1.15
4.83
2.54
2.04
1.15
5.97
0.00
1.15
MAX
15.75
10.28
4.82
0.88
3.73
2.66
3.93
0.56
14.27
1.39
5.33
3.04
2.79
1.39
647
1.27
-
2.04
INCHES
MIN
MAX
0.570 0.620
0.380 0.405
0.160 0.190
0.025 0.035
0.142 0.147
0.095 0.105
0.110 0.155
0.014 0.022
0.500 0.562
0.045 0.055
0.190 0.210
0.100 0.120
0.080 0.110
0.045 0.055
0.235 0.256
0.000 0.050
0.045
0.080
-
BUZ73
TYPICAL ELECTRICAL CHARACTERISTICS
16
VGS
= 20V_
10V~
~
12
::;;
....$z:
TJ
l!!
::>
'"
u
l,A:: ~8V
W'V
~V
V~V
V-
7V
= 25°C:/~ ~
l,Z
), V
'"
.9
"
o
o
5t-
"'"
f--
I;.
H 1/
Ii;
100"2: -
~
~
~
~~
@~ O.S
~
6~
~
0.4
~
-50
:z
10
~
~
0
250C
;
-55°C
-
-
:>
= 10V
= 100°C
150
>;-
6
VGS. ORAIN-TO-SOURCE VOLTAGE (VOLTS)
TJ
125
1.6
", 300 IA-s. Duty Cycle ~ 2%.
(1) Add 0.1 V for IRF240 and IRF241.
MOTOROLA TMOS POWER MOSFET DATA
3-92
-
MOTOROLA
SEMICONDUCTOR
_ _ _ _ _ _ _ _ _ _ _ __
TECHNICAL DATA
IRF250
IRF251
IRF252
IRF253
Power Field Effect Transistor
N-Channel Enhancement-Mode
Silicon Gate TMOS
These TMOS Power FETs are designed for low
voltage, high speed power switching applications
such as switching regulators, converters, solenoid
and relay drivers.
TMOS POWER FETs
25 and 30 AMPERES
rOSlon) = 0.085 OHM
150 and 200 VOLTS
rOSlon) = 0.12 OHMS
150 and 200 VOLTS
• Silicon Gate for Fast Switching Speeds
• Low rOS(on) to Minimize On-Losses. Specified at
Elevated Temperature
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With
Inductive Loads
G
CASE 197A-02
TO-2D4AE
MAXIMUM RATINGS
Symbol
Rating
OUTLINE DIMENSIONS
IRF
Unit
Drain-Source Voltage
VOSS
200
150
200
150
Vdc
Ln=:W.
Drain-Gate Voltage
(RGS = 20 kfi)
VDGR
200
150
200
150
Vdc
l.
250
251
252
253
--I~Dtl'l
=rm=
K
1-t-!tiJ O:rJiOO12l®ITlo®!u®1
Gate-Source Voltage
±20
VGS
Drain Current
Continuous, TC = 25°C
TC = 1000C
Peak, TC = 25°C
Total Power Dissipation @ TC
Derate above 25°C
Vdc
Adc
10
= 25°C
Operating and Storage Temperature Range
30
19
120
25
16
100
Po
150
1.2
Watts
WI"C
TJ, Tstg
-55 to 150
°c
R8JC
R8JA
0.83
30
°CIW
TL
300
°C
THERMAL CHARACTERISTICS
Thermal Resistance -
T
Junction to Case
Junction to Ambient
Maximum Lead Temp. for Soldering Purposes,
1/8" from Case for 5 Seconds
rWfl
1"'!40 0251O.010t®!T!U®1
STYLE 3:
PINt GATE
2. SOURCE
CASE DRAIN
NOTES,
1. DIMENSIONING AND TOlERANCING PER ANSI
Y14.5M,1982.
2. CONTROlliNG DIMENSION: INCtl.
See the MTM40N20 Designers Data Sheet for a complete set of design curves for the product on this data sheet.
11M
A
B
C
D
E
F
G
H
J
K
Q
R
U
MOTOROLA TMOS POo"yER MOSFET DATA
3-93
,.,.
INCtES
39.37
19.31
21.08
825
1.60
lAS
1.71
1
3O.15BSC
10.92BSC
5A6BSC
16.89 C
11.18
12.19
3.84
25-15 26.67
4.19
3.84
.'"
.(
TMOS
s
MAXIMUM RATINGS
IRF
Svmbol
450
451
452
Unit
Drain-Source Voltage
VOSS
500
450
500
Vdc
Drain-Gate Voltage
(RGS = 1.0 MO)
VOGR
500
450
500
Vdc
Rating
PIN 1. BASE
Gate-Source Voltage
VGS
Drain Current
Continuous
Pulsed
10
10M
Total Power Dissipation
@TC = 25"C
Derate above 25"C
Operating and Storage
Temperature Range
±20
Adc
13
52
150
1.2
Watts
WI'C
-55to 150
"C
Maximum Lead Temp. for Soldering
Purposes, 1/S" from Case for 5 Seconds
°C!w\
R8JC
R8JA
0.83
30
TL
300
CASE COUECTOR
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONTROlUNG DIMENSION' INCH
3. ALL RULES ANO NOTES ASSOCIATED WITH
REFERENCEO TQ.204AA OUTlINE SHAll APPLY.
12
48
Po
TJ, Tstg
2. EMmER
Vdc
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Junction to Ambient
STYLE l'
DIM
A
B
C
D
E
F
G
H
J
K
"C
R
U
V
MlU.lMET!RS
MIN
39.37
21.08
8.25
~35
1.09
0.97
1.77
30.15 SSC
10.92 esc
1."
5.46BSC
16.89BSC
12.19
11.18
<19
26.67
4.83
."
4.19
,...
,
INCHES
MAX
1.550
0.830
0.250
0.325
0.038
0.043
0,055
0.070
1.187BSC
O.
0210
0.720
0110
0.055
0.255
0.1150
0001
IRF520-523
ELECTRICAL CHARACTERISTICS (TC = 25"C unless otherwise noted)
I
Symbol
Characteristic
Min
Max
60
100
-
Unit
OFF CHARACTERISTICS
Orain-Source Breakdown Voltage
(VGS = 0, 10 = 0.25 mAl
V(BR)OSS
IRF521, IRF523
IRF520, IRF522
Zero Gate Voltage Orain Current
(VOS = Rated VOSS, VGS = 0)
(VOS = 0.8 Rated VOSS, VGS = 0, TJ
lOSS
mAdc
Gate-Body leakage Current, Forward
(VGSF = 20 Vdc, VOS = 0)
IGSSF
-
Gate-Body leakage Current. Reverse
(VGSR = 20 Vdc, VOS = 0)
IGSSR
-
=
125"C)
Vdc
0.2
1
100
nAdc
100
nAdc
4
Vdc
ON CHARACTERISTICS'
Gate Threshold Voltage
(VOS = VGS, 10 = 0.25 mAl
VGS(th)
Static Drain-Source On-Resistance
(VGS
=
10 Vdc, 10
rOS(on)
= 4 Adc)
On-State Orain Current (VGS
(VOS '" 2.4 Vdc)
(VOS '" 2.8 Vdc)
=
IRF520, IRF521
IRF522, IRF523
10 V)
2
Ohm
-
0.3
0.4
8
7
-
10(on)
IRF520, IRF521
IRF522, IRF523
Forward Transconductance
(VOS '" 2.4 V, 10 = 4 A)
(VOS '" 2.8 V, 10 = 4 A)
mhos
9FS
IRF520, IRF521
IRF522, IRF523
Adc
-
1.5
1.5
-
-
600
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS
Output Capacitance
= 25 V, VGS = 0,
f = 1 MHz)
Ciss
Coss
Crss
Reverse Transfer Capacitance
-
pF
400
100
SWITCHING CHARACTERISTICS'
, Turn-On Oelay Time
Rise Time
Turn-Off Oelay Time
Fall Time
Total Gate Charge
Gate-Source Charge
-
70
td(off)
-
100
tf
-
70
td(on)
(VOD = 0.5 VOSS, 10 = 4 Apk,
Rgen = 50 Ohms)
(VOS = 0.8 Rated VOSS,
VGS = 10 Vdc, 10 = Rated 10)
Gate-Drain Charge
tr
ns
40
Qg
13 (Typ)
15
Qgs
7 (Typ)
-
Qgd
6 (Typ)
-
nC
SOURCE DRAIN DIODE CHARACTERISTICS'
Forward On-Voltage
(IS
Forward Turn-On Time
= Rated 10,
VGS = 0)
Reverse Recovery Time
VSD
ton
trr
1.4 (Typ)
I
2.3(1)
I
Vdc
limited by stray inductance
280 (Typ)
I
-
I
ns
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25" from package to center of die)
ld
Internal Source Inductance
(Measured from the source lead 0.25" from package to source bond pad)
ls
3.5 (Typ)
4.5 (Typ)
'Pulse Test: Pulse Width", 300 '"S, Duty Cycle", 2.0%.
(11 Add 0.1 V for IRF520 and IRF521.
MOTOROLA TMOS POWER MOSFET DATA
3-108
7.5 (Typ)
-
nH
MOTOROLA
TECHNICAL DATA
N-CHANNEL ENHANCEMENT-MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
These TMOS Power FETs are designed for low voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
•
IRFS30
IRFS31
IRFS32
IRFS33
• SEMICONDUCTOR _ _ _ _ __
Part Numbe.
VDS
'DSlon)
10
IRF530
100V
0.18n
14A
IRF531
SOV
0.18n
14A
IRF532
100V
0.25 n
12 A
IRF533
SO V
0.25n
12A
• Silicon Gate for Fast Switching Speeds
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
G
GI.r---"'I
TMOS
S
MAXIMUM RATINGS
IRF
Symbol
530
531
532
533
Unit
Drain-Source Voltage
VOSS
100
60
100
SO
Vdc
Drain-Gate Voltage
(RGS = 1.0 MOl
VDGR
100
SO
100
SO
Vdc
Rating
Gate-Source Voltage
VGS
Continuous Drain Current
TC
Continuous Drain Current
TC
Drain Current -
= 25'C
= 100'C
Pulsed
Total Power
Dissipation @ TC = 25'C
Derate above 25'C
Operating and Storage
Temperature Range
10
14
14
12
12
Adc
10
9.0
9.0
8.0
8.0
Adc
10M
5S
5S
48
48
Adc
Watts
Po
TJ,Tstg
75
O.S
wrc
-55 to 150
'c
Maximum Lead Temp. for Soldering
Purposes, 1/S" from case for 5 seconds
• sou"'"
L,
I
Rgen
I
Output, Vout
Inverted
I
I
I
15.1}
15.1}
I
I
IL
I
_______
.JI
MOTOROLA TMOS POWER MOSFET DATA
3-110
Unit
nH
MOTOROLA
-
SEMICONDUCTOR
TECHNICAL DATA
IRF540
IRF541
IRF542
Power Field Effect Transistor
N-Channel Enhancement-Mode
Silicon Gate TMOS
,r
These TMOS Power FETs are designed for low
voltage, high speed power switching applications
such as switching regulators, converters, solenoid
and relay drivers.
• Silicon Gate for Fast Switching Speeds
• Low rDS(on) to Minimize On-Losses. Specified at
Elevated Temperature
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With
Inductive Loads
TMOS
TMOS POWER FETs
24 and 27 AMPERES
rDS(on) = 0.085 OHM
60 and 100 VOLTS
rDS(on) = 0.11 OHMS
100 VOLTS
G
CASE 221A-04
(TO-220ABI
MAXIMUM RATINGS
II
1
OUTLINE DIMENSIONS
IRF
Rating
Svmbol
ii
II
540
541
Drain-Source Voltage
VOSS
100
60
100
Vdc
Drain-Gate Voltage
(RGS = 20 k!ll
VDGR
100
60
100
Vdc
Gate-Source Voltage
VGS
Drain Current
Continuous, TC = 25"C
TC = 100"C
Peak, TC = 25"C
Total Power Dissipation @ TC
Derate above 25"C
542
±20
Vdc
Adc
10
=
25"C
24
15
96
125
1
Walts
TJ. Totg
-55to 150
"C
R8JC
R8JA
1
62.5
"CIW
TL
300
"C
Po
Operating and Storage Temperature Range
27
17
lOS
wrc
THERMAL CHARACTERISTICS
Thermal Resistance - Junction to Case
- Junction to Ambient
Maximum Lead Temp. for Soldering Purposes,
liS" from Case for 5 Seconds
STYlE 5:
PIN 1. GATE
2 ORAlN
3.SOUfICI:
4DRAJN
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,19B2.
2. CONTflOlLING DIMENSION: INCH.
3 DIM Z DEFINES fA ZONE WliERE ALL BODY AND
LEAD lRREGUlARmES ARE Al.l.OWED.
DOl
A
See the MTP25N10 Designer's Data Sheet for a complete set of design curves for the product on this data sheet.
•
C
D
f
G
H
J
•
l
N
Q
••
MOTOROLA TMOS POWER MOSFET DATA
"LUftTERS
MW
MAX
,.. ,."
9.66
4,0,
10.28
0,0'
0,"'
.."
3,73
2,
3,93
0.142
."
0.100
3.61
2A2
2.,
0.36
12.70
1.15
14.27
1.J9
254
2,04
'04
279
0045
19O
0.100
,080
1.15
139
5"
0.045
0.235
1.27
0.000
0045
."
T
5.91
U
0,00
V
"'
Z
3-111
1 'I
Unit
0,'
204
,00;
0.110
.014
0,500
IRF540-542
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
I
Characteristic
Symbol
Min
Max
100
60
-
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 0.25 rnA)
V(BR)OSS
IRF540, IRF542
IRF541
Zero Gate Voltage Drain Current
(VOS = Rated VOSS, VGS = 0)
(VOS = 0.8 Rated VOSS, VGS = 0, TJ
lOSS
Vdc
mAdc
-
0.2
1
Gate-Body Leakage Current, Forward
(VGSF = 20 Vdc, VOS = 0)
IGSSF
-
100
nAdc
Gate-Body Leakage Current, Reverse
(VGSR = 20 Vdc, VOS = 0)
IGSSR
-
100
nAdc
4
Vdc
=
125°C)
ON CHARACTERISTICS·
Gate Threshold Voltage
(VOS = VGS, 10 = 0.25 mAl
Static Drain-Source On-Resistance
(VGS = 10 Vdc, 10 = 15 Adc)
On-State Drain Current (VGS
(VOS '" 2.3 Vdc)
(VOS '" 2.6 Vdc)
=
2
VGS(th)
Ohm
rOS(on)
-
IRF540, IRF541
IRF542
10 V)
0.085
0.11
Adc
10(on)
IRF540, IRF541
IRF542
Forward Transconductance
(VOS '" 2.3 V, 10 = 15 A)
(VOS '" 2.6 V, 10 = 15 A)
-
27
24
9FS
mhos
-
6.0
6.0
IRF540, IRF541
IRF542
-
DYNAMIC CHARACTERISTICS
Input Capacitance
(VOS
Output Capacitance
= 25 V, VGS = 0,
f = 1 MHz)
Reverse Transfer Capacitance
Ciss
-
1600
Coss
800
Crss
-
td(on)
-
30
tr
60
tf
+
Qg
40 (Typ)
60
Qgs
17 (Typ)
-
Qgd
23 (Typ)
-
pF
300
SWITCHING CHARACTERISTICS·
Turn-On Delay Time
Rise Time
(VOO = 30 V, 10 = 15 Apk,
Rgen = 4.7 Ohms)
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
(VOS = 0.8 Rated VOSS,
VGS = 10 Vdc, 10 = Rated 10)
Gate-Drain Charge
td(off)
ns
80
30
nC
SOURCE DRAIN DIODE CHARACTERISTICS·
Forward On-Voltage
(IS = Rated 10,
Forward Turn-On Time
VGS
= 0)
Reverse Recovery Time
1.5 (Typ)
VSD
ton
I
2.3(1)
I
Vdc
Limited by stray inductance
trr
450 (Typ)
I
-
I
ns
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25", from package to center of die)
Ld
Internal Source Inductance
(Measured from the source lead 0.25" from package to source bond pad)
Ls
'Pulse Test: Pulse Width" 300 p.o, Duty Cycle" 2.0%.
(1) Add 0.1 V for IRF540 and IRF541.
MOTOROLA TMOS POWER MOSFET DATA
3-112
nH
3.5 (Typ)
4.5 (Typ)
-
7.5 (Typ)
-
-
-
MOTOROLA
SEMICONDUCTOR _ _ _ _ __
IRF610
IRF612
TECHNICAL DATA
N-CHANNEL ENHANCEMENT-MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
These TMOS Power FETs are designed for low voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
Part Number
VOS
rOSlon)
10
IRF610
200 V
1.5.n
2.5A
IRF612
200 V
2.4.n
2.0A
• Silicon Gate for Fast Switching Speeds
• Rugged -
SOA is Power Dissipation limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
lr
G
o
S
TMOS
S
MAXIMUM RATINGS
IRF
Symbol
610
612
Unit
Drain-Source Voltage
VOSS
200
200
Vdc
Drain-Gate Voltage
IRGS = 1.0 Mn)
VDGR
200
200
Vdc
Rating
Gate-Source Voltage
±20
VGS
Vdc
Continuous Drain Current T C = 25·C
10
2.5
2.0
Adc
Continuous Drain Current T C = 100·C
10
1.5
1.25
Adc
10M
10
8.0
Drain Current -
Pulsed
Total Power Dissipation @ TC = 25·C
Derate above 25·C
Operating and Storage Temperature Range
Adc
Po
20
0.16
Watts
TJ, Tstg
-55to 150
·C
wrc
Maximum Lead Temp. for Soldering
Purposes, 118" from case for 5 seconds
NOTES:
1. DIMENSIONING AND TOI£RANCIMG PER ANSI
YI4.5M,I982.
2. CONTROWNG DIMENSION. INCH.
3. DIM Z OEAKES A ZONE wtlEIIt: ALL BODY AND
lEAD IRREGUI..ARlTlE5 ARE AllOWED.
... ...
A
8
C
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Junction to Ambient
ST'Il.ES·
PIN t. GATE
2.DRAJN
3.SOURa
'-'
/'
§
90.4
10.4
s.ov
7.0V
6.0 V
'I
'/
-
r--
~
~-
~
).0--
-
6.0 V
5.0V
4.0 V
1.0
2.0
3.0
VDS, DRAIN·TO·SOURCE VOLTAGE !VOLTS)
4.0
CAPACITANCE versus DRAIN-TO-SOURCE VOLTAGE
VGS = 0 V
~
~ 60
~
~
<5
40
1\
\
1\
u
20
4.0 V
10
20
30
VDS, DRAlN·TO·SOURCE VOLTAGE IVOLTS)
g. ~
~ ::;...--:
7.0V
SO
5.0V
'I
~
100
z
'fI
..... .....-
~ :;;.--
FIGURE 4 -
9.0V
N
./
1.2
~ 0.8
t-.
~
./
az
OUTPUT CHARACTERISTICS
z
~ 0.8
iii
1.6
1501'C)
L0o1.2
~
!Z
VGS = 10V
1.6
~
--
~
I---
40
I\,
~
-I
Coss
......
10
Crss
20
30
40
50
VOS, DRAIN·TO·SOURCE VOLTAGE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
3-158
Ciss-
...... ......
60
MFElMPF910
OUTliNE DIMENSIONS
iB--j
,) 1 t
--'l
~
RI ~~==_
I
re-
K
l
,§
Dj1i
J~
-
rtR
~-~=f
N
SEATING
PLANE
STYLE 22,
PIN 1. SOURCE
2. GATE
3. DRAIN
Q
G
PIN 1. SOURCE
2. GATE
3 DRAIN ICASEI
J
'\(V
'Y'
MILLIMETERS
DIM MIN
MAX
A
8.89
9.40
B
8.00 8.51
C
6.10 6.60
0
0.406 0.533
E
0.229 3.18
F
M06 0.483
G
4.83 5.33
H
0.711 0.864
J
0.737 1.02
K 12.70
L
6.35
M
45' NOM
P
1.27
Q
90' NOM
R
2.54
!+!II 0.10iO.0041@!T!A@!B@!
4. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5. 1973.
-
STYLE 6,
!lRo\J'
M
I
MILLIMETERS
MIN
MAX
7.37
7.87
5.21
4.44
3.18
4.19
0.61
0.46
1.27 Bse
2.54 Bse
12.70
2.03
2.92
3.43
0.46
0.61
--~
H-D
- ..
N
NOTES,
1. DIMENSIONS A
AND ·B· ARE DATUMS.
2. T IS SEATING PLANE.
3. POSITIONAL TOLERANCE FOR LEADS,
DIM
A
B
C
0
G
J
K
N
R
S
~K
-
/~
C
:
INCHES
MIN
MAX
0.290 0.310
0.175 0.205
0.125 0.165
0.Q18 0.024
0.050 Bse
0.100 BSC
0.500
0.080 0.115
0.135
0.018 0.024
-
INCHES
MIN MAX
0.350 0.370
0.315 0.335
0.240 0.260
0.016 0.021
0.009~
~
4Wl-~
J!M!!...
--=--
~
All JEOECdimenslonsand notes8pply.
CASE 79-02
TO-205AD
CASE 29-03
TO-226AE
MOTOROLA TMOS POWER MOSFET DATA
3-159
MOTOROLA
-
SEMICONDUCTOR
TECHNICAL DATA
------1
-
MFE930
MFE960
MFE990
2.0 AMPERE
N-CHANNEL ENHANCEMENT-MODE
TMOS FIELD-EFFECT TRANSISTOR
N-CHANNEL TMOS
These TMOS FETs are designed for high-speed switching applications such as switching power supplies, CMOS logic, microprocessor or TTL-to-high current interface and line drivers.
30.60.90 VOLTS
• Fast Switching Speed • Low On-Resistance -
FET
ton = toft = 7.0 ns Typ
0.9 Ohm Typ MFE930
1.2 Ohm Typ MFE960 and MFE990
• Low Drive Requirement, VGS(th) = 3.5 V Max
• Inherent Current Sharing Capability Permits Easy Paralleling of
Many Devices
1r
TMOS
Q
.~
MAXIMUM RATINGS
Rating
Drain-Source Voltage
Drain-Gate Voltage
Gate Source Voltage
Drain Current
Continuous (1)
Pulsed (2)
Total Power Dissipation
@TC = 25·C
Derate above 25·C
Operating and Storage
Temperature Range
Symbol
MFE930
MFE960
MFE990
Unit
VOSS
35
60
90
Vdc
VDGO
35
60
90
Vdc
VGS
±30
STYLE 6:
PIN 1. SOURCE
2 GATE
3. DRAIN ICASE}
Vdc
Adc
10
10M
DIM
A
B
2.0
3.0
C
Po
6.25
50
TJ,Tstg
Watts
mWI"C
·C
-55to 150
11 )The Power Dissipation of the package may result In a lower continuous drain current.
(2) Pulse Width ~ 300 IJ.s, Duty Cycle ~ 2.0%.
D
E
F
G
H
J
K
L
M
P
Q
R
MILLIMETERS
MIN
MAX
8.89
9.40
8.00 8.51
6.10 6.60
0.406 0.533
0.229 3.18
0.406 0.483
4.83 5.33
0.711 0.864
0.737 1.02
12.70
6.35
45 0 NOM
1.27
900 NOM
2.54
-
INCHES
MIN
MAX
0.350 0.370
0.315 0.335
0.240 0.260
0.016 0.021
0.009 0.125
0.016 0.019
0.190 0.210
0.028 0.034
0.029 0.040
0.500
0.250
45 0 NOM
0.050
900 NOM
0.100
-
All JEDECdimensionsand notes apply.
CASE 79-02
TO-205AD
MOTOROLA TMOS POWER MOSFET DATA
3-160
MFE930, 960, 990
ELECTRICAL CHARACTERISTICS (TA = 25"<: unless otherwise noted.)
I
Characteristic
Symbol
Min
Typ
Max
-
-
Unit
OfF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 10 jIA)
Zero Gate Voltage Drain Current
(VOS = Maximum Rating, VGS
V(BR)OSS
MFE930
MFE960
MFE990
35
60
90
-
-
lOSS
-
IGSS
-
-
VGS(th)
1.0
MFE930
MFE960
MFE990
-
Vdc
10
jlAdc
50
nAdc
-
3.5
Vdc
0.4
0.6
0.6
0.7
0.8
1.0
0.9
1.2
1.2
1.4
1.7
2.0
-
2.2
2.8
2.8
3.0
3.5
4.0
-
-
0.9
1.2
1.2
1.4
1.7
2.0
10(on)
1.0
2.0
-
Amps
9FS
200
380
-
mmhos
Ciss
-
60
70
pF
Coss
-
49
60
pF
Crss
-
13
18
pF
Turn-On Time
See Figure 1
ton
-
7.0
15
ns
Turn-Off TIme
See Figure 1
toff
-
7.0
15
ns
= 0)
Gate-Body Leakage Current
(VGS = 15 Vdc, VOS = 0)
ON CHARACTERISTICS·
Gate Threshold Voltage
(VOS = VGS, 10 = 1.0 mAl
Drain-Source On-Voltage (VGS
(10 = 0.5A)
= 10 V)
VOS(on)
(10
= 1.0 A)
MFE930
MFE960
MFE990
(10
= 2.0 A)
MFE930
MFE960
MFE990
Static Drain-Source On-Resistance
(VGS = 10 Vdc, 10 = 1.0 Adc)
Vdc
-
-
Ohms
rOS(on)
MFE930
MFE960
MFE990
On-State Drain Current
(VOS = 25 V, VGS = 10 V)
Forward Transconductance
(VOS = 25 V, 10 = 0.5 A)
DYNAMIC CHARACTERISTICS
Input Capacitance
(VOS = 25 V, VGS = 0, f
Output Capacitance
(VOS = 25 V, VGS
=
1.0 MHz)
= 0, f =
1.0 MHz)
Reverse Transfer Capacitance
(VOS = 25 V, VGS = 0, f = 1.0 MHz)
SWITCHING CHARACTERISTICS·
• Pulse Test: Pulse WIdth", 300 /IS. Duty Cycle'" 2.0%.
RESISTIVE SWITCHING
FIGURE 1 - SWITCHING TEST CIRCUIT
FIGURE 2 - SWITCHING WAVEFORMS
+25V
23
To Sampling Scope
r-TodB-l-_~=::..::~50 VnoutInput
Output Vout
Inverted
Input Vin
MOTOROLA TMOS POWER MOSFET DATA
3-161
MFE930, 960, 990
FIGURE 3 -
ON VOLTAGE versus TEMPERATURE
r- VGS
w
~
2.0 !--'-
~
1.0
1
!5
05
.
~ 0.2
>
= 10 V
-I----
-
-- -
I----
180
VGS = 0 V
160
--
,
\
~140
z
~ 100
u
;t 80
;)
40
Coss
\
_\
~ 120
,
<360
"'- ~-........;:: ~
+5.0
25
45
65
85
105
125
Crss
"'-
o
o
145
5.0
10
TJ. JUNCTiON TEMPERATURE 1°C)
FIGURE 5 -
20
Ciss
30
TRANSFER CHARACTERISTIC
VDS = 10 V
FIGURE 6 -
/
2.1
/"
OUTPUT CHARACTERISTIC
2.8
""
VGS
le
9.0
!z
8.0
a
7.0
~ 2.0
~ 1.6
f·2
1/
/
6.0
-2 0.8
.2
.!i? 0.4
/V
5.0
V
./
u
u
u
= 10 V-
2.4
_/
V
1.0
50
40
VDS. DRAiN-SOURCE VOLTAGE (VOLTS)
2.4
0.3
-r-- -
I\,
20
0.1
-55 -35 -15
CAPACITANCE VARIATION
200
-- I---
iii 5.0
g
FIGURE 4 -
-
10
4.0
u
u
n
u
u
W
5.0
VGS. GATE-SOURCE VOLTAGE (VOLTS)
10
20
FIGURE 7 -
SATURATION CHARACTERISTIC
2.8
VGS
2.4
8.0
V/
~ 1.6
#
~/
1.2
/
7.0
~ /"
~-'- 0.8
0.2
9.0
/
!z
.!i? 0.4
10~ f -
../
~ 2.0
.§.
=
./
le
az
6.0
~/
~
/"""
5.0
~
~~
0.5
30
40
VOS.DRAiN-SOURCE VOLTAGE iVOLTS)
4.0
1.0
2.0
3.0
4.0
VDS. DRAiN-SOURCE VOLTAGE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
3-162
5.0
50
MOTOROLA
_ SEMICONDUCTOR - - - - - TECHNICAL DATA
MFE9200
N-CHANNEL ENHANCEMENT-MODE
TMOS FIELD EFFECT TRANSISTOR
200 VOLTS
This TMOS FET is designed for high-voltage, high-speed switching applications such as line drivers, relay drivers, CMOS logic,
microprocessor or TTL-to-high voltage interface and high-voltage
display drivers.
N-CHANNEL TMOS
FET
,/I
ton = toft = 6.0 ns Typ
4.5 Ohms Typ
• Low Drive Requirement, VGS(th) = 4.0 V Max
• Fast Switching Speed • Low On-Resistance -
• Inherent Current Sharing Capability Permits Easy Paralleling of
Many Devices
1r
2
G0---"1
TMOS
MAXIMUM RATINGS
Symbol
Value
Unit
Drain-Source Voltage
Rating
VOSS
200
Vde
Gate-Source Voltage
VGS
±20
Vde
Drain Current
Continuous (1)
Pulsed (2)
10
10M
400
800
mAde
Total Power Dissipation
@TC = 25"C
Derate above 25"C
Operating and Storage
Temperature Range
STYlf
~N 1.
2.
3.
Watts
Po
TJ Tst'"
1.8
14.4
mW/"C
-55to 150
"C
DIM
(1 )The Power Dissipation of the package may result In a lower continuous drain current.
(21 Pulse Width .. 300 "so Duty Cycle .. 2.0%.
A
B
C
0
E
F
G
H
J
K
L
M
N
P
12:
SOURCE
GATE
DRAIN (CASEI
MILLIMETERS
MIN
MAX
5.31
4.52
4.32
0.406
5.S4
4.95
5.33
0.533
0.762
0.406 0.483
2.54 SSC
0.914 1.17
0.711 1.22
12.70
6.35
450 BSC
1.27 sse
1.27
-
-
INCHES
MIN
MAX
0.209
O.17S
0.170
0.016
-
0.016
0.230
0.195
0.210
0.021
0.030
0.01.
0.100~
0.036
0.028
0.046
0.048
O.~
0.250
45" Bse
O. 50 B.G
0.050
All JEDEC notes and dimensions applv-
CASE 22-03
TO-18
MOTOROLA TMOS POWER MOSFET DATA
3-163
-
MFE9200
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted.)
I
Symbol
Min
Orain-Source Breakdown Voltage
(VGS = 0,10 = 10,.A)
V(BR)OSS
200
Zero Gate Voltage Orain Current
(VOS = 200 V, VGS = 0)
lOSS
Gate-Body Leakage Current
(VGS = 15 Vdc, VOS = 0)
Characteristic
Typ
Max
Unit
-
-
Vdc
OFF CHARACTERISTICS
0.1
10
,.Adc
IGSS
-
0.Q1
50
nAdc
VGS(th)
1.0
-
4.0
, Vdc
-
0.45
1.20
3.0
400
700
ON CHARACTERISTICS'
Gate Threshold Voltage
(VOS = VGS, 10 = 1.0 mAl
Orain-Source On-Voltage (VGS
(10 = 100 mAl
(10 = 250 mAl
(10 = 500 mAl
=
10 V)
VOS(on)
On-State Orain Current
(VOS = 25 V, VGS = 10 V)
10(on)
State Orain-Source On-Resistance
(VGS = 10 Vdc)
(10 = 100 mAl
(10 = 250 mAl
(10 = 500 mAl
Vdc
0.6
1.60
-
Ohms
rOS(on)
Forward Transconductance
(VOS = 25 V, 10 = 250 mAl
mA
-
4.5
4.8
6.0
9fs
200
400
-
mmhos
Ciss
-
72
90
pF
6.0
6.4
DYNAMIC CHARACTERISTICS
Input Capacitance
(VOS = 25 V, VGS
= 0, f =
1.0 MHz)
Output Capacitance
(VOS = 25 V, VGS
=
1.0 MHz)
15
20
pF
Crss
-
2.8
3.5
pF
Turn-On Time
See Figure 1
ton
-
6.0
15
ns
Turn-Off Time
See Figure 1
toft
-
6.0
15
ns
0, f
=
Coss
Reverse Transfer Capacitance
(VOS = 25 V, VGS = 0, f = 1.0 MHz)
SWITCHING CHARACTERISTICS'
* Pulse Test:
Pulse Width
:os;;;
300 p.s, Duty Cycle os;; 2.0%.
RESISTIVE SWITCHING
FIGURE 1 -
SWITCHING TEST CIRCUIT
FIGURE 2 -
+25V
23
To Sampling Scope
a Input
r-20dii-l-_4~-=-=;;50Vout
Output Vout
Inverted
Input Vin
MOTOROLA TMOS POWER MOSFET DATA
3-164
SWITCHING WAVEFORMS
MFE9200
FIGURE 3 - ON VOLTAGE versus TEMPERATURE
FIGURE 4 - CAPACITANCE VARIATION
10
200
~
180
~ 5.0
'";5
~
.
O
~ 0.5
:s
~
--
VGS - 10 V
20
r'
250 rnA
L---
r--
f--
~140
~
z
120
;5100
100 rnA
I--
I---
~
80
e,,; 60
,ar
20
-35 -15
+5.0
25
45
65
85
105
125
Ciss I - -
\
\ I"--
40
0.2
0.1
-55
VGS = 0 V
160
w
145
W
o.7
/
~ 0.6
in
~ 0.5
~
~
g§
az 0.4
/
~ 0.3
c
0
;;:
2.0
3.0
V
5.0 v-
//
1//
az o.3
I
o. 2
//
c
4.0 V-
v
S
.9 O.IT
I
../
1.0
o.5
g§
/
O. 1
50
'/
/
~ o. 4
/
~
gO.2
9
10~
o. 6
/
VGS = 10 V
~
fc;;;-
40
FIGURE 6 - OUTPUT CHARACTERISTIC
FIGURE 5 - TRANSFER CHARACTERISTIC
0.7
~
20
VOS, DRAIN·SOURCE VOLTAGE (VOLTS)
TJ, JUNCTION TEMPERATURE (OC)
0.8
Coss
--..;:
o
o
3.0 V
r/'"
4.0
5.0
6.0
7.0
8.0
9.0
W
10
U
M
FIGURE 7 - SATURATION CHARACTERISTIC
0.7
~ 0.6
0.5
./
g§ 0.4
az
..-...... :..-
-- ~
~ 0.3
g
...-
15
9
........
;...--
-~
5.0 V
4.0 V
V
0.2
/'
o. 1 ;- C/
,.
W
U
M
vos, DRAIN·SOURCE VOLTAGE (VOLTS)
VGS, GATE·SOURCE VOLTAGE (VOLTS)
~
I-
M
1.0
3.0 V
2.0
3.0
4.0
VOS, DRAIN-SOURCE VOLTAGE (VOLTS)
5.0
MOTOROLA TMOS POWER MOSFET DATA
3-165
W
~
20
MOTOROLA
-
MGMSN4S
MGMSNSO
MGPSN4S
MGPSNSO
• SEMICONDUCTOR _ _ _ _ __
TECHNICAL DATA
Designer's Data Sheet
5.0 AMPERE
N-CHANNEL TMOS
GEMFET
N-CHANNEL ENHANCEMENT-MODE SILICON GATE,
INSULATED GATE BIPOLAR TRANSISTOR
'CElani = 1.6 Ohm
450 and 500 Volts
These GEMFETS are designed for high voltage, high current
power controls such as line operated motor controls and
converters.
• High Input Impedance
MGMSN4S
MGMSNSO
• Low On-Voltage, 4.0 V max @ 2.5 A @ TJ
• Fast Turn-On Time
• Voltage Driven Device
• No Parasitic Source to Drain Diode
C
lr
G
TMDS
smE6:
PIN 1. GATE
E
2.EMlmR
CASE COLLECTOR
MlLlAIElfRS
Mfj
MAX
DIM
A
B
C
D
E
F
21.08
U5
8.25
0.,
109
lAO
1.77
30.158SC
10.92BSC
5.46BSC
16.89 SSC
11.18 12.19
3.84
4.19
G
MAXIMUM RATINGSS
8¥mbol
MGM5N45
MGP5N45
MGM5N50
MGP5N50
Unit
Collector-Emitter Voltage
VCES
450
500
Vdc
Collector-Gate Voltage
(RGS = 1.0 MO)
VCGR
450
500
Vdc
Rating
Gate-Emitter Voltage
Continuous
Non-repetitive (tp '" 50
~s)
Collector Cu rrent - Continuous
-Pulsed
Total Power
Dissipation @ TC = 25·C
Derate above 25·C
Operating and Storage
Temperature Range
VGE
VGEM
±20
±40
IC
ICM
5.0
8.0
Vdc
. Vpk
CASE 1-06
TO-204AA
H
J
K
Q
R
4.83
3.84
U
V
26.67
5.33
4.19
WfC
TJ, Tstg
-65 to 150
·C
R8JC
R8JA
2.S
30(1)
0.830
0.325
0043
0,070
1.187 BSC
O. Bse
O.21SBSC
0.6<1
sse
0.440
0.151
0.48)
0.165
0.190
0.210
0.151
0.166
1.050
't·1·
uJ
Watts
50
0.4
1.550
0250
0.38
0.065
-
MGPSN45
MGP5NSO
Adc
PD
INCHES
MIN
MAX
39.37
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Junction to Ambient
·CIW
Maximum Lead Temp. for
TL
Soldering Purposes, 1/8"
from case for S seconds
(1) Add 32.5'C/W for MGP5N45 and MGP5N50.
Dot
STYLE 9:
PINt GATE
2. COLLECTOR
·C
275
lEMlmR
4. COlLECTOR
, '''',.66
A
C
D
F
G
•, ,..,
J
L
N
Designer's Data for "Worst Case" Conditions
The Designer's Data Sheet permits the design of most circuits entirely
from the information presented. Limit curves - representing boundaries
CASE 221A-04
TO-220AB
on device characteristics - are given to facilitate "worst case" design.
tiIIOTOROLA TMOS POWER MOSFET DATA
3-166
<07
'3.6154
Q
R
S
r
U
V
Z
2.42
0.3&
12.70
1.15
..3
2.54
204
1.15
'"
0.00
1.15
~
~
~
VCE = VGE
10 = 1.0mA
'"
~
~
6.0
t~
5,0
~ 3.0
-.............
25
50
75
100
TJ. JUNCTION TEMPERATURE I'CI
125
8
........,
Y
I
2.0
2.0
150
~ 1.20
~
~
240
§
20
TJ = 25'C _
VGE = 0
f= 1.0MHz-
\
Ciss
180
120
u 60
~0.15
0
18
§~
we --=
~ 0.45
~ 0.30
~
W
4.0
6.0 8.0
10
12
14
16
VGE. GATE-TO-EMlmR VOLTAGE IVOLTSI
tl
= 100'C
~~C
0.75
~ 0.60
l:'
I
FIGURE B - CAPACITANCE VARIATION
VGE = 15V
~~
~ t---.... TJ
~ 0.90
~
~25'C
300
~1.50
ihos
en
f
A
1.0
AGURE 7 - ON-RESISTANCE versus
DRAIN CURRENT
§ 1.35
~ ~IOO'C
I
:5
o
10
VCE = 25 V
a 4.0
............. r-...
0.6
-25
TJ = -55'C
g§
i!i'
!i
I
FIGURE 6 - TRANSFER CHARACTERISTICS
ie
r----....
~.OV
2.0
4.0
6.0
8.0
VCE. COLLECTOR·EMlmR VOLTAGE IVOLTSI
7.0
-- -
1
1
4.0 V
8.0
............
0.8
VGE=8.0V
L. ~
o
250
1.4
~
L-tv=
1
~
I
FIGURE 5 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
~
V
V
I
10V
6.0 V
50
100
150
200
VCE. COLLECTOR-EMITTER VOLTAGE (VOLTSI
IAv
//U /
& V .-V
I
o
o
V/
~
1
0
/ rlJ 1/
18 V- 'rtf.!
15V-
8.0V
0
lOV [II IA4V
125'C
f-- f--TJ
VGE = 10V -
1\
\ 'r-
Coss
"-
1.0
2.0
3.0
4.0
5.0
6.0
Ie COLLECTOR CURRENT (AMPSI
7.0
8.0
Crss
5.0
10
15
20
VCE. COLLECTOR-EMITTER VOLTAGE (VOLTSI
MOTOROLA TMOS POWER MOSFET DATA
3-168
25
MGM/MGP5N45,50
FIGURE 9 -- MAXIMUM RATED FORWARD BIAS
SAFE OPERATING AREA
10
FIGURE 10 -- MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
10
1.0~
1Ou.s1
0.1 ms
~
1.0m
0
dc'
i:5
g§
Paclcage Limit
r-·----·Thermal Limit
rSecond Breakdown Limit
0.0 1
1.0
MGM/MGP5N45
I I
MGMIMGP5N50
3.0 5.0
10
30 50 100
300 500 1000
VCE. COLLECTOR·EMITIER VOLTAGE (VOLTSI
i :.:
r--- r-
I - - rrI--
....... ~
Vci = Rated VCES __ j...J
VGE = 15V
RG = tom
Single Pulse
TJ '" 150'C
Vci'=
r--- ~
250~-
~
'"
.s;;
IIIII
FORWARD BIASED SAFE OPERATING AREA
The dc data of Figure 9 is based on a case temperature
(Tc) of 25'C and a maximum junction temperature
(TJmax) of 150'. The actual junction temperature depends on the power dissipated in the device and its case
temperature. For various pulse widths. duty cycles, and
case temperatures, the peak allowable collector current
OCM) may be calculated with the aid of the following
equation:
ICM
6.0
aa:
~
TC 25'C
VGE 15V
Single Pulse
I--.
I-
r-I
8.0
~
25
50
150
TJ = TC + PooRWe-r(t)
Po ROJC r(t)
0
125
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SSOA) of a GEMFET device is a composite function of gate turn-off time,
inductive clamp voltage (Vcl) and device junction temperature (TJ). Figure 10 illustrates that IC is 8.0 A for
Vcl '" 250 V and TJ '" 90'C, and for Vcl '" 500 V and TJ
'" 65'C. Additionally, it is seen that for a peak collector
current of 6.0 A, TJ must be maintained less than 130'C
for Vcl = 250 V, and less than 120·C for Vcl = 500 V.
TJ may be calculated from the equation:
= I (25'C) [TJ(max) - TC]
C
75
100
Tc. CASE TEMPERATURE ('CI
0
where
IC(25'C) = the dc collector current at TC = 25'C from
Figure 9.
TJ(max) = rated maximum junction temperature
TC
= device case temperature
= rated power dissipation at TC = 25'C
Po
RWC
= rated steady state thermal resistance
r(t)
= normalized thermal response from
Figure 11
where
Po is the power averaged over a complete switching
cycle.
Generally, SSOA current declines with decreasing
gate turn-off time. Gate turn-off time is controlled by
RG; lowering RG decreases gate turn-off time. A suggested rule-of-thumb is to derate the IC of Figure 10 by
1.0 A for every 250 ohms of RG below 1.0 kO for case
temperatures greater than 65'C.
FIGURE" -- THERMAL RESPONSE
1.0
;;;:J,
0.7 I-D
~8 0.5
~~
O. 2
Rruc(tl r(tl RruC
Rruc(tl 2.5'C/W Max
DCurves Apply for Power
Pulse Train Shown
Read Time at tl
TJ(pkl TC P(pkl Rruc(tl
..,...,;
~ ~ 0.3
~~
0.5
0.2
..... 1"""""
t--- +-0.1
+--
~~ o. 1 F==:- 0.05
....
~
HUl
~ ~O.07
0.02
!!l0.05~
U
~cn
~~o.o3 -
0.Q1
~~
.:c 0.0H-- r- - Sidgle Pulse
0.0 1
0.Q1
I
0.02 0.03
0.05
0.1
0.2
0.3
0.5
1.0
2.0 3.0
t. TIME (msl
5.0
10
20
MOTOROLA TMOS POWER MOSFET DATA
3·169
30
50
Duty Cycle. D - tl~2
100
200 300 500
1000
MOTOROLA
-
-
MGM20N45
MGM20N50
MGP20N45
MGP20N50
SEMICONDUCTOR - - - - - TECHNICAL DATA
20 AMPERE
N-CHANNEL TMOS
GEMFET
N-CHANNEL ENHANCEMENT-MODE SILICON GATE.
INSULATED GATE BIPOLAR TRANSISTOR
rCElon) = 0.27 Ohm
460 and 500 Volts
These GEMFETS are designed for high voltage. high current
power controls such as line operated motor controls and
converters..
MGM20N45
MGM20N50
• High Input Impedance
• Low On-Voltage. 2.7 V max @ 10 A
• High Peak Current Capability - 30 A
• Voltage Driven Device
C
lr
G
TMOS
DIM
STYLES'
PINt GATE
2. EMmER
CASE COUECTOR
E
MAXIMUM RATINGSS
Rating
Symbol
MGM20N45 MGM20N50
MGP20N45 MGP20N50
Unit
Collector-Emitter Voltage
VCES
450
500
Vdc
Collector-Gate Voltage
(RGS = 1.0 MOl
VCER
450
500
Vdc
Gate-Emitter Voltage
Continuous
Non-repetitive (to'" 50
CASE '·06
TO·204AA
•
B
C
D
E
F
G
H
J
K
Q
R
.\I'
V
""I
Collector Current
Continuous
Pulsed
VGE
VGEM
±20
±40
MlWMElElIS
MAX
39.37
MIll
21.08
8.25
1...
lAO
1.77
3O.1SBSC
10.92BSC
6.35
0.97
INC\IES
MAX
1.560
MIN
0.830
0.250
0,008
0,056
0.070
1.187BSC
O,430BSC
5.46BSC
O.21SBSC
16.89BSC
O.665BSC
0,440
11.18
12.19
0.080
3,84
"9 0.151 0.165
26,67'
1.050
4.83
5.33
0.190 0.210
3.84
.,
0151
Total Power
Dissipation @ TC = 25°C
Derate above 25°C
Operating and Storage
Temperature Range
0.165
-
Vdc
Vpk
Adc
IC
ICM
0.325
0.1)43
20
30
Watts
Po
100
0.8
wrc
TJ, Tstg
-65 to 150
°c
RfiJC
RfiJA
1.25
30(11
TL
275
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Junction to Ambient
Maximum Lead Temp. for
Soldering Purposes, 1/8"
from case for 5 seconds
°CIW
°C
(1) Add 32SCIW for MGP20N45 and MGP20N50.
0.100
0.025
0.142
STYlE 9:
PINt GA.lE
2. COLLECTOR
lEMlmR
4. COLLECTOR
""
0.110
0.014
0500
0,""
CASE 221A-04
TO·220AB
Deslgne"s Date for "Worst ea.... Conditions
The Designer's Data Sheet permits the design of most circuits entirely
from the information presented. Limit curves - representing boundaries
on device characteristics - are given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
3·170
0100
0.210
0.100
0080
O.
0120
0.110
0.055
Q.255
0.235
0.000
o.~
0.045
2.04
0080
MGM/MGP20N45, 50
ELECTRICAL CHARACTERISTICS (TC = 25'C unless otherwise noted)
Symbol
Characteristic
Min
Max
Unit
OFF CHARACTERISTICS
Collector-Emitter Breakdown Voltage
(VGE = 0, IC = 5.0 mAl
Vdc
V(BR)CES
MGM20N45, MGP20N45
MGM20N50, MGP20N50
450
500
Zero Gate Voltage Collector Current
(VCE = 0.85 Rated VCE, VGE = 0)
TJ = 100'C
ICES
Gate-Body Leakage Cu rrent
(VGE = 20 Vdc, VCE = 0)
IGES
-
-
mAdc
0.25
2.5
500
nAdc
ON CHARACTERISTICS'
Gate Threshold Voltage
(lc = 1.0 mA. VCE = VGE)
TJ = 100'C
VGE(th)
Collector-Emitter On-Voltage
(lC = 10 Adc, VGE = 10 V)
(lC = 20 Adc, VGE = 15 V)
(lc = 10 Adc, VGE = 10 V, TJ = 100'C)
Static Collector-Emitter On-Resistance
(VGE = 10 Vdc, IC = 10 Adc)
VCE(on)
Vdc
2.0
1.5
4.5
4.0
-
2.7
5.0
3.0
Vdc
-
Forward Transconductance
(VCE = 10 V, IC = 10 A)
rCE(on)
-
0.27
Ohms
9FS
3.0
-
mhos
pF
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VCE = 25 V, VGE = 0, f = 1.0 MHz)
Reverse Transfer Capacitance
Ciss
-
950
Coss
-
150
Crss
-
60
-
0.075
SWITCHING CHARACTERISTICS* (TJ = 100'C)
RESISTIVE SWITCHING
Turn-On Delay Time
td(on)
(VCE = 250 V, IC = 20 A.
RG = 1.0n,
Vin = 15V)
Rise Time
Turn-Off Delay Time
Ici(off)
-
tf
-
8.0
td(off)
-
4.0
tc
-
6.0
tdloff)
-
9.5
tc
-
9.5
tr
Fall Time
p.s
0.15
4.0
INDUCTIVE SWITCHING
Turn-Off Delay Time
(Vcl amp = 250 V,
ICM = 20 A,
L=1BOp.H,
Vin = 15V)
Crossover Time
Turn-Off Delay Time
Crossover Ti me
*Pulse Test: Pulse Width os;; 300
J,J.S,
Duty Cycle
~
RG = 1.0 kn
RG = 4.0 kn
2.0%.
RESISTIVE SWITCHING
FIGURE 1 -
FIGURE Z -
SWITCHING TEST CIRCUIT
V
RLC 1Vout
td(on)
DUT
Pulse Generator
r- -Rgen - - - j
:
I
I
IL
50n:
"
Output, Vout
Inverted
:
I
_______ .JI
MOTOROLA TMOS POWER MOSFET DATA
3-171
SWITCHING WAVEFORMS
p.s
MGMlMGP20N45, 50
TYPICAL ELECTRICAL CHARACTERISTICS
FIGURE 3 -
FIGURE 4 - ON-REGION CHARACTERISTICS
OUTPUT CHARACTERISTICS
40
TJ ='25'C
'--
1
I--
40
V~E J2V
32
~ 24
lJV
a
t; 16
~
~
a:
24
I
6.0V
I
o
o
o
250
50
100
150
200
VCE, ORAIN-TO-SOURCE VOLTAGE ,VOLTSI
~z
~
1.0
--~
............
i
$ -so
-JCE
~ 0.4
125
~/
l00"C
'//
~
II
L4'
o
o
150
{h
I!J
24
.y 8.0
I"-....
25
50
75
100
TJ, JUNCTION TEMPERATURE ('CI
10
2.0
~
4.0
6.0 8.0
10
12
14
16
VGE, GATE-TO-EMlmR VOLTAGE (VOLTSI
18
20
FIGURE 8 - CAPACITANCE VARIATION
1250
VG~ = lJV
1\
\
~
1000
~
"- ~ :::,....
::;;
0_2
z
~
TJ -l00"C-
4.0
Ciss
if 500
;)
u
25"Cj -55,_
~
~ ..... Coss
250
o
2.0
.....
u
'-
8 0.1
\,.
~ 750
-
TJ = 25"C
VGE = 0 - !--f= 1.0 MHz- f - -
:\
,s,
0.3
00
25"C
~
..........
~ 0_5
§
~OV
t; 16
o
-25
TJ = -55"C_
FIGURE 7 - ON-RESISTANCE versus
DRAIN CURRENT
~
I
2.0
4.0
6.0
8.0
VCE, DRAIN·TO-SQURCE VOLTAGE (VOLTSI
:5
::. 0.6
~
6.0 V
J~
o
~ 32
Ia
'"
~
~
I
fI . /
IU-
1e
-
.......... .....
~ 0.8
~
I
8.0 V
/
VCE = VGE
lo=1.0mA
~
I
l~V- r-
FIGURE 6 - TRANSFER CHARACTERISTICS
~
~ 1.4
1.2
.,,"
!. V-
FIGURE 5 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
i
I
h
I. V
Y
§ 16
~
.y 8.0
8.0 V
.Y 8.0
32 -TJ= 25!C
a
I
:5
..I
1.
14V -VGE
= 12V- ' - -
if
~
I
!Z
fOV; I'
6_0 8.0
10
12
14
IC, COLLECTOR CURRENT (AMPSI
16
18
o
20
C...
5
W
ffi
~
VCE, COLLECTOR-EMlmR VOLTAGE (VOLTSI
MOTOROLA TMOS POWER MOSFET DATA
3-172
25
MGM/MGP20N45, 50
FIGURE 9 - MAXIMUM RATED FORWARD BIAS
SAFE DPERAnNG AREA
AGURE 10 - MAXIMUM RATED SWITCHING
SAFE OPERAnNG AREA
50
40
30
~ 20
~
10
IX:
5.0
3.0
2.0
i
a
-1. ~
1111
-r-.: ~ -..;:::
I--VcJ
lie
=
- ' '.00"0
Vel = Rated VCES_ 1----/
VGE = 15V
RG = 4.0kO
Single Pulse
TJ';; 15O"C
._JO
Breakdown
1.0 ~ Thennsl Limit
Pack.age Limit
~ 0.50
u 0.30
.s;. 0.20 - TC = 25°C
r- VGE = 15V
0.10
~,Single Pulse
0.05
1.0
10
100
0.1
VCE, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
~
=,
-
= 250 V
I=:::::".
.Mq~~,N~:
25
1000
= I (250C) [TJ(max) - TC]
C
150
125
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SSOA) of a GEMFET device is a composite function of gate turn-off time,
inductive clamp voltage (Vcl) and device junction temperature (TJI. Figure 10 illustrates that IC is 30 A for Vcl
'" 250 V and TJ '" 87.5°C, and for VcI '" 500 V and TJ
'" 62.5°C. Additionally, it is seen that for a peak collector
current of 24 A, TJ must be maintained less than 118°C
for Vcl = 250 V; and less than 106°C for Vcl = 500 V.
TJ may be calculated from the equation:
FORWARD BIASED SAFE OPERATING AREA
The dc data of Figure 9 is based on a case temperature
(TC) of 25°C and a maximum junction temperature
(TJmax) of 150°. The actual junction temperature depends on the power dissipated in the device and its case
temperature. For various pulse widths, duty cycles, and
case temperatures, the peak allowable collector current
(lCM) may be calculated with the aid of the following
equation:
ICM
75
100
TC, CASE TEMPERATURE 1°C)
50
TJ
Po " R9JC " r(t)
=
TC
+ Po"R9Jc"r(t)
where
Po is the power averaged over a complete switching
where
IC(25°C) = the dc collector current at TC = 25°C from
Figure 9.
TJ(maxl = rated maximum junction temperature
TC
= device case temperature
Po
= rated power dissipation at TC = 25°C
R9JC
= rated steady state thermal resistance
r(t)
= normalized thermal response from
Figure 11
cycle.
Generally, SSOA current declines with decreasing
gate turn-off time. Gate turn-off time is controlled by
RG; lowering RG decreases gate turn-off time. A suggested rule-of-thumb is to derate the IC of Figure 10 by
25 A for every 1100 ohms of RG below 4.0 kO for case
temperatures greater than 55°C.
FIGURE 11 - THERMAL RESPONSE
1.0
5~
g;;
!i,i ~
0.5
0
~ 0.5
o.~
0.3
0,2
0.1
0.05
~~ 0.1
Bin
~ ~ 0.05
~~ 0.03
IX:
~O.02
0.01
~
0.02
-
....
--- -'"
i-"
....
Plpk)
RIIJClt) rill RIIJC
1.25'C/W Max
R/lJC
oCURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT 11
TJlpk) TC Plpk) R/lJCII)
tJUl
1:~
IA"1
DUTY CYCLE, 0 = tlh2
~~.~1
",-
srglerm
0.01
0.05
0.02
-
-:
P"""
0.1
0.2
0.5
1.0
2.0
5.0
I, TIME Ims)
II
10
20
MOTOROLA TMOS POWER MOSFET DATA
3-173
so
IIII
100
200
500
I
1000
MOTOROLA
• TECHNICAL
SEMICONDUCTOR
-------------DATA
MMBF170
Advance Information
Small-Signal
Field Effect Transistor
N-Channel Enhancement-Mode
Silicon Gate TMOS
N-CHANNEL
SMALL-SIGNAL
TMOS FET
rOSlon) = 5 OHMS
60 VOLTS
This TMOS FET is designed for high voltage, high
speed power switching applications such as switching regulators, converters, solenoid and relay
drivers.
• Silicon Gate for Fast Switching Speeds
G
CASE 318-02
SOT·23
MAXIMUM RATINGS
Symbol
Value
Unit
Drain-Source Voltage
Rating
VOSS
60
Vdc
Gate-Source Voltage
VGS
±20
Vdc
Drain Current -
10
10M
0.5
0.8
Adc
Po
550
mW
4.4
mWrC
Continuous
Pulsed
Total Power Dissipation FR5 Board 1" x 0.75" x 0.62"
Derate above 25'C
TJ
-55 to + 125
·C
Tstg
-55 to +150
·C
Symbol
Min
Max
Unit
VGS(th)
0.8
3
Vdc
rOS(on)
-
5
Ohm
10(off)
-
0.5
Operating Temperature Range
Storage Temperature Range
THERMAL CHARACTERISTICS
Thermal Resistance Junction to Case
ELECTRICAL CHARACTERISTICS (TC
I
= 25'C unless otherwise noted)
I
Characteristic
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage (VGS
= 0, 10 = 100 !LA)
Gate-Body Leakage Current, Forward (VGSF
=
15 Vdc, VOS
= 0)
ON CHARACTERISTICS'
Gate Threshold Voltage (VOS
=
= 1 mAl
= 10 Vdc, 10
25 V, VGS = 0)
VGS, 10
Static Drain-Source On-Resistance (VGS
On-State Drain Current (VOS =
= 200 mAl
!LA
(continued)
'Pulse Test: Pulse Width", 300 ILS, Duty Cycle" 2%.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MOTOROLA TMOS POWER MOSFET DATA
3-174
MMBF170
ELECTRICAL CHARACTERISTICS - continued (Te = 25°e unless otherwise noted)
I
Characteristic
Symbol
Max
Min
Unit
DYNAMIC CHARACTERISTICS
Input Capacitance
(VOS
=
10 V, VGS
= a V, f
= 1 MHz)
SWITCHING CHARACTERISTICS·
(VOO = 25 V, 10 = 500 mA,
Rgen = 50 Ohms)
Figure 1
Turn-On Delay Time
Turn-Off Delay Time
*Pulse Test: Pulse Width ,e;: 300 p.s, Duty Cycle
~
2%.
+25V
SWITCHING WAVEFORM
125n
TO SAMPLING
SCOPE
50n INPUT
VOU!
Vin
(Vin AMPLITUDE 10 VOLTS)
Figure 1. Switching Test Circuit
I',
OUTLINE DIMENSIONS
NOTES;
1. DIMfNSIONING AND TOlERANCING PER Yl{SM,
1982
2. CONTROlliNG DlMENSJON; INCH;
MlLUMrnRS
DIM
MIN
MAX
A
2.80
1.20
0.85
0.37
0.085
1.78
0.51
0.10
2.10
0.45
0.89
3.04
1.40
1.20
0.46
0.130
2.04
0.80
0.25
2.50
0.80
1.02
8
smE21;
~N 1. GATE
2.S0URCE
3.DRAlN
C
D
F
G
H
K
L
M
N
INCHES
MIN
MAX
0.1102 0.1197
0.1l472 0.0551
0.033 0.0472
0.0150 0.0177
0.0034 0.0051
0.0701 0.0807
0.0200 0.023
0.0040 0.0098
0.0830 0.0984
O.D180 0.0238
0.0350 0.0401
CASE 318-02
SOT-23
MOTOROLA TMOS POWER MOSFET DATA
3-175
MOTOROLA
• TECHNICAL
SEMICONDUCTOR
-------------DATA
MPF480
MPF481
Advance Information
Small-Signal
Field Effect Transistor
N-Channel Enhancement-Mode
Silicon Gate TMOS
SMALL-SIGNAL
N-CHANNEL
TMOSFETs
I"I)Slon) = 80 OHMS
80 VOLTS
I"I)Slon) = 140 OHMS
180 VOLTS
This TMOS FET is designed for high-voltage, high-speed
switching applications such as line drivers, relay drivers,
CMOS logic, microprocessor of TTL-to-high voltage interface and high voltage display drivers.
•
•
•
•
Silicon Gate for Fast Switching Speeds
Low Input Capacitance
Low Drive Current
Inherent Current Sharing Capability Permits Easy
Paralleling of Many Devices
CASE 2S-04
G
TO-226AA
MAXIMUM RATINGS
Symbol
MPF480
Drain-Source Voltage
VOSS
80
Gate-Source Voltage
VGS
Drain Current - Continuous (1)
- Pulsed (2)
10
10M
Rating
Total Power Dissipation @ TC = 25"C
Derate above 25"C
Lead Temperature (1116" from case for 10 sec)
MPF481
Unit
180
Vdc
10
20
nAdc
±20
50
80
I
Vdc
350
2.8
mWatts
mWFC
TL
300
"C
TJ, Tstg
-55 to +150
"C
Po
Operating and Storage Temperature Range
I
I
ELECTRICAL CHARACTERISTICS (TA = 25"C unless otherwise noted.)
I
Characteristics
Symbol
Min
Max
V(BR)DSS
80
180
-
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 1 pA)
MPF480
MPF481
Zero Gate Voltage Drain Current
(VGS = 0)
VDS = 72 V, MPF480
VDS = 162 V, MPF481
Gate-Body Leakage Current (VGS = 15 V, VDS = 0)
lOSS
IGSS
-
-
(1) The Power Dissipation of the package may result in a lower continuous drain current.
(2) Puis. Width '" 300 "'s. Duty Cycle'" 2%.
This document contains information on a new product. Specifications and information herein are subject to change without notica.
MOTOROLA TMOS POWER MOSFET DATA
3-176
-
Vdc
10
10
nAdc
1
nAdc
(continued)
MPF480,81
ELECTRICAL CHARACTERISTICS - continued
I
ITA
=
25°C unless otherwise noted.)
I
Characteristics
Symbol
Min
Max
Unit
VGSlth)
0.5
3
Vdc
-
80
140
Ohm
-
ON CHARACTERISTICS
Gate Threshold Voltage
IVos = 3 V, '0 = 10 pA)
Static Orain-Source On Resistance
IVGS = 10 V, 10 = 10 rnA)
MPF480
MPF481
rOSlon)
On-State Orain Current
IVOS = 10 V. VGS = 10 V)
MPF480
MPF481
'Olon)
50
10
-
rnA
-
9fs
8
-
mmhos
Input Capacitance
IVGS = 0, VOS = 10 V, f = 1 MHz)
Ciss
-
8
pF
Reverse Transfer Capacitance
IVOS = 0 V, VGS = 0 V)
Crss
-
7
pF
tl on)
-
20
ns
t(off)
-
20
ns
Forward Transconductance
IVOS = 15 V, 10 = 10 rnA)
CAPACITANCE
SWITCHING CHARACTERISTICS
Turn-On Time
NOO = 25 V, 10 = 50 rnA, RL = 500
n, RG
= 50 0.)
Turn-Off Time
(VOO = 25 V, 10 = 50 rnA, RL = 500
n, RG
= 50
n)
OUTLINE DIMENSIONS
DIM
A
B
C
0
F
G
H
J
K
L
N
p
R
S
MILLIMETERS
MIN
MAX
4.32
5.33
4.45
5.20
3.1a
4.19
0.41
0.55
0.41
0.48
1.39
l.15
2.54
1.41
2.66
12.70
6.35
1.66
1.04
2.93
3.43
0.39
0.50
INCHES
MIN
MAX
0.170
0.110
0.175
0.105
0.115
0.165
0.016
0.011
0.016
0.019
0.045
0.055
0.100
0.095
0.105
0.500
0.250
0.080
0.105
0.115
0.135
0.015
0.010
CASE 29-04
TO-226AA
r-tB
'~~~l
---r
NOTES:
l. CONTOUR OF PACKAGE BEYOND ZONE "P" IS
UNCONTROLLED.
2. DIM "F" APPLIES BElWEEN "H" AND "L". DIM
"0" & "S" APPLIES BElWEEN "L" & 12.7Omm
10.5'" FROM SEATING PLANE. LEAD DIM IS
UNCONTROLLED IN "H" & BEYOND 11.70mm
lOS' FROM SEATING PLANE.
3. CONTROLLING DIM: INCH.
STYLE 21:
PIN 1. SOURCE
1. GATE
3. DRAIN
n-~
~
"~
SOAIING PlANEF -
C
N
MOTOROLA TMOS POWER MOSFET DATA
3-177
L
~K
D:Jp_~
I
~
SlCT.A·A
-
MOTOROLA
-
SEMICONDUCTOR
MPF930
MPF960
MPF990
TECHNICAL DATA
N-CHANNEL ENHANCEMENT-MODE
TMOS FIELD-EFFECT TRANSISTOR
2.0 AMPERE
N-CHANNEL TMOS
These TMOS FETs are designed for high-speed switching applications such as switching power supplies. CMOS logic. microprocessor or TTL to current interface and line drivers.
• Fast Switching Speed • Low On-Resistance -
FETs
35.60. 90 VOLTS
ton = toff = 7.0 ns typ
0.9 Ohm typ MPF930
1.2 Ohm typ MPF960 and MPF990
• Low Drive Requirement. VGS(th) = 3.5 V max
• Inherent Current Sharing Capability Permits Easy Paralleling of
Many Devices
,r
I
Go-----'(
---f
TMOS
S
K
D-='ifti
-~
~~~
SEn A-A
r--t-R
MAXIMUM RATINGS
Rating
Symbol
MPF930 MPF960 MPF990
Unit
Drain-Source Voltage
VOSS
35
60
90
Vdc
Drain-Gate Voltage
VOGO
35
60
90
Vdc
Gate Source Voltage
VGS
Vdc
±30
Total Power Dissipation
10
10M
Thermal Resistance
C
N
N
IflJl 0.10 (o.o04)@lITIA@IB@l1
4. DIMENSIONING AND TOLERANCING
PER ANSI YI4.5. 1973.
1.0
Watts
8.0
mW/OC
TJ. Tstg
-55 to 150
°C
8JA
125
°C/W
Po
@TA=25°C
Derate above 25°C
Operating and Storage
Temperature Range
2.0
3.0
~
f1!'f
NOTES:
1. DIMENSIONS ·A· AND ·B· ARE DATUMS.
2. ·T· IS SEATING PLANE.
3. POSITIONAL TOLERANCE FOR LEADS:
Adc
Orain Current
Continuous 111
Pulsed 121
STYLE 22:
PIN 1. SOU RCE
2. GATE
3. DRAIN
MILLIMETERS
DIM
A
B
C
D
G
J
K
(1) The Power Dissipation of the package may result in a lower continuous drain current.
N
(2) Pulse Width .. 300 ~s. Duty Cycle .. 2.0%.
R
S
MIN
MAX
7.37
7.87
4.44
5.21
3.18
4.19
0.46
0.61
1.27 BSC
2.54 BSC
12.70
2.03
2.92
3.43
0.46
0.61
CASE 29-03
TO-226AE
MOTOROLA TMOS POWER MOSFET DATA
3-178
MFE930, 960, 990
ELECTRICAL CHARACTERISTICS (TA = 25'C unless otherwise notedl
I
I
Min
Typ
Max
35
60
90
-
-
lOSS
-
-
10
",Adc
IGSS
-
-
50
nAdc
Gate Threshold Voltage
(10 = 1.0 mA, VOS = VGSI
VGS(thl
1.0
-
3.5
Vdc
Drain-Source On-Voltage (VGS = 10 V)
(10 = 0.5 A)
MPF930
MPF960
MPF990
VOS(onl
-
0.4
0.6
0.6
0.7
0.8
11.0
0.9
1.2
1.2
1.4
1.7
2.0
-
2.2
2.8
2.8
3.0
3.5
4.0
-
-
1.4
1.7
2.0
Charactarlstic
Symbol
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0,10 = 10 ",AI
Zero Gate Voltage Drain Current
(VOS = Maximum Rating, VGS
V(BRIOSS
MPF930
MPF960
MPF990
=
Vdc
-
-
01
Gate-Body Leakage Current
(VGS = 15 Vdc, VOS = 01
ON CHARACTERISTICS'
(10
(10
=
=
1.0 A)
-
MPF930
MPF960
MPF990
-
MPF930
MPF960
MPF990
2.0 AI
Static Drain-Source On-Resistance
MPF930
(VGS = 10 Vdc, 10 = 1.0 Adcl
MPF960
MPF990
Vdc
rOS(onl
Ohms
-
0.9
1.2
1.2
On State Drain Current
(VOS = 25 V, VGS = 10 V
10(onl
1.0
2.0
Forward Transconductance
(V OS = 25 V, 10 = 0.5 A)
9FS
200
380
Cis.
-
60
70
pF
Coss
-
49
60
pF
Crss
-
13
18
pF
Turn-On Time
See Figure 1
ton
-
7.0
15
ns
Turn-Off Time
See Figure 1
toft
-
7.0
15
ns
-
Amps
mmhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(VOS = 25 V, VGS
=
0, f
=
1 MHzl
Output Capacitance
(VOS = 25 V, VGS
=
0, f
=
1 MHzl
Reverse Transfer Capacitance
(VOS = 25 V, VGS = 0, f = 1 MHzl
SWITCHING CHARACTERISTICS'
* Pulse Test: Pulse Width
:!6;
300 jJ.s, Duty Cycle ~ 2%.
RESISTIVE SWITCHING
FIGURE 1 -
FIGURE 2 -
SWITCHING TEST CIRCUIT
+25 V
23 0
Pulse Generator
To Sampling Scope
r-uid'iir.--eE7=-=-3-;50 n Input
Vout
r----'
)
(
Output Vout
Invened
I
Input Vin
MOTOROLA TMOS POWER MOSFET DATA
3-179
SWITCHING WAVEFORMS
MPF930, 960, 990
FIGURE 3 -
ON VOLTAGE versus TEMPERATURE
FIGURE 4 -
10
u;
!:i 5.0
o
2-
-VGS = 10V
w
'"~ 2.0
§2
~ 1.0
a:
-
180
-
--
z
~140
~ 100
u
;t 80
;)
<.560
40
'"ci>0.2
c
""- f'...
-........;:
f"-.....
L'\.
20
>
-35
-15
+5.0
25
45
65
85
105
125
o
o
145
Coss
1
-"'-
~ 120
>-0.1
-55
\
z
0.5
~
VGS = 0 V
160
::>
1il
r---
FIGURE 5 -
w
u
TRANSFER CHARACTERISTIC
FIGURE 6 ~
VDS=10V
u;
~ 1.8
0.9
~
~
8.0
1.6
::>
7.0
u
~1. 2
'"~0.8
6.0
o
.90.4
5.0
/
w
V
./
u
u
u
10 V-
S 2.0
/
0.3
=
9.0
::;;
I-
1/
E> 0.6
50
OUTPUT CHARACTERISTIC
VGS
/
1
40
~ 2.4
V
1.2
~
2.8
~
/'"
2.1
a
w
VDS. DRAIN SOURCE VOLTAGE (VOLTSI
2.4
S
~ 1.5
Ciss
-r---t-
Crss
TJ. JUNCTION TEMPERATURE (OCI
a:
CAPACITANCE VARIATION
200
4.0
u
u
~
u
u
u
W
FIGURE 7 -
SATURATION CHARACTERISTIC
2.8
VGS = 10;-
u; 2.4
~
....V/
.fi / "
1.6
u
~ 1.2
~
~0.8
o
.90.4
0.2
L
8.0
7.0
~./
.../
6.0
~
'"z
A I/"'"
5.0
'#¥
~V
0.5
+9.0
.L
S2.0
I-
~
::>
~
40
VDS,DRAIN-SOURCE VOLTAGE (VOLTSI
VGS. GATE-SOURCE VOLTAGE (VOLTSI
i'5
w
w
4.0
3.
1.0
3.0
2.0
4.0
5.0
VDS. DRAIN·SOURCE VOLTAGE (VOLTSI
MOTOROLA TMOS POWER MOSFET DATA
3-180
50
MOTOROLA
-
SEMICONDUCTOR
TECHNICAL
DATA
-------------MPF4150
Advance Information
Small-Signal
Field Effect Transistor
Silicon Gate TMOS
•
•
•
•
625mW
TMOS FET
'DSlon) = 12 OHMS
150 VOLTS
N-CHANNEL
DEPLETION MODE
Normally Closed Relay
Telephone Line Switching
Fail Safe Systems
Current Regulator Circuits
G
MAXIMUM RATINGS
Symbol
Value
Unit
Orain-Source Voltage
VOS
150
Vdc
Orain-Gate Voltage
VOG
150
Vdc
Orain Current - Continuous
-Pulsed (1)
10
10M
250
500
mA
Po
625
5
mW
mW/"C
TJ, Tstg
-65 to +150
°C
Rating
Total Oevice Oissipation @ TA
Oerate above 25°C
= 25°C
Operating and Storage Junction Temperature Range
CASE 29-04
TO-226AA
PLASTIC PACKAGE
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
I
Characteristic
Symbol
Min
V(BR)OSX
-150
VGS(off)
-1
Max
Unit
OFF CHARACTERISTICS
Breakdown Voltage Orain to Source
(VGS = -10V,10 = 10pA)
Gate-Source Cutoff Voltage
(VOS = 3.5 V, '0 = 1 pAl
Gate Reverse Leakage
(VGS
=
-20 V, VOS
-
Vdc
-6
Vdc
1
nAdc
-800
mAde
-
12
Ohms
Yfs
100
-
Ciss
-
125
pF
C rss
-
15
pF
IGSS
= 0)
-
ON CHARACTERISTICS
Zero-Gate Voltage Orain Current (2)
(VOS = 10 V, VGS = 0)
lOSS
Static Orain-Source On-Resistance
(VGS = 0 V, 10 = 100 mAl
rOS(on)
-100
SMALL-SIGNAL CHARACTERISTICS
Forward Transadmittance (2)
(VOS = 10 V, 10 = 50 mA. f
Input Capacitance
(VOS = 10 Vdc, VGS
=
=
-10 V, f
Reverse Transfer Capacitance
(VOS = 10 V, VGS = -10 V, f
mmhos
1 kHz)
=
=
1 MHz)
1 MHz)
(1) The Power Dissipation of the package may result in a lower continuous drain current.
12) Pulse Width" 300 1'5, Duty Cycle" 2%.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MOTOROLA TMOS POWER MOSFET DATA
3-181
MPF4150
OUTLINE DIMENSIONS
NOTES:
1. CONTOUR OF PACKAGE BEYOND ZONE "P" IS
UNCONTROLLED.
2. DIM "F" APPLIES BETWEEN "H" AND "L". DIM
"0" & "S" APPLIES BETWEEN "L" & 12.70mm
to.5"1 FROM SEATING PLANE. LEAD DIM IS
UNCONTROLLED IN "H" & BEYOND 12.70mm
tO$') FROM SEATING PLANE.
3. CONTROLLING DIM: INCH.
STYLE 23:
PIN 1. GATE
2. SOURCE
3. DRAIN
CASE 29·04
PLASTIC PACKAGE
TO·226M
MOTOROLA TMOS POWER MOSFET DATA
3·182
DIM
A
B
C
o
F
G
H
J
K
L
N
P
R
S
MILUMETERS
MIN
MAX
4.32
5.33
4.45
5.20
3.18
4.19
0.41
0.55
0.41
0.48
1.15
1.39
2.54
2.42
2.66
12.70
6.35
2.04
2.93
3.43
0.39
2.66
0.50
INCHES
MIN
MAX
0.210
0.205
0.165
0.022
0.019
0.055
0.100
0.095
0.105
0.500
0.250
0.080
0.105
0.115
0.135
0.015
0.020
0.170
0.175
0.125
0.016
0.016
0.045
MOTOROLA
-
SEMICONDUCTOR
TECHNICAL DATA
------1
MPF9200
200 VOLTS
N-CHANNEL ENHANCEMENT-MODE
TMOS FIELD-EFFECT TRANSISTOR
N-CHANNEL TMOS
FET
ThisTMOS FET is designed for high voltage, high speed switching
applications such as line drivers, relay drivers, CMOS logic, microprocessor or TIL to high voltage interface and high voltage display
drivers.
•
Fast Switching Speed -
•
Low On-Resistance -
ton
=toff = 6.0 ns typ
4.5 Ohms typ
•
Low Drive Requirement, VGS(th) = 4.0 V max
•
Inherent Current Sharing Capability Permits Easy Paralleling of
Many Devices
1r
TMOS
STYlE 30:
~N 1. DRAIN
1. GATE
3. SOURCE
MAXIMUM RATINGS
Rating
Drain~Source
Voltage
Symbol
Value
Unit
Vde
NOTES:
1. CONTOUR OF PACKAGE BEYOND ZONE "P" IS
UNCONTROLLED.
1. DIM "F" APPLIES BElWEEN "H" AND "L". OIM
VOSS
200
Gate-Source Voltage
VGS
±20
Vde
Drain Current -
10
10M
400
BOO
mAde
Po
0.6
4.B
Watts
mW/oC
TJ, Tstg
-55 to 150
°C
DIM
A
8JA
208
°C/W
8
C
Continuous (1)
Pulsed (2)
Total Power Oissipation @ TA = 25°C
Derate above 25°C
Operating and Storage Temperature Range
Thermal Resistance Junction to Ambient
(1) The Power Dissipation of the package may result In a lower continuous drain current.
(2) Pulse Width -s:;;; 300 p.S, Duty Cycle ~ 2.0%.
"0" & "S" APPliES BETWEEN "l" & 12.70mm
10.5"1 FROM SEATING PLANE. LEAD OIM IS
UNCONTROLLED IN "H" & BEYOND 12.70mm
10.5"1 FROM SEATING PLANE.
3. CONTROLLING DIM: INCH.
D
F
G
H
J
K
L
N
P
R
S
MIllIMETERS
MIN
MAX
4.32
5.33
4.45
5.10
419
3.18
0.41
0.55
0.41
0.48
1.15
1.39
2.54
2.42
2.66
12.70
6.35
2.66
2.04
2.93
3.43
0.39
0.50
INCHES
MIN
MAX
0.210
0.170
0.175
0.105
0.115
0.165
0.016
0.022
0.016
0.019
0.045
0.055
0.100
0.095
0.105
0.500
0.250
0.105
0.080
0.115
0.135
0.015
CASE 29-04
(TO-921
MOTOROLA TMOS POWER MOSFET DATA
3-183
0.020
-
MPF9200
I
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted.)
I Symbol
Characteristic
Min
Typ
Max
Unit
Vdc
OFF CHARACTERISTICS
Orain-Source Breakdown Voltage
(VGS = O. 10 = 10 !SA)
V(BR)OSS
200
-
-
Zero Gate Voltage Orain Current
(VOS = 2DD V. VGS = 0)
lOSS
-
0.1
10
pAdc
Gate-Body Leakage Current
(VGS = 15 Vdc. VOS = 0)
IGSS
-
0.01
50
nAdc
-
4.0
Vdc
-
--
0.45
1.20
3.0
0.6
1.60
400
700
-
6.0
6.4
ON CHARACTERISTICS·
Gate Threshold Voltage
(10 = 1.0 rnA. VOS = VGS)
VGS(th)
Orain-Source On-Voltage (VGS = 10 V)
(10= 100 rnA)
(10= 250 rnA)
(10= 500 rnA)
VOS(on)
On State Drain Current
(VOS = 25 V. VGS = 10 V
10(on)
Static Drain-Source On-Resistance
(VGS = 10 Vdc)
(10 = 100 rnA)
(10= 250 rnA)
(l0=5DDmA)
1.0
Vdc
-
rnA
Ohms
rOS(on)
-
4.5
4.8
6.0
9FS
2DD
400
-
Input Capacitance
OVOS = 25 V. VGS= O. 1= 1.0 MHz)
Ciss
-
72
90
pF
Output Capacitance
(VOS = 25 V. VGS = O. 1= 1.0 MHz)
Coss
-
15
20
pF
Reverse Transfer Capacitance
(VOS= 25 V. VGS = O. 1= 1.0 MHz)
Crss
-
2.8
3.5
pF
Turn-On Time
See Figure 1
ton
-
6.0
15
ns
Turn-Oil Time
See Figure 1
toll
-
12
15
ns
-
Forward Transconductance
(VOS = 25 V. 10 = 250 rnA)
mmhos
DYNAMIC CHARACTERISTICS
SWITCHING CHARACTERISTICS·
·Pulse Test: Pulse Width E;; 300 p.S, Duty Cvcle ~ 2%.
RESISTIVE SWITCHING
FIGURE 1 -
FIGURE 2 -
SWITCHING TEST CIRCUIT
+25V
Pulse Generator
Ic----,I
I,
i
Vin
---
~01!---1
,-
500
L- _ _ _ .J
":'
":"
1
Output Vout
Inverted
Input Vin
MOTOROLA TMOS POWER MOSFET DATA
3-184
SWITCHING WAVEFORMS
MPF9200
FIGURE 3 - ON VOLTAGE versus TEMPERATURE
FIGURE 4 - CAPACITANCE VARIATION
10
~
g
200
180
5.0
w
VGS
C>
~ 2.0
~
z
~
0.5
~ 0.2
>
--
10 V
250 rnA
-I-- I--"
~ 1.0
g
=
-
O. 1
-55 -35 -15
VGS = 0 V
160
~140
I--
~
z
12
°l
~100
~ 80 1\\.....
r----
100 rnA
U
60
o,t ............
25
45
65
85
105
125
\.
0
145
10
TJ, JUNCTION TEMPERATURE 1°C}
>-
/
0
ifi
/
o. 4
~
o.3
a
9
2.0
3.0
5.0 I(
/
/
1/
II
4.0 V-
I
c
I
1/
o. l V
II
,.....
./
1.0
50
/
O. 5
~
a
/
1
40
:/
~O. 2
2
30
/'
10V
~ O.6
::;;
~
3
fc;;;'"
FIGURE 8 - OUTPUT CHARACTERISTIC
VDS; 10V
5
20
O. 7
/
0.7
Coss
VDS, DRAIN - SOURCE VOLTAGE (VOLTS)
FIGURE 5 - TRANSFER CHARACTERISTIC
0.8
-
\
40
+5.0
Cjss
u
4.0
5.0
6.0
7.0
8.0
9.0
10
3.0 V
2.0
4.0
VGS, GATE·SOURCE VOLTAGE (VOLTS)
6.0
FIGURE 7 - SATURATION CHARACTERISTIC
0.7
~ 0.6
::;;
~ 0.5
~
.....- .....-
a: 0.4
.......: :;....-
a
z
~
a
/
o. 1 /" V
~
9
..-
L:. ;...-I"""
0.3
/'
0.2
8.0
10
12
14
VDS, DRAIN·SOURCE VOLTAGE (VOLTS)
.........
--
1~
...5.0 V
4.0 V
3.0 V
Ii'"
1.0
2.0
3.0
4.0
VDS, DRAIN·SOURCE VOLTAGE (VOLTS)
5.0
MOTOROLA TMOS POWER MOSFET DATA
3-185
16
18
20
MOTOROLA
-
SEMICONDUCTOR
-------------TECHNICAL
DATA
MPM3002
Advance Information
TMOS Power Module
P-Channel Power MOSFET and
N.,.Channel SENSEFET™ in a Full
H-Bridge Configuration
TMOS POWER MOSFET
H-BRIDGE
100 VOLTS
The MPM3002 is a H-Bridge power circuit with lossless current sensing capability. The
upper legs of the bridge consists of P-Channel power MOSFETs and the lower legs of
the bridge consist of two SENSEFETs. This power circuit is ideal for applications such as
servo motor drives, stepper motor controls and switching power supplies. Features of
this product include:
•
•
•
•
•
P and N-Channel Power MOSFET Configuration for Ease of Drive
Lossless Current Sensing in Each Leg of the H-Bridge
Isolated Package with 2 kV Isolation Voltage Rating
High Power Handling Capability - 62.5 Watts
High Peak Current Handling Capability - 25 Amperes
8 AMPERES
12
MPM3002 Schertlatic
CASE
I
I
I
1~
11
I
I
I
I
I
12
-,
r----
I
I
I
10
.---------+--~~3
I
I
I
4JJI
I
I
I
_...1
6
KELVIN
STYLE 3:
PIN 1. GATE
2. SOURCE
3. DRAIN
~ GATE
5. MIRROR
6. KELVIN
7. SOURCE
8. MIRROR
9. GATE
10. DRAIN
11. GATE
12. SOURCE
SOURCE
CASE 806-02
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MOTOROLA TMOS POWER MOSFET DATA
3-186
MPM3002
MAXIMUM RATINGS (TJ ~ 25°C unless otherwise noted)
Symbol
Value
Unit
(All Types)
VOSS
100
Volts
(All Types)
VOGR
100
Gate-to-Source Voltage - Continuous
(All Types)
- Non-repetitive (tp '" 50 /Ls)
VGS
VGSM
±20
±4O
Volts
Vpk
Volts
Rating
Orain-to-Source Voltage
Orain-to-Gate Voltage (RGS
~
1Mil)
Orain-to-Mirror Voltage
(Q2 and Q3)
VOM
100
Gate-to-Mirror Voltage
(Q2 and Q3)
VGM
±20
Orain Current -
Continuous
Pulsed
(Q2 and Q3)
10
10M
12
30
-
Continuous
(Q1 and Q4)
-
Pulsed
10
10M
8
25
-
Continuous
Pulsed
(NIP-Channel Combination)
10
10M
8
25
(Q2 and 03)
1M
IMM
13
33
rnA
VISO
2000
Volts
TJ. Tstg
-40 to 150
°c
Sense Current -
Continuous
Pulsed
RMS Isolation Voltage
(Any Pin to Case)
Operating and Storage Temperature Range
Amps
THERMAL CHARACTERISTICS
Power Oissipation - TC ~ 25°C
(Any single device)
(Q1 and Q3 or Q1 and Q4 or Q2 and Q3 or Q2 and Q4 "On")
(Q1 and Q2 and/or Q3 and Q4 "On")
Po
Power Oerating - Oerate above TC ~ 25°C
(Any single device)
(Q1 and Q3 or Q1 and Q4 or Q2 and Q3 or Q2 and Q4 "On")
(Q1 and Q2 andlor 03 and Q4 "On")
1/R8JC
Thermal Resistance -
Junction to Case
Junction-to-Ambient
Maximum Lead Temperature for Soldering Purposes
1/8" from case for 5 seconds
ELECTRICAL CHARACTERISTICS (TJ ~ 25OC. VMS ~
W/"C
0.5
0.5
0.25
Thermal Coupling Coefficient (01 to Q2 or Q4 to Q3)
See Table 1
(Q1 to Q3. Q1 to Q4. Q2 to Q3 or Q2 to Q4)
I
Watts
62.5
62.5
31.25
R(lJC
R8JA
2
35
°CIW
a
0.5
0.01
-
{3
TL
260
°C
a unless otherwise noted)
I
Characteristics
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Orain-to-Source Breakdown Voltage
(VGS ~ O. 10 ~ 0.25 rnA)
(All Oevices)
V(BR)OSS
100
-
-
Vdc
Orain-to-Mirror Breakdown Voltage
(VGS ~ O. 10 ~ 0.25 rnA)
(Q2 and Q3)
V(BR)OMS
100
-
-
Vdc
Zero Gate Voltage Orain Current
(VOS ~ 80 V. VGS ~ 0)
(VOS ~ 80 V. VGS ~ O. TJ ~ 125°C)
(Any Single Oevice)
-
-
Gate-Body Leakage Current - Forward
(VGSF ~ 20 Vdc. VOS ~ 0)
(Any Single Oevice)
IGSSF
-
-
100
Gate Body Leakage Current - Reverse
(VGSR ~ 20 Vdc. VOS ~ 0)
(Any Single Oevice)
IGSSR
-
-
100
Gate Threshold Voltage
(VOS ~ VGS. 10 ~ 1 mAde)
(TJ ~ 12