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Advanced Peripherals

DATA COMMUNICATIONS
LOCAL AREA NETWORKS
UARTS
1988 Edition

Local Area Networks IEEE 802.3
High Speed Serial!
IBM Data Communications
ISDN Components
UARTs
Modems
Transmission Line Drivers & Receivers
Physical Dimensions
iii

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vi

Table of Contents
Alphanumeric Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 1 Local Area Networks IEEE 802.3
DP8390CINS32490C Network Interface Controller ...............................
DP8390C-1 / NS32490C-1 Network Interface Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8391AlNS32491A Serial Network Interface...................................
DP8392A1NS32492A Coaxial Transceiver Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP83910/NS324910 CMOS Serial Network Interface.............................
AN-479 DP839EB Network Evaluation Board. . .. .. .. .. . . .. . .. .. . . . . . . . .. . . . .. . .. .
AN-442 EthernetlCheapernet Physical Layer Made Easy With DP8391 /92 . . . . . . . . . . .
AN-475 DP8390 Network Interface Controller: An Introductory Guide. . . . . . . . . . . . . . . .
AN-498 StarLAN with the DP839EB Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reliability Data Summary for DP8392 ...........................................
Section 2 High Speed Serial/IBM Data Communications
DP8340/NS32440 IBM 3270 Protocol Transmitter/Encoder. . . . . . . . . . . . . . . . . . . . . . . .
DP8341/NS32441 IBM 3270 Protocol Receiver/Decoder..........................
DP8342/NS32442 High-Speed 8-Bit Serial Transmitter/Encoder. .. . ... . . . .. . . .. .. .
DP8343/NS32443 High-Speed 8-Bit Serial Receiver/Decoder. . . . . . . . .. . . . . . .. . .. .
AN-496 the BIPLAN DP8342/DP8343 Biphase Local Area Network. . . . . . . . . . . . . . . . .
DP8344 Biphase Communications Processor-BCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AB-33 Choosing Your RAM for the Biphase Communications Processor . . . . . . . . . . . . .
AB-34 Decoding Bit Fields with the "JRMK" Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . .
AB-35 Receiver Interrupts/ Flags for the DP8344 Biphase Communications Processor .
AN-517 Receiving 5250 Protocol Messages with the Biphase Communications
Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-499 "Interrupts"-A Powerful Tool of the Biphase Communications Processor. . . .
AN-504 DP8344 BCP Stand-Alone Soft-Load System .............................
AN-516 Interfacing the DP8344 to Twinax .......................................
Section 3 ISDN (Intgrated Services Digital Network) Components
Introduction to NSC Basic Access I.C. Set .......................................
TP3401 DASL Digital Adapter for Subscriber Loops. .. .. .. . . . . .. . .. . . . . .. . . . .. .. ..
TP341 0 "U" Interface Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TP3420 ISDN Transceiver "s" Interface Device. ... .. .. ... . . ... ... . .. . .. ... .. . .. .
HPC16083/HPC26083/HPC36083/HPC46083/HPC16003/HPC26003/HPC36003/
HPC46003 High-Performance Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPC16400/HPC36400/HPC46400 High-Performance Microcontrollers with HDLC
Controller .................................................................
ISDN Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ix
1-3
1-54
1-104
1-114
1-122
1-123
1-132
1-141
1-149
1-154
2-3
2-12
2-23
2-33
2-44
2-63
2-179
2-181
2-183
2-184
2-187
2-192
2-203
3-3
3-8
3-9
3-10
3-11
3-12
3-13

Section 4 UARTs (Universal Asynchronous Receiver/Transmitter)
INS8250/INS8250-B Universal Asynchronous Receiver/Transmitter. . . .. . .. . .. ... . .
NS 16450/INS8250AlNS16C450llNS82C50A Universal Asynchronous Receiver /
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS16550A Universal Asynchronous Receiver/Transmitter with FIFOs...............
AN-491 The NS16550A: UART Design and Application Considerations.. . .. . .. .. .. . .
AN-493 A Comparison of the INS8250, NS16450 and NS16550A Series of UARTs . . . .
NSC858 Universal Asynchronous Receiver/Transmitter. .. . .. .. . .. . . .. . .. . .. .. .. ..

4-19
4-36
4-58
4-85
4-93

Section 5 Modems
MM74HC942 300 Baud Modem................................................
MM74HC943 300 Baud Modem................................................
p..AV22 1200/600 bps Full Duplex Modem.......................................
p..A212AT 1200/300 bps Full Duplex Modem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-515 DAA: A Hybrid Design Program for the p..A212A1 AT and p..AV22 . . . . . . . . . . . . .

5-3
5-9
5-16
5-27
5-37

vii

4-3

Table of Contents (Continued)
Section 6 Transmission Line Drivers/Receivers
Transmission Line Drivers/Receivers ...........................................
DS1488 Quad Line Driver ............ , ........ , .. ...... .... .. .. .... .. .. .. . . ....
DS14C88/DS14C89A Quad CMOS Line Driver/Receiver..........................
DS1489/DS1489A Quad Line Receiver.........................................
DS26LS31 C/DS26LS31 M Quad High Speed Differential Line Driver. . . . . . . . . . . . . . . . .
DS26C31C CMOS Quad TRI-STATE Differential Line Driver .................... '" .
DS26LS32C/DS26LS32M/DS26LS32AC/DS26LS33C/DS26LS33M/DS26LS33AC
Quad Differential Line Receivers ...... , ....... '" ..... .. ....... ... .... ... ... .
DS26C32C Quad Differential Line Receiver .. ,. ...... ....... .......... .... ... . ...
DS3486 Quad RS-422, RS-423 Line Receiver....................................
DS34C86 Quad CMOS Differential Line Receiver . .. .. . .. .. .. . .. .. .. . .. .. . .. .. . .. .
DS3587/DS3487 Quad TRI-STATE Line Driver...................................
DS34C87 CMOS Quad TRI-STATE Differential Line Driver.. .. ...... .... .... . .. . .. .
DS1691A1DS3691 (RS-422/RS-423) Line Drivers with TRI-STATE Outputs. ... ... ...
DS1692/DS3692 TRI-STATE Differential Line Drivers.............................
DS3695/DS3695T /DS3696/DS3696T /DS3697 /DS3698 Multipoint RS-485/RS-422
Transceivers/Repeaters ...................................................•
DS75150 Dual Line Driver. .. ...... ..... .. .... ... ... .... . ........ .. ..... .. . ... .
DS75154 Quad Line Receiver. .. .... .. .... . ... . ........ .... .. .. ... ..... .. . .....
DS75176A1DS75176AT Multipoint RS-485/RS-422 Transceivers...................
DS78C120/DS88C120 Dual CMOS Compatible Differential Line Receiver ...........
DS78LS120/DS88LS120 Dual Differential Line Receiver (Noise Filtering and FailSafe) .....................................................................
DS8921 /DS8921 A Differential Line Driver and Receiver Pair . . . . . . . . . . . . . . . . . . . . . . .
DS8922/DS8922A1DS8923/DS8923A TRI-STATE RS-422 Dual Differential Line
Driver and Receiver Pairs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8924 Quad TRI-STATE Differential Line Driver.. .. ...... .... .. .. .... ....... ... .
DS96172/,..,A96172/DS96174/,..,A96174 Quad Differential Line Drivers.............
DS96173/ ,..,A96173/DS96175/ ,..,A96175 Quad Differential Line Receivers. . . . . . . . . . .
DS96177/,..,A96177 Differential Bus Repeater....................................
DS9636A1 ,..,A9636A RS-423 Dual Programmable Slew Rate Line Driver . . . . . . . . . . . . .
DS9637A1,..,A9637A Dual Differential Line Receiver... . ... .... ............ ... .. . ..
DS9638A/ ,..,A9638A RS-422 Dual High-Speed Differential Line Driver . . . . . . . . . . . . . . .
DS9639A1 ,..,A9639A Dual Differential Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS9643/ ,..,A9643 Dual TIL to MOS/CCD Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 7 Physical Dimensions
Physical Dimensions . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors

viii

6-3
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
7-3

Alpha-Numeric Index
AB-33 Choosing Your RAM for the Biphase Communications Processor ........................ 2-179
AB-34 Decoding Bit Fields with the "JRMK" Instruction ....................................... 2-181
AB-35 Receiver Interrupts/Flags for the DP8344 Biphase Communications Processor ............ 2-183
AN-442 EthernetiCheapernet Physical Layer Made Easy With DP8391 /92 ...................... 1-132
AN-475 DP8390 Network Interface Controller: An Introductory Guide ........................... 1-141
AN-479 DP839EB Network Evaluation Board ............................................... 1-123
AN-491 The NS16550A: UART Design and Application Considerations .......................... 4-58
AN-493 A Comparison of the INS8250, NS16450 and NS16550A Series of UARTs ................ 4-85
AN-496 the BIPLAN DP8342/DP8343 Biphase Local Area Network ............................. 2-44
AN-498 StarLAN with the DP839EB Evaluation Board ........................................ 1-149
AN-499 "Interrupts"-A Powerful Tool of the Biphase Communications Processor ............... 2-187
AN-504 DP8344 BCP Stand-Alone Soft-Load System ........................................ 2-192
AN-515 DAA: A Hybrid Design Program for the fA-A212A/AT and fA-AV22 ......................... 5-37
AN-516 Interfacing the DP8344 to Twinax .................................................. 2-203
AN-517 Receiving 5250 Protocol Messages with the Biphase Communications Processor ........ 2-184
DP8340 IBM 3270 Protocol Transmitter/Encoder .............................................. 2-3
DP8341 IBM 3270 Protocol Receiver/Decoder ............................................... 2-12
DP8342 High-Speed 8-Bit Serial Transmitter/Encoder ......................................... 2-23
DP8343 High-Speed 8-Bit Serial Receiver/Decoder ........................................... 2-33
DP8344 Biphase Communications Processor-BCP ............................................ 2-63
DP8390C Network Interface Controller ....................................................... 1-3
DP8390C-1 Network Interface Controller .................................................... 1-54
DP8391A Serial Network Interface ......................................................... 1-104
DP8392A Coaxial Transceiver Interface .................................................... 1-114
DP83910 CMOS Serial Network Interface .................................................. 1-122
DS14C88 Quad CMOS Line Driver/Receiver .................................................. 6-6
DS14C89A Quad CMOS Line Driver/Receiver ................................................. 6-6
DS26C31C CMOS Quad TRI-STATE Differential Line Driver ..................................... 6-9
DS26C32C Quad Differential Line Receiver .................................................. 6-11
DS26LS31 C Quad High Speed Differential Line Driver .......................................... 6-8
DS26LS31 M Quad High Speed Differential Line Driver .......................................... 6-8
DS26LS32AC Quad Differential Line Receiver ................................................ 6-10
DS26LS32C Quad Differential Line Receiver ................................................. 6-10
DS26LS32M Quad Differential Line Receiver ................................................. 6-10
DS26LS33AC Quad Differential Line Receiver ................................................ 6-10
DS26LS33C Quad Differential Line Receiver ................................................. 6-10
DS26LS33M Quad Differential Line Receiver ................................................. 6-10
DS34C86 Quad CMOS Differential Line Receiver ............................................. 6-13
DS34C87 CMOS Quad TRI-STATE Differential Line Driver ..................................... 6-15
DS78C120 Dual CMOS Compatible Differential Line Receiver .................................. 6-22
DS78LS120 Dual Differential Line Receiver (Noise Filtering and Fail-Safe) ....................... 6-23
DS88C120 Dual CMOS Compatible Differential Line Receiver .................................. 6-22
DS88LS120 Dual Differential Line Receiver (Noise Filtering and Fail-Safe) ....................... 6-23
DS1488 Quad Line Driver ................................................................... 6-5
DS1489 Quad Line Receiver ................................................................ 6-7
DS1489A Quad Line Receiver ............................................................... 6-7
DS1691 A (RS-422/RS-423) Line Driver with TRI-STATE Outputs ............................... 6-16
DS1692 TRI-STATE Differential Line Driver .................................................. 6-17
DS3486 Quad RS-422, RS-423 Line Receiver ................................................ 6-12
DS3487 Quad TRI-STATE Line Driver ....................................................... 6-14
DS3587 Quad TRI-STATE Line Driver ....................................................... 6-14

ix

Alpha-Numeric

Index(continUed)

DS3691 (RS-422/RS-423) Line Driver with TRI-STATE Outputs ................................ 6-16
DS3692 TRI-STATE Differential Line Driver .................................................. 6-17
DS3695 Multipoint RS-485/RS-422 Transceiver/Repeater ..................................... 6-18
DS3695T Multipoint RS-485/RS-422 Transceiver/Repeater ................................... 6-18
DS3696 Multipoint RS-485/RS-422 Transceiver/Repeater ..................................... 6-18
DS3696T Multipoint RS-485/RS-422 Transceiver/Repeater ................................... 6-18
DS3697 Multipoint RS-485/RS-422 Transceiver/Repeater ..................................... 6-18
DS3698 Multipoint RS-485/RS-422 Transceiver/Repeater ..................................... 6-18
DS8921 Differential Line Driver and Receiver Pair ............................................. 6-24
DS8921 A Differential Line Driver and Receiver Pair ........................................... 6-24
DS8922 TRI-STATE RS-422 Dual Differential Line Driver and Receiver Pair ...................... 6-25
DS8922A TRI-STATE RS-422 Dual Differential Line Driver and Receiver Pair ..................... 6-25
DS8923 TRI-STATE RS-422 Dual Differential Line Driver and Receiver Pair ...................... 6-25
DS8923A TRI-STATE RS-422 Dual Differential Line Driver and Receiver Pair ..................... 6-25
DS8924 Quad TRI-STATE Differential Line Driver ................ , ............................ 6-26
DS9636A RS-423 Dual Programmable Slew Rate Line Driver ................................... 6-30
DS9637A Dual Differential Line Receiver .................................................... 6-31
DS9638A RS-422 Dual High-Speed Differential Line Driver ..................................... 6-32
DS9639A Dual Differential Line Receiver .................................................... 6-33
DS9643 Dual TTL to MOS/CCD Driver ...................................................... 6-34
DS75150 Dual Line Driver ................................................................. 6-19
DS75154 Quad Line Receiver .... , ......................................................... 6-20
DS75176A Multipoint RS-485/RS-422 Transceiver ........................................... 6-21
DS75176AT Multipoint RS-485/RS-422 Transceiver ........................................... 6-21
DS96172 Quad Differential Line Drivers ..................................................... 6-27
DS96173 Quad Differential Line Receiver .................................................... 6-28
DS96174 Quad Differential Line Drivers ..................................................... 6-27
DS96175 Quad Differential Line Receiver .................................................... 6-28
DS96177 Differential Bus Repeater ......................................................... 6-29
HPC16003 High-Performance Microcontroller ................................................ 3-11
HPC16083 High-Performance Microcontroller ................................................ 3-11
HPC16400 High-Performance Microcontroller with HDLC Controller ............................. 3-12
HPC26003 High-Performance Microcontroller ......................................... , ...... 3-11
HPC26083 High-Performance Microcontroller ................................................ 3-11
HPC36003 High-Performance Microcontroller ................................................ 3-11
HPC36083 High-Performance Microcontroller ................................................ 3-11
HPC36400 High-Performance Microcontroller with HDLC Controller ............................. 3-12
HPC46003 High-Performance Microcontroller ................................................ 3-11
HPC46083 High-Performance Microcontroller .................................. , ............. 3-11
HPC46400 High-Performance Microcontroller with HDLC Controller ............................. 3-12
INS82C50A Universal Asynchronous Receiver/Transmitter .................................... 4-19
INS8250 Universal Asynchronous Receiver/Transmitter ........................................ 4-3
INS8250-B Universal Asynchronous Receiver/Transmitter .............................. , ....... 4-3
INS8250A Universal Asynchronous Receiver/Transmitter ..................................... 4-19
ISDN Definitions ................................................................... ; ...... 3-13
MM74HC942 300 Baud Modem ............................................................. 5-3
MM74HC943 300 Baud Modem ..................................•.......................... 5-9
NS16C450 Universal Asynchronous Receiver/Transmitter ..................................... 4-19
NS16450 Universal Asynchronous Receiver/Transmitter ...................................... 4-19
NS16550A Universal Asynchronous Receiver/Transmitter with FIFOs ........................... 4-36
NS32440 IBM 3270 Protocol Transmitter/Encoder ............................................. 2-3

x

Alpha-Numeric

Index(continued)

NS32441 IBM 3270 Protocol Receiver/Decoder .............................................. 2-12
NS32442 High-Speed 8-Bit Serial Transmitter/Encoder ....................................... 2-23
NS32443 High-Speed 8-Bit Serial Receiver/Decoder .......................................... 2-33
NS32490C Network Interface Controller ...................................................... 1-3
NS32490C-1 Network Interface Controller ................................................... 1-54
NS324910 CMOS Serial Network Interface ................................................. 1-122
NS32491 A Serial Network Interface ....................................................... 1-104
NS32492A Coaxial Transceiver Interface ................................................... 1-114
NSC858 Universal Asynchronous Receiver/Transmitter ....................................... 4-93
Reliability Data Summary for DP8392 ...................................................... 1-154
TP3401 DASL Digital Adapter for Subscriber Loops ............................................ 3-8
TP3410 "U" Interface Transceiver ........................................................... 3-9
TP3420 ISDN Transceiver "S" Interface Device .............................................. 3-10
f-tA212AT 1200/300 bps Full Duplex Modem ................................................. 5-27
f-tA9636A RS-423 Dual Programmable Slew Rate Line Driver ................................... 6-30
f-tA9637A Dual Differential Line Receiver .................................................... 6-31
f-tA9638A RS-422 Dual High-Speed Differential Line Driver ..................................... 6-32
f-tA9639A Dual Differential Line Receiver .................................................... 6-33
f-tA9643 Dual TTL to MOS/CCD Driver ...................................................... 6-34
f-tA96172 Quad Differential Line Drivers ..................................................... 6-27
f-tA96173 Quad Differential Line Receiver .................................................... 6-28
f-tA96174 Quad Differential Line Drivers ..................................................... 6-27
f-tA96175 Quad Differential Line Receiver .................................................... 6-28
f-tA96177 Differential Bus Repeater ......................................................... 6-29
f-tAV22 1200/600 bps Full Duplex Modem ................................................... 5-16

xi

Section 1

Local Area Networks
IEEE 802.3

Section 1 Contents
DP8390CINS32490C Network Interface Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8390C-1/NS32490C-1 Network Interface Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8391 AlNS32491 A Serial Network Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DP8392A/NS32492A Coaxial Transceiver Interface ........... , ...... ,. ... .... ... ... ...
DP8391 0INS32491 0 CMOS Serial Network Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AN-479 DP839EB Network Evaluation Board..........................................
AN-442 EthernetiCheapernet Physical Layer Made Easy With DP8391 192. . . . . . . . . . . . . . . ..
AN-475 DP8390 Network Interface Controller: An Introductory Guide. . . . . . . . . . . . . . . . . . . . ..
AN-498 StarLAN with the DP839EB Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Reliability Data Summary for DP8392 .................................................

1-2

1-3
1-54
1-104
1-114
1-122
1-123
1-132
1-141
1-149
1-154

~National

PRELIMINARY

~ Semiconductor

DP8390C/NS32490C Network Interface Controller
General Description

Table of Contents

The DP8390C/NS32490C Network Interface Controller
(NIC) is a microCMOS VLSI device designed to ease interfacing with CSMAlCD type local area networks including
Ethernet, Thin Ethernet (Cheapernet) and StarLAN. The
NIC implements all Media Access Control (MAC) layer functions for transmission and reception of packets in accordance with the IEEE 802.3 Standard. Unique dual DMA channels and an internal FIFO provide a simple yet efficient
packet management design. To minimize system parts
count and cost, all bus arbitration and memory support logic
are integrated into the NIC.

1.0 SYSTEM DIAGRAM
2.0 BLOCK DIAGRAM
3.0 FUNCTIONAL DESCRIPTION
4.0 TRANSMIT/RECEIVE PACKET ENCAPSULATION/
DECAPSULATION
5.0 PIN DESCRIPTIONS
6.0 DIRECT MEMORY ACCESS CONTROL (DMA)

The NIC is the heart of a three chip set that implements the
complete IEEE 802.3 protocol and node electronics as
shown below. The other two chips are the DP8391 Serial
Network Interface (SNI) and the DP8392A Coaxial Transceiver Interface (CTI).

7.0 PACKET RECEPTION
8.0 PACKET TRANSMISSION
9.0 REMOTE DMA

Features

10.0 INTERNAL REGISTERS

• Compatible with IEEE 802.3/Ethernet II/Thin Ethernet/
StarLAN
• Interfaces with 8-, 16- and 32-bit microprocessor
systems
• Implements simple, versatile buffer management
• Forms integral part of DP8390C, 91, 92 Ethernet/Thin
Ethernet solution
• Requires single 5V supply
• Utilizes low power microCMOS process

11.0 INITIALIZATION PROCEDURES
12.0 LOOPBACK DIAGNOSTICS
13.0 BUS ARBITRATION AND TIMING
14.0 PRELIMINARY ELECTRICAL CHARACTERISTICS
15.0 SWITCHING CHARACTERISTICS
16.0 PHYSICAL DIMENSIONS

• Includes
- Two 16-bit DMA channels
-16-byte internal FIFO with programmable threshold
- Network statistics storage
• Supports physical, multicast, and broadcast address
filtering
• Provides 3 levels of loopback
• Utilizes independent system and network clocks

1.0 System Diagram
IEEE 802.3 Compatible Ethernet/Thin Ethernet Local Area Network Chip Set

TAP
OR

aNC

DP8392
COAX
TRANSCEIVER

INlERFACE

TRANSCEIVER

CABLE

OP8391
SERIAL
NETWORK

INTERFACE

OR

AUI

1.-_ _ _ _ _ _ _ _'" (OPTIONAL) 1.-_ _ _ _ _ _ _ _ _ _ _ _ _-1
TUF/B582-1

1-3

2.0 Block Diagram
COL
CRS
BSCK

BUS ARBITRATION/
HANOSHAKE

r-------+

BREQ, BACK
READY
MRD, MWR

~

.-----,

HANOSHAKE

DI.tA
ADDRESS
REGISTERS
AND
COUNTERS

PROTOCOL
PLA

16
8 OR 16

~o
RXC

8

RXD

U

r

MULTIPLEXED
ADDRESS/DATA BUS

r

E

R

TXC

TL/F/8582-2

FIGURE 1

3.0 Functional Description
(Refer to Figure 1)

the transmit clock generated by the Serial Network Interface
(DP6391). The serial data is also shifted into the CRC generatorI checker. At the beginning of each transmission, the
Preamble and Synch Generator append 62 bits of 1,0 preamble and a 1,1 synch pattern. After the last data byte of
the packet has been serialized the 32-bit FCS field is shifted
directly out of the CRC generator. In the event of a collision
the Preamble and Synch generator is used to generate a
32-bit JAM pattern of all 1's

RECEIVE DESERIALIZER

The Receive Deserializer is activated when the input signal
Carrier Sense is asserted to allow incoming bits to be shifted into the shift register by the receive clock. The serial
receive data is also routed to the CRC generator I checker.
The Receive Deserializer includes a synch detector which
detects the SFD (Start of Frame Delimiter) to establish
where byte boundaries within the serial bit stream are located. After every eight receive clocks, the byte wide data is
transferred to the 16-byte FIFO and the Receive Byte Count
is incremented. The first six bytes after the SFD are
checked for valid comparison by the Address Recognition
Logic. If the Address Recognition Logic does not recognize
the packet, the FIFO is cleared.

ADDRESS RECOGNITION LOGIC

The address recognition logic compares the Destination Address Field (first 6 bytes of the received packet) to the Physical address registers stored in the Address Register Array.
If anyone of the six bytes does not match the pre-programmed physical address, the Protocol Control Logic rejects the packet. All multicast destination addresses are filtered using a hashing technique. (See register description.)
If the multicast address indexes a bit that has been set in
the filter bit array of the Multicast Address Register Array
the packet is accepted, otherwise it is rejected by the Protocol Control Logic. Each destination address is also checked
for all 1's which is the reserved broadcast address.

CRe GENERATOR/CHECKER

During transmission, the CRC logic generates a local CRC
field for the transmitted bit sequence. The CRC encodes all
fields after the synch byte. The CRC is shifted out MSB first
following the last transmit byte. During reception the CRC
logic generates a CRC field from the incoming packet. This
local CRC is serially compared to the incoming CRC appended to the end of the packet by the transmitting node. If
the local and received CRC match, a specific pattern will be
generated and decoded to indicate no data errors. Transmission errors result in a different pattern and are detected,
resulting in rejection of a packet.

FIFO AND FIFO CONTROL LOGIC

The NIC features a 16-byte FIFO. During transmission the
DMA writes data into the FIFO and the Transmit Serializer
reads data from the FIFO and transmits it. During reception
the Receive Deserializer writes data into the FIFO and the
DMA reads data from the FIFO. The FIFO control logic is
used to count the number of bytes in the FIFO so that after
a preset level, the DMA can begin a bus access and writel
read data to/from the FIFO before a FIFO underflowlloverflow occurs.

TRANSMIT SERIALIZER

The Transmit Serializer reads parallel data from the FIFO
and serializes it for transmission. The serializer is clocked by

1-4

C

3.0 Functional Description

"'D
CO

(Continued)

Because the NIC must buffer the Address field of each incoming packet to determine whether the packet matches its
Physical Address Registers or maps to one of its Multicast
Registers, the first local DMA transfer does not occur until 8
bytes have accumulated in the FIFO.
To assure that there is no overwriting of data in the FIFO,
the FIFO logic flags a FIFO overrun as the 13th byte is
written into the FIFO; this effectively shortens the FIFO to
13 bytes. In addition, the FIFO logic operates differently in
Byte Mode than in Word Mode. In Byte Mode, a threshold is
indicated when the n + 1 byte has entered the FIFO; thus,
with an 8-byte threshold, the NIC issues Bus Request
(BREQ) when the 9th byte has entered the FIFO. For Word
Mode, BREQ is not generated until the n + 2 bytes have
entered the FIFO. Thus, with a 4 word threshold (equivalent
to an 8-byte threshold), BREQ is issued when the 10th byte
has entered the FIFO.

two bit pattern. This allows any preceding preamble within
the SFD to be used for phase locking.

PROTOCOL PLA

SOURCE ADDRESS
The source address is the physical address of the node that
sent the packet. Source addresses cannot be multicast or
broadcast addresses. This field is simply passed to buffer
memory.

DMA AND BUFFER CONTROL LOGIC

The DMA and Buffer Control LogiC is used to control two
16-bit DMA channels. During reception, the Local DMA
stores packets in a receive buffer ring, located in buffer
memory. During transmission the Local DMA uses programmed pOinter and length registers to transfer a packet
from local buffer memory to the FIFO. A second DMA channel is used as a slave DMA to transfer data between the
local buffer memory and the host system. The Local DMA
and Remote DMA are internally arbitrated, with the Local
DMA channel having highest priority. Both DMA channels
use a common external bus clock to generate all required
bus timing. External arbitration is performed with a standard
bus request, bus acknowledge handshake protocol.

LENGTH FIELD
The 2-byte length field indicates the number of bytes that
are contained in the data field of the packet. This field is not
interpreted by the NIC.

DATA FIELD
The data field consists of anywhere from 46 to 1500 bytes.
Messages longer than 1500 bytes need to be broken into
multiple packets. Messages shorter than 46 bytes will require appending a pad to bring the data field to the minimum
length of 46 bytes. If the data field is padded, the number of
valid data bytes is indicated in the length field. The NIC
does not strip or append pad bytes for short packets,
or check for oversize packets.

4.0 Transmit/Receive Packet
Encapsulation/Decapsulation
A standard IEEE 802.3 packet consists of the following
fields: preamble, Start of Frame Delimiter (SFD), destination
address, source address, length, data, and Frame Check
Sequence (FCS). The typical format is shown in Figure 2.
The packets are Manchester encoded and decoded by the
DP8391 SNI and transferred serially to the NIC using NRZ
data with a clock. All fields are of fixed length except for the
data field. The NIC generates and appends the preamble,
SFD and FCS field during transmission. The Preamble and
SFD fields are stripped during reception. (The CRC is
passed through to buffer memory during reception.)

FCS FIELD
The Frame Check Sequence (FCS) is a 32-bit CRC field
calculated and appended to a packet during transmission to
allow detection of errors when a packet is received. During
reception, error free packets result in a specific pattern in
the CRC generator. Packets with improper CRC will be rejected. The AUTODIN II (X 32 + X26 + X23 + X22 + X16 +
X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 + 1)
polynomial is used for the CRC calculations.

PREAMBLE AND START OF FRAME DELIMITER (SFD)

PREA~BlE

sm

62b

2b

I

The Manchester encoded alternating 1,0 preamble field is
used by the SNI (DP8391) to acquire bit synchronization
with an incoming packet. When transmitted each packet
contains 62 bits of alternating 1,0 preamble. Some of this
preamble will be lost as the packet travels through the network. The preamble field is stripped by the NIC. Byte alignment is performed with the Start of Frame Delimiter (SFD)
pattern which consists of two consecutive 1'so The NIC
does not treat the SFD pattern as a byte, it detects only the

~~~~Z~ONS
~~~!~I~NS

•

I

STRIPPED
BY HIe

DESTINATION SOURCE

I

••
••

6B

I

6B

LENGTH

I

2B

I

DATA

res

46B-1500B

4B

TRANSFERRED VIA Ot.lA

+-~~-+.+-------~~---------+.+--+

•

APPENDED

TRANSFERRED VIA OMA

BY Nle

8 = BYTES
b=BITS

CALCULATED +
APPENDEO
BY Nle

TL/F/8582-3

FIGURE 2

1-5

C

o
......
z

DESTINATION ADDRESS

The destination address indicates the destination of the
packet on the network and is used to filter unwanted packets from reaching a node. There are three types of address
formats supported by the NIC: physical, multicast, and
broadcast. The physical address is a unique address that
corresponds only to a single node. All phYSical addresses
have an MSB of "0". These addresses are compared to the
internally stored physical address registers. Each bit in the
destination address must match in order for the NIC to accept the packet. Multicast addresses begin with an MSB of
"1". The DP8390C filters multicast addresses using a standard hashing algorithm that maps all multicast addresses
into a 6-bit value. This 6-bit value indexes a 64-bit array that
filters the value. If the address consists of all 1's it is a
broadcast address, indicating that the packet is intended for
all nodes. A promiscuous mode allows reception of all packets: the destination address is not required to match any
filters. Physical, broadcast, multicast, and promiscuous address modes can be selected.

The protocol PLA is responsible for implementing the IEEE
802.3 protocol, including collision recovery with random
backoff. The Protocol PLA also formats packets during
transmission and strips preamble and synch during reception.

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Connection Diagrams

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Plastic Chip Carrier

tn
Z

~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ If IS ~ ~

......

!f
Q

Dual-In-Llne Package

NC

10

NC

NC

NC

A06

INT

A07

RESET

AOB

CO

AD9

RXO

A010

CSR

AOll

RXCK
PCC

GNO

Vee
Vee

68 PIN

GNO
A012

LPBK

A013

TXO

A014

TXCK

A015

23

TXEN

AOSO

24

BREQ

NC

25

NC

NC

26

NC

ADO

RAO

ADl

RAl

AD2

RA2

AD3

RA3

AD4

PRO

ADS

WACK

AD6

INT

A07

RESET

ADS

COL

AD9

RXO

A010

CRS

AOll

RXC

GNO

Vee

A012

LBK

A013

TXO

A014

TXC

A015

TXE

ADSO

BREQ
BACK
PRQ/ADSl
READY

~ ~ ~ I~

Ii I~ I~ I~ I~ SIS

~ I~ ~ ~ ~ ~

PWR
RACK

~

a..

BSCK
TL/F 18582-5
TL/F/8582-4

Order Number DP8390CN or DP8390CV
See NS Package Number N48A or V68A

5.0 Pin Descriptions
BUS INTERFACE PINS
Symbol

DIP Pin No

Function

Description

ADO-AD15

1-12
14-17

IIO,Z

MULTIPLEXED ADDRESS/DATA BUS:
• Register Access, with DMA inactive, CS low and AO< returned from NIC, pins
ADO-AD7 are used to read/write register data. AD8-AD15 float during 110
transfers. SAD, SWR pins are used to select direction of transfer.
• Bus Master with BACK input asserted.
During t1 of memory cycle ADO-AD15 contain address.
During t2, t3, t4 ADO-AD15 contain data (word transfer mode).
During t2, t3, t4 ADO-AD7 contain data, AD8-AD15 contain address
(byte transfer mode).
Direction of transfer is indicated by NIC on MWR, MRD lines.

18

IIO,Z

ADDRESS STROBE 0
• Input with DMA inactive and CS low, latches RAO-RA3 inputs on falling edge.
If high, data present on RAO-RA3 will flow through latch.
• Output when Bus Master, latches address bits (AO-A 15) to external memory
during DMA transfers.

ADSO

1-6

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5.0 Pin Descriptions (Continued)

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CD

o

BUS INTERFACE PINS (Continued)
Symbol
CS

DIP Pin No

Function

Description

19

I

CHIP SELECT: Chip Select places controller in slave mode for !-,P access to
internal registers. Must be valid through data portion of bus cycle. RAO-RA3 are
used to select the internal register. SWR and SRD select direction of data
transfer.

MWR

20

O,l

MASTER WRITE STROBE: Strobe for DMA transfers, active low during write
cycles (t2, t3, tw) to buffer memory. Rising edge coincides with the presence of
valid output data. TRI-STATE® until BACK asserted.

MRD

21

O,l

MASTER READ STROBE: Strobe for DMA transfers, active during read cycles
(t2, t3, tw) to buffer memory. Input data must be valid on rising edge of MRD.
TRI-STATE until BACK asserted.

SWR

22

I

SLAVE WRITE STROBE: Strobe from CPU to write an internal register selected
byRAO-RA3.

SRD

23

I

SLAVE READ STROBE: Strobe from CPU to read an internal register selected
byRAO-RA3.

ACK

24

°

ACKNOWLEDGE: Active low when NIC grants access to CPU. Used to insert
WAIT states to CPU until NIC is synchronized for a register read or write
operation.

45-48

I

REGISTER ADDRESS: These four pins are used to select a register to be read
or written. The state of these inputs is ignored when the NIC is not in slave mode
(CS high).

PRD

44

°

PORT READ: Enables data from external latch onto local bus during a memory
write cycle to local memory (remote write operation). This allows asynchronous
transfer of data from the system memory to local memory.

WACK

43

I

WRITE ACKNOWLEDGE: Issued from system to NIC to indicate that data has
been written to the external latch. The NIC will begin a write cycle to place the
data in local memory.

INT

42

°

INTERRUPT: Indicates that the NIC requires CPU attention after reception
transmission or completion of DMA transfers. The interrupt is cleared by writing
to the ISA. All interrupts are maskable.

RESET

41

I

RESET: Reset is active low and places the NIC in a reset mode immediately, no
packets are transmitted or received by the NIC until STA bit is set. Affects
Command Register, Interrupt Mask Register, Data Configuration Register and
Transmit Configuration Register. The NIC will execute reset within 10 BUSK
cycles.

BREO

31

°

BUS REQUEST: Bus Request is an active high signal used to request the bus for
DMA transfers. This signal is automatically generated when the FIFO needs
servicing.

BACK

30

I

BUS ACKNOWLEDGE: Bus Acknowledge is an active high signal indicating that
the CPU has granted the bus to the NIC. If immediate bus access is desired,
BREO should be tied to BACK. Tying BACK to Vee will result in a deadlock.

PRO,ADS1

29

O,l

PORT REQUEST I ADDRESS STROBE 1
• 32-BIT MODE: If LAS is set in the Data Configuration Register, this line is
programmed as ADS1.lt is used to strobe addresses A16-A31 into external
latches. (A16-A31 are the fixed addresses stored in RSARO, RSAR1.) ADS1
will remain at TRI-STATE until BACK is received .
• 16-BIT MODE: If LAS is not set in the Data Configuration Register, this line is
programmed as PRO and is used for Remote DMA Transfers. In this mode
PRO will be a standard logic output.
NOTE: This line will power up as TRI-STATE until the Data Configuration
Register is programmed.

READY

28

I

READY: This pin is set high to insert wait states during a DMA transfer. The NIC
will sample this signal at t3 during DMA transfers.

RAO-RA3

1-7

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5.0 Pin Descriptions

C')

BUS INTERFACE PINS (Continued)

CD

N

(/)

Z

.......
oo

Symbol

(Continued)

DIP Pin No

Function

PWR

27

a

PORT WRITE: Strobe used to latch data from the NIC into external latch for
transfer to host memory during Remote Read transfers. The rising edge of PWR
coincides with the presence of valid data on the local bus.

RACK

26

I

READ ACKNOWLEDGE: Indicates that the system DMA or host CPU has read
the data placed in the external latch by the NIC. The NIC will begin a read cycle
to update the latch.

BSCK

25

I

This clock is used to establish the period of the DMA memory cycle. Four clock
cycles (t1, t2, t3, t4) are used per DMA cycle. DMA transfers can be extended by
one BSCK increments using the READY input.

CD

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Il..

C

Description

NETWORK INTERFACE PINS

COL

40

I

COLLISION DETECT: This line becomes active when a collision has been
detected on the coaxial cable. During transmission this line is monitored after
preamble and synch have been transmitted. At the end of each transmission this
line is monitored for CD heartbeat.

RXD

39

I

RECEIVE DATA: Serial NRZ data received from the ENDEC, clocked into the
NIC on the rising edge of RXC.

CRS

38

I

CARRIER SENSE: This signal is provided by the ENDEC and indicates that
carrier is present. This signal is active high.

RXC

37

I

RECEIVE CLOCK: Re-synchronized clock from the ENDEC used to clock data
from the ENDEC into the NIC.

LBK

35

a

LOOPBACK: This output is set high when the NIC is programmed to perform a
loopback through the StarLAN ENDEC.

TXD

34

a

TRANSMIT DATA: Serial NRZ Data output to the ENDEC. The data is valid on
the rising edge of TXC.

TXC

33

I

TRANSMIT CLOCK: This clock is used to provide timing for internal operation
and to shift bits out of the transmit serializer. TXC is nominally a 1 MHz clock
provided by the ENDEC.

TXE

32

a

TRANSMIT ENABLE: This output becomes active when the first bit of the
packet is valid on TXD and goes low after the last bit of the packet is clocked out
of TXD. This Signal connects directly to the ENDEC. This signal is active high.

POWER

Vee

36

GND

13

+ 5V DC is required. It is suggested that a decoupling capacitor be connected
between these pins. It is essential to provide a path to ground for the GND pin
with the lowest possible impedance.

6.0 Direct Memory Access Control (DMA)
The DMA capabilities of the NIC greatly simplify use of the
DP8390C in typical configurations. The local DMA channel
transfers data between the FIFO and memory. On transmission, the packet is DMA'd from memory to the FIFO in
bursts. Should a collision occur (up to 15 times), the packet
is retransmitted with no processor intervention. On reception, packets are DMAed from the FIFO to the receive buffer
ring (as explained below).

on a local bus, where the NIC's local DMA channel performs burst transfers between the buffer memory and the
NIC's FIFO. The Remote DMA transfers data between the
buffer memory and the host memory via a bidirectional I/O
port. The Remote DMA provides local addressing capability
and is used as a slave DMA by the host. Host side addressing must be provided by a host DMA or the CPU. The NIC
allows Local and Remote DMA operations to be interleaved.

A remote DMA channel is also provided on the NIC to accomplish transfers between a buffer memory and system
memory. The two DMA channels can alternatively be combined to form a single 32-bit address with 8- or 16-bit data.

SINGLE CHANNEL DMA OPERATION

If desirable, the two DMA channels can be combined to
provide a 32-bit DMA address. The upper 16 bits of the 32bit address are static and are used to point to a 64k byte (or
32k word) page of memory where packets are to be received and transmitted.

DUAL DMA CONFIGURATION

An example configuration using both the local and remote
DMA channels is shown below. Network activity is isolated

1-8

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6.0 Direct Memory Access Control (DMA)

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o

Dual Bus System

o.......
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tn

64K BUFFER
MEMORY

IN

I\)

"'"

MAIN CPU

CD

o

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L...--r--.... REMOTE ADD
HANDSHAKE
SIGNALS
SYSTEM
DMA
CONTROLLER

LOCAL
MICROPROCESSOR

SYSTEM
ADDRESS
SYSTEM DATA

BLOCK DATA
TRANSFERS

SYSTEM
I/O PORT

LOCAL BUS

MAIN
MEMORY

BUS
TL/F/8582-55

32-Bit DMA Operation
DP8390

~

D

7.0 Packet Reception
The Local DMA receive channel uses a Buffer Ring Structure comprised of a series of contiguous fixed length 256
byte (128 wordl buffers for storage of received packets. The
location of the Receive Buffer Ring is programmed in two
registers, a Page Start and a Page Stop Register. Ethernet
packets consist of a distribution of shorter link control packets and longer data packets, the 256 byte buffer length provides a good compromise between short packets and longer packets to most efficiently use memory. In addition these
buffers provide memory resources for storage of back-toback packets in loaded networks. The assignment of buffers

~.-t---.,;;;.;;.;.;---.
DATA

REt.lOT; DMA

LOCAL OMA I-A_DD_R_ES_S..:.{3_2_-B_IT",-l_.
HOST
MEMORY

TL/F/8582-6

NIC Receive Buffer Ring
BUFFER RAM
IUP TO 64 KBYTES)

BUFFER #1
BUFFER #2

BUFFER #3

BUFFER N

TL/F/8582-7

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7.0 Packet Reception

(Continued)

for storing packets is controlled by Buffer Management Logic in the NIC. The Buffer Management Logic provides three
basic functions: linking receive buffers for long packets, recovery of buffers when a packet is rejected, and recirculation of buffer pages that have been read by the host.

Register. An offset of 4 bytes is saved in this first buffer to
allow room for storing receive status corresponding to this
packet.
Received Packet Enters Buffer Pages

At initialization, a portion of the 64k byte (or 32k word) address space is reserved for the receive buffer ring. Two
eight bit registers, the Page Start Address Register
(PSTART) and the Page Stop Address Register (PSTOP)
define the phYSical boundaries of where the buffers reside.
The N IC treats the list of buffers as a logical ring; whenever
the DMA address reaches the Page Stop Address, the DMA
is reset to the Page Start Address.
INITIALIZATION OF THE BUFFER RING
Two static registers and two working registers control the
operation of the Buffer Ring. These are the Page Start Register, Page Stop Register (both described previously), the
Current Page Register and the Boundary Pointer Register.
The Current Page Register points to the first buffer used to
store a packet and is used to restore the DMA for writing
status to the Buffer Ring or for restoring the DMA address in
the event of a Runt packet, a CRC, or Frame Alignment
error. The Boundary Register points to the first packet in the
Ring not yet read by the host. If the local DMA address ever
reaches the Boundary, reception is aborted. The Boundary
Pointer is also used to initialize the Remote DMA for removing a packet and is advanced when a packet is removed. A
simple analogy to remember the function of these registers
is that the Current Page Register acts as a Write Pointer and
the Boundary Pointer acts as a Read Pointer.

TLlF/8582-31

LINKING RECEIVE BUFFER PAGES
If the length of the packet exhausts the first 256 byte buffer,
the DMA performs a forward link to the next buffer to store
the remainder of the packet. For a maximal length packet
the buffer logic will link six buffers to store the entire packet.
Buffers cannot be skipped when linking, a packet will always
be stored in contiguous buffers. Before the next buffer can
be linked, the Buffer Management Logic performs two comparisons. The first comparison tests for equality between
the DMA address of the next buffer and the contents of the
Page Stop Register. If the buffer address equals the Page
Stop Register, the buffer management logic will restore the
DMA to the first buffer in the Receive Buffer Ring value
programmed in the Page Start Address Register. The second comparison tests for equality between the DMA address of the next buffer address and the contents of the
Boundary Pointer Register. If the two values are equal the
reception is aborted. The Boundary Pointer Register can be
used to protect against overwriting any area in the receive
buffer ring that has not yet been read. When linking buffers,
buffer management will never cross this pointer, effectively
avoiding any overwrites. If the buffer address does not
match either the Boundary Pointer or Page Stop Address,
the link to the next buffer is performed.

Note 1: At initialization, the Page Start Register value should be loaded into
both the Current Page Register and the Boundary Pointer Register.
Note 2: The Page Start Register must not be initialized to OOH.

Receive Buffer Ring At Initialization

Linking Buffers
Before the DMA can enter the next contiguous 256 byte
buffer, the address is checked for equality to PSTOP and to
the Boundary Pointer. If neither are reached, the DMA is
allowed to use the next buffer.

TL/F/8582-30

BEGINNING OF RECEPTION
When the first packet begins arriving the N IC begins storing
the packet at the location pointed to by the Current Page

Linking Receive Buffer Pages

1) Check for

~

to PSTOP

2) Check for

~

to Boundary

TL/F/8582-32

1-10

C

"'tI

7.0 Packet Reception (Continued)

co

END OF PACKET OPERATIONS
At the end of the packet the NIC determines whether the
received packet is to be accepted or rejected. It either
branches to a routine to store the Buffer Header or to another routine that recovers the buffers used to store the packet.

Received Packet Aborted if It Hits Boundary Pointer

SUCCESSFUL RECEPTION

TLlF/8582-8

If the Buffer Ring has been filled and the DMA reaches the
Boundary Pointer Address, reception of the incoming packet will be aborted by the NIC. Thus, the packets previously
received and still contained in the Ring will not be destroyed.

Termination of Received Packet-Packet Accepted

In a heavily loaded network environment the local DMA may
be disabled, preventing the NIC from buffering packets from
the network. To guarantee this will not happen, a software
reset must be issued during all Receive Buffer Ring overflows (indicated by the OVW bit in the Interrupt Status Register). The following procedure is required to recover
from a Receiver Buffer Ring Overflow.
1. Issue the STOP mode command (Command Register =
21 H). The NIC may not immediately enter the STOP
mode. If it is currently processing a packet, the NIC will
enter STOP mode only after finishing the packet. The NIC
indicates that it has entered STOP mode by setting the
RST bit in the Interrupt Status Register.

TL/F/8582-10

2. Clear the Remote Byte Counter Registers (RBCRO,
RBCR1). The NIC requires these registers to be cleared
before it sets the RST bit.

BUFFER RECOVERY FOR REJECTED PACKETS
If the packet is a runt packet or contains CRC or Frame
Alignment errors, it is rejected. The buffer management logic resets the DMA back to the first buffer page used to store
the packet (pOinted to by CURR), recovering all buffers that
had been used to store the rejected packet. This operation
will not be performed if the NIC is programmed to accept
either runt packets or packets with CRC or Frame Alignment
errors. The received CRC is always stored in buffer memory
after the last byte of received data for the packet.

Note: If the STP is set when a transmission is in progress, the RST bit may
not be set. In this case, the NIC is guaranteed to be reset after the
longest packet time (1500 bytes ~ 1.2 ms). For the DP8390C (but not
for the DP8390B), the NIC will be reset within 2 microseconds after
the STP bit is set and Loopback mode 1 is programmed.

3. Poll the Interrupt Status Register for the RST bit. When
set, the NIC is in STOP mode.
4. Place the NIC in LOOPBACK (mode 1 or 2) by writing
02H or 04H to the Transmit Configuration Register. This
step is required to properly enable the NIC onto an active
network.
5. Issue the START mode command (Command Register =
22H). The local receive DMA is still inactive since the NIC
is in LOOPBACK.
6. Remove at least one packet from the Receive Buffer
Ring to accommodate additional incoming packets.

Termination of Received Packet-Packet Rejected

7. Take the NIC out of LOOPBACK by programming the
Transmit Configuration Register back to its original value
and resume normal operation.
Note: If the Remote DMA channel is not used, you may eliminate step 6 and
remove packets from the Receive Buffer Ring after step 1. This will
reduce or eliminate the pOlling time incurred in step 3.
TL/F/8582-13

1-11

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Q

If the packet is successfully received as shown, the DMA is
restored to the first buffer used to store the packet (pointed
to by the Current Page Register). The DMA then stores the
Receive Status, a Pointer to where the next packet will be
stored (Buffer 4) and the number of received bytes. Note
that the remaining bytes in the last buffer are discarded and
reception of the next packet begins on the next empty 256byte buffer boundary. The Current Page Register is then
initialized to the next available buffer in the Buffer Ring. (The
location of the next buffer had been previously calculated
and temporarily stored in an internal scratch pad register.)

Buffer Ring Overflow

Co)
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o

7.0 Packet Reception

(Continued)
upper byte count

Error Recovery

=

next page pointer - nexLpkt - 1

if (upper byte count) < 0 then
upper byte count = (PSTOP - nexLpkt)

If the packet is rejected as shown, the DMA is restored by
the NIC by reprogramming the DMA starting address pointed to by the Current Page Register.

+

(next page pointer - PSTART) - 1
if (lower byte count) > 0 fch then

REMOVING PACKETS FROM THE RING

upper byte count = upper byte count

Packets are removed from the ring using the Remote DMA
or an external device. When using the Remote DMA the
Send Packet command can be used. This programs the Remote DMA to automatically remove the received packet
pOinted to by the Boundary Pointer. At the end of the transfer, the NIC moves the Boundary Pointer, freeing additional
buffers for reception. The Boundary Pointer can also be
moved manually by programming the Boundary Register.
Care should be taken to keep the Boundary Pointer at least
one buffer behind the Current Page Pointer.
The following is a suggested method for maintaining the
Receive Buffer Ring pointers.
1. At initialization, set up a software variable (nexLpkt) to
indicate where the next packet will be read. At the beginning of each Remote Read DMA operation, the value of
nexLpkt will be loaded into RSARO and RSAR 1.
2. When initializing the NIC set:
BNDRY = PSTART
CURR = PSTART + 1
nexLpkt = PSTART + 1

+

1

STORAGE FORMAT FOR RECEIVED PACKETS

The following diagrams describe the format for how received packets are placed into memory by the local DMA
channel. These modes are selected in the Data Configuration Register.
Storage Format
AD15

AD8

AD7

ADO

Next Packet
Pointer

Receive
Status

Receive
Byte Count 1

Receive
Byte Count 0

Byte 2

Byte 1

BOS ~ 0, WTS ~ 1 in Data Configuration Register.

This format used with Series 32000 808X type processors.
AD15

3. After a packet is DMAed from the Receive Buffer Ring,
the Next Page Pointer (second byte in NIC buffer header)
is used to update BNDRY and nexLpkt.
nexLpkt = Next Page Pointer
BNDRY = Next Page Pointer - 1
If BNDRY < PSTART then BNDRY = PSTOP - 1
Note the size of the Receive Buffer Ring is reduced by one
256-byte buffer; this will not, however, impede the operation
of the NIC.

AD8

AD7

ADO

Next Packet
Pointer

Receive
Status

Receive
Byte Count 0

Receive
Byte Count 1

Byte 1

Byte 2

BOS ~ 1, WTS ~ 1 in Data Configuration Register.

This format used with 68000 type processors.
Note: The Receive Byte Count ordering remains the same for BOS = 0 or 1.

In StarLAN applications using bus clock frequencies greater
than 4 MHz, the NIC does not update the buffer header
information properly because of the disparity between the
network and bus clock speeds. The lower byte count is copied twice into the third and fourth locations of the buffer
header and the upper byte count is not written. The upper
byte count, however, can be calculated from the current
next page pOinter (second byte in the buffer header) and the
previous next page pointer (stored in memory by the CPU).
The following routine calculates the upper byte count and
allows StarLAN applications to be insensitive to bus clock
speeds. NexLpkt is defined similarly as above.

AD7

ADO
Receive Status
Next Packet
Pointer
Receive Byte
Count 0
Receive Byte
Count 1
Byte 0

1st Received Packet Removed By Remote DMA

Byte 1

BOS ~ 0, WTS ~

°

in Data Configuration Register.

This format used with general 8-bit CPUs.

8.0 Packet Transmission
The Local DMA is also used during transmission of a packet. Three registers control the DMA transfer during transmission, a Transmit Page Start Address Register (TPSR)
and the Transmit Byte Count Registers (TBCRO,1). When
the NIC receives a command to transmit the packet pointed
to by these registers, buffer memory data will be moved into
the FIFO as required during transmission. The NIC will generate and append the preamble, synch and CRC fields.
TL/F/8582-57

1-12

C

8.0 Packet Transmission

."
C»

(Continued)
D8 D7

D15

TRANSMIT PACKET ASSEMBLY

DO

~

The NIC requires a contiguous assembled packet with the
format shown. The transmit byte count includes the Destination Address, Source Address, length Field and Data. It
does not include preamble and CRC. When transmitting
data smaller than 46 bytes, the packet must be padded to a
minimum size of 64 bytes. The programmer is responsible
for adding and stripping pad bytes.

DAI

DAO

.....

DA3

DA2

CJ)

General Transmit Packet Format

SA5

DA4

TIll

T/lO

TX BYTE COUNT
(TBCRO.! )

DESTINATION ADDRESS

6 BYTES

SOURCE ADDRESS

6 BYTES

TYPE LENGTH

2 BYTES

DATA

~

Z

Co)

BOS

DA5

DA4

N

SAl

DAO

C)

SA3

DA2

,co.
CD

o

DATA 1

DATA 0

o. WTS

1 in Data Configuration Register.

~

~

This format is used with Series 32000, 808X type processors.

46 BYTES

----------------PAD (IF DATA < 46 BYTES)

D15

D8 D7

DO

TL/F/8582-58

DAO

DAI

TRANSMISSION
Prior to transmission, the TPSR (Transmit Page Start Register) and TBCRO, TBCR 1 (Transmit Byte Count Registers)
must be initialized. To initiate transmission of the packet the
TXP bit in the Command Register is set. The Transmit
Status Register (TSR) is cleared and the NIC begins to prefetch transmit data from memory (unless the NIC is currently
receiving). If the interframe gap has timed out the NIC will
begin transmission.

DA2

DA3

DA4

DA5

SAO

SAl

SA2

SA3

SA4

SA5

T/lO

TIll

DATA 0

CONDITIONS REQUIRED TO BEGIN TRANSMISSION
In order to transmit a packet, the following three conditions
must be met:

BOS

~

1, WTS

DATA 1
~

1 in Data Configuration Register.

This format is used with 68000 type processors.

1. The Interframe Gap Timer has timed out the first 6.4 J.Ls
of the Interframe Gap (See appendix for Interframe Gap
Flowchart)
2. At least one byte has entered the FIFO. (This indicates
that the burst transfer has been started)

D7

DO
DAO
DAI

3. If the NIC had collided, the backoff timer has expired.
In typical systems the NIC has already prefetchedthe first
burst of bytes before the 6.4 J.Ls timer expires. The time
during which NIC transmits preamble can also be used to
load the FIFO.

DA2
DA3
DA4
DA5

Note: If carrier sense is asserted before a byte has been loaded into the
FIFO, the NIC will become a receiver.

SAO

COLLISION RECOVERY
During transmission, the Buffer Management logic monitors
the transmit circuitry to determine if a collision has occurred.
If a collision is detected, the Buffer Management logic will
reset the FIFO and restore the Transmit DMA pOinters for
retransmission of the packet. The COL bit will be set in the
TSR and the NCR (Number of Collisions Register) will be
incremented. If 15 retransmissions each result in a collision
the transmission will be aborted and the ABT bit in the TSR
will be set.

SAl
SA2
SA3
BOS

~

0, WTS

~

0 in Data Configuration Register.

This format is used with general 8-bit CPUS.
Note: All examples above will result in a transmission of a packet in order of
DAO, DA 1, DA2, DA3 ... bits within each byte will be transmitted least
significant bit first.
DA = Destination Address

Note: NCR reads as zeroes if excessive collisions are encountered.

SA
T/L

TRANSMIT PACKET ASSEMBLY FORMAT
The following diagrams describe the format for how packets
must be assembled prior to transmission for different byte
ordering schemes. The various formats are selected in the
Data Configuration Register.
1-13

~
~

Source Address
Type/Length Field

or-------------------------------------------------------~

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9.0 Remote DMA

C'I

The Remote DMA channel is used to both assemble packets for transmission, and to remove received packets from
the Receive Buffer Ring. It may also be used as a general
purpose slave DMA channel for moving blocks of data or
commands between host memory and local buffer memory.
There are three modes of operation, Remote Write, Remote
Read, or Send Packet.

~

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c

SEND PACKET COMMAND
The Remote DMA channel can be automatically initialized
to transfer a single packet from the Receive Buffer Ring .
The CPU begins this transfer by issuing a "Send Packet"
Command. The DMA will be initialized to the value of the
Boundary POinter Register and the Remote Byte Count
Register pair (RBCRO, RBCR1) will be initialized to the value
of the Receive Byte Count fields found in the Buffer Header
of each packet. After the data is transferred, the Boundary
Pointer is advanced to allow the buffers to be used for new
receive packets. The Remote Read will terminate when the
Byte Count equals zero. The Remote DMA is then prepared
to read the next packet from the Receive Buffer Ring. If the
DMA pointer crosses the Page Stop Register, it is reset to
the Page Start Address. This allows the Remote DMA to
remove packets that have wrapped around to the top of the
Receive Buffer Ring.

Two register pairs are used to control the Remote DMA, a
Remote Start Address (RSARO, RSAR1) and a Remote
Byte Count (RBCRO, RBCR1) register pair. The Start Address Register pair points to the beginning of the block to be
moved while the Byte Count Register pair is used to indicate
the number of bytes to be transferred. Full handshake logic
is provided to move data between local buffer memory and
a bidirectional I/O port.
REMOTE WRITE
A Remote Write transfer is used to move a block of data
from the host into local buffer memory. The Remote DMA
will read data from the I/O port and sequentially write it to
local buffer memory beginning at the Remote Start Address.
The DMA Address will be incremented and the Byte Counter will be decremented after each transfer. The DMA is
terminated when the Remote Byte Count Register reaches
a count of zero.

Note 1: In order for the NIC to correctly execute the Send Packet Com

M

mand, the upper Remote Byte Count Register (ABCR1) must first

be loaded with OFH.
Note 2: The Send Packet command cannot be used with 68000 type proc-

essors.

10.0 Internal Registers
All registers are 8-bit wide and mapped into two pages
which are selected in the Command Register (PSO, PS1).
Pins RAO-RA3 are used to address registers within each
page. Page registers are those registers which are commonly accessed during NIC operation while page 1 registers
are used primarily for initialization. The registers are partitioned to avoid having to perform two write/read cycles to
access commonly used registers.

REMOTE READ

°

A Remote Read transfer is used to move a block of data
from local buffer memory to the host. The Remote DMA will
sequentially read data from the local buffer memory, beginning at the Remote Start Address, and write data to the I/O
port. The DMA Address will be incremented and the Byte
Counter will be decremented after each transfer. The DMA
is terminated when the Remote Byte Count Register reaches zero.

Remote DMA Autoinitialization from Buffer Ring

"0"

1-14

TLlF/8582-59

c

10.0 Internal Registers

;g

(Continued)

Co)

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10.1 REGISTER ADDRESS MAPPING

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z
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TL/F/8S82-60

10.2 REGISTER ADDRESS ASSIGNMENTS
Page 0 Address Assignments (PS1 = 0, PSO
RAO-RA3

RD

= 0)

Page 1 Address Assignments (PS1 = 0, PSO

WR

RAO-RA3

RD

= 1)

WR

OOH

Command (CR)

Command (CR)

OOH

Command (CR)

Command (CR)

01H

Current Local DMA
Address 0 (CLDAO)

Page Start Register
(PSTARD

01H

Physical Address
Register 0 (PARO)

Physical Address
Register 0 (PARO)

02H

Current Local DMA
Address 1 (CLDA1)

Page Stop Register
(PSTOP)

02H

Physical Address
Register 1 (PAR1)

Physical Address
Register 1 (PAR1)

03H

Boundary Pointer
(BNRY)

Boundary Pointer
(BNRY)

03H

Physical Address
Register 2 (PAR2)

Physical Address
Register 2 (PAR2)

04H

Transmit Status
Register (TSR)

Transmit Page Start
Address (TPSR)

04H

Physical Address
Register 3 (PAR3)

Physical Address
Register 3 (PAR3)

05H

Number of Collisions
Register (NCR)

Transmit Byte Count
Register 0 (TBCRO)

05H

Physical Address
Register 4 (PAR4)

Physical Address
Register 4 (PAR4)

06H

FIFO (FIFO)

Transmit Byte Count
Register 1 (TBCR 1)

06H

Physical Address
Register 5 (PAR5)

Physical Address
Register 5 (PAR5)

07H

Interrupt Status
Register (ISR)

Interrupt Status
Register (ISR)

07H

Current Page
Register (CURR)

Current Page
Register (CURR)

OSH

Current Remote DMA Remote Start Address
Address 0 (CRDAO)
Register 0 (RSARO)

OSH

Multicast Address
Register 0 (MARO)

Multicast Address
Register 0 (MARO)

09H

Current Remote DMA Remote Start Address
Address 1 (CRDA1)
Register 1 (RSAR 1)

09H

Multicast Address
Register 1 (MAR1)

Multicast Address
Register 1 (MAR1)

OAH

Reserved

Remote Byte Count
Register 0 (RBCRO)

OAH

Multicast Address
Register 2 (MAR2)

Multicast Address
Register 2 (MAR2)

OBH

Reserved

Remote Byte Count
Register 1 (RBCR1)

OBH

Multicast Address
Register 3 (MAR3)

Multicast Address
Register 3 (MAR3)

OCH

Receive Status
Register (RSR)

Receive Configuration
Register (RCR)

OCH

Multicast Address
Register 4 (MAR4)

Multicast Address
Register 4 (MAR4)

ODH

Tally Counter 0
(Frame Alignment
Errors) (CNTRO)

Transmit Configuration
Register (TCR)

ODH

Multicast Address
Register 5 (MAR5)

Multicast Address
Register 5 (MAR5)

OEH

Tally Counter 1
(CRC Errors)
(CNTR1)

Data Configuration
Register (DCR)

OEH

Multicast Address
Register 6 (MAR6)

Multicast Address
Register 6 (MARS)

OFH

Tally Counter 2
(Missed Packet
Errors) (CNTR2)

Interrupt Mask
Register (IMR)

OFH

Multicast Address
Register 7 (MAR7)

Multicast Address
Register 7 (MAR7)

1·15

o

~

10.0 Internal Registers

~

(Continued)

Page 2 Address Assignments (PS1 = 1, PSO = 0)

en
z
......
oo

RAO-RA3

OOH

Command (CR)

Command (CR)

08H

Reserved

Reserved

co

01H

Page Start Register
(PSTART)

Current local DMA
Address 0 (CLOAO)

09H

Reserved

Reserved

OAH

Reserved

Reserved

02H

Page Stop Register
(PSTOP)

Current local DMA
Address 1 (ClDA 1)

OSH

Reserved

Reserved

Remote Next Packet
Pointer

Remote Next Packet
Pointer

OCH

Receive Configuration
Register (RCR)

Reserved

03H

ODH
Transmit Page Start
Address (TPSR)

Reserved

Transmit Configuration
Register (TCR)

Reserved

04H

OEH
local Next Packet
Pointer

local Nex1 Packet
Pointer

Data Configuration
Register (DCR)

Reserved

05H

Address Counter
(Upper)

Interrupt Mask Register
(IMR)

Reserved

Address Counter
(Upper)

OFH

06H
07H

Address Counter
(lower)

Address Counter
(lower)

0)
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a..
C

RD

RAO-RA3

WR

RD

WR

Note: Page 2 registers should only be accessed for diagnostic purposes.
They should not be modified during normal operation.
Page 3 should never be modified.

1·16

C

10.0 Internal Registers

."
(IC)

(Continued)

Co)

CD

o

10.3 Register Descriptions
COMMAND REGISTER (CR)

OOH (READ/WRITE)

The Command Register is used to initiate transmissions, enable or disable Remote DMA operations and to select register
pages. To issue a command the microprocessor sets the corresponding bit(s) (RD2, RD1, RDO, TXP). Further commands may
be overlapped, but with the following rules: (1) If a transmit command overlaps with a remote DMA operation, bits RDO, RD1,
and RD2 must be maintained for the remote DMA command when setting the TXP bit. Note, if a remote DMA command is re·is·
sued when giving the transmit command, the DMA will complete immediately if the remote byte count register have not been reo
initialized. (2) If a remote DMA operation overlaps a transmission, RDO, RD1, and RD2 may be written with the desired values
and a "0" written to the TXP bit. Writing a "0" to this bit has no effect. (3) A remote write DMA may not overlap remote read
operation or visa versa. Either of these operations must either complete or be aborted before the other operation may start.
Bits PS1, PSO, RD2, and STP may be set any time.
7

I

PS1

5

6

I

PSO

I

RD2

4

I

3

RD1

I

RDO

2

I

1

TXP

I

STA

0

I

STP

I

Bit

Symbol

Description

DO

STP

STOP: Software reset command, takes the controller offline, no packets will be received or
transmitted. Any reception or transmission in progress will continue to completion before
entering the reset state. To exit this state, the STP bit must be reset and the STA bit must be
set high. To perform a software reset, this bit should be set high. The software reset has
executed only when indicated by the RST bit in the ISR being set to a 1. STP powers up
high.

D1

STA

START: This bit is used to activate the NIC after either power up, or when the NIC has been
placed in a reset mode by software command or error. STA powers up low.

D2

TXP

TRANSMIT PACKET: This bit must be set to initiate transmission of a packet. TXP is
internally reset either after the transmission is completed or aborted. This bit should be set
only after the Transmit Byte Count and Transmit Page Start registers have been
programmed.

D3, D4, D5

RDO, RD1, RD2

Note: If the NIC has previously been in start mode and the STP is set, both the STP and STA bits will remain set.

REMOTE DMA COMMAND: These three encoded bits control operation of the Remote DMA
channel. RD2 can be set to abort any Remote DMA command in progress. The Remote Byte
Count Registers should be cleared when a Remote DMA has been aborted. The Remote
Start Addresses are not restored to the starting address if the Remote DMA is aborted.
RD1
RDO
RD2
0
0
0
Not Allowed
0
0
1
Remote Read
0
1
Remote Write (Note 2)
0
0
1
1
Send Packet
1
X
Abort/Complete Remote DMA (Note 1)
X
Note 1: If a remote DMA operation is aborted and the remote byte count has not decremented to zero, PRQ (pin 29,

DIP) will remain high. A read acknowledge (RACK) on a write acknowledge (WACK) will reset PRQ low.
Note 2: For proper operation of the Remote Write DMA, there are two steps which must be performed before using

the Remote Write DMA. The steps are as follows:
i) Write a nonMzero value into RBCRO.

ii) Set bits RD2, RD1, ROO to 0, 0, 1.
iii) Issue the Remote Write DMA Command (RD2, RD1, ROO

D6,D7

PSO,PS1

~

0, 1, 0)

PAGE SELECT: These two encoded bits select which register page is to be accessed with
addresses RAO-3.
PS1
PSO
0
0
Register Page 0
0
1
Register Page 1
1
0
Register Page 2
1
1
Reserved

1·17

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.....
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(J)
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ct
o
o

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~

10.0 Internal Registers (Continued)

('I)

10.3 Register Descriptions (Continued)

CD

N

en

z

INTERRUPT STATUS REGISTER (ISR)

CD

This register is accessed by the host processor to determine the cause of an interrupt. Any interrupt can be masked in the
Interrupt Mask Register (IMR). Individual interrupt bits are cleared by writing a "1" into the corresponding bit of the ISR. The INT
signal is active as long as any unmasked signal is set, and will not go low until all unmasked bits in this register have been
cleared. The ISR must be cleared after power up by writing it with all 1'so

......
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CO

a..

c

7

07H (READ/WRITE)

6

5

4

3

2

1

0

I RST I ROC I CNT IOVW I TXE I RXE I PTX I PRX I
Bit

Symbol

00

PRX

Description
PACKET RECEIVED: Indicates packet received with no errors.

01

PTX

PACKET TRANSMITTED: Indicates packet transmitted with no errors.

02

RXE

RECEIVE ERROR: Indicates that a packet was received with one or more of the
following errors:
-CRC Error
-Frame Alignment Error
-FIFO Overrun
-Missed Packet

03

TXE

TRANSMIT ERROR: Set when packet transmitted with one or more of the
following errors:
-Excessive Collisions
-FIFO Underrun

04

OVW

OVERWRITE WARNING: Set when receive buffer ring storage resources have
been exhausted. (Local OMA has reached Boundary POinter).

05

CNT

COUNTER OVERFLOW: Set when MSB of one or more of the Network Tally
Counters has been set.

06

ROC

REMOTE DMA COMPLETE: Set when Remote OMA operation has been
completed.

07

RST

RESET STATUS: Set when N IC enters reset state and cleared when a Start
Command is issued to the CR. This bit is also set when a Receive Buffer Ring
overflow occurs and is cleared when one or more packets have been removed
from the ring. Writing to this bit has no effect.
NOTE: This bit does not generate an interrupt, it is merely a status indicator.

1·18

10.0 Internal Registers (Continued)
10.3 Register Descriptions (Continued)
INTERRUPT MASK REGISTER (IMR)

OFH(WRITE)

The Interrupt Mask Register is used to mask interrupts. Each interrupt mask bit corresponds to a bit in the Interrupt Status
Register (ISR). If an interrupt mask bit is set an interrupt will be issued whenever the corresponding bit in the ISR is set. If any bit
in the IMR is set low, an interrupt will not occur when the bit in the ISR is set. The IMR powers up all zeroes.

7
I

-

6

5

4

3

2

1

0

IRDCElcNTEloVVVEITXEEIRXEElpTXElpRXEI

Bit

Symbol

DO

PRXE

PACKET RECEIVED INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when packet received.

Description

01

PTXE

PACKET TRANSMITTED INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when packet is transmitted.

02

RXEE

RECEIVE ERROR INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when packet received with error.

03

TXEE

TRANSMIT ERROR INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when packet transmission results in error.

04

OVVVE

OVERWRITE WARNING INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when Buffer Management Logic lacks sufficient buffers to
store incoming packet.

05

CNTE

COUNTER OVERFLOW INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when MSB of one or more of the Network Statistics
counters has been set.

06

RDCE

DMA COMPLETE INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when Remote DMA transfer has been completed.

07

reserved

reserved

1-19

10.0 Internal Registers

(Continued)

10.3 Register Descriptions (Continued)
DATA CONFIGURATION REGISTER (DCR)

OEH(WRITE)

This Register is used to program the NIC for 8- or 16-bit memory interface, select byte ordering in 16-bit applications and
establish FIFO threshholds. The DCR must be Initialized prior to loading the Remote Byte Count Registers. LAS is set on
power up.
7

6

5

4

2

3

1

0

I - I FT1 I FTO I ARM I LS I LAS I BOS I WTsl
Bit

Symbol

DO

WTS

Description
WORD TRANSFER SELECT
0: Selects byte-wide DMA transfers
1: Selects word-wide DMA transfers
; WTS establishes byte or word transfers
for both Remote and Local DMA transfers
Note: When word-wide mode is selected, up to 32k words are addressable; AO remains low.

D1

BOS

BYTE ORDER SELECT
0: MS byte placed on AD15-AD8 and LS byte on AD7 -ADO. (32000, 8086)
1: MS byte placed on AD? -ADO and LS byte on AD15-AD8. (68000)

D2

LAS

LONG ADDRESS SELECT
0: Dual 16-bit DMA mode
1: Single 32-bit DMA mode

; Ignored when WTS is low

; When LAS is high, the contents of the Remote DMA registers RSARO,1 are issued as A 16-A31
Power up high,
D3

LS

LOOPBACK SELECT
0: Loopback mode selected. Bits D1 , D2 of the TCR must also be programmed for Loopback
operation.
1: Normal Operation.

D4

AR

AUTO-INITIALIZE REMOTE
0: Send Command not executed, all packets removed from Buffer Ring under program control.
1: Send Command executed, Remote DMA auto-initialized to remove packets from Buffer Ring.

D5, D6

FTO,FT1

Note: Send Command cannot be used with 68000 type processors.

FIFO THRESH HOLD SELECT: Encoded FIFO thresh hold, Establishes point at which bus is
requested when filling or emptying the FIFO. During reception, the FIFO threshold indicates the
number of bytes (or words) the FIFO has filled serially from the network before bus request
(BREQ) is asserted.
Note: FIFO threshold setting determines the DMA burst length.
RECEIVE THRESHOLDS
Byte Wide
FT1
FTO
Word Wide
1 Word
2 Bytes
0
0
4 Bytes
0
1
2 Words
0
4 Words
8 Bytes
1
12 Bytes
1
1
6 Words
During transmission, the FIFO threshold indicates the numer of bytes (or words) the FIFO has
filled from the Local DMA before BREQ is asserted, Thus, the transmission threshold is 16 bytes
less the receive threshold.

1-20

10.0 Internal Registers

(Continued)

10.3 Register Descriptions (Continued)
TRANSMIT CONFIGURATION REGISTER (TCR)

ODH(WRITE)

The transmit configuration establishes the actions of the transmitter section of the NIC during transmission of a packet on the
network. LB1 and LBO which select loopback mode power up as O.

I

-

5

6

7
I

-

I

-

4

3

2

1

0

IOFSTI ATD I LB1 I LBO I CRC I

Bit

Symbol

DO

CRC

D1, D2

LBO.LB1

ENCODED LOOPBACK CONTROL: These encoded configuration bits set the type of loopback
that is to be performed. Note that loopback in mode 2 sets the LPBK pin high. this places the SNI
in loopback mode and that D3 of the DCR must be set to zero for loopback operation.
LB1
LB2
Mode 0
Normal Operation (LPBK = 0)
0
0
Mode 1
0
1
Internal Loopback (LPBK = 0)
Mode 2
1
0
External Loopback (LPBK = 1)
Mode 3
1
1
External Loopback (LPBK = 0)

D3

ATD

AUTO TRANSMIT DISABLE: This bit allows another station to disable the NIC's transmitter by
transmission of a particular multicast packet. The transmitter can be re-enabled by resetting this
bit or by reception of a second particular multicast packet.
0: Normal Operation
1: Reception of multicast address hashing to bit 62 disables transmitter. reception of multicast
address hashing to bit 63 enables transmitter.

D4

OFST

COLLISION OFFSET ENABLE: This bit modifies the backoff algorithm to allow prioritization of
nodes.
0: Backoff Logic implements normal algorithm.
1: Forces Backoff algorithm modification to 0 to 2min (3 + n.1 0) slot times for first three COllisions,
then follows standard backoff. (For first three collisions station has higher average backoff delay
making a low priority mode.)

D5

reserved

D6

reserved

reserved

D7

reserved

reserved

Description
INHIBITCRC
0: CRC appended by transmitter
1: CRC inhibited by transmitter
; In loop back mode CRC can be enabled or disabled to test the CRC logic.

reserved

1-21

10.0 Internal Registers (Continued)
10.3 Register Descriptions (Continued)
TRANSMIT STATUS REGISTER (TSR)
04H(READ)
This register records events that occur on the media during transmission of a packet. It is cleared when the next transmission is
initiated by the host. All bits remain low unless the event that corresponds to a particular bit occurs during transmission. Each
transmission should be followed by a read of this register. The contents of this register are not specified until after the first
transmission.
7

6

Bit

SymbOl

DO

PTX

5

4

3

2

FU

CRS

ABT

COL

1

0

I I I I I I- I I

loWC COH

PTX

Description
PACKET TRANSMITTED: Indicates transmission without error. (No excessive
collisions or FIFO underrun) (ABT = "0", FU = "0").

01

reserved

02

COL

TRANSMIT COLLIDED: Indicates that the transmission collided at least once
with another station on the network. The number of collisions is recorded in the
Number of Collisions Registers (NCR).

03

ABT

TRANSMIT ABORTED: Indicates the NIC aborted transmission because of
excessive collisions. (Total number of transmissions including original
transmission attempt equals 16).

04

CRS

CARRIER SENSE LOST: This bit is set when carrier is lost during transmission
of the packet. Carrier Sense is monitored from the end of Preamble/Synch until
TXEN is dropped. Transmission is not aborted on loss of carrier.

05

FU

06

COH

CD HEARTBEAT: Failure of the transceiver to transmit a collision Signal after
transmission of a packet will set this bit. The Collision Detect (CD) heartbeat
signal must commence during the first 6.4 pos of the Interframe Gap following a
transmission. In certain collisions, the CD Heartbeat bit will be set even though
the transceiver is not performing the CD heartbeat test.

07

OWC

OUT OF WINDOW COLLISION: Indicates that a collision occurred after a slot
time (51.2 pos). Transmissions rescheduled as in normal collisions.

reserved

FIFO UNDERRUN: If the NIC cannot gain access of the bus before the FIFO
empties, this bit is set. Transmission of the packet will be aborted.

1·22

C

"tJ

10.0 Internal Registers (Continued)

C»
Co)

CD

o

10.3 Register Descriptions (Continued)
OCH(WRITE)

RECEIVE CONFIGURATION REGISTER (RCR)

This register determines operation of the NIC during reception of a packet and is used to program what types of packets to
accept.
5
4
3
2
1
0
7
6

I- I- I

MON

I

PRO

I

AM

I

AB

I

AR

I

SEP

I

Bit

Symbol

Description

DO

SEP

SAVE ERRORED PACKETS
0: Packets with receive errors are rejected.
1: Packets with receive errors are accepted. Receive errors are CRC and Frame
Alignment errors.

01

AR

ACCEPT RUNT PACKETS: This bit allows the receiver to accept packets that
are smaller than 64 bytes. The packet must be at least 8 bytes long to be
accepted as a runt.
0: Packets with fewer than 64 bytes rejected.
1: Packets with fewer than 64 bytes accepted.

02

AB

ACCEPT BROADCAST: Enables the receiver to accept a packet with an all1's
destination address.
0: Packets with broadcast destination address rejected.
1: Packets with broadcast destination address accepted.

03

AM

ACCEPT MULTICAST: Enables the receiver to accept a packet with a multicast
address, all multicast addresses must pass the hashing array.
0: Packets with multicast destination address not checked.
1: Packets with multicast destination address checked.

04

PRO

PROMISCUOUS PHYSICAL: Enables the receiver to accept all packets with a
physical address.
0: Physical address of node must match the station address programmed in
PARO-PAR5.
1: All packets with physical addresses accepted.

05

MON

MONITOR MODE: Enables the receiver to check addresses and CRC on
incoming packets without buffering to memory. The Missed Packet Tally counter
will be incremented for each recognized packet.
0: Packets buffered to memory.
1: Packets checked for address match, good CRC and Frame Alignment but not
buffered to memory.

06

reserved

reserved

07

reserved

reserved

Note: 02 and 03 are "OR'd" together, i.e., if 02 and 03 are set the NIC will accept broadcast and multicast addresses as well as its own physical address. To
establish full promiscuous mode, bits 02. 03, and 04 should be set. In addition the multicast hashing array must be set to all 1's in order to accept all multicast
addresses.

1-23

o......
z
(f)
Co)

N

;co.
CD

o

o

•

i

10.0 Internal Registers (Continued)
10.3 Register Descriptions (Continued)
RECEIVE STATUS REGISTER (RSR)

OCH(READ)

This register records status of the received packet, including information on errors and the type of address match, either
physical or multicast. The contents of this register are written to buffer memory by the DMA after reception of a good packet. If
packets with errors are to be saved the receive status is written to memory at the head of the erroneous packet if an erroneous
packet is received. If packets with errors are to be rejected the RSR will not be written to memory. The contents will be cleared
when the next packet arrives. CRC errors, Frame Alignment errors and missed packets are counted internally by the NIC which
relinquishes the Host from reading the RSR in real time to record errors for Network Management Functions. The contents of
this register are not specified until after the first reception.

7

6

5

4

3

2

1

0

IDFR I DIS I PHY I MPA I Fa I FAE I CRC I PRX I
Description

Bit

Symbol

DO

PRX

PACKET RECEIVED INTACT: Indicates packet received without error. (Bits
CRC, FAE, Fa, and MPA are zero for the received packet.)

D1

CRC

CRC ERROR: Indicates packet received with CRC error. Increments Tally
Counter (CNTR1). This bit will also be set for Frame Alignment errors.

D2

FAE

FRAME ALIGNMENT ERROR: Indicates that the incoming packet did not end
on a byte boundary and the CRC did not match at last byte boundary. Increments
Tally Counter (CNTRO).

D3

Fa

FIFO OVERRUN: This bit is set when the FIFO is not serviced causing overflow
during reception. Reception of the packet will be aborted.

D4

MPA

MISSED PACKET: Set when packet intended for node cannot be accepted by
NIC because of a lack of receive buffers or if the controller is in monitor mode
and did not buffer the packet to memory. Increments Tally Counter (CNTR2).

D5

PHY

PHYSICAL/MULTICAST ADDRESS: Indicates whether received packet had a
physical or multicast address type.
0: Physical Address Match
1: Multicast/Broadcast Address Match

D6

DIS

RECEIVER DISABLED: Set when receiver disabled by entering Monitor mode.
Reset when receiver is re-enabled when exiting Monitor mode.

D7

DFR

DEFERRING: Set when CRS or COL inputs are active. If the transceiver has
asserted the CD line as a result of the jabber, this bit will stay set indicating the
jabber condition.

Note: Following coding applies to CRC and FAE bits
FAECRC
Type of Error
0
0 No Error (Good CRC and <6 Dribble Bits)
0
1 CRCError
1 0 Illegal, will not occur
1 1 Frame Alignment Error andCRC Error

1-24

.-----------------------------------------------------------------------,0
10.0 Internal Registers

DMA Registers

;g
~
o

LOCAL DMA TRANSMIT REGISTERS
15
817
0

z
~
N

(Continued)

10.4 DMA REGISTERS

(TPSR)

.....
~

PAGE START

(TBCRO ,1)

TRANSMIT BYTE COUNT

I

LOCAL DMA RECEIVE REGISTERS
15
0
817
(PSTART)

PAGE START

(PSTOP)

PAGE STOP

(CURR)

CURRENT

(BRNY)
NOT
READABLE
(CLDAO ,1)

BOUNDARY

I

RECEIVE BYTE COUNT

I

(RSARO ,I)

START ADDRESS

(RBCRO ,I)

BYTE COUNT

I

I+-

CURRENT LOCAL DMA ADDRESS

REMOTE DMA REGISTERS
15
817

(CRADO ,I)

~

LOCAL
DMA
CHANNEL

0

I
I

CURRENT REMOTE DMA ADDRESS

_r

REMOTE
DMA
CHANNEL

I~L...

__"'"
TL/F/8582-61

The DMA Registers are partitioned into three groups; Transmit, Receive and Remote DMA Registers. The Transmit registers are used to initialize the Local DMA Channel for transmission of packets while the Receive Registers are used to
initialize the Local DMA Channel for packet Reception. The
Page Stop, Page Start, Current and Boundary Registers are
used by the Buffer Management Logic to supervise the Receive Buffer Ring. The Remote DMA Registers are used to
initialize the Remote DMA.

bytes in the source, destination, length and data fields. The
maximum number of transmit bytes allowed is 64k bytes.
The NIC will not truncate transmissions longer than 1500
bytes. The bit aSSignment is shown below:
7
6
5
4
3
2
1
0
TBCR11 L151 L141 L131 L121 L11 I L10 I L9 I LS I
7

6

5

4

3

o

2

~~~ul~I~I~I~I~IL1I~1

Note: In the figure above, registers are shown as 8 or 16 bits wide. Although
some registers are 16 bit internal registers, all registers are accessed
M

10.6 LOCAL DMA RECEIVE REGISTERS

as a-bit registers. Thus the 16-bit Transmit Byte Count Register is
broken into two 8·bit registers. TBCRO and TBCR1. Also TPSR,
PSTART, PSTOP, CURR and BNRY only check or control the upper 8

PAGE START STOP REGISTERS (PSTART, PSTOP)
The Page Start and Page Stop Registers program the starting and stopping address of the Receive Buffer Ring. Since
the NIC uses fixed 256-byte buffers aligned on page boundaries only the upper eight bits of the start and stop address
are specified.
PSTART,PSTOP bit assignment
7
6
5
4
3
2
1
0

bits of address information on the bus. Thus they are shifted to positions 15-8 in the diagram above.

10.5 TRANSMIT DMA REGISTERS
TRANSMIT PAGE START REGISTER (TPSR)

This register points to the assembled packet to be transmit·
ted. Only the eight higher order addresses are specified
since all transmit packets are assembled on 256-byte page
boundaries. The bit assignment is shown below. The values
placed in bits D7-DO will be used to initialize the higher
order address (AS-A 15) of the Local DMA for transmission.
The lower order bits (A7-AO) are initialized to zero.

:~~~:T'I

6

5

4

3

2

1

I A9

I AS

I

This register is used to prevent overflow of the Receive
Buffer Ring. Buffer management compares the contents of
this register to the next buffer address when linking buffers
together. lithe contents of this register match the next buff·
er address the Local DMA operation is aborted.
7
6
5
4
321
0

Bit Assignment

7

A151 A141 A131 A121 All I Al0

BOUNDARY (BNRY) REGISTER

0

TPSRI A151 A141 A131 A121 A11 I A10 I A9 I AS I
(A7-AO Initialized to zero)

BNRyl A151 A141 A131 A121 A11 I A10 I A9 I AS I

TRANSMIT BYTE COUNT REGISTER 0,1 (TBCRO, TBCR1)
These two registers indicate the length of the packet to be
transmitted in bytes. The count must include the number of
1-25

o

g
"II'
N
C')

U)

Z

(3
o
a»
C')

CO
D-

C

10.0 Internal Registers

(Continued)

CURRENT PAGE REGISTER (CURR)

10.8 PHYSICAL ADDRESS REGISTERS (PARO-PAR5)
The physical address registers are used to compare the
destination address of incoming packets for rejecting or accepting packets. Comparisons are performed on a bytewide basis. The bit assignment shown below relates the sequence in PARO-PAR5 to the bit sequence of the received
packet.
07
06
05
04
03
02
01
DO

This register is used internally by the Buffer Management
Logic as a backup register for reception. CURR contains the
address of the first buffer to be used for a packet reception
and is used to restore DMA pOinters in the event of receive
errors. This register is initialized to the same value as
PSTART and should not be written to again unless the controller is Reset.

7

6

5

4

3

2

0

CURR\ At51 At41 At31 At21 Att I AtO I A9

CURRENT LOCAL DMA REGISTER O,t (CLDAO,t)
These two registers can be accessed to determine the current Local DMA Address.

7

6

5

4

3

2

CLDAt\ At51 At41 At31 At21 Att I AtO I A9

7

6

5

RSARtl At51 At41 At31 At21 Att I AtO I A9

5

4

3

2

4

DA2

PAR4 DA39 DA38 DA37 DA36 DA35 DA34 DA33 DA32

A8

PAR5 DA47 DA46 DA45 DA44 DA43 DA42 DA4t DA40

Destination Address

AO

321

Source

IP/SIDAOIDAtIDA2IDA31 ...... I DA461DA47ISAOI· ..
Note:
P/S = Preamble, Synch
DAO = Physical/Multicast Bit

10.9 MULTICAST ADDRESS REGISTERS (MARO-MAR7)
The multicast address registers provide filtering of multicast
addresses hashed by the CRC logic. All destination addresses are fed through the CRC logic and as the last bit of
the destination address enters the CRC, the 6 most significant bits of the CRC generator are latched. These 6 bits are
then decoded by a t of 64 decode to index a unique filter bit
(FBO-63) in the multicast address registers. If the filter bit
selected is set, the multicast packet is accepted. The system designer would use a program to determine which filter
bits to set in the multicast registers. All multicast filter bits
that correspond to multicast address accepted by the node
are then set to one. To accept all multicast packets all of
the registers are set to all ones.

A8

AO

RBCRtlBCt51BCt41BCt31BCt21BCttlBCtOi BC91 BC81

5

DA3

PAR3 DA3t DA30 DA29 DA28 DA27 DA26 DA25 DA24

6.4.3.2 REMOTE BYTE COUNT REGISTERS (RBCRO,t)
765
432
1
0

6

DA8

DA4

0

0

RSAROI A7 I A6 I A5 I A4 I A3 I A2 I At

7

PARt DAt5 DAt4 DAt3 DAt2 DAtt DAtO DA9

DA5

PAR2 DA23 DA22 DA2t DA20 DAt9 DAt8 DAt7 DAt6

to.7 REMOTE DMA REGISTERS
REMOTE START ADDRESS REGISTERS (RSARO,t)
Remote DMA operations are programmed via the Remote
Start Address (RSARO,t) and Remote Byte Count
(RBCRO,t) registers. The Remote Start Address is used to
point to the start of the block of data to be transferred and
the Remote Byte Count is used to indicate the length of the
block (in bytes).
7
6
5
4
320

6

DAO

DA6

0

432

CLDAOI A7 I A6 I A5 I A4 I A3 I A2 I At

7

DAt

PARO DA7

A8

Note: Although the hashing algorithm does not guarantee perfect filtering of
multicast address, it will perfectly filter up to 64 multicast addresses if
these addresses are chosen to map into unique locations in the multicast filter.

0

RBCROI BC71 BC61BC51 BC41 BC31 BC21 BCt I Bcol
Note:
RSARO programs the start address bits AO-A7.
RSARI programs the start address bits AS-A 15.
Address incremented by two for word transfers, and by one for byte trans·

ters.
Byte Count decremented by two for word transfers and by one for byte
transfers.
RBGRO programs LSB byte count.
RBGRI programs MSB byte count.

CURRENT REMOTE DMA ADDRESS (CRDAO, CRDAt)
The Current Remote DMA Registers contain the current address of the Remote DMA. The bit assignment is shown
below:
7
0
4
3
2
6
5
CRDAtl At51 At41 At31 At21 Att I AtO I A9
7
CRDAOI A7

6

5

4

3

2

A6

A5

A4

A3

A2

SELECTED BIT
" - - - - - ..0" = REJECT "I" = ACCEPT

A8

TLlF/8582-62

0
At

AO

t-26

10.0 Internal Registers (Continued)
07

06

05

04

03

02

01

DO

NUMBER OF COLLISIONS (NCR)

FB6

FBS

FB4

FB3

FB2

FB1

FBO

MAR1 FB1S FB14 FB13 FB12 FB11 FB10 FB9

FB8

This register contains the number of collisions a node experiences when attempting to transmit a packet. If no collisions are experienced during a transmission attempt, the
COL bit of the TSR will not be set and the contents of NCR
will be zero. If there are excessive collisions, the ABT bit in
the TSR will be set and the contents of NCR will be zero.
The NCR is cleared after the TXP bit in the CR is set.

MARO FB7

MAR2 FB23 FB22 FB21 FB20 FB19 FB18 FB17 FB16
MAR3 FB31 FB30 FB29 FB28 FB27 FB26 FB2S FB24
MAR4 FB39 FB38 FB37 FB36 FB35 FB34 FB33 FB32

7

MARS FB47 FB46 FB4S FB44 FB43 FB42 FB41 FB40
NCR

MAR6 FBSS FBS4 FBS3 FBS2 FBS1 FBSO FB49 FB48

I-

6
I -

5
I -

4
I -

3

2

1

0

I NC31 NC21 NC1 I NCO I

MAR7 FB63 FB62 FB61 FB60 FB59 FBS8 FBS7 FB56

11.0 Initialization Procedures

If address Y is found to hash to the value 32 (20H), then
FB32 in MAR4 should be initialized to "1". This will cause
the NIC to accept any multicast packet with the address Y.

The NIC must be initialized prior to transmission or reception of packets from the network. Power on reset is applied
to the NIC's reset pin. This clears/sets the following bits:

NETWORK TALLY COUNTERS
Three 8-bit counters are provided for monitoring the number
of CRC errors, Frame Alignment Errors and Missed Packets. The maximum count reached by any counter is 192
(COH). These registers will be cleared when read by the
CPU. The count is recorded in binary in CTO-CT7 of each
Tally Register.

6

5

4

3

2

1

Transmit Config. (TCR)

4

3

2

1

0

5

4

3

2

1

2) Initialize Data Configuration Register (OCR)
3) Clear Remote Byte Count Registers (RBCRO, RBCR1)

0

4) Initialize Receive Configuration Register (RCR)
S) Place the NIC in LOOPBACK mode 1 or 2 (Transmit
Configuration Register = 02H or 04H)
6) Initialize Receive Buffer Ring: Boundary Pointer
(BNORY), Page Start (PSTART), and Page Stop
(PSTOP)
7) Clear Interrupt Status Register (ISR) by writing OFFh to
it
8) Initialize Interrupt Mask Register (IMR)

0

CNTR21 cnl CT61 CTsl CT41 CT31 CT21 CT1 I CTO I

9) Program Command Register for page 1 (Command
Register = 61 H)
i)lnitialize Physical Address Registers (PARO-PARS)

FIFO
This is an eight bit register that allows the CPU to examine
the contents of the FIFO after loopback. The FIFO will contain the last 8 data bytes transmitted in the loopback packet
Sequential reads from the FIFO will advance a pOinter in the
FIFO and allow reading of all 8 bytes.

7

6

5

4

3

2

1

LAS
LB1,LBO

1) Program Command Register for Page 0 (Command
Register = 21 H)

Frames Lost Tally Register (CNTR2)
This counter is incremented if a packet cannot be received
due to lack of buffer resources. In monitor mode, this counter will count the number of packets that pass the address
recognition logic.

6

All Bits

Initialization Sequence
The following Initialization procedure is mandatory.

CNTR11 CT71 CT61 CTsl CT41 CT31 CT21 CT1 I CTO I

7

RST

The NIC remains in its reset state until a Start Command is
issued. This guarantees that no packets are transmitted or
received and that the NIC remains a bus slave until all appropriate internal registers have been programmed. After
initialization the STP bit of the command register is reset
and packets may be received and transmitted.

This counter is incremented every time a packet is received
with a CRC error. The packet must first be recognized by
the address recognition logic. The counter is cleared after it
is read by the processor.

5

R02, STP

Data Control (OCR)

CRC Error Tally (CNTR1)

6

Set Bits

TXP,STA

Interrupt Mask (IMR)

CNTROI CT7 I CT61 CTsl CT41 CT31 CT21 CT1 I CTO I

7

Reset Bits

Interrupt Status (ISR)

Frame Alignment Error Tally (CNTRO)
This counter is incremented every time a packet is received
with a Frame Alignment Error. The packet must have been
recognized by the address recognition logiC. The counter is
cleared after it is read by the processor.

7

Register
Command Register (CR)

ii)lnitialize Multicast Address Registers (MARO-MAR7)
iii)lnitialize CURRent pOinter
10) Put NIC in START mode (Command Register = 22H).
The local receive OMA is still not active since the NIC is
in LOOPBACK.

0

Rrol~I~I~I~I~I~I~I~1

11) Initialize the Transmit Configuration for the intended value. The NIC is now ready for transmission and reception.

Note: The FIFO should only be read when the NIC has been programmed in
loopback mode.

1-27

oo

en

11.0 Initialization Procedures

CO)

(Continued)

~

(I)

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......
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en
CO)

CO

0.

C

When in word-wide mode with Byte Order Select low, the
following format must be used for the loopback packet.

Before receiving packets, the user must specify the location
of the Receive Buffer Ring. This is programmed in the Page
Start and Page Stop Registers. In addition, the Boundary
and Current Page Registers must be initialized to the value
of the Page Start Register. These registers will be modified
during reception of packets.

MS BYTE (AD8-15)
DESTINATION
SOURCE

12.0 Loopback Diagnostics

LENGTH

Three forms of localloopback are provided on the NIC. The
user has the ability to loopback through the deserializer on
the DP8390C NIC, through the DP8391 SNI, and to the coax
to check the link through the transceiver circuitry. Because
of the half duplex architecture of the NIC, loopback
testing is a special mode of operation with the following restrictions:

CRC

(OCR BITS)

r

ff the loopback is through the NIC then the serializer is simply linked to the deserializer and the receive clock is derived
from the transmit clock.
MODE 2: Loopback Through the SNI (LBI = 1, LBO = 0).
ff the loopback is to be performed through the SNI, the NIC
provides a control (LPBK) that forces the SNI to loopback
all signals.
MODE 3: Loopback to Coax (LBI = 1, LBO = 1).

"0" in TeA

When in word-wide mode with Byte Order Select set, the
loopback packet must be assembled in the even byte locations as shown below. (The loopback only operates with
byte wide transfers.)
LS BYTE (AD8-15)

I

BOS = "0"

Loopback Modes
MODE 1: Loopback Through the Controller (LB 1 = 0, LBO
= 1).

= 46 to 1500 bytes
=

CRC

To initiate a loopback the user first assembles the loopback
packet then selects the type of loopback using the Transmit
Configuration register bits LBO, LB 1. The transmit configuration register must also be set to enable or disable CRC generation during transmission. The user then issues a normal
transmit command to send the packet. During loopback the
receiver checks for an address match and if CRC bit in the
TCR is set, the receiver will also check the CRC. The last 8
bytes of the loopback packet are buffered and can be read
out of the FIFO using the FIFO read port.

2 bytes

Appended by NIC if CRG

T

~1..

(U.

TLiF/8582-16

SOURCE ADDRESS

DATA

DATA

Note: When using loop hack in word mode 2n bytes must be programmed in
TBCRO, 1. Where n = actual number of bytes assembled in even or
odd location.

= (6 bytes) Station Physical Address

LENGTH

Ill.

WTS ="1"

Restrictions During Loopback
The FIFO is split into two halves, one used for transmission
the other for reception. Only 8-bit fields can be fetched from
memory so two tests are required for 16-bit systems to verify integrity of the entire data path. During loopback the maximum latency from the assertion of BREQ to BACK is 2.0 !'S.
Systems that wish to use the loopback test yet do not meet
this latency can limit the loop back packet to 7 bytes without
experiencing underflow. Only the last 8 bytes of the loopback packet are retained in the FIFO. The last 8 bytes can
be read through the FIFO register which will advance
through the FIFO to allow reading the receive packet sequentially.
DESTINATION ADDRESS

LS BYTE (ADO-7)

Packets can be transmitted to the coax in loopback mode to
check all of the transmit and receive paths and the coax
itself.

MS BYTE (ADO-7)
DESTINATION

Note: In MODE 1, CRS and COL lines are not indicated in any status register. but the NIC will still defer if these lines are active. In MODE 2.
COL is masked and in MODE 3 CRS and COL are not masked. It is
not possible to go directly between the loopback modes. it is necessary to return to normal operation (OOH) when changing modes.

SOURCE
LENGTH

'-'.

I

T

WTS="I"

I

BOS="I"

DATA
CRC
(OCR BITS)

Reading the Loopback Packet
The last eight bytes of a received packet can be examined
by 8 consecutive reads of the FIFO register. The FIFO
pOinter is incremented alter the rising edge of the CPU's
read strobe by internally synchronizing and advancing the
pOinter. This may take up to four bus clock cycles, if the
pOinter has not been incremented by the time the CPU
reads the FIFO register again, the NIC will insert wait states

~~

r

TL/F/8582-15

Note: The FIFO may only be read during Loopback. Reading the FIFO at
any other time will cause the NIC to malfunction.

1-28

C

."

12.0 Loopback Diagnostics

Q)

(Continued)
Alignment of the Received Packet In the FIFO

Co)

LOOPBACK OPERATION IN THE NIC

Reception of the packet in the FIFO begins at location zero,
after the FIFO pointer reaches the last location in the FIFO,
the pointer wraps to the top of the FIFO overwriting the
previously received data. This process continues until the
last byte is received. The NIC then appends the received
byte count in the next two locations of the FIFO. The contents of the Upper Byte Count are also copied to the next
FIFO location. The number of bytes used in the loopback
packet determines the alignment of the packet in the FIFO.
The alignment for a 64-byte packet is shown below.
FIFO
LOCATION

Loopback is a modified form of transmission using only half
of the FIFO. This places certain restrictions on the use of
loopback testing. When loopback mode is selected in the
TCR, the FIFO is split. A packet should be assembled in
memory with programming of TPSR and TBCRO,TBCR1
registers. When the transmit command is issued the following operations occur:
Transmitter Actions
1) Data is transferred from memory by the DMA until the
FIFO is filled. For each transfer TBCRO and TBCR 1 are
decremented. (Subsequent burst transfers are initiated
when the number of bytes in the FIFO drops below the
programmed threshold.)
2) The N IC generates 56 bits of preamble followed by an
8-bit synch pattern.
3) Data transferred from FIFO to serializer.

FIFO
CONTENTS
LOWER BYTE COUNT

First Byte Read

UPPER BYTE COUNT

Second Byte Read

UPPER BYTE COUNT
LAST BYTE
CRCt

4) If CRC = 1 in TCR, no CRC calculated by NIC, the last
byte transmitted is the last byte from the FIFO (Allows
software CRC to be appended). If CRC=O, NIC calculates and appends four bytes of CRC.

CRC2
CRC3
Last Byte Read

CRC4

5) At end of Transmission PTX bit set in ISR.

For the following alignment in the FIFO the packet length
should be (N x 8) + 5 Bytes. Note that if the CRC bit in the
TCR is set, CRC will not be appended by the transmitter. If
the CRC is appended by the transmitter, the last four bytes,
bytes N-3 to N, correspond to the CRC.
FIFO
LOCATION

Receiver Actions
1) Wait for synch, all preamble stripped.
2) Store packet in FIFO, increment receive byte count for
each incoming byte.

FIFO
CONTENTS

Second Byte Read

3) If CRC = 0 in TCR, receiver checks incoming packet for
CRC errors. If CRC= 1 in TCR, receiver does not check
CRC errors, CRC error bit always set in RSR (for address
matching packets).

Last Byte Read

4) At end of receive, receive byte count written into FIFO,
receive status register is updated. The PRX bit is typically
set in the RSR even if the address does not match. If
CRC errors are forced, the packet must match the address filters in order for the CRC error bit in the RS to be
set.

BYTE N·4
BYTE N·3 (CRCt)

First Byte Read

AR

BYTE N·2 (CRC2)
BYTE N·t (CRC3)
BYTE N (CRC4)
LOWER BYTE COUNT
UPPER BYTE COUNT

EXAMPLES
The following examples show what results can be expected
from a properly operating N IC during loopback. The restrictions and results of each type of loopback are listed for
reference. The loopback tests are divided into two sets of
tests. One to verify the data path, CRC generation and byte
count through all three paths. The second set of tests uses
internal loopback to verify the receiver's CRC checking and
address recognition. For all of the tests the DCR was programmed to 40h.

UPPER BYTE COUNT

LOOPBACK TESTS
Loopback capabilities are provided to allow certain tests to
be performed to validate operation of the DP8390C N IC prior to transmitting and receiving packets on a live network.
Typically these tests may be performed during power up of
a node. The diagnostic provides support to verify the following:
1) Verify integrity of data path. Received data is checked
against transmitted data.
2) Verify CRC logic's capability to generate good CRC on

transmit, verify CRC on receive (good or bad CRG).
3) Verify that the Address Recognition Logic can
Note 1: Since carrier sense and collision detect inputs are blocked during
internal loopback, carrier and CD heartbeat are not seen and the CRS and
CDH bils are set.

a) Recognize address match packets
b) Reject packets that fail to match an address

Note 2: CRG errors are always indicated by receiver if CRG is appended by
the transmitter.
Nole 3: Only the PTX bit in the ISR is sel. the PRX bil is only set if status is
written to memory. In loopback this action does not occur and the PRX bit
remains 0 for all loopback modes.
Note 4: All values are hex.

1-29

CD

o

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Co)

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"'oo"
CD

12.0 Loopback Diagnostics (Continued)
NETWORK MANAGEMENT FUNCTIONS
Network management capabilities are required for maintenance and planning of a local area network. The NIC supports the minimum requirement for network management in
hardware, the remaining requirements can be met with software counts. There are three events that software alone
can not track during reception of packets: CRC errors,
Frame Alignment errors, and missed packets.

Note 1: CDH is set, CRS is not set since it is generated by the external

encoder/decoder.

Since errored packets can be rejected, the status associated with these packets is lost unless the CPU can access the
Receive Status Register before the next packet arrives. In
situations where another packet arrives very quickly, the
CPU may have no opportunity to do this. The NIC counts
the number of packets with CRC errors and Frame Alignment errors. S-bit counters have been selected to reduce
overhead. The counters will generate interrupts whenever
their MSBs are set so that a software routine can accumulate the network statistics and reset the counters before
overflow occurs. The counters are sticky so that when they
reach a count of 192 (COH) counting is halted. An additional
counter is provided to count the number of packets NIC
misses due to buffer overflow or being offline.
The structure of the counters is shown below:

Note 1: CDH and CRS should not be set. The TSR however, could also
contain 01 H,03H,07H and a variety of other values depending on whether
collisions were encountered or the packet was deferred.
Note 2.Will contain OSH if packet is not transmittable.
Note 3: During externalloopback the NIC is now exposed to network traffic.
it Is therefore possible for the contents of both the Receive portion of the
FIFO and the RSR to be corrupted by any other packet on the network. Thus
in a live network the contents of the FIFO and RSR should not be depended
on. The NIC will still abide by the standard CSMAlCD protocol in extemal
loopback mode. (i.e. The network will not be disturbed by the loopback
packet).
Nota 4: All values are hex.

CRC AND ADDRESS RECOGNITION
The next three tests exercise the address recognition logic
and CRC. These tests should be performed using internal
loopback only so that the N IC is isolated from interference
from the network. These tests also require the capability to
generate CRC in software.
The address recognition logic cannot be directly tested. The
CRC and FAE bits in the RSR are only set if the address of
the packet matches the address filters. If errors are expected to be set and they are not set, the packet has been
rejected on the basis of an address mismatch. The following
sequence of packets will test the address recognition logic.
The DCR should be set to 40H, the TCR should be set to
03H with a software generated CRC.
Packet Contents
Address

CRC

RSR

TestA
TestB
TestC

Matching
Matching
Non-Matching

Good
Bad
Bad

01 (1)
02(2)
01

,RAME ALIGNMENT ERRORS COUNTER

CIIlRl

CRC ERRORS COUNTER

CNlR2

MISSEO PACI.J>-

...;;D..
AT..A_ _ _ _ _J

---<"'________

A8...-...
15_ _ _ _ _ _ _ _

-F'_______________
,'---_-1/

1·31

TL/F/8582-65

13.0 Bus Arbitration and Timing

(Continued)

16-Bit Address, 16-Bit Data
T1

T2

T3

T4

BSCK

ADO-7

ADB-15

ADSO

--<
--<

AO-7

A6-15

X~------------~}--X~------------~}--DATA

DATA

--1\
\~________...J'

MWR,MRD

TL/F/8582-66

32-Bit Address, 8-Bit Data
T1-T4

T1

T2

T3

T4

BSCK

ADO-7

ADB-15
ADS1

--<
--<

A16-23

A24-31

X
X

X'"___.....;D.;..AT.;..A_ _ _ _.J}---

AO-7

A6-15

}---

r--\
~2r--------------------------

...

---J
ADSO

,-----------------------

r--\

--------~Z~

\~

______.J'

TL/F/8582-67

32-Bit Address, 16-Blt Data

I

T1-T4

T2

T1

BSCK~
ADO-7

ADB-15

--<
--<

A16-23

X

AO-7

A24-31

X

A6-15

X
X

T3

I

I

I

DATA

}---

DATA

}---

\\..-----',
Note: In 32-bH address mode, ADS1 is at TRI-STATE,afler the first

T4

TLlF/8582-68

n- T4 states; thus, a 4.7k pull-down resistor is required for 32-biI address mode.

1-32

C

13.0 Bus Arbitration and Timing

When in 32-bit mode four additional BSCK cycles are required per burst. The first bus cycle (Tl' - T4') of each burst
is used to output the upper 16-bit addresses. This 16-bit
address is programmed in RSARO and RSARl and points to
a 64k page of system memory. All transmitted or received
packets are constrained to reside within this 64k page.

transfer an exact burst of bytes programmed in the Data
Configuration Register (DCR) then relinquish the bus. If
there are remaining bytes in the FIFO the next burst will not
be initiated until the FIFO threshold is exceeded. If desired
the DMA can empty/fill the FIFO when it acquires the bus. If
BACK is removed during the transfer, the burst transfer will
be aborted. (DROPPING BACK DURING A DMA CYCLE IS
NOT RECOMMENDED.)

FIFO BURST CONTROL
All Local DMA transfers are burst transfers, once the DMA
requests the bus and the bus is acknowledged, the DMA will

BREO

---.I

BACK

--~I

"tI

co
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(Continued)

,'----~

~ ................ ~.
I~NE'BURST
~I

AOO-15

TLlF/8582-69

where N = 1, 2, 4, or 6 Words or N = 2, 4, 8, or 12 Bytes when in byte mode

INTERLEAVED LOCAL OPERATION

transfers. When the Local DMA transfer is completed the
Remote DMA will rearbitrate for the bus and continue its
transfers. This is illustrated below:

If a remote DMA transfer is initiated or in progress when a

packet is being received or transmitted, the Remote DMA
transfer will be interrupted for higher priority Local DMA

BREO

---.I

'..._--

'~ ___I

BACK

ADO-15

TL/F/8582-70

Note that if the FIFO requires service while a remote DMA is
in progress, BREQ is not dropped and the Local DMA burst
is appended to the Remote Transfer. When switching from
a local transfer to a remote transfer, however, BREQ is
dropped and raised again. This allows the CPU or other
devices to fairly contend for the bus.

This transfer is arbited on a byte by byte basis versus the
burst transfer used for Local DMA transfers. This bidirectional port is also read/written by the host. All transfers
through this port are asynchronous. At anyone time transfers are limited to one direction, either from the port to local
buffer memory (Remote Write) or from local buffer memory
to the port (Remote Read).

REMOTE DMA-BIDIRECTIONAL PORT CONTROL
The Remote DMA transfers data between the local buffer
memory and a bidirectional port (memory to I/O transfer).

Bus Handshake Signals for Remote DMA Transfers
BIDIRECTIONAL PORT
NIC SIGNALS

DMA SIGNALS

~
OEA
8/16
DATA 4
PWR

RACK

•

7'-

CKA

~
~

4
CKB

(

7

lOW
~ DATA

8/16
OEB

Y

lORD

PRO ~.-----------+~ ORO

1-33

TLlF/8582-71

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13.0 Bus Arbitration and Timing

(Continued)
Steps 1-3 are repeated until the remote DMA is complete.

REMOTE READ TIMING

1) The DMA reads byte/word from local buffer memory and
writes byte/word into latch, increments the DMA address
and decrements the byte count (RBCRO,1).
2) A Request Line (PRO) is asserted to inform the system
that a byte is available.

Note that in order for the Remote DMA to transfer a byte
from memory to the latch, it must arbitrate access to the
local bus via a BREO, BACK handshake. After each byte or
word is transferred to the latch, BREO is dropped. If a Local
DMA is in progress, the Remote DMA is held off until the
local DMA is complete.

3) The system reads the port, the read strobe (RACK) is
used as an acknowledge by the Remote DMA and it goes
back to step 1.
BREQ

---1

\
I

BACK

\
(

ADO-IS

IBYTE/WORD

)

f\

ADSO

'----'

MRD

'--.J
I

PWR

PRQ

_

BYTE WRIITEN
TO LATCH

\

_ _ WAIT FOR _ _ BYTE READ
HOST
BY HOST

REMOTE WRITE TIMING

A Remote Write operation transfers data from the I/O port
to the local buffer RAM. The NIC initiates a transfer by requesting a byte/word via the PRO. The system transfers a
byte/word to the latch via iOW, this write strobe is detected
by the NIC and PRO is removed. By removing the PRO, the
Remote DMA holds off further transfers into the latch until
the current byte/word has been transferred from the latch,
PRO is reasserted and the next transfer can begin.

I

PRQ

TL/F/8582-72

1) NIC asserts PRO. System writes byte/word into latch.
NIC removes PRO.
2) Remote

DMA reads contents of port and writes
byte/word to local buffer memory, increments address
and decrements byte count (RBCRO,1).
3) Go back to step 1.
Steps 1-3 are repeated until the remote DMA is complete.

\

'---'

WACK

I

BREQ

\
I

BACK

\
(

ADO-IS

IBYTE/WORD

)

f\
'----I

AOSO

MWR

'----'

PRO
-

BYTE WRmEN TO
LATCH BY SYSTEM

-

1-34

BYTE READ FROM LATCH
BY REMOTE DNA AND
WRmEN TO LOCAL
BUFFER MEMORY

TL/F/8582-73

13.0 Bus Arbitration and Timing (Continued)
SLAVE MODE TIMING

ADSO is used to latch the address when interfaCing to a
multiplexed, address data bus. Since the NIC may be a local
bus master when the host CPU attempts to read or write to
the controller, an ACl< line is used to hold off the CPU until
the NIC leaves master mode. Some number of BSCK cycles
is also required to allow the NIC to synchronize to the read
or write cycle.

When CS is low, the NIC becomes a bus slave. The CPU
can then read or write any internal registers. All register
access is byte wide. The timing for register access is shown
below. The host CPU accesses intemal registers with four
address lines, RAO-RA3, SRD and SWR strobes.

Write to Register
RAO-RA3

ADSO

ADO-A07

---------c~~~~

'--_--II"
~------------~I"

TLlF/8582-74

RAO-RA3

ADSO
ADO-AD7

---------c~~~~

ACK

'---_---JI"

CS

~------------~I"

1-35

TLlF/8582-75

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14.0 Preliminary Electrical Characteristics

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Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

-0.5Vto +7.0V
Supply Voltage (Vecl
DC Input Voltage (VIN)
-0.5V to Vee + 0.5V
DC Output Voltage (VOUT)
-0.5V to Vee + 0.5V
Storage Temperature Range (TSTG)
-65'C to + 150'C
Power Dissipation (PO)
500mW
Lead Temp. (TL) (Soldering. 10 sec.)
260'C
1600V
ESD rating (RZAP = 1.5k, CZAP = 120 pF)

Preliminary DC Specifications TA = O'C to 70'C, Vee = 5V ± 5%, unless otherwise specified
Symbol

Parameter

Conditions

= -20",A
= -2.0mA
10L = 20",A
10L = 2.0mA

Min

Max

Units

VOH

Minimum High Level Output Voltage
(Notes 1,4)

VOL

Minimum Low Level Output Voltage
(Notes 1,4)

VIH

Minimum High Level Input Voltage
(Note 2)

2.0

V

VIH2

Minimum High Level Input Voltage
for RACK, WACK (Note 2)

2.7

V

VIL

Minimum Low Level Input Voltage
(Note 2)

0.8

V

VIL2

Minimum Low Level Input Voltage
For RACK, WACK (Note 2)

0.6

V

liN

Input Current

VI

-1.0

+1.0

",A

loz

Maximum TRI-STATE
Output Leakage Current

VOUT

-10

+10

",A

lee

Average Supply Current
(Note 3)

TXCK = 10 MHz
RXCK = 10 MHz
BSCK = 20 MHz
lOUT = O",A
VIN = Vee or GND

40

mA

10H
10H

=

Vee or GND

=

Vee or GND

V
V

Vee - 0.1
3.5
0.1
0.4

V
V

Note 1: These levels are tested dynamically using a limited amount of functional test patterns, please refer to AC Test Load.
Note 2: Limited functional test patterns are performed at these input levels. The majority of functional tests are performed at levels of OV and 3V.

Note 3: This is measured with a 0.1 ,.F bypass capacitor between Vee and GND.
Note 4: The low drive CMOS compatible VOH and VOL limits are not tested directly. Detailed device characterization validates that this specification can be

guaranteed by testing the high drive TTL compatible VOL and VOH specification.

1-36

C

"tI

15.0 Switching Characteristics AC Specs DP8390C Note: All Timing is Preliminary

QC)
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Register Read (Latched Using ADSO)

RAO-3~~
~rss
Aosa
aswl

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trackh

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I:::jrdZ

ADa-7--------------------------------------1::::::§OO~-~7::::::}_----TL/F/8582-76

Symbol

Parameter

Min

Max

Units

rss

Register Select Setup to ADSO Low

10

ns

rsh

Register Select Hold from ADSO Low

13

ns

aswi

Address Strobe Width In

15

ackdv

Acknowledge Low to Data Valid

rdz

Read Strobe to Data TRI-STATE

rackl

Read Strobe to ACK Low (Notes 1, 3)

rackh

Read Strobe to ACK High

rsrsl

Register Select to Slave Read Low,
Latched RSO-3 (Note 2)

ns

55
15

70
n*bcyc
30

10

ns
ns

+ 30

ns
ns
ns

Note 1: ACR is not generated until CS and SAD are low and the NIC has synchronized to the register access. The NIC will insert an integral number of Bus Clock
cycles until it is synchronized. In Dual Bus systems additional cycles will be used for a local or remote DMA to complete. Wait states must be issued to the CPU until

7iCK is asserted low.
Note 2: CS may be asserted before or after SRD. If CS is asserted after SRD, rackl is referenced from falling edge of CS. CS can be de-asserted concurrently with

SliD or after SRD is de-asserted.
Note 3: These limits include the RC delay inherent in our test method. These signals typically turn off within 15 ns, enabling other devices to drive these lines with
no contention.

1-37

15.0 Switching Characteristics (Continued)
Register Read (Non Latched, ADSO = 1)
I
RAO-3

I-rsrh

cs

\.\\\\.

--I

'////

I--rsrsSRD

I--

-I t

rack I

-

ACK

rackh

:--1 rdz

I--ackdv
ADO-7

00-7
TL/F/8582-77

Symbol
rsrs

Parameter

Min

Register Select to Read Setup
(Notes 1, 3)

10

rsrh

Register Select Hold from Read

0

ackdv

ACK Low to Valid Data

rdz

Read Strobe to Data TRI-STATE
(Note 2)

rackl

Read Strobe to AC;K Low (Note 3)

rackh

Read Strobe to ACK High

15

Max

Units
ns
rlS

55

ns

70

ns

n*bcyc
30

+ 30

ns
ns

Note 1: rsrs includes flow-through time of latch.
Note 2: These limits include the RC delay inherent in our test method. These signals typically turn off within 15 ns enabling other devices to drive these lines with
no contention.
Note 3: CS may be asserted before or after RAe-3, and SRD, since address decode begins when ACK is asserted. If CS is asserted after RAO-3, and SAD, rack!
is referenced from falling edge of CS.

1-38

C

."

15.0 Switching Characteristics (Continued)

01)

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I-- rss -:-1 rsh
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SWR

t

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ACK

wackh

I
I-- wackl ....

I rwdh

r-rwds

AOO-7

00-7
TLiF/8582-78

Symbol

Parameter

Min

Max

Units

rss

Register Select Setup to ADSO Low

10

ns

rsh

Register Select Hold from ADSO Low

17

ns

aswi

Address Strobe Width In

15

ns

rwds

Register Write Data Setup

20

ns

rwdh

Register Write Data Hold

21

ns

ww

Write Strobe Width from ACK

50

wackh

Write Strobe High to ACK High

wackl

Write Low to ACK Low (Notes 1, 2)

ns

30
n'bcyc

ns

+ 30

ns

rswsl
Register Select to Write Strobe Low
10
ns
Note 1: ACK is not generated until CS and SWR are low and the NIC has synchronized to the register access. In Dual Bus Systems additional cycles will be used
for a local DMA or Remote DMA to complete.
Note 2: CS may be asserted before or after SWR. If CS is asserted after SWR, wackl is referenced from falling edge of CS.

1-39

oo

0>
.".
C'II

15.0 Switching Characteristics (Continued)

('t)

Register Write (Non Latched, ADSO = 1)

en
z
......
oo

I

RAO-3

0>

I-- rswh-./

('t)

CO

Q.

cs

C

I---- rsws __

ww

SWR

I---

t:

.....

wackl

-ACK

wackh

I

C
ADO-7

I rwdh

rwds

DO-7
TLiF/8582-79

Symbol
rsws

Parameter

Min

Register Select to Write Setup
(Note 1)

Max

Units

15

ns

rswh

Register Select Hold from Write

a

ns

rwds

Register Write Data Setup

20

ns

21

ns

rwdh

Register Write Data Hold

wackl

Write Low to ACK Low
(Note 2)

wackh

Write High to ACK High

ww

Write Width from ACK

n*bcyc
30
50

+ 30

ns
ns
ns

Note 1: Assumes ADSO is high when RAO-3 changing.

cs:

Note 2: ACK is not generated until
and SWR are low and the NIC has synchronized to the register access. In Dual Bus systems additional cycles will be used for
a local DMA or remote DMA to complete.

1-40

C

15.0 Switching Characteristics

"tJ
QI)

(Continued)

w
o

CD

DMA Control, Bus Arbitration
T4

n

T2

T3

T4

n

T2

T3

T4

n

T2

T3

n

T4

T2

T3

T4

n

T2

T3

brqhl

"'o"

CD

o

--''-------11---'1
bcctr

ADSO

ADO-15

MWR.MRD

r....-T--+-+-"\

-------+--~.:-.-I.

---------------------t~~~-~-::-:-!-:-~-~-~-~-::-t__1<:~::K:~~:::>

DATA

------------------------~.~.------~.~------____.11
-

FIRST TRANSFER
IF BACK SEEN ON
FIRST T1.

I
-----r--

FIRST TRANSFER
IF BACK NOT GIVEN
ON FIRST n.

I

-1

LAST TRANSFER
TL/F/8582-80

Symbol
brqhl

z
en
w

N

BREQ

BACK

o......

Parameter

Min

Max

Units

Bus Clock to Bus Request High for Local DMA

43

ns

brqhr

Bus Clock to Bus Request High for Remote DMA

38

brql

Bus Request Low from Bus Clock

backs

Acknowledge Setup to Bus Clock
(Note 1)

bccte

Bus Clock to Control Enable

60

ns

bcctr

Bus Clock to Control Release
(Notes 2,3)

70

ns

ns

50
2

ns
ns

Note 1: BACK must be setup before T1 after BREQ is asserted. Missed setup will slip the beginning of the OMA by four bus clocks. The Bus Latency will influence
the allowable FIFO threshold and transfer mode (empty Ifill vs exact burst transfer).

Note 2: During remote DMA transfers only, a single bus transfer is performed. During local DMA operations burst mode transfers are performed.
Note 3: These limits include the RC delay inherent in our test method. These signals typically turn off within 15 ns enabling other devices to drive these lines with
no contention.

1-41

15.0 Switching Characteristics (Continued)
DMA Address Generation
T1' (NOTE 1)

T2'

T3'

T4'

T1

T2

13

BSCK'--'r--'I'-J~~~
-

ADS 1
beash -

~

beh_ --bel

r"'
.~

~

beye
beadz

beasl

beash -

ADSO
beadv

ADO-15

~

beasl

aswo-

--=:j ads ~

~adh-

beadv

r--I+ ads + r-t adh
AO-A15

A16-A31

DATA
TLlF/8582-81

Symbol
bcyc

Parameter
Bus Clock Cycle Time
(Note 2)

Min

Max

Units

50

1000

ns

bch

Bus Clock High Time

22.5

bcl

Bus Clock Low Time

22.5

bcash

Bus Clock to Address Strobe High

34

ns

bcasl

Bus Clock to Address Strobe Low

44

ns

aswo

Address Strobe Width Out

bcadv

Bus Clock to Address Valid

45

ns

bcadz

Bus Clock to Address TRI-STATE
(Note 3)

55

ns

ads

Address Setup to ADSO/l Low

adh

Address Hold from ADSO/l Low

ns
ns

bch

15

ns

bch - 15

ns

bcl- 5

ns

Nole 1: Cycles T1', T2', T3', T4' are only issued for the first transfer in a burst when 32-bit mode has been selected.
Note 2: The rate of bus clock must be high enough to support transfers tolfrom the FIFO at a rate greater than the serial network transfers from/to the FIFO.
Note 3: These limits include the RC delay inherent in our test method. These signals typically turn off within 15 ns, enabling other devices to drive these lines with
no contention.

1-42

C

"'tI

15.0 Switching Characteristics (Continued)

01)
Co)

CD

o

DMA Memory Read
I

I

T1

I

T2

I

T3

I

T4

o.......
z
CJ)

I

T1

BSCK

Co)

N
~ bcrl

ADSO

I--bcrh

r-'
.....

~

asds ~

-

AO-7

YI I ILLliL~
avrh

ADS-15
(8 BIT MODE)

AS-15

d~

dsadadhf-

- ..... dh

Symbol
bcrl

A8-A15

YIIIIIIII/<

Parameter

AO-7x/1/

0 A

..... raz fds

ADS-15
(16 BIT MODE)

CD

drw

MRD

ADO-7
(8. 16 BIT MODE)

.j::o.

DATA

AS-IS

-

Min

AO-15XI I /
TLlF/8582-82

Max

Units

43

ns

40

ns

Bus Clock to Read Strobe Low

bcrh

Bus Clock to Read Strobe High

ds

Data Setup to Read Strobe High

25

ns

dh

Data Hold from Read Strobe High

0

ns

drw

DMA Read Strobe Width Out

2*bcyc - 15

ns

raz

Memory Read High to Address TRI-STATE
(Notes 1. 2)

asds

Address Strobe to Data Strobe

dsada

Data Strobe to Address Active

avrh

Address Valid to Read Strobe High

bch

+ 40

ns

bel

+

ns

10

beye - 10

ns

3*beye - 15

ns

Nole 1: During a burst A8-A15 are not TRI-STATE if byte wide transfers are selected_ On the last transfer A8-A15 are TRI-STATE as shown above.
Note 2: These limits include the RC delay inherent in our test method. These signals typically turn off within bch
lines with no contention.

1-43

+

15 ns, enabling other devices to drive these

15.0 Switching Characteristics (Continued)
DMA Memory Write

I

I

T1

I

T2

I

T3

T4

I

I

T1

BSCK

bcwh

I-bcwl
ADSO

r-\

...

asds

MWR

-

--aswd
ADO-7
(8, 16 BIT MODE)

I-

AO-A7

wds- wdh I-

'/11)

--

AD8-15
(8 BIT MODE)

X/ / /

DATA (DO-D7)

AO-A7

waz I-

A8-A15

A8-15

I--wds- wdh
ADO-15
(16 BIT MODE)

AO-A15

,/11

I-

DATA (00-015)

Ao-mX! / /
TL/F/8582-83

Symbol

Max

Units

bewl

Bus Clock to Write Strobe Low

Parameter

Min

40

ns

bewh

Bus Clock to Write Strobe High

40

ns

wds

Data Setup to WR High

wdh

Data Hold from WR Low

waz

Write Strobe to Address TRI-STATE
(Notes 1, 2)

asds
aswd

2*beye - 30
beh

ns

+7

ns
beh

+ 40

ns

Address Strobe to Data Strobe

bel
bel

+ 10
+ 30

ns

Address Strobe to Write Data Valid

ns

Nota 1: When using byte mode transfers A8-A15 are only TRI-STATE on the last transfer, wat timing is only valid for last transfer in a burst.
Nota 2: These limits include the RC delay inherent in our test method. These Signals typically turn off within bch
Jines with no contention.

1-44

+ 15 ns, enabling other devices to drive these

15.0 Switching Characteristics (Continued)
Walt State Insertion

I

Tt

I

I

T2

T3

I

I

TW

I

T4

BSCK~~~
ADSO

/

\.

MRD/MWR

..:\ewr __

I::.ews-

I

READY

\.
TL/F/B5B2-45

Symbol

Parameter

Min

ews

External Wait Setup to T3.J, Clock
(Note 1)

Max

Units

10

ns

ewr

External Wait Release Time
(Note 1)

15

ns

Note 1: The addnlon of wait stales affects the count of deserialized bytes and is limiled to a number of bus clock cycles depending on ths bus clock and network
rales. The allowable wan states are found in the table below. (Assumes 10 Mbitlsec data rate.)
The number of allowable wait states in byte mode can be calculated using:

"" of Walt States

BUSCK(MHz)

Byte Transfer

Word Transfer

8

0

1

10

0

1

12

1

2

14

1

2

16

1

3

18

2

3

20

2

4

#W(bytomode)
#W

tnw
tbsck

=

(Btnw
----1 )
4.5tbsck

= Number of wan States
= Network Clock Period
= BSCKPeriod

The number of allowable wan states In word mode can be calculated using:
#W(WOrd mode)

Table assumes 10 MHz network clock.

1-45

5tnw
)
1
= ( 2iiiSCk-

15.0 Switching Characteristics

(Continued)

Remote DMA (Read, Send Command)
I

I

Tl

T2

I

T3

BSCK~~
ADSO

~~

r-\

~

-' S

MRD

--

PWR

--- ~

-bpwrl

--bpwrh

PRO

S

.....

S~

RACK

ADO-15

S

(

AO-A15

)

(

00-015

~

S

--

~

'-... prql

'r-

rakw ~

TL/F/6562-64

Max

Units

bpwrl

Bus Clock to Port Write Low

43

ns

bpwrh

Bus Clock to Port Write High

40

ns

prqh

Port Write High to Port
Request High (Note 1)

30

ns

prql

Port Request Low from
Read Acknowledge High

45

ns

rakw

Remote Acknowledge
Read Strobe Pulse Width

Symbol

Parameter

Min

20

Note 1: Start of next transfer is dependent on where RACK is generated relative to BSCK and whether a local DMA is pending.

1-46

ns

C

"tJ

15.0 Switching Characteristics (Continued)

CO

w

CD

o
o
......

Remote DMA (Read, Send Command) Recovery Time

z

(J)

W
N
0l:Io
CD

o

o

-

ADO-15~5

Symbol

00-015
TL/F/8582-85

Parameter

Min

Max

Units

bpwri

Bus Clock to Port Write Low

43

ns

bpwrh

Bus Clock to Port Write High

40

ns

prqh

Port Write High to Port
Request High (Note 1)

30

ns

prql

Port Request Low from
Read Acknowledge High

45

ns

rakw

Remote Acknowledge
Read Strobe Pulse Width

20

ns

rhpwh

Read Acknowledge High to
Next Port Write Cycle
(Notes 2,3,4)

11

BUSCK

Note 1: Start of next transfer is dependent on where RACK is generated relative to BSCK and whether a local DMA is pending.
Note 2: This is not a measured value but guaranteed by design.
Note 3: RACK must be high for a minimum of 7 BUSCK.

Note 4: Assumes no local DMA interleave, no CS, and immediate BACK.

1-47

(.)

o
en

' 0 fch) then
upper byte count = upper byte count + 1

Z

REMOVING PACKETS FROM THE RING

Packets are removed from the ring using the Remote DMA
or an external device. When using the Remote DMA the
Send Packet command can be used. This programs the Remote DMA to automatically remove the received packet
pointed to by the Boundary Pointer. At the end of the transfer, the NIC moves the Boundary Pointer, freeing additional
buffers for reception. The Boundary Pointer can also be
moved manually by programming the Boundary Register.
Care should be taken to keep the Boundary Pointer at least
one buffer behind the Current Page Pointer.
The following is a suggested method for maintaining the
Receive Buffer Ring pointers.

AD8

AD?

ADO

Next Packet
Pointer

Receive
Status

Receive
Byte Count 1

Receive
Byte Count 0

Byte 2

Byte 1

BOS = 0, WTS = 1 in Data Configuration Register.

This format used with Series 32000 808X type processors.
AD15

CURR = PSTART+l
nexLpkt = PSTART + 1
3. After a packet is DMAed from the Receive Buffer Ring,
the Next Page Pointer (second byte in NIC buffer header)
is used to update BNDRY and nexLpkt.
nexLpkt = Next Page Pointer
BNDRY = Next Page Pointer - 1

AD8

AD?

ADO

Next Packet
Pointer

Receive
Status

Receive
Byte Count 1

Receive
Byte Count 0

Byte 1

Byte 2

BOS = 1, WTS = 1 in Data Configuration Register.

< PSTART then BNDRY = PSTOP - 1

This format used with 68000 type processors.

Note the size of the Receive Buffer Ring is reduced by one
256-byte buffer; this will not, however, impede the operation
of the NIC.
In StarLAN applications using bus clock frequencies greater
than 4 MHz, the NIC does not update the buffer header
information properly because of the disparity between the
network and bus clock speeds. The lower byte count is copied twice into the third and fourth locations of the buffer
header and the upper byte count is not written. The upper
byte count, however, can be calculated from the current
next page pointer (second byte in the buffer header) and the
previous next page pointer (stored in memory by the CPU).
The following routine calculates the upper byte count and
allows Star LAN applications to be insensitive to bus clock
speeds. NexLpkt is defined similarly as above.

Note: The Receive Byte Count ordering remains the same for BOS

=

a or 1

ADO

AD?
Receive Status
Next Packet
Pointer
Receive Byte
Count 0
Receive Byte
Count 1
Byte 0
Byte 1
BOS

1st Received Packet Removed By Remote DMA

=

0, WTS

=

Q in Data Configuration Register.

This format used with general 8-bit CPUs.

8.0 Packet Transmission
The Local DMA is also used during transmission of a packet. Three registers control the DMA transfer during transmission, a Transmit Page Start Address Register (TPSR)
and the Transmit Byte Count Registers (TBCRO,I). When
the NIC receives a command to transmit the packet pointed
to by these registers, buffer memory data will be moved into
the FIFO as required during transmission. The NIC will generate and append the preamble, synch and CRC fields.

1-63

(/)
Co)

N
.....
CD

.

o

The following diagrams describe the format for how received packets are placed into memory by the local DMA
channel. These modes are selected in the Data Configuration Register.
Storage Format

1. At initialization, set up a software variable (nexLpkt) to
indicate where the next packet will be read. At the beginning of each Remote Read DMA operation, the value of
nexLpkt will be loaded into RSARO and RSARI.
2. When initializing the NIC set:
BNDRY = PSTART

If BNDRY

......

.......

STORAGE FORMAT FOR RECEIVED PACKETS

AD15

o

o

......

~

oo
0)

"="
C\I
CO)

r-----------------------------------------------------------------------------------------------,
8.0 Packet Transmission

(Continued)
015

TRANSMIT PACKET ASSEMBLY

CO

The NIC requires a contiguous assembled packet with the
format shown. The transmit byte count includes the Destination Address, Source Address, Length Field and Data. It
does not include preamble and CRC. When transmitting
data smaller than 46 bytes, the packet must be padded to a
minimum size of 64 bytes. The programmer is responsible
for adding and stripping pad bytes.

C

General Transmit Packet Format

U)

z
......
~

oo
0)
CO)

D..

DESTINATION ADDRESS

6 BYTES

SOURCE ADDRESS

6 BYTES

TYPE LENGTH

2 BYTES

TX BYTE COUNT
(TBCRO,I)

DATA

----------------PAD (IF DATA < 46 BYTES)

2

0807

DO

DA1

DAO

DA3

DA2

DA5

DA4

SA1

DAO

SA3

DA2

SA5

DA4

TILl

TILO

DATA 1

DATA 0

BOS = 0, WTS = 1 in Data Configuration Register.

This format is used with Series 32000, 808X type processors.

46 BYTES

0807

015
TL/F/9345-16

TRANSMISSION

Prior to transmission, the TPSR (Transmit Page Start Register) and TBCRO, TBCR1 (Transmit Byte Count Registers)
must be initialized. To initiate transmission of the packet the
TXP bit in the Command Register is set. The Transmit
Status Register (TSR) is cleared and the NIC begins to prefetch transmit data from memory (unless the NIC is currently
receiving). If the interframe gap has timed out the NIC will
begin transmission.

DAO

DA1

DA2

DA3

DA4

DA5

SAO

SA1

SA2

SA3

SA4

SA5

TILO

TIl1

DATA 0

CONDITIONS REQUIRED TO BEGIN TRANSMISSION

In order to transmit a packet, the following three conditions
must be met:

DO

BOS = 1, WTS

DATA 1
=

1 in Data Configuration Register.

This format is used with 68000 type processors.

1. The Interframe Gap Timer has timed out the first 6.4 fts
of the Interframe Gap (See appendix for Interframe Gap
Flowchart)

DO

07
DAO

2. At least one byte has entered the FIFO. (This indicates
that the burst transfer has been started)

DAl

3. If the NIC had collided, the backoff timer has expired.

DA2

In typical systems the NIC has already prefetched the first
burst of bytes before the 6.4 fts timer expires. The time
during which NIC transmits preamble can also be used to
load the FIFO.

DA3
DA4
DA5

Note: If carrier sense is asserted before a byte has been loaded into the

FIFO, the NIC will become a receiver.

SAO

COLLISION RECOVERY

SAl

During transmission, the Buffer Management logic monitors
the transmit circuitry to determine if a collision has occurred.
If a collision is detected, the Buffer Management logic will
reset the FIFO and restore the Transmit DMA pointers for
retransmission of the packet. The COL bit will be set in the
TSR and the NCR (Number of Collisions Register) will be
incremented. If 15 retransmissions each result in a collision
the transmission will be aborted and the ABT bit in the TSR
will be set.

SA2
SA3
BOS

=

0, WTS = 0 in Data Configuration Register.

This format is used with general 8-bit CPUS.
Note: All examples above will result in a transmission of a packet in order of
DAO. DA 1. DA2. DA3 ... bils wilhin each byte will be Iransmitted leasl
significant bit first.

DA = Destination Address

Note: NCR reads as zeroes if excessive collisions are encountered.

SA = Source Address

TRANSMIT PACKET ASSEMBLY FORMAT

T /L

The following diagrams describe the format for how packets
must be assembled prior to transmission for different byte
ordering schemes. The various formats are selected in the
Data Configuration Register.
1-64

~

Type/Lenglh Field

o"'tJ

9.0 Remote DMA

01)
Co)

The Remote DMA channel is used to both assemble packets for transmission, and to remove received packets from
the Receive Buffer Ring. It may also be used as a general
purpose slave DMA channel for moving blocks of data or
commands between host memory and local butter memory.
There are three modes of operation, Remote Write, Remote
Read, or Send Packet.

co
o

SEND PACKET COMMAND

The Remote DMA channel can be automatically initialized
to transfer a single packet from the Receive Buffer Ring.
The CPU begins this transfer by issuing a "Send Packet"
Command. The DMA will be initialized to the value of the
Boundary Pointer register and the Remote By1e Count register pair (RBCRO, RBCR1) will be initialized to the value of
the Receive Byte Count fields found in the Buffer Header of
each packet. After the data is transferred, the Boundary
Pointer is advanced to allow the buffers to be used for new
receive packets. The Remote Read will terminate when the
Byte Count equals zero. The Remote DMA is then prepared
to read the next packet from the Receive Buffer Ring. If the
DMA pointer crosses the Page Stop register, it is reset to
the Page Start Address. This allows the Remote DMA to
remove packets that have wrapped around to the top of the
Receive Buffer Ring.

Two register pairs are used to control the Remote DMA, a
Remote Start Address (RSARO, RSAR1) and a Remote
Byte Count (RBCRO, RBCR1) register pair. The Start Address register pair point to the beginning of the block to be
moved while the By1e Count register pair are used to indicate the number of by1es to be transferred. Full handshake
logic is provided to move data between local buffer memory
and a bidirectional liD port.
REMOTE WRITE
A Remote Write transfer is used to move a block of data
from the host into local buffer memory. The Remote DMA
will read data from the liD port and sequentially write it to
local buffer memory beginning at the Remote Start Address.
The DMA address will be incremented and the Byte Counter
will be decremented after each transfer. The DMA is terminated when the Remote By1e Count register reaches a
count of zero.

o
.....
I

Z

en
Co)

....

I\)

co
o

o

.....
I

Note 1: In order for the NIC to correctly execute the Send Packet Command, the upper Remote Byte Count Register (RBCR1) must first
be loaded with OFH.
Note 2: The Send Packet command cannot be used with 68000 type proc-

essors.

10.0 Internal Registers
All registers are 8-bit wide and mapped into two pages
which are selected in the Command register (PSO, PS1).
Pins RAO-RA3 are used to address registers within each
page. Page registers are those registers which are commonly accessed during NIC operation while page 1 registers
are used primarily for initialization. The registers are partitioned to avoid having to perform two writelread cycles to
access commonly used registers.

REMOTE READ
A Remote Read transfer is used to move a block of data
from local buffer memory to the host. The Remote DMA will
sequentially read data from the local butter memory, beginning at the Remote Start Address, and write data to the 1/0
port. The DMA address will be incremented and the By1e
Counter will be decremented after each transfer. The DMA
is terminated when the Remote Byte Count register reaches
zero.
Remote DMA Autoinitialization from Buffer Ring

°

•
I

"0"

1-65

TLiF/9345-17

.- r------------------------------------------------------------------------------------------,

oo

10.0 Internal Registers

~

10.1 REGISTER ADDRESS MAPPING

0)

(Continued)

C')

(/)

Z
.......

.-

oo
0)
C')

CO

a..
C

TLlF/9345-18

10.2 REGISTER ADDRESS ASSIGNMENTS
Page 0 Address Assignments (PS1 = 0, PSO = 0)
RAO-RA3

RD

Page 1 Address Assignments (PSl
RAO-RA3

WR

RD

= 0, PSO = 1)
WR

OOH

Command (CR)

Command (CR)

OOH

Command (CR)

Command (CR)

01H

Current Local DMA
Address 0 (CLDAO)

Page Start Register
(PSTART)

01H

Physical Address
Register 0 (PARO)

Physical Address
Register 0 (PARO)

02H

Current Local DMA
Address 1 (CLDA 1)

Page Stop Register
(PSTOP)

02H

Physical Address
Register 1 (PAR1)

Physical Address
Register 1 (PAR1)

03H

Boundary Pointer
(BNRY)

Boundary Pointer
(BNRY)

03H

Physical Address
Register 2 (PAR2)

Physical Address
Register 2 (PAR2)

04H

Transmit Status
Register (TSR)

Transmit Page Start
Address (TPSR)

04H

Physical Address
Register 3 (PAR3)

Physical Address
Register 3 (PAR3)

05H

Number of Collisions
Register (NCR)

Transmit Byte Count
Register 0 (TBCRO)

05H

Physical Address
Register 4 (PAR4)

Physical Address
Register 4 (PAR4)

06H

FIFO (FIFO)

Transmit Byte Count
Register 1 (TBCR 1)

06H

Physical Address
Register 5 (PAR5)

Physical Address
Register 5 (PAR5)

07H

Interrupt Status
Register (ISR)

Interrupt Status
Register (ISR)

07H

Current Page
Register (CURR)

Current Page
Register (CURR)

08H

Current Remote DMA Remote Start Address
Address 0 (CRDAO)
Register 0 (RSARO)

08H

Multicast Address
Register 0 (MARO)

Multicast Address
Register 0 (MARO)

09H

Current Remote DMA Remote Start Address
Address 1 (CRDA 1)
Register 1 (RSAR1)

09H

Multicast Address
Register 1 (MARl)

Multicast Address
Register 1 (MAR 1)

OAH

Reserved

Remote Byte Count
Register 0 (RBCRO)

OAH

Multicast Address
Register 2 (MAR2)

Multicast Address
Register 2 (MAR2)

OBH

Reserved

Remote Byte Count
Register 1 (RBCR 1)

OBH

Multicast Address
Register 3 (MAR3)

Multicast Address
Register 3 (MAR3)

OCH

Receive Status
Register (RSR)

Receive Configuration
Register (RCR)

OCH

Multicast Address
Register 4 (MAR4)

Multicast Address
Register 4 (MAR4)

ODH

Tally Counter 0
(Frame Alignment
Errors) (CNTRO)

Transmit Configuration
Register (TCR)

ODH

Multicast Address
Register 5 (MAR5)

Multicast Address
Register 5 (MAR5)

OEH

Tally Counter 1
(CRC Errors)
(CNTR1)

Data Configuration
Register (DCR)

OEH

Multicast Address
Register 6 (MAR6)

Multicast Address
Register 6 (MAR6)

OFH

Tally Counter 2
(Missed Packet
Errors) (CNTR2)

Interrupt Mask
Register (IMR)

OFH

Multicast Address
Register 7 (MAR7)

Multicast Address
Register 7 (MAR7)

1-66

10.0 Internal Registers

C
."
c»

(Continued)

Co)

Page 2 Address Assignments (PS1
RAO-RA3

RD

WR

=

CD

1, PSO = 0)

RAO-RA3

RD

WR

o
~

...

.......

OOH

Command (CR)

Command (CR)

08H

Reserved

Reserved

z
en

01H

Page Start Register
(PSTART)

Current Local OMA
Address 0 (CLOAO)

09H

Reserved

Reserved

N

OAH

Reserved

Reserved

02H

Page Stop Register
(PSTOP)

Current Local OMA
Address 1 (CLOA 1)

03H

Remote Next Packet
Pointer

Remote Next Packet
Pointer

04H

Transmit Page Start
Address (TPSR)

Reserved

05H

Local Next Packet
Pointer

Local Next Packet
Pointer

06H

Address Counter
(Upper)

Address Counter
(Upper)

07H

Address Counter
(Lower)

Address Counter
(Lower)

OBH

Reserved

Reserved

OCH

Receive Configuration
Register (RCR)

Reserved

OOH

Transmit Configuration
Register (TCR)

Reserved

OEH

Data Configuration
Register (OCR)

Reserved

OFH

Interrupt Mask Register
(IMR)

Reserved

Co)

~
o

o,

...

Note: Page 2 registers should only be accessed for diagnostic purposes.
They should not be modified during normal operation.
Page 3 should never be modified.

II)

1-67

,...

g
...,

CD

10.0 Internal Registers

N

10.3 Register Descriptions

(/)

COMMAND REGISTER (CR)

C')

Z

......
,...

o
~

QCI

a.
C

(Continued)

OOH (READ/WRITE)

The Command Register is used to initiate transmissions, enable or disable Remote DMA operations and to select register
pages. To issue a command the microprocessor sets the corresponding bit(s) (RD2, RD1, RDO, TXP). Further commands may
be overlapped, but with the following rules: (1) If a transmit command overlaps with a remote DMA operation, bits RDO, RD1,
and RD2 must be maintained for the remote DMA command when setting the TXP bit. Note, if a remote DMA command is re-issued when giving the transmit command, the DMA will complete immediately if the remote byte count register has not been reinitialized. (2) If a remote DMA operation overlaps a transmission, RDO, RD1, and RD2 may be written with the desired values
and a "0" written to the TXP bit. Writing a "0" to this bit has no effect. (3) A remote write DMA may not overlap remote read
operation or visa versa. Either of these operations must either complete or be aborted before the other operation may start.
Bits PS 1, PSO, RD2, and STP may be set at any time.

7

6

5

4

3

2

1

0

I PS1 I PSO I RD2 I RD1 I RDO I TXP I STA I STP I
Bit

Symbol

DO

STP

Description
STOP: Software reset command, takes the controller offline, no packets will be received or
transmitted. Any reception or transmission in progress will continue to completion before
entering the reset state. To exit this state, the STP bit must be reset and the STA bit must be
set high. To perform a software reset, this bit should be set high. The software reset has
executed only when indicated by the RST bit in the ISR being set to a 1. STP powers up

high.
Note: If the NIC has previously been in start mode and the STP is set, both the STP and STA bits will remain set.

D1

STA

START: This bit is used to activate the NIC after either power up, or when the NIC has been
placed in a reset mode by software command or error, STA powers up low.

D2

TXP

TRANSMIT PACKET: This bit must be set to initiate transmission of a packet. TXP is
internally reset either after the transmission is completed or aborted. This bit should be set
only after the Transmit Byte Count and Transmit Page Start registers have been
programmed.

D3, D4, D5

RDO, RD1, RD2

REMOTE DMA COMMAND: These three encoded bits control operation of the Remote DMA
channel. RD2 can be set to abort any Remote DMA command in progress. The Remote Byte
Count Registers should be cleared when a Remote DMA has been aborted. The Remote
Start Addresses are not restored to the starting address if the Remote DMA is aborted.
RD1
RDO
RD2
0
0
0
Not Allowed
Remote Read
0
0
1
Remote Write (Note 2)
0
1
0
0
1
1
Send Packet
Abort/Complete Remote DMA (Note 1)
1
X
X
Note 1: If a remote DMA operation is aborted and the remote by1e count has not decremented to zero, PRO (pin 29,
DIP) will remain high. A read acknowledge (RACK) or a write acknowledge (WACK) will reset PRO low.

Note 2: For proper operation of the Remote Write DMA, there are two steps which must be performed before using
the Remote Write DMA. The steps are as follows:
i) Write a non-zero value into RBCRO.

ii) Set bits RD2, RD1, RDO to 0, 0, 1.

iii) Issue the Remote Write DMA command (RD2, RD1, RDO

D6,D7

PSO, PS1

= 0, 1, 0).

PAGE SELECT: These two encoded bits select which register page is to be accessed with
addresses RAO-3.
PS1
PSO
0
Register Page 0
0
Register Page 1
1
0
0
Register Page 2
1
1
1
Reserved

1-68

C

10.0 Internal Registers

"tJ

0)

(Continued)

IN

CD

o

10.3 Register Descriptions (Continued)
INTERRUPT STATUS REGISTER (ISR)

o

.....
I

07H (READ/WRITE)

This register is accessed by the host processor to determine the cause of an interrupt. Any interrupt can be masked in the
Interrupt Mask Register (IMR). Individual interrupt bits are cleared by writing a "1" into the corresponding bit of the ISA. The INT
signal is active as long as any unmasked signal is set, and will not go low until all unmasked bits in this register have been
cleared. The ISR must be cleared after power up by writing it with all 1's.
7

6

5

4

3

2

1

0

I RST I ROC I CNT IOVW I TXE I RXE I PTX I PRX I
Bit

Symbol

00

PRX

PACKET RECEIVED: Indicates packet received with no errors.

01

PTX

PACKET TRANSMITTED: Indicates packet transmitted with no errors.

02

RXE

RECEIVE ERROR: Indicates that a packet was received with one or more of the
following errors:
-CRC Error
-Frame Alignment Error
-FIFO Overrun
-Missed Packet

03

TXE

TRANSMIT ERROR: Set when packet transmitted with one or more of the
following errors:
-Excessive Collisions
-FIFO Underrun

04

OVW

OVERWRITE WARNING: Set when receive buffer ring storage resources have
been exhausted. (Local OMA has reached Boundary Pointer).

05

CNT

COUNTER OVERFLOW: Set when MSB of one or more of the Network Tally
Counters has been set.

06

ROC

REMOTE DMA COMPLETE: Set when Remote OMA operation has been
completed.

07

RST

RESET STATUS: Set when NIC enters reset state and cleared when a Start
Command is issued to the CR. This bit is also set when a Receive Buffer Ring
overflow occurs and is cleared when one or more packets have been removed
from the ring. Writing to this bit has no effect.
NOTE: This bit does not generate an interrupt, it is merely a status indicator.

Description

1-69

.......
Z

en

IN
N

"'oCD"'
o

.....
I

....

gen
.....
N

10.0 Internal Registers

(Continued)

10.3 Register Descriptions (Continued)

CO)

U)

Z

....

.......

oo

INTERRUPT MASK REGISTER (IMR)

OFH(WRITE)

The Interrupt Mask Register is used to mask interrupts. Each interrupt mask bit corresponds to a bit in the Interrupt Status
Register (ISR). If an interrupt mask bit is set an interrupt will be issued whenever the corresponding bit in the ISR is set. If any bit
in the IMR is set low, an interrupt will not occur when the bit in the ISR is set. The IMR powers up all zero.

en

CO)

CO

7

Q

-

a..

I

6

5

3

4

2

1

0

IRDCEICNTEIOVWEI TXEEI RXEEI PTXE I PRXEI

Bit

Symbol

DO

PRXE

PACKET RECEIVED INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when packet received.

D1

PTXE

PACKET TRANSMITTED INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when packet is transmitted.

D2

RXEE

RECEIVE ERROR INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when packet received with error.

D3

TXEE

TRANSMIT ERROR INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when packet transmission results in error.

D4

OVWE

OVERWRITE WARNING INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when Buffer Management Logic lacks sufficient buffers to
store incoming packet.

D5

CNTE

COUNTER OVERFLOW INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when MSB of one or more of the Network Statistics
counters has been set.

D6

RDCE

DMA COMPLETE INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when Remote DMA transfer has been completed.

D7

reserved

Description

reserved

1-70

C

10.0 Internal Registers

"'D

00

(Continued)

Co)

CQ

o

10.3 Register Descriptions (Continued)

DATA CONFIGURATION REGISTER (OCR)

o

OEH (WRITE)

This Register is used to program the NIC for 8- or 16-bit memory interface, select byte ordering in 16-bit applications and
establish FIFO thresh holds. The DCR must be initialized prior to loading the Remote Byte Count Registers. LAS is set on
power up.

IBit

Symbol

DO

WTS

5

6

7
!

FT1

!

4

3

FTO ! ARM!

LS

2

!

1

0

LAS ! BOS! WTS!

Description
WORD TRANSFER SELECT
0: Selects byte·wide DMA transfers
1: Selects word·wide DMA transfers
; WTS establishes byte or word transfers
for both Remote and Local DMA transfers
Note: When word·wide mode is selected, up to 32k words are addressable; AO remains low.

D1

BOS

BYTE ORDER SELECT
0: MS byte placed on AD15-AD8 and LS byte on AD7 -ADO. (32000, 8086)
1: MS byte placed on AD7 -ADO and LS byte on AD15-AD8. (68000)

D2

LAS

LONG ADDRESS SELECT
0: Dual 16-bit DMA mode.
1: Single 32-bit DMA mode.

; ignored when WTS is low

; When LAS is high, the contents of the Remote DMA registers RSARO,1 are issued as A16-A31
Power up high.
D3

LS

LOOPBACK SELECT
0: Loopback mode selected. Bits D1, D2 of the TCR must also be programmed for Loopback
operation.
1: Normal Operation

D4

AR

AUTOINITIALIZE REMOTE
0: Send Command not executed, all packets removed from Buffer Ring under program control.
1 : Send Command executed, Remote DMA autoinitialized to remove packets from Buffer ring.
NOTE: Send Command cannot be used with 68000 type processors.

D5, D6

FTO,FT1

FIFO THRESHOLD SELECT: Encoded FIFO threshhold. Establishes point at which bus is
requested when filling or emptying the FIFO. During reception, the FIFO threshold indicates the
number of bytes (or words) the FIFO has filled serially from the network before bus request
(BREQ) is asserted.
Note: FIFO threshold setting determines the DMA burst length.
RECEIVE THRESHOLDS
FT1
FTO
Word Wide
Byte Wide
1 Word
2 Bytes
0
0
4 Bytes
0
1
2 Words
1
4 Words
8 Bytes
0
12 Bytes
1
1
6 Words
During transmission, the FIFO threshold indicates the number of bytes (or words) the FIFO has
filled from the Local DMA before BREQ is asserted. Thus, the transmit threshold is 16 bytes, less
the receive threshold.

1-71

I
......
.......

Z

(J)
Co)

N

"""
o

CQ

o

I
......

10.0 Internal Registers

(Continued)

10.3 Register Descriptions (Continued)
TRANSMIT CONFIGURATION REGISTER (TCR)

ODH(WRITE)

The transmit configuration establishes the actions of the transmitter section of the NIC during transmission of a packet on the
network. LB1 and LBO which select loopback mode power up as O.

I

7

6

5

-

-

-

I

I

4

3

2

1

0

IOFSTI ATD I LB1 I LBO I CRcl

Bit

Symbol

Description

00

CRC

01,02

LBO,LB1

ENCODED LOOPBACK CONTROL: These encoded configuration bits set the type of loopback
that is to be performed. Note that loopback in mode 2 sets the LPBK pin high, this places the
StarLAN ENOEC in loopback mode. Also, 03 of OCR must be set to zero.
LB1
LB2
Normal Operation (LPBK = 0)
0
Mode 0
0
Internal Loopback (LPBK = 0)
Mode 1
0
1
Mode 2
0
External Loopback (LPBK = 1)
1
External Loopback (LPBK = 0)
Mode 3
1
1

03

ATD

AUTO TRANSMIT DISABLE: This bit allows another station to disable the NIC's transmitter by
transmission of a particular multicast packet. The transmitter can be re-enabled by resetting this
bit or by reception of a second particular multicast packet.
0: Normal Operation
1: Reception of multicast address hashing to bit 62 disables transmitter, reception of multicast
address hashing to bit 63 enables transmitter.

04

OFST

COLLISION OFFSET ENABLE: This bit modifies the backoff algorithm to allow prioritization of
nodes.
0: Backoff Logic implements normal algorithm.
1: Forces Backoff algorithm modification to 0 to 2 min(3 + n, 10) slot times for first three collisions,
then follows standard backoff. (For first three collisions station has higher average backoff delay
making a low priority mode.)

05

reserved

06

reserved

reserved

07

reserved

reserved

INHIBITCRC
0: CRC appended by transmitter
1: CRC inhibited by transmitter
; In loopback mode CRC can be enabled or disabled to test the CRC logic.

reserved

1-72

C

10.0 Internal Registers

"'tI
01)

(Continued)

W
<0

o

10.3 Register Descriptions (Continued)
TRANSMIT STATUS REGISTER (TSR)

o•

......

04H (READ)

This register records events that occur on the media during transmission of a packet. It is cleared when the next transmission is
initiated by the host. All bits remain low unless the event that corresponds to a particular bit occurs during transmission. Each
transmission should be followed by a read of this register. The contents of this register are not specified until after the first
transmission.

z
en
w
....,
-'="

<0

.

o

7

6

5

4

3

1

2

IOWCI COH I FU I CRS I ABT I COL I

-

0
I PTX I

Bit

Symbol

DO

PTX

01

reserved

02

COL

TRANSMIT COLLIDED: Indicates that the transmission collided at least once
with another station on the network. The number of collisions is recorded in the
Number of Collisions Registers (NCR).

03

ABT

TRANSMIT ABORTED: Indicates the NIC aborted transmission because of
excessive collisions. (Total number of transmissions including original
transmission attempt equals 16).

04

CRS

CARRIER SENSE LOST: This bit is set when carrier is lost during transmission
of the packet. Carrier Sense is monitored from the end of Preamble/Synch until
TXEN is dropped. Transmission is not aborted on loss of carrier.

05

FU

06

COH

CD HEARTBEAT: Failure of the transceiver to transmit a collision signal after
transmission of a packet will set this bit. The Collision Detect (CD) heartbeat
signal must commence during the first 6.4 I's of the Interframe Gap following a
transmission. In certain collisions, the CD Heartbeat bit will be set even though
the transceiver is not performing the CD heartbeat test.

07

OWC

OUT OF WINDOW COLLISION: Indicates that a collision occurred after a slot
time (51.2 I's). Transmissions rescheduled as in normal collisions.

Description
PACKET TRANSMITTED: Indicates transmission without error. (No excessive
collisions or FIFO underrun) (ABT = "0", FU = "0").

reserved

FIFO UNDERRUN: If the NIC cannot gain access of the bus before the FIFO
empties, this bit is set. Transmission of the packet will be aborted.

1·73

o

......

10.0 Internal Registers

(Continued)

10.3 Register Descriptions (Continued)
RECEIVE CONFIGURATION REGISTER (RCR)

OCH(WRITE)

This register determines operation of the NIC during reception of a packet and is used to program what types of packets to
accept.
7
6
5
4
3
2
1
0

I- I- I

MON

I

PRO

I

AM

I

AS

I

AR

I I
SEP

Bit

Symbol

00

SEP

Description

01

AR

ACCEPT RUNT PACKETS: This bit allows the receiver to accept packets that
are smaller than 64 bytes. The packet must be at least 8 bytes long to be
accepted as a runt.
0: Packets with fewer than 64 bytes rejected.
1: Packets with fewer than 64 bytes accepted.

02

AS

ACCEPT BROADCAST: Enables the receiver to accept a packet with an all 1's
destination address.
0: Packets with broadcast destination address rejected.
1: Packets with broadcast destination address accepted.

03

AM

ACCEPT MULTICAST: Enables the receiver to accept a packet with a multicast
address, all multicast addresses must pass the hashing array.
0: Packets with multicast destination address not checked.
1: Packets with multicast destination address checked.

04

PRO

PROMISCUOUS PHYSICAL: Enables the receiver to accept all packets with a
physical address.
0: Physical address of node must match the station address programmed in
PARO-PAR5.
1: All packets with physical addresses accepted.

05

MON

MONITOR MODE: Enables the receiver to check addresses and CRC on
incoming packets without buffering to memory. The Missed Packet Tally counter
will be incremented for each recognized packet.
0: Packets buffered to memory.
1: Packets checked for address match, good CRC and Frame Alignment but not
buffered to memory.

06

reserved

reserved

07

reserved

reserved

SAVE ERRORED PACKETS
0: Packets with receive errors are rejected.
1: Packets with receive errors are accepted. Receive errors are CRC and Frame
Alignment errors.

Note: 02 and 03 are "OR'd" together, i.e., if 02 and 03 are set the NIC will accept broadcast and multicast addresses as well as its own physical address. To
estsblish full promiscuous mode, bns 02, 03, and D4 should be set. In addition the multicast hashing array must be set to all l's in order to accept all multicast

addresses.

1-74

C

"tI

10.0 Internal Registers (Continued)

00

10.3 Register Descriptions (Continued)

o

RECEIVE STATUS REGISTER (RSR)

Co)

CO

o•

....

OCH (READ)

This register records status of the received packet. including information on errors and the type of address match, either
physical or multicast. The contents of this register are written to buffer memory by the OMA after reception of a good packet. If
packets with errors are to be saved the receive status is written to memory at the head of the erroneous packet if an erroneous
packet is received. If packets with errors are to be rejected the RSR will not be written to memory. The contents will be cleared
when the next packet arrives. CRC errors, Frame Alignment errors and missed packets are counted internally by the NIC which
relinquishes the Host from reading the RSR in real time to record errors for Network Management Functions. The contents of
this register are not specified until after the first reception.
7

6

I OFR I

DIS

5

I

PHY

3

4

1

0

I MPA I Fa I FAE I CRC I PRX I

Bit

Symbol

DO

PRX

PACKET RECEIVED INTACT: Indicates packet received without error. (Bits
CRC, FAE, Fa, and MPA are zero for the received packet.)

01

CRC

CRC ERROR: Indicates packet received with CRC error. Incrernents Tally
Counter (CNTR 1). This bit will also be set for Frame Alignment errors.

02

FAE

FRAME ALIGNMENT ERROR: Indicates that the incoming packet did not end
on a byte boundary and the CRC did not match at last byte boundary. Increments
Tally Counter (CNTRO).

03

Fa

FIFO OVERRUN: This bit is set when the FIFO is not serviced causing overflow
during reception. Reception of the packet will be aborted.

04

MPA

MISSED PACKET: Set when packet intended for node cannot be accepted by
NIC because of a lack of receive buffers or if the controller is in monitor mode
and did not buffer the packet to memory. Increments Tally Counter (CNTR2).

05

PHY

PHYSICAL/MULTICAST ADDRESS: Indicates whether received packet had a
physical or multicast address type.
0: Physical Address Match
1: Multicast/Broadcast Address Match

06

DIS

RECEIVER DISABLED: Set when receiver disabled by entering Monitor mode.
Reset when receiver is re-enabled when exiting Monitor mode.

07

OFR

DEFERRING: Set when CRS or COL inputs are active. If the tranceiver has
asserted the CD line as a result of the jabber, this bit will stay set indicating the
jabber condition.

Description

Note: Following coding applies to GRG and FAE bits
FAE CRC

, ,,
,
0
0

2

0

0

Type of Error
No Error (Good GRG and <6 Dribble Bits)
GRG Error
Illegal, will not occur
Frame Alignment Error and CRG Error

1-75

.......
Z

(f)
Co)
I\)
~

CO

.....
o

o

....

I

10.0 Internal Registers (Continued)
10.4 DMA REGISTERS
DMA Registers

z
.....
....

LOCAL DMA TRANSMIT REGISTERS
15
817
0

~

(TPSR)
(TBCRO ,1)

~

PAGE START I
I TRANSMIT BYTE COUNT

LOCAL
DMA
CHANNEL

I

LOCAL DMA RECEIVE REGISTERS
15
0
817
(PSTART)

PAGE START

(PSTOP)

PAGE STOP

(CURR)

CURRENT

(BRNY)
NOT
READABLE
(CLDAO ,I)

BOUNDARY

I

(RSARo,1)

(CRADO,1)

I

0

I

START ADDRESS
BYTE COUNT

I

I+-

CURRENT LOCAL DMA ADDRESS

REMOTE DMA REGISTERS
15
817

(RBCRO ,1)

I

RECEIVE BYTE COUNT

CURRENT REMOTE DMA ADDRESS

~

REMOTE
DMA
CHANNEL

IS

TL/F/9345-19

bytes in the source, destination, length and data fields. The
maximum number of transmit bytes allowed is 64k bytes.
The NIC will not truncate transmissions longer than 1500
bytes. The bit assignment is shown below:

The DMA Registers are partitioned into three groups; Trans·
mit, Receive and Remote DMA Registers. The Transmit registers are used to initialize the Local DMA Channel for transmission of packets while the Receive registers are used to
initialize the Local DMA Channel for packet Reception. The
Page Stop, Page Start, Current and Boundary registers are
used by the Buffer Management Logic to supervise the Re·
ceive Buffer Ring. The Remote DMA Registers are used to
initialize the Remote DMA.

7

6

543

2

1

0

TBCRll L151 L141 L1sl L121 L11 I L10 I L9 I L8 I

7

6

543

2

1

0

TBCROI L7 I L6 I L5 I L4 I LS I L2 I L1 I LO I

Note: In the figure above, registers are shown as a or 16 bits wide. Although
some registers are 16·bit internal registers. all registers are accessed
as a·bit registers. Thus the IS-bit Transmit Byte Count Register is
broken into two a·bit registers. TBCRO and TBCRI. Also TPSR,
PSTART, PSTOP, CURR and BNRY only check or control the upper a
bRs of address Information on the bus. Thus they are shifted to posi·
tions 15·8 in the diagram above.

10.6 LOCAL DMA RECEIVE REGISTERS
PAGE START STOP REGISTERS (PSTART, PSTOP)
The Page Start and Page Stop Registers program the start·
ing and stopping address of the Receive Buffer Ring. Since
the NIC uses fixed 256 byte buffers aligned on page boundaries only the upper eight bits of the start and stop address
are specified.

10.5 TRANSMIT DMA REGISTERS
TRANSMIT PAGE START REGISTER (TPSR)
This register points to the assembled packet to be transmit·
ted. Only the eight higher order addresses are specified
since all transmit packets are assembled on 256 byte page
boundaries. The bit assignment is shown below. The values
placed in bits D7-DO will be used to initialize the higher
order address (A8-A 15) of the Local DMA for transmission.
The lower order bits (A7-AO) are initialized to zero.

PSTART,PSTOP bit assignment

7

6

5

4

3

:~~~:T'I A151 A141 A1S1 A121 A11

2

IA10 I

o

BOUNDARY (BNRY) REGISTER

TPSRI A151 A141 A1S1 A121 All I Al0 I A9 I A8 I

This register is used to prevent overflow of the Receive
Buffer Ring. Buffer management compares the contents of
this register to the next buffer address when linking buffers
together. If the contents of this register match the next buff·
er address the Local DMA operation is aborted.

(A7-AO Initialized to zero)
TRANSMIT BYTE COUNT REGISTER 0,1 (TBCRO, TBCR1)

BNRyl A151 A141 A1SI A121 All I A10 I

Bit Assignment

7

6

5

4

3

2

1

0

7

These two registers indicate the length of the packet to be
transmitted in bytes. The count must include the number of

1-76

6

543

2

o

10.0 Internal Registers

(Continued)

CURRENT PAGE REGISTER (CURR)

10.8 PHYSICAL ADDRESS REGISTERS (PARO-PAR5)

This register is used internally by the Buffer Management
Logic as a backup register for reception. CURR contains the
address of the first buffer to be used for a packet reception
and is used to restore DMA pointers in the event of receive
errors. This register is initialized to the same value as
PSTART and should not be written to again unless the controller is Reset.
7
6
543
2
0

The physical address registers are used to compare the
destination address of incoming packets for rejecting or accepting packets. Comparisons are performed on a bytewide basis. The bit assignment shown below relates the sequence in PARO-PAR5 to the bit sequence of the received
packet.
07
06
D5
04
03
D2
01
DO

CURRI A151 A141 A131 A121 A11 I A10 I A9

PARO DA7

AS

CURRENT LOCAL DMA REGISTER 0,1 (CLDAO,1)
These two registers can be accessed to determine the current Local DMA Address.
7
6
5
432
0
CLDA11 A151 A141 A131 A121 A11 I A10 I A9

7

6

5

4

3

2

543

2

AS

DAO
DAS

PAR5 DA47 DA46 DA45 DA44 DA43 DA42 DA41 DA40
Destination Address

AO

Source

Note:
PIS
DAO

AS

AO

RBCR1IBC15IBC14IBC13IBC12IBC11IBC101 BC91 Bcsi

3

2

1

~
~

Preamble, Synch
PhysicallMulticast Bit

10.9 MULTICAST ADDRESS REGISTERS (MARO-MAR7)
The multicast address registers provide filtering of multicast
addresses hashed by the CRC logic. All destination addresses are fed through the CRC logic and as the last bit of
the destination address enters the CRC, the 6 most significant bits of the CRC generator are latched. These 6 bits are
then decoded by a 1 of 64 decode to index a unique filter bit
(FBO-63) in the multicast address registers. If the filter bit
selected is set, the multicast packet is accepted. The system designer would use a program to determine which filter
bits to set in the multicast registers. All multicast filter bits
that correspond to multicast address accepted by the node
are then set to one. To accept all multicast packets all of
the registers are set to all ones. Note: Although the hashing algorithm does not guarantee perfect filtering of
multicast address, it will perfectly filter up to 64 multicast addresses if these addresses are chosen to map
into unique locations in the multicast filter.

6.4.3.2 REMOTE BYTE COUNT REGISTERS (RBCRO,1)
7
6
5
4
3
2
1
0

4

DA2

PAR3 DA31 DA30 DA29 DA28 DA27 DA26 DA25 DA24

0

RSAROI A7 I A6 I A5 I A4 I A3 I A2 I A1

5

DA3

IP/SIDAOIDA1IDA2IDA31 ...... I DA461DA47ISAOI .. .

RSAR11 A151 A141 A131 A121 A11 I A10 I A9

6

DA4

PAR4 DA39 DA3S DA37 DA36 DA35 DA34 DA33 DA32

10.7 REMOTE DMA REGISTERS

7

DA5

PAR2 DA23 DA22 DA21 DA20 DA19 DA1S DA17 DA16

REMOTE START ADDRESS REGISTERS (RSARO,1)
Remote DMA operations are programmed via the Remote
Start Address (RSARO,1) and Remote Byte Count
(RBCRO,1) registers. The Remote Start Address is used to
point to the start of the block of data to be transferred and
the Remote Byte Count is used to indicate the length of the
block (in bytes).
7
6
543
2
0

6

DA6

0

CLDAOI A7 I A6 I A5 I A4 I A3 I A2 I A1

7

DA1

PAR1 DA15 DA14 DA13 DA12 DA11 DA10 DA9

0

RBCROI BC71 BC61 BC51 BC41 BC31 BC21 BC1 IBCol
Note:
RSARO programs the start address bits AO-A?
RSARI programs the start address bits AS-AI5.
Address incremented by two for word transfers, and by one for byte transfers.
Byte Count decremented by two for word transfers and by one for byte
transfers.
RBCRO programs LSB byte count.
RBCRI programs MSB byte count.

CURRENT REMOTE DMA ADDRESS (CRDAO, CRDA1)
The Current Remote DMA Registers contain the current address of the Remote DMA. The bit assignment is shown
below:
7
6
5
4
3
2
0
CRDA1j A151 A141 A131 A121 A11 I A10 I A9
7

6

5

4

3

2

CRDAOI A7

A6

A5

A4

A3

A2

' - _ _ _ _.J

TLlF/9345-20

AS
0

A1

SELECTED BIT
"0" = REJECT "1" = ACCEPT

AO

1-77

~

og
"'="
C\I

C")

t/)

z
......
~

g

r------------------------------------------------------------------------------------------,
10.0 Internal Registers

(Continued)

07

06

05

04

03

02

01

DO

NUMBER OF COLLISIONS (NCR)

MARO FB7

FB6

FB5

FB4

FB3

FB2

FB1

FBO

MAR1 FB15 FB14 FB13 FB12 FB11 FB10 FB9

FB8

This register contains the number of collisions a node experiences when attempting to transmit a packet. If no collisions are experienced during a transmission attempt, the
COL bit of the TSR will not be set and the contents of NCR
will be zero. If there are excessive collisions, the ABT bit in
the TSR will be set and the contents of NCR will be zero.
The NCR is cleared after the TXP bit in the CR is set.
765
4
3
2
1
0

MAR2 FB23 FB22 FB21 FB20 FB19 FB18 FB17 FB16

G)
C")

MAR3 FB31 FB30 FB29 FB28 FB27 FB26 FB25 FB24

a.

MAR4 FB39 FB38 FB37 FB36 FB35 FB34 FB33 FB32

co

C

MAR5 FB47 FB46 FB45 FB44 FB43 FB42 FB41 FB40

NCR

MAR6 FB55 FB54 FB53 FB52 FB51 FB50 FB49 FB48

I- \-

1 -

\ -

\ NC3\ NC2\ NC1 \ NCO \

MAR7 FB63 FB62 FB61 FB60 FB59 FB58 FB57 FB56

11.0 Initialization Procedures

If address Y is found to hash to the value 32 (20H), then
FB32 in MAR4 should be initialized to "1". This will cause
the NIC to accept any multicast packet with the address Y.

The NIC must be initialized prior to transmission or reception of packets from the network. Power on reset is applied
to the NIC's reset pin. This clears/sets the following bits:

NETWORK TALLY COUNTERS
Three 8-bit counters are provided for monitoring the number
of CRC errors, Frame Alignment Errors and Missed Packets. The maximum count reached by any counter is 192
(COH). These registers will be cleared when read by the
CPU. The count is recorded in binary in CTO-CT7 of each
Tally Register.

5

4

3

Set Bits

TXP, STA

RD2, STP

Interrupt Status (ISR)

Transmit Config. (TCR)

2

1

LAS
LB1,LBO

The NIC remains in its reset state until a Start Command is
issued. This guarantees that no packets are transmitted or
received and that the NIC remains a bus slave until all appropriate internal registers have been programmed. After
initialization the STP bit of the command register is reset
and packets may be received and transmitted.

0

CNTAO' CT7' CT61 CT51 CT41 CT31 CT21 CT1 , CTO

RST
All Bits

Data Control (DCR)

Frame Alignment Error Tally (CNTRO)

6

Reset Bits

Interrupt Mask (IMR)

This counter is incremented every time a packet is received
with a Frame Alignment Error. The packet must have been
recognized by the address recognition logic. The counter is
cleared after it is read by the processor.

7

Register
Command Register (CR)

I

Initialization Sequence
The following Initialization procedure is mandatory.

CRC Error Tally (CNTR1)
This counter is incremented every time a packet is received
with a CRC error. The packet must first be recognized by
the address recognition logic. The counter is cleared after it
is read by the processor.
765
432
1
0

1) Program Command Register for page 0 (Command Register = 21H)
2) Initialize Data Configuration Register (DCR)
3) Clear Remote Byte Count Registers (RBCRO, RBCR1)
4) Initialize Receive Configuration Register (RCR)

CNTR1' CT71 CT6\ CT5\ CT4\ CT31 CT21 CT1 1 CTO 1

5) Place the NIC in LOOPBACK mode 1 or 2 (Transmit Configuration Register = 02H or 04H)

Frames Lost Tally Register (CNTR2)

6) Initialize Recieve Buffer Ring: Boundary Pointer
(BNDRY), Page Start (PSTART), and Page Stop (PSTOP)

This counter is incremented if a packet cannot be received
due to lack of buffer resources. In monitor mode, this counter will count the number of packets that pass the address
recognition logic.
7
6
5
4
3
2
1
0

7) Clear Interrupt Status Register (ISR) by writing OFFH to it.
8) Initialize Interrupt Mask Register (IMR)
9) Program Command Register for page 1 (Command Register = 61 H)

CNTR21 CT71 CT61 CT51 CT41 CT31 CT21 CT1 1 CTO 1

i) Initialize Physical Address Registers (PARO-PAR5)
ii) Initialize Multicast Address Registers (MARO-MAR7)
iii) Initialize CURRent pointer

FIFO
This is an eight bit register that allows the CPU to examine
the contents of the FIFO after loopback. The FIFO will contain the last 8 data bytes transmitted in the loopback packet.
Sequential reads from the FIFO will advance a pOinter in the
FIFO and allow reading of all 8 bytes.
7
6
5
432
1
0

10) Put NIC in START mode (Command Register = 22H).
The local recieve DMA is still not active since the NIC is
in LOOPBACK.
11) Initialize the Transmit Configuration for the intended value. The NIC is now ready for transmission and reception.

FIFO 1 DB71 DB61 DB51 DB41 DB31 DB21 DB1 1 DBO 1
Note: The FIFO should only be read when the NIC has been programmed in
loopback mode.

1-78

11.0 Initialization Procedures

(Continued)
Before receiving packets, the user must specify the location
of the Receive Buffer Ring. This is programmed in the Page
Start and Page Stop Registers. In addition, the Boundary
and Current Page Registers must be initialized to the value
of the Page Start Register. These registers will be modified
during reception of packets.

When in word-wide mode with Byte Order Select low, the
following format must be used for the loopback packet.
MS BYTE (AD8-15)

SOURCE

12.0 Loopback Diagnostics

LENGTH

Three forms of local loopback are provided on the NIC. The
user has the ability to loopback through the deserializer on
the DPa390C-1 NIC. Because of the half duplex architecture of the NIC, loopback testing is a special mode of
operation with the following restrictions:
Restrictions During Loopback

~

2 bytes

DATA

~46tol500bytes

'--_ _C_R_C_ _--lAppended by NIC if CRC

~

SOURCE

WTS = "I"

BOS ="I"

CRC

(OCR

BITS)

r

MODE 3: Loopback to Hub (LB1 = 1, LBO = 1).
Packets can be transmitted to the Hub in loopback mode to
check all of the transmit and receive paths and the Hub
itself.

LENGTH

I

(OCR BITS)

If the loopback is through the NIC then the serializer is simply linked to the deserializer and the receive clock is derived
from the transmit clock.
MODE 2: Loopback Through the ENDEC (LB 1 = 1, LBO =
0).
Because of the method bits are clocked in during loopback,
RXC must not be active for more than 5 clocks after CRS
goes low. Failure to do so will result in false bits being
clocked Into the FIFO. This restriction also applies to
loopback mode 3.

"0" in TCR

MS BYTE (AOO-7)

DATA

I

BOS ="0"

Loopback Modes
MODE 1: Loopback Through the Controller (LB1 = 0, LBO
= 1).

DESTINATION

T

CRC

rL.i

To initiate a loopback the user first assembles the loopback
packet then selects the type of loopback using the Transmit
Configuration register bits LBO, LB 1. The transmit configuration register must also be set to enable or disable CRC generation during transmission. The user then issues a normal
transmit command to send the packet. During loopback the
receiver checks for an address match and if CRC bit in the
TCR is set, the receiver will also check the CRC. The last a
bytes of the loopback packet are buffered and can be read
out of the FIFO using the FIFO read port.

When in word-wide mode with Byte Order Select set, the
loopback packet must be assembled in the even byte locations as shown below. (The loopback only operates with
byte wide transfers.)

dol

T

rL.i

TLlF/9345-22

(6 bytes) Station Physical Address

LENGTH

roJ

DATA

Nole: When using loop back in word mode 2n bytes must be programmed in
TBCRO, 1. Where n ~ actual number of bytes assembled in even or
odd location.

SOURCE ADDRESS

LS BYTE (ADS-15)

rL.i

WTS = "I"

The FIFO is split into two halves, one used for transmission
the other for reception. Only a-bit fields can be fetched from
memory so two tests are required for 16-bit systems to verify integrity of the entire data path. During loopback the maximum latency from the assertion of BREQ to BACK is 2.0 /Jos.
Systems that wish to use the loopback test yet do not meet
this latency can limit the loopback packet to 7 bytes without
experiencing underflow. Only the last a bytes of the loopback packet are retained in the FIFO. The last a bytes can
be read through the FIFO register which will advance
through the FIFO to allow reading the receive packet sequentially.
DESTINATION ADDRESS

LS BYTE (ADO-7)

DESTINATION

r
roJ

Nole: In MODE I, CRS and COL lines are not indicated in any status register, but the NIC will still defer if those lines are active. In MODE 2.
COL is masked and in MODE 3 CRS and COL are not masked. It is
not possible to go directly between the loopback modes, it is necessary to return to normal operation (OOH) when changing modes.

TL/F/9345-21

Reading the Loopback Packet
The last eight bytes of a received packet can be examined
by a consecutive reads of the FIFO register. The FIFO
pOinter is incremented after the rising edge of the CPU's
read strobe by internally synchronizing and advancing the
pointer. This may take up to four bus clock cycles, if the
pointer has not been incremented by the time the CPU
reads the FIFO register again, the NIC will insert wait states.
Nole: The FIFO may only be read during Loopback. Reading the FIFO at
any other time will cause the NIC to malfunction.

1-79

~

~
N

(I)

tn
Z

'"
~

~

(I)

fc

r-----------------------------------------------------------------------------------------------,
12.0 Loopback Diagnostics (Continued)
Alignment of the Received Packet in the FIFO

NETWORK MANAGEMENT FUNCTIONS

Reception of the packet in the FIFO begins at location zero,
after the FIFO pointer reaches the last location in the FIFO,
the pointer wraps to the top of the FIFO overwriting the
previously received data. This process continues until the
last byte is received. The NIC then appends the received
byte count in the next two locations of the FIFO. The contents of the Upper Byte Count are also copied to the next
FIFO location. The number of bytes used in the loopback
packet determines the alignment of the packet in the FIFO.
The alignment for a 64-byte packet is shown below.

Network management capabilities are required for maintenance and planning of a local area network. The NIC supports the minimum requirement for network management in
hardware, the remaining requirements can be met with software counts. There are three events that software alone
cannot track during reception of packets: CRC errors,
Frame Alignment errors, and missed packets.

FIFO

FIFO

LOCATION

CONTENTS
LOWER BYTE COUNT

-+

Since errored packets can be rejected, the status associated with these packets is lost unless the CPU can access the
Receive Status Register before the next packet arrives. In
situations where another packet arrives very quickly, the
CPU may have no opportunity to do this. The NIC counts
the number of packets with CRC errors and Frame Alignment errors. 8-bit counters have been selected to reduce
overhead. The counters will generate interrupts whenever
their MSBs are set so that a software routine can accumulate the network statistics and reset the counters before
overflow occurs. The counters are sticky so that when they
reach a count of 192 (COH) counting is halted. An additional
counter is provided to count the number of packets NIC
misses due to buffer overflow or being offline.

First Byte Read
Second Byte Read

UPPER BYTE COUNT
UPPER BYTE COUNT
LAST BYTE
CRCl
CRC2
CRC3

Last Byte Read

CRC4

The structure of the counters is shown below:

For the following alignment in the FIFO the packet length
should be (N x 8) + 5 Bytes. Note that if the CRC bit in the
TCR is set, CRC will not be appended by the transmitter. If
the CRC is appended by the transmitter, the last four bytes,
bytes N-3 to N, correspond to the CRC.
FIFO

FIFO

LOCATION

CONTENTS

CRe ERRORS COUNTER

CNTR2

MISSED PACKETS COUNTER

I- WSBjDINTERRUPT
I- !.ISB
I- "SB

Additional information required for network management is
available in the Receive and Transmit Status registers.
Transmit status is available after each transmission for information regarding events during transmission.

First Byte Read

AR

Second Byte Read

BYTE N·2 (CRC2)

Typically, the following statistics might be gathered in software:

BYTE N·l (CRC3)
BYTE N (CRC4)
LOWER BYTE COUNT
UPPER BYTE COUNT

FRAME ALIGNMENT ERRORS COUNTER

CNTRl

TlIF/9345-23

BYTEN-4
BYTE N·3 (CRC1)

CHTRO

Traffic:

Frames Sent OK
Frames Received OK
Multicast Frames Received
Packets Lost Due to Lack of Resources
Retries/Packet

Errors:

CRC Errors
Alignment Errors
Excessive Collisions
Packet with Length Errors
Heartbeat Failure

Las1 Byte Read

UPPER BYTE COUNT

LOOPBACK TESTS
TestlngCRC

If CRC = 0 in the TCR, the NIC computes and appends a
4-byte FCS field to the packet as in normal operation. The
CRC will not be verified during reception in loopback mode.
The CRC must be read from the FIFO and verified by comparison to a previously computed value.
If CRC = 1, the NIC will not append a 4-byte FCS field. The
user must supply a pre-calculated CRC value and append it
to the transmitted packet.

1-80

C

."

13.0 Bus Arbitration and Timing

0)

W
CD

The NIC operates in three possible modes:

o

o

....

BUS MASTER (WHILE PERFORMING DMA)
BUS SLAVE (WHILE BEING ACCESSED BY CPU)
IDLE

I

Z

en
w

c::<::POR

N

""o
....o
CD

~J

STOP +
BUS SLAVE
(ACCESSED AS INT ERROR
PERIPHERAL)

I

START

BURST COfAPLETE

+ EfAPTY + FULL

TL/F/9345-24

The N IC powers up as a bus slave in the Reset State, the
receiver and transmitter are both disabled in this state. The
reset state can be reentered under three conditions, soft
reset (Stop Command), hard reset (RESET input) or an error
that shuts down the receiver or transmitter (FIFO underflow
or oveflow, receive buffer ring overflow). After initialization
of registers, the NIC is issued a Start command and the NIC
enters Idle state. Until the DMA is required the NIC remains
in an idle state. The idle state is exited by a request from the
FI Fa in the case of receive or transmit, or from the Remotel
DMA in the case of Remote DMA operation. After

acquiring the bus in a BREQ/BACK handshake the Remote
or Local DMA transfer is completed and the NIC reenters
the idle state.
DMA TRANSFERS TIMING

The DMA can be programmed for the following types of
transfers:
16 Bit Address, 8 Bit Data Transfer
16 Bit Address, 16 Bit Data Transfer
32 Bit Address, 8 Bit Data Transfer
32 Bit Address, 16 Bit Data Transfer
All DMA transfers use BSCK for timing. 16 Bit Address
modes require 4 BSCK cycles as shown below:

16 Bit Address, 8 Bit Data

Tl

T2

T3

T4

BSCK

ADO-7

AD8-15

ADSO

--<

AO-7

X'"'____D_AT_A_ _ _ _J~

--<'"'______

A_8-_15_ _ _ _ _ _...I~

- F \_________________
' .... ___--J/

1-81

TL/F/9345-25

,..

oo
..,en

r-------------------------------------------------------------------------------------~

13.0 Bus Arbitration and Timing

N

(Continued)

16 Bit Address, 16 Bit Data

C')

U)

Z

.....
,..

T1

oo

BSCK

CO

ADO-7

--{

AO-7

ADB-15

--{

AB-15

en
C')

D..

C

ADSO

--"

T4

T3

T2

X~------------>--­
X~------------>--DATA

DATA

,'--___---II

MWR,MRD

TL/F/9345-26

32 Bit Address, 8 Bit Data

I
~
T1-T4

BSCK

ADO-7

ADB-15

ADSl

--<

--<

T2

T3

T4

J>___

X

~________D_A_~__________

A16-23

X

A24-31

X'-______

AO-7

>___

A_B-_l_5_ _ _ _ _ _

~
---J

ADSO

Tl

~2~----------------------------------------~

------------~~;~

,~-------------------------------

,'----_--11

TLlF/9345-27

32 Bit Address, 16 Bit Data

I

T1-T4

T2

Tl

BSCK~
ADO-7

ADB-15

ADSl

--<
--<

A24-31

AO-7

AB-15

X
X

I

DATA

DATA

T4

I

>-->---

~
---J

ADSO

X
X

A16-23

T3

I

~2~------------------------------------~

-----------~~~
~2

,~----------------------------------'~

_____I
TLlF/9345-28

Note: In 32-bit address mode, ADSl is at TRI-STATE after the first

n- T4 states; thus,

1-82

a 4.7k pull-down resistor is required for 32-bit address mode.

r-----------------------------------------------------------------------.c

~

13.0 Bus Arbitration and Timing (Continued)
When in 32 bit mode four additional BSCK cycles are required per burst. The first bus cycle (Tl' - T4') of each burst
is used to output the upper 16 bit addresses. This 16 bit
address is programmed in RSARO and RSARI and pOints to
a 64k page of system memory. All transmitted or received
packets are constrained to reside within this 64k page.

w

transfer an exact burst of bytes programmed in the Data
Configuration Register (OCR) then relinquish the bus. If
there are remaining bytes in the FIFO the next burst will not
be initiated until the FIFO threshold is exceeded. If desired
the DMA can empty/fill the FIFO when it acquires the bus. If
BACK Is removed during the transfer, the burst transfer will
be aborted. (DROPPING BACK DURING A DMA CYCLE IS

FIFO BURST CONTROL

NOT RECOMMENDED.)

All Local DMA transfers are burst transfers, once the DMA
requests the bus and the bus is acknowledged, the DMA will

,~---

BREQ
BACK

~ ................
""'~>-------ONNEE' BURST

ADO-IS

where N

'--

--.,.,/

TL/F/9345-29

= 1,2,4, or 6 Words or N = 2,4,8, or 12 Bytes when in byte mode

INTERLEAVED LOCAL OPERATION

transfers. When the Local DMA transfer is completed the
Remote DMA will rearbitrate for the bus and continue its
transfers. This is illustrated below:

If a remote DMA transfer is initiated or in progress when a
packet is being received or transmitted, the Remote DMA
transfer will be interrupted for higher priority Local DMA

BACK

ADO-IS

,'----

',---...,,/

BREQ - - '

'-

\----r,

,

-------t<~~RE~~O~~!)~~~~~L~B~U~RS~T::~----_1~CKB
OEB

8/1}

[;16

M.---

~CK~------~y~------~ lORD
.DRQ
PRQ ~~----------+

1-83

TL/F/9345-31

8
~
....
.....
Z

~
N

....~

~

o

r------------------------------------------------------------------------------------------,

CI

13.0 Bus Arbitration and Timing

~

C'I

REMOTE READ TIMING

~

Z
.....

1) The DMA reads byte/word from local buffer memory and
writes byte/word into latch, increments the DMA address
and decrements the byte count (RBCRO,1).

a»

~

o
~
CIO

D.

C

(Continued)
Steps 1-3 are repeated until the remote DMA is complete.
Note that in order for the Remote DMA to transfer a byte
from memory to the latch, it must arbitrate access to the
local bus via a BREO, BACK handshake. After each byte or
word is transferred to the latch, BREO is dropped. If a Local
DMA is in progress, the Remote DMA is held off until the
local DMA is complete.

2) A Request Line (PRO) is asserted to inform the system
that a byte is available.
3) The system reads the port, the read strobe (RACK) is
used as an acknowledge by the Remote DMA and it goes
back to step 1.

---1

BREQ

\
I

BACK

\
<

ADD-IS

IBYTE/WORD

)

1\

AD50

'---1

MRD

'---1
I

PWR

PRQ

_

BYTE WRITTEN
TO LATCH

\

_ _ WAIT FOR _ _ _ BYTE READ
HOST
BY HOST

A Remote Write operation transfers data from the I/O port
to the local buffer RAM. The NIC initiates a transfer by requesting a byte/word via the PRO. The system transfers a
byte/word to the latch via lOW, this write strobe is detected
by the NIC and PRO is removed. By removing the PRO, the
Remote DMA holds off further transfers into the latch until
the current byte/word has been transferred from the latch,
PRO is reasserted and the next transfer can begin.

I

PRQ

TLlF/9345-32

1) NIC asserts PRO. System writes byte/word into latch.
NIC removes PRO.
2) Remote DMA reads contents of port and writes
byte/word to local buffer memory, increments address
and decrements byte count (RBCRO,1).

REMOTE WRITE TIMING

3) Go back to step 1.
Steps 1-3 are repeated until the remote DMA is complete.

\

'----I

WACK

I

BREQ

\

\

I

BACK

(

ADO-I 5

lBYTE/WORD

)

f\
LJ

ADSO
MWR

'----'

PRD
-

- B Y T E READ FROM LATCH
BY REMOTE DNA AND
WRITTEN TO LOCAL
BUFFER MEMORY

BYTE WRmEN TO
LATCH BY SYSTEM

1-84

TL/F/9345-33

13.0 Bus Arbitration and Timing

C
"'til
co

(Continued)

SLAVE MODE TIMING

ADSO is used to latch the address when interfacing to a
multiplexed, address data bus. Since the NIC may be a local
bus master when the host CPU attempts to read or write to
the controller, an ACK line is used to hold off the CPU until
the NIC leaves master mode. Some number of BSCK cycles
is also required to allow the NIC to synchronize to the read
or write cycle.

When CS is low, the NIC becomes a bus slave. The CPU
can then read or write any internal registers. All register
access is byte wide. The timing for register access is shown
below. The host CPU accesses internal registers with four
address lines, RAO-RA3, SRD and SWR strobes.

W
fD

o

....<;>
......
Z

~
N

"'o"
fD

<;>

....

---------c~~=~

_ ____"r_
____________
~

~

~r_

TLIF/9345-34

~_~r_
~

____________~r_
TL/F/9345-35

1-85

14.0 Preliminary Electrical Characteristics
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
-0.5Vt07.0V
Supply Voltage (Vecl
DC Input Voltage (VIN)
-0.5V to Vee + 0.5V
DC Output Voltage (VOUT)
-0.5VtoVee + 0.5V
- 65·C to + 150"C
Storage Temperature Range (T8TG)
Power Dissipation (PO)
500mW
260·C
Lead Temp. (TL) (Soldering, 10 sec.)
ESO rating (RZAP = 1.5k, CZAP = 120 pF)

1600V

Preliminary DC Specifications TA = o·c to 70"C Vee =
Symbol

Parameter

5V ± 5%, unless otherwise specified.

Conditions

Min

Max

Vee - 0.1
3.5

Units

VOH

Minimum High Level Output Voltage
(Note 1, 4)

IOH = -20/LA
IOH = -2.0mA

V
V

VOL

Minimum Low Level Output Voltage
(Note 1, 4)

IOl = 20/LA
IOl = 2.0mA

VIH

Minimum High Level Input Voltage
(Note 2)

2.0

V

VIH2

Minimum High Level Input Voltage
for RACK, WACK (Note 2)

2.7

V

Vil

Minimum Low Level Input Voltage
(Note 2)

0.8

V

VIl2

Minimum Low Level Input Voltage
For RACK, WACK (Note 2)

0.6

V

liN

Input Current

VI = Vee or GNO

-1.0

+1.0

/LA

loz

Maximum TRI·STATE
Output Leakage Current

VOUT = Vee or GNO

-10

+10

/LA

0.1
0.4

V
V

TXCK = 10MHz
RXCK = 10 MHz
BSCK = 20 MHz
40
mA
lOUT = O/LA
VIN = Vee or GNO
Note 1: These levels are tested dynamically using a IimHed amount of functional test patterns, please refer to Ae Test load.
Nota 2: Limited functional test pattems are performed at these Input levels. The majority of functional tests are performed at levels of 0 and 3 volts.
Note 3: This is measured with a O. t ".F bypass capaCitor between Vee and GND.
Note 4: The low drive CMOS compatible VOH and VOL limits are not tested directly. Detailed device characterization validates that this specification can be
guaranteed by testing the high drive TIL compatible VOL and VOH specHication.
lee

Average Supply Current
(Note 3)

1·86

c

;g

15.0 Switching Characteristics AC Specs DP8390C-1 Note: All Timing is Preliminary

:-bd_

~
o

Register Read (Latched Using ADSO)

o•

....
......
Z

(J)

rsh______________
Q-rsrsl-

cs

Co)

N

t:)

8•

....

/////

\.\\\

f4--

... t

rack I

ACK--------------~

rackh

I

--JrdZ

_ackdv

ADO-7---------------------------------------------------~::::JD~O-~7c:::::>_--------TLlF/9345-36

Symbol

Max

Min

Parameter

Units

rss

Register Select Setup to ADSO Low

10

ns

rsh

Register Select Hold from ADSO Low

13

ns

aswi

Address Strobe Width In

15

ackdv

Acknowledge Low to Data Valid

rdz

Read Strobe to Data TRI-STATE

rackl

Read Strobe to ACK Low (Notes 1, 2, 3)

rackh

Read Strobe to ACK High

rsrsl

Register Select to Slave Read Low,
Latched RSO-3 (Note 2)

ns

55
15

ns

70
n*bcyc
30

10

ns

+ 30

ns
ns
ns

Note 1: ACK is not generated until CS and llRD are low and the NIC has synchronized to the register access. The NIC will insert an integral number of Bus Clock
cycles until it is synchronized. In Oual Bus systems additional cycles will be used for a local or remote DMA to complete. Wait states must be issued to the CPU until
A(;K is asserted low.
Note 2: CS may be asserted before or aller llRD. If CS is asserted aller SRD, rackl is referenced from falling edge of CS.
Note 3: These IimHs include the RC delay inherent in our test method. These signals typically turn off within 15 ns, enabling other devices to drive these lines with
no contention.

1-87

15.0 Switching Characteristics

(Continued)

Register Read (Non Latched, ADSO = 1)
I
RAO-3

-rsrh--1

cs

\.\\\\.

'////

-rsrs-SRO

I--

...

rackl

-

trackh

I
l.--...j rdz

ACK

4----ackdv
00-7

ADO-7

TLlF/9345-37

Symbol

Parameter

Min

Register Select to Read Setup
(Notes 1, 3)

10

rsrh

Register Select Hold from Read

0

ackdv

ACK Low to Valid Data

rdz

Read Strobe to Data TRI-STATE
(Note 2)

rackl

Read Strobe to ACK Low (Note 3)

rsrs

15

Max

ns
ns

55

ns

70

ns

n*bcyc

30

rackh
Read Strobe to ACK High
Note 1: rsrs includes flow through time of latch.

Units

+ 30

ns
ns

Note 2: These limits inlcude the AC delay inherent in our test method. These signals typically turn off within 15 ns enabling other devices to drive these lines with
no contention.
Note 3: CS may be asserted before or after AAO-3, and SAD, since address decode begins when ACK is asserted. If CS is asserted after AAO-3, and SAD, rack1
is referenced from falling edge of CS.

1-88

15.0 Switching Characteristics (Continued)
Register Write (Latched Using ADSO)
I

I

RAO-3

AOSO

I-- rss -r-J rsh
r~
.~

cs

\.\\~

'////

I-rswsl-

SWR

t

ww

-

wackh

1

ACK

J rwdh

t=~rwds

-- wackl --

AOO-7

00-7
TL/F/9345-38

Symbol

Parameter

Min

Max

Units

rss

Register Select Setup to ADSO Low

10

ns

rsh

Register Select Hold from ADSO Low

17

ns

aswi

Address Strobe Width In

15

ns

rwds

Register Write Data Setup

20

ns

rwdh

Register Write Data Hold

21

ns

ww

Write Strobe Width from ACK

50

ns

wackh

Write Strobe High to ACK High

wackl

Write Low to ACK Low (Notes 1, 2)

rswsl

Register Select to Write Strobe Low

30
n*bcyc

10

ns

+ 30

ns
ns

Note 1: ACK is not generated until CS and SWR are low and the NIC has synchronized to the register access. In Dual Bus Systems additional cycles will be used
for a local DMA or Remote DMA to complete.

Note 2: CS may be asserted before or after SWR. If CS is asserted after SWR, wackl is referenced from falling edge of CS.

1-89

....

~

15.0 Switching Characteristics (Continued)

N

Register Write (Non Latched, ADSO = 1)

~

Z

.....
....

I
RAO-3

i

-rswh--!

cs

Q

\.
~l'IIw._

WW

SWR
~

-t

wackl

ACK

r--

ADO-7

wackh

I

rwds

I rwdh

00-7
TUF/9345-39

Symbol

Parameter

rsws

Register Select to Write Setup
(Note 1)

Min

Max

Units

15

ns

rswh

Register Select Hold from Write

0

ns

rwds

Register Write Data Setup

20

ns

rwdh

Register Write Data Hold

21

ns

wackl

Write Low to ACK Low
(Note 2)

wackh

Write High to ACK High

ww

Write Width from ACK

n'bcyc
30
50

+ 30

ns
ns
ns

Note 1: Assumes ADSO is high when RAO-3 changing.
Note 2: liCK is not generated until CS and SWR are low and the NIC has synchronized to the register access. In Dual Bus systems additional cycles will be used for
a local DMA or remote DMA to complete.

1-90

15.0 Switching Characteristics (Continued)
DMA Control, Bus Arbitration
T4

T1

T2

T3

T4

T1

T2

T4

T3

T1

T2

T3

T1

T4

T2

T3

T4

Tt

T2

T3

BREQ

~K

__4-__________~--~

-+....~I

A~O - -............- -........~--....~~~.~~....

AOO-t5---------------------1~.~_:_;_::~!_:_:_:_:_:_:_1__1<:~:)(:~~::>
NWR,WRD

--------------------~~~~-----~.~------~~
FIRST TRANSFER
IF BACK SEEN ON
FIRST T1.

I
----r--

FIRST TRANSFER
IF BACK NOT GIVEN
ON FIRST T1.

I

----I

LAST TRANSFER
TLiF /9345-40

Symbol

Parameter

Min

Max

Units

brqhl

Bus Clock to Bus Request High for Local DMA

43

brqhr

Bus Clock to Bus Request High for Remote DMA

38

brql

Bus Request Low from Bus Clock

backs

Acknowledge Setup to Bus Clock
(Note 1)

bccte

Bus Clock to Control Enable

60

ns

bcctr

Bus Clock to Control Release
(Notes 2, 3)

70

ns

ns
ns

50
2

ns
ns

Note 1: BACK must be setup before T1 aiter BREa is asserted. Missed setup will slip the beginning of the DMA by four bus clocks. The Bus Latency will influence
the allowable FIFO threshold and transfer mode (emptylfill vs exact burst transfer).
Note 2: During remote DMA transfers only, a single bus transfer is performed. During local DMA operations burst mode transfers are performed.
Note 3: These limits include the RC delay inherent in our test method. These signals typically turn off within 15 ns enabling other devices to drive these lines with

no contention.

1-91

15.0 Switching Characteristics

(Continued)

DMA Address Generation
T1' (NOTE 1)

T2'

T3'

T4'

T1

T2

T3

BSCK~"'--;' '--I~;--'\,U\J\
.... beh___ -bel

_

r"'" -

ADS1

beash ....

.~

beye
beadz

beasl

beash ....

ADSO

beadv
AOO-15

!-=ladS

.~

beasl

aswo-

c::a dh -

beadv

r-+ ads

A16-A31

+

-::j-adh

AO-A15

X

DATA
TLlF/9345-41

Symbol

Parameter

Min

Max

Units

50

500

ns

bcyc

Bus Clock Cycle Time
(Note 2)

bch

Bus Clock High Time

22.5

ns

bel

Bus Clock Low Time

22.5

ns

bcash

Bus Clock to Address Strobe High

34

bcasl

Bus Clock to Address Strobe Low

44

aswo

Address Strobe Width Out

bcadv

Bus Clock to Address Valid

bcadz

Bus Clock to Address TR I-STATE
(Note 3)

ads

Address Setup to ADSO/1 Low

adh

Address Hold from ADSO/1 Low

bch

t5

ns
ns
ns

45

ns

55

ns

bch - 15

ns

bcl- 5

ns

Note 1: Cycles T1', T2', T3', T4' are only issued for the first transfer in a burst when 32-bit mode has been selected.
Note 2: The rate of bus clock must be high enough to support transfers to/from the FIFO at a rate greater than the serial network transfers from/to the FIFO.
Note 3: These limits include the RC delay inherent in our test method. These Signals typically turn off within 15 ns, enabling other devices to drive these lines with
no contention.

1-92

C

"'U

15.0 Switching Characteristics

QI)

(Continued)

CAl

CD

o

(")

DMA Memory Read

I

I

Tt

I

T2

I

T3

I

T4

....•

I

Tt

Z

tn

BSCK

CAl
N

I- berl
ADSO

r'
-+

(")

asds I-

-+

AO-7

YIIIIIIII)

AD8-15
(8 BIT MODE)

..... dhlD A

AO-7XI

A8-A15

A8-15

YIIIIIIII)

Parameter

I/

rez I-

A8-15
-+

Symbol

dsada-

ds

-+

avrh

AD8-15
(1 6 BIT MODE)

.....

drw

MRD

ADO-7
(8. 16 BIT MODE)

.a:o.
CD
o

I-berh

d~ ~h
DATA

I-

Min

AO-15X/II
TLIF19345-42

Max

Units

berl

Bus Clock to Read Strobe Low

43

ns

bcrh

Bus Clock to Read Strobe High

40

ns

ds

Data Setup to Read Strobe High

25

ns

dh

Data Hold from Read Strobe High

0

ns

drw

DMA Read Strobe Width Out

2*bcye - 15

ns

raz

Memory Read High to Address TRI-STATE
(Notes 1. 2)

beh

+ 40

ns

asds

Address Strobe to Data Strobe

bel

+ 10

ns

dsada

Data Strobe to Address Active

avrh

Address Valid to Read Strobe High

bcyc - 10

ns

3*bcye - 15

ns

Note 1: During a burst A8-A15 are not TRI-STATE if byte wide transfers are selected. On the last transfer A8-A15 are TRI-STATE as shown above.
Note 2: These limits include the RC delay inherent in our test method. These signals typically turn off within bch
lines with no contention.

1-93

+ 15 ns, enabling other devices to drive these

....

o
~
N

15.0 Switching Characteristics (Continued)
DMA Memory Write

ell)

en
z
......

I

....

oo

BSCK

f

AOSO

I

T1

I

T2

bcwh

I-bcwl

Q)
ell)

o

I

TJ

I

T4

I

T1

4-

/""\
.....

asds I -

t.lWR
--aswd

AOO-7
(8, 16 BIT MODE)

AO-A7

A08-15
(8 BIT MODE)

w d s - wdh

XIII

DATA (00-07)

--

AO-A7XI
waz

AO-A15

XIII

I/

4-

A8-15

A8-A15
I - - - w d s - wdh

AOO-15
(16 BIT MODE)

4-

4-

DATA (00-015)

AO-A15X/ / /
TL/F/9345-43

Symbol
bewl

Parameter

Min

Max

Units

40

ns

40

ns

Bus Clock to Write Strobe Low

bewh

Bus Clock to Write Strobe High

wds

Data Setup to WR High

wdh

Data Hold from WR Low

waz

Write Strobe to Address TRI-STATE
(Notes 1, 2)

asds
aswd

2*beye - 30
bch

ns

+7

ns
beh

+ 40

ns

Address Strobe to Data Strobe

bel

Address Strobe to Write Data Valid

bel

+ 10
+ 30

ns

ns

Note 1: When using byte mode transfers AB-A15 are only TRI-STATE on the last transfer, waz timing is only valid for last transfer in a burst.
Note 2: These limits include the RC delay inherent in our test method. These signals typically turn off within bch
lines with no contention.

1-94

+

15 ns, enabling other devices to drive these

r-----------------------------------------------------------------------,c
"'U
15.0 Switching Characteristics (Continued)

Q)
c.,)

CD

C)

~

Walt State Insertion
T1

T2

13

TW

.....
......

z

T4

en

BSCK

c.,)
I\)

~

ADSO

R~~

~
.....

________.........................~
TL/F/9345-44

Parameter

Min

ews

External Wait Setup to T3..l. Clock
(Note 1)

10

ns

ewr

External Wait Release Time
(Note 1)

15

ns

Symbol

Max

Units

Nota 1: The addition of wait.tates affects the count of deserialized bytes and is limHed to a number of bus clock cycles depending on the bus clock and network
rates. The allowable waH states are found in the table below. (Assumas 1 Mbitisec data rate.)

The number of allowable wait states in byte mode can be calculated using:

'" of Walt States

BUSCK(MHz)

Byte Transfer

Word Transfer

1

0

1

2

2

4

4

6

9

8

13

19

*W(by1emodO) -

C.:::k -1)

#W

- Number of Walt States

tnw

- Network Clock Period

!bsck
- BSCK Period
Tha number of allowable waH states in word mode can be calculated using:
5tnw
)
#W(word modo) - ( 2tbsck- 1

Table assumes 1 MHz network clock.

1·95

15.0 Switching Characteristics (Continued)
Remote DMA (Read, Send Command)

I

I

T1

T2

I

T3

BSCK~~

K-J~

ADSO

S
t.lRD

---

~

\.

---

!-t>pwrl

S

I--bpwrh

S

PWR

-- ~'

PRQ

~

..... IS~

RACK

ADO-IS

(

AO-AI5

)

(

00-015

~

S

--

prql

r~

'---J
rakw

-

TLlF/9345-45

Max

Units

bpwrl

Bus Clock to Port Write Low

43

ns

bpwrh

Bus Clock to Port Write High

40

ns

prqh

Port Write High to Port
Request High (Note 1)

30

ns

prql

Port Request Low from
Read Acknowledge High

45

ns

rakw

Remote Acknowledge
Read Strobe Pulse Width

Symbol

Parameter

Min

20

Note 1: Start of next transfer is dependent on where RACK is generated relative to BSCK and whether a local DMA is pending.

1-96

ns

o"U

15.0 Switching Characteristics (Continued)

CCI

Co)

CQ

.....
o

o

Remote DMA (Read, Send Command) Recovery Time

(~~i---V ~

I

I

T1

T2

I

I

T3

BSCK

T4

I

~

.......

z
en
Co)

N

"050--1\
"'0
PWR

-

s
'\
_~PWt1
~

ss--f\
sS

r---'S

-~
~

PRO

Ss

S

~s

\
\

~s

CQ

~s

~s

s~s

RACK

""o
....o•

ss
~s

\...

rhpwh

s~

.. k.

ADO-IS

AO-A15

00-015

S

S

AO-AI5

00-015

S
TL/F/9345-46

Symbol

Parameter

Min

Max

Units

bpwrl

Bus Clock to Port Write Low

43

ns

bpwrh

Bus Clock to Port Write High

40

ns

prqh

Port Write High to Port
Request High (Note 1)

30

ns

prql

Port Request Low from
Read Acknowledge High

45

ns

rakw

Remote Acknowledge
Read Strobe Pulse Width

20

ns

rhpwh

Read Acknowledge High to
Next Port Write Cycle
(Notes 2, 3, 4)

11

BUSCK

Note 1: Start of next transfer is dependent on where RACK is generated relative to BSCK and whether a local DMA is pending.

Note 2: This is not a measured value but guaranteed by design.
Note 3: RACK must be high for a minimum of 7 BUSCK.

Note 4: Assumes no local DMA interleave, no CS, and immediate BACK.

1·97

.,...

og

15.0 Switching Characteristics (Continued)

'0:1'
N

Remote DMA (Write Cycle)

CO)

U)

Z

~~I

......
.,...

g

I

T2

I

T3

T4

~~

BSCK""""--.

CD
CO)

CO

a..

ADSO

Q

/

MWR

~

PRO

PRQ

WACK

ADO-IS

--

't
--- I.:'

~

Cbprqh

I

---

~
wackw

bprdh-

bprdl

-1-

S
-wprql

S

r(

AO-AIS

X

)-

DO-DIS

TL/F/9345-47

Symbol
bprqh

Parameter

Min

Bus Clock to Port Request High
(Note 1)

Max

Units

42

ns

45

ns

wprql

WACK to Port Request Low

wackw

WACK Pulse Width

bprdl

Bus Clock to Port Read Low
(Note 2)

40

ns

bprdh

Bus Clock to Port Read High

40

ns

20

ns

Note 1: The first port request is issued in response to the remote write command. It is subsequently issued on T1 clock cycles following completion of remote DMA
cycles.

Note 2: The start of the remote DMA write following WACK is dependent on where WACK is issued relative to BUSCK and whether a local DMA is pending.

1-98

C

15.0 Switching Characteristics

"U
(X)
Co)

(Continued)

CO

o

Remote DMA (Write Cycle) Recovery Time

~~4

ITlIT2

H~

BSCK_

<:'
....

......
Z

CJ)

...,
~
o
Co)

F\.

AoSO

I\.

MWR

/

_

bprdh~

bprdl

~

PRO

wprq

PRO~

....
I

t::r

I,I

)

tbPrqh

I
I

1:1

twprql

I~

WACK
i=:WBCkwd

(

ADO-IS

AO-AI5

X

DO-DIS

HI
TL/F/9345-48

Symbol

Parameter

Min

Max

Units

40

ns

bprqh

Bus Clock to Port Request High
(Note 1)

wprql

WACK to Port Request Low

wackw

WACK Pulse Width

bprdl

Bus Clock to Port Read Low
(Note 2)

40

ns

bprdh

Bus Clock to Port Read High

40

ns

wprq

Remote Write Port Request
to Port Request Time
(Notes 3, 4, 5)

45

ns
ns

20

12

BUSCK

Note 1: The first port request is issued in response to the remote write command. It is subsequently issued on T1 clock cycles following completion of remote DMA
cycles.
Note 2: The start of the remote DMA write following WACK is dependent on where WACK is issued relative to BUSCK and whether a local DMA is pending.

Note 3: Assuming wackw < 1 BUSCK, and no local DMA interleave, no CS, immediale BACK, and WACK goes high before T4.
Note 4: WACK must be high for a minimum of 7 BUSCK.
Note 5: This is not a measured value but guaranteed by design.

1-99

15.0 Switching Characteristics (Continued)
Serial Timing-Receive (Beginning of Frame)

TL/F/9345-49

Symbol

Parameter

Min

Units

Max

rch

Receive Clock High Time

400

rcl

Receive Clock Low TIme

400

rcyc

Receive Clock Cycle Time

800

rds

Receive Data Setup Time to
Receive Clock High (Note 1)

20

ns

rdh

Receive Data Hold Time from
Receive Clock High

19

ns

pts

First Preamble Bit to Synch
(Note 2)

8

rcyc
cycles

ns
ns
ns

1200

Nole 1: All b~s entering NIC musl be properly decoded, fflhe PLL Is slill locking, Ihe clock to the NIC should be disabled orCRS delayed. Any two sequential 1 data
b~ will be Interpreted as Synch.
Note 2: This Is a minimum requirement which allows reception of a packet.

Serial Timing-Receive (End of Frame)
RXC\.

-

r\.

-

F~~~

/\

-l

'-ftcsrl

~

CRS

\ \ \ \ \

\~

---"'\X~--. . . )eiit~~V'7i\

RXD::X BIT N-l

BIT N

"

r-

tllg

_I

______

-J;-----rxrck - - - . ;

~

I

. i'

TLlF/9345-50

Symbol

Parameter

Min

Max

Units
rcyc
cycles

rxrck

Minimum Number of Receive Clocks
after CRS Low (Note 1)

tdrb

Maximum of Allowed Dribble Bits/Clocks
(Note 2)

3

rcyc
cycles

tifg

Receive Recovery Time
(Notes 4, 5)

40

rcyc
cycles

tcrsl

Receive Clock to Carrier Sense Low
(Note 3)

1

rcyc
cycles

5

0

Note 1: The NIC requires a minimum number of receive clocks following the deassertion of carrier sense (CRS). These additional clocks are provided by the
DP8391 SNI. If other decoder/PLLs are being used additional clocks should be provided. Short clocks or gUtches are not allowed.
Note 2: Up to 5 bits of dribble bits can be tolerated without resulting in a receive error.
Note 3: Guarantees to only load bH N, additional bits up to tdrb can be tolerated.
Note 4: This is the time required for the receive state machine to complete end of receive processing. This parameter Is not measured but Is guaranteed by design.
This is not a measured parameter but is a design requirement.
Nole 5: CRS must remain d....erted for a minimum of 2 RXC cycles to be recognized as end of carrier.

1-100

C

"'0

15.0 Switching Characteristics (Continued)

00

w
CD
o

n,

....

Serial Timing-Transmit (Beginning of Frame)

......

m~'::}:j~~
\xel I-beye - -

TXE

\xesdv-

~

TXO

Symbol

--

z

en
w

.,..
CD

I\)

o

-X

n,
....

r-txesdh

1

0

X

>OC

1

Parameter

Min

txch

Transmit Clock High Time

36

txcl

Transmit Clock Low Time

36

txcyc

Transmit Clock Cycle Time

800

txcenh

Max

TLlF/9345-51

Units
ns
ns

1200

ns

Transmit Clock to Transmit Enable High
(Note 1)

48

ns

txcsdv

Transmit Clock to Serial Data Valid

67

ns

txxsdh

Serial Data Hold Time from
Transmit Clock High

10

ns

Note 1: The NIC issues TXEN coincident with the first bit of preamble. The first bit of preamble is always a 1.

Serial Timing-Transmit (End of Frame, CD Heartbeat)

TXC~~~
I--

\eenl

TXE

TXO

BIT N-2

X

BIT N-l

BIT N

f

,

~

I

~

tedl

- - \dedh
COL

Symbol

Parameter

Min

~

TLlF/9345-52

Max

Units

tcdl

Transmit Clock to Data Low

55

ns

tcenl

Transmit Clock to TXEN Low

55

ns

tdcdh

TXEN Low to Start of Collision
Detect Heartbeat (Note 1)

64

txcyc
cycles

cdhw

Collision Detect Width

0
2

Note 1: If COL is not seen during the first 64 TX clock cycles following deassertion of TXEN, the CDH bit in the TSR is set.

1-101

txcyc
cycles

.,...

oo
0)

15.0 Switching Characteristics. (Continued)

"'1:1'

N

C')

Serial Timing-Transmit (Collision)

(f)

Z

.......
.,...

TXC

g
0)
C')

COL

CO

Q.

C

---Q'----~
i-------H"'---l-.~
tcdj------+l

TXE
TL/F/9345-53

Symbol

Parameter

Min

tcolw

Collision Detect Width

tcdj

Delay from Collision to First
Bit of Jam (Note 1)

tjam

Jam Period (Note 2)

Units

Max

txcyc
cycles

2

8

txcyc
cycles

32

txcyc
cycles

Note 1: The NIC must synchronize to collision detect. If the NIC is in the middle of serializing a byte of data the remainder of the byte will be serialized. Thus the jam
pattern will start anywhere from 1 to 8 TXC cycles after COL is asserted.
Note 2: The NIC always issues 32 bits of jam. The jam is all 1's data.

Reset Timing
BSCK

TXC

RESET

_________~~________________________......J
TL/F/9345-54

Symbol
rstw

Parameter

Min

Reset Pulse Width (Note 1)

Max

8

Units
BSCK Cycles or TXC Cycles
(Note 2)

Nole 1: The RESET pulse requires that BSCK and TXC be stable. On power up, RESET should not be raised until BSCK and TXC have become stable. Several
registers are affected by RESET. Consult the register descriptions for details.
Note 2: The slower of BSCK or TXC clocks will determine the minimum time for the RESET signal to be low.

If BSCK < TXC then RESET
If TXC

<

BSCK then RESET

~

B X BSCK

~

B X TXC

1-102

C

AC Timing Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Reference Levels
TRI-STATE Reference Levels
Output Load (See Figure below)

Capacitance TA = 25'C, f =

GNDto3.0V
5ns
1.3V
Float (a V) ± 0.5V

I
I

UNDER

TEST

-b

~

I)

Open for timing tests for push pull outputs.
GND for VOH test.

81 = Vee for High Impedance to active low and active low to High
Impedance measurements.
81

CIN

Input
Capacitance

7

15

pF

COUT

Output
Capacitance

CD

o

o
I

7

15

pF

CL ;;, 50 pf: + 0.3 ns/pF (for all outputs except TXE, TXD,
and LBK)

-~

51 ~ Vee for VOL test.
51

Unit

Output timings are measured with a purely capacitave load
for 50 pF. The following correction factor can be used for
other loads:

TLiF/9345-55

~

Max

......
......
Z

Co)
~

01:00
CD

o
o
......
I

Note 1: Cl = 50 pF, includes scope and jig capacitance.
Note 2: 51

Typ

DERATING FACTOR

RL=2.2K

~(NOTE

Description

Note: This parameter is sampled and not 100% tested.

~.---+-o~\\ ~
~Jlf
DEVICE

Co)

Parameter

(J)

S,(NOTE 2)

~-'--..

"'tIl

0)

1 MHz

= GND for High Impedance to active high and active high to

High Impedance measurements.

1-103

<
.,... ,----------------------------------------------------------------,
en

-.:t

N

C')

(I)

Z
.......

<
.,...

en
C')

~National

~ Semiconductor
DP8391A/NS32491A Serial Network Interface

co

a..
Q

General Description
The DP8391 A Serial Network Interface (SNI) provides the
Manchester data encoding and decoding functions for
IEEE 802.3 EthernetiCheapernet type local area networks.
The SNI interfaces the DP8390 Network Interface Controller
(NIG) to the Ethernet transceiver cable. When transmitting,
the SNI converts non-return-to-zero (NRZ) data from the
controller and clock pulses into Manchester encoding and
sends the converted data differentially to the transceiver.
The opposite process occurs on the receive path, where a
digital phase-locked loop decodes 10 Mbitls signals with as
much as ± 18 ns of jitter.
The DP8391 A SNI is a functionally complete Manchester
encoder/decoder including ECl like balanced driver and receivers, on board crystal oscillator, collision signal translator, and a diagnostic loopback circuit.
The SNI is part of a three chip set that implements the complete IEEE compatible network node electronics as shown
below. The other two chips are the DP8392 Coax Transceiver Interface (CTI) and the DP8390 Network Interface Controller (NIG).
Incorporated into the CTI are the transceiver, collision and
jabber functions. The Media Access Protocol and the buffer
management tasks are performed by the NIC. There is an
isolation requirement on signal and power lines between the
CTI and the SNI. This is usually accomplished by using a set
of miniature pulse transformers that come in a 16-pin plastic
DIP for signal lines. Power isolation, however, is done by
using a DC to DC converter.

Features
• Compatible with Ethernet II, IEEE 802.3 10base5 and
10base2 (Cheapernet)

• 10 Mb/s Manchester encoding/decoding with receive
clock recovery
• Patented digital phase locked loop (DPll) decoder requires no precision external components
• Decodes Manchester data with up to ± 18 ns of jitter
• loopback capability for diagnostics
• Externally selectable half or full step modes of operation at transmit output
• Squelch circuits at the receive and collision inputs reject noise
• High voltage protection at transceiver interface (16V)
• TTL/MaS compatible controller interface
• Connects directly to the transceiver (AUI) cable

Table of Contents
1.0 System Diagram
2.0 Block Diagram
3.0 Functional Description
3.1
Oscillator
3.2

Encoder
Decoder
3.3
3.4
Collision Translator
3.5
loopback
4.0 Connection Diagrams
5.0 Pin Descriptions
6.0 Absolute Maximum Ratings
7.0 Electrical Characteristics
8.0 Switching Characteristics
9.0 Timing and load Diagrams
10.0 Physical Dimensions

1.0 System Diagram
IEEE 802.3 Compatible EthernetlCheapernet Local Area Network Chip Set
COAX
CABLE

TRANSCEIVER OR MAU

STATION OR OTE

......

'1l/l/h
'11/,

TAP
OR

[r--

"6P839{A~

DP8392
COAX
TRANSCEIVER I.....
INTERFACE
0
"'-

TRANSCEIVER
CABLE
OR
AUI
(OPTIONAL)

SERIAL
NETWORK
I~IERFACE
'/1/,

DP8390
~

~

~

NETWORK
I.....
INTERFACE
~
CONTROllER

"'TLiF/9357-1

1-104

2.0 Block Diagram
TRANSCEIVER
CABLE

CONTROLLER
INTERFACE
RECEIVE DATA (RXD)
RECEIVE CLOCK (RXC)

RECEIVE
PAIR
(RX+,RX-)

CARRIER SENSE (CRS)

..-_+__+_

LOOP BACK(LBK)

20 104Hz XTAL
(XI.X2)

TRANSMIT
PAIR
(TX+, TX-)

TRANSMIT CLOCK (TXC)

TRANSMIT DATA (TXD)
TRANswrr ENABLE (TXE)
COLLISION
PAIR
(CD+,CD-)

MODE SELECT (SEL)
COLLISION DETECT (COL)
TL/F/9357-2

FIGURE 1

3.0 Functional Description
The SNI consists of five main logical blocks:
a) the oscillator-generates the 10 MHz transmit clock signal for system timing.

the transmitted frequency to exceed its 0.01 % tolerance.
The frequency marked on the crystal is usually measured
with a fixed shunt capacitance (CLl that is specified in the
crystal's data sheet. This capacitance for 20 MHz crystals is
typically 20 pF. The capacitance between the Xl and X2
pins of the SNI, of the PC board traces and the plated
through holes plus any stray capacitance such as the socket capacitance, if one is used, should be estimated or measured. Once the total sum of these capacitances is determined, the value of additional external shunt capacitance
required can be calculated. This capacitor can be a fixed
5% tolerance component. The frequency accuracy should
be measured during the design phase at the transmit clock
pin (TXC) for a given pc layout. Figure 2 shows the crystal
connection.

b) the Manchester encoder and differential output driveraccepts NRZ data from the controller, performs Manchester encoding, and transmits it differentially to the
transceiver.
c) the Manchester decoder-receives Manchester data
from the transceiver, converts it to NRZ data and clock
pulses, and sends them to the controller.
d) the collision translator-indicates to the controller the
presence of a valid 10 MHz signal at its input.
e) the loopback circuitry-when asserted, switches encoded data instead of receive input signals to the digital
phase-locked loop.

3.1 OSCILLATOR
The oscillator is controlled by a 20 MHz parallel resonant
crystal connected between Xl and X2 or by an external
clock on Xl. The 20 MHz output of the oscillator is divided
by 2 to generate the 10 MHz transmit clock for the controller. The oscillator also provides internal clock signals to the
encoding and decoding circuits.

Crystal Specification
Resonant frequency
Tolerance
Stability

Xl

-2-0t.l-H-z-I"--+" CL-CP

X2

J (NOTE I)

I

TL/F/9357-3

CL

~

Load capacitance specified by the crystal's manufacturer

CP = Total parasitic capacitance including:
a) SNI input capacitance between XI and X2 (typically 5 pF)
b) PC board traces, plated through holes, socket capacitances
Note I: When using a Viking (San Jose) VXB49N5 crystal, the external ca·
pacitor is not required, as the CL of the crystal matches the input
capacitance of the DP8391 A.

20 MHz
± 0.001 % at 25'C

FIGURE 2. Crystal Connection

±0.005% 0-70'C

3.2 MANCHESTER ENCODER AND DIFFERENTIAL
DRIVER
The encoder combines clock and data information for the
transceiver. Data encoding and transmission begins with the
transmit enable input (TXE) going high. As long as TXE re-

Type

AT-Cut
Parallel Resonance
Circuit
The 20 MHz crystal connection to the SNI requires special
care. The IEEE 802.3 standard requires a 0.01 % absolute
accuracy on the transmitted signal frequency. Stray capacitance can shift the crystal's frequency out of range, causing

1-105

~

.,...
CI)

"="
C\I
CO)

(f)

z

::c
.,...
CI)
CO)

co

D..

C

r-------------------------------------------------------------------~

3.0 Functional Description

(Continued)

mains high, transmit data (TXO) is encoded out to the transmit-driver pair (TX±). The transmit enable and transmit data
inputs must meet the setup and hold time requirements with
respect to the rising edge of transmit clock. Transmission
ends with the transmit enable input going low. The last transition is always positive at the transmit output pair. It will
occur at the center of the bit cell if the last bit is one, or at
the boundary of the bit cell if the last bit is zero.

carrier sense (CRS) is asserted. Receive data (RXO) and
receive clock (RXC) become available typically within 6 bit
times. At this point the digital phase-locked loop has locked
to the incoming signal. The OP8391A decodes a data frame
with up to ± 18 ns of jitter correctly.
The decoder detects the end of a frame when the normal
mid-bit transition on the differential input ceases. Within one
and a half bit times after the last bit, carrier sense is de-asserted. Receive clock stays active for five more bit times
before it goes low and remains low until the next frame.
Figures 7, 8 and 9 illustrate the receive timing.

The differential line driver provides ECl like signals to the
transceiver with typically 5 ns rise and fall times. It can drive
up to 50 meters of twisted pair AUI Ethernet transceiver
cable. These outputs are source followers which need external 27011 pulldown resistors to ground. Two different
modes, full-step or half-step, can be selected with SEl input. With SEl low, transmit + is positive with respect to
transmit - in the idle state. With SEl high, transmit + and
transmit - are equal in the idle state, providing zero differential voltage to operate with transformer coupled loads.
Figures 4, 5 and 6 illustrate the transmit timing.

3.4 COLLISION TRANSLATOR
The Ethernet transceiver detects collisions on the coax ca·
ble and generates a 10 MHz Signal on the transceiver cable.
The SNI's collision translator asserts the collision detect
output (COL) to the OP8390 controller when a 10 MHz sig·
nal is present at the collision inputs. The controller uses this
signal to back off transmission and recycle itself. The collision detect output is de-asserted within 350 ns after the 10
MHz input signal disappears.

3.3 MANCHESTER DECODER
The decoder consists of a differential input circuitry and a
digital phase-locked loop to separate Manchester encoded
data stream into clock signals and NRZ data. The differential input should be externally terminated if the standard
7811 transceiver drop cable is used. Two 3911 resistors connected in series and one optional common mode bypass
capacitor would accomplish this. A squelch circuit at the
input rejects signals with pulse widths less than 5 ns (negative going), or with levels less than -175 mY. Signals more
negative than -300 mV and with a duration greater than
30 ns are always decoded. This prevents noise at the input
from falsely triggering the decoder in the absence of a valid
signal. Once the input exceeds the squelch requirements,

The collision differential inputs (+ and -) should be terminated in exactly the same way as the receive inputs. The
collision input also has a squelch circuit that rejects signals
with pulse widths less than 5 ns (negative going), or with
levels less than -175 mY. Figure 10 illustrates the collision
timing.
3.5 LOOPBACK FUNCTIONS
logic high at loopback input (lBK) causes the SNI to route
serial data from the transmit data input, through its encoder,
returning it through the phase-locked-loop decoder to reo
ceive data output. In loopback mode, the transmit driver is in
idle state and the receive and collision input circuitries are
disabled.

4.0 Connection Diagram
Top View
TRANSCEIVER
INTERFACE

CONTROLLER
INTERFACE

3
4
5
6
7

8
CL-Cp·

9
10
11
12

COL

CO+

RXD

CD-

CRS

RX+

RXC

RX-

SEL
GND
LBK
XI
X2
TXO
TXC
TXE

OP8391A
SNI

NC
Vee

24
COLLISION
O.OIj1F PAIR

23
22
21
20
19

RECEIVE
PAIR

18

Vee
17
CAP
16
NC
15
NC
14
TX+
13
TX-

I

O.OOIj1F MINIMUM
TRANSMIT
PAIR

270.0.

270.0.
*Refer to the Oscillator section

TL/F/9357-4

FIGURE3a
Order Number DP8391AN
See NS Package Number N24C
1-106

o"'U

PCC Connection Diagram

01)

W

(Q

.....

l>
.......
Z

39.0.

(f)

.::c.0.01 p.F

39.0.

U

X

0::

c:~SE::L_-I5
GND

(/)
0:::
C,)

0

+

...J

><
0
0:: (,)

Q
(,)

I

0

(,)

8

(Q
.....

RECEIVE
PAIR

+
a::

4321282726

25~R~X~--4

24

7

.,..

N

l>

X

•

W

COLLISION
PAIR

_ _ _ _ _ _<:J

NC

Vee

23

DP8391A
SNI

22
21

c:--=L;:::BK':""'-Il0

20
19

CAP

IO.001 p.F MINIMUM

CL-Cp·

NC

TLIF /9357-5

*Refer to the Oscillator section

FIGURE 3b
Order Number DP8391AV
NS Package Number V28A

1-107

c(

.,...
~

5.0 Pin Descriptions

C\I
C')

Pin No.

en

z......
c(
.,...
G)
C')

Name

(PCC)

1

1

COL

0

Collision Detect Output. A TTL/MOS level active high output. A 10 MHz
(+25%-15%) signal at the collision input will produce a logic high at COL
output. When no signal is present at the collision input, COL output will go low.

2

2

RXD

0

Receive Data Output. A TTL/MOS level signal. This is the NRZ data output
from the digital phase·locked loop. This signal should be sampled by the
controller at the rising edge of receive clock.

3

3

CRS

0

Carrier Sense. A TTL/MOS level active high signal. It is asserted when valid
data from the transceiver is present at the receive input. It is de-asserted one
and a half bit times after the last bit at receive input.

4

4

RXC

0

Receive Clock. A TTL/MOS level recovered clock. When the phase-locked loop
locks to a valid incoming signal a 10 MHz clock signal is activated on this output.
This output remains low during idle (5 bit times after activity ceases at receive
input).

5

5

SEL

I

6

6-9

GND

7

10

LBK

S

11

X1

I

Crystal or External Frequency Source Input (TTL).

9

12

X2

0

Crystal Feedback Output. This output is used in the crystal connection only. It
must be left open when driving X1 with an external frequency source.

10

13

TXD

I

Transmit Data. A TTL level input. This signal is sampled by the SNI at the rising
edge of transmit clock when transmit enable input is high. The SNI combines
transmit data and transmit clock signals into a Manchester encoded bit stream
and sends it differentially to the transceiver.

11

14

TXC

0

Transmit Clock. A TTL/MOS level 10 MHz clock signal derived from the 20
MHz oscillator. This clock signal is always active.

12

15

TXE

I

13
14

16
17

TXTX+

0

15
16

18

NC

17

19

CAP

18
19

20-23

VCC

20

24

NC

21
22

25
26

RXRX+

I

Receive Input. Differential receive input pair from the transceiver.

23
24

27
28

COCD+

I

Collision Input. Differential collision input pair from the transceiver.

f

c

Description

I/O

(DIP)

Mode Select. A TTL level input. When high, transmit + and transmit - outputs
are at the same voltage in idle state providing a "zero" differential. When low,
transmit + is positive with respect to transmit - in idle state.
Negative Supply Pins.

I

Loopback. A TTL level active high on this input enables the loopback mode.

Transmit Enable. A TTL level active high data encoder enable input. This signal
is also sampled by the SNI at the rising edge of transmit clock.
Transmit Output. Differential line driver which sends the encoded data to the
transceiver. These outputs are source followers and require 2700 pulldown
resistors to GNO.
No Connection.

0

Bypass Capacitor. A ceramic capacitor (greater than 0.001 ",F) must be
connected from this pin to GND.
Positive Supply Pins. A 0.1 ",F ceramic decoupling capacitor must be
connected across VCC and GND as close to the device as possible.
No Connection.

1-108

6.0 Absolute Maximum Ratings
Supply Voltage (Vce>

Recommended Operating
Conditions

7V

o to 5.5V

Input Voltage (TTL)
Input Voltage (differential)

+ 16V

-5.5 to

Output Voltage (differential)

o to 16V

Output Current (differential)

-40mA

Storage Temperature
Lead Temperature (soldering, 10 sec)

300°C
2.95W·

Package Power Rating for PCC at 25°C
Derate Linearly at the rate of 15.4 mW /'C

1.92W·

5V ± 5%

Ambient Temperature (DIP)
(PCC)

0° to 70°C
0° to 55°C

Note: Absolute maximum ratings are those values beyond
which the safety of the device cannot be guaranteed. They
are not meant to imply that the device should be operated at
these limits.

- 65' to 150°C

Package Power Rating for DIP at 25°C
(PC Board Mounted)
Derate Linearly at the rate of 23.8 mW /'C

Supply Voltage (Vce>

'For actual power dissipation of the device please refer to
Section 7.0.
ESD rating

2000V

7.0 Electrical Characteristics
Vcc

= 5V ± 5%, T A = O°C to 70'C for DIP and O°C to 55°C for PCC (Notes 1 & 2)

Symbol

Parameter

Min

Test Conditions

Max

Units

VIH

Input High Voltage (TTL)

2.0

VIHXla

Input High Voltage (X1)

No Series Resistor

2.0

Vcc-1.5

V

VIHXlb

Input High Voltage (Xl)

1k Series Resistor

2.0

V

VIL

Input Low Voltage (TTL and X1)

Vcc
0.8

IIH

Input High Current (TTL)
Input High Current (RX ± CD ±)

50
500

/J- A
/J- A

IlL

Input Low Current (TTL)
Input Low Current (RX ± CD ±)

-300
-700
-1.2

/J- A
/J- A
V

0.5

V

VCL

Input Clamp Voltage (TTL)

VOH

Ouptut High Voltage (TTL/MOS)

VOL

Output Low Voltage (TTL/MOS)

= Vcc
= Vcc
VIN = 0.5V
VIN = 0.5V
liN = -12mA
10H = -100 /J-A
10L = 8mA

V

VIN
VIN

V

3.5

los

Output Short Circuit Current (TTL/MOS)

VOO

Differential Output Voltage (TX ±)

78n termination, and
270n from each to GND
same as above

V

-40

-200

mA

±550

± 1200

mV

VOB

Diff. Output Voltage Imbalance (TX ±)

±40

mV

Vos

Diff. Squelch Threshold (RX ± CD ±)

-175

-300

mV

VCM

Difl. Input Common Mode Voltage (RX ± CD ±)

-5.25

5.25

V

Icc

Power Supply Current

270

mA

10Mbitls

8.0 Switching Characteristics Vcc =
Symbol

I

5V ± 5%, T A

= O°C to 70°C for DIP and O°C to 55°C for PCC (Note 2)

I

Parameter

Figure

I

Min

I

Typ

I

Max

I

Units

OSCILLATOR SPECIFICATION
X1 to Transmit Clock High

12

8

20

ns

X1 to Transmit Clock Low
tXTL
TRANSMIT SPECIFICATION

12

8

20

ns

42

tXTH

tTCd

Transmit Clock Duty Cycle at 50% (10 MHz)

12

tTCr

Transmit Clock Rise Time (20% to 80%)

12
12

50

58

%

8

ns

8

ns

tTC!

Transmit Clock Fall Time (80% to 20%)

tTos

Transmit Data Setup Time to Transmit Clock Rising Edge

4& 12

20

ns

tTDh

Transmit Data Hold Time from Transmit Clock Rising Edge

4& 12

0

ns

tTEs

Transmit Enable Setup Time to Trans. Clock Rising Edge

4& 12

20

ns

tTEh

Transmit Enable Hold Time from Trans. Clock Rising Edge

5 & 12

0

ns

Note 1: All currents into device pins are positive, all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.
Note 2: All

typicals are given

for

Vee

~

SV and

TA ~

2S'C.

1-109

8.0 Switching Characteristics
VCC

=

Symbol

5V ± 5%, T A

=

O°C to 70°C for DIP and O°C to 55°C for PCC (Note 2) (Continued)

I

I

Parameter

TRANSMIT SPECIFICATION (Continued)

I

Figure

Min

I

Typ

I

Max

I

Units

tTOd

Transmit Output Delay from Transmit Clock Rising Edge

4& 12

40

ns

tTOr

Transmit Output Rise Time (20% to 80%)

12

7

ns

tTO!

Transmit Output Fall Time (80% to 20%)

12

tTO'

Transmit Output Jitter

12

tTOh

Transmit Output High Before Idle in Half Step Mode

7
±0.25

5 & 12

Transmit Output Idle Time in Half Step Mode
tTOi
RECEIVE SPECIFICATION

ns
ns

200

ns

5& 12

800

ns

tRCd

Receive Clock Duty Cycle at 50% (10 MHz)

12

tRCr

Receive Clock Rise Time (20% to 80%)

12

tRC!

Receive Clock Fall Time (80% to 20%)

12

8

ns

tRDr

Receive Data Rise Time (20% to 80%)

12

8

ns

tRD!

Receive Data Fall Time (80% to 20%)

8

ns

tRDs

Receive Data Stable from Receive Clock Rising Edge

7 & 12

teSon

Carrier Sense Turn On Delay

7 & 12

50

tesoff

Carrier Sense Turn Off Delay

8,9 & 12

160

ns

tDAT

Decoder Acquisition Time

1.80

p.s

tDre'

Differential Inputs Rejection Pulse Width (Squelch)

tRd

Receive Throughput Delay

40

50

12

60

%

8

ns

±40

7

ns

0.6

7

5

8 & 12

ns

30

ns

150

ns

COLLISION SPECIFICATION
Collision Turn On Delay

10 & 12

50

ns

Collision Turn Off Delay
tCOlOf!
LOOPBACK SPECIFICATION

10 & 12

350

ns

tCOlon

tlBs

Loopback Setup Time

Loopback Hold Time
Note 2: All typicals are given for Vee ~ 5V and TA

tlBh

~

11

20

ns

11

0

ns

25°e.

9.0 Timing and Load Diagrams
TXC

I f I

I

I

1.5V

,

,

I I I I

--,, :--t TEs
,

+

1.5V

TXE

l-tTDh-1

t TDs

TXD

---.:

,
,

:F

I1.5V

,

+

I

I

I

I

I

1.5V

--I I-- trod

TX+/-

,
,

I

FIGURE 4. Transmit Timing - Start of Transmission

1-110

TL/F/9357-6

9.0 Timing and Load Diagrams (Continued)
TXC
----:

;.-......- t TEh

~
__1._~________________________

TXE

I

o

1

I

0

I

VIlliIIJ//JijI////////////IZ

TXD

,.-,.- - t T01 - - ",
,
,

:--t

TOh - - :

TX+/-

TLlF/9357-7

FIGURE 5. Transmit Timing· End of Transmission (last bit = 0)

TXC

TXE

I

o

1

1

I

VIIII)/)!)/Jl//////J1I1/!I/ij

I

TXD

TX+/-

I

~

I

1

----------------

I

0

I

1
TL/F/9357-8

FIGURE 6. Transmit Timing· End of Transmission (last bit = 1)

1·111

c(
.,...

~

9.0 Timing and Load Diagrams (Continued)

C'I

~

Z
;c

--I

FIRST BIT DECODED

111 0 1110111011101110111011101110111

Q;
C')
~

r-

RX+/- _ _ _---,

C

CRS

____--'+
--I

1.5v

I-tCSon

1.5V

RXC

I+j-- - tOAT -----I.j
RXD

TLIF/9357-9

FIGURE 7. Receive Timing· Start of Packet

11 10 11 10 10 1
RX+/-

. .---------------

IUlJlJ~---""~

-----I

I-- t CS off
~~_1_.5_V_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____

CRS

t Rd

:---

RXC

I--

5 EXTRA CLOCKS-1

TLlF/9357-10

FIGURE 8. Receive Timing· End of Packet (last bit = 0)

1-112

9.0 Timing and Load Diagrams (Continued)

I1 I0 I1 I0 I1 I
RX+/-

~-----------~~
~

--I

________________________________

I--- tCSoff

CRS

RXC

r--

5 EXTRA CLOCKS----1

RX0-u-L!U

I1I

0

I

1

I0 I1I
TL/F/9357-11

FIGURE 9. Receive Timing - End of Packet (last bit = 1)

CO+/-

---JLS1S-U
~

t COLon

I-

LtCOLOff

~-----

I

~S

COL

T

_ _ _ _ _ _ _........

+L_1_.5_V_ _ _ _ _ _ _ _ _ _ __

1.5V

TL/F/9357-12

FIGURE 10. Collision Timing

LBK

+.

______+
..

1.5V

LtLB'i

_1_o5_V_ _ _ _ _ ___

r-tLBh~

-------------,+. .

TXE __________________-J1Fr-1-o5-V

_1_o5_V______________________
TL/F/9357-13

FIGURE 11. Loopback Timing

TX+

270n

78 n

27 JLH*

TX270 n

TL/F/9357-14
*27 fLH transformer is used for testing purposes, 100 }.A-H transformers (Valor, LT1101, or Pulse Engineering 64103) are recommended for application use.

FIGURE 12. Test Loads

1·113

~National

~ Semiconductor
DP8392A/NS32492A Coaxial Transceiver Interface
General Description

Features

The DP8392A Coaxial Transceiver Interface (CTI) is a coaxial cable line driver/receiver for Ethernet/Thin Ethernet
(Cheapernet) type local area networks. The CTI is connected between the coaxial cable and the Data Terminal Equipment (DTE). In Ethernet applications the transceiver is usually mounted within a dedicated enclosure and is connected
to the DTE via a transceiver cable. In Cheapernet applications, the CTI is typically located within the DTE and connects to the DTE through isolation transformers only. The
CTI consists of a Receiver, Transmitter, Collision Detector,
and a Jabber Timer. The Transmitter connects directly to a
50 ohm coaxial cable where it is used to drive the coax
when transmitting. During transmission, a jabber timer is initiated to disable the CTI transmitter in the event of a longer
than legal length data packet. Collision Detection circuitry
monitors the signals on the coax to determine the presence
of colliding packets and signals the DTE in the event of a
collision.
The CTI is part of a three chip set that implements the complete IEEE 802.3 compatible network node electronics as
shown below. The other two chips are the DP8391 Serial
Network Interface (SNI) and the DP8390 Network Interface
Controller (NIC).
The SNI provides the Manchester encoding and decoding
functions; whereas the NIC handles the Media Access Protocol and the buffer management tasks. Isolation between
the CTI and the SNI is an IEEE 802.3 requirement that can
be easily satisfied on signal lines using a set of pulse transformers that come in a standard DIP. However, the power
isolation for the CTI is done by DC-to-DC conversion
through a power transformer.

• Compatible with Ethernet II, IEEE 802.3 10Base5 and
10Base2 (Cheapernet)
• Integrates all transceiver electronics except signal &
power isolation
• Innovative design minimizes external component count
• Jabber timer function integrated on chip
• Externally selectable CD Heartbeat allows operation
with IEEE 802.3 compatible repeaters
• Precision cirCUitry implements receive mode collision
detection
• Squelch circuitry at all inputs rejects noise
• Designed for rigorous reliability requirements of
IEEE 802.3
• Standard Outline 16-pin DIP uses a special leadframe
that significantly reduces the operating die temperature

Table of Contents
1.0
2.0
3.0
3.1
3.2
3.3
3.4
4.0
5.0
6.0
7.0

System Diagram
Block Diagram
Functional Description
Receiver and Squelch
Transmitter and Squelch
Collision and Heartbeat
Jabber Timer
Connection Diagram
Pin Descriptions
Absolute Maximum Ratings

Electrical Characteristics
8.0 Switching Characteristics
9.0 Timing and Load Diagram
10.0 Physical Dimensions

1.0 System Diagram
COAX
CABLE

TRANSCEIVER OR MAU

STATION OR OTE

I
S

TAP
ORBNC

o

DP8391

DP8390

T

SERIAL
NETWORK
INTERFACE

NETWORK
INTERFACE
CONTROLLER

L
A l+tf-----+H

I

o

TRANSCEIVER
CABLE

N

TL/F/7405-1

IEEE 802.3 Compatible EthernetlCheapernet Local Area Network Chip Set

1-114

2.0 Block Diagram

r ____-;:::::;;;;:=:-_______

COAX
CABLE

-;::-;:;-;:;~;;,;_-~DTE INTERFACE
RECEIVE
PAIR
(RX+. RX-)

HBE

10 MHz
OSCILLATOR

lXO
COLLISION

PAIR
(CO+. CD-)
TRANSWITIER
SQUELCH
GND

TRANSMITTER

TRANSMIT
PAIR

(TX+. TX-)

TL/F/7405-2

FIGURE 1. DP8392A Block Diagram

3.0 Functional Description
Receiver then stays off only if within about 1 p.s, the DC
level from the low pass filter rises above the DC squelch
threshold. Figure 2 illustrates the Receiver timing.
The differential line driver provides ECl compatible signals
to the DTE with typically 3 ns rise and fall times. In its idle
state, its outputs go to differential zero to prevent DC standing current in the isolation transformer.

The CTI consists of four main logical blocks:
a) the Receiver - receives data from the coax and sends it
to the DTE
b) the Transmitter - accepts data from the DTE and transmits it onto the coax
c) the Collision Detect circuitry - indicates to the DTE any
collision on the coax
d) the Jabber Timer - disables the Transmitter in case of
longer than legal length packets

3.2 TRANSMITTER FUNCTIONS
The Transmitter has a differential input and an open collector output current driver. The differential input common
mode voltage is established by the CTI and should not be
altered by external circuitry. The transformer coupling of
TX± will satisfy this condition. The driver meets all IEEE
802.3/Ethernet Specifications for Signal levels. Controlled
rise and fall times (25 ns V ± 5 ns) minimize the higher
harmonic components. The rise and fall times are matched
to minimize jitter. The drive current levels of the DP8392A
meet the tighter recommended limits of IEEE 802.3 and are
set by a built·in bandgap reference and an external 1 % resistor. An on chip isolation diode is provided to reduce the
Transmitter's coax load capaCitance. For Ethernet compatible applications, an external isolation diode (see Figure 4 )
may be added to further reduce coax load capaCitance. In
Cheapernet compatible applications the external diode is
not required as the coax capacitive loading specifications
are relaxed.
The Transmitter squelch circuit rejects signals with pulse
widths less than typically 20 ns (negative going), or with
levels less than -175 mY. The Transmitter turns off at the
end of the packet if the signal stays higher than -175 mV
for more than approximately 300 ns. Figure 3 illustrates the
Transmitter timing.

3.1 RECEIVER FUNCTIONS
The Receiver includes an input buffer, a cable equalizer, a
4-pole Bessel low pass filter, a squelch circuit, and a differential line driver.
The buffer provides high input impedance and low input ca·
pacitance to minimize loading and reflections on the coax.
The equalizer is a high pass filter which compensates for
the low pass effect of the cable. The composite result of the
maximum length cable and the equalizer is a flatband response at the signal frequencies to minimize jitter.
The 4-pole Bessel low pass filter extracts the average DC
level on the coax, which is used by both the Receiver
squelch and the collision detection circuits.
The Receiver squelch circuit prevents noise on the coax
from falsely triggering the Receiver in the absence of the
signal. At the beginning of the packet, the Receiver turns on
when the DC level from the low pass filter is lower than the
DC squelch threshold. However, at the end of the packet, a
quick Receiver turn off is needed to reject dribble bits. This
is accomplished by an AC timing circuit that reacts to high
level signals of greater than typically 200 ns in duration. The

1-115

•

I

3.0 Functional Description

(Continued)

3.3 COLLISION FUNCTIONS

The 10 MHz oscillator generates the signal for the collision
and heartbeat functions. It is also used as the timebase for
all the jabber functions. It does not require any external
components.
The collision differential line driver transfers the 10 MHz signal to the CD ± pair in the event of collision, jabber, or
heartbeat conditions. This line driver also features zero differential idle state.

The collision circuitry consists of two buffers, two 4-pole
Bessel low pass filters (section 3.1), a comparator, a heartbeat generator, a 10 MHz oscillator, and a differential line
driver.
Two identical buffers and 4-pole Bessel low pass filters extract the DC level on the center conductor (data) and the
shield (sense) of the coax. These levels are monitored by
the comparator. If the data level is more negative than the
sense level by at least the collision threshold (Vth), the collision output is enabled.
At the end of every transmission, the heartbeat generator
creates a pseudo collision for a short time to ensure that the
collision circuitry is properly functioning. This burst on collision output occurs typically 1.1 JLs after the transmission,
and has a duration of about 1 JLs. This function can be disabled externally with the HBE (Heartbeat Enable) pin to allow operation with repeaters.

3.4 JABBER FUNCTIONS
The Jabber Timer monitors the Transmitter and inhibits
transmission if the Transmitter is active for longer than
20 ms (fault). It also enables the collision output for the fault
duration. After the fault is removed, The Jabber Timer waits
for about 500 ms (unjab time) before re-enabling the Transmitter. The transmit input must stay inactive during the unjab
time.

RECEIVE
INPUT
FROM COAX

DC
TYPICALLY'
200 ns : _ :
TIMER"

DC
LOW PASS _ _ _ _..;!I..T_HR...ESHOLD
FILTER
OUTPUT

THRESHOLD
CHECK

+

t~,
----------5~"-------"7".~
S: TYPICALLY ,
J

I

RECEIVE
RECEIVER
ENABLE _ _ _ _ _T_U_R_N-_O_N..II

:~1p.s~:

-------------5555--------......,·1_ TURN-OFF
RECEIVER

jo.

RECEIVE
OUTPUT---------,
TO DTE
TL/F/7405-3

FIGURE 2. Receiver Timing

TRANSMIT
INPUT
FROM DTE

TRANSMm:~L~R~~D~~"':
(TYPICALLY 25 ns)

TRANSMIT
DRIVER
ENABLE

TRANSMITTER TURN-OFF - -, - - - - - - - - - - - :__

':

PULSE WIDTH ...,
(TYPICALLY 300 ns)
.

:--

~R~~S~I; S~:E~C~ -

J-

THRESHOLD

~----------~5Sr----------.

TRANSMIT
OUTPUT
TO COAX
TL/F17405-4

FIGURE 3. Transmitter Timing

1-116

~------------------------------------------------------~c

"'0

4.0 Connection Diagram

Q)

w

CD

~
......

OPTIONAL
TRANSCEIVER
CABLE

c
12 TO 15VDC

---

z

~
N

.---.

~~L

___

•• ••
••

•

"..
CD
N

+

DC TO DC
CONVERTER

:J>

9 V (ISOLATED)

500 OHM EACH

COLLISION
PAIR
D
T
E

--

.-

COAX

RECEIVE
PAIR

-

.-

~1

16

CD- 2

15

RX+ 3

~

Note 1: Tl is a 1:1 pulse transformer, L ~ 100,..H
Pulse Engineering (San Diego) Part No. 64103
Valor Electronics (San Diego)
Part No. 1101 or equivalent

CDS
TXO ........... IN916
RXI .......

1

VEE

4 DP8392A 13
RRCTI
12
RR+
6
11

~5
RX-

14

M=

lK 1%

J

TLlF/7405-5

Top View

Order Number DP8392AN
See NS Package Number N16A

FIGURE 4

III
I

1-117

5.0 Pin Descriptions
Pin No.

Name

1/0

Description

1
2

CD+'
CD-

0

Collision Output. Balanced differential line driver outputs from the collision detect
circuitry. The 10 MHz signal from the internal oscillator is transferred to these
outputs in the event of collision, excessive transmission Oabber), or during CD
Heartbeat condition. These outputs are open emitters; pulldown resistors to VEE
are required. When operating into a 780 transmission line, these resistors should
be 5000. In Cheapernet applications, where the 780 drop cable is not used,
higher resistor values (up to 1.5k) may be used to save power.

3
6

RX+'
RX-

0

Receive Output. Balanced differential line driver outputs from the Receiver. These
outputs also require 5000 pulldown resistors.

7
8

TX+'
TX-

I

Transmit Input. Balanced differential line receiver inputs to the Transmitter. The
common mode voltage for these inputs is determined internally and must not be
externally established. Signals meeting Transmitter squelch requirements are
waveshaped and output at TXO.

9

HBE

I

Heartbeat Enable. This input enables CD Heartbeat when grounded, disables it
when connected to VEE.

11
12

RR+
RR-

I

External Resistor. A fixed 1k 1 % resistor connected between these pins
establishes internal operating currents.

14

RXI

I

Receive Input. Connects directly to the coaxial cable. Signals meeting Receiver
squelch requirements are equalized for inter-symbol distortion, amplified, and
outputted at RX ±.

15

TXO

0

Transmit Output. Connects either directly (Cheapernet) or via an isolation diode
(Ethernet) to the coaxial cable.

16

CDS

I

Collision Detect Sense. Ground sense connection for the collision detect circuit.
This pin should be connected separately to the shield to avoid ground drops from
altering the receive mode collision threshold.

10

GND

Positive Supply Pin. A 0.1 J.'F ceramic decoupling capacitor must be connected
across GND and VEE as close to the device as possible.

4
5
13

VEE

Negative Supply Pins. In order to make full use of the 3.5W power dissipation
capability of this package, these pins should be connected to a large metal frame
area on the PC board. Doing this will reduce the operating die temperature of the
device thereby increasing the long term reliability.

• IEEE names for CO± - CI±, RX± - DI±, TX± - DO±

5.1 P.C.BOARDLAYOUT

VEE pins are to be connected to a copper plane which
should be included in the printed circuit board layout. Refer
to National Semiconductor application note AN-442 (EthernetlCheapernet Physical Layer Made Easy) for complete
board layout instructions.

The DP8392A package is uniquely designed to ensure that
the device meets the 1 million hour Mean Time Between
Failure (MTBF) requirement of the IEEE 802.3 standard. In
order to fully utilize this heat dissipation design, the three

1-118

C

6.0 Absolute Maximum Ratings (Note
Supply Voltage (VEE)

-12V

Package Power Rating at 25'C
(PC Board Mounted)
Derate linearly at the rate of 28.6 mW

3.5 Watts'
See Section 5

rc

Input Voltage

CD
N

Ambient Temperature

0' to 70'C
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

- 65' to 150'C

Lead Temp. (Soldering, 10 seconds)

QO
Co)

-9v ±5%

Supply Voltage (VEE)

Oto -12V

Storage Temperature

."

Recommended Operating
Conditions

1)

260'C

»
....
z
en
Co)

N

~

CD
N

»

>IoFor actual power dissipation of the device please refer to section 7.0,

7.0 Electrical Characteristics VEE
Symbol

= -9V ±5%, TA = 0't070'C(Notes2&3)

Parameter

Min

IEE1

Supply current out 01 VEE pin-non transmitting

IEE2

Supply current out of VEE pin-transmitting

IRXI

Receive input bias current (RXI)

-2

ITOC

Transmit output dc current level (TXO)

37

ITAC

Transmit output ac current level (TXO)

VCD

Collision threshold (Receive mode)

-1.45

VOD

Differential output voltage (RX ± , CD ± )

±550

VOC

Common mode output voltage (RX ± , CD ± )

-1.5

VOB

Dill. output voltage imbalance (RX ±, CD ± )

VTS

Transmitter squelch threshold (TX±)

Cx

Input capacitance (RXI)

RRXI

Shunt resistance-non transmitting (RXI)

RTXO

Shunt resistance-transmitting (TXO)

Max

Units

-85

-130

rnA

-125

-180

rnA

+25

/-,A

41

45

rnA

ITDC
-1.58

rnA

-1.53

±1200

mV

±28

-2.0

-175

-225

V

±40

mV

-300

mV
pF

Kfl

100
10

-9V ±5%, TA

Parameter

V

-2.5

1.2

8.0 Switching Characteristics VEE =
Symbol

Typ

Kfl

= 0' to 70'C (Note 3)
Fig

Min

Typ

Max

Units

tRON

Receiver startup delay (RXI to RX ±)

5 & 11

4

tRd

Receiver propagation delay (RXI to RX ± )

5 & 11

15

tRr

Differential outputs rise time (RX ± , CD ±)

5 & 11

4

tRI

Differential outputs lall time (RX ± , CD ± )

5 & 11

4

ns

tRJ

Receiver & cable total jitter

10

±2

ns

tTST

Transmitter startup delay (TX± to TXO)

6 & 11

1

tTd

Transmitter propagation delay (TX± to TXO)

6 & 11

25

tTr

Transmitter rise time -10% to 90% (TXO)

6 & 11

25

ns

tTl

Transmitter fall time -90% to 10% (TXO)

6 & 11

tTM

tTr and tTl mismatch

tTS

Transmitter skew (TXO)

tTON

Transmit turn-on pulse width at VTS (TX ±)

tTOFF
tCON

bits
50

ns
ns

bits
50

ns

25

ns

0.5

ns

±0.5

ns

6 & 11

20

ns

Transmit turn-off pulse width at VTS (TX ±)

6 & 11

250

ns

Collision turn-on delay

7 & 11

7

bits

tCOFF

COllision turn-ofl delay

7 & 11

ICD

Collision frequency (CD ±)

7 & 11

tcp

Collision pulse width (CD ±)

7 & 11

35

70

ns

tHaN

CD Heartbeat delay (TX ± to CD ±)

8 & 11

0.6

1.6

/-,S

tHW

CD Heartbeat duration (CD ±)

8 & 11

0.5

1.0

1.5

/-,S

lJA

Jabber activation delay (TX ± to TXO and CD ±)

9 & 11

20

29

60

ms

tJR

Jabber reset unjab time (TX ± to TXO and CD ±)

9 & 11

250

500

750

ms

8.0

20

bits

12.5

MHz

Note 1: Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits.
Note 2: All currents into device pins are positive, all currents out of device pins are negative. All voltages referenced to ground unless otherwise specified.

Note 3: All typicals are given lor VEE

~

-9V

and

TA ~

25'C.

1-119

-!

9.0 Timing and Load Diagrams
RXI
:...----IRON ----.~':

,

RX+/-

---------------------------~ ~
II

II

tRf --.: :~ ~: :..... tRr
TLlF17405-6

FIGURE 5. Receiver Timing

/'-----------,'~~
~--------------------,

TX+/-

V,VTS

:- ,

ITON --:

,
--,

tTST

:~ trOrF' ---.:

,-

TXO

TLlF/7405-7

FIGURE 6. Transmitter Timing

R= 1 k

INPUT STEP fUNCTION

J.

I
I

RXI
I
I

IC=510p,~'
II
_

I
I

RXI~max)

DP8392A
COLLISION
DETECTOR

COt
OUTPUT

RAND C NETWORK
SIMULATES WORST CASE
CABLE 98~ STEP RESPONSE
VCD (mln) _____

,
:....-- tcorf -----:
CD +/-

-------------------,

,

1/fCD --:

, ,
: - tcp
TL/FI740S-8

FIGURE 7. Collision Timing

TX+/-

Ul..J"""--------------------tHON----.. :.....--- t H W - :

CD+/- - - - - - - - - - - - - - - ;
TLlF/7405-9

FIGURE 8. Heartbeat Timing

1-120

9.0 Timing and Load Diagrams (Continued)

TX +1-

-11111111111111111111111111
: . . - - tJA

TXO

--+-:

- - - - - tJR - - - - - . :

1111111111111111

CD +1-

11111111111111111111111111111111111111111
TL/F/7405-10

FIGURE 9. Jabber Timing

INPUT SIGNAL
WITH 30n. RISE AND FALL TIt.tES

.----------.

: R= 1k
RXI
....-~M-....----+-~
I
I

I

DP8392A
RECEIVER

RXt
OUTPUT

L---I.~=~~p~!
RAND C NETWORK
SIt.tULATES WORST
CASE CABLE JITTER

YI1
I

I

I

I

I

I

........
I

I

t~J

I

Input jitter :-,;;

± 1 ns

RX ± Output jitter ,;;

± 7 ns

TL/F17405-11

Difference s;; ± 6 ns

FIGURE 10. Receive Jitter Timing

TRANSt.tIT OUTPUT

(TXO)

RECEIVE (RX!)

OR
COUISION (CDt)

510.0.

50j.lH·

78.0.

510.0.

TL/F/7405-12

"'The 50 JLH inductance is for testing purposes. Pulse transformers with higher inductances are recommended (see Figure 4)

FIGURE 11. Test Loads

1·121

,..

Q

~
N

CO)

,-------------------------------------------------------------------------,

~National

ADVANCE

INFORMATION

z

~ Semiconductor

Q)
CO)

DP83910/NS324910 CMOS Serial Network Interface

en
C)
,..

~

C

General Description
The DP83910 CMOS Serial Network Interface (SNI) is a direct-pin equivalent of the bipolar DP8391 and provides the
Manchester data encoding and decoding functions for IEEE
802.3 EthernetlThin-Ethernet type local area networks. The
SNI interfaces the DP8390 Network Interface Controller
(NIC) to the Ethernet transceiver cable. When transmitting,
the SNI converts non-return-to-zero (NRZ) data from the
controller and clock pulses into Manchester data and sends
the converted data differentially to the transceiver. Conversely, when receiving, a phase-locked loop decodes the
10 Mbitlsec data rate.
The DP83910 operates in conjunction with the DP8392 Coaxial Transceiver Interface (CTI) and the DP8390 Network
Interface Controller (NIC) to form a three-chip set that implements the complete IEEE 802.3 compatible network as
shown below. The DP83910 is a functionally complete Manchester encoder/decoder including a balanced driver and
receiver, on-board crystal oscillator, collision signal transla-

tor, and a diagnostic loopback feature. The DP83910, fabricated in low-power microCMOS, typically consumes less
than 100 mA.

Features
• Compatible with Ethernet II, IEEE 802.3 10base5 and
10base2 (Thin Ethernet)
• Functional and pin-out duplicate of the DP8381
• 10 Mbits/sec Manchester encoding/decoding with receive clock recovery
• Requires no precision components
• Decodes Manchester data with up to ± 20 ns of jitter
• Loopback capability for diagnostics
• Externally selectable half or full step modes of operation at transmit output
• Squelch circuitry at the receive and collision inputs reject noise
• TTL/MOS compatible controller interface
• Connects directly to the transceiver (AUI) cable

1.0 System Diagram
COAX
CABLE

T~~
BNC

DP8392
COAX
TRANSCEIVER
INTERfACE

TL/F/9365-l

2.0 Block Diagram
TRANSCEIVER
CABLE

r----------;::==::;::J..-A.

RECEIVE
PAIR
(RX+,RX-)

....--+----If--

CONTROLLER
INTERFACE
RECEIVE DATA(RXD)
RECEIVE CLOCK (RXC)
CARRIER SENSE (CRS)
LOOP BACK (LBK)

20 MHz XTAL

TRANSMIT
PAIR
(TX+, TX-)

+-+-----,."r

(Xl,X2)
~-I-"'~"\

TRANSMIT CLOCK (TXC)

TRANSMIT DATA (TXD)
TRANSMIT ENABLE (TXE)
COLLISION
PAIR
(CO+,CO-)

MODE SELECT (SEL)
COLLISION omCT (COL)
TLiF/9365-2

1-122

r------------------------------------------------------------------.~

~~

DP839EB Network
Evaluation Board

National Semiconductor
Application Note 479

OVERVIEW
The National Semiconductor DP839EB Evaluation Board
provides IBM® PCs and PC Compatibles with Ethernet,
Cheapernet and StarLAN connections. The evaluation
board is compatible with the PC-bus and requires only a V.
Size Slot for installation. The evaluation board utilizes National Semiconductor's Ethernet/Cheapernet chipset consisting of the DP8390 Network Interface Controller, the
DP8391 Serial Network Interface (SNI) and the DP8392 Coaxial Transceiver Interface (CTI). The DMA capabilities of
the DP8390, coupled with 8 kbytes of buffer RAM, allow the
Network Interface Adapter to appear as a standard I/O port
to the system.

NETWORK INTERFACE OPTIONS
The evaluation board supports three physical layer options:
Ethernet, Cheapernet and StarLAN. When using Ethernet, a
drop cable is connected to an external transceiver which is
connected to a standard Ethernet network. (See Figure 1).
When using Cheapernet, a low cost version of Ethernet, a
transceiver is available on-board allowing direct connection
to the network via the evaluation board. (See Figure 2).
When using a StarLAN network, an optional daughter card
replaces the SNI function and implements the required electronics to interface the DP8390 NIC to StarLAN. This configuration is illustrated in Figure 3. No software changes are
needed for conversion between any of the described configurations.

HARDWARE FEATURES

HARDWARE DESCRIPTION

• Half-Size IBM PC I/O Card Form Factor
• DP8390 Network Interface Controller with DMA
• 8 kby1e on-board Multipacket Buffer
•
•
•
•

Clean DMA Interface to IBM-PC
Ethernet Interface via 15-Pin D Connector
Cheapernet Interface via BNC Connector
StarLAN Support with Optional Daughter Card and 8-Pin
Modular Phone Jack

• DP8391 Serial Network Interface
• DP8392 Coaxial Transceiver Interface (For Cheapernet)
• Low Power Requirement
SOFTWARE FEATURES

• No Software changes for conversion between Ethernet!
Cheapernet and StarLAN
• Demonstration and diagnostic software available

The block diagram shown in Figure 4 illustrates the architecture of the Network Interface Adapter. The system/network
interface is partitioned at the DP8390 Network Interface
Controller (NIC). The NIC acts as both a master and a slave
on the local bus. During reception or transmission of packets, the NIC is a master. When accessed by the PC, the NIC
becomes a slave. The NIC utilizes a local 8-bit data bus
connected to an 8k x 8 Static RAM for packet storage. The
8k x 8 RAM is partitioned into a transmit buffer and a receive buffer. All outgoing packets are first assembled in the
packet buffer and then transmitted by the NIC. All incoming
packets are placed in the packet buffer by the NIC and then
transferred to the PC's memory. The transfer of data between the evaluation board and the PC is accomplished using the PC's DMA in conjunction with the NIC's Remote
DMA. Two LS374 latches implement a bidirectional I/O port
with the PC bus. The 8-bit transceiver (LS245) allows the PC
to access to the NIC's internal registers for programming. A
32 x 8 PROM located on the evaluation board contains the
unique Physical Address assigned to each board.

TL/F/9179-1

FIGURE 1. Ethernet Connection

1-123

~

.....
oo:t
:Z
c(

,-------------------------------------------------------------------~

STAR LAN DAUGHTER _______________
CARD INSTALLED
~

.---,.,,.....---......
a-WIRE
PHONE CABLE7
BNC
T CONNECTOR
MODULAR PHONE _______________
CONNECTOR
RJ-45
TL/F/9179-3

RG58

FIGURE 3. StarLAN Connector

TL/F/9179-2

FIGURE 2. Cheapernet Connector
LOCAL BUS

IBM PC BUS

A8-l5
OP8390
NIC
ETHERNET CTI

SNI

"""D~

AOO-7

1m;
7
3

::~~t:JI~N~ ~

AO-A12

00-07

____

AO-A4

00-07

TL/F/9179-4

FIGURE 4
Since the NIC is accessing 8-bit memory, only a single demultiplexing latch is required for the lower 8-bits of address.
An LS373 is provided for this purpose.

bursts and intervals. NLS is useful for performance measurement and debug of software drivers. NES, Network
Evaluation Software, consists of sample software drivers
implementing a low level interface to the evaluation board.

A 20L8 PAL provides the address decoding and support for
DMA handshaking and wait state generation.

LOCAL MEMORY MAP
The DP8390 NIC accesses an 8k x 8 buffer RAM located in
its 64 kbyte memory space. This buffer RAM is used for
temporary storage of receive and transmit packets. Data
from this RAM is transferred between the host (the PC) and
the evaluation board using the DP8390 NIC's remote DMA
channel. An ID address PROM, containing the physical address of the evaluation board is also mapped into the memory space of the NIC.

SOFTWARE SUPPORT

The evaluation board provides a simple programming interface for development of software. Several software packages are provided for evaluation and development of networks using the DP8390 Chip set. SDEMO is a demonstration program that provides a low level interface to the
DP8390 NIC for transmission and reception of packets.
SDEMO supports register dumps and simple register modification. CONF is a conferencing program which supports
simple message transfer. WORKSTAT and SERVER support file transfer between two nodes, one configured as a
server and a second configured as a workstation. NLS, Network Load Simulator, is a program that simulates network
loads based on statistical distributions of packet sizes,

Note: Partial decoding is performed on the PROM and RAM which will result
in these devices appearing at other locations in the 64k memory

space. The first occurrence of the PROM and RAM are used for programming purposes.

1-124

r--------------------------------------------------------------------.~

OOOOh
001fh

Address

PROM

•
•

OOh

2000h
3fffh

8kx 8
BUFFER RAM

01h

ADDRESS 1

02h

ADDRESS 2

•

•
•
•

03h

ADDRESS 3

04h

ADDRESS 4
ADDRESS 5
(Physical Address Least
Significant Byte)

05h

PROM FORMAT
Each evaluation board is assigned a unique network (physical) address. This address is stored in a 74S288 32 x 8
PROM. The physical address is followed by a checksum.
The checksum is calculated by exclusive OR-ing the 6 address bytes with each other. At initialization the software
reads the PROM, verifies the checksum and loads the NIC's
physical address registers. The following format is used in
the PROM:

•

""

......
co

ADDRESS 0
(Physical Address Most
Significant Byte)

•

ffffh

Z

Contents

06h

CHECKSUM
(XOR OF ADDRESS 0-5)
OPTIONAL

07h

REV. NUMBER

08h

MANUFACTURE LOT #

09h

MANUFACTURE
DATE (MONTH)

10h

MANUFACTURE
DATE (YEAR)

11h-1fh

RESERVED

15-pln
D connector

z

iQ

~

z

6

.1
J7C

J1C!EEB
J2C • • •

=>

~

R23

c:e::::::J:l

~I· ......... ·1
-IRQ- -DMA-

J3C!EEB
J4C • • •

J5C~
J6C
•••

ADD

I .............

P

1

U16

R14~

E!J

J7E

C4~

.0 0

~ ~

BNC

1

J2,---

U15

U14
J3

J4

,-E2
El

RJ-45

C21D

Modular Phone
Jack

~

131

TL/F/9179-5

FIGURES

1-125

I/O SPACE

SWITCH SETTINGS

The I/O space and EthernetlCheapernet configurations are
selected using the various I/O jumpers. There are 4 sets of
jumpers that should be programmed prior to installation of
the evaluation board into the PC environment. There are:
J4
I/O address, interrupt selection, DMA channel assignment
J 1C-J7C, J7E Select Ethernet or Cheapernet

Jumper J4 allows assignment of 110 Address Bases, DMA
channel assignments and Interrupt Request assignments.
The jumper configuration is shown below and described in
the following sections.

I: •• •• •• •• •• •• •• •• •• : I

Figure 5 depicts the location of the jumpers on the evaluation board.

The Factory Installed Configuration Is:
J4
I/O base = 300h
Interrupt = IRQ3
DMA = DREQ1, DACK1

+ OOh

•
Ofh

I

0

0

I

R

R

R

R

3

o

0

B

B

A
C

A
C

A

A

S

S

K
1

K
3

E

E

2

3
TLlF/9179-6

The 110 Base Address for DP8390B boards is fixed at 300h
and is not selectable.
INTERRUPTS
The NIC will generate interrupts based on received and
transmitted packets, completion of DMA and other internal
events. The interrupt can be connected to Interrupts 2, 3, 4
or 5 (IRQ 2,3,4,5) via Jumper J4. Interrupt 5 is also provided as a software driven DMA Channel. If Interrupt 5 is being
used as a DMA channel Interrupt 5 cannot be chosen for
the NIC interrupt. The figures below illustrate the jumper
positions for the various interrupt levels.
Interrupt 2

COMMAND REGISTER
NIC REGISTER
SPACE

•
•
•
•
•
•
•

10h

I/O PORTS

•

•
•

1fh

I

R

I/O BASE ADDRESS

The evaluation board uses 32 I/O locations in the PC's I/O
space. The base address is fixed at 300h and is not selectable using jumpers. (See Switch settings section.) The I/O
map is shown below:

01h
02h
03h
04h
05h
06h
07h

I

R

1

J1 C-J7C, J7E Cheapernet selected

BASE

I

R

QQQQEEQ
2
3
4
5
Q Q 5

~:

• • • • • • • •
• • • • • • • •

:I
TL/F/9179-9

Interrupt 3
(Factory Installed)

NOTES: The Nle's Command Register is always mapped at Base + O. The
NIe registers are Base + 01 to Base + Of; Of will contain different
registers depending on the value of bits PSO and PS1 in the Command Register. These two bits select one of three register pages.
For additional information consult the DP8390 data sheet.

• • • • • • •
• • • • • • •

:I
TL/F/9179-10

The NIC uses the remote DMA channel to read/write data from/to
the 8k x 8 Buffer RAM on the evaluation board. Typically a DMA

Interrupt 4

channel on the PC is used in conjunction with the Nle's remote

DMA. The I/O ports are then serviced by the DMA channel. If a
DMA channel on the PC is not available, the Nle's DMA can still be
used by accessing the 110 ports using programmed 1/0. Reading
the I/O port address will result in a RACK strobe to the NIC while
writing the I/O port address will result in a WACK strobe to the NIC.

I:

• • • • • •
• • • • • •

:I
TLIF/9179-11

1-126

For Cheapernet the following jumpers should be shorted:
Interrupt 5

I:

J7C

•
•

• • • • •

:I

• • • • •

TL/F/917Q-25

Note: Rev 0 demo software will not work unless the factory configuration for

JIC

•

J2C

•

J3C

•

J4C

•

J5C

•

J6C

•

J7E

•

Jumper Block J4 is used.

FACTORY CONFIGURATION:

•
•

:I

•

TL/F/9179-18

TL/F/9179-26

(Factory Installed)

DMA

For Ethernet the following jumpers should be shorted.

The evaluation board may use 1 DMA channel on the PC
expansion bus. DMA channel 1 or 3 can be selected. The
corresponding DACK line must also be installed on Jumper

J7C

••

•

J4.

•
•
•

DMA Channel 1
(Factory Instelled)

I: •• ••

•
•

:I

•
•

TLlF/9179-15

DMA Channel 3

I:

TL/F 19179-19

• • •
• • •

Double check the jumper positions prior to powering up the
board.
TL/F/9179-16

OSCILLATOR

If a DMA channel is not available an interrupt driven routine
can be used to move data between the PC and the buffer
memory on the evaluation board. Interrupt 5 is used for this
function.

When the SterLAN daughter board is used, the 20 MHz oscillator must be disconnected by removing jumper JB. The
SterLAN daughter board provides the clock to the NIC.

IRQ 5 for DMA

Ethernet, Cheapernet
(Factory Installed)

I: •• •• •• ••

• •
• •

:I

TL/F 19179-17

• •

SELECTING ETHERNET OR CHEAPERNET

APPENDICES

Two 10 Mbitlsec Interface options are available, a connection to an external transceiver via the DB-15 connector, or a
direct interface to a BNC T -connector. Seven jumpers are
used to select the appropriate option. These jumpers are
labeled J1C-J7C and J7E.

JB

StarLAN
(Removed)
TLlF/9179-21

The remainder of this document contains the evaluation
board parts list, schematic and PAL descriptions.

1-127

en
.....
~
I

PARTS LIST'

CC

Item '"

Description

Reference Designator

Qty

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

RES.CC4.7K 01f,.W5%
RES.CF39
01f,.W5%
RES.CF 1.5K 01f,.W5%
RES.CF1M
y"W5%
RES.CF270K 01f,.W1%
RES. MK 1K
01f,.W1%
CAP. FILM 0.01 p.F 630V
CAP. DIP TANT 100 p.F 10V RD
CAP. DIP 0.47 p.F 50V 0.3LS
CAP. CER 0.01 p.F 50V 0.2LS
I.C.74LS245
I.C.74LS374
I.C.74LS373
SRAM HM6264-100
PROM 74S288
PAL20L8
TRANSFORMER PE64103
OSCILLATOR 20.00 MHz
JUMPER. 2 POSITION
CONN. 15 POS D-SUB
CONN. MODULAR JACK
CONN. BNC. RIA PCB MOUNT
HEADER. 2 PIN SINGLE ROW
HEADER, 3 PIN SINGLE ROW
HEADER. 44 PIN DOUBLE ROW
SOCKET. 24 PIN DIP
SOCKET. 24 PIN DIP (.300)
SOCKET. 24 PIN (MACH)
BRACKET. CNET
SPACER. 0-25 SET
PCB
DC-DC CONVERTER. 2VP5U9
I.C. DP8390BN
I.C. DP8391N
I.C. DP8392AN

R1. R2. R3. R23
R6. R7. R8. R9
R10. R11. R12. R13
R17
R4.R5
R14
C4
C3,C21
C1. C7-C17. C19
C5.C6
U3
U2.U6
U1
U8
U4
U16
U14
Y1
AIR
J1

4
4
4
1
2
1
1
2
13
2
1
2
1
1
1
1
1
1
13
1
1
1
3
6
0.5
2
1
1
1
1

Z

o

'551 A201·01 REV D Board

1-128

J2
JB.J7C.J7E
J1C-J6C
J4
U11
U16
U9
J1
J1
U10
U11
U9
U15

PAL20LB
Decode and DMA Interface Logic for the DPB39EB
DECODEl
A9

AB

A7

AS

A5

A4

PCRST INMRD

PRQ IDACK IWAIT AEN lRACK IWACK ICSX ICSN
CSN

=

NAl3 IIORD

IIOWR GND

ICSROM lACK

INICRST

VCC

IAEN* A9* AB* IA7* IAS* IA5* IA4* 10WR +
IAEN* A9* AB* IA7* IAS* IA5* IA4* lORD

NICRST
RACK

=PCRST

= IAEN*
DACK*

WACK

= IAEN*
DACK*

CSX

=

A9* AB* IA7* IAS* IA5* A4* PRQ* lORD +
lORD
A9* AB* IA7* IAS* IA5* A4* PRQ* 10WR +
10WR

CSN* lORD +
CSN* 10WR +
IAEN* A9* AB* IA7* IAS* IA5* A4* lORD +
IAEN* A9* AB* IA7* IAS* IA5* A4* 10WR +

IF (CSX)
WAIT

=

lACK
IPRQ

* CSN
* ICSN

CSROM = INAl3

*

+

NMRD
a remote write if the PC AT's /IOWR goes low before the
NIC's PRO goes high.
NIC registers are accessed when CSN (Chip Select NIC) is
asserted. The lORD and 10WR terms are included to ensure
that the address lines are valid when CSN is given.
The RACK and WACK Signals are used by the NIC's remote
DMA channel to acknowledge the end of a single read or
write operation through the remote DMA I/O ports. These
ports are addressable by the PC DMA channel with DACK
and lORD or 10WR, or by addressing the I/O location 310h
(with string I/O's).

DESCRIPTION

This PAL performs the 110 decodes for selecting the NIC,
and the handshake signals for NIC's remote DMA. The PAL
supports the DMA channels of the PC for remote DMA
transfers with the NIC and also allows the use of string I/O
between 80286 PC's and NIC's remote DMA.
DECODE1 fixes the I/O BASE of the card at 300h. NIC
registers fall in the space 300h-30fh. To use the string I/O
port, reads and writes are done to port 310h.
Wait states are inserted (WAIT) to the PC bus when register
accesses are given and the NIC is busy performing DMA
operations. When the NIC is ready, / ACK is given and no
(more) wait states are inserted.
Wait states may also be inserted during remote DMA opera·
tions and 80286 machines using string I/O's. WAIT occurs
during a remote read if the PC AT's /IORD goes low before
the DP8390's PRO goes high. Similarly, WAIT occurs during

CSX is used to enable the TRI·STATE output of WAIT dur·
ing a register access CSN), and during string I/O to the
remote DMA's I/O port (CSX).
CSROM provides address decode for the address PROM.
The card's unique Ethernet address is transferred to the
system using the NIC's remote DMA.

1·129

II

101

102
103

J3

104

IBM I/o CHANNEL
IN1[RFACE

105
106
107

lOB

DECODEI
20LB

GND 10

GND 14
VCC 20

VCC 20

GND 10
vee 20

TL/F 19179-23

1-130

R1 R1,R2=4.7k.o.

Note: For SterlAN, the DP8391 must
be replaced with the StarlAN
Adapter Card. See AN-XXX
for details.

U16/8

I~~~EO

WX+
II~;
TX-

~~~~J~CK

RJ-45

(f" Slarl.AN)
J~OO

OP8392

,4
~

~

~

.11

'XO
C
C'S O L I
RXC
LBK
TXO
TXC
TXE
BSCK

R17
l~OH~
~Watt

LOGIC GNO
Rl0IRllIR12IR13

GND 6
VCC 10,19

R10, R1l, R12, R13= 1.5 k.o.

~·~IIII"

1

R9~ R8

C6

.01UF~

C6

O.OtuF

II ':rl
B9 1:>-o.I7E

BID

R9,R8.R7,R6=39.o.1%

lOGIC GND
1.4,6,11,14

C6

~.01UF

B3 C>---J7C

10

ISOLATED VEE
-9V

11

ISOLATED GN 0

+5V

6.1
ETHERNET AUI
CABLE CONNECTION
D-CONNECTOR

Note: All resistors are " watt, 5%
tolerance unless otherwise
specJfled.

U10

GNO 13
vee 36
NC 16

TL/F/9179-24

6Lt-NV

-I

~

Ethernet/Cheapernet
Physical Layer Made Easy
with DP8391/92

National Semiconductor
Application Note 442
Alex Djenguerian

With the integration of the node electronics of IEEE 802.3
compatible local area networks now on silicon, system design is simplified. This application note describes the differences between the Ethernet and Cheapernet versions of
the standard, and provides design guidelines for implementing the node electronics with National Semiconductor's
DP8390 LAN chip set.

tens" to the medium; if someone else is transmitting, the
station defers until the medium is clear before it begins to
transmit. However, two or more stations could still begin
transmitting at the same time and give rise to a collision.
When this happens, the two nodes detect this condition,
back off for a random amount of time before making another attempt.
The IEEE 802.3 standard supports two different versions for
the media, 10BASE5 (commonly known as Ethernet) and
10BASE2 (Cheapernet). These can be used separately, or
together in a hybrid form. Both versions have similar electrical specifications and can be implemented using the same
transceiver chip (DP8392). Cheapernet is the low cost version and is user install able. The following table compares
the two:

INTRODUCTION
The DP8390 chip set is designed to provide the physical
and media access control layer functions of local area networks as specified in IEEE 802.3 standard. This standard is
based on the access method known as carrier-sense multipie access with collision detection (CSMAlCD). In this
scheme, if a network station wants to transmit, it first "Iis-

10BASE2 (Cheapernet)

1OBASES (Ethernet)

Parameter

Data Rate

10 Mbitls baseband

10 Mbits/s baseband

Segment Length

500m

185m

Network Span

2500m

925m

Nodes per Segment

100

30

Node Spacing

2.5 m (cable marked)

0.5 m min

Capacitance per Node

4 pFmax

8pFmax

Cable

0.4 in diameter
50!!
Double Shielded
Rugged
N-Series Connectors

0.2 in diameter
50!! (RG58A1U)
Single Shielded
Flexible
BNC Connectors

Tranceiver Drop Cable

0.39 in diameter multiway cable with
15 pin D connectors 50 m max length

Not needed due to the high flexibility of
the RG58A1U cable

Typical Connection Diagram for a Station
10BASE2 (Cheapernet)

10BASES (Ethernet)

STANDARD
BNC "T"

TRANSCEIVER

~ICK

ETHERNET
COAX

~)

~.

' - - 15PIN
0 CONNECTOR

.... THIN
RG58A/U
COAX

~

DTE
DATA TERMINAL
EQUIPMENT

{ I ..... TRANSCEIVER
DROP CABLE

A

TLIF18689-2

DTE
DATA TERMINAL
EQUIPMENT
TLlF18689-1

1-132

Although Cheapernet is intended for local use, several 185
meter segments can be joined together with simple repeaters to provide for a larger network span. Similarly, several
Cheapernet segments can be tied into a longer Ethernet
"backbone". In this hybrid configuration, the network com-

bines all the benefits of Cheapernet, flexibility and low cost,
with the ruggedness and the much larger geographic range
of standard Ethernet. Figure 1 illustrates a typical hybrid
LAN configuration.

,r BNC "T" CONNECTOR

(=5=';:~

r

"BACKBONE" ETHERNET CABLE

1====[1]

__ THIN CHEAPERNET
CABLE (RG58A/U)

[i] =50 OHM TERMINATION
TLlF/8689-3

FIGURE 1. A Hybrid EthernetlCheapernet System
TRANSMITTING AND RECEIVING PACKETS WITH THE DP8390 CHIPSET
Node Block Diagram
CO AX
CA BlE

TRANSCEIVER OR MAU

STATION OR OTE

r--

TAP
OR- ~
BNC

-

DP8392
COAX
TRANSCEIVER
INTERFACE

...

I
S
0
L
A
T
I
0
N
"'-

DP8391
TRANSCEIVER
CABLE

SERIAL
NETWORK
INTERFACE

...

DP8390
NETWORK
INTERFACE
CONTROLLER

...

-

H
0
S
T

B
U
S

-

TL/F/8689-4

Iy transfers the data to a local buffer memory. The NIC then
automatically handles the transmission of the packet (from
the local buffer through an on-board FIFO to the SNI) according to the CSMA/CD protocol. The packet has to be in
the following format:

The node electronics is integrated into three chips, the
DP8390 Network Interface Controller (NIG), the DP8391 Serial Network Interface (SNI), and the DP8392 Coaxial Transceiver Interface (CTI). To transmit a packet, the host processor issues a transmit command to the NIC, which normal-

1-133

..,.
..,.
~

.

zc:(

r-------------------------------------------------------------------------------~

PREAMBLE: This section consists of alternating 1 and 0
bits. As the packet travels through the network, some of
these bits would be lost as most of the network components are allowed to provide an output some number of
bits after being presented with a valid input.

o

o

o

NRZ
DATA

START OF A FRAME DELIMITER (SFD): This field consists of two consecutive 1's to signal that the frame reception should begin.
DESTINATION AND SOURCE ADDRESSES: Each one
of these frames is 6 bytes long and specifies the address
of the corresponding node.
LENGTH: This 2 byte field indicates the number of bytes
in the data field.
DATA: This field can be from 46 to 1500 bytes long.
Messages shorter than 46 bytes require padding to bring
the data field to the minimum length. If the data field is
padded, the host can determine the number of valid data
bytes by looking at the length field. Messages longer
than 1500 bytes must be broken into multiple packets.

MANCHESTER
ENCODED
DATA

TLIF/8689-5

FIGURE 2. Manchester Coding

CRC: This field contains a Cyclic Redundancy Code calculation performed on the Destination address through
the Data field for error control.

The encoded signal appears in differential form at the SNI's
output. In 10BASE5 (Ethernet) applications, this signal is
sent to the transceiver or the Medium Attachment Unit
(MAU) through the twisted pair Tranceiver Drop cable (also
known as the Attachment Unit Interface cable). This cable
typically consists of four individually shielded twisted wire
pairs with an overall shield covering these individually
shielded pairs. The Signal pairs, which have a differential
characteristic impedance of 78f! ± 5f!, should be terminated at the receiving ends. The cable can be up to 50 meters
in length and have a maximum delay of 257 ns. The shields
of the individual pairs should be connected to the logic
ground in the Data Terminal Equipment (DTE) and the outer
shield to the chassis ground. Figure 3 shows a picture of the
cable and the corresponding pin assignments.

The shortest packet length thus adds up to be 512 bits long
(excluding the preamble and the SFD). At 10 Mbitlsec this
amounts to 51.2 IJ-s, which is twice as much as the 25 IJ-s
maximum end-to-delay time that is allowed by the IEEE
802.3 protocol. This ensures that if a collision arises in the
network, it would be recognized at all node locations.
The SNI combines the NRZ data packet received from the
controller with a clock signal and encodes them into a serial
bit stream using standard Manchester encoding. In this coding scheme, the first half of the bit cell contains the complementary data and the second half contains the true data.
Thus a transition is always guaranteed in the middle of a bit
cell.
DATA TERMINAL
EQUIPMENT
(DTE)
fEMALE
CONNECTOR - -

Pin

V - !~~~~NECTOR
U

6

TRANSCEIVER
-DROP CABLE
(AU INTERfACE CABLE)

-

fEMALE
CONNECTOR

MALE __ , - -__....
CONNECTOR
TRANSCEIVER
(MAU)

IEEE 802.3 Name

Pairs

DP8391/2
Name

3
10
11

DO + (Data Out +)
DO - (Data Out -)
DO S (DO Shield)

Transmit
Pair

TX+
TX-

5
12
4

01 + (Data In +)
01 - (Data In -)
01 S (01 Shield)

Receive
Pair

RX+
RX-

7
15
8

CO + (Control Out +)
CO - (Control Out -)
CO S (CO Shield)

Optional
Pair

2
9
1

CI + (Control In +)
CI - (Control In -)
CI S (CI Shield)

Collision
Pair

6
13
14

VC (Voltage Common)
VP (Voltage Plus)
VS (Voltage Shield)

Shell

PG (Protective GND)

TL/F/8689-6

FIGURE 3. Transceiver Cable Pin Assignments

1-134

Signal from
DTE

MAU

X
X
X
X
X
X
X
X
X
X
X

CD+
COX

Power
Pair

X
X
X
X

signal has to meet several critical electrical requirements:

The transmitted packet from the SNI as well as all other
signals (receive, collision, and DC power) must be electrically isolated from the coax in the MAU. The isolation means
provided must withstand 500 V AC rms for one minute for
10BASE2 and 2000 VAC rms for 10BASE5. In order to detect collisions reliably, the electrical isolation is not done at
the coax; instead it is done on the side of the Attachment
Unit Interface. The isolation for the three signal lines can be
easily provided by using three pulse transformers that come
in a standard 16 pin plastic DIP from several manufacturers
(Pulse Engineering, Valor Electronics). The inductance value for these transformers vary from 50 fLH to 150 fLH with
the larger inductance values slowing the rise and fall times,
and the smaller ones causing more voltage droop.

RISE/FALL TIMES: The 10%-90% rise and fall times
have to be 25 ns ± 5 ns at 10 Mbitl sec. This spec helps
to minimize electro-magnetic radiation by reducing the
higher harmonic content of the signal and contributes to
the smaller reflection levels on the coax. In addition, the
rise and fall times are required to be matched to within
1 ns to minimize the overall jitter in the system.
DC LEVEL: The DC component of the Signal has to be
between - 37 mA and - 45 mA. The tolerance here is
tight since collisions are detected by monitoring the average DC level on the coax.
AC LEVEL: The AC component of the signal has to be
between ±28 mA and the DC level. This specification
guarantees a minimum signal at the far end of the coax
cable in the worst case condition.
The signal shown in Fig. 4 would be attenuated as it travels
along the coax. The maximum cable attenuation per segment is 8.5 dB at 10 MHz and 6 dB at 5 MHz. This applies
for both the 500 meters of Ethernet cable and the 185 meters of Cheapernet cable. With 10 Mbitlsec Manchester
data, this cable attenuation results in approximately 7 ns of
edge jitter in either direction. The CTI's receiver has to compensate for at least a portion of this jitter to meet the ± 6 ns
combined jitter budget. The receiver also should not overcompensate the signal in the case of a short cable. An
equalizer filter in the CTI accomplishes this task. Figure 5
shows a typical waveform seen at the far end of the cable
and the corresponding differential output from the CTl's receiver.

The Manchester encoded data from the SNI now reaches
the CTI's transmit input after passing through the isolation
transformer. A noise filter at this input provides a static
noise margin of -175 mV to -300 mY. These thresholds
assure that differential Transmit (TX ±) data signals less
than -175 mV or narrower than 10 ns are always rejected,
while Signals greater than - 300 mV and wider than 30 ns
are always accepted. The - 300 mV threshold provides sufficient margin since the differential drivers for the transceiver drop cable provide a minimum signal level of ± 450 mV
after inductive droop, and the maximum attenuation allowed
for the drop cable is 3 dB at Signal frequencies. Signals
meeting the squelch requirements are waveshaped and outputted to the coax medium. This is done as follows:
The transmitter's output driver is a switching current source
that drives a purely resistive load of 250 presented by the
coax to produce a voltage swing of approximately 2V. This

~--~====~-------:==~--:======----=omA
RISE TIME

I

o

o
TLiF/8689-7

FIGURE 4. Coax Transmit Waveform

A TYPICAL 1OMBI S SIGNAL SEEN
AT FAR END OF COAX CABLE
---+

RECEIVE OUTPUT - - - - - - +
OF CTI

TLiF/8689-8

FIGURE 5. Oscilloscope Waveforms

1-135

»
z

.

"'"'""

N

TRANSCEIVER
DROP CABLE

TRANSCEIVER
DROP CABLE

ETHERNET OR CHEAPERNET
MAXIMUM LENGTH COAX CABLE

JITTER

I

0.5no

1.0no 2.0n.

7.0no

-1.0no 1.0ns

I
TLiF/8689-9

Total Jitter without Noise

= 0.5 + 1.0 + 2.0 + 7.0 -

1.0

+ 1.0 = 10.5 ns

AddHional Jitter from Noise on Coax Cable = 5.0 ns
Additional Jitter from Noise on Drop Cables = 1.0 ns
Total System Jitter
~

= 16.5 ns

SAMPLING POINT

TLiF/8689-10

FIGURE 6. Typical Signal Waveform at SNl's Input
In addition to the equalizer, an AC/DC squelch circuit at the
coax input prevents noise on the cable from falsely triggering the receiver in the absence of a valid signal. The Receive differential line from the CTI should be isolated before
it reaches the SNI for Manchester decoding. This signal now
could have accumulated as much as ± 16.5 ns of jitter. Figure 6 illustrates the jitter allocations for different network
components and a typical signal waveform at the SNI's input. The digital phase-locked loop of the SNI can decode
Manchester data with up to ±20 ns of random jitter which
provides enough margin for implementation.
The SNI converts the Manchester received packet to NRZ
data and clock pulses and sends them to the controller.
Upon reception, the NIC checks the destination address,
and if it is valid, verifies the CRC with the one generated on
board and stores the packet in the local buffer memory. The
packet is then moved to the host by the NIC, and when this
is completed the buffer area is reclaimed for storing new
packets. If a collision occurs during this transfer process,
the CTI will detect it by sensing the average DC level on the
coax and will send a 10 MHz collision signal to the SNI. The
SNI will translate this information to the controller in TTL
form, and the transmitting controllers will backoff, for different times and retransmit later. Also in case of illegally long
packets (longer than 20 ms), a jabber timer in the CTI will
disable the coax driver so that the "jabbering" station will
not bring down the entire network. The collision pair is activated in this case to inform the controller of the faulty condition. After the fault is removed, the jabber timer holds for
500 ms before re-enabling the coax driver.

COLLISION DETECTION SCHEMES
There are four different collision detection schemes that
can be implemented with the CTI; receive, transmit, transhybrid, and hybrid modes. The IEEE 802.3 standard allows the
use of receive, transmit, and transhybrid modes for non-repeater nodes for both Ethernet and Cheapernet applications. Repeaters are required to have the receive mode implementation. Moreover in Cheapernet, where the AUI cable
is not exposed, the collision detection scheme can be tailored to the user's needs; in this case the hybrid mode can
also be used. These different modes are defined as follows:
RECEIVE MODE: Detects a collision between any two
stations on the network with certainty at all times.
TRANSMIT MODE: Detects collisions with certainty only
when the station is transmitting.
TRANSHYBRID MODE: Same as transmit mode except
uses a signal cancellation technique.
HYBRID MODE: Detects any carrier other than the station's own transmission. Signal cancellation is used.
RECEIVE MODE: The receive mode scheme has a very
simple truth table; however, the tight threshold limits make
the design of it difficult. The threshold in this case has to be
between the maximum DC level of one station (-1300 mY)
and the minimum DC level of two far end stations
( -158 1 mY). Several factors such as the termination resistor variation, coax center conductor resistance, driver current level variation, signal skew, and input bias current of
non-transmitting nodes contribute to this tight margin. On

1-136

Truth Table for Various Collision Detection Schemes
Mode

Receive
>2 0

1 2

Transhybrid

>2 0

Transmitting

N N Y

Y N N Y

Y N N Y

Y N N Y

Y

Non-Transmitting N N Y

Y N N M

Y N N M

Y N Y Y

Y

N = It will not detect a collision,

1 2

>2 0

Hybrid

0

Y = It will detect a collision,

1 2

Transmit

No. of Stations

1 2 >2

M = It may detect a collision

two transistor self oscillating primary circuit and some regulation on the secondary as shown in Figure 7.
Several areas of the PC board layout require special care.
The most critical of these is for the coax connection. Ethernet requires that the CTI capacitance be less than 2 pF on
the coax with another 2 pF allocated for the tap mechanism.
The Receive Input (RXI) and the Transmit Output (TXO)
lines should be kept to an absolute minimum by mounting
the CTI very close to the center pin of the tap. Also, for the
external diode at TXO (see Figure 8), the designer must
minimize any stray capacitance, particularly on the anode
side of the diode. To do this, all metal lines, especially the
ground and VEE planes, should be kept as far as possible
from the RXI and TXO lines.
In order to meet the stringent capacitive loading requirements on the coax, it is imperative that the CTI be directly
soldered to the PC board without a socket. A special lead
frame in the CTI package allows direct conduction of heat
from the die through these leads to the PC board, thus reducing the operating die temperature Significantly. For good
heat conduction the VEE pins (4,5 and 13) should be connected to large metal traces or planes.
A separate voltage sense pin (CDS) is provided for accurate
detection of collision levels on the coax. In receive mode,
where the threshold margin is tight, this pin should be independently attached to the coax shield to minimize errors
due to ground drops. A resistor divider network at this pin
can be used for transmit mode operation as described earlier.
The differential transmit pair from the DTE should be terminated with a 78n differential resistive load. By splitting the
termination resistor into two equal values and capacitively
AC grounding the center node, the common mode impedance is reduced to about 20n, which helps to attenuate
common mode transients.
To drive the 78n differential line with sufficient voltage
swings, the CTl's collision and receive drivers need external
soon resistors to VEE. By using external resistors, the power dissipation of the chip is reduced, enhancing long term
reliability. The only precision component required for the
CTI is one 1k 1% resistor. This resistor sets many important
parameters of the chip such as the coax driving levels, output rise and fall times, 10 MHz collision oscillator frequency,
jabber timing, and receiver AC squelch timing. It should be
connected between pins 11 (RR +) and 12 (RR -).

top of the -1300 mV minimum level, the impulse response
of the internal low pass filter has to be added. The CTI
incorporates a 4 pole Bessel filter in combination with a
trimmed on board bandgap reference to provide this mode
of collision detection. However it would be difficult in receive
mode to extend the cable length beyond the limits of the
standard. It is also argued that it is not necessary for non-repeater nodes to detect collisions between other stations.
This brings us to transmit mode.
TRANSMIT MODE: In this case collisions have to be detected with certainty only when the station is transmitting.
Thus, collisions caused by two other nodes mayor may not
be detected. This feature relaxes the upper limit of the
threshold from -1581 mV to -1782 mV. As a result of this,
longer cable segments can be used. With the CTI, a resistor
divider can be used at the Collision Detect Sense pin (CDS)
to lower the threshold from receive to transmit mode. Typical resistor values can be 120n from CDS to GND and 10k
from CDS to VEE (This moves the threshold by about -100
mV).
TRANSHYBRID MODE: This mode has exactly the same
truth table as transmit mode. However, during transmission
collisions are detected by a cancellation technique. This
provides more margin and makes it more reliable than the
transmit mode. It also allows for longer cable lengths than
the transmit mode.
HYBRID MODE: This mode is basically a "carrier sense"
when the station is not transmitting. However, during transmission it is the same as the Transhybrid mode-it cancels
its own DC level to detect any other carrier on line. This is
by far the most robust option-the cable length can be extended to almost twice the value specified in the standard, it
is easy to implement, and it's reliable.
The DP8393-multimode CTI is needed to implement the hybrid and the transhybrid options.
IMPLEMENTING A 10 BASE5 (ETHERNET) MAU WITH
THE DP8392
The CTI provides all the MAU (transceiver) functions except
for signal and power isolation. Signal isolation can easily be
provided by a set of three pulse transformers that come in a
single Dual-in-Line package. These are available from transformer vendors such as Pulse Engineering (PE64103) and
Valor (LTll0l). However, for the power isolation a DC to
DC converter is required. The CTI requires a single - 9
(±5%) volt supply. This power has to be derived from the
power pair of the drop cable which is capable of providing
500 mA in the 12 (-6%) to 15 (+5%) volt range. The low
supply current of the CTI makes the design of the DC to DC
converter quite easy. Such converters are being developed
in hybrid packages by transformer manufacturers (Pulse Engineering PE64430 and Reliability Inc. 2E12R9). They provide the necessary voltage isolation and the output regulation. One can also build a simple DC to DC converter with a

The DP8392 features a heartbeat function which can be
externally disabled using pin 9. This function activates the
collision output for a short time (10 ± 5 bit cells) at the end
of every transmission. It is used to ensure the controller that
the collision circuitry is intact and properly functioning. Pin 9
enables CD Heartbeat when grounded, and disables it when
connected to VEE.

1-137

I··

The IEEE 802.3 standard requires a static discharge path to
be provided between the shield of the coax cable and the
DTE ground via a 1 MO, 0.25W resistor. The standard also
requires the MAU to have low susceptibility levels to electromagnetic interference. A 0.01 ",F capacitor will provide a

sufficient AC discharge path from the coaxial cable shield to
the DTE ground. The individual shields should also be capacitively coupled to the Voltage Common in MAU. A typical
Ethernet MAU connection diagram using the CTI in receive
mode with the CD Heartbeat enabled is shown in Figure 8.
PICO 33223
1:1.2
OUT

+

+
3
12 TO 15
VOLTS

9V

8
500n

9
.1 jJ.F

1500n

CER
10
TLIF18689-11

FIGURE 7. A Simple Low Cost DC to DC Converter

412

SHIELDED ENCLOSURE

--------------------.-----------------------------DC TO DC
CONVERTER
12 TO 15V INPUT
-9 VOLTS OUTPUT

T~5VDC

-

6

+
9V (iSOLATED)

-

500n EACH

1.,jJ.F

.-

1

2

.-

2

~

4

~

PE64108
LT1101 13

-

TRANSMIT
PAIR

-

7
39.n

39 n

~

_T·

01

jJ.F

r

16

2

15

3

14

I

~4

10

) (1
~9

RX-

TX+
TX-

CDS
lN4150
OR

~5

112
OR
EQUIV.

~

I

1

~

1 l

10

RX+

~

5 (

~

-

l

CD-

? ~U
)
~

3

CD+

~

~

D COLLISION
PAIR
C
9
0
N
.- 5
N
E
C
T RECEIVE
0
PAIR
R
12

......

16

)

~

DP8392
CTI

13

~N916

CO;:

RXI
VEE

6

12QIk
RR+
1%
11

7

10

8

9

\..:.
>--

GND
HBE

1M
.01 jJ.F

-------------------------------------------------- ..
TLIF18689-12

FIGURE 8. An Ethernet MAU Implementation with the CTI
1-138

CHEAPERNET APPLICATION WITH
THE DP8391 AND DP8392
The pin assignment of both the CTI and the SNI are designed to minimize the crossover of any printed circuit
traces. Some of the components needed for an Ethernet
like interface are not needed for Cheapernet. For instance,
Cheapernet's relaxed load capacitance (8 pF, compared
with 4 pF for Ethernet) obviates the need for an external
capacitance isolation diode at TXO. Also, since the transceiver drop cable is not used in Cheapernet, there's no
need for the 78n termination resistors. Moreover, without
the 78n loading on the differential outputs, the pulldown
resistors for both the CTI's collision and receive drivers and
the SNI's transmit driver can be larger to save power. These
resistors can be 1.5k instead of 500n for the CTI and 500n
instead of 270n for the SNI.
The 20 MHz crystal connection to the SNI requires special
care. The IEEE 802.3 standard requires a 0.01 % absolute
accuracy on the transmitted signal frequency. An external
capacitor between the Xl and X2 pins is normally needed to
get the required frequency range. Section 3.1 of the data
sheet describes how to choose the value of this capacitor.

--

+-

.--

-

24 CD+

. - RXD 2

__

. - CRS

--

-

1

3
22 RX+
21 I-R:::;X:...-______---.

-

6

-

20~
DP8391 19
SNI

LBK 7
X1

Vee

CD+ 1

16!-"C",DS'--+lH

~.lt~r-'-5-+-J-f--t-t4--t-:;.:o:,: :

8

..........1f--5500-+n
-

TXD 10

15~

.
_ - TXC 11

14 TX+

.--

13 TX-

TXE

12

,.....'_3-1_+-.......

JIL
----.~ I
~ ~

L-_+7- - ' EQO~V.

18-

::!:,T

-

16

'---t_4_ , LT11 01

~

M~~T'--+-=i9
T X2
-

r."I

15n
)

SEL 5

~

COAX

9V (ISOLATED)

1.5 k EACH

23 CD-

. - RXC 4

-

+

DC TO DC
CONVERTER

5V

._ - COL 1

The SNI also provides loopback capability for fault diagnosis. In this mode, the Manchester encoded data is internally
diverted to the decoder input and sent back to the controller. Thus both the encoding and the decoding circuits are
tested. The transmit differential output driver and the differential input receiver circuits are disabled during loop back.
This mode can be enabled by a TTL active high input at pin
7.
Two different modes, half step and full step, can be selected at the SNI's transmit output. The standards require half
step mode of operation, where the output goes to differential zero during idle to eliminate large idle currents through
the pulse transformers. On the other hand, the differential
output remains in a fixed state during idle in full step mode.
The SNI thus can be used with transceivers which work in
either mode. The two different modes can be selected with
a TTL input at pin 5.
Figure 9 shows a typical Cheapernet connection diagram
using the DP8391 and the DP8392.

'--'-0-t-~--,

~4
~5

9

CTI

12GJRR-~1 k
RR+

11

TX-

~~~------~~8

I

13~

RX- 6

).----t--.IL--------"'-'-ITX+ 7

8

DP8392

RXI

1%

10 t-=G::;;NO:......_.....
9

HBE

.
_-

1500n

TLlF/8689-13

FIGURE 9. Cheapernet Connection Diagram
The power isolation is similar here as in the Ethernet application, except the DC input is now usually 5V instead of
12V. Hybrid DC to DC converters are also being developed

for this application (Ex: Pulse Engineering PE64381). Figure
10 shows a discrete implementation with 5V input and -9V
output.

1-139

»
z
I

.1:10
.1:10
N

PICO 33143
1:3.45
OUT

+

+
3
5V

9V

8
1k
1500.0.

.1 JioF

CER
10
TL/F/8689-14

FIGURE 10. DC to DC Converter (5V to -9V)

1-140

:J>

z
•
......
""'(II

National Semiconductor
Application Note 475

DP8390 Network Interface
Controller: An Introductory
Guide
OVERVIEW
A general description of the DP8390 Network Interface Controller (NIC) is given in this application note. The emphasis
is placed on how it operates, and how it can be used. This
description should be read in conjunction with the DP8390
data sheet.
1.0 INTRODUCTION
The DP8390 Network Interface Controller provides all the
Media Access Control layer functions required for transmission and reception of packets in accordance with the IEEE
802.3 CSMAlCD standard. The controller was designed to
act as an advanced peripheral and serve as a complete
interface between the system and the network. The onboard FIFO and DMA channels work together to form a
straight-forward packet management scheme, providing (local) DMA transfers at up to 10 megabytes per second while
tolerating typical bus latencies.
A second set of DMA channels (remote DMA) is provided
on chip, and is integrated into the packet management
scheme to aid in the system interface. The DP8390 was
designed with the popular 8, 16 and 32 bit microprocessors
in mind, and gives system designers several architectural
options. The NIC is fabricated using National Semiconductor's double metal 2 micron microCMOS process, yielding
high speed with very low power dissipation.
2.0 METHOD OF OPERATION
The NIC is used as a standard peripheral device and is controlled through an array of on-Chip registers. These registers
are used during initialization, packet transmission and reception, and remote DMA operations. At initialization, the
physical address and multicast filters are set, the receiver,
transmitter and data paths are configured, the DMA channels are prepared, and the appropriate interrupts are
masked. The Command Register (CR) is used to initiate
transmission and remote DMA operations.

Upon packet reception, end of packet transmission, remote
DMA completion or error conditions, an interrupt is generated to indicate that an action should be taken. The processor's interrupt driven routine then reads the Interrupt Status
Register (ISR) to determine the type of interrupt that occurred, and performs the appropriate actions.
3.0 PACKET TRANSMISSION
The NIC transmits packets in accordance with the CSMAI
CD protocol, scheduling retransmission of packets up to 15
times on collisions according to the truncated binary exponential backoff algorithm. No additional processor intervention is required once the transmit command is given.
DESTINATION ADDRESS
6 BYTES
~------------~
SOURCE ADDRESS
6 BYTES
TX BYTE COUNT
(TBCRO.l)

~------------~
TYPE LENGTH

1--------1
DATA

PAD (IF DATA

< 46

2 BYTES
~

BYTES)
TLlF/e141 -1

FIGURE 1. Transmit Packet Format
3.1 Transmission Setup
After a packet that conforms to the IEEE 820.3 speCification
is set up in memory, with 6 bytes of the destination address,
followed by 6 bytes of the source address, followed by the
data byte count and the data, it is ready for transmission
(see Figure 1). To transmit a packet, the NIC is given the
starting address of the packet (TPSR), the length of the
packet (TPCRO, TBCR1), and then the PTX (transmit packet) bit of the Command Register is set to initiate the transmission (see Figure 2).

TRANSMIT
BUFFER
PSTART - + t - - - - - - - - - - i l . i
DESTINATION ADDRESS
~
16 BYTE
FIFO

.----

SOURCE ADDRESS

:::::-----~------------~
TYPE LENGTH

,

I

,

I

TxE
TxC

SERIALIZER

TxD

CRC

DATA

I
I
I
I

: BYTE
I COUNT
I
I
I
I

:MI

,,
,

PROTOCOL
PLA
TL/F/e141-2

FIGURE 2. Packet Transmission

1-141

.,
I
I

I
I

DMA PLA
CRS -+
COL-+

46 BYTES

..,r-.

U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .

Z

-

.......

U'I

U) r---------------------------------------------------------------------------------,
.....

.,.

z

c(

TLlF/9141-5
TL/F/9141-6

FIGURE 5. Receive Packet Buffering
and the (4) boundary (BNRy) pointer. to show where the
next packet to be unloaded (or processed) lies. As packets
are received, the boundary pointer follows the current page
pointer around the ring. The page start and stop pOinters
remain unchanged during operation.

the Receive Status Register (RSR), a pointer to the next
packet, and the byte count of the current packet are written
into the 4 byte offset.
If a receive error occurs (FAE, CRG) CURR is not updated
at the end of a reception, so the next packet received overwrites the bad packet (see Figure 6). This feature can be
disabled (by setting the save errored packet (SEP) bit in the
RCR) to allow examination of errored packets.
At receiving nodes, collision fragments may be seen as runt
packets. A runt packet is a packet less than 64 bytes (512
bits) long, and since a collision must occur in the first 512 bit
times, the packet will be truncated to less than 64 bytes.
After runt packets are received, the CURR is not updated,
so the next packet received will overwrite the runt packet.
This standard feature can also be suppressed by setting the
AR bit in the TCA. This is useful when it is desirable to
examine collision fragments, and in non-standard applications where smaller packets are desirable.
Once packets are in the receive ring they must be processed. However, the amount of processing that occurs while
the packet is in the buffer ring varies according to the implementation. As packets are removed from the buffer ring, the
boundary pOinter (BNRY) must be updated. The BNRY always follows CURR around the ring (see Figure 7).

The receive buffer ring is divided into 256 byte buffers, and
these buffers are linked together as required by the received packets (see Figure 4). Up to 256 of these buffers
can be linked together in the receive buffer ring, yielding a
maximum buffer size of 64K bytes. Since all NIC registers
are 8 bits wide, the ring pointers refer to 256 byte boundaries within a 64K byte space.
At initialization, PSTART register is loaded with the beginning page address of the ring, and PSTOP is loaded with the
ending page address of the ring.
On a valid reception, the packet is placed in the ring at the
page pOinted to by CURR plus a 4 byte offset (see Figure 5).
The packet is transferred to the ring, a DMA burst at a time.
When necessary, buffers are automatically linked together,
until the complete packet is received. The last and first buffers of the ring buffer are linked just as the first and seconds
buffers. At the end of a reception, the status from

TLlF/9141-7
TL/F/9141-8

FIGURE 6. Packet Rejection

FIGURE 7. Removing Packets From Receive Buffer Ring

1-144

If the current local DMA address ever reaches BNRY, the
ring is full. In this case, the current and any additional receptions are aborted and tallied until the BNRY pointer is updated. Packets already present in the ring will not be overwritten (see Figure 8). All missed packets will increment the
missed packet tally counter. When enough memory is allocated for the receive buffer ring, the overwrite warning (setting of the OVW bit of the ISR) should seldom occur.

3. After each packet is removed from the ring, use the next
packet pointer in the header information (the second byte
of the header), HNXTPKT, and set:
NXTPKT = HNXTPKT
BNRY = HNXTPKT - 1
If BNRY < PST ART then BNRY = PSTOP - 1
The above procedure is not necessary if the Send Packet
Command is used to remove packets from the ring as explained in section 7.

ZND PACKET

5_0 SYSTEMINETWORK INTERFACE
The DP8390 offers considerable flexibility when designing a
system/network interface. This flexibility allows the designer to choose the appropriate price/performance combination while easing the actual design process.
5.1 Interfacing Considerations
Several features have been included on the NIC to allow it
to easily be integrated into many systems. The size of the
data paths, the byte ordering, and the bus latencies are all
programmable. In addition, the clock the DMA channels use
is not coupled to the network clock, so the NIC's DMA can
easily be integrated into memory systems.
5.1.1 Data Path
The NIC can interface with 8, 16, and 32 bit microprocessors. The data paths are configurable for both byte- wide
and word-wide transfers (bit WTS in DCR). When in wordwide mode, the byte ordering is programmable to accommodate both popular byte ordering schemes. All N IC registers
are 8 bits wide to allow 8, 16 and 32 bit processors to access them with no additional hardware. If the NIC's 16 address lines (64K bytes) do not provide an adequate address
space, the two DMA channels can be concatenated to form
a 32 bit DMA address (bit LAS in DCR).

TLiF/9141-9

FIGURE 8. Receive Buffer Ring Overwrite Protection
A second set of DMA channels has been included on the
DP8390 to aid in the transfer of packets out of the buffer
ring. These Remote DMA channels can work in close co-operation with the receive buffer ring to provide a very effective system interface (§7).
If the BNRY is placed outside of the buffer ring, no overwrite
protection will be present, and incoming packets may overwrite packets that have not been processed. This may be
useful when evaluating the DP8390, but in normal operation
it is not recommended.
When the CURR and BNRY pointers are equal, the buffer
ring can either be completely empty or completely full. To
ensure that the NIC does not misinterpret this condition, it is
necessary to guarantee that the value of the BNRY pointer
does not equal the value of the CURR pointer. It is recommended that the BNRY pointer be kept one less than CURR
pointer when the ring is empty, and only be equal to CURR
when the ring is full, as shown below.

5.1.2 Local DMA
The DMA transfers between the FI FO and memory during
transmission and reception occur in bursts. The bursts begin when the FIFO threshold is reached. Since only a single
FI FO is required (because a node cannot receive and transmit simultaneously), the threshold takes on different meanings during transmission and reception. During reception the
FIFO threshold refers to the number of bytes in the FIFO.
During transmission the FIFO threshold refers to the number of empty bytes in the FIFO (16 - # bytes in FIFO). The
FIFO threshold is set to 2, 4, 8 or 12 bytes (1, 2, 4 or 6
words) in the DCR (bits FTO, FT1).

1. Use a variable (NXTPKT) to indicate from where the next
packet will be removed (possibly using Remote DMA)
2. At initialization set:
BNRY = PSTART
CURR = PSTART + 1
NXTPKT = PSTART + 1

The number of transfers that occur in a burst depends on
whether the Exact Transfer or Empty/Fill mode is used (bit
BMS in DCR). When in Exact Transfer mode, a number of
bytes/words equal to the FIFO threshold will be transferred
in each burst. The Empty/Fill mode continues the transfers
until the FIFO is empty, during receptions, and full, during
transmissions (see Figure 8).

,'-----

BREQ

BACK

ADO-15

_ _.-If
~ ................

'----

~ONEBURST

TL/F/9141-10

where N = 1,2,4 or 6 Words or N

=

2,4,8, or 12 Bytes when in byte mode

FIGURE 8. Local DMA Burst

1-145

.... ,--------------------------------------------------------------------------,
a burst can begin, the NIC must first arbitrate to
6.0 INTERFACE OPTIONS
;1 Before
become master of the bus. It requests the bus by activating
The network interface can be incorporated into systems in
~

c:r:

the BREQ signal and waiting for acknowledgment with the
BACK signal. Once the NIC becomes the master of the bus,
the byte/word transfers may begin. The frequency of the
DMA clock is not related to the network clock, and can be
input (pin 25) as any frequency up to 20 MHz. For 10 Mbitl
sec networks the DMA clock can be as slow as 6 MHz. This
allows tailoring of the DMA channel, to the system. The local DMA channel can burst data into and out of the FIFO at
up to 10 Mbyte/sec (8X the speed of standard Ethernet).
This means that during transmission or reception the network interface could require as little as one eighth of the bus
bandwidth.

several ways. The network interface can be controlled by
either a system processor or a dedicated processor, and
can utilize either system memory or buffer memory. This
section covers the basic interface architectures.
6.1 Single Bus System
The least complex implementation places the NIC on the
same bus as the processor (see Figure 10!. The DP8390
acts as both a master and a slave on this bus; a master
during DMA bursts, and a slave during NIC register accesses. This architecture is commonly seen on motherboards in
personal computers and low cost workstations, but until recently without an integrated network interface. A major issue in such designs is the bus bandwidth for use by the
processor. The DP8390 is particularly suitable for such applications because of its bus utilization characteristics. During transmissions and receptions, the only time the NIC becomes a bus master, the DP8390 can require as little as
one- eighth the bus bandwidth. In addition, the previously
mentioned bus tailoring features, ease its integration into
such systems.

5.1.3 Bus Analysis
Two parameters useful in analysis of bus systems are the
Bus Latency and the Bus Utilization. The Bus Latency is the
maximum time between the NIC assertion of BREQ and the
system granting of BACK. This is of importance because of
the finite size of the NIC's internal FIFO. If the bus latency
becomes too great, the FIFO overflows during reception
(FIFO overrun error), and becomes empty during transmission (FIFO underrun error). Both conditions result in an error
that aborts the reception or transmission. In a well designed
system these errors should never occur. The Bus Utilization
is the fraction of time the NIC is the master of the bus. It is
desirable to minimize the time the NIC occupies the bus, in
order to maximize its use by the rest of the system. When
designing a system it is necessary to guarantee the NIC a
certain Bus Latency, and it is desirable to minimize the Bus
Utilization required by the NIC.

NIC

PROCESSOR

Associated with each DMA burst is a DMA set up and recovery time. When a packet is being transferred either to or
from memory it will be transferred in a series of bursts. If
more byte/word transfers are accomplished in each burst,
fewer bursts are required to transfer the complete packet,
and less time is spent on DMA set up and recovery. Thus,
when longer bursts are used, less bus bandwidth is required
to complete the same packet transfer.

MEMORY

I--

-

OTHER
DEVICES

TL/F/9141-11

FIGURE 10. Single Bus Configuration
The design must only be able to guarantee the NIC a maximum bus latency « 9 ".S for 10 Mbitls networks), because
of the finite size of the on-Chip FIFO. In bus systems where
the NIC is the highest priority device, this should present no
problem. However, if the bus contains other devices such as
Disk, DMA and Graphic controllers that require the bus for
more than 10 ".S during high priority or real time activities,
meeting this maximum bus latency criteria could present a
problem.

The Empty(/Fill) mode guarantees longer bursts because
as the byte/word transfers are taking place, serialized data
is still filling(/emptying) the FIFO, and these additional
bytes/words must also be transferred out of(/into) the
FIFO. The least NIC bus utilization occurs when the bursts
are as long as possible. This occurs when the threshold is
as high as possible, and Empty/Fill mode is used. The determination of the threshold Is related to the maximum bus
latency the system can guarantee the NIC.

Likewise, many existing single bus systems make no provision for external devices to become bus masters, and if they
do, it is only under several restrictions. In such cases, an
interface without the mentioned bus latency restrictions is
highly desirable.

If the NIC is required to guarantee other devices a certain
bus latency, it can only remain master of the bus for a certain amount of time. In this case, the Exact Transfer burst
mode is desirable because the NIC only remains master of
the bus for a certain amount of time.

1-146

»
z

6.2 Dual Port Memory

I

"'"

......

One popular method of increasing the apparent bus latency
of an interface, has the added effect of shielding the system
bus from the high priority network bandwidth. In this applica·
tion, the Dual Port Memory (DPM) allows the system bus to
access the memory through one port, while the network in·
terface accesses it through the other port. In this way, all of
the high priority network bandwidth is localized on a dedicat·
ed bus, with little effect on the system bus (see Figure 11).

8-

PROCESSOR

DI.lA

I.lEI.lORY

U1

PROCESSOR

NIC

r-

--

S

DI.lA

I.lEI.lORY

I.lEI.lORY
NIC

fo- BI-DIRECTIONAL
I/O PORT

I--

TL/F/9141-13

FIGURE 12. DPM Equivalent Configuration

I--

r-

The high priority network bandwidth is decoupled from the
system bus, and the system interracts with the buffer memory using a lower priority bi-directional 1/0 port. For example, when a packet is received the local DMA channel transfers it into the buffer memory, part of which has been configured as the receive buffer ring. The remote DMA channel
then transfers the packet on a byte by byte (or word by
word) basis to the 1/0 port. At this point, as in the previous
example, the processor (or if available, DMA channel),
through a completely asynchronous protocol, transfers the
packet into the main memory.

OTHER
DEVICES

TLlF/9141-12

FIGURE 11. DPM Configuration
Dual Port Memories are typically smaller than the main
memory and little, if any, processing can occur while the
packets are in the DPM. Therefore, the processor (or if
available, DMA controller) must transfer data between the
DPM and the main memory before beginning packet processing. In this example, the DPM acts as a large packet
FIFO.

6.4 Dual Processor Configuration
For higher performance applications, it is desirable to offload the lower-level packet processing functions from the
main system (see Figure 11). A processor placed on a local
bus with the NIC, memory and a bi-directionall/O port could
accomplish these lower-level tasks, and communicate with
the system processor through a higher level protocol. This
processor could be responsible for sending acknowledgement packets, establishing and breaking logical links, assembling and disassembling files, executing remote procedure calls, etc.

Such configurations provide workable solutions, however,
Dual Port Memories are inherently expensive. Aside from
the extra complexity of the software, DPM contention logic
is expensive, and dedicated DPM chips provide only 1k of
memory and cost as much as advanced VLSI devices. In
addition, some systems do not contain additional memory
for such memory mapped interfaces.
6.3 Dual Port Memory Equivalent
The functional equivalent of a Dual Port Memory implementation can be realized for low cost with the DP8390. This
configuration makes use of the NIC's Remote DMA capabilities and requires only a buffer memory, and a bidirectional
1/0 port (see Figure 12). The complete network interface,
with 8k x 8 of buffer memory, easily fits onto a half size IBMPC card (as in the Network Interface Adapter, NIA, for the
IBM-PC.)

PROCESSOR
NIC

I.lEI.lORY

I--

t--

BI-DIRECTIONAL
t- HOST
I/O PORT

TL/F/9141-14

FIGURE 13. Dual Processor Configuration

1-147

....

~

r---------------------------------------------------------------~

"II'

7.0 REMOTE DMA

«

A second set of DMA channels is built into the DP8390 to
aid in the system integration (as discussed above). Using a
simple asynchronous protocol, the Remote DMA channels
are used to transfer data between dedicated network memory, and common system memory. In normal operation, the
remote DMA channels transfer data between the network
memory and an 1/0 port, and the system transfers between
the 110 port and the system memory. The system transfers
are typically accomplished using either the processor, or a
DMA controller.

:Z

The Remote DMA channels work in both directions; pending
transmission packets are transferred into the network memory, and received packets are transferred out of the network
memory. Transfers into the network memory are known as
remote write operations, and transfers out of the network
memory are known as remote read operations. A special
remote read operation, send packet, automatically removes
the next packet from the receive buffer ring.
7.1 Performing Remote DMA Operations

Before beginning a remote DMA operation, the controller
must be informed of the network memory it will be using.

Both the starting address (RSARO,1) and length (RBCRO,1)
are set before initiating the remote DMA operation. The remote DMA operation begins by setting the appropriate bits
in the Command Register (RDO-RD3). When the remote
DMA operation is complete (all of the byles transferred), the
RDC bit (Remote DMA Complete) in the ISR (Interrupt
Status Register) is set and the processor receives an interrupt, whereupon it takes the appropriate action. When the
Send packet command is used, the controller automatically
loads the starting address, and byte count from the receive
buffer ring for the remote read operation, and upon completion updates the boundary pOinter (BNRY) for the receive
buffer ring. Only one remote DMA operation can be active at
a time.
7.2 Hardware Considerations

The Remote DMA capabilities of the NIC were designed to
require minimal external components and provide a simple
implementation. An eight bit bi-directional port can be implemented using just two 374 latches (see the DP8390
Hardwre Design Guide). All of the control circuitry is provided on the DP8390. In addition, bus arbitration with the local
DMA is accomplished within the NIC in such a way as to not
lock out other devices on the bus (see the DP8390 Datasheet).

1-148

StarLAN With The DP839EB
Evaluation Board

National Semiconductor
Application Note 498
Wesley Lee

OVERVIEW

RECEIVER/SQUELCH

Because of the identical packet structures between StarLAN (IEEE 802.3 1base5) and Ethernet (10base5), the
DP8390 Network Interface Controller (NIC) will operate in all
versions of IEEE 802.3 based networks. To evaluate the
DP8390 in StarLAN applications, the DP839EB Evaluation
Board can be used with a "daughter card" that replaces the
EthernetlCheapernet front end with a Star LAN front end.
The StarLAN front end consists of an RS-422/485 type
transceiver and a 1 Mbitl s Manchester encoder/decoder
(EN DEC), as shown below. The 82C550A, manufactured by
Chips and Technology, and the MK5035N, manufactured by
Mostek corporation, can provide the required ENDEC functions for the NIC.

Since the cabling may be bundled together and routed close
to heavy electrical equipment, squelch circuitry is necessary
to reject signals generated from crosstalk between adjacent
wires and impulse noise from large equipment. Proper noise
immunity may be implemented using a second-order Butterworth filter with a 2 MHz cutoff and setting a 600 mV
squelch level. Because RS-422 receivers typically have
200 mV threshold levels, these inputs must be skewed to
600 mV. This may be implemented by using a resistor ladder which holds the inputs 600 mV apart (see Squelch Adjustment). When an incoming signal exceeds the 600 mV
threshold, the receiver is enabled.
As shown in the Squelch Level Adjustment figure, two receivers are used for the receive/squelch function. One receiver sets the 600 mV input threshold and is used by the
ENDEC to drive its internal squelch circuitry; the other receiver presents the actual unskewed data to be decoded.

CABLING

Since a significant number of StarLAN networks are expected to use existing twisted pair telephone wiring, DTEs will be
connected to wall outlets, which in turn, will be connected to
wiring closets where the StarLAN hubs will be located. The
cabling used typically will consist of 26-22 gauge, unshielded twisted pairs with maximum cable length approximately
250 meters (800 tt) from Hub to DTE. If 5 levels of hub are
used, the network may extend up to 2.5 Km.
TRANSCEIVER

The transceiver connects to two twisted pair phone wires,
one for transmit, the other for receive and is isolated by two
pulse transformers. Some pulse transformers also provide
rise time limiting to reduce EMI. The transceiver circuitry is
based on the DS8923 dual receiver/driver combination.
Two of the receivers are used to provide receive and
squelch functions.

TRANSMITTER

The transmitter is comprised of one RS-422 driver provided
in the DS8923 dual line driver-receiver package. The driver
is enabled using the external transceiver output of the Manchester ENDEC, which is asserted coincident with the first
bit of valid data and is de-asserted two bit times following
the last bit. This allows generation of the 2-bit idle signal,
marking the end of the packet.
82C550A INTERFACE TO THE NIC

The 82C550A interfaces to the DP8390 via 5 inverters to
provide the proper polarity of CRS, COL, TXE, RXC, and
LBK. The normal mode (MODE = 1) is selected to allow an
external transceiver to be used. The squelch level input,
/RxDI must be connected to pin 1 of the DS8923 to attain

StarLAN Front End for the DP8390
Isolation

Controller

Transceiver Block
1 Mb/s
ENDEC

RX Pair
DP8390
NIC

TX Pair

TLlF/9S46-1

1-149

Squelch Level Adjustment

Daughter Card Pin Assignment

+5V

SNI Socket (U9) Pin

1

RX+~
tOOA
RX-

Connection

COL

2

RXD

3

CRS

4

RXC

6

GND

7

lBK

10

TXD

11

TXC

12

TXE

13

TX - (Pin 2 of Phone Jack)

14

TX + (Pin 1 of Phone Jack)

16

IRST

TL/F/9346-2

the proper input threshold (600 mY). The RxDI input contains the actual data to be decoded to NRZ.
During transmission, encoded data comes from the TxDO
output and the external transceiver is enabled by the ITxDO
output. The 1 MHz transmit clock is generated from the
16 MHz on-Chip oscillator.
MK5035N INTERFACE TO THE NIC

19

+5V

The MK5035N interfaces directly to the NIC when CMODE
is selected high. The MK5035N is functionally similar to the
82C550A; IRC and RD are the squelch and receive data
inputs, and IXEN and XD are the external transceiver enable and transmit data outputs. XSEl input has been selected low to allow the use of an 8 MHz crystal.

21

RX - (Pin 6 of Phone Jack)

22

RX + (Pin 3 of Phone Jack)

INSTALLATION OF THE DAUGHTER CARD
Once the daughter card has been assembled, the DP8391
Serial Network Interface chip (socketed) can be removed
and replaced with the daughter card. Prior to installing the
daughter card, the following jumpers must be removed:
J1C-J7C, J1E-J7E, and JY (alternatively, JB some
DP839EB boards have marked the oscillator jumper as JY
or JB. This jumper lies just above the DP8391). All demo
software that is provided with the DP839EB also works in
StarLAN. The DP839EB is attached to the StarlAN network
by connecting twisted pair phone cable between the 8-pin
RJ-45 modular jack and the hub.

BUILDING A StarLAN DAUGHTER CARD FOR THE
DP839EB

The DP8391 Serial Network Interface of the DP839EB Evaluation Board has been socketed to allow insertion of a StarLAN daughter card in its place. Unused pins on the DP8391
have been wired with additional signals that are necessary
for a StarlAN daughter card. The phone jack is connected
to the receiver and transmit pairs. The schematic of a working daughter card is attached.

StarLAN Daughter Card Installation

DP839EB
Evaluation Board

TL/F/9346-3

1-150

SUPPORTING DOCUMENTS

DAUGHTER CARD PARTS LIST (Continued)
Crystal
8 MHz (for MK5035N)
NDKAT-51
16 MHz (for 82C550A)
NDKAT-51

The following references can be used to obtain further information.
-

DP8390N-1 Data Sheet

-

Advanced Peripherals IEEE 802.3 Local Area Network
Guide

-

DP8390 Data Sheet Addendum, Sept. 1987
IEEE 802.3 1Base5 ("StarLAN")

-

82C550A Data Sheet (a product of Chips and Technology Inc.)

-

MK5035N Data Sheet (a product of Mostek Corporation)
PT3589 pulse transformer Data Sheet (a product of
VALOR Electronics)

-

BH500-1436 pulse transformer Data Sheet (a product of
BH Electronics)

-

NP5413 pulse transformer Data Sheet (a product of
Nano Pulse Inc.)

ICs and Other
DS8923 (U2)
MM74HC74 (U1)
MM74HC04 (U7)
Manchester ENDECs
82C550A (U6)
MK5035N
Pulse Transformers
PT3589
NP5413
BH500-1436
LIST OF OTHER MANUFACTURERS
MANCHESTER ENCODER/DECODERS

CONSIDERATIONS FOR USING REV. C DP8390N·1

82C550A
Chips and Technologies
Ken Buntaran, Technical Marketing Engineer
521 Cottonwood Drive
Milpitas, CA 95035
(408) 434-0600

(1) In order for the 4-byte packet header to be properly written by the DP8390, the DMA clock to Network clock may
not be greater than 4:1; thus, in StarLAN applications, the
DMA clock may not exceed 4 MHz.
Higher bus clock speeds (up to 8 MHz), however, can be
achieved by manipulating the packet header under software
control. If you are using a DMA clock which is greater than
4 MHz, the DP8390 occasionally copies the Lower Byte
Count into the header twice, and fails to write the Upper
Byte Count. The Upper byte count, however, may be calculated by subtracting the Next Page Pointer (second byte in
the header) with the Next Page Pointer of the previous
packet. See DP8390 Datasheet Addendum section 3.1.

MK5035N
Mostek Corporation
1310 Electronics Drive
Carrollton, TX 75006
(214) 466-6000

PULSE TRANSFORMERS
BH Electronics
John DeCramer, Engineering Manager
604 Michigan Road
Marshall, MN 56258
(507) 532-3211

(2) Due to the asynchronous nature between the local and
remote DMAs, a race condition exists which may cause the
local DMA to use the remote DMA's address counter or vice
versa. This problem is fixed using a DMA clock synchronous
to the transmit clock of the encoder, or a clock derived from
the transmit clock.
(3) Because of problem (1) above, the "send packet" command will not operate at bus clock frequencies above
4 MHz. Instead, use the Remote Read DMA and update
BNDRY under software control. Note that there is a special
consideration for updating BNDRY as specified in section
3.0 of the DP8390 Data Sheet Addendum. BNDRY must
always be kept at least one 256-byte buffer behind the
CURR pointer.

Nano Pulse Industries, Inc.
440 Nibus Street
P.O. Box 9398
Brea, CA 92621
(714) 529-2600
Pulse Engineering, Inc.
Rey Bautista, DeSign Engineer
7250 Convoy Court
San Diego, CA 92111
(619) 268-2449

(4) Rev. C parts will be marked as DP8390N-1 and will oper·
ate at a maximum bus clock of 8 MHz.

VALOR Electronics, Inc.
Ernest R. Jensen, Product Development
6750 Nancy Ridge Drive
San Diego, CA 92121
(619) 458-1471

DAUGHTER CARD PARTS LIST

Resistors
1200 (R3)
5600 (R4)
2.2 KO (R1, 2)
10 MO (R7 or R8)

1
1
2
1

30pF (C3)
15 pF (C7, 8 or 15,16)
0.1 ,..F (C1 , 2)
35,..F (C11)

1
2
2
1

PHONE JACK
Nova-Tronic, Inc.
Jeff Hines, Sales Manager
4701 Patrick Henry Drive #24
Santa Clara, CA 95054
(408) 727·9530

Capacitors

CRYSTALS

NDK·America
20300 Stevens Creek Blvd.
Cupertino, CA 95014
(408) 255-0831

Inductors
40,..H (L1)

1-151

AN·498

StarLAN Front End Using the MK5035N
RECEIVER/
DRIVER
DSB923
U2

Pulse
Transformer
U3

n

"fn
RX+

RXJl/21

.----,
10

20· vee

,

~ i .

5 1Re

RENA 6

3 CRS

CLSN 7

1 COL

XSEL

B

RX+· 22

Lov

XeLSN £5V

4

LBACK

~~~!~;-LEN---4------------118 XEN
1RD

14

,,

TX-,
Jl/13 ,

SNI SOCKET
Jl

eMODE iL5V

,

,,,
,,
•,

""n
TX+

+5V

+5V

,

I

~I

ENCODER/
DECODER
MK5035N
U5

3
12 __ •

._---

19

~
13'
,
C7
XD
._

~

..

h

fe'
! 15(F

_____

(

'
,

,

,

14 IXI

'

'-IX2

BCd

TCLK 16

11 TXC

TENA 15

12 TXE

TX 17

10 TXD

RX9

2 RXD

RCLK B

4 RXC

RESET 11

16 RST

GND· 10

CB
15pF
RJ-45
Modular
Jack

RX_· 21

.L 5V

PROVIDES A 4 MHz SYNCHRONOUS
BUS CLOCK FOR THE DPB390.
REQUIRED FOR REV e, BUT
!I~ NOT FOR DPB390BN.
Blx1

RX+ 3
RX- 6
TX+l
TX- 2
Vee14. GND71 ,.

19 35}'F
Cll

-,
TLiF 19346-4

StarLAN Front End Using the 82C550A
RECEIVER/
DRIVER
058923

Pulse
Transformer
U3

j "
.----.

"P>
RX+
RXJl/21

+5V

U2
+5V
• ______ .3

+5V

t

R2.
2.2k.D. 16 •

:

••

: 8

•

~I

RxDI
81 RXDI

•'14

•••

._-.12

TxEN 4

•

".

11 TXC

•
12 •

1°ITXD

TxDI15

•

• ~ I' C16
6~,",,1C:
15Rf

21 TxDO

13~

:.

RxOO
l11Xl

('""!------.

RxCLK

( , , ' "I X2
C15
15 pf
RJ-45
Modular
Jack

8~

RX+ 3
RX- 6
TX+l
TX- 2

-===J

Vee 14, GND7LI

SNI SOCKET
Jl

3•

TxDO

""j
TXJl/13

MM74HC04
U7
.----.

15
CRS
20 V
13 CC
CDTI
17
6 TlAROff CDTO
10
GND
3 I MODE
18
TSRC
TxCLK

.;.l.I

•••
TX+

ENCODER/
DECODER
82C550A
U5

16
14

•
9.•

·

••.8

2 RXD
4 RXC

•
~LBK
•.. _-_.•

PROVIDES A 8101Hz SYNCHRONOUS
BUS CLOCK fOR THE DP8390.
REQUIRED fOR REV C, BUT
NOT fOR DP8390BN.
8 Xl
NOTE THAT SINCE BUS CLOCK IS
GREATER THAN 4MHz, REMOTE
READ DMAs MUST BE USED.

Veep; 35}'f
Cll

TL/F/9346-5

S6t-NY

~

Reliability Data Summary for DP8392

REF: TEST LAB FILES

TESTS PERFORMED

RDT25406
RDT25500

RDT26627
RDT26638

Operating Life Test (OPL) (100'C; biased)
Operating Life Test (OPL) (125'C; biased)

RDT26562

Temperature and Humidity Bias Test (THBT) (85'C; 85%
R.H.; biased)

ABSTRACT

Temperature Cycle Test (TMCL) (-40'C,
ased)

DP8392 Coaxial Transceiver Interface parts from 8 lots
were subjected to Operating Life Test, Temperature and
Humidity Bias Test, Temperature Cycle Test, and Electrostatic Discharge Test.

+ 125'C;

unbi-

Electrostatic Discharge Test (ESD) (Human body model:
R = 15000; C = 120 pF)

PURPOSE OF TEST

CONCLUSIONS

Evaluation of new device and qualification of U.K. fab.

1. The DP8392AN exceeds the IEEE 802.3 specification of
1 million hours Mean Time Between Failure (MTBF).

TEST SAMPLE DESCRIPTION/HISTORY
Lot

Device

1

DP8392

N, 16 Leads 8509

NSSC

NSEB

2

DP8392

N, 16 Leads 8513

NSSC

NSEB

3

DP8392

N, 16 Leads 8526

NSSC

NSEB

4

DP8392

N, 16 Leads 8552

NSSC

NSEB

5 DP8392A(-4) N, 16 Leads 8620

NSUK

Package

2. U.K. fab results are comparable to those of Santa Clara.
On ESD testing all pins passed at 1000V except for pin 7
(TX+).

Date
Fab
Assembly
Code Location Location

6 DP8392A(-5) N, 16 Leads 8637

NSUK

7 DP8392A(-5) N, 16 Leads 8637

NSUK

8 DP8392A(-5) N, 16 Leads 8637

NSUK

RESULTS
Time Point-Number of Failures
Test

Temperature

Lot

Hours

Fab

168
OPL

THBT

100'C
100'C
125'C
125'C
100'C
100'C
100'C
100'C
85'C; 85% R.H.

1
2
3
4
5
6
7
8

NSSC
NSSC
NSSC
NSSC
NSUK
NSUK
NSUK
NSUK

0/50
0/50
0/74
0/100
0/60

1

NSSC
NSSC
NSSC

0/50
0/50
0/75

2
3

500

1000

0/50
0/50

0/50
0/50

0/100

0/100

0/100

0/33
0/31
0/31

0/33
0/31
0/31

0/33
0/31
0/31

0/50
0/50
0/75

0/50
0/50
0/75

336

0/33
0/31
0/33

Cycles

TMCL

-40'C,

+ 125'C

4

NSSC

500

1000

2000

3000

0/70

0/70

0/70

0/70

1-154

2000

:::c

ELECTROSTATIC DISCHARGE TEST (ESD) RESULTS

Further characterization has been done to determine individual pin ESO damage thresholds. In particular, for pin 7
(TX +), 80 parts from 4 wafer lots were tested. Pin 7 ESO
damage thresholds varied
from 200V-300V
to
2000V-3000V, with a mean of 1800V.

26 parts from 4 wafer lots were tested by the Human Body
Model test condition; R = 15000; C = 120 pF. First ground
was held common, then VEE. 5 positive and 5 negative pulses were applied for each pinlvoltage combination.

Pin

Function

MTBF (MEAN TIME BEFORE FAILURE)
CONSIDERATIONS

Voltage-Number
of Failures
500V

1000V

1

CO+

0/26

0/20

2

CO-

0/26

0/20

3

RX+

0/26

0/20

4

VEE

0/26

0/20

5

VEE

0/26

0/20

6

RX-

0/26

0/20

7

TX+

6/26

13/20

8

TX-

0/26

0/20

9

HBE

0/26

0/20

10

GNO

0/26

0/20

11

RR+

0/26

0/20

12

VEE

0/26

0/20

13

VEE

0/26

0/20

14

RXI

0/26

0/20

15

TXO

0/26

0/20

16

COS

0/26

0/20

301,000 device hours at 100'C, 0 failures
Pd = 800 mW

Then:

3
3

0...

45'C/W

Chi-square statistics, 60% confidence

C
"'0

MTBFmin at 25'C ambient = 93,000,000
device hours.

~

MTBFmin at 70'C ambient
device hours.

1-155

~

c

~

Ea = 0.7 eV
8ja =

~

~

fI)

Results total: 212, 000 device hours at 125'C, 0 failures
Assume:

!!!.

=

5,100,000

00

N

Section 2

High Speed Seriall
IBM Data Communications

Section 2 Contents
DP8340INS32440 IBM 3270 Protocol Transmitter/Encoder .............................
DP8341INS32441 IBM 3270 Protocol Receiver/Decoder................................
DP8342INS32442 High-Speed 8-Bit Serial Transmitter/Encoder. . . . . . . . .. . . .. . . .. . .. . . . .
DP8343/NS32443 High-Speed 8-Bit Serial Receiver/Decoder ...........................
AN-496 the BIPLAN DP8342/DP8343 Biphase Local Area Network. . . . . . . . . . . . . . . . . . . . . . .
DP8344 Biphase Communications Processor-BCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AB-33 Choosing Your RAM for the Biphase Communications Processor . . . . . . . . . . . . . . . . . ..
AB-34 Decoding Bit Fields with the "JRMK" Instruction. .. .. .. ... ... .. .. .. . . .. ... . . .. .. ..
AB-35 Receiver Interrupts/Flags for the DP8344 Biphase Communications Processor. . . . . . .
AN-517 Receiving 5250 Protocol Messages with the Biphase Communications Processor ...
AN-499 "Interrupts"-A Powerful Tool of the Biphase Communications Processor..........
AN-504 DP8344 BCP Stand-Alone Soft-Load System...................................
AN-516 Interfacing the DP8344 to Twinax .............................................

2-2

2-3
2-12
2-23
2-33
2-44
2-63
2-179
2-181
2-183
2-184
2-187
2-192
2-203

C

"tI

~National

Q)

CN
<:)
"""
......

~ Semiconductor

Z

(J)
CN

N

DP8340/NS32440 IBM 3270 Protocol
TransmitterIEncoder

"""
"""

<:)

General Description

Features

The DP8340/NS32440 generates a complete encoding of
parallel data for high speed serial transmission which conforms to the protocol as defined by the IBM 3270 information display system standard. The DP8340/NS32440 converts parallel input data into a serial data stream. Although
the IBM standard covers biphase serial data transmission
over a coax line, the DP8340/NS32440 also adapts to general high speed serial data transmission over other than
coax lines, at frequencies either higher or lower than the
IBM standard.

•
•
•
•
•
•
•
•

The DP8340/NS32440 and its complementary chip, the
DP8341 (receiver/decoder) have been designed to provide
maximum flexibility in system designs. The separation of the
transmitter/receiver functions provides convenient addition
of more receivers at one end of a biphase line without the
need of unused transmitters. This is specifically advantageous in control units where typical biphase data is multiplexed over many biphase lines and the number of receivers
generally exceeds the number of transmitters.

•
•
•
•
•

Ten bits per data byte transmission
Single-byte or multi-byte transmission
Internal parity generation (even or odd)
Internal crystal controlled oscillator used for the generation of all required chip timing frequencies
Clock output directly drives receiver (DP8341) clock input
Input data holding register
Automatic clear status response feature
Line drivers at data outputs provide easy interface to
biphase coax line or general transmission lines
< 2 ns driver output skew
Bipolar technology provides TTL input/output compatibility
Data outputs power up/down glitch free
Internal power up clear and reset
Single + 5V power supply

Connection Diagrams
Dual-In-Line Package

Plastic Chip Carrier

I~ '"
-'

-'


.....

0111

(!)

0110

23

019

22

REG FUll

018

21

AUTO RESPONSE

...

'"
>'"

018

25

AUTO RESPONSE

017

24

TRANSt.lITIER ACTIVE

016

23

PARITY CRT

22
015
014

10

013

11
N

N

i5

.., ...,
f0-

::>
0

'"u

0

-'
u

e

z X
(!)

VCC

017

20

TRANSMITTER ACTIVE

016

19

PARITY CRT

015

18

EVEN/ODD

014

17

DATA OUT
DATA OUT

013

21

EVEN/ODD

20
19

012

10

DATA DELAY

DATA OUT

ClK OUT

11

X2

DATA OUT

GND

12

Xl

'"
N

x

REG lOAD

TL/F/S2S1-1

Top View

>-

...:5e
~

C!j
TLlF/S2S1-19

FIGURE 1
Order Number DP8340/NS32440 J, N or V
See NS Package Number J24A, N24A or V28A

2-3

..
....
..
0

C'I

C")

Block Diagram

en
z
0

C")

GO
Go

Q

AUTO
RESPONSE

CLOCK
OUTPUT

Vec

l.cm
ROO
X2

Tv~::CJ

la.a67.Hz - , :__

CRYSTAL
OSCILLATOR

CONTROL LOGIC

Xl

DATA }

~ 1.;:1~...~_-_-_-_- :

SERIAL
OUTPUTS

L -__.-.....

DELAY

REGISTERS
fULL

012 TO 0111
DATA INPUTS
TL/F/5251-2

FIGURE 2. DP8340/NS32440 Serial BI·Phase Transmitter/Encoder Block Diagram

Functional Description
Figure 2 is a block diagram of the DP8340/NS32440 bi-

while still maintaining even or odd parity in the bit 12 position. This is the format of data word bytes and other commands in the 3270 Standard. The Parity Control input is the
pin which controls when this operation is in effect.

phase Transmitter/Encoder. The transmitter/encoder contains a crsytal oscillator whose input is a crystal with a frequency eight (8) times the data rate. A Clock Output is provided to drive the DP8341 receiver/decoder Clock Input and
other system components at the oscillator frequency. Additionally, the oscillator drives the control logic and output
shift register /format logic blocks.

Another feature of the transmitter/encoder is the internal
TT/ AR (Transmission Turnaround/Auto Response) capability. After each Write type message from the control unit in
the 3270 Standard, the receiving unit must respond with
clean status (bits 2 through 11). With the transmitter/encoder, this function is accomplished simply by forcing the AutoResponse input to the Logic "0" state.

Data is parallel loaded from the sytem data bus to the transmitter/encoder's input holding register. This data is in turn
loaded by the transmitter/encoder to its output shift register
if this register was empty at the time of the load. During this
load, message formatting and parity are generated. The formatted message is then shifted out at the bit rate frequency
to the TTL to biphase block which generates the proper
data bit formatting. The three data outputs, DATA, DATA,
and DATA DELAY provide for flexible interface to the coax
line with a minimum of external components.

Operation of the transmitter/encoder is automatic. After the
first data byte is loaded, the Transmitter Active output is set
and the transmitter/encoder immediately formats the input
data and serially shifts it out its data outputs. If the message
is a multi-byte message, the internal format logic will modify
the message data format for multibyte as long as the next
byte is loaded to the input holding register before the last
data bit of the previous data byte is transferred out of the
internal output shift register. After all data is shifted out of
the transmitter/encoder the Transmitter Active output will
return to the inactive state.

The Control Logic block interfaces to all blocks to insure
proper chip operation and sequencing. It controls the type
of parity generation through the Even/Odd Parity input. An
additional feature provided by the transmitter/encoder is
generation of odd parity and placement in bit 10 pOSition

2-4

Detailed Pin/Functional Description
Crystal Inputs X1 and X2

is edge sensitive, the data present during the logic "0" state
of this input is loaded, and the input data must be valid
before the logic "0" to logic "1" transition. It is after this
transition that the transmitter/encoder begins formatting of
data for serial transmission.

The oscillator is controlled by an external, parallel resonant
crystal connected between the X1 and X2 pins. Normally, a
fundamental mode crystal is used to determine the operating frequency of the osicllator; however, overtone mode
crystals may be used.

Auto Response (TT/ AR)
This input provides for automatic clear data transmission (all
bits in logic "0") without the need of loading all zero's.
When a logic "0" is forced on this inpiut the transmitter / encoder immediately responds with transmission of "clean
status". This function is necessary after the completion of
each write type command and in other functions in the 3270
specification. In the logic "1" state the transmitter/encoder
transmits data entered on the Data Inputs.

Crystal Specifications (Parallel Resonant)
Type
Tolerance

AT-cut crystal
0.005% at 25·C
0.01 % from O·C to + 70·C
Fundamental (Parallel)

Stability
Resonance
Maximum Series Resistance

Dependent on Frequency
(For 18.867 MHz, 500.)

Load Capacitance

15 pF

R
C
TO PIN X2 ~L-PIN (14)
r - Vcc

..L

CJ

TO PIN Xl
PIN (13)

....-__T...
_

CRYSTAL
SEE (FIG. 16)

FREQ

R

Even/Odd Parity
This input sets the internal logic of the DP8340/NS32440
transmitter/encoder to generate either even or odd parity
for the data byte in the bit 12 position. When this pin is in the
logic "0" state odd parity is generated. In the logic "1" state
even parity is generated. This feature is useful when the
control unit is performing a loop back check and at the
same time the controller wishes to verify proper data transmission with its receiver/decoder.

C

10 MHz to 5000.
30 pF
20 MHz ±10%
>20 MHz

1200.
15 pF
±10%

TL/F/5251-3

Parity Control/Reset
Depending on the type of message transmitted, it is at times
necessary in the IBM 3270 specification to generate an additional parity bit in the bit 10 position. The bit generated is
odd parity on the previous eight (8) bits of data. When the
Parity Control input is in the logic" 1" state the data entered
at the Data Bit 10 position is placed in the transmitted word.
With the Parity Control input in the logic "0" state the Data
Bit 10 input is ignored and odd parity on the previous data
bits is placed in the normal bit 10 position while overall word
parity (bit 12) is even or odd (controlled by Even/Odd Parity
input). This eliminates the need for external logic to generate the parity on the data bits.
Truth Table

FIGURE 3. Connection Diagram
If the DP8340/NS32440 transmitter is clocked by a system
(clock crystal oscillator not used), pin 13 (X1 input) should
be clocked directly using a Schottky series (74S) circuit. Pin
14 (X2 input) may be left open. The clocking frequency must
be set at eight times the data bit rate. Maximum input frequency is 28 MHz. For the IBM 3270 Interface, this frequency is 18.867 MHz. At this frequency, the serial bit rate will be
2.358 Mbits/ sec.
Clock Output
The Clock Output is a buffered output derived directly from
the crystal oscillator block and clocks at the oscillator frequency. It is designed to directly drvie the DP8341 receiver/
decoder Clock Input as well as other system components.
Registers Full
This output is used as a flag by the external operating system. A logic "1" (active state) on this output indicates that
both the internal output shift register and the input holding
register contain active data. No additional data should be
loaded until this output returns to the logic "0" state (inactive state).

Parity Control Input

Transmitted Data Bit 10

Logic "1"

Data entered on Data Input 10

Logic "0"

Odd Parity on 8-bit data byte

When this input is driven to a voltage that exceeds the power supply level (9V to 13V) the transmitter/encoder is reset.
Serial Outputs-DATA, DATA, and DATA DELAY
These three output pins provide for convenient application
of data to the biphase Coax line (see Figure 15 for application). The Data outputs are a direct bit representation of the
biphase data while the DATA DELAY output provides the
necessary increment to clearly define the four (4) DC levels
of the pulse. The DATA and DATA outputs add flexibility to
the DP8340/NS32440 transmitter/encoder for use in high
speed differential line driving applications.

Transmitter Active
This output will be in the logic "1" state while the transmitter / encoder is about to transmit or in the process of transmitting data. Otherwise, it will assume the logic "0" state
indicating no data presently in either the input holding or
output shift registers.
Register Load
The Register Load input is used to load data from the Data
Inputs to the input holding register. The loading function

2-5

~

'OIl'
N

CO)

Functional Timing Waveforms-Message Format

(J)

Single Byte Transmission

Z
....
o
'OIl'

CO)

CO

D-

C

t

t

TRANSMISSION
TERMINATION

TRANSMISSION
START



ERROR
OUTPUT CONTROL
OUTPUT ENABLE

+IN
DP8341
RECEIVERI
DECODER

1:1:1 PULSE
TRANSFORMER
FIG. 17

BI·PHASE
INPUT
-IN

REG READ
RECEIVER ACTIVE
TL/F/5251-17

FIGURE 16. Typical Applications for IBM 3270 Interface

Rl
150
DATA
DELAY

9011 COAX
(RG62A/Ul

~
3

R5
150

J
5.

+IN

I2
I

R6
120

CONNECT TO
OP8341
RECEIVER

L __ -+-a_...J

-IN

6
GND
TLlF/5251-18
Note 1: Resislance values are in

n,

±5%,

Yo W

Note 2: T1 is a I :1:1 pulse transformer, LMIN = 500 I'H for 18 MHz system clOCk. Pulse Engineering Part No. 5762/Suriace
Part No.IILHA, Valor Electronics Part No. CT1501 or equivalent transformers.
Note 3: Cryslal manufacturer's Midland Ross Corp. NEL Unit Part No. NE·18A (C2560Nl
@ 18.867 MHz.

@

5782M/PE·85762. Technitrol

18.867 MHz and the Viking Group of San Jose, CA Part No. VXB46NS

FIGURE 17. Translation Logic
2-11

Moun~

.....-

~ ~National
~ ~ Semiconductor
..-

...

~ DP8341/NS32441 IBM 3270 Protocol Receiver/Decoder

c

General Description

Features

The DP8341/NS32441 provides complete decoding of data
for high speed serial data communications. In specific, the
DP8341/NS32441 recognizes serial data that conforms to
the IBM 3270 Information Display System Standard and
converts it into ten (10) bits of parallel data. Although this
standard covers biphase serial data transmission over a
coax line, this device easily adapts to· generalized high
speed serial data transmission on other than coax lines at
frequencies either higher or lower than the IBM 3270 standard.
The DP8341/NS32441 receiver and its complementary
chip, the DP8340 transmitter, are designed to provide maximum flexibility in system designs. The separation of transmitter and receiver functions allows addition of more receivers at one end of the biphase line without the necessity of
adding unused transmitters. This is advantageous specifically in control units where typically biphase data is multiplexed over many biphase lines and the number of receivers
generally outnumber the number of transmitters. The separation of transmitter and receiver function provides an additional advantage in flexibility of data bus organization. The
data bus outputs of the receiver are TRI-STATE, thus enabling the bus configuration to be organized as either a
common transmit/receive (bi-directional) bus or as separate
transmit and receive busses for higher speed.

• DP8341/NS32441 receivers ten (10) bit data bytes and
conforms to the IBM 3270 Interface Display System
Standard
• Separate receiver and transmitter provide maximum
system design flexibility
• Even parity detection
• High sensitivity input on receiver easily interfaces to
coax line
• Standard TTL data input on receiver provides generalized transmission line interface and also provides
hysteresis
• Data holding register
• Multi-byte or Single byte transfers
• TRI-STATE receiver data outputs provide flexibility for
common or separated transmit/receive data bus
operation
• Data transmission error detection or receiver provides
for both error detection and error type definition
• Bi-polar technology provides TTL input/output compatibility with excellent drive characteristics
• Single + 5V power supply operation

Connection Diagrams
Dual·ln·Llne Package

Plastic Chip Carrier

i

!5
... :;j

'"

$

;!;

...~

;!;

1 ~ l:l''""
DATA (m)
DATA CONTROL
CLOCK

7

RECEIVER DISABLE

VCC

+AMPLIFlER INPUT

0011

2

-AMPLIFIER INPUT

8 8

DATA ITTL)

0010
DOg

~

ffi

>'0

DATA CONTROL
25

D09

24

DOB

23

007

22
RECEIVER ACTIVE

D08

CLOCK

001

RECEIVER ACTIVE

D06

ERROR

005

REGISTER Ami

004

21

006

OATA AVAILABLE

ERROR

10

20

D05

OUTPUT CONTROL

REGISTER READ

11

19

004

GNO

003
13

D02
OUTPUT ENABLE
TLlF/5238-2

Top View
Order Number DP8341J or DP8341 N
See NS Package Number J24A or N24A
TLlF/5238-1

Order Number DP8341V or NS32441V
See NS Package Number V28A

FIGURE 1

2-12

0

."

Block Diagram

Q)
Co)
.j:Oo

....
.....
Z

RECEIVER
ACllVE

CLOCK

fI)

DATA
CONTROL

Co)

N

.j:Oo
.j:Oo

....
AMPLIFIER
IINPUT)
REGISTER

IDI

DATA
AVAILABLE
RECEIVER
DISABLE

ERROR OUTPUT

PARALLEL OUTPUT DATA
TL/F/5238-3

FIGURE 2. DP8341INS32441 Serial BI-Phase Receiver/Decoder Block Diagram

Block Diagram Functional
Description
Figure 2 is a block diagram of the DP8341 /NS32441. This

register and the holding register are full a Data Overflow
Error will be detected, terminating the message. Data is
read from the holding register through the TRI-STATE Output Buffers. The Output Enable input is the TRI-STATE control for these outputs and the Register Read input signals
the receiver that the read has been completed.

chip is essentially a serial in/parallel out shift register. How·
ever, the serial input data must conform to a very specific
format (see Figures 3-5). The message will not be recognized unless the format of the starting sequence is correct.
Deviations from the format in the data, sync bit, parity or
ending sequence will cause an error to be detected, terminating the message.

When the receiver detects an ending sequence the Receiver Active output will be reset to a logic "0" indicating the
message has been terminated. A message will also terminate when an error is detected. The Receiver Active output
used in conjunction with the Error output allows quick response to the transmitting unit when an error free message
has been received.

Data enters the receiver through the differential input amplifier or the TTL Data input. The differential amplifier is a high
sensitivity input which may be used by connecting it directly
to a transformer coupled coax line, or other transmission
medium. The TTL Data input provides 400 mV of hysteresis
and recognizes TTL logic levels. The data then enters the
demodulation block.

The Error Detection and Identification block insures that valid data reaches the outputs of the receiver. Detection of an
error sets the Error output to a logic "1" and resets the
Receiver Active output to a logic "0" terminating the message. The error type may be read from the data bus outputs
by setting the Output Control input to logic "0" and enabling
the TRI-STATE outputs. The data bit outputs have assigned
error definitions (see error code definition table). The Error
output will return to a logic "0" when the next starting sequence is received, or when the error is read (Output Control to logic "0" and a Register Read performed).

The data demodulation block samples the data at eight (8)
times the data rate and provides signals for detecting the
starting sequence, ending sequence, and errors. Detection
of the starting sequence sets the Receiver Active output
high and enables the input shift register.
As the ten bits of data are shifted into the shift register, the
receiver will verify that even parity is maintained on the data
bits and the sync bit. After one complete data byte is received, the contents of the input shift register is parallel
loaded to the holding register, assuming the holding register
is empty, and the Data Available output is set. If the holding
register is full, this load will be delayed until that register has
been read. If another data byte is received when the shift

The Receiver Disable input is used to disable both the amplifier and TTL Data receiver inputs. It will typically be connected directly to the Transmitter Active output of the
DP8340 transmitter circuit (see Figure 12).

2-13

Detailed Functional Pin Description
DP8340 transmitter also operates at this frequency. The
Clock Output of the transmitter is designed to directly drive
the receiver's Clock Input. In addition, the receiver is designed to operate correctly to a data bit rate of 3.5 MHz.

RECEIVER DISABLE
This input is used to disable the receiver's data inputs. The
Receiver Disable input will typically be connected to the
Transmitter Active output of the DP8340. However, at the
system controller it is necessary for both the transmitter and
receiver to be active at the same time in the loop-back
check condition. This variation can be accomplished with
the addition of minimal external logic.

RECEIVER ACTIVE
The purpose of this output is to inform the external system
when the DP8341INS32441 is in the process of receiving a
message. This output will transition to a logic "1" state after
the receipt of a valid starting sequence and transition to
logic "0" when a valid ending sequence is received or an
error is detected. This output combined with the Error output
will inform the operating system of the end of an error free
data transmission.

Truth Table

Receiver Disable

Data Inputs

Logic "0"

Active

Logic "1"

Disabled

ERROR
The Error output transitions to a logic "1" when an error is
detected. Detection of an error causes the Receiver Active
and the Data Available outputs to transition to a logic "0".
The Error output returns to a logic "0" after the error register has been read or when the next starting sequence is
detected.

AMPLIFIER INPUTS

The receiver has a differential input amplifier which may be
directly connected to the transformer coupled coax line. The
amplifier may also be connected to a differential type TTL
line. The amplifier has 20 mV of hysteresis.

DATA INPUT

REGISTER READ
The Register Read input when driven to the logic "0" state
signals the receiver that data in the holding register is being
read by the external operating system. The data present in
the holding register will continue to remain valid until the
Register Read input returns to the logic "1" condition. At
this time, if an additional byte is present in the input shift
register it will be transferred to the holding register, otherwise the data will remain valid in the holding register. The
Data Available output will be in the logic "0" state for a
short interval while a new byte is transferred to the holding
register after a register read.

This input can be used either as an alternate data input or
as a power-up check input. If the system designer prefers to
use his own amplifier, instead of the one provided on the
receiver, then this TIL input may be used. Using this pin as
an alternate data input allows self-test of the peripheral system without disturbing the transmission line.
DATA CONTROL
This input is the control pin that selects which of the inputs
are used for data entry to the receiver.

Truth Table

Data Control

DATA AVAILABLE
This output indicates the existence of a data byte within the
output holding register. It may.also indicate the presence of
a data byte in both the holding register and the input shift
register. This output will transition to the logic "1" state as
soon as data is available and return to the logic "0" state
after each data byte has been read. However, even after the
last data byte has been read and the Data Available output
has assumed the logic "0" state, the last data byte read
from the holding register will remain until new data has been
received.

Data input To

Logic "0"

Data Input

Logic "1"

Amplifier Inputs

Note: This input is also used for testing. When the input voltage is raised to
7.SV the chip resets.

CLOCK INPUT
The input is the internal clock of the receiver. It must be set
at eight (8) times the line data bit rate. For the IBM 3270
Standard, this frequency is 18.87 MHz or a data bit rate of
2.358 MHz. The crystal-controlled oscillator provided in the

2·14

Detailed Functional Pin Description

(Continued)
fined in the table below. The Output Control input is the
multiplexer control for the Data/Error bits.

OUTPUT CONTROL
The Output Control input determines the type of information
appearing at the data outputs. In the logic "1" state data will
appear, in the logic "0" state error codes are present.

Error Code Definition
Data Bit

Truth Table

Error Type
Data Overflow (Byte not
removed from holding register
when it and the input shift
register are both full and new
data is received)

002

Output Control

Data Outputs

Logic "0"

Error Codes

Logic "1"

Data

OUTPUT ENABLE
The Output Enable input controls the state of the
TRI-STATE Data outputs.

003

Parity Error (Odd parity detected)

004

Transmit Check conditions
(existence of errors on any or all
of the following data bits: 003,
005, and 006

Truth Table
Output Enable

TRI-STATE
Data Outputs

Logic "0"

Disabled

Logic "1"

Active

DATA OUTPUTS
The DP8341 has a ten (10) bit TRI-STATE data bus. Seven
bits are multiplexed with error bits. The error bits are de-

005

An invalid ending sequence

006

Loss of mid-bit transition
detected at other than normal
ending sequence time

007

New starting sequence detected
before data byte in holding
register has been read

008

Receiver disabled during
receiver active mode

Message Format
Single Byte Transmission

t

t

TRANSMISSION
START

TRANSMISSION
TERMINATION

Multi-Byte Transmission
PARITY
BYTE X

TLlF/5238-4

FIGURE 3. IBM 3270 Message Format

2-15

Message Format (Continued)
DATA

RECEIVER
ACTIVE _ _ _ _ _ _ _ _ _-1

DATA _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1
AVAILABLE

r--

REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - .
READ
U

TL/F/5238-5

FIGURE 4a. Single Byte Message

DATA~~~~~
LINE QUIESCE

I

CODE
VIOLATION

Ir--1st BYTE -r-----2nd
I
II
I ENDING I
BYTE - - ••• r--LAST BYTE - - SEQUENCE

RECEIVER
ACTIVE _ _ _ _ _ _ _ _ _...

nL___...-Ir ...

DATA _ _ _ _ _ _ _-r-_ _ _ _....
AVAILABLE
_

REGISTER
READ

_

u

_

L

-----------------,U
TLiF/5238-6

FIGURE 4b. Multi-Byte Message

DATA

LINE QUIESCE

I

I

I

CODE
VIOLATION I----CORRECT DATA BYTE---I

RECEIVER
ACTIVE _ _ _ _ _ _ _ _ _.....

DATA _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---J
AVAILABLE

ERROR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

REGISTER
READ

~

-----------------------.....:-----,U

OUT~T--------------------------~~

CONTROL

L . ._ _.....

TLiF/5238-7

FIGURE 5. Message with Error

2-16

Absolute Maximum Ratings

(Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, Vee

Maximum Power Dissipation" at 25'C
Cavity Package
2040mW
Dual-In-Line Package
2237mW
Plastic Chip Carrier
1690 mW
'Derate cavity package 13.6 mwrc above 25'C; derate PCC package

7V

Input Voltage

+5.5V

Output Voltage

13.5

5.25V

Storage Temperature Range

-65'C to + 150'C

Lead Temperature (Soldering, 10 seconds)

mwrc above 25°C; derate Dual-In-Line package 17.9 mW/"C above

25'C.

Operating Conditions

300'C

Min
Supply Voltage, (Vecl

4.75

Max
5.25

Units
V

0

+70

'C

Ambient Temperature, (TA)

Electrical Characteristics (Notes 2, 3, and 5)
Symbol

Parameter

Conditions

Min

VIH

Input High Level

VIL

Input Low Level

VIH-VIL

Data Input Hysteresis (TTL. Pin 4)

VeLAMP

Input Clamp Voltage

liN = -12 mA

IIH

Logic "1" Input Current

Vee = 5.25V, VIN = 5.25V

IlL

Logic "0" Input Current

Vee = 5.25V, VIN = 0.5V

VOH

Logic "1" Output Voltage

10H = -100/J-A

3.2

10H = -1 mA

2.5

VOL

Logic "0" Output Voltage

10L = 5mA

los

Output Short Circuit Current

Vee = 5V, VOUT = OV
(Note 4)

-10

loz

TRI-STATE Output Current

Vee = 5.25V, Vo = 2.5V
Vee = 5.25V, Vo = 0.5V

Typ

Max

0.8

AHYS

Amplifier Input Hysteresis

Ice

Power Supply Current

Units
V

2.0

2.0

0.4

V
V

-0.8

-1.2

V

2

40

/J- A

-20

-250

/J- A

3.9

V
V

3.2
0.35

0.5

V

-20

-100

mA

-40

1

+40

/J- A

-40

-5

+40

/J- A

5

20

30

mV

160

250

mA

Vce = 5.25V

Timing Characteristics (Notes 2, 6, 7, and 8)
Min

Typ

Max

Units

TOI

Symbol

Output Data to Data Available
Positive Edge

Parameter

Conditions

5

20

40

ns

T02

Register Read Positive Edge to Data
Available Negative Edge

10

25

45

ns

T03

Error Positive Edge to Data Available
Negative Edge

10

30

50

ns

T04

Error Positive Edge to Receiver Active
Negative Edge

5

20

40

ns

T05

Register Read Positive Edge to Error
Negative Edge

20

45

75

ns

T06

Delay from Output Control to Error Bits
from Data Bits

5

20

50

ns

T07

Delay from Output Control to Data Bits
from Error Bits

5

20

50

ns

T08

First Sync Bit Positive Edge to Receiver
Active Positive Edge

•

I

3.5 x T
+70

2-17

ns

Timing Characteristics (Notes 2, 6, 7, and 8) (Continued)
Symbol

Parameter

Conditions

Min

TOg

Receiver Active Positive Edge to First Data
Available Positive Edge

T010

Negative Edge of Ending Sequence to
Receiver Active Negative Edge

t011

Data Control Set·Up Multiplexer Time Prior
to Receiving Data through Selected Input

40

TPWI

Register Read (Data) Pulse Width

TpW2

Register Read (Error) Pulse Width

TpW3

Typ

Max

Unite

92 x T

ns

11.5 x T
+ 50

ns

30

ns

40

30

ns

40

30

ns

Data Available logic "0" State between
Data Bytes

25

45

ns

Ts

Output Control Set·Up Time Prior to
Register Read Negative Edge

0

-5

ns

TH

Output Control Hold Time After the
Register Read Positive Edge

0

-5

ns

TZE

Delay from Output Enable to logic "1" or
logic "0" from High Impedance State

load Circuit 2

TEZ

Delay from Output Enable to High Imped·
ance State from logic "1" or logic "0"

load Circuit 2

FMAX

Data Bit Frequency (Clock Input must be
8 x the Data Bit Frequency)

(Note 9)

25

35

ns

25

35

ns

3.5

MBits/s

DC

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified, min.lmax. limits apply across the O'C to + 70'C temperature range and the 4,75V to 5.25V power supply range. All typical
values are for TA ~ 25'C and Vee ~ 5.0V.
Note 3: All currents into device pins are shown as positive; all currents out of device pins are shown as negative; all voltagea are referenced to ground, unless
otherwise speCified. All values shown as max. or min. are so classKied on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: Input characteristics do not apply to amplifier inputs (pins 2 and 3).
Note 6: Unless otherwise specified, all AC measurements are referenced to the 1.5V level of the input to the 1.5V level of the output and load circuit 1 is used.
Note 7: AC tests are done with input pulses supplied by generators having the following characteristics: ZOUT ~ 50n and T, ,; 5 ns, Tf ,; 5 ns.
Note 8: T ~ 1/(clock input frequency), units for "T" should be n•.
Note 9: 28 MHz clock frequency corresponds to 3.75% litter when referenced to Figure 10.

vee

Vee

• Rl=lk

RL=2k

•

l'''''u...

I.....
I~ ..

I~

r- 15PF

I""

Load Circuit 1

,

-. f-

R2=2k"

."
~t
";r-

,.

-~

~

f~

TLlF/5238-8

Load Circuit 2
FIGURE 6. Test Load Circuits

2·18

Timing Waveforms

j 1.6V

~~m~ ---j1.5V

Dg~T~U

_ _ _ _--{

DATA
AVAILABLE

REGISTER
READ

(Z~Z:5IV r-----------------J:"(VO;HT~
I- TD1

(Z - O.5~

(OUTPUT CONTROL = Hil

0.51V

+-(VOH + D.iIV

y--------.\I
--------~I

I~

rlPW11
----------------..\i

I- TD2

'1,.-------~---

L.....!t

TL/F/5238-9

FIGURE 7. Data Sequence Timing

\

DATA
AVAILABLE

I-TD3--!

't

RECEIVER
ACTIVE

-TD4-!

t

;(

ERROR

I4-TD5-.1
REGISTER
READ
TS

--I

\

I

I - TPW2--I-TH-1

/,

'\

OUTPUT
CONTROL

~TD6-o-1

D02-DOa

LTD7 -o-1

X

DATA BITS

X

ERROR BITS

DATA BITS
TLlF/5238-10

FIGURE 8. Error Sequence Timing

I 1

I1 I1 I

Vl(f&~~ON

I1 I

I 0 IMCV I MCV I

DATA

•

~---(1C~--J1J
-I

1-

I-

TDB

TD101

RECEIVER _ _ _ _ _ _ _ _ _ _ _ _--'~;O'I------.....,L._ _ __
ACTIVE
•

I-TDB-I
DATA
AVAILABLE

1"----------

-------------~I,;o.__I

TL/F/5238-11

FIGURE 9. Message Timing

2-19

Timing Waveforms

(Continued)

-- BT±(T-25ns)--

T=

CLOCK INPU; FREQUENCY

4T±(T-25ns)-

---1f--~r---~'----\---+--- VIN-

TLIF/5238-12

FIGURE 10. Data Waveform Constraints: Amplifier Inputs

T=

Note:

IT, -

Ttl

s

CLOCK

INPU~ FREQUENCY

TL/F/5238-13

10 ns

FIGURE 11. Data Waveform Constraints: Data Input (TTL)

2-20

Typical Applications

IPARITY CONTROL ....._...a..:::..;..._.....JL.;.;;:......,

I
I

AUTO RESPONSE
OP8340
TRANSMITTER!
ENCOOER

I

~COAX

REG FULL

U ,'",W"

TRANSMITTER
ACTIVE

I
I
I

RECEIVER
OISABLE

OATA
AVAILABLE

.--~;"""-L-L.....,

ERROR

+IN

ail+-----I
In
1:; OUTPUT CONTROL

OPB341
RECEIVER!
OECOOER

OUTPUT ENABLE

1:1:1 PULSE
TRANSFORMER
FIG.14

BI·PHASE
INPUT
-IN

I

RECEIVER ACTIVE
TL/F/5238-14

Note 3: Crystal manufaclurers: Midland Ross Corp.
NEL Unit Part No. NE18A (C2560N)

@

The Viking Group Part No. VXB-46NS

18.867 MHz
@

18,867 MHz. Located in San Jose, CA.

FIGURE 12. Typical Application for IBM 3270 Interface
~C------~----'---------~~
1k
1k

VIN+

vtN-

---------+------'
TL/F/5238-15

FIGURE 13. Equivalent Circuit for DP8341 /NS32441 Input Amplifier

2-21

Typical Applications (Continued)
+5V

1

116---,
r-A DS3487 A

Rl
150

:~\ ~~-l~~-i~o-~~~.,

900 COAX
(RG62A/U)

tfj
3

R6

R5
150

I2
I

L_-*a-..J

J

120

+IN 58
CONNECT TO
OP8341
RECEIVER
-IN
6

GNO
TL/F/5238-16

Note 1: Resistance values are in

n, ± 5%,

Y.W

Nota 2: Tl is a 1:1:1 pulse transformer, LMIN ~ 500 I'H for 18 MHz system clock
Pulse Engineering Part No. 5762/Surface Mount, 5762M/PE-85762
Valor Electronics Part No. CT1501
Technltrol Part No. 11 LHA or equivalent transformers

FIGURE 14, Translation Logic

IDEAL
WAVEFORM
AT TRANSMITTER
END OF CABLE

~~~~~~RM --+1L,----+--+---fLl--+-----I-~=-L
~b
I~I
U
uAT TRANSMITTER
END OF CABLE

~

P1

l I~

VREAL=(95%) VIDEAL

U

TL/F/5238-17

'To maintain loss al 95% of ideal signal, select transformer Inductance
such that
4MINI ~ 10,000
fClK

fClK ~

Note 1: Less inductance will cause greater amplituda attenuation

System Clock

(e.:':~~~:~~HZ)

Nota 2: Greater inductance may decrease Signal
rise time slightly and increase ringing. but these
effects are generally negllgible.

EXAMPLE:
10,000
L ~ 18.87 x 106 .... L(MIN) ~ 530I'H

FIGURE 15. Transformer Selection

2·22

~National

~ Semiconductor
DP8342/NS32442
High-Speed 8-Bit Serial Transmitter/Encoder
General Description

Features

The DP8342/NS32442 generates a complete encoding of
parallel data for high speed serial transmission. It generates
a five bit starting sequence, three bit code violation, followed by a syn bit and eight bit per byte of data plus a parity
bit. A three-bit ending code Signals the termination of the
transmission. The DP8342/NS32442 adapts to generalized
high speed serial data transmission as well as the coax lines
at a maximum data rate of 3.S MHz.
The DP8342/NS32442 and its complementary chip, the
DP8343 (receiver I decoder) have been designed to provide
maximum flexibility in system deSigns. The separation of the
transmitter receiver functions provides convenient addition
of more receivers at one end of a biphase line without the
need of unused transmitters. This is specifically advantageous in control units where typical biphase data is multiplexed over many biphase lines and the number of receivers
generally exceeds the number of transmitters.

•
•
•
•
•
•
•
•

•
•
•
•
•

Eight bits per data byte transmission
Single-byte or multi-byte transmission
Internal parity generation (even or odd)
Internal crystal controlled oscillator used for the generation of all required chip timing frequencies
Clock output directly drives receiver (DP8343) clock input
Input data hold register
Automatic clear status response feature
Line drivers at data outputs provide easy interface to
bi-phase coax line or general transmission media
< 2 ns driver output skew
Bipolar technology provides TTL input! output compatibility
Data outputs power up/down glitch free
Internal power up clear and reset
Single + SV power supply

Connection Diagram
Dual·ln·Llne Package
OUTPUT ENABLE

VCC

BYTECLK

REG LOAD

BITS

REG FULL

BIT7

AUTO RESPONSE

BITS

TRANSMITIER ACTIVE

BIT 5

iiEW

BIT4

EVEN/O~~

BIT 3

DATA OUT

BITZ

DATA OUT

BIT 1

DATA DELAY

X2
Xl

CLKOUT
GNO

TLlF/5236-1

FIGURE 1
Order Number DP8342J, NS32442J
orDP8342J,NS32442N
See NS Package Number J24A or N24A

2-23

N

~
~

N

('I)

~
......
N

~
('I)

r-------------------------------------------------------~----------~

Block Diagram
CLOCK
OUTPUT

VCC

TRANSMInER
ACTIVE

EVEN/OliO
PARITY

.LCEXT
REXT

~

CRYSTAL
OSCILLATOR

C

Xl
BYTE CLOCK
DATA

DATA
DELAY

OUTPUT ENABLE

"'Ita

BITS
BIT 1 TO BIT 8
DATA INPUTS

REGISTERS
FULL

TLlF/5236-2

FIGURE 2

Functional Description
Figure 2 is a block diagram of the DP8342/NS32442 Biphase Transmitter/Encoder. The transmitter/encoder contains a crystal oscillator whose input is a crystal with a frequency eight (8) times the data rate. A Clock Output is provided to drive the DP8342/NS32442 receiver/decoder
Clock Input and other system components at the oscillator
frequency. Additionally, the oscillator drives the control logic
and output shift register/format logic blocks.

the Reset and Output-TRI-STATE® capability. Another feature of the DP8342/NS32442 is the Byte Clock output which
keeps track of the number of bytes transferred.
The transmitter/encoder is also capable of internal TT/ AR
(Transmission Turnaround/Auto Response). When the
Auto-Response (AR) input is forced to the logic "0" state,
the transmitter/encoder responds with clean status (all zeros on data bits).

Data is parallel loaded from the system data bus to the
transmitter/encoder's input holding register. This data is in
turn loaded by the transmitter/encoder to its output shift
register if this register was empty at the time of the load.
During this load, message formatting and parity are generated. The formatted message is then shifted out at the bit rate
frequency to the TTL to Biphase block which generates the
proper data bit formatting. The data outputs, DATA, DATA,
and DATA DELAY provide for flexible interface to the transmission medium with little or no external components.

Operation of the transmitter/encoder is automatic. After the
first data byte is loaded, the Transmitter Active output is set
and the transmitter/encoder immediately formats the input
data and serially shifts it out its data outputs. If the message
is a mutli-byte message, the internal format logic will modify
the message data format for multibyte as long as the next
byte is loaded to the input holding format logic will modify
the message data format for multibyte as long as the next
byte is loaded to the input holding register before the last
data bit of the previous data byte is transferred out of the
internal output shift register. After all data is shifted out of
the transmitter/encoder the Transmitter Active output will
return to the inactive state.

The control Logic block interfaces to all blocks to insure
proper chip operation and sequencing. It controls the type
of parity generation through the Even/Odd Parity input. An
additional feature provided by the transmitter/encoder is

2-24

Detailed Pin/Functional Description
CRYSTAL INPUTS X1 AND X2

TRANSMITTER ACTIVE

The oscillator is controlled by an external, parallel resonant
crystal connected between the X1 and X2 pins. Normally, a
fundamental mode crystal is used to determine the operating frequency of the oscillator; however, over-tone mode
crystals may be used.

This output will be in the logic "1" state while the transmitter/encoder is about to transmit or is in the process of transmitting data. Otherwise, it will assume the logic "0" state
indicating no data presently in either the input holding or
output shift registers.

CRYSTAL SPECIFICATIONS (PARALLEL RESONANT)

REGISTER LOAD

Type

The Register Load input is used to load data from the Data
Inputs to the input holding register. The loading function is
level sensitive, the data present during the logic "0" state of
this input is loaded, and the input data must be valid before
the logic "0" to logic "1" transition. It is after this transition
that the transmitter/encoder begins formatting of data for
serial transmission.

<20 MHz AT-cut
or> 20 MHz BT-cut

Tolerance

0.005% at 25°C

Stability

0.01 % from O°C to

Resonance

+ 70"C

Fundamental (Parallel)

Maximum Series Resistance

Dependent on Frequency
(For 20 MHz, 500)

Load Capacitance

AUTO RESPONSE (TT/ AR)

15 pF

This input provides for automatic clear data transmission (all
bits in logic "O") without the need of loading all zero's.
When a logic "0" is forced on this input the transmitter/encoder immediately responds with transmission of "clean
status". When this input is in the logic "1" state the transmitter/encoder transmits data entered on the Data Inputs.

Connection Diagram
R

C

TO PIN 22 ~L...- VCC
PIN (141
r-

.L .

c:J CRYSTAL

TO PIN Xl
PIN (131

EVEN/ODD PARITY
This input sets the internal logic of the DP8342/NS32442
transmitter/encoder to generate either even or odd parity
for the data byte in the bit 10 position. When this pin is in the
logic "0" state odd parity is generated. In the logic "1" state
even parity is generated. This feature is useful when the
control unit is performing a loop back check and at the
same time the controller wishes to verify proper data transmission with its receiver/decoder.

___I..... (FIG. 181
..
_

TLlF/5236-3

Freq

R

C

10 MHz-20 MHz 5000 30pF
>20 MHz

1200 15 pF

SERIAL OUTPUTS-DATA, DATA, AND DATA DELAY

If the DP8342/NS32442 transmitter is clocked by a system
clock (crystal oscillator not used), pin 13 (X1 input) should
be clock directly using a Schottky series (74S) circuit. Pin 14
(X2 input) may be left open. The clocking frequency must be
set at eight times the data bit rate. Maximum input frequency is 28 MHz.

These three output pins provide for convenient application
of data to the Bi-Phase transmission line. The Data outputs
are a direct bit representation of the Biphase data while the
Data Delay output provides the necessary increment to
clearly define the four (4) DC levels of the pulse. The DATA
and DATA outputs add flexibility to the DP8342INS32442
transmitter/encoder for use in high speed differential line
driving applications. The typical DATA to DATA skew is
2 ns.

CLOCK OUTPUT
The Clock Output is a buffered output derived directly from
the crystal oscillator block and clocks at the oscillator frequency. It is designed to directly drive the DP8343 receiver/
decoder Clock Input as well as other system components.

RESET
When a logic "0" is forced on this input, all outputs except
Clock Output are latched low.

REGISTERS FULL
This output is used as a flag by the external operating system. A logic "1" (active state) on this output indicates that
both the internal output shift register and the input holding
register contain active data. No additional data should be
loaded until this output returns to the logic "0" state (inactive state).

OUTPUT ENABLE
When a logic "0" is forced on this input the three serial data
outputs are in the high impedence state.
BYTE CLOCK
This pin registers a pulse at the end of each byte transmission. The number of pulses registered corresponds to the
number of bytes transmitted.

2-25

•

..,.

~ r---------------------------------------------------------------------------~

~

C")

(/)

Z

Message Format
Single Byte Transmission

i
Q

t

t

TRANSMISSION
START

TRANSMISSION
TERMINATION

Multl·Byte Transmission
SYNC BIT

BYTE 2

PARITY

BYTE X

TL/F/5236-4

FIGURE 3

Functional Timing Waveforms
II!Il:DII -U

1

12

u~~----------------------~u,~------------,L_

B::::: --ri..---------------------l1~

11~

w

--:-!II

I I I I I

DATA

~

DATA DElAY

~

J

II'I'I'I'I'I--:r; '~'~L"
!--STAIITINGSEQUENCE

B BIT + PARln

ENDIN.
SEQUENCE
TL/F/5236-5

FIGURE 4. Overall Timing Waveforms for Single Byte

~-u--------------------~I~I------------u~r----------------------~u,~----------~L_

am

~~

I

----+-!II I I I I I

I I

DATA DELAY

1111111

1 11 11 11 11

~

I I

II~~

DATA

~~

ICODE VlDLATIONrmCI D

t

ITARTlNGSEQUENCE-

,~i"Ji "lD

I

BIT2/PARm BIT//PARm
ENDING
~~ SEQUENCE"
8 BIT +PARln 8 BIT +PARITY
TL/F/5236-6

FIGURE 5. Overall Timing Waveforms for Multi-Byte

2·26

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Maximum Power Dissipation" at 25·C
Cavity Package
Dual-In-Line package

Supply Voltage, Vee
Input Voltage

*Derate cavity package 14.9 mW/oC above 25°C; derate dual in line package 20 mW I'C above 2S'C.

7V
5.5V

Output Voltage

5.25V

Storage Temperature Range

Operating Conditions

- 65·C to + 150·C

lead Temperature (Soldering, 10 sec.)

2237mW
2500mW

300"C

Supply Voltage, (Vee)

Min
4.75

Max
5.25

0

+70

Ambient Temperature, T A

Units
V
·C

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Conditions

=
=

Min

Typ

Max

Units

VIH

logic "1" Input Voltage (All Inputs Except X1 and X2)

Vee

VIL

logic "0" Input Voltage (All Inputs Except X1 and X2)

Vee

VeLAMP

Input Clamp Voltage (All Inputs Except X1 and X2)

liN

IIH

logic "1"
Input Current

IlL

logic "0"
Input Current

VOH1

logic "1" All Outputs Except ClK OUT,
DATA, DATA, and DATA DELAY

10H = -100 p.,A
Vee = 4.75V

VOH2

logic "1" for ClK OUT, DATA,
DATA, and DATA DELAY Outputs

Vee = 4.75V
10H = -10mA

VOL1

logic "0" All Outputs Except ClK OUT,
DATA, DATA, and DATA DELAY

Vee = 4.75V
10L = 5mA

0.35

0.5

V

VOL2

logic "0" forClKOUT, DATA
DATA, and DATA DELAY Outputs

Vee = 4.75V
10L = 20mA

0.4

0.6

V

1081

Output Short Circuit Current for All Except
ClK OUT, DATA, DATA, and DATA
DELAY Outputs

(Note 5)
VOUT = OV

-10

-30

-100

mA

1082

Output Short Circuit Current DATA,
DATA, and DATA DELAY Outputs

(Note 5)
VOUT = OV

-50

-140

-350

mA

1083

Output Short Circuit Current for ClK OUT

(Note 5)
VOUT = OV

-30

-90

-200

mA

lee

Power Supply Current

Vee = 5.25V

170

250

mA

Register load Input
All Others Except X1 and X2
Register load Input
All Inputs Except X1 and X2

=

Symbol

5V ± 5%, T A

=

V
0.8

5V

V

-0.8

-1.2

V

Vee = 5.25V
VIN = 5.25V

0.3

120

p.,A

0.1

40

p.,A

Vee = 5.25V
VIN = 0.5V

-15

-300

p.,A

-5

-100

p.,A

10H

Timing Characteristics Vee =

2.0

5V

-12 rnA

=

-1 mA

3.2

3.9

V

2.5

3.4

V

2.6

3.0

V

O·C to 70·C, Oscillator Frequency

Parameter

Conditions

tpd1

REG lOAD to Transmitter Active (TA)
Positive Edge

tpd2

=

28 MHz (Notes 2 and 3)

Typ

Max

Units

load Circuit 1
Figure 6

60

90

ns

REG lOAD to Register Full;
Positive Edge

load Circuit 1
Figure 6

45

75

ns

tpd3

TA to Register Full;
Negative Edge

load Circuit 1
Figure 6

40

70

ns

tpd4

Positive Edge of REG lOAD to
Positive Edge of DATA

load Circuit 2
Figure 9

50

80

ns

lpd5

REG LOAD to DATA;
Positive Edge

load Circuit 2
Figure 9

280

380

ns

tpd6

REG lOAD to DATA DELAY;
Positive Edge

load Circuit 2
Figure 9

150

240

ns

2-27

Min

Timing Characteristics
Vee = 5V
Symbol

±5%, TA =

(Continued)

O·C to 70·C, Oscillator Frequency = 28 MHz (Notes 2 and 3)
Typ

Max

Units

tpd?

Positive Edge of DATA to Negative Edge
of DATA DELAY

Parameter

load Circuit 2
Figure 9

Conditions

Min

70

85

ns

tpd8

Positive Edge of DATA DELAY to Negative
Edge of DATA

load Circuit 2
Figure 9

80

95

ns

tpd9,
todl0

Skew between DATA and DATA

load Circuit 2
Figure 9

2

6

ns

tpdll

Negative Edge of Auto Response (AR)
to Positive Edge of T A

load Circuit 1
Figure 10

70

100

ns

tpd12

Maximum Time Delay to load Second Byte
after Positive Edge of REG FUll

load Circuit 1
Figure 8, (Note 7)

4 X T - 50

ns

tpd13

Xl to ClK OUT; Positive Edge

load Circuit 2
Figure 11

21

30

ns

tpd14

Xl to ClK OUT; Negative Edge

load Circuit 2
Figure 11

23

33

ns

tpd15

Negative Edge of AR to Positive Edge of
REG FUll

load Circuit 1
Figure 10

45

75

ns

tpd16

Skew between TA and REG FUll during
Auto Response

load Circuit 1
Figure 10

50

80

ns

tpdl?

REG lOAD to REG FUll; Positive Edge
for Second Byte

load Circuit 1
Figure 7

45

75

ns

tpd18

REG FUll to BYTE ClK; Negative Edge

load Circuit 1
Figure 7

60

90

ns

tpd19

REG FUll to BYTE ClK; Positive Edge

load Circuit 1
Figure 7

145

180

ns

tZH

Output Enable to DATA, DATA, or DATA
DELAY outputs: HiZ to High

Cl = 50 pF
Figures 16, 17

25

45

ns

tZL

Output Enable to DATA, DATA, or DATA
DELAY Outputs; HiZ to High

Cl = 50 pF
Figures 16, 17

15

30

ns

tHZ

Output Enable to DATA, DATA, or DATA
DELAY Outputs; High to HiZ

Cl = 15 pF
Figures 16, 17

65

100

ns

tLZ

Output Enable to DATA, DATA, or DATA
DELAY Outputs; low to HiZ

Cl = 15 pF
Figures 16, 17

45

70

ns

towl

REG lOAD Pulse Width

Figure 12

tpw2

First REG FUll Pulse Width (Note 6)

load Circuit 1
Figure 7, (Note 7)

tpw3

REG FUll Pulse Width Prior to Ending
Sequence (Note 6)

load Circuit 1
Figure 7

tow4

Pulse Width for Auto Response

Figure 10

tpu5

Pulse Width for BYTE ClK

load Circuit 1
Figure 7, (Note 7)

ts

Data Setup Time prior to REG lOAD
Positive Edge; Hold Time = 0 ns

Figure 12

t,l

Rise Time for DATA, DATA, and DATA
DELAY Output Waveform

tfl

40

ns
8xT+60

8 X T + 100

5XB

ns
ns

40

ns
8xT+30

8xT+80

ns

15

23

ns

load Circuit 2
Figure 13

7

13

ns

Fall Time for DATA, DATA, and DATA
DELAY Output Waveform

load Circuit 2
Figure 13

5

11

ns

t,2

Rise Time for TA and REG FUll

load Circuit 1
Figure 14

20

30

ns

tf2

Fall Time for TA and REG FUll

load Circuit 1
Figure 14

15

25

ns

2-28

C

."

Timing Characteristics (Continued)

co
W

Vee = 5V ± 5%, T A = O'C to 70'C, Oscillator Frequency = 28 MHz (Notes 2 and 3)
Symbol

Parameter

Conditions

Typ

Min

Data Rate Frequency
(Clock Input must be 8 x this Frequency)

DC
(Note 4)

Input Capacitance-Any Input

5

Max

Units

3.5

Mbits/s

15

pF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety 01 the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified, minimax limits apply across the aoc to
values are for T A ~ 25'C and Vee ~ 5.0V.

+ 70"e temperature

range and the 4.75V to 5.25V power supply range. All typical

Note 3: All currents into device pins are shown as positive; aU currents out of device pins are shown as negative; all voltages are referenced to ground, unless
otherwise specified. All values shown as max or min are so classified on absolute basis.
Note 4: Input capacitance is guaranteed by periodic testing. fTEST = 10 kHz at 300 mY, TA = 25°C.
Note 5: Only one output should be shorted at a time.
Note 6: T

~

I/(Oscillator Frequency). Unit for T should be in ns. B

~

ST.

Note 7: Oscillator Frequency Dependent.

-:\'---4 -r-t-Pdt---::---:'~-_-;'
114=;

Timing Waveforms (Continued)

_______-:-_-J.

VOL

~tPd2 *tPd3~
--=

--l

REG FULL

VOH
5011

-~-

BYTE CLOCK - - - - - - - - - - - - - - - '

TLlF/5236-7

FIGURE 6. Single Byte Transfer

Y
" l__~I'
_

REG FULL

~I

t . · -=c:,

REG LOAD

_ _ _ _ _J

-

n
_

tpd2

-\ _
1

'-_ _ _ _.1

:~V

12

/I

-;;- ..

tpd17

" \ 5011
VDL
tPd3-11=

rl~

_tpw2

tpdl8-

--

BYTECLK _ _ _ _ _ _ _ _ _ _ _ _ _ _. . , / ' { '

--

-SOIlVOH

_

--j

tpw3

VOL

l~~l-

~ ~::

-tpw5
TL/F/5236-B

FIGURE 7. Two-Byte Transfer

~I\MI

REG FULL

~!1==' 1t~
~

3V

VOH
VOL

WINDOW

TO LOAD MULTI·BYTE DATA ......

15"'xl

FIGURE 8. Maximum Window to Load Multi-Byte Data
2-29

TL/F/5236-9

""

N
......

Z

rn
w
N

""""
N

Functional Timing Waveforms

(Continued)
3V

4~,--% ~\

1.5V
DV

tp_d4

VoH

DATA

VOL

'------'

I.

tpd5-·----lr----.

VoL

r~'i

DATA DELAY

VDH

VOL
TL/F/5236-10

FIGURE 9. Three Serial Outputs

r-----------~~-------------------~
- - - - - - - - - -_ _ _ _ _ _ _ _ 1.5V

AR

-":'_.Jl

'~Oll VOH

tPdl1

TA _ _

__-_I

Il+-t

-oJ

REG FUll

VOL

Pd15

---3Y

",~~

~~.
-YOH

elK OUT

_

50%

VOL

"

-

E-tPd16 VOH

Tl/F/5236-12

5011

FIGURE 11. Clock Pulse
VOL

TLlF/5236-11

FIGURE 10. Auto-Response

10%

Tl/F/5236-14
Tl/F/5236-13

FIGURE 13. Output Waveform for DATA, DATA,
DATA DELAY (Load Circuit 2)

FIGURE 12. REG LOAD

Yee

Vee

10%

TLlF/5236-15

FIGURE 14. Rise and Fall Time Measurement
for TA and REG FULL

TLlF/5236-16

Load Circuit 1
Load Circuit 2
FIGURE 15. Test Load Circuits

2-30

Timing Waveforms

(Continued)
YCC

UK

TL/F/5236-17

FIGURE 16. Load Circuit for Output TRI-STATE Test

}

OUTPUT ENABLE

VOH
DATA OUTPUTS

-tHZ
VOH-O.5V

VOL

YOL+O.5Y
-tLl

.....1

f'
HIGH Z

-I

YOH
VOL
-tZL
~YOH-O.5Y

tr- VOL +O.5Y

VOH
VOL

-tZH
TL/F/5236-18

FIGURE 17. TRI-STATE Test

Typical Applications
t-oVCC

RESET

IAUTO RESPONS~

OATA
OPTIONAL
INTERFACE
LOGIC
FIG. 19

DP8342
TRANSMITTERI
ENCODER

REG LOAD
REG FULL

COAX LINE (FIG. 19)

BYTE CLOCK

TWISTED PAIR LINES

.,::>

.
w

~
a:
w

l-

....,.'"
e.>

DATA BUS 01·08

l!!!

e.>

IE

.,I!!
~

FIBER-OPTIC
MAGNETIC
INFRARED
RF
ULTRASONIC
AUDIO
CURRENT CARRYING

TRANSMITTER
ACTIVE

RECEIVER
DISABLE

DATA
AVAILABLE
ERROR

•

+IN

OUTPUT CONTROL

I
..
I OUTPUT ENABLE
I
I REG READ
I
I RECEIVER ACTIVE

•

DP8343
RECEIVER I
DECODER

-IN

OPTIONAL
INTERFACE
LOGIC

I

DC TO 3.5MHz

I

..

TL/F/5236-19

FIGURE 18

2·31

Typical Applications (Continued)

Rl
150

DATA
DELAY
R2

33

QJ
90Q COAX
(RG62A/UI

3

R6
120

R5
150

TRANSMITTER
ACTIVE

+

I2
I

5 •

INJ
CONNECT TO
DP8343
RECEIVER

L __ *s_..J

-IN

6
GND
Note 1: Resistance values are in

n,

±5%,

TLlF/5236-2D

%W.

Note 2: Tl is a 1:1:1 pulse transformer, L ~ 500 I'H for 18 MHz to 28 MHz system clock. Pulse Engineering Part No. 5762; Technitrol Part No. lILHA, Valor
Electronics Part No. CT1501, or equivalent transformer.
Note 3: Crystal manufacturer Midland Ross Corp. NEL Unit Part No. NE-18A at 28 MHz.

FIGURE 19. Interface Logic for a Coax Transmission Line

.------.(NOTE)
DATA

1.

T1

90QCOAX

DP8342
TRANSMInERI
ENCODER

TA
OE

+

5.
INJ
CONNECT TO
0P8343
RECEIVER
-IN

(tf
4

6
TLlF/5236-21

Nole: Data rates up to 3.5 Mbits/s at 5000' still apply.

FIGURE 20. Direct Interface for a Coax Transmission Line (Non-IBM Voltage Levels)

2-32

~National

~ Semiconductor
DP8343/NS32443
High-Speed 8-Bit Serial ReceiverIDecoder
General Description

Features

The DP8343/NS32443 provides complete decoding of data
for high speed serial data communications. In specific, the
DP8343/NS32443 receiver recognizes biphase serial data
sent from its complementary chip, the DP8342 transmitter,
and converts it into 8 bits of parallel data. These devices are
easily adapted to generalized high speed serial data transmission systems that operate at bit rates up to 3.5 MHz.
The DP8343/NS32443 receiver and the DP8342 transmitter
are designed to provide maximum flexibility in system designs. The separation of transmitter and receiver functions
allows addition of more receivers at one end of the biphase
line without the necessity of adding unused transmitters.
This is advantageous in control units where the data is typically multiplexed over many lines and the number of receivers generally exceeds the number of transmitters. The separation of transmitter and receiver function provides an additional advantage in flexibility of data bus organization. The
data bus outputs of the receiver are TRI-STATEI!>, thus enabling the bus configuration to be organized as either a
common transmit/receive (bi-directional) bus or as separate
transmit and receive busses for higher speed.

• DP8343/NS32443 receives 8-bit data bytes
• Separate receiver and transmitter provide maximum
system design flexibility
• Even parity detection
• High sensitivity input on receiver easily interfaces to
coax line
• Standard TTL data input on receiver provides generalized transmission line interface and also provides
hysteresis
• Data holding register
• Multi-byte or single byte transfers
• TRI-STATE receiver date outputs provide flexibility for
common or separated transmit/receive data bus
operation
• Data transmission error detection on receiver provides
for both error detection and error type definition
• Bipolar technology provides TTL input/ output compatibility with excellent drive characteristics
• Single + 5V power supply operation

Connection Diagram
Dual-In-Llne Package
RECEIVER DISABLE-

~ -VCC

+AMPLIFIERINPUT- 2

23 ~DATACLDCK

-AMPLIFIER INPUT -

3

22 r--SERIAL DATA

DATA (TTL) -

4

DATA CONTROL -

5

21 r-- BIT8
20 r--BIT7
19 r--B1T6

CLOCK- 6
RECEIVER ACTIVE -

18 r-81T5

7

17 r--BIH

ERROR- 8
REGISTER READ -

16 -B1T3

9

15 -BIT2

DATA AVAILABLE- 10
OUTPUT CONTROL -

14 _BITl

11

13 -

GND- 12

OUTPUTENABLE
TUF/5237-1

FIGURE 1
Order Number DP8343/NS32443J
or DP8343/NS32443N
See NS Package Number J24A or N24A

2-33

C")

"Ot
"Ot

N

Block Diagram

en

CLOCK

"Ot

DATA
CONTROL

C")

z
......
C")
C")

RECEIVER
ACTIVE

co

Q.

SERIAL DATA

C

SERIAL DATA CLOCK

AMPLIFIER
INPUT

DATA
AVAILABLE
RECEIVER
DISABLE

ERROR OUTPUT

PARALLEL OUTPUT DATA
TLlF/5237-2

FIGURE 2. DP8343INS32443 Biphase Receiver

Functional Description
been read or the start of another data byte is received, in
which case a Data Overflow Error will be detected, terminat·
ing the message. Data is read from the holding register
through the TRI·STATE Output Buffers. The Output Enable
input is the TRI·STATE control for these outputs and the
Register Read input signals the receiver that the read has
been completed.
When the receiver detects an ending sequence the Receiv·
er Active output will be reset to a logiC "0" indicating the
message has been terminated. A message will also termi·
nate when an error is detected. The Receiver Active output
used in conjunction with the Error output allows quick reo
sponse to the transmitting unit when an error free message
has been received.
The Error Detection and Identification block insures that val·
id data reaches the outputs of the receiver. Detection of an
error sets the Error output to a logic "1" and resets the
Receiver Active output to a logic "0" terminating the meso
sage. The error type may be read from the data bus outputs
by setting the Output Control input to logic "0" and enabling
the TRI·STATE outputs. The data bit outputs have assigned
error definitions (see error code definition table). The Error
output will return to a logic "0" when the next starting se·
quence is received, or when the error is read (Output Con·
trol to logic "0" and a Register Read performed).

Figure 2 is a block diagram of the DP8343/NS32443 receiv·
er. This chip is essentially a serial in/parallel out shift regis·
ter. However, the serial input data must conform to a very
specific format (see Figures 3-6). The message will not be
recognized unless the format of the starting sequence is
correct. Deviations from the format in the data, sync bit,
parity or ending sequence will cause an error to be detect·
ed, terminating the message.

Data enters the receiver through the differential input ampli·
fier or the TTL Data input. The differential amplifier is a high
sensitivity input which may be used by connecting it directly
to a transformer coupled coax line, or other transmission
medium. The TIL Data input provides 400 mV of hysteresis
and recognizes TIL logiC levels. The data then enters the
demodulation block.
The data demodulation block samples the data at eight (8)
times the data rate and provides signals for detecting the
starting sequence, ending sequence, and errors. Detection
of the starting sequence sets the .Receiver Active output
high and enables the input shift register.
As the eight bits of data are shifted into the shift register, the
receiver will verify that even parity is maintained on the data
bits and the sync bit. Serial Data and Serial Data Clock, the
inputs to the shift register, are provided for use with external
error detecting schemes. After one complete data byte is
received, the contents of the input shift register is parallel
loaded to the holding register, assuming the holding register
is empty, and the Data Available output is set. If the holding
register is full, this load will be delayed until that register has

The Receiver Disable input is used to disable both the am·
plifier and TTL Data receiver inputs. It will typically be con·
nected directly to the Transmitter Active output of the
DP8342 transmitter circuit.

2·34

Detailed Functional Pin Description
RECEIVER DISABLE

ERROR
The Error output transitions to a logic "1" when an error is
detected. Detection of an error causes the Receiver Active
and the Data Available outputs to transition to a logic "0".
The Error output returns to a logic "0" after the error register has been read or when the next starting sequence is
detected.

This input is used to disable the receiver's data inputs. The
Receiver Disable input will typically be connected to the
Transmitter Active output of the DP8342. However, at the
system controller it may be necessary for both the transmitter and receiver to be active at the same time. This variation
can be accomplished with the addition of minimal external
logic.
Truth Table
Receiver Disable

REGISTER READ
The Register Read input when driven to the logic "0" state
signals the receiver that data in the holding register is being
read by the external operating system. The data present in
the holding register will continue to remain valid until the
Register Read input returns to the logic "1" condition. At
this time, if an additional byte is present in the input shift
register it will be transferred to the holding register, otherwise the data will remain valid in the holding register. The
Data Available output will be in the logic "0" state for a
short interval while a new byte is transferred to the holding
register after a register read.

Data Inputs

Logic "0"

Active

Logic "1"

Disabled

AMPLIFIER INPUTS

The receiver has a differential input amplifier which may be
directly connected to the transformer coupled coax line. The
amplifier may also be connected to a differential type TTL
line. The amplifier has 20 mV of hysteresis.
DATA INPUT

DATA AVAILABLE
This output indicates the existence of a data byte within the
output holding register. It may also indicate the presence of
a data byte in both the holding register and the input shift
register. This output will transition to the logic "1" state as
soon as data is available and return to the logic "0" state
after each data byte has been read. However, even after the
last data byte has been read and the Data Available output
has assumed the logic "0" state, the last data byte read
from the holding register will remain until new data has been
received.

This input can be used either as an alternate data input or
as a power-up check input. If the system designer prefers to
use his own amplifier, instead of the one provided on the
receiver, then this TTL input may be used. Using this pin as
an alternate data input allows self-test of the peripheral system without disturbing the transmission line.
DATA CONTROL

This input is the control pin that selects which of the inputs
are used for data entry to the receiver.
Truth Table

OUTPUT CONTROL
Data Control

Data Input To

Logic "0"

Data Input

Logic "1"

Amplifier Inputs

The Output Control input determines the type of information
appearing at the data outputs. In the logiC "1" state data will
appear, in the logiC "0" state error codes are present.
Truth Table

Note: This input is also used for testing. When the input voltage is raised to
7.5V the chip resets.

CLOCK INPUT
This input is the internal clock of the receiver. It must be set
at eight (8) times the line data bit rate. The crystal-controlled
oscillator provided in the DP8342 transmitter also operates
at this frequency. The Clock Output of the transmitter is
designed to directly drive the receiver's Clock Input. In addition, the receiver is designed to operate correctly to a data
bit rate of 3.5 MHz.

Output Control

Data Outputs

LogiC "0"

Error Codes

Logic "1"

Data

OUTPUT ENABLE

The Output Enable input controls the state of the
TRI-STATE Data outputs.
Truth Table

RECEIVER ACTIVE

The purpose of this output is to inform the external system
when the DP8343/NS32443 is in the process of receiving a
message. This output will transition to a logic "1" state after
a receipt of a valid starting sequence and transition to logiC
"0" when a valid ending sequence is received or an error is
detected. This output combined with the Error output will
inform the operating system of the end of an error free data
transmission.

Output Enable

TRI-STATE
Data Outputs

LogiC "0"

Disabled

Logic "1"

Active

DATA OUTPUTS

The DP8343/NS32443 has an 8-bit TRI-STATE data bus.
Seven bits are multiplexed with error bits. The error bits are
defined in the following table. The Output Control input is
the multiplexer control for the Data/Error bits.

2-35

r)

'II:!'

~

r)

r------------------------------------------------------------------------------------------,
Message Format

tJ)

2:

Single Byte Transmission

r)

'II:!'

TRANSMISSION
START SEQUENCE

r)

~

o

t

t

TRANSMISSION
TERMINATION

TRANSMISSION
START

Multi-Byte Transmission
SYNC BIT
BYTE 2

TL/F/5237-3

FIGURE 3

DATA

RECEIVER
ACTIVE _ _ _ _ _ _ _ _ _ _..1

-1'

DATA _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
AVAILABLE

REGISTER
READ

r---1'L____

--------------------....,U
TL/F/5237-4

FIGURE 4a. Single Byte (S-Bit) Message

DATA~~~~~
UNEQUIESCE

I

I

I

II

CODE r---1.IBYTE----2ndBYTE- ••• -LAST BYTE-lENDING
VIOLATION
SEQUENCE

I

RECEIVER
ACTIVE _ _ _ _ _ _ _ _ _--1

----InL___----Ir···

DATA _ _ _ _ _ _ _ _ _ _ _ _
AVAILABLE

REGISTER
READ

_

•

•

u

L

-----------------.U
TL/F/5237-5

FIGURE 4b. Multi-Byte Message

2-36

Error Code Definition
Data Bit
DP8343
Bit 1

Error Type
Data Overflow (Byte not removed from holding register when it and the input shift register are both full and new
data is received)

Bit 2

Parity Error (Odd parity detected)

Bit 3

Transmit Check conditions (existence of errors on any or all of the following data bits: Bit 2. Bit 4. and Bit 5)

Bit 4

An invalid ending sequence

Bit 5

Loss of mid-bit transition detected at other than normal ending sequence time

Bit 6

New starting sequence detected before data byte in holding register has been read

Bit 7

Receiver disabled during receiver active mode

SERIAL DATA
The Serial Data output is the serial data coming into the
input shift register.

DATA CLOCK
The Data Clock output is the clock to the input shift register.

Message Format (Continued)
DATA

LINE QUIESCE

I

I

I

CODE
VIOLATION \ - - - CORRECT DATA BYTE--

RECEIVER
ACTIVE _ _ _ _ _ _ _ _ _- - '

L

ERROR DETECTED

I

DATA
AVAILABLE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....

ERRoR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---'

REGISTER
READ

----------------------------:------,U

oUT~T---------------------------~--,

1.-_ _ _.1

CONTROL

TL/F/5237-6

FIGURE 5. Message with Error

,.

DATA

SERIAL - - - - - - - - - - - - ,
DATA

DATA

CLOCK _ _ _ _ _ _ _ _ _ _ _....
TLlF/5237-7

FIGURE 6. Data Clock and Serial Data

2-37

Absolute Maximum Ratings

(Note 1)
- 65°C to + 150°C

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Storage Temperature Range

Supply Voltage, (Vecl

7.0V

Operating Conditions

Input Voltage

5.5V

Output Voltage

Supply Voltage, (Vecl
Ambient Temperature, TA

5.25V

Electrical Characteristics
Symbol

Lead Temperature (Soldering, 10 sec.)

Min
4.75
0

300°C

Max
5.25
+70

Units
V
°C

Max

Units

(Notes 2, 3 and 5)

Parameter

Conditions

Min

Typ

V

2.0

VIH

Input High Level

VIL

Input Low Level

VIWVIL

Data Input Hysteresis (TTL, Pin 4)

VeLAMP

Input Clamp Voltage

IIH

Logic "1" Input Current

IlL

Logic "0" Input Current

VOH

Logic "1" Output Voltage

0.8

VOL

Logic "0" Output Voltage

los

Output Short Circuit Current

10Z

TRI·STATE Output Current

0.2

= -12 mA
Vee = 5.25V, VIN = 5.25V
Vee = 5.25V, VIN = 0.5V
10H = -100 /J-A
10H = -1 mA
10L = 5 mA
liN

Vee = 5V, VOUT
(Note 4)
Vee
Vee

AHYS

Amplifier Input Hysteresis

Icc

Power Supply Current

Vee

= OV

= 5.25V

V
V

-0.8

-1.2

V

2

40

/J-A

-20

-250

/J-A

3.2

3.9

2.5

3.2

V
V

0.35

0.5

V

-20

-100

mA

-40

1

+40

/J-A

-40

-5

+40

/J-A

5

20

30

mV

160

250

mA

-10

= 5.25V, Vo = 2.5V
= 5.25V, Vo = 0.5V

0.4

Timing Characteristics (Notes 2,6,7, and 8)
Min

Typ

Max

Units

TOI

Output Data to Data Available
Positive Edge

5

20

40

ns

T02

Register Read Positive Edge to
Data Available Negative Edge

10

25

45

ns

T03

Error Positive Edge to
Data Available Negative Edge

10

30

50

ns

T04

Error Positive Edge to
Receiver Active Negative Edge

5

20

40

ns

T05

Register Read Positive Edge to
Error Negative Edge

20

45

75

ns

T06

Delay from Output Control to
Error Bits from Data Bits

5

20

50

ns

T07

Delay from Output Control to
Data Bits from Error Bits

5

20

50

ns

T08

First Sync Bit Positive Edge to
Receiver Active Positive Edge

3.5 x T
+70

ns

T09

Receiver Active Positive Edge to
First Data Available Positive Edge

76 x T

ns

T010

Negative Edge of Ending Sequence to
Receiver Active Negative Edge

11.5 x T
+50

ns

T011

Data Control Set·up Multiplexer Time Prior
to Receiving Data through Selected Input

30

ns

T012

Serial Data Set·Up Prior to
Data Clock Positive Edge

3xT

ns

Symbol

Parameter

Conditions

40

2·38

I

o."

Timing Characteristics (Notes 2,6,7, and 8) (Continued)
Symbol

Parameter

Conditions

CO

....

to:)

Min

Typ

Max

Units

TpW1

Register Read (Data) Pulse Width

30

40

ns

TpW2

Register Read (Error) Pulse Width

40

30

ns

TpW3

Data Available Logic "0" State between
Data Bytes

25

45

ns

Ts

Output Control Set-Up Time Prior to
Register Read Negative Edge

0

-5

ns

TH

Output Control Hold Time after the
Register Read Positive Edge

0

-5

ns

TZE

Delay from Output Enable to Logic "1" or
Logic "0" from High Impedance State

Load Circuit 2

TEZ

Delay from Output Enable to High Impedance State from Logic "1" or Logic "0"

Load Circuit 2

FMAX

Data Bit Frequency (Clock Input must be
8 x the Data Bit Frequency)

to:)

.......
Z

tJ)
to:)

25

35

ns

25

35

ns

3.5

MBits/s

DC

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.

Note 2: Unless otherwise specified, min./max. limits apply across the

aoc to + 70 e temperature range and the 4.75V to 5.25V power supply range. All typical
0

values are for T A = 25°C and Vee = 5.0V.

Note 3: All currents into device pins are shown as positive; all currents out of device pins are shown as negative; all voltages are referenced to ground, unless
otherwise specified. All values shown as max. or min. are so classified on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: Input characteristics do not apply to amplifier inputs (pins 2 & 3).
Note 6: Unless otherwise specified, all AC measurements are referenced to the 1.5V level of the input to the 1.5V level of the output and load circuit 1 is used.
Note 7: AC tests are done with input pulses supplied by generators having the following characteristics: ZOUT = 5[1, Tr ::;; 5 ns, and Tf ::;; 5 ns.
Note 8: T = 1/(clock input frequency), units for "T" should be ns.

Test Load Circuits
Vee

vee
RL=2k

~

I ....

J...oil
I~ ."

ll~ ~,

I"~
':'

R1 =1k

,.

"';f-

-f-

R2 = 2k ...;
."

-f-

1'' ' '*'

~~
~

TL/F/5237-8

Load Circuit 1

~~

-=-

Load Circuit 2
FIGURE 7

2-39

TL/F/5237-9

........
N

to:)

(W)
~
~

N

(W)

r---------------------------------------------------------------------------------,
Timing Waveforms

en

z
.......
(W)

OUTPUT
ENABLE

~
(W)

fc

002-0011
OUTPUTS
(OUTPUT CONTROL = HI)

--"

\I'

l.SV

-'I

--l

(Z+ O.S)V

1-

TZE

----- ' - - - I - - - T E z - -

.:::r--Y'-_______________-=\I->-~(::,:,VO;;;H~-:::"O.::S):,:"V-....I-T-

(Z O.S)V ~'I\

(VOL +O.S)V

I-Tal

~

t

1-'---TD-2--------

1-IPW1~1

REGISTER

V,..------------

---------------.....,'X

~M

~

TL/F/5237-10

FIGURE 8. Data Sequence Timing

\

DATA
AVAILABLE

IRECEIVER
ACTIVE

T0 3 - 1

'\

-T04-1

{

t

ERROR

I-Tos-I

\

REGISTER
READ

1-

Ts-I

'\

OUTPUT
CONTROL

)(
TPw2-I-TH-1

!,

06-1

I.o- T
BIT1-BIT7

I.o-TD7-1

X

DATA BITS

X

ERROR BITS

DATA BITS
TLlF/5237-11

FIGURE 9. Error Sequence Timing

111111

I

VIJ~~~oN

11

I

DATA

10

IMCvlMcvl

~---(2~~--SlJ

--I 1--

T08

I.Tol~1

------'1._.____

RECEIVER _ _ _ _ _ _ _ _ _ _ _ _--I.----r~1
ACTIVE
!
-

I- 09-1
T

r----------

DATA _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----?I~
AVAILABLE

TLlF/5237-12

FIGURE 10. Message Timing

2-40

Timing Waveforms

(Continued)

..JX. ._______..JX~____

SERIAL DATA _ _ _ _

I. . . T012--1

_______~l~~\~___

DATA CLOCK

•

_

TL/F/5237-13

FIGURE 11. Data Clock and Serial Data Timing

..... BT±(T-25n.)--

T:.;

CLOCK

4T±(T-25n.)-

INPU~ FREQUENCY

-----;~--_t----~----~----r----~N-

TL/F/5237-14

FIGURE 12. Data Waveform Constraints: Amplifier Inputs

-BT±(T-25ns)T

4T±(T-25ns)-

Note:

=

CLOCK

INPU~ FREQUENCY

IT, - +'}I-,;-1-0-ns-----..J

TLlF/5237-15

FIGURE 13. Data Waveform Constraints: Data Input (TTL)

~C---~--~-----'-lk

VIN+

VIN-

-----+-----1

TL/F/5237-16

FIGURE 14. Equivalent Circuit for DP8343INS32443 Input Amplifier

2·41

M
-=:I'

~

M

r--------------------------------------------------------------------------Typical Applications

en
z

28 MHz MAX .

......

M
-=:I'
M

co
D-

C

IAUTO RESPONSr:.,
I
iiEGi]AO

REG FULL

DPB342
TRANSMITTER/
ENCODER

DATA
AA
DELAY

DPTIONAL
INTERFACE
LOGIC
(FIG. 16)

om

COAX LINE (FIG. 16)

BYTE CLOCK

TWISTED PAIR LINES

.'"
::>

.

...If
w

...
ili
...
ffi

DATA BUS D1·DB

!!

..

...9
...

I OUTPUT CONTROL

•
I
•
I RECEIVER ACTIVE

I

INFRARED
RF
ULTRASONIC
AUDIO

ERROR

II OUTPUT ENABLE•
I

MAGNETIC

RECEIVER
DISABLE

DATA
AVAILABLE

>-

FIBER·OPTIC

TRANSMITTER
ACTIVE

CURRENT CARRYING

+IN
OP8343
RECEIVER/
DECODER

OPTIONAL
INTERFACE
LOGIC

-IN

DC TO 3.5 MHz

REG READ

I
I

I

TLlF/5237-17

Note 1: Crystal manufacturer Midland Ross Corp., NEL Unit Part No. NE-18A

@

28 MHz

FIGURE 15

2·42

Typical Applications (Continued)
Rl
150
DATA
DELAY

gOg COAX
(RG62AfU)

(ft
3

R5

150

I2
I

J

R6
120

5.

+IN

CONNECT TO
DP8341
RECEIVER

L_-*iI--1

-IN

6
GNO
TL/F/5237-18

Note 1: Resistance values afe in

n,

±5%, YI.W.

Note 2: Tl is a 1:1:1 pulse transformer, LMIN = 500 f'H for 18 MHz system clock.
Pulse Engineering Pari No. 5762,
Valor Electronics Pari No. CT1501
Technitrol Pari No. 11 LHA or equivalentlransformers.

FIGURE 16. Interface Logic for a Coax Transmission Line

TLlF/5237-19

TL/Ff5237-20

'To maintain loss at 95% of ideal signal, select

Note 1: Less Inductance will cause greater amplitude

transformer inductance such that:

attenuation.

4MIN) =

10,000
fOLK

Note 2: Greater inductance may decrease signal rise
time slightly and incease ringing, but these effects are
generally negligible.

fOLK = System Clock
Frequency
(e.g., 18.87 MHz)

Example:

L=~18.87 X 106

L(MIN) = 530 H
f'

FIGURE 17. Transformer Selection

2-43

The BIPLAN™
DP8342/DP8343 Biphase
Local Area Network

National Semiconductor
Application Note 496
Kaushik (Chris) Popat
AI Brilliott

THE BIPLAN

The LAN system described here is a star network (see Figure 1) supporting up to 256 nodes with either fiber-optic
links or coax links or both (simultaneously) at distances up
to 2 miles and a data rate of 3.5 megabits/sec.

The BIPLAN is a star local area network designed to demonstrate the capabilities of National Semiconductor's
DP8342/43 transmitter/encoder and receiver/decoder
chips. These chips are eight bit versions of the DP8340/41
ten bit parts designed to conform to the IBM 3270 protocol.
These eight bit devices are ideal for general purpose high
speed serial communication. They enable communication at
any data rate up to 3.5 megabits/sec over a variety of transmission media with a minimum of external components and
easily interface to an eight bit data bus. These devices automatically provide line conditioning, manchester encoding
and error checking minimizing transmission errors while enhancing noise immunity and reliability.

To demonstrate this LAN system, a PC board has been developed which can be configured as a master or a slave (the
slave hardware is a subset of the master hardware). As a
master, the board will support 8 fiber-optic slaves and four
coax slaves and can be expanded to support up to 128
fiber-optic slaves and 128 coax slaves simultaneously (see
Figure 2). The network interface will communicate with its
host either serially (RS-232) or through an eight bit parallel
port (multibus). Some features of the network system include:
- 3.5 Megabits/ sec data rate
-

Distance between slaves-2 miles for coax
Simultaneous support for 128 fiber-optic slaves and 128
coax slaves
Protocol insures data integrity-All transfers acknowledged
1-254 byte transfers, up to four 254 byte pages per data
packet
1 kbyte transmit and receive buffers.

-

TL/F/9339-1

FIGURE 1

MASTER
CONTROL

COAX CABLE
1 MILE 3.5 MBITS/ S

COAX~----------------~~
MUX~

__________________

~

TRANSMIT
RECEIVE
FIBER DUPLEX FIBER OPTIC CABLE
OPTIC r.....;;;.;...~;.....;.....;.;.;...=;.;...-..
MUX~----------------~

~----... 124 COAX SLAVES
EXPANSION ~==~ ADD EXTERNAL DECODE, MUX AND DRIVERS
120 FIBER OPTIC SLAVES

L __...t------'

TL/F/9339-2

FIGURE 2. Master/Slave Network Configuration

2-44

.--------------------------------------------------------------------,~

z

NETWORK PROTOCOL
The central node controls access to the network and is therefore termed "master" and satellite nodes are "slaves" since they
provide no network control. The master polls each slave sequentially to offer access to the network. Since the master polls one
slave at a time and no slave may transmit unless polled, there is no possibililty of contention. If a slave is not ready to transmit
data, it responds to a poll with an "auto-response" and the master polls the next slave (see Figure 3). Both the poll and the
auto-response (AR) are a single byte transmission with all zero data bits (message types will be discussed in detail later). A
disabled or disconnected slave will cause the master to time out and poll the next slave .

POLLING

• MASTER OR SLAVE MAY HAVE A HOST WHICH
IS A TERMINAL, CPU, ETC.

TL/F/9339-3

FIGURE 3
If a slave is ready to transmit, it responds to a poll with a "request to transmit" indicating the number of pages to be transmitted
and a destination address. The master sends this "request to transmit" to the destination slave. If the destination slave is not
ready to receive data, it sends a "no-permission to transmit" and the master sends it to the source slave deferring data transfer
until the destination is ready to receive it (see Figure 4). This pre-interrogation prevents wasted data transfers thus improving
system throughput. It also allows each node to prepare its DMA circuitry to transfer a block of data.
(NO ERRORS)

REQUEST TO TRANSMIT
(SOURCE READY DESTINATION NOT)
TLlF/9339-4

FIGURE 4

2-45

i

U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

~

Z:
c(

In the case where the destination slave is ready to receive data, it sends a "permission to transmit" and prepares to receive

data. The master, on receiving this "permission to transmit" sends it to the source slave and prepares for a transparent transfer
of data from source slave to destination slave. The source transmits data and if it reaches the destination without error, the
destination slave sends an acknowledge byte. The data/acknowledge cycle continues until the last page of data is transferred.
At this point the destination slave sends a special acknowledge called an EaT ("end of transmission") terminating the communication sequence and releasing the master to poll the next slave (see Figure 5).
(NO ERRORS)
START AT 3
3) CAN YOU RECEIVE
(4 &: 5) PERMISSION TO XMIT
(6&:7) 1-254 BYTES SENT (1 PAGE)
TO DEST SLAVE
MASTER TRANSPARENT
8) RECEIVED DATA
PACKET (ACK)
9) ACK DATA RECEIVED
- ANY MORE PAGES?

---.........

DATA TRANSMISSION
(SOURCE AND DESTINATION READY)
TL/F/9339-5

FIGURE 5

ERROR HANDLING
Recovery from transmission error is handled in the following way. If any node (either master or slave) detects an error while
receiving any message from the network (data or control), it sends an error message to the sending node. On receiving an error
message, a node retransmits its last message (examples are shown in Figure 6). This may continue to a limit of five retransmission attempts per communication sequence. An error message is simply the error flag register of the DP8343 receiver indicating
the type of error that occurred. The receiver provides the following types of internal error checking:
-

Data overflow

-

Parity error

-

Transmit check

-

Invalid ending sequence

-

Loss of mid-bit transition

-

New starting sequence before read

-

Receiver disabled while active

2-46

l>
Error on Poll

An exception to this rule is during a transparent data transfer (from source slave through transparent master to destination slave), if the master detects an error, it will not send
an error message to the source slave. Instead, the master
forces a parity error on the next data byte causing the destination to detect a parity error in the data. The destination
slave sends an error message to the master and the master
then sends the error message to the source slave which reattempts the data transfer (see Figure 7). This method of
forcing a parity error at the master informs the destination
slave of the error condition immediately without having to
compare byte counts and enables quicker recovery.
The complete network protocol is summarized by the flow
chart in Figure 8.

• SLAVE DETECTS ERROR

SOURCE
TL/F /9339-6

®

START AT
SOURCE SLAVE RECEIVES
PERMISSION TO TRANSMIT

Error on Auto Response

MASTER TRANSPARENT
DURING DATA TRANSFER

• t.tASTER DETECTS ERROR
TLIF/9339-7

• MASTER DETECTS ERROR
•• DATA WITH FORCED PARITY ERROR

Error on Data Transfer

TL/F/9339-9

FIGURE 7. Error on Data Transfer

®

START AT
SOURCE SLAVE RECEIVES
PERMISSION TO TRANSMIT

SOURCE

MASTER TRANSPARENT
DURING DATA TRANSFER

• DESTINATION SLAVE DETECTS ERROR

DESTINATION

DESTINATION
TL/F/9339-B

FIGURE 6

2-47

z
I

""'
en
CD

~r-----------------------------------------------------------~

'It

Z

THE BIPLAN

c(

~_ _ _ _
P_ROTOCOL

FLOW CHART

(SLAVE SENDS
AR AGAIN)
TYPICAL SEQUENCES FOR
HANDLING ERRORS

YES

MASTER SENDS
PTT TO SOURCE
MASTER ESTABLISHES
TRANSPARENT LINK

AR - AUTO RESPONSE
RTT - REQUEST TO TRANSMIT
PTT - PERMISSION TO TRANSMIT
ACKMSG - ACKNOWLEDGE MESSAGE
ERRMSG - ERROR MESSAGE

j+-.:.(N_EW_P_AG_E.,;O.,;F.,;D;;,;A,;,;,TA;:,.)- - - - - - - - 1 MASTER ESTABLISHES
TRANSPARENT LINK
(SAME PAGE OF DATA)
(LIMIT 3 ATTEMPTS)
MASTER SENDS
ERRMSG TO SOURCE

NO

TL/F/9339-10

FIGURE 8. BIPLAN15B

2·48

MESSAGE TYPES

There are two major types of messages on the network: control messages and data messages. Control messages are one or
two bytes in length and include the following types: poll, auto-response, request to transmit, permission to transmit, acknowledge and error message (see Figure 9). Data messages are 3 to 256 bytes in length and include 1 to 254 bytes of data. Once a
node is granted access to the network, it is allowed to transmit up to 4 such data messages (or pages) so that any number of
data bytes from 1 to 1016 bytes (4 pages) can be transferred per access. All messages, data as well as control, begin with a
status byte as defined in Figure 9.
Data communication rates including overhead for the protocol are shown in Figure 10. Note that the effective data rate is
optimum for large data packets as the overhead becomes a less significant portion of the total time for the data transfer.
Data Communication Rates Source Slave to Destination Slave
Neglecting Cable Propagation Delays
(RG 621AU Coax = 1.2 nslft = 3.6 ns/meter)
First Page

Next Two to Four Pages

No. of Bytes

Time (I-'s)

No. of Bytes

Time (I-'s)

1

260

1

115

10

286

10

143

100

550

100

400

254

1000

254

Total Time for Transfer of: 1 Page (254 Bytes)-1000 I's
2 Pages (508 Byles)-1840 I's
3 Pages (762 Bytes)-2680 I's
4 Pages (1016 Bytes)-3520 I's or
2.3 Mbits/ sec

840
LATENCY
No Network Traffic-(40)(N)l's

(N) is the number of slaves on the
network

FIGURE 10

•
2-49

~

en

.-------------------------------------------------------------~

'0:1'

:Z

THE BIPLAN

-ll_-f--lH~~
IORC P1 - 21 <:~~"";';;;<1":""''''
(U45/11) T/ii 74LSOO

10-.....- - STRB (U23/39)
TL/F/9339-21

2-55

AN·496
5V

til

l V

GND

PP

~p-,

-=

18L
E/Pt;;-=

24 Vee

Al0t-r---,
_ 20
OEt;
MM2716 A9
23

r::--

U2

'"0,

'"

14

ND6"?,
W17

(J2-35)
LSTSl

16
7

1,
12

STRB

13

lS151

14

U6

.9
j

13
12 IS
- 17

~~Ok
5V RIa

(UI7/7)

i 18

(U23/5)
,

'19
. 1,0
5V

Q I

R17
10k

B

4
14

0 , 11

13

_-----:6,A2

0213

....-_ _ _--:5,A3

0 3 14

8
7

lS374

_---4:-JA4

0 4 15

17

U4

. -_ _-:3'A5

05 16

18

A6

Os 17
7
0

3

r-

5V

21 V

GND

PP

.!...
GND I

5~
C Y.-----,

11
5

n-::..

19

ee

or~

Al0
5V

A...
11 10 9
120
Vee

MM2716
11
ClK

"';7

8
12

15
17
16
18
19
lS374
9
a
U5
A
DA
Q 6
.....-+-_ _...,7 De
Qe 5
4 Dc
Qe 2
Do_
00
OC

,2

Ul
AO

7
6
5
4
3

Al
A2
A3
A'
A5

~

2 A6
1 A7

A9

23
A8 9
00 10
0 , 11
O2 13
0 314
04 15
05

r-:----

Os~

(UI2/8)

5V

~
22

13

_111~0
_

18
E/Pt':':'

24 V

-==

oc

~ C2 lOAD (UI3/ 12)
~C3 READ (UI4/4)
t!--C4RCVROE(UI4/13:
~ C5 MEM WE (UI5/2)
~ C6 MEM or (UI5/4)
~C7 BUS REO (U24/36:
rl--ca CNTEN (Ul0/l)

ClK
, . . - - - - _1

k -=--

SYS ClK
(U24/9)

~C1DMAC(W21/5)

0 0 10

r - -1 A7

Vee

OUT 15- 15

-----2J

(U23/2)

10

A8r

5V
+ 20

_ - - - - - - - : ; 1 8 AO
_ - - - - - - : 7 : 1 Al

~

5V
(U37/19 '=0 10~
(U46/6
3
lACK 1, ~
(UI6/22) RE'
FUll 122.
(U9/15) fAA
(U17/ CNT 13..!
4 15
(U23/6) TO ) DA 1 -

i

_

I

I

+20

..I.!;...
Vee

CK

l

7

9

8

r
GNO

O

5V

t

2&
11 ....,

I

~C9 Ail (UI6/21) 1~

lS374
U3

~

14
17
18

1 NOT USED
,3
1,2 ERROR

t-- (UI7/8)

6

13

~

~

Cl0 ADCE (J2-37)

f.L- Cl1 NZ (WI8/3)

_
O,S..
1

C12 BUSY (WI8/5)

3
lr-NDS
4 Wll

POLL (U23/33)
R19 5V
10k

L...___-_____

07.,!Z.,

L£
TL/F/9339-22

THE BIPLAN DP83421DP8343 BIPHASE LOCAL AREA NETWORK

(U16/~T'~"
ex/FO (1) 13 U3.
r-~~------------------------+-+Cl00

(US2/6)
(U30/4) Q(
(U30/S) 0

r-t'irr======:======;~tC10 1
CX/ro {R:

{USI/6~

(USI/3) ,

"r--4.2+I-f-+ Cl0 2

(USI/4) ,

5V!,
W2Oo1-

",...-+'-1>+-+ Cl0 3

~
DATI
(U16/16~

'"&,
-..J

10 2C

(U30/6) 02

(U30/7) 0',----4----+-t---------------,7lC

"

7't~7)
II ~n
L--~~::::::::::::::::::~~1Ff=::::::~~(U'-!LJ7)
W8,

DATA

...:::::r--4~ERROR (W23/2) SV

/\§

S.Y

r-__~~~,-L---~~~9 R~D

211 13

5 8 ERROR

-=

18 7 RA
~-.____~10~DA

__

"G2:

!-:4f---":'"!\OUT CONT
13

1llr~~~t=j~OUT
EN
21 87

J

........--11-_-'1' "
........--11-_..:.19'"185

/\§
nFOR

FOR 3618-2
FIBER - OPTIC

"

TTL

RECEIVERS

IN

DP8343

1.-41--~~~~B4 ~~R

1.-41--"'''
16 82

_______

1r4r---,IS'iBI
-t=:r--~114 BO RCVR

_IN 3

+ IN 2

DIS ClK

J2-S0
J2- 49
J2 - 49

6

I

TLlF/9339-26

96~·NV

AN-496

t
W19

~

I'

J2-43

[; J2-41
0 J2-42

-12V - - -......-10 J2-7.8
+12V - - C > J2-5.6

0

5V

J2-3.4

..r:!=>J2-1.2

QO
(U32/10)
Q1
(U32f7)
Q2
(U33/10)

~

.' "oj:'j"!...l.:!

U1

(U33~~ II'
iI
-

F

(J)

Ig(U6/4)---I19

74HC688
8-BIT COMPARATOR

Notes:
*--01 IS A SEPARATE GROUND BUS FROM U41-U44 TO EDGE (P1)
**-V1 IS A SEPARATE Vcc; BUS FROM U41-U44 TO EDGE (P1)
a--G2ISANOTHER GROUND BUS FROM U31 AND U17 TO EDGE (P1)
M-FOR MASTER SYSTEM ONLY.
R-FOR RING SYSTEM ONLY.

.I

1=lri-:

=- .

G1*
0575451
DUAL DRIVER- =G1*=G1*
FOR-3OD8-2
FIBER-OPTIC EMITTERS

TL/F/9339-23

THE BIPLAN DP8342/DP8343 BIPHASE
LOCAL AREA NETWORK

:l~~ ~~

J3-21

<:J

+12Y

CTS J3-10 <:J

W5

11
6

RTS J3-B < : J I - - - - - - - - - - - - - - - - - - - - - - - - - . . . . . . . : : . . . . . . . . ;

O:~~ J3-12 <:J

SET

TERO:~~J3-13
E:

~~

J3-7

5Y
15 jjA(jjj(j(ff Vee 40
32-39
hi----+-=~ RTS
C:~ 12

01

33

W4 4

11

ii'iii

CSI

~-~
~r J3-4<:J1---------------------~~;:==::~~­

GNDJ3-J4~
GND J3-25
5Y
PBO
PBl
TO OUT(U6/14)(W21/1) 6 TO OUT
PB2
RAM-1/0pB3
CE Nt~ 0 PB4
40 Vee

I\)

SYS ClK (U2V9) 3 TO IN

'"

CD

Xii (U5/1B) 5 Pes
iiR(U5/14) 2 PC4
Ui(UI6/23) 1 PC3

29
30
31
32
33

PB5 34
PB6 35
PB7 36

r----.....:li39!..1PC2(STAB)ADOIr.12:--_...v~

(Sf) AD111-"13:....-_..V ","
rr=======t=i:==j3B~PCl
----~r:~~~~~~37JP~(IN~)~2:~14~--..j,~

r

CD B7 12

21 PAO

AD3 15
AD4.J-ll16~_ _..j,.!1

B6 13
B5 14
...--+--'5"1A5 U45 B4 15

22 PAl
23 PAZ
Z4 PA3

AD6 .....'--_.....J
~7 ..1!.!!9~_.....J

8

~~Sol::;j+t=;:==i=~7 A7
~

S~B(U45/8)

6 A6

--~==:::It1rtfr=R

M 8303 B3 16
A3
B2 17
A2
Bl
Al

D7/P1-68 IOk>IOk,-_ _ _--.
IsiS
17'7
14'6
41 13,s
_

STATUS (TIL)

S'4

-

OR

7 3

74C374

~4 2

ADDRESS

3 01
ClK

DP8342
OP8343
MM74C374
DM74lS74
MM74COO
MM74C93
DM74lS00
MM74HC04

5VDC

GND

Pin

Pin
12
12
10

24
24
20
14
14
4
14
14

11

NSCBOOTM is a trademark of National Semiconductor
Corporation.

DATA!1Z
BI- PHASE RECEIVER
SERIAL TO PARALLEL
DATAIIs
DELAY

TO NScaOO" CARD

,

.1

PAO

I\)

PAl

I\)

PAl

m
R02 Oc
0D

o

r 11'
2

PA3

·'1
--

NC

AIN

PA4

REC
DlSABLE

.,N

OPEN 14
}:
FOR CHO ClK
ONLY

I

DATA
BUS

PAS
PA6
PA7

L.....---II_IN

RSTB DATA INTR

VREf

.

RSTA ERROR INTR

-----------------------.,,
NOTE 3'

2.SV

PB2

REG

PBI

READ

1N914

OUTPUT
ENABLE

SELECT DATA
OR ERROR REGISTER

READ DATA OR ERROR
CHIP SELEC ADDRESS

NC

10k
-. ADJ
tN914

NOTE "

TLIF/9339-20

r-------------------------------------------------------------'c"til
~National

PRELIMINARY

~

:=

~ Semiconductor
DP8344A Biphase Communications Processor-BCP
General Description

Table of Contents

The DP8344A BCP is a communications processor designed to efficiently process IBM 3270, 3299 and 5250 communications protocol, a general purpose 8-bit protocol is
also supported.

1.0 Block Diagram
2.0 Connection Diagram
3.0 Pin Descriptions
4.0 Electrical Specifications
5.0 InstrucUon Set Overview
6.0 Instruction Set Reference
7.0 CPU Register
8.0 Remote Interface" Arbitration System
9.0 Remote Interface Reference
10.0 Transceiver

The BCP integrates a 20 MHz 8-bit Harvard architecture
RISC processor, and an intelligent, software-configurable
transceiver on the same low power microCMOS chip. The
transceiver is capable of operating without significant processor interaction, releasing processor power for other tasks.
Fast and flexible interrupt and subroutine capabilities with
on-chip stacks, make this power readily available.
The transceiver is mapped into the processor's register
space, communicating with the processor via an asynchronous interface which enables both sections of the chip to
run from different clock sources. The transmitter and receiver run at the same basic clock frequency although the receiver extracts a clock from the incoming data stream to
ensure timing accuracy.
The BCP is designed to stand alone and is capable of implementing a complete communications interface, using the
processor's spare power to control the complete system.
Alternatively, the BCP can be interfaced to another processor with an on-chip interface controller arbitrating access to
data memory. Access to program memory is also possible,
providing the ability to download BCP code.
A simple line interface connects the BCP to the communications line. The receiver includes an on-chip analog comparator, suitable for use in a transformer-coupled environment,
although a TTL-level serial input is also provided for applications where an external comparator is preferred.
A typical system is shown below. Both coax and twinax line
interfaces are shown, as well as an example of the (optional) remote processor interface.

1.0 Block Diagram

....
Lin.

co
Co)

Features
Transceiver
• Software configurable for 3270, 3299, 5250 and general
8-bit protocols
• Fully registered status and control
• On-Chip analog line receiver
Processor
• 20 MHz clock (50 ns T-states)
• Max. instruction cycle: 200 ns
• 33 instruction types (50 total opcodes)
• ALU and barrel shifter
• 64k x 8 data memory address range
• 64k x 16 program memory address range
(note: typical system requires <2k program memory)
• Programmable wait states
• Soft-Ioadable program memory
• Interrupt and subroutine capability
• Stand alone or host operation
• Flexible bus interface with on-Chip arbitration logic
General
• Low power microCMOS; typo Icc = 25 mA at 20 MHz
• 84 pin plastic leaded chip carrier (PLCC) package

Typical BCP System

"""..v

Twtlax --~Pr-t--+

Uno

"
Note: At,plce.ll,"lm wll
require < 2k program memol')'

SyllttmI/o eul

TL/F/9336-51

2-63

2.0 Connection Diagram
Plastic Chip Carrier
:

~

Q

=~

~ ~ ~ ~ ~ ~ ~ ~ ~ ~
I I I

I I I

8

6

3

I I I I I
11 10 9

7

5

4

2

•

=~ ~I

I I I I I I

~ ~ ~
I I

I

84 83 82 81 80 79 78 77 76 75

A13- 12

74 I-IAl

A12- 13

73 I-IA2

All- 14

72 I-IA3

Al0- 15

711-IA4

A9- 16

701-IA5

A8- 17

691-IA6

AD7- 18

681-IA7

AD6- 19

67

AD5- 20

66 I- Vee

r- GND

AD4- 21

65 -IA8

Vee -

22

64 -IA9

GND -

23

63 -IA10

AD3- 24

62 -IAll

25

61 -IA12

AD1- 26

60 -IA13

AD2 -

27

59 -IA14

ALE- 28

58,...IA15

ADO -

READ -

29

57 f- GND

WRITE -

30

56 I-

LCL -

31

55 I- RESET

X-TCLK -

32

iWR

54 I- WAIT
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

TL/F/9336-2

Top View
Order Number DP8344V
See NS Package Number V84A

3.0 Pin Descriptions
Signal

I/O

Pin

Reset
State

Description

TIMING/CONTROL SIGNALS

I

Xl
X2

0

33
34

X
Xl

Input and output of the on-chip crystal oscillator amplifier. Connect a crystal
across these pins, or apply an external clock to Xl, with X2 left open.

ClK-OUT

0

35

Xl

Buffered CLocK oscillator OUTput, at the crystal frequency.

X-TClK

I

32

X

EXternal Transceiver CLocK input.

WAIT

I

54

0

CPU WAIT. When active, waits processor and remote interface controller.

RESET

I

55

X

Master RESET. Parallel reset to all sections of the ch....:ip'-._ _ _ _ _ _ _ _ _ __

0
0
0
0
0
0

l6-bit Instruction memory Address bus.

INSTRUCTION MEMORY INTERFACE
Instruction Address Bus:
IA15 (MSB)
IA14
IA13
IA12
IAll
IA10

0
0

0
0
0
0

58
59
60
61
62
63

2-64

3.0 Pin Descriptions (Continued)
Signal

I/O

Pin

Reset
State

Description

INSTRUCTION MEMORY INTERFACE (Continued)
Instruction Address Bus: (Continued)

0
0
0
0
0
0
0
0
0
0

64
65
68
69
70
71
72
73
74
75

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

76
77
78
79
80
81
82
83
2
3
4
5
6
7
8
9

IWR

0

56

I

Instruction WRite. Instruction memory write strobe.

IClK

0

51

0

Instruction CLocK. Delimits instruction fetch cycles. Rises during the first half of
T1, signifying the start of an instruction cycle, and falls when the next instruction
address is valid.

0
0
0
0
0
0
0
0

High byte of 16-bit memory Address.

0
0
0
0
0
0
0
0

low byte of 16-bit data memory Address, multiplexed with 8-bit Data bus.

IA9
IA8
IA7
IA6
IA5
IA4
IA3
IA2
IA1
lAO (lSB)

0
0
0
0
0
0
0
0
0
0

16-bit Instruction memory Address bus.

Instruction Bus:
115 (MSB)
114
113
112
111
110
19
18
17
16
15
14
13
12
11
10 (lSB)

16-bit Instruction memory data bus.

Timing Control:

DATA MEMORY INTERFACE
Address Bus:
A15(MSB)
A14
A13
A12
A11
A10
A9
A8

0
0
0
0
0
0
0
0

10
11
12
13
14
15
16
17

Multiplexed Address/Data Bus:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
ADO (lSB)

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

18
19
20
21
24
25
26
27

2-65

3.0 Pin Descriptions (Continued)
Signal

I/O

Pin

Reset
State

Description

DATA MEMORY INTERFACE (Continued)
Timing/Control:

28

0

0

29

I

Data memory READ strobe. Data is latched on the rising edge.

0

30

I

Data memory WRITE strobe. Data is presented on the rising edge.

ALE

0

READ
WRITE

Address latch Enable. Demultiplexes AD bus. Address should be latched on the
falling edge.

TRANSCEIVER INTERFACE
DATA-IN

I

39

X

logic level serial DATA INput.

AlG-IN+

I

42

X

Non-inverting AnaloG INput for biphase serial data.
Inverting AnaloG INput for biphase serial data.

I

41

X

DATA-OUT

0

38

I

DATA-DlY

0

37

0

Biphase serial DATA output DelaYed by one-quarter bit time.

TX-ACT

0

36

0

Transmitter ACTive. Normally low, goes high to indicate serial data is being
transmitted. Used to enable external line drive circuitry.

AlG-IN-

Biphase serial DATA OUTput (inverted).

REMOTE INTERFACE
RAE

I

46

X

Remote Access Enable. A "chip-select" input to allow host access of BCP
functions and memory.

CMD

I

45

X

CoMmanD input. When high, remote accesses are directed to the Remote
Interface Configuration (RIC l register. When low, remote accesses are directed
to data-memory, instruction-memory or program counter as determined by
(RICl.

REM-RD

I

47

X

REMote ReaD. When active along with RAE, a remote read cycle is requested;
serviced by the BCP when the data bus becomes available.

REM-WR

I

48

X

REMote WRite. When active along with RAE, a remote write cycle is requested;
serviced by the BCP when the data bus becomes available.

XACK

0

50

I

Transfer ACKnowledge. Normally high, goes low on REM-RD (or REM-WR going
low if RAE low) and returns high when the transfer is complete. Normally used as
a "wait" signal to the remote processor.

WR-PEND

0

49

I

WRite PENDing. In a system configuration where remote write cycles are
latched, indicates when the latches contain valid data which is yet to be serviced
by the BCP.

I

44

X

The remote processor uses this input to lOCK out local (BCP) accesses to datamemory. Once the remote processor has been granted the bus, lOCK gives it
sole access to the bus and BCP accesses are "waited".

0

31

0

loCal. Normally low goes high when the BCP relinquishes the data and address
bus to service a Remote Access.

I/O

53

I

Bi-directionallnterrupt ReQuest. As an input, can be used as an active low
interrupt input (maskable and level-sensitive). As an output, can be used to
generate remote system interrupts, reset via (RIC l.

I

52

X

Non-Maskable Interrupt. Negative edge sensitive interrupt input.

lOCK

lCl

EXTERNAL INTERRUPTS
BIRQ

NMI

2-66

4.0 Electrical Specifications
ABSOLUTE MAXIMUM RATINGS (Notes 1 & 2)

Power Dissipation (PD)
Lead Temperature (Soldering, 10 sec)
ESD Tolerance: CZAP = 100 pF,
RZAP = 15000

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (Vecl
-0.5Vto + 7.0V
DC Input Voltage (VIN) or
-0.5V to Vee + 0.5V
DC Input Diode Current
±20mA
DC Output Voltage (VOUT) or
-0.5V to Vee + 0.5V
DC Output Current, per Pin (lOUT)
±8.0mA
DC Vee or GND Current, per Pin
±50mA
Storage Temperature Range (TSTG)
-65"Cto + 150"C

500mW
260"C
1.8 kV

OPERATING CONDITIONS
Supply Voltage {Vecl
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
Input Rise or Fall Times (tr, If)

Min
4.5
0.0

Max
5.5
Vee

Units
V
V

0.0

70
500

"C
ns

DC ELECTRICAL CHARACTERISTICS Vee = 5V ± 10% (Unless otherwise specified)
Symbol

Parameter

Conditions

Guaranteed
Limits 0-70"C

Units

VIH

Minimum High Level
Input Voltage

X1 (Note 3)
DATA-IN
NMI
All Other Digital Inputs

3.8
2.3
2.3
2.0

V
V
V
V

VIL

Maximum Low Level
Input Voltage

X1 (Note 3)
DATA-IN
NMI
All Other Digital Inputs

1.5
0.6
0.6
0.8

V
V
V
V

0.4

V

25

mV

Min 2.25
Max 2.75

V
V

VIH-VIL

Minimum TTL-IN Hysteresis

VSENS

Analog Input IN+,
IN-Differential
Sensitivity

Figure6b

VSIAS

Common Mode Analog
Input Bias Voltage

User Provided Bias Voltage

VOH

Minimum High Level
Output Voltage
IA,A,AD
All Other Outputs

VIN = VIH or VIL
IIOUTI= 20 ",A
IIOUTI = 4.0 mA, Vee = 4.5V
IIOUTI = 1.0 mA, Vee = 4.5V

Vee - 0.1
3.5
3.5

V
V
V

Maximum Low Level
Output Voltage
IA,A,AD
All Other Outputs

VIN = VIH or VI
IIOUTI = 20 ",A
IIOUTI= 4.0mA, Vee = 4.5V
IIOUTI = 1.0 mA, Vee = 4.5V

0.1
0.4
0.4

V
V
V

Maximum Input Current

VIN = Vee or GND
ALG-IN-,ALG-IN+
X1 (Note 3)
All Others

±10
±20
±10

",A
",A
",A
",A

±10

",A

31
26

mA
mA

36
31

mA
mA

VOL

liN

loz

Maximum TRI-STATE®
Output Leakage Current

VOUT = Vee or GND

Maximum Operating
Supply Current
Total 4 Vee Pins
(Note 4)

VIN = Vee or GND
TCLK = 8 MHz, CPU-CLK = 16 MHz
Xcvr and CPU Operating
Xcvr Idle, CPU Waited
VIN = Vee or GND
TCLK = 20 MHz, CPU-CLK = 20 MHz
Xcvr and CPU Operating
Xcvr Idle, CPU Waited
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: X2 is an internal node with ESO protection. Do not use other than with crystal oscillator application.
Note 4: No DC loading, with XI driven, no crystal. AC load per Test Circuit for Output Tests.
lee

2-67

~
~

~
Q

4.0 Electrical Specifications (Continued)
ELECTRICAL CHARACTERISTICS AND SWITCHING
WAVEFORMS
Test Circuit for Output Tests

The following specifications apply for Vee = 4.5V to 5.5V,
TA = O°C to 70°C.

Vee

Notes on Timing:

SI (Not. 1)

t----o\ ~

• All timing with CPU-ClK running full speed [CRS) = 0
• DMEM refers to data memory
• IMEM refers to instruction memory

DEVICE
UNDER
TEST

INPUT

• RIC refers to Remote Interface Control register
• PC refers to the BCP Program Counter

RL
(Not. 2)
CL

.I.

50 pf (Not. 3)

• T = CPU-ClK period in ns
• C refers to the transceiver clock period in ns
• nlW
• nDW

= number of instruction wait states
= number of data wait states

TLlF/9336-A2
Note 1: 81

= Vee for tPZL. and tplz measurements

• nRW = number of wait states due to a remote access

8 1 = GND for tpZH, and tpHZ measurements

• All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more
parameters to create a new timing specification may lead
to invalid results.

5,

~

Open for push pull outputs

Note 2: Rl
RL

~

1.1 k for 4 mA outputs
4.4k for 1 mA outputs

~

Note 3: CL includes scope and jig capacitance.

Propagation Delay Waveforms
Except for Oscillator

Propagation Delay Waveform
for Oscillator

XI

INPUT

~IO"%:"-_GND

~:::::"--GND

CLK-OUT

TRUE
OUTPUT

L_-H
tP
- - t- VOH
2.5V

VOL
TLlF/9336-A4

INVERTED
OUTPUT
TL/F/9336-A3

Input Pulse Width Waveforms

POSITIVE
INPUT
PULSE

NEGATIVE
INPUT
PULSE

Setup and Hold Time Waveforms

CLOCK OR
LATCH ENABLE
(NOTE I) _ _ _ _.....:.:::

~1O"%:"-_GND

POSITIVE
DATA INPUT

~:::--3.0V

90%

NEGATIVE
DATA INPUT

TL/F/9336-AS

TL/F/9336-A6
Note 1: Waveform for negative edge sensitive Circuits will be inverted.

2-68

4.0 Electrical Specifications

(Continued)

TRI-STATE Output Enable and Disable Waveforms

-- r-

r-------

-, r-

t r =6ns

90~~

OUTPUT CONTROL
~90%
(LOW ENABLING) ---1Q!.. 1.5V

1.5V

tf =6ns

-3.0V

10%

.-tpLZ -

. - tpZl --

,

----VOH

"

k;;

OUTPUT

..-tpHZ OUTPUT

GND

~,VOL

.- tpZH -/

CVOH
1.3V
-----VOl
TLiF/9336-A7

Data Memory Read Timing
Symbol

10#

Parameter

Min
-7

ns

T+

-28

ns

3

ns

27

ns

1

ALE High

tpD-AD-ALE

2

AD (Data Address) Valid to ALE Falling

tpD-ALE-AD

3

ALE Falling to AD (Data Address) Invalid

tSU-RD

4

Data Valid before READ Rising

tH-RD

5

Data Valid after READ Rising

-1

tAZ-RD-AD

6

READ Falling to AD Disabled

0.5T+

Max

ns
26

tpD-RD-DATA

7

READ Falling to AD (Data) Set-Up

tZA-RD-AD

8

READ Rising to AD Enabled

tpD-AD-RD

9

AD (Data Address) Valid before READ Falling

tW-RD

10

READ Low

tACC-D

11

Data Memory Read Time

Units

Formula
(nRW+1)T+

tW-ALE

ns

-28

ns

2

ns

1.5T+

-25

ns

(MAX(nDW,nIW-1)+ l)T+

-10

(MAX(nDW,nIW-1)+ l)T +

(MAX(nDW,nIW-1) + 2.5)T +

ns
-51

ns

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.

Data Memory Read Timing
Tl
CLK-OUT

ALE

Tx

T2

r~
~-

AD

j/////////////J

A

0"///////////J

--:l0

3 -

ADDR

DATA

.cv.

0--

READ

l-K2Z

-r-"

-

1--0--

f--0---

0-

I+-

-@)- r----

@
TL/F/9336-52

2-69

4.0 Electrical Specifications

(Continued)

Data Memory Write Timing
Symbol

10#

Parameter

tW-ALE

1

ALE High

tpD-AD-ALE

2

AD (Data Address) Valid to ALE Falling

tPD-ALE-AD

3

ALE Falling to AD (Data Address) Invalid

tPD-DATA-WR

4

AD (Data) Valid to WRITE Rising

tpD-ADDR-WR

5

AD (Data Address) Valid to WRITE Falling

tpD-WR-DATA

6

WRITE Falling to AD (Data) Valid

tPD-WR-DATAz

7

WRITE Rising to AD (Data) Invalid

tW-WR

8

WRITE low

Formula

Min

(nRW+1)T+

-7

Max

ns

T+

-28

ns

0_5T+

-2

ns

(MAX(nDW,nIW-1) + 1)T +

-12

ns

1_5T+

-22

Units

ns
11

ns

0_5T+

4

ns

(MAX(nDW,nIW -1) + 1)T +

-11

ns

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.

Data Memory Write Timing
Tx

TI

T2

elK-OUT

p~ 0-

ALE

AD

////////////L2

A

/LLL//U///d/4

~

DATA

ADDR

- 0 --

WRITE

-

-01-0-

- 0 - 0-

TL/F/9336-53

Instruction Memory Read Timing
Symbol

10#

tSU-I-ICLK

1

I Valid before IClK Rising

tH-I-ICLK

2

I Invalid before IClK Falling

tPD-IA-ICLK

3

IA Valid before IClK Falling

tACC-1

4

Parameter

Formula

Min

Max

Units

23

ns

22

O.5T+

Instruction Memory Read Time

(nIW+ 1,5)T +

ns

-7

ns
-24

ns

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.

Instruction Memory Read
leLK

---I

CDI

IA

:2K

-

-10 -

- CD'I-

X'/ ////////,~

1+0K

0
TLlF/9336-54

2-70

4.0 Electrical Specifications (Continued)
Clock Timing
Symbol

10#

Parameter

Min

Max

50

500

ns

32

ns

ClK-OUT Rising to IClK Rising

29

ns

ClK-OUT Rising to IClK Falling (Note 3)

29

ns

500

ns

tT-X1

1

XI Period (Note 2)

tpO-XI-CO

2

XI to ClK-OUT (Note 2)

tpO-CO-IClKr

3

tpO-CO-IClKf

4

tT-XT

5

X-TClK Period (Note 4)

Formula

50

Units

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.
Note 2: Measurement thresholds at 2.5V.
Note 3: The falling edge of lelK occurs only after the next IA becomes valid. The CLK·QUT cycle in which this occurs depends on the instruction being executed
and the number of programmed instruction wait states.
Note 4: There is no relationship between X1 and X-TCLK. X-TCLK is fully asynchronous.

Clock Timing

}

XI

ClK-OUT

IClK

f

J0t

Cl
~®-

X-TCLK

-' ~ ~

TL/F/9336-55

•
2-71

I

~

~

co
a..

4.0 Electrical Specifications

(Continued)
Transceiver Timing

Q

Symbol

10#

Parameter

Formula

Min

Max

Units

X1 Rising to TX-ACT Rising/Falling

18

80

ns

tPD-XTCLK-TA

2

X-TCLK Rising to TX-ACT Rising/Falling

13

63

ns

tpD-TA-DO

3

TX-ACT Rising/Falling to DATA-OUT Falling/Rising (Note 2)

-12

8

ns

tW-DO-HB

4

DATA-OUT Half Bit Cell Width

4C+

-10

10

ns

tW-DO-FB

5

DATA-OUT Full Bit Cell Width

8C+

-10

10

ns

tPD-DO-DD

6

DATA-OUT Falling/Rising to DATA-DLY
Rising/Falling (Note 2)

2C+

-10

10

ns

tSK-DO-DD

7

DATA-OUT, DAT A-DL Y Skew after TX-ACT
Falling (Note 3)

7

ns

tpD-Xl-TA

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.
Note 2: lATA] ~ 0, [TIN] ~ 'I.
Note 3: 5250 mode, [TIN] ~ 1, and line hold (lATA [7-3]1 ~ 00000), If any line hold is programmed (lATR [7-31 J " 00001), then tSK-OO-OO will be the same as
tPD-DO-DD. With no line hold DATAMDLY transitions at the same time as TX-ACT.

(a) Transmission Beginning Timing
XlorX-TCLK

©1~
TX-ACT _ _ _ _ _~

0---1

{'--_ _- I I
I

DATA-DLY _ _ _ _ _ _ _ __

TL/F/9336-56

(b) Transmission Ending Timing
XlorX-TCLK

:T-:-----~-

TX-ACT

DATA-DLY

\~

\~--------~t~._. ._0________________

_______JI

TLlF/9336-57

2-72

c

."

4.0 Electrical Specifications (Continued)

co

........

Co)

Analog and DATA·IN Timing
Symbol

ID#

Parameter

Min

Max

Units

tW-Tl-hb

1

DATA-IN Data, Half Bit Width

3C+6

5C-6

ns

tW-Tl-fb

2

DATA-IN Data, Full Bit Width

7C+6

9C-6

ns

tW-AN-hb

3

Analog Data, Half Bit Width
(-ALG-INor +ALG-IN)

3C+33

5C-33

ns

tW-AN-fb

4

Analog Data, Full Bit Width
(-ALG-IN or +ALG-IN)

7C+33

9C-33

ns

Formula

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.

(a) DATA·IN Jitter Timing (3270)

I

TIL-IN

Manchester

~

tP

I

t.4anchester

tP

~

r=0=1

I

Manchester 1

!

CD

I

TL/F/9336-58

(b) Analog Jitter Timing (3270)

I
ALG-IN+

Monchester

,~

tP

~

I

Monchester

./"""..

tP

Monchester 1

I
~

--

BOrnY

tf
ALG-IN- "

'-""'"

.....--.....

_ _ _ BOrnY

'-""'"

t
TLiF/9336-59

2-73

»

4.0 Electrical Specifications (Continued)
Interrupt Timing
Symbol

10#

Parameter

tW·NMI

1

NMI low

tpD.IClK.BQ

2

iClK Rising to BiRQ (Output) Rising/Falling

Formula

Min

Tx

2

Max

Units
ns

31

ns

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results,

(a) Interrupt Timing
T2

I

ClK-OUT

~

IClK~
NMI
BIRO
(input)

IA

I

\

T1
(of NOP inst)

I

\

'--

I

t=0

I

I

*I

\

Interrupt Vector
Address

Next Instruction Address

TL/F 19336-60

(b) BIRQ Output Timing
T2
ClK-OUT

IClK

BIRO
(output)

\

T1

T1

~~

I

J

r r

~~
\I

2·74

TL/F/9336-61

4.0 Electrical Specifications

(Continued)
Control Pin Timing

Symbol

10#

Min

1

RESET Low

Tx

10

tPD-RST-ICLK

2

RESET Rising to ICLK Rising

Tx

4

ns

tSU-ALE-WT

3

WAIT Low after ALE High to Extend Cycle

T+

-28

ns

tR-WT-RDWR

4

WAIT Rising before READ or WRITE Rising

2.5T-1

ns

tW-STRT

5

RESET, REM-RD, REM-WR Low for BCP to Start (Note 2)

tSU-LK-ICLK

6

LOCK Low before ICLK High (Note 3)

tR-LK-ALE

7

LOCK High to ALE Low

Parameter

Max

Units

Formula

tW-RST

ns

1.5T-27
10

Tx

ns

7

ns

1.5T -13

2.5T+5

ns

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.
Note 2: Edges need not be synchronized or asserted/deasserted in any particular order.
Note 3: If tSU-LK-ICLK is not met. the maximum time from LOCK low till no more local accesses is T(MAX(nDW. nlw-1}+3).

Control Pin Timing

--r-0~
RESET

ICLK

\.

/

-

-0-

TL/F/9336-62

WAIT Pulse Width

WAIT

.1

~

f

ALE

1

f

-:.10

I-

\.

READ or
WRITE
TL/F/9336-63

BCP Start Timing

.

CD

RESET

REM-RD

REM-WR

TL/F19336-64

LOCK Timing
LOCK
ICLK
ALE

j®f

\

I

l®f
TLlF/9336-AB

2-75

c(
'<:I'
'<:I'

C")

co

4.0 Electrical Specifications

c..

(Continued)
Buffered Read of PC, RIC

C

Max

10#

Parameter

tSU-RR-CO

1

RAE, REM-RD Falling before ClK-OUT Rising

14

ns

tH-RR-X

2

RAE, REM-RD Rising after XACK Rising

0

ns

tSU-CMD-CO

3

CMD Valid before ClK-OUT Falling

0

ns

tH-CMD-CO

4

CMD Invalid after ClK-OUT Falling

35

tPD-RR-X

5

RAE, REM-RD Falling to XACK Falling

Symbol

Formula

Min

Units

ns

31

ns

1

tZA-LCL-A

6

A Disabled before LCL Rising

tAZ-LCL-A

7

A Enabled before LCL Falling

tpD-PC-X

8

AD (PC, RIC) Valid before XACK Rising

tpD-PC-RR

9

REM-RD, RAE Rising to AD (PC) Invalid

tW-PC-b

10

AD (PC, RIC) Valid Time

ns

13
T+

T+

ns

-30

ns

8

ns

-2

ns

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing

specification may lead to invalid results.

Buffered Read of PC, RIC

XACK

-°---:1

I~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~

_JI

LCL ________________~~

R~D -------------------+--------------------~~--~--------------~--~

~I

-I

-CD

-0

A====~~--~_r---t=

1-0~0-.~---t
f

AD _ _ _ _ _ _ _R_IC_ _ _ _ _ _ _ _

R®C

RIC

TLiF/9336-65

2-76

4.0 Electrical Specifications

(Continued)

Buffered Read of OMEM
Symbol
tSU-RR-CO

10#

Parameter

1

RAE, REM-RD Falling before ClK-OUT Rising

Formula

Min

Max

Units

14

ns

tH-RR-X

2

RAE, REM-RD Rising after XACK Rising

0

ns

tSU-CMD-CO

3

CMD Valid before ClK-OUT Falling

0

ns

tH-CMD-CO

4

CMD Invalid after ClK-OUT Falling

35

tpD-RR-X

5

RAE, REM-RD Falling to XACK Falling

tpD-RD-X

6

READ Falling to XACK Rising

ns

31
(nDW+1)T+

ns

-25

ns
ns

tpD-RR-RD

7

REM-RD, RAE Rising to READ Rising

5

tZA-LCL-AAD

8

A, AD Disabled before lCl Rising

2

tAZ-LCL-AAD

9

A, AD Enabled before lCl Falling

tW-RD-b

10

READ low

ns
17

ns

-2

(nDW+1)T+

ns

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing

specification may lead to invalid results.

Buffered Read of OMEM
ClK-OUT

-

RAE

CMD

0fl0

~£:w~~

- CD -

- 1-0
-,
REM-RD

XACK

-°1

-

~

lCl

~'--

--0-READ

AD,A

-)

-0

.

@

-0-1
-J;1

-~
TL/F/9336-66

2-77

~

~

4.0 Electrical Specifications (Continued)

CO

tl.

Buffered Read of IMEM

Q

10#

Parameter

tSU-RR-CO

1

RAE, REM-RD Falling before ClK-OUT Rising

14

ns

tH-RR-X

2

RAE, REM-RD Rising after XACK Rising

ns

tSU-CMD-CO

3

CMD Valid before ClK-OUT Falling

o
o

tH-CMD-CO

4

CMD Invalid after ClK-OUT Falling

35

tpD-RR-X

5

RAE, REM-RD Falling to XACK Falling

tZA-LCL-A

6

A Disabled before lCl Rising

tAZ-LCL-A

7

A Enabled before lCl Falling

tpD-IMEM-X

8

AD (IMEM) Valid before XACK Rising

tpD-RR-IMEM

9

AD (IMEM) Invalid after RAE, REM-RD Rising

tW-IMEM-b

10

fMEMValid

tPD-LCL-IA-b

11

lCl Falling to Next fA Valid (Note 2)

Symbol

Formula

Min

Max

Units

ns
ns

31

ns

13

ns

1

ns

-32

ns

10

ns
ns

T+

-32

o

ns

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.
Note 2: Two remote reads from instruction memory are necessary to read a 16-bit instruction word from IMEM-Iow byte followed by high byte. The timing for the
two reads are the same except that IA is incremented after the high instruction memory byte is read.

Buffered Read of IMEM

-+

CD ,-,._________

-®~I
XACK
~L

\:

~-----------------------',

______________

~

R~D ----------------~------------------~----~--------------~~------

-10 A====~~~~~-----~=
I----@------+I
-I -(6)

--0--

-0-

fA ____________________________________________________________ 1
___
_ J~,

TL/F/9336-67

2-78

c

"tJ

4.0 Electrical Specifications (Continued)

01)

w

,j:o,
,j:o,

»

Latched Read of PC, RIC

10#

Symbol

Parameter

Formula

Min

Max

Units

tSU-RR-CO

1

RAE, REM-RD Falling before ClK-OUT Rising

tH-RR-X

2

RAE, REM-RD Rising after XACK Rising

0

ns

tSU-CMD-CO

3

CMD Valid before ClK-OUT Falling

0

ns

tH-CMD-CO

4

CMD Invalid after ClK-OUT Falling

35

tpD-RR-X

5

RAE, REM-RD Falling to XACK Falling

tZA-LCL-A

6

A Disabled before lCl Rising

14

ns

ns
31

ns

1

tAZ-LCL-A

7

A Enabled before lCl Falling

tpD-PC-X

8

AD (PC) Valid before XACK Rising

tpD-X-PC

9

XACK Rising to AD (PC) Invalid

tw-PC

10

AD (PC, RIC) Valid

ns
13

ns

-30

ns

0_5T+

4

ns

1_5T+

-12

ns

T+

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing

specification may lead to invalid results.

Latched Read of PC, RIC

XACK

-0''--------------------------JI
\:

LCL _ _ _ _ _ _ _ _ _ _1

R~D .....----------------~~------------------~----------t_~~-----

-I, -0
A====~~------~~4====
-I -0

CD ~-~-0.@-----<.

AD _ _ _ _ _ _ _ _
RI_C_ _ _ _ _ _ _....

RIC, PC

• _'--_ _ _ _
RIC_ _ _ __

TLIF/9336-68

2-79

4.0 Electrical Specifications (Continued)
latched Read of OMEM

10#

Parameter

tSU-RR-CO

1

RAE, REM-RD Falling before ClK-OUT Rising

14

ns

tH-RR-X

2

RAE, REM-RD Rising after XACK Rising

0

ns

tSU-CMD-CO

3

CMD Valid before ClK-OUT Falling

0

ns

tH-CMD-CO

4

CMD Invalid after ClK-OUT Falling

35

ns

tpD-RR-X

5

RAE, REM-RD Falling to XACK Falling

tZA-lCl-AAD

6

A, AD Disabled before lCl Rising

tAZ-lCl-AAD

7

A, AD Enabled before lCl Falling

tpD-RD-X

8

READ Falling before XACK Rising

tpD-X-RD

9

XACK Rising to READ Rising

tW-RD

10

READ low

Symbol

Formula

Min

Max

Units

31

ns

2

ns
17

ns

(nDW+1)T+

-25

ns

0.5T+

-4

ns

(nDW + 1.5)T +

-14

ns

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing

specification may lead to invalid results.

latched Read of OMEM

ClK-OUT

RAE

CMD

0~0

~:

-

I-CD

Y~~~ffA

- CD -

REM-RD ""'"

XACK

-°-:1~

lCl

-0--0
READ

AD,A

-)

-0

.

@-

-~ -0
TL/F/9336-69

2-80

4.0 Electrical Specifications

(Continued)

Latched Read of 1M EM

10#

Parameter

1

RAE, REM-RD Falling before ClK-OUT Rising

tH-RR-X

2

tSU-CMD-CO

3

tH-CMD-CO

Symbol

Formula

Min

Max

Units

14

ns

RAE, REM-RD Rising after XACK Rising

0

ns

CMD Valid before ClK-OUT Falling

0

ns

4

CMD Invalid after ClK-OUT Falling

35

tpD-RR-X

5

RAE, REM-RD Falling to XACK Falling

tZA-lCl-A

6

A Disabled before lCl Rising

tAZ-lCl-A

7

A Enabled before lCl Falling

tpD-IMEM-l

8

AD (IMEM) Valid to XACK Rising

tpD-X-IMEM

9

XACK Rising to AD (IMEM) Invalid

tpD-lCl-IA

10

lCl Falling to Next IA Valid (Note 2)

tW-IMEM

11

IMEMValid

tSU-RR-CO

ns
31

ns

1

ns
13

(nIW+1)T+

-32

0.5T+

-5

T+

-30

(nlW + 1.5)T +

-30

ns
ns
ns

0

ns
ns

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing

specification may lead to invalid results.
Note 2: Two remote reads from instruction memory are necessary to read a 16-bit instruction word from IMEM-Iow byte followed by high byte. The timing for the
two reads are the same except that IA is incremented after the high instruction memory byte is read.

Latched Read of IMEM
elK-OUT

RAE

CMD

0n°

~~~~=
CD - 1-0

-

REM-RD ""'"

T

-0-:1
XACK

\:

-

LCL

READ

~

0-1

-1° -

-

A

-®----r-&
AD

RIC

.

IA

1M EM

@

--@rRIC

,-r

TLiF/9336-70

2-81

4.0 Electrical Specifications (Continued)
Slow Buffered Write of PC, RIC
Symbol

10#

Parameter

tSU-RW-CO

1

RAE, REM-WR Falling before ClK-OUT Rising

14

ns

tH-RW-X

2

RAE, REM-WR Rising after XACK Rising

0

ns

tSU-CMD-CO

3

CMD Valid before ClK-OUT Falling

0

ns

tH-CMD-CO

4

CMD Invalid after ClK-OUT Falling

35

tpD-RW-X

5

RAE, REM-WR Falling to XACK Falling

tZA-lCl-AAD

6

A, AD Disabled before lCl Rising

tAZ-lCl-AAD

7

A, AD Enabled before lCl Falling

Formula

Min

Max

Units

ns

40

ns

17

ns

ns

2

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing

specification may lead to invalid results.

Slow Buffered Write of PC, RIC

ClK-OUT

RAE

0~_- ~0

CMD~

."-, 4-eDthD

~~~ijd

1°f

XACK

LCL
WRITE
AD,A

lLi)

C)

-~

to
TL/F/9336-71

2-82

4.0 Electrical Specifications (Continued)
Slow Buffered Write of OMEM

10#

Parameter

tSU-RW-CO

1

RAE, REM-WR Falling before ClK-OUT Rising

14

ns

tH-RW-X

2

RAE, REM-WR Rising after XACK Rising

0

ns

tSU-CMD-CO

3

CMD Valid before ClK-OUT Falling

0

ns

tH-CMD-CO

4

CMD Invalid after ClK-OUT Falling

35

tpD-RW-X

5

RAE, REM-WR Falling to XACK Falling

tpD-WR-X

6

WRITE Falling to XACK Rising

tPD-RR-WR

7

Symbol

tZA-lCl-AAD

8

Min

Formula

Max

Units

ns
40

ns

-32

ns

REM-WR, RAE Rising to WRITE Rising

8

ns

A, AD Disabled before lCl Rising

2

ns

(nDW+ 1)T+

tAZ-lCl-AAD

9

A, AD Enabled before lCl Falling

tW-WR-b

10

WRITE low

ns

17
0

(nDW+1)T+

ns

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.

Slow Buffered Write of OMEM

ClK-OUT

RAE

0~0

~£=~
1-0
CD
-~
CMD

-

REM-WR

XACK

-

--°-:1lk

lCL

~

-0WRITE

AD,A

-) -0

.

@

---0-

.

-~ -0
TL/F/9336-72

2-83

4.0 Electrical Specifications (Continued)
Slow Buffered Write of IMEM (Notes 1,2)

10#

Parameter

tSU-RW-CO

1

RAE, REM-WR Falling before ClK-OUT Rising

14

ns

tH-RW-X

2

RAE, REM-WR Rising before ClK-OUT Rising

0

ns

tSU-CMD-CO

3

CMD Valid before ClK-OUT Falling

0

ns

tH-CMD-CO

4

CMD Invalid after ClK-OUT Falling

35

tpD-RW-X

5

RAE, REM-WR Falling to XACK Falling

tZA-LCL-AAD

6

A, AD Disabled before lCl Rising

tAZ-LCL-AAD

7

A, AD Enabled before lCl Falling

tPD-LCL-IA-b

8

lCl Falling to Next IA Valid

tPD-IWR-X

9

IWR Falling before XACK Rising

tPD-RR-IWR-b

10

tZA-IWR-I-b

11

tAZ-IWR-I-b
tPD-I-IWR-b

Symbol

Min

Max

Units

ns
40

ns

17

ns

0

ns

2

ns

T+

-32

(nIW+1)T+

-28

ns

REM-WR, RAE Rising to IWR Rising

8

ns

IWR Falling to I Enabled

0

12

IWR Rising to I Disabled

28

13

I Valid before IWR Rising

14

tW-IWR-b

Formula

IWR low

ns
51

ns

(nIW+1)T+

-8

ns

(nlw+1)T+

-1

ns

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.
Note 2: Two remote writes to instruction memory are necessary to store a 16-bit instruction word to IMEM-Iow byte followed by high byte. The timing for the 2nd
write is shown in this diagram. The timing of the first write is the same as a write of the PC or RIC.

Slow Buffered Write of IMEM

......

~

RAE--

0n°
--

CMoW/A:

~~~$~.@"/.Z

-- CD --

1--0

REM-WR ---,

-0..:1
XACK

La:
WRITE

\
~

--I --0

r- 1-\

AO,A

~

IA

I

-1

@i~ =t®
@

IWR

f-I

@

-I --0
-0..:1

r-

TL/F/9336-73

2-84

4.0 Electrical Specifications

(Continued)
Fast Buffered Write of RIC, PC

Symbol

Min

Max

Units

10#

Parameter

tSU-RW-CO

1

RAE, REM-WR Falling before CLK-OUT Rising

14

ns

tH-RW-X

2

RAE, REM-WR Rising after XACK Rising

0

ns

tSU-CMD-CO

3

CMD Valid before CLK-OUT Falling

0

ns

tH-CMD-CO

4

CMD Invalid after CLK-OUT Falling

35

tpD-RW-X

5

RAE, REM-WR Falling to XACK Falling

tZA-lCl-AAD

6

A, AD Disabled before LCL Rising

tAZ-lCl-AAD

7

A, AD Enabled before LCL Falling

Formula

ns
ns

40

ns

2

ns

17

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.

Fast Buffered Write of RIC, PC

elK-OUT

RAE

Ct.tO

REt.t-WR

XACK

0B0

~~~YA

4~(i)

1

0t

-®-l

lCl
WRITE

AO,A

-If-CD

(

)

~

TL/F/9336-74

2-85

4.0 Electrical Specifications

(Continued)
Fast Buffered Write of OMEM

Symbol

10#

Parameter

tSU-RW-CO

1

RAE, REM-WR Falling before ClK-OUT Rising

14

tH-RW-X

2

RAE, REM-WR Rising after XACK Rising

0

ns

tSU-CMO-CO

3

CMD Valid before ClK-OUT Falling

0

ns

tH-CMO-CO

4

CMD Invalid after ClK-OUT Falling

35

ns

Formula

tpO-RW-X

5

RAE, REM-WR Falling to XACK Falling

tpO-X-WR

6

XACK Rising to WRITE Rising

IpO-WR-X

7

WRITE Falling to XACK Rising

tZA-LCL-AAO

8

A, AD Disabled before lCl Rising

IAZ-LCL-AAO

9

A, AD Enabled before lCl Falling

tW-WR

10

WRITE low

Min

Max

Units

ns

40

(now+1)T+

ns

1

ns

-31

ns

2

ns
17

(now+1)T+

ns

-12

ns

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.

Fast Buffered Write of OMEM

ClK-OUT

RAE

CMD

REM-WR

0BG)
~=d
- - -- I-CD
CD jl.

~0..:j

XACK

\:

- -0

lCl

~

-0-WRITE

-@-

-) -0
AD,A

-~
TL/F 19336-75

2-86

4.0 Electrical Specifications

c"a
00

(Continued)

Co)

Fast Buffered Write of IMEM
Symbol

10#

Parameter

Formula

Min

Max

Units

ISU-RW-CO

1

RAE, REM-WR Falling before ClK-OUT Rising

14

ns

tH-RW-X

2

RAE, REM-WR Rising after XACK Rising

0

ns

tSU-CMD-CO

3

CMD Valid before ClK-OUT Falling

0

ns

tH-CMD-CO

4

CMD Invalid after ClK-OUT Falling

35

tpD-RW-X

5

RAE, REM-WR Falling to XACK Falling

tZA-LCL-AAD

6

A, AD Disabled before lCl Rising

tAZ-LCL-AAD

7

A, AD Enabled before lCl Falling

tPD-LCL-IA

8

lCl Falling to Next IA Valid

ns
40

T+

-30

(nIW+1)T+

-28

ns
ns

2
17

ns

0

ns

tPD-IWR-X

9

IWR Falling before XACK Rising

tPD-X-IWR

10

XACK Rising to IWR Rising

0

ns

tZA-IWR-1

11

IWR Falling 10 I Enabled

0

ns

tAZ-IWR-1

12

IWR Rising to I Disabled

28

tpD-I-IWR

13

I Valid before IWR Rising

(nIW+1)T+

-26

ns

tW-IWR

14

IWRlowTime

(nIW+1)T+

-12

ns

ns

52

ns

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing

specification may lead to invalid results.
Note 2: Two remote writes to instruction memory are necessary to store a 16~bit instruction word to IMEM-Iow byte followed by high byte. The timing of the 2nd
write is shown in this diagram. The timing of the first write is the same as a write of the PC or RIC.

Fast Buffered Write of IMEM

XACK

I~

~

______________________________-JI

~ ------------------~
WRITE

------------------~--~--------------+_----------+_~~----

-I --CD
- --0
AD,A :::::::::j--=-----~c::t:::::>----i:t::::=
~0---. CD.t.
~X

------------------------------------r----------r-----------------JII~--

@- --:;

I---------------------------~~~----------­
@_ ~@-o '~@

IWR

-----------------------~~I

I,-~------------------

i+--@_
TL/F 19336-76

2-87

"'"'""
»

4.0 Electrical Specifications (Continued)
Latched Write of PC, RIC

10#

Parameter

tSU-RW-CO

1

RAE, REM-WR Falling before ClK-OUT Rising

14

ns

tH-RW-CO

2

RAE, REM-WR Rising after ClK-OUT Rising

20

ns

tH-RW-X

3

RAE, REM-WR Rising after XACK Rising

0

ns

tSU-CMD-CO

4

CMD Valid before ClK-OUT Falling

0

ns

tH-CMD-CO

5

CMD Invalid after ClK-OUT Falling

35

ns

tpD-RW-X

6

RAE, REM-WR Falling to XACK Falling

tZA-LCL-AAD

7

A, AD Disabled before lCl Rising

tAZ-LCL-AAD

8

A, AD Enabled before lCl Falling

tPD-CO-WPND

9

ClK-OUT Rising to WR-PEND Falling/Rising

Symbol

Formula

Min

Max

Units

40

ns

2

ns

10

17

ns

57

ns

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing

specification may lead to invalid results.

Latched Write of PC, RIC

CLK-OUT

~~~'---I'-Qr ~
~_
"L0--- t~I f-0
- K5)

_ CD{~f:.®

RAE
CMD
REM-WR

,I::

//

CD-{

11', / / /

I: F/~
~f-®'-

Qr

1-:-of-

~®.:I
-\;

XACK

~

"L-

LCL

I

WRITE
AD,A
WR-PEND

,-®

_---t

1-0

-I

I..-®

®---

f
TLlF/9336-77

2-88

4.0 Electrical Specifications

(Continued)

Latched Write of OMEM

10#

Parameter

tSU-RW-CO

1

RAE, REM-WR Falling before ClK-OUT Rising

14

ns

tH-RW-CO

2

RAE, REM-WR Rising before ClK-OUT Rising

20

ns

tH-RW-X

3

RAE, REM-WR Rising after XACK Rising

0

ns

tSU-CMD-CO

4

CMD Valid before ClK-OUT Falling

0

ns

tH-CMD-CO

5

CMD Invalid after ClK-OUT Falling

35

tpD-RW-X

6

RAE, REM-WR Falling to XACK Falling

Symbol

Formula

Min

Max

Units

ns
40

tZA-lCl-AAD

7

A, AD Disabled before lCl Rising

tAZ-lCl-AAD

8

A, AD Enabled before lCl Falling

tW-WR

9

WRITE low Time

tPD-CO-WPND

10

ClK-OUT Rising to WR-PEND Falling/Rising

ns
ns

2
17
(nDW+1)T+

ns

-6

ns

10

57

ns

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing

specification may lead to invalid results.

latched Write of OMEM

.....J~~\.....ir--

ClK-OUT

_(i)~~f:.®

~~~'

@-~I

RAE

~~

~

0- •
-0

-

(i){ f-t®

REt.l-WR

~

r-(~

V~

0- 1-f

-®~
"It

XACK

LCl

"It

WRITE

-.::I
AD,A

WR-PEND

,-@

~0

-f

I-®~

i.-@

@- f-

TL/F/9336-7B

2-89

4.0 Electrical Specifications (Continued)
latched Write of IMEM

10#

Parameter

tSU-RW-CO

1

RAE, REM-WR Falling before ClK-OUT Rising

14

ns

tH-RW-CO

2

RAE, REM-WR Rising after ClK-OUT Rising

20

ns

tH-RW-X

3

RAE, REM-WR Rising after XACK Rising

0

ns

tSU-CMD-CO

4

CMD Valid before ClK-OUT Falling

0

ns

tH-CMD-CO

5

CMD Invalid after ClK-OUT Falling

35

IpD-RW-X

6

RAE, REM-WR Falling to XACK Falling

IpD-lCl-IA

7

lCl Falling to Next IA Valid

IZA-lCL-AAD

8

A, AD Disabled before lCl Rising

tAZ-lCL-AAD

9

A, AD Enabled before lCl Falling

IpD-CO-WPND

10

ClK-OUT Rising to WR-PEND Falling/Rising

10

IZA-IWR-I

11

IWR Falling to I Enabled

0

tAZ-IWR-1

12

IWR Rising to I Disabled

28

IpD-I-IWR

13

I Valid before IWR Rising

(nIW+l)T+

-26

ns

tW-IWR

14

IWR low Time

(nIW+l)T+

-7

ns

Symbol

Formula

Min

Max

ns

40

ns

0

ns

-30

T+

Units

2

ns

17

ns

57

ns
ns

52

ns

Note 1: All parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results.
Note 2: Two remote writes to instruction memory are necessary to store a 16-bit instruction word to IMEM-Iow byte followed by high byte. The timing of the 2nd
write is shown in this diagram. The first write is the same as a write of the PC or RIC.

latched Write of IMEM

--I~

ClK-OUT

~

CD{-t.0

REM-WR

-H ~0

~{.

RAE
CMD

-@

0~
~

~I

- t:.®

-

CD{Ft:0
~

~

lCl
WRITE

-+j

WR-PEND

~

"®..:j

XACK

AD,A

/{/ '///

@t:.

-

-,

-®

~®

® .. ~

®

~CV3t:

IA

@1~@J4.

I
IWR

-@
TL/F/9336-79

2-90

5.0 Instruction Set Overview
INTRODUCTION

OPERAND ADDRESSING MODES

Utilizing a total of only 30 basic instructions and capable of
5 basic addressing modes, the BCP's instruction set is very
easy to learn, executes extremely fast, and greatly reduces
the programming effort required in communications processing. This is possible because the BCP is a Reduced
Instruction Set Computer; (Le., employs a RISC processor.)
The following paragraphs introduce the BCP's architecture
by discussing addressing modes and briefly discussing the
Instruction Set. For detailed explanations and examples of
each instruction, refer to the Instruction Set Reference Section.

An addressing mode is the mechanism by which an instruction accesses its operand(s). The BCP's architecture supports five basic addressing modes: register, immediate, indexed, immediate-relative, and register-relative. The first
two allow instructions to execute the fastest because they
require no memory access beyond instruction fetch. The
remaining three addressing modes point to data or instruction memory. Typical of a RISC processor, most of the instructions only support the first three addressing modes,
with one of the operands always limited to the register addressing mode.

INSTRUCTION AND DATA MEMORY
The BCP utilizes a true Harvard Architecture, where the instruction and data memory are organized into two independent memory banks, each with their own address and data
buses. Both the Instruction Address Bus and the Instruction
Bus are 16 bits wide with the Instruction Address Bus addressing memory by words. (A word of memory is 16 bits
long; Le., 1 word = 2 by1es.) Most of the instructions are
one word long. The exceptions are two words long, containing a word of instruction followed by a word of immediate
data. The combination of word sized instructions and a word
based instruction address bus eliminates the typical instruction alignment problems faced by many CPU's.
The Data Address Bus is 16 bits wide, (with the low order 8
bits multiplexed on the Data Bus), and the Data Bus is 8 bits
wide, (Le., one byte wide). The Data Address Bus addresses
memory by bytes. Most of the BCP's instructions operate on
by1e-sized operands.
Note that although both instruction addresses and data addresses are 16 bits long, these addresses are for two different buses and, therefore, have two different numerical
meanings, (Le., byte address or word address.) Each instruction determines whether the meaning of a 16-bit address is that of an instruction word address or a data byte
address. Little confusion exists though because only the
program flow instructions interpret 16-bit addresses as instruction addresses.

Register Addressing Modes
There are two terminologies for the register addressing
modes: Register and Limited Register. Instructions that allow Register operands can access all the registers in the
CPU. Note that only 32 of the 44 CPU registers are available
at any given point in time because the lower 12 register
locations (RO-R11) access one of two switchable register
banks each. (See the "CPU Register Set" section for more
information on the CPU register banks.) Instructions that allow the Limited Register operands can access just the first
28 registers of the CPU. Again, note that only 16 of these 28
registers are available at any given point in time. Table I
shows the notations used for the Register and Limited Register operands. Some instructions also imply the use of certain registers, for example the accumulators. This is noted in
the discussions of those instructions.
Immediate Addressing Modes
The two types of the immediate addressing modes available
are: Immediate numbers and Absolute numbers. Immediate
numbers are 8 bits of data, (one data by1e), that code directly into the instruction word. Immediate numbers may represent data, data address displacements, or relative instruction addresses. Absolute numbers are 16-bit numbers. They
code into the second word of two word instructions and they
represent absolute instruction addresses. Table II shows
the notations used for both of these addressing modes.

TABLE I. Register Addressing Mode Notations
Notation

Type of Register Operand

Registers Allowed

Rs
Rd
Rsd

Source Register
Destination Register
Register is both a Source & Destination

RO-R31
RO-R31
RO-R31

rs
rd
rsd

Limited Source Register
Limited Destination Register
Limited Register is both a Source & Destination

RO-R15
RO-R15
RO-R15

TABLE II. Immediate Addressing Mode Notations
Notation

n
nn

Type of Immediate Operand

Immediate Number
Absolute Number

2-91

Size

8 Bits
16 Bits

5.0 Instruction Set Overview (Continued)
Indexed Addressing Modes
Indexed operands involve one of four possible CPU register
pairs referred to as the index registers. Figure 1 illustrates
how the index registers map into the CPU Register Set.
Note that the index registers are 16 bits wide.
Index registers allow for indirect memory addressing and
usually contain data memory addresses, although, the
LJMP instruction can use index registers to hold instruction
memory addresses. Most of the instructions that allow
memory indirect addressing, (i.e. the use of index registers),
also allow pre-incrementing, post-incrementing, or post-decrementing of the index register contents during instruction
execution, if desired. Table III lists the notations used for the
index register modes.

Immediate-Relative and Register-Relative
Address Modes
The Immediate-Relative mode adds an unsigned 8-bit immediate number to the index register IZ forming a data byte
address. The Register-Relative mode adds the unsigned
8-bit value in the current accumulator, A, to anyone of the
index registers forming a data byte address. Both of these
indirect memory addressing modes are available only on the
MOVE instruction. Table IV shows the notation used for
these two addressing modes.
INSTRUCTION SET OVERVIEW
The BCP's RISC instruction set contains seven categories
of instructions: Data Movement, Integer Arithmetic, Logic,
Shift-Rotate, Comparison, Program Flow, and Miscellaneous. Utilizing these instructions, any communications task
and almost any general computing task can be easily performed.

Index
CPU Register Pair Forming Index Register
(LSB)
Register (MSB)
IW

I

I

I

I

I

I

I

I

R13

15
IX

I

I

I

I

I

I

R15

15
IY

I

I

I

I

I

I

R17

15

IZ

I

I

I

I

R19

15

I

I

I

I

I

I
I

I

I

I

I

R12

Data Movement Instructions

0
I

I

I

I

I

I

I

The MOVE instruction is responsible for all the data transfer
operations that the BCP can perform. Moving one byte at a
time, five different types of transfer are allowed: register to
register, data memory to register, register to data memory,
instruction memory to register, and instruction memory to
data memory. Table V lists all the variations of the MOVE
instruction.

I

R14
0
I

I

I

I

I

I

I

I

R16

87
I

I

I

87
I

I

I

87
I

I

I

0
I

I

I

I

I

I

I

I

R18

87
FIGURE 1. Index Register Map

0

TABLE III. Index Register Addressing Mode Notations
Notation
[lrl
[lr-I
[lr+1
[ +Irl
[mlrl

Meaning
Index Register, Contents Not Changed
Index Register, Contents Post-Decremented
Index Register, Contents Post-Incremented
Index Register, Contents Pre-Incremented
General Notation Indicating that Any of the Above Modes Is Allowed

Note: [] denotes indirect memory addressing and is part of the instruction syntax.

TABLE IV. Relative Index Register Mode Notations
Notation

Type of Action Performed to Calculate a Data Memory Address

[lZ + nl
[lr + Al

IZ + Immediate Number (unsigned) ~ Data Memory Address
Index Register + Current Accumulator (unsigned) ~ Data Memory Address

Note: [] denotes indirect memory addressing and is part of the instruction syntax.

TABLE V. Data Movement Instructions
Syntax

Instruction Operation

Addressing Modes

MOVERs, Rd
MOVE Rs, [mlrl
MOVE [mlrl, Rd
MOVE Rs, [lr + Al
MOVE [lr + A), Rd
MOVE rs, [lZ + nl
MOVE [lZ + nl, rd
MOVE n, rd
MOVE n, [lrl

register ~ register
register ~ data memory
data memory ~ register
register ~ data memory
data memory ~ register
register ~ data memory
data memory ~ register
instruction memory ~ register
instruction memory ~ data memory

Register, Register
Register, Indexed
Indexed, Register
Register, Register-Relative
Register-Relative, Register
Limited Register, Immediate-Relative
Immediate-Relative, Limited Register
Immediate, Limited Register
Immediate, Indexed

2-92

5.0 Instruction Set Overview (Continued)
destination operand with the register as both a source and
the destination. Table VI lists the integer arithmetic instructions along with their variations.

Integer Arithmetic Instructions
The integer arithmetic instructions operate on B-bit signed
(two's complement) binary numbers. Two arithmetic functions are supported: Add and Subtract. Three versions of
the Add and Subtract instructions exist: operand ± accumulator, operand ± accumulator ± carry, and immediate operand ± operand. The first two versions support both the register and indexed addressing modes for the destination operand. These two versions also allow the specification of a
separate register or data address for the destination operand so that the sources may retain their integrity; (i.e., true
three-operand instructions). Note that the currently active
"B" register bank selects which accumulator is used in
these instructions. The third version, immediate operand ±
operand, only supports the register addressing mode for the

Logic Instructions
The logic instructions operate on B-bit binary data. A full set
of logic functions is supported by the BCP: AND, OR, eXclusive OR, and Complement. All the logic functions except
complement allow either an immediate operand or the currently active accumulator as an implied operand. Complement only allows one register operand which is both the
source and destination. The other logic instructions include
the following addreSSing modes: register, indexed, and immediate. As with the integer arithmetic instructions, the integrity of the sources may be maintained by specifying a
destination register which is different from the source. Table
VII lists all the logic instructions.

TABLE VI. Integer Arithmetic Instructions
Syntax
ADD
ADDA
ADDA
ADCA
ADCA
SUB
SUBA
SUBA
SBCA
SBCA

n, rsd
Rs, Rd
Rs, [mir]
Rs, Rd
Rs, [mir]
n, rsd
Rs, Rd
Rs, [mir]
Rs, Rd
Rs, [mir]

Instruction Operation

Addressing Modes

register + n ---+ register
Rs + accumulator ---+ Rd
Rs + accumulator ---+ data memory
Rs + accumulator + carry ---+ Rd
Rs + accumulator + carry ---+ data memory
register - n ---+ register
Rs - accumulator ---+ Rd
Rs - accumulator ---+ data memory
Rs - accumulator - carry ---+ Rd
Rs - accumulator - carry ---+ data memory

Immediate, Limited Register
Register, Register
Register, Indexed
Register, Register
Register, Indexed
Immediate, Limited Register
Register, Register
Register, Indexed
Register, Register
Register, Indexed

TABLE VII. Logic Instructions
Syntax
AND
ANDA
ANDA
OR
ORA
ORA
XOR
XORA
XORA
CPL
Note: &

n, rsd
Rs, Rd
Rs, [mir]
n, rsd
RS,Rd
Rs, [mir]
n, rsd
Rs, Rd
Rs, [mir]
Rsd

Instruction Operation

Addressing Modes

register & n ---+ register
Rs & accumulator ---+ Rd
Rs & accumulator ---+ data memory
register n ---+ register
Rs I accumulator ---+ Rd
Rs I accumulator ---+ data memory
register Ell n ---+ register
Rs Ell accumulator ---+ Rd
Rs Ell accumulator ---+ data memory
register ---+ register

Immediate, Limited Register
Register, Register
Register, Indexed
Immediate, Limited Register
Register, Register
Register, Indexed
Immediate, Limited Register
Register, Register
Register, Indexed
Register

I

~

logical AND operation
I ~ logical OR operation
GI = logical exclusive OR operation
= one's complement

r

2-93

5.0 Instruction Set Overview (Continued)
jump; and software interrupt capabilities. These instructions
redirect program flow by changing the Program Counter.

Shift and Rotate Instructions
The shift and rotate instructions operate on any of the 8-bit
CPU registers. The BCP supports shift left, shift right, and
rotate operations. Table VIII lists the shift and rotate instructions.

The unconditional jump instructions support both relative instruction addressing, the (JuMP instruction), and absolute
instruction addressing, (the Long JuMP instruction), using
the following addressing modes: Immediate, Register, Absolute, and Indexed. Table X lists the unconditional jump instructions and their variations.

Comparison Instructions
The BCP utilizes two comparison instructions. The CMP instruction performs a two's complement subtraction between
a register and immediate data. The BIT instruction tests selected bits in a register by ANDing it with immediate data.
Neither instruction stores its results, only the ALU flags are
affected. Table IX lists both of the comparison instructions.

The conditional jump instructions support both relative instruction addressing and absolute instruction addressing using the Immediate and Absolute addressing modes. The
conditional relative jump instruction tests flags in the Condition Code Register, {CCR J. and the Transceiver Status
Register, (TSR). Two possible syntaxes are supported for
the conditional relative jump instruction; see Table XI.

Program Flow Instructions
The BCP has a wide array of program flow instructions: unconditional jumps, calls and returns; conditional jumps,
calls, and returns; relative or absolute instruction addressing
on jumps and calls; a specialized register field decoding

Table XII lists the various flags "f" that the conditional JMP
instruction can test and Table XII I lists the various conditions "cc" that the Jcc instruction can test for. Keep in

TABLE VIII. Shift and Rotate Instructions
I nstruction Operation

Syntax
SHL

SHR

Register

Rsd,b

Rsd,b

~

i

o~

i

i

i

i

i

i

i

i

4

Rsd,b

i

i

i

III

~o

Rod

i

i

i
Rod

ROT

Addressing Mode

i

i

i

i

• ~
i

i
III

Rod

~

Register

Register

Note: "b" = the number of bit shifts/rotates to perform.

TABLE IX. Comparison Instructions
Syntax
CMP
BIT

rs, n
rs, n

Instruction Operation
register - n
register & n

Addressing Mode
Limited Register
Limited Register

Note: & = logical AND operation

TABLE X. Unconditional Jump Instructions
Syntax
JMP
JMP
LJMP
LJMP

n
Rs
nn
[lrl

Instruction Operation

Operand Range

PC + n (sign extended) ~ PC
PC + Rs (sign extended) ~ PC

-128, +127
-128, +127

O,64k
O,64k

nn~PC
Ir~PC

Note: PC = Program Counter; contents initially points to instruction following jump.

2-94

Addressing Mode
Immediate
Register
Absolute
Indexed

5.0 Instruction Set Overview (Continued)
mind that the Jcc instruction is just an optional syntax for
the conditional JMP instruction.

On the other hand, the conditional absolute jump instruction, LJMP, can test any bit in any currently active CPU register. Table XIV shows the conditional long jump instruction
syntax.

The example in Figure 2 demonstrates two possible ways to
code the conditional relative jump instruction when testing
for a false [Z] flag in (CCR l. In the example, assume that
the symbol "z" equals "000" binary, that the symbol "NS"
equals "0" binary, and that the symbol "SKIP. IT" pOints to
the desired instruction with which to begin execution if [Z] is
false.

JMP

Z,NS,SKIP.IT

;If [Z]=O goto SKIP. IT

-or-

JNZ

SKIP.IT
;If [Z]=O goto SKIP.IT
FIGURE 2. Coding Examples of Equivalent
Conditional Jump Instructions

TABLE XI. Conditional Relative Jump Instruction
Syntax

Instruction Operation

Operand Range

Addressing Mode

JMP f,s,n

If the flag "f" is in the state "s"
then PC + n (sign extended) --+ PC
If the condition "cc" is met
then PC + n (sign extended) --+ PC

-128, +127

Immediate

-128, +127

Immediate

Jcc n
Note: PC

=

Program Counter; contents initially pOints to instruction following jump.

TABLE XII. "f" Flags
"f"(Binary) Flag

000
001
010
011
100
101
110
111

Z
C
V
N
RA
RE
DAV
TFF

Flag Name

Register
Containing Flag

Zero
Carry
Overflow
Negative
Receiver Active
Receiver Error
Data Available
Transmitter FIFO Full

(CCRl
(CCRl
(CCRl
(CCRl
(TSRl
(TSRl
(TSRl
(TSRl

TABLE XIII. "cc" Conditions Tested
"cc" Field
Z
NZ
EO
NEO
C
NC
V
NV
N
P
RA
NRA
RE
NRE
DA
NDA
TFF
NTFF

Condition Tested for
Zero
Not Zero
Equal
Not Equal
Carry
No Carry
Overflow
No Overflow
Negative
Positive
Receiver Active
Not Receiver Active
Receiver Error
No Receiver Error
Data Available
No Data Available
Transmitter FIFO FULL
Transmitter FIFO Not Full

Flag "f"'s Condition
[Z]
[Z]
[Z]
[Z]
[C]
[C]
[V]
[V]
[N]
[N]
[RA]
[RA]
[RE]
[RE]
[DAV]
[DAV]
[TFF]
[TFF]

= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0

TABLE XIV. Conditional Absolute Jump Instruction
Syntax
LJMP

Rs,p,s,nn

Instruction Operation

Operand Range

Addressing Mode

If the bit of register "Rs" in
position "p" is in the state "s"
then nn --+ PC

O,64k

Register, Absolute

Note: PC = Program Counter

2-95

5.0 Instruction Set Overview (Continued)
protocol which is located in the Receive/Transmit Register,
{RTR[4-2]I.

The BCP also has a specialized relative jump instruction
called relative Jump with Rotate and Mask on source register, JRMK. This instruction facilitates the decoding of register fields often involved in communications processing.
JRMK does this by rotating and masking a copy of its register operand to form a signed program counter displacement
which usually pOints into a jump table. Table XV shows the
syntax and operation of the JRMK instruction.

The BCP has two unconditional call instructions; CALL,
which supports relative instruction addressing and LCALL,
(Long CALL), which supports absolute instruction addressing. These instructions push the following information onto
the CPU's internal Address Stack: the address of the next
instruction; the status of the Global Interrupt Enable flag,
[GIE]; the status of the ALU flags [Z], [C], [N], and [V]; and
the status of which register banks are currently active. Table
XVI lists the two unconditional call instructions. Note that
the Address Stack is only twelve positions deep; therefore,
the BCP allows twelve levels of nested subroutine invocations, (this includes both interrupts and calls).

JRMK's masking, (setting to zero), the least significant bit of
the displacement allows the construction of a jump table
using either one or two word instructions; for instance, a
table of JMP and/or LJMP instructions, respectively. The
example in Figure 3 demonstrates the JRMK instruction decoding the address frame of the 3299 Terminal Multiplexer

TABLE XV. JRMK Instruction
Syntax
JRMK

Rs, b,

Note: PC

=

Displacement
Range

Instruction Operation

m

(a) Rotate a copy of register "Rs" "b" bits to the right.
(b) Mask the most significant "m" bits and the least
significant bit of the above result.
(c) PC + resulting displacement (sign extended) PC.

-128,

Addressing Mode

+ 126

Register

Program Counter, contents initially points to instruction following jump.

Example Code
JRMK

RTR, 1, 4

;decode terminal address

LJMP

ADDR.O

LJMP

ADDR.l

;jump to device handler #0
;jump to device handler #1

LJMP

ADDR.7

;jump to device handler #7

Instruction Execution
JRMK Displacement Register
Copy {RTR l into JRMK's displacement register:
x
x
x
A2
A1
Rotate displacement register 1 bit to the right:
y
x
x
x
A2
AND result with "00001110" binary mask:
o
0
0
A2
Sign extended resulting displacement and add
it to the program counter, (PC).
If the bits A2 A 1 AO equal "0 0 1 " binary then
+ 2 is added to the Program Counter;
o
o
(Le., PC + 2 PC).
Execute the instruction pointed to by the PC,
which in this example is:
LJMP ADDR.1
FIGURE 3. JRMK Instruction Example

(a)
(b)
(c)
(d)

o

o

(e)

o

Contents
AO
Y
A1
AO
A1
AO

o

o

y
y

o

o

TABLE XVI. Unconditional Call Instructions
Syntax
CALL

n

LCALL

nn

Operand
Range

Instruction Operation
PC & [GIE] &ALU flags & reg. bank selection PC + n (sign extended) PC
PC & [GIE] & ALU flags & reg. bank selection nn -

PC

Note: PC = Program Counter; contents initially points to instruction following call.
[GIE] ~ Global Interrupt Enable bit.
& = concatenation operator, combines operands together forming one long operand.

2-96

Address Stack
Address Stack

-128,

+ 127

0,64k

Addressing Mode
Immediate
Absolute

5.0 Instruction Set Overview (Continued)
The BCP has one conditional call instruction capable of
testing any bit in any currently active CPU register. This call
only supports absolute instruction addressing. Table XVII
shows the conditional call instruction syntax and operation.
The return instruction complemetns the above call instructions. Two versions of the return instruction exist, the uncondtional return and the conditional return. When the unconditional return instruction is executed, it pops the last
address on the CPU's Address Stack into the program
counter and it can optionally affect the [GIE) bit, the ALU

flags, and the register bank selection. Table XVIII shows the
syntax and operation of the unconditional return instruction.
The conditional return instruction functions the same as the
unconditional return instruction if a desired condition is met.
As with the conditional jump instruction, the conditional return instruction has two possible syntaxes. Table XIX lists
the syntax for the conditional return. The "f" flags and the
"cc" conditions for the return instruction are the same as
for the conditional jump instruction, therefore refer to Table
XII and Table XIII for the listing of "'" and "cc", respectively.

TABLE XVII. Conditional Call Instruction
Syntax
LCALL

Rs, p, s, nn

Instruction Operation

Operand Range

Addressing Mode

If the bit of register "Rs" in position
"p" is in the state "s" then
PC & [GIE) & ALU flags &
reg. bank selection -+ Address Stack
nn -+ RC
End if

0,64k

Register, Absolute

Note: PC = Program Counter; contents inHially points to instruction following call.
[GIEI = Global Interrupt Enable bit
& = concatenation operator, combines operands together forming one long operand.

TABLE XVIII. Unconditional Return Instruction
Syntax
RET

(g (, rfll

Instruction Operation
Case "g" of
0: leave [GIE) unaffected, (default)
1: restore [GIE) from Address Stack
2: set [GIE)
3: clear [GIE)
End case
If "rf" = 1 then
restore ALU flags from Address Stack
restore register bank selection from Address Stack
Else (the default)
leave the ALU flags and register bank selections unchanged
End if
Address Stack -+ PC

Note: PC = Program Counter
[GIEI = Global Enable bit
II = surrounds optional operands; not part of the instruction syntax.
Optional operands may either be specified or omitted.

TABLE XIX. Conditional Return Instruction
Syntax
RETF
Rcc
Note:

f, s (, (gl, (, rfll
(g (,rfll

Instruction Operand
lithe flag "'" is in the state "s" then perform a RET (g (, rf) )
If the condition "cc" is met then perform a RET (g (,rf) )

See Table XVIII for an explanation of "RET (g (, rfll"
(I = SUrrounds optional operands; not part of the instruction syntax.
Optional operands may either be specHied or omitted.

2-97

5.0 Instruction Set Overview (Continued)
In addition to the above jump, call and return program flow
instructions, the BCP is capable of generating software interrupts via the TRAP instruction. This instruction generates
a call to anyone of 64 possible interrupt table addresses
based on its vector number operand. This allows both the
simulation of hardware interrupts and the construction of
special software interrupts, if desired. The actual interrupt
table entry address is determined by concatenating the Interrupt Base Register, {lBR l, to an 8-bit representation of
the vector number operand in the TRAP instruction. This
instruction may also clear the [GIE] bit, if desired. Table XX
shows the syntax and operation of the TRAP instruction.

Miscellaneous Instructions
As stated in the "CPU Register Set" section, the BCP has
44 registers with 24 of them arranged into four register
banks: Main Bank A, Alternate Bank A, Main Bank B, and
Alternate Bank B. The exchange instruction, EXX, selects
which register banks are currently available to the CPU, for
example either Main Bank A or Alternate Bank A. The deselected register banks retain their current values. The EXX
instruction can also alter the state of [GIEI. if desired. Table
XXI shows the EXX instruction syntax and operation.

TABLE XX. TRAP Instruction
Syntax
TRAP v (, g'l

Instruction Operation

Ii

i i i i i i
{IBRl

~

[GIE]
IBR

~

7

Program Counter; contents
~

Ii

10 i 0

15

Note: PC

Operand Range

PC & [GIE] & ALU flags &
reg. Bank selection _ Address Stack
If "g'" = 1 then clear [GIE]
Form PC address as shown below:

in~ially

0,63

i i i i

~PC

v

5

0

pOints to instruction following call.

Global Interrupt Enable bit

Interrupt Base Register

& = concatenation operator, combines operands together forming one long operand.

I I ~ surrounds optional operands; not part of the instruction syntax.
Optional operands may either be specified or omitted.

TABLE XXI. EXX Instruction
Syntax

Instruction Operation

EXX ba, bb (, gl

Case "ba" of
0: activate Main Bank A
1: activate Alternate Bank A
End case
Case "bb" of
0: activate Main Bank B
1: activate Alternate Bank B
End case
Case "g" of
0: leave [GIE] unaffected, (default)
1: (reserved)
2: set [GIE]
3: clear [GIE]
End case

Note: [GIE]

II

~

~

Global Interrupt Enable bit

surrounds optional operands; not part of the instruction syntax.

Optional operands may either be specified or omitted.

2-98

6.0 Instruction Set Reference
INTRODUCTION

Instruction Format

The Instruction Set Reference section contains detailed information on the syntax and operation of each BCP instruction. The instructions are arranged in alphabetical order by
mnemonic for easy access. Although this section is primarily
intended as a reference for the assembly language programmer, previous assembly language experience is not a
prerequisite. The intent of this instruction set reference is to
include all the pertinent information regarding each instruction on the pagels) describing that instruction. The only exceptions to this rule concerns the instruction addressing
modes and the bus timing diagrams. The discussion of the
instruction addressing modes occurs at the beginning of the
BCP Instruction Set Overview section and, therefore, will
not be repeated here. The figures for the bus timing diagrams are located at the end of this introduction rather than
constantly repeating them under each instruction. On the
other hand, the information that is contained under each
instruction is divided into eight categories titled: Syntax, Affected Flags, Description, Example, Instruction Format,
T-states, Bus Timing, and Operation. The following paragraphs explain what information each category conveys and
any special nomenclature that a category may use.
Syntax

This category illustrates the formation of an instruction's
machine code for each operand variation. Assembly or disassembly of any instruction can be accomplished using
these figures.
T-states

The T -state category lists the number of CPU clock cycles
required for each instruction, including operand variations
and conditional considerations. Using this information, actual execution times may be calculated. For example, if the
conditional relative jump instruction's condition is not met,
the CPU's clock cycle is 18.867 MHz ([CCS] = 0), and no
instruction wait states are requested ([IW1-0] =00), then
Jcc's execution time is calculated as shown below:
texecution

~ 1/(CPU clock frequency) • T-states

= 1/(18.867*106 Hz) * 2
= (53*10- 9s) * 2
=

106 ns

See the section BCP Timing for more information on calculating instruction execution times.
Bus Timing
This category refers the user to the Bus Timing Figures 7 to
12 on the following pages. These figures illustrate the relationship between software instruction execution and some
of the BCP's hardware signals.

This category illustrates the assembler syntax for each instruction. Multiple lines are used when a given instruction
supports more than one type of addressing mode or if it has
an optional mnemonic. All capital letters, commas, (,) math
symbols (+, -), and brackets ([ I) are entered into the assembler exactly as shown. Braces ({ )) surround an instruction's optional operands and their associated syntax. The
text between the braces may either be entered in with or
omitted from the instruction. The braces themselves should
not be entered into the assembler because they are not part
of the assembler syntax. Lower case characters and operands that begin with the capital R represent symbols. These
must be replaced with actual register names, numbers, or
equated registers and numbers. Table XXII lists all the symbols and their associated meanings.

Operation

The operation category illustrates each instruction's operation in a symbolic coding format. Most of the operand
names used in this format come directly from each instruction's syntax. The exceptions to this rule deal with implied
operands. Instructions that imply the use of the accumulators use the name "accumulator" as an operand. Instructions that manipulate the Program Counter use the symbol
"PC". Instructions that "push" onto or "pop" off of the internal Address Stack specify "Address Stack" as an operand.
Instructions that save or restore the ALU flags and the register bank selections use those terms as operands. Two
specialized operator symbols are used in the symbolic coding format, the arrow" -- " and the concatenation operator
"&". The arrow indicates the movement of data from one
operand to another. For instance, after the operation
"Rs -- Rd" is performed the content of Rd has been replaced with the content of Rs. The concatenation operator
"&" simply indicates that the operands surrounding an "&"
are attached together forming one new operand. For example, "PC & [GIE] 7 ALU flags & register bank
selections -- Address Stack" means that the Program
Counter, the Global Interrupt Enable bit, the ALU flags and
the register bank selections are combined into one operand
and pushed onto the internal Address Stack. Three conditional structures are utilized in the symbolic coding format:
the "Two Line If" structure, the "Blocked If" structure, and
the "Blocked Case" structure. Figure 4 shows the "Two
Line If" structure. If the condition is met then the operation
is performed, otherwise the operation is not performed.

Affected Flags

If an instruction sets or clears any of the ALU flags, (Le.,
Negative [Nl, Zero [Zl, Carry [Cl, and/or Overflow [Vl, then
those flags affected are listed under this category.
Description
The Description category contains a verbal discussion
about the operation of an instruction, the operands it allows,
and any notes highlighting special considerations the prorammer should keep in mind when using the instruction.
Example
Each instruction has one or more coding examples designed to show its typical usage(s). For clarity, register
name abbreviations are often used instead of the register
numbers, (Le., RTR is used in place of R4). Each example
assumes that the ".EQU" assembler directive has been previously executed to establish these relationships. Information relating register abbreviations to register names, numbers, and purpose is located in the CPU Registers section.

If condition
then operation
FIGURE 4. Two Line If Structure

2-99

6.0 Instruction Set Reference (Continued)
Figure 5 illustrates the "Blocked If" structure.

In the "Blocked Case" structure, the operation preceded by
the equivalent numeric value of the operand is executed.
For example, if the operand's value is equal to "1" then the
operation preceded by "1:" is executed.
One final note, two reference tables have been added to the
back of the Instruction Set Reference section. The first table, Table XXIII, lists all the instructions with their associated
T-states, Affected Flags, and Bus Timing figure numbers in
a compact format. The second table, Table XXIV, lists all
the instructions in opcode order to facilitate disassembly.

If condition then
operation
operation
etc ...
End if
FIGURE 5. Blocked If Structure
In the "Blocked If" structure, if the condition is met then all
the operations between the "If" statement and the "End if"
statement are performed. Figure 6 illustrates the "Blocked
Case" structure.
Case operand of
0: operation
1: operation
2: etc ...
End case
FIGURE 6. Blocked Case Structure

TABLE XXII. Notational Conventions for Instruction Set
Symbol

Represents

n

Ot0255
+ 127 to - 128

Meaning

Length

Unsigned Number
Signed Number

8 Bits
16 Bits

nn

Ot065535

Unsigned Number

Rs

RO-R31

Source Register

Rd

RO-R31

Destination Register

Rsd

RO-R31

Combination Source/Destination Register

rs

RO-R15

Limited Source Register

rd

RO-R15

Limited Destination Register

rsd

RO-R15

Limited Combination Source/Destination Register

Ir

IW,IX,IY,IZ

Index Register

Ir Ir
Ir +
+Ir

Index Register in One of the Following Address Modes:
Post Decrement
No Change
Post Increment
Pre-Increment

b

0-7

Shift Field

3 Bits

mlr

m

0-7

Mask Field

3 Bits

p

0-7

Position Field

3 Bits

s

0-1

State Field

1 Bit

f

0-7

Flag Reference Field

3 Bits

v

0-63

Vector Field

6 Bits

g

0-3

Global Interrupt Enable Flag [GIE] Status Control

2 Bits

g'

0-1

Global Interrupt Enable Flag [GIE] Limited Status Control

1 Bit

rf

0-1

Register Bank and ALU Flag Status Control

1 Bit

ba

0-1

Register Bank A Select

1 Bit

bb

0-1

Register Bank B Select

1 Bit

Condition Code Instruction Extensions

cc

2-100

6.0 Instruction Set Reference

(Continued)

i----INSTRUCTION ------I

ClK-OUT

IClK

x:
x:

XIIIIIIX

10-115

b'acC(I)=l

X

IAO-IA1S

TLiF/9336-21

FIGURE 7. Instruction-Memory Bus Timing for 2 T-state Instructions
(No Instruction Wait States [lW1-0] = 00, CPU Running at Full Speed ICCS]

=

0)

i-------INSTRUCTION - - - - - . j

T,

Tx

T2

ClK-OUT

IClK

10-115 _ _ _ _)fIIIIIIIIIIIIX_~-x:

I

IAO-IA1S

btaCC(I)=l

..JX?IIIIX....~_____X:

~_ _

I

TLIF/9336-22

FIGURE 8. Instruction-Memory Bus Timing for 3 T-state Instructions
(No Instruction Wait States [lW1-0] = 00, CPU Running at Full Speed ICCS]

2-101

= 0)

6.0 Instruction Set Reference

(Continued)

i--------INSTRUCTION-------.J

eLK-OUT

leLK

XZZZZVZX'-__~ZVZX'---. . .~

10-115 _ _ _ _

lAo-lA15

f±taCC(,)~8;CC(')~

X

----~X

>C
TL/F/9336-23

FIGURE 9. Instruction-Memory Bus Timing for (2 + 2) T-state Instructions
(No Instruction Walt States [lW1-0) = 00, CPU Running at Full Speed ICCS) = 0)

t--------INSTRUCTION-------.J

eLK-OUT

leLK

>eZZZZZZZZZZZZZZZZZZZX. . . _ _>eL
I
I
t:±taCC(I)~
>eZZZZZZZZZZZZX'_______>C

10-115 _ _ _ _

IAo-lA15 _ _ _ _

I

I

FIGURE 10. Instruction-Memory Bus Timing for 4 T-state Instructions
(No Instruction Wait States [lW1-0) = 00, CPU Running at Full Speed ICCS) = 0)

2-102

TUF/9336-24

6.0 Instruction Set Reference

(Continued)

I------INSTRUCTION----~

TX

T2

Tl

ClK-OUT

IClK

10-115 --:-_-.JX?///////////X,--:-_>G
I· : tacc(!) : .1
IAO-IAI5 -~--""X\"-:-___~____-:-____
ALE ___~_..JI

ADO-AD7
A8-A15

\~~----~-----

//////////~//////X~_D_AT_A_>G
1

t~cc(l)===4

1 I'

1

>eZZ)('--_--:____~--.....;.I.....(

I

WR --:-------'

I ,'-_--+...J1,--TLlF/9336-2S

FIGURE 11. Instruction/Data Memory Bus Timing for Data Memory Read
(No Instruction or Data Memory Wait States, CPU Running at Full Speed [CCS] = 0)
1------INSTRUCTlON----~

Tx

T2

elK-OUT

lelK

--JX?///////////X~~--_>C

10-115 _ _

I·:

IAO-IAI5 ----"'X
ALE

ADO-AD7

tacc(l):

.1

>C

\~r----+---

-+_...J/

/////////~
1

1

I

I

DATA

>G

A8-A15 /////////IX'-_ _ _ _ _ _>G

I''---I-'r-

TLlF/9336-26

FIGURE 12. Instruction/Data Memory Bus Timing for Data Memory Write
(No Instruction or Data Memory Wait States, CPU Running at Full Speed [CCS] = 0)

2-103

~
~

,--------------------------------------------------------------------,

~
CO)

6.0 Instruction Set Reference

~

ADCA

c

(Continued)

Add with Carry and Accumulator

ADD

Syntax

Syntax
ADD n, rsd
-immediate, limited register
Affected Flags
N,Z,C,V
Description
Adds the immediate value n to the register rsd and places
the result back into the register rsd. Note that only the active registers RO-R15 may be specified for rsd. The value of
n is limited to 8 bits; (unsigned range:
to 255, signed
range: + 127 to -128).
Example
Add the constant - 3 to register 10.
ADD
-3, Rl0
;Rl0 + (-3) -- Rl0
Instruction Format

ADCA Rs, Rd
-register, register
ADCA Rs, [mlr]
-register, indexed
Affected Flags
N,Z,C, V
Description
Adds the source register Rs, the active accumulator, and
the carry flag together, placing the result into the destination
specified. The destination may be either a register, Rd, or
data memory via an index register mode, [mlrJ. Note that
register bank selection determines which accumulator is active.
Example
Add the constant 109 to the index register IW, (which is 16
bits wide).
SUBA A, A
;Clear the accumulator
ADD
109, R12
;Add 109 to low byte of IW
ADCA R13, R13
;Add carry to high byte of IW
Instruction Format
ADCA Rs, Rd
Rd
15

I

9

15
00
01
10
11

-

I II I

.m.lr.
8
6
4

post-decrement
no change
post Increment
pre-Increment

1. °10101°1
Opcode .
15
11
T-States
2
Bus Timing
Figure 7
Operation
rsd + n -- rsd

°

ADCA Rs, [mlr]
1 10 11 10 I 0 I 0 11
1
_
Opcode

°

Rs

4

I I
Rs

o

•

00 - IW
01 - IX
10 - IY

11 - IZ

TL/F/9336-5

T-states
ADCA Rs, Rd
ADCA Rs, [mlrJ
Bus Timing
ADCA Rs, Rd
ADCA Rs, [mlrJ
Operation
ADCA Rs, Rd
Rs + accumulator
ADCA Rs, [mlrJ
Rs + accumulator

-2
-2
-Figure 7
-Figure 12

+

carry bit -- Rd

+

carry bit -- data memory

Add Immediate

2-104

n

rsd

3

°

r----------------------------------------------------------------------.c

"a

6.0 Instruction Set Reference (Continued)

CD

ADDA Add with Accumulator

AND And Immediate

Syntax

Syntax

ADDA Rs, Rd
ADDA Rs, [mlrJ

-register, register
-register, indexed

AND

n, rsd

Co)
~

~

-immediate, limited register

Affected Flags

Affected Flags

N,Z

N,Z,C,V

Description

Description

Logically ANDs the immediate value n to the register rsd
and places the result back into the register rsd. Note that
only the active registers RO-R15 may be specified for rsd.
The value of n is 8 bits wide.

Adds the source register Rs to the active accumulator and
places the result into the destination specified. The destination may be either a register, Rd, or data memory via an
index register mode, [mlrJ. Note that register bank selection
determines which accumulator is active.

Example
Unmask both the Transmitter and Receiver interrupts via
the Interrupt Control Register {lCR l. R2. Leave the other
interrupts unaffected.
EXX 0,0
;select main register banks
AND 11111100B,R2 ;unmask transmitter and
; receiver interrupts

Example
In the first example, the value 4 is placed into the currently
active accumulator, that accumulator is added to the contents of register 20, and then the result is placed into register 21.
MOVE 4, A
;Place constant into accum
ADDA R20, R21
;R20 + accum - R21
In the second example, the alternate accumulator of register bank B is selected and then added to register 20. The
result is placed into the data memory pOinted to by the index
register IZ and then the value of IZ is incremented by one.
EXX
0, 1
;Select alt accumulator
ADDA R20, liZ +] ;R20 + accum - data mem
;and increment data pOinter

Instruction Format
10 11 1 0 1 0 1
Opcode

Instruction Format

rsd

15

rsd

3

0

T-states
2
Bus Timing
Figure 7
Operation

ADDA Rs, Rd

AND

n-

rsd

1 1

1 1
Rd

1111111010101
Opcode

n
11

15

Rs

o

4

9

ADDA Rs, [mlr]

I I
Rs

15

8

~

00
01
10
11

-

6

post-decrement
no change
post Increment
pre-Increment

o

4

~

OO-IW
01 - IX
10 - IY
11 - IZ
TUF/9336-6

T-states
ADDA Rs, Rd
ADDA Rs, [mlr]

•

-2
-3

Bus Timing
ADDA Rs, Rd
ADDA Rs, [mlr]

-Figure 7
-Figure 12

Operation
ADDA Rs, Rd
Rs + accumulator ADDA Rs, [mlrJ
Rs + accumulator -

Rd
data memory

2-105

6.0 Instruction Set Reference

(Continued)

ANDA And with Accumulator

BIT Bit Test

Syntax
ANDA Rs, Rd
-register, register
ANDA Rs, [mlr)
-register, indexed
Affected Flags
N,Z
Description
Logically ANDs the source register Rs to the active accumulator and places the result into the destination specified.
The destination may be either a register, Rd, or data memory via an index register mode, [mlr]. Note that register bank
selection determines which accumulator is active.
Example
This example demonstrates a way to quickly unload all 11
bits of the Receiver FIFO when the FIFO is full. The example assumes that the index register IZ points to the location
in data memory where the information should be stored.
EXX
1,1
;select alternate banks
MOVE 00000111B, A ;place the {TSR} mask
; into the accumulator
Pop the first word from the receiver FIFO
ANDA TSR, [IZ+]
;read bits 8, 9, & 10
MOVE RTR, [IZ + ]
;pop bits 0-7
Pop the second word from the receiver FIFO
ANDA TSR, liZ + ]
MOVE RTR, liZ + ]
Pop the third word from the receiver FIFO
ANDA TSR, liZ + ]
MOVE RTR, liZ + ]
Instruction Format
ANDA Rs, Rd

Syntax
BIT rs, n
-limited register, immediate
Affected Flags
N,Z
Description
Performs a bit level test by logically ANDing the source register rs to the immediate value n. The affected flags are
updated, but the result is not saved. Note that only the active registers RO-R15 may be specified for rs. The value n
is 8 bits wide.
Example
Poll the Transmitter FIFO Empty flag [TFE] in the Network
Command Flag register {NCF}, R1, waiting for the Transmitter to send the current FIFO data.
EXX 0,1
;select main A, alt B
Poll:
BIT 10000000B,NCF ;AII data sent yet?
JZ
Poll
; No, poll TFE
; Yes, send next byte(s)
Instruction Format

n
15
T-states
2
Bus Timing
Figure 7
Operation
rs AND n

I
Rd
15
ANDA

Rs

RS,[mlr]

1 1 1
1_ 11011101110101
Opcode
.m.lr.
15

o

4

9

8

6

1 1Rs 1

4

00 - post-decrement
01 - no change
10 - post Increment
11 - pre-increment

1

_
0

l

OO-IW
01 - IX
10 - IY
11 - IZ
TL/F/9336-7

T-states
ANDA Rs, Rd
-2
ANDA Rs, [mlr)
-3
Bus Timing
ANDA Rs, Rd
-Figure 7
ANDA Rs, [mlr]
-Figure 12
Operation
ANDA Rs, Rd
Rs AND accumulator - Rd
ANDA Rs, [mlr)
Rs AND accumulator - data memory

2-106

11

rs

3

0

r----------------------------------------------------------------------,c
6.0 Instruction Set Reference

"a

~

(Continued)

....

CALL Unconditional Relative Can

CMP Compare

Syntax
-immediate
CALL n
Affected Flags
None
Description
Pushes the Program Counter, the ALU flags, the Global Interrupt Enable bit [GIEl. and the current register bank selections onto the internal Address Stack; then unconditionally
transfers control to the instruction at the memory address
calculated by adding the contents of the Program Counter
to the immediate value n, (sign extended to 16 bits). Since
the immediate value n is an 8-bit two's complement displacement, the unconditional relative call's range is from
+ 127 to -128 relative to the Program Counter. Note that
the Program Counter initially contains the memory address
of the next instruction following the call.
Example
Transfer control to the subroutine "Send.it". Note that
"Send.it" must be within + 127/-128 words relative to the
PC.
CALL
Send.it
Instruction Format

Syntax
CMP rs, n
-limited register, immediate
Affected Flags
N,Z,C,V
Description
Compares the immediate value n with the source register rs
by subtracting n from rs. The affected flags are updated, but
the result is not saved. Note that only the active registers
RO-R15 may be specified for rs. The value of n is limited to
8 bits; (unsigned range: 0 to 255, signed range: + 127 to
-128).
Example
Compare the data byte in register 11 to the ASCII character

"A

•

R11.IIA"

;If:

IN

Less-thanJ
Equal_to.....A

,

JEQ

data<"A"
data = "A"
;Else data> "A"

Instruction Format

n
15
T-states

n
15
7
T-states
3
Bus Timing
Figure 8
Operation
PC & [GIE] & ALU flags & register bank selections
- Address Stack
PC + n(sign extended) - PC

U

CMP

2

o

Bus Timing
Figure 7

Operation
rs - n

2-107

11

rs

3

0

:t

6.0 Instruction Set Reference
CPL

(Continued)

Complement

EXX

Syntax
CPL

Exchange Register Banks

Syntax

Rsd

-register

EXX

ba, bb (,g)

Affected Flags

Affected Flags

N,Z

None

Description

Description

Logically complements the contents of the register Rsd,
placing the result back into that register.

Selects which CPU register banks are active by exchanging
between the main and alternate register sets for each bank.
Bank A controls RO-R3 and Bank B controls R4-R11. The
table below shows the four possible register bank configurations. Note that deactivated registers retain their current values. The Global Interrupt Enable bit [GIE] can be set or
cleared, if desired.

Example
Load the fill-bit count passed from the host into the Transmitter's Fill-Bit Register {FBRl. R3, and then perform the
required one's complement of the fill-bit count. In this example, register 20 contains the fill-bit count.
EXX
MOVE
CPL

1,1
R20, FBR
FBR

Register Bank Configurations

;select alternate banks
;Ioad {FBR)
;complement fill-bit count

I nstruction Format

11

I 0 I 1 I 0 I b~~o~; I 0 I 0 I 0 I 0 I

15

Rsd

4

o

ba

bb

Active Register Banks

0
0
1
1

0
1
0
1

Main A, Main B
Main A, Alternate B
Alternate A, Main B
Alternate A, Alternate B

T-states

Example

2

Activate the main register set of Bank A, the alternate register set of Bank B, and leave the Global Interrupt Enable bit
[GIE] unchanged.

Bus Timing
Figure 7

EXX

Operation

0,1

;select main A, alt B reg banks

Instruction Format

Rsd -+ Rsd

15

6 -l-

4

3

2

OO-GIE not affected
01-reserved
10-SetGIE
11-Clear GIE

T-states
2
Bus Timing
Figure 7
Operation
Case ba of
0: activate main Bank A
1: activate alternate Bank A
End case
Case bb of
0: activate main Bank B
1: activate alternate Bank B
End case
Case g of
0: leave [GIE] unaffected, (default)
1: (reserved)
2: set [GIE]
3: clear [GIE]
End case

2-108

o

6.0 Instruction Set Reference
JMP

(Continued)

Conditional Relative Jump

Instruction Format

I I

Jcc
Syntax
JMP f, s, n
Jcc n

-immediate
-immediate (optional syntax)

10

2 if condition is not met
3 if condition is met

Conditionally transfers control to the instruction at the memory address calculated by adding the contents of the Program Counter to the immediate value n, (sign extended to
16 bits), if the state of the flag referenced by f is equal to the
state of the bit s; or, optionally, if the condition cc is met.
See the tables below for the flags that f can reference and
the conditions that cc may specify. Since the immediate value n is an 8-bit two's complement displacement, the conditional relative jump's range is from + 127 to -128 relative
to the Program Counter. Note that the Program Counter initially contains the memory address of the next instruction
following the jump.

Figure 7 il condition is not met
Figure 8 if condition is met

Bus Timing

Operation
JMP I, s, n
II flag I is in state s
then PC + n(sign extended) -+ PC
Jcc n
II cc condition is true
then PC + n(sign extended) -+ PC
Flag Reference Table for "f"

Example
This example demonstrates both syntaxes of the conditional relative jump instruction testing for a non-zero result from
a previous instruction; (Le., [Z] = 0). If the condition is
met then control transfers to the instruction labeled
"Loop. back"; else the next instruction following the jump is
executed.
JMP

OOOS,O,Loop.back

; Jump on not zero

JNZ

Loop.back

; Jump on not zero

Meaning

Zero
Not Zero
Equal
EO
NEQ Not Equal
C
Carry
NC
No Carry
V
Overflow
NV
No Overflow
N
Negative
P
Positive
Receiver Active
RA
NRA Not Receiver Active
RE
Receiver Error
NRE
No Receiver Error
DA
Data Available
NDA No Data Available
TFF
Transmitter FIFO Full
NTFF Transmitter FIFO Not Full

f

(binary)

0
1
2

(000)
(001)
(010)
(011)
(100)
(101)
(110)
(111)

3
4
5
6'
7

Flag Reference
[Z]
[C]
[V]
[N]
[RA]
[RE]
[DAV]
[TFF]

in (CCR)
in (CCR)
in (CCR)
in (CCR)
in (TSR)
in (TSR)
in (TSR)
in (TSR)

Note: The value of f for [DAV] differs from the numeric
value for the position of [DAV] in ITSRi.

Condition Specification Table for "cc"

Z
NZ

o

7

T-states

Affected Flags
None
Description

cc

n

f

11

15

Condition Tested for
[Z]
[Z]
[Z]
[Z]
[C]
[C]
[V]
[V]
[N]
[N]
[RA]
[RA]
[RE]
[RE]
[DAV]
[DAV]
[TFF]
[TFF]

= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0

•
2-109

~

C')
CO

a..
C

6.0 Instruction Set Reference
JMP

(Continued)

Unconditional Relative Jump

Syntax
JMP n
-immediate
JMP Rs
-register
Affected Flags
None
Description
Unconditionally transfers control to the instruction at the
memory address calculated by adding the contents of the
Program Counter to either the immediate value n or the contents of the source register Rs, (both sign extended to 16
bits). Since the immediate value n and the contents of Rs
are 8-bit two's complement displacements, the unconditional relative jump's range is from + 127 to -128 relative to
the Program Counter. Note that the Program Counter initially contains the memory address of the nexl instruction following the jump.
Example
Transfer control to the instruction labeled "lniLXmit",
which is within + 127/ - 128 words relative to the PC.
JMP IniLXmit
; go initialize Transmitter
Instruction Format
JMP n
.1

1 11 1 0 1 0 11 1 0 11 1
Opcode
15

JMP

n

o

7

Rs

1111010111110111110101
1
.
Opcode
.
15
4
T-states
JMP n
-3
JMP Rs
-4
Bus Timing
JMP n
-Figure 8
JMP Rs
-Figure 10
Operation
JMP n
PC + n(sign extended) ---+ PC
JMP Rs
PC + Rs(sign extended) ---+ PC

Rs

o

2-110

6.0 Instruction Set Reference (Continued)
JRMK

Rotate the register b bits to the right:

Relative Jump with Rotate and Mask on
Register

Syntax
JRMK Rs, b, m

~L===:::;:;::~~

-Register

register

Affected Flags
None

TL/F/9336-8

Mask the most significant m bits and the LSB:

Description
Transfers control to the instruction at the memory address
calculated by adding the contents of the Program Counter
to a specially formed displacement. The displacement is
formed by rotating a copy of the source register Rs the value of b bits to the right, masking (setting to zero) the most
significant m bits, masking the least significant bit, and then
sign extending the result to 16 bits. Typically, the JRMK
instruction transfers control into a jump table. The LSB of
the displacement is always set to zero so that the jump table
may contain two word instructions, (e.g., LJMP). The range
of JRMK is from + 126 to ~128 relative to the Program
Counter. Note that the Program Counter initially contains
the memory address of the next instruction following JRMK.
The source register Rs may specify any active CPU register.
The rotate value b may be from 0 to 7, where 0 causes no
bit rotation to occur. The mask value m may be from 0 to 7;
where m = 0 causes only the LSB of the displacement to be
masked, m = 1 causes the MSB and the LSB to be masked,
m = 2 causes bits 7 -6 and the LSB to be masked, etc ...

m

~
register AND 0 ... 0 1 ... 1 0 -+ register
Modify the Program Counter:
PC + register(sign extended) -+ PC

Example
This example demonstrates the decoding of the address
frame of the 3299 Terminal Multiplexer protocol. In the address frame, only the bits 4-2 contain the address of the
Logical Unit.
EXX
0,1
;select main A, alt B
JRMK
RTR,1,4
;decode device address
;jump to device handler #0
ADDR.O
LJMP
LJMP
ADDR.l
;jump to device handler # 1
;jump to device handler # 2
LJMP
ADDR.2
LJMP

ADDR.7

;jump to device handler #7

Instruction Format
1101010101
Opcode
.
10
15
T-states
4
Bus Timing

.1

1

m

1

Rs

b

7

4

o

Figure 10
Operation
Copy Rs to a temporary register:
Rs -+ register

2-111

6.0 Instruction Set Reference
LCALL

(Continued)

Conditional Long Call

LCALL

Syntax
LCALL

Unconditional Long Call

Syntax
Rs, p, s, nn

LCALL

-register, absolute

nn

-absolute

Affected Flags
None

Affected Flags

Description

Description

If the bit in position p of register Rs is equal to the bit s, then
push the Program Counter, the ALU flags, the Global Interrupt Enable bit [GIE], and the current register bank selections onto the internal Address Stack. Following the push,
transfer control to the instruction at the absolute memory
address nn. The operand Rs may specify any active CPU
register. The value of p may be from 0 to 7, where 0 corresponds to the LSB of Rs and 7 corresponds to the MSB of
Rs. The absolute value nn is 16 bits long, (range: 0 to 64k),
therefore, all of instruction memory can be addressed.

Pushes the Program Counter, the ALU flags, the Global Interrupt Enable bit [GIE], and the current register bank selections onto the internal Address Stack; then unconditionally
transfers control to the instruction at the absolute memory
address nn. The value of nn is 16 bits long, (range: 0 to
64k), therefore, all of instruction memory can be addressed.

None

Example
Transfer control to the subroutine "Send.it.all", which could
be located anywhere in instruction memory.
LCALL

Example

Instruction Format
1
.

I

1

15

o

15
nn

I

1 10 10 0 11 11 11
1
Opcode
.s.

15

111110101111111011101010101010101
Opcode

;select main A, alt B
;If [TFE] = 1 call

EXX
0,0
LCALL NCF,7,1, Load.Xmit

Send.it.all

Instruction Format

Call the "Load.Xmit" subroutine when the Transmitter FIFO
Empty flag, [TFE], of the Network Command Flag register
(NCF) is "1".

8

Rs

p

7

15

4

L

T-states
(2 + 2)

o

Bus Timing

Figure 9

o

Operation

T-states
(2 + 2)

PC & [GIE] & ALU flags & register bank selections
Address Stack
nn-PC

Bus Timing

Figure 9
Operation
If Rs[p] = s then
PC & [GIE] & ALU flags & register bank selections
Address Stack
nn-PC
End if

2-112

o

6.0 Instruction Set Reference (Continued)
WMP Conditional Long Jump

WMP

Syntax
LJMP Rs, p, s, nn
-register, absolute
Affected Flags
None
Description
Conditionally transfers control to the instruction at the absolute memory address nn if the bit in position p of register Rs
is equal to the state of the bit s. The operand Rs may specify any active CPU register. The value of p may be from 0 to
7, where 0 corresponds to the LSB of Rs and 7 corresponds
to the MSB of Rs. The absolute value nn is 16 bits long,
(range: 0 to 64k), therefore, all of instruction memory can be
addressed.
Example
Long Jump to one of the receiver error handling routines
based on the contents of the Error Code Register (ECR}.
EXX
0,1,3,
;select main A, alt B
; and clear [GIE]
;set [SEC] in (TSR}
OR
01000000B,TSR
;read (ECR}
MOVE ECR, R11
; Determine error condition
LJMP R11, 0,1, Software_error
LJMP R11, 1, 1, Loss_of_Midbit
LJMP R11, 2,1, InvaliLEndinQ-Seq
LJMP R11, 3, 1, Parity_error
LJMP R11, 4,1, Software_error
Instruction Format

Syntax
LJMP nn
-absolute
-indexed
LJMP Dr]
Affected Flags
None
Description
Unconditionally transfers control to the instruction at the
memory address specified by the operand. The operand
may either specify an absolute instruction address nn, (16
bits long), or an index register Ir, which contains an instruction address. LJMP's addressing range is from 0 to 64k;
(I.e., all of instruction memory can be addressed).
Example
Transfer control to the instruction labeled "Reset.System",
which may be located anywhere in instruction memory.
LJMP
Reset.System
; go reset the system
Instruction Format
LJMP nn

1
nn

15
T-states
(2

+

nn

1

o

15
LJMP

Dr]

1111101~~~0~~1011101Ir

Rs

o

4

11110101111111010101010101010101
Opcode
.
15
0

1

I I

p
B 7

15

1
.

Unconditional Long Jump

15

6,J,
4
OO-IW
01-IX
10-IY
11-IZ

1

o
T-states
LJMP nn
LJMP Dr]
Bus Timing
LJMP nn
LJMP Dr]
Operation
LJMP nn
nn-+PC
LJMP Dr]
Ir-+PC

2)

Bus Timing
Figure 9
Operation
If Rs[p] = s
then nn-+ PC

2-113

10101010101

-(2

+ 2)

-2
-Figure 9
-Figure 9

0

6.0 Instruction Set Reference
MOVE

(Continued)
MOVE

Move Data Memory

[lr+Al. Rd

I I

Syntax
MOVE
MOVE
MOVE

[mlrl, Rd
[Ir+ Al. Rd
[IZ + nl. rd

Rd

-indexed, register
-register-relative, register
-immediate-relative, limited register

6 J,

15

OO-IW
01-IX
10-IY
l1-IZ

Affected Flags
None
Description

MOVE

Moves a data memory byte into the destination register
specified. The data memory source operand may specify
anyone of the index register modes; [mlrl, [Ir+ Al. [iZ + nJ.
The index register-relative mode, [Ir+ Al. forms its data
memory address by adding the contents of the index register Ir to the unsigned 8-bit value contained in the currently
active accumulator. The immediate-relative mode, [iZ + nl.
forms its data memory address by adding the contents of
the index register IZ to the unsigned 8-bit immediate value
n. The destination register operand Rd may specify any active CPU register; where as, the destination register operand
rd is limited to the active registers RO-R15.

.1

;calculate offset into record
;get data byte from record

0,1
[lZ+3], RTR

;select main A, alt 8
;transmit 4th element

Instruction Format
MOVE

[mlrl. Rd

I I
Rd

15

8

00
01
10
11

-

6

post-decrement
no change
post increment
pre-increment

o

4

t

00 - IW
01 - IX
10 - IY

11 - IZ
TL/F/9336-9

2-114

rd

n
11

MOVE [lZ + nl. rd
data memory ~ rd

In the final example, the 4th element of an Error Count table
is transmitted to a host. The index register IZ points to the
1st entry of the table.
EXX
MOVE

I

.

MOVE [lr+Al. Rd
data memory ~ Rd

;pop accum from ext. stack

R9, A
[lY+Al. R20

Opcode
15

Bus Timing

The second example demonstrates the random access of a
data by1e within a logical record contained in memory. The
index register IY contains the base address of the logical
record.
ADDA
MOVE

[lZ + nl. rd

I0 I0 I1 1

Figure 11
Operation
MOVE [mlrl, Rd
data memory ~ Rd

Example

[ + IXl. A

1

T-states
3

The first example loads the current accumulator by "poping" an external data stack, which is pointed to by the index
register IX.
MOVE

o

4

3

o

C

6.0 Instruction Set Reference
MOVE

(Continued)

Move Immediate

Syntax
MOVE n, rd
MOVE n, [Ir]

-immediate, limited register
-immediate, indexed

Affected Flags
None
Description

Moves the immediate value n into the destination specified.
The destination may be either a register, rd, (limited to the
active registers RO-R15), or data memory via an index register, Ir. The value n is 8 bits wide.
Example
Load the current accumulator with the value of 4.
MOVE 4, A
;Load accumulator
Instruction Format
MOVE n, rd

1
.1

I0 I1 I1

1

n

Opcode .
15
11
MOVE n, [Ir]

1

1 10

.

I 0 I 0 11

rd

3
10

Opcode

I 1
I n[7-5]
.

15

9

0

I I

n[4-0]

Ir

6-l-

4

0

OO-IW
01-IX
10-IY
11-IZ
T-states

MOVE
MOVE

n, rd
n, [lr]

Bus Timing
MOVE n, rd
MOVE n, [Ir]

-2
-3
-Figure 1
-Figure 12

Operation
MOVE n, rd
n .... rd

MOVE n, [lr]
n .... data memory

2-115

"tI
CO

........
»

Co)

6.0 Instruction Set Reference
MOVE

(Continued)
I nstruction Format

Move Register

MOVE

Syntax
MOVE

Rs, Rd

-register, register

MOVE
MOVE
MOVE

Rs, [mlrl
Rs, [Ir+AI
rs, [IZ + nl

-register, indexed
-register, register-relative
-limited register, immediate-relative

Rs, Rd
Rs

15
MOVE

9
Rs, [mlr]

1_ 11110101010111
Opcode
.

Affected Flags
None

15

Description
Moves the contents of the source register into the destination specified. The source register operand Rs may specify
any active CPU register; where as the source register operand rs is limited to the active registers RO-R15. The destination operand may specify either any active CPU register,
Rd, or data memory via one of the index register modes;
[mlr], [Ir+A], [IZ+nl. The index register-relative mode,
[lr+A], forms its data memory address by adding the contents of the index register Ir to the unsigned 8-bit value contained in the currently active accumulator. The immediaterelative mode, [IZ + n], forms its data memory address by
adding the contents of the index register IZ to the unsigned
8-bit immediate value n.
Example

a

4

m

1

8

Rs

o

4

6

~

+-

00
01
10
11

post-decrement
- no change
- post increment
- pre-increment

00
01
10
11

-

IW

IX
IY

IZ

TL/F/9336-10

MOVE
11
.1

Rs, [lr+AI
10101011101011
Opcode

15

Ir
6..[,

Rs

a

4

OO-IW
01-IX
10-IY
11-IZ

The first example loads the Transmitter FIFO with a data
byte in register 20.

MOVE

EXX
0,1
;select main A, alt B
MOVE R20, RTR
;Load the Transmitter FIFO
The second example "pushes" the current accumulator's
contents onto an external data stack, which is pointed to by
the index register IX.

.1

0

rs, [Z + nl

I 0 I a 11

I

I

Opcode .
11
15
T-states
MOVE Rs, Rd
MOVE Rs, [mlrl
MOVE Rs, [Ir+AI
MOVE rs, [IZ + nl

MOVE A, [IX -I
;push accum to ext. stack
The third example demonstrates the random access of a
data byte within a logical record contained in memory. The
index register IY contains the base address of the logical
record.
ADDA R9, A
;calculate offset into record
;update data byte in record
MOVE R20, [IY + Al

rs

n

3

-2

-3
-3

-3

Bus Timing
MOVE Rs, Rd
MOVE Rs, [mlrl
MOVE Rs, [Ir+AI
MOVE rs, [IZ + nl
Operation

In the final example, the 4th element of an Error Count table
is updated with a new value contained in the current accumulator. The index register IZ points to the 1st entry of the
table.
MOVE A, [IZ + 31
;update 4th element of table

MOVE
MOVE
MOVE
MOVE

2-116

Rs, Rd
Rs, [mlr]
Rs, [Ir+AI
rs, [IZ + nl

-Figure
-Figure
-Figure
-Figure

7
12
12
12

-Rs~Rd

-Rs ~ data memory
-Rs ~ data memory
-rs ~ data memory

a

6.0 Instruction Set Reference
OR

(Continued)

Or Immediate

ORA

Syntax

OR n, rsd
Affected Flags
N,Z
Description

-immediate, limited register

ORA
ORA

0,0
000000118, ICR

-register, register

Rs, Rd
Rs, [mlrJ

-register, indexed

Affected Flags
N,Z

Logically ORs the immediate value n to the register rsd and
places the result back into the register rsd. Note that only
the active registers RO-R15 may be specified for rsd. The
value of n is 8 bits wide.
Example
Mask both the Transmitter and Receiver interrupts via the
Interrupt Control Register {ICR), R2. Leave the other interrupts unaffected.
EXX
OR

Or with Accumulator

Syntax

Description

Logically ORs the source register Rs to the active accumulator and places the result into the destination specified.
The destination may be either a register, Rd, or data memory via an index register mode, [mlr]. Note that register bank
selection determines which accumulator is active.
Example
Write an 11-bit word to the Transmitter'S FIFO. This example assumes that the index register IX points to the location
of the data in memory.

;select main reg banks
;mask transmitter and
; receiver interrupts

TCR.settings:

EQU

001010008

Instruction Format

0 11 1 0 1 1 1
Opcode .
15
11
T-states
2

1
.

n

EXX
MOVE
MOVE
ORA
MOVE

rsd

3

o

ORA

Figure 7

Rs, Rd

I

11 1 1 1 1 1 1 0 1 1
Opcode

Operation

OR

;select main A, alt 8
;Ioad accumulator w/mask
;Ioad bits 8, 9, & 10
;write bits 8,9, 10 to {TCR)
;push 11-bit word to FIFO

Instruction Format

Bus Timing

rsd

1,1
TCR.settings,A
[lZ+ l,R20
R20,TCR
[lZ+l,RTR

n --+ rsd

15
ORA

I

1
Rs

Rd

0

4

9
Rs, [mlrl

111011101110111
Opcode
15

m
8

00
01
10
11

-

II I
Ir

6

I I
Rs

post-decrement
no change
post increment
pre-increment

I

0

4

+-

00
01
10
11

IW

- IX
- IY
- IZ

TL/F 19336-11

T-states

ORA
ORA

Rs, Rd
Rs, [mlrJ

-2
-3

Bus Timing

ORA
ORA

Rs, Rd
Rs, [mlrl

-Figure 7
-Figure 12

Operation
ORA Rs, Rd
Rs OR accumulator --+ Rd

ORA Rs, [mlrJ
Rs OR accumulator --+ data memory

2-117

6.0 Instruction Set Reference
RETF

(Continued)
Condition Specification Table for

Conditional Return

Rcc
Syntax

RETF f, s(,(gl (,rfll
Rcc (g(,rfll
-(optional syntax)
Affected Flags

If rf = 1 then N, l, C, and V
Description
Conditionally returns control to the last instruction address
pushed onto the internal Address Stack by popping that address into the Program Counter, if the state of the flag referenced by f is equal to the state of the bit s; or, optionally, if
the condition cc is met. See the tables on the following page
for the flags that f can reference and the conditions that cc
may specify. The conditional return instruction also has two
optional operands, g and rf. The value of g determines if the
Global Interrupt Enable bit [GIE] is left unchanged (g=O),
restored from the Address Stack (g = 1), set (g = 2), or
cleared (g = 3). If the g operand is omitted then g = 0 is assumed. The second optional operand, rf, determines if the
ALU flags and register bank selections are left unchanged
(rf = 0), or restored from the Address Stack (rf = 1). If the rf
operand is omitted then rf = 0 is assumed.
Example
This example demonstrates both syntaxes of the conditional return instruction testing for a carry result from a previous
instruction; (i.e., [C] = 1). If the condition is met then the
return occurs, else the next instruction following the return
is executed. The current environment is left unchanged.
RETF 001 B,1
; If [C] = 1 then return

RC

15

f

4

3

2

[l]
[l]
[l]
[l]
[C]
[C]
[V]
[V]
[N]
[N]
[RA]
[RA]
[RE]
[RE]
[DAV]
[DAV]
[TFF]
[TFF]

= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0
= 1
=0

f

(binary)

Flag Referenced

(000)
(001)
(010)
(011)
(100)
(101)
(110)
(111)

[l]
in (CCRI
[C]
in (CCRI
[V]
in (CCRI
[N]
in (CCRI
[RA]
in (TSRI
[RE]
in (TSRI
[DAV] in (TSRI
[TFF] in (TSRI

Note: The value of f for [DAVI differs from the numeric
value for the position of [DAV] in I TSR J .

1 1
9
6,J..

Condition Tested for

0
1

2
3
4
5
6'
7

; If [C] = 1 then return

1101110\1111111\01
Opcode
.

Meaning

lero
Not lero
Equal
Not Equal
Carry
No Carry
Overflow
No Overflow
Negative
Positive
Receiver Active
Not Receiver Active
Receiver Error
No Receiver Error
Data Available
No Data Available
Transmitter FIFO Full
Transmitter FIFO Not Full

Flag Reference Table for "f"

Instruction Format

.1

cc

l
Nl
EO
NEO
C
NC
V
NV
N
P
RA
NRA
RE
NRE
DA
NDA
TFF
NTFF

"cc"

o

Oo-GIE not affected
01-Restore GIE
10-SetGIE
11-Clear GIE
T-states
2 if condition is not met

3 if condition is met
Bus Timing
Figure 7 if condition is not met
Figure 8 if condition is met
Operation
If flag f is in state s then
Case g of
0: leave [GIE] unaffected, (default)
1: restore [G IE] from Address Stack
2: set [GIE]
3: clear [GIE]
End case
If rf= 1 then
restore ALU flags from Address Stack
restore register bank selection from Address Stack
End if
Address Stack - PC
End if
2-118

6.0 Instruction Set Reference
RET

(Continued)

Unconditional Return

ROT

Rotate

Syntax
RET {g (,rf))

Syntax

Affected Flags

Affected Flags
N,Z,C

ROT

If rf= 1 then N, Z, C, and V

Rsd, b

-register

Description

Description

Unconditionally returns control to the last instruction address pushed onto the internal Address Stack by popping
that address into the Program Counter. The unconditional
return instruction also has two optional operands, g and rf.
The value of g determines if the Global Interrupt Enable bit
[GIE] is left unchanged (g=O), restored from the Address
Stack (g= 1), set (g=2), or cleared (g=3). If the g operand
is omitted then g = 0 is assumed. The second optional operand, rf, determines if the ALU flags and register bank selections are left unchanged (rf=O), or restored from the Address Stack (rf= 1). If the rf operand is omitted then rf=O is
assumed.

Rotates the contents of the register Rsd b bits to the right
and places the result back into that register. The bits that
are shifted out of the LSB are shifted back into the MSB,
(and copied into the Carry flag). The value b may specify
from 0 to 7 bit rotates.
Example
Add 3 to the Address Stack Pointer contained in the Internal
Stack Pointer register (iSP), R30.
MOVE
ROT
ADD
ROT
MOVE

Example
Return from an interrupt.
RET

1,1

ISP, R8
R8, 4
3, R8
R8, 4
R8, ISP

;get (iSP)
;shift [ASP] to low order nibble
;add 3 to [ASP]
;shift [ASP] to high order nibble
;store new (iSP)

Instruction Format

;Restore environment & return

I I

Instruction Format
11

I 0 I 1 I ~~;o~~ I 1 I 1 11 I

15

Rsd
g

6!

I rf 1 0 I 0 I 0 I 0 1
4

3

0

15

7

4

o

T-states
2
Bus Timing
Figure 7
Operation

OO-GIE not affected
01-Restore GIE
10-SetGIE
11-Clear GIE
T-states
2
Bus Timing
Figure 7
Operation

Rsd
TL/F9336-12

Case g of
0: leave [GIE] unaffected, (default)
1: restore [GIE] from Address Stack
2: set [GIE]
3: clear [GIE]
End case
If rf= 1 then
restore ALU flags from Address Stack
restore register bank selection from Address Stack
End if
Address Stack ---+ PC

•
2-119

6.0 Instruction Set Reference

(Continued)

SBCA Subtract with Carry and Accumulator

SHL

Syntax

Syntax

SBCA Rs, Rd
-register, register
SBCA Rs, [mlr]
-register, indexed
Affected Flags
N,Z,C,V
Description
Subtracts the active accumulator and the carry flag from the
source register Rs, placing the result into the destination
specified. The destination may be either a register, Rd, or
data memory via an index register mode, [mlr]. Negative
results are represented using the two's complement format.
Note that register bank selection determines which accumulator is active.
Example
Subtract the constant 109 from the index register IW, (which
is 16 bits wide).
SUBA A, A
;Clear the accumulator
SUB
109, R12
;Iow byte of IW-109
SBCA R13, R13
;high byte of IW-borrow
Instruction Format
SBCA Rs, Rd

SHL Rsd, b
-register
Affected Flags
N,Z,C
Description
Shifts the contents of the register Rsd b bits to the left and
places the result back into that register. Zeros are shifted in
from the right, (i.e., from the LSB). The value b may specify
from 0 to 7 bit shifts. The Carry flag contains the last bit
shifted out.
Example
Place a new internal Address Stack Pointer into the Internal
Stack Pointer register (iSP l. R30. Assume that the new
[ASP] is located in register 20.
MOVE ISP,RB
;read (iSP) for [DSP]
AND
00001111 B,RB ;save [DSP] only
SHL
R20,4
;Ieft justify [ASP]
R20,ISP
;combine [ASP] + [DSPl.
ORA
; then place into (iSP)
Instruction Format

15

Rs

9

SBCA

15

o

4

15

1 1 1
m • Ir .
8

00
01
10
11

-

6

post-decrement
no change
post Increment
pre-Increment

Rs

o

t - IW

00
01
10
11

- IX
- IY
- IZ

TL/F/9336-14

-2
-3

Bus Timing

SBCA Rs, Rd
SBCA Rs, [mlr]

Rsd

4

Operation

o

4

T-states

Rs, Rd
Rs, [mlr]

7

2
Bus Timing
Figure 7

TL/F9336-13

SBCA
SBCA

(B-b)

T-states

Rs, [mlr]

1_ 11011101011111
Opcode
.

1 1

11111010111010111
Opcode

1

Rd

Shift Left

-Figure 7
-Figure 12

Operation
SBCA Rs, Rd
Rs - accumulator - carry bit ~ Rd
SBCA Rs, [mlr]
Rs - accumulator - carry bit ~ data memory

2-120

6.0 Instruction Set Reference (Continued)
SHR

SUB

Shift Right

Syntax
SHR Rsd, b
Affected Flags
N,Z,C

-register

SUB 3, R10
; R10 - 3 Instruction Format
0 1 0 11 1 0 1
1
. Opcode .
15
11
T-states
2
Bus Timing
Figure 7
Operation
rsd-n-rsd

1 1
Rsd

4

-immediate, limited register

Affected Flags
N,Z,C,V
Description
Subtracts the immediate value n from the register rsd and
places the result back into the register rsd. Note that only
the active registers RO-R15 may be specified for rsd. The
value of n is limited to 8 bits; (signed range: + 127 to
-128). Negative numbers are represented using the two's
complement format.
Example
Subtract the constant 3 from register 10.

Description
Shifts the contents of the register Rsd b bits to the right and
places the result back into that register. Zeros are shifted in
from the left, (i.e., from the MSB). The value b may specify
from 0 to 7 bit shifts. The Carry flag contains the last bit
shifted out.
Example
Right justify the Address Stack Pointer from the Internal
Stack Pointer register (lSPI, R30.
MOVE ISP, R20
;Load [ASP] from (lSPI
SHR
R20,4
;right justify [ASP]
Instruction Format

1111010111010101 1 1
1
b
.
Opcode
.
15
7
T-states

Subtract Immediate

Syntax
SUB n, rsd

o

2

Bus Timing
Figure 7
Operation

TL/F/9336-15

2-121

R10

n

rsd
3

0

6.0 Instruction Set Reference
SUBA

(Continued)

Subtract with Accumulator

Syntax
SUBA Rs, Rd
SUBA Rs, [mlr)

TRAP

-register, register
-register, indexed

Affected Flags
None

Affected Flags
N, Z,C, V

Description
Pushes the Program Counter, the Global Interrupt Enable bit
[GIE), the ALU flags, and the current register bank selections onto the internal Address Stack; then unconditionally
transfers control to the instruction at the memory address
created by concatenating the contents of the Interrupt Base
Register (IBR} to the value of v extended with zeros to 8
bits. If the value of g' is equal to "1" then the Global Interrupt Enable bit [GIE) will be cleared. If the g' operand is
omitted, then g' = 0 is assumed. The vector number v
points to one of 64 Interrupt Table entries; (range: 0 to 63).
Since some of the Interrupt Table entries are used by the
hardware interrupts, the TRAP instruction can simulate
hardware interrupts. The following table lists the hardware
interrupts and their associated vector numbers:

Description
Subtracts the active accumulator from the source
register Rs and places the result into the destination specified. The destination may be either a register, Rd, or data
memory via an index register mode, [mlrJ. Negative numbers are represented using the two's complement format.
Note that register bank selection determines which accumulator is active.
Example
In the first example, the value 4 is placed into the currently
active accumulator, that accumulator is subtracted from the
contents of register 20, and then the result is placed into
register 21.
MOVE
SUBA

4, A
R20, R21

Software Interrupt

Syntax
TRAP v (,g'}

;Place constant into accum
;R20 - accum - R21

Hardware Interrupt Vector Table

In the second example, the alternate accumulator of register bank B is selected and then subtracted from register 20.
The result is placed into the data memory pointed to by the
index register IZ and then the value of IZ is incremented by
one.
EXX
SUBA

0, 1
;Select alt accumulator
R20, [lZ +) ;R20 - accum - data mem
;and increment data pointer

Instruction Format

v

(Binary)

28
4
8
12
16
20

(011100)
(000100)
(001000)
(001100)
(010000)
(010100)

Example
Simulate the Transmitter FIFO Empty interrupt.

SUBA Rs, Rd

I
Rd

15

Interrupt
NMI
RFF/DAIRA
TFE
LTA
BIRQ
TO

8, 1

TRAP

Rs

9

0

4

;TFE interrupt simulation

Instruction Format

SUBA Rs, [mlr)
11011101011101
1
_
Ope ode
.

15

8

00
01
10
11

-

I I

m .

ir

6

post-decrement
no change
post increment
pre-increment

.

1 1
Rs

4

v

15

1

t

-

Bus Timing
Figure 7

IW
IX
IY
IZ

Operation
PC & [GIE) & ALU flags & register bank selections
- Address Stack
if g' = 1
then clear [GIE)
Create PC address by concatonating the (IBR} register to
the vector number v as shown below:

TL/F/9336-16

T-states
SUBA Rs, Rd
SUBA Rs, [mlr)
Bus Timing
SUBA Rs, Rd
SUBA Rs, [mlr)

-2
-3
-Figure 7
-Figure 12

Operation
SUBA Rs, Rd
Rs - accumulator SUBA Rs, [mlr)
Rs - accumulator -

o

5

T-states
2

0
00
01
10
11

6

II

I I I I I II I I I

I Lpc

!

_
{IBR}
0 0
~1~5----~~------~7~~5----~----~0

Rd

TL/F/9336-17

data memory

2-122

r-----------------------------------------------------------------------,c
"a

XOR

Exclusive OR Immediate

.1

0

11 11 10

Opcode
15
T-states
2
Bus Timing
Figure 7
Operation
rsd XOR n -

Syntax
-register, register
XORA Rs, Rd
XORA Rs, [mlr] -register, indexed
Affected Flags
N,Z
Description
Logically exclusive ORs the source register Rs to the active
accumulator and places the result into the destination specified. The destination may be either a register, Rd, or data
memory via an index register mode, [mlr]. Note that register
bank selection determines which accumulator is active.
Example
Decode the data byte just received and place it into data
memory. This example assumes that the accumulator contains the "key" and that the index register IY points to the
location where the information should be stored.
EXX
1,1
;select alternate banks
XORA RTR, [IY + ] ;decode received byte and
; save it
Instruction Format
XORA Rs, Rd

I

n

.
11

W

XORA Exclusive OR with Accumulator

Syntax
XOR n, rsd
-immediate, limited register
Affected Flags
N,Z
Description
Logically exclusive ORs the immediate value n to the register rsd and places the result back into the register rsd. Note
that only the active registers RO-R15 may be specified for
rsd. The value of n is 8 bits wide.
Example
Encode/decode a data byte in register 20.
XOR code-pattern, R20
;encode/decode
Instruction Format
rsd

3

0

1 1

1

Rd

rsd
15

Rs

9

o

4

XORA Rs, [Mlr]

i i
R.
15

8

00
01
10
11

-

6

post-decrement
no change
post Increment
pre-Increment

o

4

~

00
01
10
11

-IW
- IX
- IY
- IZ
TL/F/9336-16

T-states
XORA Rs, Rd
-2
XORA Rs, [mlr] -3
Bus Timing
XORA Rs, Rd
-Figure 7
XORA Rs, [mlr] -Figure 12
Operation
XORA Rs, Rd
Rs XOR accumulator - Rd
XORA Rs, [mlr]
Rs XOR accumulator - data memory

2-123

...
;
co

6.0 Instruction Set Reference (Continued)

6.0 Instruction Set Reference

(Continued)

TABLE XXIII. Instruction Verse T-states, Affected Flags, and Bus Timing
Instruction

T-states

Affected
Flags

Timing
Figure

Instruction

T-states

Affected
Flags

Timing
Figure

ADCA

Rs, Rd

2

N,Z,C,V

7

MOVE

Rs, Rd

2

7

ADCA

Rs, [mlrl

3

N,Z,C,V

12

MOVE

Rs, [mlr]

3

12

ADD

n, rsd

2

N,Z,C,V

7

MOVE

Rs, [lr + Al

3

12

ADDA

RS,Rd

2

N,Z,C,V

7

MOVE

rs, [lZ + nl

3

12

ADDA

Rs, [mlrl

3

N,Z,C,V

12

MOVE

[mlr],Rd

3

11

AND

n, rsd

2

N,Z

7

MOVE

[lr + Al,Rd

3

11

ANDA

RS,Rd

2

N,Z

7

MOVE

[IZ + nl, rd

3

ANDA

Rs, [mlrl

3

N,Z

12

OR

n, rsd

N,Z

11

2

N,Z

7

7

ORA

Rs, Rd

2

N,Z

7

8

ORA

Rs, [mlrl

3

N,Z

12

N,Z,C,V

7

Rcc

(g (,rf}}

N,Z

7

2 false
3 true

N,Z,C,V*

7
8

BIT

rs, n

2

CALL

n

3

CMP

rs, n

2

CPL

Rsd

2

EXX

ba, bb (,g}

2

7

Jee

n

2 false
3 true

RET

(g (,rfll

2

N,Z,C,V'

7

7
8

RETF

f, s (,(g} (,rfll

2 false
3 true

N,Z,C,V*

7
8

2

N,Z,C

7

JMP

f, s, n

2 false
3 true

7
8

ROT

Rsd, b

SBCA

Rs, Rd

2

N,Z,C,V

7

JMP

n

3

8

SBCA

Rs, [mlrl

3

N,Z,C,V

12

JMP

Rs

4

10

SHL

Rsd, b

2

N,Z,C

7

JRMK

RS,b,m

4

10

SHR

Rsd, b

2

N,Z,C

7
7

LCALL

nn

(2+2)

9

SUB

n, rsd

2

N,Z,C,V

LCALL

Rs, p, s, nn

(2+2)

9

SUBA

RS,Rd

2

N,Z,C,V

7

LJMP

nn

(2+2)

9

SUBA

Rs, [mlrl

3

N,Z,C,V

12

LJMP

[lrl

2

7

TRAP

v (,g'}

2

LJMP

Rs,p,s,nn

(2+2)

9

XOR

n, rsd

2

N,Z

MOVE

n, rd

2

7

XORA

Rs, Rd

2

N,Z

7

MOVE

n, [lrl

3

12

XORA

Rs, [mlrl

3

N,Z

12

'If rf

= 1 then N, Z, C, and V are affected.

2-124

7
7

C

6.0 Instruction Set Reference

"U

co

(Continued)

........

W

»

TABLE XXIV. Instruction Opcodes
Hex

OOOO-OFFF

Opcode

15

1000-IFFF

10

IOpcode
0 I 0 11

10

10

10 11 I 0 I 0
Opcode

10 11 10 11
Opcode

10 11 11 I 0
Opcode

10

I1I1I1
Opcode

15

8000-87FF

11 10 I 0 10
Opcode
15

I I I

I

I I I

I

I I I

I I I

I

I I I

11

I I I

I

I I I

11

I I I

I

I

I I I

11

I I I

I

I I I

11

I I
m
10

I

I I
b
7

I4

0

I I I
rsd
3

0

I I I
rs
3

0

I I I
rsd
3

0

I I I
rsd
3

0

I I I
rsd
3

0

I I I

I

n

I0 I

3

I

n

I

rs

I

n

0

I I I

I

n

I

3

I

n

I

rsd

I

n

I I I

I I I

I

11

15

7000-7FFF

I I I

I

15

SOOO-SFFF

I

n

11

15

5000-5FFF

I

11

15

4000-4FFF

I I I

IOpcode
0 11 I 0 I
I 0 11 11
Opcode

I I I

n

I

15

3000-3FFF

I

11

15

2000-2FFF

I I I

101010101
Opcode

KEY

Instruction

rs

I

3

0

I I I

2-125

Rs
0

I

ADD

n, rsd

I

MOVE

rs, [IZ + n]

I

SUB

n, rsd

m
IrIr
Ir+
+Ir

00
01
10
11
Ir
00
01
10
11

IW
IX
IY
IZ

g

I

CMP

rs, n

I

AND

n, rsd

00
01
10
11

NCHG
RI
EI
Di

g'
10
1

I

OR

n, rsd

I

XOR

n, rsd

I

BIT

rs, n

I

JRMK

RS,b,m

NCHG
DI
ba/bb

000
001
010
011
100
101
110
111

[Z]
[C]
[V]
[N]
[RA]
[RE]
[DAV]
[TFF]

I

!!

6.0 Instruction Set Reference (Continued)
TABLE XXIV. Instruction Opcoc:les (Continued)

Q

Hex

Opcoc:le

SSOO-SBFF

1
1 1 1 1
\110101011101 1 1
n[7-5] 1 Ir 1
n[4-0]
Opcode
\
15
9
6
4
0

SCOO-SOFF

11101~~!~~llI0Isl
15

OOOO-FFFF
1

SEOO-SFFF

1 1
1 1 1 1
p
Rs
1
1
S 7
4
0

MOVE n, Ur]

WMP

1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
nn
1
15
0

1 1 1 1
1
111011101010101 1
AOOA
Opcode
m 1 Ir 1
Rs
1
15
4
S
6
0

NCHG
RI
EI
01

NCHG 1
01

Rs, [mlr]

1
1
1 1 1 1
AOCA
m 1 Ir 1
Rs
1
8
6
4
0

Rs, [mlr]

1
1 1 1 1
111011101011101 1
SUBA
Opcode
m 1 Ir 1
Rs
1
15
S
6
4
0

RS,[mlr]

2-126

00
01
10
11

10
1

AOOO-A1FF

A400-A5FF

IW
IX
IV
IZ

g'

1 1 1
11 10 1 0 11 1 1 1 1 1 1 1 1
MOVE UZ+nl,rd
Opcode
n
rd
1
1
15
11
3
0

15

Ir

g

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
nn
1
15
0

1110Ib~~210111

IrIr
Ir+
+Ir

00
01
10
11

9000-9FFF

A200-A3FF

m
00
01
10
11

Rs, p, s, nn

1 1 1 1
1110101011111111 1 1
LCALL Rs, p, s, nn
Opcode
s
p
Rs
1
1
15
S 7
4
0

OOOO-FFFF

KEY

Instruction

000
001
010
011
100
101
110
111

[Z]
[C]

[V]
[N]
[RA]
[RE]
[OAV]
[TFF]

C

6.0 Instruction Set Reference

""tJ
00

(Continued)

Co)

TABLE XXIV. Instruction Opcodes (Continued)

KEY

Hex

Opcode

A600-A7FF

1
m

\1101110101111\
Opcode
15

ASOO-A9FF

AAOO-ABFF

1
m

15

1

1
Ir

1

1
Ir

Rs, [mlrJ

0
1

1 1
Rs

1

1

1 1
Rs

1

m

ANDA Rs, Rs, [mlr]

1

ORA

Rs, [mlr]

\

4

IrIr
Ir+
+Ir

00
01
10
11
Ir

\

0

1

6

SCBA
\

4

1

8

1

4

6
1
m

\11011101110111
Opcode

1 1
Rs

1

6

8

15

1
Ir

1

S

111011101110101
Opcode

Instruction

00
01
10
11

IW
IX
IY
IZ

0

9
ACOO-ADFF

111011101111101
Opcode

1
Ir

1

8

15

AEOO-AE1F

1
m

1

1

BOOO-BFFF

4

6

9

15

11

1

1
n

1

1

1

3

1

EXX

ba,bb (,g)

RETF
Rcc

f,s{,(g) (,rt))
(g(,rt) )

0

IrtlOlololol

4

RET

(g(,rt) )

0
1

1

3

2-127

g'

Rsd
10
1

1
f

2

3

NCHG
RI
EI
DI

NCHG 1
DI
ba/bb

0
1

4

11 1 0 1 1 1 0 11 1 1 1 1 1 1 11 1 1
Opcode
9
15
6
1

2

3

1 rt 1 s 1

6

1

CPL

00
01
10
11

\

0

1

1110111011111111101
Opcode

11 1 0 1 1 1 1 1
Opcode

1

Ibalbblololol

9

15

AFSO-AFFO

1 1
Rs

4

\110111011111110111
Opcode

XORA Rs, [mlr]
\

0
1

11101110111111101010101
Opcode

15
AFOO-AF7F

1

4

6

15

AESO-AEFS

1 1
Rs

1

1
rd

1

MOVE n,rd
1
0

000
001
010
011
100
101
110
111

[Z]
[C]
[V]
[N]
[RA]
[RE]
[DAV]
[TFF]

"'"'""''
»

~

~

6.0 Instruction Set Reference

(Continued)

00

a.
C

TABLE XXIV. Instruction Opcodes (Continued)
Hex
COOO-C1FF

Opcode

15

C200-C3FF

C400-C47F

1
1
m 1 Ir 1

111110101010101
Opcode
8

C480-C4FF

15

1

MOVE

Rs, [lr+A)

SHR

Rsd, b

1

IW
IX
IY
IZ

00
01
10
11

NCHG
RI
EI
DI

g'

[DE]
1

SHL

Rsd,b

ROT

Rsd,b

DI

1

1
0

1 1
n

1 1

JMP

n

CALL

n

1
0

1 1 1

Ir
00
01
10
11

g

1

1 1 1
Rsd

7

11111010111110101
Opcode

IrIr
Ir+
+Ir

0

4
1 1 1

11111010111011111
Opcode

[lr+AJ. Rd

0

4

7

MOVE

1 1 1 1
Rsd

1 1
b
1

Rs, [mlr)

1

1

4

7

MOVE

0
1 1 1
Rsd

1 1
(8·b) 1

11111010111011101
Opcode

15

CCOO-CCFF

7

[mlrJ. Rd

m
00
01
10
11

0

4

1 1
b
1

11111010111010111
Opcode

15

CBOO-CBFF

6

11111010111010101
Opcode

1 1
Rd

1 1 1 1
Rs

1
Ir 1

MOVE
1

4

6

1111101010111010111
Opcode

15

CAOO-CAFF

1
0

1 1

1
Ir 1

1111101010111010101
Opcode

15

C900-C9FF

1 1
Rd

1
1 1 1 1
111110101010111 1
Opcode
m 1 Ir 1
Rs
1
15
8
6
4
0

15

C800-C8FF

1
4

6

15

KEY

Instruction

1 1
n

1 1
1
0

7

2·128

000
001
010
011
100
101
110
111

[Z)
[C)
[V]
[N]
[RA]
[RE]
[DAV]
[TFF]

6.0 Instruction Set Reference (Continued)
TABLE XXIV. Instruction Opcodes (Continued)

Hex
COOO-C060

Opcode

I

1111101011111011101
Opcode
15

COBO-C09F

Instruction
10101010101

Ir

4

6

CEOO
OOOO-FFFF

1

11111010111110111110101
Opcode
15

I I I
Rs

4

I I I

1

I I I

1
nn

1

LJMP

nn

LCALL

nn

I I I
1

15

0

111110101111111011101010101010101
Opcode
0

15

I I I

I I I

1

1

I I I

1
nn

1

I I I
1

15

0

I

1111101011111111111
1
Opcode
g'
15

6

I I

I

11 11 10 0 1
1
Opcode
5
15

Rs

0

I I I

OOOO-OFFF

JMP
1

111110101111111010101010101010101
Opcode

1

CFBO-CFFF

[lrl

0

15

CEBO
OOOO-FFFF

LJMP

0

11

I
10

I I I
v

5

I I I
1

1

TRAP

v(,g'l

JMP
Jcc

1,5, n
n

1
0

1
n

I I I
1
0

7

2·129

000
001
010
011
100
101
110
111

[Z]
[C]
[V]
[N]
[RA]
[RE]
[OAV]
[TFF]

==
~

6.0 Instruction Set Reference

(Continued)

CI)

C-

TABLE XXIV. Instruction Opcodes (Continued)

O

Hex
EOOO-E3FF

Opcode
1111111010101
Opcode
15

E400-E7FF

11 11 11 10 1 0 11
Opcode

ECOO-EFFF

11 11 11 1 0 11 1 0
Opcode
15
11 11 11 1 0 11 11
Opcode

I

11 11 11 11 10 1 0
Opcode

11 1 1 1 1 1 1 1 0 1 1
Opcode

11 11 11 11 11 1 0
Opcode

11 1 1 1 1 1 1 11 1 1
Opcode
15

1 1 1
Rd

I

1

1

1 1
Rd

1

9

I

1

1 1
Rd

1

9

I

1 1 1
Rd

1

9

I

15

FCOO-FFFF

1

9

15

FBOO-FBFF

1 1 1
Rd

I

15

F400-F7FF

1

9

15

FOOO-F3FF

1 1
Rd

9

15

EBOO-EBFF

1

1

1 1
Rd

1

9

I

1

9

1 1
Rd

KEY

Instruction

1

I
I

1

I
I
I
I

1

ADDA

Rs, Rd

ADCA

Rs, Rd

m

0
1

1 1
Rs

1

Ir

1

4

0
1

1 1
Rs

1

SUBA

1 1
Rs

RS,Rd

1

g

1

SBCA

Rs, Rd

ANDA

RS,Rd

00
01
10
11

1

4

0
1

1 1
Rs

1
0

1 1
Rs

NCHG
RI
EI
DI

g'

1

4
1

IW
IX
IY
IZ

00
01
10
11

0
1

IrIr
Ir+
+Ir

00
01
10
11

1

4

I4
I

1 1
Rs

1

1

ORA

RS,Rd

XORA

RS,Rd

0
1

NCHG
DI
ba/bb

1

4

0
1

1 1
Rs

1
1

4

0
1

1 1
Rs

4

2·130

1

MOVE
1
0

Rs, Rd

000
001
010
011
100
101
110
111

[Z]
[C]
[V]
[N]
[RA]
[RE]
[DAV]
[TFF]

I

C

"U
00

7.0 CPU Registers

Alternate

INTRODUCTION

OCR

The CPU can address a total of 44 8-bit registers, providing
access to:
• 20 general purpose registers
• 8 configuration and control registers
• 4 transceiver access registers
• 2 8-bit accumulators
• 4 16-bit poi nters
• 16-bit timer
• 16-byte data stack
• address and data stack pointers
The registers are organized as shown in Figure 13. The first
12 locations, RO-R11, are arranged in two groups of
banked registers: Group A (RO-R3) and Group B (R4-R11).
Each group contains a Main and an Alternate bank, only
one of which is active and thus can be accessed in program
execution. Switching between the banks is performed by the
exchange instruction EXX, which uses a two-bit field to select which registers occupy RO-R3 and R4-R11.

A:

CCR

RO
Rl

'FeR ICR

R2

ATR

----

Alternate A
Main B
Alternate B

ACR

R3

f - - GPO

R4

~

GPl

R5

GP2

R6

8: f - - GP3
GP4'
f - - GP4 (accumulator)

R8

TSR

rn;mGP5'

I GP6'

r;r

~

Inde. Reglsters
(polnters)

The BCP powers-up in Alternate bank A, Alternate bank B.
This allows the initialization registers to be accessed without
bank switching. When running a non-transceiver task, Main
bank A and Main bank B are typically switched in, allowing
access to the CPU control and transceiver status registers
and eight general purpose registers. When the transceiver
needs attention, Alternate bank B can be switched active
which allows access to the transceiver registers.
For those instructions that require two operands, R8, (each
bank) is designated as the accumulator and provides the
second operand. However, the result of such an operation
is stored back in the accumulator only if it is specified as the
destination.
Of the 38 instructions which have direct register access, 28
can address all 32 locations, the remaining 10 instructions
(those with an immediate data field) being limited to
RO-R15. These instructions, however, still have access to
all registers required for transceiver operation, together with
the CPU control and status registers, 12 general purpose
registers and two of the index registers.
In this chapter, two descriptions of the special function registers are provided. The Register Overview section describes the function of each bit field arranged by the registers in which they occur; this section is useful for decoding
register contents and becoming familiar with the register
set. The Bit Definition Table lists the function and power-up
state of each bit field arranged by the function that it is
associated with; this section is useful in programming the
BCP. These sections are prefaced by a Bit Index which
cross references each bit field into both the Register Overview and Bit Definition Table.

TImer

Stacks

~

I

RTR

CPU control and transceiver
status
CPU and transceiver
configuration
8 general purpose
4 transceiver access,
4 general purpose

.a::o.
.a::o.

NCr

iR

Registers in the RO-R11 address space are allocated in a
manner that minimizes the need to switch between banks:

Main A

Co)

Main
I

R7

GP5

R9

GP6

Rl0

GP7

Rll

W (low byte)

I R12

W (high byte)

I R13

I X (low byte)

R14

I X (high byte)

R15

Y (low byte)

R16

Y (high byte)

R17

Z (low byte)

R18

Z (high byte)

R19

GP8

R20

GP9

R21

GP10

R22

GPll

R23

GP12

R24

GP13

R25

GP14

R26

GP15

R27

_ _ _ _~ R28
~_TR_L
TRH
: R29

l

iSP
OS

I

R30
: R31
TLlF/9336-32

FIGURE 13. Register Map

2-131

•

7.0 CPU Registers (Continued)
BIT INDEX
An alphabetical listing of all status/control bits in the CPU-addressable special function registers, with a brief summary of
function. Detailed definitions are provided in the Bit Definition Table.
Bit

Name

ACK
ASP3-0
AT7-0
ATA
BIC
BIRQ
C
CCS
COD
DAV
DEME
DS7-0
DSP3-0
DW2-0
FB7-0
GIE
IES
IM4-0
IV15-8
IW1,0
LA
LMBT
LOR
LOOP
LTA
N
OVF
OWP
PAR
POLL
PS2-0
RA
RAR
RDIS
RE
RF10-8
RFF
RIN
RIS1,0
RLQ
RPEN
RR
RTF7-0
RW
SEC
SLR
TA
TCS1,0
TF10-8

poll/ACKnowledge
Address Stack Pointer
Auxilliary Transceiver control
Advance Transmitter Active
Bi-directionallnterrupt Control
Bi-directionallnterrupt ReQuest
Carry
CPU Clock Select
Clock Out Disable
Data AVailable
Data Error or Message End
Data Stack
Data Stack Pointer
Data memory Wait-state select
Fill Bits
Global Interrupt Enable
Invalid Ending Sequence
Interrupt Mask select
Interrupt Vector
Instruction memory Wait-state select
Line Active
Loss of Mid Bit Transition
Lock Out Remote
internal LOOP-back
Line Turn Around
Negative
receiver OVerFlow
Odd Word Parity
PARity error
POLL
Protocol Select
Receiver Active
Received Auto-Response
Receiver DISabled while active
Receiver Error
Receiver FIFO
Receive FIFO Full
Receiver INvert
Receiver Interrupt Select
Receive Line Quiesce
RePeat ENable
Remote Read
Receive/Transmit FIFO
Remote Write
Select Error Codes
Select Line Receiver
Transmitter Active
Transceiver Clock Select
Transmit FIFO

Location
NCF
ISP
ATR
TCR
ACR
CCR
CCR
OCR
ACR
TSR
NCF
OS
ISP
OCR
FBR
ACR
ECR
ICR
IBR
OCR
NCF
ECR
ACR
TMR
NCF
CCR
ECR
TCR
ECR
NCF
TMR
TSR
NCF
ECR
TSR
TSR
NCF
TMR
ICR
TCR
TMR
CCR
RTR
CCR
TCR
TCR
TSR
OCR
TCR

2-132

[1]
[7-4]
[7-0]
[4]
[4]
[4]
[1]
[7]
[2]
[3]
[3]
[7-0]
[3-0]
[2-0]
[7-0]
[0]
[2]
[4-0]
[7-0]
[4,3]
[5]
[1]
[1]
[6]
[4]
[3]
[4]
[3]
[3]
[0]
[2-0]
[4]
[2]
[0]
[5]
[2-0]
[6]
[4]
[7,6]
[7]
[5]
[6]
[7-0]
[5]
[6]
[5]
[6]
[6,5]
[2-0]

Function
Receiver Status
Stacks
Receiver Control
Transmitter Control
Interrupt Control
Interrupt Control
Arithmetic Flag
Timing Control
Timing Control
Receiver Status
Receiver Status
Stacks
Stacks
Timing Control
Transmitter Control
Interrupt Control
Receiver Error Code
Interrupt Control
Interrupt Control
Timing Control
Receiver Status
Receiver Error Code
Remote Interface
Transceiver Control
Receiver Status
Arithmetic Flag
Receiver Error Code
Transmitter Control
Receiver Error Code
Receiver Status
Transceiver Control
Receiver Status
Receiver Status
Receiver Error Code
Receiver Status
Receiver Control
Receiver Status
Receiver Control
Interrupt Control
Receiver Control
Receiver Control
Remote Interface
Transceiver Control
Remote Interface
Receiver Control
Receiver Control
Transmitter Status
Transceiver Control
Transmitter Control

7.0 CPU Registers (Continued)
BIT INDEX
An alphabetical listing of all status/control bits in the CPU-addressable special function registers, with a brief summary of
function. Detailed definitions are provided in the Bit Definition Table. (Continued)
Bit

Name

TFE
TFF
TIN
TlD
TM7-0
TM15-B
TMC
TO
TRES
TST

Location

Transmit FIFO Empty
Transmit FIFO Full
Transmitter INvert
Timer LoaD
TiMer
TiMer
TiMer Clock select
Time Out flag
Transceiver RESet
Timer StarT
oVerflow
Zero

V
Z

Function

NCF [7]
TSR [7]
TMR [3]
ACR [6]
TRl [7-0]
TRH [7-0]
ACR [5]
CCR [7]
TMR [7]
ACR [7]
CCR [2]
CCR [0]

REGISTER OVERVIEW
A list of all CPU-addressable special function registers, in
alphabetical order.
The Remote Interface Configuration register (RIC), which is
addressable only by the remote system, is not included. See
Section B.O for details of the function of this register.

Transmitter Status
Transmitter Status
Transmitter Control
Timer
Timer
Timer
Timer
Timer
Transceiver Control
Timer
Arithmetic Flag
Arithmetic Flag

GIE

ATR AUXILLIARY TRANSCEIVER REGISTER
[Alternate R2; read/write]
AT7 -0 - Auxiliary Transceiver ... In 5250 protocol
modes, bits 2-0 define the receive station address, and bits 7-3 control the amount of time
TX-ACT stays asserted after the last fill bit.

Each register is listed together with its address, the type of
access available, and a functional description of each bit.
Further details on each bit can be found in the "Bit Definition Table".

In B-bit protocol modes, bits 7-0 define the receive station address.
For further information, see Transceiver Section.

ACR AUXILLIARY CONTROL REGISTER
[Main R3; read/write]
TST

-

Timer StarT ... When high, the timer is enabled
and will count down from it's current value.
When low, timer is disabled. Timer is stopped by
writing a 0 to [TST].

TlD

-

TMC

- Timer Clock Select ... Selects timer clock frequency. Should not be written when [TST] is
high. Can be written at same time as [TST] and
[TlD].
TCS

Timer Clock

0
1

(CPU-ClK)/16
(CPU-CLK)/2

5

4

3

7

-

2

1

0

Input
1
Output
- Clock Out Disable ... When high, ClK-OUT output is at TRI-STATE.
-

0
0.5
1.0
1.5

6

-J..

-J..

11111

15.5

5

4

3

2

1

0

TO

- Time Out Flag ... Set high when timer counts to
zero. Cleared by writing a 1 or stopping the timer
(by writing a 0 to [TSTl).

RR

- Remote Read ... Set on the trailing edge of a
REM-RD pulse, if RAE is asserted and (RIC) is
pOinting to Data Memory. Cleared by writing a 1
to this location.

RW

- Remote Write ... Set on the trailing edge of a
REM-WR pulse, if RAE is asserted and (RIC) is
pOinting to Data Memory. Cleared by writing a 1
to this location.

BIRQ

o

lOR

00000
00001
00010
0001 1

CCR CONDITION CODE REGISTER
[Main RO; bits 0-3, 5-7 read/write, bit 4 read only]

Bi-directional Interrupt Control ... Controls direction of BIRQ.
BIC

COD

TX-ACT Hold Time (,...s)

I AT7 I AT6 I AT5 I AT4 I AT3 I AT2 I ATl I ATO I

I TST I TlD I TMC I BIC I rsv I COD I lOR I GIE I
BIC

ATR7-3

Timer LoaD ... When high, generates timer load
pulse. Cleared when load complete.

6

7

- Global Interrupt Enable ... When low, disables
all maskable interrupts. When high, works with
[lM4-0] to enable maskable interrupts.

Lock Out Remote ... When high, a remote system is prevented from accessing the BCP.

rsv ... state is undefined at all times.

2-133

7.0 CPU Registers (Continued)
BIRO - Bi-directional Interrupt ReQuest '" [Read
only]. Reflects the logic level of the Bi-directional
interrupt pin (BIRO). Updated at the beginning of
each instruction cycle.
7
6
5
4
3
2
o

I TO I RR I RW I BIRQ I
N

N

I

v

I

C

I

z

ECR ERROR CODE REGISTER
[Alternate R4 with SEC high; read only]
OVF
- Receiver OVerFlow ... Set when the receiver
has processed 3 words and another complete
frame is received before the FIFO is read by
the CPU. Cleared by reading IECR} or by asserting [TRES].
PAR
- PARity error ... Set when bad (odd) overall
word parity is detected in any receive frame.
Cleared by reading I ECR} or by asserting
[TRES].
- Invalid Ending Sequence .. , Set when the
IES
"mini-code violation" is not detected at the appropriate time during a 3270, 3299, or 8-bit
ending sequence. Cleared by reading I ECR}
or by asserting [TRES].

I

- Negative ... A high level indicates a negative
result generated by an arithmetic, logical or shift
instruction.
- OVerflOW ... A high level indicates an overflow
condition generated by an arithmetic instruction.
- Carry ... A high level indicates a carry or borrow
generated by an arithmetic instruction. During a
shift/rotate operation the state of the last bit shifted out appears in this location.
- Zero ... A high level indicates a zero result generated by an arithmetic, logical or shift instruction.

v
C

z

7

LMBT

RDIS

CPU Clock

o

OCLK
OCLK/2

1

7

Iccs ITCS1 ! TCSO ! IW1 I IWO ! DW2 I DW1 ! DWO!
TCLK

7

321

I DS7 I DS6 I DS5 I DS4 I DS3 ! DS2 ! DS1

0

IES ! LMBT ! RDIS !

- Loss of Mid-Bit Transition ... Set when the
expected Manchester Code mid-bit transition
does not occur within the allowed window.
Cleared by reading I ECR} or by asserting
[TRES].
- Receiver DISabled while active ... Set when
transmitter is activated while receiver is active,
without RPEN being asserted. Cleared by reading IECR} or by asserting [TRES].

6

5

4

321

0

6

543

2

1

0

I IV15 I IV14!IV131 IV12!IV11 IIV10! IV9

I.

I I I I I I I
IBR

I0 I 0 I

I IV8

I I I I I
vector address

8
5
o
Interrupt Vector
The interrupt vector is obtained by concatenating {lBR}
with the vector address:
15

DS DATA STACK
[Main R31; read/write]
D87-0 - Data Stack ... Data stack input/output port.
Stack is 16 bytes deep. Further information:
Chapter CPU.
654

1

IBR INTERRUPT BASE REGISTER
[Alternate R1; read/write]
IV15-8 - Interrupt Vector ... High byte of interrupt and
trap vectors. Further information: Chapter CPU.

00
OCLK
01
OCLK/2
10
OCLK/4
11
X-TCLK
IW1,O
- Instruction memory Wait-state select ...
Selects from 0 to 3 wait states for accessing
instruction memory.
DW2-0 - Data memory Walt-state select ... Selects
from 0 to 7 wait states for accessing data memory.

7

2

3

I FB7 I FB6 ! FB5 I FB4 I FB3 ! FB2 ! FB1 I FBO I

43210

TCSt,a

4

FBR FILL-BIT REGISTER
[Alternate R3; read/write]
FB7-0 - Fill Bits ... 5250 fill-bit control. Further information: Transceiver Section.

TCS1,O- Transceiver Clock Select ... Selects transceiver clock, TCLK, frequency.
OCLK represents the frequency of the on-chip
oscillator, or the externally applied clock on input
X1. X-TCLK is the external transceiver clock input.
765

5

I rsv I rsv Irsv I OVF I PAR !

DCR DEVICE CONTROL REGISTER
[Alternate RO; read/write]
ecs - CPU Clock Select .,. Selects CPU clock frequency. OCLK represents the frequency of the
on-chip oscillator, or the externally applied clock
on input X1.
CCS

6

0
I DSO !

Interrupt

Vector Address

NMI
Receiver
Transmitter
Line Turn Around
Bi-directional
Timer

011100
000100
001000
001100
010000
010100

rsv ... state is undefined at all times.

2-134

Priority

1 high
2
3
4
"'5 low

t

I

I.

7.0 CPU Registers (Continued)
76543210

ICR INTERRUPT CONTROL REGISTER
[Main R2; read/write]
RIS1,O -

ITFE I RFF I LA I LTA I DEME I RAR I ACK I POLL I

Receiver Interrupt Select ... Defines the
source of the Receiver Interrupt.
RIS1,O Interrupt Source
00 RFF + RE
01
DAV + RE
1 0 (unused)
11
RA
"+ .. indicates logical "or".

7

6

5

4

3

IRIS1 I RISO I rsv I IM4

2

11M3 11M2

1

I IM1

0
liMO

I

IM4-0 -Interrupt Mask ... Each bit, when set high,
masks an interrupt. 1M3 functions as an interrupt
mask only if BIRO is defined as an input. When
BIRO is defined as an output, 1M3 controls the
state of BIRO.
IM4-0

Interrupt

00000
XXXX1
XXX1X
XX1XX
X1XXX
1XXXX

No Mask
Receiver
Transmitter
Line Turn-Around
Bi-Directional
Timer

RTR RECEIVE/TRANSMIT REGISTER
[Alternate R4; read/write]
RTF7-0- Receive Transmit FIFO's ... Input/output port
to the least significant eight bits of receive and
transmit FIFO's. [OWPl, [TF10-8] and
[RTF7 -0] are pushed onto the transmit FIFO on
moves into IRTR}. [RF10-8] and [RTF7-0]
are popped from receiver FIFO on moves out of
I RTR I. Further information: Transceivers.

ISP INTERNAL STACK POINTER
[Main R30; read/write]
ASP3-0- Address Stack Pointer ... Input/output port of
the address stack pOinter. Further information:
Chapter CPU.
7

654

321

DEME - Data Error or Message End ... In 3270 & 3299
modes, asserted when a byte parity error is detected. In 5250 modes, asserted when the [111]
station address is decoded and [DAV] is asserted. Cleared by reading I RTR}. Undefined in
8-bit modes and in the first frame of 3299
modes.
RAR
- Received Auto-Response ... Set high when a
3270 Auto-Response message is decoded and
[RAR] is asserted. Cleared by reading I RTR I.
Undefined in 5250 and 8-bit modes and in the
first frame of 3299 modes.
ACK
- Poll/ ACKnowledge ... Set high when a 3270
poll/ack command is decoded and [RAR] is asserted. Cleared by reading I RTR}. Undefined in
5250 and 8-bit modes and in the first frame of
3299 modes.
POLL - POLL ... Set high when a 3270 poll command is
decoded and [RAR] is asserted. Cleared by
reading I RTR I. Undefined in 5250 and 8-bit
modes and in the first frame of 3299 modes.

7

0

DSP3-0- Data Stack POinter ... Input/output port of the
data stack pointer. Further information: Chapter
CPU.

6

5

4

321

0

TCR TRANSCEIVER COMMAND REGISTER
[Alternate R6; read/write]
RLO
- Receive Line Quiesce ... Selects number of
line quiesce bits the receiver looks for.

NCF NETWORK COMMAND FLAG REGISTER
[Main R1; read only]
TFE
- Transmit FIFO Empty ... Set high when the
FIFO is empty. Cleared by writing to I RTR}.
RFF
- Receive FIFO Full ... Set high when the Receive FI FO contains 3 received words. Cleared
by reading to I RTR}.
LA
- Line Active ... Indicates activity on the receiver input. Set high on any transition; cleared after
detecting no input transitions for 16 TCLK periods.
LTA
- Line Turn Around ... Set high when end of
message is received. Cleared by writing to
I RTR I writing a "1" to this location, or by asserting [TRES].

SEC
SLR

RLQ

Number of
Quiesces

o

2

1

3

- Select Error Codes ... When high {ECR I is
switched into {RTR I location.
- Select Line Receiver ... Selects the receiver
input source.
SLR

Source

o

TTL-IN
On-chip analog
line receiver

1

rsv. . state is undefined at all times

2-135

7.0 CPU Registers (Continued)
76543210
I RLa I SEC I SLR
ATA

OWP

TRH TIMER REGISTER - HIGH
[Main R29; read/write)
TM15-S- TIMer ... Input/output port of high byte of timer.
Further information: Chapter CPU.

I ATA I OWP I TF10 I TF9 I TFSI

- Advance Transmitter Active ... When high,
TX-ACT is advanced one half bit time so that the
transmitter can generate 5.5 line quiesce pulses.
- Odd Word Parity ... Controls transmitter word
parity.
OWP Word Parity

o

76543210
ITM151TM141TM131TM121TM111TM10lTM91TMSI
TRL TIMER REGISTER-LOW
[Main R2S; read/write)
TM7-0 - TiMer ... Input/output port of low byte of timer.
Further information: Chapter CPU.

Even
Odd

TF10-S-Transmlt FIFO ... [OWP) , [TF10-S) and
[RTF7 -0) are pushed onto transmit FIFO on
moves into IRTRl.

76543210

TMR TRANSCEIVER MODE REGISTER
[Alternate R7; read/write)
TRES - Transceiver RESet ... Resets transceiver
when high. Transceiver can also be reset by
RESET, without affecting [TRES).
LOOP - Internal LOOP-back ... When high, TX-ACT is
disabled (held at 0) and transmitter serial data is
internally directed to the receiver serial data input.
RPEN - RePeat ENable ... When high, the receiver can
be active at the same time as the transmitter.
RIN
- Receiver INvert ... When high, the receiver serial data is inverted.

TSR TRANSCEIVER STATUS REGISTER
[Alternate R5; read only)
TFF
- Transmit FIFO Full ... Set high when the FIFO
is full. I RTR 1 must not be written when [TFF) is
high.
TA
- Transmitter Active ... Reflects the state of TXACT, indicating that data is being transmitted.
Unlike TX-ACT, however, [TA] is not disabled by
[LOOP).
- Receiver ERRor ... Set high when a receiver
RE
error is detected. Cleared by reading I ECR 1 or
by asserting [TRES).
7

76543210
I TRES I LOOP I RPEN I RIN I TIN I PS2 I PS1

IPSO I

RA

5

4

3

2

o
RF9 I RFSI

- Receiver Active ... Set high when a valid starting sequence is received. Cleared when either
an end of message or an error is detected. In
5250 modes, [RA) is cleared at the same time
as [LA].
DAV
- Data Available ... Set high when valid data is
available in I RTR land ITSR 1. Cleared by reading I RTR l, or when an error is detected.
RF10-S- Receive FIFO ... [RF10-S) and [RTF7-0) reflect the state of the top word of the receive
FIFO.

TIN

- Transmitter INvert ... When high the transmitter serial data outputs are inverted.
PS2-0 - Protocol Select ... Selects protocol for both
transmitter and receiver.
PS2-0 Protocol
000
001
010
011
100
101
110
11 1

6

I TFF I TA I RE I RA I DAV I RF10

3270
3299 multiplexer
3299 controller
3299 repeater
5250
5250 promiscuous
S-bit
S-bit promiscuous

2-136

7.0 CPU Registers

(Continued)

BIT DEFINITION TABLE
The following tables describe the location and function of all control and status bits in the various BCP addressable special
function registers. The Remote Interface Configuration register (RICI, which is addressable only by a remote system, is not
included.

CPU (for further information see Chapter on the CPU).
Bit
Timing
Control

CCS

Name
CPU Clock Select

Location
OCR [7]

Reset State
1

Function
Selects CPU clock frequency.

CCS
0
1

CPUCLK
OCLK
OCLK/2

Where OCLK is the frequency of the on-chip oscillator, or
the externally applied clock on input X1.

Remote
Interface

Interrupt
Control

DW2-0

Data Memory
Wait-State Select

OCR [2-0]

111

IW1,0

Instruction Memory
Wait-State Select

OCR [4,3]

11

Selects from 0 to 3 wait states for accessing instruction
memory.

COD

Clock Out Disable

ACR [2]

0

When high, CLK-OUT is at TRI-STATE.

LOR'

Lock Out Remote

ACR [1]

0

When high, a remote processor is prevented from accessing
the BCP or its memory.

RR'

Remote Read

CCR[S]

0

Set whenever REM-RD is asserted. Cleared by writing a 1 to
[RR].

RW'

Remote Write

CCR[5]

0

Set whenever REM-WR is asserted. Cleared by writing a 1 to
[RW].

BIC

Bi-Directional
Interrupt Control

ACR[4]

0

Controls the direction of BIRO.

BIRO

Bi-Directional
Interrupt ReOuest

CCR[4]

GIE

Global Interrupt
Enable

ACR[O]

IM4-0

Interrupt Mask
Select

ICR [4-0]

Selects from 0 to 7 wait states for accessing data memory.

BIC

BIRQ

0
1

Input
Output

[Read Only]. Reflects the logic level of the (BIRO) input.
Updated at the beginning of each instruction cycle.
0
11111

When low, disables all maskable interrupts. When high,
works with [IM4-0] to enable maskable interrupts.
Each bit, when set high, masks an interrupt.

IM4-0

Interrupt

00000
XXXX1
XXX1X
XX1XX
X1XXX
1XXXX

No Mask
Receiver
Transmitter
Line Turn-Around
Bi-Directional
Timer

Priority

1
2
3
4
5

High

t
!Low

1M3 functions as an interrupt mask only when BIRO is
defined as an input. When defined as an output, 1M3 controls
the state of BIRO.
'These bits represent \he only visibility and controllhatthe processor has into the operation of the remote Interface controiler. The Remote Interfece Configuration
regiater, {RICI, accessible only by a remote processor, provides further control functions. See Remote Interface Chapter for more information.

2-137

7.0 CPU Registers

(Continued)

BIT DEFINITION TABLE (Continued)
The following tables describe the location and function of all control and status bits in the various SCP addressable special
function registers. The Remote Interface Configuration register (RIC l. which is addressable only by a remote system, is not
included.
CPU (for further information See Chapter on the CPU). (Continued)
Bit
Interrupt
Control

IV15-8

Name
Interrupt Vector

Location

Reset State

Function

ISR [7-0]

00000000

High byte of interrupt and trap vectors.
The interrupt vector is obtained by concatenating (ISR) with
the vector address:
Interrupt

I

I
15

RIS1,0

Receiver Interrupt
Select

ICR [7,6]

11

I

Defines the source of the Receiver Interrupt.
RIS1,O Interrupt Source
00
01
10
11

Address
and
Data
Stacks

Arithmetic
Flags

Vector Address

NMI
011100
Receiver
000100
Transmitter
001000
Line Turn Around
001100
Si-Directional
010000
Timer
010100
I I I I I
I
I
I
I
I
1
ISR
vector address
10 01
0
8
5
I nterru pt Vector

RFF + RE
DAV + RE
(unused)
RA

ASP3-0

Address Stack
Pointer

ISP [7-4]

0000

Address stack pointer. Writing to this location changes the
value of the pointer.

DSP3-0

Data Stack
Pointer

ISP [3-0]

0000

Data stack pointer. Writing to this location changes the value
of the pointer.

DS7-0

Data Stack

DS [7-0]

XXXXXXXX

C

Carry

CCR [1]

0

A high level indicates a carry or borrow generated by an
arithmetic instruction. During a shift/rotate operation the
state of the last bit shifted out appears in this location.

N

Negative

CCR [3]

0

A high level indicates a negative result generated by an
arithmetic, logical, or shift instruction.

V

oVerflow

CCR [2]

0

A high level indicates an overflow condition generated by an
arithmetic instruction.

Z

Zero

CCR [0]

0

A high level indicates a zero result generated by an
arithmetic, logical or shift instruction.

2-138

Data Stack Input/Output port. Stack is 16 bytes deep.

I

7.0 CPU Registers

(Continued)

BIT DEFINITION TABLE (Continued)

The following tables describe the location and function of all control and status bits in the various BCP addressable special
function registers. The Remote Interface Configuration register {RICl. which is addressable only by a remote system, is not
included.
CPU (for further information See Chapter on the CPU) (Continued)
Bit

Timer

Name

Location

Reset State

a

TLD

Timer LoaD

ACR [6]

TM15-8

Timer

TRH [7-0]

XXXXXXXX

TM7-0

Timer

TRL [7-0]

XXXXXXXX

TMC

Timer Clock
Select

ACR [5]

Function

Set high, to load timer. Cleared automatically when load
complete.

a

Input/output port of high by1e of timer.
Input/output port of low byte of timer.
Selects timer clock frequency. Must not be written when
[TST] high. Can be written at same time as [TST] and
[TLD].
TMC Timer Clock

a
1

CPU-CLK/16
CPU-CLK/2

TO

Time Out Flag

CCR [7]

a

Set high when timer counts to zero. Cleared by writing a 1 to
[TO] or by stopping the timer (by writing a a to [TST]).

TST

Timer StarT

ACR [7]

a

When high, timer is enabled and will count down from its
current value. Timer is stopped by writing a a to this location.

TRANSCEIVER

Table includes control and status bits only. It does not include definitions of bit fields provided for the formatting (de-formatting)
data frames. For further information see the Transceiver Section.
Bit

Name

Transceiver LOOP
Control

Internal
LOOP-back

TMR [6]

Protocol Select

TMR [2-0]

PS2-0

Location

RTF7-0 Receive/Transmit RTR [7-0]
FIFOs

Function

Reset State

a
000

When high, TX-ACT is disabled (held at 0) and transmitter
serial data is internally directed to the receiver serial data
input.
Selects protocol for both transmitter and receiver.
PS2-0

Protocol

000
001
010
011
100
101
11a
111

3270
3299 Multiplexer
3299 Controller
3299 Repeater
5250
5250 Promiscuous
8-bit
8-bit Promiscuous

XXXXXXXX Input/output port of the least significant 8 bits of receive and
transmit FIFOs. [OWPl, [TF10-8] and [RTF1-0] are pushed
onto the transmit FIFO on moves to {RTR I. [RF10-8] and
[RTF7 -0] are popped from receive FIFO on moves out of
{RTRI.

2-139

7.0 CPU Registers

(Continued)

BIT DEFINITION TABLE (Continued)
TRANSCEIVER (Continued)
Table includes control and status bits only. It does not include definitions of bit fields provided for the formatting (de-formatting)
data frames. For further information see the Transceiver Section. (Continued)
Bit
Transceiver TCS1,0
Control
(Continued)

Name
Transceiver Clock
Select

Location Reset State
DCR [6,5]

10

Function
Selects transceiver clock, TCLK, source.
TCS1,O

TRES
Transmitter ATA
Control
AT7-3

TMR [7]

0

Resets transceiver when high. Transceiver can also be reset
by RESET, without affecting [TRES].

Advance Transmitter TCR [4]
Active

0

When high, TX-ACT is advanced one half bit time so that the
transmitter can generate 5.5 line quiesce pulses.

Transceiver RESet

Auxilliary
Transceiver Control

ATR [7-3]

XXXXX

In 5250 modes. Controls the time TX-ACT is held after the last
fill bit.
AT7-3

TX-ACT Hold Time (ILs)

00000
00001
00010

0
0.5
1

!-

!-

11111

15.5

FB7-0

Fill Bits

FBR [7-0] XXXXXXXX The value in this register contains the 1's complement of the
number of additional 5250 fill bits selected.

OWP

Odd Word Parity

TCR [3]

0

Controls transmitter word parity.
OWP
0
1

Receiver
Control

TCLK

00
OCLK
01
OCLK/2
10
OCLK/4
11
X-TCLK
OCLK is the frequency of the on-chip oscillator, or the
externally applied clock on input X1. X-TCLK is the external
transceiver clock input.

Word Parity
Even
Odd

TF10-8 Transmit FIFO

TCR [2-0]

TIN

Transmitter INvert

TMR [3]

AT7-0

Auxilliary
Transceiver Control

ATR [7-0] XXXXXXXX In 5250 modes, [AT2-0] contains the station address. In 8-bit
modes, [AT7 -0] contains the station address.

RF10-8 Receiver FIFO

TSR [2-0]

000
0

XXX

[OWP], [TF10-8] and [RTF7 -0] are pushed onto the
transmit FIFO on moves to {RTR I.
When high, the transmitter serial data outputs are inverted.

Reflects the state of the most significant 3 bits in the top
location of the receive FIFO.

RIN

Receiver INvert

TMR (4)

0

When high, the receiver serial data is inverted.

RLQ

Receive Line
Quiesce

TCR (7)

1

Selects number of line quiesce bits the receiver requires
before it will indicate receipt of a valid start sequence.
RLQ Number of Line Quiesce Pulses
0
1

2
3

RPEN

RePeat ENable

TMR (5)

0

When high, the receiver can be active at the same time as the
transmitter.

SEC

Select Error Codes

TCR [6]

0

When high {ECR I is switched into {RTR) location.

2-140

7.0 CPU Registers

(Continued)

BIT DEFINITION TABLE (Continued)
TRANSCEIVER (Continued)
Table includes control and status bits only. It does not include definitions of bit fields provided for the formatting (de-formatting)
data frames. For further information see the Transceiver Section. (Continued)
Bit
Receiver
Control

SLR

Name
Select Line
Receiver

Location Reset State
TCR [5]

a

Function
Selects the receiver input source.

(Continued)

SLR

Source

a

TTL-IN
On-Chip Analog
Line Receiver

1
Transmitter
Status

Receiver
Status

TA

Transmitter Active TSR [6]

a

Reflects the state of TX-ACT, indicating that data is being
transmitted. Is not disabled by [LOOP].

TFE

Transmit FIFO
Empty

NCF [7]

1

Set high when the FIFO is empty. Cleared by writing to
(RTR).

TFF

Transmit FIFO
Full

TSR [7]

a

Set high when the FIFO is full. {RTRl must not be written
when [TFF] is high.

ACK

Poll I
ACKnowledge

NCF [1]

a

Set high when a 3270 poll lack command is decoded and
[DAV] is asserted. Cleared by reading {RTRl. Undefined in
5250 and 8-bit modes and in the first frame of 3299 modes.

DAV

Data Available

TSR [3]

a

Set high when valid data is available in (RTR land (TSR).
Cleared by reading {RTR l , or when an error is detected.

DEME

Data Error or
Message End

NCF [3]

a

In 3270 or 3299 modes asserted when a byte parity error is
detected. In 5250 asserted when the [111] station address is
decoded and [DAV] is asserted. Undefined in 8-bit modes
and first frame of 3299 modes.

LA

Line Active

NCF [5]

a

Indicates activity on the receiver input. Set high on any
transition; cleared after no input transitions for 16 TCLK
periods.

LTA

Line Turn Around

NCF [4]

a

Set high when end of message is detected. Cleared by writing
to {RTR l. writing a "1" to [LTA] or by asserting [TRES].

POLL

POLL

NCF [0]

a

Set high when a 3270 poll command is decoded and [DAV] is
asserted. Cleared by reading {RTR l. Undefined in 5250 and
8-bit modes and in the first frame of 3299 modes.

RA

Receiver Active

TSR [4]

a

Set high when a valid start sequence is received. Cleared
when either an end of message or an error is detected.

RAR

Received
Auto-Response

NCF [2]

a

Set high when a 3270 Auto-Response message is decoded
and [DAV] is asserted. Cleared by reading {RTRl. Undefined
in 5250 and 8-bit modes and in the first frame of 3299 modes.

RE

Receiver

TSR [5]

a

Set high when an error is detected. Cleared by reading {ECR l
or by asserting [TRES].

RFF

Receive FIFO
Full

NCF [6]

a

Set high when the receive FIFO contains 3 received words.
Cleared by reading {RTR l.

2-141

..'_________Jlllll

C~D ~

XACK

' ....________f

...J/

,

' _--_

....- - - - - - ' /

'

....
...../
....._IA ____PC_______________________________________________________________

LCL _______

~

IWR
AD::~R~IC::::»----------~(C::::::!R~IC:::::::»---------((::~R~IC:::
TLiF/9336-89

(b) Remote Write Timing (RAE = 0)

1+._1-___+\115-8
1+"!-_"'__

-1~17

-0

TLiF/9336-90

(c) I to AD Connectivity
FIGURE 20. Generic IMEM Access

2·147

~

-=:I'
-=:I'

CO)

co
a..

C

r-----------------------------------------------------------------------,
8.0 Remote Interface and Arbitration System
In addition, WAIT can delay the rising edge of XACK indefinitely. One T-state after XACK rises, (RIC) will once again
be active on AD. Timing is similar for a Remote Write. AD is
in TRI-STATE while LCL is high. LCL is asserted for a minimum of three T-states, but can be extended by instruction
wait states and the WAIT pin. IWR clocks the instruction
into memory during the write of the high byte. The Instruction Address (PC) is incremented about one T-state after
LCL falls on a high byte access for both Remote Reads and
Writes.

A Buffered Read prevents the BCP CPU from using the bus
during the time RP is allocated the buses. This time period
begins when LCL rises and ends when REM-RD is removed. If the REM-RD is asserted longer than the minimum
Buffered Read execution time (four T-states), then the BCP
may be unnecessarily prevented from using the buses.
Therefore, if there are no overriding reasons to use the Buffered Read Mode, the Latched Read Mode is preferable.

Soft-loading Instruction Memory is accomplished by first
setting the BCP Program Counter to the starting address of
the program to be loaded. The Memory Select bits are then
set to IMEM. BCP instructions can then be moved from the
Remote Processor to the BCP-Iow byte, high byte-until
the entire program is loaded.

There are three Remote Write Modes-two require buffers
and one requires latches. The timing for the writes utilizing
buffers are shown in Figure 22. The Slow Buffered Write (a)
is handshaked in the same manner as the Buffered Read
and thus has the same timing. The Fast Buffered Write has
similar timing to the Latched Read. This timing similarity exists because the BCP terminates the remote access without
waiting for the RP to deassert REM-WR.

INTERFACE MODES
The BCP will support TRI-STATE buffers or latches between the Remote Processor and the BCP. The choice between buffers and latches depends on the type of system
that is being interfaced to. Latches will help the faster system from slowing to the speed of the slower system. Buffers
can be used if the Remote Processor (RP) requires that
data be handshaked between the systems.

In both cases, XACK falls a short delay after REM-WR falls
and LCL rises when the RP is given the buses. One T-state
after LCL rises, INT-WRITE falls. The termination in the
Slow Buffered Write mode keys off REM-WR rising, as
shown in Figure 22{a). INT-WRITE rises a prop-delay later
and LCL falls on the next rising edge of the CPU-CLK. The
Fast Buffered Write, shown in Figure 22{b), begins the Termination Phase with the rising edge of XACK. INT-WRITE
rises at the same time as XACK, and LCL falls one T-state
later. The BCP can begin a local access one T-state after
IC[ transitions.

Figure 21 shows the timing of Remote Reads via a buffer (a)
and a latch (b) (called a Buffered Read and Latched Read).
The main difference in these modes is in the Termination
Phase. The Buffered Read handshakes the data back to the
RP. When the BCP deasserts XACK, data is valid and the
RP can deassert REM-RD. Only after REM-RD goes high is
LCL removed. In the Latched Read (b) XACK rises at the
same time, but the Termination Phase completes without
waiting for the rising edge of REM-RD. One half T-state after XACK rises, INT-READ rises and one half T-state later
LCL falls. The BCP can use the buses one T -state after LCL

A Fast Buffered Write is preferable to the Slow Buffered
Write if RP's write cycles are slow compared to the minimum Fast Buffered Write execution time. The Fast Buffered
Write assumes, though, that data is available to the BCP by
the time INT-WRITE rises.

~

fo

REM - RD

/

XACK

ill

I

/

'--\.

Arbitration

Access

I

/

---.I

'-Y

\

INT- READ

(Continued)

falls. The minimum time (no wait states, no arbitration delay)
the BCP CPU could be prevented from using the bus is four
T-states in the Latched Read Mode.

\

/

\

Termination

Arbitration

TLiF/9336-91

Access

Termination
TL/F/9336-92

(a) Buffered Read

(b) Latched Read
FIGURE 21. Read from Remote Processor

2-148

8.0 Remote Interface and Arbitration System

(Continued)

XACK

LCL

---Arbitration

Termination

Access

TL/F/9336-93

(a) Slow Buffered Write

'r

1

~~------~/~-------

' _---

_---JI

.....

''--_---'I
Arbitration

Access

Termination

TL/F/9336-94

(b) Fast Buffered Write
FIGURE 22. Buffered Write from Remote Processor
In both Buffered Write Modes, XACK is asserted to wait the
RP. The Latched Write Mode makes it possible for the RP to
write to the BCP without getting waited. The timing for the
LatChed Write Mode is shown in Figure 23. When the Remote Processor writes to the BCP, its address and data
buses are externally latched on the rising edge of REM-WR.
Even though REM-WR has been asserted XACK does not

switch. The BCP only begins remote access execution after
the trailing edge of REM-WR. Since the RP is not requesting
data back from the BCP, it can continue execution without
waiting for the BCP to complete the remote access. After
REM-WR is deasserted, WR-PEND is taken low to prevent
overwrite of the latches. A minimum of two T-states later
LCL switches. AD, A, and the external address latch go into
TRI-STATE, allowing the latches which contain the remote
address and data to become active. If the RP attempts to
initiate another access before the current write is complete,
XACK is taken low to wait the RP and the address and the
data are safe because WR-PEND prevents the latches from
opening. The Access Phase ends when INT-WRITE rises
and the data is written. One T-state later, LCL falls and one
T-state after that WR-PEND rises. If another access is
pending, it can begin in the next T-state. This is indicated by
XACK rising.

XACK

LCL

---\----'

Arbitration

Access Phase

A minimum BCP/RP interface utilizes four TRI-STATE buffers or latches. A block diagram of this interface is shown in
Figure 24. The blocks A, B, C, and D indicate the location of
buffers or latches. Blocks A and B isolate 16 bits of the RP's
address bus from the BCP's Data Address bus. Two more
blocks, C and D, bidirectionally isolate 8 bits of the RP's
data bus from the BCP AD bus.

Termination
TL/F/9336-95

FIGURE 23. Latched Write from Remote Processor

2-149

~r-----------------------------------------------------~
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8.0 Remote Interface and Arbitration System

(Continued)

11.

C

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____________________________

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IMEM

BCP
DMEM

ADDR

REMOTE
PROCESSOR

t---------------......J
RA15-0
8

DATA

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RD7-0
TLIF/9336-96

FIGURE 24. Minimum BCP/Remote Processor Interface
The BCP Remote Arbitrator State Machine (RASM) must
know what hardware interfaces to the RP in order to time
the remote accesses correctly. To accomplish this, three
Interface Mode bits in {RIC 1 are used to define the hardware interface. These bits are the Latched Write bit [LW],
the Latched Read bit [LR] and the Fast Buffered Write bit
[FBW].

7

6

IBIS I SS

5

4

3

@il§JiiJ

2

o

ST I MSI I MSO I

Interface Mode Bits
O-Buffered Read
I-Latched Read

o 0 -Slow Buffered Write
1 0 -Fast Buffered Write
X O-Latched Write
All combinations of Remote Reads or Writes with buffers or
latches can be configured via the Interface Mode bits. A
Buffered Read is accomplished by using a buffer for block D
and setting [LR] = O. Conversely, using a latch for block D
and setting [LR] = 1 configures the RASM for Latched
Reads. Using buffers for blocks A, B, and C and setting
[LW] = 0 allows either a Slow or Fast Buffered Write. Setting [FBW] = 0 configures RASM for a Slow Buffered Write
and [FBW] = 1 designates a Fast Buffered Write. A
Latched Write is accomplished by using latches for blocks
A, B, and C and setting [LW] = 1.

2-150

EXECUTION CONTROL
The BCP can be started and stopped in two ways. I! the
BCP is not interfaced to another processor, it can be started
by pulsing RESET low while both REM-RD and REM-WR
are low. Execution then begins at location zero. If there is a
Remote Processor interfaced to the BCP, a write to {RIC 1
which sets the start bit [STRT] high will begin execution at
the current PC location. Writing a zero to [STRT] stops execution after the current instruction is completed. A SingleStep is accomplished by writing a one to the Single-Step bit
[SS] in {RIC l. This will execute the instruction at the current
PC, increment the PC, and then return to idle. [SS] returns
low after the single-stepped instruction has completed.
Two pins (WAIT and LOCK) and one register bit [LOR] can
also affect the BCP CPU or RIAS execution. I! WAIT is taken low the required set-up time before the last read or write
T-state (before T2), the read or write cycle will be extended
until WAIT is removed. LOCK prevents local accesses of
Data Memory. I! LOCK is asserted a hal! T-state before T 1,
further local accesses will be prevented by waiting the Timing Control Unit. [LOR] prevents remote accesses when asserted. The Timing Control Unit (TCU) is the BCP CPU sub
system responsible for timing each instruction. Once [LOR],
located in {ACR l. is set high, further remote accesses are
suspended.
Though the BCP runs independently of RlAS there is some
interaction between the two systems. [LOR] is one such

8.0 Remote Interface and Arbitration System
interaction. In addition, two bits allow the BCP CPU to keep
track of remote accesses. These bits are the Remote Write
bit [RW] and the Remote Read bit [RR], and are located in
(CCR[6-5]l. Each bit goes high when its respective remote
access to DMEM reaches its Termination Phase. Once one
of these bits has been set, it will remain high until a "1" is
written to that bit to reset it low.

(Continued)

timing diagram. The RASM states listed correspond to the
flow charts. The Timing Control Unit states are described in
the CPU Timing portion of the data sheet.
Buffered Read
The unique feature of this mode is the extension of the read
until REM-RD is deasserted. The complete flow chart for the
Buffered Read mode is shown in Figure 25. Until a Remote
Read is initiated (RAE*REM-RD true), the state machine
(RASM) loops in state RSA. If [lOR] is set high, RASM will
loop in RSA indefinitely. If the BCP CPU needs to access
Data Memory at this time (and lOCK is high), it can still do
so. A local access is requested by the Timing Control Unit
asserting the local Bus Request (lCl-BREQ) signal. A local
bus grant will be given by RASM if the buses are not being
used (as is the case in RSA).
XACK is taken low as soon as RAE*REM-RD is true, regardless of an ongoing local access. RASM will move into
RSs on the next clock after RAE*REM-RD is true and there
is no local bus request. No further local bus requests will be
granted until the remote access is complete and RASM returns to RSA.
On the next CPU-ClK, RASM enters RSe and lCl is taken
high along with XACK. The wait state counters, ilw and iow,
are loaded in this state from [lW1-0] and [DW2-0], respectively, in (DCR l. The A bus (and AD if the access is to Data
Memory) now goes into TRI-STATE and the Access Phase
begins.

DETAILED TIMING

In this section, the operation of the Remote Arbitration State
Machine (RASM), is described in detail. Discussed, among
other things, are the sequence of events in a remote access, arbitration of the data buses, timing of external signals, when inputs are sampled, and when wait states are
added. Each of the five Interface Modes is described in
functional state machine form. Although each interface
mode is broken out in a separate flow chart, they are all part
of a single state machine (RASM). Thus the first state in
each flow chart is actually the same state.
The functional state machine form is similar to a flow chart,
except that transitions to a new state (states are denoted as
rectangular boxes) can only occur on the rising edge of the
internal CPU clock (CPU-ClK). CPU-ClK is high during the
first half of its cycle. A state box can specify several actions,
and each action is separated by a horizontal line. A signal
name listed in a state box indicates that that pin will be
asserted high when RASM has entered that state. Signals
not listed are assumed low.
Note: This sometimes necessitates using the inversion of the external pin

The state machine can move into one of several states depending on the state of CMD and [MS1-0] on the next
clock. XACK and lCl are still asserted in all the possible
next states. If CMD is high, the access is to (RIC l and the
next state will be RS01. Since the default state of AD is
(RIC l. it will not transition in this state.

name). This same rule applies to the A and AD buses. By default,

these buses are active. The A bus will have the upper byte of the last
used data address.

The AD bus will display (RICl. When one of these buses
appears in a state box, the condition specified will be in
effect only during that state. Decision blocks are shown as
diamonds and their meaning is the same as in a flow chart.
The hexagon box is used to denote a conditional state-not
synchronous with the clock. When the path following a decision block encounters a conditional state, the action specified inside the hexagon box is executed immediately.

The five other next states all have CMD low and depend on
the Memory Select bits. If [MS1-0] is 10 or 11 the state
machine will enter either RS02 or RS03 and the low or high
bytes of the Program Counter, respectively, will be read.
[MS1-0] = 00 designates a Data Memory access and
moves RASM into RS04. READ will be asserted in this state
and A and AD continue to be at TRI-STATE. This allows the
Remote Processor to drive the Data Memory address for
the read. Since DMEM is subject to wait states, RSo4 is
looped upon until all the wait states have been inserted.

Also provided is a memory arbitration example in the form of
a timing diagram for each of the five modes. These examples show back to back local accesses punctuated by a
remote access. Both the state of RASM and the Timing
Control Unit are listed for every clock at the top of each

2-151

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FIGURE 25. Flow Chart of Buffered Read Mode

HASM state

RS...

RS...

RS A

RS...

RSB

RSC

RSO

RSO

RSE

R5 E

RS E

RS E

RSr

RS...

RS...

RS...

RS...

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T2

T,

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TWr

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TWr

TWr

TWr

TWr

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TUF/9336-27

Register Configuration:
-One Wait-State Programmed for Data-Memory
-Zero Wait-States Programmed for Instruction-Memory
-{RICl Contents: XXXOX100
-[LOR] = 0

Other BCP Control Signals:
RAE
=0
CMD
=0
REM-WR =1
LOCK
=1

FIGURE 26_ Buffered Read of Data Memory by Remote Processor

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8.0 Remote Interface and Arbitration System

(Continued)
state machine (RASM) loops in state RSA. If [LOR) is set
high, RASM will loop in RSA indefinitely. If the BCP CPU
needs to access Data Memory at this time (and LOCK is
high), it can still do so. A local access is requested by the
Timing Control Unit asserting the Local Bus Request
(LCL-BREQ) signal. A local bus grant will be given by RASM
if the buses are not being used (as is the case in RSA).
XACK is taken low as soon as RAE*REM-RD is true, regardless of an ongoing local access. RASM will move into
RSs on the next clock after RAE*REM-RD is asserted and
there is no local bus request. No further local bus requests
will be granted until the BCP enters the Termination Phase.
If the BCP CPU initiates a Data Memory Access after RSA,
the Timing Control Unit will be waited and the BCP CPU will
remain in state TWr until the Remote Access reaches the
Termination Phase.
On the next clock, RASM enters RSc and LCL is asserted
along with XACK. The wait state counters, ilW and iow, are
loaded in this state lrom [lW1-0) and [DW2-0), respectiveIy, in (OCR). The A bus (and AD il the access is to Data
Memory) now goes into TRI-STATE and the Access Phase
begins.
The state machine can move into one 01 several states depending CMD and [MS1-0) on the next clock. XACK and
LCL are still asserted in all the possible next states. II CMD
is high, the access is to (RIC) and the next state will be
RS01. Since the delault state 01 AD is (RIC), it will not
transition in this state. The live other next states all have
CMD low and depend on the Memory Select bits.
II [MS1-0) is 10 or 11 the state machine will enter either
RS02 or RS03 and the low or high bytes of the Program
Counter, respectively, will be read.
[MS1-0) = 00 designates a Data Memory access and
moves RASM into RS04' READ will be asserted in this state
and A and AD continue to be at TRI-STATE. This allows the
Remote Processor to drive the Data Memory address for
the read. Since DMEM is subject to wait states, RS04 is
looped upon until all the wait states have been inserted.
The last possible Memory Selection is Instruction Memory,
[MS1-0) = 01. The two possible next states lor the IMEM
access depend on if RASM is expecting the low byte or high
byte. Instruction words are accessed low byte then high
byte and RASM powers up expecting the low Instruction
byte. The internal Ilag that keeps track of the next expected
Instruction byte is called the High Instruction Byte flag (HIB).
If HIB is low, the next state is RS05 and the low instruction
byte is MUXed to the AD bus. If HIB is "1" , the high instruction byte is MUXed to AD and RS06 is entered if HIB = 1.
An IMEM access, like a DMEM access, is subject to wait
states and these states will be looped on until all programmed instruction memory wait states have been inserted.

The last possible Memory Selection is Instruction Memory,
[MS1-0) = 01. The two possible next states for an IMEM
access depend on if RASM is expecting the low byte or high
byte. Instruction words are accessed low byte then high
byte and RASM powers up expecting the low Instruction
byte. The internal flag that keeps track of the next expected
Instruction byte is called the High Instruction Byte flag (HI B).
If HIB is low, the next state is RS05 and the low instruction
byte is MUXed to the AD bus. If HIB is "1 ", the high instruction byte is MUXed to AD and RS06 is entered if HIB = 1.
An IMEM access, like a DMEM access, is subject to wait
states and these states will be looped on until all programmed instruction memory wait states have been inserted.
All the RSo states eventually move to their corresponding
RSE states on the clock after the wait state conditions, if
any, are met. The RSE states are looped upon until
RAE*REM-RD is deasserted and WAIT is high. LCL is still
high in this state and A remains in TRI-STATE. AD will also
stay in TRI-STATE il the access was to DMEM. XACK is
taken back high to indicate that data is now valid on the
read. II XACK is connected to a Remote Processor wait pin,
it is no longer waited and can now terminate its read cycle.
This state begins the Termination Phase. The action specilied in the conditional box is only executed while RAE*REMRD is asserted-a clock edge is not necessary.
On the CPU-CLK after RAE*REM-RD is deasserted, RASM
enters RSF, where LCL is high and the TRI-STATE condition in RSE remains in effect. The next clock brings the state
machine back to RSA state where it will loop until another
Remote Access is initiated. If the access was to IMEM, then
the last action 01 the remote access belore returning to RSA
is to switch HIB and increment the PC il the high byte was
read.
The example in Figure 26 shows the BCP executing the first
01 two consecutive Data Memory reads when REM-RD goes
low. In response, XACK goes low waiting the remote processor. At the end of the first instruction, although the BCP
begins its second read by taking ALE high, the RASM now
takes control of the bus and takes LCL high at the end of
T1· A one T-state delay is built into this transfer to ensure
that READ has been deasserted belore the data bus is
switched. The Timing Control Unit is now waited, inserting
remote access wait states, TWr, as RASM takes over.
The remote address is permitted one T-state to settle on the
BCP address bus before READ goes low, XACK then returns high one T-state plus the programmed Data Memory
wait state, TWd later, having satislied the memory access
time. The Remote Processor will respond by removing
REM-RD to which the BCP in turn responds by removing
READ. Following the removal 01 READ, the BCP waits till
the end 01 the next T-state before taking LCL low, again
ensuring that the read cycle has concluded before the bus
is switched. Control is then returned to the Timing Control
Unit and the local memory read continues.

All the RSo states move to their corresponding RSE states
on the CPU-CLK after wait state conditions are met and
WAIT is high. LCL is asserted in all RSE states and A remains in TRI-STATE (and AD if the access is to Data Memory). XACK returns high in this state, indicating that data is
valid so that it can be externally latched. The action specific
to each RSo state remains in effect during the first half of
the RSE cycle (Le. READ is asserted in the first half of
RSE4). This hall T-state of hold time is provided to guarantee data is latched when XACK goes high. This state begins
the Termination Phase.

Latched Read

This mode differs from the Buffered Read mode in the way
the access is terminated. A latched Read cycle ends after
the data being read is valid and the termination doesn't wait
for the trailing edge of REM-RD. Therefore the Arbitration
and Access Phases of the Latched Read mode are the
same as for the Buffered Read mode. The complete flow
chart for the Latched Read mode is shown in Figure 27.
Until a Remote Read is initiated (RAE*REM-RD true), the
2-154

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TL/F/9336-98

FIGURE 27. Flow Chart of Latched Read Mode

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RASII state

RSA

RSA

T,

TX

leU state

RS A

RSA

RSa

TWd

T2

T,

RSe

RS D

TWr

RSD

TWr

RS E

TWd

TWr

RSG

RS,

TX

TWr

RSG
TWd

RSA

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BCP INT. OP. - - - - - - - - '
TL/F/9336-30

Register Configuration:
-One Wait-State Programmed for Data-Memory
-Zero Wait-States Programmed for Instruction-Memory
-{RICI Contents: XXX1X100
-[LOR] = 0

Other BCP Control Signals:
RAE
=0
CMD
=0
REM-WR =1
LOCK
=1

FIGURE 28. Latched Read of Data Memory by Remote Processor

8.0 Remote Interface and Arbitration System
On the next clock the state machine will enter RSF and LCL
will be deasserted. Once the state machine enters RSF, the
Remote Processor is no longer using the buses and the
BCP CPU will be granted the buses if LCL-BREQ is asserted. If a local bus request is made, a local bus grant will be
given to the Timing Control Unit. If the preceding access
was a read of IMEM, then HIB is switched and if the access
was to the high byte of IMEM then the PC is incremented. If
RAE·REM-RD is deasserted at this point, the next clock will
bring RASM back to RSA where it will loop until another
Remote Access is initiated. RSG is entered if RAE*REM-RD
is still true. RASM will loop in RSG until RAE*REM-RD is no
longer active at which time the state machine will return to
RSA·
In Figure 15, the BCP is executing the first of two Data
Memory reads when REM-RD goes low. In response, XACK
goes low, waiting the Remote Processor. At the end of the
first instruction, although the BCP begins its second write by
taking ALE high, the RASM now takes control of the bus
and deasserts LCL at the end of T 1. A one T-state delay is
built into this transfer to ensure that READ has been deasserted before the data bus is switched. The Timing Control
Unit is now waited, inserting remote access wait states,
TWR, as RASM takes over.
The remote address is permitted one T-state to settle on the
BCP address bus before READ goes low, XACK then returns high one T-state plus the programmed Data Memory
wait state, TWd later, having satisfied the memory access
time. READ returns high a half T -state later, ensuring sufficient hold time, followed by LCL being reasserted after an
additional half T -state, transferring bus control back to the
BCP. The Remote Processor responds to XACK by removing REM-RD, although by this time the BCP is well into its
own memory read.

(Continued)

TRI-STATE and the Access Phase begins. The state machine can move into one of several states, depending on
the state of CMD and [MS1-0), on the next clock. XACK
and LCL are still asserted in all the possible next states. If
CMD is high, the access is to [RIC} and the next state will
be RSD1. The path from AD to [RIC} opens in this state.
The five other next states all have CMD low and depend on
the Memory Select bits. If [MS1-0] is 10 or 11 the state
machine will enter either RSD2 or RSD3 and the low or high
bytes of the Program Counter, respectively, will be written.
[MS1-0] equal to 00 designates a Data Memory access
and moves RASM into RSD4. WRITE will be asserted in this
state and A and AD continue to be atTRI-STATE. This allows the Remote Processor to drive the Data Memory address and data buses for the write. Since OM EM is subject
to wait states, RSD4 is looped upon until all the programmed
data memory wait states have been inserted.
The last possible Memory Selection is Instruction Memory,
[MS1-0] = 01. The two possible next states for IMEM depend on whether RASM is expecting the low byte or high
byte. Instruction words are accessed low byte, then high
byte and RASM powers up expecting the low Instruction
byte. The internal flag that keeps track of the next expected
Instruction byte is called the High Instruction Byte flag (HI B).
If HIB is low, the next state is RSD5 and the low instruction
byte is written into the holding register, ILAT. If HIB is "1",
the high instruction byte is moved to 115-8 and the value in
ILAT is moved to 17-0. At the same time, IWR rises, beginning the write to instruction memory. An IMEM access, like a
DMEM access, is subject to wait states and these states will
be looped on until all programmed Instruction Memory wait
states have been inserted.
All the RSD states eventually move to their corresponding
RSE states on the clock after the wait state conditions, if
any, are met. The RSE states are looped until RAE·REMWR is deasserted and WAIT is high. LCL is still asserted in
this state, but XACK is taken back high to indicate that the
remote access can be terminated. If XACK is connected to
a Remote Processor wait pin, it can now terminate its write
cycle. This state begins the Termination Phase. The action
specified in the conditional box is only executed while
RAE*REM-WR is asserted-a clock edge is not necessary.

Slow Buffered Write
The timing for this mode is the same as the Buffered Read
mode. The complete flow chart for the Slow Buffered Write
mode is shown in Figure 29. Until a Remote Write is initiated
(RAE*REM-WR true), the state machine (RASM) loops in
state RSA. If [LOR) is set high, RASM will loop in RSA indefinitely. If the BCP CPU needs to access Data Memory at this
time (and LOCK is high), it can still do so. A local access is
requested by the Timing Control Unit asserting the Local
Bus Request (LCL-BREQ) signal. A local bus grant will be
given by RASM if the buses are not being used (as is the
case in RSA).
XACK is taken low as soon as RAE·REM-WR is true, regardless of an ongoing local access. RASM will move into
RSs on the next clock after RAE·REM-WR is asserted and
there is no local bus request and [LOR) = O. No further
local bus requests will be granted until the remote access is
complete and RASM returns to RSA. If the BCP CPU initiates a Data Memory access after RSA, the Timing Control
Unit will be waited and the BCP CPU will remain in state TWr
until completion of the remote access.

On the CPU-CLK after RAE·REM-WR is deasserted, RASM
enters RSF. where LCL is asserted and the BCP A and AD
buses are still in TRI-STATE. The next clock brings the state
machine back to RSA state where it will loop until another
Remote Access is initiated. If the access was to IMEM. then
the last action of the remote access before returning to RSA
is to switch HIB and increment the PC if the high byte was
read.
In Figure 30, the BCP is executing the first of two consecutive Slow Buffered Writes to Data Memory when REM-WR
goes low. In response, XACK goes low. waiting the Remote
Processor. At the end of the first instruction, although the
BCP begins its second write by taking ALE high, RASM now
takes control of the bus and deasserts LCL at the end of T 1.
A one T -state delay is built into this transfer to ensure that
WRITE has been deasserted before the data bus is
switched. The Timing Control Unit is now waited, inserting
remote access wait states. TW" as RASM takes over.

On the next CPU-CLK, RASM enters RSe and LCL is asserted along with XACK. The wait state counters, ilw and
iDW, are loaded in this state from (iW1-0) and [DW2-0],
respectively, in [DCR}. The A and AD buses now go into

2-157

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, II'U-';)I"'t "."11 , RS£l

'"<:

~

lOW = n[0W2-0]

'IW= n[1W1-0J

TRI-STATE A. AD I RSC
[

TL/F/9336-99

FIGURE 29. Flow Chart of Slow Buffered Write Mode

0)

b
RASM stat.

RS A

RSA

RS A

RS A

T1

Tx

TWd

T2

TCU stat.

RS B

T1

RS C

RS D

RS D

RS[

RS[

RS[

RS[

RS r

RS A

RS A

RS A

RS A

RS A

::D

TWr

TWr

TWd

TWr

TWr

TWr

TWr

TWr

TWr

Tx

TWd

T2

T1

--

CD

3

o

CLK-OUT

CD

::::s
CD

REM-WR

~

LCL

II

D)

~

n

CD
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XACK

::::s
D.
~

WRITE

~

cr

~
~

ALE

~

D)

ADDR1~~~~ ~

LOCAL DATA

01

o::::s·

xOOOWl/OOOO7l/llllX

en

REMOTE DATA)

-

~

CO

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LOCAL ADDRESS

REMOTE ADDRESS

CD

LOCAL ADDRESS

3

REMOTE BUS
ADDRESS

DATA

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REMOTE ADDRESS

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I
I
L- LOCAL MEMORY WRITE ----.J

REMOTE DATA

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I :!

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3-

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c

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,

L

REMOTE WRITE

LOCAL MEMORY WRITE

~
TL/F/9336-28

Register Configuration:

Other BCP Control Signals:

-One Wait-State Programmed for Data-Memory
-Zero Wait-States Programmed for Instruction-Memory
-{RIC) Contents: XXOX0100
-[LOR) = 0

RAE
CMD
REM-RD
LOCK

=0
=0
=1
=1

FIGURE 30. Slow Buffered Write to Data Memory by Remote Processor

Vttt8dQ

8.0 Remote Interface and Arbitration System
The remote address is permitted one T-state to settle on the
BCP address bus before WRITE goes low, XACK then returns high one T-state plus the programmed Data Memory
wait state, TWd later, having satisfied the memory access
time. The Remote Processor will respond by removing
REM-WR to which the 8CP in turn responds by removing
WRITE. Following the removal of WRITE, the BCP waits till
the end of the next T-state before asserting LCL, again ensuring that the write cycle has concluded before the bus is
switched. Control is then returned to the Timing Control Unit
and the local memory write continues.

(Continued)

lows the Remote Processor to drive the Data Memory address and data buses for the write. Since DMEM is subject
to wait states, RS04 is looped upon until all the wait states
have been inserted.
The last possible Memory Selection is Instruction Memory,
[MS1-0] = 01. The two possible next states for IMEM depend on whether RASM is expecting the low byte or high
byte. Instruction words are accessed low byte then high
byte and RASM powers up expecting the low Instruction
byte. The internal flag that keeps track of the next expected
Instruction byte is called the High Instruction Byte flag (HIB).
If HIB is low, the next state is RS05 and the low instruction
byte is written into the holding register, ILAT. If HIB is "1",
the high instruction byte is moved to 115-8 and ILAT is
moved to 17 -0. At the same time IWR rises, beginning the
write to instruction memory. An IMEM access, like a DMEM
access, is subject to wait states and these states will be
looped on until all programmed instruction memory wait
states have been inserted.

Fast Buffered Write
The timing for the Fast Buffered Write mode is very similar
to the timing of the Latched Read. The major difference is
the additional half clock that AD is active in the Latched
Read mode that is not present in the Fast Buffered Write
mode. The Fast Buffered Write cycle ends after the data is
written and the termination doesn't wait for the trailing edge
of REM-WR. Therefore the Arbitration and Access Phases
of the Fast Buffered Write mode are the same as for the
Latched Read mode.

All the RSo states converge to state RSE on the next CPUCLK after wait state conditions are met and WAIT is high.
LCL is asserted in all RSE states and A and AD remain in
TRI-STATE as well. XACK returns high in this state, indicating that the data is written and the cycle can be terminated
by the RP. This state begins the Termination Phase.

The complete flow chart for the Fast Buffered Write mode is
shown in Figure 31. Until a Remote Write is initiated
(RAE*REM-WR true), the state machine (RASM) loops in
state RSA. If [LOR] is set high, RASM will loop in RSA indefinitely. If the BCP CPU needs to access Data Memory at this
time (and LOCK is high), it can still do so. A local access is
requested by the Timing Control Unit asserting the Local
Bus Request (LCL-BREQ) signal. A local bus grant will be
given by RASM if the buses are not being used (as is the
case in RSA).

On the nex1 clock the state machine will enter RSF and LCL
will be deasserted. Once the state machine enters RSF, the
Remote Processor is no longer using the buses and the
BCP CPU can make an access to Data Memory by asserting
LCL-BREQ. If a local bus request is made, a local bus grant
will be given to the Timing Control Unit. If the preceding
access was a write of IMEM, then HIB is switched and if the
access was to the high byte of IMEM then the PC is incremented. If RAE*REM-WR is deasserted at this point, the
next clock will bring RASM back to RSA where it will loop
until another Remote Access is initiated. RSG is entered if
RAE*REM-WR is still true. RASM will loop in RSG until
RAE*REM-WR is no longer active at which time the state
machine will return to RSA.

XACK is taken low as soon as RAE*REM-WR is true, regardless of an ongoing local access. RASM will move into
RSB on the next clock after RAE*REM-WR is asserted and
there is no local bus request. No further local bus requests
will be granted until the BCP enters the Termination Phase.
If the BCP CPU initiates a Data Memory Access after RSA,
the Timing Control Unit will be waited and the BCP CPU will
remain in state T Wr until the Remote Access reaches the
Termination Phase.

In Figure 32, the BCP is executing the first of two Data
Memory writes when REM-WR goes low. In response,
XACK goes low, waiting the Remote Processor. At the end
of the first instruction, although the BCP begins its second
write by taking ALE high, RASM now takes control of the
bus and deasserts LCL at the end of T 1. A one T -state delay
is built into this transfer to ensure that WRITE has been
deasserted before the data bus is switched. Timing Control
Unit is now waited, inserting remote access wait states, TWr,
as RASM takes over.

On the next CPU-CLK, RASM enters RSe and LCL is asserted along with XACK. The wait state counters, ilW and
iow, are loaded in this state from [IW1-0] and [DW2-01,
respectively, in (DCR). The A and AD buses now go into
TRI-STATE and the Access Phase begins.
The state machine can move into one of several states depending on the state of CMD and [MS1-0] on the next
clock. XACK and LCL are still asserted in all the possible
next states. If CMD is high, the access is to (RIC) and the
next state will be RS01. The path from AD to (RIC) opens in
this state.

The remote address is permitted one T-state to settle on the
BCP address bus before WRITE goes low, XACK then returns high one T-state plus the programmed Data Memory
wait state, TWd later, having satisfied the memory access
time. WRITE returns high at the same time, and one T-state
later LCL is reasserted, transferring bus control back to the
BCP. The remote processor responds to XACK by removing
REM-WR, although by this time the BCP is well into its own
memory write.

The five other nex1 states all have CMD low and depend on
the Memory Select bits. If [MS1-0] is 10 or 11 the state
machine will enter either RS02 or RS03 and the low or high
bytes of the Program Counter, respectively, will be written.
[MS1-0] = 00 deSignates a Data Memory access and
moves RASM into RS04. WRITE will be asserted in this
state and A and AD continue to be at TRI-STATE. This ai-

2-160

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i

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LCL

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,

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TRI-STATE A. AD I RSC
I

TLIF/9336-AO

FIGURE 31. Flow Chart of Fast Buffered Write Mode

Vtt£8dO

DP8344A
RASM stat.

RSA

RSA

RS A

RSA

RSB

RS C

RS O

RS O

RSE

RS F

RSG

RS H

RS A

RSA

RS A

Tl

TX

TWd

T2

Tl

TWr

TWr

TWd

TWr

TWr

TWx

TWd

T2

Tl

T2

TCU stat.

CD

o

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~

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ADDRESS

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REMOTE DATA

I

I

A~~~~~

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LOCAL DATA

'Xll!ll)(

LOCAL ADDRESS

REMOTE ADDRESS

I

!llX

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X LOCAL ADDRESS X

X

~
(I)

LOCAL DATA)

XZIZI/ZlOV

LOCAL ADDRESS

REMOTE BUS

*r-.Z~Z~Zr,/r,Z"'/"'/"'Z"'/"'Z"'O""

I

DATA

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REMOTE DATA

' - - - - - LOCAL MEMORY WRITE - - - - '

)

~ DATA MEMORY WRITE BY HOST -.l ~ LOCAL MEMORY WRITE.--J L

BCP INT. OP.

~
Tl/F/9336-29

Register Configuration:

Other BCP Control Signals:

-One Wait-State Programmed for Data-Memory
-Zero Wait-States Programmed for Instruction-Memory
-(RIC) Contents: XX1X0100
-[LOR] = 0

RAE
CMD
REM-RD
LOCK

=0
=0
=1
=1

FIGURE 32_ Fast Buffered Write to Data Memory by Remote Processor

'§
~

I

REMOTE ADDRESS

CD

3

"
<::

~

8.0 Remote Interface and Arbitration System

(Continued)

RASM powers up expecting the low Instruction byte. The
internal flag that keeps track of the next expected Instruction byte is called the High Instruction Byte flag (HIB). If HIB
is low, the next state is RSF5 and the low instruction byte is
written Into the holding register, ILAT. If HIB is "I", the high
instruction byte is moved to 115-8 and the value in ILAT is
moved to 17 -0. At the same time IWR rises and the write to
Instruction Memory is begun. An IMEM access, like a
DMEM access, is subject to wait states and these states will
be looped on until all programmed instruction memory wait
states have been inserted.
All the RSF states converge to a single decision box that
tests WAIT. If WAIT is low then the state machine loops
back to RSF, otherwise RASM will move on to RSG. LCL
and WR-PEND are still asserted in this state but the actions
specific to the RSF states have ended (i.e. WRITE will no
longer be asserted).
The next CPU-CLK moves RASM into RSH, the last state in
the state machine. LCL is no longer asserted, but
WR-PEND is still low. XACK will be taken low if a Remote
Access is initiated. If the just completed access was to
IMEM, HIB will be switched. Also, the PC will be incremented if the high byte was written. A local access will be granted if LCL-BREQ is asserted in this state.

Latched Write
This mode executes a write without waiting the Remote
Processor-XACK isn't normally taken low. The complete
flow chart for the Latched Write mode is shown in Figure 33.
Until a Remote Write is initiated (RAE*REM-WR true), the
state machine (RASM) loops in state RSA. If the BCP CPU
needs to access Data Memory at this time (and LOCK is
high), it can still do so. A local access is requested by the
Timing Control Unit asserting the Local Bus Request
(LCL-BREQ) signal. A local bus grant will be given by RASM
if the buses are not being used (as is the case in RSA).

RASM will move into RSs on the next clock after
RAE*REM-WR is asserted. XACK is not taken low
and therefore the RP is not waited. The state machine will
loop in RSs until the RP terminates its write cycle-until
RAE*REM-WR is no longer true. The external address and
data latches are typically latched on the trailing edge of
REM-WR. A local bus request will still be serviced in this
state.
Next, RASM enters RSc and WR-PEND is asserted to prevent overwrite of the external latches. Since the RP has
completed its write cycle, another write or read can happen
at any time. Any Remote Read cycle (RAE*REM-RD) or
Remote Write cycle (RAE*REM-WR) occurring after the
state machine enters RSc will take XACK low. A local access initiated before or during this state must be completed
before RASM can move to RSo. Once RSo is entered,
though, no further local bus requests will be granted until
the BCP enters the Termination Phase. If the BCP CPU initiates a Data Memory Access after RSc, the Timing Control
Unit will be waited and the BCP CPU will remain in state
TWr, until the RASM enters RSH.
On the first clock where there is no local bus request the
state machine enters RSE. WR-PEND and LCL continue to
be asserted in this state and the data and instruction wait
state counters, iow and ilW, are loaded from [DW2-0] and
[IW1-0], respectively, in {DCR}. Any remote accesses now
occurring will take XACK low and wait the Remote Processor.

If another Remote Write is pending, the state machine takes
the path to RSs where that write will be processed. A pending Remote Read will return to the RSA in either the Buffered or Latched Read sections (not shown in Figure 33) of
the state machine. And if no Remote Access is pending, the
machine will loop in RSA until the next access is initiated.
In Figure 35, the BCP is executing the first of two Data
Memory writes when REM-WR goes low. The BCP takes no
action until REM-WR goes back high, latching the data and
making a remote access request. The BCP responds to this
by taking WR-PEND low. At the end of the first instruction
although the BCP begins its second write by taking ALE
high, RASM now takes control of the bus and deasserts
LCL at the end of T 1. A one T-state delay is built into this
transfer to ensure that WRITE has been deasserted before
the data bus is switched. Timing Control Unit is now waited,
inserting remote access wait states, TWr, as RASM takes
over.
The remote address is permitted one T -state to settle on the
BCP address bus before WRITE goes low. WRITE then returns high one T-state plus the programmed Data Memory
wait state, TWd later, having satisfied the memory access
time, and one T-state later LCL is reasserted, transferring
bus control back to the BCP.

The state machine will move into one of several states on
the next clock, depending on the state of CMD and
[MS1-0]. WR-PEND and LCL are still asserted in all the
possible next states. If CMD is high, the access is to {RIC}
and the next state will be RSF1. The path from AD to {RIC}
opens in this state.
The five other next states all have CMD low and depend on
the Memory Select bits. If [MS1-0] is 10 or 11 the state
machine will enter either RSF2 or RSF3 and the low or high
bytes of the Program Counter, respectively, will be loaded.
[MS1-0] = 00 designates a Data Memory access and
moves RASM into RSF4. WRITE will be asserted in this
state and A and AD continue to be at TRI-STATE. This allows the Remote Processor to drive the Data Memory address and data for the write. Since DMEM is subject to wait
states, RSF4 is looped upon until all the wait states have
been inserted.
The last possible Memory Selection is Instruction Memory,
[MS1-0] = 01. The two possible next states for IMEM depend on if RASM is expecting the low byte or high byte.
Instruction words are accessed low byte then high byte and

In this example, REM-WR goes low again during the remote
write cycle which, since WR-PEND is still low, causes XACK
to go low to wait the Remote Processor. XACK and
WR-PEND go back high at the same time as LCL goes low,
allowing the second data byte to be latched on the next
trailing edge of REM-WR.
The BCP is now shown executing a local memory write, with
remote data still pending in the latch. At the end of this
instruction, the BCP begins executing a series of internal
operations which do not require the bus. RASM therefore
takes over and, without waiting the Timing Control Unit, executes the Remote Write.

2-163

DP8344A

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TRI-STATE A, AD I RS[

i

TLIF /9336-A 1

FIGURE 33. Flow Chart of Latched Write Mode

HASM
TCU

stat.
stat.

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BCP BUS

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ADDRESS

DATA

REMOTE

ADDR~

A

I

REMOTE ADDRESS

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-

L - LOCAL MEMORY WRITE ---.J L

3-

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BCP INT. OP.-.J

L

1

.

BCP INT. OP•.-.J
TLiF/9336-31

Register Configuration:
-One Wait-State Programmed for Data-Memory
-Zero Wait-States Programmed for Instruction-Memory
-{RICl Contents: XXXX1100
-[LOR] = 0

Other BCP Control Signals:
RAE
=0
CMD
=0
REM-RD =1
LOCK
=1

FIGURE 34_ Latched Write to Data Memory by Remote Processor

Ytt&8dO

9.0 Remote Interface Reference
If the remote system and the BCP request data
memory access simultaneously, the BCP will win
first access. If the locks ([LOR], LOCK) are not set,
the remote system and BCP will alternate access
cycles thereafter.
On power-up/reset, MS1, 0 pOints to instruction
memory.

REMOTE INTERFACE CONFIGURATION REGISTER
This register can be accessed only by the remote system.
To do this, CMD and RAE must be asserted and the [LOR]
bit in the ACR register must be low.

76543210

IBIS ISS IFW ILR ILW ISTRT IMS1 IMSO IRIC
Bidirectional Interrupt Status ... Mirrors the state
of 1M3 (lCR bit 3), enabling the remote system to
poll and determine the status of the BIRO 110.
When BIRO is an output, the remote system can
change the state of this output by writing a one to
BIS. This can be used as an interrupt acknowledge, whenever BIRO is used as a remote interrupt.

SIS

SS

Single-5tep ... Writing a 1 with STRT low, the BCP
will single-step by executing the current instruction
and advancing the PC.

FW

Fast Write ... When high, with LW low, selects fast
write mode for the buffered interface. When low
selects slow write mode.

LR

Latched Read ... When high selects latched read
mode, when low selects buffered read mode.
Latched Write ... When high selects latched write
mode, when low selects buffered write mode.
STaRT . .. The remote system can start and stop
the BCP using this bit. On power-up/reset this bit is
low (BCP stopped). When set, the BCP begins executing at the current Program Counter address.
When cleared, the BCP finishes executing the current instruction, then halts to an idle mode.

LW
STRT

10.0 Transceiver
INTRODUCTION

The transceiver section operates as an on-chip, independent peripheral, implementing all the necessary formatting
required to support the physical layer of the following serial
communications protocols:
• IBM 3270 (including 3299)
• IBM 5250
• NSC general purpose a-bit
The CPU and transceiver are tightly coupled through the
CPU register space, the transceiver appearing to the CPU
as a group of special function registers and three dedicated
interrupts. The transceiver consists of separate transmitter
and receiver logic sections, each capable of independent
operation, communicating with the CPU via an asynchronous interface. This interface is software configurable for
both polled and interrupt-driven interaction, allowing the
system designer to optimize the BCP for the specific application.
The transceiver connects to the line through an external line
interface circuit which provides the required DC and AC
drive characteristics appropriate to the application. A block
diagram of such an interface is shown in Figure 35. An onchip differential analog comparator, optimized for use in a
transformer coupled coax interface, is provided at the input
to the receiver. Alternatively, if an external comparator is
necessary, the input signal may be routed to the DATA-IN
pin.
The transceiver has several modes of operation. It can be
configured for Single line, half-duplex operation in which the
receiver is disabled while the transmitter is active Alternatively, both receiver and transmitter can be active at the
same time for multi-channel (such as repeater) or loopback
operation. The transceiver has both internal and external
loopback capabilities, facilitating testing of both the software and external hardware. At all times, both transmitter
and receiver operate according to the same protocol definition.

In some applications, where there is no remote
system, or the remote system is not an intelligent
device, it may be desirable to have the BCP powerup/reset running rather than stopped at address
OOOOH. This can be accomplished by asserting
REM-RD, REM-WR and RESET, with RAE de-asserted.
MS1,O Memory Select 1,0 ... These two bits determine
what the remote system is accessing in the BCP
system, according to the following table:
MS1

MSO

Selected Function

0
0
1
1

0
1
0
1

Data Memory
Instruction Memory
Program Counter (Low Byte)
Program Counter (High Byte)

THE PROTOCOLS

In all protocols, data is transmitted serially in discrete messages containing one or more frames, each representing a
single word of information. Biphase (Manchester II) encoding is used, in which the data stream is divided into discrete
time intervals (bit-times) denoted by a level transition in the
center of the bit-time. For the IBM 3270, 3299 and NSC
general purpose a-bit protocols, a mid-bit transition from low
to high represents a biphase "1", and a mid-bit transition
from high to low represents a biphase "0". For the 5250
protocol, the definition of biphase logic levels is exactly reversed, i.e. a biphase "1" is represented by a high to low

The BCP must be idle for the remote system to
read/write Instruction memory or the Program
Counter.
All remote accesses are treated the same (independent of where the access is directed using MSO
and MS1), as defined by the configuration bits LW,
LR, FW.

2-166

.-----------------------------------------------------------------------.0
."
C»
10.0 Transceiver (Continued)
w

t

BCP

-

DATA- OUT

~

Transmitter

Une
Driver

DATA- DLY

T

TX-ACT

I

CPU

......

k~
-h

Receiver

r-r-Une
Interface
Circuit

Transmission
medium

+ALG-IN

-ALG-IN

/+ DATA-IN"'"

-

Optional External
Comparator
TLlF/9336-33

FIGURE 35. System Block Diagram, Showing Details of the Line Interface

and ends with an ending sequence, as shown in Figures
36(b) and (e). Each 12-bit frame begins with a sync bit (81)
followed by an 8-bit data byte (MS8 first), a 2-bit control
field, and the frame delimiter bit (812), representing even
parity on the previous 11 bits. The bit rate on the coax line is
2.3587 MHz.

transition. Depending on the bit sequence, there mayor
may not be a transition on the bit-time boundary. The biphase encoding of a simple bit sequence is illustrated in
Figure 36(a).
Each transmission begins with a unique start sequence
comprising 5 biphase encoded 1's, (referred to as "line
quiesce pulses") followed by a 3 bit-time code violation and
the sync bit of the first frame; Figure 36(b). The first bit of
any frame is the sync bit, a biphase "1". The frame is then
formatted according to the requirements of the protocol. If a
multi-frame message is being transmitted, additional frames
are appended to the end of the first frame-except for the
5250 protocol, where there may be an optional number of
"fill bits" (biphase "0") between each frame.

IBM 3299
Adding 3299 multiplexers to the 3270 environment requires
an address to be transmitted along with each message from
the controller to the multiplexer. The IBM 3299 Terminal
Multiplexer protocol provides this capability by defining an
additional 8-bit frame as the first frame of every message
sent from the controller, as shown in Figure 37(e). This
frame contains a 3-bit address (bits 82-84) along with the
normal sync and word parity bits.

Depending on the protocol, when all data has been transmitted, the end of a message will be indicated either by the
transmission of an ending sequence, or (for 5250) simply by
the cessation of transitions on the differential line. The ending sequence consists of a single biphase "0" followed by a
low to high transition on the bit-time boundary and two bittimes with no transitions (mini-code violation), Figure 36(e).

Following the address frame, the rest of the message follows standard 3270 convention. The bit rate is the same as
standard 3270; 2.3587 MHz.
IBM 5250
The framing format of the IBM 5250 twinax protocol is
shown in Figure 38, for both single and multi·frame messages. Each message begins with the starting sequence
shown in Figure 36(b), and ends with 3 fill bits (biphase "0").
A 16-bit frame is employed, conSisting of a sync bit (815);
an 8-bit data byte (87-814) (LS8 first); a 3-bit station address field (84-86); and the last bit (83) representing even
word parity on the previous 12 bits. Following the parity bit,
3 biphase 0 fill bits (80-82) are transmitted. Following
these required fill bits, up to 240 additional fill bits can be
inserted between frames before the next sync bit and the
start of the next frame of a multi-byte message. The bit rate
on the twinax line is 1 MHz.

The various protocol framing formats are shown in Figures
37 through 39. The diagrams use a bit pattern drawing convention which, for clarity, shows the bit-time boundaries but
not the biphase transitions in the center of the bit times. The
timing relationship between the biphase encoded bit stream
and the bit pattern diagrams is consistent with Figure 36.
IBM 3270
The framing format of the IBM 3270 coax protocol is shown
in Figures 37(a) and (b), for both single and multi·frame
messages. Each message begins with a starting sequence

2-167

10.0 Transceiver

(Continued)
A 10-bit frame is employed, consisting of the sync bit (81);
an 8-bit data byte (82-89) (LS8 first); and the last bit of the
frame (810) representing even word parity on the previous
nine bits. For multiplexed applications, the first frame can be
designated as an address frame, with all 8 bits available for
the logical address. (See General Purpose 8-bit Modes in
this Chapter.)

NSC General Purpose 8·Blt
The framing format of the general purpose 8·bit protocol is
shown in Figure 39, for both single and multi·frame messages. It is identical to that used by the National Semiconductor DP8342 transmitter and DP8343 receiver chips.
Each message begins with a starting sequence and ends
with an ending sequence, as shown in Figures 36(b) and (c).
(a) Blphase Encoding
bft times

(c) Ending Sequence

345

bft times

blphase transmlsslcn

blphase transmission

bft pettam _+-O-,!,-.....JI'-+-O-,!,-_O-+_
TL/F 19336-35

TL/F/9336-34

(b) Starting Sequence

bft times

1

line quince pulses
2 3 4 5

blphase transmlsslcn
bft pettem
TL/F/9336-36

FIGURE 36. Blphase Encoding

2-168

10.0 Transceiver (Continued)
(a) 3270 Single-Byte Message
Data byte
06 05 04 03 02

01

Frame

TL/F/9336-37

(b) 3270 Multi-Byte Message
Data byte
06 05 04

Additional Frame.

,

03 02

01

,--------'----,

00

C/O Par Sync Par

B

B12 Bl

r

First Frame
Sync 07 06 05 04

03 02

End sequence }-

DO

01

R C/O Par

Additional Frame.

TL/F/9336-38

(c) 3299 Controller/Multiplexer Message
Data byte
Par Synd 07 06 05 04

Additional Frames (If any)

03 02

01

~

DO '

C/O Par Sync Par
B-En-d-se-q-ue-n-ce"'}-

~-J:~~~~:~~~~~~~~
Address Frame

Frame
TL/F/9336-39

FIGURE 37. 3270/3299 Protocol Framing Format

(a) 5250 Single-Byte Message
Station
addre..

Data byte
01

02 03

04 05 06

oi' AO

Al

Fill bit.

A2 Par 0

0

0

Frame

TLlF/9336-40

(b) 5250 Multi-Byte Message
Station
addr...

Oata byte

Required
flll bits

Optional
flll bits

Last frame

00---0"'---'
'Sync 07 1 1 1 Par 0 D D
~____~~~~~~~~-n-J~A-J~-n~'L-~~-n~~J~J~~~
01

02 03

04 05 06

07" AO

AI

A2' Par

Sync DO

01

02 03

04 05

06

r

07 AD

~

End of Message
Delimiter

AI A2 Par

D

Fill bits

D

Additional Frames
TLlF/9336-41

FIGURE 38. 5250 Protocol Framing Format

2·169

10.0 Transceiver (Continued)
(a) 8-Bit Single-Byte Message
Data byte
01 02 03 04 05 06

oi Par

Frame

TL/F/9336-42

(b) 8-Bit Multi-Byte Message

.

Data byte

01 02 03 04 05 06 07 Par Sync Par
Bl
First Frame

B

End sequence }-

f

01 02 03 04 05 06 07 Par

Additional Frames

TL/F/9336-43

FIGURE 39. General Purpose 8-Bit Protocol Framing Format
FUNCTIONAL DESCRIPTION

Since the TCLK source can be asynchronous with respect
to the CPU clock, the CPU/Transceiver interface can be
asynchronous. All flags from the Transceiver are therefore
latched at the start of all instructions, and parallel data is
transferred through 3 word FIFOs in both the transmitter
and receiver.

A block diagram of the transceiver, revealing external inputs
and outputs and details of the CPU interface as shown in
Figure 39. The transmitter and receiver are largely independent of each other, sharing only the clock, reset and protocol select signals. The transceiver is mapped into the CPU
register space, thus the status of the transceiver can always
be polled. In addition, the CPU/Transceiver interface can be
configured for an interrupt-driven environment. (See Transceiver Interrupts in this Chapter.)

Protocol selection is controlled by three Protocol Select
bits, [PSO-21 in the Transceiver Mode Register, {TMR}
(see Table XXVI). Enough flexibility is provided for the BCP
to operate in all required positions in the network. It is not
possible for the transmitter and receiver to operate with different protocols at the same time. The protocol mode
should only be changed when both transmitter and receiver
are inactive.

Both transmitter and receiver are reset by a common Transceiver Reset bit, [TRES], allowing the CPU to independently
reset the transceiver at any time. The Transceiver is also
reset whenever the CPU reset is asserted, including the required power-up reset. The transmitter and receiver are
clocked by a common Transceiver Clock, TCLK, at a frequency equal to eight times the required serial data rate.
TCLK can either be obtained from the on-chip oscillator divided by 1, 2 or 4, or from an external clock applied to the
X-TCLK pin. TCLK selection is controlled by two Transceiver Clock Select bits, [TCS 0-11 located in the Device Control Register, {OCR}.

If both transmitter and receiver are connected to the same
line, they should be configured to operate sequentially (halfduplex). In this mode, an active transmitter will disable the
receiver, preventing simultaneous operation of transmitter
and receiver. If the transmitter is loaded while the receiver is

2-170

10.0 Transceiver (Continued)
TABLE XXVI. Protocol Mode Definition
PS2-0

Protocol Mode

Comments

000
001

3270
3299 Multiplexer

010

3299 Controller

01 1
100

3299 Repeater
5250

101
110

5250 Promiscuous
a-Bit

111

a-Bit Promiscuous

Standard IBM 3270 protocol.
Receiver expects first frame to be address frame. Transmitter uses standard
3270, no address frame.
Transmitter generates address frame as first frame. Receiver expects standard
3270, no address frame.
Both transmitter and receiver operate with first frame as address frame.
Non-promiscuous mode. IDAV] asserted only when first frame address matches
{ATRI.
IDAV] asserted on all valid received data without regard to address field.
General-purpose a-bit protocol with first frame address. Non-promiscuous mode.
IDAV] asserted only when first frame address matches {NAR I.
IDAV] asserted on all valid received frames.
CPU regist...

DATA-IN

,..------+1X- ACT

...........,I-~--+DATA- DLY

. . .___
r-~

+ALG-IN
-ALG-IN

....I",.~~

__

~DATA-OUT

loopback
TL/F/9336-44

KEY TO REGISTERS
RTR

Receive/Transmit Register

ATR

Auxiliary Transceiver Register

TSR

Transceiver Status Register

NCF

Network Command Register

TCR

Transceiver Command Register

FBR

Fill-Bit Register

TMR

Transceiver Mode Register

OCR

Device Control Register

FIGURE 39. Block Diagram of Transce ver, Showing CPU Interface

2-171

10.0 Transceiver

(Continued)

actively processing an incoming signal, the receiver will be
disabled and flag the CPU that a "Receiver Disabled While
Active" error has occurred. (See Receiver Errors in this
Chapter.) On power-up/reset the transceiver defaults to this
half-duplex mode.
By asserting the Repeat Enable flag [RPEN], the receiver is
not disabled by the transmitter, allowing both transmitter
and receiver to be active at the same time. This feature
provides for the implementation of a repeater function or
loopback for test purposes.

it must be loaded before I RTR}. A multi-frame transmission
is accomplished by sequentially loading the FIFO with the
required data, the transmitter taking care of all necessary
frame formatting.
If the FIFO was previously empty, indicated by the Transmit
FIFO Empty flag [TFE] being asserted, the first word loaded
into the FIFO will asynchronously propagate to the last location in approximately 40 ns, leaving the first two locations
empty. It is therefore possible to load up the FIFO with three
sequential instructions, at which time the Transmit FIFO Full
flag [TFF] will be asserted. If I RTR} is written while [TFF] is
high, the first location of the FIFO will be over-written and
data will be destroyed.
When the first word is loaded into the FIFO, the transmitter
starts up from idle, asserting TX-ACT and the Transmitter
Active flag [TA], and begins generating the start sequence.
After a delay of approximately 32 TCLK cycles (4 biphase
bit times), the word in the last location of the FIFO is loaded
into the encoder and prepared for transmission. If the FIFO
was full, [TFF] will be de-asserted when the encoder is
loaded, allowing an additional word to be loaded into the
FIFO.
When the last word in the FIFO has been loaded into the
encoder, [TFE] goes high, indicating that the FIFO is empty.
To ensure the continuation of a multi-frame message, more
data must then be loaded into the FIFO before the encoder
starts the transmission of the last bit of the current frame
(the frame parity bit for 3270, 3299, and 8-bit modes; the
last of the three mandatory fill bits for 5250). This maximum
load time from [TFE] can be calculated by subtracting two
from the number of bits in each frame of the respective
protocol, and multiplying that result by the bit rate. This
number represents the best case time to load-the worst
case value is dependent on CPU performance. Since the
CPU samples the transceiver flags and interrupts at instruction boundaries, the CPU clock rate, wait states (from programmed wait states, asserting the WAIT pin, or remote access cycles), and the type of instruction currently being executed can affect when the flag or interrupt is first presented
to the CPU.
If there is no further data to transmit (or if the load window is
missed), the ending sequence (if any) is generated and the
transmitter returns to idle, de-asserting TX-ACT and [TA].

The transmitter output can be connected to the receiver
input, implementing a local (on-chip) loopback, by asserting
[LOOP]. [RPEN] must also be asserted to enable both the
transmitter and receiver at the same time. With [LOOP] asserted, the output TX-ACT is disabled, keeping the external
line driver in TRI-STATE. The internal flag [TA] is still enabled, as are the serial data outputs.
Transmitter
The transmitter accepts parallel data from the CPU, formats
it according to the desired protocol and transmits it as a
serial biphase-encoded bit stream. A block diagram of the
transmitter logic is shown in Figure XR-6. Two biphase outputs, DATA-OUT, DATA-DLY, and the external line driver
enable, TX-ACT, provide the data and control signals for the
external line interface circuitry. The two biphase outputs are
valid only when TX-ACT is asserted (high) and provide the
necessary phase relationship to generate the "pre-emphasis" waveform common to all of the transceiver protocols.
See Figure 14 for the timing relationships of these outputs
as well as the output of the line interface.
The capability is provided to invert DATA-OUT and DATADLY via the Transmitter Invert bit, [TIN], located in the
Transceiver Mode Register. DATA-DLY is always initialized
to the inverse state of [TIN]. In addition, the timing relationship between TX-ACT and the two biphase outputs can be
modified with the Advance Transmitter Active control,
[ATA]. When [ATA] is cleared low (the power-up condition),
the transmitter generates exactly five line quiesce bits at the
start of each message, as shown in Figure 40. If [ATA] is
asserted high, the transmitter generates a sixth line quiesce
bit, adding one biphase bit time to the start sequence transmission. The line driver enable, TX-ACT, is asserted halfway
through this bit time, allowing an additional half-bit (with no
pre-emphasis) to preceed the first line quiesce of the transmitted waveform. This modified start sequence is depicted
in the dotted lines shown in Figure 40.

Data should not be loaded into the FIFO after the transmitter is committed to ending the message and before the [TA]
flag is deasserted. If this occurs, the load will be missed by
the transmitter control logiC and the word(s) will remain in
the FIFO. This condition exists when [TA] and [TFE] are
both low at the same time, and can be cleared by resetting
the transceiver (asserting [TRESl) or by loading more data
into the FIFO, in which case the first frame(s) transmitted
will contain the word(s) left in the FIFO from the previous
message.
Typical waveforms for transmitter operation are shown in
Figure 40.

Data is loaded into the transmitter by writing to the Receivel
Transmit Register IRTRl, causing the first location of the
FIFO to be loaded with a 12-bit word (8-bits from IRTR}
and 4 bits from the Transceiver Command Register ITCR}.
The data byte to be transmitted is loaded into I RTR}, and
ITCR} contains additional information required by the protocol. It is important to note that if ITCR} is to be changed,

2-172

10.0 Transceiver

(Continued)

dotted lines Indicate waveforms

with [ATA) set high
,....---"----,

I

I
I
I

u

I

._-----j

DATA- DLY

I
U---LJI---I

TRANSt.4ITTED
WAVEFORt.4

IIne-quiesce
bit
TLiF/9336-4S

FIGURE 40. Transmitter Output
Receiver

minimum number of line quiesce bits required by the receiv·
er logic is selectable via the Receiver Line Quiesce [RLQ)
control bit. If this bit is set high (the power·up condition),
three line quiesce bits are required; if set low, only two are
needed. Once the start sequence has been recognized, the
receiver asserts the Receiver Active flag [RA) and enables
the error detection circuitry.

The receiver accepts a serial biphase·encoded bit stream,
strips off the framing information, checks for errors and reo
formats the data for parallel transfer to the CPU. The block
diagram in Figure 41 depicts the data flow from the serial
input(s) to the FIFO's parallel outputs. Note that the FIFO
outputs are multiplexed with the Error Code Register {ECR)
outputs.

The NRZ serial bit stream is now clocked into a serial to
parallel shift register and analyzed according to the expected data pattern as defined by the protocol. If no errors are
detected by the word parity bit, the parallel data (up to a
total of 11 bits, depending on the protocol) is passed to the
first location of the FIFO. It then propagates asynchronously
to the last location in approximately 40 ns, at which time the
Data Available flag [DAV) is asserted, indicating to the CPU
that valid data is available in the FIFO.

The receiver and transmitter share the same TCLK, though
in the receiver this clock is used only to establish the sam·
piing rate for the incoming biphase encoded data. All control
timing is derived from a clock signal extracted from this
data. Several status flags and interrupts are made available
to the CPU to handle the asynchronous nature of the incoming data stream. See Figure 41 for the timing relationships
of these flags and interrupts relative to the incoming data.

Of the possible 11 bits in the last location of the FIFO, 8 bits
(data byte) are mapped into {RTR) and the remaining bits
(if any) are mapped into the Transceiver Status Register
{TSR [0-2)). The CPU accesses the data byte by reading
{ RTR), and the 5250 address field or 3270 control bits by
reading {TSR). When reading the FIFO, it is important to
note that {TSR) must be read before {RTR), since reading
{RTR) advances the FIFO. Data in the FIFO will propagate
from one location to the next in approximately 10-15 ns,
therefore the CPU is easily able to unload the FIFO with a
set of consecutive instructions.
If the received bit stream is a multi-byte message, the receiver will continue to process the data and load the FIFO.
After the third load (if the CPU has not accessed the FIFO),
the Receive FIFO Full flag [RFF) will be asserted. If there
are more than 3 frames in the incoming message, the CPU
has approximately one frame time (sync bit to start of parity
bit) to start unloading the FI FO. Failure to do so will result in
an overflow error condition and a resulting loss of data (see
Receiver Errors).
If there are no errors detected, the receiver will continue to
process the incorning frames until the end of message is
detected. The receiver will then return to an inactive state,

The input source to the decoder can be either the on-chip
analog line receiver, the DATA·IN input or the output of the
transmitter (for on-chip loopback operation). Two bits, the
Select Line Receiver [SLR) and Loopback [LOOP), control
this selection. In addition, serial data can be inverted via the
Receiver Invert [RIN) control bit.
The receiver continually monitors the line, sampling at a frequency equal to eight times the expected data rate. The
Line Active flag [LA) is asserted whenever an input transition is detected and will remain asserted as long as another input transition is detected within 16 TCLK cycles. If another transition is not detected in this time frame, [LA) will
be de-asserted. This function is independent of the mode of
operation of the transceiver; [LA) will continue to respond to
input Signal transitions, even if the transmitter is activated
and the receiver disabled.
If the receiver is not disabled by the transmitter, the decoder
will adjust its internal timing to the incoming transitions, attempting to synchronize to valid biphase·encoded data.
When synchronization occurs, the biphase clock will be extracted and the serial NRZ (Non-Return to Zero) data will be
analyzed for a valid start sequence (see Figure 36 b). The

2-173

10.0 Transceiver (Continued)
RA Interrupt

~

t

060504030201

LA RA DAY LTA -

LA

Line Active
Receiver Active
Data Available
Line Tum Arcund

DO

R

OA Interrupt

LTA Interrupt

~

~

t

OA,
Command
flags

t t

RA,
LTA

LA

TL/F/9336-46

FIGURE 41, Timing of Receiver Flags Relative to Incoming Data
clearing [RA] and asserting the Line Turn-Around flag,
[LTA] indicating that a message was received with no errors. For the 3270 and 3299 protocols, [LTA] can be used
to initiate an immediate transmitter FIFO load; for the other
protocols, an appropriate response delay time may be needed. [LTA] is cleared by loading the transmitter's FIFO, writing a one to [LTA] in the Network Command flag register, or
by asserting [TRES].

[LMBTI Loss of Mid-Bit Transition-Asserted when the
expected biphase-encoded mid-bit transition does
not occur within the expected window. Indicates a
loss of receiver synchronization.
[RDIS]

Receiver Disabled While Active-Asserted when
an active receiver is disabled by the transmitter being activated.
To determine which error has occurred, the CPU must read
[ECR). This is accomplished by asserting the Select Error
Codes control bit, [SEC] and reading [RTR). The [ECR) is
only 5 bits wide, therefore the upper 3 bits are still the output of the receive FIFO. See Figure 41. The act of reading
[ECR) resets the receiver to idle, in which case it again
monitors the incoming data stream for a new start sequence. [SEC] control bit must be de-asserted to read the
FIFO's data from [RTR).
If data is present in the FIFO when the error occurs, the
Data Available flag [DAV] is de-asserted when the error is
detected, being re-asserted when [ECR) is read. Data present in the FIFO before the error occurred is still available to
the CPU. The flexibility is provided, therefore, to read the
error type and still recover data loaded into the FIFO before
the error occurred. [TRES] the Transceiver Reset, can be
asserted at any time, clearing both Transceiver FIFOs and
the error flags.

Receiver Errors
If the Receiver Active flag, [RAJ. is asserted, the selected
receiver input source is continuously checked for errors,
which are reported to the CPU by asserting the receiver
Error flag, [RE], and setting the appropriate receiver error
flags in the Error Code Register [ECR). If a line condition
occurs which results in multiple errors being created, only
first error to be detected will be latched into [ECR). Once
an error has been detected and the appropriate error flag
has been set, the receiver is disabled, clearing [RA] and
preventing the Line Turn-Around flag and interrupt [LTA]
from being asserted. The Line Active flag [LA] remains asserted if signal transitions continue to be detected on the
input.
5 error flags are provided in [ECR):

7

6

5

4

3

I rsv I rsv I rsv I OVF I PAR
[OVF]

[PAR]
[lES]

2
liES

o

I LMBT I RDIS I

Transceiver Interrupts
The transceiver has access to 3 CPU interrupt vectors, one
each for the transmitter and receiver, and a third, the Line
Turn-Around interrupt, providing a fast turn around capability
between receiver and transmitter. The receiver interrupt is
the highest priority interrupt (excluding NMI), followed by the
transmitter and Line Turn-Around interrupts, respectively.
The three interrupt vector addresses and a full description
of the interrupts are given in Table XXVII.

Overflow Flag-Asserted when the decoder
writes to the first location of the FIFO while [RFF]
is asserted. The word in the first location will be
over-written; there will be no effect on the last two
locations.
Parity Error Flag-Asserted when a received
frame fails an even (word) parity check.
Invalid Ending Sequence Flag-Asserted during
an expected end sequence when an error occurs
in the mini code-violation. Not valid in 5250 modes.

The receiver interrupt is user-selectable from 4 possible
sources (only 3 used at present) by specifying a 2-bit field,
the Receiver Interrupt Select bits [RIS1,O] in the Interrupt
Control Register [lCR). A full description is given in Table
XXVIII.

2-174

10.0 Transceiver (Continued)
TABLE XXVII. Transceiver Interrupts
Interrupt

Vector Address

Description

Receiver
Transmitter

000100
001000

User selectable from 4 possible sources, see Table XXVIII.
Set when [TFE) asserted, indicating that the transmit FIFO is empty, cleared by
writing to (RTR). Note: [TRES) causes [TFE) to be asserted.

Line Turn-Around

001100

Set when a valid end sequence is detected, cleared by writing to (RTR) writing a
one to [LTA), or asserting [TRES). In 5250 modes, interrupt is set when the last
fill bit has been received and no further input transitions are detected. Will not be
set in 5250 or 8-bit non-promiscuous modes unless an address match was
received.

The interrupt vector is obtained by concatenating
IIBR) with the vector address as shown:

II

I

I I

I I I I I interrupt
vector address . vector

IBR

o

15
TABLE XXVIII. Receiver Interrupts
Interrupt

RIS1,O

Description

RFF+RE

00

DAV+RE

01

Not Used
RA

10
11

Set when [RFF) or [RE) asserted. If activated by [RFF), indicating that the
receive FIFO is full, interrupt is cleared by reading from I RTR). If activated by
[RE), indicating that an error has been detected, interrupt is cleared by reading
from IECR).
Set when [DAV) or [RE) asserted. If activated by [DAV), indicating that valid
data is present in the receive FIFO, interrupt is cleared by reading from I RTR). If
activated by [RE), indicating that an error has been detected, interrupt is cleared
by reading from I ECR).
Reserved for future product enhancement.
Set when [RA) asserted, indicating the receipt of a valid start sequence, cleared
by reading IECR) or IRTR).
To transmit a frame ITCR [0-3)) must first be set up with
the correct control information, after which the data byte
can be written to I RTR). The resulting composite 12-bit
word is loaded into the transmit FI FO where it propagates
through to the last location to be loaded into the encoder
and formatted for transmission.
When formatting a 3270 frame, I TCR [2)) controls whether
the transmitter is required to format a data frame or a command frame. If I TCR [2)) is low, the transmitter logic calculates odd parity on the data byte (B2-B9) and transmits this
value for B 10. If I TCR [2Jl is high, B10 takes the state of
ITCR [0)). Odd Word Parity [OWP) controls the type of
parity calculated on Bl-Bll and transmitted as B12, the
frame delimiter. If [OWP) is high, odd parity is output; otherwise even parity is transmitted. In this manner the system
designer is provided with the maximum flexibility in defining
the transmitted 3270 control bits (Bl0-812).

All receiver interrupts can be cleared by asserting [TRES).
The RFF + RE interrupt occurs only when the receive FIFO
is full (or an error is detected). If the number of frames in a
received message is not exactly divisible by 3, one or two
words could be left in the FIFO at the end of the message,
since the CPU would receive no indication of the presence
of that data. It is recommended that this interrupt be used
together with the line turn-around interrupt, whose service
routine can include a test for whether any data is present in
the receive FIFO before activating the transmitter.
Additional information is provided in Section 5.0.

3270/3299 Modes
As shown in Table XXVI, the transceiver can operate in 4
different 3270/3299 modes, to accommodate applications
of the BCP in different pOSitions in the network. The 3270
mode is designed for use in a device or a controller which is
not in a multiplexed environment. For a multiplexed network,
the 3299 multiplexer and controller modes are designed for
each end of the controller to multiplexer connection, the
3299 repeater mode being used for an in-line repeater situated between controller and multiplexer.

When data is written to I RTR), the least significant 4 bits of
ITCR) are loaded into the FIFO along with the data being
written to I RTR). The same I TCR) contents can therefore
be used for more than one frame of a multi-frame transmission, or changed for each frame.

For information on how parallel data loaded into the transmit FIFO and unloaded from the receiver FIFO maps into
the serial bit pOSitions, see Figure 42.

When a 3270 frame is received and decoded, the decoder
loads the parallel data into the receive FIFO where it propagates through to the last location and is mapped into I RTR)
and ITSR). Bits B2-811 are exactly as received; Byte Parity [BP) is odd parity on B2-89, calculated in the decoder.

2-175

10.0 Transceiver (Continued)
Reading {RTR) will advance the receive FIFO, therefore
{TSR) should be read first if this information is to be utilized.

when the receiver de-formats a 3299 address frame, the
received address bits are loaded into {RTR [2-7]); {RTR
[0-1]) and {TSR [0-2]) are undefined.

When formatting a 3299 address frame, the procedure is
the same as for a 3270 frame, with {RTR [2-7]) defining
the address to be transmitted. The only bit in {TCR) which
has any functional meaning in this mode is [OWPl. which
controls the type of parity required on 81-88. Similarly,

The POLL, POLL! ACK and TT / AR flags in the Network
Command Flag Register are valid only in 3270 and 3299
(excluding the 3299 address frame) modes. These flags are
decodes of their respective coax commands as defined in
Table XXIX. The Data Error or Message End [DEME] flag

(a) 3270 Data and Command Frames

76543210

7

6

4

ml~I~I~I~I~I~I~I~1

3

1

0

lowpi 0 18111 x Il~:ta)

T

receive

~------------~*~------------~
76543210
5

7

4

2

1

0

ml~I~I~I~I~I~I~I~1

TL/F/9336-47

(b) 3299 Address Frame

7

RTR

6

5

4

3

2

0

I 82 I 831 84 I 85 I 86 I 87 I

f

tntnsmlt and rocelye

y------.,

rr----Sync 1.0 AI 1.2 1.3

Coax tntnsmlsslon

1.4

1.5 Par

Starting Sequence

single/multi-byte me_ge

TL/F/9336-46

FIGURE 42. 3270/3299 Frame Assembly/Disassembly Procedure
TABLE XXIX. Decode of 3270 Coax Commands
Received Word
82
0
X
X

83

0
X
X

84
0
X
X

85
0
0

86
0
0
0

87
0
0
0

88

0
0

0

89
0

810
0
X
X

All flags cleared by reading I RTR I.

2-176

Flag

Description

RAR
ACK
POLL

TT / AR (Clean Status) Received
POLL/ ACK Command Received
POLL Command Received

811

0

10.0 Transceiver (Continued)
{also in the (NCFl register) indicates different information
depending on the selected protocol. In 3270 and 3299;
[DEME) is set when B10 of the received frame does not
match the locally generated odd parity on bits B2-B9 of the
received frame. This flag is not part of the receiver error
logic, it functions only as a status flag to the CPU. These
flags are decoded from the last location in the FIFO and are
valid only when [DAVI is asserted; they are cleared by reading {RTR I and should be checked before accessing that
register.

conclusion of a message the transmitter will return to the
idle state after transmitting the 3 fill bits of the last frame (no
additional fill bits will be transmitted).
As shown in Table XXVI, the transceiver can operate in 2
different 5250 modes, designated "promiscuous" and "nonpromiscuous". The transmitter operates in the same manner in both modes.
In the promiscuous mode, the receiver passes all received
data to the CPU via the FIFO, regardless of the station address. The CPU may determine which station is being addressed by reading ITSR [0-211 before reading {RTR!.
In the non-promiscuous mode, the station address field
(B4-B6) of the first frame must match the 3 least significant
bits of the Auxiliary Transceiver Register, (ATR[0-2) I, before the receiver will pass the data on to the CPU. II no
match is detected in the first frame of a mes!!age, and if no
errors were found on that frame, the receiver will reset to
idle, looking for a valid start sequence. If an address match
is detected in the first frame of a message, the received
data is passed on to the CPU. For the remainder of the
message all received frames are decoded in the same manner as the promiscuous mode.
To maintain maximum flexibility, the receiver logic does not
interpret the station address or command fields in determining the end of a 5250 message. The message typically ends
with no further line transitions after the third fill bit of the last
frame. This end of message must be distinguished from a
loss of synchronization between frames of a multi-byte
transmission condition by looking for line activity some time
after the loss of synchronization occurs. When the loss of
synchronization occurs during fill bit reception, the receiver
monitors the Line Active flag, [LAI, for up to 11 biphase bit
times (11 p.s at the 1 MHz data rate). If [LA) goes inactive at
any point during this period, the receiver returns to the idle
state, de-asserting [RA) and asserting [LTAl. II, however,
[LA) is still asserted at the end of this window, the receiver
interprets this as a real loss of synchronization and flags the
appropriate error condition to the CPU. (See the Receiver
Errors section in this Chapter.)

5250 Modes
The biphase data is inverted in the 5250 protocol relative to
3270/3299 (see the Protocol section-IBM 5250). Depending on the external line interface circuitry, the transceiver's
biphase inputs and outputs may need to be inverted by asserting the [RIN) (Receiver INvert) and [TIN) (Transmitter
INvert) control bits in {TMR!.
For information on how data must be organized in {TCR I
and {RTR I for input to the transmitter, and how data extracted from a received frame is organized by the receiver
and mapped into {TSR I and {RTR l. See Figure 43.
To transmit a 5250 message, the least significant 4 bits of
{TCR I must first be set up with the correct address and
parity control information. The station address field (B4-B6)
is defined by {TCR[0-2)l. and [OWPI controls the type of
parity (even or odd) calculated on B4-B15 and transmitted
as B3. When the a-bit data byte is written to {RTR I, the
resulting composite 12-bit word is loaded into the transmit
FIFO, starting the transmitter. The same {TCRI contents
can be used for more than one frame of a multi-frame transmission, or changed for each frame.
The 5250 protocol defines bits BO-B2 as fill bits which the
transmitter automatically appends to the parity bit (B3) to
form the 16-bit frame. Additional fill bits may be inserted
between frames of a multi-frame transmission by loading
the fill bit register, {FBR I, with the one's compliment of the
number of fill bits to be transmitted. A value of FF (hex),
corresponding to the addition of no extra fill bits. At the

7

RTR

654

3

2

I

0

7

I B71 881 B9IBIOUl1lB12IBI3IBI41

6

5

4

3

2

0

lowpi 84 1 85 1 86 ITeR

T

tranltnit

Twlnax tranltnlalon

Sync DO

DI

D2

D3

*

D4

D5

D6

D7

7

6

AD

AI

A2

Par

T

reoelve

7

RTR

6

543

2

I

0

I 871 881 B9IBIOUl1lB12IB13IBI41

*

543

2
I
0
IB41BSIB61TCR
TUF 19336-49

FIGURE 43. 5250 Frame Assembly/Disassembly Description

2-177

:;
== 10.0 Transceiver (Continued)
~
C

In the 5250 modes, the Data-Error-or-Message-End [DEME]
flag is a decode of the 111 station address and is valid only
when [DAVI is asserted. This function allows the CPU to
quickly determine when the end of message has occurred.
The transmitter has the flexibility of holding TX-ACT active
at the end of a 5250 message, thus reducing line reflections
and ringing during this critical time period. The amount of
hold time is programmable from 0 P.s to 15.5 p.s in 500 ns
increments, and is set by writing the selected value to the
upper five bits of the Auxiliary Transceiver Register, {ATR

not enabled in the promiscuous mode, and therefore all reo
ceived frames are passed through the receive FIFO to the
CPU. The transmitter operates in the same manner in both
modes.
The serial bit positions relative to the parallel data loaded
into the transmit FIFO and presented to the CPU by the
receiver FIFO are shown in Figure 44. To transmit a frame,
the data byte is written to {RTR I, loading the transmit FIFO
where it propagates through to the last location to be loaded into the encoder and formatted for transmission. Only
[OWP] in the {TCRI is loaded into the transmitter FIFO in
these protocol modes-{TSR [0-21l are don't cares. 810
is defined by a parity calculation on 81-89; [OWP] determines the type of parity transmitted as 810, which is odd if
[OWP] is high and even if low.

[3-711.
General Purpose 8·Blt Modes
As shown in Table XXVIII, the transceiver can operate in 2
different 8-bit modes, designated "promiscuous" and "nonpromiscuous". In the non-promiscuous mode, the first frame
data byte (82-89) must match the contents of {ATRI before the receiver will load the FIFO and assert [DAV). If no
match is made on the first frame, and if no errors were
found on that frame, the receiver will go back to idle, looking
for a valid start sequence. The address comparator logic is

7

6

When a frame is received, the decoder loads the processed
data into the receive FIFO where it propagates through to
the last location and is mapped into {RTR I. All bits are
exactly as received. Reading the data is accomplished by
reading {RTRI. {TSR [0-21l are undefined in the 8-bit
modes.

543

2

1

0

D6

D7 .....

mlnl.I~I"IEI~I~I~1

f

tranllllit and receive
Coax tran.......1on

Sync DO

Dl

D2

D3

*

D4

D5

TUF/9336-50

FIGURE 44. General Purpose 8-Blt Frame Assembly/Disassembly Procedure

2-178

r----------------------------------------------------------------,~

~~

National Semiconductor
Application Brief 33
Bill Fisher

Choosing Your RAM for the
Biphase Communications
Processor
As with most other aspects of a design, choosing RAM is a
cost vs. performance tradeoff. Maximum performance is
achieved running no wait states with fast, expensive RAM.
Slower, less expensive RAM can be used, but wait-states
must be added, slowing down the BCP. Therefore one
needs to choose the slowest RAM possible while still meeting design specifications.
The BCP has separate data and instruction static RAM,
each with their own requirements. Instruction read time, as
shown in Figure 1, is measured from when the instruction
address becomes valid to when the next instruction is
latched into the BCP. Preliminary data for read times of various clock frequencies and wait states are given in Table I.
Clock frequency/wait state combinations other than those
given in the table can be calculated by the following equation:
tl = 103 (1.5 + nl) / fcpu - 28
where tl is the Instruction Read Time (ns), nl is the number
of instruction wait states and fcpu is the clock frequency
(MHz) the CPU is running. The RAM chosen needs to have
a faster access time than the read time for the desired clock
frequency/wait-states combination.

TABLE I. Instruction Read Times (ns)
CPU Clock
Freq,(MHz)

Wait States

0

1

2

131

237

343

18.86

52

105

158

20.00

47

97

147

9.43

Data read time (Figure 2) is measured from when the data
address is valid to when data from the RAM is latched into
the BCP. Table II gives preliminary data read times. The
equation for calculating data read time is similar to instruction memory:
to = 103 (2 + no)/fcpu - 58
where to is the Data Read Time (ns), no is the number of
data wait states. Since the lower address byte (AD) is externally latched, the latch propagation delay needs to be subtracted from the available read time when determining the
required RAM access time.
Instruction RAM has the greatest effect on execution speed.
Each added instruction wait state slows the BCP by about
40%. Each added data wait state slows a data access by
33%. RAM costs are coming down, but at publication, an 8K
by 8 45 ns RAM costs in the $10 range. The same RAM with
a 100 ns access time (1 wait state) will run about $5. So
there's the tradeoff.
T2

Tl
elK-OUT

I::~::::::::::a
TLiF/9359-1

FIGURE 1. Preliminary Instruction Read Time

2-179

.

CO)
CO)

T1

III

-----

;this routine decodes the 3299 protocol device address field
;located in RTR(2-4). It is assumed that the Data Available flag
;or interrupt caused program control to transfer to this
;routine. The error and device handling routines are not shown.

JMPF
JMPB

MA,AB,NAI
S,RERR,ERRHDLR
RTR,S,B7,WRAP

1000 8424

JRMK

RTR,ROTl,MSK4

1001
1002
1003
1004
1005
1006
1007
1008
1009
100A
100B
100C
100D
100E
100F
1010

LJMP

ADDR.O

;jump to device 0 handler

LJMP

ADDR.l

;jump to device 1 handler

LJMP

ADDR.2

;jump to device 2 handler

LJMP

ADDR.3

;jump to device 3 handler

LJMP

ADDR.4

;jump to device 4 handler

LJMP

ADDR.5

;jump to device 5 handler

LJMP

ADDR.6

;jump to device 6 handler

LJMP

ADDR.7

;jump to device 7 handler

EI,RF

;return, restore flags, set GIE

OFFC
OFFD
OFFE
OFFF

AE08
DD20
8DE4
105D

CEOO
2000
CEOO
2050
CEOO
2100
CEOO
2150
CEOO
2200
CEOO
2250
CEOO
2300
CEOO
2350

EXX

;select main A, alt B banks
;if error, go to error handler
;i1' msb set, wrap data back

•
•
•
1011 AFDO

RET

;------< end of routine

>------

FIGURE 3. JRMK Code

2·182

Receiver Interrupts/Flags
for the DP8344 Biphase
Communications Processor

National Semiconductor
Application Brief 35
Tom Norcross

The DP8344 has a flag that corresponds to each of its interrupts except NMI. This allows the BCP to operate efficiently
in either an interrupt driven or polled environment and gives
the user the flexibility to combine the two. However, one
must be aware that even though the names are the same,
their controls may be different. The event that controls
when the interrupt and its corresponding flag is asserted or
cleared may not be the same. However, this is only the case
for the three receiver interrupts; the other 8344 interrupts
are set and cleared in exactly the same manner as their
associated flag. To easily discuss these subtle differences,
it should be made clear that the transceiver reset does clear
all the receiver flags and interrupts and that this will not be
mentioned when discussing the individual receiver interrupts
below.

a sync bit. However, the RA interrupt is cleared by reading
the {RTR I or {ECR I register while the RA flag is cleared by
an error or the end of the transmission. The receiver identifies the end of the transmission by detecting a mini code
violation in all protocols except 5250, and in 5250 by waiting
for the Line Active (LA) flag to time out after fill bits are
received. The data available (DA) interrupt and flag are both
asserted when a byte is present on the output of the FIFO.
However, the DA interrupt also becomes active when an
error is detected by the receiver. They are both cleared by
reading the {RTR I register until the FIFO is empty, but the
DA flag will also be cleared when an error is detected. The
situation is similar with the receive FIFO full interrupt and
flag. They are both asserted when three words are present
in the FIFO, but the RFF interrupt also becomes active
when an error is detected. Both the RFF flag and interrupt
are cleared exactly the same way by reading the RTR register.

To begin with, the receiver active (RA) interrupt and flag are
both asserted by the same event; the receiver detecting two
or three line quiescents, depending on the state of Receive
Line Quiescent (RLQ), followed by a code violation and

2-183

~
..-

.-----------------------------------------------------------------------~

~

Receiving 5250 Protocol
~ Messages with the Biphase
Communications Processor
In 5250 protocol, station address recognition and the lack of
any easily detectable ending sequence as in 3270 protocol
make the hardware and software tasks challenging. This
article discusses how to use the DP8344 in a typical 5250
environment with both the current and forthcoming revisions
of silicon.
The receiver works in two modes of operation for 5250 protocol. In promiscuous mode, the receiver accepts data for
all addresses on the network giving the user the ability to
support multiple or single sessions in one's software. The
program can simply reset the transceiver upon receiving a
station address of no interest. The received station address
is stored in the Transceiver Status Register (TSR) bits 2-0
and is valid when the data Available [DA] flag is high. The
received station address should be used prior to reading
(RTR). When (RTR) is read, the receiver FIFO advances
and the current word is replaced by the next available word.
If another word is in the FIFO, it will be reflected in (RTR)
and (TSR) in instructions there after. In nonpromiscuous
mode, the receiver only loads data in the FIFO in messages
where the first frame address matches (NAR) bits 2-0. The
receiver logic compares (NAR) bits 2-0 with the station
address received in the first frame to decide whether to load
data. However, error detection is enabled in all addresses
for all frames of a message and the software must determine how the error is to be handled.
The end of message determination should be handled in
software. The 5250 protocol requires an end of message
delimiter (a station address of 111) to be sent in the last
frame of a multiframe message or at the end of a single
frame message to the system. For single frame messages
from the system to a device, bit 14 (the first bit after the
sync bit; [RTROl) in the command frame will determine if the
message has ended. If bit 14 is off in a command frame, the
message is a single frame. Once the end of message determination is made in software, the receiver should be reset.
The receiver will flag a loss of midbit error and inhibit the
setting of the Line Turn Around [LTA] interrupt if the line is
not free of transitions for up to 3 /'-S after the last valid fill bit
is received. The [LTA] interrupt should not be used since it
mayor may not go high at the end of received messages.
By resetting the receiver at the end of the message, any
false loss of mid bit errors will be avoided.
An efficient way to decode the received address and end of
message delimiter is to use the JRMK instruction with
(TSR) as the source. By selecting to "rotate" right six positions and to 'mask' bits five through seven in (TSR), a
unique branch offset into a jump table is formed for each of
the received addresses. Assuming that [TFF] is low in
(TSR), the offset from the ADDECDR address will allow
four instruction slots for each address. By using the JMPB
and WMP instructions, all four slots are used for each address. Each branch from the table will contain the appropriate action for that particular address. The code example in
Figure 1 is the Data Available interrupt service routine with
the receiver in 5250 promiscuous mode. The code presented in this article is intended for example only and may not
be suitable in an actual working environment. GP6' is used

National Semiconductor
Application Note 517
Paul Patchen

to turn sessions on or off and has been loaded with H#08
to turn on the 011 station address and turn off all others.
Each bit in the register corresponds to a station address.
GP5' has been initialized to H#OO in the foreground program and is used to store a multiframe flag and end of message flag. The multiframe flag is set when the software has
determined that a multiframe message is being received.
The end of message flag is set when the software determines that the last frame in the message was received.
This code first checks to see whether an error or the reception of a data frame caused the interrupt. If not, a check to
see if the message is multiframe or not is done. Bit 0 of
GP5' is set high for multiframe messages. The ADDECDR
address is where the received address is decoded using the
JRMK instruction. Notice in the code that station address 3
is supported and all others ignored. By changing the value in
GP6', different station addresses can be turned "on" or
"off". The key point to make for ensuring clean operation is
to reset the transceiver once the last frame is received to
avoid any false loss of midbits errors flagged when the message ends.
With the upcoming silicon reVision, the receiver hardware in
5250 and 8BIT non promiscuous modes will reset if no address match is made (i.e. the received station address does
not match the address in the Network Address Register
( NAR )) and no errors are detected during the first frame of
the message. Error detection will be enabled during the first
frame of messages independent of the received station address. If an error is detected during the first frame, all devices will report the error. On subsequent frames, errors will
only be reported if the first frame contained a matching address. In 5250 mode, (NAR) bits 2-0 are compared to the
received address. In 8BIT mode, all (NAR) bits are compared. The receiver's end of message reset has been modified to avoid flagging false loss of midbit errors in 5250
modes of operation.
To reset cleanly at the end of the message, the receiver
hardware will look for abit time wihtout a transition (a "loss
of midbit") during the fill bit portion of the received message
as an indication that the message has ended. Once this
occurs, the receiver will reset and [LTA] will go high to flag
the CPU that the receiver has received a complete message. Since a loss of midbit during fill bits could be a real
error (i.e. not an end of message), the software will need to
check for an end of message indication in the last data byte
received. In situations where a sync bit is followed by inactivity on the line, the receiver hardware will consider the
message to be continuing and shift data in accordingly. The
receiver monitors Line Active [LA], in the Network Command Flag Register (NCF) to determine if the line has died.
[LA] goes high on any detected transition on the line and
will return low after 16 transceiver clocks of no activity. If
[LA] times out, [LTA] will go high and the receiver will reset.
Note again that the software will still need to check for an
end of message, for this could be an error situation. If [LA]
does not time out, the receiver shifts in the data and checks
for errors in the usual manner.

2-184

):10

****************DA ISR***********************************************

**
**

Foreground TMR=H#lD ICR=OlHHHHHO GP5'=H#00 GP6'=H#OB
Data available Interrupt Service Routine

DAISA:

EHH
JMPF

MA,AB,NAI
S,RERR,ERRHDLR

JMPB

GP5,S,B#000,ADDECDR

JMPB

RTR,NS,B#OOO,EOM

**
•*

;set appropriate banks.
;branch to error handler
;if error flag set.
;if multiframe, go to address
;decoder.
;check B14 in message, if
;low, single frame message
;set multiframe flag
;decode received address

ORI
H#01,GP5
JRMK
TSA,B#llO,B#Oll
JMPB
GP6,NS,B#000,RST
LJMP
AO
;jump table for all network
GP6,NS,B#001,RST
;addresses.
JMPB
LJMP
;in this configuration,
Al
JMPB
GP6,NS,B#010,RST
;address 3 is supported
LJMP
;and all others ignored
A2
JMPB
GP6,NS,B#011,RST
;after first frame.
LJMP
A3
JMPB
GP6,NS,B#100,RST
LJMP
A4
JMPB
GP6,NS,B#101,RST
LJMP
A5
JMPB
GP6,NS,B#110,RST
LJMP
A6
JMPB
GP6,NS,B#111,RST
LJMP
AEOMD
;go to end of message routine
;set end of message flag
EOM:
ORI
H#02,GP5
;go to address decoder
JMP
ADDECDR
;reset transceiver on
RST:
ORI
H#BO,TMR
;don't care addresses.
ANDI
H#7F,TMR
H#FC,GP5
;clear flags and return.
ANDI
RET
RI,RF
A3:
•• handle received data for address 3. If end of
message flag set, reset transceiver, clear flags
and return. If end of message flag not set, return.
AEOMD: •• the last frame of the message was just received,
handle data then reset transceiver, prepare to
transmit by loading and starting the timer for
frame timing, enable timer interrupt, clear
flags, return.

ADDECDR:

FIGURE 1. Multi-Session Application
loaded and started to timeout in the response window (45
± 15 ns) before starting the transmitting task.

To minimize software overhead, a new flag [DEMEl has
been added to (NCFl at bit 3 to indicate the reception of the
end of message delimiter in 5250 modes. [DEMEl will go
high when the currently accessible word in the receiver
FIFO contains the 111 address. In 3270/3299 modes,
[DEMEl will go high when local odd byte parity [TSR2l does
not match odd byte parity received [TSROl.
Some of the software overhead will not be required for the
forthcoming silicon revision. It will no longer be necessary to
reset the receiver to avoid false loss of mid bit errors at the
end of the message. The [LTAl interrupt can be used allowing the software to be interrupted when the receiving task is
complete. In the [LTAl interrupt routine, the timer can be

The code shown in Figure 2 is an example for a single session application with the receiver in the non promiscuous
5250 mode. Address 1 will be supported. The Data Available interrupt and the LTA interrupt are enabled in the foreground program. GP5' is used for software flags in the interrupt routine of a multiframe indicator in bitO and an end of
message indicator in bit1.
The [LTAl routine is not absolutely necessary. The actions
taken in the routine could have been handled in the Data
Available routine once the determination of the end of mes2-185

Z

.........•

U1

....an

~ r---------------------------------------------------------------------------------~

Z•

cr:

sage was made. As seen above, the software requirement
for the transceiver task can be totally interrupt driven allowing the processing power of the BCP to be used for other

tasks. The 1 Mbs data rate used in the 5250 protocol leaves
more CPU bandwidth available for other tasks than either
the 3270 or 3299 protocols.

************ DA ISR *************************************************

*

Foreground program TMR=H#lC ICR=OlHHHOHO GP5'=H#00 NAR=H#Ol
**
available Interrupt Service Routine
**
DAISR:
EHH
MA,AB,NAI
;set appropriate banks.
JMPF
S,RERR,ERRHDLR
;branch to error handler
;if error flag set.
JMPB
GP5,S,B#000,EOMCHK
;if multiframe, skip check
;for single frame message.
JMPB
RTR,NS,B#OOO,SEOMF
;check B14 in message, if
;low, single frame message.
ORI
H#Ol,GP5
;set multiframe flag.
JMP
DATA
SEOMF:
H#02,GP5
ORI
;set end of message flag
JMP
DATA
EOMCHK:
JMPB
NCF,S,B#Oll,SEOMF
DATA:
••• handle received data for address 1, return

* Data

************ LTA ISR ***********************************************.*

* Line Turn Around Interrupt Service Routine
LTAISR:
EHH MA,AB,NAI
JMPB GP5,NS,B#OlO,ERRCOND

**

;set appropriate banks.
;if end of message flag
;not set, error condition •
••• load and start timer to timeout at necessary time
required before transmitting, enable timer interrupt,
clear GP5' flags and LTA, return.
ERRCOND: ••• an error condition occurred in the message
(i.e. the line died after a sync bit was detected or
a loss of synchronization occurred during fill bits),
take appropriate action and return.
FIGURE 2. Single-Session Application

2-186

"Interrupts"-A Powerful
Tool of the Biphase
Communications Processor

National Semiconductor
Application Note 499
Mark Koether

When you have only 5.5 ,.,.s to respond you have to act fast.
This is the amount of time specified in the IBM 3270 Product
Attachment Information document as the maximum time allowed to respond to a message in a 3270 environment. This
5.5 ,.,.s is why the DP8344 interrupts are specifically tailored
for the task of managing a communications line and feature
very short latency times. This article contains information
that will help the user to take better advantage of the extensive interrupt capability found in the DP8344.

gram to continue working on another task while the transmitter is sending data. It is especially useful when sending a
long message. When the transmit FIFO becomes empty the
program is alerted by the TFE interrupt and may continue
the message by loading additional words into the FIFO. This
approach frees up a significant amount of processing time.
For example, after the transmit FIFO is loaded it takes the
transmitter approximately 264 transceiver clock cycles to
send the starting sequence and two data words in 3270
mode. With the CPU operating at the transceiver clock frequency, the program has approximately 264 T-states available before the TFE interrupt will occur.
Once the TFE interrupt occurs the CPU has approximately
80 transceiver clock cycles to load the transmit FIFO in order to continue a multiframe message in 3270 mode. If the
CPU is operating at the transceiver clock frequency, the
program has approximately 80 T-states to accomplish the
load operation. Since the load to the Receive/Transmit
Register, {RTR), only takes 2 T-states, 78 T-states are
available for interrupt latency and processing overhead after
the interrupt occurs.

The DP8344 has two external and four internal interrupt
sources. The external interrupt sources are the Non-Maskable Interrupt pin, (NMI), and the Bi-directional Interrupt ReQuest pin (BIRQ). A NMI is detected by the CPU when NMI
receives a falling edge. The falling edge is captured internally and the interrupt is processed when it is detected by the
CPU as described later. BIRQ can function as both an interrupt into the DP8344 and as an output which can be used to
interrupt other devices. When BIRQ is configured as an input an interrupt will occur if the pin is held low. Note that
BIRQ is not edge sensitive and if the pin is taken back high
before the interrupt is processed by the CPU then no interrupt will occur.
The internal interrupts consist of the Transmitter FIFO Empty (TFE) interrupt, the Line Turn Around (LTA) interrupt, the
Time Out (TO) interrupt, and a user selectable receiver interrupt source.
The receiver interrupt source is selected from either the Receiver FIFO Full (RFF) interrupt, the Data Available (DA)
interrupt, or the Receiver Active (RA) interrupt. The RFF
interrupt occurs when the receive FIFO is full or if the receiver detects an error condition. This interrupt enables the
user to handle packets of data as opposed to handling every data word individually. It also allows the program to
spend additional time performing other tasks. However,
since the RFF interrupt is only asserted when the receive
FIFO is full, the LTA interrupt should be used in conjunction
with RFF to allow the program to check the FIFO for additional words at the end of a message. The DA interrupt
indicates valid data is present in the receive FIFO and also
occurs if the receiver detects an error condition. It should be
used when it is desirable to handle each data word individually. The DA interrupt also allows the program to utilize the
time between receiving each data word for performing other
tasks. The RA interrupt is asserted when the receiver detects a valid start sequence. It provides the user with an
early indication of data coming into the receiver. This allows
the program time to perform any necessary overhead activity before handling the receiver data. The RA interrupt is
asserted approximately 90 transceiver clock cycles prior to
data becoming available in the receive FIFO when using
3270 mode. Consequently, if the transceiver and CPU are
operating at the same clock frequency, approximately 90
clock cycles (T -states) are available for interrupt latency
and taking care of overhead prior to handling the received
data.
A TFE interrupt occurs when the last word in the transmit
FIFO is loaded into the encoder. This interrupt allows a pro-

The LTA interrupt provides an easy means for determining
the end of a message. This allows a program to quickly
begin transmitting after the end of a reception. The LTA
interrupt indicates that the receiver detected a valid end sequence in 3270 mode of operation. In 5250 operating mode,
the LTA interrupt occurs when the last fill bit has been received and no further input transitions are detected by the
receiver. However, aLTA interrupt does not occur in 5250
or 8-bit non-promiscuous modes of operation unless an address match was decoded by the receiver.
The TO interrupt occurs when the CPU timer counts down
to zero. The timer provides a flexible means for timing
events. It is a sixteen bit counter which can be loaded by
accessing CPU registers {TMHI and {TMLI and is controlled by the [TCS], [TLD] and [TST] bits in the Auxiliary
Control Register, {ACR}.
After an interrupt occurs the event that generated it must be
handled in order to clear the interrupt. The exception to this
is NMI. Since it is falling edge triggered, it is cleared internally when the CPU processes the interrupt. The actions necessary to clear the interrupts are listed in Table I.
In the case where BIRQ is asserted, the response will be
dependent on the system design. Ordinarily, this response
would involve some hardware handshaking such as reading
or writing a specific data memory location. When internal
interrupts become asserted there are specific actions which
must be taken by a program to clear these interrupts. The
RFF interrupt is cleared when the receive FIFO is no longer
full and any errors detected by the receiver are cleared.
Data is read from the receive FIFO by reading {RTR}.
Reading the Error Code Register, {ECR I, clears any errors
detected by the receiver. The DA interrupt is cleared when
the receive FIFO is empty and any errors detected by the
receiver are cleared. The RA interrupt is cleared by reading
{RTRI or {ECR}. All three receiver interrupts are cleared
when the transceiver is reset. In many cases, resetting the
transceiver is the preferable response to an error detected

2-187

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TABLE I. Clearing Interrupts

Interrupt

How to Clear Interrupt

NMI

Internally Cleared When Recognized by the CPU.

RFF

Read {RTR] When Receive FIFO is Full.
Read {ECR] When an Error Occurs.
Read {ECR] and {RTR] When an Error Occurs
and Receive FIFO is Full.
Reset the Transceiver.
Reset the DP8344.

DA

Read {RTR] When Receive FIFO is Not Empty.
Read {ECR] When an Error Occurs.
Read {ECR] and {RTR] When an Error Occurs
and Receive FIFO is Not Empty.
Reset the Transceiver.
Reset the DP8344.

RA

Read {RTR] or (ECR).
Reset the Transceiver.
Reset the DP8344.

TFE

Write to {RTR].

LTA

Write to {RTR].
Reset the Transceiver.
Reset the DP8344.
Write a One to {NCF] Bit 4.

BIRO

System Dependent.

TO

WriteaOneto {CCR] Bit 7.
Stop the Timer.
Reset the DP8344.

by the receiver. The TFE interrupt is cleared by writing to
{RTR]. Unlike the receiver interrupts, the TFE interrupt is
asserted when the transceiver is reset. The LTA interrupt is
also cleared by writing to {RTR] or resetting the transceiver. The last internal interrupt is TO. It is cleared by writing a
one to bit 7 in the Condition-Code Register, {CCR] or by
stopping the timer. Note that the timer reloads itself and
continues to count after the interrupt has been generated
regardless of whether a one is written to bit 7 in {CCR].

was saved on the address stack at the time the interrupt
was recognized. They also provide the options of clearing or
setting [GIE] or leaving it unchanged. [GIE] is cleared when
an interrupt is recognized by the CPU in order to prevent
other interrupts from occurring during an interrupt service
routine. The [GIE] options described above facilitate enabling and disabling interrupts when returning from an interrupt service routine. The restore option is especially useful
with the NMI. Since an NMI can occur whether [GIE] is set
or cleared, the restore [GIE] option can be used in the return instruction to put [GIE] back to its state prior to the
interrupt occurring.
As the name implies, [GIE] affects all the maskable interrupts. However, in order to use any of these interrupts they
must be unmasked by changing the state of their associated
mask bit in {lCR). When set high, bits [IMO], [IM1], [1M2],
[1M3], and [IM4] in {lCR] mask the receiver interrupt, TFE
interrupt, LTA interrupt, BIRO interrupt, and TO interrupt respectively. To enable an interrupt, its mask bit must be set
low. The interrupts and associated mask bits are shown in
Table II. These bits are set high when the DP8344 is reset.
Bits [RIS1] and [RISO] in {lCR] are used to select the
source of the receiver interrupt as shown in Table III. Note
that only one of these interrupts can be active as the source
of the receiver interrupt.

With the exception of NMI, all of the interrupts are disabled
when the DP8344 is reset. In order to make use of the interrupts they must be enabled in software. Software enabling
and disabling of the interrupts is performed by changing the
state of the Global Interrupt Enable, [GIE], bit in {ACR] and
the state of the individual interrupt mask bits in the Interrupt
Control Register, {lCR).
[GIE] is a read/write register bit and so may be changed by
using any instruction that can write to {ACR]. In addition,
the RET, RETF, and EXX instructions have option fields
which can be used to alter the state of [GIE]. RET and
RETF are the return instructions in the DP8344 and EXX is
used to exchange register banks. The EXX instruction can
set or clear [GIE] as well as leaving it unchanged. The RET
and RETF instructions can restore [GIE] to the value that

2-188

TABLE II. (lCR) Interrupt Mask Bits
and Interrupt Priority
Interrupt

Mask Bit

-

NMI
RFF, DA, RA
TFE
LTA
BIRO
TO

IMO
IMI
1M2
1M3
IM4

interrupt service routine. The return instruction at the end of
the interrupt service routine would then return to the address at which the interrupt occurred. By changing (lBR) it
is possible to locate the interrupt jump table in memory
wherever it is convenient or for one program to use more
than one interrupt jump table.

Priority
Highest

TABLE IV. Interrupt Vector Generation

Lowest

TABLE III. {lCR) Receiver Interrupt Select Bits
RIS1

RISO

Receiver Interrupt
Source

0
0
1
1

0
1
0
1

RFF
DA
Reserved
RA

Interrupt

Code

NMI
RFF,DA,RA
TFE
LTA
BIRO
TO

111
001
010
011
100
101

Interrupt Vector
{lBR} Contents
15

As stated earlier, [GIE] is cleared when an interrupt is recognized by the CPU. This prevents other interrupts from occurring in the interrupt service routine. In cases where it is
desirable to allow nesting of interrupts, [GIE] should be set
high within the interrupt routine. An example of nesting interrupts is using the RA interrupt in the main program and
switching to the RFF or DA interrupt in the RA interrupt
routine. Note that the internal address stack is twelve words
deep and there is no recovery from a stack overflow. Therefore, care should be taken when nesting interrupts.

I

8

0

0

0

I

I0 0 I

4

2

Code

o

As mentioned previously, the interrupts are sampled in the
CPU prior to the start of each instruction. To be precise,
they are sampled by each falling edge of the CPU clock with
the last falling edge prior to the start of the next instruction
determining whether an interrupt will be processed. The timing of a typical interrupt event is shown in Figure 1. The
interrupt occurs during the current instruction and is sampled by the falling edge of the CPU clock. The next instruc·
tion is not operated on and its address is stored in the internal address stack. In addition, the current state of [GIE] and
the states of the ALU flags and bank positions are stored in
the internal address stack. A 2 T-state call is now executed
in place of the non-executed instruction. This call will cause
a branch to the interrupt address that is generated in the
first half of T-state Tl. [GIE] is then cleared during the first
half of T-state T2. From this description it is evident that the
shortest interrupt latency is 2.5 T-states. This assumes that
an interrupt occurs during the first half of T2 and is sampled
by the next falling edge of the CPU clock. However, a number of factors can increase the interrupt latency. If the interrupt misses the setup time to the falling edge of the last
CPU clock the response time will increase by a minimum of
2 T-states. This increase is caused by the execution of one
additional instruction. Of course, if the additional instruction
takes more than 2 T-states to execute the interrupt latency
will be greater.

When more than one interrupt is unmasked and asserted,
the CPU processes the interrupt with the highest priority
first. NMI has the highest priority followed by the receiver
interrupt, TFE, LTA, BIRO, and TO. Therefore, if DA and
BIRO were both active, DA would be processed first followed by BIRO. However, if a higher priority interrupt occurred while the DA interrupt was being handled then it
would be processed before BIRO. Each time the interrupts
are sampled, the highest priority interrupt is processed first,
regardless of how long a lower priority interrupt has been
active. Interrupt priority is summarized in Table II.
A call to the interrupt address is generated when an interrupt is detected by the CPU. The address for each interrupt
is constructed by concatenating the Interrupt Base Register,
(lBR l. contents with the individual interrupt code as shown
in Table IV. There is room between the interrupt addresses
for a maximum of four instruction words. Normally, at each
interrupt address there would be a jump instruction to an

2-189

AN-499

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T1

T1

T2

CPU ClK

Interrupt

\

Interrupt
sampled

~
~
Instruction
Address Bus _ _ _ _ _ _...J

Instruction
Bus

[GIEl

Non-executed
Instruction Address

Interrupt Vector
Address

Non-executed instruction

I

\
FIGURE 1. Minimum Interrupt Timing

first Interrupt Instruction

TliF/9361-1

:..
Running the DP8344 with wait states will also increase interrupt latency. Instruction memory wait states increase latency by increasing the length of each instruction, including the
call to the interrupt service routine. Data memory wait states
will increase interrupt latency if an interrupt must wait for an
instruction which accesses data memory to execute before
it can be processed. A less obvious factor that can increase
interrupt latency is data memory accesses by the remote
system. If the DP8344 is attempting a data memory access
and the remote system already has control of the data
memory bus, the CPU will be waited. If an interrupt occurs at
this time it will not be processed until the DP8344 is able to
complete the instruction which is accessing data memory.
This implies that a system with a lot of data memory arbitration occurring between the DP8344 and the remote system
may have a longer average interrupt latency. The worst
case interrupt latency will occur when the external

LOCK or WAIT pins are asserted. Clearly, if the CPU is
stopped by the assertion of the WAIT pin any interrupts
ocurring will not be processed until the CPU is released
from the wait state. Asserting the LOCK pin would have the
same affect if the DP8344 attempts to make a data memory
access. Note that interrupts are not disabled or cleared
when the CPU is stopped by the remote system deasserting
[STRn in the Remote Interface Configuration, [RICI, register. When the CPU is restarted any asserted interrupts will
be processed. From the above discussion it is evident that
calculating the interrupt latency is not trivial and will be dependent on the program and the system.
The interrupts on the DP8344 are powerful tools for controlling events in a time critical environment. They are one of
the many reasons why the DP8344 Bi-phase Communications Processor provides a superior solution to managing
communications interfaces.

2-191

Z

~

-

National Semiconductor
Application Note 504
Jim Margeson

DP8344 BCP Stand-Alone
Soft-Load System
INTRODUCTION
The DP8344 Biphase Communications Processor (BCP) is a
20 MHz Harvard architecture microprocessor with an onchip transmitter and receiver. The BCP can be used to implement several biphase communication protocols:
IBM 3270, IBM 3299, IBM 5250, and National's general purpose 8-bit protocol. This application note shows how

DP8344 software can be loaded from EPROM into instruction RAM. It is particularly valuable in stand-alone systems
where the BCP is not interfaced to a host processor. Possible applications include: protocol converters, multiplexers,
high-speed remote data acquisition systems and remote
process control systems.

INSTRUCTION ADDRESS

LINE
INTERFACE

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DATA ADDRESS

BCP

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TLIF/9403-1

FIGURE 1. BCP System with Host Processor

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INSTRucnoN AIlIlRESS

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A
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INSTRucnoN

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LATCH

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llEMOTE
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CONTROL
LINES

PAL
11RIB

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CONTROL
LINES

8

16K X 8
EPROM
350 no

-+
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----+

PERIPHERALS:
DIGITAL I/O
ANALOG I/O
AND/OR
UARTS
TL/F 19403-2

FIGURE 2. BCP Stand-Alone System with EPROM Soft Load Circuit

2-192

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INSTRUCTION ADDRESS

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INSTRUCTION BUS

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0:7
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40
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TLlF/9403-3

FIGURE 3. Schematic

2-193

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D.
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MB81C78A-45
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A 0:7

ADDRESS lOW
DATA MULTIPLEXED

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DATA toIEMORY
PERIPHERALS

(UARTS.
DIGITAL I/O.
AND/OR
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TL/F/9403-4

FIGURE 3. Schematic (Continued)

2-194

)0-

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WHY EPROM SOFT-LOAD?

In a stand-alone application, the BCP instruction code must
be kept in non-volatile memory. Instruction memory with
45 ns access time is required to run the BCP at full speed.

to come up stopped or to begin program execution after a
reset has occurred. If the following conditions are true when
reset is de-asserted then the processor will begin running:
RAE - (Remote Access Enable, active low) = High,
REMWR- (Remote Write, active low) = low, REMRD(Remote Read, active low) = low. Otherwise, it will come up
halted.
The PAL sequencer begins the software load by writing the
low byte of the first instruction to the remote interface. A
simplified flowchart of the sequence operation is shown in
Figure 4.
This byte comes from address OOOOH of the EPROM. The
corresponding locations of EPROM and RAM are shown in
Figure 5. The least significant address line of the EPROM is
controlled by the sequencer; the other address lines are
driven by the instruction address bus of the BCP. The instruction address bus reflects the contents of the BCP's
program counter (PC), which contains the destination of the
instruction currently being loaded. After the low byte of the
first instruction is written to the remote interface, the sequencer brings the least significant address line of the
EPROM high. Now location 0001 H of the EPROM is addressed, and the high byte of the first instruction is written to
the remote interface. At this point the BCP writes both bytes
into address OOOOH of instruction RAM, and increments its
program counter.

EPROM at this speed can be quite expensive, much more
than 45 ns RAM or 350 ns EPROM. RAM with 45 ns access
time can be used for instruction memory if a scheme is employed to load the BCP code into the RAM from slow
(350 ns), inexpensive EPROM, upon power-up.
In non-stand-alone applications, a host processor would
communicate with the BCP through the BCP's built-in remote interface (Figure 1). In such a system, BCP code
would be loaded from the host into the BCP's instruction
RAM using the remote interface. In a stand-alone system,
however, the BCP is not interfaced to a host; the program is
loaded from EPROM through the remote interface. As
shown in Figure 2 a PAL ® sequencer controls the loading of
the program, generating handshaking signals similar to
those of a typical host processor. When the load is complete, the sequencer tells the BCP to begin execution of the
program.
HOW THE SOFT-LOAD CIRCUIT WORKS

The BCP, as configured in this system, comes up halted
after reset (Figure 3). The program counter is set to zero,
and the remote interface is configured to receive 16-bit instructions in 8-bit pieces and write them into instruction
memory. The BCP has the feature that it can be configured

TLiF/9403-5

FIGURE 4. Sequencer Operation

2-195

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EPROM
Address
0
1
2
3
4

address bus. Location 0002H of the EPROM is addressed,
and the low byte of the second instruction is written to the
remote interface. The sequencer then brings the least significant address line of the EPROM high (to address location 0003H) and the high byte of the second instruction is
transferred. The BCP writes the second 16-bit instruction to
location 0001 H of instruction RAM. This process is repeated
until the last instruction is transferred.

Instruction
Memory Address

5

0
0
1
1
2
2

(Low Byte)
(High Byte)
(Low Byte)
(High Byte)
(Low Byte)
(High Byte)

•
•
•
•

•
•
•
•

•
•
•

16382
16383

8190
8191

(Low Byte)
(High Byte)

The sequencer senses that the load is complete when instruction address line 13 comes high. This occurs when the
program counter is incremented to a value of 4000H, indicating that 8K instruction words have been transferred. At
this pOint the BCP must be started. To achieve this, the
sequencer resets the BCP again, while holding RAE - high,
REMRD- low, and REMWR- low. A reset during these
conditions brings the processor up running, and also clears
the program counter. The BCP begins execution at instruction address OOOOH and the sequencer and EPROM go into
an inactive state, transparent to the software being executed. A detailed version of the sequencer flowchart is shown
in Figure 6. A hardware compiler/minimizer was used to obtain the equations shown in Figure 7. These equations were
used to program a National PAL16R6B. Typical timing
waveforms of the soft-load are shown in Figure 8.

•

FIGURE 5. EPROM to RAM Address Mapping
The first 16-bit instruction has been transferred; the second
is done in a similar manner. The sequencer brings the least
significant address line of the EPROM low again. The PC
now contains 0001 H, which is output on the instruction

2-196

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REMRD
STI
ST2
CS

EPAO
REMWR

I I ..
I I I I

--- III I

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WRITE LOW BYTE
OF INSTRUCTION

---- .: I
----- I I

------ I

TL/F/9403-B

FIGURE 6. Sequencer Flowchart

2-197

"II'

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There are several advantages to using the remote interface
to load the BCP software. If a scheme like the one in Figure
9 was used to load the program directly from EPROM to
instruction RAM, much more hardware would be required
and the access time of the RAM would need to be shorter.
Two EPROMs would have to be used instead of one because the transfer would be 16 bits wide instead of 8 bits. In
this case the BCP's program counter could not be used to

increment through the memory locations, thus an external
13-bit counter would be needed. TRI-STATE® buffers would
isolate the RAM and EPROM from the instruction data and
instruction address busses during soft-load. These buffers
would add propagation delays to memory accesses demanding that faster RAM be used. Soft-loading through the
remote interface requires fewer I.C.'s and does not degrade
the performance of the processor.

DMPAL16R6B;
SOFTLOAD
OK LOL XAOK IA13 RESET N06 N07 N08 IWR GND
IOE IBRESET IREMWR IEPAO lOS IST2 ISTl IREMRD ILOLINV VOO
IREMRD := RESET*
IREMRD*
OS*/EPAO*/REMWR
+ RESET*
ST2* OS*
IREMRD*
IREMWR
+ RESET*
IREMRD* ST1*
IREMWR
OS*
+ RESET*IA13* REMRD*/ST1*/ST2*IOS*/EPAO* REMWR
:= RESET*
REMRD*/ST1* ST2*IOS
1ST!
+ RESET*
REMRD* ST1*/ST2*IOS
+ RESET*
IREMRD* ST1*/ST2* OS*
IREMWR
+ RESET*
IREMRD*/ST1* ST2* OS*
IREMWR
+ RESET*/XAOK*REMRD*
IREMWR
IST2*IOS*
:= RESET*
REMRD*
IST2
ST2*IOS
+ RESET*/XAOK*REMRD*/ST1*
IREMWR
10S*
+ RESET*
IREMRD* ST2*
OS*
IREMWR
+ RESET*
IREMRD*/ST!*
OS* EPAO*/REMWR
+ RESET*
REMRD* ST!*/ST2* OS* EPAO* REMWR
REMRD*
:= RESET*
IREMWR
ICS
10S*
+ RESET*
REMRD* ST!*
lOS
+ RESET*
REMRD*
10S* EPAO
+ RESET*
REMRD*
ST2*IOS
EPAO* REMWR
+ RESET*
REMRD* ST1* ST2*
+ RESET*/IA13*REMRD*
lOS
*/EPAO := RESET*
REMRD*
ST2*IOS*/EPAO
+ RESET*/XACK*REMRD*
10S*/EPAO
+ RESET*
REMRD*
ICS*/EPAO* REMWR
+ RESET*
REMRD* ST!*
CS*/EPAO
+ RESET*
OS*/EPAO*/REMWR
/REMRD* ST!*
+ RESET*
IREMRD*
IST2* OS*/EPAO*/REMWR
+ RESET*XACK* REMRD*/ST1*/ST2*IOS EPAO*/REMWR
+ RESET*
REMRD* ST1*/ST2* OS*EPAO* REMWR
IREMWR := RESET*
IREMRD*
ST2*/CS*
IREMWR
+ RESET*
REMRD* ST!*
IREMWR
10S*
+ RESET*
OS*/EPAO*/REMWR
IREMRD*
+ RESET*
ST2* CS*
IREMWR
IREMRD*
REMWR
+ RESET*
REMRD*/ST1*/ST2*IOS*
+ RESET*
IREMWR
IREMRD* ST!*
OS*
+ RESET*/XAOK*REMRD*
IREMWR
10S*
IBRESET = IRESET + IREMRD*/ST1*OS*/EPAO*/REMWR
ILCLINV = LCL
FIGURE 7

2-198

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Timing at Beginning of Instruction Load

RESET

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BRESET

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RAE

~~.____________________________________________________________

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l

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IClK
TLlF/9403-6

Timing at End of Instruction Load

RESET------------------------------------------------------------------

IClK _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _......n~

__. .n.
TL/F/9403-9

FIGURE 8. Example of Timing Waveforms

2-199

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INSTRUCTION
ADDRESS

,

16

LINE
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INSTRUCTION
RAM
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v

16

BCP

DATA ADDRESS

1

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300n.

16

DATA
MEMORY

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8

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MULTIPLEXED
ADDRESS/DATA

'-+

I...-..t

PERIPHERALS:
DIGITAL I/O
ANALOG I/O
AND/OR
UARTS
TL/F 19403-7

FIGURE 9. Another Method of Soft-Loading (A Non-Ideal Solution)
MODIFYING THE SOFT-LOAD SYSTEM
FOR LARGER MEMORY

tional I.C.'s into the breadboard area. A diagram of the
CT -104 board with the additional components is shown in
Figure ". Note that most of the prototyping area remains
available, enabling the addition of other circuitry specific to
the application being developed. A parts list is shown in
Figure 12. The PAL16R6 is programmed with the equations
shown in Figure 7. U22 and U23 must be removed from the
CT-104 board and be replaced with specially wired 20-pin
headers. The wiring on these headers, shown in Figure 13,
provides access to the RESET - signal and disables the
unused interface circuitry on the board. Pin 11 of the header
that replaces U23 must be wired to pin 13 of the 74LS14. A
wiring list is shown in Figure 14. Power supply connections
must be added because the board can no longer reside in
the PC. Development of a stand-alone soft-load application
can be done easily and quickly by using the CT-104 board
because minimal circuit construction is required.

The soft-load system as documented loads BK x 16 bits of
instruction memory. Large programs may require more
memory; smaller, lower cost systems may use less. The
soft-load system can easily be altered to load larger or
smaller instruction memory by changing one connection.
Connecting a different instruction address line to pin 4 of
the PAL changes how much instruction memory is loaded:
These connections are shown in Figure 10
Instruction Memory Size:

Connect Pin 4 of PAL to:

32k x 16
16k x 16
Bkx 16
4kx 16
2kx 16

IA15
IA14
IA13
IA12
IAll

SUMMARY

FIGURE 10. Connections for Altering
Instruction Memory Size

The soft-load circuit uses the BCP's remote interface to
load BCP code from slow EPROM to fast RAM, with a minimum of extra hardware. This method is useful in systems
where there is no host processor directly interfaced to the
BCP and the full processing speed of the BCP is needed.

USING THE CAPSTONE CT-l04 DEVELOPMENT BOARD
TO EVALUATE THE SOFT-LOAD APPLICATION
A DPB344 biphase Communications Process development
board is available from Capstone Technology Inc., of Fremont, California. The board is designed to reside in an IBM®
PC. A breadboard area is provided on the board so that
custom circuitry can be added. It can be converted into a
stand-alone soft-load system by wire-wrapping three addi-

The circuit can easily be modified to load different sizes of
memory. The Capstone Technology, Inc. CT-l04 development board can easily be converted to a stand-alone softload system for evaluation of the application.

2-200

..

»
z

~~~.~
NMC27CP128 EPROM

BYPASS CAPACITORS

74LS14---D
PAL16R6

0

I

UP TO 64K
INSTRUCTION
MEMORY

BCP PINS
AND
PC BUS
SIGNALS
FOR
PROTOTYPING

CRYSTAL

ADDRESS
LATCH

UP TO 64K
DATA
MEMORY

I
J

OP8344

COAX
LINE
INTERFACE

-

8CP

PC BUS
INTERFACE

CUSTOM
LINE
INTERFACE
PROTOTYPING

COAX BNC
OR
TWINAX
CO NNECTOR

TLlF/9403-10

FIGURE 11. CT-104 Development Board with Soft-Load Circuitry

NMC27CP128 350 ns access time or faster
PAL16R6B
DM74LS14N
28·pin wire-wrap socket
20·pin wire-wrap socket
14-pin wire-wrap socket
3 Bypass capaCitors, 0.1 "F
2 50-pin wire-wrap strips, 2 pins wide
2 20-pin headers
FIGURE 12. Parts List for Conversion of CT-104 Board

20

Y
0

0

0

0

0

yy

0

0

0

0

0

0

0

Pin 13 of Ul02

0

0

0

Replace. U23
20

Y
0

0

0

0

0

0

0

Iy
0

11
0

0

Replace. U23

0
10
11

!--i

u
0

0
10

FIGURE 13. Header Wiring for Conversion of CT-104 Board

2·201

TL/F/9403-11

.

(II

o

0Iloo

.

"'C="

Ln

Z

~------~~~~

DRIVER CIRCUITS FOR THE DP8344
The transmitter interface on the DP8344 is sufficiently general to allow use in 3270, 5250, and 8-bit transmission systems. Because of this generality, some external hardware is
needed to adapt the outputs to form the signals necessary
to drive the twinax line. The chip provides three signals:
DATA-OUT, DATA-DLY, and TX-ACT. DATA-OUT is biphase serial data (inverted). DATA-DLY is the biphase serial
data output (non-inverted) delayed one-quarter bit-time. TXACT, or transmitter active, signals that serial data is being
transmitted when asserted. DATA-OUT and DATA-DLY can
be used to form the A and B phase signals with their three
levels by the circuit shown in Figure 5. TX-ACT is used as an
external transmitter enable. The BCP can invert the sense
of the DATA-OUT and DATA-DLY signals by asserting TIN
(TMR[3)}. This feature allows both 3270 and 5250 type
biphase data to be generated, and/or utilization of inverting
or non-inverting transmitter stages.
PHASE-B
r-;::==~~==1~=====~~ PHASE-A
SHIELD GND

12

TX-ACT

PWR-GOOO C>-t-=1L;-i1rtt';~

~

:

o

-00

54.9.0.
1%

TERMINATE

SU,B

1%

10K

10

10K

820K

....7K

11
33pr

IO"--,- NRZI-~T

4.7K

I.IINUS-12

820K

TX-DlYL.".>-"IL.._

TL/F /9635-5

FIGURE 5. Schematic

2-205

ZI

....

U1

0)

....~r---------------------------------~------------------------~
The current mode drive method used by native twinax devicnominally 29 mV ± 20%. This value allows the steady state.
'?
z

c(

worst case signal level of 100 mV 66% of its amplitude
before transitioning.

es has both distinct advantages and disadvantages. Current
mode drivers require less power to drive properly terminated. low-impedance lines than voltage mode drivers. Large
output current surges associated with voltage mode drivers
during pulse transition are also avoided. Unwanted current
surges can contribute to both crosstalk and radiated emission problems. When data rate is increased. the surge time
(representing the energy required to charge the distributed
capacitance of the transmission line) represents a larger
percentage of the driver's duty cycle and results in increased total power dissipation and performance degradation.
A disadvantage of current mode drive is that DC coupling is
required. This implies that system grounds are tied together
from station to station. Ground potential differences result in
ground currents that can be significant. AC coupling removes the DC component and allows stations to float with
respect to the host ground potential. AC coupling can also
be more expensive to implement.

To achieve this. a differential comparator with complementary outputs can be applied. such as the National LM361.
The complementary outputs are useful in setting the hysteresis or switching threshold to the appropriate levels. The
LM361 also provides excellent common mode noise rejection and a low input offset voltage. Low input leakage cur·
rent allows the design of an extremely sensitive receiver.
without loading the transmission line excessively.
In addition to good analog design techniques. a low pass
filter with a roll-off of approximately 1 MHz should be applied to both the A and B phases. This filter essentially conducts high frequency noise to the opposite phase. effectively making the noise common mode and easily rejectable.
Layout considerations for the LM361 include proper bypassing of the± 12V supplies at the chip itself. with as short as
possible traces from the pins to 0.1 ,...F ceramic capacitors.
Using surface mount chip capaCitors reduces lead inductance and is therefore preferable in this case. Keeping the
input traces as short and even in length is also important.
The intent is to minimize inductance effects as well as standardize those effects on both inputs. The LM361 should
have as much ground plane under and around it as possible. Trace widths for the input signals especially should be
as wide as possible; 0.1 inch is usually sufficient. Finally.
keep all associated discrete components nearby with short
routing and good ground/supply connections.

Drivers for the 5250 environment may not place any signals
on the transmission system when not activated. The poweron and off conditions of drivers must be prevented from
causing noise on the system since other devices may be in
operation. Figure 5 shows a "DC power good" signal enabling the driver circuit. This signal will lock out conduction
in the drivers if the supply voltage is out of tolerance.
Twinax signals can be viewed as consisting of two distinct
phases. phase A and phase B. each with three levels. off.
high and low. The off level corresponds with 0 mA current
being driven. the high level is nominally 62.5 mAo
+20%-30%. and the low level is nominally 12.5 mAo
+ 20%-30%. When these currents are applied to a properly terminated transmission line the resultant voltages impressed at the driver are: off level is OV. low level is 0.32V
±20%. high level is 1.6V ±20%. The interface must provide for switching of the A and B phases and the three
levels. A bi-modal constant current source for each phase
can be built that has a TTL level interface for the BCP.
An integrated solution can be constructed with a few current
mode driver parts available from National and Texas Instruments. The 75110A and 75112 can be combined to provide
both the A and B phases and the bi-modal current drive
required as in Figure 5. The extemal logiC usad adapts the
coax oriented BCP outputs to the twinax interface circuit.
and prevents spurious transmissions during power-up or
down. The serial NRZ data is inverted prior to being output
by the BCP by setting TIN. (TMR[3]}.

Design equations for the LM361 in a 5250 application are
shown here for example. The hysteresis voltage. Vh. can be
expressed the following way:
Vh = Vrio + ((Rin/(Rin + Rd X Vol)
- (Rin/(Rin + Rd X Vol»
where
Vh Rin Rf -

Hysteresis Voltages. Volts
Series Input Resistance. Ohms
Feedback Resistance. Ohms

Cin -Input Capacitance. Farads
Vrio- Receiver Input Offset Voltage. Volts
Voh- Output Voltage High. Volts
Vol - Output Voltage Low. Volts
The input filter values can be found through this relationship:
Vein = Vinl - Vin2/1 + jwCin (Rinl + Rin2)
where Rinl = Rin2 = Rin:
Fro = W/21T

RECEIVER CIRCUITS
The pseudo-differential mode of the twinax signals make
receiver design requirements somewhat different than the
coax 3270 world. Hence. the analog receiver on the BCP is
not well suited to receiving twinax data. The BCP provides
both analog inputs to an on-board comparator circuit as well
as a TTL level serial data input. TTL-IN. The sense of this
serial data can be inverted by the BCP by asserting RIN.
(TMR[4]1.

Fro = 1/(21T X Rin X Cin)
Cin = 1/(21T X Rin X Fro)
where
Vinl. Vin2- Phase A and B signal voltages. Volts
Vein
- Voltage across Cin. or the output of the filter.
Volts
Rinl. Rinr-Input resistor values. Rlnl = Rin2. Ohms
Fro
- Roll-Off Frequency. Hz
W
- Frequency. Radians

The external receiver circuit must be designed with care to
ensure reliable decoding of the bit-stream in the worst environments. Signals as small as 100 mV must be detected. In
order to receive the worst case signals. the input level
switching threshold or hysteresis for the receiver should be

2-206

»z

Fr02 = 1/(21T X (Rin1 + Rin2) X Cin)
or,

The roll-off frequency, Fro, should be set nominally to
1 MHz to allow for transitions at the transmission bit rate.
The transition rate when both phases are taken together is
2 MHz, but then Rin1 and Rin2 must be considered, so:

I

UI

.....
0)

Fr02 = 1/(21T X 2 X Rin X Cin)
where Fro2 = 2 X Fro, yielding the same results.
The following table shows the range of values expected:

TABLE I
Value

Maximum

Minimum

Nominal

Units

Tolerance

0.05

RIN

4.935E+03

4.465E+03

4.700E+03

RF

8.295E+05

7.505E+05

7.900E+05

.n
.n

CIN

4.4556E-ll

2.6875E-ll

3.3B63E-ll

F

VOH

5.250E+00

4.750E+00

5.000E+00

V

VOL

4.000E-Ol

2.000E-Ol

3.000E-Ol

V

VIN+

1.920E+00

1.000E-Ol

VIN-

1.920E+00

1.000E-Ol

VRIO

5.000E-03

O.OOOE+OO

1.000E-03

V

R

6.533E-03

5.354E-03

5.914E-03

.n

0.05

V
V

Fro

1.200E+06

8.000E+05

1.000E+06

Hz

VH

3.36BE-02

2.691E-02

2.8BOE-02

V

Xc

7.4025E+03

2.9767E+03

4.7000E+03

.n

The BCP has a number of advanced features that give designers much flexibility to adapt products to a wide range of
IBM environments. Besides the basic multi-protocol capability of the BCP, the designer may select the inbound and
outbound serial data polarity, the number of received and
transmitted line quiesces, and in 5250 modes, a programmabie extension of the TX-ACT signal after transmission.
The polarity selection on the serial data stream is useful in
building single products that handle both 3270 and 5250
protocols. The 3270 biphase data is inverted with respect to
5250.
Selecting the number of line quiesces on the inbound serial
data changes the number of line quiesce bits that the receiver requires before a line violation to form a valid start

0.2

sequence. This flexibility allows the BCP to operate in extremely noisy environments, allowing more time for the
transmission line to charge at the beginning of a transmission. The selection of the transmitted line quiesce pattern is
not generally used in the 5250 arena, but has applications in
3270. Changing the number of line quiesces at the start of a
line quiesce pattern may be used by some equipment to
implement additional repeater functions, or for certain inflexible receivers to sync up.
The most important advanced feature of the BCP for 5250
applications is the programmable TX-ACT extension. This
feature allows the designer to vary the length of time that
the TX-ACT signal from the BCP is active after the end of a
transmission. This can be used to drive one phase of the

2-207

....

~ r---------------------------------------------------------------------~

~

~

twinax line in the low state for up to 15.5 p.s. Holding the line
low is useful in certain environments where ringing and reflections are a problem, such as twisted pair applications.
Driving the line after transmitting assures that receivers see
no transitions on the twinax line for the specified duration.
The transmitter circuit shown in Figure 5 can be used to
hold either the A or B phase by using the serial inversion
capability of the BCP in addition to swapping the A and B
phases. Choosing which phase to hold active is up to the
designer; 5250 devices use both. Some products hold the A
phase, which means that another transition is added after
the last half bit time including the high and low states, with
the low state helf for the duration, see Figure 6. Alternatively, some products hold the B phase. Holding the B phase
does not require an extra transition and hence is inherently
quieter.

response and latency times of the BCP make interrupts very
useful in most 5250 applications.
Although factors such as data and instruction memory wait
states and remote processors waiting BCP data memory
accesses can degrade interrupt response times, the minimum latency is 2.5 T-states. The BCP samples all interrupt
sources by the falling edge of the CPU clock; the last falling
edge prior to the start of the next instruction determines
whether an interrupt will be processed. When an interrupt is
recognized, the next instruction in the present stream is not
executed, but its address is pushed on the address stack. A
two T-state call to the vector generated by the interrupt type
and the contents of (IBR] is executed and [GIE] (Global
Interrupt Enable) is cleared. If the clock edge is missed by
the interrupt request or if the current instruction is longer
than 2 bytes, the interrupt latency is extended.
Running in an Interrupt driven environment can be complex
when multiple sessions are maintained by the same piece of
code. The software has the added overhead of determining
the appropriate thread or session and handling the interrupt
accordingly. For a multi-session 5250 product, the transceiver interrupt service routines must determine which session is currently selected through protocol inferences and
internal semaphores to keep the threads separate and intact.
In a polled environment, the biggest difficulty in designing
software is maintaining appropriate polling intervals. Polling
too often wastes CPU bandwidth, not polling frequently
enough loses data and jeopardizes communication integrity.
Standard practice in servicing polled devices is to count
CPU clock cycles in the program flow to keep track of when
to poll. A program change can result in lengthy recalculations of polling intervals and requalifications of program
functionality. Using the programmable timer on board the
BCP to set the polling interval alleviates the need to count
instructions when code is changed or added. In both polled
or interrupt environments, the latency effects of remote
processors waiting memory accesses must be limited to a
known length of time and figured into both polling intervals
and worst case interrupt latency calculations. Using the programmable timer on the BCP makes both writing and maintaining polled software easier.

TL/F/9635-6

FIGURE 6. Line Hold Options
The signal was viewed In the same manner as Figures 3 and 4. The lefthand
portion of the signal is a transmitting device utilizing line hold on phase A.
The right hand side shows the IBM style (phase B) line hold.

To set the TX-ACT hold feature, the upper five bits of the
Auxilliary Transceiver Register, (ATR [3-7Jl, are loaded
with one of thirty-two possible values. The values loaded
select a TX-ACT hold time between 0 p.s and 15.5 p.s in 500
ns increments.

SOFTWARE ARCHITECTURE FOR 5250 EMULATION
The 5250 data rate is much lower than that of the 3270 data
stream, hence it is possible for the BCP to emulate all seven
5250 sessions with a CPU frequency of 8 MHz. Choosing a
16 MHz crystal allows the transceiver to share the CPU
clock at OCLK/2, eliminating an extra oscillator circuit. The
8 MHz rate yields a 125 ns T-state, or 250 ns for most
instructions. Interrupt latency is typically one instruction (assuming no wait states or remote accesses) which is suitable
for 5250 operation. If more speed is desired, the CPU could
be switched to 16 MHz operation.

SOFTWARE INTERFACE
The BCP was designed to simplify designing IBM communications interfaces by providing the specific hardware necessary in a highly integrated fashion. The power and flexibility
of the BCP, though, is most evident in the software that is
written for it. Software design for the BCP deserves careful
attention.
When designing a software architecture for 5250 terminal
emulation, for example, one concern the designer faces is
how to assure timely responses to the controller's commands. The BCP offers two general schemes for handling
the real time response requirements of the 5250 data
stream: interrupt driven transceiver interface mode, and
polled transceiver interface mode. Both modes have
strengths that make them desirable. The excellent interrupt

A MULTI·MODE TRANSCEIVER
The BCP provides two 5250 protocol modes, promiscuous
and non-promiscuous. These two modes afford the designer a real option only when the end product will attach to one
5250 address at a time. The non-promiscuous mode is configured with an address in the (ATR] register and only re-

2-208

l:ceives messages whose first frame address matches that
address, or an error occurs in the first frame of the message. Filtering out unwanted transmissions to other addresses leaves more CPU time for other non-protocol related tasks, but limits the device to one address at a time. The
promiscuous mode allows messages to any and all addresses to be received. Resetting the transceiver during a message destined to another device forces the transceiver to
begin looking for a start sequence again, effectively discarding the entire unwanted message. Because of its flexibility,
the promiscuous mode is used in this illustration.

CPU point of view, the interrupt masks are located here. In
this illustration, the system requires receiver, transmitter,
BIRO, and timer interrupts, so that in operation those interrupt bits should be unmasked. For initialization purposes,
though, interrupts should be masked until their vectors are
installed and the interrupt task is ready to be started. Therefore, loading [ICR] with H#7F is prudent. This also sets the
receiver interrupt source, but that will be discussed in the
next section.
TRANSCEIVER CONFIGURATION REGISTERS:
{TMR}-Transceiver Mode Register-This register controls the protocol selection, transceiver reset, loopback, and
bit stream inversion. Loading this register with H #00 sets
up the receiver in 5250 promiscuous mode, inverts serial
data out, does not invert incoming serial data, does not allow the transmitter and receiver to be active at the same
time, disables loop back, and does not reset the transceiver.
Choosing to set [RIN] low assumes that serial data will be
presented to the chip in NRZI form. Not allowing the receiver and transmitter to operate concurrently is not an issue in
5250 emulation, since there is no defined repeater function
in the protocol as in 3270 (3299). Bits [85, 6], [RPEN] and
[LOOP] are primarily useful in self testing, where [LOOP]
routes the transmitted data stream into the receiver and
simultaneous operation is desirable. Please note that for
loopback operation, [RIN] must equal [TIN]. [TRES] is used
regularly in operation, but should be left off when not specifically needed.
{TCR}-Transceiver Command Register-This register
has both configuration and operation orientated bits, including the transmitted address and parity bits. For this configuration, the register should be set to H # 00 and the specific
address needed summed into the three LSBs, as appropriate. The [SEC] or Select Error Codes bit is used to enable
the {ECR} register through the {RTR} transceiver FI FO
port, and should be asserted only when an error has been
detected and needs to be read. [SLR], or Select Line Receiver is set low to enable the TTL-IN pin as the serial data
in source. The BCP's on chip comparator is best suited to
transformer coupled environments, and National's LM361
high speed differential comparator works very well for the
twinax line interface. [ATA], or Advance Transmitter Active
is normally used in the 3270 modes to change the form of
the first line quiesce bit for transmission. Some twinax products use a long first line quiesce bit, although it is not necessary. The lower four bits in {TCR} are used to form the
frame transmitted when data is written into {RTR}, the
transceiver FIFO port. Writing into {RTR} starts the transmitter and/or loads the transmit FIFO. The least significant
three bits in {TCR} form the address field in that transmitted
frame, and B3, [OWP] controls the type of parity that is
calculated and sent with that frame. [OWP] set to zero calculates even parity over the eight data bits, address and
sync bit as defined in the IBM 5250 PAL
{ATR}-Auxilliary Transceiver Register-Since this application is configured for promiscuous mode, the {ATR}
register serves only to set the line hold function time. In nonpromiscuous mode, the three least significant bits of this
register are the selected address. Setting this register to
H # 50 allows a 5 !'-S hold time and clears the address field
to 0, since promiscuous mode is used.

REAL TIME CONSIDERATIONS
Choosing a scheme for servicing the transceiver is basic to
the design of any emulation device. The BCP provides both
polled and interrupt driven modes to handle the real time
demands of the chosen protocol. In this example, the interrupt driven approach is used. This implies the extra overhead of setting up interrupt vectors and initializing the interrupt masks appropriately. This approach eliminates the
need to figure polling intervals within the context of other
CPU tasks.
5250 CONFIGURATION
Configuring a complex device like the BCP can be difficult
until a level of familiarity with the device is reached. To help
the 5250 product designer through an initial configuration, a
register by register description follows, along with the reasons for each configuration choice. Certainly, most applications will use different configurations than the one shown
here. The purpose is to illustrate one possible setup for a
5250 emulation device.
There are two major divisions in the BCP's configuration
registers: CPU specific and transceiver specific ones.
CPU SPECIFIC CONFIGURATION REGISTERS:
{DCR}-Device Control Register-This register controls
the clocks and wait states for instruction and data memory.
Using a value of H#AO sets the CPU clock to the OCLK/2
rate, the transceiver to OCLK/2, and no wait states for either memory bank. As described above, the choice of a
16 MHz crystal and configuring this way allows 8 MHz operation now, with a simple software change for straight 16
MHz operation in the future.
{ACR}-Auxiliary Control Register-Loading this register
with H#20 sets the timer clock source to CPU-CLK/2, sets
[BIC], the Bidirectional Interrupt Control to configure BIRO
as an input, allows remote accesses with [LOR] cleared,
and disables all maskable interrupts through [GIE] low.
When interrupts are unmasked in (lCR l. [GIE] must be set
high to allow interrupts to operate. [GIE] can be set and
cleared by writing to it, or through a number of instructions
including RET and EXX.
(lBR}-lnterrupt Base Register-This register must be
set to the appropriate base of the interrupt vector table located in data RAM. The OP8344 development card and
monitor software expect UBR] to be at H # 1F, making the
table begin at H # 1FOO. The monitor software can be used
without the interrupt table at H # 1FOO, but doing so is simplest for this illustration.
(lCR}-lnterrupt Control Register-This register contains both CPU and transceiver specific controls. From the

2-209

z

....•
en
U1

....

~

LI)

:Z
 0)
queueldata) ;
if IluI tieount-= 0)
if Irx_eol) selected = fal se;

if IluI tieount

)

else (
if Iluitifrale) (

lu!tieount = parse (data);
queue Idata);
)

else (
if I(var = single_decode(data)) == queable)
queueldata) ;
TL/F/9635-11

2·214

r---------------------------------------------------------------.~

79
BO
Bl
B2
B3
B4
B5
B6
B7
BB
B9
90

91

n
93
94
95
96
97
9B
99
100
101
102
103
104
105
106
107
lOB
109
110
Addr

ZI

else if (var == i.ledl illediateldatal;
if Irx_eol) selected = false;

....a>CI1

}

return ();
;
;}
; lagerror ()
;{
; baol resul t;
switth (error Jype)
case RDI5:
resul t = err _rdi s ();
break;
tase L"BT:
resul t = err J Ibt () ;
break;
tase PARR:
result = err _parr 0 ;
break;
case DVF:
result = err _ovf () i
break;
default:
result = err _unknown 0;
break;

If receiver diabled while active

If loss of midbi terror

If pari ty error

If recei ver FIFO overrun

1* strange error handler

return (resultl;

Line RXINT
111
;err)lbto
112
;(
113
if I! DA U !seletted U !delay ILA)) return !fal se) j If delay of 6 usec
114
else (
115
logO;
If bUlp error counters
116
return (true);
If admi t defeat
117;
)
liB

119
120
121
122
123
124
125
126
127
128

;}
i ----------------------------------------------- ---------------- ------

nale:
description:

RUNT
receiver interrupt handler

received datul is sent to other routines thru gp7'
5CP is set appropriatel y in lZ
BP5P - aeti ve addresses: bi ts 0-6
selected flag: bi t 7
BP6P - lulticount:
bit 7-6
unused:
bi t 5
TL/F 19635-12

2-215

....CD

129
130
131

II)

Z•

CC

132
133
134
135
136
137
13B
139
140
141
142

bit 4
bit 3
hi ts 2-0

acti vated:
rx_eol flag:
seladdr:
GP7P - recei ved data

DA interrupt, GPS', GP6'
ACC' ,GP7' ARE DESTROYED
tiq 9/16/87 create
; ----------------------------_ ..... __ .. _---_ ...
.. _-------- ... __ ....... _-------PUBLIC RCVRINT
entry:
exit:
hi story:

EXTRN
EXTRN
EXTRN

_--_

PARSE, QUEUE, I""EDECODE, RESXCVR
"!DERRL," !DERRH, OVFERRL, OVFERRH, PARERRL, PARERRH
RXERRL,RXERRH,RSPCTL,RSPCTH, BASESCP, IESERRL, IESERRH

143

00000
00000
00001
00002
00003
00004
00004

AEE8
DSOO
CCOO
D900
D900
B078

00005 F16S
00006 307B
00007 DOOO

BIOI000000
BIOOOOI000
8100000111
8111000000
BIIOOOOOOO
BII01
8100000010

; select the error register
j rxeol flag
j EOM deli seter
; lulticount
j selected flag

EXX

MA,AB,DI

; SET APPROPRIATE BANK

J"PF
CALL
J"PF

NS ,RERR, NOERROR
RXERROR
; ERROR IN FRAME
S,C,EXIT
; ABORT

LDI
AND

EOM,ACC
TSR,SP7

; LOAD "ASK
; FOR" ADDRESS

C"P

GP7,EO"

; TEST

J"PF

NS,Z,CIRXINT

; IF NOT EQUAL, JUMP

ORI
J"P

RXEO",SP6
C2RXlNT

; ELSE SET EOM FLAG

ANOI

RXEO"*,GP6

j

SELERR: EaU
Eau
EOM:
EGU
"ULTI : EaU
SELECT: EQU
LTA:
EaU
CFLAS: EaU

mo":

j

; CARRY FLAG

RCVRINT:

HOERROR:

Line RUNT

Addr
00008
00009
OOOOA
OOOOA

144
145
146
147
148
149
ISO
151
152
153
154
154
155
156
157
158
159
160
160
161
161
162

SOBA
CBOO
CBOO
4f7A

163
164
165
166
167

IbB
OOOOB

169
170

CIRXINT:
j
j

171
171
172
173

DECIDE IF WE'RE ALREADY SELECTED

j

C2RXINT:

171
OOOOB 8DE9
OOOOC 0000

CLEAR IT

J"PB

GP5,S,B7,DEVSELECT

j

IF ALREADY SELECTED

j

; NOT SELECTED ... DECIDE IF ADDRESS IS ACTIVE, IE; VALID FOR US
TLlF/9635-13

2·216

,--------------------------------------------------------------------,
00000

174
175

00000 B3CS

m
m

OOOOE 8C09
OOOOF 0000
00010 CEOO
00011 0000
00012 8[29
00013 0000
00014 CEOO
00015 0000
00016 8m
00017 0000
00018 CEOO
00019 0000
OOOIA 8C69
00018 0000
OOOIC CEOO
00010 0000
0001E 8C89
OOOIF 0000
00020 CEOO
00021 0000
00022 8CA9
00023 0000
00024 CEOO
00025 0000
OO0268m

Addr
00027 0000
00028 CEOO
00029 0000
0002A CE80
00028 0000
0002C CBOO

DEVTABLE:
JR"K

177
177
177
178
178
178
179
179
179
IBO
180
180
IBI
181
IBI
182
182
IB2
183
IB3
IB3
184
184
184
185
185
185
IB6
IB6
IB6
IB7
IS7
le7
IBB
ISB
IBB
lB9
189

TSR, ROT 6, "SK3

U1
.....

; ELSE, SEE IF ACTIVE
; JU"P BASED ON THE ADDRESS FIELDt4

J"PB

SP5,NS,BO,RSTRX ; ADDR 0 - IF NOT ACTIVE, RESET RX

LJ"P

LOADSCP

J"PB

SP5,NS,81,RSTRX ; ADDR I - IF NOT ACTIVE, RESET RX

LJ"P

LOADSCP

J"PB

SP5,NS,B2,RSTRX ; ADDR 2 - IF NOT ACTIVE, RESET RX

LJ"P

LDADSCP

J"PB

6P5,NS,B3,RSTRX ; ADDR 3 - IF NDT ACTIVE,

Lm

LDADSCP

Jm

6P5,NS,B4,RSTRX ; ADDR 4 - IF NOT ACTIVE,

LJ"P

LDADSCP

J"PB

SPS,NS,BS,RSTRX ; ADDR 5 - IF NOT ACTIVE,

LJ"P

LDADSCP

JMPB

SPS,NS,B6,RSTRX ; ADDR 6 - IF NOT ACTIVE,

LJ"P

LDADSCP

; ACTIVE DEVICE,

LCALL

RESXCVR

; ADDR 7 - RECEIVED EOM ... WE'RE NDT INTERESTED

JMP

EXIT

; QUIT

en

; ACTIVE DEVICE, SET scp

; ACTIVE DEVICE, SET scp

; ACTIVE DEVICE,

; ACTIVE DEVICE,

; ACTIVE DEV I CE,

; ACTIVE DEVICE,

Line RXlNT
189
190
190
190
191
191
191
192

TLlF/9635-14

2-217

.

~

z

CD
....

In

Z•

c(

00020
00020 F908
0002E FE48
0002F B008
00030 FE68
00031 8078
00032 FI05
00033 E273

00034
00034 FD64
00035 BOOB
00036 0000
00037
00038
00039
0003A

CE80
0000
CBOO
CBOO

0003A
0003B
0003C
0003D
0003£

CE80
0000
5809
4F8A
B078

0003F FI05
00040 F54A
00041 CE80
00042 0000
00043 CBOO

Addr

00044

193
194
195
196
197
197
198
198
199
200
200
201
202
202
203
203
204
205
206
207
208
20B
209
209
209
210
210
210
211
212
213

;
; LOAD THE SCP POINTER, IZ

;
LOADSCP:
lOR

ACC,ACC

; CLEAR

"OVE

ACC,ZLO

; LOW BYTE

LDI
"OVE

BASESCP ,ACC
ACC,ZHI

; SET UP UPPER BYTE OF SCP POINTER

LDI
AND

ED",ACC
TSR,ACC

; EO" "ASK
; LEAVE IN ACC

ADD

ZHI,ZHI

; ADD INTO Z POINTER

;
; DECODE THE CO""AND FRA"E

;
DECODE:
"OVE

RTR,SP7

J"PB

GP7,S,BO,"ULTIFR"i IF "ULTIFRA"E

LCALL

I""EDECODE

J"P
"ULTlFR":
LCALL

; SET RX DATA

; ELSE, I""EDIATE ACTION REQUIRED

EXIT
PARSE

; SET "ULTI COUNT

ORI
ANDI
LDI
AND

H180,SP5
EO"f,SP6
EO",ACC
TSR,ACC

;
;
;
;

OR

SP6,SP6

; SET NEN ADDRESS

LCALL

QUEUE

; PLACE ON QUEUE

J"P

EXIT

213
213
214
215
216
217
217
218
218
219
219
219
220
221
222
223

SELECTED = TRUE
CLEAR SELECTED ADDRESS
"ASK ADDRESS
LEAVE IN ACC

;
; THIS CODE IS BRANCHED TO IF THE DEVICE IS SELECTED
FIRST, SET SCP BASED ON SELECTED ADDRESS

Line RUNT
224
225
226

;
DEVSELECT:
lOR

ACC,ACC

; CLEAR ACC
TLlF/9635-15

2-218

:J00044 F90a
00045 FE48
00046 BOOB
00047 FE68
00049 B07B
00049 FIOA
0004A E273

0004B FD64
0004C BC08
00040 FIGA
0004E C8C8
0004F 0800
00050
00051
00052
00053

CEBO
0000
2018
0800

00054 43FA
00055 cm
00056 F54A
00057 CBOO

00058
00058 43FA
00059
OOOSA
00058
0005e
0005D
0005D

BCbA
0000
47F9
CBOO
eBOO
CBOO

226
227
227
228
229
229
230
231
231
232
232
233
234
235
236
236
237
238
238
239
239
240
241
241
241
242
243
244
245
246
247
248
248
249
249
250
251
252
253
254
255
256
256
256
257
2SB
259

Z

MOVE

ACC,ZLO

•
.....

U'I

; CLEAR LOW BYTE OF POiNTER

Q)

LDI
MOVE

BASESCP I ACC
ACC I ZHI

; BASE OF SESSION CONTROL PASE
; UPPER BYTE

LDI
AND

EOM, ACC
SPo,ACC

; MASK ADDRESS
; LEAVE IN ACC

ADD

ZHI I ZHI

; FORM SCP POINTER

NOW DECIDE ABOUT MUL TIFRAME POSSIBILITIES
MOVE

RTR,GP7

; GET DATA

LDI
AND

MULTI,ACC
BP6,ACC

; MULTI MASK
; COUNT IN UPPER NIBBLE

SRL

ACC ,ROT6

; POSITION IN LOWER NIBBLE

JMPF
LCALL

SI ZI NEWCOMM
QUEUE

; NOT inA MUL TIBYTE
; MULTI I SO PUSH ON QUEUE

SUBI
JHPF

HIOI,ACC
S,Z, TERMULTI

; DECREMENT MUL mOUNT
; IF ZERO, MULTI HAS TERMINATED

; MULTI STILL IN PROSRESS
ANOI
SLA

MULTlf,6Pb
ACC,ROT6

; CLEAR OUT OLD COUNT
; REPOSITION COUNT

OR

6P6,SP6

; SUM INTO STATUS

JMP

EXIT

;
; MULTI COUNT HAS REACHED ZERO , SO TERMINATE

;
TERMULTl:
ANDI
JMPB

MULTl4 ,SP6
; CLEAR OLD COUNT TO ZERO
SP6,NS I B3 ,ClTERM; IF NOT EOM ,

ANDI
JMP

SELECT *,BPS
RSTRX

JMP

EXIT

; ELSE, SELECT = FALSE
; RESET THE TRANSCEIVER

CITERM:

260
261

;

262

; NEW COMMAND; Hum OR SINGLE

263
OOOSE

264

NENCOM":
TLlF/9635-16

2-219

CD
.,...

an
Z•

line RUNT

Addr


Z

•
en

....

en

ILLEGAL:
LOI

I LLEBAL, ACC

; WHAT ERROR IS THIS?

J"P

BU"PERR

; SHOULD NOT 6ET HERE!!

J"PF
Jm

; if DA, THEN NO ERROR
S,DA,CLEARC
SP5,S,B7,L06lT ; IF SELECTED, POST

CALL
JIII'B

; DELAY FOR 6 USEC
SDLY
NCF,NS,B5,CLEARC; IF NOT ACTIVE - DISCARD, ELSE POST

LDI
J"P

"IDERRL,ACC
BU"PERR

; LOSS OF mBIT
; INCRE"ENT COUNTER

LDI
J"P

PARERRL,ACC
BU"PERR

i PARITY

LDI

OVFERRL, ACC

; OVERFLOW ... VERY BAD'

ADD

ILO, VLO

; FOR" NEll POINTER

LDI

LD

HI01,ACC
PTRY,6P6

; INCRENENT
; FETCH OLD COUNT

3\9

ADDRI

SP6,PTRY,POSTD ; \/RITE OUT NEW

31'1
320
321

J"PF
LD

NS,C,RXElIT
PTRY,SP6

ADDRI

6P6,PTRY

ORI

CFLAS,CCR

Line RUNT

Addr

301
302
303
304
00079 8DE9 304
0007A 0000 304
oom CCOO 305
306
0007C 8CAI 306
0007D 0000 306
0007E 0000 307
oo07E B008 308
0007F CBOO 309
00080 CBOO. 310
00080 B008 311
00081 CBOO 312
00082 CBOO 3\3
00082 8008 314
00083 B008 315
316
00083 E212 316
00084 BOl8 317
318
00085 COCA 31B

00077 CBOO
00078 CDOO
00078 DEOO

00086 A04A
00087 DIOO
OOOBB COCA

m

0008'1
oo08A
00088
00088
OOOBC
OOOBe
00080

322
322
323
324
325
326
327
328
32'1

AOCA
5020
5020
AF80
AFBO
4FDO
CBoo

330
331
332
333

m

335
336
337

L"BTERR:

L06IT:

PARERR:

OVFERR:
BU"PERR:

; SET OUT
; FETCH UPPER 8YTE

; SET CARRY

RXEXlT:
; DO NOT restare fl ags

RET
CLEARC:
ANDI
J"P

CFLASf,eCR
RXEXIT

; CLEAR CARRY

;-------------------------------------------_ .. _----------------------nate:
descriptian:
entry:

exit:
WARNING:
history:

SDLY
delay radine, NULTlPLES OF 4.Busec,
1.4 usec OVERHEAD, "A X OF 410usec
delay caunt an stack
acc destroyed
DONT CALL TH I S WITH COUNT = O!
tjq '1/16/87 create

; ------------------------------------_ .... _----------------------------TLlF/9635-18

2·221

.

CD
.,...

in

Z

c:(

338
339
SDLY:
340
oooaE AEao 340
341
0008F FDIF 341
342
00090 FFEB 342
343
Addr
Line RUNT

0008E

00091 FFEA

En

KA,KB,NAI

; BANK, ALLOW INTERRUPTS

MOVE

DS,ACC

; SET COUNT

"DVE

SP7,DS

; PUSH SP7 RESISTERS USED

KaVE

SP6,DS

MOVE

ACC,SP7

; USE SP7 FOR COUNT ALSO

LDI

HI03,SP6

; LOAD FOR 4.ausec COUNTS

SUBl
J"PF
SUBl
J"PF
"OVE

HIOI,6P6
NS, Z,SDLYLP2
HIOI,SP7
NS,Z,SDLYLPI
DS,SP6

;
;
;
;
;

MOVE

DS,6P7

RET

RI,RF

343
344

00092
00093
00093
00094
00094
00095
00096
00097

FD6S
FD68
B03A
BOJA
20lA
DOOO
2018
DOOO

00098 FD5F
00099 FD7F
0009A AFBO

344
345
346
347
348
349
350
351
352
352
353
353
354
355
356
357

SDLYLPI:
SDLYLP2:
DECRE"ENT COUNT
CONTINUE UNTIL EXHAUSTED
DECREKENT OUTER COUNT
CONTINUE IF NOT ZERO
POP REG

; RETURN, RESTORE FLAGS

END

Asselbly Phase cOlplete.
o error {sl detected.
TL/F/9635-19

2-222

Section 3
ISDN Components

Section 3 Contents
Introduction to NSC Basic Access I.C. Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TP3401 DASL Digital Adapter for Subscriber Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TP3410 "U" Interface Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TP3420 ISDN Transceiver "S" Interface Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPC16083/HPC26083/HPC36083/HPC46083/HPC16003/HPC260031HPC360031
HPC46003 High-Performance Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPC16400/HPC36400/HPC46400 High-Performance Microcontrollers with HDLC Controller
ISDN Definitions...................................................................

3-2

3-3
3-8
3-9
3-10
3-11
3-12
3-13

Introduction To National Semiconductor
Basic Access I. C. Set
In developing the architecture of this ISDN chip set, National's major objective has been to create a flexible set of
building blocks which provide elegant and cost-effective solutions for a wide range of applications. With just a few highly integrated devices, a broad spectrum of ISDN equipment
can be designed, ranging from Central Office and PBX line
cards to X.25 and ISDN Terminals and telephones, PC and
Terminal Adapters, packet-mode statistical multiplexers,
NT-1's and other ISDN equipment.

processor. All devices in the chip set, together with other
standard components such as COMBOs, can be interconnected via a common serial interface without the need for
any "glue" components. The result is a very elegant architecture offering many advantages including the following:
• A high degree of modularity with minimal component
count
• The same transceiver at both ends of a loop
• No interrupts for D-Channel flow control
• Powerful Packet buffer management
Other chip set architectures, which divide a layer into some
functions in one device and the rest in other devices, are
unable to offer all these advantages.

One of the keys to this flexibility is the concept that device
functions in the chip set should be specifically aligned with
the first 3 layers of the ISO 7 layer Protocol Reference Model. Thus, National's chip set has a distinct partitioning of
functions into several transceivers which provide the bit-level transport for Layer 1, (the Physical Layer), while the functions of Layer 2, (the Data Link Layer), and Layer 3, (the
Network Layer), are supported entirely by a single micro-

ISDN Chip Set Partitioning
ISO
Layer

National

4-7

NS32322

3

Others

ChipC

HPC16400

1

ChipB

ChipB

2
TP3401DASL
or TP3410 EC or
TP3420SID

Chip A

3-3

Chip A

Transceiver Number 3

NSC Solutions for Layer 1

The TP3420 'S' Interface Device (SID), is a 4-wire transceiver which includes all the Layer 1 functions specified in
CCITT Recommendation 1.430. In addition, the TP3420 includes noise filtering and adaptive equalization, as well as a
high resolution digital phase-locked loop, to provide transmission performance far in excess of that specified in 1.430.
All Activation and '0' channel access sequences are handled automatically without the need to invoke any action
from a microprocessor.

National's solution for Layer 1 consists of 3 CMOS transceivers, which cover a wide variety of twisted-pair applications for ISDN Basic Access. Each transceiver is capable of
transmitting and receiving 2 'B' channels plus 1 '0' channel,
and has mode selections to enable it to operate at either
end of the loop.
Transceiver Number 1
The TP3400 Digital Adapter for Subscriber Loops (DASL) is
a low-cost burst-mode transceiver for 2 wire PBX and private network loops up to 6 kit in range. Scrambled Alternate
Mark Inversion coding is used, together with adaptive equalization and timing-recovery, to ensure low bit error rates on
a wide variety of cable types. All activation and loop timing
control circuitry is also included.

Digital Chip to Chip Interfaces
To retain the flexibility of interfacing components from this
chip set with a variety of other products, two digital interfaces are provided on each device. One is for the synchronous
transfer of 'B' and '0' channel information in any of several
popular multiplexed serial formats. This means that National's chip to chip interface is all encompassing of proprietary
frame structures such as the 10M, IDL, ST-BUS and more.
A second interface, for device mode control, e.g. power upl
down, setting loopbacks etc., uses the popular MICROWIRE/PLUSTM. MICROWIRE/PLUS is a synchronous serial
data transfer between a microcontroller and one or more
peripheral devices. National's HPC and COPSTM microcontroller families, together with a broad range of peripheral
devices, support this interface, which is also easy to emulate with any microprocessor.

Transceiver Number 2
The TP341 0 Echo-canceller Family is a set of 2-wire transceivers designed to meet the rigorous requirements of the
'U' interface. Derived from a common basic architecture,
these devices will be compatible with the line-code and
framing structure speCifications of various PTT administrations and with the U.S. standard.

Popular Frame Structures
Addressed by NSC ISDN Devices

NSC ISDN Transceiver Chip Set

BURST MODE (TeM)
FOR PBX LOOPS

JII

-11--------------\
X

1--{'-._ -81- - I . '-._
B2 _.X-----VfJ---~..r
_____ ~ ___ F""\....

TP3401
DASL

X

2 --<,-_81---1

ECHO CANCELLER
FOR 'U' INTERFACE

z[[

JII

B2

~:::)(:::::r<:

3 ~::::)(:: :::X_Bl---1X,-_B_2...J~<:
4 --<"'__Bl_....~::(

82

~;i-----zz<:
TL/X/OOO8-2

TL/X/OOO8-1

3-4

-

:;

NSC Solutions for Layers 2 and 3
National has developed an extremely powerful solution for
implementing various protocols for both Layer 2 (Data Link
Layer) and Layer 3 (Network Layer), including X.25 LAP8
and LAPD (0.921 and 0.931), together with the capability of
several packet-mode Terminal Adaption schemes'. A single
device incorporates all the processing for these functions:
the HPC16400. One of National's growing family of 16-bit
single chip CMOS microcontrollers, the HPC16400 is based
on a high-speed (17 MHz) 16-bit CPU "core". To this core
has been added 2 full HDLC formatters supported by DMA
to external memory, and a UART.
This set of features makes the HPC16400 an ideal processor for running all the functions of an ISDN Terminal Adapter, TE or telephone, or the communications port of a highend terminal. In a typical application, one of the HDLC channels may be dedicated to running the LAPD protocol in the
'D' channel, while the other provides packet-mode access
to one of the '8' channels. The UART would serve as an
RS232 interface running at any of the standard synchronous or asynchronous rates up to 128 kbaud. A serial interface decoder allows either or both HDLC controllers to be
directly interfaced to any of the 3 Layer 1 transceivers or to
a variety of backplanes, line-card controllers and other devices using time-division multiplexed serial interfaces.
Because of the large ROM and RAM requirements for Layer
3 and the Control Field procedures of Layer 2 in LAP8 and
LAPD protocols, the HPC16400 has 256 bytes of RAM and
no internal ROM for storage of user variables. Packet storage RAM and all user ROM is off-chip, this is by far the most

cost-effective and flexible combination. A multiplexed bus to
external memory provides direct addressing for up to 64
kby1es of memory, and on-chip I/O allows for expanded addressing for up to 544 kby1es of memory.
The HDLC controllers on the HPC16400 allow continuous
HDLC data rates up to 4.1 Mb/s to be used. In addition to
handling all Layer 2 framing, the HDLC circuitry includes
automatic multiple address recognition to support, for example, multiple TEl's in LAPD. Furthermore, the DMA controller provides several register sets for packet RAM management with minimal CPU intervention, including "chaining" of
successive packets. This integrated design achieves a high
throughput of packet data without the need for costly FIFO's
and external interrupts, thereby minimizing the impact of
packet handling on CPU time.
In many applications a number of other peripheral functions
must also be provided, such as sensing switches or scanning a small keyboard, interfacing to a display controller etc.
A number of extra I/O ports and a MICROWIRE/PLUS serial data expansion interface are available on the HPC16400
to service these functions. In addition, 4 user configurable
16 bit timer-counters simplify the many time-outs required to
manage such a system, including the default timers specified in the various protocol specifications.
Terminal adaption consistent with the CCITI V.11 0 method,
which is based on a synchronous 80 bit frame, is readily
implemented with another member of the HPC family, the
HPC16040. Around the standard core CPU, the 16040 has
on board I/O and 4 additional PWM timers, a UART, 4k of
ROM and 256 by1es of RAM.

*For example, as per DMI Modes 2 and 3.

HPC16400 Simplified Block Diagram

).IWIRE+

256 BYTE
RAN

Dt.tA

CPU

CORE

TL/XI0008-3

3-5

(;
Q,
c

2-

0'
:::J

-I

o

Z

~
o
:::J

!!.

en
CD

3

n'
o
:::J

Q,

c

2-

...

o

aJ

I\)

!II

n'
»
n
n

m
p
en
CD

-

NSC Solutions: Systems Level
...:

J
Co)

a...
~::J

HDLC #1 on the HPC16400. HDLC #2 is working in conjunction with the UART to provide an X.25 or LAPD packetmode in a 'B' channel at 64 kb/s. Terminal Adaption of both
the data and the terminal handshaking signals is performed
by the HPC16400 via the UART and HDLC controller #2,
which can use either of the 'B' channels. DMI modes 2 and
3 (for a single channel) can be supported using this method,
with the necessary data buffers set up in internal RAM. The
other 'B' channel is occupied by the TP305417 PCM COMBO providing the digitized voice channel.

Building an ISDN TE or TA
Shown below is a typical application of the chip set in a
Basic Access TE, which offers one voice channel and an
RS232 interface to support an external terminal. The
TP3420 'S' Interface Device ensures that the system is
compatible with any'S' or 'T' standard jack socket and provides the multiplexing for the other devices operating in the
'B' and 'D' channels. All timing for the TE is derived by the
TP3420 from the received line signal. In a typical application, LAPD signalling in the 'D' channel is provided via

"CI
C

8
"E

TP3420
'SID'

TP3054/57
COMBO

~

1i

c

o

:;
z

~
c
o
:;::

II[
lie
1
'5'

INTERFACE

Co)

ROM +
PACKET
RAM

::J

"CI

-2

.5

TLIX/0008-4

PBX 2 Wire Terminals
TP3420 SID with a TP3401 DASL. The clean partitioning of
device functions makes this possible with no other changes
to the design.

The following example shows how simple it is to convert an
'S' Interface terminal, which requires 2 twisted pairs, to a
terminal using only a single pair by replacing the

TP3401
OASL

TP3054/57
COMBO

MICROWIRE

lie
1
'U'

INTERFACE (:S2 km)

ROM +
PACKET
RAM

TLIX/0008-5

3-6

NSC Solutions: Systems Level
nels can be either multiplexed on and off the card for processing or can undergo Layer 2 processing on the card itself.

Basic Access Line Cards
For operation on a line card in a C.O., PABX or NT-2, each
of the 3 transceiver devices can be set to operate as the
timing master for the loop, being synchronized to the system clock and controlling all loop frame timing. If programmable time-slot assignment is required, the TP3155 TSAC
provides 8 individually programmable frame sync pulse outputs locked to a common frame marker. 'B' channels can be
interfaced to standard backplane interfaces, while 'D' chan-

'S' OR 'u'
RErERENCE
POINT

'S' OR 'U'
RErERENCE
POINT

For the latter method, one HPC16400 handles Layer 2 framing for 2 basic access lines. In this manner, packets are first
identified as data or signalling type by analysis of the SAPI
field, with data packets being routed separately to a packet
switch access node. If required, signalling packets can undergo protocol conversion in the HPC to an existing internal
switch control protocol.

. . . . . .---+

r---~

JII

BACKPLANE

TP3400
TP341 0
TP3420

JII

TP3400
TP341 0
TP3420

TLiX/0008-6

Building an NT-1
An NT-1 Network Termination is defined as a Layer 1 device
only, which converts the 2-wire long-haul 'U' interface to the
limited distance 4-wire 'S' interface. It has no capability for
intercepting higher layers of the 'D' channel protocol. As
such, it is built simply by connecting a TP3420 SID, configured in NT (or Master) mode, to a TP3410 Echo-canceller
operating in Slave mode. Sharing a common 15.36 MHz

JII
JII
1

crystal, these devices pass 'B' and 'D' channel information
across the standard 4-wire interface. Layer 1 maintenance
protocols across both the 'U' and the 'SIT' interfaces,
which are as of yet not definitively specified by most adminstrations, may be handled by a low cost 4-Bit COPSTM
Microcontroller via its Microwire Interface.

TP3420

TP341 0
E-C

"SID"

MICROWIRE

lie
1
'U'

'S'

COP413C
(OPTIONAL FOR LAYER
# 1 MAINTENANCE)
TL/X/0008- 7

3-7

~National

PRELIMINARY

~ Semiconductor

microCMOS

TP3401 DASL Digital Adapter
for Subscriber Loops
General Description
The TP3401 is a complete monolithic transceiver for data
transmission on twisted pair subscriber loops. It is built on
National's advanced double poly microCMOS process, and
requires only a single + 5 Volt supply. Alternate Mark Inver·
sion (AMI) line coding, in which binary '1 's are alternately
transmitted as a positive pulse then a negative pulse, is
used to ensure low error rates in the presence of noise with
lower emi radiation than other codes such as Bi·phase
(Manchester).

stallations, including mixed gauges from #26AWG to
# 19AWG. Within certain constraints the system can oper·
ate with good margins even when Bridge Taps are present.
Three serial digital interfaces are provided on the TP3401;
one for the transfer of B1 and B2 channel information, one
for the transfer of D channel information and a third serial
MICROWIRETM compatible interface for control and status
information.

Features

Full·duplex transmission at 144 kb/ s is achieved on a single
twisted wire pair using a burst·mode technique (Time Com·
pression Multiplexed). Thus the device operates as an ISDN
'U' Interface for short loop applications, typically in a PBX
environment, providing transmission for 2 B channels and 1
D channel. On # 26 cable, the range is at least 1.8 km (6k
tt).

Complete ISDN PBX 2·Wire Data Transceiver including:
• 2 B plus D channel interface for PBX U Interface
• 144 kb/s full·duplex on 1 twisted pair using Burst Mode
• Loop range up to 6 kft (#26AWG)
• Alternate Mark Inversion coding with transmit filter and
scrambler for low emi radiation
• Adaptive line equalizer
• On·chip timing recovery, no external components
• System interface with D channel Separate from B
• 2.048 MHz clock
• Driver for line transformer
• 2 loop·back test modes
• + 5V only, 80 mW Active Power
• 5 mW idle mode

System timing is based on a Master/Slave configuration,
with the line card end being the Master which controls loop
timing and synchronisation. All timing sequences necessary
for loop activation and de·activation are generated on·chip.
A 2.048 MHz clock, which may be synchronized to the sys·
tem clock, controls all transmission·related timing functions.
The system is designed to operate on any of the standard
types of cable pairs commonly found in premise wiring in·

Block Diagram

BX--~~~~----~

LO

rs.
BCLK

...-rr--......-r--r....J

Dx--H--....
MCLK/XTAL
DCLK/DEN
~BS/rS,

:=tE~==;:~===~===~th----,

::±I:±1-.....,----.r~;;-l
cs :=ff-i..;(...,--:r--.J+-----L..,~~-.J

coCI
CCLK

iNT_I+t----'
B,

TS,/LSii
~b..-y---.·L-~~_~

D,+-t----'

GND

3·8

TLiH/92B4-1

r----------------------------------------------------------------------,~

~National

ADVANCE

INFORMATION

"CI

w

"".....

o

~ Semiconductor
TP3410 "U" Interface Transceiver
General Description

Preliminary Features

The TP341 0 is a microCMOS monolithic digital transceiver
which provides voice or data communications capability
over a twisted pair of wires in the Public Network. The device functions at either end of the subscriber loop, handling
voice and data transmissions between the Network Termination (NT) to the Central Office (CO) line card.

•
•
•
•
•

160 kb/s full duplex transmission for 2B+D
Handles all layer 1 functions
2B1Q line coding
Range at least 18 kft
#26-#19 AWG (0.4-0.9 mm) mixed gauge wire
compatibility
• 70 dB of Echo Cancellation
• Bridge Tap Equalization
• microCMOS, + 5V only

The TP341 0 has facilities to transmit and receive using the
standard ISDN 2B + D (2 64 kb/ sand 1 16 kb/ s channels)
144 kb/ s full duplex channels plus extra channels (for loop
maintenance and performance monitoring) for a total of
160 kb/s. These channels will operate over very long Central office subscriber loops of mixed gauges from #26 to
#19 AWG (0.4-0.8 mm), which may include bridge taps.
At the time of this writing, the United States T1 D1 committee for the Standardization of the U interface has not yet
finalized the performance specification.

Block Diagram

SCRAMBLER

ADAPTIVE
CANCELLATION
FILTER

ClK

3-9

TLiH/9151-1

~National

.....

PRELIMINARY

\

~ Semiconductor

J

microCMOS

TP3420 ISDN Transceiver "S" Interface Device
General Description

Features

The TP3420 (S Interface Device) is a complete monolithic
transceiver for data transmission on twisted pair subscriber
loops. It is built on National's advanced double metal microCMOS process, and requires only a single +5V supply. All
functions specified in CCITI recommendation 1.430 for
ISDN basic access at the'S' and 'T' interfaces are provided,
and the device can be configured to operate either in a TE
(Terminal Equipment), in an NT-1 or NT-2 (Network Termination) or as a PABX line-card device.

•
•
•
•
•
•
•
•
•
•

As specified in 1.430, full-duplex transmission at 192 kb/s is
provided on separate transmit and receive twisted wire pairs
using inverted Alternate Mark Inversion (AMI) line coding.
Various channels are combined to form the 192 kb/s aggregate rate, including 2 'B' channels, each of 64 kb/s, and 1
'D' channel at 16 kb/s. In addition, the TP3420 provides the
800 b/s multiframe channels for Layer 1 maintenance.
All 1.430 wiring configurations are supported by the TP3420
SID, including the "passive bus" for up to 8 TE's distributed
within 200 meters of low capacitance cable, and point-topoint and point-to-star connections up to at least 1500 meters. Adaptive receive signal processing enables the device
to operate with low bit error rates on any of the standard
types of cable pairs commonly found in premise wiring installations.

Single Chip 4 Wire 192 kb/s Transceiver
Provides all CCITI 1.430 Layer 1 Functions
Exceeds 1.430 range: 1.5 km Point-to-Point
Adaptive and Fixed Timing Options for NT-1
Clock Resynchronizer and Data Buffers for NT-2
Multiframe Channel for Layer 1 Maintenance
Selectable System Interface Formats
Microwire™ compatible serial control interface
microCMOS, + 5V only
20 Pin Package

Applications
•
•
•
•

Same Device for NT, TE and PBX Line Card
Point-to-Point Range Extended to 1.5 km
POint-to-Multipoint for all 1.430 Configurations
Easy Interface to:
LAPD Processor
HPC16400
HPC16400
Terminal Adapter
Codec/Filter COMBOTM
TP305417
"U" Interface Device
TP3410
Line Card Backplanes

Block Diagram
XTAL2 t.lCLK/XTAL

Vee

rt,

SYSTEM
INTERFACE
o-CHANNEL
ACCESS

BCLK
Bx

TRANSMIT
FRAt.tING
AND
At.ll CODER

B,
FSa
FS b

......--Lo·

DEN x

CONTROL
INTERFACE
LSD
CCLK --""'"
CI --"","
CONTROL

CO

cs

iNT

L___r----..J

---+I

L.tJ
GND

3-10

TL/H/9143-1

::t:

~National

PRELIMINARY

."

...

o

0)

~ Semiconductor

o
CO
w
......

HPC16083/HPC26083/HPC36083/HPC46083/HPC160431
HPC26043/HPC36043/HPC46043/HPC16003/HPC260031
HPC36003/HPC46003 High-Performance Microcontrollers

."

::t:

o

~
o

CO

w
......

::t:

."

General Description

Features

The HPC16083, HPC16043 and HPC16003 are members of
the HPCTM family of High Performance microControliers.
Each member of the family has the same core CPU with a
unique memory and I/O configuration to suit specific applications. The HPC16083 and HPC16043 have 8k and 4k
bytes of on-chip ROM respectively. The HPC16003 has no
on-chip ROM and is intended for use with external memory.
Each part is fabricated in National's advanced microCMOS
technology. This process combined with an advanced architecture provides fast, flexible I/O control, efficient data manipulation, and high speed computation.
The HPC devices are complete microcomputers on a single
chip. All system timing, internal logic, ROM, RAM, and I/O
are provided on the chip to produce a cost effective solution
for high performance applications. On-chip functions such
as UART, up to eight 16-bit timers with 4 input capture registers, vectored interrupts, WATCHDOGTM logic and MICROWIRE/PLUSTM provide a high level of system integration.
The ability to address up to 64k byles of external memory
enables the HPC to be used in powerful applications typically performed by microprocessors and expensive peripheral
chips. The term "HPC16083" is used throughout this datasheet to refer to the HPC16083, HPC16043 and HPC16003
devices unless otherwise specified.

• HPC family-core features:
- 16-bit architecture, both byte and word
- 16-bit data bus, ALU, and registers
- 64k bytes of external memory addressing
- FAST-240 ns for fastest instruction when using
17.0 MHz clock, 134 ns at 30 MHz
- High code efficiency-most instructions are single
byte
- 16 x 16 multiply and 32 x 16 divide
- Eight vectored interrupt sources
- Four 16-bit timer/counters with 4 synchronous outputs and WATCHDOG logic
- MICROWIRE/PLUS serial I/O interface
- CMOS-very low power with two power save modes:
IDLE and HALT
• UART-full duplex, programmable baud rate
• Four additional 16-bit timer/counters with pulse width
modulated outputs
• Four input capture registers
• 52 general purpose I/O lines (memory mapped)
• 8k or 4k byles of ROM, 256 bytes of RAM on chip
(HPC16083, HPC16043)
• ROM less version available (HPC16003)
• Commercial (O°C to + 70°C), industrial (-40°C to
+ 85°C), automotive (- 40°C to + 105°C)' and military
( - 55°C to + 125°C) temperature ranges

The microCMOS process results in very low current drain
and enables the user to select the optimum speed/power
product for his system. The IDLE and HALT modes provide
further current savings. The HPC is available in 68-pin
PLCC, LCC and PGA packages.

Block Diagram

o
CO
w
......
::t:

."

o

"'"

0)

o
w
......
::t:
CO

."

...

o

0)

o

"'"

~
::t:

."

oN

0)

o

"'"

w
......
::t:

."

oW

0)

o

"'"

w
......
::t:

."

"'"
"'"
::t:
0)

o

w
......

r-----------------------~

, 'tt

0)

o

(HPC16083 with 8k ROM shown)
ROYliilliiimf STATUS

oW

."

...

o

eKI CKOCK2

0)

o
o
w
......

::t:

."

oN

0)

o

o
w
......

::t:

."

oW

0)

o

o
w
......
::t:

."

o
TL/DD/BB01-l

"'oo"

0)

w
3-11

o

~
U)
-=r
o
a..

J:
......

o
o
-=r
U)

(f)

o
a..

J:
......

o
o
-=r
U)

....

oa..

J:

r----------------------------------------------------------------,

'?'A National

ADVANCE

INFORMATION

~ Semiconductor
HPC 16400/HPC36400/H PC46400 High-Performance
Microcontrollers with HOLC Controller
General Description

Features

The HPC16400 is a member of the HPCTM family of High
Performance microControliers. Each member of the family
has the same identical core CPU with a unique memory and
1/0 configuration to suit specific applications. Each part is
fabricated in National's advanced microCMOS technology.
This process combined with an advanced architecture provides fast, flexible 1/0 control, efficient data manipulation,
and high speed computation.

• HPC family-core features:
- 16-bit data bus, ALU, and registers
- 64 kbytes of external memory addressing
- FAST!-20.0 MHz system clock
- High code efficiency
- 16 x 16 multiply and 32 x 16 divide
- Eight vectored interrupt sources
- Four 16-bit timerlcounters with WATCHDOG logic
- MICROWIRE/PLUS serial 1/0 interface
- CMOS-low power with two power save modes
• Two full duplex HDLC channels
- Optimized for X.25 and LAPD applications
- Programmable frame address recognition
- Up to 4.65 Mbps serial data rate
- Built in diagnostics
• Programmable interchip serial data decoder
• Four channel DMA controller
• UART-full duplex, programmable baud rate
(up to 312.5 kBaud)
• 544 kbytes of extended addressing
• Easy interface to National's DASL, 'U' and'S' transceivers-TP3400, TP3410 and TP3420
• Industrial (-40'C to +85'C) and military (-55'C to
+ 125'C) temperature ranges

The HPC16400 has 4 functional blocks to support a wide
range of communication application-2 HDLC channels, 4
channel DMA controller to facilitate data flow for the HDLC
channels, programmable serial interface and UART.
The serial interface decoder allows the 2 HDLC channels to
be used with devices using interchip serial link for point-topoint & multipoint data exchanges. The decoder generates
enable signals for the HDLC channels allowing multiplexed
D and B channel data to be accessed.
The HDLC channels manage the link by providing sequencing using the HDLC framing along with error control based
upon a cyclic redundancy check (CRC). Multiple address
recognition modes, and both bit and byte modes of operation are supported.
The HPC16400 is available in 68-pin PLCC, LCC, LOCC and
PGA packages.

Block Diagram
·RDyiHLD RESET STATUS" EXM -

- - wo -------CKl -cKe CK2'

~

! ! tt!
3

TI~ER/REG.

fIDlE1

LOGIC

~

rHAiJl

~

5P

PC

51

50

PORT I

5K

PORT A

PORT 8

PORT R

CORE CPU
. - - - - - - - - - - - - - - - - - - - - - - - - - - ______ 4

TL/DDIBB02-1

3-12

Cii

c
z
cCD

ISDN DEFINITIONS

;5"

:::;:

0"

"B" Channel, or DSO Channel

"universal portability point" for ISDN terminals from any
manufacturer in the world.

A "S" (for Sasic) channel is a 64 kb/s full-duplex transparent data channel. It is octet (= byte) oriented, that is it can
be considered as a channel bearing 8k octets/sec. "S"
channels are synchronized to the network and are generally
circuit-switched (not packet switched). The 64 kb/s rate is
also known as a DSO interface.

Primary Access to the ISDN
Primary access is provided at a DSI interface, consisting of
either:
1. Twenty-three "S" channels plus one 64 kb/s "D" channel at 1.544 Mb/s (North America), or:

"0" Channel

2. Thirty "S" channels plus one 64 kb/s "D" channel at
2.048 Mb/s (Europe and Rest of World).

The "D" channel is a packet-mode message-oriented channel on which the data-link layer (layer 2) protocol is carried
in HDLC frames. At a basic access point the "D" channel
runs at 16 kb/ s, while at a primary access point it runs at
64 kb/s. (There is no reason why a "D" channel could not
be defined to run at even higher speeds, e.g., 1.544 or
2.048 Mb/ s, though that does not seem to be a part of
current standardization work.)
Three types of data may be handled by a "D" channel:

CCITT specification 1.431 defines the multiplexing and control schemes for primary access.
TE-Terminal Equipment

Two sub-groups of terminals are defined:
1. TE-l is a full ISDN terminal which is synchronized to the
network channels (not just the far-end terminal) and uses
LAPD signaling. It connects to the ISDN at the "S" reference point, which is intended to be the point in the network at which any type of basic access terminal can be
connected, i.e., the "portability" point.
2. TE-2 is a non-ISDN terminal, generally one of today's
asynchronous or synchronous terminals operating at
rates < 64 kb/s. This includes terminals which have
RS232C, RS449, V.21, V.24, V.35, X.21 or X.25 packetmode interfaces. Each type of interface must be adapted
from the "R" reference point to the "S" reference point
by means of a Terminal Adapter (TA).

1. Type "s" (signaling) using layer 3 of the LAPD protocol.
2. Type "p" (packet) user's packet-oriented data.
3. Type "t" (telemetry) data, typically alarms and energy
monitoring functions operating at a low scan rate.
The data type is identified by the SAP I (Service Access
Point Identifier) in the HDLC extended address field.
Basic Access to the ISDN
Two independent "S" channels (SI and S2) together with a
"D" channel operating at 16 kb/s form the basic access
structure. A minimum transmission rate of 144 kb/s full duplex is therefore required for basic access transport, although in some applications additional bits are used for localized functions.
Figure 1 shows the names of the functional blocks and interfaces as defined in CCITT specifications.
The 'U' interface is the single twisted pair loop between a
customer's premises and the local central office. To transmit 144 kb/s or more full-duplex over this link, which may be
several miles long and have over 40 dS of attenuation of the
data signal, requires a complex transceiver. Adaptive echocancellation techniques are necessary and, although the
transmission format is not yet specified by CCITT, considerable work is in progress in the U.S. Tl Dl.3 ISDN Study
Group to establish a standard for North America. 160 kb/s
is the likely transmission rate, while the line code will be
2S1Q.
The'S' interface passes the same 2 'S' channels and the
'D' channel on to the terminals, together with some additional bits used for synchronization, contention control in the
'D' channel, and other housekeeping functions. CCITT
specification 1.430 defines the physical layer of this interface. A transceiver is required for transmission at the 192
kb/ s bit rate, over separate transmit and receive twisted
pairs (which already exist in both office and residential telephone wiring within the premises in many countries). Alternate Mark Inversion coding is used.

TA-Terminal Adapter

A terminal adapter converts either asynchronous or synchronous data from non-ISDN terminals into data which is
synchronized with ISDN S or D channels. The data rate
must be adapted by means of stuffing extra bits in a prescribed pattern into the bit stream to adapt the data rate to
64 kb/s.
Terminal adaption also requires the conversion of modem
handshaking signals to ISDN compatible signaling, and currently there are 2 competing schemes: either using LAPD in
the D channel (Le. out-of-band signaling) or applying LAPDtype messages but passing them end-to-end via the S channel (i.e. in-band). There are strong arguments for both methods, mostly concerned with how signaling is converted at
the boundary between an ISDN and today's network ("interworking"), and it remains to be seen which will win as a
standard.
NT-Network Termination
The NT terminates the network at the user's end of the 2
wire loop at the customer's premises. It converts the "U"
interface to the "S" and "T" interface (see Figure 1) and
acts as the "master" end of the user's passive bus. Sand D
channels must pass transparently through the NT, and there
is no capability for intercepting LAPD messages in the NT.

Thus a typical NT for basic access will consist of an'S'
interface transceiver and a 'U' interface transceiver connected back-to-back with appropriate power supplies and
fault monitoring capability.

2 additional pairs are specified as an option, 1 for power and
1 for spare, making this an 8 wire interface. A plug and jack
have been standardized so that the'S' interface can be a

An NT can also be an intelligent controller such as a PASX,
LAN access node, or a terminal cluster controller.
3-13

:::l
UI

0.-------------------------------------------------------------~

C

o

LT-Line Termination

Layer 5: Session layer.

·c

Typically, the LT consists of the "U" interface tranceiver
and power feeding functions on the ISDN line card. These
functions must interface to the switch at the "V" reference
point, which is not currently being standardized by CCITI. It
could be a proprietary backplane interface or a nationally
specified interface which would allow the LT to be physically
and electrically separated from the switch.

Layer 6: Presentation layer.
Layer 7: Application layer.

:;::::;

~

z
c

~

These layers are generally running on a high level machine,
and discussion regarding this machine is outside the scope
of this document.

LAPD
Link Access Protocol in the "0" channel is the name given
to the packet-mode Signaling protocol defined in CCITI
specs 0920 and 0921 for the data link layer (layer 2) and
0930 and 0931 for the network layer (layer 3 in the ISO 7
layer reference model). At layer 2, LAPO uses the HOLC
framing format. This protocol defines the bits, bytes and sequence of states necessary between the user and the network to establish, control and terminate calls using any of
the 100 or more types of services which may be available
via an ISDN. If the users at both ends of the call are connected to the ISDN and there is a through path for the 0
channel then end-to-end call control is available.
Because of this extensive range of services, implementation
of full LAPO requires considerable memory and processing
power. Standards work has recently focused on definition of
a minimal subset of LAPO to cover the basic requirements
of call control.

ISO Layered Protocol Model
The ISO (International Standards Organization) has defined
a 7 layer model structure which describes convenient break
pOints between various parts of the hardware and software
in any data communications system.
Layer 1: Physical layer, that is the hardware which transports bits across interfaces. This includes ISDN transceivers, modems etc., power supplies, methods of activating
and de-activating a transmission link, and also the transmission medium itself, such as wire, fiber, plugs and sockets,
etc.
Layer 2: Data Link layer, which describes a basic framing
structure and bit assignments to enable higher layer messages to be passed across a physical link. HOLC framing,
addressing and error control are the major elements of this
layer in ISDN.
Layer 3: Network layer, that is those parts of a message
associated with setting-up, controlling and tearing-down a
call through the network. These are all software control
functions, and generally this is the highest layer in the ISO
protocol model which is considered in chip development.

Activation/De-activation
Activation is the process of powering up the'S' and 'U'
interfaces from their standby (i.e. de-activated) states and
sending specific signals across the interfaces to get the
whole loop synchronized to the network. A small state machine in each TE and the NT controls this sequence of
events, and uses timers to ensure that, if the activation attempt should fail for any reason, the user or network is alerted. At the end of a call an orderly exit from the network is
effected by sending de-activation sequences before any
equipment can power-down.

The top 4 layers relate to the structure of the actual application programs;
Layer 4: Transport layer, concerned with defining sources
and destinations within an operating system for the transfer
of application programs.

3-14

R

S

S

T

U

~

~

~

~

~

r--------------------------.
,,

-<01
TE2

NT1

NT2

~

~

ET

LT

1[>-

-l2J1
X21 etc.

~

v

I~

TA

z:

LOOP

U

ECHO-CANCELLER FOR CENTRAL OFFICE OR
LOWER COST SOLUTIONS FOR
PBX e.g. BURST-MODE.

-<01

UP TO 8 TERMINALS

'"

TEl

-l2J1
loon lOon
DTE

PASSIVE
BUS

OCE (DLT)

OCE (DLI)
TC07-1

TE: Terminal Equipment
TA: Terminal Adaptor (Protocol Conversion & Rate Adaption for Non-ISDN Terminals)
NT2: Network Termination 2 (Protocol for Link Control, MUX/DEMVX etc)

NT1: Network Termination 1 (Loop Transceiver, Power Extraction)
LT: Line Termination (Loop Transceiver, Power Feed)
ET: Exchange Termination (Protocol Handling, MUX/DEMUX, Switching)

FIGURE 1. The ISDN Interfaces

SUO!I!U!Jaa NaSI

Section 4
UARTs

Section 4 Contents
INS8250/INS8250-B Universal Asynchronous Receiver/Transmitter. . . . . . . . . . . . . . . . .. .. . .
NS16450/INS8250AINS16C450/INS82C50A Universal Asynchronous Receiver/Transmitter
NS16550A Universal Asynchronous Receiver/Transmitter with FIFOs. . . . . . . . . . . . . . . . . . . . .
AN-491 The NS16550A: UART Design and Application Considerations. . . . . . . . . . . . . . . . . . . .
AN-493 A Comparison of the INS8250, NS16450 and NS16550A Series of UARTs . . . . . . . . . .
NSC858 Universal Asynchronous Receiver/Transmitter. . .. . . . . . . . . . . . . .. . . . . .. .. . .. . . . .

4-2

4-3
4-19
4-36
4-58
4-85
4-93

~National

~ Semiconductor
INS8250, INS8250-B Universal
Asynchronous Receiver ITransmitter
General Description

Features

Each of these parts function as a serial data input/output
interface in a microcomputer system. The system software
determines the functional configuration of the UART via a
TRI-STATE® 8-bit bidirectional data bus.

• Easily interfaces to most popular microprocessors.
• Adds or deletes standard asynchronous communication
bits (start, stop, and parity) to or from serial data
stream.
• Holding and shift registers eliminate the need for precise synchronization between the CPU and the serial
data.
• Independently controlled transmit, receive, line status,
and data set interrupts.
• Programmable baud generator allows division of any input clock by 1 to (2 16 - 1) and generates the internal
16 X clock.
• Independent receiver clock input.
• MODEM control functions (CTS, RTS, DSR, DTR, RI,
and DCD).
• Fully programmable serial-interface characteristics:
- 5-, 6-, 7-, or 8-bit characters
- Even, odd, or no-parity bit generation and detection
- 1-, 1'/2-, or 2-stop bit generation
- Baud generation (DC to 56k baud).
• False start bit detection.
• Complete status reporting capabilities.
• TRI-STATE TTL drive capabilities for bidirectional data
bus and control bus.
• Line break generation and detection.
• Internal diagnostic capabilities:
- Loopback controls for communications link fault
isolation
- Break, parity, overrun, framing error simulation.
• Fully prioritized interrupt system controls.

The UART performs serial-to-parallel conversion on data
characters received from a peripheral device or a MODEM,
and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete
status of the UART. Status information reported includes
the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity,
overrun, framing, or break interrupt).
The UART includes a programmable baud rate generator
that is capable of dividing the timing reference clock input
by divisors of 1 to (2 16 -1), and producing a 16 x clock for
driving the internal transmitter logic. Provisions are also included to use this 16 x clock to drive the receiver logic. The
UART includes a complete MODEM-control capability and a
processor-interrupt system. Interrupts can be programmed
to the user's requirements minimizing the computing required to handle the communications link.
National's INS8250 universal asynchronous receiver transmitter (UART) is the unanimous choice of almost every PC
and add-on manufacturer in the world. The INS8250 is a
programmable communications chip available in a standard
40-pin dual-in-line and a 44-pin PCC package. The chip is
fabricated using N-channel silicon gate technology.

Connection Diagram
INS8250
INS8250·B

TO RS·232
INTERFACE

•

"0"

"1"

TL/C/9329-1

4-3

.

m r--------------------------------------------------------------------------,
&I)
Table of Contents
C'I
co
1.0 ABSOLUTE MAXIMUM RATINGS
8.0 REGISTERS
en

CI

z

:::::::
CI
&I)

8.2 Typical Clock Circuits

C'I

3.0 AC ELECTRICAL CHARACTERISTICS

en

4.0 TIMING WAVEFORMS

co

~

8.1 Line Control Registers

2.0 DC ELECTRICAL CHARACTERISTICS

8.3 Programmable Baud Generator
8.4 Line Status Register
8.5 Interrupt Indentification Register

5.0 BLOCK DIAGRAM

8.6 Interrupt Enable Register

6.0 PIN DESCRIPTIONS

8.7 Modem Control Register
8.8 Modem Status Register

6.1 Input Signals
6.2 Output Signals

9.0 TYPICAL APPLICATIONS

6.3 Inputl out Signals

10.0 ORDERING INFORMATION
7.0 CONNECTION DIAGRAMS
11.0 RELIABILITY INFORMATION

4·4

z

en
CD

1.0 Absolute Maximum Ratings

N
UI

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

All Input or Output Voltages
with Respect to Vss

Temperature Under Bias

Note: Maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits is not intended and should be limited to those conditions
specified under DC electrical characteristics.

Power Dissipation

O°C to +70°C
- 65°C to + 150°C

Storage Temperature

-0.5V to + 7.0V
400mW

2.0 DC Electrical Characteristics
TA = O°C to + 70°C, Vee = +5V ±5%, Vss = OV, unless otherwise specified.
Symbol

Parameter

INS8250

Conditions

Min

INS82S0-B
Max

Min

Units

Max

VILX

Clock Input Low Voltage

-0.5

0.8

-0.5

0.8

VIHX

Clock Input High Voltage

2.0

Vee

2.0

Vee

V

VIL

Input Low Voltage

-0.5

0.8

-0.5

0.8

V

2.0

Vee

2.0

Vee

V

0.4

V

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

IOH = -1.0 mA (Note 1)

ledAV)

Avg. Power Supply
Current (Veel

Vee = 5.25V, T A = 25°C
No Loads on output
SIN, DSR, DCD,
CTS, RI = 2.4V
All other inputs = O.4V

Input Leakage

leL

Clock Leakage

loz

TRI-STATE Leakage

Capacitance TA =

2.4

V

80

80

mA

±10

±10

",A

±10

±10

",A

±20

±20

",A

25°C, Vee = vss = OV

Parameter

Conditions

Clock Input Capacitance

CXOUT

Clock Output Capacitance

fe = 1 MHz

CIN

Input Capacitance

COUT

Output Capacitance

Unmeasured pins
returned to V ss

apply to

2.4

Vee = 5.25V, Vss = OV
VOUT = OV,5.25V
1) Chip deselected
2) WRITE mode,
chip selected

CXIN

Note 1: Does not

0.4

Vee = 5.25V, Vss = OV
All other pins floating.
VIN = OV, 5.25V

IlL

Symbol

IOL = 1.6 mA on all (Note 1)

V

XOUT.

4·5

Min

Typ

Max

Units

15

20

pF

20

30

pF

6

10

pF

10

20

pF

Q

::::
Z

en
CD

N
UI
Q

•
\XI

3.0 AC Electrical Characteristics TA = O'Cto +70'C, Vcc =
Symbol

Parameter

Conditions

+5V ±5%

INSB250
Min

Max

INSB250-B
Min

Units

Max

tAOS

Address Strobe Width

90

120

ns

tAH

Address Hold Time

0

60

ns

tAR

RD/RD Delay from Address

110

110

ns

tAS

Address Setup Time

110

110

ns

tCH

Chip Select Hold Time

0

60

ns

tcs

Chip Select Setup Time

110

110

tesc

Chip Select Output Delay from Select

(Note 1)

@100 pF loading (Note 1)

tCSR

RD/RD Delay from Chip Select

tess

Chip Select Output Delay from Strobe

tcsw

WR/WR Delay from Select

tOH

Data Hold Time

tos

Data Setup Time

tHZ

RD/RD to Floating Data Delay

tMR

Master Reset Pulse Width

tRA

Address Hold Time from RD/RD

tRC

Read Cycle Delay

tRCS

Chip Select Hold Time from RD/RD

tRD

RD/RD Strobe Width

tRDA

Read Strobe Delay

tRDO

RD/RD to Driver Disable Delay

tRVO

Delay from RD/RD to Data

tWA

Address Hold Time from WR/WR

twc

Write Cycle Delay

twcs

Chip Select Hold Time from
WR/WR

tWOA

Write Strobe Delay

tWR

WR/WR Strobe Width

tXH

Duration of Clock High Pulse

External Clock (3.1 MHz Max.)

tXL

Duration of Clock Low Pulse

External Clock (3.1 MHz Max.)

RC

Read Cycle

WC

Write Cycle

= tAR + tOIW +
= tO~A + toow

(Note 1)

200
110
0

(Note 1)

(Note 1)

0

150

ns

ns

160

160

ns

60

100

ns

0

350
150

10
(Note 1)

ns

110
150

175
@100 pF loading (Note 3)

ns
200

0

ns
150

ns

10

p's
ns

50

50

1735

1735

ns

50

50

ns

175

350

ns

0

0

ns

@100pF loading (Note 3)

150

250

ns

@100pFloading

250

300

ns

(Note 1)

50

50

ns

1785

1785

ns

50

50

ns

50

50

ns

175

350

ns

140

140

ns

140

140

ns

tRC

2000

2205

ns

+ twc

2100

2305

ns

(Note 1)

Baud Generator
1

2 16 -1

Baud Divisor
Baud Output Positive Edge Delay

100 pF Load

250

250

tBLD

Baud Output Negative Edge Delay

100 pF Load

250

250

tHW

Baud Output Up Time

fx

tLW

Baud Output Down Time

fx

= 3 MHz,'" 3, 100 pF Load
= 2 MHz,'" 2, 100 pF Load

1

2 16 -1

N
tBHO

ns
ns

330

330

ns

425

425

ns

Receiver
tRINT

Delay from RD/RD
(RD RBR or RD LSR)
to Reset Interrupt

100 pF Load
1000

1000

ns

tsco

Delay from RCLK to Sample Time

2000

2000

ns

tSINT

Delay from Stop to Set Interrupt

2000

2000

ns

Note 1: Applicable only when ADS is tied low.
Note 2: Charge and discharge time is determined by VOL. VOH and the external loading.

4-6

3.0 AC Electrical Characteristics TA =
Symbol

Parameter

O·Cto +700C, Vee = +5V ±5% (Continued)
INS82C50-B

INS8250

Conditions

Min

Min

Max

Units

Max

Transmitter
tHR

Delay from WR/WR (WR THR)
to Reset Interrupt

100 pF Load

tlR

Delay from RD/RD (RD IIR) to Reset
Interrupt (THRE)

tlRS

Delay from InitiallNTR
Reset to Transmit Start

lsi

Delay from Initial Write to Interrupt

lss

Delay from Stop to Next Start

lsTI

Delay from Stop to Interrupt (THRE)

100 pF Load

1000

1000

ns

1000

1000

ns

16

16

BAUDOUT
Cycles

50

50

BAUDOUT
Cycles

1000

1000

ns

8

8

BAUDOUT
Cycles

1000

1000

ns

1000

1000

ns

1000

1000

ns

Modem Control
tMDO

Delay from WR/WR (WR MCR) to
Output

100 pF Load

tRIM

Delay to Reset Interrupt from RD/RD
(RDMSR)

100 pF Load

lslM

Delay to Set Interrupt from MODEM Input

100 pF Load

4.0 Timing Waveforms (All timings are referenced to valid 0 and valid 1)
External Clock Input (3.1 MHz Max.)
2.4V

AC Test Points
2.4V--

---t:=j-'XH

2.0V
(IIOtIlt

2.0V
XtN
O.4V

(NOTE2t
O.IV

OM
O.IV

~'XL~

TL/C/9329-3

TLlC/9329-2

Note 1: The 2.4V

and O.4V levels are the Yoltages that the Inputs are driven to during AC testing.
Note 2: The 2.0V and O.8V levels are the Yoltages at which the timing tests are made.
BAUDOUT Timing

I'

'I

N

J1J1JLJL

XII

'IHD~

f-'BLD-j

r-

-I

I-'HW

~LJ1JlJ1JU1
(+11
-.j f--'IHD

--I I---taLD

-I ~tLW

tLW~

D1IIIlI1IT
(+2)

f. ..".j

--I I--'ILD --1 !--'IHD

f.'HII+-'L,,---I

D1IIIlI1IT
(+3)

-I

I-taLD

--I

I-'BHD

~~
(+N.N>3)

I

I-

4-7

i,--I"

,1"" - 2XDUTCYtUS

'1"'-(11-2)XINCYCUS

TLlC/9329-4

.

ID
<:)
&I)

C'I

4.0 Timing Waveforms

(Continued)

co
tn

Write Cycle

Z

:::::
<:)
&I)

C'I

co
tn

a!!:

I--'A'=:±.J'AH
A"Al,A,:==X VALID 1

X,...----------:X=

I
I
I

CSz. CSt, cSo

~~

1---j'WA'
I-X'r-'Wcs'-I-

--r--~

I

'CM'

....

~C---T-----

'W" =1=-.:=Fc'WC-~---':---·1

---'x

ACTlV'

WIi,WR _ _

X

E

:

1

.;-

I

Rl!.RD

I-'OS -1-'DH -I

o~~1~ ------------~(

VALID DATA

E

::

}--

'Applicable Only When ADS is Tied Low.

TL/C/9329-5

Read Cycle

==x

1--== fAS --=±f tAH

A"A"AD

VALID

I Xr------------;X=

I i--'C,=H'CH

"fi2. CS1, cSo

H,RA'
I-x'--

I

~

,

CSOUT

-'1Lt=-.C'R'

'RC"--I
~:T-

I

- - - T- - --

-IAR'~ 'ADA ~~.AD -I~-,R-C====-=--=--.j,-;-I---·I
ACTIVE xr------t:~:.......:......-~

X

RD. RD

_ _- - J

~.WR

___________

OOIS

:~

+

'I _ _ _ _ _~I' _ _ _ _ _~<,I~----~
~

lH\DD
IRVO....J

rrHtHZ

DATA _____________--____
DO-D1

c::.:::J

• Applicable Only When ADS is Tied Low.

TL/C/9329-6

4-8

4.0 Timing Waveforms (Continued)
Receiver Timing
••u~'

.CL.. -------~-II_

I

SAIIPLECLk

LJ
...D

---------------------,U

(REC!~~ \""_ST_._.T_C
....___D..~T_._"_TS_I._-_I}___
.---~~--~\TI---r---r--rl--,----r~

SAMPLE
CLK

-l
INTERRUPT
(DATA RlADY OR

RCVREARI _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...I

~m---------------------------------------~
(IIEAII.Et

..

::;:-----------------------~
IN0lE2,

TL/C/9329-7

Transmitter Timing

OUT~~~trT\

\

--------..1'I.s~

I

START

~ST~A·~tf~-------

DATA 15-81

~~TI-J

INTERRUPT
ITHAE)

Wll,WR
IWRTHRI

INOlEIl

_~"R~'SI--'I
J\r--j
1

~
I

-I'"R j.:
r\

' -_ _ _ _ _ __'

\._ _ _ _ _ _ _ _ _ _ _ _ _ _-:--:-_

1.1rL
-1 '

IID,RD

IRDHRI _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
(NDTE21

TLlC/9329-B

MODEM Controls Timing

Wl~

I
~
\
I-..\
D.-~:~I-------I- . . . '---.7",-------

~~~:

\

~~

CTI.IIIII.mi

'ITERRU'Y

'I

!

\1 r \ .I

jr---.....\

(:: ., -~I----'-~ A'---:-~_I-,,,___J·~rt.t: I~
(NDTE2)

\ ,r--I

-

iii

Nota 1: See Write Cycle Timing
Note 2: See Read Cycle Timing

4-9

TLlC/9329-9

5.0 Block Diagram
INTERNAL
DATA IUS
D7· DD

RUK

.

A,

A,
,so

DDIS
CSOUT
XI.
XOUT

m
m

6TJi

POWER{~+5V

SUPPLY

DiR
DCD

~GND

III
jjjjfi

iiiiT'l
13

"""
TL/C/9329-IO

Nota: Applicable pinout numbers are included within parenthesis.

6.0 Pin Descriptions
The following describes the function of all UART, pins.
Some of these descriptions reference internal circuits.
In the following descriptions, a low represents a logic 0 (OV
nominal) and a high represents a logic 1 (+2.4V nominal).

Write (WR, WR), Pins 19 and 18: When WR is high or WR
is low while the chip is selected, the CPU can write control
words or data into the selected UART register.
Nota: Only an active WR or Wi'! input is required to transfer data to the
UART during a write operation. Therefore, tie either the WR input perma·
nently low or the WI'! input permanently high, when tt is not used.

6.1 INPUT SIGNALS
Chip Select (CSO, CS1, CS2), Pins 12-14: When CSO and
CSt are high and CS2 is low, the chip is selected. This
enables communication between the UART and the CPU.
The positive edge of an active Address Strobe signal latches the decoded chip select signals, completing chip selection. If ADS is always low valid chip selects should stabilize
according to the tcsw parameter.
Read (RD, RD), Pins 22 and 21: When RD is high or RD is
low while the chip is selected, the CPU can read status
information or data from the selected UART register.

Address Strobe (ADS), Pin 25: The positive edge of an
active Address Strobe (ADS) signal latches the Register Select (AO, A1, A2) and Chip Select (CSO, CS1, CS2) signals.
Note: An active AD!! input is required when the Register Select (AO. A I. A2)
signals are not stable for the duration of a read or write operation. If not
required. tie the AD!! Input permanently low.

Register Select (AD, AI, A2), Pins 26-28: Address signals
connected to these 3 inputs select a UART register for the
CPU to read from or write to during data transfer. A table of
registers and their addresses is shown below. Note that the
state of the Divisor Latch Access Bit (DLAB), which is the
most significant bit of the Line Control Register, affects the
selection of certain UART registers. The DLAB must be set
high by the system software to access the Baud Generator
Divisor Latches.

Note: Only an active RD or RD input is required to transfer data from the
UART during a read operation. Therefore, tie either the RD input permanent·
Iy low or the Rl5 input permanently high, when tt is not used.

4-10

6.0 Pin Descriptions (Continued)
OLAB

A2

A1

Ao

0

0

0

0

0

0
0

0

1

1

0

X
X
X
X
X
1

0

1

1

1
1
1

0
0

0

1

0

0

0
0

1

0

0

1

1

since the previous reading of the MODEM Status Register.
DCD has no effect on the receiver.

Register
Receiver Buffer (read),
Transmitter Holding
Register (write)
Interrupt Enable
Interrupt Identification
(read only)
Line Control
MODEM Control
Line Status
MODEM Status
Divisor Latch
(least significant byte)
Divisor Latch
(most significant byte)

Nota: Whenever the DCD bit of the MODEM Slatus Register changes state,
an interrupt is generated H the MODEM Slatus Interrupt is enabled.

Ring Indicator (Ai), Pin 39: When low, this indicates that a
telephone ringing signal has been received by the MODEM
or data set. The Ai signal is a MODEM status input whose
condition can be tested by the CPU reading bit 6 (RI) of the
MODEM Status Register. Bit 6 is the complement of the Ai
signal. Bit 2 (TERI) of the MODEM Status Register indicates
whether the Ai input signal has changed from a low to a
high state since the previous reading of the
MODEM Status Register.
Note: Whenever the RI bit of the MODEM Status Register changes from a
high to a low slate, an interrupt Is generated H the MODEM Status
Interrupt is enabled.

Vee, Pin 40: + 5V supply.
Vss, Pin 20: Ground (OV) reference.

Register Addresses

6.2 OUTPUT SIGNALS
Data Terminal Ready (OTR), Pin 33: When low, this informs the MODEM or data set that the UART is ready to
establish a communications link. The DTR output signal can
be set to an active low by programming bit 0 (DTR) of the
MODEM Control Register to a high level. A Master Reset
operation sets this signal to its inactive (high) state.

Master Reset (MR), Pin 35: When this input is high, it clears
all the registers (except the Receiver Buffer, Transmitter
Holding, and Divisor Latches), and the control logic of the
UART. The states of various output signals (SOUT, INTR,
OUT 1, OUT 2, RTS, DTR) are affected by an active MR
input. (Refer to Table I.).
Receiver Clock (RCLK), Pin 9: This input is the 16 x baud
rate clock for the receiver section of the chip.

Request to Send (RTS), Pin 32: When low, this informs the
MODEM or data set that the UART is ready to exchange
data. The RTS output signal can be set to an active low by
programming bit 1 (RTS) of the MODEM Control Register. A
Master Reset operation sets this signal to its inactive (high)
state.
Output 1 (OUT 1), Pin 34: This user-designated output can
be set to an active low by programming bit 2 (OUT 1) of the
MODEM Control Register to a high level. A Master Reset
operation sets this signal to its inactive (high) state. In the
XMOS parts this will achieve TTL levels.
Output 2 (OUT 2), Pin 31: This user-designated output can
be set to an active low by programming bit 3 (OUT 2) of the
MODEM Control Register to a high level. A Master Reset
operation sets this signal to its inactive (high) state. In the
XMOS parts this will achieve TTL levels.

Serial Input (SIN), Pin 10: Serial data input from the communications link (peripheral device, MODEM, or data set).
Clear to Send (CTS), Pin 36: When low, this indicates that
the MODEM or data set is ready to exchange data. The CTS
signal is a MODEM status input whose conditions can be
tested by the CPU reading bit 4 (CTS) of the MODEM Status
Register. Bit 4 is the complement of the CfS signal. Bit 0
(DCTS) of the MODEM Status Register indicates whether
the CTS input has changed state since the previous reading
of the MODEM Status Register. CTS has no effect on the
Transmitter.
Nota: Whenever the CTS bit of the MODEM Status Register changes state,
an interrupt is generated H the MODEM Status Interrupt is enabled.

Data Set Ready (OSR), Pin 37: When low, this indicates
that the MODEM or data set is ready to establish the communications link with the UART. The DSR signal is a
MODEM status input whose condition can be tested by the
CPU reading bit 5 (DSR) of the MODEM Status Register. Bit
5 is the complement of the DSR signal. Bit 1 (DDSR) of the
MODEM Status Register indicates whether the DSR input
has changed state since the previous reading of the
MODEM Status Register.

Chip Select Out (CSOUT), Pin 24: When high, it indicates
that the chip has been selected by active, CSO, CS1, and
CS2 inputs. No data transfer can be initiated until the
CSOUT signal is a logic 1. CSOUT goes low when the
UART is deselected.
Driver Disable (OOIS), Pin 23: This goes low whenever the
CPU is reading data from the UART. It can disable or control
the direction of a data bus transceiver between the CPU
and. the UART (see Typical Interface for a High Capacity
Data Bus).

Note: Whenever the DSR bH of the MODEM Status Register changes slate,
an interrupt is generated if the MODEM Status Interrupt is enabled.

Baud Out ('''B'''A''U'''O'''O''U""'n, Pin 15: This is the 16 x clock signal from the transmitter section of the UART. The clock rate
is equal to the main reference oscillator frequency divided
by the specified divisor in the Baud Generator Divisor Latches. The BAUDOUT may also be used for the receiver section by tying this output to the RCLK input of the chip.

Data Carrier Detect (DCO), Pin 38: When low, indicates
that the data carrier has been detected by the MODEM or
data set. The DCD signal is a MODEM status input whose
condition can be tested by the CPU reading bit 7 (DCD) of
the MODEM Status Register. Bit 7 is the complement of the
l5CD signal. Bit 3 (DDCD) of the MODEM Status Register
indicates whether the i5C5 input has changed state

4-11

6.0 Pin Descriptions (Continued)
Interrupt (INTR), Pin 30: This goes high whenever anyone
of the following interrupt types has an active high condition
and is enabled via the IER: Receiver Line Status; Received
Data Available; Transmitter Holding Register Empty; and
MODEM Status. The INTR signal is reset low upon the appropriate interrupt service or a Master Reset operation.

6.3 INPUT/OUTPUT SIGNALS
Data (07-00) Bus, Pins 1-8: This bus is comprised of eight
TRI-STATE input/output lines. The bus provides bidirectional communications between the UART and the CPU. Data,
control words, and status information are transferred via the
07-00 Data Bus.

Serial Output (SOUn, Pin 11: This is the composite serial
data output to the communications link (peripheral, MODEM
or data set). The SOUT signal is set to the Marking (logic 1)
state upon a Master Reset operation or when the transmitter is idle.

External Clock Input/Output (XIN, XOUT) Pins 16 and 17:
These two pins connect the main timing reference (crystal
or signal clock) to the UART. When a crystal oscillator or a
clock signal is provided, it drives the UART via XIN (see
typical oscillator network illustration).

7.0 Connection Diagrams
Dual-In-Line Package

PCC Package

DD~r-~CC

D,D2D3D,D,D&DlRC'KS'NSDUTCSOCSI-

m-

---

..

"

BJmillilii'- 15
X1N- 16
XDUT- 11

R-

"~7NcV\C1W

"r-~

2
3
,
5
,
1
8
,
ID
"
12
13

IB

WR- I,
vss- 2D

31
37
3'
35
3'
33
32
31
3D
29
28
2l
26
25
2.
23
22
21

.. .

t - DCD

/65432

-~

-CTS
-MR

-1IiITi

-~

-RTS
r-1IlIT2
I-'NTR
t-NC
t-AD
t-AI
-A2
-ADS
-CSDUT
-DOIS
-RD

DO

7

D7

,

RCLK
SIN
Ne
SOUT

10

CSO

14

"

12
13

1 4443424140

" .R

.,3811iili
iifR
36

34 NC

cal 15
CS2
iMiDDIif

RfI

3511l1i'1
HS1845D
INS8250A

18
17

33

INTR

"
31
.,

NC
AD
AI

IS

AI

1819202122232425262728

xw

::~Ij l:'~ ~D\~~m
TL/C/9329-18

rill!

Top View
Order Number INS8250V-B
See NS Package Number V44A

TL/C/9329-11

Top View
Order Number INS8250N, INS8250N-B or
INS8250N/A +
See NS Package Number N40A
TABLE I. UART Reset Functions
Register/Signal

Reset Control

Reset State

Master Reset

0000 0000 (Note 1)

Interrupt Identification Register

Master Reset

00000001

Line Control Register

Master Reset

00000000

MODEM Control Register

Master Reset

00000000

Line Status Register

Master Reset

01100000

MODEM Status Register

Master Reset

XXXX 0000 (Note 2)

Master Reset

High

Interrupt Enable Register

SOUT
INTR (RCVR Errs)

Read LSR/MR

Low

INTR (RCVR Data Ready)

Read RBR/MR

Low

Read IIR/Write THR/MR

Low

INTR(THRE)
INTR (Modem Status Changes)

Read MSR/MR

Low

Master Reset

High

RTS

Master Reset

High

DTR

Master Reset

High

OUT 1

Master Reset

High

OUT2

Note 1: Underlined bits are permanently low.
Note 2: Bits 7-4 are driven by the input Signals.

4-12

8.0 Registers
Bits 0 and 1: These two bits specify the number of bits in
each transmitted or received serial character. The encoding
of bits 0 and 1 is as follows:

The system programmer may access any of the UART registers summarized in Table II via the CPU. These registers
control UART operations including transmission and reception of data. Each register bit in Table II has its name and
reset state shown.

Bit 1

BltO

Character Length

0
0
1
1

0
1
0
1

5 Bits
6 Bits
? Bits
S Bits

8.1 LINE CONTROL REGISTER
The system programmer specifies the format of the asynchronous data communications exchange and sets the Divisor Latch Access bit via the Line Control Register (LCR).
The programmer can also read the contents of the Line
Control Register. The read capability simplifies system programming and eliminates the need for separate storage in
system memory of the line characteristics. Table II shows
the contents of the LCR. Details on each bit follow:

Bit 2: This bit specifies the number of Stop bits transmitted
and recevied in each serial character. If bit 2 is a logic 0,
one Stop bit is generated or checked in the serial data. If bit
2 is a logic 1 when a 5-bit word length is selected via bits 0

TABLE II. Summary of Registers
Register Address

o DLAB=O

ODLAB=O

Receiver
Buffer
Register
(Read

Transmitter
Holding
Register
(Write

Only)

Only)

RBR

THR

IER

a

Data BitO
(Note 1)

Data BitO

Received
Data
Available

1

Data Bit 1

DataBit1

Transmitter
Holding
Register
Empty

Interrupt

Receiver
Line Status

Interrupt

Bit
No.

2

Data Bit2

Data Bit2

1 DLAB=O

2

3

4

5

6

o DLAB=1

1 DLAB=1

Interrupt
Enable
Register

Interrupt
Ident.
Register
(Read

Line
Control
Register

MODEM
Control
Register

Line
Status
Register

MODEM
Status
Register

Divisor
Latch
(LS)

Division
Latch
(MS)

IIR

LCR

MCR

LSR

MSR

DLL

DLM

"0" if
Interrupt
Pending

Word
Length
Select
BitO
(WLSO)

Data
Terminal
Ready
(DTR)

Data
Ready
(DR)

Delta
Clear
to Send
(DCTS)

Bit

a

BitS

Word
Length
Select
Bit1
(WLS1)

Request
to Send
(RTS)

Overrun
Error
(OE)

Delta
Data
Set
Ready
(DDSR)

Bit 1

Bit9

Number of
Stop Bits
(STB)

Out 1

Parity
Error
(PE)

Trailing
Edge Ring
Indicator
(TERI)

Bit2

Bit 10

Only)

10
Bit (0)

10
Bit(1)

a

3

DataBit3

Data Bit3

MODEM
Status

a

Parity
Enable
(PEN)

Out2

Framing
Error
(FE)

Delta
Data
Carrier
Detect
(DDCD)

Bit3

Bit 11

4

Data Bit4

Data Bit4

a

a

Even
Parity
Select
(EPS)

Loop

Break
Interrupt
(BI)

Clear
to
Send
(CTS)

Bit4

Bit 12

5

Data Bit 5

Data Bit5

a

a

Stick
Parity

a

Transmitter
Holding
Register
(THRE)

Data
Set
Ready
(DSR)

Bit5

Bit13

6

DataBit6

Data Bit6

a

a

Set
Break

a

Transmitter
Shift
Register
Empty
(TSRE)

Ring
Indicator
(RI)

Bit6

Bit14

?

Data Bit?

Data Bit?

a

a

Divisor
Latch
Access
Bit
(DLAB)

a

a

Data
Carrier
Detect
(DCD)

Bit?

Bit 15

Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.

4-13

8.0 Registers (Continued)

8.2 Typical Clock Circuits

and 1, one and a half Stop bits are generated. If bit 2 is a
logic 1 when either a 6-, 7-, or 8-bit word length is selected,
two Stop bits are generated. The Receiver checks the first
Stop bit only, regardless of the number of Stop bits selected.
Bit 3: This bit is the Parity Enable bit. When bit 3 is a logic 1,
a Parity bit is generated (transmit data) or checked (receive
data) between the last data word bit and Stop bit of the
serial data. (The Parity bit is used to produce an even or odd
number of 1s when the data word bits and the Parity bit are
summed.)
Bit 4: This bit is the Even Parity Select bit. When bit 3 is a
logic 1 and bit 4 is a logic 0, an odd number of logic 1s is
transmitted or checked in the data word bits and Parity bit.
When bit 3 is a logic 1 and bit 4 is a logic 1, an even number
of logic 1s is transmitted or checked.
Bit 5: This bit is the Stick Parity bit. When bits 3, 4 and 5 are
logic 1 the Parity bit is transmitted and checked as a logic O.
If bits 3 and 5 are 1 and bit 4 is a logic 0 then the Parity bit is
transmitted and checked as a logic 1. If bit 5 is a logic 0
Stick Parity is disabled.
Bit 6: This bit is the Break Control bit. It causes a break
condition to be transmitted by the UART. When it is set to a
logic 1, the serial output (SOUT) is forced to the Spacing
(logic 0) state. The break is disabled by clearing bit 6 to a
logic O. The Break Control bit acts only on SOUT and has no
effect on the transmitter logic.

INS8250
INS8250·8

VCC

OSC, CLOCK TO

OPT~~m--C>_---~

TL/C/8401-6

• Applicable Only When ADS is Tied Low,

4-24

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....

4.0 Timing Waveforms (Continued)

....

0)

U1

Receiver Timing
RCCK

o
......

rL
rL
---------1nL---.....JnL.....'I--I_ _

Z
rJ)
01)

1---------ICLKs--------·II_1SCO

SAMPLEClk

N

U1

~
......
Z

....
o....

rJ)

(RECli~~~

0)

O,~.T-A-"-TS-('---8)---

\'"_S_TA_AT_C'___

U1

I

SAMPLE

o
......

I

Z

CLK-L_ _~~_~_ _~I~I~---L---~---L-~~---~~I~

--l l--.gNT
INTERRUPT

(DATA RCVRERRI
READY OR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _J

iiJj.RD

DA~:~F~:~

rJ)
01)

iL

fIr

N

oU1

~

~

~'AI.T

________________________

_____

~

DRRDlSRl
(NOTE 2)

TL/C/8401-7

Transmitter Timing

OUT~~~~AT~
INTERRUPT
(THRE)

Wii.WA
(WATHAI

\START/

~S~TA_A..i'_________

OAlAIS-I)

_____~I·,AS~,.--------,\
--'"I

r~~ ~
J\r--.

(NOTE 1)

~~-

SI

--1 FY
Ir ~
1STI

I

1

I

Ir\

I,

\\._______________~_;_-

I

~"A

1iD,IID _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _,
(AOHAI

I
-

~' - - -

!NOT£2)

TL/C/8401-8

MODEM Controls Timing
Wfj,WR
(WR MCR)
(NOTE 1)

ouW~

fl'-'I'\
.JI

RD. 110

- ..00-'

\\._______________

rn.ll!if.ilCii _ _ _ _

INTERAUPT

t!

/

-7--"1
I,
~_~r-\I -r
1-'SlM-1'A1Mr- 1-'SlM- -1'A1Mr- r'SlM---i
1'-

r-'V.

I~:o\'::: ---------1

\

I

\

f\J!
\\.__'-,_______

/,...--TL/C/8401-9

Note 1: See Write Cycle Timing
Note 2: See Read Cycle Timing

4-25

~
ID

oN

5.0 Block Diagram

CI)

INTERNAL
DATA BUS

(f)

Z

:::::
o

01-00

...,.

ID

oCD

....

(f)

RCLK

Z
.....

~

ID
N

""
"

Z

cso

~

:::::
o
...,.

ID

SELECT

....

CONTROL
LOGIC

&

CD

(J)

Z
DOtS
CSOUT

,IN
XOUT

iffS

rn

Ill1i

POWER{~"'5V

SUPPLY

DSR
DCiJ

~GND

R1
OUTI
QUn
(10)

WTR

TL/C/B401-10

Note: Applicable pinout numbers are included within parenthesis.

6.0 Pin Descriptions
The following describes the function of all UART pins. Some
of these descriptions reference internal circuits.

Write (WR, WR), Pins 19 and 18: When WR is high or WR
is low while the chip is selected, the CPU can write control
words or data into the selected UART register.

In the following descriptions, a low represents a logic 0 (OV
nominal) and a high represents a logic 1 (+ 2.4V nominal).

Note: Only an active WR or WR input is required to transfer data to the
UART during a write operation. Therefore. tie either the WR input permanently low or the WR input permanently high, when it is not used.

6.1 INPUT SIGNALS

Address Strobe (ADS), Pin 25: The positive edge of an
active Address Strobe (ADS) signal latches the Register Select (AO, AI, A2) and Chip Select (CSO, CS 1, CS2) signals.

Chip Select (CSO, CS1, CS2), Pins 12-14: When CSO and
CSI are high and CS2 is low, the chip is selected. This
enables communication between the UART and the CPU.
The positive edge of an active Address Strobe signal latches the decoded chip select signals, completing chip selection. If ADS is always low, valid chip selects should stabilize
according to the tcsw parameter.
Read (RD, RD), Pins 22 and 21: When RD is high or RD is
low while the chip is selected, the CPU can read status
information or data from the selected UART register.

Note: An active ADS input is required when the Register Select (AO. A 1, A2)
signals are not stable for the duration of a read or write operation. If not
required. tie the ADS input permanently low.

Register Select (AD, A1, A2), Pins 26-28: Address signals
connected to these 3 inputs select a UART register for the
CPU to read from or write to during data transfer. A table of
registers and their addresses is shown below. Note that the
state of the Divisor Latch Access Bit (DLAB), which is the
most significant bit of the Line Control Register, affects the
selection of certain UART registers. The DLAB must be set
high by the system software to access the Baud Generator
Divisor Latches.

Note: Only an active AD or AD input is required to transfer data from the
UART during a read operation. Therefore, tie either the AD input permanent·
Iy low or the RD input permanently high, when it is not used.

4-26

z

....enw

6.0 Pin Descriptions (Continued)
since the previous reading of the MODEM Status Register.
DCD has no effect on the receiver.

Register Addresses
DLAB

A2

A1

Ao

0

0

0

0

0

0
0

0

1

1

0

X
X
X
X
X
1

0

1

1

1
1
1
1

0
0

0

1
1

0

0

0

0

1

0

0

1

X

1
1

Register

Note: Whenever the DCD bit of the MODEM Status Register changes state.
an interrupt is generated if the MODEM Status Interrupt is enabled.

Receiver Buffer (read),
Transmitter Holding
Register (write)
Interrupt Enable
Interrupt Identification
(read only)
Line Control
MODEM Control
Line Status
MODEM Status
Scratch
Divisor Latch
(least significant byte)
Divisor Latch
(most significant byte)

Ring Indicator (Ai), Pin 39: When low, this indicates that a
telephone ringing signal has been received by the MODEM
or data set. The Ai signal is a MODEM status input whose
condition can be tested by the CPU reading bit 6 (RI) of the
MODEM Status Register. Bit 6 is the complement of the Ai
signal. Bit 2 (TERI) of the MODEM Status Register indicates
whether the Ai input signal has changed from a low to a
high state since the previous reading of the MODEM Status
Register.
Note: Whenever the RI bit of the MODEM Status Register changes from a
high to a low state, an interrupt is generated if the MODEM Status
interrupt is enabled.

Vee, Pin 40:
VSS,

+ 5V supply.

Pin 20: Ground (OV) reference.

6.2 OUTPUT SIGNALS
Data Terminal Ready (DTR), Pin 33: When low, this informs the MODEM or data set that the UART is ready to
establish a communications link. The DTR output signal can
be set to an active low by programming bit 0 (DTR) of the
MODEM Control Register to a high level. A Master Reset
operation sets this signal to its inactive (high) state. Loop
mode operation holds this signal in its inactive state.
Request to Send (RTS), Pin 32: When low, this informs the
MODEM or data set that the UART is ready to exchange
data. The RTS output signal can be set to an active low by
programming bit 1 (RTS) of the MODEM Control Register. A
Master Reset operation sets this signal to its inactive (high)
state. Loop mode operation holds this signal in its inactive
state.
Output 1 (OUT 1), Pin 34: This user-designated output can
be set to an active low by programming bit 2 (OUT 1) of the
MODEM Control Register to a high level. A Master Reset
operation sets this signal to its inactive (high) state. Loop
mode operation holds this signal in its inactive state. In the
XMOS parts this will achieve TTL levels.
Output 2 (OUT 2), Pin 31: This user-designated output can
be set to an active low, by programming bit 3 (OUT 2) of the
MODEM Control Register to a high level. A Master Reset
operation sets this signal to its inactive (high) state. Loop
mode operation holds this signal in its inactive state. In the
XMOS parts this will achieve TTL levels.

Master Reset (MR), Pin 35: When this input is high, it clears
all the registers (except the Receiver Buffer, Transmitter
Holding, and Divisor Latches), and the control logic of the
UART. The states of various output signals (SOUT, INTR,
OUT 1, OUT 2, RTS, DTR) are affected by an active MR
input. (Refer to Table I.) This input is buffered with a TTLcompatible Schmitt Trigger with O.5V typical hysteresis.
Receiver Clock (RCLK), Pin 9: This input is the 16 x baud
rate clock for the receiver section of the chip.
Serial Input (SIN), Pin 10: Serial data input from the communications link (peripheral device, MODEM, or data set).
Clear to Send (CTS), Pin 36: When low, this indicates that
the MODEM or data set is ready to exchange data. The CTS
signal is a MODEM status input whose conditions can be
tested by the CPU reading bit 4 (CTS) of the MODEM Status
Register. Bit 4 is the complement of the CTS signal. Bit 0
(DCTS) of the MODEM Status Register indicates whether
the CTS input has changed state since the previous reading
of the MODEM Status Register. CTS has no effect on the
Transmitter.
Note: Whenever the CTS bit of the MODEM Status Register changes state,
an interrupt is generated if the MODEM Status Interrupt is enabled.

Data Set Ready (DSR), Pin 37: When low, this indicates
that the MODEM or data set is ready to establish the communications link with the UART. The DSR signal is a
MODEM status input whose condition can be tested by the
CPU reading bit 5 (DSR) of the MODEM Status Register. Bit
5 is the complement of the DSR signal. Bit 1 (DDSR) of the
MODEM Status Register indicates whether the DSR input
has changed state since the previous reading of the
MODEM Status Register.

Chip Select Out (CSOUT), Pin 24: When high, it indicates
that the chip has been selected by active, CSO, CS1, and
CS2 inputs. No data transfer can be initiated until the
CSOUT signal is a logiC 1. CSOUT goes low when the
UART is deselected.
Driver Disable (DO IS), Pin 23: This goes low whenever the
CPU is reading data from the UART. It can disable or control
the direction of a data bus transceiver between the CPU
and the UART (see Typical Interface for a High Capacity
Data Bus).
Baud Out (i'iB"Ai"iU"'D"'Oi"iU""T), Pin 15: This is the 16 x clock signal from the transmitter section of the UART. The clock rate
is equal to the main reference oscillator frequency divided
by the specified divisor in the Baud Generator Divisor Latches. The BAUDOUT may also be used for the receiver section by tying this output to the RCLK input of the chip.

Note: Whenever the DSR bit of the MODEM Slatus Register changes state,
an interrupt is generated if the MODEM Status Interrupt is enabled.

Data Carrier Detect (DC D), Pin 38: When low, indicates
that the data carrier has been detected by the MODEM or
data set. The DCD signal is a MODEM status input whose
condition can be tested by the CPU reading bit 7 (DCD) of
the MODEM Status Register. Bit 7 is the complement of the
DCD signal. Bit 3 (DDCD) of the MODEM Status Register
indicates whether the DCD input has changed state

4-27

~

U1

o
......

Z

~
II.)
U1

o

~

Z
W

....en

o

~

U1

o
......

Z
w

00
II.)

o

~

~
II)

oN

~

Z

:::::::

c
..,.

II)

~
.....
en

z

~

II)

N

co

en

z

6.0 Pin Descriptions (Continued)
Interrupt (INTR), Pin 30: This goes high whenever anyone
of the following interrupt types has an active high condition
and is enabled via the IER: Receiver Line Status; Received
Data Available; Transmitter Holding Register Empty; and
MODEM Status. The INTR signal is reset low upon the appropriate interrupt service or a Master Reset operation.

6.3 INPUT/OUTPUT SIGNALS
Data (07- Do) Bus, Pins 1-8: This bus is comprised of eight
TRI-STATE input/output lines. The bus provides bidirectional communications between the UART and the CPU. Data,
control words, and status information are transferred via the
DrDo Data Bus.
External Clock Input/Output (XIN, XOUT) Pins 16 and
17: These two pins connect the main timing reference (crystal or signal clock) to the UART. When a crystal oscillator or
a clock signal is provided, it drives the UART via XIN (see
typical oscillator network illustration).

Serial Output (SOUT), Pin 11: This is the composite serial
data output to the communications link (peripheral, MODEM
or data set). The SOUT signal is set to the Marking (logic 1)
state upon a Master Reset operation or when the transmitter is idle.

7.0 Connection Diagrams
Dual-In-Line Package

:::::::

cII)

..,.

PCC Package

OO-~I-vcc
0,0203040,0,07RClKSlN50UTC50C51-

CD

.....
en
z

CSl8AUOOUT-

2
3
4

,
6

7
8

9
10
11

NS16450
INSB250A

12
13
14

"

XIN- 16
XOUT- 11
WA- 18
WR- 19
V55- 20

D4

39 I-Rl
38 l-ifCD
371-OSA
J61-C'fS
3' I-MR
34 l-ilUTI
33 I-IlfR
"I-RfS
31 I-OUTI
3D I-'NTR
29 I- NC
28 I- Ao
21 I-Al
26 I-A2
"I-AllS
24 I-C50UT
23 1-0015
22 I-RO
21 I-liil

~\\
1"

j'NC'\C

5432

liP'

14443424140

1

"38

01

9

RClK

10
11

37
36

" •
D6

SIN
NC

SOUT

cso

Cst

ffi
iiAiiDODT

35

NS1645D
lNS8250A

12
13
14

"
16

11

MR

rnm
jj'ffi

iii>

i'iUf2

34

NC

33

INTI!

32
31
3D
29

Ne
AD
Al
A2

18 19 20 21 2223 24 25 26 27 28

X1N~/jj

t'l ~O\~~ADS
TL/C/8401-18

Top View
Order Number NS16450V, NS-16450V,
INS8250AV, NS16C450Vor INS82C50AV
See NS Package Number V44A

TL/G/B401-11

Top View
Order Number NS16450N, NS-16450N,
INS8250AN, NS16C450N or INS82C50AN
See NS Package Number N40A

TABLE I. UART Reset Functions
Reset Control

Reset State

Interrupt Enable Register

Register/Signal

Master Reset

0000 0000 (Note 1)

Interrupt Identification Register

Master Reset

00000001

Line Control Register

Master Reset

00000000

MODEM Control Register

Master Reset

00000000

Line Status Register

Master Reset

01100000

MODEM Status Register

Master Reset

XXXX 0000 (Note 2)

SOUT

Master Reset

High

INTR (RCVR Errs)

Read LSR/MR

Low

INTR (RCVR Data Ready)

Read RBR/MR

Low

Read IIR/Write THR/MR

Low

INTR (THRE)
INTR (Modem Status Changes)

Read MSR/MR

Low

OUT2

Master Reset

High

RTS

Master Reset

High

DTR

Master Reset

High

OUT1

Master Reset

High

Note 1: Boldface bits are permanently low.
Note 2: Bits 7 -4 are driven by the input signals.

4-28

z

8.0 Registers
The system programmer may access any of the UART registers summarized in Table II via the CPU. These registers
control UART operations including transmission and reception of data. Each register bit in Table II has its name and
reset state shown.

Bits 0 and 1: These two bits specify the number of bits in
each transmitted or received serial character. The encoding
of bits 0 and 1 is as follows:

8.1 LINE CONTROL REGISTER
The system programmer specifies the format of the asynchronous data communications exchange and sets the Divisor latch Access bit via the Line Control Register (lCR).
The programmer can also read the contents of the Line
Control Register. The read capability simplifies system programming and eliminates the need for separate storage in
system memory of the line characteristics. Table II shows
the contents of the LCR. Details on each bit follow:

2

Character length

Q)

0
0
1
1

0
1
0
1

5 Bits
6 Bits
7 Bits
S Bits

~
......
z

N
U1

en
......
en

Bit 2: This bit specifies the number of Stop bits transmitted
and received in each serial character. If bit 2 is a logic 0,
one Stop bit is generated or checked in the transmitted
data. If bit 2 is a logic 1 when a 5-bit word length is selected
via bits 0 and 1, one and a half Stop bits are generated. If

4

3

Interrupt
Bit Receiver Transmitter
Buffer
Holding
Interrupt
Ident.
line
MODEM
No.
Register
Register
Enable
Register Control Control
(Read
(Write
Register
(Read
Register Register
Only)
Only)
Only)

5
line
Status
Register

6

7

U1

o
......

Z

en

Q)

MODEM Scratch
Status
RegRegister
ister

o DlAB= 1 1 DlAB=1 ~
Divisor
latch
(lS)

Divisor
latch
(MS)

RBR

THR

IER

IIR

lCR

MCR

lSR

MSR

SCR

Dll

DlM

Data Bit 0

Received
Data
Available

"0" if
Interrupt
Pending

Word
length
Select
BitO
(WLSO)

Data
Terminal
Ready
(DTR)

Data
Ready
(DR)

Delta
Clear
to Send
(DCTS)

BitO

Bit 0

BitS

1

Data Bit 1

Data Bit 1

Transmitter Interrupt
Holding
10
Register
Bit (0)
Empty

Word
Length
Select
Bit 1
(WLS1)

Request
to Send
(RTS)

Overrun
Error
(OE)

Delta
Data
Set
Ready
(DDSR)

Bit 1

Bit 1

Bit 9

2

Data Bit 2

Data Bit 2

Receiver Interrupt Number of
Line Status
10
Stop Bits
(STB)
Bit (1)

Out 1

Parity
Error
(PE)

Trailing
Edge Ring
Indicator
(TERI)

Bit2

Bit2

Bit 10

3

Data Bit 3

Data Bit 3

MODEM
Status

0

Parity
Enable
(PEN)

Out 2

Framing
Error
(FE)

Delta
Data
Carrier
Detect
(DDCD)

Bit3

Bit 3

Bit 11

4

Data Bit 4

Data Bit4

0

0

Even
Parity
Select
(EPS)

Loop

Break
Interrupt
(BI)

Clear
to
Send
(CTS)

Bit4

Bit4

Bit 12

5

Data Bit 5

Data Bit 5

0

0

Stick
Parity

0

Transmitter
Holding
Register
(THRE)

Data
Set
Ready
(DSR)

Bit 5

Bit 5

Bit 13

6

Data Bit 6

Data Bit 6

0

0

Set
Break

0

Transmitter
Ring
Empty
Indicator
(TEMT)
(RI)

Bit6

Bit6

Bit 14

7

Data Bit 7

Data Bit 7

0

0

Divisor
Latch
Access
Bit
(DLAB)

0

Bit7

Bit 7

Bit 15

4-29

.jlIo

oU1

Data Bit 0
(Note 1)

0

o

N

0

Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.

Z

en

Bit 0

Register Address
1 DlAB=O

U1

o
......

Bit 1

TABLE II. Summary of Registers

o DlAB=O o DlAB=O

en
......
en
.jlIo

Data
Carrier
Detect
(DCD)

c(

~

~
co

en
z

::::
o
Lt)
~

U

....
<0

en
z
.......
~
Lt)

'"CO
en
z
::::
o
Lt)
~

....en
<0

z

8.2 TYPICAL CLOCK CIRCUITS

8.0 Registers (Continued)
bit 2 is a logic 1 when either a 6-, 7-, or 8-bit word length is
selected, two Stop bits are generated. The Receiver checks
the first Stop-bit only, regardless of the number of Stop bits
selected.
Bit 3: This bit is the Parity Enable bit. When bit 3 is a logic 1,
a Parity bit is generated (transmit data) or checked (receive
data) between the last data word bit and Stop bit of the
serial data. (The Parity bit is used to produce an even or odd
number of 1s when the data word bits and the Parity bit are
summed.)
Bit 4: This bit is the Even Parity Select bit. When bit 3 is a
logic 1 and bit 4 is a logic 0, an odd number of logic 1s is
transmitted or checked in the data word bits and Parity bit.
When bit 3 is a logic 1 and bit 4 is a logic 1, an even number
of logic 1s is transmitted or checked.
Bit 5: This bit is the Stick Parity bit. When bits 3, 4 and 5 are
logic 1 the Parity bit is transmitted and checked as a logic o.
If bits 3 and 5 are 1 and bit 4 is a logic 0 then the Parity bit is
transmitted and checked as a logic 1. If bit 5 is a logic 0
Stick Parity is disabled.
Bit 6: This bit is the Break Control bit. It causes a break
condition to be transmitted by the UART. When it is set to a
logic 1, the serial output (SOUT) is forced to the Spacing
(logic 0) state. The break is disabled by clearing bit 6 to a
logic O. The Break Control bit acts only on SOUT and has no
effect on the transmitter logic.

1NS82I1OA
NS16450

VCC

OSC. CLOCK TO
BAUO GEN LOGIC

OPTIONAL

o~~~S~-c><·t-:=+-----...-·

TLlC/8401-12

VCC

1NS8250A
NS16450

XIN

Rp

CRYSTAL
OSC. CLOCK TO

r - _..._ ......J\tYt.+____.B.AUO GEN LOGIC

Note: This feature enables the CPU to alert a terminal in a computer communications system. If the following sequence is used. no erroneous
or extraneous characters will be transmitted because of the break.

1. Load an all Os, pad character, in response to THRE.

TL/C/8401-13

2. Set break after the next THRE.
3. Wait for the transmitter to be idle, (TEMT= 1), and clear break when
normal transmission has to be restored.
During the break, the Transmitter can be used as a character timer to accurately establish the break duration.

Typical Oscillator Networks

Bit 7: This bit is the Divisor Latch Access Bit (DLAB). It must
be set high (logic 1) to access the Divisor Latches of the
Baud Generator during a Read or Write operation. It must
be set low (logic 0) to access the Receiver Buffer, the
Transmitter Holding Register, or the Interrupt Enable Register.
TABLE III. Baud Rates Using 1.8432 MHz Crystal
Desired
Baud Rate

Decimal
Divisor Used
to Generate
16xCIock

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000

2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2

TABLE IV. Baud Rates Using 3.072 MHz Crystal

Percent Error
Difference Between
Desired and Actual

-

0.026
0.058

-

-

-

-

0.69

-

-

-

-

-

-

2.86
4-30

Desired
Baud Rate

Decimal
Divisor Used
to Generate
16 x Clock

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400

3840
2560
1745
1428
1280
640
320
160
107
96
80
53
40
27
20
10
5

Percent Error
Difference Between
Desired and Actual

-

-

0.026
0.034

-

-

0.312

0.628

1.23

-

-

8.0 Registers

(Continued)
select bit. The PE bit is set to a logic 1 upon detection of a
parity error and is reset to a logic 0 whenever the CPU reads
the contents of the Line Status Register.

8.3 PROGRAMMABLE BAUD GENERATOR
The UART contains a programmable Baud Generator that is
capable of taking any clock input from DC to 3.1 MHz and
dividing it by any divisor from 1 to 216 -1. The output frequency of the Baud Generator is 16 x the Baud [divisor #
= (frequency input) .,. (baud rate x 16)1. Two 8-bit latches
store the divisor in a 16-bit binary format. These Divisor
Latches must be loaded during initialization in order to ensure proper operation of the Baud Generator. Upon loading
either of the Divisor Latches, a 16-bit Baud counter is immediately loaded.

Bit 3: This bit is the Framing Error (FE) indicator. Bit 3 indicates that the received character did not have a valid Stop
bit. Bit 3 is set to a logic 1 whenever the Stop bit following
the last data bit or parity bit is a logic 0 (Spacing level). The
FE indicator is reset whenever the CPU reads the contents
of the Line Status Register. The UART will try to resynchronize after a framing error. To do this it assumes that the
framing error was due to the next start bit, so it samples this
"start" bit twice and then takes in the "data".

Tables III and IV provide decimal divisors to use with crystal
frequencies of 1.8432 MHz and 3.072 MHz respectively for
common baud rates. For baud rates of 38400 and below,
the error obtained is minimal. The accuracy of the desired
baud rate is dependent on the crystal frequency chosen.
Using a division of 0 is not recommended.

Bit 4: This bit is the Break Interrupt (BI) indicator. Bit 4 is set
to a logic 1 whenever the received data input is held in the
Spacing (logiC 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits +
Parity + Stop bits). The BI indicator is reset whenever the
CPU reads the contents of the Line Status Register. Restarting after a break is received, requires the SIN pin to be
logical 1 for at least Yz bit time.

Note: The maximum operating frequency of the Baud Generator is 3.1 MHz.
However, when using divisors of 3 and below, the maximum frequen~
cy is equal to the divisor in MHz. For example, if the divisor is 1, then
the maximum frequency is 1 MHz. In no case should the data rate be

Note: Bits 1 through 4 are the error conditions that produce a Receiver Line
Status interrupt whenever any of the corresponding conditions are
detected and the interrupt is enabled.

greater than 56k Baud.

8.4 LINE STATUS REGISTER
This 8-bit register provides status information to the CPU
concerning the data transfer. Table II shows the contents of
the Line Status Register. Details on each bit follow:

Bit 5: This bit is the Transmitter Holding Register Empty
(THRE) indicator. Bit 5 indicates that the UART is ready to
accept a new character for transmission. In addition, this bit
causes the UART to issue an interrupt to the CPU when the
Transmit Holding Register Empty Interrupt enable is set
high. The THRE bit is set to a logic 1 when a character is
transferred from the Transmitter Holding Register into the
Transmitter Shift Register. The bit is reset to logic 0 whenever the CPU loads the Transmitter Holding Register.

Bit 0: This bit is the receiver Data Ready (DR) indicator. Bit

o is set to a logiC 1 whenever a complete incoming charac-

ter has been received and transferred into the Receiver
Buffer Register. Bit 0 is reset to a logic 0 by reading the data
in the Receiver Buffer Register.
Bit 1: This bit is the Overrun Error (OE) indicator. Bit 1 indicates that data in the Receiver Buffer Register was not read
by the CPU before the next character was transferred into
the Receiver Buffer Register, thereby destroying the previous character. The OE indicator is set to a logic 1 upon
detection of an overrun condition and reset whenever the
CPU reads the contents of the Line Status Register.

Bit 6: This bit is the Transmitter Empty (TEMn indicator. Bit
6 is set to a logic 1 whenever the Transmitter Holding Register (THR) and the Transmitter Shift Register (TSR) are both
empty. It is reset to a logic 0 whenever either the THR or
TSR contains a data character.

Bit 2: This bit is the Parity Error (PE) indicator. Bit 2 indicates that the received data character does not have the
correct even or odd parity, as selected by the even-parity-

to this register is not recommended as this operation is only used for

Bit 7: This bit is permanently set to logic

o.

Note: The Line Status Register is intended for read operations only. Writing
factory testing.

TABLE V.lnterrupt Control Functions
Interrupt Identification
Register
Bit 2

Bit 1

Bit 0

0

0

1

1

1

0

1

0

0

0

Interrupt Set and Reset Functions
Priority
Level

-

Interrupt Type

Interrupt Source

Interrupt Reset Control

None

None

Highest

Receiver Line Status

Overrun Error or
Parity Error or Framing
Error or Break Interrupt

Reading the Line Status
Register

0

Second

Received Data Available

Receiver Data Available

Reading the Receiver
Buffer Register

1

0

Third

Transmitter Holding
Register Empty

Reading the IIR Register
(if source of interrupt) or
Writing into the Transmitter Holding Register

0

0

Fourth

Clear to Send or
Data Set Ready or
Ring Indicator or Data
Carrier Detect

Reading the MODEM
Status Register

, Transmitter Holding
Register Empty

MODEM Status

4-31

8.0 Registers (Continued)
in Table II and are described below. Table II shows the contents of the MCR. Details on each bit follow.

8.5 INTERRUPT IDENTIFICATION REGISTER
In order to provide minimum software overhead during data
character transfers, the UART prioritizes interrupts into four
levels and records these in the Interrupt Identification Register. The four levels of interrupt conditions in order of priority are Receiver Line Status; Received Data Ready; Transmitter Holding Register Empty; and MODEM Status.

Bit 0: This bit controls the Data Terminal Ready (DTR) output. When bit 0 is set to a logic 1, the DTR output is forced
to a logic O. When bit 0 is reset to a logic 0, the DTR output
is forced to a logic 1.
Note: The i5fR output of the UART may be applied to an EIA inverting line
driver (such as the DS1488) to obtain the proper polarity input at the
succeeding MODEM or data set.

When the CPU accesses the IIR, the UART freezes all interrupts and indicates the highest priority pending interrupt to
the CPU. While this CPU access is occurring, the UART
records new interrupts, but does not change its current indication until the access is complete. Table II shows the contents of the IIR. Details on each bit follow:

Bit 1: This bit controls the Request to Send (RTS) output.
Bit 1 affects the RTS output in a manner identical to that
described above for bit o.
Bit 2: This bit controls the Output 1 (OUT 1) Signal, which is
an auxiliary user-designated output. Bit 2 affects the OUT 1
output in a manner identical to that described above for bit o.

Bit 0: This bit can be used in an interrupt environment to
indicate whether an interrupt condition is pending. When bit
is a logic 0, an interrupt is pending and the IIR contents
may be used as a pointer to the appropriate interrupt service
routine. When bit 0 is a logic I, no interrupt is pending.

o

Bit 3: This bit controls the Output 2 (OUT 2) Signal, which is
an auxiliary user-designated output. Bit 3 affects the OUT 2
output in a manner identical to that described above for bit o.

Bits 1 and 2: These two bits of the IIR are used to identify
the highest priority interrupt pending as indicated in Table V.

Bit 4: This bit provides a localloopback feature for diagnostic testing of the UART. When bit 4 is set to logic I, the
following occur: the transmitter Serial Output (SOUT) is set
to the Marking (logic 1) state; the receiver Serial Input (SIN)
is disconnected; the output of the Transmitter Shift Register
is "looped back" into the Receiver Shift Register input; the
four MODEM Control inputs (CTS, DSR, Ai, and DCD) are
disconnected; and the four MODEM Control outputs (DTR,
RTS, OUT I, and OUT 2) are internally connected to the
four MODEM Control inputs. The MODEM Control output
pins are forced to their inactive state (high). In the diagnostic mode, data that is transmitted is immediately received.
This feature allows the processor to verify the transmit-and
received-data paths of the UART.

Bits 3 through 7: These five bits of the IIR are always logic O.
8.6 INTERRUPT ENABLE REGISTER
This register enables the four types of UART interrupts.
Each interrupt can individually activate the interrupt (lNTR)
output signal. It is possible to totally disable the interrupt
system by resetting bits 0 through 3 of the Interrupt Enable
Register (IER). Similarly, setting bits of this register to a logic I, enables the selected interrupt(s). Disabling an interrupt
prevents it from being indicated as active in the IIR and from
activating the INTR output signal. All other system functions
operate in their normal manner, including the setting of the
Line Status and MODEM Status Registers. Table II shows
the contents of the IER. Details on each bit follow.

In the diagnostic mode, the receiver and transmitter interrupts are fully operational. The MODEM Control Interrupts
are also operational, but the interrupts' sources are now the
lower four bits of the MODEM Control Register instead of
the four MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable Register.

Bit 0: This bit enables the Received Data Available Interrupt
when set to logic 1.
Bit 1: This bit enables the Transmitter Holding Register
Empty Interrupt when set to logic 1.

Bits 5 through 7: These bits are permanently set to logic O.

Bit 2: This bit enables the Receiver Line Status Interrupt
when set to logic 1.

8.8 MODEM STATUS REGISTER
This register provides the current state of the control lines
from the MODEM (or peripheral device) to the CPU. In addition to this current-state information, four bits of the
MODEM Status Register provide change information. These
bits are set to a logic 1 whenever a control input from the
MODEM changes state. They are reset to logic 0 whenever
the CPU reads the MODEM Status Register.

Bit 3: This bit enables the MODEM Status Interrupt when
set to logic 1.
Bits 4 through 7: These four bits are always logic O.
8.7 MODEM CONTROL REGISTER
This register controls the interface with the MODEM or data
set (or a peripheral device emulating a MODEM). The contents of the MODEM Control Register (MCR) are indicated

4-32

8.0 Registers (Continued)
Table II shows the contents of the MSR. Details on each bit
follow.
Bit 0: This bit is the Delta Clear to Send (DCTS) indicator.
Bit 0 indicates that the CTS input to the chip has changed
state since the last time it was read by the CPU.

Bit 4: This bit is the complement of the Clear to Send (CTS)
input. If bit 4 (loop) of the MCR is set to a 1, this bit is
equivalent to RTS in the MCR.
Bit 5: This bit is the complement of the Data Set Ready
(DSR) input. If bit 4 of the MCR is set to a 1, this bit is
equivalent to DTR in the MCR.
Bit 6: This bit is the complement of the Ring Indicator (RI)
input. If bit 4 of the MCR is set to a 1, this bit is equivalent to
OUT 1 in the MCR.
Bit 7: This bit is the complement of the Data Carrier Detect
(DCD) input. If bit 4 of the MCR is set to a 1, this bit is
equivalent to OUT 2 in the MCR.

Bit 1: This bit is the Delta Data Set Ready (DDSR) indicator.
Bit t indicates that the DSR input to the chip has changed
state since the last time it was read by the CPU.
Bit 2: This bit is the Trailing Edge of Ring Indicator (TERI)
detector. Bit 2 indicates that the RI input to the chip has
changed from a low to a high state.
Bit 3: This bit is the Delta Data Carrier Detect (DDCD) indicator. Bit 3 indicates that the DCD input to the chip has
changed state.

B.9 SCRATCHPAD REGISTER
This 8-bit Read/Write Register does not control the UART
in any way. It is intended as a scratchpad register to be used
by the programmer to hold data temporarily.

Note: Whenever bit 0, I, 2, or 3 is set to logic I, a MODEM Status Interrupt
is generated.

9.0 Typical Applications
This shows the basic connections of an NS16450 to an NS32016 CPU
ALTERNATE
XTAlCONTROL

All-A23 1:::============:;-;=:>AlB-A23

XlN

16

I

CJ-=-

Al-A3

~~=~~AO-A2

-

'OUT
RClK

14

ADDRESS
DECODER

1&32018
C"'

CSl

RS-232
CONNECTlIt

i!TII

"

m

iIiIi

IIOTl

+5

lliifl

IIIf/iIiT
Ii ..2!-..+5V
N518450

IUART)

m
Olli

00-07

00-07

m

J8

37

36

SOUl

NS32201
TCU

~~-------------i r------~21~IM

WIIi--------------i 1-______"'18~IWIi

SIN

INTR
CSOUl

00-015

OOiS
NC

"

+5V
IVCCI

TLlC/8401-14

4-33

NS16450/lNS8250A/NS16C450/lNS82C50A
CD

(:)

~
'0

Typical shows the basic connections of an INS8250A to an 8088 CPU

n'

ALTERNATE
XTAl CONTROL

r-------'-------,

I
!i'~
D~
I
I
I

v"

I"
I
I

READY
RESET

~

~

RClK

101M

114DSI489

114DSI489

rn
DEN

Rii
iii!

114DSI488

SOUT

18
35

Rii
1/4OS1489

iii!

SIN

INTR

MR

CSOUT

oms
Ne

IVSSI

j
(I)

So

JI

1/408t489

11

O·

5"

8688

OT/R

n'
&»

3-

~
~

"2.

lfi

l!iifj

c:,

'0

'§

iiTA

1m

liiiT2

~

l>

24

13

,.

(Vee)

TlIC/B401-15

9.0 Typical Applications (Continued)
Typical Interface for a
High-Capacity Data Bus

-

~~~~

____

RECEIVER

~~.'=U~.L~I

____

i---l---;
MICROCOMPUTER

SYSTEM

.ATA .~.

.1

I

.....

1.5
~~

INSIIIIIA

L .1TA IUS

.....

Typical Supply Current va
Temperature, Normalized

IIIARI)

1.Or--

I

L_~_J
•. a~C~V~At - -

-

~

o.~ L-----:+"'25!-----:+'"'50=---+,;n

IUS TRANSCEIVER ~.~"'V~IR=-----1DDIS
Dlum
L -__- - '

TL/C/8401-16

10.0 Ordering Information
Order Number

NS16450V }
or
NS·16450V
INSB250A
NS16C450V
INSB2C50AV

AMBIENT TEMPERATURE lOCI
TUC/8401-17

11.0 Reliability Information
Description

Plastic Dip Package
NS16450N}
or
NS-16450N
INSB250AN
NS16C450N
INSB2C50AN
Plastic Chip carrier Package

--I'---

high speed part
Vee = 5V ±5%
CMOS high speed part
CMOS Vee = 5V ±5%

high speed part
Vee = 5V ± 5%
CMOS high speed part
CMOS Vee = 5V ±5%

4·35

Gate Count
XMOS
CMOS

2,000
1,600

Transistor Count
XMOS
CMOS

4,500
6,300

~

~ ~National

~ ~ Semiconductor
NS 16550A Universal Asynchronous ReceiverITransmitter
with FIFOst
General Description

Features

The NS16550A is an improved version of the NS16450 Universal Asynchronous Receiver/Transmitter (UART). The improved specifications ensure compatibility with the
NS32532 and other state-of-the-art CPUs. Functionally
identical to the NS16450 on powerup (CHARACTER
mode)' the NS16550A can be put into an alternate mode
(FIFO mode) to relieve the CPU of excessive software overhead.
In this mode internal FIFOs are activated allowing 16 bytes
(plus 3 bits of error data per byte in the RCVR FIFO) to be
stored in both receive and transmit modes. All the logic is on
chip to minimize system overhead and maximize system efficiency. Two pin functions have been changed to allow signalling of DMA transfers.

• Capable of running all existing 16450 software.
• Pin for pin compatible with the existing 16450 except
for CSOUT (24) and NC (29). The former CSOUT and
NC pins are TXRDY and RXRDY, respectively.
• After reset, all registers are identical to the 16450 register set.
• In the FIFO mode transmitter and receiver are each
buffered with 16 byte FIFO's to reduce the number of
interrrupts presented to the CPU.
• Adds or deletes standard asynchronous communication
bits (start, stop, and parity) to or from the serial data.
• Holding and shift registers in the NS16450 Mode eliminate the need for precise synchronization between the
CPU and serial data.
• Independently controlled transmit, receive, line status,
and data set interrupts.
• Programmable baud generator divides any input clock
by 1 to (2 16 - 1) and generates the 16 x clock.
• Independent receiver clock input.
• MODEM control functions (CTS, RTS, DSR, DTR, RI,
and DCD).
• Fully programmable serial-interface characteristics:
- 5-, 6-, 7-, or a-bit characters
- Even, odd, or no-parity bit generation and detection
- 1-, 1%-, or 2-stop bit generation
- Baud generation (DC to 256k baud).
• False start bit detection.
• Complete status reporting capabilities.
• TRI-STATE@ TTL drive for the data and control buses.
• Line break generation and detection.
• Internal diagnostic capabilities:
- Loopback controls for communications link fault
isolation
- Break, parity, overrun, framing error simulation.
• Full prioritized interrupt system controls.

The UART performs serial-to-parallel conversion on data
characters received from a peripheral device or a MODEM,
and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete
status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the
UART, as well as any error conditions (parity, overrun, framing, or break interrupt).
The UART includes a programmable baud rate generator
that is capable of dividing the timing reference clock input
by divisors of 1 to (216 -1), and producing a 16 x clock for
driving the internal transmitter logic. Provisions are also included to use this 16 x clock to drive the receiver logic. The
UART has complete MODEM-control capability, and a processor-interrupt system. Interrupts can be programmed to
the user's requirements, minimizing the computing required
to handle the communications link.
The UART is fabricated using National Semiconductor's advanced scaled N-channel silicon-gate MOS process, XMOS.
"'Can also be reset to NS16450 Mode under software control.

tNote: This part has a patent pending.

Basic Configuration
ftS18550A

EIA

DRIVERS

~TORS.Zl2

1"""'-----" INTERFACE

TLlC/B652-1

Table of Contents
1.0 ABSOLUTE MAXIMUM RATINGS

8.0 REGISTERS (Continued)
8.3 Programmable Baud Generator
8.4 Line Status Register
8.5 FIFO Control Register
8.6 Interrupt Identification Register
8.7 Interrupt Enable Register
8.8 Modem Control Register
8.9 Modem Status Register
8.10 Scratchpad Register
8.11 FIFO Interrupt Mode Operation
8.12 FIFO Polled Mode Operation

2.0 DC ELECTRICAL CHARACTERISTICS
3.0 AC ELECTRICAL CHARACTERISTICS
4.0 TIMING WAVEFORMS
5.0 BLOCK DIAGRAM
6.0 PIN DESCRIPTIONS

6.1 Input Signals
6.2 Output Signals
6.3 Input/Output Signals

9.0 TYPICAL APPLICATIONS

7.0 CONNECTION DIAGRAMS

10.0 ORDERING INFORMATION

8.0 REGISTERS
8.1 Line Control Register
8.2 Typical Clock Circuits

11.0 RELIABILITY INFORMATION

4·37

1.0 Absolute Maximum Ratings
Note: Maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits is not intended and should be limited to those conditions
specified under DC electrical characteristics.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
O'C to +70'C

Temperature Under Bias
Storage Temperature

- 65'C to + 150'C

All Input or Output Voltages
with Respect to Vss

-0.5Vto +7.0V

Power Dissipation

1W

2.0 DC Electrical Characteristics
TA = O'C to +70'C, Vee = +5V ±5%, Vss =
Symbol

ov,

VILX

Clock Input Low Voltage

VIHX

Clock Input High Voltage

VIL

Input Low Voltage

unless otherwise specified.
Conditions

Parameter

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

IOH = -1.0 mA (Note 1)

lec!AV)

Avg. Power Supply
Current (Veel

Vee = 5.25V
No Loads on output
SIN, DSR, DCD,
CTS, RI = 2.0V
All other inputs = 0.8V

IlL

Input Leakage

leL

Clock Leakage

IOZ

TRI-STATE Leakage

VILMR

CXOUT

Units

0.8

V

2.0

Vee

V

-0.5

0.8

V

2.0

Vee

V

0.4

V

160
(Note 2)

mA

140
(Note 3)

mA

±10

p.A

±10

p.A

±20

p.A

0.8

V

V

2.4

Vee = 5.25V, Vss = OV
All other pins floating.
VIN = OV, 5.25V
Vee = 5.25V, Vss = OV
VOUT = OV,5.25V
1) Chip deselected
2) WRITE mode,
chip selected

MR Schmitt VIL

Capacitance TA =
CXIN

Max

IOL = 1.6 mA on all (Note 1)

2.0

MR Schmitt VIH
VIHMR
Note 1: Does not apply to XOUT
Note 2: TA ~ 25°C
Note 3: TA ~ 70°C

Symbol

Min
-0.5

V

25'C, Vee = Vss = OV

Parameter

Condit