1988_National_Interface_Databook 1988 National Interface Databook

User Manual: 1988_National_Interface_Databook

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400029.2

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Charles E. Sporck
President, Chief Executive Officer
National Semiconductor Corporation

INTERFACE
DATABOOK
1988 Edition

Transmission Line Drivers/Receivers
Bus Transceivers
Peripheral Power Drivers
Display Drivers
Memory Support
Microprocessor Support
Level Translators and Buffers
Frequency Synthesis
Hi-Rei Interface
Appendices/Physical Dimensions
iii

••
•
•

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iv

o-·

5'

Introduction
Since its creation in 1973, National Semiconductor's Interface design and production teams have produced technically
advanced products unparalleled in the semiconductor industry.
Growing from a line of eary drivers and receivers, which pioneered the introduction of the TRI-STATE® function, National Semiconductor's Interface product line today is the most
comprehensive available-with over 200 devices in a variety
of product categories.
Based on its advanced design and process capabilities, National's Interface product line includes:
• The industry's most advanced RS-232 drivers and receivers
• The industry's most advanced RS-422 drivers, receivers
and transceivers
• The industry's most advanced RS-485 drivers, receivers
and transceivers
• The industry's only offering of over 16 devices incorporating power up/down glitch-free protection
• The industry's first Trapezoidal™ bus transceiver
• The industry's first transceivers for the Future Bus standard
• The industry's first fault protected peripheral driver incorporating a major breakthrough in current sensing and shutdown circuitry.
In addition to the detailed Interface product datasheets included in this databook, complete product selection guides
can be found at the beginning of each section for quick reference.
The Interface Appendix supplies helpful application notes,
terms and definitions, cross references, design and process
information and package information.
These Interface devices support and complement National's
VLSI Advanced Peripheral product families. These Advanced
Peripherals Processing Solutions are families of VLSI peripheral circuits deSigned to serve a variety of applications. The
products are especially well suited for microcomputer and
microprocessor based systems such as graphic workstations, personal computers, and many others. National Semiconductor's Advanced Peripheral devices are fully described
in a series of databooks and handbooks.
Among the books are the following titles:
GRAPHICS
MASS STORAGE
DRAM MANAGEMENT
DATACOMMUNICATIONS/LAN/UARTS

All the Advanced Peripheral products currently provided by
National Semiconductor and their appropriate Advanced Peripheral Databook title are listed in a section following the
Table of Contents of this databook.
For more information on National Semiconductor's INTERFACE and Advanced Peripheral products contact your local
National authorized sales representative or distributor.

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Product Status Definitions

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Definition of Terms
This data sheet contains the design specifications for product
development. Specifications may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will
be published at a later date. National Semiconductor Corporation
reserves the right to make changes at any time without notice in order
to improve design and supply the best possible product.
This data sheet contains final specifications. National Semiconductor
Corporation reserves the right to make changes at any time without
notice in order to improve design and supply the best possible product.
National Semiconductor Corporation reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. National does not assume any liability arising out of the application or use of any product
or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

vi

Table of Contents
Alphanumeric Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Additional Information on Advanced Peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 1 Transmission Line Drivers/Receivers
Transmission Line Drivers and Receivers-Introduction .......................... .
Transmission Line Drivers and Receivers-Selection Guide ....................... .
OS1488 Quad Line Driver ..................................................... .
OS14C88/0S14C89A Quad CMOS Line Oriver/Receiver ......................... .
OS1489/0S1489A Quad Line Receiver ........................................ .
OS26C31C CMOS Quad TRI-STATE Differential Line Driver ....................... .
DS26F31C/DS26F31M Quad High Speed Differential Line Driver .................. .
OS26LS31 C/OS26LS31 M Quad High Speed Differential Line Driver ................ .
OS26C32C CMOS Quad Differential Line Receiver ............................... .
OS26F32C/DS26F32M Quad Differential Line Receiver .......................... .
OS26LS32C/OS26LS32M/DS26LS32AC/OS26LS33C/OS26LS33M/OS26LS33AC
Quad Differential Line Receivers ............................................ .
OS34C86 Quad CMOS Differential Line Receiver ................................ .
DS35F86/0S34F86 RS-422/RS-423 Quad Line Receiver with TRI-STATE Outputs .. .
OS3486 Quad RS-422/RS-423 Line Receiver ................................... .
OS34C87 CMOS Quad TRI-STATE Differential Line Driver ........................ .
OS35F87/0S34F87 RS-422 Quad Line Driver with TRI-STATE Outputs ............ .
OS3587/0S3487 Quad TRI-STATE Line Driver .................................. .
OS1603/0S3603 TRI-STATE Dual Receivers ................................... .
OS1650/0S1652/0S3650/0S3652 Quad Differential Line Receivers .............. .
OS1691A/OS3691 RS-422/RS-423 Line Drivers with TRI-STATE Outputs .......... .
OS1692/0S3692 TRI-STATE Differential Line Drivers ............................ .
DS16F95/DS36F95 RS-485/RS-422 Differential Bus Transceiver ................. .
OS3695/0S3695T IOS3696/0S3696T IOS3697 IOS3698 Multipoint RS-485/RS-422
Transceivers/Repeaters ................................................... .
OS551 07/0S751 07/0S551 08/0S751 08/DS75208 Dual Line Receiver ............ .
OS55110AIJ.LA55110A/OS75110AIJ.LA75110A Dual Line Drivers .................. .
OS55113/0S75113 Dual TRI-STATE Differential Line Driver ...................... .
OS55114/0S75114 Dual Differential Line Drivers ................................ .
OS55115/0S75115 Dual Differential Line Receiver .............................. .
OS55121/0S75121 Dual Line Drivers .......................................... .
OS75123 Dual Line Driver .................................................... .
OS75124 Triple Line Receiver ................................................. .
OS75125/0S75127 Seven-Channel Line Receivers .............................. .
OS75128/0S75129 Eight-Channel Line Receivers ............................... .
OS75150 Dual Line Driver .................................................... .
OS75154 Quad Line Receiver ................................................. .
OS75176A/OS75176AT Multipoint RS-485/RS-422 Transceivers .................. .
OS7820/0S8820 Dual Line Receiver ........................................... .
OS7820A/OS8820A Dual Line Receiver ........................................ .
OS78C20/0S88C20 Dual CMOS Compatible Differential Line Receiver ............. .
OS7830/0S8830 Dual Differential Line Driver ................................... .
OS7831 IOS8831 IOS7832/0S8832 Dual TRI-STATE Line Driver .................. .
OS78C120/0S88C120 Dual CMOS Compatible Differential Line Receiver .......... .
OS78LS120/0S88LS120 Dual Differential Line Receiver (Noise Filtering and Fail Safe)
OS8921 IOS8921 A Differential Line Driver and Receiver Pair ...................... .
OS8922/0S8922A/OS8923/0S8923A TRI-STATE RS-422 Dual Differential Line
Driver and Receiver Pairs ................................................... .

vii

xii
xix
1-4
1-6
1-13
1-17
1-23
1-27
1-31
1-34
1-37
1-40
1-44
1-47
1-50
1-54
1-58
1-62
1-66
1-69
1-73
1-81
1-87
1-92
1-98
1-105
1-112
1-117
1-124
1-129
1-134
1-136
1-138
1-141
1-145
1-149
1-153
1-158
1-163
1-167
1-172
1-176 1-180
1-187
1-195
1-202
1-207

Table of Contents (Continued)
Section 1 Transmission Line Drivers/Receivers (Continued)
DS8924 Quad TRI-STATE Differential Line Driver.................................
p.A9622/DS9622 Dual Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
p.A9627/DS9627 Dual Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS9636AI p.A9636A RS-423 Dual Programmable Slew Rate Line Driver .. . . . . . . . . . . .
DS9637 AI p.A9637 A Dual Differential Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS96381 p.A9638 RS-422 Dual High Speed Differential Line Driver . . . . . . . . . . . . . . . . . .
DS9639AI p.A9639A Dual Differential Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS96F172/DS96F174 RS-485/RS-422 Quad Differential Drivers...................
DS96172/p.A96172/DS961741p.A96174 RS-485/RS-422 Quad Differential Line
Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS96F173/DS96F175 RS-485/RS-422 Quad Differential Receivers ................
DS961731 p.A96173/DS961751 p.A96175 RS-485/RS-422 Quad Differential Line
Receivers ................................................ . . . . . . . . . . . . . . . . .
DS961761 p.A96176 RS-485/RS-422 Differential Bus Transceiver. . . . . . . . . . . . . . . . . . .
DS96F177/DS96F178 RS-485/RS-422 Differential Bus Repeaters .................
DS96177 I p.A96177 RS-485/RS-422 Differential Bus Repeater. . . . . . . . . . . . . . . . . . . . .
MM78C29/MM88C29 Quad Single-Ended Line Driver.............................
MM78C30/MM88C30 Quad Differential Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-22 Integrated Circuits for Digital Data Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-1 08 Transmission Line Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-214 Transmission Line Drivers and Receivers for EIA Standards RS-422 and
RS-423 ...................................................................
AN-216 Summary of Electrical Characteristics of Some Well Known Digital Interface
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-409 Transceivers and Repeaters Meeting the EIA RS-485 Interface Standard. . . . .
AN-438 Low Power RS-232C Driver and Receiver in CMOS . . . . . . . . . . . . . . . . . . . . . . . .
AN-457 High Speed, Low Skew RS-422 Drivers and Receivers Solve Critical System
Timing Problems ................. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
p.A9614/DS9614 Dual Differential Line Driver (See DS55114 Datasheet)
p.A9615/DS9615 Dual Differential Line Receiver (See DS55115 Datasheet)
DS55107A Dual Line Receiver (See DS55107 Datasheet)
Section 2 Bus Transceivers
Bus Transceivers-Introduction ................................................
Bus Transceivers-Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8303A 8-Bit TRI-STATE Bidirectional Transceiver (Inverting) ....................
DP7304B/DP8304B 8-Bit TRI-STATE Bidirectional Transceiver (Non-Inverting). . . . . . .
DP8307A 8-Bit TRI-STATE Bidirectional Transceiver (Inverting) ....................
DP7308/DP8308 8-Bit TRI-STATE Bidirectional Transceiver (Non-Inverting) .........
DS26S1 OC/DS26S1 OM/DS26S11 C/DS26S11 M Quad Bus Transceiver. . . . . . . . . . . . .
DS3662 Quad High Speed Trapezoidal Bus Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-259 DS3662-The Bus Optimizer ...........................................
AN-337 Reducing Noise on Microcomputer Buses .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3667 TRI-STATE Bidirectional Transceiver.......................... ..........
DS3862 Octal High Speed Trapezoidal Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3890 BTL Octal Trapezoidal Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3892 BTL Octal TRI-STATE Repeater........................................
DS3898 BTL Octal Trapezoidal Repeater. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3893A BTL Turbotransceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3896/DS3897 Futurebus Trapezoidal Transceivers ............................
AN-458 The Proposed IEEE 896 Futurebus-A Solution to the Bus Driving Problem...

viii

1-213
1-216
1-219
1-223
1-227
1-232
1-236
1-240
1-245
1-250
1-255
1-260
1-267
1-274
1-281
1-281
1-287
1-301
1-307
1-317
1-330
1-337
1-341

2-3
2-4
2-6
2-11
2-16
2-20
2-24
2-29
2-33
2-40
2-47
2-52
2-58
2-58
2-58
2-64
2-69
2-76

Table of Contents (Continued)
Section 2 Bus Transceivers (Continued)
AN-514 Timing Analysis of Synchronous and Asynchronous Buses..................
OS75160A/OS75161A/OS75162A IEEE-488 GPIB Transceivers....... ............
OS7640/0S8640 Quad NOR Unified Bus Receiver ...............................
OS7641/0S8641 Quad Unified Bus Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS7833/0S8833/0S7835/0S8835 Quad TRI-STATE Bus Transceivers............
OS7834/0S8834/0S7839/0S8839 Quad TRI-STATE Bus Transceivers............
OS7836/0S8836 Quad NOR Unified Bus Receiver...............................
OS7837/0S8837 Hex United Bus Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS7838/0S8838 Quad Unified Bus Transceiver..... .............................
OS8T26A/OS8T26AM/OS8T28/0S8T28M 4-Bit Bidirectional Bus Transceivers. . . . . .
Section 3 Peripheral Power Drivers
Peripheral Power Drivers-Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Power Drivers-Selection Guide ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OP731 0/OP831 0/OP7311 /OP8311 Octal Latched Peripheral Drivers ...............
OS1631 /OS3631 /OS1632/0S3632/0S1633/0S3633/0S1634/0S3634 CMOS Dual
Peripheral Drivers ..........................................................
OS3654 Printer Solenoid Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS3656 Quad Peripheral Driver .............................................. , .
OS3658 Quad High Current Peripheral Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS3668 Quad Fault Protected Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS3669 Quad High Current Peripheral Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS3680 Quad Negative Voltage Relay Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS3686 Dual Positive Voltage Relay Driver ......................................
OS1687/0S3687 Negative Voltage Relay Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS55451/2/3/4, OS75450/1 /2/3/4 Series Dual Peripheral Drivers ............... , .
OS55461 /2/3/4, OS75461 /2/3/4 Series Dual Peripheral Drivers. . . . . . . . . . . . . . . . .. .
OS2001 / J.tA9665/0S2002/ J.tA9666/0S2003/ J.tA9667 /OS2004/ J.tA9668 High
Current/Voltage Darlington Drivers ...........................................
AN-213 Safe Operating Areas for Peripheral Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 4 Display Drivers
Display Drivers-Introduction ..................................................
Display Drivers-Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS75491 MOS-to-LEO Quad Segment Driver ....................................
OS75492 MOS-to-LEO Hex Digit Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS55493/0S75493 Quad LED Segment Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS55494/0S75494 Hex Digit Driver............................................
OS8654 8-0utput Display Driver (LED, VF, Thermal Printer) ........................
OS8669 2-0igit BCD to 7-Segment Decoder/Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS8863/0S8963 MOS-to-LEO 8-0igit Driver. . . . . . .. . . .. .. . . . . . . . . . .. .. .. . .. . . . . .
OS8870 Hex LED Digit Driver ..................................................
OS8874 9-0igit Shift Input LED Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS7880/0S8880 High Voltage 7-Segment Oecoder/Oriver ........................
OS8881 Vacuum Fluorescent Display Driver .....................................
OS8884A High Voltage Cathode Decoder/Driver.................................
OS8973 9-0igit LED Driver. . . . . . . .. . . . . . . . . . . . . . . .. . .. .. .. . .. .. . . . . .. .. . .. . . . ..
AN-84 Driving 7-Segment Gas Discharge Display Tubes with National Semiconductor
Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5450/MM5451 LED Display Drivers.........................................
MM5452/MM5453 Liquid Crystal Display Drivers..... .......................... ..
MM5480 LED Display Driver...................................................

ix

2-81
2-88
2-96
2-98
2-101
2-105
2-109
2-111
2-114
2-117
3-3
3-4
3-5
3-12
3-17
3-21
3-23
3-26
3-29
3-32
3-35
3-38
3-41
3-57
3-65
3-70
4-3
4-4
4-6
4-6
4-9
4-12
4-14
4-18
4-21
4-24
4-26
4-28
4-32
4-36
4-39
4-41
4-44
4-50
4-57

Table of Contents (Continued)
Section 4 Display Drivers (Continued)
MM5481 lED Display Driver......................... ..........................
MM5483 Liquid Crystal Display Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM548416-8egment lED Display Driver................ ........................
MM5486 lED Display Driver...................................................
MM58201 Multiplexed LCD Driver.................... ..................... .....
MM58241 High Voltage Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM58242 High Voltage Display Driver................. ..................... .....
MM58248 High Voltage Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM58341 High Voltage Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM58342 High Voltage Display Driver................. ..........................
MM58348 High Voltage Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-350 Designing an LCD Dot Matrix Display Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-371 The MM58348/342/341 /248/242/241 Directly Drive Vacuum Fluorescent
(VF) Displays .......................................... ~ . . . . . . . . . . . . . . . . . . .
AN-378 A Novel Process for Vacuum Fluorescent (VF) Display Drivers ..............
AN-440 New CM08 Vacuum Fluorescent Drivers Enable Three Chip 8ystem to
Provide Intelligent Control of Dot Matrix VF Display. ...................... ......
Section 5 Memory Support
Memory 8upport-lntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory 8upport-8election Guide .............................................
DP84240/DP84244 Octal TRI-8TATE M08 Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D80025C Two Phase M08 Clock Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D80026/D80056 5 MHz Two Phase M08 Clock Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . .
D83245 Quad M08 Clock Driver ...............................................
D81628/D83628 Octal TRI-8TATE M08 Drivers......................... ........
D83647A Quad TRI-8TATE M08 Memory I/O Register...........................
D81648/D83648/D81678/D83678 TRI-8TATE TTL to M08 Multiplexers/Drivers....
D81649/D83649/D81679/D83679 Hex TRI-8TATE TTL to M08 Drivers........... .
D81651/D83651 Quad High 8peed M08 8ense Amplifiers........................
D81674/D83674 Quad TTL to M08 Clock Driver.................................
D816149/D836149/D816179/D836179 Hex M08 Drivers........................
D855325/D875325 Memory Drivers............. .............................. .
D875361 Dual TTl-to-M08 Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D875365 Quad TTl-to-M08 Driver............... ..............................
D89643/p.A9643 Dual TTL to M08/CCD Driver... .............................. .
AN-76 Applying Modern Clock Drivers to M08 Memories . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 6 Microprocessor Support
Microprocessor 8upport-lntroduction ..........................................
Microprocessor 8upport-8election Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8212/DP8212M 8-Bit Input/Output Port ......................................
DP8216/DP8216M/DP8226/DP8226M 4-Bit Bidirectional Bus Transceiver........ ..
DP8224 Clock Generator and Driver ............................................
DP8228/DP8228M/DP8238/DP8238M 8ystem Controller and Bus Driver ...........
Section 7 Level Translators and Buffers
level Translators and Buffers-Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
level Translators and Buffers-8election Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8480A 10k ECl-to-TTL level Translator with latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8481 TTl-to-1 Ok ECl level Translator with latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8482A 1OOk ECl to TTL level Translator with latch. . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8483 TTl-to-1 OOk ECl level Translator with latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
x

4-61
4-65
4-68
4-71
4-76
4-82
4-87
4-92
4-97
4-102
4-107
4-112
4-131
4-142
4-148
5-3
5-4
5-5
5-10
5-14
5-22
5-25
5-28
5-34
5-39
5-43
5-49
5-54
5-58
5-71
5-76
5-81
5-85
6-3
6-4
6-5
6-13
6-18
6-24
7-3
7-4
7-5
7-8
7-11
7-14

Table of Contents (Continued)
Section 7 Level Translators and Buffers (Continued)
OS1630B/OS3630B Hex CMOS Compatible Buffer, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,
OS7800/0S8800 Oual Voltage Level Translator, , , , , , , .. , .... , ........ , .. , , .. , . , ,
OS78L 12/0S88L12 Hex TIL-MOS Inverter/lnterface Gate, , , , , , , , , , , , , , , , , , , , , , , ,
Section 8 Frequency Synthesis
Frequency Synthesis-Introduction , , , , , , ... , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,
Frequency Synthesis-Selection Guide, , , , . , , , , , , , , , , , , , , , , , , , . , , , , , , , , , , , , . , , , ,
OS8614/0S8615/0S8616/0S8617130/225 MHz Low Power Oual Modulus
Prescalers , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , . , , , , , , , , , , , , , , ,
OS8627/0S8628 130/225 MHz Low Power Prescalers . , , , , , , , , , , , , , , , , , , , , , , , , , , ,
OS8629 120 MHz Oivide-by-100 Prescaler .... " ........ , .. , ...... , .... ,",......
OS8673/0S8674 Low Power VHF/UHF Prescalers " " " " " ' , . , " ' , . , " " ' , . , ' "
OS8906 AM/FM Oigital Phase-Locked Loop Synthesizer .,"',"',"',",'.".,,"
OS8907 AM/FM Oigital Phase-Locked Loop Frequency Synthesizer ",",.,",","
OS8908 AM/FM Oigital Phase-Locked Loop Frequency Synthesizer"",,"""""
OS8911 AM/FM/TV Sound Up-Conversion Frequency Synthesizer, , , , , , , , , , , , , , , , ,
AN-335 Oigital PLL Synthesis " " " " " " " , . , " " " " " " " " ' , . , " " " " " ' "
AN-512 OS8911 AM/FM/TV Sound Up-Conversion Frequency Synthesizer, , , , .. , , , ,
Section 9 Hi-Rei Interface
Hi-Rei Interface-Introduction , , , , , , , , , , , , , . , .... , . , , .. , .. , , ...... , , ... , , , . . . . . .
National's A + Program " " " " " " " " , " " " , " . , ' , , " " ' , ' , " ' , " , " " ' , , "
Hi-Rei Interface-Selection Guide " " " , , " " ' , , " " ' , , " " ' , ' , " " , ' , " " ' , , "
Section 10 Appendices and Physical Dimensions
Application Note Index, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , . , , , , , , , , , , , , , ,
Technical Terms and Oefinitions , , , . , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,
Interface Product Cross Reference Guide, , , , , , , , , , , , , , , , , , , , , , , , , , . , , , , , , , , , , , , ,
Industry Package Cross Reference Guide, , , , , , , . , , , , , , , , , , , , , , , , , , . , , , , , , , , , , , , ,
Packaging and Physical Dimensions
AN-336 Understanding Integrated Circuit Package Power Capabilities, , , , , , , , , . , . , , ,
AN-450 Small Outline (S,O,) Package Surface Mounting Methods-Parameters and
Their Effect on Product Reliability, , , , , , , , , , , , , . , . , , , , , , , , , , , , . , , , , , , , , , , , , , , , ,
Physical Oimensions , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,
Oata Bookshelf
Sales and Oistribution Offices

xi

7-17
7-21
7-24
8-3
8-5
8-6
8-10
8-13
8-16
8-19
8-26
8-32
8-40
8-49
8-56
9-3
9-13
9-15
10-3
10-4
10-6
10-13
10-16
10-21
10-31

Alpha-Numeric Index
AN-22 Integrated Circuits for Digital Data Transmission ....................................... 1-287
AN-76 Applying Modern Clock Drivers to MOS Memories ...................................... 5-85
AN-84 Driving 7 -Segment Gas Discharge Display Tubes with National Semiconductor Drivers ...... 4-41
AN-1 08 Transmission Line Characteristics .................................................. 1-301
AN-213 Safe Operating Areas for Peripheral Drivers ........................................... 3-70
AN-214 Transmission Line Drivers and Receivers for EIA Standards RS-422 and RS-423 ......... 1-307
AN-216 Summary of Electrical Characteristics of Some Well Known Digital Interface Standards .... 1-317
AN-259 DS3662-The Bus Optimizer ....................................................... 2-33
AN-335 Digital Pll Synthesis .............................................................. 8-49
AN-336 Understanding Integrated Circuit Package Power Capabilities .......................... 10-16
AN-337 Reducing Noise on Microcomputer Buses ............................................. 2-40
AN-350 Designing an LCD Dot Matrix Display Interface ....................................... 4-112
AN-371 The MM58348/342/341 1248/242/241 Directly Drive Vacuum Fluorescent (VF) Displays .. 4-131
AN-378 A Novel Process for Vacuum Fluorescent (VF) Display Driver .......................... 4-142
AN-409 Transceivers and Repeaters Meeting the EIA RS-485 Interface Standard ................ 1-330
AN-438 low Power RS-232C Driver and Receiver in CMOS ................................... 1-337
AN-440 New CMOS Vacuum Fluorescent Drivers Enable Three Chip System to Provide
Intelligent Control of Dot Matrix VFDisplay ................................................ 4-148
AN-450 Small Outline (S.O.) Package Surface Mounting Methods-Parameters and
Their Effect on Product Reliability ........................................................ 10-21
AN-457 High Speed, low Skew RS-422 Drivers and Receivers Solve Critical System
Timing Problems ...................................................................... 1-341
AN-458 The Proposed IEEE 896 Futurebus-A Solution to the Bus Driving Problem ............... 2-76
AN-512 DS8911 AM/FM/TV Sound Up-Conversion Frequency Synthesizer ...................... 8-56
AN-514 Timing Analysis of Synchronous and Asynchronous Buses .............................. 2-81
DP7304B 8-Bit TRI-STATE Bidirectional Transceiver (Non-Inverting) ............................ 2-11
DP73088-Bit TRI-STATE Bidirectional Transceiver (Non-Inverting) ............................. 2-20
DP7310 Octal latched Peripheral Driver ...................................................... 3-5
DP7311 Octal latched Peripheral Driver ...................................................... 3-5
DP8212 8-Bit Input/Output Port .............................................................. 6-5
DP8212M 8-Bit Input/Output Port ............................................................ 6-5
DP8216 4-Bit Bidirectional Bus Transceiver .................................................. 6-13
DP8216M 4-Bit Bidirectional Bus Transceiver ................................................ 6-13
DP8224 Clock Generator and Driver ........................................................ 6-18
DP8226 4-Bit Bidirectional Bus Transceiver .................................................. 6-13
DP8226M 4-Bit Bidirectional Bus Transceiver ................................................ 6-13
DP8228 System Controller and Bus Driver ................................................... 6-24
DP8228M System Controller and Bus Driver ................................................. 6-24
DP8238 System Controller and Bus Driver ................................................... 6-24
DP8238M System Controller and Bus Driver ................................................. 6-24
DP8303A 8-Bit TRI-STATE Bidirectional Transceiver (Inverting) .................................. 2-6
DP8304B 8-Bit TRI-STATE Bidirectional Transceiver (Non-Inverting) ............................ 2-11
DP8307A 8-Bit TRI-STATE Bidirectional Transceiver (Inverting) ................................ 2-16
DP8308 8-Bit TRI-STATE Bidirectional Transceiver (Non-Inverting) ............................. 2-20
DP8310 Octal latched Peripheral Driver ...................................................... 3-5
DP8311 Octal latched Peripheral Driver ...................................................... 3-5
DP8480A 10k ECl-to-TTl level Translator with latch .......................................... 7-5
DP8481 TTl-to-1 Ok ECl level Translator with latch ........................................... 7-8
DP8482A 1OOk ECl to TTL level Translator with latch ........................................ 7-11
DP8483 TTl-to-1 OOk ECl level Translator with latch ......................................... 7-14
DP84240 Octal TRI-STATE MOS Driver ...................................................... 5-5

xii

Alpha-Numeric

Index(continUed)

DP84244 Octal TRI-STATE MOS Driver ...................................................... 5-5
DS8T26A 4-Bit Bidirectional Bus Transceiver ............................................... 2-117
DS8T26AM 4-Bit Bidirectional Bus Transceiver .............................................. 2-117
DS8T28 4-Bit Bidirectional Bus Transceiver ................................................. 2-117
DS8T28M 4-Bit Bidirectional Bus Transceiver ............................................... 2-117
DS14C88 Quad CMOS Line Driver/Receiver ................................................. 1-17
DS14C89A Quad CMOS Line Driver/Receiver ...................•............................ 1-17
DS16F95 RS-485/RS-422 Differential Bus Transceiver ............ ; ........................... 1-92
DS0025C Two Phase MOS Clock Driver ..................................................... 5-10
DS00265 MHz Two Phase MaS Clock Driver ................................................ 5-14
DS26C31 C CMOS Quad TR I-STATE Differential Line Driver ....•..•............................ 1-27
DS26C32C CMOS Quad Differential Line Receiver ........•.........•......................... 1-37
DS26F31C Quad High Speed Differential Line Driver .......................................... 1-31
DS26F31 M Quad High Speed Differential Line Driver .......................................... 1-31
DS26F32C Quad Differential Line Receiver .................................................. 1-40
DS26F32M Quad Differential Line Receiver .................................................. 1-40
DS26LS31C Quad High Speed Differential Line Driver ......................................... 1-34
DS26LS31M Quad High Speed Differential Line Driver ........................................ 1-34
DS26LS32AC Quad Differential Line Receiver .........................•...................... 1-44
DS26LS32C Quad Differential Line Receiver ................................................. 1-44
DS26LS32M Quad Differential Line Receiver ................................................. 1-44
DS26LS33AC Quad Differential Line Receiver ................................................ 1-44
DS26LS33C Quad Differential Line Receiver ................................................. 1-44
DS26LS33M Quad Differential Line Receiver ...................................•............. 1-44
DS26S 1OC Quad Bus Transceiver ...................•...................................... 2-24
DS26S1 OM Quad Bus Transceiver .......................................................... 2-24
DS26S11C Quad Bus Transceiver .......................•.................................. 2-24
DS26S11 M Quad Bus Transceiver .......................................................... 2-24
DS34C86 Quad CMOS Differential Line Receiver ............................................. 1-47
DS34C87 CMOS Quad TRI-STATE Differential Line Driver ..................................... 1-58
DS34F86 RS-422/RS-423 Quad Line Receiver with TRI-STATE Outputs ........................ 1-50
DS34F87 RS-422 Quad Line Driver with TRI-STATE Outputs ................................... 1-62
DS35F86 RS-422/RS-423 Quad Line Receiver with TRI-STATE Outputs ........................ 1-50
DS35F87 RS-422 Quad Line Driver with TRI-STATE Outputs ................................... 1-62
DS36F95 RS-485/RS-422 Differential Bus Transceiver ........................................ 1-92
DS00565 MHz Two Phase MOS Clock Driver ................................................ 5-14
DS78C20 Dual CMOS Compatible Differential Line Receiver .................................. 1-17£
DS78C120 Dual CMOS Compatible Differential Line Receiver ................................. 1-187
DS78L 12 Hex TTL-MOS Inverter/Interface Gate .............................................. 7-24
DS78LS120 Dual Differential Line Receiver (Noise Filtering and Fail Safe) ...................... 1-195
DS88C20 Dual CMOS Compatible Differential Line Receiver .........•........................ 1-172
DS88C120 Dual CMOS Compatible Differential Line Receiver ................................. 1-187
DS88L12 Hex TIL-MOS Inverter/Interface Gate .............................................. 7-24
DS88LS120 Dual Differential Line Receiver (Noise Filtering and Fail Safe) ...................... 1-195
DS96F172 RS-485/RS-422 Quad Differential Driver ......................................... 1-240
DS96F173 RS-485/RS-422 Quad Differential Receiver ....................................... 1-250
DS96F174 RS-485/RS-422 Quad Differential Driver ......................................... 1-240
DS96F175 RS-485/RS-422 Quad Differential Receiver ....................................... 1-250
DS96F177 RS-485/RS-422 Differential Bus Repeater .......•................................ 1-267
DS96F178 RS-485/RS-422 Differential Bus Repeater .....•..•..•............................ 1-267
DS1488 Quad Line Driver ...................................................•.............. 1-13

xiii

Alpha-Numeric

Index(continUed)

DS1489 Quad Line Receiver ............................................................... 1-23
DS1489A Quad Line Receiver .......................................... " ................... 1-23
DS1603 TRI-STATE Dual Receiver .....................................................•... 1-69
DS1628 Octal TRI-STATE MOS Driver ...................................................... 5-25
DS1630B Hex CMOS Compatible Buffer ..................................................... 7-17
OS 1631 CMOS Dual Peripheral Driver ....................................................... 3-12
DS1632 CMOS Dual Peripheral Driver ....................................................... 3-12
DS1633 CMOS Dual Peripheral Driver ....................................................... 3-12
OS 1634 CMOS Dual Peripheral Driver ....................................................... 3-12
DS1648 TRI-STATE TTL to MOS Multiplexer/Driver .......................................... 5-34
DS1649 Hex TRI-STATE TTL to MOS Driver ................................................. 5-39
DS1650 Quad Differential Line Receiver ..................................................... 1-73
DS1651 Quad High Speed MOS Sense Amplifier ............................................. 5-43
DS1652 Quad Differential Line Receiver ..................................................... 1-73
DS1674 Quad TTL to MOS Clock Driver ..................................................... 5-49
DS1678 TRI-STATE TTL to MOS Multiplexer/Driver .......................................... 5-34
DS1679 Hex TRI-STATE TTL to MOS Driver ................................................. 5-39
DS1687 Negative Voltage Relay Driver ...................................................... 3-38
DS1691A RS-422/RS-423 Line Driver with TRI-STATE Outputs ................................ 1-81
DS1692 TRI-STATE Differential Line Driver .................................................. 1-87
DS2001 High Current/Voltage Darlington Driver .............................................. 3-65
DS2002 High Current/Voltage Darlington Driver .............................................. 3-65
DS2003 High Current/Voltage Darlington Driver .............................................. 3-65
DS2004 High Current/Voltage Darlington Driver .............................................. 3-65
DS3245 Quad MOS Clock Driver ........................................................... 5-22
DS3486 Quad RS-422/RS-423 Line Receiver ................................................ 1-54
DS3487 Quad TRI-STATE Line Driver ....................................................... 1-66
DS3587 Quad TRI-STATE Line Driver ....................................................... 1-66
DS3603 TRI-STATE Dual Receiver ......................................................... 1-69
DS3628 Octal TRI-STATE MOS Driver ...................................................... 5-25
DS3630B Hex CMOS Compatible Buffer ..................................................... 7-17
DS3631 CMOS Dual Peripheral Driver ....................................................... 3-12
DS3632 CMOS Dual Peripheral Driver . ~ ...................................••................. 3-12
DS3633 CMOS Dual Peripheral Driver ...................................••...........••..... 3-12
DS3634 CMOS Dual Peripheral Driver ...........................•...................••...... 3-12
DS3647A Quad TRI-STATE MOS Memory I/O Register •.........•............................ 5-28
DS3648 TRI-STATE TTL to MOS Multiplexer/Driver ....................................•..... 5-34
DS3649 Hex TRI-STATE TTL to MOS Driver ................................................. 5-39
DS3650 Quad Differential Line Receiver ..................................................... 1-73
OS3651 Quad High Speed MOS Sense Amplifier ............................................. 5-43
OS3652 Quad Differential Line Receiver ................................•.................... 1-73
OS3654 Printer Solenoid Driver ............................................................. 3-17
OS3656 Quad Peripheral Driver ............................................................ 3-21
OS3658 Quad High Current Peripheral Driver ..................•.............................. 3-23
OS3662 Quad High Speed Trapezoidal Bus Transceiver ....................................... 2-29
OS3667 TRI-STATE Bidirectional Transceiver ................................................ 2-47
DS3668 Quad Fault Protected Peripheral Driver ........... ; .................................. 3-26
DS3669 Quad High Current Peripheral Driver ................................................. 3-29
OS3674 Quad TTL to MOS Clock Driver ..................................................... 5-49
OS3678 TRI-STATE TTL to MOS Multiplexer/Driver .......................................... 5-34
OS3679 Hex TRI-STATE TTL to MOS Driver ................................................. 5-39

xiv

Alpha-Numeric

Index(Continued)

DS3680 Quad Negative Voltage Relay Driver ................................................. 3-32
DS3686 Dual Positive Voltage Relay Driver .................................................. 3-35
DS3687 Negative Voltage Relay Driver ...................................................... 3-38
DS3691 RS-422/RS-423 Line Driver with TRI-STATE Outputs .................................. 1-81
DS3692 TRI-STATE Differential Line Driver .................................................. 1-87
DS3695 Multipoint RS-485/RS-422 Transceiver/Repeater ..................................... 1-98
DS3695T Multipoint RS-485/RS-422 Transceiver/Repeater ................................... 1-98
DS3696 Multipoint RS-485/RS-422 Transceiver/Repeater ..................................... 1-98
DS3696T Multipoint RS-485/RS-422 Transceiver/Repeater ................................... 1-98
DS3697 Multipoint RS-485/RS-422 Transceiver/Repeater ..................................... 1-98
DS3698 Multipoint RS-485/RS-422 Transceiver/Repeater ..................................... 1-98
DS3862 Octal High Speed Trapezoidal Bus Transceiver ....................................... 2-52
DS3890 BTL Octal Trapezoidal Driver .................•.........................•........... 2-58
DS3892 BTL Octal TRI-STATE Repeater .................................................... 2-58
DS3893A BTL Turbotransceiver ............................................................ 2-64
DS3896 Futurebus Trapezoidal Transceiver .................................................. 2-69
DS3897 Futurebus Trapezoidal Transceiver .................................................. 2-69
DS3898 BTL Octal Trapezoidal Repeater .............•...................................... 2-58
DS7640 Quad NOR Unified Bus Receiver .................................................... 2-96
DS7641 Quad Unified Bus Transceiver ...................................................... 2-98
DS7800 Dual Voltage Level Translator ...................................................... 7-21
DS7820 Dual Line Receiver ............................................................... 1-163
DS7820A Dual Line Receiver ............................................................. 1-167
DS7830 Dual Differential Line Driver ....................................................... 1-176
DS7831 Dual TRI-STATE Line Driver ....................................................... 1-180
DS7832 Dual TRI-STATE Line Driver ....................................................... 1-180
DS7833 Quad TRI-STATE Bus Transceiver ................................................. 2-101
DS7834 Quad TRI-STATE Bus Transceiver ................................................. 2-105
DS7835 Quad TRI-STATE Bus Transceiver ................................................. 2-101
DS7836 Quad NOR Unified Bus Receiver ................................................... 2-109
DS7837 Hex United Bus Receiver ......................................................... 2-111
DS7838 Quad Unified Bus Transceiver ..................................................... 2-114
DS7839 Quad TRI-STATE Bus Transceiver ...............•................................. 2-105
DS7880 High Voltage 7-Segment Decoder/Driver ............................................ 4-28
DS8614130/225 MHz Low Power Dual Modulus Prescaler ..................................... 8-6
DS8615 130/225 MHz Low Power Dual Modulus Prescaler ..................................... 8-6
DS8616 130/225 MHz Low Power Dual Modulus Prescaler ..................................... 8-6
DS8617 130/225 MHz Low Power Dual Modulus Prescaler ..................................... 8-6
DS8627 130/225 MHz Low Power Prescaler ................................................. 8-10
DS8628130/225 MHz Low Power Prescaler ................................................. 8-10
DS8629120 MHz Divide-by-100 Prescaler .....................•............................. 8-13
DS8640 Quad NOR Unified Bus Receiver .................................................... 2-96
DS8641 Quad Unified Bus Transceiver ...................................................... 2-98
DS8654 8-0utput Display Driver (LED, VF, Thermal Printer) .................................... 4-14
DS8669 2-Digit BCD to 7-Segment Decoder/Driver ........................................... 4-18
DS8673 Low Power VHF/UHF Prescaler .................................................... 8-16
DS8674 Low Power VHF/UHF Prescaler .................................................... 8-16
DS8800 Dual Voltage Level Translator ..................................•................... 7-21
DS8820 Dual Line Receiver .............................................•................. 1-163
DS8820A Dual Line Receiver ....................................................•........ 1-167
DS8830 Dual Differential Line Driver ....................................................... 1-176

xv

Alpha-Numeric

Index(continUed)

OS8831 Dual TRI-STATE Line Driver ....................................................... 1-180
OS8832 Dual TRI-STATE Line Driver ........................•.............................. 1-180
OS8833 Quad TRI-STATE Bus Transceiver ................................................. 2-101
OS8834 Quad TRI-STATE Bus Transceiver ................................................. 2-105
OS8835 Quad TRI-STATE Bus Transceiver ................................................. 2-101
OS8836 Quad NOR Unified Bus Receiver ................................................... 2-109
OS8837 Hex United Bus Receiver ......................................................... 2-111
OS8838 Quad Unified Bus Transceiver ..................................................... 2-114
OS8839 Quad TRI-STATE Bus Transceiver ................................................. 2-105
OS8863 MOS-to-LED 8-Digit Driver ......................................................... 4-21
OS8870 Hex LED Digit Driver .............................................................. 4-24
OS8874 9-Digit Shift Input LED Driver ....................................................... 4-26
OS8880 High Voltage 7-Segment Decoder/Driver ........................................•... 4-28
OS8881 Vacuum Fluorescent Display Driver ................................................. 4-32
OS8884A High Voltage Cathode Decoder/Driver ............................................. 4-36
OS8906 AM/FM Digital Phase-Locked Loop Synthesizer ...................................... 8-19
OS8907 AM/FM Digital Phase-Locked Loop Frequency Synthesizer ............................ 8-26
OS8908 AM/FM Digital Phase-Locked Loop Frequency Synthesizer ............................ 8-32
OS8911 AM/FM/TV Sound Up-Conversion Frequency Synthesizer ............................. 8-40
OS8921 Differential Line Driver and Receiver Pair ........................................... 1-202
OS8921 A Differential Line Driver and Receiver Pair .......................................... 1-202
OS8922 TRI-STATE RS-422 Dual Differential Line Driver and Receiver Pair ..................... 1-207
OS8922A TRI-STATE RS-422 Dual Differential Line Driver and Receiver Pair .................... 1-207
OS8923 TRI-STATE RS-422 Dual Differential Line Driver and Receiver Pair ..................... 1-207
OS8923A TRI-STATE RS-422 Dual Differential Line Driver and Receiver Pair .................... 1-207
OS8924 Quad TRI-STATE Differential Line Driver ............................................ 1-213
OS8963 MOS-to-LED 8-Digit Driver ......................................................... 4-21
OS8973 9-Digit LED Driver ................................................................. 4-39
OS9614 Dual Differential Line Driver (See DS55114 Datasheet) ............................... 1-124
OS9615 Dual Differential Line Receiver (See DS55115 Datasheet) ............................. 1-129
OS9622 Dual Line Receiver ............................................................... 1-216
OS9627 Dual Line Receiver ............................................................... 1-219
OS9636A RS-423 Dual Programmable Slew Rate Line Driver .................................. 1-223
OS9637A Dual Differential Line Receiver ................................................... 1-227
OS9638 RS-422 Dual High Speed Differential Line Driver ..................................... 1-232
OS9639A Dual Differential Line Receiver ................................................... 1-236
OS9643 Dual TTL to MOS/CCD Driver ...................................................... 5-81
OS16149 Hex MOS Driver ................................................................. 5-54
OS16179 Hex MOS Driver ................................................................. 5-54
OS36149 Hex MOS Driver ................................................................. 5-54
OS36179 Hex MOS Driver ................................................. ~ ............... 5-54
OS55107 Dual Line Receiver ............................................................. 1-105
OS55107A Dual Line Receiver (See DS55107 Datasheet) .................................... 1-105
OS55108 Dual Line Receiver ............................................................. 1-105
OS55110A Dual Line Driver ............................................................... 1-112
OS55113 Dual TRI-STATE Differential Line Driver ...•....................................... 1-117
OS55114 Dual Differential Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-124
OS55115 Dual Differential Line Receiver ................................................... 1-129
OS55121 Dual Line Driver ................................................................ 1-134
OS55325 Memory Driver .................................................................. 5-58
OS55451 Series Dual Peripheral Driver ...................................................... 3-41

xvi

Alpha-Numeric

Index(continUed)

DS55452 Series Dual Peripheral Driver ...................................................... 3-41
DS55453 Series Dual Peripheral Driver ...................................................... 3-41
DS55454 Series Dual Peripheral Driver ...................................................... 3-41
DS55461 Series Dual Peripheral Driver ...................................................... 3-57
DS55462 Series Dual Peripheral Driver ...................................................... 3-57
DS55463 Series Dual Peripheral Driver ...................................................... 3-57
DS55464 Series Dual Peripheral Driver ...................................................... 3-57
DS55493 Quad LED Segment Driver ......................................................... 4-9
DS55494 Hex Digit Driver .................................................................. 4-12
DS75107 Dual Line Receiver ............................................................. 1-105
DS75108 Dual Line Receiver ............................................................. 1-105
DS75110A Dual Line Driver ............................................................... 1-112
DS75113 Dual TR I-STATE Differential Line Driver ........................................... 1-117
DS75114 Dual Differential Line Driver ...................................................... 1-124
DS75115 Dual Differential Line Receiver ................................................... 1-129
DS75121 Dual Line Driver ................................................................ 1-134
DS75123 Dual Line Driver ................................................................ 1-136
DS75124 Triple Line Receiver ............................................................. 1-138
DS75125 Seven-Channel Line Receiver .................................................... 1-141
DS75127 Seven-Channel Line Receiver .................................................... 1-141
DS75128 Eight-Channel Line Receiver ..................................................... 1-145
DS75129 Eight-Channel Line Receiver ..................................................... 1-145
DS75150 Dual Line Driver ................................................................ 1-149
DS75154 Quad Line Receiver ............................................................. 1-153
DS75160A IEEE-488 GPIB Transceiver ..................................................... 2-88
DS75161A IEEE-488 GPIB Transceiver ..................................................... 2-88
DS75162A IEEE-488 GPIB Transceiver ..................................................... 2-88
DS75176A Multipoint RS-485/RS-422 Transceiver .......................................... 1-158
DS75176AT Multipoint RS-485/RS-422 Transceiver ......................................... 1-158
DS75208 Dual Line Receiver ............................................................. 1-105
DS75325 Memory Driver .................................................................. 5-58
DS75361 Dual TTL-to-MOS Driver .......................................................... 5-71
DS75365 Quad TTL-to-MOS Driver ......................................................... 5-76
DS75450 Series Dual Peripheral Driver ...................................................... 3-41
DS75451 Series Dual Peripheral Driver ...................................................... 3-41
DS75452 Series Dual Peripheral Driver ...................................................... 3-41
DS75453 Series Dual Peripheral Driver ...................................................... 3-41
DS75454 Series Dual Peripheral Driver ...................................................... 3-41
DS75461 Series Dual Peripheral Driver ...................................................... 3-57
DS75462 Series Dual Peripheral Driver ...................................................... 3-57
DS75463 Series Dual Peripheral Driver ...................................................... 3-57
DS75464 Series Dual Peripheral Driver ...................................................... 3-57
DS75491 MOS-to-LED Quad Segment Driver ................................................. 4-6
DS75492 MOS-to-LED Hex Digit Driver ....................................................... 4-6
DS75493 Quad LED Segment Driver ......................................................... 4-9
DS75494 Hex Digit Driver .................................................................. 4-12
DS96172 RS-485/RS-422 Quad Differential Line Driver ...................................... 1-245
DS96173 RS-485/RS-422 Quad Differential Line Receiver .................................... 1-255
DS96174 RS-485/RS-422 Quad Differential Line Driver ...................................... 1-245
DS96175 RS-485/RS-422 Quad Differential Line Receiver .................................... 1-255
DS96176 RS-485/RS-422 Differential Bus Transceiver ....................................... 1-260

xvii

Alpha-Numeric

Index(continUed)

DS96177 RS-485/RS-422 Differential Bus Repeater ......................................... 1-274
MM78C29 Quad Single-Ended Line Driver .................................................. 1-281
MM78C30 Quad Differential Line Driver .................................................... 1-281
MM88C29 Quad Single-Ended Line Driver .................................................. 1-281
MM88C30 Quad Differential Line Driver .................................................... 1-281
MM5450 LED Display Driver ............................................................... 4-44
MM5451 LED Display Driver ............................................................... 4-44
MM5452 Liquid Crystal Display Driver ....................................................... 4-50
MM5453 Liquid Crystal Display Driver ....................................................... 4-50
MM5480 LED Display Driver ............................................................... 4-57
MM5481 LED Display Driver ............................................................... 4-61
MM5483 Liquid Crystal Display Driver ....................................................... 4-65
MM5484 16-Segment LED Display Driver .................................................... 4-68
MM5486 LED Display Driver ............................................................... 4-71
MM58201 Multiplexed LCD Driver .......................................................... 4-76
MM58241 High Voltage Display Driver ....................................................... 4-82
MM58242 High Voltage Display Driver ....................................................... 4-87
MM58248 High Voltage Display Driver ....................................................... 4-92
MM58341 High Voltage Display Driver ....................................................... 4-97
MM58342 High Voltage Display Driver ..................................................... 4-102
MM58348 High Voltage Display Driver ..................................................... 4-107
p,A9614 Dual Differential Line Driver (See DS55114 Datasheet) ............................... 1-124
p,A9615 Dual Differential Line Receiver (See DS55115 Datasheet) ............................. 1-129
p,A9622 Dual Line Receiver ............................................................... 1-216
p,A9627 Dual Line Receiver ............................................................... 1-219
p,A9636A RS-423 Dual Programmable Slew Rate Line Driver .................................. 1-223
p,A9637 A Dual Differential Line Receiver ................................................... 1-227
p,A9638 RS-422 Dual High Speed Differential Line Driver ..................................... 1-232
p,A9639A Dual Differential Line Receiver ................................................... 1-236
p,A9643 Dual TTL to MOS/CCD Driver ...................................................... 5-81
p,A9665 High Current/Voltage Darlington Driver .............................................. 3-65
p,A9666 High Current/Voltage Darlington Driver .............................................. 3-65
p,A9667 High Current/Voltage Darlington Driver .............................................. 3-65
p,A9668 High Current/Voltage Darlington Driver .............................................. 3-65
p,A5511 OA Dual Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-112
p,A75110A Dual Line Driver ............................................................... 1-1:12
p,A96172 RS-485/RS-422 Quad Differential Line Driver ...................................... 1-245
p,A96173 RS-485/RS-422 Quad Differential Line Receiver .................................... 1-255
p,A96174 RS-485/RS-422 Quad Differential Line Driver ...................................... 1-245
p,A96175 RS-485/RS-422 Quad Differential Line Receiver .................................... 1-255
p,A96176 RS-485/RS-422 Differential Bus Transceiver ....................................... 1-260
p,A96177 RS-485/RS-422 Differential Bus Repeater ......................................... 1-274

xviii

Additional Information on
Advanced Peripherals
AB-1 DP8408A/9A Application Hints .......................................... DRAM Management
AB-9 DP8408A/9A Fastest DRAM Access Mode ................................ DRAM Management
AN-302 The DP8400 Family of Memory Interface Circuits ........................ DRAM Management
AN-305 Precautions to Take when Driving Memories ............................ DRAM Management
AN-306 Expanding the Versatility of the DP8400 ................................ DRAM Management
AN-308 DP8400s in 64-Bit Expansion .......................................... DRAM Management
AN-309 Memory Supporting the DP8408A/09A to Various Microprocessors ........ DRAM Management
AN-387 DP8400/8419 Error Correcting Dynamic RAM Memory System for
the Series 32000 .......................................................... DRAM Management
AN-411 Determining the Speed of the Dynamic RAM Needed for No-Wait State
CPU Operation when Using the DP8418, 8419, 8428, 8429 ..................... DRAM Management
AN-413 Disk Interface Design Guide and User Manual ................................. Mass Storage
AN-414 Precautions for Disk Data Separator (PLL) Designs-How to Avoid
Typical Problems ............................................................... Mass Storage
AN-415 Designing with the DP8461 ................................................. Mass Storage
AN-416 Designing with the DP8465 ................................................. Mass Storage
AN-436 Dual Porting Using DP84XX Family DRAM Controller/Drivers .............. DRAM Management
DP5380 Asynchronous SCSI Interface ............................................... Mass Storage
DP8340 (IBM 3270) Serial Bi-Phase Transmitter/Encoder ............................ , LAN/Datacom
DP8341 (IBM 3270) Serial Bi-Phase Receiver/Decoder ............................... LAN/Datacom
DP8342 High-Speed Serial Transmitter/Encoder ..................................... LAN/Datacom
DP8343 High-Speed Serial Receiver/Decoder ....................................... LAN/Datacom
DP8344 Bi-Phase Communications Processor ....................................... LAN/Datacom
DP8390 IEEE 802.3 (EthernetlCheapernet) Network Interface Controller ................ LAN/Datacom
DP8391 IEEE 802.3 (EthernetlCheapernet) Serial Network Interface ................... LAN/Datacom
DP8392 IEEE 802.3 (EthernetlCheapernet) Coax Transceiver Interface ................. LAN/Datacom
DP8400-2 E2C2 Expandable Error Checker/Corrector .............................. Memory Support
DP8402A 32-Bit Parallel Error Detector and Corrector (EDAC) ....................... Memory Support
DP8408A 16k/64k Dynamic RAM Controller/Driver ............................. DRAM Management
DP8408A-2 16k/64k Dynamic RAM Controller/Driver ............................ DRAM Management
DP8409A 64k/256k Multi-Mode DynamiC RAM Controller/Driver .................. DRAM Management
DP8409A-2 64k/256k Multi-Mode Dynamic RAM Controller/Driver ................ DRAM Management
DP8417-70 64k/256k High Speed Dynamic RAM Controller/Driver (TRI-STATE) .... DRAM Management
DP8417-80 64k/256k High Speed Dynamic RAM Controller/Driver (TRI-STATE) .... DRAM Management
DP8418 64k/256k High Speed DynamiC
RAM Controller/Driver (32-Bit Systems) ..................................... DRAM Management
DP8418-70 64k/256k High Speed Dynamic
RAM Controller/Driver (32-Bit Systems) ..................................... DRAM Management
DP8418-80 64k/256k High Speed Dynamic
RAM Controller/Driver (32-Bit Systems) ..................................... DRAM Management
DP8419-70 64k/256k High Speed Dynamic
RAM Controller/Driver (16-Bit Systems) ..................................... DRAM Management
DP8419-80 64k/256k High Speed Dynamic
RAM Controller/Driver (16-Bit Systems) ..................................... DRAM Management
DP8419X-70 256k to 1 Megabit Dynamic RAM Controller/Driver Bridge ............ DRAM Management
DP8419X-80 256k to 1 Megabit Dynamic RAM Controller/Driver Bridge ............ DRAM Management
DP8420 1 Megabit Programmable Dynamic RAM Controller/Driver ................ DRAM Management
DP84221 Megabit Programmable Dynamic RAM Controller/Driver ................ DRAM Management
DP8428-70 1 Megabit High Speed Dynamic
RAM Controller/Driver (32-Bit Systems) ..................................... DRAM Management
DP8428-80 1 Megabit High Speed Dynamic
RAM Controller/Driver (32-Bit Systems) ..................................... DRAM Management
xix

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Additional Information on
Advanced Peripherals (Continued)
DP8429-70 1 Megabit High Speed Dynamic
RAM Controller/Driver (16-Bit Systems) ..................................... DRAM Management
DP8429-80 1 Megabit High Speed Dynamic
RAM Controller/Driver (16-Bit Systems) ..................................... DRAM Management
DP8451-3 Winchester Hard Disk Data Synchronizer (10 MBitiSec) ...................... Mass Storage
DP8451-4 Winchester Hard Disk Data Synchronizer (5 MBitiSec) ....................... Mass Storage
DP8455-3 Winchester Hard Disk Data Synchronizer (10 MBitiSec) ...................... Mass Storage
DP8455-4 Winchester Hard Disk Data Synchronizer (5 MBitiSec) ....................... Mass Storage
DP8459 All-Code Data Synchronizer ................................................ Mass Storage
DP8461-3 Winchester Hard Disk Data Separator (10 MBitiSec) ......................... Mass Storage
DP8461-4 Winchester Hard Disk Data Separator (5 MBitiSec) .......................... Mass Storage
DP8462-3 Winchester Hard Disk Data Synchronizer for 2, 7 Codes (10 MBitiSec) ......... Mass Storage
DP8462-4 Winchester Hard Disk Data Synchronizer for 2, 7 Codes (5 MBitiSec) .......... Mass Storage
DP8463B Winchester Hard Disk 2, 7 Code to NRZ Encoder/Decoder .................... Mass Storage
DP8464B-2 Winchester Hard Disk Pulse Detector ..................................... Mass Storage
DP8464B-3 Winchester Hard Disk Pulse Detector ..................................... Mass Storage
DP8465-3 Winchester Hard Disk Data Separator (10 MBitiSec) ......................... Mass Storage
DP8465-4 Winchester Hard Disk Data Separator (5 MBitiSec) .......................... Mass Storage
DP8466 Disk Data Controller ....................................................... Mass Storage
DP8466-12 Disk Data Controller (12 MBitiSec Data) .................................. Mass Storage
DP8466-20 Disk Data Controller (20 MBitiSec Data) .................................. Mass Storage
DP8466-25 Disk Data Controller (25 MBitiSec Data) .................................. Mass Storage
DP8472 Floppy Disk Controller Plus ................................................. Mass Storage
DP8473 Floppy Disk Controller Plus-AT .............................................. Mass Storage
DP84 74 Floppy Disk Controller Plus ................................................. Mass Storage
DP8500 Raster Graphics Processor ..................................................... Graphics
DP8506 Video Plane Controller ......................................................... Graphics
DP8510 BITBLT Processing Unit ........................................................ Graphics
DP8512 Video Clock Generator ......................................................... Graphics
DP8515 Video Shift Register ........................................................... Graphics
DP8516 Video Shift Register ........................................................... Graphics
DP8520 Video DRAM Controller ........................................................ Graphics
DP84300 Dynamic RAM Controller Programmable Refresh Timer ................. DRAM Management
DP84322 Dynamic RAM Controller Interface Circuit for 68000/008/010 CPU(s) ..... DRAM Management
DP84412 Dynamic RAM Controller Interface Circuit for 32008/016/032 CPU(s) ..... DRAM Management
DP84422 Dynamic RAM Controller Interface Circuit for 68000/008/010 CPU(s) ..... DRAM Management
DP84432 Dynamic RAM Controller Interface Circuit for 8086/88/186/188 CPU(s) ... DRAM Management
DP84512 Dynamic RAM Controller Interface Circuit for 32332 CPU ................ DRAM Management
DP84522 Dynamic RAM Controller Interface Circuit for 68020 CPU ................ DRAM Management
DP84532 Dynamic RAM Controller Interface Circuit for 80286 CPU ................ DRAM Management
DP8468B Disk Pulse Detector and Embedded Servo Detector .......................... Mass Storage
DP8469 Synchronizer/2,7 Endec ................................................... Mass Storage
DP8490 Enhanced Asynchronous SCSI Interface ..................................... Mass Storage
Dynamic RAM Controller Pushes System Speed to 10 MHz-and Beyond .......... DRAM Management
Effortless Error Management ................................................. DRAM Management
Error Correction the Hard Way ................................................ DRAM Management
MM74HC942 300 Baud Modem .................................................... LAN/Datacom
MM74HC943 300 Baud Modem .................................................... LAN/Datacom
Simplification of 2-Bit Error Correction ......................................... DRAM Management
Single-Chip Controllers Cover all RAMs from 16k to 256k ........................ DRAM Management

xx

Section 1
Transmission Line
Drivers/Receivers

Section 1 Contents
, Transmission Line Drivers and Receivers-Introduction .................................
Transmission Line Drivers and Receivers-Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS1488 Quad Line Driver..... ................................ ......................
OS14C88/0S14C89AQuad CMOS Line Driver/Receiver................................
OS1489/0S1489A Quad Line Receiver ...............................................
OS26C31C CMOS Quad TRI-STATE Differential Line Driver.............................
OS26F31 C/OS26F31 M Quad High Speed Differential Line Driver. . . . . . . . . . . . . . . . . . . . . . . . .
OS26LS31 C/OS26LS31 M Quad High Speed Differential Line Driver ......................
OS26C32C CMOS Quad Differential Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS26F32C/OS26F32M Quad Differential Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS26LS32C/OS26LS32M/OS26LS32AC/OS26LS33C/OS26LS33M/OS26LS33AC Quad
Differential Line Receivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS34C86 Quad CMOS Differential Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS35F86/0S34F86 RS-422/RS-423 Quad Line Receiver with TRI-STATE Outputs.........
OS3486 Quad RS-422/RS-423 Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS34C87 CMOS Quad TRI-STATE Differential Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS35F87/0S34F87 RS-422 Quad Line Driver with TRI-STATE Outputs...................
OS3587/0S3487 Quad TR I-STATE Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS1603/0S3603 TRI-STATE Dual Receivers..........................................
OS1650/0S1652/0S3650/0S3652 Quad Differential Line Receivers.....................
OS1691A/OS3691 RS-422/RS-423 Line Drivers with TRI-STATE Outputs.................
OS1692/0S3692 TRI-STATE Differential Line Drivers...................................
OS16F95/0S36F95 RS-485/RS-422 Differential Bus Transceiver........................
OS3695/0S3695T /OS3696/0S3696T /OS3697 /OS3698 Multipoint RS-485/RS-422
Transceivers/Repeaters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS551 07 /OS751 07 /OS551 08/0S751 08/0S75208 Dual Line Receiver. . . . . . . . . . . . . . . . . . .
OS55110A/p,A55110A/OS7511 OA/p,A75110A Dual Line Drivers. . . . . . . . . . . . . . . . . . . . . . . . .
OS55113/0S75113 Dual TRI-STATE Differential Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
OS55114/0S75114 Dual Differential Line Drivers.......................................
OS55115/0S75115 Dual Differential Line Receiver.....................................
OS55121/0S75121 Dual Line Drivers.................................................
OS75123 Dual Line Driver...........................................................
OS75124 Triple Line Receiver........................................................
OS75125/0S75127 Seven-Channel Line Receivers.....................................
OS75128/0S75129 Eight-Channel Line Receivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS75150 Dual Line Driver...........................................................
OS75154 Quad Line Receiver........................................................
OS75176A/OS75176AT Multipoint RS-485/RS-422 Transceivers........................
OS7820/0S8820 Dual Line Receiver .................................................
OS7820A/OS8820A Dual Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
OS78C20/0S88C20 Dual CMOS Compatible Differential Line Receiver. . . . . . . . . . . . . . . . . . . .
OS7830/0S8830 Dual Differential Line Driver..........................................
OS7831/0S8831/0S7832/0S8832 Dual TRI-STATE Line Driver.........................
OS78C120/0S88C120 Dual CMOS Compatible Differential Line Receiver.................
OS78LS120/0S88LS120 Dual Differential Line Receiver (Noise Filtering and Fail Safe). . . . ..
OS8921 /OS8921 A Differential Line Driver and Receiver Pair. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS8922/0S8922A/OS8923/0S8923A TRI-STATE RS-422 Dual Differential Line Driver and
Receiver Pairs ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1-2

1-4
1-6
1-13
1-17
1-23
1-27
1-31
1-34
1-37
1-40
1-44
1-47
1-50
1-54
1-58
1-62
1-66
1-69
1-73
1-81
1-87
1-92
1-98
1-105
1-112
1-117
1-124
1-129
1-134
1-136
1-138
1-141
1-145
1-149
1-153
1-158
1-163
1-167
1-172
1-176
1-180
1-187
1-195
1-202
1-207

Section 1 Contents (Continued)
DS8924 Quad TR I-STATE Differential Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
p.A9622/DS9622 Dual Line Receiver .................................................
p.A9627/DS9627 Dual Line Receiver .................................................
DS9636A/ p.A9636A RS-423 Dual Programmable Slew Rate Line Driver. . . . . . . . . . . . . . . . . ..
DS9637 A/ p.A9637 A Dual Differential Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS9638/ p.A9638 RS-422 Dual High Speed Differential Line Driver. . . . . . . . . . . . . . . . . . . . . . ..
DS9639A/ p.A9639A Dual Differential Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DS96F172/DS96F174 RS-485/RS-422 Quad Differential Drivers.........................
DS96172/p.A96172/DS96174/p.A96174 RS-485/RS-422 Quad Differential Line Drivers....
DS96F173/DS96F175 RS-485/RS-422 Quad Differential Receivers. . . . . . . . . . . . . . . . . . . . . .
DS96173/ p.A96173/DS96175/ p.A96175 RS-485/RS-422 Quad Differential Line Receivers..
DS96176/ p.A96176 RS-485/RS-422 Differential Bus Transceiver ........................
DS96F177 /DS96F178 RS-485/RS-422 Differential Bus Repeaters .......................
DS96177/p.A96177 RS-485/RS-422 Differential Bus Repeater...........................
MM78C29/MM88C29 Quad Single-Ended Line Driver...................................
MM78C30/MM88C30 Quad Differential Line Driver......... ............................
AN-22 Integrated Circuits for Digital Data Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AN-1 08 Transmission Line Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-214 Transmission Line Drivers and Receivers for EIA Standards RS-422 and RS-423 . . ..
AN-216 Summary of Electrical Characteristics of Some Well Known Digital Interface
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AN-409 Transceivers and Repeaters Meeting the EIA RS-485 Interface Standard...........
AN-438 Low Power RS-232C Driver and Receiver in CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AN-457 High Speed, Low Skew RS-422 Drivers and Receivers Solve Critical System Timing
Problems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
p.A9614/DS9614 Dual Differential Line Driver (See DS55114 Datasheet)
p.A9615/DS9615 Dual Differential Line Receiver (See DS55115 Datasheet)
DS551 07 A Dual Line Receiver (See DS551 07 Datasheet)

1·3

1-213
1-216
1-219
1-223
1-227
1-232
1-236
1-240
1-245
1-250
1-255
1-260
1-267
1-274
1-281
1-281
1-287
1-301
1-307
1-317
1-330
1-337
1-341

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::::i
c
o
'iii
o

'Eo
c

~
I-

to 4000 feet (up to 1 kBaud). RS-423 also requires high
impedance driver outputs with power off so as not to load
the transmission line.

The common purpose of transmission line drivers and receivers is to transmit data quickly and reliably through a
variety of environments over electrically long distances.
This task is complicated by the fact that externally introduced noise and ground shifts can severely degrade the
data.

Differential Data Transmission
When transmitting at very high data rates, over long distances and through noisy environments, single-ended transmission is often inadequate. In these applications, differential data transmission offers superior performance. Differential transmission nullifies the effects of ground shifts and
noise signals which appear as common mode voltages on
the transmission line.

The connection between two elements in a system should
be considered a transmission line if the transmitted signal
takes longer than twice its rise or fall time to travel from the
driver to the receiver.

Single-Ended Data Transmission
In data processing systems today there are two basic
means of communicating between components. One method is single-ended, which uses only one signal line for data
transmission, and the other is differential, which uses two
signal lines.
The Electronics Industry Association (EIA) has developed
several standards to simplify the interface in data communications systems.

RS-422
RS-422 was defined by the EIA for this purpose and allows
data rates up to 10 MBaud (up to 40 ft.) and line lengths up
to 4000 feet (up to 100 kBaud).
Drivers designed to meet this standard are well suited for
party-line type applications where only one driver is connected to, and transmits on, a bus and up to 10 receivers
can receive the data. While a party-line type of application
has many uses, RS-422 devices cannot be used to construct a truly multipoint bus. A multipoint bus consists of
multiple drivers and receivers connected to a single bus,
and anyone of them can transmit or receive data.

RS-232
The first of these, RS-232, was introduced in 1962 and has
been widely used throughout the industry. RS-232 was developed for single-ended data transmission at relatively
slow data rates (20 kBaud) over short distances (up to
50 ft.).

RS-485
To meet the need for truly multipoint communications, the
EIA established RS-485 in 1983. RS-485 meets all the requirements of RS-422, but in addition, this new standard
allows up to 32 drivers and 32 receivers to be connected to
a single bus-thus allowing a truly multipoint bus to be constructed.

RS-423
With the need to transmit data faster and over longer distances, RS-423, a newer standard for single-ended applications, was established. RS-423 extends the maximum data
rate to 100 kBaud (up to 30 ft.) and the maximum distance

RS-232C Application

~

RS2l2C_\
-INTERFACE

DA~~

~)

DATA
DUT

~
TL/XX/0094-1

EIA RS-423 Application

DA~~

r--IN:E~:!CE~

~

~)

DATA
DUT

~>---4")~

TL/XX/0094-2

1-4

Differential Data Transmission

(Continued)
EIA RS-422 Application

I-

..........
DA~:~

>

»

RS422
INTERFACE

-:j

»-

O",ONA~ctJ

DATA

OUT

»

»

-

':"

TLlXX/OO94-3

• Drivers can withstand bus contention and bus faults

The key features of RS-485:
• Implements a truly multipoint bus consisting of up to 32
drivers and 32 receivers
• An extended common· mode range for both drivers and
receivers in TRI·STATE and with power off (-7V to
+12V)

National Semiconductor produces a variety of drivers, receivers, and transceivers for these four very popular transmission standards and numerous other data transmission
requirements.
Shown below is a table that highlights key aspects of the
EIA Standards. More detailed comparisons can be found in
the various application notes in Section 1.

RS-485 Application

/.\ /;)(
IV)

RT
120

~

"
" fA
//

D-Driver
R-

Receiver
Transceiver

T

V
Specification

\~
~

//

//

OHMS

T-

/.\ /.\
r"

OHMS

"

)( 1.\

RT
120

//

1

'\/
RS-423

RS-232C

TLlXX/OO94-4

RS-422

RS-485

Mode of Operation

Single· Ended

Single·Ended

Differential

Differential

Number of Drivers and Receivers
Allowed on One Line

1 Driver,
1 Receiver

1 Driver,
10 Receivers

1 Driver,
10 Receivers

32 Drivers,
32 Receivers

Maximum Cable Length

50 feet

4000 feet

4000 feet

4000 feet

Maximum Data Rate

20 kb/s

100 kb/s

10 Mb/s

10 Mb/s

Driver Output Maximum Voltage

±25V

±6V

- 0.25V to + 6V

-7Vto +12V

Loaded

±5V

±3.6V

±2V

±1.5V

Unloaded

±15V

±6V

±5V

±5V

3 kn to 7 kn

450n min

100n

54n

Driver Output Signal Level

I
I

Driver Load Impedance
Power On

----

Power Off

VMAX/ 300n

±100 }J-A

Slew Rate

30 V/}J-s max

Controls Provided

Receiver Input Voltage Range

±15V

±12V

Maximum Driver Output Current
(High Impedance State)

I
I

----

---±100}J-A

----7Vto +7V

±100 }J-A
±100 }J-A

----7Vto +12V

Receiver Input Sensitivity

±3V

±200 mV

±200 mV

±200 mV

Receiver Input Resistance

3 kn to 7 kn

4 kn min

4 kn min

12 kn min

1-5

10k
4k

g

Line length is a function of data rate (baud) and slew rate. The recommended safe operating area
(line length vs baud rate) is shown below for 24 AWG wire. It assumes that a differential line
receiver is used which is referenced at the driver ground. Also, it assumes that the driver slew
rate is between 0.1 to 0.3 times the reciprocal of the baud rate (minimum unit interval). Otherwise, line lengths greater than 50 feet are not recommended. The exception to line length is the
360 I/O coaxial interface. The coaxial provides improved grounding and eliminates crosstalk.

.-:z:

~

1k

RECOMMENDED "
OPERATING
AREA

c:I

~
~

:::;

~

100

"

10
100

1k

100k

10k

, DATA MODULATION (BAUD RATE)
TL/XX/OO99-1

RS-423
UNBALANCED DRIVERS

Standard

a,

'Device Number
Circuits
Per
Military
Commercial
O°Cto + 70°C - 55°C to + 125°C Package

RS-232

OS1488

RS-232

OS14C88

RS-232

OS75150

RS-423

OS3691

RS-423

OS9636ACI
p.A9636AC

MIL-188-114 OS3692
360 I/O
360 I/O

OS75121

4

Power
Supplies
(V)

Open-CollectorI
Output
Party-Line Slew Rate
Current
Open Emitter
Application Control
TRI-STATE
(mA)

±9 or ±15

10S/C

Output
Voltage
(V)

Propagation
Delay
(ns)

±6

±60r ±9

200

1-13

60

1-149
1-81

±9 or ±15

Internal

±6

±7 or ±11

2

±12

10S/C

±10

±5

OS1691A

4

+5 or ±5

CEXT

±20

±2

200

OS9636AMI
p.A9636AM

2

±12

Yes

±60

±6

1400

OS1692

4

+50r ±5

TRI-STATE

Yes

CEXT

±20

±2

200

OS55121

2

5

Emitter

Yes

-100

2.4

TRI-STATE

Yes

1-223
± 1OV Common-Mode
Range

1-87

10

50n Coax Oriver

1-134

50n Coax Oriver (IBM) 1-136

OS75123

2

5

Emitter

Yes

2.4

10

OS75450

2

5

Emitter and
Collector

Yes

300

0.7

20

2

5

Collector

Yes

300

0.7

18

OS55451

Page
No.

1-17

-100

OS75451

Comments

3-41
3-41

OS75452

OS55452

2

5

Collector

Yes

300

0.7

26

3-41

OS75453

OS55453

2

5

Collector

Yes

300

0.7

18

3-41

OS75454

OS55454

2

5

Collector

Yes

300

0.7

27

3-41

OS75110Al
p.A75110A

OS55110Al
p.A55110A

2

±5

Constant
Current

Yes

12

15

1-112

UNBALANCED RECEIVERS
Device Number

Input
Range
(V)

Threshold Propagation
Delay
Sensitivity
(V)
(ns)

Page
No.

Standard

Commercial
O·Cto +70·C

RS-232

OS1489

4

5

CEXT

250

+25

3

30

RS-232

OS1489A

4

5

CEXT

1150

±25

3

30

RS-232

OS14C89

4

5

±25

3

RS-232

OS75154

4

5 or 15

CEXT

800

±25

3

22

1-153

2

±12

Strobed

±3

250

1-219

4

5

TRI-STATE
±0.2

22

1-40

RS-232

.:...

Circuits
Power
Strobed
Response Hysteresis
Per
Supplies
or
Military
Control
(mV)
Package
(V)
TRI-STATE
-55·C to + 125·C

OS9627/ p.A9627

Comments

1-23
Preferential in
Applications to OS1489

1-23
1-17

RS-423

OS26C32

RS-423

OS26F32C

OS26F32M

4

5

TRI-STATE

30

±7

RS-423

OS26LS32C

OS26LS32M

4

5

TRI-STATE

100

±7

±0.2

17

RS-423

OS26LS32AC

4

5

TRI-STATE

100

±7

±0.2

23

RS-423

OS3486

4

5

TRI-STATE

100

±15

±0.2

25

1-54

RS-423

OS34C86

4

5

TRI-STATE

RS-423

OS34F86

OS35F86

4

5

TRI-STATE

±7

±0.2

22

1-50

RS-423

OS88C20

OS78C20

2

5

Strobed

CEXT

50

±25

±0.2

50

RS-423

OS88C120

OS78C120

2

5

Strobed

CEXT

50

±25

±0.2

50

Fail-Safe

1-187

RS-423

OS88LS120

OS78LS120

2

5 to 15

Strobed

CEXT

50

±25

±0.2

50

Fail-Safe

1-195

RS-423

OS9637AC/
,..,A9637AC

OS9637AM/
p.A9637AM

2

5

RS-423

OS9639AC/
ILA9639AC

2

5

1-37
1-44
Fail-Safe

1-44
1-47
1-172

1-227
1-236

RS-423

OS96F173C

OS96F173M

4

5

TRI-STATE

50

+12/-7

RS-423

OS96173C/
ILA96173C

OS96173M/
ILA96173M

4

5

TRI-STATE

50

+12/-7

±0.2

22

±0.2

25

1-250
1-255

RS-423

OS96F175C

OS96F175M

4

5

TRI-STATE

50

+12/-7

±0.2

22

RS-423

OS96175C/
p.A96175C

OS96175M/
ILA96175M

4

5

TRI-STATE

50

+12/-7

±0.2

25

360 I/O

OS75124

3

5

Strobed

400

20

50n Coax. Receiver (18M)

1-138

OS75125

7

5

7
-2/7

0.8 to 2

360 I/O

0.7 to 1.7

16

IBM Coax. Receiver

1-141

360 I/O

OS75127

7

5

16

IBM Coax. Receiver

1-141

OS75128
OS75129

8

Strobed

0.7 to 1.7

1-145

0.7 to 1.7

16
16

IBM Coax. Receiver

8

5
5

-217
-217
-217

0.7 to 1.7

360 I/O
360 I/O

IBM Coax. Receiver

1-145

4

5

TRI-STATE

200

±15

±0.5

17

4

5

TRI-STATE

200

±15

±0.5

23

Fail-Safe

1-44

±15

±0.5

75

OS26LS33C

OS26LS33M

OS26LS33AC

-

--

OS9615/,..,A9615

2

5

OS9622/,..,A9622

2

+5
-10

Strobed

Yes
Strobed
--

±10

50

1-250
1-255

1-44
1-129
1-216

BALANCED DIFFERENTIAL TRANSMISSION LINE DRIVERS AND RECEIVERS
10k

4k

The balanced or differential scheme of data transmission is preferred for applications incorporating high data rates and long transmission lines in the presence of high common-mode noise.
Induced signals appear as common-mode levels and are rejected by the differential line receiver.

g
:::

lk

le:!

...-'~

5

100
-40
10
10k

1001t

1M

10M

DATA MODULATION (BAUD RATE)
TL/XX/OO99-2

RS-422

Co

BALANCED DIFFERENTIAL TRANSMISSION LINE DRIVERS AND RECEIVERS

(Continued)

BALANCED DRIVERS
Device Number
Standard

cO

Commercial
O°C to + 70°C

Circuits
Per
Military
-55°C to + 125°C Package

Power
Supplies
(V)

VOL (V) Propagation
Party-Line
VOH (V)
Delay
Open Collector Application TRI-STATE IOH (rnA) IOl(mA)
(V)
(ns)

Comments

Page
No.

RS·422

DS26C31

RS-422

DS26F31C

DS26F31M

4

5

Yes

Yes

2.5/-20

0.5/20

15

1·31

RS-422

DS26LS31C

DS26LS31M

4

5

Yes

Yes

2.5/-20

0.5/20

15

1-34

RS-422

DS3487

DS3587

4

5

Yes

Yes

2.0/-50

0.5/48

15

RS-422

DS34C87

RS-422

DS34F87

DS35F87

4

5

Yes

Yes

2.5/-20

0.5/48

15

RS-422

DS3691

DS1691A

2

+5 or ±5

Yes

Yes

2/-20

-2/20

200

RS-422

DS8921, 21A

1

5

No

No

2.5/-20

0.5/20

12

Transceiver

1-202

RS-422

DS8922
DS8922A

2

5

Yes

Yes

2.5/-20

0.5/20

12

Dual Transceiver with
Driver/Receiver Pair
Disable

1-207

RS-422

DS8923
DS8923A

2

5

RS-422

DS9638C/

2

5

1

5

Yes

Yes

15

1

5

Yes

Yes

16

5

Yes

Yes

15

Transceiver with Une
Fault Reporting

ILA9638C

1·27

1-66
1·58

DS9638M/
ILA9638M

Yes

Yes

2.5/-20

0.5/20

12

2.0/-40

0.5/40

20

1-62
1-81

Dual Transceiver with
Separate Driver and
1-207
Receiver Disables
1-232

RS-485

DS3695

RS-485

DS36F95

RS-485

DS3696

1

RS-485

DS3697

1

5

Yes

Yes

15

Repeater

1-98

RS-485

DS3698

1

5

Yes

Yes

15

Repeater with Une
Fault Reporting

1-98

RS-485

DS75176A

RS-485

DS96F172C

RS-485

DS96172/

DS16F95

DS96F172M

1

5

Yes

Yes

4

5

Yes

Yes

16

4

5

Yes

Yes

20

4

5

Yes

Yes

16

4

5

Yes

Yes

20

1

5

Yes

Yes

20

1

5

Yes

Yes

1

5

Yes

Yes

Transceiver

Transceiver

DS96F174C

RS-485

DS96174/

DS96F174M

DS96176/

1-240
1-245
Transceiver

ILA96176

RS-485

DS96F177C

RS-485

DS96177/
ILA96177

DS96F177M

Repeater
20

1-158

1-245

ILA96174

RS-485

1-98

1-240

ILA96172

RS-485

1-98
1-92

Repeater

1-260
1-267
1-274

I

BALANCED DRIVERS
Device Number
Circuits
Power
Strobed
Common-Mode Threshold Propagation
Response Hysteresis
Standard Commercial
Range
Sensitivity
Supplies
or
Per
Delay
Military
(mV)
Control
(V)
TRI-STATE
(V)
(V)
Package
(ns)
QOC to +7QoC -55°C to + 125°C
RS-485

OS96F178C
OS8830
OS8831
OS8832

OS96F178M
OS7830
OS7831
OS7832

1
2
2
2

5
5
5
5

OS8924
OS75113
OS75114

OS55113
OS55114

4
2
2
2

5
5
5

2
2

5 or 15
5 or 15

OS9614/
.uA9614
MM88C29
_ MM88C30

.....
a

MM78C29
MM78C30

Optional
Optional

.Yes
No
Yes
Yes

Yes
No
Yes
Yes

Yes
Yes

Yes
Yes

Comments
Repeater

Page
No.
1-267
1-176
1-180

1.8/-40
1.8/-40
1.8/-40

0.5/40
0.5/40
0.5/40

10
10
10

2.0/-48
2.0/-40
2.0/-40

0.5/48
0.4/40
0.4/40

12
13
15

OS8831 without Vee
1-180
ClampOiode
1-213
1-117
1-124
See 0555114
1-124

2.9/-57
2.9/-57

0.4/11
0.4/11

100
100

1-281
1-281

5

BALANCED RECEIVERS
Device Number
Circuits Power
Strobed
Common-Mode Threshold Propagation
Response Hysteresis
Standard Commercial
Per
Supplies
Delay
Range
Sensitivity
or
Military
(mV)
Control
(V)
(V)
(ns)
TRI-STATE
(V)
ooe to + 70°C ~ 55°e to + 125°C Package

Comments

Page
No.

RS-422

OS26C32

RS-422

OS26F32C

OS26F32M

4

5

TRI-STATE

30

±7

±0.2

22

RS-422

OS26LS32C

OS26LS32M

4

5

TRI-STATE

100

±7

±200

17

RS-422

OS26LS32AC

4

5

TRI-STATE

100

±7

±200

17

RS-422

OS3486

4

5

TRI-STATE

80

±10

±200

17

1-54

RS-422

OS34C86

4

5

TRI-STATE

RS-422

OS34F86

OS35F86

4

5

TRI-STATE

±7

±0.2

22

1-50

RS-422

OS88C20

OS78C20

2

5 to 15

Strobed

Yes

50

±10

±200

60

Fail-Safe CMOS Compatible 1-172

RS-422

OS88C120

OS78C120

2

5 to 15

Strobed

Yes

50

±10

±200

60

1-187

RS-422

OS88LS120

OS78LS120

2

5

Strobed

Yes

50

±10

±200

50

RS-422

OS8921

1

5

50

±7

±200

RS-422

OS8921A

1

5

50

±7

±200

RS-422

OS8922

2

5

TRI-STATE

50

±7

±200

RS-422

OS8922A

2

5

TRI-STATE

50

±7

±200

RS-422

OS8923

2

5

TRI-STATE

50

±7

±200

RS-422

OS8923A

2

5

TRI-STATE

50

±7

±200

RS-422

OS9637ACI
,...A9637AC

2

5

±7

±0.2

25

RS-422

OS9639A1
,...A9639A

2

5

±7

±0.2

85

4

1-37

TRI-STATE

1-40
1-44
Fail-Safe

1-44
1-47

1-195
1-202
I

OS9637AMI
,...A9637AM

Low Skew

1-202
1-207

Low Skew

1-207
1-207

Low Skew

1-207
1-227
236
1-

1

I

- -

------

i

BALANCED RECEIVERS Continued
Device Number
Standard
RS-485

OS3695

RS-485

OS36F95

RS-485

OS3696

.....

Military
- 5SOC to + 125°C
OS16F95

Circuits
Per
Package

Power
Supplies
(V)

Strobed
or
TRI-STATE

1

5

1

5

1

5

Hysteresis
(mY)

Common-Mode
Range
(V)

Threshold
Sensitivity
(V)

Propagation
Delay
(ns)

TRI-STATE

70

+12/-7

±200

22

Transceiver

1-98

TRI-STATE

50

+12/-7

±0.2

16

Transceiver

1-92

TRI-STATE

70

+12/-7

±200

22

Transceiver
with Line
Fault
Reporting

Response
Control

Comments

RS-485

OS3697

1

5

TRI-STATE

70

+12/-7

±200

22

Repeater

RS-485

OS3698

1

5

TRI-STATE

70

+12/-7

±200

22

Repeater
with Line
Fault
Reporting

RS-485

OS75176A

RS-485

OS96F173C

RS-485

OS96173/
,...A96173

RS-485

OS96F175C

RS-485

OS96175/
,...A96175

RS-485

OS96176

.....

I\)

Commercial
O°Cto + 70°C

OS96F173M

OS96F175M

1

5

TRI-STATE

70

+12/-7

±200

4

5

TRI-STATE

50

+12/-7

±0.2

22

4

5

TRI-STATE

50

+12/-7

±0.2

25

4

5

TRI-STATE

50

+12/-7

±0.2

22

4

5

TRI-STATE

50

+12/-7

±0.2

25

50

Transceiver

Page
No.

1-98
1-98

1-98
1-158
1-250
1-255
1-250
1-255

1

5

TRI-STATE

+12/-7

±0.2

25

OS3603

OS1603

2

±5

TRI-STATE

±3

±25

17

1-69

OS3650

OS1650

4

±5

TRI-STATE

±3

±25

10

1-73

OS3652

OS1652

4

±5

Strobed

±3

±25

10

1-73

OS8820

OS7820

2

5

Strobed

Yes

±15

±1000

40

1-163

OS8820A

OS7820A

2

5

Strobed

Yes

±15

±1000

30

1-167

OS75107

OS55107

2

±5

Strobed

±3

±25

17

1-205

OS75108

OS55108

2

±5

Strobed

±3

±25

17

1-105

OS75115

OS55115

2

5

Strobed

Yes

±15

±500

20

1-129

Strobed

±3

±10

17

Yes

±15

±0.5

75

2

±5

OS9615/
,...A9615

2

5

OS9622/
,...A9622

2

+5/-10

OS75208

-- -

Strobed

±10

50

Transceiver

1-260

1-105
See
OS55115

1-129
1-216

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.......

~National

0l:Io

Q)
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~ Semiconductor
DS1488 Quad Line Driver
General Description

Features

The OS1488 is a quad line driver which converts standard
TTL input logic levels through one stage of inversion to output levels which meet EIA Standard No. RS-232C and
CCITT Recommendation V.24.

•
•
•
•
•

Current limited output
± 10 rnA typ
Power-off source impedance
300n min
Simple slew rate control with external capacitor
Flexible operating supply range
Inputs are TTL/LS compatible

Schematic and Connection Diagrams
1/4 Circuit

Dual-In-Line Package

v+

r-----~~------~~~~---ov+

INPUT

09
INPUT

R3
R8

....---+--+-'VV\.........o OUTPUT
07

08

v-

GNO
TL/F/5776-2

R7

Top View

~--~-----4----~~~~---ov­

Order Number DS1488J, DS1488M or DS1488N
See NS Package Number J14A, M14A or N14A

TLlF/5776-1

Typical Applications
RS-232C Data Transmission

1/40S14881
OS1488A

1/40S1488

TIL/OTl
--~-,

---t

):)0-

--'1-_"

TIL/On

---::t'--a..-t--,_r--

INTERFACE DATA
TERMINAL EnUIPMENT

TIL/OTl
__ .r--,

t,)oo - -

- -.f

--"1.._ "

1/40S14881
OS1488A

INTERCONNECTING
CABLE
TIll on

'-"1--... - ,_r--

--<:f

SIGNAL GROUND

MODEM
TL/F/5776-3

'Optional for noise filtering

1-13

III

co
co
~

'9""

en
c

Absolute Maximum Ratings

(Note 1)

Supply Voltage
V+
V-

Maximum Power Dissipation· at 25°C
Cavity Package
1364 mW
Molded DIP Package
1280 mW
974mW
SO Package
Lead Temperature (Soldering, 4 sec.)
260°C
'Derate cavity package 9.1 mW/,C above 25'C; derate molded DIP package 10.2 mW/,C above 25'C; derate SO package 7.8 mW/,C above 25'C.

±15V
-15V

Input Voltage (VIN)

~

-15V

VIN

~

7.0V
±15V

Output Voltage
Operating Temperature Range

O°Cto +75°C

Electrical Characteristics (Notes 2 and 3) Vee+ =
Symbol

Parameter

IlL

Logical "0" Input Current

IIH

Logical "1" Input Current

VOH

High Level Output Voltage

= OV
VIN = +5.0V
RIL = 3.0 k!l,
VIN = 0.8V

=
V+ =
V+ =
V+ =

V+

RL = 3.0 k!l,
VIN = 1.9V

los+

High Level Output
Short-Circuit Current

VOUT

= OV, VIN = 0.8V

los-

Low Level Output
Short-Circuit Current

VOUT

= OV, VIN = 1.9V

ROUT

Output Resistance

V+

lee+

Positive Supply Current
(Output Open)

VIN

VIN

VIN

VIN

Pd

Power Dissipation

= - 9V unless otherwise specified
Min

VIN

Low Level Output Voltage

Negative Supply Current
(Output Open)

9V, Vee-

Conditions

VOL

lee-

- 65°C to + 150°C

Storage Temperature Range

If Military! Aerospace specified devices are required,
contact the National Semiconductor Sales Office!
Distributors for availability and specifications.

V+
V+

Switching Characteristics

= -9.0V
13.2V, V- = -13.2V
9.0V, V- = -9.0V
13.2V, V- = -13.2V
9.0V, V-

= V- = OV, VOUT = ±2V
V+ = 9.0V, V- = -9.0V
= 1.9V
V+ = 12V, V- = -12V
V+ = 15V, V- = -15V
V+ = 9.0V, V- = -9.0V
= 0.8V
V+ = 12V, V- = -12V
V+ = 15V, V- = -15V
V+ = 9.0V, V- = -9.0V
= 1.9V
V+ = 12V, V- = -12V
V+ = 15V, V- = -15V
V+ = 9.0V, V- = -9.0V
= 0.8V
V+ = 12V, V- = -12V
V+ = 15V, V- = -15V
= 9.0V, V- = -9.0V
= 12V, V- = -12V
(Vee

Typ

Max

Units

-1.0

-1.3

mA

0.005

10.0

p,A

6.0

7.0

9.0

10.5

V

-6.0

-6.8

V

-9.0

-10.5

V

-6.0

-10.0

-12.0

mA

6.0

10.0

12.0

mA

15.0

20.0

mA
mA

V

!l

300

19.0

25.0

25.0

34.0

mA

4.5

6.0

mA

5.5

7.0

mA

8.0

12.0

mA

-13.0

-17.0

mA

-18.0

-23.0

mA

-25.0

-34.0

mA

-0.001

-0.015

mA

-0.001

-0.015

mA

-0.01

-2.5

mA

252

333

mW

444

576

mW

Units

= 9V, VEE = -9V, TA = 25°C)
Typ

Max

tpd1

Propagation Delay to a Logical "1"

RL

= 3.0 k!l, CL = 15 pF, TA = 25°C

230

350

ns

tpdO

Propagation Delay to a Logical "0"

RL

= 3.0 k!l, CL = 15 pF, TA = 25°C

70

175

ns

tr

Rise Time

RL

= 3.0 k!l, CL = 15 pF, TA = 25°C
RL = 3.0 k!l, CL = 15 pF, TA = 25°C

75

100

ns

Symbol

Conditions

Parameter

Min

40
75
ns
Fall Time
tf
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified min/max limits apply across the O'C to + 75'C temperature range for the DS1488.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.

1-14

Applications
By connecting a capacitor to each driver output the slew
rate can be controlled utilizing the output current limiting
characteristics of the OS1488. For a set slew rate the appropriate capacitor value may be calculated using the following relationship

RS-232C specifies that the output slew rate must not exceed 30V per microsecond. Using the worst case output
short circuit current of 12 mA in the above equation, calculations result in a required capacitor of 400 pF connected to
each output.
See Typical Performance Characteristics.

C = Isc (~T/~V)
where C is the required capacitor, Isc is the short circuit
current value, and ~ VI ~ T is the slew rate.

Typical Applications

(Continued)

DTL/TTL-to-MOS Translator

DTL/TTL-to-HTL Translator

+12V

.12V

OTL/TTL
INPUT

OTL/TTL
INPUT

-12V

-12V

-12V

TLIF/5776-4

TL/F/5776-5

DTL/TTL-to-RTL Translator
+12V

OTl/TTL

RTl OUTPUT
JO-~. .----tl~-{) -O.7V TO +J.7V

INPUT

-12V

II

+J.OV
TL/F/5776-6

AC Load Circuit and Switching Time Waveforms

,. --4 '" t :

)()---.l~----.l~-O VOUT

,~

TL/F/5776-7

'CL includes probe and jig capacitance.

if_~ ' ' 1r
~ .~

t, and tf are measured between 10%
and 90% of the output waveform.

1-15

~, ~

TL/F/5776-B

co
co

~
,....

U)

Typical Performance Characteristics T A = + 25°C unless otherwise noted

c

12.0
9.0

LoJ

3.0 I-Vi=iEE=ltsVI

~
<.!)

~
a
>

I~

0I~

a

0
>

6.0

I-- VCC=VEE=lt9VI

v~v

-3.0 1--1

o

3.0

r- ..........

0

'l-i-

I----

~

·2

f- l V- t - Vee= +9V

B

o f - f-~- I - -3.0 I---- t- 0.8V - f-V EE = -9V -=

U

-6.0

.-

0::

I 1-=1

Ii:

I

VI

I

r--~

6.0

3k.!l

f-

-9.0
-12.0

..........

9.0

0

-6.0

12

Vcc- VEE = t 12V

In'
::i
a

~

I

U

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

_VI

po

_k j....-- lOS

-9.0

j....-- ~

-12 -55
-75

-so

-25

VIN' INPUT VOLTAGE (VOLTS)

0

25

SO

75 100 125

T. TEMPERATURE (OC)
TL/F/5776-9

TL/F/5776-10

FIGURE 1. Transfer Characteristics
vs Power Supply Voltage

FIGURE 2. Short-Circuit Output
Current vs Temperature

lK

~
~
a

<100

~

9

I-

6

0::
0::
~

(.)

LoJ

~
0::

.5
z
LoJ

~

I~

1=

10 VI2IVo

F

~

a

E.~~L

-'
VI

11111111

1
1

10

_0

II

100

lK

10K

18
15
12

-

.1
1\ ,

\

,

\ \

~
......

, _\

\. \

\

0
\ 1\
-3
\ \
-6
_\
-9 1.9Y
10
-12
-15 •
Yo -=O.BY
-18
-16 -12 -8 -4

,

11:\

,

'-cAr""":L

)

\
0

4

8

12 16

Yo. OUTPUT VOLTAGE (V)

CL• CAPACITANCE (pF)
TLlF/5776-11

TL/F/5776-12

FIGURE 3. Output Slew Rate vs
Load Capacitance

FIGURE 4. Output Voltage and
Current-Limiting Characteristics

1-16

c
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~National

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CD

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DS14C88/DS14C89A Quad CMOS Line Driver/Receiver

(J)
.....
.I::loo
oCD

CD

General Description

Features

The DS14C88 and DS14C89A, pin-for-pin replacements for
the DS1488/MC1488 and the DS1489/MC1489, are line
drivers/receivers designed to interface data terminal equipment (DTE) with data communications equipment (DCE).
These devices translate standard TTL or CMOS logic levels
to/from levels conforming to RS-232-C and CCITT V.24
standards.

• Meets EIA RS-232-C and CCITT V.24 standard
• Low power consumption
• Pin-for-pin equivalent to DS1488/MC1488 and
DS1489/MC1489

l>

• Low Delay Slew
• DS14C88 Driver
- Power-off source impedance 300n min.
- Wide operating voltage range: 4.5V -12.6V
- TTLILSTTL compatible

Both devices are fabricated in low threshold CMOS metal
gate technology. They provide very low power consumption
in comparison to their bipolar equivalents; 900 JJ-A versus
26 mA for the receiver and 500 JJ-A versus 25 mA for the
driver.

• DS14C89A
- Internal noise filter
-Inputs withstand ±30V
- Fail-safe operating mode
- Internal input threshold with hysteresis

The DS14C88/DS14C89A simplify designs by eliminating
the need for external capacitors. For the DS14C88, slew
rate control in accordance with RS-232-C is provided on
chip, eliminating the output capacitors. For the DS14C89A,
noise pulse rejection circuitry eliminates the need for response control filter capacitors. When replacing the
DS1489 with DS14C89A, the response control filter pins
can be tied high, low or not connected.

Connection Diagrams
DS14C89A Dual-In-Line Package

DS14C88 Dual-In-Line Package
V'

INPUT
Vee

14

o

NC

12

OUTPUT
0

11

INPUT
C

NC

OUTPUT
C

10

GND
TL/F/8508-9

Order Number DS14C88J, DS14C88N and DS14C88M
See NS Package Number J14A, M14A or N14A
INPUT
A

NC

OUTPUT

INPUT

A

B

NC

OUTPUT
B

GND
TL/F/8508-2

Order Number DS14C89AJ, DS14C89AM or DS14C89AN
See NS Package Number J14A, M14A or N14A

1-17

•



c:(
0)

co

OS 14C89A Quad CMOS Line Receiver

C/)

Absolute Maximum Ratings

o
-.::t
,....

c

(Note 1)

co

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

,....

Voltage at Any Input Pin

"co

o-.::t

C/)

c

Lead Temp. (Soldering 10 sec)
Supply Voltage

+ 260°C
+6V

This product does not meet 2000V ESD rating. (Note 3)

-30Vto +30V

Voltage at Any Output Pin

Operating Conditions

(Vee> + 0.3V to GND - 0.3V

Storage Temperature

- 65°C to + 150°C

Power Dissipation

500 mW at + 75°C

Junction Temperature

Supply Voltage Vee (GND= OV)
Temperature Range

+150°C

Min

Max

+4.5V
O°C

+5.5V
+75°C

Max

Units

DC Electrical Characteristics
T A = O°C to + 75°C, + 4.5 S; Vee S; 5.5V, GND = OV, unless otherwise specified

Symbol

Parameter

Conditions

Typ

Min

VTH

Input High Threshold Voltage

1.3

2.7

V

VTL

Input Low Threshold Voltage

0.5

1.9

V

VH

Typical Input Hysteresis

liN

Input Current

3.6
-3.6

8.3
-8.3

mA

+0.43
-0.43

+1.0
-1.0

mA
mA

1.0
VIN = +25V
VIN = -25V
VIN = +3V
VIN = -3V

VOH

Output High Voltage

VIN = VTL (min)
lOUT = - 3.2 mA

VOL

Output Low Voltage

VIN = VTH(max)
lOUT = + 3.2 mA

Ice

Supply Current

V

mA

V

2.8

RL = open

0.4

V

+900

fLA

VIN = VTH (max)
orVTL (min)

AC Electrical Characteristics
T A = O°C to + 75°C, + 4.5V s; Vee s; + 5.5V, GND = OV, CL = 50 pF, unless otherwise specified (Note 2)

Symbol

Parameter

Conditions

Max

Units

tpLH

Propagation Delay to a Logic "1"

Input pulse width::::: 10 fLs

Min

Typ

6.5

fLs

tpHL

Propagation Delay to a Logic "0"

Input pulse width::::: 10 fLs

6.5

fLs

tSK

Typical Propagation Delay Skew

tr

Output Rise Time

300

ns

tf

Output Fall Time

300

ns

tnw

Pulse Width Assumed to be Noise

1.0

fLS

400

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range",

they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: AC input waveform for test purposes: tr = tf = 200 ns, VIH = + 3V, VIL = -3V, f = 20 kHz.
Note 3: For additional details on ESD, contact the local National Semiconductor Sales Office.

1-20

o

en

DS14C89A AC Test Circuit

...a.
~

Vee

oC)

OUTPUT

C)

.......

o

en
...a.
~

oC)
CD

l>

PULSE
GENERATOR

TL/F/8508-4

DS14C89A Timing Diagram
-tNW-

VOUT---I--

TL/F /8508-5

Typical Applications for DS 14C88 and DS 14C89A

III

RS232C Data Transmission

TTL

1/4 DS14C88

1/4DS14C89A

---r-'k>--

TTL
--~-,

---1

--..

--~-~

t .... - -

--"1.._~

INTERCONNECTING
CABLE

TTL

TTl

114DS14C89A

'-'1- __

---~(-1:==

... - ,_.J---

-~:t

... _.1- - 1/4 DS14C88

DATA TERMINAL
EQUIPMENT (DTE)

SIGNAL GROUND

-=-

DATA COMMUNICATIONS
EQUIPMENT (DCE)

TL/F/8508-3

1-21

o-~~- OUTPUT

LEVEL
SHIFTER

INPUT 2

SLEW RATE
CONTROL

TLIF/8508-6

DS14C89A
(% circuit shown)

INPUT -..I\IVY--'---1
INPUT
RESISTOR
COMPARATOR

OUTPUT

NOISE
FILTER

OUTPUT
DRIVER
TL/F/8508-1

1-22

c
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.......

~National

.I:lo

(X)

D Semiconductor

CD
.......

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.......
.I:lo

DS1489/DS1489A Quad Line Receiver

(X)

CD

l>

General Description

Features

The DS1489/DS1489A are quad line receivers designed to
interface data terminal equipment with data communications equipment. They are constructed on a single monolithic silicon chip. These devices satisfy the specifications of
EIA Standard RS-232C. The DS1489/DS1489A meet and
exceed the specifications of MC1489/MC1489A and are
pin-for-pin replacements.

•
•
•
•
•

Four totally separate receivers per package
Programmable threshold
Built-in input threshold hysteresis
"Fail safe" operating mode
Inputs withstand ± 30V

Schematic and Connection Diagrams
Dual-In-Llne Package
INPUT
0

Vee

RESPONSE
CONTROL
0

OUTPUT
0

INPUT
C

11

10

RESPONSE
CONTROL
C

OUTPUT
C

r-----.-----.---~V~
14

(% of unit shown)
~~s:~:~~

9k

13

12

2k

Sk

R,

OUTPUT

O------------....--+-JIII/'V-.....

4k

INPUT

o--JIII/'V-..........- -....--1

~--.-.--...- -....- -....- - < l GNO

DS1489: RF

=

DS1489A: RF

TL/F/5777-1

10k

=

2k
INPUT
A

RESPONSE
CONTROL

OUTPUT
A

INPUT
B

RESPONSE
CONTROL

A

OUTPUT
B

GNO

B

TLIF/S777-2

Top View
Order Number DS1489J, DS1489AJ,
DS1489M, DS1489AM, DS1489N or DS1489AN
See NS Package Number J14A, M14A or N14A

AC Test Circuit and Voltage Waveforms
RESPONSE CONTROL
• OPEN

OUTPUT

J

Vee

15pf
INCLUDING
JIG AND PROBE

':'

INPUT

TLIF/5777-3

t

-J

~I'r

OUTPUT

~y;Lt~1

~Jl

1-23

JV

OV

TL/F/5777-4

<

Q)

co
~

.....
c......

tJ)

Q)

co

Absolute Maximum Ratings

(Note 1)

If Military I Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.

~

Power Supply Voltage

tJ)

Input Voltage Range

±30V

Output Load Current

20mA

.....
c

10V

Power Dissipation (Note 2)

1308 mW
1207 mW
1042 mW

Lead Temperature (Soldering, 4 sec.)
260°C
·Derate cavity package 8.7 mWrC above 2S'C; derate molded DIP package
9.7 mWrC above 2S'C; derate 50 package 8.33 mWrC above 2S'C.

1W

Operating Temperature Range
Storage Temperature Range

Maximum Power Dissipation* at 25°C
Cavity Package
Molded DIP Package
SO Package

O°Cto +75°C
- 65°C to + 150°C

Electrical Characteristics

(Notes 2,3 and 4)

DS1489/DS1489A: The following apply for Vee = 5.0V ± 1 %, O°C ~ TA ~ + 75°C unless otherwise specified.
Symbol
VTH

Parameter
Input High Threshold Voltage

Conditions
VOUT ~ 0.45V,
lOUT = 10 mA

DS1489

TA = 25°C

Min

Typ

Max

Units

1.0

1.25

1.5

V

1.6

V

2.25

V

0.9
DS1489A

TA = 25°C

1.75

2.00

1.55
VTL

liN

VOH

Input Low Threshold Voltage

Input Current

Output High Voltage

TA = 25°C

VOUT;;:: 2.5V,
lOUT = -0.5 mA

1.00

0.75
0.65

2.40

V

1.25

V

1.35

V

VIN = +25V

+3.6

+5.6

+8.3

mA

VIN = -25V

-3.6

-5.6

-8.3

mA

VIN = +3V

+0.43

+0.53

VIN = -3V

-0.43

-0.53

VIN = 0.75V

2.6

3.8

5.0

V

Input = Open

2.6

3.8

5.0

V

0.45

lOUT = -0.5 mA

mA
mA

VOL

Output Low Voltage

VIN = 3.0V, lOUT = 10 mA

0.33

Ise

Output Short Circuit Current

VIN = 0.75V

-3.0

Ice

Supply Current

VIN = 5.0V

14

26

mA

Pd

Power Dissipation

VIN = 5.0V

70

130

mW

Switching Characteristics Vec =
Symbol

Parameter

V
mA

5V, T A = 25°C
Conditions

tpd1

Input to Output "High"
Propagation Delay

RL = 3.9k, (Figure 1) (AC Test Circuit)

tpdO

Input to Output "Low"
Propagation Delay

RL = 3900, (Figure 1) (AC Test Circuit)

tr

Output Rise Time

RL = 3.9k, (Figure 1) (AC Test Circuit)

t,

Output Fall Time

RL = 3900, (Figure 1) (AC Test Circuit)

Min

Typ

Max

Units

28

85

ns

20

50

ns

110

175

ns

9

20

ns

1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the O'C to + 7S'C temperature range for the 051489 and D51489A.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value baSis.
Note 4: These specifications apply for response control pin = open.

Note

1-24

Typical Applications
RS-232C Data Transmission

TTL

1/40S1489/
OS1489A

1/4 OS1488

---r-'
---t
):)00-

--..
--'1.._

TTL

--~-,

---L_~

()---

~

INTERCONNECTING

CA8LE

1/40S1489/
OS1489A

TTL

TTL

'-"1--~-,_.J---

,-~--

--·~t

-~:f

,_.J--t---

1/40S1488

INTERFACE DATA
TERMINAL EQUIPMENT

MODEM

SIGNAL GRDUND

TL/F/5777-5

'Optional for noise filtering.

M05 to TTLILS Translator

sv

r-----,

I

TTL/OTL

,...-,

~1._)

MOS LOGIC

L ____ -I

I ,._,

.. ~

I

1/40S1489/
OS1489A

Typical Characteristics Vcc =

5.0 VDC. T A =

I

10

~

20

::>

0

g§
u

::>

-20

i?i

-4.0

~

a..

...J

/

-6.0
-8.0

u

--'

/"

V

V

l/

V

V

z:..
....

4.0

~
0

3.0

(!)

>

I

~

IL I

::>

~VO

::>
0

a..

6
>

5 10 15 20 25

VIN • INPUT VOLTAGE (VOLTS)

~
~~

RT RT RT f RT
5k 13k -00 11k f - f--Vth Vth r- Vth f - f--I
20 +5V +5V

~

III

-10
-25-20 -15-10 -5 0

5.0

"tJ

/

4.0

~

,.

6.0

6.0

III

TL/F/5777-6

+ 25°C unless otherwise noted

8.0

]:

J

L._"'-

1.0

1

1

1

_I
~

R

T

0
IYIHL _ f-- r-ir;
:~ _ ~ILH
"I
-1.0
u
-3.0-20-1.0 0 1.0 20 3.0
VI' INPUT VOLTAGE (Vdc)

TLlF/5777-7

TL/F/5777-B

FIGURE 1. Input Current

FIGURE 2. 051489 Input Threshold
Voltage Adjustment

1·25

Typical Characteristics Vcc =
c.>

5.0 Voc. TA =

+ 25°C unless otherwise noted (Continued)

.,

6.0

"

2.4 , ...... j",.
2.2
I -11
1""'.... ~S1489A
2.0
VIHL r-1.8
1"'1.6
~1489 VIHL
I"'-..
1.4
I~ ....
~
1.2
I""'-r--.
1.0 ~(~
OS1489A VILH
0.8
I
;7
~
0.6
D~14~9 VILH r - r-0.4
0.2

I

5.0

"0

.2:-

4.0

~
0

3.0

I--

2.0

.....
C>

I-I--

>

::>

I-I--

RTf-- f--

5k
VIh
5V

:;f- 11RTk
VIh
-5V

¥

I--

0

0
>

1.0
0

-

...... =- ......

.1.Vth

-= -

~

::>

T

f--

f-

I-

R

+-

--

10...-

10..

;-;

o

-1.0
~
-3.0-2.0-1.0 0 1.0 2.0 3.0 4.0

-60 -40 -20 0

TL/F/5777-10

TLIF/5777-9

FIGURE 4. Input Threshold Voltage
vs Temperature

FIGURE 3. DS1489A Input Threshold
Voltage Adjustment

c.>

"0

20 40 60 80 100 120

T. TEt.4PERATURE (OC)

VI' INPUT VOLTAGE (Vdc)

2.0

~VIHL

.2:.....
C>

I

~
0
>

9
0

::I:
Vl

1.0

OS1489 VIHL
OS1489 VILH
1

OS148 9A VILH

.....
0::

::I:
I-I--

::>
~

~

o

o

4.0

8.0

12.Q

Vee. POWER SUPPLY VOLTAGE (Vdc)
TL/F/5777-11

FIGURE 5. Input Threshold vs
Power Supply Voltage

1-26

c

~National

PRELIMINARY

~ Semiconductor

General Description
The DS26C31 is a quad differential line driver designed for
digital data transmission over balanced lines. The DS26C31
meets all the requirements of EIA standard RS-422 while
retaining the low power characteristics of CMOS. This enables the construction of serial and terminal interfaces while
maintaining minimal power consumption.

disable circuitry common to all four drivers. The DS26C31 is
pin compatible to the AM26LS31 and the DS26LS31.

The DS26C31 accepts TIL or CMOS input levels and translates these to RS-422 output levels. This part uses special
output circuitry that enables the individual drivers to power
down without loading down the bus. The DS26C31 also includes special power up and down circuitry which will TRISTATE the outputs during power up or down, preventing
spurious glitches on its outputs. This device has enable and

•
•
•
•
•
•
•
•

All inputs are protected against damage due to electrostatic
discharge by diodes to Vee and ground.

Features
TIL input compatible
Typical propagation delays: 8 ns
Typical output skew: 0.5 ns
Outputs won't load line when Vee = OV
Meets the requirements of EIA standard RS-422
Operation from single 5V supply
TRI-STATE outputs for connection to system buses
Low quiescent current

Logic and Connection Diagrams
Dual-In-Line Package
INPUT A

INPUT B

INPUT C

INPUT 0

ENABLE

16

INPUT A
CHANNEL A {
OUTPUTS
3
ENABLE

OUTPUT
02

OUTPUT
01

OUTPUT
C2

OUTPUT
Cl

OUTPUT
B2

OUTPUT
Bl

OUTPUT
A2

OUTPUT
Al

CHANNELB{
OUTPUTS

6

TLIF/8574-2
GNO

Truth Table

=
=
X =
Z =
L

H

INPUT C

TLIF/8574-1

Non-Inverting Inverting
Active High Active Low
Input
Enable
Enable
Output
Output
H

X

Z

Z

All other
combinations of
enable inputs

L

L

H

H

H

L

L

m

ow

......
o

DS26C31C CMOS Quad TRI-STATE®
Differential Line Driver

rnm

en

N

Top View
Order Number DS26C31CJ,
DS26C31CM or DS26C31CN
See NS Package Number J16A,
M16Aor N16A

Low logic state
High logic state
Irrelevant
TAl-STATE (high impedance)

For complete specifications see the Interface Databook.

1-27

o

T""

Cf)

oCD

C'I
C/)

C

Absolute Maximum Ratings

Operating Conditions

(Notes 1 & 2)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (Ved

-0.5V to 7.0V

DC Input Voltage (VIN)

-1.5VtoVee +1.5V
-0.5Vto 7V

DC Output Voltage (VOUT)

Max
5.50

Units
V

DC Input or Output Voltage
(VIN, VOUT)
Operating Temperature Range (TA)

0
-40

Vee
+85

°C

500

ns

Input Rise or Fall Times (tr, tf)

V

±150 rnA

DC Output Current, per pin (lOUT)
DC Vee or GND Current, per pin (led

±150 rnA

Storage Temperature Range (TSTG)

- 65°C to + 150°C

Power Dissipation (Po) (Note 3)

500mW

Lead Temperature (T d (Soldering, 4 sec.)

260°C

DC Electrical Characteristics Vee =
VIH

Min
4.50

±20mA

Clamp Diode Current (11K, 10K)

Symbol

Supply Voltage (Ved

5V ± 10% (unless otherwise specified) (Note 4)

Parameter

Conditions

Min

High Level Input Voltage

Max

Typ

Units
V

2.0

VIL

Low Level Input Voltage

VOH

High Level Output Voltage

VIN = VIH or VIL,
lOUT = -20 rnA

VOL

Low Level Output
Voltage

VIN = VIH or VIL,
lOUT = 20 rnA

VT

Differential Output
Voltage

RL = 100n
(Note 5)

IVrl-lvTI

Difference In
Differential Output

RL = 100n
(Note 5)

0.4

V

Vas

Common Mode
Output Voltage

RL = 100n
(Note 5)

3.0

V

Ivos - vosl

Difference In
Common Mode Output

RL = 100n
(Note 5)

0.4

V

liN

Input Current

VIN = Vee, GND, VIH, or VIL

±1.0

J1-A

lee

Quiescent Supply
Current

lOUT = 0 J1-A,
VIN = Vee or GND
VIN = 2.4V or 0.5V (Note 6)

TRI-STATE Output
Leakage Current

VOUT = Vee or GND
ENABLE = VIL
ENABLE = VIH

Ise

Output Short
Circuit Current

VIN = Vee or GND
(Note 7)

10FF

Output Leakage Current
Power Off

Vee

loz

0.8

=

ov

V
V

2.5
0.5

V
V

2.0

I
I

VOUT
VOUT

200
0.8

J1-A
rnA

±0.5

-30

=
=

6V
-0.25V

±5.0

J1-A

-150

rnA

100

J1-A

-100

J1-A

Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified, all voltages are referenced to ground. All currents into device pins are positive, all currents out of device pins are negative.
Note 3: Power Dissipation temperature derating-plastic "N" package: -12 mW I'C from 65'C to 85'C.
ceramic "J" package: -12 mWI'C from 1OO'C to 125'C.
Note 4: Unless otherwise specified, minImax limits apply across the -40'C to 85'C temperature range. All typicals are given for Vee
Note 5: See EIA Specification RS-422 for exact test conditions.
Note 6: Measured per input. All other inputs at Vee or GND.
Note 7: Only one output at a time should be shorted.

1-28

=

5V and

TA

=

25'C.

c

Switching Characteristics Vcc =

± 10%, tr =

5V

en
N

tf = 6 ns (Figures 1,2,3 and 4) (Note 4)

0)

(")

Symbol

Parameter

Min

Conditions

tpLH, tpHL

Propagation Delay
Input to Output

S10pen

Skew

(Note 8)

S10pen

tTLH, tTHL

Differential Output Rise
And Fall Times

S1 Open

tPZH

Output Enable Time

tPZL

Output Enable Time

tpHZ

Output Disable Time
(Note 9)

S1 Closed

tpLZ

Output Disable Time
(Note 9)

S1 Closed

CPD

CIN

Typ

Max

Units

8

ns

0.5

ns

8

ns

S1 Closed

18

ns

S1 Closed

19

ns

9

ns

9

ns

Power Dissipation
Capacitance (Note 10)

100

pF

Input Capacitance

10

pF

Note 8: Skew is defined as the difference in propagation delays between complementary outputs at the 50% pOint.
Note 9: Output disable time is the delay from ENABLE or ENABLE being switched to the output transistors turning off. The actual disable times are less than
indicated due to the delay added by the RC time constant of the load.
Note 10: CPO determines the no load dynamic power consumption, Po

=

Cpo Vee 2 f

+ Icc Vee, and the no load dynamic current consumption, Is = CPO Vee f +

Icc·

AC Test Circuit and Switching Time Waveforms
1.5V

C2

;~
INPUT

• Rl

Cl

=~

0

::.
C3

~.1.

~

y

51

R3

J

•• R2

-

Note: C1

=

C2

=

C3

=

40 pF, Rl

TL/F/B574-3

=

R2

=

50n, R3

=

500n.

FIGURE 1. AC Test Circuit

ENABLE INPUT 3.0V

f=1 ~Hz, trs 6 ns,

I.

INPUT JV

'=lMHz, tr,,6ns,
",,6ns

"'1

ov--1

OUTPUT _

t f S6ns

'-1.3V

- y.::'.LH
1.JV

OUTPUT-~V
tpHL-

-'~

l

~

~r-l.3V

O.OV
I.SY-

~

-,( YOL+O.3V

VOL

TpLZ - YOH

£

TpZL

~f\ VOH-O.3V

~
2.0Y

1.SY-

TpHZ f4--

TpZHR
TL/F/B574-5

FIGURE 3. Enable and Disable Times

TL/F/B574-4

FIGURE 2. Propagation Delays

1-29

U)

-'"
(")

o
.....
C")

o
CD

AC Test Circuit and Switching Time Waveforms (Continued)

N

CJ)

C
INPUT

:-.1 \'--__
90%

OUTPUT
(DIFFERENTIAL)

tTLH
Input pulse; f =1MHz, 50%; tr= tf" 6ns.

TL/F/B574-7

FIGURE 4. Differential Rise and Fall Times

Typical Applications
Two-Wire Balanced System, RS-422

DATA
OUTPUT

TLlF/B574-B

1-30

c

en

~National

a

N

0)

"TI

Semiconductor

W

.....

(')

......

c

DS26F31C/DS26F31M
Quad High Speed Differential Line Driver

en

General Description

Features

:ii:

The DS26F31 is a quad differential line driver designed for
digital data transmission over balanced lines. The DS26F31
meets all the requirements of EIA Standard RS-422 and
Federal Standard 1020. It is designed to provide unipolar
differential drive to twisted-pair or parallel-wire transmission
lines.

•
•
•
•
•
•
•

The DS26F31 offers improved performance due to the use
of state-of-the-art L-FAST bipolar technology. The L-FAST
technology allows for higher speeds and lower currents by
utilizing extremely short gate delay times. Thus, the
DS26F31 features lower power, extended temperature
range, and improved specifications.
The circuit provides an enable and disable function common
to all four drivers. The DS26F31 C/DS26F31 M features TRISTATE® outputs and logical OR-ed complementary enable
inputs. The inputs are all LS compatible and are all one unit
load.

•
•
•
•
•

N

0)

"TI

W
.....

Low power version
Output skew-2.0 ns typical
Input to output delay-12 ns
Operation from single + 5.0V supply
16-lead ceramic and molded DIP Package
Outputs won't load line when Vee = OV
Four line drivers in one package for maximum package
density
Output short circuit protection
Complementary outputs
Meets the requirements of EIA standard RS-422
High output drive capability for 100n terminated
transmission lines
Extended temperature range

The DS26F31 C/DS26F31 M offers optimum performance
when used with the DS26F32 Quad Differential Line
Receiver.

Connection and Logic Diagrams
16-Lead Dual-In-Line Package
and SO-16 Package

INPUT

ENABLE

INPUT
C

INPUT

INPUT

D

B

A

D1 D2

C1 C2

B182

A1 A2

ENABLE

16

IN A

Vee
15

OUT Al

14

OUT A2

13

ENABLE

IN 0

OUT 01

OUT 02

GND

VCC

'~

12

OUT B2

11

OUT Bl

10

IN B

OUTPUTS

ENABLE

TLlF/9614-2

FIGURE 1. Logic Symbol
OUT C2

Function Table (Each Driver)

OUT Cl

Input
GNO

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J /

Outputs

Enable

IN C

V

Z

H

L

H

H

Top View

L

H

L

H

Order Number DS26F31CJ or DS26F31MJ
See NS Package Number J16A *

X

L

Z

Z

TL/F/9614-1

H

Order Number DS26F31CN
See NS Package Number N16A

=

High Level

L = Low Level

Order Number DS26F31CM
See NS Package Number M16A
'For most current package information contact product marketing.

1-31

x

=

Z

= High Impedance (Off)

Immaterial

:5
,....
C")

Absolute Maximum Ratings

CD
N

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications,

DS26F31C
Temperature
Supply Voltage

O°Cto + 70°C
4.75V to 5.25V

Storage Temperature Range
Ceramic DIP
Molded DIP and SO Package

DS26F31M
Temperature
Supply Voltage

- 55°C to + 125°C
4.5Vto 5.5V

u.

U)

C
.......

o
,....
C")
u.
CD
N

U)

C

-65°C to
- 65°C to

+ 175°C
+ 150°C

Lead Temperature
Ceramic DIP (Soldering, 60 sec.)
Molded DIP and SO·16
(Soldering, 10 sec.)
Maximum Power Dissipation" at 25°C
Cavity Package
Molded Package
SO Package

Operating Range

(Note 1)

300°C
265°C
1500mW
1040mW
960mW

Supply Voltage

7.0V

Input Voltage

7.0V
Output Voltage
5.5V
'Derate cavity package 10 mWfOC above 25'C; derate molded DIP package
8.3 mWfOC above 25'C; derate SO package 7.7 mW'C above 25'C.

Electrical Characteristics over operating range, unless otherwise specified (Notes 2 & 3)
Symbol

Min

Typ

= -20 mA
Min, IOL = 20 mA

2.5

3.2

Min

2.0

Parameter

Conditions

VOH

Output Voltage HIGH

Vee

VOL

Output Voltage LOW

Vee

VIH

Input Voltage HIGH

Vee

VIL

Input Voltage LOW

Vee

IlL

Input Current LOW

Vee

IIH

Input Current HIGH

Vee

IIR

Input Reverse Current

Vee

loz

Off State (High Impedance)
Output Current

Vee

Vie

Input Clamp Voltage

Vee

los

Output Short Circuit

Vee

Icex

Supply Current

Ice
tpLH

Input to Output

tpHL

Input to Output

SKEW

Output to Output

tLZ

Enable to Output

tHZ

Enable to Output

tZL

Enable to Output

tZH

Enable to Output

=
=
=
=
=
=
=
=

Min, IOH

0.32

= O.4V
Max, VI = 2.7V
Max, VI = 7.0V
Max

I
I

Vo
Vo

-0.10

= 2.5V
= 0.5V

= Min, II = -18 mA
= Max (Note 4)
Vee = Max, All Outputs Disabled
Vee = Max, All Outputs Enabled
Vee = 5.0V, TA = 25°C,
Load = Note 5
Vee = 5.0V, TA = 25°C,
Load = Note 5
Vee = 5.0V, TA = 25°C,
Load = Note 5
Vee = 5.0V, TA = 25°C,
CL = 10 pF
Vee = 5.0V, TA = 25°C,
CL = 10 pF
Vee = 5.0V, TA = 25°C,
Load = Note 5
Vee = 5.0V, TA = 25°C,
Load = Note 5

Note 1: "Absolute Maximum

-30

Units

V
0.5

V
V

Max
Max, VI

Max

0.8

V

-0.20

mA

0.5

20

IJ-A

0.001

0.1

mA

0.5

20

0.5

-20

IJ-A

-0.8

-1.5

V

-60

-150

mA

50

mA

40

mA

10

15

ns

10

15

ns

2.0

4.5

ns

23

32

ns

15

25

ns

20

30

ns

23

32

ns

Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the - 55'C to + 125'C temperature range for the DS26F31 Mand across the O'C to + 70'C range
for the DS26F31 C. All typicals are given for Vee = 5V and TA = 25'C.
Note 3: All currents into the device pins are positive; all currents out of the device pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 4: Only one output at a time should be shorted.
Note 5: CL = 30 pF, VI = 1.3V to Vo = 1.3V, VPULSE = OV to +3V (See AC Load Test Circuit for TRI-STATE Outputs).
1·32

c

en

Test Circuit and Timing Waveforms

N

m

"T1

INPUT
TRANSITION

TEST
POINT

1

7S!l.

(")

"T1

W
.....
::

S2

~
TL/F/9614-4

TL/F/9614-3

ENABLE

m

OUT

FIGURE 2. AC Load Test Circuit for TRI-STATE Outputs

ENABLE
INPUT

"enc

I'----OV

N

FROM OUTPUT - -..........- - 0 '
UNDER TEST
CL
RI
(NOTE 4)

W
.....

r-------~-------3V

FIGURE 3. Propagation Delay (Notes 1 and 3)

DISABLE

r-----~--------3V

I'------OV

OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH

Note 1: Diagram shown for Enable Low. Switches Sl and S2 open.
Note 2: Sl and S2 of Load Circuit are closed except where shown.
Note 3: Pulse Generator for all Pulses: Rate oS: 1.0 MHz. Zo
6.0 ns, tf oS: 6.0 ns.

= 50n, tr

oS:

Note 4: CL includes probe and jig capacitance.

"",1.5V

O.SV
TL/F/9614-5

FIGURE 4. Enable and Disable Times (Notes 2 and 3)

Typical Application

DATA
OUT

DATA
IN

DATA
OUT

SHIELD OR COMMON GROUND RETURN
TL/F/9614-6

FIGURE 5. Typical Application

1-33

~National

~ Semiconductor
DS26LS31C/DS26LS31M Quad High
Speed Differential Line Driver
General Description

Features

The DS26LS31 is a quad differential line driver designed for
digital data transmission over balanced lines. The
DS26LS31 meets all the requirements of EIA Standard
RS-422 and Federal Standard 1020. It is designed to provide unipolar differential drive to twisted-pair or parallel-wire
transmission lines.

•
•
•
•
•
•

The circuit provides an enable and disable function common
to all four drivers. The DS26LS31 features TRI-STATE®
outputs and logically ANDed complementary outputs. The
inputs are all LS compatible and are all one unit load.

•
•
•
•
•
•

The DS26LS31.features a power up/down protection circuit
which keeps the output in a high impedance state (TRISTATE) during power up or down preventing erroneous
glitches on the transmission lines.

Output skew-2.0 ns typical
Input to output delay-10 ns
Operation from single 5V supply
16-pin hermetic and molded DIP package
Outputs won't load line when Vee = OV
Four line drivers in one package for maximum package
density
Output short-circuit protection
Complementary outputs
Meets the requirements of EIA Standard RS-422
Pin compatible with AM26LS31
Available in military and commercial temperature range
Glitch free power up/down

Logic and Connection Diagrams
ENABLE

ENABLE

INPUT D

INPUT A

INPUT B

INPUT C

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

DZ

D1

CZ

C1

BZ

B1

AZ

A1
TLIF/5776-1

Dual-In-Line Package

INPUT A

CHANNEL A {
OUTPUTS

~I-----I

ENABLE

INPUT B

GND
TL/F/5776-2

Top View
Order Number DS26LS31CJ, DS26LS31CM,
DS26LS31CN or DS26LS31MJ
See NS Package Number J16A, M16A or N16A

1-34

Absolute Maximum Ratings

c
en
N

Operating Conditions

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office I
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Output Voltage

7V
5.5V

0)

Min

Max

Units

Supply Voltage, Vcc
DS26LS31M
DS26LS31

4.5
4.75

5.5
5.25

V
V

Temperature, TA
DS26LS31M
DS26LS31

-55
0

+125
+70

°C
°C

Output Voltage (Power OFF)

-0.25 to 6V
Maximum Power Dissipation· at 25°C
Cavity Package
1509mW
Molded DIP Package
1476mW
SO Package
1051 mW
'Derate cavity package 10.1 mWI'C above 2S"C; derate molded DIP pack·
age 11.9 mW I'C above 2S"C; derate SO package 8.41 mW I'C above
2S"C.

Electrical Characteristics
Symbol

Max

Units

Conditions

Min

VOH

Output High Voltage

10H

= -20 mA

2.5

VOL

Output Low Voltage

10L

= 20mA

VIH

Input High Voltage

VIL

Input Low Voltage

IlL

Input Low Current

VIN

= OAV

IIH

Input High Current

VIN

= 2.7V

20

p.A

II

Input Reverse Current

VIN

= 7V

0.1

mA

10

TRI-STATE Output Current

Vo

= 2.5V

20

p.A

Vo

= 0.5V

-20

p.A

liN

= -18mA

-1.5

V

-150

mA

60

mA

VCL

Input Clamp Voltage

Isc

Output Short-Circuit Current

Icc

Power Supply Current

Symbol

Typ

V
0.5

2.0

-40

All Outputs Disabled
or Active
5V, TA

V
V

-30

Switching Characteristics Vcc =

35

0.8

V

-200

p.A

= 25°C
Typ

Max

Units

tpLH

Input to Output

CL = 30 pF

10

15

ns

tpHL

Input to Output

CL = 30 pF

10

15

ns

Parameter

Conditions

Min

Skew

Output to Output

CL

= 30 pF

2.0

6.0

ns

tLZ

Enable to Output

CL

= 10 pF, S2 Open

15

35

ns

tHZ

Enable to Output

CL

= 10 pF, S1 Open

15

25

ns

tZL

Enable to Output

CL

= 30 pF, S2 Open

20

30

ns

ns
CL = 30 pF, S1 Open
Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -SS"C to + 12S"C temperature range for the DS726LS31 M and across the O°C to + 70°C
range for the D526LS31. All typicals are given for Vee = SV and TA = 2S"C.
Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.
Note 4: Only one output at a time should be shorted.
tZH

o
.......
c
en
N

0)

r-

en
w
.....

3:

(Notes 2,3 and 4)

Parameter

r-

en
w
.....

Enable to Output

20

Note 1: "Absolute

1-35

30

==
..M
en

AC Test Circuit and Switching Time Waveforms

...I

CD
C\I

TEST
POINT

en
c
o
"..M
en
...I

CL (lNCLUOES
PROBE AND JIG

CD
C\I

I

CAPACITANCEI ':"

en
c

TL/F/S778-3

Note: 51 and 52 of load circuit are closed except where shown.

FIGURE 1. AC Test Circuit

DISABLE

OV
tpZL
OUTPUT
S2 OPEN
VOL-------'------------~~·

VOH-------'------------~~
OUTPUT
Sl OPEN
TLlF/S778-4

f

= 1 MHz, t,

~

15 ns, tf

~

tpZH

6 ns
TL/F/S778-S

FIGURE 2. Propagation Delays
f = 1 MHz, t,

~

15 ns, tf

~

6 ns

FIGURE 3. Enable and Disable Times

Typical Applications
Two-Wire Balanced System, RS-422

DATA
OUTPUT

TL/F/S778-6

°RT is optional although highly recommended to reduce reflection.

1-36

c

~National

PRELIMINARY

~ Semiconductor
DS26C32C Quad Differential Line Receiver
General Description

Features

The DS26C32 is a quad differential line receiver designed to
meet the RS-422, RS-423, and Federal Standards 1020 and
1030 for balanced and unbalanced digital data transmission, while retaining the low power characteristics of CMOS.

• Low power CMOS design
• ± 0.2V sensitivity over the entire common mode range
• Typical propagation delays: 20 ns
• Typical input hysteresis: 50 mV
• Input fail-safe circuitry
• Inputs won't load line when Vee = OV
• Meets the requirements of EIA standard RS-422
• TRI-STATE outputs for connection to system buses

The DS26C32 has an input sensitivity of 200 mV over the
common mode input voltage range of ± 7V. Each receiver is
also equipped with input fail-safe circuitry, which causes the
output to go to a logic "1" state when the inputs are open.
The DS26C32 provides an enable and disable function
common to all four receivers, and features TRI-STATE®
outputs with 6 mA source and sink capability. This product is
pin compatible with the DS26LS32A and the AM26LS32.

Logic Diagram
ENABLE

ENABLE

GND

Vee

IN D2

IN D1

IN e2

OUTPUT D

IN e1

IN B2

OUTPUT e

IN B1

IN A2

OUTPUT B

IN A1

OUTPUT A
TLlF/8764-1

Connection Diagram

Truth Table

Dual-In-Line Package

ENABLE
0
Vee

INPUTS A {

I
I

ENABLE

Input

Output

1

X

Hi-Z

See
Note Below

OUTPUT A .....;;.........- - - 1
Hi-Z

' - - - - 1 - OUTPUT B

ENABLE

=

V,D ;::: VTH (Max)

1

V,D ::;; VTH (Min)

0

Open

1

TRI-STATE

Note: Input conditions may be any combination not defined for ENABLE and
ENABLE.

OUTPUT e ...;.04----.
.-----I~

0 UTPUT D

For complete specifications
see the Interface Databook.
GND

TLlF/8764-2

Top View
Order Number DS26C32CJ, DS26C32CM,
DS26C32CN, DS26C32MJ or DS26C32MN
See NS Package J 16A, M 16A or N 16A

1-37

en
N

CJ)

oW
N
o

o
N

C")

o
(D
N

tJ)

C

Absolute Maximum Ratings

Operating Conditions

(Notes 1 & 2)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VcC>

7V

Common Mode Range (VCM)

±14V

Differential Input Voltage (VOIFF)

±14V

Enable Input Voltage (VIN)
Storage Temperature Range (TSTG)
Lead Temperature (Soldering 4 sec.)
Maximum Current Per Output

Min

Max

Units

Supply Voltage (VcC>

4.75

5.25

Operating Temperature Range (TA)

-40

+85

V
·C

500

ns

Enable Input Rise or Fall Times

7V
- 65·C to + 150·C
260·C
±25mA

DC Electrical Characteristics Vcc =

5V ± 5% (unless otherwise specified) (Note 3)

Symbol

Conditions

Parameter

VTH

Minimum Differential
Input Voltage

VOUT = VOH orVaL
-7V < VCM < +7V

RIN

Input Resistance

-7V < VCM < +7V
(One Input AC GND)

liN

Input Current
(Under Test)

VOH

Minimum High Level
Output Voltage

VCC = Min, VOIFF = + 1V
lOUT = - 6.0 mA

VOL

Maximum Low Level
Output Voltage

VCC = Max, VOIFF = + 1V
lOUT = 6.0 mA

VIH

Minimum Enable High
Input Level Voltage

VIL

Maximum Enable Low
Input Level Voltage

loz

Maximum TRI-STATE
Output Leakage Current

VOUT = VccorGND,
ENABLE = VIL,
ENABLE = VIH

II

Maximum Enable Input
Current

VIN = Vcc or GND

Icc

Quiescent Power
Supply Current

Vec = Max,
VOIFF = +1V

VHYST

Input Hysteresis

Parameter

-0.2

Max

Units

+0.2

V

10

kO

VIN = + 10V, Other Input = GND

-1.1

mA

VIN = -10V, Other Input = GND

+1.6

mA

4.2

V

3.84

0.2

0.33

V
V

2.0

AC Electrical Characteristics Vec =
Symbol

Typ

Min

±0.5

0.8

V

±5.0

p.A

±1.0

p.A

12

mA

50

mV

5V ±5% (Note 3)

Conditions

tpLH,
tpHL

Propagation Delay
Input to Output

CL = 50 pF

tpLZ,
tpHZ

Propagation Delay
ENABLE to Output

tpZL,
tPZH

Propagation Delay
ENABLE to Output

Min

Typ

Max

Units

20

ns

CL = 50 pF
RL = 10000
VOIFF = 2.5V

12

ns

CL = 50 pF
RL = 10000
VOIFF = 2.5V

14

ns

VOIFF = 2.5V

Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified, all voltages are referenced to ground.
Note 3: Unless otherwise specified, MinIMax limits apply across the -40·C to

+ 85'C temperature range. All typicals are given for Vee =

1-38

5V and TA

= 25'C.

c

en

Test and Switching Waveforms

N

0)

(')
W
N

Test Circuit for TRI-STATE
Output Tests

Propagation Delay
,.-----~
OUTPUT

{

-----i 'PL:~

v- INPUT
v+ =OV INPUT

"

j'PHLF::~sv
~

,

VOH

50 %

V+ INPUT

OV
-2.5V

V- INPUT
TL/F/8764-3

TL/F/8764-4

CL includes load and test jig capacitance.
51
51

=
=

Vee for tpZL. and tpLZ measurements.
Gnd for tPZH and tPHZ measurements.

TRI-STATE Output Enable and Disable Waveforms
OUTPUT
CONTROL
(LOW ENABLING)

I~~~--------------------------GND

' - - - - - - - - - VOL

'PZ"~J

OUTPUT

v"

J50r.
'---------------------------------J----------------VOL

1-39

TLlF/8764-5

(')

:!:
N

('I')

U.

CD
N

en
C
......
oN

~National

~ Semiconductor

DS26F32C/DS26F32M
Quad Differential Line Receiver
N
en
C
('I')

U.

CD

General Description

Features

The DS26F32 is a quad differential line receiver designed to
meet the requirements of EIA Standards RS-422 and RS423, and Federal Standards 1020 and 1030 for balanced
and unbalanced digital data transmission.

• Low power version
• Input voltage range of ± 7.0V (differential or common
mode) ± 0.2V sensitivity over the input voltage range
• Meets all the requirements of EIA standards RS-422
and RS-423
• Input impedance (18k typical)
• 30 mV input hysteresis
• Operation from single + 5.0V supply
• Fail-safe input/output relationship. Output always high
when inputs are open
• TRI-STATE drive, with choice of complementary output
enables, for receiving directly onto a data bus
• Propagation delay 15 ns typical
• Advanced low power Schottky processing
• Extended temperature range

The DS26F32 offers improved performance due to the use
of state-of-the-art L-FAST bipolar technology. The L-FAST
technology allows for higher speeds and lower currents by
utilizing extremely short gate delay times. Thus, the
DS26F32 features lower power, extended temperature
range, and improved specifications.
The device features an input sensitivity of 200 mV over the
input range of ± 7.0V. The DS26F32 provides an enable
function common to all four receivers and TRI-STATE® outputs with 8.0 rnA sink capability. Also, a fail-safe input/output relationship keeps the outputs high when the inputs are
open.
The DS26F32 offers optimum performance when used with
the DS26F31 Quad Differential Line Driver.

Function Table

Connection Diagram
16-Lead DIP and SO-16 Package

Differential Inputs

16

-IN A

Vee
15

+IN A

14
OUT A

13
ENABLE

12
OUT C

11

+IN C

-IN B

+IN B

(Each Receiver)
Outputs

Enables

A-8

E

E

V

VIO ~ 0.2V

H
X

X
L

H
H

VID::;: -0.2V

H
X

X
L

L
L

X

L

H

Z

H = High Level
L = Low Level
X = Immaterial

OUT B

Order Number DS26F32CJ or DS26F32MJ
See NS Package Number* J16A

ENABLE

Order Number DS26F32CM
See NS Package Number M16A
OUT D

-IN C

+IN D

GND

-IN D

Order Number DS26F32CN
See NS Package Number N16A
"For most current package information contact product marketing.

TL/F/9615-1

Top View

1-40

c
Absolute Maximum Ratings

en

I\)
0)

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range
Ceramic DIP
Molded DIP and SO-16

- 65·C to + 175·C
- 65·C to + 150·C

Operating Temperature Range
DS26F32M
DS26F32C

- 55°C to + 125·C
O·Cto +70·C

Lead Temperature
Ceramic DIP (soldering, 60 sec)
Molded DIP and SO-16
(soldering, 10 sec)

Supply Voltage

Electrical Characteristics

±25V

Differential Input Voltage
Enable Voltage
Output Sink Current

300·C
265·C

O·Cto +70·C
4.75V to 5.25V

DS26F32M
Temperature
Supply Voltage

- 55·C to + 125·C
4.5Vto 5.5V

Min

Typ

Max

Units

+0.2

V

-7.0V:o::: VCM :0::: +7.0V,
Vo = VOL or VOH

-0.2

±0.06

RI

Input Resistance

-15V:o::: VCM :0::: + 15V,
One Input AC Ground

14

18

II

Input Current (under Test)

VI = +15V,
Other Input -15V
VI = -15V,
Other Input -15V

VOL

Output Voltage HIGH

Output Voltage LOW

VI

:0:::

VI

:0:::

:0:::

k!1

2.3

+ 15V

mA
-2.8

+ 15V

VCC = Min,
/lVI = + 1.0V,

O·Cto +70·C

VENABLE = 0.8V,
10H = - 440 p,A

- 55·C to + 125·C

VCC = Min,
/lVI = -1.0V,

10L = 4.0 mA

004

10L = 8.0 mA

0045

VENABLE

=

2.8

3.4
V

2.5

304

0.8V

V

0.8

V

-1.5

V

VIL

Enable Voltage LOW

VIH

Enable Voltage HIGH

VIC

Enable Clamp Voltage

VCC

=

Min, II

loz

Off State (High Impedance)
Output Current

Vcc

=

Max

IlL

Enable Current LOW

VI

-0.2

-0.36

mA

IIH

Enable Current HIGH

VI = 2.7V

0.5

10

p,A

II

Enable Input High Current

VI = 5.5V

1.0

50

p,A

los

Output Short Circuit Current

Vo = OV, Vcc = Max, (Note 4)
/lVI = + 1.0V

-50

-85

mA

Icc

Supply Current

VCC = Max, All VI = GND,
Outputs Disabled

30

50

mA

VHYST

Input Hysteresis

T A = 25·C, Vcc = 5.0V, VCM = OV

30

V

2.0

=

-18 mA
Vo

=

20

2AV

OAV

1-41

p,A

-20

Vo = OAV

=

-15

0)

."
W
I\)

Differential Input Voltage

VOH

en
I\)

3:

VTH

:0:::

I\)

o
c

7.0V
50mA

DS26F32C
Temperature
Supply Voltage

Conditions

W

±25V

Over operating range, unless otherwise specified (Notes 2 and 3)

Parameter

."

........

Operating Range

Maximum Power Dissipation" at 25·C
Cavity Package
1500mW
Molded Package
1040 mW
SO Package
960mW

o
.......

N

c
en
N

Electrical Characteristics over the operating temperature range unless otherwise specified (Notes 2,3 and 4)
Symbol

Parameter

Conditions

I DS26LS32, DS26LS32A, -7V :::;: VCM :::;: + 7V
I DS26LS33, DS26LS33A, -15V :::;: VCM + 15V

VTH

Differential Input
Voltage

VOUT = VOH
or VOL

RIN

Input Resistance

-15V :::;: VCM :::;: + 15V (One Input AC GND)

liN

Input Current (Under
Test)

VIN = 15V, Other Input -15V :::;: VIN :::;: + 15V

VOH

VOL

Output High Voltage

Output Low Voltage

Typ

Max

Units

-0.2

±0.07

0.2

V

-0.5

±0.14

0.5

6.0

8.5

c
N

2.3

mA

en
w

-2.8

mA

3:
.......

2.7

4.2

V

Military

2.5

4.2

V

VCC = Min, a VIN = -1V,
VENABLE = 0.8V

10l = 4 mA

0.4

V

10L = 8 mA

0.45

V

0.8

V

Enable High Voltage

VI

Enable Clamp
Voltage

VCC = Min, liN = -18 mA

10

OFF·State (High
Impedance) Output
Current

VCC = Max

Enable Low Current

2.0

V
-1.5

V

Vo = 2.4V

20

JJ-A

Vo = 0.4V

-20

JJ-A

VIN = O.4V

-0.36

mA

20

JJ-A

-85

mA

70

mA

80

mA

IIH

Enable High Current

VIN = 2.7V

Isc

Output Short·Circuit
Current

Vo = OV, Vcc = Max, aVIN = 1V

Icc

Power Supply
Current

Vcc = Max, All VIN = GND,
Outputs Disabled

II

Input High Current

VIN = 5.5V

VHYST

Input Hysteresis

TA = 25°C, Vcc = 5V,
VCM = OV

-15
DS26LS32,DS26LS32A

52

DS26LS33,DS26LS33A

57

100
DS26LS32,DS26S32A

100

JJ-A
mV

DS26LS33,DS26LS33A
200
mV
"Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: All currents into device pins are shown as positive, all currents out of device pins are shown as negative, all voltages are referenced to ground, unless
otherwise specified. All values shown as max or min are so classified on absolute value basis.
Note 3: All typical values are Vee = 5V, TA = 25'C.
Note 4: Only one output at a time should be shorted.
Note 1:

1·45

w
o
.......

V

Commercial

VIH

ren
w

kn

VCC = MIN, aVIN = 1V,
VENABLE = 0.8V, 10H = -440 JJ-A

Enable Low Voltage

III

en

Min

VIN = -15V, Other Input -15V :::;: VIN :::;: + 15V

VIL

c
en
N
en

Supply Voltage, (Vce)
DS26LS32M,DS26LS33M
(MIL)
DS26LS32C, DS26LS33C
DS26LS32AC,DS26LS33AC
(COML)
Temperature, (TA)
DS26LS32M,DS26LS33M
(MIL)
DS26LS32C, DS26LS33C
DS26LS32AC, DS26LS33AC
(COML)

7V
50mA

N

o
.......

Operating Conditions

±25V
±25V

ren
w

en

en

rw

c
en
N

en

ren
w

w
l>

o

o

-.
~

CL=15pF
-'"- INCLUDES PROBE

~ANOSTRAV

51

~ CAPACITANCE

~

I TRI·STATE® CONTROL
C

)

1.5V

2V
TL/F/5779-3

INPUT

3V~.5V
DV
tpLH(O)

OUTPUT

tPLH(O)

I

VOH

1I,.3V
1.3V
1
VOL---.-:T
DV------------------TL/F/5779-4

Input pulse characteristics:
tTLH
PRR

= tTHL = 6 ns (10% to 90%)
= 1 MHz, 50% duty cycle

FIGURE 1. Propagation Delay Differential Input to Output

1-56

AC Test and Switching Time Waveforms
TO SCOPE
(INPUT)

c
en

(,,)

(Continued)

0l:Io
CO

en
TRI·STATE
CONTROL

TO SCOPE
(OUTPUT)

2k
DIFFERENTIAL
INPUTS
CL = 15 pF INCLUDES
PROBE AND STRAY
CAPACITANCE

T

All DIODES lN916 OR
EQUIVALENT

5k

1.5V for tpHZ and tpLZ
- 1.5V for tpLZ and tpZL
Input pulse characteristics:
ITLH = ITHL = 6 ns (10% 10 90%)
PRR = 1 MHz, 50% duty cycle

TL/F/5779-5

JV

JV

INPUT
OV
PLZ

"'1.JV
OUTPUT
VOL
OV

SWI CLOSED
SW2CLOSED

OV---i-...._ -

~

.

EOUT

O~V

=T

~t;PHZ

SWI CLDSED
SW2 CLOSED

.:::=sr

OV---------TL/F/5779-7

TL/F/5779-6

tpZH

tPZL
JV

JV
INPUT

INPUT

SW10PEN
SW2 CLOSED

OV - -

SWI CLOSED
SW2 OPEN

"'5V-VBE~---

VDH=lJ;-PZH

tpZL

1.5V

OUTPUT

OV-----'
TL/F/5779-8

1.5V
VOL
OV---------TLIF/5779-9

FIGURE 2. Propagation Delay TRI-STATE Control Input to Output

1-57

.....
co

~ ~National
~ D Semiconductor

PRELIMINARY

DS34C87 CMOS Quad TRI-STATE®
Differential Line Driver
~eneral

Description

The DS34C87 is a quad differential line driver designed for
digital data transmission over balanced lines. The DS34C87
meets all the requirements of EIA standard RS-422 while
retaining the low power characteristics of CMOS. This enables the construction of serial and terminal interfaces while
maintaining minimal power consumption.
The DS34C87 accepts TTL or CMOS input levels and translates these to RS-422 output levels. This part uses special
output circuitry that enables the individual drivers to power
down without loading down the bus. The DS34C87 also includes special power up and down circuitry which will TRISTATE the outputs during power up or down, preventing
spurious glitches on its outputs. This device has separate
enable circuitry for each pair of the four drivers. The
DS34C87 is pin compatible to the DS3487.

All inputs are protected against damage due to electrostatic
discharge by diodes to Vee and ground.

Features
•
•
•
•
•
•
•
•

TTL input compatible
Typical propagation delays: 8 ns
Typical output skew: 0.5 ns
Outputs won't load line when Vee = OV
Meets the requirements of EIA standard RS-422
Operation from single 5V supply
TRI-STATE outputs for connection to system buses
Low quiescent current

Connection and Logic Diagrams
I()o-~D

Dual-In-Line Package
INPUT

INPUT A

OUTPUTS A

{...;;,,0I---'

...-

INPUT 0

NON·INVERTING

..... OUTPUTS

I()o--t~o

INVERTING

OUTPUT
CONTROL

AlB CONTROL

TLlF/8S76-2

OUTPUTS B{

Truth Table

INPUT B

TL/F/8S76-1

Top View

Order Number DS34C87J,
DS34C87N or DS34C87M
See NS Package Number
J16A, M16A or N16A

Input

Control
Input

Non-Inverting
Output

Inverting
Output

H
L
X

H
H
L

H
L

L
H

Z

Z

= Low logic state
H = High logic state
L

x=
Z

Irrelevant

= TRI-STATE (high impedance)

For complete specifications
see the Interface Databook.

1-58

Absolute Maximum Ratings

c
en
Co)

(Notes 1 & 2)

,r.:..

If MilitaryI Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Supply Voltage (Vee)

Supply Voltqge (Vee)
DC Input or Output Voltage
(VIN, VOUT)
Operating Temperature Range (TA)

-1.5 to Vee + 1.5V
-0.5 to 7V

Clamp Diode Current (11K, 10K)
DC Output Current, per pin (lOUT)
DC Vee or GND Current (Ice)
Storage Temperature Range (TSTG)
Power Dissipation (Note 3) (Po)
Lead Temperature (T d (Soldering 4 sec)

±20mA

Input Rise or Fall Times (tr, tf)

Min
4.50

Max
5.50

Units
V

0

Vee

V

-40

+85
500

°C
ns

±150 rnA
- 65°C to + 150°C
500mW
260·C
5V ± 10% (unless otherwise specified) (Note 4)

Parameter

Conditions

Min

Typ

Max

Units

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

VOH

High Level Output
Voltage

VIN = VIH or VIL.
lOUT = -20 rnA

VOL

Low Level Output
Voltage

VIN = VIH or VIL.
lOUT = 48 rnA

VT

Differential Output
Voltage

RL=100n
(Note 5)

IVTI-lvTI

Difference In
Differential Output

RL=100n
(Note 5)

0.4

V

Vas

Common Mode
Output Voltage

RL=100n
(Note 5)

3.0

V

IVos-vosl

Difference In
Common Mode Output

RL = 100 n
(Note 5)

0.4

V

liN

Input Current

VIN = Vee, GND, VIH, or VIL

±1.0

/LA

lee

Quiescent Supply
Current

lOUT = O/LA,
VIN = Vee or GND
VIN = 2.4V or 0.5V (Note 6)

102

TRI-STATE Output
Leakage Current

VOUT = Vee or GND
Control = VIL

Ise

Output Short
Circuit Current

VIN = Vee or GND
(Note 7)

V

2.0
0.8

V

2.5
0.5

V
V

2.0

200
0.8
±0.5
-30

V

/LA
rnA
±5.0

/LA

-150

rnA

100
Output Leakage Current
Vee = OV
VOUT = 6V
/LA
-100
Power Off
VOUT = -0.25V
/LA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified. all voltages are referenced to ground. All currents into device pins are positive; all currents out of device pins are negative.
Note 3: Power Dissipation temperature derating-plastic "N" package: -12 mWfOC from 65'C to 85'C.
ceramic "J" package: -12 mW fOC from 1ao'c to 125'C.
Note 4: Unless otherwise specified, min/max limits apply across the -40'C to 85'C temperature range. All typicals are given for Vee = 5V and TA = 25'C.
Note 5: See EIA Specification RS-422 for exact test conditions.
Note 6: Measured per input. All other inputs at Vee or GND.
Note 7: Only one output at a time should be shorted.

10FF

......

±150 rnA

DC Electrical Characteristics Vee =
Symbol

Operating Conditions

-0.5 to 7.0V

DC Voltage (VIN)
DC Output Voltage (VOUT)

o
CO

I

1-59

III

Switching Characteristics Vee =
Symbol

5V

± 10%, tr

Parameter

= tf =

Conditions

Propagation Delay
Input to Output

S10pen

Skew

(Note 8)

S10pen

tTLH, tTHL

Differential Output Rise
And Fall Times

S10pen

tpZH

Output Enable Time

tpZL
tpHZ

tpLH, tpHL

6 ns (Figures 1,2,3, and 4) (Note 4)
Typ

Min

Max

Units

8

ns

0.5

ns

8

ns

S1 Closed

13

ns

Output Enable Time

S1 Closed

15

ns

Output Disable Time (Note 9)

S1 Closed

9

ns

tpLZ

Output Disable Time (Note 9)

S1 Closed

10

ns

CPO

Power Dissipation
Capacitance (Note 10)

100

pF

CIN

Input Capacitance

10

pF

Skew is defined as the difference in propagation delays between complementary outputs at the 50% pOint.
Note 9: Output disable time is the delay from ENABLE or ENABLE being switched to the output transistors turning off. The actual disable times are less than
indicated due to the delay added by the RC time constant of the load.
Note 10: CPO determines the no load dynamic power consumption, Po = Cpo V2ee f + lee Vee. and the no load dynamic current consumption, Is = CPO Vee f +
Ice·
Note 8:

AC Test Circuit and Switching Time Waveforms

INPUT
-

~ == 1-~ .

1.5V
R1

CI

D

:

c3f

R3

51

J

R2

-L

-

Note: C1

= C2 = C3 = 40 pF, R1 = R2 = 50n, R3 = 500n

FIGURE 1. AC Test Circuit

1-60

TL/F/8576-3

AC Test Circuit and Switching Time Waveforms
INPUT JV - - - . - - - - - ' " ' '=IMHz,II,,6n$,
1,JV
1,,,6n$ OV

(Continued)

ENABLE INPUT
f=1 t.lHz, tr:S 6 ns,
t, :S 6 ns

3.0V ---,.----~
O.OV
1.5V

OUTPUT

VOL--+---'I
VOH - - + - - " " ,
1.5V
TL/F/8576-4
TL/F/8576-5

FIGURE 2. Propagation Delays

FIGURE 3. Enable and Disable Times

JV
INPUT

OV

OUTPUT
(DIFFERENTIAL)

Input pulse; f

=1MHz, 50%; tr =t,,, 6ns.

TL/F/8576-7

FIGURE 4. Differential Rise and Fall Times

Typical Applications

•

Two-Wire Balanced System, RS-422

DATA
OUTPUT

TL/F/8576-8

1-61

r....
co

~ ~National
~ Semiconductor
r....

e
co

~ DS35F87/DS34F87
~ RS-422 Quad Line Driver with TRI-STATE® Outputs
General Description

Features

The DS34F87/DS35F87 RS-422 Quad Line Driver features
four independent driver chains which comply with EIA Standards for the electrical characteristics of balanced voltages
digital interface circuits. The outputs are TRI-STATE structures which are forced to a high impedance state when the
appropriate output control lead reaches a logic zero condition. All input leads are PNP buffered to minimize input loading for either logic one or logic zero inputs. In addition, internal circuitry assures a high impedance output state during
the transition between power-up and power-down.

•
•
•
•
•
•
•
•

The DS34F87/DS35F87 offers improved performance due
to the use of state-of-the-art L-FAST bipolar technology.
The L-FAST technology allows for higher speeds and lower
currents by utilizing extremely short gate delay times. Thus,
the DS34F87/DS35F87 features lower power, extended
temperature range, and improved specifications.

Four independent driver chains
TRI-STATE outputs
PNP high impedance inputs
Fast propagation time
TTL compatible
Single 5.0V supply voltage
Output rise and falls times less than 20 ns
Lead compatible and interchangeable with MC3487 and
DS3487
• Extended temperature range

The DS34F87/DS35F87 offers optimum performance when
used with the DS34F86/DS35F86 Quad Line Receiver.

Block and Connection Diagrams
16-Lead DIP and 50-16 Package
NON-INVERTING
OUTPUTS

IN A

INVERTING

{---t~,..

OUTA-............
ALB
CONTROL
OUTB

TL/F/9618-2

FIGURE 1

INB{

GND
TL/F/9618-1

Top View

Function Table
Input
H
L
X
H = High Level
L = Low Level
X = Immaterial
Z = High Impedance (off)

Order Number DS34F87J or DS35F87J
See NS Package Number J 16A *

(Each Driver)

Output

Enable
H
H
L

V

Z

H
L

L
H

Z

Z

Order Number DS34F87M
See NS Package Number M16A
Order Number DS34F87N
See NS Package Number N16A
·For most current package information, contact product marketing.

1-62

Absolute Maximum Ratings

c
en
w

(Note 1)

U1

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range
Ceramic DIP
Molded DIP and SO-16

Operating Range

265°C
8.0V

Input Voltage

5.5V

DS34F87
Temperature
Supply Voltage

O°Cto + 70°C
4.75V to 5.25V

DS35F87
Temperature
Supply Voltage

- 55°C to + 125°C
4.5V to 5.5V

Electrical Characteristics over operating range, unless otherwise specified (Notes 2 & 3)
Symbol

Parameter

Conditions

Min

Typ

Max
0.8

Vil

Input Voltage LOW

VIH

Input Voltage HIGH

III

Input Current LOW

Vil = 0.5V

-200

IIH

Input Current HIGH

VIH = 2.7V

+50

VIH = 5.5V

+100

Units
V
V

2.0

JJ-A
JJ-A

VIC

Input Clamp Voltage

11= -18mA

-1.5

V

VOL

Output Voltage LOW

10l = 48 mA

0.5

V

VOH

Output Voltage HIGH

10H = -20 mA

2.5

los

Output Short Circuit Current (Note 4)

VIH = 2.0V

-40

-140

mA

ioz

Output Leakage Current Hi-Z State

Vil = 0.5V, Vil (z) = 0.8V

±100

VIH = 2.7V, Vil (z) = 0.8V

± 100

VOH = 6.0V, Vcc = OV

+100

VOL = -0.25V, Vcc = OV

-100

10l(aff)

Output Leakage Current
Power Off

Vos-Vos

Output Offset
Voltage Difference (Note 5)

VOD

Output Differential Voltage (Note 5)

~VOD

Output Differential
Voltage Change

Iccx

Supply Current

Icc

V

±0.4

JJ-A

JJ-A

V
V

2.0
±0.4

V

Control Leads Gnd

50

mA

Control Leads 2.0V

40

mA

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified min/max limits apply across the - 55'C to
the DS34F87. All typicals are given for Vee = 5V and T A = 25'C.

CO

.......
.......

c
en
w
~

'TI

CO

.......

300°C

Supply Voltage

1500 mW
1040 mW
960mW

"Derate cavity package 10 mWI'C above 25'C; derate molded DIP package
8.3 mW/'C; derate SO package 7.7 mW'C above 25'C.

- 65°C to + 175°C
- 65°C to + 150°C

Lead Temperature
Ceramic DIP (soldering, 60 sec.)
Molded DIP and SO-16
(soldering, 10 sec.)

'TI

Maximum Power Dissipation' at 25°C
Cavity Package
Molded Package
SO Package

+ 125'C temperature range for the DS35F87 and across the O'C to + 70'C range for

Note 3: All currents into the device are positive; all currents out of the device pins are negative. All voltages are referenced to ground unless otherwise specified.
Note 4: Only one output at a time should be shorted.
Note 5: Refer to EIA RS-422/3 for exact conditions.

1-63

......

co
u..
~

Switching Characteristics Vee =

5.0 V, TA = 25°C

('t)

~

Symbol

r:::
co

tpHL

~

Max

Units

High to Low Input

20

ns

Low to High Input

15

ns

Output Transition
Times-Differential

High to Low Input

15

ns

Low to High Input

15

ns

Propagation Delay

RL = 200, CL = 50 pF

25

ns

RL = 200, CL = 50 pF

25

ns

tpZH(E)

RL =

25

ns

tpZL(E)

RL = 200, CL = 50 pF

25

ns

Load = (Note 1)

4.5

ns

Parameter

Min

Conditions

Propagation Delay Times

tpLH

Typ

('t)

CJ)

C

tTHL

1--'-'-=----1

tTLH

Control to Output

tpLZ(E)

SKEW

Output to Output

00,

CL = 50 pF

Note 1: CL = SO pF, VI = 1.SV to Vo = 1.SV, VPULSE = OV to +3.0V.

Parameter Measurement Information
TO SCOPE
OUT

TO SCOPE 3.0V or GND
IN
INPUT

,......

"-~

, .....

~~--o()

~

...._ _ _ _ _..

PULSE:~
GENERATOR
.n.

=

NON-INVERTING C 15 pF-....
L
OUTPUT
(Note 2).1.

:.:~ 50n

(Note 1)

OPEN FOR
tPZL(E)
TEST ONLY

~

INVERTING
OUTPUT

i'..

200n

G---I\III'v- +sV

"

-~

~, (Note

3)

-~

~,.
-~

..

..r

OPEN F'OR
tpZL(E)
TEST ONLY
TLlF/9618-3

FIGURE 2. TRI-STATE Enable Test Circuit and Waveforms

CONTROL
INPUT

3.0V

)~1.5V

CONTROL
INPUT
OV

l-

tpHZ(E)-

t
~

I->KJ'

OUT

tPLZ(E) OUT

O.sV

)c

VOH

3.0V

11.5V

-

OUT

OV

itPZL(E)

\.... ,

VOH
1.5V

:Sl.sV

-

....,1.SV
OUT

VOL
OV

VOL
OV
I-tpZH(E)
VOH
)'l.1.5V
VOL
OV

TL/F/9618-4

TL/F/9618-5

FIGURE 2a

FIGURE 2b

1·64

Parameter Measurement Information

c
en
w

(Continued)

U1

"T1
TO SCOPE

ex»
......

TO SCOPE

om

~

.......

5.0V

c
en
w
~

"T1

ex»
......

=

CL 15 pF

(Note 2),I

(Note 4)

TL/F/9616-6

IN

OUT

OUT

VOL
-------------------------OV

TLIF/9616-7

FIGURE 3. Propagation Delay Times Input to Output Waveforms and Test Circuit

TO SCOPE
IN

RL

~~~~~T

200.n (DIFFERENTIAL)

TL/F/9616-6

,.._---"'\.-----3.0V

----OV

OUT
(DIFFERENTIAL) - - - . I J
TL/F/9616-9

FIGURE 4. Output Transition Times Circuit and Waveforms
Note 1: The input pulse is supplied by a generator having the following characteristics: PAR

Zo

=

50n.

Note 2: CL includes probe and jig capacitance.
Note 3: All diodes are IN3064 or equivalent.
Note 4: All diodes are IN914 or equivalent.

1-65

= 1.0 MHz, 50% duty cycle, tTLH = tTHL

:$;

5.0 ns (10% to 90%),

~National

~ Semiconductor
OS3587/0S3487 Quad TRI-STATE® Line Driver
General Description

Features

National's quad RS-422 driver features four independent
driver chains which comply with EIA Standards for the electrical characteristics of balanced voltage.Jiigital interface circuits. The outputs are TRI-STATE structures which are
forced to a high impedance state when the appropriate output control pin reaches a logic zero condition. All input pins
are PNP buffered to minimize input loading for either logic
one or logic zero inputs. In addition, internal circuitry assures a high impedance output state during the transition
between power up and power down.

•
•
•
•
•
•
•
•
•
•

Four independent driver chains
TRI-STATE outputs
PNP high impedance inputs (PIA compatible)
Power up/down protection
Fast propagation times (typ 10 ns)
TTL compatible
Single 5V supply voltage
Output rise and fall times less than 20 ns (typ 10 ns)
Pin compatible with DS8924 and MC3487
Output skew-2 ns typ

Block and Connection Diagrams
Dual-In-Line Package

INPUT A
NON·INVERTING
OUTPUTS A {
INPUT

OUTPUTS
AlB CONTROL

INVERTING

OUTPUTS B{

OUTPUT
CONTROL
TL/F/5780-1

INPUT B

TL/F/5780-2

Top View
Order Number DS3587J, DS3487J,
DS3487M or DS3487N
See NS Package Number J16A, M16A or N16A

Truth Table
Input

H
L
X
L

=

Control
Input

Non-Inverter
Output

H
H

H

L

L

L

Z

H
Z

Low logic state

H = High logic state
X

=

Irrelevant

Z = TRI·STATE (high impedance)

1-66

Inverter
Output

c
en
w

Absolute Maximum Ratings (Note 1)

U1

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

SO Package

Supply Voltage

Operating Conditions

Lead Temperature (Soldering, 4 seconds)

8V

Input Voltage

1051 mW

Storage Temperature

- 65°C to + 150°C

Maximum Power Dissipation· at 25°C
Cavity Package
1509mW
Molded DIP Package
1476mW
"Derate cavity package 10.1 mWI'C above 25'C; derate DIP molded package 11.9 mW I'C above 25'C. Derate SO package 8.41 mW I'C above 25'C

260°C

c
'"
en
CO

w

~

Min

Max

Units

Supply Voltage, Vcc
083587
083487

4.5
4.75

5.5
5.25

V
V

Temperature (TA)
083587
083487

-55
0

+125
+70

°C
°C

5.5V

Electrical Characteristics (Notes 2, 3, 4 and 5)
Symbol

Parameter

VIL

Input Low Voltage

VIH

Input High Voltage

IlL

Input Low Current

IIH

Input High Current

Conditions

V

-200

,..,A

VIH = 2.7V

50

,..,A

VIH = 5.5V

100

,..,A

Input Clamp Voltage

ICL = -18 mA

Output Low Voltage

10L = 48 rnA

VOH

Output High Voltage

10H = -20mA

los

Output Short-Circuit Current

loz

Output Leakage Current (TRI-STATE)

-1.5

V

0.5

V

-140

mA

Vo = 0.5V

-100

,..,A

Vo = 5.5V

100

,..,A

Vo = 6V

100

,..,A

-100

,..,A

2.5

V

-40

Output Leakage Current Power OFF

Vcc = OV

Vo = -0.25V
Ivos-vosl

Difference in Output Offset Voltage

VT

Differential Output Voltage

IVTI-'hl

Difference in Differential Output Voltage

Icc

Power Supply Current

0.4
2.0

Switching Characteristics Vcc =
tpHL

Units

0.8

V

VIL = 0.5V

VOL

Symbol

Max

2.0

VCL

10FF

Typ

Min

V
V

0.4

V

Active

50

80

mA

TRI-STATE

35

60

mA

5V, TA = 25°C

Parameter

Conditions

Input to Output

Min

Typ

Max

Units

10

15

ns

tpLH

Input to Output

10

15

ns

tTHL

Differential Fall Time

10

15

ns

tTLH

Differential Rise Time

10

15

ns

tpHZ

Enable to Output

RL = 2000., CL = 50 pF

17

25

ns

tpLZ

Enable to Output

RL = 2000., CL = 50 pF

15

25

ns

tpZH

Enable to Output

RL =

11

25

ns

00,

CL = 50 pF, S1 Open

15
25
ns
Enable to Output
RL = 2000., CL = 50 pF, S2 Open
tPZL
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified min/max limits apply across the O'C to + 70'C range for the DS3487. All typicals are given for Vce = 5V and TA = 25'C.
Note 3: All currents into device pins are positive, all currents out of device pins as negative. All voltages are referenced to ground unless otherwise specified.
Note 4: Only one output at a time should be shorted.
Note 5: Symbols and definitions correspond to EIA RS-422, where applicable.

1-67

CO

.......

.......

AC Test Circuits and Switching Time Waveforms
5V

INPUT

1.5V

=

CL 50 pF
INCLUDES PROBEI
AND JIG CAPACITANCE

1.5V
TL/F/S7S0-4
Input pulse: f

TL/F/S780-3

=

MHz, 50%; t,

=

t,

~

15 ns.

FIGURE 1. Propagation Delays

CONTROL
INPUT

3V OR OV
CONTROL
INPUT

VOH - - - t -.... 't-=-':::-:-

OUTPUT

1.5V

OUTPUT
VOL-~-+'" t..c..:..r.:....

S1 and S2 closed except as noted.

TL/F/S780-6

CL includes probe and jig capacitance.

Input pulse: f
TL/F/S780-S

Sl

=

S2

= open for tpZL

=

MHz, 50%; t,

=

t,

~

15 ns.

open for tpZH

FIGURE 2. TRI-STATE Enable and Disable Delays

JV
INPUT

\~

~

OV
INPUT

TEM eT2
CURRENT TRANSFORMER
OR EQUIVALENT

90%
OUTPUT
(DIFFERENTIAL)

T-= T-=

CL
15 pF
INCLUDING PROBE
AND JIG CAPACITANCE

tTLH

tTHL
TL/F/S780-S

Input pulse: f
TL/F/S7S0-7

FIGURE 3. Differential Rise and Fall Times

1-68

=

MHz, 50%; t,

= t,

~

15 ns.

c
en
.....
0')

~National

o

~ Semiconductor

........

OS1603/0S3603 TRI-STATE® Dual Receivers

o

w

c
en
w
0')

w

General Description
The OS1603/0S3603 are dual differential TRI-STATE line
receivers designed for a broad range of system applications. They feature a high input impedance and low input
current which reduces the loading effects on a digital transmission line, making them ideal for use in party line systems
and general purpose applications like transducer preamplifiers, level translators and comparators.

The OS1603/0S3603 are pin compatible with the OS75107,
OS75108 and OS75208 series of dual line receivers.

Features
• Oiode protected input stage for power "OFF" condition
• 17 ns typ high speed
• TTL compatible
• ± 25 mV input sensitivity
• ± 3V input common-mode range
• High-input inpedance with normal Vee, or Vee = OV
• Strobes for channel selection
• TRI-STATE outputs for high speed buses

The receivers feature a ± 25 mV input sensitivity specified
over a ± 3V common mode range. Input protection diodes
are incorporated in series with the collectors of the differential stage. These diodes are useful in applications that have
multiple Vee+ supplies or Vee+ supplies that are turned
off thus avoiding signal clamping. In addition, TTL compatible strobe and control lines are provide for flexibility in the
application.

Connection Diagram
Dual-In-Line Package
vcc-

INPUT

INPUT

lA

lB

INPUT
2A

NC

INPUT
2B

NC

OUTPUT
2V

OUTPUT

STROBE

OISABLE

IV

lG

0

Top View
Order Number DS1603J, DS3603J or DS3603N
See NS Package Number J 14A or N 14A

1-69

STROBE
2G

GNO
TLlF/5781-2

C")

o

CD
C")

U)

c

"C")

o

CD
,..
U)

c

Absolute Maximum Ratings

(Note 1)

If Military!Aerospace specified devices are required,

Supply Voltage (Vcc+)

±6V

Common Mode Input Voltage

- 65°C to

+ 150°C

Maximum Power Dissipation" at 25°C
1308 mW
Cavity Package
1207 mW
Molded Package
Lead Temperature (Soldering, 4 sec)
260°C
"Derate cavity package B.7 mWrC above 2S'C; derate molded package
9.7 mWrC above 2S'C.

7V
-7V

Supply Voltage (Vcc-)
Differential Input Voltage

5.5V

Strobe Input Voltage
Storage Temperature Range

contact the National Semiconductor Sales Office!
Distributors for availability and specifications.

±5V

Operating Conditions
051603

053603

Min

Nom

Max

Min

Nom

Max

4.5V

5V

5.5V

4.75

5V

5.25V

Supply Voltage Vcc-

-4.5V

-5V

-5.5V

-4.75

-5V

-5.25V

Operating Temperature Range

-55°C

to

+ 125°C

O°C

to

+ 70°C

Supply Voltage Vcc +

Electrical Characteristics TMIN :0; TA:O; TMAX (Notes 2, 3)
Symbol

Parameter

Conditions

IIH

High Level Input Current
into 1A, 1B, 2A or 2B

Vcc+ = Max, Vcc- = Max,
VID = 0.5V, VIC = -3V to 3V

IlL

Low Level Input Current
into 1A, 1B, 2A or 2B

Vcc+ = Max, Vcc- = Max,
VID = -2V, VIC = -3V to 3V

IIH

High Level Input Current
into 1G, 2G or 0

Vcc+ = Max
Vcc- = Max

Low Level Input Current
into 0

Vcc+ = Max, Vcc- = Max,
VIL(D) = O.4V

IlL
IlL

VOH

VOL

laD

Max

Units

30

75

/-LA

-10

/-LA

VIH(S) = MaxVcc+

/-LA

1

mA

-1.6

mA

VIH(D) = 2V

/-LA

VIL(D) = 0.8V

-1.6

mA

High Level Output Voltage

Vcc+ = Min, Vcc- = Min,
ILOAD = -2 mA, VID = 25 mV,
VIL(D) = 0.8V, VIC = -3V to 3V

2.4

V

Vcc+ = Min, Vcc- = Min,
ISINK = 16 mA, VID = - 25 mV,
VIL(D) = 0.8V, VIC = -3V to 3V
Vcc+ = Max,
Vcc- = Max,
VIH(D) = 2V

40

-40

Vcc+ = Max,
Vcc- = Max,
VIL(G) = O.4V

Output Disable Current

Typ

VIH(S) = 2.4V

Low Level Input Current
into 1G or 2G

Low Level Output Voltage

Min

0.4

V

VOUT = 2.4V

40

/-LA

VOUT = O.4V

-40

/-LA

-70

mA

los

Short Circuit Output Current

Vcc+ = Max, Vcc- = Max,
VIL(D) = 0.8V (Note 4)

ICCH+

High Logic Level Supply
Current from Vcc+

Vcc+ = Max, Vcc- = Max,
VID = 25 mV, TA = 25°C

28

40

mA

ICCH-

High Logic Level Supply
Current from Vcc-

Vcc+ = Max, Vcc- = Max,
VID = 25 mV, TA = 25°C

-8.4

-15

mA

-18

Input Clamp Voltage
Vcc+ = Min, Vcc- = Min,
-1
-1.5
V
on G orO
liN = -12 mA, TA = 25°C
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified min/max limits apply across the -SS'C to + 12S'C temperature range for the D81603 and across the O'C to + 70'C range for
the D83603. All typical values are for TA = 2S'C and Vee = SV.
Note 3: All current into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown as
max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.

VI

1-70

c

Switching Characteristics

Vcc+

= 5V, Vcc- = -5V, TA = 25°C

Symbol

Parameter

tpLH(D)

Propagation Delay Time, Low-toHigh Level, from Differential
Inputs A and B to Output

RL

Propagation Delay Time, High-toLow Level, from Differential
Inputs A and B to Output

RL

Propagation Delay Time, Low-toHigh Level, from Strobe Input G
to Output

RL

Propagation Delay Time, High-toLow Level, from Strobe Input G
to Output

RL

t1H

Disable Low-to-High to Output
High to Off

RL

tOH

Disable Low-to-High to Output
Low to Off

tH1
tHo

tpHL(D)

tpLH(S)

tpHL(S)

Min

Conditions

Typ

Max

Units

17

25

ns

= 3900., CL = 50 pF, (Note 1)

0')

25

ns

10

15

ns

8

15

ns

= 3900., CL = 5 pF

20

ns

RL

= 3900., CL = 5 pF

30

ns

Disable High-to-Low to Output
Off to High

RL

= 1k to OV, CL = 50 pF

25

ns

Disable High-to-Low to Output
Off to Low

RL

= 3900., CL = 50 pF

25

ns

+ 100 mV to

c
en
w
o
w

= 3900., CL = 50 pF, (Note 1)
17

Note 1: Differential input is

en
......
0')
o
w
......

= 3900., CL = 50 pF
= 3900., CL = 50 pF

-100 mV pulse. Delays read from 0 mV on input to 1.5V on output.

Typical Application
Line Receiver Used in a Party-Line or Data-Bus System
RECEIVERS

,

i

)

I )

I

STROBE

-

~

•••• Zo/2
••

r.
- .•

r--.

I I

\I

\I

\I

\ I •.~•Zo/2

\I

A

A

1\

1\
II

A

1\

1\

I I

I I

I I

'-"

'-"

'-'

V\

,nrI

TWISTED·PAIR
TRANSMISSION
LINE

/

II

II

•

-

II
\I

~

~ Zo/2

~

NHIB

gr
V\

"

\

1\

•

-n
.

:. Zo/2
~

-=

Line receivers are
0575107/0575108
or OS3603
Line drivers are
5N751 091 J-LA7511 0/057511 0
or OS8831

,)T

n

i

DRIVERS
TL/F/57Bl-3

1-71

Schematic Diagram

(Note 1)

051603/053603
Vee + ~---4~~t-------~---t~~t---~------------__~----__~------~--------~

INPUT B

INPUT A

OUTPUT

0----+----1
~-----+--~~----------~--~----_4~OGNO

3k

.....---------il~-------_+_---+--f~

ADD 2o--i-<>-r---e-

10-1--1-0+-00() OUTPUT
ADD 4o-......~--t:;..;

-IN A

+IN A

OUT A

STB

OUT C

+IN C

-IN C

GND

TL/F/5782-1

Top View

TL/F/5782-2

Order Number DS1650J, DS1652J,
DS3650J, DS3652J, DS3650M,
DS3652M, DS3650N or DS3652N
See NS Package Number J16A, M16A, or N16A

Wired "OR" Data Selecting Using TRI-STATE Logic

Truth Table
Output
Input
VD;:: 25 mV
-25 mV :s;: VID :s;: 25 mV

VID:S;: -25 mV

Strobe

D516501

D516521

OS3650

OS3652

L

H

Open

DATA

H

Open

Open

LINES

L

X

X

H

Open

Open

L

L

L

H

Open

Open

1-<:.........+4-+--0 DATA

I-c.........*-+-+--o OUTPUT

L = Low Logic State
H

Open = TRI·STATE
= High Logic State X = Indeterminate State

lo----I--f...<>-f--I-<>-+1-+4

TL/F/5782-3

1-73

.......
C

en
Co.)
0')

01
I\)

N

in

CD
C")

U)

C

.......
C
in

CD

C")

U)

C

.......
N

in

,....

CD

U)

If Military! Aerospace specified devices are required,
contact the National Semiconductor Sales Office!
Distributors for availability and specifications.
Power Supply Voltages
Vcc
VEE
Differential-Mode Input Signal Voltage
Range, VIOR

±6.0 Voc

Common-Mode Input Voltage Range, VICR

C

Strobe Input Voltage, VI(S)

CD

,....

Storage Temperature Range

U)

Lead Temperature (Soldering, 4 seconds)

in

C

Supply Voltage, Vcc
OS1650,OS1652
OS3650, OS3652
Supply Voltage, VEE
OS1650,OS1652
OS3650, OS3652
Operating Temperature, T A
OS1650,OS1652
OS3650, OS3652
Output Load Current, 10L
Oifferential-Mode Input
Voltage Range, VIOR
Common-Mode Input
Voltage Range, VICR
Input Voltage Range
Input to GNO, VIR

+7.0Voc
-7.0Voc

C

.......

Operating Conditions

Absolute Maximum Ratings (Note 1)

±5.0Voc
5.5 Voc

- 65°C to + 150°C

Maximum Power Oissipation* at 25°C
Cavity Package
Molded OIP Package
SO Package

260°C
1509 mW
1476 mW
1051 mW

"Derate cavity package 10.1 mWI'C above 25°C; derate molded DIP package 11.6 mW toc above 25°C; derate SO package 6.41 mW I'C above 25°C.

Min

Max

Units

4.5
4.75

5.5
5.25

Voc
Voc

-4.5
-4.75

-5.5
-5.25

Voc
Voc

-55
0

+125
+70
16

°C
°C
mA

-5.0

+5.0

Voc

-3.0

+3.0

Voc

-5.0

+3.0

VOC

Electrical Characteristics
(Vcc = 5.0 Voc, VEE = - 5.0 Voc, Min ~ T A ~ Max, unless otherwise noted) (Notes 2 and 3)

Symbol
VIS

Max

Units

±25.0

mV

75

,...A

-10

,...A

VIH(S) = 2.4V,
OS1650,OS1652

100

,...A

VIH(S) = 2.4V,
OS3650, OS3652

40

,...A

1

mA

-1.6

mA

Conditions

Parameter
Input Sensitivity, (Note 5)
(Common-Mode Voltage Range =
-3V ~ VIN ~ 3V)

Min

Min ~ Vcc ~ Max
Min ~ VEE ~ Max

IIH(I)

High Level Input Current to
Receiver Input

(Figure 5)

IIL(I)

Low Level Input Current to
Receiver Input

(Figure 6)

IIH(S)

High Level Input Current to
Strobe Input

(Figure 3)

VIH(S) = Vcc

Typ

IIL(S)

Low Level Input Current to
Strobe Input

VOH

High Level Output Voltage

(Figure 1)

OS1650,OS3650

ICEX

High Level Output Leakage Current

(Figure 1)

OS1652, OS3652

250

VOL

Low Level Output Voltage

(Figure 1)

OS3650, OS3652

0.45

OS1650,OS1652

0.50

VIH(S) = 0.4V

V

2.4

V

los

Short-Circuit Output Current (Note 4)

(Figure 4)

OS1650/0S3650

-70

mA

10FF

Output Oisable Leakage Current

(Figure 7)

OS1650

100

,...A

OS3650

40

,...A

1-74

-18

,...A

c
en

Electrical Characteristics
(Vcc

= 5.0 Voc, VEE = -

Symbol

~

0)

5.0 Voc, Min ~ T A ~ Max, unless otherwise noted) (Notes 2 and 3) (Continued)

Parameter

Conditions

ICCH

High Logic Level Supply Current
from Vcc

(Figure 2)

IEEH

High Logic Level Supply Current
from VEE

(Figure 2)

Min

U1

o

Typ

Max

Units

45

60

mA

-17

-30

.........

c
en
.....
0)

U1

N
.........

mA

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.

C

en
w

0)

U1

o

.........

for the

c
en
w

Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.

U1

Note 2: Unless otherwise specified, minImax limits apply across the O'C to + 70'C range for the 053650, 053652 and the - 55'C to
051650,051652. All typical values are for TA = 25'C, Vee = 5V and VEE = -5V.

+ 125'C range

Note 4: Only one output at a time should be shorted.
Note 5: A parameter which is of primary concern when designing with line receivers is, what is the minimum differential input voltage required as the receiver input
terminals to guarantee a given output logic state. This parameter is commonly referred to as threshold voltage. It is well known that design considerations of
threshold voltage are plagued by input offset currents, bias currents, network source resistances, and voltage gain. As a design convenience, the 051650, 051652
and the 053650, 053652 are specified to a parameter called input sensitivity (VIS)' This parameter takes into consideration input offset currents and bias currents
and guarantees a minimum input differential voltage to cause a given output logic state with respect to a maximum source impedance of 2000 at each input.

Switching Characteristics (Vcc = 5 Voc, VEE =
Symbol

Parameter

tpHL(O)

High-to-Low Logic Level Propagation
Oelay Time (Oifferentiallnputs)
Low-to-High Logic Level Propagation
Oelay Time (Oifferentiallnputs)

tpOH(S)

TAl-STATE to High Logic Level
Propagation Oelay Time (Strobe)

tpHO(S)

High Logic Level to TAl-STATE
Propagation Oelay Time (Strobe)

= 25°C unless otherwise noted)
Typ

Max

Units

OS1650/0S3650

21

25

ns

OS1652/0S3652

20

25

ns

OS1650/0S3650

20

25

ns

OS1652/0S3652

22

25

ns

OS1650/0S3650

16

21

ns

OS1650/0S3650

7

18

ns

Conditions

(Figure 8)
tpLH(O)

-5 Voc, TA

Min

(Figure 9)

tpOL(S)

TAl-STATE to Low Logic Level
Propagation Oelay Time (Strobe)

OS1650/0S3650

19

27

ns

tpLO(S)

Low Logic Level to TAl-STATE
Propagation Oelay Time (Strobe)

OS1650/0S3650

14

29

ns

tpHL(S)

High-to-Low Logic Level Propagation
Oelay Time (Strobe)

OS1652/0S3652

16

25

ns

OS1652/0S3652

13

25

ns

tpLH(S)

(Figure 10)

Low-to-High Logic Level Propagation
Oelay Time (Strobe)

1-75

0)

N

~

Ln
CD
CO)

en
c
......

r---------------------------------------------------------------------------------------~

Electrical Characteristic Test Circuits

o

",I

VI"

Ln
CD
CO)

V2'"

:2
-3

O.8V"'-

:4
- 5

en

c
......
~

Ln
CD

,....
o

Ln
CD

,....

~

12
H>-+-+-OMIN VEE

DSI6521

DS3652

~
10

7

r

V4

en
c

~
14_

DSI6501
DS3650,

~

V3

en
c
......

16
H>---OMIN Vee

~

DS16521

~~~' \~~
leEX

II!

±

V'H OR VOl

DSI6501
DSJ650 "::'

TLlF/5782-4

V1

VOH

V3

V4

0516501

0516521

0516501

0516521

0516501

0516521

0516501

0516521

053650

053652

053650

053652

053650

053652

053650

053652

+2.975V
-3.0V

+3.0V
-2.975V
+2.975V
-3.0V

ICEX

VOL

V2

+3.0V
-2.975V

+3.0V

GND

GND

-3.0V

+3.0V
-2.975V

+3.0V
-2.975V

+2.975V
-3.0V

+2.975V
-3.0V

11
-0.4 rnA
-0.4 rnA

+3.0V

GND

GND

-3.0V

GND

GND

+3.0V

+3.0V

-3.0V

-3.0V

GND

GND

+16rnA
+16rnA

Channel A shown under test. Other channels are tested similarly.

FIGURE 1. ICEX, VOH and VOL

16
15-

" I

3V~

~
~
_4

ICCH
16

..... 1
-2

-0;
e>7
~

~7

*

-

8

A

MAX Vee

15:
14-

DSI6501
DSJ650,
DS16521
DSJ652

r,;o-

r,;o'""

r,;o
1'-

0+

IEEH
A

IIHORIIl,t

~
~7

VIH(S) OR _

~

MAX VEE
VIL(S)

~

o:!-

14-

DS16501
DS3650,
DS16521
DS3652

-;;0~
,,~
~

"MAX
-Vee
JV

,.MAX
-VEE

-:.:
TL/F/5782-6

TL/F/5782-5

FIGURE 3. IIH(S) and IIL(S)

FIGURE 2. ICCH and IEEH

1-76

Electrical Characteristic Test Circuits
16

en
U1
c
......

MAX

C

Vee

25mV

VI
3V

D.BV

c
rn
.....

(Continued)

OS1650/
OS3650

VI-2V

MAX

3V

VEE

16

MAX

15

Vee

rn
.....
en

U1
N

......

OS1650/
OS3650,
OS16521
083652

C

MAX
VEE

rn
W

en
U1
c
......

c
rn

w
en
U1
N

TL/F/5782-7

TL/F/5782-8

Note: Channel A shown under test, other channels are tested similiarly. Only
one output shorted at a time.

Note: Channel A( -) shown under test, other channels are tested similarly.
Devices are tested with VI from 3V to -3V.

FIGURE 4. lOS

FIGURE 5. IIH

16
3V
VI -2V
VI

16

MAX

15

Vee
2V

3V

OS1650/
OS3650,
OS1652/
OS3652

MAX
Vee

081650/
083650,
OS1652/
OS3652

MAX
VEE

MAX
VEE

TL/F/5782-10

TL/F/5782-9

Note: Output of Channel A shown under test, other outputs are tested
similarly for VI = D.4V and 2.4V.

Note: Channel A( -) shown under test, other channels are tested
similarly. Devices are tested with VI from 3V to -3V.

FIGURE 7. 10FF

FIGURE 6. IlL

1-77

III

N

r.n

(.0
C")

(/)

C

.......
o

AC Test Circuits and Switching Time Waveforms
SV

IOOmV

EIN

r.n

(.0

200mv~
50%

';;:::J: {"""'
OV

C")

(/)

C
.......

EO

N

r.n

I.5Y

VOL

(.0

..-

TLlF/5782-12

(/)

Note: EIN waveform characteristics:
tTLH and tTHL ,.;; IOns measured
10% to 90%
PRR = 1 MHz
Outy Cycle = 50%

C

.......

o

r.n

(.0

..-

(/)

EO

C

TLlF/5782-11

Note: Output of Channel 9 shown under test, other channels are tested similarly.
SI at "A" for OS1652/0S3652
SI at "9" for OS1650/0S3650
CL = 15 pF total for OS1652/0S3652
CL = 50 pF total for OS1650/0S3650

FIGURE 8. Receiver Propagation Dealy tpLH(D) and tpHL(D)
SV
VIo-----.----o~

OV

V2o-------+-.--o~

__- - - - ' " I.SV
EO

VOL

TLlF/5782-14

EO

OV

TL/F/5782-13

Note: Output of Channel 9 shown under test, other channels are tested similiarly.

Eo VOH~~

...
HO_(_S)_____

~

VOH-O.SV
"I.SV

TL/F/5782-15

V1

V2

51

52

CL

tplO(S)

100mV

GND

Closed

Closed

15 pF

tpOl(S)

100mV

GND

Closed

Open

50pF

tpHO(S)

GND

100mV

Closed

Closed

15 pF

tpOH(S)

GND

100mV

Open

Closed

50 pF

EIN3V~O%
OV

"-"'~ ~'''''.
Eo

CL includes jig and probe capacitance.

\:.:SV

VOL

EIN waveform characteristics: tTLH and tTHL ,.;; 10 ns measured 10% to 90%

PRR = 1 MHz

TL/F/5782-16

Outy Cycle = 50%
3V

OV----~·'----------

tpOH(S)
VOH---------r-,------EO

"ov--_J
TL/F/5782-17

FIGURE 9. Strobe Propagation Delay tpLO(S). tpOL(S). tpHO(S) and tpOH(S)

1-78

AC Test Circuits and Switching Time Waveforms

c
en
004

(Continued)

0')

U1

o

5V

100 mV o - - -.......--c~

EIN

390

c
"en

3V~
50%

004

0')

OV

tPLH~S)
tpHL(S)

8 - + - + - - -.....-0 ED
-SV

l'

U1

N

VOH
EO

15 pF
(TOTAL)

"en
C

I.SV

VOL
TL/F/5782-19

o

Note: EIN waveform characteristics:
tTLH and tTHL :5: 10 ns measured 10% and 90%
PRR = 1 MHz
Duty Cycle = 500 ns

TLlF/5782-18

eN

0')

U1

c
"en
eN

0')

Note: Output of Channel B shown under tesl, other channels
are lested similarly.

U1

N

FIGURE 10. Strobe Propagation Delay tpLH(S) and tpHL(S)

Schematic Diagrams
051650/053650
VCCo---~--"""'----'---'---~~~r-~~---'----"""'------------~~

850

OUTPUT
INPUT

[O---+-_...J
t----~->+--o

4k

VEE

GND

4k

o---__.......______' -__' -____

III

-4~----...J

""""4r-------
......

c
en
w

DS1691A/DS3691 (RS-422/RS-423) Line Drivers

en

CD
.....

with TRI-STATE® Outputs
General Description

Features

The DS1691A1DS3691 are low power Schottky TTL line
drivers designed to meet the requirements of EIA standards
RS-422 and RS-423. They feature 4 buffered outputs with
high source and sink current capability with internal short
circuit protection. A mode control input provides a choice of
operation either as 4 independent line drivers or 2 differential line drivers. A rise time control pin allows the use of an
external capacitor to reduce rise time for suppression of
near end crosstalk to other receivers in the cable.
With the mode select pin low, the DS1691A1DS3691 are
dual-differential line drivers with TRI-STATE outputs. They
feature ± 10V output common-mode range in TRI-STATE
mode and OV output unbalance when operated with ± 5V
supply.

• Dual RS-422 line driver with mode pin low, or quad RS423 line driver with mode pin high
• TRI-STATE control for individual outputs
• Short circuit protection for both source and sink outputs
• Outputs will not clamp line with power off or in TRISTATE
• Individual rise mode time control for each output
• 100n transmission line drive capability
• Low Icc and lEE power consumption
RS-422
35 mW/driver typ
RS-423
26 mW/driver typ
• Low current PNP inputs compatible with TTL, MOS and
CMOS
• Pin compatible with AM26LS30

Connection Diagram
With Mode Select LOW
(RS-422 Connection)
16

VCC
15

INPUT A

14

INPUT B/OISABLE
13

MODE SELECT

12

GND

11

INPUT C/DISABLE

lD

INPUT D

With Mode Select HIGH
(RS-423 Connection)

RISE TIME CONTROL A

OUTPUT A

OUTPUT A

INPUT A

OUTPUT B

INPUT B/OISABLE

>----t--

OUTPUT B

RISE TIME CONTROL B

MODE SELECT

----+-

RISE TIME CONTROL B

RISE TIME CONTROL C

GND

RISE TIME CONTROL C

OUTPUT C

INPUT C/DISABLE

OUTPUT D

INPUT D

>----+-

OUTPUT 0

VEE

---+-

RISE TIME CONTROL 0

RISE TIME CONTROL D

VEE

RISE TIME CONTROL A

VCC

OUTPUT C

TLlF/5783-2

TLlF/5783-1

Top View

Top View

Truth Table
Inputs

Operation

Outputs

Mode A(D) 8(C)
RS-422

0
0
0
0

0
0
1
1

0
1
0
1

RS-423

1
1
1
1

0
0
1
1

0
1
0
1

A(D)

8(C)

0
1
TRI-STATE TRI-STATE
1
0
TRI-STATE TRI-STATE
0
0
1
1

0
1
0
1

Order Number DS1691AJ, DS3691J, DS3691M or DS3691N
See NS Package Number J16A, M16A or N16A

1-81

III

..0)
CD
C")

en

c........
IOns

- - III--

TLIF/5783-4

OUT

.~

VEE

TL/F/5783-3

FIGURE 1. Differential Connection
lV

.~

Vce 2

INPUT

IN~

A

eL~

J

5

~

ov

'1' ' '

RL

I

I,:> 10 ns

--

.~
VEE

'j

0.5 VSS/RL

O.IVSST

TLIF/5783-5

----i
FIGURE 2. RS-423 Connection

1-84

t,

I---

~ 11:>10ns

k---- IPOL

t--lpOH

} mal

OUT
OUTPUT

\

I

0.9 VSS";

\

-

0.5 VSS/RL

~
II

t-TL/F/5783-6

(Continued)

c
en
......

2.5v------ 1r - - - - - - - - - - t

CD
......

AC Test Circuits and Switching Time Waveforms

en

>
.......

VCC 2

c

INPUT

en

INPUT
OUTPUT

w
en

OV-----

CD
......

TLIF/5783-7

TLIF/5783-8

FIGURE 3. Rise Time Control for RS-423

"TEK cn CURRENT
TRANSF. OR
EQUIVALENT
OUTPUT

-

Ipll

DUT

TL/F/5783-10
TL/F/5783-9

FIGURE 4. TRI-STATE Delays

Switching Waveforms
INPUT

MODE' 1 UN8A~~~~~~

Vce' 5V VEE' GND
8 ( C I - - - - i . ~---....;.;;.......-=----~ ~----+
MODE' 0

8A~~~~~~
A(DI----{ " ' - - - : : " : " - - - - - - - -

.,,,.,

"~~:::~

Vcc· 5V, VEE • -5V

~"

....
O V - - - - - - - - - -...

1·85

-----+

:

TL/F/5783-11

,....

en
CD
Cf)

en
c.......
<
,....

Typical Rise Time Control Characteristics
Rise Time vs External Capacitor
lk

en

,....

CD

en
c

::l

100

""

w
:::E

i=

w
en

iii:

10

""
~

1
10

100

lk

10k

CAPACITANCE (pF)
TLIF/5783-12

1-86

c
en
-"

~National

en

co

~ Semiconductor

.....
c
en
w

DS1692/DS3692 TRI-STATE® Differential Line Drivers

co
I\)

I\)

General Description

Features

The OS1692/0S3692 are low power Schottky TTL line drivers electrically similar to the OS1691A10S3691 but tested
to meet the requirements of MIL-STO-188-114 (see Application Note AN-216). They feature 4 buffered outputs with
high source and sink current capability with internal short
circuit protection. A mode control input provides a choice of
operation either as 4 independent line drivers or 2 differential line drivers. A rise time control pin allows the use of an
external capacitor to reduce rise time for suppression of
near end cross-talk to other receivers in the cable.
With the mode select pin low, the OS1692/0S3692 are dual
differential line drivers with TRI-STATE outputs. They feature ± 10V output common-mode range in TRI-STATE and
OV output unbalance when operated with ± 5V supply.

• Dual differential line driver or quad single-ended line
driver
• TRI-STATE differential drivers meet MIL-STO-188-114
• Short circuit protection for both source and sink outputs
• Individual rise time control for each output
• 100n transmission line drive capability
• Low Icc and lEE power consumption
Differential mode
35 mWldrivertyp
Single-ended mode
26 mW 1driver typ
• Low current PNP inputs compatible with TTL, MOS and
CMOS

Logic Diagram

(% Circuit Shown)
,.----<:>-~.....- - - - - - - - - - - t
INPUT B (C)

.><:>----00 UTPUT A (0)

10-----_

TRI·STATE~o-~""'---------f----r~

DISABLE

.>C)---oOUTPUT B (C)

' - - - - - 0 CEXT. B (C)
TLlF/5784-1

Connection Diagram

Truth Table
Inputs
16 RISE TIME CONTROL A

VCC
INPUT A

15 OUTPUT A

INPUT B/DISABLE

OUTPUT B
RISE TIME CONTROL B

MODE SELECT

RISE TIME CONTROL C

GND

OUTPUT C

INPUT C/DISABLE

OUTPUT D

INPUT D

RISE TIME CONTROL D

TL/F/5784-2

Top View
Order Number OS1692J, OS3692J or OS3692N
See NS Package Number J 16A or N 16A

1-87

Outputs

Mode

A(O)

8 (C)

A(O)

8 (C)

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
TRI-STATE
1
TRI-STATE
0
0
1
1

1
TRI-STATE
0
TRI-STATE
0
1
0
1

en

N

0)

CD

('f)

tJ)

C

......
N

0)

CD

.....

tJ)

C

Absolute Maximum Ratings

Operating Conditions

(Note 1)

If Military I Aerospace specified devices are required,
contact the National Semiconductor Sales Officel
Distributors for availability and specifications.
Supply Voltage

Vee
VEE
DS3692

7V
-7V

Vee
VEE
Maximum Power Dissipation* at 25·C
Cavity Package
Molded Package

Vee
VEE
Temperature (TA)
DS1692
DS3692

1509 mW
1476 mW

Input Voltage

15V

Output Voltage (Power OFF)
Storage Temperature

Min

Max

Units

4.5
-4.5

5.5
-5.5

V
V

4.75
-4.75

5.25
-5.25

V
V

-55
0

+125
+70

·C
·C

Supply Voltage
DS1692

±15V
- 65·C to + 150·C

Lead Temperature (Soldering, 4 sec.)

260·C

"Derate cavity package 10.1 mW/,C; derate molded package 11.9 mW/,C
above 2SOC.

Electrical Characteristics DS1692/DS3692 (Notes 2, 3 and 4)
Symbol

I

Parameter

I

Conditions

I

Min

I

Typ

I

Max

I

Units

DS1692, Vee = 5V ± 10%, DS3692, Vee = 5V ± 5%, VEE CONNECTION TO GROUND, MODE SELECT:::;: 0.8V
Vo
Vo

Differential Output Voltage
VA,S

RL =

Vr
Vr

Differential Output Voltage
VA,S

RL = 100n
Vee ~ 4.75V

Vos, Vos

Common-Mode Offset
Voltage

RL = 100n

IVrl-lvTI

Difference in Differential
Output Voltage

RL = 100n

Ivosl - Ivosl

Difference in CommonMode Offset Voltage

RL = 100n

VIN = 2V

00

VIN = 0.8V

Vss

IVT - vTI

RL = 100n, Vee

lox

TRI-STATE Output Current

Va:::;: -10V

ISA

Output Short Circuit Current

Va

Iss

Ice

Output Short Circuit Current

~

VIN = 2V
VIN = 0.8V

~

4.75V

2.5

3.6

V

-2.5

-3.6

V

2

2.6

V

-2

-2.6

V

4.0

VIN = 2.4V

3

V

0.05

0.4

V

0.05

0.4

V

-0.002

-0.15

mA

V

4.8

0.002

0.15

mA

VOA = 6V

80

150

mA

Vas = OV

-80

-150

mA

VOA = OV

-80

-150

mA

Vas = 6V

80

150

mA

18

30

mA

15V

VIN = 0.4V

2.5

Supply Current

DS1692, Vee = 5V ± 10%, VEE = -5V ± 10%, DS3692, Vee = 5V ±5%, VEE = -5 ±5%, MODE SELECT:::;: 0.8V
VIN = 2.4V

7

8.5

V

VIN = O.4V

-7

-8.5

V

VIN = 2.4V

6

7.3

V

VIN = O.4V

-6

-7.3

Va
Va

Differential Output Voltage
VA,S

RL =

Vr
Vr

Differential Output Voltage
VA,S

RL = 200n

IVTI-lvTI

Output Unbalance

lox

TRI-STATE Output Current

Is+
Is-

Output Short Circuit Current

ISLEW

Slew Control Current

Ice

Positive Supply Current

VIN = O.4V, RL =

00

lEE

Negative Supply Current

VIN = O.4V, RL =

00

00

0.4

V

0.002

0.15

mA

Vo = -10V

-0.002

-0.15

mA

VIN = 2.4V

-80

-150

mA

VIN = O.4V

80

150

mA

18

30

mA

-10

-22

mA

IVeci = IVEEI, RL = 200n
Va = 10V

Va = OV

V

0.02

±140

1-88

iJ- A

Electrical Characteristics (Notes 2 and 3) VEE

c
en
.....

~ OV

c:n

CD

Symbol

Parameter

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

IIH

High Level Input Current

IlL

Low Level Input Current

Conditions

VIN

~

VIN

= O.4V

0.8

V

40

J.LA

10

100

J.LA

-30

-200

J.LA

-1.5

V

0.01

0.15

mA

-0.01

-0.15

mA

1

15V

= -12 mA

liN

IXA
IXB

Output Leakage Current
Power OFF

Vee

= VEE = OV

Switching Characteristics T A =

I
I

Vo

= 15V

Vo

= -15V

Units
V

= 2.4V

VIN

Input Clamp Voltage

Vee

Max

2

VI

Symbol

Typ

Min

Parameter

Min

Conditions

Typ

Max

Units

c:n

CD

I\)

= 5V, MODE SELECT = O.8V
Differential Output Rise Time

RL

= 100n, CL = 500 pF (Figure

1)

120

200

ns

tf

Differential Output Fall Time

RL

= 100n, CL = 500 pF (Figure 1)

120

200

ns

tpDH

Output Propagation Delay

RL

= 100n, CL = 500 pF (Figure

120

200

ns
ns

1)

tpDL

Output Propagation Delay

RL

= 100n, CL = 500 pF (Figure

1)

120

200

tpZL

TRI-STATE Delay

RL

= 1oon, CL = 500 pF (Figure 2)

180

250

ns

tpZH

TRI-STATE Delay

RL

= 1oon, CL = 500 pF (Figure 2)

180

250

ns

tpLZ

TRI-STATE Delay

RL

= 1oon, CL = 500 pF (Figure 2)

80

150

ns

RL

= 100n, CL = 500 pF (Figure 2)

80

150

ns

Vee

c
en
eN

25°C

tr

tpHZ

I\)

'-

TRI-STATE Delay

= 5V, VEE = -5V, MODE SELECT = O.8V

tr

Differential Output Rise Time

RL

= 200n, CL = 500 pF (Figure

1)

190

300

ns

tf

Differential Output Fall Time

RL

= 200n, CL = 500 pF (Figure

1)

190

300

ns

tpDL

Output Propagation Delay

RL

= 200n, CL = 500 pF (Figure

1)

190

300

ns

tpDH

Output Propagation Delay

RL

= 200n, CL = 500 pF (Figure

1)

190

300

ns

tpZL

TRI-STATE Delay

RL

= 200n, CL = 500 pF (Figure 2)

180

250

ns

tpZH

TRI-STATE Delay

RL

= 200n, CL = 500 pF (Figure 2)

180

250

ns

tpLZ

TRI-STATE Delay

RL

= 200n, CL = 500 pF (Figure 2)

80

150

ns

ns
TRI-STATE Delay
RL = 200n, CL = 500 pF (Figure 2)
Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified, min/max limits apply across the -SS'C to + 12S'C temperature range for the 081692 and across the O'C to + 70'C range for
the 083692. All typicals are given for Vee = SV and TA = 2S'C. Vee and VEE as listed in operating conditions.
Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.
Note 4: Only one output at a time should be shorted.
80

tpHZ

Note 1: "Absolute

1-89

150

•

N

0')

 IOns
: If!> IOns

OR

OV~----------~-~----------~~----------J
5V------R-0------~~

OUTPUT

NORMAllYlOW

'------------r

~--------------+_J--------.,_

VOL

------------u--------------+_"'" ---------''---- VOH
RO
OUTPUT

1.5V

OV ___N~O_RM_AL~L_YH_IG_H_____ _ J
TL/F/5272-6

FIGURE 3. Receiver Enable/Disable Propagation Delay Timing

1-101

III

AC Test Circuits and Switching Waveforms

re
I

FROM OUTPUT
UNDER TEST

II

-+-----'-00

82

T

00

~~":"
~'LD" tLl"'~1
~ I
~CL2='OOPI

-VCC

5000

CL
IINCLUDES PROBE
AND JIG
CAPACITANCE!
':'

(Continued)

=600

I 1.
':'

Note: Unless otherwise specified
the switches are closed.

TL/F/5272-10
TL/F/S272-9

FIGURE 4. Driver Propagation Delay Test Circuits
3V

t

01

=1MHz: tr ~ 10 ns
If~10ns

OV
DO

DO

tpLH

!

tpHL

f~2VO ~

n~K~

tSKEW

t
1/2VO

t
TL/F/5272-11

FIGURE 5. Driver Input-to-Output Propagation Delay Timing (Single-Ended)
3V

1=IMHz: IrS IOns
: II S IOns

DE or E
OV
5V

DO

DO.

VOL

OUTPUT

NORMALLY LOW

VOH
DO.

DO
OUTPUT

OV

NORMALLY HIGH

TL/F/5272-12

FIGURE 6. Driver Enable/Disable Propagation Delay Timing
3V

01
OV

1.5V

=

F 1 MHz
I r • If !!i 10 ns

+Vo

TLIF/5272-13

FIGURE 7. Driver Differentiallnput-to-Output Propagation Delay and Differential Transition Timing

1-102

c

en

DS3695/DS3696 Channel Distortion (Note 8, Figures 8, 9)

w

Q')

Symbol
tpRR

tpDD

Parameter

Conditons

The difference of any
two input to output
propagation delays between
any two receivers.

ATA :::; 25°C
AVee:::; 200 mV
(4.75V :::; Vee:::; 5.25V)

The difference of any
two differential input
to output propagation
delays between any
two drivers.

Measured between any
two parts on the
same interface channel.

Max

co

Units

U1

........

c

9

en
w

ns

Q')

co
U1
-I
........
C

en
6

w

ns

Q')

co

Q')

........

c

en
w

Q')

+5VDC

~
'
Ri

co
Q')
-I
........
C

510n

en

RO

w

Q')

62n

co

......

........

c

en

51 on

TL/F/5272-14

w

Q')

25 MBS Receiver Propagation Delay Test Circuit

co

(X)

TL/F/5272-15

25 MBS Driver Propagation Delay Test Circuit

3V
01

RI- Ri
F= 1 MHz
t r • If ::S 10 ns

OV

OV

F= 1 MHz
Ir • t f ::S 10 ns

1.5V

+Vo

1.5V

RO

TL/F/5272-16

TLlF/5272-17

FIGURE 9. 25 MBS Driver Propagation Delay Timing

FIGURE 8. 25 MBS Receiver Propagation Delay Timing

Note 8: Specified to meet the 25 Mbyte Intelligent Peripheral Interface (IPI) requirements.

1-103

co
en
CD
CO)

Function Tables

CJ)

o.......

053695/053696 Transmitting

......

en

Inputs
RE

OE

01

Line
Condition

X
X
X
X

1
1
0
1

1
0
X
X

No Fault
No Fault
X
Fault

CD
CO)

CJ)

o

~
en
CD
CO)

CJ)

o.......

Outputs
00

00

LF*
(053696 Only)

0
1
Z
Z

1
0
Z
Z

H
H
H
L

CD

en
CD

053695/053696 Receiving

CO)

CJ)

o.......

Outputs

Inputs

lll)

en

RE

OE

0
0
0
1

0
0
0
0

RI-AT

RO

LF*
(053696 Only)

1
0
1
Z

H
H
H
H

CD

CO)

CJ)

o.......
Il)

en

CD

CO)

~

+0.2V
-0.2V
Inputs Open* *
X
~

CJ)

o

053697/053698
Outputs

Inputs

E

RI-AT
~

1
1
1
0
1
1

Line
Condition

Open"

No Fault
No Fault
No Fault

X
+0.2V
~ -0.2V

Fault
Fault

+0.2V

~-0.2V

X

~

x-

Don't care condition

Z-

High impedance state

Fault -

00

00

RO/OI
(053697 Only)

LF*
(053698 Only)

0
1
0
Z
Z
Z

1
0
1
Z
Z
Z

1
0
1
Z
1
0

H
H
H
H
L
L

Improper line conditions causing excessive power dissipation in the driver, such as shorts or bus contention situations

-0= is an

"open collector" output with an on·chip 10 k!l. pull-up resistor

- - This Is a fall safe condition

Typical Application

OS3695/0S3696
TL/F/5272-18

1-104

c
en
01

~National

....o

01

~ Semiconductor

.......
.......

0555107/0555108/0575107/0575108/0575208
Oual Line Receivers

(X)

The products described herein are TIL compatible dual
high speed circuits intended for sensing in a broad range of
system applications. While the primary usage will be for line
receivers of MOS sensing, any of the products may effectively be used as voltage comparators, level translators,
window detectors, transducer preamplifiers, and in other
sensing applications. As digital line receivers the products
are applicable with the SN55109/SN75109 and JLA75110/
OS75110 companion drivers, or may be used in other balanced or unbalanced party-line data transmission systems.
The improved input sensitivity and delay specifications of
the OS75208 make it ideal for sensing high performance
MOS memories as well as high sensitivity line receivers and
voltage comparators.
Input protection diodes are incorporated in series with the
collectors of the differential input stage. These diodes are

useful in certain applications that have multiple Vee+ supplies or Vee+ supplies that are turned off.

Features
•
•
•
•
•
•
•
•
•
•

Diode protected input stage for power "OFF" condition
17 ns typ high speed
TIL compatible
± 10 mV or ± 25 mV input sensitivity
± 3V input common-mode range
High input impedance with normal Vee, or Vee = OV
Strobes for channel selection
Dual circuits
Sensitivity gntd. over full common-mode range
Logic input clamp diodes-meets both "A" and "8"
version specifications
• ± 5V standard supply voltages

Dual-In-Line Package

INPUT
1B

INPUT
2A

NC

INPUT
2B

NC

OUTPUT
1Y

STROBE
1G

OUTPUT
2Y

STROBE
S

STROBE
2G

GNO
TLlF/9446-1

Top View
Order Number DS55107J, DS75107J, DS55108J, DS75108J, DS75208J, DS75107N, DS75108N or DS75208N
See NS Package Number J14A or N14A

Selection Guide
Temperature -+
Package -+

-55°C S; TA S; + 125°C
Cavity Dip

O°C S; TA S; +70°C
Cavity or Molded Dip

Input Sensitivity -+
Output Logic!

±25mV

±25mV

±10mV

TIL Active Pull-Up
TIL Open Collector

OS55107
OS55108

OS75107
OS75108

OS75208

1-105

c
en
.......

....01

o
.......
.......

Connection Diagram

INPUT
1A

....o01

.......

General Description

vcc -

c
en
01

c
en
.......

....o
01

(X)

.......

c
en
.......
01
N

o

(X)

co

o
N

Lt)

I'

en

Absolute Maximum Ratings

(Note 1)

C

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

~

Supply Voltage, Vcc+

......
CO
o
Lt)

C

Supply Voltage, VccDifferential Input Voltage

I'

Common Mode Input Voltage

I'

en

......
o

~

Lt)

I'

en

±5V

OS55107,
OS55108

en
c

OS75107,
OS75108,OS75208

Min

Nom

Max

Min

Nom

Max

Supply Voltage VCC +

4.5V

5V

5.5V

4.75V

5V

5.25V

Supply Voltage Vcc-

-4.5V

-5V

-5.5V

-4.75V

-5V

-5.25V

~

Lt)
Lt)

en
c

Maximum Power Dissipation* at 25°C
1308 mW
Cavity Package
1207 mW
Molded Package
Lead Temperature (Soldering, 4 sec)
260°C
'Derate cavity package 8.7 mW/'C above 25'C; derate molded package 9.7
mWI'C above 25'C.

±6V

CO

~

- 65°C to + 150°C

Operating Conditions

o

Lt)
Lt)

5.5V

Storage Temperature Range

7V
-7V

C
......

......
I'
o

Strobe Input Voltage

to
+70°C
Operating Temperature Range
-55°C
to
+ 125°C
O°C
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2. Unless otherwise specified min/max limits apply across the - 55'C to + 125'C temperature range for the OS55107 and 0855108 and across the O'C to
+ 70'C range for the 0875107, 0875108 and 0875208. All typical values are for TA = 25'C and Vee = 5V.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.

0555107/0575107,0555108/0575108
Electrical Characteristics TMIN ~ TA ~ TMAX (Notes 2, 3)
Symbol

Conditions

Parameter

IIH

High Level Input Current
into A1, 81, A2 or 82

Vcc+ = Max, Vcc- = Max,
VIO = 0.5V, VIC = -3V to 3V

IlL

Low Level Input Current
into A1, 81, A2 or 82

Vcc+ = Max, Vcc- = Max,
VIO = -2V, VIC = -3Vt03V

IIH

High Level Input Current
into G1 orG2

Vcc+
Vcc-

IlL

Low Level Input Current
into G1 or G2

Vcc+
VIL(S)

IIH

High Level Input Current into S

IlL

Low Level Input Current into S

VOH

High Level Output Voltage

VOL

Low Level Output Voltage

IOH

High Level Output Current

los

Short Circuit Output Current

= Max,
= Max

Min

Typ

Max

Units

30

75

p.A

-10

p.A

40

mA

1

mA

-1.6

mA

I VIH(S) = 2.4V

I VIH(S) Max Vcc+

= Max, Vcc- = Max,
= 0.4V
Vcc+ = Max,
Vcc- = Max

I VIH(S) = 2.4V
I VIH(S) = Max Vcc+

= Max, Vcc- = Max,
= O.4V
Vcc+ = Min, Vcc- = Min,
ILOAO = -400 p.A, VIO = 25 mY,
VIC = -3V to 3V, (Note 3)
Vcc+ = Min, Vcc- = Min,
ISINK = 16 mA, VIO = -25 mY,
VIC = -3V to 3V
Vcc+ = Min, Vcc- = Min
VOH = Max Vcc+, (Note 4)
Vcc+ = Max, Vcc- = Max,
Vcc+
VIL(8)

(Notes 2 and 3)

80

p.A

2

mA

-3.2

mA
V

2.4

-18

0.4

V

250

p.A

-70

mA

ICCH+

High Logic Level Supply
Current from Vcc

Vcc+ = Max, Vcc- = Max,
VIO = 25 mY, TA = 25°C

18

30

mA

ICCH-

High Logic Level Supply
Current from Vcc

Vcc+ = Max, Vcc- = Max,
VIO = 25 mY, TA = 25°C

-8.4

-15

mA

VI

Input Clamp Voltage on G or S

VCC+ = Min, Vcc- = Min,
liN = -12 mA, TA = 25°C

-1

-1.5

V

1·106

Switching Characteristics Vcc+

c
en
CJ'1

= 5V, Vcc- = -5V, TA = 25°C

CJ'1

...&.

Symbol

Parameter

tpLH(O)

Propagation Delay Time, Low to
High Level, from Differential
Inputs A and 8 to Output

RL = 390n, CL = 50 pF,
(Note 1)

Propagation Delay Time, High to
Low Level, from Differential
Inputs A and 8 to Output

RL = 390n, CL
(Note 1)

Propagation Delay Time, Low to
High Level, from Strobe Input G
or S to Output

RL

Propagation Delay Time, High to
Low Level, from Strobe Input G
or S to Output

RL

tpHL(O)

tpLH(S)

tpHL(S)

Typ

Max

Units

(Note 3)

17

25

ns

(Note 4)

19

25

ns

(Note 3)

17

25

ns

(Note 4)

19

25

ns

(Note 3)

10

15

ns

(Note 4)

13

20

ns

Conditions

Min

o

........

.......

c
en
CJ'1
CJ'1

=

=

390n, CL

390n, CL

=

=

=

50 pF,

50 pF

50 pF

(Note 3)

8

15

ns

(Note 4)

13

20

ns

...&.

o

co

.......

c
en
........
CJ'1

...&.

o

........
.......

c
en
........
CJ'1

...&.

o
co
.......

Note 1: Oifferential input is + 100 mV to -100 mV pulse. Oelays read from 0 mV on input to 1.5V on output.
Note 2: Only one output at a time should be shorted.
Note 4: 0855108/0875108 only.

c
en
........

OS75208

o
co

Note 3: 0855107/0875107 only.

CJ'1

N

Electrical Characteristics
Symbol

O°C

~ TA ~ + 70°C

Parameter

Min

Conditions

IIH

High Level Input Current
into A1, 81, A2 or 82

Vcc+ = Max, Vcc- = Max,
VIO = 0.5V, VIC = -3V to 3V

IlL

Low Level Input Current
into A 1, 81, A2 or 82

Vcc+ = Max, Vcc- = Max,
VIO = -2V, VIC = -3V to 3V

IIH

High Level Input Current

Vcc+

into G1 or G2

VCC-

=
=

IlL

Low Level Input Current
into G1 or G2

Vcc+
VIL(S)

= Max, Vcc- =
= O.4V

IIH

High Level Input Current into S

Vcc+
Vcc-

=
=

= Max, Vcc- =
= O.4V

Max,
Max

Max,
Max

l

I

VIH(S)

=

2.4V

VIH(S)

=

Max Vcc+

Typ

Max

Units

30

75

fJ-A

-10

fJ-A

Max,

I

VIH(S)

=

2.4V

I

VIH(S)

=

Max Vcc+

40

fJ-A

1

mA

-1.6

mA

80

fJ-A

2

mA

-3.2

mA

IlL

Low Level Input Current into S

Vcc+
VIL(S)

VOL

Low Level Output Voltage

Vcc+ = Min, Vcc- = Min,
ISINK = 16 mA, VID = -10 mV,
VIC = -3V to 3V

0.4

V

250

fJ-A

IOH

High Level Output Current

Vcc+ = Min, VccVOH = Max Vcc+

ICCH+

High Logic Level Supply
Current from Vcc+

Vcc+ = Max, Vcc- = Max,
VIO = 10 mV, TA = 25°C

18

30

mA

ICCH-

High Logic Level Supply
Current from Vcc-

VCC+ = Max, Vcc- = Max,
VIO = 10 mV, TA = 25°C

-8.4

-15

rnA

VI

Input Clamp Voltage on G or S

Vcc+ = Min, Vcc- = Min,
liN = -12 mA, TA = 25°C

-1

-1.5

V

1-107

=

Max,

Min,

co
o
~

r--

en
c
.......
co
o,....

Switching Characteristics Vcc+
Symbol

Parameter

tpLH(D)

Propagation Delay Time, Low-toHigh Level, from Differential
Inputs A and B to Output

RL

Propagation Delay Time, High-toLow Level, from Differential
Inputs A and B to Output

RL

Propagation Delay Time, Low-toHigh Level, from Strobe Input G
or S to Output

RL

Propagation Delay Time, High-toLow Level, from Strobe Input G
or S to Output

RL

Lt)

r--

en
c.......

= 5V, Vcc- = -5V, TA = 25°C

tPHL(D)

r-o
,....

Conditions

Min

Typ

Max

Units

35

ns

20

ns

17

ns

17

ns

= 4700, CL = 15 pF, (Note 1)

= 4700, CL = 15 pF, (Note 1)

Lt)

r--

en
c.......
co
o
,....

Lt)
Lt)

tpLH(S)

tpHL(S)

en

c.......
r-o,....

Note 1: Differential input is

Lt)
Lt)

Typical Applications

en
c

= 4700, CL = 15 pF

= 4700, CL = 15 pF

+ 10 mV to -30 mV pulse. Delays read from 0 mV on input to 1.5V on output.

Basic Balanced-Line Transmission System
P

!

......~

().'A55/75110A)/
(OS55/75110A)

DATA
INPUT=D-IN A2
AI
IN
IN..!!.!,B IT
INH A

iNH
COMMON

-l(-

lWISTEO-PAIR OR EQUIVALENT
TRANSMISSION LINE
Zo 2 RT

=

r-.....

~
.. ....

().'A55/75107A)
(OS55/751 07)

+IN'-~
-IN_
~--IV>-----I
STROBE
A

-

STROBE
COMMON

RECEIVER

DRIVER

TL/F/9446-2

1-108

c

Typical Applications

en

U1
U1
-"

(Continued)

Q

Data-Bus or Party-Line System

......

........

C

en

U1
U1
-"
Q
Q)

........

C

TWISTED-PAIR LINE

en
......

P

U1
-"
Q

......

........

C

en
......
DATA
INPUT
IN Al
IN A2

DRIVER 1

U1
-"

DRIVER 3

Q

Q)

IN Al
IN A2

........

C

en
......

INHIBIT

iNHA
iNH

iNHA
iNH

iNHA
iNH

COMMON

COMMON

COMMON

(J1

N
TL/F/9446-3

25 mV (or less). For normal line resistances, data may be
recovered from lines of several thousand feet in length.

APPLICATION

The 0855107, 0875107 dual line circuits are designed specifically for use in high speed data transmission systems
that utilize balanced, terminated transmission lines such as
twisted-pair lines. The system operates in the balanced
mode, so that noise induced on one line is also induced on
the other. The noise appears common mode at the receiver
input terminals where it is rejected. The ground connection
between the line driver and receiver is not part of the signal
circuit so that system performance is not affected by circulating ground currents.

Line termination resistors (RT) are required only at the extreme ends of the line. For short lines, termination resistors
at the receiver only may prove adequate. The signal amplitude will then be approximately:
VOIFF ~ IO(on) x RT
(2)
The strobe feature of the receivers and the inhibit feature of
the drivers allow the 0855107,0875107 dual line circuits to
be used in data-bus or party-line systems. In these applications, several drivers and receivers may share a common
transmission line. An enabled driver transmits data to all
enabled receivers on the line while other drivers and receivers are disabled. Oata is thus time multiplexed on the transmission line. The 0855107, 0875107 device specifications
allow widely varying thermal and electrical environments at
the various driver and receiver locations. The data-bus system offers maximum performance at minimum cost.

The unique driver output circuit allows terminated transmission lines to be driven at normal line impedances. High
speed system operation is ensured since line reflections are
virtually eliminated when terminated lines are used. Crosstalk is minimized by low signal amplitudes and low line impedances.
The typical data delay in a system is approximately (30 +
1.3L) ns, where L is the distance in feet separating the driver and receiver. This delay includes one gate delay in both
the driver and receiver.

The 0855107,0875107 dual line circuits may also be used
in unbalanced or single line systems. Although these systems do not offer the same performance as balanced systems for long lines, they are adequate for very short lines
where environment noise is not severe.

Oata is impressed on the balanced-line system by unbalancing the line voltages with the driver output current. The driven line is selected by appropriate driver input logic levels.
The voltage difference is approximately:

The receiver threshold level is established by applying a OC
reference voltage to one receiver input terminal. The signal
from the transmission line is applied to the remaining input.
The reference voltage should be optimized so that signal

VOIFF ~ % IO(on) x RT
(1)
High series line resistance will cause degradation of the signal. The receivers, however, will detect signals as low as

1-109

Q
Q)

co

o
N

II)

.....
U)
C

......
CO
o,...

Typical Applications (Continued)
DS75108 Wired-OR Output Connections

swing is symmetrical about it for maximum noise margin.
The reference voltage should be in the range of - 3.0V to
+ 3.0V. It can be provided by a voltage supply or by a voltage divider from an available supply voltage.

II)

.....

Unbalanced or Single-Line Systems

U)

C

......
.....
o
,...

INPUT
OUTPUT

II)

.....
U)
C

......
CO
o
,...

STROBES

JO.-~~_-

U)

Precautions In the Use of DS1603, DS3603, DS55107,
DS75107, DS75108 and DS75208 Dual Line Receivers

C
......
.....

The following precaution should be observed when using or
testing 0855107, 0875107 line circuits .

II)
II)

o
,...

II)
II)

U)

C

OUTPUT

TL/F/9446-4

TL/F/9446-6

Circuit Differences Between Industry Standard
75107175108 A and B Versions

When only one receiver in a package is being used, at least
one of the differential inputs of the unused receiver should
be terminated at some voltage between -3.0V and +3.0V,
preferably at ground. Failure to do so will cause improper
operation of the unit being used because of common bias
circuitry for the current sources of the two receivers.

The essential difference between the "A" and "8" versions
is shown in the following schematics of the input state:

A Version
v+----~-~---~~-_,

The 0855107, 0875107 and 0875108 line receivers feature a common mode input voltage range of ± 3.0V. This
satisfies the requirements for all but the noisiest system applications. For these severe noise environments, the common mode range can be extended by the use of external
input attenuators. Common mode input voltages can in this
way be reduced to ± 3.0V at the receiver input terminals.
Differential data signals will be reduced proportionately. Input sensitivity, input impedance and delay times will be adversely affected.

+IN

The 0875108 line receivers feature an open-collector-output circuit that can be connected in the DOT-OR logic configuration with other 0875108 outputs. This allows a level of
logic to be implemented without addtional logic delay.

-IN -----+---....

Increasing Common Mode Input
Voltage Range of Receiver
TL/F/9446-7

Rl
OS55/75107
OS55/75108

B Version
v+----~--~------~~--~

Rl

TL/F/9446-5

+IN

-IN

--------+-----.. . .

TL/F/9446-8

1-110

Typical Applications

c
en
U1

(Continued)

U1

The input protection diodes are useful in certain party-line
systems which may have multiple V + power supplies and,
in which case, may be operated with some of the V + supplies turned off. In such a system, if a supply is turned off
and allowed to go to ground, the equivalent input circuit
connected to that supply would be as follows:

This would be a problem in specific systems which might
possibly have the transmission lines biased to some potential greater than 1.4V. Since this is not a widespread application problem, both the A and B versions will be available.
The ratings and characteristic specifications of the B versions are the same as those of the A versions.
The OS751 07 IOS751 08/0S75208 feature the protective diodes shown in the B version below. The }J-A55107A1
OS55107A feature the A version input stage.

A Version
INPUT

-~""'I--+t::J-~"'-l--'

-4

o

~
.......

c
en
U1
U1

-4

o

ex»
.......

c
en
~

U1
-4

o

~

.......

c
en

TL/F/9446-9

~

B Version
INPUT

U1

-4

t::J--..-.--.,l

o

--t~~1~14III---..

ex»
.......

c
en
~

U1
N

TLIF/9446-10

o

ex»

Schematic Diagrams
0555107/0575107,OS55108/0575108,0575208

Vee +o--.....- .....- - -.....- ....- ....- ....- - - - - -.....----a~-... - - - - - - -,

..
I

120 ::
1.6k

4k

"

.1"-----,
~~

8.5k

...
..... -~

........
I .... -~
I

I

~

I
I

:: 4k

,

I

INPUT B

I

I

OUTPUT

INPUT A o----+---~

...---OSTROBE G

L----+-~

..-----4t-------o STROBE S
vee-o---.....- - - -.....- . ._ _....______- - I
TL/F/9446-11

Note 1:

% of the dual circuit is shown.

Note 2: 'Indicates connections common to second half of dual circuit.
Note 3: Components shown with dash lines are applicable to the OS55107, OS75207 and OS75107 only.

1-111

III

~National

D Semiconductor
DS55110A/~A55110A/DS75110A/~A75110A

Dual Line Drivers
General Description

Features

The 085511 OAf fLA5511 OA, 087511 OAf fLA7511 OA are
dual line drivers with independent channels, common supply
and ground terminals featuring constant current outputs.
These drivers are designed for optimum performance when
used with the 0855107/0875107, 0855108/0875108 line
receivers.

• No output transients on power-up or down
• Improved stability over supply voltage and temperature
ranges
• Constant current, high impedance outputs
• High speed 15 ns
• 8tandard supply voltages
• Inhibitor available for driver selection
• High common mode output voltage range
(-3.0V to 10V)
• TTL input compatibility
• Extended temperature range

The output current of the 085511 OAf fLA5511 OA,
OS75110AffLA75110A is nominally 12 mA and may be
switched to either of two output terminals with the appropriate logic levels at the driver input.
8eparate or common control inputs are provided for increased logic versatility. These control or inhibit inputs allow
the output current to be switched off (inhibited) by applying
low logic levels to the control inputs. The output current in
the inhibit mode, 10(011), is specified so that minimum line
loading is induced. This is highly desirable in system applications using party line data communications.

Function Table

Connection Diagram

Inputs

14-Lead Dual-ln-L1ne Package
and SO-14 Package

Logic
A

B

C

0

A1/B1

A2/B2

X

X

L

X

Off

Off

X

X

X

L

Off

Off

v-

L

X

H

H

On

Off

X

L

H

H

On

Off

L...-I--INH COMMON

H

H

H

H

Off

On

14

IN A1

v+

........_-I--OUT A2

IN A2
INH A--i---r"",

L...-I--OUT A1

INH B-.......-~.....- - IN 81

Outputs
Inhibitor

IN 82

H""C"'1--+--0UT B1

GND

L...-......-OUT 82

H = High,

TL/F/9619-1

Top View
Order Number DS55110AJ, DS75110AJ,
fLA55110ADM, fLA75110ADC
See NS Package Number J14A*
Order Number DS75110AM or fLA75110ASC
See NS Package Number M14A
Order Number DS75110AN or fLA75110APC
See NS Package Number N14A

'For most current package information, contact product marketing.

1-112

L = Low,

x=

Don't Care

c

Absolute Maximum Ratings

en

U1
U1

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range
Ceramic DIP
Molded DIP and SO-14

..",
..",

Maximum Power Dissipation" at 25°C
Cavity Package
Molded Package
SO Package

1360mW
1040 mW
930mW

• Derate cavity package 9.1 mWI'C above 2S·C; derate molded DIP package
8.3 mWI"C above 2S·C; derate SO package 7.S mWrC above 2S·C.

- 65°C to + 175°C
- 65·C to + 150°C

Suppy Voltage

Lead Temperature
Ceramic DIP (Soldering, 60 sec.)
Molded DIP and SO-14
(Soldering, 10 sec.)

±7.0V

Input Voltage (Any Input)

30DoC

5.5V

Output Voltage (Any Output)

-5.0Vto +12V

265°C

Typ

Max

Min

Typ

4.5

5.0

5.5

4.75

5.0

5.25

V

Negative Supply Voltage (V-)

-4.5

-5.0

-5.5

-4.75

-5.0

-5.25

V

10

0

10

V

-3.0

0

125

0

0
0
25

Max

-3.0

V

25

70

°C

Typ

Max

Electrical Characteristics
Over recommended operating temperature range, unless otherwise specified. (Notes 2 and 3)
Symbol

Parameter

Conditions

VIH

Input Voltage HIGH

VIL

Input Voltage LOW

VIC

Input Clamp Voltage

Vcc = Min,ll = -12 rnA

10(On)

On-State
Output Current

Vcc = Min, Vo = -3.0V

Off-State Output Current
Input Current
At Maximum
Input Voltage

A, B orC
Inputs

Input Current HIGH

A, B orC
Input

V
V

-0.9

-1.5

V

12

15

Input Current LOW

100

Vcc = Min, Vo = 10V
Vcc = Max, VI = 5.5V

1.0

D Input

A,BorC
Input

Positive Supply Current
with Driver Enabled

I-(On)

Negative Supply Current
with Driver Enabled

1+ (Off)

Positive Supply Current
with Driver Inhibited

I-(Off)

Negative Supply Current
with Driver Inhibited

/LA
mA

2.0
Vcc = Max, VI = 2.4V

40

/LA

80
Vcc = Max, VI = O.4V

-3.0

D Input
1+(On)

rnA

12

6.5

D Input
IlL

Units

0.8

Vcc = Max, Vo = 10V

10(011)

IIH

Min
2.0

II

rnA

-6.0
Vce = Max,
A & B Inputs at O.4V,
C & D Inputs at 2.0V

23

35

mA

-34

-50

mA

Vce = Max,
A, B, C & D Inputs
at D.4V

21

rnA

-17

rnA

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified min/max limits apply across the -SS·C to
the D57S110. All typicals are given for Vee = SV and TA = 2S·C.

..",
..",

o

»

.......

c

en
......
o

Units

Min

-55

U1

..",

DS75110Af/LA75110A

Positive Supply Voltage (V+)

Operating Temperature (TA)

»
U1

..",

DS5511 OAf /LA5511 OA

Negative Common Mode Voltage (VCM-)

1=

U1

Recommended Operating Conditions

Positive Common Mode Voltage (VCM +)

o

»
.......

+ 12S·C temperature range for the D55S110 and across the O·C to + 70·C range for

Note 3: When using only one channel of the line drivers, the other channel should be inhibited and/or its outputs grounded.

1-113

»
.......
1=
»
......

U1
..",
..",

o

»

«

,...
,...
Q

Ln
.....

«::L
......
«
Q
,...
,...

Ln

.....
c......

en

«

,...
,...

Switching Characteristics Vee = ± 5V, TA =
Symbol

25°C

Parameter

Conditions
CL = 40 pF,
RL = 500
See Test Circuit

tpLH

Propagation Delay Time, LOW to HIGH

tpHL

Propagation Delay Time, HIGH to LOW

tpLH

Propagation Delay Time, LOW to HIGH

tpHL

Propagation Delay Time, HIGH to LOW

From
(Input)

To
(Output)

AorB

1 or 2

CorD

Min

1 or 2

Typ

Max

Units

9.0

15

ns

9.0

15

ns

16

25

ns

13

25

ns

Q

Ln
Ln

«::L
......
«

LOGIC
INPUT
V-

V+

50.0.

,...
,...

Q

OUTPUT 2

Ln
Ln

en

PULSE
GENERATOR

c

#1

INHIBITOR
INPUT

I
I
I
I
I
I
I
I
I
I

~---"""---4""'-- OUTPUT 1

TO OTHER CHANNEL
~------..I:-----"

I

TL/F/9619-3

Note 1: The pulse generators have the following characteristics:
tr

=

tf

=

10 ns ±5.0 ns, tw1

=

500 ns, PRR

=

1.0 MHz, tW2

=

1.0 ).los, PRR

=

500 kHz, Zo

=

son.

Note 2: CL includes probe and jib capacitance.
Note 3: For simplicity, only one channel and the inhibitor connections are shown.

FIGURE 2. AC Test Circuit

LOGIC
INPUT

3V

1 OR 2

OV

INHIBITOR
INPUT OR
INHIBITOR
COt.lt.lON

3V

OV
OFF

OUT
2

ON
OFF

OUT
1

ON
TL/F/9619-4

FIGURE 3. AC Waveforms

1-114

c

en
U1
U1
.....
.....

v+----------------------.------------~~------------~~------------~

0

»
.......

1=

»

U1
U1

.....
.....
0

»
.......

INAI--+--

IN A2

c

en
.......
U1
.....
.....

-----+----..

0

»
.......

GNO---~------~----------------r_---------~

1=

»
.......

.....
.....
0
U1

»
05
2.4

06

-=

iNH
COIIIION

v+
RI09
1.2kA

RI5
I kA
Z5

iNHs
07

III

010.4
RIIO
I kA

v-

-=
v+
BOA

INBI--+--

IN S2

-----+------..

o

=CROSSUNOER
TL/F/9619-2

FIGURE 1. Equivalent Circuit

1-115

<
o

.....
Typical Applications
.....
LI)

.....
<::L
.....
<
o

DATA
IN
DATA OUT

.....
.....
LI)
.....
en

INHIBIT

c
.....
<
o
.....
.....

SHIELD OR C0t.4t.40N GROUND RETURN

LI)
LI)

<
.....::L
<
o
.....
.....
LI)
LI)

en
c

TL/F/9619-5

FIGURE 4. Simplex Operation

PORT
ENABLES

PORT
ENABLES

DATA
IN

DATA
OUT

....""",.."....,

RT

SHIELD OR
C0t.4t.40N GROUND
RETURN

DATA
IN

DATA
OUT

TL/F/9619-6

FIGURE 5. Half-Duplex Operation
Note 1: All drivers are 0575110Al/-1A75110A or 0555110Al/-1A55110A. Receivers are 0575107 or 0575108. Twisted-pair or coaxial transmission line should
be used for minimum noise and cross talk.
Note 2: When only one driver in a package is being used, the outputs of the other driver should either be grounded or inhibited to reduce power dissipation.

1·116

'?A National
~ Semiconductor
DS55113/DS75113 Dual TRI-STATE®
Differential Line Driver
General Description

Features

The 0555113/0575113 dual differential line drivers with
TAl-STATE outputs are designed to provide all the features
of the 0555114/0575114 line drivers with the added feature of driver output controls. There are individual controls
for each output pair, as well as a common control for both
output pairs. When an output control is low, the associated
output is in a high-impedance state and the output can neither drive nor load the bus. This permits many devices to be
connected together on the same transmission line for partyline applications.

• Each circuit offers a choice of open-collector or active
pull-up (totem-pole) outputs
• Single 5V supply
• Differential line operation
• Dual channels
• TTL/L5 compatibility
• High-impedance output state for party-line applications
• Short-circuit protection
• High current outputs
• Single-ended or differential ANO/NANO outputs
• Common and individual output controls
• Clamp diodes at inputs
• Easily adaptable to DS55114/DS75114 applications

The output stages are similar to TTL totem-pole outputs, but
with the sink outputs, YS and ZS, and the corresponding
active pull-up terminals, YP and ZP, available on adjacent
package pins.

Connection Diagram
Dual-In-Llne Package

= AS
Z =AB

Positive logic: Y

Output is OFF when
C orCC is low

1ZP

1ZS

1YS

1A

1YP

GND

1C

1B

TLIF/5785-1

Top View
Order Number DS55113J, DS75113J, DS75113M or DS75113N
See NS Package Number J16A, M16A or N16A

Truth Table
Inputs

Outputs

Output Control

AND

Data

NAND

C

CC

A

B*

Y

Z

L
X
H
H
H

X
L
H
H
H

X
X
L
X
H

X
X
X
L
H

Z
Z
L
L
H

Z
Z
H*
H
L

1-117

H = high level
L = low level
X = irrelevant
Z = high impedance (OFF)
'S input and 4th line of truth
table applicable only to
driver number 1

III

,....
,....

C")
Lt)

Absolute Maximum Ratings

en

If Military/Aerospace specified devices are required,

Storage Temperature Range

contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Lead Temperature (1/16" from case for
60 seconds): J Package

300·C

Supply Voltage (Vee> (Note 1)

Lead Temperature (1/16" from case for
4 seconds): N Package

260·C

......

o
.......

,....
,....

C")
Lt)
Lt)

(Note 1)

7V

Input Voltage

en

o

5.5V

OFF-State Voltage Applied to
Open-Collector Outputs

Operating Conditions

12V

Maximum Power Dissipation· at 25·C
Cavity Package
Molded DIP Package
SO Package

- 65·C to + 150·C

Min

Max

Units

4.5
4.75

V
V

High Level Output Current (IOH)

5.5
5.25
-40

mA

Low Level Output Current (Iou

40

mA

Operating Free-Air Temperature (TA)
-55
OS55113
OS75113
0

125
70

·C
·C

Supply Voltage (Vee>
OS55113
OS75113

1433 mW
1362 mW
1002 mW

Operating Free-Air Temperature Range
OS55113
- 55·C to + 125·C
OS75113
O·Cto +70·C
'Derate cavity package 9.6 mW'oC above 2SoC; derate molded DIP pack·
age 10.9 mwrc above 2SoC; derate SO package 8.01 mW'oC above 2SoC
(Note 2).

Electrical Characteristics Over recommended operating free-air temperature range (unless otherwise noted)
OS55113

Symbol

Parameter

VIH

High Level
Input Voltage

VIL

Low Level
Input Voltage

2

=

=

-0.9

Input Clamp Voltage

Vee

VOH

High Level
Output Voltage

Vee = Min, VIH = 2V,
VIL = O.SV

VOL

Low Level
Output Voltage

Vee

=

Min, VIH

=

2V, VIL

VOK

Output Clamp Voltage

Vee

=

Max, 10

=

-40 mA

10(off)

Off-State
Open-Collector
Output Current

Vee

=

Max

Min, II

-12 mA

IIH

IlL

Off· State (HighImpedance-State)
Output Current

=

=

10H

=

-10 mA 204

10H

=

-40mA

O.SV, 10L

=

40 mA

TA

=

25·C

TA

=

125·C

5.25V TA

=

25·C

TA

=

70·C

VOH = 12V

VOH

II

V

2
0.8

VIK

loz

OS75113
Units
Typ
Typ
Max Min
Max
Min
(Note 4)
(Note 4)

Conditions (Note 3)

TA = 25·C, Va = 0 to Vee
Vee = Max,
Output Controls
Va = OV
TA = Max
at O.SV
Va = OAV

Input Current at A,B,C Vee
t-Maximum Input
CC
Voltage

=

High Level
Input Current

t--

=

Low Level
Input Current

t--

A,B,C Vee

Max, VI

Max, VI

=

=

=

Max, VI

=

-0.9
2.4

3.4

3.0

2

3.0

V

-1.5

V
V

0.23

004

0.23

0.4

V

-1.1

-1.5

-1.1

-1.5

V

1

10

1

10
200

/LA
20

±10

±10

-150

-20

±SO

±20

Va

=

2AV

±80

±20

Va

=

Vee

so

20

5.5V

2AV

CC
A,B,C Vee

2

-1.5

304

O.S

OAV

CC

1-11S

1

1

2

2

40

40

SO

SO

-1.6

-1.6

-3.2

-3.2

/LA

mA

/LA

mA

c
en
CJ1
CJ1
.....
.....

Electrical Characteristics
Over recommended operating free-air temperature range (unless otherwise noted) (Continued)
OS55113
Symbol

Parameter

Conditions (Note 3)

Typ
Max
(Note 4)

Min
los

Short-Circuit Output
Current (Note 5)

Vee = Max, Va = OV

Icc

Supply Current
(80th Drivers)

All Inputs at OV, No Load
TA = 25°C

OS75113

-40

Min

-120 -40

-90

Units
Typ
Max
(Note 4)
-90

-120

Ivee = Max

47

65

47

65

IVee = 7V

65

85

65

85

rnA

(,,)
......
c

en

CJ1
'"
.....

.....

(,,)

rnA

All voltage values are with respect to network ground terminal.
For operation above 25'C free-air temperature, refer to Dissipation Derating Curves In the Thermal information section.
Note 3: All parameters with the exception of OFF-state open-collector output current are measured with the active pull-up connected to the sink output.
Note 4: All typical values are at TA = 25'C and Vcc = 5V, with the exception of IcC at 7V.
Note 5: Only one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
Note 1:
Note 2:

Switching Characteristics Vee =
Symbol

Parameter

5V, CL = 30 pF, TA = 25°C
OS55113

Conditions
Min

OS75113

Unit

Typ

Max

20

13

30

ns

20

12

30

ns

Typ

Max

13
12

Min

tpLH

Propagation Delay Time, Low-to
High-Level Output

tpHL

Propagation Delay Time, High-to
Low-Level Output

tPZH

Output Enable Time to High Level

RL = 180.0., (Figure 2)

7

15

7

20

ns

tpZL

Output Enable Time to Low Level

RL = 250.0., (Figure 3)

14

30

14

40

ns

tpHZ

Output Disable Time from High
Level

RL = 180.0., (Figure 2)

10

20

10

30

ns

tpLZ

Output Disable Time from Low
Level

RL = 250.0., (Figure 3)

17

35

17

35

ns

(Figure 1)

III

1-119

0555113/0575113

•

•

tn
n
:::r

INPUT IA

INPUT 18

•

1'"'1'"

•••

•••

•

(16) VCC

CD

3
D)

...

c:;"

o

iir

...

cg
D)

3

a
:J
CD

en

(I) NAND

AND (4)
PULL·UP -1.....- - IVP

'----.t-

a:
CD

PULL·UP
IZP

en

::T

~

o

:J

:$
100

......
a

I\)

AND SINK (3)
DUTPUT
I
IVS

(2) NAND SINK

•

•

DUTPUT
IZS

':'

':'

VccO •

COMMON OUTPUT (9)
CONTROL cc - - - - - - ,
(COMMON TO BOTH SIDES)
OUTPUT (7)
CONTROL
IC

•

'These components common to both drivers.
Resistor values shown are typical and in !l.
(8)

••
':'

•

•

GNO
TL/F/5785-2

AC Test Circuits and Switching Time Waveforms
~--~--~-------~~~~T

3V
INPUT

VOH
NANO
OUTPUT
VOL

~"'----I-L..J.:""---1 >-+-+--...- - - ~~~PUT
ANO
OUTPUT

VOH

VOL

TL/F/5785-3

FIGURE 1. tpLH and tpHL

INPUT

INPUT

VOH ----+F:....__h
OUTPUT

TlIF/5785-4

FIGURE 2. tPZH and tpHz

•

INPUT

5V
3V-H~::--::;::~

250

INPUT

OUTPUT

I
I
I
I

1k
5V

1

1
I

~L

_________________

5V
OUTPUT
VOL-----~~----

I
I

~

TL/F/5785-5

FIGURE 3. tPZL and tpLZ
Note 1: The pulse generator has the following characteristics: ZOUT = 50n, PRR = 500 kHz, tw = 100 ns.
Note 2: CL includes probe and jig capacitance.

1-121

,....
,....

C")

LI)

......

Typical Performance Characteristics *

en

c
......
C")
,....
,....

Output Voltage vs Output
Control Voltage
LOAD' soon TO GROUN~J-

LI)
LI)

Vcc' SV

en
c

6

f--

TA' 2S·C

~

1.

~ISABLED

-----

'"

~>

~

DISABLED

~

3.2

'"

2.8

1
1

~

>

2

'"

I-

t.&

I

co

>

1
I.

5

VCC' 4.5V

1
1

VOH UOH' -10 mA~

I-

'"co

1
1

-I

.......

1
1

t.2
0.8

1
1

1
1

1
1

-~-~-25

co

0

25

co

~

~

100 125

80

oS

70

....
Z

60

ex:
ex:
u
>-

50

III

'"

i
I

u
u

INPUTS GRDUNDE~P"

,

~

30

~

54

oS

52

i

48

>...0

INPUTS OPEN

~
I

...
u

I

10

o

"'

~

40

III

>

~co

-40

-60

0.3
0.2

I

.:'

hoIY--+--+--f--+---I

0.1

0'---'--.......-1....--'----'---'
o

-80 -100 -120

20

-

......

46
44

60

80

100

120

Supply Current (Both
Drivers) vs Frequency
100

VCC - 5V
INPUTS GROUNDED
NO LOAD

50

40

IDL - OUTPUT CURRENT )mA)

Supply Current (Both
Drivers) vs Free-Air
Temperature
56

I

-20

TA - 25·C

0.5 1---+--+--1----+--t-:~

10H - QUTPUT CURRENT )mA)

NO LOAD
TA - 25·C

20

o

r--""-..,--r---r-...,---,

'" 0.4 t--+--t~

I
I

)~C)

Supply Current (Both
Drivers) vs Supply Voltage
C

~

1

"•

>

Low Level Output
Voltage vs Output
Current

0.&

-1-00..

I
%

I

LOW

o

VI-INPUT VOLTAGE )OUTPUT CONTROL) IV)

1 TA -25°C

::I

TA - FREE·AIR TEMPERATURE

OIS~BLE

_VCC-4.5V"'--- 1-00.."

o

o

>

o

~

~ 25°~

TA ~ -5S~C

co

LOAD' 500n TO Vcc
TA' 2S·C

High Level Output
Voltage vs Output
Current

....

::I

VOL UOL • 40 mAl

0.4

TA

o

--

'"

V~~Om~)
I

'"~
I

f'.... J _~'~.5V- -

III

~ I--

~
>

I

TA~125!C

co

R,VCc"5V
~

~

+-rT l- ~ I-'I

~

VI-INPUT VOLTAGE )OUTPUT CONTROL) IV)

Output Voltage vs Free-Air
Temperature

2.4

II

o

VI-INPUT VOLTAGE IOUTPUT CONTROL) IV)

4

1I

'"

LOW

I I II

co

>

3.&

LOAD' soon TO Vee
Vce' 5V

I-

'"

o

Output Voltage vs Output
Control Voltage

S~SV

I-

TA' -SS·C

HIGH

I

o

vc1c·

&

Vcc' 5V
I
I
,..-"Vcc' 4.5V f -

r-

III

-'TA .'125·1:_ f--

Output Voltage vs Output
Control Voltage

"'oS....

VCC' 5V
RL - ~
CL - 30 pF
INPUTS: 3V SQUARE WAVE
TA·2SoC

80

Z

III

..........
.......

42

ex:
ex:

60

i...

40

...'">-

"

40

.","

I

20

u

38

./';'

36
-75 -50 -25

o

0

25

50

0.4

!

Vce - SV

30

IPLH_

~

k-" i-""'"
i,.....oo I--""

25

'"

20

Ii

15

~
is

-

c

III

'"

~
'"

2

~

o
50

40 100

75 100 125

TA - FREE·AIR TEMPERATURE)"C)

1000-

........~
~~

-

~

~

10

....
25

10

II~

...0

IpHL

0

4

II

VCC' 5V
)FIGURES 2 AND 3)

~

18 CL • 30 pF
)FIGURE 1)

1

Output Enable and Disable
Times vs Free-Air Temperature

20

-75 -50 -25

0.1

,- FREQUENCV (MHz)

Propagation Delay Times
from Data Inputs vs Free-Air
Temperature

..

o

75 100 125

TA - FREE·AIR TEMPERATURE rC)

VCC - SUPPLY VOLTAGE (V)

o

-75 -50 -25

IPZH _

II
0

25

50

75 100 125

TA - FREE·AIR TEMPERATURE )OC)

TL/F/5785-7

'Data for temperatures below O·C and above 70·C and for supply voltages below 4.75V and above 5.25V are applicable to 0855113 circuits only. These
parameters were measured with the active pull-up connected to the sink output.

1-122

c
en
.....
.....

Typical Performance Characteristics * (Continued)
Output Voltage VB Data
Input Voltage
NO LOAD
TA - 2S'C

E
w

/

~

f

co

J.

.1

J

VCC - S.5V

I
I

I-

::>

I

VCC -4.5V

S
co

Output Voltage VB Data
Input Voltage
NO LOAD
VCC - sv

jVCC oSV

c:o

>

I

8

E
...

/

,

'"
~
co

/

>

I-

~

T~ - 2~'C

TA - -SS'C -

Tl-1Js'c

I-

::>

co

I

VI- DATA INPUT VOLTAGE (V)

LOAD -

/

~

;

co

VI- DATA INPUT VOLTAGE (V)

J

IVCC- SV -

c:o

-

VC~-S.5V_ -=

W
......

c
en
U1
'"
.....
.....
W

I

>

I-

~

VCC - 4.5V
DIS~BLEID

o

o

soon TO GROUND

TA-2S'C

E
...

>

o

o

8

co

co

>

o

Output Voltage VB Output
Control Voltage

I

I

co

>

U1
U1

o

~IGH

I

VI- INPUT VOLTAGE (OUTPUT CONTROL) (V)
TL/F/5785-6

"Data for temperatures below O'C and above 70'C and for supply voltages below 4.75V and above 5.25V are applicable to D555113 circuits only. These
parameters were measured with the active pull-up connected to the sink output.

III

1-123

~
......

~ ~National

eD
~
......

......
~
en
c

Semiconductor

D555114/D575114 Dual Differential Line Drivers
General Description

Features

The DS55114/DS75114 dual differential line drivers are designed to provide differential output signals with high current
capability for driving balanced lines, such as twisted pair at
normal line impedances, without high power dissipation.
The output stages are similar to TTL totem-pole outputs, but
with the sink outputs, YS and ZS, and the corresponding
active pull-up terminals, YP and ZP, available on adjacent
package pins. Since the output stages provide TTL compatible output levels, these devices may also be used as TTL
expanders or phase splitters.

• Each circuit offers a choice of open-collector or active
pull-up (totem-pole) outputs
•
•
•
•
•
•
•
•
•
•

Single 5V supply
Differential line operation
Dual channels
TTLILS compatibility
Designed to be interchangeable with Fairchild 9614 line
drivers
Short-circuit protection of outputs
High current outputs
Clamp diodes at inputs and outputs to terminate line
transients
Single-ended or differential AND/NAND outputs
Triple inputs

Connection Diagram
Dual-In-Llne Package
2ZP

VCC
16

15

14

1ZP

1ZS

1YS

2C

2YP

2YS

2ZS

2A

GND

1C

1B

1A

1YP

2B

TL/F/5786-1

Top View
Positive logic: Y

= ABC

Z = ABC

Order Number DS55114J, DS75114J, or DS75114N
See NS Package Number J16A or N16A

Truth Table
Inputs
A

Outputs

B

H
H
All Other Input Combinations
H
L

= high level
= low level

1-124

C

Y

Z

H

H
L

L
H

Absolute Maximum Ratings

c
en
CJ1

(Note 1)

Supply Voltage (Vee

7V

Input Voltage

5.5V

OFF-State Voltage Applied to
Open-Collector Outputs

12V

Cavity Package

1433 mW

Molded Package

1362 mW

Operating Free-Air Temperature Range
DS55114

- 55°C to + 125°C
O°C to +70°C

Storage Temperature Range

- 65°C to + 150°C

Lead Temperature (1/16" from case
for 60 seconds): J Package

Lead Temperature (1/16" from case
for 4 seconds): N Package
260°C
'Derate cavity package 9.6 mWrC above 2SoC; derate molded package
10.9 mWrC above 2SoC (Note 2).

"-

Operating Conditions

........

Supply Voltage (Vee)
DS55114
DS75114
High Level Output Current (IOH)
Low Level Output Current (Iod
Operating Free-Air
Temperature (TA)
DS55114
DS75114

Maximum Power Dissipation" at 25°C

DS75114

Min

Max

Units

4.5
4.75

5.5
5.25
-40
40

V
V
mA
mA

-55

125
70

°C
°C

0

300°C

0555114
Parameter

Conditions (Note 3)

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

VIK

Input Clamp Voltage

VOH

High Level Output Voltage Vee = Min, VIH = 2V

2

Min

Typ
(Note 4)

-0.9

Vee = Min,ll = -12 mA
10H = -10 mA 2.4
10H = -40 mA

VOL

Low Level Output Voltage Vee = Min, VIH = 2V, VIL = 0.8V,
10L = 40 mA

VOK

Output Clamp Voltage

2

Vee = Max,lo = -40 mA, TA
OFF-State Open-Collector
Output Current

VOH = 12V

V

VOH

=

5.25V

II

Input Current at Maximum Vee = Max, VI = 5.5V
Input Voltage

IIH

High Level Input Current

Vee = Max, VI = 2.4V

IlL

Low Level Input Current

Vee = Max, VI = O.4V

los

Short-Circuit Output
Current (Note 5)

Vee = Max, Vo = OV

lee

Supply Current
(Both Drivers)

Inputs Grounded, No Load,

=

25°C

25°C

TA

=

25°C

TA

=

70°C

-0.9
3.4

3.0

2

3.0

0.4

0.2

6.5

6.1

6.5

-1.1

-1.5

1

100

7V

200
1
40

/-LA

-1.6

mA

-90

-120

mA

-1.6

-90

120

37

50

37

50

47

65

47

70

-40

Note 3: All parameters, with the exception of OFF· state open·collector output current, are measured with the active pull-up connected to the sink output.

= 2SoC and Vcc = SV, with the exception of Icc at 7V.

Note 5: Only one output should be shorted at a time, and duration of the short·circuit should not exceed one second.

mA

-1.1

-1.1

Note 1: All voltage values are with respect to network ground terminal.

1-125

V

/-LA

Note 2: For operation above 2SoC free·air temperature, refer to Dissipation Derating Curves in the Thermal information section.
Note 4: All typical values are at TA

V

100
200

-40

=

0.45

-1.5

40

Vee

V
V

6.1

1

Vee = Max

-1.5

-1.1
1

TA = 25°

-1.5
2.4

TA = 125°C

Vee = Max

TA

=

Units

0.8

3.4

0.2

Vee = 5V, 10 = 40 mA, TA = 25°C

Max

2
0.8

VIL = 0.8V

Io (off)

0575114

Typ
Max
Min
(Note 4)

~

c
en
~

U1

Electrical Characteristics Over recommended operating free-air temperature range (unless otherwise noted)
Symbol

........

U1

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Officel
Distributors for availability and specifications.

mA

~

"'I::t'
,....
,....

Ln
I'

Switching Characteristics Vee =

5V, TA = 25°C

(/)

o
......
"'I::t'
,....
,....

Ln
Ln

Symbol
tpLH

Propagation Delay Time,
Low-to-High-Level Output

tpHL

Propagation Delay Time
High-to-Low-Level Output

0575114

0555114

Conditions
Min

(/)

o

Parameter

CL = 30 pF, (Figure 1)

Max

20

15

30

ns

20

11

30

ns

Max

15
11

Min

Units

Typ

Typ

AC Test Circuit and Switching Time Waveforms

PULSE
GENERATOR
(NOTE 1)

Tl/F/578S-3
Note 1: The pulse generator has the following characteristics: ZOUT
tw = 100 ns, PRR = 500 kHz.

=

son,

Note 2: CL includes probe and jig-capacitance.

s; 5 ns
JV----~---+~----------------~

INPUT
OV

VOH

y
OUTPUT
VOL
VOH

Z

~Hl~
1.5V

OUTPUT

'Pl)
1.5V

VOL
TLIF/578S-4

FIGURE 1

1-126

Typical Performance Characteristics *
Output Voltage vs Data
Input Voltage

6

Output Voltage vs Data
Input Voltage

N6LO~D

N6

_TA"25'C

'"

~>

VC~" 5.lv Jcr 5V

___

'"

~

t

I
I

...
...=>=>

LO~D

f- VCC"5V

l

TIA"I~5'C T~' 2~'e

>

TA' 55'C- t--

~

vCC" 4.5V

CI

~

....

'"

~>

...=>
~
I

I

I

:z:

CI

CI

CI

>

>

o

>

o

o

o

-20

-40

-60

-80 -100 -120

10H - OUTPUT CURRENT (mA)

VI - DATA INPUT VOLTAGE (V)

VI- DATA INPUT VOLTAGE (V)

TL/F/5786-5

Low Level Output Voltage
vs Output Current

Output Voltage vs Free-Air
Temperature

TA" 25'C

~

....

'"<
~
>

~....
I

O.l

0.2

V

0.1

>

o

V

Vec"5.5~

~

/1.
VCC" 4.5V

~~

l/

....

l.6

!

l.Z

'"
~
;:::

2.8
2.4

~

..--+--±""""I,..000"""",::::j..--:-:-1--:-:;--;

2 I--+--+-"::':':'-F"-r---,,-+---i

5

1.6

o

1.2 1--+--+-+--+--+----<1--+_-1

~

0.8

I

~V

CI

..--+--t-I-+--+---1f-;--;
I-+-+-t-+-t-I-+-I
VOL (lOL =40 mAl

0.4

V
10

20

30

40

50

60

70

80

-75 -50 -25

10L - OUTPUT CURRENT (mA)

0

25

50

Vce" 5V
(FIGURE 11
30

>-

g

20

~
;:::
~

10

i

OL-...L..-L._L......L..-L.--lI....-...1-...J

o

Propagation Delay Times vs
Free-Air Temperature

40

4.--...--r-r--"'T""'--'---';--"'T""'-'

0.4

/
tPlH ~ 1/

I-- ~

I
t~HL

-

o
-75 -50 -25

75 100 125

0

25

50

75 100 125

TA - FREE·AIR TEMPERATURE ('C)

TA - FREE·AIR TEMPERATURE ('Cl

TL/F/5766-6

Supply Current (Both Drivers)
vs Supply Voltage

Supply Current (Both Drivers)
vs Free-Air Temperature
42

10

;c

70

.5

...z

60

a::
a::
=>
u
>....

50

...=>

'"uI
u

NO LOAD
TA = zrC

.5

...

INPUTS GROUNDEo...

40
30
20

/

10

o

;c

~

~

LIj'UTjOPT-

~

o
VCC - SUPPLY VOLTAGE (V)

i
=>

J4

u

32

'"uI

I
I

;c

40 _INPUTS GROUNDED
OUTPUTS OPEN
38

>....

V~C = ~V

36

~

-

~

30
-75 -50 -25

Supply Current (Both Drivers)
vs Frequency
"'"
Vee' 5V' ....

100

.........

"

.5

...z

60

a:
a::
=>

60

7~

u

~

r--....

1\

~
I
u
u

~

RL' ..
CL' 30 pF
INPUTS =3V SQUARE WAVE
TA' 25'C

-

40

I20

o
0

25

50

75 100 125

TA - FREE·AIR TEMPERATURE ('Cl

0.1

0.4

1

10

40

100

f - FREQUENCY (MHz)

TLlF/5786-7

"Oala for lemperatures below O'C and above 70'C and for supply voltages below 4.75V and above 5.25V are applicable to OS55114 circuits only. These
parameters were measured with the active pull-up connected to the sink output.

1-127

0555114/0575114
fA

n

:::T

CD

3D)

,.
C:;"

c

Di"
cc

...

D)

C

3

INPUTS
B--A-'

~1, ~6,
11)

Iii
I»

TO OTHER
DRIVER

o

~

?(S, 9)

o

1;0)

!!!!.aVec

1k

I\)

CD

(4,12)

(1,15)

AND
PULL·UP

NAND
PULL·UP

ZP

YP
(3,13)

(2,14)

AND
SINK OUTPUT
YS

NAND
SINK OUTPUT
ZS

500
,

,~

Resistor values shown are typical and in ohms.

, ,

,

"~

,

"

(8) 0 GND
TL/F/5786-2

~.
(1)

~

c

en

~National

U1
U1
-'"
-'"
U1

~ Semiconductor

"-

c

en

......

OS55115/0S75115 Dual Differential Line Receiver

U1
-'"
-'"

U1

General Description

Features

The OS55115/0S75115 is a dual differential line receiver
designed to sense differential signals from data transmission lines. Designed for operation over military and commercial temperature ranges, the OS55115/0S75115 can typically receive ± 500 mV differential data with ± 15V common-mode noise. Outputs are open-collector and give TTL
compatible signals which are a function of the polarity of the
differential input signal. Active output pull-ups are also available, offering the option of an active TTL pull-up through an
external connection.

•
•
•
•
•
•
•
•

Single 5V supply
High common-mode voltage range
Each channel individually strobed
Independent response time control
Uncommitted collector or active pull-up option
TTL compatible output
Optional 130n termination resistors
Direct replacement for 9615

Response time may be controlled with the use of an external capacitor. Each channel may be independently controlled and optional input termination resistors are also
available.

Connection Diagram

Function Table

Dual-ln-L1ne Package
vee

2YS

2YP

2
2 RESP
STRB TIME CONT

B2

Strobe
2RT

A2

L
H
H

Dlff.
Input

X
L
H

Output
H
H
L

H = VI 
500

7k

;r 4:

':'

':"

INPUT B

130

~~
r

29

,

150

~
150

-:.:

I~vcc II

I

500- ..

-

~~

~~

I

I
I
I
_ _ _ .J

20
~

PULL·UP
YP

• 5k

'*

rr:
3k

SINK
OUTPUT
YS

~

r----'
I
I
I
I

~,

150

1.5k

':"

~

I

150

L~

COMMON TO
BOTH RECEIVERS
TLIF/5787-2

1-131

U1

.......

c

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for the actual device
operation.

Note 5: Unless otherwise noted, VSTROBE
connected to the sink output.

c
en
.....
.....
U1
U1

en
.....
U1
.....
.....
U1

Ln
,...
,...
Ln
.....
tJ)

Typical Performance Characteristics (Note 3)

c

Input Current vs Input
Voltage

........
Ln
,...
,...

1 .L J J J. J V

VCC" 5V
INPUT NOT UNOER TEST AT O~rT~ "25°C

Ln
Ln

V

tJ)

C

...c
w

...>
~

/

:>

/

I

co

>

1//

I

3.2

2.8

-

2.4

1.2

~ ..,1'"'-

~

"N-IVC~

~...
w
~

-,"

VCC" 5V

co

0.4 f- VOL (VIO" 0.5V,IOL "15 mAl

>

~

-10

-20

-30

...w~
~

...

~
...

r

I
I
I

~V

,/

0.1

-0.1

......
~
>

~

~

30

-0.2

r--VCC·5V

~

~
I

u
u

10

Vs - STROBE INPUT VOLTAGE (V)

VCC - SUPPLY VDLTAGE (V)

Propagation Delay Times
vs Temperature
30

r-

:!
'"
w
::!l

i=

>-

20

g

15

i!i

10

o
1234511.

\

o

35

25

~

20

I

:-f-T~ - 25°C

>

a:
a:

:>
u

TA--55°C- t-- r--

I

30

0.2

Vcc-a.5V
NO LOAD
VIO - 0.5V

moc

co

...z
w

D

~

Supply Current (Both Receivers)
vs Temperature

.!

30

0.1

= ~~

~

40

40

...:!!

...w
~>

Vs - STROBE INPUT VOLTAGE (V)

C

50

-0.1

VIO - DIFFERENTIAL INPUT VOLTAGE (V)

Output Voltage vs
Strobe Input Voltage

VCC-4.5V~

0.2

I

u
u

25

VIO" 0.5VTA - Z5°C

VCC D 5.5V

o

10

ill

20

N~ LO~D
~

Supply Current (Both Receivers)
vs Supply Voltage

~

15

Output Voltage vs
Strobe Input Voltage

VIO - DIFFERENTIAL INPUT VOLTAGE (V)

>-

co

>

0.1

TA" -5SoC

TA-Z5°C

I

I

-0.2

i

:>

co

LOAD - 2k TO VCC
TA " 25°C

TA~125°C

...
~

IOL - LOW LEVEL OUTPUT CURRENT (mA)

~

I

co

>

...
~
>

o

~

~

.!

VCC - S.5V

~

10

J

VCC- UV

VCC ·5V
LOAD· 2k t. VCC

~

>

>

C

,-1

Output Voltage vs
Differential Input Voltage

>

-50

~ VCC"5V-

5 10 15 20 25

w

/

I

-40

VCC-5.5~

~ID~IV
-25 -20 -15 -10 -5 0

VIC - COMMON-MODE INPUT VOLTAGE (V)

VCC·~

0.2

Output Voltage
vs Differential Input Voltage
I
I
I

>

15 100 125

0.3

IDH - HIGH LEVEL OUTPUT CURRENT (mA)

~

50

J .l

VIO - 0.5V
TA" 25°C

...co

l

o

~

>
~

~

~

o

25

-=

Low Level Output Voltage
vs Output Current

...wcc

"

I

:z:
co

a

~ 0.4

r- , l
~\

~

~ VIO"-IV

I

TA - AMBIENT TEMPERATURE (OC)

VIO" -0.5V
TA" 25°C

::

-I 1

co

D••

L~

r- VCC.:'5V- f-VCC "4.5V

~

1.1

~

"

-

~

High Level Output Voltage
vs Output Current

...w
~
>

VCC" i.5V

...w
~>

-l--t-t"I

2

VI -INPUT VOLTAGE (V)

~

~

" ~ (VI~" -~.5V,IIOH ~ -5 ~A)

0
-15 -50 -25

5 10 15 20 25

NO LOAD
TA" 25°C

VCC"4.5V

3.4

~

~

yV

-I
-25 -20-15 -10 -5 a

Output Voltage vs
Common-Mode
Input Voltage

Output Voltage vs
Temperature

~

VCC· 5.5V
B INPUT AT 5.5V

i

A1Pu~ATIV

-15 -50 -25

0

25

50

15 100 125

TA - AMBIENT TEMPERATURE rc)

25

VCC·5V
(FIGURE 2B)
I

..!

-'.

tpHL (RL "39~

-W

20
15
10

r/

~

~

tpLH (RL • Uk)

I"

~

r--

o
-15 -50 -25

0

25

50

15 100 125

TA - AMBIENT TEMPERATURE (OC)

TL/F/5787-4

1-132

c
en

Frequency Response Control

U1
U1

Frequency Response as a
Function of Capacitance
10M
1M

U1

........

Vee - 5V
TA- 25'C

C

en

'"

I'

U1

-4
-4

,

~ lOOk

~

-4
-4

10k

U1

I'

I

Ik

TlIF/5787-5

Note: CR (response control)
times of the output.

> 0.01 JLF may cause slowing of rise and fall

'"

100
0.001

10

0.1

0.01

CR - CAPACITANCE (PFI
TL/F/5787-6

AC Test Circuit and Switching Time Waveforms
OPEN

2.4V

.-_"""""-,JO-~~'-OVo

TL/F/5787-7

Note 1: The pulse generator has the following characteristics: ZOUT

=

500, PRR

=

500 kHz/tw

=

100 ns

Note 2: CL includes probe and test fixture capacitance
tf~5ns
3V--~r-----------~.

DIFFERENTIAL
INPUT

90%

3V

VOH

DV

OV

10%

10% _ _ ___

~tPHL
--l tPlH

OUTPUT

1.5V

I.SV

VOL--TL/F/5787-8

FIGURE 1. Propagation Delay Time

Typical Application
Basic Party-Line or Data-Bus Differential Data Transmission

TWISTED
PAIR
LINE

=c=:t::

::::t>---

DS75113 DRIVER

DS75115 RECEIVER

·ZO is internal to the 0855115/0875115
A capacitor may be connected in series with Zo to reduce power dissipation.

1-133

TL/F/5787-3

....
C\I

~ ~National

e
.... D

Semiconductor

....
C\I

:g OS55121/DS75121 Dual Line Drivers
U)
c

General Description

Features

The OS55121 10575121 are monolithic dual line drivers designed to drive long lengths of coaxial cable, strip line, or
twisted pair transmission lines having impedances from 50n
to 500n. Both are compatible with standard TTL logic and
supply voltage levels.

• Designed for digital data transmission over 50n to
500n coaxial cable, strip line, or twisted pair transmission lines

The 0555121/0575121 will drive terminated low impedance lines due to the low-impedance emitter-follower outputs. In addition the outputs are uncommitted allowing two
or more drivers to drive the same line.
Output short-circuit protection is incorporated to turn off the
output when the output voltage drops below approximately
1.5V.

Connection Diagram

Typical Performance
Characteristics

Dual-In-Llne Package
Vee

E2

F2

02

C2

82

V2

A2

• TTL compatible
• Open emitter-follower output structure for party-line
operation
• Short-circuit protection
• AN~-OR logic configuration
• High speed (max propagation delay time 20 ns)
• Plug-in replacement for the SN55121 15N75121 and the
8T13

Output Current vs Output Voltage
16

15

14

-300

Jcc ! 5.~V

~

-250

VIH • 2.0VTA ·25'C

III

-200

.s.
ta::
a::

"I\.

~ -150

\

5

~
c

-100

I

.2 -50

o 0.5

~

\

to- 1-1-

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Vo - OUTPUT VOLTAGE (V)

Al

81

Cl

01

El

Fl

GNO

VI

TL/F/5788-2

TLlF/5788-1

Top View
Order Number DS55121J, DS75121J or DS75121N
See NS Package Number J16A or N16A

Truth Table
Inputs

AC Test Circuit and Switching
Time Waveforms
l.OV

F

Output
V

C

D

H

H

H

X

X

H

X

X

X

H

H

H

A

B

H

X

E

All Other Input
Combinations

L

H=High Level, L=Low Level, X=lrrelevant

)--+--.....- -.....-0 OUTPUT
CL

(NOTE 2)

TLlF/5788-3

Note 1: The pulse generators have the following characteristics:
ZOUT :::: 50n, tw = 200 ns, duty cycle = 50%,

:s: S.On.
3.0V -l-J.~~~~
INPUT

OUTPUT
VOL

Ir, = tf = 5.0 ns.

TLlF/5788-4

Note 2: CL includes probe and jig capacitance.

1-134

c

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, Vcc

6.0V

Input Voltage

6.0V

Output Voltage

6.0V

Output Current

-75mA

Maximum Power Dissipation- at 25°C
Cavity Package
Molded Package

en

Operating Conditions

(Note 1)

Supply Voltage, Vcc
Temperature, TA
DS55121
DS75121

Min
4.75

Max
5.25

Units
V

-55
0

+125
+75

°C
°C

260°C

-Derate cavity package 9.1 mWI'C above 25'C; derate molded package

Electrical Characteristics Vcc = 4.75V to 5.25V (unless otherwise noted) (Notes 2 and 3)
Symbol

Parameter
High Level Input Voltage

VIL

Low Level Input Voltage

VI

Conditions

Min

Typ

Max

2.0

Input Clamp Voltage

Vcc

Units
V

= 5.0V, II = -12 mA
= 5.25V, VIN = 5.5V

0.8

V

-1.5

V

1

mA

II

Input Current at Max Input Voltage

Vcc

VOH

High Level Output Voltage

VIH

10H

High Level Output Current

Vcc = 5.0V, VIH = 4.75V, VOH
T A = 25°C (Note 4)

10L

Low Level Output Current

VIL

10(OFF)

Off State Output Current

Vcc

IIH

High Level Input Current

VI

= 4.5V

IlL

Low Level Input Current

VI

= O.4V

los

Short Circuit Output Current

Vcc

= 5.0V, T A = 25°C

-30

mA

ICCH

Supply Current, Outputs High

Vcc

= 5.25V, All Inputs at 2.0V, Outputs Open

28

mA

ICCL

Supply Current, Outputs Low

Vcc = 5.25V, All Inputs at 0.8V, Outputs Open

60

mA

Switching Characteristics Vcc =
Symbol
tpLH

tpHL

= 2.0V, 10H = -75 mA (Note 4)

2.4

= 2.0V,

V

-100

= 0.8V, VOL = O.4V (Note 4)
= OV, Vo = 3.0V

5.0V, T A

-0.1

-250

mA

-800

IlA

500

Il A

40

IlA

-1.6

mA

= 25°C
Typ

Max

Units

Propagation Delay Time,
Low-to-High Level Output

RL = 370, (See AC Test Circuit
and Switching Time Waveforms)

CL

= 15 pF

11

20

ns

CL

= 1000 pF

22

50

ns

Propagation Delay Time,
High-to-Low Level Output

RL = 370, (See AC Test Circuit
and Switching Time Waveforms)

CL

=

15 pF

8.0

20

ns

CL

=

1000 pF

20

50

ns

Parameter

Min

Conditions

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the - 55'C to
the 0875121. All typical values are for TA = 25'C and Vee = 5V.

N

en
.....
U1

....
....
N

10.2 mWI'C above 25'C.

VIH

....
....
.......
C

1371 mW
1280 mW

Lead Temperature (Soldering, 4 seconds)

U1
U1

+ 125'C temperature range for the 0855121

and across the O'C to

+ 70'C range for

Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: The output voltage and current limits are guaranteed for any appropriate combination of high and low inputs specified by the truth table for the desired
output.

1-135

~ r-------------------------------------------------------------------------------------~

C"II

~ ~ National

~

.
D Semiconductor
OS75123 Dual Line Driver
General Description

Features

The DS75123 is a monolithic dual line driver designed specifically to meet the 110 interface specifications for IBM System 360. It is compatible with standard TTL logic and supply
voltage levels.

• Meet IBM System 360 110 interface specifications for
digital data transmission over 50n to 500n coaxial cable, strip line, or terminated pair transmission lines
• TTL compatible with single 5.0V supply
• 3.11V output at IOH = -59.3 mA
• Open emitter-follower output structure for party-line
operation
• Short circuit protection
• AND-OR logic configuration
• Plug-in replacement for the SN75123 and the 8T23

The low-impedance emitter-follower outputs of the
DS75123 enable driving terminated low impedance lines. In
addition the outputs are uncommitted allowing two or more
drivers to drive the same line.
Output short-circuit protection is incorporated to turn off the
output when the output voltage drops below approximately
1.5V.

Connection Diagram

Typical Performance
Characteristics

Dual-In-Line Package
Vee
16

F2

E2
15

02

C2

82

A2

Y2

Output Current vs Output Voltage
-300

14

ee ~ 5.Jv
V1H = 2.0V TA = 25°C

J

<
-250
.§.
....
:::l

a:

g;

Co>
....

~o

-200

'\r\.

-150

~

-100

I'\

I

~

-50
-~t-

o

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Va - OUTPUT VOLTAGE (V)
TL/F/5790-3

lA

81

Cl

01

El

Fl

GNO

Yl

TL/F/5790-1

Top View

Truth Table
INPUTS

Order Number DS75123J or DS75123N
See NS Package Number J16A or N16A

AC Test Circuit and Switching
Time Waveforms

OUTPUT

A

B

C

D

E

F

V

H

H

H

H

X

X

H

X

X

X

X

H

H

H

All Other Input
Combinations

L

H = High level, L = Low level, X = Irrelevant
::; 5.0 os
3.0V
OUTPUT

INPUT

CL
(NOTE 2)
OUTPUT

":"

VOL
TL/F/5790-2

Note 1: The pulse generators have the following characteristics: ZOUT :::: 500, tw
= 50%.
Note 2: CL includes probe and jig capacitance.

1-136

= 200 ns, duty cycle

TLIF/5790-4

c

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, Vcc
Input Voltage
Output Voltage

Supply Voltage, Vcc
High Level Output Current,
10H
Temperature, TA

7.0V
5.5V
7.0V

Maximum Power Dissipation· at 25·C
Cavity Package
Molded Package
Operating Free-Air Temperature Range

en
........

Operating Conditions

(Note 1)

U1

Min

Max

Units

.....

4.75

5.25
-100

V

W

rnA

+75

·C

0

1371 mW
1280 mW
O·Cto +75·C

- 65·C to + 150·C
Storage Temperature Range
Lead Temperature (Soldering, 4 seconds)
260·C
"Derate cavity package 9.1 mW/'C above 25'C; derate molded package
10.2 mW/'C above 25'C.

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Conditions

Min

Typ

Max

2.0

Units

VIH

High Level Input Voltage

V

VIL

Low Level Input Voltage

VI

Input Clamp Voltage

Vcc = 5.0V, II = -12 mA

-1.5

V

II

Input Current at Max Input Voltage

Vce = 5.25V, VIN = 5.5V

1

mA

VOH

High Level Output Voltage

Vcc = 5.0V, VIH = 2.0V,

0.8

I TA =25·C

10H = - 59.3 mA, (Note 4) ITA = O·C to + 75·C

V

3.11

V

2.9

V

High Level Output Current

Vcc = 5.0V, VIH = 4.5V, TA = 25·C,
VOH = 2.0V, (Note 4)

VOL

Low Level Output Voltage

VIL = 0.8V, 10L = - 240 flA, (Note 4)

10(OFF)

Off State Output Current

IIH

High Level Input Current

IlL

Low Level Input Current

VI = O.4V

lOS

Short Circuit Output Current

Vec = 5.0V, TA = 25·C

-30

mA

ICCH

Supply Current, Outputs High

VCC = 5.25V, All Inputs at 2.0V, Outputs Open

28

mA

ICCL

Supply Current, Outputs Low

Vcc = 5.25V, All Inputs at 0.8V, Outputs Open

60

mA

Units

10H

-250

rnA

0.15

V

Vcc = 0, Vo = 3.0V

40

flA

VI = 4.5V

40

flA

-1.6

mA

Switching Characteristics Vcc =
Symbol
tpLH

tpHL

-100

-0.1

5.0V, TA = 25·C
Typ

Max

Propagation Delay Time, Lowto-High Level Output

RL = 50n, (See AC Test Circuit
and Switching Time Waveforms

CL = 15 pF

12

20

ns

CL = 100 pF

20

35

ns

Propagation Delay Time, Highto-Low Level Output

RL = 50n, (See AC Test Circuit
and Switching Time Waveforms

CL=15pF

12

20

ns

Parameter

Min

Conditions

25
ns
15
CL = 100 pF
1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: All currents into device pins are shown as positive, currents out of device pins shown as negative, all voltage values are referenced with respect to network
ground terminal, unless otherwise noted. All values shown as max or min on absolute value basis.
Note 3: MinImax limits apply across the guaranteed operating temperature range of O'C to + 75'C for 0575123, unless otherwise specified. Typicals are for Vce
= 5.0V, TA = 25'C. Positive current is defined as current into the referenced pin.
Note 4: The output voltage and current limits are guaranteed for any appropriate combination of high and low inputs specified by the truth table for the desired
output.
Note

1-137

I\)

oo::t
N

~ ~National

~ ~ Semiconductor
OS75124 Triple Line Receiver
General Description

Features

The OS75124 is designed to meet the input/output interface
specifications for IBM System 360. It has built-in hysteresis
on one input on each of the three receivers to provide large
noise margin. The other inputs on each receiver are in a
standard TTL configuration. The OS75124 is compatible
with standard TTL logic and supply voltage levels.

•
•
•
•
•
•

Built-in input threshold hysteresis
High speed ... typical propagation delay time 20 ns
Independent channel strobes
Input gating increases application flexibility
Single 5.0V supply operation
Plug-in replacement for the SN75124 and the 8T24

Connection Diagram and Truth Table
Dual-In-Line Package

Inputs
A
H
X
L
L
X
X

Output

Bt

R

S

y

H
X
X
X
L
L

X
L
H
X
H
X

X
H
X
L
X
L

L
L
H
H
H
H

H = high level, L = low level, X = irrelevant
tB input and last two lines of the truth table
are applicable to receivers 1 and 2 only

At

Bt

R2

S2

A2

B2

GND

Y2

TL/F/5792-1

Top View
Order Number DS75124J or DS75124N
See NS Package Number J16A or N16A

Typical Application
A -_ _
B

~ ---=-'---

95 COAXIAL CABLE

Y

TLIF/5792-2

1-138

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, Vee

7.0V

Input Voltage
A Input with Vee Applied
A Input with Vee not Applied
A, S, or S Input

7.0V
6.0V
5.5V

Output Voltage

7.0V

Output Current

±100 rnA

Maximum Power Dissipation· at 25°C
Cavity Package
Molded Package

1433 mW
1362 mW

Operating Temperature Aange

O°Cto +75°C

Storage Temperature Aange

- 65°C to + 150°C

Lead Temperature (Soldering, 4 seconds)

260°C

"Derate cavity package 9.6 mWI'C above 25"C; derate molded package
10.9 mWI"C above 25"C.

Operating Conditions
Min
4.75

Supply Voltage, Vee
High Level Output Current,
10H
Low Level Output Current,
10L
Operating Temperature, T A

0

Max
5.25
-800

Units
V
p,A

16

rnA

+75

°C

Electrical Characteristics (Notes 2 and 3)
Symbol
VIH

VIL

Parameter
High Level Input Voltage

Low Level Input Voltage

Conditions

Min

Typ

Max

Units

A,S,orS

2.0

V

A

1.7

V

A,S,orS

0.8

V

A

0.8

V

VT+ -VT-

Hysteresis

Vee

= 5.0V, T A = 25°C, A, (Note 6)

VI

Input Clamp Voltage

Vee

= 5.0V, II = -12 rnA, A, S, or S

-1.5

V

II

Input Current at Maximum
Input Voltage

Vee

= 5.25V, VIN = 5.5V, A, S, or S

1

rnA

0.2

0.4

I VI = 7.0V
I VI = 6.0V, Vee = OV

A
VOH

High Level Output Voltage

VIH
10H

VOL

Low Level Output Voltage

VIH = VIHMIN, VIL
(Note 4)

IIH

High Level Input Current

VI

= VIHMIN, VIL = VILMAX,
= -800 p,A, (Note 4)

V

5.0

rnA

5.0

rnA

2.6

V

= VILMAX, 10L = 16 rnA,

0.4

V

= 4.5V, A, S, or S

40

p,A

VI

= 3.11V, A

170

p,A

= O.4V, A, S, or S

-0.1

-1.6

rnA

-50

-100

rnA

72

rnA

IlL

Low Level Input Current

VI

los

Short Circuit Output Current

Vee

lee

Supply Current

Vee = 5.25V

Switching Characteristics TA =

= 5.0V, T A = 25°C, (Note 5)

25°C, nominal power supplies unless otherwise noted

Parameter

Conditions

Typ

Max

Units

tpLH

Propagation Delay Time, Low-to-High
Level Output from A Input

(See AC Test Circuit and Switching
Time Waveforms)

20

30

ns

tpHL

Propagation Delay Time, High-to-Low
Level Output from A Input

(See AC Test Circuit and Switching
Time Waveforms)

20

30

ns

Symbol

Min

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: All currents into device pins are shown as positive, currents out of device pins shown as negative, all voltage values are referenced with respect to network
ground terminal, unless otherwise noted. All values shown as max or min on absolute value basis.
Note 3: MinImax limits apply across the guaranteed operating temperature range of O"C to
= 5.0V, T A = 25"C. Positive current is defined as current into the referenced pin.

+ 75"C for 0575124, unless otherwise specified. Typicals are for Vce

Note 4: The output voltage and current limits are guaranteed for any appropriate combination of high and low inputs specified by the truth table for the desired
output.
Note 5: Not more than one output should be shorted at a time.
Note 6: Hysteresis is the difference between the positive going input threshold voltage,

1-139

VT +, and the negative going input threshold voltage, VT -.

III

~

N

u;
.....

AC Test Circuit and Switching Time Waveforms

(/)

c

Vee

2.6V

1------,
I

lN3064

)Qo--+--...----t~ OUTPUT

TL/F/5792-3

Note 1: The pulse generator has the following characteristics: ZOUT :::: 50n, tw

= 200 ns, duty cycle = 50%

Note 2: CL includes probe and jig capacitance.

~5.0

ns

2.6V-+-·r---__ooi
INPUT

OUTPUT
VOL - - - -

TL/F/5792-4

Typical Performance Characteristics
Output Voltage vs
Receiver Input Voltage
4.0

2

...

C!I

I I I
=5.OV
NO LOAD
3.0 f- TA =25°C

3.5 f- Vcc



~

;:)

VT _

VT +

c

I
0

>

1.0
0.5

o

o

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VI -INPUT VOLTAGE (V)
TL/F/5792-5

1-140

c
en
.......

~National

U1
....

D Semiconductor

I\)

U1
.......

c
en

.......

OS75125/0S75127 Seven-Channel Line Receivers

....
U1

I\)

.......

General Description

Features

The OS75125 and OS75127 are monolithic seven-channel
line receivers designed to satisfy the requirements of the
IBM System 360/370 input/output interface specifications.
Special low-power design and Schottky clamped transistors
allow for low supply current requirements while maintaining
fast switching speeds and high current TTL outputs. The
OS75125 and OS75127 are characterized for operation
from O·C to 70·C.

•
•
•
•
•
•
•

Meets IBM 360/370 I/O specification
Input resistance-7 kn to 20 kn
Output compatible with TTL
Schottky-clamped transistors
Operates from single 5V supply
High speed-low propagation delay
Ratio specification for propagation delay time, low-tohigh/high-to-Iow
• Seven channels in one 16-pin package
• Standard Vee and ground positioning on OS75127

Connection Diagrams
DS75125
Dual-In-Line Package
lY

16

lA

Vee
15

2A

3Y
14

3A

5V

4V

12

13

4A

5A

DS75127
Dual-ln-L1ne Package

6Y

11

6A

7Y

Vee

2Y

16

10

7A

GND

lA

IV
15

2A

2Y
14

3A

3Y

13

4A

4Y

12

5A

TLIF/5791-1

=

11

6A

6Y

7Y

10

7A

GND
TL/F/S791-2

Top View

Top View
logic:Y

5Y

logic:Y

A

=A

Order Number DS75127J or DS75127N
See NS Package Number J16A or N16A

Order Number DS75125J or DS75125N
See NS Package Number J16A or N16A

1-141

......
N

Absolute Maximum Ratings

T""

it)

......

en
c
......

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

it)

N

Maximum Power Dissipation" at 25°C (Note 2)
Cavity Package
1509 mW
Molded Package
1476 mW
"Derate cavity package 10.1 mWrC above 25'C; derate molded package
11.9 mW rc above 25'C.

Supply Voltage, Vee (Note 1)
7V
Input Voltage Range
DS75125
-0.15V to 7V
DS75127
-2Vt07V
Operating Free-Air Temperature Range
O°Cto 70°C
Storage Temperature Range
- 65°C to + 150°C
Lead Temperature (Soldering, 4 seconds)
260°C

T""

it)

......

en
c

Recommended Operating
Conditions
Min Typ Max Units
V
5
5.5
-0.4 mA

4.5
Supply Voltage, Vee
High-Level Output Current, IOH
Low-Level Output Current, IOL
Operating Free-Air Temperature, TA 0

16
70

mA
°C

Electrical Characteristics over recommended operating free-air temperature range (Note 3)
Symbol
VIH

Parameter

Conditions

High-Level Input Voltage

Typ
(Note 5)

Min

Max

1.7

Units
V

VIL

Low-Level Input Voltage

VOH

High-Level Output Voltage

Vee = 4.5V, VIL = 0.7V, IOH = -0.4 mA

0.7

VOL

Low-Level Output Voltage

Vee = 4.5V, VIH = 1.7V, IOL = 16 mA

0.4

0.5

V

IIH

High-Level Input Current

Vee = 5.5V, VI = 3.11V

0.3

0.42

mA

I'L

Low-Level Input Current

Vee = 5.5V, VI = 0.15V

-0.24

mA

los

Short-Circuit Output Current (Note 4)

Vee = 5.5V, Vo = OV

-18

-60

mA

rl

Input Resistance

Vee = 4.5V, OV, or Open,
!l.v, = 0.15Vt04.15V

7

20

ko.

Ice

Supply Current

Vee = 5.5V, IOH = -0.4 mA,
All Inputs at 0.7V

15

25

mA

Vee = 5.5V, IOL = 16 mA,
All Inputs at 4V

28

47

mA

Switching Characteristics Vee =

2.4

V
V

3.1

5V, TA = 25°C
Min

Typ

Max

Units

tpLH

Propagation Delay Time, Low-to-High-Level Output

7

14

25

ns

tpHL

Propagation Delay Time, High-to-Low-Level Output

10

18

30

ns

tpLH
tpHL

Ratio of Propagation Delay Times

0.5

0.8

1.3

ns

tTLH

Transition Time, Low-to-High-Level Output

1

7

12

ns

Symbol

Parameter

Conditions

RL = 4000., CL = 50 pF,
(See Figure 1)

1
12
ns
Transition Time, High-to-Low-Level Output
3
tTHL
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: For operation above 25'C free-air temperature, refer to Thermal Ratings for ICs, in App Note AN-336.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output should be shorted at a time.
Note 5: All typical values are at Vee = 5V, TA = 25'C.

1-142

c
en

Schematic (each receiver)

.......

....

U1

cV~CC__________. .__. .________________-e____________-e____~____-e~-4~-4~______-4~~~~2~~:~

I\)

U1

......

c
en
.......

....

U1
I\)

.......

A
INPUT

12k
NOM

GND

L-________________________________

~t_--------------------+_,_..}TOOTHER

CHANNELS

L _

~O::.ON~C~R~

_

-l
TL/F/S791-3

AC Test Circuit and Switching Time Waveforms
VCC

TLIF/S791-4

3V
INPUT
OV

100/0

VOH
OUTPUT
VOL
TL/F/S791-5

Note 1: The pulse generator has the following characteristics: ZOUT

= 50n,

PRR

= 5 MHz.

Note 2: CL includes probe and jig capacitance.
Note 3: All diodes are 1N3064 or equivalent.

FIGURE 1

1-143

•

......

N
.....
Typical Performance Characteristics
II)

......

U)

C

Voltage Transfer
Characteristics

........
II)

N

.....
II)

......

~

C

'"

U)

..~
>

~

Voltage Transfer
Characteristics
Vee' 5.5V

_ _ TA

I O'i-t-Httr-t-t--;

.
.

4

ct

31-t-I-I-Hf-f-1~HH-I

.'"

Vee -4.5V

co

:::>
u

~

/

/

z

/

0.1

I

ll-t-t-t-t-fl-I-H-1H-I

1/

TA = 2S'Cl--f--H--I-H-l-It--I

o l...!!NO~L~0l!!AD!....L-L~~:±!~::I:::::I
1
o

o~-L-L.~~~==~

o

1

0

.~
>

:::>

0.3

...>

0.2

I

co

>

30

Vee - SV
VI = SV
TA
2S'C

<'

=

/'

......

.

.§.

0.4

~
~

Supply Current vs
Supply Voltage

0.6
0.5

./

~

./

z

0::
0::

:::>
u

i

=

20

I

15

I I

10

u

0.1

ALL S£VEN CHANNELS
NO LOAD
TA
2S'C

25

I

10

15

20

3

4

5

I

ALL

~

INP~TS

I

-

AT4V

'J

v

...LA

0
5

2

,

A~L INP~TS I ~ 1,- I ATr~V

5

0
0

1

VI - INPUT VOLTAGE (V)

Low-Level Output Voltage
vs Output Current
<.:I

/

0

VI -INPUT VOLTAGE (V)

VI -INPUT VOLTAGE (V)

~

/

0.2

:::>

I

o

>

= 2S'C
/

.

:::>

11-+-t-t-I-H-~HHH

~~~:; l--l--l--l--hH-/-t---l

TA

0.3

0::
0::

>

2 i--r-;- TA = 2S',C__-+ff-++--t--t---l

,

1

t=~V~~IC":"=t.:5v;iL=t~~U---1-~

<.:I

I

co

>

Input Current vs
Voltage

0.4 Input

0

1

2

3

4

5

6

Vee - SUPPL Y VOLTAGE (V)

10 - OUTPUT CURRENT (mAl

TL/F/5791-6

1-144

c
en

~National

a

"'-'"U1"

Semiconductor

N

Q)

.......
C

en

"'"

OS75128/0S75129 Eight-Channel Line Receivers
General Description

Features

The OS75128 and OS75129 are eight-channel line receivers designed to satisfy the requirements of the input-output
interface specification for IBM 360/370. Both devices feature common strobes for each group of four receivers. The
OS75128 has an active-high strobe; the OS75129 has an
active-low strobe. Special low-power design and Schottkydiode-clamped transistors allow low supply-current requirements while maintaining fast switching speeds and high-current TIL outputs. The OS75128 and OS75129 are characterized for operation from O°C to 70°C.

•
•
•
•
•
•
•
•
•

U1

-'"

N
CD

Meets IBM 360/370 1/0 specification
Input resistance-7 kn to 20 kn
Output compatible with TIL
Schottky-clamped transistors
Operates from a single 5V supply
High speed-low propagation delay
Ratio specification-tpLH/tpLH
Common strobe for each group of four receivers
OS75128 strobe-active-high
OS75129 strobe-active-Iow

Connection Diagrams
DS75128
Dual-In-Line Package

DS75129
Dual-In-Llne Package

vee

IV

2Y

3Y

4Y

5Y

6Y

7Y

BY

2S

vee

IV

2Y

3Y

4Y

5Y

6V

7V

BY

2S

IS

lA

2A

JA

4A

5A

6A

7A

8A

GND

IS

lA

2A

JA

4A

5A

6A

7A

BA

GND

positive logic: Y

=

AS

TL/F/5793-1

positive logic: Y

= AS

TL/F/5793-2

Top View

Top View

Order Number DS75128J or DS75128N
See NS Package Number J20A or N20A

Order Number DS75129J or DS75129N
See NS Package Number J20A or N20A

1-145

•

en

C\I
.,..

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
7V
Supply Voltage, Vee
Input Voltage Range
-0.15Vto 7V
Strobe Input Voltage
7V
Maximum Power Oissipation- at 25°C (Note 2)
Cavity Package
1564 mW
Molded Package
1687 mW
Operating Free-Air Temperature Range
O°Cto + 70°C
Storage Temperature Range
- 65°C to + 150°C
Lead Temperature
300°C
V16 Inch from Case for 60 Seconds: J Package

Ln

.....

CJ)

c.......
co

C\I
.,..
Ln
.....
CJ)

c

260°C
Lead Temperature
1,1,6 Inch from Case for 4 Seconds: N Package
'Derate cavity package 10.4 mWrC above 25'C; derate molded package
13.5 mWrC above 25'C.

Recommended Operating
Conditions
Min Typ Max Units
V
4.5 5.0 5.5
Supply Voltage, Vee
-0.4 mA
High-Level Output Current, IOH
16
mA
Low-Level Output Current, IOL
Operating Free-Air Temperature, TA 0
70
°C

Electrical Characteristics over recommended operating free-air temperature range (Note 3)
Symbol
VIH

VIL

Min

Conditions

Parameter
High-Level Input Voltage

-

Low-Level Input Voltage

A

1.7

S

2

Typ
(Note 5)

0.7

A
~

High-Level Output Voltage

Vee = 4.5V, VIL = 0.7V, IOH = 0.4 mA

Low-Level Output Voltage

VI

Input Clamp Voltage

S Vee = 4.5V, II = -18 mA

IIH

High-Level Input Current

A

2.4

0.4

Vee = 4.5V, VIH = 1.7V, IOL = 16 mA

0.3

Vee = 5.5V, VI = 3.11V

A

Vee = 5.5V, VI = 0.15V

Short-Circuit Output Current
(Note 4)

Vee = 5.5V, Vo = OV

rl

Input Resistance

Vee = 4.5V, OV, or Open,

Icc

Supply Current

0.5

V

-1.5

V

0.42

mA

20

/-LA

-0.24

mA

-0.4

S Vee = 5.5V, VI = O.4V
los

V

3.1

S Vee = 5.5V, VI = 2.7V
Low-Level Input Current

V

0.7

VOL

IlL

Units
V

S
VOH

Max

-18
I:::.. V, =

0.15V to 4.15V

7

-60

mA

20

kO

19

31

Vee = 5.5V, Strobe at 0.4V, All A Inputs at 0.7V

19

31

Vee = 5.5V, Strobe at 2.4V, All A Inputs at 4V

32

53

OS75128

Vee = 5.5V, Strobe at 2.4V, All A Inputs at 0.7V

OS75129
OS75128

mA

53
OS75129
Vee = 5.5V, Strobe at 0.4V, All A Inputs at 4V
32
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: For operation above 25'C free·air temperature, refer to Thermal Ratings for ICs, in App Note AN-336.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output should be shorted at a time.
Note 5: All typical values are at Vee = 5V, TA = 25'C.

1-146

Switching Characteristics Vee =
Symbol

c
en

.......

5V, TA = 25°C

Parameter

Conditions

tpLH

Propagation Delay Time, Low-to-High-Level Output

tpHL

Propagation Delay Time, High-to-Low-Level Output

tpLH

Propagation Delay Time, Low-to-High-Level Output

tpHL

Propagation Delay Time, High-to-Low-Level Output

tpLH

Ratio of Propagation Delay Times

A

RL = 4000.,
CL = 50 pF,
See Figure 1

Units

Min

Typ

Max

Min

Typ

Max

7

14

25

7

14

25

ns

10

18

30

10

18

30

ns

26

40

20

35

ns

22

35

16

30

ns

0.5

0.8

1.3

0.5

0.8

1.3

A

S

0575129

0575126

U1
-"'"
N

co
C

........

en

.......

U1
-"'"
N

co

tpHL
tTLH

Transition Time, Low-to-High-Level Output

1

7

12

1

7

12

ns

tTHL

Transition Time, High-to-Low-Level Output

1

3

12

1

3

12

ns

Schematic Diagram

(each receiver)
~

150

t

VCC

NOM

V-

1NPUr

,..O-t---------J\lI/\r.-------+----4~
II

+-~,~T---~---~--' ~

.1' r;; ";~ .f)
~

:J-

OUTPUT
y

"J

~

~

1

OS7512;+9
~OS75128

-

.... --, I

t2k~1
NOM

I
I

:. I 1
I J"I.~+J

INPu~o-HI-1~+~':"'''HI-II''

:~~~ l~,

I
I

-~

r 1--------- ,

I

~

~

~

~

GNO

rll

II w~:I

I

L":~.J

ONE OF TWO

L _______n7 ____

I
J II ~
I ,....... ~

I
I
-~I

I

~;:~

I
I

~

I
I
L

COMMON
l!!!,C.!!!!,R:!..... _ _ _ _ _

JI

/';'7
TO THREE

''- _ _ _---.. __- - - - - J '

OTHER
CHANNELS

TOSEVEN
OTHER CHANNELS

TLIF/5793-3

1-147

III

AC Test Circuit and Switching Time Waveforms
OUTPUT

Vee
INPUT
(SEE NOTES
1,4, AND S)
OV

OUTPUT
TL/F/5793-4
VOL------~--I~----~~~

TL/F/5793-5

Note 1: Input pulses are supplied by a generator having the following characteristics: Zo

=

son, PRR

= 5 MHz.

Note 2: Includes probe and jig capacitance.
Note 3: All diodes are 1N3064 or equivalent.
Note 4: The strobe inputs of 0575129 are in-phase with the output.
Note 5: VREFl

=

0.7V and VREF2

=

1.7V for testing data (A) inputs, VREFl

=

VREF2

=

1.3V for strobe inputs.

FIGURE 1

Typical Characteristics
Voltage Transfer Characteristics
From A Inputs

Voltage Transfer Characteristics
From A Inputs
I-- riA

~

...

S
Vee= SV
NO LOAD

...
!::;
'"
...>

I

I

I

vee = S.SV

=sv

V~e

c.:I

I I

t-

--

~

TA"' DoC

-

c.:I

'"

!::;
Q
>

=170o~- 1--1--

Vee = 4.SV

Q

...

-- -- _ TA =2SoC-

::I

I!:
::I
Q

::I

I!:
::I
Q

I

I

Q

Q

>

>

o

TA = 2soe
NO LOAD

o

VI-INPUT VOLTAGE (VI

VI -INPUT VOLTAGE (V)
TLlF/5793-6

TL/F/5793-7

Low-Level Output Voltage
vs Output Current

Input Current vs
Input Voltage, A Inputs
0.4
C(

..s...

~

Vec =SV
NO LOAD
TA =2SoC

~'

~
a::
a::

::I

...

u

I

>

...

::I

1/

!:
.:

0.1

o

I
o

O.S

Vee =SV
VI"' SV
TA =2SoC

0.4

V"
./

I!:

/

~

~

Q

/

0.2

0.6

c.:I

)'
)'

0.3

...

...~...

0.3

;
i!=

0.2

::I

1/

...
Q

>
4
VI -INPUT VOLTAGE (V)

/'

~

",

0.1

0

o

10

1S

20

10 - OUTPUT CURRENT (rnA)
TLlF/5793-8

1-148

TL/F/5793-9

c

en
......

~National

U1

.....

D Semiconductor

U1

o

DS75150 Dual Line Driver
General Description

Features

The OS75150 is a dual monolithic line driver designed to
satisfy the requirements of the standard interface between
data terminal equipment and data communication equip·
ment as defined by EIA Standard RS·232·C. A rate of
20,000 bits per second can be transmitted with a full 2500
pF load. Other applications are in data·transmission sys·
tems using relatively short single lines, in level translators,
and for driving MOS devices. The logic input is compatible
with most TIL and LS families. Operation is from -12V and
+ 12V power supplies.

• Withstands sustained output short·circuit to any low im·
pedance voltage between - 25V and + 25V
• 2 J.Ls max transition time through the - 3V to + 3V tran·
sition region under full 2500 pF load
• Inputs compatible with most TIL and LS families
• Common strobe input
• Inverting output
• Slew rate can be controlled with an external capacitor
at the output
• Standard supply voltages
± 12V

Schematic and Connection Diagrams
+Vee 0 - + - - - . - - - - -.....- -.....- - . - . , - - - - - ,
TO OTHER
LINE DRIVER

11k

10k

15k

Dual-In-Llne Package

INPUTAo--........

+Vee

IV

2V

-Vee

STROBE
S

INPUT
lA

INPUT
2A

GND

STROBE S o-+-...- *....~.......-1
TO OTHER
LINE DRIVER

1 - -.....-___4H""'~~+-.f_4~-. .-___4"_O OUTPUT

GNDo-+---*--~

TO OTHER
LINE DRIVER

TLIF/5794-2

Top View
Positive Logic C = AS

47

TO OTHER
LINE DRIVER
-veeo-+------------~~--+-----~

TL/F/5794-1
Component values shown are nominal.
1/2 of circuit shown

1·149

Order Number DS75150J-8,
DS75150M or DS75150N
See NS Package Number
J08A, M08A or N08E

o
an
......
an

......

U)

c

Absolute Maximum Ratings

Operating Conditions

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (+ Vee)

Min
10.B

Max
13.2

Units
V

Supply Voltage (- Vee)

-10.B

-13.2

V

Supply Voltage + Vee

15V

Input Voltage (VI)

0

+5.5

V

Supply Voltage - Vee
Input Voltage

15V

Output Voltage (Vo)

±15

V

15V

Operating Ambient Temperature
Range (TA)

+70

°C

Applied Output Voltage
Storage Temperature Range
Maximum Power Dissipation* at 25°C
Cavity Package
Molded DIP Package
SO Package

+25V

0

- 65°C to + 150°C
1133 mW
1022mW
655mW

Lead Temperature (Soldering, 4 sec.)
260°C
"Derate cavity package 7.6 mWI"C above 25'C; derate molded DIP package
B.2 mWI'C above 25'C. Derate SO package B.01 mWI'C above 25'C.

DC Electrical Characteristics (Notes 2, 3,4 and 5)
Symbol

Parameter

Conditions

Min

VIH

High-Level Input Voltage

(Figure 1)

VIL

Low-Level Input Voltage

(Figure 2)

VOH

High-Level Output Voltage

+ Vee = 10.BV,-Vee = -13.2V, VIL = O.BV,
RL = 3 k!1 to 7 k!l (Figure 2)

VOL

Low-Level Output Voltage

+Vee = 10.BV,-Vee = -10.BV, VIH = 2V,
RL = 3 k!l to 7 k!l (Figure 1)

IIH

High-Level Input Current

+Vee = 13.2V,-Vee = -13.2V,
VI = 2AV, (Figure 3)

Data Input

+Vee = 13.2V, -Vee = -13.2V,
VI = 2.4V, (Figure 3)

Strobe Input

+Vee = 13.2V,-Vee = -13.2V,
VI = OAV, (Figure 3)

Data Input

+ Vee = 13.2V, - Vee = -13.2V,
VI = 0.4V, (Figure 3)

Strobe Input

+Vee = 13.2V,-Vee = -13.2V,
(Figure 4), (Note 4)

Vo = 25V

IlL

los

Low-Level Input Current

Short-Circuit Output Current

Typ

Max

Units

O.B

V

2

Vo = -25V

5

V

B

V

-B

-5

V

1

10

p.A

2

20

p.A

-1

-1.6

mA

-2

-3.2

mA

2

5

mA

-3

-6

mA

Vo = OV, VI = 3V

15

30

mA

Vo = OV, VI = OV

-15

-30

mA

+leeH

Supply Current From + Vee,
High-Level Output

+Vee = 13.2V, -Vee = -13.2V, VI = OV,
RL = 3 k!l, T A = 25°C, (Figure 5)

10

22

mA

-leeH

Supply Current From -Vee,
High-Level Output

+Vee = 13.2V, -Vee = -13.2V, VI = OV,
RL = 3 k!l, T A = 25°C, (Figure 5)

-1

-10

mA

+leeL

Supply Current From + Vee,
Low-Level Output

+Vee = 13.2V, -Vee = -13.2V, VI = 3V,
RL = 3 k!1, T A = 25°C, (Figure 5)

B

17

mA

Supply Current From -Vee,
Low-Level Output

+Vee = 13.2V, -Vee = -13.2V, VI = 3V,
-20
-9
mA
RL = 3 k!1, TA = 25°C, (Figure 5)
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified min/max limits apply across the O'C to + 70'C range for the DS75150. All typical values are TA = 25'C and + Vee = 12V,
-vee = -12V.
Note 3: All current into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown as
max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: The algebraic convention where the most-positive (least-negative) limit is designated as maximum is used in this data sheet for logic levels only, e.g., when
- 5V is the maximum, the typical value is more-negative voltage.

-leeL

1-150

AC Electrical Characteristics
Symbol

c
en
.....
U1
.....

(+Vee = 12V, -Vee = -12V, TA = 25°C)

Parameter

Conditions

tTLH

Transition Time, Low-to-High
Level Output

CL = 2500 pF, RL
(Figure 6)

= 3 kfl to 7 kfl,

tTHL

Transition Time, High-to-Low
Level Output

CL = 2500 pF, RL = 3 kfl to 7 kfl,
(Figure 6)

tTLH

Transition Time, Low-to-High
Level Output

CL

= 15 pF, RL = 7 kfl, (Figure 6)

tTHL

Transition Time, High-to-Low
Level Output

CL

= 15 pF, RL = 7 kfl, (Figure 6)

tpLH

Propagation Delay Time
Low-to-High Level Output

CL

= 15 pF, RL = 7 kfl, (Figure 6)

tpHL

Propagation Delay Time
High-to-Low Level Output

CL

= 15 pF, RL = 7 kfl, (Figure 6)

Min

Typ

Max

Units

0.2

1.4

2

J.Ls

0.2

1.5

2

JLs

40

ns

20

ns

60

ns

45

ns

U1

c

DC Test Circuits
+vcc

-vcc

~---~
TL/F/5794-3

TL/F/5794-4

Each input is tested separately.

FIGURE 1. VIH. VOL

FIGURE 2. VIL. VOH
+Vcc

JV

-Vee

~---~ ---

I

+Ios

I

L_

1

r

-

~Vo

:

.J--100

TLIF/5794-5

TL/F/5794-6

Note: When testing IIH. the other input is at 3V; when testing IlL. the other
input is open.

los is tested for both input conditions at each of the specified output conditions.

FIGURE 3. IIH. IlL

FIGURE 4.IOS
+Vcc

-Vcc

",,", ",,, ~ ~ ___ ~ t-I,,", -I",
V'~.
L -

I':'

---J

:=

Jk

"::?'

FIGURE 5.ICCH+. ICCH-. ICCL+. ICCL-

1-151

TL/F/5794-7

III

AC Test Circuit and Switching Waveforms
3V

PULSE
GENERATOR
(SEE NOTE 1)

>-+.......~-............o OUTPUT

t---.L--L_~

TL/F/5794-B

3V----4-~~~--~~

INPUT
OV
VOH

---------.J

VOL-----------4--~-----~

OUTPUT
TL/F/5794-9

Note 1: The pulse generator has the following characterstics:
duty cycle :5: 50%, ZOUT '" 50n.
Note 2: CL includes probe and jig capacitance.

FIGURES

Typical Performance Characteristics
Output Current vs
Applied Output Voltage
20

<"

15

...

10

.§.

ffi
a:
a:

B

...

-5

:;)

c

I

.2

-

VI =2.4~

-10

I-- RL = 7k
.... RL =3k-

""""
II

-15
-20
-25

-

-~::::~

I-- ~

:;)

:=

+Vcc = 12V
-Vce = -12V
TA = 25°C {

~VI
-15

=0.4V

-5

0

5

15

25

Vo - APPLlEO OUTPUT VOLTAGE (V)
TL/F/5794-10

FIGURE 7

1-152

c

en

.......

~National

U1

......

~ Semiconductor

U1
~

0575154 Quad Line Receiver
General Description
The OS75154 is a quad monolithic line receiver designed to
satisfy the requirements of the standard interface between
data terminal equipment and data communication equipment as defined by EIA Standard RS-232C. Other applications are in relatively short, single-line, point-to-point data
transmission systems and for level translators. Operation is
normally from a single 5V supply; however, a built-in option
allows operation from a 12V supply without the use of additional components. The output is compatible with most TTL
and LS circuits when either supply voltage is used.
In normal operation, the threshold-control terminals are
connected to the VCC1 terminal, pin 15, even if power is
being supplied via the alternate VCC2 terminal, pin 16. This
provides a wide hysteresis loop which is the difference between the positive-going and negative-going threshold voltages. In this mode, if the input voltage goes to zero, the
output voltage will remain at the low or high level as determined by the previous input.

tive-going threshold voltage to be above zero. The positivegoing threshold voltage remains above zero as it is unaffected by the disposition of the threshold terminals. In the failsafe mode, if the input voltage goes to zero or an open-circuit condition, the output will go to the high level regardless
of the previous input condition.

Features
• Input resistance, 3 k!l to 7 k!l over full RS-232C voltage range
• Input threshold adjustable to meet "fail-safe" requirements without using external components
• Inverting output compatible with TTL or LS
• Built-in hysteresis for increased noise immunity
• Output with active pull-up for symmetrical switching
speeds
• Standard supply voltage-5V or 12V

For fail-safe operation, the threshold-control terminals are
open. This reduces the hysteresis loop by causing the nega-

Schematic Diagram
COMMON TO 4 CIRCUITS

------1

VCC2

(NOTE)

Vee,

0-+--------.
5k

Rlo-~---~~~

GNO

0-.......--------,1-......

I
I
I
I
I
I
I

•
OUTPUT

INPUT O-4-..I\IItI'v-+-~

I

lk

I

IL

_ _ _ _ _ _ _ _ _ _ _ _ .J
TL/F/5795-1

Note: When using VCC1 (pin 15), VCC2 (pin 16) may be left open or shorted to VCC1. When using VCC2, VCC1 must be left open or connected to the threshold
control pins.

1-153

~

I.l)
.,..
I.l)

Absolute Maximum Ratings

en

If Military! Aerospace specified devices are required,

......

c

Operating Conditions

(Note 1)

contact the National Semiconductor Sales Office!
Distributors for availability and specifications.

Supply Voltage (Pin 15), (VCC1)
Alternate Supply Voltage
(Pin 16), (VCC2)
Input Voltage
Temperature, (TA)

Normal Supply Voltage (Pin 15), (VCC1)
7V
Alternate Supply Voltage (Pin 16), (VCC2)
14V
Input Voltage
±25V
Storage Temperature Range
- 65°C to + 150°C
Maximum Power Dissipation· at 25°C
Cavity Package
1433 mW
Molded DIP Package
1362 mW
Lead Temperature (Soldering, 4 seconds)
260°C
'Derate cavity package 9.6 mW I'C above 25'C; derate molded DIP package
10.9 mWI'C above 25'C; derate SO package 8.01 mWI'C above 25'C.

Min
4.5

Max
5.5

Units
V

10.8

13.2
±15
+70

V
V
°C

0

Electrical Characteristics (Notes 2,3 and 4)
Symbol

Parameter

Conditions

VIH

High-Level Input Voltage

(Figure 1)

VIL

Low-Level Input Voltage

(Figure 1)

VT+

Positive-Going Threshold Voltage

(Figure 1)

VTVT+-VT-

Negative-Going Threshold Voltage
Hysteresis

Min

Typ

Max

3

(Figure 1)
(Figure 1)

Units
V

-3

V

Normal Operation

0.8

2.2

3

V

Fail-Safe Operation

0.8

2.2

3

V

Normal Operation

-3

-1.1

0

V

Fail-Safe Operation

0.8

1.4

3

V

Normal Operation

0.8

3.3

6

V

0

0.8

2.2

V

2.4

3.5

Fail-Safe Operation
VOH

High-Level Output Voltage

IOH= -400 /-tA, (Figure 1)

VOL

Low-Level Output Voltage

IOL = 16 mA, (Figure 1)

rl

Input Resistance

(Figure 2)

V

0.23

0.4

V

tlVI= -25Vto -14V

3

5

7

k!1

tlVI= -14Vto -3V

3

5

7

k!1

tlVI= -3V to +3V

3

6

tlVI=3Vto 14V

3

5

7

k!1

tlVI= 14Vto 25V

3

5

7

k!1

0

0.2

2

V

-10

-20

-40

mA

k!1

VUOPEN)

Open-Circuit Input Voltage

II = 0, (Figure 3)

los

Short-Circuit Output Current
(Note 5)

VCC1 =5.5V, VI= -5V, (Figure 4)

ICC1

Supply Current From VCC1

VCC1 =5.5V, TA=25°C, (A'gure5)

20

35

mA

ICC2

Supply Current From VCC2

Vcc2=13.2V, TA=25°C, (Figure 5)

23

40

mA

Typ

Max

Switching Characteristics
Symbol

(VCC1 = 5V, T A = 25°C)

Parameter

Conditions

tpLH

Propagation Delay Time, Low-to-High
Level Output

CL = 50 pF, RL = 390!1, (Figure 6)

tpHL

Propagation Delay Time, High-to-Low
Level Output

CL = 50 pF, RL = 390!1, (Figure 6)

tTLH

Transition Time, Low-to-High Level
Output

CL = 50 pF, RL = 390!1, (Figure 6)

Min

Units

22

ns

20

ns

9

ns

Transition Time, High-to-Low Level
CL = 50 pF, RL = 390!1, (Figure 6)
6
ns
Output
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the O'C to +70'C range for the 0575154. All typical values are for TA = 25'C and VCC1 =5V.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: The algebraic convention where the most·positive (Ieast·negative) limit is designated as maximum is used in this data sheet for logiC and threshold levels
only, e.g., when -3V is the maximum, the minimum limit is a more·negative voltage.
Note 5: Only one output at a time should be shorted.

tTHL

1-154

Typical Performance Characteristics

c
en
.......
U1
.....

Connection Diagram

U1

Dual-In-Line Package
Output Voltage vs
Input Voltage

ALT
Vcc ,

4
I
3 f - - f--

FAIL!SAFE
OPERATION

TI6

I--

(NOTE 3)

NORMAL I
i--OPEIRATlr l -

1

I

I

0

1

2Y

13

114

lY

12

)

e--

-2

-1

10

2

19

~~

0

-3

RI

4Y

11

I

U

VT+

-VT

VT-I

\

I

I

2

I~

~

OUTPUTS

THRESHOLD
NORM
CONT I
4T
Vee1
IY

3

I

INPUT VOLTAGE (V)

II

TL/F/5795-10

3T

4

1

2

I

\

5

IA

IT

2T

6

3A

2A

7

8

1
4A

GND

\

THRESHOLD
CONTROLS

Y"A

INPUTS
TL/F/5795-2

Top View
Order Number DS75154J, DS75154M or DS75154N
See NS Package Number J16A, M16A or N16A

DC Test Circuits and Truth Tables

;LG,n.
01l·2V

5.5V O

" ..45V
0

OIOBV
OPEN

rT
A

V,. VT

-

IS

16

- Vee1

VCC2

L ___

.J.Al-,

*___
-

YI
I

{

..J

',.

:I'~

Till
',. - j ~

li_i
-= -= -= -=

TL/F/5795-3

Measure

A

T

Y

VCC1
(Pin 15)

VCC2
(Pin 16)

Open-Circuit Input
(Fail-Safe)

VOH
VOH

Open
Open

Open
Open

IOH
IOH

4.5V
Open

Open
10.8V

VT+ min,
VT - (Fail-Safe)

VOH
VOH

O.8V
O.8V

Open
Open

IOH
IOH

5.5V
Open

Open
13.2V

VT + min (Normal)

VOH
VOH

(Note 1)
(Note 1)

Pin 15
Pin 15

IOH
IOH

5.5VandT
T

Open
13.2V

VIL max,
VT - min (Normal)

VOH
VOH

-3V
-3V

Pin 15
Pin 15

IOH
IOH

5.5VandT
T

Open
13.2V

VIH min, VT + max,
VT - max (Fail-Safe)

VOL
VOL

3V
3V

Open
Open

IOL
IOL

4.5V
Open

Open
10.8V

VIH min, VT + max,
(Normal)

VOL
VOL

3V
3V

Pin 15
Pin 15

IOL
IOL

4.5VandT
T

Open
10.8V

VT - max (Normal)

VOL
VOL

(Note 2)
(Note 2)

Pin 15
Pin 15

IOL
IOL

5.5VandT
T

Open
13.2V

Test

Note 1: Momentarily apply -5V, then O.BV.
Note 2: Momentarily apply 5V, then ground.

FIGURE 1. VIH, VIL, VT+, VT-, VOH, VOL

1-155

DC Test Circuits and Truth Tables

(Continued)

Open
Open
Open
Pin 15
Gnd
Open
Open
Pin 15
Pin 15
Pin 15

">O_-""";'+-OOPEN

L ___ ~ ___ --1

VCC2

VCC1

T

(Pin 15)

(Pin 16)

5V
Gnd
Open
Tand 5V
Gnd
Open
Open
T
T
T

Open
Open
Open
Open
Open
12V
Gnd
12V
Gnd
Open

TL/F/5795-4

FIGURE 2. rl

5'5V~~-J

O--013.2V

VCC1

T
OPEN

15
-Vcc •

-

16
-

VCC2-

___ *___

L

Open
Pin 15
Open
Pin 15

Rll

x ......-~+-oO OPEN

~

VHOPENI

L

VCC2

(Pin 15)

(Pin 16)

5.5V
5.5V
Open
T

Open
Open
13.2V
13.2V

--lI
TLlF/5795-5

FIGURE 3. VI(OPEN)

5'5VJt~

j~:

OPEN
51:.
~Vo---~

~

-Vcc.

-

_ _ _ _~

Icc.

OPt

OPEN!

VCC2-Rll
~~

-J

IT -

_____
V~

V

O--013.2V
Icc2

! OPEN

15
cc •

16
-

5Vo--~~ ~------1

VC C2-

L

Rll

">O---+-oO OPEN

TLlF/5795-6
TL/F/5795-7

Each output is tested separately.

FIGURE 4. los

All four line receivers are tested simultaneously.

FIGURE 5. ICC

1-156

c
en
.......
(J1
.....
(J1

AC Test Circuit and Switching Time Waveforms
INPUT

5V

~

OUTPUT

OPEN

OPEN

..1

.J.

VCC2

Rl

16_

I

PULSE
GENERATOR .......-+.......
(NOTE 1)

L_--

ALL DIODES ARE lN3064

.J

I

T

CL

= 50 pF

(NOTE 2)

TLIF/5795-6

-10 ±2 ns
5V

INPUT

OV
-5V

90%

10 ± 2 ns
90%

10%
tpLH

VOH

OUTPUT

2V

2V

VOL
TLiF/5795-9

Note 1: The pulse generator has the following characteristics: ZOUT=50n, tw=200 ns, duty cycle
Note 2: CL includes probe and jig capacitance.

FIGURE 6

1-157

:s:

20%.

le:(

c.o
......

.... ~National
Lt)

......

C/)

c
......
e:(

c.o

PRELIMINARY

~ Semiconductor
OS75176A/OS75176AT Multipoint

......
....
...... RS-485/RS-422 Transceivers
Lt)

C/)

c

General Description
The OS75176A is a high speed differential TRI-STATE®
buslline transceiver designed to meet the requirements of
EIA standard RS485 with extended common mode range
(+ 12V to -7V), for multipoint data transmission. In addition
it meets the requirements of RS422.
The driver and receiver outputs feature TRI-STATE capability, for the driver outputs over the entire common mode
range of + 12V to -7V. Bus contention or fault situations
that cause excessive power dissipation within the device
are handled by a thermal shutdown circuit, which forces the
driver outputs into the high impedance state.
The receiver incorporates a fail safe feature which guarantees a high output state when the inputs are left open.
Both AC and DC specifications are guaranteed over the 0 to
70°C temperature and 4.75V to 5.25V supply voltage range.

Features
• Meets EIA standard RS485 for multipoint bus transmission and RS422 .
• Small Outline (SO) Package option available for minimum board space.

• 22 ns driver propagation delays with 8 ns skew (typical).
• Single channel per package isolates faulty channels
(from shutting down good channels).
• Single + 5V supply.
• - 7V to + 12V bus common mode range permits ± 7V
ground difference between devices on the bus.
• Thermal shutdown protection.
• Power-up down glitch-free driver outputs permit live insertion or removal of transceivers.
• High impedance to bus with driver in TRI-STATE or
with power off, over the entire common mode range allows the unused devices on the bus to be powered
down.
• Pin out capatible with OS3695 and SN75176A.
• Combined impedance of a driver output and receiver input is less than one RS485 unit load, allowing up to 32
transceivers on the bus.
• 70 mV typical receiver hysteresis.

Connection and Logic Diagram

RO

Vee
...... 110-......,.:.- 00 j

Ri

OE

OOjRI

01

GNO
TL/F/8759-1

Top View
Order Number DS75176AN, DS75176AM,
DS75176AJ-8, DS75176ATN
See NS Package Number N08E, M08A or J08A

1-158

c
Absolute Maximum Ratings

en
.......

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Storage Temperature Range

Supply Voltage, Vee

7V

Control Input Voltages

7V

Recommended Operating
Conditions

Driver Input Voltage

7V

Driver Output Voltages

+ 15V/ -10V

Receiver Input Voltages (DS75176A)

+ 15V/ -10V

Receiver Output Voltage

Supply Voltage, Vee
Voltage at Any Bus Terminal
(Separate or Common Mode)
Operating Free Air Temperature TA
DS75176A
DS75176AT
Differential Input Voltage,
VID (Note 6)

5.5V

Continuous Power Dissipation @25°C
for M Package

675 mW (Note 5)

Continuous Power Dissipation @25°C
(for N Package)

900 mW (Note 4)

- 65°C to + 150°C

Lead Temperature (Soldering, 4 seconds)

260°C

Parameter

Min
4.75
-7

Max
5.25
+12

Units
V
V

0
-40

+70
+85

°C
°C
+12V

Conditions
10

VOD2

Differential Driver Output
Voltage (with Load)

(Figure 1)

t:.VOD

Min Typ Max Units

=0

Differential Driver Output
Voltage (Unloaded)

5
R
R

= 500.; (RS-422) (Note 4) 2
= 270.; (RS-485)
1.5

Driver Common Mode Output
Voltage

t:.lvocl

Change in Magnitude of Driver
Common Mode Output Voltage
For Complementary Output
States

VIH

Input High Voltage

Vil

Input Low Voltage

(Figure 1)

R

V

= 270.

0.2

V

3.0

V

0.2

V

2

VCl

Input Clamp Voltage

III

Input Low Current

IIH

Input High Current

liN

Input
Current

VTH

Differential Input Threshold
Voltage for Receiver

-7V ~ VCM ~ + 12V

DO/RI, DO/RI Vec = OV or 5.25V
DE = OV

= -18 mA
= O.4V
VIH = 2.4V
VIN = 12V
VIN = -7V
liN

-1.5

Vil

-200

-0.2

= OV
= -400 p,A
10l = 16 mA (Note 7)
10l = 8 mA
Vce = Max

t:.VTH

Receiver Input Hysteresis

VCM

VOH

Receiver Output High Voltage

10H

VOL

Output Low
Voltage

10ZR

OFF-State (High Impedance)
Output Current at Receiver

O.4V

RIN

Receiver Input Resistance

- 7V ~ VCM ~ + 12V

lec

Supply Current

LF

V
0.8

DI,DE,
RE, E

RO

V

V

Change in Magnitude of Driver
Differential Output Voltage For
Complementary Output States

Voe

~

Vo

~

1-159

p,A

20

p,A

+1.0

mA

-0.8

mA

+0.2

V

70

mV

2.4

V

2.4V

No Load
(Note 7)

l>

en
.......

Electrical Characteristics (Notes 2 and 3)
Symbol

0)

.......
C

O°C ~ T A ~ 70°C, 4.75V < Vec < 5.25V unless otherwise specified

VOD1

U1
.....
.......

0.5

V

0.45

V

±20

p,A

12

ko.

Driver Outputs Enabled

35

50

mA

Driver Outputs Disabled

27

40

mA

U1
.....
.......
0)

~

~
CD
......
,..
Il)

......

CJ)

c
.....
c:C

Electrical Characteristics (Notes 2 and 3)
O°C ::;: TA ::;: 70°C, 4.75V

Symbol
loso

CD

......
,..
Il)

......

CJ)

c

<

Vee

<

5.25V unless otherwise specified (Continued)

Max

Units

Vo = -7V (Note 7)

-250

mA

Vo = +12V(Note7)

+250

mA

Parameter

Typ

Min

Conditions

Driver Short·Circuit
Output Current

-85
mA
Receiver Short·Circuit
Vo = OV
10SR
-15
Output Current
Note 1: "Absolute Maximum Ratings" are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should
be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise
specified.
Note 3: All typicals are given for Vee = 5V and TA = 25'C.
Note 4: Derate linearly at 5.56 mWI'C to 650 mW at 70'C.
Note 5: Derate linearly @ 6.11 mW I'C to 400 mW at 70'C.
Note 6: Differential· Input/Output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
Note 7: All worst case parameters for which note 7 is applied, must be increased by 10% for D875176AT. The other parameters remain valid for -40'C < TA
< +B5'C.

Switching Characteristics 4.75V ::;: Vce ::;: 5.25V; O°C < T A < 70°C
Symbol

Parameter

Typ

Min

Conditions

Units

Max

22

ns

Driver Input to Output

RLOIFF = 60n
CL1 = CL2 = 100 pF

22

ns

ISKEW

Driver Output to Output

(Figures 3 and 5)

8

ns

Ir

Driver Rise Time

10

ns

If

Driver Fall Time

RLOIFF = 60n
CL1 =CL2 = 100 pF

10

ns

IZH

Driver Enable to Output High

CL = 100 pF (Figures 4 and 6) S 1 Open

35

ns

IZL

Driver Enable to Output Low

CL = 100 pF (Figures 4 and 6) S2 Open

35

ns

ILZ

Driver Disable Time from Low

CL = 15 pF (Figures 4 and 6) S2 Open

15

ns

1HZ

Driver Disable Time from High

CL = 15 pF (Figures 4 and 6) S 1 Open

15

ns

IpLH

Receiver Input to Output

25

ns

IpHL

Receiver Input to Output

CL = 15 pF (Figures 2 and 7)
S1 and S2 Closed

25

ns

IZL

Receiver Enable to Output Low

CL = 15 pF (Figures 2 and 8) S2 Open

15

ns

IZH

Receiver Enable to Output High

CL = 15 pF (Figures 2 and 8) S1 Open

15

ns

ILZ

Receiver Disable from Low

CL = 15 pF (Figures 2 and 8) S2 Open

12

ns

1HZ

Receiver Disable from High

CL = 15 pF (Figures 2 and 8) S1 Open

12

ns

IpLH

Driver Input to Output

IpHL

(Figures 3 and 5)

AC Test Circuits
DO

Ih
DO

RECEIVER

.~m

~

1

TEST
POINT

I

IINCLUDES PROBE
ANDJIO
CAPACITANCEl

.}
TL/F/8759-2

FIGURE 1

.,

,....
""

~

~,

-

AUOUIEI

11018011
IID4

U

It

~r

~

TLlF/8759-3

Note: 81 and 82 of load circuit are closed except as otherwise mentioned.
FIGURE 2

.-1«. f'~ l'' "' '
DE

!XI

=600

CL2=I00pl

~l.

-Vee

FROM OUTPUT
UNDER TEST

!

IiOOn

12

T

CL PROBE
IINCLUDES
ANDJIO
CAPACITANCEI ":'

TL/F/8759-4

FIGURE 3

":'

TL/F/8759-5

Note: Unless otherwise specified the switches are closed.
FIGURE 4
1·160

Switching Time Waveforms
3V----------------r-------------~~--~------------~
f = lMHz: II s100s
: If $100s
01

--------------1

OV

TL/F/8759-6

VO----------------~-----------V-D-,F-F=-V-D-O--V-OO------------~
OV--------------~I----------------------------------I~

-VO------""'I
TLlF/8759-10

FIGURE 5. Driver Propagation Delays

3V

s: IOns
:t, s: 10 ns

f = lMHz:tr

DE
OV
5V

00.

Do

Val

OUTPUT

NORMALLY lOW

VOH
00.

Do
OV

OUTPUT

NORMAllY HIGH

TLlF/8759-7

FIGURE 6. Driver Enable and Disable Times

VOH -----------------""'\

~.5V

RO

1.5V!

~I..-

VOL

IP:L

2.5V - - - - - - - - - - " ' "

OUTPUT

-11-s-l0-ns------------'IP~ 1-

---------f=-l-M-H-Z:

: If'" IOns
INPUT

RI·Ai

·2.5V ------------------ '-_________________________.1
TLlF/8759-8
Note: Differential input voltage may may be realized by grounding Ai and pulsing RI between

FIGURE 7. Receiver Propagation Delays

1-161

+ 2.5V and

- 2.5V

Switching Time Waveforms

(Continued)

3V-----~

1= lMHz:t,

~

: tf

S;

10ns
10 ns

ov----------L4-~-----------~~--------------J

~---------~~
RO
OUTPUT
NORMALLYLOW

'---------1

~----------+-.-------..._

VOL

_-----------1

~---------+_.-----'----

VOH

RO
OUTPUT
NORMALLY HIGH

OV--~~~~----J

TL/F/6759-9

FIGURE 8. Receiver Enable and Disable Times

Function Tables
DS75176A Transmitting
Inputs
RE

DE

01

X
X
X
X

1
1
0
1

1
0
X
X

Line
Condition

Outputs
DO

DO

No Fault
No Fault

0
1

1
0

X

Z
Z

Z
Z

Fault

DS75176A Receiving
Inputs

x-

Don't care condition

Z-

High impedance state

Fault -

Outputs

RE

DE

RI·Ri

RO

0
0
0
1

0
0
0
0

:?: +O.2V
:5: -O.2V
Inputs Open**

1
0
1
Z

X

Improper line conditons causing excessive power dissipation in the driver, such as shorts or bus contention situations

• 'This is a lail sale condition

Typical Application
OS75176A/OS3695/0S3696

OS3697/0S3698

OS75176A/OS3696

OS75176A

OS75176A
TL/F/6759-11

1-162

c

en

.......

~National

Q:)

N

~ Semiconductor

o
.......
C

OS7820/0S8820 Dual Line Receiver

o

en
Q:)
Q:)

N

General Description

Features

The OS7820, specified from - 55°C to + 125°C, and the
OS8820, specified from ooe to + 70°C, are digital line receivers with two completely independent units fabricated on
a single silicon chip. Intended for use with digital systems
connected by twisted pair lines, they have a differential input designed to reject large common mode signals while
responding to small differential signals. The output is directly compatible with TTL or LS integrated circuits.
The response time can be controlled with an external capacitor to eliminate noise spikes, and the output state is
determined for open inputs. Termination resistors for the
twisted pair line are also included in the circuit. Both the
OS7820 and the OS8820 are specified, worst case, over
their full operating temperature range, for ± 1O-percent supply voltage variations and over the entire input voltage
range.

•
•
•
•
•
•

Operation from a single + 5V logic supply
Input voltage range of ± 15V
Each channel can be strobed independently
High input resistance
Fan out of two with TTL integrated circuits
Strobe low forces output to "1" state

Connection Diagram
Dual-In-Line Package

INPUT

'-./
---+-----,

14

~vcc
1]

INPUT

TERMINATION - - -.....--,

INPUT

---+-......

STROBE

~
---t-.-..

RESPONSE TIME

12

TERMINATION

,-----i~--

11

"'""-1t--- INPUT

+j

---4

10

I----i~--

OUTPUT ---f--_.....J

_

9

STROBE

RESPONSE TIME

'----t~-- OUTPUT

GROUND - - - o f

TL/F/5796-2

Top View
Order Number DS7820J, DS8820J or DS8820N
See NS Package Number J14A or N14A

1-163

o

N

CO
CO

en
c
.......
o

N

Absolute Maximum Ratings

(Note 1)

CO
I"-

Supply Voltage

C

Input Voltage

±20V

Differential Input Voltage

±20V

en

Maximum Power Dissipation· at 25°C
Cavity Package
1308mW
1207 mW
Molded Package
"Derate cavity package 8.7 mWrC above 25°C; derate molded package
9.7 mWrC above 25°C.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
8.0V

Strobe Voltage

Operating Conditions

8.0V

Output Sink Current

Supply Voltage (Vce)
OS7820
OS8820
Temperature (TA)
057820
058820

25mA

Storage Temperature Range

- 65°C to + 150°C

Lead Temperature (Soldering, 4 sec.)

260°C

Min

Max

Units

4.5
4.75

5.5
5.25

V
V

-55
0

+125
+70

°C
°C

Units

Electrical Characteristics (Notes 2 and 3)
Symbol
VTH

Parameter
Input Threshold Voltage

Min

Typ

Max

VCM = OV

-0.5

0

0.5

V

-15V::;: VCM ::;: 15V

-1.0

0

1.0

V

5.5

V

Conditions

High Output Level

lOUT::;: 0.2 mA

VOL

Low Output Level

ISINK ::;: 3.5 mA

RI-

Inverting Input Resistance

RI+

Non-Inverting Input Resistance

RT

Line Termination Resistance

tr

Response Time

VOH

1ST

Strobe Current

2.5

TA = 25°C

0.4

0
3.6

5.0

1.8

2.5

120

170

COELAY = 0 pF

40

COELAY = 100 pF

150

VSTROBE = O.4V

-1.0

VSTROBE = 5.5V
IcC

IIN+

IIN-

Power Supply Current

Non-Inverting Input Current

Inverting Input Current

V
kO
kO

250

0
ns
ns

-1.4

mA

5.0

/1- A

VIN = 15V

3.2

6.0

mA

VIN = OV

5.8

10.2

mA

VIN = -15V

8.3

15.0

mA

VIN = 15V

5.0

7.0

mA

VIN = OV

-1.6

-1.0

VIN = -15V

-9.8

-7.0

VIN = 15V
VIN = OV
VIN = -15V

-4.2

mA
mA

3.0

4.2

mA

0

-0.5

mA

-3.0

mA

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: These specifications apply for 4.5V ~ VCC ~ 5.5V, -15V ~ VCM ~ 15V and - 55°C ~ T A ~ + 125°C for the DS7820 or O°C ~ T A ~ + 70°C for the
DS8820 unless otherwise specified; typical values given are for VCC = 5.0V, T A = 25°C and VCM = 0 unless stated differently.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: The specifications and curves given are for one side only. Therefore, the total package dissipation and supply currents will be double the values given when
both receivers are operated under identical conditions.

1-164

c

Typical Performance Characteristics

U'J

.......

(Note 3)

CO

Common Mode Rejection

~

~

...

...

0.2

'"~or

5

N

o

Transfer Function

"'C"

Vec - 5V
r- FAN OUT-2

0.4 t--+_t---+---If---+-_T-iA_-_2-t5°_C--t

U'J

'"
or

0

~ 0.2

I-

~

I-

....
or

~

> 0.1

~

>
55°C"

~

~

5

-0.1 I--t--I--+---If--+--'l=-....=I

4.5

5

!!;
-0.4
o

5.5

10

-10

SUPPL Y VOLTAGE (V)

o

125°C-

0' j'

t---+---If---+---I--+--+--+---I

-20

CO
CO

N

0"J~·

~

Ci

~

1-

25°C -

~

~ -0.2 1---+--+_+--+::.0

a:

•
'n

!1 r-

....
or

!t -0.2 1--t--I--+--If--f----1-4--l

..,...t:::..

~"'
;

J:S
-0.4

20

0.2

-0.2

0.4

DIFFERENTIAL INPUT VOLTAGE (V)

INPUT VOLTAGE (V)

TL/F/5796-4

~

4

Output Voltage Levels

Response Time

...

~>

~ -2
~

5

Vec- 5V
TA - 25°C

'"or
-4

~

r/

'"or~
o

-

Vee - 5.0V

~

~

1 I"\.

I

\

t~

OUlPUTlOW -

~

~

o

a

a

-

..J
0.2

0.4

- -

0.1

~
~

/
./

180

~

to.

"- r- ,., . /

170
160

o

0.8

0.6

190

i!i

>

I-

2DO

f-

t
>
~ 0.2

\

CdoIIY=O,

...

'"ct

I
I
\ ' Cdel.y = 100 pF

~

-~

...

-

~

OUTPUT H,IGH

Termination Resistance

-75 -50 -25

TIME Isa)

25 50

75 100 125

150
-75 -50 -25

0

25

50

75 100 125

TEMPERATURE (OC)

TEMPERATURE (OC)

TLlF/5796-5

10

Positive Supply Current

........

........

,-In_t..,e_r_n''Tal_p_orw_e,r_D-,is,-s_i..:.p_a_tiTo_n-,
Vee 2 5.0V
OUTPUT LOW

Vee = 5V

..........

......

i'

o

~lOIf.- - ]"0...

........

s. .........

,!tIC

-10

..s

~"/'p

....... r-..."'/'p,,/'

-2
-20

300

10

~

200

~H----I--+--+--+--+-+--~

a: 100

t---+-~r---+--+---,"""""-+'1J5t---i

III

;:

:E

~

~
Ci

~

........

~

-10

20

INPUT VOLTAGE (V)

10

20

INPUT VOLTAGE (V)
TL/F/5796-6

1-165

o

N
CO
CO

C/)

Typical Application

C

.......

o

N
CO

r--

C/)

C

TWISTED PAIR LINE

OUTPUT

tExact value depends on line length .
• Optional to control response time.
STROBE

TL/F/5796-3

Schematic Diagram
RESPONSE· TIME
CONTROL

NON.:~~~~TING _ . ._ _~.

OUTPUT

R7

as

170
TERMINATION

R4

R5

lK

lK

R14

750

.------....

..

----4~----

R2
167

..------..

IN~~~~~NG --yV\~---

...-----

--~

GROUNO

STROBE
TL/F/5796-1

1-166

c

en
.......

~National

(X)

N

~ Semiconductor

o

l>
......
C

en
(X)

DS7820A/DS8820A Dual Line Receiver

(X)

N

o

l>

General Description
The DS7820A and the DS8820A are improved performance
digital line receivers with two completely independent units
fabricated on a single silicon chip. Intended for use with
digital systems connected by twisted pair lines, they have a
differential input designed to reject large common mode signals while responding to small differential signals. The output is directly compatible with TTL or LS integrated circuits.
The response time can be controlled with an external capacitor to reject input noise spikes. The output state is a
logic "1" for both inputs open. Termination resistors for the
twisted pair line are also included in the circuit. Both the
DS7820A and the DS8820A are specified, worst case, over

their full operating temperature range (- 55°C to + 125°C
and O°C to 70°C respectively), over the entire input voltage
range, for ± 10% supply voltage variations.

Features
Operation from a single + 5V logic supply
Input voltage range of ± 15V
Strobe low forces output to "1" state
High input resistance
Fanout of ten with TTL integrated circuits
Outputs can be wire OR'ed
Series 54174 compatible

•
•
•
•
•
•
•

Connection Diagram
Dual-In-Line Package
- INPUT

"-"

14

~Vcc

-~t------.

2
TERMINATION -

.....-..,

13

..------41-0-. - INPUT
12

+ INPUT -----4t--e
4

STROBE

RESPONSE TIME -

5

'\

r--i~-

11

1\/+/

10

6

TERMINATION

+ INPUT
STROBE

9

OUTPUT

-

7
GROUNO-

RESPONSE TIME

8

OUTPUT

Note: Pin 7 connected to bottom of cavity package.

Top View
Order Number DS7820AJ, DS8820AJ or DS8820AN
See NS Package Number J 14A or N 14A

1-167

TL/F/5797-2

<
o
N

Absolute Maximum Ratings

U)

If Military!Aerospace specified devices are required,
contact the National Semiconductor Sales Office!
Distributors for availability and specifications.

CO
CO

C
.......

<
o
N
CO
.....
U)
C

Operating Conditions

(Note 1)

Supply Voltage

8.0V

Common-Mode Voltage

±20V

Differential Input Voltage

±20V

Strobe Voltage

Min

Max

Units

Supply Voltage (Vce)
DS7820A
DS8820A

4.5
4.75

5.5
5.25

V
V

Temperature (TA)
DS7820A
DS8820A

-55
0

+125
+70

°C
°C

8.0V

Output Sink Current
Storage Temperature Range

50mA
- 65°C to 150°C

Maximum Power Dissipation· at 25°C
Cavity Package
Molded Package

1308mW
1207 mW

Lead Temperature (Soldering, 4 sec.)
260°C
"Derate cavity package 8.7 mWrC above 25'C; derate molded package
9.7 mWrC above 25'C.

Electrical Characteristics (Notes 2,3, and 4)
Symbol
VTH

Parameter
Differential Threshold Voltage

Conditions
lOUT = - 400 ,..,A,
VOUT;;::: 2.5V
lOUT = + 16 mA,
VOUT::;; OAV

Typ

Max

Units

-3V::;; VCM ::;; +3V

Min

0.06

0.5

V

-15V ::;; VCM ::;; + 15V

0.06

1.0

V

-3V::;; VCM ::;; +3V

-0.08

-0.5

V

-15V::;; VCM::;; +15V

-0.08

-1.0

V

RI-

Inverting Input Resistance

-15V::;; VCM::;; +15V

3.6

5

RI+

Non-Inverting Input Resistance

-15V ::;; VCM ::;; + 15V

1.8

2.5

RT

Line Termination Resistance

TA

120

170

250

n

11-

Inverting Input Current

VCM = 15V

3.0

4.2

mA

11+

Non-Inverting Input Current

= 25°C

VCM

= OV

VCM

= -15V

VCM

= 15V

= OV
VCM = -15V
Power Supply Current
One Side Only

lOUT

0

-0.5

mA

-4.2

mA

5.0

7.0

mA

-1.0

-1.6

mA

-7.0

-9.8

mA

3.9

6.0

mA

9.2

14.0

mA

6.5

10.2

mA

2.5

4.0

5.5

V

0

0.22

004

I
I VCM = -15V

= Logical "0" VOIFF = -W VCM = 15V
VOIFF

VOH

Logical "1" Output Voltage

= -0.5V, VCM = OV

lOUT

= -400 ,..,A, VOIFF = W

VOL

Logical "0" Output Voltage

lOUT

= +16 mA, VOIFF

VSH

Logical "1" Strobe Input Voltage

lOUT

= + 16 mA, VOUT ::;; OAV, VOIFF = -3V

VSL

Logical "0" Strobe Input Voltage

lOUT

= -400 ,..,A, VOUT;;::: 2.5V, VOIFF = -3V

ISH

Logical "1" Strobe Input Current

VSTROBE = 5.5V, VDIFF = 3V

ISL

Logical "0" Strobe Input Current

VSTROBE

= -W

= OAV, VOIFF = -3V

kn

-3.0

VCM

Icc

kn

2.1

V
V

0.9

V

0.01

5.0

,..,A

-1.0

-104

mA

-2.8
-4.5
-6.7
mA
Va = OV, VCC = 5.5V, VSTROBE = OV
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: These specifications apply for 4.5V ~ Vee ~ 5.5V, -15V ~ VeM ~ 15Vand -55'C ~ TA ~ +125'C for the DS7820A or 4.75V ~ Vee ~ 5.25V, O'C ~
TA ~ + 70'C for the DS8820A unless otherwise specified. Typical values given are for Vee = 5.0V, TA = 25'C and VeM = OV unless stated differently.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.

Isc

Output Short Circuit Current

1-168

Switching Characteristics TA =
Symbol

c
en

.......

25°C, Vee = 5V, unless otherwise noted

Parameter

Conditions

Q)

Min

Typ

Max

Units

tpdO

Propagation Delay, Differential
Input to "0" Output

30

45

ns

tpdl

Propagation Delay, Differential
Input to "1" Output

27

40

ns

N
0

>
......
C
en
Q)
Q)

RL = 400 fl, CL = 15 pF, see Figure 1

tpdO

Propagation Delay, Strobe
input to "0" Output

16

25

ns

tpdl

Propagation Delay, Strobe
Input to "1" Output

18

30

ns

AC Test Circuit and Waveforms
_ - - - - - - -...~>JVcc = SV
PULSE
GEN.

"Includes Jig and Probe Capacitance

PULSE
GEN.

I, = If = 10 ns

PRR = 1 MHz
TL/F/5797-7

DIFF
INPUT

-2.SV

STROBE
INPUT

OV

OUTPUT
TL/F/5797 -6

A

= Differential Input to "0" Output

B = Differential Input to "I" Output
C

= Strobe Input to "0" Output

D = Strobe Input to "I" Output

FIGURE 1

1-169

N
0

>



.! 25'C

~

I .1. I vcy ov

'".....e<

TA

f;;;:::: -

e
e
:z:

VOUT ' 2.5V, 'OUT' -400/4A

I

VI

= O.~V,

VOUT

a:
:z:
..... -0.1

T

I

i

~

C

-0.2

5.0

I
I-- 1--'- -l.~'" lou 1
e
"ou1 ='6"'P.~
e
:z:
I-"" 1 =\l.~"~~;"r- "ou
a:
i= -0.2 ~
..:

~

1

4.5

=-4~~

0.2

5.5

6.0

C

'4

Transfer Function

e

I I
I I

::>

1 I

lfI

-55'C-

rll

>
.....

.....
::>
e

I I

ill

-... ;..F--"

-0.4

S

~

,....:~5.C- -

~
e

170

z

"',,,
... ,

0.2

./

0

25

200

a:

~

::>

VI

-20

+20

~

C

26

I--"""

......

J

L

./
~

..-'7
/

18

I-"""

30

-

>
..:

26

e

22

'"ea:
.....

./..V DIFFERENTIAL
22

./

-75 -50 -25

0

I-TO "I" OUTPUT

I

I

25

50

TA ('C)

I

+--+--+-1--+--1

e

>

.....

.....

::>

o

10

0.1 '---'----'---'-_.1..-...1---'----'---..1
-75 -50 -25 0 25 50 75 100 125

20

TA('C)

Noise Rejection

Strobe Delays
I

~

= 5V

'".....e<

~~

-10

34

I

75 100 125

Vee = 5V
I
I

I

1000

I
I
I

/

STIROB~ TO ~'1" ~UTP~T- ~ r--

\/

./
r--

~

/

l--' K

;z5TROBE TO "0" OUTPUT

10
-15 -50 -25

0

25
TA ('C)

I

I

50

15 100 125

I

-1·

t-

e

l:
on

/....--"

5V
Vee
25'C
TA
VOIFF = ± 2.5V PULSE

-.....:z:
::>

1.

18
14

I
I
I

20

Output Voltage Levels

COMMON·MOOE VOLTAGE (V)

Differential Input Delays
Vee = 5V

10

::>

p
.~

1

-10

Vee

'I.'
I

12rC ~

COMMON·MODE VOLTAGE (V)

30

/""-+INPUT

I

~

~'C

o
+10

I

'\

100

~

A

-6

Vee = 5.0V
OUTPUT LOW

~~

~

. / ......... I/V'

-10
-20

75 100 125

/~ ~

INPUT VOLTAGE (WITH RESPECT TO GROUND) (V)

I

~

~
C

...>

e

50

300

~

::>

..:

-4

-8

~

a:
a:

38
34 f-- TO "0" OUTPUT

-2

::>

z

i

."

>

::>
u

.....

I'-- ~ I-'

.,.,

1

-INPUT,:>

Internal Power Dissipation

C[

I
J
I
DIIFFE~ENi'AL I

z
a:
a:

/

/

I

..s.....

/

TA ('C)

..s.....

..:

::; -150 '---'---'---'-_.1..-...1---'----''---1
:::
-75 -50 -25 o 25 50 75 100 125

160

Power Supply Current

!

~ -1 00 ~+--+--+--

C[

/

-75 -50 -25

0.4

10 __~-r-T~~~~-r~

42

-50

Input Characteristics

/

OIFFERENTIAllNPUT VOLTAGE (V)

-10

a:
:z:
.....

Vee = 5V
TA = 25'C

190
180

S
~

-0.2

e
e
:z:

TA('C)

z

I I I
--~

50

~

Termination Resistance

~

'".....e<

'"

C

COMMON·MDDE VOLTAGE (V)

SUPPL Y VOLTAGE (V)

FANOUT'10
-\25.1C
Vee' 5.0V
VeM = OV

+20

+10

-10

100

~

-0.4
-20

:>

..s

r::: r-

'O~T • 161rnA

e<

~

Temperature Sensitivity

T! = ~5'C
Vee = 5V

0.4

::::::

100

=
=
-

on

~
~

=10
10

100

1000

10,000

CRESPONSE TIME CONTROL (pF)

TL/F/5797-6

1-170

c

en
......

Schematic Diagram

r-----------__

C)
I\)

RESPONSE TIME
CONTROL

o

l>
......

~--~t_------~--_t~----------~----~._------vcc

C

en
C)
C)
I\)

o

l>

NON INVERTING
INPUT
-

Rl~

. .- - - -. .

J20

(+1

. .- -. .- - - - OUTPUT
R7
170

R8
5k

TERMINATION
R14
7~0

.----------~I-------+--------_4t_---~-------------- GROUND

Rl
5k

INVERTING
INPUT
(-I

Note: Schematic shows one-half of unit.

STROBE

TL/F/5797-1

Typical Applications
Differential Line Driver and Receiver
Cl

=

.01 fLF

TWISTEO
PAIR LINE
ANO OUTPUT
OUTPUT

112 OS7830
NAND OUTPUT

C2'

Tl00Pf
~

INPUTS

'Optional to control response time.

STROBE

-=

TL/F/5797-3

Single Ended (EIA-RS232C) Receiver with Hysteresis
lN914

4V

VOUT

0.2V
OUTPUT

VIN

2.5V
TL/F/5797-5

(Output
CZ'

Tl00Pf
STROBE

-=
1-171

TL/F/5797-4

= "I" for Open Input)

o

N

~ ~National
~ ~ Semiconductor
......
o
N

~ DS78C20/DS88C20 Dual CMOS Compatible
~

Differential Line Receiver
General Description

Features

The OS78C20 and OS88C20 are high performance, dual
differential, CMOS compatible line receivers for both balanced and unbalanced digital data transmission. The inputs
are compatible with EIA and Federal Standards.

• Meets requirements of EIA Standards RS-232-C RS422 and RS-423, and Federal Standards 1020 and
1030
• Input voltage range of ± 15V (differential or commonmode)
• Separate strobe input for each receiver
• % Vee strobe threshold for CMOS compatibility
• 5k typical input impedance
• 50 mV input hysteresis
• 200 mV input threshold
• Operation voltage range = 4.5V to 15V
• OS7830/0S8830 or MM78C30/MM88C30 recommended driver

Input specifications meet or exceed those of the popular
OS7820/0S8820 line receiver, and the pinout is identical.
A response pin is provided for controlling sensitivity to input
noise spikes with an external capacitor. Each receiver includes a 1800 terminating resistor, which may be used optionally on twisted pair lines. The OS78C20 is specified over
a - 55°C to + 125°C operating temperature range, and the
DS88C20 over a O°C to + 70°C range.

Connection Diagram
Dual-In-Line Package

Vee
14

-INPUT

-INPUT
13

TERMI·
NATION

TERMI·
NATION

12

+INPUT

+INPUT

STROBE

11

10

STROBE

RESPONSE
TIME

RESPONSE
TIME

OUTPUT

OUTPUT

GNO
TL/F/5798-1

Top View
Order Number DS78C20J, DS88C20J or DS88C20N
See NS Package Number J14A or N14A

1-172

Absolute Maximum Ratings

Operating Conditions

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Min
4.5

Supply Voltage (Vce)

±25V

Differential Input Voltage

±25V

Common·Mode Voltage (VCM)

Strobe Voltage

-55
0

+125
+70

°C
°C

-15

+15

V

en
co
co
oN
o

1BV

Output Sink Current

50 rnA

Maximum Power Dissipation* at 25°C
Cavity Package
Molded Package

1364mW
12BOmW

Storage Temperature Range

- 65°C to + 150°C

Lead Temperature (Soldering, 4 seconds)

260°C

'Derate cavity package 9.1 mWI'C; derate molded package 10.2 mWI'C
above 25'C.

Electrical Characteristics
Symbol
VTH

(Notes 2 and 3)

Parameter
Differential Threshold Voltage

Conditions

Min

0.2

-15V::;; VCM ::;; 15V

0.06

0.3

V

lOUT = 1.6 rnA, VOUT ::;; 0.5V

-10V::;; VCM ::;; 10V

-O.OB

-0.2

V

-15V::;; VCM ::;; 15V

-O.OB

-0.3

RT

Line Termination Resistance

TA = 25°C

liND

Data Input Current (Unterminated) VCM = 10V

5
100

VCM = OV
VCM = -10V
VTHB

Max Units

lOUT = - 200 /-LA,
VOUT;;:: Vcc -1.2V

-15V::;; VCM ::;; 15V

Input Balance

Typ
0.06

-10V::;; VCM ::;; 10V

Input Resistance

RIN

lOUT = 200 /-LA, VOUT ;;::
VCC -1.2V, Rs = 500n,
(Note 5)

Logical "1" Output Voltage

lOUT = - 200 /-LA, VOIFF = 1V

VOL

Logical "0" Output Voltage

lOUT = 1.6 rnA, VOIFF = -1V

Icc

Power Supply Current

15V::;; VCM ::;; -15V,
VOIFF = -0.5V

V

V
kn

1BO

300

n

2

3.1

rnA

0

-0.5

rnA

-2

-3.1

rnA

0.1

0.4

V

-0.1

-0.4

V

-7V::;; VCM::;; 7V

lOUT = 1.6 rnA, VOUT ::;; 0.5V, -7V::;; VCM::;; 7V
Rs = 500n, (Note 5)
VOH

V

Vcc-1.2 VCC - 0.75
0.25

0.5

V

VCC = 5.5V

B

15

rnA

VCC = 15V

15

30

rnA

VSTROBE = 15V, VOIFF = 3V VCC = 15V

15

100

/-LA

-0.5

(Both Receivers)
IIN(1)

Logical "1" Strobe Input Current

IIN(O)

Logical "0" Strobe Input Current

VSTROBE = OV, VOIFF = -3V VCC = 15V

VIH

Logical "1" Strobe Input Voltage

lOUT = 1.6 rnA, VOL::;; 0.5V

VIL

los

Logical "0" Strobe Input Voltage

Output Short·Circuit Current

lOUT = - 200 /-LA,
VOH = VCC -1.2V

1-173

-100 /-LA

VCC = 5V

3.5

2.5

V

VCC = 10V

B.O

5.0

V

VCC = 15V

12.5

7.5

V

VCC = 5V

2.5

1.5

V

VCC = 10V

5.0

2.0

V

VCC = 15V

7.5

2.5

V

-20

-40

rnA

VOUT = OV, VCC = 15V, VSTROBE = OV, (Note 4)

o

C

Common·Mode Voltage

1BV

Units
V

'-

Temperature (TA)
DS7BC20
DSBBC20

Supply Voltage

Max
15

c
en
.......
co
oN

-5

0

C\I

0
co
co

CJ)

C
......

Switching Characteristics Vcc =
Symbol

5V, TA = 25°C

Parameter

Conditions

Typ

Min

Max

Units
ns

0

Differential Input to "0" Output

CL = 50 pF

60

100

0
co

Differential Input to "1" Output

CL = 50 pF

100

150

ns

CJ)

Strobe Input to "0" Output

CL = 50 pF

30

70

ns

Strobe Input to "1" Output

CL = 50 pF

100

150

ns

C\I

I'

C

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the - 55'C to + 125'C temperature range for the OS78C20 and across the O'C to
the OS88C20. All typical values are for T A = 25'C, Vee = 5V and VeM = OV.

+ 70'C range for

Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: Refer to EIA-RS-422 for exact conditions.

Typical Applications
RS-422/RS-423 Application
Cl
O.OII'F
(NOTE 1)
Vcc

Vcc

LINE DRIVER AND RECEIVER (NOTE 3)

OUTPUT

STROBE
TL/F/5798-2

Note 1: (Optional internal termination resistor.)
a) Capacitor in series with internal line termination resistor, terminates the line and saves termination power. Exact value depends on line length.
b) Pin 1 connected to pin 2; terminates the line.
c) Pin 2 open; no internal line termination.
d) Transmission line may be terminated elsewhere or not at all.
Note 2: Optional to control response time.
Note 3: Vee 4.5V to 15V for the OS78C20. For further information on line drivers and line receivers, refer to applicaton notes AN-22, AN-83 and AN-lOB.

RS-232-C Application with Hysteresis

Vcc

Rl

INPUT

Vee

R1 ±5%

5V
10V
15V

4,3k!l
15 k!l
24k!l

STROBE

TLlF/5798-3

For Signals which require fail-safe or have slow rise and
fall times, use Rl and 01 as shown above. Otherwise,
the positive input (pin 3 or 11) may be connected to
ground.

1-174

(OUTPUT2
"1" FOR
OPEN INPUT)

OV O.SV

2.5V
TL/F/5798-4

c
en
.......

AC Test Circuit

Q)

OIFF INPUT

o
N

Vee

Q

.......

C

_ _ _ _ _....rI

en
Q)
Q)
oN

OUTPUT

Q

Ir = If = , :; 10 ns
PRR = 1 MHz

TL/F/5798-5

'Includes probe and jig capacilance

Switching Time Waveforms
2.SV - - - - - - ' _ - - - " " \
OIFF
INPUT

-2.SV - - - - - '

III

OUTPUT

TLlF/5798-6

1-175

oC")
CO
CO

UJ

C

......
oC")

~National

~ Semiconductor

CO

......

UJ

C

057830/D58830 Dual Differential Line Driver
General Description

Features

The OS7830/0S8830 is a dual differential line driver that
also performs the dual four-input NAND or dual four-input
AND function.

• Single 5V power supply
• Diode protected outputs for termination of positive and
negative voltage transients
• Diode protected inputs to prevent line ringing

TIL (Transistor-Transistor-Logic) multiple emitter inputs allow this line driver to interface with standard TTL systems.
The differential outputs are balanced and are designed to
drive long lengths of coaxial cable, strip line, or twisted pair
transmission lines with characteristic impedances of 50n to
500n. The differential feature of the output eliminates troublesome ground-loop errors normally associated with single-wire transmissions.

• High speed
• Short circuit protection

Connection Diagram
Dual-In-Llne and Flat Package
AND
OUTPUT

Vee

14

13

12

11

NAND
OUTPUT

10

AND
OUTPUT

NAND
OUTPUT

GND
TL/F/5799-2

Top View
Order Number DS7830J, DS8830J or DS8830N
See NS Package Number J14A or N14A

Typical Application
Digital Data Transmission
CIt

0.01 ",F

TWISTED PAIR liNE

OUTPUT

tExact value depends on line length.
'Optional to control response time.
STROBE
TL/F/5799-3

1-176

c

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (Vee)
DS8730
DS8830
Temperature (TA)
DS7830
DS8830

7.0V

Vee
Input Voltage

5.5V
- 65°C to + 150°C

Storage Temperature

en
......

Operating Conditions

(Note 1)

Lead Temperature (Soldering, 4 sec.)

260°C

Output Short Circuit Duration (125°C)

1 second

Min

Max

Units

4.5
4.75

5.5
5.25

V
V

-55
0

+125
+70

°C
°C

CO
W

o
.......

c
en
CO
CO
W

o

Maximum Power Dissipation· at 25°C
Cavity Package
1308 mW
Molded Package
1207 mW
-Derate cavity package 8.7 mWI'C above 25'C; derate molded package
9.7 mWI'C above 25'C.

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Conditions

VIH

Logical "1" Input Voltage

VIL

Logical "0" Input Voltage

VOH

Logical "1" Output Voltage

VIN = 0.8V

VOL

Logical "0" Output Voltage

VIN = 2.0V

IIH

Logical "1" Input Current

VIN = 2AV

IlL

Logical "0" Input Current

Ise

Output Short Circuit Current

Vee = 5.0V, TA = 125°C, (Note 4)

lee

Supply Current

VIN = 5.0V, (Each Driver)

VI

Input Clamp

lOUT = - 0.8 rnA

204

lOUT = 40 rnA

1.8

V
V

3.3
0.2

lOUT = 40 rnA

0.22

V
0.4

V

0.5

V

120

/J- A

VIN = 5.5V

2

rnA

VIN = OAV

-4.8

rnA

-100

-120

rnA

11

18

rnA

-1.0

-1.5

V

-40

Vee = Min, liN = - 12 rnA

Parameter

25°C, Vee = 5V, unless otherwise noted
Conditions

Propagation Delay NAND Gate

RL = 400n, CL = 15 pF
(Figure 1)

t1

Differential Delay

Load, 100n and 5000 pF,
(Figure 2)

t2

Differential Delay

Load, 100n and 5000 pF,
(Figure 2)

tpdO

tpdo

Units
V

lOUT = 32 rnA

RL = 400n, CL = 15 pF
(Figure 1)

tpd1

Max

0.8

Propagation Delay AND Gate

tpd1

Typ

2.0

Switching Characteristics TA =
Symbol

Min

Min

Typ

Max

Units

8

12

ns

11

18

ns

8

12

ns

5

8

ns

12

16

ns

12

16

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the - 55'C to + 125'C temperature range for the 057830 and across the O'C to + 70'C range for
the 058830. Typical values for TA = 25'C and Vce = 5.0V.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.

1-177

•

oC")
CO
CO

U)

AC Test Circuit and Switching Time Waveforms

C

........

oC")

Vee

CO
,....
c

INPUT

U)

AND OUTPUT
NAND OUTPUT

TL/F/5799-4

f = 1 MHz
tr = tf ~ 10 ns (10% to 90%)
Duty cycle = 50%

TL/F/5799-9

FIGURE 1

3V

r--------------,

Vee I

1/2 OS7830/0S8830

I

I

I

I
I

I

V

~

:.5V

OV

v.-~ "Jt

5000 pF

...........--Va
TL/F/5799-B

TL/F/5799-10

FIGURE 2

Typical Performance Characteristics
4.0

Output High Voltage
(Logical" 1")
vs Ouput Current

.......
3.0

"

,

]

~ ~25'C
....... ~

>

g

It',,

IT' ~25'C
f'

2.0

,,

,-55'C

1.0

o

a

Differential Delay vs
Temperature

I
20

40

60

80

20

."

15

00:

~

........ ..... ."

10

Threshold Voltage
vs Temperature

.

."

'"00:

1.8

>

1.4

g
c
c

x

a:

x

is

I-

10D 12D 14D

·50 ·25 0

OUTPUT SOURCE CURRENT (mAl

25 50 75 100 125

1.6

1.2
1.0
.8

Differential Output Voltage
Power Dissipation (No Load)
vs Data Input Frequency

Differential Output Current
~
~

.....

c
;;;
x
le

a

-50 -25

25 50 75 100 125

TEMPERATURE (OC)

TEMPERATURE (OC)

(IVANO - VNANOI) vs

Output Low Voltage
(Logical "0") vs
Output Current

-

-

200
180
160
140
120

rr--

100 ~I10

r-0.12

OUTPUT CURRENT (rnA)

~ 2.0

-

-'"
571.02

-5~'cI

-I

"1
5710020.05710

DATA INPUT FREQUENCY (MHz)

f

-20

40

I

J

~~

2S'C

I"

J

b ~25'C
60

10 100 120 140

OUTPUT SINK CURRENT (rnA)

TL/F/5799-7

1-178

c
en

Schematic Diagram

~

P---------------~----~------~----_1~--Vcc

CO
W

.....
<:)

c
en
CO
CO
W
<:)

2K

""--....------4._- NAND
OUTPUT

A-"'-.

...----..--...-----+---~.-- Vee

------~

II
AND

""--...------4~- OUTPUT

TL/F/5799-1

·2 Per Package

1·179

N

C")

co
co

m

c.......
N

C")

co
.....

m

c

.......
.,...
C")

co
co
m

c.......

.,...
co
.....
m
c
C")

~National

~ Semiconductor

DS7831/0S8831/0S7832/0S8832
Dual TRI-STATE® Line Oriver
General Description

Features

Through simple logic control, the OS7831 IOS8831,
OS7832/0S8832 can be used as either a quad single-ended line driver or a dual differential line driver. They are specifically designed for party line (bus-organized) systems.
The OS7832/0S8832 does not have the Vee clamp diodes
found on the OS7831/0S8831.
The OS7831 and OS7832 are specified for operation over
the - 55°C to + 125°C military temperature range. The
OS8831 and OS8832 are specified for operation over the
O°C to + 70°C temperature range.

•
•
•
•
•

Series 54/74 compatible
17 ns propagation delay
Very low output impedance-high drive capability
40 mA sink and source currents
Gating control to allow either single-ended or differential operation
1
• High impedance output state which allows many outputs to be connected to a common bus line

Connection and Logic Diagram
Dual-ln-L1ne Package
Vee

"A" OUTPUT
OISASlE

OUTPUT
A2

INPUT
A2

OUTPUT
AI

INPUT
AI

DIFFERENTIAll
SINGLE-ENDED
MODE CONTROL

Order Number DS7831J, DS8831J,
DS7832J, DS8832J, DS8831 N or DS8832N
See NS Package Number J16A or N16A

"S" OUTPUT
DISABLE

OUTPUT
B2

INPUT
S2

OUTPUT INPUT DIFFERENTIAll GND
BI
BI SINGLE-ENDED
MODE CONTROL

TL/F/5800-1

Top View

Truth Table

(Shown for A Channels Only)

"A" Output Disable

x=

Differentiall
Single-Ended
Mode Control

InputA1

OutputA1

InputA2

OutputA2

Same as
InputA1

a

a

a

a

Logical "1" or
Logical "0"

Logical "1" or
Logical "0"

Same as
InputA2

a

a

X
1

1
X

Logical "1" or Opposite of Logical "1" or
Logical "0"
Input A1
Logical "0"

Same as
InputA2

1
X

X
1

X

X

High
Impedance
State

High
Impedance
State

X

Don't Care

1-180

X

Absolute Maximum Ratings

Operating Conditions

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
5upply Voltage
7V
Input Voltage

5.5V

Output Voltage

5.5V

5torag~ Temperature Range

Min

Max

Units

5upplyVoitage (Vee)
057831/057832
058831/058832

4.5
4.75

5.5
5.25

V
V

Temperature (TA)
057831/0S7832
058831/058832

-55
0

+125
+70

·C
°C

- 65°C to + 150°C

Lead Temperature (50Idering, 4 sec.)

260°C

Maximum Power Oissipation· at 25°C
Cavity Package
1433 mW
Molded Package
1362mW
"Derate cavity package 9.6 mWI'C above 25'C; derate molded package
10.9 mW/'C above 25'C.

Electrical Characteristics
Symbol

(Notes 2 and 3)

Parameter

Conditions

VIH

Logical "1" Input Voltage

Vee = Min

VIL

Logical "0" Input Voltage

Vee = Min

VOH

Logical "1" Output Voltage

057831/057832

058831/058832

VOL

Logical "0" Output Voltage

Min

Typ

Vee = Min

1.8

2.3

V

10 = -2mA

204

2.7

V
V

10 = -40 mA

1.8

2.5

10 = -5.2mA

2.4

2.9
0.29

10 = 40 mA
Vee = Min

0.29

10 = 40mA
10 = 32mA

IIH

Logical "1" Input Current

IlL

Logical "0" Input Current

100

Output Oisable Current

Vee = Max, Vo = 2.4V or OAV

-40

Ise

Output 5hort Circuit Current

Vee = Max, (Note 4)

-40

lee

5upply Current

Vee = Max in TRI-5TATE

VeLi

Input Oiode Clamp Voltage

Vee = 5.0V, TA = 25°C, liN = -12 mA

VeLD

Output Oiode Clamp Voltage Vce = 5.0V,
TA = 25°C

057831/057832, VIN = 5.5V
058831/058832, VIN = 2AV

Vee = Max, VIN = OAV

1-181

057831/058831

V
0.50

V

0040

V

0.50

V

0040

V

1.

mA

40

IJ-A

-1.0

-1.6

mA

40

IJ-A

-100

-120

mA

65

lOUT = -12 mA 057831/058831
057832/058832
lOUT = 12 mA

V

10 = -40mA

10 = 32mA

Vee = Max

Units
V

0.8

057831/057832

058831/058832

Max

2.0

90

mA

-1.5

V

-1.5

V

Vee + 1.5

V

N

C")

co
co

en
c
.......
N

C")

co
.....
en
c.......

Switching Characteristics T A = 25°C, Vee =
Symbol
tpdO

T""

C")

co
co

en

c.......
T""

C")

co
.....
en
c

tpd1

Parameter

5V, unless otherwise noted

Typ

Max

Units

Propagation Delay to a Logical "a"
from Inputs A 1, A2, B1, B2
Differential Single-ended Mode
Control to Outputs

13

25

ns

Propagation Delay to a Logical "1"
from Inputs A 1, A2, B1, B2
Differential Single-ended Mode
Control to Outputs

13

25

ns

6

12

ns

Delay from Disable Inputs to High
Impedance State (from Logical "0"
Level)

14

22

ns

Propagation Delay from Disable Inputs
to Logical "1" Level (from High
Impedance State)

14

22

ns

Propagation Delay from Disable Inputs
to Logical "a" Level (from High
Impedance State)

18

27

ns

Delay from Disable Inputs to High
Impedance State (from Logical "1"
Level)

Conditions

(See Figures 4 and 5)

Min

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified min/max limits apply across the -55'C to + 125'C temperature range for the 087831 and 087832 and across the Q'C to
+ 7Q'C range for the 088831 and 088832. All typical values are for TA = 25'C and Vee = 5V.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltage referenced to ground unless otherwise noted. All values shown as
max or min on absolute value basis.
Note 4: Applies for TA

= 125'C only. Only one output should be shorted at a time.

Mode of Operation
in the "high impedance" state. This is accomplished by ensuring that a logical "1" is applied to at least one of the
Output Disable pins of each device which is to be in the
"high impedance" state. A NOR gate was purposely chosen
for this function since it is possible with only two DM5442/
DM7442, BCD-to-decimal decoders, to decode as many as
100 DS7831/DS8831's, DS7832/DS8832's (Figure 2).

To operate as a quad single-ended line driver apply logical
"O"s to the output disable pins (to keep the outputs in the
normal low impedance mode) and apply logical "O"s to both
Differential/Single-ended Mode Control inputs. All four
channels will then operate independently and no signal inversion will occur between inputs and outputs.
To operate as a dual differential line driver apply logical
"O"s to the Output Disable pins and apply at least one logical "1" to the Differential/Single-ended Mode Control inputs.

The unique device whose Disable inputs receive two logical
"a" levels assumes the normal low impedance output state,
providing good capacitive drive capability and waveform integrity especially during the transition from the logical "a" to
logical "1" state. The other outputs-in the high impedance
state-take only a small amount of leakage current from the
low impedance outputs. Since the logical "1" output current
from the selected device is 100 times that of a conventional
Series 54174 device (40 mA vs. 400 IJ-A), the output is easily
able to supply that leakage current for several hundred other DS7831 /DS8831 's, DS7832/DS8832's and still have
available drive for the bus line (Figure 3).

The inputs to the A channels should be connected together
and the inputs to the B channels should be connected together.
In this mode the signals applied to the resulting inputs will
pass non-inverted on the A2 and B2 outputs and inverted on
the A1 and B1 outputs.
When operating in a bus-organized system with outputs tied
directly to outputs of other DS7831 /DS8831 's, DS7832/
DS8832's (Figure 1), all devices except one must be placed

1-182

c

en

-.....
Q)

BUS LINES

CN

~

...A.

.......
C

en
Q)

SELECTED AS
DRIVINGDEVICE

Q)

CN
...A.

.......
C

en
-.....

Q)

CN
N

.......
C

en
co

Q)

CN
N
GATED INTO
THIRD STATE - - -

TLIF/5800-2

FIGURE 1

TL/F/5800-3

FIGURE 2

FOR DRIVING
OTHER
TTl INPUTS

SELECTED AS
DRIVING DEVICE

GATED INTO
HI IMPEDANCE
STATE

GATED INTO
HI IMPEDANCE
STATE

TLIF/5800-4

FIGURE 3

1-183

N

C")

co
co

Typical Performance Characteristics

N

Propagation Delay from Input
to Output (Channel 1)

en
o
.......
C")

co
......

en
o.......
,....

C")

co
co

en
o.......
,....
C")

co
......

30

g

20

~

15

~

i

en
o

30

1 Vee = 5.0V
OIFFERENTIAL/SINGLHNO'EO M'OOE
CONTROL INPUTS AT LOGICAL "0"
I
I

25

->

J J.

.1 J.

--

II

tpdO

I. d , - e--

10

1

-

I

o

-so

-15

-25 0

25

g

>

20

z

15

;:
~

10

F: -..

>

g

i
-15 -50 -25

0

50

Delay from Disable to Low
Impedance State
lO

fo---

.

I-- I--I0H

10

/"

"....
~

!
~

I

:-15
.~

10
I'H

,

>

40

z

lO

...- ...- g

1".0.- 10-"

C>

~

. - IH'

o

o

-15 -50 -25

0

25

50

-15 -50 -25

15 100 125

TEMPERATURE ('C)

00'

1
E

..

~

30

r-fff-

r--

10

.....

f-

.....

o

-

125"C-

>

-r--

.....

L...

.01

1000

40

100

10

,,
\

!(MHz)

lOUT

Ve~' ~V

I

i~

:::>
0

I

OS18l2

lO

..

V

/~ .....

0

>

/~
~ ;.4- -55'C

125'C-/

O,l

:::>

0.2

/0

~

0.1

1\
160

20

40
lOUT

l

Vee

,

60

80

100

(mAl

5.~V

I I
l.d2

20

~

.:~-55'C

-20

~
7lJE~
V ~

I

Propagation Delay in
Differential Mode

---.!-

C

I

"tOl- l--

I

E

25

25'C
_55°C_

.!

I

0.4

125°C_

+20

vr

(mA)

,

I OS18l1

r I

120

lOUT vs VOUT High
Impedance Output State
+40

0.5

I

,

80

10,000

Logical "0" Output Voltage
vs Sink Current

...!--55'C

, l
\
\

-

ff-

100
CL (pFI

~ ~25'C
"""01[-.....

I--

!iiI

~1I1

10

Vee = 5.0V

:::>

r--

1'1::....~

-

o

100 125

I

t" ~

r--

20

15

~

j'..

SO

C 40

50

20
10

Logical "1" Output Voltage
vs Source Current

00"_

Vee' 5.0V
TA '25°C
ALL CHANNELS SWITCHING

60

2S

J
(

TEMPERATURE ('C)

Total Supply Current vs
Frequency
10

0

Vee" 5.0V
T." 25'C

50

!

.--

- -

r- I--I HO

15 100 125

60

l

-

so

25

Propagation Delay vs Load
Capacitance

Ve e = 5~OV

20

0

TEMPERATURE ('C)

Delay from Disable to High
Impedance State

",

-15 -50 -25

15 100 125

TEMPERATURE ('C)

'""-

.!
II

25

TEMPERATURE ('C)

Ve1e " 5~OV

15

=

l.dO- i-=

I

15 100 125

20

Ve~ = 5~OV

I.!!,.. ~

C>

25

!

lO

I

Vee =5.0V
OIFFERENTIAL/SINGLHNOEO MODE
CONTROL INPUTS AT LOGICAL "I"
I
~
~.-

25

.s

JI. J

.1

o

50

lO

Propagation Delay from Input
to Output (Channel 2)

Propagation Delay from Input
to Output (Channel 1)

15

:ao,.

10

1~25°CI

:::::-

+- ...-

-- T- -

~

I-

- r-

I.d'

11:l+-T-125'C

-40

IS

I

-so

-2

so

100

TEMPERATURE ('C)

VOUT (VI

TL/F/5800-5

1-184

Typical Performance Characteristics

c
en
.....,

(Continued)

(X)

....

W
INPUTAI

......

OUTPUT AI

INPUT

c
en

VI

(X)
(X)

OS11311
OS8831

....
......
W

SOOOpF

c
en
.....,

V2
OUTPUT A2

(X)

W

N
......

C

....:Jl

uvi

INPUT

-.l

Vl-V2

en

\.SV

(X)
(X)

1•

t--

W
N

-.l to.. t--

r----:x

I •••

~..

•• ' - - -

TL/F/S600-6

Switching Time Waveforms
~-----------JV

INPUT

INPUT

I
I

I

DV---..I1
DV----

--1

IOH
:-

I
I

I

I
I
I

INVERTED
OUTPUT

OUTPUT
_ _ _ _ _..I

ACTUAL

>

1.SV

f f

~~~~CAAGLE"D"

I

_-----

I~
-DIv

1
1

,----------lV

I

~I••• ~

NONINVERTED
OUTPUT

tlH

I

I
I
I
I

I
I
I

1

I

III

INPUT

I
1

DV
ACTUAL
LOGICAL "I"
VOLTAGE

Input characteristic:
Amplitude
Frequency
tr

= 3.0V
= 1.0 MHz, 50% duty cycle

I.H

OUTPUT

t4-

:_1

-l
~

= tf s;: ns (10% to 90%)

>I.SV

TL/F/S600-7

tHO

INPUT

\.
I
I
I

tHl

INPUT

\

..

OV

1

-lI

OUTPUT

ov

IH•

I
I

OUTPUT

TL/F/5600-6

FIGURE 4
1-185

N

C")

co
co
(J)
C

AC Load Circuit

Symbol

sv

C")

co
,....

I

(J)

C

.......
N

C
.......

....

co
co

C

...........

t1H
tHO
tH1
"Jig capacitance

I ....

I~

~,

-I0511321

co
,....

C

tOH

5,

01

-

C")

(J)

tpdO

:400

C")

(J)

tpd1

Ik

OSlllZ

-

T"

~,

-I~,

-II

1

52

TLIF/5BOO-9

FIGURE 5

1-186

Switch S1

closed
closed
closed
closed
closed
open

Switch S2

closed
closed
closed
closed
open
closed

CL

50pF
50 pF
*5 pF
*5 pF
50 pF
50pF

c

en
......

~National

Q)

o
......

~ Semiconductor

I\)

o
......

c
en
Q)

DS78C120/DS88C120 Dual CMOS Compatible
Differential Line Receiver

Q)

o
......
I\)

o

General Description

Features

The OS78C120 and OS88C120 are high performance, dual
differential, CMOS compatible line receivers for both balanced and unbalanced digital data transmission. The inputs
are compatible with EIA, Federal and MIL standards.

• Full compatibility with EIA Standards RS232-C, RS422
and RS423, Federal Standards 1020, 1030 and MIL188-114
• Input voltage range of ± 15V (differential or commonmode)
• Separate strobe input for each receiver
• 1/2 Vee strobe threshold for CMOS compatibility
• 5k typical input impedance
• 50 mV input hysteresis
• 200 mV input threshold
• Operation voltage range = 4.5V to 15V
• Separate fail-safe mode

Input specifications meet or exceed those of the popular
OS7820/0S8820 line receiver.
The line receiver will discriminate a ± 200 mV input signal
over a common-mode range of ± 10V and a ± 300 mV signal over a range of ± 15V.
Circuit features include hysteresis and response control for
applications where controlled rise and fall times and/or high
frequency noise rejection are desirable. Threshold offset
control is provided for fail-safe detection, should the input
be open or short. Each receiver includes a 180n terminating
resistor and the output gate contains a logic strobe for time
discrimination. The OS78C120 is specified over a -55°C to
+ 125°C temperature range and the OS88C120 from O°C to
+ 70°C.

Connection Diagram
Dual-In-Line Package
Vee

16

FAIL-SAFE
OFFSET -INPUT

15

14

OFFSET -INPUT TERMI·
FAIL·SAFE
NATION

TERMI·
NATION +INPUT

13

12

STROBE

11

RESPONSE
TIME OUTPUT

10

+INPUT STROBE RESPONSE OUTPUT
TIME

GND
TLIF/5801-1

Top View
Order Number DS78C120J, DS88C120J or DS88C120N
See NS Package Number J16A or N16A

1-187

o
N
......
oco
co

Absolute Maximum Ratings

(Note 1)

If MilitaryI Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications .

Storage Temperature Range

N
......

Supply Voltage

Operating Conditions

I'-

Strobe Voltage

C

Output Sink Current

(J)

C
.......
o

o
co
(J)

18V

Input Voltage

- 65°C to + 150°C

Min

Max

Units

Supply Voltage (Vce)

4.5

15

V

Temperature (TA)
DS78C120
DS88C120

-55
0

+125
+70

°C
°C

Common-Mode Voltage (VCM)

-15

+15

V

±25V
18V
50mA

Maximum Power Dissipation* at 25°C
Cavity Package
Molded Package

260°C

Lead Temperature (Soldering, 4 seconds)

1433 mW
1362 mW

-Derate cavity package 9.6 mWfOC above 25°C; derate molded package
10.9 mW rc above 25°C.

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Min

Conditions

Typ

Max Units

Differential Threshold
Voltage

lOUT = - 200 /-LA,
VOUT ;;::: Vcc - 1.2V

-7V ~ VCM ~ 7V

0.06

0.2

V

-15V ~ VCM ~ 15V

0.06

0.3

V

Differential Threshold
Voltage

lOUT = 1.6 rnA,VOUT ~ 0.5V

-7V ~ VCM ~ 7V

-0.08

-0.2

V

-15V ~ VCM ~ 15V

-0.08

-0.3

V

Differential Threshold
Voltage Fail-Safe

lOUT = - 200 /-LA,
VOUT ;;::: VCC - 1.2V

-7V~VCM~7V

0.47

0.7

V

VTL

Offset = 5V

lOUT = 1.6 rnA, VOUT ~ 0.5V

-7V ~ VCM ~ 7V

RIN

Input Resi~tance

-15V ~VCM ~ 15V, OV ~ VCC ~ 15V

VTH

VTL

VTH
1-

RT

Line Termination Resistance TA = 25°C

RO

Offset Control Resistance

TA = 25°C

IINO

Data Input Current
(Unterminated)

OV ~ VCC ~ 15V

0.2

0.42

V

4

5

kn

100

180

Input Balance
(Note 5)

2

3.1

rnA

VCM = OV

0

-0.5

rnA

-2

-3.1

rnA

0.1

0.4

V

-0.1

-0.4

V

0.5

V

8

15

rnA

15

30

rnA

15

100

/-LA

-0.5

-100

/-LA

lOUT = 200 /-LA, VOUT ;;:::
VCC - 1.2V, RS = 500n

-7V ~ VCM ~ 7V

lOUT = 1.6 rnA, VOUT ~ 0.5V
Rs = 500n

-7V~VCM~7V

VOH

Logical "1" Output Voltage

lOUT = - 200 /-LA, VOIFF = 1V

VOL

Logical "0" Output Voltage

lOUT = 1.6 rnA, VOIFF = -1V

Icc

Power Supply Current

15V ~ VCM ~ -15V,
VOIFF = -0.5V (Both Receivers)

IIN(1)

Logical "1" Strobe Input
Current

VSTROBE = 15V, VOIFF = 3V

IIN(O)

Logical "0" Strobe Input
Current

VSTROBE = OV, VOIFF = -3V

VIH

Logical "1" Strobe Input
Voltage

VOL ~ 0.5V,IOUT = 1.6 rnA

1-188

n
kn

VCM = 10V

VCM = -10V
VTHB

300

56

V

VCC - 1.2 VCC - 0.75
0.25
VCC = 5.5V
VCC = 15V

VCC = 5V

3.5

2.5

V

VCC = 10V

8.0

5.0

V

VCC = 15V

12.5

7.5

V

Electrical Characteristics
Symbol
VIL

los

(Notes 2 and 3) (Continued)

Parameter

Min

Conditions

Logical "0" Strobe Input

VOH Vee -

Voltage

lOUT

Output Short-Circuit Current

= -

=

VOUT

1.2V,

200

JLA

OV, Vee

=

15V, VSTROBE

=

Typ

Max

Units

Vee

=

5V

2.5

1.5

V

Vee

=

10V

5.0

2.0

V

Vee

=

15V
-5

OV, (Note 4)

7.5

2.5

V

-20

-40

rnA

Note I: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified min/max limits apply across the - 55'C to + 125'C temperature range for the DS78C120 and across the O'C to
for the DS88C120. All typical values for TA = 25'C. Vcc = 5V and VCM = OV.

+ 70'C range

Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: Refer to EIA·RS422 for exact conditions.

Switching Characteristics Vee =

5V,

TA =

25°C
Typ

Max

Units

Differential Input to "0" Output

CL

=

50 pF

60

100

ns

tpdl(D)

Differential Input to "1" Output

CL

=

50 pF

100

150

ns

tpdO(S)

Strobe Input to "0" Output

CL

=

50 pF

30

70

ns

tpdl(S)

Strobe Input to "1" Output

CL

=

50 pF

100

150

ns

Symbol

Parameter

tpdO(D)

Conditions

Min

AC Test Circuit and Switching Time Waveforms
Differential and Strobe Input Signal

-~

DlFF.,N'UT 0- OPEN

0--

STROBE
INPUT

OPEN

2.SV
OIFF
INPUT
-2.SV

°7

r

f f~~

0

~

'Includes probe and test fixture capacitance

-

~_

~

!---SOOns-

~ OUTPUT

°t""·

TL/F/5801-3

J

\

Vee
STROBE
INPUT

J

OV

--l

-500ns-

'\
r:-

7~

OUTPUT

I-- tpdO(O)-

7

lOr.

10%-'kt, = tf';; 10 ns

f-50%

f- t pdl(D)-

I-- tpdO(S)

~tpd1(S)-

TL/F/5801-4

PRR = 1 MHz
Note: Optimum switching response is obtained by minimizing stray capacitance on Response Control pin (no external connection).

1-189

c
en
.....
0)
o

...&.

N

o
.......
C

en
o

0)
0)
...&.

N

o

DS78C120/DS88C120

en
()

::::r
(1)

RESPONSE
CONTROL

3
D)

,..

Vee

c:;'

c

Di'

ce
""l

STROBE

D)

3
~
()
~.

C

;:;:
C/)

:::r

o

5k

:E

2-

CD

25

o

OUTPUT

-=

-=
FAIL·SAFE
OFFSET
INVERTING
INPUT

-=

56k

5k

3k

5k

-=

NON·

-=

~INVERTING

-=

-

GND

-

':'"

-=

INPUT

-=

TERMINATION
RESISTOR
TL/F/5801-2

c

en
......

Application Hints

CO

o

Balanced Data Transmission

-4

N

o
......
C

en

CO
CO

o

-4

N

o
OUTPUT

TL/F/5801-5

Unbalanced Data Transmission
1/4 DS1488
OR 1/4 DS3691

OUTPUT

TLIF/5801-6

Logic Level Translator

J
INPUT VOLTAGE

VOH
w

<:I

<
~

o

>

!;
VOL

OUTPUT

~

o

TL/F/5801-8
TLIF/5801-7

The DS78C120/DS88C120 may be used as a level transistor to interface between ± 12V MOS, ECl, TTL and CMOS. To configure, bias either input to a voltage
equal to 'Iz the voltage of the input signal, and the other input to the driving gate.

1·191

o
N

'I"'"

Application Hints (Continued)

co

LINE DRIVERS

C

Line drivers which will interface with the DS78C120/
DS88C120 are listed below.

N

Balanced Drivers

o
co
(f)

"o
'I"'"

oco

.......

(f)

C

OS26LS31
OS7830, DS8830
OS7831, DS8831
OS7832, DS8832
OS1691A, DS3691
OS1692, DS3692
OS3587, DS3487

100

,

POSITIVE INPUT ,.

Quad RS-422 Line Oriver
Dual TTL
Dual TRI-STATE® TTL
Dual TRI-STATE TTL
Quad RS-423/0ual RS-422 TTL
Quad RS-423/0ual TRI-STATE
RS-422 TTL
Quad TRI-STATE RS-422

/ ~EGATIVE INPUT
1/

Unbalanced Drivers
OS1488
OS14C88
OS75150

~

0.1

Quad RS-232
Quad RS-232
Dual RS-232

V
10

100

1k

10k

RESPONSE CONTROL CAPACITOR (pFI
TL/F/5801-9

RESPONSE CONTROL AND HYSTERESIS
In unbalanced (RS-232/RS-423) applications it is recommended that the rise time and fall time of the line driver be
controlled to reduce cross-talk. Elimination of switching
noise is accomplished in the OS78C120/0S88C120 by the
50 mV of hysteresis incorporated in the output gate. This
eliminates the oscillations which may appear in a line receiver due to the input signal slowly varying about the threshold
level for extended periods of time.

FIGURE 1. Noise Pulse Width vs
Response Control Capacitor

OUTPUT

High frequency noise which is superimposed on the input
signal which may exceed 50 mV can be reduced in amplitude by filtering the device input. On the DS78C120/
OS88C120, a high impedance response control pin in the
input amplifier is available to filter the input signal without
affecting the termination impedance of the transmission
line. Noise pulse width rejection vs the value of the response control capacitor is shown in Figures 1 and 2. This
combination of filters followed by hysteresis will optimize
performance in a worse case noise environment.

-

TL/F/5801-10

O.5V

TRANSMISSION LINE TERMINATION
On a transmission line which is electrically long, it is advisable to terminate the line in its characteristic impedance to
prevent signal reflection and its associated noise/crosstalk. A 1800. termination resistor is provided in the
DS78C120/DS88C120 line receiver. To use the termination
resistor, connect pins 2 and 3 together and pins 13 and 14
together. The 1800. resistor provides a good compromise
between line reflections, power dissipation in the driver, and
IR drop in the transmission line. If power dissipation and IR
drop are still a concern, a capacitor may be connected in
series with the resistor to minimize power loss.

NEGATIVE INPUT
NOISE PULSE

0

I I
\-

POSITIVE INPUT
NOISE PULSE

-\

I I

-2V
NOISE PU LSE WIDTH
2V

0
-D.5V
TL/F/5801-11

FIGURE 2

The value of the capacitor is recommended to be the line
length (time) divided by 3 times the resistor value. Example:
if the transmission line is 1,000 feet long, (approximately
1000 ns) the capacitor value should be 1852 pF. For additional application details, refer to application notes AN-22
and AN-108.

1-192

c

Application Hints (Continued)
performance of the receiver over its common-mode operating range, and will not change the input impedance balance
of the receiver.

FAIL-SAFE OPERATION
Communication systems require elements of a system to
detect the presence of signals in the transmission lines, and
it is desirable to have the system shut-down in a fail-safe
mode if the transmission line is open or shorted. To facilitate
the detection of input opens or shorts, the DS78C1201
DS88C120 incorporates an input threshold voltage offset.
This feature will force the line receiver to a specific logic
state if presence of either fault is a condition.

It is recommended that the receiver be terminated (500.0. or
less) to insure it will detect an open circuit in the presence
of noise.
The offset control can be used to insure fail-safe operation
for unbalanced interface (RS-423) or for balanced interface
(RS-422) operation.

Given that the receiver input threshold is ± 200 mV, an input
signal greater than ± 200 mV insures the receiver will be in
a specific logic state. When the offset control input (pins 1
and 15) is connected to Vee = 5V, the input thresholds are
offset from 200 mV to 700 mV, referred to the non-inverting
input, or - 200 mV to - 700 mV, referred to the inverting
input. Therefore, if the input is open or shorted, the input will
be greater than the input threshold and the receiver will
remain in a specified logic state.

For unbalanced operation, the receiver would be in an indeterminate logic state if the offset control input was open.
Connecting the offset to 5V offsets the receiver threshold
0.45V. The output is forced to a logic zero state if the input
is open or shorted.
For balanced operation with inputs shorted or open, receiver C will be in an indeterminate logic state. Receivers A and
B will be in a logic zero state allowing the NOR gate to
detect the short or open condition. The strobe will disable
receivers A and B and may therefore be used to sample the
fail-safe detector. Another method of fail-safe detection
consists of filtering the output of the NOR gate 0 so it would
not indicate a fault condition when receiver inputs pass
through the threshold region, generating an output transient.

The input circuit of the receiver consists of a 5k resistor
terminated to ground through 120.0. on both inputs. This network acts as an attenuator, and permits operation with common-mode input voltages greater than ± 15V. The offset
control input is actually another input to the attenuator, but
its resistor value is 56k. The offset control input is connected to the inverting input side of the attenuator, and the input
voltage to the amplifier is the sum of the inverting input plus
0.09 times the voltage on the offset control input. When the
offset control input is connected to 5V the input amplifier will
see VIN(INVERTING) + 0.45V or VIN(INVERTING) + 0.9V
when the control input is connected to 10V. The offset control input will not significantly affect the differential

In a communications system, only the control signals are
required to detect input fault condition. Advantages of a balanced data transmission system over an unbalanced transmission system are:
1. High noise immunity
2. High data ratio
3. Long line lengths

Unbalanced RS-423 and RS-232 Fall-Safe
LINE RECEIVER
1/2 DS7BC120

SV

W
t:I

-

~

CI

(OFFSET CONTROL
INPUT OPEN)

(OFFSET CONTROL
INPUT = SV)

...>

~

I;;I

CI

O.4SV
INPUT VOLTAGE

INPUT VOLTAGE
TL/F/5801-12

1-193

en
......
co
o
.....

N
o
........

C

en
co
co

o
.....
N

o

o

N

[)

Application Hints (Continued)

CO
CO

Balanced RS-422 Fail-Safe

m

c.......
o

BALANCED
LINE DRIVER

N

'9"'"

oCO
.....
m
c

D

0-0

5V~----------~--~

TLlF/5801-13

1§

w

w

t:I

t:I

~
c

~
c

<

<

>

>

~

~

~

~

~
::;)

~
::;)

c

'"
';t

c
c

-

I.....-

INPUT VOLTAGE

INPUT VOLTAGE

TL/F/5801-14

Truth Table

INPUT VOLTAGE
TL/F/5801-15

TL/F/5801-16

(For Balanced Fail-Safe)

Input

Strobe

A-OUT

B-OUT

C-OUT

D-OUT

0

1
1
1

0

1

0

1

1

0
0

0

0
0

0
0
0

1
1
1

1
1
1

X
0
0
0

0
0
0

1

X
0
1

X

1-194

1

c
en

.......

~National

C)

r-

~ Semiconductor

en
.....
N

o

.......
C

DS78LS120/DS88LS120 Dual Differential
Line Receiver (Noise Filtering and Fail-Safe)

en
C)
C)

~
.....
N

o

General Description
The OS78LS120 and OS88LS120 are high performance,
dual differential, TTL compatible line receivers for both balanced and unbalanced digital data transmission. The inputs
are compatible with EIA, Federal and MIL standards.

Input specifications meet or exceed those of the popular
OS7820/0S8820 line receiver.

The line receiver will discriminate a ± 200 mV input signal
over a common-mode range of ± 10V and a ±300 mV signal over a range of ± 15V.

• Meets EIA standards RS232-C, RS422 and RS423,
Federal Standards 1020,1030 and MIL-188-114
• Input voltage range of ± 15V (differential or commonmode)
• Separate strobe input for each receiver
• 5k typical input impedance
• Optional 180n termination resistor
• 50 mV input hysteresis
• 200 mV input threshold
• Separate fail-safe mode

Circuit features include hysteresis and response control for
applications where controlled rise and fall times and/or high
frequency noise rejection are desirable. Threshold offset
control is provided for fail-safe detection, should the input
be open or short. Each receiver includes an optional 180n
terminating resistor and the output gate contains a logic
strobe for time discrimination. The OS78LS120 is specified
over a - 55°C to + 125°C temperature range and the
OS88LS120 from O°C to + 70°C.

Features

Connection Diagram
Dual·ln·Line Package
Vee

FAll·SAFE
OFFSET -INPUT

15

14

FAll·SAFE -INPUT
OFFSET

TERMI·
NATION

16

TERMI·
NATION +INPUT

13

12

STROBE

11

RESPONSE
TIME OUTPUT

10

+INPUT STROBE RESPONSE OUTPUT
TIME

GND

Top View
Order Number DS78LS120J, DS88LS120J or DS88LS120N
See NS Package Number J16A or N16A

1-195

TL/F17499-1

o

C\I

§

Absolute Maximum Ratings

Operating Conditions

(Note 1)

CO
CO

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

o

Supply Voltage

en
o
......

....

C\I

~

CO

"en
o

7V

Input Voltage

±25V

Strobe Voltage

Min
4.5

Max
5.5

Units
V

Temperature (TA)
DS7SLS120
DSSSLS120

-55

a

+125
+70

°C
°C

Common-Mode Voltage (VCM)

-15

+15

V

Supply Voltage (Vce)

7V

Output Sink Current
Storage Temperature Range
Maximum Power Dissipation* at 25°C
Cavity Package
Molded Package
Lead Temperature (Soldering, 4 sec)

50mA
- 65°C to + 150°C
1433 mV
1362mW
260°C

'Oerate cavity package 9.6 mWrC above 25·C; derate molded package
10.9 mWrC above 25·C.

Electrical Characteristics (Notes 2 and 3)
Symbol
VTH

VTL

Parameter
Differential Threshold Voltage

Differential Threshold Voltage

Conditions
lOUT = -400 /LA, VOUT ~ 2.5V

lOUT = 4 mA, VOUT::;: 0.5V

Typ

Max

Units

-7V::;: VCM::;: 7V

0.06

0.2

V

-15::;: VCM ::;:15V

0.06

0.3

V

-7V::;: VCM ::;:7V

-O.OS

-0.2

V

-15V::;: VCM ::;: 15V

-O.OS

-0.3

V

0.47

0.7

V

Min

lOUT = -400 /LA, VOUT ~ 2.5V

-7V::;: VCM::;: 7V

lOUT = 4 mA, VOUT ::;: 0.5V

-7V::;: VCM::;: 7V

VTH
VTL

Differential Threshold Voltage
with Fail-Safe Offset = 5V

RIN

Input Resistance

-15V::;: VCM::;: 15V, OV::;: VCC::;: 7V

-0.2 -0.42
4

5

V
ko.

RT

Line Termination Resistance

TA = 25°C

100

1S0

300

0.

Ro

Offset Control Resistance

TA = 25°C

42

56

70

ko.

IINO

Data Input Current (Unterminated) VCM = 10V
OV::;: VCC::;: 7V

VCM = OV
VCM = -10V
VTHB

Input Balance
(Note 5)

lOUT = -400 /LA, VOUT ~ 2.5V,
Rs = 5000.

-7V::;: VCM 7V

lOUT = 4 mA, VOUT ::;: 0.5V,
Rs = 5000.

-7V::;: VCM::;: 7V

VOH

Logical "1" Output Voltage

lOUT = -400 /LA, VOIFF = 1V, VCC = 4.5V

VOL

Logical "0" Output Voltage

lOUT = 4 mA, VOIFF = -1V, VCC = 4.5V

Icc

Power Supply Current

VCC = 5.5V
VCM = 15V
VOIFF = -0.5V, (Both Receivers)
VCM = -15V

2.5

2

3.1

mA

a

-0.5

mA

-2

-3.1

mA

0.1

0.4

V

-0.1

-0.4

V

0.35

0.5

V

10

16

mA

10

16

mA

3

V

IINUl

Logical "1" Strobe Input Current

VSTROBE = 5.5V, VOIFF = 3V

1

100

/LA

liN

Logical "0" Strobe Input Current

VSTROBE = OV, VOIFF = -3V

-290

-400

/LA

VIH

Logical "1" Strobe Input Voltage

VOL::;: 0.5, lOUT = 4mA

VIL

Logical "0" Strobe Input Voltage

VOH ~ 2.5V, lOUT, = -400/LA

(0)

2.0

1.12
1.12

V
O.S

V

-30 -100 -170 mA
Output Short-Circuit Current
VOUT = OV, VCC = 5.5V, VSTROBE = OV, (Note 4)
los
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the - 55·C to + 125·C temperature range for the OS78LS120 and across the O·C to + 70·C for the
OS88LS120. All typical values are for TA = 25·C, Vec = 5V and VCM = OV.
Note 3: All currents into device pins shown as positive. out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: Refer to EIA-RS422 for exact conditions.

1-196

c

en

-...

Switching Characteristics Vee = 5V, TA = 25°C

0)

r-

Typ

Max

Units

en
.....

38

60

ns

0
......

38

60

ns

Strobe Input to "0" Output

16

25

ns

Strobe Input to "1" Output

12

25

ns

Parameter

Conditions

Min

Differential Input to "0" Output
Differential Input to "1" Output

Response Pin Open, CL

=

15 pF, RL

=

2 kn

N

C

en
0)
0)

r-

en
.....
N
0

AC Test Circuit and Switching Time Waveforms
Differential and Strobe Input Signal
OUTPUT

INPUT
OPEN

':"

TL/F/7499-3

"Includes probe and test fixture capacitance
Z.5V ------~---""
OIFF
INPUT

-Z.5V - - - -

III

OUTPUT

t, = tf $ 10 ns
PAR = 1 MHz

tpdOIO)

Note: Optimum switching response is obtained by minimizing stray capacitance on Response Control pin (no external connection).

TL/F/7499-4

Application Hints
Balanced Data Transmission

OUTPUT

TL/F17499-5

1·197

o

N

0p-

t/)

Application Hints (Continued)

..J

Unbalanced Data Transmission

CO
CO

1/4 OSI488 DR

t/)

1/40S1891A10S3891

C
o

.......
N

op-

~
CO
......

OUTPUT

t/)

C

TL/F17499-6

Logic Level Translator

J

V,L

VT

OUTPUT

VIH

INPUT VOLTAGE

TL/F17499-7

The OS78LS120/0S88LS120 may be used as a level translator to interface between ± 12V MaS, ECL, TTL and
CMOS. To configure, bias either input to a voltage equal to
% the voltage of the input signal, and the other input to the
driving gate.

affecting the termination impedance of the transmission
line. Noise pulse width rejection vs the value of the response control capacitor is shown in Figures 1 and 2. This
combination of filters followed by hysteresis will optimize
performance in a worse case noise environment.
lOOk

LINE DRIVERS
~

Line drivers which will interface with the OS78LS1201
OS88LS120 are listed below.

...
:>:

:!N'

Balanced Drivers

OS26LS31
OS7830, OS8830
OS7831, OS8831
OS7832, OS8832
OS1691A,OS3691
OS1692, OS3692
OS3487

10k

~w

!=

wa:

~~

~~

Quad RS-422 Line Oriver

If)

lk

~

Oual CMOS
OualTTL
Oual TRI-STATE TTL
Oual TRI-STATE TTL
Quad RS-423/0ual RS-422 TTL
Quad RS-423/0ual TRI-STATE
RS-422 TTL
Quad TRI-STATE RS-422

NEGA,T!,VE INPU
III

JI

100
10

100

II

11111
lk

10k

RESPONSE CONTROL CAPACITOR (pFI
TLlF/7499-9

FIGURE 1. Noise Pulse Width vs
Response Control Capacitor

INPUT

Unbalanced Drivers

OS1488
OS75150

POSITIVE INPUT

Quad RS-232
Oual RS-232

OUTPUT

RESPONSE CONTROL AND HYSTERESIS

In unbalanced (RS-232/RS-423) applications it is recommended that the rise time and fall time of the line driver be
controlled to reduce cross-talk. Elimination of switching
noise is accomplished in the OS78LS120/0S88LS120 by
the 50 mV of hysteresis incorporated in the output gate.
This eliminates the oscillations which may appear in a line
receiver due to the input signal slowly varying about the
threshold level for extended periods of time.

U

-----,

NEGATIVE INPUT
NOISE PULSE

. - - ~.5V

l----t-

----2V

High frequency noise which is superimposed on the input
signal which may exceed 50 mV can be reduced in amplitude by filtering the device input. On the OS78LS1201
OS88LS120, a high impedance response control pin in the
input amplifier is available to filter the input signal without

POSITIVE INPUT
NOISE PULSE

n-

~

NOISE PULSE WIDTH
2V

0

L - -O.5V
TLlF/7499-10

FIGURE 2

1-198

c

Application Hints

(Continued)
are offset from 200 mV to 700 mV, referred to the non-inverting input, or -200 mV to -700 mV, referred to the
inverting input. Therefore, if the input is open or shorted, the
input will be greater than the input threshold and the receiver will remain in a specified logic state.

TRANSMISSION LINE TERMINATION
On a transmission line which is electrically long, it is advisable to terminate the line in its characteristic impedance to
prevent signal reflection and its associated noise/crosstalk. A 1800 termination resistor is provided in the
DS7BLS120/DSBBLS120 line receiver. To use the termination resistor, connect pins 2 and 3 together and pins 13 and
14 together. The 1800 resistor provides a good compromise between line reflections, power dissipation in the driver, and IR drop in the transmission line. If power dissipation
and IR drop are still a concern, a capacitor may be connected in series with the resistor to minimize power loss.

The input circuit of the receiver consists of a 5k resistor
terminated to ground through 1200 on both inputs. This network acts as an attenuator, and permits operation with common-mode input voltages greater than ± 15V. The offset
control input is actually another input to the attenuator, but
its resistor value is 56k. The offset control input is connected to the inverting input side of the attenuator, and the input
voltage to the amplifier is the sum of the inverting input plus
0.09 times the voltage on the offset control input. When the
offset control input is connected to 5V the input amplifier will
see VIN(INVERTING) + 0.45V or VIN(INVERTING) + 0.9V when
the control input is connected to 10V. The offset control
input will not significantly affect the differential performance
of the receiver over its common-mode operating range, and
will not change the input impedance balance of the receiver.

The value of the capacitor is recommended to be the line
length (time) divided by 3 times the resistor value. Example:
if the transmission line is 1,000 feet long, (approximately
1000 ns), and the termination resistor value is 1BOO, the
capacitor value should be 1852 pF. For additional application details, refer to application notes AN-22 and AN-10B.
FAIL-SAFE OPERATION

It is recommended that the receiver be terminated (5000 or
less) to insure it will detect an open circuit in the presence
of noise.

Communication systems require elements of a system to
detect the presence of signals in the transmission lines, and
it is desirable to have the system shut-down in a fail-safe
mode if the transmission line is open or shorted. To facilitate
the detection of input opens or shorts, the DS78LS1201
DS8BLS120 incorporates an input threshold voltage offset.
This feature will force the line receiver to a specific logic
state if presence of either fault is a condition.

The offset control can be used to insure fail-safe operation
for unbalanced interface (RS-423) or for balanced interface
(RS-422) operation.
For unbalanced operation, the receiver would be in an indeterminate logic state if the offset control input was open.
Connecting the fail-safe offset pin to 5V, offsets the receiver
threshold to 0.45V. The output is forced to a logic zero state
if the input is open or shorted.

Given that the receiver input threshold is ± 200 mV, an input
signal greater than ± 200 mV insures the receiver will be in
a specific logic state. When the offset control input (pins 1
and 15) is connected to Vee = 5V, the input thresholds

Unbalanced RS-423 and RS-232 Fail-Safe

LINE RECEIVER
1/2 DS78LS120

SV

TL/F/7499-11

(OFFSET CONTROL
INPUT OPEN)

(OFFSET CONTROL
INPUTc SV)

O.4SV
INPUT VOLTAGE

INPUT VOLTAGE

TLlF/7499-12

1-199

en
......
co
ren
~

N

o
......
C

en
(X)
co
ren
~

N

o

o

N
.....

tJ)

Application Hints (Continued)

..J
CO
CO

tJ)

C
......

Balanced RS-422 Fail-Safe
BALANCED
LINE DRIVER

o

N
.....

~
CO
......

tJ)

C

5V~-----------4~~

TL/F/7499-13

j
1

w

w

w

"":;ct

""ct

"":;ct

:;

o

o

~
~

I-

I-

~

o

0

>

>

>

I-

~

~
~
o

0

I-

:::>

o
..,

INPUT VOLTAGE

INPUT VOLTAGE

TLlF17499-14

For balanced operation with inputs open or shorted, receiver C will be in an indeterminate logic state. Receivers A and
B will be in a logic zero state allowing the NOR gate to
detect the open or short condition. The strobe will disable
receivers A and B and may therefore be used to sample the
fail-safe detector. Another method of fail-safe detection
consists of filtering the output of NOR gate 0 so it would not
indicate a fault condition when receiver inputs pass through
the threshold region, generating an output transient.

Truth Table

In a communications system, only the control signals are
required to detect input fault conditions. Advantages of a
balanced data transmission system over an unbalanced
transmission system are:
1. High noise immunity
2. High data ratio
3. Long line lengths

(For Balanced Fail-Safe)
Input

Strobe

A-Out

B-Out

C-Out

D-Out

0
1
X
0
1
X

1
1
1

0
1
0
1
1
1

1

0
1
X
0
0
0

0
0
1
0
0
0

0
0
0

0
0
1
1
1

1-200

c
en
......

Schematic Diagram
'"m
I

m

.......

u.

::J
f-

en

r-

en
.....
N

o
.......
C

en
en
en

..,

N

r-

en
.....

. _ - - - - - - 4 II

N

o

...
M

...
II

...

<:>

II
co

II
(!I

-

z
i=

z

0

ffi

II

~~

>

::f:E~
a::'"
WW
f-a::

~~
z,,Oz
z_

II
~
<:>

......

N

II

>

II

W....l

"'0
zc::
Of-

=

~~
c:: ...

N

II
..,...
'"

~~

(!II-

Co?~

I-Z

:;:

>

~'"

...

::0

"

II
;f.

1-201

~

::~

ffi-

::



(Continued)

CD
N
N

......
C
en

\

X

1
1
1
1----1
QQ TpLH
DO TpHL

ex>

CD
N
N

l>
......

>C

5O %

C

1
1
1
1----1
QQ TpHL
DO TpLH

en
ex>

CD
N
eN

TLIF/8511-8

......
C

en

FIGURE 5

ex>

CD
N
eN

l>

3.0V~1.3V
O.OV
I

\

1"------

1

~.:: ----I
TpLZ
VOH

1

IVOL + .3V

:----1
1
1

i ~

TpZL :----1

=\- 'VOH I\.

1
1.5V---- 1
TpHZI----1

.r::-::.
T1 2.0V

.3V :
1
1

TpZH 1----1
TL/F/8511-9

FIGURES

3V

J.----\,

~~

~.-------

1

---T--""
,--.. . ---v-: XCP
~
1

50

DO---~'--~I

1

1
1
1----1

1
1
1----1

TpLH

TpHL
TLIF/8511-10

FIGURE 7

1-211

III

<

C")

N

CJ)

co

Typical Applications

U'J

ESDI Application

C

......
C")

DS8923

DS8923

p---------.

N

CJ)

1- - - - - - - - -

1

co

U'J

NRZ READ DATA

C

......

<
N
N

CJ)

co

U'J

READ CLOCK

C

......
N
N

CJ)

co

U'J

C

NRZ WRITE DATA

WRITE CLOCK

~-

1

- - - - - - - - - - - _I

1

.. - - - - - - - - - - - - - _I

DRIVE

CONTROLLER

TL/F/8511-11

ST504 and ST412 Applications
DS8921

DS8922

r-----.,
I

r-------,

I

I

DRIVE 1

t.lF't.l READ DATA
I
I
DRIVE 2 :
I
I

ENI
DISK DRIVES
EN2

I

-----------.1
CONTROLLER

TL/F/8511-12

1-212

~National

~ Semiconductor
DS8924 Quad TRI-STATE® Differential Line Driver
General Description

Features

The OS8924 is a quad differential line driver designed for
digital data transmission over balanced lines. The outputs
are TRI-STATE® structures which are forced to a high impedance state when the appropriate output control pin
reaches a logic zero condition. All input pins are PNP buffered to minimize input loading for either logic one or logic
zero inputs. In addition, internal circuitry assures a high impedance output state during the transition between power
up and power down.

•
•
•
•
•
•
•
•
•
•

The OS8924 is pin and functionally compatible with
OS3487. It features improved performance over 3487-type
circuit as outputs can source and sink 48 mAo In addition,
outputs are not significantly affected by negative line reflections that can occur when the transmission line is unterminated at the receiver end.

Four independent driver chains
TRI-STATE outputs
PNP high impedance inputs
Power up/down protection
Fast propagation times (typ 12 ns)
TTL compatible
Single 5V supply voltage
Output rise and fall times less than 20 ns (typ 10 ns)
Pin compatible with OS3487 and MC3487
Output skew-2 ns typ

Block and Connection Diagrams
Dual-In-Line Package
10--0{} NON·INVERTING
16 VCC

INPUT A
INPUT
OUTPUTS A

JOo-t--lD INVERTING

[..-+-_-1

AlB CONTROL
OUTPUT
CONTROL
OUTPUTS B [

TLIF/8507-1

INPUT B
GND

TL/F/8507-2

Top View

Order Number DS8924J or N
See NS Package J16A or N16A

Truth Table
Input

Non-Inverter
Output

H
H

H

L

L

L

Z

H
Z

H
L
X
= Low logic state
H = High logic state
L

X = Irrelevant
Z

=

Inverter
Output

Control
Input

TRI·STATE (high impedance)

1-213

"'I:t'
N

en

CIO

en
c

Absolute Maximum Ratings (Note 1)
If Militaryl Aerospace specified devices are required,
contact the National Semiconductor Sales Officel
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Storage Temperature
- 65°C to + 150°C
Lead Temperature (Soldering, 4 sec.)
260°C

Maximum Power Dissipation· at 25°C
1550mW
Cavity Package
1560 mW
Molded Package
"Derate cavity package 10.3 mWI'C above 25'C; derate molded package
12.5 mWI'C above 2S'C.

Operating Conditions
Supply Voltage (Vce)
DS8924
Temperature (TA)
DS8924

Electrical Characteristics
Symbol

Input Low Voltage

VIH

Input High Voltage

IlL

Input Low Current

IIH

Input High Current
Input Clamp Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

VOH

Output High Voltage

VIL

5.25

V

0

70

·C

Typ

Max

Units

0.8

V

-200

/LA

V

= 0.5V
VIH

= 2.7V
= 5.5V

= -18 mA
= 48 mA
10H = -20 mA
10H = -48 mA
ICL

10L

loz

=
Vo =
Vo =
Vo =
Vo

Output Leakage Current Power OFF

Vcc

= OV

50

/LA

100
-1.5

/LA
V

0.5

V

2.5

V

2.0

V

-80

Output Short-Circuit Current
Output Leakage Current (TRI-STATE)

Ivos - vosl

4.75

2.0

los

10FF

Units

Min

Conditions

VIH
VCL

Max

(Notes 2, 3,4 and 5)

Parameter

VIL

Min

-260

mA

0.5V

-100

/LA

5.5V

100

/LA

6V

100

/LA

-100
0.4

/LA
V

0.4

V

-0.25V

Difference in Output Offset Voltage

V

2.0

VT

Differential Output Voltage

IVTI-lvTI

Difference in Differential Output
Voltage

Icc

Power Supply Current

Switching Characteristics Vee =

Active

50

80

mA

TRI-STATE

35

60

mA

5V, TA = 25°C

Input to Output

Typ
12

Max

tpHL

20

ns

tpLH
Skew

Input to Output

12

20

ns

Output to Output

2.0

5.0

ns

tTHL

Differential Fall Time

10

20

ns

10

20

ns

17

25

ns

20

30

ns

13

25

ns

Symbol

Conditions

Parameter

tTLH

Differential Rise Time

tpHZ

Enable to Output

tpLZ

Enable to Output

tpZH

Enable to Output

CL

= 50 pF

= 200n, CL = 50 pF
RL = 200n, CL = 50 pF
RL = 00, CL = 50 pF, S1 Open
RL = 200n, CL = 50 pF, S2 Open

RL

Min

Units

17
30
ns
Enable to Output
tpZL
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified, minImax limits apply across the O'C to + 70'C range for the 058924. All typicals are given for Vcc = 5V and TA = 2S'C.
Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.
Note 4: Only one output at a time should be shorted.
Note 5: Symbols and definitions correspond to EIA RS·422, where applicable.
1-214

c

en

AC Test Circuits and Switching Time Waveforms

co

CD
N

~

3V----------J~--------~

INPUT
OV---..I
INPUT

CL· 50 pF
INCLUDES PROBE

AND JIG CAPACITANCE

I

OUTPUT

1.5V

1.5V

Input pulse: f = 1 MHz, 50%; tr = tf

S 15 ns.
TL/F/BS07-3

FIGURE 1. Propagation Delays
5V

Jzoo

1/4058924

3V OR
OV

~SI

CONTROL
INPUT
CONTROL
INPUT

OV
VOH

lk

----+-.,

tpZH

VOH----~~~---

OUTPUT

im'fiiITf
VOL-----~..I-~~

VOL----~~·~--­

Input pulse: f = 1 MHz, 50%; tr
51 and 52 closed except as noted.
CL includes probe and jig capacitance.

tpZL

~

tf

S 15 ns.

51 = open for tpZH
52 = open for tpZL
TLIF/BS07-4

FIGURE 2. TRI-STATE Enable and Disable Delays
RL
100

3V
INPUT

INPUT

TEM CT2
CURRENT TRANSFORMER
OR EQUIVALENT

OV

11---------.1 90%

TT
':'

':'

OUTPUT
(DIFFERENTIAL)

CL
15 pF
INCLUDING PROBE
AND JIG CAPACITANCE

tTLH

tTHL

Input pulse: f = 1 MHz, 50%; tr = tf

S 15 ns.
TL/F/BS07-S

FIGURE 3. Differential Rise and Fall Times

1-215

•

~National

~ Semiconductor
J.tA9622/DS9622 Dual Line Receiver
General Description
The p.A9622/DS9622 is a dual line receiver designed to
discriminate a worst case logic swing of 2V from a ± 10V
common mode noise Signal or ground shift. A 1.5V threshold is built into the differential amplifier to offer a TTL compatible threshold voltage and maximum noise immunity. The
offset is obtained by use of current sources and matched
resistors.
The p.A9622/DS9622 allows the choice of output states
with the input open, without affecting circuit performance by
use of S3. A 1300 terminating resistor is provided at the
input of each line receiver. An enable is also provided for
each line receiver. The output is TTL compatible. The output

high level can be increased to 12V by tying it to a positive
supply through a resistor. The output circuits allow wired-OR
operation.

Features
•
•
•
•
•
•
•
•

TTL compatible threshold voltage
Input terminating resistors
Choice of output state with inputs open
TTL compatible output
High common mode
Wired-OR capability
Enable inputs
Logic compatible supply voltages

Connection Diagram
14-Lead DIP

TL/F/9760-2

Top View
Order Number p.A9622DM or DS9622MJ
See NS Package Number J14A*

• For most current package information, contact product marketing.

1-216

Absolute Maximum Ratings

(Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Voltage Applied to Outputs
for Output High State
V- to GND

Storage Temperature Range

-65'C to + 175'C

Enable to GND

Operating Temperature Range

- 55'C to + 125'C

Lead Temperature (Soldering, 60 sec.)

400mW

V+ toGND

Supply Voltage, Vcc
Temperature, TA

-0.5Vto +7.0V

Input Voltage

-0.5Vto -12V
-0.5V to + 15V

Operating Conditions

300'C

Internal Power Dissipation

- 0.5V to + 13.2V

±15V

Min
4.5
-55

Max
5.5
+125

Units
V
'C

Electrical Characteristics (Notes 2,3)
Symbol
VOL

VOH

ICEX

Parameter

Conditions

Min

Max

Units

0.4

V

V+ = S3 = 4.5V, V- = -11V,
VOIFF = 2.0V, 10l = 12.4 mA,
EN = Open

Output Voltage LOW

V+ = 4.5V, V- = -9.0V,
S3 = OV, VOIFF = 1.0V,
10H = -0.2 rnA, EN = Open

Output Voltage HIGH

Output Leakage Current

V

2.8

V+ = 4.5V, V- = -11V,
S3 = OV, VOIFF = 1.0V,
Va = 12V, EN = Open

200

Il A

-1.4

mA

5.0

Il A

Output Short Circuit
Current (Note 4)

V+ = 5.0V, V- = -10V,
VOIFF = 1.0V, Va = S3 = OV,
EN = Open

IR(EN)

Enable Input
Leakage Curent

V+ = S3 = 4.5V, V- = -11V,
IN = Open, EN = 4.0V

IF(EN

Enable Input
Forward Current

V+ = 5.5V, V- = -9.0V
VI = Open, EN = S3 = OV

-1.5

rnA

IF(+IN)

+ Input Forward Current

V+ = 5.0V, V- = -10V,
VI+ = OV, VI- = GND,
EN = S3 = Open

-2.3

mA

V+ = S3 = 5.0V, V- = -10V,
VI+ = GND, VI- = OV,
EN = Open

-2.6

rnA

los

IF(-IN)

VI dEN)

-Input Forward Curent

4.5V ~ V+ ~ 5.5V,
-11V ~ V- ~ -9.0V,
EN = Open

Input Voltage LOW

Differential Input
Threshold Voltage

4.5V, ~ V + ~ 5.5V,
-11V ~ V- ~ -9.0V,
EN = Open

VCM

Common Mode Voltage

V+ = 5.0V, V- = -10V,
1.0V ~ VOIFF ~ 2.0V

RT
1+

Terminating Resistance

1-

Negative Supply Current

VTH

Positive Supply Current

SWITCHING CHARACTERISTICS T A
tpLH

Propagation Delay
to High Level

tpHl

Propagation Delay
to Low Level

-3.1

+25'C

1.0

+125'C

0.7

V

-55'C

1.3

V

1.0

2.0

V

-10

+10

V

25'C
25'C

V+
V-

= S3 = VI+ = 5.5V,
= 11V, VI- = OV

91

25'C

V

215

0

22.9

rnA

-11.1

rnA

= 25'C
V+ = 5.0V,
V- = -10V,
OV ~ VI ~ 3.OV,
Cl = 30 pF
(See Figure 1 )

Rl

= 3.9 kO

RL

= 3900

50

ns

50

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified MinIMax limits apply across the -55'C to

+ 125'C temperature range. All typicals are given for Vee =

5V and TA

= 25'C.

Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.
Note 4: Only one output at a time should be shorted.

1-217

N
N
CD

Q)

U)

Switching Time Test Circuit and Waveforms

C

......
N
N
CD

Q)

<::L

Vl

V, 3.: \1:.5V.______ ".5V

f? ~I!R'.m

~LH

~tPHL

Vo
O'5~ ~~~~

TL/F/9760-4

________=~
TLIF /9760-5

FIGURE 1

Equivalent Circuit
~--'--'------~----~------'--------1~--~~------'-----'-----~~-----V+
5k.o.
OUTB

+INA

RA

-IN A~~y..,.--""-MI-+------I----"""

S3~~---------+----~----~--------+---~

~----~----+-------~--------------~~--~~----~-----------vTLIF/9760-6

1-218

~National

~ Semiconductor
J.LA9627/DS9627 Dual Line Receiver
General Description
The /lA9627/0S9627 is a dual-line receiver which meets
the electrical interface specifications of EIA RS-232C and
MIL-STO-188C. The input circuitry accommodates ±25V input signals and the differential inputs allow user selection of
either inverting or non-inverting logic for the receiver operation. The /lA9627/0S9627 provides both a selectable hysteresis range and selectable receiver input resistance.
When pin 1 is tied to V-, the typical switching points are at
2.6V and - 2.6V, thus meeting RS-232-C requirements.
When pin 1 is open, the typical switching points are at
50 /lA and - 50 /lA, thus satisfying the requirements of MILSTO-188C LOW level interface. Connecting the RA and/or
RB pins to the (-) input yields an input impedance in the
range of 3 kn to 7 kn and satisfies RS-232-C requirements;
leaving RA and/or RB pins unconnected, the input resistance will be greater than 6 kn to satisfy MIL-STO-188C.

The output circuitry is TTL/OTL compatible and will allow
"collector-dotting" to generate the wired-OR function. A
TTL/OTL strobe is also provided for each receiver.

Features
•
•
•
•
•
•
•
•

EIA RS-232-C input standards
MIL-STO-188C input standards
Variable hysteresis control
High common mode rejection
R control (5 kn or 10 kn)
Wired-OR capability
Choice of inverting and non-inverting inputs
Outputs and strobe TTL compatible

Connection Diagram
16-Lead DIP

HYSTERESIS
OUT A
STROBE A

3
4

.~

5

-j

RA
+IN A

6
A
+

16
15
OUT B
14
STROBE B
13
-NC
12
-IN B
11
RB
10

I-Y+

2

NC-IN A

'-'

----2..

B
+

6
7

t-

•

+IN B
9
-Y-

8
GND-

TL/F/9761-1

Top View
Order Number /lA9627DM or DS9627MJ
See NS Package Number* J16A
• For most current package information, contact product marketing.

1-219

Absolute Maximum Ratings

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range

- 65°C to + 175°C

Operating Temperature Range

- 55°C to + 125°C

Lead Temperature (Soldering, 60 sec.)

- 0.5V to + 5.5V

Applied Output Voltage

-0.5Vto +15V

Operating Conditions

300°C

Internal Power Dissipation

400mW

V+ to GND

OVto +15V

V- to GND

OVto -15V

±25V

Input Voltage Referred to GND
Strobe to GND

Min

Max

Supply Voltage (Vee)

4.5

5.5

Units
V

Temperature (TA)

-55

+125

°C

Electrical Characteristics
Hysteresis, -IN A, -IN S, RA and RS Open for MIL-STD-188C, unless otherwise specified (Notes 2 and 3)
Symbol

Characteristics

VOL

Output Voltage LOW

VOH

Output Voltage HIGH

los

Output Short Circuit
Current (Note 4)

IIH(ST)

Input Current HIGH
(Strobe)

Min

Conditions

= 10.8V, V- = -13.2V,
= 0.6V, IOL = 6.4 mA
V+ = 10.8V, V- = -13.2V,
VI+ = 0.6V, IOH = -0.5 mA
V+ = 13.2V, V- = -10.8V,
VI+ = 0.6V, Va = ov
V+ = 10.8V,
V- = -13.2V, VI+ = 0.6V

V+
VI +

RI

Input Resistance

V+ = 13.2V, V- = -13.2V,
-3.0V ~ VI+ ~ 3.0V

ITH+

Positive Threshold Current

± 10.8V ~ Vee ~ ± 13.2V,
Vo = 2.4V

ITH-

Negative Threshold Current

± 10.8V ~ Vee ~ ± 13.2V,
Va = O.4V

VldST)

Input Voltage LOW (Strobe)

VI+

VIH(ST)

Input Voltage HIGH (Strobe)

V+
VI+

1+

Positive Supply Current

± 10.8V ~ Vee ~ ± 13.2V
VI+ = -0.6V

1-

Negative Supply Current

±10.8V ~ Vee
VI+ = 0.6V

= -0.6V
= 13.2V, V- =
= -0.6V

~

I

I

VST
VST

=
=

Max

Units

0.4

V

2.4

V

-3.0

mA

2.4V

40

p.A

5.5V

1.0

mA

kn

6.0
100
-100

p.A
p.A

0.8
-10.8V,

V

2.0

V
18

±13.2V

-16

mA
mA

Electrical Characteristics

+ IN A and -IN S connected to ground, RA and RS connected to -IN A and -IN S
and Hysteresis connected to V- for RS-232C, unless otherwise specified
Symbol
RI

Characteristics
Input Resistance

VI

Input Voltage

VTH+

Positive Threshold Voltage

Conditions

Min

Max

Units

3.0V ~ VI ~ 25V

3.0

7.0

kn

-3.0V ~ VI ~ -25V

3.0

7.0

kn

-2.0

2.0

V

3.0

V

-3.0
V
Negative Threshold Voltage
VTHNote 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified MinIMax limits apply across the -55'C to + 125'C temperature range.
Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.
Note 4: Only one output at a time should be shorted.

1-220

'1=

Electrical Characteristics
Symbol

Vee

»
CD

= ±12VforMIL-STD-188CandRS-232C,TA = 25°C

Characteristics

Conditions

Propagation Delay to High Level
Propagation Delay to Low Level

0')

Max

Units

(See Figure 1)

250

ns

(See Figure 1)

250

ns

Min

N
......
......

C

en
CD
0')

N
......
Vo

-S.OV

+S.OV

lkD.
+IN

---+--11-------"\1

:1:1%

-S.OV---

-IN

3.92kD.

:1:1%
--V-=-12V
HYS OPEN
TL/F/9761-2
TL/F/9761-3

15 pF includes jig capacitance. All diodes are FD777 or equivalent.
PRR = 10 kHz
PW

=

50 f1.s

Ir = If = 5 ns

FIGURE 1. Switching Time Test Circuit and Waveforms

1-221

p,A9627/DS9627

m

Y+
Rll
1.2Bk.o.

Cl
1.1 pF

tTl

R14
6k.o.

017

R43
700.0.

24 k.o.

<"

CD

::J

Bk.o.

~ R4

c:::

Q)

.'N --r-lRl

R2
11.3 k.o.

.c

I

0

-r ---r

--~

03

..L

010

::;"

(')

1

I
R7
Bk.o.

~

R13
345.0.

J...

C2
1.1 of ..,...

RB
2k.o.

'"

f\)
f\)

~

;::;
R42
7.6k.o.

hOIl

4k.o.

c:::

*019

-IN

09 I

04

~I

~12

~

g,
0

~.

R34
11.3 k.o.

c

a

R41
3.2k.o.

OUT
GNO

DB
07

D1-d
STROBE

I.L KU...I:--J
_

014

015
015

f

R24
_ 5.3k.o.

y-

HYS

T

~

R22
1.12 k.o.

~

R25
450.0.

~

R23
450.0.

~

016
R21
5.3k.o.

R29
3.76k.o.

1

TLlF/9761-4

c
en
CD

~National

(7)

eN

~ Semiconductor

(7)

»
......

1=

DS9636AI J.tA9636A
RS-423 Dual Programmable Slew Rate Line Driver
General Description
The DS9636A1 p.A9636A is a TTL/CMOS compatible, dual,
single ended line driver which has been specifically designed to satisfy the requirements of EIA Standard RS-423.
The DS9636A1 p.A9636A is suitable for use in digital data
transmission systems where signal wave shaping is desired.
The output slew rates are jointly controlled by a single external resistor connected between the wave shaping control
lead (WS) and ground. This eliminates any need for external
filtering of the output signals. Output voltage levels and slew
rates are independent of power supply variations. Currentlimiting is provided in both output states. The DS9636A1
p.A9636A is designed for nominal power supplies of ± 12V.

Inputs are TTL compatible with input current loading low
enough (1/10 UL) to be also compatible with CMOS logic.
Clamp diodes are provided on the inputs to limit transients
below ground.

Features
•
•
•
•
•

Programmable slew rate limiting
Meets EIA Standard RS-423
Commercial or extended temperature range
Output short circuit protection
TTL and CMOS compatible inputs

Connection Diagram
8·Lead DIP

WAVESHAPE

V+

CONTROL

IN A
IN B
GND

OUT A

Order Number DS9636ACJ, p.A9636ARC,
DS9636AMJ, p.A9636ARM or DS9636ACN, p.A9636ATC
See NS Package Number J08A or N08E

OUT B

VTLIF/9620-1

Top View

·For most current package information. contact product marketing.

1-223

»
CD
(7)

eN

(7)

»



JLs

W

l>

JLs

TO
OTHER +--I---I-~;;;...-+-+-......----I---+-4-+-~
CHANNEL

v+

06

R2
6Jl

OUT

Rl
7Jl

TO
O~ER+--L+-~~--+--f--~-~"""~~-+-~~--+-;--~---r~
CHANNEL

TO
OTHER + - " ' 1 " ' + - - I : - - - + - - + - - - t - - - + - + -........,....~~--+-----t---;r--+---t--t
CHANNEL

018

CHANNEL

R6
25kJl

TO
OTHER . -......
CHANNEL

R9
910Jl

'----4_-.....- -.....~----.............-~-+-----....-----.....--~-.......--~-.....----.....-

o

- - - - - = COIolIION TO

BO~

v-

CHANNELS

= CROSSUNOER
TLIF/9620-2

FIGURE 1. Equivalent Circuit

1-225

eo
0')

0')

WSC IN
IN
TO
OTHER +--+--~~-"""--'-----+--"--+-+---'--------1---"-~:---"--1-"""­
CHANNEL

TO
019
O~ER.-~~-t-~--I--+~-+~~-I---+---+~----+----+-~R~6-+-~---+--+--;
2.53 kJl

w

0')

l>
......

Typical Performance Characteristics
Input/Output Transfer
Characteristic vs Temperature
Vee=:l:12V
Rws = 100kllRL = 45011 -

...
I

~

g
....
:::l

6.0
4.0
2.0

125OCf-700C -I--

o -4.0

4(

100

~

SO

o.s

Q.4

-ISO

1.8

....

i
....

~

0

0

-20
-40
-60
-80

;

-

-55OC

!:;

-

2SOC

f--

1250C

5
0

~:=
I)

;

(

30
20

-20
-30
-40

LOGIC

VI = 1
I-

~ -20

II

VI

7

LOGIC
VI = I I -

VI
~

LOGIC
VI = 0 l -

-30

I
-55

o

70

25

TE~PERATURE

OUTPUT VOLTAGE - V

I

lJ.J

I I

LoJ

125

- OC

l000nn;ra
100

i=

g
<>

~

-40

-100
-10 -8.0-6.0-4.0-2.0 0 2.0 4.0 6.0 8.0 10

VI = OV

J

-10-8.0-6.0-4.0-2.002.0 4.D 6.0 8.0 10

::IE

1+ LOGIC

~ -10

II

I I
I I

Transition Time vs Rws

I VI = 01-

1~

I I

-10

OUTPUT VOLTAGE - V

Vcc=:l:12V
Rws = 100 kll

40

~

VI = 2V

10

-SO

Supply Current
vs Temperature

II

Vee=:l:12V
Rws = 100kllTA = ?5OC . -

40
30
20

INPUT VOLTAGE - V

100

80
Vee = VI = OV I I
60 F0600 DIODE CONNECTED I 40 IN SERIES WITH Vee PIN f-20

~

1250C l -

-1.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0

Output Current vs
Output Voltage (Power Off)

~

25OCl-

I

INPUT VOLTAGE - V

-<

-55OC:-

I

~

~ -100

1.6

Output Current vs
SOOutput Voltage (Power On)

I
I

-200
1.2

I

Vee =:l:12V I
I - Rws = 100 kll

ISO

~

-55OC

-6.0

I

200

i3 -SO
....

250C - I - .
ooc -f----:

5 -2.0

Input Current vs
Input Voltage

~

10

LoJ

VI

0:

1.0
10K 20K50K lOOK 300K 1.0104

3.0104

WAVE SHAPING RESISTANCE - .0.
TL/F/9620-3

+12V

~-.....--+-_VO
51.0.
Offset: OV
Pulse Width: 500 /Ls

TL/F/9620-5

PRR: 1.0 kHz

tr

-12V

= tf

~

10 ns

TL/F/9620-4

Note: CL includes jig and probe capacitance

FIGURE 2. AC Test Circuit and Waveforms

Note: Use 1 N4448 or equivalent.

V-

TLIF/9620-6

FIGURE 3. RS-423 System Application

1·226

~National

~ Semiconductor
DS9637 AI p.A9637 A

Dual Differential Line Receiver
General Description

Features

The OS9637 AlILA9637 A is a Schottky dual differential line
receiver which has been specifically designed to satisfy the
requirements of EIA Standards RS-422 and RS-423. In addition, the OS9637 AlILA9637 A satisfies the requirements of
MIL-STO 188-114 and is compatible with the International
Standard CCITT recommendations. The OS9637 AI
ILA9637 A is suitable for use as a line receiver in digital data
systems, using either single ended or differential, unipolar or
bipolar transmission. It requires a single 5V power supply
and has Schottky TTL compatible outputs. The OS9637 AI
ILA9637 A has an operational input common mode range of
± 7V either differentially or to ground.

•
•
•
•
•
•
•
•
•

Oual channels
Single 5V supply
Satisfies EIA standards RS-422 and RS423
Built-in ± 35 mV hysteresis
High common mode range
High input impedance
TTL compatible output
Schottky technology
Extended temperature range

Connection Diagram
8-Lead DIP and SO-8 Package

Order Number DS9637 ACJ, ILA9637ARC,
DS9637AMJ, ILA9637ARM
See NS Package Number J08A *

.~,-.,._8 +IN A

Order Number DS9637ACM, /LA9637ASC
See NS Package Number M08A

''--'"------I-=-7 -IN A

Order Number DS9637ACN, /LA9637ATC
See NS Package Number N08E

L..-..-,..6_ +IN B

'r--L..-.L5~ -IN B

'For most current package information, contact product marketing.

TL/F/9621-1

Top View

1-227

Absolute Maximum Ratings (Note 1)
If MilitaryI Aerospace specified devices are required,
contact the National Semiconductor Sales Officel
Distributors for availability and specifications.
Storage Temperature Range
Ceramic DIP
-65°C to + 175°C
Molded DIP
- 65°C to + 150°C
Lead Temperature
Ceramic DIP (Soldering, 30 seconds)
300°C
Molded DIP and SO Package
(Soldering, 10 seconds)
265°C
Maximum Power Dissipation* at 25°C
Cavity Package
1300 mW
Molded Package
930mW
SO Package
810mW

Vee Lead Potential to Ground

-0.5V to 7.0V

Input Potential to Ground

± 15V

Differential Input Voltage

± 15V

Output Potential to Ground

- 0.5V to + 5.5V

Output Sink Current

50 mA

Recommended Operating
Conditions

• Derate cavity package B.7 mwre above 2S'C; derate molded DIP package
7.S mWI'C above 2S'C; derate 50 package 6.S mWrC above 2S'C.

059637 AM/,...A9637 AM
Supply Voltage (Vee)
Operating Temperature (TA)

Min
4.5
-55

Max
5.5
+125

Units
V
°C

059637 AC/,...A9637 AC
Supply Voltage (Vee)
Operating Temperature (TA)

4.75
0

5.25
+70

V
°C

Electrical Characteristics
Over recommended operating temperature and supply voltage ranges, unless otherwise specified (Notes 2 and 3)
Symbol

Parameter

Conditions

VTH

Differential Input
Threshold Voltage (Note 5)

-7.0V:5: VeM:5: +7.0V

VTH(R)

Differential Input
Threshold Voltage (Note 6)

-7.0V :5: VeM :5: + 7.0V

II

Input Current
(Note 7)

VI

= 10V, OV :5: Vee :5: +5.5V

VI

= -10V,OV:5: Vee:5: +5.5V

VOL

Output Voltage LOW

IOL

= 20 mA, Vee = Min

VOH

Output Voltage HIGH

IOH

= -1.0 mA, Vee = Min

los

Output Short Circuit
Current (Note 4)

Va

= OV, Vee = Max

Ice

Supply Current

Vee
VI-

VHYST

Input Hysteresis

VeM

Min

Typ

Max

Units

-0.2

+0.2

V

-0.4

+0.4

V

1.1
-3.25

3.25

mA

-1.6
0.35

0.5

V

2.5

3.5

-40

-75

-100

mA

= Max, VI + = 0.5V,
= GND

35

50

mA

= ±7.0V (See Curves)

70

V

mV

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified MinIMax limits apply across the - SS'C to
the DS9637A5C. All typicals are given for VCC = SV and TA = 2S'C.

+ 12S'C temperature range for DS9637AM and across the O'C to + 70'C range for

Note 3: All currents into the device pins are positive; all currents out of the device pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 4: Only one output at a time should be shorted.
Note 5: VOIFF (Differential Input Voltage)
Note 6:

soon

= (VI +) - (VI-)' VCM (Common Mode Input Voltage) = VI + or VI-'

± 1 % in series with inputs.

Note 7: The input not under test is tied to ground.

1-228

)'

Switching Characteristics Vee
Symbol

=

5.0V. TA

=

c
en
CD

25°C

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High

See AC Test Circuit

tpHL

Propagation Delay Time
High to Low

See AC Test Circuit

Min

Typ

Max

Units

15

25

ns

en
w
......

>
.....

1=

>

CD

13

25

en
W
......

ns

>

Vee
R7
R8

R24

R14

R15

R23
02

OUT

-IN ~~W\r-""+----+----"

III
GNO
TL/F/9621-2

FIGURE 1. Equivalent Circuit

1-229

Typical Input/Output Transfer Characteristics
4

4

Vcc= 5.25V

VJ=4.75V

3

I
I
I
I

I

I
I
I
I
I
I
I

:h

(!)

I

~
-I

I

I-

VC\I=OV? :

I!:
::;)

: VCW =*7V

o
>

2
I

::;)

o
-100

I

IJ.I

~=*7V

.

2

;1

3

>

I

-50

II

o

I
I
I

o

VC\I=OV/ :
I
I
I
I

o
50

-100

100

INPUT VOLTAGE - mV

-50

50

100

INPUT VOLTAGE - mV
TL/F/9621-4

TLIF/9621-3

AC Test Circuit and Waveforms
+0.5V ----:-__----"""
VI

-0.5V

VO--_J
TL/F/9621-6

VI
Amplitude: 1.0V

TLIF/9621-5
Notes:

Offset: 0.5V
Pulse Width: 100 ns

CL includes jig and probe capacitance.

PRR: 5.0 MHz

All diodes are FD700 or equivalent.

tr

=

tf ~ 5.0 ns

FIGURE2a

FIGURE 2

1-230

Typical Applications
TWISTED PAIR
OR
rLAT CABLE

+5V

SL

+5V

+

DUAL RS-422 LINE DRIVER

+5V

TLlF/9621-7

FIGURE 3. RS-422 System Application (FIPS 1020) Differential Simplex Bus Transmission
Notes:

RT

;0,

50n for RS·422 operation.

RT combined with input impedance of receivers must be greater than 90n.

1-231

~National

PRELIMINARY

D Semiconductor
OS96381 p,A9638
RS-422 Dual High Speed Differential Line Driver
General Description

Features

The OS9638/ fLA9638 is a Schottky, TTL compatible, dual
differential line driver designed specifically to meet the EIA
Standard RS-422 specifications. It is designed to provide
unipolar differential drive to twisted pair or parallel wire
transmission lines. The inputs are TTL compatible. The outputs are similar to totem pole TTL outputs, with active pullup and pull-down. The device features a short circuit protected active pull-up with low output impedance and is specified to drive 50n transmission lines at high speed. The miniDIP provides high package density.

•
•
•
•
•
•
•
•
•
•
•
•

Single 5V supply
Schottky technology
TTL and CMOS compatible inputs
Output short circuit protection
Input clamp diodes
Complementary outputs
Minimum outupt skew « 1.0 ns typical)
50 mA output drive capability for 50n transmission lines
Meets EIA RS-422 specifications
Propagation delay of less than 10 ns
"Glitchless" differential output
Delay time stable with Vee and temperature variations
«2.0 ns typical) (Figure 3)
• Extended temperature range

Connection Diagram
8-Lead DIP and SO-8 Package

v.1

cc

Order Number DS9638MJ, fLA9638RM,
DS9638CJ or fLA9638RC
See NS Package Number J08A *

'-''----1,;;.8 OUT A
-tF
A

IN A.l~vo_ _+7;""OUT
I

~
GND j; I '-1~

IN 8 211

Order Number DS9638CM or fLA9638SC
See NS Package Number M08A

6 OUT 8
5 OUT

Order Number DS9638CN or fLA9638TC
See NS Package Number N08E

B
TL/F/9622-1

·For most current package information: contact product marketing.

Top View

1-232

Absolute Maximum Ratings

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range
Ceramic DIP
- 65·C to + 175·C
- 65·C to + 150·C
Molded DIP and SO-8
Lead Temperature
Ceramic DIP (Soldering, 60 sec.)
Molded DIP and SO Package
(Soldering, 10 sec.)

Maximum Power Dissipation· at 25·C
Cavity Package
Molded Package
SO Package

1300 mW
930mW
810mW

-5Vto 7V
Vee Lead Potential to Ground
Input Voltage
-0.5Vto +7V
'Derate cavity package 8.7 mWrC above 25'C; derate molded DIP package
7.5 mW/'C above 25'C; derate SO package 6.5 mWC above 25'C.

300·C
265·C

Recommended Operating Conditions

Supply Voltage (Vee)
Output Current HIGH (IOH)
Output Current LOW (lad
Operating Temperature (TA)

DS9638M/ JJ.A9638M

DS9638C/ JJ.A9638C

Min

Typ

Max

Min

Typ

Max

Units

4.5

5.0

5.5
-50

4.75

5.0

-55

25

125

40
0

25

5.25
-50
50
70

V
mA
mA
·C

Electrical Characteristics Over recommended operating temperature and supply voltage ranges, unless otherwise specified (Notes 2 & 3)
Symbol

Parameter

VIH

Input Voltage HIGH

VIL

Input Voltage LOW

Conditions

Min

Typ

Max

2.0

V

O·Cto +70·C

0.8

- 55·C to + 125·C

0.5

= Min, II = -18 mA

Vie

Input Clamp Voltage

Vee

VOH

Output Voltage HIGH

Vee = Min,
VIH = VIH Min,
VIL = VILMax

-1.0

10H

= -10 mA

2.5

10H

= -40 mA

2.0

VOL

Output Voltage LOW

Vee = Min, VIH = VIH Min,
VIL = VIL Max, 10L = 40 mA

II

Input Current at Maximum
Input Voltage

Vcc

= Max, VI Max = 5.5V

Units

-1.2

V
V

3.5
V

0.5

V

50

JJ.A
JJ.A

IIH

Input Current HIGH

Vec

= Max, VIH = 2.7V

25

IlL

Input Current LOW

Vee

= Max, VIL = 0.5V

-200

JJ.A

los

Output Short Circuit Current

Vec

= Max, Vo = OV (Note 4)

-150

mA

vT,'h

Terminated Output Voltage

See Figure 1

vT-'h

Output Balance

0.4

-50
2.0

V
V

Vos, 'los

Output Offset Voltage

3.0

V

Vos-Vos

Output Offset Balance

0.4

V

Ix

Output Leakage Current

100

JJ.A

TA = 25·C
-0.25V < Vx < 6.0V

Vec = 5.5V,
65
mA
45
All input at OV,
No Load
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics provide conditions for actual device operation.
Note 2: Unless otherwise specified min/max limits apply across the - 55'C to + 125'C temperature range for the DS9638M and across the O'C to + 70'C range for
the DS9638C. All typicals are given for Vee = 5V and TA = 25'C.
Note 3: All currents into the device pins are positive; all currents out of the device pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 4: Only one output at a time should be shorted.

Ice

Supply Current
(Both Drivers)

1-233

co
Cot)
CD

Q)



>

I

I
I
I
I

w

~

o
>

I
I
I
I
I
I
I

I-

::::>

1=
::::>
o

I

II

~=t7V
I

~o
>

I'
I

1.1

:~=t7V

I

2

I

I-

::::>

1=
::::>

VCW=OV/ :
I
I
I
I

VCW=OV/ :
I
I
I
I

o

a
-100

;1

3

w

a
-50

50

-100

100

INPUT VOLTAGE- mY

-50

a

50

100

INPUT VOLTAGE - mY
Tl/F/9623-3

Tl/F/9623-4

FIGURE 2a

FIGURE 2

1-238

+O.5V -~~----~
VI
-O.5V

--_.1

Vo

TL/F/9623-6

VI
Amplitude: 1.0V
TLIF/9623-5

Offset: O.5V

Notes:
CL includes jig and probe capacitance.

Pulse Width: 500 ns
PRR: 1 MHz

All diodes are FD700 or equivalent.

tr = tf ~ 5.0 ns

FIGURE 3. AC Test Circuit and Waveforms

FIGURE 3a

Typical Applications
TWISTED PAIR
OR
FLAT CABLE

+5V

...JL

+5V

+

DUAL RS-422 LINE DRIVER

III
TL/F/9623-7

Notes:
Rt

~

son for RS-422 operation.

Rt combined with input impedance of receivers must be greater than 90n.

FIGURE 4. RS-422 System Application (FIPS 1020) Differential Simplex Bus Transmission

1-239

'III:t
.....
,...

LL.
CD

Q)

(/)

c
.....
,...

......

~National

PRELIMINARY

D Semiconductor

N

LL.
CD

Q)

(/)

DS96F172/DS96F174
RS-485/RS-422 Quad Differential Drivers

C

General Description
The DS96F172 and the DS96F174 are high speed quad
differential line drivers designed to meet EIA Standard RS485. The DS96F172 and the DS96F174 offer improved performance due to the use of new, state-of-the-art L-FAST
bipolar technology. The L-FAST technology allows for higher speeds and lower currents by utilizing extremely short
gate delay times. Thus, the DS96F172 and the DS96F174
feature lower power, extended temperature range, improved
RS-485 specifications, and meet SCSI specifications.
The DS96F172 and the DS96F174 have TRI-STATE® outputs and are optimized for balanced multipoint data bus
transmission at rates up to 15 Mbps. The drivers have wide
positive and negative common mode range for multipoint
applications in noisy environments. Positive and negative
current-limiting is provided which protects the drivers from
line fault conditions over a + 12V to - 7.0V common mode
range. A thermal shutdown feature is also provided. The
DS96F172 features an active high and active low Enable,
common to all four drivers. The DS96F174 features separate active high Enables for each driver pair.

respective device types are DS96F173,
DS36F95, DS96F177 and DS96F178.

DS96F175,

Features
•
•
•
•
•
•
•
•
•
•
•
•

Meets EIA Standard RS-485 and RS-422A
Meets SCSI specifications
Monotonic differential output switching
Transmission rate to 10 Mbps
TRI-STATE outputs
Designed for multipoint bus transmission
Common mode output voltage range: - 7.0V to + 12V
Operates from single + 5.0V supply
Extended temperatura range available
Lower power version
Thermal shutdown protection
DS96F172 and DS96F174 are lead and function compatible with the SN75172175174 or the AM26LS31!
MC3487 respectively

Compatible RS-485 receivers, transceivers, and repeaters
are also offered to provide optimum bus performance. The

Connection Diagrams
16-Lead Dual-In-Line Package
and 50-16 Package

TL/F/9625-1

Top View

TL/F/9625-2

Top View
Order Number DS96F172CJ, DS96F172MJ,
DS96F174CJ or DS96F174MJ
See NS Package Number J16A*
Order Number DS96F172CM or DS96F174CM
See NS Package Number M 16A
Order Number DS96F172CN or DS96F174CN
See NS Package Number N16A

'For most current package information, contact product marketing.

1-240

c
en
<0

Absolute Maximum Ratings (Note 1)

en

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range
Ceramic DIP
Molded DIP and SO-16

-65°C to + 175°C
- 65°C to + 150°C

Lead Temperature
Ceramic DIP (Soldering, 60 sec.)
Molded DIP and SO-16
(Soldering, 10 sec.)
Maximum Power Dissipation· at 25°C
Cavity Package
Molded Package
SO Package

."

Enable Input Voltage
5.5V
'Derate cavity package 10 mWI'C above 25'C; derate molded DIP package
8.3 mWI'C above 25'C; derate SO package 7.7 mW'C above 25'C.

.....

Supply Voltage (Vee)
DS96F172C/DS96F174C
DS96F172MI DS96F17 4M
Common Mode
Output Voltage (Voe)
Output Current HIGH (IOH)
Output Current LOW (IoU
Operating Temperature (TA)
DS96F172C/DS96F174C
DS96F172M/DS96F174M

265°C
1500 mW
1040 mW
960mW

...........

."

Min

Typ

Max

Units

4.75
4.50
-7.0

5.0
5.0

5.25
5.50

V

0
-55

+25
+25

I\)

c
en
<0

en

Recommended Operating
Conditions

300°C

...........

7.0V

Supply Voltage

+12.0

V

-60
60

rnA
rnA

+70
+125

°C

01:lIo

Electrical Characteristics Over recommended operating conditions, unless otherwise specified (Notes 2 & 3)
Symbol

Parameter

VIH

Input Voltage HIGH

VIL

Input Voltage LOW

Conditions

Min

Typ
Max Units
(Note 1)

2.0

V

ITA = O°Cto +70°C

0.8

ITA = -55°C to + 125°C

0.7

VOH

Output Voltage HIGH

VOL

Output Voltage LOW

10L = 55 mA

Vie

Input Clamp Voltage

11= -18 mA

IVOD11

Differential Output Voltage

10 = OmA

IVOD21

Differential Output Voltage

RL = 54n, Figure 1

1.5

2.0

RL = 100n, Figure 1

2.0

2.3

VOD

Differential Output Voltage

~IVODI Change in Magnitude of Differential
Output Voltage (Note 4)
Voe

10H = -55 mA, Vee = 5.0V,
TA = + 25°C to + 70°C

3.0

V

ITA = O°Cto + 70°C

VeM = -7.0Vto +12V

ITA = O°Cto +70°C

Common Mode Output Voltage (Note 5)
Mode Output Voltage (Note 4)
Output Current with Power Off

Vee = OV, Va = -7.0Vto +12V

High Impedance State Output Current

Vo = -7.0Vto +12V

IIH

Input Current HIGH

IlL
los

V
V

6.0

V
V
V

~Ivocl Change in Magnitude of Common

loz

2.0
-1.5

1.0

RL = 54n or 1oon, Figure 1

10

V

±0.2

V

3.0

V

±0.2

V

±50

IJ-A

±50

IJ-A

VI = 2AV

20

IJ-A

Input Current LOW

VI = OAV

-50

IJ-A

Short Circuit Output Current
(Note 6)

Vo = -7.0V

-250

Va = OV

-150

±20

250

Vo = +12V

,~ Supply Current (All Drivers)

rnA

150

Vo = Vee

No Load

leex

1-241

I Outputs Enabled

50

I Outputs Disabled

30

mA

III

Switching Characteristics Vcc =
Symbol

5.0V, T A

=

25°C
Conditions

Parameter

Min

RL =

60n, Figure 2

RL =

27n, Figure 3

tZH

Output Enable Time to High Level

RL =

11 on, FIgure 4

tZL

Output Enable Time to Low Level

RL =

11 on, Figure 5

tHZ

Output Disable Time from High Level

RL =

tLZ

Output Disable Time from Low Level

RL =

110n, Figure 4
11 on, Figure 5

tSKEW

Driver Output to Output

RL =

60n

tDD

Differential Output Delay Time

tTD

Differential Output Transition Time

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

Typ

Max

Units

15
15

20
22

ns

12

16

ns

12

16

ns

25

ns

25

32
32

25
20
1.0

30
25
4.0

ns

ns

ns

ns
ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the - 55'C to + 125'C temperature range for the DS96F172M/DS96F174M and across the O'C to
+ 70'C range for the DS96F172C/DS96FI74C. All typicals are given for Vee = 5V and TA = 25'C.
Note 3: All currents into the device pins are positive; all currents out of the device pins are negative. All voltages are reference to ground unless otherwise
specified.
Note 4: .:lIVool and .:lIVoci are the changes in magnitude of Voo and Voe respectively, that occur when the input is changed from a high level to a low level.
Note 5: In EIA Standards RS-422A and RS-4B5, VOC, which is the average of the two output voltages with respect to ground, is called output offset voltage, Vos.
Note 6: Only one output at a time should be shorted.

Parameter Measurement Information

vL .

~ RL

I

ENABLED
(Note 3)

2"

~-

~2" ~OC
Tl/F/9625-3

FIGURE 1. Differential and Common Mode Output Voltage

p-------- .

I
I

I

I

GENERATOR
(Note 1)

50n
~

-==
-

3V

I
I
I
I

I
I
I
I
I
I

.. _------_.

I

_
-

ENABLED
(Note 3)

cli

.L

CL

.I.

-

. J

IN

RL = O!T
60n

-1.

15~3V

5V

too I -

CL = 15 pF
(Note 2)

OUT

5~:J

10%

tTO-l
TLIF /9625-4

too
90%

-

FIGURE 2. Differential Output Delay and Transition Times

1-242

t.l

I

OV

::::2.5V

9O'~

10% ::::-2.5V

-

tTO
Tl/F/9625-5

Parameter Measurement Information

c
en
CO

(Continued)

0')

2.3V

3V
IN
OV

~:>-.-......-

OUT

GENERATOR

VOH

y

(Note 1)

OUT
VOL

TL/F/962S-6

"T1

.....
N
.....
-10

C

en
CO

0')

"T1
-10

.....
0l:Io

VOH

Z
OUT

VOL
TL/F/962S-7

FIGURE 3. Propagation Delay Times

IN -{j,5V I.5Vlzr ::

--o--.....- .....--OUT

LLVOH
GENERATOR

(Note 1)

50.0.

OUT

2.3V
•

3V

\---to.SV

I~~~FF=OV

(Note 4)

TLIF/962S-9

TL/F/962S-B

FIGURE 4. tZH and tHZ

5V
RL

=110.0.

~:>--'-""-OUT

0:: -1.:j.3V 1.5~::
'''-------r VOL

GENERATOR

0.5VI

(Note 1)

TLIF/962S-11

TLIF/962S-10

FIGURE 5. tZl and tLZ
Note 1: The input pulse is supplied by a generator having the following characteristics: PRR
tf ~ 5.0 ns, Zo = son.

1.0 MHz. duty cycle

50%, tr

~

Note 2: CL includes probe and jig capacitance.
Note 3: DS96F172 with active high and active low Enables is shown here. DS96F174 has active high Enable only.
Note 4: To test the active low Enable E of DS96F172 ground E and apply an inverted waveform to

1-243

E.

DS96F174 has active high Enable only.

5.0 ns,

III

"I:t'

r---

u:

m
c

Typical Application

CD

1/4 DS96f174

1/4 DS96f172

~D----4"""--""----

......

------ ------4I~-....-r--__--+

2Y

2A
GND 8
TL/F/9626-2

TL/F/9626-1

Top View

Top View

Order Number DS96172J, ,...A96172DC or DS96174J, ,...A96174DC
See NS Package Number J16A
Order Number DS96172N, ,...A96172PC or DS96174N, ,...A96174PC
See NS Package Number N16A

1-245

Absolute Maximum Ratings

Recommended Operating
Conditions

(Note 1)

If Military! Aerospace specified devices are required,
contact the National Semiconductor Sales Office!
Distributors for availability and specifications.
Storage Temperature Range
Ceramic DIP
- 65°C to + 175°C
Molded DIP
- 65°C to + 150°C
Operating Temperature Range
O°Cto + 70°C
Lead Temperature
Ceramic DIP (soldering, 60 sec.)
Molded DIP (soldering, 10 sec.)
Supply Voltage

Typ
5

Min
4.75

Supply Voltage (Vcd
Common Mode Output
Voltage (Vod

-7

Output Current HIGH (IOH)
Output Current LOW (Iod
Operating Temperature (TA)

300°C
265°C

25

0

Max
5.25

Units
V

+12
-60

rnA

60

rnA

70

°C

V

7V

Enable Input Voltage

5.5V

Maximum Power Dissipation *
25°C
Cavity Package
1500 mW
Molded Package
1040 mW
'Derate cavity package 10 mWI'C above 25'C; derate molded DIP package
8.3 mWI'C above 25'C.

Electrical Characteristics
over recommended temperature and supply voltage ranges, unless otherwise specified (Notes 2 and 3)

Symbol

Parameter

VIH

Input Voltage HIGH

VIL

Input Voltage LOW

VOH

Output Voltage HIGH

Conditions

Min

Typ

3.1

VOL

Output Voltage LOW

10L = 20 rnA

0.8

VIC

Input Clamp Voltage

11= -18 rnA

IVOD11

Differential Output Voltage

10 = 0 rnA

IVOD21

Differential Output Voltage

RL = 540., Figure 1a
RL = 1000., Figure 1b

Change in Magnitude of Differential
Output Voltage (Note 4)

Voc

Units
V

0.8
10H = -20mA

alVODI

Max

2

V
V
V

-1.5

V

6

V

1.5

2

V

2

2.3

V

RL = 540. or 1000., Figure 1b

±0.2

V

Common Mode Output Voltage (Note 5)

3

V

alvocl

Change in Magnitude of Common Mode
Output Voltage (Note 4)

±0.2

V

10

Output Current with Power Off

Vcc = OV, Vo = -7.0Vto 12V

±100

p,A

loz

High Impedance State Output Current

Vo = -7.0Vto 12V

±200

p,A

IIH

Input Current HIGH

VI = 2.7V

20

p,A

IlL

Input Current LOW

VI = 0.5V

-100

p,A

los

Short Circuit Output Current
(Note 6)

Vo = -7.0V

-250

Vo = OV

-150

±50

250

Vo = 12V
Icc

Supply Current (All Drivers)

No Load

1-246

rnA

150

Vo = Vcc

l
1 Output Disabled

Outputs Enabled

50

70

50

60

rnA

Switching Characteristics Vee =
Symbol

5V, T A = 25°C

Parameter

Conditions

too

Differential Output Delay Time

tTD

Differential Output Transition Time

tpLH

Propagation Delay Time,

RL

Min

= 60n, Figure 2
= 27n, Figure 3

RL

Low-to-High Level Output
Propagation Delay Time,

tpHL

High-to-Low Level Output

Typ

Max

Units

15

25

ns

15

25

ns

12

20

ns

12

20

ns

tpZH

Output Enable Time to High Level

RL

= 110n, Figure 4

30

45

ns

tPZL

Output Enable Time to Low Level

RL

= 110n, Figure 5

30

45

ns

tpHZ

Output Disable Time from High Level

RL

= 11 on, Figure 4

25

35

ns

tpLZ

Output Disable Time from Low Level

RL

= 11 on, Figure 5

30

45

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified min/max limits apply across the O'C to
Vee = SV and TA = 2S'C.

+ 70'C range for the DS96172/ /LA96172/DS96174//LA96174. All typicals are given for

Note 3: All currents into the device pins are positive; all currents out of the device pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 4: t:. IVaol and alvacl are the changes in magnitude of Vao and Vae respectively, that occur when the input is changed from a high level to a low level.
Note 5: In EIA Standards RS-422A and RS-485, Vae, which is the average of the two output voltages with respect to ground, is called output offset voltage, Vas.
Note 6: Only one output at a time should be shorted.

Parameter Measurement Information
~7sn

.t
VOO2
I

•

yyy

RL
Esn
yyy

--

ENABLED
(Note 3)

r--------.

I
I

I

GENERATOR
(Note 1)

.
:

son

--4

3V

-=--

I
I
I
I
I
I

I

--

.. --------~
ENABLED

CL

.I.

--

..L

CL

.I.
--

~oc
TL/F/9626-4

FIGURE 1a. Differential and Common Mode
Output Voltage

..L

I

I
I
I
I

~-

ENABLED
(Note 3)

TL/F/9626-3
FIGURE 1. Differential Output Voltage with
Varying Common Mode Voltage

RL

vl, :-z
I -z

-7Vto+12V

=t

RL
60n

or

IN

-{1.5V
tDO

=

CL 15 pF
(Note 2)

OUT

3V

IS},

W

50%

10%'')
tro-l

(Note 3)
TL/F/9626-5

FIGURE 2. Differential Output Delay and Transition Times

1-247

f-gO%

too

OV

I

:::2.SV

''"~

10% :::-2.SV

I+-

--to

tro
TL/F/9626-6

•

~
.....
..-

CD

Parameter Measurement Information

--+
2Y

2Y

2A

2A

28

28

GND

GND
TL/F/9627-2

TL/F/9627-1

Top View

Top View
Order Number DS96F173CJ, DS96F173MJ,
DS96F175CJ or DS96F175MJ
See NS Package Number J16A *
Order Number DS96F173CM or DS96F175CM
See NS Package Number M16A
Order Number DS96F173CN or DS96F175CN
See NS Package Number N16A
-For most current package information, contact product marketing.

1-250

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range
Ceramic DIP
Molded DIP and SO-16

Supply Voltage (Vce)
DS96F173C/DS96F175C
DS96F173M/DS96F175M

- 65°C to + 175°C
- 65°C to + 150°C

Lead Temperature
Ceramic DIP (Soldering, 60 sec.)
Molded DIP and SO-16 (Soldering, 10 sec.)
Maximum Power Dissipation· at 25°C
Cavity Package
Molded Package
SO Package
Supply Voltage

300°C
265°C
1500 mW
1040 mW
960mW
7.0V

Input Voltage, A or B Inputs

±25V

Differential Input Voltage

±25V

Enable Input Voltage

c
en
CD

Recommended Operating
Conditions

(Note 1)

m

"T1
-'"

Min

Typ

Max

4.75
4.50

5.0
5.0

5.25
5.50

Units

V

Common Mode
Input Voltage VCM

-7

+12

V

Differential Input Voltage
(Note 2) (VIO)

-7

+12

V

Output Current HIGH (lOH)

-400

p,A

Output Current LOW {lad

16

mA

70
125

°C

Operating Temperature (TA)
DS96F173C/DS96F175C
DS96F173M/DS96F175M

0
-55

25
25

7.0V

Parameter

Conditions

Differential-Input
High Threshold Voltage

Va = VOH

VTL

Differential-Input (Note 4)
Low Threshold Voltage

Va = VOL
VCM = OV

Min

VT+ - VT-

Hysteresis (Note 5)
Enable Input Voltage HIGH

VIL

Enable Input Voltage LOW

VIC

Enable Input Clamp Voltage

11= -18mA

VOH

Output Voltage HIGH

VIO = 200 mV

O°Cto +70°C

2.8

10H = -400 p,A

- 55°C to + 125°C

2.5

Output Voltage LOW

Typ

Max

Units

0.2

V
~

-0.2

VIH

VOL

102

High-Impedance State Output

Va = O.4V to 2.4V

II

Line Input Current (Note 6)

Other Input = OV

V
mV

50

V

2.0

VIO = -200 mV

0.8

V

-1.5

V
V

IOL = 8.0 mA

0.45

10L = 16 mA

0.50
±20
1.0

VI = 12V

V
p,A
mA

-0.8

VI = -7.0V
IIH

Enable Input Current HIGH

VIH = 2.7V

20

p,A

IlL

Enable Input Current LOW

VIL = O.4V

-100

p,A

RI

Input Resistance

los

Short Circuit Output Current

(Note 7)

Icc

Supply Current

No Load

14
-15

Iccx

1-251

m

-'"

Electrical Characteristics over recommended operating conditions, unless otherwise specified (Notes 2, 3)
Symbol

c
en
CD

"T1

Low Level Output Current
50mA
·Oerate cavity package 10 mwrc above 25'C; derate molded DIP package
8.3 mW/,C above 25'C; derate SO package 7.7 mW'C above 25'C.

VTH

-.....
(,,)

.......

18

22

k!l

-85

mA

Outputs Enabled

50

Outputs Disabled

50

mA

-.....
CJ1

II)

I'

.....

u..

Switching Characteristics Vee = 5.0V, TA = 25°C

CD

Q)

(J)

c
......
C")

Symbol

Parameter

Max

Units

5.0

15

22

ns

5.0

15

22

ns

Propagation Delay Time,
High to Low Level Output

tZH

Output Enable Time to High Level

CL

= 15 pF, Figure 2

12

16

ns

tZL

Output Enable Time to Low Level

CL

= 15 pF, Figure 3

13

18

ns

Q)

(J)

c

Typ

tpHL

.....

CD

Min

tpLH

I'

u..

Conditions
VID = - 2.5V to + 2.5V,
CL = 15 pF, Figure 1

Propagation Delay Time,
Low to High Level Output

tHZ

Output Disable Time from High Level

CL

= 5.0 pF, Figure 2

14

20

ns

tLZ

Output Disable Time from Low Level

CL

= 5.0 pF, Figure 3

14

18

ns

ItpLH-tpHLI

Pulse Width Distortion (SKEW)

Figure 1

1.0

3.0

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -55'C to + 125'C temperature range the DS96F173M/DS96F175M and across the Q'C to
+7Q'C range for the DS96F173C/DS96F175C. All typicals are given for Vee = 5V and T A = 25'C.
Note 3: All currents into the device pins are positive; all currents out of the device pins are negative. All voltages are reference to ground unless otherwise
specified.
Note 4: The algebraic convention, when the less positive (more negative) limit is designated minimum, is used in this data sheet for common mode input voltage
and threshold voltage levels only.
Note 5: Hysteresis is the difference between the positive·going input threshold voltage. Vr +, and the negative going input threshold voltage, Vr _.
Note 6: Refer to EIA Standards RS·485 for exact conditions.
Note 7: Only one output at a time should be shorted.

Function Tables
(Each Receiver) DS96F173
Differential Inputs

A-B
VID> 0.2V
VID

<

-0.2V

X
H =
L =
Z =
X =

Enables

(Each Receiver) DS96F175
Outputs

Differential Inputs

A-B

Enable

VID ~ 0.2V

H

E

E

V

H

X

X

L

H
H

H

X

X

L

L
L

L

H

Z

VID

~

-0.2V

X

High Level
Low Level
High Impedance (off)
Immaterial

1·252

Output

V
H

H

L

L

Z

c
en

Parameter Measurement Information

(Q
0')

"T1
-""

.......
W
.......
GENERATOR

>-.--+---OUT

c
en
(Q

2.5V

(Note t)

IN

\OV

0')

~t~-2.5V

"T1
-""

.......

U1

, - - - - " " " " \ : - - VOH
1.3V

OUT

TL/F/9627-3

TL/F/9627-4

FIGURE 1. tpLH. tpHL (Note 3)

IN

~'3V
t.3V
3V

Sl OPEN

tZH

OUT

tHZ

I

OV
Sl CLOSED

,-.--~LLVOH
1.3V

TL/F/9627-5

FIGURE 2. tHZ. tZH (Note 3)

Vee
IN

2kIl

~
1.3V

tZL

S2 OPEN

3V

1.3V

OV

tLl

S2 CLOSED

OUT

(Note 04)
TLlF/9627-8

TLIF19627-7

FIGURE 3. tZL. tLl (Note 3)
Note 1: The input pulse is supplied by a generator having the following characteristics: PRR = 1.0 MHz, 50% duty cycle, tr ,::; 6.0 ns, tf ,::; 6.0 ns, Zo =
Note 2: CL includes probe and stray capacitance.
Note 3: DS96F173 with active high and active low Enables is shown here. DS96F175 has active high Enable only.
Note 4: All diodes are 1N916 or equivalent.
Note 5: To test the active low Enable

E of DS96F173, ground E and apply an inverted input waveform to E.

1-253

DS96F175 has active high enable only.

son.

•

Lt)

I"

u:: Typical Application

m
CD

1/4 DS96Fl72

1/4DS96F174

c

r""oo.o---.......-~.-.----- - - - - - - - - - - -....- -....""T""---a,.......

....

........:;...........~H~--+----- - - - - - -

"('t)
I"

......---......

-----+-~~-t--4

U.
CD

0)

en
c
1/4DS96F173
1/4DS96Fl72

1/4DS96F173
1/4 DS96F175
1/4 DS96F173

1/4DS96F174

UP TO 32
DRIVER/RECEIVER
PAIRS
TLlF/9627-9

FIGURE 4
Note: The line length should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short as possible.

1-254

c

en

eo
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......

~National

~ Semiconductor

.......

CI)

"»

~

eo

DS96173/~A96173/DS96175/~A96175

en
......
.......

RS-485/RS-422 Quad Differential Line Receivers
General Description

Features

The OS96173/J.tA96173 and OS96175/J.tA96175 are high
speed quad differential line receivers designed to meet EIA
Standard RS-485. The devices have TRI-STATE® outputs
and are optimized for balanced multipoint data bus transmission at rates up to 10 Mbps. The receivers feature high
input impedance, input hysteresis for increased noise immunity, and input sensitivity of 200 mV over a common mode
input voltage range of -12V to + 12V. The receivers are
therefore suitable for multipoint applications in noisy environments. The OS961731 J.tA96173 features an active high
and active low Enable, common to all four receivers. The
OS961751 J.tA96175 features separate active high Enables
for each receiver pair. Compatible RS-485 drivers, transceivers, and repeaters are also offered to provide optimum
bus performance. The respective device types are
OS96172/J.tA96172,
OS96174/J.tA96174,
OS961761
J.tA96176, OS96177 1J.tA96177 and OS961781 J.tA96178.

•
•
•
•
•
•
•
•
•

CI)

c
"en

Meets EIA Standard RS-485, RS-422A, RS-423A
Oesigned for multipoint bus applications
TRI-STATE Outputs
Common mode input voltage range: - 7V to + 12V
Operates from single + 5V supply
Input sensitivity of ± 200 mV over common mode range
Input hysteresis of 50 mV typical
High input impedance
Fail-safe input/output features drive output HIGH when
input is open
• OS96173/J.tA96173/0S96175/J.tA96175 are lead and
function compatible with SN75173175175 or the
AM26LS32/MC3486 respectively.

Connection Diagrams
16-Lead DIP
DS96175/,...A96175

16-Lead DIP
DS961731 J.tA96173

lB~I-----.

lA

16 Vee
15

48

lY

El,2......;...-.. >--+
2Y
2A

2B-t-----'
GND 8
TL/F/9628-1

Order Number DS96173J, J.tA96173DC, DS96175J, J.tA96175DC
See NS Package Number J16A*
Order Number DS96173N, J.tA96173PC, DS96175N, J.tA96175PC
See NS Package Number N16A

'For most current package information, contact product marketing.

1-255

9 38
TLIF/9628-2

eo
en
......
.......
en

"»

~

eo

en
......
.......

en

Lt)

1'0
..-

CD

Q)

<::i.

.......
Lt)

1'0
..CD

Q)

en
c.......
('t)

1'0

..-

CD

Q)

Absolute Maximum Ratings

Storage Temperature Range
Ceramic DIP
Molded DIP

.......

1'0

..-

Supply Voltage

CD

Input Voltage, A or B Inputs
Differential Input Voltage

('t)

Q)

en
c

Supply Voltage (Vee>
Common Mode Input
Voltage (VCM)
Differential Input
Voltage (VIO)

-65°C to + 175°C
- 65°C to + 150°C

Lead Temperature
Ceramic DIP (soldering, 60 sec.)
Molded DIP (soldering, 10 sec.)
Maximum Power Dissipation· at 25°C
Cavity Package
Molded Package

<::i.

Recommended Operating
Conditions

(Note 1)

If Military!Aerospace specified devices are required,
contact the National Semiconductor Sales Office!
Distributors for availability and specifications.

300°C
265°C
1500 mW
1040mW

Min

Typ

Max

Units

4.75
-7

5

5.25

V

+12

V

-7

+12

V

Output Current High (IOH)

-400

Output Current LOW (Iou

16

Il A
mA

70

°C

Operating Temperature (TA)

0

25

7V
±25V
±25V

Enable Input Voltage

7V
Low Level Output Current
50mA
·Derate cavity package 10 mWrC above 25'C; derate molded DIP package
8.3 mW rc above 25'C.

Electrical Characteristics over recommended temperature, common mode input voltage, and supply voltage
ranges, unless otherwise specified (Notes 2 & 3)
Symbol

Parameter

Conditions

Min

VTH

Differential Input
High Threshold Voltage

Vo = 2.7V, 10 = - 0.4 mA

VTL

Differential Input (Note 4)
Low Threshold Voltage

Vo = 0.5V, 10 = 16 mA

VT+ - VT-

Hysteresis (Note 5)

VCM = OV

VIH

Enable Input Voltage HIGH

VIL

Enable Input Voltage LOW

VIC

Enable Input Clamp Voltage

II = -18mA

VOH

Output Voltage HIGH

VIO = 200 mY, 10H = -400 IlA

VOL

Output Voltage LOW

VIO = -200 mV

High Impedance State Output

Vo = O.4V to 2.4V

Line Input Current (Note 6)

Other Input = OV

Enable Input Current HIGH

IlL
RI

Input Resistance

los

Short Circuit Output Current

Units

0.2

V

-0.2

V
50

mV
V
0.8

102

Enable Input Current LOW

Max

2.0

II

IIH

Typ

I
I

V

2.7

V

10L = 8 mA

0.45

10L = 16mA

0.50
±20

I VI
I VI

V

-1.5

= 12V

1.0

= -7V

-O.B

V

Il A
mA

VIH = 2.7V

20

Il A

VIL = O.4V

-100

Il A

-85

mA

12
-15

(Note 7)

Supply Current

15

kfl

Outputs Disabled
75
mA
Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified MinIMax limits apply across the O'C to + 70'C range for the OS96173//LA96173/DS96175//LA96175. All typicals are given for
Vee = 5V and TA = 25'C.
Note 3: All currents into the device pins are positive; all currents out of the device pins are negative. All voltages are reference to ground unless otherwise
specified.
Note 4: The algebraic convention, when the less positive (more negative) limit is designated minimum, is used in this data sheet for common mode input voltage
and threshold voltage levels only.
Note 5: Hysteresis is the difference between the positive·going input threshold voltage, VT +, and the negative going input threshold voltage, VT-.
Note 6: Refer to EIA Standards RS·485 for exact conditions.
Note 7: Only one output at a time should be shorted.

Icc

Note 1: "Absolute Maximum

1-256

Switching Characteristics Vee =
Symbol

5V, TA = 25°C

Parameter

Conditions

Propagation Delay Time,

tpLH

Min

VIO = -2.5Vt02.5V,
CL = 15 pF, Figure 1

Low to High Level Output

Typ

Max

Units

15

25

ns

15

25

ns

22

ns

tpHL

Propagation Delay Time,
High to Low Level Output

tPZH

Output Enable Time to High Level

CL = 15 pF, Figure 2

15

tPZL

Output Enable Time to Low Level

CL = 15 pF, Figure 3

15

22

ns

tpHZ

Output Disable Time from High Level

CL = 5 pF, Figure 2

14

30

ns

tpLZ

Output Disable Time from Low Level

CL = 5 pF, Figure 3

24

40

ns

Function Tables
(Each Receiver) DS961731 JLA96173

Differential Inputs

A-B
VIO> 0.2V

VIO

<

-0.2V

X
=
L=
X=
Z =
H

(Each Receiver) DS961751JLA96175

Enables
E

E

Outputs

Differential Inputs

V

A-8

Enable

Output

Y

VIO;;:: 0.2V

H

H

H

X

H

X

L

H

VIO ~ -0.2V

H

L

X

L

Z

H

X

L

X

L

L

L

H

Z

High Level

Low Level
Immaterial
High Impedance (off)

,

1-257

Parameter Measurement Information

p------ .

2.5V

js-

IN

>-.......- ....--OUT

GENERATOR

OV

-2.5V

(Note I)

IpHLi

-----·--VOH
1.3V

OUT

TLIF/962S-4
TLIF/962S-3

FIGURE 1. tpLH. tpHL (Note 3)

.----~-",-_''-''''_-+_''''_'''''''I-",,_-o..--S1J2k.

IN

~'3V
1.3V
3V
OV

SI OPEN

PHtSI CLOSED

tpZH

_---..:LLvOH
OUT

1.3V
=1.4V

TL/F/962S-6

TL/F/962S-5

FIGURE 2. tpHZ. tpZH (Note 3)
VCC
IN

~'3V
1.3V
3V
OV
tpZL

tpLZ

S2 OPEN

S2 CLOSED
=UV

OUT

TL/F/962S-S

TL/F/962S-7

FIGURE 3. tpZL. tpLZ (Note 3)
Note 1: The input pulse is supplied by a generator having Ihe following characteristics: PRR = 1.0 MHz. 50% duty cycle, Ir

~

6.0 ns, tf ~ 6.0 ns, Zo

= 50n.

Note 2: CL includes probe and stray capacitance.
Note 3: DS96173/fLA96173 with active high and active low Enables is shown here. DS96175/fLA96175 has active high Enable only.
Note 4: All diodes are 1 N916 or equivalent.
Note 5: To test the active low Enable
Enable only.

E of DS96173/fLA96173,

ground E and apply an inverted input waveform to

1-258

E.

DS96175/fLA96175 has active high

Typical Application
1/4 DS96172/~A96172

1/4 DS96174/~A96174

1......0 - - -........- -.....- - - - - - - - - - - - - - - -......- -...--r---
DS96F177C/DS96F178C
DS96F177M/DS96F178M

-65°C to + 175°C
- 65°C to + 150°C

Lead Temperature
Ceramic DIP (Soldering, 60 sec.)
Molded DIP and SO-8 (Soldering, 10 sec.)
Maximum Power Dissipation* at 25°C
Cavity Package
Molded Package
SO Package

Typ

4.75
4.50

5.0 5.25
5.0 5.50

Voltage at Any Bus
Terminal (VI or VCM)
(Separately or Common Mode) -7.0

300°C
265°C

7.0V

Input Voltage
5.5V
'Derate cavity package 8.7 mwrc above 25'C; derate molded DIP package
7.5 mW/'C above 25'C; derate SO package 6.5 mwrc above 25'C.

Max

Units
V
V

12

V

±12

V

Output Current HIGH (IOH)
Driver
Receiver

-60
-400

mA

Output Current LOW (IoU
Driver
Receiver

60
16

mA

70
125

°C
°C

Differential Input Voltage(VID)
(Note 2)

1300 mW
930mW
810mW

Supply Voltage

Min

Operating Temperature (TA)
DS96F177C/DS96F178C
DS96F177M/DS96F178M

0
-55

25
25

J!A

Driver Electrical Characteristics
Over recommended operation conditions, unless otherwise specified (Notes 2 and 3)

Symbol
VIH

Parameter

Conditions

Input Voltage HIGH

Min

Typ

Max

2.0

VIL

Input Voltage LOW

VOH

Output Voltage HIGH

10H = -55 mA

VOL

Output Voltage LOW

10H = 55 mA

10°C to + 70°C

V
0.8

V

2.0

V

3.0

V

10°C to + 70°C

VIC

Input Clamp Voltage

II = -18mA

IVOD11

Differential Output Voltage

10 = 0 mA

IVOD21

Differential Output Voltage

RL = 100n Figure 1

2.0

2.25

RL = 54n Figure 1

1.5

2.0

1O°Cto +70°C

-1.3

V

6.0

V
V

IVOD31

Differential Output Voltage

VCM = -7.0Vto +12V

~IVODI

Change in Magnitude of Differential
Output Voltage (Note 4)

RL = 54n or 1oon, Figure 1

VOC

Common Mode Output Voltage (Note 5)

~Ivocl

Change in Magnitude of Common
Mode Output Voltage (Note 4)

10

Output Current with Power Off

VCC = OV, Vo = -7.0Vto +12V

loz

High Impedance State Output Current

Vo = -7.0Vto +12V

IIH

Input Current HIGH

VI = 2.4V

20

IlL

Input Current LOW

VI = O.4V

-50

los

Short Circuit Output Current
(Note 9)

Vo = -7.0V

-250

Vo = OV

-150

1Outputs Disabled

Iccx

1-268

±0.2

V

3.0

V

±0.2

V

±50

J!A
J!A
J!A
J!A

±100

mA

250

l Outputs Enabled

No Load

V

150

Vo = +12V
Supply Current (Total Package)

1.5

±20

Vo = VCC

Icc

Units

28
25

mA

Driver Switching Characteristics Vcc =
Symbol

Parameter

Conditions

too

Differential Output Delay Time

tTD

Differential Output Transition Time

tpLH

Propagation Delay Time
Low-to-High Level Output

c
en
CD

5.0V, TA = 25·C

RL = 60n, Figure 3
RL = 27n, Figure 4

0')

Min

Typ

Max

Units

8.0

15

20

ns

8.0

15

25

ns

6.0

12

16

ns

."
-4

......
......
.......

c
en
CD
0')

."

-4

tpHL

Propagation Delay Time,
High-to-Low Level Output

tZH

Output Enable Time to High Level

tZL

Output Enable Time to Low Level

tHZ

6.0

12

16

ns

RL = 110n, Figure 5

20

30

ns

RL = 11 on, Figure 6

25

35

ns

Output Disable Time from High Level

RL = 11 on, Figure 5

20

30

ns

tLZ

Output Disable Time from Low Level

RL = 11 on, Figure 6

20

30

ns

tSKEW

Driver Output to Output

RL = 60n

1.0

4.0

ns

......
CO

Receiver Electrical Characteristics
Over recommended operating conditions, unless otherwise specified
Symbol

Parameter

Conditions

VTH

Differential Input High Threshold Voltage

Va = 2.7V, 10 = -0.4 mA

VTL

Differential Input Low Threshold Voltage
(Note 6)

Va = 0.5V,10 = 8.0 mA
VCM = OV

Min

Typ

Max

Units

0.2

V

-0.2

V

VT+ -VT-

Hysteresis (Note 7)

VIH

Enable Input Voltage HIGH

VIL

Enable Input Voltage LOW

VIC

Enable Input Clamp Voltage

11= -18mA

VOH

High Level Output Voltage

VIO = 200 mV,
10H = - 400 J.LA,
Figure 2

O·Cto +70·C

2.8

- 55·C to + 125°C

2.5

VIO = -200 mV,
Figure 2

10L = 8.0 mA

0.45

10L = 16mA

0.50

Low Level Output Voltage

VOL

High-Impedance State Output

loz

35

mV

50

V

2.0
0.8

V

-1.3

V
V

Va = O.4V

-360

Va = 2.4V

20

V

J.LA

II

Line Input Current (Note 8)

Other Input = OV

IIH

Enable Input Current HIGH

VIH = 2.7V

20

IlL

Enable Input Current LOW

VIL = O.4V

-50

J.LA

RI

Input Resistance

22

kn

los

Short Circuit Output Current

(Note 9)

-85

mA

Icc

Supply Current (Total Package)

No Load

VI= +12V

1.0

VI = -7.0V

-0.8

14

Iccx

18

-15
Outputs Enable

28

Outputs Disabled

25

mA

J.LA

mA

Function Tables
DS96F177

DS96F178

Differential Inputs

Enable

A-8

E

T

Y

VIO ~ 0.2V

H

H

VIO::;: -0.2V

H

X

L

H = High Level
L = Low Level

Outputs

Differential Inputs

Enable

Z

A-8

E

T

Y

H

L

VIO ~ 0.2V

L

H

H

L

L

L

H

VIO::;: -0.2V

L

L

L

H

Z

Z

Z

X

H

Z

Z

Z

X = Immaterial
Z

= High Impedance (Off)

1-269

Outputs

Z

III

co
......

it

Receiver Switching Characteristics Vcc =

5.0V, T A = 25°C

CD

en

en

c
......
......
......
.....
u.
CD

Symbol

Parameter

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tZH

Output Enable Time to High Level

tZL

Output Enable Time to Low Level

tHZ

Output Disable Time from High Level

tLZ

Output Disable Time from Low Level

ItpLH - tpHLi

Pulse Width Distortion (SKEW)

en

en
c

Conditions

Min

Typ

Max

Units

VIO = OV to + 3.OV
CL = 15 pF, Figure 7

12

19

24

ns

10

16

22

ns

10

16

ns

12

18

ns

CL = 5.0 pF, Figure 8

12

25

ns

12

18

ns

Figure 7

1.0

4.0

ns

CL = 15 pF, Figure 8

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified MiniMax limits apply across the - 55'C to + 125'C temperature range for the DS96F177M/DS96F178M and across the O'C to
+ 70'C range for the DS96F177C/DS96F178C. All typicals are given for Vee = 5V and TA = 25'C.
Note 3: All currents into the device pins are positive; all currents out of the device pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 4: alvaDI and alvad are the changes in magnitude of VaD, Vae respectively, that occur when the input is changed from a high level to a low level.
Note 5: In EIA Standards RS·422A and RS·485, Vae, which is the average of the two output voltages with respect to ground, is called output offset voltage, Vas.
Note 6: The algebraic convention, when the less positive (more negative) limit is designated minimum, is used in this data sheet for common mode input voltage
and threshold voltage levels only.
Note 7: Hysteresis is the difference between the positive·going input threshold voltage, VT +, and the negative going input threshold voltage, VT-.
Note 8: Refer to EIA Standards RS·485 for exact conditions.
Note 9: Only one output at a time should be shorted.

Parameter Measurement Information

1
V

:~

.~

2

~

RL

OO2

I

ENABLED
(Note 3)

~

t

~-

Voe

2

-b
TLIF/9631-3

TL/F/9631-4

FIGURE 1. Driver VOD2 and Voe

GENERATOR
(Note 1)

. ~~i
:

50Il

--4

-==
-

ENABLED
(Note 3)

CL

1.-

FIGURE 2. Receiver VOH and VOL

.

RL

=

60Il

3V

i
or

IN

11.5V

--l

=

CL 15pF
(Note 2)

too t-

,.5V}.-OO-i-- OV
:::2'5V

OUT

50% 't'-90%
107."].

907.-'

10% :::-2.5V

TL/F/9631-5

-

FIGURE 3. Driver Differential Output Delay and Transition Times

1-270

~
50%

tTD
TLlF/9631-6

Parameter Measurement Information

c
en
CD

(Continued)

en

~---~.~---3V

IN

2.3V

'----OV

RL
""""""C:>--....-

....-

=27n
~----I\.-+---VOH

y
OUT

OUT

GENERATOR

'TI

...&.

.......
.......
"-

c
en
CD
en

'TI
...&.

.......

Q)

(Note 1)
ENABLED

(Note 3)

Z
OUT

TL/F/9631-7

'-------~-- VOL
TL/F/9631-8

FIGURE 4. Driver Propagation Times

OV or 3V

""""""C:>--....-

.....-

~1.5V

OUT

IN

tZH
GENERATOR

son

(Note I)

(Note 3)
OUT

TL/F/9631-10

TL/F/9631-9

FIGURE 5. Driver Enable and Disable Times (tzH. tHZ)
SV
RL
OV or 3V

GENERATOR

""""""CD--....-

son

(Note I)

....-

=loon
OUT

IN

OUT

(Note 3)

-1.::r '.V~::
~2.3V

~

----t

O.SV
VOL
TLIF/9631-12

TLIF/9631-11

FIGURE 6. Driver Enable and Disable Times (tZl. tlZ)
~---~------3V

GENERATOR

(Note I)

IN

son

-j1.SV

--J

tpLH

I.SV \ .

-J -i--

OV

t:"""H-L

,----"""'\.--VOH
I . S V - - - -....

OUT
VOL

ENABLED _ _ _ _ _ _....

TL/F/9631-14

(Note 3)
TL/F/9631-13

FIGURE 7. Receiver Propagation Delay Times

1-271

eo

r---------------------------------------------------------------------------------------------~

1'0

.....

U.

Parameter Measurement Information

(Continued)

CD

en

U)

1.5V

C
......

1'0
1'0

.....

U.

5k.o.

CD

en

U)

C

(Note 3)

GENERATOR

50.0.

(Note 1)

TL/F/9631-15

~3V

(DS96F177)=X
IN
(DS96FI78)

1.5V

OV

~
ZH

OM

SI to 1.5V
S2 OPEN

OUT

I~V

TLIF/9631-16

OUT

OV

~

) C 3V SI to 1.5V
1.5V
S2 CLOSED
......- - 0V S3 CLOSED

(DS96F177)=1
IN
1.5V
(DS96FI78)
----

__

SI to -1.5V
S2 CLOSED
S3 OPEN

=4.5V

1.5V

>C

(DS96FI77)~

!Zr
r-~""

1.5V

ZL

VOH

--OV

IN
(DS96F178)

~3V

(DS96FI77)=X
IN
(DS96FI78)

S3 CLOSED

VOL
TLIF/9631-17

3V
0v SI to -1.5V
S2 CLOSED
S3 CLOSED

tlZ

OUT

.-JrVOH
=1.3V
TL/F/9631-16

TL/F/9631-19

FIGURE 8. Receiver Enable and Disable Times
Note 1: The input pulse is supplied by a generator having the following characteristics: PRR
Note 2: CL includes probe and stray capacitance.
Note 3: DS96LF178 Enable is active low, DS96LF177 Enable is active high.
Note 4: All diodes are lN916 or equivalent.

1·272

= 1.0 MHz, duty cycle::::: 50%, tr

!S: 6.0 ns, tf !S: 6.0 ns, Zo

= 500.

c
en
CO

Typical Application

en

-n
.....
....,
....,

DS96F177
DS36F95

DS36F95

.......

c
en
CO

en

-n
.....
....,
Q:)

RT

RT

DS96F178

TL/F/9631-20

Notes:
The line length should be terminated at both ends in its characteristic impedance.
Stub lengths off the main line should be kept as short as possible.

FIGURE 9

•

1-273

........

~ ~National

~
....

....

U Semiconductor

~ DS96177/ JLA96177

~ RS-485/RS-422 Differential Bus Repeater
General Description

Features

The DS96177/j.tA96177 Differential Bus Repeater is a
monolithic integrated device designed for one-way data
communication on multipoint bus transmission lines. This
device is designed for balanced transmission bus line applications and meets EIA Standard RS-485 and RS-422A. The
device is designed to improve the performance of the data
communication over long bus lines. The DS961771
j.tA96177 is an active high Enable.

• Meets EIA Standard RS-422A and RS-485
• Designed for multipoint transmission on long bus lines
in noisy environments

The DS96177 1j.tA96177 features positive and negative current limiting and TRI-STATE® outputs for the receiver and
driver. The receiver features high input impedance, input
hysteresis for increased noise immunity, and input sensitivity of 200 mV over a common mode input voltage range of
-12V to + 12V. The driver features thermal shutdown for
protection from line fault conditions. Thermal shutdown is
designed to occur at a junction temperature of approximately 160°C. The driver is designed to drive current loads up to
60 mA maximum.

•
•
•
•
•
•
•
•
•
•

TRI-STATE outputs
Bus voltage range -7.0V to + 12V
Positive and negative current limiting
Driver output capability ± 60 mA max
Driver thermal shutdown protection
Receiver input high impedance
Receiver input sensitivity of ± 200 mV
Receiver input hysteresis of 50 mV typical
Operates from single 5.0V supply
Low power requirements

The DS96177/j.tA96177 is designed for optimum performance when used on transmission buses employing the
DS96172/j.tA96172 and DS96174/j.tA96174 differential line
drivers, DS961731 j.tA96173 and DS961751 j.tA96175 differential line receivers, or DS961761 j.tA96176 differential bus
transceivers.

Connection Diagram

Function Table
Differential Inputs

8-Lead Dual-In-Line Package

T

A} BUS
NP----rB
IN

E

GND

VIO
VIO

E

T

V

H

H

H

L

-0.2V

H

L

L

H

Z} BUS

"",_ _~_y

L

Z

Z

Z

~

~

X

OUT
TL/F/9644-1

Top View

H = High Level
L = Low Level
X = Immaterial
Z = High Impedance (off)

Order Number DS96177J, j.tA96177RC
See NS Package Number J08A *
Order Number DS96177N, j.tA96177TC
See NS Package Number N08E

"For most current package information, contact product marketing.

1-274

Outputs

0.2V

A-B

Vee

Enable

Z

Absolute Maximum Ratings

Recommended Operating
Conditions

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range
Ceramic DIP
Molded DIP

Supply Voltage (Vce)
Voltage at any Bus Terminal
(Separately or Common
Mode) (VI or VCM)
Differential Input Voltage
(VID)
Output Current HIGH (IOH)
Driver
Receiver
Output Current LOW (lod
Driver
Receiver
Operating Temperature (TA)

- 65°C to + 175°C
- 65°C to + 150°C

Lead Temperature
Ceramic DIP (Soldering, 60 sec.)
Molded DIP (Soldering, 10 sec.)
Maximum Power Dissipation" at 25°C
Cavity Package
Molded Package

300°C
265°C
1300 mW
930mW

Supply Voltage

7.0V

Input Voltage

5.5V

-Derate cavity package 8.7 mWrC above 2S'C; derate molded DIP package
7.5 mWrC above 2S'C.

Min
4.75

Max
5.25

Units
V

12

V

±12

V

-60
-400

mA

Ty!>
5.0

-7.0

60
16
70

25

0

Il A
rnA
°C

Electrical Characteristics Over recommended temperature, common mode input voltage, and supply voltage
ranges, unless otherwise specified (Notes 2 and 3)
DRIVER SECTION
Symbol

Parameter

Conditions

Min

Typ

VIH

Input Voltage HIGH

VIL

Input Voltage LOW

VIC

Input Clamp Voltage

11= -18mA

IVOD11
IVOD21

Differential Output Voltage

10 = OmA

Differential Output Voltage

RL = 100n, Figure 2

2.0

2.25

RL = 54n, Figure 1

1.5

2.0

~IVODI

Change in Magnitude of Differential
Output Voltage (Note 4)

VOC

~Ivocl

Max

RL

= 54n or 100n, Figure

V

1

0.8

V

-1.5

V

6.0

V
V

±O.2

V

Common Mode Output Voltage (Note 5)

3.0

V

Change in Magnitude of Common Mode
Output Voltage (Note 4)

±0.2

V

±100

Il A
Il A
Il A
Il A

= OV, Vo = -7.0Vto +12V

10

Output Current with Power Off

VCC

102

High Impedance State Output Current

Vo= -7.0Vto+12V

±50

±200

IIH

Input Current HIGH

VI = 2.7V

20

IlL

Input Current LOW

VI = 0.5V

-100

los

Short Circuit Output Current
(Note 9)

Vo = -7.0V

-250

= OV
Vo = VCC
Vo = 12V

-150

Supply Current

Icc

Units

2.0

Vo

250

I Outputs Enabled
I Outputs Disabled

No Load

mA

150
35

mA

40

RECEIVER SECTION
Symbol

Parameter

Conditions

Min

Typ

= 2.7V, 10 = -0.4 mA

VTH

Differential Input
High Threshold Voltage

Vo

VTL

Differential Input Low
Threshold Voltage (Note 6)

Vo = 0.5V, 10 = 8.0 mA

VT+ -VT-

Hysteresis (Note 7)

VCM = OV

VIH

Enable Input Voltage HIGH

VIL

Enable Input Voltage LOW

VIC

Enable Input Clamp Voltage

Max

Units

0.2

V

-0.2

V
mV

50

V

2.0

11= -18 mA

1-275

0.8

V

-1.5

V

III

Electrical Characteristics (Continued)
Over recommended temperature, common mode input voltage, and supply voltage ranges, unless otherwise specified
RECEIVER SECTION (Continued)
Symbol

Parameter

VOH

High Level Output Voltage

VOL

Low Level Output Voltage

Min

Conditions

High-Impedance State Output

Line Input Current (Note 8)

II

Max

2.7

:3

loz

Typ

Units

VIO = 200 mY, IOH = -400 }-tA, Figure
VIO = -200 mY,
Figure:3

I
I IOL

V

IOL = 8.0 mA

0045

= 16 mA

0.50

Vo = OAV

-360

Vo = 2.4V

20

Other Input = OV

I VI
I VI

1.0

= 12V

V

}-tA

mA

-0.8

= -7.0V

IIH

Enable Input Current HIGH

VIH = 2.7V

20

}-tA

IlL

Enable Input Current LOW

VIL = O.4V

-100

}-tA

RI

Input Resistance

los

Short Circuit Output Current

(Note 9)

-85

mA

lee

Supply Current (Total Package)

No Load

12

kn

15

-15

l Outputs Enabled

35

I Outputs Disabled
Drive Switching Characteristics Vee =

mA

40

5.0V, T A = 25°C

Typ

Max

Units

tDO

Differential Output Delay Time

RL = 60n, Figure 4

15

25

ns

tTD

Differential Output Transition Time

RL = 60n, Figure 4

15

25

ns

tpLH

Propagation Delay Time,
Low-to-High Level Output

RL = 27n, Figure 5

12

20

ns

tpHL

Propagation Delay Time,
High-to-Low Level Output

RL = 27n, Figure 5

12

20

ns

tPZH

Output Enable Time to High Level

RL = 110n, Figure 6

25

45

ns

tPZL

Output Enable Time to Low Level

RL = 11 on, Figure 7

25

40

ns

tpHZ

Output Disable Time from High Level

RL = 110n, Figure 6

20

25

ns

tpLZ

Output Disable Time from Low Level

RL = 11 on, Figure 7

29

35

ns

Symbol

Receiver Switching Characteristics Vee =
Symbol

Min

Conditions

Parameter

Parameter

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tPZH

Output Enable Time to High Level

tPZL

Output Enable Time to Low Level

tpHZ

Output Disable Time from High Level

tpLZ

Output Disable Time from Low Level

5.0V, T A = 25°C

Conditions
VIO = OV to 3.0V,
CL = 15 pF, Figure 8

CL = 15 pF, Figure 9

CL = 5.0 pF, Figure 9

1-276

Min

Typ

Max

Units

16

25

ns

16

25

ns

15

22

ns

15

22

ns

14

30

ns

24

40

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified MinIMax limits apply across the O'C to
TA = 2S·C.

+ 70'C range

for the DS96177I,..A96177. All Iypicals are given for Vee = SV and

Note 3: All currents into the device pins are positive; all currents out of the device pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 4: ~Ivool and ~Ivocl are the changes in magnitude of Voo, Voe respectively, that occur when the input is changed from a high level to a low level.
Note 5: In EIA Standards RS·422A and RS·48S, Voe. which is the average of the two output voltages with respect to ground, is called output offset voltage, Vos.
Note 6: The algebraic convention, when the less positive (more negative) limit is designated minimum, is used in this data sheet for common mode input voltage
and threshold voltage levels only.
Note 7: Hysteresis is the difference between the positive·going input threshold voltage, VT +, and the negative going input threshold veltage, VT _.
Note 8: Refer to EIA Standards RS·48S for exact conditions.
Note 9: Only one output at a time should be shorted.

Parameter Measurement Information
3750

-7V to +12V
3750

TL/F/9644-2

TLlF/9644-4

FIGURE 1. Driver VOD2 and Voe

FIGURE 2. Driver VOD2 with Varying
Common Mode Voltage

VI~{
OV
T6
1.
:r t l

oL

(+)
TL/F/9644-3

FIGURE 3. Receiver VOH and VOL

III

~--------,~-------3V

IN

GENERATOR

(Note 1)

-1'.::V

t.5V} ,...
oo-,--OV
~~--~~-i--::::2.5V

OUT
TL/F/9644-5
TLlF/9644-6

FIGURE 4. Driver Differential Output Delay and Transition Times
r-------~.~------3V

2.3V

RL

=27.n

IN

------OV

...........o--.--+--OUT
GENERATOR

(Note 1)

so.n

y

,-------~,~------VOH

OUT
ENABLED

(Note 3)
TLlF/9644-7

Z
OUT

r-

VOL
tpLH

~VOH

/I' ·2.3V

'--------1......:.....----- VOL
TLlF/9644-8

FIGURE 5. Drive Propagation Times

1-277

Parameter Measurement Information

(Continued)
,--------,--------3V

. . . . o-----.....

OV or 3V

-OUT

IN

!-1.SV

~~
(Note 3)

GENERATOR

50.0.

(Note 1)

OUT

TL/F/9644-9

TL/F/9644-10

FIGURE 6. Driver Enable and Disable Times (tpZH. tpHZ)
5V

RL

IN ~:~ l~Vlp-:

=100.0.

"""'-o(:>----+--OUT

OV or 3V

~2.3V

OUT

(Note 3)

GENERATOR

~ O.SV

"'-----'t VOL

50.0.

(Note 1)

TL/F/9644-12
TL/F/9644-11

FIGURE 7. Driver Enable and Disable Times (tpZL. tpLZ)
3V
IN

GENERATOR

-j-1.SV

(Note 1)
-

~

tpLH

I.SV\

~ ~'-H-L-I--OV
--------VOH

l.SV-----'

OUT
VOL

ENABLED - - - - - - - '

TLIF/9644-14

(Note 3)
TL/F/9644-13

FIGURE 8. Receiver Propagation Delay Times

1-278

Parameter Measurement Information

(Continued)

1.5V

GENERATOR
(Note 1)

TLIF/9644-15

IN

OUT

~

~ZH

~"
~PZH 1."f--

~

51 to 1.5V
52 OPEN
53 CL05ED

IN

VOH

1.5V

OUT

--OV

tm

to

~

TL/F/9644-16

3V

IN

FlY 51 -1.5V
~ ~v ='.5V;;;;~ED

~

VOL
TLIF/9644-17

51 to 1.5V
52 CL05ED
53 CL05ED

IN

OUT

OUT
TL/F/9644-18

TLIF/9644-19

FIGURE 9. Receiver Enable and Disable Times
Note 1: The input pulse is supplied by a generator having the following characteristics: PRR = 1.0 MHz, duty cycle::::: 50%, I,
Note 2: CL includes probe and stray capacitance.
Note 3: DS96178/fLA96178 Enable is active low, DS96177/fLA96177 Enable is active high.
Note 4: All diodes are lN916 or equivalent.

1-279

:0;;

6.0 ns, If

:0;;

6.0 ns, 20 = 50n.

•

Typical Application
DS96177 /}lA96177
OS96176/J'A96176

OS96176/}lA96176

RT

RT

OS96178/}lA96178

TLlF/9644-20

Notes:
The line length should be terminated at both ends in its characteristic impedance.
Stub lengths off the main line should be kept as short as possible.

FIGURE 10

1-280

~National

~ Semiconductor
MM78C29/MM88C29 Quad Single-Ended Line Driver
MM78C30/MM88C30 Dual Differential Line Driver
General Description
The MM78C30/MM88C30 is a dual differential line driver
that also performs the dual four-input NAND or dual four-input AND function. The absence of a clamp diode to Vee in
the input protection circuitry of the MM78C30/MM88C30 allows a CMOS user to interface systems operating at different voltage levels. Thus, a CMOS digital signal source can
operate at a Vee voltage greater than the Vee voltage of
the MM78C30 line driver. The differential output of the
MM78C30/MM88C30 eliminates ground-loop errors.

The MM78C29/MM88C29 is a non-inverting single-wire
transmission line driver. Since the output ON resistance is a
low 200 typ., the device can be used to drive lamps, relays,
solenoids, and clock lines, besides driving data lines.

Features
3V to 15V
0.45 Vee (typ.)
200 (typ.)

• Wide supply voltage range
• High noise immunity
• Low output ON resistance

Logic Diagrams
1/4 MM78C29/MM88C29
Vee

INPUT 0--+---4
OUTPUT

III

TL/F/590B-l

112 MM78C30/MM88C30
Vee
INPUT 1
INPUT 2
INPUT 3

AND
OUTPUT

INPUT 4

Vee

NAND
OUTPUT

TL/F/590B-2

1-281

Absolute Maximum Ratings

(Note 1)

If Military!Aerospace specified devices are required,
contact the National Semiconductor Sales Office!
Distributors for availability and specifications.
Voltage at Any Pin (Note 1)

-0.3V to Vee

+ 16V

Operating Temperature Range
MM78C29/MM78C30
MM88C29/MM88C30

- 55°C to + 125°C
- 40°C to + 85°C

Storage Temperature

- 65°C to

Power Dissipation (Po)
Dual-In-Line
Small Outline

3Vto 15V

Operating Vee Range

18V

Absolute Maximum Vee

+ 150°C

Average Current at Output
MM78C30/MM88C30
MM78C29/MM88C29

50mA
25mA

Maximum Junction Temperature, Tj

150°C

Lead Temperature
(Soldering, 10 seconds)

260°C

700mW
500mW

DC Electrical Characteristics MiniMax limits apply across temperature range unless otherwise noted
Symbol

Parameter

Min

Conditions

Typ

Max

Units

CMOS TO CMOS
VIN(1)

Logical "1" Input Voltage

Vee
Vee

=
=

5V
10V

VIN(O)

Logical "0" Input Voltage

Vee
Vee

=
=

5V
10V

IIN(1)

Logical "1" Input Current

Vee

=

15V, VIN

=

15V

IIN(O)

Logical "0" Input Current

Vee

=

15V, VIN

=

OV

Icc

Supply Current

Vee

=

V
V

3.5
8

0.005
-1

V
V

1

,..,A

100

mA

-0.005
0.05

5V

1.5
2

,..,A

OUTPUT DRIVE
ISOUReE

Output Source Current
MM78C29/MM78C30

MM88C29/MM88C30

MM78C29/MM88C29
MM78C30/MM88C30
ISINK

Output Sink Current
MM78C29/MM78C30

MM88C29!MM88C30

ISOUReE

Output Source Resistance
MM78C29/MM78C30

MM88C29/MM88C30

VOUT = Vee -1.6V.
Vee ~ 4.5V, Tj = 25°C
Tj = 125°C

-57
-32

-80
-50

mA
mA

VOUT = Vee - 1.6V.
Vee ~ 4.75V, Tj = 25°C
Tj = 85°C

-47
-32

-80
-60

mA
mA

-2

-20

mA

11
8

20
14

mA
mA

22
16

40
28

mA
mA

9.5
8

22
18

mA
mA

19
15.5

40
33

mA
mA

VOUT = Vee - 0.8V
Vee ~ 4.5V
VOUT = O.4V, Vee
Tj = 25°C
Tj = 125°C

=

VOUT = O.4V. Vee
Tj = 25°C
Tj = 1.25°C

=

VOUT = O.4V, Vee
Tj = 25°C
Tj = 85°C

=

VOUT = O.4V, Vee
Tj = 25°C
Tj = 125°C

=

4.5V.

10V.

4.75V.

10V.

VOUT = Vee - 1.6V.
Vee ~ 4.5V. Tj = 25°C
Tj = 125°C

20
32

28
50

n
n

VOUT = Vee - 1.6V.
Vee ~ 4.75V. Tj = 25°C
Tj = 85°C

20
27

34
50

n
n

1-282

DC Electrical Characteristics
MiniMax limits apply across temperature range, unless otherwise noted (Continued)
Symbol

Parameter

Conditions

Min

Typ

Max

Units

VOUT = OAV, Vee = 4.50V,
Tj = 25°C
Tj = 125°C

20
28

36
50

n
n

VOUT = OAV, Vee = 10V,
Tj = 25°C
Tj = 125°C

10
14

18
25

n
n

VOUT = OAV, Vee = 4.75V,
Tj = 25°C
Tj = 85°C

18
22

41
50

n
n

VOUT = OAV, Vee = 10V,
Tj = 25°C
Tj = 85°C

10
12

21
26

n
n

OUTPUT DRIVE (Continued)
ISINK

Output Sink Resistance
MM78C29/MM78C30

MM88C29/MM88C30

Output Resistance
Temperature Coefficient
Source
Sink
(JJA

0.55
0040

%rC
%rC

Thermal Resistance
MM78C29/MM78C30
(D-Package)

100

°C/W

MM88C29/MM88C30
(N-Package)

150

°C/W

AC Electrical Characteristics * TA =
Symbol
tpd

Parameter
Propagation Delay Time to
Logical "1" or "0"
MM78C29/MM88C29
MM78C30/MM88C30

tpd

CIN

CPO

Differential Propagation Delay
Time to Logical "1" or "0"
MM78C30/MM88C30

25°C, CL = 50 pF
Typ

Max

Units

(See Figure 2)
Vee = 5V
Vee = 10V

80
35

200
100

ns
ns

Vee = 5V
Vee = 10V

110
50

350
150

ns
ns

400
150

ns
ns

Conditions

Min

RL = 100n, CL = 5000 pF
(See Figure 1)
Vee = 5V
Vee = 10V

Input Capacitance
MM78C29/MM88C29
MM78C30/MM88C30

(Note 3)
(Note 3)

5.0
5.0

pF
pF

Power Dissipation Capacitance
MM78C29/MM88C29
MM78C30/MM88C30

(Note 3)
(Note 3)

150
200

pF
pF

•AC Parameters are guaranteed by DC correlated testing.
"Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CPO determines the no load AC power consumption of any CMOS device. For complete explanation see 54C17 4C Family Characteristics application note
AN-gO.
Note 1:

1-283

III

oC")

oco
co

Connection Diagrams

:E
:E
.......
oC")

Dual-In-Line Package
MM78C29/MM88C29
NC

Vee

o

co

.....

NC

IN"
13

114

12

OUT"
10

111

1

:E
:E
.......

Dual-ln-L1ne Package
MM78C30/MM88C30
BAND
OUT

B NAND
OUT

9

8

8

9

13

1'4

11

12

10

Q)

N

o
co
co

:E
:E
.......

-

-

-

-

Q)

N

oco
.....

:E
:E
1

4

2

5

6

17

/3

2

1

3

4

5

6
/7

NC

NC

OUT 1

A AND
OUT

GND
TL/F/5908-3

A NAND
OUT

GND
TL/F/5908-4

Top View

Top View

Order Number MM78C29* or MM88C29*

Order Number MM78C30J* or MM88C30J*

• Please look into Section 8, Appendix 0 for availability of various package types.

Typical Performance Characteristics

g

~

z
0

~
~

MM78C29/MM88C29
Typical Propagation Delay vs
125 Load Capacitance
~
f- T = 25°c
J
115 f- Vee=5V

~~

105

~

95
85

75

ih

~

1'/

+

55

0

45

1=

40

~

35

VI _

,V
V

30

c- tpdl

200

400

600

800

0

65

z

~
~

70

V

50

t:.7
VI
TpdO ~

L~

130

0

120

~

100

z

/'"
V

~

600

400

800

LOAD CAPACITANCE,

Ct. (pF)

1000

'"..,..

tpdO

"

-

200

600

400

800

1000

LOAD CAPACITANCE, CL (pF)

Typical Source Current vs
Output Voltage
500

~~

1-1-

j

Vce =10V,_f-

~

,

Vee = 5V

4

I-

tr' , '._

Vee = 10V_

II'
II'

Vec=5V

I I I

100

... ~I-

2

,

300

~ 200

"

~'7

o

r- TJ = 25°C - r-r- Vee = I % -

1 400

/,

o
800

........

./

"

1000

Vee=15V

"

1/
J ~

100

600

I

I

'1
~

. '"
400

TJ =25OC

_0

1/"

I
lA"

600

~ 200

/

200

..,
VI,.'
/V
:/

110

Typical Sink Current vs
Output Voltage

~ 300

""...

V

./

60

55

~

500

85

~

::;:; ; 7

LOAD CAPACITANCE, CL (pF)

90

75

~

I

tpdl"

150
5140

~v

V

200

MM78C30/MM88C30
Typical Propagation Delay vs
Load Capacitance

80

~ I--

90

1000

LOAD CAPACITANCE, CL (pF)

]:

.1..;17"

tpdO

I

V

tpdl

I--

/

50

t!i

~

)'/

60

~

z

tpd~ V

TJ =25OC
Vce= 10V

65

g

~

MM78C30/MM88C30
Typical Propagation Delay vs
160 Load Capacitance

MM78C29/MM88C29
Typical Propagation Delay vs
70 Load Capacitance

6

oJ
8

10

TYPICAL VOUT (V)

12

14

o

2

4

I

I I

6

8

10

12

14

lYPICAL VCC-VOUT (V)
TLIF/5908-5

1-284

AC Test Circuits
Vee
14

VA

VIN

AND OUTPUT

5
100
12 t.lt.l78C30
VA-VB
50000 pF'

4

TL/F/5908-7

VB
NAND OUTPUT

TL/F/5906-6
FIGURE 1

Vee

Vee

14

14
AND
OUTPUT

5

12 t.lt.l78C30

I

CL

2

1/4 t.lt.l78C29

~--4"--O

I

7

OUTPUT

CL

TLIF/5906-9

TLIF/5908-6
FIGURE 2

Typical Applications
Digital Data Transmission
Cl
0.01 J'F'
(NOTE 1)
Vee
LINE DRIVER AND RECEIVER (NOTE 3)
14

AND
OUTPUT

1/2 t.lt.l78C30/
t.lt.l88C30

>---0 OUTPUT

.....----r------'
7

NAND
OUTPUT
STROBE

Note 1: Exact value depends on line length.
Note 2: Optional to control response time.
Note 3: Vee to 4.5V to 5.5V for the D57820.

1-285

TLIF/5906-10

oC")

oco
co

Typical Applications

:e
:e

(Continued)

Vee
Vee

14

o
""

AND
OUTPUT

C")

oco
......
:e
:e

1/2 MM78C30/
MMB8C30

>-'-'--0 OUTPUT

""
0)

C\I

oco
co

L..-_-"""T"--_..I

NAND
OUTPUT

:e
:e

TLIF/590B-ll

""
0)

C\I

o
co

Vee

......

:e
:e

14

INPUT

1/6 MM78C30/

Vec

SINGLE-WAVE TRANSMISSION LINE (NOTE 1)

OUTPUT

0--0 OUTPUT

MM88C30

TL/F/590B-12
Note 1: Vee is 3V to 15V

Typical Data Rate vs Transmission Line Length
104
TA - 250(;
N

::J:
..>t.

103

~
~

102

-'
-<
u

~

IV.

I

Cc~s~~§

~C~!

"'"'"
V.
Oy
- CC~ IS y ~~

101

103
LENGTH OF TRANSMISSION LINE (FT)

TLIF/5908-13

Note 1: The transmission line used was #22 gauge unshielded twisted pair (40k
termination).

Note 2: The curves generated assume that both drivers are driving equal lines,
and that the maximum power is 500 mW/package.

1-286

National Semiconductor
Application Note 22

Integrated Circuits for
Digital Data Transmission
INTRODUCTION

It is frequently necessary to transmit digital data in a highnoise environment where ordinary integrated logic circuits
cannot be used because they do not have sufficient noise
immunity. One solution to this problem, of course, is to use
high-noise-immunity logic. In many cases, this approach
would require worst case logic swings of 30V, requiring high
power-supply voltages. Further, considerable power would
be needed to transmit these voltage levels at high speed.
This is especially true if the lines must be terminated to
eliminate reflections, since practical transmission lines have
a low characteristic impedance.
A much better solution is to convert the ground referred
digital data at the transmission end into a differential signal
and transmit this down a balanced, twisted-pair line. At the
receiving end, any induced noise, or voltage due to groundloop currents, appears equally on both ends of the twistedpair line. Hence, a receiver which responds only to the differential signal from the line will reject the undesired signals
even with moderate voltage swings from the transmitter.

Figure f illustrates this situation more clearly. When ground
is used as a signal return as in Figure fa, the voltage seen
at the receiving end will be the output voltage of the transmitter plus any noise voltage induced in the signal line.

Hence, the noise immunity of the transmitter-receiver combination must be equal to the maximum expected noise
from both sources.
The differential transmission scheme diagrammed in Figure
fb solves this problem. Any ground noise or voltage induced on the transmission lines will appear equally on both
inputs of the receiver. The receiver responds only to the
differential signal coming out of the twisted-pair line and delivers a single-ended output signal referred to the ground at
the receiving end. Therefore, extremely high noise immunities are not needed; and the transmitter and receiver can be
operated from the same supplies as standard integrated
logic circuits.
This article describes the operation and use of a line driver
and line receiver for transmission systems using twisted-pair
lines. The transmitter provides a buffered differential output
from a DTL or TTL input signal. A four-input gate is included
on the input so that the circuit can also perform logic. The
receiver detects a zero crossing in the differential input voltage and can directly drive DTL or TTL integrated circuits at
the receiving end. It also has strobe capability to blank out
unwanted input signals. Both the transmitter and the receiver incorporate two independent units on a single silicon
chip.

DATA
INPUT

DATA
OUTPUT

a. Single-Ended System

TL/FI7188-1

INDUCED
NOISE
DATA
OUTPUT

DATA
INPUT

~----------------~~.\----------------tI
GROUND A

GROUND
NOISE

GROUND B
TL/F17188-2

b. Difference System

FIGURE 1. Comparing Differential and Single-Ended Data Transmission

1-287

.

N
N

Z

«

r---------------------------------------------------------------------------~

LINE DRIVER

010 and 011 will be turned off; and the output will be in a
high state. When all the emitters of 09 are at a one logic
level, 010 receives base drive from R8 through the forward
biased collector-base junction of 09. This saturates 010
and also 011, giving a low output state. The input voltage at
which the transition occurs is equal to the sum of the emitter-base turn on voltages of 010 and 011 minus the saturation voltage of 09. This is about 1.4V at 25°C.

Figure 2 shows a schematic diagram of the line transmitter.
The circuit has a marked resemblance to a standard TTL
buffer. In fact, it is possible to use a standard dual buffer as
a transmitter. However, the 057830 incorporates additional
features. For one, the output is current limited to protect the
driver from accidental shorts in the transmission lines. Secondly, diodes on the output clamp sever voltage transients
that may be induced into the transmission lines. Finally, the
circuit has internal inversion to produce a differential output
signal, reducing the skew between the outputs and making
the output state independent of loading.

A standard "totem-pole" arrangement is used on the output
stage. When the output is switched to the high state, with
010 and 011 cut off, current is supplied to the load by 013
and 014 which are connected in a modified Darlington configuration. Because of the high compound current gain of
these transistors, the output resistance is quite low and a
large load current can be supplied. R10 is included across
the emitter-base junction of 013 both to drain off any collector-base leakage current in 013 and to discharge the collector-base capacitance of 013 when the output is switched to

As can be seen from the upper half of Figure 2, a quadrupleemitter input transistor, 09, provides four logic inputs to the
transmitter. This transistor drives the inverter stage formed
by 010 and 011 to give a NAND output. A low state logic
input on any of the emitters of 09 will cause the base drive
to be removed from 010, since 09 will be saturated by current from R8, holding the base of 010 near ground. Hence,

r-----------~

__

~.---~.-~---y+

01

NAND
OUTPUT

07

A
04

-

-

'::"

'::"

y+

03

-

06

02
'::"
0
01

AND

-

OUTPUT

OS

TLlF17188-3

FIGURE 2. Schematic Diagram of the 057830 Line Driver
1-288

the low state. In the high state, the output level is approximately two diode drops below the positive supply, or roughly
3.6V at 25°C with a 5.0V supply.

The AND output is similarly protected by R6 and 05, which
limits the maximum output current to about 100 mA, preventing damage to the circuit from shorts between the outputs and ground.

With the output switched into the low state, 010 saturates,
holding the base of 014 about one diode drop above
ground. This cuts off 013. Further, both the base current
and the collector current of 010 are driven into the base of
011 saturating it and giving a low-state output of about
0.1 V. The circuit is designed so that the base of 011 is
supplied 6 mA, so the collector can drive considerable load
current before it is pulled out of saturation.

The current limiting transistors also serve to increase the
low state output current capability under severe transient
conditions. For example, when the current into the NAND
output becomes so high as to pull 011 out of saturation, the
output voltage will rise to two diode drops above ground. At
this voltage, the collector-base junction of 012 becomes
forward biased and supplies additional base drive to 011
through 010 which is saturated. This minimizes any further
increase in output voltage.

The primary purpose of R12 is to provide current to remove
the stored charge in 011 and charge its collector-base capacitance when the circuit is switched to the high state. Its
value is also made less than R9 to prevent supply current
transients which might otherwise occur' when the power
supply is coming up to voltage.

When either of the outputs are in the high state, they can
drive a large current towards ground without a significant
change in output voltage. However, noise induced on the
transmission line which tries to drive the output positive will
cut it off since it cannot sink current in this state. For this
reason, 06 and 08 are included to clamp the output and
keep it from being driven much above the supply voltage, as
this could damage the circuit.

The lower half of the transmitter in Figure 2 is identical to
the upper, except that an inverter stage has been added.
This is needed so that an input signal which drives the output of the upper half positive will drive the lower half negative, and vice versa, producing a differential output signal.
Transistors 02 and 03 produce the inversion. Even though
the current gain is not necessarily needed, the modified Darlington connection is used to produce the proper logic transition voltage on the input of the transmitter. Because of the
low load capacitance that the inverter sees when it is completely within the integrated circuit, it is extremely fast, with
a typical delay of 3 ns. This minimizes the skew between the
outputs.

When the output is in a low state, it can sink a lot of current
to clamp positive-going induced voltages on the transmission line. However, it cannot source enough current to eliminate negative-going transients so 05 and D7 are included to
clamp those voltages to ground.
It is interesting to note that the voltage swing produced on
one of the outputs when the clamp diodes go into conduction actually increases the differential noise immunity. For
example with no induced common mode current, the lowstate output will be a saturation voltage above ground while
the high output will be two diode drops below the positive
supply voltage. With positive-going common mode noise on
the line, the low output remains in saturation; and the high
output is clamped at a diode drop above the positive supply.
Hence, in this case, the common mode noise increases the
differential swing by three diode drops.

One of the schemes used when dual buffers are employed
as a differential line driver is to obtain the NAND output in
the normal fashion and provide the AND output by connecting the input of the second buffer to the NAND output. Using
an internal inverter has some distinct advantages over this:
for one, capacitive loads which slow down the response of
the NAND output will not introduce a time skew between the
two outputs; secondly, line transients on the NAND output
will not cause an unwanted change of state on the AND
output.
Clamp diodes, 01 through 04, are added on all inputs to
clamp undershoot. This undershoot and ringing can occur in
TIL systems because the rise and fall times are extremely
short.
Output-current limiting is provided by adding a resistor and
transistor to each of the complementary outputs. Referring
again to Figure 2, when the current on the NAND output
increases to a value where the voltage drop across R11 is
sufficient to turn on 012, the short circuit protection comes
into effect. This happens because further increases in output current flow into the base of 012 causing it to remove
base drive from 014 and, therefore, 013. Any substantial
increase in output current will then cause the output voltage
to collapse to zero. Since the magnitude of the short circuit
depends on the emitter base turn-on voltage of 012, this
current has a negative temperature coefficient. As the chip
temperature increases from power dissipation, the available
short circuit current is reduced. The current limiting also
serves to control the current transient that occurs when the
output is going through a transition with both 011 and 013
turned on.

1

I---t--t--t+-----il--+~t--;
I

o L...--"---"""'---_......l---.........l--'
o

25

50

15

100

125

150

OUTPUT SOURCE CURRENT (rnA)
TLlF17188-4

FIGURE 3. High State Output Voltage
as a Function of Output Current
Having explained the operation of the line driver, it is appropriate to look at the performance in more detail. Figure 3
shows the high-state output characteristics under load.
Over the normal range of output currents, the output resistance is about 10n.. With higher output currents, the short
circuit protection is activated, causing the output voltage to
drop to zero. As can be seen from the figure, the short-circuit current decreases at higher temperatures to minimize
the possibility of over-heating the integrated circuit.

*J. Kalb, "Design Considerations for a TIL Gate", National Semiconductor
TP-6, May, 1968.

1-289

.z r---------------------------------------------------------------------------------------I
~

~

«

V+ = 5V

V

-55°C

I

~V

25°C

V""

I
J
~

lb::cI
25

50

75

100

125

150

OUTPUT CU RRENT (rnA)

OUTPUT SINK CURRENT (rnA)

TLlF17188-6

TL/F17188-5

FIGURE 5. Differential Output Voltage as a
Function of Differential Output Current

FIGURE 4. low-State Output Current as a
Function of Output Current
Figure 4 is a similar graph of the low-state output characteristics. Here, the output resistance is about 5n with normal
values of output current. With larger currents, the output
transistor is pulled out of saturation; and the output voltage
increases. This is more pronounced at -55°C where the
transistor current gain is the lowest. However, when the output voltage rises about two diode drops above ground, the
collector-base junction of the current-limit transistor becomes forward biased, providing additional base drive for
the output transistor. This roughly doubles the current available for clamping positive common-mode transients on the
twisted-pair line. It is interesting to note that even though
the output level increases to about 2V under this condition,
the differential noise immunity does not suffer because the
high-state output also increases by about 3V with positive
going common-mode transients.

150

~
~

z

c
i=
~

125
100
75

~

C
a:

50

f

25

I

II

~

1....

f--

~I-~~I- ,':'~J

1I

~

~

c..001

/

c..""

~~

WJ
~

~

V
ONE SIDE

r=1 1115

0.1

1.0

10

100

SWITCHING FREQUENCY (MHz)
TLlF17188-7

FIGURE 6. Power Dissipation as a
Function of Switching Frequency

It is clear from the figure that the low state output current is
not effectively limited. Therefore, the device can be damaged by shorts between the output and the 5V supply. However, protection against shorts between outputs or from the
outputs to ground is provided by limiting the high-state current.
The curves in Figures 3 and 4 demonstrate the performance
of the line driver with large, capacitively-coupled commonmode transients, or under gross overload conditions. Figure
5 shows the ability of the circuit to drive a differential load:
that is, the transmission line. It can be seen that for output
currents less than 35 mA, the output resistance is approximately 15n. At both temperature extremes, the output falls
off at high currents. At high temperatures, this is caused by
current limiting of the high output state. At low temperatures, the fall off of current gain in the low-state output transistor produces this result.

power dissipation at high frequencies must be added to the
excess power dissipation caused by the load to determine
the total package dissipation. Second, and more important,
it is a measure of the "glitch" current which flows from the
positive supply to ground through the output transistors
when the circuit is going through a transition. If the output
stage is not properly designed, the current spikes in the
power supplies can become quite large; and the power dissipation can increase by as much as a factor of five between 100 kHz and 10 MHz. The figure shows that, with no
capacitive loading, the power increases with frequencies as
high as 10 MHz is almost negligible. However, with large
capacitive loads, more power is required.
The line receiver is designed to detect a zero crossing in the
differential output of the line driver. Therefore, the propagation time of the driver is measured as the time difference
between the application of a step input and the point where
the differential output voltage crosses zero. A plot of the
propagation time over temperature is shown in Figure 7.
This delay is added directly to the propagation time of the
transmission line and the delay of the line receiver to determine the total data-propagation time. However, in most cases, the delay of the driver is small, even by comparison to
the uncertainties in the other delays.

Load lines have been included on the figure to show the
differential output with various load resistances. The output
swing can be read off from the intersection of the output
characteristic with the load line. The figure shows that the
driver can easily handle load resistances greater than 100n.
This is more than adequate for practical, twisted-pair lines.
Figure 6 shows the no load power dissipation, for one-half
of the dual line driver, as a function of frequency. This information is important for two reasons. First, the increase in

1-290

Normally this would not be too difficult a task because of the
large signal swings involved. However, it was considered
important that the receiver operate from the + 5V logic supply without requiring additional supply voltages, as do most
other line receiver designs. This complicates the situation
because the receive must operate with ± 15V input signals
which are considerably greater than the operating supply
voltage.

25
V+·5V

20

]
~

i=
z
c
i=

"'
~

c.:I

15

~

,

~
t..,.....o

10

g:

o
0

25

50

N
N

The large common mode range over which the circuit must
work can be reduced with an attenuator on the input of the
receiver. In this design, the input signal is attenuated by a
factor of 30. Hence, the ± 15V common mode voltage is
reduced to ± 0.5V, which can be handed easily by circuitry
operating from a 5V supply. However, the differential input
signal, which can go down as low as ±2.4V in the worst
case, is also reduced to ± BO mY. Hence, it is necessary to
employ a fairly accurate zero crossing detector in the receiver.

C

-75 -50 -25

»
z

75 100 125

TEMPERATURE (OCI
TLlFI71BB-B

FIGURE 7. Propagation Time as a
Function of Temperature
To summarize the characteristics of the OS7830 line driver,
the input interfaces directly with standard TTL circuits. It
presents a load which is equivalent to a fan out of 3 to the
circuit driving it, and it operates from the 5.0V, ± 10% logic
supplies. The output can drive low impedance lines down to
50n and capacitive loads up to 5000 pF. The time skew
between the outputs is minimized to reduce radiation from
the twisted-pair lines, and the circuit is designed to clamp
common mode transients coupled into the line. Short circuit
protection is also provided. The integrated circuit consists of
two independent drivers fabricated on a 41 x 53 mil-square
die using the standard TTL process. A photomicrograph of
the chip is shown in Figure 8.

System requirements dictated that the threshold inaccuracy
introduced by the zero crossing detector be less than
17 mY. In principle, this accuracy requirement should not
pose insurmountable problems because it is a simple matter
to make well matched parts in an integrated circuit.
Figure 9 shows a simplified schematic diagram of the circuit
configuration used for the line receiver. The input signal is
attenuated by the resistive dividers R 1-R2 and RB-R3. This
attenuated signal is fed into a balanced DC amplifier, operating in the common base configuration. This input amplifier,
consisting of 01 and 02, removes the common mode component of the input signal. Further, it delivers an output signal at the collector of 02, which is nearly equal in amplitude
to the original differential input signal. this output signal is
buffered by 06 and drives an output amplifier, OB. The output stage drives the logic load directly.
An understanding of the circuit can be obtained by first considering the input stage. Assuming high current gains and
neglecting the voltage drop across R3, the collector current
of 01 will be:
I
- V+ - VSE1 - VSE3 - VSE4
C1 R11

(1)

With equal emitter-base voltages for all transistors, this becomes:
I
_ V+ - 3VSE
C1 R11

(2)

The output voltage at the collector of 02 will be:
VC2 = V+ - IC2R12

(3)

When the differential input voltage to the receiver is zero,
the voltages presented to the emitters of Q1and 02 will be
equal. If 01 and 02 are matched devices, which is easy to
arrange when they are fabricated close together on a single
silicon chip, their collector currents will be equal with zero
input voltage. Hence, the output voltage from 02 can be
determined by substituting (2) into (3):

TL/FI71B8-9

FIGURE 8_ Photomicrograph of the
DS7830 Dual Line Driver
LINE RECEIVER
As mentioned previously, the function of the line receiver is
to convert the differential output signal of the line driver into
a single ended, ground-referred signal to drive standard digital circuits on the receiving end. At the same time it must
reject the common mode and induced noise on the transmission line.

VC2 = V
For R11

+

-

R'R12
11 (V +

R12, this becomes:
VC2 = 3VSE

1-291

- 3VSE)

(4)

•

.

N
N

r-------__~------~------~t_------~---v+

Z

«

OUTPUT

RS
5K

~----------------+_------~------_4._--GROUNO

INVE~:~~~

R1
5K
_ _~"",,_.........______________.....
TL/F 17168-10

FIGURE 9. Simplified Schematic of the Line Receiver
The voltage on the base of 06 will likewise be 3VSE when
the output is on the verge of switching from a zero to a one
state. A differential input signal which causes 02 to conduct
more heavily will then make the output go high, while an
input signal in the opposite direction will cause the output to
saturate.

mode range. To compensate for this, a separate divider, R9
and R10, is used to maintain a constant collector current in
01 with varying common mode signals. With an increasing
common mode voltage on the non-inverting input, the voltage on the emitter of 01 will increase. Normally, this would
cause the voltage across R11 to decrease, reducing the
collector current of 01. However, the increasing common
mode signal also drives the top end of R 11 through R9 and
R10 so as to hold the voltage drop across R11 constant.

It should be noted that the balance of this circuit is not affected by absolute values of components-only by how well
they match. Nor is it affected by variations in the positive
supply voltage, so it will perform well with standard logic
supply voltages between 4.5V and 5.5V. In addition, component values are chosen so that the collector currents of 04
and 06 are equal. As a result, the base currents of 04 and
06 do not upset the balance of the input stage. This means
that circuit performance is not greatly affected by production
or temperature variations in transistor current gain.

In addition to improving the common mode rejection, R9
also forces the output of the receiver into the high state
when nothing is connected to the input lines. This means
that the output will be in a pre-determined state when the
transmission cables are disconnected.
A diode connected transistor, 05, is also added in the complete circuit to provide strobe capability. With a logic zero on
the strobe terminal, the output will be high no matter what
the input signal is. With the strobe, the receiver can be
made immune to any noise signals during intervals where
no digital information is expected. The output state with the
strobe on is also the same as the output state with the input
terminals open.

A complete schematic of the line receiver, shown in Figure
10, shows several refinements of the basic circuit which are
needed to secure proper operation under all conditions. For
one, the explanation of the simplified circuit ignores the fact
that the collector current of 01 will be affected by common
mode voltage developed across R3. This can give a O.5V
threshold error at the extremes of the ± 15V common

1-292

RESPONSE·TlME
CONTROL

r-----------~~--_I~------+_--~----------~I_----~------------ v+

R15
320
. .----~---------- OUTPUT

TERMINATION

R4
lk

RS
lk

R14

150

RJ
161

~----------~--------+---------"~--~~------------------GROUND

Rl
Sk

R2
161

DM7820 dual line receiver (one side).

STROBE
TL/F17188-11

FIGURE 10. Complete Schematic of One Half of the 057820 Line Receiver
The collector of Q2 is brought out so that an external capacitor can be used to slow down the receiver to where it will
not respond to fast noise spikes. This capacitor, which is
connected between the response-time-control terminal and
ground, does not give exactly-symmetrical delays. The delay for input signals which produce a positive-going output
will be less than for input signals of opposite polarity. This
happens because the impedance on the collector of Q2
drops as Q6 goes into saturation, reducing the effectiveness
of the capacitor.
Another difference in the complete circuit is that the output
stage is improved both to provide more gain and to reduce
the output resistance in the high output state. This was accomplished by adding Q9 and Q10. When the output stage
is operating in the linear region, that is, on the verge of
switching to either the high or the low state, Q9 and Q10
form sort of an active collector load for Q8. The current
through R15 is constant at approximately 2 mA as the output voltage changes through the active region. Hence, the
percentage change in the collector current of Q8 due to the
voltage change across R17 is made smaller by this pre-bias
current; and the effective stage gain is increased.

This particular output configuration gives a higher gain than
either a standard DTL or TIL output stage. It can also drive
enough current in the high state to make it compatible with
TIL, yet outputs can be wire DR'ed as with DTL.
Remaining details of the Circuit are that Q7 is connected as
an emitter follower to make the circuit even less sensitive to
transistor current gains. R16limits the base drive to Q7 with
the output saturated, while R17 limits the base drive to the
output transistor, Q8. A resistor, R7, which can be used to
terminate the twisted-pair line is also included on the chip. It
is not connected directly across the inputs. Instead, one end
is left open so that a capacitor can be inserted in series with
the resistor. The capacitor significantly reduces the power
dissipation in both the line transmitter and receiver, especially in low-duty-cycle applications, by terminating the line
at high frequencies but blocking steady-state current flow in
the terminating resistor.
Since line receivers are generally used repetitively in a system, the DS7820 has been designed with two independent
receivers on a single silicon chip. The device is fabricated
on a 41 x 49 mil-square die using the standard six mask
planar-epitaxial process. The processing employed is identical to that used on TIL circuits, and the design does not
impose any unusual demands on the processing. It is only
required that various parts within the circuit match well, but
this is easily accomplished in a monolithic integrated circuit
without any special effort in manufacturing. A photomicrograph of the integrated Circuit chip is shown in Figure 11.

With the output in the high state (Q8 cut off), the output
resistance is equal to R 15, as long as the load current is
less than 2 mA. When the load current goes above this
value, Q9 turns on; and the output resistance increases to
1.5k, the value of R17.

1-293

III

N

r-------------------------------------------------------------------------------~

N

Figure 13 is a similar plot for varying common mode input
voltage. Again the differential input voltages are given for
high and low states on the output with a worst case fanout
of 2. With precisely matched components within the integrated circuit, the threshold voltage will not change with
common mode voltage. The mismatches typically encountered give a threshold voltage change of ± 100 mV over a
± 20V common mode range. This change can have either a
positive slope or a negative slope.

I

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02

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~

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....

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TL/F17188-12

FIGURE 11. Photomicrograph of the DS7820
Dual Line Receiver

~C

The only components in the circuit which see voltages higher than standard logic circuits are the resistors used to attenuate the input signal. These resistors, R1, R7, R8 and
R9, are diffused into a separate, floating, N-type isolation
tub, so that the higher voltage is not seen by any of the
transistors. For a ± 15V input voltage range, the breakdown
voltages required for the collector-isolation and collectorbase diodes are only 15V and 19V, respectively. These
breakdown voltages can be achieved readily with standard
digital processing.

-02
-0.4
-20

-10

20

10

INPUT VOL TAGE (VI
TLlF17188-14

FIGURE 13. Differential Input Voltage Required for High
or Low Output as a Function of Common Mode Voltage

~

4 I-

w

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The purpose of the foregoing was to provide some insight
into circuit operation. A more exact mathematical analysis of
the device is developed in Appendix A.

CI

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FANOUT'2

,t::.:::I j.~'I-

."

3

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~

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RECEIVER PERFORMANCE
The characteristics of the line receiver are described graphically in Figures 12 through 18. Figure 12 illustrates the effect of supply voltage variations on the threshold accuracy.
The upper curve gives the differential input voltage required
to hold the output at 2.5V while it is supplying 200 p.A to the
digital load. The lower curve shows the differential input
needed to hold the output at O.4V while it sinks 3.5 rnA from
the digital load. This load corresponds to a worst case fanout of 2 with either DTL or TTL integrated circuits. The data
shows that the threshold accuracy is only affected by
± 60 mV for a ± 10% change in supply voltage. Proper operation can be secured over a wider range of supply voltages, although the error becomes excessive at voltages below4V.

5SoC 1---<0{1

rl1t-

2

", '

iU _

2SoC

125°C

: 'I'
-0.4

0.2

- 0.2

0.4

DIFFERENTIAL INPUT VOLTAGE (VI
TLlF17188-15

FIGURE 14. Voltage Transfer Function
The transfer function of the circuit is given in Figure 14. The
loading is for a worst case fanout of 2. The digital load is not
linear, and this is reflected as a non-linearity in the transfer
function which occurs with the output around 1.5V. These
transfer characteristics show that the only significant effect
of temperature is a reduction in the positive swing at
- 55·C. However, the voltage available remains well above
the 2.5V required by digital logic.

~
w

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~>

0.2
Vee' 5V
Til. '25°C-

0.1

-

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....

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~

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-0.1
-0.2

C

j

4

4.5

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-0.3

d • ,• y •

5.5

0.2

SUPPl V VOLTAGE (VI

,--

.I Cd • , • y = 100 pF

."

f

0
0.4

I

0.6

0.8

TIME(j.osl

TLlF17188-13

FIGURE 12. Differential Input Voltage Required for High
or Low Output as a Function of Supply Voltage

TL/F/7188-16

FIGURE 15. Response Time with and
without an External Delay Capacitor

1-294

Figure 15 gives the response time, or propagation delay, of
the receiver. Normally, the delay through the circuit is about
40 ns. As shown, the delay can be increased, by the addition of a capacitor between the response-time terminal and
ground, to make the device immune to fast noise spikes on
the input. The delay will generally be longer for negative
going outputs than for positive going outputs.

The variation of the internal termination resistance with temperature is illustrated in Figure 18. Taking into account the
initial tolerance as well as the change with temperature, the
termination resistance is by no means precise. Fortunately,
in most cases, the termination resistance can vary appreciably without greatly affecting the characteristics of the
transmission line. If the resistor tolerance is a problem, however, an external resistor can be used in place of the one
provided within the integrated circuit.

Under normal conditions, the power dissipated in the receiver is relatively low. However, with large common mode input
voltages, dissipation increases markedly, as shown in Figure 16. This is of little consequence with common mode
transients, but the increased dissipation must be taken into
account when there is a OC difference between the grounds
of the transmitter and the receiver. It is important to note
that Figure 16 gives the dissipation for one half the dual
receiver. The total package dissipation will be twice the values given when both sides are operated under identical
conditions.
300
~
.§
z
0

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200

~\

~

~

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a:

~

OUTPUT LOW
ONE SlOE

'~

~

25~

-20

u

ct

Ii;

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-10

-

10

~"Pu,.(1

DATA TRANSMISSION

I

20

The purpose of C1 on the receiver is to provide OC isolation
of the termination resistor for the transmission line. This capacitor can both increase the differential noise immunity, by
reducing attenuation on the line, and reduce power dissipation in both the transmitter and receiver. In some applications, C1 can be replaced with a short between Pins 1 and
2, which connects the internal termination resistor of the
087820 directly across the line. C2 may be included, if necessary, to control the response time of the receiver, making
it immune to noise spikes that may be coupled differentially
into the transmission lines.

ONE SIDE-

l'..

..... ~It

.........
.........

........

.........
..........

-10

10

15 100 125

The interconnection of the 087830 line driver with the
087820 line receiver is shown in Figure 19. With the exception of the transmission line, the design is rather straightforward. Connections on the input of the driver and the output
or strobe of the receiver follow standard design rules for
OTL or TTL integrated logic circuits. The load presented by
the driver inputs is equal to 3 standard digital loads, while
the receiver can drive a worst-case fanout of 2. The load
presented by the receiver strobe is equal to one standard
load.

~QJt

Qur,
"" Pu,.

50

FIGURE 18. Variation of Termination Resistance
with Temperature

I
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....... ...... 10.

25

TL/F17188-19

Ii
'I

10

0

TEMPERATURE (OC)

with common mode input voltage due to the current drawn
out of or fed into the supply through R9. The supply current
reaches a maximum with negative input voltages and can
actually reverse with large positive input voltages. The figure
also shows that the supply current with the output switched
into the low state is about 3 mA higher than with a high
output.

-2
-20

"- r--- f-'
-15 -50 -25

TL/F/7188-17

"

~",
/~

150

FIGURE 1S.lnternal Power Dissipation as a Function of
Common Mode Input Voltage
Figure 17 shows that the power supply current also changes

["'0..

110

a:

INPUT VOL TAGE (V)

:--...

180

z

'/125°C

~ ~ ~;

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/

~~

t

~

100

...

160

':\\

j::

190

§

I

v+ = 5.0V

1-

200

20

INPUT VOL TAGE (V)
TLlF17188-18

FIGURE 17. Power Supply Current as a Function of
Common Mode Input Voltage

1-295

.

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O.002IlF



....

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C(

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~
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~~

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150n+2000 pF

1/V

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U~TE~MINATED

~
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N.! ~

V- I----'

j.fti

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-10

2

4
TIME (!LS)

150n

75n

TL/F17188-22

FIGURE 21. Line Response for Various Termination
Resistances with a DC Isolation Capacitor
The effect of different values of DC isolation capacitors is
illustrated in Figure 22. This shows that the RC time constant of the termination resistor/isolation capacitor combination should be 2 to 3 times the line delay. As before, this
data was taken for a 150 ns long line.

t'-~

v'"1~

-5

V'

-10
TIME (/lS)

10
ls0n+200 pF

TL/F17188-20

FIGURE 20. Transmission Line Response
with Various Termination Resistances

IV V V

1.& ~

~

Figure 21 gives the line-transmission characteristics with
various termination resistances when a DC isolation capacitor is used. The line is identical to that used in the previous
example. It can be seen that the transient reponse is nearly
the same as a DC terminated line. The attenuation, on the
other hand, is considerably lower, being the same as an
unterminated line. An added advantage of using the isolation capacitor is that the DC signal current is blocked from
the termination resistor which reduces the average power
drain of the driver and the power dissipation in both the
driver and receiver.

w

r- Ison +4000 pF

CI
C(

~
c
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C(

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150n +1100 pF

~~

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-10

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4
TIME (liS)
TL/F/7188-23

FIGURE 22. Response of Terminated Line with Different
DC Isolation Capacitors

1-296

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UNTERMINATED

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UNTERMINATED

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c:>

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1\~lson +2000 pF

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-10

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TIME !}.is)

TIME (I's)

TLlFI71BB-24

a. VCM =

OV

b. VCM

=

c.

-15V

VCM

=

15V

FIGURE 23. Line Response With Different Terminations and Common Mode Input Voltages
In Figure 23, the influence of a varying ground voltage between the transmitter and the receiver is shown. The difference in the characteristics arises because the source resistance of the driver is not constant under all conditions. The
high output of the transmitter looks like an open circuit to
voltages reflected from the receiving end of the transmission line which try to drive it higher than its normal DC state.
.This condition exists until the voltage at the transmitting end
becomes high enough to forward bias the clamp diode on
the 5V supply. Much of the phenomena which does not follow simple transmission-line theory is caused by this. For
example, with an unterminated line, the overshoot comes
from the reflected signal charging the line capacitance to
where the clamp diodes are forward biased. The overshoot
then decays at a rate determined by the total line capacitance and the input resistance of the receiver.

differential load current is large by comparison to the common mode current so that the output transistors of the driver
are always conducting.
The low output of the driver can also be pulled below
ground to where the lower clamp diode conducts, giving
effects which are similar to those described for the high
output. However, a current of about 9 mA is required to do
this, so it does not happen under normal operating conditions.
To summarize, the best termination is an RC combination
with a time constant approximately equal to 3 times the
transmission-line delay. Even though its value is not precisely determined, the internal termination resistor of the
integrated circuit can be used because the line characteristics are not greatly affected by the termination resistor.
The only place that an RC termination can cause problems
is when the data transmission rate approaches the line delay and the attenuation down the line (terminated) is greater
than 3 dB. This would correspond to more than 1000 ft. of
twisted-pair cable with No. 22 copper conductors. Under
these conditions, the noise margin can disappear with lowduty-cycle signals. If this is the case, it is best to operate the
twisted-pair line without a termination to minimize transmission losses. Reflections should not be a problem as they will
be absorbed by the line losses.

When the ground on the receiver is 15V more negative than
the ground at the transmitting end, the decay with an unterminated line is faster, as shown in Figure 23b. This occurs because there is more current from the input resistor of
the receiver to discharge the line capacitance. With a terminated line, however, the transmission characteristics are the
same as for equal ground voltages because the terminating
resistor keeps the line from getting charged.
Figure 23c gives the transmission characteristics when the
receiver ground is 15V more positive than the transmitter
ground. When the line is not terminated, the differential voltage swing is increased because the high output of the driver
will be pulled against the clamp diodes by the common
mode input current of the receiver. With a DC isolation capacitor, the differential swing will reach this same value with
a time constant determined by the isolation capacitor and
the input resistance of the receiver. With a DC coupled termination, the characteristics are unchanged because the

CONCLUSION
A method of transmitting digital information in high-noise
environments has been described. The technique is a much
more attractive solution than high-noise-immunity logic as it
has lower power consumption, provides more noise rejection, operates from standard 5V supplies, and is fully compatible with almost all integrated logic circuits. An additional
advantage is that the circuits can be fabricated with integrated circuit processes used for standard logic circuits.

1-297

z
N
N

.

N
N

Z

«

APPENDIX A

where VIN is the common mode input voltage and RallRb
denotes the parallel connection of the two resistors. In
Equation (A.1), R8 = R9, R3 = R10, R10 <%:: R11,
R9 ~ R10,R3 <%:: R11,R8 ~ R3and

LINE RECEIVER
Design Analysis
The purpose of this appendix is to derive mathematical expressions describing the operation of the line receiver. It will
be shown that the performance of the circuit is not greatly
affected by the absolute value of the components within the
integrated circuit or by the supply voltage. Instead, it depends mostly on how well the various parts match.
The analysis will assume that all the resistors are well
matched in ratio and that the transistors are likewise
matched, since this is easily accomplished over a broad
temperature range with monolithic construction. However,
the effects of component mismatching will be discussed
where important. Further, large transistor current gains will
be assumed, but it will be pointed out later that this is valid
for current gains greater than about 10.

R3
R4 + 2R6 + R3
so it can be reduced to
V
IC1 =

R10 +
- 3VSE - R9"V

R10 + R11 + R3

(A.2)

VC2 = V+ - IC2R12

(A.3)

For zero differential input voltage, the collector currents of
01 and 02 will be equal so Equation (A.3) becomes
_ +
VC2- V -

R12 (v+ - 3VSE - R10 v+)
R9
R10+R11+R3

(AA)

It is desired that this voltage be 3VSE so that the output
stage is just on the verge of switching with zero input. Forcing this condition and solving for R12 yields
V+ - 3V
R12 = (R10 + R11 + R3)
SE
(A.5)
+
R10 +
V -3VSE-R9"V

R3
V
R311R11
R4 + 2R6 + R3 SE1 - R8 + R3//R1 VIN
R911R10 + R11 + R311R8
V+)
R10llR11
(V
IN R9 + R10llR11
+ R911R10 + R11 + R311R8

3

which shows that the collector current of 01 is not affected
by the common mode voltage.
The output voltage on the collector of 02 is

A schematic diagram of the OS7820 line receiver is shown
in Figure A-f. Referring to this circuit, the collector current
of the input transistor is given by
V+ - VSE1 - VSE3 - VSE4
IC1 = R911R10 + R11 + R311R8

+

<%::

(A.1)

This shows that the optimum value of R12 is dependent on
supply voltage. For a 5V supply it has a value of 4.7 kn.
Substituting this and the other component values into (AA),
VC2 = 2.83VSE + 0.081V+

(A.6)

RESPONSE·TlME
CONTROL

..----------- v+

r---------~t_--~._------~~._--------~._--~

R15
320

NON·INVERTING
INPUT

e---..- - - - - OUTPUT
Rl
110

TERMINATION

R4
lk

R5
lk

R14
150

R3
161
~----------+-------+---------~----~-----------------GROUNO

Rl
5k

R2
161
STROBE
TL/F/7188-25

FIGURE A·1. Schematic Diagram of One Half of the DS7820 Line Receiver

1·298

l>
which shows that the voltage on the collector of 02 will vary
by about SO mV for a 1V change in supply voltage.

load the output of the first-stage amplifier, because of the
compounded current gain of the three transistors, and that
OS is driven from a low resistance source.

The next step in the analysis is to obtain an expression for
the voltage gain of the input stage.

It follows thet the gain of the output stage can be determined from the change in the emitter-base voltage of OS
required to swing the output from a logic one state to a logic
zero state. The expression

An equivalent circuit of the input stage is given in Figure A-2.
Noting that R6 = R7 = RS and R2 ~ 0.1 (R6 + R71IRS),
the change in the emitter current of 01 for a change in input
voltage is

~I

_
0.9R2
~V
E2 - R1 (0.9 R2 + RE2)
IN

IC1
kT
= -log 9 (A.13)
IC2
q
describes the change in emitter-base voltage required to
vary the collector current from one value, IC1' to a second,
IC2. With the output of the receiver in the low state, the
collector current of OS is
~VSE

(A.7)

Hence, the change in output voltage will be
~VOUT = alE2R12

0.9 a R2 R12

------~VIN

Since a

~

R1 (0.9 R2 + RE2
1, the voltage gain is
A

_
0.9R2R12
V1 - R1 (0.9 R2 + RE2)

The emitter resistance of 02 is given by
kT
RE2=qlC2
V+ - 3VSE
where
IC2 =
R12
so

kTR12
RE2 = q (V+ - 3VSE)

(A.S)
IOL =

+ VSE9

R15 -

(A.9)

(A. 10)
(A.11)

IOL =

I

R2

R13

SINK,

(A.14)

VSE

+ R15

(A.15)

+ ISINK

Similarly, with the output in the high state, the collector current of OS is
v+ - VOH - VSE9 - VSE10
R17

IOH =

+

+

VSE9 _ VSE8
R15
R14
VSE?
R13 - ISOURCE,

(A.16)

where VOH is the high-level output voltage and ISOURCE is
the current needed to supply the input leakage of the digital
circuits loading the comparator.
With the same conditions used in arriving at (A.15), this becomes

Rl
Sk
Ru

161

+ VSE? + I

V+ - VOL - 2VSE
R17
VSE
- 2R14

(A.12)

Finally, the threshold error due to finite gain in the output
stage can be considered. The collector current of 07 from
the bleeder resistor R14, is large by comparison to the base
current of OS, if OS has a reasonable current gain. Hence,
the collector current of 07 does not change appreciably
when the output switches from a logic one to a logic zero.
This is even more true for 06, an emitter follower which
drives 07. Therefore, it is safe to presume that 06 does not

1

VSE8
R14

where VOL is the low state output voltage and ISINK is the
current load from the logic that the receiver is driving. Noting that R13 = 2R14 and figuring that all the emitter-base
voltages are the same, this becomes

Therefore, at 25°C where VVE = 670 mV and kT/q =
26 mV, the computed value for gain is 0.745. The gain is not
greatly affected by temperature as the gain at - 55°C where
VSE = 810 mV and kT/q = 1S mV is 0.774, and the gain at
125°C where VSE = 4S0 mV and kT/q = 34 mV is 0.730.
With a voltage gain of 0.75, the results of Equation (A.6)
show that the input referred threshold voltage will change
by O.11V for a 1V change in supply voltage. With the standard ± 10-percent supplies used for logic circuits, this
means that the threshold voltage will change by less than
±60 mV.

~VIN

V+ - VOL - VSE9 - VSE10
R17

IOH =

V+ - VOH - 2VSE
R17

VSE

+ R15

VSE
- 2R14 - ISOURCE

!~IE2

(A.17)

I

R12 ~VOUT
4.1Sk

RS
lk

I
TLlF17188-26

FIGURE A-2. Equivalent Circuit Used to Calculate Input Stage Gain

1-299

z
N
N

.

C\I
C\I

Z

~

From (A.13) the change in the emitter-base voltage of OS in
going from the high output level to the low output level is

ties, if known, can be added directly into Equation (A.1S) to
give a more accurate gain expression.

kT
IOL
!1VSE = -loge-I
(A.1S)
q
OH
providing that OS is not quite in saturation, although it may
be on the verge of saturation.

The most stringent matching requirement in the receiver is
the matching of the input stage divider resistors: R1 with RS
and R2 with R3. As little as 1% mismatch in one of these
pairs can cause a threshold shift of 150 mV at the extremes
of the ± 15V common mode range. Because of this, it is
necessary to make the resistors absolutely identical and locate them close together. In addition, since R1 and RS do
dissipate a reasonable amount of power, they have to be
located to minimize the thermal gradient between them. To
do this, R9 was located between R1 and RS so that it would
heat both of these resistors equally. There are not serious
heating problems with R2 and R3; however, because of
their low resistance value, it was necessary even to match
the lengths of the aluminum interconnects, as the resistance of the aluminum is high enough to cause intolerable
mismatches. Of secondary importance is the matching of
01 and 02 and the matching of ratios between R11 and
R12. A 1 mV difference in the emitter-base voltages of 01
and 02 causes a 30 mV input offset voltage as does a 1 %
mismatch in the ratio of R 11 to R 12.

The change of input threshold voltage is then
kT
IOL
!1VTH = -loge - I
(A.19)
qAv1
OH
where Av1 is the input stage gain. With a VvJrst case fanout
of 2, where VOH = 2.5V, VOL = O.4V, ISOURCE = 40 IlA
and ISINK = 3.2 mA, the calculated change in threshold is
37 mV at 25°C, 24 mV at -55°C and 52 mV at 125°C.
The measured values of overall gain differ by about a factor
of two from the calculated gain. This is not too surprising
because a number of assumptions were made which introduce small errors, and all these errors lower the gain. It is
also not too important because the gain is high enough
where another factor of two reduction would not cause the
circuit to stop working.
The main contributors to this discrepancy are the non-ideal
behavior of the emitter-base voltage of OS due to current
crowding under the emitter and the variation in the emitter
base voltage of 07 and OS with changes in collector-emitter
voltage (hRE)'
Although these parameters can vary considerably with different manufacturing methods, they are relatively fixed for a
given process. The !1 VSE errors introduced by these quanti-

The circuit is indeed insensitive to transistor current gains
as long as they are above 10. The collector currents of 04
and 06 are made equal so that their base currents load the
collectors of 01 and 02 equally. Hence, the input threshold
voltage is affected only by how well the current gains match.
Low current gain in the output transistor, OS, can cause a
reduction in gain. But even with a current gain of 10, the
error produced in the input threshold voltage is less than
50 mV.

1-300

>
Z

National Semiconductor
Application Note 108
Bill Fowler

Transmission Line
Characteristics

I

....A.

o

(X)

INTRODUCTION
Digital systems generally require the transmission of digital
signals to and from other elements of the system. The component wavelengths of the digital signals will usually be
shorter than the electrical length of the cable used to connect the subsystems together and, therefore, the cables
should be treated as a transmissions line. In addition, the
digital signal is usually exposed to hostile electrical noise
sources which will require more noise immunity than required in the individual subsystems environment.
The requirements for transmission line techniques and
noise immunity are recognized by the designers of subsystems and systems, but the solutions used vary considerably.
Two widely used example methods of the solution are
shown in Figure 1. The two methods illustrated use unbalanced and balanced circuit techniques. This application
note will delineate the characteristics of digital signals in
transmission lines and characteristics of the line that effect
the quality, and will compare the unbalanced and balanced
circuits performance in digital systems.

INDUCED NDISE ALONG CABLE ROUTE
GROUND PROBLEMS IN ASSOCIATED EQUIPMENT

TL/F/6626-2

FIGURE 2. External Noise Sources

UNBALANCED METHOD
SV

120

CABLE
BALANCED METHOD

TLlF/6626-3

FIGURE 3. Internal Noise Sources

TLlF/6626-1

FIGURE 1
NOISE
The cables used to transmit digital signals external to a subsystem and in route between the subsystem, are exposed to
external electromagnetic noise caused by switching transients from actuating devices of neighboring control systems. Also external to a specific subsystem, another subsystem may have a ground problem which will induce noise
on the system, as indicated in Figure 2.

DISTORTION
The objective is the transmission and recovery of digital in·
telligence between subsystems, and to this end, the characteristics of the data recovered must resemble the data
transmitted. In Figure 4 there is a difference in the pulse
width of the data and the timing signal transmitted, and the
corresponding signal received. In addition there is a further
difference in the signal when the data is "AND"ed with the
timing signal. The distortion of the signal occurred in the
transmission line and in the line driver and receiver.

The signals in adjacent wires inside a cable may induce
electromagnetic noise on other wires in the cable. The induced electromagnetic noise is worse when a line terminated at one end of the cable is near to a driver at the same
end, as shown in Figure 3. Some noise may be induced from
relay circuits which have very large transient voltage swings
compared to the digital signals in the same cable. Another
source of induced noise is current in the common ground
wire or wires in the cable.

n

TRANSMITTED
NRZ DATA

---1

TRANSMITTEO

--1 LJ LJ LJ U L

TIMING

l......---

n n n nn

RECEIVED--11
DATA

......------

RECEIVEDJWUUL
TIMING

tll~-_ _ _ _ __

RECOVERED
DATA ~

TL/F/6626-4

FIGURE 4. Effect of Distortion
1-301

III

co

.

o
,...
z

.:(

A primary cause of distortion is the effect the transmission
line has on the rise time of the transmitted data. Figure 5
shows what happens to a voltage step from the driver as it
travels down the line. The rise time of the signal increases
as the signal travels down the line. This effect will tend to
affect the timing of the recovered signal.

In the previous example, it was assumed that the threshold
of the receiver was halfway between the ONE and ZERO
logic levels. If the receiver threshold isn't halfway the receiver will contribute to the distortion of the recovered signal. As
shown in Figure 8, the pulse time is lengthened or shortened, depending on the polarity of the signal at the receiver.
This is due to the offset of the receiver threshold.

r-lL------..":.
~...

DRIVER
INPUT ~

~~C-'"
=-.J'J
'-_
,

RECEIVER
INPUT

\

RECEIVER
THRESHOLD
0

---'n

RECEIVER _ _ _
OUTPUT

TLIF/BB26-5
RECEIVER
OUTPUT

FIGURE 5. Signal Response at Receiver

POSITIVE PULSE

' .

---,I

r----

~_..J

NEGATIVE PULSE

TLIF/BB26-B
I-e- CC

FIGURE 8. Slicing Level Distortion

1-.rfP

UNBALANCED METHOD
Another source of distortion is caused by the IR losses in
the wire. Figure 9 shows the IR losses that occur in a thousand feet of no. 22 AWG wire. Notice in this example that
the losses reduce the signal below the threshold of the receiver in the unbalanced method. Also that part of the IR
drop in the ground wire is common to other circuits-this
ground signal will appear as a source of noise to the other
unbalanced line receivers in the system.

THE STEP RESPONSE OF A TRANSMISSION
LINE RESEMBLES A COMPLIMENTARY
ERROR FUNCTION RATHER THAN AN
EXPONENTIAL FUNCTION

TIME

TLIF/BB26-6

FIGURE 6. Signal Rise Time
The rise time in a transmission line is not an exponential
function but a complementary error function. The high frequency components of the step input are attenuated and
delayed more than the low frequency components. This attenuation is inversely proportional to the frequency. Notice
in Figure 6 particularly that the signal takes much longer to
reach its final DC value. This effect is more significant for
fast risetimes.

120
LM75452

r----'
I

30
~~I~~~H-4-~~

The Duty Cycle of the transmitted signal also causes distortion. The effect is related to the signal rise time as shown in
Figure 7. The signal doesn't reach one logic level before the
signal changes to another level. If the signal has a % (50%)
Duty Cycle and the threshold of the receiver is halfway between the logic levels, the distortion is small. But if the Duty
Cycle is Va as shown in the second case the signal is considerably distorted. In some cases, the signal may not reach
the receiver threshold at all.

I

I
I

I

I

I
L ____.......J~\""',..,..-Hi---:--J...---'o:---.......
':'
0.S3V I
30

-..I

t

IR OROP GENERATES
GROUND LOOP NOISE

TLIF/BB26-9

FIGURE 9. Unbalanced Method
Transmission lines don't necessarily have to be perfectly
terminated at both ends, (as will be shown later) but the
termination used in the unbalanced method will cause additional distortion. Figure 10 shows the signal on the transmission line at the driver and at the receiver. In this case the
receiver was terminated in 1200, but the characteristic impedance of the line is much less. Notice that the wave forms
have significant steps due to the incorrect termination of the
line. The signal is subject to misinterpretation by the line
receiver during the period of this Signal transient because of
the distortion caused by Duty Cycle and attenuation. In addition, the noise margin of the signal is reduced.

h h h h h
U U U U L
... - - - - -

LINERESPONSE~VTH
.... _--

nL - - - JnL

1ISOUTY
CYCLE DATA..J

/' V
'<~
... _____
---vTH

liB DUTY CYCLE'

LINE RESPONSE

IL--l

I

1/20UTY
CYCLE OATA..J

1/2 OUTY CYCLE

I
I

TL/F IBB26- 7

FIGURE 7. Signal Distortion Due to Duty Cycle
1-302

-

method, they generate very little ground noise. As a result,
the balanced circuit doesn't contribute to the noise pollution
of its environment.

AT DRIVER

r

>
Z

.....
I

oQ)

2V/DIV

AT RECEIVER

DM7B30
30

100 FT TWISTED
PAIR SHiElDED

2001ls/DIV

I

-----=>

170

TL/F/8826-10

FIGURE 10. LM75451, DM7400 Line Voltage Waveforms

30

The signal waveforms on the transmission line can be estimated before hand by a reflection diagram. Figure 11 shows
the reflection diagram of the rise time wave forms. The voltage versus current plot on left then is used to predict the
transient rise time of the signal shown on the right. The
initial condition on the transmission line is an IR drop across
the line termination. The first transient on the line traverses
from this initial point to zero current. The path it follows
corresponds to the characteristic impedance of the line. The
second transient on the diagram is at the line termination.
As shown, the signal reflects back and forth until it reaches
its final DC value.

30

INPUT

BALANCED LINE SIGNAL

OUTPUT

THE GROUND LOOP CURRENT IS MUCH LESS THAN SIGNAL CURRENT

TL/F/8826-13

FIGURE 13. Cross Talk of Signals
The circuit used for a line receiver in the balanced method is
a differential amplifier. Figure 14 shows a noise transient
induced equally on lines A and line B from line C. Because
the signals on line A and B are equal, the signals are ignored by the differential line receiver.
Likewise for the same reason, the differential signals on
lines A and B from the driver will not induce transients on
line C. Thus, the balanced method doesn't generate noise
and also isn't susceptible to noise. On the other hand the
unbalanced method is more sensitive to noise and also generates more noise.

Figure 12 shows the reflection diagram of the fall time.
Again the signal reflects back and forth between the line
termination until it reaches its final DC value. In both the rise
and fall time diagrams, there are transient voltage and current signals that subtract from the particular signal and add
to the system noise.

•

40 mA

TL/F/8826-11

FIGURE 11. Line Reflection Diagram of Rise Time

+S.OV

SIGNAL ON LINE A
SIGNAL AT DRIVER

SIGNAL ON LINE B

~
~

DIFFERENCE SIGNAL (A-B) - - - - - . . . , _

-

TL/F/8826-14

FIGURE 14. Cross Talk of Signals

TIME

The characteristic impedance of the unbalanced transmission line is less than the impedance of the balanced transmission line. In the unbalanced method there is more capacitance and less inductance than in the balanced method.
In the balanced method the Reactance to adjacent wires is
almost cancelled (see Figure 15). As a result a transmission
line may have a 60n. unbalanced impedance and a 90n.
balanced impedance. This means that the unbalanced

TLIF/8826-12

FIGURE 12. Line Reflection Diagram of Fall Time
BALANCED METHOD
In the balanced method shown in Figure 13, the transient
voltages and currents on the line are equal and opposite
and cancel each others noise. Also unlike the unbalanced
1-303

~

Q
,...
z•



MEASURED PERFORMANCE

~

The unbalanced method circuit used in this application note
up to this point is the unbalanced circuit shown in Figure 1.
The termination of its transmission line was greater than
the characteristic impedance of the unbalanced line and the

:a

100

co

E
w

...<

~

1/2 DUTY CYCLE

...w

~

10

~

a:

== 1I8~IJtc~

~
~

TL/F/8826-18

FIGURE 18. Data Rate vs Cable Type

100
1/8 DUTY CYCLE
DM7820AlDM7830
NINE TWISTED PAIR
Zo BALANCED 90n

:Ii

<
;;;

Q

~

10
450 FT

x

...

DM7820A/DM7830
SINGLE TWISTED
PAIR SHIELDED

1.0
10

100

...=
1000

LINE LENGTH (FT)

~
<

LM754521DM7400
-TERMINATED 100#150n
NINE TWISTED PAIRS
ABSOLUTE 1/8 DUTY CYCLE

=

250~1---"

~

;;;

<

<

1000

100

10

LINE LENGTH (FT)

C[

:Ii
)(

;

1.0 l..---L-...........................---l-L.LLlWJ

g

Q

:a= 100
a:

F==F*i±B~~~~am

:!

FIGURE 16. Impedance Measurement

...<

10

~

MAXI~UrHfI'?'k~-+-+++++H

~

E

...
~
...<

25%
15%
10%

10

w

~
1.0

1.0
100
1000
10
LINE TERMINATION RESISTANCE (OHMS)

10

1000

100
LINE LENGTH (FT)

TL/F18826-19

FIGURE 19. Data Rate vs Duty Cycle

FIGURE 20. Data Rate vs Line
Termination
1-304

FIGURE 21. Data Rate vs Distortion
of LM75452, DM7400

.

»

Figure 19 shows the reduction in Data Rate caused by Duty
Cycle. It can be observed that the Absolute Maximum Duty
Rate of % Duty Cycle is less than % Duty Cycle. The following performance curves will use % Duty Cycle since it is the
worst case.

drastically reduced as additional Near End Drivers are added. When this performance is compounded by timing distortion the performance is further reduced.

z
....
o

Q)

5V

Absolute Maximum Duty Rate versus the Line Termination
Resistance for two different lengths of cable is shown in
Figure 20. It can be seen from the figure that the termination
doesn't have to be perfect in the case of balanced circuits.
It is better to have a termination resistor to minimize the
extra transient signal reflecting between the ends of the
line. The reason the Data Rate increases with increased
Termination Resistance is that there is less IR drop in the
cable.

10D

NEAR
END RECEIVER

......--+~t-----~II

The graphs in Figure 21 show the Data Rate versus the Line
Length for various percentages of timing distortion using the
unbalanced LM75452 and DM7400 circuits shown in Figure
17. The definition of Timing Distortion is the percentage difference in the pulse width of the data sent versus the data
received.
100

llt---...-++--...
CI

A~~~J~~

::>

~

~ ~<~IMm

to

E

......<

10

10%
III
DM7820AlDM7830
NINE TWISTED PAIR
1/8 DUTY CYCLE

II:

...

<
<
CI

1.0
10

100

CABLE WITH
NINE TWISTED PAIR

.~
15%

5%

III

11t---....++--...

1000

LINE LENGTH 1FT)
TLIF/BB26-20
TLIF/BB26-21

FIGURE 22. Data Rate vs Distortion of DM7820A,
DM7830

FIGURE 23. Signal Cross Talk Experiment Using
DM75452, DM7400

Data Rate versus the Line Length for various percentage of
timing distortion using the balanced DM7820A and DM7830
circuit is shown in Figure 22. The distortion of this method is
improved over the unbalanced method, as was previously
theorized.

~ 100

~

E

=~

-I--

~

II:

...<<

===1=
-i--

...

The Absolute Maximum Data Rate versus Line Lengths
shown in the previous two figures didn't include any induced
signal noise. Figure 23 shows the test configuration of the
unbalanced circuits which was used to measure near end
cross talk noise. In this configuration there are eight line
drivers and one receiver at one end of the cable. The performance of the receiver measured in the presence of the
driver noise is shown in Figure 24.
Figure 24 shows the Absolute Maximum Duty Rate of the
unbalanced method versus line length and versus the number of line drivers corresponding to the test configuration
delineated in Figure 23. In the noise measurement set-up
there was a ground return for each signal wire. If there is
only one ground return in the cable the performance is
worse. The graph shows that the effective line length is

II

CI

::>

10

lM75452/DM7400
TERMINATED 100 1/ 150n
NINE TWISTED PAIR
~8 DUTY CYCLE

FOUR NOISE
GENERATORS

Two' N(lIS~ B:

~GENERATORS
~

CI

~
::;;

HSIXNDISE

)(

r-GE~ERIA~OIRIS

<

::;;

......

~<

\

II

1.0
10

100

1000

LINE LENGTH 1FT)
TLIF/BB26-22

FIGURE 24. Data Rate vs Signal Cross Talk of LM75452,
DM7400
Figure 25 shows the test configuration of the balanced circuit used to generate worst case Near End cross talk noise
similar to the unbalance performance shown in the previous
figure. Unlike the unbalanced case, there was no measurable degradation of the circuits Data Rate or distortion.

1-305

co ,----------------------------------------------------------------------------------,

.

o
,..

z

«

when used within their limitation. This application note
shows that the balanced method is preferable for long lines
in noisy electrical environments. On the other hand the un·
balanced circuit works perfectly well with shorter lines and
reduced data rates.

NEAR END

..o~'~ l110i ~

DEFINITION OF BAUD RATE

-I

1/2 DUTY CYCLE

T,

1--

1--1---- T2

- - - - - 1__

1
TL/F/8826-24

1

1

BIT RATE = INTERVAL PER BIT

T2

1
BAUD RATE

= MINIMUM UNIT INTERVAL

1
Tl

The data in this note was plotted versus Baud Rate. The
minimum unit interval reflected the worse case conditions
and also normalized the diagrams so that the diagrams
were independent of duty cycle. If the duty cycle is 50%
then the Baud Rate is twice the Bit Rate.

CABLE WITH
NINE TWISTED PAIR

REFERENCES
IC's for Digital Data Transmission, Widlar and Kubinec, Na·
tional Semiconductor Application Note AN-22.
RADC TR73-309, Experimental Analysis of the Transmis·
sion of Digital Signals over Twisted Pair Cable, Hendrickson
and Evanowski, Digital Communication Section Communi·
cations and Navigation Division, Rome Air Development
Center, Griffis Air Force Base, New York.

170

\

B NEAR END GENERATORS

TL/F/8826-23

Fast Pulse Techniques, Thad Dreher, E·H Research Labo·
ratories, Inc., The Electronic Engineer, Aug. 1969.
Transient Analysis of Coaxial Cables, Considering Skin Ef·
fects, Wigingtom and Nahmaj, Proceedings of the IRE, Feb.
1957.

FIGURE 25. Signal Cross Talk Experiment Using
DS7830, DS7820A
CONCLUSION
National has a full line of both Balanced and Unbalanced
Line Drivers and Receivers. Both circuit types work well

Relection and Crosstalk in Logic, Circuit Interconnection,
John De Falco, Honeywell, Inc., IEEE Spectrum, July 1970.

1-306

.

l>

z

Transmission Line Drivers
and Receivers for
EIA Standards RS-422
and RS-423

National Semiconductor
Application Note 214
John Abbott

With the advent of the microprocessor, logic designs have
become both sophisticated and modular in concept. Frequently the modules making up the system are very closely
coupled on a single printed circuit board or cardfile. In a
majority of these cases a standard bus transceiver will be
adequate. However because of the distributed intelligence
ability of the microprocessor, it is becoming common practice for the peripheral circuits to be physically separated
from the host processor with data communications being
handled over cables (e.g. plant environmental control or security system). And often these cables are measured in hundreds or thousands of feet as opposed to inches on a backplane. At this point the component wavelengths of the digital signals may become shorter than the electrical length of
the cable and consequently must be treated as transmission
lines. Further, these signals are exposed to electrical noise
sources which may require greater noise immunity than the
single chassis system.
It is the object of this application note to underscore the
more important design requirements for balanced and unbalanced transmission lines, and to show that National's
OS1691 driver and OS78LS120 receiver meet or exceed all
of those requirements.

tor's application note AN-108 and EIA standards RS-422
(balanced) and RS-423 (unbalanced). A summary review of
these notes will show that the controlling factors in a voltage digital interface are:

N
.....
~

1) The cable length
2) The modulation rate
3) The characteristic of the interconnection cable
4) The rise time of the signal
RS-422 and RS-423 contain several useful guidelines relative to the choice of balanced circuits versus unbalanced
circuits. Figures 1a and 1b are the digital interface for balanced (1a) and unbalanced (1b) circuits.
Even though the unbalanced interface circuit is intended for
use at lower modulation rates than the balanced circuit, its
use is not recommended where the following conditions exist:
1) The interconnecting cable is exposed to noise sources
which may cause a voltage sufficient to indicate a change
of binary state at the load.
2) It is necessary to minimize interference with other signals, such as data versus clock.

a
~--VGRDUNo-::'-'_~Rt-r

3) The interconnecting cable is too long electrically for unbalanced operation (Figure 2).

THE REQUIREMENTS

The requirements for transmission lines and noise immunity
have been adequately recognized by National SemiconducBALANCED

LOAD

IDRIVER-t--INTERCDNNECTING---t--TER~~~~~ION-r-RECEIVER

I

r

I

I

CABLE

Legend:
Rt = Optional cable termination resistance/receiver input impedance.
VGROUND = Ground potential difference
A, B = Driver interface

TLIF/5854-1

A', B' = Load interface
C = Driver circuit ground
C' = Load circuit ground

FIGURE 1a. RS-422 Balanced Digital Interface Circuit

UNBALANCED
-DRIVER-j-INTERCONNECTING
CABLE
A
SIGNAL CONDUCTOR
\

I•

o

SIGNAL COMMON RETURN

B'

Legend:
Rt = Transmission line termination and/or receiver input impedance
VGROUND = Ground potential difference
A, C = Driver interface

TL/F/5854-2

A', S' = Load interface
C = Driver circuit ground
C' = Load circuit ground

FIGURE 1b. RS-423 Unbalanced Digital Interface Circuit

1-307

.

~
,...

N

z



5

100
40

lk

10k

1M

lOOk

10M

DATA MODULATION RATE (BAUDS)
TL/F/5854-3

Driver Balanced (RS-422)

FIGURE 2. Data Modulation Rate vs Cable Length
MODULATION RATE

The balanced driver characteristics as specified by RS-422
Sec 4.1 are as follows:

Section 3 of RS-422 and RS-423 states that the unbalanced
voltage interface will normally be utilized on data, timing or
control circuits where the modulation rate on these circuits
is below 100 kilobauds, and balanced voltage digital interface on circuits up to 10 megabauds. The voltage digital

1) A driver circuit should result in a low impedance (1000. or
less) balanced voltage source that will produce a differential voltage applied to the interconnecting cable in the
range of 2V to 6V.

I-TIl

---I

I~~

~I~----------T2------------~
Bit Rate =
Baud Rate =

1
Interval Per Bit

1
T2

1
1
=Minimum Unit Interval Tl

FIGURE 3a. Definition of Baud Rate

1-308

TLlF/5854-4

1/2 DUTY
CYCLE DATA

1/2 DUTY CYCLE
llNERESPDNSE VTH

A

A

A

/\

A

~~~"-7

/'
TL/F/5854-5

1/8 DUTY
CYCLE DATA

",
....... ""-

\C

-

TLlF/5854-6

FIGURE 3b. Signal Distortion Due to Duty Cycle

+----O.IVSS

O·1VSS

vss = IVI - vII
vss = Difference in steady state voltages

~-=--

O.9VSS
---I.IVSS

/
TL/F/5854-7

FIGURE 4. Unbalanced Driver Output Signal Waveform
2) With a test load of 2 resistors, 50n each, connected in
series between the driver output terminals, the magnitude
of the differential voltage (VT) measured between the 2
output terminals shall not be less than either 2.0V or 50%
of the magnitude of Va, whichever is greater. For the
opposite binary state the polarity of VT shall be reversed
(VT). The magnitude of the difference in the magnitude of
VT and VT shall be less than O.4V. The magnitude of the
driver offset voltage (Vas) measured between the center
point of the test load and driver circuit ground shall not be
greater than 3.0V. The magnitude of the difference in the
magnitude of Vas for one binary state and Vas for the
opposing binary state shall be less than O.4V.

steady state value, until the next binary transition occurs,
and at no time shall the instantaneous magnitude of VT or
VT exceed 6V, nor less than 2V.
Interconnecting Cable
The characteristics of the interconnecting cable should result in a transmission line with a characteristic impedance in
the general range of 100n to frequencies greater than
100 kHz, and a DC series loop resistance not exceeding
240n. The cable may be composed of twisted or untwisted
pair (flat cable) possessing the characteristics specified in
RS-422 Sec 4.3 as follows:
1) Conductor size of the 2 wires shall be 24 AWG or larger
with wire resistance not to exceed 30n per 1000 feet per
conductor.

3) During transitions of the driver output between alternating
binary states, the differential signal measured across a
100n test load connected between the driver output terminals shall be such that the voltage monotonically
changes between 0.1 and 0.9 of Vss within 0.1 of the unit
interval or 20 ns, whichever is greater. Thereafter the signal voltage shall not vary more than 10% of Vss from the

2) Mutual pair capacitance between 1 wire in the pair to the
other shall not exceed 20 pF per foot.
3) Stray capacitance between 1 wire in the pair with all other
wires connected to ground, shall not exceed 40 pF per
foot.

1-309

III

.

~
,...

A

C'I

+1/2 Vi

z

«

----------------------------------~+12V

TLIF/5854-8

1

TRANSITION
REGION
-1-----+-------4 MAXIMUM
OPERATING

-_~

R_A~iG~'v

____________________________

TLIF/5854-9

tb

TL/F/5854-10

= Time duration of the unit interval at the applicable modulation rate.

FIGURE 6. Receiver Input Sensitivity Measurement

tr:s: 0.1 tb when tb ~ 200 ns

Note: Designers of terminating hardware should be aware that slow signal
transitions with superimposed noise present may give rise to instability or oscillations in the receiving device, and therefore appropriate
techniques should be implemented to prevent such behavior. For example, adequate hysteresis and response control may be incorporated into the receiver to prevent such conditions.

tr :s: 20 ns when tb < 200 ns

Vss = Difference in steady state voltages
Vss = IVI - vII

FIGURE 5. Balanced Driver Output Signal Waveform

sions shall be incorporated in the load to provide a steady
binary condition (either "1" or "0") to protect against certain fault conditions (open or shorted cable).

Receiver
The load characteristics are identical for both balanced (RS422) and unbalanced (RS-423) circuits. Each consists of a
receiver and optional termination resistance as shown in
Figure 1. The electrical characteristics single receiver without termination or optional fail-safe provisions are specified
in RS-422/423 Sec 4.2 as follows:

The designer should be aware that in circuits employing
pull-up resistors, the resistors used become part of the
termination.
SIGNAL RISE TIME
The signal rise time is a high frequency component which
causes interference (near end cross-talk) to be coupled to
adjacent channels in the interconnecting cable. The nearend crosstalk is a function of both rise time and cable
length, and in considering wave shaping, both should be
considered. Since in the balanced voltage digital interface
the output is complementary, there is practically no crosstalk coupled and therefore wave shaping is limited to unbalanced circuits.

1) Over an entire common·mode voltage range of - 7V to
+ 7V, the receiver shall not require a differential input
voltage of more than 200 mV to correctly assume the
intended binary state. The common-mode voltage (VCM)
is defined as the algebraic mean of the 2 voltages appearing at the receiver input terminals with respect to the
receiver circuit ground. Reversing the polarity of VT shall
cause the receiver to assume the opposite binary state.
This allows for operations where there are ground differences caused by IR drop and noise of up to ± 7V.

Per RS-423 Sec 4.1.6, the rise time of the signal should be
controlled so that the signal has reached 90% of Vss between 10% and 30% of the unit interval at the maximum
modulation rate. Below 1 kilobaud the time to reach 90%
Vss shall be between 100 J-ts and 300 J-ts. If a driver is to
operate over a range of modulation rates and employ a
fixed amount of wave shaping which meets the specification
for the maximum modulation rate of the operating range, the
wave shaping is considered adequate for all lesser modulation rates.
However a major cause of distortion is the effect the transmission line has on the rise time of the transmitted signal.
Figure 7 shows the effect of line attenuation and delay to a
voltage step as it progresses down the cable. The increase
of the rise time with distance will have a considerable effect
on the distortion at the receiver. Therefore in fixing the
amount of wave shaping employed, caution should be taken
not to use more than the minimum required.

2) To maintain correct operation for differential input signal
voltages ranging between 200 mV and 6V in magnitude.
3) The maximum voltage present between either receiver
input terminal and receiver circuit ground shall not exceed 10V (3V signal plus 7V common-mode) in magnitude nor cause the receiver to operationally fail. Additionally, the receiver shall tolerate a maximum differential signal of 12V applied across its input terminals without being
damaged.
4) The total load including up to 10 receivers shall not have
a resistance greater than 900 for balanced, and 4000 for
unbalanced at its input points and shall not require a differential input voltage of greater than 200 mV for all receivers to assume the correct binary state.
5) Fail-safe operation per RS-423 Sec 4.2.5 states that other standards and specifications using the electrical characteristics of the unbalanced interface circuit may require
that specific interchange leads be made fail-safe to certain fault conditions. Where fail-safe operation is required
by such referencing standards and specifications, provi-

1-310

pression of near end cross-talk to adjacent channels in the
interconnect cable. Figure 11 is the typical rise time vs external capacitor used for wave shaping.
The OS3691 configured for RS-422 is connected Vee = 5V
VEE = av, and configured for RS-423 connected Vee = 5V
VEE = -5V. For applications outside RS-422 conditions
and for greater cable lengths the OS1691 IOS3691 may be
connected with a Vee of 5 volts and VEE of -5 volts. This
will create an output which is symmetrical about ground,
similar to Mil Standard 188-114.

TIME

When configured as balanced drivers (Figure 8), each of the
drivers is equipped with an independent TRI-STATE® control pin. By use of this pin it is possible to force the driver
into its high impedance mode for applications using party
line techniques.

TL/F/5B54-11

FIGURE 7. Signal Rise Time on
Transmission Line vs Line Length

If the common-mode voltage, between driver 1 and all other
drivers in the circuit, is small then several line drivers (and
receivers) may be incorporated into the system. However, if
the common-mode voltage exceeds the TRI-STATE common-mode range of any driver, then the signal will become
attenuated by that driver to the extent the common-mode
voltage exceeds its common-mode range (see Figure 12,
top waveform).

DS1691A,DS78LS120
The Driver
The OS1691A10S3691 are low power Schottky TTL line
drivers designed to meet the above listed requirements of
EIA standard RS-422 and RS-423. They feature 4 buffered
outputs with high source and sink current capability with internal short circuit protection. The OS1691 IOS3691 employ
a mode selection pin which allows the circuit to become
either a pair of balanced drivers (Figure 8) or 4 independent
unbalanced drivers (Figure 9). When configured for unbalanced operation (Figure 10) a rise time control pin allows
the use of an external capacitor to control rise time for sup-

It is important then to select a driver with a common-mode
range equal to or larger than the common-mode voltage
requirement of the system. In the case of RS-422 and RS423 the minimum common-mode range would be ± 7V. The
OS1692/0S3692 driver is tested to a common-mode range
of ± 1av and will operate within the requirements of such a
system (see Figure 12, bottom waveform).

5V

J

\'-----,

15
14

DISABLE

J
l

L
I

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DISABLE

11
D

10
MODE
OV
TL/F/5B54-12

FIGURE 8. DS3691 Connected for Balanced Mode Operation

1-311

III

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INPUT VOLTAGE

c(

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l-

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l-

w

w

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---

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C

(,,)

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INPUT VOLTAGE

TL/F/5B54-26

0

INPUT VOLTAGE
TL/F/5854-27

FIGURE 17. Fail-Safe Using the DS88LS120 Threshold Offset for Balanced Lines

1-316

TL/F/5B54-2B

»
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Summary of Electrical
Characteristics of Some
Well Known Digital
Interface Standards

National Semiconductor
Application Note 216
Don Tarver

FOREWORD

have become "defacto" standards because of the desire to
provide/use equipment which interconnect to them.

Not the least of the problems associated with the design or
use of data processing equipment is the problem of providing for or, actually interconnecting the differing types and
models of equipment to form specific processing systems.
The magnitude of the problem becomes apparent when one
realizes that every aspect of the electrical, mechanical and
architectural format must be specified. The most common
of the basic decisions confronting the engineer include:
• Type of logic (negative or positive)
• Threshold levels
• Noise immunity
• Form of transmission
• Balanced/unbalanced, terminated/unterminated
• Unidirectionallbidirectional, simplex/multiplexed
• Type of transmission line
• Connector type and pin out
• Bit or byte oriented
• Baud rate
If each make and/or model of equipment presented a
unique interface at its I/O ports, "interface" engineering
would become a major expenditure associated with the use
of data processing equipment.
Fortunately, this is not the case as various interested or
cognizant groups have analyzed specific recurring interface
areas and recommended "official" standards around which
common 110 ports could be structured. Also, the I/O specifications of some equipment with widespread popularity
such as the IBM 360/370 computer and DEC minicomputer

N
......

Q)

Compliance with either the "official" or "defacto" standards
on the part of equipment manufacturers is voluntary. However, it is obvious that much can be gained and little lost by
providing equipment that offers either the "official" or "defacto" standard I/O ports.
As can be imagined, the entire subject of interface in data
processing systems is complicated and confusing, particularly to those not intimately involved in the day-to-day aspects of interface engineering or management. However, at
the component level the questions simplify to knowing what
standards apply and what circuits or components are available to meet the standards.
This application note summarizes the important electrical
characteristics of the most commonly accepted interface
standards and offers recommendations on how to use National Semiconductor integrated circuits to meet those standards.
1.0 INTRODUCTION
The interface standards covered in this application note are
listed in Table I. The body of the text expands upon the
scope and application of each listed standard and summarizes important electrical parameters.
Table II summarizes the National Semiconductor IC's applicable to each standard.

II

TABLE I. Common Line Driver/Receiver Interface Standards Summary
Interface Area
Data Communications
Equipment (DCE*)
to Data Terminal
Equipment (DTE)

Application
U.S.A. Industrial

Standard

Origin

Comments

RS-232C
RS-422
RS-423

EIA
EIA
EIA

RS-449

EIA

RS-485

EIA

International

CCITTVol. VIII V. 24
CCITT No. 97 X. 26
CCITT No. 97 X. 27

International Telephone and Telegraph
Consultative
Committee

Similar to RS-232
Similar to RS-423
Similar to RS-422

U.S.A. Military

MIL-STD-188C
MIL-STD-188-114
MIL-STD-1397
(NTDS-Slow)
MIL-STD-1397
(NTDS-Fast)

0.0.0.
0.0.0.
Navy

Unbalanced, Short Lines
Similar to RS-422, RS-423
42k bits/sec.

Navy

250k bits/sec

GSA
GSA

Identical to RS-423
Identical to RS-422

U.S. Government,
Non-Military

FED-STD-1020
FED-STD-1030

1-317

Unbalanced, Short Lines
Balanced, Long Lines
Unbalanced,
RS-232 Up-Grade
System Standard Covering
Use of RS-422, RS-423
Balanced,
Long Line Multipoint

TABLE I. Common Line Driver/Receiver Interface Standards Summary (Continued)
Interface Area

Application

Computer to Peripheral

Standard

IBM 360/370

Unbalanced Bus

DEC

Unbalanced Bus

NIM (AEC)

OTL/TTL Logic Levels

Laboratory Instrumentation

CAMAC
(IEEE Std. 583-1975)
488

IEEE

Unbalanced Bus

Microprocessor Circuits

Microbus™

National
Semiconductor

Short Line; 8-Bit Parallel,
Digital Transmission

Nuclear Instrumentation

Microprocessor to
Interface Devices

Comments

IBM

DEC Mini-Computer
Instrument to Computer

Origin

System 360/370
Channel I/O
DEC Unibus®

Facsimile Equipment to OTE

Facsimile Transmission

RS-357

EIA

Incorporates RS-232

Automatic Calling
Equipment to OTE

Impulse Dialing and
Multi-Tone Keying

RS-366

EIA

Incorporates RS-232

Numerically Controlled
Equipment to OTE

Numerically Controlled
Equipment

RS-408

EIA

Short Lines «4 Ft.)

• Changed to "Data Circuit-Terminating Equipment"

TABLE II. Line Driver/Receiver Integrated Circuit Selection Guide for Digital Interface Standards
Part Number

Standard
Designation

Line Driver
O°C to +70°C

Line Receiver
- 55°C to + 125°C

0° to + 70°C

- 55°C to + 125°C

Not Applicable
Not Applicable

OS1489 (A)
OS75154

Not Applicable
Not Applicable

U.S. INDUSTRIAL STANDARDS
RS-232C

OS1488
OS75150

RS-357

See RS-232C

RS-366

See RS-232C

RS-408

OS75453
OS75454

OS55454
OS55454

OS7820A
OS75115

OS7820A
OS55115

RS-422

OS3691
OS26LS31C
OS3487

OS1691A
OS26LS31M
OS3587

OS88LS120
OS26LS32C
OS3486
OS26LS33C
OS88C20
OS88C120

OS78LS120
OS26LS32M

OS88LS120
OS88C20
OS88C120

OS78LS120
OS78C20
OS78C120

OS1691A
OS1692

RS-423

OS3691
OS3692

RS-449

See RS-422, RS-423

RS-485
Transceivers

OS3695
OS3696
OS3697
OS3698
OS75176A

OS3695
OS3696
OS3697
OS3698
OS75176A

IEEE 488

OS3666
OS75160A
OS75161A
OS75162A

OS3666
OS75160A
OS75161A
OS75162A

CAMAC

See RS-232C, RS-422, RS-423 or IEEE 488

IBM 360/370
I/O Port

OS75123

Not Applicable

1-318

OS75124

OS26LS33M
OS78C20
OS78C120

Not Applicable

TABLE II. Line Driver/Receiver Integrated Circuit Selection Guide for Digital Interface Standards (Continued)

.

»
z

I\)

......

Part Number

Standard
Designation

0')

Line Receiver

Line Driver
O°C to +70°C

-55°C to + 125°C

0° to +70°C

-55°C to + 125°C

DEC Unibus®

OS36147
OS8641
Transceiver

OS16147
OS7641
Transceiver

OS8640
OS8641
Transceiver

OS7640
OS7641
Transceiver

Microbus™

OS3628
OP8228
OP8216
OP8212
OP8340B
Transceiver

OS1628
OP8228M
OP8216M
OP8212M
OP8304B
Transceiver

GOVERNMENT STANDARDS
MIL-STO-188C

OS3692

OS1692

OS88LS120

OS78LS120

MIL-STO-188-114

OS3692

OS1692

OS88LS120

OS78LS120

FEO-STO-1020

See RS-423

FEO-STO-1030

See RS-422

MIL-STO-1397
(NTOS-Slow)

Use Discrete Components and/or Comparators

MIL-STO-1397
(NTOS-Fast)

Use Discrete Components and/or Comparators

INTERNATIONAL STANDARDS (CCITT)
1969 White Book
Vol. VIII, V. 24

See RS-232C

Circular No. 97, X. 26

See RS-422

Circular No. 97, X. 27

See RS-423

2.0 (DTE) (DCE)

dard, it provides for one-way/non-reversible, single ended
(unbalanced) non terminated line, serial digital data transmission. Figure 1 shown below illustrates a typical application. See Table III for Specification Summary.

Data terminal equipment (OTE) to data communications
equipment (OCE) interface standards
2.1 Application

III

Important features are:

The OTE/OCE standards cover the electrical, mechanical
and functional interface between or among terminals (i.e.,
teletypewriters, CRT's etc.) and communications equipment
(i.e., modems, cryptographics sets, etc.).

• Positive logic (± 5V min to ± 15V max)
• Fault protection
• Slew-rate control
• 50 feet recommended cable length

2.2 U.S. Industrial DTE/DCE Standards

• 20k bits per second data rate

2.2.1 EIA RS-232
RS-232C is the oldest and most widely known OTE/OCE
interface standard. Viewed by many as a complete stan-

I>--J

--INTERFACE -

DA~~o-

~

V
-=:;-

Rm2C

I

)~
~,

»

»

~

DATA
OUT

V
-=:;TL/F/5855-1

FIGURE 1. EIA RS-232C Application

1-319

.

---+-..- V \..jI\·,..-----1~~

TRI·STATE®

0---

INPUT

o--4~

TL/F/5855-6

FIGURE 6. MIL-STD-188-114 (Balanced Applications)
2.4.2 MI L-STD-188-114 Balanced

3.0 COMPUTER TO PERIPHERAL INTERFACE
STANDARDS

This standard is similar to RS-422 with the exception that
the driver offset voltage level is limited to ±O.4V vs ±3V
allowed in RS-422.

To date, the only standards dealing with the interface between processors and other equipment are the "defacto"
standards in the form of specifications issued by IBM and
DEC covering the models 360/370 I/O ports and the Unibus, respectively.

2.4.3 MIL-STD-188-114 Unbalanced.
This standard is similar to RS-423 with the exception that
loaded circuit driver output voltage at RL = 450D. must be
90% of the open circuit output voltage vs ± 2V at Rs =
100D. for RS-422.

3.1 GA-22-6974-0
IBM specification GA-22-6974-0 covers the electrical characteristics, the format of information and the control sequences of the data transmitted between 360/370's and up
to 10 1/0 ports.
The interface is an unbalanced bus using 95D., terminated,
coax cables. Devices connected to the bus should feature
short-circuit protection, hysteresis in the receivers, and
open-emitter drivers. Careful attention should be paid to line
lengths and quality in order to limit cable noise to less than
400 mV.

2.4.4 MIL-STD-1397 (Slow and Fast)
2.5 FED-STD-1020/1030
U.S. Government (non-military) standards FED-STD-1020
and 1030 are identical without exception to EIA RS-423 and
RS-422, respectively.

TABLE VIII. MIL-STD-1397 Specification Summary

Symbol

Parameter

Conditions

Comparison Limits
(MIL-STD)
1397
(Slow)

1397
(Fast)

Data Transmission Rate

Units

42

250

k Bits/Sec

VOH
VOL

Driver Output Voltage

±1.5
-10to -15.5

0
-3

V
V

IOH
IOL

Driver Output Current

~-4

RS

Driver Power OFF Impedance

mA
mA

1
Receiver Input Voltage

~100

Fail-Safe Open Circuit

~4.5
~

1-323

-7.5

kD.
~

-1.1

~-1.9

V
V

CD
'I"'"

r------,

N

Z•

<

c

J

F

I
I

I "

I

)-_"--I""""4~_t:l,...95-C..,D~:.'~X~C-AB-lEi::f_-. . .----J1L--.J"<0I
I 95 ••~ , " 1
• 95
I
·
I

D
E

r----------,

II

AB,!?

r---

I
-

L _ _ I~S~3 _ _ .J

""'""-

~

~

ff
""

_

I

I
I

~I--...;S;.;.T;.;.;RD;.;;B.;;.E_ _..I

~

I

A

I

B

:

I
I

1__

L _ _ _ _ 1.!!.ES!!!,!4 _ _ _ _ .J

TL/F/5855-7

FIGURE 7. IBM 3601370 I/O Application
TABLE IX. IBM 360/370 Specification Summary
Symbol

IBM 360/370

Conditions

Parameter

Typ

Min
VOH
VOH
VOH
VOL

Driver Output Voltage

10H
10H
10H
10L

Units
Max
7
5.85

= 123 mA
= 30/LA
= 59.3 mA

3.11
0.15

= - 240 /LA

Receiver Input Threshold
Voltage

1.7

V
V

-0.42

mA
mA

-0.15
-0.15

7
6

V
V

-0.15
-0.15

7
6

V
V

0.7

Receiver Input Current

VIN = 3.11V
VIN = 0.15V

0.24

Receiver Input Voltage Range
Power ON
Power OFF
Power ON
Power OFF
Receiver Input Impedance

0.15V:O; VIN

Receiver Input Current

VIN = 0.15V

Zo

CABLE Impedance

RO

CABLE Termination
Line Length (Specified as
Noise on Signal and Ground Lines)

:0;

n

7400

3.9V

PD ~ 390mW

240

/LA

83

101

90

100
400

n
n

5V
()

~)

~~ 180

:= 180

\-~/
.: 390

-:::-

"

T

T

I ' ' II ' '
DRIVER

'-,
"

-.

T
LINE
DRIVER

RECEIVER

T

I

1-324

,IN,

'-,
"

RECEIVER

FIGURE 8. DEC Unibus Application

V
V
V
V

I

:

•~ 390
-:::-

TL/F/5855-8

mV

l>
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TABLE X. DEC Unibus Specification Summary
Symbol

Parameter

DEC Unibus

Conditions

Typ

Min
VOL
Vo

Driver Output Voltage

VIH
VIL

Receiver Input Voltage

IIH
IlL

Receiver Input Current

Units
Max

10L = 50 mA
Absolute Maximum

0.7
7

V
V

1.3

V
V

100
100

,..,A
,..,A

1.7
VIN = 4V
VIN = 4V Power OFF

3.2 DEC UNIBUS

4.3CAMAC

Another example of an unofficial industry standard is the
interface to a number of DEC minicomputers. This interface,
configured as a 1200. double-terminated data bus is given
the name Unibus. Devices connected to the bus should feature hysteresis in the receivers and open-collector driver
outputs. Cable noise should be held to less than 600 mY.

The CAMAC system is the result of efforts by those in the
nuclear physics community to standardize the interface between laboratory instruments and computers before the introduction of IEEE 488.

4.0 INSTRUMENTATION TO COMPUTER INTERFACE
STANDARDS

The electrical requirements of the interfaces are compatible
with DTL and TTL logic levels.

4.1 INTRODUCTION

5.0 MICROPROCESSOR SYSTEMS INTERFACE
STANDARDS

It allows either serial or parallel interconnection of instruments via a "crate" controller.

The problem of linking instrumentation to processors to
handle real-time test and measurement problems was largeIy a custom interface problem. Each combination of instruments demanded unique interfaces, thus inhibiting the wide
spread usage of small processors to day-to-day test, measurement and control applications.

5.1 Microprocessor Systems
Microprocessor systems are bus organized systems with
two types of bus requirements:
a) Minimal system: for data transfer over short distances
(usually on 1 PC board), and,

Two groups addressed the problem for specific environments. The results are:

b) Expanded system: for data transfer to extend the memory or computational capabilities of the system.

a) IEEE 488 bus standard based upon proposals made by
HP, and

5.2 Minimal Systems and Microbus

b) The CAMAC system pioneered by the nuclear physics
community.

Microbus considers the interface between MOSILSI microprocessors and interfacing devices in close physical proximity which communicate over 8-bit parallel unified bus systems. It specifies both the functional and electrical characteristics of the interface and is modeled after the 8060, 8080
and 8090 families of microprocessors as shown in Figures
10, 11 and 12.

4.2 IEEE 488

IEEE 488 covers the functional, mechanical and electrical
interface between laboratory instrumentation (Le., signal
generators, DPM's, counters, etc.) and processors such as
programmable calculators and minicomputers. Equipment
The electrical characteristics of Microbus are shown in Tawith IEEE 488 1/0 ports can be readily daisy chained in any
ble XII.
combination of up to 15 equipments (including processor)
spanning distances of up to 60 feet. 16 lines (3 handshake,
5 control and 8 data lines) are required.
TABLE XI. IEEE 488 Specification Summary
Symbol

Parameter

IEEE 488

Conditions
Min

VOH
VOL

Driver Output Voltage

10H = -5.2mA
10L = 48 mA

Driver Output Current
TRI-STATE®
Open Collector

Vo = 2AV
Vo = 5.25V

VIH
VIL

Receiver Input Voltage

OAV Hysteresis Recommended

IIH
IlL

Receiver Input Current

VIN = 2AV
VIN = OAV

Receiver Clamp Current

VIN = -1.5V

RL1
RL2

Termination Resistor

Vee = 5V (±5%)
V = Gnd

loz
10H

1-325

Typ

Units
Max

004

V
V

±40
250

,..,A
,..,A

0.8

V
V

40
-1.6

,..,A
mA

12

mA

204

2.0

2850
5890

3150
6510

N
.....
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N
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TABLE XII. Microbus Electrical Specification Summary
Receiver

oCt

Parameter

Symbol

Driver

0.8

0.6

2.0

2.0

V

10

10

pF

:?:2.4V

(At -100 J.1-A)

VOH

Hysteresis
(Recommended)

::;:O.4V

Output Voltage (At 1.6 mAl

VOL

Input Voltage

VIL

Units

Standard

VIH

V

Internal Capacitive Load at 25°C

15

tr

Rise Time (Maximum)

100

ns

tf

Fall Time (Maximum)

100

ns

"

,,~

:"

"

....

J"""

'''"
~

~
DEFINED:

::;;

~

l-

::;;

~

I-

::;;

~

l-

::;;

~ I-~

~

I-

~

l-

5V

::;;

~

~

I-

l-

3k

16 LlNES}--

....

IN"

OUT
~~
~~

~

$;

PORT A

15 PORTS

6.2k

~~

I

PORT "N"

":d=' GND
TL/F/5855-9

FIGURE 9. IEEE 488 Application

J2I"
.1

NADS

LOGIC

:

I CSi1.

1'r
LATCH

1'r

A

K.,

5V _

8060

~rc

CHIP SelECT :..::::.:....

AI5-AO

All-AO

DB1-DBO

MICROBUS

:•

r

J
~

,

.

~

~.
~.

lID

NRDS

WR

NWDS

b-

~DJ

TLIF/5855-10

FIGURE 10.8060 SC/MP II System Moldel
1-326

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rOl

MICROBUS

~.-.c:I

A15-AO

INS8D80A

H1
A

07-00

~

RR

..... 19

REMOTE RELEASE

RC

..... 20

REMOTE CONTROL

RY

..... 21

READY

RI·1

",,"22

RING INDICATOR 1

RI·2

23

RING INDICATOR 2

*"

*

...

lk-"

-A . . . .

~

~~

COMMUNICATIONS
CONTROL
CIRCUITRY

WHENEVER
RINGING IS
DETECTED

-'"

...

18 Vrms

CLOSES

.J:.
>40k-

-

FEMALE MALE
CONNECTOR

>40k

OPENTO ~
-TERMINATE
CALL
CLOSE FOR

J , AUTO ANSWER

...

....

'Must be closed or Data Set cannot be placed In data mode
oOReceive

Sensitivity

Source

ON

3V-25V

5V-25V

OFF

3V-25V

5V-25V

FIGURE 13. Functional and Electrical Characteristics RS-357
1-328

TL/F/S8SS-13

l>
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6.3 EIA RS-408

....

I\)

RS-408 recommends the standardization of the 2 interfaces
shown in Figure 14.

0')

The electrical characteristics of NCE to DTE interface are,
in summary, those of conventional TTL drivers (series 7400)
with:
VOL

s:

O.4Vat IOL = 48 mA

s:

VOH ~ 2.4V at IOH
CL

s:

-1.2 mA, and

2000 pF.

Short circuit protection should be provided.

SWITCHED DR DEDICATED,
COMMON CARRIER, OR
PRIVATE LINE TO DATA
SOURCE/SINK

(TYPICAllY A MODEM
IF INCLUDED IN
SYSTEM)

DATA
COMMUNICATIONS
EQUIPMENT

-

-

-

- ~ -

-

-

INTERFACE DEFINED BY RS·232C

DATA
TERMINAL
EQUIPMENT (DTE)

-

-

-

(TYPICALLY INCLUDES
SERIAL TO PARALLEL
CONVERTER, ETC.)

-I- TYPICALLY-INTERFACE DEFINED BYTHISSTANDARo
< 40 FEET
(TYPICAllY COULD
INCLUDE A SWITCH TO
SelECT EITHER LOCAL
TAPE READER DR DATA
TERMINAL EQUIPMENT)

NUMERICAL CONTROL
EQUIPMENT (NCE)

III

(TYPICAll Y A MACHINE
TOOL, DRAFTING TABLE,
ETC.)

CONTROLLED
EQUIPMENT

TL/F/5855-14

FIGURE 14. EIA RS-408lnterface Applications

1-329

CJ)

o

oo:::r
I

Z



L....----1---r>

r~DlTIONAL
RECEIVERS

(IF ANY)

TL/F/8579-1

FIGURE 1a. An RS-422 Configuration

RT

RT

120

120

OHMS

OHMS

TL/F/8579-2

FIGURE 1b. A Typical RS-485 Party-Line Configuration

1-330

»
The output in Figure 2a can be taken high until the emitterbase junction of 01 breaks down. Thereafter, the output will
be clamped to a zener voltage plus a base-collector diode
voltage above Vee; Vee could be zero if the device is powered off. If the output is taken below ground, it will cause the
substrate diode, DSUB, associated with 02 to turn on and
clamp the output voltage at a diode drop below ground. If a
disabled driver turns on and clamps the line, the signal put
out by the active driver will get clipped and distorted. It is
also possible for ground drops to cause dangerously large
substrate currents to flow and damage the devices as illustrated in Figure 2b. Figure 2b depicts two drivers A and B; it
shows the pull down transistors (02A and 02B) and their
associated substrate diodes (DSUB-A and DSUB-B) for the
two drivers A and B. Here driver A is ON in the low output
state; driver B is disabled, and therefore, should neither
source nor sink current. The ground of driver A is 3 volts
lower than that of driver B. Consequently, the substrate diode DSUB-B sees a forward bias voltage of about 2.7V (the
collector-emitter voltage of 02A will be about 0.3V), which
causes hundreds of milliamperes of current to flow out of it.

ceivers were intended for use in the configuration shown in
Figure la. The driver is at one end of the line; the termination resistor (equal to 100n) and up to 10 receivers reside at
the other end of the line. This approach works well in simplex (unidirectional) data transmission applications, but creates problems when data has to be transmitted back and
forth between several pieces of equipment. If several Data
Terminal Equipments (DTEs) have to communicate with one
another over long distances using RS-422 links, two such
balanced lines have to be established between each pair of
DTEs. The hardware cost associated with such a solution
would normally be unacceptable.
A party line is the most economical solution to the above
problem. RS-422 hardware could conceivably be used to
implement a party line if the driver is provided with
TRI-STATE® capability, but such an implementation would
be subjected to severe restrictions because of inadequacies
in the electrical characteristics of the driver. The biggest
problem is caused by ground voltage differences. The common mode voltage on a balanced line is established by the
enabled driver. The common mode voltage at the receiver is
the sum of the driver offset voltage and the ground voltage
difference between the driver and the receiver. In simplex
systems only the receiver need have a wide common mode
range. Receiver designs that provide a wide common mode
range are fairly straightforward. In a party-line network several hundred feet long, in which each piece of equipment is
earthed at a local ac outlet, the ground voltage difference
between two DTEs could be as much as a few volts. In such
a case both the receiver and the driver must have a wide
common mode range. Most RS-422 drivers are not designed to remain in the high impedance state over a wide
enough common mode range, to make them immune to
even small ground drops.
Classical line drivers are vulnerable to ground drops because of their output stage designs. A typical output stage is
shown in Figure 2a. Two such stages driven by complementary input signals, may be used to provide the complementary outputs of a differential line driver. Transistors 01 and 04
form a Darlington pull up for the totem pole output stage; 02
is the pull down transistor. The phase splitter 03 switches
current between the upper and lower transistors to obtain
the desired output state. DSUB is the diode formed by the
collector of 02 and the grounded substrate of the integrated
circuit. The output in Figure 2a can be put into the high
impedance state by pulling down the bases of transistors
03 and 04. Unfortunately, the high impedance state cannot
be maintained if the output is pulled above the power supply
voltage or below ground voltage. In party-line applications,
where ground voltage differences of a few volts will be common, it is essential that the drivers be able to hold the high
impedance state while their outputs are taken above Vee
and below ground.

z
.l:..

o

CD

III
TLIF/8579-3

FIGURE 2a. Driver Output Stage
(not RS-485)

1-331

.

0)

o

oo::t'

DRIVER A
ON lOW

Z

DRIVER B
OFT

~ TRANSMISSION

<

LINE

r--!-I- SUBSTRATE
CURRENT

I
I
I
I
__+-_-+I ____
t

ON--+-~

_~

1----1-- OFF

a2A

~;~

___ __
~

i

1- FROM
SUBSTRATE

~_~~~OFB

SUBSTRATE
OF A
GND A

------t,. VCNO = 3 V - - - - - -GN,.D B

SUBSTRATE
OF B
TL/F/6579-4

FIGURE 2b. Two DCEs Separated by a Ground Drop

I
I

I

Q"(";tI
I
I
I

I

~'(OFF)
I
I

GND A

\J

DRIVER A
ON HIGH

DRIVER B
ON lOW

TL/F/6579-5

FIGURE 2c. Bus Contention

Another problem is line contention, i.e. two drivers being
'ON' simultaneously. Even if the protocol does not allow two
drivers to be on at the same time, such a contingency could
arise as a result of a fault condition. A line contention situation, where two drivers are on at the same time, is illustrated
in Figure 2c. Here, drivers A and 8 are 'ON' simultaneously;
driver A is trying to force a high level on the line whereas
driver 8 is trying to force a low level. Transistors 01 A and
028 are 'ON' while transistors 02A and 018 are 'OFF'. As
a result, a large current is sourced by 01 A and sunk by
028; the magnitude of this current is limited only by the
parasitic resistances of the two devices and the line. The
problem is compounded by any ground drop that may exist
between the two contending drivers. This large contention
current can cause damage to one or both of the contending
drivers. Most RS-422 drivers are not designed to handle line
contention.

the more stringent hardware requirements of muti-point data
links.
THE RS-485 STANDARD

The RS-485 standard specifies the electrical characteristics
of drivers and receivers that could be used to implement a
balanced milti-point transmission line (party-line). A data exchange network using these devices will operate properly in
the presence of reasonable ground drops, withstand line
contention situations and carry 32 or more drivers and receivers on the line. The intended transmission medium is a
120f! twisted pair line terminated at both ends in its characteristic impedance. The drivers and receivers can be distributed between the termination resistors as shown in Figure
1b.

The effects of ground voltage differences are mitigated by
expanding the common mode voltage (VCM) range of the
driver and the receiver to -7V < VCM < + 12V. A driver
forced into the high impedance state, should be able to
have its output taken to any voltage in the common mode
range and still remain in the high impedance state, whether
powered on or powered off. The receiver should respond
properly to a 200 mV differential signal super-imposed on
any common mode voltage in this range. With a 5V power
supply, the common mode voltage range specified by RS485 has a 7V spread from either supply terminal. The system will therefore perform properly in the presence of
ground drops and longitudinally coupled extraneous noise,
provided that the sum of these is less than 7 volts.

A multi-point driver should also be capable of providing
more drive than a RS-422 driver. The RS-422 driver is only
required to drive one 100f! termination resistor, and ten receivers each with an input impedance no smaller than 4 kf!.
A party-line, however, would have to be terminated at both
ends; it should also be able to drive more devices to be
useful and economical.
Because of the above limitations, it is quite impractical to
use RS-22 hardware to interconnect systems on a partyline. Clearly, a new standard had to be generated to meet

1-332

The output drive capability of the driver and the input impedance of the receiver are increased to accommodate two
termination resistors and several devices (drivers, receivers
and transceivers) on the line. The RS-485 standard defines
a 'unit load' so that the load presented to the line by each
device can be expressed in terms of unit loads (a 12 k!1
resistor, with one end tied to any voltage between ground
and Vee/2, will satisfy the requirements of a unit load). It
was anticipated that most manufacturers would design their
drivers and receivers such that the combined load of one
receiver and one disabled driver would be less than one unit
load. This would require the RS-485 receiver to have three
times the input resistance of a RS-422 receiver. The required receiver sensitivity is ± 200 mV-the same as for RS422. The driver is required to provide at least 1.5V across its
outputs when tied to a terminated line populated with 32
transceivers. Although this output voltage is smaller than
the 2.0V specified for RS-422, a careful design of the driver,
with special regard to ac performance, can allow the user to
operate a multi-point network at data rates and distances
comparable to RS-422.

and skew. RS-485 limits the DC imbalance in the driver
output to ±0.2V i.e., 13% of worst-case signal amplitude. Usually, the greatest distortion is caused by offset
in the receiver threshold. In a long line in which a 1.5V
driver output signal amplitude is attenuated by the loop
resistance to about O.4V, a 200 mV offset in the receiver
threshold can cause severe pulse width distortion if the
rise time is comparable to the bit interval. For lines longer than about five hundred feet, the rise time would be
dominated by the line and not the driver. In short-haul
networks, the transient response of the driver can significantly affect signal distortion; a faster transient creates
less distortion and hence permits a smaller bit interval
and a higher baud rate. A rise time less than 20 ns will be
a good target spec., for it will permit a baud rate of 10
Meg over 50' of standard twisted pair wire with less than
5% distortion.
The driver should provide the above risetime and propagation delay numbers while driving a reasonable capacitance, say 100 pF from each output, in addition to the
maximum resistive load of 54!1. A properly terminated
transmission line appears purely resistive to the driver.
Most manufacturers take this into account and specify
their driver delays with 15 pF loads. However, if any disabled transceivers are situated close to the driver (such
that the round trip delay is less than the rise time), the
input capacitances of these transceivers will appear as
lumped circuit loads to the driver. The driver output rise
time will then be affected by all other devices in such
close proximity. In the case of high speed short-haul networks, where rise time and propagation delay are critical,
several devices could be clustered in a short span. In
such an instance, specifying propagation delays with
15 pF loads is quite meaningless. A 100 pF capacitive
load is more reasonable; even if we allocate a generous
20 pF per transceiver, it allows up to six transceivers to
be clustered together in an eight foot span (the eight foot
span is the approximate round trip distance travelled by
the wavefront in one rise time of 20 ns).

RS-485 has additional specifications to guarantee device
safety in the event of line contention or short circuits. An
enabled driver whose output is directly shorted to any voltage in the common mode range, is required to limit its current output to ± 250 mA. Even with such a current limit, it is
possible for a device to dissipate as much as 3 Watts (if the
device draws 250 mA while shorted to 12 volts). Power dissipation of such a magnitude will damage most ICs; therefore, the standard requires that manufacturers include some
additional safeguard(s) to protect the devices in such situations.
The ± 250 mA current limit also serves another purpose. If a
contending driver is abruptly turned off, a voltage transient,
of magnitude IcZ/2, is reflected along the line as the line
discharges its'stored energy (Ie is the contention current
and Z is the characteristic impedance of the line). This voltage transient must be small enough to avoid breaking down
the output transistors of the drivers on the line. If the contention current is limited to 250 mA, the magnitude of this
voltage transient, on a 120!1 line, is limited to 15V, a value
that is a good compromise between transistor breakdown
voltage and speed.

(3) Skew: The ideal differential driver will have the following
waveform characteristics: the propagation delay times
from the input to the high and low output states will be
equal; the rise and fall times of the complementary outputs will be equal and the output waveforms will be perfectly symmetrical.

AC PERFORMANCE
To achieve reliable transmission at high data rates over long
distances, the driver should have optimum ac characteristics. The response should be fast and the output transients
sharp and symmetrical.

If the propagation delay to the low output state is different from the propagation delay to the high output state,
there is said to be 'propagation skew' between output
states. If a square wave input is fed into a driver with
such skew, the output will be distorted in that it will no
longer have a 50% duty cycle.

(1) Propagation Delay: The propagation delay through the
driver should be small compared to the bit interval so
that the data stream does not encounter a bottle-neck at
the driver. If the propagation delay is comparable to the
bit interval, the driver will not have time to reach the full
voltage swing it is capable of. In lines a few hundred feet
long, the line delay would impose greater limits on data
throughput than the driver propagation delay. However,
a fast driver would be desirable for short haul networks
such as those in automobile vehicles or disc drives; in
the latter case high data throughput would be essential.
Driver propagation delays less than 20 ns would be very
good for a wide range of applications.

If the mid-points of the waveforms from the two complementary driver outputs are not identical, there is said to
be SKEW between the complementary outputs. This
type of skew is undesirable because it impairs the noise
immunity of the system and increases the amount of
electromagnetic emission.

Figure 3a shows the differential signal from a driver that
has no skew. Figure 3b shows the case when there is 80
ns of skew. The first signal makes its transition uniformly
and passes rapidly through OV. The second waveform
flattens out for tens of nanoseconds near OV. Unfortunately, this flat region occurs near the receiver threshold.
A common mode noise spike hitting the inputs of a
slightly unbalanced receiver would create a small differential noise pulse at the receiver inputs. If this noise

(2) Transition Time: For distortion free data transmission,
the signal at the farthest receiver must have rise and fall
times much smaller than the bit interval. Signal distortion
results from driver imbalance, receiver threshold offset

1-333

»z

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.

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r---------------------------------------------------------------------------------------,

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z



Low Power RS-232C Driver
and Receiver in CMOS

National Semiconductor
Application Note 438
Gordon W. Campbell

This article sets out to describe the new innovative low power CMOS RS-232C driver and receiver IC's introduced by
National Semiconductor with particular reference to the EIA
RS-232C standard. Comparison will also be made with existing bipolar driver and receiver circuits.

THE DRIVER

The DS14C88 and DS14C89A are monolithic MOS circuits
utilizing a standard CMOS process. Important features are a
wide operating voltage range (4.5V-12.6V), together with
ESD and latch up protection and proven reliability.
The Electronics Industries Association released Data Terminal Equipment (DTE) to Data Communications Equipment
(DCE) interface standards to cover the electrical, mechanical and functional interface between/among terminals (Le.
teletypewriters, CRT's etc.) and communications equipment
(Le. modems, cryptographic sets etc.).
The EIA RS-232C is the oldest and most widely known
DTE/DCE standard. Its European version is CCITT V.24
specification. It provides for one-way/non-reversible, single
ended (unbalanced) non-terminated line, serial digital data
transmission.
The DS14C88 quad CMOS driver and its companion circuit,
the DS14C89A quad CMOS receiver, combine to provide an
efficient low power system for RS-232C or CCITT V.24 applications.

DATAt:~I'

RS232C
INTERFACE

IN

~

).~I

DATA
OUT

).
TL/F/8681-1

FIGURE 1_ EIA RS-232C Application

~~

The DS14C88 quad CMOS line driver is a pin replacement
of the existing bipolar circuit DS1488/MC1488.
The DS14C88 is fabricated in CMOS technology and therefore has an inherent advantage over the bipolar DS1488/
MC1488 line driver in terms of current consumption. Under
worst case static conditions, the OS 14C88 is a miser when it
comes to current consumption. In comparison with the
DS1488/MC1488 line driver, a current consumption reduction to 500 ,..,A max versus 25 mA can be achieved.
The RS-232C specification states that the required driver
output voltage is defined as being between + 5V and + 15V
and is positive for a logic "0" (+ 5V to + 15V) and negative
for a logic "1" (-5V to -15V). These voltage levels are
defined when driver is loaded (30000. < RL < 7000n). The
DS14C88 meets this voltage requirement by converting HC
or TTL/LSTTL levels into RS-232C levels through one
stage of inversion.
In applications where strict compliance to RS-232C voltage
levels is not essential, a ± 5V power supply to the driver
may be used. The output voltage of the DS14C88 will be
high enough to be recognized by either the 1489 or 14C89A
receiver as valid data.
The RS-232C specification further states that, during transitions, the driver output slew rate must not exceed 30V /,..,s.
The inherent slew rate of the equivalent bipolar circuit
DS14C88/MC1488 is much too fast and requires the connection of one external capacitor (330-400 pF) to each
driver output in order to limit the slew rate to the specified
value. However, the DS14C88 does not require any external
components. The DS14C88 has a novel feature in that
unique internal slew rate control circuitry has been incorporated which eliminates the need for external capacitors; to
be precise, a saving of four capacitors per package. The
14C88 minimizes RFI and transition noise spikes by typically
setting the slew rate at 5V -6V /,..,s. This will enable optimum
noise performance, but will restrict data rates to below 40k
baud.
The DS14C88 can also withstand an accidental short circuit
from a conductor in the interconnecting cable to anyone of
four outputs in a package without sustaining damage to itself or its associated equipment.

INPUT 1

OUTPUT
DRIVER
>C~""-OUTPUT

INPUT 2

LEVEL
SHIFTER

('/4 circuit shown)

SLEW RATE
CONTROL

FIGURE 2. DS14C88 Line Driver Block Diagram
1-337

TL/F/8681-2

~

r---------------------------------------------------------------------~

"'II:t'

THE RECEIVER

Iv-_.....~
INPUT
RESISTOR

~

0.01

For example, Figure 5 shows a small CMOS system utilizing
a CMOS NSC800 microprocessor, NSC858 CMOS UART,
CMOS RAM/ROM, and a clock timer. This system runs off a
9V battery so a DC-DC converter is used to generate -9V
for the RS-232 interface. In this design a standard DC-DC
convert IC is used to generate a - 9V supply from the single
+ 9V battery.

OUTPUT

As a second example, a "cheater" RS-232 interface is
sometimes implemented. This interface is compatible with
the current RS-232 driver/receiver products, but rather than
using a ± (9-15)V supply, a ± 5V supply is used. The drivers will not meet the RS-232 output voltage level specifications, but will correctly drive either the CMOS or bipolar receivers. The DC-DC converter circuit in Figure 5 may be
used to implement this. While for non-portable applications
this can be done with the old bipolar 1488/89s, the DC-DC

(% circuit shown)
TL/F/8681-3
FIGURE 3. DS14C89A Line Receiver Block Diagram

1-338

converter is somewhat simpler with the CMOS parts due to
the much reduced current consumption.

with a total power of 8 watts when using the bipolar devices.
The CMOS devices need only 400 mW.

The RS-232 driver/receivers are also useful in non-power
sensitive mUlti-user computers. Imagine a 16 terminal cluster controller for a multi-user computer system, Figure 6.
This controller would require 16 drivers and 16 receivers

Also proper noise rejection for receivers and slew rate limiting for the driver would require 128 capacitors for the bipolar
parts, but they are unnecessary in the CMOS implementation.

+9V

,1- _____ ,
REQUEST TO SEND
DATA TERI.4INAL READY
TRANSI.4IT DATA
NSCSOO
SOCSS

ADO-AD7
+5V

NC

;-'----- ..
DATA CARRIER DETECT

CI.40S RAI.4 -- 6264

NC

(SK x 8)

CLEAR TO SEND

CI.40S ROI.4 -- 27C64
8K x 8

r-~~------------

___

NC
DATA SET READY

~+9V

NC
RECEIVE DATA

+5V

DSI4CS9A

+9V TO -9V DC-DC CONVERTER
+9Vo--+------------~------------------~---O

+9: --

--I

1 - -...1--....-:--0 -9V

TL/F/8681-5

FIGURE 5. Typical portable system application using CMOS ,...P, ROM, RAM, and UART_
RS-232 Interface Is shown using 7660 supply inverter and CMOS Receiver/Driver.

1-339

BIPOLAR
.... --------OS1488

OS14C88

mn

\

......

"-....::.;,,;...

CMOS
--------.,

\
\

\
\

OS1489

~

OS14C89A

\

\

TERMINAL
CLUSTER
TO HOST
SYSTEM

CONTROLLER

TL/F/B6Bl-6

FIGURE 6. A multi-terminal application showing a comparison of Bipolar vs CMOS solutions.

Lit # 100438

1-340

High Speed, Low Skew
RS-422 Drivers and
Receivers Solve Critical
System Timing Problems

National Semiconductor
Application Note 457
Toan Tran
Larry Kendall

In system design, due to the distributed intelligence ability of
the microprocessor, it is a common practice to have the
peripheral circuits physically separated from the host processor with data communications being handled over cables.
Usually, these cables are measured in hundreds or thousands of feet. Signals transmitted on these lines (or cables)
are exposed to electrical noise sources which may require
large noise immunity. The requirements for transmission
lines and noise immunity are covered in E.I.A. standard
RS-422.

There are three major controlling factors in balanced voltage digital interface:

The object of this application note is to describe the design
requirement of RS-422 standard and to show that National's
DS8921, DS8922 and DS8923 Differential Driver and Receiver pair meet all of those requirements. Special circuit
design techniques are used to achieve small skew on complementary signals of the driver outputs. In fact, these devices are designed specifically for applications which must
meet stringent timing constraints including the ESDI Disk
Drive standard. Additionally, the DS8921 series meet the
requirement of ST506 and ST412HP standards.

1. The cable length
2. The modulation rate
3. The characteristics of the Driver and Receiver
CABLE LENGTH
There is no maximum cable length specified in the RS-422
standard. Guidelines are given with respect to conservative
operating distances as a function of modulation rate. Figure
2 below is the guideline provided by RS-422 for data modulation rate versus cable length.

10k~1I

g
~

w
co

-'

BALANCED VOLTAGE DIGITAL INTERFACE CIRCUITS
(RS-422) REQUIREMENT
Balanced circuits are normally used in data, timing, or control applications where the data signaling rate approaches
speeds of 10 Mbitls. In addition, balanced data transmission techniques should be used whenever the following
conditions exist:

2. The interconnecting cable is exposed to a noise source
which may cause a voltage sufficient to indicate a change
of binary state at the load.

lk

::

;3

1. The interconnecting cable is too long for effective unbalanced operation.

4k~

100
40

lk

10k

lOOk

1M

10M

DATA MODULATION RATE (BAUDS)
TLIF/BB37-2

FIGURE 2. Data Modulation Rate vs Cable Length
The curve is based on empirical data using a 24 AWG, copper conductor, twisted pair cable terminated for worst case
in a 100n load, with rise and fall time equal or less than one
half unit interval at the applied modulation rate.

Figure 1 below is a balanced circuit connection.

Even though the maximum cable length between driver and
load is a function of data signaling rate, it is also influenced
by the tolerable signal distortion, the amount of longitudinally coupled noise and ground potential difference introduced
between the generator and load circuit grounds.

Legend:

N, S' = Load Interface

Rt

= Optional cable transmission resistance/receiver input impedance.
= Ground potential difference
A, S = Driver interface

C = Driver circuit ground

VGROUND

C'

3. It is necessary to minimize interference with other signals.

TL/F/BB37-1

= Load circuit ground

FIGURE 1. RS-422 Balanced Digital Interface Circuit

1-341

III

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r---------------------------------------------------------------------------------------,
as the algebraic mean of the 2 voltages appearing at the
receiver input terminals with respect to the receiver circuit
ground. This allows for operations where there are
ground differences caused by IR drop and noise of up to
±7V.

MODULATION RATE
The balanced (or differential) voltage mode interface will
normally be utilized on data, timing or control circuits operating at up to 10 Mbauds. The voltage digital interface devices
meeting the electrical characteristics of this standard need
not meet the entire modulation range specified. They may
be designed to operate over narrower ranges to more economically satisfy specific applications, particularly at the
lower modulation rates. The OS8921 family of devices
meets or exceeds all of the recommended RS-422 performance specifications.

2. The receiver shall maintain correct operation for a differential input signal rang\ng between 200 mV and 6V in
magnitude.

A. The Driver

3. The maximum voltage between either receiver input terminal and receiver circuit ground shall not exceed 10V
(3V signal + 7V common-mode) in magnitude. Also, the
receiver shall tolerate a maximum differential signal of
12V applied across its input terminals without being damaged.

The balanced driver characteristics are specified in RS-422
as follows:

4. The total load (up to 10 receivers) shall not have a resistance more than 90n at its input points.

RS-422 CHARACTERISTICS

1. A driver circuit should result in a low impedance (100n or
less) balanced voltage source that will produce a differential voltage to the interconnecting cable in the range of
2V to 6V.

DS8921, DS8922 AND DS8923
The OS8921 is a single differential line driver and receiver
pair. Whereas, the OS8922 and OS8923 are dual differential
line driver and receiver pairs. The difference between the
OS8922 and OS8923 is in the TRI-STATE® control (Figure
3).

2. With a test load of 2 resistors, 50n each, connected in
series between the driver output terminals, the magnitude
of the differential voltage (VT) measured between the two
output terminals shall be equal to or greater than 2V, or
50% of the magnitude of Va, whichever is greater. For
the opposite binary state the polarity of VT is reversed
(VT).

These devices are designed to meet the full specifications
of RS-422. The driver features high source and sink current
capability.
The receiver will discriminate a ± 200 mV input signal over a
full common-mode range of ± 7V. Switching noise which
may occur on input signal can be eliminated by the built-in
hysteresis (50 mV typical, and 15 mV min.). An input failsafe circuit is provided so that if the receiver inputs are
open, the output will assume the logical one state.

3. During transitions of the driver output between alternating
binary states, the differential voltage measured across
100n load shall monotonically change between 0.1 and
0.9 of Vss within 0.1 of the unit interval or 20 ns, whichever is greater. Thereafter, the signal voltage shall not
change more than 10% of Vss from the steady state value until the binary state occurs.

These devices have power up/down circuitry that will TRISTATE the outputs and prevent erroneous glitches on the
transmission lines during system power up or down operation.

B. The Receiver
The electrical characteristics of the receiver are specified in
RS-422 as follows:

The most attractive feature of these devices is the small
skew beween the complementary outputs of the driver, typically about 0.5 ns. This small skew specification is often
necessary to meet tight system timing requirements.

1. The receiver shall not require a differential input voltage
more than 200 mV to correctly assume the intended binary state, over an entire common-mode voltage range of
. -7 to + 7V. The common-mode voltage (VCM) is defined
DS8921A

DS8923A

DS8922A

vee

RI+

ROI

RO

RI-

011

01

00+

vee

GNO

00TL/F/8837-3

rn;

EN2
GND
012

R02
TL/F/8837-4

FIGURE 3. DS8921A, DS8922A and DS8923A Connection Diagrams
1-342

TLIF/8837-5

>
Z
+ REFERENCE CLOCK

I

~

U1

0

&
NRZ t
WRITE
DATA 0

.......

0.5 '0.05 T-..J

0

rP'

0

WRITE
TIMING

I

0.2T~
WRITE t
CLOCK 0

~

0

0

0

0

0

ffi

I-- 0.2 T
I

READ t
CLOCK 0
READ
TIMING
NRZ t
READ
DATA 0

0

-j

I--TtO.t T
TL/F/6637-6

Note 1. All times in ns measured at 1/0 connector of the drive. T is the period of the clock Signals and is the inverse of the reference or read ciock frequency.
Note 2. Similar period symmetry shall be in ± 4 ns between any two adjacent cycles during reading and writing.
Note 3. Except during a head change or PLO synchronization the clock variances for spindle speed and circuit tolerances shall not vary more than -5.5% to
+ 5.0%. Phase relationship between reference clock and NRZ write data or write clock is not defined.
Note 4. The write ciock must be the same frequency as the drive supplied reference clock (i.e .• the write clock is the controller received and retransmitted drive
reference ciock).
Note 5. Reference clock is valid when read gate is inactive. Read ciock is valid when read gate is active and PLO synchronization has been established.

FIGURE 4. ESDI Timing Diagrams

DM7 4AS7 4 Switching Characteristics
over recommended operating free air temperature range (Note 1). All typical values are measured at Vee
Parameter

To

FMAX

TpHL
TpLH
TpHL

5V, TA

=

25°C.

DM74AS74
From

Conditions

Units
Min

TpLH

=

Preset
or clear
Clock

Q or
Q

Vee = 4.5V to 5.5V
RL = 500n
CL = 50 pF

Qor
Q

Note 1: See Section 1 for test waveforms and output load.

FIGURE 5. 1 ns Clock Skew

1-343

Typ

Max
MHz

105
3.3

7.5

ns

3.5

10.5

ns

3.5

8

ns

4.5

9

ns

III

~ r-----------------------------------------------------------------~
"'1::1"

ESDI ENHANCED SMALL DEVICE INTERFACE

Z•
c:(

The ESDI specification requires that the read and Reference Clock must meet the symmetry shown in Figure 4. This
necessitates the use of National's DS8921A122A123A series of transceivers.
All specifications are in % T, where T =

~, the ESDI specifi-

cation is assumed to be a 10 Mbits/second standard, T =
100 ns.
Given this, the negative pulse width measured at the drive
connector must equal 0.5T ± 0.05T (50 ns ± 5 ns). The best
available RS-422 driver, other than the DS8921 A Family, is
specified at ± 4 ns differential skew. If the clock is from a
high speed 74AS7 4 device, shown in Figure 5, it will have a
typical skew of 1 ns.
This combination of 4 ns + 1 ns uses all of the ESDI specified 5 ns and leaves no margin for noise. Use of the
DS8921A, 22A, or 23A, specified at ±2.75 ns max. differential skew would allow up to ± 2.25 ns for clock skew and
noise. This is as close a guarantee to meeting the ± 5 ns
spec. of ESDI, as is possible with todays advanced testing
systems.
One other consideration is the relationship between Read
Clock and Read Data. Figure 4 shows that the positive edge

of Read Clock must be 0.31T (31 ns) after the leading edge
of Read Data, and 0.31T (31 ns) before the trailing edge of
Read Data.
The Read Clock positive edges will be used to strobe Read
Data into the controller after both signals go through their
respective cable lines and receivers. Use of the DS8922A1
23A assures minimum skew between these two signals. Because both drivers, or both receivers, are on the same piece
of silicon an optimum match is achieved.
The above is applicable to an ESDI controller as well as the
Drive itself. The controller receives the Reference Clock
and uses both positive and negative edges to generate
WRITE CLOCK. The negative edge of WRITE CLOCK is
used to strobe out WRITE DATA and the positive edge will
strobe WRITE DATA into the Drive.
The WRITE CLOCK positive edge has to be centered within
WRITE DATA after it is received by the Drive. The transmitted WRITE CLOCK and WRITE DATA must be as closely
matched as possible.
National's DS8921 A, 22A, and DS8923A devices offer the
combination of tightly spec'd parameters and drivers and
receivers on one chip to meet various system timing constraints.

1-344

Section 2
Bus Transceivers

Section 2 Contents
Bus Transceivers-Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Transceivers-Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OP8303A 8-Bit TRI-STATE Bidirectional Transceiver (Inverting) ..........................
OP7304B/OP8304B 8-Bit TRI-STATE Bidirectional Transceiver (Non-Inverting). . . . . . . . . . . . .
OP8307 A 8-Bit TRI-STATE Bidirectional Transceiver (Inverting) ..........................
OP7308/0P8308 8-Bit TRI-STATE Bidirectional Transceiver (Non-Inverting) ...............
OS26S10C/OS26S10M/OS26S11C/OS26S11 M Quad Bus Transceiver.. ... ..............
OS3662 Quad High Speed Trapezoidal Bus Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-259 OS3662-The Bus Optimizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-337 Reducing Noise on Microcomputer Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS3667 TRI-STATE Bidirectional Transceiver................. ......... ................
OS3862 Octal High Speed Trapezoidal Bus Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS3890 BTL Octal Trapezoidal Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS3892 BTL Octal TRI-STATE Repeater. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS3898 BTL Octal Trapezoidal Repeater. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS3893A BTL Turbotransceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS3896/0S3897 Futurebus Trapezoidal Transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-458 The Proposed IEEE 896 Futurebus-A Solution to the Bus Driving Problem.........
AN-514 Timing Analysis of Synchronous and Asynchronous Buses .......................
OS75160A/OS75161 A/OS75162A IEEE-488 GPIB Transceivers. . . . . . . . . . . . . . . . . . . . . . . . .
OS7640/0S8640 Quad NOR Unified Bus Receiver .....................................
OS7641/0S8641 Quad Unified Bus Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS7833/0S8833/0S7835/0S8835 Quad TRI-STATE Bus Transceivers....... ...........
OS7834/0S8834/0S7839/0S8839 Quad TRI-STATE Bus Transceivers.. ................
OS7836/0S8836 Quad NOR Unified Bus Receiver.....................................
OS7837/0S8837 Hex United Bus Receiver............................................
OS7838/0S8838 Quad Unified Bus Transceiver..................... ...................
OS8T26A/OS8T26AM/OS8T28/0S8T28M 4-Bit Bidirectional Bus Transceivers. . . . . . . . . . ..

2-2

2-3
2-4
2-6
2-11
2-16
2-20
2-24
2-29
2-33
2-40
2-47
2-52
2-58
2-58
2-58
2-64
2-69
2-76
2-81
2-88
2-96
2-98
2-101
2-105
2-109
2-111
2-114
2-117

~National

~ Semiconductor
Bus Transceivers
A bus is a common communication medium, such as a cable or a printed circuit trace, that is time shared by several
elements of a system. Single-ended bus circuits are listed in
this section and these may be further categorized into opencollector circuits and TRI-STATE circuits.

noise filtering. Oevices such as National Semiconductor's
OS3662 and OS3862 Trapezoidal bus transceivers and
OS3896 and OS3897 Future Bus transceivers are specifically designed for reducing crosstalk and noise susceptibility
on high-speed buses.

When not transmitting, a bus driver should be capable of
presenting a high impedance output in order to allow other
drivers to freely use the bus. This is achieved by using either
an open-collector or TRI-STATE output.
Open-collector drivers may be connected in a wired-or configuration which is very useful for polling and bus arbitration.
These devices require pull-up resistors, which can also
serve as bus terminators.

FUTUREBUS TRANSCEIVERS
The OS3896 and OS3897 are the first two devices designed
for driving high-speed microcomputer backplane buses.
Both devices meet the proposed IEEE-P896 Future Bus
standard and incorporate low output capacitance « 5 pF)
with the ability to drive a bus with a loaded impedance of
less than 180. This excellent drive capability is achieved
while still maintaining high levels of noise immunity.

TRI-STATE drivers, on the other hand, do not require bus
termination for short bus runs on PC boards. In addition,
TRI-STATE devices provide improved rise time characteristics with low power dissipation. Hence, they are popular in
high-speed microcomputer systems.

POWER UP/DOWN GLITCH FREE PROTECTION
Powering a device up or down, or simply connecting or disconnecting a device from an active bus, has frequently presented the design engineer with the problem of invalid data
glitches being transmitted onto the bus. National Semiconductor is the industry leader in offering bus transceivers incorporating glitch-free power up/down protection. For more
detailed information on National Semiconductor's line of
bus transceivers, refer to the following Selection Guide and
application notes within this section.

A single-ended bus is highly susceptible to noise, including
ground noise and crosstalk. For this reason the bus should
not be extended beyond the subsystem's enclosure without
special care. Line lengths in excess of 10 feet are not recommended without the use of noise reduction techniques,
such as slew rate control, high receiver thresholds and

2-3

Bus Circuits
BUS CIRCUITS
Data bus circuits are not transmission line circuits in the normal interpretation where the transmission line is electrically long (1/4 wavelength) with respect to the baud rate. Like
unbalanced transmission lines, the data transmission is susceptible to common-mode noise, such as ground IR noise and induced reactive noise from crosstalk. A bus is a
communications method where many elements of a system time share the same signal (address or data) bus. A bus shouldn't extend out of its subsystem's electronic enclosure
without special care. Line length in excess of 10 feet is not recommended without slew rate control. Cables should be in the form of twisted pair or flat cable where a signal wire is
alternated with a ground wire.
OPEN-COLLECTOR BUS CIRCUITS
Device Number
Commercial
DOC to +7DoC

I\)

1:.

OM8131
OM8136
0526510
0526511
053662
053862
053890
053892
053893A
053896
053897
053898
0575450
0575451
0575452
0575453
0575454
058640
058641
058836
058837
058838

Bus Driver
Driver!
Circuits!
Receiver! Propagation VOL (V)! Propagation
Military
Package
Transceiver
Delay (ns)
Delay (ns)
- 55°C to + 125°C
IOl (rnA)

OM7131
OM7136
052651 OM
0526511M

0555451
0555452
0555453
0555454
057640
057641
057836
057837
057838

1
1
4
4
4
8
8
8
4
8
4
8
2
2
2
2
2
4
4
4
6
4

Receiver
Receiver
Transceiver
Transceiver
Transceiver
Transceiver
Driver
Receiver
Transceiver
Transceiver
Transceiver
Repeator
Driver
Driver
Driver
Driver
Driver
Receiver
Transceiver
Receiver
Receiver
Transceiver

10
10
30

0.8/100
0.8/100
0.9/100

30
30
10
10
40

Bus Receiver
Vil (V)!
III (JLA)

VIH (V)/
IIH (JLA)

2/50
0.95/50
2/50
0.95/50
1.75/-100 2.25/100
1.75/-100 2.25/100
1.50/400
1.9/100

Hysteresis
(V)
0.65
0.65

15
18
8

7

30
20
18
26
18
27

0.7/300
0.7/300
0.7/300
0.7/300
0.7/300

30

0.7/50

25

0.8/50

23
30
20
20
30

1.2/-50
1.8/50
1.2/-100
1.8/100
1.05/-50 2.65/50
1.05/-50 2.65/50
1.05/-100 2.65/100
-

--

1
1
1

Comments

Page
No.

6-Bit Bus Comparator
6-Bit Bus Comparator

Logic
Logic
2-24
2-24
Input to Bus is Non-Inverting
2-29
Trapezoidal Transceiver
2-52
Trapezoidal Transceiver
Futurebus Driver
2-58
2-58
Futurebus Receiver
TURBOTRAN5CEIVER
2-64
Futurebus Transceiver
2-69
Futurebus Transceiver
2-69
Futurebus Repeator
2-58
AND 5eparate Output Transistors 3-41
3-41
AND
3-41
NAND
3-41
OR
3-41
NOR
Quad NOR Receiver
2-96
2-98
Quad NOR Receiver
2-109
2-111
2-114

I

TRI-STATE® BUS CIRCUITS
Bus Driver
Device Number
Commercial
Military
DOC to +7DoC -55°C to + 125°C

I\)

DM74S240
DM74S241
DM74S940
DM74S941
DP8212

DM54S240
DM54S241
DM54S940
DM54S941
DP8212M

DP8216
DP8226
DP8228

I

Bus Receiver

Driver/
Circuits/
Package

Propagation
Propagation
VodV)/ VOH (V)/
Delay
Delay
Transceiver
IOL(mA) IOH (rnA)
Typ (ns)
Typ (ns)
Receiver/

VIL (V)/
IlL (,uA)

VIH (V)/ Hysteresis
(mV)
IIH (,uA)

4or8
4or8
8
8
8

Transceiver
Transceiver
Transceiver
Transceiver
Driver

4.5
6
4.5
6
20

0.55/64
0.55/64
0.55/64
0.55/64
0.45/15

2.4/-3
2.4/-3
2.4/-3
2.4/-3
3.6/-1

4.5
6
4.5
6

0.8/-400
0.8/-400
0.8/-400
0.8/-400

2/50
2/50
2/50
2/50

DP8216M
DP8226M
DP8228M

4
4
8

Transceiver
Transceiver
Transceiver

20
16
30

0.6/55
0.6/50
0.45/10

3.6/-1
3.6/-1
2.4/-1

15
15
20

0.95/-250
0.95/-250
0.8/-250

2/10
2/10
2/20

DP8238

DP8238M

8

Transceiver

30

0.45/10

2.4/-1

20

0.8/-250

2/20

DP8303A
DP8304B

DP7304B

8
8

Transceiver
Transceiver

10
10

0.5/50
0.5/50

3.6/-5
3.6/-5

10
15

0.8/-250
0.8/-250

2/80
2/80

8
8
4
8
8
8
8
4
4
4
4
4
4

Transceiver
Transceiver
Transceiver
Transceiver
Transceiver
Transceiver
Transceiver
Transceiver
Transceiver
Transceiver
Transceiver
Transceiver
Transceiver

10
11
8
20
20
20
20
14
17
14
14
14
14

0.5/50
0.5/50
0.5/50
0.5/48
0.5/48
0.5/48
0.5/48
0.5/48
0.5/48
0.5/50
0.5/50
0.5/50
0.5/50

3.6/-5
3.6/-5
2.4/-5
2.5/-5.2
2.5/-5.2
2.5/-5.2
2.5/-5.2
2.4/-10
2.4/-10
2.4/-10
2.4/-10
2.4/-10
2.4/-10

10
15
7
20
20
20
20
14
17
20
20
20
20

0.8/-250
0.8/-250
0.8/-500
0.8/-100
0.8/-100
0.8/-100
0.8/-100
0.85/-200
0.85/-200
0.8/-40
0.8/-40
0.8/-40
0.8/-40

2/80
2/80
2/100
2/20
2/20
2/20
2/20
2/20
2/20
2/80
2/80
2/80
2/80

400
400
400
400

0,

DP8307A
DP8308
DS3647
DS3667
DS75160A
DS75161A
DS75162A
DS8T26A
DS8T28
DS8833
DS8834
DS8835
DS8839

DP7308

DS8T26AM
DS8T28M
DS7833
DS7834
DS7835
DS7839

400
400
400
400

400
400
400
400

Comments

Page
No.

Logic
Non-Inverting
Logic
Inverting
Logic
Non-Inverting
Logic
Inverting
8080 MPU Data Latch and Service
6-5
Request f/t
6-13
8080 MPU Non-Inverting
6-13
8080 MPU Inverting
8080 MPU System Bus Controller
6-24
and Bus Driver
8080 MPU System Bus Controller
6·24
and Bus Driver
2-6
Bidirectional Inverting
Bidirectional Non-Inverting IEEE
2-11
488
2-16
Bidirectional Inverting
2-20
Bidirectional Non-Inverting
Quad Bidirectional I/O Register
5-28
2-47
2-88
IEEE 488 GPIB
2-88
IEEE 488 GPIB
2-88
IEEE 488 GPIB
2-117
Inverting
2-117
Non-Inverting
Non-Inverting TRI-STATE Receiver 2-101
2-105
Inverting
Inverting TRI-STATE Receiver
2-101
2-105
Non-I nverting

Note: Unless otherwise specified. bus circuits listed above are TTL compatible and use 5V supplies.

sl!n~J!O

iii

sna

c:(
C")

~ ~National

~

U Semiconductor
DP8303A 8-Bit TRI-STATE®
Bidirectional Transceiver (Inverting)
General Description

Features

This family of high speed Schottky 8-bit TRI-STATE bidirectional transceivers are designed to provide bidirectional
drive for bus oriented microprocessor and digital communications systems. They are all capable of sinking 16 mA on
the A ports and 48 mA on the B ports (bus ports). PNP
inputs for low input current and an increased output high
(VOH) level allow compatibility with MaS, CMOS, and other
technologies that have a higher threshold and less drive
capabilities. In addition, they all feature glitch-free power
up/down on the B port preventing erroneous glitches on the
system bus in power up or down.
DP8303A and DP7304B/DP8304B are featured with Transmit/Receive (T /R) and Chip Disable (CD) inputs to simplify
control logic. For greater design flexibility, DP8307 A and
and
DP7308/DP8308 are featured with Transmit
Receive (R) control inputs.

• 8-bit directional data flow reduces system package
count
• Bidirectional TRI-STATE inputs/outputs interface with
bus oriented systems
• PNP inputs reduce input loading
• Output high voltage interfaces with TTL, MaS, and
CMOS
• 48 mAl300 pF bus drive capability
• Pinouts simplify system interconnections
• Transmit/Receive and chip disable simplify control logic
• Compact 20-pin dual-in-line package
• Bus port glitch free power up/down

en

Logic and Connection Diagrams
Dual-In-Llne Package
AD
AD 0-++--1

>c>--~,,,,,-+--oSo

Al

I

I

L-

A2

Al~_
A2o--r-

!

_-----.r---<>SI
-......oS2

--1

A3o-t-

APORT

=
A6o-t =

-:}--oS3

::~

)

_~::

82

A3
A PORT

A4

SPORT

8 PORT
A5

=J-oS6

_~S7

A700-L_

14

AS

TRANSMIT/RECEIVE

85

r--_ _...._-+-(){-~.....rl(T/R)

CHIP DISfc~~o-",--_ _ _ _ _ _""'"

A7

13 S6

CHIP DISASLE

12 B7

GND

TLIF/5856-1

10

11

TRANIi'fEC

TL/F/5856-2

Top View
Order Number DP8303AJ or DP8303AN
See NS Package Number J20A, N20A

Logic Table
Inputs

Resulting Conditions

Chip Disable

Transmit/Receive

APort

0

0

OUT

IN

0

1

IN

OUT

1

X

TRI-STATE

TRI-STATE

x = Don't care
2-6

BPort

Absolute Maximum Ratings

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Storage Temperature

Supply Voltage

Recommended Operating
Conditions

7V

Input Voltage

5.5V

Output Voltage

5.5V

Maximum Power Dissipation· at 25°C
Cavity Package
Molded Package

- 65°C to + 150°C

Lead Temperature (soldering, 4 seconds)

Supply Voltage (Vee)
DP8303A
Temperature (TA)
DP8303A

1667mW
1832mW

'Derate cavity package 11.1 mWrC above 25'C; derate molded package
14.7 mWrC.

260°C

Min

Max

Units

4.75

5.25

V

0

70

°C

DC Electrical Characteristics (Notes 2 and 3)
Symbol

I

Parameter

I

Conditions

I

Min

I

Typ

I

Max

I Units

A PORT (AO-A7)
VIH

Logical "1" Input Voltage

CD = VIL, T IR = 2.OV

VIL

Logical "0" Input Voltage

CD = VIL, T IR = 2.OV

VOH

Logical "1" Output Voltage

CD = T/R = VIL
VIL = 0.5V

10H = -O.4mA

IOL=16mA

0.35

0.5

V

10L = 8 mA

0.3

0.4

V

-38

-75

mA

0.1

80

,..,A

1

mA
,..,A

V

2.0
0.7

10H = -3mA

VOL

Logical "0" Output Voltage

CD = TIA = VIL
VIL = 0.5V

los

Output Short Circuit
Current

CD = VIL. T IR = VIL, Vo = OV,
Vee = Max, (Note 4)

IIH

Logical "1" Input Current

CD = VIL, T IR = 2.OV, VIH = 2.7V

II

Input Current at Maximum
Input Voltage

CD = 2.OV, Vee = Max, VIH = 5.25V

Vee - 1.15

Vee - 0.7

2.7

3.95

-10

V
V
V

IlL

Logical "0" Input Current

CD = VIL, T IR = 2.OV, VIN = O.4V

-70

-200

VeLAMP

Input Clamp Voltage

CD = 2.OV, liN = -12 mA

-0.7

-1.5

V

100

Output/Input
TRI-STATE Current

CD = 2.OV

VIN = O.4V

-200

,..,A

VIN = 4.0V

80

,..,A

8 PORT (80-87)
VIH

Logical "1" Input Voltage

CD = VIL, T/R = VIL

VIL

Logical "0" Input Voltage

CD = VIL, T/R = VIL

VOH

Logical "1" Output Voltage

CD = VIL, T IR = 2.OV
VIL = 0.5V

10H = -0.4 mA

CD = VIL, T IR = 2.OV

10L = 20 mA

0.3

0.4

V

10L = 48 mA

0.4

0.5

V

-50

-150

mA

0.1

80

,..,A

1

mA
,..,A

VOL

Logical "0" Output Voltage

2.0

V

Vee - 1.15

Vee -0.8

V

10H = -5mA

2.7

3.9

V

10H = -10 mA

2.4

3.6

Output Short Circuit
Current

CD = VIL, T IR = 2.OV, Vo = OV,
Vee = Max, (Note 4)

IIH

Logical "1" Input Current

CD = VIL, T IR = VIL. VIH = 2.7V

II

Input Current at Maximum
Input Voltage

CD = 2.OV, Vee = Max, VIH = 5.25V

los

V
0.7

-25

V

IlL

Logical "0" Input Current

CD = VIL, T IR = VIL, VIN = O.4V

-70

-200

VeLAMP

Input Clamp Voltage

CD = 2.OV, liN = -12 mA

-0.7

-1.5

V

100

Output/Input
TRI-STATE Current

CD = 2.0V

VIN = O.4V

-200

,..,A

VIN = O.4V

+200

,..,A

2-7

«

('t)

o('t)
CO

DC Electrical Charcateristics

(Notes 2 and 3) (Continued)

D.

C

Symbol

Parameter

Min

Conditions

Typ

Max

Units

CONTROL INPUTS CD, T /R"
2.0

V,H

Logical "1" Input Voltage

V,L

Logical "0" Input Voltage

I'H

Logical "1" Input Current

V,H = 2.7V

I,

Maximum Input Current

Vee = Max, V,H = 5.25V

I,L

Logical "0" Input Current

0.5

-1

Input Clamp Voltage

V

20

p.A

1.0

mA

-0.1

-0.25

mA

-0.25

-0.5

mA

-0.8

-1.5

V

CD = 2.0V, V'N, Vee = Max

70

100

mA

CD = O.4V, V,NA = T fR = 2V, Vee = Max

100

150

mA

V,L = O.4V

TfR

I CD
VeLAMP

V
0.7

liN = -12 mA

POWER SUPPLY CURRENT
Icc

Power Supply Current

AC Electrical Characteristics Vee =
Symbol

5V, T A = 25°C
Conditions

Parameter

Min

Typ

Max

Units

A PORT DATA/MODE SPECIFICATIONS
tpDHLA

Propagation Delay to a Logical
8 Port to A Port

"a" from

CD = O.4V, TfR = O.4V (Figure A)
R1 = 1k, R2 = 5k, C1 = 30 pF

8

12

ns

tpDLHA

Propagation Delay to a Logical "1" from
8 Port to A Port

CD = O.4V, TfR = O.4V (Figure A)
R1 = 1k, R2 = 5k, C1 = 30 pF

11

16

ns

tPLZA

Propagation Delay from a Logical
TRI-STATE from CD to A Port

"a" to

80 to 87 = 2.4V, T fR = O.4V (Figure C)
S3 = 1, R5 = 1k, C4 = 15 pF

10

15

ns

tPHZA

Propagation Delay from a Logical "1" to
TRI-STATE from CD to A Port

80 to 87 = O.4V, T fR = O.4V (Figure C)
S3 = 0,R5 = 1k,C4 = 15pF

8

15

ns

tpZLA

Propagation Delay from TRI-STATE to
a Logical "a" from CD to A Port

80 to 87 = 2.4V, T fR = O.4V (Figure C)
S3 = 1, R5 = 1k, C4 = 30 pF

20

30

ns

tPZHA

Propagation Delay from TRI-STATE to
a Logical "1" from CD to A Port

80 to 87 = O.4V, T fR = O.4V (Figure C)
S3 = 0, R5 = 5k, C4 = 30 pF

19

30

ns

= O.4V, TfR = 2.4V (Figure A)
= 1000., R2 = 1k, C1 = 300 pF
= 6670., R2 = 5k, C1 = 45 pF

12
7

18
12

ns
ns

CD = 0.4V, T fR = 2.4V (Figure A)
R1 = 1000., R2 = 1k, C1 = 300 pF
R1 = 6670., R2 = 5k, C1 = 45 pF

15
9

20
14

ns
ns

B PORT DATA/MODE SPECIFICATIONS

"a" from

CD
R1
R1

tpDHLB

Propagation Delay to a Logical
A Port to 8 Port

tpDLHB

Propagation Delay to a Logical "1" from
A Port to 8 Port

tpLZB

Propagation Delay from a Logical
TRI-STATE from CD to 8 Port

"a" to

AO to A7 = 2.4V, T fR = 2.4V (Figure C)
S3 = 1, R5 = 1k, C4 = 15 pF

13

18

ns

tpHZB

Propagation Delay from a Logical "1" to
TRI-STATE from CD to 8 Port

AO to A7 = 0.4V, T fR = 2.4V (Figure C)
S3 = 0, R5 = 1k, C4 = 15 pF

8

15

ns

tPLZB

Propagation Delay from TRI-STATE to
a Logical "a" from CD to 8 Port

AO to A7 = 2.4V, T fR = 2.4V (Figure C)
S3 = 1, R5 = 1000., C4 = 300 pF
S3 = 1, R5 = 6670., C4 = 45 pF

25
16

35
25

ns
ns

tpZHB

Propagation Delay from TRI-STATE to
a Logical "1" from CD to 8 Port

AO to A7 = 0.4V, T fR = 2.4V (Figure C)
S3 = 0, R5 = 1k, C4 = 300 pF
S3 = 0, R5 = 5kn, C4 = 45 pF

22
14

35
25

ns
ns

2-8

C

AC Electrical Characteristics Vee =

"'C
(X)

5V, TA = 25°C (Continued)

w
w

0

Symbol

Parameter

Conditions

Min

Typ

Max

Units

l>

TRANSMITIRECEIVE MODE SPECIFICATIONS
tTRL

tTRH

Propagation Delay from Transmit Mode to
Receive a Logical "0", T /R to A Port

CD = O.4V (Figure 8)
81 = 1, R4 = 1oon, C3 = 5 pF
82 = 1, R3 = 1 k, C2 = 30 pF

23

35

ns

Propagation Delay from Transmit Mode to
Receive a Logical" 1", T /R to A Port

CD = O.4V (Figure 8)
81 = 0, R4 = 1oon, C3 = 5 pF
82 = 0, R3 = 5k, C2 = 30 pF

23

35

ns

Propagation Delay from Receive Mode to
Transmit a Logical "0", T fA to B Port

CD = 0.4V (Figure 8)
81 = 1, R4 = 100n, C3 = 300 pF
82 = 1, R3 = 300n, C2 = 5 pF

23

35

ns

Propagation Delay from Receive Mode to
Transmit a Logical "1", T fA to B Port

CD = O.4V (Figure 8)
81 = 0, R4 = 1 k, C3 = 300 pF
82 = 0, R3 = 300n, C2 = 5 pF

27

35

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the
devices should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified. minImax limits apply across the supply and temperature range listed in the table of Recommended Operating Conditions.
All typical values given are for Vee = 5V and T A = 25°C.
Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.
Note 4: Only one output at a time should be shorted.

Switching Time Waveforms and AC Test Circuits

3V
INPUT

-tf

1.5V

A:u~~~: O. ----'5.

tr =tf';; IOns
10'10 TO 90'10

Jr15V

ir_tP_O_L_H_ _ _ _ _ _t_PO_H_L_ _......\

f

BnORAn

1:.

~
TLIF/5856-3

Vcc

Vcc
~

... ~

. . ~RI

INPUT

OUTPUT

C)

4

I

PULSE
GENERATOR

I......~__--I

I

...

~t
DEVICE
UNDER
TEST

~,

-~

leI

:~R2

+ "*'

Note: Cl includes test fixture capacitance.

~,

--

... ~

~,
-l-

~

FIGURE A. Propagation Delay from A Port to B Port or from B Port to A Port

2-9

TLlF/5856-4

•

-L_

60

61

A PORT

-J-083

::~_

11

A3

82

A3o-t-

APORT

A2

_~81

A2

18

14

A6

13

AJ

TRANSMIT/RECEIVE

85

66

IT/AI
12

CHIP DISA6LE

GND

10

8J

11 TRANiRIC

CHIP DISA8LE
(COl

TL/F/8793-2
TL/F/8793-1

Top View
Order Number DP7304BJ, DP8304BJ,
DP8304BN or DP8304BWM
See NS Package Number J20A, N20A or M20B

Logic Table
Inputs

x=

Resulting Conditions

Chip Disable

Transmit/Receive

APort

B Port

0

0

OUT

IN

0

1

IN

OUT

1

X

TRI-STATE

TRI-STATE

Don't Care

2-11

m

'01::1'

o

Absolute Maximum Ratings

CO

If Military/Aerospace specified devices are required,

C

contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

C")

D..

.......

m
'01::1'

Supply Voltage

oC")

.....
D..

7V

Input Voltage

5.5V

Output Voltage

C

Recommended Operating
Conditions

(Note 1)

5.5V

Storage Temperature

- 65°C to

Maximum Power Dissipation· at 25°C
Cavity Package
Molded Package

+ 150°C

Min

Max

Units

Supply Voltage (Vee>
DP73048
DP83048

4.5
4.75

5.5
5.25

V
V

Temperature (TA)
DP73048
DP83048

-55
0

125
70

°C
°C

1667 mW
1832 mW

Lead Temperature (soldering, 4 sec.)

260°C

"Derate cavity package 11.1 mW fOC above 25'C; derate molded package
14.7 mWfOC above 25'C.

DC Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Min

Conditions

Typ

Max

Units

A PORT (AO-A7)
VIH

Logical "1" Input Voltage

CD

=

VIL, T /R

=

2.0V

VIL

Logical "0" Input Voltage

CD

=

VIL, T /R

=

2.0V

VOH

Logical "1" Output Voltage

CD

=

VIL, T/R

VOL

Logical "0" Output Voltage

CD

=

T/R

=

=

VIL

0.8

DP73048

0.7

10H

=

-0.4 rnA

10H

=

-3mA

VIL IIOL

=

16 rnA (83048)

IIOL

=

8 rnA (both)

Output Short Circuit
Current

CD = VIL, T IA = VIL, Vo
Vee = Max (Note 4)

IIH

Logical "1 " Input Current

CD

=

VIL, T IR

II

Input Current at Maximum
Input Voltage

CD

=

2.0V, Vee

los

=

=

2.0V, VIH

=

V

2.0
DP83048

OV,

=

Max, VIH

IlL

Logical "0" Input Current

CD

=

VIL, T IA

=

2.0V, VIN

VCLAMP

Input Clamp Voltage

CD

=

2.0V, liN

=

-12 rnA

100

Output/Input
TRI-STATE Current

CD

=

2.0V

2.7

-10

2.7V

=

=

Vee- U5 Vee- 0.7

V
V
V

3.95
0.35

0.5

V

0.3

0.4

V

-38

-75

rnA

0.1

80

/-LA

1

rnA

-70

-200

/-LA

-0.7

-1.5

V

5.25V

O.4V

V

VIN

=

O.4V

-200

/-LA

VIN

=

4.0V

80

/-LA

8 PORT (80- 87)
VIH

Logical "1" Input Voltage

CD

=

VIL, T/A

=

VIL

VIL

Logical "0" Input Voltage

CD

=

VIL, T/A

=

VIL

VOH

VOL

los

Logical "1" Output Voltage

Logical "0" Output Voltage

Output Short Circuit
Current

CD

CD

=

=

VIL, T IA

VIL, T IA

=

=

2.0

2.0V

2.0V

CD = VIL, T IA = 2.0V, Vo
Vee = Max (Note 4)

=

2-12

OV,

V

DP83048

0.8

V

DP73048

0.7

V

10H

=

-0.4 rnA

10H

=

-5mA

2.7

3.9

10H

=

-10 rnA

2.4

3.6

IOL

=

20 rnA

0.3

0.4

V

10L

=

48 rnA

0.4

0.5

V

-50

-150

rnA

Vee-1.15

Vee- 0.8

V
V

-25

V

DC Electrical Characteristics (Notes 2 and 3) (Continued)
Symbol

Parameter

Conditions

Min

Typ

Max

Units

0.1

80

/LA

1

rnA

/LA

8 PORT (80-87) (Continued)
IIH

Logical "1" Input Current

CD = VIL, T/R = VIL, VIH = 2.7V

II

Input Current at Maximum
Input Voltage

CD = 2.0V, Vee = Max, VIH = 5.25V

IlL

Logical "0" Input Current

CD = VIL, T IR = VIL, VIN = O.4V

-70

-200

VeLAMP

Input Clamp Voltage

CD = 2.0V,IIN = -12 rnA

-0.7

-1.5

V

100

Output/Input
TRI-STATE Current

CD = 2.0V

VIN = O.4V

-200

= 4.0V

+200

/LA
/LA

I
I VIN

CONTROL INPUTS CD, T IR
VIH

Logical "1" Input Voltage

VIL

Logical "0" Input Voltage

2.0

I
I DP7304B

IIH

Logical "1" Input Current

VIH = 2.7V

II

Maximum Input Current

Vee = Max, VIH = 5.25V

IlL

Logical "0" Input Current

VIL

VeLAMP

Input Clamp Voltage

V

DP8304B

=

0.5

I T/R
I CD

0.8

V

0.7

V

20

/LA

1.0

rnA

-0.1

-0.25

rnA

-0.25

-0.5

rnA

-0.8

-1.5

V

CD = 2.0V, VIN = O.4V, Vee = Max

70

100

rnA

CD = VINA = O.4V, T IR = 2V, Vee = Max

90

140

rnA

O.4V

liN = -12mA

POWER SUPPLY CURRENT
lee

Power Supply Current

AC Electrical Characteristics Vee =
Symbol

5V, T A = 25°C

Parameter

Conditions

Min

Typ

Max

Units

A PORT DATA/MODE SPECIFICATIONS
tpOHLA

Propagation Delay to a Logical "0" from
B Port to A Port

CD = O.4V, T/R = O.4V (Figure A)
R 1 = 1k, R2 = 5k, C1 = 30 pF

14

18

ns

tpOLHA

Propagation Delay to a Logical "1" from
B Port to A Port

CD = O.4V, T IR = O.4V (Figure A)
R 1 = 1k, R2 = 5k, C1 = 30 pF

13

18

ns

tpLZA

Propagation Delay from a Logical "0" to
TRI-STATE from CD to A Port

BO to B7 = O.4V, T IR = O.4V (Figure C)
S3 = 1, R5 = 1k, C4 = 15 pF

11

15

ns

tPHZA

Propagation Delay from a Logical "1" to
TRI-STATE from CD to A Port

BO to B7 = 2.4V, T IR = O.4V (Figure C)
S3 = 0, R5 = 1k, CR = 15 pF

8

15

ns

tpZLA

Propagation Delay from TRI-STATE to
a Logical "0" from CD to A Port

BO to B7 = O.4V, T IR = O.4V (Figure C)
S3 = 1, R5 = 1k, C4 = 30 pF

27

35

ns

tpZHA

Propagation Delay from TRI-STATE to
a Logical "1" from CD to A Port

BO to B7 = 2.4V, T IR = O.4V (Figure C)
S3 = 0, R5 = 5k, C4 = 30 pF

19

25

ns

8 PORT DATA/MODE SPECIFICATIONS
tpOHLB

tpOLHB

Propagation Delay to a Logical "0" from
A Port to B Port

CD = O.4V, TIR = 2.4V (Figure A)
R1 = 100!}, R2 = 1k, C1 = 300 pF
R1 = 667!}, R2 = 5k, C1 = 45 pF

18
11

23
18

ns
ns

Propagation Delay to a Logical "1" from
A Port to B Port

CD = O.4V, T/R = 2.4V (Figure A)
R1 = 100!}, R2 = 1k, C1 = 300 pF
R1 = 667!}, R2 = 5k, C1 = 45 pF

16
11

23
18

ns
ns

2-13

m
"'I:t'

o

(f)

AC Electrical Characteristics Vee =

5V, T A = 25'C (Continued)

CO

a..

Symbol

m

B PORT DATA/MODE SPECIFICATIONS (Continued)

o(f)

tPLZB

Propagation Delay from a Logical "0" to
TRI·STATE from CD to B Port

tPHZB
tpZLB

C
.......
"'I:t'

I"-

a..
C

tpZHB

Typ

Max

Units

AO to A7 = O.4V, T /R" = 2.4V (Figure C)
S3 = 1,R5 = 1k,C4 = 15pF

13

18

ns

Propagation Delay from a Logical "1" to
TRI·STATE from CD to B Port

AO to A7 = 2.4V, T /R = 2.4V (Figure C)
S3 = 0, R5 = 1k, C4 = 15 pF

8

15

ns

Propagation Delay from TRI·STATE to
a Logical "0" from CD to B Port

AO to A7 = O.4V, T /R = 2.4V (Figure C)
S3 = 1, R5 = 1000, C4 = 300 pF
S3 = 1, R5 = 6670, C4 = 45 pF

32
16

40
22

ns
ns

Propagation Delay from TRI·STATE to
a Logical "1" from CD to B Port

AO to A7 = 2.4V, T IR = 2.4V (Figure C)
S3 = 0, R5 = 1 k, C4 = 300 pF
S3 = 0, R5 = 5k, C4 = 45 pF

26
14

35
22

ns
ns

Parameter

Conditions

Min

TRANSMIT/RECEIVE MODE SPECIFICATIONS
tTRL

tTRH

tRTH

Propagation Delay from Transmit Mode to
Receive a Logical "0", T IR to A Port

CD = O.4V (Figure 8)
S1 = 0, R4 = 1000, C3 = 5 pF
S2 = 1, R3 = 1k, C2 = 30 pF

30

40

ns

Propagation Delay from Transmit Mode to
Receive a Logical "1", T IR to A Port

CD = 0.4V, (Figure 8)
S1 = 1, R4 = 1000, C3 = 5 pF
S2 = 0, R3 = 5k, C2 = 30 pF

28

40

ns

Propagation Delay from Receive Mode to
Transmit a Logical "1", T IR to B Port

CD = O.4V (Figure 8)
S1 = 0, R4 = 1k, C3 = 300 pF
S2 = 1, R3 = 3000, C2 = 5 pF

28

40

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified, minImax limits apply across the supply and temperature range listed in the table of Recommended Operating Conditions. All
typical values given are for Vee = 5V and TA = 25'C.
Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.
Note 4: Only one output at a time should be shorted.

Switching Time Waveforms and AC Test Circuits
JV
/ - Ir
1 5V ..... ~

INPUT

AnOR8n~

Ir = If .;; 10ns
111% TO 90%

':)'~

OV

OUTPUT
8n OR An

'POHL

f'POLH

1.5V

1.5V

TL/F/B793-3

VCC

VCC

..~:Rl
~

INPUT
4)

I

PULSE
GENERATOR

II

OUTPUT

•

~
~ f0o-

-!Note: Cl includes test fixture capaCitance.

±"

~~

..

~t
~~

"'!~

"'!~

DEVICE
UNDER
TEST
: .. R2

FIGURE A. Propagation Delay from A Port to B Port or from B Port to A Port

2·14

TLlF/8793-4

Switching Time Waveforms and AC Test Circuits (Continued)
3V-------J----------------------~

If

I, • If " IOns

IN~~

10% TO 90%
OV

OUTPUT ----+-~

IRTL

B PORT

RTH

~

A PORT

1.5V

OUTPUT

ITRL

tyRH~~
--..!"1.5V
TLlF/B793-5

VCC

t---41-----0

APORT~---~._-~

S2 = 1
VCC~

DEVICE
UNDER
TEST

R3

B PORT

R4

TL/F/8793-6

Note: C2 and C3 include test fixture capacitance.

FIGURE B. Propagation Delay from T /R' to A Port or B Port
3V--------,-----------------~

= If .;; IOns
10% TO 90%

Ir

INPUT
CD

If

OV
PORT OUTPUT

-----+-...
tpHZ
PLZ

~
O.5V

PORT OUTPUT

--..i

TLlF/B793-7

VCC

2.4VO
PORT
INPUT

O.4V

t----4I-----~D ~~~~UT
INPUT
DEVICE
UNDER
TEST

....+-------4 CD

TL/F/B793-B

Note: C4 includes test fixture capacitance.
Port input is in a fixed logical
condition. See AC table.

FIGURE C. Propagation Delay to/from TRI·STATE from CD to A Port or B Port

2·15

«
I"~ ~National
~ ~ Semiconductor
DP8307A a-Bit TRI-STATE®
Bidirectional Transceiver (Inverting)
General Description

Features

The DP8307A is a high speed Schottky 8-bit TRI-STATE
bidirectional transceiver designed to provide bidirectional
drive for bus oriented microprocessor and digital communications systems. It is capable of sinking 16 mA on the A
ports and 48 mA on the B ports (bus ports). PNP inputs for
low input current and an increased output high (VOH) level
allow compatibility with MOS, CMOS, and other technologies that have a higher threshold and less drive capabilities.
In addition, it features glitch-free power up/down on the B
port preventing erroneous glitches on the system bus in
power up or down.

• 8-bit bidirectional data flow reduces system package
count
• Bidirectional TRI-STATE inputs/outputs interface with
bus oriented systems
• PNP inputs reduce input loading
• Output high votlage interfaces with TTL, MOS, and
CMOS
• 48 mA/300 pF bus drive capability
• Pinouts simplify system interconnections
• Independent T and R controls for versatility
• Compact 20-pin dual-in-line package
• Bus port glitch free power up/down

DP8303A and DP7304B/DP8304B are featured with Transmit/Receive (T /R) and Chip Disable (CD) inputs to simplify
control logic. For greater design flexibility, DP8307 A and
DP7308/DP8308 is featured with Transmit
and
Receive (R) control inputs.

en

Logic and Connection Diagrams
Dual-ln-L1ne Package
20 Vee
AD 0--+-....--1

I

I
1--

AI0--t...- _
A2

A PORT

o---J""""

A3o-t=
A4C>--L _

A5o--r

A6o-C=
A70--L._

.....-+----

19 BO

I
I
---I
_ ----.r--o B1

=
=

A3

"""l-oB2

::l--oB3
_j-OB4
"""1-oB5

B2

A PORT
A4

B PORT

B PORT

::l--oB6
_...J""'OB7

A5

15 B4

A6

14

A7

13 B6
12

TLlF/8794-1

Logic Table

TLlF/8794-2

Resulting Conditions

Transmit

Receive

A Port

B Port

1

0

OUT

IN

0

1

IN

OUT

1

1

TRI-STATE

TRI-STATE

0

0

B7

11 R

GNO

Control Inputs

B5

Top View
Order Number DP8307AJ or DP8307AN
See NS Package Number J20A or N20A

Both Active*

'This is not an intended logic condition and may cause oscillations.

2-16

Absolute Maximum Ratings

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

Lead Temperature (soldering, 4 sec.)

5.5V

Output Voltage

5.5V

Maximum Power Dissipation* at 25°C
Cavity Package
Molded Package

- 65°C to + 150°C

Recommended Operating
Conditions

7V

Input Voltage

260°C

Storage Temperature

Min
4.75
0

Supply Voltage (Vee)
Temperature (TA)

1667 mW
1832mW

Max
5.25
70

Units
V
°C

• Derate cavity package 11.1 mW I'C above 2SoC; derate molded package
14.7 mWI'C above 25°C.

DC Electrical Characteristics
Symbol

I

Parameter

(Notes 2 and 3)

Conditions

I

I

Min

I

Typ

I Max I Units

A PORT (AO-A7)
VIH

Logical "1" Input Voltage

T = VIL, R = 2.0V

VIL

Logical "0" Input Voltage

T = VIL, R = 2.0V

VOH

Logical "1" Output Voltage

T = 2.0V, R = VIL
VIL = 0.5V

10H = -0.4 mA

10L = 16mA

0.35

0.5

V

10L = 8 mA

0.3

0.4

V

-38

-75

mA

0.1

80

p.A

1

mA

-70

-200

p.A

-0.7

-1.5

V

VIN = O.4V

-200

p.A

VIN = 4.0V

80

p.A

2.0

10H = -3 mA

VOL

Logical "0" Output Voltage

T = 2.0V,
R = VIL

los

Output Short Circuit
Current

T = 2.0V, R = VIL, Vo = OV,
Vee = Max, (Note 4)

IIH

Logical "1" Input Current

T = VIL, R = 2.0V, VIH = 2.7V

II

Input Current at Maximum
Input Voltage

R = T = 2.0V, Vee = Max, VIH = 5.25V

IlL

Logical "0" Input Current

T=

VeLAMP

Input Clamp Voltage

T = R = 2.0V, liN = -12 mA

100

Outputllnput
TRI-STATE Current

T= R=

Vee - 1.15

Vee - 0.7

2.7

3.95

-10

VIL, R = 2.0V, VIN = O.4V

2.0V

V
0.7

V
V
V

8 PORT (80-87)
VIH

Logical "1" Input Voltage

T =2.0V, R = VIL

VIL

Logical "0" Input Voltage

T = 2.0V, R = VIL

VOH

Logical "1" Output Voltage

T = VIL, R = 2.0V
VIL = 0.5V

VOL

los

Logical "0" Output Voltage

Output Short Circuit
Current

T = VIL, R = 2.0V

2.0

V
0.7

10H = -0.4 mA

V

Vee - 1.15

Vcc - 0.8

V

10H = -5mA

2.7

3.9

V

10H = -10 mA

2.4

3.6

V

10L = 20 mA

0.3

0.4

V

10L = 48 mA

0.4

0.5

V

-50

-150

mA

0.1

80

p.A

1

mA
p.A

T = VIL, R = 2.0V, Vo = OV,
Vee = Max, (Note 4)

IIH

Logical "1" Input Current

T = 2.0V, R = VIL, VIH = 2.7V

II

Input Current at Maximum
Input Voltage

T= R=

-25

2.0V, Vee = Max, VIH = 5.25V

IlL

Logical "0" Input Current

T = 2.0V, R = VIL, VIN = O.4V

-70

-200

VCLAMP

Input Clamp Voltage

-0.7

-1.5

V

100

Outputllnput
TRI-STATE Current

T= R=
T = R=

VIN = O.4V

-200

p.A

VIN = 4.0V

+200

p.A

2.0V, liN = -12 mA
2.0V

2-17

<
I"oC")

DC Electrical Characteristics (Notes 2 and 3) (Continued)

CO

D-

C

Symbol

I

Parameter

CONTROL INPUTS f,

R

I

Conditions

VIH

Logical "1" Input Voltage

VIL

Logical "0" Input Voltage

IIH

Logical "1" Input Current

VIH = 2.7V

II

Maximum Input Current

Vee = Max, VIH = 5.25V

IlL

Logical "0" Input Current

VIL = OAV

Input Clamp Voltage

VeLAMP

I

I

Min

I

Typ

Max

I

2.0

Units

V

IR
IT

liN = -12 mA

0.7

V

0.5

20

p,A

1.0

mA

-0.1

-0.25

mA

-0.25

-0.5

mA

-0.8

-1.5

V

POWER SUPPLY CURRENT
Power Supply Current

Ice

f

=

R=

AC Electrical Characteristics Vee =
Symbol

I

Parameter

70

100

mA

100

150

mA

2.0V, VIN = 2.0V, Vee = Max

T = OAV, VINA = R = 2V, Vee = Max
5V, T A = 25°C

I

Conditions

I

Min

I

Typ

I

Max

I

Units

A PORT DATA/MODE SPECIFICATIONS
= 2AV, R = O.4V (Figure A)
R1 = 1 k, R2 = 5k, C1 = 30 pF

8

12

ns

= 2.4V, R = O.4V (FigureA)
R1 = 1k, R2 = 5k, C1 = 30 pF

11

16

ns

Propagation Delay from a Logical "0" to
TRI-STATE from R to A Port

80 to 87 = 2.4V, f = 2.4V (Figure 8)
S3 = 1,R5 = 1k,C4 = 15pF

10

15

ns

tPHZA

Propagation Delay from a Logical" 1" to
TRI-STATE from R to A Port

80 to 87 = O.4V, f = 2.4V (Figure 8)
S3 = 0, R5 = 1 k, C4 = 15 pF

8

15

ns

tPZLA

Propagation Delay from TRI-STATE to
a Logical "0" from R to A Port

80 to 87 = 2.4V, f = 2.4V (Figure 8)
S3 = 1, R5 = 1k, C4 = 30 pF

25

35

ns

tpZHA

Propagation Delay from TRI-STATE to
a Logical "1" from R to A Port

80 to 87 = O.4V, f = 2.4V (Figure 8)
S3 = 0, R5 = 5k, C4 = 30 pF

24

35

ns

= O.4V, R = 2.4V (Figure A)
R1 = 1000., R2 = 1k, C1 = 300 pF
R1 = 6670., R2 = 5k, C1 = 45 pF

12
8

18
12

ns
ns

= O.4V, R = 2.4V (Figure A)
R1 = 1000., R2 = 1k, C1 = 300 pF
R1 = 6670., R2 = 5k, C1 = 45 pF

15
9

23
14

ns
ns

tpDHLA

Propagation Delay to a Logical "0" from
8 Port to A Port

f

tpDLHA

Propagation Delay to a Logical "1" from
8 Port to A Port

f

tPLZA

B PORT DATA/MODE SPECIFICATIONS
Propagation Delay to a Logical "0" from
A Port to 8 Port

f

Propagation Delay to a Logical "1" from
A Port to 8 Port

f

tpLZB

Propagation Delay from a Logical "0" to
TRI-STATE from f to 8 Port

AO to A7 = 2.4V, R = 2.4V (Figure 8)
S3 = 1, R5 = 1k, C4 = 15 pF

13

18

ns

tpHZB

Propagation Delay from a Logical "1" to
TRI-STATE from f to 8 Port

AO to A7 = 0.4V, R = 2.4V (Figure 8)
S3 = 0, R5 = 1k,C4 = 15pF

8

15

ns

tPZLB

Propagation Delay from TRI-STATE to
a Logical "0" from f to 8 Port

AO to A7 = 2.4V, R = 2.4V (Figure 8)
S3 = 1, R5 = 1000., C4 = 300 pF
S3 = 1, R5 = 6670., C4 = 45 pF

32
18

40
25

ns
ns

Propagation Delay from TRI-STATE to
a Logical "1" from f to 8 Port

AO to A7 = 0.4V, R = 2.4V (Figure B)
S3 = 0, R5 = 1k, C4 = 300 pF
S3 = 0, R5 = 5k, C4 = 45 pF

25
16

35
25

ns
ns

tpDHLB

tpDLHB

tPZHB

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified, min/max limits apply across the supply and temperature range listed in the table of Recommended Operating Conditions. All
typica! values given are for Vee = 5V and T A = 25'C.
Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.
Note 4: Only one output at a time should be shorted.

2-18

C

"tJ

SWitching Time Waveforms and AC Test Circuits

CO

w
o

.......

3V

»

Ir =If " IOns
10'10 TO 90'10

Ir~POLH
OUTPUT
On OR An

1.5 V
IPOHL

1.5Vf

_ _ _ _..I

TL/F/8794-3

VCC

VCC

INPUT

DEVICE
UNDER
TEST

TL/F/8794-4

Note: Cl includes test fixture capacitance.

FIGURE A. Propagation Delay from A Port to B Port or from B Port to A Port
3V--------,-------------~

Ir

CONTROL INPUT

= If

If

.;; IOns

10'10 TO 90%

OV
PORT OUTPUT

---+.,
IPHZ

~
PLZ

0.5V

PORT OUTPUT

---1.

TLIF/8794-5

VCC
2.4VO

PORT
INPUT

0.4V

1 - -...- - - - 0 ~~~~UT

CONTROL
INPUT
DEVICE
UNDER
TEST
.....+----tii OR T

RS

:r

TL/F/8794-6

Note: C4 includes test fixture capacitance. Port input is in a fixed logical condition. See AC Table.

FIGURE B. Propagation Delay to/from TRI-STATE from R to A Port and T to B Port

2-19

co
oC")
CO

a..
......
CO
oC")
C

.....

a..
C

J?A National
a Semiconductor
DP7308/DP8308 8-Bit TRI-STATE®
Bidirectional Transceiver (Non-Inverting)
General Description

Features

The DP730S/DP8308 are high speed Schottky 8-bit TRISTATE bidirectional transceivers designed to provide bidirectional drive for bus oriented microprocessor and digital
communications systems. They are all capable of sinking
16 mA on the A ports and 48 mA on the B ports (bus ports).
PNP inputs for low input current and an increased output
high (VOH) level allow compatibility with MOS, CMOS, and
other technologies that have a higher threshold and less
drive capabilities. In addition, they all feature glitch-free
power up/down on the B port preventing erroneous glitches
on the system bus in power up or down.
DP7308/DP8308 are featured with Transmit
and
Receive (R) control inputs.

• 8-bit bidirectional data flow reduces system package
count
• Bidirectional TRI-STATE inputs/outputs interface with
bus oriented systems
• PNP inputs reduce input loading
• Output high voltage interfaces with TTL, MOS, and
CMOS
• 48 mAi300 pF bus drive capability
• Pinouts simplify system interconnections
• Independent 'f and R controls for versatility
• Compact 20-pin dual-in-line package
• Bus port glitch free power up/down

en

Logic and Connection Diagrams

r------,

AOo--+-...........

~---__~-oBO

I

I

I

L-

Al~_
A2o--1'"""
A3o-{:

=

A4~_

APORT

AS

Dual-In-Llne Package
AO

0--1""""

Al

I

-....J

A2

_~Bl
-.......oB2

A3
A PORT

=j-oB3
B4

_

t-O

B PORT

A4

~BS

ASo-C=

B PORT
AS

=J-oB6
B7

_ .-r-o

A7D--L.. _

A6

BS

A7

13 B6

TLlF/8795-1

12 B7

GNO

10

11

Logic Table

R
TLlF/8795-2

Control Inputs

Top View

Resulting Conditions

Transmit

Receive

A Port

B Port

1

0

OUT

IN

0

1

IN

OUT

1

1

TRI·STATE

TRI·STATE

0

0

Order Number DP7308J, DP8308J
or DP8308N
See NS Package Number J20A or N20A

Both Active*

·This is not an intended logic condition and may cause oscillations.

2·20

C

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

Min

5.5V

Output Voltage

5.5V

Storage Temperature

- 65'C to + 150'C

Maximum Power Dissipation· at 25'C
Cavity Package
Molded Package

~

w

o
Q)

Units

Max

w

4.5
4.75

5.5
5.25

V
V

-55

+125
+70

'c
'c

a

oQ)

260'C

• Derate cavity package 11.1 mW I'C above 2S'C; derate molded package
14.7 mWI'C above 2S'C.

DC Electrical Characteristics (Notes 2 and 3)
Symbol

I

Parameter

I

Conditions

I

Min

I

Typ

I

Max

I

Units

A PORT (AO-A7)
VIH

Logical "1" Input Voltage

VIL

Logical "0" Input Voltage

VOH

Logical "1" Output Voltage

f
f
f

= VIL,
= VIL,

R=
R=

2.0V

R=

= 2.0V,

VIL

DP8308

0.8

V

DP7308

0.7

V

10H = -0.4mA
10H = - 3mA

VOL

Logical "0" Output Voltage

f

= 2.0V,

R=

VIL

V

0.4

V

-38

-75

mA

0.1

80

IJ-A

1

mA

-70

-200

IJ-A

-0.7

-1.5

V

R=

IIH

Logical "1" Input Current

f

= VIL,

Input Current at Maximum
Input Voltage

R = T = 2.0V, Vee = Max, VIH = 5.25V

IlL

Logical "0" Input Current

VeLAMP

Input Clamp Voltage

f
f

100

Output/Input
TRI-STATE Current

T =

R=

V
0.5

II

R=
R=

3.95

0.3

VIL, Vo = OV
Vee = Max (Note 4)

=

V

2.7

0.35

= 2.0V,

= VIL,

Vee- 0.7

10L = 8 mA (both)

f

R=

Vee- 1.15

10L = 16 mA (8308)

Output Short Circuit
Current

los

V

2.0

2.0V

-10

2.0V, VIH = 2.7V

2.0V, VIN = O.4V

2.0V, liN = -12 mA
2.0V

VIN = O.4V

-200

IJ-A

VIN = 4.0V

80

IJ-A

8 PORT (80-87)
VIH

Logical "1" Input Voltage

VIL

Logical "0" Input Voltage

VOH

VOL

los

Logical "1" Output Voltage

Logical "0" Output Voltage

Output Short Circuit .
Current

f
f
f

= 2.0V,
= 2.0V,

= VIL,

R=
R=

R=

2.0

VIL
VIL

2.0V

T = VIL, R = 2.0V

0.8

DP7308

0.7

2.7

3.9

10H = -10 mA

2.4

3.6

V

10L = 48 mA

0.4

0.5

V

.,--50

-150

mA

0.1

80

IJ-A

1

mA

-70

-200

IJ-A

-0.7

-1.5

V

VIN = O.4V

-200

IJ-A

VIN = 4.0V

+200

IJ-A

-25

T = 2.0V, R = VIL, VIH = 2.7V

II

f

=

IlL

Logical "0" Input Current

f

= 2.0V,

100

T =

Output/Input
TRI-STATE Current

f

=

R=
R=

2.0V, Vee = Max, VIH = 5.25V
VIL, VIN = O.4V

2.0V, liN = -12 mA
2.0V

2-21

V
0.4

Logical "1" Input Current

Input Clamp Voltage

V

0.3

Input Current at Maximum
Input Voltage

VeLAMP

V

10L = 20 mA

IIH

R=

V

V

Vee- 1. 15 Vee- 0.8

10H = -5mA

T = VIL, R = 2.0V, Vo = OV,
Vee = Max (Note 4)

R=

V

DP8308

10H = -0.4 mA

C

Q)

1667mW
1832mW

Lead Temperature (soldering, 4 sec.)

........
""0

Supply Voltage (Vee)
DP7308
DP8308
Temperature (TA)
DP7308
DP8308

7V

input Voltage

""0

Recommended Operating
Conditions

co

oC")
CO

DC Electrical Characteristics (Notes 2 and 3) (Continued)

C

Symbol

CO

CONTROL INPUTS 1', R

D.

.......

oC")

.....

D.

C

Parameter

VIH

Logical "1" Input Voltage

VIL

Logical "0" Input Voltage

Conditions

Min

Typ

Max

2.0

I
I

IIH

Logical "1" Input Current

VIH = 2.7V

II

Maximum Input Current

Vee = Max, VIH = 5.25V

IlL

Logical "0" Input Current

VIL = O.4V

VCLAMP

Input Clamp Voltage

liN = -12 mA

I
I

Units

V

DPS30S

O.S

DP730S

0.7

V

0.5

20

p,A

1.0

mA

-0.1

-0.25

mA

-0.25

-0.5

mA

-O.S

-1.5

V

70

100

mA

90

140

mA

R
T

V

POWER SUPPLY CURRENT
lee

Power Supply Current

T= R=
'f

2.0V, VIN = O.4V, Vce = Max

= VINA = O.4V, R = 2V, Vee = Max

AC Electrical Characteristics Vee =
Symbol

5V, T A = 25°C

Parameter

Typ

Max

Units

= 2.4V, R = O.4V (Figure A)
R1 = 1 k, R2 = 5k, C1 = 30 pF

14

18

ns

Conditions

Min

A PORT DATA/MODE SPECIFICATIONS
tpDHLA

Propagation Delay to a Logical "0" from
8 Port to A Port

'f

tpDLHA

Propagation Delay to a Logical "1" from
8 Port to A Port

'f

= 2.4V, R = O.4V (Figure A)
R1 = 1k, R2 = 5k, C1 = 30 pF

13

18

ns

tPLZA

Propagation Delay from a Logical "0" to
TRI-STATE from R to A Port

80 to 87 = O.4V, 'f = 2.4V (Figure 8)
S3 = 1, R5 = 1 k, C4 = 15 pF

11

15

ns

tPHZA

Propagation Delay from a Logical "1" to
TRI-STATE from R to A Port

80 to 87 = 2.4V, 'f = 2.4V (Figure 8)
S3 = 0, R5 = 1 k, C4 = 15 pF

8

15

ns

tpZLA

Propagation Delay from TRI-STATE to
a Logical "0" from R to A Port

80 to 87 = 0.4V, 'f = 2.4V (Figure 8)
S3 = 1, R5 = 1k, C4 = 30 pF

24

35

ns

tpZHA

Propagation Delay from TRI-STATE to
a Logical "1" from R to A Port

80 to 87 = 2.4V, 'f = 2.4V (Figure 8)
S3 = 0, R5 = 5k, C4 = 30 pF

21

30

ns

= O.4V, R = 2.4V (Figure A)
R1 = 1000, R2 = 1k, C1 = 300 pF
R1 = 6670, R2 = 5k, C1 = 45 pF

1S
11

23
18

ns
ns

= 0.4V, R = 2.4V (Figure A)
R1 = 1000, R2 = 1k, C1 = 300 pF
R1 = 6670, R2 = 5k, C1 = 45 pF

16
11

23
18

ns
ns

B PORT DATA/MODE SPECIFICATIONS
Propagation Delay to a Logical "0" from
A Port to 8 Port

'f

Propagation Delay to a Logical "1" from
A Port to 8 Port

'f

tPLZB

Propagation Delay from a Logical "0" to
TRI-STATE from 'f to 8 Port

AO to A7 = O.4V, R = 2.4V (Figure 8)
S3 = 1, R5 = 1k, C4 = 15 pF

13

18

ns

tpHZB

Propagation Delay from a Logical "1" to
TRI-STATE from 'f to 8 Port

AO to A7 = 2.4V, R = 2.4V (Figure 8)
S3 = 0, R5 = 1k, C4 = 15 pF

8

15

ns

tPZLB

Propagation Delay from TRI-STATE to
a Logical "0" from 'f to 8 Port

AO to A7 = 0.4V, R = 2.4V (Figure 8)
S3 = 1, R5 = 1000, C4 = 300 pF
S3 = 1, R5 = 6670, C4 = 45 pF

25
17

35
25

ns
ns

Propagation Delay from TRI-STATE to
a Logical "1" from 'f to 8 Port

AO to A7 = 2.4V, R = 2.4V (Figure 8)
S3 = 0, R5 = 1k, C4 = 300 pF
S3 = 0, R5 = 5k, C4 = 45 pF

24

35
25

ns
ns

tpDHLB

tpDLHB

tpZHB

2-22

17

C

AC Electrical Characteristics

-a

(Continued)

.......
w
o

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature
Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual
device operation.

......

Note 2: Unless otherwise specified, min/max limits apply across the supply and temperature range listed in the table of Recommended Operating Conditions.
All typical values given are for Vee = 5V and TA = 25'C.

(X)

Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.
Note 4: Only one output at a time should be shorted.

Switching Time Waveforms and AC Test Circuits
3V--_

tr

INPUT

=tf~10 ns

107. TO 907.

An OR Bn

OV-------;-~------------------------

______________

J

OUTPUT

1.5V

Bn OR An

TLlF/8795-3

VCC

VCC

INPUT

DEVICE
UNDER

TEST

TL/F/8795-4

Note: Cl includes test fixture capaCitance.

FIGURE A. Propagation Delay from A Port to B Port or from B Port to A Port

CDNTRDL INPUT

3V--------,~--------------------~
If
I, • If .. IOns
10'10 TO 90'10
OV

PORT OUTPUT - - -.........

IPHZ

~
PLZ

O.5V

PORT OUTPUT

---1

TL/F/B795-5

VCC
PORT
INPUT

2.4VO
O.4V

....- - t.....--~O ~~~~UT

CONTROL
INPUT
DEVICE
UNDER

TEST

..........--....f"RORT

S3 = 1
R5

VCC

TL/F/8795-6

Note: C4 includes test fixture capacitance. Port input is in a fixed logical condition. See AC Table.

FIGURE B. Propagation Delay to/from TRI-STATE from R to A Port and f to B Port
2-23

(X)

C

-a

w

o(X)

:E
,..

,..

en
CD

I?A National

Q

D Semiconductor

,..

DS26S10C/DS26S10M/DS26S11C/DS26S11M

CD
N

Quad Bus Transceivers

N

en

......
o
,..
en

~
......
General Description
:E
Q
The OS26S10 and OS26S11 are
,..
en

CD

N

en
Q

......

oQ
,..
(J)
CD
N
(J)

Q

The OS26S10 and OS26S11 feature advanced Schottky
processing to minimize propagation delay. The device package also has 2 ground pins to improve ground current handling and allow close decoupling between Vee and ground
at the package. Both GNO 1 and GNO 2 should be tied to
the ground bus external to the device package.

quad Bus Transceivers
consisting of 4 high speed bus drivers with open-collector
outputs capable of sinking 100 rnA at O.BV and 4 high speed
bus receivers. Each driver output is connected internally to
the high speed bus receiver in addition to being connected
to the package pin. The receiver has a Schottky TTL output
capable of driving 10 Schottky TTL unit loads.

Features

An active low enable gate controls the 4 drivers so that
outputs of different device drivers can be connected together for party-line operation.

•
•
•
•
•
•

The bus output high-drive capability in the low state allows
party-line operation with a line impedance as low as 1000..
The line can be terminated at both ends, and still give considerable noise margin at the receiver. The receiver typical
switching point is 2V.

Input to bus is inverting on OS26S10
Input to bus is non-inverting on OS26S11
Quad high speed open-collector bus transceivers
Oriver outputs can sink 100 rnA at O.BV maximum
Advanced Schottky processing
PNP inputs to reduce input loading

Logic and Connection Diagrams
DS26S10

DS26S11

11

ZO

Z\

Z3

Z2

ZO

Z2

Z\

Z3

TL/F/5802-1

GND \

BO"

TLIF/5802-2

Dual-In-Line Package

Dual-In-Line Package

DS26S10N

DS26SIIN

ZO

10

1\

Z\

Ii1

GND \

GND 2

TL/F/5802-3

BO"

ZO

11

Z\

III

GND2

TLIF/5802-4

Top View
Order Number DS26S 11 CJ, DS26S 11 MJ
or DS26S11CN
See NS Package Number J16A or N16A

Top View
Order Number DS26S10CJ, DS26S10MJ
or DS26S10CN
See NS Package Number J16A or N16A
2-24

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Maximum Power Dissipation· at 25°C
Cavity Package
Molded Package

Storage Temperature

- 65°C to + 150°C

Temperature (Ambient) Under Bias

- 55°C to + 125°C

·Derate cavity package 9.6 mW/·C above 2S"C; derate molded package
10.9 mWI·C above 2S"C.

Supply Voltage to Ground Potential
DC Voltage Applied to Outputs for
High Output State

-0.5Vto +7V

Operating Conditions

-0.5V to + Vee Max

DC Input Voltage

Supply Voltage (Vee)
DS26S10C, DS26S11C
DS26S10M,DS26S11M
Temperature (TA)
DS26S10C,DS26S11C
DS26S10M,DS26S11M

- 0.5V to + 5.5V

Output Current, Into Bus

200 rnA

Output Current, Into Outputs (Except Bus)
DC Input Current

1433 mW
1362mW

30 rnA

-30 rnA to +5 rnA

Min

Max

Units

4.75
4.5

5.25
5.5

V
V

0
-55

+70
+125

°C
°C

Electrical Characteristics (Unless otherwise noted)
Symbol

Conditions
(Note 1)

Parameter

= Min,IOH =
= VIL or VIH

Min

Output High Voltage
(Receiver Outputs)

Vee

VOL

Output Low Voltage
(Receiver Outputs)

Vee = Min, IOL = 20 rnA,
VIN = VIL or VIH

VIH

Input High Level
(Except Bus)

Guaranteed Input Logical High for
All Inputs

VIL

Input Low Level
(Except Bus)

Guaranteed Input Logical Low for
All Inputs

VI

Input Clamp Voltage
(Except Bus)

Vee

= Min, lIN =

IlL

Input Low Current
(Except Bus)

Vee

= Max, VIN = O.4V

Input High Current
(Except Bus)

Vee

II

Input High Current
(Except Bus)

Vee

= Max, VIN = 5.5V

Ise

Output Short·Circuit Current
(Except Bus)

Vee

= Max, (Note 3)

Power Supply Current
(All Bus Outputs Low)

Vee

VOH

IIH

leeL

VIN

-1 rnA,

Typ
(Note 2)

= Max, Enable = GND

Military

2.5

3.4

V

2.7

3.4

V
0.5

2.0

V
V

0.8

V

-1.2

V

Enable

-0.36

rnA

Data

-0.54

rnA

Enable

20

IJ-A

Data

30

IJ-A

100

IJ-A

Military

-20

-55

rnA

Commercial

-18

-60

rnA

70

rnA

80

rnA

DS26S10
DS26S11

2·25

Units

Commercial

-18 rnA

= Max, VIN = 2.7V

Max

45

:E
,...

,...
en
CD
N
en
C
.......
o,...
,...
en
CD
N
en

Bus Input/Output Characteristics
Symbol

Conditions
(Note 1)

Parameter

Military

Output Low Voltage

VOL

Vee = Min

C
.......

Commercial

:E
o
,...

en
CD
N
en

C
.......

o

o
,...
en
CD
N
en
C

Vee = Max

0.33

0.5

0.42

0.7

10L = 100 mA

0.51

0.8

10L = 40 mA

0.33

0.5

10L = 70mA

0.42

0.7

10L = 100 mA

0.51

0.8

V

Military

Vo = 4.5V

200

Commercial

Vo = 4.5V

100

/-LA

100

Bus Leakage Current (Power OFF)

Vo = 4.5V

VTH

Receiver Input High Threshold

Bus Enable = 2.4V,
Vee = Max

Receiver Input Low Threshold

10L = 40 mA
10L = 70 mA

-50

10FF

VTL

Units

Max

Vo = 0.8V

Bus Leakage Current

10

Typ
(Note 2)

Min

Bus Enable = 2.4V,
Vee = Min

Military

2.4

2.0

Commercial

2.25

2.0

Military

/-LA
V

1.6

2.0

V

2.0
1.75
Commercial
Note 1: For conditions shown as min or max, use the appropriate value specified under Electrical Characteristics for the applicable device type.
Note 2: Typical limits are at Vee = 5V, 25'C ambient and maximum loading.
Note 3: Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.

Switching Characteristics (TA =
Symbol

25°C, Vee = 5V)
Min

Conditions

Parameter

Typ

Max

Units

tpLH

Data Input to Bus

10

15

ns

tpHL

Data Input to Bus

10

15

ns

tpLH

Data Input to Bus

12

19

ns

tpHL

Data Input to Bus

12

19

ns

tpLH

Enable Input to Bus

14

18

ns

tpHL

Enable Input to Bus

13

18

ns

tpLH

Enable Input to Bus

15

20

ns

tpHL

Enable Input to Bus

14

20

ns

tpLH

Bus to Receiver Out

15

ns

tpHL

Bus to Receiver Out

Rs = 50n, RL = 280n, Cs = 50 pF (Note 1),
CL = 15 pF

10
10

15

ns

tr

Bus

Rs = 50n, Cs = 50 pF (Note 1)

Rs = 50n, Cs = 50 pF (Note 1)

0526510

0526511

0526510

0526511

Bus
Note 1: Includes probe and jig capacitance.

tl

4.0

10

ns

2.0

4.0

ns

Truth Tables
OS26S11

OS26S10
Inputs

E

B

Outputs

Inputs

Outputs

I

z

L
H
L
L
L
L
H
H
Y
X
Y
H
H = High voltage level
L = Low voltage level
X = Don't care
Y = Voltage level of bus (assumes control by another bus transceiver)
2-26

E

I

B

z

L
L
H

L
H
X

L
H

H
L

y

Y

c
en
0')
en

Typical Application
STROBE

STROBE

INPUTS

N

INPUTS

....A.

STROBE

STROBE

o

o
.......

10 1,

12

13

E

ZO

ZO
OS26S10

ZI

RECEIVER
OUTPUTS

RECEIVER
OUTPUTS

Z2

OS26S11

}

}

Z3

ZI
Z2

RECEIVER
OUTPUTS

OS26S11

ZI
Z2

}

Z3

Z3

}""".."
OUTPUTS

5V

5V
100

100

100

100

100

100
100

100
100 PARTY·LlNE OPERATION

c
en
N
0')
en
....A.

o
3:
.......

c
en
N
0')
en
....A.
....A.

o
.......

c
en
0')
en
N

TL/F/5802-5

....A.
....A.

AC Test Circuit and Switching Time Waveforms
Vee

ZTEST
POINT

3:
Vee

PULSE

GENERATOR
NO.1

All OIODES
lN916 OR
EQUIVALENT

PULSE
GENERATOR
NO.2

TLIF/5802-6
Note 1: Includes probe and jig capacitance.

•

3V----------.~--------~

OS26S11

TlNPUT
OV _____. I

3V----"'"
OS26S10

TlNPUT
DV--------+-,----------J
3V--------+-------------+------------~--------~

[INPUT

OV--------+-------------+---------'
VOH----------~-~----------"'"

ii TEST POINT
VOL - - - - - - - - - - '
PHL

-_J-__
V\ ------'!t

VOH _ t

ZTESTP',"T

'PL"

, .•

VOL

\'--~/
TL/F/5802-7

2-27

:iE
,...

,... Typical Performance Characteristics

(/)

CD

C'I

Typical Bus Output Low Voltage vs Ambient Temperature

(/)

Q

........

1.0

o
,...

,...

(/)
CD

0.8

~>

0.6

C'I

'""'

Q

~

(/)

........

~
'"::>

::E
Q
,...

yICC.l5Y

E
...

...

(/)

2.5

~

2.3 I-2.2

;

-

~

_IIBUS.l00 mA
IBUS· 70 mA

0.4

IBUS· 40 mA

III

I

E
...
~

I

CD

>

C'I

I·

o

Q

-55 -35 -15 5 25 45 65 85 105 125

o
Q

TA - AMBIENT TEMPERATURE ('C)

........

,...

t-Y~C·15.5J
I

YCC·5.25Y

~
I-

1.9

ffi
>

1.8

I
vCc·4.5V

1.7
1.6

I

Q

(/)

I

2.4

2.1
2.0

§a:

0.2

Receiver Threshold Variation
vs Ambient Temperature

I

r-

Yc~ .l.nv ~ COM'l
-Mll~ I-- ~
./

-

I

~ 1.5
-55 -35 -15 5 25 45 65 85 105 125
TA - AMBIENT TEMPERATURE ('C)
TLfF/S802-9

TLfF/S802-8

(/)
CD

C'I

Schematic Diagram

(/)

Q

110

3, (6),

(10),(14)

......~.-oz
4,(5),
(11),(13)
To----.~~~~~

Vee = Pin 16
GNO 1 = Pin 1
GNO 2 = Pin 8
Connect for 0526510
·Remove R1, 01,01 for 0526510

TL/F/S802-10

2-28

c

en
CI.)

~National

Q)
Q)

~ Semiconductor

N

OS3662 Quad High Speed Trapezoidal™ Bus Transceiver
General Description

Features

The DS3662 is a quad high speed Schottky bus transceiver
intended for use with terminated 1200 impedance lines. It is
specifically designed to reduce noise in unbalanced transmission systems. The open collector drivers generate precise trapezoidal waveforms with rise and fall times of 15 ns
(typical), which are relatively independent of capacitive
loading conditions on the outputs. This reduces noise coupling to the adjacent lines without any appreciable impact
on the maximum data rate obtainable with high speed bus
transceivers. In addition, the receivers use a low pass filter
in conjunction with a high speed comparator, to further enhance the noise immunity. Tightly controlled threshold levels on the receiver provide equal rejection to both negative
and positive going noise pulses on the bus.

• Pin to pin functional replacement for DS8641
• Guaranteed AC specifications on noise immunity and
propagation delay over the specified temperature and
supply voltage range
• Temperature insensitive receiver thresholds track bus
logic level
• Trapezoidal bus waveforms reduce noise coupling to
adjacent lines
• Precision receiver thresholds provide maximum noise
immunity and symmetrical response to positive and
negative going pulses
• Open collector driver output allows wire-OR connection
• High speed Schottky technology
• 15 p.A typical bus termination current with normal Vee
or with Vee = OV
• Glitch free power up/down protection on the driver output
• TTL compatible driver and disable inputs, and receiver
outputs

The external termination is intended to be a 1800 resistor
from the bus to 5V logic supply, together with a 3900 resistor from the bus to ground. The bus can be terminated at
one or both ends. A two input NOR gate is provided to disable all drivers in a package simultaneously.

Block and Connection Diagram
Dual-In-Llne Package

Vee

BUS 1

IN 1

OUT1

BUS2

IN 2

OUT 2 DISABLE A

Tl/F/5803-1

Top View
Order Number DS3662J or DS3662N
See NS Package Number J16A or N16A

2-29

N
CD
CD

Absolute Maximum Ratings

C")

(J)

C

Recommended Operating
Conditions

(Note 1)

If MilitaryI Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Supply Voltage

7V

Input and Output Voltage
Storage Temperature Range

5.5V
- 65°C to

Maximum Power Dissipation* at 25°C
Cavity Package
Molded Package

Electrical Characteristics

I

Parameter

DRIVER AND DISABLE INPUTS
VIH

Logical "1" Input Voltage

VIL

Logical "0" Input Voltage

II

Logical "1" Input Current

IIH

Logical "1" Input Current

IlL

Logical "0" Input Current

Input Diode Clamp Voltage
VCL
DRIVER OUTPUTIRECEIVER INPUT

+ 150°C

1509 mW
1476 mW

Lead Temperature (Soldering, 4 sec.)

Symbol

Units
Max
Min
4.75
5.25
V
Supply Voltage (Vce>
70
Temperature Range (TA)
0
°C
"Derate cavity package 10.1 mWI'C above 25'C; derate molded package
11.B mWI'C above 25'C.

260°C
(Notes 2 and 3)

I

I Min I

Conditions

Typ

I

I Units

Max

V

2.0

= 5.5V
VIN = 2.4V
VIN = O.4V
ICLAMP = -12 mA

O.B

V

1

mA

40

VIN

= O.BV, VIN = 2V, Isus = 100 mA
= O.BV, VBUS = 4V, Vcc = 5.25V
VIN = O.BV, VBUS = 4V, Vcc = OV
VIN = O.BV, VOL = 16 mA
VIN = O.BV, 10H = -400/-LA

-1

-1.6

/-LA
mA

-O.B

-1.5

V

VOLB

Low Level Bus Voltage

VDIS

0.6

0.9

V

IIHB

Maximum Bus Current

VIN

10

100

/-LA

100

/-LA
V

1.50

V

0.35

0.5

V

-70

-100

mA

50

90

mA

IILB

Maximum Bus Current

VIH

High Level Receiver Threshold

Low Level Receiver Threshold
VIL
RECEIVER OUTPUT

1.90

1.70

= O.BV, VBUS = 0.5V, 10H = -400/-LA
= O.BV, VSUS = 4V, 10L = 16 mA
VOIS = O.BV, VIN = O.BV, VBUS = 0.5V,
Vas = OV, Vcc = 5.25V, (Note 4)
VOIS = OV, VIN = 2V

VOH

Logical "1" Output Voltage

VIN

VOL

Logical "0" Output Voltage

VIN

los

Output Short Circuit Current

Icc

Supply Current

1.70

2.4

3.2

-40

V

Switching Characteristics (Notes 2 and 3)
Symbol

I

Parameter

PROPAGATION DELAYS
tpLHO

Disable to Bus "1"

tpHLO

Disable to Bus "0"

tpLHB

Driver Input to Bus "1"

tpHLB

Driver Input to Bus "0"

tpLHR

Bus to Logical "1" Receiver Output

I

Conditions

I

Min

Figure 1
Figure 2
Figure 3

Bus to Logical "0" Receiver Output
tpHLR
NOISE IMMUNITY
trB. tIB

Rise and Fall Times (10%-90%)
of the Driver Output

Figure 2

10

I

Typ

I

Max

I

Units

25

35

ns

25

35

ns

20

30

ns

20

30

ns

25

40

ns

25

40

ns

15

20

ns

No Response at Receiver
Receiver Noise Rejection
20
10
ns
Output as per Figure 4
Pulse Width
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics" and "Recommended Operating Conditions" provide conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the supply and temperature range listed in the table of "Recommended Operating Conditions". All
typical values are for TA = 25'C and Vee = 5V.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
tnR

2-30

c

en
w
Q)

AC Test Circuits and Switching Waveforms

Q)
I\)

5.0V
J.OV----t-~~---__=~

r---------,

91
DV
VOH----r--~~----+-~

5.0V~~~---...

Va

200

VOL----+--"
-

TL/F/5803-2

IpLHO
ENABlE TO BUS
(HIGH LEVell
TL/F/5803-3

Note: tr

=

tf

=

2.S ns. Pulse width

= sao ns measured between 1.SV levels. f =

1 MHz.

FIGURE 1. Disable Delays
5.0V
J.OV

r---------,

VI
91

OV
Va

VOH
Vo

VI

2,5, 1
L.

1
1 .J1
_________

200

VOL

11,14
TLIF/5803-4
TLIF/5803-5

Note: tr

=

tf

=

2.S ns. Pulse width

= sao ns measured between 1.SV levels. f =

1 MHz.

FIGURE 2. Driver Propagation Delays
5.0V
3.4V -------+~=---~~

r - - 1
1

-

-

,

390

OV---"';';'.J[·

13• 6,
110.13
><>---""I"';';";~-"'-""--VO

1,4.1
12.151
VI

RECeiVER -

1

1

~ - .! - - - - - - - ~

VOH-------~-,

r""

Vo

1.6k

VOL---------+---r-~-----+_--'

tpHLR
BUS TO LOGIC LOW LEVEL
RECEIVER OUTPUT

TL/F/5803-6

BUS TO LOGIC HIGH LEVEL
RECEIVER OUTPUT
TL/F/5803-7

Note: tr

=

tf

=

1S ns. Pulse width

= sao ns measured between 1.7V levels. f =

1 MHz.

FIGURE 3. Receiver Propagation Delays

2.5V --+r--,.I
VI

5.0V

OV

TL/F/5803-9

390

tr
120

I

~ -J-------~

r""

BUS LOGIC
LOW LEVEL

=

= 2.S ns
(a) Receiver Output (Vo) to
Remain Greater than 2.2V

tf

Uk

BUS LOGIC
HIGH LEVEL
TLIF/5803-8
TL/F/5803-10

tr

=

= 2.S ns
(b) Receiver Output (Vo) to
Remain Less than O.7V

tf

FIGURE 4. Receiver Noise Immunity: "No Response at Output" Input Waveforms

2-31

N

CD

~

U)

Typical Application

c

1200 Unified Data Bus
5V

5V

l ... _ _

390

"::"

I
I
I

r;/4iiS36&Z

11/4 OS366Z

I I

I
I

tilt

t_,' ... __

11/4 OS366Z

I

'- ____ ..1

I
I
I

.J

-,

11/4iiS36&Z

I

-,

I
I ,
I
I
I
I
I
,
I
, I
'- ____ .J L ____

I
I
I
I
I

.J
TLlF/5803-11

2-32

l>

z

National Semiconductor
Application Note 259
R. V. Balakrishnan

053662-The Bus
Optimizer

•

N

U1

CD

I. INTRODUCTION
A single ended Bus is an unbalanced Data Transmission
medium, which is timeshared by several system elements.
Like any unbalanced system, it is highly susceptible to common-mode noise, such as ground noise and crosstalk. In
general, the latter determines the maximum physical length
of the Bus that can be incorporated with acceptable reliability. Crosstalk is a major problem in high speed computer
Buses which employ Schottky Transceivers for increased
data rate capability. It is therefore highly desirable to minimize crosstalk noise in Bus circuits to allow for longer Buses
and to provide higher system reliability.
This article describes the operation of the DS3662 Quad
High Speed Trapezoidal Bus Transceiver, which has been
specially designed to minimize crosstalk problems. The
Driver generates precise Trapezoidal waveforms that reduce noise coupling to adjacent Bus channels. The Receiver uses a low pass filter, whose time constant is matched to
the Driver slew rate to provide maximum noise rejection with
acceptable signal delay characteristics. Precision high
speed circuitry optimizes noise immunity without sacrificing
the high data rate capability of Schottky Transceivers.

II. THE PROBLEM
Conventional Bus Drivers are designed to provide high output currents for charging and discharging relatively large
Bus capacitances quickly. These high speed transitions are
characterized by peak slew rates of up to 5V/ns around the
mid-region of the transition. This can cause considerable
noise coupling to adjacent lines, commonly referred to as
crosstalk. Crosstalk also includes noise induced by sources

external to the Bus. Additional noise may be generated due
to reflections at imperfect terminations.
Bus Receviers are designed to respond to high speed transitions and to provide low propagation delays. Unfortunately, their fast response results in high noise sensitivity. The
combined effect of the noise on the Bus and the sensitivity
of the Receiver to the noise severely limits the Bus performance.
III. THE SOLUTION
The above situation can be considerably improved by employing noise reduction techniques in both the Driver and
the Receiver circuits. Slew rate control can be used in the
Driver to reduce crosstalk, and Receiver noise sensitivity
can be reduced by using a low pass filter at its input. These
techniques are commonly used in line transmission circuits
where the associated data rates in general are considerably
lower. However, these techniques do present some difficulties in high speed Bus circuits. Increased rise and fall times,
resulting from slew rate control, can affect data rates unless
care is taken to limit the maximum rise and fall times to
minimum pulse width requirements. With any appreciable
slew rate control, the rise and fall times of the resulting Driver output waveform will be comparable to the pulse widths
at maximum data rates. This condition dictates high fidelity
of the transmitted waveform and precise Receiver thresholds at the middle of the Bus voltage swing in order to minimize pulse width distortion. Figure 1 illustrates the different
sources of pulse width distortion due to the trapezoidal nature of the signal.

~ DRIVER INPUT

~

Vo

DRIVER INPUT

Vo

-l-

-

I I
~

Vo/2- -

I
I

VTH

DRIVER OUTPUT
AND
RECEIVER INPUT

I
I

~

~

DRIVER OUTPUT
AND
RECEIVER INPUT

~

RECEIVER OUTPUT

Vo/2- -

RECEIVER OUTPUT

Vo

----

VTH

I

I

I
I

I
I

Vo

t

~

~
DRIVER OUTPUT
Vo/2:cr====~ ~~gEIVER INPUT

~

DRIVER OUTPUT
AND
RECEIVER INPUT

~ RECEIVER OUTPUT

~

RECEIVER OUTPUT

DISTORTION DUE TO OFF CENTERED
RECEIVER THRESHOLDS (VTH)

DISTORTlDN DUE TO NON SYMMETRICAL
TRAPEZOIDAL DRIVER OUTPUT WAVEFORM

I

I

Vo/2- -

I

I

TL/F/5657-1

--

VTH

I

I

I
I

I
I

.

TLIF/5657-2

FIGURE 1. Pulse Width Distortion

2-33

fII

en
II)
N

Z•



1Z0 g UNIFIED DATA BUS

+5V

Z

+5V

N

U1

CD

TL/F/5657-4

FIGURE 3. Bus Termination

SL

DRIVER INPUT

~ DRIVER OUTPUT

Vo __ Ir.
Vo/2
- - ~ tl
OV
I
I

I--jtpm

TL/F/5657-5



z

DS8641

I

I\)

CJ1

4V

..

3V

I

2V
IV

CD

~

W Lr

~/

M hi

OV
4V

j

1",,-

~

RECEIVER
INPUT

10 rEET

r-

~~

RECEIVER
OUTPUT

2V
OV
-- TIt.4E 100 NS/OIV

TL/F/5857-18

FIGURE 14

I II

~

1'-

\

~

III

10

'"

~

1=

:IE
~

134'

:IE

~

m:l~

:IE

~
o

!i

D 3662"

~~
1=

TERMIN

150~ ,D~
0.1

1

~~~~~

;yl~
10

r-

t\l
1902

34' ....... 1'

S j41 I-"

~

TWISTED PAIR CABLE
\22 AWG STRANDED~
ERMINATED 180/3 02
50% DUry,pYCLE

III

\

'\ 11111111
100

10

1000

F=

~

100

1000

LINE LENGTH (FTI

LINE LENGTH (FT.I

TL/F/5857-20

TL/F/5857-19

FIGURE 15. Data Rate vs. Line Length

2-39

Reducing Noise on
Microcomputer Buses

National Semiconductor
Application Note 337
R. V. Balakrishnan

Abstract: This paper focuses on the noise components that

a 'Z' as possible in order to reduce the drive requirement of
the bus driver and to reduce the power dissipated at the
terminations. But much larger values of 'Z" translate to significantly larger physical dimensions and therefore are not
very practical.
The bus appears like a transmission line to any signal having a transition time 'tr' less than the round trip delay '2TL' of
the bus, The bus delay 'T L' is given by:

have a significant impact on the performance of a high
speed microcomputer bus. An overview of their nature is
followed by ways to minimize their contribution by suitable
design of the PC board backplane, the termination network
and the bus transceiver. The DS3662 trapezoidal bus transceiver, which is specifically designed to minimize such noise
on high speed buses, is presented along with its performance data. And to conclude, some possible new transceiver
designs for further improvement of the bus performance are
explored.
INTRODUCTION

As the microcomputer bus bandwidth is extended to handle
ever increasing clock rates, the noise susceptibility of a single-ended bus poses a serious threat to the overall system
integrity. Thus, it is mandatory that the various noise contributions be taken into account in the design of the bus transceiver, the PC board backplane and the bus terminations to
avoid intermittent or total failure of the system.
Although noise such as crosstalk and reflections are inevitable in any practical bus configuration, their impact on the
system can be determined and minimized by careful design
of all three components mentioned above. The combined
contribution of the noise under worst-case conditions
should be within the noise margin for reliable bus operation.

h

= L~L1 C1

, (1)

where

L = length of the bus
L1 = distributed inductance per unit length
C1 = distributed capacitance per unit length
For a typical unloaded 1000. microstrip line, C1 ~ 20 pF/ft
and L1 ~ 0.2 p.H/ft. Therefore, T L = 2.0 ns/ft. This corresponds to approximately half the speed of light. However,
the capacitive loading at each connector on the backplane
increases the delay time significantly. The loaded delay time
'TLL' is given 'by:
(2)

where CL = distributed load capacitance/unit length

The design of the transceiver plays a significant role in minimizing crosstalk and reflection. The bus can be optimized
for minimum noise at a given bandwidth by using a trapezoidal driver having suitable rise and fall times along with a
matched low pass filtered receiver which provides a symmetrical noise margin. The DS3662 is one such transceiver,
the first member in the family of trapezoidal bus transceviers
available from National Semiconductor Corporation. This
device represents a significant improvement in high speed
bus circuit design and provides a solution to commonly encountered bus noise problems.
THE MICROCOMPUTER BUS

A typical microcomputer bus usually consists of a printed
circuit board backplane with signal and ground traces on
one side and a ground plane on the other. The length
ranges from a few inches to several feet with as many as 32
closely spaced (0.6" typical) card edge connectors. Each
signal line interacts with the ground plane to form a transmission line with characteristic impedance 'Z' in the range
of 900.-1200. typical. It is desirable to have as large

Given a 10 pF loading at each connector (connector +
transceiver capacitance) and a 0.6" spacing between connectors, CL = 200 pF 1ft and T LL = 6.6 nslft. So even a 6"
long bus has a 2TLL = 6.6 ns, which is higher than the
transition time (tr) of many high speed bus drivers. When in
doubt, it is always better to use the transmission line approach than the lumped circuit approach as the latter is an
approximation of the former. Also, the transmission line
analysis gives more pessimistic (worst-case) values of
crosstalk and reflection and is, hence, safer.
CROSSTALK REDUCTION

The crosstalk is due to the distributed capacitive coupling
Cc and the distributed inductive coupling Lc between two
lines. When crosstalk is measured on an undriven sense
line next to a driven line (both terminated at their characteristic impedances), the near end crosstalk and the far end
crosstalk have quite distinct features, as shown in Figure 1.
Their respective peak amplitudes are:

2-40

VNE = KNE(2T d(VI/tr) for tr > 2 T L
VNE = KNE(VI)
for tr < 2 TL
VFE = KFE(L)(VI/tr)
where VI = signal swing on the drive line.

(3)
(4)
(5)

The coupling constants are given by the expressions:
KNE = L(Ce Z + Le /Z )
4TL
CeZ - Le /Z
KFE =
2
nslft

1. The noise margin expressed as a percentage of the signal swing is what's important, not the absolute noise margin.
Therefore, to improve noise immunity, the percentage noise
margin has to be maximized. This is achieved by reducing
the receiver threshold uncertainty region and by centering
the threshold between the high and low levels.

(6)

(7)

The near end component reduces to zero at the far end and
vice versa. At any pOint in between, the crosstalk is a fractional sum of near and far end crosstalk waveforms shown.

2. Smaller signal amplitude with the same transition time
reduces bus drive requirements without reducing noise immunity.

It should be noted from expressions 6 and 7 that the far end
crosstalk can have either polarity whereas the near end
crosstalk always has the same polarity as the signal causing
it. In microstrip backplanes the far end crosstalk pulse is
usually the opposite polarity of the original signal.

3. Far end crosstalk is eliminated if the receiver is designed
to reject pulses having pulse widths less than or equal to t r.
4. When tr < 2TL, the near end crosstalk immunity for a
given percentage noise margin has to be built into the backplane PC layout. Since (VNEIVI) = KNE for this case, KNE
should be kept lower than the available worst-case noise
margin. KNE may be reduced by either increasing the spacing between lines or by introducing a ground line in between. The ground line, in addition to increasing the spacing
between the signal lines, forces the electric field lines to
converge on it, significantly reducing crosstalk.

Although the real world bus is far from the ideal situation
depicted in Figure 1, several useful observations that apply
to a general case can be made:
1. The crosstalk always scales with the signal amplitude.
2. Absolute crosstalk amplitude is proportional to slew rate
Vl/tr, not just 1/tr•

5. For minimum crosstalk the rise and fall times of the signal
waveform should be as large as possible consistent with the
minimum pulse width requirements of the bus. A driver that
automatically limits the slew rate of the transition can go a
long way in reducing crosstalk.

3. Far end crosstalk width is always t r.
4. For tr < 2TL, the near end crosstalk amplitude VNE expressed as a fraction of signal amplitude VI is a function of
physical layout only.
5. The higher the value of 'tr' the lower the percentage of
crosstalk (relative to signal amplitude).
The corresponding design implications are:

----iU--L---(I'1

111>--~

~~~~C::>~-RT-JE_~~I----------------------~i1~----_DR_IV_E_N_lI_N-E------~1--71-1~'T

~I

SENSE LINE

I
I

~-

----Y

~

v,

__ VNE=KNE2TLTr fo rt r>2TL

t

= KNE VI

for tr<2TL

II ~~ I
1£-

KFEL
II_VFE=t
Vtrl

l-tr+2TL-1
-trFAR END CROSSTALK

NEAR END CROSSTALK

TL/F/5281-1

FIGURE 1. Crosstalk under Ideal Conditions

2-41

CROSSTALK MEASUREMENT

THE TERMINATION

When multiple lines on either side of the sense lines switch
simultaneously the crosstalk is considerably larger, typically
3.5 times the single line switching case for microstrip backplanes. Also, the location of the drivers on the driven lines
and the receiver on the sense line for worst-case crosstalk
differs for the near end and far end cases as shown in Figure 2 and 3 for a uniformly loaded bus. But if the far end
crosstalk is not of the opposite polarity, then the combined
effect of far end and near end crosstalk could have a larger
amplitude and pulse width at a point near the middle of the
sense line in Figure 2. So in a general case, or in the case of
a non-uniformly loaded bus, it is advisable to check the
sense line at several locations along the length of the bus to
determine the worst-case crosstalk. The measurement
should be made for both the positive and the negative transition of the drive signal.

A properly terminated transmission line has no reflections.
But a practical microcomputer bus is neither a perfect transmission line nor is it properly terminated under all conditions. The capacitive loading at discrete locations, such as a
used card slot, act as sources of reflection. However, in the
limiting case when the bus is uniformly populated with a
large number of modules, the bus behaves like a lower impedance transmission line. The loaded impedance 'Zl' of
the bus is given by the expression:

Z

Zl =

(8)

~1 + Cl/C1

where Z = unloaded line impedance
Unfortunately, uniform loading of the bus is not guaranteed
at all times and even if it were (by dummy loading of

r-------------------BUS

PULSE
INPUT

~~--------------------------

~--------------------S-EN-S-E-L1-NE--------------------.~ ~

~\ ~----------------------------------------------_4 SENSE
\\~--------------------------­
~-------------------Note: All lines terminated at both ends (not shown)

FIGURE 2. Worst-Case Far End Crosstalk Measurement

SENSE LINE

\

------------~----------Note: All lines terminated at both ends (not shown)

FIGURE 3. Worst-Case Near End Crosstalk Measurement

2-42

TLIF/52Bl-3

TL/F/52Bl-2

the unused slots) ZL is usually too low for proper termination
of the bus. For example, a 10 pF per module loading of the
1000 microstrip bus at 0.6" spacing results in a ZL = 300.
One such termination at each end will require a 200 mA
drive capacity on the bus driver for a nominal 3V swing.
Such large drive currents and low value terminations increase the power dissipation of the system significantly in
addition to causing other problems such as increased
ground drop, inductive drops in traces due to large current
being switched, etc. As a compromise the bus is usually
terminated at an impedance higher than ZL but less than or
equal to Z. Consequently, there is always some amount of
reflection present. For a perfect transmission line the reflection coefficient T' is given by the well known expression:

r =Z Z+

This value of the initial swing is large enough to cross the
narrow threshold region of the receiver as shown and therefore no waiting period is required for the reflections to build
up the output high level. On the negative transition the problem is less critical due to the much higher sink capability of
the OS3662 during pull down.
Aeflections can also be caused by resistive loading of the
bus by the OC input current of the receiver. The resulting
reflectoin coefficient (r) is given by the expression:

r

-%

(~)

(11 )

where IR = receiver input current
Having a receiver with a high input impedance not only
makes this component of reflection insignificant but also reduces the OC load on the driver, allowing the use of lower
value termination resistors. This is particularly true when a
large number of modules are connected to the bus.

(9)

At
At

=

where Z = impedance of the bus
At = termination resistance

The design implications of the above discussion may be
summarized as follows:

The net effect, in the general case of a nonuniformly loaded
bus, is that it may take several round trip bus delays after a
bus driver output transition, before the quiescent voltage
level is established. However, this delay is avoided by using
a bus driver that has sufficient drive to generate a large
enough voltage step during the first transition to cross well
beyond the receiver threshold region under the worst-case
load conditions.

1. If the driver has adequate drive to produce the necessary
voltage swing under the worst-case loading (ZL/2), reflections do not restrict the bus performance. This translates to
a 100 mA minimum drive requirement for a typical microstrip
bus.
2. If the drive is insufficient, time should be allowed for the
reflections to build up the voltage level before the data is
sampled.

Figure 4 illustrates the driver output waveform under such a
condition. Here the fully loaded bus (with ZL = 300), of the
previous example, is driven by the OS3662 bus transceiver
at the mid point. The driver is actually driving two transmission lines of ZL = 300 in either direction from the middle
and hence the initial step is given by:

3. For signals such as clock, strobe, etc., wherein the edge
is used for triggering events, it is mandatory that the driver
meet the above drive requirements if delayed or multiple
triggering is to be avoided.
4. An ideal TTL bus transceiver should have at least a
100 mA drive, a high input impedance receiver with a narrow threshold uncertainty region.

(10)

where Is = Standing current on the bus due to each
termination
For the OS3662, the termination can be designed for 21s =
100 mA and therefore:
V1 = (30/2)100 = 1.5V

I-ZTL
Z.ZV----1.9 V

1.5V

MAX-I

I

t

2'Z2Z22Z22Z22Z22~~~Z22~Z22Z22Z22Z22::ZZZ22:zzz- THRESHOLD

I

RANGE,

VI = 100 mA X 15!l = 1.5V

VI
VOL=D.7V _ _ _ _ _.....

_---Ll
TLIF/52Bl-4

FIGURE 4. Worst-Case OS3662 Output Transition for ZL = 150 and RT = 500

2-43

THE OS3662 TRANSCEIVER
The OS3662 quad trapezoidal bus transceiver has been designed specifically to minimize the noise problems discussed previously. The driver generates precise trapezoidal
waveforms that reduce crosstalk and the receiver uses a
low pass filter to reject noise pulses having pulse widths up
to the maximum driver output transition times. Precision output circuitry optimizes noise immunity without sacrificing the
high data rate capability of Schottky transceivers.

Using a Miller integrator circuit, the driver generates a linearly rising and falling waveform with a constant slew rate of
0.2 V Ins (Figure 6). This corresponds to a nominal transition
time of 15 ns. Figure 7 compares the output waveform of a
typical high speed driver to that of OS3662 under different
load conditions. It should be noted that even under heavy
loading; the regular drivers have peak slew rates that are
much higher than the average. On the other hand, the trapezoidal waveform has a much lower slew rate with only a
slight increase in the transition time. Such an increase in the
transition time has little or no effect on the data rates. In
fact, the high fidelity of the OS3662 driver output waveform
allows pulse widths as low as 20 ns to be transmitted on the
bus.

Figure 5 shows the recommended configuration for microcomputer buses. The use of a 3.4V source with a single
termination resistor at each end reduces the average power
dissipation of the bus. However, a two resistor termination
connected between the line and the power rails, having the
same Thevenin's equivalent, can be substituted for lower
cost.

RT
3.4V o-.JVttI'v--t-----t----.....
'I. DS36.r62==---L_--':;

----+-<. . . W'v-O 3.4V

TL/F/5281-5

RT = son to 90n

FIGURE 5. Recommended Bus Termination for Heavily Loaded Microstrlp Backplanes

INPUT

1

f'

0---

s__....._ .......
JOUTPUT

SLEW RATE
":" VTH

=2VBE

FIGU~E

=IIC
TL/F/5281-7

6. OS3662 Driver

TLlF/5281-6

.ate1: Typical high speed driver output unloaded; tr
lIIate 2: Typical high speed driver output loaded; tr

= tf ::::: 3 ns

= 4 ::::: 10 ns

Nate 3: Typical outupt of controlled slew rate driver which is load independent; tr

FIGURE 7. Waveform Comparison

2-44

= tf ::::: 15 AS

The receiver consists of a low pass filter followed by a high
speed comparator, with a typical threshold of 1.7V (Figure
8). The noise immunity of the receiver is specified in terms
of the width of a 2.5V pulse that is guaranteed to be rejected
by the receiver. The receiver typically rejects a 20 ns pulse
going positive from the ground level or going negative from
the 3.4V logic 1 level. The receiver threshold lies within a
specified 400 mV region over the supply and temperature
range and is centered between the low and high levels of
the bus for a symmetrical noise margin.
INPUT

Waveforms in Figure 9 demonstrate the ability of the receiver to distinguish the trapezoidal signal from noise. Here the
receiver rejects a noise pulse of 19 ns width, while accepting a narrower signal pulse (16 ns) of the same peak amplitude (the signal is triangular because of the pulse width
which is smaller than the transition time).
The real-world performance of the D83662 transceiver
shows an order of magnitude improvement in noise immunity over conventional transceivers under actual operating
conditions (Reference # 3). The controlled rise and fall
times on the driver output significantly reduces both near
end and the far end crosstalk. As expected, the pulse discrimination at the receiver input virtually eliminates the far
end crosstalk, even on extremely long buses (over 100
feet). The near end crosstalk, which is particularly severe on
the state of the art backplanes due to the tight spacing between the signal lines, is easily accommodated by the large
percentage noise margin (> 75%) provided by the receiver.

-W~~-I

OUTPUT

Field reports indicate that the 083662 not only solves those
mysterious intermittent failure problems in mini and microcomputer systems, but also helps them meet the new FCC
emission requirements due to the reduced RF radiation from
the bus.

TL/F/5281-8

FIGURE 8. 053662 Receiver
Other features of the device include a 100 J-LA maximum DC
bus loading specification under power ON or OFF condition
and a glitch-free power up/down protection on the bus output.
4V
3V

RECEIVER
OUTPUT

2V

,

-- ......

.r

('- ~

;\

IV

\J

OV

4V

v

~-

/ 1\

\

3V

RECEIVER
INPUT

2V
OV

NOISE INPUT

-

/
>-J

\

I

I~ ~ .--...
SIGNAL INPUT

TIME IONS/DIV

TL/F/5281-12

FIGURE 9. 053662 Receiver Response
+5V

TRAPEZOIDAL
DRIVER

1
2RT

2.5V
2RT

TRAPEZOIDAL
RECEIVER

25V - - 1.;5V
1V

I

=.7

\
tr=tl==6ns

c=

VTH

...l.. CR==

T

1T0 2pF

*"

TLIF/5281-21

FIGURE 10. High 5peed Bus Transceiver with Low Output Loading for MicroComputer Backplanes
2-45

......

.

C")
C")

z

-...-+-+-.....;;.3 82

Data Transceivers

TE

PE

Mode

Bus Port

Terminal Port

H

H

T

Totem-Pole
Output

Input

H

L

T

Open
Collector
Output

Input

L

H

R

Input

Output

L

L

D

TRI-STATE

TRI-STATE

H: High Level Input
L: Low Level Input
T: Transmitting Mode
R: Receiving Mode
D: Dumb Mode

TERMINAL

BUS

">-....-+-+-.....:..7 B6

Note 1 : + Denotes driver
Note 2: ~ Denotes receiver
TL/F/5245-2

2-48

c

Absolute Maximum Ratings

If Military I Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Supply Voltage (Vce)

Vcc, Supply Voltage
TA, Ambient Temperature

7.0V

Input Voltage
- 65·C to

Maximum Power Dissipation· at 25·C
Molded Package
Lead Temperature (Soldering, 4 seconds)
"Derate molded package 14.7 mWI'C above 25'C.

Min
4.75

Max
5.25

0

70

Units
V
·C

48
16

mA
mA

10L' Output Low Current
Bus
Terminal

5.5V

Storage Temperature Range

en
w

Operating Conditions

(Note 1)

+ 150·C

1832 mW
260·C

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Conditions

Min

Typ

Max

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

VIK

Input Clamp Voltage

VHYS

Input Hysteresis

Bus

VOH

High Level
Output Voltage

Terminal
Bus

Low Level
Output Voltage

Terminal

10L = 16 mA

0.3

0.5

Bus

10L = 48 mA

0.4

0.5

High Level
Input Current

TE, PE

VI = 5.5V

0.2

100

VI = 2.7V

0.1

20

VOL

IIH

2

-0.8
400

500

10H = -800/J-A

2.7

3.5

10H = -5.2 mA

2.5

3.4

VI = 4V
VI = 0.5V

Low Level
Input Current

Terminal
andTE, PE

los

Short Circuit
Output Current

Terminal

Supply Current

V
V
mV
V

V

200
-10

-100

/J- A
mA

-0.4

-1.0

-15

-35

-75

-50

-120

-200

Transmit, TE = 2V, PE = 2V, VI = 0.8V

75

100

Receive, TE = 0.8V, PE = 2V, VI = 0.8V

65

90

Bus

Icc

-1.5

/J- A

Terminal
and Bus
IlL

V
0.8

11= -18mA

Units

VI = 2V, Va = OV (Note 4)

Bus

mA

mA

Bus-Port
Bus
Vcc = OV, VI = OV,
20
30
pF
Capacitance
f = 10 kHz (Note 5)
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operations.
Note 2: Unless otherwise specified, min/max limits apply across the O'C to + 70'C temperature range and the 4.75V to 5.25V power supply range. All typical
values are for TA = 25'C and Vee = 5.0V.
Note 3: All currents into device pins are shown as positive; all currents out of device pins are shown as negative; all voltages are referenced to ground, unless
otherwise specified. All values shown as max or min are so classified on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: This parameter is guaranteed by design. It is not a tested parameter.

CIN

\

2-49

0')
0')

.......

.....
CD
CD

C")

(J)

c

Switching Characteristics Vee =
Symbol

Parameter

5.0V ±5%, TA = O·Cto +70·C (Note 1)

From

Conditions

To

Propagation Delay Time,
Low to High Level Output
Terminal

Bus

Propagation Delay Time,
High to Low Level Output
Propagation Delay Time,
Low to High Level Output
Propagation Delay Time,
High to Low Level Output
tPZH

Output Enable Time
to High Level
Output Disable Time
to High Level

tPZL

TE

Bus

Output Enable Time
to High Level
Output Disable Time
to High Level

tPZL

TE,PE

Terminal

tpHZ

Output Pull-Up Enable
Time

PE

Output Pull-Up Disable
Time

Note 1: All typical values are for TA

=

25'C, Vee

ns

14

20

ns

15

20

ns

10

20

ns

19

30

ns

15

20

ns

24

40

ns

17

30

ns

19

35

ns

17

25

ns

27

40

ns

17

30

ns

10

20

ns

10

20

ns

VI = 3V
VL = OV
RL = 4800
CL = 15 pF
(Figure 1)

Bus

(Notes 2 and 3)

=

20

VI = OV
VL = 5V
RL = 2800
CL = 15 pF
(Figure 1)

Output Disable Time
to Low Level
tPZH

10

VI = 3.0V
VL = OV
RL = 3 kO
CL=15pF
(Figure 1)

(Notes 2 and 3)

Output Enable Time
to Low Level

Units

VI = OV
VL = 2.3V
RL = 38.30
CL = 15 pF
(Figure 1)

Output Disable Time
to Low Level
tpZH

Max

VI = 3.0V
VL = OV
RL = 4800
CL = 15 pF
(Figure 1)

(Notes 2 and 3)

Output Enable Time
to Low Level

Typ

VL = 5.0V
RL = 2400
CL = 30 pF
(Figure 2)

Terminal

Bus

Min

VL = 2.3V
RL = 38.30
CL = 30 pF
(Figure 1)

5V.

Note 2: Refer to Functional Truth Table for control input definition.
Note 3: Test configuration should be connected to only one transceiver at a time due to the high current stress caused by the VI voltage source when the
output connected to that input becomes active.

Switching Load Configurations

4·4. RL

TEST
DEVICE
1N914

TEST
DEVICE
VI

0-

IN

Vc

0-

CONTROL

OUT
Vc

0-

-1..1 ......

~ CL* ~, 1N914

CONTROL

..L
":"
Ve logic high
TL/F/5245-3

4

1 - -.............1-.

= 3.0V

Ve logic low = OV

Ve logic high = 3.0V

-~

-~

, 1N914

~, 1N914

-~

Ve logic low = OV
TL/F/5245-4

'CL includes jig and probe capacitance

'CL includes jig and probe capacitance

FIGURE 1

FIGURE 2
2-50

c

en

Switching Waveforms

w

Transmit Propagation Delays
3.GV

l

.,----------_

1.5v

- : 5 1 •5V

TERMINAL
(INPUT)*

m
m
.......

OV

----~L

.W
BUS
(OUTPUT)

TL/F/5245-5

Receive Propagation Delays

(lNP~~r

'r----------_.

3.0V

OV

f·5V

--::::::.J

1.5V\ _ _ _ __

~

tpLH

tpHL

TERMINAL
(OUTPUT)
TL/F/5245-6

Terminal Enable/Disable Times
3V
CONTROL*
INPUT

OV

TERMINAL
OUTPUT

TERMINAL
OUTPUT
TL/F/5245-7

Bus Enable/Disable Times
3V
CONTROL*
INPUT

OV

BUS
OUTPUT

BUS
OUTPUT
TL/F/5245-B

'Input signal: f

= 1.0 MHz, 50% duty cycle, tr = tf :s:

2-51

5 ns

~

CD
CO

r-------------------------------------------------------------------------------------,

en ~National
c

PRELIMINARY

('t)

~ Semiconductor
OS3862 Octal High Speed Trapezoidal Bus Transceiver
General Description

Features

The 053862 is an octal high speed schottky bus transceiver
intended for use with terminated 120n impedance lines. It is
specifically designed to reduce noise in unbalanced transmission systems. The open collector drivers generate precise trapezoidal waveforms with rise and fall times of 9 ns
(typical), which are relatively independent of capacitive
loading conditions on the outputs. This reduces noise coupling to the adjacent lines without any appreciable impact
on the maximum data rate obtainable with high speed bus
transceivers. In addition, the receivers use a low pass filter
in conjunction with a high speed comparator, to further enhance the noise immunity. Tightly controlled threshold levels on the receiver provide equal rejection to both negative
and positive going noise pulses on the bus.

• Guaranteed A.C. specifications on noise immunity and
propagation delay over the specified temperature and
supply voltage range
• Temperature insensitive receiver thresholds track bus
logic level and respond symmetrically to positive and
negative going pulses
• Trapezoidal bus waveforms reduce noise coupling to
adjacent lines
• Open collector driver output allows wire-or connection
• Advanced low power schottky technology
• Glitch free power up/down protection on driver and receiver outputs
• TTL compatible driver and control inputs, and receiver
outputs
• Control logic is the same as the 053896

The external termination is intended to be a 180n resistor
from the bus to 5V logic supply, together with a 390n resistor from the bus to ground. The bus can be terminated at
one or both ends.

Logic and Connection Diagram
OS3862

A2

A3

A4

Vee

2

19 B2

3

18

4

17

5

16

15

A5

14

A6

A7

A8

8

13

9

12

83

B4

GND

B5

Order Number OS3862J or OS3862N
See NS Package Number J20A or
N20A

B6

B7

B8

TL/F/B539-1

2-52

C

Absolute Maximum Ratings

en
(,)

Recommended Operating
Conditions

(Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Offlce/
Distributors for availability and specifications.
Supply Voltage
6V
Control Input Voltage
5.5V
Driver Input and Receiver Output
5.5V
Receiver Input and Driver Output
5.5V
Power Dissipation
1400 mW
- 65·C to + 150·C
Storage Temperature Range
Lead Temperature (Soldering, 4 seconds)
260·C

Supply Voltage,Vcc
Operating Free Air Temperature

Min
4.75
0

CO

en
N

Max
5.25
70

Units
V
·C

Electrical Characteristics o·c ~ TA ~ 70·C, 4.75V ~ Vee ~ 5.25V unless otherwise specified (Notes 2 and 3)
Symbol

Parameter

Conditions

Min

Typ

Max

Units

Driver and Control Inputs:
2.0

VIH

Logical "1" Input Voltage

Vil

Logical "0" Input Voltage

II

Logical "1" Input Current

An = Vcc

IIH

Logical "1" Input Current

An = 2.4V

III

Logical "0" Input Current

An = O.4V

III

CD & T /R Logical "0" Input Current

VCl

Input Diode Clamp Voltage

V
O.B

V

1

rnA

40

Il A

-1

-1.6

rnA

CD = T/R = O.4V

-1BO

-400

IlA

Iclamp = -12 rnA

-0.9

-1.5

V

Driver Output/Receiver Input
VOLS

Low Level Bus Voltage

An = T/R = 2V, Ibus = 100 rnA

0.6

0.9

V

IIHS

Logical "1" Bus Current

An = O.BV, Bn = 4V, Vcc = 5.25V and OV

10

100

IlA

100

IlA

1.9

V

IllS

Logical "0" Bus Current

An = O.BV, Bn = OV, Vcc = 5.25V and OV

VTH

Input Threshold

Vcc = 5V

1.5

Bn = 0.9V, loh = - 400ilA

2.4

1.7

Receiver Output
VOH

Logical "1" Output Voltage

VOL

Logical "0" Output Voltage

Bn = 4V, 101 = 16 rnA

los

Output Short Circuit Current

Bn = 0.9V

-40

3.2

V

0.35

0.5

V

-70

-100

rnA

135
90
rnA
Supply Current
Vcc = 5.25V
Note 1: "Absolute Maximum Ratings" are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that device should be
operated at these limits. The table of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise
specified.
Note 3: All typicals are given for Vee = 5V and TA = 25'C.

Icc

2-53

•

Switching Characteristics o·c ~ T A ~ 70·C, 4.75V ~ Vee ~ 5.25V unless otherwise specified
Symbol

Parameter

Min

Conditions

Typ

Max

Units

12

20

ns

12

20

ns

Driver:
tOLH

An to Bn

CD

=

O.BV, TfR

=

2.0V, VL

=

5V

(Figure 1)

tOHL
tOLHC

CDto Bn

An

=

TfR

=

2.0V, VL

=

(Figure 1)

5V,

12

20

ns

15

25

ns

20

30

ns

25

40

ns

4

9

20

ns

4

9

20

ns

tOHLC
tOLHT

TfR to Bn

tOHLT
tR

Driver Output Rise Time

tF

Driver Output Fall Time

VCI = An, VC = 5V,
(Figure 2)
CD = O.BV, RC = 390!l, CL = 30 pF
RL1 = 91!l, RL2 = 200!l, VL = 5V
CD

=

O.BV, TfR

=

2V, VL

=

5V

(Figure 1)

Receiver:
Bn toAn

CD

=

O.BV, T fR = O.BV

(FigureS)

15

25

ns

15

25

ns

Bn = 2.0V, TfR = O.BV, CL = 5 pF
RL 1 = 390!l, RL2 = NC, VL = 5V (Figure 4)

15

25

ns

tRZLC

Bn = 2.0V, T fR = O.BV, CL = 30 pF
RL 1 = 390!l, RL2 = 1.6K, VL = 5V (Figure 4)

10

20

ns

tRHZC

Bn = O.BV, T fR = O.BV, VL = OV,
RL 1 = 390!l, RL2 = NC, CL = 5 pF(Figure 4)

5

10

ns

tRZHC

Bn = O.BV, TfR = O.BV, VL = OV,
RL 1 = NC, RL2 = 1.6K, CL = 30 pF (Figure 4)

B

15

ns

VCI = Bn, VC = 3.4V, RC
CD = O.BV, VL = 5V, RL 1
RL2 = NC,CL = 5pF

= 39!l
= 390!l,

20

30

ns

tRZLT

VCI = Bn, VC = 3.4V, RC
CD = O.BV, VL = 5V, RL 1
RL2 = 1.6K, CL = 30 pF

= 39!l,
= 390!l,

30

45

ns

tRHZT

VCI = Bn, VC = OV, RC = 39!l
CD = O.BV, VL = OV, RL 1 = 390!l,
RL2 = NC, CL = 5 pF
(Figure 2)

5

10

ns

tRZHT

VCI = Bn, VC = OV, RC = 39!l,
CD = O.BV, VL = OV, RL1 = NC
RL2 = 1.6K, CL = 30 pF

10

20

ns

tRLH
tRHL
tRLZC

tRLZT

tNR

CD to An

TIR to An

(Figure 2)

(Figure 2)

(Figure 2)
(FigureS)

Receiver Noise Rejection
Pulse Width

Note: NC means open

2-54

9

12

ns

c
en
w

Switching Waveforms

Q)
0')

N

I - -....--f--o Vo
(An,CD) ....._ - '

VI 0 - - - - 1

200.n

I

30 pF

(INCLUDES JIG CAPACITANCE)
TL/F/8539-2

Note: tr = tf

:$;

5 ns from 10% to 90%

FIGURE 1. Driver Propagation Delays

VI (T/R)

3V--------,-----------------------~
tf

1.5V
OV-----'I

Vlo----...r---,
(T/R)

1 - - -.....- -....- 0 Vo

TL/F/8539-3

Note: Ir = If

:$;

5 ns from 10% to 90%

FIGURE 2. Propagation Delay From T /R" Pin to An or Bn.

2-55

Switching Waveforms (Continued)

VI 0----1
(B n) ....._

1 - -...- -....-00 Vo
.....
1.6 k.n

I

30 pF

(INCLUDES JIG CAPACITANCE)
TL/F /8539-4

Note: tR = tF

~

10 ns from 10% to 90%

FIGURE 3. Receiver Propagation Delays

VI (CD)

1.SV

---'1

-+--

tRLZCl--.j ..

....._.....

VI 0-----1
(CD)

1 - - -.....- -....- 0 Vo

TL/F/8539-5

Note: t, = tf

~

5 ns from 10% to 90%

FIGURE 4. Propagation Delay From CD Pin to An

2-56

c

Switching Waveforms

en
CJ,)

(Continued)

Q)
Q)

N

tf

tr

3.4V

~'
'~0.9V
....
~~':"----'

5V
390.n

1.6 k

I

30 pF
(INCLUDES JIG CAPACITANCE)
TL/F/8539-6

Note: tr = If = 2 ns from 10% 1090%

FIGURE 5. Receiver Noise Immunity: No Response at Output Input Waveform.

Typical Application
5V

5V
120.n UNIFIED DATA BUS
lS0.n

lS0.n

390.n

390.n

TLIF/8539-7

2-57

co
co

en
C")

CJ)

c
......
N

en

co
C")

CJ)

C

......
o
en
CO
C")

CJ)

C

~National

PRELIMINARY

~ Semiconductor
OS3890 BTL™ Octal Trapezoidal Oriver
OS3892 BTL Octal TRI-STATE® Receiver
OS3898 BTL Octal Trapezoidal Repeater
General Description
The OS3890, OS3892 and OS3898 are advanced IEEE-896
Future Bus compatible devices designed specifically to
overcome problems associated with driving densely populated backplanes. These products provide significant improvement in both speed and data integrity in comparison to
conventional bus drivers and receivers. Their low output capacitance, low voltage swing and noise immunity features
make them ideal for driving low impedance busses with minimum power dissipation.
The OS3890 and OS3898 feature open collector outputs
that generate precise trapezoidal waveforms with typical
rise and fall times of 6 ns which are relatively independent
of capacitive loading conditions. These controlled output
characteristics significantly reduce noise coupling to adjacent lines.
To minimize bus loading, the OS3890 and OS3898 also feature a schottky diode in series with the open collector outputs that isolates the driver output capacitance in the disabled state. With this type of configuration the output low

voltage is typically "1V". The output high level is intended to
be 2 volts. This is achieved by terminating the bus with a pull
up resistor. Both devices can drive an equivalent OC load of
18.5n (or greater) in the defined configuration.
(General Oescription to be continued)

Features
•
•
•
•
•

•
•
•
•

Meets IEEE 896 Future Bus Specification
Oriver output capacitance less than 5 pF
1 volt bus signal reduces power consumption
Trapezoidal driver waveforms (tr, tf, typically 6 ns) reduces noise coupling to adjacent lines
Precise receiver threshold track the bus logic high level
to maximize noise immunity in both logic high ahd low
states
Open collector driver output allows wire-or connection
Advanced low power schottky technology
Glitch free power up/down protection
TTL compatible driver and control inputs and receiver
output

Logic and Connection Diagrams
DS3890 Octal Future Bus Drivers

DS3892 Octal Future Bus Receivers

Al

Al

A2

A2

DS3898 Octal Future Bus Repeaters

A3 3

17 84

Vee

16 GND

15

A4 4

Vee

85

A5

815

86

A6 7

816

A7

13 87

A7 8

817

A8

12 88

A8

818

A5

A6

14

11

TLIF/6700-1

NC

TL/F/6700-2

Order Numbers DS3890J, N, DS3892J, N or DS3898J, N
See NS Package Number J20A or N20A

2-58

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Offlce/
Distributors for availability and specifications.
Supply Voltage
Control Input Voltage
Driver Input and Receiver Output
Receiver Input and Driver Output
Storage Temperature Range
Lead Temperature (Soldering, 4 sec.)

Supply Voltage
Temperature (TA)

6V
5.5V
5.5V
2.5V
- 65°C to + 165°C
260°C

OS3890 Electrical Characteristics

c
en
w

Recommended Operating
Conditions

(Note 1)

Min
4.75
0

Max
5.25
70

CD
CD

o

Units
V
°C

Conditions

CD
CD
CD

(Notes 2 and 3)

Min

Typ

Max

Units
V

VIL
IILAn

Vcc=Max

VIN=O.4V

-1

IlL Dis

Vcc=Max

VIN=O.4V

-180

0.8

V

-1.6

mA

-400

/J- A

IIH

Vcc=Max

VIN=2.4V

40

II

Vcc=Max

VIN=5.25V

1

mA

VCL

Vcc=Min

IIN= -12 mA

-1.5

V

VOL

Vcc=Min

RL = 18.50

0.75

1.0

1.2

V

10H

Vcc=Max

Vour=2V

-20

10

100

/J- A

10

Vcc=OV

100

/J-A

IlL

Vcc=Max

-0.9

/J- A

DRIVER OUTPUT

Icc Low

Vour=2V
Vour=0.75V

Vcc=Max

-100

-250

/J- A

50

80

mA

TSD

mA

Max

Units

Icc High

OS3892 Electrical Characteristics

(Notes 2 and 3)

CONTROL INPUTS
Symbol

Conditions

Min

Typ

V

2.0

VIH
VIL

-180

0.8

V

-400

/J-A

IlL

Vcc=Max

VIN=O.4V

IIH

Vcc=Max

VIN=2.4V

40

/J- A

II

Vcc=Max

VIN=5.25V

1

mA

VCL

Vcc=Min

IIN= -12 mA

-0.9

-1.5

V

0.35

0.5

V

-100

mA

RECEIVER
VOL

Vcc=Min

10L =16mA

VOH

Vcc=Min

10H= -400 /J-A

2.4

3.2

los

Vcc=Max

Vour=OV

-40

-70

VrH Rec

Vcc=5V

1.5

1.55

1.6

V

IIH Rec

Vcc=Max

10

100

/J-A

II Rec

Vcc=OV

100

/J- A

IlL Rec

Vcc=Max

Icc Low

CD
CD

c
en
w

2.0

VIH

c
en
w

~
.......

DRIVER AND CONTROL INPUTS
Symbol

.......

VIN=2V
VIN=2V
VIN=0.75V

Vcc=Max

Icc High

2-59

V

TSD

/J-A

80

mA

TSD

mA

co
co
C")

0)

tJ)

c
.......
N

053898 Electrical Characteristics

0)

Symbol

tJ)

VIH

C
.......

VIL

co
C")

IlL

Vcc=Max

VIN=0.4V

tJ)

IIH

Vcc=Max

VIN=2.4V

II

Vcc=Max

VIN=5.25V

VCL

Vcc=Min

IIN= -12 rnA

co
C")
Q
0)

C

(Notes 2 and 3)

CONTROL INPUTS
Conditions

Min

Typ

Max

Units

0.8

V

-400

,..,A

V

2.0

-180

40

,..,A

1

rnA

-0.9

-1.5

V

1.55

1.6

V

10

100

,..,A

RECEIVER INPUT
1.5

VrH Rec

Vcc=5V

IIHRec

Vcc=Max

II Rec

Vcc=OV

IILRec

Vcc=Max

VIN=0.75V

VOL

Vcc=Min

RL =18.50

0.75

1.0

1.2

V

10H

Vcc=Max

Vour=2V

-20

10

100

,..,A

10

Vcc=OV

100

,..,A

IlL

Vcc=Max

-100

-250

rnA

90

135

rnA

TBD

rnA

VIN=2V
VIN=2V

100

,..,A

TBD

,..,A

DRIVER OUTPUT

Icc Low

Vour=2V
Vour=0.75V

Vcc=Max

Icc High
Note 1: "Absolute

Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The Table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: All currents into device pins are shown as positive values; all currents out of the device are shown as negative; all voltages are referenced to ground unless
otherwise specified. All values shown as max or min are classified on absolute value basis and apply to the full operating temperature and Vcc range.
Note 3: All typical values are Vcc=5V, TA= 25°C.

053890 Switching Characteristics (Figure 1)
(O·C ~ T A ~ 70·C, 4. 75V ~ Vcc ~ 5.25V unless otherwise specified)

Typ

Max

Units

9

15

ns

TdHL

9

15

ns

TdLH

10

18

ns

12

20

ns

6

10

ns

Typ

Max

Symbol
TdLH

Conditions

Min

An to Bn

Dis to Bn

TdHL
Tr&Tf

Bn rise and fall time

3

053892 Switching Characteristics (Figures 2,3 and 4)
Symbol

Conditions

Min

Units

12

18

ns

TpHL

10

18

ns

TdLZ

10

18

ns

TdZL

8

15

ns
ns

TdLH

Bn to An

DistoAn

TdHZ

4

8

TdZH

7

12

TNR

Receiver noise rejection

3

2-60

6

ns
ns

053898 Switching Characteristics
Symbol

c
en

CA)

(Figures 4 and 5)

Conditions

co

Typ

Max

20

30

ns

TdHL

20

30

ns

CO

TdLH

10

1B

ns

N
.......
C

TdLH

Min

Bito BOn

Units

co
0
.......
C
CA)

Dis to BOn

12

20

ns

Tr&Tf

Bn rise and fall time

3

6

10

ns

TNR

Receiver noise rejection

3

6

TdHL

General Descriptions

ns

(Continued)

The OSB9B2 and OS3B9B receiver inputs incorporate a low
pass filter in conjunction with high speed comparator to further enhance the noise immunity. Both devices provide
equal rejection to both positive and negative noise pulses
(typically 6 ns) on the bus.

dards Committee. This standard was adopted to enhance
the performance of Backplane Busses. BTL compatible bus
interface circuits feature low capacitance drivers to minimize bus loading. a 1V nominal signal swing for reduced
power consumption and receivers with precision thresholds
for maximum noise immunity. This new standard overcomes
some of the fundamental limitations of TTL bus transceivers
in heavily loaded backplane bus applications. Devices designed to this standard provide significant improvements in
switching speed and data integrity.

The OS3B90 features TIL compatible inputs while both the
OS3B92 and OS3B9B inputs are BTL compatible. The control inputs on all devices are TIL compatible.
BTL "Backplane Transceiver Logic" is a new logic signaling
method developed by IEEE PB96 Future Bus Stan-

AC Switching Waveforms
DISABLE

An
-tDHL
Vo(Bn)

Voh· - - - - - - - ~~----~~ 1.SSV
1.55V-i~1090%
9:J% ~. 10%
Vol
1
%
1

tR
VL

~ tr

--l f--

TL/F/8700-4

=2.0VOLTS
c

~
Vi 0 - -

en

DS3890

18.n

1----4~---.()_

I

Vo

(Bn) _ .... 30 pr
(INCLUDES JIG CAPACITANCE)

Note: tR=tF<10 ns from 10% to 90%

TLIF/8700-5

FIGURE 1
Driver Propagation Delays

2-61

CO

en

CA)

co
co
co

co
co
('t)

m

en
c.......

AC Switching Waveforms

(Continued)
5V

N

m
co
('t)

en
c.......
o
m

co
('t)

Vi(Bn)

:: -- -)----J ~1.55VtDHL
Voh • -

Vo(An)

en

~~H_

-F .

- 1.5V
Vol---......I

(Bn)
Vi

DS3892 1 - -.....-

....- - 0 Vo

1.5V

c

TLlF/B700-6

Note: tR = tF < 10 ns from 10% to 90%

TL/F/6700-7

FIGURE 2. Receiver Propagation Delays

Vi (DISABLE)
OV---I
tDHZ

tDLZ - I

1-=--

-I

tDZL

~

~

Vo(An)

r-

r

TLlF/B700-6

tOLZ

VL

RL1

RL1

390n

390n

(An)
Vi
(DISABLE)

DS3892

(An)

Vo

Vi
(DISABLE)

I"'

DS3892

~--'-~---OVo

_ _ _--II

(INCLUDES JIG CAPACITANCE)

TL/F/6700-14

Note: tR

RL2
1.6 kn

(An)

(An)

Note: tR

Vi
(DISABLE)

Vo

RL1

TLlF/6700-9

tOZH

DS3892
390 n

CL
(INCLUDES JIG CAPACITANCE)

= tF < 5 ns from 10% to 90%

tOHZ

Vi
(DISABLE)

I

~--4---'---OVo

RL1

I"'

= tF < 5 ns from 10% to 90%

DS3892

'--_...II 1.6 kn

(INCLUDES JIG CAPACITANCE)

r

CL
(iNCLUDES JIG CAPACITANCE)

TL/F/B700-16

TL/F/B700-15

FIGURE 3. Propagation Delay from Disable Pin to An

2-62

AC Switching Waveforms
VI

1.85V - 1.1V

c
en
CJ.)

(Continued)

-1~55~--,.----"\~

BUS LOGIC
LOW LEVEL

co
co
o

BUS LOGIC

~ ~~25VHIGH

--j

tNR

c
'"
en

LEVEL

f-

tNR

CJ.)

co
co
TL/F/8700-10

Low

High

'"c
'"
en

CJ.)

co
co
co

5V

390.n
(Bn)

(An)

VI O-JW"v--I
39.n

DS3892

~---'---'----~Vo

....._ _... 1.6k.n

Note: IR = IF < 2 ns from 10% 10 90%

I

30PF
(INCLUDES JIG CAPACITANCE)

TL/F/8700-11

FIGURE 4

Receiver Noise Immunity:
"No Response at Output" Input Waveforms

DISABLE

Vi(Bn)
OV----'I

Vo(Bn)
tF
TL/F/8700-12

VL

=2.0VOLTS

BI OR DISABLE OV
18.n

Vi

Note: tR

=

IF

< 10 ns from 10% to 90%

DS3898

~--1~-----oVo

I

30PF
(INCLUDES JIG CAPACITANCE)

TL/F/8700-13

FIGURE 5

Repeater Propagation Delays

2-63

<

C")

!

~National

PRELIMINARY

~ ~ Semiconductor

DS3893A BTLTM TURBOTRANSCEIVER™
General Description
The bus driver is an open collector NPN with a Schottky
diode in series to isolate the transistor output capacitance
from the bus when the driver is in the inactive state. The
active output low voltage is typically 1V. The bus is intended
to be operated with termination resistors (selected to match
the bus impedance) to 2.1 V at both ends. Each of the resistors can be as low as 20n.

The TURBOTRANSCEIVER is designed for use in very high
speed bus systems. The bus terminal characteristics of the
TURBOTRANSCEIVER are referred to as "Backplane
Transceiver Logic" (BTL). BTL is a new logic signaling standard that has been developed to enhance the performance
of backplane buses. BTL compatible transceivers feature
low output capacitance drivers to minimize bus loading, a
1V nominal signal swing for reduced power consumption
and receivers with precision thresholds for maximum noise
immunity. This new standard eliminates the settling time delays, that severely limit the TTL bus performance, to provide
significantly higher bus transfer rates.

Features
• Fast single ended transceiver (typical driver enable and
receiver propagation delays are 3.5 ns and 5 ns)
• Backplane Transceiver Logic (BTLTM) levels (1V logiC
swing)
• Less than 5 pF bus-port capacitance
• Drives densely loaded backplanes with equivalent load
impedances down to 10n
• Complies with IEEE 896 Futurebus standard
• 4 transceivers in 20 pin PCC package
• Specially designed for stripline backplanes
• Separate bus ground returns for each driver to minimize
ground noise
• High impedance, MOS and TTL compatible inputs
• TRI-STATE® control for receiver outputs
• Built-in bandgap reference provides accurate receiver
threshold
• Glitch free power up/down protection on all outputs
• Oxide isolated bipolar technology

The TURBOTRANSCEIVER is compatible with the requirements of the proposed IEEE 896 Futurebus draft standard.
It is similar to the DS3896/97 BTL TRAPEZOIDAL Transceivers but the trapezoidal feature has been removed to
improve the propagation delay. A stripline backplane is
therefore required to reduce the crosstalk induced by the
faster rise and fall times. This device can drive a 10n load
with a typical propagation delay of 3.5 ns for the driver and
5 ns for the receiver.
When multiple devices are used to drive a parallel bus, the
driver enables can be tied together and used as a common
control line to get on and off the bus. The driver enable
delay is designed to be the same as the driver propagation
delay in order to provide maximum speed in this configuration. The low input current on the enable pin eases the drive
required for the common control line.

Connection and Logic Diagram
01

VCC

BUS
GNO

lOGIC
GNO

04

R4

DE

BUS
GNO

Order Number DS3893AV
See NS Package Number V20A

2-64

TLlF/8698-1

Absolute Maximum Ratings

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

6.5V

Control Input Voltage
Driver Input and Receiver Output

5.5V
5.5V

Driver Output Receiver Input Clamp Current

±15mA

Power Dissipation at 70°C

900mW

Storage Temperature Range

I

Parameter

I

+ 150°C
260°C

Recommended Operating
Conditions
Supply Voltage, Vee
Bus Termination Voltage (VT)
Operating Free Air Temperature

Electrical Characteristics (Notes 2,3 and 4) TA =
Symbol

- 65°C to

Lead Temperature (Soldering, 4 sec.)

0 to

+ 70°C, Vee

Min
4.5
2.0
0

Max
5.5
2.2
70

Units
V
V
°C

= 5V ± 10%

Conditions

I

Min

I

Typ

I

Max

I

Units

DRIVER AND CONTROL INPUT: (DE, RE, Dn)
VIH

Input High Voltage

Vil

Input Low Voltage

2.0

V
O.S

V

II

Input Leakage Current

DE = RE = On = Vec

100

,."A

IIH

Input High Current

DE = RE = On = 2.5V

20

,."A

III

On Input Low Current

On = 0.5V, DE = Vee = Max

-200

,."A

DE Input Low Current

DE = 0.5V, On = Vec = Max

-700

,."A

RE Input Low Current

RE = 0.5V, Vcc = Max

-100

,."A

Input Diode Clamp Voltage

Icl amp = -12 mA

-1.2

V

VCl

DRIVER OUTPUT/RECEIVER INPUT: (8n)
VOLS

Output Low Bus Voltage

On = DE = VIH (Figure 2)
RT = 100, VT = 2.2V

0.75

1.0

1.2

V

On = DE = VIH (Figure 2)
RT = 1S.50, VT = 2.14

0.75

1.0

1.1

V

-250

100

,."A

100

,."A

IllS

Output Bus Current (Power On)

On = DE = O.SV, Vee = Max
Bn = 0.75V

IIHS

Output Bus Current (Power Off)

On = DE = O.SV, Vec = OV
Bn = 1.2V

VOCS

Driver Output Positive Clamp

Vce = Max or OV, Bn = 1 mA

1.9

2.9

V

Vee = Max orOV, Bn = 10 mA

2.3

3.2

V

Vcc = Max, On = O.SV (Figure 2)
VT = 2.0V, RT = 100

1.90

VOHS

Output High Bus Voltage

VTH

Receiver Input Threshold

1.475

V
1.55

1.625

V

0.35

0.5

V

RECEIVER OUTPUT: (Rn)
V

2.5V

VOH

Voltage Output High

Bn = 1.2V, loh = -3 mA, RE = O.SV

VOL

Voltage Output Low

Bn = 2V, 101 = 6 mA, RE = O.SV

102

TRI-STATE Leakage

Va = 2.5V, RE = 2V

20

,."A

Va = 0.5V, RE = 2V

-20

,."A

lOS

Output Short Circuit Current
(Note 5)

-200

rnA

Bn = 1.2V, Va = OV
RE = O.SV, Vcc = Max

-SO

-120

95
mA
70
Supply Current
On = DE = RE = VIH, Vec = Max
ICC
Note 1: "Absolute maximum ratings" are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be
operated at these limits. The table of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise
specified.
Note 3: All typicals are given for Vee = 5V and TA = 25'C.
Note 4: Unused inputs should not be left floating. Tie unused inputs to either Vee or GND thru a resistor.
Note 5: Only one output at a time should be shorted.

2-65

•

<

C")

en

Switching Characteristics TA =

en
c

Symbol

co
C")

Oto +70·C, Vee

Parameter

= 5V ±10%
Min

Conditions

Typ

Max

Units

DRIVER: (Figures 3 and 6)

tpHL

Driver Input to Output

VT

= 2V RT = 10n, CL = 30 pF, DE = 3V

1

3.5

7

ns

tpLH

Driver Input to Output

VT

= 2V, RT = 10n, CL = 30 pF, DE = 3V

1

3.5

7

ns

tr

Output Rise time

VT

= 2V, RT = 10n, CL = 30 pF, DE = 3V

1

2

5

ns

tl

Output Fall Time

VT

= 2V, RT = 1on, CL = 30 pF, DE = 3V

1

2

5

ns

tskew

Skew Between Drivers
in Same Package

(Note 1)

ns

1

DRIVER ENABLE: (Figures 3 and 6)

= 2V, RT = 10n, CL = 30 pF, On = 3V

1

3.5

7

ns

= 10n, CL = 30 pF, On = 3V

1

3.5

7

ns

tpHL

Enable Delay

VT

tpLH

Disable Delay

VT = 2V, RT

RECEIVER: (Figures 4 and 7)

tpHL

Receiver Input to Output

CL

= 50 pF, RE = DE = 0.3V, S3 Closed

2

5

8

ns

tpLH

Receiver Input to Output

CL

= 50 pF, RE = DE = 0.3V, S3 Open

2

5

8

ns

tskew

Skew Between Receivers
in Same Package

(Note 1)

ns

1

RECEIVER ENABLE: (Figures 5 and 8)

tZL

Receiver Enable to
Output Low

CL = 50 pF, RL = 500, DE
S2 Open Bn = 2V

= 0.3V

tZH

Receiver Enable to
Output High

CL = 50 pF, RL = 500, DE
S10pen Bn = 1V

= 0.3V

tLZ

Receiver Disable
From Output Low

CL = 50 pF, RL = 500, DE
S2 Open Bn = 2V

= 0.3V

2

6

12

ns

2

5

12

ns

1

5

8

ns

Receiver Disable
CL = 50 pF, RL = 500, DE = 0.3V
1
4
8
ns
From Output High
S10pen Bn = 1V
Note 1: tD and tR skew is an absolute value, defined as differences seen in propagation delays between each of the drivers or receivers in the same package of the
same delay, Vee, temperature and load conditions.

tHZ

C VT

~~~
-~r

On
DE

--

-==
-

TL/F/869B-12

VIL, VIH-!-

I
I

~

1

~,

-:...

,
J
1

=

:: RT 10.0.

DS3893A
~

.-

Bn

.I..
-

-

FIGURE 1. Equivalent Bus Output

Note:n = 1,2,3,4
TL/F/8698-2

FIGURE 2. Driver Output Voltage

2-66

.... VOlB'VOHB

c

(J)
CAl

AC Test Circuits

ClO

co
CAl
:£>
VDn(t)

o-.....;;;Dn~-+--I

VDE(t)

o--..;;.D~EI--'

RT

DS3893A

=10D.

JO~.--t-B_n~.....-o VBn(t)
CL = 30PF

I

(INCLUDES JIG CAPACITANCE)
TL/F/8698-3

FIGURE 3

DS3893A

VBn(t) O-~+-+---I .x>-_--t_Rn_....._ _ _......_o VRn(t)
RL

=

CL 50PF'
(INCLUDES JIG CAPACITANCE)

I

=1k

TL/F/8698-4

FIGURE 4

DS3893A

VRn(t) RL =500

lV-2V

S2
CL 50 PF
(INCLUDES JIG CAPACITANCE)

-::L

=

I

-=

Note: Unless Otherwise Specified
The Switches are Closed

TL/F/8698-5

FIGURES

Switching Time Waveforms

•

VDn(t) 3V - - - - - - -

ItPH~

VDE(t)
OR .3V - - - - -.......
1.3V ~

VBn(t)

V~:

---------9-.:'" ~.l~-~-.____-\ "'____

;..,;,0,;,.,.

TL/F/8698-6

FIGURE 6. Driver Propagation Delay

2V------_

V,,(t)
VRn(t)

v::

1.55V

i

t
Pl

"-1 _____

--1

-j1.3V

>-----1 1.55V
,

l

VOL----------~

~tpHL:l

1.3V'\'-----TL/F/8698-7

FIGURE 7. Receiver Propagation Delay

2-67

c(
C")

~

Switching Time Waveforms (Continued)

C")

en

o

1 sv
- 3v------------~f

VRE(t}

VR,(t) .::

. :

VOL

'Y

't.z

IZ\J... 1.5V
-------------\

tZH~
Ii(sv

__

VRn(t)
Note: IR = IF

~

/1.
ov-----------------J

--==___

tHZ~

VOH - - - - - - - 1 - - --+1 ,._ _ _ _~~ \-i_ _ _ _ _ _

t VOL
----1..., V
OH

---~t

.sv

~-----Note: n = 1, 2, 3, 4

4 ns From 10% to 90%

TLlF/8698-B

FIGURE 8. Receiver Enable and Disable Times

Typical Application
20 OHM LOADED BACKPLANE

I

•

DS3893A

DS3893A

DS3893A
I

I

_______ 4

I
I
I
I,

DS3893A
I
I

I
I

I
I
I

_______ 4

TL/F/8698-9

Application Information
Due to the high current and very high speed capability of the
TURBOTRANSCEIVER's driver output stage, circuit board
layout and bus grounding are critical factors that affect the
system performance.

B.G. REFERENCE GROUND

Each of the TURBOTRANSCEIVER's bus ground pins
should be connected to the nearest backplane ground pin
with the shortest possible path. The ground pins on the connector should be distributed evenly through its length.
Although the bandgap reference receiver threshold provides sufficient DC noise margin (Figure 9), ground noise
and ringing on the data paths could easily exceed this margin if the series inductance of the traces and connectors are
not kept to a minimum. The bandgap ground pin should be
returned to the connector through a separate trace that
does not carry transient switching currents. The transceivers should be mounted as close as possible to the connector. It should be noted that even one inch of trace can add a
significant amount of ringing to the bus signal.

1

1.62SV -..l------"\r1.47SV-...---~~

B
z
z

1.2V-..l---------

8

TL/F/8698-10

FIGURE 9. Noise Margin
TL/F/8698-11

FIGURE 10

2-68

c

U)

w
Q)

~National

CD

~ Semiconductor
OS3896/0S3897 Futurebus Trapezoidal™ Transceivers

0")

.......
C
U)
w
Q)

CD

......

General Description
These advanced IEEE-896 Futurebus compatible transceivers are specifically designed to overcome problems associated with driving a densely populated backplane, and thus
provide significant improvement in both speed and data integrity. Their low output capacitance, low output signal
swing and noise immunity features make them ideal for driving low impedance buses with minimum power consumption.
The 083896 is an octal high speed schottky bus transceiver
with common control signals, whereas the 083897 is a
quad device with independent driver input and receiver output pins. The 083897 has a separate driver disable for each
driver and is, therefore, suitable for arbitration lines. On the
other hand, the 083896 provides high package density for
datal address lines.
The open collector drivers generate precise trapezoidal
waveforms, which are relatively independent of capacitive
loading conditions on the outputs. This significantly reduces
noise coupling to adjacent lines. In addition, the receivers
use a low pass filter in conjunction with a high speed comparator, to further enhance the noise immunity and provide
equal rejection to both negative and positive going noise
pulses on the bus.
To minimize bus loading, these devices also feature a
schottky diode in series with the open collector output that
isolates the driver output capacitance in the disabled state.
The output low voltage is typically "W" and the output high
level is intended to be 2V. This is achieved by terminating
the bus with a pull up resistor to 2V at both ends. The device

can drive an equivalent DC load of 18.50. (or greater) in the
above configuration.
These signalling requirements, including a 1 volt signal
swing, low output capacitance and precise receiver thresholds are referred to as Bus Transceiver Logic (BTLTM).

Features
• 8 bit 083896 transceiver provides high package density
• 4 bit 083897 transceiver provides separate driver input
and receiver output pins
• Meets IEEE 896 Futurebus specification
• BTL compatible
• Less than 5 pF output capacitance for minimal bus
loading
• 1 Volt bus signal swing reduces power consumption
• Trapezoidal driver waveforms (tr, tf ~ 6 ns typical) reduce noise coupling to adjacent lines
• Temperature insensitive receiver thresholds track the
bus logic high level to maximize noise immunity in both
high and low states
• Guaranteed A.C. specifications on noise immunity and
propagation delay over the specified temperature and
supply voltage range
• Open collector driver output allows wire-or connection
• Advanced low power schottky technology
• Glitch free power up/down protection on driver and receiver outputs
• TTL compatible driver and control inputs and receiver
outputs

Logic and Connection Diagrams
DS3896N, J
Al
A2
A3
A4
Vee
A5

D83897V

D83897N,J
El

01
19 82
18
17

83
84

02

A7

°2

B2

R2

E2

Vee

GNO

°3

Vee

B3

R3

E3

°4

85

14 86
13

R3
B4

87
04

A8

Rl

R2

03
A6

°1

Rl

16 GNO
15

Bl

E4

RE IT

R4

TL/F/8S10-11
Order Number DS3896J, N,
DS3897J, N or D83897V
See NS Package Number
J20A, N20A or V20A

12 88
R4
11 (T/R)
TRANSMIT /
RECEIVE

TL/F/8S10-2

TL/F/8S10-1

2-69

•

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
SV
Control Input Voltage
Driver Input and Receiver Output
Receiver Input and Driver Output
Power Dissipation at 70°C N Package

5.5V
5.5V
2.5V
1480 mW

J Package
Storage Temperature Range
Lead Temperature (Soldering, 4 sec.)

1250 mW
-S5°C to + 150°C
2S0·C

Electrical Characteristics:
Symbol

Recommended Operating
Conditions
Supply Voltage, Vee
Bus Termination Voltage
Operating Free Air Temperature

(Note 2 and 3) (O·C

Parameter

~

TA

~

70°C, 4.75V

~

Vee

Conditions

~

Min
4.75
1.90
0

Max
5.25
2.10
70

Units
V
V
°C

5.25V unless otherwise specified)
Min

Typ

Max

Units

Driver and Control Inputs: (An, On, En, CD, T /R, RE, TE)
VIH

Logical "1" Input Voltage

Vil

Logical "0" Input Voltage

II

Logical "1" Input Current

An = On = En = Vee

IIH

Logical "1" Input Current

An = On = En = 2.4V

III

Logical "0" Input Current

An = On = En = O.4V

Ille

Logical "0" Input Current

Vel

Input Diode Clamp Voltage

V

2.0
0.8

V

1

mA

40

p,A

-1

-1.S

mA

CD = T /R" = RE = TE = O.4V

-180

-400

p,A

Iclamp = -12 mA

-0.9

-1.5

V

1.0

1.2

V

10

100

p,A

100

p,A

1.S0

V

Driver Output/Receiver Input: (Bn)
VOlB

Low Level Bus Voltage

An = On = En =TfR = 2V, VL = 2V
RL = 18.50, CD = TE = 0.8V (Figure 1)

0.75

IIHB

Maximum Bus Current (Power On)

An = On = En = 0.8V, Vee = 5.25V
Bn = 2V

IllB

Maximum Bus Current (Power Off)

An = On = En = O.SV, Vee = OV
Bn = 2V

VTH

Receiver Input Threshold

Vee = 5V

1.5

1.55

2.4

3.2

Receiver Output: (An, Rn)
VOH

Logical "1" Output Voltage

Bn = 1.2V,IOH = -400 p,A
CD = T fR = RE = 0.8V

Val

Logical "0" Output Voltage

Bn = 2V,IOl = 1SmA
CD = T fR = RE = O.SV

los

Output Short Circuit Current

Bn = 1.2V
CD = T fR = RE = 0.8V

Icc

Supply Current (DS389S)

Ice

Supply Current (DS3897)

V

0.35

0.5

V

-70

-100

mA

Vec = 5.25V

90

135

mA

Vcc = 5.25V

50

80

mA

-40

Note 1. "Absolute maximum ratings" are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be
operated at these limits. The table of "Electrical Characteristic" provide conditions for actual device operation.
Note 2. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise
specified.
Note 3. All typicals are given for

Vce =

5V and Ta

= 25°C.

2-70

053896 Switching Characteristics
(O·C

s:

TA

s:

70·C, 4.75V

I

Symbol

s:

Vee

s:

5.25V unless otherwise specified)

I

Parameter

I

Conditions

I

Min

Typ

I

Max

I

Units

Driver:
An to Bn

tOLH

=

0.8V, T IR

=

=

5

9

15

ns

5

9

15

ns

5

10

18

ns

(Figure 2)

5

12

20

ns

(FigureS)
VCI = An, VC = 5V,
CD = 0.8V, RC = 3900, CL = 30 pF
RU = 180, RL2 = NC, VL = 2V

5

15

25

ns

5

22

35

ns

CD

2.0V, VL

2V

(Figure 2)

tOHL
CD to Bn

tOLHC

An

= T/R =

2.0V, VL

=

2V

tOHLC
T/RtoBn

tOLHT
tOHLT
tR

Driver Output Rise Time

tF

Driver Output Fall Time

CD

=

0.8V, T/R

=

2V, VL

=

2V

3

6

10

ns

(Figure 2)

3

6

10

ns

5

12

18

ns

(Figure 3)

5

10

18

ns

5

10

18

ns

Receiver:
Bn toAn

tRLH

CD

=

0.8V, T IR

=

0.8V

tRHL
Bn = 2.0V, T IR = 0.8V, CL = 5 pF
RL 1 = 3900, RL2 = NC, VL = 5V

CDtoAn

tRLZC

(Figure 4)

tRZLC

Bn = 2.0V, T IR = 0.8V, CL = 30 pF
RL 1 = 3900, RL2 = 1.6k, VL = 5V (Figure 4)

5

8

15

ns

tRHZC

Bn = 0.8V, T/R = 0.8V, VL = OV,
RL 1 = 3900, RL2 = NC, CL = 5 pF (Figure 4)

2

4

8

ns

tRZHC

Bn = 0.8V, T IR
RL 1 = NC, RL2

3

7

12

ns

8

14

20

ns

14

24

40

ns

2

4

8

ns

2

8

15

ns

3

6

0.8V, VL
1.6k, CL

=
=

OV,
30 pF (Figure 4)

VCI = Bn, VC = 2V, RC = 180,
CD = 0.8V, VL = 5V, RL 1 = 3900,
RL2 = NC, CL = 5 pF

T/R to An

tRLZT

=
=

tRZLT

VCI = Bn, VC = 2V, RC = 180,
CD = 0.8V, VL = 5V, RL 1 = 3900,
RL2 = 1.6k, CL = 30 pF

tRHZT

VCI = Bn, VC = OV, RC = 180,
CD = 0.8V, VL = OV, RL 1 = 3900,
RL2 = NC, CL = 5 pF

tRZHT

VCI = Bn, VC = OV, RC = 180,
CD = 0.8V, VL = OV, RL1 = NC
RL2 = 1.6k, CL = 30 pF

(FigureS)

(FigureS)

(FigureS)
(Figure 6)

Receiver Noise
Rejection Pulse Width

tNR

(FigureS)

ns

Note: NC means open

053897 Switching Characteristics
(O·C

s:

Symbol

TA

I

s:

70·C, 4.75V

s:

Vee

s:

Parameter

5.25V unless otherwise specified)

I

I

Conditions

Min

I

Typ

I

Max

I

Units

Driver:
tOLH

On, En to Bn

TE

=

=

tOLHT

TE to Bn

An

=

5

9

15

ns

(Figure 2)

5

9

15

ns

(Figure 2)

5

10

18

ns

5

12

20

ns

= 180, RL2 = NC, VL = 2V (Figure S)
= 0.8V, T/R = 2V, VL = 2V

3

6

10

ns

(Figure 2)

3

6

10

ns

0.8V, RE

2.0V, VL

tOHL

=

RE

=

2.0V, VL

=

2V,

2V

tOHLT
RL 1
tR

Driver Output Rise Time

tF

Driver Output Fall Time

CD

2-71

r--

0)

CIO

('t)

en
c
.......
CD

0)

CIO

('t)

en
c

OS3897 Switching Characteristics

(Continued)

(O°C ~ T A ~ 70°C, 4.7SV ~ Vee ~ S.2SV unless otherwise specified)
Symbol

I

I

Parameter

I

Conditions

Min

I

Typ

I

Max

I

Units

Receiver:
tRLH

Bn to Rn

TE

= 2.0V, RE = 0.8V

(Figure 3)

tRHL
tRLZR

RE to Rn

tRzLR

Bn = TE = 2V, VL = 5V, CL
RL 1 = 390n, RL2 = NC

= 5 pF

Bn = TE = 2V, VL = 5V, CL
RL 1 = 390n, RL2 = 1.6k

= 30 pF

5

10

18

5

12

18

ns
ns

5

10

18

ns

5

8

15

ns

(Figure 4)
(Figure 4)

tRHZR

Bn = 0.8V, TE = 2V, VL = OV,
RL 1 = 390n, RL2 = NC, CL = 5 pF(Figure 4)

2

4

8

ns

tRZHR

Bn = 0.8V, TE = 2V, VL = OV,
RL1 = NC, RL2 = 1.6k, CL = 30 pF(Figure 4)

3

7

12

ns

(Figure 6)

3

6

(Figure 7)

10

20

30

ns

10

20

30

ns

tNR

Receiver Noise
Rejection Pulse Width

ns

Driver plus Receiver:
tORLH

Dn to Rn

TE

= RE = 0.8V

tORHL
Note: NC means open

OVL
.~

.=•

053896

RL
.... Volb

OR
(8n)

053897

TL/F/8510-3

FIGURE 1. Driver Output Low Voltage Test

{

~

1

tf~}1.5V

(CO) 3V - •. ·"5V ,,t
OV

r

t OLHC -

Vi

t ~f
1.5 V\.

3V
(An, On, En)
OV - -

tO~H-~

Voh - - - - - - - 1.55 V....,
Vo (8n) Vol

-

90%

10~

tR

, -tOHLC

tr"
1.5 V

-

90%

-tOHL
~

1.55 V

~ 10%

-1-tF

() V
L
:: 18,n
.~

Vi ::;
(An, On, En, CD)

OS3896
OR
OS3897

f

(8n)

-. Vo
30 pF (INCLUDES JIG CAPACITANCE)

-Note: tr

= tf :;; 5 ns from 10% to 90%
FIGURE 2. Driver Propagation Delays
2-72

TL/F/8510-4

c

en
w
0)
CD

0')
......

c

en
tF

tR "-

~~ __ iR~L.5H-5_~~~_

V1(Bn)

w
0)

1.55 V

~'

CD

l~----

......

":11- tRHL

Vo (An, Rn)oh - - - - -1 ~5 ~: - - - - - - - - \ 1.5 V
Vol·

"'----

OS3896
VI

OR

(8n)

.....- -. .-

OS3897

....- - 0 Vo

I

30 pF (INCLUDES JIG CAPACITANCE)

TLiF/8510-5

Note: tR = IF :5: 10 ns from 10% 10 90%

FIGURE 3. Receiver Propagation Delays

VI (CO)

3V - - - - - - - - - - - .,....------"""'.
1.5V

OV

't

r

1.5 V
tRLZC-

1-_

~tRZLC

....,X;;

1.5 V

Vo (An) _ _ _ _ _ _

f

OS3896
Vlo---t

(co)

OR

053897

1----4,....--411---0 Vo

(An)
RL2

I

CL (INCLUDES JIG CAPACITANCE)

TL/F/8510-6

Note: Ir

= If

:5: 5 ns from 10% 1090%

FIGURE 4. Propagation Delay from CD pin to An

2-73

.....
0)
co
C")

en
c
.......
CD

0)

_

co
C")

Vi (T/ R)

en

c

3v------------~------------~.

1.5 V
OV -----------',

'tr

Vo (Bn)

Vo (An)

1.5V

O.5V

f
t RHZT -

JtRZHT

!-

~

Vo(An)

Vi

0-----"'"
(T/R)

Vc

C>--¥Inr----I

1.5 V

OS3896 ~----~----. .--oVo
OR

OS3897
RC (An. Bn) ...._ _..

RL2

I

'1. (iNCLUDES JIG CAPACITANCE)
TLIF/8510-7

Note: Ir

=

If :::: 5 ns from 10% 10 90%

FIGURE 5. Propagation Delay from T /R" pin to An or Bn

1.85V - - - - ..----,.
1.55 V
1.1V
BUS LOGIC
_
LOW LEVEL
Vi

tr

~
tf

2V BUS LOGIC
1.55 V
HIGH LEVEL
- - - - 1.25V

tNR

OS3896
Vi D--uV\l-----I

39.0.

(Bn)

OR

~----~------~--~Vo

I

OS3897

3D pF (iNCLUDES JIG CAPACITANCE)

TL/F/8510-8

Note: Ir = If = 2 ns from 10% 10 90%

FIGURE 6. Receiver Noise Immunity: "No Response at Output" Input Waveforms

2-74

c

en
w

VI(On}:~- -

~.5-Vi'tr
'ORLH --:j
I~

0)

tf\1_.5_V_~_ _ __
-I' ~ 'ORHL

- - -

CD

<»

.......

c
en
w

1.5V-l----------\"',_1.5_V_____

Vo{Rn}

0)

CD

.......

2V
18.0.
~------~---_e---_oVo

30 PF

I
TLIF/6510-9

Note: I, =

If

s: 5 JLs from 10% 1090%
FIGURE 7. Driver Plus Receiver Delays

Typical Application

!t::~:;:---~ ~----[----~
I

OS3896/ OS3897: : OS3896 /OS3897 :
I
I
I

I
I
I

I

I

I
I

I
I
I
I
I
I
I
I
I

I
I
I
I
I
I

I
I
I

I

OS3896 / OS3897 :

I
I
I

I
I
I
I

I
I
I
I

I

I

._-------_.

I

I

.---------'"

I

TL/F/6510-10

2-75

co

.

r---------------------------------------------------------------------------------~

II)
~

z


5) 
TOTAL (ns)

TTL
AS
6.5
9.0
6.5
-4.0
-2.0

BTL
Trap
6.5
9.0
15.0
-4.0
-5.0

BTL
Turbo
6.5
9.0
7.0
-4.0
-2.0

16.0

21.5

16.5

AS

Trap.

21.5 ns

Turbo

TLIF/9633-6

DELAY 2
1) Max XOR Delay
2) Max '374 Hold Time
3) Delay 3
4) < Min '373 Delay>
5) < Min Ack Driver Delay>
5) < Min Data Receiver Delay>
TOTAL (ns)

TTL
AS
6.5
3.0
5.5
-3.5
-2.0
-2.0

BTL
Trap
6.5
3.0
14.0
-3.5
-5.0
-5.0

BTL
Turbo
6.5
3.0
7.0
-3.5
-2.0
-2.0

7.5

10.0

9.0

AS

Trap.

10.0ns

Turbo
TL/F/9633-7

DELAY 3
1) Max Data Receiver Delay
2) Max '374 Setup Time
4) 
5) 
TOTAL (ns)

TTL
AS
6.5
2.0
-2.0
-1.0

BTL
Trap
18.0
2.0
-5.0
-1.0

BTL
Turbo
8.0
2.0
-2.0
-1.0

5.5

14.0

7.0

AS

Trap.

Turbo
TLIF/9633-8

FIGURE 6. Asynchronous Bus Logic Delay Calculations

2-84

BTL - Trap.
BTL- Turbo

I2 I

I4 I

3

5

16

TTL
AS

9

6.5
7.5
16.0
6.5
35.0
6.5
6.0
7.5
6.5
35.0

18.0
7.5
21.5
15.0
10.0
18.0
6.0
10.0
15.0
9.0

8.0
7.5
16.5
7.0
10.0
8.0
6.0
9.0
7.0
9.0

133.0

130.0

88.0

7.5

7.7

11.4

MTransfersl second

1133 ns

I 10 1130 ns

FIGURE 7. Asynchronous Burst Data Transfer Timing
(Worst Case)
The largest cycle time delay in the final BTL Turbo example
is clock skew. Bus skews can be reduced by distributing the
clock to each board independently, using a dedicated trace
on the backplane such that all lines are of equal length. This
makes the clock propagation delay from the driver to each
board the same, and thus practically eliminates ·the bus
skew. In addition, better tolerances on driver, receiver, and
logic propagation delays (smaller skews) will improve both
the clock skew and the effect of transceiver delays on the
cycle time.

The result of this lack of timing constraints is that a board
built today, using today's technology, is guaranteed to work
in a system designed perhaps twenty years from now. That
system will be forced to slow down whenever necessary to
accommodate the greater internal delays and skews of the
older module. However, if two future modules are communicating, they will transfer data at the maximum rate allowed
by the future technology. The new IEEE Futurebus standard
implements this type of protocol.

ASYNCHRONOUS BUS TIMING

The requirement that boards generate their own data synchronization and acknowledge signals, and the likelihood of
zero set-up and hold times on the bus, make the timing of
the asynchronous system more complicated than the previous example (Figure 5). Also, we are maximizing the performance of the sync/ack handshake by transferring data
on each signal transition. This is known as a two-edge handshake.

ASYNCHRONOUS DATA TRANSFER TIMING

Our second example is also of a burst transfer, but this time
using asynchronous bus timing. In this system, the master
issues a strobe along with the data, and waits for an acknowledgement from the slave before removing the current
data from the bus lines. All timing is controlled by the two
participants in the data transfer. (Once again, we are assuming that new status does not have to be generated on
each data transfer.)

On the master side, the board must guarantee that its data
is valid on the bus before issuing the synchronization signal.
This means that a delay must be inserted in the sync signal
path (Delay 1) which includes the maximum propagation delays through the XOR clock generation circuit, edge-triggered flip-flop, and data bus driver. This is excessive, however, because the minimum delays through the sync latch
and bus driver can be subtracted (Figure 6).

The greatest advantage of an asynchronous bus protocol is
its ability to adapt the speed of the bus to the speed of any
two communicating boards. The most flexibility is achieved
when no technology dependencies are introduced into the
protocol. Unlike a synchronous system, where every board
is designed with the same timing constraints in mind, a technology-independent module is designed with no assumptions about the timing of the rest of the system. Instead,
each transmitting board simply guarantees that its data is
valid on the bus at least zero nanoseconds before it issues
its synchronization signal, and each receiving board is responsible for ensuring that its data has been successfully
latched before issuing an acknowledge. The protocol itself
imposes no artificial set-up or hold time limitations.

On the slave side, delays are required to guarantee that
both the set-up and hold time specifications of the data
latch are met. The set-up time delay (Delay 3) ensures that
the sync signal, which may have minimum propagation delays through the sync bus receiver and XOR clock generator, arrives at the edge-triggered data flip-flop a set-up time
after the data, which may have a maximum delay through

2-85

U1

...Ao

BTL
Turbo

4) Max Sync Driver Delay
5) Max Bus Delay + Skew
6) Max Sync Receiver Delay
7) Max '373 Delay
8) Delay 2
9) Max Ack Driver Delay
10) Max Bus Delay
TOTAL (ns)

10

BTL
Trap

1) Max Ack Receiver Delay
2) Max '533 Delay
3) Delay 1

.

>

Z

I7 I 8 I9 1
1
I2 I 3 I 4 I 5 I 6 I7 I 8 I
3
1 I 21
I 4 I 5 I 6 I 7 I 8 I 9 I 10 188 ns

TTL-AS 1

~

BTL - Trap.1--1--L_'--_ _ _ _ _..I.--1-..l.-_'--..l.-_ _..l.-....J

1) Min Ack Receiver Delay
2) Min '533 Delay
3) Delay 1
4) Min Sync Driver Delay
5) Min Bus Delay + Skew
6) Min Sync Receiver Delay
7) Min '373 Delay
8) Delay 2
9) Min Ack Driver Delay
10) Min Bus Delay

TTL
AS
2.0
4.0
16.0
2.0
35.0
2.0
3.5
7.5
2.0
35.0

BTL
Trap
5.0
4.0
21.5
5.0
1.0
5.0
3.5
10.0
5.0
0.0

BTL
Turbo
2.0
4.0
16.5
2.0
1.0
2.0
3.5
9.0
2.0
0.0

TOTAL (ns)

109.0

60.0

42.0

9.2

16.7

23.8

MTransfers/ second

FIGURE 8. Asynchronous Burst Data Transfer Timing
(Best Case)
the data bus receiver. The hold time delay (Delay 2) ensures
that the data remains at the data flip-flop a hold time after
the sync signal, which this time may have a maximum propagation delay through the XOR and the set-up time delay
element just introduced. Since the removal of data is controlled by the ack signal, the hold time delay can be reduced
by the minimum delays through the ack latch and bus driver,
and the minimum propagation delay of the data bus receiver.

ASYNCHRONOUS TIMING CALCULATIONS
Once again, the TTL design is overwhelmed by the settling
time of the bus. Since the sync/ack signal pair are acting as
clocks in this system, glitches that may occur during the
signal settling time are intolerable. This means that the
35 ns bus settling time must be hard-wired into the receiver
logic, and cannot be reduced under best-case conditions.
The performance of an asynchronous TTL backplane, from
7.5 to 9.2 MT, cannot approach that of a similar synchronous backplane.

This is all very confusing at first, but these delay elements
now in place in our circuit guarantee the receiver set-up and
hold time requirements while maintaining the technology independence of the bus protocol. Now we can calculate the
burst data transfer rate on this asynchronous bus.

The BTL Trapezoidal system has very similar performance
to a TTL backplane under worst-case conditions. However,
because there is no settling time penalty associated with
BTL signals, the effect of improvements in device operation
have a far more pronounced effect. In the best case, the
performance is close to that of the equivalent synchronous
system. Also, since the bus signal propagation delay is a
function only of the distance between the two boards, modules placed in adjacent slots will experience almost no
backplane delays.

The critical path is now the sync/ ack handshake. The circuit
delays are in place to make sure that data is transferred
successfully. To calculate the transfer rate, simply add up all
the propagation delays through the sync/ ack loop (Figures
7 and 8): on the master, the ack receiver, the sync latch,
Delay 1, and the sync driver; a bus propagation delay; on
the slave, the sync receiver, the ack latch, Delay 2, and the
ack driver; and another bus propagation delay.

A BTL Turbo board benefits from the same clean electrical
environment that a Trapezoidal one does, except with a 4050% overall improvement in performance. In the best case,
the performance is the same as that of the equivalent synchronous system. Of course, as device parameters improve,
with lower propagation delays and skews, the performance
of the asynchronous system will continue to improve. The
largest reductions in the transfer cycle time will come as
interfaces for asynchronous busses such as Futurebus are
integrated onto a single piece of silicon, where skews and
delays can be more tightly controlled.

Should you use worst-case values throughout your evaluation? The beauty of a technology-independent asynchronous protocol is that is will adapt to the speed of the individuallogic elements in the sync/ack handshake path. If all the
devices happen to have worst-case characteristics, then
yes. If they are all fast parts, however, then data transfer will
take place under best-case conditions. Both calculations
are included, providing the expected operating range of the
circuit.

2-86

»
z

CONCLUSION

REFERENCES

The use of transceivers designed specifically for the transmission-line environment typical in today's high-speed backplanes provides advantages in both the performance and
electrical integrity of a system. The advantages of BTL only
become obvious after a careful analysis of data transfer timing considerations. The Trapezoidal and Turbo options provide a designer with the opportunity to make the appropriate
application-dependent cost/performance tradeoffs. A
sometimes controversial issue is the appropriateness of a
synchronous versus an asynchronous design. The former
will usually provide an immediate performance advantage in
a fully synchronized environment, but a carefully-designed
general-purpose asynchronous protocol will often have a
longer useful product life.

1. R.V. Balakrishnan, "The Proposed IEEE 896 Futurebus-A Solution to the Bus Driving Problem," IEEE Micro, August 1984.
2. R.V. Balakrishnan, "Physical Layer Timing Design Considerations for High Speed Backplane Busses," Buscon/
87 West, January 1987.
3. D.B. Gustavson and J. Theus, "Wire-OR Logic on Transmission Lines," IEEE Micro, June 1983, pp. 51-55.
4. Interface Oatabook, National Semiconductor Corp., Santa Clara, CA, 1986.
5. ALS/AS Logic Oatabook, National Semiconductor Corp.,
Santa Clara, CA, 1987.
6. IEEE P896 07.5a, "Futurebus: A Bus Standard for Multiprocessing Architectures", IEEE, June 1987.

TABLE I. Device Parameters
Parameter
(Transition)

Minimum
Prop. Delay

Maximum
Prop. Delay

DM74AS374
Edge-Triggered Flip-Flop

LH
HL

3.0
4.0

8.0

5.0

9.0

5.0

DM74AS373
Transparent Latch

LH
HL

3.5
3.5

6.0
6.0

2.5
2.5

DM74AS533
Inverting Transparent Latch

LH
HL

4.0

7.5

3.5

4.0

7.0

3.0
4.5
5.0

Device

Maximum
Skew

Other Input L
Other Input H

2.0

6.5

1.0

6.0

DM74AS240
Bus Driver/Receiver

LH
HL

2.0
2.0

6.5
5.7

4.5

DM74AS242
Bus Transceiver

LH
HL

2.0

6.5

4.5

2.0

5.7

3.7

DS3896
BTL Trapezoidal Transceiver

Rx
Tx

5.0
5.0

18.0
15.0

13.0
10.0

DS3893
BTL Turbo Transceiver

Rx
Tx

2.0
2.0

8.0
7.0

6.0
5.0

DM74AS86
2-lnputXOR

Note: Values in boldface are those used in the preceding calculations.

2-87

3.7

Setup/Hold

2.0/3.0
2.0/3.0
2.0/3.0

.

U1
.....
~

~National

~ Semiconductor

DS75160A/DS75161A/DS75162A
IEEE-488 GPIB Transceivers
General Description

Features

This family of high-speed-Schottky 8-channel bi-directional
transceivers is designed to interface TTL/MaS logic to the
IEEE Standard 488-1978 General Purpose Interface Bus
(GPIB). PNP inputs are used at all driver inputs for minimum
loading, and hysteresis is provided at all receiver inputs for
added noise margin. The IEEE-488 required bus termination
is provided internally with an active turn-off feature which
disconnects the termination from the bus when Vee is removed. A power up/down protection circuit is included at all
bus outputs to provide glitch-free operation during Vee power up or down.

• 8-channel bi-directional non-inverting transceivers
• Bi-directional control implemented with TRI-STATE®
output design
• Meets IEEE Standard 488-1978
• High-speed Schottky design
• Low power consumption
• High impedance PNP inputs (drivers)
• 500 mV (typ) input hysteresis (receivers)
• On-chip bus terminators
• No bus loading when Vee is removed
• Power up/down protection (glitch-free)
• Pin selectable open collector mode on DS75160A driver outputs
• Accommodates multi-controller systems

The General Purpose Interface Bus is comprised of 16 signallines - 8 for data and 8 for interface management. The
data lines are always implemented with DS75160A, and the
management lines are either implemented with DS75161A
in a single-controller system, or with DS75162A in a multicontroller system.

Connection Diagrams
Dual-In-Llne Package
TE...!.

u

~Vcc

Bl-

2

~Dl

B22-

.,!!.. D2

BJ..!

~D3
~D4

B4..1
BUS

TERMINAL

DS7S160A
BS...!

~DS

B62

~D6

81-!.

~D7

8S-1

~DS

GND..!.!!.

~PE

14

TLIF/5804-1

Top View
Order Number DS75160AN
See NS Package Number N20A

2-88

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

TA, Ambient Temperature

Supply Voltage, Vee
Input Voltage
Storage Temperature Range

10L, Output Low Current
Bus
Terminal

Vee, Supply Voltage

7.0V
5.5V
- 65°C to + 150°C

Lead Temperature (Soldering, 4 sec.)
Maximum Power Dissipation· at 25°C
Molded Package
-Derate molded package 15.2 mW/,C above 25'C.

c
en
......

Operating Conditions

(Note 1)

Min
4.75

Max
5.25

Units
V

0

70

°C

48
16

mA
mA

260°C

N

Min

Typ

Max

Units

0.8

V

VIL
VIK

Input Clamp Voltage

VHYS

Input Hysteresis

Bus

VOH

High-Level
Output Voltage

Terminal
Bus (Note 5)

Low-Level
Output Voltage

Terminal

10L = 16 mA

0.3

0.5

Bus

10H = 48 mA

0.4

0.5

VI = S.SV

0.2

100

VI = 2.7V

0.1

20

-10

-100

)LA

3.0

3.7

V

IlL

Low-Level
Input Current

VSIAS

Terminator Bias
Voltage at Bus Port

ILOAD

Terminator
Bus Loading
Current

2

11= -18mA

V

-0.8
400

500

10H = - 800 )LA

2.7

3.5

10H = -5.2mA

2.5

3.4

VI = O.SV
Driver
Disabled

II(bus) = 0 (No Load)
VI(bus) = -1.SV to O.4V
VI(bus) = O.4V to 2.5V

Bus

Driver
Disabled

2.5

lee

Short-Circuit
Output Current
Supply Current

-1.5

V

2.5
-3.2

VI(bus) = 2.SV to 3.7V
VI(bus) = 3.7V to SV

0

2.5

VI(bus) = 5V to 5.5V

0.7

2.5
40
-35

-75

-35

-75

-150

Transmit, TE = 2V, PE = 2V, VI = 0.8V

85

125

Receive, TE = 0.8V, PE = 2V, VI = 0.8V

70

100

DS7S161A

TE = 0.8V, DC = 0.8V, VI = 0.8V

84

125

DS75162A

TE = 0.8V, DC = 0.8V, SC = 2V, VI = 0.8V

85

125

VI = 2V, Vo = OV (Note 4)

Bus (Note 5)
DS75160A

V

)LA

-3.2

0

-15

Terminal

V
mV

-1.3

Vee = OV, VI(bus) = OV to 2.5V
los

U1

l>
Conditions

Low-Level Input Voltage

Terminal and
TE, PE, DC,
SC Inputs

....
....

en
l>
.....
C
U1

Parameter

High-Level
Input Current

en
......

....en

High-Level Input Voltage

IIH

l>
.....

en
......

1897 mW

VIH

VOL

en
o
C

Electrical Characteristics (Notes 2 and 3)
Symbol

....

U1

rnA

)LA
mA

mA

Bus-Port
Bus
Vee = 5V or OV, VI = OV to 2V,
20
30
pF
f = 1 MHz
Capacitance
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified, min/max limits apply across the O'C to + 70'C temperature range and the 4.75V to 5.25V power supply range. All typical
values are for TA = 25'C and Vee = 5.0V.
Note 3: All currents into device pins are shown as positive; all currents out of device pins are shown as negative; all voltages are referenced to ground, unless
otherwise specified. All values shown as max or min are so classified on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: This characteristic does not apply to outputs on DS75161A and DS75162A that are open collector.

CIN

2-89

......+-..:..2 Bl

3

12

4 B3

DS75161A

.::..._++-10......-+-.:.5 84

This device is also an 8-channel bi-directional transceiver
which is specifically configured to implement the eight management signal lines of the IEEE-488 bus. This device,
paired with the DS75160A, forms the complete 16-line interface between the IEEE-488 bus and a single controller instrumentation system. In compliance with the system organization of the management signal lines, the SRO, NDAC,
and NRFD bus port outputs are open collector. In contrast
to the DS75160A, these open collector outputs are a fixed
configuration. The direction control is divided into three
groups. The DAV, NDAC, and NRFD transceiver directions
are controlled by the TE input. The ATN, SRO, REN, and
IFC transceiver directions are controlled by the DC input.
The EOI transceiver direction is a function of both the TE
and DC inputs, as well as the logic level present on the ATN
channel. The port connections to the bus lines have internal
terminators identical to the DS75160A.

BUS

TERMINAL

• B5

.::...-+.....~O:>....+...:... B8

I B1

DS75162A
This device is identical to the DS75161A, except that an
additional direction control input is provided, denoted SC.
The SC input controls the direction of the REN and IFC
transceivers that are normally controlled by the DC input on
the DS75161A. This additional control function is instrumental in implementing multiple controller systems.
Table of Signal Line Abbreviations
Signal Line
MneClassiDefinition
Device
monic
fication
DC
Direction Control
DS75161A1
DS75162A
Control
PE
Pull-Up Enable
DS75160A
Signals
TE
Talk Enable
All
Data
I/O Ports

Management
Signals

SC
81-88

System Controller

8us Side of Device
D1-D8 Terminal Side
of Device
ATN

Attention

DAV

Data Valid

EOI
IFC

End or Identify
Interface Clear

NDAC
NRFD

Not Data Accepted

I B8

TE
PE

Notal:
Nota 2:

Remote Enable

SRO

Service Request

-
.......

TE

c
en

DAY

""

U1
-a.

en
-a.

7 DAY

DAY

>
.......
C
NDAC

en

""

5 NDAC

NDAC

U1
-a.

en
N

>
NRFD

NRFD

NRFD

EOI

EDI

EDI

TERMINAL

TERMINAL

IUS

BUS

';';;"---411--1

1.>--...- + - -___ ATN

--+-----

SRQ

SRQ - - -....-t~~~~-I----~IQ SRO

--+-----

REN

REN - - -....-t ~~-4"'-lI-I----""';;" REI!

-'---"--l ~>-....

REN

IFC

';';;"---411--1 ~>-.....

-'---"--l

ATN ---~-li!>----4~--I-----;;" ATN

>--....- + - - - - - - I F C

IFC - - -....-4

i ) -...- + - - I - - - - - I F C

SC

TLlF/S804-S

DC

TL/F/5B04-6

Nole 1:
Nole 2:

~

-

-6

I

C>

~

-8
-10

-1

0
VI- BUS VOLTAGE (V)

TL/F/5804-14

Reier to Electrical Characteristics table

2-94

c
en
......

Functional Truth Tables

U1
~

en

DS75160A

Control Input
Level

o

>
.....
c
en
......

Data Transceivers

TE

PE

Direction

Bus Port Configuration

H
H

H
L

T
T

L

X

R

Totem-Pole Output
Open Collector Output
Input

U1
~

en
~

>
.....
c

en
......

U1

DS75161A

Control Input Level
TE

DC

H
H

H

L
L

H

H

X
X

H
H

H

L
L

Transceiver Signal Direction

ATN*

L

L

>

EOI REN IFC SRQ NRFD NDAC DAV

R
T
R
T

L

L
X
X

~

en
I\)

R
T
R
T

R
T
R
T

R
R
T
T

T
R
T
R

R
R
T
T

T
T
R
R

T
R
R
T

DS75162A

Control Input Level

Transceiver Signal Direction
ATN*

SC

TE

DC

H
H
H
H

H
H

H

L
L

H

L
L
L
L

H
H

H

L
L

H

X
X
X
X

H

X
X

H
H

H

L
L

L
X
X

H

= High level input

L

=

L
L
L
L

L

EOI REN IFC SRQ NRFD NDAC DAV

R
T
R
T
R
T
R
T

T
T
T
T
R
R
R
R

T
T
T
T
R
R
R
R

T
R
T
R
T
R
T
R

R
R
T
T
R
R
T
T

R
R
T
T
R
R
T
T

T
T
R
R
T
T
R
R

T
R
R
T

Low level input

X = Don't care
T = Transmit, i.e., signal outputted to bus
R = Receive, i.e., signal outputted to terminal
*The ATN signal level is sensed for internal multiplex control of EOI transmission direction logic.

2-95

o

~

CD
CO

en ~National
c.......
o

~

~ Semiconductor

CD

......

en
c OS7640/0S8640 Quad NOR Unified Bus Receiver
General Description

Features

The 057640 and 058640 are quad 2-input receivers designed for use in bus organized data transmission systems
interconnected by terminated 120n impedance lines. The
external termination is intended to be 180n resistor from
the bus to the + 5V logic supply together with a 390n resistor from the bus to ground. The design employs a built-in
input threshold providing substantial noise immunity. Low
input current allows up to 27 driver/receiver pairs to utilize a
common bus.

• Low input current with normal Vee or Vee
OV
(30 /LA typ)
• High noise immunity (1.1V typ)
• Temperature-insensitive input thresholds track bus logic
levels
• TTL compatible output
• Matched, optimized noise immunity for "1" and "0"
levels
• High speed (19 ns typ)

Connection Diagram
Dual-ln-L1ne Package

14

GND

DUT2

DUTl

IN lA

IN 18

IN 28

IN 2A

Tl/F/5805-1

Top View
Order Number DS7640J, DS8640J or DS8640N
See NS Package Number J14A or N14A

Typical Application
120n Unified Data Bus
+5V

+5V

180

--, r- -, rI I
I I

1I

1
__ J

1 1/6

~~7

I I
I I
I I
I

_ ...J

11/4

l2!!8!!!,

-,

390

I

I
1
I

_-1

TlIF/5805-2

2-96

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7.0V

Input Voltage

5.5V

°
Storage Temperature Range

Supply Voltage (Vee)
OS7640
OS8640
Temperature (TA)
OS7640
OS8640

- 65°C to + 150°C

Maximum Power Oissipation* at 25°C
Cavity Package
Molded Package

c
en

Operating Conditions

(Note 1)

.......

0')

Min

Max

Units

4.5
4.75

5.5
5.25

V
V

-55
0

+125
+70

°C
°C

1308mW
1207mW

Electrical Characteristics
The following apply for VMIN :::; Vee:::; VMAX, T MIN:::; T A :::; TMAX, unless otherwise specified (Notes 2 and 3)

VIH

VIL

IIH

Parameter
High Level Input Threshold

Low Level Input Threshold

Maximum Input Current

Conditions
VOUT = VOL

VOUT = VOH

VIN

= 4V

Min

Typ

OS7640

1.80

1.50

V

OS8640

1.70

1.50

V

Maximum Input Current

VIN

= 0.4V, Vee = VMAX

VOH

Output Voltage

10H

= -400 J-tA, VIN = VIL

VOL

Output Voltage

10L

= 16 mA, VIN = VIH

los

Output Short Circuit Current

VIN = 0.5V, Vos

lee

Power Supply Current

VIN

1.50

1.20

V

1.50

1.30

V

= VMAX

Symbol
tpd

80

J-tA

50

J-tA

1.0

50

J-tA
V

0.25

= OV, Vee = VMAX, (Note 4)

-18

0.4

V

-55

mA

40

mA

25

25°C, nominal power supplies unless otherwise noted

Parameter
Propagation Delays

30
1.0

2.4

= 4V, (Per Package)

Switching Characteristics TA =

Units

OS8640

Vee =OV
IlL

Max

OS7640

Vee

Conditions
(Notes 5 and 6)

I
I

Min

Typ

Max

Units

Input to Logic "1" Output

10

23

35

ns

Input to Logic "0" Output

10

15

30

ns

1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the - 55·C to + 125·C temperature range for the 057640 and across the O·C to + 70·C range for
the 058640. All typical values are TA = 25·C and Vee = 5V.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: Fan-out of 10 load, CLOAD = 15 pF total, measured from VIN = 1.5V to VOUT = 1.5V, VIN = OV to 3V pulse.
Note 6: Apply to Vee = 5V, TA = 25·C.
Note

2-97

c
en
CO
0')
~

Lead Temperature (Soldering, 4 seconds)
260°C
'Oerate cavity package 8.7 mWI'C above 25·C; derate molded package
9.7 mW I'C above 25·C.

Symbol

~

o
.......

o

,...
~

CD

en ~National
CO

c
.....
,... ~ Semiconductor
~

CD

1'0

en

c

OS7641/0S8641 Quad Unified Bus Transceiver
General Description

Features

The DS7641 and DS8641 are quad high speed drivers/receivers designed for use in bus organized data transmission
systems interconnected by terminated 1200. impedance
lines. The external termination is intended to be a 1800.
resistor from the bus to the + 5V logic supply together with
a 3900. resistor from the bus to ground. The bus can be
terminated at one or both ends. Low bus pin current allows
up to 27 driver/receiver pairs to utilize a common bus. The
bus loading is unchanged when Vee = OV. The receivers
incorporate tight thresholds for better bus noise immunity.
One two-input NOR gate is included to disable all drivers in
a package simultaneously.

• 4 separate driver/receiver pairs per package
• Guaranteed minimum bus noise immunity of 0.6V, 1.1 V
typ
• Temperature insensitive receiver thresholds track bus
logic levels
• 30 p,A typical bus terminal current with normal Vee or
with Vee = OV
• Open collector driver output allows wire-OR connection
• High speed
• Series 74 TTL compatible driver and disable inputs and
receiver outputs

Connection Diagram
Dual-In-Line Package
vee

BUS 3

BUS 1

IN 3

IN lOUT 1

OUT 3

BUS 4

BUS Z

IN Z

IN 4

OUT 4

OUT Z DISABLE A

DISABLE B GND
TLIF/5806-1

Top View
Order Number DS7641J, DS8641J or DS8641N
See NS Package Number J16A or N16A

Typical Application
1200. Unified Data Bus
+5V

+5V

r----, r---l
I

I
I

I I
I 1
I 1
I 1'/4

_J

~!!!O

1

1
I
I

_J

TL/F/5806-2

2-98

c
Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
Input and Output Voltage

Temperature Range, (TA)
OS7641
OSB641

5.5V
- 65°C to + 150°C

Maximum Power Dissipation· at 25°C
Cavity Package
Molded Package

Max

Units

4.5
4.75

5.5
5.25

V
V

en
co

0)
~

-55
0

+125
+70

°C
°C

260°C

Electrical Characteristics
The following apply for VMIN ~ Vee ~ VMAX, TMIN ~ T A ~ T MAX unless otherwise specified (Notes 2 and 3)

Symbol

Parameter

Min

Conditions

Typ

Max

Units

DRIVER AND DISABLE INPUTS
VIH

Logical "1" Input Voltage

2.0

V

Vil

Logical "0" Input Voltage

II

Logical "1" Input Current

VIN

=

IIH

Logical "1" Input Current

VIN

=

2.4V

40

,...A

III

Logical "0" Input Current

VIN

=

O.4V

-1.6

mA

Vel

Input Diode Clamp Voltage

lOIS = -12 mA, liN
TA = 25°C

-1

-1.5

V

50 mA

0.4

0.7

V

5.5V

=

-12 mA, Isus

=

-12 mA,

O.B

V

1

mA

DRIVER OUTPUT/RECEIVER INPUT
VOlS

Low Level Bus Voltage

VOIS

=

O.BV, VIN

=

2V, Isus

=

IIHS

Maximum Bus Current

VIN

=

O.BV, VSUS

=

4V, Vee

=

VMAX

30

100

,...A

IllS

Maximum Bus Current

VIN

=

O.BV, VSUS

=

4V, Vee

=

OV

2

100

,...A

VIH

High Level Receiver Threshold

VINO

=

16 mA

Vil

Low Level Receiver Threshold

VINO

=
=

O.BV, VOL

O.BV, VOH

=

-400,...A

OS7641

1.BO

1.50

V

OSB641

1.70

1.50

V

OS7641

1.50

1.20

V

OSB641

1.50

1.30

V

0.25

0.4

V

-55

mA

70

mA

RECEIVER OUTPUT
VOH

Logical "1" Output Voltage

VIN

=

VOL

Logical "0" Output Voltage

O.BV, VSUS

=

0.5V, 10H

O.BV, VSUS

=

VIN

=

=

los

Output Short Circuit Current

VOIS = O.BV, VIN = O.BV, VSUS
Vee = VMAX, (Note 4)

Ice

Supply Current

VOIS

=

OV, VIN

=

4V, 10l

=

0.5V, VOS

2V, (per Package)

2-99

2.4

-400,...A

16 mA

=

=

0)
~

c

'Derate cavity package 9.6 mWI'C above 25'C; derate molded package
10.9 mWI'C above 25'C.

1433 mW
1362 mW

Lead Temperature (Soldering, 4 seconds)

Min

'"
.....

.......

Supply Voltage, (VeC>
OS7641
OSB641

7V

Storage Temperature Range

en

Operating Conditions

(Note 1)

OV,

V

-1B
50

.....

.....
~

CD

Q)

U)

c.......
.....
~

CD

......

U)

c

Switching Characteristics TA =
Symbol
tpD

25·C, Vee = 5V, unless otherwise indicated
Conditions

Parameter

Min

Typ

Max

Units

19
15
17
17

30
30
25
25

ns
ns
ns
ns

20
18

30
30

ns
ns

(Note 5)

Propagation Delays (Note 7)
Disable to Bus "1"
Disable to Bus "a"
Driver Input to Bus "1"
Driver Input to Bus "a"
Bus to Logical "1 " Receiver Output
Bus to Logical "0" Receiver Output

(Note 6)

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.

Note 2: Unless otherwise specified

minImax limits apply across the
= 25·C and Vce = 5V.

- 55·C to

+ 125·C temperature range for the OS7641

and across the O·C to

+ 70·C range for

the OS8641. All typical values are for TA

Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: 910 from bus pin to Vee and 2000 from bus pin to ground. CLOAD = 15 pF total. Measured from VIN = 1.5V to Vsus = 1.5V, VIN = OV to 3V pulse.
Note 6: Fan-out of 10 load, CLOAD = 15 pF total. Measured from VIN = 1.5V to VOUT = 1.5V, VIN = OV to 3V pulse.
Note 7: The following apply for Vee = 5V, T A = 25·C unless otherwise specified.

2·100

~--------------------------------------------------------------------.

en
......

~National

en
w
w
......

~ Semiconductor

c

en
......
en

057833/058833/057835/058835
Quad TRI-5TATE® Bus Transceivers

w

U1
......

c

en
en
en
w

General Description

Features

This family of TRI-STATE bus transceivers offers extreme
versatility in bus organized data transmission systems. The
data bus may be unterminated, or terminated DC or AC, at
one or both ends. Drivers in the third (high impedance) state
load the data bus with a negligible leakage current. The
receiver input current is low allowing at least 100 driver/receiver pairs to utilize a single bus. The bus loading is unchanged when Vee = OV. The receiver incorporates hysteresis to provide greater noise immunity. All devices utilize a
high current TRI-STATE output driver. The OS7833/
OS8833 and OS7835/0S8835 employ TRI-STATE outputs
on the receiver also.

• Receiver hysteresis
• Receiver noise immunity
• Bus terminal current for
normal Vee or Vee =

The OS7833/0S8833 are non-inverting quad transceivers
with a common inverter driver disable control and common
inverter receiver disable control.
The OS7835/0S8835 are inverting quad transceivers with a
common inverter driver disable control and a common inverter receiver disable control.

400 mV typ
1.4V typ
80 /-LA max

ov

• Receivers
Sink
Source

16 mA at O.4V max
2.0 mA (Mil) at 2.4V min
5.2 mA (Com) at 2.4V min

• Drivers
Sink

•
•
•
•

50 mA at 0.5V max
32 mA at O.4V max
Source
10.4 mA (Com) at 2.4V min
5.2 mA (Mil) at 2.4V min
Drivers have TRI-STATE outputs
OS7833/0S8833, OS7835/0S8835 receivers have
TRI-STATE outputs
Capable of driving 100n. DC-terminated buses
Compatible with Series 54174

Dual-In-Llne Package
BUS o

Dual-In-Line Package
DUTe

INo

DUT o

BUSc

INc

OUTA

BUSa

INa

OUT a RECEIVER
DISABLE

DRIVER
DISABLE

GND

Vee

BUS o

INo

OUT 0

BUS e

INc

INa

OUTa RECEIVER
DISABLE

OUTe

DRIVER
DISABLE

GND

TL/F/5808-2

TLIF/5808-1

Top View

Top View

Order Number DS7833J, DS8833J
or DS8833N
See NS Package Number J16A or N16A

Order Number DS7835J, DS8835J
or DS8835N
See NS Package Number J16A or N16A

2-101

w
......
c
en

en
en
w

U1

Connection Diagram
Vee

c

In
Cot)

co
co

Absolute Maximum Ratings

en
c

Operating Conditions

(Note 1)

Min

Max

Units

Supply Voltage, Vee
057833/057835
058833/058835

4.5
4.75

5.5
5.25

V
V

Temperature (TA)
057833/057835
058833/058835

-55
0

+125
+70

°C
°C

If Militaryl Aerospace specified devices are required,

'"

contact the National Semiconductor Sales Officel
Distributors for availability and specifications.

en

Supply Voltage

Cot)
Cot)

co
co

c

7.0V

Input Voltage

5.5V

In
'"

Output Voltage

5.5V

co
......

Storage Temperature

Cot)

en
c

- 65°C to + 150°C

Maximum Power Oissipation· at 25°C
Cavity Package
Molded Package

'"
Cot)
Cot)

co
......

1509 mW
1476mW

Lead Temperature (50Idering, 4 sec.)

en
c

260°C

"Derate cavity package 10.1 mWrC above 25°C; derate molded package
11.8 mWrC above 25°C.

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Conditions

Min

Typ

Max

Units

DISABLE/DRIVER INPUT
VIH

High Level Input Voltages

Vee

= Min

VIL

Low Level Input Voltage

Vee

= Min

IIH

High Level Input Current

Vee

V

2.0

= Max

057833,058833,058835

0.8

057835

0.7

V

VIN

= 2.4V

40

IlA

VIN

= 5.5V

1.0

rnA

IlL

Low Level Input Current

Vee

= Max, VIN = O.4V

-1.0

-1.6

rnA

VeL

Input Clamp Oiode

Vee

= 5.0V, liN = -12mA, TA = 25°C

-0.8

-1.5

V

liT

Oriver Low Level Oisabled
Input Current

Oriver Oisable Input

-40

IlA

V

= 2.0V, VIN = O.4V

RECEIVER INPUTtBUS OUTPUT
VTH

High Level Threshold Voltage

VTL

Low Level Threshold Voltage

Is

Bus Current, Output Oisabled
or High

VOH

VOL

los

Logic "1" Output Voltage

Logic "0" Output Voltage

Output 5hort Circuit Current

Vsus

= 4.0V

Vee

= Max

Vee

= OV

Vee

= Max, Vsus = O.4V

Vee

= Min

Vee

= Min

Vee

= Max, (Note 4)

Vee

= Min

057833, 057835

1.4

1.75

2.1

058833, 058835

1.5

1.75

2.0

V

057833,057835

0.8

1.35

1.6

V

058833, 058835

0.8

1.35

1.5

V

25

80

IlA

5.0

80

IlA

-2.0

-40

IlA

lOUT

= - 5.2 rnA

057833, 057835

2.4

2.75

V

lOUT

= -10.4 rnA 058833, 058835

2.4

2.75

V

lOUT

= 50mA

lOUT

= 32mA

0.28

-40

-62

0.5

V

0.4

V

-120

rnA

RECEIVER OUTPUT
VOH

Logic "1" Output Voltage

lOUT

= - 2.0 rnA

057833, 057835

2.4

3.0

V

lOUT

= - 5.2 rnA

058833, 058835

2.4

2.9

V

= Min,lOUT = 16 rnA
= Max,Oisable VOUT = 2.4V
Inputs = 2.0V
VOUT = O.4V

VOL

Logic "0" Output Voltage

Vee

lOT

Output Oisabled Current

Vee

2·102

0.22

0.4

V

40

IlA

-40

IlA

c

en
.......

Electrical Characteristics (Notes 2 and 3) (Continued)
Symbol

Parameter

Typ

Max

Units

OS7833, OS7835

28

-40

-70

mA

co

OS8833, 058835

-30

-70

mA

""
c
en

RECEIVER OUTPUT (Continued)
Output Short Circuit Current

lOS

Supply Current

lee

Vee = Max, (Note 4)

Vee = Max

OS7833, OS8833

84

116

mA

OS7835, OS8835

75

95

mA

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the - 55·C to + 125·C temperature range for the D87833, D87835 and across the O·C to
range for the 088833, 088835. All typicals are given for Vee = 5.0V and T A = 25·C.

+ 70·C

Note 4: Only one output at a time should be shorted.

Symbol

5.0V, TA = 25°C

Parameter

tpdQ

(Figure 1)

tpdl

Propagation Oelay to a Logic "1"
from Input to Bus

(Figure 1)

tpdQ

Propagation Oelay to a Logic "0"
from Bus to Input

(Figure 2)

tpdl

Propagation Oelay to a Logic "1"
from Bus to Input

(Figure 2)

Oelay from Oisable Input to High
Impedance State (from Logic "1" Level)

CL = 5.0 pF,
(Figures 1 and 2)

Oelay from Oisable Input to High
Impedance State (from Logic "0" Level)

CL = 5.0 pF,
(Figures 1 and 2)

Oelay from Oisable Input to Logic
"1" Level (from High Impedance State)

CL = 5.0 pF,
(Figures 1 and 2)

Oelay from Oisable Input to Logic
"0" Level (from High Impedance State)

CL = 5.0 pF,
(Figures 1 and 2)

tpHZ

tpLZ

tpZH

tPZL

Typ

Max

Units

OS7833/0S8833

14

30

ns

OS7835/0S8835

10

20

ns

OS7833/0S8833

14

30

ns

OS7835/0S8835

11

30

ns

OS7833/0S8833

24

45

ns

OS7835/0S8835

16

35

ns

OS7833/0S8833

12

30

ns

OS7835/0S8835

18

30

ns

Conditions

Propagation Oelay to a Logic "0"
from Input to Bus

Min

Oriver

8.0

20

ns

Receiver

6.0

15

ns

Oriver

20

35

ns

Receiver

13

25

ns

Oriver

24

40

ns

Receiver

16

35

ns
ns

Oriver

19

35

Receiver OS7833/0S8833

15

30

ns

Receiver OS7835/0S8835

33

50

ns

AC Test Circuits
Vcc
(

Vce
(

:: 100

.....
OUTPUT .....

CL
50 pF

..L

T
':'

:.400

4

~

L .....
I .......

--......J
l1li""""1

•.....1

IIIIo.....L

,.....1

,...1

CL
50 pF

:.1.0k

~

-1..

OUTPUT -

...

-==

4·

T
':'

~

I ......
..

~1III..1

~.

l1li""""1

..... 1

l1li""""1

~

:.1.0k

~

TL/F/5808-3

~
TL/F/5808-4

FIGURE 1. Driver Output Load

FIGURE 2. Receiver Output Load

2-103

c
""
en
.......

w

U1

co
co
w
w

c
""
en
co
co
w

U1

Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.

Switching Characteristics Vee =

co
w
w

Min

Conditions

Ln
~

CIO
CIO

en
o
......

Switching Time Waveforms

~
~

tpLZ

tpd1 & tpdO

CIO
CIO

J.OV

en

o
......

INPUT

.,-----,\1

~ .5V

1\.5V

--It,.dO!--

--tt,.dl,.-

ov.Jl

Ln
~

CIO

......

en
o
......

OUTPUT

(INVERTED)

1

1\
I

I

•

I

I.d! 14I
I

CIO

f

--I t,.dO

l

......

en
o

OUTPUT _ _ _I _

(NON INVERTED)

1

r-

PI

_ - - - - - - ..I.SV

OUTPUT
ACTUAL LO~~t~~~; _ _ _ _ _ _ _- .

\L' -.l._SV
. . _ __

l.SV

•

--ltoH~

1

I'

I

--J

~
~

INP::

1,.----

II sv

1 SV

I

'-:-1- - - -

1

-----t.

J.OV - - - - - - , , . . - - - - - - - - -

O.SV
TLIF/5808-6

J

TL/F/5808-5

f

= 1 MHz

tr

=

t, ,,;; 10 ns (10% to 90%)

DUTY CYCLE

=

50%

JV----------7--------INPUT

I"

oV - - - - I

ACTUAL LOGICAL "I"
VOLTAGE
OUTPUT

I
1

1

JV----~~,!
INPUT

r\.5V

OV-------fl-'"--------

I

O.5V

~
1

~'!H--1

:

J

------

"1.5V

OUTPUT

t

~~::'-

"'1.5V

I--IHO--j~ ACTUAL LOGICAL "0"
i
VOLTAGE

1

TLIF/5808-8

TL/F/5808-7

tPZH
3V---~

INPUT

\'.

OV---------~I-'------------------

I

~

OUTPUT

I
II

1
/-1
1 __ _

""1.5V------

ACTUAL LOGICAL "1"

'-j-------- VOLTAGE

O.5V
--r
TL/F/5808-9

2-104

c

en
......

~National

co

w

~ Semiconductor

oI:ao
......

c

en

co
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OS7834/0S8834/0S7839/0S8839 Quad TRI-STATE®
Bus Transceivers
Features

This family of TRI-STATE bus transceivers offers extreme
versatility in bus organized data transmission systems. The
data bus may be unterminated, or terminated DC or AC, at
one or both ends. Drivers in the third (high impedance) state
load the data bus with a negligible leakage current. The
receiver input current is low, allowing at least 100 driver/receiver pairs to utilize a single bus. The bus loading is unchanged when Vee = OV. The receiver incorporates hysteresis to provide greater noise immunity. Both devices utilize a
high current TRI-STATE output driver. The OS7834/
OS8834 and OS7839/0S8839 employ TTL outputs on the
receiver.

• Receiver hysteresis
• Receiver noise immunity
• Bus terminal current for
normal Vee or Vee = OV

The OS7834/0S8834 are inverting quad transceivers with
two common inverter driver disable controls.

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......

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General Description

The OS7839/0S8839 are non-inverting quad tranceivers
with two common inverter driver disable controls.

oI:ao
......

• Receivers
Sink
Source

400 mV typ
1.4V typ
80 p.A max

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......

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16 mA at O.4V max
2.0 mA (Mil) at 2.4V min
5.2 mA (Com) at 2.4V min

• Drivers
Sink

•
•
•
•

50 mA at 0.5V max
32 mA at O.4V max
10.4 mA (Com) at 2.4V min
Source
5.2 mA (Mil) at 2.4V min
Drivers have TRI-STATE outputs
Receivers have TRI-STATE outputs
Capable of driving 1000. DC-terminated Buses
Compatible with Series 54/74

Connection Diagrams
Dual-In-Line Package

Dual-In-Line Package
BUSo

INo

OUTo

BUSc

INc

OUTc

DRIVER
DISABLE

BUS o

INo

OUTo

BUSc

INc

OUTc

DRIVER
DISABLE

fJI
INB

OUTB

DRIVER
DISABLE

GND

INB

TLIF/5809-1

OUT B

DRIVER
DISABLE

Top View

Top View

Order Number DS7834J, DS8834J or DS8834N
See NS Package Number J16A or N16A

Order Number DS7839J, DS8839J or DS8839N
See NS Package Number J16A or N16A

2-105

GND

TL/F/5809-2

D)
C")

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Absolute Maximum Ratings

C

If Military/Aerospace specified devices are required,

5torage Temperature

contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Lead Temperature (50Idering, 4 seconds)

5upply Voltage

7.0V

Operating Conditions

Input Voltage

5.5V

Output Voltage

5.5V

U)

........
D)
C")

co
......

U)

c........
~
C")

co
co

U)

C

........
~

C")

co
......
c
U)

(Note 1)

Maximum Power Oissipation* at 25°C
Cavity Package
Molded Package

1509 mW
1476 mW

·Oerate cavity package 10.1 mWI'C above 25°C; derate molded package
11.8 mW1°C above 25°C.

- 65°C to + 150°C
260°C

Min

Max

Units

5upply Voltage (Vee>
057834, 057839
058834, 058839

4.5
4.75

5.5
5.25

V
V

Temperature (TA)
057834, 057839
058834, 058839

-55
0

+125
+70

°C
°C

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Conditions

Min

Typ

Max

Units

DISABLE/DRIVER INPUT
VIH

High Level Input Voltage

Vee = Min

VIL

Low Level Input Voltage

Vee = Min

IIH

High Level Input Current

Vee = Max

2.0

V
0.8

V

VIN = 2.4V

40

IJ-A

VIN = 5.5V

1.0

mA

-1.6

mA

-40

IJ-A

-0.8

-1.5

V

-1.0

IlL

Low Level Input Current

Vee = Max, VIN = O.4V

liND

Driver Oiasbled Input
Low Current

Driver Disable Input = 2.0V, VIN = O.4V

Vel

Input Clamp Diode

Vee = 5.0V, liN = -12 mA, TA = 25°C

RECEIVER INPUT/BUS OUTPUT
VTH

High Level Threshold Voltage

Vee = Max

VTl

Low Level Threshold Voltage

Vee = Min

ISH

Bus Current, Output
Disabled or High

Vsus = 4.0V

057834, 057839

1.4

1.75

2.1

V

058834, 058839

1.5

1.75

2.0

V

057834, 057839

0.8

1.35

1.6

V

058834, 058839

0.8

1.35

1.5

V

Vee = Max, Disable Input = 2.0V

25

80

IJ-A

Vee = OV

5.0

80

IJ-A

-40

IJ-A

Vee = Max, Vsus = O.4V, Disable Input = 2.0V
VOH

VOL

Logic "1" Output Voltage

Logic "0" Output Voltage

Vee = Min

Vee = Min

lOUT = -5.2 mA

057834, 057839

2.4

2.75

lOUT = -10.4 mA

057834, 058839

2.4

2.75
0.28

lOUT = 50 mA
lOUT = 32 mA

los

Output 5hort Circuit Current

Vee = Max, (Note 4)

-40

-62

V
V
0.5

V

0.4

V

-120

mA

RECEIVER OUTPUT
VOH

Logic "1" Output Voltage

Vee = Min

lOUT = - 2.0 mA

057834, 057839

2.4

3.0

lOUT = - 5.2 mA

058834, 058839

2.4

2.9

VOL

Logic "0" Output Voltage

Vee = Min, lOUT = 16 mA

los

Output 5hort Circuit Current

Vee = Max, (Note 4)

lee

5upply Current

Vee = Max

057834, 057839

-28

058834, 058839

-30

V
V

0.22

0.4

V

-40

-70

mA

-70

mA

95

mA

75

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.

Note;;:; Jnless othE.wise specified. minImax limits apply across the -55°C to
range for the 088834, 088839. All typicals are given for Vee

+ 125°C temperature range for the 057834, 057839 and across the O°C to + 70°C

= 5.0V and TA = 25°C.

Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.

Note 4: ("I"ly one outj:>ut at a time should be shorted.

2·106

Switching Characteristics Vee =
Symbol

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en
.....

5.0V, T A = 25°C

Parameter

(X)

Min

Conditions

Propagation Delay to a Logic "0"
from Input to Bus

(Figure 1)

tpdl

Propagation Delay to a Logic "1"
from Input to Bus

(Figure 1)

tpdO

Propagation Delay to a Logic "0"
from Bus to Output

(A"gure2)

tpd1

Propagation Delay to a Logic" 1"
from Bus to Output

(Figure 2)

tpHZ

Delay from Oisable Input to High
Impedance State (from Logic" 1" Level)

CL = 5.0 pF, (Figures 1 and 2) Oriver Only

tpLZ

Delay from Disable Input to High
Impedance State (from Logic "0" Level)

CL = 5.0 pF, (Figures 1 and 2) Oriver Only

tpZH

Delay from Disable Input to Logic
"1" Level (from High Impedance State)

CL = 50 pF, (Figures 1 and 2) Driver Only

tpZL

Delay from Disable Input to Logic
"0" Level (from High Impedance State)

CL = 50 pF, (Figures 1 and 2) Driver Only

tpdO

Max

Typ

C

14

30

ns

OS7834/0S8834

10

20

ns

(X)

OS7839/0S8839

14

30

ns

........

11

30

ns

en
.....

24

45

ns

OS7834/0S8834

16

35

ns

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........

OS7839/0S8839

12

30

ns

en
(X)

Vee
(

. ......,
,......

18

30

ns

8

20

ns

20

35

ns

24

40

ns

19

35

ns

• ~ 400

• ~ 100

OUTPUT

T
C.-'--

50 p~

I ......

T

:=

-=

'*

...... ,

JIll"" I

....... I

JIll"" I

I....

T

OUTPUT

......,

,

..... 1

......

...... ,

.......

FT

.~

Cl
50 P

1.0k

-:: -

-'--

~
TL/F/S809-4

TLIF/S809-3

FIGURE 2. Receiver Output Load

FIGURE 1. Driver Output Load

Switching Time Waveforms
tpLZ

tpd1 and tpdO

K"

l.OV

3V---·r----'"

INPUTJ5V
ov:

---jt,.dOr-I

! \1.5V
I
----lI tpdl If---

OUTPUT

(INVERTED)

(NONINV~~!ie~~

l

___
1 --I

1.5V

INP~:

11----

~tpdlr-I

I

tOH'---

I _------"'1.5V

OUTPUT:~

ACTUAL LOGICAL "a"
VOLTAGE

I

--.j tpdO ~

I

~",,1.5_V

T------J--r
0.5V
TLlF/S809-6

_ __
TL/F/S809-S

f = 1 MHz
Ir = If:S; 10 ns (10% 10 90%)

Duty Cycle

...,,1..

___

--j

I~----

i f1.5V

= 50%

2-107

~

C

OS7839/0S8839

(

..... 1

w

OS7834/0S8834

OS7834/0S8834

......,

en
(X)

OS7839/0S8839

Vee

.

~

........

AC Test Circuit

I....

w

Units

(X)

C

(X)

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en
CW)
co
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(/)

Switching Time Waveforms

(Continued)

C
......

en
CW)

3v------------r------------------

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.....
c
......

....II.

(/)

v

INPUT _______

~

CW)

OV

(/)

ACTUAL LOGICAL "I"
VOL TAGE

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C
......

I

I'J". . ._____

i

OUTPUT

~

O.SV

l--.-t

----------II-----~_.

CW)

"'I.SV

t--tIH~

co

.....
c

TL/F/5809-7

(/)

tPZL
3V ---------~

~~:_u,. .

INP:: ___________

V_____________
""'--....Jt'----"'I.SV

_ _ _ _ _ _-:-.I_ _ _

:
OUTPUT

\

O.SV

: - - - tHO--!\

T

ACTUAL LOGICAL "0"

I ""------ VOLTAGE

I

TL/F/5809-8

INP::

tPZH

------.\.v

OV----------rl~.'------------------

I
I

tHI

~
I

I
I
OUTPUT

I

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f-~v--r

e~I~:~~OGICAL "I"

"'1.SV-------.I

TLIF/5809-9

Truth Table
Oisable
Input

Oriver
Input
(INx)

ReCeiver Input!
Bus Output
(BU5x)

Receiver
Output
(OUTx)

Mode of
Operation

0
1

BUS
1
0

Receive Bus Signal
Drive Bus
Drive Bus

1
0

BUS
1
0

Receive Bus Signal
Drive Bus
Drive Bus

057834/058834
1
0
0

X
1
0

057839/058839
1
0
0

x=

X
1
0

Don't care

2-108

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057836/058836 Quad NOR Unified Bus Receiver

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General Description

Features

The D57836/D58836 are quad 2-input receivers designed
for use in bus organized data transmission systems interconnected by terminated 1200 impedance lines. The external termination is intended to be 1800 resistor from the bus
to the + 5V logic supply together with a 3900 resistor from
the bus to ground. The design employs a built-in input hysteresis providing substantial noise immunity. Low input current allows up to 27 driver/receiver pairs to utilize a common bus. Performance is optimized for systems with bus
rise and fall times $; 1.0 }J-slV.

• Low input current with normal Vee or Vee
OV
(15 }J-A typ)
• Built-in input hysteresis (1 V typ)
• High noise immunity (2V typ)
• Temperature-insensitive input thresholds track bus logic
levels
• TTL compatible output
• Matched, optimized noise immunity for "1" and "0"
levels
• High speed (18 ns typ)

Typical Application
1200 Unified Data Bus

.sv

+SV

180

180

--1

390

--1

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I I
I I

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I

-=-

r-

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_...1

390

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I 1116

J

-, r- -,
11/4

~~

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TL/F/SB10-l

Connection Diagram
Dual-In-Line Package
OUT 3

OUT 4

IN 4A

IN 48

IN 3A

IN 38

Vee

OUT 2

OUT 1

IN lA

IN 18

IN 2A

IN 28

14

GNO

TL/F/SB10-2

Top View
Order Number DS7836J, DS8836J or DS8836N
See NS Package Number J14A or N14A

2-109

CD

('t)

CO
CO

Absolute Maximum Ratings

c.......
('t)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

......

Supply Voltage

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Operating Conditions
Supply Voltage (Vee)
OS7836
OS8836
Temperature (TA)
OS7836
OS8836

7.0V

Current Voltage

5.5V

Storage Temperature Range

- 65°C to + 150°C

Maximum Power Oissipation* at 25°C
Cavity Package
Molded Package

Min

Max

Units

4.5
4.75

5.5
5.25

V
V

-55
0

+125
+70

°C
°C

1308 mW
1207 mW

Lead Temperature (Soldering, 4 seconds)
260°C
·Derate cavity package 8.7 mWI'C above 25'C; derate molded package 9.7
mW rc above 25·C.

Electrical Characteristics
The following apply for VMIN

Symbol
VTH

:0;;

Vee

:0;;

VMAX, TMIN

:0;;

TA

Parameter
High Level Input Threshold

:0;;

T MAX, unless otherwise specified (Notes 2 and 3)

Min

Typ

Max

Units

OS7836

1.65

2.25

2.65

V

OS8836

1.80

2.25

2.50

V

OS7836

0.97

1.30

1.63

V

OS8836

1.05

1.30

1.55

V

15

50

p,A

1

50

p,A

Conditions
Vec = Max

VIL

Low Level Input Threshold

Vee = Min

liN

Maximum Input Current

VIN = 4V

VOH

Logical "1" Output Voltage

VIN = 0.5V, lOUT = -400 p,A

I Vee =
I Vee =

Max
OV

V

2.4
0.25

Logical "0" Output Voltage

VIN = 4V, lOUT = 16 mA

Isc

Output Short Circuit Current

VIN = 0.5V, VOUT = OV, Vee = Max, (Note 4)

lec

Power Supply Current

VIN = 4V, (Per Package)

25

VCl

Input Clamp Diode Voltage

liN = -12 mA, TA = 25°C

-1

VOL

Switching Characteristics Vee =
Symbol
tpd

V

-55

mA

40

mA

-1.5

V

5V, TA = 25°C unless otherwise specified

Typ

Max

Units

Input to Logical "1" Output

20

30

ns

Input to Logical "0" Ouptut

18

30

ns

Conditions

Parameter
Propagation Delays

-18

0.4

(Notes 4 and 5)

I
I

Min

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified min/max limits apply across the - 55'C to + 125'C temperature range for the 057836 and across the O'C to + 70'C range for
the 058836. All typical values are for TA = 25'C and Vee = 5V.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Fan-out of 10 load, CLOAD = 15 pF total, measured from VIN = 1.3V to VOUT = 1.5V. VIN = OV to 3V pulse.
Note 5: Fan-out of 10 load, CLOAD = 15 pF total, measured from VIN = 2.3V to VOUT = 1.5V, VIN = OV to 3V pulse.

2-110

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......

087837/088837 Hex Unified Bus Receiver

Q)

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w

........

General Description

Features

The D87837/DS8837 are high speed receivers designed for
use in bus organized data transmission systems interconnected by terminated 1200 impedance lines. The external
termination is intended to be 1800 resistor from the bus to
the + 5V logic supply together with a 3900 resistor from the
bus to ground. The receiver design employs a built-in input
hysteresis providing substantial noise immunity. Low input
current allows up to 27 driver/receiver pairs to utilize a common bus. Disable inputs provide time discrimination. Disable
inputs and receiver outputs are TTL compatible. Performance is optimized for systems with bus rise and fall times
:0;;1.0 p.slV.

• Low receiver input current for normal Vee or Vee = OV
(15 p.A typ)
• Six separate receivers per package
• Built-in receiver input hysteresis (1V typ)
• High receiver noise immunity (2V typ)
• Temperature insensitive receiver input thresholds track
bus logic levels
• TTL compatible disable and output
• Molded or cavity dual-in-line or flat package
• High speed

Typical Application
+5V

+5V

180

180

r- ---, r- ---,

--1

390

I
I
I

I I

I

I

I I

I I
11/4

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390

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_...1
TLlF/5811-1

Connection Diagram
Dual-In-Llne Package
Vee

IN 4

IN lOUT 1

OUT 4

IN 5

IN 2

OUT 2

OUT 5

IN 6

IN J

OUT J

DISABLE A

OUT 6 DISABLE B

GND

TL/F/5811-2

Top View
Order Number DS7837J, DS8837J,
DS8837M or DS8837N
See NS Package Number J16A, M16A or N16A
2-111

r--

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Absolute Maximum Ratings

C
.......
r--

If Military! Aerospace specified devices are required,
contact the National Semiconductor Sales Office!
Distributors for availability and specifications.
Supply Voltage
7V

(f)

C")

co
r--

(f)

C

Operating Conditions

(Note 1)

Supply Voltage, (Vee)
DS7837
DS8837
Temperature (TA)
DS7837
DS8837

Input Voltage
5.5V
Operating Temperature Range
DS7837
- 55°C to + 125°C
DS8837
O°Cto + 70°C
Storage Temperature Range
- 65°C to + 150°C
Maximum Power Dissipation* at 25°C
Cavity Package
1433 mW
Molded DIP Package
1362mW
SO Package
1002mW
Lead Temperature (Soldering, 4 seconds)
260°C
'Derate cavity package 9.6 mW 1°C above 25°C; derate molded DIP package
10.9 mwrc above 25°C; derate SO package 8.01 mwrc above 25°C.

Min

Max

Units

4.5
4.75

5.5
5.25

V
V

-55
0

+125
+70

°C
°C

Electrical Characteristics
The following apply for VMIN ~ Vee ~ VMAX, T MIN ~ T A ~ T MAX, unless otherwise specified (Notes 2 and 3)
Symbol

VTH

VTl

IIH

Parameter

High Level Receiver Threshold

Low Level Receiver Threshold

Maximum Receiver Input Current

III

Logical "0" Receiver Input Current

VIH

Logical "1" Input Voltage

Min

Conditions

Vee = Max

Vee = Min

VIN = 4V

Typ

Max

DS7837

1.65

2.25

2.65

V

DS8837

1.80

2.25

2.50

V

DS7837

0.97

1.30

1.63

V

DS8837

1.05

1.30

1.55

V

Vee = VMAX

15.0

50.0

J.LA

Vee = OV

1.0

50.0

J.LA

1.0

50.0

J.LA

VIN = O.4V, Vee = VMAX
Disable

2.0

V

Disable

0.8

V

VIND = 2.4V

80.0

J.LA

2.0

mA

-3.2

mA

Vil

Logical "0" Input Voltage

IIH

Logical "1" Input Current

Disable Input

III

Logical "0" Input Current

VIN = 4V, VIND = 0.4V, Disable Input

VOH

Logical "1" Output Voltage

VIN = 0.5V, VIND = 0.8V,
IOH = -400 J.LA

VOL

Logical "0" Output Voltage

VIN = 4V, VIND = 0.8V, IOH = 16 mA

los

Output Short Circuit Current

VIN = 0.5V, VIND = OV, Vos = OV,
Vee = VMAX, (Note 4)

Icc

Power Supply Current

VIN = 4V, VIND = OV, (Per Package)

Vel

Input Clamp Diode

VIN = -12 mA, VIND = -12 mA,
TA = 25°C

VIND = 5.5V

2-112

Units

2.4

V
0.25

0.4

V

-55.0

mA

45.0

60.0

mA

-1.0

-1.5

V

-18.0

c

Switching Characteristics TA =
Symbol
tpd

=

OV,

Receiver
Input = OV,
Disable, (Note 7)

Units

.......
......

Input to Logical "1" Output, (Note 5)

20

30

ns

en
Q)

Input to Logical "0" Output, (Note 6)

18

30

ns

Q)

Input to Logical "1" Output

9

15

ns

Input to Logical "0" Output

4

10

ns

Min

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the -55'C to
the D58837. All typical values are for TA = 25'C and Vee = 5V.

+ 125'C temperature range for the D57837 and across the D'C to + 7D'C range for

Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: Fan-out of 10 load, CLOAD
Note 6: Fan-out of 10 load, CLOAD
Note 7: Fan-out of 10 load, CLOAD

=
=
=

15 pF total. Measured from VIN
15 pF total. Measured from VIN
15 pF total. Measured from VIN

w

Max

Conditions

VIND

Q)

Typ

Parameter
Propagation Delays

en
.......

25°C, nominal power supplies unless otherwise noted

=
=
=

1.3V to VOUT
2.3V to VOUT
1.5V to VOUT

2-113

=
=
=

1.5V, VIN
1.5V, VIN
1.5V, VIN

=
=
=

OV to 3V pulse.
OV to 3V pulse.
OV to 3V pulse.

C

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.......

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~ OS7838/0S8838 Quad Unified Bus Transceiver
General Description

Features

The 087838/088838 are quad high speed drivers/receivers designed for use in bus organized data transmission
systems interconnected by terminated 120n impedance
lines. The external termination is intended to be 180n resistor from the bus to the + 5V logic supply together with a
390n resistor from the bus to ground. The bus can be terminated at one or both ends. Low bus pin current allows up to
27 driver/receiver pairs to utilize a common bus. The bus
loading is unchanged when Vee = OV. The receivers incorporate hysteresis to greatly enhance bus noise immunity.
One two-input NOR gate is included to disable all drivers in
a package simultaneously. Receiver performance is optimized for systems with bus rise and fall times::;: 1.0 p.slV.

•
•
•
•

4 totally separate driver/receiver pairs per package
1V typical receiver input hysteresis
Receiver hysteresis independent of receiver output load
Guaranteed minimum bus noise immunity of 1.3V, 2V
typo
Temperature-insensitive receiver thresholds track bus
logic levels
20 p.A typical bus terminal current with normal Vee or
with Vee =
Open collector driver output allows wire-OR connection
High speed
8eries 74 TTL compatible driver and disable inputs and
receiver outputs

•
•

ov

•
•
•

Typical Application
+5V

+5V

180

--, r-

390

390

I 1
I 1
I I
1

_ -1

11/4
L.!!!7~
TL/F/5812-1

Connection Diagram
Dual-ln-L1ne Package
vee

BUS 1

IN lOUT 1

BUS 2

IN 2

OUT 2 DISABLE A

TL/F/5812-2

Top View
Order Number DS7838J, DS8838J, DS8838M or DS8838N
See NS Package Number J16A, M16A or N16A
2-114

c

Absolute Maximum Ratings

en
.....

(Note 1)

00

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7V

Input and Output Voltage
Storage Temperature Range

w

Maximum Power Dissipation" at 25°C
Cavity Package
Molded DIP Package
SO Package

- 65°C to + 150°C

Lead Temperature, (Soldering, 4 sec.)
260°C
"Derate cavity package 9.6 mWI"C above 25°C; derate molded DIP package
10.9 mWI"C above 25°C; derate SO package 8.01 mW/"C above 25°C.

- 55°C to + 125°C
O°Cto +70°C

Electrical Characteristics
OS7838/0S8838: The following apply for VMIN ~ Vcc ~ VMAX. TMIN ~ T A ~ T MAX. unless otherwise specified (Notes 2 and 3)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

DRIVER AND DISABLE INPUTS
VIH

Logical "1" Input Voltage

Vil

Logical "0" Input Voltage

II

Logical "1 " Input Current

VIN

=

IIH

Logical "1" Input Current

VIN

III

Logical "0" Input Current

VIN

VCl

Input Diode Clamp Voltage

lOIs = -12 mA.IIN
TA = 25°C

2.0

V
0.8

V

5.5V

1

mA

=

2.4V

40

fJ-A

=

O.4V

-1.6

mA

-1.5

V

=

-12 mA,lsus

=

-12 mA,

-1

DRIVER OUTPUT/RECEIVER INPUT

=

VOlS

Low Level Bus Voltage

VOIS

IIHS

Maximum Bus Current

VIN

=

0.8V, Vsus

=

0.8V, Vsus

0.8V, VIN

IllS

Maximum Bus Current

VIN

VIH

High Level Receiver Threshold

VINO = 0.8V. 10l
Vee = Max

Vil

Low Level Receiver Threshold

=

2V, Isus

=

50 mA

0.4

0.7

V

4V. Vee

=

VMAX

20

100

fJ-A

4V, Vee

=

OV

=
=
=

VINO = 0.8V, VOH
Vee = Min

=

2

100

fJ-A

1.65

2.25

2.65

V

OS8838

1.80

2.25

2.50

V

OS7838

0.97

1.30

1.63

V

OS8838

1.05

1.30

1.55

V

OS7838

16 mA

-400 fJ-A

RECEIVER OUTPUT
Logical "1" Output Voltage

VIN

=

0.8V. Vsus

=

0.5V, 10H

VOL

Logical "0" Output Voltage

VIN

=

0.8V. Vsus

=

4V. 10l

los

Output Short Circuit Current

VOIS = 0.8V, VIN = 0.8V, Vsus = 0.5V,
Vos = OV, Vee = VMAX, (Note 4)

Ice

Supply Current

VOIS

VOH

=

OV. VIN

=

=

=

-400 fJ-A

2-115

V

2.4
0.25

16 mA

2V. (Per Package)

00

.......

c
en
00
00

w

Operating Temperature Range
OS7838
OS8838

5.5V

1433 mW
1362 mW
1002 mW

-18
50

0.4

V

-55

mA

70

mA

00

co
Cf)
~

~
........

Electrical Characteristics

087838/088838: The following apply for VMIN ~ Vee ~ VMAX. T MIN ~ T A ~ T MAX. unless otherwise specified (Notes 2 and 3)
(Continued)

co
Cf)
co

Symbol

en

RECEIVER OUTPUT (Continued)

r--

c

tpd

Parameter

Conditions

Typ

Max

Units

(Note 5)

19

30

ns

Disable to Bus "0"

(Note 5)

15

23

ns

Driver Input to Bus "1"

(Note 5)

17

25

ns

Propagation Delays (Note 8)
Disable to Bus "1"

Min

Driver Input to Bus "0"

(Note 5)

9

15

ns

Bus to Logical "1" Receiver Output

(Note 6)

20

30

ns

Bus to Logical "0" Receiver Output

(Note 7)

18

30

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.

Note 2: Unless otherwise specified min/max limits apply across the - 55'C to
the DS8838. All typical values are for T A = 25'C and Vee = 5V.

+ 125'C temperature range for the DS7838 and across the O'C to + 70'C range for

Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: 91 n from bus pin to Vee and 200n from bus pin to ground, CLOAD = 15 pF total. Measured from VIN = 1.5V to Vsus = 1.5V, VIN = OV to 3.0V pulse.
Note 6: Fan-out of 10 load, CLOAD = 15 pF total. Measured from VIN = 1.3V to VOUT = 1.5V, VIN = OV to 3.0V pulse.
Note 7: Fan-out of 10 load, CLOAD = 15 pF total. Measured from VIN = 2.3V to VOUT = 1.5V, VIN = OV to 3.0V pulse.
Note 8: These apply for Vee

=

5V, T A

=

25'C unless otherwise speicified.

2-116

c

en
co

~National

-t
N
en

~ Semiconductor

"-

DS8T26A/DS8T26AM/DS8T28/DS8T28M 4-Bit
Bidirectional Bus Transceivers

co
-t
N
en

General Description

Features

"-

The OS8T26A, OS8T28 consist of 4 pairs of TRI-STATE®
logic elements configured as quad bus drivers/receivers
along with separate buffered receiver enable and driver enable lines. This single IC quad transceiver design distinguishes the OS8T26A, OS8T28 from conventional multi-IC
implementations. In addition, the OS8T26A, OS8T28's ultra
high speed while driving heavy bus capacitance (300 pF)
makes these devices particularly suitable for memory systems and bidirectional data buses.

•
•
•
•
•
•
•
•

en
co

»
c

en

»

3:

c

Inverting outputs in the OS8T26A
Non-inverting outputs in the OS8T28
TRI-ST ATE outputs
Low current PNP inputs
Fast switching times (20 ns)
Advanced Schottky processing
Oriver glitch free power up/down
Non-overlapping TRI-STATE

-t
N
co

"-

C

en

co
-t
N
co
3:

Both the driver and receiver gates have TRI-STATE outputs
and low current PNP inputs. PNP inputs reduce input loading to 200 p,A maximum.

Logic and Connection Diagrams
DS8T26A

DS8T28

TL/F/5813-1

Dual-In-Line Package

Order Number DS8T26AJ, DS8T26AMJ, DS8T28J,
DS8T28MJ, DS8T26AN or DS8T28N
11

DOUT

GND

See NS Package Number J16A or N16A

"OUT

10

IN

DOUT

IN

•

TL/F/5813-3

Top View

2-117

TL/F/5813-2

:e
co
N

t;
(J)

C

......
co

Absolute Maximum Ratings

N

All Output and Supply Voltages

-0.5Vto +7V

co

All Input Voltages

-1Vto +5.5V

C

Output Currents

:e

Storage Temperature

I(J)

......

DS8T26A, DS8T28
DS8T26AM, DS8T28M

1509 mW
1476mW

·Derate cavity package 10.1 mW/,C above 25°C; derate molded package
11.B mW/,C above 25°C.

CD
N

Recommended Operating
Conditions

(Note 1)

If Military! Aerospace specified devices are required,
contact the National Semiconductor Sales Office!
Distributors for availability and specifications.

I

Conditions

I

Min

I

Typ

I

Max

I

Units

DRIVER
IlL

Low Level Input Current

VIN = O.4V

-200

IlL

Low Level Input Current (Disabled)

VIN = O.4V

-25

J.1-A

IIH

High Level Input Current (DIN, DE)

VIN = Vee Max

25

J.1-A

VOL

Low Level Output Voltage
(Pins 3, 6, 10, 13)

lOUT = 48 mA

0.5

V

VOH

High Level Output Voltage,
(Pins 3, 6, 10, 13)

lOUT = -10 mA

lOS

Short·Circuit Output Current,
(Pins 3, 6, 10, 13)

VOUT = OV, Vee =
Vee Max

IlL

Low Level Input Current

VIN = 0.4V

IIH

High Level Input Current (RE)

VIN = Vee Max

VOL

Low Level Output Voltage

lOUT = 20 rnA

VOH

High Level Output Voltage,
(Pins 2, 5, 11, 14)

V

2.4
-50

J.1-A

-150

mA

-200

J.1-A

25

J.1-A

0.5

V

RECEIVER

los

Short-Circuit Output Current,
(Pins 2, 5, 11, 14)

lOUT = -100 J.1-A

3.5

V

lOUT = - 2mA

2.4

V

VOUT = OV, Vee =
Vee Max

-30

0.85

-75

mA

BOTH DRIVER AND RECEIVER
VTL

Low Level Input Threshold Voltage

Vee = Min, VIN = 0.8V,
IOL = Max

VTH

High Level Input Threshold Voltage

Vee = Max, VIN = 0.8V,
10H = Max

102

Low Level Output OFF Leakage
Current

VOUT = 0.5V

102

High Level Output OFF Leakage
Current

VOUT = 2.4V

VI

Input Clamp Voltage

liN = -12mA

lee

Power Supply Current
DS8T26A

Vee = Vee Max

DST28

Vee = Vee Max

V
2

V

-100

J.1-A

100

J.1-A

-1.0

V

87

mA

110

mA

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified, minImax limits apply across the - 55°C to + 125°C temperature range for the DSBT26AM, DSBT2BM and across the DoC to
+ 70°C range for the DSBT26A, DSBT2B. All typicals are given for Vee = 5V and TA = 25°C.
Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.
Note 4: Only one output at a time should be shorted.

2-118

c

Switching Characteristics Vee =
Symbol

en
CD

5V, T A = 25°C

Parameter

-I

Conditions

N

DS8T28
Max

Units

Dour to Rour, (Figure 1)

14

17

ns

-I

tOFF

Dour to Rour, (Figure 1)

14

17

ns

»

tON

DIN to Dour, (Figure 2)

14

17

ns

tOFF

DIN to Dour, (Figure 2)

14

17

ns

CL = 30 pF

CL = 300 pF

»
......

c
en
CD

Propagation Delay
tON

en

DS8T26A
Max

N

en

=:
......
c
en
CD

-I

Data Enable to Data Output

N

tPZL

High Z to 0, (Figure 3)

tpLZ

oto High Z, (Figure 3)

CL = 300 pF

25

28

ns

CD
......

20

23

ns

en
CD

C

-I

Receiver Enable to Receiver Output

N

CD

tPZL

High Z to 0, (Figure 4)

tpLZ

o to High Z, (Figure 4)

CL = 30 pF

20

23

ns

15

18

ns

AC Test Circuits and Switching Time Waveforms
Vee' 5V

r

Doun

r - - DIE
DOUT2
~

0- 0- 0-

0-

....-

iiiE

Doun

DIN1

DOUT4

DIN2

Roun
ROUTZ

DINJ

RDun
DIN4
RDun

~}
::: I"....,,·1
--0

PULSE

0'0
""

§}

-=

1

82
~2.6V

,,."

J",~ j.,,~r-

1

,

1.5V

1.5V

TL/F/5813-6

TL/F/5813-5

Input pulse:
tr = tf = 5 ns (10% to 90%)
Freq = 10 MHz (50% duly cycle)
Amplitude = 2.6V

~
TL/F/5813-4

FIGURE 1. Propagation Delay (DOUT to ROUT)
ZJV

veei5.0V

DOUTl
~ DIE

DOUT2

'"'-

[~

00-

1......,,·1 :
PULSE

iiiE

Doun

DIN1

DOUT4

DIN2

Roun

DIN]

§l 0'0
'"."

ROUTZ

~
~

Roun

f-o

Roun

~

OlN4

-=

1

JD
"NY-02.6V

-J1 . ~ J.." r~
,
1.5V

.,"

TLlF/5813-9

TL/F/5813-8

~
TL/F/5813-7

FIGURE 2. Propagation Delay (DIN to DOUT)

2-119

1.5V

Input pulse:
Ir = If = 5 ns (10% 1090%)
Freq = 10 MHz (50% duly cycle)
Amplitude = 2.6V

=:

:::E
co
N

to

U)

AC Test Circuits and Switching Time Waveforms
Vcc- IV

2.8V

(Continued)

IV

c
......
co

~
co

DOUT1
DIE

U)

iiiE

C
......

OlN1

:::E

Uk
DOUT2



.j:,.

Drivers!
Package

Logic Function
(Driver On)

Input
Compatibility
(Logic)

Output High
Voltage (V)

8
8

(Note 5)
(Note 6)

TTL
TTL

7

NANO

7

Output Low
Voltage (V)

Output Low
Current (rnA)

Propagation
Delay
Typ (ns)

On Power
Supply
Current (rnA)

Page
No.

30
30

0.5
0.5

100
100

40
40

152
125

3·5
3·5

TTL

50

1.6

350

5000

NANO

PMOS

50

1.6

350

5000

7

NANO

TTLICMOS

50

1.6

350

5000

7

NANO

CMOS/PMOS

50

1.6

350

5000

2
2
2
2

ANO
NANO
OR
NOR

CMOS
CMOS
CMOS
CMOS

56
56
56
56

40
40
40
40

1.4
1.4
1.4
1.4

300
300
300
300

150
150
150
150

8
8
8
8

3-12
3-12
3-12
3-12

OS3654
OS3656
OS3658
OS3668
OS3669

10
4
4
4
4

(Note 2)
NANO
NANO
NANO
ANO

(Note 2)
TTL/LS
TTL/LS
TTLILS
TTLILS

(Note 1)
65
70
70
70

45
30
35
(Note 7)
35

1.6
1.5
0.7
1.5
0.7

250
600
600
600
600

1000

70
65
65
80
65

3-17
3-21
3-23
3-26
3-29

OS3680

4

(Note 4)

TTL/CMOS

-2.1

-60

-60

-50

10,000

4.4

3-32

OS3686

2

NANO

TTL/CMOS

(Note 1)

56

1.3

300

1000

28

3-35

QOCto +7QoC

-55°C to + 125°C

OP8310
OP8311

OP7310
OP7311

OS2001C
JA.A9665C
OS2002C
JA.A9666C
OS2003C
JA.A9667C
OS2004C
JA.A9668C

OS2002M
JA.A9666M
OS2003M
JA.A9667M
OS2004M
JA.A9668M

OS3631
OS3632
OS3633
OS3634

OS1631
OS1632
OS1633
OS1634

Latch-Up
Voltage
(Note 3) (V)

2430
2000

3-65
3-65
3-65
3-65
3-65
3-65
3-65
3-65

OS1687

2

NANO

TTLICMOS

(Note 1)

-56

-1.3

300

1000

2.8

3-38

OS75450
OS75451
OS75452
OS75453
OS75454

OS55451
OS55452
OS55453
OS55454

2
2
2
2
2

ANO
ANO
NANO
OR
NOR

TTL
TTL
TTL
TTL
TTL

30
30
30
30
30

20
20
20
20
20

0.7
0.7
0.7
0.7
0.7

300
300
300
300
300

31
31
31
31
31

55
55
55
55
55

3-41
3-41
3-41
3-41
3-41

OS75461
OS75462
OS75463
OS75464

OS55461
OS55462
OS55463
OS55464

2
2
2
2

ANO
NANO
OR
NOR

TTL
TTL
TTL
TTL

35
35
35
35

30
30
30
30

0.7
0.7
0.7
0.7

300
300
300
300

33
33
33
33

55
55
55
55

3-57
3-57
3-57
3-57

2

ANO

CMOS

13.5

15

Vee - 1.8

300

150

0.015

CMOS
CMOS

OS3687

MM74C908,
MM74C918

I

Note 1: The 053686, 053687 and 053654 contain an internal inductive fly-back clamp circuit connected from the output to ground. As an example, OS3686 driving a relay solenoid connected to 28V would clamp the output voltage fly·
back transient at 56V caused by the solenoid's stored inductive current. This clamp protects the circuit output and quenches the fly-back.
Note 2: The 053654 is a 10-bit shift register followed by 10 enabled drivers. The input circuit is equivalent to a 4k resistor to ground, and the logic input thresholds are 2.8V and 0.8V. The recommended power supply voltage is 7.5V to
9.5V. The circuit can be cascaded to be a 20 or 30-bit shift register.
Note 3: Latch-up voltage is the maximum voltage the output can sustain when switching an inductive load.
Note 4: OS3680 has a differential input circuit.
Note 5: OS8310 inverting, positive edge latching.
Note 6: OS8311 inverting, fall through latch.
Note 7: OS3668 35V, latch-up with output fault protection.

- - - -

I

C

"tJ
........

~National

W
......
o
........

~ Semiconductor

C

"tJ
........

W
......
......

DP7310/DP8310/DP7311/DP8311 Octal Latched
Peripheral Drivers

........

C

"tJ
Q)

• All outputs simultaneously sink rated current "DC" with
no thermal derating at maximum rated temperature
• Parallel latching or buffering
• Separate active low enables for easy data bussing
• Internal "glitch free" power up clear

General Description
The DP731 0/831 0, DP7311 /8311 Octal Latched Peripheral
Drivers provide the function of latching eight bits of data
with open collector outputs, each driving up to 100 mA DC
with an operating voltage range of 30V. Both devices are
designed for low input currents, high input/output voltages,
and feature a power up clear (outputs off) function.

• 10% Vee tolerance

Applications

The DP7310/8310 are positive edge latching. Two active
low write/enable inputs are available for convenient data
bussing without external gating.

•
•
•
•
•
•
•
•
•

The DP7311 /8311 are positive edge latches. The active low
strobe input latches data or allows fall through operation
when held at logic "0". The latches are cleared (outputs off)
with a logic "0" on the clear pin.

Features
• High current, high voltage open collector outputs
• Low current, high voltage inputs

High current high voltage drivers
Relay drivers
Lamp drivers
LED drivers
TRIAC drivers
Solenoid drivers
Stepper motor drivers
Level translators
Fiber-optic LED drivers

Connection Diagrams
Dual-In-Line Package

Dual-In-Line Package

WEl

Vee

eLR

014

WE2

014

vee
STR

013

DiS

013

Dis

012

016

Dl2

016

011

017

Oil

017

001

018

001

Dl8

002

008

002

008

003

007

003

007

004

006

004

006

DDs

GNO

005

GNO

10

TL/F/5246-2

TL/F/5246-1

Top View

Top View
Order Number DP7310J, DP7311J,
DP8310J,DP8311J,DP8310N
or DP8311N
See NS Package Number J20A or N20A

3-5

W
......
o
........

C

"tJ

Q)

W

......

......

......

......
C")

a.
c
......
o
......
C")

Absolute Maximum Ratings (Note 1)

Operating Conditions

If Mllitaryl Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.

Supply Voltage (Vee)

Min
4.5

Max
5.5

Units
V

CO

Supply Voltage

7.0V

C

Input Voltage

35V

Temperature
DP7310/DP7311
DP8310/DP8311

-55
0

+125
+70

°C
°C

Output Voltage

35V

Input Voltage

30

V

Output Voltage

30

V

co

a.
......
......
......

C")

I"-

a.

c

......
o......
C")

I"-

a.

c

Maximum Power Dissipation· at 25°C
Cavity Package
DP8310/DP8311
Storage Temperature Range

1821 mW
2005 mW
- 65°C to + 150°C

Lead Temperature (Soldering, 4 sec.)
260°C
'Derate cavity package 12.1 mWrC above 25'C; derate molded package
16.0 mWrC above 25'C.

DC Electrical Characteristics
Symbol

Conditions

Parameter

VIH

Logical "1" Input Voltage

VIL

Logical "0" Input Voltage

VOL

Logical "0" Output Voltage
DP7310/DP7311
DP8310/DP8311

IOH

DP731 0/DP831 0, DP7311 IDP8311 (Notes 2 and 3)

Logical "1" Output Current
DP7310/DP7311
DP8310/DP8311

Min

Units
V

0.8

V

0.35

0.4
0.5

V
V

Data outputs latched to
logical "1", Vee = Min.
VOH = 25V
VOH = 30V

2.5

500
250

/-LA
/-LA

0.1

25

/-LA

1

250

/-LA

-215

-300

/-LA

-0.8

-1.5

V

100
100
88
88

125
152
117
125

mA
mA
mA
mA

40
40
25
25

47
57
34
36

mA
mA
mA
mA

Logical "1" Input Current

VIH

=

2.7V, Vee

=

Max

II

Input Current at Maximum Input
Voltage

VIN

=

30V, Vee

=

Max

= 0.4V, Vee =
= 12mA

IlL

Logical "0" Input Current

VIN

Vclamp

Input Clamp Voltage

liN

leeo

Supply Current, Outputs On

Data outputs latched to a
logical "0". All Inputs are
at logical "1", Vee = Max.

Max

DP7310
DP8310
DP7311
DP8311
Supply Current, Outputs Off

Max

Data outputs latched to
logical "0", Vee = Min.
IOL = 75 mA
IOL = 100 mA

IIH

leel

Typ

2.0

Data outputs latched to a
logic" 1 ". Other
conditions same as leeo.

DP7310
DP8310
DP7311
DP8311

3-6

AC Electrical Characteristics
Symbol

DP7310/DP8310: Vee

Parameter

= 4.5V, TA = -55°C to + 125°C

Conditions

tpdO

High to Low Propagation Delay
Write Enable Input to Output

(Figure 1)

tpd1

Low to High Propagation Delay
Write Enable Input to Output

(Figure 1)

tSETUP

Minimum Set-Up Time
Data in to Write Enable Input

tHOLD = 0 ns
(Figure 1)

tpWH'
tpWL

Minimum Write Enable Pulse
Width

(Figure 1)

Min

Typ

Max

Units

40

120

ns

70

150

ns

45

20

ns

60

25

ns

tTHL

High to Low Output Transition Time

(Figure 1)

16

35

tTLH

Low to High Output Transition Time

(Figure 1)

38

70

ns

CIN

ION" Package (Note 4)

5

15

pF

Typ

Max

Units

30

60

ns

AC Electrical Characteristics
Symbol

DP7311/DP8311: Vee

Parameter

ns

= 5V, TA = 25°C

Conditions

tpdO

High to Low Propagation Delay
Data In to Output

(Figure 2)

tpd1

Low to High Propagation Delay
Data to Output

(Figure 2)

tSETUP

Minimum Set-Up Time
Data in to Strobe Input

tpWL
tpdC

Min

70

100

ns

tHOLD = 0 ns
(Figure 2)

0

-25

ns

Minimum Strobe Enable Pulse Width

(Figure 2)

60

Propagation Delay Clear to Data Output

(Figure 2)

tpwc

Minimum Clear Input Pulse Width

(Figure 2)

tTHL

High to Low Output Transition Time

(Figure 2)

20

35

ns

tTLH

Low to High Output Transition Time

(Figure 2)

38

60

ns

CIN

Input Capacitance-Any Input

(Note 4)

5

15

pF

35
70

60

ns
135

25

ns
ns

1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minimax limits apply across the -SS'C to + 12S'C temperature range for the DP7310/DP7311 and across the O'C to + 70'C
for the DPB310/DPB311. All typical values are for TA = 2S'C, Vee = SV.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted.
Note 4: Input capacitance is guaranteed by periodic testing. fTEST = 10kHz at 300 mV, TA = 2S'C.
Note

3-7

•

,....
,....
C")

co
DC

......
o
,....
C")

CO

D-

C
......
,....

,....
C")
.....
D-

Logic Table
DP7310/DP8310
Write
Enable 1
WE1

Write
Enable 2
WE2

Data
Input
01 1-8

Data
Output

0
0
0

0

X

Q

...r
...r

0
1
0
1

1
0
1
0

X
X
X

Q

C
......
o
,....

...r
...r

C")

0
1
1

.....
DC

DP7311/DP8311

0
0
1
0
1

0°1-8

Data
Input
01 1-8

Data
Output

1
0
0

X

X

X

Q
1
0
1

Clear
CLR

Strobe
STR

1
1
1
0

0
1

X = Don't Care
1 = Outputs Off
o = Outputs On
Q = Pre-existing Output
...r = Positive Edge Transition

Q
Q

Block Diagrams
DP7310/DP8310
DATA IN 1
(0111

DATA IN 2
(012)

DATA IN 8
(Ola)

0------...----,
o--+-'--r--'-.,

..
..
..

..

o--4--.J--.r-.&...--'

DATA OUT 1
(001)

DATA OUT 2
(002)

DATA OUT 8
(008)

WRITE ENABLE 1
(WEl)

WRITE ENAID,U
(WE2)
TL/F/5246-3

=

DP7311/DP8311

DATA IDlII
IN 1 :

DATA IN 2
(0121

DATA IN 8
(018)

eM:~DATAOUT1
10011

O-_1~-4_--1-LA-!""'1

r:J:IOUT 2

LA~H

• •
··•
·
• ·•
o--+-'--r-----,

DATA OUT B
(0081

CLEAR
(Wi)

STROBE

(STR)

TLlF/5246-4

3-8

0°1-8

~------------------------------------------------------------------~c

"'C
......

Switching Time Waveforms

W
.....

o
.......
C

DP7310/DP8310

"'C

......

3V
DATA INPUT
OV

W
.....
.....
.......

3V

"'C

C

CO
W

.....

WE1 OR WEZ

OV

o
.......
C

-----:----'~I

"'C

V+ - - - . . . : . . - - , . .
OUTPUT

CO

w
.....

.....

VOL
TLlF/5246-5

DP7311/DP8311

3V
DATA INPUT
OV

3V
STR
OV

---+---+---'

3V---~----~------4--------~+_-------~
eLR
OV
V+
OUTPUT
VOL
TLlF/5246-6

Switching Time Test Circuits
5V

5V
V+ = 10V

V+ =10V

Vee

Vee

•

WE1·
OR

RL=100Q

\VEz

RL=100Q

DUT

J;

INPUT

CL=50pF

TL/F/5246-7
'WEI

=

OV When the Input

=

TLlF/5246-8

WE2

Pulse Generator Characteristics:
Zo = 50n,Ir = If = 5 ns

FIGURE 1. DP7310/DP8310

FIGURE 2. DP7311/DP8311

3-9

,...
,...
C")

co

D-

Typical Applications

C

......
o
,...

DP8310/11 Buffering High Current Device (Notes 1 and 2)

PNP High Current Driver

NPN High Current Driver
30V MAX.

V+

30V MAX

C")

CO

D-

C
......
,...

,...
C")

I"

D-

1 OF 8
OUTPUTS

1 OF 8
OUTPUTS

C

......
o,...

V-

C")

TLlF/5246-10

TL/F/5246-9

I"

D-

C

VMOS High Current Driver

Circuit Used to Reduce Peak
Transient Lamp Current

VG

VB =6.lV
RG

Rs = (
Rs =

Vs - VL)
-v;:RL

(-6.31--1) 180. = 95.4::::: loon

1 OF 8
OUTPUTS

TLlF/5246-11
TL/F/5246-12

Eight Output/Four Output Fiber Optic LED Driver
DP8311100 rnA Drivers

DP8311 Parallel Outputs (200 rnA) Drivers*

v+

V+

1 OF B
OUTPUTS

FALLTHROUGH

...... LED TO
...... LED TO

1 OF 4
OUTPUTS

FIBER OPTIC

MODE

FIBER OPTIC

FALLTHROUGH
MODE
TLlF/5246-13

• Parallel only adjacent outputs
TLlF/5246-14

3-10

c

Typical Applications

-C

......

(Continued)

a-Bit Level Translator-Driver
+5

V+

Vee

,-30V

--b

.......

c

-C
......

LOAD OR
OUTPUT PULL·UP

INPUT

1.4Vth

W
....
0

Digital Controlled 256 Level
Power Supply from 1.2V to 30V

•

\8 IN

8 OUT

OV

I·

YOUT

r~~~

........
.......
W

C

-C

-1---ov

0)

....

W

DP8311

0
.......

c

-C

0)

........
W

ill GND

TLlF/5246-15

"SETS VOUT

TL/F/5246-16

200 rnA Drive for a 4 Phase Bifilar Stepper Motor

Reading the State of the Latched Peripherals
y+

+VSTEPPER
30V MAX.

S

DATA BUS

Y

OP8l10

S
T
E
M
~1

'High Level Input
Voltage must not
Exceed Vee of the

AOORESS/CE

I70W

'Parallel only
adjacent outputs

DM81LS96

OM81LS96"
TRI·STATE
OCTAL
BUFFER

TLlF/5246-17

Gi

iii

TLlF/5246-18

Note 1: Always use good Vee bypass and ground techniques to suppress transients caused by peripheral loads.
Note 2: Printed circuit board mounting is required if these devices are operated at maximum rated temperature and current (all outputs on DC).

3-11

•

~

C")

CD

C")
en ~National

c
......
C")
C")

CD

C")

en
c
......
N

C")

D Semiconductor
OS1631/0S3631/0S1632/0S3632/0S1633/0536331
051634/053634 CM05 Dual Peripheral Drivers

CD

C")
en General Description
c...... The DS1631 series of dual peripheral drivers was designed
.,.. to be a universal set of interface components for CMOS
C")

CD

C")

en
c
......
~

C")

.,..
en
CD

c......
C")
C")

.,..
en
c......
CD

N

C")

dance OFF state with the same breakdown levels as when
Vee was applied .
Pin-outs are the same as the respective logic functions
found in the following popular series of circuits: DS75451,
DS75461. This feature allows direct conversion of present
systems to the MM74C CMOS family and DS1631 series
circuits with great power savings.
The DS1631 series is also TTL compatible at Vee = 5V.

circuits.
Each circuit has CMOS compatible inputs with thresholds
that track as a function of Vee (approximately % Vee). The
inputs are PNPs providing the high impedance necessary
for interfacing with CMOS.
Outputs have high voltage capability, minimum breakdown
voltage is 56V at 250 pA
The outputs are Darlington connected transistors. This allows high current operation (300 mA max) at low internal
Vee current levels since base drive for the output transistor
is obtained from the load in proportion to the required loading conditions. This is essential in order to minimize loading
on the CMOS logic supply.
Typical Vee = 5V power is 28 mW with both outputs ON.
Vee operating range is 4.5V to 15V.
The circuit also features output transistor protection if the
Vee supply is lost by forcing the output into the high impe-

Features
•
•
•
•
•

CMOS compatible inputs
High impedance inputs
PNP's
High output voltage breakdown
56V min
High output current capability
300 mA max
Same pin-outs and logic functions as DS75451 and
DS75461 series circuits
• Low Vee power dissipation (28 mW both outputs "ON"
at 5V)

.,..
en
c......
.,..
CD
.,..
en Connection Diagrams (Dual-In-Line and Metal Can Packages)
c
CD

C")

A2

Vee

X2

Vee

A2

TL/F/5816-1

Top View
Order Number DS1631J-B,
DS3631J-B or DS3631N
Vee

TL/F/5816-3

TL/F/5816-4

Top View
Top View
Order Number DS1633J-B,
Order Number DS1632J-B,
DS3632J-B or DS3632N
DS3633J-B or DS3633N
See NS Package Number JOBA or NOBE

Top View
Order Number DS1634J-B,
DS3634J-B or DS3634N

TL/F/5816-2

Vee

GND

GND

GND

GND

TLfF/5816-5

Vee

Vee

TL/F/5816-7

TL/F/5816-6

TL/F/5816-8

Top View

Top View

Top View

Top View

(Pin 4 is electrically connected to the
case.)

(Pin 4 is electrically connected to the
case.)

(Pin 4 is electrically connected to the
case.)

(Pin 4 is electrically connected to the
case.)

Order Number
DS1631H or DS3631H

Order Number
Order Number
DS1632H or DS3632H
DS1633H or DS3633H
See NS Package Number HOBe

3-12

Order Number
DS1634H or DS3634H

Absolute Maximum Ratings

Operating Conditions

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
5upply Voltage

5upply Voltage, Vee
051631/0516321
0516331051634

16V

Voltage at Inputs

- 65°C to + 150°C

4.5

15

V

4.75

15

V

N

........

C

en
.....

0)

Maximum Power Oissipation* at 25°C
Cavity Package
Molded Package
TO-5 Package

W
W

Temperature, T A
051631/0516321
0516331051634

1133mW
1022mW
787mW

Lead Temperature (50Idering, 4 sec.

260°C
053631/0536321
0536331053634

"Derate cavity package 7.6 mWI'C above 25'C; derate molded package
8.2 mWI'C above 25'C; derate TO·5 package 5.2 mWI'C above 25'C.

Electrical Characteristics
Parameter

Units

W

053631/0536321
0536331053634

56V

5torage Temperature Range

I

Max

-0.3V to Vee + 0.3V

Output Voltage

Symbol

Min

c
en
.....
0)
w
.....
........
c
en
.....
0)

-55

+ 125

°C

a

+70

°C

........

c
en
.....
0)

W
-'="
........

c
en
w

0)

(Notes 2 and 3)

I

I Min I Typ I Max IUnits

Conditions

ALL CIRCUITS

w
.....
........
c
en
w
0)

VIH

Logical "1" Input Voltage

(Figure 1)

Vee
Vee
Vee

VIL

Logical "0" Input Voltage

(Figure 1)

Vee
Vee
Vee

IIH

Logical "1" Input Current

IlL

Logical

"a" Input Current

VOH

Output Breakdown Voltage

VOL

Output Low Voltage

=
=
=
=
=
=

5V

3.5

2.5

V

W

10V

8.0

5

V

........
C

15V

12.5

7.5

V

5V

2.5

1.5

V

10V

5.5

2.0

V

15V

7.5

2.5

V

0.1

10

flA

-50

-120

flA

-200

-360

flA

= 15V, VIN = 15V, (Figure 2)
VIN = OAV, (Figure 3) Vee = 5V
Vee = 15V
Vee = 15V, 10H = 250 flA, (Figure 1)
Vee = Min, (Figure 1),
051631, 051632,
IOL = 100 mA
051633,051634
IOL = 300 mA
Vee = Min, (Figure 1),
053631, 053632,
10L = 100 mA
053633, 053634
10L = 300 mA
Vee

56

65

V

0.85

1.1

V

1.1

104

V

0.85

1.0

V

1.1

1.3

V

051631/053631
lee(o)

5upply Currents

VIN

=

OV, (Figure 4)

Vee
Vee

=
=
=
=

5V

Output Low

7

11

mA

15V

Both Orivers

14

20

mA

2

3

mA

7.5

10

mA

tpD1

Propagation to "1 "

Vee = 5V, TA
(FigureS)

=

25°C, CL

=

15 pF, RL

Output High
= 5V
= 15V Both Orivers
= 500., VL = 10V,

tpDo

Propagation to "0"

Vee = 5V, TA
(FigureS)

=

25°C, CL

=

15 pF, RL

=

=
=
=
=

= 5V
= 15V

(Figure 4)

lee(1)

Vee
Vee

5V, VIN

15V, VIN

50n, VL

=

10V,

500

ns

750

ns

051632/053632
lee(o)

5upply Currents

(Figure 4)

Vee
Vee

VIN

lee(1)

=

OV, (Figure 4)

Vee
Vee

8

12

mA

15V, VIN

18

23

mA

5V

2.5

3.5

mA

9

14

mA

5V, VIN

Output Low

Output High

15V

tpD1

Propagation to "1"

Vee = 5V, TA
(FigureS)

=

25°C, CL

=

15 pF, RL

=

500., VL

=

10V,

tpDo

Propagation to "0"

Vee = 5V, TA
(FigureS)

=

25°C, CL

=

15 pF, RL

=

500., VL

=

10V,

3-13

500

ns

750

ns

N

en
w

0)

w
w

........

c
en
w
0)

w

~

Electrical Characteristics (Notes 2 and 3) (Continued)
Symbol

I

I

Parameter

I

Conditions

Min

I

Typ

I

Max

I

Units

051633/0S3633
lec(o)

Supply Currents

VIN

=

OV, (Figure 4)

Output Low

Vee = SV
Vee = 1SV

(Figure 4)

leC(1)

Vee = SV, VIN = SV

Output High

Vee = 1SV, VIN = 1SV
tpD1

Propagation to "1"

Vee = SV, TA = 2SoC, CL = 1S pF, RL =

son, VL =

10V,

son, VL =

10V,

(Figure 5)
tpDO

Propagation to

"a"

Vee = SV, TA = 2SoC, CL = 1S pF, RL =

(Figure 5)

7.S

12

16

23

2

4

7.2

1S

rnA
rnA
rnA
rnA

sao

ns

7S0

ns

051634/0S3634
lec(o)

Supply Currents

(Figure 4)

Vee

=

SV, VIN = SV

Vee = 1SV, VIN
VIN

leC(1)

=

OV, (Figure 4)

Vee =

=

Output Low

1SV

sv

Output High

Vee = 1SV
tpD1

Propagation to "1"

2SoC, CL = 1S pF, RL =

son, VL =

10V,

Vee = SV, TA = 2SoC, CL = 1S pF, RL =

son, VL =

10V,

Vee = SV, TA

=

(Figure 5)
tpDO

Propagation to

"a"

(Figure 5)

7.S

12

18

23

3

S

11

18

rnA
rnA
rnA
rnA

sao

ns

7S0

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
thoy are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the -55'C to + 125'C temperature range for the 081631, 081632, 081633 and 081634 and
across the O'C to + 70'e range for the D83631, 083632, 083633 and 083634. All typical values are for TA = 25'e.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.

Test Circuits
Vcc

L~
VIH

0--

- ....

Vllo--

- I--A

SEE
TEST
TABLE

B

~
r

CIRCUIT
UNDER
TEST

- I---

Y
-

~J:d
SEE
TEST
__TABLE

---

VOH

~IOl

VOL

-==
Input
Circuit

Under

OS3632

OS3633

OS3634

Output
Other
Input

Apply

Measure

VIH

VIH

IOH

VOH

VIL

Vee

IOL

VOL

VIH

VIH

IOL

VOL

VIL

Vee

IOH

VOH

VIH

GNO

IOH

VOH

VIL

VIL

IOL

VOL

VIH

GNO

IOL

VOL

VIL

VIL

IOH

VOH

Test
OS3631

~~

~

Note: Each input is tested separately.
FIGURE 1. VIH, VIL, VOH, VOL

3-14

TL/F/5816-9

Test Circuits (Continued)

---

Vee

IIH

V1H

A. B

B.A

CIRCUIT
UNDER
TEST

Y

OPEN

TL/F/5816-10

Each input is tested separately.

FIGURE 2. I'H

i?~ I", JOPE~
.-1_-- 1

Vec

I".

Vee

~B.A

CIRCUIT
UNDER
TEST

y
OPEN

n.,..,rtA

I

VI-~B
I

I

I

L-----1-=

GND
TL/F/5816-12

Both gates are tested simultaneously.
TL/F/5816-11

FIGURE 4. ICC for AND and NAND Circuits

Note A: Each input is tested separately.
Note B: When testing D51633 and D51634 input not under test is grounded.
For ali other circuits it is at Vee.

FIGURE 3. I,L

Schematic Diagram

(Equivalent Circuit)
r---~~----------------~----~--~Vce

INPUT

I

LOGIC
AND LEVEL
TRANSLATION
ELEMENTS

I

L __ .J

1/2 of circuit shown

GND
TLlF/5816-15

3-15

~

('t)

CD

('t)

en
c

Switching Time Waveforms

'"
('t)
('t)

INPUT

5.0V

10V

,L,

CD

('t)

en
c

'"
N

OS3631,
OS3632

('t)

CD

Vcc = 5V

('t)

en
c

. .- ....- 0 OUTPUT
PULSE
GENERATOR
(NOTE 1)

,...
'"
('t)

x
CIRCUIT
UNOER
TEST

CD

('t)

en

c

'"

GNO

~

('t)

OS3633,
OS3634

,...
en
c
CD

! OV

'"
('t)
('t)

CD
,...
en
c

TLIF/SB16-13

'"
N
('t)

CD
,...

en
c

,...
'"
('t)

CD
,...
en
c

5.0V
INPUT
OS1631
OS1633

OV----~~~~------------------------~
~--------------

O.51's -----------I~

::; 5.0 ns

5.DV---I--l--I-----------------::::::':"\
INPUT
OS1632
OS1634

DV

VOH----------~~

900/0

OUTPUT

VOL-------+--~~----------------------------------II
1,
TLIF/SB16-14

Note 1: The pulse generator has the following characteristics: PRR = 500 kHz, ZOUT ::::: 50!}
Note 2: CL includes probe and jig capacitance

FIGURE 5. Switching Times

3-16

c

en
w
0')

~National

CJ'1

~ Semiconductor

~

053654 Printer Solenoid Driver
General Description
The 083654 is a serial-to-parallel 10-bit shift register with a
clock and data input, a data output from the tenth bit, and
10 open-collector clamped relay driver outputs suitable for
driving printer solenoids.
Timing for the circuit is shown in Figure 1. Data input is
sampled on the positive clock edge. Data output changes

on the negative clock edge, and is always active. Enable
transfers data from the shift register to the open-collector
outputs. Internal circuitry inhibits output enable for power
supply voltage less than 6V.
Each output sinks 250 mA and is internally clamped to
ground at 50V to dissipate energy stored in inductive loads.

Connection Diagram
Dual-In-Llne Package

Pin Descriptions
Pin No.

Function

1
2
3
4
5
6
7
S
9
10
11
12
13
14
15
16

Output Enable
Output 6
Output 7
OutputS
Output 9
Output 10
Data Output
Ground
Clock Input
Data Input
Output 1
Output 2
Output 3
Output 4
Output 5

OUTPUT ENABLE
OUTPUT 6
OUTPUT 7
OUTPUT 8
OUTPUT9
OUTPUT 10
DATA OUTPUT
GNO

TlIF/5817-1

Top View
Order Number DS3654J or DS3654N
See NS Package Number J16A or N16A

Vee

Logic Diagram
OUTPUTS
OUTPUT
ENABLE

1

DATA
INPUT

CLOCK
INPUT

16

Os-

Vcc
GND~

TlIF/5817-2

3-17

Absolute Maximum Ratings

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Maximum Power Dissipation· at 25°C
Cavity Package
Molded Package

Supply Voltage, VCC
Input Voltage

Lead Temperature (Soldering, 4 seconds)
260°C
"Derate cavity package 10.9 mW/"C above 25'C; derate molded package
13.5 mW I'C above 25'C.

9.5V Max
-0.5V Min. 9.5V Max

Output Supply, Vp-p

45V Max

Storage Temperature Range

- 65°C to + 150°C

Output Current (Single Output)

O.4A

Ground Current

4.0A

Peak Power Dissipation t
Duty Cycle < 5%

Operating Conditions
Min
7.5
0

Supply Voltage (Vce>
Temperature (TA)
Output Supply (Vp-p)

< 10 ms,
4.5W Max

Electrical Characteristics (Notes 2,3 and 4) Vp-p =
Parameter

Min

Typ

Max

2.6
0.8

Logical "1" Output Voltage Clamp

IClAMP

Logical "1" Output Current

VOH

= 0.1A, VEN = OV

45

50

= 40V, VEN = OV

= 250 mA, VEN = 2.6V

Logical "0" Output Current

IOl

Logical "1" Input Current
Clock
Enable
Data
Clock
Enable
Data

TA =
TA =
TA =
TA =
TA =
TA =

Logical "0" Input Current
Clock
Enable
Data

TA
TA
TA

Input Pull-Down Resistance
Clock
Enable
Data

TA = 25°C, VCl < Vce
TA = 25°C, VEN < VCC
TA = 25°C, Vo < Vce

70°C, VCl = 2.6V
70°C, VEN = 2.6V
70°C, Vo = 2.6V
O°C, VCl = 2.6V
O°C, VEN = 2.6V
O°C, Vo = 2.6V

0.2
0.2
0.3

= 70°C, VCl = 1V
= 70°C, VEN = 1V
= 70°C, Vo = 1V

TA 225°C, VEN
Vce = 9.5V
T A 225°C, VEN
Each Bit

Units
V
°C
V

Units

V

Logical "0" Input Voltage

Outputs Enabled

Max
9.5
+70
40

30V unless otherwise noted

Conditions

Logical "1" Input Voltage

Supply Current (Ice>
Outputs Disabled

1635 mW
1687 mW

0.33
0.33
0.57
0.33
0.33
0.57

V

65

V

1.0

mA

1.6

V

0.5
0.5
0.75

mA
mA
mA
mA
mA
mA

125
125
220

J-lA
J-lA
J-lA

8
8
4.5

k!1
k!1
k!1

= OV, VOO = OV,

27

40

mA

= 2.6V, IOl = 250 mA

55

70

mA

0.01

0.5

V

Data Output Low (VooL>

Vo

= OV, IOl = OV

Data Output High (VOOH)

Vo

= 2.6V, IOH = -0.75 mA

2.6

3.4

V

14
k!1
Vo = OV, Voo = 1V
1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified, min/max limits apply across the O'C to + 70'C temperature range and the 7.5V to 9.5V power supply range. All typical values
given are for Vce = 8.5V and TA = 25'C.
Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.
Note 4: Only one output at a time should be shorted.
Data Output Pull-Down Resistance

Note

3-18

c

Switching Characteristics O°C to + 70°C, TA =

en
w

25°C, nominal power supplies unless otherwise noted

0)

CJ1

Parameter

Conditions

Clk, Data and Enable Inputs

Min

Typ

Max

Units

2.0
2.0

11- 5

~

(Figure 1)

tFC
tAC
tCLK
tCLK
tHOLD
tSET-UP
tAE,tADIN
tFE, tFOIN

tBIT ~ 10 I1-s
2
3.5

1.0
1.0
1.0
5.0
Vp-p = 20V
RL = 100n, CL < 100 pF
RL = 100n, CL < 100 pF

Output 1-10
tAO
tFO
tpDEH
tpDEL

1.2
1.2
3.5
3.0

I1-s
I1-s
I1-s
11- 5

I1-s
11- 5

I1-s
11- 5

I1-S
I1-s
I1-s

Data Output
RL

tpDH, tpDL
tAD
tFO

= 5 kn, CL

~

10 pF

0.8
0.4
0.4

2.5

I1-s
I1-s
I1-s

Clock to Enable Delay
tCE

2 tBIT

I1-s

tBIT

11- 5

Enable to Clock Delay

Switching Time Waveforms
I-IECLK--OUTPUT
ENABLE

I-- IBITMIN---I---IBIT---j
CLOCK

n

1-2IBITMIN-1

~~

- - - - - - -......CLK 1

I

V CLOCK

DATA IN

I

_~~

OUTPUT
ENABLE

OUTPUT

---

•

c~~
.,,--1-- 'eLK

=><

IRCl,

><

~ ~IHOLD
ISET·UP

~-J

IFEN-t

'POEl1

-----L

IRD IFD

,..-I-PD-E-H-

N_
-11-

•

=

_

-l

IFO

IRO

CLOCK

DATA OUT

J\~i--IPDL

------+JCpo,
TLlF/5817-3

FIGURE 1. Shift Timing

3-19

~ r-------------------------------------------------------------------------------------~

Ln



~

~

~
:;:

-

r--r--.,..--,-..,....---r---,.-...--.

Q

a:

<
~

60

I

40

TA-

~25'C-

~

-~ ...
..------ ~-

-+-I
TA O"C'-

Q

I\.

a:

20

~
....

0

<

1\
-30

..-

z

1.0 1-+--+--1-\-1:--1-+--+--1

.1

T~_

80

"en

I-+-'-t-r\~-+-+--+-t--l

-20

VeE =3V
(NOTE 8)

~

r'\..

-10

100

~

VCC=5V
I-+-+-+---lf---I- VIL = 0.8V 3.0"
TA-25°C
(FIGURE 2)
2.0

~

-40

~

Ii;

HIGH·lEVEL OUTPUT CURRENT (mA)

10

20

40

70 100

200

400

COllECTOR CURRENT (mA)
TL/F/5824-35

TL/F/5824-34

FIGURE 17.0575450 Transistor Static Forward Current
Transfer Ratio vs Collector Current

FIGURE 16.0575450 TTL Gate High-Level Output
Voltage vs High-Level Output Current

3-49

"'I:t

Ll)

"'I:t

Ll)

r0-

Typical Performance Characteristics

(Continued)

t/)

C

......
C")

.

1.2

Ll)
Ll)

r0-

t/)

C

......

~

(NOTE 8)

'"~
>

i:

Ll)

r0-

t/)

C
......
orLl)

"'I:t

Ll)

r0-

0.8

= 0.6

N

"'I:t

Ll)

1=10

1.0

:iii
~

~

--

f-

Ie

- = 10

I.

0.5

(NOTE

TA=~7~C

rr
~ ~ TA= +25'~

8)

0.4
0.3

0.4

0.2

1--+-+--b.lo"6W1F!,---+--+--l

0.2

o

o
10

20

40

70 100

200

400

~~~-L~~~~~~

10

20

40

70 100

200

400

COLLECTOR CURRENT (mA)

COLLECTOR CURRENT (mA)

TL/F/5824-37

TL/F/5824-36

t/)

C
o

......

0.6

IIII
I
It~~~

Ie

"'I:t

FIGURE 18. OS75450 Transistor Base-Emitter
Voltage vs Collector Current

FIGURE 19. Transistor Collector-Emitter Saturation
Voltage vs Collector Current

Ll)

"'I:t

Ll)

r0-

Typical Applications

t/)

C

......
"'I:t

Ll)

"'I:t

A2o----......,
+5V
11

Ll)
Ll)

10
SUB

t/)

+V

C

......
C")
Ll)

"'I:t

v

OS75450

Ll)
Ll)

t/)

C
......
N

Ll)

GNO

"'I:t
Ll)
Ll)

t/)

C

......
or-

AlO----~

v = G+ Al

Ll)

. A2 + Ai

"'I:t

Ll)
Ll)

. A2

TLlF/5824-38

FIGURE 20. Gated Comparator

t/)

C
+5V
11

10
SUB

OS75450

+V

.....~.....-o

OUTPUT

INPUT G
INPUT A 0--+----'
TL/F/5824-39

FIGURE 21. 500 rnA Sink

3-50

Typical Applications

c
en
U1

(Continued)

U1
~

+ V l O - - - - - - - . . - -.......J\IV'Y-.....- - - - - - O OUT·Of·PHASE OUTPUT

U1
......
.......

c
en
U1

r - - -.......--o IN·PHASE OUTPUT
INPUT 0 - - - - - ,

U1

+5V

~

-V2

U1

I\)

.......

SUB

c
en
U1
U1
~

U1

(,)

.......

c
en
U1
U1
~

U1

STROBE

~

This side can perform the same or another function.

TL/F/SB24-40

FIGURE 22. Floating Switch

.......

c
en
......
U1
~

U1

5Vo-~~-------..---~------1~

2k

8.2k

820

0.II'F820

o
.......

B.2k

c

en
......
U1

r - - - + - - - f - - - - - - - 4 4 - - o OUTPUT Q
II

~

U1
......

10

.......

c

en
......
U1

~

DS75450

U1

I\)

.......

c

en
......

eND

U1
~

U1

'---+---------+--+--oOUTPUT ii

(,)

.......

c
en
......

TL/F/5B24-41

FIGURE 23. Square-Wave Generator

U1
~

U1

~

+Vlo-......- - - - - - - _ - -......---.

+5V

r---------,
DIODE ARRAY

I
I
I
I
I

J

I SOURCE

• CURRENT
STROBE

TO MEMORY DRIVE LINES

'----+-----.()-V2

Source and sink controls are activated by
high-level input voltages (VIH ~ 2V).
TL/F/5B24-42

FIGURE 24. Core Memory Driver

3-51

•

~ r---------------------------------------------------------------------------------------~
II)
~

II)

r-..

Typical Applications

en
c

(Continued)

+5Vo----1~------------------------------~--~

lN759

"C")
II)

_--I--....--4--
<0

en
en

DS2001/~A9665/DS2002/~A9666
DS2003/~A9667/DS2004/~A9668

U1
.......

c

rn
N

High Current/Voltage Darlington Drivers

o
o

N

.......
1=

General Description
The OS2001 1 /LA9665/0S20021 /LA9666/0S20031 /LA9667
OS20041/LA9668 are comprised of seven high voltage, high
current NPN Darlington transistor pairs. All units feature
common emitter, open collector outputs. To maximize their
effectiveness, these units contain suppression diodes for
inductive loads and appropriate emitter base resistors for
leakage.
The OS2001 I/LA9665 is a general purpose array which may
be used with OTL, TTL, PMOS, CMOS, etc. Input current
limiting is done by connecting an appropriate discrete resistor to each input.
The OS20021/LA9666 version does away with the need for
any external discrete resistors, since each unit has a resistor and a Zener diode in series with the input. The OS20021
/LA9666 was specifically designed for direct interface from
PMOS logic (operating at supply voltages from 14V to 25V)
to solenoids or relays.
The OS2003//LA9667 has a series base resistor to each
Darlington pair, thus allowing operation directly with TIL or
CMOS operating at supply voltages of 5.0V.

l>
<0

The OS20041/LA9668 has an appropriate input resistor to
allow direct operation from CMOS or PMOS outputs operating from supply voltages of 6.0V to 15V.

en
en
en
.......

The OS2001 1 /LA9665/0S20021 /LA9666/0S20031 /LA9667
OS20041/LA9668 offer solutions to a great many interface
needs, including solenoids, relays, lamps, small motors, and
LEOs. Applications requiring sink currents beyond the capability of a single output may be accommodated by paralleling the outputs.

rn
N

o

o
w
.......

1=

l>
<0

en
en

Features
•
a
•
•
•
•

c

Seven high gain Darlington pairs
High output voltage (VCE = 50V)
High output current (Ic = 350 mA)
OTL, TIL, PMOS, CMOS compatible
Suppression diodes for inductive loads
Extended temperature range

........
.......

c

rn
N

o
o

00l::Io

.......
1=

l>
<0

en
en
Q)

Connection Diagram
16-Lead DIP

IN A
IN 8
IN C
IN 0
IN E
IN

r

IN G
GND

1

16

2

15

3

14

4

13

5

12

6

11

7

10

8

9

-=

OUT A
OUT 8

II

OUT C
OUT 0
OUT E
OUT

r

OUT G
COMMON
TL/F/9647-1

Top View
Order Number DS2001CN, /LA9665PC, DS2002CN, /LA9666PC,
DS2003CN, /LA9667PC or DS2004CN, /LA9668PC
See NS Package Number N16A
Order Number DS2001CJ, /LA9665DC, DS2002CJ, DS2002MJ, /LA9666DC,
/LA9666DM, DS2003CJ, DS2003MJ, /LA9667DC, /LA9667DM or DS2004CJ, DS2004MJ, /LA9668DC, /LA9668DM
See NS Package Number J16A

3-65

co

CD
CD

en



'/

SATURATION VOLTAGE - V

~~

I-

1 /

o
o

l>

0)
0)

1.5

I

/ /

1.5

lD

t.tAX/

"" /

\I

~

2.0

I

TYPICAL,

......
......

l>

CD

0)
0)
0)

,.

16

18

20

22

2.

26

INPUT VOLTAGE - V

INPUT CURRENT - p.A

TlIF/9647-6

OS20031 J-LA9667
Input Current vs
Input Voltage
2.5

.,

I

OS20041 J-LA966B
Input Current vs
Input Voltage

,

~

2.0

I

~a

IAAX/lYP,

I-

1.5

a

lD

~

~

.,

/

/

V,

~

,

~

~
a
~

I

/.,
,

0.5

IAAX
lD

",

o4D

SD

6D

7D

aD

v

... ...

0.5

o

o
2.0 3.0

1.5

"V

I

I'

SD 6D

9D

INPUT VOLTAGE - V

",

V

.... ......
TYP

Peak Collector Current vs
Duty Cycle and Number of
Outputs (Molded Package)

~

400 r--'rrr-r---r--r---r;---r--r-.....

~r_+-~~~~~+--r~

~

..... ...

aD

11

10

12

~_

~

l>
CD

0)
0)

.....
......
c
en
N
~

l>

CD

100

L....--'----'---I---'-_'---'---'--'

20

040

60
DUTY CYCLE -

INPUT VOLTAGE - V

o

o

CN
......

o

~ 200

9D

c
en
N

o
0l:Io
......

8

~

7D

......

80

100

0)
0)
Q)

r.
TlIF/9647-16

Peak Collector Current vs
Duty Cycle and Number of
Outputs (Ceramic Package)

~

~

300

1----1i-\-1~Hr-H.:-_t_-l

8

~
:il

200

~

g

~ 100

L....::.._ _ _.l...-_.J.30...~..L.;;:!~

o

040

60

80

100

DUTY CYCLE - %
TLlF/9647-19

3·67

Ell

ClO

CD
CD

CD

«:i.

Equivalent Circuits

......

COMMON

052001/},A9665

"I:t

o

N

OUT

2.7k.o.
IN

IN

(/)

C
......
......

COMMON

052003/}'A9667

OUT

o

CD
CD

CD

«:i.

7.2k.o.

3.0k.o.

......
C")
o

o

TL/F/9647-2

C

COMMON

N
(/)

......
CD
CD
CD

CD

«:i.
......
N
o
o

N

(/)

C

......
II)
CD
CD

CD

«:i.

......
,....
o
o
N

(/)

C

DS2004/}'A966B

OUT

IN

10.5k.o.
IN

TL/F/9647-3

COMMON
OUT

C

en
I\,)

Typical Applications

o

PMOS to Load

o
...I,
.......

Buffer for Higher Current Loads

"l:

l=eD

en
en
U1
.......

16

l

PIoIOS
OUTPUT

OS2002/
}L49666

OS2003/
}L49667

15

c

14

o

en
I\,)

oI\,)
.......

13

"l:

12

l=-

11
7

10

eD

en
en
en
.......

10

8

c

en
I\,)
o

o

w
.......

TL/F/9647-15

"l:

l=-

eD

en
en

TLlF/9647-16

c'"

.......

en
I\,)

m

o
o

to Load
V,

~

.......
"l:

16

l=-

eD

en
en
(X)
OS200'(/
~A9668

TL/F/9647-17

3-69

•

~ r-------------------------------------------------------------------------------------~

.....

National Semiconductor
Application Note 213
Bill Fowler

N

Safe Operating Areas for
Z
c:(
Peripheral Drivers

Peripheral Drivers is a broad definition given to Interface
Power devices. The devices generally have open-collector
output transistors that can switch hundreds of milliamps at
high voltage, and are driven by standard Digital Logic gates.
They serve many applications such as: Relay Drivers, Printer Hammer Drivers, Lamp Drivers, Bus Drivers, Core Memory Drivers, Voltage Level Transistors, and etc. Most IC devices have a specified maximum load such as one TTL gate
can drive ten other TTL gates. Peripheral drivers have many
varied load situations depending on the application, and requires the design engineer to interpret the limitations of the
device vs its application. The major considerations are Peak
Current, Breakdown Voltage, and Power Dissipation.

times measured in an Inductive Latch-Up Test). Observe
that all breakdown voltages converge on LVCEO at high
currents, and that destructive secondary breakdown voltage
occurred (shown as dotted line) at high currents and high
voltage corresponding to exceeding the power dissipation
of the device. The characteristics of secondary breakdown
voltage vary with the length of time the condition exists,
device temperature, voltage, and current.
Ie

OUTPUT CURRENT AND VOLTAGE CHARACTERISTICS
Figure 1 shows the circuit of a typical peripheral driver, the
0575451. The circuit is equivalent to a TTL gate driving a
300 mA output transistor. Figure 2 shows the characteristics
of the output transistor when it is ON and when it is OFF.
The output transistor is capable of sinking more than one
amp of current when it is ON, and is specified at a VOL =
O.7V at 300 mAo The output transistor is also specified to
operate with voltages up to 30V without breaking down, but
there is more to that as shown by the breakdown voltages
labeled BVCE5, BVCER, and LVCEO.

Vee

OUTPUT ON

300mA

vee vee
~------------------~--~~-----VeE

TL/F/5860-2

FIGURE 2. Output Characterlstlc~ ON and OFF
OUTPUT TRANSFER CHARACTERISTICS VS
INDUCTIVE AND CAPACITIVE LOADS

INPUT A
INPUT B0--+-_

TLIF/5860-1

FIGURE 1. Typical Peripheral Driver DS75451
BVCES corresponds to the breakdown voltage when the
output transistor is held off by the lower output transistor of
the TTL gate, as would happen if the power supply (Vee>
was 5V. BVCER corresponds to the breakdown voltage
when the output transistor is held off by the 500 resistor, as
would happen if the power supply (Vee> was off (OV).
LVCEO corresponds to the breakdown voltage of the output
transistor if it could be measured with the base open.
LVCEO can be measured by exceeding the breakdown voltage BVCE5 and measuring the voltage at output currents of
1 to 10 mA on a transistor curve tracer (LVCEO is some-

Figure 3 shows the switching transfer characteristics superimposed on the DC characteristics of the output transistor
for an inductive load. Figure 4 shows the switching transfer
characteristics for a capacitor load. In both cases in these
examples, the load voltage (VB) exceeds LVCEO. When the
output transistor turns on with an inductive load the initial
current through the load is 0 mA, and the transfer curve
switches across to the left (VoL> and slowly charges the
inductor. When the output transistor turns off with an inductive load, the initial current is IOL' which is sustained by the
inductor and the transistor curve switches across to the
right (VB) through a high current and high voltage area
which exceeds LVCEO and instead of turning off (shown as
dotted line) the device goes into secondary breakdown. It is
generally not a good practice to let the output transistor's
voltage exceed LVCEO with an inductive load.

In a similar case with a capacitive load shown in Figure 4,
the switching transfer characteristics rotate counter-clockwise through the DC characteristics, unlike the inductive
load which rotated clockwise. Even though the switching
transfer curve exceeds LVCEO, it didn't go into secondary
breakdown. Therefore, it is an acceptable practice to let the
output transistor voltage exceed LVCEO, but not exceed
BVCER with a capacitive load.

3-70

.

l>

Figure 6 shows the switching transfer characteristics of a
capacitive load which leads to secondary breakdown. This
condition occurs due to high sustained currents, not break·
down voltage. In this example, the large capacitor prevent·
ed the output transistor from switching fast enough through
the high current and high voltage region; in turn the power
dissipation of the device was exceeded and the output tran·
sistor went into secondary breakdown.

Ie
Va

z
I\)
.....
w

Ie
IOL

TL/F/5860-3

FIGURE 3. Inductive Load Transfer Characteristics
Ie

Va

"--'::~---""'--,-L.---~--VCE
Va

TLlF/5860-6

FIGURE 6. Capacitive Load Transfer Characteristics

Figure 7 shows another method of quenching the inductive
voltage spike caused by the initial inductive current. This
method dampens the switching response by the addition of
Ro and Co. The values of Ro and CD are chosen to critically
dampen the values of RL and LL; this will limit the output
voltage to 2 X VB.
LL

(RL
Va

+ RO)O

X

~

1
LL CD

~ 0.5

Va

TLlF/5860-4

FIGURE 4. Capacitive Load Transfer Characteristics

Figure 5 shows an acceptable application with an inductive
load. The load voltage (VB) is less than LVCEO, and the
inductive voltage spike caused by the initial inductive cur·
rent is quenched by a diode connected to VB.

•

Ie

TL/F/5860-7

FIGURE 7. Inductive Load Dampened by Capacitor

Figure 8 shows a method of reducing high sustaining cur·
rents in a capacitive load. Ro in series with the capacitor
(Cd will limit the switching transistor without affecting final
amplitude of the output voltage, since the IR drop across Ro
will be zero after the capacitor is charged.
As an additional warning, beware of parasitic reactance. If
the driver's load is located some distance from the driver
(as an example: on the inclosure panel or through a con·
TLlF/5860-5

FIGURE 5. Inductive Load Transfer Characteristics
Clamped by Diode
3-71

necting cable) there will be additional inductance and capacitance which may cause ringing on the driver output
which will exceed LVCEO or transient current that exceeds
the sustaining current of the driver. A 300 mA current
through a small inductor can cause a good size transient
voltage, as compared with 20 mA transient current observed with TTL gates. For no other reason than to reduce
the noise associated with these transients, it is good practice to dampen the driver's output.

device, and the power on the output of the device due to the
Driver Load.
POWER LIMITATIONS OF PACKAGE
Figure 9 shows the equivalent circuit of a typical power device in its application. Power is shown equivalent to electrical current, thermal resistance is shown equivalent to electrical resistance, the electrical reactance C and L are equivalent to the capacity to store heat, and the propagation delay through the medium. There are two mediums of heat
transfer: conduction through mass and radiant convection.
Convection is insignificant compared with conduction and
isn't shown in the thermal resistance circuits. From the point
power is generated (device junction) there are three possible paths to the ultimate heat sink: 1) through the device
leads; 2) through the device surface by mechanical connection; and 3) through the device surface to ambient air. In all
cases, the thermal paths are like delay lines and have a
corresponding propagation delay. The thermal resistance is
proportional to the length divided by the cross sectional
area of the material. The Thermal Inductance is proportional
to the length of the material (copper, molding compound,
etc.) and inversely proportional to the cross sectional area.
The thermal capacity is proportional to the volume of the
material.

In conclusion, transient voltage associated with inductive
loads can damage the peripheral driver, and transient currents associated with capacitive loads can also damage the
driver. In some instances the device may not exhibit failure
with the first switching cycle, but its conditions from ON to
OFF will worsen after many cycles. In some cases the device will recover after the power has been turned off, but its
long term reliability may have been degraded.
POWER DISSIPATION
Power Dissipation is limited by the IC Package Thermal
Reactance and the external thermal reactance of the environment (PC board, heat sink, circulating air, etc.). Also, the
power dissipation is limited by the maximum allowable junction temperature of the device. There are two contributions
to the power: the internal bias currents and voltage of the

TLlF/5860-8

FIGURE 8. Capacitive Load with Current Limiting Resistor

TJUNCTION

TL/F/5860-9

FIGURE 9. Thermal Reactance from Junction to Ambient

3-72

»

z

Device Package

I

1.4
DIE SIZE. 6000 MIL

N
--.

2

W

1.2

~

DIE
PAD

z
0
i=

[:::~~~~~~J

~

0.8

C

0.6

~

0.4

i:i
a:

~

0.2
DEVICE
PIN

0
25

TL/F/5860-10

1.8

1.6

z
i=
~

1.4

C

a:

0.8

~

0.4

1.2

~

~

0.6

0
50

75

100

125

150

125

150

Another variance in thermal resistance is the size of the IC
die. If the contact area to the lead frame is greater, then the
thermal resistance from the Die to the Lead Frame is reduced. This is shown in Figure 13. The thermal resistance
shown in Figure 11 corresponds to die that are 6000 mil2 in
area.

0.2
25

10D

TL/F/5860-12

2.0

c

75

FIGURE 12. Maximum Package Rating Copper vs
Kovar Lead Frame Packages
Figure 11 shows that 14 pin packages have less thermal
resistance than 8 pin packages; which should be expected
since it has more pins to conduct heat and has more surface area. Something that may not be expected is that the
Thermal Resistance of the molded devices is comparable to
the ceramic devices. The reason for the lower thermal resistance of the molded devices is the Copper lead frame,
which is a better thermal conductor than the Kovar lead
frame of the ceramic package. Almost all the peripheral
drivers made by National Semiconductor are constructed
with Copper lead frames (refer to 

0.2

:z::
....
w

~
a:

o

o

500

100

1k

{EAK POWER (WATIS)

AIR FLOW (LINEAR FEETIMIN)
TLIF/S660-14

FIGURE 14. Thermal Resistance vs Air Velocity
The thermal resistance can also be improved by connecting
the package to the PC board copper or by attaching metal
wings to the package. The improvement by these means is
outside the control of the IC manufacturer, but is available
from the manufacturer of the heat sink device. If the IC is
mounted in a socket rather than soldered to a PC board, the
thermal resistance through the device leads will worsen. In
most cases, the thermal resistance is increased by 20%;
again this is a variable subject to the specific socket type.

EINEIR~11 (J~UILfft 1°-~)

-r-

-i7 it

III II I 1111 I I
r-I II I IIII I I

0.01
1

10

100

1k

10k

(APPLIED TIME I/Is)
TL/F/S660-1S

The maximum package rating shown in this note corresponds to a 90% confidence level that the package will
have thermal resistance equal to or less than the value
shown. The thermal resistance varies ± 5% about the mean
due to variables in assembly and package material.

FIGURE 15. Peak Power and Energy vs the
Period of Time the Power was Applied
To calculate power dissipation, the only information avail. able to the design engineer is the parametric limits in the
device data sheet, and the same information about the load
reactance. If the calculations indicate the device is within its
limits of power dissipation, then using those parametric limits is satisfactory. If the calculation of power dissipation is
marginal, the parametric limits used in the calculations
might be worst case at low temperature instead of high temperature due to a positive temperature coefficient (Tc> of
resistance. IC resistors and resistors associated with the
load generally have a positive Tc. On the other hand, diodes
and transistor emitter base voltages have a negative T c;
which may in some circuits negate the effect of the resistors
T c. Peripheral output transistors have a positive Tc associated with VOL; while output Darlington transistors have a
negative Teat low currents and may be flat at high currents.
Figure 16 shows an example of power dissipation vs temperature; note that the power dissipation at the application's
maximum temperature (TA) was less than the power dissipation at lower temperatures. Since maximum junction temperature is the concern of the calculation, then maximum
ambient temperature power should be used. The junction
temperature may be determined by projecting a line (shown
dotted in Figure 16), with a slope proportional to 

late Icc vs temperature is to measure a device, then normalize the measurements vs the typical value for Icc in the data
sheet, then worst case the measurements by adding 30%.
Thirty percent is normally the worst-case resistor tolerance
that IC devices are manufactured to.

Refer to Figure 18 voltage and current waveforms corresponding to the power dissipation calculated for this example of an inductive load.
PON = Average power dissipation in device output
when device is ON during total period (T)
T

~
2-

1.2

=

LL
RL

=~=

41.7 ms

1200

VB - VOL
30 - 1.5
75 A
= - - - = 23 . m
RL
120
Ip = IL (1 - e -TON/T)
IL =

z

0

i=

~

0.'

~
Q
a:

0.6

~

0.4

Ip = 237.5 mA (1 - e- 100 ms/41.7 ms)
Ip = 215.9 mA

0.2
50

75

100

TEMPERATURE

125

tlT dt]
fTON e--

TON [
PON = VOL X IL X 1T

150

rei

TON

0

PON = VOL X IL X -TON [ 1 - - T (1 - e -TON/T]
)
T
TON

TL/F/5860-16

FIGURE 1S.IC Power Dissipation vs Temperature
PON = 1.5x237.5 mAX

CALCULATION OF OUTPUT POWER WITH
AN INDUCTIVE LOAD

100 [
41.7
]
1- 100 (1-e-100/41.7)
200

PON = 110.6 mW

For this example, the device output circuit is similar to the
DS3654 (10-Bit Printer Solenoid Driver) and the DS3686
and DS3687 (Telephone Relay Driver) as shown in Figure
17. Special features of the circuit type are the Darlington
output transistors 01 and 02 and the zener diode from the
collector of 02 to the base of 02. The Darlington output
requires very little drive from the logic gate driving it and in
turn dissipates less power when the output is turned ON and
OFF, than a single saturating transistor output would. The
zener diode (Dz) quenches the inductive backswing when
the output is turned OFF.
Device and Load Characteristics Used for
Power Calculation
Output Voltage ON
1.5V
VOL
65V
Output Clamp Voltage
Vc
Load Voltage
30V
VB
Load Resistance
1200
RL
Load Inductance
5h
LL
Period ON
100 ms
TON
Period OFF
100ms
TOFF
T
Total Period
200ms

POFF = Average power dissipation in device output when
device is OFF during total period (T)
Vc - VB
65 - 30
IR = - - - = - - - = 291.7mA
RL
1200
Ip + IR)
tx = Tin ( --IRtx = 41.7 ms in (
POFF = Vc X

215.9 + 291.7)
291.7

=

23.1 ms

tx [
ftxe-tlTdt]
- IR
T
(Ip + iR)
- - t0

x

POFF = Vc X -tx [ (Ip
T

+

IR) X s -T (1 - e -t
tx

23.1 [
POFF = 65 X 200 (215.9 mA

X/ T

) - IR ]
41.7

+ 291.7 mA) 23.1

(1 - e-23.1/41.7) - 291.7 mA]
POFF = 736 mW
Po = Average power dissipation in device output
Po = PON

Va

+

POFF = 110.6

+

736 = 846.6 mW

In the above example, driving a 1200 inductive load at 5 Hz,
the power dissipation exceeded a more simple calculation
of power dissipation, which would have been:
PO=

VOL (VB - VoL>
RL

TON

X-

T

P = 1.5 (30 - 1.5) X 100 ms = 182.5 mW
120
200 ms
o
An error 460% would have occurred by not including the
reactive load. The total power dissipation must also include
other outputs (if the device has more than one output), and
the power dissipation due to the device power supply currents. This is an example where the load will most likely
exceed the device package rating. If the load is fixed, the
power can be reduced by changing the period (T) and duty
rate (TONtTOFF).

':"

':"

TL/F/5860-17

FIGURE 17. Peripheral Driver with Inductive Load
3-75

z
I\)
.....
w

.

,...

~

r----------------------------------------------------------------------------------------------,

N

~5Y--------------P_~

Z

cs:

50

l/

w

'"
~

en
::E
::c

o

>

~

~

E!.

-30Y-

w
u

z0(
Ii;
~

::I

o

__________~--~__~
100 ms
200 ms

1!Y~====~==~==L_

a

o I

I

a

o

\

\

,,

,I
~~~~~~~~~~~

o

1

2

3

4

5

6

7

8 9 10

LAMP VOLTAGE (V)
TL/F/5860-20

FIGURE 20. DC Characteristics of an Incandescent
Lamp
Figure 21 shows the transient response of a driver similar to
a D575451 driving the lamp characterized in Figures 19 and
20. The equivalent load doesn't include the reactance of the
lamp base to ambient, which has a 250 ms time constant,
since 10 ms to an IC is equivalent to DC. The peak transient
current was 1 amp, settling to 200 ms, with an 8 ms time
constant. Observe the peak current is clamped at 1 amp, by
the sinking ability of the driver; otherwise the peak current
may have been 1.2 amps. The 0575451 is only rated at 300
mA, but it is reasonable to assume it could sink 1 amp because of the designed force (3 required for switching response and worst case operating temperature.

200ms

\

l/~

/

20
10

~\--~I

100ms

V

~"

,/

30

a:

/

:~n

40

"-

"
IR--------------------------------TL/F/5860-18

FIGURE 18. Voltage and Current Waveforms
Corresponding to Inductive Load
CALCULATION OF OUTPUT POWER
WITH AN INCANDESCENT LAMP

1

An incandescent lamp is equivalent to a reactive load. The
reactance is related to the period of time required to heat
the lamp and the filaments positive temperature coefficient
of resistance. Figure 19 shows the transient response for a
typical lamp used on instrument panels, and the equivalent
electrical model for the lamp. Much like IC packages the
lamp has a thermal circuit and its associated propagation
delay. This lamp filament has an 8 ms time constant, and a
longer 250 ms time constant from the lamp body to ambient.
The DC characteristics are shown in Figure 20. Note the
knee in the characteristics at 2 volts; this is where power
starts to be dissipated in the form of light. This subject is
important, since more peripheral drivers are damaged by
lamps than any other load.

0.6
en

:E

S-

0.6

fZ

w
a:
a:

0.4

~~M
~~

~~22 /IF

0.2

~

f

;::)

u

7.13

1=8 ms

0-

o

10

20

3D

40

50

TIME (msl
TL/F/5860-21

en

30

::E

20

Ii;

~

a:

~

--

Calculation of the energy dissipated by a peripheral driver
for the transient lamp current shown in Figure 21 is shown
above, and the plot of energy vs time is shown in Figure 22.
Figure 22 also includes as a reference the maximum peak
energy from Figure 15. It can be seen from Figure 22 that in
this example there is a good safety margin between the
lamp load and the reference max peak energy. If there were
more drivers than one per package under the same load,
the margin would have been reduced. Also, if the peripheral
driver couldn't saturate because it COUldn't sink the peak
transient lamp current, then the energy would also reduce
the margin of safe operation.

/1'"'

::c

E!.
~
z
0(

....- ~

FIGURE 21. Transient Incandescent Lamp Current

10

t: J.l-"
3B

2100/lF

T

T

1122/lF

o ~~~~----------~~
o 10 20 30 40 50 60 70 80 90 100
TIME (ms)
TL/F/5860-19

FIGURE 19. Transient Response of
an Incandescent Lamp

3-76

100

'7;

VB = 6.JV

J II
I
r=IPE~k'~NiRd~

10

1=

><

en

w
.....

~

REFERENCE
~

~

::::I

0

::!

INCANDESCENT
LAMP LOAD

>
c:J

ffi
15

RB RS
100

0.1
~

0.01
10

100

1k

10k

100k

TLIF/5860-23

FIGURE 23. Circuit Used to Reduce Peak
Transient Lamp Current

TIME (PSI
TL/F/5860-22

FIGURE 22. Energy vs Time for a Peripheral
Driver with an Incandescent Lamp Load

PERIPHERAL DRIVER SECTION
National 5emiconductor has a wide selection of peripheral
drivers as shown in this section's guide. The 0575451,
0575461, 053631 and the 053611 series have the same
selection of logic function in an 8-pin package. The
0575461 is a high voltage selection of the 0575451 and
may switch slower. The 053611 and 053631 are very high
voltage circuits and were intended for slow relay applications. The 053680, 053686, and 053687 were intended for
56V telephone relay applications. The D53654 contains a
1O-bit shift register followed by ten 250 rnA clamped drivers.
The D53654 was intended for printer solenoid applications.

CALCULATION OF ENERGY IN AN
INCANDESCENT LAMP
Energy =
.
'R1

=

J:

+ IA2) dt

VOL (IA1

VB - VOL
R1

=

i
= (VB - VOL)
R2
R2

=
Energy =

IA2 e- tlT

J:

T

VOL (IA1

= VOL [lA1t

Given:

+

IA1

e- tlT
=

R2C2

High current and high voltage peripheral drivers find many
applications associated with digital systems, and it is the
intention of the application note to insure that reliability and
service life of peripheral drivers equal or exceed the performance of the other logic gates made by National.

+ IA2 e- tlT ) dt
IA2T (i -

e- tlT )]

VOL = 0.6V
IR1 = 0.2 Amps
IA1

+

(6.3 1-1) 18n = 95.4 ::::: loon

= --

IA2 = 1 Amp

A common technique used to reduce the 10 to 1 peak to DC
transient lamp current is to bias the lamp partially ON, so
the lamp filament is warm. This can be accomplished as
shown in Figure 23. From Figure 20 it can be seen that the
lamp resistance at OV is 5.70, but at 1V the resistance is
180. At 1V the lamp dosen't start to emit light. Using a lamp
resistance of 1000 and lamp voltage of 1V, RB was calculated to be approximately 1000. This circuit will reduce the
peak lamp current from 1 amp to 316 rnA.

For additional information, please contact the Interface Marketing Department at National or one of the many field application engineers world-wide.

3-77

Section 4
Display Drivers

Section 4 Contents
Display Drivers-Introduction ........................................................
Display Drivers-Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75491 MOS-to-LED Quad Segment Driver..........................................
DS75492 MOS-to-LED Hex Digit Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS55493/DS75493 Quad LED Segment Driver ........................................
DS55494/DS75494 Hex Digit Driver......................... .........................
DS8654 8-0utput Display Driver (LED, VF, Thermal Printer) . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .
DS8669 2-Digit BCD to 7-Segment Decoder/Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8863/DS8963 MOS-to-LED 8-Digit Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8870 Hex LED Digit Driver ........................................................
DS8874 9-Digit Shift Input LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7880/DS8880 High Voltage 7-Segment Decoder/Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8881 Vacuum Fluorescent Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8884A High Voltage Cathode Decoder/Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8973 9-Digit LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-84 Driving 7-Segment Gas Discharge Display Tubes with National Semiconductor Drivers
MM5450/MM5451 LED Display Drivers ...............................................
MM5452/MM5453 Liquid Crystal Display Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5480 LED Display Driver.................................. .......................
MM5481 LED Display Driver............ ............................. ...... ..........
MM5483 Liquid Crystal Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5484 16-Segment LED Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5486 LED Display Driver.......................................... ................
MM58201 Multiplexed LCD Driver ....................................................
MM58241 High Voltage Display Driver ................................................
MM58242 High Voltage Display Driver ................................................
MM58248 High Voltage Display Driver.. .................... ........... ...............
MM58341 High Voltage Display Driver ................................................
MM58342 High Voltage Display Driver................ ............... .. ...............
MM58348 High Voltage Display Driver ................................................
AN-350 Designing an LCD Dot Matrix Display Interface ................................ "
AN-371 The MM58348/342/341 /248/242/241 Directly Drive Vacuum Fluorescent (VF)
Displays ........................................................................
AN-378 A Novel Process for Vacuum Fluorescent (VF) Display Drivers ....................
AN-440 New CMOS Vacuum Fluorescent Drivers Enable Three Chip System to Provide
Intelligent Control of Dot Matrix VF Display ..........................................

4-2

4-3
4-4
4-6
4-6
4-9
4-12
4-14
4-18
4-21
4-24
4-26
4-28
4-32
4-36
4-39
4-41
4-44
4-50
4-57
4-61
4-65
4-68
4-71
4-76
4-82
4-87
4-92
4-97
4-102
4-107
4-112
4-131
4-142
4-148

~National

~ Semiconductor
Display Drivers
MOS/LSI DISPLAY DRIVERS
National's comprehensive family of display drivers provides
direct interface to all of the common display technologieslight-emitting diode (LED), liquid crystal display (LCD), and
vacuum fluorescent (VF).

for direct or multiplexed interface to large complex VF panel
arrays or 5 X 7 (or larger) dot-matrix character strings. Each
of the drivers are cascadable for further expansion. Application note AN-371 provides further details and other application information.

FUNCTION SIMILAR FAMILY

THE MM5450 SERIES-LED

Each driver utilizes a simple serial-data input channel, onchip shift register, latches and buffer/driver outputs. The
serial input channel allows direct interface to most microprocessors, including COPSTM, NSC800™, 8080 series,
and TMS1000 series. Besides a serial-data input, each driver requires a clock input. Some offer a latch (data) input
and/or data output for easy cascade interconnect of additional drivers.

National's MM5450 series of LED display drivers rounds out
this comprehensive product family. This popular series offers direct drive of LED displays by providing up to 25 rnA of
current drive per LED segment.
CMOS/LSI
Many of the products in the display driver family utilize
CMOS technology and are further evidence of National's
capabilities and commitment to CMOS/LSI-the technology
of the '80s.

Once loaded, the shift register data can be transferred to
the on-chip latches, which then output to the buffer/driver
and respective display. This buffer/driver is where each provides the unique driver interface desired by the particular
display technology-LED, LCD, or VF.

In addition, National offers a line of bipolar segment and
digit drivers with a broad range of output sink and source
currents.
Detailed features/functions of the 16-member display driver
family are high-lighted in the following product guide.

THE MM58241 SERIES-VF
Each of the products in the MM58241 series provides highvoltage (several up to 60V) drive of VF displays. All are ideal
OUTPUT
32

OUTPUT
1

-- --

-- - I

BLANKING
CONTROL --+

'1

32 OUTPUT
BUFFERS

I

-- -32 LATCHES

1-- -DATA
IN

CLOCK

-[>-+1

32-BIT
SHIFT REGISTER

1.I

1
I

DATA
OUT

"l,/./

ENABLE

TLlXX/0100-1

FIGURE 1. Typical Block Diagram
4-3

(1)

"C

"5

Cl
c::::

~NatiOnal

Semiconductor

o

;;
(.)
(1)

Q)

en
...

LSI Display Driver
Selection Guide

(1)

>
"i:
C

>m

Q.
(/)

is

Display
Technology

Product
Number

Vacuum
Fluorescent (VF)

MM58241

32"segment, direct/multiplexed drive to 60V, data enable, brightness control,
cascadable, 40-pin DIP or 44-pin PCC package.

4-82

VF

MM58242

20-digit, direct/multiplexed drive to 60V, data enable, brightness control,
cascadable, 28-pin DIP or PCC package.

4-87

VF

MM58248

35-segment, direct/multiplexed drive to 60V, pin-compatible to MM5448, 40-pin
DIP or 44-pin PCC package.

4-92

VF

MM58341

32-segment, direct/multiplexed drive to 35V, data enable, brightness control,
cascadable, 40-pin DIP or 44-pin PCC package.

4-97

VF

MM58342

20-digit, direct/multiplexed drive to 35V, data enable, brightness control,
cascadable, 28-pin DIP or PCC package.

4-102

VF

MM58348

35-segment, direct/multiplexed drive to 35V, pin-compatible to MM5448, 40-pin
DIP or 44-pin PCC package.

4-107

Liquid Crystal
(LCD)

MM5452

32-segment, direct drive, serial-data input, data enable, on-chip backplane (SIP)
oscillator, 40-pin DIP or 44-pin PCC package.

4-50

LCD

MM5453

33-segment, direct drive, serial-data input, SIP oscillator, 40-pin DIP or 44-pin
PCC package.

4-50

LCD

MM5483

31-segment, direct drive, serial-data input/output, latch (data) control, 40-pin DIP
or 44-pin PCC package.

4-65

LCD

MM58201

Multiplexed drive, 192 segments (8 backplanes, 24 segments), 192-bit RAM,
cascadable, RIC oscillator, serial-data input/output, 40-pin DIP or 44-pin PCC
package.

Light-Emitting
Diode (LED)

MM5450

34-segment, direct drive up to 25 mA, brightness control, data enable, 40-pin DIP
or 44-pin PCC package.

4-44

LED

MM5451

35-segment, direct drive up to 25 mA, brightness control, 40-pin DIP or 44-pin
PCC package.

4-44

LED

MM5480

23-segment, direct drive up to 25 mA, serial-data input, brightness control, 28-pin
DIP package.

4-57

LED

MM5481

14-segment, direct drive up to 25 mA, serial-data input, brightness control, 20-pin
DIP package.

4-61

LED

MM5484

16-segment, direct drive up to 10 mA, serial-data input/ output, cascadable,
22-pin DIP package.

4-68

LED

MM5486

33-segment, direct drive up to 25 mA, serial-data input/output, brightness
control, latch (data) control, 40-pin DIP package.

4-71

Features

4-4

Page
No"

4-76

c

iii"

~NatiOnal

"C

iii"

'<
C
-.

Semiconductor

<'
CD

-.
en
CD

Bipolar Display Driver
Selection Guide

CD

n

0'

::l

G)

c

ii

LED Display Segment Drivers

Device Number
and Temperature Range
O°C to + 70°C

Drivers!
Package

-55°C to + 125°C

OS75491
OS75493

CD

lo/Segment (mA)

4
OS55493

OS8654

Sink·
(Common
Anode)

Source
(Common
Cathode)

50

VMAX(V)
Comments
Input

Supply

50

15

10

4

30

10

10

8

50

36

36

Page
No.
4-6

Programmable Constant
Current

4-9
4-14

'Digit drivers with output sink capability may be used to drive segments of "common anode" displays.

LED Display Digit Drivers

Device Number
and Temperature Range
O°C to +70°C

IO!Dlglt (mA)
Drivers!
Package

- 55°C to + 125°C

OS75491
OS75494

Sink
(Common
Anode)

Input

Supply

50

10

10

10

10

4
OS55494

6

VMAX (V)

Source
(Common
Cathode)

150

Comments

Page
No.
4-6

Enable Control

4-12
4-6

OS75492

6

250

10

10

OS8870

6

350

10

10

OS8863

8

500

15

10

4-21

500

23

18

4-21

OS8963
OS8654

50

OS75492 Pinout,
Darlington Output

4-24

4-14

36

36

OS8874

50

10

10

Serial Shift Register Input

4-26

OS8973

100

10

10

3-Cell Operation-Low
Battery Indicator

4-39

400

9.5

45

Serial Input

3-17

OS3654

10

Gas Discharge Display Drivers
Device Number
and Temperature Range
O°C to +70°C
OS8880

-55°C to + 125°C
OS7880

Device
Type
Cathode Drivers

OS8884A

Drivers!
Package

Comments

Page
No.

7

BCD to 7-Segment

4-28

7

BCD to 7-Segment
with Comma and OP

4-36

Comments

Page
No.

Vacuum Fluorescent Display Drivers
Device Number
and Temperature Range

Device
Type

Drivers!
Package

OS8654

Ground Driver (segments)

8

OS8654

Anode Driver (digit)

8

O°Cto +70°C

-55°C to + 125°C

4-5

7-Segment plus OP

4-14
4-14

~National

D Semiconductor
DS75491 MOS-to-LED Quad Segment Driver
DS75492 MOS-to-LED Hex Digit Driver
General Description

Features

The OS75491 and OS75492 are interface circuits designed
to be used in conjunction with MOS integrated circuits and
common-cathode LEOs in serially addressed multi-digit displays. The number of drivers required for this time-multiplexed system is minimized as a result of the segment-address-and-digit-scan method of LED drive.

•
•
•
•
•

50 mA source or sink capability per driver (OS75491)
250 mA sink capability per driver (OS75492)
MOS compatability (low input current)
Low standby power
High-gain Darlington circuits

Schematic and Connection Diagrams
DS75492 (each driver)

DS75491 (each driver)

v

..----.

(14.3,5, .,10,121

(1,2,6, 7, 9, 131

A -"~M,;~"'-I
4k

TL/F/S830-1

TL/F/S830-2

DS75492 Dual-ln-L1ne Package

DS75491 Dual-ln-L1ne Package
4A

14

IA

4E

13

IE

4C

12

IC

Vss

II

GND

3C

3E

3A

IA

10

2C

14

2E

2A

IV

6Y

13

2V

5A

6A

12

2A

II

GND

SY

4A

10

3A

3V

4V
TL/F/S830-4

TLIF/S830-3

Top View

Top View
Order Number DS75491J, DS75492J,
DS75491N or DS75492N
See NS Package Number J14A or N14A

4-6

c
en
.......

Absolute Maximum Ratings

(Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Olstrlbutors for availability and specifications.
OS75491 OS75492
Input Voltage Range (Note 4)
-5V to Vss
Collector Output Voltage (Note 5)
10V
10V
Collector Output to Input Voltage
10V
10V
Emitter to Ground Voltage (VI ~ 5V)
10V
Emitter to Input Voltage
5V
Voltage at Vss Terminal with Respect
to any Other Device Terminal
10V
10V
Collector Output Current
Each Collector Output
50mA
250mA
All Collector Outputs
200mA
600 rnA

Electrical Characteristics Vss =
Symbol

OS75491
OS75492
600mW
600mW
Continuous Total Dissipation
O'Cto + 70°C
Operating Temperature Range
-65°C to + 150°C
Storage Temperature Range
Lead Temp. (Soldering, 10 sec)
300°C
300°C
Maximum Power Dissipation
at 25'C
1308 mW·
Cavity Package
1364 mWt
Molded Package
1207 mW·
1280 mWt
°Derate cavity package 8.72 mWI'C above 25'C; derate molded package
9.66 mWI'C above 25'C.
tDerate cavity package 9.09 mW/,C; derate molded package 10.24 mWI'C
above 25'C.

CJ1
~

CD

.....
...I.

C

en

.......

CJ1

~

CD
I\)

10V (Notes 2 and 3)

Parameter

Min

Conditions

Typ

Max

Units

0.9

1.2

V

OS75491
VCEON

"ON" State Collector Emitter Voltage

Input = 8.5V through 1 kO, ITA
VE = 5V, Ic = 50 mA
I TA

II

Input Current at Maximum Input Voltage

= 10V, I liN = 40/LA
= OV
I VIN = 0.7V
VIN = 10V, VE = OV,lc = 20 mA

IE

Emitter Reverse Current

VIN

Iss

Current Into Vss Terminal

ICOFF

"OFF" State Collector Current

= 25°C
= 0-70°C

Vc
VE

2.2

= OV, VE = 5V, Ic = 0 mA

1.5

V

100

/LA

100

/LA

3.3

rnA

100

/LA

1

mA

1.2

V

OS75492
VOL

Low Level Output Voltage

Input = 6.5V through 1 kO, ITA
lOUT = 250 mA
TA

IOH

High Level Output Current

VOH

II

Input Current at Maximum Input Voltage

Iss

Current Into Vss Terminal

I

Switching Characteristics Vss =
Symbol

0.9

= 0-70'C

= 10V I liN = 40/LA
I VIN

VIN

= 25°C

= 0.5V

= 10V,IOL = 20 mA

7.5V, TA

2.2

1.5

V

200

/LA

200

/LA

3.3

mA

1

mA

= 25'C

Parameter

I

Conditions

I Min I Typ I Max

Units

OS75491
tpLH

Propagation Delay Time, Low-to-High Level Output (Collector) I VIH

tpHL

Propagation Delay Time, High-to-Low Level Output (Collector) I RL

= 4.5V, VE = OV,
I
= 2000, CL = 15 pF I

I 100 I

ns

I 20 I

ns

OS75492
tpLH

Propagation Delay Time, Low-to-High Level Output

I VIH

= 7.5V, RL = 390, I

I

I 300

I

I
I

ns

I CL = 15 pF
ns
Propagation Delay Time, High-to-Low Level Output
30
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the O'C to +70'C temperature range for the D875491 and D875492.
Note 3: All currents into device pins shown as pOSitive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: The input is the only device terminal which may be negative with respect to ground.
Note 5: Voltage values are with respect to network ground terminal unless otherwise noted.

tpHL

4-7

•

AC Test Circuits and Switching Time Waveforms
0575491

0575492
7.5V

7.SV

""""",)----e-OUTPUT
"x)-~""-OUTPUT

TLIF/5830-5
TLIF/5830-6

\--$ 10".

--l
I

I

~=:"!'""_ _~"\JI_-I-- - - - - - - - - V'H
I
I

INPUT

I

_________ OV

~IO_%

10%

----VOH

50%

OUTPUT

I
I

I
I

I

I

I
I

I

I

IpHl~

I

Note 1: The pulse generator has the following characteristics. ZOUT

I
I

r--lplH--j

=

50n. PRR

Note 2: CL includes probe and jig capacitance.

4-8

=

100 kHz. tw

=

1 ,...s.

TLIF/5830-7

~National

~ Semiconductor
OS55493/0S75493 Quad LED Segment Driver
General Description

Features

The OS55493/0S75493 is a quad LED segment driver. It is
designed to interface between MaS IC's and LED's. An external resistor is required for each segment to drive the output current which is approximately equal to O.7V/RL and is
relatively constant, independent of supply variations. Blanking can be achieved by taking the chip enable (CE) to a
logical "1" level.

• Low voltage operation
• Low input current for MaS compatibility
•
•
•
•

Low standby power
Display blanking capability
Output current regulation
Quad high gain circuits

Schematic and Connection Diagrams

Rl
(4,5,12,13)

INPUT

3.1k

....-__t

o----~N\r-----

R4
5.5k
CHIP (9)
EN AB LE Q-...JV\/I\r-t......---1
(2,7,10,15)
'----_--0---.,

R5
4k

~ EXTERNAL

RSET

(3,6,11, ~~.J

CURRENT SET
RESISTOR

lOUT
TLlF17561-1

Dual-In-Line Package
RSET 4

IOUT4

IN 4

IN 3

IOUTJ

Truth Table
RSET 3

CE

13

x=

vss

RSET ,

louT1

IN 1

IN 2

IOUT2

RSET2

GND

TL/F/7561-2

Order Number DS55493J, DS75493J
or DS75493N
See NS Package Number J16A or N16A

4-9

CE

VIN

lOUT

0
0
1

1
0
X

ON
OFF
OFF

Don't care

Absolute Maximum Ratings

Operating Conditions

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

Supply Voltage
Vcc
Vss
Temperature T A
OS75493
OS55493

10V

Input Voltage

10V

Output Voltage

Vcc
- 65°C to + 150°C

Storage Temperature Range

Min

Max

Units

3.2
6.5

8.8
8.8

V
V

0
-55

+70
+125

°C
°C

-25mA

Output Current (lOUT)
Maximum Power Oissipation* at 25°C
Cavity Package
Molded Package

1371 mW
1280 mW

Lead Temperature (Soldering, 4 seconds)
260°C
'Derate cavity package 9.14 mW/'C above 25'C; derate molded package
10.24 mWI'C above 25'C.

Electrical Characteristics
Symbol

(Vss

~ Vce) (Notes 2 and 3)

Parameter

Conditions

Min

liN

Vss

ICE

Chip Enable Input Current

Vcc = Max, Vss
toGNO

= Max, VCE = 8.8V, All Other Pins

lOUT

Output Current

lOUT

= 50!!

lOUT

= RSET @ OV, VCE = 8.8V

@

2.15V, RL

Vcc = Min, Vss = 6.5V,
ICE = 80 J-tA, VIN = 6.5V
Through 1.0 k!!

Output Leakage Current

lOUT = RSET @ OV,
Measure Current to Gnd,
Vss = 8.8V

-8

= OV, VIN = 8.8V

Max

Units

3.2

mA

3.6

mA

2.1

mA

-13
-16

mA
-20

mA

Vcc = Min, VCE = OV
VIN = B.BV Through
100 k!!

-200

J-tA

VCE = 6.5V Though
1.0 k!!, VIN = 8.8V

-100

J-tA

VCE
IOL

Typ

= Max, VIN = 8.8V, Vcc = Open, VCE = OV

Input Current

Icc

Supply Current, Vcc

Vcc

= Max, Vss = Max, All Other Pins to Gnd

40

J-tA

Iss

Supply Current

Vcc

= OV, All Other Pins to Gnd

40

J-tA

Vcc

= Min, Vss = 8.8V

1.5

mA

1.4

mA

lOUT @ 2.15V, VCE
Through 100 k!!,
RL = 50!!

= 8.8V
0.5

lOUT = Open, RSET
VCE = ov

Switching Characteristics TA =

= Open,

25°C, nominal power supplies unless otherwise noted

Symbol

Parameter

Conditions

tpd(OFF)

Propagation Delay to a Logical "0"
From Input to Output

(See AC Test Circuit

tpd(ON)

Propagation Delay to a Logical "1"
From Input to Output

(See AC Test Circuit)

Min

Typ

Max

Units

170

300

ns

11

100

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the O'C to +70'C range for the 0575493 and across the -55'C to + 125'C range for the
0555493.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.

4-10

c

en
U1

Typical Applications

U1

+:ao

CD

w

.......

Vss

c

en
~

CALCULATOR
OROTHER-1
CURRENT
SOURCE
OUTPUT

U1

+:ao

CD

w

L _ _ _ 0~9!.....

__

.J

OS75494 DIGIT DRIVER
TL/F17561-3

AC Test Circuit
Vss
B.BV

Vee
J.2V

Switching Time Waveforms
RSET

RL = 50

Vss--.......,j
OV------~-~-----

-

10--------._00
">Cl.-..--tL-..J

lOUT

-2.1V-----__

OV--------~~---J

TLlF17561-5

DIODES
lN914

TL/F/7561-4

4-11

~

en

:e

~ National

eD

Semiconductor

~

en
~

~

CJ)

c

OS55494/0S75494 Hex Digit Driver
General Description

Features

The 0555494/0575494 is a hex digit driver designed to
interface between most M05 devices and common cathodes configured LED's with a low output voltage at high
operating currents. The enable input disables all the outputs
when taken high.

•
•
•
•
•
•
•

150 mA sink capability
Low voltage operation
Low input current for MOS compatibility
Low standby power
Display blanking capability
Low voltage saturating outputs
Hex high gain circuits

Schematic and Connection Diagrams
Dual-ln-L1ne Package
Vee (161

vee

IN 6

NC

IN 1

OUT 6

OUTS

IN 5

OUT4

IN 4

OUT 2

IN 2

OUT 3

IN 3

CE

INPUT

CHIP ENABLE
(91

OUT 1

GND
TLlF/5832-2

Top View
Order Number DS55494J, DS75494J
or D575494N
See NS Package Number J 16A or N 16A

GND (81
TL/F/5832-1

Truth Table

x=

Enable

VIN

VOUT

0
0
1

0
1

1
0
1

X

don't care

4-12

Absolute Maximum Ratings

If MilitaryI Aerospace specified devices are required,
contact the National Semiconductor Sales Officel
Distributors for availability and specifications.
Supply Voltage

10V

Input Voltage

10V

Output Voltage

c
en
U1

Operating Conditions

(Note 1)

Supply Voltage, Vcc

Min
3.2

Max
8.8

Units
V

Temperature, TA
OS75494
OS55494

0
-55

+70

+ 125

°C
°C

U1
0l:Io

<0

10V

Maximum Power Oissipation* at 25°C
Cavity Package
Molded Package

0l:Io

1433 mW
1362 mW

Lead Temperature (Soldering 4 seconds)
260°C
"Derate cavity package 9.55 mW/'C above 25'C; derate molded package
10.9 mWI'C above 25'C.

Electrical Characteristics
Symbol

(Notes 2 and 3)

Parameter

IIH

VCC

= Min, VIN = 8.8V

IlL

Logical "0" Input Current

VCC

= Max, VIN = -5.5V

IOH

Logical "1 " Output Current VCC

ICC

Min Typ Max Units

Conditions

IVCE = 8.8V through 100k
IVCE = 8.8V

Logical "1 " Input Current

VOL

Logical "0" Output Voltage VCC
VCE

I
IVIN = 8.8V, VCE = 6.5V through 1.0k

= Max, VOH = 8.8V VIN = 8.8V through 100k, VCE = OV
= Min, IOL = 150 mA, VIN = 6.5V through 1.0k,
= 8.8V through 100k

Supply Currents

One Driver "ON", VIN

VCC

=

= 8.8V

Max All Other Pins to GNO

Output "OFF" Time

CL

2.0

mA

2.7

mA

-20

J.tA

400

J.tA

400

J.tA

OS75494

0.25 0.35

V

OS55494

0.25

0.4

V

OS75474

8.0

mA

OS55494

10.0

mA

lVCE = 6.5V through 1.0k

100

J.tA

100

J.tA

40

J.tA

1.2

J.ts

IVIN = 8.8V through 100k

All Other Pins to GNO
tOFF

= 20 pF, RL = 24!l, VCC = 4.0V, See AC Test Circuits

0.04

13 100
ns
CL = 20 pF, RL = 24!l, VCC = 4.0V, See AC Test Circuits
tON
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified minimax limits apply across the O'C to +70'C range for the 0875494 and across the -55'C to + 125'C range for the
0855494.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Output "ON" Time

AC Test Circuit and Switching Time Waveforms
Vcc
()

VINe--

~-

:/

- TF
vss

~ RL

:~ 240
~~

-

<0

0l:Io

.......
C

en
......

- 65°C to + 150°C

Storage Temperature Range

U1
0l:Io

10%

0

- VOUT

TF =10ns
TR = 10 ns

TR

90 %

90%

VIN

5%

- r1

\
i\0%

10%

f---0.2ms- r---0.2ms-

_ ..... C

L

T 2 0 PF
_
±10%

,~2.2V
90%

VOUT

O.SV

TL/F/5832-3

!pOFF

\

-~

-

!pON
TL/F/5832-4

4-13

~National

~ Semiconductor
OS8654 8-0utput Display Driver
(LED, VF, Thermal Printer)
General Description
OS8654 is an 8-digit driver with emitter/follower outputs. It
can source up to 50 mA at a low impedance, and operates
with a constant internal drive current over a wide range of
power supply-from 4.5V to 33V. The OS8654 can be used
to drive electrical or mechanical, multiplexed or unmultiplexed display systems. It can be used as a segment driver
for common cathode displays with external current limiting
resistors or can drive incandescent or fluorescent displays
directly, both digits (anodes) and segments (grids). It will be
necessary to run the device at a lower duty cycle, to keep
the maximum package dc power dissipation less than
600 mW while operating all 8 outputs at high supply voltage

and large source current. The inputs are MOS compatible
and eliminate the need for level shifting since inputs are
referenced to the most negative supply of system.

System Description
The OS8654 is specifically designed to operate a thermal
printing head for calculator or other uses. In this application
the same segment in each digit is selected at the same
time, reducing the overall time for a complete print cycle.
The OS8654 is an 8-digit driver. With a 15-digit print head,
two of the OS8654 are required.

Connection Diagram
Dual-In-Llne Package
OUTS

our 6

OU.T 7

OU.TB

118

117

11 6

11 5

1~6

111

I

IN 5

10

TL/F/5633-1

Top View
Order Number DS8654N
See NS Package Number N18A

4-14

Absolute Maximum Ratings

If Military I Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Supply Voltage
36V
Input Voltage
Output Voltage

c
en

Operating Conditions

(Note 1)

Min
Supply Voltage (Ved

Q)
0)

Max

Units

4.5

33

V

0

+70

°C

Temperature (TA)

U1
0I:loo

36V
Vee - 36V
- 65°C to + 150°C

Storage Temperature Range
Maximum Power Dissipation· at 25°C
Molded Package

1563 mW

Lead Temperature (Soldering, 4 seconds)
·Derate molded package 12.5 mW/'C above 25'C.

260°C

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Conditions

Min

Typ

Max

Units

IIH

Logical "1" Input Current

Vee

= Max, VIN = 6.5V

390

500

/loA

IlL

Logical "0" Input Current

Vee

= Max, VIN = O.4V

13

40

/loA

0.01

-100

/loA

Vee - 1.8

Vee - 2.5

V

0.01

1.0

mA

= Vee - 33V

IOFF

"Off" State Leakage Current

VOUT

VON

"On" State Output Voltage

Vee = Max, liN
IOH = -50 mA

leC(OFF)

Supply Current

Vee

= 500/loA,

= Max, VIN = VOUT = GND

Vee = Max, VIN = 6.5V,
7.5
10
mA
lOUT = OmA
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified min/max limits apply across the O'C to + 70'C range for the 058654. All typicals are given for Vee = 30V and TA = 25'C.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.

leC(ON)

Supply Current
(All Outputs "ON")

Schematic Diagram
DS8654
~----------------. .--~~----e-----~--O~Vcc

IN...,

15k
......
.....

••• : 20k

'~, .....
':k!K

- '~,

•

: 2k

-'-

.:

•

1

L....----..

-O_DUT

4-15

TLIF/5833-2

•

Typical Applications
Thermal Printer
8 DIGITS

OS8654

LI

....

f

~

...........

r--~

•

~:
1

L--

......

r---

~~
~

... ..

~

"" ....

~~

~

~~

:
...

""

•

..

.

...

.AAA

~~

•
.....

1

,.........,

..--

•
~

---0 Vee

~~

~,
-'-

MOS CALCULATOR
CHIP
OS8656

7 SEGMENTS
SEGMENT DRIVERS

!

!

Vee

Veo

TL/F/5833-3

LED Display-o rnA to 50 rnA Peak Segment Current
SEGMENT INPUTS

VCC

DIGIT INPUTS

TL/F/5833-4

4-16

c
Typical Applications

en
0)

(Continued)

0')

U1
0l:Io

LED Display-50 rnA to 100 rnA Peak Segment Current
SEGMENT INPUTS

SEGMENT INPUTS

.....----,

.....----,

I I I I
oS8654

':'

I I I I
OS8654

Vee

LL

Inn
n n n
I~I I~I I~I I~I I~I

I I

I

Vee

':'

.H
"
'
nn nl

I~I I~I I~I

Vee

os8863

OS8863

':'

I I

Vee

':'

I

)
\

I

DIGIT INPUTS

TLIF/5833-5

VF Display
Vee
JOV

----

I

b

,

)""""

d

oS8654

I

DIGITS

f

T

I

T I

oP

T'00kf
~

.1 .l.. ...l _'- __

'-

'-

PLATES

-------------GRID

I
CATHODE
FILAMENT
AC]

~~6V

-- --- -- --- --- ---

----··f f f f f f f f
r---

OS8654

All resist ors are 100k.

-:d='

--

VCC
JDV

':'
\

For other applications, see D58881 data sheet.

DIGIT INPUTS

TLIF/5833-6

4-17

en
CD
CD

CO
en ~National

c

a

Semiconductor

DS8669 2-Digit BCD to 7-Segment Decoder/Driver
General Description

Features

The 088669 is a 2-digit BCD to 7-segment decoder/driver
for use with common anode LED displays. The 088669
drives 2 7-segment LED displays without multiplexing. Outputs are open-collector, and capable of sinking 25 rnA/segment. Applications include TV and CB channel displays.

•
•
•
•
•
•

Direct 7-segment drive
25 rnA/segment current sink capability
Low power requirement-16 rnA typ
Very low input currents-2 p,A typ
Input clamp diodes to both Vee and ground
No multiplexing oscillator noise

Logic and Connection Diagrams
Dual-ln-L1ne Package
AI

.1

24

GND

A2

bl
Bl
BCD

dl

INPUTS

Cl

AI

cl
7·SEGMENT
OUTPUTS

Bl

el
f1

01

gl

A2

a2

Cl

01
b2
B2
BCD

d2

INPUTS

C2

.1

c2
7·SEGMENT
OUTPUTS

bl

e2
cl

f2

12

dl
TLlF/5836-1

.1
f1

gl

12
TL/F/5836-2

Top View
Order Number DS8669N
See NS Package Number N24A

4-18

Absolute Maximum Ratings

c(J)
CD

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
Input Current

Temperature (TA)

Electrical Characteristics Vee =
Parameter

300°C

Operating Conditions

12V
-65°C to + 150°C

Supply Voltage (Vee)

Symbol

Min

Max

4.5

6.0

Units
V

0

+70

°C

5.25V. (Note 2)
Conditions

Min

Typ

Max

Units

VIH

Logical "1" Input Voltage

Vee = Min

2.0

Vee + 0.6

V

VIL

Logical "0" Input Voltage

Vee = Min

-0.3

0.8

V

10

Logical "1" Output
Leakage Current

Vee = Max.
VOUT = 10V

50

IJ-A

VOL

Logical "0" Output Voltage

10L = 25 mAo
Vee = Min

0.4

0.8

V

IIH

Logical "1" Input Current

VIN = Vee = Max

2.0

10

IJ-A

IlL

Logical "0" Input Current

VIN = OV.
Vee = Max

-0.1

-10

IJ-A

lee

Supply Current

All Outputs Low.
Vee = Max

16

25

mA

Vie

Input Clamp Voltage

liN = 10mA

Vee + 1.5V

V

-1.5V

V

10

IJ-s

10

IJ-S

liN = -10 mA
tpdO

Propagation Delay to a Logical "0"
from Any Input to Any Output

tpdl

Propagation Delay to a Logical "1"
from Any Input to Any Output

CO

"Derate molded package 16.04 mWI'C above 25'C.

20mA

Storage Temperature Range

2005mW

Lead Temperature (Soldering. 10 seconds)

7V

Output Voltage

en
en

Maximum Power Dissipation· at 25°C
Molded Package

RL = 4000
CL = 50 pF
TA = 25°C

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified

minImax limits apply across the O'C to + 70'C range for the 058669. All typicals are given for Vee

= 5.25V and TA

= 25'C.

Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.

•
4-19

en
CD

~

en

Truth Table

c

INPUT LEVELS
eN

BN

AN

81

b1

c1

d1

e1

n

91

82

b2

c2

d2

e2

12

92

DISPLAY 1

0
0
0
0
0
0
0
0
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
1

0
0
0
0
0
1
1
0
0
0
1
0
0
1
1
1

0
0
1
0
0
0
0
0
0
0
1
0
1
1
1
1

0
1
0
0
1
0
0
1
0
0
0
1
1
0
1
1

0
1
0
1
1
1
0
1
0
1
0
0
0
0
1
1

0
1
1
1
0
0
0
1
0
0
0
0
0
0
1
1

1
1
0
0
0
0
0
1
0
0
1
0
0
0
0
1

0
1
0
0
1
0
0
0
0
0
1
1
1
0
1
1

0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1

0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1

0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1

0
1
0
1
1
1
0
1
0
1
0
0
0
0
1
1

0
1
1
1
0
0
0
1
0
0
0
1
0
0
1
1

1
1
0
0
0
0
0
1
0
0
0
1
1
0
0
1

0

1
1

1
1
1
"0"
"I"

SEGMENT OUTPUTS

ON

DISPLAY 2
11
I_I

I
I

/

E'

E'

=1
_I

=1
_I

5
5-,

5
5-,

CJ

EI
9
1-1I

1-/
I

I_I

9
C

,q

1-/
I

I_I

F'
E

L

(Blank)

(Blank)

-

c

I

-

= Segment ON
= Segment OFF

TL/F/5836-3

Display Segment Notation

TL/F/5836-4

AC Test Circuit
Vee

4
00

TO OUTPUT
UNOERTEST

~PFJ

TL/F/5836-5

Switching Time Waveforms
3V
INPUT
OV

IN·PHASE OUTPUT

I

1.5V~'-\ tf<- 15 ns

t r ::;15ns Jr-1.5V

r-- tpdO-

tpd1

\

J'-f 1.5V

1.5V-'~

OV
I--tpd1-

OUT OF PHASE OUTPUT

JrIf

1.5V

,

tpdO

-,1.5V

OV
TL/F/5836-6

4-20

c

en
Q)

~National

Q)
C')

~ Semiconductor

w
......
c

DS8863/DS8963 MOS-to-LED 8-Digit Driver

co
C')

en
Q)

General Description

Features

The OS8863 and OS8963 are designed to be used in conjunction with MOS integrated circuits and common-cathode
LEO's in serially addressed multi-digit displays.

•
•
•
•

The OS8863 is an 8-digit driver. Each driver is capable of
sinking up to 500 mA.

w

500 mA sink capability per driver, DS8863, OS8963
MOS compatibility (low input current)
Low standby power
High gain Oarlington circuits

The OS8963 is identical to the OS8863 except it is intended
for operation at up to 18V.

Schematic and Connection Diagrams
y

11.4,5,7,10,12,14,16)
(2,3,6.8,11,13, IS, 171

A -e--'V"V'III-4t--I
6.6k
6.8k

TL/F/5839-1

Dual-In-Line Package
vss
18

IN8
17

OUT8

16

IN7

15

OUT7
14

IN6
13

OUT6

IN5

OUT5

12

EPI

SUBS

OUT1

INI

IN2

OUT2

OUTJ

IN3

OUT4

IN4

Voo
TLlF/5839-2

Top View
Order Number DS8863N or DS8963N
See NS Package Number N18A

4-21

Cf)

CD

0)

co

Absolute Maximum Ratings

C

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

en

......
Cf)
CD

co
co

en

Input Voltage Range
(Note 1)

C

058863

058963

-5Vto Vss

-5VtoVss

Collector (Output) Voltage
(Note 2)

10V

Collector (Output)-to-Input
Voltage

10V

10V

800mW

800mW

18V

Storage Temperature
Range

O°C to

High Level Output Current

VIN

- 65°C to

+ 150°C

+ 70°C

1563 mWt

1563mWt

260°C

260°C

Conditions

VOH

O°Cto

+ 70°C unless otherwise noted

10V, TA = O°C to

VIN

+ 70°C

tOerate molded package 12.5 mW/,C above 25'C.

18V

Parameter
Low Level Output Voltage

Input Current at Maximum Input Voltage

Iss

Continuous Total
Dissipation

Lead Temperature
(Soldering, 4 sec.)

Electrical Characteristics Vss =

II

500mA
600mA

Maximum Power Dissipation
at 25°C
Molded Package

Voltage at Vss Terminal With
Respect to Any Other
Device Terminal

IOH

500mA
600mA

18V

Emitter-to-Input Voltage

VOL

058963

Operating Temperature
Range

Emitter-to-Ground Voltage
(VI ~ 5V)

Symbol

058863
Collector (Output) Current
Each Collector (Output)
All Collectors (Output)

=
=
=

7V, lOUT

10V·

=

500 rnA

Typ

Min

I TA = 25°C

I liN = 40,..,A
I VIN = 0.5V

10V, IOL

=

20 rnA

Current into Vss Terminal

Max

Units

1.5

V

1.6

V

250

,..,A

250

,..,A

2

mA

1

rnA

'18V for the 058963

Switching Characteristics Vss = 7.5V, TA = 25°C
Symbol

Parameter

Conditions

Propagation Delay Time, Low-to-High Level Output

VIH = 8V, RL = 20!l,
CL = 15 pF

Propagation Delay Time, High-to-Low Level Output

Note 1: The input is the only device terminal which may be negative with respect to ground.
Note 2: Voltage values are with respect to network ground terminal unless otherwise noted.

4-22

Min

Typ

Max

Units

300

ns

30

ns

c

en

AC Test Circuits and Waveforms

0)
0)
0)

W
.......

058863

c

7.5V

en
0)
CD

0)

W

PULSE
GENERATOR
(NOTE I)

~~--4IIt---OUTPUT

IN

CL = 15pF
(NOTE 2)

TL/F/5B39-3

--l

f---$10nS

I I
iI-:~--~~--I-- - - - - - - - - V

1H

I
I

INPUT

I
10%

10%

~~-------ov

-----V
OUTPUT

OH

I

I

I
I

I

I

I

I
I

----~::.....-.l.-f------- VOL
I
I

I
I

I

tPHL~

I
I
I

~tPLH--j

I

TL/F/5B39-4

Note 1: The pulse generator has the following characteristics: ZOUT

= 50n. PRR = 100 KHz. tw = 1/Ls.

Note 2: CL includes probe and jig capacitance.

4·23

o

I'-

CO
CO
(f)

C

~National

a

Semiconductor

DS8870 Hex LED Digit Driver
General Description

Features

The DS8870 is an interface circuit designed to be used in
conjunction with MOS integrated circuits and common-cathode LED's in serially addressed multi-digit displays. The
number of drivers required for this time-multiplexed system
is minimized as a result of the segment-address-and-digitscan method of LED drive.

•
•
•
•

Sink capability per driver-350 mA
MOS compatibility (low input current)
Low standby power
High-gain Darlington circuits

Schematic and Connection Diagrams
DS8870 (Each Driver)

Dual-In-Line Package

v

lA

__- - - . ( 1 , 2, 6, 7, 9,13)

14

(14, J, 5,8,10,12)

6Y

13

6A

12

Vss

11

5A

5V

4A

10

A ~""''''''V-'''-I
4k

(4)

GND
TL/F/5841-1

IV

2Y

2A

GND

3A

3Y

4Y
TL/F/5841-2

Order Number DS8870J or DS8870N
See NS Package Number J14A or N14A

4-24

oen

Absolute Maximum Ratings (Note 1)

CO

CO

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Continuous Total Dissipation

Input Voltage Range (Note 4)

Storage Temperature

10V

Collector Output to Input Voltage

10V

Voltage at Vss Terminal with Respect to
Any Other Device Terminal

10V

Collector Output Current
Each Collector Output
All Collector Outputs

+ 70°C
+ 150°C

0° to
- 65°C to

Maximum Power Dissipation- at 25°C
Cavity Package
Molded Package

1308mW
1207 mW
260°C

Lead Temperature (Soldering, 4 seconds)

'Derate cavity package 8.72 mW/'C above 2S'C; derate molded package
9.66 mW/'C above 2S'C.

10V (Notes 2 and 3)

Parameter

Conditions

Min

Typ

Max

Units

1.2

1.4

V

1.6

V
p.A

VOL

Low Level Output Voltage

Input = 6.5V through kO,
lOUT = 350 mA, T A = 25°C

VOL

Low Level Output Voltage

Input = 6.5V through 1 kO,
lOUT = 350 mA

IOH

High Level Output Current

VOH

= 10V, liN = 40 p.A

200

IOH

High Level Output Current

VOH

= 10V, VIN = 0.5V

200

p.A

II

Input Current at Maximum Input Voltage

VIN

= 10V, IOL = 20 p.A

3.3

mA

Iss

Current into Vss Terminal

1

mA

Max

Units

Switching Characteristics Vss =
Symbol

.....
o

350mA
600mA

Electrical Characteristics Vss =
Symbol

Operating Temperature Range

-5Vto Vss

Collector Output Voltage

800mW

7.5V, TA

2.2

= 25°C

Parameter

Conditions

tpLH

Propagation Delay Time, Low-to-High Level Output

VIH = 7.5V, RL
CL = 15 pF

= 390,

tpHL

Propagation Delay Time, High-to-Low Level Output

VIH = 7.5V, RL
CL = 15 pF

= 390,

Min

Typ
300

ns

30

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the O'C to

+ 70'C temperature range.

Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: The input is the only device terminal which may be negative with respect to ground.

4-25

•

~National

~ Semiconductor
DS8874 9-Digit Shift Input LED Driver
General Description

Features

The OS8874 is a 9-digit LED driver which incorporates a
shift register input decoding circuit and a low battery indicator. Outputs will sink 110 mA at less than O.5V drop when
sequentially selected. When the Vee supply falls below 6.5V
typical, segment current will be furnished at digit 9 time to
indicate a low battery condition. Pin 13 is generally connected to the decimal point segment on the display so that when
a low battery condition exists, the left-most decimal point
lights up.

•
•
•
•

110 mA digit sink
Low battery indicator
Minimum number of connections
MOS compatible inputs

Connection Diagram
Dual-In-Llne Package
LOW
VCC

BATT
OUT

OUT 9

OUTS

OUT 7

OUT6

13

12

11

10

9

14

OUTS

I

I~~~--~--~----~
CP

SIR

r--- D

1

CLOCK
PULSE

5

2

IiAfA

OUT 1

OUT2

OUTl

6
OUT4
TL/F/5843-1

Top View

Order Number DS8874N
See NS Package Number N 14A

Equivalent Schematic

---ri
I~":"
I.PUTT cq ~
LOGIC

OUTPUT

1-----..._

TL/F/5843-2

4-26

c
en
00

Absolute Maximum Ratings

(Note 1)
If Militaryl Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Supply Voltage
10V
Input Voltage
3V
Output Voltage
10V
Storage Temperature Range
- 65°C to + 150°C

00
........

Maximum Power Dissipation· at 25°C
Molded Package
Lead Temperature (Soldering, 4 sec.)
"Derate mOlded package 10.24 mWrC above 2S'C.

1280 mW
260°C

Operating Conditions
Min
6.0
0

Supply Voltage (Vee)
Temperature (TA)

Max
9.5
+70

Units
V
°C

Electrical Characteristics (Notes 2 and 3)
Symbol
IIH

Parameter

Conditions

Logical "1" Input Current

Vee

Min

= Max, VIN = 3V

Typ

Max

Units

0.25

0.4

mA

0.05

0.1

mA

6.0

V

100

/-LA

IlL

Logical "0" Input Current

Vee

= Max, VIN = 0.8V

VeeL

Decimal Point "ON"

Vdp

=

VeeH

Decimal Point "OFF"

10H

Logical "1" Output Current

= 1V, Idp = -10 /-LA, 09 = VOL
Vee = Max, Output Not Selected

VOL

Logical "0" Output Voltage

Vee

= Min, Output Selected, 101 = 80 mA

0.45

1

V

Vee

= Max, Output Selected, 101

0.6

1.5

V

2.3V,ld~ =

-4 mA, 09

= VOL
7.0

Vdp

= 110 mA

V

13
Supply Current
19
mA
Vee = Max, One Output Selected
lee
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the O'C to + 70'C range. All typicals are given for TA = 2S'C.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.

Timing Diagram

(Upper Level More Positive)

U

IfmlJ
CLOCK PULSE

1

2

3

OUTPUTllJ

OUTPUT 2

---u

OUTPUI3~

.

OUTPU~9 J

4

5

6

7

8

9

1

2

U3

U
U
U
U

4-27

4

5

6

7

8

9

1

2

U-L.J
Lr

U

TLlF/5843-4

~

o

CO
CO
CO

en ~National
o

.......

o

CO
CO
1'0

~ Semiconductor

en DS7880/DS8880 High Voltage 7-Segment Decoder/Driver
o
General Description
The 087880/088880 is custom designed to decode four
lines of BCD and drive a gas-filled seven-segment display
tube.
Each output constitutes a switchable, adjustable current
sink which provides constant current to the tube segment,
even with high tube anode supply tolerance or fluctuation.
These current sinks have a voltage compliance from 3V to
at least 80V; typically the output current varies 1 % for output voltage changes of 3 to 50V. Each bit line of the decoder switches a current sink on or off as prescribed by the
input code. Each current sink is ratioed to the b-output current as required for even illumination of all segments.
Output currents may be varied over the 0.2 to 1.5 mA range
for driving various tube types or multiplex operation. The
output current is adjusted by connecting an external pro-

gram resistor (Rp) from Vee to the Program input in accordance with the programming curve. The circuit design provides a one-to-one correlation between program input current and b-segment output current.
The Blanking Input provides unconditional blanking of any
output display, while the Ripple Blanking pins allow simple
leading- or trailing-zero blanking.

Features
•
•
•
•
•
•

Current sink outputs
Adjustable output current-O.2 to 1.5 mA
High output breakdown voltage-110V typ
8uitable for multiplex operation
Blanking and Ripple Blanking provisions
Low fan-in and low power

Logic Diagram
~-----------------I

I

....-___-+_

I

+

I

r--+--.....-

I

a OUTPUT

I
b OUTPUT

A INPUT
r-~--~- c OUTPUT

B INPUT
r-~--~- d OUTPUT

C INPUT

o INPUT
RIPPLE
BLANKING
INPUT

r-~--~-

e OUTPUT

r-~--~- f

-+------1

OUTPUT

r-~--~- g OUTPUT

BLANKING
INPUT!
RIPPLE
BLANKING
OUTPUT

-+---+--1

CURRENT
PROGRAMMING
INPUT
TLIF/5845-1

4-28

Absolute MalCimum Ratings

c
en
'-I

(Note 1)

If MilitaryI Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.

Storage Temperature Range

7V

Vee
Input Voltage (Except BI)
Input Voltage (BI)

50mA
- 65°C to + 150°C

Lead Temperature (Soldering, 4 sec.)

260°C

6V

Power Dissipation

600mW

Maximum Power Dissipation· at 25°C
Cavity Package
1509mW
Molded Package
1476 mW
'Derate cavity package 10.06 mWI'C above 2S'C; derate molded package
11.61 mWI'C above 2S'C.

Electrical Characteristics

Min

Max

Units

Supply Voltage (Vee)
DS7880
DS8880

4.5
4.75

5.5
5.25

V
V

Temperature (TA)
057880
DS8880

-55
0

+125
+70

°C
°C

(Notes 2 and 3)

Parameter

Min

Conditions

VIH

Logical "1" Input Voltage

Vee

VIL

Logical "0" Input Voltage

Vee

VOH

Logical "1" Output Voltage

Vee

VOL

Logical "0" Output Voltage

Vee

IIH

Logical "1" Input Current

Vee

=
=
=
=
=

IlL

Logical "0" Input Current

Vee

= Max, VIN = O.4V

Typ

Max

2.0

Min

= -200 J.LA, RBO
Min, lOUT = 8 mA, RBO

2.4

Max, Except BI

= 2.4V
VIN = 5.5V
VIN

Units
V

0.8

Min
Min, lOUT

V
V

3.7
0.13

0.4

V

2

15

J.LA
J.LA

4

400

Except BI

-300

-600

J.LA

BI

-1.2

-2.0

mA

= Max, Rp = 2.2k, All Inputs = OV
= Max, TA = 25°C, liN = 12 mA
Outputs a, f, and g
All Outputs = 50V,
10UTb = Ref.
Oututc

lee

Power Supply Current

Vee

27

43

mA

VeD

Input Diode Clamp Voltage

Vee

-0.9

-1.5

V

10

SEGMENT OUTPUTS
"ON" Current Ratio

0.84

0.93

1.02
1.38

Ib ON

Output b "ON" Current

VSAT

Output Saturation Voltage

leEX

Output Leakage Current

VSR

Output Breakdown Voltage

tpd

Propagation Delays BCD
Input to Segment Output

Vee = 5V, VOUTb = 50V,
All Other Outputs ~ 5V,
TA = 25°C

1.12

1.25

Outputd

0.90

1.00

1.10

Outpute

0.99

1.10

1.21

=
=
Rp =
Rp =
Rp

18.1k

0.15

0.20

0.25

mA

Rp

7.03k

0.45

0.50

0.55

mA
mA
mA

3.40k

0.90

1.00

1.10

2.20k

1.35

1.50

1.65

0.8

2.5

V

0.003

3

J.LA

= Min, Rp = 1k ± 5%, 10UTb = 2 mA, (Note 5)
VOUT = 75V, BI = OV, Rp = 2.2k
lOUT = 250 J.LA, BI = OV, Rp = 2.2k
Vee = 5V, TA = 25°C
Vee

80

110
0.4

V
10

J.Ls

BI to Segment Output

0.4

10

J.Ls

RBI to Segment Output

0.7

10

J.Ls

RBI to RBO
10
0.4
J.Ls
Note 1: "Absolute Maximum Rating" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -SS'C to + 12S'C temperature range for the 057660 and across the O'C to +70'C range for
the 056660. All typical values are for TA = 2S'C and Vee = SV.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min or absolute value basis.
Note 4: In all applications transient segment output current must be limited to SO rnA. This may be accomplished in dc applications by connecting a 2.2k resistor
from the anode-supply filter capacitor to the display anode, or by current limiting the anode driver in multiplex applications.
Note 5: For saturation mode the segment output currents are externally limited and ratioed.

4-29

o

........

c
en
CO
CO
CO

o

Operating Conditions

Vee
80V

Segment Output Voltage

Symbol

CO
CO

Transient Segment Output Current
(Note 4)

0
CO
CO

co

t/)

Connection Diagram
Dual-ln-L1ne Package

C

0
'"
co

OUTPUTS
i

•

•

b

c

d

r16

115

114

113

112

111

110

[I

r

Vcc

t/)

......

C

\

f

co

i.

)

B
\

6

17

X 1

PROXAM. BI/!:O

A

0

i

\

I

INPUTS

J:

INPUTS

TL/F/S84S-2

Top View
Order Number DS7880J,
DS8880J or DS8880N
See NS Package Number J16A or N16A

Typical Performance Characteristics
Output Current Programming

~~~~II~E;~~
sov

1.08

10.0

-_1
~

VoUT -

ON CURRENTS

TA-2SOC
3.0 "'_~.,-t--+-++t+H+--+-+-++t+t+I

~ 1.0 ~~mlElgl
~

ON CURRENT RATIOS -

\

~

~

_~

.1

_ Vee z 5V

TA

=

25·C-+--+---+-I---+l--I

V

1.02 J--+-+--'"I\-+V-'f~f--I--I

~

~

1.08
1.04

Output Characteristic

On Currents vs Temperature

Vcc - IV

~
0.3

1--+-+-++t+H.p,,_+-~+-H-Hf

",

0.1 ......................&....L..L..I.IoJIoI....-L.-.u........I..I..L,II
1
100
10
30

1.00 ........+-+-~/++-+--+---1
0.98

t--t--+-b~I-+--+--+---i

/

0.98 .....-.-+---f-,V'" Vee - 5V
0.94 ~-t-~- Vour - 50V

0.92
0.90

/
~

OUTPUT ON.,7 f1 mA

Ir-+-+--It-+I.....,,~~---i+-i

1\

TYPICAL OPERATING POINTS

-

Rp-OTEMPCOEFF.
0.2mA~lour~1.5mA

50

-50

Rp(kO)

100

30

60

90

120

OUTPUT VOLTAGE (V)
TLlF/S84S-3

4-30

c
en
.....
co

Typical Application

co

VAA

o
.......

(170 - 200 VDC)

c
en
co
co
co
o

DISPLAY

BECKMAN
DISPLAY TUBE

Vee
5V ± 10%

RBI
Bl/RBO

DECODER/DRIVER

MEMORY

COUNTER

TLlF/5B45-4

Truth Table
DECIMAL
RBlt
OR
FUNCTION

D

C

B

A

BI/RBO

a

b

c

d

e

f

9

0

1

0

0

0

0

0

0

1

0

1

0

0

0

DISPLAY

,-,

I_I
I
I

1

X

0

0

0

1

1

1

0

0

1

1

1

1

2

X

0

0

1

0

1

0

0

1

0

0

1

0

3

X

0

0

1

1

1

0

0

0

0

1

1

0

=1
_I

4

X

0

1

0

0

1

1

0

0

1

1

0

0

'-I

5

X

0

1

0

1

1

0

1

0

0

1

0

0

5

6

X

0

1

1

0

1

0

1

0

0

0

0

0

E,

7

X

0

1

1

1

1

0

0

0

1

1

1

1

-,
I

8

X

1

0

0

0

1

0

0

0

0

0

0

0

I_I

9

X

1

0

0

1

1

0

0

0

0

1

0

0

_I

10

X

1

0

1

0

1

0

0

0

1

0

0

0

11

X

1

0

1

1

1

1

1

0

0

0

0

0

,?

CJ

X

1

1

0

0

1

0

1

1

0

0

0

1

'-

X

1

1

0

1

1

1

0

0

0

0

1

0

I_I

14

X

1

1

1

0

1

0

1

1

0

0

0

0

15

X

1

1

1

1

1

0

1

1

1

0

0

0

Sl*

X

X

X

X

X

O·

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

1

1

1

tx

=

SEGMENT
IDENTIFICATION

d

1=1
b1-

12

*BI/RBO used as input onlv

lIe

e

0

13

RBI

.

t/~b

-1

E
I-

I-

Don't cara
TLlF/5B45-5

4·31

.....

co
co
co

en ~National
c

U Semiconductor
OS8881 Vacuum Fluorescent Display Driver
General Description

Features

The DS8881 vacuum fluorescent display driver will drive
16-digit grids of a vacuum fluorescent display. The decode
inputs select one of the sixteen outputs to be pulled high.
The device contains an oscillator for supplying clock signals
to the MOS circuit, the filament bias zener and 50 kn pulldown resistors for each grid. Outputs will source up to 7 mA.
The DS8881 is designed for 9V operation. If the enable input is pulled low, all outputs are disabled.

• Oscillator frequency accuracy and stability allows maximum system speed
• Interdigit blanking with the enable input provides ghostfree display operation
• 50 kn pull-down resistors for each grid
• 7V filament bias zener

Connection Diagram
D1
28

02
27

OJ

04

26

05

25

06

24

07

23

08

22

09

21

010

20

011

19

012

18

D1J

17

1
00

.F
VSS

J

EN

4

5

0

6

C

7

I~
r

OSCILLATOR

~

'7V

'r'.J

J8

B

A

15

~

DECODER

I

014

16

OSC

P

1

Jl0

12

1T~RTV'

13
VBB

r4
015

TL/F/5846-1

Top View
Order Number DS8881N
See NS Package Number N28B

Truth Table All outputs now shown high are off (low)
Inputs

Digit Outputs

EN

D

C

B

A

0

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X

H

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

H
H
H
H
H
H
H
H
H
H
H
H
H
H
L

L

L

L

L

L
4-32

L

L

L

L

L

L

L

L

L

H
L

c
Typ

required,
3S Office!

Max

I.Inlts

/-ts

j

66

Max

Units

5.0
Gnd

9.5
-26

V
V

0

+70

°C

5°C to + 150°C

ns

2168 mW
260°C

500

400

10mA

Min

-20mA

300

0

IS.

/-ts

1

50

Supply Voltage
Vss
VBB
Temperature (TA)

38V

1

en

Operating Conditions

ote 1)

ns
ns

S

(Notes 2 and 3)

kHz

Conditions

%
~

,ax

Max

= Max

Min

Typ

Max

Units

Enable

liN = 260,...,A

5.1

V

A,B,C,D

liN = 1400}.LA

1.5

V

260

}.LA

Enable

1.0

V

A,B,C,D

0.3

V

Enable A, B, C, D

-1.0

Enable

VIN = OV

A, B, C, D

VIN = VIL(MAX)

t Output, IOH = -7 mA

}.LA

25

,...,A

Vss - 2.5

V

;s = Max, Osc. Output, VRC = 0.6V, VOH = 10V

50

}.LA

-450

,...,A

85

kfl

IOL = 6mA

0.5

V

IOL = 60,...,A

0.2

V

Iss = Min, Pin R, VRC = 0.6V, VR = OV

-150

Vss = Min, Digit Output

30

50

~2

Vss = Min

Osc

VRC = 1.6V

Pin R
Vss = Max

Digit Output

Vss = 9.5V, IOH = 0

,t

as

Vss = 9.5V, IB = 0,
VBB = -26V, liN = 300,...,A
(Note 4)

VENABLE = 1V IOL = 10,...,A
9.0

VENABLE = 5.1V

VBB + 1.4

V

12.5

mA

VENABLE = 1V

5.0

9.0

mA

VENABLE = 1V

-0.8

-1.5

mA

VENABLE = 5.1V

-3.0

-5.0

mA

IB=10mA

VBB + 6.4 VBB + 6.9 VBB + 7.4

V

lximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
3rwise specified, minimax limits apply across the O·C to

+ 70·C range.

All typicals are given for T A

= 25°C.

s into device pins shown as positive, out of device pins as negative, and all voltages referenced to ground unless otherwise noted. All values
min on absolute value basis.
,ately 50% of input current on pins 4, 5, 6, 7 is shunted to Vss. If minimum Iss is desired, then liN should be minimized by using resistors in series

4-33

CO
CO
CO
~

,....

co
co
co
(/)
C

Switching Characteristics TA =
Symbol
tpdO
tpdO

25°C unless otherwise specified

Parameter

Conditions

Min

Propagation Delay to a Logical "0"
from Enable Input to Digit Output
Propagation Delay to a Logical "0"

A, S, C, D to Digit Output

RL = 4.7 kn, CL = 50 pF, VBB = -23V, VSS = 8V r---r--

tpd1

Propagation Delay to a Logical "1"
from Enable Input to Digit Output

tpd1

Propagation Delay to a Logical "1"
from A, S, C, D to Digit Output

tFALL

Oscillator Output Transition Time
from 1 to 0

Vss = 9.5V, RL = 6k to Vss, CL = 25 pF

fosc

Oscillator Frequency

dc

Oscillator Duty Cycle

7V < vss < 9.5V, RT = 27 kn ±2%, RL = 1.3k,
CT = 100 pF, ±5%, CL = 50 pF

--

320

3t

46

5~

AC Test Circuit

8V

TO PULSE {EN

()

GEN

.~
• ~ Rl

.~

C~
8V "'-

6

10k

.....;.
1

AAA

~

~
~

5

.........

DRIVER OUT

~rL::':::1--""-...L"'-C-i.-tr<:~_)J TO SCOPE

~ 'v~

/:::\ .. '!,;2k

~

28

...!.

T_

r!!.

.!!.

DS8881

!!..
~

.l!.
.!!..
~
~
~
-23Vo-~,,----------'"

TLlFIt

4-34

c
Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage
Vss
VBB
Temperature (TA)

38V

Supply Voltage (VSS-VBB)
Input Curront
Output Current

10mA
-20mA

Storago Tomperature

en

Operating Conditions

(Note 1)

Min

Max

Units

5.0
Gnd

9.5
-26

V
V

0

+70

°C

en
en

ClO
.....

- 65°C to + 150°C

Maximum Power Dissipation* at 25°C
Moldod Package

2168 mW

Load Tomperature (Soldering, 4 sec.)
'Oorato moldod package 17.35 mW/'C above 2S'C.

260°C

Electrical Characteristics (Notes 2 and 3)
Symbol

Max

Units

Enable

liN

= 260 fLA

5.1

V

A,B,C,D

liN

= 1400}.LA

1.5

V

260

}.LA

Enable

1.0

V

A,B,C,D

0.3

V

-1.0

}.LA

Parameter

Conditions

Min

VIH

Logical "1"
Input Voltage

Vss

= Max

IIH

Logical "1"
Input Current

Vss

= Max

VIL

Logical "0"
Input Voltage

Vss

= Max

Logical "0"
Input Current

Vss

VOti

Logical "1"
Output Voltage

Digit Output, 10H

lOti

Logical "1"
Output Current

Vss

los

Output Short-Circuit Vss
Current

= Min, Pin R, VRC = 0.6V, VR = OV

ROUT

Output Pull-Down
Resistor

Vss

= Min, Digit Output

VOL

Logical "0"
Output Voltage

Vss

= Min

Vss

= Max

Vss

= 9.5V, 10H = 0

IlL

Iss

100

VB

Supply Current

Supply Current

Filament Bias
Voltage

= Max

Enable A, B, C, D

Enable
A,B,C,D

= OV

VIN

= VIL(MAX)

VIN

= -7 rnA

25

}.LA

Vss - 2.5

V

= Max, Osc. Output, VRC = 0.6V, VOH = 10V

Osc

Digit Output

Vss = 9.5V, IB = 0,
VBB = -26V, liN = 300}.LA
(Note 4)

-150
30

VRC

= 1.6V

Pin R

IB

Typ

10L

= 6 rnA

10L

= 60}.LA

VENABLE

= 1V 10L = 10 fLA

VENABLE
VENABLE

50

50

}.LA

-450

}.LA

85

kn

0.5

V

0.2

V

VBB + 1.4

V

= 5.1 V

9.0

12.5

rnA

= 1V

5.0

9.0

rnA

VENABLE

= 1V

-0.8

-1.5

rnA

VENABLE

= 5.1V

-3.0

-5.0

rnA

= 10 rnA

VBB + 6.4 VBB + 6.9 VBB + 7.4

V

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified, minimax limits apply across the O'C to + 70'C range. All typicals are given for TA = 25'C.
Note 3: All currents into device pins shown as positive. out of device pins as negative, and all voltages referenced to ground unless otherwise noted. All values
shown as max or min on absolute value basis.
Note 4: Approximately 50% of input current on pins 4, 5, 6, 7 is shunted to Vss. If minimum Iss is desired, then liN should be minimized by using resistors in series
with the inputs.

4-33

•

......

co
co
co

(J)

C

Switching Characteristics T A =
Symbol
tpdO
tpdO

25°C unless otherwise specified

Parameter

Conditions

Min

Typ

Propagation Delay to a Logical "0"
from Enable Input to Digit Output
Propagation Delay to a Logical "0"

A, B, C, D to Digit Output

Max

Units

1

,..,s

1

,..,s

RL = 4.7 k!1, CL = 50 pF, Vss = -23V, Vss = BV

tpdl

Propagation Delay to a Logical "1"
from Enable Input to Digit Output

300

ns

tpdl

Propagation Delay to a Logical "1"
from A, B, C, D to Digit Output

500

ns

tFALL

Oscillator Output Transition Time
from 1 to 0

Vss = 9.5V, RL = 6k to VSS, CL = 25 pF

50

ns

fosc

Oscillator Frequency

dc

Oscillator Duty Cycle

7V < Vss < 9.5V, RT = 27 k!1 ± 2%, RL = 1.3k,
CT = 100 pF, ±5%, CL = 50 pF

320

360

400

kHz

46

56

66

%

AC Test Circuit

8V
C)

{,.= .vo---f

TO PULSE·~
GEN

~

=RL

8V~

.!!.

.!.

~~ A'!..2!

C~

A

1°! l'

2!.

23

yyy

DS8881

10

T

1 ..
-1. ._...... 1
T RT.2..
r---2l11

OSC OUT ~~
TO SCOPE ~ C

C
T

~-==':"

TO SCOPE

~

9

---CL

%

1'::\ DRIVER OUT

~

25

1!.

8

...LCi.

-

5
6

•• '"

-

28
21

..l.

~
~
~

.....

Ri.

18

~

l!..

.1!.
!!..

~

-23V ....
0-. .- - - - - - - - - -...
TLlF/5846-2

4-34

c
en
Q)

Switching Time Waveforms

Q)
Q)
.....

ENABLE
INPUT
O.4V
IFAll

-7V

OSC VOH --r-------,

DRIVER
OUTPUT

OUTPUT

--23V

VOL

I------Ip-----I
TLIF/584S-4

5V
DECODE
INPUT

Duty Cycle

OV
Frequency

toN

=t;
1

-7V
DRIVER
OUTPUT
--23V

(tr =

tf

=

10 ns from 10% to 90% of input)

TLIF/584S-3

Input-Output Schematics
Vss

ENABlE
INPUT

Vss

5k

R
OUTPUT

00-015
OUTPUTS

RC
INPUT

TO DECODER
CIRCUITRY

Vaa
TLlF/5846-7

'::'
TL/F/584S-S

TLlF/584S-5

III

csc

DUTPUT? __

A.a.c.Dl1
INPUTS

I

5k
TL/F/5846-9

TLlF/584S-8

4-35



Maximum Power Dissipation· at 25°C
Molded Package
'Derate molded package 13.71 mW/'C above 2S'C.

7V

Vee
Input Voltage (Note 4)

- 65°C to + 150°C

Supply Voltage (Vee>
Temperature (TA)

50mA

Min
4.75
0

Max
5.25
+70

Units
V
°C

Electrical Characteristics ,(Notes 2 and 3)
Symbol

Parameter

Min

Conditions

Max

Units

V

VIH

Logical "1" Input Voltage

Vee = 4.75V

VIL

Logical "0" Input Voltage

Vee = 4.75V

1.0

V

IIH

Logical "1" Input Current

Vee = 5.25V, VIN = 2.4V

15

,...A

IlL

Logical "0" Input Current

Vee = 5.25V, VIN = O.4V

-250

,...A

40

rnA

2.0

lee

Power Supply Current

Vee = 5.25V, Rp = 2.Sk, All Inputs = 5V

VI+

Positive Input Clamp Voltage

Vee = 4.75V, liN = 1 mA

VI-

Negative Input Clamp Voltage

Vee = 5V,IIN = -12 mA, TA = 25°C

Ala

SEGMENT OUTPUTS
"ON" Current Ratio

All Outputs = 50V, lOUT b = Ref., All Outputs

IbON

Output b "ON" Current

Vee = 5V, VOUT b = 50V,
TA = 25°C

leEX

Output Leakage Current

VOUT = 75V

VSR

Output Breakdown Voltage

lOUT = 250,...A

tpd

Propagation Delay of Any
Input to Segment Output

Vee = 5V,TA = 25°C

5.0

V
-1.5

0.9

1.1

V

Rp = 1S.1k

0.15

0.25

Rp = 7.03k

0.45

0.55

mA

Rp = 3.40k

0.90

1.10

mA

Rp = 2.S0k

1.0S

1.32

mA

5

,...A

SO

rnA

V
10

,...5

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified min/max limits apply across the O'C to + 70'C temperature range for the DS8884A. All typical values are for TA = 2S'C and
Vcc = SV.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: This limit can be higher for a current limiting voltage source.
Note 5: In all applications transient segment output current must be limited to SO mA. This may be accomplished in DC applications by connecting a 2.2k resistor
from the anode·supply filter capacitor to the display anode, or by current limiting the anode driver in multiplex applications.

Typical Application
v.

Y
r - - ycc----..,
I
I
I
I
I
I

e????99999

I
I

I:F
I jl
I

I
I
I

: v"

I
!PRoe

PANAPLEXII DISPLAV

1.1.1, Id 1·1' I, Ip~ I

R
•

COMMA
---OO.PT.

DSlll4A

nANKING

~!,!l~.~_

I
I
I

:.J

_ _

~ ~ ~ ~

- - - 0 COMMA

~

eNo

TL/F/SB47-4

'::"

4·37

•

<

ico

Truth Table

.

(J)

C

FUNCTION

D.PT.

COMMA

D

C

B

A

a

b

c

d

0

I

I

0

0

I

0

I

I

0
0

2

I

0
I

0
0

I

I

0
0
0
0
0

0

I

0
0

0

I

0
0
0
0

I

I

3

I

I

4

I

I

0
0
0

I

I

I

0

I

0
0

0

5
6
7
8
9
10

I

I

I

I

I

0

1
1
1

1
1
1
1
1
1
1
1
1
1
0

0
0

I

I

I

0

0

1

0
0
0
1
1
1

0
I

1
0
1
0

0
0
0
0
0
1

1

0
0
0

1

1

:

1

0

0

0
1
0

0

0
1
1
1

1
1
1
1

I

11

I

12

13
14
15

1
1
1
1

·D.PT.

0

·Comma

0

I
1

I

I
I

0
0
0

0
0
0
0
0

f

g

DISPLAY

0

0

I

I

I

I

I

0
0

0

I

I

I

I

I

0
0

0
0
0

0
I
2
3
'-I

I

0
0
1
0
0
0
0
1
0
1

0

0
1
0
1

0

0

1
0
0

1
0
0

0

1

1

0

1

0
0
1
1

0
0
0
0

I

1

I

I

0
1
1

I

1
0
1
1

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

1
1
I

0
I

I

5
6-,
I

B
9

n
a

BIe

F3

,
a

D Decimal Point

P Comma

TLlF/5847-3

·Decimal point and comma can be displayed with or without any numeral.

Logic Diagram
Vee

r-------------t----------i

OUTPUTS

+

140k

INPUTS

7SEGMENT
DECODER

140k
d.pL

I

~------------~-----------~
GND

4·38

TL/F/5847-1

c
en
QO

~National

D

CD

.......

Semiconductor

W

058973 9-Digit LED Driver
General Description
The DS8973 is a 9-digit driver designed to operate from
3-cell battery supplies. Each driver will sink 100 rnA to less
than 0.7V when driven by only 0.1 rnA. Each input is blocked
by diodes so that the input can be driven below ground with
virtually no current drain. This is especially important in calculator systems employing a DC-to-DC converter on the
negative side of the battery. If the converter were on the
positive side of the battery, the converter would have to
handle all of the display current, as well as the MOS calculator chip current. But if it is on the negative side, it only has

to handle the MOS current. The DS8973 is designed for the
more efficient operating mode.

Features
•
•
•
•

Nine complete digit drivers
Built-in low battery indicator
High current outputs-100 rnA
Straight through pin out for easy board layout

Equivalent Circuit Diagrams
Typical Driver Circuit

Typical D.P. Out Circuit

r-----e--o vCC2

VCC1

10k
INPUT

O-...J\M_. .-~

PIN 1

OUTPUT

TL/F/5851-2

.....---e~o() GROUND
TLlF/5851-1

Connection Diagram
Dual-In-Llne Package
OUTPUTS

10

VOLT
LOW
IND

9_ _ _ _ _ _ _

~\

~

_ _ _ _ _ _-J'
1

INPiJrs

Top View
Order Number DS8973N
See NS Package Number N22A
4-39

11

GNO
TL/F/5851-3

Absolute Maximum Ratings (Note 1)

Operating Conditions

If Military/Aerospace spp.clfled devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Min

Max

Units

Supply Voltage (VB)

3.0

5.5

V

Supply Voltage (Vee1)
Temperature (TA)

3.0

9.5

V

0

+70

°C

Supply Voltage

10V

Input Voltage

10V

Output Voltage
Storage Temperature Range

10V
- 65°C to + 150°C

Maximum Power Dissipation* at 25°C
Molded Package
Lead Temperature (Soldering, 4 seconds)
'Derate molded package 13.39 mWrC above 25·C.

1673 mW
260°C

Electrical Characteristics
Symbol

Parameter

Conditions

Min

VIH

Logical "1 " Input Voltage

Vee = Max

3.9

IIH

Logical "1 " Input Current

Vee = Max, VIH = 3.9V

0.1

VIL

Logical "0" Input Voltage

Vee = Max

IlL

Logical "0" Input Current

Vee = Max, VIL = 0.5V

VSH

High Battery Threshold

VOT (Pin 1) = 1V, lOT::;: -50 p,A,
TA = 25°C, VIH (Pin 2) = 3.9V

DS8973

VSl

Low Battery Threshold

VOT (Pin 1) = 2.1V, lOT::;: -6 rnA,
TA = 25°C, VIH (Pin 2) = 3.9V

DS8973

ICEX

Logical "1" Output Current

VOL

Logical "0" Output Voltage

leC1

Supply Current

Vee = Max, One Input "ON"

Typ

Max

Units

0.3

rnA

0.5

V

40

p,A

V

3.6

V
3.2

V

Vee = Min, VOH = 9.5V, VIL = 0.5V

50

p,A

Vee = Min, IOL = 100 rnA, VIH = 3.9V

0.7

V

6

rnA

Pin 21 (High Battery Supply)
rnA
1.2
Vee = Max, VB = Max
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified, min/max limits apply across the O·C to + 70·C range. All typicals are given for TA = 25·C.
Note 3: All currents into device 'pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.

IB

4-40

National Semiconductor
Application Note 84

Driving 7-Segment Gas
Discharge Display Tubes
with National
Semiconductor Drivers
INTRODUCTION
Circuitry for driving high voltage cold cathode gas discharge
7-segment displays, such as Sperry Information Displays·
and Burroughs Panaplex II, is greatly simplified by two
monolithic integrated circuits from National Semiconductor.
They are: DS8880 high voltage cathode decoder/driver and
DS8884A high voltage cathode decoder/driver.

To allow operation without anode voltage regulation, the
cathode driver must be able to sink a constant current in
each output, with the output "on" voltage ranging from 5V
to 50V (see Figure 1). The following is a brief description of
the circuits now offered by National:

In addition to satisfying all the displays' parameter requirements, including high output breakdown voltage, these circuits have capability of programming segment current, and
providing constant current sinking for the display segments.
This feature alleviates the problem of achieving uniformity of
brightness with unregulated display anode voltage. The National cirucits can drive the displays directly.
Sperry Information Display· and Burroughs Panaplex II are
used principally in calculators and digital instruments. These
7-segment, multi-digit displays form characters by passing
controlled currents through the appropriate anode/segment
combinations. The cathode in any digit will glow when a
voltage greater than the ionization voltage is applied between it (the cathode) and the anode for that digit. In the
multiplexed mode of operation, a digit position is selected
by driving the anode for that digit with a positive voltage
pulse. At the same time, the selected cathode segments are
driven with a negative current pulse. This causes the potential between the anode and the selected cathodes to exceed the ionization level, causing a visible glow discharge.
Generally, these displays exhibit the following characteristics: low "on" current per segment-from 200 /-tA (in DC
mode) to 1.2 mA (in multiplex mode); high tube anode supply voltage-180V to 200V; and moderate ionization voltage-170V. Once the element fires, operating voltage drops
to approximately 150V and light output becomes a direct
function of current, which is controlled by current limiting or
current regulating cathode circuits. Current regulation therefore is most desirable since brightness will then be constant
for large anode voltage changes. Tube anode to cathode
"off" voltage is approximately 100V; and maximum "off"
cathode leakage is 3 /-tA to 5 /-tA.
Correspondingly, specifications for the cathode driver must
be complimentary, approximately as follows: A high "off"
output breakdown voltage 80V minimum; typical "on" output voltage of 50V; maximum "on" output current of 1.5 mA
per segment; and maximum "off" leakage current of 3 /-tA to
5/-tA.
'Now called Beckman Displays

4-41

TYPICAL OPERATING POINTS

OUTPUT OFF

I

5nA

30

60

90

120

OUTPUT VOLTAGE (V)
TL/F/5871-1

(a) Cathode Driver Output Characteristic
1.04

c
;::
c:c
a: 1.03
a:
c
1.02

\1

l~~V

~~~l

I-

~
a:
a:

1.01

:::::I

u
2

1.00

5:l
N

0.99

c

/

a:
c
2

0.97

~ C~RREINT RATIOS
~.1
J I I
Vee =5V
Rp

V
o

=50V
=0 TEMP. COEF.

VOUT

/V

::::i

c:c
:E 0.98

/

-

0.2 rnA:S
10

20

30

40

lOUT

50

:S 1.2 rnA
60

70

TA (OC)

TL/F/5871-2

(b) On Currents vs Temperature
FIGURE 1
058880 HIGH VOLTAGE CATHODE DECODER/DRIVER
The DS8880 offers 7-segment outputs with high output
breakdown voltage of 80V minimum; constant current-sink
outputs; and programmable output current from 0.2 mA to
1.5 mA.

~

CD

Z•

.:(

APPLICATION
The circuit has a built-in BCD decoder and can interface
directly to Sperry and Panaplex II displays, minimizing exter-

nal components (Figure 2). The inputs can be driven by TTL
or MOS outputs directly. It is optimized for use in systems
with 5V supplies.
v....
(+170 - 200 VDC)

DISPLAY

Vee
I+5V ±lDl1)

RBI

DECODER/DRIVER

BI/RBD

MEMORY

COUNTER

TL/F/5871-3

FIGURE 2. DC Operation From TTL
The 058880 decoder/driver provides for unconditional as
well as leading and trailing zero blanking. It utilizes negative
input voltage clamp diodes. Typically, output current varies
only 1 % for output voltage changes of 3V to 50V. Operating
power supply voltage is 5V. The device can be used for
multiplexed or DC operation.

Available in 16-pin cavity DIP packages, the 057880 is
guaranteed over the full military operating temperature
range of - 55·C to + 125·C; the 058880 in molded DIP
over the industrial range of O·C to + 70·C.

+SV

+200V

INPUT

SWITCHES
DR

nL

GATES
INPUT

OV

FIGURE 3. Interfacing Directly With TTL Output

4-42

TLlF/5871-4

DS8884A HIGH VOLTAGE CATHODE
DECODER/DRIVER

pled to TIL (Figure 3) or MOS outputs (Figure 4), or AC-coupled to TIL or MOS outputs (Figure 5) using only a capacitor. This means the device is useful in applications where
level shifting is required. It can be used in multiplexed operation, and is available in an 18-pin molded DIP package.

The DS8884A offers 9-segment outputs with high output
breakdown voltage of 80V minimum; constant current-sink
outputs, programmable from 0.2 mA to 1.2 mAo It also offers
input negative and positive voltage clamp diodes for DC restoring, and low input load current of -0.25 mA maximum.

Other advantages of the DS8884A are: typical output current variation of 1% for output voltage changes of 3V to
5aV; and operating power supply voltage of 5V. Inputs have
pull-up resistors to increase noise immunity in AC coupled
applications.

APPLICATION
DS8884A decodes four lines of BCD input and drives 7-segment digits of gas-filled displays. There are two separate
inputs and two additional outputs for direct control of decimal point and comma cathodes. The inputs can be DC cou-

The DS8884A is guaranteed over the aoc to
ing temperature range.

+ 70°C operat-

+5V

+180V
8 SEGMENT LINES

BCD

{.

MOS
CALCULATOR
CHIP

U)

U)

w

DS8884A
CATHODE
DRIVER

c
c

SPERRY
:r:: DISPLAY
I-

5

w

w

c
c

c
c

SPERRY

:r:: DISPLAY

z

I-

et

5

w

DS8887
ANODE
DRIVER

c
c

z

et

OV

-12V

TYP. COUPLING
CAPACITOR

8 ANODE CONTROL LINES

TLIF/5871-5

FIGURE 4. BCD Data Interfacing Directly With MOS Output
-195V

OV

Vcc

BCD!
MOS
COUNTER
OR
CALCULATOR
CHIP

DS8884AA
CATHODE
DRIVER

•

PANAPLEX II
DISPLAY
U)

w

t-----I~c

t-_d_.p;..t._. . .

3

c

U)

w

c

~

comma

8 ANODE LINES
1M TVP(8 PL)

-JOV
TL/F/5871-6

Note: Capacitive coupling between the logiC and the segment drivers may be used only when the segment drivers are turned "OFF" during digit-to-digit
transistions.

FIGURE 5. Cathode BCD Data AC Coupled From MOS-Output
4-43

....

.."

~ ~National
~ ~ Semiconductor
c

.."
~

~

:E

MM5450/MM5451 LED Display Drivers
•
•
•
•
•

General Description
The MM5450 and MM5451 are monolithic MOS integrated
circuits utilizing N-channel metal-gate low threshold, enhancement mode, and ion-implanted depletion mode devices. They are available in 40-pin molded or cavity dual-in-line
packages. A single pin controls the LED display brightness
by setting a reference current through a variable resistor
connected to Voo.

Enable (on MM5450)
Wide power supply operation
TTL compatibility
34 or 35 outputs, 15 mA sink capability
Alphanumeric capability

Applications
•
•
•
•
•

Features
• Continuous brightness control
• Serial data input
• No load signal required

COPSTM or microprocessor displays
Industrial control indicator
Relay driver
Digital clock, thermometer, counter, voltmeter
Instrumentation readouts

Block Diagram
VOO

OUTPUT 34

OUTPUT 1

BRIGHTNESS r-"'--~:-:-~--"
CONTROL

18

35 lATCHES

OUTPUT35 (MM5451)
S~~~~

....._ _ _ _-+-~

-----i-...

CLOCK ....

9

r--------------~tL...._,1

bATA ENABLE (MM5450) ....._ _ _ _-+-__

LOAD

35·BIT SHIFT REGISTER

....

.)~----

RESET

TL/F/6136-1

FIGURE 1

4-44

Absolute Maximum Ratings
If Military I Aerospace specified devices are required,
contact the National Semiconductor Sales Officel
Distributors for availability and specifications.

Storage Temperature

- 65°C to + 150°C

Power Dissipation

560 mW at + 85°C
1Wat +25°C

Voltage at Any Pin

Junction Temperature

Vss to Vss + 12V

Operating Temperature

- 25°C to + 85°C

+150°C
300°C

Lead Temperature (Soldering, 10 sec.)

Electrical Characteristics
T A within operating range, VDD = 4.5V to 11.0V, Vss = OV unless otherwise specified
Parameter

Conditions

Min

Power Supply

Typ

Max

4.75

Power Supply Current

Excluding Output Loads

Input Voltages
Logical "0" Level (VLl
Logical "1" Level (VH)

± 10 p.A Input Bias
4.75V:s; Voo :s; 5.25V
Voo> 5.25V

Brightness Input Voltage (Pin 19)

V

7

mA

O.B

-0.3
2.2
Voo - 2V

Voo
Voo

V
V
V

0

0.75

mA

VOUT = 3.0V
VOUT = 1V (Note 3)
Brightness Input = 0 p.A
Brightness Input = 100 p.A
Brightness Input = 750 p.A

0
0
2.0
15

10
15
10
4
25

p.A
mA
p.A
mA
mA

Input Current 750 p.A

3.0

Brightness Input (Note 2)
Output Sink Current
Segment OFF
Segment ON

Units

11

2.7

4.3

V

±20

0/0

500
950
950

kHz
ns
ns

Data Input
Set-Up Time, tos
Hole Time, tOH

300
300

ns
ns

Data Enable Input
Set-Up Time, tOES

100

ns

Output Matching (Note 1)
Clock Input
Frequency, fe
High Time, th
Low Time, tl

(Notes 5 and 6)

Note 1: Output matching is calculated as the percent variation (IMAX + IMIN)/2.
Note 2: With a fixed resistor on the brightness input pin, some variation in brightness will occur from one device to another. Maximum brightness input current can,
be 2 mA as long as Note 3 and junction temperature equation are complied with.
Note 3: See Figures 5, 6, and 1 for Recommended Operating Conditions and limits. Absolute maximum for each output should be limited to 40 mAo
Note 4: The VOUT voltage should be regulated by the user. See Figures 6 and 1 for allowable VOUT vs lOUT operation.
Note 5: AC input waveform specification for test purpose: t, ,;; 20 ns, tf ,;; 20 ns, f = 500 kHz, 50% ± 10% duty cycle,
Note 6: Clock input rise and fall times must not exceed 300 ns.

Connection Diagrams
Dual-In-Line Package
1

oUTPUT BI:~~ J:

38

r!!.. OUTPUTBIT21

?

OUTPUTBITll~
OUTPUTBIT10...!.
MM5450

..g.. OUTPUT BIT25
2!.. OUTPUT BIT2B
2!.. OUTPUT BIT21

OUTPUT BITl...!!.

,!!.. OUTPUT BIT II

OUTPUT BIT 8",*
OUTPUTBIT5~

OUTPUTBIT2~
BRIGHTNESS CONT:~~

OUTPUT Bill

~OUTPUTBIT22
~OUTPUTBIT2l
~OUTPUTBIT24

r#- OUTPUT BIT 25

~OUTPUTBIT26

MMS451

OUTPUTBIT113
OUTPUT BIT 6

"it
~ ~~:~~ ::~ ~16
~~~:~~ :II~: Ji

~

~

~CLOCKIN

VOO-

TL/F/6136-2
Top View

FIGURE 2b
FIGURE 2a
Order Number MM5450N, MM5451N, MM5450Vor MM5451V
See NS Package Number N40A or V44A
4-45

OUTPUTBITJ5

-¥.- DATA IN

BRIGHTNESS CONTROL-To

r-- CLOCK IN

OUTPUT BITJO

.!!.. OUTPUTBITJ4

18

Top View

OUTPUT BIT 21

l2... OUTPUT BIT 28
.!!.. OUTPUT BIT29
.!!.. OUTPUT IITl2
.!!.. OUTPUT BITll

OUTPUT BIT 1"";'

~ OATAIN

~

.g.. OUTPUTBITJl

:

~1l1iTA'!1Jill[

J!

7.

OUTPUT BIT 8"t'

~OUTPUTBITl4

OUTPUT BIT 1-;;

~ OUTPUT BIT 20

OUTPUT BIT 10..!.

2.!.. OUTPUTBIT21

OUTPUTBIT4..!!

r.!.!.. OUTPUT BIT21

OUTPUTBITI2~
OUTPUTBITll~

OUTPUT BIT24

~ OUTPUT BIT29
~ OUTPUT BIT lO
~OUTPUTBlTll
~ OUTPUT BIT l2

OUTPUT BIT1...!!.

OUTPUTBITI5"5
OUTPUT BIT 14
OUTPUTBITll-

~ OUTPUT BIT 2l

OUTPUT BIT 12..2.

l!.. OUTPUT BIT 19

"6

.!!. OUTPUT BIT 22

OUTPUT BIT 13.!.

~OUTPUTB1T18

OUTPUTBI:~~~3

OUTPUTBIT16.

~OUTPUTBIT20

~~~:~~ ::~ ::~

BIT9~
OUTPUTBITI~

1

~ OUTPUT BIT 19

OUTPUT BIT 16-+

OUTPUT

Dual-In-Line Package

.!!. OUTPUT BIT 18

TL/F/6136-3

•

,....
&l)
~

&l)

:e
:e
......

Connection Diagrams

(Continued)

Plastic Chip Carrier

0

&l)

~ ~ ~ ~

~

~

~ ~ ~ ~

~ ~ ~

CD

~ ~ ~ ~

~

~

&l)

:e
:e

"'u
5o 5 5o 5 ~~
0

0

I!:

:::l

0

~

:::l

0

N

:::l

N

N
N

t::

~
~

5 5 5 I!:
000

:::l

0

OUTPUT BIT 13

OUTPUT BIT 23

OUTPUT BIT 12

OUTPUT BIT 24

OUTPUT BIT 11

OUTPUT BIT 25

OUTPUT BIT 10

OUTPUT BIT 26

OUTPUT BIT 9

OUTPUT BIT 27

H/C

H/C

OUTPUT BIT 8

OUTPUT BIT 28

OUTPUT BIT 7

OUTPUT BIT 29

OUTPUT BIT 6

OUTPUT BIT 30

OUTPUT BIT 5

OUTPUT BIT 31

OUTPUT BIT 4

OUTPUT BIT 32

..,

....I

N

""

~

U

~ I"

.., ..,..,
'Ot

~~
~ ~ ~ ~
~ ~ ~
Z
g C< z... ~
~ :::l ~ 0u
u
~
0

I!: I!: I!:
:::l :::l :::l
0

o

0

~

~

i!:
::t:

!::::
CD

....
:::l

I!:
I!:
:::l :::l
0

0

(!)

~

TLIF/6136-13

Top View
Plastic Chip Carrier
0
N
N NN
~ ~ ~ ~ ~

~ ~ ~ ~

~ ~

~ ~ ~ ~
:::l

~ ~ ~

I!: :::l
I!:

:::l

o

0

5 I!:
0

:::l

0

~ ~

"'u

~~

:::l

~

5 5 5 I!:
000

:::l

0

~

I!:

:::l

0

OUTPUT BIT 13

OUTPUT BIT 23

OUTPUT BIT 12

OUTPUT BIT 24

OUTPUT BIT 11

OUTPUT BIT 25

OUTPUT BIT 10

OUTPUT BIT 26

OUTPUT BIT 9

OUTPUT BIT 27

H/c

H/c

OUTPUT BIT 8

OUTPUT BIT 28

OUTPUT BIT 7

OUTPUT BIT 29

OUTPUT BIT 6

31

OUTPUT BIT 30

OUTPUT BIT 5

OUTPUT BIT 31

OUTPUT BIT 4

OUTPUT BIT 32

..,

N

-

0....I

~ ~ ~ ~
.... 0z

....
:::l

~

0

0

I!:
I!:
:::l :::l

:::l

""

U

VI

0

~

..,..,

~

u

~ ~ ~ !::::
CD
C§
~ :::l :::l

d

U

5~

..,

~

~ ........ :.::
z

It')

.... ....

I!:
I!: I!:
:::l :::l :::l
0

i!:
::t:

~

0

0

TL/F/6136-14

Top View

4-46

Functional Description
Both the MM5450 and the MM5451 are specifically designed to operate 4- or 5-digit alphanumeric displays with
minimal interface with the display and the data source. Serial data transfer from the data source to the display driver is
accomplished with 2 signals, serial data and clock. Using a
format of a leading "1" followed by the 35 data bits allows
data transfer without an additional load signal. The 35 data
bits are latched after the 36th bit is complete, thus providing
non-multiplexed, direct drive to the display. Outputs change
only if the serial data bits differ from the previous time. Display brightness is determined by control of the output current for LED displays. A 0.001 capacitor should be connected to brightness control, pin 19, to prevent possible oscillations.

There must be a complete set of 36 clocks or the shift registers will not clear.

A block diagram is shown in Figure 1. For the MM5450 a
DATA ENABLE is used instead of the 35th output. The
DATA ENABLE input is a metal option for the MM5450. The
output current is typically 20 times greater than the current
into pin 19, which is set by an external variable resistor.
There is an internal limiting resistor of 400n nominal value.

For applications where a lesser number of outputs are used,
it is possible to either increase the current per output, or
operate the part at higher than 1V Your. The following
equation can be used for calculations.

When the chip first powers ON an internal power ON reset
signal is generated which resets all registers and all latches.
The START bit and the first clock return the chip to its normal operation.

Figure 2 shows the pin-out of the MM5450 and MM5451. Bit
1 is the first bit following the start bit and it will appear on pin
18. A logical "1" at the input will turn on the appropriate
LED.
Figure 3 shows the timing relationships between data, clock
and DATA ENABLE. A max clock frequency of 0.5 MHz is
assumed.

Tj = (Vour) (ILEO) (No. of segments) (124°C/W)

+ TA

where:

Figure 4 shows the input data format. A start bit of logical
"1" precedes the 35 bits of data. At the 36th clock a LOAD
signal is generated synchronously with the high state of the
clock, which loads the 35 bits of the shift registers into the
latches. At the low state of the clock a RESET signal is
generated which clears all the shift registers for the next set
of data. The shift registers are static master-slave configuration. There is no clear for the master portion of the first shift
register, thus allowing continuous operation.

Tj = junction temperature

+ 150·C max

Your = the voltage at the LED driver outputs

ILEO = the LED current
124·C/W = thermal coefficient of the package
T A = ambient temperature
The above equation was used to plot Figure 5, Figure 6 and
Figure 7.

1r-==\--90%
-----'~10%

DATA

DATA ENABLE ---~
(MM5450)
TL/F/6136-4

FIGURE 3

4-47

Functional Description

(Continued)
~

I

CLOCKrL.Il...f"Lrl..1....fUUL
START

BIT 34

-

BIT 35

"'r~" "'r---\.r - -~~_J~_J~_J~

-"\r---\.r -

r--\,.- -

~~

nL--

LOAD
(INTERNALI------------------J

RESET
(INTERNALI--------------

------1LTL/F/6136-5

FIGURE 4. Input Data Format

Typical Performance Characteristics
1.0

~

0.8

E

0.6

Ci

0.4

2.5

zQ

Q

~

ill
a:

~

l~ I~

2.0

~

>

1.5 f1.0

-

110
TA' 85'C
Tj" 150'C (MAX)

100
90

..) J
~ J""9V
Ik

TL/F/6136-9

FIGURE 8. Typical Application of Constant Current Brightness Control
5V

TL/F/6136-IO

FIGURE 9. Brightness Control Varying the Duty Cycle

4-48

--

25

NUMBER OF SEGMENTS

TLlF/6136-7

TLlF/6136-6

FIGURES

- -

...... ..... r........

~

20
10

TA .185'C

.--

I

.... VOUT"2V

r\X r\.

40
30

0

I

\,

50

wH

.... VOUT=I.5V

.\-

60

0.5

0.2

- -l JOUT ~

Typical Applications

(Continued)

Basic Electronically Tuned Radio System
LED DISPLAY
AM
FM

Il- -11-1
Ii 7_71_1

~

~

~~

- 34--MM5450
DISPLAY
DRIVER
~

KEYBOARD

...

COPS
ELECTRONIC
TUNING
CONTROLLER

PLL
SYNTHESIZER

111

STATION
DETECT, ETC.
TLIF/6136-11

Duplexlng 8 Digits with One MM5450

MM5450

CLOCK IN ~---.....
OATAIN .....- - - -.....
BRIGHTNESS
CONTROL

lOOk
TVP

TL/F/6136-12

4-49

r----------------------------------------------------------------------------------,
~ ~National
~
~ Semiconductor
N
~

1.1)

1.1)
~

:E MM5452/MM5453 Liquid Crystal Display Drivers

:e

General Description
The MM5452 is a monolithic integrated circuit utilizing
CMOS metal gate, low threshold enhancement mode devices. It is available in a 40-pin molded package. The chip can
drive up to 32 segments of LCD and can be paralleled to
increase this number. The chip is capable of driving a 4 %digit 7-segment display with minimal interface between the
display and the data source.
The MM5452 stores display data in latches after it is
clocked in, and holds the data until new display data is received.

Features

•
•
•
•
•
•

DATA ENABLE (MM5452)
Wide power supply operation
TTL compatibility
32 or 33 outputs
Alphanumeric and bar graph capability
Cascaded operation capability

Applications
•
•
•
•
•

COPSTM or microprocessor displays
Industrial control indicator
Digital clock, thermometer, counter, voltmeter
Instrumentation readouts
Remote displays

• Serial data input
• No load signal required

Block Diagram
BACKPLANE BACKPLANE
OUT
IN

OUTPUT 32 OUTPUT 1

24

OATA ENABLE (MM5452) ....._ _ _ _ _ _....._ _ _ _ _ _......
OUTPUT 33 (MM5453)

s~~~k.-------22~-------i ~-------~~~~~~~!!l
21

CLOCK~------~-----__i ~---------~

TL/F/6137-1

FIGURE 1

4-50

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Storage Temperature

- 65°C to + 150°C

Power Dissipation

300 mW at + 70°C
350 mW at + 25°C

Voltage at Any Pin

Junction Temperature

Vss to Vss + 10V

Operating Temperature

O°Cto +70°C

+150°C

Lead Temperature (Soldering, 10 sec.)

300°C

Electrical Characteristics
TA within operating range, Voo = 3.0V to 10V, Vss = OV, unless otherwise specified
Parameter

Conditions

Power Supply Current

Max

Units

10

V

40
10

/-LA
/-LA

500

kHz

-0.3
-0.3

0.1 Voo
0.8

0.8 Voo
2.0

Voo
Voo

V
V
V
V

Min

Power Supply

3
Excluding Outputs
OSC = Vss, BP IN @ 32 Hz
Voo = 5V, Open Outputs, No Clock

Clock Frequency
Input Voltages
Logical 'a' Level
Logical '1' Level
Output Current Levels
Segments
Sink
Source
Backplane
Sink
Source

Voo <
Voo ~
Voo>
Voo:::;

4.75
4.75
5.25
5.25

Voo = 3V, VOUT = 0.3V
Voo = 3V, VOUT = Voo - 0.3V

20

Voo = 3V, VOUT = 0.3V
Voo = 3V, VOUT = Voo - 0.3V

320

Output Offset Voltage

Segment Load 250 pF
Backplane Load 8750 pF (Note 1)

Clock Input Frequency, fc

(Notes 2 and 3)

Typ

-20

/-LA
/-LA

-320

/-LA
/-LA

±50

mV

500

kHz

High Time, th

950

ns

Low Time, tl

950

ns

Data Input
Set-Up Time, tos
Hold Time, tOH

300
300

ns
ns

100

ns

Data Enable Input
Set-Up Time, tOES

Note 1: This parameter is guaranteed (not 100% production tested) over operating temperature and supply voltage ranges. Not to be used in a.A. testing.
Note 2: AC input waveform for test purpose: tr ,;; 20 ns, tf ,;; 20 ns, f

= 500 kHz, 50% ± 10% duty cycle.

Note 3: Clock input rise and fall times must not exceed 300 ns.

4-51

Connection Diagrams
Dual·ln·Llne Package

Dual·ln·Llne Package

Vss

Vss

OUTPUT BIT 18

OUTPUT BIT 17

OUTPUT BIT 17

OUTPUT BIT 19

OUTPUT BIT 11

OUTPUT BIT 11

OUTPUT BIT 20

OUTPUT BIT 15

OUTPUT BIT 15

OUTPUT BIT 21

OUTPUT BIT 14

OUTPUT liT 14

OUTPUT BIT 22

OUTPUT BIT 13

OUTPUT BIT 13

OUTPUT BIT 23

OUTPUT BIT 12

OUTPUT BIT 24

OUTPUT BIT 12

OUTPUT BIT 24

OUTPUT BIT 11

OUTPUT BI125

OUTPUT BIT 11

OUTPUT BIT 25

OUTPUT BIT 10

OUTPUTBI12I

OUTPUT BIT 10

OUTPUTBI127

OUTPUTBIT9

OUTPUTBIT9

MM5452

OUTPUT BIT.

OUTPUT BIT 26
OUTPUTBIT 27

MM5453

OUTPUTBI121

OUTPUT BIT I

OUTPUT BIT7

OUTPUTBI121

OUTPUT BIT 7

OUTPUT BIT 29

OUTPUT BITa

OUTPUTBIT30

OUTPUT liT 8

OUTPUT BIT 3D

OUTPUTlIH

OUTPUTBIT31

OUTPUT liT 5

OUTPUT BIT 31

OUTPUTlIT4

OUTPUT 81T 32

OUTPUT BIT4

OUTPUT BIT 32

OUTPUT BIT 3

mnrmrr

OUTPUT BIT 3

OUTPUT BIT 33

OUTPUTBIT2

BACKPLANE IN

OUTPUTlIT2

BACKPLANE IN

OUTPUT BIT 1

BACKPLANE OUT

OUTPUT liT 1

OUTPUT BIT 2.

BACKPLANE OUT

OATA IN
CLOCK IN

21

OATA IN
CLOCK IN

TLlF/6137-2

TL/F/6137-3

Top View
FIGURE2a

Top View
FIGURE2b

Plastic Chip Carrier

:

~ ~ ~

:!!

Iii Iii Iii Iii

~

~

....

Plastic Chip Carrier
~

~ ~ ~ N

Iii Iii Iii Iii Iii

~

Iii Iii Iii Iii Iii

l:I
~ ~ ~ ~o>~
5o 5 5 5o 5
!; !; !; !; !;

U

0

0

0

0

0

OUTPUT BIT 13

0

OUTPUT BIT 23

OUTPUT BIT 13

OUTPUT BIT 23

OUTPUT BIT 12

OUTPUT BIT 24

OUTPUT BIT 12

OUTPUT BIT 24

OUTPUT BIT 11

OUTPUT BIT 25

OUTPUT BIT 11

OUTPUT BIT 25

OUTPUT BIT 10

OUTPUT BIT 26

OUTPUT BIT 10

OUTPUT BIT 26

OUTPUT BIT 9

OUTPUT BIT 27

OUTPUT BIT 9

OUTPUT BIT 8

OUTPUT BIT 28

OUTPUT BIT 8

34

OUTPUT BIT 28

OUTPUT BIT 7

OUTPUT BIT 29

OUTPUT BIT 7

33

OUTPUT BIT 29

OUTPUT BIT 6

OUTPUT BIT 30

OUTPUT BIT 6

32

OUTPUT BIT 30

OUTPUT BIT 5

OUTPUT BIT 31

OUTPUT BIT 5

31

OUTPUT BIT 31

OUTPUT BIT 4

OUTPUT BIT 32

OUTPUT BIT 4

30

OUTPUT BIT 32

HIe

OUTPUT BIT 3

29

OUTPUT BIT 33

OUTPUT BIT 3

39

17

29

OUTPUT BIT 27

TL/F/6137-11

TLlF/6137-12

Top View

Top View
Order Number MM5452N, MM5453N,
MM5452V or MM5453V
See NS Package Number N40A or V44A

Functional Description
The MM5452 is specifically designed to operate 4 %-digit 7segment displays with minimal interface with the display and
the data source. Serial data transfer from the data source to
the display driver is accomplished with 2 signals, serial data
and clock. Since the MM5452 does not contain a character
generator, the formatting of the segment information must
be done prior to inputting the data to the MM5452. Using a
format of a leading "1" followed by the 32 data bits allows
data transfer without an additional load signal. The 32 data

bits are latched after the 36th clock is complete, thus providing non-multiplexed, direct drive to the display. Outputs
change only if the serial data bits differ from the previous
time.
A block diagram is shown in Figure 1. For the MM5452 a
DATA ENABLE is used instead of the 33rd output. If the
DATA ENABLE signal is not required, the 33rd output can
be brought out. This is the MM5453 device.

4·52

Functional Description

(Continued)

Figure 4 shows the input data format. A start bit of logical
"1" precedes the 32 bits of data. At the 36th clock a LOAD
signal is generated synchronously with the high state of the
clock, which loads the 32 bits of the shift registers into the
latches. At the low state of the clock a RESET signal is
generated which clears all the shift registers for the next set
of data. The shift registers are static master-slave configuration. There is no clear for the master portion of the first shift
register, thus allowing continuous operation.

If the clock is not continuous, there must be a complete set
of 36 clocks otherwise the shift registers will not clear.
Figure 2a shows the pin-out of the MM5452. Bit 1 is the first
bit following the start bit and it will appear on pin 18.
Figure 3 shows the timing relationships between data, clock
and DATA ENABLE.

CLOCK

DATA

DATA ENABLE
(MM5452)
TLIF/6137-4

FIGURE 3
36
CLOCK
BIT 35

START BIT 1
DATA

LOAD
(INTERNAL)

~

(INTERNAL)

BIT 36

-I?1WawJff.-~qiW.

n
----------------tl ____________....n•_____
----------------tl ___________..
~,

L_ _ _ _ _ __

~,

TLIF/6137-5

FIGURE 4_ Input Data Format

4-53

Functional Description

(Continued)

Figure 5 shows a typical application. Note how the input
data maps to the output pins and the display. The MM5452
and MM5453 do not have format restrictions, as all outputs

are controllable. This application assumes a specific display
pinout. Different display/driver connection patterns will, of
course, yield a different input data format.

Segm ent Identification

l~/b

"l3<
d

-I
BP Gl

Fl

1

r-

AI Bl G2 F2 A2 B2 G3 F3 A3 B3 C4 F4 A4

Il-I l-I I-I I-I

I./~/./~./~.I=I

1 DP El 01 ClOP E2 02 C2 DP E3 03 C3 DP E4 04 C4 B4

~

-

"'---

"""'--

'-'-'--

r---

"'--':"

vss
17

18
19

16

20

~
~

21

~I~
24

13
12
11

25

10

26

9
8

27
MM5453

28

7

29

6

3D

5

31

4

32

3

BACKPLANE OUT

2

BACKPLANE IN

1

33

OSC IN

~"-L
"*O.OI/J.F'(~

T

DATA IN
CLOCK IN

l-

v·
DATA FORMAT
TlME-LEFT END
DECIMAL
POINT

4TH
DECIMAL
POINT

2ND
DECIMAL
POINT

I
NULLS

I

I
TLIF/6137-6

Consult LCD manufacturer's data sheet for specific pinouts.

FIGURE 5. Typical 4Y:z-Dlglt Display Application

4·54

Functional Description

(Continued)
DISPLAY

BACKPLANE

TL/F/6137-7

"The minimum recommended value for R for the oscillator input is 9 kfi. An RC time constant of approximately
4.91 x 10- 4 should produce a backplane frequency between 30 Hz and 150 Hz.

FIGURE 6. Parallel Backplane Outputs
DISPLAY

BACKPLANE

BP
DUT
DSC
IN

BP
IN

2 X BACKPLANE
DRIVE FREQUENCY

TL/F/6137-8

FIGURE 7. External Backplane Clock
Figure 8 shows a four wire remote display that takes advantage of the device's serial input to move many bits of display
information on a few wires.

Figure 9 is a general block diagram that shows how the
device's serial input can be used to advantage in an analog
display. The analog voltage input is compared with a staircase voltage generated by a counter and a digital-to-analog
converter or resistor array. The result of this comparison is
clocked into the MM5452, MM5453. The next clock pulse
increments the staircase and clocks the new data in.

USING AN EXTERNAL CLOCK
The MM5452/MM5453 LCD Drivers can be used with an
externally supplied clock, provided it has a duty cycle of
50%. Deviations from a 50% duty cycle result in an offset
voltage on the LCD. In Figure 7, a flip-flop is used to assure
a 50% duty cycle. The oscillator input is grounded to prevent oscillation and reduce current consumptions in the
chips. The oscillator is not used.

With a buffer amplifier, the same staircase waveform can be
used for many displays. The digital-to-analog converter
need not be linear; logarithmic or other non-linear functions
can be displayed by using weighted resistors or special
DACs. This system can be used for status indicators, spectrum analyzers, audio level and power meters, tuning indicators, and other applications.

Using an external clock allows synchronizing the display
drive with AC power, internal clocks, or DVM integration
time to reduce interference from the display.
4-55

•

Functional Description

(Continued)
DISPLAY

~-------.------------~
DATA

-------1----1-.....

BYPASS
CAPACITOR
CLOCK ------+---+--I~

V-------~--~--------~
TLIF/6137-9

FIGURE 8. Four Wire Remote Display
LCD BAR GRAPH DISPLAY

ANALOG VOLTAGE IN

11111000000

COUNT
CLOCK

DATA IN

I•
""'START
BIT

TL/F/6137-10

Data Is high until staircase > Input

FIGURE 9. Analog Display

4·56

~National

~ Semiconductor
MM5480 LED Display Driver
General Description
The MM5480 is a monolithic MOS integrated circuit utilizing
N-channel metal gate low threshold, enhancement mode
and ion-implanted depletion mode devices. It utilizes the
MM5451 die packaged in a 28-pin package making it ideal
for a 3% digit display. A single pin controls the LED display
brightness by setting a reference current through a variable
resistor connected either to Voo or to a separate supply of
11 V maximum.

Features
• Continuous brightness control
• Serial data input

•
•
•
•
•

No load signal required
Wide power supply operation
TTL compatibility
Alphanumeric capability
3% digit displays

Applications
•
•
•
•
•

COPSTM microcontrollers or microprocessor displays
Industrial control indicator
Relay driver
Digital clock, thermometer, counter, voltmeter
Instrumentation readouts

Block Diagram
BRIGHTNESS
CONTROL

TL/F/6138-1

FIGURE 1

Connection Diagram
Dual·ln·Llne Package
28

Vss
OUTPUT BIT 11

OUTPUT BIT 12
OUTPUT BIT 13

OUTPUT BIT 10

OUTPUT BIT 14

OUTPUT BIT 9

OUTPUT BIT 15

OUTPUT BIT 8

OUTPUT BIT 16

OUTPUT BIT 7

OUTPUT BIT 17

OUTPUT BIT 6

1011015480

OUTPUT BIT 5

OUTPUT BIT 18
OUTPUT BIT 19

OUTPUT BIT 4

OUTPUT BIT 20

OUTPUT BIT 3

OUTPUT BIT 21

OUTPUT BIT 2

OUTPUT BIT 22

OUTPUT BIT 1

OUTPUT BIT 23

BRIGHT. CONT.

DATA IN

VDD

14

Order Number MM5480N
See NS Package Number N28B

CLOCK
TLlF/6138-2

Top View
FIGURE 2
4-57

Absolute Maximum Ratings
If MilitaryI Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Voltage at Any Pin
Vss to Vss + 12V
Storage Temperature
- 65·C to + 150·C

Power Dissipation
Junction Temperature
Lead Temperature (Soldering, 10 sec.)

490 mW at + 85·C
940 mW at + 25·C
150·C
300·C

Electrical Characteristics
TA = -25·C to +85·C, Voo = 4.75V to 11.0V, Vss = OV unless otherwise specified
Symbol

Parameter

Conditions

Voo

Power Supply

100

Power Supply Current

Excluding Output Loads

VIL

Input Voltage
Logical "0" Level

± 10 p.A Input Bias

VIH

Input Voltage
Logical "1" Level

4.75V ::;: Voo ::;: 5.25V

Min

-0.3

"."

Voo> 5.25V

Brightness Input Current
(Note 2)

IOH

Output Sink Current (Note 3)
Segment OFF

VOUT = 3.0V

IOL

Output Sink Current (Note 3)
Segment ON

VOUT = 1V
Brightness Input = 0 p.A
Brightness Input = 100 p.A
Brightness Input = 750 p.A

Brightness Input Voltage
(Pin 19)

OM

Output Matching (Note 1)

Units

11

V

7

rnA

0.8

V

......

\/.

\/

Voo - 2

Voo

V

0

0.75

rnA

10.0

p.A

10.0
4.0
25.0

p.A
rnA
rnA

4.3

V

±20

%

0
2.0
15.0

Input Current = 750 p.A

AC Electrical Characteristics TA =
Symbol

Max

4.75

ISR

VISR

Typ

2.7

3.0

-25·Cto +85·C, Voo = 5V ±0.5V

Parameter

Conditions
(Notes 5 and 6)

Min
DC

Typ

Max

Units

500

kHz

fc

Clock Input Frequency

th

High Time

950

ns

tl

Low Time

950

ns

tos

Data Input Set-Up Time

300

ns

ns
Data Input Hold Time
300
matching is calculated as the percent variation from (lMAX + IMIN)/2.
Note 2: With a fixed resistor on the brightness input pin some variation in brightness will occur from one device to another. Maximum brightness input current can
be 2 mA as long as Note 3 and junction temperature equation are complied with.
Note 3: Absolute maximum for each output should be limited to 40 mAo
Note 4: The VOUT voltage should be regulated by the user.
Note 5: AC input waveform specification for test purpose: tr ~ 20 ns, tf ~ 20 ns, f = 500 kHz, 50% ± 10% duty cycle.
Note 6: Clock input rise and fall times must not exceed 300 ns.
tOH

Note 1: Output

4-58

Functional Description
The MM5480 is specifically designed to operate 3%-digit
alphanumeric displays with minimal interface with the display and the data source. Serial data transfer from the data
source to the display driver is accomplished with 2 signals,
serial data and clock. Using a format of a leading "1" followed by the 35 data bits allows data transfer without an
additional load signal. The 35 data bits are latched after the
36th bit is complete, thus providing non-multiplexed, direct
drive to the display. Outputs change only if the serial data
bits differ from the previous time. Display brightness is determined by control of the output current for LED displays. A
0.001 tJ.F ceramic or mica disc capacitor should be connected to brightness control, pin 13, to prevent possible oscillations.

There must be a complete set of 36 clocks or the shift registers will not clear.
When the chip first powers ON an internal power ON reset
signal is generated which resets all registers and all latches.
The START bit and the first clock return the chip to its normal operation.
Figure 5 shows the Output Data Format for the 5480. Because it uses only 23 of the possible 35 outputs, 12 of the
bits are 'Don't Cares'.
Figure 3 shows the timing relationships between data and
clock. A maximum clock frequency of 0.5 MHz is assumed.

For applications where a lesser number of outputs are used,
it is possible to either increase the current per output, or
operate the part at higher than 1V VOUT. The following
equation can be used for calculations.

A block diagram is shown in Figure 1. The output current is
typically 20 times greater than the current into pin 13, which
is set by an external variable resistor. There is an internal
limiting resistor of 400(1 nominal value.

Tj = (VOUT) (lLED) (No. of segments) (132°C/W)
where:
Tj = junction temperature

Figure 4 shows the input data format. A start bit of logical
"1" precedes the 35 bits of data. At the 36th clock a LOAD
signal is generated synchronously with the high state of the
clock, which loads the 35 bits of the shift registers into the
latches. At the low state of the clock a RESET signal is
generated which clears all the shift registers for the next set
of data. The shift registers are static master-slave configuration. There is no clear for the master portion of the first shift
register, thus allowing continuous operation.

+ TA

+ 150°C max.

VOUT = the voltage at the LED driver outputs
ILED = the LED current
132°C/W = thermal coefficient of the package
TA = ambient temperature

==~.-----90%

\

----~
,=,-10%

DATA
TLlF/613B-3

FIGURE 3

CLOCK

..

~~---- ~~-------

DATA

.-~~-~~.----~~

n

LOAD
(INTERNAL) - - - - - - - - - - - - - - - - - -....S~~S------.I

1._ _ __

IIL - -

RESET
(lNTERNAL) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-\S~

TLlF/613B-4

FIGURE 4. Input Data Format

FIGURE 5. Output Data Format

4·59

C) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

co
~

I.l)

Functional Description

:E
:E

(Continued)
7V

RAW DC
>9V

240n

119=~
1k
FIGURE 6. Typical Application of Constant Current Brightness Control

TL/F/6138-5

5V

TL/F/6138-6

FIGURE 7. Brightness Control Varying the Duty Cycle

,, ,,-",
,
... -Basic 3%-Dlglt Interface

Safe Operating Area
1.0 ,---"T""OI:::----r------::-:-===--,

:§:

0.8

z

~ 0.6 1----+--<'~~~~~~-----1

Q.

~

c

ei
~
Q.

0.4 I---+-N
0.2

I---~~~~~~~--l

1

23
0'----"'--''''''''''-''''''''''-'''''''''"''''''''''-'''''"'''-........''"""---'

o

20

40

60

80

MM5480
DISPLAY
DRIVER

100

TEMPERATURE (OC)
TL/F/6138-7

11

CLOCK

DATA
TL/F/6138-8

4-60

~National

~ Semiconductor
MM5481 LED Display Driver
• No load signal required

General Description
The 5481 is a monolithic MOS integrated circuit utilizing Nchannel metal gate low threshold, enhancement mode and
ion-implanted depletion mode devices. It utilizes the
MM5450 die packaged in a 20-pin package making it ideal
for a 2 digit display. A single pin controls the LED display
brightness by setting a reference current through a variable
resistor connected either to Voo or to a separate supply of
11 V maximum.

Features

•
•
•
•
•

Data enable
Wide power supply operation
TTL compatibility
Alphanumeric capability
2 digit LED driver

Applications
• cOPS or microprocessor displays
• Industrial control indicator
• Relay driver
• Instrumentation readouts

• Continuous brightness control
• Serial data input

Block and Connection Diagrams
Voo

OUTPUT 14

OUTPUT 1

BRIGHTNESS
CONTROL

TL/F/6139-1

FIGURE 1
Dual-In-Line Package
OUTPUT BIT B

OUTPUT BIT

OUTPUT BIT 7

OUTPUT BIT 10

OUTPUT BIT

OUTPUT BIT 11

OUTPUT BIT 5

4

OUTPUT BIT 4

OUTPUT BIT 12
OUTPUT BIT 13

1.41.45481

OUTPUT BIT 3

Vss

OUTPUT BIT 2

OUTPUT BIT 14

OUTPUT BIT 1

DATA ENABLE

BRIGHT CONT.

Voo

DATA IN
10

11

CLOCK
TL/F/6139-2

Top View
FIGURE 2
Order Number MM5481N
See NS Package Number N20A
4-61

Absolute Maximum Ratings
Voltage at Any Pin

Electrical Characteristics
TA

= - 25°C to

Symbol

+ 85°C, Voo

=

=

4.75V to 11.0V, Vss

Parameter

OV unless otherwise specified
Min

Conditions

Voo

Power Supply

100

Power Supply Current

Excluding Output Loads

VIL

Input Voltages
Logical "0" Level

± 10 p,A Input Bias

VIH

Logical "1 " Level

Brightness Input Current
(Note 2)

IOH

Output Sink Current
(Note 3)
Segment OFF

IOL

Segment ON

4.75

~

Voo

~

Brightness Input Voltage
(Pin 19)

OM

Output Matching (Note 1)

Units

11

V

7

mA

-0.3

0.8

V
V

2.2

Voo
Voo

V

0

0.75

mA

10.0

p,A

10.0
4.0
25.0

p,A
mA
mA

4.3

V

±20

%

Your = 3.0V
Your = 1V(Note4)

Input Current

AC Electrical Characteristics TA =
Symbol

Max

Voo - 2

5.25

Brightness Input
Brightness Input
Brightness Input
VISR

Typ

4.75

Voo> 5.25
ISR

+150°C
300°C

Junction Temperature
Lead Temperature (Soldering, 10 sec.)

Vss to Vss + 12V
- 65°C to + 150°C
450 mW at + 85°C
860 mW at + 25°C

Storage Temperature
Power Dissipation

= 0 p,A
= 100 p,A
= 750 p,A

0
2.0
15.0

= 750 p,A

3.0

-25°C to + 85°C, Voo

Parameter

Conditions
(Notes 5 and 6)

2.7

= 5V

Min

Typ

Max

Units

500

kHz

fc

Ciock Input Frequency

th

High Time

950

ns

tl

Low Time

950

ns

tos
tOH

Data Input
Set-UpTime
Hold Time

300
300

ns
ns

tOES

Data Enable Input
Set-UpTime

DC

± 0.5V

100
ns
Note 1: Output matching is calculated as the percent variation from IMAX + IMIN/2.
Note 2: With a fixed resistor on the brightness input pin some variation in brightness will occur from one device to another. Maximum brightness input current can
be 2 mA as long as Note 3 and junction temperature equation are compiled with.
Note 3: Absolute maximum for each output should be limited to 40 mA.
Note 4: The VOUT voltage should be regulated by the user.
Note 5: AC input waveform specification for test purpose: tr :s: 20 ns, tf :s: 20 ns, f = 500 kHz, 50% ± 10% duty cycle.
Note 6: Clock input rise and fall times must not exceed 300 ns.

4-62

Functional Description
The MM5481 uses the MM5450 die which is packaged to
operate 2-digit alphanumeric displays with minimal interference to the display and the data source. Serial data transfer
from the data source to the display driver is accomplished
with 2 signals, serial data and clock. Using a format of a
leading" 1" followed by the 35 data bits allows data transfer
without an additional load signal. The 35 data bits are
latched after the 36th bit is complete, thus providing nonmultiplexed, direct drive to the display. Outputs change only
if the serial data bits differ from the previous time. Display
brightness is determined by control of the output current for
LED displays. A 0.001 fLF capacitor should be connected to
brightness control, pin 9, to prevent possible oscillations.

There must be a complete set of 36 clocks or the shift registers will not clear.
When the chip first powers ON an internal power ON reset
signal is generated which resets all registers and all latches.
The START bit and the first clock return the chip to its normal operation.
Figure 5 shows the Output Data Format for the MM5481.
Because it uses only 14 of the possible 34 outputs, 20 of the
bits are 'Don't Cares'. Note that only alternate groups of 4
outputs are used.
Figure :3 shows the timing relationships between data,
clock, and data enable. A maximum clock frequency of
0.5 MHz is assumed.

A block diagram is shown in Figure 1. The output current is
typically 20 times greater than the current into pin 9, which
is set by an external variable resistor. There is an internal
limiting resistor of 400n nominal value.

For applications where a lesser number of outputs are used,
it is possible to either increase the current per output, or
operate the part at higher than 1V VOUT. The following
equation can be used for calculations.

Figure 4 shows the input data format. A start bit of logical
"1" precedes the 35 bits of data. At the 36th clock a LOAD
signal is generated synchronously with the high state of the
clock, which loads the 35 bits of the shift registers into the
latches. At the low state of the clock a RESET signal is
generated which clears all the shift registers for the next set
of data. The shift registers are a static master-slave configuration. There is no clear for the master portion of the first
shift register, thus allowing continous operation.

Tj = (VOUT) (lLED) (No. of segments)(145°C/W)
where:
Tj = junction temperature

+

+ TA

150°C max.

VOUT = the voltage at the LED driver outputs
ILED = the LED current
145°C/W = thermal coefficient of the package
TA = ambient temperature

I F-==~--90r.

CLOCK VH- -

VL-;;;;;=J----'----f"

~--.;f ----;;;;=-1 Or.

DATA ------'\-F=~==~~VH

______

~=-*===_VL

DATA ENABLE

TL/F/6139-3

FIGURE 3. Timing

•

CLOCK

DATA

n

LOAD _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _HSS_ _ _ _ _..I
(INTERNAL)

_ _ _ __

r"lL -

RESET
(iNTERNAL) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-\Ss----------J

TL/F/6139-4

FIGURE 4. Input Data Format

FIGURE 5. Output Data Format

4-63

?-

co
~

~
~

r-------------------------------------------------------------------------------------~

Functional Description

(Continued)

RAW DC

>9V
240n

5kn

TL/F/6139-5

FIGURE 6. Typical Application of Constant Current Brightness Control
5V

TL/F/6139-6

FIGURE 7. Brightness Control Varying the Duty Cycle
Safe Operating Area
1.0

Basic Electronically Tuned Television System

34 SEGMENTS
VOUT =IV
15 mA SEGMENT

~ 0.8

"~
"

z

~ 0.6 t-----+-<~~~""'*"~"""".____I

a..
iii

~

III

c

LED DISPLAY

0.4 t----+--<'"'"

C<:

~

• • • • • •

~ 0.2 1----I---"~~~"'<2i<~~_2__l

14
O'----..J.-,;"-"'-""'""-.::...:....;:w;...;:...::....,...:.....:.....---I

o

20

40

60

80

MM5481
DISPLAY
DRIVER

100

TEMPERATURE (OC)
TL/F/6139-7

KEYBOARD

.---.

TTl
PROCESSOR
(COPS, ETC.)

TL/F/6139-8

4·64

~National

~ Semiconductor
MM5483 Liquid Crystal Display Driver
General Description
The MM5483 is a monolithic integrated circuit utilizing
CMOS metal-gate low-threshold enhancement mode devices. It is available in a 40-pin molded package. The chip can
drive up to 31 segments of LCD and can be cascaded to
increase this number. This chip is capable of driving a 4%digit 7-segment display with minimal interface between the
display and the data source.
The MM5483 stores the display data in latches after it is
latched in, and holds the data until another load pulse is
received

Features

•
•
•
•
•

Wide power supply operation
TTL compatibility
31 segment outputs
Alphanumeric and bar graph capability
Cascade capability

Applications
•
•
•
•
•

COPSTM or microprocessor displays
Industrial control indicator
Digital clock, thermometer, counter, voltmeter
Instrumentation readouts
Remote displays

• Serial data input
• Serial data output

Block and Connection Diagrams
VDD---1~-'"

LOAD -~t------I '---"L~~~:!....~
SERIAL
DATA

_2~-----b~---f3ti~iiiiFifiiE~~

CLOCK

-......;;,;+------1>------.......

-=-

TL/F/6140-1

FIGURE 1
Dual-In-Line Package

vss

OUTPUT BIT 17
OUTPUT BIT 1B
OUTPUT BIT 19
OUTPUT BIT 20
OUTPUT BIT 21
OUTPUT BIT 22
OUTPUT BIT 23
OUTPUT BIT 24
OUTPUT BIT 25
OUTPUT BIT 26
OUTPUT BIT 27
OUTPUT BIT 2B
OUTPUT BIT 29
OUTPUT BIT 30
OUTPUT BIT 31
LOAD
BACKPLANE IN
BACKPLANE OUT
DATA IN
CLOCK IN

OUTPUT BIT 16
OUTPUT BIT 15
OUTPUT BIT 14
OUTPUT BIT 13
OUTPUT BIT 12
OUTPUT BIT 11
OUTPUT BIT 10
OUTPUT BIT 9
OUTPUT BIT B
OUTPUT BIT 7
OUTPUT BIT 6
OUTPUT BIT 5
OUTPUT BIT 4
OUTPUT BIT 3
OUTPUT BIT 2
OUTPUT BIT 1
OATA OUT
OSC IN
VDD

Order Number MM5483N
See NS Package Number N40A

TL/F/6140-2

Top View
FIGURE 2

4-65

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage at Any Pin

300 mW at + 85°C
350 mW at + 25°C

Power Dissipation

+150°C

Junction Temperature

Operating Temperature

VsstoVss + 10V
-40°C to +85°C

Storage Temperature

- 65°C to + 150°C

Lead Temperature
(Soldering, 10 seconds)

300°C

DC Electrical Characteristics
TA within operating range, Voo

= 3.0V to 10V, Vss = OV, unless otherwise specified

Parameter

Max

Units

10

V

9
17
35

15
25
45

IlA
IlA
IlA

1.5

2.5

IlA

0.9

2.0

V
V
V
V

Min

Conditions

Power Supply

Typ

3.0

Power Supply Current

R = 1M,C = 470pF,
Outputs Open
Voo = 3.0V
Voo = 5.0V
Voo = 10.0V
OSC = OV, Outputs Open,
SPIN = 32 Hz, Voo = 3.0V

Input Voltage Levels
Logic "0"
Logic "1"
Logic "0"
Logic "1"

Load, Clock, Data
Voo = 5.0V
Voo = 5.0V
Voo = 3.0V
Voo = 3.0V

Output Current Levels
Segments and Data Out
Sink
Source

Voo
Voo

= 3.0V, VOUT = 0.3V
= 3.0V, VOUT = 2.7V

20
20

Il A
IlA

SPOUT
Sink
Source

Voo
Voo

= 3.0V, VOUT = 0.3V
= 3.0V, VOUT = 2.7V

320
320

IlA
IlA

AC Electrical Characteristics
Symbol

2.4
0.4

Voo ;::: 4.7V, Vss

= OV unless otherwise specified
Min

Parameter

fc

Clock Frequency, Voo

= 3V

tCH

Clock Period High

tCl

Clock Period Low

I
I

tos

Data Set-Up before Clock

tOH
tlW

Typ

Max

Units

500

kHz

500

ns

500

ns

300

ns

Data Hold Time after Clock

100

ns

Minimum Load Pulse Width

500

ns

tLTC

Load to Clock

400

tcoo

Clock to Data Valid

(Notes 1, 2)

ns
400

Note 1: AC input waveform specification for test purpose: t, ,;; 20 ns, tf ,;; 20 ns, f

750

ns

= 500 kHz, 50% ± 10% duty cycle.

Note 2: Clock input rise and fall times must not exceed 300 ns.
Note 3: Output offset voltage is ± 50 mV with CSEGMENT

= 250 pF,

Csp

= 8750

pF.

Functional Description
the number of segments used) of data are clocked into the
MM5483 in a short time frame (with less than 0.1 second
there probably will be no noticeable flicker) with no more
clocks until new information is to be displayed. If data was
slowly clocked in, it can be seen to "walk" across the dis·
play in the 2-wire mode. An AC timing diagram can be seen
in Figure 6. It should be noted that data out is not a TTLcompatible output.

A block diagram for the MM5483 is shown in Figure 1 and a
package pinout is shown in Figure 2. Figure 3 shows a possible 3·wire connection system with a typical signal format
for Figure 3. Shown in Figure 4, the load input is an asynchronous input and lets data through from the shift register
to the output buffers any time it is high. The load input can
be connected to Voo for 2-wire control as shown in Figure
5. In the 2-wire control mode, 31 bits (or less depending on

4-66

Functional Description

(Continued)

8DK

lOAD
DATA

CLOCK

----~---+-----+-

--....

l O A O - - - - - - -.....- - - - - - -.....- -....

TLIF/6140-3

FIGURE 3. Three-Wire Control Mode

lOAD

rI
--.....- -.....- .....- -.....--l~~2-.....- - - - - - ' LTIMETLIF/6140-4

FIGURE 4. Data Format Diagram

LCD DISPLAY

80K

18-22 DATA IN

ClK

21
DATA

25
VOO

-

....------...

CLOCK _-----4~-------

TLIF/6140-5

FIGURE 5. Two-Wire Control Mode

1-ICH--I-ICl-1
CLOCK

-I 1-,,,

I

-I 1-

10'

DATA~
lOAD

I
-IICDO

~m

I-'LW-I -'LTC

1-

j

\ . . .____

___. . .-J}(~-..........-~)(~_______
TL/F/6140-6

FIGURE 6. Timing Diagram

4-67

~

co

~ ~National
~ D Semiconductor
MM5484 16-Segment LED Display Driver
•
•
•
•
•

General Description
The MM5484 is a low threshold N-channel metal gate circuit
using low threshold enhancement and ion implanted depletion devices. The MM5484 is available in a 22-pin molded
package and is capable of driving 16 LED segments.

MM5484 is cascadeable
TTL compatibility
No load signal required
Non multiplex display
2% digit capability-MM5484

Features

Applications

• Serial data input
• Wide power supply operation
• 16 output, 15 mA sink capability

•
•
•
•

COPSTM or microprocessor displays
Instrumentation readouts
Industrial control indicator
Relay driver

Block and Connection Diagrams
16 SEGMENT OUTPUTS

ENABLE o-....--~

DATA
OUT

CLOCK
DATA IN

0------.....1

TL/F/6141-1

FIGURE 1. MM5484

Dual-In-Llne Package
22

013

012
011

D14
D15

010

016

09
ENABLE

DATA DUT

Voo

MM5484

CLOCK IN

Vss

DATA IN
D1

08
07

D2
03

13

06

D4

12

05
TLIF/6141-3

Top View
Order Number MM5484N
See NS Package Number N22A

4-68

Absolute Maximum Ratings
If Militaryl Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Voltage at LED Outputs
Vss - 0.5V to Vss + 12V
Voltage at Other Pins
VSS - 0.5V to Vss + 10V

DC Electrical Characteristics Voo
Parameter

Operating Temperature
Storage Temperature
Maximum Power Dissipation
MM5484
Lead Temperature (Soldering, 10 sec.)

500mW
300°C

= 4.5Vt09V, TA = -40°C to +85°C unless otherwise specified

Conditions

Typ

Min

Supply Voltage

4.5

Units
V

10

mA

2.4

Voo + 0.5

V

0

0.8
±1
7.5

V
fLA
pF

0.5
50

V
V
IJ-A

1.0

V

5

Logic One
Input High Level VIH

Max
9

Supply Current

Logic Zero
Input Low Level VIL
Input Current
Input Capacitance

- 40°C to + 85°C
- 40°C to + 150°C

High or Low Level

OUTPUTS
Data Output Voltage
High Level VOH
Low Level VOL
Segment Off
(Logic Zero on Input)

lOUT = 0.1 mA
lOUT = -0.1 mA
VOUT = 12V
REXT = 400n

Output Current Segment On
(Logic One on Input)
Output Voltage

lOUT = 15 mA
Voo 2 6V

Voo - 0.5

0.5

AC Electrical Characteristics
(See Figure 3.) Voo = 4.5V to 9V, TA = - 40°C to + 85°C unless otherwise specified
Symbol

Parameter

Conditions

Min

Typ

Max

Units

0.5

MHz

fe

Clock Frequency

th

High Time

0.95

IJ-s

t)

Low Time

0.95

IJ-s

tS1

Data Setup Time

0.5

IJ-s

tH1

Data Hold Time

0.5

IJ-s

tS2

Enable Setup Time

0.5

IJ-s

tH2

Enable Hold Time

0.5

IJ-s

Data Out Delay
0.5
tpd
IJ-S
Note 1: Under no condition should the power dissipated by the segment driver exceed 50 mW nor the entire chip power dissipation exceed 500 mW.
Note 2: AC input waveform specification for test purpose: tr ~ 20 ns, tf ~ 20 ns, f = 500 kHz, 50% ± 10% duty cycle.
Note 3: Clock input rise and fall times must not exceed 500 ns.

4·69

Functional Description
The MM5484 is designed to drive LED displays directly. Serial data transfer from the data source to the display driver is
accomplished with 3 signals, DATA IN, CLOCK and ENABLE. The signal ENABLE acts as an envelope and only
while this signal is at a logic '1' do the circuits recognize the
clock signal.

When the ENABLE signal goes to a low (logic zero state),
the contents of the shift register is latched and the display
will show the new data. While new data is being loaded into
the SR the display will continue to show the old data.
For the MM5484, data is output from the serial DATA OUT
pin on the falling edge of clock so cascading is made simple
with race hazards eliminated.

While ENABLE is high, data on the serial data input is transferred and shifted in the internal shift register on the rising
clock edge, i.e. a logic '0' to logic '1' transition.

When the chip first powers on, an internal power on reset
signal is generated which resets the SR and latches to zero
so that the display will be off.

Timing Diagram

CLOCK

ENABLE _ _ _ _ _..1

DATA IN _ _ _ _ _.J

-I

ir'Pd

1 ------""'\"'------

DATA DuT-_ _ _ _ _ _ _ _ _ _ _.....J

FIGURE 3

4-70

TLlF/6141-5

~National

D Semiconductor
MM5486 LED Display Driver
General Description
The MM5486 is a monolithic MOS integrated circuit utilizing
N-channel metal-gate low-threshold, enhancement mode
and ion-implanted depletion mode devices. It is available in
a 40-pin molded dual-in-line package. A single pin controls
the LED display brightness by setting a reference current
through a variable resistor connected to Voo.

Features
•
•
•
•

Continuous brightness control
Serial data inputloutut
External load input
Cascaded operation capability

•
•
•
•

Wide power supply operation
TIL compatibility
33 outputs, 15 rnA sink capability
Alphanumeric capability

Applications
•
•
•
•
•
•

COPSTM or microprocessor displays
Industrial control indicator
Relay driver
Digital clock, thermometer, counter, voltmeter
Instrumentation readouts
Reference MOS Brief # 1

Block and Connection Diagrams

':"

TL/F/6142-1

FIGURE 1
Dual-ln-L1ne Package

Vss

OUTPUT BIT 17
OUTPUT BIT 1B
OUTPUT BIT 19
OUTPUT BIT 20
OUTPUT BIT 21
OUTPUT BIT 22
OUTPUT BIT 23
OUTPUT BIT 24
OUTPUT BIT 25
OUTPUT BIT 26
OUTPUT BIT 27
OUTPUT BIT 2B
OUTPUT BIT 29
OUTPUT BIT 30
OUTPUT BIT 31
OUTPUT BIT 32
OUTPUT BIT 33
LOAD
DATA IN
CLOCK IN

OUTPUT BIT 16
OUTPUT BIT 15
OUTPUT BIT 14
OUTPUT BIT 13
OUTPUT BIT 12
OUTPUT BIT 11
OUTPUT BIT 10
OUTPUT BIT 9
OUTPUT BIT 8
OUTPUT BIT 7
OUTPUT BIT 6
OUTPUT BIT 5
OUTPUT BIT 4
OUTPUT BIT 3
OUTPUT BIT 2
OUTPUT BIT 1
DATA DUT
BRIGHTNESS CONTROL
VDD

Order Number MM5486N
See NS Package Number N40A

TL/F/6142-2

Top View
FIGURE 2
4-71

•

Absolute Maximum Ratings
If Military I Aerospace specified devices are required,
contact the National Semiconductor Sales Officel
Dls!rlbutors for availability and specifications.
Voltage at Any Pin
VSS to Vss + 12V
Operating Temperature
- 25°C to + 85°C
Storage Temperature
- 65°C to + 150°C

560 mW at + 85°C
1Wat + 25°C
+150°C
Junction Temperature
Lead Temperature (Soldering, 10 seconds)
300°C
Power Dissipation

Electrical Characteristics
TA within operating range, Voo = 4.75V to 11.0V, Vss = OV, unless otherwise specified
Symbol

Parameter

Conditions

Power Supply

IOD

Power Supply Current

Excluding Output Loads

VIL
VIH

Input Voltages
Logic "a" Level
Logic "1" Level

± 10 p.,A Input Bias
4.75 ::;: Voo ::;: 5.25

ISR

Brightness Input (Note 2)

10H
10L

Output Sink Current (Note 3)
Segment OFF
Segment ON

Voo> 5.25

10

Maximum Segment Current

VISR

Brightness Input Voltage (Pin 19)

OM

Output Matching (Note 1)

VOL
VOH

Data Output
Logical "0" Level
Logical "1" Level

fc
th
tl

Clock Input
Frequency
High Time
Low Time

tDS
tOH

Data Input
Set-UpTime
Hold Time

Min

Typ

4.75

Voo

-0.3
2.2

Units

11

V

7

mA

0.8
Voo

V
V

Voo-2

Voo

V

a

0.75

mA

10

p.,A

10
4
25

p.,A
mA
mA

40

mA

VOUT = 3.0V
VOUT = 1V (Note 4)
Brightness Input = a p.,A
Brightness Input = 100 p.,A
Brightness Input = 750 p.,A

0
2.0
15

Input Current = 750 p.,A

3.0

lOUT = 0.5mA
lOUT = 100 p.,A

Max

2.7

4.3

V

±20

%

0.4
Voo

V
V

500
950
950

kHz
ns
ns

300
300

ns
ns

Vss
2.4

(Notes 5 and 6)

Data Enable Input
100
ns
Set-UpTime
Note 1: Output matching is calculated as the percent variation (IMAX + IMIN)/2.
Note 2: With a fixed resistor on the brightness input pin, some variation in brightness will occur from one device to another. Maximum brightness input current can
be 2 mA as long as Note 3 and junction temperature equation are complied with.
Note 3: Absolute maximum for each output should be limited to 40 mAo
Note 4: The VOUT voltage should be regulated by the user. See Figures 6 and 7for allowable VOUT vs lOUT operation.
Note 5: AC input waveform specification for test purpose: t, !S: 20 ns, tf !S: 20 ns. f = 500 kHz. 50% ± 10% duty cycle.
Note 6: Clock input rise and fall times must not exceed 300 ns.
tOES

4-72

Functional Description
The MM5486 is specifically designed to operate four-digit
alphanumeric displays with minimal interface with the display and the data source. Serial data transfer from the data
source to the display driver is accomplished with 3 signals,
serial data, clock, and load. The data bits are latched by a
positive-level load signal, thus providing non-multiplexed, direct drive to the display. When load is high, the data in the
shift registers is displayed on the output drivers. Outputs
change only if the serial data bits differ from the previous
time. Display brightness is determined by control of the output current for LED displays. A 0.001 j.LF capacitor should
be connected to brightness control, pin 19, to prevent possible oscillations. The output current is typically 20 times
greater than the current into pin 19, which is set by an external variable resistor. There is an internal limiting resistor of
4000 nominal value.

When the chip first powers ON, an internal power ON reset
signal is generated which resets all registers and latches.
The leading clock returns the chip to its normal operation.
Figure 3 shows the timing relationship between data, clock
and data enable. A maximum clock frequency of 0.5 MHz is
assumed.

For applications where a lesser number of outputs are used,
it is possible to either increase the current per output, or
operate the part at higher than 1V VOUT. The following
equation can be used for calculations:
T J = (V OUT) (I LED) (No. of segments) (124°C/W)

+ TA

where:
TJ = junction temperature

+ 150°C max.

VOUT = the voltage at the LED driver outputs
ILEO = the LED current

A block diagram is shown in Figure 1.
Figure 4 shows the input data format. Bit "1" is the first bit

124°C/W = thermal coefficient of the package
T A = ambient temperature

into the data input pin and it will appear on pin 17. A logical
"1" at the input will turn on the appropriate LED. The load
signal latches the 33 bits of the shift register into the latches. The data out pin allows for cascading the shift registers
for more than 33 output drivers.

The above equation was used to plot Figure 6, Figure 7, and
Figure 8.

£==~-90%
,~_~f

DATA

---"",,==10%

--_J"f\.;=4;;==
TLlF/6142-3

FIGURE 3

LEADING
CLOCK" 1

33

Lrl...rUl-

CLOCK

BIT 32

BIT 1

~~~

LOAD

RESET
(INTERNAL)

BIT 33

i"1

-I

I_____________~I----------TL/F/6142-4

'This leading clock is necessary only after power ON.

FIGURE 4. Input Data Format

Voo
lEADING CLOCK
CLOCK

-----'

--I

1-3oons

RESET _ _ _ _ _ _ _---' ~I'___M_IN_ _ _ __
(INTERNAL)
i1'
~
TL/F/6142-5

FIGURE 5

4-73

Typical Applications
1.0 .-----..,r----r---,.----,.-.....,

2.5

~ 0.8

2.0

z

C>

~

~...

0.6

2i

=>
~

~ 0.4

~

0.2

\1 I~
~t
r~\ ~~
~;

.l1

TA=85°C
Tj = 15~oCI (MAX.)

1-----4~~

20

40

f-

'f ,~

1.0

~~Lt'-

60

80

100

o
o

TEMPERATURE (OCt

- --j

rr

...
...

to-..

...

'"

o
8

12

16

20

24

28

o

5

10

-- - r-.

.......

15

20

FIGURE 7

FIGURES

RAW DC
>9V

TLlF/6142-9

119

tN

= 1k

FIGURE 9. Constant Current Brightness Control

5V

TL/F/6142-10

FIGURE 10. Brightness Control Varying the Duty Cycle

4-74

30

34

TL/F/6142-B

TLlF/6142-7

FIGURE 6

25

NUMBER OF SEGMENTS

ILED (mA)

TLlF/6142-6

1.~V

~I'\.

~

0.5

OL-_L...:...:.'"

o

1.5 r

110
.! I I
TA = 85°C
100
VDUTj1.0V
I
90
I
c
oS 80
VOU{
..
70
r-z
I
I
a:
60 I-VOUT=2V
a:
=>
50
u
Me,x IDUT,,40mA
~
40
......
30
1'... . . .
20
~
10

Typical Applications

(Continued)

Basic Electronically Tuned Radio System
LED DISPLAY

AM
FM

'''BOARD

Il- -11-1

II~ ::11_1

I=L.-----r--r-r----..

PLl
SYNTHESIZER

STATION
OETECT. ETC.

TL/F/6142-11

Duplexing 8 Digits with One MM5486

MM5486

16 21 22 19

20

23

17

CLOCK IN ~----....
DATA IN ~-----.... L......,j'I/IJ'v-...- VDD
BRIGHTNESS
CONTROL

LOAD~-------------~

TL/F/6142-12

-This driver has 7 segments only.

4-75

....o

:g
~

~ National

D Semiconductor
MM58201 Multiplexed LCD Driver
General Description

Features

The MM58201 is a monolithic CMOS LCD driver capable of
driving up to 8 backplanes and 24 segments. A 192-bit RAM
stores the data for the display. Serial input and output pins
are provided to interface with a controller. An RC oscillator
generates the timing necessary to refresh the display. The
magnitude of the driving waveforms can be adjusted with
the Vrc input to optimize display contrast. Four additional
bits of RAM allow the user to program the number of backplanes being driven, and to designate the driver as either a
master or slave for cascading purposes. When two or more
drivers are cascaded, the master chip drives the backplane
lines, and the master and each slave chip drive 24 segment
lines. Synchronizing the cascaded drivers is accomplished
by tying the RC OSC pins together and the BP1 pins together.

•
•
•
•
•

Drives up to 8 backplanes and 24 segment lines
Stores data for display
Cascadable
Low power
Fully static operation

Applications
• Dot matrix LCD driver
• Multiplexed 7-segment LCD driver
• Serial in/Serial out memory

The MM58201 is packaged in a 40-lead dual-in-line package, or 44 lead plastic chip carrier package.

Block Diagram
BACKPLANES

..------------------------~~------~c
RC

SEGMENT

COLUMN ...._ _ _..

CONTROL LOGIC

TL/F/6146-1

FIGURE 1

4-76

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage at Any Pin

Storage Temperature Range

500mW

Operating Voo Range

Vss -0.3Vto VSS +18V

Operating Temperature Range

- 65°C to + 150°C

Package Dissipation

Vss + 7.0V to Vss + 18.0V

Lead Temperature (Soldering,
10 seconds)

O°Cto 70°C

300°C

DC Electrical Characteristics MinImax limits apply across temperature range unless otherwise noted.
Symbol

Parameter

Conditions

Min

Typ

Max

Units

0.3

mA

Icc

Quiescent Supply Current

VIN(1)

Logical "1" Input Voltage

0.45 Voo

Voo +0.3

V

VIN(O)

Logical "0" Input Voltage

Vss-0.3

1.0

V

VOUT(O)

Logical "0" Output Voltage

ISINK = 0.6 mA

0.4

V

IOUT(1)

Logical "1" Output Leakage
Current

VOUT = Voo

0

±10

J.LA

IIN(1)

Logical "1" Input Leakage
Current

VIN = Voo

0

1.0

J.LA

IIN(O)

Logical "0" Input Leakage
Current

VIN = Vss

-1.0

0

J.LA

VTC

Input Voltage

4.5

Voo+0.3

V

10

30

kn

10

kn

±10

mV

Max

Units

VTC

Input Impedance

ZOUT

Output Impedance

Backplane and Segment
Outputs

ZOUT

DC Offset Voltage

Between Any Backplane
and Segment Output

0

AC Electrical Characteristics T A and Voo within operating range unless otherwise noted.
Symbol

• 1j

Parameter

fosc

Oscillator Frequency'

fClKIN

Conditions

Min

Typ

1281)

4001)

Hz

Clock Frequency

DC

100

kHz

tON

Clock Pulse Width

5.0

J.Ls

tOFF

Clock OFF Time

5.0

J.Ls

ts

Input Data Set-Up Time

2.0

J.Ls

tH

Input Data Hold Time

1.0

J.Ls

tACC

Access Time

5.0

J.Ls

tr

Rise Time

Backplane, Segment Outputs
Cl = 2000 pF

60

J.Ls

tf

Fall Time

Backplane, Segment Outputs
Cl = 2000 pF

60

J.Ls

is the number of backplanes programmed.

4-77

.....
0
C'\I

co
Ln
:E
:E

Connection Diagrams
Plastic Chip Carrier

Dual-In-Llne Package

.....

511

CIl

00
CIl

en
CIl

U

0

in in

........
Z

oN

0CIl

>

...,. It)
t<')
in in in

510
59

S6

S16

57

515

S5

S17

56

516

S4

S18

55

511

S19

54
53

511

S3
S2

S20

58

519

N/C

SZO
SZI

52
51
BPI

SZ2

BP8

BP7

5n

BP7

BPI

SZ4

BP6

BP6

VTC

BPS

es

B'4
BP3
BP2

N/C
S21

S1

S22
31

S23
S24
VTC

17
18 19 20 21 22 23 24 25 26 27 28

...,.
D..

III

t<')

D..

III

N

D..

III

D..

III

VI

U

U

;;n~~
u

a:::

RC 05C

to:::I

0

~

~

~

~ :s
c u

I~

c

TL/F/6146-10

Top View

TLlF/6146-2

Top View
FIGURE 2

Order Number MM58201N or MM58201V
See NS Package Number N40A or V44A

Switching Time Waveforms
!----ION----.j
eLK IN

DATA IN. CS

DATA OUT

VALID

VALID

TL/F/6146-3

Backplane Output

Segment Output
D.GaVTC

..!::J
II ~
_~

D.J2VTC - - TLlF/6146-5

TLlF/6146-4

4-78

Functional Description
TABLE I. Backplane Select

A functional diagram of the MM58201 LCD driver is shown
in Figure 1. Connection diagrams are shown in Figure 2.

Number of
Backplanes

SERIAL INPUTS AND OUTPUTS
A negative-going edge on the CS input initiates a frame. The
CS input must then stay low for at least one rising edge of
CLK IN, and may not be pulsed low again for the next 31
clocks. At least one clock must occur while CS is high. If
CLK IN is held at a logic "1 ", CS is disabled. This allows the
signal that drives CS to be used for other purposes when
the MM58201 is not being addressed.

2
3
4
5
6
7
8

CLK IN latches data from the DATA IN input on its rising
edge. Data from the DATA OUT pin changes on the falling
edge of CLK IN and is valid before the next rising edge.

B1

BO

0
0
0

0
1
1
0
0
1
1

1
0
1
0
1
0
1

1
1
1
1

RCOSCPin
This oscillator generates the timing required for multiplexing
the liquid crystal display. The oscillator operates at a frequency that is 41] times the refresh rate of the display,
where 1] is the number of backplanes programmed. Since
the refresh rate should be in the range from 32 Hz to 100
Hz, the oscillator frequency must be:

The first five bits of data following CS are the address bits
(Figure 3). The address selects the column where the operation is to start. Bit 1 is the MSB and bit 5 is the LSB. The
sixth bit is the readlwrite bit. A logic "1" specifies a read
operation and a logic "0" specifies a write operation. The
next 24 bits are the data bits. The first data bit corresponds
to the BP1 row of the display, the second data bit to the BP2
row, and so on. After the eighth and sixteenth data bits, the
column pointer is incremented. When starting address
10110 or 10111 is specified, the column pointer increments
from 10111 to 00000.

1281] :5: fosc :5: 4001]
The frequency of oscillation is related to the external Rand
C components in the following way:

1
fosc = 1.25 RC ± 30%

During a read or write cycle, the LCD segment outputs do
not reflect the data in the RAM. To avoid disrupting the
pattern viewed on the display, the read or write cycle time
should be kept short. Since the LCD turn-on time can be as
little as 30 ms, a clock rate of at least 10kHz would be
required in order to address the entire contents of the RAM
within that time interval. The formula below can be used to
estimate the minimum clock rate:

f

B2

The value used for the external resistor should be in the
range from 10 k!l to 1 M!l.
The value used for the external capacitor should be less
than 0.005 J.LF.

VTC Pin
The VTC pin is an analog input that controls the contrast of
the segments on the LCD. If eight backplanes are being
driven (1] = 8), a voltage of typically 8V is required at 25°C.
The voltage for optimum contrast will vary from display to
display. It also has a significant negative temperature coefficient.

_
30
ClK IN - (tlCD - 7ts)

where ts is the processor's set-up time between each read
or write cycle, and tlCD is the minimum turn-on or turn-off
time of the LCD as specified by the LCD manufacturer.

The voltage source on the VTC input must be of relatively
low impedance since the input impedance of VTC ranges
from 10 k!l to 30 k!l. A suitable circuit is shown in Figure 5.

The DATA OUT output is an open drain N-channel device to
Vss (Figure 4). With an external pull-up this configuration
allows the controller to operate at a lower supply voltage,
and also permits the DATA OUT output to be wired in parallel with the DATA OUT outputs from any other drivers in the
system.

In a standby mode, the VTC input can be set to Vss. This
reduces the supply current to less than 300 J.LA per driver.

BACKPLANE AND SEGMENT OUTPUTS
Connect the backplane and segment outputs directly to the
LCD row and column lines. The outputs are designed to
drive a display with a total ON capacitance of up to 2000 pF.

To program the number of backplanes being driven and the
MIS bit, load address 11000, a write bit, three bits for the
number of backplanes (Table I), and the MIS bit. The remaining 20 data bits will be ignored but it is necessary to
provide 21 more clocks before initiating another frame.

The output structure consists of transmission gates tapped
off of a resistor string driven by VTC (Figure 6).
A critical factor in the lifetime of an LCD is the amount of DC
offset between a backplane and segment signal. Typically,
50 mV of offset is acceptable. The MM58201 guarantees an
offset of less than 10 mY.
The BP1 output is disabled when the MIS bit is set to zero.
This allows the BP1 output from the master chip to be connected directly to it so that synchronizing signals can be
generated. Synchronization occurs once each refresh cycle,
so the cascaded chips are assured of remaining synchronized.

4-79

Functional Description

(Continued)
MUST RISE BY THIS POINT
RISE AT ANY TIME

CLK IN

~ON'T CARE

DATA IN

DATA OUT

I

A4

AJ

A2

Al

AO

I RIW I

OJ

02

01

----------------------------------~~OI1][JO~2:r:0~J~
51

S2

5J

54

S5

56

S1

5.

59

510

511

512

BPI
BP2

I 02J I

022

I 023 I 024
SI.

S19

S20

S21

S22

~ON'T

CARE

S2J

S24

514

SIS

01

09

011

B2

018

Bl

010

SI1

024

513

02

S16

022

--,
I
~

I
-I

I

BPJ

OJ

011

019

BO

BP4

04

012

020

MIS I
J

BPS

05

01J

021

BP6

06

014

022

BP1

07

015

02J

BP8

08

016

024

0
1
1

0

a

0

1
1

0

0

1
1
1

a

1

0

1
1
1
1

A4
AJ
A2
AI
AO

a
0
0
0
0

0
0
0
0
1

a

a

a

a

0
0
1
0

0

0
1
0
0

0
1
0
1

0
1
1

0
0
1
1
0

0

a
1
1
1

0
1
0

a

0
0

0

1
0
1

0
1
0
1
0

0
1
0
1
1

1
0
0
0
0

1

0
0
0
1

1
0
0
1

0

1
0
0
1
1

1
0
1
0
0

1
0
1
0
1

1
0
1
1
0

1
0
I
1
1

~

1
1
0

0
0
TL/F/6146-6

Diagram above shows where data will appear on display if starting address 01100 is specified in data format.

FIGURE 3. Data Format

:J'
rl'''~

TL/F/6146-7

FIGURE 4. DATA OUT Structure

4-80

Functional Description

(Continued)

ISV
COP420l
00

01

SK

so

SI

33k

lOOk

a
15V

15V

CLK
IN

a

ClK
IN

8Ik

OATA OATA
IN
OUT
ISV

MMSI201

RC OSC

RC OSC

MMSI201

~O.OOI"F
":"

BPI-BPI

SI-S24

SI-S24

BPI

24
SEGMENT LINES
I x 41 DDT MATRIX
liQUID CRYSTAL DISPLAY

TL/F/6146-B

FIGURE 5. Typical Application

VTC
SELECT

1
t
T

'}-BACKPlANE OR
SEGMENT OUTPUT

SELECT
TL/F/6146-9

FIGURE 6. Structure of LCD Outputs

4-81

•

~National

D Semiconductor
MM58241 High Voltage Display Driver
General Description

Features

The MM58241 is a monolithic MOS integrated circuit utilizing CMOS metal gate low threshold P- and N-channel devices. It is available both in 40-pin molded dual-in-line packages or as dice. The MM58241 is particularly suited for driving high voltage (60V max) vacuum fluorescent (VF) displays (e.g., a 32-digit alphanumeric or dot matrix display).

•
•
•
•
•
•
•
•
•

Applications
•
•
•
•
•
•

COPSTM or microprocessor-driven displays
Instrumentation readouts
Industrial control indicator
Digital clock, thermostat, counter, voltmeter
Word processor text displays
Automotive dashboards

Direct interface to high voltage display
Serial data input
No external resistors required
Wide display power supply operation
LSTTL compatible inputs
Software compatible with NS display driver family
Compatible with alphanumeric or dot matrix displays
Display blanking control input
Simple to cascade

Block Diagram
OUTPUT
32

B~~~~~ __~_______~

OUTPUT
1

I+--I+-VOIS

DA~~_""--IH

CLOCK -

....--tHi

ENABLE - - - -...
TL/F/5600-1

FIGURE 1

4-82

Absolute Maximum Ratings

E!:
E!:

Operating Conditions
Min

U1

Max

Units

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (VOO)
VSS = OV

4.5

5.5

Voltage at Any Input Pin

Display Voltage (VOIS)

-55

-25

V

Temperature Range

-40

+85

·C

VOO + 0.3V to VSS - 0.3V

Voltage at Any Display Pin

VOO to VOO - 62.5V

0)

N

....
0l:Io

V

62.5V

VOO + IVolsl
Storage Temperature

- 65·C to + 150·C

Power Dissipation

500 mW at + 85·C

Junction Temperature

130·C

Lead Temperature
(Soldering, 10 sec.)

260·C

DC Electrical Characteristics
TA = -40·C to +85°C, VOO = 5V ±0.5V, VSS =

Symbol

ov unless otherwise specified

Parameter
Power Supply Currents

100

lOIS

Conditions

Min

Typ

VIN = Vss or VOO, Vss = OV,
VOIS Disconnected
VOO = 5.5V, Vss = OV, VOIS = -55V
All Outputs Low

Max

Units

150
10

mA

IJ-A

Input Logic Levels
DATA IN, CLOCK
ENABLE, BLANK
VIL
VIH

Logic 'a'
Logic '1'

(Note 1)

VOL
VOH
VOH

Data Output Logic Levels
Logic 'a'
Logic '1'
Logic '1'

lOUT = 400 IJ-A
lOUT = -10 IJ-A
lOUT = - 500 IJ-A

liN

CIN

ROFF

RON

VOOL

Input Currents
DATA IN, CLOCK
ENABLE, BLANK

-10

Display Output Impedances

Voo = 5.5V, Vss = OV
VOIS
VOIS
VOIS
VOIS
VOIS
VOIS

Note 1: 74LSTIL VOH = 2.7V

@

0.4

V
V
V

10

IJ-A

15

pF

400
550
650
4.0
3.7
3.4

kn
kn
kn
kn
kn
kn

VOIS + 4

V

VIN = OV or VOO

Output Off (Figure 3a)

Display Output Low Voltage

V
V

VOO - 0.5
2.8

Input Capacitance
DATA IN, CLOCK
ENABLE, BLANK

Output On (Figure 3b)

0.8
2.4

60
70
80

= -25V
= -40V
= -55V

3.0
2.6
2.3

= -25V
= -40V
= -55V

VOO = 5.5V, lOUT = Open Circuit,
-55V S; VOIS S; -25V

lOUT = -400 ,...A, TIL VOH = 2.4V

@

lOUT = -400,...A.

4-83

VOIS

III

,...
-.:::t

~

Lt)

:!:
:!:

AC Electrical Characteristics TA =
Symbol

Parameter

-40·Cto

+ 85·C, Voo

Conditions

= 5V iO.5V

Typ

Max

Units

800
300
300

kHz
ns
ns

Min

fc
tH
tL

Clock Input
Frequency
High Time
Low Time

tos
tOH

Data Input
Set-UpTime
Hold Time

100
100

ns
ns

tES
tEH

Enable Input
Set-UpTime
Hold Time

100
100

ns
ns

tcoo

Data Output
CLOCK Low to Data Out
Time

(Notes 3 and 4)

CL = 50 pF
500

ns

Note 2: For timing purposes, the signals ENABLE and BLANK can be considered to be totally independent of each other.
Note 3: AC input waveform specification for test purposes: Ir' I, :s; 20 ns, f = 800 kHz, 50% ± 10% duty cycle.
Note 4: Clock input rise and fall times must not exceed 5 ,""s.

Connection Diagrams
Dual-In-Llne Package
VSS(OV)
OUTPUT 17
OUTPUT 16
OUTPUT 15
OUTPUT 14
OUTPUT 13
OUTPUT 12
OUTPUTll
OUTPUT 10
OUTPUT9
OUTPUTS
OUTPUT 7
OUTPUT 6
OUTPUT 5
OUTPUT 4
OUTPUT 3
OUTPUT2
OUTPUTI
VOIS
VOO (5V)

-

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

v

40 ~
39 ~
38 ' 37 36 ~
35
34 ~
33 ~
32 I 31 I 30 I 29 I 28 I 27 I 26 25 24 ~
23 ~
22

OUTPUT 18
OUTPUT 19
OUTPUT 20
OUTPUT 21
OUTPUT 22
OUTPUT 23
OUTPUT 24
OUTPUT 25
OUTPUT 26
OUTPUT 27
OUTPUT 28
OUTPUT 29
OUTPUT 30
OUTPUT 31
OUTPUT 32
BLANKING CONTROL
ENABLE
DATAOUT
DATAIN

21

CLOCK

r-

MM58241

Plastic Chip Carrier

rr-

/

6

5

4

3

2

144 43 42 41 40

OUTPUT 13- 7
OUTPUT 12 -

39

~

OUTPUT 23

38 I- OUTPUT 24

8

~

OUTPUT 11- 9

37

OUTPUT 10 -

10

36 I- OUTPUT 26

OUTPUT 9- 11

35 I- OUTPUT 27

N/C- 12

OUTPUT 25

341- N/C

OUTPUT 8- 13

33 I- OUTPUT 28

OUTPUT 7 -

14

32 - OUTPUT 29

OUTPUT 6 -

15

31 - OUTPUT 30

OUTPUT 5 -

16

30 - OUTPUT 31

OUTPUT 4 -

17

29 - OUTPUT 32
18 19 20 21 22 23 24 25 26 27 28

TLIF/5600-2

Top View
TL/F/S600-8

FIGURE 2

Top View

Order Number MM58241N or MM58241V
See NS Package Number N40A or V44A

Functional Description
to be loaded into the shift register following ENABLE high. A
logic '1' at the input will turn on the corresponding display
digit/segment/dot output.

This product is specifically designed to drive multiplexed or
non-multiplexed high voltage alphanumeric or dot matrix
vacuum fluorescent (VF) displays. Character generation is
done externally in the microprocessor, with a serial data
path to the display driver. The MM58421 uses three signals,
DATA IN, CLOCK and ENABLE, where ENABLE acts as an
external load signal. Display blanking can be achieved by
means of the BLANKING CONTROL input, and a logic '1'
will turn off all sections of the display. A block diagram of
the MM58241 is shown in Figure 1.

A significant reduction in discrete board components can be
achieved by use of the MM58241, because external pulldown resistors are not required. Due to the nature of the
output stage, both its on and off impedance values vary as a
function of the display voltage applied. However, Figures 3a
and 3b show that this output impedance will remain constant for a fixed value of display voltage.

Figure 2 shows the pinout of the MM58241 device, where
output 1 (pin 18) is equivalent to bit 1, i.e., the first bit of data

4-84

Functional Description

(Continued)

Figure 4 demonstrates the critical timing requirements between CLOCK and DATA IN for the MM58241.

new data. During data transfer, the display will show old
data. DATA OUT is also provided on the MM58241, being
output on the falling edge. At any time, the display may be
blanked under processor control, using the BLANKING
CONTROL input.
Figure 6 shows a schematic diagram of a microprocessorbased system where the MM58241 is used to provide the
grid drive for a 32-digit 5 x 7 dot matrix vaccum fluorescent
(VF) display. The anode drive in this example is provided by
another member of the high voltage display driver family,
namely the MM58248, which does not require an externally
generated load signal.

When the chip first powers on, an internal reset is generated, resetting all registers and latches. The chip returns to
normal operation on application of ENABLE, and so all interface signals should be inactive at power on.
In Figure 5, the ENABLE signal acts as an envelope, and
only while this signal is at a logic '1' does the circuit accept
CLOCK input signals. Data is transferred and shifted in the
internal shift register on the rising clock edge, i.e., '0'-'1'
transition. When the ENABLE signal goes low, the contents
of the shift registers are latched, and the display will show
+S5°C· +25°C TYPICAL
59.5
_ 49.5
>

:;; 39.5
~
"+
29.5

~ 19.5
9.5
IK-_ _--'L--_ _- '_ _ _---L_ _ _- ' - _. . .

200

400

600

lOUT (!IA)

BOO

TLlF/5600-3

FIGURE 3a. Output Impedance Off

3.3 kO TYPICAL
AT +25°C, VOIS = -40V
2.3 kO MAX
AT -40°C, YOIS = -55Y

.....L.._.

o . : ; . - - - - l l . -_ _--L_ _ _-L._ _ _
o

lOUT (rnA)
TL/F/5600-4

FIGURE 3b. Output Impedance On

Timing Diagrams

For the purposes of AC measurements, VIH

= 2.4V, VIL = O.8V.

FIGURE 4. Clock and Data Timings

4-85

TL/F/5600-5

....
-.:t"

~

Lt)

:E
:E

Timing Diagrams (Continued)
CLOCK 50% -t--#--t-;-I---I--~----I--~----

DATA IN 50%

-t-if--t--t--+-I--JE-----4------4---

DATA OUT 50%

+--t--+-+----1I-----...- - - - -.....- - -

fEs-+--i+-+IENABLE 50%

B=~~~

+--t----\;:-------~,._-----.:l\_-----

"'1

\

50% - - - -_ _ _ _
VOO

\

-----r---~

DISPLAY
OUTPUT

VOIS---"
TL/F/5600-6

FIGURE 5. MM58241 Timings (Data Format)

Typical Application
32·DIGIT MULTIPLEXED
5 x 7 DOT MATRIX
VACUUM FLUORESCENT
(VF) DISPLAY

;

.-L

25.!~~s..1

------32 GRIDS

MM58248
DISPLAY DRIVER

CLOC K8

~

MM58241
DISPLAY DRIVER

t

DATA8

DATAl
CLDCK 1

J

ENABLE 1

I

BLANK 1

I

MICROPRDCESSDR

DATA
DUT 1
TL/F/5600-7

FIGURE 6. Microprocessor-Controlled Word Processor

4-86

~National

D Semiconductor
MM58242 High Voltage Display Driver
General Description

Features

The MM58242 is a monolithic MOS integrated circuit utilizing CMOS metal gate low threshold P and N-channel devices. It is available both in 2S-pin molded dual-in-line packages or as dice. The MM58242 is particularly suited for driving high voltage (60V max) vacuum fluorescent (VF) displays (e.g., a 20-digit alphanumeric or dot matrix display).

IJ Direct interlace to high voltage display
II Serial data input
• No external resistors required
• Wide display power supply operation
II LSTTL compatible inputs
• Software compatible with NS display driver family
• Compatible with alphanumeric or dot matrix displays
• Display blanking control input
• Simple to cascade

Applications
•
•
•
•
•
•

COPSTM or microprocessor-driven displays
Instrumentation readouts
Industrial control indicator
Digital clock, thermostat, counter, voltmeter
Word processor text displays
Automotive dashboards

Block Diagram
OUTPUT
20

BLANKING CONTROL

1------.....

....

OUTPUT
1

I+--K-VOIS

CLOCK -"'---l~

ENABLE

----...I
TL/F17924-1

FIGURE 1

4-87

Absolute Maximum Ratings

Operating Conditions

If PJlllltary/Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Voltage at Any Input Pin
Voo + 0.3Vto VSS -0.3V
Voltage at Any Display Pin
VOO to VOO -62.5V
62.5V
VOO +Ivoisl
Storage Temperature
-65°C to + 150°C
Power Dissipation
500 mW at + 85°C
Junction Temperature
130°C
Lead Temperature (Soldering, 10 sec.)
260°C

Supply Voltage (Voo)
VSS = OV
Display Voltage (VOIS)
Temperature Range

Min

Max

Units

4.5
-55
-40

5.5
-25

V
V
°C

+85

DC Electrical Characteristics
TA = -,40°C to + 85°C, VOO = 5V ±0.5V, VSS = OV unless otherwise specified
Symbol
100

Parameter

Power Supply Currents

lOIS

Conditions

Min

VIN = Vss or Voo, Vss = OV, VOIS Disconnected
VOO = 5.5V, VSS = OV, VOIS = 55V
All Outputs Low

VIL
VIH

Input Logic Levels
DATA IN, CLOCK
ENABLE, BLANK
Logic '0'
Logic '1'

(Note 1)

VOL
VOH
VOH

Data Output Logic Levels
Logic '0'
Logic '1'
Logic '1'

lOUT = 400,...A
lOUT = -10,...A
lOUT = - 500 ,...A

Voo-0.5
2.8

VIN = OV or VOO

-10

liN

Input Currents
DATA IN, CLOCK
ENABLE, BLANK

CIN

Input Capacitance
DATA IN, CLOCK
ENABLE, BLANK

ROFF

Display Output Impedances
Output Off (Figure 3a)

RON

Output On (Figure 3b)

VOOL

Display Output Low Voltage

Note 1:

Typ

Voo =
VOIS =
VOIS =
VOIS =
VOIS =
VOIS =
VOIS =

Max

Units

150
10

,...A
mA

0.8

V
V

0.4

V
V
V

10

,...A

15

pF

400
550
650
4.0
3.7
3.4

kn
kn
kn
kn
kn
kn

VOIS+4

V

2.4

5.5V, Vss = OV
-25V
-40V
-55V
-25V
40V
-55V

VOO = 5.5V, lOUT = Open Circuit,
-55V ~ VOIS ~ -25V

74LSTTL VOH = 2.7V @ lOUT = -400 /LA, TTL VOH = 2.4V @ lOUT = -400/LA.

4-88

60
70
80
3.0
2.6
2.3
VOIS

AC Electrical Characteristics TA =
Parameter

-40·Cto

+ 85·C, Voo

Q)

Typ

Min

Conditions

:s:
:s:
U1

= 5V ±0.5V

Max

Units

N

.;..
N

Clock Input
Frequency, fe
High Time, tH
Low Time, tL

(Notes 3 and 4)
800

Data Input
Set·Up Time, tos
Hold Time, tOH
Enable Input
Set·Up Time, tES
Hold Time, tEH

(Note 2)

Data Output
CLOCK Low to Data Out
Time, teoo

CL = 50 pF

300
300

kHz
ns
ns

100
100

ns
ns

100
100

ns
ns
500

ns

Note 2: For timimg purposes. the signals ENABLE and BLANK can be considered to be totally independent of each other.
Note 3: AC input waveform specification for test purposes: t,. :5: 20 ns, tf :5: 20 ns, f = 800 kHz, 50% ± 10% duty cycle.
Note 4: Clock input rise and fall times must not exceed 5 /Ls.

Connection Diagrams
Dual-In-Line Package
Vss (OV)_ 1

u

OUTPUT 11_ 2

Plastic Chip Carrier

28 -

OUTPUT 12

27 _

OUTPUT 13

e
I-

;:)

OUTPUT 10 _

3

26

~

OUTPUT 14

OUTPUT 9 _

4

25

~

OUTPUT 15

OUTPUT 8 _

5

24

~

OUTPUT 16

OUTPUT 7 -

6

23

~

OUTPUT 6 -

7

22

~

MM58242

en
l-

;:)

-

l;:)

1= 1= 1=

I'

~

~

:!

I-

l-

I-

;:)

VI
VI

;:)

;:)

1= 1= 1=
;:)

;:)

;:)

0

0

0

I

I

I

;:)

;:)

0

0

I

I

I

I

4

3

2

1 28 27 26

;:)

o >

OUTPUT 8 -

5

25 - OUTPUT 15

OUTPUT 7 -

6

24 - OUTPUT 16

OUTPUT 17

OUTPUT 6 -

7

OUTPUT 18

OUTPUT 5- 8

OUTPUT 5 -

8

21 -

OUTPUT 19

OUTPUT 4 -

9

20 -

OUTPUT 20

OUTPUT 3 -

10

19 -

BLANKING CONTROL

OUTPUT 2 -

11

18 -ENABLE

OUTPUT 1 -

12

17

~DATA

VDlS -

13

16

~DATAIN

Voo (5V) -

14

15 ~ CLOCK

23 - OUTPUT 17
t.lt.l58242V

22 - OUTPUT 18

OUTPUT 4- 9

21 - OUTPUT 19

OUTPUT 3- 10

20 - OUTPUT 20
19 i- BLANKING CONTROL

OUTPUT 2- 11

12 13 14 15 16 17 18

OUT
TL/FI7924-B

Top View
Order Number MM58242V
See NS Package Number V28A

~------~
TLlF17924-2

Top View
FIGURE 2
Order Number MM58242N
See NS Package Number N28B

4-89

C\I
~

~
II)
:E
:E

Functional Description
This product is specifically designed to drive multiplexed or
non-multiplexed high voltage alphanumeric or dot matrix
vacuum fluorescent (VF) displays. Character generation is
done externally in the microprocessor, with a serial data
path to the display driver. The MM58242 uses three signals,
DATA IN, CLOCK and ENABLE, where ENABLE acts as an
external load signal. Display blanking can be achieved by
means of the BLANKING CONTROL input, and a logic '1'
will turn off all sections of the display. A block diagram of
the MM58242 is shown in Figure 1.

When the chip first powers on, an internal reset is generated, resetting all registers and latches. The chip returns to
normal operation on application of ENABLE, and so all interface signals should be inactive at power on.

Figure 2 shows the pinout of the MM58242 device, where
output 1 (pin 12) is equivalent to bit 1 (Le., the first bit of data
to be loaded into the shift register following ENABLE high).
A logic '1' at the input will turn on the corresponding display
digit/segment/dot output.

In Figure 5, the ENABLE signal acts as an envelope, and
only while this signal is at a logic '1' does the circuit accept
CLOCK input signals. Data is transferred and shifted in the
internal shift register on the rising clock edge, Le., '0'- '1'
transition. When the ENABLE signal goes low, the contents
of the shift registers are latched, and the display will show
new data. During data transfer, the display will show old
data. DATA OUT is also provided on the MM58242 being
output on the falling edge. At any time, the display may be
blanked under processor control, using the BLANKING
CONTROL input.

A significant reduction in discrete board components can be
achieved by use of the MM58242, because external pulldown resistors are not required. Due to the nature of the
output stage, both its on and off impedance values vary as a
function of the display voltage applied, However, Figures 3a
and 3b show that this output impedance will remain constant for a fixed value of display voltage.

Figure 6 shows a schematic diagram of a microprocessorbased system where the MM58242 is used to provide the
grid drive for a 40-digit 2 line 5 x 7 multiplexed vacuum
fluorescent (VF) display. The anode drive in this example is
provided by another member of the high voltage display
driver family, namely the MM58248, which does not require
an externally generated load signal.

Figure 4 demonstrates the critical timing requirements between CLOCK and DATA IN for the MM58242.

+BS'C

+25'C TYPICAL

59.5
_ 49.S
>

::;; 39.5
~

+29.S

~ 19.5
9.S
~----~------~------~----~--~IO~(~)

200

400

600

BOO
TLIF/7924-3

FIGURE 3a. Output Impedance Off
3.3 kO TYPICAL
AT +2S'C, VDlS = -40V
2.3 kOMAX
AT -40'C, VDlS = -55V

o -=::.____.........______....L..._ _ _ _ _ _L...-____

~

__. . .

o

lo~

(mA)
TLIF/7924-4

FIGURE 3b. Output Impedance On

4-90

Timing Diagrams

TLlF/7924-5

For the purposes of AC measurement, VIH

=

2.4V, VIL

=

O.BV.

FIGURE 4. Clock and Data Timings
CLOCK 50%

-I----,#--+-~___f-___,f---~--~L-----..:~---

DATA IN 50% -+-.......+--+-+---+__- - - - - - - l.....- - - - - - I t - -

DATA OUT 50% - I - - i - - + - - I - - I f - - - - - " I I - - - - - - i l i - - -

10-;'-'1-"~M~ 5O%~-+-~------~~--~~----

B~~~~

-Ir=\"'_______

50% _ _ _ _ _ _ _

Voo

-----r---'"'\.

DISPLAY
OUTPUT

VINS---"
Tl/F17924-6

FIGURE 5. MM58242 Timings (Data Format)

Typical Application
40·DIGIT BY 2·UNE
5 x 7 MULTIPLEXED
DOT MATRIX VACUUM
FLUORESCENT (VF)
DISPLAY

----

CLOCK 8

I

I
I

----

35
ANODES

MM58248
DISPLAY
DRIVER 1

I

20
GRIDS

I I
DATA 81

20
GRIDS

----

35
ANODES

I

MM58248
DISPLAY
DRIVER 2

MM58242
DISPLAY
DRIVER 1

----

~.
OUT

I

II-DATA 82
DATA 22

MM58242
DISPLAY
DRIVER 2

I

I

CLOCK 2
DATA 21
MICROPROCESSOR

ENABLE
BLANK

Tl/F/7924-7

FIGURE 6. Microprocessor-Controlled Word Processor

4-91

~National

U Semiconductor
MM58248 High Voltage Display Driver
General Description

Features

The MM58248 is a monolithic MOS integrated circuit utilizing CMOS metal gate low threshold P~ and N-channel devices. It is available both in 40-pin molded dual-in-line packages or as dice. The MM58248 is particularly suited for driving high voltage (60V max) vacuum fluorescent (VF) displays (e.g., a 5 x 7 dot matrix display).

•
•
•
•
•
•
•
•

Applications
•
•
•
•
•
•

COPSTM or microprocessor-driven display
Instrumentation readouts
Industrial control indicator
Digital clock, thermostat, counter, voltmeter
Word processor text displays
Automotive dashboards

Direct interface to high voltage display
Serial data input
No external resistors required
Wide display power supply operation
LSTIL compatible inputs
Software compatible with NS display driver family
Compatible with alphanumeric or dot matrix displays
No load signal required

Block Diagram
OUTPUT

OUTPUT

35

1

1+-----11+-- VDlS

DATA IN

CLOCK

TLIF/5599-1

FIGURE 1

4-92

Absolute Maximum Ratings
If Military I Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.

Junction Temperature
Lead Temperature
(Soldering, 10 seconds)

Voltage at Any Input Pin
Voltage at Any Display Pin

Operating Conditions

Voo + IVolsl
Storage Temperature
Power Dissipation

Voo + 0.3V to VSS - 0.3V
Voo to Voo - 62.5V
62.5V
- 65°C to + 150°C
500 mW at + 85°C

Supply Voltage (Voo)
VSS = OV
Display Voltage (VOIS)
Temperature Range

130°C
260°C

Min

Max

Units

4.5
-55
-40

5.5
-25

V
V
°C

+85

DC Electrical Characteristics
TA = -40°C to + 85°C, Voo = 5V ±0.5V, VSS = OV unless otherwise specified
Symbol
100

Max

Units

VIN = VSS or Voo, VSS = OV,
VOIS Disconnected

150

,..,A

Voo = 5.5V, Vss = OV,
VOIS = -55V, All Outputs Low

10

mA

0.8

V

Parameter

Min

Conditions

Power Supply Currents

lOIS
VIL

Input Logic Levels
DATA IN, CLOCK Logic '0'

VIH

Input Logic Levels
DATA IN, CLOCK Logic '1'

(Note 1)

liN

Input Currents, DATA IN, CLOCK

VIN = OV or Voo

CIN

Input Capacitance, DATA IN, CLOCK

ROFF

Display Output Impedances
Output Off (Figure 3a)

Voo = 5.5V, VSS = OV
VOIS = -25V
VOIS = -40V
VOIS = -55V

Display Output Impedances
Output on (Figure 3b)

Voo = 5.5V, VSS = OV
VOIS = -25V
VOIS = -40V
VOIS = -55V

RON

-10

Parameter

Conditions

Clock Input Frequency

(Notes2,3)

tH

Clock Input High Time

tL

Clock Input Low Time

tos

Data Input Setup Time

Min

300

CL = 50 pF
~

,..,A

15

pF

400
550
650

kn
kn
kn

4.0
3.7
3.4

kn
kn
kn

VOIS + 4

V

3.0
2.6
2.3
VOIS

-40°C to + 85°C, VOO = 5V ±0.5V

fc

Data Input Hold Time
tOH
Note 2: AC input waveform specification for test purposes: tr, tf
Note 3: Clock input rise and fall times must not exceed 5 /Ls.

10

60
70
80

Display Output
Voo = 5.5V, lOUT = Open Circuit,
Low Voltage
-55V ::;; VOIS ::;; -25V
Note 1: 74LSTTL VOH = 2.7V @ lOUT = -400 /LA, TTL VOH = 2.4V @ lOUT = -400/LA.

Symbol

V

2.4

VOOL

AC Electrical Characteristics TA =

Typ

Max

Units

1.0

MHz
ns

300

ns

100

ns

100
20 ns, f = 1 MHz, 50% ± 10% duty cycle.

4·93

Typ

ns

co
~

C\I

co
LI)
::::E
::::E

Connection Diagrams
Dual-In-Llne Package
Vss (OV)
OUTPUT 17
OUTPUT 16
OUTPUT 15
OUTPUT 14
OUTPUT 13
OUTPUT 12
OUTPUT 11
OUTPUT 10
OUTPUT 9
OUTPUT 8
OUTPUT 7
OUTPUT 6
OUTPUT 5
OUTPUT 4
OUTPUT 3
OUTPUT 2
OUTPUT 1
VoIS

VDD (5V)

40
39
38
37
36
35
34
33
10
11
12
13
14
15
16
17
18
19
20

MM58248

21

Plastic Chip Carrier
OUTPUT 18
OUTPUT 19
OUTPUT 20
OUTPUT 21
OUTPUT 22
OUTPUT 23
OUTPUT 24
OUTPUT 25
OUTPUT 26
OUTPUT 27
OUTPUT 28
OUTPUT 29
OUTPUT 30
OUTPUT 31
OUTPUT 32
OUTPUT 33
OUTPUT 34
OUTPUT 35
OATA IN

:!

~ ~

~

~ ~

::>

::>
o

f!:

0

N

~ ~ ~ N N
~ ~ ~ ~ ~

f!: f!: '" ()
::>
0
>"' .......
z

!5
0

f!: ::>
f!: f!:
o ::>
0

::>
0

!5
0

OUTPUT 13

OUTPUT 23

OUTPUT 12

OUTPUT 24

OUTPUT 11

OUTPUT 25

OUTPUT 10

OUTPUT 26

OUTPUT 9

OUTPUT 27

Nle

Nlc

CLOCK

OUTPUT 8

OUTPUT 28

OUTPUT 7

OUTPUT 29

OUTPUT 6

OUTPUT 30

OUTPUT 5

OUTPUT 31

OUTPUT 4

OUTPUT 32

_

V)

a

(.)

~

~~~;!S>c';?g

!5 !5 !5

TL/F/5599-2

d

000

Top View

2;

....
'" '" '"'"
U"I

~ ~ ~ ~

~

!5
0

f!:

::>
0

!5
0

TL/F/5599-8

Order Number MM58248N
See NS Package Number N40A

Top View
Order Number MM58248V
See NS Package Number V44A
FIGURE 2

Functional Description
normal operation on application of the start bit and the first
clock pulse, and so all interface signals should be inactive
at power on.

This product is specifically designed to drive multiplexed or
non-multiplexed high voltage alphanumeric or dot matrix
vacuum fluorescent (VF) displays. Character generation is
done externally in the microprocessor, with a serial data
path to the display driver. The MM58248 uses two signals,
DATA IN and CLOCK, with a format of a leading '1' followed
by the 35 data bits, hence allowing data transfer without an
additional signal. A block diagram of the MM58248 is shown
in Figure 1.

In Figure 5, a start bit of logic '1' precedes the 35 bits of
data, each bit being accepted on the rising edge of CLOCK,
i.e., a '0'-'1' transition. At the 36th clock, a LOAD signal is
generated synchronously with the high state of the clock,
thus loading the 35 bits of the shift register into the latches.
At the low state of the clock, a RESET Signal is generated,
clearing all bits of the shift register for the next set of data.
Hence, a complete set of 36 clock pulses is needed for the
MM58248, or the shift register will not clear. If, at any given
time, it is required that the display be cleared under microprocessor control, i.e., without power on reset, then the following flushing routine may be used. Clock in 36 'zeroes',
followed by a 'one' (start bit), followed by 35 'zeroes'. This
procedure will completely blank the display.

Figure 2 shows the pinout of the MM58248 device, where
output 1 (pin 18) is equivalent to bit 1, i.e., the first bit of data
to be loaded into the shift register following the start bit. A
logic '1' at the input will turn on the corresponding display
digit/segment/dot output.

A significant reduction in discrete board components can be
achieved by the use of the MM58248, because external
pull-down resistors are not required. Due to the nature of
the output stage, both its on and off impedance values vary
as a function of the display voltage applied. However, Figures 3a and 3b show that this output impedance will remain
constant for a fixed value of display voltage.

Figure 6 shows a schematic diagram of a microprocessorbased system where the MM58248 is used to provide the
anode drive for a 32-digit 5 x 7 dot matrix vacuum fluorescent (VF) display. The grid drive in this example is provided
by another member of the high voltage display driver family,
namely the MM58241, which has the additional features of
a BLANKING CONTROL pin, a DATA OUT pin, and an
ENABLE (external load signal) pin.

Figure 4 demonstrates the critical timing requirements between CLOCK and DATA IN for the MM58248.

When the chip first powers on, an internal reset is generated, resetting all registers and latches. The chip returns to

4-94

Functional Description

(Continued)
+B5°C

+25°C TYPICAL

59.5
E49.5
~39.5
.f;

+29.5

~

19.5
9.5
K -_ _----'_ _ _---'-_ _ _........_ _ _- ' - _ .

400

200

600

lOUT (pA)

BOO
TLiF/5599-3

FIGURE 3a. Output Impedance Off

3.3 kO TYPICAL
AT +25°C, VOIS = -40V
2.3 kO MAX
AT -40°C, VOIS = -55V

....1.-_.

o ..::;.__-...1._ _ _........1-_ _ _........_ _ _
o

lOUT (rnA)
TLiF/5599-4

FIGURE 3b. Output Impedance On

Timing Diagrams

For the purposes of AC measurement, VIH

TLIF/5599-5

= 2.4V, VIL = O.BV.

FIGURE 4. Clock and Data Timings

ClK 35

START
ClK

ClK 1

CLK 2

ClK 3

ClK 33

ClK 34

ClK 35

START
ClK

CLOCK

DATA IN

n
n

lOADJl1..._ _ _ _ _ _ _ _ _ _ _ _..,/11_______..
(INTERNAL)
RESET
(INTERNAL)

..._____

FI
-oJ I...__________...,~--------..

/

...____

~~~;~'----------..,,.------...1
VOIS

TL/F/5599-6

FIGURE 5. MM58248 Timings (Data Format)
4-95

co

-.:t

~
an
:E
:E

Typical Applications
32-DIGIT MULTIPLEXED
5 x 7 DOT MATRIX
VACUUM FLUORESCENT
(VF) DISPLAY

;
~

25~!!!!~S-i

32 GRIDS

~------

MM58248
DISPLAY DRIVER

CLOC KS'

,

MM58241
DISPLAY DRIVER

t

DATA 8

DATAl
CLOCK 1

J

ENA8LE 1

I

BLANK 1

I

MICROPROCESSOR

DATA
OUT 1
TL/F/5599-7

FIGURE 6. Microprocessor-Controlled Word Processor

4-96

~National

~ Semiconductor
MM58341 High Voltage Display Driver
General Description

Features

The MM58341 is a monolithic MOS integrated circuit utilizing CMOS metal gate low threshold P and N-channel devices. It is available both in 40-pin molded dual-in-line packages or as dice. The MM58341 is particularly suited for driving high voltage (35V max) vacuum fluorescent (VF) displays, (e.g., a 32-digit alphanumeric or dot matrix display).

•
•
•
•
•
•
•
•
•

Applications
•
•
•
•
•
•

COPSTM or microprocessor-driven displays
Instrumentation readouts
Industrial control indicator
Digital clock, thermostat, counter, voltmeter
Word processor text displays
Automotive dashboards

Direct interface to high voltage display
Serial data input
No external resistors required
Wide display power supply operation
LSTTL compatible inputs
Software compatible with NS display driver family
Compatible with alphanumeric or dot matrix displays
Display blanking control input
Simple to cascade

Block Diagram
OUTPUT
32

OUTPUT
1

I+-of+-VOIS

OA~~_+lI-""

CLOCK --+11-....

ENABLE _ _ _ _-oJ
TLIF/5603-1

FIGURE 1

4-97

Operating Conditions

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage at Any Input Pin
VOO + 0.3V to VSS - 0.3V
Voltage at Any Display Pin
VOO to VOO - 36.5V
36.5V
VOO + IVolsl
Storage Temperature
- 65·C to + 150·C
Power Dissipation
500 mW at + 85°C
Junction Temperature
130°C
260·C
Lead Temperature (Soldering, 10 seconds)

Supply Voltage (Voo)
VSS = OV
Display Voltage (VOIS)
Temperature Range

Min

Max

Units

4.5
-30
-40

5.5
-10

V
V
·C

+85

DC Electrical Characteristics
TA = -40·Cto +85°C, VOO = 5V ±0.5V, VSS = OV unless otherwise specified
Symbol
100

Max

Units

VIN = VSS or VOO, Vss = OV,
VOIS Disconnected

150

/LA

VOO = 5.5V, VSS = OV,
VOIS = -30V, All Outputs Low

10

rnA

0.8

V

Parameter

Conditions

Power Supply Currents

lOIS
VIL

Input Logic Levels DATA IN,
CLOCK ENABLE, BLANK Logic '0'

VIH

Input Logic Levels DATA IN,
CLOCK ENABLE, BLANK Logic '1'

(Note 1)

VOH

Data Output Logic Levels
Logic '0'

lOUT = 400 /LA

VOH

Data Output Logic Levels
Logic '1'

lOUT = -10/LA

VOH

Data Output Logic Levels
Logic '1'

lOUT = - 500 /LA

liN

Input Currents DATA IN,
CLOCK ENABLE, BLANK

VIN = OV or VOO

CIN

Input Capacitance DATA IN,
CLOCK ENABLE, BLANK

ROFF

Display Output Impedances
Output Off (Figure 3a)

RON

VOOL

Display Output Impedances
Output On (Figure 3b)

VOO =
VOIS =
VOIS =
VOIS =

=

2.7V @ lOUT

=

Typ

V

2.4

5.5V, VSS = OV
-10V
-20V
-30V

0.4

VOO = 5.5V, lOUT = Open Circuit,
-30V ~ VOIS ~ -10V
-400 "A, TTL VOH = 2.4V @ lOUT = -400 "A.

4-98

V

VOO - 0.5

V

2.8

V

-10

55
60
65
700
600
500

VOIS = -10V
VOIS = -20V
VOIS = -30V

Display Output Low Voltage

Note 1: 74LSTTL VOH

Min

VOIS

10

/LA

15

pF

250
300
400

kn
kn
kn

800
750
680

n
n
n

VOIS + 2

V

AC Electrical Characteristics TA =
Symbol

Parameter

-40°C to

+

Conditions

3:
3:

85°C,Voo = 5V ±0.5V
Min

Typ

U1

Max

Units

800

kHz

fc

Clock Input Frequency

(Notes 3, 4)

tH

Clock Input High Time

300

ns

tL

Clock Input Low Time

300

ns

tos

Data Input Setup Time

100

ns

tOH

Data Input Hold Time

100

ns

tES

Enable Input Setup Time

100

ns

tEH

Enable Input Hold Time

100

ns

tcoo

Data Output Clock Low to
Data Out Time

CL = 50 pF

500

ns

Note 2: Note that, for timing purposes, the signals ENABLE and BLANK can be considered to be totally independent 01 each other.
Note 3: AC input waveform specification lor test purpose: tr ~ 20 ns, tf ,,:; 20 ns, I
Note 4: Clock input rise and fall times must not exceed 5 ,,"S.

Connection Diagrams

Functional Description
This product is specifically designed to drive multiplexed or
non-multiplexed high voltage alphanumeric or dot matrix
vacuum fluorescent (VF) displays. Character generation is
done externally in the microprocessor, with a serial data
path to the display driver. The MM58341 uses three signals,
DATA IN, CLOCK and ENABLE, where ENABLE acts as an
external load signal. Display blanking can be achieved by
means of the BLANKING CONTROL input, and a logic '1'
will turn off all sections of the display. A block diagram of
the MM58341 is shown in Figure 1.
Figure 2 shows the pinout of the MM58341 device, where
output 1 (pin 18) is equivalent to bit 1 (i.e., the first bit of data
to be loaded into the shift register following ENABLE high).
A logic '1' at the input will turn on the corresponding display
digit/segment/dot output.
A significant reduction in discrete board components can be
achieved by use of the MM58341, because external pulldown resistors are not required. Due to the nature of the
output stage, both its on and off impedance values vary as a
function of the display voltage applied. However, Figures 3a
and 3b show that this output impedance will remain constant for a fixed value of display voltage.
Figure 4 demonstrates the critical timing requirements between CLOCK and DATA IN for the MM58341.
When the chip first powers on, an internal reset is generated, resetting all registers and latches. The chip returns to
normal operation on application of ENABLE, and so all interface signals should be inactive at power on.
In Figure 5, the ENABLE signal acts as an envelope, and
only while this signal is at a logic '1' does the circuit accept
CLOCK input signals. Data is transferred and shifted in the
internal shift register on the rising clock edge, i.e., '0'-'1'
transition. When the ENABLE signal goes low, the contents
of the shift registers are latched, and the display will show
new data. During data transfer, the display will show old
data. DATA OUT is also provided on the MM58341, being
output on the falling edge. At any time, the display may be
blanked under processor control, using the BLANKING
CONTROL input.
Figure 6 shows a schematic diagram of a microprocessorbased system where the MM58341 is used to provide the
grid drive for a 32-digit 5 x 7 dot matrix vacuum fluorescent
(VF) display. The anode drive in this example is provided by
another member of the high voltage display driver family,
namely the MM58348, which does not require an externally
generated load signal.

Dual-In-Line Package
'-"

Vss(OV) 1
OUTPUT17 2
OUTPUT16-3
OUTPUT15 4
OUTPUT14 5
OUTPUT13 OUTPUT12 -

MM58341

OUTPUT8 - "
OUTPUT 1 12
OUTPUT6 - 1 3
OUTPUT5 14
OUTPUT4 15
OUTPUT3 16
OUTPUT2 - 1 7
OUTPUTl-18
VOls-19
Voo(5V) -

OUTPUT 18
OUTPUT19
OUTPUT20
OUTPUT21
OUTPUT22

351-- OUTPUT23
34t- OUTPUT24
331-- OUTPUT25
321- OUTPUT26
311-- OUTPUT21
301- OUTPUT 28
2 9 - OUTPUT29
28-0UTPUT30
21 r- OUTPUT31
26t- OUTPUT32
25 I-- 8LANKING CONTROL
24 t - ENABLE
23 I- DATA OUT
22 I-- DATA IN

6
7

OUTPUT" 8
OUTPUT1D-9
OUTPUT 9 10

I--

39t381-31t361--

40

211- CLOCK

20

TLIF/5603-2

Top View
Order Number MM58341N
See NS Package Number N40A
Plastic Chip Carrier
~ ~
~ ~ 555
~~55
~~55555
a a a > z a a a a a

~ ~

a
/

I

I

I

I

I

I

I

I

6

5

4

3

2

1 44 43 42 41 40

I

I

I
39 ~ OUTPUT 23

OUTPUT 13- 7
OUTPUT 12 -

8

38 ~ OUTPUT 24

OUTPUT 11 -

9

371- OUTPUT 25
36 ~ OUTPUT 26

OUTPUT 10- 10

35 f- OUTPUT 27

OUTPUT 9- 11
N/C- 12

t.lt.I58341V

34f-N/C

OUTPUT 8- 13

33 I- OUTPUT 28

OUTPUT 7- 14

32 f- OUTPUT 29

OUTPUT 6- 15

31 I- OUTPUT 30

OUTPUT 5- 16

30 I- OUTPUT 31

OUTPUT 4 -

17

29 f- OUTPUT 32
18 19 20 21 22 23 24 25 26 27 28

I
..,.,

I
N

I

I

.-

CIl

5 5 5

>0

5a 5a 5a

I

I

0

(J

>0 ~

I

I

I

t-

L&J

d ~ ~

Q

::::.:::

I

:z

= 800 kHz, 50% ± 10% duty cycle.

I

o-J

g ~ 5 ~ ~~
CI

~8

CD

TLIF/5603-B

Top View
Order Number MM58341V
See NS Package Number V44A

4-99

co
w

.....
~

Functional Decription

(Continued)

+85'C
-40'C

34.5
~ 24.5

+
.J: 14.5
~~----JI-----L

100

_ _....J.._ _-L._ _....L..._ _..J....,~ lOUT

200

300

400

500

(pAl

600
TL/F/S603-3

FIGURE 3a. Output Impedance Off

6000 TYPICAL
AT +25'C, VOIS = -20V

1.0

~

~

4000 MAX
AT -40'C, VOIS = -30V
0.5

_""'"-_---L._ _ _..L-_ _---'_ _ _.....L.._ _ _•

0.5

IOUTI,",,)

1.5
TL/F/S603-4

FIGURE 3b. Output Impedance On

Timing Diagrams

TL/F/S603-S
For the purposes of AC measurements, VIH = 2.4V, VIL = O.BV.

FIGURE 4. Clock and Data Timings

CLOCK 50% +-;r-t-~-t---:l'--~----J~---:l~---

DATA IN 50%

+ ...1--t-+-t-J(-----l(------I~-

DATA OUT 50% + - t - - t - + - - I r - - - - - ' l l - - - - - - ' l l - - - -

IEs

tEH
~

I
,,_ _ _ __
ENABLE 50% ,~£...._ _ _ _ _..J~

B~~:~~~

50% _ _ _ _ _ _ _....I~\'"_ _ _ _ _ __

TYPICAL
DISPLAY
OUTPUT
VOIS---'"
TL/F/S603-6

FIGURE 5. MM58341 Timings (Data Format)

4-100

Typical Application
32·DlGIT MULTIPLEXED
5 x 7 DOT MATRIX
VACUUM FLUORESCENT
(VF) DISPLAY

:

~

2~~I!S_~

1------32 GRIDS

MM58348
DISPLAY DRIVER

CLOC K8

MM58341
DISPLAY DRIVER

t

DATA 8

DATAl
CLOCK 1

1

ENABLE 1

I

BLANK 1

I

MICROPROCESSOR

r
DATA
OUT 1
TLIF/S603-7

FIGURE 6. Microprocessor-Controlled Word Processor

4·101

~National

a

Semiconductor

MM58342 High Voltage Display Driver
General Description

Features

The MM58342 is a monolithic MOS integrated circuit utilizing CMOS metal gate low threshold P- and N-channel devices. It is available both in 28-pin molded dual-in-line packages or as dice. The MM58342 is particularly suited for driv~
ing high voltage (35V max) vacuum fluorescent (VF) displays (e.g., a 20-digit alphanumeric or dot matrix display).

•
•
•
•
•
•
•
•
•

Applications
•
•
•
•
•
•

COPSTM or microprocessor-driven displays
Instrumentation readouts
Industrial control indicator
Digital clock, thermostat, counter, voltmeter
Word processor text displays
Automotive dashboards

Direct interface to high voltage display
Serial data input
No external resistors required
Wide display power supply operation
LSTIL compatible inputs
Software compatible with NS display driver family
Compatible with alphanumeric or dot matrix displays
Display blanking control input
Simple to cascade

Block Diagram
OUTPUT

20

BLANKING -+t-----~
CONTROL

OUTPUT
1

...-

....-VDIS

t -.....*"""~ DATA
OUT

CLOCK -

--1"

....

ENABLE----..
TL/F17925-1

FIGURE 1

4-102

Operating Conditions

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage at Any Input Pin
Voo + 0.3V to VSS - 0.3V
Voltage at Any Display Pin
VOO to Voo - 36.5V
36.5V
VOO + IVolsl
Storage Temperature
- 65°C to + 150°C
Power Dissipation
500 mW at + 85°C
Junction Temperature
130°C
Lead Temperature (Soldering, 10 sec.)
260°C

Supply Voltage (Voo)
VSS = OV
Display Voltage (VOIS)
Temperature Range

Min

Max

Units

4.5
-30
-40

5.5
-10

V
V
°C

+85

DC Electrical Characteristics
TA

=

-40°C to + 85°C, VOO

Symbol

= 5V

= OV unless otherwise specified

±0.5V, VSS

Parameter

Conditions

Min

Typ

Max

Units

150

).LA

10

mA

0.8

V
V

0.4

V
V
V

10

).LA

15

pF

250
300
400
800
750
680

kn
kn
kn
n
n
n

VOIS + 2

V

Power Supply Currents
VIN = Vss or Voo, Vss = OV,
VOIS Disconnected
VOO = 5.5V, VSS = OV, VOIS = -30V
All Outputs Low

100

lOIS

VIL
VIH

Input Logic Levels
DATA IN, CLOCK
ENABLE, BLANK
Logic '0'
Logic '1'

(Note 1)

VOL
VOH
VOH

Data Output Logic Levels
Logic '0'
Logic '1'
Logic '1'

lOUT
lOUT
lOUT

liN

Input Currents DATA IN,
CLOCK ENABLE, BLANK

CIN

Input Capacitance DATA IN,
CLOCK ENABLE, BLANK

ROFF

Display Output Impedances
Output Off (Figure 3a)

RON

Output On (Figure 3b)

VOOL

Display Output Low Voltage

Note 1: 74LSTTL VOH

= 2.7V @

VIN

2.4

= 400).LA
= -10).LA
= - 500 ).LA
= OV or VOO

Voo = 5.5V, Vss
VOIS = -10V
VOIS = -20V
VOIS = -30V
VOIS = -10V
VOIS = -20V
VOIS = -30V

Voo - 0.5
2.8
-10

= OV
55
60
65
700
600
500

VOO = 5.5V, lOUT = Open Circuit,
-30V ~ VOIS ~ -10V
lOUT = -400 /LA, TTL VOH = 2.4V @ lOUT = -400/LA.

4·103

VOIS

Symbol

Parameter

Typ

Max

Units

800
300
300

kHz
ns
ns

100
100

ns
ns

100
100

ns
ns

Min

fc
tH
tL

Clock Input
Frequency
High Time
Low Time

tos
tOH

Data Input
Set-UpTime
Hold Time
Enable Input
Set-UpTime
Hold Time

(Note 2)

tES
tEH

CL = 50 pF

tcoo

Data Output
CLOCK Low to Data Out
Time

500

ns

Note 2: For timing purposes, the signals ENABLE and BLANK can be considered to be totally independent of each other.
Note 3: AC input waveform specification for test purposes: t r, tf ,,; 20 ns, f
Not~

= 800 kHz, 50% ± 10% duty cycle.

4: Clock input rise and fall times must not exceed 5 p.s.

C,?nnection Diagrams
Dual-In-Line Package

U

Vss(OVI_l
OUTPUT11_ 2

~

28 r - OUTPUT 12
27

OUTPUT10_ 3

Plastic Chip Carrier

:::;)

r- OUTPUT 13

:::;)

~

:::;)

25

OUTPUT 8 _

5

24 r- OUTPUT 16

OUTPUT 7 -

6

23 r - OUTPUT 17

OUTPUT 6 -

7

22

OUTPUT 5 -

8

21 I - OUTPUT 19

OUTPUT 4 -

9

20

I- OUTPUT 20

OUTPUT 3 -

10

19

r- BLANKING CONTROL

OUTPUT 2 -

11

18 r-ENABlE

OUTPUT 1 -

12

r- OUTPUT 15

:::;)

:::;)

:::;)

en I!:
en :::;)

I!: I!:
:::;)
0

0

I

I

:::;)

o >

o

I

I

I

I

I

4

3

2

1 28 27 26

0

26 r - OUTPUT 14

4

.... .... ....

:::;)

I!:
I!:
I!:
:::;)
:::;)

OUTPUT 9 _

0

OUTPUT 8- 5

25 :- OUTPUT 15

OUTPUT 7- 6

24 !- OUTPUT 16
23 ~ OUTPUT 17

OUTPUT 6- 7

r- OUTPUT 18

OUTPUT 5- 8

1.11.I58342V

22 ~ OUTPUT 18

OUTPUT 4- 9

21 !- OUTPUT 19

OUTPUT 3- 10

20 ~ OUTPUT 20

OUTPUT 2 -

19 !- BLANKING CONTROL

11
12 13 14 15 16 17 18

17 r - DATA OUT

VDlS -13
VoD (5VI -

~ ~ ~

~

'"
.... .... ....

16 I-DATA IN

14

15 r-ClOCK

TL/FI7925-B

TL/F17925-2

Top View
Order Number MM58342V
See NS Package Number V28A

Top View
FIGURE 2
Order Number MM58342N
See NS Package Number N28B

F~nctional

Description
Figure 2 shows the pinout of the MM58342 device, where
output 1 (pin 12) is equivalent to bit 1 (Le., the first bit of data
to be loaded into the shift register following ENABLE high).
A logic '1' at the input will turn on the corresponding display
digit/segment/dot output.

This product is specifically designed to drive multiplexed or
non-multiplexed high voltage alphanumeric or dot matrix
vacuum fluorescent (VF) displays. Character generation is
done externally in the microprocessor, with a serial data
path to the display driver. The MM58342 uses three signals,
DATA IN, CLOCK and ENABLE, where ENABLE acts as an
external load signal. Display blanking can be achieved by
means of the BLANKING CONTROL input, and a logic '1'
will turn off all sections of the display. A block diagram of
the MM58342 is shown in Figure 1.

A significant reduction in discrete board components can be
achieved by use of the MM58342, because external pulldown resistors are not required. Due to the nature of the
output stage, both its on and off impedance values vary as a
function of the display voltage applied. However, Figures 3a

4-104

Functional Description

(Continued)

and 3b show that this output impedance will remain constant for a fixed value of display voltage.

of the shift registers are latched, and the display will show
new data. During data transfer, the display will show old
data. DATA OUT is also provided on the MM58342 being
output on the falling edge. At any time, the display may be
blanked under processor control, using the BLANKING
CONTROL input.

Figure 4 demonstrates the critical timing requirements between CLOCK and DATA IN for the MM58342.

When the chip first powers on, an internal reset is generated, resetting all registers and latches. The chip returns to
normal operation on application of ENABLE, and so all interface signals should be inactive at power on.

Figure 6 shows a schematic diagram of a microprocessorbased system where the MM58342 is used to provide the
grid drive for a 40-digit 2 line 5 x 7 multiplexed vacuum
fluorescent (VF) display. The anode drive in this example is
provided by another member of the high voltage display
driver family, namely the MM58348, which does not require
an externally generated load signal.

In Figure 5, the ENABLE signal acts as an envelope, and
only while this signal is at a logic '1' does the circuit accept
CLOCK input signals. Data is transferred and shifted in the
internal shift register on the rising clock edge, i.e., '0' - '1 '
transition. When the ENABLE signal goes low, the contents

34.5

5 24 .5

~

+0:0
~ 14.5

-=--101-0---201-0---30.1...0---40.1...0---5..1..00---6.1.00'" lOUT (JLA)
TL/FI792S-3

FIGURE 3a. Output Impedance Off

6000 TYPICAL
AT +25°C, VOIS = -20V

1.0

E
~

4000 MAX
AT -40'C. VOIS= -30V
0.5

0

_=_--l___......L.._ _ _..L_ _ _...L_ _
0.5

0

--.,~

IOUT(mAI

1.5
TL/FI792S-4

FIGURE 3b. Output Impedance On

Timing Diagrams
CLOCK

::i

tos

DATA IN

500/,-

For the purposes of AC measurement, VIH

=

2.4V, VIL

=

TLlF/792S-S
O.BV.

FIGURE 4. Clock and Data Timings

4-105

~

~
C")

co
I.t)

r----------------------------------------------------------------------------------Timing Diagrams

:::a:
:::a:

(Continued)

CLOCK 50%

-+---I--l--\r---+----I------lIk------I------l~-----

DATA IN 50% -I--4-+--+-+--+-lIf-----------lI----------Jlf--

DATA OUT 50% -I---+--+-+--.:W----------lf:....-----------J~---

ENABLE 50%

Bro~~~~

-I----+-~o--------------+------;..---------

50% ________________

-'~~________________

VDD - - - - - - - - . - - - - - - _

DISPLAY
OUTPUT

VDIS ______-6

TL/F17925-6

FIGURE 5. Timings (Data Format)

Typical Application

,,

40-DlGIT BY 2-LlNE
5 x 7 MULTIPLEXED
DOT MATRIX VACUUM
FLUORESCENT (VF)
DISPLAY

----

----

CLOCK 8

I I
DATA B1

20
GRIDS

20
GRIDS

35
ANODES

35
ANODES

MM5B348
DISPLAY
DRIVER 1

,,

----

----

I

MM5B34B
DISPLAY
DRIVER 2

MM58342
DISPLAY
DRIVER 1

P;' r
OUT

MM5B342
DISPLAY
DRIVER 2

I

DATA 82
DATA 221

'

CLOCK 2
DATA 21
MICROPROCESSOR

ENABLE
BLANK

TL/F/7925-7

FIGURE 6. Microprocessor-Controlled Word Processor

4-106

~National

~ Semiconductor
MM58348 High Voltage Display Driver
General Description

Applications

The MM58348 is a monolithic MOS integrated circuit utilizing CMOS metal gate low threshold P and N-channel devices. It is available both in 40-pin molded dual-in-line packages or as dice. The MM58348 is particularly suited for driving high voltage (35V max) vacuum fluorescent (VF) displays (e.g., a 5 x 7 dot matrix display).

•
•
•
•
•
•

COPSTM or microprocessor-driven displays
Instrumentation readouts
Industrial control indicator
Digital clock, thermostat, counter, voltmeter
Word processor text displays
Automotive dashboards

Features
•
•
•
•
•
•
•
•

Direct interface to high voltage display
Serial data input
No external resistors required
Wide display power supply operation
LSTTL compatible inputs
Software compatible with NS display driver family
Compatible with alphanumeric or dot matrix displays
No load signal required

Block Diagram
OUTPUT
35

OUTPUT
1

I+----t+-

VDlS

DATA IN

CLOCK

TLiF/5601-1

FIGURE 1

4-107

Absolute Maximum Ratings

Operating Conditions

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (VOO)
VSS = OV

Voltage at Any Input Pin

Display Voltage (VOIS)
Temperature Range

-40

Min

Voo + 0.3V to VSS - 0.3V

Voltage at Any Display Pin

VOO to Voo - 36.5V

Max

Units

4.5

5.5

V

-30

-10

V

+85

·C

36.5V

Voo + IVolsl
Storage Temperature

- 65·C to + 150·C

Power Dissipation

500 mW at + 85·C

Junction Temperature

130·C

Lead Temperature
(Soldering, 10 seconds)

260·C

DC Electrical Characteristics
TA = -40·C to +85·C, Voo = 5V ±0.5V, VSS =

Symbol
10D

ov unless otherwise specified.

Parameter

Conditions

Power Supply Currents

lOIS

VIL

Max

Units

150

p.A

Voo = 5.5V, Vss = OV,
VOIS = -30V, All Outputs Low

10

mA

0.8

V

Min

Input Logic Levels
DATA IN, CLOCK
Logic '0'

VIH

Logic '1'

2.4
-10

liN

Input Currents DATA IN, CLOCK

CIN

Input Capacitance DATA IN, CLOCK

ROFF

Display Output Impedances
Output Off (Figure 3a)

Voo =
VOIS =
VOIS =
VOIS =

RON

Output On (Figure 3b)

VOIS = -10V
VOIS = -20V
VOIS = -30V

VOOL

Display Output Low Voltage

Voo = 5.5V, lOUT = Open Circuit,
-30V ~ VOIS ~ -10V

Note 1: 74LSTTL VOH = 2.7V

@

VIN = OV or Voo

lOUT = -400 /LA, TTL VOH = 2.4V

AC Electrical Characteristic TA =
Symbol

Typ

VIN = Vss or Voo, Voo = 5.5V,
Vss = OV, VOIS Disconnected

@

5.5V, Vss = OV
-10V
-20V
-30V

V
10

p.A

15

pF

250
300
400

k!l
k!l
k!l

800
750
680

!l
!l
!l

VOIS + 2

V

55
60
65
700
600
500
VOIS

lOUT = -400/LA.

-40·Cto + 85·C, Voo = 5V ±0.5V

Parameter

Conditions
(Notes 2 and 3)

Min

Typ

Max

Units

1.0

MHz

fc

Clock Input Frequency

tH

Clock Input High Time

300

ns

tL

Clock Input Low Time

300

ns

tos

Data Input Set-Up Time

100

ns

tOH

Data Input Hold Time

100

ns

Note 2: AC input waveform specification for test purpose: tr

~

20 ns, tf

~

20 ns, f = 1 MHz, 50% ± 10% duty cycle.

Note 3: Clock input rise and fall times must not exceed 5 /Ls.

4-108

Connection Diagrams
Dual-ln-L1ne Package
VSS (OV)
OUTPUT 17
OUTPUT 16
OUTPUT 15
OUTPUT 14
OUTPUT 13
OUTPUT 12
OUTPUT 11
OUTPUT 10
OUTPUT 9
OUTPUT 8
OUTPUT 7
OUTPUT 6
OUTPUT 5
OUTPUT 4
OUTPUT 3
OUTPUT 2
OUTPUT 1
VDlS
VoD (5V)

Plastic Chip Carrier
OUTPUT 18
OUTPUT 19
OUTPUT 20
OUTPUT 21
OUTPUT 22
OUTPUT 23
OUTPUT 24
OUTPUT 25
OUTPUT 26
OUTPUT 27
OUTPUT 28
OUTPUT 29
OUTPUT 30
OUTPUT 31
OUTPUT 32
OUTPUT 33
OUTPUT 34
OUTPUT 35
DATA IN

MM58348

19
21

~ ~ ~ ~

~ ~ ~ ~ ~

5555
!:l~55555
o 0 00> zoo 000

OUTPUT 13

OUTPUT 23

OUTPUT 12

38

OUTPUT 24

OUTPUT 11

37

OUTPUT 2S

OUTPUT 10

36

OUTPUT 26

OUTPUT 9

35

OUTPUT 27

N/C

34

N/C

OUTPUT 8

33

OUTPUT 28

OUTPUT 7

32

OUTPUT 29

OUTPUT 6

31

OUTPUT 30

OUTPUT 5

30

OUTPUT 31

29

OUTPUT 32

CLOCK
II">
....
............
~

TLfF/5601-2

Top View

t-

FIGURE 2

000

t-

t-

~ ~ ~

TLfF/5601-8

Top View
Order Number MM58348V
See NS Package Number V44A

Order Number MM58348N
See NS Package Number N40A

Functional Description
This product is specifically designed to drive multiplexed or
non-multiplexed high voltage alphanumeric or dot matrix
vacuum fluorescent (V F) displays. Character generation is
done externally in the microprocessor, with a serial data
path to the display driver. The MM58348 uses two signals,
DATA IN and CLOCK, with a format of a leading "1" followed by the 35 data bits, hence allowing data transfer without an additional signal. A block diagram of the MM58348 is
shown in Figure 1.

data to be loaded into the shift register following the start
bit). A logic "1" at the input will turn on the corresponding
display digit/segment/dot output.
A significant reduction in discrete board components can be
achieved by use of the MM58348, because external pulldown resistors are not required. Due to the nature of the
output stage, both its on and off impedance values vary as a
function of the display voltage applied. However, Figure 3a
and 3b show that this output impedance will remain constant for a fixed value of display voltage.

Figure 2 shows the pinout of the MM58348 device, where
output 1 (pin 18) is equivalent to bit 1, (Le., the first bit of

+B5'C
-40'C

34.5

!

24.5

+

~

14.5

~=------L

__..!-_ _

100

.l....-_......L._ _..I-._ _~

200

300

400

500

lOUT (pAl

600

TL/F/5601-3

FIGURE 3a. Output Impedance Off

BODO MAX
AT +B5'C, VDIS= -10V

1.0

6000 TYPICAL
AT +25'C, VDlS= -20V

E

:i

4000 MAX
AT -40'C, VOIS = -30V

0.5

o

"~_..!-

o

0.5

_ _--L_ _ _.l....-_ _..I-._ _ _ IOUT(lnA)

1.5

FIGURE 3b. Output Impedance On

4-109

TL/F/5601-4

~ r---------------------------------------------------------------------~

-.::t'

~
LI)
::::E
::::E

Functional Description

(Continued)

Figure 4 demonstrates the critical timing requirements between CLOCK and DATA IN for the MM58348.

for the MM58348, or the shift register will not clear. If, at any
given time, it is required that the display be cleared under
microprocessor control, i.e., without power on reset, then
the following flushing routine may be used. Clock in 36 "zeroes", followed by a "one" (start bit), followed by 35 "zeroes". This procedure will completely blank the display.

When the chip first powers on, an internal reset is generated, resetting all registers and latches. The chip returns to
normal operation on application of the start bit and the first
clock pulse, and so all interface signals should be inactive
at power on.

Figure 6 shows a schematic diagram of a microprocessorbased system where the MM58348 is used to provide the
anode drive for a 32-digit 5 x 7 dot matrix vacuum fluorescent (VF) display. The grid drive in this example is provided
by another member of the high voltage display driver family,
namely the MM58341, which has the additional features of
a BLANKING CONTROL pin, a DATA OUT pin, and an ENABLE (external load signal) pin.

In Figure 5, a start bit of logic "1" precedes the 35 bits of
data, each bit being accepted on the rising edge of CLOCK,
i.e., a "0"-"1" transition. At the 36th clock, a LOAD signal
is generated synchronously with the high state of the clock,
thus loading the 35 bits of the shift register into the latches.
At the low state of the clock, a RESET signal is generated,
clearing all bits of the shift register for the next set of data.
Hence, a complete set of 36 clock pulses is needed

Timing Diagrams

TLlF/5601-5

For the purpose of AC measurement, VIH

= 2.4V, VIL = O.BV

FIGURE 4. Clock and Data Timings

CLK 35

START
ClK

ClK 1

ClK 2

ClK 3

ClK 33

ClK 34

CLOCK

DATA IN

lOAD
(INTERNAL)

Jl

RESET
(INTERNAL)

--I

n•_____

1..._ _ _ _ _ _ _ _ _ _ _ _I111/~------.....1

n

0--------....

T,":~

.._ _ __

/

DISPLAY
OUTPUT

VDlS

n

1.------------

'----------""~--------I
TLlF/5601-6

FIGURE 5. MM58348 Timings (Data Format)

4-110

Typical Application
32·o1GIT MULTIPLEXED
5 x 7 DOT MATRIX
VACUUM FLUORESCENT
(VF) DISPLAY

;

~

2~~~S_{

32 GRIDS

-------

MM58348
DISPLAY DRIVER

CLoC K8

MM58341
DISPLAY DRIVER

t

DATA 8

DATA 1
CLOCK 1

1

ENABLE 1

I

BLANK 1

I

MICROPROCESSOR

,
DATA
OUT 1
TlIF/5601-7

FIGURE 6. Microprocessor-Controlled Word Processor

4-111

C) r---------------------------------------------------------------------------------~
Lt)

National Semiconductor
Application Note 350
Bob Lutz

C"')

:Z Designing an LCD Dot

Z

BACKGROUND
LCD displays have become very popular because of their
ultra-low power consumption and high contrast ratio under
high ambient light levels. Typically an LCD has a backplane
that overlaps the entire display area and multiple segment
lines that each overlap just one segment or descriptor. This
means that a separate external connection is needed for
every segment or descriptor as shown in Figure 2. For a
display with many segments such as a dot matrix display,
the number of external connections could easily grow to be
very large.

One way to reduce the number of external connections is to
multiplex the display. An example of this could be an LCD
with its segments arranged as intersections of an X-V grid. A
driver to control a matrix like this would be fairly straightforward for an LED display. However, it is more complex for an
LCD because of the DC bias restriction.
A multiplexed LCD driver must generate a complex set of
output signals to insure that an "on" segment sees an rms
voltage greater than the display's turn-on voltage and that
an "off" segment sees an rms voltage less than the display's turn-off voltage. The driver must also insure that there
is no DC bias.

Unlike other display technologies that respond to peak or
average voltage and current, LCDs are sensitive to the rms
voltage between the backplane and given segment location.
Also, any DC bias across this junction would cause an irreversible electrochemical action that would shorten the life of
the display. A typical LCD driving signal is shown in Figure 3.
The backplane signal is simply a symmetrical square wave.
The individual segment outputs are also square waves, either in phase with the backplane for an "off" segment or out
of phase for an "on" segment. This causes a Vrms of zero
for an "off" segment and a Vrms of + V for an "on"
segment.

One pattern that can accomplish this is shown as an example in Figure 4. This is the pattern that the MM58201 uses.
The actual Vrms of an "on" segment and an "off" segment
is shown in Figure 5. If there are eight backplanes, the Vrms
(ON) = 0.2935 x VTC and the Vrms (OFF) = 0.2029 X
VTC. It can be seen in Figure 6 that as the number of backplanes increases, the difference between Vrms (ON) and
Vrms (OFF) becomes less. Refer to the specifications of the
LCD to determine exactly what Vrms is required.

"OW SEGMENT +V ---,
DRIVE (IN PHASE) 0 _

n

L...J

BACKPLANE

n

L...J

I
L...J

+VlflJl.j

0-

COMMON
PIN

"ON" SEGMENT +V DRIVE (180° OUT or PHASE) 0

n

---1

n L...Jn

L...J

L

TLl8/5606-3

FIGURE 3. Drive Signals from a
Direct Connect LCD Driver

TL/8/5606-2

FIGURE 2. Typical LCD Pin Connections

POLARITY
REVERSAL
VTC
BPI 0.5 VTC
OV
SI

S2

:::~

BP2 0.5 VTC
OV

~3"

BP3 0.5 VTC
OV

• = ON

(DARK)

0.68 VTC
SI
0.32 VTC
0.68 VTC
S2
TL/8/5606-4

FIGURE 4. Example of Backplane and Segment Patterns

4-113

eN
U1

o

VTCn

-------""U

0.5 VTC

} BACKPLANE

.....

OV-------------------

I

0.68 VTC

} SEGMENT COLUMN

0.32 vTC-.I
0.68 VTC - - ,
0.18 VTC
-0.18 V
L.._ _ _ _ _ _ _
TC
-0.68 VTC - - - - - - - - - - - - - - - - - - -

- ,.-------J

--,---i.f----------------

or "ON"

~.

o

N N+l

(~

Vrms (ON) =

f:

} 4V

2N

SEGMENT

TIME

TLIB/5606-5

+ T V2(t)dt) 1/2

(-

=

(~[f: (0.68 VTcl 2dt + f~

=

(~VTc2[0.4624 + 0.0324(N -

= VTC[0.4624 + 0~324(N -

0.18 VTcl 2dt ]) 1/2

1)] )1/2

1)]1/2

N = number of backplanes

a. Analysis of Vrms (ON)

VTCn

-------.,U

0.5 VTC

} BACKPLANE

.....

OV-------------------0.68 VTC ---,
0.32 V
L.._ _ _ _ _ _ _ _.....
TC
0.32 VTC - - ,
0.18VTC

} SEGMENT COLUMN

1

- - - - - - - -..

l.Jr----------

-0.18 VTC
-0.32 VTC - - - - - - - - - - - - - - - - - - -

o

N

Vrms (OFF)

f:

N+l

(~

=

(~[

=

(~VTc2[0.1024 + 0.0324(N -

J:

or "orr" SEGMENT

TIME

TL/B/5606-6

1/2

(0.32 VTcl 2dt

= VTC[0.1024

N

2N

=

+ T v2(t)dt )

} 4V

+ f~

+ 0~324(N

(-

0.18 VTcl2dt] ) 1/2

1)] )1/2

- 1)]1/2

= number of backplanes

b. Analysis of Vrms (OFF)
vrms

VTC=I/2

(0.102.. +

(orr)

Vrms (ON)

~032-4(N-l») + ~0."62" + ~032"(N-l»),

]

[

--It

MUST BE GREATER THAN ______

Example: If N = 8
and Vrms (OFF) = 1.8V
and Vrms (ON) = 2.2V
then VTC = 7.5V

FIGURE 5

4-114

TL/B/5606-7

»
z

FUNCTIONAL DESCRIPTION

I

W

Connecting an MM5B201 to an LCD

Since the input impedance of VTC may vary between 10 ko.
and 30 ko., the output impedance of the voltage reference
at VTC should be relatively low. One example of a VTC driver
is shown in Figure 8. To put the MM58201 in a standby
mode, bring VTC to Vss (ground). This will blank out the
display and reduce the supply current to less than 300 I1A

The backplane and segment outputs of the MM58201 connect directly to the backplane and segment lines of the
LCD. These outputs are designed to drive a display with a
total "on" capacitance of up to 2000 pF. This is especially
important for the backplane outputs, as it is usually the
backplanes that have the most capacitance. As the capacitance of the output lines increases, the DC offset between a
backplane and segment signal may increase. Most LCD displays specify that a maximum offset of 50 mV is acceptable.
For backplane capacitance under 2000 pF the MM58201
guarantees an offset of less than 10 mV.
If the LCD display to be used has 24 segments per backplane or less, then each MM58201 should be configured as
a "master" so that each one will generate its own set of
backplane signals. However, if the LCD display has more
than 24 segments per backplane, more than one MM58201
will be needed for each backplane. To synchronize the driving signals there must be one "master" chip and then an
additional "slave" chip for every 24 segments after the first
24. When a chip is configured as a "slave" it does not generate its own backplane signals. It simply synchonizes itself
to the backplane signals generated by a "master" chip by
sensing the BP1 signal. An example of both an all "master"
configuration and a "master-slave" configuration will be
shown later.

15V

r

2N2222

Vrc

RC Oscillator
This oscillator works with an external resistor tied to VDD
and an external capacitor tied to Vss. The frequency of oscillation is related to the external Rand C by:
fosc = 1/1.25 RC ± 30%
The value of the external resistor should be in the range
from 10 ko. to 1 MO.. The value of the external capacitor
should be less than 0.005 f-LF.
The oscillator generates the timing required for multiplexing
the LCD. The frequency of the oscillator is 4N times the
refresh rate of the display, where N is the number of backplanes programmed. Since the refresh rate should be in the
range from 32 Hz to 100 Hz, the oscillator frequency should
be:

~

>

£
e
~

~

~

\.

"'\..

"

,

........ ......

128N < fOSC < 400N
If the frequency is too slow, there will be a noticeable flicker
in the display. If the frequency is too fast, there will be a loss
of contrast between segments and an increase in power
consumption.

--...

Serial Input and Output
Data is sent to the MM58201 serially through the DATA IN
pin. Each transmission must consist of 30 bits of information, as shown in Figure 9. The first five bits are the address,
MSB first, of the first column of LCD segments that are to be
changed. The next bit is a read or write flag. The following
24 bits are the actual data to be displayed.

1
NUt.4BER OF BACKPLANES
TL/B/5606-8

FIGURE 6. I:l Vrms/VTC

It

a. Backplane Output

The address specifies the first LCD column that is going to
be affected. The columns are numbered as shown in Figure
10. Data is always written in three column chunks. Twentyfour bits of data must always be sent, even if some of the
backplanes are not in use. The starting column can be any
number between one (00000) and twenty-four (10111). If
column 23 or 24 is specified the displayed data will wrap
around to column 1.

0.68Vrc~11L
0.32Vrc~-­

If the R/W bit is a "0" then the specified columns of the
LCD will be overwritten with the new data. If the bit is a "1"
then the data displayed in the specified columns will be
available serially at the DATA OUT pin and the display will
not be changed.

I--

j
f
Vrc--tr-tr--"",
tr _

0.5 Vrc

TL/B/5606-11

FIGURE B. Example of VTC Driver

The voltage presented at the VTC pin determines the actual
voltage that is output on the backplane and segment lines.
These voltages are shown in Figure 7. VTC should be set
with respect to Vrms (ON) and Vrms (OFF) and can be calculated as shown in Figure 5.

~
£
8-

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• 68K

Voltage Control Pin and Circuitry

01-4
012
0.20
0.18
0.16
0.1-4
0.12
0.10
0.08
0.Q6
0.Q.4
0.02
0

~ 33K

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f4-

tf

-

f4-

tr

r-

...l

~--Vss
TL/B/5606-9

TL/B/5606-10

b. Segment Output
FIGURE 7. Output Voltages
4-115

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o

oU')
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z•
oct
ClK IN

DATA IN _ _
DC_N1_CA_R_E--&.1_A.---1I_ A_3 ....L..I_A_2-L_A'-J,I_A0--J1I..-.,;R/W_,-1_0_'-L1_02-J,1_03--JL-

022

023

-----------------{
~D1J:~02=:JI~D3~[

022

023

DATA OUT

02.

DCN1 CARE

TLIB/5606-12

FIGURE 9. Transmission of Data
SI

S2

S3

S.

S5

S6

S7

S8

S9

S10 SII S12 S13 SU S15 S16 S17 S18 S19 S20 S21 S22 S23 S2.

BPI

01

09

BP2

02

010 018

BP3

03

011 019

BP4

04

012 020

BP5

05

013 021

BP6

06

OU 022

BP7

07

015 023

BP8

08

016 024

017

B2:
--,
Bl'

--I
BO,

--,

~:!

A.

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

A3

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1
1

A2

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

AI

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

AO

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

TL/B/5606-13
Diagram above shows where data will appear on display if starting address 01100 is specified in data format.

FIGURE 10. Address of Particular Segment Columns
5.0 fLs. A transmission is initiated by CS going low. CS can
then be raised anytime after the rising edge of the first clock
pulse and before the rising edge of the last clock pulse (the
clock edge that reads in 024). 30 bits of information must
always be sent.

The data is formatted as shown in Figure 10. The first bit in
the data stream corresponds to backplane 1 in the first
specified column. The second bit corresponds to backplane
2 in the first specified column and so on.
During initialization each MM58201 must be programmed to
select how many backplanes are to be used, and whether
the chip is to be a "master" or a "slave". The format of this
transmission is just like a regular data transmission except
for the following: the address must be 11000; the R/W must
be a write (0); the first three data bits must be selected from
the list in Table I. The next bit should be a "1" for the chip to
be a master or a "0" for the chip to be a slave. The following
20 bits are necessary to complete the transm!ssion but they
will be ignored. The mode cannot be read back from the
chip.
TABLE I. Backplane Select
Number of
Backplanes
2
3
4
5
6
7
8

B2

B1

BO

a
a
a

a

1

1
1

a

1
1
1
1

a
a

a

1
1

The data at DATA IN is latched on each rising edge of the
clock pulse. The data at DATA OUT is valid after each failing edge of the last 24 clock pulses.
It is important to note that during a read or write transmission the LCD will display random bits. Thus the transmissions should be kept as short as possible to avoid disrupting
the pattern viewed on the display. A recommended frequency is:
fosc = 30/(tLCD - 7 ts)
tLCD = turn onloff time of LCD
ts = time between each successive transmission.
This should produce a flicker-free display.
The DATA OUT pin is an open drain N-channel device to
Vss. This output must be tied to VDD through a resistor if it
is to be used. It could also be tied to a lower voltage if this
output is to be interfaced to logic running at a lower voltage.
The value of the resistor is calculated by:

1

R

1

+V

a
1

= (+ V - 0.4)/0.0006
= voltage of lower voltage logic

Power Supply
VDD can range between 7V and 18V. A voltage should be
used that is greater than or equal to the voltage that you
calculate for VTC as shown in Figure 5.

The timing of the ClK, CS, DATA IN, and DATA OUT are
illustrated in Figure 11. The frequency of the clock can be
between DC and 100 kHz with the shortest half-period being

4-116

»
z

TYPICAL APPLICATIONS

One application of the MM58201 is a general purpose display to show graphic symbols and text. This type of display
could be used in an electronic toy or a small portable computer or calculator. One such display is shown in Figure 12.
This display consists of four separate LCD displays that are
built into one housing. Each separate LCD display has 8
backplanes and 24 segment lines. The entire display will
require four MM58201 s to control it.

The VTC driver is as described beforehand. The MM74C906
is an open drain CMOS buffer that has near regular TTL
compatible inputs. This is to provide level translation from
the 5V supply of the computer system to the 12V supply of
the MM58201.
If 1/0 ports are not available, the circuit in Figure 15 could
be used as an interface between the MM58201 s and a microprocessor bus.
To reduce the number of connections between the circuit
and the lCD, all of the backplanes could have been driven
by one MM58201 as shown in Figure 16. The other
MM58201s would be configured as "slaves" synchronized
to the one "master" MM58201. This would save 24 connections to the LCD but would increase the capacitance of the
backplanes. In this application the capacitance is not 'a
problem with either setup.
..

The circuit diagram of this application is shown in Figure 14.
Each separate LCD display is driven by one MM58201. The
backplanes are driven by the separate MM58201 s and are
not paralleled together. There are three common lines: ClK,
DATA IN, and DATA OUT. The ClK and DATA IN are generated from an output port such as an INS8255. Four other
bits of the output port generate a linear select with a different bit going to each MM58201 chip select as shown in
Figure 13. DATA OUT is sent to one bit of an input port.

...

ClK

rllt~

~

L....- - - - - - ••• "

CAN RISE ANY TIt.4E

...

"

•••

~
~ t.4UST RISE BY THIS POINT
~

IN

02 • • • .:.:-:.:.

•••

OUT

01

02

•••

........................ .

024.::::::::::::::::::::::::.

y . . . _..I!
_02_4

TLIB/5606-14

FIGURE 11. Timing of One Transmission
51

BPI

BPS

•

••
••
•

524

LCD 0

LCD 1

••
•

LCD 2

LCD 3

••
•

6

5

CS4

CS3

CS2

CS 1

1

0

o
o
o

TLIB/5606-15

1

FIGURE 12. Four Separate LCD Displays
Positioned to Look Like One Display

43210

7

1

Chip 1 Selected
Chip 2 Selected
Chip 3 Selected
Chip 4 Selected
No Chip Selected

FIGURE 13. Chip Select Scheme

4-117

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2s

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Vrc Voo
DATA OUT
ClK
WW58201
DATA IN
CS

#1

51-524
Bl-B7

RC OSC
121

r--1:
-=

330k
12V

O.OOII"F

'~ .. '"

5V
2

1 CSI

4

3 CS2

6

S CS3

8

9 CS4

>>-

12V
6k

12V
6k

......

6k

rrr-

-f

'F"

10

11 ClK

12

13 DATA IN

WM58201
#2

1

I:

-

'

...
...

~

13

-f

WW74C906

,1

#2

13

,4

MW58201

-

I

~

1

I:

,

~

...

~

SEGMENTS
1-24

12V

t-6k

~

BACKPLANES
1-8

fll

Ii

"

12V

-

~

I---I---

SV
INPUT
PORT

t

MW58201
,4

128 CONNECTIONS FROW LCD

7.Sk

DATA OUT

r--1:

1

12V

TL/B/5606-16

FIGURE 14. Diagram of Application

1

°2
03
0
04

5V

1

INPUT
PORT

OUTPUT
PORT

Os

RD

06

ADDRESS
DECODE
MW74HCD2

Wil

2

ADDRESS
DECODE

3

TL/B/5606-18

b. Input Port
IoIW74HC02

TLIB/5606-17

a. Output Port
FIGURE 15. Input and Output Ports for Interface

4·118

»
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12V

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lOOk

68k

~:
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T~

~

VSS
Vrc VOO
DATA OUT
SI-S24
CLK
...... 58201
DATA IN
CS

n

,1
RC OSC

BI-B7

I-!"'-

121

5V
2

I

CSI

4

3 CS2

6

5 CS3

8

9 CS4

>>-

l-

12V

12V
6k

12V
6k

1--

6k

7-'--

...... 58201
,2
BPI

I--

I

,.

'~'
6k

10

II elK

12

13 DATA IN

I-I-5V
6k

11 ... 58201
,3
7.5k

1--'---

~ 1-8

BACKPLANES

~

,1

13

12

+-

,4

~

I--r-

r-

I

'7

~

SEG ... ENTS 1-24

r--

J

I

"

I--

...... 74C906

_I--

DATA OUT

"----

INPUT
PORT

--

... 1158201
,4

---1
104 CONNECTIONS FRO ... LCD

330k

o.oOll'F

12V

TL/8/5606-19

FIGURE 16. Diagram of a Master-Slave Set-Up Not Used for This Application
SOFTWARE

MAIN

The real heart of this system is the software which consists
of four parts. Part one is the initialization portion. This sets
up the MM58201 s as "masters" and programs them for 8
backplanes. It then sets up the needed pointers for the other subroutines which consist of:

This program initializes the MM58201 s. It controls the sequence of display output by calling other programs.
It first sends out a "dummy" transmission to make sure that
the chips are ready to respond to a valid transmission. It
then programs the chips to be "masters" and to use eight
backplanes.

1) GRAPH: displays pattern on LCD.
2) TEXT: prints ASCII characters on display.

After initialization, this program sets up the correct pOinters
to display a graphic symbol. First it displays the upper eight
bits of it, then it displays the lower eight bits.

3) SCROLL: scrolls whatever pattern is displayed to the
right until LCD is cleared.

The words "TESTING MM58201" are then displayed. A call
to scroll then causes this to scroll to the right until the
screen is blank. Finally the words "END OF TEST" appear
and the program ends.

This application used an NSC800TM with 8080 mnemonics.
It could easily be adapted for other microprocessors.

The method to create a custom graphic symbol will be demonstrated in the next section.

4-119

C)

r---------------------------------------------------------------------------------------------~

&l)
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N8080
EXTRN GRAPH, WRITE, MODE, TEXT, CURSOR, SCROLL

:Z

«

;INITIALIZE THE STACK POINTER
LXI SP ,lFFFH
;INITIALIZE
;SET MODE 0
;INIT: MVI
OUT
;SET PORT A
MVI
OUT
MVI
OUT

THE 810
FOR PORT A
A,OOH
27H
AS OUTPUT AND PORT C AS INPUT
A,OFFH
24H
;PORT A DDR
A,OOH
26H
;PORT B DDR

;INITIALIZE THE FOUR 58201' S
MVI A,O
STA MODE
LXI H,MASTER,
MVI E, 1l000B
MVI D,00001l10B
CALL WRITE
LXI H,MASTER
MVI D,00001l10B
CALL WRITE
LXI H,MASTER
MVI D,OOOOllOlB
CALL WRITE
LXI H, MASTER
MVI D,00001011B
CALL WRITE
LXI H,MASTER
MVI D,OOOOOl11B
CALL WRITE

;SET FOR WRITE MODE
;SEND A COMPLETE TRANSMISSION TO CLEAR OUT
ANY OLD CHIP SELECT.
;CONFIGURE CHIPS 0, 1, 2, AND 3 AS MASTERS

;SET UP POINTER AND COUNTERS TO DISPLAY NATIONAL SEMI SYMBOL
MVI B,21
;B HOLDS # OF COLUMNS TO CHANGE
RESTRT: MVI D, 0
;D HOLDS THE STARTING COLUMN NUMBER FOR UPPER HALF
MVI E,48
;E HOLDS STARTING COLUMN NUMBER FOR LOWER HALF
DSLOOP: MOV C, D
LXI H,NATSM1
;DISPLAY UPPER HALF OF GRAPHIC
CALL GRAPH
LXI H,NATSM2
;DISPLAY LOWER HALF OF GRAPHIC
MOV C,E
CALL GRAPH
PAUSE:

LXI
DCX
MOV
ORA
JNZ

H, OFFFFH
H
A,H
L
PAUSE

;PAUSE

INR
INR
INR
INR
INR
INR
MVI
CMF
JNZ

D
D
D
E
E
E
A,30
D
DSLOOP

;INCREMENT STARTING COLUMN NUMBERS

;DISPLAY IT UNTIL COLUMN COUNT IS 30

LXI H,TEXTl
MVI A,O
STA CURSOR
CALL TEXT

;PRINT FIRST TEXT
;ZERO THE CURSOR

CALL SCROLL

;SCROLL THE TEXT

LXI H,TEXT2
MVI A,O
STA CURSOR
CALL TEXT

;PRINT SECOND TEXT
;ZERO THE CURSOR

LXI
PAUSE1: DCX
MVI
PAUSE2: DCR
JNZ
MOV
ORA
JNZ

H, OFFFFH
H
A,2
A
PAUSE2
A,H
L
PAUSEl

;PAUSE

4·120

TEXTI:
TEXT2:
TEXT3:

LXI H,TEXT3
MVI A,O
STA CURSOR
CALL TEXT

;PRINT THIRD TEXT

RST 6

;END

»
z
I

CAl
U1

o

DB "TESTING MM58201·
DB "THIS IS THE END·
DB" OF THE
TEST •

MASTER: DB llllB
SLAVE: DB OlllB

0
0
0
;ADDRESS FOR MASTER
;ADDRESS FOR SLAVE

NATSMI: DB OFFH, OFFH, OFFH, 7FH, 3FH, 9FH, OCFH, 67H, 33H, OIH, 7FH
DB 3FH, 9FH, OCFH, 67H, 33H
DB 99H, OFFH, OFFH, OOH, ~OH
NATSM2: DB OFFH, OFFH, OFFH, OE6H, OF3H, OF9H, OFCH, OFEH, OFFH
DB OEOH, OE6H, OF3H, OF9H, OFCH
DB OFEH, OFFH, OFFH, OFFH, OFFH, OOH, OOH
END

GRAPH
select going low. The rest of the column address is then
output with all the chip selects high. If the operation is a
write, the data is sent to the display bit by bit. If the operation is a read, the data is read in bit by bit.

This subroutine is the center of the software. It is the interface between the calling programs and the hardware. All
110 is generated by this subroutine.
There are two entrances to this subroutine: graph and read.
Graph is the entrance used to display new data. Read is the
entrance used to read data from the display.

To create a custom graphic symbol, draw it on a grid as
shown in Figure 17. Group the upper eight squares as a byte
with the least significant bit at the top, counting a dark
square as a one. Group the lower eight squares as a byte
with the most significant bit at the bottom. Use this generated data as input lists to the graph subroutine. A good example of this is shown in the listing of main when it calls graph.

The HL register should point to the beginning of the data to
be displayed. The B register should hold the number of columns to change. This must be a multiple of three. The C
register should hold the column number to start with. This
must also be a multiple of three. These restrictions are to
simplify the software.

Pad the data at the end with zeros as shown to keep the
number of data values a multiple of three. Remember, this is
only a software restriction. A different routine could be used
that would allow any number of columns to be displayed.

The first operation is the calculation of the correct chip to
enable and the column number to start within that chip. The
first bit of the column address is output with the correct chip
7F

3F

9F

CF

67

33

01

7F

3F

9F

eF

67

33

99

FF

FF

00

00

UPPER

Data Upper: 7F, 3F, 9F, CF, 67,33,

01, 7F, 3F, 9F, CF, 67,

33,99, FF, FF, 00, 00
Data Lower: E6, F3, F9, FC, FE, FF,

EO, E6, F3, F9, Fe, FE,
FF, FF, FF, FF, 00, 00

LOWER

E6

F3

F9

Fe

FE

FF

EO

E6

F3

F9

Fe

FE

FF

fF

Ff

FF

OO~

00

FIGURE 17. Example Graphic Symbol

4-121

TL/8/5606-20

•

oLt)

.

N8080
PUBLIC GRAPH, READ, WRITE, MODE

C")

z

<

GRAPHIC DISPLAY DRIVER
INPUT: HL - POINTS TO START OF DATA
B- # OF 8 BIT COLUMNS TO CHANGE (MUST BE MULT. OF 3)
C- COLUMN # TO START WITH (MUST BE MULT. OF 3)
OUTPUT: NO REGISTERS DISTURBED
DATA POINTED TO IS DISPLAYED ON LCD DISPLAY.
COLUMNS NOT SPECIFIED ARE NOT AFFECTED.
READ:
;SAVE ALL STATES
PUSH PSW
PUSH B
PUSH D
PUSH H
;FLAG FOR A
MVI
STA
JMP

READ OPERATION
A,10000000B
MODE
GRAPH1

GRAPH:
;SAVE ALL STATES
PUSH PSW
PUSH B
PUSH D
PUSH H
;FLAG FOR A WRITE OPERATION
MVI A,O
STA MODE
;CALCULATE WHICH 58201 TO ACCESS
GRAPH 1 : MVI D, OEEH
;START WITH CS1
ACC:
MOV A,C
SUI 24
;SUBTRACT 24 FROM COLUMN COUNT
JC GO
;IF CARRY IS SET THE CORRECT CHIP IS SELECTED
MOV C,A
;REG C GETS NEW COLUMN NUMBER
MOV A,D
RLC
;INCREMENT THE CS TO NEXT CHIP
MOV D,A
JMP ACC
;MAIN LOOP
GO:
MOV E,C
M.LOOP: CALL WRITE
DCR B
DCR B
DCR B
JZ END.G
MOV A,E
ADI 3
CPI 11000B
JNZ SKIP1
MOV A,D
RLC
MOV D,A
MVI A,O
SKIP1: MOV E,A
JMP M.LOOP

;SAVE NEXT ADDRESS
;LOOP UNTIL DONE

END.G:

;RESTORE ALL STATES

POP
POP
POP
POP
RET

H
D
B
PSW

;GET COLUMN NUMBER
;DRAW 3 COLUMNS
;SUBTRACT 3 FROM COLUMN COUNT
;IF DONE, JUMP.
;ADD 3 TO ADDRESS
;IF ADDRESS NOT MAX THEN SKIP THIS
;SELECT NEXT 58201 CS

WRITE:
DISPLAY 3 COLUMNS OF DATA
INPUT: HL- POINTS TO START OF DATA
E - ADDRESS
D - OUTPUT CS
OUTPUT: HL <- HL + 3
;SAVE ALL STATES
PUSH PSW
PUSH B
PUSH D
START:

MVI
ANA
MOV
MOV
RLC
RLC
MOV

A,OOOOllllB ;ISOLATE CS IN REG D
D
D,A
A,E
;GET ADDRESS BITS AT HIGH END OF BYTE
E,A

4-122

;OUTPUT FIVE ADDRESS BITS WITH CHIP SELECT
MVI C,5
W.LOOP: MOV A,E
RLC
;ROTATE ADDRESS
MOV E,A
MVI A,10000000B
ANA E
;GET MSB
ORA D
;MERGE WITH CHIP SELECT
CALL DISPLY
DCR C
;DEC ADDRESS BIT COUNTER
JNZ W.LOOP
;LOOP UNTIL ADDRESS IS OUT
;SIGNAL FOR A READ OR WRITE
LDA MODE
ORI OOOOllllB
CALL DISPLY
JP DISO
;READ THE DATA
MVI B,3
READ1: MVI C,B
MVI D,O
READ2: IN 22H
ANI 00000001B
ORA D
RRC
MOV D,A
MVI A,OOOOllllB
CALL DISPLY
DCR C
JNZ READ2
MOV M,D
INX H
DCR B
JNZ READl

.

»
z
w

U1

o

;JUMP IF THIS IS A WRITE
;3 BYTES OF DATA
;8 BITS PER BYTE
;CLEAR DATA BYTE
;GET A BIT OF DATA
;MASK OFF UNWANTED BITS
;MERGE WITH DATA BYTE
;ROTATE DATA
;SET UP 58201 TO READ NEXT BIT
;LOOP UNTIL DONE WITH BYTE
;INCREMENT BYTE POINTER
;LOOP UNTIL DONE WITH ALL BYTES

;RESTORE STATES
POP D
POP B
POP PSW
RET
;DISPLAY THE DATA
DISO:
MVI B,3
DIS1:
MVI C,8
MOV D,M
DIS2:
MOV A,D

;3 BYTES OF DATA
;8 BITS PER BYTE
;ROTATE DATA

RRC
MOV D,A
ANI 10000000B
ORI OOOOllllB
CALL DISPLY
DRC C
JNZ DIS2
INX H
DCR B
JNZ DISl

;GET NEXT BIT
;SET CS
;OUTPUT A BIT OF DATA
;LOOP UNTIL DONE WITH BYTE
;LOOP UNTIL DONE WITH 3 BYTES

;RESTORE STATES
POP D
POP B
POP PSW
RET

II

DISPLY:
;DISPLAY ROUTINE
INPUT: A - DATA AND CHIP SELECT
BIT 7 - DATA
BITS 0-3 - CHIP SELECT
OUTPUT: NO REGISTERS DISTURBED
OUTPUT ONE BIT TO 58201
PUSH PSW

;SAVE STATES

ANI
OUT
ORI
OUT
ANI

;MASK OFF UNWANTED BITS
;SET UP DATA AND CHIP SELECT
;CLOCK HIGH

10001111B
20H
01000000B
20H
10111111B

POP PSW

;CLOCK LOW
;RESTORE STATES

RET
MODE:

DS 1
END

4-123

oLt)

.

('I)

z



z

)lULT:
;UULTIPLY BC REG BY SIX
INPUT: BC - MULTIPLICAND
OUTPUT: BC <= BC • 6
NO REGISTERS DISTURBED

w

U1

o

PUSH PSW
PUSH H
MOV H,B
MOV L,C
DAD B
DAD B
DAD B
DAD B
DAD B
MOV B,H
MOV C,L
POP H
POP PSW

RET
CURSOR: DS 1
ASCII : DB 0,0,0,0,0,0
DB 0,95,95,0,0,0
DB 0,7,0,7,0,0
DB 20,127,20,127,20,0
DB 36,42,127,42,18,0
DB 35,19,8,100,98,0
DB 54,73,102,32,80,0
DB 0,0,7,0,0,0
DB 0,28,34,65,0,0
DB 0,65,34,28,0,0
DB 34,20,127,20,34,0
DB 8,8,62,8,8,0
DB 0,64,48,0,0,0
DB 8,8,8,8,8,0
DB 0,96,96,0,0,0
DB 32,16,8,4,2,0
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB

62,81,73,69,62,0
0,66,127,64,0,0
122,73,73,73,70,0
34,65,73,73,54,0
15,8,8,126,8,0
39,69,69,69,57,0
62,73,73,73,49,0
1,97,17,9,7,0
54,73,73,73,54,0
6,9,9,9,126,0
0,54,54,0,0,0
96,54,54,0,0,0
8,20,34,65,0,0
20,20,20,20,20,0
0,65,34,20,8,0
2,1,88,5,2,0
62,65,93,89,78,0

DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB

124,18,17,18,124,0
127,73,73,73,54,0
62,65,65,65,34,0
127,65,65,65,62,0
127,73,73,65,65,0
127, 9 , 9: I, I, 0
62,65,65,81,114,0
127,8,8,8,127,0
0,65,127,65,0,0
32,64,64,64,63,0
127,8,20,34,65,0
127,64,64,64,64,0
127,2,12,2,127,0
127,4,8,16,127,0
62,65,65,65,62,0
127,9,9,9,6,0
62,65,81,33,94,0
127,9,25,41,70,0
34,69,73,81,34,0
1,1,127,1,1,0
63,64,64,64,63,0
31,32,64,32,31,0
127,32,24,32,127,0
99,20,8,20,99,0
3,4,120,4,3,0
97,81,73,69,67,0

; SPACE
:!

..

;#
;$
;%

..

;11:

;(
;)

;.
;+

..

..

;-

;/
;0
;1
;2
;3
;4
;5
;6
;7
;8
;9

,.
;<

,-

;>
;1
;@

;A
;B
;C
;D
;E
;F
;G
;H
;1
;J
;K

;L
;M
;N
;0
;P
;Q

;R
;S
;T
;U
;V
;W
;X
;Y
;Z

END

4-125

.<

z

SCROLL
This subroutine will scroll whatever is displayed on the LCD
to the right until the screen is clear. It first reads in three
columns of data. It then writes three columns of data with
the HL pointer shifted by one byte. This will shift the displayed data by one column. This is repeated until the

entire LCD has been shifted by one column. Then the entire
operation is repeated until all the displayed data is shifted
off the screen.
This subroutine could easily be adapted to scroll the display
to the left if desired.

N8080

PUBLIC SCROLL
EXTRN READ, GRAPH
SCROLL:
;SCROLLS DISPLAY TO THE RIGHT UNTIL CLEAR
INPUT: NONE
OUTPUT: NO REGISTERS ARE CHANGED
SCREEN IS SCROLLED UNTIL CLEAR
;SAVE ALL STATES
PUSH PSW
PUSH B
PUSH D
PUSH H
;SET UP ALL
MVI
REPEAT: MVI
STA
MVI
MVI

THE POINTERS
D,96
A, 0
BUFFER
B,3
C,O

;READ THE DATA
L.READ: LXI H,BUFFER+l
CALL READ
LXI H, BUFFER
CALL GRAPH

;LOOP UNTIL SCREEN IS CLEAR (96 CYCLES)
;CLEAR FIRST BYTE IN BUFFER
;READ 3 COLUMNS ALWAYS
;START WITH COLUMN ZERO
;SET HL TO POINT TO BUFFER+l
;SET HL TO SHIFT THE DATA
;REDRAW THE SHIFTED DATA

;MOVE LAST COLUMN OF LAST READ INTO FIRST COLUMN OF NEXT WRITE
LDA BUFFER+3
STA BUFFER
;UPDATE COUNTERS
MOV A,C
ADI 3
MOV C,A
CPI 96
JNZ L.READ
DCR D
JNZ REPEAT

;INCREMENT COLUMN NUMBER
;CHECK IF DONE WITH ONE CYCLE
;DECREMENT LOOP COUNT
;LOOP UNTIL DONE WITH ALL CYCLES

;RESTORE STATES
POP H
POP D
POP B
POP PSW
RET
BUFFER: DS 4
END

4-126

.

:£>
Z

OTHER APPLICATIONS

There are many different types of LCOs that can be controlled by the MM58201. Some of these are shown in Figure
18.

Given a string of numbers to display, this subroutine simply
looks up the data it needs from a look-up table and stores
this data in a buffer. After every three digits, the subroutine
sends this data to the MM58201 to be displayed. The digit
backplanes are wired backward in groups of three to simplify the software. The subroutines that this subroutine uses
are very similar to the equivalent subroutines in the LCD dot
matrix application. Since there is only one MM58201, the
software is simpler. There is no need to calculate which
MM58201 chip select to enable.

Up to 24 seven-segment digits can be controlled by one
MM58201. The software to control a multiplexed seven-segment display is not too much different from that of the previous application. The software is simpler because only one
MM58201 is needed instead of four. A logic diagram for a
six-digit multiplexed seven-segment LCD display is shown in
Figure 19 and the software to control it is in Listing 5.

w
U1
o

BP7 BP2
BP6 BPI

o" 0"
BP4

SI

S2

0" 0" 0···0
" "
S4

S3

S5

S6

S24

I
I

-

I I-I I-I I-I
1 1:1 1:1 1:1

BPI

I
I

I I-I I-I I-I
1 1:1 1:1 1:1

BP2

-

Ell

S24

SI

111111111111111111111111
111111111111111111111111

BPI

BP2

S24

SI

TLIB/5606-21

FIGURE 18. Typical LCD Connections to the MM58201

4-127

AN-350

12V
iV
10k

12V

Ll

,

33k

)

OUTPUT
PORT

!

I\)
Q)

4

)

lOOk

)

68k

12V

"-

5V

26

i....-.

BPl

VTC

BP2

10k

BP3

CS

BP4

10k

11

10

~

12V
25

)

I (iJ 0

12V
140

-:.=

)

,,

:~~22
24 ClK

10110158201

BPS
BP6

12

,

13

BP7

23 DATA IN
330k

:906

± I' r
21 RC OSC

12V

S6

000lp

S5

S4

I'

~~D

19

r;a

~

0 0

0" " Ll Ll
~

"

16
15
14

~

12
BP8
Sl 11
10
S2
S3

I'
TUB/5606-22

FIGURE 19. Diagram of a Six-Digit Seven-Segment LCD Multiplexed Display

l>
Z

N8080
;INITIALIZE THE 810
MV A,O
OUT 27H
MVI A,OFFH
OUT 24H

W
U1

o

LXI BC,TEST
MVI E,6
CALL NUMBER
RST 6
TEST:

DB 1,2,3,4,5,6

;SUBROUTINE TO DISPLAY NUMERALS ON LCD DISPLAY
INPUT
BC-POINTS TO BCD DATA STRING
E -LENGTH OF DATA STRING (MULTIPLE OF 3)
OUTPUT
-NO REGISTERS DISTURBED
-DATA STRING IS DISPLAYED
NUMBER: PUSH
PUSH
PUSH
PUSH
DIG3:
LOOP:

PSW
B
D
H

MVI D,3
LDAX B
LXI H,TABLE
ADD L
MOV L,A
MVI A,OOH
ADC H
MOV H,A

;SAVE STATES

;LOOP FOR 3 DIGITS
;CALCULATE ADDRESS INTO TABLE

MOV A,M
PUSH PSW

;GET OUTPUT DATA FROM TABLE

LXI
MOV
ADD
MOV
DCR
POP
MOV

H,DATA
A,L
D
L,A
L
PSW
M,A

;STORE INTO DATA BUFFER

INX
DCR
DCR
JNZ

B
E
D
LOOP

;INCREMENT POINTER TO DATA STRING
;DECREMENT # OF DIGITS
;DECREMENT :5 DIGIT COUNT
;IF NOT THIRD DIGIT THEN LOOP BACK

LXI H,DATA
CALL WRITE

;DISPLAY THESE THREE DIGITS

MOV A,E
ANA A
JNZ DIG:5

;CHECK FOR LAST DIGIT OF DATA STRING

POP
POP
POP
POP
RET

;RESTORE STATES

H
D
B
PSW

WRITE:
; DISPLAY 3 DIGITS
INPUT
HL-POINTS TO START OF DATA
E -COLUMN ADDRESS
OUTPUT
-NO REGISTERS DISTURBED
PUSH
PUSH
PUSH
PUSH

PSW
B
D
H

MOV A,E
RLC
RLC
MOV E,A

;SAVE STATES

;GET ADDRESS BITS AT HIGH END OF BYTE

4·129

o

.

1.1)
C")

z

<

;OUTPUT FIVE ADDRESS BITS
MVI C,5
W.LOOP: MOV A,E
RLC
MOV E,A
MVI A,lOOOOOOOB
ANA E
CALL OUT
DCR C
JNZ W.LOOP
;SIGNAL FOR A WRITE
MVI A,OOH
CALL OUT
;OUTPUT THE DATA
MVI B,3
DIS1:
MVI C,B
MOV D,M
DIS2:
MOV A,D
RRC
MOV D,A
ANI 10000000B
ORI OOOOOOOlB
CALL OUT
DCR C
JNZ DIS2
INX H
DCR B
JNZ DIS1
POP
POP
POP
POP
RET

H
D
B
PSW

;ROTATE ADDRESS
;GET MSB &: ENABLE CHIP SELECT BIT
;OUTPUT BIT WITH CHIP SELECT
;LOOP UNTIL ADDRESS IS OUT

;OUTPUT A ZERO BIT
;3 BYTES OF DATA
;8 BITS PER BYTE
;ROTATE DATA
;GET NEXT BIT
;DISABLE CHIP SELECT
;LOOP UNTIL DONE WITH BYTE
;LOOP UNTIL DONE WITH 3 BYTES
;RESTORE STATES

OUT:
;SUBROUTINE TO OUTPUT ONE BIT TO THE MM58201
INPUT
A -DATA BIT IN MSB POSITION
OUTPUT
-NO REGISTERS DISTURBED
-OUTPUT ONE BIT TO 58201
PUSH PSW
OUT 20H
ORI OlOOOOOOB
OUT 20H
ANI 101l11l1B
OUT 20H
POP PSW
RET
DATA:
TABLE:

DS
DB
DB
DB

;CLOCK HIGH
;CLOCK LOW

3
OOllllllB, OOOOOllOB, OlOllOllB, OlOOllllB
OllOOllOB, OllOllOlB, OlllllOlB, OOOOOlllB
OlllllllB, OllOllllB

END

SUMMARY
The MM58201 makes it easy to interface a multiplexed LCD
display to a microprocessor. It is simply a matter of connecting the display and the microprocessor to the chip, choosing
a value for VeT, then interfacing your program to use the

subroutines listed here or similar ones. Multiplexed LCOs
are the perfect way to cut down on display interconnections
while still taking advantage of the LC~'s low power consumption and high contrast ratio-and the MM58201 makes
them easy to use.

4-130

The MM58348/342/3411
248/242/241 Directly Drive
Vacuum Fluorescent (VF)
Displays

National Semiconductor
Application Note 371
David Stewart

1.0 INTRODUCTION

The MM58348/248 devices use a two control line data input
format (data in and clock) which enables the 40-pin part to
have 35 display outputs. To load data into the controller, a
start bit precedes the 35 data bits. The start bit is a logical
"1" clocked into the IC by the first clock pulse. Next, 35
data bits are clocked into these parts. The start and data
bits are shifted in on the rising edge of the clock. As the
data is clocked into the IC, the start bit is shifted down the
35-bit register. On the rising edge of the 36th clock pulse,
data is transferred to the display register and the start bit is
shifted into the control latch. On the negative edge of the
clock, the shift register is cleared. The display register feeds
the level shifters that translate 5V CMOS levels to the 35V60V required by the display. The MM5B348/248 devices are
not cascadable. Typically, these devices would perform the
segment refresh drive in a multiplexed multi-digit system. A
functional block diagram is shown in Figure 2.

National has produced a family of high voltage display drivers which is specially designed for use with vacuum fluorescent (VF) displays. These circuits are fabricated using a
standard metal gate CMOS process which has been extended to allow a maximum operating voltage of 60V, thus
enabling the design of bright multiplexed displays. In this
way, the advantages of CMOS are retained (low power),
while the range of applications for this technology is increased. Many of today's high voltage MOS display drivers
require the use of one external resistor per display output,
and this leads to a considerable increase in component
count and board area. National's display drivers, however,
incorporate an on-board pull-down resistor structure which
removes these disadvantages.
This application note is intended to demonstrate several
ways in which these display drivers can be configured to
drive and control a wide range of VF displays. Although particular attention will be given to one specific display, a 32character alphanumeric display, the design is presented in
such a way as to enable easy extrapolation to the system
designer's specific applications.
2.0 FUNCTIONAL DESCRIPTION
There are six circuits in this new family of high voltage VF
drivers and they can be sub-divided according to maximum
operating voltage, number of display outputs, data interfacing requirements and ability to be cascaded. Each of the
three circuit configurations is available with maximum operating voltages of 35V (MM583XX) or 60V (MM582XX). Due
to the nature of the output stage required to attain high voltage operation of CMOS devices, the drive capabilities of the
display output decrease as maximum operating voltage increases. Therefore, to maintain the option of trading off display voltage against drive current, each circuit has a high
voltage (reduced drive) version and a low voltage (high
drive) version. The three circuit configurations can be identified by the number of display outputs they contain (e.g., 20,
32 or 35 outputs). In all cases, data is entered serially into a
5V internal CMOS shift register. This data is latched to the
output either by an external enable control signal
(MM58241/341/242/342) or automatically by a leading
start bit in the data stream (MM58248/348). Figure 1 shows
how the 6 device numbers correspond to the different circuit
configurations and operating voltages.

Outputs

Each of the MM58241/341 and MM5B242/342 devices has
a serial data output pin which is connected directly to the
last stage's output of the shift register. By connecting data
out from one device to the data in pin of another device, and
by holding each circuit's enable constantly high, the display
drivers can be cascaded. The result is a shift register with a
variable number of bits, depending on the mix of circuits
used.
The MM58341 1241 1342/242 devices also have a blanking
control input. A logic high on this pin turns all outputs off,
while still retaining the display data. If a logic "0" is then
applied, the display data will return unchanged. Consequently, the brightness of the display is proportional to the
duty cycle of this blank signal. A functional block diagram of
these devices is shown in Figure 3.

35V

SOV

20

MM58342

MM58242

32

MM58341

MM58241

MM58348

MM58248

35

w

......
.....

The MM58341/241/342/242 devices use a three control
line data input format (data in, clock and enable) and have
either 32 or 20 display outputs, as given by A'gure 1. This
configuration sacrifices some outputs to enable cascading,
enhance control signal flexibility, and provide brightness
control. Here again, data is shifted into the shift register on
the riSing edge of clock, but no start bit is needed. Instead,
the enable signal is taken high to input data to the chip.
When the enable is taken low, the contents of the shift register are loaded into the display register. Again, the display
register feeds the level translator and display driver outputs.

Operating Voltage

Number
of

.

»
z

20 and 32 output drivers use envelope enable
data format and may be cascaded.
35 output (5 x 7 dot matrix) drivers use start bit
data format.

FIGURE 1. The Complete VF Display Driver Family

4-131

•

,......

.

C")

r---------------------------------------------------------------------------------------~

BLOCK DIAGRAMS

z

OUTPUT
35

IVTIIVDSI~5V

HORIZDNTAL
PUNCHTHROUGH

TLIF/8349-4

FIGURE 4. Horizontal Punchthrough In a CMOS P-Channel Transistor

4-144

SOURCE (SI

GATE (GI

DRAIN (01
EQUIPOTENTIAL
LINES

+5V 0-....--4----1

CORNER
REGION

DEPLETION
REGION

TL/F/6349-5

FIGURE 5. Surface Avalanche Breakdown in a CMOS P-Channel Transistor
ceptable in normal applications. One occasion where such
resistors are used is where it is only the ratio between the
resistors which is important, and not their precise values, for
instance in a voltage divider. Under these circumstances,
any change in the nominal resistance value will be reflected
in all the resistors and hence the divider will operate as
designed.
As was pointed out above, such resistors are normally
formed by making use of the sheet resistance of diffusion. In
particular, the diffusion with the highest value of sheet resistance is used, and this is p-material. Hence, the structure
shown in Figure 6, known as a pinched p - resistor, is common, and it is clear that this device is in fact a p-channel
junction field effect transistor (JFET). The theory of JFET
operation is described by Glaser and Subak-Sharpe (4), and
because the p - diffusion process is followed by n + diffusion it can be seen that the JFET gate completely surrounds
the p-type channel region in the form of n + and n - (substrate) material, which is tied to 5 volts. For this reason, the
pinch-off voltage is very low (typically 10V) and so these
pinched resistors are widely used in low voltage applications. Further, p- diffusion sheet resistance is a parameter
which has a wide process spread, i.e. 4.5-7.0 kfl per
square, and although the pinched resistor technique increases this nominal resistance value due to depletion effects, such resistors are difficult to specify in advance.
If the large changes in resistance value are not tolerable
then p + diffusion resistors in the n - substrate are a viable
alternative, for two reasons. First, because of the doping
profile of p+ diffusion, the JFET depletion effects are reduced, and consequently such resistors have a much higher
pinch-off voltage. Second, the nominal resistance of p+
diffusion is much more stable over the process range, although its value is far lower (40-80n per square). For this
latter reason, p + resistors occupy large areas for relatively
small values.

High Voltage CMOS
Referring to the 'Ideal' VF Driver section, one of the principal aims of this design is that a standard fabrication process
be used. Bearing that in mind then, there follows a study of
possible ways by which the original VF display driver specification could be realised or even enhanced.
HIGH VOLTAGE TRANSISTORS
The simpler of the two operating voltage limitation factors to
overcome is horizontal punchthrough. From Figure 5, it is
clear that in order to increase the drain source voltage at

which the depletion regions combine the distance between
the drain and source must be increased. This has the effect
of lengthening the transistor channel, and the consequences of such action should be considered. The basic
equations which describe the mode of operation of the MOS
transistor are derived by A.M.I. (5), and from these, increasing the channel length (L) will result in lower drain source
current (IDS), lower gain factor (f3), and higher threshold
voltage (VT). All of these effects will degrade the transistor
performance, although it is worth noting that the aspect ratio
(W/L), Le. the ratio of channel width (W) to its length, is a
major component of the transistor equations. Hence, some
performance can be salvaged by increasing the channel
width to return the aspect ratio to its original value. Unfortunately, this approach increases gate area and hence parasitic capacitances, and so the resulting high voltage transistor is still inferior to its low voltage equivalent.
The other mechanism which leads to high voltage breakdown in MOS transistors is surface avalanche breakdown,
and this phenomenon can only be overcome at a cost. As
was explained previously in reference 3, this avalanche effect is caused by a region of high electric field which can
lead to electrons with energy levels high enough to start a
chain reaction of collisions within the silicon lattice. The
electric field at the corner (~corner) determines whether this
phenomenon will occur and reference 3 points out that
~corner is inversely proportional to gate oxide thickness
(t ox). Armed with this information, initial experiments were
carried out with long channel devices having tox values
ranging from the standard process value of 1aaoA up to a
maximum possible value of 2300A. In practice, the oxidation
cycle had to be altered to allow these different oxide thicknesses to be fabricated without affecting other process parameters. As a result of these experiments, it was found that
surface avalanche breakdown occurred at approximately
40V with tox = 2300A. An alternative experiment involved
making use of the oxide which isolates the silicon from the
metal inter-connect, that known as field oxide. Field oxide is
typically 8800A thick, and hence it was felt that using this as
gate oxide on long channel devices could provide the desired high voltage performance. However, field oxide MOS
transistors were found to have breakdown voltages in excess of 70V, and for this reason it was decided that the VF
driver outputs would be designed for a maximum voltage
swing of 60V. The high breakdown voltage, however, is
achieved at a cost in terms of performance. Using the basic
MOS transistor equations of reference 5, and noting that
increasing tox will decrease gate capacitance (Cox), it is
clear that low values of gain factor (f3 ~ 1 JLAIV2), and high

4-145

co

.

1'0

('I)

z

C

t.ft.f58341
OUTPUTS
(19)
DIGIT 19 "ON" \

(20)

(1)

""----------------------------------------------_ _ _ _ _ _...J1 DIGIT 20 "ON" \"'_ _ _ _ _ _ _ _ _ _ _ _ __
_ _ _ _ _ _ _ _ _ _ _ _....J1 DIGIT 1 "ON" \ _ _ _ _ _ _ __
1 DIGIT 2 "ON" ' -

(2) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-J

TLIF/8683-4

FIGURE 4. Timing Diagram

4-150

In between digit strobes, the segment data is updated. The
first 34 bits of segment data are set up in the dot driver and
the blanking signal is activated to disable all 20 digits. The
35th bit of data is clocked in, updating the segments. Since
the MM58348 resets its internal shift register each time the
data is latched, it can accept all but the final data bit while
still displaying the previous digit. The digit driver is then
clocked, shifting the digit strobe to the next position. The
enable is then brought low, enabling the next digit. Finally
blanking control is deactivated and the data displayed.
During the time which the blanking control is high, the order
in which the segments or the digits are updated is not critical. Since this occurs while the display is blank. The digit
driver may be clocked first, or the segments could be
changed first. In general, the philosophy for the driving this
VF multiplexed display is outlined in Figure 5.
LOAD GRID DRIVER
WITH A "1"

HOST INTERFACE AND PROGRAMMING

With a minimal amount of address decoding and an eight bit
latch, COPS can be interfaced with a common microprocessor bus. When a character has been input into the host to
be displayed, the ASCII value of that character is latched
into the eight bit latch (MM74HC373) and is read on the L
port (LO-6) of the COPS. The MSB of the ASCII value must
be a logic 1. This MSB is the signal to the COPS that a new
character is being presented. Once the character has been
stored, an interrupt is sent from the COPS to the host
through the 0-0 port. The COPS checks for a new character
being input every 200 J.Ls. If a character is being sent, 1 ms
is required to store that character in the RAM of the COPS.
With the COPS controlling the display, the host micro-processor is not being tied down with character look-up and display refresh. A simple flowchart of the host requirements is
shown in Figure 6.
COPS SOFTWARE

There are four main sections of the COPS software. The
first section, the initialization of the RAM, sets up the RAM
as shown in Figure 7. A '0' is stored in all of the LSB positions and a '2' is stored in all of the MSB positions. Since
the COPS is in a constant display loop, this is necessary to
insure a blank display. 20H is the ASCII value of a space.
With the RAM set up in this way, a maximum of 28 characters can be stored in RAM. Since the display in this application is only 20 characters long, RAM locations M 1,4 to
M 1,11 and M3,4 to M3,11 are not used. RAM locations 1,12
to 1,15 and 3,12 to 3,15 are used as temporary storage
throughout the program and cannot be used for character
storage.

TL/F/6663-5

FIGURE 5. Flowchart for Display Drivers

YES

The second part of the program, stores the new characters
sent by the host CPU in RAM. Once a character has been
sent, this section of the program checks the ASCII value of
that character to see if it is a control character or a display
character. If it is a display character, the character is stored
in RAM and an interrupt is sent to the host. There are three
control characters which the COPS program will recognize.
Cursor forward (ASCII value 08H) moves the cursor forward
without destroying the data, cursor backwards (ASCII value
OCH) moves the cursor backwards without destroying the
data, and return (ASCII value ODH) will clear the display and
put the cursor at the beginning of the display. To recognize
and store a character, 1 ms is required.

EXCLUSIVE OR
eASCIl VALUE
WITH BOH

OUTPUT ASCII
VALUE TO
DATA BUS

The third part of the program, the display loop, is the heart
of the program. Unless a new character has been detected,
the program is always in this loop. This section does the

TL/F/6663-6

FIGURE 6. Host System Flowchart

4-151

15

14

LSB
Chr1

LSB
Chr2

13

12

11

10

9

7

8

5

6

3

4

MSB
LSB Temp. ASCII
Pointer Pointer STORAGE
MSB
Chr 1

MSB
Chr2

2

0

1

LSB
LSB
LSB LSB LSB LSB LSB LSB
LSB
LSB
LSB
LSB
LSB
LSB
MO
Chr3 Chr4 Chr5 Chr6 Chr7 Chr8 Chr9 Chr10 Chr 11 Chr 12 Chr 13 Chr14 Chr 15 Chr 16
LSB
LSB
LSB
LSB
M1
Chr17 Chr18 Chr 19 Chr20

MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB
M2
Chr3 Chr4 Chr5 Chr6 Chr7 Chr8 Chr9 Chr10 Chr 11 Chr12 Chr 13 Chr14 Chr15 Chr16
MSB MSB MSB MSB
M3
Chr17 Chr 18 Chr 19 Chr20

Temp. Storage of Pointer

FIGURE 7. COPS RAM Map

I Column 1 I

I

I

I

IPAD

Matrix

PAD

Binary

0001001111101010001001000010100000111110

Hex.

13

I

Column 2

EA

I

Column 3

24

I

Column 4

28

I

Column 5

3E

FIGURE 8
character font look-up, shifts the character data out the
COPS serial port to the MM58348, and controls the
MM58341 through the four bit parallel port (GO-4). Because
the most significant nibble of the program counter is used
as part of some COPS instructions, it is important that parts
of the program are located at specific locations in ROM.

second byte. In this case, the third byte of data would be
stored at 2E1 H. The fourth byte of data is stored at 300H
plus the ASCII value of the character or at 341 H for the
letter 'A'. The final byte of data is stored 40H from the fourth
byte or at 381 H. Remember the LSB of each byte is stored
first. Table I shows the locations in ROM and the values
stored in them for the letter 'A'.
This application shows a VF display controller designed
with a minimum number of IC's. If additional information
about VF displays or VF display drivers is required,
refer to Application Note AN-371 (The MM58348/
342/341/248/242/241 direct drive Vacuum Fluorescent
(VF) Displays.

The final part of the program is the data. Each character is
represented by a 5 byte data word. Each byte of the data
word is stored at a different location in ROM. Fonts for characters with the ASCII values from 20H-5AH have already
been stored in ROM. These characters can be changed or
more characters can be added. The only limitation to the
number of characters is the amount of available ROM.
CREATING THE 5 BYTE DATA WORD
Any number or combination of pixels or dots can be turned
on at a time. To create a new character, it is easiest to first
create a binary string which represents the character. A '1'
in the binary string will turn on the pixel, a '0' will turn it off.
To create this string, start in the upper left corner of the
matrix and go down the columns.
The letter 'A' (Figure EJ) would have a binary string shown in
Figure 8. The data must be padded to make it an even 5
bytes in length. The pad at the beginning of the data (0001)
is used as the leading 1 for the MM58348. The one bit pad
at the end of the binary string must be a O. If a 1 were sent
as the pad, it would be used as the start bit for the next
character.
The 5 byte data word that would be stored in ROM and
represent the letter 'A' would then be 13EA24283E.

TABLE I. Character Data of 'A'
and Its Locations In ROM
Address
In ROM

Data
Stored

0241H
02A1H
02E1H
0341H
0381H

31
AE
42
82
E3

•
••• •••
•••••••
• •

STORING THE DATA IN ROM
The 5 bytes of data are stored in 5 different locations in
ROM. The first byte of data will be stored, LSB first, at location 200H plus the ASCII value of the character. For example, the ASCII value of the letter' A' is 41 H. The first byte of
data for the letter 'A' would be stored, least significant bit
first, at 241 H. The second byte of data is stored at the location of the first data byte plus 60H or in this case at 2A 1H.
The location of the third byte is 40H plus the location of the

TLlF/8683-7

FIGURE 9. 5 x 7 Character as Stored in ROM

4-152

Section 1 of COPS Software

.CHIP 424C
;DEFINES COPS CHIP
;THIS SECTION INITIALIZES THE RAM IN THE COPS BY LOADING A
;2 IN THE MSB AND A 0 IN THE LSB LOCATIONS OF EACH CHARACTER.
;IT ALSO STOPS THE CLOCK AND SETS THE POINTER AT THE FIRST
;CHARACTER OF THE DISPLAY.
RESET:

CLRA
LBI 3,15
JSR CLEAR2
LBI 2,15
JSR CLEAR2
LBI 1,15
JSR CLEAR
LBI 0,15
JSR CLEAR

;LOADS A 2 IN ALL
;MSB LOCATIONS
;LOADS A 2 IN ALL
;MSB LOCATIONS
;LOADS A 0 IN ALL
;LSB LOCATIONS
;LOADS A 0 IN ALL
;LSB LOCATIONS

CLRA
XAD 1,15
CLRA
AISC 15
XAD 1,14

;LOADS POINTER IN RAM
;MSB IN 1,OF

RC
XAS
JMP START

;RESETS CARRY TO
STOP CLOCK

CLEAR:

CLRA
XDS 0
JMP CLEAR
RET

;CLEARS REGISTORS

CLEAR2:

CLRA
AISC 02
XDS 0
JMP CLEAR2
RET

;PUTS A 2 IN REGISTORS

;LSB IN 1,OE

Section 2 of COPS Software

;THIS SECTION OF CODE IS ONLY EXECUTED WHEN A NEW
;CHARACTER HAS BEEN ENTERED. IF THE CHARACTER IS
;A CONTROL CHARACTER, THE CURSOR IS MOVED ACCORDINGLY,
;OTHERWISE THE CHARACTER IS STORED IN THE RAM OF THE COPS.

NEW:

;NEW CHARACTER HAS BEEN ENTERED
LBI 1,OC
;DUMMY POINTER
INL
;READS ASCII FROM
XIS 0
;DATA BUS
X0
LDD 1,OD
RC
;CHAR. MSB=O THEN YES
AISC 15
;MSB < > 0 THEN NO
JMP SPECIAL
AISC 01
LDD 1,OE
;STORE ASCII IN RAM
CAB
LDD 1,OF
XABR
LDD 1,OC
;MSB IN 1,OC
X2
LDD 1,OD
;LSB IN 1, OD
X0
4-153

.

C) . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
~
~

Section 2 of COPS Software (Continued)

z

 1000 pF
Oriven by OS8830, OM? 440
"Zero" Quiescent Power

Connection Diagrams
Dual-In-Llne Package

Metal Can Package
V'

8 NC

NC 1

INPUT A 2

v-

V-

-+---1 JlIO---+-- 7

OUTPUT A

-+---1 JlIO---+-- 5

OUTPUT B

3

TL/F/5852-1

Note: Pin 4 connected to case.

INPUT B 4

Top View
Order Number DS0025CH
See NS Package Number H08C

TL/F/5852-2

Top View
Order Number DS0025CJ-8
or DS0025CN
See NS Package Number J08A or N08E
Dual-In-Llne Package

NC

NC

0 UT A

NC

IN A

NC

vTLlF/5852-3

Top View
Order Number DS0025CJ
See NS Package Number J14A

5-10

c

Absolute Maximum Ratings

If Military/ Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(V+ - V-)Voltage Differential
Peak Output Current

20V

Maximum Power Dissipation- at 25·C
8-Pin Cavity Package
14-Pin Cavity Package
Molded Package
Metal Can (TO-5) Package

1.5A
O·Cto + 85·C
300·C

Lead Temperature (Soldering, 10 sec)

Max
70

o

Temperature

- 65·C to + 150·C

Operating Temperature

N

U1

Min

100mA

Storage Temperature

o

o

v+ V- Differential Voltage

25V

Input Current

en

Recommended Operating
Conditions

(Note 1)

1150 mW
1410 mW
1080 mW
670mW

* Derate 8-pin cavity package 7.8 mW;oC above 25·C; de-

rc

rate 14-pin cavity package 9.5 mW
above 25·C; derate
above 25·C; derate metal
molded package 8.7 mW
can (TO-5) package 4.5 mW;oC above 25·C.

rc

Electrical Characteristics (Notes 2 and 3) See test circuit.
Symbol

Parameter

Conditions

Min

Typ

Max

Units
ns

tdON

Turn-On Delay Time

CIN

= 0.001 p.F, RIN =

15

30

Rise Time

CIN

= 0.001 p.F, RIN =

= 0.001 p.F

25

50

ns

tdOFF

Turn-Off Delay Time

CIN = 0.001 p.F, RIN
(Note 4)

on, CL
on, CL
= on, CL

= 0.001 p.F

tRISE

= 0.001 p.F

30

60

ns

tFALL

Fall Time

CIN = 0.001 p.F, RIN
CL = 0.001 p.F

on,

I (Note 4)
I (Note 5)

=

Pulse Width (50% to 50%)

CIN = 0.001 p.F, RIN = on,
CL = 0.001 p.F (Note 5)

VO+

Positive Output Voltage Swing

VIN

= OV,IOUT = -1 mA

VO-

Negative Output Voltage Swing

liN

= 10 mA,lOUT = 1 mA

PW

60

90

120

ns

100

150

250

ns

500
V+-1.0

ns

V+-O.7V
V-+O.7V

V
V-+1.5V

V

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the O'C to 70'C range for the DS0025C.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Parameter values apply for clock pulse width determined by input pulse width.
Note 5: Parameter values for input width greater than output clock pulse width.

Timing Diagram
5V

A. Input pulse width
clock pulse
width

VIN

>

B. Input pulse width
sets clock pulse
width

Clock pulse
output

OV

~ON j

Input waveform:
PRR = 0.5 MHz
Vp.p = 5.0V
t, = tf ~ 10 ns

VIN

10%

~

k-~O%
50%

PW

90%

Pulse width:
A. 1.0 /Ls
B. 200 ns

5V

90%

-I,ise

"r---~-O-F-F-------

-!iJ10%...,
50%
90%

5·11

V3

= OV

V2

=

Your

1

---l

OV

-16V

-I'all

TL/F/5852-5

o

o
LI)
N

o

o

Typical Application

U)

C

!Pz

TlIF/5852-4

AC Test Circuit
, - . -. .-oVOUTI

L.._,,-o VOUT2
TL/F/5852-6
'Ql is selected high speed NPN switching transistor.

Typical Performance
Transient Power vs Rep. Rate

DC Power (Poe> vs Duty Cycle

400

160

~z

i

.! 300
a:

~
en
z
a:

.-'"

120

Q

i=
~

~

.-~

140

200

80

1----+---.,r--boi~f--hioC4-+__I

Ci
a:

60

I--I--I-l~-+-....,i'~

~

~

40 I--I-+ho.,rr"'--;I---t--t--t--i

Q

20

...

100

1.5

1.0

.5

100

~

1-J[A,;tC-l-+~I-+-+-+__I

10

2.0

20

30

40

50

60

10 85
TlIF/5852-8

PULSE REPETITION RATE (MHz)
DUTY CYCLE (%)

TL/F/5852-7

V+_V;~2(DC)

Poe

Maximum Load Capacitance
3200 I-+--+--If--+--+--+-I---I--I
""""O+--+---.lh~/'+I....._,-I.J.""".v_o-+__Iv_-_"to!20'/_.,,-+_1_"-1'

:e. 2800

-'

ri:i

~

1\'

,~

I\.

K,

1200

g 800
Q

400

1\'

"' . '.

900

DS002SC:V1'-V-·2OY.TA-2IC

..5.

f'....

.-= 100

'" I'

i

Q

~

r---..""'. . . . ""

I-+--+'......,~+--+---f"""'~.....,..-I

"r':t-...
........

~"-

OUTPUT ttULSEwlDTH VS. t.,.fOR LONG
INP\l'"'lSES.

FORINPlITPUlSE <85

2400
"'V
2000 I-.ll-llt+--I~+-'~-+-l-+__I

...
'- 1600

::5

Output PW Controlled by CIN
1100

~

t""-~

~=J:_:g<_.~lo___.!J_:L,~_~;l:,"_"""JfYi~~'/'r.:;;;;~::;~~

100

OL-.................--'--J,.--''--..L..-~........- l

I-tI-t....... r-t-

l/

1-1-

D~932~RIVEt ~~!"D t-I-~
DRIVER

f.)

1). ~F-

1/

~~ ~
~L,..oor:;;.
son PUllUP
I~~

I
I

200

0.2 0.4 0.& 0.8 1.0 1.2 1.4 1.6 1.8 2.0

I.~

OUTPIITPUlStWiDTH-INPIITPUWWlDTH
PLUSSO ••.

500
300

+ RoCtN In ~

&00

1000 1400 1800 noD
CIN (pF)

FREQUENCY (MHz)

TL/F/5852-10

TL/F/5852-9
IMAX = Peak Current delivered by driver

< (PMAX) (lk)-(V+ - V-)2 (DC) < ~

C
L

(f) (lk) (V+ - V-)2

I
VeE - ~
MIN Rl - lk

V+ - V-

5"12

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Applications Information

N
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Circuit Operation

Transient Output Power

Input current forced into the base of 01 through the coupling capacitor CIN causes 01 to be driven into saturation,
swinging the output to V- + Vcdsat) + VOiode.

The average transient power (Pad dissipated, is equal to
the energy needed to charge and discharge the output capacitive load (Cd multiplied by the frequency of operation
(f).

When the input current has decayed, or has been switched,
such that 01 turns off, 02 receives base drive through R2,
turning 02 on. This supplies current to the load and the
output swings positive to V+ -VSE.

r__--.._-ov+

o

PAC = CL x (V+ _V-)2 x f
ForV+ - V400 mW.

=

20V, f

=

(2)

1.0 MHz, CL

=

1000 pF, PAC

=

Internal Power
"0" State

Negligible «3 mW)

"1" State
Pint =
..........__....- 0 OUTPUT

=

INPUT

(V+_V-)2
R2
x Duty Cycle
80 mW for V+ -V-

=

20V, DC

(3)

=

20%

Package Power Dissipation
Total average power = transient output power
power.

Rt

+

internal

250

Example Calculation

~--~,---~~------~v-

TLIF/58S2-11

FIGURE 1. 050025 Schematic (One-Half Circuit)
It may be noted that 01 must switch off before 02 begins to
supply current, hence high internal transients currents from
V - to V + cannot occur.

Fan-Out Calculation

How many MM506 shift registers can be driven by a
DS0025CN driver at 1 MHz using a clock pulse width of 200
ns, rise time 30-50 ns and 16V amplitude over the temperature range O· -70·C?

Power Dissipation:
At 70·C the DS0025CN can dissipate 870 mW when soldered into printed circuit board.

The drive capability of the DS0025 is a function of system
requirements, i.e. speed, ambient temperature, voltage
swing, drive circuitry, and stray wiring capacity.

Transient Peak Current Limitation:

The following equations cover the necessary calculations to
enable the fan-out to be calculated for any system condition.

Average Internal Power:

From equation (1), it can be seen that at 16V and 30 ns, the
maximum load that can be driven is limited to 2800 pF.

Transient Current

Equation (3), gives an average power of 50 mW at 16V and
a 20% duty cycle.

The maximum peak output current of the DS0025 is given
as 1.5A. Average transient current required from the driver
can be calculated from:

For one-half of the DS0025C, 870 mW -:- 2 can be dissipated.

1= CL(V+-V-)

(1)

tr
Typical rise times into 1000 pF load is 25 ns. For V+ - V= 20V, I = 0.8A.

435 mW = 50 mW

+

transient output power.

385 mW = transient output power.
Using equation (2) at 16V, 1 MHz and 350 mW, each half of
the DS0025CN can drive a 1367 pF load. This is less than
the load imposed by the transient current limitation of equation (1) and so a maximum load of 1367 pF would prevail.
From the data sheet for the MM506, the average clock
pulse load is 80 pF. Therefore the number of devices driven
is 1367/80 or 17 registers.
For further information please refer to National. Semiconductors Application Note AN-76.

5-13

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~National

~ Semiconductor
OS0026/0S0056 5 MHz Two Phase MOS Clock Drivers
General Description
OS0026/0S0056 are low cost monolithic high speed two
phase MOS clock drivers and interface circuits. Unique circuit design provides both very high speed operation and the
ability to drive large capacitive loads. The device accepts
standard TTL outputs and converts them to MOS logic levels. They may be driven from standard 54174 series and
54S174S series gates and flip-flops or from drivers such as
the DS8830 or OM7440. The OS0026 and OS0056 are intended for applications in which the output pulse width is
logically controlled; i.e., the output pulse width is equal to
the input pulse width.

output when it is in the high state. An external resistor tied
between these extra pins and a supply higher than V + will
cause the output to pull up to (V + - 0.1 V) in the off state.
For OS0056 applications, it is required that an external resistor be used to prevent damage to the device when the
driver switches low. A typical Vss connection is shown on
the next page.
These devices are available in 8-lead TO-5, one watt copper
lead frame 8-pin mini-DIP, and one and a half watt ceramic
DIP, and TO-8 packages.

The OS0026/0S0056 are designed to fulfill a wide variety of
MOS interface requirements. As a MOS clock driver for long
silicon-gate shift registers, a single device can drive over
10k bits at 5 MHz. Six devices provide input address and
precharge drive for a 8k by 16-bit 1103 RAM memory system. Information on the correct usage of the OS0026 in
these as well as other systems is included in the application
note AN-76.

Features
•
•
•
•
•

Fast rise and fall times-20 ns 1000 pF load
High output swing-20V
High output current drive- ± 1.5 amps
TTL compatible inputs
High rep rate-5 to 10 MHz depending on power dissipation
• Low power consumption in MOS "0" state-2 mW
• Drives to O.4V of GNO for RAM address drive

The OS0026 and OS0056 are identical except each driver in
the OS0056 is provided with a Vss connection to supply a
higher voltage to the output stage. This aids in pulling up the

Connection Diagrams (Top Views)
Dual-In-Llne Package

TO-5 Package
v'

Nt

OUT A

v'

TO-8 Package

IN B

TL/F/5853-1

Note: Pin 4 connected to case.

Order Number
DS0026H or DS0026CH
See NS Package
Number H08C

Dual-In-Llne Package
or

INA

OUT 8

Nt

IN A

V'

TO-5 Package

Dual-In-Llne Package

NC

NC

OUTA

Nt

Order Number
DS0026J or DS0026CJ
See NS Package
NumberJ14A

Order Number
DS0026G or DS0026CG
See NS Package
Number G12C

TL/F/5853-2

Order Number DS0026CJ-8,
or DS0026CN
See NS Package Number
J08A or NOSE

OUTI

TL/F/5853-4

TL/F/5853-3

IN B

NC

Dual-In-Llne Package

v'

Ne

v...

TL/F/5853-7

TL/F/5853-5

Note: Pin 4 connected to case.

Order Number
DS0056H or DS0056CH
See NS Package
Number H08C

v...

IN A

Y-

IN8

TL/F/5853-6

Order Number DS0056J-8,
DS0056CJ-8 or DS0056CN
See NS Package Number
J08A or N08E
5-14

Order Number DS0056J
or DS0056CJ
See NS Package Number J14A

c

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Absolute Maximum Ratings (Note 1)

o

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V+ - V- Differential Voltage
22V
Input Current

100mA
5.5V

Input Voltage (VIN - V-)
Peak Output Current

Symbol

- 55·C to + 125·C
O·Cto +70·C

Storage Temperature Range

- 65·C to + 150·C
300·C

• Derate 8·pin cavity package 7.7 mW/'C above 25'C; derate 14·pin cavity
package 9.3 mWI'C above 25'C; derate molded package 8.4 mW/'C
above 25'C; derate metal can (TO-5) package 4.4 mWI'C above 25'C.

1150mW
1380 mW

Electrical Characteristics

Operating Temperature Range
DS0026, DS0056
DS0026C, DS0056C
Lead Temperature (Soldering, 10 sec.)

1.5A

Maximum Power Dissipation· at 25·C
Cavity Package (8-Pin)
Cavity Package (14-Pin)

1040 mW
660mW

Molded Package
Metal Can (TO-5)

(Notes 2 and 3)

Parameter

Conditions

= OV

Min

Typ

2

1.5

Max

Units

10

15

rnA

0.6

0.4

VIH

Logic "1" Input Voltage

V-

IIH

Logic "1" Input Current

VIN - V-

VIL

Logic "0" Input Voltage

V-

IlL

-3
-10
= OV
V-+0.7 V-+1.0
Logic "1" Output Voltage VIN - V- = 2.4V, IOL = 1 rnA
Logic "0" Output Voltage VIN - V- = O.4V, Vss ~ V+ + 1.0V DS0026 V+ - 1.0 V+ -0.8
IOH = -1 rnA
DS0056 V+ - 0.3 V+ -0.1
"ON" Supply Current
V+ - V- = 20V, VIN - V- = 2.4V
DS0026
30
40
Logic "0" Input Current

VOL
VOH

ICC(ON)

ICC(OFF)

= OV

Symbol

(one side on)

(Note 6)

"OFF" Supply Current

V+ - VVIN - V-

tOFF

tr

tf

(TA

= 20V,
= OV

Turn-Off Delay

Rise Time

Fall Time

V
p.A
V
V
V
rnA

DS0056

12

30

rnA

70·C

10

100

p.A

125°C

10

500

p.A

= 25°C) (Notes 5 and 7)

Parameter
Turn-On Delay

V

VIN - V-

Switching Characteristics
tON

= 2.4V

Conditions
(Figure 1)

Min

Typ

Max

Units

5

7.5

12

ns

(Figure 2)

11

(Figure 1)

12

(Figure 2)

13

(Figure 1),
(Note 5)

CL
CL

(Figure 2),
(Note 5)

CL

(Figure 1),
(Note 5)

CL

(Figure 2),
(Note 5)

CL

CL

CL

=
=
=
=
=
=
=
=

ns
15

ns
ns

500 pF

15

18

ns

1000 pF

20

35

ns

500 pF

30

40

ns

1000 pF

36

50

ns

500 pF

12

16

ns

1000 pF

17

25

ns

500 pF

28

35

ns

31
40
ns
CL
1000 pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics provides conditions for actual device
operation.
Note 2: These specifications apply for V+ - V- = 10V to 20V, CL = 1000 pF, over the temperature range of - 55'C to + 125'C forthe 050026, 050056 and
O'C to + 70'C for the 050026C, 050056C.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: All typical values for TA = 25'C.
Note 5: Rise and fall time are given for M05 logic levels; i.e., rise time is transition from logic "0" to logic "1" which is voltage fall.
Note 6: Iss for 050056 is approximately (Vss - V-)/1 kn (for one side) when output is low.
Note 7: The high current transient (as high as 1.5A) through the resistance of the internal interconnecting V- lead during the output transition from the high state to
the low state can appear as negative feedback to the input. If the external interconnecting lead from the driving circuit to V- is electrically long, or has significant dc
resistance, it can subtract from the switching response.
5-15

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Typical Vee Connection

c
......

Vaa· +8V

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lk

lk

V' = -12V

TLIF/5853-8

Typical Performance Characteristics
10

Input Current vs Input Voltage
8.5

I

<
.§

...z

/

a:
a:

......

...z

-2
-4

-6

V

<

r

DUTY CYCLE' 20%
'-IMHz
I
Cl = 0

8.0

-

.§

...z

7.5

a:
a:

...>-

:...-V

:>
:>

J

:>

~

I
J

7.0

0

>-

g
...

..",

c

~

~

--

~
V· -V· -nv

l0

25

50

?'~RE~)

-so

75 100 125

a

-25

TEMPERATURE ('C)

INPUT VOLTAGE IV)

./

l..-'"

Vee' 20V
C'N - Cl =1000 pF
54S00 ON INPUT

~

~

I

-75 -50 -25

0.5 1.0 1.5 2.0 2.5

24
I
22
20
I
18
16 _'oIN
14
J""'oo.
12
I- tOFF
10

:!

V· -V·· 20V

6.5
6.0

-1.0 -0.5

Turn-On and Turn-Off Delay
vs Temperature

Supply Current vs Temperature

25

50

75

i

lOa

125

TEMPERATURE (' C)

Fall Time vs Load
Capacitance

Rise Time vs Load
Capacitance
40

I---+--+-~

30

30

g
~

...;::

~

;::

I--t+-+-----I--:::*-'F----l

20

....

en

20

~

0:

~~~-+-----I---r-+----l

10

200

400

600

BOO

10

200

1000 1200

J 2400
ci 2200

.Recommended Input Coding
Capacitance
.--...--.--..,.-.--..,...-,---,,--.,

320

5

280
~
.§
a:

~

S

i

BOO

1000 1200

400
360

2000
1BOO
:: 1600
51400
liil'200 1--+--+-+-hI''+i2 1000 I--+--+--+~'!--+--r=r=---l
800 I--+--+~<--+---+--+=-,~

~

600

DC Power (Poe) vs
Duty Cycle

~

~ :~~

400

LOAD CAPACITANCE (pF)

LOAD CAPACITANCE (pF)

240

200
160
120
80

I--+-'Ll--::lo""""l-

40

200
0 0'--,....
00---'20....
0-3......
00---'40-0-5......
00---'60-0-7.....
00-8..00

TA'25°C
Cl = a

v· - V· • 20V -., ../ ~
v·-v·.nv.......,. ~ V

y+ -V·'12~X

j

,
o

'/
./

./

V".

/y V
v....~

10

5-16

~'"

~

(v. _V·)2

POCo ~(DC)

20

30

40

50

DUTY CYCLE (%)

OUTPUT PULSE WIDTH (ns)

~

~

/

60

70

80

TL/F/5853-9

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Schematic Diagrams

<:)
<:)

N

en
......

1/2050026

C

en

<:)
<:)

U1
AI

en

AI
AI

Rl
09

01

AZ

EXTERNAL
Co.
o-i

~UT

OZ

RJ
OUTPUT

TLlF/5853-10

1/2050056
VBO

RS

RI

os
Rl

01

RZ

EXTERNAL

LII

co.

o-i~UT

OUTPUT

010

R5
10k

RI

~--'-~~------~--~~------~---4~~---ov·
TLlF/5853-11

5-17

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AC Test Circuits and Switching Time Waveforms

CD
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+5V

o
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INPUT

50
IDOpF

V,N

'

5V

PRF'1 MHz

PW·0.5p.
". ~,.:; IOn.

TL/F/5853-13
TLIF/5853-12

FIGURE 1
+20V

1.5V\

-I~PULSE GEN
INPUT
VOUT

0-3V

TL/F/5853-15

TLIF/5853-14

FIGURE 2

Typical Applications
DC Coupled RAM Memory Address or Pre charge
Driver (Positive Supply Only)

AC Coupled MOS Clock Driver
+5V

+HV
l00pf

Cl

~OPf

C2
1000pF

TD ADDRESS
L1NESDN
MEMDRY SYSTEM

DS0026CN

}

~
54n4SERIES
GATES AND flDPS

100pf

TWD PHASE ClK
TDSHIFT
REGISTERS DR RAMS

DSO026CN

}

1I2DM1400

3 .
-I2V

TL/F/5853-16

TL/F/5853-17

Application Hints
DRIVING THE MM5262 WITH THE
DS0056 CLOCK DRIVER

have the potential of causing the memory system to malfunction. Recognizing the source and potential of these
problems early in the design of a memory system is the
most critical step. The object here is to point out the source
of these problems and give a quantitative feel for their magnitude.

The clock signals for the MM5262 have three requirements
which have the potential of generating problems for the
user. These requirements, high speed, large voltage swing
and large capacitive loads, combine to provide ample opportunity for inductive ringing on clock lines, coupling clock
signals to other clocks and/or inputs and outputs and generating noise on the power supplies. All of these problems

5-18

c

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Application Hints (Continued)
Line ringing comes from the fact that at a high enough frequency any line must be considered as a transmission line
with distributed inductance and capacitance. To see how
much ringing can be tolerated we must examine the clock
voltage specification. Figure 6 shows the clock specification, in diagram form, with idealized ringing sketched in. The

mation stored in the memory could be altered. Referring to
Figure 1, if the threshold voltage of a transistor were -1.3V,
the clock going to Vss - 1 would mean that all the devices,
whose gates are tied to that clock, would be only 300 mV
from turning on. The internal circuitry needs this noise margin and from the functional description of the RAM it is easy
to see that turning a clock on at the wrong time can have
disastrous results.

V~+I----------------------------~r------

V~---~

Controlling the clock ringing is particularly difficult because
of the relative magnitude of the allowable ringing, compared
to magnitude of the transition. In this case it is 1V out of 20V
or only 5%. Ringing can be controlled by damping the clock
driver and minimizing the line inductance.

.~~~~:========t===================1========
VDD+l----------+-~------------~--------­

VDD -----------\

Damping the clock driver by placing a resistance in series
with its output is effective, but there is a limit since it also
slows down the rise and fall time of the clock signal. Because the typical clock driver can be much faster than the
worst case driver, the damping resistor serves the useful
function of limiting the minimum rise and fall time. This is
very important because the faster the rise and fall times, the
worse the ringing problem becomes. The size of the damp-

VDD-l----------~-------------------------

·VTIMINI • Minimum th...hold voltage.
TLlF/5853-18

FIGURE 6. Clock Waveform
ringing of the clock about the Vss level is particularly critical.
If the Vss - 1 VOH is not maintained, at aI/times, the infor-

R6

R8

05
Rl

09

01

R2

EXTERNAL

05

C'N

o-j ~UT
........--QOUTPUT

03

08

010

09
R5

10k

Rl

....-------e----....- ....----ov-

~-~---.------.---

TL/F/5853-11

FIGURE 7. Schematic of 1/2050056

5-19

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Application Hints (Continued)

CD
N

ing resistor varies because it is dependent on the details of
the actual application. It must be determined empirically. In
practice a resistance of 10n to 20n is usually optimum.

en
c.......
o
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en

c

saturate, pulling the output to within a VeE(SAT) of the V+
supply. This is critical because as was shown before, the
Vss - 1.0V clock level must not be exceeded at any time.
Without the VBB pull up on the base of 08 the output at best
will be 0.6V below the V + supply and can be 1V below the
V+ supply reducing the noise margin on this line to zero.

Limiting the inductance of the clock lines can be accomplished by minimizing their length and by laying out the lines
such that the return current is closely coupled to the clock
lines. When minimizing the length of clock lines it is important to minimize the distance from the clock driver output to
the furthest point being driven. Because of this, memory
boards are usually designed with clock drivers in the center
of the memory array, rather than on one side, reducing the
maximum distance by a factor of 2.

Because of the amount of current that the clock driver must
supply to its capacitive load, the distribution of power to the
clock driver must be considered. Figure 8 gives the idealized voltage and current waveforms for a clock driver driving
a 1000 pF capacitor with 20 ns rise and fall time.
As can be seen the current is significant. This current flows
in the Voo and Vss power lines. Any significant inductance
in the lines will produce large voltage transients on the power supplies. A bypass capacitor, as close as possible to the
clock driver, is helpful in minimizing this problem. This bypass is most effective when connected between the Vss
and Voo supplies. A bypass capacitor for each OS0056 is
recommended. The size of the bypass capacitor depends
on the amount of capacitance being driven. Using a low
inductance capacitor, such as a ceramic or silver mica, is
most effective. Another helpful technique is to run the Voo
and Vss lines, to the clock driver, adjacent to each other.
This tends to reduce the lines inductance and therefore the
magnitude of the voltage transients.
While discussing the clock driver, it should be pOinted out
that the OS0056 is a relatively low input impedance device.
It is possible to couple current noise into the input without
seeing a significant voltage. Since the noise is difficult to
detect with an oscilloscope it is often overlooked.

Using multilayer printed circuit boards with clock lines sandwiched between the Voo and Vss power plains minimizes
the inductance of the clock lines. It also serves the function
of preventing the clocks from coupling noise into input and
output lines. Unfortunately multilayer printed circuit boards
are more expensive than two sided boards. The user must
make the decision as to the necessity of multilayer boards.
Suffice it to say here, that reliable memory boards can be
designed using two sided printed circuit boards.
The recommended clock driver for use with the MM4262/
MM5262 is the OS0056/0S0056C dual clock driver. This
device is designed specifically for use with dynamic circuits
using a substrate, VBB, supply. Typically it will drive a 1000
pF load with 20 ns rise and fall times. Figure 7 shows a
schematic of a single driver.
In the case of the MM5262, V+ is a +5V and VBB is
+ 8.5V. VBB should be connected to the VBB pin shown in
Figure 7through a 1 kn resistor. This allows transistor 08 to

::

Lastly, the clock lines must be considered as noise generators. Figure 9 shows a clock coupled through a parasitic
coupling capacitor, Ce, to eight data input lines being driven
by a 7404. A parasitic lumped line inductance, L, is also
shown. Let us assume, for the sake of argument, that Ce is
1 pF and that the rise time of the clock is high enough to
completely isolate the clock transient from the 7404 because of the inductance, L.

~ ~~

r

20ns

20ns-1

-

'~---D

-lAMP----U
+8.5V

Vss
TL/F/5853-20

FIGURE 9. Clock Coupling
With a clock transition of 20V the magnitude of the voltage
generated across CL is:

-15V
CL x.::N

lL=~

10·9F ·20V

=20 x 10·9sec =

lA

= 20V x

~ = 20V x

(_1_) = 0.35V
CL + Ce
56 +1
This has been a hypothetical example to emphasize that
with 20V low rise/fall time transitions, parasitic elements
can not be neglected. In this example, 1 pF of parasitic
capacitance could cause system malfunction, because a
7404 without a pull up resistor has typically only 0.3V of
V

TL/F/5853-19

FIGURE 8. Clock Waveforms (Voltage and Current)
5-20

c

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Application Hints (Continued)
noise margin in the "1" state at 25°C. Of course it is stretching things to assume that the inductance, L, completely isolates the clock transient from the 7404. However, it does
point out the need to minimize inductance in input/output as
well as clock lines.

Clock coupling to inputs and outputs can be minimized by
using multilayer printed circuit boards, as mentioned previously, physically isolating clock lines and/or running clock
lines at right angles to input/ output lines. All of these techniques tend to minimize parasitic coupling capacitance from
the clocks to the signals in question.

The output is current, so it is more meaningful to examine
the current that is coupled through a 1 pF parasitic capacitance. The current would be:

t:..v

1= Cc x M =

1

10- 12 X 20
20 X 10- 9

In considering clock coupling it is also important to have a
detailed knowledge of the functional characteristics of the
device being used. As an example, for the MM5262, coupling noise from the 2 clock to the address lines is of no
particular consequence. On the other hand the address inputs will be sensitive to noise coupled from  1 clock.

X

= 1 mA

This exceeds the total output current swing so it is obviously
significant.

5-21

o
N
en
.......
C

en
o
o

U1

en

~National

~ Semiconductor
083245 Quad MOS Clock Driver
General Description

Features

The DS3245 is a quad bipolar-to-MOS clock driver with TTL
compatible inputs. It is designed to provide high output current and voltage capabilities necessary for optimum driving
of high capacitance N-channel MaS memory systems.

• TTL compatible inputs
• Operates from 2 standard supplies: 5 Voc, 12 Voc
• Internal bootstrap circuit eliminates need for external
PNP's
• PNP inputs minimize loading
• High voltage/current outputs
• Input and output clamping diodes
• Control logic optimized for use with MaS memory systems
• Pin and function equivalent to Intel 3245

Only 2 supplies, 5 Voc and 12 Voc, are required without
compromising the usual high VOH specification obtained by
circuits using a third supply.
The device features 2 common enable inputs, a refresh input, and a clock control input for simplified system designs.
The circuit was designed for driving highly capacitive loads
at high speeds and uses Schottky-clamped transistors. PNP
transistors are used on all inputs, thereby minimizing input
loading.

Logic and Connection Diagrams

ENZ------------~

Dual-In-Llne Package

EN 1------------...,.

eLK - - - - - - - - -.........
16

vOO

OUTI
SEll---~::r............

Vee

OUT 1

SEll

SEL4

elK IN

EN 1

RFSH IN

EN 2

OUTZ

SEl Z.......----
Temperature (TA)
DS1628
DS3628

7.0V

Logical "0" Input Voltage

Min
4.5

Max
5.5

Units
V

-55
0

+125
+70

°C
°C

-1.5V

Storage Temperature Range

- 65°C to + 150°C

Maximum Power Dissipation* at 25°C
Cavity Package
Molded Package

1667 mW
1832 mW

Lead Temperature (Soldering, 10 seconds)
300°C
• Derate cavity package 11.1 mW I'C above 2S'C; derate molded package
14.7 mWI'C above 2S'C.

Electrical Characteristics
Symbol

(Notes 2,3)

Parameter

Conditions

VIN(1)

Logical "1" Input Voltage

VINIO)

Logical "0" Input Voltage

IIN(1)

Logical "1" Input Current

Vee

IIN(O)

Logical "0" Input Current

Vee

Input Clamp Voltage

Vee

VOH

Logical "1" Output Voltage
(No Load)

Vee

Logical "0" Output Voltage
(No Load)

Vee

Logical "1" Output Voltage
(With Load)

Vee

Logical "0" Output Voltage
(With Load)

Vee

VOH
VOL

Typ

=
=
=
=
=
=
=

= 5.5V
5.5V VIN = 5.5V
4.5V liN = -18 mA
4.5V,IOH = -10 p.A
5.5V

VIN

4.5V, IOL

4.5V, 10H

4.5V,IOL

=
=
=

10 p.A

-1.0 mA

V
V

0.1

40

p.A

-180

-400

p.A

-0.7

-1.2

V

DS1628

3.4

4.3

DS3628

3.5

4.3
0.4

V

DS3628

0.25

0.35

V

DS1628

2.5

3.9

V

DS3628

2.7

3.9

V

= 4.5V, VOUT = OV, (Note 6)
= 4.5V, VOUT = 4.5V, (Note 6)
VOUT = O.4V to 2.4V, DIS1 or DIS2 = 2.0V
Vee = 5.5V One DIS Input = 3.0V
All Other Inputs = X, Outputs at Hi-Z
DIS1, DIS2 = OV, Others = 3V

0.35

Logical "1" Drive Current

Vee

-150

Logical "0" Drive Current

Vee

150

Hi-Z

TRI-STATE Output Current

lee

Power Supply Current

-40

Outputs on

Switching Characteristics (Vee =
Symbol

ts-+
tF

tR

=

Storage Delay Positive Edge

Fall Time

Rise Time

OV, Outputs Off

0.5

V
mA
mA

0.1

40

p.A

90

120

mA

70

100

mA

25

50

mA

Units

5V, T A = 25°C) (Note 6)

Parameter
Storage Delay Negative Edge

V

0.25

110

All Inputs

V

DS1628

DS1628/DS3628

20 mA

Units

0.8

100

ts+ -

Max

2.0

VeLAMP

VOL

Min

Conditions
(Figure 1)

(Figure 1)

(Figure 1)

(Figure 1)

tZL

Delay from Disable Input to Logical "0"
Level (from High Impedance State)

CL = 50 pF
toGND

tZH

Delay from Disable Input to Logical "1"
Level (from High Impedance State)

CL = 50 pF
toGND
5-26

Typ

Max

50 pF

4.0

5.0

500 pF

6.5

8.0

50 pF

4.2

5.0

500 pF

6.5

8.0

50 pF

4.2

6.0

500 pF

19

22

50 pF

5.2

7.0

500 pF

20

24

2 kn to Vee
(Figure 2)

19

25

ns

RL = 2 kn to GND
(Figure 2)

13

20

ns

=
CL =
CL =
CL =
CL =
CL =
CL =
CL =
RL =
CL

Min

ns

ns

ns

ns

Switching Characteristics
Symbol

(Continued) (Vee

c
en
-""

= 5V. TA = 25°C) (Note 6)

Parameter

en

Min

Conditions

Typ

Max

Units

tlZ

Delay from Disable Input to High Impedance
State (from Logical "0" Level)

Cl = 50 pF
toGND

Rl = 4000. to Vee
(Figure 3)

18

25

n5

tHZ

Delay from Disable Input to High Impedance
State (from Logical "1" Level)

Cl = 50 pF
toGND

Rl = 4000. to GND
(Figure 3)

8.5

15

ns

AC Test Circuits and Switching Time Waveforms
ts+ -. ts- +. t r • tf
Vee

JV
INPUT

,..---_
jl.5V

OV----:j

OUTPUT

.......VVIr-. . .O Vo UT

TL/F/S87S-S

TL/F/S87S-4

FIGURE 1
tZH

tZL

Vee

Vee

~____~------_.D~.,~
2ku

OISABLE
INPUT

OUTPUT'

15n
(NOTE I)

TL/F/S87S-6

r;:'"

TL/F/S87S-8

• ANY ONE OF EIGHT OUTPUT5

TL/F/S87S-7

FIGURE 2

tLZ
Vee

Vee

r-____~------_.D~.,~

DISABLE
INPUT

VOH -----1f-1.+-----;;;~.
40011

.......~-+----4II-oVauT

un
~M~,--oVOUT

INOTE 6)

400n

I

50PF

":" INOTE 5)

TL/F/S87S-9

OUTPUT

'''~

TL/F/S87S-\\

TL/F/S87S-\O

FIGURE 3
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified, min/max limits apply across the -SS'C to
the D53628. All typical values are for TA = 25'C and Vee = 5V.

+ 12S'C temperature range for the 051628 and across the O'C to + 70'C range for

Note 3: All currents into device pins shown as positive; all currents out of device pins shown as negative; all voltages references to ground unless otherwise noted.
All values shown as max or min on absolute value basis.
Note 4: The pulse generator has the following characteristics: ZOUT

= SOO and PRR s: 1 mHz. Rise and fall times between 10% and 90% points s: S ns.

Note 5: CL includes probe and jig capacitance.
Note 6: When measuring output drive current and switching response for the 051628 and 053628 a 1SO resistor should be placed in series with each output.

5-27

I\)
Q)

.......

C
en
w
en
I\)
Q)

«
r-..
~ ~National

~ ~ Semiconductor
DS3647A Quad TRI-STATE®MOS Memory 1/0 Register
General Description
The DS3647A is a 4-bit 1/0 buffer register intended for use
in MOS memory systems. This circuit employs a fall-through
latch for data storage. This method of latching captures the
data in parallel with the output, thus eliminating the delays
encountered in other designs. This circuit uses Schottkyclamped transistor logic for minimum propagation delay and
employs PNP input transistors so that input currents are
low, allowing a large fan-out for this circuit which is needed
in a memory system.
Two pins per bit are provided, and data transfer is bi-directional so that the register can handle both input and output
data. The direction of data flow is controlled through the
input enables. The latch control, when taken low, will cause
the register to hold the data present at that time and display
it at the outputs. Data can be latched into the register independent of the output disables or EXPANSION input. Either
or both of the outputs may be taken to the high-impedance
state with the output disables. The EXPANSION pin disables both outputs to facilitate multiplexing with other I/O
registers on the same data lines.

The DS3647A features TRI-STATE outputs. The "B" port
outputs are designed for use in bus organized data transmission systems and can sink 80 mA and source - 5.2 mA.
Data going from port "A" to port "B" and from "B" to port
"A" is inverted in the DS3647A.

Features
•
•
•
•
•
•
•
•

PNP inputs minimize loading
Fall-through latch design
Propagation delay of only 15 ns
TRI-STATE outputs
EXPANSION control
Bi-directional data flow
TTL compatible
Transmission line driver output

Logic and Connection Diagrams

r---------------------,

I
I
I
I
I
I
I

B
MULTIPLEX

L ____ _

_ _ _ _ _ .J

Dual-In-Llne Package

I
Bl
Bl
AI
INPUT { A
ENABLE
B

AI

==== =}-oBZ
=====}-oB3
=====}-oB4
-----,

AZo-[=====
A3o-{=====
A4o-{=====
r-----

I
I
I
_ _ _ .JI

I

I
I
I

L ____ _
A

INPUT
ENABLES

IiiiTiiiiT

B

EXPANSION

DISABLES
TL/F/B354-1

5-28

AZ
BZ

B3

GNO

TL/F/B354-2

Top View
Order Number DS3647AD or DS3647AN
See NS Package Number D16C or N16A

Absolute Maximum Ratings

Operating Conditions

(Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Offlce/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
-1.5Vto +7V
Storage Temperature Range
-65· to + 150·C
Maximum Power Dissipation· at 25·C
Molded Package

Electrical Characteristics
Logic "1" Input Voltage

VIN(O)

Logic "0" Input Voltage

IIN(1)

Logic "1" Input Current

Conditions

Logic "0" Input Current
Vee=5.5V, VIN=0.5V

VelAMP

Input Clamp Voltage

Vee=4.5V, IIN= -18 mA

VOl(A)

Logic "0" Output Voltage
A Ports

Vee=4.5V, 10l =20 mA

VOl(B)

Logic "0" Output Voltage

Vee=4.5V

8 Ports
VOH(A)

VOH(B)

Logic "1" Output Voltage

Units
V

0

+70

·C

Min

Typ

Max

2.0

Vee=5.5V, VIN=5.5V

IIN(O)

Max
5.5

(Notes 2 and 3)

Parameter

VIN(1)

Min
4.5

1476mW
300·C

Lead Temperature (Soldering, 10 seconds)
'Derate molded package 10.0 mWI' C above 2S'C.

Symbol

Supply Voltage (Vee>
Temperature (TA)
DS3647A

Units
V

0.8

V

Latch, Disable Inputs

0.1

40

/-LA

Expansion

0.2

80

/-LA

A Ports, 8 Ports

0.2

100

/-LA

Enable Inputs

0.4

200

/-LA

Latch, Disable Inputs

-25

-250

/-LA

Expansion

-50

-500

/-LA

A Ports, 8 Ports

-50

-500

/-LA

Enable, Inputs

-0.1

-1.25

mA

-0.6

-1.2

V

0.4

0.5

V

10l =30 mA

0.3

0.4

V

10l =50 mA

0.4

0.5

V

Vee=5V

3.0

3.4

A Ports

Vee=4.5V

2.5

3.4

V

Logic "t" Output Voltage

Vee=5V

2.9

3.3

V.

Vee=4.5V

2.4

3.3

V

10H= -1 mA

10H= -5.2 mA, (Note 4)

8 Ports

V

10S(A)

Output Short-Circuit Current
A Port

Vee=4.5V to 5.5V, Vour=OV, (Note 4)

-50

-80

-120

mA

lOS (B)

Output Short-Circuit Current
8 Port

Vee = 4.5V to 5.5V, Vour= OV, (Note 4)

-70

-120

-180

mA

Icc

Power Supply Current

DS3647A

100

140

mA

DS3647A

70

105

mA

Exp=3V, A Ports=OV,
B Ports Open, All Other Pins = OV
Enable A, Latch=3V, A Ports =
OV, B Ports Open, All Other
Pins=OV

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the O'C to + 70'C range. All typicals are given for Vcc= SV and TA = 2S'C.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted.
Note 4: Only one output at a time should be shorted.

5-29

Switching Characteristics (Vcc=5V, TA=25°C)
Symbol

Parameter

Conditions

Min

Typ·

Max

Units

DATA TRANSFER B PORT TO A PORT

tpdO

Propagation Delay to a Logic "0"

CL= 50 pF, Rl = 280n,
(Figures 1 and 4)

7.5

15

ns

tpd1

Propagation Delay to a Logic "1"

Cl = 50 pF, Rl = 280n,
(Figures 1 and 4)

6.0

12

ns

A PORT CONTROL FROM OUTPUT DISABLE A INPUT

tlZ

Delay to High Impedance from
Logic "0"

(Figures 1 and 5)

13

20

ns

tHZ

Delay to High Impedance from
Logic "1"

(Figures 1 and 6)

14

20

ns

tZl

Delay to Logic "0" from High
Impedance

(Figures 1 and 7)

10

15

ns

tZH

Delay to Logic "1" from High
Impedance

(Figures 1 and 8)

25

35

ns

DATA TRANSFER A PORT TO B PORT, DS3647A

tpdO

Propagation Delay to a Logic "0"

Cl =50 pF, Rl = 100 n,
(Figures 2 and 4)

6.5

12

ns

tpd1

Propagation Delay to a Logic "1"

Cl =50 pF, Rl = 100 n,
(Figures 2 and 4)

8.0

15

ns

B PORT CONTROL FROM OUTPUT DISABLE B INPUT, DS3647A

tlZ

Delay to High Impedance from
Logic "0"

(Figures 2 and 5)

15

25

ns

tHZ

Delay to High Impedance from
Logic "1"

(Figures 2 and 6)

14

20

ns

tZl

Delay to Logic "0" from High
Impedance

(Figures 2 and 7)

10

16

ns

tZH

Delay to Logic "1" from High
Impedance

(Figures 2 and 8)

25

35

ns

LATCH SET-UP AND HOLD TIMES, ALL DEVICES

tSET-UP

Set-Up Time of Data Input Before
Latch Goes Low

5

a

ns

tHOlD

Hold Time of Data Input After
Latch Goes Low

10

5

ns

Product Description
Device Number

B Port To A Port
Function

A Port To B Port
Function

A Port Outputs

B Port Outputs

DS3647A

Inverting

Inverting

TRI-STATE

TRI-STATE

5-30

c

en
w

Truth Table

en

Input
Enables

A

Expansion

A Ports
A1-A4

8 Ports
81-84

»

Comments

8

A

8

o

o

0

Hi-Z

A

Data in on A, output to B

o

0

B

Hi-Z

Data in on B, output to A

o

o
o
o

o

0

Hi-Z

A

Data stored which is present
when latch goes low

o

o

o

0

B

Hi-Z

Data stored which is present
when latch goes low

x

o

0

Hi-Z

Hi-Z

Both A and B in Hi-Z state,
Data in on A, may be latched

o

0

Hi-Z

Hi-Z

Both A and B in Hi-Z state,
Data in on B, may be latched

x

1

Hi-Z

Hi-Z

Both A and B in Hi-Z state

o

o
o

o
o

x

x

~
~

Output
Disables

x

x

x

AC Test Circuits

VCC' 5V
(

TEST
POINT

.

)

VCC
(

TEST
POINT
(

.
4

:. 280

OUTPUTC_~~'-~'-:10111~"'''

OUTPUT

0 - -....-

_." ...
CL

-...

(

.....
."

NoTE

":"

100

.......1.............
,~

.~
• lk

lII·

50pF-i-

."

= 5V

~

."

- ...

~~
~~

-=::
TL/F/8354-4

TL/F/8354-3

FIGURE 1. A Port Load

FIGURE 2. 8 Port Load
Note 1: CL includes probe and jig capacitance.

Operating Waveforms
Using TRI-STATE

TRI-STATE Disabled

.1~INPUTDATAVALlD:j

r------, ,....------

'K-------X

INPUT OATAVAlI01

DATA
INPUT;
__ (

J

_ ____ J

\.. ______ _

,

'-- __ _

/

INPUT
ENABLE

OUTPUT
DISABLE

OUTPUT -

-

-

-

-

L

~

////II

-«((((«

}'»\)).. __

j

u.u.u.u. - - - ~.IJ.u

OUTPUT
TRI·STATE

--1

--\:'*~-"'\

1

--~;'~--I---~~~~

I

DATA
LATCHED
OUTPUT
ACTIVE

I

-

OUTPUT
TRI·STATE-j

I

TL/F/8354-5

IFEEO·THROUGHi---LATCHEO
OUTPUT ACTIVE

_I

I

TLlF/8354-6

·When the Input Enable makes a negative transition, the output will be indeterminate for a short duration. The negative transition of the Input Enable normally
occurs during a don't-care timing state at the output.

5-31

~ r-------------------------------------------------------------------~

I'~

CD

Switching Time Waveforms

C")

en
c

tpdO and tpd1
INPUT
OV

OUTPUT
(INVERTED)

-Itpdl~r

~1.5V

OUTPUT
(NON·INVERTED)

1.5VL
TL/F/B354-7

Input Characteristics: f

= 1 MHz, tR = tF :!: 5 ns (10% to 90% points), duty cycle = 50%, ZOUT = 50 n
FIGURE 4

tLZ

INPUT

"r.
I.SV

1.SV

t
ov~
=---r

LOGIC "I"
OUTPUT VOLTAGE
HI·Z---

~

LOGIC "0"
VOLTAGE

"~

INPUT

ov~

HI·Z
OUTPUT

tHZ

--r

O.SV

O.SV

TL/F/B354-10

TLlF/B354-B

FIGURE 6

FIGURE 5

tZH

tZL
INPUT

"k

HI·Z
OUTPUT

1.SV

OV

L"IC"'"~
IZH

~

LOGIC "0" _ _ _
VOLTAGE

"~

INPUT

1.SV

OV

OUTPUT VOLTAGE

~

HI·Z

~

O.SV

O.SV

TL/F/B354-11

TL/F IB354-9

FIGURES

FIGURE 7

Schematic Diagram
EQUIVALENTINPUT

EQUIVALENT OUTPUT

r----..,
I

Vee

I

I

I
I
INPUT

OUTPUT

L-~----------~----------_4--~~GNO

Note. Data pins Al-A4 and 81-84 consist of
an input and an output tied together.

5-32

TL/F IB354-12

Typical Application
The diagram below shows how the DS3647A can be used as a register capable of multiplexing data lines.

AI

81

rr-

A2 3~4S7A 82
A3
83 I""-

4

DATA LINES
(MULTIPLEXED)

A4
84
EXPANSIDN

r-

I

....
~ ~

OS3847A

-----

~

16
DATA LINES
TO MOS
MEMORY
ARRAY

I

-

-

10f4
DECODER
DM74155

P-

~

~

~

~ ~

OS3847A

~

P-

rrr-

I

.....
...-.-

~

tOS3647A
tt-

J
TO OS384 7A INPUT ENABLES

DATA
TD/FRDM
ARRAY

L!>O tJ

TO OS3647A meR INPUTS

t

LATCH
CDNTRDL-------------------------------'

TL/F/8354-13

5-33

co

I'(D
C")

en

c.......
co

I'(D
,...

en

c.......
co
-.::t

(D
C")

en

c.......
co

-.::t

(D
,...

en

c

~Nationar
~ Semiconductor
OS1648/0S3648/0S1678/0S3678 TRI-STATE® TTL to
MOS Multiplexers/Orivers
General Description
The OS1648/0S3648 and OS1678/0S3678 are quad 2-input multiplexers with TRI-STATE outputs designed to drive
the large capacitive loads (up to 500 pF) associated with
MOS memory systems. A PNP input structure is employed
to minimize input currents so that driver loading in large
memory systems is reduced. The circuit employs Schottkyclamped transistors for high speed and TRI-STATE outputs
for bus operation.
The OS1648/0S3648 has a 150 resistor in series with the
outputs to dampen transients caused by the fast-switching

output. The OS1678/0S3678 has a direct, low impedance
output for use with or without an external resistor.

Features
•
•
•
•
•
•

TRI-STATE outputs interface directly with system-bus
Schottky-clamped for better ac performance
PNP inputs to minimize input loading
TTL compatible
High-speed capacitive load drivers
Built-in damping resistor (OS1648/0S3648 only)

Logic and Connection Diagrams
OUTPUT
CONTROL
AI

BI

AZ

BZ

A3

B3

A4

Dual-ln-L1ne Package

(15)
(2)
Vce

INPUTS
OUTPUT - - - - - - - .
CONTROL
A4
B4

OUTPUT
Y4

INPUTS

~

A3

83

OUTPUT
Y3

(3)

(5)

(6)

(II)

(10)

(14)
SELECT
(13)

Y4

AI
Bl
~
INPUTS

Yl
OUTPUT

A2
B2
~
INPUTS

Y2
OUTPUT

GNO

TL/F/7506-2

B4

Top View
SELECT

Order Number DS1648J, DS3648J, DS1678J
DS3678J, DS3648N or DS3678N
See NS Package Number J16A or N16A

5-34

c

Absolute Maximum Ratings

Supply Voltage

Supply Voltage (Vee)
Temperature (TA)
OS1648,OS1678
OS3648, OS3678

7V

Logical "1" Input Voltage
Logical "0" Input Voltage
Storage Temperature Range

en
.......

Operating Conditions

(Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
7V
-1.5V

Q)

Min
4.5

Max
5.5

Units
V

-55
0

+125
+70

°C
°C

0l:Io

CX)
......

C

en

w
Q)
0l:Io

CX)
......

C

en
.......

- 65°C to + 150°C

Q)

Maximum Power Dissipation· at 25°C
Cavity Package
Molded Package

........

CX)
......

1433 mW
1362 mW

c

en
w
Q)

Lead Temperature
(Soldering, 10 seconds)
300°C
• Oerate cavity package 9.6 mW/"C above 25°C; derate molded package
10.9 mW/"C above 25°C.

........
CX)

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Conditions

Min

Typ

Max

Units

VIN(1)

Logical "1" Input Voltage

VIN(O)

Logical "0" Input Voltage

0.8

V

IIN(1)

Logical "1" Input Current

Vee = 5.5V, VIN = 5.5V

0.1

40

/-LA

'IN(O)

Logical "0" Input Current

Vee = 5.5V, VIN = 0.5V

-50

-250

/-LA

VeLAMP

Input Clamp Voltage

Vee = 4.5V,IIN = -18 mA

-0.75

-1.2

VOH

Logical "1" Output Voltage
(No Load)

Vee = 4.5V, IOH = -10/-LA

VOL

Logical "0" Output Voltage
(No Load)

Vee = 4.5V, IOL

Logical "1" Output Voltage
(With Load)

Vee = 4.5V, IOH = -1.0 mA

VOH

VOL

110

Logical "0" Output Voltage
(With Load)

Logical "1" Drive Current

2.0

Vee = 4.5V, IOL

= 10 /-LA

= 20 mA

OS1648/0S1678

2.7

OS3648/0S3678

2.8

V

3.6

V
V

3.6

V

OS1648/0S1678

0.25

0.4

V

OS3648/0S3678

0.25

0.35

V

OS1648

2.4

3.5

V

OS1678

2.5

3.5

V

OS3648

2.6

3.5

V

OS3678

2.7

3.5

V

OS1648

0.6

1.1

V

OS1678

0.4

0.5

V

OS3648

0.6

1.0

V

OS3678

0.4

0.5

V

Vee = 4.5V, Your = OV, (Note 4)

100

Logical "0" Drive Current

Vee = 4.5V, Your = 4.5V, (Note 4)

IHi.Z

TRI-STATE Output Current

Your

Icc

Power Supply Current

Vee = 5.5V

-250
150
-40

= 0.4V to 2.4V, Output Control = 2.0V

Output Control = 3V
All Other Inputs at OV

mA

42

mA
40

/-LA

60

mA

,

All Inputs at OV
20
32
mA
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherWise specified minImax limits apply across the -55°C to + 125°C temperature range for the 051648 and 051678 and across the O°C to
+ 70°C range for the 053648 and 053678. All typical values for TA = 25°C and Vee = 5V.
Note 3: All currents into device pins shown as positive. out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: When measuring output drive current and switching response for the 051678 and 053678 a 150 resistor should be placed in series with each output. This
resistor is internal to the 051648/0S3648 and need not be added.

5-35

•

co

I'
CD

Switching Characteristics Vee =

CO')

en

c.......
CO
I'
CD

.,..
en
c.......
CO
oo::t
CD
CO')

Symbol
ts±

5V, TA

=

25°C (Note 4)

Parameter
(Figure 1)

CL
CL

ts~

Storage Delay Positive Edge

(Figure 1)

CL
CL

tF

Fall Time

(Figure 1)

tR

Rise Time

(Figure 1)

CL

en

c.......
CO
oo::t
CD

CL

en

CL
CL

.,..

c

Typ

Max

50 pF

5

7

ns

500 pF

9

12

ns

50 pF

6

8

ns

500 pF

9

13

ns

50 pF

5

8

ns

500 pF

22

35

ns

50 pF

6

9

ns

500 pF

22

35

ns

Conditions

Storage Delay Negative Edge

=
=
=
=
=
=
=
=

Min

Units

tZL

Delay from Output Control Input to Logical "0"
Level (from High Impedance State)

CL = 50 pF, RL = 2 kn to Vee,
(Figure 2)

10

15

ns

tZH

Delay from Output Control Input to Logical "1 "
Level (from High Impedance State)

CL = 50 pF, RL
(Figure 2)

=

2 kn to GND

8

15

ns

tLZ

Delay from Output Control Input to High Impedance
State (from Logical "0" Level)

CL = 50 pF, RL
(Figure 3)

=

400.0. to Vee,

15

25

ns

tHZ

Delay from Output Control Input to High Impedance
State (from Logical "1 " Level)

CL = 50 pF, RL
(Figure 3)

=

400.0. to GND,

10

25

ns

ts±

Propagation Delay to Logical "0" Transition When
Select Selects A

CL

=

50 pF, (Figure 1)

12

15

ns

ts~

Propagation Delay to Logical "1 " Transition When
Select Selects A

CL

=

50 pF, (Figure 1)

14

17

ns

ts±

Propagation Delay to Logical "0" Transition When
Select Selects B

CL

=

50 pF, (Figure 1)

16

20

ns

ts~

Propagation Delay to Logical "1 " Transition When
Select Selects B

CL

=

50 pF, (Figure 1)

14

20

ns

Schematic Diagram

-

EQUIVALENT QUTPUT

EQUIVALENT INPUT

r

I
I

~:
.~

........
.......
INPUT0--4r(

1~

--

-l---~

I

IJ"'"

15*

I

INTERNAL
lOGIC
CIRCUITRY

:. I
I
~

-

--l--

"''''

."''''

I
~.

I
I
L_

~

Ie....

I
I
I
I
I

-'" Vec

V

.~

j'J

~

~
·051648/053648 only

,

5-36

::: OUTPUT

-

GNO
TL/F17506-3

AC Test Circuits and Switching Time Waveforms
ts±. ts±. TR. tF
Vee

O.hF

VIN
OUT

~
*RO
OUTPUT

VOUT

el

1"'"'

TL/FI7S06-S

TlIF17506-4
Note 1: The pulse generator has the following characteristics: ZOUT = 50n and PRR ,.;: 1 MHz. Rise and fall times between 10% and 90% pOints";: 5 ns.
Note 2: CL includes probe and jig capacitance.

FIGURE 1

tZH

tZl

Vee

Vee

0.1 "F

1
1-1\1\/\,-...-

INPUT

OUTPUT

t--v\f\r....-o VOUT

....0 Your

~LLD.5V

~D.5V
TlIFI7S06-8
TlIFI7S06-7

TL/FI7S06-6
"Internal on OS1648 and OS3648

FIGURE 2

tlZ
Vee

Vee

0.1 ~F

VIN

t-IV\/\,-...-

400

1,

*Ro

...-o VOUT

Your

':'

r

Y
VOL

"

TL/FI7S06-10

TL/FI7S06-9
"Internal on OS1648 and OS3648

FIGURE 3

Truth Table
Output
Control

Inputs

Outputs

Select

A

B

X
L
L

X
L

Hi-Z
H

H

H
H

X
X

X
X
X
L
H

L

H

L
L
L
L
H = High level
L = Low level
X = Oon't care
Hi-Z = TRI-STATE mode

5-37

L
H

TlIFI7S06-11

•

I

co
......

~

en

r---------------------------------------------------------------------------------~

Typical Applications

c

Ui

Addressing 16k RAM

......

...

2:1 Multiplexing of RAM Outputs

r- - - : 1

CD

en

I

c......
co

I

~

CD

Cf)

en
c......
co

I
I
I

16k
RAM
ARRAY

SELECT

...
en
~

CD

A7

MOSRAM
ARRAY

8

} 4 MOS OUTPUTS
(INVERTED)

MOS
OUTPUTS

c

- - - A l B SElECT
Tl/F/7506-14
TlIF17506-12

Refreshing Using TRI-STATE Counter
TRI·STATE
CONTROL

.-

T
OUTPUT
A1 CONTROL
A2

A11
A1D

A9

A3

AI

A4

Y1
DS3648 Y2
OR
DS3678 Y3

AS

B1

Y4

A4

82

A3

83

A7
A6

A2
A1

84

-

ADI -

I
~
~

OUTPUT
A1 CONTROL
A2
MOS RAM
REnUiRING
ADDRESS
MULTI·
PLEXING

Y1
DS3648
OR Y2
0S3678
81
82

TRI·STATE
CONT ROL

I
6·81T
TRI·STATE
REFRESH
COUNTER

~

OS3646
OR
OS3676

CL OCK

I
TlIF/7506-13

5-38

c
en
.....
en

~National

~

~ Semiconductor

co
.......

OS1649/0S3649/0S1679/0S3679 Hex TRI-STATE® TTL
to MOS Orivers

en

c
en
w

General Description

The OS1649/0S3649 has a 150 resistor in series with the
outputs to dampen transients caused by the fast-switching

output. The OS1679/0S3679 has a direct low impedance
output for use with or without an external resistor.

co
.......

Features

en

Truth Table
EOUIVALENT OUTPUT

EOUIVALENT INPUT

Vce

Disable Input
DIS 1

DIS2

0
0
0
1
1

0
0
1
0
1

x=

Input Output

0
1

1
0
Hi-Z
Hi-Z
Hi-Z

X
X
X

Don't care

Hi·Z = TAI·5TATE mode

L _ __ _

GNO

"051649/053649 only

TLlF17515-1

Connection Diagram

Typical Application
DSlIICS
OR
DSlII7.

Dual-In-Llne Package
IN I

oura

IN 5

OUTS

IN 4

r----'

OUT4
I·BIT RAM
ADDRESS

MDS
DRIVER

DISABLE

ADDRESS
LINES

MM5Z10
OR

MMmo
DSl649
OR
DSll11
I·BITRAM
ADDRESS

MDS
DRIVER

DISABLE

DIS 1

IN lOUT 1

IN 2

OUT 2

IN 3

OUT 3

GNO

DSl648
OR
DSl611

TL/F/7515-2

Top View

CLOCK

Order Number DS1649J, DS3649J,
DS1679J, DS3679J, DS3649N or DS3679N
See NS Package Number J16A or N16A

MDSRAM
ARRAY

REFRESH.
ADDRESS
LINES

L ____

"0" ADDRESS
"I· COUNTER

MDS
COUNTER
DRIVER

ENABLE
ADDRESSOR
CDUNTSELECT

5-39

c
en
w
~

• High speed capabilities
• Typ 9 ns driving 50 pF
• Typ 30 ns driving 500 pF
• TRI-STATE outputs for data bussing
• Built-in 150 damping resistor (OS1649/0S3649)
• Same pin-out as OM8096 and OM74366

Schematic Diagram

DIH

c

en
.....
en
~

The OS1649/0S3649 and OS1679/0S3679 are Hex
TRI-STATE MOS drivers with outputs designed to drive
large capacitive loads up to 500 pF associated with MOS
memory systems, PNP input transistors are employed to reduce input currents allowing the large fan-out to these drivers needed in memory systems. The circuit has Schottkyclamped transistor logic for minimum propagation delay,
and TRI-STATE outputs for bus operation.

Vce

~

co

.......

TLlF17515-3

co

en
.....
(0
('t)

(1J

c.......
en
.....
(0
,....
(1J
c.......

Absolute Maximum Ratings

Supply Voltage

7.0V

Logical "1" Input Voltage

7.0V

en

Logical "0" Input Voltage

(0
('t)

Storage Temperature Range

~

(1J

c.......
en
~

(0
,....

Operating Conditions

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (Vee
Temperature (TA)
OS1649,OS1679
OS3649, OS3679

Min
4.5

Max
5.5

Units
V

-55
0

+125
+70

°C
°C

• Derate cavity package 9.1 mWrc above 2S'C; derate molded package
10.2 mWrC above 2S'C.

-1.5V
- 65°C to + 150·C

Maximum Power Oissipation" at 25°C
Cavity Package
Molded Package

1371 mW
1280 mW

Lead Temperature (Soldering, 10 sec.)

300·C

(1J

c

Electrical Characteristics (Note 2 and 3)
Symbol

Parameter

VIN(1)

Logical "1" Input Voltage

VIN(O)

Logical "0" Input Voltage

IIN(1)

Logical "1" Input Current

Vee

= 5.5V, VIN = 5.5V

IIN(O)

Logical "0" Input Current

Vee

= 5.5V, VIN = 0.5V

VeLAMP

Input Clamp Voltage

Vee

= 4.5V, liN = -18 mA

VOH

Logical "1" Output Voltage
(No Load)

Vee

= 4.5V, IOH = -10 J-LA

Logical "0" Output Voltage
(No Load)

Vee

Logical "1" Output Voltage
(With Load)

Vee

VOL

VOH

VOL

Logical "0" Output Voltage
(With Load)

Typ

Max

Vee

= 4.5V, IOL = 10 J-LA
= 4.5V, IOH = -1.0 mA

= 4.5V, IOL = 20 mA

Vee = 4.5V, VOUT

100

Logical "0" Orive Current

Vee

Hi-Z

TRI-STATE Output Current

VOUT

Icc

Power Supply Current

Vee = 5.5V

Units
V

2.0

Logical "1" Orive Current

110

Min

Conditions

0.8

V

0.1

40

J-LA

-50

-250

J-LA

-0.75

-1.2

V

OS1649/0S1679

2.7

3.6

OS3649/0S3679

2.8

3.6

V

OS1649/0S1679

0.25

0.4

V

OS3649/0S3679

0.25

0.35

V

OS1649

2.4

3.5

V

OS1679

2.5

3.5

V

OS3649

2.6

3.5

V

OS3679

2.7

3.5

V

OS1649

0.6

1.1

V

OS1679

0.4

0.5

V

OS3649

0.6

1.0

V

OS3679

0.4

0.5

= OV (Note 4)

-250

= 4.5V, VOUT = 4.5V (Note 4)
= O.4V to 2.4V, 0lS1 or 0lS2 = 2.0V

150
-40

V
mA
mA

40

J-LA

One OIS Input = 3.0V
All Other Inputs = X

42

75

mA

All Inputs = OV

11

20

mA

5-40

Switching Characteristics
Symbol

c
en

(Vee = 5V, T A = 25°C) (Note 4)

Parameter

-10.

0)

Conditions

ts±

Storage Delay Negative Edge

(Figure 1)

ts±

Storage Delay Positive Edge

(Figure 1)

Min

CL = 50 pF

Typ

Max

Units

4.5

7

ns

~

co

"-

c
en
w

CL

= 500 pF

7.5

12

ns

CL

= 50 pF

5

8

ns

CL

= 500 pF

8

13

ns

CL

= 50 pF

5

8

ns

.......

CL

= 500 pF

22

35

ns

"-

CL

= 50 pF

6

9

ns

0)
~

co

"-

c
en
-10.

Fall Time

tF

(Figure 1)

(Figure 1)

Rise Time

tR

CL = 500 pF

21

35

ns

tZL

Delay from Disable Input to Logical "0"
Level (from High Impedance State)

CL
RL

= 50 pF
= 2 kn to Vee (Figure 2)

10

15

ns

tZH

Delay from Disable Input to Logical "1"
Level (from High Impedance State)

CL
RL

= 50 pF
= 2 kn to GND (Figure 2)

8

15

ns

tLZ

Delay from Disable Input to High Impedance
State (from Logical "0" Level)

CL
RL

= 50 pF
= 400n to Vec(Figure3)

15

25

ns

tHZ

Delay from Disable Input to High Impedance
State (from Logical "1" Level)

CL
RL

= 50 pF
= 400n to GND (Figure 3)

10

25

ns

0)

co

c
en
w

0)

.......

co

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the -55'C to + 125'C temperature range for the 051649 and 051679 and across the Q'C to
+ 7Q'C range for the 053649 and 053679. All typical values are for TA = 25'C and Vcc = 5V.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: When measuring output drive current and switching response for the 051679 and 053679 a 1511 resistor should be placed in series with each output. This
resistor is internal to the 051649/053649 and need not be added.

AC Test Circuits and Switching Time Waveforms
ts±, ts=!=, tR, tF

Vee

I

PULSE
GENERATOR
(NOTE 1)

I--

~'~
OUT
IN

OUT

~*!~

3V

•

,"PUT--:{'."

1::
1

OV

OUT

_IS+-

OUTPUT

~%10%

\t.5V

--l

-IS-+
90%

to%

I/.

INO" 21
-- I-If

'::"

-j

-IR

TL/F17515-5
TL/F17515-4

FIGURE 1

5-41

III

AC Test Circuits and Switching Time Waveforms

(Continued)

tZH

tZl
vee

Vee

O.lI'F

O.lI'F

~

VIN

2k

*RD

VOUT

VOUT
50 pF

1.0TE2IJ,

50 pf

J,"OTEII

2k

':"

':"

~

*Ro

':"
TL/F17515-6

TL/F17515-7

DISABLE
INPUT

OUTPUT

TL/F/7515-B

FIGURE 2

tLZ

tHZ
Vee

vee
O.lI'F

O.ll'f

~

VIN

~

*RO
VOUT
50 pF

1NOTE2I1
':"

.....""""............0 Vo UT

50 pF

4D0

J'NDTEII
':"
TL/F/7515-9

TL/F17515-10

DISABLE
INPUT

VOH
OUTPUT

VOL---------'-~--~~

"Internal on 051649 and 053649

TL/F17515-11

FIGURE 3
Note 1: The pulse generator has the following characteristics: ZOUT

=

son and PRR

Note 2: CL includes probe and jig capacitance.

5-42

$;

1 MHz. Rise and fall times between 10% and 90% points

$;

5 ns.

c

en

~National

~

en

U1

~ Semiconductor

~

......

c
en
w

DS1651/DS3651
Quad High Speed MOS Sense Amplifiers
General Description

Features

The OS1651/0S3651 is TTL compatible high speed circuits
intended for sensing in a broad range of MaS memory system applications. Switching speeds have been enhanced
over conventional sense amplifiers by application of
Schottky technology, and TAI-STATE® strobing is incorporated, offering a high impedance output state for bused organization.
The OS1651/0S3651 has active pull-up outputs and offers
open collector outputs providing implied "AND" operations.

•
•
•
•
•
•

Connection Diagram

Truth Table

en

U1
~

High speed
TTL compatible
Input sensitivity - ± 7 mV
TAl-STATE outputs for high speed buses
Standard supply voltages - ± 5V
Pin and function compatible with MC3430

Dual-In-Llne Package
Vee

-IN B

+IN lOUT B

VEE

OUT D

+IN D

Input

-IN D

Output

Strobe

DS3651

+ 70°C
-7 mV ~ VID ~ + 7 mV
TA = O°Cto + 70°C

L
H

H
Open

L
H

X
Open

VIO:::: -7mV
TA = O°Cto + 70°C

L
H

L
Open

VID:::: 7 mV
TA = O°Cto

-IN A

+IN A

DUT A

sn

DUT e

+IN e

-IN e

L = Low logic state
H = High logic state
Open = TRI-STATE
x = Indeterminate state

GND

Top View

TLlF17528-1

Order Number DS1651J, DS3651J or DS3651N
See NS Package Number J16A or N16A

Typical Applications
A Typical MOS Memory Sensing Application for a 4k word by 4-blt
memory arrangement employing 1103 type memory devices

•

)0--.......1--0 DATA IIU

ZOD

-=

DATA BIT 3
JO---t~r-OOATA

-=
200

200

-=

lIT J

OATABIT2
)o--iHI-ODATA lIT Z

-=

I

DATA BIT I

)O--+~I-oDATAIITI

+5V
Ilk

2ao
STROlE

-=

L ____

Note: Only 4 devices are required for a 4k word

5-43

by 16-bit memory system.

I
J
TLlF17528-2

.....
II)

CD
C")

CJ)

c.......

.....

II)

CD

.....

CJ)

c

Absolute Maximum Ratings

Operating Conditions

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Supply Voltages
Vcc
VEE
Differential-Mode Input Signal Voltage
Range, VIOR

+ 7Voc
-'- 7Voc

Common-Mode Input Voltage Range, VICR
Strobe Input Voltage, VI(S)
Strobe Temperature Range

Supply Voltage (Vce>
DS1651
DS3651
Supply Voltage (VEE)
DS1651
DS3651
Operating Temperature (TA)
DS1651
DS3651
Output Load Current, (IOU
Differential Mode Input
Voltage Range, (VIOR)
Common-Mode Input
Voltage Range, (VICR)
Input Voltage Range (Any
Input to GND), (VIR)

± 6Voc
± 5V oc

5. 5Voc
-65·C to + 150·C

Maximum Power Dissipation· at 25°C
Cavity Package
Molded Package
Lead Temp. (Soldering, 10 seconds)

1509mW
1476 mW
300·C

• Derate cavity package 10.1 mW/,C above 25'C; derate molded package
11.8 mW I'C above 25'C.

Min

Max

Unit

4.5
4.75

5.5
5.25

V
V

-4.5
-4.75

-5.5
-5.25

V
V

-55
0

+125
+70
16

·C
·C
mA

-5.0

+5.0

V

-3.0

+3.0

V

-5.0

+3.0

V

Electrical Characteristics
vec =.5 Voc, VEE = -5 Voc, Min ~ TA ~ Max, unless otherwise noted (Notes 2 and 3)

Symbol
VIS

Parameter
Input Sensitivity, (Note 5)
(Common-Mode Voltage Range)
VICR = ~3V ~ VIN ~ +3V)

VIO

Input Offset Voltage

Conditions

Min

Typ

Min ~ Vcc ~ Max
Min ~ VEE ~ Max

Max

Unit

±7.0

mV

2

mV
20

Il A
Il A

0.8

V

-1.6

mA

DS3651

40

Il A

1

mA

DS1651

100

Il A

1

mA

118

Input Bias Current

110

Input Offset Current

VIL(S)

Strobe Input Voltage (Low State)

VIH(S)

Strobe Input Voltage (High State)

IIL(S)

Strobe Current (Low State)

Vcc = Max, VEE = Max, VIN = 0.4V

IIL(S)

Strobe Current (High State)

Vcc = Max,

VIN = 2.4V

VEE = Max

VIN = Vec

Vcc = Max, VEE = Max
0.5

V

2

VIN = 2.4V
VIN = Vcc
VOH

Output Voltage (High States)

Vcc = Min,
VEE = Min

10 = -400

VOL

Output Voltage (Low State)

Vcc = Min,

10 = 16mA

IlA

DS1651/DS3651

V

2.4

DS3651

0.45

VEE = Min

DS1651

0.50

los

Output Current Short Circuit

Vcc = Max, VEE = Max,
(Note 4)

DS1651/DS3651

10FF

Output Disable Leakage Current

Vcc = Max, VEE = Max

-18

V

-70

mA

DS3651

40

DS1651

100

Il A
Il A

lec

High Logic Level Supply Current

Vcc = Max, VEE = Max

45

60

mA

lEE

High Logic Level Supply Current

Vcc = Max, VEE = Max

-17

-30

mA

5-44

Switching Characteristics Vcc =

5 Voc, VEE = -5 Voc, TA = 25°C unless otherwise noted.

Symbol

Parameter

Typ

Max

Units

tpHL(O)

High-to-Low Logic Level Propagation
Oelay Time (Oifferentiallnputs)

5mV + VIS,
(Figure 2)

Conditions
OS1651/
OS3651

Min

23

45

ns

tpLH(O)

Low-to-High Logic Level Propagation
Oelay Time (Oifferentiallnputs)

5mV + VIS,
(Figure 2)

OS1651/
OS3651

22

55

ns

tpOH(S)

TRI-STATE to High Logic Level
Propagation Oelay Time (Strobe)

(Figure 1)

OS1651/
OS3651

16

21

ns

tpHO(S)

High Logic Level to TRI-STATE
Propagation Oelay Time (Strobe)

(Figure 1)

OS1651/
OS3651

7

18

ns

tpOL(S)

TRI-STATE to Low Logic Level
Propagation Oelay Time (Strobe)

(Figure 1)

OS1651/
OS3651

19

27

ns

tpLO(S)

Low Logic Level to TRI-STATE
Propagation Oelay Time (Strobe)

(Figure 1)

OS1651/
OS3651

14

29

ns

0)

U1

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the device should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified min/max limits apply across the O'C to
All typical values are for TA = 25'C, Vee = 5V and VEE = -5V.

+ 70'C range for the 053651

and across the -55'C to

+ 12S'C range for the 051651.

Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: A parameter which is of primary concern when designing with sense amplifiers is, what is the minimum differential input voltage required at the sense
amplifier input terminals to guarantee a given output logic state. This parameter is commonly referred to as threshold voltage. It is well known that deSign
considerations of threshold voltage are plagued by input offset currents, bias currents, network source resistances, and voltage gain. As a deSign convenience, the
051651 and 053651 are specified to a parameter called input sensitivity (VIS)' This parameter takes into consideration input offset currents and bias currents, and
guarantees a minimum input differiential voltage to cause a given output logic state with respect to a maximum source impedance of 2000 at each input.

Switching Time Waveform
5V
1

VI

.

16

2

V2

~

0+

~

E1Ne~
~

051651/
053651

12

.!!o
~

~~

-=

r

~

~
~
13

.20--

390
51
01

1
Cl*,

~
I ""

5V

lk

~,

i; lN916

; ~ OREOUIV

'-52

EO

Note: Output of channel B shown under test,

~

TLlFI752B-3

other channels are tested similarly.

Delay

V1

V2

51

52

CL

tpLO(S)
tpOL(S)
tpHO(S)
tpOH(S)

100mV
100mV
GNO
GNO

GNO
GNO
100mV
100 mV

Closed
Closed
Closed
Open

Closed
Open
Closed
Closed

15 pF
50 pF
15 pF
50pF

CL includes jig and probe capacitance.
EIN waveform characteristics: tTLH and tTHL ~ 10 ns measured 10% to 90%
PRR

= 1 MHz
= 50%

Outy cycle

5-45

c
en
.....
0)
U1
.....
c
'"
en
w
.....

......

Lt)

<0

C")

(/)

AC Test Circuits

c
......

tpLO(S)

......

<0

......

EIN

JV

(/)

c

tpHO(S)

/.0%

Lt)

DV~

tpLO(S)
_----"1.SV

vOH------~,~
H~O(_S)
~1II~.---------VOH-O.5V
...

EO

EO

______

VOL------

'" 1.5V
TL/F17528-5

TLlF/7528-4

tpOL(S)

tpOH(S)
JV

JV\

'IN

,,~'"

EIN
OV----~~------

tpOH(S)

tpOl(S)

VOH------+-,~-----

5V - VO 1 - - - - - - _

EO

EO

OV----

VOl---------~-------

TLlF17528-7

TLlF17528-6

FIGURE 1. Strobe Propagation Delay tpLO(S). tpOL(S). tpHL(S) and tpOH(S)
5V

100 mV
16

15

OS1651/0S3651

1-<>-+....."""0 -5V

TL/F/7528-10

Note: Output of channel 8 shown under test, other channels are tested similarly.
51 at "8" for 051651/053651, CL

= 50 pF total for 051651/053651

TL/F/7528-11

EIN waveform characteristics:
tTLH and tTHL
PRR

=

:S;

10 ns measured 10% to 90%

1 MHz, duty cycle

=

500 ns

FIGURE 2. Differential Input Propagation Delay tpLH(D) and tpHL(D)

5·46

c

en

Schematic Diagrams

-"
0')

U1
-"

0516511053651
850

c
'"
en
CAl

850

0')

U1
-"

OUTPUT
INPUT

[0----+---'
~-~~--~-~GNO

4k

4k

VEEo---~----~--~---4----

~~----o

1/4 OF CIRCUIT SHOWN

STROBE

TO OTHER
CIRCUITS

TL/F/7S28-12

Typical Applications
Transfer Characteristics
and Equations for
Level Detector with Hysteresis

Level Detector with Hysteresis
HS

1/4 DS1651/DS3651

VREF

4

en
~

o
2
o

VLOW

>

VHIGH

~VH

I-~

VREF
TLlFI7S28-1S

4

VIN (VOL lSI
TLlF/7S28-16
R2 [VO(MAX) - VREFI
Rl + R2
VHIGH = VREF I

VLOW = VREF

+

R2 [VO(MIN) - VREFI
Rl + R2

Hysteresis Loop (VH)
VH

5-47

= VHIGH

R2

- VLOW

= Rl + R2 [VO(MAX)

- VO(MIN)1

,....
Ln

CD

C")

UJ

Typical Applications

(Continued)

C

4·81t Parallel AID Converter

........
,....
Ln

CD
,....

5.0V

UJ

C

'0
60 mA

I

R

O.lI'F~

270

270

270

270

VIN
R

R

R

R

R

R

~--~----------~-----------+--~--~~~~23

R

R

R

X>---+---+--~~----~
R

R

__

~--~-e-------------L ~>---+---~---------~

R

----------20

10--....
R

-

TLlF17528-14

~=~+~~+~~+~~+~~+u~+~~+~~

21 = (8 + 0) (F +
22 = (0 + J)(N)

23

=

J)

(L + N) (R)

J

Conversion time "" 50 ns

5·48

~National

~ Semiconductor
OS1674/0S3674 Quad TTL to MOS Clock Drivers
General Description
The 051674/053674 is a quad bipolar-to-MOS clock driver
with TTL compatible inputs. It is designed to provide high
output current and voltage capabilities necessary for optimum driving of high capacitance N-channel MOS memory
systems.
The device features two common enable inputs, a refresh
input, and a clock control input for simplified system designs. The circuit was designed for driving highly capacitive
loads at high speeds and uses Schottky-clamped transistors. PNP transisitors are used on all inputs thereby minimizing input loading.
The circuit may be connected to provide a 12V clock output
amplitude as required by 4k RAMs or a 5V clock output
amplitude as required by 16k RAMs.

The 051674/053674 has a direct, low impedance output
for use with or without an external damping resistor.

Features
•
•
•
•
•
•
•

TTL compatible inputs
12V clock or 5V clock driver
Operates from standard bipolar and MOS supplies
PNP inputs minimize loading
High voltage/current outputs
Input and output clamping diodes
Control logic optimized for use with MOS memory systems
• Pin and function compatible with MC3460 and 3235

Schematic and Connection Diagrams
VCC3
EQUIVALENT INPUT

I
INPUT

~--...~.....- - _ o

I

OUTPUT

INTERNAL
LOGIC
CIRCUITRY

I
I
I
I

I ___ _
L
~-4~--------'------'---------4----oGNO

TL/F/5876-1

Dual-ln-L1ne Package
VCCI

auTO

IlL D

EN I

EN I

IlL C

OUT C

VCCJ

TLlF/5876-2

Top View
Order Number DS3674J or DS3674N
See NS Package Number J16A or N16A
5-49

•

Absolute Maximum Ratings

Operating Conditions

(Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
VCC1
13.5V
VCC2
16V
VCC3
Input Voltage
-1.0Vto +7V
Output Voltage

-1.0Vto +16V

Storage Temperature Range

- 65°C to + 150°C

Maximum Power Oissipation* at 25°C
Cavity Package
Molded Package

Min

Max

Units

VCC1
OS1674
OS3674

4.5
4.75

5.5
5.25

V
V

VCC2
OS1674
OS3674

4.5
4.75

13.2
12.6

V
V

VCC3
OS1674
OS3674

VCC2
VCC2

16.5
15.75

V
V

-55
0

+125
+70

°C
°C

Supply Voltage

1509 mW
1476 mW

Temperature, TA
OS1674
OS3674

Lead Temperature (Soldering, 10 sec.)
300°C
• Derate cavity package 10.1 mWI'C above 25'C; derate molded package
11.6 mW I'C above 25'C.

Electrical Characteristics
5V operation, (VCC1 = VCC2 = 5V, VCC3 = 12V); 12V operation, (VCC1 = 5V, VCC2 = 12V, VCC3 = VCC2 + (3V ±10%»;
OS1674, ± 10% power supply tolerances; OS3674, ±5% power supply tolerances, unless otherwise noted. (Notes 2,3 and 4).

Symbol

Parameter

VIH

Logical "1" Input Voltage

Vil

Logical "0" Input Voltage

IIH

Logical "1" Input Current

III

Logical "0" Input Current

Conditions

Min

VIN

VIN

= 5.5V

0.8

V

V

10

/LA

All Other Inputs

0.04

40

/LA

Select Inputs

= OAV

11= -12mA

Input Clamp Voltage

VOH

Logical "1" Output Voltage

IOH

= -1 rnA, Vil = 0.8V

VOL

Logical "0" Output Voltage

IOl

= 5 rnA, VIH = 2.0V

VOC

Output Clamp Voltage

loc = 5 rnA, Vil

ICCH

Supply Current Output High

VCC2 -0.5

= 0.8V
VCC1 = Max

ICC1
All Inputs VIN = OV
Outputs Open

ICC2

12V Operation

5V Operation

ICC3
ICCl

Units

0.01

Vco

ICC3

Max

Select Inputs

All Other Inputs

ICC2

Typ

2

-40

-250

/LA

-0.16

-1.0

mA

-0.8

-1.5

V

0.3

0.5

V

VCC2 +0.8

VCC2 + 1.5

V

V

VCC2 -0.2

18

27

mA

-2

-4

rnA

2

4

rnA

-8

-16

mA

8

16

rnA

25

40

rnA

3

rnA

Supply Currents Outputs Low
ICC1
ICC2

All Inputs VIN = 5V
Outputs Open

VCC1

= 5.25V

VCC2

= 12.6V

16
25
rnA
VCC3 = 15.75V
ICC3
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the -55'C to + 125'C temperature range for the OS1674 and across the O'C to + 70'C range for
the OS3674. All typicals are given for TA = 25'C.
Note 3: All currents into device pins shown as positive. out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: For AC measurements, a 100 resistor must be placed in series with the output of the OS1674/0S3674.

5-50

Switching Characteristics TA =
Symbol

Parameter
Storage Delay Negative Edge

RD = 10n

ts-+

Storage Delay Positive Edge

RD = 10n

tF

Fall Time

RD = 10n

tpdO

tpd1

Rise Time

RD = 10n

Propagation Delay to a
Logical "0"

RD = 10n

Propagation Delay to a
Logical "1"

RD = 10n

0')

Typ

Max

Units

CL = 100 pF

8

11

ns

CL = 400 pF

12

16

ns

CL = 100 pF

10

13

ns

CL = 400 pF

13

16

ns

CL = 100 pF

9

16

ns

CL = 400 pF

17

24

ns

CL = 100 pF

8

12

ns

CL = 400 pF

13

19

ns

CL = 100 pF

17

27

ns

CL = 400 pF

29

40

ns

CL = 100pF

18

25

ns

CL = 400 pF

26

35

ns

Conditions

ts+ -

tR

c
en
......

25°C unless otherwise noted, (Note 4), (Figures 1,2, :3 and 4)
Min

AC Test Circuits and Switching Time Waveforms
sv 12V

I I

1r

VCC1 VCC2 VCC3
PULSE
GENERATOR
(NOTE 11

~
INPUT

.A

OUT

IN

''''l

CL
T(NOTE2)

GNO

REFRESH INPUT • 2.4V
ALLOTHERINPUTS=OV

(INTERNAL ON
lOA OS1644/0S3644)

11

TL/F/5876-3

FIGURE 1. 12V Operation

3V
INPUT
OV

I

J
ts+--

VOH

1.SV)r-

-H.SV

--

--

-~C2-'V
OUTPUT

--ts-+
~"""VCC2-2V

I

+ZV...,1-

-'r-+2V
VOL

~

-- --

- --tR

tF

- --

I--tpd1-

tpdO

TL/F/5876-4

FIGURE 2. 12V Operation

5-51

......

~
......

c
en
w
0')

......

~

AC Test Circuits and Switching Time Waveforms
5V

PULSE
GENERATOR
(NOTE 1)

SELECT
INPUT

5V

(Continued)

12V

10

IN

OUT~"",,-

CL
T(NOTE2)
REFRESH INPUT = 2.4V
ALL OTHER INPUTS =OV

TL/F/5876-5

FIGURE 3. 5V Operation

3V----------J~------------~
INPUT
OV-----I
VOH ---------+-.1

OUTPUT

VOL---------+-+~~----------~--~

TL/F/5876-6

FIGURE 4. 5V Operation
Note 1: The pulse generator has the following characteristics. PPR = 1 MHz, tR ~ 10 ns, ZOUT = 50n.

Note 2: CL includes probe and jig capacitance.

5·52

c

en
.....

Truth Table

en
.......

~
......

Input
Enable

Enable

1

2

1
X
X
X

0
0

X
1
X
X
0
0

Select
Input
X
X
X
1
0
X

5-53

Clock
Input

Refresh
Input

X
X
1
X
0
0

X
X
X
1
X
0

Output

c
en
w

en

.......
~

0
0
0
0
1
1

en
.....
,...
CD
C")

CJ)

c.......
en

"III:t
,...
CD
C")

CJ)

r----------------------------------------------------------------------------------,
~National

~ Semiconductor
0516149/0536149,0516179/0536179 Hex M05 Orivers

c

.......
en General Description
.....
,... The 0516149/0536149 and 051617910536179 are Hex
CD
,...

CJ)

c
.......
en

"III:t
,...
CD
,...
CJ)
c

MOS drivers with outputs designed to drive large capacitive
loads up to 500 pF associated with M05 memory systems.
PNP input transistors are employed to reduce input currents
allowing the large fan-out to these drivers needed in memory systems. The circuit has 5chottky-clamped transistor logic for minimum propagation delay, and a disable control that
places the outputs in the logic "1" state (see truth table).
This is especially useful in M05 RAM applications where a
set of address lines has to be in the logic "1" state during
refresh.

Features
• High speed capabilities
• Typ 9 ns driving 50 pF
• Typ 29 ns driving 500 pF
• Built-in 15 n damping resistor (0516149/0536149)
• 5ame pin-out as OM8096 and OM74366

The 0516149/0536149 has a 15 n resistor in series with
the outputs to dampen transients caused by the fast-switching output. The 0516179/0536179 has a direct low impedance output for use with or without an external resistor.

Schematic Diagram

EOUIVALENT OUTPUT

EOUIVALENT INPUT

r------------------------------.------~------~----__oVCC

INTERNAL
LOGIC
CIRCUITRY

15*
~-----4""''V\'''''''-O OUTPUT

INPUT

*0516149/0536149 only.

L

~~.....-----------------e-----------------~------~----~GNO

TL/F17553-1

5-54

Absolute Maximum Ratings

Operating Conditions

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7.0V

Logical "1" Input Voltage

7.0V

Logical "0" Input Voltage
Storage Temperature Range

Supply Voltage (Vee>
Temperature (T A)
OS16149,OS16179
OS36149,OS36179

Min
4.5

Max
5.5

Units
V

-55
0

+125
+70

°C
°C

-1.5V
- 65°C to + 150°C

Maximum Power Oissipation· at 25°C
Cavity Package
Molded Package

1371 mW
1280 mW

Lead Temperature (Soldering 10 seconds)

300°C

·Derate cavity package 9.1 mW/"C above 25·C; derate molded package
10.2 m/W·C above 25·C.

DC Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Min

Conditions

Max

Units

0.8

V

0.1

40

J.LA

-50

-250

J.LA

-1.2

V

Typ

V

VIN(1)

Logical "1" Input Voltage

VIN(O)

Logical "0" Input Voltage

IIN(1)

Logical "1" Input Current

Vee = 5.5V, VIN = 5.5V

IIN(O)

Logical "0" Input Current

Vee = 5.5V, VIN = 0.5V

VeLAMP

Input Clamp Voltage

Vee = 4.5V, liN = -18 rnA

-0.75

VOH

Logical "1" Output Voltage
(No Load)

VOL

VOH

Logical "0" Output Voltage
(No Load)

2.0

Vee = 4.5V,IOH = -10 J.LA

Vee = 4.5V, IOL = 10 J.LA

Logical "1" Output Voltage
(With Load)
Vee = 4.5V, 10H = -1.0 mA

VOL

Logical "0" Output Voltage
(With Load)
Vee = 4.5V, 10L = 20 mA

OS16149/0S16179

3.4

4.3

OS36149/0S36179

3.5

4.3
0.25

0.4

V

OS36149/0S36179

0.25

0.35

V

OS16149

2.4

3.5

V

OS16179

2.5

3.5

V

OS36149

2.6

3.5

V

OS36179

2.7

3.5
0.6

1.1

V

OS16179

0.4

0.5

V

OS36149

0.6

1.0

V

OS36179

0.4

0.5

V

Logical "1" Orive Current

Vee = 4.5V, VOUT = OV, (Note 4)

Logical "0" Orive Current

Vee = 4.5V, VOUT = 4.5V, (Note 4)

lee

Power Supply Current

Oisable Inputs = OV
All Other Inputs = 3V

ts±

tSf

tF

Parameter
Storage Oelay Negative Edge

Storage Oelay Positive Edge

Fall Time

-250

mA

150

mA

33

All Inputs = OV

Symbol

V

OS16149

100

Switching Characteristics (Vee =

V

OS16149/0S16179

110

Vee = 5.5V

V

14

60

mA

20

mA

5V, TA = 25°C) (Note 4)
Typ

Max

CL = 50 pF

4.5

7

ns

CL = 500 pF

7.5

12

ns

Conditions
(Figure 1)

(Figure 1)

(Figure 1)

5-55

Min

Units

CL = 50 pF

5

8

ns

CL = 500 pF

8

13

ns

CL = 50 pF

5

8

ns

CL = 500 pF

22

35

ns

0)

.....
,..
CD
C")

U)

Switching Characteristics (Vee =

c.......

Symbol

,..

tR

0)
~

5V, TA

= 25°C) (Note 4) (Continued)

Conditions

Parameter
Rise Time

CL

CD
C")

U)

c
.......

tLH

Delay from Disable Input
to Logical "1"

.....
,..
CD
,..

tHL

Delay from Disable Input
to Logical "0"

0)

U)

c.......
0)

Min

= 50 pF
CL = 500 pF

(Figure 1)

= 2 kO to Gnd,
= 50 pF, (Figure 2)
RL = 2kOtoVee,
CL = 50 pF, (Figure 3)

RL
CL

Typ

Max

Units

6

9

ns

26

35

ns

15

22

ns

11

18

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation .

~
,..

Note 2: Unless otherwise specified minImax limits apply across the -SS'C to + 12S'C temperature range for the OS16149 and OS16179 and across the O'C to
+70'C range for the OS36149 and OS36179. All typical values are for TA = 2S'C and Vcc = SV.

U)

Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.

CD
,..

c

Note 4: When measuring output drive current and switching response for the OS16179 and OS36179 a lS
This resistor is internal to the OS16149/0S36149 and need not be added.

Connection Diagram

Truth Table

Dual In-Line Package
vee

DIS 2

IN 6

OUTS

IN 5

OUT5

Disable Input
IN 4

OUT4

DIS 1

DIS2

a

0
0

0
0

x=

DIS 1

IN lOUT 1

IN 2

n resistor should be placed in series with each output.

DUT 2

IN 3

DUll

1

1

0

1

1

Input

Output

0

1
0

1
X
X
X

1
1
1

Oon't care

GND

TL/FI7S53-2

Top View
Order Number DS16149J, DS36149J, DS16179J,
DS36179J, DS36149N or DS36179N
See NS Package Number J16A or N16A

AC Test Circuits and Switching Time Waveforms
ts±, ts±, tR, tF
Vee

3V

INPUT- - - - : { ' . ,
DV

....""''''''. .-OVOUT

OUTPUT

TLlF17553-3

FIGURE 1
5·56

c

....en
....

AC Test Circuits and Switching Time Waveforms (Continued)

(7)

tLH

~

U)

........

Vee

c

en
....

....
......
(7)

INPUTji;.5V

U)

........

c
en
w

'LH

t-~~....-

......-o VOUT

~

OUTPUT

....

----r

VOL
2k

(7)

~

0.5 V

U)

........
TLIF/7553-4

FIGURE 2

c
en
w

..........
(7)

U)

Vee
0.1 jJF

~
....""""....- 0 VOUT

TL/F/7553-5

FIGURE 3
"Internal on 0516149 and 0536149
Note 1: The pulse generator has the following characteristics: ZOUT = 50 nand PRR

s:

1 MHz. Rise and fall times between 10% and 90% points

Note 2: CL includes probe and jig capacitance.

Typical Applications

r----..,I

t------__
1--------4
t------.. . .

6·BIT RAM
ADDRESS

I

ADDRESS
LINES

I
I
MM527D
OR
I
MM5280
MOS RAM
ARRAY
I
I
REFRESH
I
I-I-HH~-...... ~IDN~~ESS
I
I
L _ _ _ _ .J
I-I-H~----4

6·BIT RAM
ADDRESS

&

"0" ADDRESS
"1" COUNTER
CLOCK

ENABLE

TL/F/7553-6

5·57

s:

5 ns.

II)

N

~ ~National
~ Semiconductor

e
II)

N

~ 0555325/0575325
Memory Drivers

en
c

General Description
The DS55325 and DS75325 are monolithic memory drivers
which feature high current outputs as well as internal decoding of logic inputs. These circuits are designed for use with
magnetic memories.
The circuit contains two 600 mA sink-switch pairs and two
600 mA source-switch pairs. Inputs A and B determine
source selection while the source strobe (S1) allows the
selected source turn on. In the same manner, inputs C and
o determine sink selection while the sink strobe (S2) allows
the selected sink turn on.

to operate at higher source currents for a given junction
temperature. If this method of source current setting is not
desired, then Nodes Rand RINT can be shorted externally,
activating an internal resistor connected from VCC2 to Node
R. This provides adequate base drive for source currents up
to 375 mA with VCC2 = 15V or 600 mA with VCC2 = 24V.
The OS55325 operates over the fully military temperature
range of - 55°C to + 125°C, while the OS75325 operates
from O°C to + 70°C.

Features

Sink-output collectors feature an internal pull-up resistor in
parallel with a clamping diode connected to VCC2. This protects the outputs from voltage surges associated with
switching inductive loads.
The source stage features Node R which allows extreme
flexibility in source current selection by controlling the
amount of base drive to each source transistor. This method
of setting the base drive brings the power associated with
the resistor outside the package thereby allowing the circuit

•
•
•
•
•
•
•

Connection Diagram

Truth Table

Dual-In-Line Package
NODE

R

RINT

D

600 mA output capability
24V output capability
Dual sink and dual source outputs
Fast switching times
Source base drive externally adjustable
Input clamping diodes
TTL compatible

Address Inputs

z

Source
A
B

VCCI

16

L
H
X
X
X
H

H
L
X
X
X
H

Sink
C D
X X
X X
L
H
H
L
X X
H H

Strobe Inputs
Source
S1

Sink
S2

L
L
H
H
H
X

H
H
L
L
H
X

Outputs
Source
W X
ON
OFF
OFF
OFF
OFF
OFF

OFF
ON
OFF
OFF
OFF
OFF

H = High Level, L = Low Level, X = Irrelevant
Note: Not more than one output is to be on at anyone time.

SOURCE W
COLLECTORS

A

SI

S2

C

y

GND

'----'
STROBES
TL/F/9755-2

Top View
Order Number DS55325J,
DS75325J or DS75325N
See NS Package Number J14A or N14A

5-58

Sink
Y
Z
OFF OFF
OFF OFF
ON OFF
OFF ON
OFF OFF
OFF OFF

c
Absolute Maximum Ratings

en
01
01

(Note 1)

If MilitaryI Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Supply Voltage VCC1 (Note 5)

- 65°C to + 150°C

Storage Temperature Range
Lead Temperature
(Soldering, 10 seconds)

300°C

7V

Supply Voltage VCC2 (Note 5)

25V

Input Voltage (Any Address or Strobe Input)

5.5V

Operating Conditions
Temperature (TA)
OS55325
OS75325

Maximum Power Dissipation· at 25°C
Cavity Package
1509 mW
Molded Package
1476 mW
"Derate Cavity Package 10.1 mW/,C above 25'C; derate molded package
11.8 mW /'C above 25'C.

Symbol

Parameter

Max

Units

-55
0

+125
+70

°C
°C

Min

Conditions

High Level Input Voltage

(Figures 1 and 2)

VIL

Low Level Input Voltage

(Figures 3 and 4)

VI

Input Clamp Voltage

VCC1 = 4.5V, VCC2 = 24V, liN = -12 mA
T A = 25°C (Figure 5)

IOFF

Source Collectors Terminal
"Off" State Current

VCC1 = 4.5V, VCC2 = 24V
(Figure 1)

TA = 25°C

01

-1.7

V

OS55325

500

IJ-A

OS75325

200

IJ-A

OS55325

3

150

IJ-A

OS75325

3

200

IJ-A

VSAT

Saturation Voltage Source
Outputs

VCC1 = 4.5V, VCC2 = 15V,
RL = 24!l,
ISOURCE ::::: - 600 mA
(Figure 3) (Notes 4 and 6)
VCC1 = 4.5V, VCC2 = 15V,
RL = 24!l,
ISINK ::::: 600 mA (Figure 4)
(Notes 4 and 6)

19

0.9

V

OS55325

0.43

0.7

V

OS75325

0.43

0.75

V

0.9

V
V

Full Range
TA = 25°C

V

23

Full Range
TA = 25°C

Units
V

-1.3

VCC1 = 4.5V, VCC2 = 24V, lOUT = 0 mA (Figure 2)

Saturation Voltage
Sink Outputs

Max

V

High Level Sink Output Voltage

OS55325

0.43

0.7

OS75325

0.43

0.75

V

1

mA

II

Input Current at Maximum
Input Voltage

VCC1 = 5.5V, VCC2 = 24V,
VI = 5.5V (Figure 5)

Address Inputs

2

mA

IIH

High Level Input Current

VCC1 = 5.5V, VCC2 = 24V,
VI = 2.4V (Figure 5)

Address Inputs

3

40

IJ-A

Strobe Inputs

6

80

IJ-A

Strobe Inputs

IlL

Low Level Input Current

VCC1 = 5.5V, VCC2 = 24V,
VI = O.4V (Figure 5)

Address Inputs

-1

-1.6

mA

Strobe Inputs

-2

-3.2

mA

ICC OFF

Supply Current, All Sources
and Sinks "Off"

VCC1 5.5V, VCC2 = 24V,

VCC1

14

22

mA

T A = 25°C (Figure 6)

VCC2

7.5

20

mA

Supply Current from VCC1,
Either Sink "On"

VCC1 = 5.5V, VCC2 = 24V, ISINK = 50 mA,
T A = 25°C (Figure 7)

55

70

mA

ICC1

Supply Current from VCC2,
VCC1 = 5.5V, VCC2 = 24V, ISOURCE = -50 mA
50
mA
32
Either Source "On"
T A = 25°C (Figure 8)
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the - 55'C to + 125'C temperature range for the OS55325 and across the O'C to + 70'C range for
the OS75325. All typical values are at TA = 25'C.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: Voltage values are with respect to network ground terminal.
Note 6: These parameters must be measured using pulse techniques. tw = 200 ,...s, duty cycle ~2%.

ICC2

5-59

C

en
.......
W
N

0.8

VOH

VSAT

Typ

2

Full Range

01
......

01

Min

Electrical Characteristics (Notes 2 and 3)
VIH

W
N

II)

N

('f)
II)

Switching Characteristics VCC1

.....
en

Symbol

II)

tpLH

c.......
N

('f)
II)
II)

en
c

= 5V, T A = 25°C

Parameter

VCC2 = 15V, RL = 240,
CL = 25 pF (Figure 9)

tpHL

Propagation Delay Time,
High-to-Low Level Output

VCC2 = 15V, RL = 240,
CL = 25 pF (Figure 9)

tTLH

Transition Time,
Low-to-High Level Output

CL

tTHL

ts

Typ

Max

Units

Source Collectors

25

50

ns

Sink Outputs

20

45

ns

Source Collectors

25

50

ns

Sink Outputs

20

45

ns

Source Outputs, VCC2 = 20V,
RL = 1 kO (Figure 10)

55

Sink Outputs, VCC2 = 15V,
RL = 240 (Figure 9)

7

Source Outputs, VCC2 = 20V,
RL = 1 kO (Figure 10)

7

Sink Outputs, VCC2 = 15V,
RL = 240 (Figure 9)

9

20

ns

15

30

ns

Conditions

Propagation Delay Time,
Low-to-High Level Output

Transition Time,
High-to-Low Level Output

Storage Time, Sink Outputs

CL

= 25 pF

= 25 pF

Min

VCC2 = 15V, RL = 240, CL = 25 pF (Figure 9)

DC Test Circuits
24V
(

1-----r-¥1---...
r-

2V

()o-o

-

(SEE
TEST
TA8LE}

r--

-

I
I
I
I

R

&&

VCC2

SOURCE
COLLECTORS

~:,~

•

-

.

W

t(OF'F)

18

X

I
I
I
I

Y

~C

I

...,

I
I S2

~D~
I

VCC1

GND

ZI
I
I
I
I
I

-==
-=

OPEN

=

OPEN

"-1---------- --"
1>

-

~

4.5V
Test Table
A

B

GND GND
2V

2V

S1
2V
GND

FIGURE 1.IOFF

5-60

TL/F/9755-3

ns
15

ns
ns

c
en

DC Test Circuits (Continued)

U1
U1
W
I\)

24V

p-

I
I

U1
.......

c
en
......

-----~

-

R

VCC2
RINT

I
I

U1

W

I\)

SOURCE
COLLECTORS

U1

IA

4.5V 0-.....-

Test Table

I
lSI
......--.
I
IB

W

4 . 5 V ; [ (SEE
2V
TEST
TABLE)

c

0

S2

Y

Z

2V

4.5V

GND

VOH

GND

4.5V

2V

VOH

OPEN
OPEN

GND OPEN
2V OPEN

4.5V

2V

4.5V

GND

A

B

51

O.BV

4.5V

O.BV

4.5V

O.BV

O.BV

VOH
VOH

OPEN

1

4.5V

TL/F/9755-4

FIGURE 2. VIH and VOH
15V

350

OPEN

r-

5V
4.

l

~~~.

----- ..I

VCC2

I
SOURCE I
COLLECTORS I

Test Table
(SEE
TEST
TABLE)

O.BV

r----I--O OPEN

r---I-~-O

I

OPEN

ID
I

lk I1.-VCCI_ _ _ _ _ _ _ _ _GND
_

-"

4.5V
TL/F/9755-5

Note 1: Figure 3 and 4 parameters must be measured using pulse techniques, tw = 200 ,...S, duty cycle

FIGURE 3. VIL and Source VSAT

5·61

s: 2%.

W

X

GND OPEN
OPEN GND

DC Test Circuits

(Continued)
15V

,..-.....-.--0 OPEN

A

B

lk
y

O.SVl

(SEE
TEST
TABLE)

4,5V

_I
4.5V

TL/F/9755-6

Note 1: Figure 3and 4 parameters must be measured using pulse techniques, tw = 200 /Ls, dutycycla s:2%.

Test Table

C

D

S2

Y

Z

O.BV

4.5V

O.BV

RL

OPEN

4.5V

O.BV

O.BV

OPEN

RL

FIGURE 4. VIL and Sink VSAT

5-62

c

en

DC Test Circuits (Continued)

U1
U1
W
I\)

U1
.....

24V

c

en
.....
U1
W
I\)

U1

5.5V

0 _-.-__

(SEE
TEST
TABLE)

y

r----r--o OPEN

-1

1

.---t-........-o OPEN

I

~-T!.-------':~
5.5V
(4.5V fOR
TESTING VI)
TL/F/9755-7

Test Tables

Apply VI = 5.5V
Measure II

Ground

Apply VI = 0.4V
Measure IlL

Apply 5.5V

Apply 5.5V

Apply II = -10 rnA
Measure VI

Apply VI = 2.4V
Measure IIH

S1,S,C,S2,O

A

S1

S,C,S2,O

A

S1

A,S

C,S2,O

S1

A,S,C,S2,O

S

S1

A,C,S2,O

S

A, S1, C, S2, 0

C

S2

A,S1, S,O

C

A,S1,S,S2,O

S2

C,O

A,S1,S

S2

A,S1,S,C,O

0

S2

A,S1,S,C

0

A,S1,S,C,S2

5-63

U)

N

C"')
U)

r-U'J

~-----------------------------------------------------------------------------------,

DC Test Circuits (Continued)

C

"N

U)

C"')
U)
U)

U'J

C

,.....""_-0 OPEN

SV

I
I
I
I
Ie

Y

OPEN

I
I S2
OPEN

I
10
I
I

GND

VCC1

'-n~~:----S.SV

TL/F/9755-8

FIGURE 6. ICC1 (OFF) and ICC2 (OFF)

5·64

c
en

DC Test Circuits (Continued)

U1
U1
W

I\)

CJ'1
......

24V

c
en
~

CJ'1
W

I\)

CJ'1
...... - - r - O OPEN

4.SV

o---e--+-.-.

SV

I

~ _VICC!. - - - - - - - !N.2 -"
llcC1
S.SV

TL/F/9755-9

Test Table

c
GND
5V

0

S2

y

Z

GND ISINK OPEN
GND GND OPEN ISINK
5V

FIGURE 7. ICC1. Either Sink On

5·65

Lt)

C\I
C")
Lt)

.....
en

DC Test Circuits (Continued)

c.......
Lt)

C\I

C")
Lt)
Lt)

en
c
SV

!

1:

ISO;CE

= -SOmA

y
, - - -__- 0 OPEN

c
52

,--+-~-o

OPEN

o

S.SV

TL/F/9755-10

Test Table

B

S1

GND

5V

GND

5V

GND

GND

A

FIGURE 8. ICC2. Either Source On

'.~'

5·66

c
en
U1

DC Test Circuits (Continued)

U1
W

N
U1

15V

........

C

en
......

RL
24

RL
24

U1
W
N
U1

RL
24

INPUT
SOURCE

r--....-r--t--+---II-O COLLECTORS

PULSE
GENERATOR
(NOTE 1)

x

(SEE
TEST
TABLE)

y

r - - - - - y - - - -....--f--o OUTPUT V

r---t---!--------+-o OUTPUT Z

5V
TLlF/9755-11

Note 1: The pulse generator has the following characteristics: loUT = 50n, duty cycle s; 1 %.

Note 2: CL includes probe and jig capacitance.

Voltage Waveforms
3V
INPUT

OV

OUTPUT

TLlF/9755-12

Test Table

Parameter
tpLH and tPHL

tpLH, tpHL,
tTLH, tTHL and ts

Output Under Test

Input

Connect to 5V

Aand S1

8, C, DandS2

8 and S1

A, C, 0 and S2

Sink Output Y

Cand S2

A, 8, 0 and S1

Sink Output Z

Dand S2

A, 8, Cand S1

Source Collectors

FIGURE 9. Switching Times
5-67

~

N

C")

,...
~

,-------------------------------------------------------------------------------------------,
DC Test Circuits (Continued)

U)

C

20V

......
~

N

C")
~
~

U)

C

INPUT
PULSE
GENERATOR
(NOTE 1)

}
(SEE
TEST
TABLE)

OU~UT

y

5V
TLlF/9755-13

Note 1: The pulse generator has the following characteristics: ZOUT = 500. duty cycle!: 1 %.
Note 2: CL includes probe and jig capacitance.

Voltage Waveforms

3V

INPUT

OV

OUTPUT

tTHL
TL/F/9755-14

Test Table

Parameter
tTLH and tTHL

Output Under Test

Input

Connect to 5V

Source Output W

A and S1

B, C, Dand S2

Source Output X

Band S1

A, C, Dand S2

FIGURE 10. Transition Times of Source Outputs

5·68

c

en

Schematic Diagram

U1
U1

VCCI

(,,)
I\)

VCC2

U1

.......
C

575

en

--...

RINT

U1

(,,)
I\)

U1
SOURCE
COLLECTORS

ADDRESS A

OUTPUT W
STROBE SI
NODE R

OUTPUT X
ADDRESS B

5k

OUTPUT Y

ADDRESS C

STROBE S2

-

•

5k

OUTPUT Z

ADDRESS D

t-------~~------~----------4_----------~------_oGND
TL/F/9755-1

5-69

I

~

N

C")
~

.....

en
c
......
~

N

C")
~
~

en
c

r-------------------------------------------------------------------------------------------,
Applications
EXTERNAL RESISTOR CALCULATION

After solving for Rext' the magnitude of the source collector
current (Ics) is determined from Equation 3.

A typical magnetic-memory word drive requirement is shown
in Figure 11. A source-output transistor of one OS75325
delivers load current (Id. The sink-output transistor of another OS75325 sinks this current.

Ics ;:::; 0.94 IL

As an example, let VCC2(Min) = 20V and VL = 3V while IL
of 500 mA flows. Using Equation 1:

The value of the external pull-up resistor (Rext) for a particular memory application may be determined using the following equation:

R

16 [VCC2(Min) - Vs - 2.2]
ext - IL -1.6 [VCC2(Min) - Vs - 2.9]

R

=

ext

(1 )

16 (20 - 3 - 2.2)
= 0.5 kn
500 - 1.6 (20 - 3 - 2.9)

and from Equation 2:

where: Rext is in kn,

PRext ;:::;

VCC2(Min) is the lowest expected value of VCC2 in volts, Vs
is the source output voltage in volts with respect to ground,
IL is in mAo

500
16
[20 -

3 - 2] ;:::; 470 mW

The amount of the memory system current source (Ics)
from Equation 3 is:
Ics;:::; 0.94 (500) ;:::; 470 mA

The power dissipated in resistor Rext during the load current
pulse duration is calculated using Equation 2.
IL
PRext ;:::; 16 [VCC2(Min) - Vs - 2]

(3)

where: Ics is in mAo

In this example the regulated source-output transistor base
current through the external pull-up resistor (RexV and the
source gate is approximately 30 mAo This current and Ics
comprise IL.

(2)

where: PRext is in mW.

ONE

OS55325/
OS75325
SOURCE

1
Vs

_1
ONE

Y OR Z

OS55325/
OS75325
SINK

GNO

------"
TL/F/9755-15

Note 1: For clarity, partial logic diagrams of two DS55325s are shown.
Note 2: Source and sink shown are in different packages.

FIGURE 11. Typical Application Data

5-70

c

(J)

.......

J?'A National
~ Semiconductor

U1

W

.....
Q)

0575361 Dual TTL-ta-MeS Driver
General Description

Features

The OS75361 is a monolithic integrated dual TTL-to-MOS
driver interface circuit. The device accepts standard TTL
input signals and provides high-current and high-voltage
output levels for driving MOS circuits. It is used to drive
address, control, and timing inputs for several types of MOS
RAMs including the 1103 and MM5270 and MM5280.

•
•
•
•

The OS75361 operates from standard TTL 5V supplies and
the MOS Vss supply in many applications. The device has
been optimized for operation with VCC2 supply voltage from
16V to 20V; however, it is designed for use over a much
wider range of VCC2.

•
•
•
•
•

Capable of driving high-capacitance loads
Compatible with many popular MOS RAMs
VCC2 supply voltage variable over wide range to 24V
Diode-clamped inputs
TTL compatible
Operates from standard bipolar and MOS supplies
High-speed switching
Transient overdrive minimizes power dissipation
Low standby power dissipation

Schematic and Connection Diagrams
Dual-In-Line Package
(1/2 shown)

VZ

V1

Vee,

"D~:::: {...._______...

INPUT A

ENABLE E

o-----_-+__.....

~

o-.........._--+~

....Je--.....-+.....-o OUTPUT Y

__-'
Z

T~~I~~~~

-------4~__()

{....
- - - - . . - -. . .- - - - - -. . .

A1

AZ

GND
TLlF/7557-1

Top View
GND

Order Number DS75361J or DS75361N
See NS Package Number J08A or N08E

TL/F17557-3

5-71

4

Absolute Maximum Ratings

(Note 1)

If Military 1Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Supply Voltage Range of VCC1 (Note 1)
Supply Voltage Range of VCC2

60 Seconds: J Package

-0.5 to 7V
5.5V

Inter-Input Voltage (Note 4)

5.5V

200·C

10 Seconds: N or P Package
'Derate molded package 8.2 mWI' above about 25'C.

Operating Conditions
Min
4.75
4.75
0

-65·C to + 150·C
Supply Voltage (VCC1)
Supply Voltage (VCC2)
Operating Temperature (TA)

Maximum Power Dissipation* at 25·C
Molded Package

300·C

Lead Temperature 1/16 inch from Case for

-0.5Vt025V

Input Voltage
Storage Temperature Range

Lead Temperature 1/16 inch from Case for

1022 mW

Max
5.25
24
+70

Units
V
V
·C

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Conditions

Min

Typ

VIH

High-Level Input Voltage

VIL

Low-Level Input Voltage

VI

Input Clamp Voltage

11= -12 mA

VOH

High-Level Output Voltage

VIL = 0.8V, IOH = -50/LA

VCC2 - 1

VCC2 - 0.7

VIL = 0.8V, IOH = -10 mA

VCC2 - 2.3

VCC2 - 1.8

VOL

Low-Level Output Voltage

0.5

V

IIH

High-Level Input Current

ICC1(L)

Supply Current from VCC1, Both
Outputs Low

ICC2(L)

Supply Current from VCC2, Both
Outputs Low

ICC2(S)

Supply Current from VCC2,
Stand-by Condition

V

0.25

VI = 5.5V

Supply Current from VCC2, Both
Outputs High

V

V

VI = OV, IOH = 20 mA

ICC2(H)

V

VCC2 = 15V to 24V, VIH = 2V,
IOL = 40 mA

Input Current at Maximum
Input Voltage

Supply Current from VCC1, Both
Outputs High

V

-1.5

0.3

Output Clamp Voltage

ICC1(H)

V
0.8

0.15

II

Low-Level Input Current

Units

VIH = 2V, IOL = 10 mA

Vo

IlL

Max

2

VI = 2.4V

VI = O.4V

VCC2 + 1.5

V

1

mA

A Inputs

40

/LA

E Input

80

/LA

A Inputs

-1

-1.6

mA

E Input

-2

-3.2

mA

2

4

mA

0.5

mA

16

24

mA

7

11

mA

0.5

mA

VCC1 = 5.25V,
All Inputs at OV,

VCC2 = 24V,
No Load

VCC1 = 5.25V,
All Inputs at 5V,

VCC2 = 24V,
No Load

VCC1 = OV,
All Inputs at 5V,

VCC2 = 24V,
No Load

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the O'C to
VCC2 = 20V.

+ 70'C range for the OS75361. All typical values are for T A = 25'C and VCCl = 5Vand

Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: This rating applies between the A input of either driver and the common E input.

5-72

Switching Characteristics VCC1
Symbol
tDLH

c
en
......

= 5V, VCC2 = 20V, TA = 25°C

Parameter

Conditions

Min

Delay Time, Low-to-High Level Output

tDHL

Delay Time, High-to-Low Level Output

tTLH

Transition Time, Low-to-High Level Output

CL = 390 pF,
RD = 10n

tTHL

Transition Time, High-to-Low Level Output

(Figure 1)

tPLH

Propagation Delay Time, Low-to-High Level Output

10

tpHL

Propagation Delay Time, High-to-Low Level Output

10

Typ

Max

Units

11

20

ns

10

18

ns

25

40

ns

21

35

ns

36

55

ns

31

47

ns

en
w
0)

.....

AC Test Circuit and Switching Time Waveforms
5V

INPUT

I

2DV

1.1 I

(

, VCCI

II

PULSE
GENERATOR
(NOTE 11

I

Vccz

- '- I .....LI
RD

..;.

......

J

I

L
)
2.4V

r'

-*GNO

I

$.10ns-

.J

OUTPUT

CL
J(NOTE21

TL/F17557-4

I

1---$.10ns

3V----~--~~-------9~0~u.

1.90%

INPUT

V

OV~

/I

I.SV

I.SV

1-------O.Slls-----iI\""',;.O%....._ __

--

tCHL - -

VOH---~~"\I

--tTHL

Vccz -3V\
OUTPUT

~

'''"-

I--/

~,
Vccz-

~

3V

VOL _________.....::.;2V:....l\.__________--' 2V
TLlF17557-5
Note 1: The pulse generator has the following characteristics: PRR

=

1 MHz, ZOUT

Note 2: CL includes probe and jig capacitance.

FIGURE 1. Switching Times, Each Driver

5-73

=

50n.

•

Typical Performance Characteristics
High-Level Output Voltage vs
Output Curre_nr'TtTmlll'--r-r

Low-Level Output Voltage vs
Output Current

0.5

~

~ -0.5

~
!i:

...

~~

-1.0

l;
~ -1.5

ill

;::

~

-2.0
-2.5

;;:
-3.0 L...L...LJJ.WIL.....L...I.WllII....L...LJJ.J.WL.....L..L
-0.01
-0.1
-1
-10
-100

Vcc , - SV
VCC2 - 20V
V, - 2V
+---t--t~9

0.4

0.2

I--Wz:....+--+--+---l

;::

0.1

p<'--+--+--+--+-~

~

o

aoo

~

600 I---+-+-++H-+l'l-.~-It-+-II'I++H

is
cc
....
~

500

w .. .,s.

35

~E
>- ..

30

e'"

25

z>

ZO

g~
o~

~:i:

400
300

~~
eX

~~~$$mt~~~nnm
I"!

~~

~~

0.2

0.4

30

~;

20

~~
~~
",,,,

15

.... 0
0 ..

10

~;;:

~

...-

CL - ZOO pF

.....

30

o

10

ZO

C~ - SOIPF_ r-- r--

~~
z>

e'"

Z5

o

I I

>- ..
20

~~

15

~6

10

~~

o
40

50

60

70

80

o

z>

ZO

!i~

15

""~
....
0

10

g~

0 ..

ZO

I 1

r--

c~ -sJ pF

f--

I

I I
I I
30

40

50

60

70

ao

AMBIENT TEMPERATURE (OCI

Propagation Delay Time,
Low-to-High Level Output
vs Load CapaCitance
60

e'"

......
>- ..

10

CL -200pF

I

Vcc , - 5V
VCC2 - ZOV
Ro -IOu
(FIGURE 11

;;:

30

2.5

CL - 390 pF

... 0

VCC' = SV
35 >- RD = 1011
30 >- TA - Z5'C
(FIGURE II
ZS

... 0

Vcc, - SV
Ro -IOn
TA - 25°C
(FIGURE 11

f~
o

!l;

0'"

CL =390PFY

.......t" J
V ..- C~O~
,/V

0'"

e~:
...

35

Propagation Delay Time,
High-to-Low Level Output
vs VCC2 Supply Voltage
~~

~

1.5

40

l

40

....,., ACL-200p~

0.5

Propagation Delay Time,
High-to-Low Level Output
vs Ambient Temperature

AMBIENT TEMPERATURE (OCI

CL - 390pF_
I--

25

I

o

INPUT VOLTAGE (VI

Vcc,' SV
10
VCC2 - ZOV
r- Ro =IOn
(FIGURE 11

10

40
35

o

100

w ..

Propagation Delay Time,
Low-to-High Level Output
vs VCC2 Supply Voltage
:ill;
......

80

_ Vcc , - SV
VCC2 - 20V
NO LOAD
-TA -2SoC

~

CL - 390 pF

FREQUENCY (MHz!

.... ]

60

15

o

O~~~~~~~~~~

0.1

40

40

-::

900

200
100

20

12

Propagation Delay Time,
Low-to-High Level Output
vs Ambient Temperature

1000 ,...--,-..,....i-r-I"TT'I":-""""'TT"""""'TTTW

~ 700

~

.'"

'\

18

LOW·LEVEL OUTPUT CURRENT (mAl

Total Dissipation (Both Drivers)
vs Frequency

~

...
~
>

0'---"--"---"---"----'

HIGH·LEVEL OUTPUT CURRENT (mAl

!

20

~

0.3

...~

Voltage Transfer
Characteristics

24

,/

f~
;;:

o
12

18

ZO

Z4

O~~--~~~~--~~

o

12

SUPPLY VOLTAGE (VI

16

20

24

o

100

200

300

400

500

600

LOAD CAPACITANCE (pFI

SUPPLY VOLTAGE (VI

Propagation Delay Time,
High-to-Low Level Output
vs Load Capacitance
60

""-~--'--';---r--.--,

50

~:C: ;s~~V t---+--r--t-:;,...,

vcc ,

- 5V

40 ~(~FI~G~UR~E~I~I__~_~-+~~

20 r--t~~--r--+--+--1
10

r--+---t---r--+--+--1

O~~--~~--~~~~

o

100

200

300

400

500

600

LOAD CAPACITANCE (pFI

TL/F17557-2

5-74

c
en
.....
U1

Typical Applications
The fast switching speeds of this device may produce undesirable output transient overshoot because of load or wiring
inductance. A small series damping resistor may be used to
reduce or eliminate this output transient overshoot. The
5V

-+

16.7V

ee1
A .-

V

OS75361

--. E

)

0575361
(5 PACKAG ES)

(2 PACKAGES)

[

5V

XeCl

TTL
INPUTS

19.5V

optimum value of the damping resistor to use depends on
the specific load characteristics and switching speed. A typical value would be between 10n and 30n (Figure 3).

TTL
INPUTS

TL/F/7557-7

Note: AD ::::: 1on to 30n (Optional).

GNO

FIGURE 3. Use of Damping
Resistor to Reduce or Eliminate
Output Transient Overshoot In
Certain 0575361 Applications
TLIF/7557-6

FIGURE 2_lnterconnectlon of 0575361 Devices with 1103 RAM

Thermal Information
The OS75361 is so designed that Ps is a negligible portion
of PT in most applications. Except at very high frequencies,
tL + tH ~ tLH + tHL so that Ps can be neglected. The total
dissipation curve for no load demonstrates this point. The
power dissipation contributions from both channels are then
added together to obtain total device power.

POWER DISSIPATION PRECAUTIONS
Significant power may be dissipated in the OS75361 driver
when charging and discharging high-capacitance loads over
a wide voltage range at high frequencies. The total dissipation curve shows the power dissipated in a typical OS75361
as a function of load capacitance and frequency. Average
power dissipated by this driver can be broken into three
components:

The following example illustrates this power calculation
technique. Assume both channels are operating identically
with C = 200 pF, f = 2 MHz, VCC1 = 5V, VCC2 = 20V, and
duty cycle = 60% outputs high (tH/T = 0.6). Also, assume
VOH = 19.3V, VOL = 0.1V, Ps is negligible, and that the
current from VCC2 is negligible when the output is high.

PT(AV) = POC(AV) + PC(AV) + PS(AV)
where POC(AV) is the steady-state power dissipation with the
output high or low, PC(AV) is the power level during charging
or discharging of the load capacitance, and PS(AV) is the
power dissipation during switching between the low and
high levels. None of these include energy transferred to the
load and a" are averaged over a full cycle.

On a per-channel basis using data sheet values:
POC(AV) = [ (5V) (

The power components per driver channel are:
POC(AV) =

PLtL

+

T

[(5V)

PHtH

2

;A)

C

62mA)

+

+

(20V) (

0

;A) ] (0.6)

C

(20V)

;A) ] (0.4)

POC(AV) = 47 mW per channel
PC(AV) ;:::: (200 pF) (19.2V)2 (2 MHz)

PC(AV) ;:::: C Vc 2 f

PC(AV) ;:::: 148 mW per channel.

PLHtLH + PHLtHL
P
S(AV) =
T

For the total device dissipation of the

+

two channels:

where the times are defined in Figure 4.

PT(AV) ;:::: 2 (47

148)

PL, PH, PLH, and PHL are the respective instantaneous levels of power dissipation and C is load capacitance.

PT(AV) ;:::: 390 mW typical for total package.

I------T = 1/1-----1
TL/F/7557-8

FIGURE 4. Output Voltage Waveform

5-75

+

eN

0)
.....

II)

CD

~ ~National
~ ~ Semiconductor

PRELIMINARY

0575365 Quad TTL-to-MOS Driver
•
•
•
•

General Description
The OS75365 is a quad monolithic integrated TTL-to-MOS
driver and interface circuit that accepts standard TTL input
signals and provides high-current and high-voltage output
levels suitable for driving MOS circuits. It is used to drive
address, control, and timing inputs for several types of MOS
RAMs including the 1103.

•
•

The OS75365 operates from the TTL 5V supply and the
MOS Vss and Vss supplies in many applications. This device has been optimized for operation with VCC2 supply voltage from 16V to 20V, and with nominal VCC3 supply voltage
from 3V to 4V higher than VCC2. However, it is designed so
as to be usable over a much wider range of VCC2 and VCC3.
In some applications the VCC3 power supply can be eliminated by connecting the VCC3 to the VCC2 pin.

•
•
•
•
•
•

Capable of driving high-capacitance loads
Compatible with many popular MOS RAMs
Interchangeable with Intel 3207
VCC2 supply voltage variable over side range to 24V
maximum
VCC3 supply voltage pin available
VCC3 pin can be connected to VCC2 pin in some
applications
TTL compatible diode-clamped inputs
Operates from standard bipolar and MOS supply
voltages
Two common enable inputs per gate-pair
High-speed switching
Transient overdrive minimizes power dissipation
Low standby power dissipation

Features
• Quad positive-logic NAND TTL-to-MOS driver
• Versatile interface circuit for use between TTL and
high-current, high-voltage systems

Schematic and Connection Diagrams
Dual-ln-L1ne Package
Vcc•

TO OTHER
DRIVERS

{+-______

2E2

13

2EI

Al

Vl

Vee3

12

+-_ _--.

INPUT A 0 - - - - - - 4............--4

. . . . . .f-e.............._O~UTPUT

ENABLE EI 0 - - -...-+..............
ENABLE E2

Vee.

o-.....--t--t-Ile---'

VI

AI

lEI

IE2

A2

V2

GND

Tl/F/7560-2

Top View
Positive Logic: Y = A-E1-E2
TO OTHER {
DRIVERS

Order Number DS75365J or DS75365N
See NS Package Number J16A or N16A
~~.....-~-----f-e-----~~-oGND

ONE OF 4 SHOWN

TL/F17560-1

5-76

c

Absolute Maximum Ratings (Note 1)

en
.......

Operating Conditions

If MilitaryI Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.

Supply Voltage (VCC1)
Supply Voltage (VCC2)
Supply Voltage (VCC3)
Voltage Difference Between
Supply Voltages: VCC3-VCC2
Operating Ambient Temperature
Range (TA)

-0.5Vto 7V
Supply Voltage Range of VCCl
-0.5V to 25V
Supply Voltage Range of VCC2
-0.5Vto 30V
Supply Voltage Range of VCC3
nput Voltage
5.5V
Inter-Input Voltage (Note 4)
5.5V
Storage Temperature Range
- 65°C to + 150°C
Maximum Power Dissipation· at 25°C
Cavity Package
1509mW
Molded Package
1476mW
300°C
Lead Temperature (Soldering, 10 sec)
• Derate cavity package 10.1 mW /'C above 25'C; derate molded package
11.8 mW/,C above 25'C.

Min
4.75
4.75

VCC2
0

Max
5.25
24
28
10

Units
V
V
V
V

0

70

°C

U1

(,,)
C')

U1

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

VIH

High-Level Input Voltage

VIL

Low-Level Input Voltage

Conditions

Min

Typ

Max

2

Units

V
V

-1.5

V

VI

Input Clamp Voltage

VOH

High-Level Output Voltage VCC3 = VCC2 + 3V, VIL = 0.8V, IOH = - 100 p.A VCC2 - 0.3 VCC2 - 0.1

V

VCC2 - 1.2 VCC2 - 0.9

V

VCC3 = VCC2, VIL = 0.8V, IOH = - 50 p.A

VCC2 - 1 VCC2 - 0.7

V

VCC3 = VCC2, VIL = 0.8V, IOH = - 10 mA

VCC2 - 2.3 VCC2- 1.8

11=

-12mA

0.8

VCC3 = VCC2 + 3V, VIL = 0.8V, IOH = - 10 mA

VOL

0.3

0.25

0.5

V

VCC2 + 1.5

V

1

mA

A Inputs

40

p.A

E1 and E2 Inputs

80

p.A

VCC3 = 15V to 28V, VIH = 2V, IOL = 40 mA
Vo

Output Clamp Voltage

II

Input Current at Maximum VI = 5.5V
Input Voltage

IIH

High-Level Input Current

VI = OV, IOH = 20 mA

VI = 2.4V

V

0.15

Low-Level Output Voltage VIH = 2V,IOL = 10 mA

V

A Inputs

-1

-1.6

mA

E1 and E2 Inputs

-2

-3.2

mA

4

8

mA

-2.2

+0.25

mA

-2.2

-3.2

mA

ICC3(H)

Supply Current from VCC3,
All Outputs High

2.2

3.5

mA

ICC1(L)

Supply Current from VCC1, VCCl = 5.25V, VCC2 = 24V
All Outputs Low
VCC3 = 28V, All Inputs at 5V, No Load

31

47

mA

ICC2(L)

Supply Current from VCC2,
All Outputs Low

3

mA

ICC3(L)

Supply Current from VCC3,
All Outputs Low

25

mA

0.25

mA

0.5

mA

IlL

Low-Level Input Current

VI = O.4V

ICC1(H) Supply Current from VCC1, VCCl = 5.25V, VCC2 = 24V
All Outputs High
VCC3 = 28V, All Inputs at OV, No Load
ICC2(H)

Supply Current from VCC2,
All Outputs High

16

ICC2(H) Supply Current from VCC2, VCCl = 5.25V, VCC2 = 24V
All Outputs High
VCC3 = 24V, All Inputs at OV, No Load
ICC3(H)

Supply Current from VCC3,
All Outputs High
5-77

•

Electrical Characteristics (Notes 2,3) (Continued)
Symbol
ICC2(S)

ICC3(S)

Parameter

Conditions

Supply Current from VCC2,

VCC1

Stand-By Condition

VCC3

Min

Typ

= OV, VCC2 = 24V
= 24V, All Inputs at 5V, No Load

Supply Current from VCC3,
Stand-By Condition

Max

Units

0.25

rnA

0.5

rnA

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified, min/max limits apply across the O'C to
VCC2 = 20V and VCC3 = 24V.

+ 70'C range for the D575365. All typical values are for TA = 25'C and VecI = 5Vand

Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: This rating applies between any two inputs of anyone of the gates.

Switching Characteristics VCC1 = 5V, VCC2 = 20V, VCC3 = 24V, TA = 25°C
Symbol

Parameter

Conditions

tOLH

Delay Time, Low-to-High Level Output

CL

tOHL

Delay Time, High-to-Low Level Output

Ro

tTLH

Min

= 200 pF
= 240

Typ

Max

Units

11

20

ns

10

18

ns

Transition Time, Low-to-High Level Output

20

33

ns

tTHL

Transition Time, High-to-Low Level Output

20

33

ns

tpLH

Propagation Delay Time, Low-to-High Level Output

10

31

48

ns

tpHL

Propagation Delay Time, High-to-Low Level Output

10

30

46

ns

(Figure 1)

AC Test Circuit and Switching Time Waveforms
INPUT

I

PULSE
GENERATOR
(NOTE 1)

5V

24V 20V

JV~c-;vL;vL~
II

I

•

I

L

2.4V

~

_I

.r'
GNO

-~-

I
I

.J

I

I

:::;10ns3V

1.90%

. . . . . . .1..

INPUT

Ro

OUTPUT

-:::;10nl

90%
1.5V

/1.5V

OV~

0.5111

CL

-tpHL-

IINOlE2I
TL/F/7560-3

--

--ITHL

V~'-2V\

OUTPUT
2V

VOL

10%

ro-tpLH-

tOHLVOH

\

IOLH-

V'

r--tTLH
~

V~,-lV

2V
TL/F17560-4

Note 1: The pulse generator has the following characteristics: PRR

=

1

Note 2: CL includes probe and jig capacitance.

FIGURE 1. Switching Times, Each Driver

5-78

MHz, ZOUT = 580.

c
en
.....

Typical Performance Characteristics
High-Level Output Voltage vs
Output Current

II ~

~,

>
~

-0.5

~>

...

o ~~~-TTn~~~-rTn

II

~ -0.5 b-+-ttit--t-+tlf-H1fft--t-t+I

~>

~

...

~ -1.5

~

-1.0 t-+-ttit-.,.,d-tf!-H1fft--t-t+I

§ -2.0

Vcc" SV
Vcc.· 20V
VCC3' 24V
V, ·0.8V

-2.5

:;:

-J.O
-0.01

~
-I

-10

-100

0.4

VCC3 ' 24V-t--t--+-~...
V.-2V

~

O.J t--I---I---::>'!l~--1I---i

-3.0 L-,;,................................'--J....L.LJL.....J...J.J.JI
-0.01
-0.1
-1
-10
-100

H1GH·LEVEL OUTPUT CURRENT (mAl

en

U1

~::::~V

~

0.2 t--~~I---I---I---i

~

0.1 1iL--1--1----:1--I1----I

~

-2.5

:;:

-0.1

..

...

~ -1.5

E-Z.O

~-...--,....--,....--,....---,

~

::I

::I

0.5

~

>

~'+70·C

-1.0

U1
CAl

Low-Level Output Voltage
Output Current

High-Level Output Voltage vs
Output Current

20

40

60

80

100

LOW-LEVEL OUTPUT CURRENT (mAl

HIGH·LEVEL OUTPUT CURRENT (mAl

TLIF/7560-5

24

Voltage Transfer
Characteristics

r---,,----,,---,---r--,

1000

Propagation Delay Time,
Low-to-Hlgh Level Output
vsAm b lent Temperature

Total Dissipation (All Four
Drivers) vs Frequency

-

CL ' 200 pF
:

16

1--1-~1----I~-t--1

~

IZ

1----I---:-t---4~_+-_4

...
~

vcc ,

~::; :~v-+---+f--+---i

::I

4

= 5V
Vea ·20V
VCCl = 24V
RD' 24!Z
(FIGURE 11

:
VCCl " 24V
TA• 25°C - t - - - t i - + - - t
NO LOAD
0.5

1.5
INPUT VOLTAGE (VI

2.5

0.1

Propagation Delay Time,
Hlgh-to-Low Level Output
vs Ambient Temperature

0.2

0.4 0.7 1
FREQUENCY (MHz)

710

10

~~
~~
c ...

Propagation Delay Time,
Low-to-Hlgh Level Output vs
VCC2 Supply Voltage

21:;
c .....
;:;:
c(c

15

~6

10

~;
.....

f - - f-CL 200 plF
ICL =

20

~opJ __ ' - - -

,.

~~

10

20

3D

40

60

60

70 80

AMBIENT TEMPERATURE ("CI

---

I

12
16
20
SUPPLY VOLTAGE (VI

r--~-.--,-.--r~......,

~~

50

~~
..........

40

~1:;

JO

~~
..........
......

.....

~i

20

~;

10t-+--t--+--1--+-+--+--i

... ~

80

-

__ i.--fo-CL"IOOpF-

cc,

VCCl " VCC2 +4V
RD " 2411
TA =25"c
(FIGURE 11
12
1&
20
SUPPLY VOLTAGE (VI

24

60

......
0

7D

24

Propagation Delay Time,
Hlgh-to-Low Level Output vs
Load Capacitance

1!

:i~

60

/'" v I·sv I

I

VCC' = SV
VCCl • Vcc. + 4V
AD =25U
TA"25"C
(FIGURE 11

Propagation Delay Time,
Low-to-Hlgh Level Output vs
Load Capacitance
60

SO

CL=200~ ~

/V'

~ I""CL"'OOpF-

Vcc , = SV
VC C2 = 20V
VCCl = 24V
Ro -241!
(FIGURE 11

:;:

40

Propagation Delay Time,
High-to-Low Level Output
vs VCC2 Supply Voltage

-

~

CL ' 200pF

25

JO

40

J5
Jo

20

AMBIENT TEMPERATURE ( CI

40

""
~t~
......

CLI. 50!F

' - - f--

r-~~~-II--+--t--+---t

50 100 150 200 250 300 J50 400

~~~:: ~~~ +--t--+--I--+--i

40

TA • 25°C
(FIGURE 11
I

30

~~

20

~~

~

:;:

VCCI = 5V

50

~~

f

r-~~--r--'-.-'--r-'

AD'

10Ui::::':-!5=-t::~4'--1

r-.....--r=-+-t--+--+--+-~

10 1--I-+-+---I--+--+--+-_4

50 100 150 200 250 JOO 350 400
LOAD CAPACITANCE (pFI

LOAD CAPACITANCE (pFI

TLIF/7560-6

5-79

•

I

5V

19.5V

16V

5V

TTl
INPUTS

1

TL/F/7560-7

FIGURE 2. Interconnection of DS75365 Devices
with 1103-Type Silicon-Gate MOS RAM

The power components per driver channel are:

Typical Applications
The fast switching speeds of this device may produce undesirable output transient overshoot because of load or wiring
inductance. A small series damping resistor may be used to
reduce or eliminate this output transient overshoot. The optimum value of the damping resistor depends on the specific
load characteristics and switching speed. A typical value
would be between 10n and 30n (Figure 3 ).

r

Ds7S3&5i

r

MOs -,

~!o..LSt:1
=t==L-"'Ivv'Tlc~ 1- I
L __ ..J L_-=.J
Note: RD "" 100 to 300 (Optional)
TL/F17560-8

FIGURE 3. Use of Damping Resistor to Reduce or
Eliminate Output Transient Overshoot in Certain
DS75365 Applications

Thermal Information
POWER DISSIPATION PRECAUTIONS
Significant power may be dissipated in the OS75365 driver
when charging and discharging high-capacitance loads over
a wide voltage range at high frequencies. The total dissipation curve shows the power dissipated in a typical OS75365
as a function of load capacitance and frequency. Average
power dissipation by this driver can be broken into three
components:

PT(AV) = POC(AV) + PC(AV) + PS(AV)
where POC(AV) is the steady-state power dissipation with the
output high or low, PC(AV) is the power level during charging
or discharging of the load capacitance, and PS(AV) is the
power dissipation during switching between the low and
high levels. None of these include energy transferred to the
load and all are averaged over a full cycle.

POC(AV)
PC(AV)

e!

PS(AV) =

PLtL
=

+ PHtH

C vc2f
PLHtLH

T

+ PHLtHL
T

where the times are as defined in Figure 4.
PL, PH, PLH, and PHL are the respective instantaneous levels of power dissipation and C is load capacitance.
The OS75365 is so designed that Ps is a negligible portion
of PT in most applications. Except at very high frequencies,
tL + tH » tLH + tHL so that Ps can be neglected. The total
dissipation curve for no load demonstrates this point. The
power dissipation contributions from all four channels are
then added together to obtain total device power.
The following example illustrates this power calculation
technique. Assume all four channels are operating identically with C = 100 pF, f = 2 MHz, VCC1 = 5V, VCC2 = 20V,
VCC3 = 24V and duty cycle = 60% outputs high
(tH/T = 0.6). Also, assume VOH = 20V, VOL = O.W, Ps is
negligible, and that the current from VCC2 is negligible when
the output is low.
On a per-channel basis using data sheet values:
4
POC(AV) = [(5V)( ;A) + (20V) (-2.: mA) + (24V)
(2.24mA)] (0.6)
(20V) (

0

;A)

+ [(5V)

+ (24V)

(31 ;A)

+

mA
(16 4 ) ] (0.4)

POC(AV) = 58 mW per channel
PC(AV) ~ (100 pF) (19.9V)2 (2 MHz)
PC(AV) ~ 79 mW per channel.
For the total device dissipation of the four channels:
PT(AV) e! 4 (58 + 79)
PT(AV) ~ 548 mW typical for total package.

I - - - - - - T = t/l----~
TL/F17560-9

FIGURE 4. Output Voltage Waveform

5-80

~National

~ Semiconductor
DS9643/ J.tA9643
Dual TTL to MOS/CCD Driver
General Description

Features

The OS9643/1lA9643 is a dual positive logic "AND" TIL-toMOS driver. The OS96431 IlA9643 is a functional replacement for the SN75322 with one important exception: the
two external PNP transistors are no longer needed for operation. The OS96431 IlA9643 is also a functional replacement for the 75363 with the important exception that the
VCC3 supply is not needed. The lead connections normally
used for the external PNP transistors are purposely not internally connected to the OS96431 IlA9643.

• Satisfies CCO memory and delay line requirements
• Dual positive logic TIL to MOS driver
• Operates from standard bipolar and MOS supply voltages
• High speed switching
• TIL and OTL compatible inputs
• Separate drivers address inputs with common strobe
• VOH and VOL compatible with popular MOS RAMs
• Does not require external PNP transistors or VCC3
• VOH minimum is VCC2 - O.5V

Connection Diagram

Truth Table

8-Lead DIP

Input

Enable

L

L

Output

L

L

H

L

H

L

L

H

H

H

TL/F/9646-1

Top View
Order Number DS9643N/IlA9643TC
See NS Package Number N08E

•
5-81

Absolute Maximum Ratings

Recommended Operating
Conditions

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Storage Temperature Range

Supply Voltage (VCC1)

-65°C to + 150°C

Operating Temperature Range
Lead Temperature
Molded DIP (soldering, 10 sec.)
Maximum Power Dissipation" at 25°C
Molded Package

Supply Voltage (VCC2)
Operating Temperature (TA)

O°Cto +70°C

Min
4.75

Typ
5.0

Max
5.25

Units
V

11.4

12

12.6

V

0

25

70

°C

265°C
930mW

Supply Voltage
-0.5V to + 7.0V
Range of VCC1
-0.5Vto +15V
Range of VCC2
Input Voltage
5.5V
·Derate molded DIP package 7.S mW/'C above 2S'C.

Electrical Characteristics
over recommended operating temperatures and VCC1, VCC2 ranges, unless otherwise specified (Notes 2 and 3)
Symbol

VIH

Parameter

Conditions

Input Voltage HIGH

Min

Typ

Max

2.0

V

VIL

Input Voltage LOW

VOH

Output Voltage HIGH

IOH ~ - 400 p,A

0.8

VOL

Output Voltage LOW

IOL = 10 rnA

0.4

0.5

IOL = 1.0 rnA

0.2

0.3

VCC2 - 0.5

II

Input Current at Maximum
Input Voltage

VCC1 = 5.25V, VCC2 = 11.4V
VI = 5.25V

IIH

Input Current HIGH

VI = 2.4V

IlL

ICC1(L)
ICC2(L)

Input Current LOW

V
V

VCC2 - 0.2

0.1

A Inputs

40

E Inputs

80

A Inputs

-0.5

E Inputs

-1.0

V

rnA
p,A

rnA

Supply Current from VCC1
All Outputs LOW

VCC1 = 5.25V,
VCC2 = 12.6V

15

19

rnA

Supply Current from VCC2

VCC1 = 5.25V,
VCC2 = 12.6V

5.5

9.5

rnA

VCC1 = 5.25V,
VCC2 = 12.6V

9.0

13

rnA

All Outputs LOW
ICC1(H)

VI = O.4V

Units

Supply Current from VCC1

All Outputs HIGH

VCC1 = 5.25V,
5.5
9.5
rnA
VCC2 = 12.6V
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified MinIMax limits apply across the O'C to + 70'C range for the 059643. All typicals are given for VCCl = SV, VCC2 = 12Vand
TA = 2S'C.
Note 3: All currents into the device pins are positive; all currents out of the device pins are negative. All voltages are reference to ground unless otherwise
specified.

ICC2(H)

Supply Current from VCC2

All Outputs HIGH

5-82

Switching Characteristics VCC1

= 5.0V. VCC2 = 12V. TA = 25°C

Parameter

Symbol

Conditions

tOLH

OelayTime

CL = 300 pF

tOHL

OelayTime

tTLH

Rise Time

tTHL

Fall Time

tTLH

Rise Time

tTHL

Fall Time

tPLHA_
tPLHB
tPHLA_
tpHLB

Skew between Outputs
AandB

a

RSERIES =

CL = 300 pF

CL = 300 pF

RSERIES = 10n

Min

Typ

Max

Units

5.0

9.0

17

ns

5.0

9.0

17

ns

6.0

11

17

ns

6.0

11

17

ns

8.0

14

20

ns

8.0

14

20

ns

0.5

VCC2

VCC1

1

I

[0
~

IN

Rl
3k.o.

~

I ,~~..L
J~

[0

Cl

R3

II

~1k.o.

r~

,...."

t" .......

.~ R2

: >1.5 k.o.

05

~

J .......

~01 ,~

E

~ ~D12

[0

~'D7

-~

~03

1\

~~

) .......

\0 R5
~ 5k.o.

~~DI3

,!
~
) .......

..

.

Rll
600.0.

D2~ ~

~1

~OUT

1~ 'D9'-~
~

06

CCROSSUNDER

~10~~

RI3
10 k.o.

RI2
150.0.

R4
~ 500.0.

.R6
1.5 k.o.

~

=-

~,

R9
10k.o.

~14

~'l

-

ns

R7
5k.o.

~D8

012 '~

R8

~Dll

~ 4k.o.

I

~o

011

~~DI4

,I- RIO
: ~ 1.5 k.o.

II

T

GND

TL/F/9646-2

FIGURE 1. Equivalent Circuit (% of Circuit)

5-83

< 10ns

TL/F/9646-3

Note: The pulse generator has the following
characteristics:
PRR

=

1.0 MHz, Zo

'-~---VON

vo------I~~

= son

CL includes strobe and jig capacitance.

~-----+---~-~----------VOL
TLIF/9646-4

FIGURE 2. AC Test Circuit and Waveforms

5-84

»
z

.

National Semiconductor
Application Note 76
B. Siegel
M.Scott

Applying Modern Clock
Drivers to MOS Memories

.......

0')

INTRODUCTION
MOS memories present unique system and circuit challenges to the engineer since they require precise timing of
input waveforms. Since these inputs present large capacitive loads to drive circuits. it is often that timing problems
are not discovered until an entire system is constructed.
This paper covers the practical aspects of using modern
clock drivers in MOS memory systems. Information includes
selection of packages and heat sinks. power dissipation.
rise and fall time considerations. power supply decoupling.
system clock line ringing and crosstalk. input coupling techniques. and example calculations. Applications covered include driving various types shift registers and RAMs (Random Access Memories) using logical control as well as other techniques to assure correct non-overlap of timing waveforms.

The OS0026 is a high speed. low cost. monolithic clock driver intended for applications above one megacycle. Table II
illustrates its performance characteristics while its unique
circuit design is presented in Appendix II. The OS0056 is a
variation of the OS0026 circuit which allows the system designer to modify the output performance of the circuit. The
OS0056 can be connected (using a second power supply)
to increase the positive output voltage level and reduce the
effect of cross coupling capacitance between the clock
lines in the system. Of course the above are just examples
of the many different types that are commercially available.
Other National Semiconductor MOS interface circuits are
listed in Appendix III.
The following section will hopefully allow the design engineer to select and apply the best circuit to his particular
application while avoiding common system problems.

Although the information given is generally applicable to any
type of driver. monolithic integrated circuit drivers. the
OS0025. OS0026 and OS0056 are selected as examples
because of their low cost.

PRACTICAL ASPECTS OF USING
MOS CLOCK DRIVERS
Package and Heat Sink Selection

The OS0025 was the first monolithic clock driver. It is intended for applications up to one megacycle where low cost
is of prime concern. Table I illustrates its performance while
Appendix I describes its circuit operation. Its monolithic.
rather than hybrid or module construction. was made possible by a new high voltage gold doped process utilizing a
collector sinker to minimize VeE SAT.

Package type should be selected on power handling capability. standard size. ease of handling. availability of sockets.
ease or type of heat sinking required. reliability and cost.
Power handling capability for various packages is illustrated
in Table III. The following guidelines are recommended:

TABLE I. DS0025 Characteristics
Parameter

Conditions (V+ - V-)

= 17V

Value

Units

15

ns

toN
tOFF

CIN

tr

CL

on

30

ns

= 0.0001 ,...,F. RO = 50.11

25

ns

150

ns

= 0.0022 ,...,F. RIN =

tl
Positive Output Voltage Swing

VIN - V-

= OV.IOUT = -1 mA

Negative Output Voltage Swing

liN

= 10 mA.loUT = 1 mA

On Supply Current (V+)

liN

= 10 mA

V+ - 0.7

V

+

V

V-

1.0

17

mA

Value

Units

TABLE II. DS0026 Characteristics
Parameter

Conditions (V+ - V-)

= 17V

7.5

ns

7.5

ns

25

ns

25

ns

V+ - 0.7

V

tON

on

tOFF

CIN

= 0.001 ,...,F. RIN =

tr

RO

= 50.11. CL = 1000 pF

tl

= OV.IOUT = -1 mA

Positive Output Voltage Swing

VIN - V-

Negative Output Voltage Swing

liN

= 10 mA,lOUT = 1 mA

On Supply Current (V+)

liN

= 10 mA

5-85

V-

+ 0.5
28

V
mA

CD

......

Z•
1 may be transmitted to
4>2 (and vice versa) during the transition of 4>1 to MOS logic
"1". The spike is due to mutual capacitance between clock
lines and is, in general, aggravated by long clock lines when
numerous registers are being driven. Figure 5 illustrates the
problem.
+5V

r--

I
I
I
I

o
~ / 'H

I
I

CONCLUSION
The practical aspects of driving MOS memories with low
cost clock drivers has been discussed in detail. When the
design guide lines set forth in this paper are followed and
reasonable care is taken in circuit layout, the DS0025,
DS0026 and DS0056 provide superior performance for
most MOS input interface applications.

1 (to MOS logic "1 ") is
capacitively coupled via CM to 4>2. Obviously, the larger CM
is, the larger the spike. Prior to 4>1's transition, 01 is "OFF"
since only ,.,.A are drawn from the device.
The DS0056 connected as shown in Figure 6 will minimize
the effect of cross talk. The external resistors to the higher
power supply pull base of a 01 up to a higher level and
forward bias the collector base junction of 01. In this bias
condition the output impedance of the DS0056 is very low
and will reduce the amplitude of the spikes.

II

II

II

7. Bapat and Mrazek, "Dynamic MOS Random Access
Memory System Considerations, National Semiconductor, AN-50, August 1971.
8. Don Femling, "Using the MM5704 Keyboard Interface in
Keyboard Systems, National Semiconductor, AN-52.
II

+5V +8V +8V

·",n

II

APPENDIX I
050025 Circuit Operation
The schematic diagram of the DS0025 is shown in Figure 7.
With the TTL driver in the logic "0" state 01 is "OFF" and
02 is "ON" and the output is at approximately one VSE
below the V+ supply.

r----....-ov·

1

'1" C'N

I

..........__

-t~-o

OUTPUT

INPUT

Tl/F17322-6

FIGURE 6. Use of 050056 to Minimize
Clock Line Cross Talk

Rl
250
~--~

__----__---------ovTlIF17322-7

FIGURE 7. DS0025 Schematic (One-Half Circuit)
5-88

When the output of the TTL driver goes high, current is supplied to the base of 01, through CIN, turning it "ON." As the
collector of 01 goes negative, 02 turns "OFF." Oiode CR2
assures turn-on of 01 prior to 02's turn-off minimizing current spiking on the V+ line, as well as providing a low impedance path around 02's base emitter junction.

Equation (AI-5) may be used to predict tr as a function of Cl
and !:J.V. Values for CTC and hFE are 10 pF and 25 pF respectively. For example, if a OM7440 with peak output current of 50 mA were used to drive a DS0025 loaded with
1000 pF, rise times of:
(1000 pF

The negative voltage transition (to MaS logic "1 ") will be
quite linear since the capacitive load will force 01 into its
linear region until the load is discharged and 01 saturates.
Turn-off begins when the input current decays to zero or the
output of the TTL driver goes low. 01 turns "OFF" and 02
turns "ON" charging the load to within a VSE of the V+
supply.

+ 250 pF)(17V)

(50 mAl (20)
or 21 ns may be expected for V+ = 5.0V, VFigure 9 gives rise time for various values of Cl.
32

II~ ",15o~A

28 -T -25·C
A I
I
24

Rise Time Considerations
The logic rise time (voltage fall) of the OS0025 is primarily a
function of the ac load, Cl, the available input current and
total voltage swing. As shown in Figure 8, the input current

!

or

~.

-

20

,/V'
V+-V-Z2~
~ ...

16

a:

12
B

(

4

-12V.

-

k' ...-

lLI" ~+ -v-= 17V I-- I -

i=

w
en

v+

l..".oo ~

J I

=

VV
~~

oL--L--L-L-L-L-L---'--'--'

o
CR2

.......

200

400

600

800

1000

LOAD CAPACITANCE, CL (pF)

Q2

~

TL/F17322-9

FIGURE 9. Rise Time vs CL for the 050025
Fall Time Considerations
The MaS logic fall time (voltage rise) of the OS0025 is dictated by the load, Cl, and the output capacitance of 01. The
fall time equivalent circuit of OS0025 may be approximated
v+

_ ...... c

~L

CTCQl

~c,

T T-10 pF

-

TL/F/7322-8

hFEQz+l

--

TLlF17322-10

FIGURE 8. Rise Time Model for the 050025

FIGURE 10. Fall Time Equivalent Circuit

must charge the Miller capacitance of 01, CTC, as well as
supply sufficient base drive to 01 to discharge Cl rapidly.
By inspection:

with the circuit of Figure 10. In actual practice, the base
drive to 02 drops as the output voltage rises toward V + . A
rounding of the waveform occurs as the output voltage
reaches to within a volt of V +. The result is that equation
(AI-7) predicts conservative values of tf for the output voltage at the beginning of the voltage rise and optimistic values at the end. Figure 11 shows tf as function of Cl.

liN = 1M
liN ~ 1M

+ Is + IR1
+ Is, for 1M »

(AI-1)
IR1 and Is

»

IR1

!:J.V

Is = liN - CTC

M

(AI-2)

If the current through R2 is ignored,
Ic

=

Is hFEQ1

=

Il

+

(AI-3)

1M

160 I-f--f--1f-1f-1f-1f-i--i--i--i

where:
!:J.V

Il = Cl

M

Combining equations AI-1, AI-2, and AI-3 yields:
!:J.V

M [Cl + CTC (hFEQ1 + 1)]

= hFEQ111N

(AI-4)

100 L-l..-l..-I-I-I-L-L-L-I---I
o 200 400 600 800 1000

or

LOAD CAPACITANCE, CL (pF)

FIGURE 11.050025 Fall Time vs CL

(AI-5)
5-89

TL/F17322-11

.

CD
I'-

z

The logic "1" output impedance of the OM7440 is approximately 65.0. and the peak current (lMAX) is about 50 mA.
The pulse width for GIN = 2,200 pF is:

Assuming hFE2 is a constant of the total transition:



2.01-+-*-4'-+--+-+-+--I

/

V

8 800
fil

::>

o

CI

z

~
§

1.0 I--!--t--t"r-I--'''k-

/

20
lOUT

30

L.,...o-

......fo"'"

b-'

0

0

100 200 300 400 500 600 700 800
OUTPUT PU lSE WIDTH (ns)

TL/F17322-22

FIGURE 22. Suggested Input Capacitance vs
Output Pulse Width

40

1m A)

""

foM74S00DRIVING_
DS0026

600
~
.....~RANSISTDR_
400
WITH 50 0 HMS
200 f-- f TO +5V DRIVING DS0026-

a:
10

/
~

V

TLlF17322-21

DC Coupled Applications

FIGURE 21. Logical "1" Output Voltage
vs Source Current

The 080026 may be applied in direct coupled applications.
Figure 23 shows the device driving address or pre-charge
lines on an MM1103 RAM.
+17V
100pF

TD ADDRESS
LINES ON
MEMORY
SYSTEM

DS0026CN

l

1/2DM7400

TL/F17322-23

FIGURE 23. DC Coupled RAM Memory Address or
Precharge Driver (Positive Supply Only)
For applications requiring a dc level shift, the circuits of Figure 24 or 25 are recommended.
+S.OV

INP~~_2..,.....",,----_

-12V
TLlF17322-24

FIGURE 24. Transistor Coupled MOS Clock Driver
5-93

»
z

.

~

0')

.

~

.....

r-------------------------------------------------------------------------------~

Z



STB

DI>

CLR

0::>

MD

ENABLE

DATA
LATCH

0::>

BUFFERS

01 3

005

DI>

DI>

01 6

006

DI>

OI>

Dla

DDa

m:>
TLlF/6B24-5

6-9

:::E

N
.....
N

co

Logic Table A

D.

C
......

STB

co
C

N

.....
N

D.

Oata In (011-018): Eight-bit data input to the data latch,
which consists of eight Ootype flip-flops. Incorporating a level sensitive clock while the data latch clock input is high, the
Q output of each flip-flop follows the data input. When the
clock input returns low, the data latch stores the data input.
The clock input high overrides the clear (CIR) input data
latch reset.
Clear (CLR): When low, asynchronously resets (clears) the
data latch and the service request flip-flop. The service request flip-flop is in the non-interrupting state when reset.

Logic Tables
MO

(OS1- 0S2)

OataOut
Equals

0

0

0

TRI-STATE

1

0

0

TRI-STATE

0

1

0

OATALATCH

1

1

0

OATALATCH

0

0

1

OATALATCH

1

0

1

OATAIN

0

1

1

OATAIN

1

1

1

OATAIN

OUTPUT SIGNALS
Interrupt (lNT): Goes low (interrupting state) when either
the service request flip-flop is synchronously set by the
strobe (STB) input or the device is selected.
Oata Out (001-008): Eight-bit data output of data buffers,
which are TRI-STATE, non-inverting stages. These buffers
have a common control line that either enables the buffers
to transmit the data from the data latch outputs or disables
the buffers by placing them in the high-impedance state.

CCR ' - resets data latch to the output low state.
The data latch clock is level sensitive, a low level clock latches the data.

Logic Table B

Connection Diagram

CLR

(OS1- 0S2)

STB

Q*

INT

oRESET

0

0

0

1

1

0

0

0

1

05,-,

24

-Vee

1

0

"""-

1

0

MO-

2

23

~INT

1

1 RESET

0

0

0

01,-

3

22

~018

1

0

0

0

1

00,- 4

21

~008

012- 5

2D

~017

Oual-In-Llne Package

·Internal Service Request flip·flop.

Functional Pin Definitions

002- 6

The following describes the function of all the OP82121
OP8212M input/output pins. Some of these descriptions
reference internal circuits.

q13-

INPUT SIGNALS
Oevlce Select (OS1, OS2): When OS1 is low and OS2 is
high, the device is selected. The output buffers are enabled
and the service request flip-flop is asynchronously reset
(cleared) when the device is selected.
Mode (MO): When high (output mode), the output buffers
are enabled and the source of the data latch clock input is
the device selection logic (OS1 - OS2). When low (input
mode), the state of the output buffers is determined by the
device selection logic (OS1 - OS2) and the source of the
data latch clock input is the strobe (STB) input.
Strobe (STB): Used as data latch clock input when the
mode (MO) input is low (input mode). Also used to synchronously set the service request flip-flop, which is negative
edge triggered.

7

"'-'

OPB212!
OPB212M

19 -007

18 -DIG

003- 8

17

~OU6
~015

014- 9

16

004- 'D

15 ~005

ST8- 11

14

GNO-

12

-ern

13 -

05 2
TL/F/6824-6

Top View
Order Number OP8212J, OP8212N
orOP8212MJ
See NS Package Number J24A or N24A

6-10

C

"0

Applications in Microcomputer Systems

co

N
.....
N

Gated Buffer

.......
C

Vee

(TRI-STATE)
VCC--~------------~

"0

co

N
.....

STB

N

STB

DATA - - - - -......"-. I
BUS A..."'r"--'II' I

DUTPUT

INPUT

DATA

DATA

L--L-_ _ _ DATA
BUS

1SmAI
1l.6SV MINI

(2SOIlAl

DATA BUS

CONTROL

GATING
CONTROL

F

(0- L -+ R\
U-R-+L

----.....1

1.=--....

TL/F/6824-7

TLIF/6824-8

Interrupting Input Port
INPUT..,_ _-..
STROBE
(FROM INPUT
STB
DEVICE)

Interrupt Instruction Port

DATA
BUS

Vce

DATA
BUS

STB

RESTART
INSTRUCTION
(RST 0 -+ RST 7)

SYSTEM
INPUT

SYSTEM
RESET

.......--JfC~~~~R~~~)CKT
OR
TO CPU
INTERRUPT INPUT

INTERRUPT ACKNOWLEDGE - - - - - TLIF/6824-10

TL/F/6824-9

6·11

==

:E
N
......
N

Applications in Microcomputer Systems

(Continued)

co

a..

c
......

Outp,ut Port (with Hand-Shanking)

N
......

DATA
BUS

N

co

a..

.----~

c

STB

OUTPUT STROBE
(HAN O·SHAKI NG
SIGNAL FROM
OUTPUT DEVICE)

SYSTEM OUTPUT

SYSTEM RESET

~ PORT SELECTION
...._ _ _ _ ~ (LATCH CONTROL)
TLIF 16824-11

INS8080A Status Latch

~ ..
01
02
03
04
05
06
07

8080A

9
8
7
3
4
5
6

DATA BUS

..

SYNC ~
OBIN

j

12V
DV

J

tll-

4>2

4>1
22

STATUS
LATCH

15

~ 01
.............g.
1

r\

\.,~ ~

CLOCK GEN
& DRIVER

~TL)

9
16
18
20
22

. DO

+0~

OP8212/
OP8212M

~ MEMR

..

P 'it
•

STACK
HLTA
OUT

~ Ml
~ INP

_
1i CLR
OS2 MO OSI
'13

~ INTA
~ Wii

I'll
BASIC
CONTROL
BUS
SYNC
DATA ....._ _n...____

OBIN
STATUS ~---""'----4

VCC
TL/F/6824-12

6-12

C

"tJ

~National

Q)

N
.....

~ Semiconductor

0)

.......
C

"tJ
Q)

N
.....

DP8216/DP8216M/DP8226/DP8226M
4-Bit Bidirectional Bus Transceivers

0)

3:

.......
C

"tJ
Q)

General Description
The OP8216/0P8216M and OP8226/0P8226M are 4-bit bidirectional bus drivers to use in bus oriented applications.
The non-inverting OP8216/0P8216M and inverting
OP8226/0P8226M drivers are provided for flexibility in system design.
Each buffered line of the four-bit drivers consists of two
separate buffers that are TRI-STATE® to achieve direct bus
interface and bidirectional capability. On one side of the
driver the output of one buffer and the input of another are
tied together (OB); this side is used to interface to the system side components such as memories, I/O, etc., because
its interface is TTL compatible and it has high driver (50
rnA). On the other side of the driver the inputs and outputs
are separated to provide maximum flexibility. Of course,
they can be tied together so that the driver can be used to
buffer a true bidirectional bus. The 00 outputs on this side
of the driver have a special high voltage output drive capability so that direct interface to the 8080 type CPUs is
achieved with an adequate amount of noise immunity.
The CS input is a device enable. When it is "high" the output drivers are all forced to their high-impedance state.
When it is a "low" the device is enabled and the direction of
the data flow is determined by the OlEN input.

The OlEN input controls the direction of data flow, which is
accomplished by forcing one of the pair of buffers into its
high-impedance state and allowing the other to transmit its
data. A simple two-gate circuit is used for this function.

Features

DP8226/DP8226M

0--------1 >---t---,

DID

0-------.. . . ~o_+_-...
O-----iHX,

DBa

OBO

000

0----+-< ...- - - - 1 - - 1

DOD

011

o----+---t >---1-........

011

001

0----+-<. I-----if---II

OIZ

0----+----1 ">---1f-........
D----+--c

0----+----1 >---1f--........

003

o----+-c ..- - - - l l -.......

1----+--...

0-----11----1

001 O-----lHX.

OOz o-----lHX.

~O_......- " " I I

1---+--'"

OIZ o-----tf----I

"--~I-""'"

01 3

.......
C
"tJ
Q)

N
N

3:

• Oata bus buffer driver to 8080 type CPUs
• Low input load current-O.25 rnA maximum
• High output drive capability for driving system data
bus-50 rnA at 0.5V
• Power up-down protection
• OP8216/0P8216M have non-inverting outputs
• OP8226/0P8226M have inverting outputs
• Output high voltage compatible with direct interface to
MOS
• TRI-STATE outputs
• Advanced Schottky processing
• Available in military and commercial temperature

DP8216/DP8216M

OOZ

0)

0)

Logic Diagrams
010

N
N

~IO__+_-...

1----+--....

01] o - - - - - l l - - - - t ~K>__+_-.,

OB3

OB3
~O] O-----iH~

1----+--....

OlEN 0 - - -...+ - - - -.......
OlEN o---~~----~

"'-----...---ocs

L-----~~--Ocs

TL/F/8753-1

TL/F/8753-2

6-13

:E

CD
C\I
C\I

CO

c..

c.......
CD
C\I
C\I

CO

c..

c.......

:E

CD
,....
C\I

CO

c..

c.......
CD
,....

Absolute Maximum Ratings

(Note 1)

If Military!Aerospace specified devices are required,
contact the National Semiconductor Sales Office!
Distributors for availability and specifications.
Min
-0.5
-1.0

Max

Units

+7.0

V

+5.5

V

Output Currents

125

mA

Maximum Power Dissipation* at 25·C
Cavity Package
Molded Package

1509
1476

mW
mW

All Output and Supply Voltages
All Input Voltages

Min Max Units
·C

-65 +150

Storage Temperature
Lead Temperature (soldering, 4 seconds)

260

Operating Conditions

Note: ·Derate cavity package 10.1 mW/'C above 2S'C; derate molded
package 11.8 mW I'C above 2S'C.

Min

Max

Units

Supply Voltage, Vee
DP8216M, DP8226M
DP8216, DP8226

4.5
4.75

5.5
5.25

V
V

Temperature, T A
DP8216M, DP8226M
DP8216, DP8226

-55
0

+125
+70

·c

C\I

CO

c..
c

Electrical Characteristics DP8216, DP8226 Vee =
Symbol

Parameter

·C

·C

5V ± 5% (Notes 2,3, and 4)

Limits
Conditions
Min

Typ

Max

Units

DRIVERS
VIL

Input Low Voltage

VIH

Input High Voltage

IF

Input Load Current

VF = 0.45V

0.95

V

-0.25

mA

V

2
-0.03

IR

Input Leakage Current

VR = 5.25V

10

I-'-A

Ve

Input Clamp Voltage

Ie = -5mA

-1.2

V

VOL1

Output Low Voltage

IOL = 25 mA

0.3

0.45

V

VOL2

Output Low Voltage

DP8216 10L = 55 mA
DP8226 10L = 50 mA

0.5

0.6

V

VOH

Output High Voltage

10H = -10 mA

2.4

3.0

Ise

Output Short Circuit Current

Vee = 5V

-30

-75

-120

mA

1101

Output Leakage Current TRI-STATE

Vo = 0.45V /5.5V

100

I-'-A

0.95

V

-0.25

mA

-1.2

V

0.45

V

-65

mA

20

I-'-A

0.95

V

-0.5

mA

20

I-'-A

130
120

mA
mA

V

RECEIVERS
VIL

Input Low Voltage

VIH

Input High Voltage

IF

Input Load Current

2

V
-0.08

VF = 0.45V

Ve

Input Clamp Voltage

Ie = -5mA

VOL

Output Low Voltage

10L = 15 mA

VOH1

Output High Voltage

10H = -1 mA

3.65

4.0

Ise

Output Short Circuit Current

Vee = 5V

-15

-35

1101

Output Leakage Current TRI-STATE

Vo = 0.45V /5.5V

0.3

V

CONTROL INPUTS (CS, OlEN)
VIL

Input Low Voltage

VIH

Input High Voltage

IF

Input Load Current

VF = 0.45V

IR

Input Leakage Current

VR = 5.25V

lec

Power Supply Current
DP8216
DP8226

V

2
-0.15

95
85

6-14

C

"'tJ

co

Electrical Characteristics (Continued) DP8216M, DP8226M Vee = 5V ± 10% (Notes 2, 3 and 4)

N
.....
Q)

Limits
Symbol

Parameter

Conditions

Units
Min

Typ

Max

VIH

C

"'tJ

co

N
.....
Q)

DRIVERS
VIL

......

Input Low Voltage
DP8216M
DP8226M

0.95
0.90

Input High Voltage

V

2

IF

Input Load Current

VF = 0.45V

IR

Input Leakage Current

VR = 5.5V

Ve

Input Clamp Voltage

Ie = -5mA

V
V

-0.08

~
......

C

"'tJ

co
N
N

Q)

-0.25

rnA

......

40

f-tA

co

-1.2

V

C

"'tJ
N
N

Q)

VOL1

Output Low Voltage

10L = 25mA

0.3

0.45

V

VOL2

Output Low Voltage

10L = 45 mA

0.5

0.6

V

VOH

Output High Voltage

10H = -5mA

2.4

3.0

Ise

Output Short Circuit Current

Vee = 5.0V

-30

-75

-120

mA

1101

Output Leakage Current TRI-STATE

Vo = 0.45V/5.5V

100

f-tA

0.95
0.9

V
V

-0.25

mA

-1.2

V

0.45

V

V

RECEIVERS
VIL

Input Low Voltage
DP8216M
DP8226M

VIH

Input High Voltage

IF

Input Load Current

VF = 0.45V

Ve

Input Clamp Voltage

Ie = -5 mA

VOL

Output Low Voltage

10L = 15 mA

VOH1

Output High Voltage

10H = -0.5 mA

3.4

VOH2

Output High Voltage

10H = -2mA

2.4

Ise

Output Short Circuit Current

Vee = 5.0V

-15

1101

Output Leakage Current TRI-STATE

Va = 0.45V/5.5V

V

2
-0.08

0.3

V

3.8

V
-35

-65

mA

20

f-tA

0.95
0.9

V
V

-0.5

mA

80

f-tA

130
120

mA
mA

CONTROL INPUTS (CS, OlEN)
VIL

Input Low Voltage
DP8216M
DP8226M

VIH

Input High Voltage

IF

Input Load Current

VF = 0.45V

IR

Input Leakage Current

VR = 5.5V

lee

Power Supply Current
DP8216M
DP8226M

V

2
-0.15

95
85

6-15

~

::E
U)

'"
co
'"

Switching Characteristics (Notes 2,3 and 4)

D.

C

.......

Limits

Symbol

Parameter

Conditions
Min

U)

'"co'"

D.

DP8216M, DP8226M, Vee

C

Input to Output Delay, DO Outputs

::E
U)

CL
R2

= 30 pF, R1 = 3000,
= 6000

tp02

Input to Output Delay, DB Outputs
DP8216M
DP8226M

CL
R2

= 300 pF, R1 = 900,
= 1800

Output Enable Time
DP8216M
DP8226M

DO Outputs: CL = 30 pF,
R1 = 3000/10 kO,
R2 = 6000/1 kO
DB Outputs: CL = 300 pF,
R1 = 900110 kO,
R2 = 1800/1 kO

Output Disable Time
DP8216M
DP8226M

DO Outputs: CL = 5 pF,
R1 = 3000/10 kO,
R2 = 6000/1 kO
DB Outputs: CL = 5 pF,
R1 = 900110 kO,
R2 = 1800/1 kO

.......

'"

co

D.

C
.......

,..
U)

tE

co
'"
D.
C

to

DP8216, DP8226 Vee

Input to Output Delay, DO Outputs

CL
R2

= 30 pF, R1 = 3000,
= 6000

tp02

Input to Output Delay, DB Outputs
DP8216
DP8226

CL
R2

= 300 pF, R1 = 900,
= 1800

Output Enable Time
DP8216
DP8226

DO Outputs: CL = 30 pF,
R1 = 3000/10 kO,
R2 = 6000/1 kO
DB Outputs: CL = 300 pF,
R1 = 900/10 kO,
R2 = 1800/1 kO

Output Disable Time

DO Outputs: CL = 5 pF,
R1 = 3000/10 kO,
R2 = 6000/1 kO
DB Outputs: CL = 5 pF,
R1 = 900110 kO,
R2 = 1800/1 kO

to

15

25

ns

19
16

33
25

ns
ns

42
36

75
62

ns
ns

16
16

40
38

ns
ns

15

25

ns

20
16

30
25

ns
ns

45
35

65
54

ns
ns

20

35

ns

= S.OV ± S%

tp01

tE

Units

Max

= sv ± 10%

tp01

,..

I

Typ

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the
devices should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified, minImax limits apply across the -SS'C to + 12S'C temperature range for the DP8216M and DP8226M and across the O'C
to + 70'C temperature range for the DP8216 and DP8226. All typical values are given for Vee = SV and TA = 2S'C.
Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.
Note 4: Only one output at a time should be shorted.

6·16

C

Test Conditions

"'tJ
CD

Test Load Circuit

Input pluse amplitude of 2.5V.
Input rise and fall times of 5.0 ns between 1.0V and 2.0V.
Output loading is 5.0 rnA and 10 pF.
Speed measurements are made at 1.5V levels.

N
-.
Q)

VCC

4)

C
'"
"'tJ
CD
N

-.
Q)

OurD- ....- - -..

-~:"

:s::
'"
c

"'tJ
CD

N
N

~

Q)

TL/F/8753-4

'"
C
"'tJ
CD

Switching Time Waveforms

N

N

INPUTS

__________________

Q)

3V

--J~'_.5_V

:s::

_________________________________

[~O-I

I

OUTPUT

ENABLE _ _ _ _ _ _ _ _ _ _ _) , ( ' 5 V

~'E-I

OUTPUTS

_________________________

-'~~s_v

DV

X~I._S_V

_____ ::

~.ob'ltV

___________

J~

VOH

VOL

t

D.SV
TL/F/8753-5

Connection Diagram

Capacitance TA =

25°C

Dual-In-Llne Package

~

CHIP SELECT "B"- I

16

Symbol

Min

f- VCC

DATA OUTPUT 000- 2
14

~

003 DATA OUTPUT

DATA INPUT 010- 4
DATA OUTPUT 001- 5

810IRrt~~:~~

081- 6

12 -013
11

~

10 -082

GNO- 8

9 ~012

Unit

Typ

Min

CIN

Input Capacitance

4

6

pF

COUT

Output Capacitance
DO Outputs
DO Outputs

6
13

10
18

pF
pF

Note: This parameter is periodically sampled and is not 100% tested. Condition 01 measurement is 1 = 1 MHz, VSIAS = 2.5V, Vee = 5.0V, and TA =
25°C.

DATA INPUT

002 DATA OUTPUT

DATA INPUT 011- 1

Limit

Parameter

~to~~tC~~ONAL
DATA INPUT

TL/F/8753-3

Order Number DP8216J, DP8216N, DP8226J, DP8226N,
DP8216MJ or DP8226MJ
See NS Package Number J16A or N16A

6-17

~

N
N

co
a..
C

~National

~ Semiconductor
DP8224 Clock Generator and Driver
General Description

Features

The DP8224 is a clock generator/driver contained in a standard, 16-pin dual-in-Iine package. The chip, which is fabricated using Schottky Bipolar technology, generates clocks
and timing for the 8080A microcomputer family.
Included in the DP8224 is an oscillator circuit that is controlled by an external crystal, which is selected by the designer to meet a variety of system speed requirements. Also
included in the chip are circuits that provide: a status strobe
for the DP8228 or DP8238 system controllers, power-on reset for the 8080A microprocessor, and synchronization of
the READY input to the 8080A.

• Crystal-controlled oscillator for stable system operation
• Single chip clock generator and driver for 8080A microprocessor
• Provides status strobe for DP8228 or DP8238 system
controllers
• Provides power-on reset for 8080A microprocessor
• Synchronizes READY input to 8080A microprocessor
• Provides oscillator output for synchronization of external circuits
• Reduces system component count

8080A Microcomputer Family Block Diagram
RDMI

RAMI

8080A
MICROPROCESSOR

READY

PARALLEL
110
INTERFACE

DP8224

IERIAl
110
INTERFACE
RESET IN

CPDWERDN)

READY IN

EXTENDED
CAPAllllTY

TL/F/8752-1

6-18

Absolute Maximum Ratings (Note 2)

Operating Conditions

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Vee
15V
VDD
Input Voltage
-1Vto +5.5V
Storage Temperature Range
- 65°C to + 150°C
Maximum Power Dissipation· at 25°C
Cavity Package
1509mW
Molded Package
1476mW
Lead Temperature (Soldering, 4 seconds)
260°C
o Derate cavity package 10.1 mWI'C above 25'C; derate molded package
11.B mW I'C above 25'C.

Electrical Characteristics
Symbol

Supply Voltage
Vee
Voo
Temperature (TA)

Min

Max

Units

4.75
11.4
0

5.25
12.6
+70

V
V
°C

(Note 3)

Parameter

Conditions

IF

Input Current Loading

VF

Min

= 0.45V

Typ

Max

Units

-0.25

mA

IR

Input Leakage Current

VR

= 5.25V

10

/J- A

Ve

Input Forward Clamp Voltage

Ie

= -5mA

-1.0

V

VIL

Input "Low" Voltage

Vee

= 5V

0.8

VIH

Input "High" Voltage

RESIN Input

2.6

V

All Other Inputs

2.0

V

= 5V

0.25

V

VIH-VIL

RESIN Input Hysteresis

Vee

VOL

Output "Low" Voltage
(1 and <1>2 output drivers do not have short circuit protection.
Note 2: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 3: Unless otherwise specified min/max limits apply across the O'C to + 70'C range for the DPB224. All typical values are for TA = 25'C, Vcc = 5V, and
Voo = 12V.

Crystal Requirements*
Tolerance

0.005% at O°C to + 70°C
Fundamental
Resonance
Load Capacitance
20 pFto 30 pF
°It is good design practice to ground the case of the crystal
"With tank circuit, use 3rd overtone mode

Equivalent Resistance
Power Dissipation (Min)

6-19

750. to 200.
4mW

•

~

N
N

co

D..

C

Switching Characteristics (Note 3)
Symbol

Parameter

Conditions

Min

Typ

Max

Units

t1

 1 Pulse Width

2tCY _ 20
9

ns

t2

2 Pulse Width

5tCY _ 35
9

ns

t01

1 to 2 Delay

0

ns

t02

2 to 1 Delay

2tCY _ 14
9

ns

t03

1 to 2 Delay

2tCY
9

tr

1 and 2 Rise Time

20

ns

tf

1 and 2 Fall Time

20

ns

to2

2 to 2 (TTL) Delay

15

ns

CL = 20 pF to 50 pF

2 TTL, CL = 30 pF,
R1 = 300n, R2 = 600n

toss

2 to STSTB Delay

tpw

STSTB Pulse Width

tORS

RDYIN Set-Up Time to Status Strobe

tORH

RDYIN Hold Time After STSTB

tOR

READY or RESET to 2 Delay

tCLK

ClK Period

fMAX

Maximum Oscillating Frequency

CIN

Input Capacitance

2tCY
9

-5

+ 20

"

6tCY
9

6tCY _ 30
9
STSTB, CL = 15 pF
R1 = 2 kn, R2 = 4 kn

Ready and Reset, CL = 10 pF,
R1 = 2 kn, R2 = 4 kn

ns

4tCY
50 - -9-

ns

4tCY
9

ns

4tCY -25
9

ns
ns
MHz

27
VCC = 5V, VOO = 12V,
VBIAS = 2.5V, f = 1 MHz

8

Test Circuit
Vee
~~
~~ Rl

.. ~

i
GND

6-20

eL

~~
~~

~~

R2

~~

GND

ns

tCY _ 15
9

tCY
9

INPUT

ns

TL/F/8752-2

pF

Waveforms
_I

tCY
tR ....

-'4>I-1

,..

.... tF

"-

V

~!

r-

~1

tOl

~'Dl£j?

~z

4>z(nU

IFROM:=tJ

't

'4>2

I"::..t 0 4>Z

t04>Z-

J

-\
I

I.

toSS

1

STSTB

ROYIN
DR RESIN

READY OUT

_---I

I

.1

tORH

n

I

SYNC

tORS

toz

----------------

~-----------.------------------------~tOR-

-------------------------).

--------- ~------------------------.
I----tOR k-

RESET OUT

TLlF/8752-3
Voltage Measurement Points:

1, 2 Logic "0" =

1.0V, Logic "1"

Switching Characteristics (Fortey =
Symbol

Parameter

=

B.OV.

All other Signals measured at 1.5V.

488.28 ns)
Conditions

Min

Typ

Max

Units

tc/>1

cf>1 Pulse Width

89

ns

t2

cf>2 Pulse Width

236

ns

t01

Delay cf> 1 to cf>2

0

ns

t02

Delay cf>2 to cf> 1

95

t03

Delay cf>1 to cf>2 Leading Edges

109

tr

Output Rise Time

tf

Output Fall Time

toss

cf>2 to STSTS Delay

tOc/>2

cf>2 to cf>2 (TTL) Delay

tpw

Status Strobe Pulse Width

tORS
tORH

cf>1 and cf>2 Loaded to CL = 20 to 50 pF
Ready and Reset Loaded to 2 mA/10 pF
All Measurements Referenced to 1.5V
unless Specified Otherwise

ns
129

ns

20

ns

20

ns

296

326

ns

-5

15

ns

40

ns

RDYIN Set-Up Time to STSTS

-167

ns

RDYIN Hold Time after STSTS

217

ns

tOR

READY or RESET to cf>2 Delay

192

fMAX

Oscillator Frequency

ns
18.432

6-21

MHz

•

Functional Pin Definitions
The following describes the function. of all of the DP8224
input/output pins. Some of these descriptions reference internal circuits.

For manual system reset, a momentary contact switch that
provides a low (ground) when closed is also connected to
the RESIN input.

INPUT SIGNALS

Ready In (RDYIN): An asynchronous READY signal that is
re-clocked by a D-type flip-flop of the DP8224 to provide the
synchronous READY output discussed below.

Crystal Connections (XTAL 1 and XTAL 2): Two inputs
that connect an external crystal to the oscillator circuit of
the DP8224. Normally, a fundamental mode crystal is used
to determine the basic operating frequency of the oscillator.
However, overtone mode crystals may also be used. The
crystal frequency is 9 times the desired microprocessor
speed (that is, crystal frequency equals 1/tey x 9). When
the crystal frequency is above 10 MHz, a selected capacitor
(3 to 10 pF) may have to be connected in series with the
crystal to produce the exact desired frequency. Figure A.

+ 5 Volts: Vee supply.
+ 12 Volts: Voo supply.
Ground: 0 volt reference.
OUTPUT SIGNALS
Oscillator (OSC): A buffered oscillator signal that can be
used for external timing purposes.



m>
IJ!>

Dual-In-Line Package
XTALI
OSC

OSCILLATOR
XTAL2

TANK---.....I
4>1
4>2
4>2(TTL)

lD
OD
DD
CD

RESET

16

VCC

RESIN

15

XTAL 1

RDYIN

14

XTAL 2

13

TANK

SYNC

12

DSC

4>2 (TTL)

11

4>1

READY

DP8224

4>2

STm

0:::>
0::>

SYNC

------+---L~

RESIN

----I ~~~~
SCHMITT
INPUT

[D

ROYIN

-------+-1

STSTB

CD

GND

VDD

TLIF/87S2-S

Top View
nt-...- - - RESET

CD

0 1 - - - - - READY

CD
TLIF/87S2-4

6-22

Order Number DP8224J or DP8224N
See NS Package Number
J16A or N16A

Applications Information
1 UNIT ___1_ _
OSC. FREn.

¢2-----'
TL/F/8752-7

EXAMPLE: (8080 Icy

F _ _1_

= 500 ns)

osc = 18 MHz/55 ns

ZIr-ja
USED ONLY

<1>1 = 110 ns (2 x 55 ns)
<1>2 = 275 ns (5 x 55 ns)

FOR OVERTONE

CRYSTALS

<1>2-<1>1 = 110 ns (2 x 55 ns)

ro~~~FNEEDED

FIGURE B. DP8224 Clock Generator Waveforms

ABOVE 10MHz)

13

14

15
11

22

10

15
23

DP8224

12

19

STSTB (TO 8228 PIN

11

TL/F/8752-6

FIGURE A. DP8224 Connection Diagram

6·23

::E
co
C")
C\I

co

D..

C

........

co
C")
C\I

co

D..
C
........

::E
co

~National

~ Semiconductor

DP8228/DP8228M/DP8238/DP8238M
System Controller and Bus Driver

C\I
C\I

General Description

D..

The DPS22S/DPS22SM, DPS23S/DPS23SM are system
controller/bus drivers contained in a standard, 2S-pin dualin-line package. The chip, which is fabricated using Schottky
Bipolar technology, generates all the read and write control
signals required to directly interface the memory and input!
output components of the SOSOA microcomputer family. The
chip also provides drive and isolation for the bidirectional
data bus of the SOSOA microprocessor. Data bus isolation
enables the use of slower memory and input! output components in a system, and provides for enhanced system noise
immunity.

co
C

........

co
C\I
C\I

co

D..

C

when an interrupt is acknowledged by the SOSOA. This feature permits the use of a multilevel priority interrupt structure
in large, interrupt-driven systems.

Features
• Single chip system controller and bus driver for SOSOA
Microcomputer Systems
• Allows use of multibyte CALL instructions for Interrupt
Acknowledge
• Provides user-selected single-level interrupt vector
(RST 7)
• Provides isolation of data bus
• Supports a wide variety of system bus structures
• Reduces system component count
• DPS23S/DPS23SM provides advanced Input!Output
Write and Memory Write control signals for large system timing control

A user-selected signal-level interrupt vector (RST 7) is provided by the device for use in the interrupt structure of small
systems that need only one basic vector. No additional
components (such as an interrupt instruction port) are required to use the single interrupt vector in these systems.
The devices also generate an Interrupt Acknowledge (INTA)
control signal for each byte of a multibyte CALL instruction

8080A Microcomputer Family Block Diagram

..
r

ROMs

4>1 & 4>2 CLOCKS
DP8224
CONTROL SIGNALS
CLOCK
(RESET & REAOY)
GENERATOR
&
SYNC
DRIVER

-+
-+..
,.

8080A
MICROPROCESSOR

WAIT . . . HOLO

~J~T:~O~

~

AI,..

""I~

CONTROL

(~I.GONB~~~
& HLDA)
--

BIDIRECTIONAL
BUS DRIVER

! t
mTB

.

--....
r

..

~

~

r------,
""I

I

SYSTEM
CONTROLLER
LOGIC

I

I

OPTIONAL
BUFFERS/
DECODERS
ADDRESS
BUS (16)

DP8228/DP8228M.
DP82J8/DP82JBM

DATA BUS (8)
CONTROL (5)

~

I
I
I

L-TC--J

BUSEN

I. . . .

-+..

A15 - AD

07 - 00

-

RAMs

..
1-+

-

r

PARALLEL
I/O
INTERFACE

SERIAL
I/O
INTERFACE

~

.

-- ..
r

1-

EXTENDED
CAPABILITY

r

TL/F/6B2 5-1

6-24

C

If Military/Aervspace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Storage Temperature
- 65DC to + 150DC
Supply Voltage, Vee

Supply Voltage (Vee)
DP8228M, DP8238M
DP8228, DP8238
Operating Temperature (TA)
DP8228M, DP8238M
DP8228, DP8238

-0.5to +7V

Input Voltage

."

Operating Conditions

Absolute Maximum Ratings

-1.5Vto +7V

Output Current

100mA
2179mW

Molded Package

2361 mW

Units

4.50
4.75

5.50
5.25

VDe
VDe

."

-55
0

+125
+70

DC
DC

3:
......

"Derate cavity package 14.5 mWI"C above 25'C; derate molded package
18.9 mWI"C above 25'C.

Electrical Characteristics
Symbol

Min

Conditions

Ve

Input Clamp Voltage, All Inputs

Vee = Min, Ie = -5 mA

IF

Input Load
Current

Vee = Max
VF = 0.45V for DP8228, DP8238
VF = 0.40V for DP8228M, DP8238M

IA

Units

0.6

-1.0

V

fJ-A

250

fJ-A

All Other
Inputs

250

fJ-A

20

fJ-A

100

fJ-A

2.0

V

Vee = Max, VA = Vee

All Other
Inputs

lee

Power Supply Current

Vee = Max

Output Low
Voltage

00-07

Output High

Vee = Min,
10L = 2 mA

All Other
Outputs

Vee = Min,
IOL=10mA

00-07

Ve = Min,
10L = -10 fJ-A

All Other
Outputs

0.8
DP8228, DP8238

160

190

mA

DP8228M, DP8238M

160

210

mA

DP8228M, DP8238M

0.50

V

DP8228, DP8238

0.45

V

DP8228M, DP8238M

0.50

V

0.45

V

DP8228, DP8238
DP8228M, DP8238M

3.3

3.8

V

DP8228, DP8238

3.6

3.8

V

2.4

3.8

V

Vee = Min,lOH = -1 mA

los

Short Circuit Current, All Outputs

Vee = 5V, Vo = OV

10 (OFF)

OFF State Output Current
All Control Outputs

Vee = Max, Vo = Vee

INTA Current

(See Test Conditions, Figure 3)

Note 1: Typical values are for TA

Max

00,01,04,
05 and 07

Vee = 5V

liNT

Typ
(Note 1)

fJ-A

Input Threshold Voltage,
All Inputs

VOH

Min

500

VTH

VOL

CO
N
N
CO

C

."
CO
N
eN
CO

......
C

3:

750

DBO-DB7

Input Leakage
Current

C

CO
N
eN
CO

Parameter

02 and 06

CO
......

."

~ TA ~ Max, Min ~ Vee ~ Max, unless otherwise noted

STSTB

N

Max

Note: Maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits is not intended and should be limited to those conditions
specified under DC electrical characteristics.

Maximum Power Dissipation· at 25DC
Cavity Package

CO

N

Min

Vee = Max, Vo = 0.45V

= 25'C and typical supply voltages.

6-25

15

90

mA

100

fJ-A

-100

fJ-A

5

mA

:E
co
C"')
N

co

Capacitance * VSIAS

D.

= 2.5V, Vee = 5.0V, TA = 25°C, f = 1 MHz

Symbol

C

.......

co
C"')

Parameter

Min

Typ
(Note 1)

Max

Units

N

CIN

Input Capacitance

8

12

pF

D.

COUT

Output Capacitance Control Signals

7

15

pF

.......

1/0

1/0 Capacitance (0 or DB)

8

15

pF

co
C

:E
co

'This parameter is periodically sampled and not 100% tested.

N
N

co

D.

C

Switching Characteristics Min::;; Vee::;;

Max, Min::;; T A ::;; Max

.......
co
N

N

co

Symbol

Parameter

DP8228M,
DP8238M

Conditions

D.

Min

C

DP8228,
DP8238

Max

Min

Units

Max

tpw

Width of Status Strobe

25

22

ns

tss

Set-Up Time, Status Inputs 00-07

8

8

ns

tSH

Hold Time, Status Inuts 00-07

toe

Delay from STSTB to Any Control Signal

(Figure 2)

tRR

Delay from DBIN to Control Outputs

(Figure 2)

tRE

Delay from DBIN to Enablel
Disable 8080 Bus

(Figure 1)

tRo

Delay from System Bus to 8080
Bus During Read

(Figure 1)

tWR

Delay from WR to Control Outputs

(Figure 2)

tWE

Delay to Enable System Bus
DBO-DB7 after STSTB

(Figure 2)

two

Delay from 8080 Bus 00-07 to
System Bus DBO-DB7 During Write

(Figure 2)

tE

Delay from System Bus Enable to
System Bus DBO-DB7

(Figure 2)

tHO

HLDA to Read Status Outputs

(Figure 2)

tos

Set-Up Time, System Bus Inputs to HLDA

10

10

ns

tOH

Hold Time, System Bus Inputs to HLDA

20

20

ns

5
20

5

5
75

20

ns

30

30

ns

45

45

ns

45

30

ns

45

ns

30

ns

40

ns

30

ns

25

ns

60

5

30
5

ns
60

40

5

30
25

Test Conditions
~ Vee
Vee
~

~

: 500n
... ~

:~ 4kn
~

OUTPUT
PIN

J

+12 V
~

1 k!'!± 10%: ~

...

OUTPUT
PIN

I

I
DP8228/8238

"pf

I'OOPf

...

... ~ND

GND

TL/F/6825-3

TL/F/6825-2

FIGURE 1. Test Load

FIGURE 2. Test Load

6-26

liNT

... ~
... : tkn

IE

INTA 1-

TLIF/6825-4

FIGURE 3.INTA Test Circuit
(For RST 7)

Timing Diagram
4>1
4>2
STATUS STROBE ----~.

·F;;....----------'\

8080 OATA BUS ----Jr-+-I-~_-------------DBIN

------+-+-=-;.;....-1'

HLOA - - - - - + - I - - - + - - - - / (
INTA.IOR. MEMR
OURING HLDA

\i=F;;;...;.;.;;....--------

SYSTEM BUS DURING READ
INS8080A BUS DURING READ - - - - - - - -

WR

-----+-1------""

tWR_~--~I_IWR
IOWOR MEMW------+I----~~~
11,.;......;..;.;;....---

---------~---~

:I~---J;~-~IW=D--------SYSTEM BUS DURING WRITE - - - - - - - - - <
¥__________
__ IWE __

INS8080A BUS DURING WRITE : : : : : : : : :

SYSTEM BUS ENABLE

\

J
~I-

--
CD

..J

Device Number
Logic Function
O°C to +70°C

Output Characteristics

Output

Input

-55°C to + 125°C

Page
Number

DP8480A

Inverting

TRI-STATE Fall Through latch

TTL

10k ECl

7-5

DP8481

Inverting

Gated Fall Through latch

10k ECl

TTL

7-8

DP8482A

Inverting

TRI-STATE Fall Through latch

TTL

10k ECl

7-11

Inverting

Gated Fall Through latch

100k ECl

TTL

7-14

DS3630

DS1630

Hex Buffer

50 ns Prop. Delay at 500 pF

CMOS

CMOS

7-17

DS8800

DS7800

Dual 2-lnput Gate

Open-Collector - 30V to 30V

PMOS

7-21

DS88L12

DS78l12

Hex Inverter

Active Pull-Up O.4V to 14V

MOS

TTL
TTL

@

2.6 rnA

@

3.2 rnA

DP8483

7-24

TTL
TTL

CMOS

CMOS

CMOS

CMOS

MM74C901

MM54C901

Hex Inverter

Active Pull-Up O.4V

MM74C902

MM54C902

Hex Buffer

Active Pull-Up O.4V

MM74C903

MM54C903

Hex Inverter

Active Pull-Up OV to 15V

PMOS

CMOS

CMOS

MM74C904

MM54C904

Hex Buffer

Active Pull-Up OV to 15V

PMOS

CMOS

CMOS

MM74C906

MM54C906

Hex Buffer

Open Drain OV to 15V

NMOS

CMOS

CMOS

MM74C907

MM54C907

Hex Buffer

Open Drain Vee to Vee - 15V

PMOS

CMOS

CMOS

7-4

C

"C

~National

Q)
~

Q)

o

~ Semiconductor

>

DP8480A 10k Eel to TTL level Translator with latch
General Description

Features

This circuit translates Eel input levels to TIL output levels
and provides a fall-through latch. The TRI-ST ATE@ outputs
are designed to drive standard 50 pF loads. The strobe and
chip select inputs operate at Eel levels.

• l6-pin flat-pack or DIP
• TRI-STATE outputs
• Eel control inputs
• 8 ns typical propagation delay with 50 pF load
• Outputs are TRI-STATE during power up/down for
glitch free operation
• 10k Eel input compatible

Logic and Connection Diagram

Truth Table

Dual-In-Llne Package
VEE

1

16 Vee

D

Q

STR

H

l

l

l

l

H

l

l

X

Q

H

l

X

Hi-Z

X

H

CS

00 2
H

= high level (most positive)

L = low level (most negative)
X

= don't care

01 3

02 4

Order Number DP8480AF, DP8480AJ
or DP8480AN
See NS Package Number F16B, J16A or N16A
03 5

04 6

•

TL/F/5861-1

Top View

7-5

<
Q

co
~
co

0..

C

Absolute Maximum Ratings

(Note 1)

If Military I Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
VEE Supply Voltage

-8V

Vee Supply Voltage

7V

Input Voltage

Maximum Power Dissipation" at 25°C
Molded Package

-65°C to + 150°C

• Derate molded package 11.B mW I'C above 2S'C.

Recommended Operating
Conditions

GNDtoVEE

Output Voltage

1476 mW

Storage Temperature

5.5V

VEE Supply Voltage

-5.2V ±10%

Vee Supply Voltage

5.0V ± 10%

TAl Ambient Temperature

O°Cto 75°C

Electrical Characteristics (TIL logic) Notes 2, 3 and 4
Symbol

Parameter

Conditions

Min

VOL

Output low Voltage

VOH

Output High Voltage

= 12mA
10H = -10 mA

IAV

Output low Drive Current

Force 2.5V

los

Output High Drive Current

ForceOV

loz

TRI-STATE Output Current

lec

Supply Current

Typ

10l

Max

Units

0.5

V
V

Vee -2V
70

150

-70

-150

-350

-50

1

+50

/-LA

35

mA

mA
mA

Electrical Characteristics (ECl logic) Notes 2 and 3
Symbol
Vil

VIH

Parameter
Input low Voltage

Input High Voltage

Conditions

=

VEE

=

VEE

-5.2V

-5.2V

TA

Min

Max

Units

0° C
25°C
75°C

-1870
-1850
-1830

Typ

-1490
-1475
-1450

mV

O·C
25°C
75·C

- 1145
-1105
-1045

-840
-810
-720

mV
/-LA

III

Input low Current

VIN

= VllMax

50

125

IIH

Input High Current

VIN = VIH Max

75

750

/-LA

lEE

Supply Current

-55

mA

Switching Characteristics Notes 2 and 5
Symbol

Conditions

Min

Typ

Max

Units

tpD1

Strobe to Output Delay

Parameter

CL = 50 pF

4

9

15

ns

tpD2

Data to Output Delay

CL = 50 pF

3.5

8

15

ns

ts

Data Set-Up Time

(Note 6)

3.0

1.0

ns

tH

Data Hold Time

(Note 6)

3.0

1.0

ns

tpw

Strobe Pulse Width

(Note 6)

5.0

3.0

tZE

Delay from Chip Select to
Active State from Hi-Z State

CL

=

6

15

25

ns

tEZ

Delay from Chip Select to Hi-Z
State from Active State

CL = 50 pF

4.5

12

22

ns

50 pF

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified, minImax limits apply across the O'C to 7S'C ambient temperature range in still air and across the specified supply variations.
All typical values are for TA = 2S'C and nominal supply. Maximum propagation delays are specified with all outputs switching simultaneously.
Note 3: All currents into device pins are shown as positive; all currents out of device pins are shown as negative. All voltages are referenced to ground, unless
otherwise specified.
Note 4: When DC testing lAY or los, only one output should be tested at a time and the current limited to 120 MA max.
Note 5: Unless otherwise specified, all AC measurements are referenced from the 50% level of the ECl input to the O.BV level on negative transitions or the 2.4V
level on positive transitions of the output. ECl input rise and fall times are 2.0 ns ± 0.2 ns from 20% to BO%.
Note 6: Caution should be used when latching data while the outputs are switching. TIL outputs generate severe ground noise when switching. This noise can be
sufficient to cause the ECl latch to loose data. Board mounting and good supply decoupling are desirable. The worst case conductions are with all outputs
switching low simultaneously, the maximum capacitive loading on the outputs and the maximum Vee supply voltage applied.

7-6

Switching Time Waveforms
-tpw-

TL/F/5861-2

81 open

TL/F/5861-3

Test Load

CL

INCLUDING PROBE
AND JIG CAPACITANCE

TL/F/5861-4

Typical Performance Versus CL
15n5

VCC=5V±10%
ALL OUTPUTS- TA=25°C ~
SWITCHING
~
SIMULTANEOUSLY ~

15ns

~

'" 10n5

.:.

E 5ns

--15 pF

.--

.---"""

50pF

'" 10n5

~

~

~

.:.
N

fONE
fOUTPUT
SWITCHING f
f-

VCC=5V±10%
ALL OUTPUTS - TA=25°C ~
SWITCHING
.J#'
~
SIMULTANEOUSLY

5ns

15 pF

150pF

---

~

--- --

----ONE
OUTPUT
SWITCHING - .

-

50 pF

150 pF

CL-LOAD CAPACITANCE (pF)

CL-LOAD CAPACITANCE (pF)

TLIF/5861-6

TL/F/5861-5

7-7

....

co
~
co
Q.
C

~National

~ Semiconductor
DP8481 TTL to 10k Eel level Translator with latch
General Description

Features

This circuit translates TTL input levels to ECl output levels
and provides a fall-through latch. The outputs are gated with
CS providing for wire ORing of outputs. The strobe and chip
select inputs operate at ECl levels.

•
•
•
•
•

Logic and Connection Diagram

Truth Table

Dual-In-Llne Package

16-pin flat-pack or DIP
ECl control inputs
CS provided for wire ORing of output bus
10k ECl 1/0 compatible
3.0 ns typical propagation delay

D

Q

STR

CS

H

l

l
X
X

H

l
l

Q
l

H
X

H
H
H

l

H=high level (most positive)
L=low level (most negative)
X=don't care

Order Number
DP8481F, DP8481J or DP8481N
See NS Package
F16B, J16A or N16A

TL/F/5862-1

Top View

7-8

Absolute Maximum Ratings

Recommended Operating Conditions

(Note 1)

If Military!Aerospace specified devices are required,
contact the National Semiconductor Sales Office!
Distributors for availability and specifications.

VEE Supply Voltage

-5.2V ±10%

Vcc Supply Voltage

5.0V ± 10%

TAl Ambient Temperature

O°C to 75°C

-8V

VEE Supply Voltage
Vcc Supply Voltage

7V

Input Voltage (ECL)

GND to VEE

Input Voltage (TTL)

-1Vto 5.5V

Output Current

50mA

Maximum Power Dissipation· at 25°C
Molded Package

1476 mW

Storage Temperature
-65°C to +150°C
•Derate molded package 11.B mWrc above 2S'C.

Electrical Characteristics (TTL Logic) (Notes 2 and 3)
Symbol

Parameter

VIL

Input Low Voltage

VIH

Input High Voltage

IlL

Input Low Current

VIN=0.5V

IIH

Input High Current

VIN=2.5V

Input Clamp Voltage

IIN= -12 mA

Supply Current

Vcc=5.5V

VIL

VIH

Parameter
Input Low Voltage

Input High Voltage

Max

Units

0.8

V

-200

p.A
p.A

V
-25

Icc

Symbol

Typ

2.0

VCLAMP

Electrical Characteristics

Min

Conditions

1.0

40

-0.9

-1.2

V

10

20

mA

(ECL Logic) (Notes 2 and 3)

Conditions

TA

Min

Max

Units

VEE= -5.2V

O°C
25°C
75°C

-1870
-1850
-1830

-1490
-1475
-1450

mV

O°C
25°C
75°C

-1145
-1105
-1045

-840
-810
-720

mV

VEE= -5.2V

Typ

IlL

Input Low Current

VIN= -1.8V

55

150

p.A

IIH

Input High Current

VIN= -0.8V

85

200

p.A

VOL

Output Low Voltage

VEE= -5.2V

VOH

VOLC

VOHC

lEE

Output High Voltage

Output Low Voltage

Output High Voltage

Supply Current

VEE= -5.2V

VEE= -5.2V

O°C
25°C
75°C

-1870
-1850
-1830

-1665
-1650
-1625

mV

O°C
25°C
75°C

-1000
-960
-900

-840
-810
-720

mV

-1645
-1630
-1605

mV

O°C
25°C
75°C
O°C
25°C
75°C

VEE= -5.2V

-1020
-980
-920

mV
-70

VEE= -5.7V

7-9

-90

mA

•

,..
ClO
"II:t'
ClO

a..
C

SWitching Characteristics

(Notes 2 and 4)

Min

Typ

Max

Units

tpDl

Strobe To Output Delay

1.5

3.0

6.0

ns

tpD2

Data To Output Delay

2.5

4.5

7.5

ns

ts

Data Set-Up Time to Strobe

5.0

2.0

tH

Data Hold Time

1.0

0

ns

tpw

Strobe Pulse Width

5.0

3.0

ns

tpD3

Chip Select to Output Delay

1.0

2.5

tscs

Data Set-Up Time to Chip Select

5.5

3.0

Symbol

Parameter

Conditions

ns

4.0

ns
ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified, minImax limits apply across the O'C to 75'C ambient temperature range in still air and across the specified supply variations.
All typical values are for 25'C and nominal supply.
Note 3: All currents into device pins are shown as positive; all currents out of device pins are shown as negative. All voltages are referenced to ground, unless
otherwise specified.
Note 4: Unless otherwise specified, all AC measurements are referenced from the 1.5V level of the TTL input and to/lrom the 500/0 point of the ECl signal and a
50n resistor to - 2V is the load. ECl input rise and fall times are 2.0 ns ± 0.2 ns from 200/0 to 800/0. TTL input characteristic is OV to 3V with tr= tf S; 3 ns measured
from 100/0 to 900/0.

SWitching Time Waveforms

-/

cs

j

-tPD3-

-tPD3-

Q

.

--{tsc,~
TL/F/5862-2

~PW""

STR

)["

\s..-/\

-,l

I\-J

-

.-t

tH -

-ts-

)~

-

-;l

Q

tPD1-

-

j

.,l
~

-tpDl

-tPD2-

-)~r

)~

7-10

I- tpD2
TLlF/5862-3

~National

~ Semiconductor
DP8482A 100k Eel to TTL level Translator with latch
General Description

Features

This circuit translates Eel input levels to TIL output levels
and provides a fall-through latch. The TRI-STATE® outputs
are designed to drive standard 50 pF loads. The strobe and
chip select inputs operate at Eel levels.

•
•
•
•
•

Logic and Connection Diagram

Truth Table

16-pin flat-pack or DIP
TRI-STATE outputs
Eel control inputs
8 ns typical propagation delay with 50 pF load
Outputs are TRI-STATE during power up/down for
glitch free operation
• 100k Eel input compatible

Dual-In-Line Package
D

Q

STR

CS

H

l

l

l

l

H

l

l

X

Q

H

l

X

Hi-Z

X

H

16 Vee

VEE 1

00_2+-_--t

H = high level (most positive)
L=low level (most negative)

3
01--t--r-I

X=don't care

4
02_+-_+-1

03-+--+-1
Order Number DP8482AF, DP8482AJ or DP8482AN
See NS Package Number F16B, J16A or N16A
04....;6+-_+-1

GND 8

GND
TL/F/5863-1

Top View

7-11



Min
3

Max
15

Units
V

oC")

Supply Voltage

16V

Input Voltage

16V

Temperature (TA)
OS16308
OS36308

-55
0

+125
+70

·C
·C

C")

CD

C")

tJ)

.......
In
CD
,...

tJ)

Q

Output Voltage

16V

Lead Temperature (Soldering, 4 seconds)

260·C

Electrical Characteristics (Notes 2 and 3)
Symbol
IINH

Parameter
VIN

VIN

IINL

VOH

Min

Conditions

Logical "1" Input Current

Logical "0" Input Current

Logical "1" Output Voltage

VIN

= Vee, lOUT = -400,...A
= Vee - 2.0V, lOUT = 16 mA
= 0.4V, lOUT = 16 mA

VIN

= Vee, lOUT = - 400 ,...A

VIN

Typ

Max

Units

OS16308

90

200

,...A

OS36308

90

200

,...A

OS16308

0.5

6.4

mA

OS36308

0.5

4.0

mA

OS16308

-0.15

2.0

mA

OS36308

Vee - 150

1.3

mA

OS16308

Vee -1

Vee - 0.75

V

OS36308

Vee - 0.9

Vee - 0.75

V

= Vee - OAV, lOUT = -16 mA OS16308 Vee - 2.5

Vee - 2.0

V

OS36308
VOL

Logical "0" Output Voltage

VIN

= OV, lOUT = 400,...A

VIN

= OV, lOUT = 16 mA

VIN

= 0.4V, lOUT = 16 mA

Switching Characteristics Vee =
Symbol
tpdO

tpd1

5.0V, T A

Parameter
Propagation Delay to a Logical "0"

Propagation Delay to a Logical "1"

Vee - 2.5

V

Vee - 2.0

OS16308

0.75

1

V

OS36308

0.75

0.9

V

OS16308

0.95

1.3

V

OS36308

0.95

1.3

V

OS16308

1.2

1.6

V

OS36308

1.2

1.5

V

= 25·C unless otherwise specified
Typ

Max

Units

CL

Conditions

= 50 pF

Min

30

45

ns

CL

= 250 pF

40

60

ns

CL

= 500 pF

50

75

ns

CL

= 50 pF

15

25

ns

CL

= 250 pF

35

50

ns

50
75
ns
CL = 500 pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for 'Operating Temperature Range"
they are not meant to imply that the devices should be operating at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the -SS·C to + 12S·C temperature range for the D816308 and across the O·C to +70"C range for
the D836308. All typicals are given for Vee = S.OV and TA = 2S·C.
Note 3: All currents into device pins shown as positive, out of device pins as negative. all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.

7-18

c

en
......

Typical Applications

0)

W

o

tD
"-

C

CMOS to Transmission Line Interface
~c

en
w
0)

~C

CMOS

CMOS

FAMilY

0S3630B

w

FAMilY

o
tD

~tsmDLINE

TL/F/5826-3

CMOS to CMOS Interface

LED Driver

74C

CMOS
FAMilY

TL/F/5826-4

TL/F/5826-5

AC Test Circuit and Switching Time Waveforms
INPUT

v+
INPUT
ov-......;.~II

VOH-------+---,.----~

OUTPUT

OUTPUT

VOL - - - + '
tpdO

TL/F/5826-8
Pulse Generator characteristics: PRR

=

1.0 MHz, PW

=

500 ns,

tr = tf < 10 ns, VIN = 0 to Vee

TLiF/5826-7
CL includes probe and jig capacitance

•
7-19

I

m

oC")

CD

Typical Performance Characteristics

C")

tJ)

c
......
m
o

0.3

C")

,....

CD

tJ)

c

0.4

~

VOH vs Temperature,
VIN = Vee

~
CI

0.6
0.1

~

0.8

>

0.9

a

H
>

0.5

I:

~

VOH Active vs Temperature

~ lou/ ~ -.Joo"l

~
~

-

io"'"

....

'~IN ~ Ve~ - 0~4:

1.1

IOUT=16mA _

'" I"

1.8

~

1.9

~

Z.O

CI

~

Z.1

>

Z.Z

a

1.0

1.6

Z5 45 65 85 105 lZ5

.....

§

>

J

" ro-..

TEMPERATURE I'C)

TA =Z5°C

j.

~i"'"

1"'00..

-r-

....

30
ZO

-55 -35 -15 5

Z5 45 65 85 105 lZ5

ZOO

)t'

40

400

./

~

40

f

V
100

!>

50

200

300

400

t,.al

11

13

15

I-- Vee = 5V
I-- CL ~ 250 pF

t,.ao

.....

f

/

V

~

Vee IV)

;::
~

/

o

-

3

500

~CI

./

30

10

300

--t

Y

TA • Z5'C

ZO

...........

t,.,o

Propagation Delay
vs Temperature

~

j.

........

LOAD CAPACITANCE IpF)

f- Vee = 5.0V

]

35

.........

30
100

tpd1 vs Load Capacitance

50

"

g:

i"'"

TEMPERATURE I'C)

60

~

1..,..;"""

o

I...

40

~
;::
~

~i"""

~

./

1.0'

g

~

~i"'"

40

CL =Z50pFTA zZ5'C -

]
>

I.Z

0.9

Propagation Delay vs Vee
45

50

" ........

560
-55 -35 -15 5 Z5 45 65 85 105 125

'pdo vs Load Capacitance

60

"

600

I- Vee = 5.0V

]

"'"

,

640

.....

10

1.3

1.0

" ........

680

TEMPERATURE I'C).

VIN = OV
lOUT --16mA

1.1

......

.! 7Z0

I"

1.4

~

lOUT' -40IJpA:
_
VIN • OV

I"-

160

-55 -35 -15 5 Z5 45 65 85 105 lZ5

VOL vs Temperature
1.5

>"

"

TEMPERATURE I'C)

1.6

840

VOL vs Temperature

800

Z.3

1.1
-55 -35 -15 5

880

500

30

--

--

-r
t,.a!,..o
.... i"""

"...
~

-

~

-55 -35 -15 5 25 45 65 85 105 lZ5

LOAD CAPACITANCE IpF)

TEMPERATURE (OC)
TLIF/582S-S

7·20

c
en

~National

~

0)

o
o
......

~ semiconductor

c
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0)

OS7800/0S8800 Dual Voltage Level Translator

o
o

General Description

Features

The OS7800/0S8800 are dual voltage translators designed
for interfaCing between conventional TTL or LS voltage levels and those levels associated with high impedance junction or MOS REF-type devices. The design allows the user a
wide latitude in his selection of power supply voltages, thus
providing custom control of the output swing. The translator
is especially useful in analog switching; and since low power
dissipation occurs in the "off" state, minimum system power
is required.

• 31 volt (max) output swing
• 1 mW power dissipation in normal state
• Standard 5V power supply
• Temperature range:
OS7800
- 55°C to + 125°C
O°C to +70°C
OS8800
• Compatible with all MOS devices

Schematic and Connection Diagrams
Metal Can Package
Vee

Vee

V.

Rl

11K

OUTPUT X

TL/F/5827-2

...- -.....M-...-

Top View
Order Number DS7800H or DS8800H
See NS Package Number H10C

OUTPUT X

.....- - - -. . .-V2

TL/F/5827-1

Typical Applications
4-Channel Analog Switch

+i
5Y

rID

r------

+!'DV

-,1

___4

I

SWITCH I

Bipolar to MOS Interfacing

MM451
ANALOG INPUT I'

I
ANALOG INPUT 2

SWITCH 2

rJ---0

~MOSSHIFT
REGISTER
TTL
DS1IOO
I
INPUT~
OTL
DR

Lr--r

LEVELS~

OTl
DR

TTl
INPUT
LEVElS
ANALOG INPUT 3

SWITCH 3

ANALOG INPUT 4

SWITCH 4

'I

,-__ ,...J I

-=

-22V

..,,""""

L _____ --.J
TL/F/5827-3

• Analog signals within the range of

+ BV to

- BV.

7-21

-=

-IOV

TL/F/5827-4

•

o
o

CO
CO

Absolute Maximum Ratings (Note 1)

C

......
o
o

If Military!Aerospace specified devices are required,
contact the National Semiconductor Sales Office!
Distributors for availability and specifications.

r-..

Vee Supply Voltage

C

V2 Supply Voltage

-30V

V3 Supply Voltage

30V

(/)

CO

(/)

Operating Conditions
Supply Voltage, Vee
DS7800
DS8800
Temperature (TA)
OS7800
DS8800

7.0V

V3-V2 Voltage Differential

40V

Input Voltage

5.5V

Min

Max

Units

4.5
4.75

5.5
5.25

V
V

-55
0

+125
+70

·C
·C

- 65·C to + 150·C

Storage Temperature
Lead Temperature (Soldering, 4 seconds)

260·C

Maximum Power Dissipation* at 25·C
Metal Can (TO-5) Package
·Derate metal can package 4.6 mWI'C above 25'C.

690mW

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Min

Conditions

VIH

Logical "1" Input Voltage

Vee = Min

Vil

Logical "0" Input Voltage

Vee = Min

IIH

Logical "1" Input Current

Vee = Max

III

Logical "0" Input Current

Vee = Max, VIN = O.4V

IOl

Output Sink Current

Vee = Min, VIN = 2V,

I
I VIN =

-0.2

I
I DS8800

IOH

Vee = Max, VIN = 0.8V (Notes 4 and 7)

Ro

Output Collector Resistor

TA = 25°C

VOL

Logical "0" Output Voltage

Vee = Min, VIN = 2.0V (Note 7)

leC(MAX)

Power Supply Current
Output "ON" Per Gate

Vee = Max, VIN = 4.5V (Note 5)

leC(MIN)

Power Supply Current
Output "OFF" Per Gate

Vee = Max, VIN = OV (Note 5)

tpdO

V
V

5

Il A

1

rnA

-0.4

mA

5.5V

DS7800

1.6

mA

2.3

11.5

Units

0.8
VIN = 2.4V

Output Leakage Voltage

Symbol

Max

2.0

V3 Open

Switching Characteristics TA =

Typ
(Note 6)

mA

16.0

10

Il A

20.0

kn

V2 + 2.0

V

0.85

1.6

rnA

0.22

0.41

mA

25°C, nominal power supplies unless otherwise noted

Parameter

Conditions

Transition Time to Logical
"0" Output

TA = 25·C, C = 15 pF (Note 8)

Min

Typ

Max

Units

25

70

125

ns

TA = 25°C, C = 15 pF (Note 9)
Transition Time to Logical
25
62
125
ns
"1" Output
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the - 55'C to + 125'C temperature range for the DS7800 and across the o'e to + 70'e range for
the DS8800.
Note 3: All currents into device pins shown as pOSitive, out of device pins as negative, all voltages referenced to' ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Current measured is drawn from V3 supply.
Note 5: Current measured is drawn from Vee supply.
Note 6: All typical values are measured at TA = 2S'C with Vee = S.OV, V2 = -22V, V3 = +8V.
Note 7: Specification applies for all allowable values of V2 and V3.
Note 8: Measured from 1.SV on input to SO% level on output.
Note 9: Measured from 1.SV on input to logiC "0" voltage, plus 1V.
tpd1

7-22

Since this current is relatively constant, the collector of 02
acts as a constant current source for the output stage. Logic
inversion is performed since logical "1" input voltages
cause current to be supplied to 02 and Os. And when Os
turns on the output voltage drops to the logical "0" level.

Theory of Operation
The two input diodes perform the AND function on TIL input voltage levels. When at least one input voltage is a logical "0", current from Vee (nominally 5.0V) passes through
R1 and out the input(s) which is at the low voltage. Other
than small leakage currents, this current drawn from Vee
through the 20 kO resistor is the only source of power dissipation in the logical "1" output state.

The reason for the PNP current source, 02, is so that the
output stage can be driven from a high impedance. This
allows voltage V2 to be adjusted in accordance with the
application. Negative voltages to - 25V can be applied to
V2. Since the output will neither source nor Sink large
amounts of current, the output voltage range is almost exclusively dependent upon the values selected for V2 and Vs.

When both inputs are at logical "1" levels, current passes
through R1 and diverts to transistor 01, turning it on and
thus pulling current through R2. Current is then supplied to
the PNP transistor, 02. The voltage losses caused by current through 01, Os, and 02 necessitate that node P reach a
voltage sufficient to overcome these losses before current
begins to flow. To achieve this voltage at node P, the inputs
must be raised to a voltage level which is one diode potential lower than node P. Since these levels are exactly the
same as those experienced with conventional TIL, the interfacing with these types of circuits is achieved.

c
en
.......

co
o

o
......

c
en
co
co
o

o

Maximum leakage current through the output transistor Os
is specified at 10 J-I-A under worst-case voltage between V2
and Vs. This will result in a logical "1" output voltage which
is 0.2V below Vs. Likewise the clamping action of diodes 04,
Os, and 06, prevents the logical "0" output voltage from
falling lower than 2V above V2, thus establishing the ouput
voltage swing at typically 2 volts less than the voltage separation between V2 and Vs.

Transistor 02 provides "constant current switching" to the
output due to the common base connection of 02. When at
least one input is at the logical "0" level, no current is delivered to 02; so that its collector supplies essentially zero
current to the output stage. But when both inputs are raised
to a logical "1" level current is supplied to 02'

V3

25
2D

15
1D

Selecting Power Supply Voltage
-5

The graph shows the boundary conditions which must be
used for proper operation of the unit. The range of operation
for power supply V2 is shown on the X axis. It must be
between -25V and -avo The allowable range for power
supply Vs is governed by supply V2. With a value chosen for
V2, Vs may be selected as any value along a vertical line
passing through the V2 value and terminated by the boundaries of the operating region. A voltage difference between
power supplies of at least 5V should be maintained for adequate Signal swing.

-5
-1D

-15
-2D

-25
TL/F/5827-5

Switching Time Waveforms

INPUT----'
OUTPUT----+_~

Tpc! 0
TL/F/5827-6

7-23

•

I

N
'I'""

..J
CX)
CX)

U)

C

.......
N

~National

~ Semiconductor

'I'""

..J

CX)

......

U)

C

DS78L 12/DS88L 12 Hex TTL-MOS Inverter/Interface Gate
General Description
The OS78L 12/0S88L12 is a low power TTL to MOS hex
inverter element. The outputs may be "pulled up" to + 14V
in the logical "1" state, thus providing guaranteed interface
between TTL and MOS logic lev~ls. The gate may also be

operated with Vee levels up to + 14V without resistive pullups at the outputs and still providing a guaranteed logical
"1" level of Vee - 2.2V with an output current of - 200 IJ-A.

Schematic and Connection Diagrams
vee

Dual-In-Llne Package

Vee

500

20K

--""''''''"__- 0 VOUT

GND
TL/F/8584-2

Top View
Order Number DS78L 12J, DS88L 12J,
DS88L 12N and DS78L 12W
See NS Package Number J14A, N14A or W14B

12K

Note: Shown is schematic for each inverter.

TL/F/B5B4-1

Typical Applications
TTL Interface to MOS ROM
without Resistive Pull-Up

TTL Interface to MOS ROM
with Resistive Pull-Up

+12V

+12V

Vss

+5V
3.6K

Vss

INPUT

>e.........-""""'IINPUT

ROM
DS88L12

ROM

Voo
DS88L12

Voo

-12V
TL/F/85B4-3

-12V
TL/F IB584-4

7-24

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
15V
Input Voltage
5.5V
Output Voltage
15V
Storage Temperature Range
- 65·C to + 150·C
Maximum Power Dissipation· at 25·C
Cavity Package
1308 mW
Molded Package
1207 mW
Lead Temperature (Soldering, 4 sec.)
260·C
"Derate cavity package 8.72 mW/·e above 25·C; derate molded package
9.66 mW/·C above 25·C.

Operating Conditions
Min

Max

Units

Supply Voltage (Vee)
DS78L12
DS88L12

4.5
4.75

5.5
5.25

V
V

Temperature (TA)
DS78L12
DS88L12

-55
0

125
70

·C
·C

Electrical Characteristics (Notes 2 and 3)
Symbol
VIH

Parameter
Logical "1" Input Voltage

Min

Typ

Vee = 14.0V

Conditions

2.0

1.3

Vee = Min

2.0

1.3

VIL

Logical "0" Input Voltage

Vee = 14.0V

VOH

Logical "1 " Output Voltage

VIN = 0.7V

Vee = Min

Max

V
V

1.3

0.7

V

1.3

0.7

V

Vee = 14.0V, lOUT = -200/AA

11.8

12.0

Vee = Min, lOUT = -200/AA

14.5

15.0

V
V
V

VIN = OV, Vee = Min, lOUT = - 5.0 /AA (Note 6)
VOL
IIH

Logical "0" Output Voltage
Logical "1 " Input Current

VIN = 2.0V
VIN = 2.4V
VIN = 5.5V

Units

Vee = 14.0V, lOUT = 12 mA

0.5

1.0

V

Vee = Min, lOUT = 3.6 mA

0.2

0.4

V

Vee = 14.0V

<1

20

/-LA

Vee = Max

<1

10

/-LA

Vee = 14.0V

<1

100

/-LA

Vee = Max

<1

100

/-LA

-320

-500

/-LA

-100

-180

/-LA

-25

-50

mA

IlL

Logical "0" Input Current

VIN = 0.4V

Ise

Output Short Circuit Current

VOUT = OV
(Note 4)

Vee = 14.0V

-10

Vee = Max

-3

-8

-15

mA

leeH

Supply Current-Logical "1 "
(Each Inverter)

VIN = OV

Vee = 14.0V

0.32

0.50

mA

Vee = Max

0.11

0.16

mA

Supply Current-Logical "0"
(Each Inverter)

VIN = 5.25V

Vee = 14.0V

1.0

1.5

mA

Vee = Max

0.3

0.5

mA

Vee = 14.0V
Vee = Max

leeL

Switching Characteristics TA =
Symbol
tpdO
tpd1

25·C, nominal power supplies unless otherwise noted
Typ

Max

Units

(Figure 2)

27

45

ns

Vee = 14.0V (Figure 1)

11

20

ns

79

100

ns

Parameter

Conditions

Propagation Delay to a Logical "0"
from Input to Output

TA = 25°C

Propagation Delay to a Logical "1 "
from Input to Output

TA = 25·C

Vee = 5.0V
Vee = 5.0V

(Figure 2), (Note 5)

Min

34
55
ns
Vee = 14.0V (Figure 1)
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the - 55·C to + 125·C temperature range for the DS78L12 and across the O·C to + 70·C range for
the DS8BL12.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: \Pdl for Vee = 5.0V is dependent upon the resistance and capaCitance used.
Note 6: VOH = Vee - 1.1V for the DSBBL12 and Vee - 1.4V for the DS7BL12.
7·25

II

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AC Test Circuits

Switching Time Waveforms
+14V

C

.......

~

,...
N

Vee

..J

....co

fJ)

C

V. -

r-t. - ~

~

Ve e • 5V

14
V",

Yf'"''
ForVcc -14V

, - - l.lV - - I

r

INPUT

>4:-::'--"--0_ Your

:

1

:
1

1

1
I

1

c, '""
f = 1 MHz

TLlF/8584-6

7-26

---50%---

I i i
1 1
I

IpdO_1

For Vee· S.OV

FIGURE 2

.

OUTPUT~'
1

I

TL/F18584-5

FIGURE 1

-J=L
l .DV

=14.DV

Ir = If = 10 ns
PW = 100 ns

1---I
1'

:
1
' - - I .. ,
1

TL/F18584-7

Section 8
Frequency Synthesis

Section 8 Contents
Frequency Synthesis-Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Synthesis-Selection Guide ...............................................
OS8614/0S8615/0S8616/0S8617 130/225 MHz Low Power Dual Modulus Prescalers . . . . .
OS8627/0S8628130/225 MHz Low Power Prescalers..................................
OS8629 120 MHz Oivide·by·100 Prescaler........ .....................................
OS8673/0S8674 Low PowerVHF/UHF Prescalers.....................................
OS8906 AM/FM Digital Phase·Locked Loop Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS8907 AM/FM Digital Phase·Locked Loop Frequency Synthesizer. . . . . . . . . . . . . . . . . . . . . .
OS8908 AM/FM Digital Phase·Locked Loop Frequency Synthesizer. . . . . . . . . . . . . . . . . . . . . .
OS8911 AM/FM/TV Sound Up·Conversion Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . .
AN·335 Digital PLL Synthesis . .. . . . . .. . . . . . . . .. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. . .. . .
AN·512 OS8911 AM/FM/TV Sound Up·Conversion Frequency Synthesizer. . . . . . . . . . . . . . . .

8·2

8·3
8·5
8·6
8·10
8·13
8·16
8·19
8·26
8·32
8·40
8·49
8·56

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Frequency Synthesis

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Frequency synthesis is the process of generating a multitude of different frequencies from one reference frequency.
A common application where the frequency synthesis concept is used is in electronically tuned radios and televisions.

state-of-the-art microCMOS devices are usually limited to
100 MHz operation. Even the FM band exceeds this limitation. As a result, a prescaler is almost always used in PLL
tuning applications such as FM radios, police scanning radios, aircraft radios, etc. The prescaler is specifically designed
to divide high frequency AC input signals down to a usable
frequency for the PLL. The prescaler becomes an extension
of the PLL's programmable counter as illustrated in Figure
2.

Digital tuning systems are fast replacing the conventional
mechanical systems in AM, FM and television receivers.
The digital approach encompasses the following operational features:
• Precise tuning of station frequencies
• Exact digital frequency display
• Keyboard entry of desired frequency
• Virtually unlimited station memory
• Up/down scanning through the band
• Station "search" (stop on next active station)
• Power-on to the last station
• Easy option for time-of-day clock
In addition, recent developments in large-scale integrated
circuit technology and new varactor diodes for the AM band
have made the cost-benefit picture for digital tuning very
attractive.

For less sophisticated tuning applications, a fixed division
prescaler will make the VCO signal palatable to the PLL and
be sufficient for general tuning characteristics. However, in
some applications, a fixed division prescaler can cause significant undesirable side effects such as:
1. Increased channel spacing (step size) at the output of
the PLL's counter; or
2. A forced decrease of the fixed oscillator reference frequency in order to obtain specific channel spacing
which can lead to

A. increased lock-on time,
B. decreased scanning rates, and

The heart of any digital tuning system is, of course, the
phase locked loop (PLL) synthesizer. The basic subcomponents of a digital system are: a voltage controlled oscillator
(VCO), a phase comparator and some programmable and
fixed dividers. The PLL's basic function is to take two input
signals and match them as illustrated in Figure 1. The output
of the phase comparator of the PLL is an error signal which
is filtered and fed back to the VCO as a DC control voltage.
The DC control voltage adjusts the VCO until it causes the
phase comparator's two inputs to match one another.

C. sidebands at undesirable frequencies.
AN-335 in this section explains in detail how these two
shortcomings of fixed division prescaling are alleviated by
using a dual modulus prescaler. A dual modulus prescaler is
SUbstituted for the fixed prescaler and is controlled by programmable counters in the dual modulus PLL, as illustrated
by the dotted line in Figure 2.
In order to address the requirements of digital frequency
synthesis applications, National has introduced a growing
family of PLL synthesizers and prescalers. The OS8906,
OS8907 and OS8908 are complete PLL synthesizers with
features that go beyond those illustrated in Figure 2.

The weak point of this simple illustration is that many PLLs
are fabricated using MOS processes which make them relatively incapable of receiving high frequency signals. In fact,

PLL

PROGRAMMABLE
COUNTER

TL/XX/0108-1

FIGURE 1

8-3

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Highlights

c

• The OS8908 integrates a reference oscillator, phase comparator, charge pump, operational amplifier, 120 MHz
ECL/12L dual modulus programmable divider, and a shift
register/latch for serial data entry.

-

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turers' NMOS or CMOS PLLs. These low-power/highspeed prescalers are available with division ratios ranging
from a fixed + 20 up to a dual modulus + 64/65. This
array of products allows for the choice of a division ratio
which is virtually tailored to the speed and tuning requirements of a particular frequency synthesis application.

• The OS8614, OS8615, OS8616, OS8617, OS8627, and
OS8628 represent a broad family of single and dual modulus prescalers for use in conjunction with other manufac-

u.

PROGRAt.4t.4ABLE
COUNTER

TL/XX/010B-2

FIGURE 2

8-4

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Frequency Synthesizers Selection Guide

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PLL FREQUENCY SYNTHESIZERS
Product Type
088906
088907
088908
088911

Frequency Bands

Power (mA)

Tuning Resolution

Page No.

AM/FM
AM/FM
AM/FM
AM/FMIVHF TV

160
160
160
35

500 Hz/12.5 kHz
10 Hz/25 kHz

8-19
8-26
8-32

1 kHz,9 kHz,1 0 kHz, 20 kHz
FM; 10, 12.5,25, 100 kHz
AM; 1, 1.25, 2.5, 10kHz

AN-335 Oigital
PLL 8ynthesis

8-40
8-49

HIGH FREQUENCY PRESCALERS
Product Type

Power (mA)

fMAX

Page No.

+24
+20
+100

7/10

130/225 MHz
130/225 MHz
30/120 MHz

8-10
8-10
8-13

+20/21
+32/33
+40/41

7/10
7/10
7/10
7/10

130/225 MHz

8-6
8-6
8-6
8-6

Divide Modulus

Single (Fixed) Modulus Dividers
088627
088628
088629

7/10
135

Dual-Modulus Dividers
088614
088615
088616
088617

+64/65

8-5

130/225 MHz
130/225 MHz
130/225 MHz

CD
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Low Power Oual Modulus Prescalers

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The DS8614 series products are low power dual modulus
prescalers which divide by 20/21, 32/33, 40/41, and 64/65,
respectively. The modulus control (MC) input selects division by N when at a high TTL level and division by N + 1
when at a low TTL level. The clock inputs are buffered,
providing 40/100 mVrms input sensitivity. The two outputs
provide the user the option to wire either a totem-pole or
open-collector output structure. Additionally, the user can
wire a resistor between the two output pins to minimize
edge transition emissions. The outputs are designed to
drive positive edge triggered PLLs. These products can be
operated from either an unregulated 5.5V to 13.5V source
or regulated 5V ± 10% source. Unregulated operation is obtained by connecting Vs to the source with VREG open.
Regulated operation is obtained by connecting both Vs and
VREG to the supply source.

The device can be used in phase-locked loop applications
such as FM radio or other communications bands to prescale the input frequency down to a more usable level. A
digital frequency display system can also be derived separately or in conjunction with a phase-locked loop, and it can
extend the useful range of many inexpensive frequency
counters to 225 MHz.

Features
•
•
•
•
•

Input frequency: 130 MHz (-4); 225 MHz (-2)
Low power: 10 rnA (-4, -2)
Input sensitivity: 100 mVrms (-4); 40 mVrms (-2)
Pin compatible with Motorola MC12015-17 prescalers
Unregulated/regulated power supply option

Logic and Connection Diagrams
Generalized ..;- NIN

+1

MODULUS
CONTROL 01_ _ _--ti>_ _ _ _..,
H=+N
L=+N+1

2

UPPER OUTPUT

3
LOWER OUTPUT
CLK

CLK

CLK

TL/F/5240-1

Dual-In-Line Package

Me

Vs

UPPER OUTPUT

LOWER OUTPUT

-INPUT

GROUND

+ INPUT

TLIF/5240-2

Top View
Order Number DS8614N, DS8615N,
DS8616N or DS8617N (-4, -2)
See NS Package Number N08E
8-6

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Absolute Maximum Ratings

(Note 1)
If Military/Aerospace specified devices are required,
contact the National 5emlconductor 5ales Office/
Distributors for availability and specifications.
Vs, Unregulated Supply Voltage
VREG, Regulated Supply Voltage

Modulus Control Input Voltage
Open-Collector Output Voltage
Operating Free Air Temperature Range
Storage Temperature Range

15V
7V

7V
7V
- 30·C to + 70·C
- 65·C to + 150·C

Parameter

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......
UI

........

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Recommended Operating Conditions

5ymbol

en
......

........

058614-4
058615-4
058616-4
058617-4

Conditions

Min

Max

en
......

058614-2
058615-2
058616-2
058617-2

en

........

Units

Min

Max

en
......
.......

Vs

Unregulated Supply Voltage

VREG

= Open

6.8

13.5

5.5

13.5

V

VREG

Regulated Supply Voltage

Vs and VREG Shorted

4.5

5.5

4.5

5.5

V

fMAX

Toggle Frequency

VIN

20

130

225

MHz

VIN

Input Signal Amplitude

100

300

40

300

mVrms

VSLW

Slew Rate

20

IOH

High Level Output Current

-400

-400

/-LA

IOL

Low Level Output Current

2.0

2.0

rnA

= 100 mVrms

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V/p.,s

20

DC Electrical Characteristics (Notes 2 and 3)

5ymbol

Parameter

058614-4
058615-4
058616-4
058617-4

Conditions

Min

= 13.5V, VREG = Open

VIH

High Level MC Input
Voltage

Vs

VIL

Low Level MC Input
Voltage

VREG

VOH

High Level Output
Voltage

IOH = -0.4 rnA,
Pins 2 and 3 Shorted

ICEX

Open-Collector High
Level Output

Lower Output

VOL

Low Level Output
Voltage

VREG

II

Max MC Input Current

Vs = 13.5V, VREG
VIH = 7V

IIH

High Level MC Input
Current

VREG

IlL

Low Level MC Input
Current

Vs = 13.5V, VREG
VIL = O.4V

Is

Supply Current,
Unregulated Mode

Vs

058614-2
058615-2
058616-2
058617-2

Max

2.0

= Vs = 4.5V

Min

VREG -2

= 4.5V, IOL = 2 rnA
= Open,

= 4.5V, VIH = 2.7V
= Open,

= 13.5V, VREG = Open

Max

2.0
0.8

= 5.5V

Units

V
0.8

V
V

VREG -2
100

100

/-LA

0.5

0.5

V

100

100

/-LA

20

20

/-LA

-200

-200

/-LA

10

10

rnA

Supply Current,
Vs = VREG = 5.5V
10
10
rnA
Regulated Mode
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified MinIMax limits apply across the -30·C to + 70·C range.
Note 3: All current into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown as
Max or Min on absolute value basis.

IREG

8-7

•

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AC Electrical Characteristics Vcc =

C

Symbol

CD
,..

tMODULUS

......
CD

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Parameter
Modulus 8et-Up Time
(Notes 4 and 5)

C

......
II)

,..
CD

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C

......

,..
~

CD

5V ±10%, TA = -30·Cto +70·C

Conditions

Min

Max

088614

55

088615,088616

65

088617

75

AC Input Resistance

VIN = 100 MHz and 50 mVrms

1.0

Input Capacitance

VIN = 100 MHz and 50 mVrms

3

Units

ns

kn
pF

10

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.

CO
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Note 2: Unless otherwise specified min/max limits apply across the - 30·C to

C

Note 3: All currents into device pins are shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values
shown as max or min on absolute value basis.

+ 70·C temperature range.

Note 4: tMODULUS = the period of time the modulus control level must be defined prior to the positive transition of the prescaler output to ensure proper modulus
selection.
Note 5: See Timing Diagrams.

Timing Diagram
+N

+N+l

OUTPUT
WAVEFORM

MODULUS CONTROL
INPUT WAVEFORM

JL,~I

TLIF/S240-3

The logical state of the modulus control input just prior to the output's rising edge will determine the modulus ratio of the device
immediately following that rising edge. The pulse width difference of Nand N + 1 operation occurs during the output = HI conditions.

Typical Applications
5V
0.1,.F

P
REGULATEO

TL/F/S240-S

TL/F/S240-4

Schematic Diagrams
VREG

75k

2

UPPER OUTPUT

~-~
TL/F/S240-7
TL/F /S240-8
TL/F/S240-6

8-8

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Application Hints

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the single ended mode, a capacitor of 0.001 p.F (C2) should
be connected between the unused input and the ground
plane to provide a good high frequency bypass. The capacitor should be made larger for lower frequencies.

OPERATING NOTES

The signal source is usually capacitively coupled to the input. At higher frequencies a 0.001 p.F input capacitor (C1) is
usually sufficient, with larger values used at the lower frequencies. If the input signal is likely to be interrupted, it may
be desirable to connect a 100 k!l resistor between one input and ground to stabilize the device. In the single-ended
mode, it is preferable to connect the resistor to the unused
input. In the differential mode, the resistor can be connected
to either input. The addition of the 100 k!l pulldown resistor
causes a loss of input sensitivity, but prevents circuit oscillations under no signal (open circuit) conditions. In addition, in

The input waveform may be sinusoidal, but below about
20 MHz the operation of the circuit becomes dependent on
the slew rate of the input rather than amplitude. A square
wave input with a slew rate of greater than 20 V / p's will
permit correct operation down to lower frequencies, provided the proper input coupling capacitor is provided.
For regulated mode operation connect Vs to VREG to ensure proper operation (see Typical Application diagram).

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8-9

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OS8627/0S8628 130/225 MHz Low Power Prescalers
General Description
The DS8627 and DS8628 are low power fixed ratio prescalers which divide by 24 and 20, respectively. The inputs can
be driven either single or double-ended and they are buffered, providing 40/100 mVrms input sensitivity. The output
provided is open-collector and is capable of interfacing with
TTL and CMOS.
The device can be used in phase-locked loop applications
such as FM radio or other communications bands to prescale the input frequency down to a more usable level. A
digital frequency display system can also be derived

separately or in conjunction with a phase-locked loop, and it
can extend the useful range of many inexpensive frequency
counters to 225 MHz.

Features
• Input frequency: 130 MHz (-4, -3); 225 mHz (-2, std)
• Low power: 10 mA (-4, -2); 7 mA (-3, std)
• Input sensitivity: 100 mVrms (-4, -3); 40 mVrms (-2, std)

Logic and Connection Diagrams
DS8627 (-:- 24)

+ INPUT
-INPUT
TL/F/5009-1

DS8628 (-:- 20)

+ INPUT
-INPUT
TL/F/5009-2

Dual-In-Llne Package
+INPUT

-INPUT

Vee

Ne

Ne

Ne

OUTPUT

GNO
TL/F/5009-3

Top View
Order Number DS8627N or DS8628N (-4, -3, -2)
See NS Package Number N08E

8-10

Absolute Maximum Ratings

c
en
C)

(Note 1)

0)

If Military/Aerospace specified devices are required,
contact the National 5emlconductor 5ales Office/
Olstrlbutors for availability and specifications.
Vee 5upply Voltage
VIN Input Voltage

Open·Coliector Output Voltage

7V
- 30°C to + 70°C
- 65°C to + 150°C

en
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Operating Free Air Temperature Range
Storage Temperature Range

Parameter

7V

0)
C)

N

058627-4
058628-4

Conditions

058627-2
058628-2

058627-3
058628-3

058627
058628

Units

Min

Max

Min

Max

Min

Max

Min

Max

4.5

5.5

4.5

5.5

4.5

5.5

4.5

5.5

Vee

Supply Voltage

fMAX

Toggle Frequency

20

130

20

130

20

225

20

225

MHz

VIN

Input Signal Amplitude

100

300

100

300

40

300

40

300

mVrms

VSlW

51ewRate

20

IOl

Low Level Output Current

VIN = 100 mVrms

20

20

V

20

3

3

058627-4
058628-4

058627-3
058628-3

058627-2
058628-2

Min

Min

Min

V//J-s
mA

3

DC Electrical Characteristics (Notes 2 and 3)
5ymbol

Parameter

Conditions

Max

Max

Max

058627
058628
Min

Units

Max

leEX

Open·Coliector High Level Output

Output = 5.5V

100

100

100

100

/J-A

VOL

Low Level Output Voltage

Vee = 4.5V,
IOl = 3 mA

0.4

0.4

0.4

0.4

V

Icc

Supply Current

Vee = 5.5V

10

7

10

7

mA

AC Electrical Characteristics Vee =
5ymbol

Parameter

RIN

AC Input Resistance

CIN

Input Capacitance

C

< Vee

Recommended Operating Conditions
5ymbol

N

.......
.......

5V ±10%, TA = -30°C to +70°C
Conditions

Min

VIN = 100 MHz and 50 mVrms

1.0
3

Note 1: "Absolute Maximum

Max

Units

k!l
10

pF

Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the -30'C to + 70'C temperature range.
Note 3: All currents into device pins are shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values
shown as max or min on absolute value basis.

8-11

~~------------------------------------------------------------~

CD
CO

Application Hints

Q

OPERATING NOTES

(J)

......
.....
N
CD
CO

(J)

Q

tions under no signal (open circuit) conditions. In addition, in
the single ended mode, a capacitor of 0.001 ,...F should be
connected between the unused input and the ground plane
to provide a good high frequency bypass. The capacitor
should be made larger for lower frequencies.

The signal source is usually capacitively coupled to the input. At higher frequencies a 0.001 ,...F input capacitor is usually sufficient, with larger values used at the lower frequencies. If the input signal is likely to be interrupted, it may be
desirable to connect a 100 kO resistor between one input
and ground to stabilize the device. In the single-ended
mode, it is preferable to connect the resistor to the unused
input. In the differential mode, the resistor can be connected
to either input. The addition of the 100 kO pull-down resistor
causes a loss of input sensitivity, but prevents circuit oscilla-

The input waveform may be sinusoidal, but below about 20
MHz the operation of the circuit becomes dependent on the
slew rate of the input rather than amplitude. A square wave
input with a slew rate of greater than 20 V /,...s will permit
correct operation down to lower frequencies, provided the
proper input coupling capacitor is provided.

Schematic Diagrams
Vee

OUTPUT
1

-~

15k

+INPUT
15k

TL/F/S009-S

TLIF/S009-4

Typical Application

c3D

0.001 JLf

0886271
OS8628

C1
0.001/lFT

NC

~~UT

liN

5V

C2
0.1/lF

':'
TL/F/S009-6

8-12

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~National

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~ Semiconductor
058629 120 MHz Oivide-by-100 Prescaler
General Description

Features

The OS8629 is a fixed ratio counter combining ECl and low
Power Schottky technology on a single monolithic substrate. This provides high frequency capability and TTL
compatibility. A single 5.2V ± 10% supply is needed.

•
•
•
•
•
•
•
•

The device can be operated in a single-ended or differential
input mode, with the signal source typically capacitively coupled to the input. An input amplifier is included to allow use
of extremely small amplitude, high frequency signals. The
output of the device is a square wave of frequency fOUT =
flN/100 for the OS8629. The output is standard low Power
Schottky.

High Frequency, dc-120 MHz-smail input amplitude
Sine wave input 30 MHz < fiN < 120 MHz
TTL compatible output
May be used with TTL input
Single supply operation 5.2V ± 10%
Single ended or differential input modes
Positive or negative-edge triggered
Count down sequence avoids broadcast FM IF harmonics

Logic and Connection Diagrams

N 3 5 OS8629
TL/F17539-1

Dual-ln-L1ne Package
(TTL) VCC2

VCCI (ECl/BUFFER)

INPUT

OUTPUT

(NEGATIVE·EDGE TRIGGERED)
INPUT
(POSITIVE·EDGE TRIGGERED)

(TTL) GND 2

GND 1
(ECl/BUFFER)

BIAS
TL/F17539-2

Order Number DS8629N
See NS Package Number N08E

Typical Applications
High Frequency-Single-Ended Input
5.2V
Cl
0.01 fJF

flN~
'ITERM

T
-=

fOUT

'05862',

o.01 fJF

T

-=

-=-

·rTERM is the termination impedance

8-13

0.01

~F

-=

TLlF17539-3

m

C'\I

CD
CO

Absolute Maximum Ratings

C

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V

CJ)

Input Voltage
Output Voltage
Storage Temperature Range

Operating Conditions

(Note 1)

Supply Voltage (Vee>
Temperature (TA)

Min
4.68
0

Units
V
·C

Max
5.72
+70

5V
5.5V
- 65·C to + 150·C
300·C

Lead Temperature (Soldering, 10 sec.)

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Conditions

VIN1(P·p)

Input Voltage (Peak-To-Peak)

Single-Ended

@

VIN2(p-p)

Input Voltage (Peak-To-Peak)

Differential

120 MHz

fSINE

Input Frequency with Sine Wave

VIN

fTTL

Input Frequency with TIL Input

dv

Minimum Slew Rate of
Square Wave Input

VIN

VOH

Logical "1" Output Voltage

los

Output Short-Circuit Current

= Min,loH = -10 p.,A
= Min, 10H = -400 p.,A
= Min,lOH = -1.6 mA
Vee = Max
Vee = Min
Vee = Max
VIN = 0.1 Vp_p to 1 Vp_p
Freq. = 120 MHz

VOL

Logical "0" Output Voltage

Icc

Supply Current

ZIN

Input Impedance

@

120 MHz

= 600 mVp-p

Max

Units

200

1000

mV

100

1000

mV

30

120

MHz

0

120

MHz

100

V/p.,s

Min

Typ

= 600 mVp-p
2.9
2.4
2.0

Vee
Vee
Vee

V
V
V

-10

J 10L = 8 mA DS8629
I DS8629
100

-40

mA

0.5

V

90

135

mA

200

350

n

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified. min/max limits apply across the O·C to 70·C range. All typical values are for TA = 25·C and Vee = 5.2V.
Note 3: All currents into device pins shown as positive, out of device pins negative, all voltage referenced to ground unless otherwise noted. All values shown as
max or min on absolute value basis.

8-14

cCf)

Application Hints

C)
0)

OPERATING NOTES

be connected between the unused input and the ground
plane to provide a good high frequency bypass. The capacitor should be made larger for lower frequencies.

Two ground and two Vee connections are provided separating the ECl and buffer/amplifier stages from the TTL section, isolating the noise transients inherent in the TTL structure. In most cases, shorting the two grounds externally to a
good ground plane and the Vee's to a wide Vee bus will
provide sufficient isolation. All components used in the circuit layout should be suitable for the frequencies involved
and leads should be kept short to minimize stray inductance. A well by-passed voltage source should be used.

The input waveform may be sinusoidal, but below about 30
MHz the operation of the circuit becomes dependent on the
slew rate of the input rather than amplitude. A square wave
input with a slew rate of greater than 100 V / JLs will permit
correct operation down to lower frequencies, provided the
proper input coupling capacitor is provided. If it is desired to
use a TTL input signal source, the unused input should have
a 10 k!l resistor added to ground and the input coupling
capacitor should be eliminated with the TTL source dc coupled to the input.

The signal source is usually capacitively coupled to the input. At higher frequencies a 0.01 JLF input capacitor (C1) is
usually sufficient, with larger values used at the lower frequencies. If the input signal is likely to be interrupted, it may
be desirable to connect a 100 k!l resistor between one input and ground to stabilize the device. In the single-ended
mode, it is preferable to connect the resistor to the unused
input. In the differential mode, the resistor can be connected
to either input. The addition of the 100 k!l pull-down resistor
causes a loss of input sensitivity, but prevents circuit oscillations under no Signal (open circuit) conditions. In addition, in
the single ended mode, a capacitor of 0.01 JLF (C2) should

The device can be used in phase-locked loop applications
such as FM radio or other communications bands to prescale the input frequency down to a more usable level. A
digital frequency display system can also be derived separately or in conjunction with a phase-locked loop, and it can
extend the useful range of many inexpensive frequency
counters to 160 MHz (typically).

Input Configuration

Output Configuration

vee

.......-".1\1\,--1....- - 0 BIAS

PIN 5

TLlF17539-4
TL/F17539-5

8-15

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o 088673/088674 Low Power VHF/UHF Prescalers
General Description
The OS8673 and OS8674 products are low power prescalers which divide by 64 and 256 respectively. The devices
are used in frequency synthesis applications such as TV /
CATV, cellular phone, and instrumentation to divide a very
high frequency down to a frequency usable by low power
MOS Pll's.
The devices have differential buffered inputs and complementary ECl outputs. The inputs provide high input sensitivity and good isolation. The OS8673 is pin compatible with
Plessey's SP4531, SP4632, and Motorola's MC12073 prod-

ucts. The OS8674 is pin compatible with Plessey's SP4653
and Motorola's MC12074 products.

Features
•
•
•
•
•

1.0 GHz operating frequency
25 mA typical supply current
20 mV rms input sensitivity
0.8V complementary ECl outputs
low output radiation

Block and Connection Diagrams
Dual-In-Llne Package

NcOavcc

INI

2

7

OUT2

IN2

3

6

OUT1

GND

4

5 Ne
TL/F/9340-1

Top View
Order Number DS8673N or DS8674N
See NS Package Number N08E

vee (a)

.....--+-+-OUT2

"=:-:=e-+- OUTI
NC
TLIF/9340-2

8-16

Absolute Maximum Ratings

(Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V

Output Voltage
Operating Free Air Temperature Range
Storage Temperature Range
ESD rating is to be determined.

Vee + 0.5V
-40°C to + 85°C
- 65°C to + 150°C

Recommended Operating Conditions
Symbol

Parameter

Conditions

Max

Units

4.5

5.5

V

Min

Typ

Vee

Power Supply Voltage Range

FIN

Input Frequency Range

VINMin

80

1,000

MHz

VIN

Input Sensitivity into 50n

80 MHz
300 MHz
500 MHz
700 MHz
1 GHz

20
20
20
20
20

200
200
200
200
200

mVrms

Parameter

Conditions

Min

lee

Power Supply Current

Vee = 5.5V

VOUT

Output Voltage Swing

Peak-to-Peak
(no load)

DC Electrical Characteristics
Symbol

0.8

Typ

Max

Units

25

35

mA

1.2

1.6

V

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.

Typical Applications
Typical Wiring Configuration

-1

~

lr':::;i~:

SIGNAL
SOURCE

-

_--_...

5-

.....

[4

--

TLIF /9340-3

8-17

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......
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Typical Applications

(Continued)

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Typical Input Impedance

en
c

Reference value =
Vi (rms) = 25 mV

son

Vee = 5V
Waveshape is TSD

-1

TL/F/9340-4

Typical Sensitivity Curve Under Nominal Conditions
1000

100

§
~

Recommended
operating area

~~

~ ==

10

1

o

500

f1n (t.lHz)

8-18

1000
TLlF/9340-5

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U Semiconductor
DS8906 AM/FM Digital Phase-Locked Loop Synthesizer
General Description
The OS8906 is a Pll synthesizer designed specifically for
use in AM/FM radios. It contains the reference oscillator, a
phase comparator, a charge pump, a 120 MHz ECLlI 2 l
dual modulus programmable divider, and a 20-bit shift register/latch for serial data entry. The device is designed to
operate with a serial data controller generating the necessary division codes for each frequency, and logic state information for radio function inputs/outputs.
The Colpitts reference oscillator for the Pll operates at 4
MHz. A chain of dividers is used to generate a 500 kHz
clock signal for the external controller. Additional dividers
generate a 12.5 kHz reference signal for FM and a 500 Hz
reference signal for AM/SW. One of these reference signals
is selected by the data from the controller for use by the
phase comparator. Additional dividers are used to generate
a 50 Hz timing signal used by the controller for "time-ofday".
Data is transferred between the frequency synthesizer and
the controller via a 3 wire bus system. This consists of a
data input line, an enable line and a clock line. When the
enable line is low, data can be shifted from the controller
into the frequency synthesizer. When the enable line is transitioned from low to high, data entry is disabled and data
present in the shift register is latched.
From the controller 22-bit data stream, the first 2 bits address the device permitting other devices to share the same
bus. Of the remaining 20-bit data word, the next 14-bits are
used for the Pll divide code. The remaining 6 bits are connected via latches to output pins. These 6 bits can be used
to drive radio functions such as gain, mute, FM, AM, lWand
SW only. These outputs are open collector. Bit 18 is used
internally to select the AM or FM local oscillator input and to
select between the 500 Hz and 12.5 kHz reference. A high
level at bit 18 indicates FM and a low level indicates AM.

The high speed charge pump consists of a switchable constant current source (-0.3 mAl and a switchable constant
current sink (+ 0.3 mAl. If the VCO frequency is low, the
charge pump will source current, and sink current if the VCO
frequency is high.
A separate VCCM pin (typically drawing 1.5 rnA) powers the
oscillator and reference chain to provide controller clocking
frequencies when the balance of the Pll is powered down.

Features
• Uses inexpensive 4 MHz reference crystal
• FIN capability greater than 120 MHz allows direct synthesis at FM frequencies
• FM resolution of 12.5 kHz allows usage of 10.7 MHz
ceramic filter distribution
• Serial data entry for simplified control
• 50 Hz output for "time-of-day" reference with separate
low power supply (VCCM)
• 6-open collector buffered outputs for band switching
and other radio functions
• Separate AM and FM inputs. AM input has 15 mV (typical) hysteresis

Connection Diagram

The Pll consists of a 14-bit programmable 12 l divider, an
ECl phase comparator, an ECl dual modulus (p/p + 1)
prescaler, and a high speed charge pump. The programmable divider divides by (N + 1), N being the number loaded
into the shift register (bits 1-14 after address). It is clocked
by the AM input via an ECl -:- 7/8 prescaler, or through a -:63/64 prescaler from the FM input. The AM input will work
at frequencies up to 8 MHz, while the FM input works up to
120 MHz. The AM band is tuned with a frequency resolution
of 500 Hz and the FM band is tuned with a resolution of 12.5
kHz. The buffered AM and FM inputs are self-biased and
can be driven directly by the VCO thru a capacitor. The ECl
phase comparator produces very accurate resolution of the
phase difference between the input signal and the reference
oscillator.

Dual-In-Line Package
BIT 19 OUT
BIT 20 OUT

DATA
CLOCK

DS8906

AMIN
CAP
BYPASS

8

FMIN

GND

VCCM
TL/F/5775-1

Top View
Order Number DS8906N
See NS Package Number N20A

8-19

CD

o
en
co

en
c

Absolute Maximum Ratings

(Note 1)

If Military I Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.

Storage Temperature Range
- 65°C to
Lead Temperature (Soldering, 4 seconds)

Supply Voltage
(VCC1)
(VCCM)
Input Voltage
Output Voltage

Operating Conditions
7V
7V
7V
7V

DC Electrical Characteristics
Symbol

Supply Voltage, VCC
VCC1
VCCM
Temperature, TA

Logical "1" Input Voltage

IIH

Logical "1" Input Current

Units

4.75
4.5

5.25
6.0
70

V
V
°C

Min

Typ

Max

Units

a

10
0.7

IlA
V

-5

-25

IlA

50

IlA

-250

IlA

0.5

V

2.1
VIN=VCC1

Logical "0" Input Voltage
Logical "0" Input Current

Data, Clock and ENABLE INPUTS, VIN = OV

IOH

Logical "1" Output Current
All Bit Outputs, 50 Hz Output

VOH=5.25V

500 kHz Output

Max

Conditions

IlL

Logical "0" Output Voltage
All Bit Outputs

Min

a

VIL

VOL

V

VOH=2.4V, VCCM=4.5V
IOL =5 mA

50 Hz Output, 500 kHz Output IOL =250 IlA
ICC1

Supply Current (VCC1)

ICCM(STANDBY) VCCM Supply Current
lOUT

Charge Pump Output Current

All Bit Outputs High

90

1.2V:5: VOUT:5: VCCM -1.2V
VCCM:5:6.0V

Pump Up
Pump Down

Symbol

VIN(MIN)(F)

Parameter

FIN Minimum Signal Input

V

160

mA

1.5

4.0

mA

-0.30

-0.6

mA

0.10

0.30

0.6

mA

a

±100

nA

2.5

6.0

mA

VCCM=6.0V, VCC1=5.25V,
All Other Pins Open

AC Electrical Characteristics VCC =

-0.5

-0.10

VCCM = 6.0V, All Other Pins Open

TRI-STATE®
ICCM(OPERATE) VCCM Supply Current

260°C

(Notes 2 and 3)

Parameter

VIH

+ 150°C

5V, TA = 25°C, t r :5: 10 ns, tf:5: 10 ns
Min

Conditions

AM and FM Inputs, O°C :5: TA :5: 70°C

VIN(MAX)(F)

FIN Maximum Signal Input

AM and FM Inputs, O°C :5: TA :5: 70°C

FOPERATE

Operating Frequency Range
(Sine Wave Input)

VIN = 100 mV rms
O°C:5: TA:5: 70°C

AM
FM

1000

Typ

Max

Units

20

100

mV (rms)

1500

0.4
60

mV(rms)

8
120

MHz
MHz

n
n

RIN(FM)

AC Input Resistance, FM

120 MHz, VIN = 100 mV rms

300

RIN(AM)

AC Input Resistance, AM

2 MHz, VIN = 100 mV rms

1000

CIN

Input Capacitance, FM and AM

VIN = 120 MHz

6

10

pF

tEN1

Minimum ENABLE High
Pulse Width

625

1250

ns

tENa

Minimum ENABLE Low
Pulse Width

375

750

ns

tCLKENO

Minimum Time before ENABLE
Goes Low that CLOCK must
be Low

-50

a

ns

Minimum Time after ENABLE
Goes Low that CLOCK must
Remain Low

275

550

ns

Minimum Time before ENABLE
Goes Highthat Last Positive
CLOCK Edge May Occur

300

600

ns

tENOCLK

tCLKEN1

8-20

3

c
AC Electrical Characteristics Vcc =
Symbol

Parameter

tEN1CLK

en

0)

5V, TA = 25°C, t r :<: : 10 ns, tf:<::: 10 ns (Continued)

CD
0

Typ

Max

Units

Minimum Time After ENABLE
Goes High Before an Unused
Positive CLOCK Edge May Occur

175

350

ns

tCLKH

Minimum CLOCK High
Pulse Width

275

550

ns

tCLKL

Minimum CLOCK Low
Pulse Width

400

800

ns

tDS

Minimum OAT A Setup Time,
Minimum Time Before CLOCK
that DATA Must be Valid

150

300

ns

Minimum DATA Hold Time,
Minimum Time After CLOCK
that OATA Must Remain Valid

400

800

ns

tDH

Conditions

Min

0')

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the O'C to

+ 70'C temperature range for the D58906.

Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.

Schematic Diagrams

(OS8906 AM/FM PLL TypicallnputiOutput Schematics)
7 DIODE RAIL
FROM VCCM

VCCI

BIT OUTPUTS,

._~" ,.OUTPUT

DATA IN,
ENABLE

TL/F/5775-3

TL/F/5775-2

-

TL/F/5775-4

VCCM

TO 4 DIODE
RAIL
CLOCK IN
(HYSTERESIS)

OSC B
OSC E

':"

':"
TLlF/5775-6

TL/F/5775-5

8·21

[II

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r---------------------------------------------------------------------------------------,
Schematic Diagrams

c

(DS8906 AM/FM PLL TypicallnputiOutput Schematics) (Continued)
VCCI

VCCM

VCCI

AM
IN
FM
IN

CHARGE
PUMP OUT

TL/F/5775-7

TL/F/5775-8

Timing Diagrams*
ENABLE vs CLOCK

3V--t-_-...

rnm
DV

3V--------+~--~

CLOCK

TLIF/5775-9

CLOCK vs DATA
3V~

___

~~~~

DATA
OV~~~~~~

3V-----------+r----------.5V

CLOCK

TL/F/5775-10

AM/FM Frequency Synthesizer (Scan Mode)

~----,~------------------------------~i~I------------------~
OATAIN~
CLOCK

-----..

CLOCK PULSE

t

'-,..---I

PLL ADDRESS
1,1

DATA BITS
BITS 1-14, +N CODE (LSB FIRST)
BITS 15-20, OUTPUT BITS

t

t

NEGATIVE TRANSITION ON
mnrE CLEARS PREVIOUS
ADDRESS. CLOCK MUST BE
LOW DURING TRANSITION.

POSITIVE TRANSITION ON
ENABLE LATCHES IN NEW
CODE IF PLL IS ADDRESSED.

"Timing diagrams are not drawn to scale. Scale within anyone drawing may not be consistent, and intervals are defined positive as drawn.

8-22

TLIF /5775-11

c

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Applications Information

(X)

CD

Note that until this time, the states of the internal ciata latches have remained unchanged.

SERIAL DATA ENTRY INTO THE DS8906
Serial information entry into the DS8906 is enabled by a low
level on the ENABLE input. One binary bit is then accepted
from the DATA input with each positive transition of the
CLOCK input. The CLOCK Input must be low for the specified time preceding and following the negative transition of
the ENABLE input.

These data bits are interpreted as follows:
DATA BIT POSITION
DATA INTERPRETATION
Bit 20 Output (Pin 2)
Last
2nd to Last
Bit 19 Output (Pin 1)
Bit 18 Output (FMI AM) (Pin 20)
3rd to Last
Bit 17 Output (Pin 19)
4th to Last
5th to Last
Bit 16 Output (Pin 18)
Bit 15 Output (Pin 17)
6th to Last
MSBofN (2 13)
7th to Last
(212)
8th to Last
(211)
9th to Last
10th to Last
(2 10)
(2 9 )
11th to Last
12th to Last
(28)
(27)
13th to Last
+N
(2 6)
14th to Last
5
(2 )
15th to Last
(24)
16th to Last
(23)
17th to Last
(22)
18th to Last
(21)
19th to Last
LSB of N (20)
20th to Last

The first 2 bits accepted following the negative transition of
the ENABLE input are interpreted as address. If these address bits are not 1,1, no further Information will be accepted from the DATA Inputs, and the internal data latches will
not be changed when ENABLE returns high.
If these first 2 bits are 1,1, then all succeeding bits are accepted as data, and are shifted successively into the internal shift register as long as ENABLE remains low.
Any data bits preceding the 20th to last bit will be shifted
out, and are thus irrelevant. Data bits are counted as any
bits following 2 valid (1,1) address bits with the ENABLE
low.
When the ENABLE input returns high, any further serial data
input is inhibited. Upon this positive transition of the
ENABLE, the data in the internal shift register is transferred
into the internal data latches.

Note. The actual divide code is N + 1, i.e., the number loaded plus 1.

8-23

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CD

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Typical Application

C

Electronically Tuned Radio Controller System; Direct Drive LED
5V

SWB+

POSSIBLE MODULE
INSIDE OOTTED LINE

KEYBOARD

-=

6x4

••

+V

34

••

NSC
cOPs
VSS CONTROLLER
(20 PINS)
COP420L
5VGND

G3 SI CKI SK SO Gl
CLOCK
DATA

470PF
4MHz
XTAL

L
T
c:::J

FROM

FROM

DIAl

100 pF
OSC B

CLOCK

OSC E

OS8906
PLL SYNTHESIZER
(20·PIN)

500 kHz

BIT 15 OUT
BIT 16 OUT
BIT 17 OUT
BIT 18 OUT
BIT19 OUT

50 Hz

UNSWITCHED
B+

BIT20 OUT

SWITCHED B+
TO RADIO
TL/F/5775-12

8-24

c
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Logic Diagram

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AM/FM PLL Synthesizer
CHARGE
PUMP
OUT

REF

5V

VCC~

CONTROL
LOGIC
DATA INPUT
AND
CLOCK ..._ _ _ _ _...... AD(~~~~**

BIT 15
OUT

BIT 16
OUT

BIT 11
OUT

BIT1S
OUT

BIT 19
OUT

BIT 20
OUT

FM/AM

DATA
TLIF/5775-13
-Sections operating from VCCM supply
--Address (1,1)

8-25

~

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,-------------------------------------------------------------------------------------,
~National

~ Semiconductor
DS8907 AM/FM Digital
Phase-Locked Loop Frequency Synthesizer
General Description
ble divider divides by (N + 1), N being the number loaded
into the shift register (bits 1-13 after address). It is clocked
by the AM input via an ECl + % prescaler, or through a
+ 6%4 prescaler from the FM input. The AM input will work
at frequencies up to 15 MHz, while the FM input works up to
120 MHz. The AM band is tuned with a frequency resolution
of 10kHz and the FM band is tuned with a resolution of
25 kHz. The buffered AM and FM inputs are self biased and
can be driven directly by the VCO through a capacitor. The
ECl phase comparator produces very accurate resolution
of the phase difference between the input signal and the
reference oscillator. The high speed charge pump consists
of a switchable constant current source (- 0.3 mA) and a
switchable constant current sink (+ 0.3 mA). If the VCO frequency is low, the charge pump will source current, and sink
current if the VCO frequency is high. When using an AFC
the charge pump output may be forced into TRI-STATE® by
applying a low level to the charge pump enable input.

The DSB907 is a Pll synthesizer designed specifically for
use in AM/FM radios. It contains the reference oscillator, a
phase comparator, a charge pump, a 120 MHz ECl/1 2 l
dual modulus programmable divider, and an 1B-bit shift register/latch for serial data entry. The device is designed to
operate with a serial data controller generating the necessary division codes for each frequency, and logiC state information for radio function inputs/outputs.
The Colpitts reference oscillator for the Pll operates at
4 MHz. A chain of dividers is used to generate a 500 kHz
clock signal for the external controller. Additional dividers
generate a 25 kHz reference signal for FM and a 10kHz
reference signal for AM. One of these reference signals is
selected by the data from the controller for use by the
phase comparator.
Data is transferred between the frequency synthesizer and
the controller via a 3 wire bus system. This consists of a
data input line, an enable line, and a clock line. When the
enable line is low, data can be shifted from the controller
into the frequency synthesizer. When the enable line is transitioned from low to high, data entry is disabled and data
present in the shift register is latched.

A separate VCCM pin (typically drawing 1.5 mA) powers the
oscillator and reference chain to provide controller clocking
frequencies when the balance of the Pll is powered down.

Features

From the controller 20-bit data stream, the first 2 bits address the device permitting other devices to share the same
bus. Of the remaining 1B-bit data word, the next 13 bits are
used for the PlL divide code. The remaining 5 bits are connected via latches to output pins. These 5 bits can be used
to drive radio functions such as gain, mute, FM, AM and
stereo only. These outputs are open collector. Bit 16 is used
internally to select the AM or FM local oscillator input and to
select between the 10kHz and 25 kHz reference. A high
level at bit 16 indicates FM and a low level indicates AM.

• Uses inexpensive 4 MHz reference crystal
• FIN capability greater than 120 MHz allows direct synthesis at FM frequencies
• FM resolution of 25 kHz allows usage of 10.7 MHz ceramic filter distribution
• Serial data entry for simplified control
• 50 Hz output for "time-of-day" reference driven from
separate low power VCCM
• 5-open collector buffered outputs for controlling various
radio functions
• Separate AM and FM inputs. AM input has 15 mV (typical) hysteresis

The PLl consists of a 13-bit programmable 12 l divider, an
ECl phase comparator, an ECl dual modulus (p/p + 1) prescaler, and a high speed charge pump. The programma-

Connection Diagram

Dual-In-Llne Package
.!!.~~/lLOUT

BIT 17 OUT...!..

U

BIT 11 ouT..l

.1!.BITI50UT
.1!.8IT 14 OUT

r!!- ~~::~: PUMP

CLOCK....!

Order Number DS8907N
See NS Package Number
N20A

~~~~~~i PUMP
DS8907

.!!..SDHz OUT
..!!.500 kHz OUT

BYP~~~...!.

~OSCB

FMIN...!.

~OSCE

GND..!!!I--_ _ _ _ _......t1!-VCCM

Top View

8-26

TL/F/7511-1

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
(VCC1)
7V
(VCCM)
Input Voltage
7V
Output Voltage
7V

- 65·C to

Storage Temperature Range
Lead Temperature (Soldering, 4 sec.)

+ 150·C
260·C

Operating Conditions
Supply Voltage, VCC
VCC1
VCCM
Temperature, TA

Min

Max

Units

4.75
4.5
0

5.25
6.0
70

V
V
·C

DC Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Conditions

Logical "1" Input Voltage

IIH

Logical "1" Input Current

VIL

Logical "0" Input Voltage

IlL

Logical "0" Input Current

Data, Clock, and ENABLE Inputs, VIN = OV

IlL

Logical "0" Input Current

Charge Pump Enable, VIN = OV

IOH

Logical "1" Output Current
VOH = 5.25V
All Bit Outputs, 50 Hz Output

VOL

Logical "0" Output Voltage
All Bit Outputs

ICC1

Supply Current (VCC1)

500 kHz Output

Typ

Max

Units

0

10
0.7

/-LA
V

-5

-25

/-LA

-250

-450

/-LA

50

/-LA

-250

/-LA

0.5

V

Min

VIH

2.1

V

VIN = 2.7V

VOH = 2.4V, VCCM = 4.5V
IOL = 5 rnA

50 Hz Output, 500 Hz Output IOL = 250/-LA
ICCM(STANDBY) VCCM Supply Current
Charge Pump Ougtput Current
lOUT

90

All Bits Outputs High
VCCM = 6.0V, All Other Pins Open
1.2V ::;: VOUT ::;: VCCM -1.2V

Pump Up

VCCM:S;: 6.0V

Pump Down

1.5

4.0

rnA

-0.30

-0.6

rnA

0.10

0.30

0.6

mA

0

±100

VCCM = 6.0V, VCC1 = 5.25V,
All Other Pins Open

AC Electrical Characteristics VCC =
Symbol
VIN(MIN)(F)

2.5

6.0

nA
mA

5V, TA = 25·C, tr:s;: 10 ns, tf:S;: 10 ns

Parameter
FIN Minimum Signal Input

V
rnA

-0.10

TRI·STATE
ICCM(OPERATE) VCCM Supply Current

0.5
160

Conditions

Min

AM and FM Inputs, O·C ::;: TA :s;: 70·C

Typ

Max

Units

20

100

mV(rms)
mV(rms)

VIN(MAX)(F)

FIN Maximum Sign~llnput

AM and FM Inputs, O·C :s;: TA ::;: 70·C

FOPERATE

Operating Frequency Range
(Sine Wave Input)

VIN = 100 mVrms
O·C ::;: TA ::;: 70·C

RIN(FM)

AC Input Resistance, FM

120 MHz, VIN = 100 mV rms

300

RIN(AM)

AC Input Resistance, AM

2 MHz, VIN = 100 mV rms

1000

CIN

Input Capacitance, FM and AM

VIN = 120 MHz

6

10

pF

tEN1

Minimum ENABLE High
Pulse Width

625

1250

ns

tENo

Minimum ENABLE Low
Pulse Width

375

750

ns

tCLKENO

Minimum Time Before ENABLE
Goes Low That CLOCK Must
BeLow

-50

0

ns

tENoCLK

Minimum Time After ENABLE
Goes Low That CLOCK Must
Remain Low

275

550

ns

tCLKEN1

Minimum Time Before ENABLE
Goes High That Last Positive
CLOCK Edge May Occur

300

600

ns

8·27

I AM
I FM

1000

1500

0.4

8

MHz

60

120

MHz

3

n
n

r-o
en
co
C

U)

AC Electrical Characteristics Vcc =

5V, TA = 25°C, tr

~ 10 ns, t, ~ 10 ns (Continued)
Typ

Max

Units

Minimum Time After ENABLE
Goes High Before an Unused
Positive CLOCK Edge May Occur

175

350

ns

tCLKH

Minimum CLOCK High
Pulse Width

275

550

ns

tCLKL

Minimum CLOCK Low
Pulse Width

400

800

ns

tos

Minimum OATA Setup Time,
Minimum Time before CLOCK
That DATA Must Be Valid

150

300

ns

Minimum DATA Hold Time,
Minimum Time after CLOCK
That DATA Must Remain Valid

400

800

ns

Symbol

Parameter

tEN1CLK

tOH

Min

Conditions

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the -40'C to

+ 85'C temperature range for the 058907.

Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.

Schematic Diagrams (DS8907 AM/FM PLL typicallnputlOutput Schematics)
VCCI

."",}'YI~

ENABLE ONL
DATA IN.

mm.

I

• _ _ _,L

CLOCK IN
(HYSTERESIS)

CHARGE PUMP ENABLE

CHARGE
PUMP OUT

TLlF17511-2

--1

TL/F17511-4
B)T OUTPUTS,

U
"''''''''

TLlF17511-3

TLlF/7511-5
7 DIODE RAIL
FROM VCCM

VCCM
__ T04 DIODE
RAIL

+-""'".,..-

OSCB .....

OSC E.....-

AM
IN

""',..,..-I

...

FM
IN

TL/F17511-6
TL/F17511-7

TL/F17511-8

8·28

Timing Diagrams*
ENABLE vs CLOCK
3V--+-.-_

E1mTI
OV

3V------~r-_

CLOCK
OV------

TLlF17511-9

CLOCK vs DATA
3V~~~~~~

DATA
DV~~~~~0;1

3V-------------r~-------CLOCK

1.5V

DV--------------I

TL/F17511-10

AM/FM Frequency Synthesizer (Scan Mode)

~---'~------------------------~t~l--------------~

DATAIN~
CLOCK
CLOCK PULSE

'---.---'
PLL ADDRESS
1,1

DATA BITS
BITS 1-13, + N CODE (LSB FIRST)
BITS 14-18, OUTPUT BITS

t

t

NEGATIVE TRANSITION ON

POSITIVE TRANSITION ON
£'fiA'BU LATCHES IN NEW
CODE IF PLL IS ADDRESSED.

mill CLEARS PREVIOUS
ADDRESS. CLOCK MUST BE
LOW DURING TRANSITION.

TL/F17511-11

'Timing diagrams are not drawn to scale. Scale within anyone drawing may not be consistent, and intervals are defined positive as drawn.

SERIAL DATA ENTRY INTO THE DS8907
Serial information entry into the OS8907 is enabled by a low
level on the ENABLE input. One binary bit is then accepted
from the OATA input with each positive transition of the
CLOCK input. The CLOCK input must be low for the specified time preceding and following the negative transition of
the ENABLE input.
The first two bits accepted following the negative transition
of the ENABLE input are interpreted as address. If these
address bits are not 1,1 no further information will be accepted from the OATA inputs, and the internal data latches
will not be changed when ENABLE returns high.
If these first two bits are 1,1, then all succeeding bits are
accepted as data, and are shifted successively into the internal shift register as long as ENABLE remains low.
Any data bits preceding the 18th to last bit will be shifted
out, and thus are irrelevant. Oata bits are counted as any
bits following two valid address bits (1,1) with the ENABLE
low. When the ENABLE input returns high, any further serial
data entry is inhibited. Upon this positive transition, the data
in the internal shift register is transferred into the internal
data latches. Note that until this time, the states of the internal data latches have remained unchanged.

These data bits are interpreted as follows:
Data Interpretation
Data Bit Position
Last
Bit 18 Output (Pin 2)
2nd to Last
Bit 17 Output (Pin 1)
3rd to Last
Bit 16 Output (FMI AM) (Pin 20)
4th to Last
Bit 15 Output (Pin 19)
5th to Last
Bit 14 Output (Pin 18)
6th to Last
MSB of -;- N (212)
7th to Last
(2 11 )
8th to Last
(210)
9th to Last
(29 )
10th to Last
(2 8)
11 th to Last
(27)
12th to Last
(26 )
-;- N
(2 5 )
13th to Last
14th to Last
(24)
15th to Last
(23 )
16th to Last
(22)
17th to Last
(21)
18th to Last
LSB of -;- N (20)
Note: The actual divide code is N + 1, i.e., the number loaded plus 1.

8-29

•

,...o
~

en

Typical Application

C

Electronically Tuned Radio Controller System; Direct Drive LED
5V

KEYBDARD
ax 4

SWITCHED

'='
••

+V

34

••

RIS

NSC
CDPs
VSS CONTROLLER
(28 PINS)
MM51170N
5VGND

CLOCK
DATA

J: 1'='
47 pF

FROM

FROM

DIT
100 pF
OSC B

CLDCK

OSC E

C.P.O. ENABLE

DS8907
PLL SYNTHESIZER
(20·PIN)

BIT 14 OUT
BIT 15 OUT

500 kHz

BIT 16 DUT
BIT 17 OUT

50 Hz

BIT 18 OUT
VCCM

UNSWITCHED
B+

VCCI

GND

SWITCHED B+
TO RADIO
TL/F/7511-12

8-30

c
en

Logic Diagram

0)

CD

o

~

AM/FM PLL/Synthesizer (Serial Data 20-Pin Package)
CHARGE
PUMP
OUT

CHARGE (AFC)
PUMP OUT
ENABLE

REF

25 kHz

PHASE
DETECT

VCCM
6V, 1.5 mA
(TYPICAL)

+2

5V
VCc-+

DATA INPUT

~-----tH~

CLOCK

~-----iH~

CONTROL
LOGIC
AND
AooRESS**

BIT 14
OUT

BIT 15
OUT

(2·BIT)

BIT 16
OUT
FM/AM

BIT 17
OUT

BIT 18
OUT

DATA
TL/F/7511-13

'Sections operating from VCCM supply.
"Address (1,1)

8-31

co .-------------------------------------------------------------------------------------,
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CJ)

C

~National

~ Semiconductor
DS8908 AM/FM Digital Phase-Locked
Loop Frequency Synthesizer
General Description
current if the VCO frequency is low. The low noise operational amplifier provided has a high impedance JFET input
and a large output voltage range. The op amp's negative
input is common with the charge pump output and its positive input is internally biased.

The OS8908 is a Pll synthesizer designed specifically for
use in AM/FM radios. It contains the reference oscillator, a
phase comparator, a charge pump, an operational amplifier,
a 120 MHz ECLlI 2 l dual modulus programmable divider,
and a 19-bit shift register/latch for serial data entry. The
device is designed to operate with a serial data controller
generating the necesary division codes for each frequency,
and logic state information for radio function inputs/outputs.

Features
• Uses inexpensive 3.96 MHz reference crystal
• FIN capability greater than 120 MHz allows direct synthesis at FM frequencies
• FM resolution of either 10kHz or 20 kHz allows usage
of 10.7 MHz ceramic filter distribution
• Serial data entry for simplified control
• 50 Hz output for time-of-day reference driven from separate low power VCCM
• 2 open collector buffered outputs for controlling various
radio functions or loop gain
• Separate AM and FM inputs; AM input has 15 mV (typical) hysteresis
• Programmable charge pump current sources enable adjustment of system loop gain
• Operational amplifier provides high impedance load to
charge pump output and a wide voltage range for the
VCO input

A 3.96 MHz pierce oscillator and divider chain generate a
1.98 MHz external controller clock, a 20 kHz, 10kHz, 9 kHz,
and a 1 kHz reference signals, and a 50 Hz time-of-day
signal. The oscillator and divider chain are sourced by the
VCCM pin thus providing a low power controller clock drive
and time-of-day indication when the balance of the Pll is
powered down.
The 21-bit serial data steram is transferred between the frequency synthesizer and the controller via a 3-wire bus system comprised of a data line, a clock line, and an enable
line.
The first 2 bits in the serial data stream address the synthesizer thus permitting other devices such as display drivers to
share the same bus. The next 14 bits are used for the
Pll(N + 1) divide code. The 15th bit is used internally to
select the AM or FM local oscillator input. A high level on
this bit enables the FM input and a low level enables the AM
input. The 16th and 17th bits are used to select one of the 4
reference frequencies. The 18th and 19th bits are connected via latches to open collector outputs. These outputs can
be used to drive radio functions such as gain, mute, AM,
FM, or charge pump current source levels.

Connection Diagram
Dual-In-Llne Package

The PLL consists of a 14-bit programmable 12 l divider, an
ECl phase comparator, an ECl dual modulus (p/p + 1) prescaler, a high speed charge pump, and an operational amplifier. The programmable divider divides by (N + 1), N being
the number loaded into the shift register. The programmable
divider is clocked through a ~ % prescaler by the AM input
or through a ~ 63/64 prescaler by the FM input. The AM input
will work at frequencies up to 15 MHz, while the FM input
works up to 120 MHz. The VCO can be tuned with a frequency resolution of either 1 kHz, 9 kHz, 10kHz, or 20 kHz.
The buffered AM and FM inputs are self-biased and can be
driven directly by the VCO through a capacitor. The ECl
phase comparator produces very accurate resolution of the
phase difference between the input signal and the reference
oscillator. The high speed charge pump consists of a
switch able constant current source and sink. The charge
pump can be programmed to deliver from 75 /-LA to 750 /-LA
of constant current by connection of an external resistor
from pin RpROGRAM to ground or the open collector bit outputs. Connection of programming resistors to the bit outputs
enables the controller to adjust the loop gain for the particular reference frequency selected. The charge pump will
source current if the VCO frequency is high and sink

8-32

Top View

Order Number DS8908N
See NS Package Number N20A

TL/F/5111-1

c
en

Absolute Maximum Ratings (Note 1)

Q)

co

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Storage Temperature Range

Supply Voltage
(VCC1) (VCCM)
(VCC2)
Input Voltage

Operating Conditions

Lead Temperature (Soldering, 4 seconds)

7V
17V

VCC1
VCC2
VCCM
Temperature, TA

7V

Output Voltage

- 65°C to + 150°C

7V

Min
4.5

260°C

Max
5.5
15.0
5.5
+85

VCC1 + 1.5
3.5
-40

Units
V
V
V
°C

DC Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

VIH

Logical "1" Input Voltage

Conditions

Min

Typ

Max

0

10

Units

2.0

=

V

IIH

Logical "1" Input Current

VIL

Logical "0" Input Voltage

IlL

Logical "0" Input Current

Data, Clock, and ENABLE Inputs, VIN

IOH

Logical "1" Output Current
All Bit Outputs, 50 Hz Output

VOH

=

5.5V

1.98 MHz Output

VOH

=

2.4V, VCCM

Logical "0" Output Voltage
All Bit Outputs

IOL

=

5 mA

50 Hz Output, 1.98 MHz Output

IOL

0.5

V

IOL
IOL

=
=
=

250 J.LA

1.98 MHz Output

20 J.LA, TA > 70°C
20 J.LA, TA ::;: 70°C

0.3
0.4

V
V

VOL

VIN

2.7V

=

ICC1

Supply Current (VCC1)

All Bit Outputs High

VCCM Supply Current

VCCM

lOUT

Charge Pump Ougtput Current

3.33k ::;: RpROG ::;: 33.3k
lOUT Measured between
Pin 17 and Pin 18
IpROG = VCC1/ 2 RpROG

ICC2

VCC2 Supply Current

=
=

Op Amp Minimum High Level

VCC1

Op Amp Maximum Low Level

VCC1

CPOBIAS

Charge Pump Bias Voltage
Delta

CPO Shorted to Op Amp Output
CPO = TRI-STATE
Op Amp IOL: 750 J.LA vs -750 J.LA

4.5V, IOH
5.5V, IOL

AC Electrical Characteristics VCC = 5V, T A =
Symbol
VIN(MIN)(F)

Parameter
FIN Minimum Signal Input

Pump Up

-20

Pump Down

-20

J.LA

0.5

V

mA
mA

IpROG

+20

%

IpROG

+20

%

0

11

nA

6.7

11

mA
V

0.6

V

100

mV

25°C, tr ::;: 10 ns, tf ::;: 10 ns

Conditions

Min

VIN(MAX)(F)

FIN Maximum Signal Input

AM and FM Inputs, - 40°C ::;: TA ::;: 85°C

FOPERATE

Operating Frequency Range
(Sine Wave Input)

VIN = 100 mV rms
-40°C::;: T A ::;: 85°C

RIN(FM)

AC Input Resistance, FM

120 MHz, VIN

600

RIN(AM)

AC Input Resistance, AM

15 MHz, VIN

= 100 mV rms
= 100 mVrms

1000

CIN

Input Capacitance, FM and AM

VIN

120 MHz (FM), 15 MHz (AM)

3

tEN1

Minimum ENABLE High
Pulse Width

8-33

-250

VCC2 -0.4

AM and FM Inputs, -40°C::;: T A ::;: 85°C

=

J.LA

4.0

15V

= -750 J.LA
= 750 J.LA

OPVOH
OPVOL

50

160

TRI-STATE®

=

J.LA

2.5

5.5V, All Other Pins Open

VCCM = 5V, VCC1 = 5.5V, VCC2
All Other Pins Open

V

-25

-5

OV

4.5V

ICCM

=

=

J.LA

0.8

I AM
I FM

1000

Typ

Max

Units

20

100

mV(rms)

1500

mV(rms)

0.5

15

MHz

80

120

MHz

n
n
6

10

pF

625

1250

ns

oQ)

co
en

o

CO

en

c

AC Electrical Characteristics VCC =
Symbol

5V, TA = 25°C, tr :5: 10 ns, tf:5: 10 ns (Continued)
Typ

Max

Units

tENo

Minimum ENABLE Low
PuiseWidth

Parameter

375

750

ns

tCLKENO

Minimum Time before ENABLE
Goes Low That CLOCK Must
BeLow

-50

0

ns

Minimum Time after ENABLE
Goes Low That CLOCK Must
Remain Low

275

550

ns

Minimum Time before ENABLE
Goes High That Last Positive
CLOCK Edge May Occur

300

600

ns

Minimum Time after ENABLE
Goes High before an Unused
Positive CLOCK Edge May Occur

175

350

ns

tCLKH

Minimum CLOCK High
PuiseWidth

275

550

ns

tCLKL

Minimum CLOCK Low
PuiseWidth

400

800

ns

tos

Minimum DATA Set-Up Time,
Minimum Time before CLOCK
That DATA Must Be Valid

150

300

ns

Minimum DATA Hold Time,
Minimum Time after CLOCK
That DATA Must Remain Valid

400

800

ns

tENoCLK

tCLKEN1

tEN1CLK

tOH

Conditions

Min

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified min/max limits apply across the -40'C to +85'C temperature range for the D58908.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltage referenced to ground unless otherwise noted. All values shown as
max or min on absolute value basis.

Schematic Diagrams (DS8908 AM/FM PLL TypicallnputlOutput Schematics)
VeCl

VCCI

VCCI

VCCI

:K
I

::15k

'~15k

~~

.~

"""1

TIiABrr

~

CLOCK

~~

~t!1

l:~'""UT'
'""ur
':"

~,

-=

p._-o- -~21k
~

~

.:

27k

-=

TLIF/5111-2

8-34

•

~5.4k

~

~

-=

TL/F/5111-4

~

.. H,

RpROGRAM

-,,",
15k

::15k -=

-

~~

TL/F/5111-3

Schematic Diagrams

(Continued)
2·DIDDE

RAIL

VCCM

--+-

OSC C ~-....

20k

1.9BMHz

OSCO"'-"--4

TL/F/5111-6

TL/F/5111-7
TL/F/5111-5

VCCI

~--~~---------~~~~A~

TLlF/5111-B

8·35

co

oQ)
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U)

Schematic Diagrams (Continued)

C
VCC2

OPAMP
OUTPUT
20k

TLIF/5111-9

Timing Diagrams*
ENABLE vs CLOCK

3V---+-,-OV

3V------------~,~

__

CLOCK

OV-------I
TL/F/5111-10

CLOCK vs DATA
3V~~~~~~

DATA
OV~~~~~';'

fo-- t[l!; ---I---t- tDH

3V--------------------+,---------------1.5V

CLOCK

OV-------------------J

8-36

TL/F/5111-11

c
en

Timing Diagrams*

Q)

co
o

Q)

AM/FM Frequency Synthesizer (Scan Mode)

r

ENABLE.

~'------------------------~I~I--------------------

DATAIN~
CLOCK

~

--~

.

+

CLOCK PULSE

14

~

PLL ADDRESS
1,1

+
15

+
16

+
17

DATA BITS
BITS 1-14, +N CODE (LSB FIRST)
BIT 15, AM/FM SELECT BIT
BITS 16-17, REFERENCE FREQUENCY SELECT BITS
BITS 18-19, OUTPUT BITS

1
NEGATIVE TRANSITION ON

tL

U

\?\---~IJ

+
18

+
19

1

POSITIVE TRANSITION ON
ENABLE LATCHES IN NEW
CODE IF PLL IS ADDRESSED.

ENABLE CLEARS PREVIOUS
ADDRESS. CLOCK MUST BE
LOW DURING TRANSITION.

TL/F/5111-12

'Timing diagrams are not drawn to scale. Scale within anyone drawing may not be consistent, and intervals are defined positive as drawn.

These data bits are interpreted as follows:
Data Interpretation
Data Bit Position
Last
Bit 19 Output (Pin 2)
2nd to Last
Bit 18 Output (Pin 1)
3rd to Last
Ref. Freq. Select Bit(1)17
4th to Last
Ref. Freq. Select Bit(1)16
5th to Last
AM/FM Select Bit 15
6th to Last
(2 13)
7th to Last
(212)
8th to Last
(211)
9th to Last
(210)
10th to Last
(2 9 )
11 th to Last
(28 )
12th to Last
(27)
+N(2)
13th to Last
(2 6)
14th to Last
(2 5)
15th to Last
(24)
16th to Last
(2 3)
(22)
17th to Last
18th to Last
(21)
19th to Last
LSB of + N(2 0)

SERIAL DATA ENTRY INTO THE 058908
Serial information entry into the DS8908 is enabled by a low
level on the ENABLE input. One binary bit is then accepted
from the DATA input with each positive transition of the
CLOCK input. The CLOCK input must be low for the speci·
fied time preceding and following the negative transition of
the ENABLE input.
The first two bits accepted following the negative transition
of the ENABLE input are interpreted as address. If these
address bits are not 1,1 no further information will be ac·
cepted fromt he DATA inputs, and the internal data latches
will not be changed when ENABLE returns high.
If these first two bits are 1,1, then all succeeding bits are
accepted as data, and are shifted successively into the in·
ternal shift register as long as ENABLE remains low.
Any data bits preceding the 19th to last bit will be shifted
out, and thus are irrelevant. Data bits are counted as any
bits following two valid address bits (1,1) with the ENABLE
low. When the ENABLE input returns high, any further serial
data entry is inhibited. Upon this positive transition, the data
in the internal shift register is transferred into the internal
data latches. Note that until this time, the states of the inter·
nal data latches have remained unchanged.

Note 1: See Reference Frequency Select Truth Table.
Note 2: The actual divide code is N + 1, ie., the number loaded plus 1.

Truth Table
Reference Frequency Selection Truth Table
Reference
Frequency

Serial Data
Bit 16

Bit 17

(kHz)

1
1
0
0

1

20
10
9
1

0
1

0

8·37

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Typical Application

C

Additional application notes are located at the back of section 11.

Electronically Tuned Radio Controller System; Direct Drive LED
5V

SWITCHED
B+

POSSIBLE MODULE
INSIDE DOTTED LINE

DISPLAY
KEYBOARD

6x4

••

+V

34

• •

RIS

NSC
COPs
VSS CONTROLLER
(20 PINS)
COP420L

MM5450
DRIVER
(40·PIN)

BRIGHTNESS

L 3 . . . - - - -..

I

L4 .....- - - -..

L5~-----...
LS~_ _ _ _ _ _ _E~N~A~B~LE~________~-+~

G2 ...........
GNO

~:TOA~I~~O~~TECT"

5V GNO

G3 SI CKI SK SO Gl

':"
CLOCK
DATA

.JiiOPF

~

co
..,

...<

~ <

~

c

5Sd[

~

FROM
FMVCO

FROM
AMVCO

Bl l

w
....

II>

<

ffi

DATA
CLOCK

OS8908
PLL SYNTHESIZER
(20·PIN)

OPAMP
OUTPUT
OPAMP
GROUND

TO VCO

RpROG

1.98 MHz
BIT 19 OUT
SO Hz
VCC2

UNSWITCHEO
B+

BIT 18 OUT

}-----

TO RADIO CONTROL CIRCUITS
(MUTE. GAIN, AM, FM, STEREO)

VCCM

PROGRAM
RESISTOR

':"

SWITCHED B+
TO RADIO
TL/F/S111-13

8-38

ro

AM/FM PLL/Synthesizer (Serial Data 20-Pin Package)
1.98 MHz

CQ

n'
c

iir

CQ
~

Q)

osc B

.r-<'

3

50 Hz
OUTPUT

t::::I

L-o

osc C

3.96 MHz
XTAL

10kHz

:20

20 kHz

1kHz

0)

lJ
(0

RPROGRAM
CHARGE

I •

FM
LO

~ PUMP

OUTPUT

VCC2
MOOULUS CONTROL LINE
CLOCK ~

OP AMP
OUTPUT

~~~~LO~~~K~IG~A~T~ED~)~~~Ir-----------------------------------------------------------------"""

OPAMP
GROUNO
DATA ~

•

ENABLE ~

•

I~

~

I

5V~VCCI

5V~VCCM

'Sections operating from VCCM supply.
"Address (1,1)

BIT 19
OUTPUT

BIT 18
OUTPUT

r

GND

TL/F/5111-14

S06ssa

iii

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~ Semiconductor
OS8911 AM/FM/TV Sound
Up-Conversion Frequency SyntheSizer
General Description
The 088911 is a digital Phase-Locked Loop (PLL) frequency synthesizer intended for use as a Local Oscillator (LO) in
electronically tuned radios. The device is used in conjunction with a serial data controller, a loop filter, some varactor
diodes and several passive elements to provide the local
oscillator function for both AM and FM tuning.

crystal filtering is mixed (externally) with a reference frequency provided by the PLL to obtain a 450 kHz second IF
frequency. The OS8911 derives the 450 kHz second IF by
mixing an 11.55 MHz first IF with a 12.00 MHz reference
frequency.
FM and WB (weather band) tuning is done using the conventional down conversion approach. Here the yeO signal
is buffered to produce the LO signal and then mixed on chip
with the RF signal to obtain an IF frequency at the MIXER
output pins. This IF frequency is typically chosen to be 10.7
MHz although placement at 11.50 MHz can further enhance
AM mode performance and minimize IF circuitry.

The conventional superheterodyne AM receiver utilizes a
low IF or down conversion tuning approach whereby the IF
is chosen to be below the frequencies to be received. The
OS8911 PLL on the other hand, utilizes an up-conversion
technique in the AM mode whereby the first IF frequency is
chosen to be well above the RF frequency range to be
tuned. This approach eliminates the need for tuned circuits
in the AM frontend since the image, half IF, and other spurious responses occur far beyond the range of frequencies to
be tuned. Sufficient selectivity and second IF image protection is provided by a crystal filter at the output of the first
mixer.

The PLL provides phase comparator reference frequencies
of 10, 12.5, 25, and 100 kHz. The tuning resolutions resulting from these reference frequencies are determined by dividing the reference by the premix modulus. Table II shows
the tuning resolutions possible.

A significant cost savings can be realized utilizing this upconversion approach to tuning. Removal of the AM tuned
circuits eliminates the cost of expensive matched varactor
diodes and reduces the amount of labor required for alignment down from 6 adjustments to 2. Additional cost savings
are realized because up-conversion enables both the AM
and FM bands to be tuned using a single Voltage Controlled
Oscillator (YCO) operating between 98 and 120 MHz. (The
2 to 1 LO tuning range found in conventional AM down conversion radios is reduced to a 10% tuning range; 9.94 MHz
to 11.02 MHz).
Up-conversion AM tuning is accomplished by first dividing
the yeO signal down by a modulus 10 to obtain the LO
signal. This LO in turn is mixed on chip with the RF signal to
obtain a first IF at the MIXER output pins. This first IF after

The OS8911 contains the following logic elements: a voltage controlled oscillator, a reference oscillator, a 14-bit programmable dual-modulus counter, a reference frequency divider chain, a premix divider, a mixer, a phase comparator, a
charge pump, an operational amplifier, and control circuitry
for latched serial data entry.

Features
• Oirect synthesis of LW, MW, SW, FM, and WB
frequencies
• Serial data entry for simplified processor control
• 10, 12.5, 25, and 100 kHz reference frequencies
• 8 possible tuning resolutions (see Table II)
• An op amp with high impedance inputs for loop filtering
• Programmable mixer with high dynamic range

8-40

BIT Outputs: The open-collector BIT outputs provide either
the status ot shift register bits 22, 23, and 24 or enable
access to key internal circuit test nodes. The mode for the
bit outputs is controlled by shift register bits 20 and 21. In
operation, the bit outputs are intended to drive radio functions such as gain, mute, and AM/FM status. These outputs
can also be used to program the loop gain by connection of
an external resistor to IPROG. Bit 24 output can also be
used as a 300 millisecond timer under control ot shift register bit 19. During service testing, these pins can be used for
the purpose of either monitoring or driving internal logic
points as indicated in the TEST MODES description under
Table V.

Connection Diagram
Plastic Chip Carrier
0...

~

X

:::IE

/

N

it J.

c
:z

U

..... <:::IE
0
0...
U

N

N

CD

0

I I I Ico I,... I
T
.....

U>

N

t.lIXER- 5

25 I-CPO

t.lIXER- 6

24 --IPROG

GNDL- 7

23 -VCC2

VCCL- 8

22 -GNDI

ENABLE- 9

21 i-VCC 1

CLOCK- 10

VCOb and VCOe: The Voltage Controlled Oscillator inputs
drive the 14-bit programmable counter and the premix divider. These inputs are the base and emitter leads of a transistor which require connection of a coil, varactor, and several
capacitors to function as a Colpitts oscillator. The VCO is
designed to operate up to 225 MHz. The VCO's minimum
operating frequency may be limited by the choice of reference frequency and the 961 minimum modulus constraint of
the 31/32 dual modulus counter.

20 -B1T24

DATA- 11

19 -BIT23
~

~

~

t !u~uu~
I ! ~ I

:!

~

~

~

~

:I::I:

~~>c..>t5~~lii

RF+ and RF-: The Radio Frequency inputs are ted differentially into the mixer.

TL/F/7398-8

Top View

IMXR: The bias current for the mixer is programmed by connection of an external resistor to this pin. The total mixer
output current equals 4 times the current entering this pin.
MIXER and MIXER: The MIXER outputs are the collectors
of the double balanced pair mixer transistors. They are intended to operate at voltages greater than VCC1.
OSCb and OSCe: The Reference Oscillator inputs are part
of an on-chip Pierce oscillator designed to work in conjunction with 2 capacitors and a crystal resonator. The DS8911
requires a 12 MHz crystal to derive the reference frequencies shown in Table II.

Order Number DS8911V
See NS Package Number V28A

Pin Descriptions
VCC1: The VCC1 pin provides a 5V supply source for all
circuitry except the reference divider chain, op amp and mixer sections of the die.
VCC2: The VCC2 pin provides a 12V supply source for the
Op amp.
VCCL: The VCCL pin provides an isolated 5V supply source
for the premix divider and mixer functions.

The 12 MHz OSC signal is also used externally as the 2nd
AM LO to obtain a 450 kHz 2nd IF frequency in the AM
mode.
2 MHz: The 2 MHz output is provided to drive a controller's
clock input.

VCCM: The VCCM pin provides a 5V supply source for the
reference oscillator and divider chain down through the 50
Hz output, thus enabling low standby current for time-of-day
clock applications.
GND1, GND2, GNDL and GNDM: Provide isolated circuit
ground for the various sections of the device.

50 Hz: The 50 Hz output is provided as a time reference for
radios with time-ot-day clocks.

DATA and CLOCK: The DATA and CLOCK inputs are for
serial data entry from a controller. They are CMOS inputs
with TTL logic thresholds. The 24-bit data stream is loaded
into the PLL on the positive transition of the CLOCK. The
first 14 bits of the data stream select PLL divide code in
binary form MSB first. The 15th through 24th bits select the
premix modulus, the reference frequency, the bit output
status, and the test/operate modes as shown in Tables I
through V.

IPROG: The IPROG pin enables the charge pump to be
programmed trom 0.25 mA to 1.0 rnA by connection of an
external resistor to ground.
CPO: The Charge Pump Output circuit sources current if the
VCO frequency is high and sinks current if the VCO frequency is low. The CPO is wired directly to the negative input of
the loop filter op amp.
OP AMP: The OP AMP output is provided for loop filtering.
The op amp has high impedance PMOS gate inputs and is
wired as a transconductance amplifier/filter. The op amp's
positive input is internally referenced while its negative input
is common with the CPO output.

ENABLE: The ENABLE input is a CMOS input with a TTL
logic threshold. The ENABLE input enables data when at a
logic "one" and latches data on the transition to a logic
"zero".

8-41

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......

......

~ r---------------------------------------------------------------------------~

en
co
en
C

Reference Tables
cycle the timer's BIT 24 output will finish out the 300 ms
pulse. Readdressing the device with bit 19 "HI" before the
timer finishes its cycle will extend the BIT 24 output pulse
width by 300 ms. Addressing should be performed immediately after the 50 Hz output transitions "HI". BIT 24's output
state is not guaranteed during the first 300 ms after Vee
power up as a result of a timer reset in progress.
1

TABLE I
Bit 15

Premix Modulus

0

+1

1

+10

TABLE V

TABLE II
Bit
16

17

0

0

0

Reference
Frequency

+1 Premix

+10 Premix

20

21

FUNCTION OF
PINS 3, 4, & 5

10 kHz

10 kHz

1 kHz

0

0

Status of Bits 22-24

1.25 kHz

0

1

Test mode 1

0

Test mode 2

1

Test mode 3

1

12.5 kHz

Bit

Tuning Resolution

12.5 kHz

1

0

25 kHz

25 kHz

2.5 kHz

1

1

1

100 kHz

100 kHz

10 kHz

1

TEST MODE OPERATION
Test Mode 1: Enables the BIT output pins to edge trigger
the phase comparator inputs and monitor an internal lock
detector. BIT 22 negative edge triggers the reference divider input of the phase comparator if the reference divider
state is low. BIT 23 provides the open collector ORing of the
phase comparator's pump up and down outputs. BIT 24
negative edge triggers the N counter input of the phase
comparator if the N counter state is preconditioned low.

TABLE III
Bit 18

Mode

0

Normal Operation·

1

Production Test
Mode Only

'The user should always load Bit 18 low.

Test Mode 2: Enables the BIT outputs to clock the programmable N counter, monitor its output, and force either its
load or count condition. BIT 22 provides the N counter output which negative edge triggers the phase comparator and
which appears low one N counter clock pulse before it reloads. BIT 23 positive edge triggers the N counter's clock
input if the prescaler's output is preconditioned HI. BIT 24
clears the N counter output so that loading will occur on the
next N counter clock edge.

TABLE IV
Bit 19

Timer

0

Bit 24 Status

1

Bit 24 for 300 ms

TIMER OPERATION
The timer function is provided for use as a retriggerable
"one shot" to enable muting for approximately 300 milliseconds after station changes. The timer is enabled at bit 24's
output if the normal operating mode is selected (shift register bits 20 and 21 = "LOW") and shift register bit 19 data is
latched as a "HI". The timer's output state will invert immediately upon latching bit 19 "HI" and remain inverted for
approximately 300 milliseconds. If the user readdresses the
device with bit 19 data "LOW" before the timer finishes its

Test Mode 3: Enables the BIT outputs to clock the 50 Hz
and 10kHz reference dividers and monitor the reference
divider input to the phase comparator. BIT 22 positive edge
clocks the 10kHz reference divider chain if the 10kHz output is preconditioned HI. BIT 23 positive edge clocks the 50
Hz divider chain. BIT 24 is the reference divider negative
edge trigger input to the phase comparator.

8-42

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
VCCM
7V
VCC1
15V
VCC2
Input Voltage
7V
Output Voltage
Logic
7V
Op Amp and Mixer Outputs
15V
ESD Sensitivity
1000V
DC Electrical Characteristics
Symbol

Storage Temperature Range
Lead Temp. (Soldering, 10 seconds)

- 65·C to + 150·C
300·C

Operating Conditions
VCCM
VCC1
VCC2
Temperature, TA

Min
3.5
4.5
7.0
-40

Mixer ISlAS
(Mixer + Mixer Current) 1

Max
5.5
5.5
12.0
+85

Units
V
V
V
·C

20

mA

(Notes 2 and 3)

Parameter

Test Conditions

Min

Typ

Max

Units

VIH

Logic "1" Input Voltage

VIL

Logic "0" Input Voltage

IIH

Logic "1" Input Current

VIN = 5.5V

II

Logic "1" Input Current

IlL

Logic "0" Input Current

VOH

Logic "1"
2MHz
Output Voltage

IOH = -20/LA

VCCM-0.3

V

IOH = - 400 /LA

VCCM-2

V

IOH = -1.0 mA

VCC2- 1.5

V

OpAmp
VOL

Logic "0"
2MHz
Output Voltage

V
0.8

V

10

/LA

Data, Clock and Enable Inputs, VIN = 7V

100

/LA

Data, Clock and Enable Inputs, VIN = OV

-10

/LA

IOL = 20/LA

0.3

V

IOL = 400/LA

0.4

V

IOL = 250/LA

0.3

V

Bit Outputs IOL = 1 mA

0.3

V

OpAmp

IOL = 1.0 mA

1.5

V

Op Amp 1/0 Shorted, VCC1 = 5.5V, VCC2 = 12V,
CPO = TRI-STATE®, Op Amp IOH vs. IOL Applied

50 Hz

VSIAS

Op Amp Input VI:l.

ICEX

High Level
Output Current

IcPO

2.0

200

mV

Bit Outputs VCC1 = 4.5V, Vo = 8.8V

100

/LA

50 Hz

VCCM = 3.5V, Vo = 5.5V

10

/LA

Mixers

VCCL = VCC1 = 4.5V, Vo = 12V

100

/LA
%

Charge Pump Program
Current

0.25 mA < IcPO < 1.0 mA
21PROG = VCC1 /R pROG,
Measured IpROG to CPO

Pump-up

-30

21PROG

+30

Pump-down

-30

21pROG

+30

%

0

100

nA

TRI-STATE
ICCM

VCCM Supply Current
(Static)

VCCM = 5.5V, OSCC = High

0.5

1.0

mA

ICC1 +
ICCL

VCC1 + VCCL
Supply Current

VCC = 5.5V, Bits Hi, IMXR and IpROG Open

25

35

mA

ICC2
Mixer
ISlAS

VCC2 Supply Current

VCC2 = 12V

1.5

2.5

mA

Mixer + Mixer
Current (Note 4)

VCC1 = VCCL = 5.5V, Mixer = Mixer = 12V

41MXR

+25

%

RFIN

Mixer Input Max
Signal Level

Mixer ISlAS = 20 mA
RF + or RF - Signal Level

-25

300

mVrms

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range",
they are not meant to imply that the device should be operated at these limits.
Note 2: Unless otherwise specified, minImax limits apply across the -40'C to +85'C temperature range.
Note 3: All currents into device pins are shown as positive, out of device pins as negative, all voltage referenced to ground unless otherwise noted. All values
shown as maximum or minimum on absolute value basis.
Note 4: Total mixer output current (Mixer + MiXSr) '" 4 times the current into the IMXR pin.

8-43

AC Electrical Characteristics (Note 2)
Symbol

Parameter

Conditions

Typ

Min

Max

Units

tr

20%-80% Rise Time

200

ns

tf

80%-20% Fall Time

200

ns

DATAsu

Data Setup Time

100

ns

DATAH

Data Hold Time

100

ns

ENsu

Enable Setup Time

100

ns

ENH

Enable Hold Time

100

ns

ENpw+

Enable Positive Pulse Width

200

ns

CLKpw+

Clock Positive Pulse Width

200

ns

VCC1 = 4.5V to 5.5V

CLKpw-

Clock Negative Pulse Width

VCO fmax

VCO Max Frequency

See Typical Wiring Diagram

OSCfmax

Reference Oscillator
Max Frequency

VCCM = 3.5V

ns

200
225

20

MHz
MHz

12

Timing Diagram

I r;:'

vee l ENABLE
ov
vee1 CLOCK
OV
Vee1
OV

DATA

.1- CLKpw_ -I ~ iCLKpw+

ENH -

h.ENsu
1.5V
I

-1 r-tR,t

-I-

~
1

Jf"

~
1-

fDAT~=1DAT"

f

1.5~X

TL/F/7398-10

MICROWIRETM Bus Format
DATA

J'i'1..2.J

CLOCK

----1UL

1

0

1

0

o

I

1

1

I0

0

1

0

0

r-J

ENABLE

BIT 22 OUTPUT

I

7

7

7

7

7

71

BIT 23 OUTPUT

I

7

7

7

7

7

71

BIT 24 OUTPUT

Z Z Z Z Z Z Z

BIT POSITION

F300MS=L

I' + ""31'11JJLL~
MSB

N CODE

LSB

2

PREMIX SELECT
RErERENCE rREQUENCY SELECT
PRODUCTION TEST BIT

BIT OUTPUTS
TEST MODE CONTROLS
TIMER CONTROL
TL/F17398-19

8-44

cen

TABLE VI. 058911 Tuning Characteristics
Mode

IF
Frequency
(MHz)

Tuning
Range
(MHz)

VCO
Range
(MHz)

Premix
Modulus

Q)

Tuning
Resolution
(kHz)

Reference
Frequency
(kHz)

Image
(MHz)

LW
MW
SW
FM
WB

11.55/.450

.145-.290

112.4-114.1

10

10

11.55/.450

.515-1.61

99.4-110.2

10

10,12.5,25,100

1,1.25,2.5,10

11.55/.450

5.94-6.2

53.5 to 56.1

10

10,12.5,25

1,1.25,2.5

28-30

87.4-108.1

98.1-118.8

1

10,12.5,25,100

10,12.5,25,100

109-130

10.7

162.4-162.6

151-152

12.5,25

12.5,25

140-142

TV1

10.7

59.75-87.75

70.45-98.45

25

25

81-109

TV2

10.7

179.75-215.75

169.1-205.1

25

25

158-194

10.7

22-23

Input and Output Schematics

1

1
'----f---+-- PREMIX

'---~-----~--4---PREMIX

GNDL

4 (V - 0.8)

R", - - - - 2 0 0 n
MIXER I BIAS
I IIXR

RESISTOR CALCULAnON

TL/F/7398-11

TL/F/l398-12

8·45

21-23

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.....
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.....
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Q

Input and Output Schematics (Continued)
---t...---I 14 Veet.l -

CRYSTAL
OSCILLATOR

----t~

--t----+-I

2t.1Hz
OUT

2 MHz

OUTPUT
BUFFER

TLIF17396-14

TLlF17396-13

- - - -.....-

...-1 22

--'--~~---I

Vee 1

22

Vee 1
PIN 18 BIT 22
PIN 19 BIT 23
PIN 20 BIT 24

PIN 9 ENABLE
PIN 10 CLOCK
PIN 11 DATA

(ONE OF THREE)

INPUT
BUFFERS ESD
(ONE OF THREE)
-.-.-.....----.-.-1 22

GND1
GND1

TL/F17396-16

TLlF17398-15

vcc1

0--.....-----.

Pii ----+---4

Pii-

GND1

22

1------'---'

TL/F17396-17

8-46

TL/F 17396-16

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Logic Diagram

co
.......
.......

058911 PLL Synthesizer
OSCb

OSCe

MIXER MImI

Vccz
OP AMP
OUTPUT
VCOb
VCO.

' - - - - - - 0 CPO
......- - - - - - - o l p R O G

1-+-00--0 50HZ

81T liT BIT
22 23 24

OATA ClK EN

TL/F17398-4

Note 1: The 14 bit programmable N counter is a dual modulus counter with 31/32 prescaler. The minimum continuous modulus of the N counter is
961. (There are a limited number of valid modulus codes below 961.)

Typical Application Diagram
AM/FM ETR Radio Application
ANTENNA

DS8911
PLL

SERIAL DATA

MICROPROCESSOR

2 MHz CLOCK

AM
AUDIO

FM IF &
DETECTOR

FM
AUDIO
TLlF17398-5

8-47

,....

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en

Wiring Diagrams

c

Configuration Using PLL and First Mixer Functions

VTUNETO

RFFRONTEND

R21

R22

UK

68

15pf

05

Rll
12K

Fl2
FlIT(OPTIONAq]L)

T
RI2

22,.H

FROG

T

C2.-= :.~~

-=

2.

~Pf

RI3
23
DSa911

lOOCI!

o.o~

27 CI"

h
-l-

AWFOOT

22
(BOTTOW VlW)

5V

-= -=

1

CI8

o.o~
BIT2.

10

O.Q~

CLOCK

t--~--t---cos

T2

wo cos 
1

Tl

=

w02T2

= Ko Kv ( -woT1-1)
Nw02
woT2+1

Cl
where 0

wo

= desired phase margin
=

loop natural frequency

:::: closed loop bandwidth

Note: DS8909 op amp required C3 :::: 1000 pF for compensation.

TL/F/5269-10

FIGURE 8. Third Order Type 2 Loop

100

r--r-

80 b:::
60

'"

'0

40

Z

<

CI

20

~

r-

r--

f-

I-

VHF loop, running at 100 MHz, ref

180

~

16D ."

I'

1"'1

I"""

~

~

::z:

140

~

-40
100

Ko

=

o=

~

-20
10

=

2.5 MHzlV
400/LA

"""'4;-

=

=

=

10 kHz

15.7 Mrad/seclV

31.8/LA/radian

100 MHz
N = 10 kHz = 10,000, wO ~ 27T /. 100 Hz

"0
120 ~

I""'~

Kv

45' (desired phase margin)

T2

= 6.6 ' 10

T1

=

3.84 ' 10- 3 sec

Cl

=

0.3 JiF

4

sec

so Rl = Tl/Cl = 13 kll

1DOO

C2

Wo

=

T2/Rl

=

0.05/LF

TLIF /5269-11

FIGURE 9. Example of Gain and Phase Calculation

8-53

DUAL-MODULUS COUNTING RANGE LIMITATIONS

The last equation is in the final form used internally by the
DS8906/7/8. The equation indicates that, if N is loaded into
the device, it will solve for N + 1.

• Minimum count limitations
• Maximum count limitations

The minimum continuous N modulus (code) the equation
dictates should occur when A = B. B maximum = 63 implies A = 62, 8 = 63 should be an illegal N + 1 code (N +
1 = 3969). However, because this is just inside the lower
FM band limits, extra circuitry was added to enable this particular code's operation. The actual minimum N + 1 ~de
for these PLLs thus becomes the case when A = 61, 8 =
61, N + 1 minimum = 3907. There are legitimate N + 1
codes below this 3907 value, however, they are not continuous. (Le., Starting at 3907 and counting down, one additional code is in error every 63 codes. Thereafter, these erroneous codes are the cases where A < B.) The sequence of
illegal codes is shown in Figure 10.

The DS890617 /8 series PLLs utilize a dual-modulus counting scheme internally based on a 63/64 prescale modulus
in FM mode in order that all of the U.S. FM frequency assignments could be reached using a 25 kHz reference. The
counter modulus N = 64A + 8 where 8 is the 6 least
significant bits of N and A is the 7th and greater significant
bits of N.

N = 64A + 8
N = 64A + 63 - 8 (8 = 63 - B)
1 + N = 64A + 63 + 1 - 64B + 63B
1

+

N = 64(A

+

1 - B)

+ 638

Loaded Value
ofN

A

3906
3905
3904
3903

61
61
61
60

•
•
•

•
•
•

3843
3842
3841
3840
3839

60
60
60
60
59

•
•
•

•
•
•

3780
3779
3778
3777
3776
3775

59
59
59
59
59
58

•
•
•

•
•

3717
3716
3715
3714
3713
3712
3711

58
58
58
58
58
58
57

58
59
59
60
61
63

illegal
illegal
illegal
illegal
illegal

o

OK

3718
3718
3718
3718
3718
3718
3712

•
•
•

•
•
•

•
•
•

•
•
•

•
•
•

Status

61
62
63

OK

Actual Locked
N + 1 Value

OK

3907
3907
3907
3904

•
•
•

•
•
•

60
61
62
63

illegal
illegal
illegal

o

OK

3844
3844
3844
3844
3840

•

•
•
•

•
•
•

59
60
61
62
63

illegal
illegal
illegal
illegal

o

OK

3781
3781
3781
3781
3781
3776

•

•
•

o
•

•
•

illegal
illegal

OK

OK

OK

•
•
•

FIGURE 10. FM Mode Dual-Modulus Counting Below the Minimum Continuous N Code of 3906

8-54

»

the marketplace. Figure 12 shows the block diagram of
such a radio. In this application the following performance
relating to the PLL tuning system is realized.

Maximum code limits for these dual-modulus PLLs are determined by the N code bit length. The OS8906 and OS8908
have a 14-bit N counter allowing 16,383 counts. The
OS8907 has a 13-bit N node length, allowing a maximum N
count of 8,191. See Figure 11 for table operating ranges of
the OS8906, OS8907 and OS8908 PLLs.
CONCLUSION
The major application for the OS890617 /8 PLLs are synthesizers for AM-FM radios, and have been widely accepted in

Product

Input

PLL Loop Bandwidth

300 Hz

Reference Frequency Sidebands

>60dB

Signal-to-Noise Ratio
AM: 30% modulation
FM: 22.5 kHz deviation

>50dB
>55dB

Switching Speed (one channel)

fiN (Hz)

Ref
(Hz)

Min·

Max

OS8906

AM

500

24.5k

8.193M

FM

12.5k

48.8375M

120M

OS8907

AM

10k

490k

15M

FM

25k

97.675M

120M

OS8908

AM

1k

49k

15M

9k

441k

15M

10k

490k

15M

20k

980k

15M

1k

3.907M

15M

9k

35.163M

120M

10k

39.07M

120M

20k

78.14M

120M

FM

<1.5 ms

'The minimum frequency shown is obtained when the minimum continuous N code is
utilized and it assumes the edge rates > 20V / Ils.

FIGURE 11. Product Operating Frequency Range

MM545D LED
COPS47D VF
MM5445
....-'"T"-.... COPS472 LCD

MM5452
TL/F/5269-12

FIGURE 12. AM·FM Digitally Tuned Radio System

8·55

z
W
w

U1

.

,...

~

it)

z



0

u

>

x

SERIAL DATA

:i

2MHz CLOCK

DS8911
PLL

AM AUDIO

FM IF AND DETECTOR

FM AUDIO
TL/F/9449-2

FIGURE 2. Up-Conversion Electronically Tuned Radio
THE 058911 IN AN ACTUAL RECEIVER APPLICATION

Shown below is a block diagram of the DS8911 demonstration radio.

AM AUDIO

FM AUDIO

AUDIO
AMP

RIGHT

POWER
CONTROLLER

AM FM
SUPPLY

12V IN
TLIF/9449-3

FIGURE 3. Block Diagram of 058911 Up-Conversion Radio

8-57

THE AM AND FM FRONT ENDS

OS8911. Note that C7 and L2 perform a low pass function
to limit the response of the RF amp to about 2 MHz. 010 is
connected directly across the antenna input and is activated
by the AGC circuit to limit very large received signals.

The AM RF amplifier, shown in Figure 4, is an untuned JFET
input cascode RF amplifier. With the exception of there being no tuned circuits, this is a standard configuration. The
output of the cascode amplifier, 01 and 02, is further amplified by 03, which in turn drives a low impedance (::::: 50n)
wide band transformer, T1. Transformer T1 provides a 2 to
1 impedance step down to drive the differential inputs of the

The typical gain of the AM RF block is 20 dB (antenna to 03
collector). Most of this gain is lost in the low pass filter and
wide-band transformer, T1. The net gain from antenna to
the input of the OS8911 is about 8 dB.

r---~~--~~---'-----'----------------08VA

r-+To F'M RF'
...LCll

•Hi
TlO
33).LH

OTo Tl

TLIF /9449-4

FIGURE 4. 058911 Untuned AM RF Front End
AGC for the FM RF is applied to the second gate of the dual
gate mosfet, 07 (Figure 5). To insure pinch off action during
AGC, R68 biases the source of 07 so that the source cannot drop below about 650 mV. Note that R49 is used in the
drain of 07. This is designed to limit gain and add circuit
stability. The approximate gain of the FM RF amplifier is
10 dB.

The FM RF amplifier is shown in Figure 5. It is of conventional design, using two varactor diodes, 01 and 02, for
tuning. These diodes and the LO varactor, 01, are driven
directly by the OS8911 Mixer/Synthesizer's tuning voltage
output (OPAMP OUT).
Note that the wide-band transformer, T1, shown in Figure 6,
serves as both the AM and FM differential input for the
OS8911 mixer. C11 and L2 (Figure 4), are used as isolating
devices between the AM and FM front ends.

~--------------~'---------012VB

R112
F'MAGCo-----------~~----.

C70

o.05I

A~~------~~--~--~--~~~+-----4
3.9pF'

111

R66
47K

R52

• 39 pF' on bottom
of board

47K

L-------------~~-------1~-OVTUNE

To AM RF
TL/F/9449-5

FIGURE 5. FM RF Front End
8-58

.

l>
THE 058911 MIXER AND IF FILTER SECTION

RF inputs of the mixer can be de-biased which results in
passing the internally generated LO signal to the mixer output pins.

A mixer is provided on the OS8911 IC for both the FM conversion to 11.50 MHz and the AM first conversion to 11.55
MHz. The 2nd AM conversion to 450 kHz is provided by the
mixer within the AM IF IC. If other partitioning constraints
require that the first mixer be external to the OS8911, the

The OS9811 rviixerlSynthesizer section is shown in Figure

6.

R!!r:-

VlUNE TO
RF FRONT END
U

1
-=

C.I

22jU1

C.I

CII
"pl

28
CPO

RI2
••7K
12V

22I'H
RU

YCC2

3.3K
R22

UK

~ ~-=
28

I

25
24
ICI
23

IOD CI3

C.O~
RU
SV

PROt

27



~

It should be noted that T4 could be replaced by a ceramic
resonator centered around 11.50 to 11.55 MHz with a bandwidth of several hundred kHz. Transformer T5 could be
eliminated and T6 replaced with a 450 kHz resonator to
produce a minimum tuned circuit design.

~

t:;

J.

§

u

g:

:::

II>
0

~

><

2

~

>~

0

:::

2

§

~

><

~

~

~

~

-=AM

R29
220
R24

01
C27

C32
470

C28

O.O~

12 MHz
0

11'

O.~

AM OUT
C37

R26 _
100 -

-=
R30
C34

-=

AM MONO OUT

IO.02

8VA

68

.Jl7 ",F
TL/F/9449-8

FIGURE 8. AM IF Circuitry

8-60

:J>
Detected audio is available at pin 14 (Mono AM out test
point). AGC is generated internal to the LA 1130, buffered by
08 and applied to 010, located in the AM front end.

Device IC7, shown in Figure 10, is a Motorola MC13020P,
an AM stereo decoder designed to decode the C-Ouam AM
stereo format. Because this chip needs a relatively high level 450 kHz IF signal to operate, transistors 04 and 05 boost
the IF signal from T6 and apply it to pin 3 of IC7.
The FM stereo decoder, shown in Figure 11, is IC8, an
LM 1800. This device performs the FM stereo multiplex decoding. This circuit is standard and used in numerous consumer applications, therefore is mentioned only briefly.
The audio output section, shown in Figure 12, consists of
two LM386 devices, IC3 and IC11. These are used simply to
drive a pair of monitor loud speakers. No special de-emphasis of the audio has been done in this evaluation board. This
should be taken into account if performance measurements
are done on this board.

THE FM IF SECTION
The FM IF filtering is done by FL3 (Figure 6) and FL4 (Figure
9) which precede the IF amplifier chip IC6, an LM3089. FM
quadrature detection is done on chip. External inductor T9 is
adjusted for correct FM demodulation. Audio output is made
available on pin 6 (FM mono out test point). This is fed to
the stereo decoder IC8. (Figure 11)
THE STEREO DECODER SECTION
The stereo decoders are a standard configuration with their
outputs resistively summed into the dual volume control potentiometer, Rvol.

Z

....•
U1

N

12VB

R60
100
n.t AGe

16

r
T9

C76
0.05I

C74
o.OlI
15

12

14

11

10

L7
18JJH

IC8
3089

R62
UK

n.tIN~
FU

T-

330

...- - - - - - - - o n . t MONO OUT

C73
Io.05

~-------_orMOUT

TLIF/9449-9

FIGURE 9. FM IF Circuitry

•
8-61

AN·512

Cl0611+
0.47
Cl07
0.47

rL5

R84

0

1 •

3300+1£,104
33J.1F

Cl02
3300

R91

R88

Rl00

lOOK
R89

2.7K

220K
20

19

18

17

16

15

14

13

12

11

430 .J£.110
]I;7 J.lF

8VA

t.lC13020P

IC7
R41
4.7K

R43
470

2

3

4

5

7

.Cl141cl15

I\)

0.1

m
_C123
3300

.J}OJ.lF

10

8

CD

To.l

Lu

IT

L...------_O RIGHT CH OUT
L...---------~O

LEFT CH OUT

TL/F/9449-10

FIGURE 10. AM Stereo Decoder

12VB
R72

19 KHz
R70
5K

C86
390

R75
560

R71
22K

16
C125
0.033

15

14

13

IC8
3

4

IC77

I

8

C92
0.1

'-----+---------0

RIGHT CH OUT
' - - - - - - - f - - - - - - - - - O O L E F T CH OUT

C90
I2200
R74
3.9K

I220

7

5

C91
0.1

INO

10

Lt.l1800
2

C85
0.1

11

12

C93
022

IO.

TL/F/9449-11

FIGURE 11. FM Stereo Decoder
12V
r - - - -....-+-I
....._ _....,j_ _....,j....._ . . . . . .

8
IC3

R80
LEFT CH AM o--"Mr----'
47K

5

7

3

~ LEFT CH
470).LF

OUT

£
.1

R82
10

LM386

2

C96

4

R77

LEFT CH Ft.I o--\M--"
47K
R78
lOOK DUAL STEREO

TLlF/9449-12

12V

£
.1

R83
10

LM386

R81
RIGHT CH AM o--"Mr----,
47K

2

R76
RIGHT CH FM 0--1\"",--"
47K
R79

3

4

lOOK DUAL STEREO
TL/F/9449-13

FIGURE 12. DS8911 Audio Output Circuitry

8-63

POWER SUPPLIES

Key Functions.

The evaluation board is designed for 12 VdC nominal operation. The power to various sections is controlled by the microcontroller via 011, 012, 013, and 014 shown in Figure
13. On board regulation is provided by IC4, and 8V regulator
(used for the signal circuits), and IC5, a 5V regulator (used
for the logic circuits). The 12V power is used to operate the
rest of the circuitry. No provisions have been made on the
board for automobile load dump protection.

AM/FM: This key switches between the AM and FM bands.
If the key is pressed while in FM, the station is first stored
internally and then the band is changed to AM, recalling the
last station played.

APPENDIX

Fast tune up (t t), tune down (J. J.): Holding this key
down steps the frequency up or down repetitively for speedy
tuning. There are upper and lower tuning limits which vary
according to what reference frequency the OS8911 is using.

Note: An "An will appear in the left digit location on the display while in the
AM band, and no letter will appear for the FM band.

Tune up ( t ), tune down ( J.): Steps the tuned frequency by
one reference increment at each key stroke.

Operating Instructions for the DS8911
Application Board
The OS8911 AM/FM radio application board contains a
built·in COPS controller which is programmed to send a 24bit serial data stream to the OS8911 each time a key is
pressed on the 4 by 4 keypad. Additionally, new data is sent
to the display.

STO 1/2/3: A station may be stored by pressing the STO
key and then the desired store location 1, 2 or 3 . An "S"
will show up in the left digit space prompting the user for a
store location.
A station may be recalled by directly pressing the store 1, 2
or 3 location. FM stations will be recalled while in the FM
band and AM stations will be recalled while in the AM band.

Power up.
Upon power up the radio will tune 98.5 MHz in the FM band.
The store keys are preset to tune this frequency in the FM
band and 810 kHz in the AM band.

~----------------~12V

12V IN O-....----4I>-4~......

....---._---~~--o8V

~

8VA

12VB

Rl0S
AM/F'M BAND
SWITCH CONTROL o----V\I\_--I
3.9K

~---'----------05V

TL/F/9449-14

FIGURE 13. Power Supply

8-64

Circ~itry

Column

Row

Function

M
N

D
D
D
D
E
E
E
E
P
P
P
P

STO
1
3
3
AMFM
LO
TIM
REF

G
F
M
N

G
F
M
N

G

CXl

en
U1

F
M
N

Q

G

Q

F

Q

Q

At.I/FM

+5V

ENABLE
(LEFT DISPLAY)
-"- DATA
DATA

NSt.l4000A
6

~, 1N4001

~4

CLOCK

ClK
EN

2t.1Hz

I~
822
823
824
STEP UP
SCAN UP
SCAN DOWN
STEP DOWN

IN3
IN2
IN1
INO
l3
l2

11

N

c

::.:::
Vl

10
9

l

12

00
4_BL4
KEYPAD
GRAYHlll
#87883-201

0

"E'"
P

..

.""

I

~, 1N4001

7 f9

-r

~ 0.01#'

--

~, 1N4001

.......
1:;;4

~.l~r

13
11

lO

15

27
16

Vee

(RIGHT DISPLAY)

01

DATA

NSt.l4000A
6

~4

...

~

o.l~r~

Q

.

3
8

~

1 t.lEG

R

19

tt

G H t.I

<.:l

4

1
r

N

3 26 18 17 23
DO
20
28

r - 14

-

oVl

-r
7.5k

5

~

10K 10K 10K

ClK
EN

.~

:= 7.5k

5
3
8

~

7~

9

%

O.Ol~r

TL/F/9449-1B

FIGURE 14. Microprocessor Control and Display Section

~~S·NV

II

....
N

Lt)

:Z


z

AM Signal to Noise

AM SPURIOUS RESPONSE

o

dB
-15
-9.5
-12
-8
-11
-16

Freq. kHz

700
850
913
1051
1074
1198

-10
~

.
CD

-20

"g

.s

:::I

Q,

~

AM CROSS MODULATION

-30

1-

I\)

,J"
I-- ~

f= 1.00 MHz
mod. = 1 kHz 307-

.... 1\.

-40

-

'-

0

Ref. Gen. Level = 200 IJ-V (Radio tuned to Ref. Gen.)

en
.....

-50

Frequency = 1.01 MHz

-60

Gen #2 Level = 10,000 IJ-V
Gen #2 signal appears 30 dB down-

o

10

Frequency = 1.05 MHz

FM Signal to Noise

-10

.
CD

-20

"g

~

:::I

,So
:::I

-30

40

50

60

70

AM Percent Harmonic Distortion
12

L

10

/V

- r\

f= 1.00 101Hz
mod. = 1 kHz

8
22.5 kHz dey.

\,

-40

0

4

2

-50
-60

30

TL/F 19449-15

o
>:::I

20

Input Level dB MIcrovolts

o

10

20

30

40

50

60

o
o

70

1\

\
1\

\ .......

......

, /

10 20 30 40 50 60 70 80 90 100
Input Level dB MIcrovolts

Input Level dB Microvolts
TLlF/9449-16

8-67

TL/F 19449-17

Section 9
Hi-Rei Interface

•

Section 9 Contents
Hi-Rei Interface-Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
National's A+ Program..... ........................................................
Hi-Rei Interface-Selection Guide....................................................

9-2

9-3
9-13
9-15

~

;:;:

~National

I»

-<......

~ Semiconductor

»
CD

...

MilitaryI Aerospace Programs from
National Semiconductor

oen

"0

I»

n

CD

...o
c.c
...

"'C

I»

This section is intended to provide a brief overview of military products available from National Semiconductor. For
further information, refer to our 1987 Reliability Handbook.

There are two processing levels specified within MIL-M38510: Classes Sand B. Class S is typically specified for
space flight applications, while Class B is used for aircraft
and ground systems. National is a major supplier of both
classes of devices. Screening requirements are outlined in
Table 3.

MIL-M-38S10
The MIL-M-38510 Program, which is sometimes called the
JAN IC Program, is administered by the Defense Electronics
Supply Center (DESC). The purpose of this program is to
provide the military community with standardized products
that have been manufactured and screened to governmentcontrolled specifications in government certified facilities.
All 38510 manufacturers must be formally qualified and their
products listed on DESC's Qualified Products List (QPL) before devices can be marked and shipped as JAN product.

Tables 1 and 2 explain the JAN device marking system.
Copies of MIL-M-38510, the QPL, and other related documents may be obtained from:
Naval Publications and Forms Center
5801 Tabor Avenue
Philadelphia, PA 19120
(212) 697-2179

-...
3

en

o
3

z

I»

o·
::::J
e.

en
CD
3
n·
o
::::J
Co
C

-...

n

o

TABLE I. The MIL·M·38510 Part Marking
Jt.l38510/XXXXXYYY

L

The Lead Finish
A Solder Dipped
B TIn Plate
C=Gold Plate
X Any lead finish above
Is acceptable

=
=
=

" - - - The Device Package
(see Table 2)

' - - - - - The Screening Level
S or B

'--_ _ _ The Device Number
on Slash Sheet

L..-_ _ _ _ _

L..-_ _ _ _ _ _

L..-_ _ _ _ _ _ _ _

The Slash Sheet Number

For radiation hardened devices
the slash Is replaced by the
Radiation Hardness Assurance
Indication per paragraph
3.4.1.3 of t.lIL-t.l-38510
t.lIL-t.l-38510

'--_ _ _ _ _ _ _ _ _ _ _ The JAN Prefix
(which may be applied only to
a fully conformant device per
paragraphs 3.6.2.1 and 3.6.7 of
t.lIL-t.l-38510)
TL/XX/Ol13-1

9-3

...o

u

:;,
"C

TABLE II. JAN Package Codes

C

o

u

38510

CI)

Package
Designation

'E

tJ)

tU
c
o

;

CO

z

E

-......
o

tn

E

CO

C)

e

D.
CI)

CJ

ca

Q.

en
o

...
CI)

c:(

.......

~

CO

~

~

general specification for non-JAN military product. Revision
C of this document defines the minimum requirements for a
device to be marked and advertised as 883-compliant. Included are design and construction criteria, documentation
controls, electrical and mechanical screening requirements,
and quality control procedures. Details can be found in paragraph 1.2.1 of MIL-STD-883.

MI L-M-38S1 0 (Continued)

A
B
C
D
E
F
G
H
I
J

K
L
M
N
P
Q
R
S
T
U
V
W
X

y
Z
2
3

Microcircuit Industry
Description

National offers both 883 Class Band 883 Class S product.
The screening requirements for both classes of product are
outlined in Table III.

14-Pin %" x %" (Metal) Flat Pack
14-Pin 3/15" x %" Flat Pack
14-Pin %" x %" Dual-In-Line
14-Pin %" x %" (Ceramic) Flat Pack
16-Pin %" x %" Dual-In-Line
16-Pin %" x %" (Metal or Ceramic) Flat Pack
8-Pin TO-99 Can or Header
10-Pin %" x %" (Metal) Flat Pack
1O-Pin TO-1 00 Can or Header
24-Pin %" x 1%" Dual-In-Line
24-Pin %" x %" Flat Pack
24-Pin %" x 1%" Dual-In-Line
12-Pin TO-101 Can or Header
(Note 1)
8-Pin %" x %" Dual-In-Line
40-Pin 3/1S" x 21As" Dual-In-Line
20-Pin %" x 11As" Dual-In-Line
20-Pin %" x %" Flat Pack
(Note 1)
(Note 1)
18-Pin %" x 15;'s" Dual-In-Line
22-Pin %" x 1 Ye" Dual-In-Line
(Note 1)
(Note 1)
(Note 1)
20-TerminaI0.350" x 0.350" Chip Carrier
28-TerminaI0.450" x 0.450" Chip Carrier

As with DESC specifications, a manufacturer is allowed to
use his standard electrical tests provided that all critical parameters are tested. Also, the electrical test parameters,
test conditions, test limits, and test temperatures must be
clearly documented. At National Semiconductor, this information is available via our RETS (Reliability Electrical Test
Specification Program). The RETS document is a complete
description of the electrical tests performed and is controlled by our QA department. Individual copies are available
upon request.
Some of National's older products are not completely compliant with MIL-STD-883, but are still required for use in military systems. These devices are screened to the same
stringent requirements as 883 product, but are marked
"-MIL" .

Military Screening Program (MSP)
National's Military Screening Program was developed to
make screened versions of advanced products such as gate
arrays and microprocessors available more quickly than is
possible for JAN and 883 devices. Through this program,
screened product is made available for prototypes and
breadboards prior to or during the JAN or 883 qualification
activities. MSP products receive the 100% screening of Table III, but are not subjected to Group C and D quality conformance testing. Other criteria such as electrical testing
and temperature range will vary depending upon individual
device status and capability.

Note 1: These letters are assigned to packages by individuals MIL-M-38510
detail specifications and may be assigned to different packages in different
specifications.

Reliability Electrical Test
Specifications (RETSTM)

DESC Specifications

National has implemented the first realtime, electronic catalog of military test specifications called RETS.

DESC specifications are issued to provide standardized versions of devices which are not yet available as JAN product.
MIL-STD-883 Class B screening is coupled with tightly controlled electrical specifications which have been written to
allow a manufacturer to use his standard electrical tests. A
current listing of National's DESC specification offerings can
be obtained from our franchised distributors, sales representatives, of DESC. DESC is located in Dayton, Ohio.

Included in this computerized directory is a detailed listing of
the electrical tests performed on all military devices qualified by National, including forcing functions, test limits and
temperature ranges.
Call your local National sales office for essential up-to-theminute information on device testing.

MI L-STD-883
Although originally intended to establish uniform test methods and procedures, MIL-STD-883 has also become the

9-4

Reliability Electrical Test Specifications (RETSTM)

~

::;:

(Continued)

D)

TABLE 111.100% Screening Requirements
Class B

ClassS

Screen

CD

Method

Reqmt

1. Wafer Lot Acceptance

5007

All Lots

2. Nondestructive Bond Pull (Note 14)

2023

100%

2020, Condition A

100%

2010, Condition B

100%

1008, Condition C, Min.
24 hrs. Min.

100%

1008, Condition C, Min.,
24 hrs. Min.

100%

3. Internal Visual (Note 1)
4. Stabilization Bake (Note 16)

Method

-<.......
l=...o

Reqmt

fA

"C
D)
(')

CD

..."'D
...

o

CO
D)

3

-...
fA

5. Temperature Cycling (Note 2)
6. Constant Acceleration

1010, Condition C
2001, Condition E Min.
y 1 Orientation Only

100%

1010, Condition C

100%

100%

2001, Condition E, Min.
Y 1 Orientation Only

100%

7. Visual Inspection (Note 3)

100%

8. Particle Impact Noise Detection (PIND) 2010, Condition A (Note 4)

100%

9. Serialization

100%

(Note 5)

10. Interim (Pre-Bum-In) Electrical
Parameters

Per Applicable Device
Specification (Note 13)

100%

11. Burn-In Test

1015
240 Hrs. @ 125°C Min.
(Cond. F Not Allowed)

100%

12. Interim (Post Burn-In) Electrical
Parameters

Per Applicable Device
Specification (Note 13)

100%

13. Reverse Bias Burn-In (Note 7)

1015; Test Condition A, C,
72 Hrs. @ 150°C Min.
(Cond. F Not Allowed)

100%

Per Applicable Device
Specification (Note 13)
5% Parametric (Note 14),
3% Functional

14. Interim (Post Burn-In) Electrical
Parameters
15. PDA Calculation
16. Final Electrical Test (Note 15)
a) Static Tests
1) 25°C (Subgroup 1, Table I, 5005)
2) Max & Min Rated Operating
Temp.
(Subgroups 2,3, Table 15005)
b) Dynamic Tests or Functional Tests
1) 25°C (Subgroups 4 or 7)
2) Max & Min Rated Operating
Temp.
(Subgroups 5 and 6 or 8,
Table I, 5005)
c) Switching Tests 25°C
(Subgroups 9 Table I, 5005)
17. Seal Fine, Gross
18. Radiographic (Note 10)
19. Qualification or Quality Conformance
Inspection Test Sample Selection
20. External Visual (Note 12)

Per Applicable Device
Specification

~

en
CD

3
n"
o
~
a.

Per Applicable Device
Specification (Note 6)
100%

100%

Per Applicable Device
Specification

100%

All Lots

5% Parametric (Note 14)

All Lots

160 Hrs.

100%

100%

100%
Per Applicable Device
Specification

100%

100%

100%

100%

100%

100%, (Note 8)

2012 Two Views

100%

(Note 11)

Samp.

2009

100%

-...
c

()

o

100%

100%

zD)
0"

e!.

1015
@ 125°C Min.

1014

9-5

100%

o
3

1014

100%, (Note 9)

(Note 11)

Samp.
100%

...o

-=
( ,)

"C

Reliability Electrical Test Specifications (RETSTM)

(Continued)

C

TABLE III. 100% Screening Requirements (Continued)

(,)

"e

Note 1: Unless otherwise specified, at the manufacturer's option, test samples for Group B, bond strength (Method 5005) may be randomly selected prior to or
following internal visual (Method 5004), prior to sealing provided all other specification requirements are satisfied (e.g., bond strength requirements shall apply to
each inspection lot, bond failures shall be counted even if the bond would have failed internal visual).

en

Note 2: For Class B devices, this test may be replaced with thermal shock method 1011, test condition A, minimum.

o

CI)

(ij

Note 3: At the manufacturer's option, visual inspection for catastrophic failures may be conducted after after each of the thermal/mechanical screens, after the
sequence or after seal test. Catastrophic failures are defined as missing leads, broken packages, or lids off.

:;::

Note 4: The PIND test may be performed in any sequence after step 6 and prior to step 16. See MIL·M-38510, paragraph 4.6.3.

c
o

CO

z

Note 5: Class S devices shall be serialized prior to interim electrical parameter measurements.

E

Note 6: When specified, all devices shall be tested for those parameters requiring delta calculations.

t /)

Note 8: For Class S devices, the seal test may be performed in any sequence between step 16 and step 19, but it shall be performed after all shearing and forming
operations on the terminals.

-e
...o

E

Note 7: Reverse bias burn-in is a requirement only when specified in the applicable device specification. The order of performing burn-in and reverse bias burn-in
may be inverted.

...

Note 9: For Class B devices, the fine and gross seal tests shall be performed separately or together in any sequence and order between step 6 and step 20 except
that they shall be performed after all shearing and forming operations on the terminals. When 100% seal screen cannot be performed after shearing and forming
(e.g., flatpacks and chip carriers) the seal screen shall be done 100% prior to these operations and a sample test (LTPD= 5) shall be performed on each inspection
lot following these operations. If the sample fails, 100% rescreening shall be required.

CI)
(.)

Note 10: The radiographic screen may be performed in any sequence after step 9.

CO
Co

Note 11: Samples shall be selected for testing in accordance with the specific device class and lot requirements of Method 5005.

C)

o

D-

t/)

Note 12: External Visual shall be performed on the lot any time after step 19 and prior to shipment.

CI)

Note 13: Read and record is required at steps 10 and 12 only for those parameters for which post-bum-in delta measurements are specified. All parameters shall
be read and recorded at step 14.

e


....oCD
en

2 Devices
(No Failures)

2016

4 Devices
(No Failures)

2015

2003
or
2002

"tJ
I»

n

CD

"U
....
o

(Q

;;
3
en

Soldering Temperature of 245 ± 5°C

10

....

o

3
z

-

I»

2014

Failure Criteria from Design and Construction
Requirements of Applicable Procurement Document

1 Device
(No Failures)

0'
::s

e!-

en
CD
3

2011

(;'

1) Condition C or D
2) Condition C or D
3) Condition F
4) Condition H

15

::s
Co
c

n

1018

1,000 ppm Maximum Water Content at 100°C

3 Devices
(0 Failures)
(Note 7) or
5 Devices
(1 Failure)

1014

As Applicable

5

2015

Group A, Subgroup 1

15 (0)

Group A, Subgroup 1

Note 1: Electrical reject devices from the same inspection lot may be used for all subgroups when end-point measurements are not required, except for devices
submitted to subgroup 7.
Note 2: Not required for qualification or quality conformance inspections where Group 0 inspection is being performed on samples from the same inspection lot.
Note 3: All devices submitted for solderability test shall be in the lead finish that will be on the shipped product and which has been through the temperature/time
exposure of burn-in except for devices which have been hot-solder dipped or have undergone tin fusing after burn-in. The LTPD for solderability test applies to the
number of leads inspected except in no case shall less than 3 devices be used to provide the number of leads required.
Note 4: Test samples for internal visual and mechanical shall be selected at any point following the seal operation.
Note 5: Test samples for bond strength may, at the manufacturer's option, unless otherwise specified, be randomly selected prior to or following internal visual
(precap) inspection provided all other specification requirements are satisfied. Unless otherwise specified, the LTPD sample size for condition C or 0 is the number
of bond pulls selected from a minimum number of 10 devices, and for conditions F or H is the number of dice (not bonds) (see Method 2011).
Note 6: This test is required only if the package contains a desiccant.
Note 7: Test 3 devices, if 1 fails, test 2 additional devices with no failure.
Note 8: This test is not required if either the 100% screen or sample test is performed between steps 14 and 18 and 100% screening of Table 3 of this section.
Note 9: Unless otherwise specified, test shall be performed for initial qualification and product redesign as a minimum.

9-7

o

....o

Subgroup 6
Internal Water-Vapor Content (Note 6)

Subgroup 7
Seal (Note 8)
1) Fine
2) Gross

LTPD

..

o

( ,)

=

Reliability Electrical Test Specifications (RETSTM)

"C

TABLE VI. Group B (Class S)

C

o
(,)

'sCD

Test (Note 1)

Method

1i
c

Subgroup 1
a) Physical Dimensions (Note 2)
b) Internal Water-Vapor (Notes 2, 3)

2016
1018

en
o

;::

ca

z

E

e

Subgroup 2 (Note 5)
a) Resistance to Solvents
b) Internal Visual and Mechanical

U)

E

l!

C)

e

D.
CD

g
Q.

U)

e

~

c) Bond Strength (Note 6)
1) Thermocompression
2) Ultrasonic
3) Flip-Chip
4) Beam Lead
d) Die Shear Test
Subgroup 3
Solderability (Note 7)

"E-

~
:i

(Continued)

Subgroup 4
Lead Integrity (Note 5)
Seal
1) Fine
2) Gross
Lid Torque (Note 3)

2015
2013&
2014

Subgroup 6 (Note 5)
a) Electrical Parameters (Note 11)
b) Temperature Cycling
c) Constant Acceleration
d) Seal
1) Fine
2) Gross
e) Electrical Parameters
Subgroup 7 (Note 12)
a) Electrical Parameters
b) Electrostatic Discharge
Sensitivity
b) Electrical Parameters

5,000 ppm Maximum Water Content at 100°C

Failure Criteria from Design and Construction
Requirements of Applicable Procurement
Document

2011

2019
2003 or
2022
2004
1014

Quallty/(Accept No.)
orLTPD
2 (0)
3 (0) or 5 (1) (Note 4)
4(0)
2 (0)

LTPD = 10
1) Condition C or 0
2) Condition C or 0
3) Condition F
4) Condition H
Per Method 2019 for the Applicable Die Size
Soldering Temperature or 245 ± 5°C

Condition B2, Lead Fatigue
As Applicable

3 (0)
LTPD = 15

2 (0)

As Applicable

Subgroup 5 (Notes 8, 9)
a) Electrical Parameters (Note 11)
b) Steady State Life
c) Electrical Parameters

Condition

1005

1010
2001
1014

Group A, Subgroups 1, 2, 3: Read and Record
Group A, Subgroups 4-11: Attributes
Condition C, 0 or E: 1000 hours
Groups A, Subgroups 1, 2, 3: Read and Record
Group A, Subgroup 4-11: Attributes

LTPD = 5

Group A, Subgroups 1, 2, 3: Read and Record
Condition C, 100 Cycles/min.
Test Condition E: Y1 Orientation Only

LTPD = 5

Group A, Subgroups 1, 2, 3: Read and Record
Group A, Subgroup 1
3015
Group A, Subgroup 1

9-8

15 (0)

Reliability Electrical Test Specifications (RETSTM)

~

;:::;:

(Continued)

D)

-<......

TABLE VI. Group B (Class S) (Continued)
Note 1: Electrical reject devices from the same Inspection may be used for all subgroups where electrical end-point measurements are not required.
Note 2: Not required for qualification or quality conformance inspections where Group 0 inspection is being performed on samples from the same inspection lot.
Note 3: This test is required only if it is a glass-frit sealed package.

:r:CD
.,
o
en

"C

Note 4: Test 3 devices; if 1 fails, test 2 additional devices with no failures.

D)

Note 5: All samples for subgroup 82 must have been through the complete sequence of subgroup 86 tests.

n

Note 6: Unless otherwise specified, the LTPD sample size for conditions C and 0 is the number of bond pulls selected from a minimum of 4 devices and for
conditions F and H is the number of dice (not bonds).

.,"'C

CD

Note 7: All devices must be In the same lead finish that will be on the shipped product and shall have been through the temperature/time exposure of burn-In
except for devices that have been hot-solder dipped or undergone tin fusing after burn-in. The LTPD applies to the number of leads inspected, except in no case
shall less than 3 devices be used to provide the number of leads required.
Note 8: The alternate removal-of-bias provisions of Method 1005 shall not apply for test temperatures above 125°C.

z

Note 11: Read and record data Group A of quality conformance Is acceptable.

-

Note 12: Unless otherwise specified, test shall be performed for initial qualification and product redesign as a minimum.

D)

0'
::s

TABLE VII. Group C (Ole-Related Tests for Class Band COnly)

Subgroup 1
Steady State Life Test
End·Point Electrical Parameters
Subgroup 2
Temperature Cycling
Constant Acceleration
Seal
a) Fine
b) Gross
Visual Examination
End-Point Electrical Parameters

Condition

o
3

Note 10: For lead less chip carriers, condition 0 will apply.

Method

OJ
3
en

.,

Note 9: The same temperature must be employed for operating life that was used for the 100% burn-in.

Test

o

CC

e!-

LTPD

en
CD

3

1005

Test Condition to be Specified (1,000 hours at 125°C)
As Specified in the Applicable Device Specification

5

1010
2001
1014

Condition C
Condition E min, Y 1 Orientation Only (Note 1)
As Applicable

15

(;'

o
::s
c.

c

n

Per Visual Criteria of Method 1010 or 1011 as
Specified in the Applicable Device Specification

Note 1: See paragraph 3 of Method 5005 for the procedure for large cavity package.

9-9

o
.,

...

o

u

::::s

Reliability Electrical Test Specifications (RETSTM) (Continued)

"C

c
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u

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ca

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ca
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.....

~

ca

~

:i

TABLE VIII. Group 0 (Package-Related Tests for Classes)
Test
Subgroup 1 (Note 1)
a) Physical Dimensions
Subgroup 2 (Note 1, 4)
Lead Integrity
Seal
a) Fine
b) Gross
Subgroup 3 (Note 3)
Thermal Shock
Temperature Cycling
Moisture Resistance (Note 4)
Seal
a) Fine
b) Gross
Visual Examination
End-Point Electrical Parameter (Note 4)
Subgroup 4 (Note 3)
Mechanical Shock
Vibration Variable Frequency
Constant Acceleration
Seal
a) Fine
b) Gross
Visual Examination
End-Point Electrical Parameters
Subgroup 5 (Note 1)
Salt Atmosphere
Seal
a) Fine
b) Gross
Visual Examination

Method

Condition

LTPD
15

2016

2004
1014

Test Condition 82 (Lead Fatigue) (Note 10)
As Applicable

15

1011
1010
1004
1014

Test Condition 8 Minimum, 15 Cycles Minimum
Test Condition C, 100 Cycles Minimum

15

As Applicable

Per Visual Criteria of Method 1004 or 1010
As Specified in the Applicable Device Specification

2002
2007
2001
1014

Test Condition 8 Minimum
Test Condition A Minimum
Test Condition E Minimum
y 1 Orientation Only (Note 6)
As Applicable

15

Per Visual Criteria of Method 1010 or 1011
As Specified in the Applicable Device Specification

1009
1014

Test Condition A Minimum
As Applicable

15

Per Visual Criteria of Method 1009

Subgroup 6 (Note 1)
Internal Water-Vapor Content

1018

Subgroup 7 (Note 1)
Adhesion of Lead Finish (Notes 7,8)

2025

15

Subgroup 8 (Note 1)
Lid Torque (Note 2)

2024

5 (0)

5,000 ppm Maximum Water Content at 100'C

3 Devices
(0 Failures)
or
5 Devices
(1 Failure)(Note 5)

Note 1: Electrical reject devices from that same inspection lot may be used for samples.
Note 2: Lid torque test shall apply only to packages which use a glass-frit seal to lead frame, lead or package body (Le., wherever frit seal establishes hermeticity or
package integrity).
Note 3: Devices used in subgroup 3, "Thermal and Moisture Resistance" may be used in Subgroup 4 "Mechanical".
Note 4: At the manufacturer's option, end-point electrical parameters may be performed after moisture resistance and prior to seal test.
Note 5: Test 3 devices; if 1 fails, test 2 additional devices with no failures.
Note 6: See paragraph 3 of Method 5005 for the procedure for large cavity packages.
Note 7: Does not apply to lead less chip carriers.
Note 8: The LTPD applies to the number of leads to be tested.
Note 9: The lead bend stress initial conditioning is not required for leadless chip carriers.
Note 10: For leadless chip carriers only, condition 0 shall apply.

9-10

Reliability Electrical Test Specifications (RETSTM)

~

::;:

(Continued)

D)

-<.......

TABLE IX. Group E (Radiation Hardness Assurance Tests)
Test (Note 1)

Method

Condition

Quantity (Accept Number = 0)

(1)
~

ClassS
Subgroup 1 (Note 3)
Neutron Irradiation
a) Qualification

»

ClassB

o

en

"C

D)

1017

n

25°C

(1)

-a
~

11 per Wafer Lot
b) Quality Conformance
End·Point Electrical Parameters

11 per Wafer Lot

5 from each of
3 Wafer Lots
11 per Wafer Lot

Per Applicable Detail Specification

o

CQ

OJ

3
en

~

Subgroup 2
Steady·state Total Dose
Irradiation
a) Qualification

o

1019

b) Quality Conformance
End·Point Electrical Parameters

3
zD)

25°C, Maximum Supply Voltage
(Note 2)
(Note 2)

5 from each of
3 Wafer Lots
11 per Wafer Lot

Per Applicable Detail Specification

Note 1: Parts used for one subgroup test may not be used for the other subgroup but may be used for higher levels in the same subgroup. Total exposure shall not
be considered cumulative unless testing is performed within the time limits of the test method.
Note 2: 4 per wafer for devices type S less than or equal to 4000 equivalent transistors per chip. 2 per wafer for larger dice. Samples will be selected at radius
approximately equal to two-thirds of the wafer radius and spaced uniformly around this radius.
Note 3: Subgroup 1 is not required for MOS devices.

-o·
~

e!.

en
(1)

3

n·

o

~

Co

c
n
o

~

9·11

~

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( ,)

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Reliability Electrical Test Specifications (RETSTM)

"C

o

CJ

'E

Test

Q)

U)

(ij

c

o

;

CO

z
E

-ee

Maximum deviation of ± 2 mil
for approved design nominal 6
mil minimum.

Two wafers per lot. Reject lot if
any measurement exceeds
limits or revert to test of each
wafer.

2. Metallization thickness

MIL-STD-977 Method 5500. All
readings shall be recorded.

a) Conductor: 8 kA minimum for
single level metal and for the
top level of multi-level metal:
6 kA minimum for lower levels,
with a maximum deviation of ±
20% from the approved design
nominal.
b) Barrier: Maximum deviation
of ± 30% from the approved
design nominal.

One wafer (or monitor) per lot.
Reject lot if measurement
exceeds limits or revert to test
of each wafer.

3. Thermal stability (applicable
to: all linear; all MOS; all bipolar
digital operating at 10V or
more)

MIL-STD-977, Method 2500.
Record VFB or VT. (Note 3)

a)~VFB

or ~VT ::;: 0.75Vfor
bipolar digital devices operating
at ~ 10V and all bipolar linear
devices not containing MOS
transistors. The monitor shall
have an oxide and shall be
metallized with the lot.
b)~ VFB or ~ VT ::;: 1.0V for
bipolar linear devices that
operate above 5V and contain
MOS transistors and digital
devices that operate above 10V
and contain MOS structures.
c) ~ VFB or ~ VT ::;: O.4V for
MOS devices.

One wafer (or monitor) per lot.
Reject lot if measurement
exceeds limits or revert to test
of each wafer.
Separate monitors may be used
but must be oxidized and
metallized with the lot.
A monitor consisting of a gate
oxide metallized with the lot
shall be used.

4. SEM (Note 4)

MIL-STD-883, Method 2018.

MIL-STD-883, Method 2018.

MIL-STD-883, Method 2018.
Lot acceptance basis.

5. Glassivation Thickness

MIL-STD-977, Method 5500. All 6 kA minimum for Si02 and
readings shall be recorded.
2 kA minimum Si3N4 with
maximum deviation of ± 20%
from approved design nominal.

One wafer (or monitor) per lot.
Reject lot if any measurement
exceeds limits or revert to test
of each wafer.

6. Gold backing thickness
(when applicable)

MIL-STD-977, Method 5500. All Per approved design nominal
readings shall be recorded.
thickness and tolerance.

One wafer (or monitor) per lot.
Reject lot if any measurement
exceeds limits or revert to test
of each wafer.

E

o

~

D.
Q)

CJ
CO

c..
en

e

~
~

CO

~

Sampling Plan

MIL-STD-977, Method 1580.
Measurement shall be
performed after final lap or
polish. All readings shall be
recorded.

C)

Q)

Limits
(Note 2)

Conditions
(Note 1)

1. Wafer Thickness (not
required when the finished
wafer design thickness is
greater than 10 mils)

en

<
.......

(Continued)

TABLE X. Wafer Lot Acceptance Tests

C

:§

Note 1: Approved equivalent test methods may be used in lieu of the reference MIL·STD·977 methods.
Note 2: Approved design nominal values or tolerances shall be submitted for line certification per DESC·EQM·42.
Note 3: All reading shall be normalized to oxide thickness of 1000A.
Note 4: When wafer lots fail to pass the SEM requirements of Method 201 S, compliance with the current density requirement shall not be used to waiver the SEM
requirement.

9-12

~National

~ Semiconductor
National's A + Program
A + Program: A comprehensive program that utilizes National's experience gained from participation in the many
Military/ Aerospace programs.

The concept of reliability, on the other hand, refers to how
well a part that is initially good will withstand its environment. Reliability is measured by the percentage of parts that
fail in a given period of time.

A program that not only assures high quality but also increases the reliability of molded integrated circuits.

Thus the difference between quality and reliability means
the ICs of high quality may, in fact be of low reliability, while
those of low quality may be of high reliability.

The A + program is intended for users who need better than
usual incoming quality and higher reliability levels for their
standard integrated circuits.

Improving the Reliability of Shipped Parts

Users who specify A + processed parts will find that the
program:

The most important factor that affects a part's reliability is
its construction; the materials used and the method by
which they are assembled.

• Eliminates incoming electrical inspection.

Reliability cannot be tested into a part. Still, there are tests
and procedures that an IC vendor can implement which will
subject the IC to stresses in excess of those that it will endure in actual use, and which will eliminate marginal, shortlife parts.

• Eliminates the need for, and thus the added cost of, independent testing laboratories.
• Reduces the cost of reworking assembled boards.
• Reduces field failures.
• Reduces equipment down time.

In any test of reliability the weaker parts will normally fail
first. Further, stress tests will accelerate, or shorten, the
time of failure of the weak parts. Because the stress tests
cause weak parts to fail prior to shipment to the user, the
population of shipped parts will in fact demonstrate a higher
reliability in use.

• Reduces the need for excess inventories due to yield loss
incurred as a result of processing performed at independent testing laboratories.
The A + Program Saves You Money
It is a widely accepted fact that down-time of equipment is
costly not only in lost hours of machine usage but also costly in the repair and maintenance cycle. One of the added
advantages of the A + program is the burn-in screen, which
is one of the most effective screening procedures in the
semiconductor industry. Failure rates as a result of the burnin can be decreased many times. The objective of burn-in is
to stress the device much higher than it would be stressed
during normal usage.

National's A + Program
National provides the A + program as the best practical approach to maximum quality and reliability on molded devices. The following flow chart shows how we do it step by
step.

~

Reliability vs. Quality
The words "reliability" and "quality" are often used interchangeably, as though they connoted identical facets of a
product's merit. But reliability and quality are different, and
IC users must understand the essential difference between
the two concepts in order to evaluate properly the various
vendors' programs for products improvement that are generally available, and National's A + program in particular.

SEM
Randomly selected wafers are taken from production regularly and subjected to SEM analysis.

Epoxy B Processing for All Molded Parts
At National, all molded semiconductors, including
ICs, have been built by this process for some time
now. All processing steps, inspections, and QC
monitoring are designed to provide highly reliable
products. (A reliability report is available that
gives, in detail, the background of Epoxy B, the
reason for its selection at National, and reliability
data that proves its success.)

The concept of quality gives us information about the population and faulty IC devices among good devices, and generally relates to the number of faulty devices that arrive at a
user's plant. But looked at in another way, quality can instead relate to the number of faulty ICs that escape detection at the IC vendor's plant.

Six Hour, 150°C Bake

It is the function of a vendor's Quality Control arm to monitor
the degree of success of that vendor in reducing the number of faulty ICs that escape detection. Quality Control does
this by testing the outgoing parts on a sampled basis. The
Acceptable Quality level (AQL) in turn determines the stringency of the sampling. As the AQL decreases it becomes
more difficult for defective parts to escape detection, thus
the quality of the shipped parts increases.

This stress places the die bond and all wire bonds
into a combined tensile and shear stress mode,
and helps eliminate marginal bonds and electrical
connections.

9-13

•

National's A + Program

(Continued)

Five Temperature Cycles WC to 100°C)

DC Functional and Parametric Tests

Exercising each device over a 100°C temperature
range provides an additional die and package
stress.

These room-temperature functional and parametric tests are the normal, final tests through which
all National products pass.
Thermal Shock Monitor

Samples from each package
type are selected at random
each week and submitted to
cycles of liquid to liquid thermal shock - 65°C to + 150°C. In addition, samples are selected every four weeks and subjected
to 2000 temperature cycles of O°C to + 25°C.

High Temperature (100°C)
Functional Electrical Test
A high temperature test with voltages applied
places the die under the most severe stress possible. The test is actually performed at 100°C-15°C
higher than the commercial ambient limit. All devices are thoroughly exercised at the 100°C ambient.

Tighter-Than-Normal QC Inspection Plans

Most vendors sample inspect outgoing parts to a
0.3% AQL. When you specify the A + program,
we sample your parts to a 0.035% AQL at room
temperature and 0.05% AQL at TA Max. This eight
times tightening (from 0.3 to 0.035% AQL) coupled with three 100% electrical tests, dramatically
reduces the number of "escapes" and allows us
to guarantee the AOLs listed below.

Electrical Testing

Every device is tested at 25°C for functional and
DC parameters.

Burn-In Test

Each device is burned-in for 160 hours at a minimum junction temperature of + 125°C or under
equivalent conditions of time and temperature, as
established by a time-temperature regression
curve based on 0.96 eV activation energy (i.e., 23
hours at + 155°C). All burn-in done under steadystate conditions unless otherwise specified.

o

Ship Parts

Here are the OC sample plans used in our A + test program:
Test
Temperature
AQL
Electrical Functionality
25°C}
0.035%
Parametric, DC
25°C
Parametric, AC
0.1%
25°C
Electrical Functionality
At each temperature}
0.05%
Parametric, DC
extreme.
Mechanical
Critical
0.01%
Major
0.28%

9-14

~National

~ Semiconductor
Interface Hi-Rei Selection Guide
NSID
OP73048

-MIL

OP8238

081632
081634
081649

087834
087835
087836
087837
087838
088T28

X
X
X

081691A
0826F31

",

",

0896F173

",

0896F174

",

0896F175
0896F177

",

0896F178
089614

",

X

0826F32

",

089615

0826L832

X
X

089622

0826L833
0835F86

",

0835F87

",

089636A
089637A

0855107A

X
X
X
X
X

0855110A
0855113
0855122
0855451
0855452
0855453

0855464
0855494
087640
0878C120
0878C20
0878L8120

x=

X
X
X
X
X
X
X
X
X

089638
089639A
089667A
MM5452
J.LA55107A

X
X

/LA55110A
/LA9614

X
X

0855461
0855462
0855463

X

J.LA9615
J.LA9622
J.LA9627
J.LA9636A

X
X
X
X
X
X
X

/LA9637A
J.LA9638
J.LA9639A
J.LA9667A

Available Now

", = Future Product

9-15

JAN

X

X
X

",

089627

X

DESC
SMD

X
X

0896F172

0826L831

X

1883

X
X
X
X
X
X
X
X
X
X
X

087832
087833

X
X

081674
081687

X

087831

X

X
X
X
X
X
X

081631

0878L 12

087830

",

0816179

-MIL

087820

X
X

081603

NSID
087800
087820A

X
X

080056
0816F95

081652

JAN

X
X

080026

081651

DESC
5MD

X

OP7311
OP8216
OP8228

1883

X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X

•

Section 10
Appendices and
Physical Dimensions

Section 10 Contents
Application Note Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Terms and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interface Product Cross Reference Guide .............................................
Industry Package Cross Reference Guide .............................................

10-3
10-4
10-6
10-13

Packaging and Physical Dimensions
AN-336 Understanding Integrated Circuit Package Power Capabilities. . . . . . . . . . . . . . . . . . . ..
AN-450 Small Outline (S.O.) Package Surface Mounting Methods-Parameters and Their
Effect qn Product Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Bookshelf
Sales and Distribution Offices

10-2

10-16
10-21
10-31

l>

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~National

"'5!.
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~ Semiconductor

D)

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Application Note Index

CD

S-

a.
CD

><

PAGE
APPLICATION NOTE

NUMBER

AN-22

Integrated Circuits for Digital Data Transmission

1-287

AN-76

Applying Modern Clock Drivers to MOS Memories

5-85

AN-84

Driving 7-Segment Gas Discharge Display Tubes with National Semiconductor Circuits

4-41

AN-108

Transmission Line Characteristics

1-301

AN-213

Safe Operating Areas for Peripheral Drivers

3-70

AN-214

Transmission Line Drivers and Receivers for EIA Standards RS-422 and RS-423

1-307

AN-216

Summary of Electrical Characteristics of Some Well Known Digital Interface Standards.

1-317

AN-259

DS3662 The Bus Optimizer

2-33

AN-335

Digital PLL Synthesis

8-49

AN-336

Understanding Integrated Circuit Package Power Capabilities

10-16

AN-337

Reducing Noise on Microcomputer Busses

2-40

AN-350

Designing an LCD Dot Matrix Display Interface

4-112

AN-371

The MM58348/342/341/248/242/241 Directly Drive Vacuum Fluorescent (VF)
Displays

4-131

AN-378

A Novel Process for Vacuum Fluorescent (VF) Display Drivers

4-142

AN-409

Transceivers and Repeaters Meeting the EIA RS-485 Interface Standard

1-330

AN-438

Low Power RS-232C Driver and Receiver in CMOS

1-337

AN-440

New CMOS Vacuum Fluorescent Drivers Enable Three Chip System to Provide
Intelligent Control of Dot Matrix (VF) Display

4-148

AN-450

Small Outline (S.O.) Package Surface Mounting Methods-Parameters and their
Effect on Product Reliability

10-21

AN-457

High Speed, Low Skew RS-422 Drivers and Receivers Solve Critical System Timing
Problems

1-341

AN-458

The Proposed IEEE 896 Futurebus a Solution to the Bus Driving Problem

2-76

AN-512

DS8911 AM/FM/TV Sound Up-Conversion Frequency Synthesizer

8-56

AN-514

Timing Analysis of Synchronous and Asynchronous Busses

2-81

10-3

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Technical Terms and Definitions
CURRENT

Low-Level Input Voltage, Vil

High-Level Input Current, IIH

An input voltage level within the less positive (more negative) of the two ranges of values used to represent the binary variables.

The current into* an input when a high-level voltage is applied to that input.

NOTE: A maximum is specified that is the most positive value of low-level
input voltage for which operation of the logic element within specification limits is guaranteed.

Input Current at Maximum Input Voltage, II
The current into* an input when maximum specified input
voltage is applied.

Positive-Going Threshold Voltage, VTH

Low-Level Input Current, III

The voltage level at a transition-operated input that, causes
operation of the logic element according to specification, as
the input voltage rises from a level below the negative-going
threshold voltage, VTL.

The current into* an input when a lOW-level voltage is applied to that input.
Low-Level Input Current HiZ, IILZ
The current into* an input when a low-level voltage is applied to the input with the device in the TRI-STATE condition.

Negative-Going Threshold Voltage, VTl
The voltage level at a transition-operated input that, causes
operation of the logic element according to specification, as
the input voltage falls from a level above the positive-going
threshold voltage, VTH.

High-Level Output Current, 10H
The current into* an output with input conditions applied
that, according to the product specification, will establish a
logic high level at the output.

Hysteresis, VHVS
The absolute difference in voltage value between the positive going threshold and negative going threshold.

Low-Level Output Current, 10l
The current into* an output with input conditions applied
that, according to the product specification, will establish a
logic low level at the output.

Input Clamp Voltage, VIK
An input voltage in a region of relatively low differential resistance that serves to limit the input voltage swing.

Off-State Output Current, 10 (ICEX)
The current flowing into* an output with input conditions
applied that, according to the product specification, will
cause the output switching element to be in the off state.

High-Level Output Voltage, VOH
The voltage at an output terminal with input conditions applied that, according to the product specification, will establish a logic high level at the output.

NOTE: This parameter is usually specified for open·collector outputs intended to drive devices other than logic circuits at a specified voltage
usually greater then the Vcc supply.

Low-Level Output Voltage, VOL
The voltage at an output terminal with input conditions applied that, according to the product specification, will establish a logic low level at the output.

Output Current of a TRI-STATE Device, loz
The current into* a TRI-STATE output having input conditions applied that, according to the product specification,
will establish the high-impedance state at the output.

Off-State Output Voltage, VO(off)
The voltage at an output terminal with input conditions applied that, according to the product specification, will cause
the output switching element to be in the off state.

Short-Circuit Output Current, los
The current into* an output when that output is short-circuited to ground or any other specified potential, with input conditions applied to establish the output logic level farthest
from ground potential or any other specified potential.

NOTE: This characteristic is usually specified only for the outputs not having
internal pull-up elements.

On-State Output Voltage, VO(on)
The voltage at an output terminal with input conditions applied that, according to the product specification, will cause
the output switching element to be in the on-state.

Supply Current, ICCH
The current into* the Vee supply terminal of an integrated
circuit when the outputs are in a logic high state.

Output Clamp Voltage, VOK
An output voltage in a region of low differential resistance
that serves to limit the voltage swing.

Supply Current, ICCl
The current into* the Vee supply terminal of an integrated
circuit when the outputs are in a logic low state.

PROPAGATION TIME

VOLTAGE

Propagation Delay Time, tpD
The time between the specified reference points on the input and output voltage waveforms with the output changing
from one logic level (high or low) to the other logic level.

High-Level Input Voltage, VIH
An input voltage within the more positive (less negative) of
the two ranges of values used to represent the binary variables.
NOTE: A minimum is specified that is the least positive value of high-level
input voltage for which operation of the logic element within specification limits is guaranteed.
·Current out of a terminal is given as a negative value.

10-4

-I
C'D

Technical Terms and Definitions

n

:::r
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(Continued)

n"

Propagation Delay Time, Low-to-Hlgh-Level Output,
tPLH
The time between the specified reference points on the input and output voltage waveforms with the output changing
from the logic low level to the logic high level.

SETUP AND HOLD TIME

Propagation Delay Time, Hlgh-to-Low-Level Output,
tpHL
The time between the specified reference points on the input and output voltage waveforms with the output changing
from the logic high level to the logic low level.

Note 1: The setup time is defined as the time between two events and may
be insufficient to accomplish the setup. A minimum value is speci·
fied that is the shortest interval for which proper operation of the
logic element is guaranteed.

e!.

Setup Time, tsu
The time interval between the application of a signal that is
maintained at a specified input terminal prior to a consecutive active transition at another specified input terminal.

Note 2: The setup time may have a negative value in which case the mini·
mum limit defines the longest interval of time between the active
transition and the application of the other signal for which proper
operation of the logic element is guaranteed.

Transition Time LOW to HIGH, tTLH
The time between two specified reference points on a
waveform, normally specified between the 10% and 90%
points, that is changing from LOW to HIGH.

Hold Time, th
The interval during which a signal is maintained at a specified input terminal after an active transition occurs at another specified input terminal.

Transition Time HIGH to LOW, tTHL
The time between two specified reference points on a
waveform, normally specified between the 90% and 10%
points, that is changing from HIGH to LOW.

Note 1: The hold time is defined as the time between two events and may
be insufficient to accomplish the intended result. A minimum value is
specified that is the shortest interval of time for which proper opera·
tion of the logiC element is guaranteed.

TRI-STATE DELAYS

Note 2: The hold time may have a negative value in which case the minimum limit defines the longest interval of time between the release of
data and the active transition on the specified input for which proper
operation of the logic element is guaranteed.

Output Enable Time, tpZL
The propagation delay time between the specified reference
points on the input and output voltage waveforms with the
TRI-STATE output changing from a high-impedance (off)
state to the logic low level.

TRUTH TABLE EXPLANATIONS
Symbols generally associated with Functional Truth Tables.

Output Enable Time, tPZH

H

= Logic high level (steady-state)

The propagation delay time between the specified reference
points on the input and output voltage waveforms with the
TRI-STATE output changing from a high-impedance (off)
state to the logic high level.

L

= Logic low level (steady-state)

....r

Output Disable Time, tpLZ

X

= irrelevant (any input, including transitions)

The propagation delay time between the specified reference
points on the input and output voltage waveforms with the
TRI-STATE output changing from the logic low level to a
high-impedance (off) state.

Z

= off state (high-impedance) of a TRI-STATE
output

a.. h

= the level of steady-state inputs at inputs A

= Transition from a logic low to high level
= Transition from a logiC high to low level

through H respectively

Output Disable Time, tpHZ
The propagation delay time between the specified reference
points on the input and output voltage waveforms with the
TRI-STATE output changing from the logic high level to a
high-impedance (off) state.

Qo

= level of Q before the indicated steady-state

'00

= complement of Qo or level of

CLOCK FREQUENCY

Qn

= level of Q before the most recent active tran-

input conditions were established

'0 before the
indicated steady-state input conditions were
established
sition indicated by

Maximum Clock Frequency, fMAX

....r or

NOTE: II, in the input columns, a row contains only the symbols H, L, and/or
X, this means the indicated output is valid whenever the input configuration is achieved and regardless of the event sequence. The output logic state persists so long as the input configuration is maintained.

The highest rate at which the clock input of a bistable circuit
can be driven through its required sequence while maintaining stable transitions of logic level at the output with input
conditions established that should cause changes of output
logic level in accordance with the specification.

If, in the input columns, a row contains (H, L, and/or X) together with
- ' and/or
this means the output is valid whenever the input
configuration is achieved. However, the transition(s) must occur following the application of the steady-state levels. II the output is
shown as a level (H, L, 00 or (0), it will be maintained so long as the
steady-state input levels and the levels that terminate the defined
transitions are maintained. Unless otherwise specified, input transitions in the opposite direction to those shown have no effect on the
steady state output.

PULSE WIDTH
Pulse Width, tw
The time interval between specified reference points on the
leading and trailing edges of the pulse waveform.

10-5

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,------------------------------------------------------------------------------,

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~National

~ Semiconductor
Interface Cross Reference Guide

e

o

CD

U
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-

AMD to National's Interface

"t:
CD

.E

National's
Direct
Replacement

National's
Closest
Replacement

AM26LS30DC
AM26LS30PC
AM26LS31DC
AM26LS31PC
AM26LS32DC
AM26LS32PC
AM26LS33DC
AM26LS33PC

DS3691J
DS3691N
DS26LS31CN
DS26LS31CN
DS26LS32ACJ
DS26LS32ACN
DS26LS33ACJ
DS26LS33ACN

DS26LS32CJ
DS26LS32CN
DS26LS33CJ
DS26LS33CN

AM26S10DC
AM26S10PC
AM26S11DC
AM26S11PC
AM26S12DC
AM26S12PC

DS26S10J
DS26S10N
DS26S11J
DS26S11N

Device
Designation
AMD

DS8838J
DS8838N

AM2965DC
AM2965PC
AM2966DC
AM2966PC

DP84240J
DP84240N
DP84244J
DP84244N

N8T26AB
N8T26AF
N8T28F
N8T28N

DS8T26AN
DS8T26AJ
DS8T28J
DS8T28N

D8212
P8212
D8216
P8216

DP8212J
DP8212N
DP8216J
DP8216N

D8224
AM8224PC
D8226
P8226

DP8224J
DP8224N
DP8226J
DP8226N

AM8228PC
D8228
AM8238PC
D8238
DP8303J
DP8303N
DP8304BJ
DP8304BN
DP8307J
DP8307N
DP8308J
DP8308N

DP8228N
DP8228J
DP8238N
DP8238J
DP8303AJ
DP8303AN
DP8304BJ
DP8304BN
DP8307AJ
DP8307AN
DP8308J
DP8308N

DS8838J
DS8838N

DS8838J
DS8838N

The manufacturer's most current data sheets
take precedence over this guide.

10·6

-5'

Intel to National's Interface
Device
Deslgnat/on

Nat/onal's
Direct
Replacement

INTEL

Nat/onal's
Closest
Replacement

(1)
..,
D)
(')
(1)

o
..,
oen
en

03245

OS3245J

08212
P8212
08216
P8216

OP8212J
OP8212J
OP8216J
OP8216N

08224
08224
08226
P8226

OP8224J
OP8224N
OP8226J
OP8226N

08228
08228
08238
P8238

OP8228J
OP8228N
OP8238J
OP8238N

08286
P8286
08287
P8287

OP8304BJ
OP8304BN
OP8303AJ
OP8303AN

The manufacturer's most current data sheets
take precedence over this guide.

10-7

-

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(1)
(1)
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(1)

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~

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,---------------------------------------------------------------------------------,
Motorola to National's Interface

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.5

Device
Designation

National's
Direct
Replacement

National's
Closest
Replacement

Device
Designation

MOTOROLA
MC12015P
MC12016P
MC12017P
MC12071P

National's
Closest
Replacement

MOTOROLA (Continued)
DS8615N
DS8616N
DS8617N
DS8621N

MC3486L
MC3486P
MC3487L
MC3487P

MC1411P
MC1411P
MC1412P
MC1412P
MC1413P
MC1413P
MC1416P
MC1416P

DS2001N
ILA9665PC
DS2002N
ILA9666PC
DS2003N
ILA9667PC
DS2004N
ILA9668PC

MC3488AP
MC3488AP

MC1472P1
MC1472U

DS3632N
DS3632J·8

MC1488L
MC1488P
MC1489AL
MC1489AP
MC1489L
MC1489P

DS1488J
DS1488N
DS1489AJ
DS1489AN
DS1489J
DS1489N

AM26LS31DC
AM26LS31PC

DS26LS31CJ
DS26LS31CN

MC26S10L
MC26S10P

DS26S10J
DS26S10N

MC3430L
MC3430P
MC3431L
MC3431P
MC3432L
MC3432P
MC3433L
MC3433P
MC3437L
MC3437P
MC3438L
MC3438P

DS3651J
DS3651N

MC3450L
MC3450P
MC3452P

National's
Direct
Replacement

DS3486J
DS3486N
DS3487J
DS3487N
DS9636AN
ILA9636AT

MC3491P

DS3651J
DS3651N
DS3653J
DS3653N
DS3653J
DS3653N
DS8837J
DS8837N
DS8838J
DS8838N
DS3650J
DS3650N
DS3652N

The manufacturer's most current data sheets
take precedence over this guide.

DS8889N

MC6880AL
MC6880AP

DS8T26AJ
DS8T26AN

MC6889L
MC6889P

DS8T28J
DS8T28N

MC75107L
MC75107P
MC75108L
MC75108P
MC75125L

DS75107J
DS75107N
DS75108J
DS75108N
DS75125J

MC75125P
MC75127L
MC75127P
MC75128L
MC75128P
MC75129L
MC75129P

DS75125N
DS75127J
DS75127N
DS75128J
DS75128N
DS75129J
DS75129N

MC75325L

DS75325J

MC75491P
MC75492P

DS75491N
DS75492N

MC8T13L
MC8T13P
MC8T23L
MC8T23P
MC8T24L
MC8T24P

DS75121J
DS75121N
DS75123J
DS75123N
DS75124J
DS75124N

MC8T26AL
MC8T26AP
MC8T28L
MC8T28P

DS8T26AJ
DS8T26AN
DS8T28J
DS8T28N

DS8641N
DS8641J

DS8641N
DS8641N

The manufacturer's most current data sheets
take precedence over this guide.

10·8

DS8834J
DS8834N

Signetics to National's Interface
Device
Designation

National's
Direct
Replacement

National's
Closest
Replacement

CD

:::.

Q)
(')

CD
(')

...,

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SIGNETICS
MC1488F
MC1488N
MC1489AN
MC1489AF
MC1489F
MC1489N

-

:;-

en

DS1488J
DS1488N
DS1489AN
DS1489AJ
DS1489J
DS1489N

:0
CD
CD
CD
:l

...,

(')

NE582F
NE582N

DS75494J
DS75494N

75S107F
75S107N
75S108F
75S108N
75S208F
75S208N

DS75107J
DS75107N
DS75108J
DS75108N
DS75208J
DS75208N

NE5601N
NE5601N
NE5602N
NE5602N
NE5603N
NE5603N
NE5604N
NE5604N

DS2001N
,...A9665PC
DS2002N
,...A9666PC
DS2003N
,...A9667PC
DS2004N
,...A9668PC

N8T13F
N8T13N
N8T15F
N8T15N

DS75121J
DS75121N

N8T23F
N8T23N
N8T24F
N8T24N
N8T26AF
N8T26AN
N8T28F
N8T28N

DS75123J
DS75123N
DS75124J
DS75124N
DS8T26AJ
DS8T26AN
DS8T28J
DS8T28N

N8T34F
N8T34N
N8T37F
N8T37N
N8T38F
N8T38N
N8T380F
N8T380N

DS8834J
DS8834N
DS8837J
DS8837N
DS8838J
DS8838N
DS8836J
DS8836N

DS8820AF
DS8820AN
DS8820F
DS8820N

DS8820AJ
DS8820AN
DS8820J
DS8820N

DS8830F
DS8830N

DS8830J
DS8830N

DS8880F
DS8880N

DS8880J
DS8880N

,...LN2001 N
,...LN2003F
,...LN2003N
,...LN2004F
,...LN2004N

,...A9665PC
,...A9667DC
,...A9667PC
,...A9668DC
,...A9668PC

DS75150J-8
DS75150N

The manufacturer's most current data sheets
take precedence over this guide.

10-9

DS8640J
DS8640N

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National's
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SPRAGUE
UDN3611H
UDN3611M

DS3631J-8
DS3631N

UDN3612H
UDN3612M

DS3632J-8
DS3632N

UDN3613H
UDN3613M

DS3633J-8
DS3633N

UDN3614M

DS3634N

ULN2001
ULN2001
ULN2002
ULN2002
ULN2003
ULN2003
ULN2004
ULN2004

DS2001
/-LA9665
DS2002
/-LA9666
DS2003
/-LA9667
DS2004
/-LA9668

The manufacturer's most current data sheets
take precedence over this guide.

10-10

-

5'

Texas Instruments to National's Interface
Device
Designation

National's
Direct
Replacement

National's
Closest
Replacement

Device
Designation

TEXAS INSTRUMENTS
MC1488J
MC1488N
MC1489AJ
MC1489AN
MC1489J
MC1489N

DS1488J
DS1488N
DS1489AJ
DS1489AN
DS1489J
DS1489N

AM26LS31CJ
AM26LS31CN
AM26LS32ACJ
AM26LS32ACN
AM26LS33AJ
AM26LS33AN

DS26LS31CJ
DS26LS31CN
DS26LS32ACJ
DS26LS32ACN
DS26LS33ACJ
DS26LS33ACN

AM26S10CJ
AM26S10CN
AM26S11CJ
AM26S11CN

DS26S10J
DS26S10N
DS26S11J
DS26S11N

MC3486J
MC3486N
MC3487J
MC3487N

DS3486J
DS3486N
DS3487J
DS3487N

SN74LS424J
SN74LS424N

DS8224J
DS8224N

SN74S412J
SN74S412N
SN74S428N
SN74S436N
SN74S437N
SN74S438N

DP8212J
DP8212N
DP8228N
DP36149N
DP36179N
DP8238N

DS26LS32CJ
DS26LS32CN
DS26LS33CJ
DS26LS33CN

SN75123N
SN75124J
SN75124N
SN75125J
SN75125N
SN75127J
SN75127N
SN75128J
SN75128N
SN75129J
SN75129N

DS75123N
DS75124J
DS75124N
DS75125J
DS75125N
DS75127J
DS75127N
DS75128J
DS75128N
DS75129J
DS75129N

SN75150J
SN75150N
SN75154J
SN75154N

DS75150J-8
DS75150N
DS75154J
DS75154N
DS75160AN
DS75160AN
DS75161AN
DS75161AN
DS75162AN
DS75162AN
DS96172

DS75208J

SN75113J
SN75113N
SN75114J
SN75114N
SN75115J
SN75115N

DS75113J
DS75113N
DS75114J
DS75114N
DS75115J
DS75115N

SN75121J
SN75121N
SN75123J

DS75121J
DS75121N
DS75123J

SN75208BJ
SN75208J
SN75208N

DS75107J
DS75107N
DS75107J
DS75107N
DS75108J
DS75108N
DS75108J
DS75108N

SN75110AD
SN75110AD
SN75110AN
SN75110AN

National's
Closest
Replacement

TEXAS INSTRUMENTS (Continued)

SN75160N
SN75160AN
SN75161N
SN75161AN
SN75162N
SN75162AN
SN75172
SN75172
SN75173
SN75173
SN75174
SN75174
SN75175
SN75175
SN75176A
SN75176A
SN75176A
SN75176A
SN75176A
SN75177
SN75177
SN75177
SN75ALS056N
SN75182J
SN75182N
SN75183J
SN75183N
SN75188J
SN75188N
SN75189AJ
SN75189AN
SN75189J
SN75189N

SN75107AJ
SN75107AN
SN75107BJ
SN75107BN
SN75108AJ
SN75108AN
SN75108BJ
SN75108BN

National's
Direct
Replacement

C'D

DS75110AJ
IlA75110ADC
DS75110AN
IlA75110APC

10-11

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DS96173

IlA96173
DS96174

IlA96174
DS96175

IlA96175
DS75176A
DS96176

IlA96176
DS3695
DS36F95
DS96177

IlA96177
DS96F177
DS3696N
DS8820AJ
DS8820AN
DS8830J
DS8830N
DS1488J
DS1488N
DS1489AJ
DS1489AN
DS1489J
DS1489N

The manufacturer's most current data sheets
take precedence over this guide.

The manufacturer's most current data sheets
take precedence over this guide.

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DS75208J
DS75208N

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Device
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National's
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Device
Designation

TEXAS INSTRUMENTS (Continued)
SN75322
SN75322
SN75325J
SN75325N
SN75361AJG
SN75361AP
SN75363
SN75363
SN75365J
SN75365N
SN75369J
SN75369N

SN75472JG
SN75472P
SN75473JG
SN75473P
SN75474P
SN75477JG
SN75477P

DS75325J
DS75325N
DS75361J-8
DS75361N
DS9643
p.A9643

SN75480N

DS75365J
DS75365N

SN75491AN
SN75491N
SN75492AN
SN75492J
SN75492N
SN75494N

DS0026CJ-8
DS0026CN

DS3669

SN75437ANE
SN75437NE
SN75438NE
SN75450BJ
SN75450BN
SN75451BJG
SN75451BP
SN75452BJG
SN75452BP
SN75453BJG
SN75453BP
SN75454BJG
SN75454BP

DS3658N
DS3658N
DS3658N
DS75450J
DS75450N
DS75451J-8
DS75451N
DS75452J-8
DS75452N
DS75453J-8
DS75453N
DS75454J-8
DS75454N

SN75461JG
SN75461P
SN75462JG
SN75462P
SN75463JG
SN75463P
SN75464JG
SN75464P

DS75461J-8
DS75461N
DS75462J-8
DS75462N
DS75463J-8
DS75463N
DS75464J-8
DS75464N

DS3668
DS3658
DS3658
DS3658

SN75471JG
SN75471P

National's
Closest
Replacement

TEXAS INSTRUMENTS (Continued)
DS9643
p.A9643

SN75435
SN75436
SN75437A
SN75438
SN75440

(Continued)

National's
Direct
Replacement

DS3631J-8
DS3631N

The manufacturer's most current data sheets
take precedence over this guide.

DS3632J-8
DS3632N
DS3633J-8
DS3633N
DS3634N
DS3632J-8
DS3632N
DS8880N
DS75491N
DS75491N
DS75492N
DS75492J
DS75492N
DS75494N

N8T13J
N8T13N

DS75121J
DS75121N

N8T23J
N8T23N
N8T24J
N8T24N
N8T26AJ
N8T26AN

DS75123J
DS75123N
DS75124J
DS75124N
DS8T26AJ
DS8T26AN

DS3680
DS8820AJ
DS8820AN

DS3680
DS8820AJ
DS8820AN

DS8830J
DS8830N

DS8830J
DS8830N

DS8831J
DS8831N

DS8831J
DS8831N

DS8832J
DS8832N

DS8832J
DS8832N

p.A9636A
p.A9636A
p.A9637A
p.A9637A
p.A9638
p.A9638
p.A9639
p.A9639

DS9636A
p.A9636A
DS9637A
p.A9637A
DS9638
p.A9638
DS9639
p.A9639

The manufacturer's most current data sheets
take precedence over this guide.

10-12

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Industry Package Cross-Reference Guide

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National Semiconductor
Application Note 336
Charles Carinalli
Josip Huljev

Understanding Integrated
« Circuit Package Power
Capabilities
z

INTRODUCTION
The short and long term reliability of National Semiconductor's interface circuits, like any integrated circuit, is very dependent on its environmental condition. Beyond the mechanical/environmental factors, nothing has a greater influence on this reliability than the electrical and thermal stress
seen by the integrated circuit. Both of these stress issues
are specifically addressed on every interface circuit data
sheet, under the headings of Absolute Maximum Ratings
and Recommended Operating Conditions.
However, through application calls, it has become clear that
electrical stress conditions are generally more understood
than the thermal stress conditions. Understanding the importance of electrical stress should never be reduced, but
clearly, a higher focus and understanding must be placed on
thermal stress. Thermal stress and its application to interface circuits from National Semiconductor is the subject of
this application note.
FACTORS AFFECTING DEVICE RELIABILITY

Figure 1 shows the well known "bathtub" curve plotting failure rate versus time. Similar to all system hardware (mechanical or electrical) the reliability of interface integrated
circuits conform to this curve. The key issues associated
with this curve are infant mortality, failure rate, and useful
life.

INFANT
MDRTALITY
(SHADED AREA)

w

EARLY LIFE

"

USEFUL LIFE

~

WEARDUT TIME

Failure rate is the number of devices that will be expected to
fail in a given period of time (such as, per million hours). The
mean time between failure (MTBF) is the average time (in
hours) that will be expected to elapse after a unit has failed
before the next unit failure will occur. These two primary
"units of measure" for device reliability are inversely related:
MTBF

1
Failure Rate

Although the "bathtub" curve plots the overall failure rate
versus time, the useful failure rate can be defined as the
percentage of devices that fail per-unit-time during the flat
portion of the curve. This area, called the useful life, extends
between t1 and t2 or from the end of infant mortality to the
onset of wearout. The useful life may be as short as several
years but usually extends for decades if adequate design
margins are used in the development of a system.
Many factors influence useful life including: pressure, mechanical stress, thermal cycling, and electrical stress. However, die temperature during the device's useful life plays an
equally important role in triggering the onset of wearout.
FAILURE RATES vs TIME AND TEMPERATURE
The relationship between integrated circuit failure rates and
time and temperature is a well established fact. The occurrence of these failures is a function which can be represented by the Arrhenius Model. Well validated and predominantly used for accelerated life testing of integrated circuits, the
Arrhenius Model assumes the degradation of a performance
parameter is linear with time and that MTBF is a function of
temperature stress. The temperature dependence is an exponential function that defines the probability of occurrence.
This results in a formula for expressing the lifetime or MTBF
at a given temperature stress in relation to another MTBF at
a different temperature. The ratio of these two MTBFs is
called the acceleration factor F and is defined by the following equation:

TL/F/S2BO-l

F = X1 = exp [~(.!..
X2
K T2

FIGURE 1. Failure Rate vs Time
Infant mortality, the high failure rate from time to to t1 (early
life), is greatly influenced by system stress conditions other
than temperature, and can vary widely from one application
to another. The main stress factors that contribute to infant
mortality are electrical transients and noise, mechanical
maltreatment and excessive temperatures. Most of these
failures are discovered in device test, burn-in, card assembly and handling, and initial system test and operation. Although important, much literature is available on the subject
of infant mortality in integrated circuits and is beyond the
scope of this application note.

= .

_.!..)]
T1

Where: X1 = Failure rate at junction temperature T1

10-16

X2 = Failure rate at junction temperature T2
T = Junction temperature in degrees Kelvin
E = Thermal activation energy in electron volts
(ev)
K = Boltzman's constant

However, the dramatic acceleration effect of junction temperature (chip temperature) on failure rate is illustrated in a
plot of the above equation for three different activation energies in Figure 2. This graph clearly demonstrates the importance of the relationship of junction temperature to device failure rate. For example, using the 0.99 ev line, a 30°
rise in junction temperature, say from 130°C to 160°C, results in a 10 to 1 increase in failure rate.

flows from the chip to the ultimate heat sink, the ambient
environment. There are two predominant paths. The first is
from the die to the die attach pad to the surrounding package material to the package lead frame to the printed circuit
board and then to the ambient. The second path is from the
package directly to the ambient air.
Improving the thermal characteristics of any stage in the
flow chart of Figure 4 will result in an improvement in device
thermal characteristics. However, grouping all these characteristics into one equation determining the overall thermal
capability of an integrated circuit/package/environmental
condition is possible. The equation that expresses this relationship is:

~ loook

lOOk

Q

l-

e

I--t--+__;~-t----::Iff---t

~

10k I--+-+---+---:IIP.;:-.:t~'-i

~

lk I--t--+_~~~~+_--t

~
:!:..
~
~

:3

TJ = TA + Po (OJA)
Where: TJ = Die junction temperature

100

T A = Ambient temperature in the vicinity device

10 I-~~+__;I::::b.....-!F+_--t

Po = Total power dissipation (in watts)

ff

8JA = Thermal resistance junction-to-ambient
60 90 120 150 lBo 210
JUNCTION TEMPERATURE (OC)

8JA, the thermal resistance from device junction-to-ambient
temperature, is measured and specified by the manufacturers of integrated circuits. National Semiconductor utilizes
special vehicles and methods to measure and monitor this
parameter. All interface circuit data sheets specify the thermal characteristics and capabilities of the packages available for a given device under specific conditions-these
package power ratings directly relate to thermal resistance
junction-to-ambient or 8JA.

TL/F/52BO-2

FIGURE 2. Failure Rate as a Function
of Junction Temperature
DEVICE THERMAL CAPABILITIES
There are many factors which affect the thermal capability
of an integrated circuit. To understand these we need to
understand the predominant paths for heat to transfer out of
the integrated circuit package. This is illustrated by Figures
3 and 4.

Although National provides these thermal ratings, it is critical that the end user understand how to use these numbers
to improve thermal characteristics in the development of his
system using interface components.

Figure 3 shows a cross-sectional view of an assembled integrated circuit mounted into a printed circuit board.
Figure 4 is a flow chart showing how the heat generated at
the power source, the junctions of the integrated circuit

DEVICE LEAD

TLIF/52BO-3

FIGURE 3. Integrated Circuit Soldered into a Printed Circuit Board (Cross-Sectional View)

DIE
JUNCTION
(ENERGY
SOURCE)

r--+

DIE

r-+

DIE
ATIACH
PAD

r-+

PACKAGE
MATERIAL

r--+

LEAD
FRAME

r--+

PRINTED
CIRCUIT
BOARD

AIRFILM
AROUND
PACKAGE

--+

AMBIENT

f-+

AMBIENT

TL/F/52BO-4

FIGURE 4. Thermal Flow (Predominant Paths)

10-17

The slope of the straight line between these two points is
minus the inversion of the thermal resistance. This is referred to as the derating factor.

DETERMINING DEVICE OPERATING
JUNCTION TEMPERATURE
From the above equation the method of determining actual
worst-case device operating junction temperature becomes
straightforward. Given a package thermal characteristic,
9JA, worst-case ambient operating temperature, TA(max),
the only unknown parameter is device power dissipation,
Po. In calculating this parameter, the dissipation of the integrated circuit due to its own supply has to be considered,
the dissipation within the package due to the external load
must also be added. The power associated with the load in
a dynamic (switching) situation must also be considered.
For example, the power associated with an inductor or a
capacitor in a static versus dynamic (say, 1 MHz) condition
is significantly different.

UJA

As mentioned, Figure 5 is a plot of the safe thermal operating area for a device in a 16-pin molded DIP. As long as the
intersection of a vertical line defining the maximum ambient
temperature (70°C in our previous example) and maximum
device package power (600 mW) remains below the maximum package thermal capability line the junction temperature will remain below 150°C-the limit for a molded package. If the intersection of ambient temperature and package
power fails on this line, the maximum junction temperature
will be 150°C. Any intersection that occurs above this line
will result in a junction temperature in excess of 150°C and
is not an appropriate operating condition.

The junction temperature of a device with a total package
power of 600 mW at 70°C in a package with a thermal resistance of 63°C/W is 10BoC.
TJ

= 70°C + (63°C/W) x (0.6W) = 10BoC

J----lf-----l---+-MO~DED

~ 2.0

!ii~

MAXIMUM ALLOWABLE JUNCTION TEMPERATURES
What is an acceptable maximum operating junction temperature is in itself somewhat of a difficult question to answer.
Many companies have established their own standards
based on corporate policy. However, the semiconductor industry has developed some defacto standards based on the
device package type. These have been well accepted as
numbers that relate to reasonable (acceptable) device lifetimes, thus failure rates.

-

~

1.6
1.2

MAXIMUM PACKAGE f - ~ THERMAL CAPABILITY f - t---II-''~,....lINE
f-OPERATING"
AREA

~ 0.8

Po = 600 rrAN

~

04
•

~6-PlNPACKAGE-

J

~"

Q

a:

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~

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SlOPE= _--L_

r"

8JA

t-0PERATING~~_~~',,_-4-_-I

POINT TA=70°C_~I~
'~--t

O~~~rl~I__~'~~
25 50 75 100 125 150 175

National Semiconductor has adopted these industry-wide
standards. For devices fabricated in a molded package, the
maximum allowable junction temperature is 150°C. For
these devices assembled in ceramic or cavity DIP packages, the maximum allowable junction temperature is
175°C. The numbers are different because of the differences in package types. The thermal strain associated with the
die package interface in a cavity package is much less than
that exhibited in a molded package where the integrated
circuit chip is in direct contact with the package material.

TEMPERATURE (Oe)
TL/F/S2BO-S

FIGURE 5. Package Power Capability
vs Temperature
The thermal capabilities of all interface circuits are expressed as a power capability at 25°C still air environment
with a given derating factor. This simply states, for every
degree of ambient temperature rise above 25°C, reduce the
package power capability stated by the derating factor
which is expressed in mWrC. For our example-a 9JA of
63°C/W relates to a derating factor of 15.9 mW

Let us use this new information and our thermal equation to
construct a graph which displays the safe thermal (power)
operating area for a given package type. Figure 5 is an example of such a graph. The end points of this graph are
easily determined. For a 16-pin molded package, the maximum allowable temperature is 150°C; at this point no power
dissipation is allowable. The power capability at 25°C is
1.9BW as given by the following calculation:

@

I

2.4
_

The next obvious question is, "how safe is 10BOC?"

Po

1

~

Derating Factor = -

rc.

FACTORS INFLUENCING PACKAGE
THERMAL RESISTANCE
As discussed earlier, improving any portion of the two primary thermal flow paths will result in an improvement in
overall thermal resistance junction-to-ambient. This section
discusses those components of thermal resistance that can
be influenced by the manufacturer of the integrated circuit. It
also discusses those factors in the overall thermal resistance that can be impacted by the end user of the integrated
circuit. Understanding these issues will go a long way in
understanding chip power capabilities and what can be
done to insure the best possible operating conditions and,
thus, best overall reliability.

° = TJ(max)-TA = 150°C-25°C = 19BW
25 C
9JA
630C/W
.

10-1B

l>

z

Ole Size

w•
w

Figure 6 shows a graph of our 16-pin DIP thermal resistance
as a function of integrated circuit die size. Clearly, as the
chip size increases the thermal resistance decreases-this
relates directly to having a larger area with which to dissipate a given power.

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c:.

""'" ""

1

~~
~I--

TL/F/52S0-S

FIGURE 8. Thermal Resistance vs
Board or Socket Mount

60
50

AirFlow
1

2
3 4 5 678910
DIE SIZE (kMll2)
TLlF/52S0-6

FIGURE 6. Thermal Resistance vs Ole Size
Lead Frame Material
Figure 7 shows the influence of lead frame material (both
die attach and device pins) on thermal resistance. This
graph compares our same 16-pin DIP with a copper lead
frame, a Kovar lead frame, and finally an Alloy 43 type lead
frame-these are lead frame materials commonly used in
the industry. Obviously the thermal conductivity of the lead
frame material has a significant impact in package power
capability. Molded interface circuits from National Semiconductor use the copper lead frame exclusively.
170

~_
Z

I-

i!if:i

~ as

~~5

150

=0.~

:Ii

130 1----+-

~

AlLDY42

0.5 L-J.....I-J-L...I.--L....J....J....L...L...L...L..J
500
o
1000
AIR FLOW (LINEAR FEET/MINUTE)

.....

----.I.

I
KOVA;r-- ..
··f .'j

Z

~::!.

When a high power situation exists and the ambient temperature cannot be reduced, the next best thing is to provide air
flow in the vicinity of the package. The graph of Figure 9
illustrates the impact this has on thermal resistance. This
graph plots the relative reduction in thermal resistance normalized to the still air condition for our 16-pin molded DIP.
The thermal ratings on National Semiconductor's interface
circuits data sheets relate to the still air environment.

16-P1N MOLDED DIP
~BOARD MOUNT-STill AIR
.......... I I

~ ~:.= 110
~~
I~

2
3 4 5 6 7 8910
DIE SIZE (kMll2)

TL/F/52S0-9

90 ,.................
&;;;::::"-!...
--I--I+-IH-f-I-H

~

FIGURE 9. Thermal Resistance vs Air Flow

70 1----t-cqPPEr~.....I.d-~

Other Factors

50~--~--~I~~~u
1

2
3 4 5 6 78910
DIE SIZE (kMll2)
TL/F/52S0-7

FIGURE 7. Thermal Resistance vs
Lead Frame Material
Board vs Socket Mount
One of the major paths of dissipating energy generated by
the integrated circuit is through the device leads. As a result
of this, the graph of Figure 8 comes as no surprise. This
compares the thermal resistance of our 16-pin package soldered into a printed circuit board (board mount) compared
to the same package placed in a socket (socket mount).
Adding a socket in the path between the PC board and the
device adds another stage in the thermal flow path, thus
increasing the overall thermal resistance. The thermal capabilities of National Semiconductor's interface circuits are
specified assuming board mount conditions. If the devices
are placed in a socket the thermal capabilities should be
reduced by approximately 5% to 10%.

A number of other factors influence thermal resistance. The
most important of these is using thermal epoxy in mounting
ICs to the PC board and heat sinks. Generally these techniques are required only in the very highest of power applications.
Some confusion exists between the difference in thermal
resistance junction-to-ambient (8JA) and thermal resistance
junction-to-case (8Jd. The best measure of actual junction
temperature is the junction-to-ambient number since nearly
all systems operate in an open air environment. The only
situation where thermal resistance junction-to-case is important is when the entire system is immersed in a thermal bath
and the environmental temperature is indeed the case temperature. This is only used in extreme cases and is the exception to the rule and, for this reason, is not addressed in
this application note.

10-19

NATIONAL SEMICONDUCTOR
PACKAGE CAPABILITIES
Figures 10 and 11 show composite plots of the thermal
characteristics of the most common package types in the
National Semiconductor Interface Circuits product family.
Figure 10 is a composite of the copper lead frame molded
package. Figure 11 is a composite of the ceramic (cavity)
DIP using poly die attach. These graphs represent board
mount still air thermal capabilities. Another, and final, thermal resistance trend will be noticed in these graphs. As the
number of device pins increase in a DIP the thermal resistance decreases. Referring back to the thermal flow chart,
this trend should, by now, be obvious.

bers found in this application note. Insuring that total package power remains under a specified level will guarantee
that the maximum junction temperature will not exceed the
package maximum.
The package power ratings are specified as a maximum
power at 25°C ambient with an associated derating factor
for ambient temperatures above 25°C. It is easy to determine the power capability at an elevated temperature. The
power specified at 25°C should be reduced by the derating
factor for every degree of ambient temperature above 25°C.
For example, in a given product data sheet the following will
be found:
Maximum Power Dissipation· at 25°C
Cavity Package
1509 mW
Molded Package 1476 mW

RATINGS ON INTERFACE CIRCUITS DATA SHEETS
In conclusion, all National Semiconductor Interface Products define power dissipation (thermal) capability. This information can be found in the Absolute Maximum Ratings section of the data sheet. The thermal information shown in this
application note represents average data for characterization of the indicated package. Actual thermal resistance can
vary from ± 10% to ± 15% due to fluctuations in assembly
quality, die shape, die thickness, distribution of heat sources
on the die, etc. The numbers quoted in the interface data
sheets reflect a 15% safety margin from the average num-

• Derate cavity package at 10 mWrc above 25'C; derate molded package
at 11.8 mWrC above 25'C.

If the molded package is used at a maximum ambient temperature of 70°C, the package power capability is 945 mW.
PD @ 70°C= 1476 mW-(11.B mWI"C) X (70°C-25°C)
= 945mW

Molded (N Package) DIp·
Copper Leadframe-HTP
Die Attach Board MountStill Air

Cavity (J Package) DIp·
Poly Ole Attach Board
Mount-Still Air

130
w

-

....z ....

110

t!ffi

~Cii

"':IE

~"'fS

90

70
~~~
:lEz ....
a: c::> °

~t;

50

~::2.

30

I~



2

3

4 5 6 78910

2

DIE SIZE (kMIL2)
'Packages from 8- to 20-pin 0.3 mil width

3

4 5 6 78910

DIE SIZE (kMIL2)
TL/F/S280-10

22-pin 0.4 mil width

'Packages from 8- to 20-pin 0.3 mil width

TL/F/S280-11

. 22-pin 0.4 mil width
24- to 48-pin 0.6 mil width

24- to 40-pin 0.6 mil width

FIGURE 10. Thermal Resistance vs Die Size
vs Package Type (Molded Package)

FIGURE 11. Thermal Resistance vs Ole Size
vs Package Type (Cavity Package)

10-20

l>

Small Outline (SO) Package
Surface Mounting MethodsParameters and Their
Effect on Product Reliabilty

National Semiconductor
Application Note 450
Josip Huljev
W. K. Boey

The SO (small outline) package has been developed to
meet customer demand for ever-increasing miniaturization
and component density.

In order to achieve reliability performance comparable to
DIPs-SO packages are designed and built with materials
and processes that effectively compensate. for their small
size.

COMPONENT SIZE COMPARISON

.
,
OIJ

All SO packages tested on 85%RA, 85°C were assembled
on PC conversion boards using vapor-phase reflow soldering. With this approach we are able to measure the effect of
surface mounting methods on reliability of the process. As
illustrated in Figure A no significant difference was detected
between the long term reliability performance of surface
mounted S.O. packages and the DIP control product for up
to 6000 hours of accelerated 85%/85°C testing.

S.O. Package

I

I

L_.J

-I 1-

TYPICAllY 0.050· lEADSPACING

TL/F/8766-1

Standard DIP Package

SURFACE-MOUNT PROCESS FLOW
The standard process flowcharts for basic surface-mount
operation and mixed-lead insertion/surface-mount operations, are illustrated on the following pages.
Usual variations encountered by users of SO packages are:
• Single-sided boards, surface-mounted components only.
• Single-sided boards, mixed-lead inserted and surfacemounted components.
• Double-sided boards, surface-mounted components only.

-I I-

• Double-sided boards, mixed-lead inserted and surfacemounted components.
TYPICAllY 0.100· UADSPACING

TL/F/8766-2

Because of its small size, reliability of the product assembled in SO packages needs to be carefully evaluated.
SO packages at National were internally qualified for production under the condition that they be of comparable reliability performance to a standard dual in line package under
all accelerated environmental tests. Figure A is a summary
of accelarated bias moisture test performance on 30V bipolar and 15V CMOS product assembled in SO and DIP (control) packages.
V+

In consideration of these variations, it became necessary for
users to utilize techniques involving wave soldering and adhesive applications, along with the commonly-used vaporphase solder reflow soldering technique.
PRODUCTION FLOW

=15VCMOS

30V BIPOLAR
8570 RH/85OC
TEST CONDITION
DIP

o

2000

6000

TEST TIME (HRS)
TL/F/8766-3

FIGURE A

10-21

Basic Surface-Mount Production Flow

z
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Ln
~

z•

Mixed Surface-Mount and Axial-Leaded Insertion
Components Production Flow

Thermal stress of the packages during surface-mounting
processing is more severe than during standard DIP PC
board mounting processes. Figure 8 illustrates package
temperature versus wave soldering dwell time for surface
mounted packages (components are immersed into the
molten solder) and the standard DIP wave soldering process. (Only leads of the package are immersed into the molten solder).

c(

SOLDER TEt.lPERATURE 2600C

o

1 2 3 4 5 6 7

9 10 SEC.

DWELL Tlt.lE
TL/F/8766-6

FIGURE B

For an ideal package, the thermal expansion rate of the
encapsulant should match that of the leadframe material in
order for the package to maintain mechanical integrity during the soldering process. Unfortunately, a perfect matchup
of thermal expansion rates with most presently used packaging materials is scarce. The problem lies primarily with the
epoxy compound.
Normally, thermal expansion rates for epoxy encapsulant
and metal lead frame materials are linear and remain fairly
close at temperatures approaching 160°C, Figure C. At lower temperatures the difference in expansion rate of the two
materials is not great enough to cause interface separation.
However, when the package reaches the glass-transition
temperature (Tg) of epoxy (typically 160-165°C), the thermal expansion rate of the encapsulant increases sharply,
and the material undergoes a transition into a plastic state.
The epoxy begins to expand at a rate three times or more
greater than the metal leadframe, causing a separation at
the interface.

TL/F/8766-5

z

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en
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a.
xLa.I
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La.I
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100 110 120 130 140 150 160 1170 180

Tg

T(OC)
TL/F/8766-26

FIGUREC

10-22

When this happens during a conventional wave soldering
process using flux and acid cleaners, process residues and
even solder can enter the cavity created by the separation
and become entrapped when the material cools. These
contaminants can eventually diffuse into the interior of the
package, especially in the presence of moisture. The result
is die contamination, excessive leakage, and even catastrophic failure. Unfortunately, electrical tests performed immediately following soldering may not detect potential flaws.

The basic component-placement systems available are
classified as:
(a) In-line placement
-

-

- Multiple pickup heads
- Whole array of components placed onto the PCB at
the same time
(d) Sequential/simultaneous placement

Standard DIP package

- X-V moving table, multiple pickup heads system

SO packages vapor-phase reflow soldered on
PC boards
Group 3-6 SO packages wave soldered on PC boards
dwell time 4 seconds

Either a X-V moving table system or a 8, X-V moving
pickup system used

-Individual components picked and placed onto boards

Group 2 -

dwell time 2 seconds

Fixed placement stations

(c) Simultaneous placement

performance on the 30V bipolar process.

456-

o

Boards indexed under head and respective components placed
(b) Sequential placement

Figure 0 is a summary of accelerated bias moisture test

Group 3 -

~

U1

-

Most soldering processes involve temperatures ranging up
to 260°C, which far exceeds the glass-transition temperature of epoxy. Clearly, circuit boards containing SMD packages require tighter process controls than those used for
boards populated solely by DIPs.

Group 1 -

.

>
Z

- Components placed on PCB by successive or simultaneous actuation of pickup heads
The SO package is treated almost the same as surfacemount, passive components requiring correct orientation in
placement on the board.
Pick and Place Action

dwell time 6 seconds
dwell time 10 seconds

o

2000

4000

6000

TEST TIME (HRS)
TLIF/8766-7

FIGURE D

It is clear based on the data presented that SO packages
soldered onto PC boards with the vapor phase reflow process have the best long term bias moisture performance
and this is comparable to the performance of standard DIP
packages. The key advantage of reflow soldering methods
is the clean environment that minimized the potential for
contamination of surface mounted packages, and is preferred for the surface-mount process.

TL/F/8766-8

BAKE

This is recommended, despite claims made by some solder
paste suppliers that this step be omitted.
The functions of this step are:

When wave soldering is used to surface mount components
on the board, the dwell time of the component under molten
solder should be no more than 4 seconds, preferrably under
2 seconds in order to prevent damage to the component.
Non-Halide, or (organic acid) fluxes are highly recommended.

• Holds down the solder globules during subsequent reflow
soldering process and prevents expulsion of small solder
balls.
• Acts as an adhesive to hold the components in place during handling between placement to reflow soldering.
• Holds components in position when a double-sided surface-mounted board is held upside down going into a vapor-phase reflow soldering operation.

PICK AND PLACE

The choice of automatic (all generally programmable) pickand-place machines to handle surface mounting has grown
considerably, and their selection is based on individual
needs and degree of sophistication.

• Removes solvents which might otherwise contaminate
other equipment.
• Initiates activator cleaning of surfaces to be soldered.
• Prevents moisture absorption.

10-23

III

The process is moreover very simple. The usual schedule is
about 20 minutes in a 65°C-95°C (dependent on solvent
system of solder paste) oven with adequate venting. Longer
bake time is not recommended due to the following reasons:

In-Line Conveyorized Vapor-Phase Soldering

J

• The flux will degrade and affect the characteristics of the
paste.

-

• Solder globules will begin to oxidize and cause solderability problems.
• The paste will creep and after reflow, may leave behind
residues between traces which are difficult to remove and
vulnerable to electro-migration problems.

~~

I
-

VAron

L

PRODUCT

I ---BELT-~~--~

~

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COILS

COILS

c:=:::::>
LIQUID

REFLOW SOLDERING
IMMERSION HEATER

There are various methods for reflowing the solder paste,
namely:

TL/F/8766-9

The question of thermal shock is asked frequently because
of the relatively sharp increase in component temperature
from room temperature to 215°C. SO packages mounted on
representative boards have been tested and have shown
little effect on the integrity of the packages. Various packages, such as cerdips, metal cans and TO-5 cans with glass
seals, have also been tested.

• Hot air reflow
• Infrared heating (furnaces)
• Convectional oven heating
• Vapor-phase reflow soldering
• Laser soldering
For SO applications, hot air reflow/infrared furnace may be
used for low-volume production or prototype work, but vapor-phase soldering reflow is more efficient for consistency
and speed. Oven heating is not recommended because of
"hot spots" in the oven and uneven melting may result. Laser soldering is more for specialized applications and requires a great amount of investment.

Vapor-Phase Furnace

HOT GAS REFLOW/INFRARED HEATING

A hand-held or table-mount air blower (with appropriate orifice mask) can be used.
The boards are preheated to about 100°C and then subjected to an air jet at about 260°C. This is a slow process and
results may be inconsistent due to various heat-sink proper.
ties of passive components.
Use of an infrared furnace is the next step to automating the
concept, except that the heating is promoted by use of IR
lamps or panels. The main objection to this method is that
certain materials may heat up at different rates under IR
radiation and may result in damage to these components
(usually sockets and connectors). This could be minimized
by using far-infrared (non-focused) system.
VAPOR-PHASE REFLOW SOLDERING
TL/F/B766-10

Currently the most popular and consistent method, vaporphase soldering utilizes a fluoroinert fluid with excellent
heat-transfer properties to heat up components until the solder paste reflows. The maximum temperature is limited by
the vapor temperature of the fluid.

Batch-Fed Production Vapor-Phase Soldering Unit
SECONDARY
COILS

The commonly used fluids (supplied by 3M Corp) are:
• FC-70, 215°C vapor (most applications) or FX-38
PRIMARY COILS

• FC-71 , 253°C vapor (low-lead or tin-plate)
HTC, Concord, CA, manufactures equipment that utilizes
this technique, with two options:
• Batch systems, where boards are lowered in a basket and
subjected to the vapor from a tank of boiling fluid .
• In-line conveyorized systems, where boards are placed
onto a continuous belt which transports them into a concealed tank where they are subjected to an environment
of hot vapor.
Dwell time in the vapor is generally on the order of 15-30
seconds (depending on the mass of the boards and the
loading density of boards on the belt).

TL/F18766-11

10-24

Solder Joints on a SO-14 Package on PCB

Solder Joints on a SO-14 Package on PCB

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TLIF/8766-12

Tl/F/8766-13

The SO package is molded out of clean, thermoset plastic
compound and has no particular compatibility problems with
most printed circuit board substrates.

The typical lithographic "footprints" for SO packages are
illustrated below. Note that the 0.050" lead center-center
spacing is not easily managed by commercially-available air
pressure, hand-held dispensers.

PRINTED CIRCUIT BOARD

Using a stainless-steel, wire-mesh screen stencilled with an
emulsion image of the substrate pads is by far the most
common and well-tried method. The paste is forced through
the screen by a V-shaped plastic squeegee in a sweeping
manner onto the board placed beneath the screen.
The setup for SO packages has no special requirement
from that required by other surface-mounted, passive components. Recommended working specifications are:

The package can be reliably mounted onto substrates such
as:
• G10 or FR4 glass/resin
• FR5 glass/resin systems for high-temperature
applications
• Polymide boards, also high-temperature
applications
• Ceramic substrates
General requirements for printed circuit boards are:

• Use stainless-steel, wire-mesh screens, #80 or #120,
wire diameter 2.6 mils. Rule of thumb: mesh opening
should be approximately 2.5-5 times larger than the average particle size of paste material.

• Mounting pads should be solder-plated whenever
applicable.

• Use squeegee of Durometer 70.
• Experimentation with squeegee travel speed is recommended, if available on machine used.

• Solder masks are commonly used to prevent solder bridging of fine lines during soldering.
The mask also protects circuits from processing chemical
contamination and corrosion.

• Use solder paste of mesh 200-325.
• Emulsion thickness of 0.005" usually used to achieve a
solder paste thickness (wet) of about 0.008" typical.

If coated over pre-tinned traces, residues may accumulate
at the mask/trace interface during subsequent reflow,
leading to possible reliability failures.
Recommended application of solder resist on bare, clean
traces prior to coating exposed areas with solder.
General requirements for solder mask:
- Good pattern resolution.
- Complete coverage of circuit lines and resistance to
flaking during soldering.
- Adhesion should be excellent on substrate material to
keep off moisture and chemicals.
- Compatible with soldering and cleaning requirements.

• Mesh pattern should be 90 degrees, square grid.
• Snap-off height of screen should not exceed
damage to screens and minimize distortion.

Ye", to avoid

SOLDER PASTE
Selection of solder paste tends to be confusing, due to numerous formulations available from various manufacturers.
In general, the following guidelines are sufficient to qualify a
particular paste for production:

• Particle sizes (see photographs below). Mesh 325 (approximately 45 microns) should be used for general purposes, while larger (solder globules) particles are preferred for lead less components (LCG). The larger particles
can easily be used for SO packages.

SOLDER PASTE SCREEN PRINTING
With the initial choice of printed circuit lithographic design
and substrate material, the first step in surface mounting is
the application of solder paste.

10-25

C)

an
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r------------------------------------------------------------------------------------,
• Composition, generally 60140 or 63/37 Sn/Pb. Use 62/36
Sn/Pb with 2% Ag in the presence of Au on the soldering
area. This formulation reduces problems of metal leaching
from soldering pads.

• Uniform particle distribution. Solder globules should be
spherical in shape with uniform diameters and minimum
amount of elongation (visual under 100/200 x magnification). Uneven distribution causes uneven melting and subsequent expulsion of smaller solder balls away from their
proper sites.

• RMA flux system usually used.
• Use paste with aproximately 88-90% solids.

RECOMMENDED SOLDER PADS FOR SO PACKAGES

so-a, SO-14, SO-16

SO-16L, SO-20

····1
L••••
1-

0.045" : 0.005"

r····~

L••••~05.

0.245"

0.030" :0.005"

0.160"

-l I- -I

0,420" MIN

0,'],"'.
0045"
:0.005"

1-0.050" TYP
TL/F 18766-14

0.030" :0.005"--..1

--1 1-:JTYp
TL/F/8766-15

TLlF/8766-16

Comparison of Particle Size/Shape of Various Solder Pastes
200 X Kester (63/37)

200 x Alpha (62/36/2)

TL/F/8766-18

TL/F/8766-17

10-26

»
z

.

Comparison of Particle SlzelShape of Various Solder Pastes (Continued)

~

Solder Paste Screen on Pads

U1

200 x Fry Metal (63137)

o

TL/F/8766-20

TL/F/8766-19

200 ESL (63137)

TL/F/8766-21

10·27

o

.

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Mixed Surface Mount and Lead Insertion

I

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ADHESIVE

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4

(b) Opposite Sides

(a) Same Side

-

tttt
PREHEAT

SOLDER FLOW
TLIF/8766-24

A typical dual-wave system is illustrated below, showing the
various stages employed. The first wave typically is in turbulence and given a transverse motion (across the motion of
the board). This covers areas where "shadowing" occurs. A
second wave (usually a broad wave) then proceeds to perform the standard soldering. The departing edge from the
solder is such to reduce "icicles," and is still further reduced
by an air knife placed close to the final soldering step. This
air knife will blow off excess solder (still in the fluid stage)
which would otherwise cause shorts (bridging) and solder
bumps.

Dual Wave

AQUEOUS CLEANING
• For volume production, a conveyorized system is often
used with a heated recirculating spray wash (water temperature 130°C), a final spray rinse (water temperature
45-55°C), and a hot (120°C) air/air-knife drying section.
• For low-volume production, the above cleaning can be
done manually, using several water rinses/tanks. Fastdrying solvents, like alcohols that are miscible with water,
are sometimes used to help the drying process.

•

TL/F/8766-25

CONFORMAL COATING

• Neutralizing agents which will react with the corrosive materials in the flux and produce material readily soluble in
water may be used; the choice depends on the type of flux
used.

Conformal coating is recommended for high-reliability PCBs
to provide insulation resistance, as well as protection
against contamination and degradation by moisture.

• Final rinse water should be free from chemicals which are
introduced to maintain the biological purity of the water.
These materials, mostly chlorides, are detrimental to the
assemblies cleaned because they introduce a fresh
amount of ionizable material.

• Complete coating over components and solder joints.

Requirements:
• Thixotropic material which will not flow under the packages or fill voids, otherwise will introduce stress on solder
joints on expansion.
• Compatibility and possess excellent adhesion with PCB
material/ components.
• Silicones are recommended where permissible in
application.

10·29

~r---------------------------------------------------------------

~

<

SMD Lab Support
FUNCTIONS
Demonstration-Introduce first-time users to surfacemounting processes.
Service-Investigate problems experienced by users on
surface mounting.
Reliability Builds-Assemble surface-mounted units for reliability data acquisition.

Techniques-Develop techniques for handling different
materials and processes in surface mounting.
Equipment-In conjunction with equipment manufacturers,
develop customized equipments to handle high density,
new technology packages developed by National.
In-House Expertise-Availability of in-house expertise on
semiconductor research/development to assist users on
packaging queries.

10-30

J?)I National

D Semiconductor

All dimensions are in inches (millimeters)

PIN NO.1
IOENT

0.005
(0.127)

R

~ r- r-

0485
0.050 ±0.005 TYP 0.180
_'_1(1.270 !0.1271
(4.5721
(12.319)
MAX

0.020-0.060

(0.508-1.524)
MIN~i1 , L_..t:==M=A=X==±::t:t;---, --

o.!o~

0.008-0.015
(0203-0.381)

1...1

(0.127)
MIN

0.015-0.023
(0.381-0.584)

L

0.080
(2.032)
TYP

0.290-0.320

MAX

(7.366-8.128)

.J L
0.125-0.200
(3.175-5.080)

0.100 to.01o
(2.540 to.254)
(0.1001(2.540) sse
TYP REL TO LEADS
1 AND 16)

0.150
(3.810)
MIN

DI6C(REV HI

NS Package D16C

--

0.010-0.020 __
(0.254-0.508)

0.408
1-(10.36)--MAX

-- 0.045-0.085
(1.143-2.159)

I--

0.05o±0.005
(1.27o±0.127)

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f---

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0.045 MAX TYP
ALL ENDS

0.25Lo.33o
(6.350 - 8.382)

t

0.130
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IJ

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161514131211109

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0.245-0.285

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(0.102-0.152)

I
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3 • 5

IDENT

0.008-0.015
(0.203-0.381)

X
I

-

TYP 0.015-0.019 __
(0.381-0.483)

B" 'B"T7."',
0.250-0.330
(6.35T 8.382)

I

0.005

--j I- (0.127)
MIN ALL ENDS
FI6B(REV HI

NS Package F16B

10-31

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(3.759-4.572)

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LEADDIA

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0.500

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0.016-0.019
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0.026-0.036

A<~'-"141

0.495-0.505
112.573-12.827)
DIATVP

~------------~~~ ~~~~0~.0=26~-~0.=03~6

(0.660-0.914)

GI2C(REVC)

NS Package G12C

0.165-0.185
(4.191-4.699)
REFERENCE PLANE -+---r--

0.195-0.205 DIA
(4.953-5.207) P.C.

0.100
(2.540) TVP

H08C(REVD)

NS Package HOSC

10-32

0.165-0.1B5
14.191-4.6991

-+----1

0.350-0.370
IB.890-9.39BI
DIA
0.315-0.335
rIB.001-8.509Il
DIA

0.025 MAX
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0.500

0.035
91
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-

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0.016-0.019 DIA TYP--ll(0.406-0.483)

0.015-0.040
(0.381-1.0161

~ 0.028-0.034

4/
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(0.711-0.8641

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0.029-0.045
(0.737-1.1431

HIOC(REV 0)

NS Package H10C

t

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0.025
(0.635) HAD

(100~060o)j
MAX
7
6

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0.310 MAX GLASS
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0.220-0.291
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95° i5°

0.310-0.410
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0.015
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0.010
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0.055

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0.018±0.003 0.125-0.200

--l t-- (0.457±0.076) (3.175-5.0BO)

BOTH ENDS

0.100io.010
(2.540 i 0.254)
J08A (REV H)

NS Package J08A

10-33

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0.025
(0.635)
RAD

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(~I ~~:=:~~;J I~
0290-0.320 I-(':"'-""'1
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NS Package J16A

0.985
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------~

MAX

0.180
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GLASS SEALANT

MAX

0.200
(5.080)

MAX
0.125-0.200
(3.175 - 5.080)

0.008-0.012
(0.203 - 0.305)

t

0.018±o.003 _~II_
(0.457±0.076)

' - - 0.310-0.410
(7.874-10.41)

II

0.100±O.010
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J20AIREVMI

NS Package J20A

1.290

1 - - - - - - - - - (32.766) - - - - - - - _ a

I

0.600
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MAX

fMAX

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i

0.025
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0.514-0.526
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0.590-0.620 ~
114.986-15.748)

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0.005
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0.008-0.012
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+0.025
0.685 -0.060
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0.150
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10-35

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0.060-0.100
11.524-2.540)

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0.Q18 '0.002

0.100 !0.010
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0.125
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(0.457 !0.508)

NS Package J28A

rf':7::.:I~
0.228-0.244

1"T19~~~
LEAD NO.1
IDENT

- . 0.150-0.158
(3.810-4.013)

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0.007-0.010 ALL LEAD TIPS
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0.053-0.069
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0.024 -0.031
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1

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10-36

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=1Fr

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(0.178-0.254)
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0.336 -0.344
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0.004
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ALL LEAD TIPS

0.004-0.010
(0.102 -0.254)

J 1_

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1~---(:;,a95-=-1003;8)-1

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0.228-0.244
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0.01tO.019
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0 020t_O 050
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NS Package M16A

10-37

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0.004-0010
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AFTER LEAD FINISH

t

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0.050
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NS Package M20B

0.032 ± 0.005
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RAD

7

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0.130±0.00S
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0.125-0.140
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0.020
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0.045±0.015
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N08EIREVFI

10-38

--------------------------------------------------------------------------------------1

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0.325
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0.125 _ 0.140
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NS Package N14A

-0.381

0.092
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OIA NOM
(ZX)

~

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0.280
(7.112)
MIN
D.300-D.32D

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3

4

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(1.905 ±0.381)

Ir-

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NI6A(REV E)

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1 - " - - - - - 1.013-1.040
(25.73-26.42)

0.092 x 0.030
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MAX DP

16

15

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-0.381

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(2.540 ±0.254)

(0.457 10.076)
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NS Package N22A

0.062
(1.5751
RAD
PIN NO.1 IDENT

1

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114.731
0.030
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0.600-0.620
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0.075
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0.125-0.145
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1

0.062
(1.&761
RAD

0.550 ±0.005

PIN NO. 11DENT

0.076 to.016
(1.8051D.3811

N'OA(REVE)

NS Package N40A

10·42

4 SPACES AT

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0.050
(1.270)

19

20 1 2

(1.143)
0.045if
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3

0.080
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0.226
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0.310 - 0.330
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0.005-0.015
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0.104-0.118
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0.350:_
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0.385 -0.395
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0.050
(1.270)

0.013 - 0.018
(0.330-0.457)
TYP
0.020
(0.508)
MIN

il

0.026 - 0.032
(0.660 - 0.813)
TYP

15

0.165-0.180
(4.191-4.572)

V20A(REVJ)

NS Package V20A

r

l or

0_032 - 0.040
(0.813-1.016)

(~:~~)
DIA

NOM
PEDESTAl

VIEW A-A

~JI
(1.143)

x45'

0.032-0.040
10.•13-1.0181

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I~..

0.450

0.165-0.180
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0.485-0.495
(12.32-12.57)
saUARE

V2&A(REVGI

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10-43

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r---------------------------------------------------------------------------~

0.526
(13.36)
NOM

~~O~;~~S: ~

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REF

(1.143)

VIEW A-A

0.032-0.040
(0.813-1.016)
MAX

(0.127-0.361)
MAX

0.026 - 0.032
(0.680 - 0.813)

0.104-0.118

~

m

(17.40 -17.65)
SQUARE

V«A (REV H)

NS Package V44A
0.050-0.080
(1.270 - 2.032)

0372-0385
(9.449-9.779)

0.004-0.006
(0.102-0.152)

0.045: --

(1.~~

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0.050 ± 0.005
(1.270±0.127)

D.250!0.370

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0.280 MAX

l

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(7. 112 GLASS

0.245-0.255
(6.223-6.477)

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0.020-0.035
(0.508-0.889)

L

0.015-0.019
(0.381-0.483)

0.250-0.370
(S.350f· 398)

---ll-- --l

f-- 0.005
0.127

MIN

TYP

W14B(REVD)

NS Package W14B

10-44

(1.143)

NOTES

~National

~ Semiconductor
Bookshelf of Technical Support Information
National Semiconductor Corporation recognizes the need to keep you informed about the availability of current technical
literature.
This bookshelf is a compilation of books that are currently available. The listing that follows shows the publication year and
section contents for each book.
Please contact your local National sales office for possible complimentary copies. A listing of sales offices follows this
bookshelf.
We are interested in your comments on our technical literature and your suggestions for improvement.
Please send them to:
Technical Communications Dept. M/S 23-200
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P.O. Box 58090
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For a recorded update of this listing plus ordering information for these books from National's Literature Distribution operation,
please call (408) 749-7378.

ALS/AS LOGIC DATABOOK-1987
Introduction to Bipolar logic • Advanced low Power Schottky • Advanced Schottky

ASIC DESIGN MANUAL/GATE ARRAYS & STANDARD CELL5-1987
SSI/MSI Functions • Peripheral Functions. lSllVlSI Functions • Design Guidelines • Packaging

CMOS LOGIC DATABOOK-1988
CMOS AC Switching Test Circuits and Timing Waveforms. CMOS Application Notes. MM54HC/MM74HC
MM54HCT/MM74HCT. CD4XXX. MM54CXXX/MM74CXXX. Surface Mount

DATA CONVERSION/ACQUISITION DATABOOK-1984
Selection Guides • Active Filters • Amplifiers • Analog Switches • Analog-to-Digital Converters
Analog-to-Digital Display (DVM) • Digital-to-Analog Converters • Sample and Hold • Sensors/Transducers
Successive Approximation Registers/Comparators • Voltage References

DATA COMMUNICATION/LAN/UART DATABOOK-Rev. 1
lAN IEEE 802.3 • High Speed Serial/IBM Data Communications • ISDN Components • UARTs
Modems • Transmission Line Drivers/Receivers

INTERFACE/BIPOLAR LSI/BIPOLAR MEMORY/PROGRAMMABLE LOGIC
DATABOOK-1983
Transmission Line Drivers/Receivers • Bus Transceivers • Peripheral/Power Drivers
level Translators/Buffers • Display Controllers/Drivers • Memory Support • Dynamic Memory Support
Microprocessor Support • Data Communications Support • Disk Support • Frequency Synthesis
Interface Appendices • Bipolar PROMs. Bipolar and ECl RAMs • 2900 Family/Bipolar Microprocessor
Programmable logic

INTUITIVE IC CMOS EVOLUTION-1984
Thomas M. Frederiksen's new book targets some of the most significant transitions in semiconductor technology since the
change from germanium to silicon. Intuitive IC CMOS Evolution highlights the transition in the reduction in defect densities and
the development of new circuit topologies. The author's latest book is a vital aid to engineers, and industry observers who need
to stay abreast of the semiconductor industry.
.

INTUITIVE IC OP AMPS-1984
Thomas M. Frederiksen's new book, Intuitive Ie Op Amps, explores the many uses and applications of different IC op amps.
Frederiksen's detailed book differs from others in the way he focuses on the intuitive groundwork in the basic functioning
concepts of the op amp. Mr. Frederiksen's latest book is a vital aid to engineers, designers, and industry observers who need to
stay abreast of the computer industry.

LINEAR APPLICATIONS HANDBOOK-1986
The purpose of this handbook is to provide a fully indexed and cross-referenced collection of linear integrated circuit
applications using both monolithic and hybrid circuits from National Semiconductor.
Individual application notes are normally written to explain the operation and use of one particular device or to detail various
methods of accomplishing a given function. The organization of this handbook takes advantage of this innate coherence by
keeping each application note intact, arranging them in numerical order, and providing a detailed Subject Index.

LINEAR 1 DATABOOK-1988
Voltage Regulators • Operational Amplifiers • Buffers • Voltage Comparators • Instrumentation Amplifiers • Surface Mount

LINEAR 2 DATABOOK-1988
Active Filters • Analog Switches/Multiplexers • Analog-to-Digital • Digital-to-Analog • Sample and Hold
Sensors • Voltage References • Surface Mount

LINEAR 3 DATABOOK-1988
Audio Circuits • Radio Circuits • Video Circuits • Motion Control • Special Functions • Surface Mount

LINEAR SUPPLEMENT DATABOOK-1984
Amplifiers. Comparators • Voltage Regulators • Voltage References. Converters • Analog Switches
Sample and Hold • Sensors • Filters • Building Blocks. Motor Controllers • Consumer Circuits
Telecommunications Circuits. Speech. Special Analog Functions

LS/S/TTL DATABOOK-1987
Introduction to Bipolar logic • low Power Schottky • Schottky • TTL • low Power

MASS STORAGE HANDBOOK-Rev. 2
Winchester Disk Preamplifiers • Winchester Disk Servo Control • Winchester Disk Pulse Detectors
Winchester Disk Data Separators/Synchronizers and ENDECs • Winchester Disk Data Controller
SCSI Bus Interface Circuits • Floppy Disk Controllers

MEMORY SUPPORT HANDBOOK-1986
Dynamic Memory Control • Error Checking and Correction • Microprocessor Interface and Applications
Memory Drivers and Support

NON-VOLATILE MEMORY DATABOOK-1987
CMOS EPROMs • EEPROMs • Bipolar PROMs

SERIES 32000 DATABOOK-1986
Introduction • CPU-Central Processing Unit • Slave Processors • Peripherals • Data Communications and lAN's
Disk Control and Interface • DRAM Interface. Development Tools • Software Support • Application Notes

RANDOM ACCESS MEMORY DATABOOK-1987
Static RAMs • TTL RAMs • TTL FIFOs • ECl RAMs

RELIABILITY HANDBOOK-1986
Reliability and the Die • Internal Construction. Finished Package. MIL-STD-883. MIL-M-38510
The Specification Development Process • Reliability and the Hybrid Device. VLSIIVHSIC Devices
Radiation Environment • Electrostatic Discharge. Discrete Device. Standardization
Quality Assurance and Reliability Engineering • Reliability and Documentation. Commercial Grade Device
European Reliability Programs • Reliability and the Cost of Semiconductor Ownership
Reliability Testing at National Semiconductor. The Total Militaryl Aerospace Standardization Program
8838/RETSTM Products. MILS/RETSTM Products. 883/RETSTM Hybrids. MIL-M-38510 Class B Products
Radiation Hardened Technology. Wafer Fabrication. Semiconductor Assembly and Packaging
Semiconductor Packages. Glossary of Terms • Key Government Agencies. ANI Numbers and Acronyms
Bibliography. MIL-M-38510 and DESC Drawing Cross Listing

TELECOMMUNICATIONS-1987
Line Card Components • Integrated Services Digital Network Components • Modems
Analog Telephone Components. Application Notes

THE SWITCHED-CAPACITOR FILTER HANDBOOK-1985
Introduction to Filters • National's Switched-Capacitor Filters. Designing with Switched-Capacitor Filters
Application Circuits • Filter Design Program. Nomographs and Tables

TRANSISTOR DATABOOK-1982
NPN Transistors • PNP Transistors • Junction Field Effect Transistors. Selection Guides. Pro Electron Series
Consumer Series • NAINB/NR Series. Process Characteristics Double-Diffused Epitaxial Transistors
Process Characteristics Power Transistors • Process Characteristics JFETs • JFET Applications Notes

VOLTAGE REGULATOR HANDBOOK-1982
Product Selection Procedures • Heat Flow & Thermal Resistance • Selection of Commercial Heat Sink
Custom Heat Sink Design • Applications Circuits and Descriptive Information. Power Supply Design
Data Sheets

48-SERIES MICROPROCESSOR HANDBOOK-1980
The 48-Series Microcomputers. The 48-Series Single-Chip System. The 48-Series Instruction Set
Expanding the 48-Series Microcomputers. Applications for the 48-Series • Development Support
Analog 1/0 Components • Communications Components. Digital 1/0 Components. Memory Components
Peripheral Control Components

NATIONAL SEMICONDUCTOR CORPORATION DISTRIBUTORS
ALABAMA
Arrow Electronics
1015 Henderson Rd.
Huntsville, AL 35818
(205) 837-6955
Bell Industries
1031 Putnam Drive, Suite A
Huntsville, AL 35816
(205) 837-1074
Hamilton/ Avnet
4940 Research Drive NW
Huntsville, AL 35805
(205) 837-7210
TWX: 810 726 2162
Pioneer Technology
4825 University Square
Huntsville, AL 35805
(205) 837-9300
TWX: 810 726 2197
ARIZONA
Anthem Electronics
1727 E Weber Dr.
Tempe, AZ 85281
(602) 966-6600
Arrow Electronics
4134 East Wood SI.
Phoenix, AZ 85040
(602) 437-0750
TWX: 910 951 1550
Bell Industries
1705 W. Fourth SI.
Tempe, AZ 85281
(602) 966-7800
TWX: 910 950 0133
Hamilton/ Avnet
30 South McKemy
Chandler, AZ 85226
(602) 231-5100
TWX: 66 7450
CALIFORNIA-Northern
Anthem Electronics
1040 East Brokaw Rd.
San Jose, CA 95131
(408) 295-4200
TWX: 910 338 2038
Anthem Electronics
4700 Northgate Blvd.
Suite 165
Sacramento, CA 95834
(916) 922-6800
TWX: 510 101 1419
Arrow Electronics
521 Weddell Drive
Sunnyvale, CA 94089
(408) 745-6600
TWX: 910 339 9371
Bell Industries
1161 North Fairoaks Ave.
Sunnyvale, CA 94086
(408) 734-8570
TWX: 910 339 9378

Hamilton/ Avnet
4103 Northgate Blvd.
Sacramento, CA 95834
(916) 925-2216

Hamilton Electro Sales
9650 DeSoto
Chatsworth, CA 91311
(818) 700-0440

Time Electronics
1339 Moffet Park Dr.
Sunnyvale, CA 94089
(408) 734-9888
TWX: 172233

Hamilton/ Avnet
1361B West 190th SI.
Gardena, CA 90248
(213) 217-6751

Zeus Components Inc., Reg 6
N CAlOR/WAlCO/
UTINEINM/ & AZ
1580 Old Oakland Rd. # C205
San Jose, CA 95181
(408) 998-5121
CALIFORNIA-Southern
Anthem Electronics
9369 Carroll Park Dr.
San Diego, CA 92121
(619) 453-9005
TWX: 910 3351515
Anthem Electronics
1 Oldfield Dr.
Irvine, CA 92718
(714) 768-4444
TWX: 910 5951583
Anthem Electronics
20640 Bahama SI.
Chatsworth, CA 91311
(818) 700-1000
TWX: 9104932083
Arrow Electronics
9511 Ridgehaven CI.
San Diego, CA 92123
(619) 565-4800
TWX: 910 3351195
Arrow Electronics
2961 Dow Ave.
Tustin, CA 92680
(714) 838-5422
TWX: 910 595 2860
Arrow Electronics
19748 Dearborn SI.
Chatsworth, CA 91311
(818) 701-7500
TWX: 9104932086
Avnet Electronics
350 McCormick Ave.
Irvine Industrial Complex
Costa Mesa, CA 92626
(714) 754-6050
TWX: 910 5951928
Bell Industries
306 E. Alondra Blvd.
Gardena, CA 90248
(213) 515-1800
Bell Industries
12322 Monarch SI.
Garden Grove, CA 92641
(714) 895-7801
TWX: 910 596 2362

Bell Industries
500 Giuseppe CI. Suite 6
Roseville, CA 95678
(916) 969-3100

Bell Industries
1829 Dehavilland Suite A
Thousand Oaks, CA 91320
(805) 499-6821
TWX: 910321 3799

Hamilton/ Avnet
1175 Bordeaux
Sunnyvale, CA 94086
(408) 743-3355
TWX: 910 339 9332

Hamilton Electro Sales
3170 Pullman Street
Costa Mesa, CA 92626
(714) 641-4159

Hamilton/ Avnet
4545 Viewridge Avenue
San Diego, CA 92123
(619) 571-7510
TWX: 695 415
Hamilton/ Avnet
3002 East G Street
Ontario, CA 91764
(714) 989-4602
Time Electronics
370 South Crenshaw Blvd.
Suite E-l04
Torrance, CA 90503-1727
(213) 320-0880
TWX: 910 349 6650
Time Electronics
2410 E. Cerritos Ave.
Anaheim, CA 92806
(714) 934-0911
TWX: 910 591 1234
Time Electronics
8525 Arjons Drive
San Diego, CA 92126
(619) 586-1331
TWX: 858902
Time Electronics
9751 Independence Ave.
Chatsworth, CA 91311
(818) 998-7200
TWX: 910 380 6274
Zeus Components Inc., Reg 5
San Fernando Valley
5236 Colodny Drive
Agoura Hills, CA 91301
(818) 889-3838
Zeus Components Inc., Reg 5H
All Hughes
22700 Savy Ranch Pkwy.
Yorba Linda, CA 92686
Zeus Components Inc., Reg 8
S CA, SG VLY, OC, SD CTY
22700 Savy Ranch Pkwy.
Yorba Linda, CA 92686
(714) 921-9000
COLORADO
Anthem Electronics
373 Inverness Dr. South
Englewood, CO 80112
(303) 790-4500
Arrow Electronics
7060 S Tucson Way
Suite 136
Englewood, CO 80112
(303) 790-4444
TWX: 910 931 2626
Bell Industries
8155 W. 48th Avenue
Wheatridge, CO 80033
(303) 424-1985
TWX: 910 938 0393
Hamilton/ Avnet
8765 E Orchard Road # 708
Englewood, CO 80111
(303) 779-9998
TWX: 910 935 0787

CONNECTICUT
Arrow Electronics
12 Beaumont Rd.
Wallingford, CT 06492
(203) 265-7741
TWX: 710 476 0162
Hamilton/ Avnet
Commerce Drive
Commerce Park
Danbury, CT 06810
(203) 797-2800
Anthem Electronics
170 Research Parkway
Meridan, CT 06450
(203) 237-2282
Pioneer Northeast
112 Main SI.
Norwalk, CT 06852
(203) 853-1515
TWX: 710 468 3378
Time Electronics
1701 Highland Ave.
Cheshire, CT 06410
(203) 271-3200
TWX: 910 380 6270
FLORIDA
Arrow Electronics
400 Fairway Drive
Deerfield Beach, FL 33441
(305) 429-8200
TWX: 5109559456
Arrow Electronics
37 Skyline Drive #3101
Lake Mary, FL 32746
(407) 323-0252
Bell Industries
10810 72nd SI. North #201
Suite 201
Largo, FL 33543
(813) 541-4434
Bell Industries
638 South Military Trail
Deerfield Beach, FL 33442
(305) 421-1997
Hamilton/ Avnet
6801 N.w. 15th Way
FI. Lauderdale, FL 33309
(305) 971-2900
TWX: 510 956 3097
Hamilton/ Avnet
3197 Tech Drive North
SI. Petersburg, FL 33702
(813) 576-3930
TWX: 8108630374
Hamilton/ Avnet
6947 University Blvd.
Winter Park, FL 32792
(305) 628-3888
Pioneer Technology
221 North Lake Blvd.
Altamonte Springs, FL 32701
(305) 834-9090
TWX: 8108530284
Pioneer Technology
674 South Military Trial
Deerfield Beach, FL 33441
(305) 428-8877
TWX: 5109559653

NATIONAL SEMICONDUCTOR CORPORATION DISTRIBUTORS (Continued)
FLORIDA

(Continued)

Zeus Components Inc., Reg 4
FL, GA, AL, MI, SC & TN
1750 West Broadway
Oviedo, FL 32765
(305) 365-3000
GEORGIA
Arrow Electronics
3155 Northwoods Parkway
Suite A
Norcross, GA 30071
(404) 449-8252
TWX: 810 766 0439
Bell Industries
6690-C Jones Mill Ct.
Norcross, GA 30092
(404) 662-0923
Hamilton! Avnet
58250 Peach Tree Corner E
Norcross, GA 30092
(404) 447-7500
Pioneer Technology
3100F Northwoods Place
Norcross, GA 30071
(404) 448-1711
TWX: 810 766 4515
ILLINOIS
Anthem Electronics
180 Crossen Ave.
Elk Grove Village, IL 60007
(312) 640-6066
Arrow Electronics
1140 West Thorndale Avenue
Itasca, IL 60143
(312) 250-0500
TWX: 910 222 0351
Bell Industries
515 Busse Road
Elk Grove Village, II 60007
(312) 640-1910
TWX: 9102234519
Bell Industries
730 West Kilarney
Urbana, IL 61801
(217) 328-1077
Hamilton! Avnet
1130 Thorndale Ave.
Bensenville, IL 60106
(312) 860-7780
Pioneer Electronics
2171 Executive Dr., Suite 200
Addison, IL 60101
(312) 495-9680
TWX: 910 2221834
INDIANA
Advent Electronics Inc.
8446 Moller Rd.
Indianapolis, IN 46268
(317) 872-4910
TWX: 810 3413228
Arrow Electronics
2495 Directors Row
Suite H
Indianapolis, IN 46241
(317) 243-9353
TWX: 8103413119
Bell Industries
3606 E. Maumee Ave.
Fort Wayne, IN 46803
(219) 423-3422
TWX: 910 997 0701

Bell Industries-Graham Div.
133 S Pennsylvania St.
Indianapolis, IN 46204
(317) 834-8202
TWX: 810 341 3481
Hamilton! Avnet
485 Gradle Dr.
Carmel, IN 46032
(317) 844-9333
TWX: 810 260 3966
Pioneer-Indiana
6408 Castleplace Drive
Indianapolis, IN 46250
(317) 849-7300
IOWA
Advent Electronics
682 58th Ave. Court S.W.
Cedar Rapids, IA 52404
(319) 363-0221
TWX: 9105251337
Arrow Electronics
375 Collins Rd. N.E.
Cedar Rapids, IA 52402
(319) 395-7230
TWX: 9104932086
Bell Industries
1221 Park Place N.E.
Cedar Rapids, IA 52402
(319) 395-0730
Hamilton! Avnet
915 33rd Avenue S.W.
Cedar Rapids, IA 52404
(319) 362-4757
KANSAS
Arrow Electronics
8208 Melrose Dr.
Suite 210
Lenexa, KS 66214
(913) 541-9542
Hamilton! Avnet
9219 Quivira Rd
Overland Park, KS 66215
(913) 888-8900
Pioneer Standard
10551 Lackmann Road
Lenexa, KS 66215
(913) 492-0500
MARYLAND
Arrow Electronics
8300 Guilford Dr.
Columbia, MD 21045
(301) 995-0003
TWX: 710 236 9005
Hamilton! Avnet
6822 Oak Hall Lane
Columbia, MD 21045
(301) 995-3500
TWX: 710 862 1861
Anthem Electronics
9020-A Mendenhall Court
Columbia, MD 21045
(301) 964-0040
TWX: 7108621909
Pioneer Technology
9100 Gaither Road
Gaithersburg, MD 20877
(301) 921-0660
TWX: 7108280545
Time Electronics
9051 Red Branch Rd.
Columbia, MD 21045
(301) 964-3090
TWX: 7108622860

Zeus Components Inc., Reg 2
MD, DE, VA, WVA,
NC,RAYTHEON
8930 Route 108
Columbia, MD 21045
(301) 997-1118
MASSACHUSETTS
Arrow Electronics
25 Upton Drive
Wilmington, MA 01887
(617) 935-5134
TWX: 710 393 6770
Gerber Electronics
128 Carnegie Row
Norwood, MA 02062
(617) 769-6000
TWX: 710 3361987
Hamilton! Avnet
100 Centennial Dr.
Peabody, MA 01960
(617) 531-7430
TWX: 7103930382
Anthem Electronics
38 Jonspin Road
Wilmington, MA 01887
(617) 657-5170
TWX: 710 3321387
Pioneer Northeast
44 Hartwell Avenue
Lexington, MA 02173
(617) 861-9200
TWX: 7103266617
Time Electronics
lOA Centennial Drive
Peabody, MA 01960
(617) 532-6200
TWX: 710 393 0171
Zeus Coomponents Inc., Reg lA
MA, RI, VT, NH, ME & CANADA
429 Marrett Rd.
Lexington, MA 02173
(617) 863-8800
MICHIGAN
Arrow Electronics
3510 Roger Chaffee
Memorial Blvd. S.E.
Grand Rapids, MI 49508
(616) 243-0912
Arrow Electronics
755 Phoenix Dr.
Ann Arbor, MI 48108
(313) 971-8220
TWX: 810 223 6020

Pioneer Standard
13485 Stanford
Livonia, MI48150
(313) 525-1800
TWX: 810 242 3271
R. M. Electronics
4310 Roger B Chaffee
Wyoming, MI 49508
(616) 531-9300
MINNESOTA
Anthem Electronics
10025 Valley View Rd. ill 160
Eden Prairie, MN 55344
(612) 944-5454
Arrow Electronics
5230 73rd Street
Edina, MN 55435
(612) 830-1800
TWX: 910 5763125
Hamilton! Avnet
12400 Whitewater Dr.
Minnetonka, MN 55343-9421
(612) 932-0600
TWX: 910 572 2867
Pioneer-Twin Cities
7625 Golden Triangle Dr.
Suite G
Eden Prairie, MN 55344
(612) 935-5444
TWx: 910 576 2738
MISSOURI
Arrow Electronics
2380 Schuetz Road
St. Louis, MO 63146
(314) 567-6888
TWX: 910 764 0882
Hamilton! Avnet
13743 Shoreline Ct.-East
Earth City, MO 83045
(314) 344-1200
TWX: 910 762 0627
Time Electronics
330 Sovereign Ct.
SI. Louis, MO 63011-4491
(314) 391-6444
TWX: 910 7601893
NEW HAMPSHIRE
Arrow Electronics
3 Perimeter Rd.
Manchester, NH 03103
(603) 668-6968
TWX: 7102201684

Bell Industries
814 Phoenix Dr.
Ann Arbor, MI 48104
(313) 971-9093

Bell Industries-C & H Div.
19 Park Avenue
Hudson, NH 03051
(603) 882-1133
TWX: 7102288959

Hamilton! Avnet
2215 29th St. S.E.
Grand Rapids, MI 49508
(616) 243-8805
TWX: 810 273 6921

Hamilton! Avnet
444 Industrial Dr.
Manchester, NH 03102
(603) 624-9400

Hamilton! Avnet
32487 Schoolcraft Road
Livonia, MI48150
(313) 522-4700
Pioneer Standard
4505 Broadmoor S.E.
Grand Rapids, MI 49508
(616) 698-1800
TWX: 510 600 8456

NEW JERSEY-Northern
Arrow Electronics
6 Century Drive
Parsippany, NJ 07054
(201) 575-5300
TWX: 710 734 4403
Hamilton! Avnet
10 Industrial Rd.
Fairfield, NJ 07006
(201) 575-3390
TWX: 7107344409

NATIONAL SEMICONDUCTOR CORPORATION DISTRIBUTORS
NEW JERSEY-Northern
(Continued)
Anthem Electronics
311 Rt. 46 West
Fairfield, NJ 07006
(201) 227·7960
TWX: 7107344312
Nu Horizons Electronics
39 Route 46
Pinebrook, NJ 07058
(201) 882·8300
Pioneer
45 Route 46
Pine Brook, NJ 07058
(201) 575·3510
TWX: 7107344382

NEW JERSEY-Southern
Arrow Electronics
6000 Lincoln Drive East
Marlton, NJ 08053
(609) 596·8000
TWX: 710 897 0829
Hamilton! Avnet
One Keystone Ave.
Cherry Hill, NJ 08003
(609) 424·0100
TWX: 710 940 0262

NEW MEXICO
Alliance Electronics Inc.
11030 Cochiti S.E.
Albuquerque, NM 87123
(505) 292·3360
TWX: 910 989 1151
Arrow Electronics
2460 Alamo Ave. S.E.
Albuquerque, NM 87106
(505) 243·4566
TWX: 910 9891679

Pioneer Northeast
68 Corporate Drive
Binghamton, NY 13904
(607) 722·9300
TWX: 5102520893
Pioneer Northeast
840 Fairport Rd.
Fairport, NY 14450
(716) 381·7070
TWX: 5102537001
Summit Electronics
916 Main Street
Buffalo, NY 14202
(716) 887·2800
TWX: 710 522 1692
Summit Electronics
292 Commerce Drive
Rochester, NY 14623
(716) 334·8110
Time Electronics
6075 Corporate Dr.
East Syracuse, NY 13057
(315) 432·0355
TWX: 510 1006192

NEW YORK-Metro Area
Arrow Electronics
20 Oser Ave.
Hauppauge, NY 11788
(516) 231·1000
TWX: 510 227 6623
Hamilton! Avnet
833 Motor Parkway
Hauppauge, NY 11788
(516) 434·7413
Hamilton/ Avnet Export Div.
1065 Old Country Rd., #211A
Westbury, NY 11590
(516) 997·6868

NORTH CAROLINA
Arrow Electronics
5240 Greens Dairy Rd.
Raleigh, NC 27604
(919) 876·3132
TWX: 5109281856
Arrow Electronics
938 Burke Street
Winston·Salem, NC 27101
(919) 725·8711
TWX: 510 9313169
Hamilton! Avnet
3510 Spring Forest Road
Raleigh, NC 27601
(919) 878·0810
TWX: 510 9281836
Pioneer Technology
9801·A Southern Pine Blvd.
Charlotte, NC 28210
(704) 527·8188
TWX: 810 621 0366

OHIO
Arrow Electronics
7620 McEwen Rd.
Centerville, OH 45459
(513) 435·5563
TWX: 810 459 1611
Arrow Electronics
6238 Cochran Rd.
Solon, OH 44139
(216) 248·3990
TWX: 810 427 9409

(Continued)

Zeus Components Inc., Reg 3
Dayton (DESC)
2912 Springboro St., Ste. 106
Dayton, OH 45439
(914) 937·7400

OKLAHOMA
Arrow Electronics
12111 E.51stStreet
Tulsa, OK 74146
(918) 252·7537
Hamilton! Avnet
12121 East 51st St.
Suite 102A
Tulsa, OK 74146
(918) 252·7297
Quality Components
3158 South 108th East Ave.
Suite 274
Tulsa, OK 74146
(918) 664·8812
Radio Inc.
1000 South Main Street
Tulsa, OK 74119
(918) 587·9123
TWX: 49 2429

OREGON
Almac·Stroum Electronics
1885 N.W. 169th Place
Beaverton, OR 97006
(503) 629·8090
TWX: 910 467 8743

Bell Industries
444 Windsor Park Drive
Dayton, OH 45459
(513) 435·8660

Anthem Electronics
9705 S.W. Sunshine Ct.
Suite 900
Beaverton, OR 97005
(503) 643·1114

Bell Industries
Micro·MiI Division
118 Westpark Road
Dayton, OH 45459
(513) 434·8231
TWX: 810 4591615

Arrow Electronics
1800 N.W 167th Place
Suite 145
Beaverton, OR 97006
(503) 645·6456
TWX: 910 464 0007

Bell Industries
11728 Linn N.E.
Albuquerque, NM 87123
(505) 292·2700
TWX: 910 989 0625

Anthem Electronics
400 Oser Ave.
Hauppauge, NY 11787
(516) 273·1660
TWX: 510 2271042

Hamilton/ Avnet
2524 Baylor Drive S.E.
Albuquerque, NM 87106
(505) 765·1500
TWX: 910 989 1631

Nu Horizons Electronics
6000 New Horizons Blvd.
Amityville, NY 11701
(516) 226·6000

CAM!OHIO Electronics
749 Miner Road
Highland Heights, OH 44143
(216) 461·4700
TWx: 8104272976

Bell Industries
6024 S.W. Jean Rd.
Lake Oswego, OR 97034
(503) 241·4115
TWX: 910 455 8177

Pioneer
60 Crossways Park West
Woodbury, NY 11797
(516) 921·8700
TWX: 710 326 6617

Hamilton/ Avnet
954 Senate Drive
Dayton, OH 45459
(513) 439·6700
TWX: 810 450 2531

Hamilton/ Avnet
6024 S.W. Jean Rd.
Bldg. C, Suite 10
Lake Oswego, OR 97034
(503) 635·7850

Time Electronics
70 Marcus Boulevard
Hauppauge, NY 11788
(515) 273·0100
TWX: 858881

Hamilton/ Avnet
30325 Bainbridge Rd., Bldg. A
Solon, OH 44139
(216) 831·3500
TWX: 810 427 9452

Zeus Components Inc., Reg 1
NY /ROCKINJ/E PAl CT
100 Midland Ave.
Port Chester, NY 10573
(914) 937·7400

Hamilton/ Avnet
777 Brooksedge Blvd.
Westerville, OH 43081
(614) 882·7004

NEW YORK-Upstate
Arrow Electronics
3375 Brighton·Henrietta
Townline Rd.
Rochester, NY 14623
(716) 427·0300
TWX: 510 253 4766
Hamilton/ Avnet
103 Twin Oaks Drive
Syracuse, NY 13206
(315) 437·2641
TWX: 710 541 1506
Hamilton/ Avnet
2060 Town Line Road
Rochester, NY 14623
(716) 475·9130
TWX: 5102535470

Zeus Components Inc., Reg 1B
Long IslandlNYC
2110 Smithtown Ave.
Ronkonkoma, NY 11779
(516) 737·4500

Pioneer Standard
4800 East 131st Street
Cleveland, OH 44105
(216) 587·3600
TWX: 810 422 2210
Pioneer Standard
4433 Interpoint Blvd.
Dayton, OH 45424
(513) 236·9900
TWX: 810 4591683

PENNSYLVANIA-Eastern
Arrow Electronics
650 Seco Rd.
Monroeville, PA 15146
(412) 856·7000
TWX: 710 797 3894
CAM!RPC IND Electronics
620 Alpha Drive
RIDC Park
Pittsburgh, PA 15238
(412) 782·3770
TWX: 710 795 3126
Hamilton/ Avnet
2800 Liberty Ave.
Pittsburgh, PA 15227
(412) 281·4150

NATIONAL SEMICONDUCTOR CORPORATION DISTRIBUTORS (Continued)
PENNSYLVANIA-Eastern

(Continued)
Anthem Electronics
101 Rock Road
Horsham, PA 19044
(215) 443-5150
Pioneer Technology
261 Gibraltar Road
Horsham, PA 19044
(215) 674-4000
TWX: 5106656778
Pioneer-Pittsburgh
259 Kappa Drive
Ridgepark
Pittsburgh, PA 15238
(412) 782-2300
TWX: 710 795 3122
Time Electronics
600 Clark Ave.
King of Prussia, PA 19406
(215) 337-0900
TWX: 845317
TENNESSEE
Bell Industries
Instate: (800) 752-2050
Out of State: (800) 433-8301
TEXAS
Arrow Electronics
3220 Commander Dr.
Carrollton, TX 75006
(214) 380-6464
TWX: 910 860 5377
Arrow Electronics
2227 West Braker Lane
Austin, TX 78758
(512) 835-4180
TWX: 9108741348
Arrow Electronics
10899 Kinghurst Dr.
Suite 100
Houston, TX 77099
(713) 530-4700
TWX: 910 880 439
Hamilton/ Avnet
2111 West Walnut Hill Ln.
Irving, TX 75062
(214) 550-7755
TWX: 07 32359
Hamilton/ Avnet
4850 Wright Road # 190
Staford, TX 77477
(713) 240-7733
TWX: 910881 5523
Hamilton/ Avnet
1807A West Braker Lane
Austin, TX 78758
(512) 837-8911
TWX: 9108741319
Pioneer Electronics
1826 Kramer Lane
Suite D
Austin, TX 78758
(512) 835-4000
Pioneer Standard
13710 Omega Road
Dallas, TX 75240
(214) 386-7300
TWX: 910 860 5563

Pioneer Electronics
5853 Point West Drive
Houston, TX 77036
(713) 988-5555
TWX: 910 881 1606
Quality Components
1005 Industrial Blvd.
Sugarland, TX 77478
(713) 240-2255
TWX: 910 881 7251
Quality Components
2120M Braker Lane
Austin, TX 78758
(512) 835-0220
TWX: 910 874 1377
Quality Components
4257 Kellway Circle
Addison, TX 75001
(214) 733-4300
TWX: 910 660 5459
Zeus Components Inc., Reg 7
TX, AR, OK, LA, KS, MO, 10, NE
1800 N. Glenville Rd.
Richardson, TX 75081
(214) 783-7010
UTAH

WISCONSIN
Arrow Electronics
200 N. Patrick Blvd.
BrOOkfield, WI 53005
(414) 792-0150
TWX: 910 2621193
Bell Industries
W227 N913 Westmound Ave.
Waukesha, WI 53186
(414) 547-8879
TWX: 910 2621156
Hamilton/ Avnet
2975 Moorland Rd.
New Berlin, WI 53151
(414) 784-4516
Taylor Electric
1000 West Donges Bay Road
Mequon, WI 53092
(414) 241-4321
TWX: 910 262 3414
CANADA
Electro Sonic Inc.
1100 Gordon Baker Road
Willowdale, Ontario M2H 3B3
(416) 494-1666
TWX: 06 525295

Anthem Electronics
1615 West 2200 South #A
Salt Lake City, UT 84119
(801) 973-8555

Hamilton/ Avnet
2550 Boundary Rd. # 105
Burnaby, B.C., V5M 3Z0
(604) 437-6667

Arrow Electronics
1946 W. Parkway Blvd.
Salt Lake City, UT 84119
(801) 973-6913

Hamilton/ Avnet
2816 21st N.E.
Calgary, Alberta T2E 6Z2
(403) 250-9380
TWX: 03 827642

Bell Industries
3639 West 2150 South
Salt Lake City, UT 84120
(801) 972-6969
Hamilton/ Avnet
1585 West 2100 South
Salt Lake City, UT 84117
(801) 972-4300
TWX: 910 925 4018
WASHINGTON
Almac-Stroum Electronics
14360 S.E. Eastgate Way
Bellevue, WA 98007
(206) 643-9992
TWX: 9104442067
Anthem Electronics
5020 148th Ave. N.E.
Suite 103
Redmond, WA 98052
(206) 881-0850
TWX: 910 997 0118
Arrow Electronics
19450 68th Ave. South
Kent, W A 98032
(206) 575-4420
TWX: 910 444 2034
Hamilton/ Avnet
14212 North East 21st
Bellevue, WA 98005
(206) 453-5844

Hamilton/ Avnet
2795 Rue Halpern
SI. Laurent, Quebec H4S 1P8
(514) 335-1000
TWX: 610 421 3731
Hamilton/ Avnet
6845 Redwood Drive 3, 4, 5
Mississauga, Ontario L4V 1Tl
(416) 677-7432
TWX: 6104928867
Hamilton/ Avnet
190 Colonnade Rd.
Nepean, Ontario K2E 7L5
(613) 226-1700
TWX: 053 4971
Semad Electronics Ltd.
243 Place Frontenac
Pointe Claire, Quebec H9R 4Z7
(514) 694-0860
Semad Electronics Ltd.
3700 Gilmore Way #210
Burnaby, B.C. V5G 4Ml
(604) 438-2515
Semad Electronics Ltd.
75 Glendeer Dr. S.E. #210
Calgary, Alberta T2H 2S8
(403) 252-5664

Semad Electronics Ltd.
1827 Woodward Dr. # 303
Ottawa, Ontario K2C OR3
(613) 727-8325
Zentronics
8 Tilbury CI.
Brampton, Ontario L6T 3T4
(416) 451-9600
TWX: 06 97678
Zentronics
Edmonton Sales Office
Edmonton, Alberta T6N 1B2
(403) 468-8306
Zentronics
11400 Bridgeport Rd., Unit 108
Richmond, B.C. V6X 1T2
(604) 273-5575
TWX: 04 355844
Zentronics
155 Colonade Rd. So.
Units 17 & 18
Nepean, Ontario K2E 7Kl
(613) 226-8840
Zentronics
817 McCaffrey SI.
Ville SI. Laurent, Quebec H4T 1N3
(514) 737-9700
Zentronics
93-1313 Border SI.
Winnipeg, Manitoba R3H OX4
(204) 694-1957
Zentronics
Waterloo Sales Office
Waterloo, Quebec H4T 1N3
(800) 387-2329
Zentronics
Saskatoon Sales Office
Saskatoon, Alberta R3H OX4
(306) 955-2207
Zentronics
6815 8th SI. N.E.
Suite 100
Calgary, Alberta T2E 7H7
(403) 272-1021
TWX: 04 355844

SALES OFFICES
ALABAMA
Huntsville
(205) 637-8960
(205) 721-9367
ARIZONA
Tempo
(602) 966-4563

B.C.
Burnaby
(604) 435-8107
CALIFORNIA
Encino
(816) 668-2602
Inglewood
(213) 645-4226
Rosevillo
(916) 766-5577
San Diogo
(619) 567-0666
Santa Clara
(406) 562-5900
Tustin
(714) 259-8880
Woodland Hills
(816) 068-2602
COLORADO
Bouldor
(303) 440-3400
Colorado Springs
(303) 578-3319
Englowood
(303) 700-8090
CONNECTICUT
Fairfiuld
(203) 371-0181
Hamdon
(203) 206-1560

FLORIDA
Boca Raton
(305) 997-8133
Orlando
(305) 629-1720
Sl Petersburg
(613) 577-1360

MINNESOTA
Bloomington
(612) 835-3322
(612) 854-8200

GEORGIA
Atlanta
(404) 396-4048
Norcross
(404) 441-2740

NEW MEXICO
Albuquerque
(505) 884-5601

NEW JERSEY
Paramus
(201) 599-0955

INDIANA
Carmel
(317) 843-7160
Fort Wayne
(219) 464-0722

NEWYORK
Endicott
(607) 757-0200
Fairport
(716) 425-1356
(716) 223-7700
Melville
(516) 351-1000
Wappinger Falls
(914) 296-0680

IOWA
Cedar Rapids
(319) 395-0090

NORTH CAROLINA
Cary
(919) 481-4311

KANSAS
Overland Park
(913) 451-6374

OHIO
Dayton
(513) 435-6686
Highland Heights
(216) 442-1555
(216) 461-0191

ILLINOIS
Schaumburg
(312) 397-6777

MARYLAND
Hanover
(301) 796-6900
MASSACHUSETTS
Burlington
(617) 273-3170
Waltham
(617) 890-4000
MICHIGAN
W. Bloomfield
(313) 855-0166

ONTARIO
Mississauga
(416) 676-2920
Nepean
(404) 441-2740
(613) 596-0411
Woodbridge
(416) 746-7120

OREGON
Portland
(503) 639-5442
PENNSYLVANIA
Horsham
(215) 675-6111
Willow Grove
(215) 657-2711

PUERTO RICO
Rio Piedias
(809) 758-9211
QUEBEC
Dollard Des Ormeaux
(514) 683-0683
Lachine
(514) 636-6525
TEXAS
Austin
(512) 346-3990
Houston
(713) 771-3547
Richardson
(214) 234-3811
UTAH
Salt Lake City
(801) 322-4747
WASHINGTON
Bellevue
(206) 453-9944
WISCONSIN
Brookfield
(414) 782-1618
Milwaukee
(414) 527-3600

~National

~ Semiconductor



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