1988_National_Linear_Databook_Vol_3 1988 National Linear Databook Vol 3

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~

National
Semiconductor
Corporation

400043

Rev. 1

Linear
Databook

3

1988 Edition

General Information
Alphanumeric
Cross Reference Guide by Part Number
Package Cross Reference
Linear Databook 1 Selection Guides
Voltage Regulators
Operational Amplifiers
Buffers
Voltage Comparators
Instrumentation Amplifiers
Linear Databook 2 Selection Guides
Active Filters
Analog Switches/Multiplexers
Analog-to-Digital Converters
Digital-to-Analog Converters
Sample and Hold
Temperature Sensors
Voltage References

Audio Circuits
Radio Circuits

II

PI

Special Functions

I
II
I

Surface Mount

[I

Video Circuits
Motion Control

Appendices/Physical Dimensions
iii

fI

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iv

,-----------------------------------------------------------------------------'r

Linear Products
Introduction

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National Semiconductor Corporation first established itself
as the Linear Leader in 1967 with the introduction of the
FIRST MONOLITHIC VOLTAGE REGULATOR ... LM100.ln
the 20 years since, many of our products were firsts in performance and function. Today, this catalog spans the traditional areas of Op Amps, Voltage Regulators, Voltage References and Temperature Sensors, to Data Acquisition, Communication, Automotive, and Power Plus Control. National
Semiconductor intends to remain a leader in the traditional
product areas while forging ahead into VLSI solutions for analog problems and analog systems.
You can rely on National LINEAR to develop the most comprehensive product offering for use in the commercial, computer, automotive, telecommunication, industrial or military
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The Linear product line is presented in 3 Databooks. All sections are referenced and cross-indexed to provide quick and
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Additional application information is available as specific application notes or completely compiled in the LINEAR APPLICATIONS HANDBOOK. A product cross reference to the
specific application note has been provided. This handbook
and the 3-volume set of Linear Data Books represent a complete base of information to the National LINEAR product
line.

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Product Status Definitions

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Definition of Terms
Data Sheet Identification

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Product Status

Definition

Formative or
In Design

This data sheet contains the design specifications for product
development. Specifications may change in any manner without notice.

First
Production

This data sheet contains preliminary data and supplementary data will
be published at a later date. National Semiconductor Corporation
reserves the right to make changes at any time without notice in order
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Full
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This data sheet contains final specifications. National Semiconductor
Corporation reserves the right to make changes at any time without
notice in order to improve design and supply the best possible product.

National Semiconductor Corporation reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. National does not assume any liability ariSing out of the application or use of any product
or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

vi

Table of Contents
Alphanumeric Index.. ..... .. .. .. .... ........ .... .. .. ... ...... .... ...... ..... . .
Cross Reference by Part Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Cross Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Linear 1 Selection Guides .....................................................
Voltage Regulator Definition ofTerms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Regulator Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operational Amplifiers Definition of Terms .......................................
Operational Amplifiers Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffers Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffers Selection Guide .......................................................
Voltage Comparator Definition ofTerms ............. ...... .... ...... ....... .. . ..
Voltage Comparator Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instrumentation Amplifiers Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instrumentation Amplifiers Selection Guide ......................................
Linear 2 Selection Guides .....................................................
Active Filters Definition ofTerms ...............................................
Active Filters Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Switches/Multiplexers Definition of Terms ................................
Analog SWitches/Multiplexers Selection Guide ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Converters Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Converters Selection Guide....... .. ........ .......... .... ... . ..
Digital-to-Analog Converters Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-to-Analog Converters Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample and Hold Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample and Hold Selection Guide ..............................................
Temperature Sensor Selection Guide.. ...... ..... ..... . .. .. ... ..... .. .... ... . ..
Voltage Reference Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1
13
19
23
24
25
28
29
38
39
40
41
42
43
45
46
47
48
49
50
51
54
55
57
58
59
60

Section 1 Audio Circuits
Definition of Terms .......................................................... .
Selection Guide ............................................................. .
LM377 Dual 2-Watt Audio Amplifier ............................................ .
LM378 Dual 4-Watt Audio Amplifier ............................................ .
LM380 Audio Power Amplifier ................................................. .
LM381 Low Noise Dual Preamplifier ............................................ .
LM382 Low Noise Dual Preamplifier ............................................ .
LM383 7-Watt Audio Power Amplifier ......................................... '"
LM384 5-Watt Audio Power Amplifier ........................................... .
LM386 Low Voltage Audio Power Amplifier ...................................... .
LM387 Low Noise Dual Preamplifier ............................................ .
LM388 1.5-Watt Audio Power Amplifier ......................................... .
LM389 Low Voltage Audio Power Amplifier with NPN Transistor Array .............. .
LM390 1-Watt Battery Operated Audio Power Amplifier ........................... .
LM391 Audio Power Driver .................................................... .
* LM831 Low Voltage Audio Power Amplifier ...................................... .
LM832 Dynamic Noise Reduction System DNR .................................. .
LM1035/LM1036 Dual DC Operated TonelVolume/Balance Circuit. ............... .
LM1037 Dual Four-Channel Analog Switch ...................................... .
LM1038 Dual Four-Channel Analog Switch ...................................... .
LM1040 Dual DC Operated TonelVolume/Balance Circuit with Stereo Enhancement
Facility ................................................................... .
LM1112A Dolby B-Type Noise Reduction Processor ............................. .
"Devices Not Covered In Last Publication

vii

1-3
1-4
1-8
1-9
1-10
1-14
1-18
1-21
1-25
1-30
1-35
1-39
1-45
1-53
1-58
1-69
1-81
1-89
1-99
1-105
1-110
1-120

Table of Contents (Continued)
Section 1 Audio Circuits (Continued)
LM1131A Dual Dolby B-Type Noise Reduction Processor.... ............. ..... ....
* LM1141 Dolby B-C Type Noise Reduction Processor. . . . . . . • . . . . . . . . . . . . . . . . . . . . . .
LM 1818 Electronically Switched Audio Tape System .. . . . . . • . . . . . . . . . . . . . . . . . . . . . .
LM 1837 Low Noise Preamplifier for Autoreversing Tape Playback Systems ..........
LM1875 20-Watt Power Audio Amplifier. ........... .. .. ..... .... ........... .. ...
LM1877 Dual Power Audio Amplifier ............................................
LM1894 Dynamic Noise Reduction System DNR..................................
LM1895 Audio Power Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM1896 Dual Power Audio Amplifier ............................................
LM1897 Low Noise Preamplifier for Tape Playback Systems .......................
LM2002 8-Watt Audio Power Amplifier ..........................................
LM2005 20-Watt Automotive Power Amplifier ....................................
LM2877 Dual 4-Watt Power Audio Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM2878 Dual 5-Watt Power Audio Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM2879 Dual 8-Watt Audio Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LMC835 Digital Controlled Graphic Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
* LMC1992/LMC1993 Computer Controlled Tone and Volume Circuits. . . . . . . . . . . . . . . .
Section 2 Radio Circuits
Definition of Terms .......................................................... .
Selection Guide ............................................................. .
LM1800 Phase-Locked Loop FM Stereo Demodulator ............................ .
LM1863 AM Radio System for Electronically Tuned Radio ........................ .
LM1865/LM19651*LM2065 Advanced FM IF System ............................ .
LM1866 Low Voltage AM/FM Receiver ......................................... .
LM1868 AM/FM Radio System ................................................ .
LM1870 Stereo Demodulator with Blend ........................................ .
LM1871 RC Encoder/Transmitter ............................................. .
LM1872 Radio Control Receiver/Decoder ...................................... .
LM1884 TV Stereo Decoder .................................................. .
LM3089 FM Receiver IF System ............................................... .
LM3189 FM IF System ....................................................... .
LM3361 A Low Voltage/Power Narrow Band FM IF System ....................... .
LM3820 AM Radio System .................................................... .
LM4500A High Fidelity FM Stereo Demodulator with Blend ........................ .
TBA 120S IF Amplifier and Detector ............................................ .
Section 3 Video Circuits
Definition of Terms .......................................................... .
Selection Guide ............................................................. .
* LM592 Differential Video Amplifier ............................................. .
LM733/LM733C Differential Video Amplifier .................................... .
* LM1044 Analog Video Switch ................................................. .
* LM1201 Video Amplifier System ............................................... .
* LM1203 RGB Video Amplifier System .......................................... .
LM1391 Phase-Locked Loop .................................................. .
LM1823 Video IF Amplifier/PLL Detection System ............................... .
LM1880 No-Holds Vertical/Horizontal .......................................... .
* LM1881 Video Sync Separator ................................................ .
LM1886 TV Video Matrix DtoA ............................................... .
LM 1889 TV Video Modulator .................................................. .
LM2889 TV Video Modulator .................................................. .
"Devices Not Covered In Last Publication

viii

1-126
1-131
1-136
1-149
1-161
1-167
1-172
1-180
1-186
1-194
1-202
1-206
1-213
1-220
1-227
1-234
1-249
2-3
2-4
2-8
2-11
2-23
2-37
2-44
2-52
2-58
2-74
2-93
2-96
2-102
2-109
2-114
2-118
2-125
3-3
3-5
3-8
3-13
3-18
3-22
3-23
3-34
3-39
3-46
3-54
3-61
3-68
3-78

Table of Contents (Continued)
Section 4 Motion Control
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• LM621 Brushless Motor Commutator TC ........................................
• LM622 Pulse Width Modulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• LM628 Precision Motion Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• LM18293 Four Channel Push-Pull Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• LM18298 Dual Full-Bridge Driver........... ......... ... .... ........ .. ... .. .... .
Section 5 Special Functions
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM122/LM322/LM2905/LM3905 Precision Timer..... .. .. .. .... .... .. . .... ... ...
LM194/LM394 Super Match Pair. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .
LM195/LM295/LM395 Ultra Reliable Power Transistors. . . . . . . . . . . . . . . . . . . . . . . . . . .
LM555/LM555C Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM556/LM556C Dual Timer ...................................................
LM565/LM565C Phase Locked Loop. ... .. .. ...... .. ........ . .......... ... .. ...
LM566C Voltage Controlled Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• LM567/LM567C Low Power Tone Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM903 Fluid Level Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
* LM1042 Fluid Level Detector. .. ........ . .... .. .... .... .. .. .. ...... ... . . ... .. ...
• LM1211 Broadband Demodulator System .......................................
LM1596/LM1496 Balanced Modulator Demodulator. .... ...... .... ..... ..... .. ...
* LM1801 Battery Operated Power Comparator. ...... .. .. .... .............•.. .. ...
LM1812 Ultrasonic Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM 1815 Adaptive Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM1819 Air-Core Meter Driver. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .
LM1830 Fluid Detector.... ...... ..... ...... ...... ...... .. ...... .. . .. ....... . ..
LM1851 Ground Fault Interrupter.. . .. . ...... .......... .... .... .... ... .... ... . ..
• LM1893/LM2893 Biline Carrier Current Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
* LM19211 Amp Industrial Switch................................................
* LM1946 Over/Under Current Limit Diagnostic Circuits.. ...... ......... .. ..........
• LM 1949 Injector Drive Controller ...............................................
LM1951 Solid State 1 Amp Switch..... ........ . ........ ............ .. . .. .. .....
LM1964 Sensor Interface Amplifier. .. . ...... ... ... .... ............ . .. . .. .. .....
LM2907lLM2917 Frequency to Voltage Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM3045/LM3046/LM3086 Transistor Arrays.. ...... ...... ........ .. . .... ... .....
LM3146 High Voltage Transistor Array....... ............. .... .. .. ..... ... ... ...
LM3909 LED Flasher/Oscillator....... . ..... .... .. ........... .. .. .. ... ... ... .. .
LM3914 Dot/Bar Display Driver ................................................
LM3915 Dot/Bar Display Driver ................................................
LM3916 Dot/Bar Display Driver ................................................
* LMC555 CMOS Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• LMC567 Low Power Tone Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . .
* LMC568 Low Power Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 6 Surface Mount
Surface Mount ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 7 Appendices/Physical Dimensions
Appendix A General Product Marking and Code Explanation .......................
Appendix B Application Note Referenced by Part Number.. .. .... .... ... ... ........
Appendix C Summary of Commercial Reliability Programs. . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix 0 Military Aerospace Programs from National Semiconductor. . . . . . . . . . . . . .
Appendix E Understanding Integrated Circuit Package Power Capabilities. . . . . . . . . • . .
"Devices Not Covered In Last Publication

ix

4-3
4-4
4-15
4-16
4-17
4-23
5-3
5-7
5-19
5-27
5-38
5-46
5-50
5-58
5-62
5-68
5-74
5-82
5-92
5-97
5-105
5-113
5-117
5-125
5-131
5-138
5-160
5-165
5-176
5-184
5-192
5-196
5-210
5-215
5-220
5-227
5-242
5-260
5-280
5-283
5-287
6-3
7-3
7-4
7-10
7-11
7-18

Table of Contents (Continued)
Section 7 Appendices/Physical Dimensions (Continued)
Appendix F How to Get the Right Information from a Datasheet.. .... .... .. ........ .
Appendix G Obsolete Product Replacement Guide. . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix H Products Not Recommended for New Design. . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors

"Devices Not Covered In Last Publication

x

7-23
7-27
7-28
7-29

Alpha-Numeric Index
ADC0800 8-Bit AID Converter ........................................................... Linear 2
ADC0801 8-Bit ILP Compatible AID Converters ............................................ Linear 2
ADC0802 8-Bit ILP Compatible AID Converters ............................................ Linear 2
ADC0803 8-Bit ILP Compatible AID Converters ............................................ Linear 2
ADC0804 8-Bit ILP Compatible AID Converters ............................................ Linear 2
ADC0805 8-Bit ILP Compatible AID Converters ............................................ Linear 2
ADC0808 8-Bit ILP Compatible AID Converters with 8-Channel Multiplexer ...........•........ Linear 2
ADC0809 8-Bit ILP Compatible AID Converters with 8-Channel Multiplexer .................... Linear 2
ADC0811 8-Bit Serial 1/0 AID Converter with 11-Channel Multiplexer ........................ Linear 2
ADC0816 8-Bit ILP Compatible AID Converters with 16-Channel Multiplexer ................... Linear 2
ADC0817 8-Bit ILP Compatible AID Converters with 16-Channel Multiplexer ................... Linear 2
ADC0819 8-Bit Serial 1/0 AID Converter with 19-Channel Multiplexer ........................ Linear 2
ADC0820 8-Bit High Speed ILP Compatible AID Converter with Track/Hold Function ........... Linear 2
ADC0829 ILP Compatible 8-Bit AID with 11-Channel MUX/Digitallnput ....................... Linear 2
ADC0831 8-Bit Serial 1/0 AID Converters with Multiplexer Options ........................... Linear 2
ADC0832 8-Bit Serial 1/0 AID Converters with Multiplexer Options ..................•........ Linear 2
ADC0833 8-Bit Serial 1/0 AID Converter with 4-Channel Multiplexer .......................... Linear 2
ADC0834 8-Bit Serial 1/0 AID Converters with Multiplexer Options ........................... Linear 2
ADC0838 8-Bit Serial 1/0 AID Converters with Multiplexer Options ........................... Linear 2
ADC0841 8-Bit ILP Compatible AID Converter ............................................. Linear 2
ADC0844 8-Bit ILP Compatible AID Converters with Multiplexer Options ......•............... Linear 2
ADC0848 8-Bit ILP Compatible AID Converters with Multiplexer Options ...................... Linear 2
ADC0852 Multiplexed Comparator with 8-Bit Reference Divider .............................. Linear 2
ADC0854 Multiplexed Comparator with 8-Bit Reference Divider .............................. Linear 2
ADC1001 1O-Bit ILP Compatible AID Converters ........................................... Linear 2
ADC1005 10-Bit ILP Compatible AI D Converters ........................................... Linear 2
ADC1021 1O-Bit ILP Compatible AID Converters ........................................... Linear 2
ADC1025 1O-Bit ILP Compatible AID Converters ........................................... Linear 2
ADC1205 12-Bit Plus Sign ILP Compatible AID Converters .................................. Linear 2
ADC1210 12-Bit CMOS AID Converters .................................................. Linear 2
ADC1211 12-Bit CMOS AID Converters .................................................. Linear 2
ADC1225 12-Bit Plus Sign ILP Compatible AID Converters .................................. Linear 2
ADC3511 3%-Digit Microprocessor Compatible AID Converter .............................. Linear 2
ADC3711 3%-Digit Microprocessor Compatible AID Converter .............................. Linear 2
ADD3501 3%-Digit DVM with Multiplexed 7-Segment Output ................................ Linear 2
ADD3701 3%-Digit DVM with Multiplexed 7-Segment Output ............................•... Linear 2
AF100 Universal Active Filter ............................................................ Linear 2
AF150 Universal Wideband Active Filter .................................................. Linear 2
AF151 Dual Universal Active Filter ....................................................... Linear 2
AH0014 Dual DPST-TTTL/DTLD Compatible MOS Analog Switch ............................ Linear 2
AH0014C DPDT Dual DPST-TTTL/DTLD Compatible MOS Analog Switch .................... Linear 2
AH0015C Quad SPST Dual DPST-TTTL/DTLD Compatible MOS Analog Switch ............... Linear 2
AH0019 Dual DPST-TTTL/DTLD Compatible MOS Analog Switch ............................ Linear 2
AH0019C Dual DPST-TTTL/DTLD Compatible MOS Analog Switch .......................... Linear 2
AH5009 Monolithic Analog Current Switch ................................................. Linear 2
AH5010 Monolithic Analog Current Switch ................................................ Linear 2
AH5011 Monolithic Analog Current Switch ................................................ Linear 2
AH5012 Monolithic Analog Current Switch ................................................ Linear 2
AH5020C Monolithic Analog Current Switch ............................................... Linear 2
CD40 16C Quad Bi-Lateral Switch ........................................................ Linear 2
CD4051 BC Single 8-Channel Analog Multiplexer/Demultiplexer .............................. Linear 2

Alpha-Numeric IndexccontinUed)
CD4051 BM Single 8-Channel Analog Multiplexer/Demultiplexer ............................. Linear 2
CD4052BC Dual 8-Channel Analog Multiplexer/Demultiplexer ....•.......................... Linear 2
CD4052BM Dual8-Channel Analog Multiplexer/Demultiplexer ....•.•..........•...........•. Linear 2
CD4053BC Triple 8-Channel Analog Multiplexer/Demultiplexer ..•..........•................ Linear 2
CD4053BM Triple 8-Channel Analog Multiplexer/Demultiplexer ......•....................... Linear 2
CD4066BC Quad Bi-Lateral Switch ......................................•................ Linear 2
CD4066BM Quad Bi-Lateral Switch ....•................................•................ Linear 2
CD4529BC Dual 4-Channel or 8-Channel Analog Data Election ....•......................... Linear 2
DAC0800 8-Bit Digital-to-Analog Converters .....................•.•....................... Linear 2
DAC0801 8-Bit Digital-to-Analog Converters ..............................•................ Linear 2
DAC0802 f;!-Bit Digital-to-Analog Converters ..............................•........•....... Linear 2
DAC0806 8-Bit D/ A Converters .......................................................... Linear 2
DAC0807 8-Bit D/ A Converters .......................................................... Linear 2
DAC0808 8-Bit D/ A Converters ........•.........•.............•...................•..... Linear 2
DAC0830 8-Bit /LP Compatible Double-Buffered D to A Converters ........................... Linear 2
DAC0831 8-Bit /LP Compatible Double-Buffered D to A Converters ........................... Linear 2
DAC0832 8-Bit /LP Compatible Double-Buffered D to A Converters ........................... Linear 2
DAC1000 /LP Compatible, Double-Buffered D to A Converters ...........•.............•..... Linear 2
DAC1001 /LP Compatible, Double-Buffered D to A Converters ....................•.......... Linear 2
DAC1002 /LP Compatible, Double-Buffered D to A Converters ............................... Linear 2
DAC1006 /LP Compatible, Double-Buffered D to A Converters ...•...........•.........•....• Linear 2
DAC1007 /LP Compatible, Double-Buffered D to A Converters ............................... Linear 2
DAC1008 /LP Compatible, Double-Buffered D to A Converters .....••..................•..... Linear 2
DAC1020 12-Bit Binary Multiplying D/ A Converters ................•........................ Linear 2
DAC1021 12-Bit Binary Multiplying D/ A Converters ......................................... Linear 2
DAC1022 12-Bit Binary Multiplying D/ A Converters ....•...........•........................ Linear 2
DAC1208 12-Bit /LP Compatible Double-Buffered D to A Converters .......................•.. Linear 2
DAC1209 12-Bit /LP Compatible Double-Buffered D to A Converters .......................... Linear 2
DAC1210 12-Bit /LP Compatible Double-Buffered D to A Converters .......................... Linear 2
DAC1218 12-Bit Multiplying D/ A Converters .....................................•......... Linear 2
DAC1219 12-Bit Multiplying D/ A Converters ..............................•............•..• Linear 2
DAC1220 12-Bit Binary Multiplying D/ A Converters ..•....•...........•..................... Linear 2
DAC1221 12-Bit Binary Multiplying D/ A Converters ......................................... Linear 2
DAC1222 12-Bit Binary Multiplying D/ A Converters ......................................... Linear 2
DAC1230 12-Bit /LP Compatible Double-Buffered D to A Converters .......................... Linear 2
DAC1231 12-Bit /LP Compatible Double-Buffered D to A Converters .......................... Linear 2
DAC1232 12-Bit /LP Compatible Double-Buffered D to A Converters ......................•... Linear 2
DAC1265 Hi-Speed 12-Bit D/ A Converter with Reference ..............•.................... Linear 2
DAC1265A Hi-Speed 12-Bit D/ A Converter with Reference .................................. Linear 2
DAC1266 Hi-Speed 12-Bit D/ A Converter ................................................. Linear 2
DAC1266A Hi-Speed 12-Bit D/ A Converter ....•........•.......•......................... Linear 2
DAC1655 16-Bit D/ A Converter .......................................................... Linear 2
DM2502 Successive Approximation Registers ............................................. Linear 2
DM2503 Successive Approximation Registers ...........•..........•...................... Linear 2
DM2504 Successive Approximation Registers ...............................•............. Linear 2
HS7067 7 Amp, Multimode, High Efficiency Switching Regulator ............................. Linear 1
HS71 07 7 Amp, Multimode, High Efficiency Switching Regulator ............................. Linear 1
HS9151 Micro-Switching Off-Line Power Converter 1201VAC/ + 5V .......................... Linear 1
LF111 Voltage Comparators ............................................................ Linear 1
LF147 Wide Bandwidth Quad JFET Input Operational Amplifiers ............................. Linear 1
LF155 Low Supply Current ........................•....•..............•................. Linear 1

2

Alpha-Numeric

Index(continued)

LF155 Series Monolothic JFET Input Operational Amplifiers ................................. Linear 1
LF156 Series Monolothic JFET Input Operational Amplifiers ................................. Linear 1
LF156 Wide Band ...................................................................... Linear 1
LF157 Series Monolothic JFET Input Operational Amplifiers ................................. Linear 1
LF157 Wide Band Decompensated (AVMIN = 5) .......................................... Linear 1
LF198 Monolithic Sample and Hold Circuits ............................................... Linear 2
LF198A Monolithic Sample and Hold Circuits .............................................. Linear 2
LF211 Voltage Comparators ............................................................ Linear 1
LF255 Low Supply Current .............................................................. Linear 1
LF256 Wide Band ...................................................................... Linear 1
LF257 Wide Band Decompensated (AVM IN = 5) .......................................... Linear 1
LF298 Monolithic Sample and Hold Circuits ............................................... Linear 2
LF311 Voltage Comparators ............................................................ Linear 1
LF347 Wide Bandwidth Quad JFET Input Operational Amplifiers ............................. Linear 1
LF347A Wide Bandwidth Quad JFET Input Operational Amplifiers ............................ Linear 1
LF351 Wide Bandwidth JFET Input Operational Amplifier .................................... Linear 1
LF353 Wide Bandwidth Dual JFET Input Operational Amplifier ............................... Linear 1
LF355 Low Supply Current .............................................................. Linear 1
LF356 Wide Band ...................................................................... Linear 1
LF357 Wide Band Decompensated (AVMIN = 5) .......................................... Linear 1
LF398A Monolithic Sample and Hold Circuits ......................................•....... Linear 2
LF400C Fast Settling JFET Input Operational Amplifier ..................................... Linear 1
LF401 Precision Fast Settling JFET Input Operational Amplifier .............................. Linear 1
LF411 Low Offset, Low Drift J FET Input Operational Amplifier ............................... Linear 1
LF412 Low Offset, Low Drift Dual JFET Operational Amplifier ................................ Linear 1
LF441 Low Power JFET Input Operational Amplifier ........................................ Linear 1
LF442 Dual Low Power JFET Input Operational Amplifier .................................... Linear 1
LF444 Quad Low Power JFET Input Operational Amplifier ................................... Linear 1
LF455 Series Monolithic JFET Operational Amplifier ........................................ Linear 1
LF456 Series Monolithic JFET Operational Amplifier ........................................ Linear 1
LF457 Series Monolithic JFET Operational Amplifier ........................................ Linear 1
LF1333 Quad SPST JFET Analog Switches ............................................... Linear 2
LF11201 Quad SPST JFET Analog Switches .............................................. Linear 2
LF11202 Quad SPST JFET Analog Switches .............................................. Linear 2
LF11331 Quad SPST JFET Analog Switches .............................................. Linear 2
LF11332 Quad SPST JFET Analog Switches .............................................. Linear 2
LF13006 Digital Gain Set ............................................................... Linear 2
LF13007 Digital Gain Set ............................................................... Linear 2
LF13201 Quad SPST JFET Analog Switches .............................................. Linear 2
LF13202 Quad SPST JFET Analog Switches .............................................. Linear 2
LF13331 Quad SPST JFET Analog Switches .............................................. Linear 2
LF13333 Quad SPST JFET Analog Switches .............................................. Linear 2
LF13508 8-Channel Analog Multiplexer ................................................... Linear 2
LF13509 4-Channel Analog Multiplexer ................................................... Linear 2
LF13741 Monolithic JFET Input Operational Amplifier ....................................... Linear 1
LH0002 Current Amplifier ............................................................... Linear 1
LH0003 Wide Bandwidth Operational Amplifier ............................................ Linear 1
LH0004 High Voltage Operational Amplifier ............................................... Linear 1
LH0020 High Gain Operational Amplifier .................................................. Linear 1
LH0021 1.0 Amp Power Operational Amplifier ............................................. Linear 1
LH0022 High Performance FET Op Amp .................................................. Linear 1

3

Alpha-Numeric Index (Continued)
LH0023 Sample and Hold Circuits ........................................................ Linear 2
LH0023C Sample and Hold Circuits ...................................................... Linear 2
LH0024 High Slew Rate Operational Amplifier ............................................. Linear 1
LH0032 Ultra Fast FET-Input Operational Amplifier ......................................... Linear 1
LH0033 Fast Buffer Amplifiers ........................................................... Linear 1
LH0036 Instrumentation Amplifier ........................................................ Linear 1
LH0038 True Instrumentation Amplifier ................................................... Linear 1
LH0041 0.2 Amp Power Operational Amplifier ............................................. Linear 1
LH0042 Low Cost FET Op Amp .......................................................... Linear 1
LH0043 Sample and Hold Circuits ........................................................ Linear 2
LH0043C Sample and Hold Circuits ...................................................... Linear 2
LH0044 Series Precision Low Noise Operational Amplifiers .................................. Linear 1
LH0045 Two Wire Transmitter ........................................................... Linear 1
LH0052 Precision FET Op Amp .......................................................... Linear 1
LH0053 High Speed Sample and Hold Amplifier ............................................ Linear 2
LH0053C High Speed Sample and Hold Amplifier ..................................•....... Linear 2
LH0061 0.5 Amp Wide Band Operational Amplifier ......................................... Linear 1
LH0062 High Speed FET Operational Amplifier ............................................ Linear 1
LH0070 Series BCD Buffered Reference .................................................. Linear 2
LH0071 Series Precision Buffered Reference .............................................. Linear 2
LH0075 Positive Precision Programmable Regulator ........................................ Linear 1
LH0076 Negative Precision Programmable Regulator ....................................... Linear 1
LH0082 Optical Communication Receiver/Amplifier ........................................ Linear 1
LH0084 Digitally-Programmable-Gain Instrumentation Amplifier .............................. Linear 1
LH0086 Digitally-Programmable-Gain Amplifier ............................................ Linear 1
LH0091 True RMS to DC Converter ...................................................... Linear 2
LH0094 Multifunction Converter ......................................................... Linear 2
LH0101 Power Operational Amplifier ..................................................... Linear 1
LH4001 Wideband Current Buffer ........................................................ Linear 1
.LH4002 Wideband Video Buffer ......................................................... Linear 1
LH4003 Precision RF Closed Loop Buffer ................................................. Linear 1
LH4004 Wideband FET Input Buffer/Amplifier ............................................. Linear 1
LH4006 Precision RF Closed Loop Buffer ................................................. Linear 1
LH4101 Wideband High Current Operational Amplifier ...................................... Linear 1
LH41 01 C Wideband High Current Operational Amplifier ..................................... Linear 1
LH41 04 Fast Settling High Current Operational Amplifier .................................... Linear 1
LH41 05 Precision Fast Settling High Current Operational Amplifier ............... , ........... Linear 1
LM10 Op Amp and Voltage Reference .................................................... Linear 1
LM11 Operational Amplifiers ............................................................ Linear 1
LM 12(L) 150W Operational Amplifier ..................................................... Linear 1
LM34 Precision Fahrenheit Temperature Sensors .......................................... Linear 2
LM34A Precision Fahrenheit Temperature Sensors ......................................... Linear 2
LM34C Precision Fahrenheit Temperature Sensors ......................................... Linear 2
LM34CA Precision Fahrenheit Temperature Sensors ....................................... Linear 2
LM34D Precision Fahrenheit Temperature Sensors ........................................ Linear 2
LM35 Precision FahrenheitTemperature Sensors .......................................... Linear 2
LM35A Precision Fahrenheit Temperature Sensors ......................................... Linear 2
LM35C Precision Fahrenheit Temperature Sensors ......................................... Linear 2
LM35CA Precision Fahrenheit Temperature Sensors ....................................... Linear 2
LM35D Precision Fahrenheit Temperature Sensors ........................................ Linear 2
LM78LXX Series 3-Terminal Positive Regulator ................................ .' ........... Linear 1

4

Alpha-Numeric Index (Continued)
LM78XX Series Voltage Regulator ....................................................... Linear 1
LM79LXXAC Series 3-Terminal Negative Regulator ........................................ Linear 1
LM79XX Series 3-Terminal Negative Regulator ............................................ Linear 1
LM1 01 A Operational Amplifiers .......................................................... Linear 1
LM 102 Voltage Follower ................................................................ Linear 1
LM103 Reference Diode ................................................................ Linear 2
LM104 Negative Regulator .............................................................. Linear 1
LM105 Voltage Regulator ...................•.........................................•. Linear 1
LM106 Voltage Comparator ............................................................. Linear 1
LM 107 Operational Amplifiers ........................................................... Linear 1
LM108 Operational Amplifiers ........................................................... Linear 1
LM 108A Operational Amplifiers .......................................................... Linear 1
LM109 5-Volt Regulator ................................................................ Linear 1
LM110 Voltage Follower ................................................................ Linear 1
LM111 Voltage Comparator ............................................................. Linear 1
LM 112 Operational Amplifiers ........................................................... Linear 1
LM113 Precision Reference ............................................................. Linear 2
LM117 3-Terminal Adjustable Regulator .................................................. Linear 1
LM117HV 3-Terminal Adjustable Regulator ................................................ Linear 1
LM 118 Operational Amplifiers ........................................................... Linear 1
LM119 High Speed Dual Comparator ..............................•..•................... Linear 1
LM120 Series 3-Terminal Negative Regulator .............................................. Linear 1
LM122 Precision Timer ...............................•..................................... 5-7
LM123 3 Amp, 5-Volt Positive Regulator .................................................. Linear 1
LM 124 Low Power Quad Operational Amplifiers ............................................ Linear 1
LM125 Voltage Regulators .............................................................. Linear 1
LM126 Voltage Regulators .............................................................. Linear 1
LM129 Precision Reference ............................................................. Linear 2
LM131 Precision Voltage-to-Frequency Converters ......................................... Linear 2
LM131 A Precision Voltage-to-Frequency Converters ....................................... Linear 2
LM133 3-Amp Negative Adjustable Voltage Regulator ...................................... Linear 1
LM134 3-Terminal Adjustable Current Sources ............................................ Linear 2
LM 135 Precision Temperature Sensors ................................................... Linear 2
LM 135A Precision Temperature Sensors .................................................. Linear 2
LM136-2.5V Reference Diode ..................................•........................ Linear 2
LM136-5.0V Reference Diode ........................................................... Linear 2
LM137 3-Terminal Negative Adjustable Regulator .......................................... Linear 1
LM137HV 3-Terminal Negative Adjustable Regulators (High Voltage) ......................... Linear 1
LM138 5 Amp Adjustable Power Regulator ................................................ Linear 1
LM139 Low Power Low Offset Voltage Quad Comparators .................................. Linear 1
LM140 Series 3-Terminal Positive Regulators .......................... , ................... Linear 1
LM140L Series 3-Terminal Positive Regulators ...................•........................ Linear 1
LM143 High Voltage Operational Amplifier ................................................ Linear 1
LM144 High Voltage, High Slew Rate Operational Amplifiers ........•........................ Linear 1
LM 145 Negative 3 Amp Regulator ....................................................... Linear 1
LM146 Programmable Quad Operational Amplifiers ...............•........................ Linear 1
LM148 Quad 741 Op Amps ............................................................. Linear 1
LM149 Wide Band Decompensated (AV(MIN) = 5) ........................................ Linear 1
LM150 3 Amp Adjustable Power Regulator ................................................ Linear 1
LM158 Low Power Dual Operational Amplifiers ............................................ Linear 1
LM160 High Speed Differential Comparator ............................................... Linear 1

5

Alpha-Numeric Index (Continued)
LM161 High Speed Differential Comparator ........................•.....•............•... Linear 1
LM168 Precision Voltage Reference ...................................................... Linear 2
LM169 Precision Voltage Reference .................................•............•......• Linear 2
LM185 Adjustable Micropower Voltage References ...........................•............ Linear 2
LM185-1.2 MicropowerVoltage Reference Diode .......................................... Linear 2
LM185-2.5 Micropower Voltage Reference Diode ..................................•....... Linear 2
LM192 Low Power Operational Amplifier/Voltage Comparator ............................... Linear 1
LM193 Low Power Low Offset Voltage Dual Comparator .........••......................... Linear 1
LM194 Super Match Pair ...............................•...............•.................. 5-19
LM195 Ultra Reliable Power Transistors ..................................................... 5-27
LM196 10 Amp Adjustable Voltage Regulator .............................................. Linear 1
LM199 Precision Reference .. '..................................................••......• Linear 2
LM201 A Operational Amplifiers .......................................................... Linear 1
LM204 Negative Regulator ...............................................•.............. Linear 1
LM205 Voltage Regulator ............................................................... Linear 1
LM206 Voltage Comparator ............................................................. Linear 1
LM207 Operational Amplifiers ................................................•.......... Linear 1
LM208 Operational Amplifiers ................•..•........................•.............. Linear 1
LM208A Operational Amplifiers .......................................................... Linear 1
LM210 Voltage Follower ................................................................ Linear 1
LM211 Voltage Comparator .......................................•..................... Linear 1
LM212 Operational Amplifiers ........................................................... Linear 1
LM218 Operational Amplifiers ........................................................... Linear 1
LM219 High Speed Dual Comparator ..........................•...........•.............. Linear 1
LM221 Precision Preamplifiers ............................•.............................. Linear 1
LM224 Low Power Quad Operational Amplifiers ............................................ Linear 1
LM231 Precision Voltage-to-Frequency Converters ......................•.................. Linear 2
LM231 A Precision Voltage-to-Frequency Converters ................................•...... Linear 2
LM234 3-Terminal Adjustable Current Sources ......................•..................... Linear 2
LM235 Precision Temperature Sensors ...................................• , .............. Linear 2
LM235A Precision Temperature Sensors .................................................. Linear 2
LM236-2.5V Reference Diode ...........................................•....•.......... Linear 2
LM236-5.0V Reference Diode .....................................•..................... Linear 2
LM239 Low Power Low Offset Voltage Quad Comparators .................................. Linear 1
LM246 Programmable Quad Operational Amplifiers ....•.............•..................... Linear 1
LM248 Quad 741 Op Amps ............................................•.............•.. Linear 1
LM249 Wide Band Decompensated (AV(MIN) = 5) ........................................ Linear 1
LM258 Low Power Dual Operational Amplifiers ............................................ Linear 1
LM260 High Speed Differential Comparator ............................................... Linear 1
LM261 High Speed Differential Comparator ...........•................................... Linear 1
LM268 Precision Voltage Reference ...........................................•.......... Linear 2
LM285 Adjustable Micropower Voltage References ........................................ Linear 2
LM285-1.2 Micropower Voltage Reference Diode .......................................... Linear 2
LM285-2.5 Micropower Voltage Reference Diode .......................................... Linear 2
LM292 Low Power Operational Amplifier /Voltage Comparator ............................... Linear 1
LM293 Low Power Low Offset Voltage Dual Comparator ............•.............•......... Linear 1
LM295 Ultra Reliable Power Transistors ............................................•........ 5-27
LM299 Precision Reference ..................•.......................................... Linear 2
LM301 A Operational Amplifiers .............................•.......................•.... Linear 1
LM302 Voltage Follower .....................•.......................................... Linear 1
LM304 Negative Regulator ........................................•..................... Linear 1

6

Alpha-Numeric Index (Continued)
LM305 Voltage Regulator ............................................................... Linear 1
LM305A Voltage Regulator ............................................................. Linear 1
LM306 Voltage Comparator ............................................................. Linear 1
LM307 Operational Amplifiers ........................................................... Linear 1
LM308 Operational Amplifiers ........................................................... Linear 1
LM308A Operational Amplifiers .......................................................... Linear 1
LM309 5-Volt Regulator ................................................................ Linear 1
LM310 Voltage Follower ................................................................ Linear 1
LM311 Voltage Comparator ..............................................•.............. Linear 1
LM312 Operational Amplifiers ........................................................... Linear 1
LM313 Precision Reference ............................................................. Linear 2
LM317 3-Terminal Adjustable Regulator .................................................. Linear 1
LM317HV 3-Terminal Adjustable Regulator ................................................ Linear 1
LM317L 3-Terminal Adjustable Regulator ................................................. Linear 1
LM318 Operational Amplifiers ........................................................... Linear 1
LM319 High Speed Dual Comparator ..................................................... Linear 1
LM320 Series 3-Terminal Negative Regulator .............................................. Linear 1
LM320L 3-Terminal Negative Regulator ................................................... Linear 1
LM321 Precision Preamplifiers ........................................................... Linear 1
LM322 Precision Timer ..................................................................... 5-7
LM324 Low Power Quad Operational Amplifiers ............................................ Linear 1
LM325 Voltage Regulators .............................................................. Linear 1
LM326 Voltage Regulators .............................................................. Linear 1
LM329 Precision Reference ............................................................. Linear 2
LM330 3-Terminal Positive Regulator ..................................................... Linear 1
LM331 Precision Voltage-to-Frequency Converters ......................................... Linear 2
LM331 A Precision VOltage-to-Frequency Converters ....................................... Linear 2
LM333 3-Amp Negative Adjustable Voltage Regulator ...................................... Linear 1
LM334 3-Terminal Adjustable Current Sources ............................................ Linear 2
LM335 Precision Temperature Sensors ................................................... Linear 2
LM335A Precision Temperature Sensors .................................................. Linear 2
LM336-2.5V Reference Diode ........................................................... Linear 2
LM336-5.0V Reference Diode ........................................................... Linear 2
LM337 3-Terminal Negative Adjustable Regulator .......................................... Linear 1
LM337HV 3-Terminal Negative Adjustable Regulators (High Voltage) ......................... Linear 1
LM337L 3-Terminal Adjustable Regulator ................................................. Linear 1
LM338 5 Amp Adjustable Power Regulator ................................................ Linear 1
LM339 Low Power Low Offset Voltage Quad Comparators .................................. Linear 1
LM340 Series 3-Terminal Positive Regulators .............................................. Linear 1
LM340L Series 3-Terminal Positive Regulators ............................................ Linear 1
LM343 High Voltage Operational Amplifier ................................•.•............. Linear 1
LM344 High Voltage, High Slew Rate Operational Amplifiers ................................. Linear 1
LM345 Negative 3 Amp Regulator ....................................................... Linear 1
LM346 Programmable Quad Operational Amplifiers ........................................ Linear 1
LM348 Quad 741 Op Amps ............................................................. Linear 1
LM349 Wide Band Decompensated (AV(MIN) = 5) ........................................ Linear 1
LM350 3 Amp Adjustable Power Regulator ................................................ Linear 1
LM358 Low Power Dual Operational Amplifiers ............................................ Linear 1
LM359 Dual, High Speed, Programmable Current Mode (Norton) Amplifier .................... Linear 1
LM360 High Speed Differential Comparator ............................................... Linear 1
LM361 High Speed Differential Comparator ............................................... Linear 1

7

Alpha-Numeric

Index(ContinUed)

LM363 Precision Instrumentation Amplifier ................................................ Linear 1
LM368 Precision Voltage Reference ...................................................... Linear 2
LM368-2.5 Precision Voltage Reference ...•.............................................. Linear 2
LM369 Precision Voltage Reference ...................................................... Linear 2
LM376 Voltage Regulator ............................................................... Linear 1
LM377 Dual 2-Watt Audio Amplifier .......................................................... 1-8
LM378 Dual 4-Watt Audio Amplifier .......................................................... 1-9
LM380 Audio Power Amplifier .....................•........................•............... 1-10
LM381 Low Noise Dual Preamplifier ......................................................... 1-14
LM382 Low Noise Dual Preamplifier ......................................................... 1-18
LM383 7-Watt Audio Power Amplifier ........................................................ 1-21
LM384 5-Watt Audio Power Amplifier ........................................................ 1-25
LM385 Adjustable Micropower Voltage References ........................................ Linear 2
LM385-1.2 Micropower Voltage Reference Diode .........................................• Linear 2
LM385-2.5 Micropower Voltage Reference Diode .........................•.............•.. Linear 2
LM386 Low Voltage Audio Power Amplifier .................................................. 1-30
LM387 Low Noise Dual Preamplifier ......................................................... 1-35
LM388 1.5-Watt Audio Power Amplifier .•.................................................... 1-39
LM389 Low Voltage Audio Power Amplifier with NPN Transistor Array ............•.............. 1-45
LM390 1-Watt Battery Operated Audio Power Amplifier ........................................ 1-53
LM391 Audio Power Driver ................................................................. 1-58
LM392 Low Power Operational Amplifier/Voltage Comparator ............................... Linear 1
LM393 Low Power Low Offset Voltage Dual Comparator .................................... Linear 1
LM394 Super Match Pair ........................................•......................... 5-19
LM395 Ultra Reliable Power Transistors ..................................................... 5-27
LM396 10 Amp Adjustable Voltage Regulator .............................................. Linear 1
LM399 Precision Reference ............................................................. Linear 2
LM555 Timer ............................................................................ 5-38
LM555C Timer ........................•.................................................. 5-38
LM556 Dual Timer ..................................................•..................... 5-46
LM556C Dual Timer ...................................................................... 5-46
LM565 Phase Locked Loop .....................................•.......................... 5-50
LM565C Phase Locked Loop .................................•............................ 5-50
LM566C Voltage Controlled Oscillator ....................................................... 5-58
LM567 Low Power Tone Decoder .......................................................... 5-62
LM567C Low Power Tone Decoder ......................................................... 5-62
LM581 Voltage Reference Precision 10-Volt. .............................................. Linear 2
LM592 Differential Video Amplifier ........................................................... 3-8
LM604 4 Channel MUX-Amp ...................................................•........ Linear 1
LM607 Precision Operational Amplifier ................................................... Linear 1
LM611 Adjustable Micropower Floating Voltage Reference and Single-Supply Operational
Amplifier ............................................................•............... Linear 1
LM614 Adjustable Micropower Floating Voltage Reference and Four Single-Supply Operational
Amplifiers ...........................................................•............... Linear 1
LM621 Brushless Motor Commutator TC ...................................................... 4-4
LM622 Pulse Width Modulator ............................................................. 4-15
LM628 Precision Motion Controller ......................................................... 4-16
LM675 Power Operational Amplifier .......•.............................................. Linear 1
LM723 Voltage Regulator ............................................................... Linear 1
LM733 Differential Video Amplifier .......................................................... 3-13
LM733C Differential Video Amplifier ......................................................... 3-13

8

Alpha-Numeric Index (Continued)
LM741 Operational Amplifier ............................................................ Linear 1
LM831 Low Voltage Audio Power Amplifier .................................................. 1-69
LM832 Dynamic Noise Reduction System DNR ............................................... 1-81
LM833 Dual Audio Operational Amplifier .................................................. Linear 1
LM837 Low Noise Quad Operational Amplifier ............................................. Linear 1
LM903 Fluid Level Detector ................................................................ 5-68
LM1035 Dual DC Operated TonelVolume/Balance Circuit ..................................... 1-89
LM1036 Dual DC Operated TonelVolume/Balance Circuit ..................................... 1-89
LM1037 Dual Four-Channel Analog Switch .................................................. 1-99
LM1038 Dual Four-Channel Analog Switch ................................................. 1-105
LM1040 Dual DC Operated TonelVolume/Balance Circuit with Stereo Enhancement FaCility ...... 1-110
LM 1042 Fluid Level Detector ............................................................... 5-74
LM1044 Analog Video Switch .............................................................. 3-18
LM1112A Dolby B-Type Noise Reduction Processor ......................................... 1-120
LM1131A Dual Dolby B-Type Noise Reduction Processor. .................................... 1-126
LM1141 Dolby B-C Type Noise Reduction Processor ......................................... 1-131
LM1201 Video Amplifier System ............................................................ 3-22
LM1203 RGB Video Amplifier System ....................................................... 3-23
LM1211 Broadband Demodulator System ................................................... 5-82
LM1391 Phase-Locked Loop ............................................................... 3-34
LM 1458 Dual Operational Amplifier ...................................................... Linear 1
LM1496 Balanced Modulator Demodulator ................................................... 5-92
LM1558 Dual Operational Amplifier ...................................................... Linear 1
LM 1578 Switching Regulator ............................................................ Linear 1
LM1596 Balanced Modulator Demodulator ................................................... 5-92
LM1800 Phase-Locked Loop FM Stereo Demodulator .......................................... 2-8
LM 180 1 Battery Operated Power Comparator ................................................ 5-97
LM1812 Ultrasonic Transceiver ........................................................... 5-105
LM 1815 Adaptive Sense Amplifier ......................................................... 5-113
LM1818 Electronically Switched Audio Tape System ......................................... 1-136
LM1819 Air-Core Meter Driver ............................................................ 5-117
LM1823 Video IF Amplifier/PLL Detection System ............................................ 3-39
LM1830 Fluid Detector ................................................................... 5-125
LM1837 Low Noise Preamplifier for Autoreversing Tape Playback Systems ..................... 1-149
LM1851 Ground Fault Interrupter .......................................................... 5-131
LM 1863 AM Radio System for Electronically Tuned Radio ..................................... 2-11
LM1865 Advanced FM IF System ........................................................... 2-23
LM1866 Low Voltage AM/FM Receiver ...................................................... 2-37
LM 1868 AM/FM Radio System .................................................•........... 2-44
LM 1870 Stereo Demodulator with Blend ..................................................... 2-52
LM1871 RC Encoder/Transmitter .......................................................... 2-58
LM1872 Radio Control Receiver/Decoder ................................................... 2-74
LM1875 20-Watt Power Audio Amplifier .................................................... 1-161
LM 1877 Dual Power Audio Amplifier ....................................................... 1-167
LM1880 No-Holds Vertical/Horizontal ....................................................... 3-46
LM1881 Video Sync Separator ............................................................. 3-54
LM1884 TV Stereo Decoder ............................................................... 2-93
LM1886 TV Video Matrix D to A ............................................................ 3-61
LM1889 TV Video Modulator ............................................................... 3-68
LM1893 Biline Carrier Current Transceiver .................................................. 5-138
LM1894 Dynamic Noise Reduction System DNR ............................................ 1-172

9

Alpha-Numeric Index (Continued)
LM1895 Audio Power Amplifier ............................................................ 1-180
LM1896 Dual Power Audio Amplifier ....................................................... 1-186
LM1897 Low Noise Preamplifier for Tape Playback Systems .......•.......................... 1-194
LM19211 Amp Industrial Switch ........................................................... 5-160
LM1946 Over/Under Current Limit Diagnostic Circuits ........................................ 5-165
LM1949 Injector Drive Controller .......................................................... 5-176
LM1951 Solid State 1 Amp Switch ......................................................... 5-184
LM1964 Sensor Interface Amplifier ........................................................ 5-192
LM1965 Advanced FM IF System .........................................................•. 2-23
LM2002 8-Watt Audio Power Amplifier ..................................................... 1-202
LM2005 20-Watt Automotive Power Amplifier ............................................... 1-206
LM2065 Advanced FM IF System ........................................................... 2-23
LM2578 Switching Regulator ............................................................ Linear 1
LM2877 Dual 4-Watt Power Audio Amplifier ................................................. 1-213
LM2878 Dual 5-Watt Power Audio Amplifier ................................................. 1-220
LM2879 Dual 8-Watt Audio Amplifier ....................................................... 1-227
LM2889 TV Video Modulator ............................................................... 3-78
LM2893 Biline Carrier Current Transceiver .................................................. 5-138
LM2900 Quad Amplifiers ................................................................ Linear 1
LM2901 Low Power Low Offset Voltage Quad Comparators ................................. Linear 1
LM2902 Low Power Quad Operational Amplifiers .......................................... Linear 1
LM2903 Low Power Low Offset Voltage Dual Comparator ................................... Linear 1
LM2904 Low Power Dual Operational Amplifiers ........................................... Linear 1
LM2905 Precision Timer .................................................................... 5-7
LM2907 Frequency to Voltage Converter ................................................... 5-196
LM2917 Frequency to Voltage Converter ................................................... 5-196
LM2924 Low Power Operational AmplifierlVoltage Comparator .............................. Linear 1
LM2925 Low Drop-Out Regulator with Delayed Reset ...................................... Linear 1
LM2930 3-Terminal Positive Regulator .................................................... Linear 1
LM2931 Series Low Drop-Out Regulator .................................................. Linear 1
LM2935 Low Drop-Out Dual Regulator ...................................................• Linear 1
LM2940C 1A Low Drop-Out Regulator .................................................... Linear 1
LM2984C Microprocessor Power Supply System ........................................... Linear 1
LM3045 Transistor Arrays ................................................................ 5-210
LM3046 Transistor Arrays ................................................................ 5-210
LM3080 Operational Transconductance Amplifier .......... '.' .............................. Linear 1
LM3080A Operational Transconductance Amplifier ......................................... Linear 1
LM3086 Transistor Arrays ................................................................ 5-210
LM3089 FM Receiver IF System ............................................................ 2-96
LM3146 High Voltage Transistor Array ..................................................... 5-215
LM3189 FM IF System .......................................... , ........................ 2-102
LM3301 Quad Amplifiers ..............•................................................. Linear 1
LM3302 Low Power Low Offset Voltage Quad Comparators ................................. Linear 1
LM3361 A Low Voltage/Power Narrow Band FM IF System ................................... 2-109
LM3401 Quad Amplifiers ................................................................ Linear 1
LM3578 Switching Regulator ....................................•....................... Linear 1
LM3820 AM Radio System ............................................................... 2-114
LM3900 Quad Amplifiers ..........................•..................................... Linear 1
LM3905 Precision Timer .................................................................... 5-7
LM3909 LED Flasher/Oscillator ........................................................... 5-220
LM3911 Temperature Controller ......................................................... Linear 2

10

Alpha-Numeric

Index(continUed)

LM3914 Dot/Bar Display Driver ........................................................... 5-227
LM3915 Dot/Bar Display Driver ........................................................... 5-242
LM3916 Dot/Bar Display Driver ..........................•................................ 5-260
LM3999 Precision Reference ............................................................ Linear 2
LM4250 Programmable Operational Amplifiers ............................................. Linear 1
LM4500A High Fidelity FM Stereo Demodulator with Blend ................................... 2-118
LM6113 High Speed Operational Amplifiers Plus Power Buffer ............................... Linear 1
LM6121 High Speed Buffer ............................................................. Linear 1
LM6125 High Speed Buffer ............................................................. Linear 1
LM6161 High Speed Operational Amplifiers ............................................... Linear 1
LM6161 ILM6261 ILM6361 High Speed Operational Amplifiers ............................... Linear 1
LM6164 High Speed Operational Amplifiers ............................................... Linear 1
LM6164/LM6264/LM6364 High Speed Operational Amplifiers ............................... Linear 1
LM6165 High Speed Operational Amplifiers ............................................... Linear 1
LM6165/LM6265/LM6365 High Speed Operational Amplifiers ............................... Linear 1
LM6214 High Speed Operational Amplifiers Plus Power Buffer ............................... Linear 1
LM6221 High Speed Buffer ............................................................. Linear 1
LM6225 High Speed Buffer ............................................................. Linear 1
LM6261 High Speed Operational Amplifiers ............................................... Linear 1
LM6264 High Speed Operational Amplifiers ............................................... Linear 1
LM6265 High Speed Operational Amplifiers ............................................... Linear 1
LM6314 High Speed Operational Amplifiers Plus Power Buffer ............................... Linear 1
LM6321 High Speed Buffer ............................................................. Linear 1
LM6325 High Speed Buffer ............................................................. Linear 1
LM6361 High Speed Operational Amplifiers ............................................... Linear 1
LM6364 High Speed Operational Amplifiers ............................................... Linear 1
LM6365 High Speed Operational Amplifiers ............................................... Linear 1
LM 13080 Programmable Power Operational Amplifiers ..................................... Linear 1
LM13600 Dual Operational Transconductance Amplifiers with Linearizing Diodes and Buffers .... Linear 1
LM13700 Dual Operational Transconductance Amplifier with Linearizing Diodes and Buffers ..... Linear 1
LM 18272 Dual Power Operational Amplifier ............................................... Linear 1
LM18293 Four Channel Push Pull Driver ..................................................... 4-17
LM18298 Dual Full-Bridge Driver ........................................................... 4-23
LMC555 CMOS Timer .................................................................... 5-280
LMC567 Low Power Tone Decoder ........................................................ 5-283
LMC568 Low Power Phase-Locked Loop ................................................... 5-287
LMC660 CMOS Quad Operational Amplifier ............................................... Linear 1
LMC668 Chopper Stabilized Operational Amplifier .......................................... Linear 1
LMC669 Auto Zero ..................................................................... Linear 1
LMC835 Digital Controlled Graphic Equalizer ................................................ 1-234
LMC1992 Computer Controlled Tone and Volume Circuits .................................... 1-249
LMC1993 Computer Controlled Tone and Volume Circuits .................................... 1-249
LMC7660 Switched Capacitor Voltage Converter ........................................... Linear 1
LMC7669 Switched Capacitor Voltage Converter ........................................... Linear 1
LMF60 6th Order LMCMOSTM Switched Capacitor Butterworth Lowpass Filter ................. Linear 2
LMF90 4th-Order LMCMOSTM Programmable Elliptic Notch Filter ............................ Linear 2
LMF100 Universal Monolithic Dual Switched Capacitor Filter ................................ Linear 2
LMF120 Mask Programmable Switched Capacitor Filter ..................................... Linear 2
LP124 Micropower Quad Operational Amplifier ............................................ Linear 1
LP165 Micropower Programmable Quad Comparator ....................................... Linear 1
LP311 Voltage Comparator ............................................................. Linear 1

11

Alpha-Numeric Index (Continued)
LP324 Micropower Quad Operational Amplifier .................................•.......... Linear 1
LP339 Ultra-Low Power Quad Comparator ................................................ Linear 1
LP365 Micropower Programmable Quad Comparator ....................................... Linear 1
LP2902 Micropower Quad Operational Amplifier ........................................... Linear 1
LP2950 5V Adjustable Micropower Voltage Regulator .....•...•............................ Linear 1
LP2951 Adjustable Micropower Voltage Regulator ........•...•............................ Linear 1
MF4 4th Order Switched Capacitor Butterworth Lowpass Filter ..................•............ Linear 2
MF5 Universal Monolithic Switched Capacitor Filter ........................................ Linear 2
MF6 6th Order Switched Capacitor Butterworth Lowpass Filter ..................•............ Linear 2
MFB 4th Order Switched Capacitor Bandpass Filter ........................................ Linear 2
MF10 Universal Monolithic Dual Switched Capacitor Filter ...•............................... Linear 2
MM54HC4016 Quad Analog Switch ...................................................... Linear 2
MM54HC4051 8-Channel Analog Multiplexer .............................................. Linear 2
MM54HC4052 Dual 4-Channel Analog Multiplexer ......................................... Linear 2
MM54HC4053 Triple 2-Channel Analog Multiplexer ........................................ Linear 2
MM54HC4066 Quad Analog Switch ...................................................... Linear 2
MM54HC4316 Quad Analog Switch with Level Translator ......................•............ Linear 2
MM74C905 12-Bit Successive Approximation Register ...................................... Linear 2
MM74HC4016 Quad Analog Switch ...................................................... Linear 2
MM74HC4051 8-Channel Analog Multiplexer .............................................. Linear 2
MM74HC4052 Dual4-Channel Analog Multiplexer ......................................... Linear 2
MM74HC4053 Triple 2-Channel Analog Multiplexer ..................•..................... Linear 2
MM74HC4066 Quad Analog Switch .........................................•............ Linear 2
MM74HC4316 Quad Analog Switch with Level Translator ................................... Linear 2
TBA 120S IF Amplifier and Detector .................•...................................... 2-125
TLOB1CP Wide Bandwidth JFET Input Operational Amplifier ....................•............ Linear 1
TL082CP Wide Bandwidth Dual JFET Input Operational Amplifier ............................ Linear 1

12

...0

(")

~NatiOnal
Semiconductor
Corporation

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CROSS REFERENCE BY PART NUMBER

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A complete interchangeability list of Linear IC's offered by most Integrated Circuit
Manufacturers are listed in this section and reference the nearest National Semiconductor Corp. direct replacement or recommended replacement with either an
improved or functional replacement. The following notations are appended to assist you in finding the best option.

Z

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...
CD

No reference note ...... "DIRECT REPLACEMENT"
Note (1) ............... "IMPROVED REPLACEMENT" Pinfor-Pin replacement with "SUPERIOR" Electrical Specifications.
Note (2) ............... "FUNCTIONAL
REPLACEMENT"
Similar device. Consult datasheet to
determine the suitability for specific
application.
Note (3) ............... "SIMILAR DEVICE" with superior
performance. Consult datasheet to
determine suitability of the replacement for specific application.

ANALOG
DEVICES
ADOP07
ADDAC-08
ADDAC-08
ADDAC-08
ADDAC80
ADDAC85
AD101A
AD201A
AD301A
AD506
AD509
AD521
AD521
AD524
AD537
AD562
AD563
AD565A
AD566A
AD567
AD573
AD573
AD581
AD581
AD582
AD583
AD588
AD589M
AD589U
AD590
AD590
AD590
AD590
AD611K
AD611J
AD614

NATIONAL
LM607
DAC0800
DAC0801
DAC0802
DAC1280+
DAC1280+
LM101A
LM201A
LM301A
LH0022
LHOO03
LM363
LH0036
LH0038
LM331
DAC1266
DAC1265
DAC1265
DAC1266
DAC1230
ADC1005
ADC1025
LM581
LH0070
LF398
LF198
LM369
LM385
LM185
LM135
LM34
LM134
LM35
LF411AC
LF411C
LH0086

(1)

(1)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
(3)

(2)
(2)
(2)
(1)
(2)
(3)
(2)
(1)
(1)
(2)
(3)
(2)
(3)
(1)
(1)
(2)

AD624
AD650
AD651
AD654
AD673
AD741
ADLH0032
ADLH0033
ADOO42
AD3542
AD5035
AD7502
AD7516
AD7523
AD7523
AD7523
AD7524
AD7524
AD7524
AD7533
AD7533
AD7533
AD7541A
AD7541A
AD7541
AD7541
AD7542
AD7542
AD7542
AD7545
AD7545
AD7545
AD7548
AD7548
AD7548
AD7552
AD7552
AD7571

LH0038
LM331
LM331
LM331
ADC0841
LM741
LH0032
LH0033
LH0042
LH0042
LH0042
LF13509
C040668
DAC0832
DAC0831
DAC0830
DAC0830
DAC0831
DAC0832
DAC1020
DAC1022
DAC1021
DAC1218
DAC1219
DAC1219
DAC1218
DAC1210
DAC1209
DAC1208
DAC1209
DAC1210
DAC1208
DAC1230
DAC1232
DAC1231
ADC1225
ADC1205
ADC1005

13

(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
(3)
(3)

(2)
(2)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)

(2)
(2)
(2)
(2)
(2)

AD7571
AD7575
AD7576
AD7578
AD7578
AD7820

ADC1025
ADC0820
ADC0820
ADC1225
ADC1205
ADC0820

APEX
PA01
PA01
PA07
PA10
PA10
PA11
PA51
PA73

NATIONAL
LM12
LH0101
LM12
LM12
LH0101
LM12
LM12
LM12

(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)

BURR-BROWN
SHC80
SHC85
HOS-100
INA102
SHC298A
3507
3533
3542
3550
3551
3553
3554
3571
3572
3573
3606A6
3606A6
3626
3629

NATIONAL
LF398
LF398
LH0033
LH0038
LF398A
LM6361
LH0033
LH0042
LM6361
LM6361
LH0063
LH0032
LM675
LH0021
LM675
LH0084
LH0086
LH0036
LH0038

(2)
(2)
(2)
(2)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)

...CII

.c

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-...
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C'CI

Q.

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CII
CJ
C
CII
CII
CII

-...
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III
III

...
0

0

CTS
CTSOOO2
CTSOOO4
CTSOO21
CTSOO24
CTSOO32
CTSOO33
CTSOO41
CTSOO42
CTS2101A
CTS2111

NATIONAL
LHOOO2
LHOOO4
LHOO21
LHOO24
LHOO32
LHOO33
LHOO41
LHOO42
LH2101A
LH2111

(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)

ELANTEC
ELHOOO2
ELHOO21
ELHOO32
ELHOO33
ELHOO41
ELH0101
EL2006C
EL2006
EHA2500
EHA2502
EHA2505
EHA2510
EHA2512
EHA2515
EHA2520
EHA2522
EHA2525
EHA2600
EHA2602
EHA2605
EHA2620
EHA2622
EHA2625

NATIONAL
LHOOO2
LHOO21
LHOO32
LHOO33
LHOO41
LH0101
LM6261
LM6161
LM6161
LM6161
LM6361
LM6161
LM6161
LM6361
LM6164
LM6164
LM6364
LM6161
LM6161
LM6361
LM6164
LM6164
LM6364

(1)
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)

EXAR
XR084M
XR084
XR146
XR246
XR346
XR-1001
XR-1002
XR1458

NATIONAL
LF147
LF347
LM146
LM246
LM346
MF4C-100
MF4C-50
LM1458

(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)

FAIRCHILD
/LA78XXKM
/L78LXXACH
/L78XXUC
/L78XXUC
/LA78LXXACLP
/LA78 LXXAWC
/L78MXXCKC
/L78MXXCKC
/LA78MXXUC
/LA78MXXCKC
/LA78XXKC
/LA79XXUC
/LA79XXUC
/LA79XXCKC
/LA79XXCKC
/LA79XXUC
/LA79XXUC
/LA79XXCKC
/LA79XXCKC
/LA79MXXAUC
/LA79XXKM

NATIONAL
LM140K-XX
LM78LXXACH
LM340T-XX
LM78XXCT
LM78LXXACZ
LM78LXXACZ
LM78XXCK
LM78MXXCT
LM341P-XX
LM78XXCT
LM340K-XX
LM79LXXACZ
LM79MXXCP
LM79XXCT
LM79MXXCP
LM79MXXCH
LM320T-XX
LM79MXXCH
LM79LXXACZ
LM320MP-XX
LM120K-XX

(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)

/LA79XXKC
/LA79XXUC
/LA101A
/LA102
/LA105HM
/LA107
/LA108A
/LA108
/LA109KM
/LA110
/L A111
/L A124
/LA139
/LA139A
/LA201A
/LA207
/LA208
/LA208A
/L A211
/L A224
/LA239
/LA239A
/LA248
/LA249
/LA301A
/LA302
/LA304HC
/LA305HC
/LA305AHC
/LA307
/LA308A
/LA308
/LA309KC
/LA31 0
/LA311
/LA317KC
/LA317UC
/LA318
/LA324
/LA339
/LA339A
/LA348
/LA349
/LA376TC
/LA555TC
/LA556PC
/LA709
/LA709
/LA71 0
/LA71 0
/L A711
/L A714
/LA723HM
/LA723HC
/LA723DC
/LA723MJ
/LA723CJ
/LA723DM
/LA723PC
/LA723CN
/LA725
/LA725
/LA733CN
/LA733
,."A741
/L A741
/L A747
/L A747
/LA748

LM320K-XX
LM79XXCT
LM101A
LM102
LM105H
LM107
LM108A
LM108
LM1 09K STEEL
LM110
LM111
LM124
LM139
LM139A
LM201A
LM207
LM208
LM208A
LM211
LM224
LM239
LM239A
LM248
LM249
LM301A
LM302
LM304H
LM305H
LM305AH
LM307
LM308A
LM308
LM309K STEEL
LM310
LM311
LM317K STEEL
LM317T
LM318
LM324
LM339
LM339A
LM348
LM349
LM376N
LM555CN
LM556CN
LM709
LM709
LM710
LM710
LM711
LM607
LM723H
LM723CH
LM723CJ
LM723J
LM723CJ
LM723J
LM723CN
LM723CN
LM725
LM725
LM733CN
LM733
LM741
LM741
LM747
LM747
LM748

14

(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)

(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)

/LA748
/LA760
/L A771B
/L A771
/LA771 A
/L A772B
/L A772
/L A772A
/L A774
/L A774B
/LA776
/LA1458
/LC1496P
/LC1496G
/LA1558
/LC1596G
TDA2310
/LA2901
/LA2902
TCA3089
/LA3301
/LA3302
/LC4558CD
/LA7392

LM748
LM760
LF411
LF351
LF411
LF412A
LF353
LF412A
LF347
LF347B
LM4250
LM1458
LM1496N
LM1496H
LM1558
LM1596H
LM381
LM2901
LM2902
LM3089N
LM3301
LM3302
LM833CN
LM1014

HARRIS
HA-OP07
HF-10
HI-201
HI-300
LM741
HA2400
HA2404
HA2405
HA2406
HA2500
HA2502
HA2505
HA2510
HA2512
HA2515
HA2520
HA2520
HA2522
HA2522
HA2525
HA2525
HA2530
HA2535
HA2540
HA2541-5
HA2541-2
HA2542
HA2542-2
HA2542-5
HA2600
HA2602
HA2605
HA2620
HA2622
HA2625
HA2640
HA5033
HA5162
A5180

NATIONAL
LM607
MF10
LF13201
AH5020
LM741
LM604AM
LM604AM
LM604C
LM604C
LM6161
LM6161
LM6361
LM6161
LM6161
LM6361
LM6164
LHOOO3
LHOOO3
LM6164
LHOOO3
LM6364
LHOO24
LHOO24
LHOO32
LM6361
LM6161
LHOO32
LM6164
LM6164
LM6161
LM6161
LM6361
LM6164
LM6164
LM6364
LHOOO4
LHOO33
LHOO62
LHOO52

(2)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(2)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(2)
(1)

HEWLETT
PACKARD
HCTL-100

NATIONAL
LM628

(3)

(1)

..
..-

(")

HITACHI
HA13421A
HA17082
HA17082A
HA17084
HA17084A
HA17094
HA17301
HA17324
HA17339
HA17358
HA17393
HA17458
HA17741
HA17747
HA17901
HA17902
HA17903

NATIONAL
LM18293
LF353
LF412
LF347
LF3478
LM2904
LM3301
LM324
LM339
LM358
LM393
LM1458
LM741
LM747
LM2901
LM2902
LM2903

(3)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)

LINEAR
TECHNOLOGY
REF-01
REF-01
LM129
LM134
LM185
LM199
LM234
LM329
LM334
LM385
LM399
AD581
AD581
LT1001
LT1004C
LT1004M
LT1009M
LT1009C
LT1019C
LT1019M
LT1020
LT1021M
LT1021C
LT1029M
LT1029C
LT1031

NATIONAL
LM168
LM368
LM129
LM134
LM185
LM199
LM234
LM329
LM334
LM385
LM399
LM581
LHOO70
LM607A
LM385
LM185
LM136-2.5
LM336-2.5
LM368
LM168
LP2951
LM169
LM369
LM136-5.0
LM336-5.0
LHOO70

LSI
COMPUTER
LS7261
LS7263

NATIONAL
LM621
LM621

(3)
(3)

MICRA
MCOOO2
MCOOO3
MCOOO4
MCOO32
MCOO33
MCOO41
MCOO63

NATIONAL
LHOOO2
LHOOO3
LHOOO4
LHOO32
LHOO33
LHOO41
LHOO63

(1)
(1)
(1)
(1)
(1)
(1)
(1)

MICRO POWER
SYSTEMS
MPOP07
MP108
MP108A
MP155A
MP155
MP156

NATIONAL
LM607
LM108
LM108A
LF155A
LF155
LF156

(1)
(1)

(1)

(2)
(2)
(3)
(1)
(1)

(1)
(1)
(1)
(1)
(1)
(1)

MP156A
MP157
MP157A
MP208A
MP208
MP308
MP308A
MP355A
MP356A
MP357A
MP2108A
MP5010H
MP5010L
MP5010G
MP5010H
MP5010L
MP5010G

LF156A
LF157
LF157A
LM208A
LM208
LM308
LM308A
LF355A
LF356A
LF357A
LH2108A
LM385
LM385
LM185
LM185
LM185
LM385

MOTOROLA
DAC-08
DAC-08
DAC-08

NATIONAL
DAC0800
DAC0802
DAC0801
LM340AT-XX
LM78XXCK
LM78LXXACZ
LM78XXCK
LM341P-XX
LM78LXXCH
LM78LXXCH
LM78MXXCT
LM78XXCT
LM78LXXACZ
LM342P-XX
LM78LXXACH
LM320K-XX
LM320MP-XX
LM79XXCK
LM320T-XX
LM79XXCT
LM79MXXCH
LM320LZ-XX
LM320H-XX
LM320LZ-XX
LM79MXXCP
LM79LXXACZ
LM79LXXCZ
LM320T-XX
LM79XXCT
LM79LXXACZ
LM79LXXACZ
LM79MXXCH
LM79MXXCP
LM109K STEEL
LM109H
LM117K STEEL
LM123K STEEL
LM137H
LM137KSTEEL
LM140K-XX
LM150KSTEEL
LM285
LM309H
LM309K
LM309K STEEL
LM317H
LM317LZ
LM317T
LM317T
LM317KSTEEL
LM323K STEEL

MC78~XACT

MC78XXCK
MC78LXXACP
MC78MXXCT
MC78MXXCT
MC78LXXACG
LM78XXCT
MC78MXXCT
MC78XXCT
MC78LXXCP
MX78MXXCT
MC78LXXCG
MC79XXCK
MC79MXXCKC
MC79XXCK
MC79XXCKC
LM79XXCP
MC79XXCT
MC79LXXCP
MC79LXXACG
MC79LXXCLP
MC79XXCT
MC79LXXACP
MC79LXXCP
MC79XXCT
MC79XXCT
MC79XXCT
LM79XXCP
LM79XXCP
LM79XXCP
LM109K
LM109H
LM117H
LM123K
LM137H
LM137K
LM140K
LM150K
LM285
LM309H
LM309H
LM309K
LM317H
LM317LZ
LM317T
LM317KC
LM317K
LM323K

15

(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)

(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)

LM330-XKC
LM337H
LM337K
LM337KC
LM337T
LM340T-XX
LM340T-XX
LM340-XXKC
LM350T
LM350K
LM350KC
LM350KA
LM385
AD562A
AD563A
p.PC741
MC1408
MC1408
MC1408
MC1414
MC1436
MC1458
MC1496
MC1508
MC1514
MC1536
MC1558
MC1596G
MC1709
MC1709
MC1710
MC1723CL
MC1723CG
MC1723CP
MC1723CL
MC1723L
MC1723G
MC1733CG
MC1741
MC1741
MC1747
MC1747
MC1748
LM2930-XKC
MC3301
MC3302
MC3361
MC3401
MC341 0
MC3412
MC3510
MC4741
MC14442
MC14444
MC34001A
MC340018
MC34001
MC340028
MC34002
MC34002A
MC340048
MC34004
MC340048
MC34004
MC35001
MC35001A
MC350018
MC350028
MC35002
MC35002A

LM330T-XX
LM337H
LM337K STEEL
LM337T
LM337T
LM340T-XX
LM340K-XX
LM340T-XX
LM350T
LM350K STEEL
LM350T
LM350K STEEL
LM385
DAC1266
DAC1265
LM741
DAC0806
DAC0808
DAC0807
LM1414
LM343
LM1458
LM1446
DAC0808
LM1514
LM143
LM1558
LM1596CH
LM709
LM709
LM710
LM723CJ
LM723CH
LM723CN
LM723CM
LM723J
LM723H
LM723CH
LM741
LM741
LM747
LM747
LM748
LM2930T-XX
LM3301
LM3302
LM3361AN
LM3401
DAC1020
DAC1265
DAC1020
LM348
ADC0829
ADC0830
LF411C
LF411C
LF351
LF412C
LF353
LF412A
LF3478
LF347
LF147
LF147
LF411M
LF411M
LF411M
LF412M
LF412M
LF412AM

(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(2)

0
0
0

::D

I'D
I'D
I'D
:J

n

I'D
C"

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-..
..
"tJ

I»

Z

c

3

C"
I'D

(1)
(1)
(1)

(1)
(1)
(1)
(1)
(1)

(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)

(1)
(1)
(1)
(1)
(1)
(2)
(1)
(2)
(1)
(2)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)

...CD

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Z

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Il.

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CD
U
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CD
CD
CD

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II:

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I/)

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0

0

MC145040
MC145041

PRECISION·
MONOLITHIC
INC.
REF-01J
REF-01
AMP-01
DAC-02
DAC-02
REF-02
DAC-02
DAC-03
DAC-03
BUF03
DAC-03
OP05
DAC-05
DAC-05
DAC-05
SW06B
SW06G
SW06F
OP07
DAC-08
DAC-08
MUX-08E
DAC-08
OP15
MUX-24E
REF-43

opn

OP100
DAC100
DAC100
DAC100
OP105/111
PM108A
PM108
PM139A
PM139
PM155
PM155A
PM156
PM156A
PM157
PM157A
SW201G
SW201B
SW201F
SW202B
SW202F
SW202G
PM208A
PM208
OP215
PM308A
PM308
DAC312
PM339A
PM355
PM355A
PM356A
PM356
PM357A
PM357
PM420
OPA501/3573
PM725

ADC0811
ADC0811

NATIONAL
LM368-10
LM369
LH0038
DAC1022
DAC1020
LM368-5.0
DAC1021
DAC1020
DAC1022
LH0033
DAC1021
LM607
DAC1020
DAC1021
DAC1022
LF11333
LF13333
LF13333
LM607
DAC0801
DAC0800
LF13508
DAC0802
LF411
LF13509
LM368-2.5
LM607
LH0052
DAC1021
DAC1020
DAC1022
LH0052
LM108A
LM108
LM139A
LM139
LF155
LF155A
LF156
LF156A
LF157
LF157A
LF13201
LF11201
LF13201
LF11202
LF13202
LF13202
LM208A
LM208
LF412
LM308A
LM308
DAC1266
LM339A
LF355
LF355A
LF356A
LF356
LF357A
LF357
LF124
LH0101
LM725

(2)

(1)
(1)
(2)
(2)
(2)
(3)
(2)
(2)
(2)
(1)
(2)
(2)
(2)
(2)
(2)

(1)

(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)

(1)
(1)
(1)
(1)
(1)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(1)

PM-725
PM741
PM-741
PM-747
PM747
DAC888
DAC888
DAC888
ADC910
ADC910
DAC0812
DAC0812
DAC0812
DAC1408
DAC1408
DAC1408
PM2108A
PM7533
PM7533
PM7533
PM7541
PM7541

LM725
LM741
LM741
LM747
LM747
DAC0831
DAC0832
DAC0830
ADC1005
ADC1025
DAC1208
DAC1209
DAC1210
DAC0806
DAC0808
DAC0807
LH2108A
DAC1021
DAC1020
DAC1022
DAC1219
DAC1218

RAYTHEON
REF-01
REF-On
REF-02
REF-03
LP365
RC714
RC741
RC741
RC747
RC747
RC1458
RC1558

NATIONAL
LM369
LM368
LM368-5.0
LM368-2.5
LP365
LM607
LM741
LM741
LM747
LM747
LM1458
LM1558

RCAI
INTERSIL/G.E.
CA081C
CA081A
CA081
CA081B
CA082C
CA082B
CA082
CA082A
CA084B
CA084
CA084C
CA124
CA139
CA139A
CA158
CA158A
DG201
DG211
DG212
CA224
CA239
CA239A
CA258
CA258A
CA301A
CA307
CA311
CA324
CA339A
CA339
CA358A

NATIONAL
TL081C
LF411C
LF411M
LF411C
TL082C
LF412C
LF412M
LF412C
LF347B
LF147
LF347
LM124
LM139
LM139A
LM158
LM158A
LF11201
LF13201
LF13202
LM224
LM239
LM239A
LM258
LM258A
LM301A
LM307
LM311
LM324
LM339A
LM339
LM358A

16

(1)

(1)
(2)
(2)
(2)
(2)
(2)
(2)

(2)
(2)
(2)
(1)

(1)
(1)
(3)
(1)
(1)
(1)

(1)
(1)
(1 )

(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
(1)

(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)

CA358
CA741
CA741
CA747
CA747
CA748
I-'A748
CA748
ADC0801
ADC0802
ADC0803
ADC0804
CA1458
CA1558
CA31 05
CA3290
CA3401
IH5009
IH5010
IH5011
IH5012
IH6108
IH6208
ICL7114
ICL7114
AD7520
AD7520
AD7520
AD7521
AD7521
AD7521
AD7530
AD7530
AD7530
AD7531
AD7531
AD7531
AD7533
AD7533
AD7533
AD7541
AD7541
ICL7650
ICL8069
ICL8069
ICH8530

LM358
LM741
LM741
LM747
LM747
LM748
LM748
LM748
ADC0801
ADC0802
ADC0803
ADC0804
LM1458
LM1558
LM675
LF393
LM3401
AH5009
AH5010
AH5011
AH5012
LF13508
LF13509
ADC1205
ADC1225
DAC1021
DAC1020
DAC1022
DAC1221
DAC1220
DAC1222
DAC1020
DAC1021
DAC1022
DAC1220
DAC1221
DAC1222
DAC1020
DAC1021
DAC1022
DAC1219
DAC1218
LMC668
LM385-1.2
LM313
LH0101

SAMSUNG
LM741

NATIONAL
LM741

SGS
L78M12CV
L78M15CV
L78S12CV
L78S05CV
L78S15CV
L78M05CV
LM117K
L123CB
L272
L293
L298
LM317T
LM317K
LM748
TDA2310
LM2930A
LM2931A
TCA3089
L7805CT

NATIONAL
LM341P-12
LM341P-15
LM340T-12
LM340T-5.0
LM340T-15
LM341P-5.0
LM117K
LM723CN
LM18272
LM18293
LM18298
LM317T
LM317K
LM748
LM381
LM2930T-5.0
LM2931AT-5.0
LM3089
LM7805CK

(1)
(1)
(1)
(1)

(1)
(1)
(2)
(2)
(1)

(2)
(2)

(3)
(3)
(3)

(1)

(2)

(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)

(1)
(1)

(1)
(1)
(1)

L7815CV
L7905ACV
L7905CT
L7905CV
L7912CT
L7912ACV
L7915CT
L7915ACV

LM7815CT
LM320T-5.0
LM7905CK
LM7905CT
LM7912CK
LM320T-12
LM7915CK
LM320T-15

(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)

SIEMENS
TCA365

NATIONAL
LH0101

(1)

SIGNETICS
DAC-08
DAC-OB
DAC-OB
78LXXACS
7BLXXADB
7BLXXCDB
7BLXXCS
7BXXCU
7BXXDA
79XXDA
79XXCU
LM109DB
TBA120S-4
TBA120S-3
TBA120S-2
LF198
LF29B
LM309DA
LM309DB
LM340XXLL
LM340XXDA
LF398
NE529
SE529
SE532
SA532
NE532
SA534
NE555N
SE567
JLA723CN
JLA723CL
JLA723L
JLA723CF
JLA723F
JLA741
JLA747
ADCOB01
ADCOB02
ADCOB03
ADCOB04
ADCOB05
MC140B
MC140B
MC140B
MC1496N
MC150B
MC1596K
NE455BD
NE455BN
NE4558
NE5034
SE511B
NE5118
NE5410
SE5410
NE5532P

NATIONAL
DACOB02
DACOB01
DACOBOO
LM7BXXACZ
LM7BXXACH
LM7BLXXCH
LM7BLXXCZ
LM7BXXCT
LM7BXXCK
LM79XXCK
LM79XXCT
LM109H
TBA120SIV
TBA120SII1
TBA120S11
LF19B
LF29B
LM309K
LM309H
LM340TXX
LM340KXX
LF39B
LM361
LM161
LM15B
LM2904
LM35B
LM2902
LM555CN
LM567
LM723CN
LM723CH
LM723H
LM723CJ
LM723J
LM741
LM747
ADCOB01
ADC0802
ADCOB03
ADC0804
ADC0805
DACOBOB
DACOB07
DACOB06
LM1496N
DACOB08
LM1596H
LM833CM
LM833CN
LMB33
ADCOB41
DACOB30
DACOB30
DAC1020
DAC1020
LM833CN

(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)

(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(1)
(1)
(1)
(1)
(1)

(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)

NE5532
NE5532N

LM833
LM833CN

SILICON
GENERAL
SG101
SG101A
SG107
SG124
SG201
SG201A
SG207
SG224
SG301A
SG307
SG324
SG741
SG741
SG1173
SG1436
SG1536
SG3173

NATIONAL
LM101A
LM101A
LM107
LM124
LM201A
LM201A
LM207
LM224
LM301A
LM307
LM324
LM741
LM741
LM675
LM343
LM143
LM675

SILICON IX
DG201
DG202
DG211
DG212
DG50B
DG509

NATIONAL
LF13201
LF13202
LF13201
LF13202
LF13508
LF13509

SPRAGUE
UDN22933

NATIONAL
LM1B293

TELEDYNE
TPOO32
TPOO33

NATIONAL
LHOO32
LHOO33

(1)
(1)

TEXAS
INSTRUMENTS
JLA78XXCKC
JLA78LXXACL
",A7BMXXCKD
JLA79MXXCKD
JLA79XXCKC
TL061A
TL0618
TL061
TL062A
TL0628
TL062
TL064A
TL064
TL071B
TL071A
TL071
TL072
TL072A
TL072B
TL074
TL074A
TLOB1B
TL081
TL081A
TL082B
TLOB2A
TLOB2
TLOB4A
TLOB4

NATIONAL
LM7BXXCT
LM7BLXXACZ
LM7BMXXCP
LM79MXXCP
LM79XXCT
LF441
LF441A
LF441
LF442
LF442
LF442
LF444
LF444
LF411
LF411
LF351
LF353
LF412
LF412
LF347
LF347B
LF411
TLOB1
LF411
LF412
LF412
TLOB2
LF347B
LF347

(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)

17

(2)

(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(1)
(1)
(2)

TL087
TL088
TLC274BI
TLC274BM
TLC274M
TLC274AC
TLC274BC
TLC274AM
TLC2741
TLC274C
TLC274AI
TL288
LM317KC
TL4B7N
TL489N
TL490N
TL491 N
TL520
TL521
TL522
TL530
TL531
TL532
TLC532A
TLC533A
TL533
TLC540
TLC541
TLC549
",A709
",A723CN
",A723CJ
",A723MJ
",A733CN
",A741
",A747
ADCOB01
ADCOB02
ADCOB03
ADC0804
ADCOB05
ADCOBOB
ADC0809
ADC0831
ADC0832
ADC0834
ADCOB3B
RC455B
RV455BD
RC455BD

LF411A
LF411A
LMC660AI
LMC660AM
LMC660AM
LMC660AI
LMC660AI
LMC660AM
LMC660AI
LMC660C
LMC660AI
LF412A
LM317T
LM3915N
LM3914N
LM3914N
LM3914N
ADCOB4B
ADCOB4B
ADCOB48
ADC0830B
ADC0830C
ADC0829B
ADCOB29B
ADCOB29C
ADC0829C
ADCOB11
ADCOB11
ADCOB31
LM709
LM723CN
LM723CJ
LM723J
LM733CN
LM741
LM747
ADCOB01
ADCOB02
ADCOB03
ADCOB04
ADCOB05
ADCOBOB
ADCOB09
ADCOB31
ADCOB32
ADCOB34
ADC083B
LMB33
LMB33CM
LM833CM

THOMSON
LM105H
LM109K
LM117K
LM117H
LM123K
LM134
LM135
LM137K
LM137H
LM138K
LF198
LM234
LM235
LF29B
LM305H
LM309H
LM309K

NATIONAL
LM105H
LM109KSTEEL
LM117KSTEEL
LM117H
LM123KSTEEL
LM134
LM135
LM137KSTEEL
LM137H
LM13BKSTEEL
LF198A
LM234
LM235
LF29B
LM305H
LM309H
LM309K STEEL

(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)

(2)
(2)
(2)
(2)
(1)
(1)
(1)

(1)
(1)
(1)
(1)
(1)

(1)
(1)
(1)
(1)

(1)
(1)
(1)

0
....
0

VI
VI

::c

CD
CD
CD
:J

....
~

CD

e-

'<

"'tI

-z
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....
c

3
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Q.

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..
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I/)

0

0

LM317K
LM317H
LM323K
LM334
LM335A
LM335
LM337H
LM337K
LM338K
LF398
p.A741
p.A748
TBC0136
p.A7805CK
p.A7805MK
p.A7812MK
p.A7812CK
p.A7815CK
p.A7815MK
p.A7905MK
p.A7905CK
p.A7912MK
p.A7912CK
p.A7915MK
p.A7915CK

LM317K STEEL
LM317H
LM323K STEEL
LM334
LM335A
LM335
LM337H
LM337K STEEL
LM338KSTEEL
LF398A
LM741
LM748
LM336
LM7805KC
LM140K-5.0
LM140K-12
LM7812KC
LM7815KC
LM140K-15
LM120K-5.0
LM7905KC
LM120K-12
LM7912KC
LM120K-15
LM7915KC

TOSHIBA
TA7504
TA75339
TA75358
TA75393
TA75902

NATIONAL
LM741
LM2901
LM2904
LM2903
LM2902

UNITRODE
L293
L298

NATIONAL
LM18293
LM18298

(1)
(1)
(1)

(1)
(1)
(1)
(1)

(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)

(1)
(1)
(1)
(1)

18

~

Industry Package Cross-Reference Guide

CJ
wmmr

~=

~
IIIn

@

CJ
~

NSC

Signetics

Fairchild

Motorola

4/16 Lead
Glass/Metal DIP

D

I

D

L

Glass/Metal
Flat Pack

F

Q

F

F

TO-99, TO-100, TO-5

H

T,
K,
L,
DB

H

8-, 14- and 16-Lead
Low Temperature
GeramicDIP

J

F

~

0

D

m

R,
D

TI

RCA

Hitachi

NEC

LTC

D

G

D

D

F,
S

K

F

G

L

S',
V1"

U

J

G

Q

A

H

D

J,
J8

(Steel)
K
TO-3

K

KS

KG

DA

K

K

K

N

V,
A,
B

T,
P

P

P,
N

(Aluminum)

8-, 14- and 16-Lead
Plastic DIP

'With dual-in-line formed leads

"·With radically formed leads

19

E

P

G

N,
N8

NSC

~~

~;

~

~
~~~

TO-202
(0-40, Ourawatt)

TO-220
3-&5-Lead
TO-220
11-,15- & 23-Lead

Signetlcs

Fairchild

Motorola

TI

Hitachi

NEC

LTC

T

H

T

H

Z

G

8

KO

P

T

RCA

U

KC

U

T

Low Temperature
Glass Hermetic
Flat Pack

W

TO-92
(Plastic)

Z

M

F

F

W

8

W

P

LP

0

8

0

0

0

uuutCJUiJ

AAAAAAAAAA
~

80

(Narrow Body)
(Wide Body)

WM

0
OW

•

I:IIHHHII:Hl 1::11::11::1

bttiJUUUUttUd

20

M

MP

NSC

Signetics

Fairchild

Motorola

TI

RCA

Hitachi

NEC

LTC

:;
a.

-

c

!II
~

'<

"'tI

II)

n

~

II)

cc
CD

PCC

V

A

Q

FN

FN

Q

CP

L

0

~

.

0

!II
!II
;:Q

CD
CD
~
CD

tooailJJW

~

n

CD
C)

c

a:
CD
LCC
Leadless Ceramic
Chip Carrier

E

G

L1

II~~~~~~~II

21

U

FKI
FG/FH

BJ

CG

K

Linear 1 Databook
Selection Guides

Voltage Regulators
Operational Amplifiers
Buffers
Voltage Comparators
Instrumentation Amplifiers

23

II)

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toc
CI)

~ Semiconductor
NatiOnal

Corporation

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Voltage Regulators
Definition of Terms
Current-Limit Sense Voltage: The voltage across the current limit terminals required to cause the regulator to current-limit with a short circuited output. This voltage is used
to determine the value of the external current-limit resistor
when external booster transistors are used.

Output-Input Voltage Differential: The voltage difference
between the unregulated input voltage and the regulated
output voltage for which the regulator will operate within
specifications.
Output Noise Voltage: The RMS ac voltage at the output
with constant load and no inut ripple, measured over a
specified frequency range.

Dropout Voltage: The input-output voltage differential at
which the circuit ceases to regulate against further reductions in input voltage.

Output Voltage Range: The range of regulated output voltages over which the specifications apply.

Feedback Sense Voltage: The voltage, referred to ground,
on the feedback terminal of the regulator while it is operating in regulation.

Output Voltage Scale Factor: The output voltage obtained
for a unit value of resistance between the adjustment terminal and ground.

Input Voltage Range: The range of dc input voltages over
which the regulator will operate within specifications.

Quiescent Current: That par of input current to the regulator that is not delivered to the load.

Line Regulation: The change in output voltage for a
change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected.

Ripply Rejection: The line regulation for ac inupt signals at
or above a given frequency with a specified value of bypass
capacitor on the reference bypass terminal.

Load Regulation: The change in output voltage for a
change in load current at constant chip temperature.

Standby Current Drain: That part of the operating current
of the regulator which does not contribute to the load current. (See Quiescent Current)

Long Term Stability: Output voltage stability under accelerated life-test conditions at 125'C with maximum rated voltages and power dissipation for 1000 hours.

Temperature Stability: The percentage change in output
voltage for a thermal variation from room temperature to
either temperature extreme.

Maximum Power Dissipation: The maximum total device
dissipation for which the regulator will operate within specifications.

Thermal Regulation: Percentage change in output voltage
for a given change in power dissipation over a specified time
period.

24

~NatiOnal

Semiconductor
Corporation

Voltage Regulators Selection Guide
Adjustable Positive Voltage Regulators
Amps

Device

Output
Voltage

Package

10.0

LM196K
LM396K

1.25V-15V
1.25V-15V

TO-3
TO-3

5.0

LM138K
LM338K

1.2V-32V
1.2V-32V

TO-3
TO-3

3.0

LM150K
LM350K, T

1.2V-33V
1.2V-33V

TO-3
TO-3, TO-220

1.5

LM117K
LM117HVK
LM2941CT
LM317K, T
LM317HVK

1.2V-37V
1.2V-57V
5.0V-24V
1.2V-37V
1.2V-57V

TO-3
TO-3
TO-220
TO-3, TO-220
TO-3

0.5

LM117H
LM117HVH
LM317H
LM317HVH
LM317MP

1.2V-37V
1.2V-57V
1.2V-57V
1.2V-37V
1.2V-37V

TO-39
TO-39
TO-39
TO-39
TO-202

0.1

LM317LZ, M
LM2931CT
LP2951CN, J, H, M

1.2V-37V
3.0V-24V
1.24V-29V

TO-92,SO-8
TO-220, 5-LEAD
DIP, CERDIP, HEADER, SO-8

Page

Adjustable Negative Voltage Regulators
Amps

Device

Output Voltage

Package

3.0

LM133K
LM333K, T

-1.2V - -32V
-1.2V - -32V

TO-3
TO-3, TO-220

1.5

LM137K
LM137HVK
LM337K, T
LM337HVK

-1.2V -1.2V -1.2V -1.2V -

-37V
-47V
-37V
-47V

TO-3
TO-3
TO-3, TO-220
TO-3

0.5

LM137H
LM137HVH
LM337H
LM337HVH
LM337MP

-1.2V -1.2V-1.2V -1.2V -1.2V -

-37V
-47V
-37V
-47V
-37V

TO-39
TO-39
TO-39
TO-39
TO-202

0.1

LM337LZ, M

-1.2V - -37V

25

TO-92,SO-8

Page

Q)

"C

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Fixed Positive Voltage Regulators

c

Amps

:;::;

3.0

LM123K
LM2943CT*
LM323K

1.0

o

Output Voltage

Package

5V
5V
5V

TO·3
TO·220
TO·3

LM109K
LM140AK
LM140K
LM2940CT
LM309K
LM340AK, T
LM340K, T
LM78xxCK, T

5V
5V, 12V, 15V
5V, 12V, 15V
5V,12V,15V
5V
5V, 12V, 15V
5V, 12V, 15V
5V, 12V, 15V

TO·3
TO·3
TO·3
TO·220
TO·3
TO·3, TO·220
TO·3, TO·220
TO·3, TO·220

0.5

LM2984CT
LM341T, P
LM78MxxCT

5V,12V,15V
5V, 12V, 15V
5V, 12V, 15V

TO·220, TO·202
TO·220, TO·202
TO·220

0.2

LM109H
LM309H
LM342P

5V
5V
5V, 12V, 15V

TO·39
TO·39
TO·202

5V,8V

TO·220

5V, 12V, 15V
5V
5V, 12V, 15V
5V, 12V, 15V
5V

TO·39
TO·92, TO·220
TO·92, TO·39
TO·92, TO·39, 80·8
TO·92

(.)

Q)

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Device

0.15

LM2930T

0.1

LM140LAH
LM2931Z, T
LM340LZ, H
LM78LxxACZ, H, M
LP2950CZ

Page

*Future Product

Fixed Negative Voltage Regulators
Amps

Device

Output Voltage

Package

-5V, -5.2V
-5V, -5.2V

TO·3
TO·3

LM120K
LM320K, T
LM79xxCT, K

-5V, -12V, -15V
-5V, -12V, -15V
-5V, -12V, -15V

TO·3
TO·3, TO·220
TO·3, TO·220

0.5

LM320MP
LM79MxxCP, K

-5V, -12V, -15V
-5V, -12V, -15V

TO·220
TO·202, TO·3

0.2

LM120H
LM320H

-5V, -12V, -15V
-5V, -12V, -15V

TO·39
TO·39

0.1

LM320LZ
LM79LxxACZ, M

-5V, -12V, -15V
-5V, -12V, -15V

TO·92
TO·92,80·8

3.0

LM145K
LM345K

1.5

'The LM320 has better electrical characteristics than the LM79xx.
LM100 Series
LM300 Series

+ 55'C to + 150'C
O'C to + 125'C

26

Page

o<

Low Dropout Regulators

::+

Amps

Device

Output Voltage

Package

0.100

LM2931T,Z
LP2950CZ
LP2951N,J,H

5V,ADJ
5V
ADJ

TO-220, TO-92
TO-92
DIP, CERDIP, HEADER

5V,BV

TO-220

0.150

LM2930T

0.500

LM29B4CT

TRIPLE 5V

+ WATCHDOG

TO-220, 11-LEAD

0.750

LM2925T
lM2935T

5V WITH DELAYED RESET
DUAl5V

TO-220, 5-LEAD
TO-220, 5-lEAD

lM2940CT
lM2941CT*

5V, 12V, 15V
ADJ

TO-220
TO-220,5-LEAD

lM2943CT*

5V

TO-220

1.5
3.0
-Future Product

27

Page

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Operational Amplifiers
Definition of Terms

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Q.

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Bandwidth: That frequency at which the voltage gain is reduced to 1/,f2 times the low frequency value.

"is
c

Common·Mode Rejection Ratio: The ratio of the input
common-mode voltage range to the peak-to-peak change in
input offset voltage over this range.

c(

o

~
CI.
o
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Large-Signal Voltage Gain: The ratio of the output voltage
swing to the change in input voltage required to drive the
output from zero to this voltage.
Output Impedance: The ratio of output voltage to output
current under the stated conditions for source resistance
(Rs) and load resistance (Rt,}.
Output Resistance: The small signal resistance seen at the
output with the output voltage near zero.
Output Voltage Swing: The peak output voltage swing, reo
ferred to zero, that can be obtained without clipping.

Harmonic Distortion: That percentage of harmonic distortion being defined as one-hundred times the ratio of the
root-mean-square (rms) sum of the harmonics to the fundamental. % harmonic distortion =
(V22

+ V32 + V42 + ...)1/2 (100%)

Offset Voltage Temperature Drift: The average drift rate
of offset voltage for a thermal variation from room tempera·
ture to the indicated temperature extreme.
Power Supply Rejection: The ratio of the change in input
offset voltage to the change in power supply voltages pro·
ducing it.
Settling Time: The time between the initiation of the input
step function and the time when the output voltage has set·
tied to within a specified error band of the final output voltage.
Slew Rate: The internally-limited rate of change in output
voltage with a large-amplitude step function applied to the
input.
Supply Current: The current required from the power supply to operate the amplifier with no load and the output midway between the supplies.

V1
where V1 is the rms amplitude of the fundamental and V2,
V3, V4, ... are the rms amplitudes of the individual harmonics.
Input Bias Current: The average of the two input currents.
Input Common-Mode Voltage Range: The range of voltages on the input terminals for which the amplifier is operational. Note that the specifications are not guaranteed over
the full common-mode voltage range unless specifically
stated.
Input Impedance: The ratio of input voltage to input current
under the stated conditions for source resistance (Rs) and
load resistance (Rt,}.
Input Offset Current: The difference in the currents into
the two input terminals when the output is at zero.

Transient Response: The closed-loop step-function response of the amplifier under small-signal conditions.
Unity Gain Bandwidth: The frequency range from dc to the
frequency where the amplifier open loop gain rolls off to
one.
Voltage Gain: The ratio of output voltage to input voltage
under the stated conditions for source resistance (Rs) and
load resistance (Rt,}.

Input Offset Voltage: That voltage which must be applied
between the input terminals through two equal resistances
to obtain zero output voltage.
Input Resistance: The ratio of the change in input voltage
to the change in input current on either input with the other
grounded.
Input Voltage Range: The range of voltages on the input
terminals for which the amplifier operates within specifications.

28

~NatiOnal

Semiconductor
Corporation

General Purpose Operational
Amplifier Selection Guide

Part #

Vos
mV(Max)

Ie
nA(Max)

GBW
MHz (Typ)

Slew
Rate
VII's (Typ)

Military Temperature Range (- 55'C to
LH0044A

0.025

15

0.4

LM607A

0.025

2

LH0044

0.05

30

LM607B

0.05

3

1.B

LM11

0.3

0.05

LF411A

0.5

0.2

Supply
Current
(Note 3)
mA(Max)

Su·pply
Voltage
Min
V

+ 125'C) Specs at T A =

Max
V

25'C (Note 1)
±3

±20

0.06

3

1.B

0.7

1.5

0.4

0.06

4

0.7

1.5

0.3

0.6

15

2.B

±6

±22

·
4

Special
Features

·

±3

··

±22
±20
±22
±20

LF441 A

0.5

0.05

1

1

0.2

±6

±22

LH0052

0.5

0.003

1

3

3.5

±5

±22

LM10BA

0.5

2

1

0.3

0.4

±2

±20

LF412A

1

0.2

4

15

5.6

±6

±22

Dual BiFet

LF442A

1

0.05

1

1

±6

±22

Dual BiFet

1

100

0.15

±5

±45

LM604A

1

40

7

·

0.4

LHOO04

2

B

4

36

LF155A

2

0.05

2.5

5

4

±5

±22

LF156A

2

0.05

5

12

7

±5

±22

LF157A

2

0.05

25

50

7

±5

±22

LF411

2

0.2

4

15

3.4

±6

±1B

1.5

1.7

2.2

5

15

LMC660A

2

0.02

LM10

2

20

LM101A

2

75

LM107

2

75

LM10B

2

LM112
LM124A

·

1

·

0.4

0.5

3

±3

±22

1

0.5

3

±3

±22

2

1

0.3

0.4

±2

±20

2

2

1

0.2

0.6

±2

±20

2

50

3

3

32

LM15BA

2

50

LP124

2

4

LH0020

2.5

250

3

0.2

LF412

·

·
·

·
·

(Note 4)

Multiplexed OA

Minimum Gain of 5

Quad CMOS
OA

+ Reference

Compensated LM10B
Quad

1.2

3

32

Dual

0.1

0.05

0.13

3

32

Quad

5

±5

±22

4

15

6.B

±6

±22

·

·

LM741A

3

BO

1.5

0.7

2.B

±3

±22

LH0022

4

0.01

1

3

3.5

±5

±22

LF155

5

0.1

2.5

5

4

±5

±22

29

Dual

General Purpose Operational Amplifier Selection Guide (Continued)
Part -#

18
nA{Max)

Vos
mV{Max)

GBW
MHz (Typ)

Slew
Rate
V/p.s (Typ)

Military Temperature Range (- 55°C to

Supply
Current
(Note 3)
mA{Max)

Supply
Voltage
Min
V

+ 125°C) Specs at TA =

Special
Features

Max
V
25°C (continued)

LF156

5

0.1

5

12

7

±5

±22

LF157

5

0.1

20

50

7

±5

±22

Minimum Gain of 5

LF147

5

0.2

4

13

11

±6

±22

Quad BiFet

LF412

5

0.2

4

15

6.8

±6

±18

Dual BiFet

LF442

5

0.1

1

1

0.5

±6

±18

Dual BiFet

LF444A

5

0.1

1

1

0.80

±6

±22

Quad BiFet

3

10

15.5

±8

±18

Programmable Gain OA

3

3

32

4

±4

±40

LHOO86

5

0.5

LM124

5

150

LM143

5

20

1

LM144

5

20

1

2.5

4

±4

±40

LM146

5

100

1.2

0.4

2

±1.5

±22

(Note 5)

LM148

5

100

1

0.5

3.6

±5

±22

Quad

LM149

5

100

4

2

3.6

±5

±22

Minimum Gain of 5, Quad

LM158

5

150

1.2

3

32

Dual

LM192

5

150

2

3

32

Comparator and Op Amp

LM741

5

500

2.8

±3

±22

LM1558

5

500

5

±3

±22

Dual

±18

(Note 5)

±22

·

·

2.5

·
·•
·

·
·

0.5

·

LM4250

5

50

0.2

0.2

0.1

±1

LHOO42

20

0.025

1

3

3.5

±5

18
nA{Max)

GBW

Part -#

Vos
mV{Max)

MHz (Typ)

Slew
Rate
V/p.s (Typ)

Supply
Current
(Note 3)
mA{Max)

Industrial Temperature Range (-25°C to

·

·

LMC669B

0.025

0.1

LH0044B

0.05

30

0.4

0.06

LHOO44C

0.05

30

0.4

0.06

LMC669C

0.05

0.1

·

·

Min
V

+ 85°C) (Note 1)
6

±8

±22

4

±3

±20

4

±3

±20

6

±8

±22
±20

0.5

2

1

0.3

0.6

LHOO52C

1

0.005

1

3

3.8

±5

±22

LMC660A

2

0.02

1.5

1.7

2.2

5

15

LM10B(L)

2

20

LM201A

2

75

LM207

2

LM208

2

LM212
LM224A

·

0.5

75

1

0.5

2

1

0.3

2

2

1

0.3

3

80

·

·
30

Special
Features

Max
V

LM208A

1

Minimum Gain of 10

Supply
Voltage

±2

·

Quad

0.4

(Note 4)
±3

±22

3

±3

±22

0.6

±2

±20

0.6

±2

±20

2

3

32

3

Autozero Block

Autozero Block

Quad CMOS
Op Amp and Reference

Compensated LM208
Quad

o

'"C
CD

General Purpose Operational Amplifier Selection Guide (Continued)
Part #

Ves
mV(Max)

18
nA(Max)

GBW
MHz (Typ)

Slew
Rate
V/""s(Typ)

Supply
Current
(Note 3)
mA(Max)

Industrial Temperature Range (- 25'C to

Min
V

1.2

3

32

0.1

2.5

5

4

±5

±22

5

0.1

5

12

7

±5

±22

LF257

5

0.1

20

50

7

±5

±22

LM224

5

150

LM25B

5

150

LM292

5

250

LH0020C

6

500

LH0022C

6

0.025

LM246

6

250

LM24B

6

200

LM249

6

LHOOB6C

10

BO

LF255

5

LF256

LH0042C

Part #

20

Ves
mV(Max)

·
··
·

·
·

·
·

n

Minimum Gain of 5

2

3

32

Quad

1.2

3

32

Dual

2

3

32

Comparator and Op Amp

C

±22
±22

0.5

0.4

2.5

±2

±1B

(Note 5)

1

0.5

4.5

±5

±1B

Quad

200

4

2

4.5

±5

±1B

Minimum Gain of 5, Quad

0.5

3

10

15.5

±B

±1B

Programmable Gain 1 to 200

±5

±22

18
nA(Max)

GBW
MHz (Typ)

4

Slew
Rate
V/""s(Typ)

Supply
Current
(Note 3)
mA(Max)

0.06

1

2.5

3.5

LMC66B

0.01

0.06

1

2.5

0.025

0.1

LM607A

0.025

2

LMC669C

0.05

0.1

.
.

3.5

LMC669B

·
·

0.7

Special
Features

Max
V

+ 70'C) (Notes 1 and 2)

0.005

1.B

Supply
Voltage
Min
V

6
1.5
6

±B

·
·
·

±B

1B
1B
±22

Commutating Autozero
Commutating Autozero
Autozero Block

±22
±22

Autozero Block

±22

LM607B

0.05

3

1.B

0.7

LM607

0.15

10

1.B

0.7

1.B

LF411A

0.5

0.2

4

15

2.B

±6

±22

LF441 A

0.5

0.05

1

1

0.2

±6

±22

LM30BA

0.5

7

1

O.B

±2

±20

LM11C

0.6

0.1

0.3

O.B

LF412A

1

0.2

·

0.3

4

15

5.6

±6

±22

Dual

LF442A

1

0.05

1

1

0.4

±6

±22

Dual

LM604A

1

40

5

3

9

4

36

LF355A

2

0.05

2.5

5

4

±5

±22

LF356A

2

0.05

5

12

10

±5

±22

LF357A

2

0.05

20

50

10

±5

±22

31

1.5

·
·

·

o·

:::I
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c:
CD

±5

3

iii"

±5

Commercial Temperature Range (O'C to
LMC66BA

~

4

1

»

en
CD

6

0.05

:::I

!!.

iii'

Dual

3

1

O·

3
"Eo
:::;:

+ 85'C) (continued)

·

3

Special
Features

Max
V

·

LM25BA

iiI

Supply
Voltage

±22

±20

Multiplexed Op Amp

Minimum Gain of 5

III

General Purpose Operational Amplifier Selection Guide (Continued)
GBW
MHz (Typ)

Slew
Rate
V/,..s(Typ)

Supply
Current
(Note 3)
mA(Max)

Supply
Voltage

Special
Features

Vos
mV(Max)

18
nA(Max)

LF411

2

0.2

4

15

3.4

±6

±22

LF412

3

0.2

4

15

6.8

±6

±22

Dual

LM324A

3

100

3

3

32

Quad

LM358A

3

100

2

3

32

Dual

LM604

3

60

7

9

4

36

Multiplexed Op Amp

LM741E

3

80

0.7

2.8

±3

±22

LM10C(L)

4

30

LP324

4

10

0.1

0.05

0.15

3

32

LF347B

5

0.2

4

13

11

±6

±22

LF355B

5

0.1

2.5

5

4

±5

±22

LF356B

5

0.1

5

12

4

±5

±22

LF357B

5

0.1

20

50

7

±5

±22

LF441

5

0.1

1

1

0.25

±6

±22

LF442

5

0.1

1

1

0.5

±6

5

0.2

0.3

0.8

LM392

5

250

LM833

5

1000

10

5

8

.
.

±22

LM11CL

LMC660

6

0.02

1.5

1.7

2.7

5

15

LM346

6

250

0.5

0.4

2.5

±1.5

±22

LM348

6

200

1

0.5

4.5

±5

±18

LM349

6

200

4

2

4.5

±5

±18

LM741C

6

500

1.5

0.5

2.8

±3

±18

LM1458

6

500

5.6

±3

±18

LM4250C

6

75

0.1

±1

±18

LM324

7

250

3

3

32

Part #

Commercial Temperature Range (O"C to

LM358

7

250

LM301A

7.5

250

LM307

7.5

LM308

7.5

·
·
5

1.5

·

·
·

·
··

0.2

·
·
·

·

·
·
·

0.2

Min
V

Max
V

+ 70"C) (continued)

0.5

2

(Note 4)

3

±18

3

32

±3

±18

0.5

3

±3

±18

0.3

0.8

±2

±18
±18

250

1

7

1

Dual

32

2

0.5

Quad

±20

3

1

OA and Reference

LM312

7.5

7

1

0.2

0.8

±2

LM343

8

40

1

2.5

5

±4

±34

Dual Low Noise
Quad CMOS
(Note 5)

(Note 5)

Compensated LM308

LM344

8

40

1

2.5

5

±4

±34

Minimum Gain of 10

LF347

10

0.2

4

13

11

±6

±18

Quad BiFet

LF351

10

0.2

4

13

3.4

±6

±18

LF353

10

0.2

4

13

6.8

±6

±18

LF355

10

0.2

2.5

5

4

±5

±18

LF356

10

0.2

5

12

10

±5

±18

LF357

10

0.2

20

50

10

±5

±18

32

Dual BiFet

Minimum Gain of 5

o

General Purpose Operational Amplifier Selection Guide
vos
mV(Max)

Part #

Commercial Temperature Range (O'C to

±6

±18

~

13

5.6

±6

±18

0.2

1

0.5

TL081C

15

0.2

4

TL082C

15

0.2

4

Slew
Rate
V/p.s (Typ)

Supply
Current
(Note 3)
mA(Max)

Vos
mV(Max)

Ie
nA(Max)

LM604

3

60

7

3

9

0.1

0.05

Automotive Temperature Range ( - 40'C to

LM2904

7

250

LM2924

7

250

·Not Specified.

·
·
·

·
·
·

±6

iii

Dual BiFet

:::J
G)

III

Special
Features

Max
V

+ 85'C)
4

36

Multiplexed Op Amp

0.15

3

26

Quad

3

3

26

Quad

2

3

26

Quad

2

3

26

Comparator Plus Op Amp

Note 2: Those looking for a commercial part should also look at the Industrial Temp Range guide as many Hybrids are listed there.
Nole 3: Supply current is for ali amplifiers in a package.
Nole 4: The LM10 has 2 versions: one a high voltage part, good to 45V and a low voltage part, good to 7V. Refer to the datasheet for more information.
Nole 5: The LM146 and LM4250 are programmable amplifiers. The data shown is for Vs =

0'

c
is:
(I)

Supply
Voltage
Min
V

Quad BiFet

Note 1: Datasheet should be referred to for test conditions and more detailed information.

33

...

CD'

2.8

15

20

::;:

13

LF13741

250

3

'3!.

±18

1

7

»

4

1

4

:::J

!!!..

en
(I)

1

LP2902

Special
Features

±18

0.1

LM2902

Max
V

a
0'

.

10

GBW
MHz (Typ)

Min
V

+ 70'C) (continued)

LF444

Part #

(I)

Supply
Voltage

Supply
Current
(Note 3)
mA(Max)

Slew
Rate
V/p.s (Typ)

GBW
MHz (Typ)

Ie
nA(Max)

"0

(Continued)

± 15V and ISET = 10 p.A. Refer to the datasheets for more information.

:g

"CJ'S

~NatiOnal

Semiconductor
Corporation

c

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~...

Low IBIAS Selection Guide

,!!!

:t:

is.

E


(')

~NatiOnal
Semiconductor
Corporation

~.

:!!
;::;:

CD
...,
en
CD

Active Filter Selection Guide

(D

-

(')

ci"

:::J

C>
c:::

Max
Order

Max Freq
Accuracy

Freq
Range

Typ.Q
Accuracy

Max
FxQ

Device #

Type

MF10 (S, T)

Universal

Universal

4th

±0.6%

0.1-30 kHz

±2%

200 kHz

Bandpass

Chebyshev
Butterworth

4th

±1.0%

0.1-20 kHz

±2%

5 MHz

MF6 (S, T)

Lowpass

Butterworth

6th

±1.0

0.1-20 kHz

N/A

N/A

MF5(S)

Universal

Universal

2nd

±1.0%

0.1-30 kHz

±6%

200 kHz

MF8 (Tl

Function

MF4(S)

Lowpass

Butterworth

4th

±0.6%

0.1-20 kHz

N/A

N/A

'LMF100

Universal

Universal

4th

±0.6%

40 kHz

±2%

1.8MHz

'LMF60

Lowpass

Butterworth

6th

±0.6%

40 kHz

N/A

N/A

S Surface Mount Available

T Extended Temperature Available
'" Advance Information

47

ii
CD

o
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'2

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r--------------------------------------------------------------------.

~ Semiconductor
NatiOnal

Corporation

Analog Switch
Definition of Terms

.c
u

~
Q

o
'ii
c
c(

RON: Resistance between the output and the input of an
addressed channel.

10-15: Leakage current that flows from the closed switch
into the body. This leakage is the difference between the
current 10 going into the switch and the current Is going out
of the switch.
tRAN: Delay time when switching from one address state to
another.

Is: Current at any switch input. This is leakage current when
the switch is ON.
10: Current at any switch input going into the switch. This is
leakage current when the switch is OFF.
es: Capacitance between any open terminal "S" and
ground.
eo: Capacitance between any open terminal "Dn and
ground.

tON: Delay time between the 50% points of an enable input
and the switch ON condition.
tOFF: Delay time between the 50% pOints of the enable
input and the switch OFF condition.

48

~NatiOnal

Semiconductor
Corporation

Analog Switch/Multiplexer Selection Guide

RON

CMOS

±7.5
±7.5
±15
±15
±15
±15
±15
±12

150/300
150/300
20/40
25/50
90/500
90/500
90/500
90/500
90/500
5/8

100
150
850
280
200
200
200
200
200
40

TTL,CMOS

-

150/300

150

160175
15/16

300
40

150/300
150/300

100
150

Function

Logic Input

AH5011
AH5012
CD4016
CD4066
LF11201/LF13201
LF11202/LF13202
LF11331/LF13331
LF11332/LF13332
LF11333/LF13333
MM74HC4016

QUADSPST

TTL,CMOS
TTL,CMOS
CMOS
CMOS

AH5020

DUALSPDT
TRIPLESPDT

CMOS
CMOS

4-CHANNEL

TTL,CMOS
TTL,CMOS

CD4053
MM74HC4053
AH5009
AH5010

Vs

TON/TOFF
ns (Typ)

Part Number

TTL
TTL
TTL
TTL
TTL

(Typ)

-

±7.5
±6.0

-

n

CD4052
CD4529B
LF13509
MM74HC4052

4-CHANNEL
DIFFERENTIAL

CMOS
CMOS
TTL,CMOS
CMOS

±7.5
±7.5
±18
±6.0

160175
50
1600/200
15/16

300
350
350
40

CD4051
CD4529B
LF13508
MM74HC4051

8-CHANNEL

CMOS
CMOS
TTL,CMOS
CMOS

±7.5
±7.5
±18
±6.0

160/75
50
1600/200
15/16

300
350
350
40

49

~ r-------------------------------------------------------------------------~

~
~

c

o

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c
......

1E

NatiOnal

~ Semiconductor
Corporation

Definition Of Terms
AID Converters

{!!.
'0
c

~c

~

Conversion Time: The time required for a complete measurement by an analog-to-digital converter.

Multiplying DAC: In a sense, every DAC is a multiplying
DAC since the output voltage (or current) is equal to the
reference voltage times a constant determined by the digital
input code divided by 2n (n is the number of bits of resolution). In a two quadrant multiplying DAC the reference voltage or the digital input code can change the output voltage
polarity. If both the reference voltage and the digital code
change the output voltage polarity four quadrant multiplication exists.
Offset Error (Zero Error): In a DAC, this is the output voltage that exists when the input digital code is set to give an
ideal output of zero volts. In the case of an ADC, this is the
difference between the ideal input voltage (% LSB) and the
actual input voltage that is needed to make the transition
from zero to 1 LSB. All the digital codes in the transfer curve
are offset by the same value. Many converters allow nulling
of offset with an external potentiometer. Offset error is usually expressed in LSBs.
Power Supply Rejection (Power Supply Sensitivity): The
sensitivity of a converter to changes in the dc power supply
voltages.

DC Common-Mode Error: This specification applies to
ADCs with differential inputs. It is the change in the output
code that occurs when the analog voltages on the two inputs are changed by an equal amount. It is expressed in
LSBs.
Differential Nonlinearity: Ideally, any two adjacent digital
codes correspond to measured analog voltages that are exactly one LSB apart. Differential non-linearity is a measure
of the worst case deviation from the ideal 1 LSB step. For
example, a DAC with a 1.5 LSB output change for a 1 LSB
digital code change exhibits % LSB differential non-linearity.
Differential non-linearity may be expressed in fractional bits
or as a percentage of full scale. A differential non-linearity
greater than 1 LSB will lead to a non-monotonic transfer
function in a DAC and missing codes in an ADC.
Gain Error (Full Scale Error): For an ADC, the difference
(usually expressed in LSBs) between the input voltage that
should ideally produce a full scale output code and the actual input voltage that produces that code. For DACs, it is the
difference between the output voltage (or current) with full
scale input code and the ideal voltage (or current) that
should exist with a full scale input code.

Quantizing Error: The error inherent in all AID conversions. Since even an "ideal" converter has finite resolution,
any analog voltage that falls between two adjacent output
codes will result in an output code that is inaccurate by up to
% LSB.
Ratlometrlc Operation: Many AID applications require a
stable and accurate reference voltage against which the input voltage is compared. This approach results in an absolute conversion. Some applications, however, use transducers or other signal sources whose output voltages are
proportional to some external reference. In these ratlometriC applications, the reference for the Signal source should
be connected to the reference input of the converter. Thus,
any variations in the source reference voltage will also
change the converter reference voltage and produce an accurate conversion.

Gain Temperature Coefficient (Full Scale Temperature
CoeffiCient): Change in gain error divided by change in
temperature. Usually expressed in parts per million per degree Celsius (ppmI"C).
Integral Nonlinearity (Linearity Error): Worst case deviation from the line between the endpoints (zero and full
scale). Can be expressed as a percentage of full scale or in
fractions of an LSB.
LSB (Least-Slgniflcant Bit): In a binary coded system this
is the bit that carries the smallest value or weight. Its value
is the full scale voltage (or current) divided by 2n, where n is
the resolution of the converter.
Missing Codes: When an incremental increase or decrease
in input voltage causes the converter to increment or decrement its numeric output by more than one LSB the converter is said to exhibit "missing codes". If there are missing
codes, there is a numeric value on the output on the converter which cannot be reached by any input voltage value.
Monotoniclty: A monotonic function has a slope whose
sign does not change. A monotonic DAC has an output that
changes in the same direction (or remains constant) for
each increase in the input code. The converse is true for
decreasing codes.

Resolution: The smallest analog increment corresponding
to a 1 LSB converter code change. For converters, resolution is normally expressed in bits, where the number of analog levels is equal to 2n. As an example, a 12-bit converter
divides the analog signal into 212 = 4096 discrete voltage
(or current) levels.
Settling Time: The time from a change in input code until a
DAC's output signal remains within ± % LSB (or some other
specified tolerance) of the final value.

MSB (Most Significant Bit): In a binary coded system this
is the bit that has the largest value or weight. Its value is one
half of full scale.

50

»
.....
c

~NatiOnal

n
o

Semiconductor
Corporation

:::I

-...
Ii...
CD

AID Converter Selection Guide

en
CD

CD

(')

o·

Part
No.

Absolute
Input
Resolution
Conversion
Accuracy
Voltage
(Bits)
Time
(Max)
Range

Output
Logic
Levels

Supplies
(V)

Temperature
Range'
M

I

Package

Comments

C

AID CONVERTER
TTL,
+5, -12
TRI-STATE

•

5V

TTL,
TRI·STATE

+5

•

•

110 ".S

5V

TTL,
TRI·STATE

+5

•

•

•

20·PinDIP
20·PinSO Differential Input
20·PinPCC

±%LSB

110 ".S

5V

TTL,
TRI·STATE

+5

•

•

•

20·PinDIP
20·PinSO Differential Input
20·PinPCC

8

±1 LSB

110 ".S

5V

TTL.
TRI·STATE

+5

•

•

20·PinDIP
20·PinSO Differential Input
20·PinPCC

ADC0805

8

±1 LSB

110 ".S

5V

TTL.
TRI·STATE

+5

•

20·PinDIP

ADC0808

8

±%LSB

100 ".S

5V

TTL.
TRI·STATE

+5

•

28·PinDIP
8·Channel MUX
28·PinPCC

ADC0809

8

±1 LSB

100 ".S

5V

TTL.
TRI·STATE

+5

•

28·PinDIP
8·Channel MUX
28·PinPCC

ADC0811B

8

±%LSB

32".s

5V

TTL

+5

•

•

20·PinDIP 11-Channel
20·PinPCC Serial 1/0

ADC0811C

8

±1 LSB

32".s

5V

TTL

+5

•

•

20·PinDIP 11·Channel
20·PinPCC Serial 1/0

ADC0816

8

±%LSB

100".s

5V

TTL.
TRI·STATE

+5

ADC0817

8

±1 LSB

100 ".s

5V

TTL.
TRI·STATE

ADC0819B

8

±%LSB

16".s

5V

ADC0819C

8

±1 LSB

16 ".s

ADC0820B

8

±%LSB

ADC0820C

8

±1 LSB

ADC0800

8

±2LSB

50 ".S

±5V

ADC0801

8

±%LSB

110 ".S

ADC0802

8

±%LSB

ADC0803

8

ADC0804

•

18·Pin DIP
20·PinDIP Differential Input

Ratiometric
Operation

•

40-PinDIP 16-Channel MUX

+5

•

40·PinDIP 16·Channel MUX

TTL

+5

•

•

28·PinDIP 19·Channel
28·PinPCC Serial 1/0

5V

TTL

+5

•

•

28·PinDIP 19·Channel
28·PinPCC Serial 110

1.2 ".s

5V

TTL,
TRI·STATE

+5

•

•

•

20·PinDIP
Built·ln Track and
20·PinSO
Hold Function
20·PinPCC

1.2 ".s

5V

TTL,
TRI·STATE

+5

•

•

•

20·PinDIP
Built·ln Track and
20·PinSO
Hold Function
20·PinPCC

51

•

•

:::I
G)
C

c:
CD

AID Converter Selection Guide (Continued)
Part
No.

Absolute
Input
Resolution
Conversion
Accuracy
Voltage
(Bits)
Time
(Max)
Range

Output
Logic
Levels

Supplies
(V)

Temperature
Range"
M

I

Package

Comments

C

AID CONVERTER (Continued)
ADC0829B

8

±%LSB

100 p.s

SV

TTL,
TRI-STATE

+S

•

28·Pin DIP

Additional Digital
Input Capability

ADC0829C

8

±1 LSB

100 p's

SV

TTL,
TRI-STATE

+S

•

28-PinDIP

Additional Digital
Input Capability

Ai:1C0831B

8

±%LSB

32 p's

SV

TTL

+S

±1 LSB

32 p's

SV

TTL

+S

•
•

Serial 1/0

8

•
•

8-Pin DIP

ADC0831C

8-PinDIP

Serial 1/0

ADC0832B

8

±'1z LSB

32 p.s

SV

TTL

+S

•

•

8-Pin DIP

2-Channel
Serial 1/0

ADC0832C

8

±1 LSB

32 p.s

SV

TTL

+S

•

•

8-Pin DIP

2-Channel
Serial 1/0

ADC0833B

8

±%LSB

32 p's

SV

TTL

+S

•

•

14-Pin DIP

4-Channel
Serial 1/0

ADC0833C

8

±1 LSB

32 p's

SV

TTL

+S

•

•

14-Pin DIP

4-Channel
Serial 110

ADC0834B

8

±%LSB

32 p's

SV

TTL

+S

•

•

14-Pin DIP

4-Channel
Serial 1/0

ADC0834C

8

±1 LSB

32 p's

SV

TTL

+S

•

•

14-Pin DIP

4-Channel
Serial 1/0

ADC0838B

8

±%LSB

32 p.s

SV

TTL

+S

•

•

20-Pin DIP 8-Channel
20-PinPCC Serial 1/0

ADC0838C

8

±1 LSB

32 p's

SV

TTL

+S

•

•

20-PinDIP 8-Channel
20-Pin PCC Serial 1/0

ADC0841B

8

±%LSB

40 p's

SV

TTL,
TRI-STATE

+S

•

•

20-Pin DIP Differential Input,
20-PinPCC Internal Clock

ADC0841C

8

±1 LSB

40 p.s

SV

TTL,
TRI-STATE

+S

•

•

20-Pin DIP Differential Input,
20-PinPCC Internal Clock

ADC0844B

8

±%LSB

40 p's

SV

TTL,
TRI-STATE

+S

•

•

20-Pin DIP

4-Channel MUX,
Internal Clock

ADC0844C

8

±1 LSB

40 p's

SV

TTL,
TRI-STATE

+S

•

•

20-PinDIP

4-Channel MUX,
Internal Clock

ADC0848B

8

±%LSB

40 p's

SV

TTL,
TRI-STATE

+S

•

•

28-PinDIP 8-Channel MUX,
28-PinPCC Internal Clock

ADC0848C

8

±1 LSB

40 p's

SV

TTL,
TRI-STATE

+S

•

•

28-Pin DIP 8-Channel MUX,
28-Pin PCC Internal Clock

ADC1001C

10

±1 LSB

200 p's

SV

TTL,
TRI-STATE

+S

•

•

8-Bit Bus
20-PinDIP Compatible,
Differential Input

ADC100SB

10

±%LSB

SO p.s

SV

TTL,
TRI-STATE

+S

•

•

8-BitBus
20-Pin DIP
Compatible,
20-Pin PCC
Differential Input

S2

•

l>
.......

o
oo

AID Converter Selection Guide (Continued)
Part
No.

Absolute
Input
Resolution
Conversion
Accuracy
Voltage
(Bits)
Time
(Max)
Range

Output
Logic
Levels

Supplies
(V)

Temperature
Range*
M

I

~

Package

Comments

C

ADC1021C
ADC1025B

10

10
10

±1 LSB

±1 LSB
±%LSB

I'D

50 J.Ls

200 J.Ls
50 J.Ls

5V

TIL,
TRI-STATE

5V

TIL,
TRI·STATE

+5

·

•
•

+5

5V

TIL,
TRI·STATE

+5

•

+5

•

·
•

· ·
· •

8-Bit Bus
20-Pin DIP
Compatible,
20-Pin PCC
Differential Input
24-Pin DIP Differential Input
24-Pin DIP
Differential Input
28-Pin PCC
24-Pin DIP
Differential Input
28-Pin PCC

ADC1025C

10

±1 LSB

50 J.Ls

5V

TIL,
TRI-STATE

ADC1205B

12+sign

±%LSB

100 J.Ls

±5V

TIL,
TRI-STATE

+5, ±5

•

•

8-Bit Bus
24-Pin DIP Compatible,
Differential Input

ADC1205C

12+sign

±1 LSB

100 J.Ls

±5V

TIL,
TRI-STATE

+5, ±5

·

•

8-Bit Bus
24-Pin DIP Compatible,
Differential Input

ADC1210

12

±%LSB

200 J.Ls

10.2V

ADC1211

12

±2 LSB

200 J.Ls

10.2V

ADC1225B

12+sign

±%LSB

100 J.Ls

±5V

TIL,
TRI-STATE

+5, ±5

•

•

28-Pin DIP

Differential
Input

ADC1225C

12+sign

±1 LSB

100 J.Ls

±5V

TIL,
TRI-STATE

+5, ±5

•

•

28-Pin DIP

Differential
Input

ADC3511

3%-Digit

0.05%

200ms

2V

TIL,
TRI-STATE

+5

•

24-Pin DIP

Integrating
J.LP Compatible

ADC3711

3%-Digit

0.05%

400ms

2V

TIL,
TRI-STATE

+5

•

24-Pin DIP

Integrating
J.LP Compatible

•

VOltage-to8-Pin DIP or Frequency
TO-99 Can Converter
100 kHz Max

LM131

V-F

0.01%

N/A

CMOS

+5to ±15

CMOS

+5to ±5

Open
Vee - 2V
Collector

+5to +40

·•

•

•
•

•

24-Pin DIP
24-Pin DIP

DIGITAL VOLTMETER
ADD3501

3%-Digit

0.05%

200ms

2V

7-Segment
LED Drive

+5

•

28-Pin DIP

3%-Digit
LED DVM

ADD3701

3%-Digit

0.05%

400ms

2V

7-Segment
LED Drive

+5

•

28-Pin DIP

3%-Digit
LED DVM

*Temperature ranges: "M" is -55°C to

-......
-

en
I'D

AID CONVERTER (Continued)
ADC1005C

<
I'D

+ 125°C ambient;

"I" is -40·C to +85°C or -25°C to +85°C; "C" is D·G to +70·C.

53

CD
0o

~

G>

c:

c::

I'D

f

~
~
c
o

o
~

!E

r-------------------------------------------------------------------------------------~

_

National

Semiconductor
Corporation

Definition of Terms
01 A Converters

~

'0
c

o
-2

:;:

li
c

Conversion Time: The time required for a complete measurement by an analog-to-digital converter.

Multiplying DAC: In a sense, every DAC is a multiplying
DAC since the output voltage (or current) is equal to the
reference voltage times a constant determined by the digital
input code divided by 2n (n is the number of bits of resolution). In a two quadrant multiplying DAC the reference voltage or the digital input code can change the output voltage
polarity. If both the reference voltage and the digital code
change the output voltage polarity, four quadrant multiplication exists.
Offset Error (Zero Error): In a DAC, this is the output voltage that exists when the input digital code is set to give an
ideal output of zero volts. In the case of an ADC, this is the
difference between the ideal input voltage (% LSB) and the
actual input voltage that is needed to make the transition
from zero to 1 LSB. All the digital codes in the transfer curve
are offset by the same value. Many converters allow nulling
of offset with an external potentiometer. Offset error is usually expressed in LSBs.

DC Common-Mode Error: This specification applies to
ADCs with differential inputs. It is the change in the output
code that occurs when the analog voltages on the two inpuis are changed by an equal amount. It is expressed in
LSBs.
Differential Nonlinearity: Ideally, any two adjacent digital
codes correspond to measured analog voltages that are exaclly one LSB apart. Differential non-linearity is a measure
of the worst case deviation from the ideal 1 LSB step. For
example, a DAC with a 1.5 LSB output change for a 1 LSB
digital code change exhibits % LSB differential non-linearity.
Differential non-linearity may be expressed in fractional bits
or as a percentage of full scale. A differential non-linearity
greater than 1 LSB will lead to a non-monotonic transfer
function in a DAC and missing codes in an ADC.
Gain Error (Full Scale Error): For an ADC, the difference
(usually expressed in LSBs) between the input voltage that
should ideally produce a full scale output code and the actual input voltage that produces that code. For DACs, it is the
difference between the output voltage (or current) with full
scale input code and the ideal voltage (or current) that
should exist with a full scale input code.

Power Supply Rejection (Power Supply Sensitivity): The
sensitivity of a converter to changes in the dc power supply
voltages.
Quantizing Error: The error inherent in all AID conversions. Since even an "ideal" converter has finite resolution,
any analog voltage that falls between two adjacent output
codes will result in an output code that is inaccurate by up to
% LSB.
Ratiometric Operation: Many AID applications require a
stable and accurate reference voltage against which the input voltage is compared. This approach results in an absolute conversion. Some applications, however, use transducers or other signal sources whose output voltages are
proportional to some external reference. In these ratlometric applications, the reference for the signal source should
be connected to the reference input of the converter. Thus,
any variations in the source reference voltage will also
change the converter reference voltage and produce an accurate conversion.

Gain T!,mperature Coefficient (Full Scale Temperature
Coefficient): Change in gain error divided by change in
temperature. Usually expressed in parts per million per degree Celsius (ppmI"C).
Integral Nonlinearity (Linearity Error): Worst case deviation from the line between the endpOints (zero and full
scale). Can be expressed as a percentage of full scale or in
fractions of an LSB.
LSB (Least-Significant Bit): In a binary coded system this
is the bit that carries the smallest value or weight. Its value
is Ihe full scale voltage (or current) divided by 2n, where n is
the resolution of the converter.
Monotonicity: A monotonic function has a slope whose
sign does not change. A monotonic DAC has an output that
changes in the same direction (or remains constant) for
each increase in the input code. The converse is true for
decreasing codes.
MSB (Most Significant Bit): In a binary coded system this
is the bit that has the largest value or weight. Its value is one
half of full scale.

Resolution: The smallest analog increment corresponding
to a 1 LSB converter code change. For converters, resolution is normally expressed in bits, where the number of analog levels is equal to 2n. As an example, a 12-bit converter
divides the analog signal into 212 = 4096 discrete voltage
(or current) levels.
Settling Time: The time from a change in input code until a
DAC's output signal remains within ± % LSB (or some other
specified tolerance) of the final value.

54

c
.......

»

~NatiOnal

o
o

Semiconductor
Corporation

::l

...~
...CD
en

Of A Converter Selection Guide

CD

-

CD

n

O·

Part
No.

Resolution
(Bits)

Linearity
@2S"C
% (Max)

Settling
Time
(+'h LSB)

Temperature
Range"

Supplies
(V)

M

Package

I

C

Comments

ADC08S2

8

0.19

5

•

•

8-Pin DIP

DAC, Comparator,
Serial Input

ADC0854

8

0.19

5

•

•

14-Pin DIP

DAC, Comparator,
Serial Input

DAC0800

8

0.19

lOOns

±5to ±15

0

•

lS-Pin DIP
lS-pinS.a.

High-Speed
Multiplying

DAC0801

8

0.39

lOOns

±5to ±15

•

•

lS-Pin DIP
lS-pinS.a.

High-Speed
Multiplying

DAC0802

8

0.10

lOOns

±5to ±15

0

•

lS-Pin DIP
lS-pinS.a.

High-Speed
Multiplying

DAC080S

8

0.78

150 ns

±5to ±15

•

lS-Pin DIP
lS-pinS.a.

Multiplying

DAC0807

8

0.39

150 ns

±5to ±15

•

lS-Pin DIP
lS-pinS.a.

Multiplying

DAC0808

8

0.19

150 ns

±5to ±15

•

•

lS-PinDIP
lS-pinS.a.

Multiplying

DAC0830

8

0.05

1

"'S

5to 15

•

•

20-PinDIP
20-pinS.a.
20-Pin PCC

",p Compatible
4-Quadrant
Multiplying

DAC0831

8

0.10

1

"'S

5to 15

•

20-Pin DIP

",p Compatible
4-Quadrant
Multiplying

DAC0832

8

0.20

1

"'S

5to 15

•

•

20-Pin DIP
20-pinS.a.
20-PinPCC

",p Compatible
4-Quadrant
Multiplying

DAC1000

10

0.05

500 ns

5to 15

0

•

24-PinDIP

",p Compatible
Double Buffered

DAC100l

10

0.1

500 ns

5to 15

•

24-Pin DIP

",p Compatible
Double Buffered

DAC1002

10

0.2

500ns

5to 15

•

•

•

24-Pin DIP

",p Compatible
Double Buffered

DAC100S

10

0.05

500 ns

5to 15

•

•

•

20-Pin DIP

",p Compatible
Double Buffered

DAC1007

10

0.1

500ns

5to 15

•

•

20-Pin DIP

",p Compatible
Double Buffered

DAC1008

10

0.2

500ns

5to 15

•

•

20-Pin DIP

",p Compatible
Double Buffered

55

•

•

•

::l
C)
C

a:
CD

c»
'C
'S 01 A Converter Selection Guide (Continued)
CJ
Linearity
Settling
c
Part
Resolution
Supplies

o

tic»

Ci)

No,

(Bits)

@25°C
% (Max)

Time
(+%LSB)

(V)

Temperature
Range"
M

I

C

Package

Comments

(/)

DAC1020

10

0.05

500n5

5to 15

•

•

•

16-Pin DIP

4-Quadrant
Multiplying

~

DAC1021

10

0.1

500 n5

5to 15

•

•

•

16-Pin DIP

4-Quadrant
Multiplying

DAC1022

10

0.2

500n5

5to 15

•

•

•

16-Pin DIP

4-Quadrant
Multiplying

DAC1208

12

0.012

1 ,",5

5to 15

•

•

24-PinDIP

,",P Compatible
4-Quadrant
Multiplying

DAC1209

12

0.024

1 ,",5

5to 15

•

•

24-Pin DIP

,",P Compatible
4-Quadrant
Multiplying

DAC1210

12

0.05

1,",5

5to 15

•

•

24-Pin DIP

,",P Compatible
4-Quadrant
Multiplying

DAC1218

12

0.012

1 ,",5

5to 15

•

•

18-Pin DIP

4-Quadrant
Multiplying

DAC1219

12

0.024

1 ,",5

5to 15

•

•

18-Pin DIP

4-Quadrant
Multiplying

DAC1220

12

0.05

500 n5

5to 15

•

•

18-Pin DIP

4-Quadrant
Multiplying

DAC1221

12

0.1

500n5

5to 15

•

18-Pin DIP

4-Quadrant
Multiplying

DAC1222

12

0.2

500n5

5to 15

•

•

18-Pin DIP

4-Quadrant
Multiplying

DAC1230

12

0.012

1,",5

5to 15

•

•

20-Pin DIP

,",P Compatible
4-Quadrant
Multiplying

DAC1231

12

0.024

1 ,",5

5to 15

•

•

20-PinDIP

,",P Compatible
4-Quadrant
Multiplying

DAC1232

12

0.05

1 ,",5

5 to 15

•

•

20-Pin DIP

,",P Compatible
4-Quadrant
Multiplying

DAC1265A

12

0.006

200n5

±15

•

•

24-Pin DIP

High-Speed

DAC1265

12

0.012

200n5

±15

High-Speed

12

0.006

200n5

±12to ±15

•
•

24-Pin DIP

DAC1266A

•
•

24-Pin DIP

High-Speed

DAC1266

12

0.012

200n5

±12to ±15

•

•

24-Pin DIP

High-Speed

...

~
c
o
o
 10W)
FM

STEREO
DEMOD
LM1870

FM IF
LM1965

TUNER

AM T

AM RF/IF
LM1863

~

I
I

I--

TONE/VOLUME
LM833
LM1035
LM1036
LM1040

-

POWER AMPS
LM1875
LM391

-l(]
rl(]

I I
EQUALIZER
LMC835

TAPEJ

I

CASSETTE
PREAMP
LM833
LM1897

-I

DOLBY
LM1131

I-

PHONO
PREAMP
LM833
TUXX/OOI3-3

1-6

Automotive Radio (Electronically Tuned)
STEREO
DEMOD
LM1870
LM4500

FM

POWER AMPS
LM383
LM2002
LM2005

AUDIO
SWITCH
LM1037
LM1038

AM

CASSETTE
PREAMP
LM1837
LM1897
TL/XX/0013-4

Auto Radio (Manually Tuned)
STEREO
DECODER
LM1870
LM4500

FM

TONE/VOLUME
LM1035
LM1036
LM1040

AM

POWER AMPS
U.t383
LM2002
LM2005

CASSETTE
PREAMPS
LM1837
LM1897
TL/XX/0013-5

II

1-7

~ r-----------------------------------------------------------------------------------~
~

;
..J

~NatiOnal
Semiconductor
Corporation

LM377 Dual 2 Watt Audio Amplifier
General Description
The LM377 is a monolithic dual power amplifier which offers
high quality performance for stereo phonographs, tape players, recorders, and AM-FM stereo receivers, etc.
The LM377 will deliver 2W/channel into 8 or 16n loads.
The amplifier is designed to operate with a minimum of external components and contains an internal bias regulator to
bias each amplifier. Device overload protection consists of
both internal current limit and thermal shutdown. For more
information, see AN-125.

Features
•
•
•
•
•

•
•
•
•
•

Self centered biasing
3 Mn input impedance
10-26V operation
Internal current limiting
Internal thermal protection

Applications
•
•
•
•
•
•
•
•
•

Multi-channel audio systems
Tape recorders and players
Movie projectors
Automotive systems
Stereo phonographs
Bridge output stages
AM-FM radio receivers
Intercoms
Servo amplifiers

Avo typical 90 dB
2W per channel
70 dB ripple rejection
75 dB channel separation
Internal sta.y.·w·zaLlOIJ__________________________-III-II~I'l.IR'IeIIIt_$~ems-------------~

Connect on

DiagrN'OT TWEC51MMENDED

Dual-I -Line Package
BIAS

FOR

~s~e

v'

"

OUTPUT 1

GND

GND
GNO

4

8U

11 GNO

I.

GND

INPUT 1

INPUT'

INPUT 2

lOOk
FEEDBACK 1

FEEDBACK 2

C,
250"F "'J:foOk

TL/H17837-1

Top View
Order Number LM377N
See NS Package Number N14A

INPun

o--1l------.. . -c~
8"

2k

lOOk

~FT
TL/H17837 -2

1-8

r--------------------------------------------------------------------------------,
NatiOnal

~ Semiconductor

r-

:s::

Co)

......
00

Corporation

LM378 Dual 4 Watt Audio Amplifier
General Description
The LM378 is a monolithic dual power amplifier which offers
high quality performance for stereo phonographs, tape players, recorders, and AM-FM stereo receivers, etc.
The LM378 will deliver 4W channel into 8 or 16!l loads. The
amplifier is designed to operate with a minimum of external
components and contains an internal bias regulator to bias
each amplifier. Device overload protection consists of both
internal current limit and thermal shutdown. For more information see AN-125.

_
_
_
_

Features

-

Self centered biasing
3 M!l input impedance
Internal current limiting
Internal thermal protection

Application
_ Multi-channel audio systems
_ Tape recorders and players
_ Movie projectors
_
_
_
_

_ Avo typical 90 dB

Automotive systems
Stereo phonographs
Bridge output stages
AM-FM radio receivers
Intercoms

- 4W per channel
- 70 dB ripple rejection
_ 75 dB channel separation
..
- Servo amplifiers
- InternaI stalljlW:za.lILUJ'----------------------------;......===;r;;:=1=",---------____--,

Connect on

Diagr~ T Tl!¥~t!~~l: NDE D

Dual·1 ·Line Package

FOR NEW D~.sifier
SEELM
lOOk

14

BIAS
OUTPUT 1

v""

GND

Sn

GND
GNO

INPUT I

INPUT 1

INPUT 2

o-j I---~~H
C,

O.1J.1F
FEEDBACK 1

FEEDBACK 2

II

TL/H17876-1

Top View
Order Number LM378N
See NS Package Number N14A

Sn

Zk

lOOk

TL/H17876-2

1-9

o

CD

:i
C")

~NatiOnal

Semiconductor
Corporation

LM380 Audio Power Amplifier
General Description
The LM380 is a power audio amplifier for consumer application. In order to hold system cost to a minimum, gain is
internally fixed at 34 dB. A unique input stage allows inputs
to be ground referenced. The output is automatically self
centering to one half the supply voltage.
The output is short circuit proof with internal thermal limiting.
The package outline is standard dual-in-line. A copper lead
frame is used with the center three pins on either side comprising a heat sink. This makes the device easy to use in
standard p-c layout.
Uses include simple phonograph amplifiers, intercoms, line
drivers, teaching machine outputs, alarms, ultrasonic drivers, TV sound systems, AM-FM radio, small servo drivers,
power converters, etc.

A selected part for more power on higher supply voltages is
available as the LM384. For more information see AN-69.

Features
•
•
•
•
•
•
•
•

Wide supply voltage range
Low quiescent power drain
Voltage gain fixed at 50
High peak current capability
Input referenced to GND
High input impedance
Low distortion
Quiescent output voltage is at one-half of the supply
voltage
• Standard dual-in-line package

Connection Diagrams (Dual-In-Line Packages, Top View)
BYPASS 1

14 Vs

NON·INVERTING INPUT 2

13 Ne

Ne 1

NON·INVERTING INPUT 2

'GN{

")

11 GND"

INVERTING INPUT 3

I BYPASS

, v,
6 VOUT

10

INVERTING INPUT 6

GNO 1

•

Ne

GND 4

5 GND

8 VOUT

TL/H/6977 -2

·HeatsinkPins

TLlH/6977 -1

Order Number LM380N
See NS Package Number N14A

Order Number LM380N·8
See NS Package Number N08E

Block and Schematic Diagrams
LM380N
, . - - - - - - - - - - - - -. . .- - -............-oV,I1 ..
BYPASS

Vs

INPUT

INPUT
Z5K

,.-_ _ _JI,I\"..,.._ _ _ _-I-___-4......-o~~TPUT

..

(3.4.6.10.11,121

GN.

TLlH/6977-5

r-

s::

Absolute Maximum Ratings

Co)

CD

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

22V

Peak Current

1.3A

Package Dissipation 14-Pin DIP (Notes 6 and 7)

S.3W

Package Dissipation S-Pin DIP (Notes 6 and 7)

1.67W

Input Voltage

±0.5V

Storage Temperature

o

-65'C to + 150'C
O'Cto +70'C

Operating Temperature
Junction Temperature

+ 150'C

Lead Temperature (Soldering, 10 sec.)

+ 260'C

ESD rating to be determined

Electrical Characteristics (Note 1)
Symbol

Parameter
Output Power

POUT(RMS)

RL

=

Conditions

Min

=

2.5

SO, THD

3% (Notes 3,4)

40

Typ

Max

Units

50

60

V/V

W

Av

Gain

VOUT

Output Voltage Swing

liN

Input Resistance

THD

Total Harmonic Distortion

(Notes 4, 5)

0.2

%

PSRR

Power Supply Rejection Ratio

(Note 2)

3S

dB

Vs

Supply Voltage

BW

Bandwidth

IQ

Quiescent Supply Current

RL

SO

Quiescent Output Voltage

ISlAS

Bias Current

=

2W, RL

=

Note 1: Vs

=

V p_p

150k

0

S
Inputs Floating

22
100k

SO

Short Circuit Current

Isc

14

10
POUT

VOUTO

V
Hz

7

25

9.0

10

mA
V

100

nA

1.3

A

16V and TA = 25g C unless otherwise specified.

Note 2: Rejection ratio referred to the output with CBYPASS

=

Note 3: With device Pins 3, 4, 5, 10, 11, 12 soldered into a

1,1,6"

Note

=

4: CSYPASS

~

5 JLF.
epoxy glass board with 2 ounce copper foil with a minimum surface of 6 square inches.

0.47 I'fd on Pin 1.

Note 5: The maximum junction temperature of the LM3BO is 150°C.
Note

6: The package is 10 be deraled all5'C/W iunclion 10 heal sink pins for 14·pin pkg; 75'C/W for 8·pin.

Heat Sink Dimensions

t·~
y

r-1.5"---i
I

I

I

I

I

I
I
I
I

I

I
I

~

---l 0.25!--

Staver Heat Sink #V-7

Staver Company
41 Saxon Ave.
P.O. Drawer H

11
1.5"

1.55

J I

Bayshore, NY 11706
Tel: (516) 666-8000
Copper Wings
2 Required
Soldered to

Pins 3, 4, 5,
10,11,12
Thickness 0.04
Inches

TL/H/6977 -6

1-11

II

CI

co

~

Typical Performance Characteristics

...I

Maximum Device Dissipation vs
Ambient Temperature
10
I I I
I
INFINITE HEAT SINK
I
I

I
I

ST1V£Rl

.1.,.....,

I
I

vJ-

•,1"IN,

Ico~PEIj WI,!=!

SQ.

:II

PPER
FOIL

FREE Alit;/"
...,..
2 IN. SQ.
COPPER FOIL (P.C. BOARD)

o
o

10 20 30 40

so

~~
~~~~
~g~~

60 70 80 90 100

TA-AMBIENT TEMPERATURE (OCl
Note: 2 oz. copper foU. single-sided PC board.

Device Dissipation vs Output
Power--411 Load
3.5

3%01$T
LEVEL

30

5

2.5

~

z

V
~
./~ /
12V
10V I- -,

14Y ~

2.0

C>

i

1.5

~

10

u

~

r

.V

"
/

o

1.5 'Z.O

05 t.O

2.5 3.0

2.0

::

~-~
1.5 I.
16V
1.0 I.V
12Vr::f""
10%
0.5
DlST.

V
l/:v

B.O

~

•. 0

-

7.0

~

I"""

5.0

~
'"

C>

~1.5
1.0

LEIVE~

~

~D.5

o

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

OUTPUT POWER {WATTSI

Output Voltage Gain and
Phase vs Frequency
40

TA=2S-C~

III

35

=

iii 30

'z"

~
~

10

12

14

16

lB

20

22

100 200

500

v· SUPPLY VOLTAGE (V)

15

10

~
is

taYrASS .. &,..f

i

HEATSINK = TWO
COPPER WINGS

5.0

SEE FIG. PAGE.

~

•. 0

:

3.0

I

18D'~
240'
30D'

i

iiic;

0.3

1-/ -Rl=181l

0.2

II

~

u

~

2.0

1.0
0

,r

0.1

0.2

0.5

1.0

2.0

5.0

Po - OUTPUT POWER (WATTS)

10

0.1

I

'1/-

~'3%

o ~

/

THO

I

0.2

0.3

10k

lOOk

C>

~ ZOdB

~

I

D..

OUTPUT POWER IWATTSI

10dB

11111
11111

II
II

5~F

'J.,..!o

3BD'
1M

10M

~

~

D.471£F

NO

III ~ III
BY~l~I~APACITOR
I

0.5

"7

2~'

~ JOd8

-IVe~~9V

I

40dB

~

I I

11
0.1

I

1/
v.!.
1"THD

A'

RL'" 4011

o

CJ

I
I

Ik

Supply Decoupllng vs
Frequency

RLI~·ln

I'"

0.'

100

FREQUENCY (HZ")

50dS

E

6.0

10

2k

0.5

Vee = 22V
RL = 8n

t; 1.0

,.

Device Dissipation vs
Output Power

""

'''' 1 kHz

i ..0

~

1ZD'

RL" an j
PrUT=ZW

FREnUENCY (HII

Total Harmonic Distortion
vs Output Power

~ 9.0

c

S..

III
PjAjEI

20

IIIII
BD

e

..

~~~

25

~ 10

o

~

Vee = IIV

III

2.0
.E 1.0

g

~rl

~i)'

:.f- ~~~ r-- >~i:l
11

20

1.0 1.5 2.0 2.5 3.0 35 4.04.55.0

'.0
3.0

I,

~

2.0 r--r-T'T.,.-....,.......,r-r"TT-"-""

9.0

-

z

~~\' ~

Total Harmonic Distortion
vs Frequency

Power Supply Current vs
Supply Voltage

z

~

LEVEL

OUTPUT POWER (WATTSI

10.0

0-

II
3%DIST.

5!. 2.0

lEVEl

o 0.5

3.5 4.0

OUTPUT POWER (WATTSI

.,.!i

-

~~;I/'

Device Dissipation vs Output
Power-1611 Load

3.0

iii 2.5

.....

-- ~\r-:-tt

~

"

o

2.5

is

u

;1-

0.5

30

c

iiic;

"~-

Lrm

-

e
;::

10%

Device Dissipation vs Output
Power-811 Load

3.'

~

t;.rrt /1 I-/

TL/H/6977 -12

10H,

100Hz

11I11I~
1 kHz

I 1\111
10kHz

FREQUENCY
TL/H/6977-7

1-12

Typical Applications
Phono Amplifier

CRYSTAL
CARTRIDGE

TLlHI6977-B

Bridge Amplifier

v,

v,

TLIHI6977 -9

Intercom

v,

LISTEN

I

TALK

I

!

:;r'"'
L__________________________

I

I
I
I

~

-FOR STABILITY WITH
HIGH CURRENT LOADS

TLIHI6977-10

Phase Shift Oscillator

f

~

4kHz

TLIHI6977 -11

1-13

II

---'---"-00.5 Vrms

II

1.2M

240
lOOk

TLlHI7841-3

Two-Pole Fast Turn-On NAB Tape Preamp

TLlH17841-4

Audio Mixer

24V

24V

(7,8)
(7,8)

1 "F

120pF
A

II
2k

Bo_f. F_~~

C~,,~F-~~'---e---JVj9~~~--~

2k
24k

-

~

2~F

22K

........

220k

220k

0--1 ~>IV--'<~
!,,!

;rM -

500 Kn

:

2.4K

No--...U·-~-..1

"
TL/HI7841-5
TL/H/7841-6

Ultra-Low Distortion Amplifier
(Ay = 10, THD < 0.05%, VOUT = 3 VRMS)
24V

(7,8)

1 ~F

YIN

10k

~ ..+~'V\"..,.-.;.;...;~
Av = 10

lOOk

TLlH17841-7

1·16

Typical Performance Characteristics
pop Output Voltage

Large Signal Frequency
Response

Vee Swing vs

Veevslee

22,-----r--,.,0--,::.".-,...-,=::1

13.-.-.----.-----r--.-.--,--,

20 1---t-,-t.~~rD~~~R'rio~ ~

12r-+-+-+-l--+-+-+-1

161--t----v----+--+---l

llr-+-+-+-t--+-+--+-1

18r-~r-~--~--~---1
14r---r--l~-l---1---1

10r-+-~~~~~-+-1--r---1

12r---r--t~-t---1---1

2Or---+---t7/L--t-----l

10 1---+----1-\,,-----1---+---1

9r-t--l-+-+-1-t1--r-1

81---+--l-~\1---+---1

81-t-t-+-+-+-+-+-~

61--+-+~\~-+--1
4r--t--+-~--+---l
O~~-~--L~~~

1M

10M

101---V/!C--l---1--1

/

71-t-t-+-+-+-+-+-~

__+--1

21--+-+~~,,

1kHz 10kHz 100kHz

6~~~~~~~~~

o

lOON

5

20

W g

~

~

~

O~-~-~-~-~

% Distortion
,-;--;--.---.-----r-,-,--,

Channel Separation
70,-----rr-----r------r------r---,

1.1

50 1---+--+-+---P~""__1

~I--+-+-+-+-+-t--~

./---"

120I--+/-,l""-+-P-.d----l
'iii"

110 1-+,-1-S~1n-,(-+---+-1

D.61-1--I1--I,-----I,-----I,-----I,-----I,-----I

~I--+-+--+-+---'I

D.51--+:::-±=±-±-+-t--~

OA I-fNA=B'-iE",Q",UIVf~",LE'1N,-T~-1'"

~~4=~~:;~f;~~~
__
__
100

lk

~~~d~B

10k

~

O~~-~--L-~~

lOOk

10

FREQUENCY (Hz)

1kHz 10kHz 100kHz lMHz

i
~

100

...... :"0

1L
~--I--

500~F!!C1+

r--R'~ 1_~IOO0
=f~

7O~-L_.l--'-_.l-~~

10

100

190

280

370 460

550

FREQUENCY (Hz)

12 Noise Voltage vs Frequency
15

NOTE:

!~

'\ "'

Ei~1---

"(

FREQUENCY (Hz)

Gain and Phase Response

:~~
1~

100

~

PSRR vs Frequency
130 ,---r--.-----r--...,----.,.--,

.....

60

DB I-t-+-+-+-t-t--H

~

20

SUPPLY VOLTAGE(V)

1.0 val = 12V-+-1-t-+-+--1
03r-t-+-+-1--r-+-+--l

10

10

o

~

SUPPLY VOLT~GE(V)

FREQUENCY (Hz)

M~~~~~

f--+---t-----b'/<--..j

30

10 '\

80r-+~~~~~N--r-+-160
I'\. '\.
75
60 r--rP
c:.HASepE'--1'_+''''-::
~r-+-1~~5

:~~EO_ SI~G~E IJ~D

8r-~~~~-r-l-H~

70

~

,",
'\.

30

20
10

o

1

.3 1---l-H1I-HtH----1F'1"'H-I1o

High peak current capability (3.5A)
Large output voltage swing
Externally programmable gain
Wide supply voltage range (5V-20V)
Few external parts required
Low distortion
High input impedance
No turn-on transients
High voltage protection available (LM383A)
Low noise
AC short circuit protected

Equivalent Schematic
.--------1~~~----~----~~--~----._--_1~------t_~VS

.....ot-.H.....";'O VOUT

L-~~~--~--_4------~--~--~----4--------------------4~~GNO

+INPUT

-INPUT
TL/H17145-1

Connection Diagram
Plastic Package
5 SUPPl Y VOLTAGE

o

4 OUTPUT
3 GROUND
2 INVERTING INPUT
1 NON·INVERTING INPUT
TL/H17145-2

Order Number LM383T or LM383AT
See NS Package Number T05B

1-21

III

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Peak Supply Voltage (50 ms)
LM3B3A (Note 2)
40V
LM3B3
25V
Operating Supply Voltage
20V
Output Current
Repetitive
3.5A
Non-repetitive
4.5A

Electrical Characteristics Vs =
Parameter

Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 sec.)

15W
O·Cto +70·C
-60·Cto + 150·C
260·C

14.4V, TTAB = 25·C, Av = 100 (40 dB), RL = 4n, unless otherwise specified
Conditions

DC Output Level
Quiescent Supply Current

±0.5V

Input Voltage
Power Dissipation (Note 3)

Min

Typ

Max

6.4

7.2

a

V

45

BO

mA

20

V

Excludes Current in Feedback Resistors

Supply Voltage Range

5

Input Resistance

Units

150

kn

30

kHz

4.7
7.2

W
W

5.1
7.B

W
W

5.5
B.6
9.3

W
W
W

7
10.5
11

W
W
W

0.2
0.2

%
%

40
44

dB
dB

2

jJ.V

40
Input Noise Current
Rs = 100 kn, 15 kHz Bandwidth
Note 1: A 0.2 I'F capacitor in series with a 10 resistor should be placed as close as possible to pins 3 and 4 for stability.
Note 2: The LM383 shuts down above 25V.

pA

Bandwidth

Gain = 40dB

Output Power

Vs
RL
RL
Vs
RL
RL
Vs
RL
RL
RL
Vs
RL
RL
RL

=
=
=
=
=
=
=
=
=
=
=
=
=
=

13.2V, f = 1 kHz
4n, THD = 10%
2n, THD = 10%
13.aV, f = 1 kHz
4n, THD = 10%
2n, THD = 10%
14.4V, f = 1 kHz
4n, THD = 10%
2n, THD = 10%
1.6n, THD = 10%
16V,f = 1 kHz
4n, THD = 10%
2n, THD = 10%
1.6n, THD = 10%

4.B
7

THD

Po = 2W, RL = 4n, f = 1 kHz
Po = 4W, RL = 2n, f = 1 kHz

Ripple Rejection

Rs=50n,f=100Hz
Rs = 50n, f = 1 kHz

Input Noise Voltage

Rs = 0, 15 kHz Bandwidth

30

Note 3: For operating at elevated temperatures, the device must be derated based on a 1500C maximum junction temperature and a thermal resistance of 4"C/W
junction to case.

1-22

Typical Performance Characteristics

16
14

."

~

12

;::
;;!

10

i:i
co

T

~

."

I I I I
I I I I

o w m

~

~

~

ro

~

I'

RS' 50

"'

~

lk

1M

10k
lOOk
FREQUENCY (Hz!

-50
-60

100

~
lk
FREQUENCY (Hz!

~HOI'I~

"""j..-

3D

>

l- I--~...J.....

40

20
10

o

10k

o 2 4 6 B 10 12 14 16 IB 20
VSUPPLY (VI

Distortion vs Frequency

Distortion vs Output Power
10

10
1

~AV'100

9

I-- VS' 14.4V

1

RL ;4

RLi.~1L
I
'I

!;;

..t;

V

/1/
,o

i

-

~

FEEDBACK RESISTORS

50

oS

-20
-3D

E~c~uois C~RRIENi IN

60
;;:

Output Power vs
Supply Voltage

=

Supply Current vs
Supply Voltage

-10

::: -40
::;

"

~

OUTPUT POWE R(WI

70

...-"
~

I

o 2 4 & B 10 12 14 16 IB

Supply Ripple Rejection
vs Frequency

.

~

I

o

14

12

..... V

1.-1'.0'10%

ft'~v

;;!

10
OUTPUT PQWER (WI

VS=lSV

1/ 1/ :..-

'"~
~

I/I--'ITHO ' 3%/

I

~

Open Loop Gain
vs Frequency

20
II
1&
14
12
10

10 f--

i:i
co

TA - AMBIENT TEMPERATURE (OCI

100
90
! 1070
";;: 60
'" 50
~
!:;
40
'"I 3D
c: 20
10
0
100

V~'2Jv- f-- l -

12

~

J

RL' 2

14

~

JCJHEJSIJ.

~
o

16

INFITTE iEATSIN~- I-

H~cJ HE~T SI.!:' t-

u

Power Dissipation vs
Output Power

Power Dissipation vs
Output Power

Device Dissipation vs
Ambient Temperature

-{L'4
f--

id.\. ~

1

2.5W

F""
o

2

4

o

10

& 8 10 12 14 1& 18 H

20

50 100

OUTPUT POWER (WI

VSUPPLY (VI

10
f-- AV'100

..

I-- VS' 14.4V
RL' 2

~

"'"~
....
"....

o

500 ,. 2k

5k 10k 20k

Output Swing vs
Supply Voltage

Distortion vs Frequency

I

zoo

FREQUENCY (Hz)

.."

~~

20
lB
1&
14
12
10
B

1 I
1 1 RL'~

j..l

RL '4-"

1'/

~

~

r,... V RL • 2_

f--

l.5W

o 2 4 6 B 10 12 14 16 IB 20
VSUPPLY (VI

20 50 100200 SOD lk 2k 5k 10k 20k
FREQUENCY (Hz!

TL/HI7145-4

1-23

II

c(

~

Typical Applications

:E

Single Amplifier

...I

.......
C')
co
C')

:E
...I

411

TLlH/714S-3

16W Bridge Amplifier
Vs
14.4V

Vs
14.4V

lD"F
SIGNAL

~

+

1M

INPUT.

ZZD

Z.Z

TL/H/714S-S

Component Layout
Single Amplifier

Vs = 20V
RL = 411

Heatsink from:
Staver Company
41 Saxon Ave.
P.O. Drawer H

Bay Shore, NY 11706
Tel: (516) 666-8000

TLlH/714S-6

1-24

.-------------------------------------------------------------------------;r

s::
w

~ Semiconductor
NatiOnal

CD
~

Corporation

LM384 5 Watt Audio Power Amplifier
General Description

Features

The LM384 is a power audio amplifier for consumer application. In order to hold system cost to a minimum, gain is
internally fixed at 34 dB. A unique input stage allows inputs
to be ground referenced. The output is automatically selfcentering to one half the supply voltage.

•
•
•
•
•
•
•
•

The output is short-circuit proof with internal thermal limiting. The package outline is standard dual-in-line. A copper
lead frame is used with the center three pins on either side
comprising a heat sink. This makes the device easy to use
in standard p-c layout.
Uses include simple phonograph amplifiers, intercoms, line
drivers, teaching machine outputs, alarms, ultrasonic drivers, TV sound systems, AM-FM radio, sound projector systems, etc. See AN-69 for circuit details.

Wide supply voltage range
Low quiescent power drain
Voltage gain fixed at 50
High peak current capability
Input referenced to GND
High input impedance
Low distortion
Quiescent output voltage is at one half of the supply
voltage
• Standard dual-in-line package

Schematic Diagram

.-----------------11------.....-<>

Vs (14)

.5

25h
25k

OUTPUT
(8)

BVPASS
.5

(1)

II
t--1....--Q+1N
(2)

150k

(3;4.5.10.11.12)
(7) GNO

GNO
TL/H17843-3

1-25

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
2aV
Peak Current
1.3A

Power Dissipation (See Notes 3 and 4)
Input Voltage
Storage Temperature
Operating Temperature
Lead Temperature (Soldering, 10 sec.)

1.67W
±0.5V
-65'C to + 150'C
O'Cto +700C
2600C

Electrical Characteristics (Note 1)
Symbol

Parameter

ZIN

Input Resistance

IBIAS

Bias Current

Av

Gain

POUT

Output Power

Conditions

Min

Typ

Max

150
Inputs Floating

kO

100

THD = 10%, RL = ao

40

50

5

5.5

Units

nA
60

VIV

25

mA

W

IQ

Quiescent Supply Current

VOUTQ

Quiescent Output Voltage

BW

Bandwidth

V+

Supply Voltage.

Isc

Short Circuit Current (Note 5)

1.3

A

PSRRRTO

Power Supply Rejection Ratio
(Note 2)

31

dB

a.5

POUT = 2W, RL = ao

11

V

450

kHz
26

12

THD
Total Harmonic Distortion
POUT = 4W, RL = ao
Note 1: V+ = 22V and TA = 2S'C operating with a Staver V7 heat sink for 30 seconds.
Note 2: Rejection ratio referred to the output with CBYPASS = Sp.F, freq = 120 Hz.
Note 3: The maximum junction temperature of the LM384 is ISO'C.
Note 4: The package is to be derated at IS'C/W junction to heat sink pins.
Note 5: Output is fully protected against a shorted speaker condition at all voltages up to 22V.

0.25

Heat Sink Dimensions
Staver "V7" Heat Sink
Staver Company
41 Saxon Ave.
P.O. Drawer H
Bay Shore, N.Y.
Tel: (SI6) 666-8000

h-1.6

"1
I \\\\\\\\
11./111"1.35

~v-;~
~1.5

TL/H17843-4

1·26

1.0

V

%

Typical Performance Characteristics

12.0

~
~
;:

::

iii
e;
~

u

~

Device Dissipation vs
Ambient Temperature

11I11~lII111Ls11IJ

10.0

90

U<'1JI

.........

B.O

~

'~

........

u

ST"'WEIIV'COPPIR"''''TSI''K]II''t,..~_

6.C

,i~O (III CO"~RJOll't BOARD l~·tw

'IS~!: ~~'~:,~~I~:I~ :~AI~O.R~~~
I~

USQ

4.0
2.0

"

w-

=
~

",.

CQ'PfAfOILPC BOARD

t-.

~

"~

"""1

UUt" il"CW

:=

Thermal Resistance vs
Square Inches

Bo

40

\

10

:s
~

z

_t

6'

~

0

u

\

SO

">..........

40

~

r-.

~
~

r- I'-

20

30 40

SO

60

10

111111

Output Voltage Gain vs
Frequency

30

RLI)ll

~;~:EH: ,~,!.IJ~IAT SI~K

~
z

~
~

~":>

20

5

10

~

III
II

~

0.3

14W

~

1T I

;;;
u

0.2

2W
lW
0.1

~ Ve ,-22"111111

~

S~A;E~ "v1!!W1AT SINK

00
0-

10k

1M

lOOk

100

10M

2.4
2.2 f-2.0
24V
I.B
1.6 ~_32V""""
I".
1.4
~~,
1.2 !-IBV
1'>0 .....
1.0
16V'
0.8
IV
Oil
LEYEL_
0.6
0.4
0.2 ~STAVER "V1" HEATISINK

z
0
;:

::

iii
;;;
w

u

~

o
18

22

SUPPLY VOLTAGE IVI

26

-.>-

.,'

Olr.

I

12BV

h

OUTPUT POWER IWI

C>-~

, / l!!v
24V
22V
20V
lav

no<

~

17~3" oIST. LEVEL

I

~~ r-lO%IOIST.
II
I
LEVEL_
IsrAVEJ "vl,,, JEA+SI~K

1

3D

lOOk

Device Dissipation vs
Output Power-811 Load
6

~

!:

10k

1k

FREQUENCY IHd

Device Dissipation vs
Output Power-1611 Load

l..oo-

10k

I'

Total Harmonic Distortion
vs Freaue ncy

FREOUENCY IH.I

Power Supply Current vs
Supply Voltage

14

i3

~
;l
g

lk

10

10

100

§

o

10

OUTPUT POWER IWI

9

D.'

Po =2W

w

1.0

~ : IN~I ;I~I;

~

FREQUENCY IH,)

IIII

I

RL -B+H
111-H+-11I--!-+-H-1-HfI

0.1

o41/IF

I. 1/

SQUARE INCHES OF COPPER FOIL
p.e. BOARD HEATSINK

40

C-.

V

10

Total Harmonie Distortion
vs Output Power
Vee - 26V

""
-

~

!"F

BO

fA - AMBIENT TEMPERATURE (CI

10

20

I

10~F

o '-

3D

10

30

Supply Decoupling vs
Free uenc~

2

3

4

5

6

1

a

9 10

OUTPUT POWER (WI

Device Dissipation vs
Output Power-411 Load

OUTPUT POWER IWI

TL/HI7B43-S

1-27

II

~

~
:::E

.----------------------------------------------------------------------------,
Block and Connection Diagrams

...I

Dual-In-Llne Package

BYPASS

BYPASS 1

14 Vs

NON·INVERTING INPUT 2

13 Nt

Vs

12)
11 GNO'

Your

10
9

INVERTING INPUT 6
GNO

GNO 1

GNO

Nt

B Your

TL/H/7843-1

"'Heatsink Pins

TL/HI7843-2

Top View
Order Number LM384N
See NS Package Number N14A

Typical Applications
Typical 5W Amplifier
+22V

V,N

lDk>Ot-----.::.t

an

TL/HI7843-6

Bridge Amplifier

TL/H17843-7

1-28

~------------------------------------------------------~,

Typical Applications

s::

(Continued)

Co)

CD

,j:>.

Intercom

V.

D.lpF

Q

Co

'::" 5O.F
8

LISTEN

5,.

LISTEN

I TALK
I
MASTER

L
I __________________________
-

I
I
I
I
I
I

.~

"

~

• For stability with
high current loads

TL/H/7843-8

Phase Shift OSCillator
Vs

TL/HI7843-9

II

1-29

~

;
....I

~NatiOnal
semiconductor
Corporation

LM386 Low Voltage Audio Power Amplifier
General Description
•
•
•
•
•

The LM386 is a power amplifier designed for use in low
voltage consumer applications. The gain is internally set to
20 to keep external part count low, but the addition of an
external resistor and capacitor between pins 1 and 8 will
increase the gain to any value up to 200.
The inputs are ground referenced while the output is automatically biased to one half the supply voltage. The quiescent power drain is only 24 milliwatts when operating from a
6 volt supply, making the LM386 ideal for battery operation.

Applications
•
•
•
•
•
•
•
•

Features
•
•
•
•

Battery operation
Minimum external parts
Wide supply voltage range
Low quiescent current drain

Voltage gains from 20 to 200
Ground referenced input
Self-centering output quiescent voltage
Low distortion
Eight pin dual-in-line package

4V-12V or 5V-18V
4 mA

AM-FM radio amplifiers
Portable tape player amplifiers
Intercoms
TV sound systems
Line drivers
Ultrasonic drivers
Small servo drivers
Power converters

Equivalent Schematic and Connection Diagrams
Dual-In-Llne and Small Outline
Packages

r-------------------------~----_1~v,

GAIN

GAIN

....W'lr-.....W'lr-....----..111'>/Ir----+----~~ VOUT

-INPUT - -.......----F....

BYPASS

+INPUT

Vs

GND

-INPUT

VOUT

TUH/6976-2

Top View

L-_4--~----------~--'_~~----_4------'_OGND

TL/H/6976-1

Order Number LM386M-1,
LM386N-1, LM386N-3 or LM386N-4
See NS Package Number
M08Aor N08E

Typical Applications
Amplifier with Gain = 20
Minimum Parts

Amplifier with Gain = 200

v,.

TUH/6976-4
TUH/6976-3

'Required for LM386N·4 only.

1-30

'Required for LM386N-4 only.

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (LM386N-1 , -3, LM386M-1)
15V
Supply Voltage (LM386N-4)
Package Dissipation (Note 1) (LM386N-4)
Input Voltage
Storage Temperature
Operating Temperature

+ 150'C
Soldering Information
Dual-In-Line Package
Soldering (10 sec)
+ 260'C
Small Outline Package
Vapor Phase (60 sec)
+215'C
Infrared (15 sec)
+ 220'C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

22V
1.25W
±O.4V
- 65'C to + 150'C

Electrical Characteristics
Parameter

Junction Temperature

O'Cto +70'C
TA = 25'C

Conditions

Operating Supply Voltage (Vs)
LM386N-1, -3, LM386M-1
LM386N-4

Typ

4
5

Quiescent Current (10)

Vs = 6V, V,N = 0

Output Power (POUT)
LM386N-1, LM386M-1
LM386N-3
LM386N-4

Vs = 6V, RL = 80., THD = 10%
Vs = 9V, RL = 80., THD = 10%
Vs = 16V, RL = 320., THD = 10%

Voltage Gain (Av)

Min

4

Max

Units

12
18

V
V

8

mA

325
700
1000

mW
mW
mW

Vs = 6V, f = 1 kHz
10,..F from Pin 1 to 8

26
46

dB
dB

250
500
700

Bandwidth (BW)

Vs = 6V, Pins 1 and 8 Open

300

kHz

Total Harmonic Distortion (THD)

Vs = 6V, RL = 80., POUT = 125 mW
f = 1 kHz, Pins 1 and 8 Open

0.2

%

Power Supply Rejection Ratio (PSRR)

Vs = 6V, f = 1 kHz, CBYPASS = 10,..F
Pins 1 and 8 Open, Referred to Output

50

dB

50
250

kn
nA

Input Resistance (R'N)
Input Bias Current (IBIAS)

Vs = 6V, Pins 2 and 3 Open

Note 1: For operation in ambient temperatures above 25°C, the device must be derated based on a 150"C maximum junction temperature and 1) a thermal
resistance of 80'C/W junction to ambient for the dual·in·line package and 2) a thermal resistance of 170'C/W for the small outline package.

Application Hints
GAIN CONTROL
To make the LM386 a more versatile amplifier, two pins (1
and 8) are provided for gain control. With pins 1 and 8 open
the 1.35 kn resistor sets the gain at 20 (26 dB). If a capacitor is put from pin 1 to 8, bypassing the 1.35 kn resistor, the
gain will go up to 200 (46 dB). If a resistor is placed in series
with the capaCitor, the gain can be set to any value from 20
to 200. Gain control can also be done by capacitively coupiing a resistor (or FEn from pin 1 to ground.
Additional external components can be placed in parallel
with the internal feedback resistors to tailor the gain and
frequency response for individual applications. For example,
we can compensate poor speaker bass response by frequency shaping the feedback path. This is done with a series RC from pin 1 to 5 (paralleling the internal 15 kn resistor). For 6 dB effective bass boost: R "" 15 kn, the lowest
value for good stable operation is R = 10 kn if pin 8 is
open. If pins 1 and 8 are bypassed then R as low as 2 kn
can be used. This restriction is because the amplifier is only
compensated for closed-loop gains greater than 9.

INPUT BIASING
The schematic shows that both inputs are biased to ground
with a 50 kn resistor. The base current of the input transistors is about 250 nA, so the inputs are at about 12.5 mV
when left open. If the dc source resistance driving the
LM386 is higher than 250 kn it will contribute very little
additional offset (about 2.5 mV at the input, 50 mV at the
output). If the dc source resistance is less than 10 kn, then
shorting the unused input to ground will keep the offset low
(about 2.5 mV at the input, 50 mV at the output). For dc
source resistances between these values we can eliminate
excess offset by putting a resistor from the unused input to
ground, equal in value to the dc source resistance. Of
course all offset problems are eliminated if the input is capacitively coupled.
When using the LM386 with higher gains (bypassing the
1.35 kn resistor between pins 1 and 8) it is necessary to
bypass the unused input, preventing degradation of gain
and possible instabilities. This is done with a 0.1 ,..F capacitor or a short to ground depending on the dc source resistance on the driven input.

1-31

II

Typical Performance Characteristics
Power Supply Rejection Ratio
(Referred to the Output)
vs Frequency

Quiescent Supply Current
vs Supply Voltage
60

-

-

I-

i-

:l

;;;

'"~

......
~

~

>-

~

~

lO

~

.0

2!

~. ~ ~
"

0
10

11

.0

12

.00

SUPPLY VOLTAGE (VOLTS)

'z~"
'"

~

111111111

l!~I!II!

lO

'.2

--

t-- t---

i!!

0.6

~

'0
0
.00

~

.k

.Ok

lOOk

20

50 100 200 SOO lk 21e

~

ilic;
u

~

0.'
0.2

vs! ....

12V- t---

V

1.0

0.6

•.6

/

J--

~ +D.'

I

VS'9V
Vs =6V

i

I

ilic;

...i

l%THO
Ir-t' LEVEL

~

u

~'O%THO
LEVEL

0.2

O.l

0.'

~

0.5

-I::;

'.2

J

1.0
0.8
0.6
0.'
0.2

I

OUTPUT POWER !WI

~
~ 1.4

0

1/

ru

,...

~ 0.8
I
I

Vs"12V

ltv I-y~]
V,, 6V.., J:.;'i;i'THO
LEVEL

I

Device Dissipation vs Output
Power-1611 Load
1.0

I I
IJ

1.8

I

0.8

POWER OUT (WATTS)

Device Dissipation vs Output
Power-a11 Load
2.0

1.2

5k 1011 201c

FREQUENCY (Hz)

Device Dissipation vs Output
Power-411 Load
~
z
c 1.4
;::

~.otO='ttmmo.to.:t;ttWllot. 1:t:tJ1•.0

o

.M

2.0

•.6

~~

V

1"--

0.2

FREOUENCY (Hzl

1.8

2UB (e u '" OJ

0.8

D.'

12

:

•. 0

~

20

>

11

:~ :~! ttIt--t-H-tttttt-+-tlltittfl

u

~c;

1\

10

Distortion vs Output Power

POUT = 125mW
=

-

• I--

, •• kH,tttt--t-tt-ttltlt-tiHtittil

...

Av

~ ......

9

I I.

Rc' 81!,

Ii:

'.6

~ V" ~ r-

.0 r-rr~m-il~mr-rTInTIm

Vs =6V

1.8

~

L

SUPPLY VOLTAGE (VOL lS)

Distortion vs Frequency
~
~

~

.0

~

2.0

ell ~I~~I F

50

;;;

lOOk

'Ok

'k

FREQUENCY (Hz)

Voltage Gain vs Frequency
60

.....::

~

'"w

9

Rc;.-~ ~

6

.0

20

Peak-to-Peak Output Voltage
Swing vs Supply Voltage
.0

:;

50

~

;;

z

c

~ D.'

0.0

c;
~

u

10% THD

LEVEL

trr

1.0 0.2 0.3 0.4 0.5 0.6 0.1 0.8 0.9 1.0
OUTPUT POWER (WI

~

0.2

o

0.2 0.4 0.5 O.B 1.0 1.2 1.4 1.6 1.8 2.0

OUTPUT POWER (WI
TLlH/6976-5

1-32

Typical Applications

(Continued)

Amplifier with Gain = 50

Low Distortion Power Wienbridge Oscillator
390

V,.

ELDEMA

Vo

CF·5-Z158

T

O.05"F· ':'

TUH/6976-6

TUH/6976-7

Amplifier with Bass Boost

Square Wave Oscillator

Vo

lk
f= 1 kHz

TL/H/6976-B

"Required for LM386N-4 only.
TUH/6976-9

II

Frequency Response with Bass Boost
27
26

.

iii

25

~

24

c;:

23

...'"
...'"'"

22
21

'r

I
I

J

\.
\

\
\.

....I

co
>

20
19

......

18

17
20

50 100200 500 Ik 2k

5k 10k 20k

FREDUENCY (Hz)
TUH/6976-10

1-33

Typical Applications

(Continued)

AM Radio Power Amplifier
Cc

Vso-",--...

FROM......j
OETECTOR,

TLfH16976-11

Note 1: Twist supply lead and supply ground very tightly.

Note 4: R1G1 band limils input signals.

Note 2: Twist speaker lead and ground very lightly.

Note 5: All components must be spaced very close to IG.

Note 3: Ferrite bead is Ferroxcube KS-001-00113B with 3 turns of wire.

1-34

NatiOnal

~ Semiconductor
Corporation

LM387/LM387 A Low Noise Dual Preamplifier
General Description

Features

The LM387 is a dual preamplifier for the amplification of low
level signals in applications requiring optimum noise performance. Each of the two amplifiers is completely independent, with an internal power supply decoupler-regulator, providing 110 dB supply rejection and 60 dB channel separation. Other outstanding features include high gain (104 dB),
large output voltage swing (Vee - 2V)p-p, and wide power
bandwidth (75 kHz, 20 Vp-p). The LM387A is a selected
version of the LM387 that has lower noise in a NAB tape
circuit, and can operate on a larger supply voltage. The
LM387 operates from a single supply across the wide range
of 9V to 30V, the LM387A operates on a supply of 9V to

•
•
•
•
•
•
•
•
•
•
•

40V.

1.0 /-LV total input noise
Low noise
104 dB open loop
High gain
Single supply operation
9 to 30V
Wide supply range LM387
LM387A
9 to 40V
110 dB
Power supply rejection
Large output voltage swing (Vee - 2V)p-p
Wide bandwidth 15 MHz unity gain
Power bandwidth 75 kHz, 20 Vp-p
Internally compensated
Short circuit protected
Performance similar to LM381

The amplifiers are internally compensated for gains greater
than 10. The LN387, LM387A is available in an 8-lead dualin-line package. The LM387, LM387A is biased like the
LM381. See AN-64 and AN-104.

Schematic and Connection Diagrams
Dual-In-Line Package

1------

I

I "'

Iwo~'~~~-L

I

____~

+INIII

+IN121

-IN

-IN III

GNO

OUTPUT 111

I
I
I
I

'------+---t-o 14,5)

TLlH17845-2

Top View
Order Number LM387N or LM387AN
See NS Package Number N08E

I

I
IL___

QUTPUT{ZI

~

__ _

II

TLlH/7845-1

Typical Applications
14V

14V

TL/H17845-3

TL1H/7845-4

FIGURE 1. Flat Gain Circuit (Av = 1000)

FIGURE 2. NAB Tape Circuit

1-35

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
LM387
+30V
LM387A
+40V

Electrical Characteristics TA =

Power Dissipation (Note 1)
Operating Temperature Range

1.5W

Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)

25'C, Vee = 14V, unless otherwise stated

Parameter

Conditions

Voltage Gain

Open Loop, f = 100 Hz

Supply Current

LM387, Vee 9V-30V, RL = 00
LM387A, Vee 9V-40V, RL = 00

Input Resistance
Positive Input
Negative Input

Typ

Min

Max

VIV

10
10

mA
rnA

100
200

kO
kO

Input Current
Negative Input

0.5

Output Resistance

Open Loop

Output Current

Source
Sink

Output Voltage Swing

Peak-to-Peak

Unity Gain Bandwidth

Maximum Input Voltage

Linear Operation
f = 1 kHz

3.1

,..A

150

0

8
2

rnA
rnA

Vee- 2
15

MHz

75

kHz

20 Vp-p (Vee> 24V),
THO"; 1%

Supply Rejection Ratio
Input Referred

Units

160,000

50

Large Signal Frequency
Response

O'Cto +70'C
- 65'C to + 150'C
260'C

V

300
110
40

mVrms
dB

Channel Separation

f = 1 kHz

Total Harmonic Distortion

60 dB Gain, f = 1 kHz

0.1

60
0.5

dB
%

Total Equivalent Input
Noise (Flat Gain Cricuit)

10 Hz-10,000 Hz
LM387 Figure 1

1.0

1.2

,..Vrms

Output Noise NAB Tape
Playback Circuit Gain of 37 dB

Unweighted
LM387A Figure 2

400

700

,..Vrms

Note 1: For operation in ambient temperatures above 2S'C, the device must be derated based on a 150°C maximum junction temperature and a thermal resistance
of 80'C/W junction to ambient.

Typical Applications (Continued)
Two-Pole Fast Turn'()N NAB Tape Preamplifier

Frequency Response of NAB
Circuit of Figure 2

24V

f'r+ ".~
LM387

'''."

I

65
&0
55
50

(4,5)

~

+

2D.F "';'1--

T

20

~

&0 1&0 2&0 510 Ik 211 5k 10k 20k
FREQUENCY (Hz)

11k
.AA

24D

"

I.....

30
25
20

II

240

"-

35

D.Di8i .F

.A~k

"

45
40

""v(
11k

NAB PLAYBACK

TL/HI7B45-6

Uk.

+
2D.Fi

~
TL/H17845-5

1-36

Typical Performance Characteristics
Gain and Phase Response

Vccvslcc

13
12

II

:<
S

10

.ll

9

~

i"""

z

~

•
1
&
10 15

5

0

20

25

35

3D

120
110
100
'0
80
10
60
50
40
3D
20
10
0

40

:::-".
'\.

I-

'" :"

"

I

10

100

I

_

I--

80

l-

10

r--

sIn

150
~ 1&5
180
10k O.IM 1M IBM

w

~
~

S!

~
""
~

"~

20

<1%

-z

8

\

&
4

\

2
0
lltHz 10kHz 10DltHz

"

~
~

5~F

I

!..OOO

"

50
40

'\

100

Ik

10k

lOOk

1M

0.15

c-- _Av"60d8

1000

0.10

Vee" 12V

0.05

:

10M

10

FREQUENCY 1Hz!

100

0.50
Vee = 24V

0.45

,c,~s:·m

VOUT " 5 Vtms

0.40

~

10

~

"

~

§

~

1111

[\,

IIIIIIIII

I

....

.i.

INVERTING

§! 0.35
~ O.lO

ii

~

0.25



50100200500151 2k
FREQUENCV (Hd

10 Frequency

100

Av =40dB

I I I

10

1kHz 10kHz 100kHz 1 MHz

V

. / r'> 1/
~
L J.....-1": I,...-

fREQUENCY (Hd

NOise Voltage vs
Frequency

En~IV~LENIT

020

60
10

100M

II

I I I

NAJ

20
"

10M

_~:C;;~'~$

30

Ay

""1M

0.40 - NON·INVERTING
0.15
I
0.30

025

10

\

Distortion vs Frequency
Non-Inverting Amplifier

0.50

0.45

&0

0ISTORTI~N-

18
1&
14
12
10

FREQUENCV (H.I

10

~~t1$1
=

,,"

~

Channel Separation

lA---h.1
LJ IJ

90

Ik

100

135

'"

Large Signal Frequency
Response

FREQUENCY 1Hz)

PSRR vs Frequency
(Input Referred)

110

15
3D
45
&0
15
90
IDS
120

-

"- ~~IN
PHASE

SUPPLY VOLTAGE (VI

120

"-

22

f--

~Od~:::;;

II

~t

0.1
10

100

Ik

FREOUENCV (Hd

10k

10

100

Ik

FREOUENCV (Hd

10k

20

50100200 500 1k 21t

5k 10k20k

FREQUENCY (Hz)

TLlH17845-7

1-37

a

Typical Applications

(Continued)

Inverting Amplifier Ultra-Low Distortion

Typical Magnetic Phono Preamplifier
24Y

24Y

14,51

Av" 10

lOOk

15k

39.

TL/HI7B45-B

561t

+
T47/.1F

TL/H/7B45-9

1-38

r

s::

w

~ Semiconductor
NatiOnal

CD
CD

Corporation

LM388 1.5 Watt Audio Power Amplifier
General Description
The LM388 is an audio amplifier designed for use in medium
power consumer applications. The gain is internally set to
20 to keep external part count low, but the addition of an
external resistor and capacitor between pins 2 and 6 will
increase the gain to any value up to 200.
The inputs are ground referenced while the output is automatically biased to one half the supply voltage.

Features
•
•
•
•
•

Minimum external parts
Wide supply voltage range
Excellent supply rejection
Ground referenced input
Self-centering output quiescent voltage

•
•
•
•

Variable voltage gain
Low distortion
Fourteen pin dual-in-line package
Low voltage operation, 4V

Applications
•
•
•
•
•
•
•
•
•

AM-FM radio amplifiers
Portable tape player amplifiers
Intercoms
TV sound systems
Lamp drivers
Line drivers
Ultrasonic drivers
Small servo drivers
Power converters

Equivalent Schematic and Connection Diagrams
Dual-In-Line Package

14

r---------------------------------~_oVs
14 Vs

BVPASS

15k

GAIN

.--_-+:.:.13

vou,

:1

GND

t-"",.,......'V\/Ir+-----"IM,..-----f-----.....-o

13

10

Vou,

9

GAIN
-INPUT

BOOTSTRAP

+INPUT

-INPUT

TL/H/7846-2

Top View
3.4.5.
10,11,12

GND
TLlH17846-1

1-39

Order Number LM388N-1
See NS Package Number N14A

II

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

150'C

Lead Temperature (Soldering. 10 sec.)

260'C

25'C, (Figure 1)

Parameter

Conditions

Typ

Min

Vs

Operating Supply Voltage
LM388

IQ

Quiescent Current
LM388

VIN = 0
Vs = 12V

POUT

Output Power (Note 2)
LM388N-1

R1 = R2 = 180n, THD = 10%
Vs = 12V, RL = 8n
Vs = 6V, RL = 4n

Voltage Gain

Vs = 12V,f = 1 kHz
10 /-tFfrom Pins 2 to 6

Av

O'Cto +70'C

Junction Temperature

8.3W

Electrical Characteristics T A =
Symbol

-65'Cto + 150'C

Operating Temperature

15V

Package Dissipation 14-Pin DIP (Note 1)

±O.4V

Input Voltage
Storage Temperature

Max

Units

12

V

23

mA

4
16

1.5
0.6

2.2
0.8

23

26
46

W
W
30

dB
dB

BW

Bandwidth

Vs = 12V, Pins 2 and 6 Open

300

THD

Total Harmonic Distortion

Vs = 12V, RL = 8n, POUT = 500 mW,
f = 1 kHz, Pins 2 and 6 Open

0.1

PSRR

Power Supply Rejection Ratio
(Note 3)

Vs = 12V, f = 1 kHz, CSYPASS = 10 /-tF,
Pins 2 and 6 Open, Referred to Output

50

dB

RIN

Input Resistance

10

50

kn

Input Bias Current
Vs = 12V, Pins 7 and 8 Open
ISlAS
Nole 1: Pins 3. 4. 5. 10.11.12 at 25'C. Derate at 15'C/Wabove 25'C case.
Nole 2: The amplifier should be in high gain for full swing on higher supplies due to input voltage limitations.
Nole 3: If load and bypass capacitor are returned to Ys (Figure 2), rather than ground (Figure 1), PSRR is typically 30 dB.

250

nA

kHz
1

%

Typical Performance Characteristics
Maximum Device Dissipation vs
Ambient Temperature
10

~

is

::'"

~
~

9
8
7
6
5

STAVER V·}

.....

Z

1
0

40

i

30

...

r"

IIN.Sn.

~

15

em

+rr-

3S0CJW
, _ ... CIW
5D"C/W
8S0C/W
COPPER FOIL (P.C.BOARD)

FREE AIR

c

'"is

.!l

4 COPPER WJNGS- COjEi JDIL

3

Power Supply Rejection Ratio
(Referred to the Output) vs
Frequency

!~IJl~~
~I

;;;

INFINITEHEAT$INK

I I
I I
I I

60

50

I I I

u

~

Quiescent Supply Current vs
Supply Voltage

t-t;t.i1.S~jE

~

~

E
~

V
1/

IO

10 20 30 40 50 60 70 80 DO 100

I

V-

t-

TA - AMBIENT TEMPERATURE ('CI
Note: 2 oz. copper foil, single·sided PC bOlrd.

i.

~

20

0

50
40

II

M

30

;/

20

V

10
0

0

4

8

12

SUPPLY VOLTAGE (VI

16

20

10

100

/

JI

'I'"

v = 26dB

O.5j.1

1k

10k

lOOk

FREQUENCY IHzl
TLlH/7846-5

1-40

Typical Performance Characteristics

(Continued)

Voltage Gain vs Frequency

10

Distortion vs Frequency

60

.'"
;;

:iw
m

,.~

Vs =tZV
RL :30
PD .. O.5W

I11I

50

CZ,8

40

= 10~F

ll!~~ .!

30

1\

0.6
0.4

20

02
0.1

10

o
10k

1M

20

FREQUENCY (Hz!

Distortion vs Output Power

5

,;'

ArT- - -

50100200 '00 It 2k

5k 10k 20k

FREQUENCY (Hzl

Device Dissipation vs Output
Power-4n Load

."

!-1kHz

>=

Device Dissipation vs

~

Cz,s",g

100THD
LEVEL

t;
is

~

lOOk

/
-200

2.5

0f-u""t....p,.u_t_P..:,°rw..:.e:.;r-,.S-,n;,,;L,..o:.;a.;.;d-,

Z.D

t--If----i--f--+--i

VB = 12V
RL -8n

§!
~

..

" Av

........ ""'t-'I'"

0.04

100

SUPPLY VDLTAGE (VI

u

-

0.06

o '------'_-i.._-'-_--'-_--'
o
12
16
2D

10

II

......

z

"
~

3%THD \
LEVEL

1.0

/t'V ~~r2V

'"'"
I;
'"....
~

s"9V

H'"
Vs "'6V

0.1
0.01

0.1

1.0

1.5 I--I--+--+-+-~

iii

~

1.0

t-::~~"-:I--+-

~

D.5

L...O-.L~'~~

10

POWER OUTPUT (W)

OUTPUT POWER (W)

OUTPUT POWER (WI

Device Dissipation vs
Output Power-16n Load
2.5

i

Z.O

z

i"iii
is

w
u

~

1.5

1.0

0.5

o

~zv

",THD

i

~~
LEVEL
0% TH01LEVEL
Vs-6V

o

0.5

I.D

1.5

Z.O

z.&

DUTPUT POWER (W)
TL/H17846-6

Application Hints
output dc level may shift due to the additional dc gain. Gain
control can also be done by capacitively coupling a resistor
(or FET) from pin 6 to ground, as in Figure 7.

GAIN CONTROL
To make the LM388 a more versatile amplifier, two pins (2
and 6) are provided for gain control. With pins 2 and 6 open,
the 1.35 kn resistor sets the gain at 20 (26 dB). If a capacitor is put from pins 2 to 6, bypassing the 1.35 kn resistor,
the gain will go up to 200 (46 dB). If a resistor is placed in
series with the capacitor, the gain can be set to any value
from 20 to 200. A low frequency pole in the gain response is
caused by the capacitor working against the external resistor in series with the 150n internal resistor. If the capacitor
is eliminated and a resistor connects pins 2 to 6 then the

Additional external components can be placed in parallel
with the internal feedback resistors to tailor the gain and
frequency response for individual applications. For example,
we can compensate poor speaker bass response by frequency shaping the feedback path. This is done with a series RC from pin 6 to 13 (paralleling the internal 15 kn resistor). For 6 dB effective bass boost: R "" 15 kn, the lowest
value for good stable operation is R = 10 kn if pin 2

1-41

II

~
~
C")

:::!i

....I

r--------------------------------------------------------------------------,
Application Hints (Continued)
is open. If pins 2 and 6 are bypassed then R as low as 2 kO
can be used. This restriction is because the amplifier is only
compensated for closed-loop gains greater than 9 VIV.

beta is the value required for the current in Rl and R2:
(Rl

INPUT BIASING

+ R2)

=

130 (Vs/2)

- VSE
lOMAX

Good design values are VBE = 0.7V and 130 = 100.
Example: 1 watt into 80 load with Vs = 12V.

The schematic shows that both inputs are biased to ground
with a 50 kO resistor. The base current of the input transistors is about 250 nA, so the inputs are at about 12.5 mV
when left open. If the dc source resistance driving the
LM388 is higher than 250 kO it will contribute very little
additional offset (about 2.5 mV at the input, 50 mV at the
output). If the dc source resistance is less than 10 kO, then
shorting the unused input to ground will keep the offset low
(about 2.5 mV at the input, 50 mV at the output). For dc
source resistances between these values we can eliminate
excess offset by putting a resistor from the unused input to
ground, equal in value to the dc source resistance. Of
course all offset problems are eliminated if the input is capacitively coupled.
When using the LM388 with higher gains (bypassing the
1.35 kO resistor between pins 2 and 6) it is necessary to
bypass the unused input, preventing degradation of gain
and possible instabilities. This is done with a 0.1 JLF capacitor or a short to ground depending on the dc source resistance on the driven input.

lOMAX =
(Rl

+ R2)

PO
-- =
~
RL

500 rnA

= 100 (12/2) - 0.7) = 10600

0.5

To keep the current in R2 constant during positive swing
capacitor Cs is added. As the output swings positive Cs lifts
Rl and R2 above the supply, maintaining a constant voltage
across R2. To minimize the value of Cs, Rl = R2. The pole
due to Cs and Rl and R2 is usually set equal to the pole
due to the output coupling capacitor and the load. This
gives:
4Cc
Cc
Cs"'-"'130 25
Example: for 100 Hz pole and RL = 80; Cc = 200 JLF and
CB = 8 JLF, if Rl is made a diode and R2 increased to give
the same current, CB can be decreased by about a factor of
4, as in Figure 4.
For reduced component count the load can replace Rl. The
value of (Rl + R2) is the same, so R2 is increased. Now Cs
is both the coupling and the bootstrapping capacitor (see
Figure 2).

BOOTSTRAPPING
The base of the output transistor of the LM388 is brought
out to pin 9 for Bootstrapping. The output stage of the amplifier during positive swing is shown in Figure 3 with its
external circuitry.
R 1 + R2 set the amount of base current available to the
output transistor. The maximum output current divided by

Typical Applications
vs

vs

Rl
510

Tl/HI7846-3

Tl/H17846-4

FIGURE 1. Load Returned to Ground
(Amplifier with Gain = 20)

FIGURE 2. Load Returned to Vs
(Amplifier with Gain = 20)

1-42

Typical Applications

(Continued)

, - - - - -...-ovs
RI

BVPASS

14

-=dh

I

-

1

7

R2

TUH/7846-7

FIGURE 3

TL/H17846-8

FIGURE 4. Ampifier with Gain = 200 and Minimum CB
Vs

'!"O.I.F

210

210

+
22"F

22"F

210

Vs

~

6V

Vs ~ 12V

+

O.o5.F

210

TL/H17846-9

RL

~

4n

Po

~

1.0W

RL

~

an

Po

~

4W

FIGURE 5. Bridge Amp
Vs

II

510
21
26

25

;;;
3

24

~

23

~

22

~

21

>

20

1'\
I

II

,

1\

r-...

19
18

11
20

50 100200 500 lk 2k

5k 10k 20k

FREQUENCY (Hz)

TL/H17846-11

FIGURE 6b. Frequency Response
with Bass Boost
TL/H17846-10

FIGURE 6a. Amplifier with Bass Boost

1-43

co
co

;

Typical Applications (Continued)

...I

vso-~t--e-------,

BYPASS

dh

~

II

2.7

TALK

TALK

.....---------,t----o LISTEN

REMOTE

TL/H/7846-12

FIGURE 7. Intercom

TL/HI7846-13

FIGURE 8. AM Radio Power Amplifier
Note I: Twist supply lead and supply ground very tightly.

Note 4: RICI band limits input signals.

Note 2: Twist speaker lead and ground very tightly.

Note 5: All components must be spaced very close to IC.

Note 3: Ferrite bead is Ferroxcube KS-OOI -001 13B with 3 turns of wire.

1-44

NatiOnal

~ Semiconductor
Corporation

LM389 Low Voltage Audio Power Amplifier
with NPN Transistor Array
• Low quiescent current drain
• Voltage gains from 20 to 200
• Ground referenced input
• Self-centering output quiescent voltage
• Low distortion
Transistors
• Operation from 1 ",A to 25 mA
• Frequency range from DC to 100 MHz
• Excellent matching

General Description
The LM3B9 is an array of three NPN transistors on the same
substrate with an audio power amplifier similar to the
LM3B6.
The amplifier inputs are ground referenced while the output
is automatically biased to one half the supply voltage. The
gain is internally set at 20 to minimize external parts, but the
addition of an external resistor and capacitor between pins
4 and 12 will increase the gain to any value up to 200.
The three transistors have high gain and excellent matching
characteristics. They are well suited to a wide variety of applications in DC through VHF systems.

Applications
•
•
•
•
•
•
•

Features
Amplifier
• Battery operation
• Minimum external parts
• Wide supply voltage range

AM-FM radios
Portable tape recorders
Intercoms
Toys and games
Walkie-talkies
Portable phonographs
Power converters

Equivalent Schematic and Connection Diagrams
r--------------------.----~~~

-INPUT

TL/HI7B47-1

Dual·ln·Line Package
SUB
~

~

•

~

u

~

0

You,

VI

IYrASS

GAIN

_IN

Cl

~

~

H

It

£I

E2

Order Number LM389N
See NS Package Number N18A

1-45

TLlH17847 -2

II

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

Lead Temperature (Soldering, to sec.)

15V

260'C

Collector to Emitter Voltage, VCEO

12V

Collector to Base Voltage, VCSO

15V

Package Dissipation (Note 1)

I.S9W

Collector to Substrate Voltage, VCIO
(Note 2)

Input Voltage

±OAV

Collector Current, Ic

25mA

Emitter Current, IE

25mA

Storage Temperature

-65'C to + 150'C

Operating Temperature

O'Cto +70'C

Junction Temperature

Symbol

5mA

Base Current, Is

150'C

Electrical Characteristics TA =

15V

Power Dissipation (Each Transistor) T A ,;; + 70'C

150mW

25'C

Parameter

Conditions

Min

Typ

Max

Units

12

V

6

12

mA

AMPLIFIER
Vs

Operating Supply Voltage

IQ

Quiescent Current

4

POUT

Output Power (Note 3)

Av

Voltage Gain

Vs = 6V, I = 1 kHz
10 JLF Irom Pins 4 to 12

Vs = 6V, VIN = OV
THD = 10%

Vs = 6V, RL = sn
Vs = 9V,RL = 16n

250

325
500

23

26
46

BW

Bandwidth

Vs = 6V, Pins 4 and 12 Open

250

THD

Total Harmonic Distortion

Vs = 6V, RL = sn, POUT = 125 mW,
I = 1 kHz, Pins 4 and 12 Open

0.2

PSRR

Power Supply Rejection Ratio

Vs = 6V, 1= 1 kHz, CSYPASS = 10 JLF,
Pins 4 and 12 Open, Relerred to Output

RIN

Input Resistance

ISlAS

Input Bias Current

Vs = 6V, Pins 5 and 16 Open

VCEO

Collector to Emitter
Breakdown Voltage

Ic = 1 mA, Is = 0

VCSO

Collector to Base
Breakdown Voltage

Ic = 10 JLA, IE = 0

VCIO

Collector to Substrate
Breakdown Voltage

Ic = 10 JLA, IE = Is = 0

VESO

Emitter to Base
Breakdown Voltage

IE = 10 JLA, Ic = 0

HFE

Static Forward Current
Transler Ratio (Static Beta)

Ic=IOJLA
Ic = 1 mA
Ic=IOmA

30
10

mW
mW
30

dB
dB
kHz

3.0

%

50

dB

50

kn

250

nA

12

20

V

15

40

V

15

40

V

604

7.1

100

100
275
275

TRANSISTORS

7.S

V

hoe

Open-Circuit Output Admittance

Ic = 1 mA, VCE = 5V, 1= 1.0 kHz

20

VSE

Base to Emitter Voltage

IE = 1 mA

0.7

0.S5

V

IVSE1-VSE21

Base to Emitter Voltage Offset

IE = 1 mA

1

5

mV

VCESAT

Collector to Emitter
Saturation Voltage

Ic = 10 mA, Is = 1 mA

0.15

0.5

V

CES

Emitter to Base Capacitance

VES = 3V

1.5

pF

CCS

Collector to Base Capacitance

VCS = 3V

2

pF

CCI

Collector to Substrate
Capacitance

VCI = 3V

3.5

pF

hIe

High Frequency Current Gain

Ic = 10 mA, VCE = 5V, f = 100 MHz

1.5

JLmho

5.5

Note 1: For operation in ambient temperatures above 25~C, the device must be derated based on a 150"C maximum junction temperature and a thermal resistance
of 66"C/W junction to ambient.
Note 2: The collector of each transistor is isolated from the substrate by an integral diode. Therefore, the collector voltage should remain positive with respect to
pin 17 at all times.
Note 3: If oscillation exists under some load conditions, add 2.70 and 0.05 IAF series network from pin 1 to ground.

1-46

Typical Amplifier Performance Characteristics
Power Supply Rejection Ratio
(Referred to the Output)
vs Frequency

Quiescent Supply Current
vs Supply Voltage

Peak-to-Peak Output Voltage
Swing vs Supply Voltage
:i2

10

::l

- -

I-

~ I-

I-

z

"
~

10

A~~ ~
-

6
:;

so

/-?"V~
r,.,.
'/
/. ~

~

40

~

30

~~

-

4 '-

o
9

10

11

12

10

SUPPL Y VOL TAGE (VOL IS)

Voltage Gain vs Frequency

'"z

30

'""

20

~>

~

C!. I,! 1)1!loJ

z

"
~
t;

111111111

40

~

c! !!ll~1

E
u

~

~
~
~
~

10

"~
100

lk

10k

lOOk
FREQUENCY (Hz)

~

."

0.&

~
iii

0.5

0.4

OUTPUT POWER (WATTS)

0.5

0.7
0.&
0.5
0.4

"

0.3
D.Z

..

0.1

0.8

i::

w
u

0.3

V
o
50 100200 500 lk Zk

5k 10k 20k

l::tI;J;Itttt!!ll!tttltI

0.001

0.01

0.1

·~Ai'MJM

I
V!"lzv
1-.

V
r--,~

~~CONTINUOUS

~t ;.....

DISSIPATION

I

':::lrt

~VS'&V ~~

I

:!f-'0llD'ST._
LEVEL

~~:~~T.

r-

I

f/l

0.1

1.0

POWER OUT IWATTS}

Device Dissipation vs Output
Power-S!l Load

~

D.Z

I

20

S

0.1

=an HIIt--f+ttttlll-+-tlltitHI
1kHzHttt-J--t1'ltt1IH--t--IffiHttt

FREQUENCY 1Hz)

0.7

i::

"

f"

o

1.0

12

Vs" 6V

Rl

1 I.

0.2

1M

11

Distortion vs Output Power

POUT = 125 mW
Av "26 dB IC4, 12 " OJ

0.4

0.9

0.3
D.Z

A,.8ll.1

10

10

I I

0.8
0.&

1.0

0.4

"uw

9

SUPPLY VOLTAGE (VOLTS)

1.0

0.9
0.8

";::
iii

:

Vs =6V

1.8
1.&
1.4
I.Z

Device Dissipation vs Output
Power-4!l Load

!z

4

Distortion vs Frequency
ZD

SO

lOOk

FREQUENCY 1Hz)

60

;;;

10k

lk

100

0.1 D.Z 0.3 0.4 0.5 0.& 0.7 0.8 0.9 1.0
OUTPUT POWER (WATTS)

Device DIssIpatIon vs Output
Power-16!l Load
0.5

V~~

~ 0.4

:;:

~

z

"
~

0.3

iii o.z
E
u

~

0.1

I

I

//1)
Vs=9V

.-{-t>
l~ r>-<

/

loLDIST.
F- LEVEl

_3%OIST.
LEVEl

1T
s

0.1 0.2 0.3 0.4 0.5 0.6 0.1 0.8 0.9 1.0
OUTPut POWER (WATTS)

TL/H17847-3

1·47

II

a»
co
(")

:s

Typical Transistor Performance Characteristics
Forward Current Transfer Ratio
vs Collector Current

i

&00

-

~

40D

-

'"~

laO

-

o

~~

Saturation Voltage vs
Collector Current

Open Circuit Output Admittance
vs Collector Current

250
Ie =101a

"oS..

.

200

w

-

200

'"'"a 100
o
'" o

~

~
>

OYNAM~

is
;::
:il

Tm

.....
~

'"~

I-

II

-

0.01

150

f-

100

r-

0

50

V

o

0.1

0.01

10

COLLECTOR CURRENT (mAl

0.1

10

COLLECTOR CURRENT (mAl

COLLECTOR CURRENT (mAl

TL/H17847-4

20

Noise Voltage vs~requency

High Frequency Current Gain
vs Collector Current

Noise Current vs Frequency
10

100

~

18

-

:~

=

12

.......1 Ic"10mA

VeE" 5V
''"10DMHz

Ii

-<:

~

10

IZ

,.-

W

'"'"
'"u
;g

;'

z

I

It

10k

100

FREQUENCV (Hz)

S

i

.3
w
u

z

8DD

400

~

200

I-

I

J

16

700

i8

14
",.

L

500

C~ ~

I/.:.

300

/

,

100

o

o

10k

Ik

o

FREQUENCY (Hd

goe and Coe vs Collector
Current

600

o

I

12
10

V

Ie - COLLECTOR CURRENT (mA)

0

~
~
~

VeE =5V

~

fi'O.7~HZ -

10

{'

~

I

"'z"

..
w
u

i
I-

~
1l
I
J

200

goe and Coe vs Collector
Current

I
I

180
160

60
40
20

14

,-

100
80

~ 16

c_........ /

120

J

12
10

'/ /
/

8
VeE" 5V

'::lMHz

J

10
Ie - COLLECTOR CURRENT (mA)

a"
I

g
:;I
OJ

l:
~

§
~

o

12

4

8

10

12

14

16

Contours of Constant Noise
Figure
20
II

"/

140

2

Ie - COLLECTOR CURRENT (mAl

12

10k
7k ~:

§

4k

u

g;

...

2k

5l

tV.CE -5V·

f~~; .Hz
l~d8

'\

It

;; 700

iiiI

~

400
200
100

r-...

~

N~

0.1

0.3

1.0

3.0

10

Ie - COLLECTOR CURRENT (mAl

TL/HI7847-5

1-48

Application Hints
bypass the unused input, preventing degradation of gain
and possible instabilities. This is done with a 0.1 ftF capacitor or a short to ground depending on the dc source resistance of the driven input.

Gain Control
To make the LM389 a more versatile amplifier, two pins (4
and (2) are provided for gain control. With pins 4 and 12
open, the 1.35 kfl resistor sets the gain at 20 (26 dB). If a
capacitor is put from pin 4 to 12, bypassing the 1.35 kfl
resistor, the gain will go up to 200 (46 dB). If a resistor is
placed in series with the capacitor, the gain can be set to
any value from 20 to 200. A low frequency pole in the gain
response is caused by the capacitor working against the
external resistor in series with the 150fl internal resistor. If
the capacitor is eliminated and a resistor connects pin 4 to
12, then the output dc level may shift due to the additional
dc gain. Gain control can also be done by capacitively coupling a resistor (or FET) from pin 12 to ground.
Additional external components can be placed in parallel
with the internal feedback resistors to tailor the gain and
frequency response for individual applications. For example,
we can compensate poor speaker bass response by frequency shaping the feedback path. This is done with a series RC from pin 1 to 12 (paralleling the internal 15 kfl resistor). For 6 dB effective bass boost: R "" 15 kfl, the lowest
value for good stable operation is R = 10 kfl if pin 4 is
open. If pins 4 and 12 are bypassed then R as low as 2 kfl
can be used. This restriction is because the amplifier is only
compensated for closed-loop gains greater than 9V/V.

Supplies and Grounds
The LM389 has excellent supply rejection and does not require a well regulated supply. However, to eliminate possible high frequency stability problems, the supply should be
decoupled to ground with a 0.1 ftF capacitor. The high current ground of the output transistor, pin 18, is brought out
separately from small signal ground, pin 17. If the two
ground leads are returned separately to supply then the parasitic resistance in the power ground lead will not cause
stability problems. The parasitic resistance in the signal
ground can cause stability problems and it should be minimized. Care should also be taken to insure that the power
dissipation does not exceed the maximum dissipation of the
package for a given temperature. There are two ways to
mute the LM389 amplifier. Shorting pin 3 to the supply voltage, or shorting pin 12 to ground will turn the amplifier off
without affecting the input signal.
Transistors
The three transistors on the LM389 are general purpose
devices that can be used the same as other small signal
transistors. As long as the currents and voltages are kept
within the absolute maximum limitations, and the collectors
are never at a negative potential with respect to pin 17,
there is no limit on the way they can be used.

Input Biasing
The schematic shows that both inputs are biased to ground
with a 50 kfl resistor. The base current of the input transistors is about 250 nA, so the inputs are at about 12.5 mV
when left open. If the dc source resistance driving the
LM389 is higher than 250 kfl it will contribute very little
additional offset (about 2.5 mV at the input, 50 mV at the
output). If the dc source resistance is less than 10 kfl, then
shorting the unused input to ground will keep the offset low
(about 2.5 mV at the input, 50 mV at the output). For dc
source resistances between these values we can eliminate
excess offset by putting a resistor from the unused input to
ground, equal in value to the dc source resistance. Of
course all offset problems are eliminated if the input is capacitively coupled.

For example, the emitter-base breakdown voltage of 7.W
can be used as a zener diode at currents from 1 ftA to
5 mAo These tranSistors make good LED driver devices,
VSAT is only 150 mV when sinking 10 mA.
In the linear region, these transistors have been used in AM
and FM radios, tape recorders, phonographs and many other applications. Using the characteristic curves on noise
voltage and noise current, the level of the collector current
can be set to optimize noise performance for a given source
impedance. Some of the circuits that have been built are
shown in Figures 1-7. This is by no means a complete list
of applications, since that is limited only by the designers
imagination.

When using the LM389 with higher gains (bypassing the
1.35 kfl resistor between pins 4 and (2) it is necessary to

II
~;-{gE}[g- *
LOCAL OSC
& MIXER

1ST
IF

2NO
IF

OETECTOR

OUTPUT AMPLIFIER & SPEAKER
TLlH17847-6

FIGURE 1_ AM Radio

1-49

Application Hints (Continued)

t-------~V.3~~------~t_----~--------._~------~,~.5k~-------.--.--O·V
HEAD

])

"*220J.l.F

1.8k

15k

Mit

D
5.6k

100

All switches in record mode
O.02$1F

Head characteristic 280 mH/30011

6.8.
TL/H/7847 -7

FIGURE 2. Tape Recorder
+12V

Uk

0.1,,1

SASS
10k

10k

'OOk

"*

5.6k
1pF

+

4""

ODJl"F

,.

1pF

O.1"F

2k

,.

':"
O.DDJ3pf

+

16

+

IBDk

oDOJJs,rF

i

p''''''

510
':"

':"

-r"'"
TUHI7B47-B

FIGURE 3. Ceramic Phono Amplifier with Tone Controls

1·50

Application Hints (Continued)
FM
DETECTOR
OUTPUT

+lZV

It

VOL

10k

5kHz

BP
FILTER

tOOk

:""ffiF

lOOk

un

---f

T

D.D5JJF

O.lpF

~
TLlH/7847-9

FIGURE 4. FM Scanner Noise Squelch Circuit
V,
ON RATE
{1-1HzI

10.

1= _ _
1__
O.69R1C1

1k

TLlH17847-10

FIGURE 5. Siren
+12V

1211<

5."

10k

II

1k

+1QV

TO.'"
220l'F

+~

11

2.1n

~

6

T

*OPTIDNAL
TREMOLO
INPUT

O.OSpF

~

2.1k

• Tremolo Ireq. ,;; 2" (R

+ 10k)C

TLlH17847-11

FIGURE 6. Voltage-Controlled Amplifier or Tremolo Circuit

1-51

en
co
('I)

:;

r----------------------------------------------------------------------------,
Application Hints (Continued)
12V
Vs

q

O.I~F

.-----..--..---~

NC

TLlH17847 -12

FIGURE 7. Noise Generator Using Zener Diode

1-52

.-s:::

~ Semiconductor
NatiOnal

Co)

co
o

Corporation

LM390 1 Watt Battery Operated Audio Power Amplifier
II Self-centering output quiescent voltage

General Description
The LM390 Power Audio Amplifier is optimized for 6V, 7.5V,
9V operation into low impedance loads. The gain is internally set at 20 to keep the external part count low, but the
addition of an external resistor and capacitor between pins
2 and 6 wil increase the gain to any value up to 200. The
inputs are ground referenced while the output is automatically biased to one half the supply voltage.

II

Variable voltage gain

II Low distortion
II Fourteen pin dual-in-line package

Applications
II AM-FM radio amplifiers
II Portable tape player amplifiers
II Intercoms

Features

II TV sound systems
II Lamp drivers
II Line drivers
II Ultrasonic drivers
II Small servo drivers
II Power converters

II Battery operation
II 1W output power
II Minimum external parts
II Excellent supply rejection
II Ground referenced input

Equivalent Schematic and Connection Diagrams
14
BOOT

v,

Dual-In-Line Package

,

STRAP

'"

BYPASS

GAIN

13
VOUT

GND [

-INPUT

50'

13 Your

"]
11

GND

10

GAIN

-INPUT

14 Vs

9

800T
STRAP
+INPUT

TLlHI7B4B-2
3,4,5,
10,11,12

~~--+---------~--+-~~----~----------~-oGND

Order Number LM390N
See NS Package Number N14A

TLlH/7B4B-1

II

1-53

C) r-----------------------------~------------------------------------------------__.

~
:::i
....I

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
10V
Package Dissipation 14·Pin DIP (Note 1)

±O.4V

+ 150·C
O·C to + 70·C

-65·C to

Operating Temperature
Junction Temperature
Lead Temperatur~ (Soldering, 10 sec.)

8.3W

Electrical Characteristics TA =
Symbol

Input Voltage
Storage Temperature

150·C
260·C

25·C, (Figure 1)

Parameter

Conditions

Min

Max

Typ

Vs

Operating Supply Voltage

4

10

Quiescent Current

Vs = 6V, VIN = 0

POUT

Output Power

Vs = 6V, RL = 40, THD = 10%

0.8

1.0

Av

Voltage Gain

Vs = 6V, f 1 kHz
10 ",Ffrom Pin 2 to 6

23

26
46

10

Units

9

V

20

mA
W

30

dB
dB

BW

Bandwidth

Vs = 6V, Pins 2 and 6 Open

300

THD

Total Harmonic Distortion

Vs = 6V, RL = 40, POUT = 500 mW
f = 1 kHz, Pins 2 and 6 Open

0.2

PSRR

Power Supply Rejection Ratio

Vs = 6V, f = 1 kHz, CSYPASS = 10 ",F,
Pins 2 and 6 Open, Referred to Output
(Note 2)

50

dB

10

50

kO

Input Bias Current
Vs = 6V, Pins 7 and 8 Open
ISlAS
Nole 1: Pins 3, 4, 5, 10, 11, 12 at 25'C. Derate at 15'C/W above 25'C case.
Nole 2: If load and bypass capacitor are returned to Vs (Figure 2). rather than ground (Figure 1). PSRR is typically 30 dB.

250

nA

Input Resistance

RIN

kHz

%

1

Typical Performance Characteristics
Maximum Device Dissipation
vs Ambient Temperature

16 ~~~-,-T~-r-r-r.~

I I I
9 t;;1N;;!FI.;;;:IT~';;;;HE+'AT:-;;,,;!;,.:-+-++++-l

10

I~~~d-+-~~-+~

7f-H-+--P-.t-++-+-H
I I
"
I I I i " ' - " e/W

&

5

STAVERVl

BIN SO

Ll

4 ~_s- C~iEjiO'llTl~35'C/W

3
2

iW~

FREE AIR

f-

14

~

~-+-+-r~-~~~~~

~

6 ~~-+-+-+-+-+~~~

~

4

~~-+-+-+-+-r-r-r~

2 ~~-+-+-+-+-r~~~

RL=II!

i75V ......

6 1-+-+~'-+:.oI"'i':,joo......
og,...o'l-+-t-f

5
4

::::;~

~ .....

FiL =t!~-+-t-+-l
I
I

3

2
I

SUPPLY VOLTAGE IVI

10

Iii'

i
;;

~

~~

mit
~

100

1k

10k

Distortion vs Frequency

.~ ~~T.'500Imw+-+-~+-~

IIIIIIII

I=I:IJ~Wl:tilHt

4.0

40

Httt'llilrit-t--'lIIlH1lllll-+tHfl.-\+t

2.0

f= 1 kHz

C2.6= 10~F

~~~~~2~~&·'~0~~~~~

20

H-Hfl!II!-1H-H'I!III-++

10

H-Hfl!II!-1H-HiIHI-++

I

. . . . r-.. A~=200
II

>

10k

1/

0.2~

o L..J..1J.WlL.L.lJJJJJL..J.J.
lk

tOOk

10

50

3D

IIIII~

I1111

FREQUENCY IHzl

Voltage Gain vs Frequency
60

100

4

;~10~
:o:~

~I

SUPPLY VOLTAGE (V)

H-++I~RL~-7~P-'

1-++-11f-+-bo1I/'Y-'971~~

HI~~~

I-i-t-iiil........

40

4

Peak-to-Peak Output Voltage
Swing vs Supply Voltage
I

50

L....JL...-J--'---'---'---'---'---'-....L......I

TA - AMBIENT TEMPERATURE I'CI
Note: 2 oz:. copper foil. single-sided PC baard.

1

1
'"

/'

12 ~~-+-+~-+~~~~~~

o

60 I""Tmn,...-,rr

a;

i ': ~~,.~+~-+-+-+-+-~~~

~ H;t;if-:'·LS~7.J= 85°C}W to 10 20 30 40 50 &lJ 70 10 10 1110

9

Power Supply Rejection Ratio
(Referred to the Output) vs
Frequency

Quiescent Supply Current vs
Supply Voltage

lOOk

FREQUENCY IHzl

1M

0.1 L......J'---1.....J.I---L-L-...I.--'--'-I
20 50 100 200 500 Ik 2k 51< 10k 2011

FREQUENCY 1Hz!
TL/H17848-5

1-54

.-----------------------------------------------------------------------------'.
Typical Performance Characteristics

1.2

10.0

"
~

3.0

u

1.0

0

VS' sv
Rl - 4~t
AV"20

~

"
~

in
c;

~

ill
~

~

E

v~.J'Y

f,., 1 kHz
S.O

O.s
0.3

0.1

1.0

0

O.B

illc;

0.6

u

D.'

~

I--

Co)

co
o

Device Dissipation vs
Output Power 4fl load

Distortion vs Output Power

g

s:

(Continued)

/

rr

I.'

~

"

0.2

r-

08

,.
,.f'~~

0.1

THL\%

VS·1.5V

/

Device Dissipation vs
Output Power afl load

,.
~

~

;:

0.01

0.3

0.6 1.0

,.,

05

~
c;
w

03

~

0.2

u

VS'6V

-I 1

v

0.'

re-

THO ~ 3%~'"

Vs= 7.5V

Vs'" 6V

V'

0.1

::bLY
-:~"t
I' ITH~ -lr%
11
I I

0

0
0.03 0.060.1

V'

0

~rl0%-

v~. Jv

c--

0.6

z

0

0.4

POWER OUTPUT (WI

0,8

1.2

1.6

0

2.0

0.2

0.4

0.6

0.8

OUTPUT POWER (WI

OUTPUT POWER (WI

TL/H17848-6

Application Hints
Gain Control
To make the LM390 a more versatile amplifier, two pins (2
and 6) are provided for gain control. With pins 2 and 6 open,
the 1.35 kfl resistor sets the gain at 20 (26 dB). If a capacitor is put from pin 2 to 6, bypassing the 1.35 kfl resistor, the
gain will go up to 200 (46 dB). If a resistor is placed in series
with the capacitor, the gain can be set to any value from 20
to 200. A low frequency pole in the gain response is caused
by the capacitor working against the external resistor in series with the 150fl internal resistor. If the capacitor is eliminated and a resistor connects pin 2 to 6 then the output dc
level may shift due to the additional dc gain. Gain control
can also be done by capacitively coupling a resistor (or
FET) from pin 6 to ground, as in Figure 7.
Additional external components can be placed in parallel
with the internal feedback resistors to tailor the gain and
frequency response for individual applications. For example,
we can compensate poor speaker bass response by frequency shaping the feedback path. This is done with a series RC from pin 6 to 13 (paralleling the internal 15 kfl resistor). For 6 dB effective bass boost: R "" 15 kfl, the lowest
value for good stable operation is R = 10 kfl if pin 2 is
open. " pins 2 and 6 are bypassed then R as low as 2 kO
can be used. This restriction is because the amplifier is only
compensated for closed-loop gains greater than 9 VIV.

bypass the unused input, preventing degradation of gain
and possible instabilities. This is done with a 0.1 ",F capacitor or a short to ground depending on the dc source resistance on the driven input.
Bootstrapping
The base of the output transistor of the LM390 is brought
out to pin 9 for Bootstrapping. The output stage of the amplifier during positive swing is shown in Figure 3 with its
external circuitry.
R1 + R2 set the amount of base current available to the
output transistor. The maximum output current divided by
beta is the value required for the current in R1 and R2:
(R1

+ R2)

=

fio (Vs/2)

- VBE

lOMAX

Good design values are VBE = 0.7V and fio = 100.
Example 0.8 watt into 4fl load with Vs = 6V.
10 MAX =

(R1

+

R2)

~

j?

100

Po
RL

- - = 632 mA

«6/~~6;20.7)

= 364fl

To keep the current in R2 constant during positive swing
capacitor CB is added. As the output swings positive CB lifts
R1 and R2 above the supply, maintaining a constant voltage
across R2. To minimize the value of CB, R1 = R2. The pole
due to CB and R1 and R2 is usually set equal to the pole
due to the output coupling capacitor and the load. This
gives:
4Cc
Cc
CB""-""fio
25
Example: for 100 Hz pole and RL = 4fl; Cc = 400 ",F and
CB = 16 ",F, if R1 is made a diode and R2 increased to give
the same current, CB can be decreased by about a factor of
4, as in Figure 4.
For reduced component count the load can replace R1. The
value of (R1 + R2) is the same, so R2 is increased. Now CB
is both the coupling and the bootstrapping capacitor (see
Figure 2).

Input Biasing
The schematic shows that both inputs are biased to ground
with a 50 kfl resistor. The base current of the input transistors is about 250 nA, so the inputs are at about 12.5 mV
when left open. " the dc source resistance driving the
LM390 is higher than 250 kfl it will contribute very little
additional offset (about 2.5 mV at the input, 50 mV at the
output). " the dc source resistance is less than 10 kfl, then
shorting the unused input to ground will keep the offset low
(about 2.5 mV at the input 50 mV at the output). For dc
source resistances between these values we can eliminate
excess offset by putting a resistor from the unused input to
ground, equal in value to the dc source resistance. Of
course all offset problems are eliminated if the input is capacitively coupled.
When using the LM390 with higher gains (bypassing the
1.35 kO resistor between pins 2 and 6) it is necessary to

1-55

II

or-----------------------------------------------------~

en

~

Typical Applications

...I

6V

6V

lBO

TL/HI7848-4

TL/H/7848-3

FIGURE 2. Load Returned to Supply
(Amplifier with Gain = 20)

FIGURE 1. Load Returned to Ground
(Amplifier with Gain = 20)

{ r.

,....---....-oVs

F_..._ ...._-o Vs

Rl

14

R2
CB
Cc

+1·,
TLlH/7848-7

FIGURE 3

TLlH/7848-8

FIGURE 4. Amplifier with Gain

=

200 and Minimum CB

6V

120

47,.1'

+
120

10k>......--~

500k

FIGURE 5. 2.5W Bridge Amplifier
1-56

TLlH17848-9

r-

Typical Applications

:s::

(Continued)

Co)

Vs

CD

o

27
26

180

25

=
~

z

~

I +1

"''"

470~F

u .'

24
23
22

<[

:;

21

CI

20
19

>

r- V"

I
I

_.

t\
\

II

\ -r- _.- r-r- -~ r--.

f-

18

V

.,'

17
20

50 100200 500 lk 2k . 5k 10k 20k

2.7

":"

l-

FREQUENCY (Hz 1

TLlH17848-11

":"

TLlH17848-10

FIGURE SIb). Frequency Response
with Bass Boost

FIGURE S(a). Amplifier with Bass Boost
6Vo--4-...- - - - .
BYPASS

dh "J

~

O.1~F

180

,1

TALK

TALK

REMOTE

MASTER

.....- - - - - 1 - - - 0 LISTEN

TLlH/7848-12

FIGURE 7. Intercom

1

180

Cc

OETE~~~~

0-1

Vl~~

II

Rl
10k

""',..,.+---=--:..j

....

!50"1
F

T

O1
. "F

8"
SPEAKER

-::-

TL/H/7848-13

FIGURE 8. AM Radio Power Amplifier
Note I: Twist supply lead and supply ground very tightly.

Note 4: RICI band limits input signals.

Note 2: Twist speaker lead and ground very tightly.

Note 5: All components must be spaced very close to IC.

Note 3: Ferrite bead is Ferroxcube KS-OOI-OO1l38 with 3 turns of wire.

1-57

.r--------------------------------------------------------------------------------,
CD
~ ~National
....
Semiconductor
CorporaHon

LM391 Audio Power Driver
General Description

Features

The LM391 audio power driver is designed to drive external
power transistors in 10 to 100 watt power amplifier designs.
High power supply voltage operation and true high fidelity
performance distinguish this IC. The LM391 is internally protected for output faults and thermal overloads; circuitry providing output transistor protection is user programmable.

•
•
•
•
•
•
•

±50V max
0.01%
3 p,V
90 dB

High Supply Voltage
Low Distortion
Low Input Noise
High Supply Rejection
Gain and Bandwidth Selectable
Dual Slope SOA Protection
Shutdown Pin

Equivalent Schematic and Connection Diagram
r---~--~----------~----------t_----------_1~--~-o15

y+

25k

25k

L.o---+--o B OUTPUT SOURCE
>-...---+--o 10 + I LIMIT
L-~I-+--o 11 +SOA

..--------+_0 9
........1-+--0

OUTPUT SENSE

12 - SOA

~""-----+-O 13 -I LIMIT

...------..---------+-_0 5

OUTPUT SINK

25k

25k

L-____~~----~~----~~--------------_~~16

yTLlH17146-1

Dual-In-Llne Package
v-

+IN

16

-IN

15

y+

COMPC

14

SHUTOOWN

RIPPLE C

13

-I LIMIT

SINK

-SOA DIODE

BIAS

+SOA DIODE

BIAS

+ I LIMIT
OUTPUT SENSE

SOURCE

TLlH17146-2

Top View
Order Number LM391N-100
See NS Package Number N16A

1-58

r-

s::

Absolute Maximum Ratings

(,)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
LM391N-100

Shutdown Current (Pin 14)

Parameter

O·Cto +70·C

Operating Temperature

260·C

Lead Temp. (Soldering, 10 sec.)

Supply Voltage less 5V

Electrical Characteristics TA =

1.39W
- 65·C to + 150·C

Storage Temperature

±50Vor + 100V

Input Voltage

1 mA

Package Dissipation (Note 1)

CD
......

25·C (The following areforV+ = 90% V+MAX and V- = 90% V-MAX.)
Conditions

Min

Quiescent Current
LM391N-100

Current in Pin 15
VIN = 0

Output Swing

Positive
Negative

Drive Current

Source (Pin 8)
Sink (Pin 5)

V+ -7
V- + 7

Noise (20 Hz-20 kHz)

Input Referred

Supply Rejection

Input Referred

Total Harmonic Distortion

1= 1 kHz
f=20kHz

Typ

Max

5

6

V+ - 5
V- + 5

mA
mA

70

3

/LV

90

dB

0.01
0.10

Intermodulation Distortion

60 Hz, 7 kHz, 4:1
f = 1 kHz

mA
V
V

5
5

Open Loop Gain

Units

1000

Input Bias Current
Input Offset Voltage

0.25

%
%

0.01

%

5500

VIV

0.1

1.0

/LA

5

20

mV

Positive Current Limit VSE

Pin 10-9

650

Negative Current Limit VSE

Pin 9-13

650

mV

Positive Current Limit Bias Current

Pin 10

10

100

/LA

Negative Current Limit Bias Current

Pin 13

10

100

/LA

mV

Pin 14 Current Comments
Minimum pin 14 current required lor shutdown is 0.5 mA, and must not exceed 1 mAo
Maximum pin 14 current for amplifier not shut down is 0.05 mA.
The typical shutdown switch point current is 0.2 mA.
Note 1: For operation in ambient temperatures above 25"C, the device must be derated based on a 150"C maximum junction temperature and a thermal resistance
of 90"C/W junclion to ambient.

Typical Applications
v+

t

Rfl

w_r-..

_

tCI
THERMAL
SWITCH

.... RTH

ffi·~m·"
-= OPEN o---J.h

14

+
100>"

;..RIN

"*
v-

II

RI2

RE

.r;

RE

RO

B 9

~
6 5

16 1

R~

/'

~

"L-

4

LM391

~1

CIN

~
5

L

RA

+CC~

;~

C~B

"

t*

~CO

r
TLlH/7146-3

FIGURE 1. LM391 with External Components-Protection Circuitry Not Shown
1-59

Typical Performance Characteristics
Output Power vs Supply Voltage

200

~
~

.'"t

il
:;

"
I

0:

lID

O.IB

160

0.16

140
120
10D
80

~
~

ZO

/

/

40

"'

D~ t-"
t1D

i

V

120

0.04

20

50 100200

iii
ez

~

Z'

in

~~

90

t=c:;
uw

"'-

~e

~~

50

I

3D

I
I

2D
lD
0

~~
w'"

~~

"'-

2!!

I

100

1.

'\.
10k

lOOk

I\V"ZO

0.04
2D

5D 10D 2DO

1M

0.4
'!20iH,

r-...WITH CR

"

'\
WITHOUT CR '\.'\.
I
'\.

I

50
10M

FREQUENCV (HERT2)

Total Harmonic Distortion vs
AB Bias Current

PQS1TIVE SUPPL V

80

6D

20

50 100200 500 ,. 2'

CR" Cc

5k 10k 20k

D.5

NEG1T1V~ SJPPL V

1D

50D ,. Z'

FREQUENCV (HERTZ)

J

>0:

Cc' 5pF WITH
1MO RESISTOR

D.oa

51!. 101r: 20k

.",

4D

/

O.IZ

Input Referred Power Supply
Rejection vs Frequency
100

Cc' 5pF

80

60

500 ,.

0.20

FREnUENCV (HERT2I

Open Loop Gain vs Frequency

~

~ 0.24

AV'ZD

.00

AV'200/

0.28

0.02

10D

10

0.32

... 0.16

V

SUPPLV VOLTAGE (VOLTS)

90

0.36

~

/

0.D6

I
±3D

0.10

... o.oa

. / RL ·an

v.:

AV'200/

Total Harmonic Distortion vs
Fre uency (RL = 40)

0.40

I
1
I I

Si 0.12

./

./

Total Harmonic Distortion vs
Frequency (RL = 80)

0.14

,r

RL '40

6D

!;

0.20

~

0.3

'"'"....
02

~

......

D.l

RL"an

0
5' 10. zoo

RL"4n

r-..
0

5 10 15 ZO 25 30 35 40 45 50
AB BIAS CURRENT (MILLIAMPS)

FREQUENCV (HERTZ)

TUH17146-4

Pin Descriptions
Pin No.

Pin Name

Comments

1
2
3
4
5
6

+ Input
-Input
Compensation
Ripple Filter
Sink Output
BIAS
BIAS
Source Output
Output Sense
+ Current Limit
+SOADiode
-SOADiode
- Current Limit
Shutdown
V+
V-

Audio input
Feedback input
Sets the dominant pole
Improves negative supply rejection
Drives output devices and is emitter of AB bias VSE multiplier
Base of VSE multiplier
Collector of VSE multiplier
Drives output devices
Biases the IC and is used in protection circuits
Base of positive side protection circuit transistor
Diode used for dual slope SOA protection
Diode used for dual slope SOA protection
Base of negative side protection circuit transistor
Shuts off amplifier when current is pulled out of pin
Positive supply
Negative supply

7
B
9
10
11
12
13
14
15
16

1-60

External Components (Figure 1)
Component

Typical Value

CIN

1,...F

RIN

100k

Sets.input impedance and DC bias to input.

RI2

100k

Feedback resistor; for minimum offset voltage at the output this should be equal to RIN.

Rll

S.1k

Comments
Input coupling capacitor sets a low frequency pole with RIN.
1
fL =
2'ITRINCIN

Feedback resistor that works with Rf2 to set the voltage gain.
Av = 1

+ !!!2
Rll

Ct

10 ,...F

Feedback capacitor. This reduces the gain to unity at DC for minimum offset voltage at the
output. Also sets a low frequency pole with Rll'
1
fL=--2'ITR1 1CI

Ce

SpF

Compensation capacitor. Sets gain bandwidth product and a high frequency pole.
GBW =

1
f = GBW
2'ITSOOOCe' h
Av
Max fh for stable design :::: SOO kHz.

RA

3.9k

AB bias resistor.

Rs

10k

AB bias potentiometer. Adjust to set bias current in the output stage.

CAS

0.1,...F

Bypass capacitor for bias. This improves high frequency distortion and transient response.

CR

SpF

Ripple capacitor. This improves negative supply rejection at midband and high frequencies.
CR, if used, must equal Ce.

Reb

1000

Bleed resistor. This removes stored charge in output transistors.

Ro

2.7!l

Output compensation resistor. This resistor and Co compensate the output stage. This value
will vary slightly for different output devices.

Co

0.1 p.F

Output compensation capacitor. This works with Ro to form a zero that cancels fp of the
output power transistors.

RE

0.30

Emitter degeneration resistor. This resistor gives thermal stability to the output stage
quiescent current. IRC PWS type.

RTH

39k

Shutdown resistor. Sets the amount of current pulled out of pin 14 during shutdown.

C2,C'2

1000 pF

Compensation capacitors for protection circuitry.

XL

1001ls p.H

Used to isolate capacitive loads, usually 20 turns of wire wrapped around a 100, 2W resistor.

II

1-61

~

en
C')

~

r------------------------------------------------------------------------------------------,
Application Hints
To prevent thermal runaway of the AB bias current the following equation must be valid:

GENERALIZED AUDIO POWER AMP DESIGN
Givens:

Power Output

9JA

Load Impedance

s:

Input Sensitivity

9JA is the thermal resistance of the driver transistor, junction to ambient, in 'C/W.

Bandwidth
The power output and load impedance determine the power
supply requirements. Output signal swing and current are
found from:
VOpeak = 42 RL Po

IOpeak =

/r!
PO

---

RE is the emitter degeneration resistance in ohms.
13min is that of the output transistor.

(I)

VCEOMAX is the highest possible value of one supply from
equation (3).

(2)

K is the temperature coefficient of the driver base-emitter
voltage, typically 2 mV

rc.

RL
Add 5 volts to the peak output swing (VOp) for transistor
voltage to get the supplies, i.e., ± (Vop + 5V) at a current
of Ipeak. The regulation of the supply determines the unloaded voltage, usually about 15% higher. Supply voltage will
also rise 10% during high line conditions.

± (VOpeak

(5)

where:

Input Impedance

max supplies ~

RE (13MIN + 1)
VCEOMAX{K)

+ 5) (I + regulation) (1.1)

Often the value of RE is to be determined and equation (5)
is rearranged to be:
RE :;;, 9JA (VCEOMAxl K
(6)
13MIN + 1
The maximum average power dissipation in each output
transistor is:

(3)

POMAX = 0.4 POMAX
The power dissipation in the driver transistor is:

The input sensitivity and output power specs determine the
required gain.

(7)

-POMAX
PORIVER(MAX) = -a-(8)
... MIN
Heat sink requirements are found using the following formulas:

(4)

Normally the gain is set between 20 and 200; for a 25 watt,

a ohm amplifier this results in a sensitivity of 710 mV and 71
mY, respectively. The higher the gain, the higher the THO,
as can be seen from the characteristics curves. Higher gain
also results in more hum and noise at the output.

9
JA
9SA

The desired input impedance is set by RIN. Very high values
can cause board layout problems and OC offsets at the output. The bandwidth requirements determine the size of Ct
and Cc as indicated in the external component listing.

s: TJMAX -

TAMAX

(9)

Po

s:

9JA - 9Jc- 9cs

(10)

where:
TjMAX is the maximum transistor junction temperature.
T AMAX is the maximum ambient temperature.

The output transistors and drivers must have a breakdown
voltage greater than the voltage determined by equation (3).
The current gain of the drive and output device must be high
enough to supply IOpeak with 5 mA of drive from the LM391.
The power transistors must be able to dissipate approximately 40% of the maximum output power; the drivers must
dissipate this amount divided by the current gain of the outputs. See the output transistor selection guide, Table A.

9JA is thermal resistance junction to ambient.
6SA is thermal resistance sink to ambient.
6JC is thermal resistance junction to case.
9cs is thermal resistance case to sink, typically I'C/W for
most mountings.

1-62

Application Hints (Continued)
PROTECTION CIRCUITRY
The protection circuits of the LM391 are very flexible and
should be tailored to the output transistor's safe operating
area. The protection V-I characteristics, circuitry, and resistor formulas are described below. The diodes from the output to each supply prevent the output voltage from exceeding the supplies and harming the output transistors. The output will do this if the protection circuitry is activated while
driving an inductive load.

resistor is set to limit the current to less than 1 mA (the
absolute maximum). This resistor with the capacitor gives a
time constant of RC. The turn-ON delay is approximately 2
time constants.
Example:
Amplifier with maximum supply of 30V, like the 20W, an
example in the data sheet, requiring a delay of 1 second.
Time delay = 2 RC
MaxV+
R=-1 mA
So:

TURN-ON DELAY
It is often desirable to delay the turn-ON of the power amplifier. This is easily implemented by putting a resistor in series
with a capacitor from pin 14 to ground. The value of the

R = 30k. Solving for C gives 16.7 JoLF. Use C = 20 JoLF with
a 30V rating.

Protection Circuitry with External Components

Protection Characteristics

v+-t--....~,....-,
VB=V+ORV-

RE
OUTPUT

VCE
TL/H17146-6

C21S FOR STABILITY ~ IOOOpF
TLlH17146-5

Protection Circuit Resistor Formulas (VB = V+)
Type of Protection

RE,R'

R1,R'1

R2,R'2

R3,R'3

Current Limit

RE =.2
IL

Not Required

Short

Not Required

Single Slope SOA
Protection

RE = IL

R1 =R2

(VM - -

1 kn

Not Required

Dual Slope SOA
Protection
(VB = V+)

RE =.2
IL

R, = R2

(VM - 

Note:.p is Ihe currenlUmil VeE voltage. 650 mV. Assumptions: V+

>>

.p, VM

>>

transistors.

1-63

---

Rs = R2

kR~+-

 -

II
1]

.p. V+ is the load supply voltage. VM is the maximum rated VCE of the output

~

G)
C')

:!!
..J

r------------------------------------------------------------------------------------------,
OSCILLATIONS & GROUNDING

Application Hints (Continued)

Most power amplifiers work the first time they are turned on .
They also tend to oscillate and have excess THD. Most oscillation problems are due to inadequate supply bypassing
and/or ground loops. A 10 ",F, 50V electrolytic on each
power supply will stop supply-related oscillations. However,
if the signal ground is used for these bypass caps the THD
is usually excessive. The signal ground must return to the
power supply alone, as must the output load ground. All
other grounds-bypass, output R-C, protection, etc., can tie
together and then return to supply. This ground is called
high frequency ground. On the 40W amplifier schematic all
the grounds are labeled.
Capacitive loads can cause instabilities, so they are isolated
from the amplifier with an inductor and resistor in the output
lead.

TRANSIENT INTERMODULATION DISTORTION

There has been a lot of interest in recent years about transient intermodulation distortion. Matti Otala of University of
Oulu, Oulu, Finland has published several papers on the
subject. The results of these investigations show that the
open loop pole of the power amplifier should be above 20
kHz.
To do this with the LM391 is easy. Put a 1 MO resistor from
pin 3 to the output and the open loop gain is reduced to
about 46 dB. Now the open loop pole is at 30 kHz. The
current in this resistor causes an offset in the input stage
that can be cancelled with a resistor from pin 4 to ground.
The resistor from pin 4 to ground should be 910 kO rather
than 1 MO to insure that the shutdown circuitry will operate
correctly. The slight difference in resistors results in about
15 mV of offset. The 40W, SO amplifier schematic shows
the hookup of these two resistors.

AB BIAS CURRENT
To reduce distortion in the output stage, all the transistors
are biased ON slightly. This results in class AB operation
and reduces the crossover (notch) distortion of the class B
stage to a low level, (see performance curve, THO vs AB
bias). The potentiometer, Re, from pins 6-7 is adjusted to
give about 25 rnA of current in the output stage. This current
is usually monitored at the supply or by measuring the voltage across RE.

BRIDGE AMPLIFIER

A switch can be added to convert a stereo amplifer to a
single bridge amplifer. The diagram below shows where the
switch and one resistor are added. When operating in the
bridge mode the output load is connected between the two
outputs, the input is VIN #1, and VIN #2 is disconnected.

Typical Applications

(Continued)
Bridge Circuit Diagram

5.lk

5.U

lOOk

lOOk

YSTEREO

I
TUH17146-7

Output Transistors Selection Guide
TableA.
Power
Output

Output Transistor

Driver Transistor
PNP

NPN

PNP

NPN

20W@80
30W@40

MJE711
MJE171
D43C8

MJE721
MJE1S1
D42C8

TIP42A
2N6490

TIP41A
2N6487

40W@SO
60W@40

MJE712
MJE172
D43C11

MJE722
MJE182
042C11

2N5882

2N5S80

1-64

r-----------------------------------------------------------------------------~

Application Hints (Continued)

r

s:
w

....

CD

A 20W, an; 30W, 4n AMPLIFIER

Solving for CI:

Givens:

1

Power Output

C,:<: - - - = 7.8I-'F; use 10 I-'F
27TRllfL
The recommended value for Cc is 5 pF for gains of 20 or
larger. This gives a gain-bandwidth product of 6.4 MHz and
a resulting bandwidth of 320 kHz, better than required.

20W into Bn
30Wint04n

Input Sensitivity

1VMax

Input Impedance

lOOk

The breakdown voltage requirement is set by the maximum
supply; we need a minimum of 58V and will use GOV. We
must now select a 60V power transistor with reasonable
beta at IOpeak, 3.87A. The TIP42, TIP41 complementary pair
are 60V, 60W transistors with a minimum beta of 30 at 4A.
The driver transistor must supply the base drive given 5 rnA
drive from the LM391. The MJE711, MJE721 complementary driver transistors are 60V devices with a minimum beta of
40 at 200 rnA. The driver transistors should be much faster
(higher fT) than the output transistors to insure that the R-C
on the output will prevent instability.

20 Hz-20 kHz ± 0.25 dB

Bandwidth
Equations (1) and (2) give:
20W/Bn

Vop = 17.9V

lOp = 2.24A

30W/4n

Vop = 15.5V

lop = 3.87A

Therefore the supply required is:
± 23V

@

2.24A, reducing to ...

±21V

@

3.B7A

With 15% regulation and high line we get ±29V from equation (3).
Sensitivity and equation (4) set minimum gain:

To find the heat sink required for each output transistor we
use equations (7), (9), and (10):

420 X 8
Av ~ - 1 - = 12.65

PD = 0.4 (30) = 12W
150'C - 55'C
0JA s;
12
= 7.9'C/WforTAMAX = 55'C

We will use a gain of 20 with resulting sensitivity of 632 mV.
Letting RIN equal lOOk gives the required input impedance.
For low DC offsets at the output we let RI2 = lOOk. Solving
for Rll gives:

0SA s; 7.9 - 2.1 - 1.0 = 4.8'C/W

(7)
(9)
(10)

If both transistors are mounted on one heat sink the thermal
resistance should be halved to 2.4'C/W.

RI2 = lOOk
lOOk
Rll = 20 _ 1 = 5.26k; use 5.1k

The maximum average power dissipation in each driver is
found using equation (8):
12
_
PDRIVER(MAX) = 30 = 400 mW

The bandwidth requirement must be stated as a pole, i.e.,
the 3 dB frequency. Five times away from a pole gives 0.17
dB down, which is better than the required 0.25 dB. Therefore:

Using equation (9):
155 - 55

0JA s; ~ = 237'C/W

20
fL="5=4Hz
fh = 20k x 5 = 100kHz

II

1-65

~

CD

C')

:ill
....I

r------------------------------------------------------------------------------------------,
Application Hints (Continued)
Since the free air thermal resistance of the MJE711,
MJE721 is 100·C/W, no heat sink is required. Using this
information and equation (6) we can find the minimum value
of RE required to prevent thermal runaway.
R
100 (30) (0.002)
E :eo
30 + 1
= 0.190

The data points from the curve are:
VM = 60V, VB = 23V, IL = 3A, I~
Using the dual slope protection formulas:
0.65
RE = -3- = 0.220

(6)

=

7A

R2 = 1k

We must now use the SOA data on the TIP42, TIP41 transistors to set up the protection circuit. Below is the SOA
curve with the 40 and BO load lines. Also shown are the
desired protection lines. Note the value of VB is equal to the
supply voltage, so we use the formulas in the table.

60 - 0.65)
Rl = 1k (
0.65
::::; 91k
R3 = 1k (

23
- 1) ::::; 24k
7(0.22) - 0.65
Note that an RE of 0.220 satisfies equation (6). The final
schematic of this amplifier is below. If the output is shorted
the current will be 1.BA and VeE is 23V. Since the input is
AC, the average power is:
shortPD = %(1.B)(23)::::; 21W

D.C. SOA of TIP42, TIP41
Transistors
8~~--'---r--r--'--'

This power is greater than was used in the heat sink calculations, so the transistors will overheat for long-duration
shorts unless a larger heat sink is used.

VeE (VOLTS)

TLlHI7146-B

Typical Applications

(Continued)

20w-ao, 30W-40 Amplifier with 1 Second Turn-ON Delay
V+--t----------------1~~._------~--_.__,

-21 V TO -29V

V---__--------~__----_4. .- - - - - -. .--~~
TL/H/7146-9

'Additional protection for LM391 N; Schottky diodes and R '" 1000.

1-66

,-----------------------------------------------------------------------------, r

Application Hints

s:

(Continued)

A 40W/80, 60W/40 AMPLIFIER
Given:
Power Output

Since a heat sink is required on the driver. we should investigate the output stage thermal stability at the same time to
optimize the design. If we find a value of RE that is good for
the protection circuitry. we can then use equation (5) to find
the heat sink required for the drivers.

40W/80
60W/40

Input Sensitivity

lVMax

Input Impedance

20 Hz-20 kHz ± 0.25 dB

Equations (1) and (2) give:
40W/80

....

The SOA characteristics of the 2N5882. 2N58BO transistors
are shown in the following curve along with a desired protection line.

lOOk

Bandwidth

~

SOA 2N5882, 2N5880

VOPeak = 25.3V

IOPeak = 3.16A

60W/40
VOPeak = 21.9V
Therefore the supply required is:

IOPeak = 5.48A

± 30.3V

@

3.16A. reducing to ...

±26.9V

@

5.4BA

10

\

~

The minimum gain from equation (4) is:
We select a gain of 20; resulting sensitivity is 900 mY.

RI2 = lOOk

Ct =

o

o

'-4nLOAD

~ ~ ,....-BnLOAD

,,'

\~

\

10

.....

~'

1

The input impedance and bandwidth are the same as the 20
watt amplifier so the components are the same.
RIN = lOOk

,"\

~

'" ~"

Av;;;' 18

SOA

----

V

\

\
_'\

With 15% regulation and high line we get ±38.3V using
equation (3).

Rll = 5.1k

\

20

"

30

~

PROTECTION

.~ ~

~

40

50

60

70

80

VCE (VOLTS)

Cc = 5 pF

TLlH/7146-10

10 ",F
The desired data points are:

The maximum supplies dictate using BOV devices. The
2N5882. 2N5880 pair are 80V. 160W transistors with a minimum beta of 40 at 2A and 20 at 6A. This corresponds to a
minimum beta of 22.5 at 5.5A (IOpeak)' The MJE712.
MJE722 driver pair are 80V transistors with a minimum beta
of 50 at 250 mAo This output combination guarantees IOpeak
with 5 mA from the LM391.

VM=80V

VB=47V

IL=3A

1~=llA

Since the break voltage is not equal to the supply. we will
use two resistors to replace Rs and move VB.
Circuit Used

Output transistor heat sink requirements are found using
equations (7). (9). and (10):
PD = 0.4 (60) = 24W

(7)

200 - 55
(}JA";' ---24-- = 6.0'C/WforTAMAX = 55'C

(9)

eSA";' 6.0 - 1.1 - 1.0 = 3.9'C/W

(10)

For both output transistors on one heat sink the thermal
resistance should be 1.9'C/W.
Now using equation (8) we find the power dissipation in the
driver:
_
24
(8)
PDRIVER = 20 = 1.2W
150 - 55
(}JA";' --1.-2- = 79'C/W

TL/H/7146-11

II

Thevenin Equivalent

(9)
Where: RTH ~ R~

II R~

VTH~v-[~l
R~ + R~

TL/H17146-12

1-67

Application Hints (Continued)
The easiest way to solve these equations is to iterate with
standard values. If we guess R; = 62k, then Rg = 47.12k;
use 47k. The Thevenin impedance comes out 26.7k, which
is close enough to 25.55k.
Now we will use equation (5) to determine the heat sinking
requirements of the drivers to insure thermal stability:

The formulas for RE, Rl, and R2 do not change:
RE =
Rl = lk

0.65

SA =

0.220

80 - 0.65
0.65
= 120k

The formula for R3 now gives RTH when the V+ in the formula becomes Va.
RTH=

8
JA

R2[~-I]
ILRE - c/>

VTH is the additional voltage added to the supply voltage to
get Va.
VTH = -(Va - V+) = -(47 - 30) = -17V
Now we must find R; and Rg using the Thevenin formulas.
Putting VTH, V-, and RTH into the appropriate formulas reduces to:
and

25.55k = R;

Typical Applications

(5)

This value is lower than we got with equation (9), so we will
use it in equation (10):
8SA ,;;; 57 - 6 - 1 = 50'C/W
(10)
This is the required heat sink for each driver. For low TIM
we add the 1 MO resistor from pin 3 to the output and a
910k resistor from pin 4 to ground. The complete schematic
is shown below.
If the output is shorted, the transistor voltage is about 28V
and the current is 5A. Therefore the average power is:
short PD = %(28) 5 = 70W

= 1k [11 (0.2:; _ 0.65 - 1 ] = 25.55k

Rg = 0.76 R;

,;;; 0.22 (20 + 1) :::: 57"C/W
40 (0.002)

This is much larger than the power used to calculate the
heat sinks and the output transistors will overheat if the output is shorted too long.

II Rg

(Continued)
40W-SO, 60W-40 Amplifier

47k

•

27VT039V

TID~F

62k

120kJ,.

5.lk

SHUTOOWN

IN4003

'High Frequency Ground

47k
-27 V TO -3av

""'nput Ground
"·Speaker Ground

TL/H/7146-13

Note: All Grounds Should be Tied Together
Only at Power Supply Ground.
tAdditional protection for LM391N; Schottky diodes and R ., 10011.

1-68

r-------------------------------------------------------------------------,r

s:
co

NatiOnal

~ Semiconductor

....

c.:I

Corporation

LM831 Low Voltage Audio Power Amplifier
General Description

Features

The LMB31 is a dual audio power amplifier optimized for
very low voltage operation. The LMB31 has two independent amplifiers, giving stereo or higher power bridge (BTL)
operation from two- or three-cell power supplies.
The LMB31 uses a patented compensation technique to reduce high-frequency radiation for optimum performance in
AM radio applications. This compensation also results in
lower distortion and less wide-band noise.
The input is direct-coupled to the LMB31, eliminating the
usual coupling capacitor. Voltage gain is adjustable with a
single resistor.

•
•
•
•
•

Low voltage operation, 1.BV to 6.0V
High power, 440 mW, Bn, BTL, 3V
Low AM radiation
Low noise
LowTHD

Applications
•
•
•
•

Portable tape recorders
Portable radios
Headphone stereo
Portable speakers

Typical Application
Dual Amplifier with Minimum Parts

LM831

16kQ
16kQ
8011

Av

+IN

II

-IN

IO'l
+~
4!~
TLlH/6754-1
Av~46dB,BW~250

POUT

~

Hzto35 kHz

220 mW/Ch,RL

1-69

~

4!l

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, Vs

Power Dissipation (Note I), Po
Storage Temperature, T stg
Junction Temperature, Tj

7.5V

Input Voltage, VIN

I.4W

Operating Temperature (Note 1), T apr

±0.4V

-40'Cto +85'C
-65'C to + 150'C
+ 150'C

Lead Temp. (Soldering, 10 sec.), TL

+ 260'C

Electrical Characteristics
Unless otherwise specified, TA = 25'C, Vs = 3V, f = 1 kHz, test circuit is dual or BTL amplifier with minimum parts.
Symbol

Parameter

Conditions

Vs

Operating Voltage

IQ

Supply Current

VIN = 0, Dual Mode
VIN = 0, BTL Mode

Vas

Output DC Offset

VIN = 0, BTL Mode

RIN

Input Resistance

Av

Voltage Gain

PSRR
PO~

Typ

Tested Limit

Unit (Limit)

3
3

1.8
6

V(Min)
V(Max)

5
6

10
15

mA(Max)
mA(Max)

10

50

mV(Max)

25

15
35

k(Min)
k(Max)

VIN = 2.25 mVrms , f = 1 kHz,
Dual Mode

46

44
48

dB (Min)
dB (Max)

Supply Rejection

Vs = 3V + 200 mVrms

46

30

dB (Min)

Power Out

Vs = 3V, RL = 40.,
10% THD, Dual Mode

220

150

mW(Min)

POOL

Power Out Low, Vs

Vs = 1.8V, RL = 40.,
10% THD, Dual Mode

45

10

mW(Min)

POB

Power Out

Vs = 3V, Rl = 80.,
10% THD, BTL Mode

440

300

mW(Min)

POBl

Power Out Low, Vs

Vs = 1.8V, Rl = 80.,
10% THD, BTL Mode

90

20

mW(Min)

Sep

Channel Separation

Referenced to Va = 200 mVrms

52

40

dB (Min)

IB

Input Bias Current

1

2

p.A (Max)

EnO

Output Noise

Wide Band (250 - 35 kHz)

250

500

p.V (Max)

THD

Distortion

Vs = 3V, Po = 50 mW,
f = 1 kHz, Dual

0.25

1

% (Max)

@

f = 1 kHz

Note 1: For operation in ambient temperatures above 25°C. the device must be derated based on a 150"C maximum junction temperature and a thermal resistance

of 90'C/W iunction to ambient.

Connection Diagram
Dual-In-Llne Package

'-'

BTL R .2.
2

Av +INPUT
-INPUT
BOOTSTRAP
POWER GROUND
SIGNAL GROUND
OUTPUT

.!!
.!!
..... .!!

-

I--

..! i--I

13

4

.! ~
.!
.2.
.! I-

utl

BYPASS
Av
+INPUT
-INPUT

~

BOOTSTRAP

~

POWER GROUND

.!!!.
.!.

OUTPUT
POWER SUPPLY
TLIHI67S4-2

Top View
Order Number LM831 N
See NS Package Number N16E

1-70

.-----------------------------------------------------------------------------'r
ii!:
co
Typical Performance Characteristics
.....
Supply Current vs Supply Voltage
PSRR vs Supply Voltage
Co)

10

80
NO SIGNAL
70
60
BTL MOOE

-L.l-

..

-L

II'"

~UAL

r

2kHl.5kHz

50

=

MOOE

1 kHz

1_'"

40

~

30

400 Hz
200 Hz

I-IF

10~Hz

20
DUAL MODE
RAV=O. CBW=O
VSW\NG = 200mVRMS

10

o

~
o

0.5

1

o
15

2

2.5

3

3.5

4

4.5

5

5.5

6

1.5

2.5

SUPPLY VOLTAGE (V)

3.5

4.5

5.5

SUPPLY VOLTAGE (V)

Supply Current vs Temperature

PSRR vs Supply Voltage
80
70

BT'!i0E
60

1-,

,."

V ,..,...,.,

DUAL JOOE

......, ,
-,
'I'-.

V

50

...=

~

40

-

-;; ;.....:

~

GAIN =46 dB
(RAV=O!l. C,w=O pF)

30

~Tr-40'C

20
Vcc=3V
r-NOSrAL

o
-50

DUAL MOOE
F=l kHz

10

-25

75

25
50
TEMPERATURE

100

1.5

2.25

>
~
~
~
~
~

c
u
c

V

1.75
1.5

V

1.25

V

V

L

1 kHz

/

o

0.5

1

1.5

2

2.5

=
z

50

~

40

0

~

,10kHZ

AOOHZ

30
20
10

0.25

o

II

60

I..CH"t' CI·B

0.5

5.5

70

/

0.75

3.5
4.5
SUPPLY VOLTAGE (V)

BO

V

2.5

2.5

Separation vs Supply Voltage

DC Output vs Supply Voltage
3
2.75

I

VSWING= 20DmVRMS

o

125

GAIN =34 dB
(RAV = 240!!. Cow = 270 pF)

3

3.5

4

4.5

5

5.5

o

6

1.5

SUPPLY VOLTAGE

DulL MDDE
CH·A TO CH·B
Vour 200 mV
1

2.5

3
3,5
4
4.5
SUPPLY VOLTAGE (V)

5.5
TLlH/6754-4

1-71

,...
M

co

:::E

Typical Performance Characteristics

....I

(Continued)

Separation vs Frequency

Power Output vs Supply Voltage

BO

riInTTIr--,-rTTnmr--r-rrnTm--,

10

t--+t+Ht1-+-HJ-I++HIIII+-+++
111-I++H11l----l
~),WjL

I - -I - - BTL. RL=Bn

~

~

50

~-W~~~~t:tt~~;;~~~~~
1./
GAIN-46dB
r-...;;:

i

0.2

"

0.1

rifHtHr--+-rtt~t-+-4-~~--4

"

~~1Hr~_+-rt(tR'Hv=HOtn_.c~,w~=~O~PhFj~#--4

40

30

~

1/

60 H-H-H++-+-+(RAV=240n. C,w=210pFj
;
z

~UAL.

0.5

I 11111

~

V

/
)1//

~

V
/

.......-r

RL=4n

r-

,....

.........r

~RLJn- r -

V-

0

~

0.05

./

III
DUAL MODE
Vee = 3V. CH-A TO CH-B -ttffii--t--t-t-tt1-ttt---t
Your =2~~1 mV

10

o

~~Ull__~~Uliil--L~~~~

20

50 100

200

500 lK 2K
FREOUENCY (Hzj

5K

10K

z

~

20K

1.5

GAIN=46 dB
(RAyOn, Caw

o pFj

JJJlilJ

111111
111111

GAIN'~34

~

0.5

~

0.2

~
~

0.1
0.05

DUAL MODE
50 100 200

0.01
-50

500 lK 2K
5K 10K 20K SDK lOOK
FREQUENCY (Hzj

Gain vs Frequency

m

z

~

BTL M DE
Vee = 3V. Rl = au
THO=i O%

0.02

Vcc-3V

20

80
15
10
65
60
55
50
45
40
35
30
25
20
15
10

5.5

~

dB

IJ

o

3.5
4.5
SUPPLY VOLTAGE (V)

~

JJilljJ

(RAV=240n, CBw=270 pF)

10

2.5

10

Jll

....

f=1kHz
THD=10%

Power Output vs Temperature

I II

II'"

II

0.01

Gain vs Frequency
BO
15
10
65
60
55
50
45
40
35
30
25
20
IS

'1

0.02

I

-25

25
50
15
TEMPERATURE ('C)

100

125

500

1000

Bandwidth vs BW Capacitance
50

illIl ..1J II
1111 ..1JJJ

45
40

,

35

IIII

'"'"
'"

J11

~

1111

0

:
z

I'..

30
25

'\

20

~ 15
10
DUAL MODE

Vcc=3V

Vcc=3V, RL=40

_r~(~~~~-r~~r-t+t»Hfr-+++Hm
o ~~~-L~~W--L~Ull~~~WW
20

50 100200

GAIN=46dB

o

500 lK 2K
5K 10K 20K SDK lOOK
FREQUENCY (Hzj

10

20

50

100

200

BW CAPACITOR (pF)
Tl/H/6754-5

1-72

r

s::

Typical Performance Characteristics (Continued)

Co)

Dual Mode, RL =

Dual Mode, RL = 40 Distortion vs Frequency

~ 0.5

~

::z

GAIN 46 dB
(R.y_OO. c,w-o pF)

z

c

~

L

:;

.===

III

0.2

==

0.05
DUAL MODE. RL 40
Veeel.8 TO 6V
P.ul e 50 mW (CON ST.)

0.02

DUAL MODE, RL 811
Vee e l.8 TO 6V
PjU')j 5
ICO~STi)

0.02

0.01

Mf

0.01
20

50 100

200

500 lK
FREQUENCY (Hz)

2K

5K 10K

20K

20

Distortion vs Power Output (Note 2)

~

e
~

i'-

_

10kHz

--.
~

0.5
0.2

~

0.5

1' k;{;"

:;

0.2
1 kHz

=

~UAL MODE
Vee-3V. RL e 40

!llE

0.5
0.2
0.1

...... ~

0.02

0.2

~

-"

~rDe loj

:

.61

r""

0.2

0.5

1

Power Dissipation vs Power Output

,::=4V

.r

DUAL MODE
Vcc a 3V, RL=80
COWeR,ye O""

0.01
0.001 0.002 0.005 0.01 0.02 0.05 0.1
POWER OUTPUT (WATT)

0.5

1-

j;;

0.5

!

0.2

~

i

!llE

0.05

111111

1111

THO:'3%

THOel0%
Vee 6VVcc-5V
Vee 'ijv_

~

....Vee

0.1

lV'

Veee2V

0.05

~

~

~

"

0.05

Power Dissipation vs Power Output

~

10K

0.1

- C,tiRi'itllll
0.01
0.001 0.002 0.005 0.01 0.02 0.05 0.1
POWER OUTPUT (WATT)

z

5K

10 kHz

E

0.1

0.02

c

500 lK 2K
FREQUENCY 1Hz)

~

0.05

i

100 200

10

z

50

Distortion vs Power Output (Note 2)

10

~

I

GAirl'- 34 dB
•~
IRAY - 24011. COW e 270 p~)

0.1

0.05

/

IA'"

ilL

E

GAINe34 dB
(RAye2400. C,w-270 pF)

0.1

GAIN-46 dB
IR.y-OO. CoweD pF)

0.5

c

-+""

0.2

E

ao Distortion vs Frequency

10

10

:;;

...

CD

w

0.02

~

0.01
0.005

0.02
0.01
0.005

:O~~L

- n~~410~I'i'I,uHZ'
0.001
0.0010.0020.0050.01 0.020.05 0.1 0.2 0.5 1
POWER OUTPUT (WATT)

0.002

0.002

-DUAL MODE
- (BOTH DRIVE)
RL e 80. f~,1,kHZ

0.001
0.0010.0020,0050.01 0.02 0.05 0.' 0.2

0.5

1

POWER OUTPUT (WATT)
TL/H/6754-6

1-73

II

Typical Performance Characteristics (Continued)
BTL Mode, RL =
10

an Distortion vs Frequency

Device Dissipation vs Ambient Temperature
1.8

~
15

0.5

i;;

i

-

GAIN=46 dB
{RAV = on. Caw o pFI

~

1.6

i

.........

2i!

=

0.2

FREE AIR
90 0 C/W

1.4

z 1.2
C>
;:::

.......

.........

"- I'...

c;

GAIN=34 dB
(R,y = 240D. Cow = 270 pFI

0.1

w

u

F

~

O.B
0.6

0.05
0.4

BTL MODE. Rl 8D
Vee=l.B TO 6V

0.02

0.2

~Uli~OI~f (CO~STi)
20

50

100 200

500 lK 2K
FREQUENCY (Hz I

5K

o

10K 20K

Distortion vs Power Output (Note 2)

o

10

20

30 40 50 60 70 BO
AMBIENT TEMPERATURE ('CI

90

100

Supply Current vs Power Output

10

1000
500
200

-;;~

~
15

0.5

:;;c;

0.2

~

~

100

~

z

i;;

=
=
=>

50

~

20

u

....

1 kHz

~

0.1

~

10

0.05
rBTL MODE
0.02

BTL MODE
Rl=-8fl
1=1 kHz

Vcc=3V, RL=8D
CBw=RAV=O

0.01
0.001 0.002

0.005 0.01 0.02
0.05 0.1
POWER OUTPUT (WATT)

0.2

0.5

II-

1
0.0010.0020.0050.01 0.02 0.05 0.1 0.2 0.5 1
POWER OUTPUT (WATT)

1

5

10

Power Dissipation vs Power Output
2
veeU
Vcc=5V

i

0.5

51

0.2

".

z

I!:

=
c;

0.1

i

0.05

....-::

~

;::;

Vee

Vee-3V

~r'
Vcc- 2V

4V

I

THO!3~

THD~1d,.o

0.02

BTL MODE
Rl=BII. 1=ll,~Hz
0.01
0.0010.0020.0050.010.02 0.05 0.1 0.2 0.5
POWER OUTPUT (WATT)

Nole 2: 1 kHz curve is measured wilh 400 Hz-30 kHz Filler.
1

TL/H/6754-7

1-74

Typical Applications
BTL Amplifier with Minimum Parts

O.33~
47 p.F

811

Av

+IN

2

3

+

VIN:].

101'~

10:t-----'
TL/H/6754-8

Av

~

52 dB, BW

POUT ~

~

250 Hz to 25 kHz

440 mW, RL

~

an

BTL Amplifier for Hi-Fi Quality

II

TLlH/6754-9

Av

~

40 dB, BW

POUT ~

~

20 Hz to 20 kHz

440 mW, RL

~

an

(Dynamic Range Over ao dB)

1-75

.,...
C')

~

Typical Applications

(Continued)

..J
Dual Amplifier for Hi-Fi Quality

AV
2

+IN

240n

VIN:}.

J-

22¥

1O

TLlH/6754-10
AV

~

34dB, BW

~

50 Hz to 20 kHz

POUT ~ 220 mWICh, RL ~ 4fi
(Dynamic Range Over 80 dB)

Low-Cost Power Amplifier (No Bootstrap)
O.33~F

P:r.--3V....:.·~
1 'I'"
+.1

+

10~~47~

r-. ; 16=-:1:, 5~':i14:1- :~8
13i:1- : :1;:2f-: ~>-vo
i:i1 :tId!.-: ,"iO,--,:.~...,47It I
BY' A,

Vs

+IN

~

LMB31

·12Dk

~-+~------~

VIN].
1O

J+---------'

TLlH/6754-11

POUT ~ 150 mW/Ch, BW ~ 300 Hzt035 kHz
BTL Mode is also possible
'For 3·cell applications, the 120k resistor should be changed to 20K.

1-76

.-----------------------------------------------------------------------,r
lM831 Circuit Description

Refer to the external component diagram and equivalent schematic.

The power supply is applied to Pin 9 and is filtered by resistor R1 and capacitor CBY on Pin 16. This filtered voltage at
Pin 16 is used to bias all of the LM831 circuits except the
power output stage. Resistor Ro generates a biasing current
that sets the output DC voltage for optimum output power
for any given supply voltage.

:s:::
co
Co)

.....

The capacitor CNF on Pin 2 provides unity DC gain for maximum DC accuracy.
02 provides voltage gain and the rest of the devices buffer
the output load from 02'S collector.
Bootstrapping of Pin 5 by CBS allows maximum output
swing and improved supply rejection.

Feedback is provided to the input transistor 01 emitter by
Rs and R7.

Rs is provided for bridge (BTL) operation.

External Component Diagram

CBWI-_-9'---,h Cc

L_~-l

r-~~~~~~~~~~~~~.,

Cs

RL

I

~II

I
I
I

~BTLLOAO'

fBTL

I
I

(CONNECT FOR BTL)

-------

VIN

AV

+IN

2

3

I
I
I
I
I
I

"V)-------'

TLlH/6754-12

II

1-77

LM831

r
i:

LM831 Equivalent Schematic

0)

....

~

0
=i'
n

c

;:;:

BOOTSTRAP (B)

120 '

~

BOOTSTRAP (A)

. , .

, .

fII

R2

50 II

..,n

> 5011
VSUPPLY

35011

-

-6'
0'
~

C'l
0

a:

::l

<:

CD

a

~'I

OUTPUT (A)

F

1

t08

6
SIGNAL GROUND

POWER GROUND (A)
TL/H/6754-13

External Components
Component

(Refer to External Component Diagram)
Comments

Min

Max

Co

Required to stabilize output stage.

0.33 fLF

1 fLF

Cc

Output coupling capacitors for Dual Mode. Sets a low-frequency pole in
the frequency response.
1
fL=--27TCcRL

100 fLF

10,000 fLF

CSS

Bootstrap capacitors. Sets a low-frequency pole in the power BW.
Recommended value is
1
CBS =
10-27T-fL -RL

22 fLF or
(short Pins
4 & 12 to 9)

470 fLF

Cs

Supply bypass. Larger values improve low-battery performance by
reducing supply ripple.

47 fLF

10,000 fLF

CSY

Filters the supply for improved low-voltage operation. Also sets
turn-on delay.

47 fLF

470 fLF

CNF

Sets a low-frequency response. Also affects turn-on delay.
1
fL =
27T-CNF-(RAV + 80)

10 fLF

100 fLF

0.1 fLF

1 fLF

In BTL Mode, CNF on Pin 15 can be reduced without affecting the
frequency response. However, the turn-on "POP" will be worsened.
CSTL

Used only in the Bridge Mode. Connects the output of the first amplifier to
the inverting input of the other through an internal resistor. Sets a lowfrequency pole in one-half the frequency response.
1
fL =
27T-CSTL-16k

CSW

Improves clipping waveform and sets the high-frequency bandwidth.
Works with an internal 16k resistor. (This equation applies for RAV "" O.
For 46 dB application, see BW-CBW curve.)
1
f H - 27T e Csw-16k

See table below

RAV

Used to reduce the gain and improve the distortion and Signal to noise. If
this is desired, Csw must also be used.

See table below

TypicalAv

CBW

RAV

Min

Max

46dB

Short

Open

4700 pF

40dB

82

100 pF

4700 pF

34dB

240

270 pF

4700 pF

28dB

560

500 pF

4700 pF

1-79

II

....
:I
CO)

Printed Circuit Layout for LM831 N (Foil Side View) Refer to External Component Diagram

...I

A-CH INPUT

GROUND
POWER SUPPLY

TLIH/6754-14

Note: Power ground pattern should be as wide as possible. Supply bypass capac"or should be as close to the IC as possible. Output compensation capac"ors

should also be close to the IC.

1-80

NatiOnal

~ Semiconductor
Corporation

DYNAMIC NOISE REDUCTION SYSTEM

LM832 Dynamic Noise Reduction System DNR®
General Description

Features

The LM832 is a stereo noise reduction circuit for use with
audio playback systems. The DNR system is noncom plementary, meaning it does not require encoded source material. The system is compatible with virtually all prerecorded
tapes and FM broadcasts. Psychoacoustic maSking, and an
adaptive bandwidth scheme allow the DNR to achieve 10
dB of noise reduction. DNR can save circuit board space
and cost because of the few additional components required.

Low voltage battery operation
III Non-complementary noise reduction, "single ended"
III Low cost external components, no critical matching
II Compatible with all prerecorded tapes and FM
II 10 dB effective tape noise reduction CCIR/ ARM
weighted
1\1 Wide supply range, 1.5V to 9V
II 150 mVrms input overload
III No royalty requirements
IJ Cascade connection for 17 dB noise reduction
III

The LM832 is optimized for low voltage operation with input
levels around 30 mVrms.
For higher input levels use the LM1894.

Applications
1/1 Headphone stereo

The

DNR~

Microcassette players
Radio cassette players
III Automotive radio/tape players

I]

system is licensed to National Semiconductor Corp. under U.S. patent 3,676,416

and 3,753,159.

iii

A trademark and licenSing agreement is required for the use of this product.

Order Number LM832M See NS Package M14A
Order Number LM832N See NS Package N14A

Application Circuit
L
INPUT
FROM SOURCE
SELECTOR
TAPE PREAMP, STEREO I
FM DEMODULATOR, MONO
AM DETECTOR, ETC.
SW

L

ie,-----------.,

r-------------------------------------~~~~~ME
CONTROL

C7
39 of

14

R3
2k
ON

/f!;R

OFF

i

SW

II

0.65V

40k

v+

C3

~220F

Cl
10 pF

+

R

R

sri~:~~ ---------------'

FROM
SELECTOR

C6
82lrpF

~~----------------------------------~~~~~ME
CONTROL

FIGURE 1. Component Hook-up for Stereo DNR System

1-81

TLlH/5176-1

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

Soldering Information
• Dual-In-Line Package
Soldering (10 seconds)
• Small Outline Package

10V

Power Dissipation (Note 1)

1.2W

Input Voltage

1.7 Vpp

Storage Temperature

-65 to + 150°C

Operating Temperature (Note 1)

Vapor Phase (60 seconds)

215°C

Infrared (15 seconds)

220°C

See AN-450 "Surface Mounting Methods and Their Effects
on Products Reliability" for other methods of soldering surface mount devices."

-40 to +85°

DC Electrical Characteristics TA =

25°CVcc = 3.0V

Symbol

Conditions

Parameter

260°C

VOP

Operating Voltage

Supply Voltage for Normal Operation

Icc{l)

Supply Current (1)

Pin 9 to GND 0.1 p.F, BW= Min, Note 2

Min

Typ

Max

1.5

3.0

9.0

Units
V

2.5

4.0

mA

ICc(2)

Supply Current (2)

DC GND Pin 9 with 2k, BW = Max, Note 2

5.0

8.0

mA

VIN(l)

Input Voltage (1)

Pin 2, Pin 13

0.20

0.36

0.5

V

VIN(2)

Input Voltage (2)

Pin6

0.50

0.65

0.8

V

VIN(3)

Input Voltage (3)

Pin9

0.50

0.65

0.8

V

VOUT(l)

Output Voltage (1)

Pin 4, Pin 11

0.20

0.35

0.50

V

VOUT(2)

Output Voltage (2)

Pin 5 Stereo Mode

0.15

0.28

0.40

V

VOUT(3)

Output Voltage (3)

Pin 5 Monaural Mode, DC Ground Pin 14

0.10

0.20

0.30

V

VOUT(4)

Output Voltage (4)

Pin8

0.25

0.40

0.60

V

VOUT(5)

Output Voltage (5)

Pin 10 BW=Max, Note 2

1.00

1.27

1.50

V

VOUT(6)

Output Voltage (6)

Pin 10 BW = Min, Note 2

0.50

0.65

0.75

V

Vos

Output DC Shift

Pin 4, PIN 11; Change BW Min to Max

1.0

3.0

mV

AC Electrical Characteristics
Symbol

I

Parameter

MAIN SIGNAL PATH (Note 3)

I

Conditions

I

Min

I

Typ

I

Max

I

Units

Av

Voltage Gain

VIN = 30 mVrms, f = 1 kHz, BW = Max, Note 2

-1.0

0.0

+1.0

dB

C.B.

Channel Balance

VIN = 30 mVrms, f = 1 kHz, BW = Max, Note 2

-1.0

0

+1.0

dB

fMIN

Min Bandwidth

0.1 p.F between Pin 9 - GND

600

1000

1500

Hz

fMAX
THD

Max Bandwidth

DC Ground Pin 9 with 2k

24

30

46

kHz

Distortion

VIN=30 mVrms, f= 1 kHz, BW= Max, Note 2

0.07

0.5

MVIN

Max Input Voltage

THD=3%, f=l kHz, BW= Max Note 2

120

150

SIN

Signal to Noise

REF=30 mVrms, BW=Max, CCIR/ARM

60

68

ZIN

Input Impedance

Pin 2, Pin 13

14

20

C.S.

Channel Separation

Ref = 30 mVrms, f = 1 kHz, BW = Max, Note 2

40

68

dB

VRIPPLE=50 mVrms, f= 100 Hz

40

55

dB

PSRR
PSRR
CONTROL PATH

%
mVrms
dB

26

kn

Avsum(l)

Summing Amp Gain (1)

VIN=30 mVrms at Rand L, f= 1 kHz

-3.0

-1.5

0.0

dB

Avsum(2)

Summing Amp Gain (2)

DC Ground Pin 14, f = 1 kHz

-9.0

-6.0

-3.0

dB

Av 1st

Gain Amp Gain

Pin6to Pin 8

25

30

35

dB

ZINlst

Input Impedance

Pin6

28

40

52

kn

AVPKD

Peak Detector Gain

AC In, DC Out; Pin 9 to Pin 10

25

30

35

VIV

ZINPKD

Input Impedance

Pin 9

500

800

1100

n

VRPKD

Output DC Change

Pin 10, Change BW Min to Max

0.5

0.62

0.8

V

Note 1: For operation in ambient temperature above 25°C, the device must be derated based on a 1500C maximum junction temperature and a thermal resistance

junction 10 ambien~ as follows: LM832N -90' c/w, LM832M-115° c/w.
Note 2: To force the DNR system into maximum bandwidth, connect a 2k resistor from pin 9 to GND. AC ground pin 9 or pin 6 to select minimum bandwidth. To
change minimum and maximum bandwidth, see Application Hints.

Nole 3: The maximum noise reduction CCIR/ARM weighled is aboul14 dB. This is accomplished by changing Ihe bandwidlh from maximum 10 minimum. In aclual
operation, minimum bandwidth is not selected, a nominal minimum bandwidth of about 2 kHz gives 10 dB of noise reduction. See Application Hints.
1-82

External Component Guide (See Figure 1)
PIN

Recommended
Value

Effect
Purpose

Remarks
Smaller

Larger

C1

10 ,..F

Power supply
decoupling

Poor supply
rejection

Better supply
rejection

Do not use less
than 10,..F

C2,C11

1,..F

Input coupling
capacitor

Increases
frequency of lowfrequency roll-off

Reduces
frequency of lowfrequency rOil-off

DC voltage at pin 2
and pin 13 is 0.35V

Establishment of Min
and Max Bandwidth

Bandwidth
becomes wider

Bandwidth
becomes narrower

See Note 4

Output coupling
capacitor

Increases
frequency of lowfrequency rOil-off

Reduces
frequency of lowfrequency rOil-off

DC voltage at pin 4
and pin 11 is 0.35V

C3,C10

22 nF for Stereo,
15 nF for mono

C4,C8

1,..F

1
f=--2'7TC2 RIN

f=

1
2'ITC4RLOAD

C5

C6

0.1,..F

820 pF

Works with R1 and R2
to set one of the lowfrequency corners
in control path
Works with input
resistance of pin 6
to set one of the
low-frequency
corners in the
control path

C7

39nF

Works with input
resistance of pin 9
to form part of
control path
frequency weighing

C9

1,..F

Sets attack time

R1,R2

Rj+R2=1 kn

R3

-2 kn

This voltage
divider sets
control path
sensitivity
Sets gain amp load
when DNR is OFF

Some high frequency
program material
may be attenuated

Same as
above

Bandwidth may
increase due
to low-frequency
inputs, causing
"Breathing"

Same as
above

f

1
2'7TCs (R1 + R2)

1.6 kHz

See Note 4

f

1
2'ITCsRpINS

4.8 kHz

See Note 4

Same as
above

Same as
above

Reduces attack
and decay time

Increases attack
and decay time

f

1
2'7TC7Rp1N7

4.8 kHz

See Note 4

-

Loads gain amp
output, may
cause distortion

-

See Note 4
Sensitivity should be set for
maximum noise reduction
and minimum audible
frequency program effect
on high

Max bandwidth
will be reduced

Note 4: The values of the control path filter components (C5. C6, C7, Cg, RI, R2) and the integrating capacitors (C3, CIO) should not be changed from the
recommended values unless the characteristics of the noise or program material differ substantially from that of FM or tape sources. Failure to use the correct
values may result in degraded performance, and therefore the application may not be approved for DNR trademark usage. Please contact National Semiconductor
for more information and technical assistance.

1-83

II

N

C')

~

Typical Performance Characteristics

-'

10

10
I
I

9

I
I

_f-'rT

f

I

E-10
'"
~ -20
~ -30
~ -40
~ -50
~ -60
z
~ -70

-

I I I
MINIMUMBW

f-f- _

I
I

1

I I
II

ll: - 50 H"i~Ht--t-i"!'tI1llt..,.1"t'!1'MH

-

MAXIMUM BW

~

~-BO rr~ffl--rtH~-1-r~m-;

ILlllJl1i
20

100

-90

lk
FREQUENCY (Hz)

TLlH/S176-2

TLlH/S176-4

FIGURE 4. Power supply
rejection ratio vs frequency

c

0.9
0.8
0.7
0.6
~
Q
0.5

V,N = 30 mVrms 1=400 Hz
;REF 1 AT Vee = 3V AND MAX BW

4

10

...'"

-60
-70
-80
-90
20

100

lk

10k

20

lOOk

~

TlIHIS176-7

-10

-20

FREQUENCY (Hz)

'"

:s

-i'i"lftin 4Oldj

r-

2.
~
~

50
40

'"

30

'"
'";::;
'"
:>

Vee =3.0V
VIN = 30 mVrms

60

z

c(

~ ~-0.8%)- I - -

--... J-,..

20

c(

10

o

@

30

-25

25

50

75

TEMPERATURE (Oe)
TLlH/5176-11

FIGURE 11. Change in main signal path
maximum bandwidth vs temperature
1-84

'"

~

20

IJ WITHOUT

~

10

'"z:

19 kHz
PllOT_

I

mrM

111111111

100

TLlHIS176-9

80

40

o

10k

FIGURE 9. Frequency response
for various input levels

70

~

--'

z

TLlH/5176-B

FIGURE 8. Output vs frequency
and control path signal

Ii

50

:>::

co

-60
NOMINAL BW 1111111 I I
-70
OdB=30mVIIIIIII II
-80
20
100
lk
FREQUENCY (Hz)

10k

60

V,N- 10 dB
V,N- 20 dB
V,N - -30 dB

~ -30
~ -40
co
-50

!;

10k

FIGURE 7. THO vs
frequency

V,N-l0dB I
V,N -0 dB

o

C>

lk

Tl1HIS176-6

FIGURE 6. Output level
vs frequency
20
10

l-++l+lllI---l-+Hf+I

100

FREQUENCY (Hz)

FREQUENCY (Hz)
TLlH/5176-S

lk

1+l-ttttIt-t-Hrtffitt-ttt-tffiH

O.~ rrrm~:r:tl!I::!:nlrJ

FIGURE 5. Output level
change vs supply voltage

100

FUll8ANOWIDTH.
V,N =30mV

0.4
0.3
0.2

Vee (V)

~ -10

1

o odB _ 30 mVrms MAXIMUM BW
I 1111IllN.l1
-10
t--~:~:~~M IB~
-20
E.-3D
~ -40
~ -50

o

10k

TLlH/5176-3

-2 f-i- I - MINIMUM BW i- i - -

-16

lk

100

FREQUENCY (Hz)

10

-12
-14

~~w-~~~~~~~

20

10k

FIGURE 3. Channel separation
vs frequency

MAXIMUM BW

co -10

I-tlrtttttl-+H+Httt-t-ttftHH

- 60

~ -70 rt~ffi--rtHTIffl-i-rrtttm-i

MINIMUM BW

FIGURE 2. Supply current
vs supply voltage

:>

VRIPPlE =500 mvrms-t-t-ttttillH
NOMINAL BW

~ -40 rt~ffi--rtHTIffl-i-H~m-i

Vee (V)

~ -4
... -6
~ -8

~~~~~~rTnn~

~ -30 rr~ffi--rtH~-1-HHttm-;

-90
10

o

~ -10

~ -20 rr~ffl--rtH~~-H~m-;

'-' -BO

o

10

Vee =3.0V
V,N = 30 mvrms

o

MA~IM~M IBW r- I;:;;~

1-:- -

o

I
I

lk
10k
FREQUENCY (Hz)

lOOk

TlIHI5176-10

FIGURE 10. Gain of control
path vs frequency

.-----------------------------------------------------------------------------'r
31:
(XI

Circuit Operation
The LM832 has two signal paths, a main signal path and a
bandwidth control path. The main path is an audio low pass
filter comprised of a gm block with a variable current, and a
unity gain buffer. As seen in Figure 1, DC feedback constrains the low frequency gain to Av = -1. Above the cutoff
frequency of the filter, the output decreases at -6 dB/oct
due to the action of the 0.022 I-'F capacitor.
The purpose of the control path is to generate a bandwidth
control signal which replicates the ear's sensitivity to noise
in the presence of a tone. A single control path is used for
both channels to keep the stereo image from wandering.
This is done by adding the right and left channels together
in the summing amplifier of Figure 1. The Rl, R2 resistor
divider adjusts the incoming noise level to slightly open the
bandwidth of the low pass filter. Control path gain is about
60dB and is set by the gain amplifier and peak detector
gain. This large gain is needed to ensure the low pass filter
bandwidth can be opened by very low noise floors. The capacitors between the summing amplifier output and the
peak detector input determine the frequency weighting as
shown in the typical performance curves. The 1 I-'F capacitor at pin 10, in conjunction with internal resistors, sets the
attack and decay times. The voltage is converted into a
proportional current which is fed into the gm blocks. The
bandwidth sensitivity to gm current is 70 HZ/I-'A. In FM
stereo applications a 19 kHz pilot filter is inserted between
pin 8 and pin 9 as shown in Figure 16.

acts as an integrator and is unable to detect it. Because of
this, signals of sufficient energy to mask noise open the
bandwidth to 90% of the maximum value in less than 1 ms.
Reducing the bandwidth to within 10% of its minimum value
is done in about 60 ms: long enough to allow the ambience
of the music to pass through, but not so long as to allow the
noise floor to become audible.
3. Reducing the audio bandwidth reduces the audibility of
noise. Audibility of noise is dependent on noise spectrum, or
how the noise energy is distributed with frequency. Depending on the tape and the recorder equalization, tape noise
spectrum may be slightly rolled off with frequency on a per
octave basis. The ear sensitivity on the other hand greatly
increases between 2 kHz and 10kHz. Noise in this region is
extremely audible. The DNR system low pass filters this
noise. Low frequency music will not appreciably open the
DNR bandwidth, thus 2 kHz to 20 kHz noise is not heard.

W
N

Application Hints
The DNR system should always be placed before tone and
volume controls as shown in Figure 1. This is because any
adjustment of these controls would alter the noise floor
seen by the DNR control path. The sensitivity resistors Rl
and R2 may need to be switched with the input selector,
depending on the noise floors of different sources, i.e., tape,
FM, phono. To determine the value of Rl and R2 in a tape
system for instance; apply tape noise (no program material)
and adjust the ratio of Rl and R2 to slightly open the bandwidth of the main signal path. This can easily be done by
viewing the capacitor voltage of pin 10 with an oscilloscope,
or by using the circuit of Figure 12. This circuit gives an LED
display of the voltage on the peak detector capacitor. Adjust
the values of Rl and R2 (their sum is always 1 kO) to light
the LEOs of pin 1 and pin 18. The LED bar graph does not
indicate signal level, but rather instantaneous bandwidth of
the two filters; it should not be used as a signal-level indicator. For greater flexibility in setting the bandwidth sensitivity,
R 1 and R2 could be replaced by a 1 kO potentiometer.
To change the minimum and maximum value of bandwidth,
the integrating capacitors, C3 and Cl0, can be scaled up or
down. Since the bandwidth is inversely proportional to the
capacitance, changing this 0.022 I-'F capacitor to 0.015 I-'F
will change the typical bandwidth from 1 kHz-30 kHz to 1.5
kHz-44 kHz. With C3 and Cl0 set at 0.022 I-'F, the maximum bandwidth is typically 30 kHz. A double pole double
throw switch can be used to completely bypass DNR.
The capacitor on pin lOin conjunction with internal resistors
sets the attack and decay times. The attack time can be
altered by changing the size of C9. Decay times can be
decreased by paralleling a resistor with Cg, and increased
by increasing the value of Cg.
When measuring the amount of noise reduction of DNR in a
cassette tape system, the frequency response of the cassette should be flat to 10 kHz. The CCIR weighting network
has substantial gain to 8 kHz and any additional roll-off in
the cassette player will reduce the benefits of DNR noise
reduction. A typical signal-to-noise measurement circuit is
shown in Figure 13. The DNR system should be switched
from maximum bandwidth to nominal bandwidth with tape
noise as a Signal source. The reduction in measured noise is
the signal-to-noise ratio improvement.

Normal methods of evaluating the frequency response of
the LM 832 can be misleading if the input signal is also
applied to the control path. Since the control path includes a
frequency weighting network, a constant amplitude but varying frequency input signal will change the audio signal path
bandwidth in a non-linear fashion. Measurements of the audio signal path frequency response will therefore be in error
since the bandwidth will be changing during the measurement. See Figure 9 for an example of the misleading results
that can be obtained from this measurement approach. Although the frequency response is always flat below a single
high-frequency pole, the lower curves do not resemble single pole responses at all.
A more accurate evaluation of the frequency response can
be seen in Figure 8. In this case the main signal path is
frequency swept while, the control path has a constant frequency applied. It can be seen that different control path
frequencies each give a distinctive gain roll-off.

PSYCHOACOUSTIC BASICS
The dynamic noise reduction system is a low pass filter that
has a variable bandwidth of 1 kHz to 30 kHz, dependent on
music spectrum. The DNR system operates on three principles of psychoacoustics.
1. Music and speech can mask noise. In the absence of
source material, background noise can be very audible.
However, when music or speech is present, the human ear
is less able to distinguish the noise-the source material is
said to mask the noise. The degree of masking is dependent on the amplitude and spectral content (frequencies) of
the source material, but in general multiple tones around 1
kHz are capable of providing excellent masking of noise
over a very wide frequency range.
2. The ear cannot detect distortion for less than 1 ms. On a
transient basis, if distortion occurs in less than 1 ms, the ear

1-85

II

Application Hints (Continued)

620

Tl/H/5176-12

FIGURE 12. Bar Graph Display of Peak Detector Voltage

Tl/H/5176-13

FIGURE 13. Technique for Measuring SIN Improvement of the DNR System
CASCADE CONNECTION
Additional noise reduction can be obtained by cascading the
DNR filters. With two filters cascaded the rolloff is 12 dB per
octave. For proper operating bandwidth the capacitors on
pin 3 and 12 are changed to 15 nF. The resulting noise
reduction is about 17 dB.

L INPUT

---i

Figure 15 shows the monaural cascade connection. Note
that pin 14 is grounded so only the pin 2 input is fed to the
summing amp and therefore the control path.
Figure 14 shows the stereo cascade connection. Note that
pin 14 is open circuit as in normal stereo operation.

+

1""

r----------lOUTPUT

fll""
+

11

10

..

v+--.~-_r~-~-~F---f~-~-~F_---

Rl·

I . . . . - - -_ _ _ _ _ _ R OUTPUT

'Rl + R2 = 1 kn (refer to application hints)

FIGURE 14. Stereo Cascade Connection

1-86

TlIH/5176-14

Application Hints (Continued)
r--------------OUTPUT

2k

39

nF

ON

OFFfNR
SW

~~--~~--~--~~--~--~~--~~

v'-I--'"

I N P U T - - - - - -.......

'R1 + R2

~

TLlH/5176-15

1 kU (refer to application hints)

FIGURE 15. Monaural Cascade Connection
FMSTEREO
When using the DNR system with FM stereo as the audio
source, it is important to eliminate the ultrasonic frequencies
that accompany the audio. If the radio has a multiplex filter
to remove the ultrasonics there will be no problem.
This filtering can be done at the output of the demodulator,
before the DNR system, or in the DNR system control path.

Standard audio multiplex filters are available for use at the
output of the demodulator from several filter companies.
Figure 16 shows the additional components L1, C15 and
C16 that are added to the control path for FM stereo applications. The coil must be tuned to 19 kHz, the FM pilot
frequency.

lr-l-"F---------4~-:-:I:-~F-H--- LOUTPUT
+
2k
ON

11

OFF /@R

i
FROM FM MPX

-:r 22nF

'Rl+R2~1

SW

KU

(rafer to application hints)

L..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ROUTPUT

TLlH/5176-16

FIGURE 16. FM Stereo Application
FOR FURTHER READING
Tape Noise Levels
1. "A Wide Range Dynamic Noise Reduction System"
Blackmer, 'dB' Magazine, August-September 1972, Volume
6, #8.

Noise Masking
1. "Masking and Discrimination", Bos and De Boer, JAES,
Volume 39, #4, 1966.
2. "The Masking of Pure Tones and Speech by White
Noise", Hawkins and Stevens, JAES, Volume 22, # 1, 1950.
3. "Sound System Engineering", Davis, Howard W. 8ams
and Co.
4. "High Quality Sound Reproduction", Moir, Chapman Hall,
1960.
5. "Speech and Hearing in Communication", Fletcher, Van
Nostrand, 1953.

2. "Dolby B-Type Noise Reduction System", Berkowitz and
Gundry, Sert Journal, May.June 1974, Volume 8.
3. "Cassette vs Elcaset vs Open Reel", Toole, Audioscene
Canada, April 1978.
4. "CCIR/ARM: A Practical Noise Measurement Method",
Dolby, Robinson, Gundry, JAES, 1978.

1-87

II

LM832 Simple Circuit Schematic

t:;

~{~

6

t----------+~~~-oz

r----+--,I---..-,

;:

~~~~

____________

~

____

~~

______

if -

~~

teI:Z:~

t---------------~~~

r--__________+Lr:I J:..l g
>
ci

1-88

r-------------------------------------------------------------------------, r
3:
oCo)

NatiOnal

~ Semiconductor

~

U1

Corporation

.......
r
3:
~

oCo)

LM 1035/LM 1036 Dual DC Operated
Tone/Volume/Balance Circuits

CD

General Description

Features

The LM1035/LM1036 is a DC controlled tone (bass/treble),
volume and balance circuit for stereo applications in car radio, TV and audio systems. An additional control input allows loudness compensation to be simply effected.

•
•
•
•
•

Wide supply voltage range, BV to lBV
Large volume control range, 75 dB typical
Tone control, ± 15 dB typical
Channel separation, 75 dB typical
Low distortion, 0.06% typical for an input level of
1 Vrms (0.3 Vrms for LM1036)
• High signal to noise, 80 dB typical for an input level of
1 Vrms (0.3 Vrms for LM1036)
• Few external components required

Four control inputs provide control of the bass, treble, balance and volume functions through application of DC voltages from a remote control system or, alternatively, from
four potentiometers which may be biased from a zener regulated supply provided on the circuit.
Each tone response is defined by a single capacitor chosen
to give the desired characteristic.

Block and Connection Diagram
Dual-In-Line Package
INTERNAL SUPPLY DECOUPLE....1.I==:::;-'-::;--i
INPUT 1
18 TREBLE CAPACITOR 2

TREBLE CAPACITOR 1

17 ZENER VOLTAGE

TREBLE CONTROL INPUT
AC BYPASS 1

AC BYPASS 2

BASS CAPACITOR 1

BASS CAPACITOR 2

LOUDNESS COMPENSATION
CONTROL INPUT

BASS CONTROL INPUT

OUTPUT 1
BALANCE CONTROL INPUT

OUTPUT 2
- - _

-

+L-___
--' ....lI'"

VOLUME CONTROL INPUT

II

11 Vee

GND 10
TOP VIEW

Order Number LM1035N or LM1036N
See NS Package Number N20A

1-89

TL/H/5142-1

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
LM1036
LM1035

16V
20V

Control Pin Voltage (Pins 4, 7, 9, 12, 14)

Vee

Operating Temperature Range

O"Cto +70"C

Storage Temperature Range

-65'C to + 150'C

Power Dissipation

1W

Lead Temp. (Soldering, 10 seconds)

260'C

Electrical Characteristics Vee= 12V, TA = 25'C (unless otherwise stated)
Parameter
Supply Voltage Range

Max

Units

LM1036

9

16

V

LM1035

8

18

V

45

mA

5

V
mA

Min

Conditions
Pin 11

I
l

Supply Current

35

Zener Regulated Output
Voltage
Current

Pin 17

Maximum Output Voltage
LM1036

Pins 8,13; 1= 1 kHz
Vee = 9V, Maximum Gain
Vee=12V

Maximum Output Voltage
LM1035

Typ

5.4

Pins 8,13; 1= 1 kHz
Vee=8V
Vee=12V
Vee=18V

0.8
1.0

Vrms
Vrms

1.3
2.5
3.5

Vrms
Vrms
Vrms

1.3

1.1
1.6

Vrms
Vrms

0.8

2

Maximum Input Voltage
LM1036 (Note 1)

Pins 2, 19; 1=1 kHz, Vee=9V
Flat Response, Vcc= 12V
Gain=-10dB

Maximum Input Voltage
LM1035 (Note 1)

Pins 2, 19;1=1 kHz
Flat Response

2

2.5

Vrms

20

30

ko.

Input Resistance

Pins 2, 19; 1= 1 kHz

Output Resistance

Pins 8, 13;1 = 1 kHz

Maximum Gain

V(Pin 12)=V(Pin 17);
f= 1 kHz

Volume Control Range

1=1 kHz

l

I

20

0.

-2

0

LM1036

70

75

dB

LM1035

70

80

dB

Gain Tracking
Channel1-Channel 2

f= 1 kHz
o dB through -40 dB
-40 dB through -60dB

Balance Control Range

Pins 8,13; 1= 1 kHz

1
2

2

3

dB

dB
dB

1
-26

-20

dB
dB

Bass Control Range
(Note 2)

1=40 Hz, Cb=0.39 ",F
V(Pin 14)=V(Pin 17)
V(Pin 14)=OV

12
-12

15
-15

18
-18

dB
dB

Treble Control Range
(Note 2)

1= 16 kHz, Ct,=0.01 ",F
V(Pin 4) = V(Pin 17)
V(Pin4)=OV

12
-12

15
-15

18
-18

dB
dB

Total Harmonic Distortion
LM1036

1=1 kHz, VIN=0.3Vrms
Gain=OdB
Gain= -30 dB

0.06
0.03

0.3

%
%

Total Harmonic Distortion
LM1035

1=1 kHz, VIN=1 Vrms
Maximum Gain

0.05

0.2

%

1·90

....
s::
......
oCo)

Electrical Characteristics Vcc= 12V, TA = 25'C (unless otherwise stated) (Continued)
Parameter

Conditions

Channel Separation

/= 1 kHz,
Maximum Gain

Signal/Noise Ratio
LM1036

Unweighted 100 Hz-20 kHz
Maximum Gain, 0 dB = 0.3 Vrms
CCIRt ARM (Note 3)
Gain = 0 dB, VIN = 0.3 Vrms
Gain = - 20 dB, VIN = 1.0 Vrms

Signal/Noise Ratio
LM1035

LM1036

Min

Typ

Units

U1
.......

60

75

dB

75

dB

s::
......

80

dB

79
72

dB
dB

80

dB

80
64

dB
dB

LM1035

Unweighted 100 Hz-20 kHz
Maximum Gain, 0 dB = 1 Vrms
CCIRt ARM (Note 3)
Gain=O dB
Gain= -20 dB

75

76

Max

Output Noise Voltage at
Minimum Gain

CCIRtARM
(Note 3)

LM1036

10

16

/LV

LM1035

25

35

/LV

Supply Ripple Rejection

200 mVrms,
1 kHz Ripple

LM1036

35

LM1035

50

Pins 4,7,9,12,14 (V=OV)

-0.6

Frequency Response

-1 dB (Flat Response
20 HZ-16 kHz)

250

oCo)

Q)

dB
dB

40

Control Input Currents

....

-2.5

/LA
kHz

Note 1: The maximum permissible input level is dependent on tone and volume settings. See Application Notes.
Note 2: The tone control range is defined by capacitors Cb and Ct. See Application Notes.

Note 3: Gaussian noise, measured over a period of 50 ms per channel, with a CCIR filter referenced to 2 kHz and an average·responding meter.

II

1-91

Typical Performance Characteristics
Volume Control
Characteristics

iii

~

/

-20

!z

Balance Control
Characteristic

;;; -8

~~::mv_

-16
-20

~~

-80

-24

a

4

II

\

-10

l/

-15

/

/

CUT
40 Hz OR 16 kHz

20 ,---,--,-,-.--,-,-.-,-,
151o.::c+-l~

15

18

10 I--~C-+

!z
f-+-~F-+-+-~d-~

-5

iii

-5

1..

~ 18

~

1.6

I;

I :~
.... 1.0

6

8

"
I

ro ~

U ffi

.

zo
15

10

:::::::b.!,o Hz
16 kHz ......
~

-5

o

~

.

~

iz

\

o

~
....
S
4

Ii

70

...

60

ifw

100

...... ~ 1-00 .....

..........

~

z

40

FLAT FREQUENCY RESPONSE
BALANCED GAINS

30
20

0.2

....

-

10

~ 0.1

~

~tl

-20

-40
-60
GAIN (dB)

20k

FLAT FREQUENC:Ii~
RESPONSE
;:
BALANCED GAINS ~ ..(! .t
MAXIMUM GAIN ~
~;=rYcc=l2V
.J.~~

1=
'" 0.05
0.02

~;~

~~

I

0.81

Vcc=9V

a

100
500
5k
FREQUENCY 1Hz}

THO vs Input Voltage-LM1036
1.0

40

20

20k

5k

c

5

0.5

30

500

iii
z 50

TONE CONTROLS FLAT
50 BALANCED GAINS
CCIR FILTER

a
V7-CONTROL VOLTAGE (V)

!

BO

1!!

60

!:!i

\.

PIN 7 CONNECTED TO PIN 12

20

Output Noise Voltage
vs Gain-LM1036

w

..... ""

90

-

Loudness Control
Characteristic

/

......
CONOITIONS~

Channel Separation vs
Frequency

0.81 1=1 kHz
FLAT FREQUENCY RESPONSE
BALANCED GAINS
0.00
10
0 -10 -20 -30 -40 -50
GAIN (dB)

m ~ ~

./

.... t-'

......

FREQUENCY 1Hz}

.... 0.02

VIN-l00 mV
TON CONTROLS FLAT

-

-60

20k

" .....

~0.03

SUPPLY VOLTAGE (V)

25

5k

,

0.04

:z:

LUl036

I

500

~

0.05

LUl035

100

THO vs Gain

I"

/

'"j!:2J)

-50

V

...... 1--.

-

....

...... r--.,

---

FREQUENCY (Hz)

,.

:S~~GAINS

le2.2

-40

0.06

flAT FREQUENCY

-20

~ -30

~"---'~

20

GAIN=-10dB

iu

-10

!

-15 I-"'-+-+-f-+-+-f-+-~
- 20 '--.l..-.l-'--.l..-.l-'--.l..-.LJ

Input Signal Handling vs
Supply Voltage

2.8

~

a

10

k::-+-H-I---l-+-+-+...,

-10

~2.6 f= 1 kHz

i

-5

Loudness Compensated
Volume Characteristic

-15

!....

~

Tone Characteristic (Gain
vs Frequency)
20 ,---,-,-.---,-,-r--,-.,..,

- 20 '--.l-L....I_L....L---L----'---L-'
20
100
500
5k
20k
FREQUENCY (Hz)

~

J

0123456
V4 OR VI4-CONTROL VOUAGE IV}

-10 t--t.'I-t-

a:

I

!

I

/

024
V9 - CONTROL VOLTAGE (V)

Tone Characteristic (Gain
vs Frequency)

I

"1\\

/

BOOST
40 Hz OR 16 kHz

10

CHANNEL 1

-28

V12 - CONTROL VOLTAGE (V)

~

/

;- -12

iii

j

-60

1

CHANNEL 27'" "

-4

I
I

-40

Tone Control Characteristic
15

-80

0.00

0.0

0.2
0.4
0.6
0.8
INPUT VOLTAGE (Vlms)

1.0
TL/H/5142-2

1-92

r-

Typical Performance Characteristics

s::
.....

(Continued)

o

IN
U1

......

Output NOise Voltage
vs Gain-LM1035

THD vs Input Voltage-LM1035

90

r.....
1'\
70
.3
... 60 r.....

]'

,

80

--'

50

...

40

0

30

0-

20

0

>

:==>=>
0

,

1=10

Vee = 12V
.........

"-

VI

z

BW=20 kHz
FLAT FREQUENCY
RESPONSE
BALACED GAINS

~Hz

r-

s::
.....
o

IN

a>

1'\ 1\

(!)

;:!:

0.50

r-....

Vee -8V .........
1'--....

I~ 1~0 ~z

r--

III

I I

10

FLAT FREQUENCY RESPONSE
BALANCED GAINS

0
0

-40

-20

-60

-80

0.25

0.75

1.25

1.75

2.25

INPUT VOLTAGE (Vrms)

GAIN (dB)

TL/H/5142-21

TLlH/5142-20

Application Notes
TONE RESPONSE

LOUDNESS COMPENSATION
A simple loudness compensation may be effected by applying a DC control voltage to pin 7. This operates on the tone
control stages to produce an additional boost limited by the
maximum boost defined by Cb and Ct. There is no loudness
compensation when pin 7 is connected to pin 17. Pin 7 can
be connected to pin 12 to give the loudness compensated
volume characteristic as illustrated without the addition of
further external components. (Tone settings are for flat response, Cb and Ct as given in Application Circuit.) Modification to the loudness characteristic is possible by changing
the capacitors Cb and Ct for a different basic response or,
by a resistor network between pins 7 and 12 for a different
threshold and slope.

The maximum boost and cut can be optimized for individual
applications by selection of the appropriate values of Ct (treble) and Cb (bass).
The tone responses are defined by the relationships:
1 + 0.00065(1 - ab)
jez>Cb
Bass Response = ---!.::.::!!...-1 + 0.00065ab
jez>Cb
Treble Response = 1 + jez>5500(1 - at)Ct
1 + jez>5500atCt
Where ab=at=O for maximum bass and treble boost respectively and ab = at = 1 for maximum cut.

SIGNAL HANDLING
The volume control function of the LM1036 is carried out in
two stages, controlled by the DC voltage on pin 12, to improve signal handling capability and provide a reduction of
output noise level at reduced gain. The first stage is before
the tone control processing and provides an initial 15 dB of
gain reduction, so ensuring that the tone sections are not
overdriven by large input levels when operating with a low
volume setting. Any combination of tone and volume settings may be used provided the output level does not exceed 1 Vrms, Vcc=12V (0.8 Vrms, Vcc=9V). At reduced
gain ( < - 6 dB) the input stage will overload if the input level
exceeds 1.6 Vrms, Vcc=12V (1.1 Vrms, Vcc=9V). As
there is volume control on the input stages, the inputs may
be operated with a lower overload margin than would otherwise be acceptable, allowing a possible improvement in signal to noise ratio.

For the values of Cb and Ct of 0.39 /LF and 0.01 /LF as
shown in the Application Circuit, 15 dB of boost or cut is
obtained at 40 Hz and 16 kHz.
ZENER VOLTAGE
A zener voltage (pin 17=5.4V) is provided which may be
used to bias the control potentiometers. Setting a DC level
of one half of the zener voltage on the control inputs, pins 4,
9, and 14, results in the balanced gain and flat response
condition. Typical spread on the zener voltage is ± 100 mV
and this must be taken into account if control signals are
used which are not referenced to the zener voltage. If this is
the case, then they will need to be derived with similar accuracy.

1-93

II

U)
C")
C)

..-

r------------------------------------------------------------------------------------------,
Application Circuit

::::iE
..J

.....
II)
C")
C)

47k

npp.

..-

:i

II

0.01 pF

..J

t-~M""< 47k

BASS CONTROL

;J;D.22 PF

lD pF

r-----.....JVI-IIr+< 47k

D.47 pF

VOLUME CONTROL

LM1D36N
47#

P IN~

LOUDNESS
COMPENSATION

O.47pF

BALANCE CONTROL

T

OUTPUT 1 47k

t-------~~--------+<47k ~~~~~L

TL/H/5142-3

Applications Information
Figures 2 and 3 show the effect of changing the response
defining capacitors Cj and Cb to 2Ct, Cb/2 and 4Cj, Cb/4
respectively, giving increased tone control ranges. The values of the bypass capacitors may become significant and
affect the lower frequencies in the bass response curves.

OBTAINING MODIFIED RESPONSE CURVES
The LM1036 is a dual DC controlled bass, treble, balance
and volume integrated circuit ideal for stereo audio systems.
In the various applications where the LM1036 can be used,
there may be requirements for responses different to those
of the standard application circuit given in the data sheet.
This application section details some of the simple variations possible on the standard responses, to assist the
choice of optimum characteristics for particular applications.

20
15
10

!

j!1

TONE CONTROLS

-15
-20

~

15
10

!

.
.

-10
-15
5k

100

2.0

"r-

2Ct

500

5k

1.4
0.7
0.0

:!!

~

i

~

:3

20k

5.4
4.7

~g.EASEo CONTROL RANGEI--'

ljf-""

fo- 1-......
~

5

..

J~

f$Io~

I

0

m

-5

.....:

-10

-~
1-"-:

t--

-15
I-"
-20
20
100

:3

100

;::-.-

C,/2

;§

;i

2.7 Iil

TLlH/5142-5

2.7 Iil
2.0 ~
1.4
0.7 ~
0.0

-5

~~

FIGURE 2. Tone Characteristic (Gain vs Frequency)

i

!

3.•

,,~

fo-~

i

4.0 •

~

""'liI

g

FREQUENCY IH,!

a

10

~
-:tI)

20

5.4
4.7
4.0
~
3.4 !il

15

rr-

-10 --I-

20
20

--

4.7

~

"' -5

Summarizing the relationship given in the data sheet, basically for an increase in the treble control range Cj must be
increased, and for increased bass range Cb must be reduced.
Figure 1 shows the typical tone response obtained in the
standard application circuit. (Cj=O.Ol ,..F, Cb=O.39 ,..Fl.
Response curves are given for various amounts of boost
and cut.

5.4

INCREASED CONTROL RANGE "

~
,~

~t-

Co/4 4Ct

500

I""'-

5k

4.0
3.4
2.7
2.0
1.4
0.7
0.0

I
;§

!il

Iil

.~
~

0:
<

20k

fIIEQUENCY (H,)

20k

TL/H/5142-6

FREQUENCY (Hz)

FIGURE 3. Tone Characteristic (Gain vs Frequency)

TUH/5142-4

FIGURE 1. Tone Characteristic (Gain vs Frequency)

1-94

,-----------------------------------------------------------------------------, r

Applications Information

(Continued)
for greater control range also has the effect of flattening the
tone control extremes and this may be utilized, with or without additional modification as outlined above, for the most
suitable tone control range and response shape.

Figure 4 shows the effect of changing Ct and Cb in the
opposite direction to Ct/2, 2Cb respectively giving reduced
control ranges. The various results corresponding to the different Ct and Cb values may be mixed if it is required to give
a particular emphasis to, for example, the bass control. The
particular case with Cb/2, Ct is illustrated in Figure 5.

Other Advantages of DC Controls
The DC controls make the addition of other features easy to
arrange. For example, the negative-going peaks of the output amplifiers may be detected below a certain level, and
used to bias back the bass control from a high boost condition, to prevent overloading the speaker with low frequency
components.

Restriction of Tone Control Action at High or Low Frequencies
It may be desired in some applications to level off the tone
responses above or below certain frequencies for example
to reduce high frequence noise.
This may be achieved for the treble response by including a
resistor in series with Ct. The treble boost and cut will be 3
dB less than the standard circuit when R = Xc.
A similar effect may be obtained for the bass response by
reducing the value of the AC bypass capacitors on pins 5
(channel 1) and 16 (channel 2). The internal resistance at
these pins is 1.3 kO and the bass boost! cut will be approximately 3 dB less with Xc at this value. An example of such
modified response curves is shown in Figure 6. The input
coupling capacitors may also modify the low frequency response.
It will be seen from Figures 2 and :3 that modifying Ct and Cb

20
15
REDUCED CONTROL RANGE

10

~~

iii"

5

~

0

:s

-5
-10
-15
-20

5.4
4.7
4.0
3.4
2.7
2.0
1.4
0.7
0.0

---

~

liiio.

..... lef.-'

I--::: ~

~t--

~~

I'§

"

2 Cb C,/2

20

100
500
FREQUENCY (Hz)

5k

'"
'"
;:

20 ....!-NCREASEO BASS CONTROL RANGE
15 ___
'-

<

ID __ -

?!

,.!=i'"

~ :

~
J!

~

z

,....'"z

.. -5

~

tIe'

-.....;::....

f-"'""

~"""

1---1:;;::1"

~:

!

STANDARD

'"
:;:

-15
-20

'--....I.......I.......I.........I.......I.......I._.L....J.....I

20k

100

20

2.7 ~
J!
2.0 z

,....'"

c,,/2 Ct
5k
500
FREQUENCY (Hz)

:3

20k
TLlH/5142-B

FIGURE 5. Tone Characteristic (Gain vs Frequency)

10

~:

STANDARD APPliCATION CIRCUIT

II

RESPONSE=~r--

-

V

V

/~

-10 -=-.~ C.-D.39"
'"

-15

.-.-.-.-,-,-,--r-r,

ol--+-HI-+-+-f-+-H

MDDlFIED~I.--+--+--+-A-+--l
RESPONSE"

~f-

Ct=O.01I'F+l.2kU

car"'i"'!

I

~
~t--

I'..

r-r

-00

_20L-J-~L-J-J-~~~

20

100

500
FREQUENCY (Hz)

5k

en

1.4
0.7 z
'"
'" 0.0 :;:

:3

HIGH ~ND LDr FRIEQU\NCIESf-t7'

5

(,)

g

~~

'V
I-- .--

-10

~'-'-'-'-'-'-'--r'-'
REDUCING RESPONSE AT
10

r

s:::
....
o

5.4 z
4.7 ;!
?!
4.0 <
'"
3.4 !=i

TL/H/5142-7

~

(,)

U1
......

LOUDNESS CONTROL
The loudness control is achieved through control of the
tone sections by the voltage applied to pin 7; therefore, the
tone and loudness functions are not independent. There is
normally 1 dB more bass than treble boost (40 Hz-16 kHz)
with loudness control in the standard circuit. If a greater
difference is desired, it is necessary to introduce an offset
by means of Ct or Cb or by changing the nominal control
voltage ranges.
Figure 7 shows the typical loudness curves obtained in the
standard application circuit at various volume levels
(Cb=0.39 p.F).

FIGURE 4. Tone Characteristic (Gain vs Frequency)

15

s:::
....
o

L-J-~~-L-L~~~~

20

20k

100
SOD
FREQUENCY (Hz)

5k

20k
TLlH/5142-10

TLlH/5142-9

FIGURE 7. Loudness Compensated Volume
Characteristic

FIGURE 6. Tone Characteristic (Gain vs Frequency)

1-95

Applications Information

(Continued)

Figures 8 and 9 illustrate the loudness characteristics obtained with Cb changed to Cb/2 and Cb/4 respectively, Ct
being kept at the nominal 0.01 ",F. These values naturally
modify the bass tone response as in Figures 2 and 3.

ance, this is easily done and high value resistors may be
used for minimal additional loading. It is possible to reduce
the rate of onset of control to extend the active range to
-50 dB volume control and below.
The control on pin 7 may also be divided down towards
ground bringing the control action on earlier. This is illustrated in Figure 12, With a suitable level shifting network between pins 12 and 7, the onset of loudness control and its
rate of change may be readily modified.

With pins 7 (loudness) and 12 (volume) directly connected,
loudness control starts at typically - 8 dB volume, with most
of the control action complete by -30 dB.
Figures 10 and 11 show the effect of resistively offsetting
the voltage applied to pin 7 towards the control reference
voltage (pin 17). Because the control inputs are high imped10

-10

!

-20

z

g -30

10

INCREASED BASS RESPONSE

~

iI--

--.... r--..

-:--., I'
Cb/2 Ct ........

-40

-10

r--..

-50

~ l-

t--.
t--.

!-20

I--"
L"
i-"'"
./ /

~ -30

'" -40

./~

INCREASED BASS RESPONSE

---. -......:-....

-

......

t--..

....
1,...;'/

-

I'.. I' r-... . / Io'~

i' ./

Ctd4 Ct

-50
-60

-60
20

100

500
5k
FREQUENCY (Hz)

20

20k

100

500
FREQUENCY (Hz)

5k

20k

TLIHISI42-11

TLIHISI42-12

FIGURE 8. Loudness Compensated Volume
Characteristic
10

-20

g

-30

z

r-

-40 I -

-. r-.
...... r-.

PlN17 , ................

-50
-60

10

REOUCED RAn: OF ONS£T OF
LOUDNESS COMP£HSATION

-10

~

FIGURE 9. Loudness Compensated Volume
Characteristic

"~"~1
20

100

--

....

-10

!-20

...... ~

~

~

/

- -r-.,--.
I-

"Nl1 1 M ' .........

-50

~=O.OI"

5k

-30
-40

i-"'"

C.-O.39,.

500
FREQUENCY (Hz)

:~~~~~1~~~::T~:f

-60
20k

"~"~1
20

100

500
FREQUENCY (Hz)

TLIHISI42-13

INCREASED RATE OF ONSET OF
LOU~NESS COMPENSATION

-10

I-- "-

-40

l- t--.. t' r-...

~ l-

I - ~ r-... I'--..
~-2Q
l- t--.. 'I'--..
~ -30
PlH12nO~

-60
20

20k

FIGURE 11. Loudness Compensated Volume
Characteristic

~

-50

5k

TLIHISI42-14

FIGURE 10. Loudness Compensated Volume
Characteristic
10

----

.... ....

~ -100

....... ~ /
....... k-"
./

~

,,/

500
FREQUENCY (Hz)

Q,=O.39,.
Ct=D.01 p.F

5k

20k
TLlHISI42-1S

FIGURE 12. Loudness Compensated Volume Characteristic

1-96

r-

s:
....

Applications Information

(Continued)
When adjusted for maximum boost in the usual application
circuit, the LM1036 cannot give additional boost from the
loudness control with reducing gain. If it is required, some
additional boost can be obtained by restricting the tone con·
trol range and modifying Clo Cb, to compensate. A circuit
illustrating this for the case of bass boost is shown in Figure
13. The resulting responses are given in Figure 14 showing
the continuing loudness control action possible with bass
boost previously applied.

o

USE OF THE LM1036 ABOVE AUDIO FREQUENCIES
The LM1036 has a basic response typically 1 dB down at
250 kHz (tone controls flat) and therefore by scaling Cb and
Ct , it is possible to arrange for operation over a wide fre·
quency range for possible use in wide band equalization
applications. As an example Figure 15 shows the responses
obtained centered on 10 kHz with Cb=0.039 I-'F and
Ct =0.001 I-'F.

(0)

CJ1
........

r-

s:
....
o
(0)

m

5k

12
10

11
TOP VIEW

TUH/5142-16

FIGURE 13. Modified Application Circuit for Additional Bass Boost with Loudness Control

20
15

.

-10

~ -20 ~'-P:rf.,i~:-l--+-+-+-:J.,."'l

~

10

'" r'\l1\
Cb=D.D3~.F

:e

.
z

~=D.DD1·F

;;:

-30

-5

-40

1--+-+-1-

-10

-50

1-+-+-+-+++-+-+-1

-15

500
FREQUENCY (Hz)

5k

/

1/

;'

"I\.

cui'

1
200

20k

"-

/I.AXIMUM BASS AND TIIEBLE

-20
100

MAXIMUM BASS AND TREBLE BOOST

lk

5k

50k

II

200k

FREQUENCY (Hz)
TL/H/5142-1B

TLlH/5142-17

FIGURE 15. Tone Characteristic (Gain vs Frequency)

FIGURE 14. Loudness Compensated Volume
Characteristic

1·97

LM1035/LM1036
(J)

3"

"2:::;:
INTERNAL VOLTAGE

CH 2 INPUT

VOLUME

VOLUME CONTROL

VOLUME ANO BALANCE

BALANCE CONTROL

11 SUPPLY

Ci"

a.

(J)

n

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CD

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100

II

-

~

TREBLE CAPACITOR

• Connections reversed

CH2 ....

4CH2

14

TREBLE CONTROL

"

9k

LOUONESS
COMPENSATION

BASS
CONTROL

CH2-' 4CH2

USlMlf
5 (16)
AC BYPASS

06(15)
BASS
CAPACITDR

c

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cc

~~

$

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ZENER REGULATED DUTPUT VDLTAGE

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.-------------------------------------------------------------------------,r
_

s:
.....

National

oCo)

Semiconductor
Corporation

"'-I

LM 1037 Dual Four-Channel Analog Switch
General Description

Features

The LM1037 is a dual, electronically controlled, analog
switch with an internal muting facility. Anyone of four stereo
signal sources may be selected by means of four control
inputs.

•
•
•
•
•
•
•

Its features make it ideal for stereo source selection in audio
equipment and for use in a wide range of industrial, automotive, multiplexing or sampling applications.

Wide supply voltage range, 5V-2BV
Low distortion, 0.04% typical
Low noise, typically 5 ",V
High input impedance
Low output impedance
TTL compatible control inputs
Very low control current

An additional pin is included to allow parallel connection of
two or more integrated circuits.

Block Diagram
(16) A
(18) B

CONTROL
INPUT
STAGES

lA (2)

(1)

c

2A (4)
lB (6)

+---4.....___(_5) V+
2B (8)
SIGNAL
INPUTS lC (11)
(12) VBIAS
H~--""'----ANO MUTE

2C (13)
10 (17)
20 (15)

(14)
,.........--..;....V-

2

1

II

MUTE

'iiiiWiITs' INHIBIT
TlIH/5199-1

Order Package Number LM1037N
See NS Package N18A

1-99

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
28V
Pin 7 Input Current
5mA

- 20'C to + 70'C
-65'Cto + 150'C
1.3W

Operating Temperature Range
Storage Temperature Range
Power Dissipation (Note 1)
Lead Temp. (Soldering, 10 seconds)

260'C

Electrical Characteristics Vs=12V, TA=25'C
Parameter

Conditions

Tested
Limit (Note 7)

Typical

Supply Voltage

Design
Limit (Note 8)

Units
(Umits)

28

V(ma&

Supply Voltage

5

V(min)

8.5

mA(max)

10

14

mA(max)

0

±0.7

dB

VSUPPLY= 12V

3.0

2.8

Vrm5tmi&
kHz

Distortion THD

VSIGNAL = 1 Vrms @ 1 kHz

0.04

Noise Voltage at Output (Note 3)

CCIR/ARM RS=OO

Channel Separation (Note 4)

VSIGNAL= 1 Vrms@ 1 kHz

-95

Relative Output in Muted State

VSIGNAL = 1 Vrms @ 1 kHz

-90

Supply Current

VSUPPLY= 12V

6.4

VSUPPLY= 28V
Voltage Gain
Signal Handling (Notes 2, 6)
Small-Signal Bandwidth

300
0.1

% (max)

5

20

""V(max)

-70

dB(min)

-70

dB(min)

Output Impedance

10

n

Signal Input Impedance

30

MO

Logic Low Input Level

0.8

Logic High Input Level

2.0

V(mi&

Logic High Input Level

VSUPPLY

~ax)

V(max)

Typical Performance Characteristics (Vs = 12V, TA = 25'C unless otherwise noted)
Supply Current vs Supply
Voltage

Supply Current vs
Temperature

11

«
§.

i

10

9
8

=>
'-'

7

f

6

ill

V

5

V

V

V

V

!

Signal-ta-Noise vs
Temperature (Note 3)

7.5

-115

7.0

;; -110

'"
~

i

l-

! "

w

6.5

~

~

.:.

r---"",

6.0

~

~-100
in

4
3

5.5
0

-110

10
20
3D
SUPPLY VOLTAGE (V)

40

-95
0

10 20 3D 40

50 60 70 80

0

10 20 3D 40 50 60 70 80
AMBIENT TEMPERATURE ('C)

AMBIENT TEMPERATURE ('C)

Signal-to-Noise vs Source
Impedance (Note 3)

i

-70

........

+-

105
6z

J"""o ,......,

Attenuation of Unselected
Inputs vs Frequency
(Note 5)

Channel Separation vs
Frequency (Note 4)
-70

i'" -80

I

~

;; -105

r""\.

~
w
a-lOa

~

'-.

~
~

./

-90

1

10

100

lk

SOURCE IMPEDANCE (kill

10k

-110
0.01

0.1

1

10

FREQUENCY 1kHz)

100

lk

.L

If

- -- --

'" 100

13

to

-90

~

:i-1OO

in

~

ti
=>

/

~

~ -95

-90
0.1

/'

~

~ -80

-110
0.01

~

I

1

I.l

0.1
1
10
100
FREQUENCY 1kHz)

lk

TUH/5199-2

1-100

r-

Typical Performance Characteristics

Co)

Total Harmonic Distortion
vs Frequency
0.2

Total Harmonic Distortion
vs Frequency
0.2

SUPPLY VOLTAGE - 12V
VSIGNAL=I00mVrms -

SUPPLY VOLTAGE=12V

'--

VSIGNAL

=1 Vlms

Total Harmonic Distortion
vs Frequency
0.2

-

~
C>
i!:

0.1

VSIGNAL = 5 Vlms

"

o

0.01

o
10

100

lk

" '"

0.01

FREQUENCY (kHz,

~
c
i!:

0.1

./

0.1

-

.....

-

0.15

0.05

0.05

SUPPLY VOLTAGE=28V

r--

0.15

0.15

~
'"
i!:

....s::o

(Continued) (Vs = 12V, TA= 25°C unless otherwise noted)

i'o..

0.1

-

10

0.1

0.05

o
100

"

0.01

lk

......... V

0.1

FREQUENCY (kHz)

1

./
10

100

lk

FREOUENCY (kHz)
TL/H/5199-3

Signal Handling vs
Frequency (Note 6)

Note 1: Above TA=25'C derate based on TJ max=150'C and 8JA=90'C/W.
Nole 2: The instantaneous maximum voltage difference between any two input pins of one channel is
9.6V. Voltages in excess of this level may cause increased distortion and degraded channel separation.
Note 3: Gaussian noise, monitored over a period of 50 ms per channel, with a CerA filter referenced to
2 kHz, and an average~responding meter. Signal to noise ratios are referenced to 1V Ims input signal.

~

\

Nole 4: The level of output signal of a selected undriven amplifier with respect to the output level of a
selected driven amplifier. For test purposes, Signal is applied to only one input and all other inputs are
decoupled to eliminate stray pick-up through external components. Channel separation is then defined as
the ratio of signal levels of the two output pins.

\

\

Note 5: For test purposes, signals are connected to three unselected input pins of one channel group and
all other inputs are decoupled to eliminate stray pick-up through external components.
Note 6: Supply voltage 12V; signal handling defined at 1 % distortion, 1 kHz.

o

Note 7: Guaranteed and 100% production tested.

0.01

0.1

1

10

100

lk

Note 8: Guaranteed but not 100% production tested. These limits are not used to calculate outgoing
quality levels.

FREQUENCY (kHz)
TLlH/5199-4

Typical Application
CONTROL INPUTS

r-o
1-----+--1 r-o
CIN

1--__++--1

......--i--_......

10

CIN

20

INPUTS

INPUTS
CIN

'-----+--i

R

=100 k!l1l4 watt

C2= 1 pF

CIN=1 pF

2C

C3

Cl =10pF
C3=I00pF

t-0

TO PIN 7
NEXT DEVICE
(MUTE INHIBIT)

T

T

CH2
AUDIO OUTPUTS

TLlH/5199-5

1-101

II

~

C')

....

o
:E
-'

r-----------------------------------------------------------------------------,
Truth Tables

LM1037
Channel selection is achieved by the application of DC voltages to the control pins.
Unselected control pins should be held low.

DC Control Pin
in HIGH State

Input Pair Switched to
Output Pins (10, 9)

16
18
1
3
None

(2,4)
(6,8)
(11,13)
(17,15)
(12)

A
B
C
D
Mute

Low switching level (VLJ~""'----------f

(10) OUTPUT 1

II

> _______...:(:::9) OUTPUT 2

BIAS (;...12.;.)_ _- '
TLiH/5200-1

Order Number LM1038N
See NS Package Number N18A

1-105

co
C")

o
,..
:::E

....I

Absolute Maximum Ratings
If Military!Aerospace specified devices are required,
contact the National Semiconductor Sales Office!
Distributors for availability and specifications.
Supply Voltage
28V
Pin 7 Input Current

- 20"C to + 70·C
-65·C to + 150"C

Operating Temperature Range
Storage Temperature Range
Power Dissipation (Note 1)
Lead Temperature (Soldering, 10 sec.)

1.3W
260·C

5mA

Electrical Characteristics Vs=12V, TA=25·C.
Parameter

Tested
Limit (Note 7)

Typ

Conditions

Supply Voltage

Design
Limit (Note 8)

Units
(Limits)

28

V(max)

Supply Voltage

5

Supply Current

Signal Handling (Notes 2, 6)

mACmax)

17

2B

mA(max)

0

±0.7

dB

3.0

2.8

Vrms(MIN)

0.1

%Cmax)

12

VSUPPLy=28V
Voltage Gain
VSUPPLY= 12V

Small·Signal Bandwidth

VCmin)

17

VSUPPLY= 12V

300

Distortion THO

VSIGNAL = 1 Vrms

Noise Voltage at Output (Note 3)

CCIR/ARM Rs=On

@

kHz

1 kHz

0.04
5

20
-70

Channel Separation (Note 4)

VSIGNAL = 1 Vrms

@

1 kHz

-95

Relative Output in Muted State

VSIGNAL = 1 Vrms

@

1 kHz

-90

""V(max)
dBCmin)

-70

dBjrni'!t

Output Impedance

10

n

Signal Input Impedance

30

Mn

Logic Low Input Level

0.8

Logic High Input Level

2.0

VCmin)

Logic High Input Level

VSUPPLY

V(maxl

V(max)

Typical Performance Characteristics (Vs = 12V, TA = 25·C unless otherwise noted)
Supply Current vs Supply
Voltage

!

18

17

17

16

~

14

~

13

=>
"1

12

~

8:

Supply Current vs
Temperature

lB

I

15

If

!...

/

I

I...
=>

14

~

13

~

12

40

-110

z
6

......

""'"
0

.
~

.- ...... .-

-..

~-lO0

;;;

-95

10 20 3D 40 50 60 70 BO
AMBIENT TEMPERATURE ('CI

0

10 20 30 40 50 60 70 80
AMBIENT. TEMPERATURE ('CI

Attenuation of Unselected
Inputs vs Frequency
(Note 5)

Channel Separation vs
Frequency (Note 4)

.
i

~

-70

-70

-80

~ -80

I

~

;; -105

~w

a-l00
z
6

.

1$ -105

10
30
20
10
SUPPLY VOLTAGE (VI

-

~w

11

Signal-to-Noise vs Source
Impedance (Note 3)

~

'"

~-110

15

10

~

-115

16

11
0

Signal-to-Noise vs
Temperature (Note 3)

~

"\.

i10k

-110
0.01

0.1

1
10
100
FREQUENCY (kHzl

-90

~"'-100

1OO

lk

'(

15

Ei
=>

./

~

;;;

1
10
100
lk
SOURCE IMPEDANCE (kO)

./

!Ii!

-95
-90
0.1

/'

Ii
'"
~ -90
'"

-110
0.01

I

I
/

I

I

0.1
10
100
1
FREQUENCY (kHzl

lk

TL/H/5200-2

1·106

Typical Performance Characteristics (Continued) (Vs = 12V, TA = 25'C unless otherwise noted)
Total Harmonic Distortion
vs Frequency
0.2

Total Harmonic Distortion
vs Frequency
0.2

SUPPLY VOLTAGE=12V
VSlGNAl = 100 mVrms -

VSIGNAL = 1 Vrms

0.2

-

I--

0.15

0.15

~
c
:z:
....

SUPPLY VOLTAGE=12V

f--

Total Harmonic Distortion
vs Frequency

~
c
i=

0.1

~

0.1

~

V

o

,-

~
c
i=

0.1

10

100

lk

0.01

FREQUENCY (kHz)

f--

~

0.1

1

0.1

0.05

r-...

o

0.01

-

0.15

0.05

0.05

SUPPLY VOLTAGE - 28V
VSIGNAl = 5 Vrms

10

i.

.....

./

"""'- V"

o
100

lk

0.01

0.1

FREQUENCY (kHz)

1

10

100

lk

FREQUENCY (kHz)
TLlH/S200-3

Signal Handling vs
Frequency (Note 6)
Note 1: Above TA=2S'C derate based on TJ max=lS0'C and 9JA=90'C/W.
Note 2: The instantaneous maximum voltage difference between any two input pins of one channel is
9.6V. Voltages in excess of this level may cause increased distortion and degraded channel separation.

1\

\

Note 3: Gaussian noise, monitored over a period of 50 ms per channel. with a CCIR filter referenced to
2 kHz, and an average responding meter. Signal-ta-noise ratios are referenced to a 1 Vrms input signal.

,

Note 4: The level of output signal of a selected undriven amplifier with respect to the output level of a
selected driven amplifier. For test purposes, signal is applied to only one input and all other inputs are
decoupled to eliminate stray pick-up through external components. Channel separation is then defined as
the ratio of signal levels of the two output pins.

\

Note 5: For test purposes, signals are connected to three unselected input pins of one channel group and
all other inputs are decoupled to eliminate stray pick-up through external components.
0.01

0.1

1

10

100

lk

Note 6: Supply voltage 12V; signal handling defined at 1% distortion, 1 kHz.

FREQUENCY (kHz)

Note 7: Guaranteed and 100% production tested.
TLlH/S200-4

Note 8: Guaranteed but not 100% production tested. These limits are not used to calculate outgOing
quality levels.

Typical Application
CONTROL INPUTS
D(LSB)

C'N

L-____-+~~

lA

L..--_-;-_ _--'

~10

II

C'N

'--------+~ ~ 20

2A
INPUTS

INPUTS
C'N

L-______~~

~2C

C'N

'--______+-1
R= 100 kn

v.. watt

Cl=10/LF
C2=1/LF
C3=100/LF
C'N=l/LF

~ lC

T

T

CH2

CHl

OUTPUTS
TL/H/S200-S

1-107

co
C")

~

r----------------------------------------------------------------------------,
Truth Table

:::iE

Logic Inputs

....I

Latch
Enable
Pin 18

Mute
Pin 1

Input Pin Selected

Channel Select
Data
Pin3
Pin 16

Output 1 Output 2
Pin 10

Pin9

0

DPin 17

D Pin 15

0

1

APin2

APin4

1

0

BPinS

BPin8

0

1

1

C Pin 11

C Pin 13

1

1

0

X

X
X

X
X

1

0

0

1

0

1

0

1

Pin 12 Mute Bias
Inputs Previously
Selected are
Retained

Low (0) (47k

VOLUME
CONTROL

STEREO
ENHANCEMENT
ON

OOFF

0.22"F

-;J;
ON

OFF

LOUDNESS
COMPENSATION

BALANCE
CONTROL

0.1 "F

....--------I\,/\,,..,...--------..~47k~~~~~~L
-;/;0.22 "F

TL/H/5147-4

1-113

.,..oo

o
.....
o
.....

::i!!
..J

Application Notes (Continued)
ZENER VOLTAGE
A zener voltage (pin 19=5.4V) is provided which may be
used to bias the control potentiometers. Setting a DC level
of one half of the zener voltage on the control inputs, pins 6,
11, and 16, results in the balanced gain and flat response
condition. Typical spread on the zener voltage is ± 100 mV
and this must be taken into account if control signals are
used which are not referenced to the zener voltage. If this is
the case, then they will need to be derived with similar accuracy.

TONE CONTROLS
Summarizing the relationship given in the data sheet, basically for an increase in the treble control range Ct must be
increased, and for increased bass range Cb must be reduced.
Figure 1 shows the typical tone response obtained in the
standard application circuit. (Ct=O.Ol ",F, Cb=0.39 ",F).
Response curves are given for various amounts of boost
and cut.
20

LOUDNESS COMPENSATION
A simple loudness compensation may be effected by applying a DC control voltage to pin 9. This operates on the tone
control stages to produce an additional boost limited by the
maximum boost defined by Cb and Ct. There is no loudness
compensation when pin 9 is connected to pin 19. Pin 9 can
be connected to pin 14 to give the loudness compensated
volume characteristic as illustrated without the addition of
further external components. (Tone settings are for flat response, Cb and Ct as given in Application Circuit.) Modification to the loudness characteristic is possible by changing
the capacitors Cb and Ct for a different basic response or,
by a resistor network between pins 9 and 14 for a different
threshold and slope.

:::-10

.,

5

~

z
;;;:

0

'"

-5
-10
-15

.

n

STANDARD APPLICATION CIRCUIT

15

--

,BASS AND TREBLE BOOST

~~

~

~ f-"'"

-r-:::~

~f.'

-~1ilI"""

~t-

...-::~

~

-

:;

T~EB~+ :s
~ ~ BAfSCbA~O=0.39"F
14=0.01 "F

-20
20

100

500
FREQUENCY (Hz)

5k

5.4 z
4.7
4.0 <§
3.4 ::;

~

~
2.7 -a
2.0 ~
1.4
0.7 i§
0.0 ~

,.
~

:3

20k
TLlH/5147-5

FIGURE 1. Tone Characteristic (Gain vs Frequency)
Figures 2 and 3 show the effect of changing the response
defining capacitors Ct and Cb to 2Ct, Cb/2 and 4Ct, Cb/4

SIGNAL HANDLING
The volume control function of the LM1040 is carried out in
two stages, controlled by the DC voltage on pin 14, to improve signal handling capability and provide a reduction of
output noise level at reduced gain. The first stage is before
the tone control processing and provides an initial 15 dB of
gain reduction, so ensuring that the tone sections are not
overdriven by large input levels when operating with a low
volume setting. Any combination of tone and volume settings may be used provided the output level does not exceed 1 Vrms, Vee = 12V(0.7 Vrms, Vee=9V). At reduced
gain « -6 dB) the input stage will overload if the input level
exceeds 1.6 Vrms, Vee=12V (1.1 Vrms, Vee=9V). As
there is volume control on the input stages, the inputs may
be operated with a lower overload margin than would otherwise be acceptable, allowing a possible improvement in signal to noise ratio.

respectively, giving increased tone control ranges. The values of the bypass capacitors may become significant and
affect the lower frequencies in the bass response curves.
20 r-.-.-.-~~~-~,..-,
15 i-- INCREASED CONTROL RANGE""" 5.4 g
10

~
Z

~

5
0
-5

f--I-.t\..
I-I-r--;~
~

IY ....

l.e~
~~

3.4 !iii
2.7 ~
2.0

!

~

1-'2'

i

4.7
4.0 <§

F
......
-+:::I-*I:::;5'l-jr"-+-+-+-I~~t--.dl--j 1.4 ~
-10 1-1-':
Cb/2 214
'"~r-~
-15
~
I.....
0.7 ~
-20

L-...l.......l.......l....-L-L--L_",-.J.-J

2D

100

500
FREQUENCY (Hz)

5k

0.0

:3

20k
TLlH/5147-6

Applications Information

FIGURE 2: Tone Characteristic (Gain vs Frequency)

OBTAINING MODIFIED RESPONSE CURVES
20

The LM1040 is a dual DC controlled bass, treble, balance
and volume integrated circuit ideal for stereo audio systems.
In the various applications where the LM1040 can be used,
there may be requirements for responses different to those
of the standard application circuit given in the data sheet.
This application section details some of the simple variations possible on the standard responses, to assist the
choice of optimum characteristics for particular applications.

~~ASEO CONTROL RANGEV' ......

.,
~

z
;;;:

'"

ul-

I-

15
10

~

5

.....;~

0
-5
-10
-15
-20

I-

--

J.~

"

f-""

20

Cb/4
100

414

~ ,.....
r-

500
5k
FREQUENCY (Hz)

n

i

3.4

$i

<§

2.7 il1
-a

Z
2.0 en

,.

,~

l- f- ::::::

.

4.0

4.7

.....-:: r ~
~

5.4

~

--

1.4
i§
0.7
0.0 :3
~

20k
TL/H/5147-7

FIGURE 3: Tone Characteristic (Gain vs Frequency)

1-114

Applications Information (Continued)
Figure 4 shows the effect of changing Ct and Cb in the
opposite direction to Ct/2, 2Cb respectively giving reduced
control ranges. The various results corresponding to the different Ct and Cb values may be mixed if it is required to give
a particular emphasis to, for example, the bass control. The
particular case with Cb/2, Ct is illustrated in Figure 5.

It will be seen from Figures 2 and 3 that modifying Ct and Cb
for greater control range also has the effect of flattening the
tone control extremes and this may be utilized, with or without additional modification as outlined above, for the most
suitable tone control range and response shape.
OTHER ADVANTAGES OF DC CONTROLS
The DC controls make the addition of other features easy to
arrange. For example, the negative-going peaks of the output amplifiers may be detected below a certain level, and
used to bias back the bass control from a high boost condition; to prevent overloading the speaker with low frequency
components.

RESTRICTION OF TONE CONTROL ACTION AT HIGH
OR LOW FREQUENCIES
It may be desired in some applications to level off the tone
responses above or below certain frequencies for example
to reduce high frequency noise.
This may be achieved for the treble response by including a
resistor in series with Ct. The treble boost and cut will be
3 dB less than the standard circuit when R = Xc.
A similar effect may be obtained for the bass response by
reducing the value of the AC bypass capacitors on pins 7
(channel 1) and 18 (channel 2). The internal resistance at
these pins is 1.3 kO and the bass boost! cut will be approximately 3 dB less with Xc at this value. An example of such
modified response curves is shown in Figure 6. The input
coupling capacitors may also modify the low frequency response.

20
15
10

~

z

C

'"

-5
-10
-15

REDUCED CONTROL RANGE

i::::: ~

Ie

..... lef--'

I - r-;; ~
fjjiiII

-~

1IIliiit--

~~
~

~

2 Cb Ct/Z

5.4
4.7
4.0
3.4
2.7
2.0
1.4
0.7
0.0

LOUDNESS CONTROL
The loudness control is achieved through control of the
tone sections by the voltage applied to pin 9; therefore, the
tone and loudness functions are not independent. There is
normally 1 dB more bass than treble boost (40 Hz-16 kHz)
with loudness control in the standard circuit. If a greater
difference is desired, it is necessary to introduce an offset
by means of Ct or Cb or by changing the nominal control
voltage ranges.
Figure 7 shows the typical loudness curves obtained in the
standard application circuit at various volume levels
(Cb=0.39 ".F).

g

20

:==

15

z
....

10

;§

~

'"
:!!.

ill

.

..,.

C

z

20

100
500
FREQUENCY (Hz)

5k

-

~~

-5

l=- I- t;:;"

r-- 1-'":1'
-15

"

;;\

~

~I""

~,...

-10

:3

-20

l- t-- ~
+- ~

z

"
z

n

INCREASED BASS CONTROL RANGE

"

5.4
4.7
4.0 ;§
3.4 !=i

i

~ ~~ .,..,.
t§~
2.7 ~
2.0 z

I-"""

~

Cb/Z Ct

1.4
0.7 ~
0.0 ;;\

:3

-20
20

20k

100

SOD
FREQUENCY (Hz)

5k

20k
TLIHI5147-9

TLIHI5147-8

FIGURE 4. Tone Characteristic (Gain vs Frequency)
20

FIGURE 5. Tone Characteristic (Gain vs Frequency)
10

r--r-r-r~-,-,r-,-,--

STANDARD APPLICATION CIRCUIT

15
10

-10

!

-20

l"-

I--

t- r--- ,.....

l- t-.... """,
~ -3~
l- I"-.. .....

'"
'"

-40
-50

./

100

SOD
5k
FREQUENCY (Hz)

20

20k

""

~

t,....-

PIN 9 CONNECTED TO PIN 14

-60

II

-l- tV

100
500
FREQUENCY (Hz)

Cb=O.39 IlF
Ci=O.01 pF

5k

20k
TLlHI5147-11

TLlHI5147-10

FIGURE 7. Loudness Compensated
Volume Characteristic

FIGURE 6. Tone Characteristic (Gain vs Frequency)

1-115

o

-.:t

o
.,...

Applications Information

:E

Figures 8 and 9 illustrate the loudness characteristics obtained with Cb changed to Cb/2 and Cb/4 respectively, Ct
being kept at the nominal 0.01 /-,F. These values naturally
modify the bass tone response as in Figures 2 and 3.

....I

(Continued)
voltage (pin 19). Because the control inputs are high impedance, this is easily done and high value resistors may be
used for minimal additional loading. It is possible to reduce
the rate of onset of control to extend the active range to
-50 dB volume control and below.

With pins 9 (loudness) and 14 (volume) directly connected,
loudness control starts at typically -8 dB volume, with most
of the control action complete by -30 dB.

The control on pin 9 may also be divided down towards
ground bringing the control action on earlier. This is illustrated in Figure 12. With a suitable level shifting network be:
tween pins 14 and 9, the onset of loudness control and its
rate of change may be readily modified.

Figures 10 and 11 show the effect of resistively offsetting
the voltage applied to pin 9 towards the control reference

10

10

-10

~ -20
z

~

-30
-40

-10

-

r---..

~,.--.

I - r-:-..

-l-

r---. I:-..

r--", f"'.

.....
./
./

.......

~ -2Q i - ,.....

z
:;;: -30

'"

. / ..... 1/

I......... ~

Cb/2 C,

-50

INCREASEO BASS RESPONSE

INCREASED BASS RESPONSE

V

""-

r-...

r--. t-.... i'.
r--- r-.... ~

-40

I'

Cb/4 Ct

-50

.,. J..-- I./

...-

. / 7",..

./

-60

-60

20

100

500
5k
FREQUENCY (Hz)

20

20k

100

500
FREQUENCY (Hz)

5k

20k
TLlH/5147-13

TL/H/5147-12

FIGURE 9_ Loudness Compensated Volume
Characteristic

FIGURE 8. Loudness Compensated Volume
Characteristic
10

-10

!

-20

z

~

~ -30
-40 ~

-

-60

-

...... I:-..
.......

r-....

PI~9

20

100

REDUCED RATE OF ONSET OF
LOUDNESS COMPENSATION

-10

I-

PlN191M',

-50

10

REDUCED RATE OF ONSET OF
LOUDNESS COMPENSATION

,.... .....

~-20
z
fj -30

l-

.....
1/

-40

5k

i-

r-.. I:-..

I'IN191M'-.. .........

-50

Cb-O.39pF
CI=D.01 pF

500
FREQUENCY (Hz)

-

-60

1'I~9
20

20k

100

500
FREQUENCY (Hz)

-10

~ -20
z

~

-30
-40
-50

-60

5k

20k

FIGURE 11. Loudness Compensated Volume
Characteristic

INCREASED RATE OF ONSET OF
LOUONESS COMPENSATION

--

i- ~

- ...........

-'"

../ ~ -"

:-.. ....... ........

........
t- ......t-.......

./

P

100

V

V

PlNl.220~

20

--,-

TL/H/5147-15

TL/H/5147-14

FIGURE 10_ Loudness Compensated Volume
Characteristic
10

----

V

V

/

l- I- F Cb =D,39pF
Ct=O.Dl p F

500
5k
FREQUENCY (Hz)

20k
TLIH/5147-16

FIGURE 12_ Loudness Compensated Volume Characteristic

1-116

,---------------------------------------------------------------------------------, r-

Ei:
.....

Applications Information

(Continued)
When adjusted for maximum boost in the usual application
circuit, the LM-l040 cannot give additional boost from the
loudness control with reducing gain. If it is required, some
additional boost can be obtained by restricting the tone control range and modifying C.. Cb, to compensate. A circuit
illustrating this for the case of bass boost is shown in Figure
13. The resulting responses are given in Figure 14 showing
the continuing loudness control action possible with bass
boost previously applied.

USE OF THE LM1040 ABOVE AUDIO FREQUENCIES
The LM1040 has a basic response typically 1 dB down at
250 kHz (tone controls flat) and therefore by scaling Cb and
C.. it is possible to arrange for operation over a wide frequency range for possible use in wide band equalization
applications. As an example Figure 15 shows the responses
obtained centered on 10kHz with Cb = 0.039 ",F and
C1=0.001 ",F.

U

-1
..J.

....

o
o

~
~

....!

~

..!

~
~

..J!
.....!!

lMl040N

19

...!.

.!!.

8

.!!.

Cb=0.22.Fr-:

16

"J;J!

~

..1!

.!i.

.1!

.!!.

5k

r

47k
25k

...L,
O 22 F
. •

5k

n'T

TOP VIEW

TlIH/5147-17

FIGURE 13. Modified Application Circuit for Additional
Bass Boost with Loudness Control

1

0

o t---

-10

IRESloNStS

OBT~INEb WI~H MOJIFlEJ

CIRCUIT Of FIGURE 13

~

IIIIII

20
15

-

ADDITIONAL BASS BOOST OBTAINED

5

!ill -20 I'""-'i'"ll'"l-""~:-+I+1+--+~""1

i-3D
..
-40

BASl!olsT

N
1\

10

WITH LO~ONE~S CON"OL

_

r-,--,--,----...,--..,---r-r-,
r-..... MlXlM~M BA~S AND TREBLE BOOST

I~ ..... "...
I. J
C,=O.22"+_-+-+---I

:z:

0

~1_+_~-+_+__+_~-+-4

Cb

=o.03L.+-i'---'l:;;;;::I...-~V_+_+__{

;;;:
~=0.001 " . /
'"
.. -5 r--r-+-~~~~~~~

r'
1-+--+---1
I
'---'--'--'--'--'--'-_'-L......I

-10

~=I··Ol

I--t-:.I"
I.I/,+---+-+-+-+I'--'k-J
cur'

-50 f-+-I-+-f-+-+

-15

_ 60

_ 20 L...-.L-..lI--1.---L-'----'--'-...L.......I
200
lk
5k
50k 200k
FREQUENCY (Hzl

20

100

500
FREQUENCY (Hz)

5k

20k

/"IMAXIMUM BASS AND TREBLE

II
TL/H/5147-19

TLlH/5147-18

FIGURE 14_ Loudness Compensated
Volume Characteristic

FIGURE 15. Tone Characteristic (Gain vs Frequency)

1-117

Q

oo:r

.,...
Q

:::i!i

....I

r--------------------------------------------------------------------,
Applications Information

(Continued)

DC CONTROL OF STEREO ENHANCEMENT AND
LOUDNESS CONTROL
The high impedance PNP base input of the loudness control
pin 9 is readily switched with a general purpose NPN transistor.

Figure 16 shows a possible circuit if electronic control of
these functions is required. the typical DC level at pins 3 and
22 is 7.5V (Vee = 12V), with the input signal superimposed,
and this can be used to bias a FET switch as shown to save
components. For switching with a OV-5V signal a lowthresh hold FET is required when using a 12V supply. With
larger switching levels this is less critical.

BASS
CONTROL

Vee

VOLUME
CONTROL

2N4393

LOUDNESS

L-......W \ t - - - - 4 - COMPENSATION

390k

5V ON, OV OFF
BALANCE
CONTROL

STEREO
ENHANCEMENT
5V ON, OV OFF

47k

+---------~~--------_.~47k~~:~~L

;J; 0.22 pF

TL/H/5147-20

FIGURE 16. Application Circuit with Electronic Switching

1-118

~

INTERNAL VOLTAGE
13 SUPPLY

CH 2

INPUT
2(23)

STEREO
EXPANSION VOLUME
3(22)

3

=

'a
VOLUME AND BALANCE

VOLUME CONTROL
14

BALANCE CONTROL
11

OUTPUT
10

::!!

CD

Q.

4.1k

&

en
n
:::r
CD

~

I~

i

~

n
C

iii'

CC

,. f

ml~

:::J

~

~

~

co
24
0--

~

160pA
3.3V

1.5V

t ~. >?

I

j

..........

100
4(21)
TREBLE CAPACITOR

$

-~
CH2+-

4CH2

6
TREBLE CONTROL

9
LOUDNESS
COMPENSATION

~

16
BASS
CONTROL

CH 2....-J

4

~
CH 2

5.

1(18)

AC BYPASS

tK$

4V

2~0 pA

0 8(11)

BASS
CAPACITOR

ZENER REGULATED OUTPUT VoLJAGE

OtO~Wl

II

~
.,...

.,...
.,...

:!

....I
.....

NatiOnal

~ Semiconductor

[][]

Corporation

ID

.,...
.,...
.,... LM1112A/LM1112B/LM1112C
('II

:!
....I

Dolby® B-Type Noise Reduction Processor

;C

.,...
.,... General Description
.,...
The LM1112 is a monolithic integrated
('II

:!
....I

Features

circuit specifically
designed to realize the Dolby B-type noise reduction system.
It is a replacement for the LM1111 and the Signetics NE645/648 but with improved performance figures.

• Very high signal/noise ratio, 74 dB encode
(CCIR/ARM)
• Wide supply voltage range, 6V to 20V
• Very close matching to standard Dolby characteristics
• Audible switch-on transients greatly reduced
• Improved temperature performance
• Reduced number of precision external components
• Improved transient stability
• Input protection diodes

Available only to licensees of Dolby Laboratories Ucensing Corporation, San Francisco, from whom licensing and application information must be obtained.

Dolby and the double-D symbol are registered trademarks of Dolby Laboratories Licensing Corporation.

Schematic Diagram

TUH17876-1

1-120

r1i:
......

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
24V
Operating Temperature Range
-20'Cto +70'C

Electrical Characteristics Vs =
Parameter

LM1112A

Supply Current

(Pin 5-6)

1 kHz Pin 6 Open

(Pin 3-7)

1 kHz (Noise
Reduction Out)

Distortion
Signal Handling

24.5

25.5

26.5

24.5

-0.5

Typ

LM1112C
Max

Min

20

6

15

20

25.5

26.5

24

0

0.5

-1

0.03

0.1

14.7

10 kHz, + 10 dB

0.2

l>
r1i:
......
......
OJ

Typ

Units
Max
20

V

15

20

mA

25.5

27

dB

14.7

0.2

r1i:
......

......
......
o

N

dB

0

1

dB

0.03

0.1

%

0.2

%

1 kHz, 0.3% Distortion

Rs = 10k

8.5
13

8.5

15.5

13

71.5

13

dB

19

dB

74

dB

83

dB

83

83

83

dB

RS = 10k

70

dB

77
83

71

74

8.5
15.5

77
83

74

77

Rs = 10k

15.5
19

19

Rs = 1k

Encode Characteristics Input to Pin 5
10 kHz, 0 dB
1.3 kHz, -20dB

Pin 7

20

0.1

Encode Mode
(CCIR/ARM)
NR In

Load Impedance
Pin3

15

0.5

Pins6and2
Connected

PSRR

6

0

SignallNoise Ratio
at Pin 7 (Note 1)

Output Resistance

20

0.03

Vs = 18V

Input Resistance

Min

1 kHz,OdB

Vs = 12V

Decode Mode
(CCIR/ARM)

LM1112B
Max

14.7
-0.5

Vs = 6V

NROut

Typ

6

1 kHz Pins 6 and 12
Connected

......
......

N

......

12V, TA = 25'C. 0 dB relers to Dolby level which is 580 mVrms at pin 3.
Min

Voltage Gain
(Pin 5-3)

-65'C to + 150'C
260'C

N

Conditions

Supply Voltage Range

Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)

dB

0
-16.2

-0.5
-0.2
0.5
1.2
0.5
1.5
0.5
1.0
-15.7 -15.2 -16.7 -15.7 -14.7 -17.2 -15.7 -14.2

dB

5 kHz, -20dB

-17.3

-16.8 -16.3 -17.8 -16.8 -15.8 -18.3 -16.8 -15.3

dB

3kHz, -30dB

-21.7 -21.2 -20.7 -22.2 -21.2 -20.2 -22.7 -21.2 -19.7

dB

5 kHz, -30dB

-22.3

10 kHz, -30 dB

-21.8 -21.3 -22.8 -21.8 -20.8 -23.3 -21.8 -20.3
-24.0 -23.5 -23.0 -24.5 -23.5 -22.5 -25.0 -23.5 -22.0

dB
dB

10 kHz, -40 dB

-30.1

-29.6 -29.1

-30.3 -29.6 -28.9

-30.6 -29.6 -28.6

dB

dB

Pin5

45

65

80

45

65

80

45

65

80

k!l.

Pin2

4.3

5.6

6.9

4.3

5.6

6.9

4.3

5.6

6.9

k!l.

Pin6

1.8

2.4

3.0

1.8

2.4

3.0

1.8

2.4

k!l.

Pin3

30

45

30

45

30

3.0
45

Pin 7

30

45

30

45

30

45

I = 120Hz

40

40

40

!l.
!l.
dB

5

5

5

k!l.

5

5

5

k!l.

Note 1: Gaussian noise, measured over a period of 50 ms with a CCIR filler and an average responding meter.

1-121

II

o
C'I

.,..
.,..
.,..

Typical Performance Characteristics

:::E

Signal/Noise Ratio vs Source Impedance
Encode Mode (CCIRIARM)

....I

......

m
C'I
.,..
.,..
.,..

80

:::E

....I

......
~
.,..

.,..
.,..

:::E

....I

Gain vs Frequency (NR OFF)
34
32

78

~

28

......

76

24

174

iii 20
;g

"

~ 72

~ 70

-

~ 16
12

68

8

66

4

P6-"7,

10

100

lK

10K

o

lOOK

0.1

10

Source Impedance (OJ

100

1000

Frequency (KHz)

TUH17876-2

Total Harmonic Distortion -

Total Harmonic Distortion - 0 dB Level

+ 10 dB Level

0.9

0.8

0.3

0.7
0.6

._- --

~0.5

~0.2

ci
:i 0.4
..,:

ci
:i

..,:

o. 1

'-

""

0.3

,
I

-

-+

I

0.2

Y
1//

O. 1

o
0.1

10

o

100

II

Dif" .
0.1

10

100

Frequency (KHz)

Frequency (KHz)

TL1H17876-3

Back to Back Response Error vs Frequency and
Supply Voltage (Standard Dolby Encoder)
+1
0
1
+1
0

_y:12'

o

_6:12:2OV

~-10

I

...

~ -10

+1:2
20V

1

:1~:2P'

-40

0.1

26°C

1

ev- c-10

20

1-30

+1
0
1
+1
0
1

,-~

2 ·C

-40

100

Frequency (KHz)

I

--

+1
0
-1
7 C
+1
0
1
7·C_
+1
0
I
1
0
7 ·C +1
0
1
+1

c--

t20

o 11

1-30

0;+ 5:+75D C

o

'iii

1

] 20

Back to Back Response vs Frequency and
Temperature (Encoder Temperature 2S·C)
___Lill

r-

,
QOf-

1

0

0.1

10

20

100

Frequency (KHz)
TL/H/7B78-4

1-122

,-----------------------------------------------------------------------------, r

Typical Performance Characteristics

.........==

(Continued)

~p

30

~ 22
~
",,'

~ 18

~

14

.- .

_... ...

<3

~

l - I-' ~

--

- .- - --

10

6

8

10

-

.s
'"
;:;
:I:

14

.."

;;;

"

I-' ~

I-' I-' I-'"

/

iii
16

L"

l/

1-

:/

12
10

.

--

~

r--

aI

r

I'

.!?

'"

r

==

~

18
26

»

Signal Handling vs Supply Voltage
20

1

-.........
-.........
~

Supply Current vs Supply Voltage

==

I'

~

o

)

IL

8

12
14
16
Supply Voltage IVI

18

20

6

8

10

12
14
16
Supply Voltage IVI

18

20
TL/H17876-5

TRANSIENT RESPONSE TO ABRUPT LEVEL CHANGE (Measured at pin 7)
(a) Encode (f = 5 kHz)

(b) Encoded and Decoded (f = 5 kHz)

100mS/DIV
TLlH/7876-7

TL1H17876-6

TRANSIENT RESPONSE TO ABRUPT FREQUENCY CHANGE (Measured at pin 7)
(a) Encode ( - 20 dB)

(b) Encoded and Decoded (- 20 dB)

100mS/DIV
TL/H17876-8

TL/H17876-9

1-123

II

oCIoI
.....
.....
.....
:::E

...I

iii
CIoI
.....
.....
.....

:::E

...I

2. Supply current may be significantly increased by high pin
14 forced voltages. Values for V and R should thus be
chosen such that pin 14 voltage is 3V-4V.
3. When electrical NR switching is used, signal level is
slightly affected by the minimum value of the internal variable impedance. (At 10 kHz-10 dB, a residual boost of
approximately 0.4 dB remains.) This is not the case for
mechanical NR switching.

ELECTRICAL NOISE REDUCTION SWITCH
In place of the normal mechanical noise reduction on/off
switch, the circuit below is often used to permit electrical NR
control. When using this circuit, the following points should
be noted:
1. Signal boost is reduced by increasing DC voltage on Pin
14 (see curve). A voltage of approximately 3V is adequate
to achieve NR OFF.

......

~
.....
.....
.....

-

- -- - --

- - ----

---

-

--,

I

:::E

DOLBY B-TYPE INTEGRATED CIRCUIT
NATIONAL LM1112.

...I

-------

--

- -

~~13

-

I
I
I

-+I-

G

-

~~14

15
-- - ---

R303

150K
Noise Reduction
Switch
OUT

V

R304
270K

5%

R305

R

~

NR Lamp

r r

330K
5%

•

n~

To C306 in
other Dolby
Processors

C306

C3tJ7

1

33

TL/H17876-10

Note 1: Where not otherwise specified, component tolerances are ± 10%.

Supply Current vs Pin 14 Control Voltage
(Vs = 12V) (Encode, 10 kHz)

Signal Boost vs Pin 14 Control Voltage
(Encode, 10 kHz)

,-I--

10

Max Boost

35
_ 31

8

\.;0'

1

iii

"
;i6

~

0
0

V

27

I'

::0

,..

u

CD

!4
.!!'

/

g.23

I

::0

CII

CII

Minomum Boost with_

1/ 1&iT;na\ N.~. Cyntr~

Z

-

.... .-

19

II

15

0
0

2

4

6

8

10

0

Pin 14 Voltage (V)

2

4

6

8

10

12

Pin 14 Voltage (V)
TL/H17876-11

1-124

r3:
......

Test Circuit (Encode)

......

Ir---------------------------~
Dolby a-Type Intograted Circuit
I
q:]~~~!}-----~~-1
L+6to20voltl

National LMll12N

I
I
I

,-----r------------.I

I
I

Input

15...J

......

N

~

r3:
......

......
......

N

m

r3:
......

......
......
N

n
10K

R.

.
a.

8

TLlH17876-12

Note 1: 1 nF capacitors from pin 3 and pin 7 to ground may be required on older devices.
Note 2: Where not otherwise specified, component tolerances are ± 10%.
Note 3: For LM1112AN use 2% components for C304, R303, R305. (5% components may cause errors up to +0.3 dB.)

Connection Diagram
Dual-In-Line Package
VARIABLE
IMPEDANCE
INPUT
AMPLIFIER B
INPUT

II

AMPLIFIER B
OUTPUT

RECTIFIER OUTPUT

BIAS

RECTIFIER BIAS

AMPLIFIER A
INPUT

RECTIFIER INPUT

AMPLIFIER A
OUTPUT
AMPLIFtER EK
OUTPUT

POSITIVE SUPPLY
VARIABLE IMPEDANCE
CONTROL

AMPLIFIER D
OUTPUT

II

AMPLIFIER D
FEEOBACK DECOUPLING

'

GROUND

OECOUPLING

TLIH17876-13

Order Number LM1112AN, LM1112BN
or LM1112CN
See NS Package Number N16E

1-125

or------------------------------------------------------------------.
.,...
.,...
.,...

C")

:E
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......

NatiOnal

~ Semiconductor
Corporation

m
.,...

.,...
.,...
C")

:E
..J

......

LM1131A/LM1131B/LM1131C
Dual Dolby® B-Type Noise Reduction Processor

 +20 dB (Vs = 20V)
• Full-wave rectifier in both channels
• Operates with both single and split supply voltages
• Excellent transient response characteristics
• Minimal input switch-on transients
• Reduced number of external components per channel
• Improved input protection

Available to licensees of Dolby Laboratories Ucensing Corporation, San Francisco, from whom licensing and application information must be obtained.

Schematic Diagram (1 channel shown only)

TL/H/685B-l

1-126

r-

s::
......

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
24V
Operating Temperature Range
- 20'C to + 70'C
Storage Temperature Range
-65'Cto +150'C

Soldering Information
Dual-In-Line Package
Soldering (10 seconds)
260'C
Small Outline Package
215'C
Vapor Phase (60 seconds)
Infrared (15 seconds)
220'C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" (appendix D) for other methods of
soldering surface mount devices.

rs::
......
......
(0)
......

III
......

rs::
......
(0)

......

o

Vs = 12V, TA = 25'C unless otherwise specified. 0 dB refers to Dolby level and is 580 mY, measured at TP1 and TP2.
LM1131A

Conditions
Min

Supply Voltage Range

~

......

Electrical Characteristics
Parameter

......
......

(0)

Typ

5

Supply Current

LM1131B
Max

Min

20

5

20

Typ

LM1131C
Max
20

20

Min

Typ

5

Units
Max
20

20

V
rnA

Voltage Gain
(Pins 7-10 and 14-11)
(Pins 10-9 and 11-12)

1 kHz Decode
1 kHz Decode

19.2
-0.5

19.7
0

20.2
0.5

18.7
-0.5

19.7
0

20.7
0.5

18.2
-1.0

19.7
0

21.2
1.0

dB
dB

Difference in Voltage

1 kHz Noise

-0.2

0

0.2

-0.5

0

0.5

-1.0

0

1.0

dB

-60

-90

-60

-90

-60

-90

dB

77

79
82
90
92

75.5

79
82
90
92

74

79
82
90
92

dB
dB
dB
dB

0
-16.2
-17.3
-21.7
-22.3
-30.1

0.5
-15.7
-16.8
-21.2
-21.8
-29.6

0.2
-16.7
-17.8
-22.2
-22.8
-30.3

0.5
-15.7
-16.8
-21.2
-21.8
-29.6

-0.5
-17.2
-18.3
-22.7
-23.3
-30.6

0.5
-15.7
-16.8
-21.2
-21.8
-29.6

Gain between Channels Reduction OFF
Crosstalk between
Channels

1 kHz,OdB

Signal/Noise Ratio
at Pins 9 and 12
Encode

(Note 1)

Decode
Encode Characteristics

Variation in Encode
Characteristics
Temperature
Voltage
Distortion
Signal Handling

Rs = 10kO
Rs=1kO
Rs = 10 kO
Rs=1kO
10 kHz, 0 dB
1.3 kHz, -20 dB
5 kHz, -20dB
3 kHz, -30 dB
5kHz, -30dB
10 kHz, -40 dB

O'C-70'C
5V-20V
1 kHz,OdB
10 kHz, 10 dB
1 kHz, Dist = 0.3%
Vs = 5V
Vs = 7V
Vs = 12V
Vs = 20V

Input Resistance

Pins 7 and 14

Output Resistance

Pins 9 and 12
Pins 10 and 11

1.0
-15.2
-16.3
-20.7
-23.0
-29.1

<±0.5
<±0.2
0.03
0.2

14.0
45

<±0.5
<±0.2
0.03
0.2

0.1

6.5
10.5
16.0
21.0

14.0

65

80

30
30

55
55

45

1.2
-14.7
-15.8
-20.2
-20.8
-28.9

<±0.5
<±0.2
0.03
0.2

0.1

6.5
10.5
16.0
21.0

14.0

65

80

30
30

55
55

45

0.2

6.5
10.5
16.0
21.0

dB
dB
dB
dB
dB
dB

dB
dB
%
%
dB
dB
dB
dB

65

80

kO

30
30

55
55

0
0

Note 1: Gaussian noise, measured over a period of 50 ms per channel, with a CCIR filter referenced to 2 kHz and an average.responding meter.

1-127

1.5
-14.2
-15.3
-19.7
-20.3
-28.6

II

o
....

........

Typical Performance Characteristics

...I

Supply Current vs Supply Voltage
(1 kHz, 0 dB; NR ON)

C')

::E

.....

m
....

........
...I
;c....
........

Signal Handling vs Supply Voltage
22

C')

.

::E

.... ....

30

C')

i26

~

E

.

...

~22

........ ....
.... ....

l



R1
'00

lGO~

,--+-JVIo.........

'"
IUD"F

RlI

v,

+ cia

,,:,,'I1011I'Ji!

RfCOROIPLA,(':'"
HEAD

RECORoo-J'-+--------1

41,f

T

41J1f

82PF

TO RIGHTCHAftNEl HEAD
AND ElECTRONICS

T

BlPF
PlAVI

RttDRDO

TlIH/7894-1

FIGURE 1. Stereo Application Circuit (Left Channel Shown), Vs = 15V
Order Number LM1818N
See NS Package Number N20A

1-136

rii5:

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

-65'C to + 150'C

Parameter

-0.1 Voc

Maximum Voltage on Pins 2 and 5

0.1 Voc

Maximum Current Out of Pin 14

5mAoc
260'C

Lead Temperature (Soldering, 10 sec.)
25'C, See Test Circuits (Figures 2 and 3)

Conditions

Min

Operating Supply Voltage Range

Typ

3.5

Supply Current

Test Circuit (Figure 2)

Turn-ON Time

Externally Programmable

Playback Signal to Noise

DIN Eq. (31BO and 120 /Ls), 20-20 kHz,
Rs = 0, Unweighted, VREF = 1 mV
at 400 Hz

Record Signal to Noise

5

Flat Gain, 20-20 kHz, Rs
ALC OFF, VREF = 1 mV
at 1 kHz, Unweighted

50

Max

Units

18

Voc

12

mA

400

ms

74

dB

69

dB

200

/LA

100

dB

= 0,

Fast Turn-ON Charging Current

Pins 16 and 17

Record and Playback Preamplifier
Open Loop Voltage Gain

f

Preamplifier Input Impedance

Pin 16 or Pin 17

50

ko.

Preamplifier Input Referred PSRR

1 kHz -

85

dB

0.5

V

0.5

/LA

80

dB

=

100Hz

Flat Gain

Bias Voltage on Pin 18 in Play Mode
or Pin 15 in Record Mode
Monitor Amplifier Input
Bias Current

Pins 11 and 12

Monitor Amplifier Open
Loop Voltage Gain

Record or Playback, f

Monitor Output Current Capability

Pins 9 and 10, Source Current Available

Monitor Amplifier Output Swing

RL

=

=

100 Hz

10k, AC Load

THD, All Amplifiers

At 1 kHz, 40 dB Closed Loop Gain

Record-Playback Switching Time

As in Test Circuit

Input ALC Range

.

(I)

1M

~
-

l •

~II
n

-==

I

.n

15

14

1 F

I'

"

""""" _

ORIVE
METER
8
9

..

;:

~

':"

""

I

~!'
•

20k

200
VI'"•

...""
...
RECORD

T

, - - 0.01 pF

20k

3.9k

~>

""

,J

L~~------~.~ ~
l------1PL3---::-~;--~::--~-

J'+~

rAA
5.1k

2 /F & T MONITOR INPUT

...

1

~OMONITOROUTPUT -

~-Io.I
~~10k

_

T

- - O.11'F

T
-_
__

._--'-

2pF _

FIGURE 2. General Test Circuit

TL/H/7894-2

r

:s::
....
....CDCD

Test Circuits (Continued)
SHIELDED
TEST

BOX

I
I

RIP

RECORD

LOGIC

~ PLAY
VCC

AUTO

LEVEL

3.16k

14
6V

lk

13

100

+

T

':'

':'

10

T

470""

I

..J
4.14k

2k

470""

Q

4 POLE

20 Hz-20 kHz
FIL TER

VN X 10.000

TLfH17894-3

FIGURE 3. Noise Test Circuit

II

1-139

co
....
co
....

Equivalent Schematic Diagram

::!E

..J

TLIHI7894-4

FIGURE 4

1·140

rES:
co
co

......

Typical Performance Characteristics
Automatic Level Control
(ALC) Response Characteristic
-10

I~

~

Preamp Input Noise Voltage
10k .-n-n--.-TT-rr-.-.rrr-,

-20

!«1oU~_
~

~~~

-30 Ir

i

1k

"w
'"'"=>

100

...

H-tIl--HtIl--HtHi't-

~

z
0:_

@

-h~~~7-.!.!'...-':I::';';;-l

Preamp Input Noise Current
r-rrn-~n-n-'-TT-rr,

0

c;

"
...~

-40

C>~

>8

i -50

10

."

1.0

~

0.1

~

-60

>

:;

-70 L..l.L!LL-_---"_ _ _ _....J

0.1

10

100

lk

10k

100

VIN ImVrmsl

lk

10k

I

"

FREQUENCY (Hz)

10

100

lk

10k

FREOUENCY 1Hz)

TL/H/7894-5

Application Hints
transistor. The amplifiers are stable for all gains above 5
and have a typical open loop gain of 100 dB. R8 and R9
enable C6 to be quickly charged and set the DC gain. Internal biasing provides a DC voltage independent of ~emper~­
ture at pin 17 so that the preamplifier DC output will r~m~n
relatively constant with temperature. Supply decouphng IS
provided by an internal regulator. Additional deco~pling can
be added for the input stages by increasing the size of the
capacitor on pin 20 of the IC. A fast charging circuit is connected to the preamplifiers' input capacitors (pins 16 and
17) to decrease the turn-ON time. Larger input capacitors
decrease the noise by reducing the source impedance at
lower frequencies where 1If noise current produces an input noise voltage. The input resistance of the preamplifiers
is typically 50 kO.

PREAMPLIFIERS (Rgure 5)
There are 2 identical preamplifiers with 1 common output
pin on the IC. One amplifies low level inputs such as a microphone in the record mode and another amplifies the signal from the playback head in the playback mode. The amplifiers use a common capacitor, C6, to set the low frequency pole of the closed loop responses. On the playback amplifier, the collector of the input device is made availa.ble ~o
that an external low noise device can be connected In cntical applications. When using an external low noise transistor, pins 17 and 18 of the IC are shorted together to ensure
that the internal input transistor is turned OFF and the external transistor's collector is tied to pin 19. The input and
feedback connections are now made to the external input

Quiescent DC Output Voltage

500

20

VCC

voc= (1 +~) (O.5-50xlO- 6 R2)VifR2+R3>10 RE

30k

19
14

1.2V

where RE

RBR9
RS + R9

AC Voltage Gain

SDk

V+(QUIESCENTIo 0.5 Voe

+

17

=

II

R3

R4+~

R3

18

AAC=

R2

+1

R4

0.5Vac

C5
R2

+

"*

R9

AV
C6

1.2V

RS

SDk

TL/H/7894-7

16

TL/H17894-6

FIGURE 5. Preamplifier

1-141

m.-----------------------------------------------------~
.,...

m
.,...

::E
-I

Application Hints (Continued)
MONITOR AND RECORD AMPLIFIERS (Figure 6)
The monitor and record amplifiers share common input and
feedback connections but have separate outputs. During
playback, the input signal is amplified and appears only at
the playback monitor output. Because the outputs are separate, different feedback components can be used and, as a
result, totally different responses can be set. The amplifiers
are stable for all closed loop gains above 3 and have an
open loop gain of typically 80 dB. The outputs are capable
of supplying a minimum of 400 ",A into a load and swing
within 500 mV of either Vee or ground. If more than 400 ",A
is needed to drive a load, an external pull-up resistor on the
output of these amplifiers can increase the load driving capability.

ed transistor. The impedance of the saturated transistor
forms a voltage divider with the source impedance of a series resistor (Rl in Figure 9). The input signal is decreased
as the ALC transistor is increasingly forward biased. The
ALC transistor will be forward biased when the preamplifiers's AC output (pin 14), coupled to the combination ALCmeter drive input (pin 4) reaches 40 mV peak (25 mVrms).
The gain of the ALC loop is such that a preamp input signal
increase of 10 dB will result in a 2 dB increase on the AC
output of the preamplifier. If greater than 25 mVrms is desired at the output of the preamp, a series resistor can be
added between the preamp output coupling capacitor and
the ALC input (pin 4). The input Impedance of the ALC circuit is 2 kll; therefore, if a 2 kll series resistor is added,
ALC action will begin at 50 mVrms.

AUTOMATIC LEVEL CONTROL-ALC (Figure 7)
The automatic level control provides a constant output level
for a wide range of record source input levels. The ALC
works on the varying impedance characteristic of a saturat-

The ALC memory capacitor connected to pin 6 has the additional function of amplifier anti-pop control; for this reason, it
is necessary that a capacitor be connected to pin 6 even if
ALC is not used.

Record gain

=1+

Playback gain = 1

Rll

R15
R14

+

Vccl2

R16
R14

Rl2

r--,.....VCC

R14

+

T

C12

RIG
TLIHI7894-8

FIGURE 6. Monitor Amplifier

1-142

r-

....s::
....

Application Hints (Continued)

QI)

VCC

QI)

VCC

...

T

CIJ
"::'

VCC
VCC

+

RIB

T

Cl4

TL/H/7894-9

FIGURE 7. Auto Level-Meter Circuit

meter output pin is between 0 Voc and 0.7 Voc there is a
50 ,..,A discharge current; when the pin is between 0.7V and
I.W there is no internal discharge current; and when the
voltage on pin 8 is greater than I.W there is a discharge
equivalent to a 3.3k resistor across the memory capacitor.
These different discharge rates allow the meter circuit to
display fast, accurate responses on the lower portion of the
meter display, slow responses in the higher portion of the
meter display, and rapid discharge when the voltage is
above the maximum reading the meter can display. The resistor in series with the meter can be adjusted such that the
previously mentioned responses coincide with the proper
points (0 VU and + 3 VU) on the meter scale.

METER DRIVING-MOTIONAL PEAK LEVEL
RESPONSE (Figure 7)

The meter drive output (pin 8) is capable of supplying 1-2
mA at a filtered DC voltage that is typically equal to 10 times
the RMS value of the signal applied to the ALC-meter drive
input (pin 4). The RC network connected to pin 7 of the IC
determines the memory constant of the meter circuit. It is
therefore possible to store the peak input signal by giving
this RC network a long time constant, or read the instantaneous signal level by giving this RC network a very short
time constant (Le., no capacitor). This memory capacitor is
discharged within the integrated circuit at a discharge rate
related to the DC level on the meter output pin. When the

II

1-143

co r---------------------------------------------------------------------------------,
.,...
co
.,...
Application Hints (Continued)
:iii
....I

Anti-Pop Circuitry (Figure 8)

t2=R13Cllln[ Vec]_
0.3Vec

The capacitor on pin 3 is used in a time delay system in
conjunction with C13, the ALC capacitor, to suppress pops
when switching between record and playback. Figure 8 illustrates how this is done. The output amplifier, either record or
playback, is shut off prior to switching and carefully rebiased
after switching takes place. It is therefore required that a
proper ratio is selected between the ALC capacitor and the
logic input RC time constant. The ALC capacitor must be
discharged to 0.7V within the time it takes the logic input
capacitor to: 1) charge from Vec/2 to 0.7 Vee when switching from record to playback, or 2) discharge from Vee/2 to
0.3 Vee when switching from playback to record. These
times would normally be similar; however, the ALC capacitor
can be charged to a different initial value depending upon
the input to the ALC circuit. The maximum value to which
the ALC memory capacitor will normally charge is 3.2V,
therefore, the maximum time allowed for discharging C13 is
given by:
tl = (C13

R13 Cll In [

To be sure that C13 is completely discharged, let t2 > tl.
R13Cll

>....!.!.... =
0.51

(72ms) = 141 ms
0.51

If Cll = 10 p.F, R13 = 15 kO
R13 should be kept to a value less than 50 kO to insure that
bias current existing from pin 3 does not cause an offset
voltage above 200 mV. Typically this bias current is less
than 3 p.A.
Record Playback Switch
When the voltage on pin 3 of the IC is greater than 0.5 Vee,
the internal record-playback switch switches into the playback mode. During playback the record preamplifier remains partially biased but the input signal to this preamp
does not appear at the preamplifier output. In addition, during the playback mode, the record monitor output (pin 9) is
disabled and the ALC circuit operates to minimize the signal
into the record preamp input. The meter circuit is operational in the playback as well as the record mode. Similarly,
during the record mode, the playback preamp input is ignored and the playback monitor output is disabled. In addition, a pin is available to hold one side of the record head at
ground potential while sinking up to 500 p.A of AC bias and
record current.

x !:..V) = C13 (3.2V - 0.7V)
11

Veve ] = 0.51 R13 Cll
0.5 ec

350 p.A

= C13 X 7.2 X 104
IfC13 = 10p.F,tl = 72ms
It is now necessary to determine the minimum value for the
RIP logic capacitor. This is done by computing the time
between the 2 voltage switching points using the exponential equations for a single RC network.

INTERNAL RECORD
PLAYBACK SWITCH

RIP
SWITCH

Rl3

o
VCC

GNO
TUH17894-10

FIGURE SA. Anti-Pop Circuit

1-144

.-3:

......

Application Hints (Continued)
EXTERNAL
RIP
SWITCH

PREAMP
OUTPUT
PIN 14

PLAY

Mg~~~~~

C)

0
VCC - - - - - - - - - - -

PIN 3 0.7 VCC
LOGIC 0.5 VCC
CAP 0.3 VCC

PIN 6
ALe CAP

C)

VCC

------

---

::=:::::::::===~----~= ~--=-~-~---~--------

2V
0.7V

Vcc/2 -lll4I\1otl:ttllIWllIWM~~-+"""+--_""""""---'i
SWITCHING _ .
OCCURS MONITOR
AMPLIFIER OUTPUTS
DISABLED
VCc/2

r

I.

.1.

., ..

Jj,

1J1',..I..-_..........._ ....~.."""'~.~.,.__11-

.

PIN 9
TLlH/7894-11

FIGURE BB. Waveform for Anti-Pop Circuit

External Components (Refer to Figure 9, Monaural Application Circuit)
Component

External Component Function

Normal Range
of Value
5000-20 kO

R1

Used in conjunction with varying impedance of pin 5, forming a resistor divider
network to reduce input level in automatic level control circuit.

C2

Forms a noise reduction system by varying bandwidth as a function of the
changing impedance on pin 5. With a small input signal, the bandwidth is
reduced by R1 and C2. As the input level increases, so does the bandwidth.

C1,C3

Coupling capacitors. Because these are part of the source impedance, it is
important to use the larger values to keep low frequency source impedance at
a minimum.

0.5 ",F-10 ",F

C4

Radio frequency interference roll-off capacitor

100 pF-300 pF

R2
R3
R4
C5

Playback response equalization. C5 and R3 form a pole in the amplifier
response at 50 Hz. C5 and R4 form a zero in the response at 1.3 kHz for
120
equalization and 2.3 kHz for 70
equalization.

500-2000
47 kO-3.3 MO
2kO-200 kO

R5
R6

Microphone preamplifier gain equalization

R7
RB
R9
C6
C7

DC feedback path. Provides a low impedance path to the negative input in
order to sink the 50 ",A negative input amplifier current. C6, R9, R7 and C7
provide isolation from the output so that adequate gain can be obtained at 20
Hz. This 2-pole technique also provides fast turn-ON settling time.

"'S

"'S

0.01 ",F-0.5 ",F

500-2000
5 kO-200kO
0-2kO
2000-5kO
1 kO-30kO
200 ",F-1000 ",F
0-100 ",F

CB

Preamplifier output to monitor amplifier input coupling

0.05 ",F-1 ",F

C9

ALC coupling capacitor. Note that ALC input impedance is 2 kO

0.1 ",F-5 ",F

R10
R11
R12
C10

These components bias the monitor amplifier output to half supply since the
amplifier is unity gain at DC. This allows for maximum output swing on a
varying supply.

1-145

10kO-100 kO
10kO-100 kO
10 kO-100 kO
1 ",F-100 ",F

II

....coco
....

External Components (Refer to Figure 9, Monaural Application Circuit) (Continued)

:!l
....I

Component

External Component Function

Normal Range
of Value

C11
R13

Exponentially falling or rising signal on pin 3 determines sequencing, time
delay, and operational mode of the record/play anti-pop circuitry. See antipop diagram.

0-10 ",F
0-50kO

R14
R15
R16
C12

R16, R14 and C12 determine monitor amplifier response in the play mode.
R 15, R14 and C12 determine monitor amplifier response in the record mode.

1k-100k
30kO-3 MO
30kO-3MO
0.1 ",F-20 ",F

C13
R17

Determines decay response on ALC characteristic and reduces amplifier pop

5 ",F-20",F
100k-oo

C14
R18

Determines time constant of meter driving circuitry

0.1 ",F-10 ",F
100k-oo
10 kO-100 kO

R19

Meter sensitivity adjust

C15

Record output DC blocking capacitor

C16

Play output DC blocking capacitor

0.1 ",F-10",F

C17
R21
R22

Changes record output response to approximate a constant current output in
conjunction with record head impedance resulting in proper recording
equalization

500 pF-0.1",F
5 kO-100kO
5 kO-100 kO

C18

Preamplifier supply decoupling capacitor. Note that large value capacitor will
increase turn-ON time

0.1 ",F-500 ",F

C19

Supply decoupling capacitor

C20

Decouples bias oscillator supply

R23

Allows bias level adjustment

R24

Adjusts DC erase current in DC erase machines (for AC erase, see "Stereo
Application Circuit," Figure 1)

L1
C21

Optional bias trap

C22

Bias Roll-Off

H1

Record/play head

H2

Erase head (DC type, AC optional)

1 ",F-10 ",F

100 ",F-1000 ",F
10 ",F-500",F
0-1 kO

1 mH-30 mH
100 pF-2000 pF
0.001 ",F-0.01 ",F
1000-5000;
70mH-300 mH
100-3000

1-146

r-

Typical Applications

3:
.....
co
.....

(Continued)

co

MIC/LINE
INPUT

...----_-_v,

R2

200

RS

R,

300

.

,R'

RID
100.

RI2

lOOk

'DO

.---+-'W_+v,

PLAY RECORD

~=---------------------~----~

TOKD BIAS OSCILLATOR BLOCK
NO. 721BDR-1D1BN USES

v,

OSCILLATOR COIL NO. 715YS·1033TM
'-35kHz

RI3

"
TOKO America. Inc.
1250 Feehanville Drive
Mount

Prospec~

IL 60056

TEL: (312) 297-0070

R20

U.
TL/H17894-12

FIGURE 9A. Monaural Application Circuit

1-147

II

co
....
co
....
:::!!i

Typical Applications

(Continued)

10

...I

-3 d8 PIN 9 PLAY8ACK MONITOR
-10

!

-20

:::,

-30

E

m

~

/

-23 dB PIN 14 PREAMP O~

-40

e

~

..iii

-50
-60
-70

/

/

10

or.,.

MONOUT-

~

i::,

-30

m

e

$
~

/

-14 dB PIN 10 RECORD MONITOR
-20

>E

/

-10

~

- - 7 2 dB HEAD INPUT 400 Hz

-80

or

/
-34 dB PIN 14 PREAMP OUTPUy

-40
-50
-60

-li4 d8 MIC INPUT

-70

'\.

/

/

/

'-----"-74 dB PIN 18 ALC IN LIMITING

-80
PLAY

RECORD

TL/H/7894-13

FIGURE 98. Level Diagram for Monaural Application Circuit

1-148

TLlH/7894-14

NatiOnal

~ Semiconductor
Corporation

LM 1837 low Noise Preamplifier for
Autoreversing Tape Playback Systems
The LMl B37 is a dual autoreversing high gain tape preamplifier for applications requiring optimum noise performance.
It has forward (left, right) and reverse (left, right) inputs
which are selectable through a high impedance logic pin. It
is an ideal choice for a tape playback amplifier when a combination of low noise, auto reversing, good power supply rejection, and no power-up transients are desired. The application also provides transient-free muting with a single pole
grounding switch.

Features
III
Ii
III

Low noise-D.6 !'-V CCIR/ARM in a DIN circuit referenced to 1 kHz
r!.I Low voltage battery operation -4V
IilI Wide gain bandwidth due to broadband two-amplifier
approach-76 dB @ 20 kHz
fII High power supply rejection-95 dB
III Low distortion-D.D3%
11,\ Fast slew rate-6V /!,-s
II Short circuit protection
III Internal diodes for diode switching applications
I!lI Low cost external parts
9 Excellent low frequency response
III Prevents "click" from being recorded onto the tape during power supply cycling in tape playback applications
Il High impedance logic pin for forward/reverse switching
GI

General Description

Programmable turn-on delay
Transient-free power-up-no pops
Transient-free muting

R5
1.2M

Vcc=12 VDC

R2
10k Rl
10k

5(4)

C2
10,F
3V

~

R4
56k
5%

Cl
0.0022,F
5%

R3
1.5Mn
5%

2(1)

3(2)

RIGHT
OUTPUT

1

RIGHT FORWARD
INPUT

R6
10k

RIGHT REVERSE
INPUT

II

LEFT FORWARD
INPUT

10k

.------1+

LEFT
OUTPUT

18

LEFT REVERSE
INPUT
14
(131

16
(15)

10k
Numbers in parentheses are for
Small Outline package.

LOGIC
FORWARDsO.5V
REVERSE" 2.2V

+ 3V
10k

"'Not bonded out in Small Outline
package.

15
(14)
0.0022 "F
5%

~10"F

56k
5%

270k

R7
270k

J\Mr!J\Mr
1.5M
5%

lOPTIONAL MUTE

1.2M

~~r-~--------~----~
TL/H17902-1

FIGURE 1. Autoreversing Tape Playback Application
1-149

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
18V
Voltage on Pins 1 and 18
Package Dissipation (Note 1)
Storage Temperature
Operating Temperature

Soldering Information
Dual-In-line Package
Soldering (10 seconds)
260"C
Small Outline Package
215·C
Vapor Phase (60 seconds)
220·C
Inlrared (15 seconds)
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" lor other methods 01 soldering surface mount devices.

18V
1390mW
-65·C to + 150·C
O·Cto +70·C

Minimum Voltage on Any Pin

-0.1 voe

Electrical Characteristics (TA =

25·C, Vee = 12V,seeTestCircuit,Figure2)

Parameter
Operating Supply Voltage Range

Conditions
R5 Removed Irom Circuit lor
Low Voltage Operation

Min

Typ

4

Supply Current

Vee = 12V

Total Harmonic Distortion

f = 1 kHz, VIN = 0.3 mV,
Pins 2 and 17, Figure 2

0.03

THD + Noise (Note 2)

I = 1 kHz, VOUT = 1V,
Pins 2 and 17, Figure 2

0.10

9

Power Supply Rejection

Input Rei. I = 1 kHz, 1 Vrms

Channel Separation (Note 3)
Left to Right
Forward to Reverse

I = 1 kHz, Output = 1 Vrms,
Output to Output

Signal-to-Noise (Note 4)

Noise
Input Amplilers
Input Bias Current
Input Impedance
ACGain
AC Gain Imbalance
DC Output Voltage
DC Output Voltage Mismatch
Output Source Current
Output Sink Current

Units

18

V

15

mA
%

0.25

%

80

95

dB

40
40

60
60

dB
dB
dB

Unweighted 32 Hz-12.74 kHz (Note 2)
CCIR/ARM (Note 5)
A Weighted
CCIR, Peak (Note 6)

58
62
64
52

dB
dB
dB
dB

Output Voltage CCIRI ARM (Note 5)

120

200

/LV

0.5

2.0

28
±0.15
2.5
±30
10
600

29
±0.5
2.9
200

/LA
kO
dB
dB
V
mV
mA
/LA

f = 1 kHz

150
27
2.1
-200
2
300

Pins 5 and 14
Pins 5 and 14
Pins 5 and 14

Logic Level
Forward
Reverse

0.5
2.2

Logic Pin Current
DC Voltage Change at
Pins 5 and 14

Max

-100

Change Logic State

1·150

V
V

2

6

/LA

±20

100

mV

r-

Electrical Characteristics (TA =

.....
==

25'C, Vee = 12V, see Test Circuit, Figure 2) (Continued)

co
Co)

Parameter
Output Amplifiers
Closed Loop Gain
Open Loop Voltage Gain
Gain Bandwidth Product
Slew Rate
Input Offset Voltage
Input Offset Current
Input Bias Current
Output Source Current
Output Sink Current
Outut Voltage Swing
Output Diode Leakage

Conditions

Min

Typ

Max

5

Stable Operation
DC

100

5
6

2

Pin20r 17
Pin20r 17
Pin 2 or 17

2
400

Voltage on Pins 1 and 18 = 18V

20
250
10
900
11

o

5
100
500

10

Units

.......

VIV
dB
MHz
V/p.s
mV
nA
nA
rnA
p.A
Vp-p
p.A

Note 1: For operation in ambient temperatures above 25°C, the device must be derated based on a 1500C maximum junction temperature and a thermal resistance
of 900C/W junction to ambient (Dual-In-Line). Small Outline Thermal Resistance is 100·C/W.
Note 2: Measured with an average responding voltmeter using the filter circuit in Figure 4. This simple filter is approximately equivalent to a "brick wall" filter with a
passband of 20 Hz to 20 kHz (see Application Hints). For 1 kHz THO the 400 Hz high pass filter on the distortion analyzer is used.
Note 3: Channel separation can be measured by applying the input Signal through transformers to simUlate a floating source (see Application Hints). Care must be
taken to shield the coils from extraneous signals. Actual production test techniques at National simulate this floating source with a more complex op amp circuit.
Note 4: The numbers are referred to an output level of 160 mV at pins 2 and 17 using the circuit of Figure 2. This corresponds to an input level of 0.3 mVrms at 333
Hz.

Note 5: Measured with an average responding voltmeter using the Dolby lab's standard CCIR filter having a unity gain reference at 2 kHz.
Note 6: Measured using the Rhode-Schwarz psophometer, model UPGR.

II

1-151

~
Cf)

co
,...

,--------------------------------------------------------------------------,
Typical Performance Characteristics

:i
Input Amplifier THO
vs Input Level

5.0

§:
z

~
co

INPUT AMPUFIER ONLY
Vce=12V
4.0 .=1 kHz

40

I-- I-- GAIN

-'

If'.

20

!z

u

:i'i
%

...'"

2.0
1.0

i!!

I'!

o
o

20

40

160

'"

60

80

120 I--

30

30

l - t--

is

.

Output Amplifier Open
Loop Gain and Phase
vs Frequency

"'lASE

I;; 3.0

iii

Input Amplifier Gain and
Phase vs Frequency

10

\
\

60

:!!

~

...

80

90

~

:z

40

120

.§

120

,

~

180
240

150

-40

-20

UO

-60

10 100 lk 10k lOOk 1M 10M 100M

INPUT (mVrms)

60

I-- GAIii' I':

~

-10

100

~ PH~E
to-..

""

~

I

.!!

300

360

10 100 lk 10k lOOk 1M 10M 100M
FREQUENCY (Hz)

FREQUENCY 1Hz)

TUH17902-2

Spot Noise Voltage
vs Frequency

100

Total Harmonic Distortion
vs Frequency

Spot Noise Current
vs Frequency
10.0

~

1=
~

§:

1 0 " .

;

l-

I-

ill

:z
co

2.0
1.0
I;;
is 0.5

~

'"

u

iii
:Ii 0.1
~ 0.05

!§
u

w

Irl
:z
1 L..l...l..J..Will-L.l.J..LWJ1..-LLJ..llUU

10

100
lk
FREQUENCY (Hz)

;;!
~ 0.02

0.1

I

III 300

...
~

250

.;

:g

1
.;

/I

/I

l.,

7

t! t!" "
~ 200 ~ Ii
il
~
=
co 150
ts
II
:z 100
...'" 50
II II
co

I-

u

o

~ .I I'" r..

o

0.2 0.4 0.6 0.8 1.0 1.2
TURN-ON TIME DELAY (SECONDS)

100
lk
FREQUENCY (Hz)

L

--

THO USING 4TH ORDER
2D Hz-20 kHz FILTER

TTT

1

THO USING WAVE ANALYZER

I I I

I
20

10k

100

500

2k

10k

FREQUENCY (Hz)

PSRR vs Frequency
120

II

-b"

I I I

THD WITHOUT~ILTh.

TLIHI7902-3

Turn-On Delay vs
Component Values
and Gain
350

Vorr,l ~m.

0.01
10

10k

CIRCUIT OF FIGURE 2

5.0

PSRRvsVCC
120

INPUT REFERRED
CIRCUIT OF FIGURE 2

100

;

80

~

60

100

"'",

ii;'

80

'"
'"Ie

60

:!:!.

40

-

.....
INPUT REFERRED
CIRCUIT OF FIGURE 2
R5 REMOVED
1=1 kHz
Av=47 d8 @ 1 kHz

40
IVceti
20

20
20 50100200 500 lk 2k 5k 10k 20k
FREQUENCY (Hz)

4

8

10 12
Vee (V)

14

16

18

TLIH17902-4

1-152

r-----------------------------------------------------------------------------, r
i:
....
Typical Performance Characteristics (Continued)
co
Co)

Right to Left Channel
Separation vs Frequency

ICC vs VCC

12 r-r--r:";;",.--,---r---r---,

80

l°CWHi§

'"
:z:
'"
~
~

8

:<
§.

' \ R5 REMOVED

a:

6

J;l

~

.
-'
w

4

:z:
:z:

2

is

70r-'-.-~~~_~~

CIRCUIT OF FIGURE 2

60

r

50

....... 1--"

r

CIRCUIT OF FIGURE 2

~ 60r-~+-t-+-+-~+-~

r'\

15
'''~ 501--+-+-1--+-~1--+1'~-I

~

1\

40

~

4

6

8

10 12

14

\

401--+-+-1--+-~1--+-~

:z:

~ 301--+-+-1--+-+-1--+-~

30
20L-~L-L-~L-L-L-~

0

20L-~L-L-L-~L-L-~

20 50100200500 lk 2k 5k lok2ok

16 18

20 50 100200 500 lk 2k 5k 10k20k
FREQUENCY (Hz)

FREQUENCY (Hz)

Vee (V)

TLlH17902-5

Input Amplifier DC Output
Voltage vs Temperature
(Pins 5,14)

3.0

r-.,--T---r---r-,.---r--,

~
III 2.5
~

1::;;:I;;;*'-F9=9F=f;;;;;;J

s:

2.0

1---+-+-+-+---11--1---1

~

1.5

1---+-+-+-+---11--1---1

5

......

Forward to Reverse
Channel Separation
vs Frequency

2l 1.0 1--+-+--+--+---11--+--1

lif

0.5

1---+-+-+-+---11--1---1

OL-~~~-L~~~

-50 -25 0

25

50

75 100 125

TEMPERATURE ('C)
TLlH17902-6

Connection Diagrams
Small Outline Package

Dual·ln·Line Package

RIGHT OUTPUT -

1

16 - LEfT OUTPUT

R(+)IN -

2

15 -L(+)IN

R(-)IN -

3

14 -L(-)IN

RIGHT OUTPUT
R(+) IN

RIGHT X25 OUT -

4

13 - LEfT X25 OUT

BIAS -

5

12 -LOGIC

RIGHTFORWARD INPUT -

6

11 - LEfT FORWARD INPUT

RIGHT REVERSE INPUT -

7

10 - LEfT REVERSE INPUT

V+- 8

~

RIGHT DIODE OUTPUT ...!

r!! LEFT OUTPUT
r!!! l(+) IN

11-

15
rL(-) IN

.!
RIGHT X25 OUT .!
BIAS .!
RIGHT FORWARD INPUT .2
RIGHT REVERSE INPUT .!
v+ .!
R(-) IN

9 -GND
TLIH17902-7

Order Number LM1837M
See NS Package Number M16B

LEFT DIODE OUTPUT

~

LEFT X25 OUT

~ LOGIC
~ LEFT FORWARD INPUT

r!!. LEFT REVERSE INPUT
r!!! GND
TLlH17902-8

Top View
Order Number LM1837N
See NS Package Number N18A

1-153

II

External Components (Figure 1)
Component Normal Range of Value and Function
R1, C2
2 kO-40 kO, 0.1 /l-F-10 /l-F (low leakage)

R2, R3

R4, C1

Component Normal Range of Value and Function
R6
2 kO-47 kO

Set turn-on delay and second amplifier's low
frequency pole. Leakage current in C2 results
in DC offset between the amplifier's inputs
and therefore this current should be kept low.
R1 is set equal to R2 such that any input offset voltage due to bias current is effectively
cancelled. An input offset voltage is generated by the input offset current multiplied by
the value of these resistors.
2 kO-40 kO, 500 kO-10 MO
Sets the DC and low frequency gain of the
output amplifier. The total input offset voltage
will also be multiplied by the DC gain of this
amplifier. It is therefore essential to keep the
input offset voltage specification in mind
when employing high DC gain in the output
amplifier; i.e., 5 mV x 400 = 2V offset at the
output.

C3

R5

Biases the output diode when it is used in DC
switching applications. This resistor can be
excluded if diode switching is not desired.
100 pF-1000 pF
Often used to resonate with tape head in order to compensate for tape play-back losses
including tape head gap and eddy current.
For a typical cassette tape head, the resonant frequency selected is usually between
13 kHz and 17 kHz.
100 kO-10 MO
Increases the output DC bias voltage from
the nominal 2.5V value (see Application
Hints).

R7

Optionally used for tape muting. The use of
this resistor can also provide "no-pop" turnoff if desired (see Application Hints).

10 kO-200 kO, 0.00047 /l-F-O.01 /l-F
Set tape playback equalization characteristics in conjunction with R3 (calculations for
the component values are included in the Application Hints section).

Simplified Schematic

7,12

5,14

B,11

4,15

3.16

2,17

1,18
TLlH17902-9

1-154

Application Hints

Vee
12V

Cl

Rl

O.0022I'F

10k

2%

LM1837
OUTPUT
OUTPUT
SELECT

INPUT 100 pF

@+l

.------1+

~

y-

\oJ

18

REF L-.....,r::;---b--+.:;----;;+::::-::---tl;-;;5~1~.4;-:M;;:O:--t17;------l
1%

54.9k
1%

TL/HI7902-10

FIGURE 2. General Test Circuit

80
70
~

60

z

g

50

40

CIRCUIT OF FIGURE 2

r"~

INPUT
FROM LM1837
PINS 2 DR 17

o

I'

"'r-

HP334A DISTORTION ANALYZER I
VOLTMETER

1-1-

TUH/7902-12

FIGURE 4. Simple 32 Hz-12740 Hz Filter and Meter

3D

20 50100200 500 lk 2k 5k 10k 20k
FREQUENCY (Hzl
TL/H17902-11

FIGURE 3. Frequency Response of
Test Circuit

1·155

II

Application Hints (Continued)
DISTORTION MEASUREMENT METHOD

SIGNAL-TQ-NOISE RATIO

In order to clearly interpret and compare specifications and
measurements for low noise preamplifiers, it is necessary to
understand several basic concepts of noise. An obvious example is the measurement of total harmonic distortion at
very low input signal levels. Distortion analyzers provide outputs which allow viewing of the distortion products on an
oscilloscope. The oscilloscope often reveals that the "distortion" being measured contains 1) distortion, 2) noise, and
3) 50 or 60 cycle AC line hum.
Line hum can be detected by using the "line sync" on the
oscilloscope (horizontal sync selector). The triggering of a
constant waveform indicates that AC line pick-up is present.
This is usually the result of electro-magnetic coupling into
the preamplifiers input or improper test equipment grounding, which simply must be eliminated before making further
measurements!
Input coupling problems can usually be corrected by any
one of the following solutions: 1) shielding the source of the
magnetic field (using mu metal or steel), 2) magnetically
shielding the preamplifier, 3) physically moving the preamplifier far enough away from the magnetic field, or 4) using a
high pass filter (fo = 200 Hz-1 kHz) at the output of the
preamplifier to prevent any line signal from entering the distortion analyzer. Ground loop problems can be solved by
rearranging ground connections of the circuit and test
equipment.

In the measurement of the signal-to-noise ratio, misinterpretations of the numbers actually measured are common. One
amplifier may sound much quieter than another, but due to
improper testing techniques, they appear equal in measurements. This is often the case when comparing integrated
circuit to discrete preamplifier designs. Discrete transistor
preamps often "run out of gain" at high frequencies and
therefore have small bandwidths to noise as indicated in
Figure 5.
80
DISCRETE
iii

:s

60

,,
,

z

~

- - , IC

40

\,
20

200

2k 2Dk 2DDk 2M
FREQUENCY (Hz)
TL/H17902-13

FIGURE 5
Integrated circuits have additional open loop gain allowing
additional feedback loop gain in order to lower harmonic
distortion and improve frequency response. It is this additional bandwidth that can lead to erroneous signal-to-noise
measurements if not considered during the measurement
process. In the typical example above, the difference in
bandwidth appears small on a log scale but the factor of 10
in bandwidth (200 kHz to 2 MHz) can result in a 10 dB
theoretical difference in the signal-to-noise ratio (white
noise is proportional to the square root of the bandwidth in a
system).

Separating noise from distortion products is necessary
when it is desired to find the actual distortion and not the
signal-to-noise ratio of an amplifier. The distortion produced
by the LM 1837 is predominantly a second harmonic. It is for
this reason that the third and higher order harmonics can be
filtered without resulting in any appreciable error in the measurement. The filter also reduces the amount of noise in the
measured data. Another more tedious technique for measuring THD is to use a wave analyzer. Each harmonic is
measured and then summed in an rms calculation. A typical
curve is plotted for distortion vs frequency using this method. A typical curve is also included using a 20 Hz to 20 kHz
4th order filter.
To specify the distortion of the LM1837 accurately and also
not require unusual or tedious measurements the following
method is used. The output level is set to 1 Vrms at 1 kHz
(apprOXimately 5 mV at the input). The output is filtered with
the circuit of Figure 4 to limit the bandwidth of the noise and
measured with a standard distortion analyzer. The analyzer
has a filter that is switched in to remove line hum and
ground loop pick-up as well as unrelated low frequency
noise. The resulting measurement is fast and accurate.

In comparing audio amplifiers it is necessary to measure the
magnitude of noise in the audible bandwidth by using a
"weighting" filter.1 A "weighting" filter alters the frequency
response in order to compensate for the average human
ear's sensitivity to certain undesirable frequency spectra.
The weighting filters at the same time provide the bandwidth
limiting as discussed in the previous paragraph.
The 32 Hz to 12740 Hz filter shown in Figure 4 is a simple
two pole, one zero filter, approximately equivalent to a
"brick wall" filter of 20 Hz to 20 kHz. This approximation is
absolutely valid if the noise has a flat energy spectrum over
the frequencies involved. In other words a measurement of
a noise source with constant spectral density through either
of the two filters would result in the same reading. The output frequency response of the two filters is shown in Figure

6.

1-156

Application Hints (Continued)
BASIC CIRCUIT APPROACH
The LM1837 IC incorporates a two stage broadband design
which minimizes noise, attains overall DC stability and prevents audible transients during turn-on.

rBANoWloTH--!

I

The first stage consists of four direct coupled preamplifiers
with internal gain of 25VIV (28 dB). Direct coupling to the
tape head reduces input source impedance and external
component cost by removing the input coupling capacitor. A
typical input coupling capacitor of 1 ".F has a reactance of
1.5 k!l at 100 Hz. The resulting noise due to the amplifier's
input noise current can dominate the noise voltage at the
output of the playback system. The inputs of the amplifiers
are biased from a common reference voltage that is temperature compensated to produce a quiescent DC voltage of
2.5V at the output of the first stage. The input stage bias
current that flows through the tape head is kept below 2 ".A
in order to prevent any erasure of tape moving past the
head. An added advantage of DC biasing is the prevention
of large current transients during the charging of coupling
capacitors at turn-on and turn-off. The outputs of the forward and reverse preamplifier are fed to the common output
op amp through a logic controlled switch.

I

NOISE A1

20

20k
FREQUENCY (Hz)
"BRICK WALL" FILTER
TL/H17902-14

iii'

:2.

III

~

:i!

t-BANoWloTH-1

,II\.

1/

0 f-3

r /'
"

NOISE A2

I

2032

1 '\.

12740 20k
32 Hz-1274o Hz FILTER
TL/H17902-15

The second stage provides additional gain and proper
equalization while preventing audible turn-on transients or
"pops". The output (pin 2) is kept low until C2 charges
through R1. When the voltage on C2 gets close to the DC
voltage on pin 5, the output rises exponentially to its final
DC value. The result is a transient-free turn-on characteristic.

FIGURE 6
Typical signal-to-noise figures are listed for several weighting filters which are commonly used in the measurement of
noise. The shape of all weighting filters is similar with the
peak of the curve usually occurring in the 3 kHz-7 kHz region as shown in Figure 1.

Internal diodes are provided to facilitate electronic diode
switching, popular in automotive applications.
The General Test Circuit illustrates the topography of the
system. The components determining the overall frequency
response are external due to the extreme sensitivity when
matching a DIN equalization curve.
20

MUTE CIRCUIT AND LOGIC

200

2k 6k 20k
FREQUENCY (Hz)

The LM1837 can be muted with the addition of two resistors
and a grounding switch, as shown in Figure 1. When the
circuit is not muted the additional resistors have no effect on
the AC performance. They do have an effect on the DC Q
point however.

TUH17902-16

FIGURE 7
In addition to noise filtering, differing meter types give different noise readings. Meter responses include: 1) rms reading, 2) average responding, 3) peak reading, and 4) quasi
peak reading. Although theoretical noise analysis is derived
using true rms (root mean square) based calculations, most
actual measurement is taken with ARM (Average Responding Meter) test equipment.

The difference in the DC output voltages of the input amplifiers is applied across the mute resistors (R7) and the positive input resistors (R 1). This results in an additional offset
at the input of the output amplifiers. To keep this offset to a
minimum R7 should be as large as possible to achieve effective muting. Unmute voltage is the peak signal the preamplifier can swing without turning on the output amplifier
under mute conditions:

Unless otherwise noted an average responding meter is
used for all AC measurements in this data sheet.

Unmute
[R511R3
R7]
voltage = VPIN 5, 14 R2 + R511R3 - R1 + R7

1-157

II

r-

C')

co
.,...
:!!

....

r------------------------------------------------------------------------------------------,
Application Hints (Continued)
For example: The circuit in Figure 1 has 2.5V DC at pins 5
and 14, so:
Unmute voltage =

We can now solve for Cl as a function of R2, or:

Av(1 kHz) = -25l

1.2Mlll.5M
270k]
[
2.5V 10k + 1.2Mlll.5M - 10k + 270K = 52.3 mV

[21TC1~1326J [~1TC1;51.96)] 1

(1.663)

[ R2 21TCI (50J

(5)

It may be necessary to slow the transition of the logic pin if
-4.80 X 10- 3
Cl = R2 IAv (1 kHz)]

the mute circuit is not used. The forward and reverse preamplifier output DC voltages can differ by ± 100 mY. This
rapid DC charge is gained up by the output amplifier and
appears as a pop. The circuit of Figure 8 will slow the DC
transition.

When chromium dioxide is used, the defined time constants
are 3180
and 70 ,,"s. This changes equation (3) to:
1
R4 - 21TC1(2274 Hz)
(7)

""S

V+=12V

hr

The value of R3 is normally not changed. This results in an
error of less than 0.2 dB in the low frequency response.
The output voltage of the LM1837 is set by the input amplifier DC voltage at pin 5 or 14, and by R3 and R5.

oOk1DDk

\"

+

;h

J;1~F

TO PIN 13

. VOUT (Pin
. 2 or 17) = 2.5 (1R
Nominal
+3
R5)

DESIGN EQUATIONS
The overall gain of the circuit is given by:

-R4R3]
(s
[
Av = 25 R2(R3 + R4) (s +

+

R5 =

2.5 R3
(9)
Vo - 2.5
The output voltage of the LM 1837 will vary from that given
in equation (8) due to variations in the input amplifier DC
voltage as well as the output amplifier input bias current,
input offset current and input offset voltage. The following
equation gives the worst-case variation in the output voltage
in either forward or reverse state.

~)
1

)

(1)

(R3 + R4)Cl
Standard cassette tapes require equalization of 3180 ,,"S (50
Hz) and 120
(1.3 kHz). These time constants result in an
AC gain at 1 kHz given by:

""S

t.VOUT = ± [t.VPIN3 (1

-R4R3 )
Av (1 kHz) = 25 ( R2(R3 + R4) 1.663

R3 (
R2 t.IBIAS (Rl - R2)

(2)

3180 ,,"sor50 HZ}
and
120
or 1326 Hz
Using the pole and zero locations of the transfer function,
the two other equations needed to solve for the component
values are:
R4 =

1
21TCI (1326 Hz)

(8)

Pins 1 and 18 are biased 0.7V less than VOUT(pin 2 or 17).
When these diodes are used the output (pin 2 or 17) should
be biased at one half the minimum operating supply voltage.
Equation (8) can be rewritten to solve for R5.

TL/H17902-17

FIGURE 8. Circuit to Slow Logic

{

(6)

+ ::) +

I

+ ~S (Rl + R2) + VOS

)](10)

USing the worst-case values in the electrical characteristics
reduces this to

""S

t.VOUT = ± [0.4 (1

:~ ( 200 nA (Rl

(3)

- R2)

+ ::) +

(11)

+ 50 nA (Rl + R2) + 5 mv) ]

Equation (10) does not incorporate the effect of mute resistors on the output voltage. The presence of mute resistors
causes an additional offset
t.V(pins 5-14)
t.VOUT(mute) = ± 2(Rl + R7) x Rl
(12)
For the circuit in Figure 1 worst-case:
400mV
t.VOUT(mute) = 2(20k + 270k)

x 1.5M

=

tv

This means that the output pins 2 and 17 would differ by 1V.
The trade off here is the amount of unmute voltage versus
the DC accuracy of pins 2 and 17.

1-158

Application Hints (Continued)
The turn-on delay is set by R1 and C2; delay can be approximated by:
.
Delay timet
= R1C2Ln ( -2.5- ) (R3)
VaDe
R2

(13)
"'---O-OUTPUT

EXAMPLE

If we desire a tape preamp with 100 mV output signal from a
tape head with a nominal output of 0.5 mV at 1 kHz for
standard ferric cassette tape, the external components are
determined as follows. The value of R2 is arbitrarily set to
10 kO.

TL/H/7902-18

FIGURE 9

R1 = R2 = 10k
This minimizes errors due to the output amplifier bias currents.
-4.80 X 10- 3
C1 =
[
] = 2400 pF _ 0.0022 ,..F
10 kO -100 mV
0.5mV
Use 0.0022 ,..F and determine:
R4

= 21TC1 ~1326) = 54.6 kO -

R3 = 21TC1 ;51.96) = 1.39 MO -

CROSSTALK AND CHANNEL SEPARATION

When two signal sources share a common reference point
which is separated from ground by a resistance, there will
always be some amount of interchannel crosstalk (the reciprocal of channel separation) induced. The coupling method of Figure 1 is examined to determine whether the induced crosstalk is acceptably low.
Figure 10 is the equivalent AC circuit for the connection
scheme of Figure 1. Rs is the Thevenin resistance of the
common bias point, RIN is the preamplifier input resistance,
Zs is the impedance of the playback head, and VS7, VS8,
VSl1, and VS12 are the open-circuit output voltages of the
sources. If we set VSB, VSl1, and VS12 equal to zero, we
can define crosstalk for this circuit as V121V7, where V7
and V12 are the AC signal voltages appearing at the two
preamplifier inputs, assuming Rs ..:: RIN/3.
The crosstalk can be shown to be:

54.9 kO 1%
1.4 M01 %

To bias the output amplifier output voltage at 6V (half supply):
R5 = 2.5(1.4 MO) = 1 MO
6 - 2.5
The maximum variation in the output is found using equation
(11):

V12

RB

V7
Rs + Zs + RIN/3
Since Zs is dependent on the measurement frequency and
the particular head used, we choose the worst-case condition and set Zs = o. The minimum value of RIN is 150 kO,
and Rs "" 1000. This yields a crosstalk figure of:

aVaUT = ±1.9V
The low frequency response and turn-on delay determine
the value of C2. For R1 = 10k and C2 = 10 ,..F the low
frequency 3 dB point is 1.6 Hz and the turn-on delay is 0.4
seconds, from equation (12).
The complete circuit is shown in Figure 2. A circuit with 5%
components and biased for a minimum supply of 10V .is
shown in Figure 1. If additional gain is needed R1 and R2
can be reduced without changing the frequency response of
the circuit.

V12 = ~ = -54dB
V7
50100
This is 14 dB better than the minimum guaranteed channel
separation, so the connection method of Figure 1 will provide acceptable crosstalk levels.
Reference 1: CCIRI ARM: A Practical Noise Measurement
Method; by Ray Dolby, David Robinson and Kenneth Gundry, AES Preprint No. 1353 (F-3).

DIODE SWITCHING
The LM1837 has a diode in series with each output for
source switching applications. The outputs of several functional blocks can be diode OR-connected as shown in Figure9.
By removing the power supply from the FM demodulator, its
output diode will be cut off by the LM1837 output DC voltage. R6 is used to bias ON the diode of the LM1837 when
power is applied to it. When the output is taken from pin 1 or
pin 18, the THD will be higher because of the current modulation in the diode.

1-159

II

~
C")

co
....
:::E

r----------------------------------------------------------------------------,
Application Hints (Continued)
VS7

....I

Vsa

RIGHT
FORWARD

lEFT
FORWARD
TUH17902-19

FIGURE 10. AC Equivalent of Figure 1

1·160

r-------------------------------------------------------------------------,

~ Semiconductor
NatiOnal

r

...s::

CD
.....
U'I

Corporation

LM 1875 20 Watt Power Audio Amplifier
General Description

Features

The LM1875 is a monolithic power amplifier offering very
low distortion and high quality performance for consumer
audio applications.

II Up to 30 watts output power

The LM1875 delivers 20 watts into a 4.0. or 8.0. load on
±25V supplies. Using an 8.0. load and ±30V supplies, over
30 watts of power may be delivered. The amplifier is designed to operate with a minimum of external components.
Device overload protection consists of both internal current
limit and thermal shutdown.

II Wide power bandwidth 70 kHz

The LM1875 design takes advantage of advanced circuit
techniques and processing to achieve extremely low distortion levels even at high output power levels. Other outstanding features include high gain, fast slew rate and a wide
power bandwidth, large output voltage swing, high current
capability, and a very wide supply range. The amplifier is
internally compensated and stable for gains of 10 or greater.

II Avo typically 90 dB
II Low distortion 0.015%, 1 kHz, 20 W
II Short circuit protection
II Thermal protection with parole circuit
II High current capability 3A
II Wide supply range 20V-60V
II Internal protection diodes
II 94 dB ripple rejection
II Plastic power package TO-220

Applications
II High performance audio systems
II Bridge amplifiers
II Stereo phonographs
II Servo amplifiers
II Instrument systems

Connection Diagram

Typical Applications
+ Vee
C3
O. lpF

~

v,.

411-811

-rj

t·

:~r
+IN
Vee

r

-=-

Cl
2.2pF

M

TLiH/S030-1

R5
1

-=-

TO.

C5

Front View

22 PF

R3
lk

Order Number LM187ST
See NS Package Number TOS8

TL/H/5030-2

1-161

II

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
60V
Input Voltage
-VEE to Vee
Operating Temperature
O·Cto + 70"C

-65·Cto

Storage Temperature
Junction Temperature

+ 150"C
150·C

Power Dissipation (Note 1)
Lead Temperature (Soldering, 10 seconds)

30W
260·C

Electrical Characteristics
Vee=

+ 25V,

-VEE= -25V, TTAB= 25·C, RL =8.0., Av=20 (26 dB), 10= 1 kHz, unless otherwise specilied.

Parameter

Conditions

Supply Current

POUT = OW

Typical

Tested Limits

Units

70

100

mA

DC Output Level
Output Power

THD=l%

THD

POUT=20W,lo =1 kHz
POUT=20W, 10=20 kHz
POUT=20W, RL =40,10=1 kHz
POUT=20W, RL =4.0.,10 =20 kHz

Offset Voltage
Input Bias Current

0

V

25

W

0.015
0.05
0.022
0.07
±1

±15

mV

±0.2

±2

/LA

0

±0.5

Input Offset Current
Gain-Bandwidth Product

10=20 kHz

5.5

Open Loop Gain

DC

90

PSRR

Vee, 1 kHz,l Vrms
VEE, 1 kHz, 1 Vrms

95
83

Max Slew Rate

20W, 80, 70 kHz BW

8

Current Limit

4

Equivalent Input Noise Voltage

0.6

%
%
%
%

0.4

Rs=6000, CCIR

/LA
MHz
dB

52
52

dB
dB
V//Ls

3

3

A
/LVrms

Note 1: Assumes TTAB equal to 60"C max. For operation at higher tab temperatures and at ambient temperatures greater than 25°C, the LM1875 must be derated
based on a maximum 150"C junction temperature. Thermal resistance depends upon device mounting techniques. 8JC is typically 2" C/W. See Application Hints.

Typical Applications

(Continued)
Typical Single Supply Operation
Hl
22k

-:!-

Cl

~pr
R4
1M

C4
Vee 0.1 ~F

H2
22k
..l!.C2
T1DI'F

=

{b.

'1":"

H3
22k

+ E-:lDD I'F

1~5

":"
4

LM1875

--.!

V

R7
1

3

C6

~~
=_
I

&5--

D.22~T

C3
lDI'F

p.:+

R5
10k

~R6
200k

TL/H/5030-3

1-162

Typical Performance Characteristics
THO vs Power Output
z

0.1
0.09
0.08

~

0.07

~

Vs ±Z5V

c>

~c;

'"'~

;; 0.05
~ 0.04

RL 40

~
'" := R\,,;;,~O
fI
'"
~ 0.01
illlill
0.1

Vs = ±Z5V
Po=10W

0.03
O.OZ

1'0
I""'"

1.0

0.01
0

100

10

\..

"""

- -It

RL=80

[..I

;

iJ! 20
0
5

10

20

15

....
0

5

25

45
40

,...

~
ili

'"

NE~ATIVE SUPPLY"'~

-

30

SUPPLY VOLTAGE (tV)

/

20
10 15
25
SUPPLY VOLTAGE (tV)

30

Device Dissipation vs
Ambient Temperaturet

~

iiic;

'"'"

II:

0

/

10

0

100
90
V
I
80
POSITIVE SUPPLY-1
70
60
f-50
Is'! 40
30 INPUT REFERRE'o
20 Rs=O
RL=4
10
1 Vrrns
0
ZO 50100200 500 lk Zk 5k 10k 20k
FREQUENCY (Hz)

"
,,""'"

40

15

PSRR vs Frequency

~

60

~

J

Zo

5

N

80

'"
3

/

25

FREQUENCY 1Hz)

100

~

RL=40

~
2:

ZO 50 100 zoo 500 lk Zk 5k 10k Zok

Supply Current vs Supply
Voltage

..

...~

i.

RL=sn
THO=I%

30

r-

I

POWER OUTPUT IW)

!!j
'"::0

35

~O.O6

0.1

:i

...~

Power Output vs Supply
Voltage

THO vs Frequency

1.0

..,...
~

.J.

INFINITE HEAT SINK

IN
FC/W HEAT SINK

35
30

zoc/w
~EATSINK

......
l~
I .,.....,."" i""""-....

Z5
20

5°C/W HEAT SINK

15
10

,.... .....

J I.,.... ~

5

lOT/WI HEAl SljK

0
0 10 ZO 30 40 50 60 70

80

TA-AMBIENT TEMPERATURE (OC)

=

tINTERFACE
I°C/W.
See Application Hints.

Power Dissipation vs
Power Output

~

:z
51

~

iiic;
'"

~

50
45
40
35
30

-

.

--

I

I
~! b..-I--

~ ~Vs=±Z5V

..-

50

Vs=±30V _

~--I---

~

--~-

25
20
15
10

Power Dissipation vs
Power Output

-"

~
ili

--

~
iii
c;

I

Vs= ±20V

,.. "'Vs= ± 15~

5
0

~

I
i RL=40

~

fO= 1 kHz

45
40
35
30
25
20
15
10
5
0

0

5

10

15

ZO

25

30

RL~80 I
fo =1

kH~

Vs= ±30V

r,/..

./

Vs= ±25V

"..
Vs

~ ~rS=±;15V
0

5

10

15

+20V

r--

I
20

25

30

POWER OUTPUT (W)

POWER OUTPUT (W)

TLIH/5030-4
*Thermal shutdown with infinite heat sink

• ·Thermal shutdown with 1°C/W heat sink

1-163

II

LM1875

en

g.
CD

3

I»

~

Rl
102

L;

lk7

R21
30

013

o~
',.....t

D

~~~

R2~

3k3

....

R3

;pk3

~04

02
R18
2k7

J

r-t:

012'l111

014

05)-

0&

-INPUT

, ~n

'"
.,JlI.

R11

Cl

~--n-

DIS!,.

~

._'-.

07~
~R4

6k8

010

,.....t

Z2~

Z3j

t4
~

R23
l20k

r-

.....

f4

!

..... 08

'-.1025

R3~4

10 VEE

&k5

1

'--

.,.t

027

~030

R7
50k

.:"
395

I~

1~

I,

R
0 12

R36
R i2
0 12
OUTPUT

200

~l--

R38
10k

038
.... 40X

~~

---,.,;

'~l-' ~ R~
~p.

R25
Ik2

~~
Bk5

R17
30k

831
100

041

R24
l&Ok

018

R13019d:

&Ok

'-.1 03

500

.....

'-1 011
R5
.k2

3

~~

R15
3U

R9

4k9

iiJ

~~

02&

Vee

RIB
Bk2

CQ

034~~
~

028 R30

'-l

C

~

.29
lkB

032..-c 826
40k

R2?L
250

",033

037r

R28
100

SIGNAL
V"

Ik
C2

~p~
I

tt-

(')

i"

036"

09"", R.

"lI

L;

~~
~~

10k

017

R12

450

~

f-

R22
30

.... 024

~021

td
~
ni

HC4~ [!;

.

..

RID
3kS

+INPUT

R20
370

OU':..

023,....1

,(

~O15

....

....

VEE

3(

029

R19
lk

Vee

039

lDO

R35
2•
'----~ VEE

Application Hints
STABILITY

CURRENT LIMIT AND SAFE OPERATING AREA (SOA)
PROTECTION

The LM1875 is designed to be stable when operated at a
closed-loop gain of 10 or greater, but, as with any other
high-current amplifier, the LM1875 can be made to oscillate
under certain conditions. These usually involve printed circuit board layout or output/input coupling.

A power amplifier's output transistors can be damaged by
excessive applied voltage, current flow, or power dissipation. The voltage applied to the amplifier is limited by the
design of the external power supply, while the maximum
current passed by the output devices is usually limited by
internal circuitry to some fixed value. Short-term power dissipation is usually not limited in monolithic audio power amplifiers, and this can be a problem when driving reactive
loads, which may draw large currents while high voltages
appear on the output transistors. The LM1875 not only limits
current to around 4A, but also reduces the value of the limit
current when an output transistor has a high voltage across
it.
When driving nonlinear reactive loads such as motors or
loudspeakers with built-in protection relays, there is a possibility that an amplifier output will be connected to a load
whose terminal voltage may attempt to swing beyond the
power supply voltages applied to the amplifier. This can
cause degradation of the output transistors or catastrophic
failure of the whole circuit. The standard protection for this
type of failure mechanism is a pair of diodes connected between the output of the amplifier and the supply rails. These
are part of the internal circuitry of the LM1875, and needn't
be added externally when standard reactive loads are driven.

Proper layout of the printed circuit board is very important.
While the LM1875 will be stable when installed in a board
similar to the ones shown in this data sheet, it is sometimes
necessary to modify the layout somewhat to suit the physical requirements of a particular application. When designing
a different layout, it is important to return the load ground,
the output compensation ground, and the low level (feedback and input) grounds to the circuit board ground pOint
through separate paths. Otherwise, large currents flowing
along a ground conductor will generate voltages on the conductor which can effectively act as signals at the input, resulting in high frequency oscillation or excessive distortion.
It is advisable to keep the output compensation components and the 0.1 /'oF supply decoupling capacitors as close
as possible to the LM1875 to reduce the effects of PCB
trace resistance and inductance. For the same reason, the
ground return paths for these components should be as
short as possible.
Occasionally, current in the output leads (which function as
antennas) can be coupled through the air to the amplifier
input, resulting in high-frequency oscillation. This normally
happens when the source impedance is high or the input
leads are long. The problem can be eliminated by placing a
small capacitor (on the order of 50 pF to 500 pF) across the
circuit input.

THERMAL PROTECTION
The LM 1875 has a sophisticated thermal protection scheme
to prevent long-term thermal stress to the device. When the
temperature on the die reaches 170'C, the LM1875 shuts
down. It starts operating again when the die temperature
drops to about 145'C, but if the temperature again begins to
rise, shutdown will occur at only 150'C. Therefore, the device is allowed to heat up to a relatively high temperature if
the fault condition is temporary, but a sustained fault will
limit the maximum die temperature to a lower value. This
greatly reduces the stresses imposed on the IC by thermal
cycling, which in turn improves its reliability under sustained
fault conditions.
Since the die temperature is directly dependent upon the
heat sink, the heat sink should be chosen for thermal resistance low enough that thermal shutdown will not be reached
during normal operation. Using the best heat sink possible
within the cost and space constraints of the system will improve the long-term reliability of any power semiconductor
device.

Most power amplifiers do not drive highly capacitive loads
well, and the LM1875 is no exception. If the output of the
LM1875 is connected directly to a capacitor with no series
resistance, the square wave response will exhibit ringing if
the capacitance is greater than about 0.1 /'oF. The amplifier
can typically drive load capacitances up to 2 /'oF or so without oscillating, but this is not recommended. If highly capacitive loads are expected, a resistor (at least 10.) should be
placed in series with the output of the LM1875. A method
commonly employed to protect amplifiers from low impedances at high frequencies is to couple to the load through a
100. resistor in parallel with a 5 /'oH inductor.
DISTORTION
The preceding suggestions regarding circuit board grounding techniques will also help to prevent excessive distortion
levels in audio applications. For low THD, it is also necessary to keep the power supply traces and wires separated
from the traces and wires connected to the inputs of the
LM1875. This prevents the power supply currents, which
are large and nonlinear, from inductively coupling to the
LM1875 inputs. Power supply wires should be twisted together and separated from the circuit board. Where these
wires are soldered to the board, they should be perpendicular to the plane of the board at least to a distance of a
couple of inches. With a proper physical layout, THD levels
at 20 kHz with 10W output to an 80. load should be less
than 0.05%, and less than 0.02% at 1 kHz.

POWER DISSIPATION AND HEAT SINKING
The LM1875 must always be operated with a heat sink,
even when it is not required to drive a load. The maximum
idling current of the device is 100 mA, so that on a 60V
power supply an unloaded LM1875 must dissipate 6Wof
power. The 54'C/W junction-to-ambient thermal resistance
of a TO-220 package would cause the die temperature to
rise 324'C above ambient, so the thermal protection circuitry will shut the amplifier down if operation without a heat
sink is attempted.

1-165

II

U) r-------------------------------------------------------------------------------~

CD
"""
.....

:iii
...I

Application Hints (Continued)
In order to determine the appropriate heat sink for a given
application, the power dissipation of the LM1875 in that application must be known. When the load is resistive, the
maximum average power that the IC will be required to dissipate is approximately:
VS2
PO(MAX)::::: 2'IT2RL + Po

If a mica insulator is used, the thermal resistance will be
about 1.6"C/W lubricated and 3.4·C/W dry. For this example, we assume a lubricated mica insulator between the
LM1875 and the heat sink. The heat sink thermal resistance
must then be less than

4.2'C/W - 2'C/W -1.6'C/W = 0.6'C/W.
This is a rather large heat sink and may not be practical in
some applications. If a smaller heat sink is required for reasons of size or cost, there are two alternatives. The maximum ambient operating temperature can be reduced to
50'C (122'F), resulting in a 1.6'C/W heat sink, or the heat
sink can be isolated from the chassis so the mica washer is
not needed. This will change the required heat sink to a
1.2'C/W unit if the case-to-heat-sink interface is lubricated.

where Vs is the total power supply voltage across the
LM1875, RL is the load resistance, and Po is the quiescent
power dissipation of the amplifier. The above equation is
only an approximation which assumes an "ideal" class B
output stage and constant power dissipation in all other
parts of the circuil. The curves of "Power Dissipation vs
Power Output" give a better representation of the behavior
of the LM1875 with various power supply voltages and resistive loads. As an example, if the LM1875 is operated on a
50V power supply with a resistive load of 80., it can develop
up to 19W of internal power dissipation. If the die temperature is to remain below 150'C for ambient temperatures up
to 70'C, the total junction-to-ambient thermal resistance
must be less than
150'C-70'C
19W

Note: When using a single supply. maximum transfer of heat away from the
LM1875 can be achieved by mounting the device directly to the heat
sink (tab is at ground potential); this avoids the use of a mica or other
type insulator.

The thermal requirements can become more difficult when
an amplifier is driving a reactive load. For a given magnitude
of load impedance, a higher degree of reactance will cause
a higher level of power dissipation within the amplifier. As a
general rule, the power dissipation of an amplifier driving a
60' reactive load (usually considered to be a worst-case
loudspeaker load) will be roughly that of the same amplifier
driving the resistive part of that load. For example, a loudspeaker may at some frequency have an impedance with a
magnitude of 80. and a phase angle of 60'. The real part of
this load will then be 40., and the amplifier power dissipation
will roughly follow the curve of power dissipation with a 40.
load.

4.2'C/W.

Using OJc=2'C/W, the sum of the case-to-heat-sink interface thermal resistance and the heat-sink-to-ambient thermal resistance must be less than 2.2'C/W. The case-toheat-sink thermal resistance of the TO-220 package varies
with the mounting method used. A metal-to-metal interface
will be about 1'C/W if lubricated, and about 1.2'C/W if dry.

Component Layouts
Split Supply

Single Supply

TL/H/5030-6
TUH/5030-7

1-166

r
3:
......

NatiOnal

~ Semiconductor

co
........

Corporation

LM 1877 Dual Power Audio Amplifier
•
•
•
•
•

General Description
The LM1877 is a monolithic dual power amplifier designed
to deliver 2W/channel continuous into 8n loads. The
LM1877 is designed to operate with a low number of external components, and still provide flexibility for use in stereo
phonographs, tape recorders and AM-FM stereo receivers,
etc. Each power amplifier is biased from a common internal
regulator to provide high power supply rejection, and output
Q point centering. The LM1877 is internally compensated
for all gains greater than 10.

Wide supply range, 6V-24V
Very low cross-over distortion
Low audio band noise
AC short circuit protected
Internal thermal shutdown

Applications
•
•
•
•
•
•
•

Features
• 2W/channel
• - 65 dB ripple rejection, output referred
• -65 dB channel separation, output referred

Multi-channel audio systems
Stereo phonographs
Tape recorders and players
AM-FM radio receivers
Servo amplifiers
Intercom systems
Automotive products

Connection Diagram
Dual-in-Line Package

BIAS
OUTPUT 1

GND
GND

Order Number LM1877N-9
See NS Package Number N14A

GND
INPUT 1

FEEDBACK 1

TL/H/7913-1

Top View

Equivalent Schematic Diagram

D
Ok

'"
5k

7
-FEEDBACK 1

I

6

,

+INPUT2

"INPUT 1

B
-FEEDBACK 2

TLlH17913-2

1-167

.....
.....
co
..-

:E
..J

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

Operating Temperature

26V

Input Voltage

O'Cto +70'C

Storage Temperature

-65'C to + 150'C

Junction Temperature

150'C

Lead Temperature (Soldering, 10 sec.)

260'C

±0.7V

Electrical Characteristics
Vs = 20V, TA = 25'C, (See Note 1) RL = Bn, Av = 50 (34 dB) unless otherwise specified
Parameter

Conditions

Total Supply Current

Po= OW

Output Power
LM1B77

THD = 10%
Vs = 20V, RL = Bn

Total Harmonic Distortion
LM1B77

f = 1 kHz, Vs = 14V

Min

Typ

Max

Units

25

50

mA

2.0

W/Ch

Po = 50 mW/Channel

0.075

%

Po = 500 mW/Channel

0.045

%

Po = 1 W IChannel

0.055

%

Output Swing

RL = Bn

Vs -6

Vp·p

Channel Separation

CF = 50 ,..,F, CIN = 0.1 ,..,F,
f = 1 kHz, Output Referred
-70

dB

-60

dB

-65

dB

-40

dB

Rs = 0, CIN = 0.1 ,..,F,
BW = 20 Hz-20 kHz, Output Noise Wideband

2.5

fLY

Rs = 0, CN = 0.1 ,..,F, Av 200

O.BO

mV

-50

Vs = 20V, Vo = 4 Vrms
Vs = 7V, Vo = 0.5 Vrms
PSRR Power Supply
Rejection Ratio

CF = 50 ,..,F, CIN = 0.1 ,..,F,
f = 120 Hz, Output Referred
Vs = 20V, VRIPPLE = 1 Vrms

-50

Vs = 7V, VRIPPLE = 0.5 Vrms
Noise

Open Loop Gain

Equivalent Input Noise

Rs = 0, f = 100 kHz, RL = Bn

Input Offset Voltage
Input Bias Current
Input Impedance

Open Loop

DC Output Level

Vs = 20V

9

Slew Rate

70

dB

15

mV

50

nA

4

Mn

10

11

V

2.0

V/fLS

Power Bandwidth

65

kHz

Current Limit

1.0

A

Note 1: For operation at ambient temperature greater than 2S'C, the LM1877 must be derated based on a maximum 1SO"C iunction temperature using a thenmal
resistance which depends upon device mounting techniques.

1-16B

Typical Performance Characteristics

~

i=
"'
_

c;;

'"

It.)

~
Q

Power Supply Rejection Ratio
(Referred to the Output) vs
Frequency

12.0

Device Dissipation vs
Ambient Temperature

to.o

INH!m H(~l SI,J nocl-j-f-+--1
~F'p>+........,~~l-+-+--l

B.O

6.0
4.0

1-+-+--I-+-.......
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st". . EAVICO"[RK(AJ$lNK]a;;;:.~1....-..

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ltclW I.....-

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~; ~ ~'~"~'i"~' '~"i'"~' ~' ~' '~'i' ~"'~
~

IllCfIII'

_I

z.o

i'ciVI

IIIH1.I.,11

to

20

30

40

50

60

70

-z
c

50

!

40

>
~

e
iJ
a:
>

>

30

~

~

to

~

ffi

w

iffi

80

'"cz

;::
~

~

VRIPPLf .. 0.5 Vrms

VRIPPlE'" 1 Vnns

~

f= 120Hz
AV· 50

o
6

to

_

~

-

..... ~

_~~;li~11 11111

50

~

I ~i,r O.O~,~,~F 11111
10

tOO

tk

0.5

70

AV· 50

r- e,N· 0.1 pF

60

..liiwiL~

c:~ :1~:~04j ~F

50

JllllI11
to

tOO

tk

to.

Total Harmonic Distortion

Total Harmonic Distortion

t;
E
u

u

~

~

ill

O.t

,.'"
~'"

O.t

~

to.

t.5
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/'

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tav

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IL 4J" TIHO r-

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I

T
I

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I
I

o

z

~

~
>

an

V

L

V

V

60

/

I'

40

V

I'

20

I
o

0
tOO

POWER OUTPUT IW/CHANNELl

Output Swing vs Supply
Voltage

BO

w

'"'"

t6

VS=20V

RL::;

;

too.

FREQUENCV 1Hz)

Open Loop Gain vs
Frequency

I

eo

lOOk

i!i;::
:;

Power Dissipation (W)

o

VCe"7V

Vo ,. 500 mVrms

~

a Both Channels Operating

/.

Channel Separation (Referred
to the Output) vs Frequency

FREQUENCY 1Hz)

POWER OUTPUT IW/CHANNEL)

Rl ""

to.

FREQUENCY (Hz)

~

o

lk

CBY~ASS· 'O'~F

too.

E

,.'"
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/

o

100

40
to'

1;;

ill

V

200

l'iiTIiIiI I

J 11111111

'pF

~

z
z

~

w

'"~
>
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~

Vee = 20V
VDUT= 4 Vrms

c

i;l

VcBYPASS" 1 .uF

to

~

g

1--"' .....

I
10~

;::

z

400

~

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60

t6

«
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>

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20

'0

=

1m

~

z
z

BOO

~

II

70

Average Supply Current vs
POUT

600

30

FREQUENCY 1Hz)

e,N'" D.1pF

SUPPLY VOLTAGE IV)

...
:s

/

V

10

Channel Separation (Referred
to the Output vs Freguen cy

40
t4

t2

tIN .. 0.0047.uF
AV-50

100.uF

10k

tk

VRIPPLE'" 1 Vrms

40

o
tOO

11111111

V~IP~LE ~ O.3:Vrm:s

20

II
II

FREOUENCY 1Hz!

..,.

"BYPASS· 5 p
CIN"O.tpF

50

!

BO

~Vv~RIPPLE' t V'm.
40

c

20

NOISE~

T

60

60

~
a:

Power Supply Rejection Ratio
(Referred to the Output) vs
Supply Voltage

.,

'"~

~
z

TA - AMBIENTTEMPERATURE rc)

.0

70

70
60

Power Supply Rejection Ratio
(Referred to the Output) vs
Frequency

l'

10.

tOO'

FREQUENCY 1Hz)

tM

o

to

t5

20

25

SUPPLY VOLTAGE IV)

TL/H17913-3

1-169

Typical Applications
Stereo Phonograph Amplifier with Bass Tone Control

+
10hF

lk

T

51k
510k
lOOk

Vs
O.03hF
10k

+1
+l
500pF

4: r+r
-=

STEREO
CERAMIC
CARTRIDGE

I
I
I
I
I
I
I

2.m

'::'

TO.

1L~p

1PF

Bn

-=

500pF

0.1 pF

2.m

T

510k
lOOk

Bn

0.1 pF

-=

-=

51k

+
10hF
T

TL/H/7913-4

Frequency Response of Bass Tone Control
;;;

65

;:!

....
o
a:

.
.....

Ii;

Inverting Unity Gain Amplifier

;;;;;:;;
55 r--

~

Vs

MAXIMUM
BOOST
~ESPDNSE

lOOk

o

45

TONE.J:'-CONTROL FLAT

z

35

1/

...co
~
o

25

~

o
o

;;:

>

o.lpf

---.J t-JW\I-+--~
lOOk

..,..

~ ::;; AAXIMUM
~

1

15
20

10k

CUT
RESPONSE

1

50 100 200 500 lk 2k

5k 10k 20k

FREOUENCY (Hz)
TLlH17913-5
TLlH/7913-6

1-170

r-------------------------------------------------------------------------, r
Typical Applications

:s:::
.....
co
......
......

(Continued)
Stereo Amplifier with AV = 200

+1
5QOjJF

2.1u

RL
Bu

rO,' F":"
JJ

I3,4.5, --

~

I
I

.J;ABGND

lOOk

TLlH17913-7

Non-Inverting Amplifier Using Split Supply
2k

Typical Split Supply

lOOk

v+jj l-J0.1/JF ":"

r-I

1

14

--,

I

II
TLlH17913-9

2k

lOOk

TLlH17913-8

1-171

NatiOnal

~ Semiconductor
Corporation

DYNAMIC NOISE REDUCnON SYSTEM

LM1894 Dynamic Noise Reduction System DNR®
General Description
The LM 1894 is a stereo noise reduction circuit for use with
audio playback systems. The DNR system is non-complementary, meaning it does not require encoded source material. The system is compatible with virtually all prerecorded
tapes and FM broadcasts. Psychoacoustic masking, and an
adaptive bandwidth scheme allow the DNR to achieve 10
dB of noise reduction. DNR can save circuit board space
and cost because of the few additional components required.

Features

• Compatible with all prerecorded tapes and FM
• 10 dB effective tape noise reduction CCIRtARM
weighted
• Wide supply range, 4.5V to 18V
• 1 Vrms input overload

Applications
•
•
•
•
•

Automotive radioltape players
Compact portable tape players
Quality HI-FI tape systems
VCR playback noise reduction
Video disc playback noise reduction

• Non-complementary noise reduction, "single ended"
• Low cost external components, no critical matching

Typical Application
C9
O.D47IlF

+

LEFT
INPUT
FROM TAPE
PREAMP DR FM

13

12

LEFT
OUTPUT
TO VOLUME
CONTROL AND
POWER AMPLIFIERS

LMIB94
RIGHT
INPUT

RIGHT
OUTPUT

*R?'~"' ::.:
"R2

C4

IpF

+
'RI + R2 = 1 kG total.
See Application Hints.

TL/H/7916-1

FIGURE 1. Component Hook-Up for Stereo DNR System
Order Number LM1894M or LM1894N
See NS Package Number M14A or N14A

1-172

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications_
Supply Voltage

260'C

Smail Outline Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

20V

Input Voltage Range, Vpk
Operating Temperature (Note 1)
Storage Temperature

Soldering Information
Dual-In-Line Package
Soldering (10 seconds)

Vs/2
O'Cto +70'C

215'C
220'C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" (Appendix D) for other methods of
soldering surface mount devices.

-65'Cto +150'C

Electrical Characteristics
Vs = 8V, T A = 25'C, Y,N = 300 mVat 1 kHz, circuit shown in Figure 1 unless otherwise specified
Parameter

Conditions

Operating Supply Range
Supply Current

Min

Typ

Max

4.5

8

18

V

17

30

mA

-0.9

-1

-1.1

VIV

3.7

4.0

4.3

V

1.0

dB

1400

Hz

Vs = 8V

Units

MAIN SIGNAL PATH
Voltage Gain

DC Ground Pin 9, Note 2

DC Output Voltage
Channel Balance

DC Ground Pin 9

-1.0

Minimum Balance

AC Ground Pin 9 with 0.1 I-'F
Capacitor, Note 2

675
27

965

Maximum Bandwidth

DC Ground Pin 9, Note 2

34

46

kHz

Effective Noise Reduction

CCIRI ARM Weighted, Note 3

-10

-14

dB

Total Harmonic Distortion

DC Ground Pin 9

0.05

0.1

%

Input Headroom

Maximum Y,N lor 3% THD
AC Ground Pin 9

1.0

Vrms

Output Headroom

Maximum VOUT for 3% THD
DC Ground Pin 9

Vs - 1.5

Vp-p

Signal to Noise

BW = 20 Hz-20 kHz, re 300 mV
AC Ground Pin 9
DC Ground Pin 9
CCIRI ARM Weighted re 300 mV
Note 4
AC Ground Pin 9
DC Ground Pin 9
CCIR Peak, re 300 mY, Note 5
AC Ground Pin 9
DC Ground Pin 9

79

77

dB
dB

88
76

dB
dB

77

dB
dB

82
70

64

Input Impedance

Pin 2 and Pin 13

14

20

Channel Separation

DC Ground Pin 9

-50

-70

dB

Power Supply Rejection

C14 = 100 I-'F,
VRIPPLE = 500 mVrms,
1= 1 kHz

-40

-56

dB

Output DC Shift

Reference DVM to Pin 14 and
Measuree Output DC Shift from
Minimum to Maximum Bandwidth, Note 6.

1-173

4.0

26

20

kO

mV

II

'Of'

G)

CD
.-

::E
...J

Electrical Characteristics
Vs = BV, TA = 25'C, VIN = 300 mV at1 kHz, circuit shown in Rgure 1 unless otherwise specified (Continued)

I

Parameter

I

Conditions

I

Min

Typ

I

I

Max

Units

CONTROL SIGNAL PATH
Summing Amplifier Voltage Gain

Both Channels Driven

0.9

1

1.1

VIV

Gain Amplifier Input Impedance
Voltage Gain

Pin6
Pin6toPinB

24
21.5

30
24

39
26.5

k!l
VIV

Peak Detector Input Impedance

Pin 9

560

700

B40

!l

Voltage Gain

Pin 9to Pin 10

30

33

36

VIV

Attack Time

Measured to 90% of Final Value
with 10kHz Tone Burst
Measured to 90% of Final Value
with 10kHz Tone Burst
Minimum Bandwidth to Maximum
Bandwidth

300

500

700

/Ls

45

60

75

ms

3.B

V

Decay Time
DC Voltage Range

1.1

Note 1: For operation in ambient temperature above 25°C, the device must be derated based on a 1500C maximum junction temperature and a thermal resistance
of 1) 800C/W junction to ambient for the dual-in-line package, and 2) 1Ofl'C/W junction to ambient for the small outline package.

Note 2: To force the DNR system into maximum bandwidth, DC ground the input to the peak detector, pin 9. A negative temperature coeificient of -0.5%I"C on
the bandwidth, reduces the maximum bandwidth at increased ambient temperature or higher package dissipation. AC ground pin 9 or pin 6 to select minimum
bandwidth. To change minimum and maximum bandwidth, see Appliction Hints.
Note 3: The maximum noise reduction CCIRtARM weighted is about t4 dB. This is accomplished by changing the bandwidth from maximum to minimum. In actual
operation, minimum bandwidth is not selected, a nominal minimum bandwidth of about 2 kHz gives -10 dB of noise reduction. See Application Hints.
Note 4: The CCIRtARM weighted noise is measured wHh a 40 dB gain amplifier between the DNR system and the CCIR weighting filter; it is then input referred.
Note 5: Measured using the Rhode-Schwartz psophometer.
Note 6: Pin 10 is DC forced halfway between the maximum bandwidth DC level and minimum bandwidth DC level. AnAC 1 kHz signal is then applied to pin 10. Its
peak·to·peak amplitude is Voc (max BW) - Voe (min 8W).

Typical Performance Characteristics
Channel Separation
(Referred to the Output)
vs Frequency

Supply Current vs
Supply Voltage

25 r-~~-r~~--~~,

V .......

c 20r4~-+~/~~~~

1 V/
oS

Vi-""

~

10
5 r-r-i-i-+-+-+-+~
O~~~~~~~~~

4

~,,~

i

15

::;

90
80

8

12

16

20

I-r:::S:aHf~~I;j:::umm
FULL ~~III

70 j-:FrM#~I"ii!m~~M~8~Wi"f'ff

~

40

Hl+ftItIl!I-+lttj-tffi--I--H1H+!!t

30

l-t-+tffiJtt-+H+ttfII---+-t+ttHtI

10

C14= 100pF-t-t+ttt!lH--Httt1-1tt
VIN -1 Vnns

OL-L..J...u..uJII.....J....u.J.WJL.....1...I.J.WJII

10

SUPPLY VOLTAGE 'V)

100

lk

NOMINAL BW

m

~

~~

••
'"

~

JlJJ~II~_\\-b,IoMIf-~-++HHllI
40 J.l0JJ

~~~'-H+HIII-HtttHH

20

--l-+t-Htfll--H+tflfll

25pF

cliw,r",t-+ltt+l!l~tt!--Il~:I!II

0

10k

10

FREQUENCY 'Hz)

100

10k

I>

FREQUENCY 'Hz)

- 3 dB Bandwidth
vs Frequency and
Control Signal

THO vs Frequency

t+t-ltHl--++Hf+tt!I

60 Rs·on

~

60~~Hffi~~Hmr4~

u::
z

~

Power Supply Rejection
Ratio (Referred to the
Output) vs Frequency
80r.V~R-IP-PL-E~'-I-Vm--,n7~~~mm

Gain of Control Path
vs Frequency (with
10 kHz FM Pilot Filter)
:~~mr-nl~~~_;c~~

is

"j!:

0.08

r-+++-+-+-+-t-H

0.06

t--t-++--+--+--+-t-H

~
!f
"e:
z
1::
~

0.02

"z
~

r-+++-+-+-+-t-H

0'--~J....J_J....J......L--l......L....I

28

50 100 200 500 lk 2k
FREQUENCY 'Hz)

5k 10k 201c

40

19kHz

10r,HHjffill-t+H*m-+-+~~

t-f-IIl+tttfl-+lf+

-

-10 t-Ift-I+tttfl-+lf+

10k

0

-20
20

50 100200 500 1k 2k
FREQUENCY 1Hz)

5k 10k 20k

t-t-++tttHt--1'l~WJ~
/

30 I--t+Htll¥--t PILOT
20 1--t+IfflIll--t-IFiiILijTIiiERji-JH1*HH

L-L..J..I.WIIL.....L..Ju,

100

lk

ll111k

FREQUENCY 'Hz)

TLlH17918-2

1-174

r-

Typical Performance Characteristics

s::
.....

(Continued)

(XI

CD

"'"

Main Signal Path
Bandwidth vs
Voltage Control
20

Peak Detector Response

INPUT

v
o
100

lk

10k

lOOk

BANDWIDTH IHrJ

P~K~-+--+--+--4-~~~~~-+--~~

TL/H17918-3

DETECTOR
OUTPUT

~-+--+--+--4-~~-+----~-+--~~

TIME: 20 ms/DIV

TLlH17918-4

Output Response

INPUT

1--1----1-

DNR
OUTPUT

1-+---1-

TIME: 20 ms/D1V

TLlHI7918-S

External Component Guide (Rgure 1)
Component
C1

C2,C13

C14

C3,C12

Value
0.1 f£F100 f£F

1 f£F

25 f£F100 f£F
0.0033 f£F

Purpose
May be part of power
supply, or may be added to suppress power
supply oscillation.
Blocks DC, pin 2 and
pin 13 are at DC potential of Vs/2. C2,
C13 form a low frequency pole with 20k
RIN·
1
fL =
27T C2 RIN
Improves power supply rejection.
Forms integrator with
internal gm block and
op amp. Sets bandwidth conversion gain
of 33 Hz/ f£A of gm
current.

1-175

Component Value
C4,C11
1 f£F

Purpose
Output coupling capacitor. Output
is at DC potential of Vs/2.

C5

Works with R1 and R2 to attenuate low frequency transients
which could disturb control path
operation.
1
fs = 27TC5(R1 + R2) = 1.6kHz

0.1 f£F

C6

0.001 f£F

C8

0.1 f£F

Works with input resistance of pin
6 to form part of control path frequency weighting.
1
= 5.3 kHz
f6 =
27T C6 R1PIN 6
Combined with L8 and CL forms
19 kHz filter for FM pilot. This is
only required in FM applications
(Note 1).

II

'Oil'

0)

co
....

:E
...I

peak detector input determine the frequency weighting as
shown in the typical performance curves. The 1 p.F capacitor at pin 10, in conjunction with internal resistors, sets the
attack and decay times. The voltage is converted into a
proportional current which is fed into the gm blocks. The
bandwidth sensitivity to gm current is 33 Hz/p.A. In FM
stereo applications at 19 kHz pilot filter is inserted between
pin B and pin 9 as shown in Figure 1.

External Component Guide (Figure 1)
(Continued)
Component
LB,CL

Value
4.7mH,
0.015 p.F

Purpose
Forms 19 kHz filter for FM pilot. LB is Taka coil CAN1A1B5HM· (Note 1).

C9

0.047 p.F

Works with input resistance
of pin 9 to form part of control
path frequency weighting.
1
fg = 2 C9 R
= 4.B kHz
7r
PINg
Set attack and decay time of
peak detector.

C10

1 p.F

R1,R2

1 kn

RB

Figure 3 is an interesting curve and deserves some discussion. Although the output of the DNR system is a linear
function of input signal, the -3 dB bandwidth is not. This is
due to the non-linear nature of the control path. The DNR
system has a uniform frequency response, but looking at
the -3 dB bandwidth on a steady state basis with a single
frequency input can be misleading. It must be remembered
that a single input frequency can only give a single - 3 dB
bandwidth and the roll-off from this point must be a smooth
-6 dB/oct.

Sensitivity resistors set the
noise threshold. Reducing attentuation causes larger signals to be peak detected and
larger bandwidth in main signal path. Total value of R1 +
R2 should equal 1 kn.
Forms RC roll-off with CB.
This is only required in FM
applications.

100n

A more accurate evaluation of the frequency response can
be seen in Figure 4. In this case the main signal path is
frequency swept, while the control path has a constant frequency applied. It can be seen that different control path
frequencies each give a distinctive gain roll-off.
Psychoacoustic Basics
The dynamic noise reduction system is a low pass filter that
has a variable bandwidth of 1 kHz to 30 kHz, dependent on
music spectrum. The DNR system operates on three principles of psychoacoustics.

• Taka America Inc .• 1250 Feehanville Drive, Mt. Prospect IL 60056
Note 1: When FM applications are not required, pin 8 and pin 9 hook-up as

follows:

CD
.047PF

__

~
D

1. White noise can mask pure tones. The total noise energy
required to mask a pure tone must equal the energy of the
tone itself. Within certain limits, the wider the band of masking noise about the tone, the lower the noise amplitude
need be. As long as the total energy of the noise is equal to
or greater than the energy of the tone, the tone will be inaudible. This principle may be turned around; when music is
present, it is capable of masking noise in the same bandwidth.
2. The ear cannot detect distortion for less than 1 ms. On a
transient basis, if distortion occurs in less than 1 ms, the ear
acts as an integrator and is unable to detect it. Because of
this, signals of sufficient energy to mask noise open bandwidth to 90% of the maximum value in less than 1 ms. Reducing the bandwidth to within 10% of its minimum value is
done in about 60 ms: long enough to allow the ambience of
the music to pass through, but not so long as to allow the
noise floor to become audible.

8

LM1894

I

TL/H17918-6

Circuit Operation
The LM1B94 has two signal paths, a main Signal path and a
bandwidth control path. The main path is an audio low pass
filter comprised of a gm block with a variable current, and an
op amp configured as an integrator. As seen in Figure 2, DC
feedback constrains the low frequency gain to Av = -1.
Above the cutoff frequency of the filter, the output decreases at -6 dB/oct due to the action of the 0.0033 p.F capacitor.
The purpose of the control paths is to generate a bandwidth
control Signal which replicates the ear's sensitivity to noise
in the presence of a tone. A single control path is used for
both channels to keep the stereo image from wandering.
This is done by adding the right and left channels together
in the summing amplifier of Figure 2. The R1, R2 resistor
divider adjusts the incoming noise level to open slightly the
bandwidth of the low pass filter. Control path gain is about
60 dB and is set by the gain amplifier and peak detector
gain. This large gain is needed to ensure the low pass filter
bandwidth can be opened by very low noise floors. The capacitors between the summing amplifier output and the

3. Reducing the audio bandwidth reduces the audibility of
noise. Audibility of noise is dependent on noise spectrum, or
how the noise energy is distributed with frequency. Depending on the tape and the recorder equalization, tape noise
spectrum may be slightly rolled off with frequency on a per
octave basis. The ear sensitivity on the other hand greatly
increases between 2 kHz and 10kHz. Noise in this region is
extremely audible. The DNR system low pass filters this
noise. Low frequency music will not appreciably open the
DNR bandwidth, thus 2 kHz to 20 kHz noise is not heard.

1-176

r-

...s:

Block Diagram

01)

CHZ 10

CHZ OUTPUT

IZ

CHI OUTPUT

CD
01:>0

V+

----.t-l

11

Zo.
CHZ
INPUT

CHilO

I

t-______-;r-~2~0.~_,

I-...."""'Z"ok,..,.......____-+.:....o ~:pIUT

13

I
I

.....--f----..-----------------.....--+_--'

BYPASS o-~+------<

I
I
I

I

I

21k

30k

I.ZV . . .""',.,....,

I

I

I
I

I

I
I

90

100

I

L ____ _
~AMP

OUTPUT

_J

GAIN AMP
INPUT

GAIN AMP
OUTPUT

PEAK
DETECTOR
INPUT

PEAK
DETECTOR
OUTPUT

GNU

TL/H/7916-7

FIGURE 2
20
10
0

IJ I
VIN'" 30DmV

lOOmV

-10
~

'",.l;co

30mV

-20

lDmV

-30

3mV

-<10

I
I

-50
-60

:~.;-::~~~ ~kH' FILTER- 1-1--

-10
-80
20

50 100200 500 Ik 2k

20

5k 10k 20k

50 100200 500 Ik 2k

5k 10k 20k

FREQUENCY (H.I

FREnUENCY (Hz I

TL/H17916-6

TL/H17916-9

FIGURE 4. -3 dB Bandwidth vs
Frequency and Control Signal

FIGURE 3. Output vs Frequency

Application Hints
tor. For greater flexibility in setting the bandwidth sensitivity,
R1 and R2 could be replaced by a 1 kn potentiometer.
To change the minimum and maximum value of bandwidth,
the integrating capacitors, C3 and C12, can be scaled up or
down. Since the bandwidth is inversely proportional to the
capacitance, changing this 0.0039 ,...F capacitor to
0.0033 ,...F will change the typical bandwidth from 965 Hz34 kHz to 1.1 kHz-40 kHz. With C3 and C12 set at 0.0033
,...F, the maximum bandwidth is typically 34 kHz. A double
pole double throw switch can be used to completely bypass
DNA.

The DNR system should always be placed before tone and
volume controls as shown in Figure 1. This is because any
adjustment of these controls would alter the noise floor
seen by the DNR control path. The sensitivity resistors R1
and R2 may need to be switched with the input selector,
depending on the noise floors of different sources, i.e., tape,
FM, phono. To determine the value of R1 and R2 in a tape
system for instance; apply tape noise (no program material)
and adjust the ratio of R1 and R2 to open slightly the bandwidth of the main signal path. This can easily be done by
viewing the capacitor voltage of pin 10 with an oscilloscope,
or by using the Circuit of Figure 5. This circuit gives an LED
display of the voltage on the peak detector capacitor. Adjust
the values of R1 and R2 (their sum is always 1 kn) to light
the LEOs of pin 1 and pin 1B. The LED bar graph does not
indicate signal level, but rather instantaneous bandwidth of
the two filters; it should not be used as a signal-level indica-

The capacitor on pin 10 in conjunction with internal resistors
sets the attack and decay times. The attack time can be
altered by changing the size of C10. Decay times can be
decreased by paralleling a resistor with C10, and increased
by increasing the value of C10.

1-177

II

~

G)

....

co

::E
...I

r---------------------------------------------------------------------------------,
Application Hints (Continued)
When measuring the amount of noise reduction of the DNR
system, the frequency response of the cassette should be
flat to 10 kHz. The CCIR weighting network has substantial
gain to 8 kHz and any additional roll-off in the cassette player will reduce the benefits of DNR noise reduction. A typical

signal-to-noise measurement circuit is shown in Figure 6.
The DNR system should be switched from maximum bandwidth to nominal bandwidth with tape noise as a signal
source. The reduction in measured noise is the signal-tonoise ratio improvement.

..--~~--~~--~----~----..--~t_--~~--_e--+V=8V

r--.~~---O.I Il F

T
18

16

15

14

13

10

11

LM3915

lk

430
910

TUH/7918-10

FIGURE 5. Bar Graph Display of Peak Detector Voltage

TONE AND
VOLUME

CASSETTE

CCIR
WEIGHTING
FILTER

AVERAGE
RESPONDING
METER
TL/H17918-11

FIGURE 6. Technique for Measuring SIN Improvement of the DNR System

1-178

Application Hints (Continued)
FOR FURTHER READING

Tape Noise Levels
1. "A Wide Range Dynamic Noise Reduction System",
Blackmer, 'dB'Magazine, August-September 1972, Volume
6, #8.
2. "Dolby B-Type Noise Reduction System", Berkowitz and
Gundry, SertJourna/, May-June 1974, Volume 8.
3. "Cassette vs Elcaset vs Open Reel", Toole, Audioscene
Canada, April 1978.
4. "CCIRI ARM: A Practical Noise Measurement Method",
Dolby, Robinson, Gundry, JAES, 1978.

Noise Masking
1. "Masking and Discrimination", Bos and De Boer, JAES,
Volume 39, #4,1966.
2. "The Masking of Pure Tones and Speech by White
Noise", Hawkins and Stevens, JAES, Volume 22, # 1, 1950.
3. "Sound System Engineering", Davis Howard W. Sams
and Co.
4. "High Quality Sound Reproduction", Moir, Chapman Hall,
1960.
5. "Speech and Hearing in Communication", Fletcher, Van
Nostrand, 1953.

Printed Circuit Layout
DNR Component Diagram

TL/H/7918-12

1-179

II

U)

en

r----------------------------------------------------------------------------,

:i~

~NatiOnal
Semiconductor
it)
Corporation
~

~ LM 1895/LM2895 Audio Power Amplifier
General Description
The LM1895 is a 6V audio power amplifier designed to deliver 1W into 40. Utilizing a unique patented compensation
scheme, the LM1895 is ideal for sensitive AM radio applications. This new circuit technique exhibits lower noise, lower
distortion, and less AM radiation than conventional designs.
The amplifier's supply range (3V-9V) is ideal for battery operation. The LM1895 is packaged in an 8-pin miniDIP for
minimum PC board space. For higher supplies (Vs > 9V)
the LM2895 is available in an 11-lead single-in-line package.
The l1-lead package has been redesigned, resulting in a
slightly degraded thermal characteristic shown in the figure
Device Dissipation vs Ambient Temperature.

Features

•
•
•
•
•
•
•
•
•

Low noise
3V, 40, Po = 250 mW
Wide supply operation 3V-15V (LM2895)
Low distortion
No turn on "pop"
Smooth waveform clipping
8-pin miniDIP (LM1895)
12V, 40, Po = 4W (LM2895)
Tested for low crossover distortion

Applications
• Compact AM-FM radios
• Battery operated tape player amplifiers
• Line driver

• Guaranteed low crossover distortion
• Low AM radiation

Typical Applications
Cs

~--~

; · '...

....- -...-ovs= 6V

>~---4"""OVOUT

TLlH17919-1

FIGURE 1. LM1895 with Av = 500, BW = 5 kHz, AM Radio
Application (VIN = 4.2 mV for Full Power Output)
Order Number LM1895N or LM2895P
See NS Package Number N08E or P11A

1-180

r-

...

Ei:

Absolute Maximum Ratings
If Military! Aerospace specified devices are required,
contact the National Semiconductor Sales Office!
Distributors for availability and specifications.
Supply Voltage
LM1895
Vs = 12V
LM2895
Vs = 18V

Operating Temperature (Note 1)
Storage Temperature

O'Cto +70'C
-65'C to + 150'C

Junction Temperature
Lead Temperature (Soldering, 10 sec.)

150'C
260'C

00
<0

U1
.....
r-

Ei:

I\)

00
<0

U1

Electrical Characteristics
Unless otherwise specified, TA = 25'C, Av = 200 (46 dB). For the LM1895, Vs = 6V and RL = 4n. For the LM2895, TTAB =
25'C, Vs = 12V and RL = 4n. Test circuit shown in Figure 2.
Parameter

LM1895

Conditions
Min

Supply Current

Typ

Max

8

14

Po = W

Operating Supply Voltage

3
THD = 10%,1 = 1 kHz
Vs = 6V, RL = 4!1 }
Vs = 9V, RL = 8n
Vs = 12V, RL = 4!1}
Vs = 12V, RL = 8n

Output Power
LM1895N
LM2895P

f =
Po
Po
Po
f =

Distortion

TA = 25'C

LM2895

10

Min

Units

Typ

Max

12

20

rnA

15

V

3

1.1
1.1

0.9

3.6

TTAB = 25'C

W
W
W
W

4.3
2.5

1 kHz

= 50mW
= O.5W
= 1.0W

0.27
0.20

20 kHz, Po = 100 mW, Vs = 3.6V

Crossover Distortion

f = 20 kHz, RL = 4!1, Po = 100 mW,
Vee = 3.6V

Power Supply Rejection
Ratio (PSRR)

CBY = 100 ,..F, f = 1 kHz, CIN = O.l,..F
Output Referred, VRIPPLE = 250 mV

Noise

Equivalent Input Noise Rs = 0,
CIN = O.l,..F, BW = 20 -20 kHz
CCIR/ARM
Wideband

0.27
0.20
0.15
3.0

3.0

%
%
%
%

3

3

%

52

40

40

1.4
1.4
2.0

52

dB

1.4
1.4
2.0

,..V
,..V
,..V

DC Output Level

2.8

3.0

3.2

5.6

6.0

6.4

V

Input Impedance

50

150

350

50

150

350

kn

Input Offset Voltage
Input Bias Current

5

5

mV

120

120

nA

Note 1: For operation at ambient temperature greater than 25°C, the LM1895/LM2895 must be derated based on a maximum junction temperature using a thermal
resistance which depends upon mounting techniques.

Typical Performance Characteristics

10

9

~
i1i

~

~

i5

rl

~

~
6

AWMINUMTHICKNESS",1/16UtCH

i-+-+-....

lXl~~:~~~/.;"
,.~;~::~:~~:~
lxlIH2SoC/,.N,\\

r-:

.1. .L .!.
~~~~IJ!HEATSIHKN

,.J~.

5 r-+-+-:~ ~~, TYPiCAlCHASSI$
4
~ R~W
3
t2
FREEAlR~·CJW
1
0

o

1.'
1.0

"-

O.B

FRtA)R- f-t25"'C/W

I'

D.'

10 20 30 40 50 60 10 BO

100
90

80
70

"-

D.'

50
50
40

3D

~

]~!

2Dr-' ~R1":2.iW

0.'

10

0

TA-AMBIENT TEMPERATURE ('CI

- 3 dB Bandwidth vs
Voltage Gain for Stable
Operation

LM1895 Maximum Device
Dissipation vs Ambient
Temperature

LM2895 Device Dissipation
vs Ambient Temperature

~

0

0

10

ZO

30

4050607080

T A - AMBIENT TEMPERATURE (OC)

0 100200300400500600

AV(VNl

TL/H17919-2

1-181

II

Typical Performance Characteristics (Continued)
AM Recovered Audio and Noise
vs Field Strength for Different
Speaker Lead Placement

THO and Gain vs Frequency
Ay = 54dB,BW = 30kHz

;a

60

i

iii __
;~
<1("

-10

-40

"

-50

'"

is
o

~

I-HftHr'!'=:±'±!,!!!.'!:=!:"'=!-

'\.

OA

~

is
0
I!:

••

o

20

50 'DO 290 SOD lk 2k

THO and Gain vs Frequency
Ay = 46dB,BW = 30kHz
60
50
40

'".
~

0.8

1.0

I

.....

is
0
I!:

.

'"

.0

!

40

liD 100 280 SOO 111 2k

30

~
'"

20

i

~

o
501002011 500,. 2k

Power Supply Rejection
Ratio (Referred to the
Output) vs Frequency

Power Output vs Supply
Voltage

Total Harmonic Distortion
Output Power

10 vs

.:;;

IL

1/
o

·100

10k

1k

.

~
0

~

iiic;

12

u

~

OA
0.2

o

LMjn

1.0

~O.HZ

ill

~

Rt"l8Ir
10

~

P"-I-<

1'1'

111111
0.01

0.1

IA:!lHO

..
0

~

I'

illc;

~-rt ~\r

!:!
~

li

1>,,+~

1.15

I

1.5

,...,.

Vs-9V

125
1.0

0.'

2.0

2.5

I I
0

3.0

/~

V~"8V

0

1.5

1/

/~

V

~ Kn·v

0.7'
0.25

1.0

r-. 3% THO

lM~S=12V

2.0

$

I' I-:

O.S

1.0

OUTPUT POWER !WI

Power Dissipation vs
Output Power, RL = 4n

~ 10%THIj
/
~
)<

, .. , kHz

0.1

12

2.25

Vs·'2V

D

~

~

Power Dissipation vs
Output Power, RL = an

Vs-9V
0.6

r-

c;

SUPPLY VOLTAGE (V)

1.0
0.8

t;
u

I II
o

FREQUENCY (Hz)

1.4

0

R"4.\l ~ II

10

LM1895
BW-30kHz
Vs"6V
AL -4n
AV -208

is

V

~
'"
~

D: 10k 20k

FREQUENCY IHd

LPG.9S

~
!;

50 100200 500 Ik 2It

20

5k 10k 20k

FREnUENCY CHz)

10

i/

..2

20

0

-

0.&

0.'

FREQUENCY (Hz)

0

>

o

02
5k 10k 20k

Po =O.5W
Rl .. 4fl

go.•

U
OA

V

VS~6J

12
1.0

o
20

ii

~

Rl"'4Sl

OJ

0

..

,..

50
40
30

..

vs!av i
I.' Po
-O.SW

Po' 0.5W

5k 10k 20k

THO and Gain vs Frequency
Ay = 34dB,BW = 50kHz

,.

!

30

vs!.v l
RL-4n

50 100200 50D ,. 2k

FREQUENCY (Hz)

THO and Gain vs Frequency
Ay = 40 dB, BW = 20 kHz
ii

30
12
1.0

20

5k ll1k 20k

FREOUENCV (Hz)

50
40

0••
OA
0.2

OA

o

10

0.1

RL-40

......

D••

FIELD STRENGTH CmVJM)

'"..

Po ·0.5W

is 0.8
0
I!: o.a

02

0.01

ii

I.' vs-ev
1.0

/

RL=4n

0.&

-60

30

I

1.0 -VS"6V
Po=0.5W
OJ

~

40

~

1.4
12

-20
-30

e:'
gee

.

50

g ..

::!

THO and Gain vs Frequency
Ay = 54dB,BW = 5kHz

60
50

1.0

I I
2.0

3.0

4.0

5.0

OUTPUT POWER fWI

OUTPUT POWER {WI

TL/H/7919-3

1-182

r
3:
.....

Equivalent Schematic

0)

co

BOOTSTRAP

C11
........

r

2(3)

3:
N

r---------------~------------i_--_t----_1~Ov+

0)

co
C11

10k

.........+-0 OUTPUT

lOOk

liZ)

10k

L------i~4~(8~)+------~---;~~~--------6·(6~)~GNO
BYPASS

-INPUT

+INPUT

TL/H17919-4

Pin 7 no connection on LM1895
Pins 4, 7, 10, 11 no connection on LM2895
( ) indicates pin number for LM2895

Typical Applications

(Continued)
Cs

~"..~------...----...._o Vs

>~---""'_OVOUT

R5
5tO

+

II

RO

tn

Rl

4n
C5

~tOI'F

Ct
50 pF

Co
TO,tI'F

-

FIGURE 2. Amplifier with Av = 200, BW = 30 kHz

1-183

TL/H17919-5

La

!

r---------------------------------------------------------------------------------,

:i......
La

m
.....

External Components (Figure2)
Components
1. Rl, R5
2.R2

Comments
Setsvoltagegain,Av = 1 + Rl/R5
Bootstrap resistor sets drive current for output stage and allows pin 2 to go
aboveVs
Works with Co to stabilize output stage
Input coupling capacitor. Pin 4 is at a DC potential of VS/2. Low frequency
pole set by:
1
fL = ---=:,-.."..,.
2'11" RINC4
Feedback capacitor. Ensure unity gain at DC. Also a low frequency pole at:
1
fL = 2'11" R5C5
Bootstrap capacitor, used to increase drive to output stage. A low frequency
pole is set by:
1
fL = 2'11" R2C2

:iii

..J

3.RO
4.C4

5.C5

6.C2

7.Cl

Compensation capacitor. This stabilizes the amplifier and adjusts the
bandwidth. See curve of bandwidth vs allowable gain
Improves power supply rejection. (See Typical Performance Curves).
Increasing C3 increases turn-on delay
Output coupling capacitor. Isolates pin 1 from the load. Low frequency pole
set by:

8.C3
9.CC

1

fL=--2'11" CCRL
Works with Ro to stabilize output stage
Provides power supply filtering

10.CO
11. Cs

Connection Diagrams
Dual-In-Line Package
OUTPUT

Single-in-Line Package

v+

•

+VS
OUTPUT

NC

BOOTSTRAP

o

BOOTSTRAP

LMIS9S
BYPASS

GND

+IN

-IN

NC
BYPASS

GNO
TL/H17919-6

LMZ895

NC

Top View

o



-60

....'"
a:

......

Av =

----"AS'

Wo =

r3:
I\)

1
R1Cl

01)

CD

A curve of -3 dB BW (wo) vs Av is shown in the Typical
Performance Curves.

U1

Figure 3 shows a plot of recovered audio as a function of
field strength in p.V1M. The receiver section in this example
is an LM3820. The power amplifier is located about two
inches from the loopstick antenna. Speaker leads run parallel to the loopstick and are 118 inch from it. Referenced to a
20 dB SIN ratio, the improvement in noise performance
over conventional designs is about 10 dB. This corresponds
to an increase in usable sensitivity of about 8.5 dB.

AUDIO AT
SPEAKER

RECOVERED
NOISE AT
SrEAKER
I111

1/

".

"

l--!1

r-...

-,iim ~/~!~:~~HL~~Ep~~~cRK

0.01

+ Wo

~~~lbIJERJD

III
IIII

•

S

U1

Rl +R5

where

The LM1895 exhibits extremely low wideband noise due in
part to an external capaCitor Cl which is used to tailor the
bandwidth. The circuit shown in Figure 2 is capable of a
signal-to-noise ratio in excess of 60 dB referred to 50 mW.
Capacitor Cl not only limits the closed loop bandwidth, it
also provides overall loop compensation. Neglecting C5 in
Figure 2, the gain is:
~.

CD

S _ S + Avwo

LEADS

TiTiTi.~~~;i~~I~~~~N:~pDR
0.1

1

GND Vs

10

FIELD STRENGTH (mV/M)

VOUT VOUT
DC
AC
TLlH17919-9

TL/H/7919-B

FIGURE 4. Printed Circuit Board Layout for LM1895

FIGURE 3. Improved AM Sensitivity
Over Conventional Design

II

1-185

U)
Q)

:i~
u;

r----------------------------------------------------------------------------,
~NatiOnal

Semiconductor
Corporation

Q)

co

~ LM 1896/LM2896 Dual Power Audio Amplifier
General Description

Features

The LM1896 is a high performance 6V stereo power amplifier designed to deliver 1 wattl channel into 40 or 2 watts
bridged monaural into 80. Utilizing a unique patented compensation scheme, the LM1896 is ideal for sensitive AM
radio applications. This new circuit technique exhibits lower
wideband noise, lower distortion, and less AM radiation than
conventional designs. The amplifier's wide supply range
(3V -9V) is ideal for battery operation. For higher supplies
(Vs > 9V) the LM2896 is available in an 11-lead single-inline package. The LM2896 package has been redesigned,
resulting in the slightly degraded thermal characteristics
shown in the figure Device Dissipation vs Ambient Temperature.

•
•
•
•
•
•
•
•
•

Low AM radiation
Low noise
3V, 40, stereo Po = 250 mW
Wide supply operation 3V-15V (LM2896)
Low distortion
No turn on "pop"
Adjustable voltage gain and bandwidth
Smooth waveform clipping
Po = 9W bridged, LM2896

Applications
• Compact AM-FM radios
• Stereo tape recorders and players
• High power portable stereos

Typical Applications
. .+,...-+--_'""""0 +Vs
Sill

150pF

*1

O.1Io1F

VOUT

Ra
100k

+Vs

Ca
0.11'1'

Zk

an
SPEAKER

\

III

SOpF

TUH/7920-1

FIGURE 1. LM2896 in Bridge Configuration (Av = 400, BW = 20 kHz)
Order Number LM1896N
Order Number LM2896P
See NS Package Number N14A
See NS Package Number P11A

1-186

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Officel
Distributors for availability and specifications.
Supply Voltage
LM1896
LM2896

Vs
Vs

=
=

Operating Temperature (Note 1)

O'Cto +70'C
- 65'C to + 150'C

Storage Temperature

12V
18V

Junction Temperature

150'C

Lead Temperature (Soldering, 10 sec.)

260'C

Electrical Characteristics
Unless otherwise specilied, TA = 25'C, Av = 200 (46 dB). For the LM1896; Vs
T TAB = 25'C, Vs = 12V and RL = 8n. Test circuit shown in Figure 2.
Parameter
Po

=

OW, Dual Mode

Operating Supply Voltage
Output Power
LM1896N-1
LM1896N-2
LM2896P-1
LM2896P-2

Distortion

6V and RL

V, ~
Vs =
Vs =
Vs =

12\1. R, ~ an Do. Modo

}

l

12V, RL = 8n Bridge Mode
9V, RL = 4n Bridge Mode
9V, RL = 4n Dual Mode

0.9
TA

=

TTAB

25'C

Max

15

25

=

10
1.1
1.8
1.3

Min

Units

Typ

Max

25

40

mA

15

V

3

2.5
9.0
7.8
2.5

W/ch
W
W/ch
W/ch
W
W
W/ch

0.09
0.11
0.14

%
%
%

2.1
2.0
7.2

25'C

1 = 1 kHz
Po = 50mW
Po = 0.5W
Po = 1W

4n. For LM2896,

LM2896

Typ

3
THD = 10%,1 = 1 kHz
Vs = 6V, RL = 4n Dual Mode
Vs = 6V, RL = 8n Bridge Mode
Vs = 9V, RL = 8n Dual Mode

=

LM1896

Conditions
Min

Supply Current

=

0.09
0.11

Power Supply Rejection
Ratio (PSRR)

CBY = 100 /LF, 1 = 1 kHz, CIN = 0.1 /LF
Output Referred, VRIPPLE = 250 mV

-40

-54

-40

-54

dB

Channel Separation

CBY = 100 /LF, f
Output Referred

-50

-64

-50

-64

dB

Noise

Equivalent Input Noise Rs = 0,
CIN = 0.1 /LF, BW = 20 - 20 kHz
CCIR/ARM
Wideband

1.4
1.4
2.0

/LV
/LV
/LV

=

1 kHz, CIN

=

0.1 /LF

1.4
1.4
2.0

DC Output Level

2.8

3

3.2

5.6

6

6.4

Input Impedance

50

100

350

50

100

350

Input Offset Voltage
Voltage Difference
between Outputs

5
LM1896N-2, LM2896P-2

10
120

Input Bias Current
Nole 1: For operation at ambient temperature greater than 25'C.
thermal resistance which depends upon mounting techniques.

5
20

10
120

V
kn
mV

20

mV
nA

the LM1696/LM2696 must be derated based on a maximum 150'C iunction temperature using a

1-187

II

~

m

co
IN
:E

r---------------------------------------------------------------------------------,
Typical Performance Curves

...I

U;

LM1B96 Maximum Device
Dissipation vs Ambient
Temperature

LM2896 Device Dissipation
vs Ambient Temperature

m

co
.....
:E

10

Z.O

I ALU...UIITHICICNESS="'&INCH

...I

.~'"'~EA1.!..-

IXl~:'~!~""
u~~;=~::~~~

'5-CIW

r-....I
n~..S1S

3:dIN.-CtW\,'

~NI

25-C/W
iI.'l..
-~ ~ ~

1

o

~ 1.6

;::

~

~
~

u

~

flEEN"l5eC/W

1.4

......

I.Z
1.0
0.6
0.4

o

10 20 3D 40 50 60 70 80

o ro H

g

40

z

LM18B6
- l - tVs' BV
'0' 0.6W - - f RL '411
DUAL MODE

30

...
:s
;;:
co

1.0

..,.

g

I-

0.8
0.6
0.4

.

If

/

"-

0.2

./
50 100 ZOO 500 Ik 2k

.

60

iii
co

40
30

..

~

,.
I-

0.6
0.4

..
:s

--,

g

50 100 200 500 Ik 2k

5k 10k

J

40

I-

1.0
O.B
0.6

I

0.4
0.2
20

50 IDI200 6DO Ik Ik

5k 10k 10k

FREQUENCY IHd

AM Recovered Audio and Noise
vs Field Strength for Different
Speaker Lead Placement

!Ii
E

C.
~F

LMI895
Vs'6V
PD' 0.6W
RL -m
DUAL MODE

-- t-- r-

1.0
0.8

~
~

-

1-1-

zC:

0.6
0.4

20

-10
-20
-30

50 100 200 500 Ik 2k

~

-50

'"

-60

~

....

o

'"

I:j

~S
......S':..
...

§'" -40

0.2

5k 10k 20k

~

0.01

FREQUENCY IHzI

0.1

ID

FIELD STRENGTH (mVIMI

Channel Separation (Referred
to the Output) VB Frequency

60 r-.....TTI"...-r-rT

--,

o

m

I I I
I I

50

5k 10k ZOk

-

LMI.96
VS'6Y
Po - D.5W
RL -411
DUAL MODE

30

i!
i!'

60

Power Supply Rejection Ratio
(Referred to the Outputl
VB Frequency

Power Output VB
Supply Voltage

10
m

60

~

50

O\!!

40

co f-t-+HftHhl'HIR-

;::

30 f-I-+~FH-I-I+

::I:j

ZO

.
~

1---I-++Ill'lll--+-1+
100

I-r---:

60
60

THD and Gain vs Frequency
Av - 34 dB, BW - 50 kHz

FREQUENCY 1Hz)

10

..g

i

I\...

3D

-

....
50 100 100 500 Ik Zk

THD and Gain VB Frequency
Av - 46dB,BW - 50kHz

..

20

..,.

20

Ay (v/VI

- f-~

o

g

o

100 ZOO 300 400 500 600

~

FREQUENCY IHzI

LMI896
VS'6V
Po - 0.5W
RL 'Cll
DUAL MODE

0.2

n

1.0
O.B

i!'

5k 10k ZOk

IJ

1.0
O.B
0.6
0.4

~

LMI896
YS'8V
PO·O.6W RL '411
DUAL MODE

40
30

0.1

THD and Gain vs Frequency
Av - 40dB,BW - 20kHz
~

~

60
5D

FREOUENCY IHd

§

U

THD and Gain vs Frequency
Av - 54dB,BW - 5kHz

g

o
20

~

TA - AMBIENTTEMPERATURE rCI

THD and Gain VB Frequency
Av - 54 dB, BW - 30 kHz
60
50

~

-

t--... ......

D••

lA-AMBIENT TEMPEftAlURE ('CI

.

FREE AIR_
BII'CIW

0.2

I I

o

I
I

I.'

..

- 3 dB Bandwidth VB VollBge
Gain for SIBbie OperaUon

,.

FREQUENCY IHzI

10k

12

z

ZO

!i

10
0
10

BRIDGE

7

:h'=D~~' I-

CBVPASS' IOOpF
C,N' 0.1 pF
Av: 2oo
POUT' 0.5W

30

-++-t~L ·OSI

LMZ89&

RL ·m
'j'DuAL
}'811
DUAL

-A.

100

Ik

FREQUENCY IHzI

III<

lOOk

o

o

10
SUPPLY VOLTAGE IVI

12

TL/H/7920-2

1·188

Typical Performance Curves (Continued)
Total Harmonic Distortion
vs Power Output

Power Dissipation vs
Power Output RL = sn

Power Dissipation vs
Power Output RL = 4n

3.0 .--,--,,--,-,-,-.-,--,--,-.,

~

2.5

~~

2.0

zo;
if~

1-Y'+-+-+-++-bo'f-7f'-l

;;;10

2i~

wz
~~
g

LM1B9&
0.1

1.0

~

1.5

1.0 .....t-+-Ib"bo-"l-++-+-+-l
0.5

f-":PO:'1!!!''t'':':::=±-++-+-+-I

10

0.5

POWER OUTPUT IW/CHANNEL)

poWER OUTPUT IW/CHANNEL)

1.0

1.5

2.0

POWER OUTPUT IW/CHANNEL)

TLlH/7920-3

Equivalent Schematic
BOOTSTRAP 2

BooTSTRAP 1

12 (3)

3(9)

r-----~--~----------~._--------------._--------------~----------~~--+_----~-oV+

10k

oUTPUT 1

0-.............

lOOk

5(10)

.....+-+-0 oUTPUT 2

lOOk

10(2)

10k

L---------+---+~~~------. .--~1~17~)--t7-1.11-)------~~. .------+---i~13~1~4)+---------4,~I~I-I&)OGNO
-INPUT 1

+INPUT 1 BYPASS

-INPUT2

+INPUT 2

6, 9 No connection on LMl B96

TLlH17920-4

() indicates pin number for LM2B96

Connection Diagrams
Single-In-Line Package

•

+VS

Dual-In-Line Package
OUTPUT 2
14
13

-IN 1

12

BOOTSTRAP 1
GNO

+IN2

o

BDDTSTRAP2

-IN 2
-IN2
800TSTRAP2
+IN2

LM1896

OUTPUT 1

GNo

NC

+IN 1

LM2B96

o

BYPASS
-IN 1

TL/H/7920-5

BOOTSTRAP 1

Top View
OUTPUT 1
BYPASS

10
11

TL1H17920-6

Top View
1-189

II

U)

en
~

r---------------------------------------------------------------------------------,
Typical Applications

(Continued)

::::iE
-J

.....
U)

en
co

....

v+

Cs

~o~..:~_ _..._ _. .-o v+

::::iE
-J

TL/H/7920-8
TL/H17920-7

6, 9 No connection on LM1896
() Indicates pin number for LM2896

FIGURE 2. Stereo Amplifier with AV = 200, BW = 30 kHz

External Components (Figure2)
Components
1. R2, R5, R10, R13
2. R3, R12
3.R o
4. C1, C14

Comments
Setsvoltagegain,Av = 1 + R5/R2foronechanneiandAv = 1 + R10/R13
for the other channel.
Bootstrap resistor sets drive current for output stage and allows pins 3 and 12 to
go above Vs.
Works with Co to stabilize output stage.
Input coupling capacitor. Pins 1 and 14 are at a DC potential of Vs/2. Low
frequency pole set by:
fL =

5.C2,C13

6.C3,C12

1

---=:-'--::-

2?T RIN C1
Feedback capacitors. Ensure unity gain at DC. Also a low frequency pole at:
1
fL = 2?TR2C2
Bootstrap capacitors, used to increase drive to output stage. A low frequency
pole is set by:

1
?C5,C10
B.C?
9.Cc

fL = 2?TR3C3
Compensation capacitor. These stabilize the amplifiers and adjust their
bandwidth. See curve of bandwidth vs allowable gain.
Improves power supply rejection (See Typical Performance Curves). Increasing
C? increases turn·on delay.
Output coupling capacitor. Isolates pins 5 and 10 from the load. Low frequency
pole set by:

1

10. Co

11. Cs

fL=--2?T CcRL
Works with Ro to stabilize output stage.
Provides power supply filtering.

1·190

r

s::
......

Application Hints
Amp 1 has a voltage gain set by 1 + R5/R2. The output of
amp 1 drives amp 2 which is configured as an inverting
amplifier with unity gain. Because of this phase inversion in
amp 2, there is a 6 dB increase in voltage gain referenced to
Vi. The voltage gain in bridge is:

AM Radios
The LM1896/LM2896 has been designed fo fill a wide
range of audio power applications. A common problem with
IC audio power amplifiers has been poor signal-to-noise performance when used in AM radio applications. In a typical
radio application, the loopstick antenna is in close proximity
to the audio amplifer. Current flowing in the speaker and
power supply leads can cause electromagnetic coupling to
the loopstick, resulting in system oscillation. In addition,
most audio power amplifiers are not optimized for lowest
noise because of compensation requirements. If noise from
the audio amplifier radiates into the AM section, the sensitivity and signal-to-noise ratio will be degraded.

V~
62
PD=--X2=--X2
20 RL
20 X 4

+ Cdo

R2 + R5

R2'

PD = 0.9 Watts
This amount of dissipation is equivalent to driving two 40
loads in the stereo configuration.
When adjusting the frequency response in the bridge configuration, R5C5 and R10C10 form a 2 pole cascade and the
-3 dB bandwidth is actually shifted to a lower frequency:

1
Cdo = R5G5

A curve of -3 dB BW (Cdo) vs Av is shown in the Typical
Performance Curves.
Figure 3 shows a plot of recovered audio as a function of
field strength in ,,"VIM. The receiver section in this example
is an LM3820. The power amplifier is located about two
inches from the loopstick antenna. Speaker leads run parallel to the loopstick and are 1/8 inch from it. Referenced to a
20 dB SIN ratio, the improvement in noise performance
over conventional deSigns is about 10 dB. This corresponds
to an increase in usable sensitivity of about 8.5 dB.

BW = 0.707
27TRC
where R = feedback resistor
G = feedback capacitor
To measure the output voltage, a floating or differential meter should be used because a prolonged output short will
over diSSipate the package. Figure 1 shows the complete
bridge amplifier.

Bridge Amplifiers
The LM1896/LM2896 can be used in the bridge mode as a
monaural power amplifier. In addition to much higher power
output, the bridge configuration does not require output coupling capacitors. The load is connected directly between the
amplifier outputs as shown in Figure 4.
~.

dB

..
=

...'"

l-

III

-10

~iii

-20

:l! ~

-30

co::!!
co "

..g
~

ri

~

~

lIT

-50

-60

/,

III -

RECOVERED

NDISE AT

-40

II:
Q

II

. kTIW~ERJD
AUDID AT
SPEAKER

II:

-

"

~

StE~~~~
-riiffil~~!~:RWo'~HL~DEp~~~~K LEADS

.Tiiiiit~:~~:~~~!~N::,on

II:

0.01

OC)
CQ

en

fL=-_1_27T RaCa
Several precautions should be observed when using the
LM1896/LM2896 in bridge configuration. Because the amplifiers are driving the load out of phase, an 80 speaker will
appear as a 40 load, and a 40 speaker will appear as a 20
load. Power dissipation is twice as severe in this situation.
For example, if Vs = 6V and RL = 80 bridged, then the
maximum dissipation is:

Av(S) = S + Av Cdo

where Av =

s::

N

VO=2(1 +R5)
Vi
R2
Ca is used to prevent DC voltage on the output of amp 1
from causing offset in amp 2. Low frequency response is
influenced by:

The LM1896 exhibits extremely low wideband noise due in
part to an external capacitor C5 which is used to tailor the
bandwidth. The circuit shown in Figure 2 is capable of a
signal-to-noise ratio in excess of 60 dB referred to 50 mW.
Capacitor C5 not only limits the closed loop bandwidth, it
also provides overall loop compensation. Neglecting G2 in
Figure 2, the gain is:

S

OC)
CQ

en
.......
r

0.1

10

FIELD STRENGTH (mV/M)
TlIH1792D-9

FIGURE 3. Improved AM Sensitivity over Conventional Design

1-191

~r-------------------------------------------------------------~

~

::::i

i

Application Hints (Continued)

tvv;o-f

CO

.....

::::i

....I

R2

-:;rC2

C5
RB

T

Cl3

TUH17920-10

Figure 4. Bridge Amplifier Connection

Printed Circuit Layout
less than 50 kO to prevent an input-output oscillation. This
oscillation is dependent on the gain and the proximity of the
bridge elements Rs and Cs to the (+) input. If the bridge
mode is not used, do not insert Rs, Cs into the PCB.
To wire the amplifer into the bridge configuration, short the
capacitor on pin 7 (pin 1 of the LM1896) to ground. Connect
together the nodes labeled BRIDGE and drive the capacitor
connected to pin 5 (pin 14 of the LM1896).

Printed Circuit Board Layout
Figure 5 and Figure 6 show printed circuit board layouts for
the LM1B96 and LM2896. The circuits are wired as stereo
amplifiers. The signal source ground should return to the
input ground shown on the boards. Returning the loads to
power supply ground through a separate wire will keep the
THO at its lowest value. The inputs should be terminated in

COMPONENT SIDE

FIGURE 5. Printed Circuit Board Layout for the LM 1896
1-192

TL/H17920-11

r

...3:

Printed Circuit Layout (Continued)
~

~
<:!

...

~

~

...
~

...

<:!

S

Q)
(I)

$t\,
<:!d'"

§

...

~

c§i

r
3:

<§

::;

i'

N

,g;s

~ ....

~

.",<.;

en
......

<:!

~

<:!~

Q)
(I)

en

470llF

-1hCB

0.1 f./F

22QOpF

.Jt

-If!-

T

150 f./F

COMPONENT SIDE
TLIH17920-12

FIGURE 6. Printed Circuit Board Layout for the LM2896

II

1·193

NatiOnal

~ Semiconductor
Corporation

LM 1897 Low Noise Preamplifier
for Tape Playback Systems
• Low Voltage Battery Operation
4V
• Wide gain bandwidth due to broadband
76 dB @ 20 kHz
two amplifier approach
• High power supply rejection
105 dB
• Low distortion
0.03%
• Fast slew rate
6V//Ls
• Short circuit protection
• Internal diodes for diode switching applications
• Low cost external parts
• Excellent low frequency response
• Prevents "click" from being recorded onto the tape
during power supply cycling in tape playback
applications

General Description
The LM1897 is a dual high gain preamplifier for applications
requiring optimum noise performance. It is an ideal choice
for a tape playback amplifier when a combination of low
noise, high gain, good power supply rejection, and no power
up transients are desired. The application also provides
transient·free muting with a single pole grounding switch.

Features
•
•
•
•

Programmable turn·on delay
Transient·free power up-no pops
Transient·free muting
Low noise-0.6 /LV CCIR/ARM in a DIN circuit refer·
enced to gain at 1 kHz
Vee 12VDC

R210k

R3 1.5M2 5%
5%

R5
1.2M
R4 56k 5%

11

12

10
RIGHT
OUTPUT

RIGHT
INPUT

R6
10k

""="

LEFT
INPUT

10k
LEFT
OUTPUT

.".

10k

56k 5% 0.0022 ""

10k

5%

1.5MQ5%

3V

1.ZM

-wr-r-wr270k

R7
270k

" { OPTIONAL MUTE
CIRCUIT

.".

TLlH17094-1

FIGURE 1. Typical Tape Playback Preamplifier Application
Order Number LM1897N
See NS Package Number N16E

1·194

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
18V
Voltage on Pins 8 and 9
18V
Package Dissipation (Note 1)
715mW

Electrical Characteristics (TA =

Storage Temperature
Operating Temperature
Minimum Voltage On Any Pin
Lead Temperature (soldering, 10 sec.)

-65'Cto +150'C
O'Cto +70'C
-0.1 VDe
260'C

25'C, Vee = 12V, See Circuit-Figure 2)

Parameter

Conditions

Min

Typ

Operating Supply Voltage Range

Rs removed Irom circuit

Supply Current

Vee = 12V

Total Harmonic Distortion

1= 1 kHz, Y,N = 0.3 mY, Pins 7 & 10, Figure 2

0.03

THO + Noise (Note 2)

f = 1 kHz, VOUT = 1V, Pins 7 & 10, Figure 2

0.10

4
6

Max

Units

18

V

12

mA

%
0.25

%

Power Supply Rejection

Input Ref. I = 1 kHz, 1 VRMS

85

105

dB

Channel Separation

f = 1 kHz, Output = 1 VRMS, Output to Output

40

60

dB

Signal to Noise (Note 3)

Unweighted 32 Hz-12.74 kHz (Note 2)
CCIRIARM (Note 4)
A Weighted
CCIR, Peak (Note 5)

58
62
64
52

dB
dB
dB
dB

Noise

Output Voltage CCIRI ARM (Note 4)

120

200

/LV

0.5

2.0

28
±0.15
2.2
±30
10
600

29
±0.5
2.6
+200

/LA
k!l
dB
dB
V
mV
mA
/LA

Input Ampliliers
Input Bias Current
Input Impedance
A.C. Gain
A.C. Gain Imbalance
D.C. Output Voltage
D.C. Output Voltage Mismatch
Output Source Current
Output Sink Current

1= 1 kHz

50
27
1.8
-200
2
300

Pins 3 and 14
Pins 3 and 14
Pins 3 and 14

Output Amplifiers
Closed Loop Gain
Open Loop Voltage Gain
Gain Bandwidth Product
Slew Rate
Input Offset Voltage
Input Offset Current
Input Bias Current
Output Source Current
Output Sink Current
Output Voltage Swing

Pin 7 or 10
Pin70r10
Pin 7 or 10

Output Diode Leakage

Voltage on Pins 8 and 9 = 18V

Stable Operation
D.C.

5

2
400

110
5
6
2
20
250
10
900
11

5
100
500

0

10

VIV
dB
MHz
V//LS
mV
nA
nA
mA
/LA
Vpp
/LA

Note 1: For operation in ambient temperatures above 25°C, the device must be derated based on a 150"C maximum junction temperature and a thermal resistance

of 175°C/Walt junction to ambient.
Note 2: Measured with an average responding voltmeter using the filter circuit in Rgure 4. This simple filter is approximately equivalent to a "brick wall" filter with a

passband of 20 Hz to 20 kHz (see "Application Hints" section). For 1 kHz THO the 400 Hz high pass filter on the distortion analyzer is used.
Nole 3: The numbers are referred to an output level of 160 mV at Pins 7 and 10 using the circuit of Figure 2. This corresponds to an input level of 0.3 mV RMS at
333 Hz.
Nole 4: Measured with an average responding voltmeter using the Dolby lab's standard CCIR filter having a unity gain reference at 2 kHz.
Nole 5: Measured using the Rhode-Schwarz psophometer, model UPGR.

1-195

II

R5820k

Vee

12V
R210k 1%
C2

10""

+

Rll0k

R4 54.9k 1%

10

11

INPUTG

:1.--8'_

2.49k 1%
LMI897

10k
LEFT

10121%

INPUT
ATTENUATOR
250:1
48dB

10k
10""
10k 1%

-=

*

OUTPUT
SELECT

1.4Mgl%

820k
TUH/7094-2

FIGURE 2. General Test Circuit

Gain vs. Frequency
80

CIRCUIT OF FIGURE 2

70

"

40

"

......
~

30
20

50 100 200 500 lk 2k

5k 10k 2Dk

FREQUENCY (Hz.
TL/H/7094-3

FIGURE 3. Frequency Response of Test Circuit

INPUT
FROM LM1897
PINS 7 OR 10

12.5k III
D.47~F

211

l000pF
10.5k12
211 I_--I_-I--~:
111.
0

HP334A DISTORTION ANALYZERI
VOLTMETER
TUHI7094-4

FIGURE 4. Simple 32 Hz-12740 Hz Filter and Meter

1-196

2.5V

REGULATOR

Mr-----'

TLlH/7094-5

FIGURE 5. Schematic Diagram
Component (Refer to
External
CompoFigure 1) External
nent
Component Function
Set turn-on delay and second
Rl,
amplifier's low frequency pole.
Leakage current in C2 results in
C2
DC offset between the amplifier's
inputs and therefore this current
should be kept low. Rl is set equal
to R2 such that any input offset
voltage due to bias current is
effectively cancelled. An input
offset voltage is generated by the
input offset current multiplied by
the value of these resistors.
R2

R3

R4

Cl

Set the DC and low frequency gain
of the output amplifier. The total
input offset voltage will also be
multiplied by the DC gain of this
amplifier. It is therefore essential
to keep the input offset voltage
specification in mind when
employing high DC gain in the
output amplifier; i.e. 5 mV x 400
= 2V offset at the output.
Set tape playback equalization
characteristics in conjunction with
R3 (calculations for the
component values are included in
the Applications Hints section).

Normal
Range
of Value
2 kO-40 kO

External
Component (Refer to
CompoFigure 1) External
nent
Component Function
Biases the output diode when it is
Rs
used in DC switching applications.
This resistor can be excluded if
diode switching is not desired.

0.1 ,.F10,.F
(Low
Leakage)

2kO40kO
500kO10MO

Normal
Range
of Value
2kO47kO

C3

Often used to resonate with tape
head in order to compensate for
tape playback losses including
tape head gap and eddy current.
For a typical cassette tape head,
the resonant frequency selected is
usually between 13 and 17kHz.

100 pF1000 pF

Rs

Increases the output DC bias
voltage from the nominal2.2V
value (See the Application Hints
section).

100 kO10MO

R7

Optionally used for tape muting.
The use of this resistor can also
provide "No Pop" turn-off if
desired.

Application Hints
10kO200kO

DISTORTION MEASUREMENT METHOD
In order to clearly interpret and compare specifications and
measurements for low noise preamplifiers, it is necessary to
understand several basic concepts of noise. An obvious example is the measurement of total harmonic distortion at
very low input signal levels. Distortion analyzers provide outputs which allow viewing of the distortion products on an
oscilloscope. The oscilloscope often reveals that the "distortion" being measured contains 1) distortion, 2) noise, and
3) 50 or 60 cycle AC line hum.

0.00047,.F0.01 ,.F

1-197

II

~

~
.....
:::E
....I

r---------------------------------------------------------------------------------,
Application Hints (Continued)
Line hum can be detected by using the "line sync" on the
oscilloscope (horizontal sync selector). The triggering of a
constant wave form indicates that AC line pickup is present.
This is usually the result of electro-magnetic coupling into
the preamplifier's input or improper test equipment grounding, which simply must be eliminated before making further
measurements!

Integrated circuits have additional open loop gain allowing
aditional feedback loop gain in order to lower harmonic distortion and improve frequency response. It is this additional
bandwidth that can lead to erroneous Signal to noise measurements if not considered during the measurement process. In the typical example above, the difference in bandwidth appears small on a log scale but the factor of lOin
bandwidth, (200 kHz to 2 MHz) can result in a 10 dB theoretical difference in the signal-to-noise ratio (white noise is
proportional to the square root of the bandwidth in a system).

Input coupling problems can usually be corrected by any
one of the following solutions: 1) shielding the source of the
magnetic field (using mu metal or steel), 2) magnetically
shielding the preamplifier, 3) physically moving the preamplifier far enough away from the magnetic field, or 4) using a
high pass filter (fo = 200 HZ-l kHz) at the output of the
preamplifier to prevent any line signal from entering the distortion analyzer. Ground loop problems can be solved by
rearranging ground connections of the circuit and test
equipment.

In comparing audio amplifiers it is necessary to measure the
magnitude of noise in the audible bandwidth by using a
"weighting" filter.l A "weighting" filter alters the frequency
response in order to compensate for the average human
ear's sensitivity to certain undesirable frequency spectra.
The weighting filters at the same time provide the bandwidth
limiting as discussed in the previous paragraph.

Separating noise from distortion products is necessary
when it is desired to find the actual distortion and not the
signal-to-noise ratio of an amplifier. The distortion produced
by the LM1897 is predominately a second harmonic. It is for
this reason that the third and higher order harmonics can be
filtered without resulting in any appreciable error in the measurement. The filter also reduces the amount of noise in the
measured data. Another more tedious technique for measuring THD is to use a wave analyzer. Each harmonic is
measured and then summed in an RMS calculation. A typical curve is plotted for distortion vs. frequency using this
method. A typical curve is also included using a 20 Hz to
20 kHz 4th order filter.

The 32 Hz to 12740 Hz filter shown in Figure 4 is a simple
two pole, one zero filter, approximately equivalent to a
"brick wall" filter of 20 Hz to 20 kHz. This approximation is
absolutely valid if the noise has a flat energy spectrum over
the frequencies involved. In other words a measurement of
a noise source with constant spectral density through either
of the two filters would result in the same reading. The output frequency response of the two filters is shown is Figure
7.

To specify the distortion of the LM1897 accurately and also
not require unusual or tedious measurements the following
method is used. The output level is set to one volt RMS at 1
kHz (approximately 5 millivolts at the input). The output is
filtered with the circuit of Figure 4 to limit the bandwidth of
the noise and measured with a standard distortion analyzer.
The analyzer has a filter that is switched in to remove line
hum and ground loop pick-up as well as unrelated low frequency noise. The resulting measurement is fast and accurate.

j-BANDWIDTHi,

NOISE A,
20

FREQUENCY
"BRICKWALL" FILTER

20k

SIGNAL-TO-NOISE RATIO
In the measurement of the signal-to-noise ratio, misinterpretations of the numbers actually measured are common. One
amplifier may sound much quieter than another, but due to
improper testing techniques, they appear equal in measurements. This is often the case when comparing integrated
circuit to discrete preamplifier designs. Discrete transistor
preamps often "run out of gain" at high frequencies and
therefore have small bandwidths to noise as indicated below.

20

200

2k

20k

200k

1274020k
32·12740 Hz FILTER

TlIH/7094-7

FIGURE 7
Typical signal-to-noise figures are listed for several weighting filters which are commonly used in the measurement of
noise. The shape of all weighting filters is similar, with the
peak of the curve usually occurring in the 3 kHz-7 kHz region as shown below.

2M
20

FREQUENCY

200

2k

6k 20k

FREQUENCY

TlIH/7094-6

FIGURE 8

FIGURES
1-198

TLlH17094-8

Application Hints (Continued)
In addition to noise filtering, differing meter types give different noise readings. Meter responses include: 1) RMS reading, 2) average responding, 3) peak reading, and 4) quasi
peak reading. Although theoretical noise analysis is derived
using true RMS (root mean square) based calculations,
most actual measurement is taken with ARM (Average Responding Meter) test equipment. Unless otherwise noted an
average responding meter is used for all AC measurements
in this data sheet.

The general test circuit illustrates the topography of the system. The components determining the overall frequency response are external due to the extreme sensitivity when
matching a DIN equalization curve.
MUTE CIRCUIT
The LM1897 can be muted with the addition of two resistors
and a grounding switch, as shown in Figure 1. When the
circuit is not muted the additional resistors have no effect on
the AC performance. They do have an effect on the DC Q
pOint however.
The difference in the DC output voltages of the input amplifiers is applied across the mute resistors (R7) and the positive input resistors (R1). This results in an additional offset
at the input of the output amplifiers. To keep this offset to a
minimum R7 should be as large as possible to achieve effective muting. In all cases R7 should be at least ten times
R1. A typical value of R7 is 25 to 50 times R1.

BASIC CIRCUIT APPROACH

The LM1897 IC incorporates a two stage broadband design
which minimizes noise, attains overall DC stability and prevents audible transients during turn-on.
The first stage is a direct coupled amplifier with an internal
gain of 25 VIV (28 dB). Direct coupling to the tape head
reduces input source impedance and external component
cost by removing the input coupling capacitor. A typical input coupling capacitor of 1 /LF has a reactance of 1.5 kn at
100 Hz. The resulting noise due to the amplifier's input
noise current can dominate the noise voltage at the output
of the playback system. The input of the amplifier is biased
from a reference voltage that is temperature compensated
to produce a quiescent DC voltage of 2.2V at the output of
the first stage. The input stage bias current that flows
through the tape head is kept below 2 /LA in order to prevent any erasure of tape moving past the head. An added
advantage of DC biaSing is the prevention of large current
transients during the charging of coupling capacitors at turnon and turn-off.

CAPACITOR-COUPLED INPUT
The LM1897 is intended to be coupled directly to the signal
source. Direct coupling permits faster turn-on and less lowfrequency noise than would be possible with a capacitorcoupled input. However, there are some applications which
require that the signal source be referred to ground and
coupled to the input through a capacitor. Figure 9 is an example of an LM1897 with a capacitor-coupled input. As
shown, the circuit has a flat frequency response and is suitable for use as a microphone preamp.

Rs provides a DC path for input bias current. The value of
Rs should be as low as possible without loading the source.
A very large value of Rs can cause excessive DC offset at
the amplifier output. In order to avoid turn-on pops, the inverting input of the second amplifier must be at a higher
voltage than the non-inverting input when Vee is applied.
Rla, Rll, R12, and Dl ensure that this condition will be met.
If later stages in the playback system employ turn-on muting
circuitry, these extra components may not be needed. The
value of Rla depends on Vee as defined by the following
relationship:

The second stage provides additional gain and proper
equalization while preventing audible turn-on transients or
"pops". The output (Pin 10) is kept low until C2 charges
through R1. When the voltage on C2 gets close to the DC
voltage on Pin 14, the output rises exponentially to its final
DC value. The result is a transient-free turn-on characteristic.
Internal diodes are provided to facilitate electronic diode
switching popular in automotive applications.

Rla = (Vee - 1)
+12V

01

R12
10k

R3
lOOk

II

Rll
lk

G4

~;'\
lOOk

Rl0
11k

x 1k

":"

R2
10k

14

470 pF

R5
68k
Rl
10k

":"

":"

TLlH/7094-9

FIGURE 9. Microphone Preamplifier with CapaCitor Coupled Input

1-199

Application Hints (Continued)
Design Equation
The overall gain of the circuit is given by:

-R4 Ra ] (s + _1_) (s +
1
) (1)
R2(R3 + R4)
R4Cl
(Ra + R4)Cl
Standard cassette tapes require equalization of 3180
(50
Hz) and 120 ,...s (1.3kHz). These time constants result in an
AC gain at 1 kHz given by:

AV = 25 [

"'S

Using the worst case values in the electrical characteristics
reduces this to
t.VOUT= ± [0.4(1

-R R )
{3180,...sor50Hz}
Av(l kHz) = 25 ( R (R 4 a ) 1.663
and
2 3 + R4
120,...sor1326Hz

~ (200nA(Rl -

(2)
Using the pole and zero locations of the transfer function,
the two other equations needed to solve for the component
values are:

(5)
(6)

10kO

The value of Ra is normally not changed. This results in an
error of less than 0.2 dB in the low frequency response.

1.39 MO

~ 1.4 MO 1%

To bias the output amplifier output voltage at 6 volts (half
supply):
R5 = 2.2(1.4 MO) = 811 kO
6 - 2.2

(8)

Pins 8 and 9 are biased 0.7 volts less than VOUT (pin 7 or
10). When these diodes are used the output (pin 7 or 10)
should be biased at one half the minimum operating supply
voltage. Equation (8) can be rewritten to solve for R5.
_
2. 2R3
5 - Vo - 2.2

0.5mV

Ra = 217Cl ;51.96)

The output voltage of the LM1897 is set by the input amplifier DC voltage at pin 3 or 14, and by Ra and R5.

R

(12)

Use 0.0022 ,...F and determine:
1
R4 =
C (
) = 54.6 kO ~ 54.9 kO 1%
217 1 1326

1

+ ::)

(::)

Rl = R2 = 10k
This minimizes errors due to the output amplifier bias currents.
-4.80 X lO-a
Cl =
[-100 mY] = 2400 pF ~ 0.0022 ",F

When chromium dioxide tape is used, the defined time constants are 3180 ,...s and 70 ,...s. This changes equation (3) to:

Nominal VOUT (pin 7 or 10) = 2.2 (1

C~:J

If we desire a tape preamp with 100 mV output signal from a
tape head with a nominal output of 0.5 mV at 1 kHz for
standard ferric cassette tape, the external components are
determined as follows. The value of R2 is arbitrarily set to 10
kO.

[: l7C l;51.96)]} (1.663)

[ R2 217Cl (50)]

(11)

Example

We can now solve for Cl as a function of R2, or:

C _ -4.80 X 10- 3
1 - R2 [AV(1 kHz)]

+ 50nA(Rl + R2) + 5mV) ) ]

Delay Time t = R1 C2 1n

(4)

{[217Cl~1326)]

Rll>

The turn·on delay is set by Rl and C2; delay can be approximated by:

(3)

Av(l kHz) = -25

+~) +

~ 820 kO

The maximum variation in the output voltage is found using
equation (11):
aVOUT = ±1.9V
The low frequency response and turn-on delay determine
the value of C2. For Rl = 10k and C2 = 10,...F the low
frequency 3 dB point is 1.6 Hz and the turn-on delay is 0.4
seconds, from equation (12).

(9)

The output voltage of the LM1897 will vary from that given
in equation (8) due to variations in the input amplifier DC
voltage as well as the output amplifier input bias current,
input offset current and input offset voltage. The following
equation gives the worst case variation in the output voltage.

The complete circuit is shown in Figure 2. A circuit with 5%
components and biased for a minimum supply of 10 volts is
shown in Figure 1. If additional gain is needed Rl and R2
can be reduced without changing the frequency response of
the circuit.
Reference 1: CCIR/ARM: A Practical Noise Measurement
Method; by Ray Dolby, David Robinson and Kenneth Gundry, AES Preprint No. 1353 (F-3).

1-200

r3:
.....

Typical Performance Characteristics
Total Harmonic Distortion vs
Frequency
_ 10.0

i§
~

ti

is
u

1!i

'~"
~

CIRCUIT OF FIGURE 2
VOUT= IVRMS

II

2.0
1.0
.5

350

ffi

ii:
::l

120

I I I I I

!100 ./'

.....THD WITHOUT FILTER

.2 L -

7~~~z~~~~:~I&~ER

=
=
~

l-

.02
.0 I

20

THO USING WAVE ANALYZER

60

I I I I I I

40

50 100 200 500 lk 2k 5k 10k 20k
FREQUENCY

10

12

140

R5

,_

rOVi D

14

16

..;
Q

I--

~

14

16

I

50

1/1/

80
CIRCUIT Of fiGURE 2
~

r-

l!i

S

i

SUPPLY VOLTAGE IVOLTS)

I

50 100 200 500 lk 2k

10

r"\

40

20

FREQUENCY 1Hz)

Input Amplifier Gain and
Phase vs Frequency

I

3.0

1!i

2.0

~

1.0

30d8

!

u

i

15
30
45
r- GAIN
60
20dB
\
15
1adB
90
105
Od8
120
135
-IOdS
150
165
-20dS
180
10 100 lk 10k lOOk 1M 10M 100M
PHASE"

INPUf AMPLlilER ONiy
Vcc=l2V
1= 1kHz

4.0

-

r-..

~

0
0

20

40

80

60

100

INPUT ImY RMS)

i
~

~

~

iE

1'-

30
60
90
.......
120
150
0A1tl'
180
\
210
240
210
300
330
360
10 100 lk 10k lOOk 1M 10M 100M

......

PHASE

r-

"

i
~

FREQUENCY 1Hz)

Input Amplifier
DC Output Voltage vs
Temperature (Pins 3, 14)

Spot Noise Current vs
Frequency

100

2.5
1 0 _

a
~

~

~...

:!
~
:;:

140
120
100
80
60
40
20
0
-20
-40
-60

FREQUENCY 1Hz)

Spot Noise Voltage vs
Frequency

!:i

50 100200 500 lk 2k 5k 10k 20k

Output Amplifier Open Loop
Gain and Phase vs
Frequency

5.0

~
l!i

'"

50

30

5k 10k 20k

......

60

fREQUENCY 1Hz)

Input Amplifier THO vs
Input Level

/
II

Channel Separation vs
Frequency

m

20

1/

~

TURN-ON TIME DELAY ISECONDS)

80

40

18

....

~

rEr-~

o .1 .2 .3 .4 .5 .6 .1 .8 .91.01.11.2

vcrYV
12

-~ ~J ~t

~
II:

18

60

10

150

INPUT REfERRED
CIRCUIT OF fiGURE 2

~ 100

8

~

~ 100

120

4

:j"

PSRR vs Frequency

CIRCUIT OF AGURE 2

o

200

Vee IVOLTS)

ICC vs Supply Voltage
10

.,;

~

z

INPUT REFERRED
CIRCUIT OF FIGURE 2
R5 REMOVED
1=lkHz
Av=47dB @ 1kHz
4

L-l

:g

~

0

II

I

300
250

1i

80

I
.05

Turn On Delay vs
Component Values and Gain

PSRRvsVcc
140

I I

~ 5.0

E

co

~

10

2.0

RS

56011-=

1.5

is

1.0

i

0.5

~

!!l

"-

!il
1
10

100

lk

FREQUENCY 1Hz)

10k

0.1 L-J...J...L.WIlL-,W.WJ.llL....L..J..LIJJ1II
10
1k
10k
100
FREQUENCY 1Hz)

0
-50 -25

I
25

50

75

100

TEMPERATURE I'C)
TLlH17094-10

1·201

co
......

II

NatiOnal

~ Semiconductor
Corporation

LM2002/LM2002A 8 Watt Audio Power Amplifier
General Description
The LM2002 is a cost effective, high power amplifier suited
for automotive applications. High current capability (3.5A)
enables the device to drive low impedance loads with low
distortion. The LM2002 is current limited and thermally protected. High voltage protection is available (LM2002A)
which enables the amplifier to withstand 40V transients on
its supply. The LM2002 comes in a 5-pin TO-220 package.

Features

•
•
•
•
•
•
•

Externally programmable gain
Wide supply voltage range (5V-20V)
Few external parts required
Low distortion
High input impedance
No turn-on transients
High voltage protection available (LM2002A)

• Low noise
• AC short circuit protected
• Pin for pin compatible with TDA2002

• High peak current capability (3.5A)
• Large output voltage swing

Equivalent Schematic

.----+"";:"OVOUT

+INPUT

-INPUT

TL/H17929-1

Connection Diagram

Typical Application

Plastic Package

1"~"''''''
: . OUTPUT
3 GROUND

2 INVERTING INPUT
1 NON·INVERTING INPUT

TLlH/7929-2

Order Number LM2002T or LM2002AT
See NS Package Number T05A

+)
20DQ~F

1.0

INOTE 11

"*,"O.,.F

470",F

4n

2.2

TLlH17929-3

1-202

r
3:

Absolute Maximum Ratings

N

o

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

o
.......
r
N

Output Current
Repetitive
Non·repetitive

3.5A
4.5A

Peak Supply Voltage (50 ms)
LM2002A (Note 2)
LM2002

40V
25V

Input Voltage
Power Dissipation (Note 3)

Operating Supply Voltage

20V

Operating Temperature

±0.5V
15W
O·Cto +70·C

s:
N
o
o

N

l>

- 60·C to + 150·C

Storage Temperature

260·C

Lead Temperature (Soldering, 10 sec.)

Electrical Characteristics
Vs

=

14.4V, TTAB

=

25·C, Av

=

100 (40 dB), RL

Parameter

=

40, unless otherwise specified

Conditions

DC Output Level
Quiescent Supply Current

Min

Typ

Max

6.4

7.2

8

V

45

80

mA

Excludes Current in Feedback Resistors

Supply Voltage Range

5

Input Resistance

kO

100

kHz

4.3
6.5

W
W

4.8
7.4

W
W

5.2
8
9

W
W
W

6.5
10
10.5

W
W
W

0.1
0.1

%
%

40
44

dB
dB

0, 15 kHz Bandwidth

2

)J.V

100 kO, 15 kHz Bandwidth

40

pA

=

Bandwidth

Gain
Vs
RL
RL
Vs
RL
RL
Vs
RL
RL
RL
Vs
RL
RL
RL

=
=
=
=
=
=
=
=
=
=
=
=
=
=

13.2V, f = 1 kHz
40, THD = 10%
20, THD = 10%
13.8V, f = 1 kHz
40, THD = 10%
20, THD = 10%
14.4V, f = 1 kHz
40, THD = 10%
20, THD = 10%
1.60, THD = 10%
16V,f = 1 kHz
40, THD = 10%
20, THD = 10%
1.60, THD = 10%

THD

Po
Po

2W, RL
4W, RL

Ripple Rejection

RS
Rs

=
=
=
=

Input Noise Voltage

Rs
Rs

=
=

V

150

Output Power

Input Noise Current

20

Units

40 dB

500, f
500, f

4.8
7

= 40, f = 1 kHz
= 20, f = 1 kHz
= 100 Hz
= 1 kHz

30

Note 1: A 1.0 resistor and 0.1 /LF capacitor should be placed as close as possible to pins 3 and 4 for stability.
Nole 2: The

LM2002 shuts down above 25V.

Note 3: For operating at elevated temperatures, the device must be derated based on a 150"'C maximum junction temperature and a thermal resistance of 4"'C/W
junction to case.

1·203

II

Typical Performance Characteristics
Device Dissipation vs
Ambient Temperature
16

~

12

;::

10

;;

lJ

Ii!

"

~
o

RL ·2!l

iNFlilTE rAT SIN~_ c-

14

10

SIJK

I I I I
I I I I
o m

~

~

Q

~

I

ro

~

~

10

Open Loop Gain
vs Frequency

~

."
.,
~

12

o

14

70

:9.

4

6

8 10 12 14 16 18

Supply Current VB
Supply Voltage
60

C>

ti

30
10

o
lk

-20

~

-30

::cr

-40

::

-5D

::;

I

I
I

100

RS·50
-10

z

50

20

~

co

1ii

I

60

.

2

OUTPUT POWER IW)

Supply Ripple Rejection
vs Frequency

11'IWI
III

80

40

/

70

90

!j
co

'-- -

THO ·10%

VS·15V

OUTPUT POWER IW)

100

"z

V

THO.3}

II I~ /'
~V~

TA - AMBIENTTEMPERATURE I C)

ii

V~.JOV -

12

cJ HE~T J

r- 2: c~ HE~T SIr- .......

c
=

Power Dissipation VB
Output Power
16

-t-

14

Power Dissipation vs
Output Power

iil

lOOk

-

t

10

16

1111111

RL .2fYF-

10.0

11

1111111
1111111

o

2

4

6

2.0

8 10 12 14 16 18 20

1.0

:;;

0.'

~

I JI

c;

I 1/

0.2
0.1
0.05

i- Rl·4l!

I i
I I

20

50 100200 500 lk 2k

20

.....

~

14

..

12

V

~

10

~~

!;

2.5W

0.02

I

7t7
VYL.-"

JL•

50 100200 500 lk 2k

r--r-

RL·4S2 ....

~

~

/X.A""

~~L·~l!-

14:

I

I

z

I

0.01
20

Output Swing vs
Supply Voltage

16

1.0

50 10k 20k

FREQUENCY (Hz)

18

0.5

0.1

Ko5W

0.01

Distortion vs Frequency

0.05

z."L

"- r-...

OUTPUT POWE R (W)

0.2

I

0.02
10

5.0 r---AV ·100
Vs • 14.4V
2.0 r---RL -212

~

~

;;

-H

0.1

VSUPPLV IV)

~

I I

1111

I

10.0

I
;

RL -4.l!, VS'14AV_

\41

!!
g

Distortion vs Frequency
Vs" 14.4V

Rl '''In,Vs= 13.2V_

Y

.....:~

2 4 6 8 10 12 14 16 18 H

5.0 I--AV·l00

I I

RL· 2l!, Vs • 14.4V

/I

p

o

VSUPPLV IV)

RL ·412, Vs· Il.2V

14

o

o
10k

Distortion vs Output Power

1111111
1111111

8

20
10

1.

THO~I~

12
10

I.....

30

FREQUENCY (Hz)

Output Power vs
Supply Voltage
18

40

iil

FREQUENCV 1Hz)

20

ffi

,-

,-

::;

100

1M

50

~_

-60
10k

1

o

5. 10k 20'

o

2 4

6

8 10 12 14 16 18 20
VSUPPlV IV)

FREQUENCV 1Hz)

TUH/7929-4

1-204

.-------------------------------------------------------------------------,r

s::

Typical Applications (Continued)

I\)

o
o

16W Bridge Amplifier

I\)

.......
r

s::

Vs
14.4V

Vs

14.4V

I\)

o

o
1D~F

SIGNAL........J
INPUT

"I

+

T

~

0.2~F

1M

220
lOOk

2.2

220
TL/H/7929-5

Component Layout

Single Amplifier

Vs
RL

= 20V
= 40

TL/H17929-6

"Staver V-5 Heatsink
Staver Company
41 Saxon Ave
P.O. Drawer H
Bayshore, NY 11706
TEL: (516) 666·8000

1-205

II

~

C
C

N

:i
~

r---------------------------------------------------------------------,

~ Semiconductor
NatiOnal

Corporation

LM2005 20-Watt Automotive Power Amplifier
General Description
The LM2005 is a dual high power amplifier, designed to
deliver optimum performance and reliability for automotive
applications. High current capability (3.5A) enables the device to deliver 1OW/channel into 2!l (LM2005T-S), or 20W
bridged monaural (LM2005T-M) into 4!l, with low distortion.

•
•
•
•

Features

•
•
•
•
•
•

•
•
•
•
•

Wide supply range (BV-1BV)
Externally programmable gain
With or without bootstrap
Low distortion
Low noise

Connection Diagram

High peak current capability
Po=20W bridge
High voltage protection
AC and DC output short circuit protection to ground or
across load
Thermal protection
Inductive load protection
Accidental open ground protection
Immunity to 40V power supply transients
3°C/W device dissipation
Pin for pin compatible with TDA2005

Typical Application
R3
120k

Plastic Package
TAB CONNECTED
TO PIN 6
11

10

o

9
B
7

6
5

4
3
2
1

BOOTSTRAP 1
OUTPUT 1

+ C6

+Vs
OUTPUT 2
BOOTSTRAP 2
GNO
INPUT +2
INPUT -2
BYPASS
INPUT -1
INPUT +1

2k

110
Co

O.I PF

T

1

R5

12

TLlH/5129-1

Order Number LM2005T·S
or LM2005T·M
See NS Package Number T11A

110

1

TOP VIEW

220 pF

R4

R2
lk

T

CO
O.1 PF

Rl
12

TLlH/5129-2

FIGURE 1. 20W Bridge Amplifier Application and Test Circuit

1-206

r-

s::

LM2005T-M and LM2005T-S
Absolute Maximum Ratings

N

o
o

C1I

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Supply Voltage
18V
DC Supply Voltage (Note 1)

Output Current
Repetitive (Note 2)
Non-Repetitive
Power Dissipation
Operating Temperature
Storage Temperature

28V
40V

Peak Supply Voltage (50 ms)

3.5A
4.5A
30W
-40'C to + 85'C
-60'C to + 150'C

Lead Temp. (Soldering, 10 seconds)

260'C

LM2005T-M
Electrical Characteristics

Refer to the bridge application circuit, Figure 1, T amb = 25'C, AV = 50 dB,
Rth (heatsink) = 4'C/W, unless otherwise specified
Parameter

Test Conditions

Supply Voltage

Min

Max
18

V

±20

±150
±150

mV
mV

75
70

150
160

rnA
rnA

8

Output Offset Voltage (Note 3)
(between Pin 8 and 10)

Vs = 14.4V
Vs = 13.2V

Total Quiescent Drain Current
Includes Current in Feedback Resistors

Vs = 14.4V
Vs = 13.2V

RL = 40
RL = 3.20

Output Power

d = 10%
Vs = 14.4V

f = 1 kHz
RL= 40
RL = 3.20
RL = 3.20

Vs = 13.2V
THO

18
20
17

20
22
19

f = 1 kHz
Vs = 14.4V
RL = 40
Po = 50 mWto 15W
Vs = 13.2V
RL = 3.20
Po = 50 mWto 13W
f = 1 kHz
Po= 2W
Po= 2W

Input Sensitivity

f = 1 kHz

Low Frequency Roll Off ( - 3 dB)

RL = 3.20

High Frequency Roll Off (-3 dB)

RL = 3.20

20
45

f = 1 kHz
Rg = 10 kO (Note 4)

Supply Voltage Rejection

Rg = 10kO
C4 = 10".F

fripple = 100 Hz
VripPle = 0.5V

Efficiency

Vs
Po
Po
Vs
Po

f=
RL
RL
f=
RL

Output Voltage with One Side
of the Speaker Shorted to Ground
Note 1: Internal voltage limit. Shuts down above 20V.

14.4V
20W
22W
13.2V
19W

Vs = 14.4V
Vs = 13.2V

%

1

%
mV
mV
kO

40

Closed Loop Voltage Gain

=
=
=
=
=

1

70

Total Input Noise Voltage

1 kHz
= 40
= 3.20
1 kHz
= 3.20

RL = 40
RL = 3.2V

Note 2: Internal current limit.
kHz.

1-207

Hz
kHz

50
3

45

Units

W
W
W

9
8

RL = 40
RL = 3.20

Input Resistance

Note 3: For LM200ST-M only.
Note 4: Bandwidth filter. 22 Hz to 22

Typ

dB
10

".V

55

dB

60
60

%
%

58

%
2

V

II

LM200ST-S
Electrical Characteristics Refer to the stereo application circuit. Figure 2. Tamb =

25'C. Gv = 50 dB.

Rth (heatsink) = 4'C/W. unless otherwise specified
Parameter

Test Conditions

Supply Voltage
Vs = 14.4V
Vs = 13.2V

Total Quiescent Drain Current
Includes Current in Feedback Resistors

Vs = 14.4V
Vs = 13.2V

Output Power
(Each Channel)

f = 1 kHz
Vs = 14.4V

Vs = 13.2V
Vs = 16V

CrossTalk
(Note 5)

f =
Vs
Po
Vs
Po
Vs
Po
Vs
Po

6.6
6

d = 10%
RL=40
RL = 3.20
RL = 20
RL = 1.60
RL = 3.20
RL = 1.60
RL = 20

1 kHz
= 14.4V
RL
= 50 mWto 4W
= 14.4V
RL
= 50 mWt06W
= 13.2V
RL
= 50mWt03W
= 13.2V
RL
= 40 mW to 6W

Input Resistance

Max

Units

18

V

7.2
6.6

7.8
7.2

V
V

65
62

120
120

mA
mA

Vs =
RL =
Vo =
Rg =

14.4V
40
4Vrms
5kO

6
7
9
10
6
9

6.5
8
10
11
6.5
10
12

W
W
W
W
W
W
W

= 40
0.2

1

%

0.3

1

%

0.2

1

%

0.3

1

%

= 20
= 3.20
= 1.60

f = 1 kHz

40

f = 10kHz

Input Saturation Voltage
Input Sensitivity

Typ

8

Quiescent Output Voltage

THD
(Each Channel)

Min

60

dB

40

dB
mV

300
f = 1 kHz

f = 1 kHz

Po= 1W
RL = 40
RL = 3.20
Non-Inverting Input

70

Inverting Input
Low Frequency Roll Off (-3 dB)

RL = 20

High Frequency Roll Off (-3 dB)

RL = 20

Voltage Gain (Open Loop)

f = 1 kHz

Voltage Gain (Closed Loop)

f = 1 kHz

6
5.5

mV

200

kO

10

kO
50

15
90
48

Closed Loop Gain Matching

50

dB
51

Rg = 10 kO (Note 6)

Supply Voltage Rejection

Rg =10kO
C3=10p.F

fripple= 100 Hz
Vripple = 0.5V

Efficiency

Vs =
RL =
RL=
Vs =
RL =
RL =

f =
Po
Po
f =
Po
Po

14.4V
40
20
13.2V
3.20
1.60

Note 5: For LM2005T-S only.
Note 6: Bandwidth filter. 22 Hz to 22 kHz.

1-208

1.5

1 kHz
= 6.5W
= 10W
1 kHz
= 6.5W
= 10W

35

dB
dB

0.5

Total Input Noise Voltage

Hz
kHz

5

p.V

45

dB

70
60

%
%

70
60

%
%

~-----------------------------------------------'r

s::

Equivalent Schematic

-,."

o
o

~IO

-*-

~

U1

Io

r*•

N

T

T

!!

r--!------,

II

t----f-

TLlH/5129-3

1-209

Ln

o
o
N
:E
....I

r---------------------------------------------------------------------------------,
External Components (Figure2j
Components

Comments

Components

Comments

1. R1, R2
RS,R4

Sets voltage gain,

S.C4, CS

Bootstrap capacitors, used to increase
drive to output stage.

6.C3

Improves power supply rejection.
Increasing C3 increases turn-on delay
(approximately 2 ms per ".F).

7. C2, C6

Inverting input DC decouple. Low
frequency pole:

R'

Av'" I + RI for one channel,

R'

Av = 1 + RS for the other.
Where R' is the equivalent resistance
of R2 in parallel with an internal 10k
resistor:

FL2

R'= 10k e R2.
R2+10k
If R2 <: 10k, then

21TZ(inverting)C2'

Z (inverting) "" 10 kO.
Output coupling capacitor. Isolates
pins 10 and B from load. Low
frequency pole;

B.CC

R2
Av"'I+ R1 '

2. R3

Adjusts output symmetry for maximum
power output.

3. Ro,Co

Works to stabilize internal output
stage. Necessary for stability. Co
should be ceramic disc or equivalently
good high frequency capacitor.

4.CI,C9

Input coupling capacitor. Low
frequency pole set by

1
FL3=-----·
21TRLCC
Power supply filtering.

9.CS

F 1=
1
L
21TZ (non-inverting) C1
Decreasing capacitor value will also
increase noise.

Typical Applications

(Continued)

+ C4
100 ~F

+ C6

C2
220 ~F

220 ~F

R4
Uk
Cc

~-.

'~n

RL

':'

+

+ Cc

211

RL
211

Co

I"
Ro
1

R5
3.3
':'

FIGURE 2_ lOW/Channel Stereo Amplifier Application and Test Circuit

1-210

TLlH15129-4

r-----------------------------------------------------------------------------,
Typical Performance Characteristics
Device Dissipation vs
Ambient Temperature

1

~ 24

11~rINITE HEAT SINK

~

20 2°CI/W

iJj

16

~

Ci
w

.iii
<.>

~EAT~
.......
.·1 ·r

4°C/W HEAT SINii""'-

12

80 C(W

o

.....

C

60

i

40

oS

...

.....

g

~

~EATI SINf

iil

I I I I
20 ~ 40 ~ 60 ro 60
TA - AMBIENT TEMPERATURE (OC)

20

:z:

..,"''""

~

DUAL
1=1 kHz

16

II
I I

ILL..!'

:-t.V

!

....
.... ....~ r.,..i"'"

:z:
'"

~

:::>

5o
8

~

'"'"
~

~~

o

8

Ay=~dB

16

RL-41l

co
'"

I
~L= ;:.

o

18

~~

§:

10

:z:

.~
co

~

.
....

~

o 1::::I:l1±II!!I1::±:l1:t±l!H~WlJlU

"

5"'"

20
10

o

10

Ay=50 dB
Vo=4 Vrms
RL=411
CmASS =10 pF
CIN =4.7.F

~
...

24
2D

I

12

~
..

50

iil
~
:::>

40

~

.

JS~D

~
8s=5 kll

I

30

I

20 Vs=14.4V
Ay=5o dB
lD CBYPASS=lo .F
DUAL

~
I-

f-

100
lk
FREQUENCY 1Hz)

10

BRIDGE
1=1 kHz
Av =50 dB
THD=ID%
RL=411

16

f-

10k

WITH 800TSTRAP

I.....

V

,

I;'

1/ I"

r, I

,,~

~~ ~r-

DU Borry

o

~

100
lk
FREQUENCY 1Hz)

60

co

Power Output vs Supply
Voltage
28

30

w

.\.000'
RL-41l1

o

32

~

:z:
z

'"~

D.l
1
lD
POWER OUTPUT (WI CHANNEL)

60

~

If

'I

~

Power Supply Rejection
Ratio (Referred to the
Output) vs Frequency

~

70

40

~

1/

2D 5D 100 200 500 1k 2k 5k 10k 20k
FREQUENCY (Hz)

2

o

r--

o

z

f0.01

100

§.I

Channel Separation
(Referred to the Output)
vs Frequency

50

I\..

70

l-

~

~

I

0.2

W

r

'"
"'"
'"

II

<.>

RL!m

:e

"

Z

:e 0.4

~
M
~
SUPPLY VDLTAGE (V)

Z

~

:;;

~

co

18

I

1;;

'"

I-1kHz
Ay=5D dB Vs=14. 4V -

16

VS-14.4V
Ay=5o dB
0.8 1'o=2.5W

~

<.>

~

co

Total Harmonic Distortion
vs Power Output (Dual)

1=1 kHz
RL=411
Vs=l4.4V

14

0.6
Ci

W

8

12

1.0

§:
:z:

6

10 ~A:-'y-_~50::-d:':Br-TTTTI1rnr,..,;mnn

1
10
POWER OUTPUT (W)

10

8

SUPPLY VOLTAGE (V)

....."""

Total Harmonic Distortion
vs Power Output (Bridge)

'"

10~-L-LJ-~~~~~

18

.-!~ ~
.-!~ ..... RL-20

I

10
12
14
16
SUPPLY VOLTAGE (V)

0.1

12~r;~~-+-+~~~~

Total Harmonic Distortion
vs Frequency (Dual)

,~""

12

~

RL 411

2

10
12
14
16
SUPPLY VOLTAGE (V)

~

~r.,..

~

~ ~ ~kl:t:t~;j;;!;;!;;j;~

...

.=1 kHz

RL=211
RL=3.211
~.. ~

...

26~-+-t-r~~+-~~

~ 24 HH-+-+-t-t--r-r+-i

20

20

RL=I.~~

~~~~~~ I

12

~~r;~-+-+~~~~4

Output Swing vs
Supply Voltage
I.I.!.

CJ1

30 .---r-.-.-r--r-.---r~--r-.,

!

I-- ~

o
o

!£o
o

o W

--

1--

Power Output vs
Supply Voltage

iii
:z:

Output Offset Voltage vs
Supply Voltage

80

28

!is:
I\)

Supply Current vs
Supply Voltage

32

I

10k

8

1-211

lD
12
14
16
SUPPLY VDLTAGE (V)

18
TUH/5129-5

II

Application Hints
The high current capability of the LM2005 allows it to continuously endure either AC or DC short circuit of the output
with a maximum supply voltage of 16V. This will protect the
loudspeaker in a bridge mode, when a DC short of the output occurs on one side of the speaker. The device will prevent the speaker from destruction by reducing the DC
across the load (bridge mode) to typically less than 2
VDC(VS= 14.4V, RL =4n), by an internal current pullback
method.

supply or less than ground levels. The protection diodes will
clamp these transients to a safe VBE above and below the
rails.
The bridge configuration in Figure 3 is designed for applications requiring minimal printed circuit board area and maximum cost effectiveness. The circuit will function with the
elimination of bootstrap components R3, C4 and C5 (refer
to Figure 1). This will result in less output power by decreasing output voltage swing to the load. By using internal feedback resistors (typically 10 kn), feedback components R2,
R3 and C2 (Figure 1) may be omitted where closed loop
voltage gain accuracy is not critical. The net result is a stable, cost effective circuit that will satiSfy many application
needs.

The LM2005 can withstand a constant 28 VDC on the supply
with no damage (maximum operating voltage is 18V). The
device is also protected from load dump or dangerous transients up to 40V for 50 ms (every 1000 ms) on the supply
with no damage.
Protection diodes protect the device driving inductive loads,
during which the load can generate voltages greater than

r1t1~-.------t--v+

15D

TL/H/5129-6

AV

~

41.5dB@lkHz

FIGURE 3. Minimal Component Application Circuit
Component Side (Scale 2:1)

TL1H/5129-7

FIGURE 4. Printed Circuit Board Layout for LM2005
1-212

NatiOnal

~ Semiconductor
Corporation

LM2877 Dual 4-Watt Power Audio Amplifier
General Description
The LM2877 is a monolithic dual power amplifier designed
to deliver 4W/channel continuous into 8n loads. The
LM2877 is designed to operate with a low number of external components, and still provide flexibility for use in stereo
phonographs, tape recorders and AM-FM stereo receivers,
etc. Each power amplifier is biased from a common internal
regulator to provide high power supply rejection and output
Q point centering. The LM2877 is internally compensated
for all gains greater than 10, and comes in an 11-lead single-in-line package.

Features
• 4W/channel
• - 68 dB ripple rejection, output referred
• - 70 dB channel separation, output referred

•
•
•
•
•

Wide supply range, 6-24V
Very low cross-over distortion
Low audio band noise
AC short circuit protected
Internal thermal shutdown

Applications
•
•
•
•
•
•
•

Multi-channel audio systems
Stereo phonographs
Tape recorders and players
AM-FM radio receivers
Servo amplifiers
Intercom systems
Automotive products

Connection Diagram
(Single-In-Line Package)
BIAS

-!. •

OUTPUT 1.2..

o

GNO...l
INPUTI-!
FEEOBACK 1"":'

*GNO"'!"
7

FEEOBACK2-

II

o

INPUT22

GNO...!
OUTPUT2...!!

v+...!!

......._----......

TL/H17933-1

Top View
Order Number LM2877P
See NS Package Number P11A
"'Pin 6 can be connected to pin 3 or pin 9,
il nOI. pin 6 must be 1811 with NO connection.

1-213

.....
.....
co
N

:E
..I

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
Input Voltage

Parameter

Lead Temperature (Soldering, 10 sec.)

Distortion, THD

Conditions

Min

Po= OW

Typ

Max

Units

25

50

mA

24

V

6
f = 1 kHz, THD = 10%, TTAB = 25'C
Vs = 20V
Vs = 18V
Vs = 12V,RL = 4n
f =
Po
Po
Po
f =
Po
Po
Po

260'C

20V, TTAB = 25'C, RL = 8n, Av = 50 (34 dB) unless otherwise specified.

Operating Supply Voltage
Output Power/Channel

O'Cto +70'C
- 65'C to + 150'C
150'C

Storage Temperature
Junction Temperature

26V
±0.7V

Electrical Characteristics Vs =
Total Supply Current

Operating Temperature

4.0
1.5

1 kHz, Vs = 20V
= 50 mW/Channel
= 1W/Channel
= 2W/Channel
1 kHz, Vs = 12V, RL = 4n
= 50 mW/Channel
= 500 mW/Channel
= 1W/Channel

Output Swing

RL = 8n

Channel Separation

CF = 50 /LF, CIN = 0.1 /LF, f = 1 kHz,
Output Referred
Vs = 20V, Vo = 4 Vrms
Vs = 7V, Vo = 0.5 Vrms

4.5
3.6
1.9
0.1
0.07
0.07
0.25
0.20
0.15

W
W
W

1

1

%
%
%
%
%
%

Vs-4

Vp.p

-50

-70
-60

dB
dB

-50

-68
-40

dB
dB

2.5

/LV

0.80

mV

70

dB

Input Offset Voltage

15

mV

Input Bias Current

50

nA

4

Mn

PSRR Power Supply

CF = 50 /LF, CIN = 0.1 /LF, f = 120 Hz

Rejection Ratio

Output Referred
Vs = 20V, VRIPPLE = 1 Vrms
Vs = 7V, VRIPPLE = 0.5 Vrms

Noise

Open Loop Gain

Equivalent Input Noise
Rs = 0, CIN = 0.1 /LF, BW = 20 Hz-20 kHz
Output Noise Wideband
Rs = 0, CIN = 0.1 /LF, Av = 200
Rs = 0, f = 1 kHz, RL = 8n

Input Impedance

Open Loop

DC Output Level

Vs = 20V

9

10

11

V

Slew Rate

2.0

V//Ls

Power Bandwidth

65

kHz

Current Limit

1.0

Nole I: For operation at ambient lemperature grealer Ihan

A
25·C, the LM2877 must be derated based on a maximum 150·C junction temperature using a thermal

resistance which depends upon device mounting techniques.

1-214

Equivalent Schematic Diagram

::

..
N

.........'"
CI

W
W

...
I

...,
;;;

N

.

... 1-

~

+'

...=
~

~

'"

...
'"

. -...
..
I-

::::I

+'

....

"' '"

.....- - - -....-O~
w
~
I

- -.....-0--111

1-215

II

.....
.....

re

::is

Typical Performance Characteristics

..J

Power Supply Rejection Ratio
(Referred to the Output) vs
Frequency

Device Dissipation vs
Ambient Temperature
10

-.l ALUMINUM THICKNESS .. 1J1BINCH
INh,nE ;EATSi,,-

lXl.l~~~~~~,w~

lS'CtW

1.4~~::=~:~~:~

~

TYPI~~ASSI$

3X3IN28°C/~

I-~ i::.r ~~

2S"C/W

r- ~ ~~

=
:s

g

40

~

~

I I

o
o

:s

g

50

3D

~

FI'IEE.lIR65·C/W

70
60

~

0:

I

70
60

E
i1

.,z

40 50 60 70

i
!;

~
"

~

0:

~

80

;

..

.,

V~IP~lE ~ O.l:Vrm?

VRIPPLE "0.5 Vrms

1Jl

10

G

lZ

14

60

Vee

5

50

~I~ • ooO~F

40

~

GOD

t - r-

~ I-"""

~

'/

!; 400

10

100

.13

..

§

Jill

«

Wl1

lOOk

ri(L,4v

10

~

"~
1i!

0.1

~

~iV :r::

~

"'"

,... t:;:t1

11

I I

o

"........e
lk

10k

lOOk

100

z

lk

RL

=an

L

lZ

i"

V

w

«
'"

~>

lOOk

Output Swing vs Supply
Voltage
16

60

10k

FREQUENCy IHzl

VS' 20V
RL" an

r-.

V

1/

V

40

V
V

20

o

o
100

POWER OUTPUT {W/CHANNELI

0.1

~

BO

THO- 3%

lOOk

z
e

100

I.2r:h,.

10k

g

Open Loop Gain vs
Frequency

ZOV

lk

Total Harmonic Distortion
vs Frequency

FREQUENCY {Hzl

18V

!'rHO -10%

100

e
l;;
c;

100

I I

LL

II111I Ifl
10

FREQUENCY {Hzl

~
~

Power Dissipation vs
Power Output

V

50

40

10k

e

POWER OUTPUT {W/CHANNELI

11

C:~ ~llll~04l ~I

z

lo~.

0.5 1.0 1.5 Z.O 2.5 l.o l.5 4.0

RL" 8n

I-IC:~I;I~.1 ~FI

GO

w

~

o

AV- 50

r::

:<

o

o

"
~

«

Total Harmonic Distortion
vs Frequency

"
"........e

ffi>

"

11

CB~;~~~ c 50;lF
Vee'" 7V
VO'" 500 mVrms

70

FREQUENCY {Hzl

1i!

V

'" ZOO
«

e

"~

V

~w

z

J~

.lll!

20V

.tWillL

16

800

~

lk

0;

Vour" 4Vlms

w

Average Supply Current vs
Power Output
~8n

IIUIIIIII
100

Channel Separation (Referred)
to the Output) vs Frequency

:s

p..
CBYPASS· 50 JAF

SUP1'LY VOLTAGE {VI

BOTH CHANNELS QRIVEN

lIciymilil'j

5J

80

=0.1 pF

CIN

Z

z

-

RL

"

FREQUENCY (Hzl

llllllLU

70

~

'BYPASS - 50"
CIN-O.l"F
_
VRIPPLE'" 1 Vrm$
f= 120 Hz
AV-50

.§

I

lo~

20

Channel Separation (Referred)
to the Output) vs Frequency

~
«

20

II

~ot V

W

10

AV' 50

FREQUENCY (Hzl

~VvVRIPPLE -I V.ms

o

"....

lo

CIN" 0.0647 /.IF

10

NOISE~

40

40

>-

VRIPPlE "1 Vrms

10D".F

Bo

1:1 ::!'b

60

~
~

20

Power Supply Rejection Ratio
(Referred to the Output) vs
Supply Voltage
0;

50

0:

TA-AMBIENT TEMPERATURE (OC)

:s

II
II

o

10 20 3D

80

Power Supply Rejection Ratio
(Referred to the Output) vs
Frequency

lk

10k

lOOk

FREQUENCY (Hz)

1M

4

8

10

12

14

16

18

ZO

SUPPLY VOL TACE {VI

TLlH17933-3

1·216

,-----------------------------------------------------------------------------, r
3:
N
Typical Applications
Q)

.....
.....

Stereo Phonograph Amplifier with Bass Tone Control

+

100PF

T

Ik
51k

510k

~ :~}r ·
'::"

STEREO
CERAMIC
CARTRIDGE

I
I
I

'::"

+

I
I
I

1M

ft
51k

+
T'ODPF
TL/H/7933-4

Frequency Response of Bass Tone Control
;;;
::!

65

a:
....
z

55

w

45

...c

.
:=.

;;;;;

- ~

MAXIMUM
BOOST
~ESPONSE

c

z

c

'";;:co
w

Z5

c
>

15

1/

./

35

co

~

TONE.!."
CONTROL FLAT

",

'/

-1,AXIMUM
CUT
RESPONSE

1
ZO

50 100 200 500 Ik 2k

5k 10k 20k

FREQUENCY (Hz)
Tl/H/7933-5

1-217

II

rreo

N

:5

r---------------------------------------------------------------------------------,
Typical Applications (Continued)
Stereo Amplifier with AV = 200
VSo-....--.

TL/H17933-6

Non-Inverting Amplifier Using Split Supply
2k

100k

Y+~b.
0.1 #F ':'

r-I 5

11

--,

I

2k

100k

TYP1CAL SPLIT SUPPLY
TL/H17933-7

1·218

,-----------------------------------------------------------------------------, r
s::
N
Typical Applications (Continued)
c»
"'-J
"'-J

Window Comparator Driving High, Low Lamps

r---t---------.-----.---o+V
lk

LOW

10

TL/H/7933-8

Truth Table
VIN

High

Low

<%V+
% V+ to%V+
>%V+

Off
Off
On

On
Off
Off

Application Hints
The LM2877 is an improved LM377 in typical audio applications. In the LM2877, the internal voltage regulator for the
input stage is generated from the voltage on pin 1. Normally,
the input common-mode range is within ±O.7V of this pin 1
voltage. Nevertheless, the common-mode range can be increased by externally forcing the voltage on pin 1. One way
to do this is to short pin 1 to the positive supply, pin 11.

The only special care required with the LM2877 is to limit
the maximum input differential voltage to ± 7V. If this differential voltage is exceeded, the input characteristics may
change.
Figure 1 shows a power op amp application with Av = 1.
The lOOk and 10k resistors set a noise gain of 10 and are
dictated by amplifier stability. The 10k resistor is bootstrapped by the feedback so the input resistance is dominated by the 1 MO resistor.

lOOk

II

15V

>~--oVOUT

10k

VINo-_......;!.j
1M

-15V

TO.

lIlF
TL/H17933-9

FIGURE 1

1-219

_

National

Semiconductor
Corporation

LM2878 Dual 5 Watt Power Audio Amplifier
General Description

Features

The LM2878 is a high voltage stereo power amplifier de·
signed to deliver 5W/channel continuous into 8n loads. The
amplifier is ideal for use with low regulation power supplies
due to the absolute maximum rating of 35V and its superior
power supply rejection. The LM2878 is designed to operate
with a low number of external components, and still provide
flexibility for use in stereo phonographs, tape recorders, and
AM·FM stereo receivers. The flexibility of the LM2878 al·
lows it to be used as a power operational amplifier, power
comparator or servo amplifier. The LM2878 is internally
compensated for all gains greater than 10, and comes in an
11-lead single-in-line package (SIP). The package has been
redesigned, resulting in the slightly degraded thermal characteristics shown in the figure Device Dissipation vs Ambient Temperature.

•
•
•
•
•
•
•

Wide operating range 6V-32V
5W/channel output
60 dB ripple rejection, output referred
70 dB channel separation, output referred
Low crossover distortion
AC short circuit protected
Internal thermal shutdown

Applications
•
•
•
•

Stereo phonographs
AM-FM radio receivers
Power op amp, power comparator
Servo amplifiers

Typical Applications
Frequency Response
of Bass Tone Control

+
100"FT
0.33"F

51k

lk

.,

65

j=;

~

..:3
....
.

Q

...

510k
lOOk

0:

55 t--

w

45

Q

~

0.033 "F

+)
+l

Q

'"
w

500"F

-!r1r
-=-

STEREO
CERAMIC
CARTRIDGE

I
I
I

-=-

Vs

>

1/
~AXIMUM
po ~ t-- ~~~PONSE
L

t-25

"~
Q

TONE.\'
CONTROL FLAT

I

15
ZO

50 100 ZOO 500 lk Zk

8u

T O . l "F

-=

I
I
I

ft

'"

2.m
1M

35

;;:

~

500"F

8n

r O . l "F
510k
lOOk

-=-

-=-

+
TL/H/7934-1

FIGURE 1. Stereo Phonograph Amplifier with Bass Tone Control
1-220

5k 10k ZOk

FREQUENCY IHzl
TL/H17934-2

":"

un

MAXIMUM
BOOST
NESPONSE

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

O'Cto +70'C

Storage Temperature

- 65'C to + 150'C

Junction Temperature

+ 150'C

Lead Temperature (Soldering, 10 sec.)

+ 260'C

35V

Input Voltage (Note 1)

±0.7V

Electrical Characteristics Vs =
Parameter
Total Supply Current

Operating Temperature (Note 2)

22V, TTAB = 25'C, RL =

Conditions

al1, Av =
Min

Po= OW

Operating Supply Voltage

50 (34 dB) unless otherwise specified.
Typ

Max

Units

10

50

mA

6

Output Power/Channel

f = 1 kHz, THO = 10%, TTAB = 25'C

Distortion

f = 1 kHz, RL =
Po = 50mW

5

32

V

5.5

W

0.20

%

Po = 0.5W

0.15

%

Po = 2W

0.14

%

Vs - 6V

Vp-p

al1

al1

Output Swing

RL =

Channel Separation

CBYPASS = 50 p.F, CIN = 0.1 p.F
f = 1 kHz, Output Referred
Vo = 4Vrms

-50

-70

dB

CSYPASS = 50 p.F, CIN = 0.1 p.F
f = 120 Hz, Output Referred
Vripple = 1 Vrms

-50

-60

dB

-60

dB

±13.5

V

PSRR Power Supply
Rejection Ratio
PSRR Negative Supply

Measured at DC, Input Referred

Common-Mode Range

Split Supplies ± 15V, Pin 1
Tied to Pin 11

Input Offset Voltage
Noise

Open Loop Gain

10

mV

Equivalent Input Noise
Rs = O,CIN = 0.1p.F
BW = 20 - 20kHz

2.5

p.V

CCIR-ARM

3.0

/LV

Output Noise Wideband
Rs = 0, CIN = 0.1 p.F, Av = 200

o.a

mV

70

dB

Rs = 5111, f = 1 kHz, RL =

al1

Input Bias Current
Input Impedance

Open Loop

DC Output Voltage

Vs = 22V

10

Slew Rate
Power Bandwidth

3 dB Bandwidth at 2.5W

Current Limit

100

nA

4

MI1

11

12

V

2

V/p.S

65

kHz

1.5

A

Not. 1: ±O.7V applies to audio applications; for extended range, see Application Hints.
Note 2: For operation at ambient temperature greater than 2S'C, the LM2878 must be derated based on a maximum ISO"C junction temperature using a thermal
resistance which depends upon device mounting techniques.

1·221

II

co
.....
~

:=;

Typical Performance Characteristics
Power Supply Rejection
Ratio (Referred to the
Output) vs Frequency

Device Dissipation vs
Ambient Temperature
10

10

I ALUMINUMTJfICKNESS=1JUiINCH I

9

TYPI~"'SSIS
zrC/W

-

::.1' ~~

1

!:

......

3x3INZIOC/W'\\

~

-

~

"

10

60
50

~

40

i'"
!!!
f

-

0.3 Vnn •• 1",'

-~

III

30

1'\
§

..fi

'"
~

10

60

14

lB

22

26

30

"
~

2.0
1.0

is

0.5

In
u

!

0.1

:

0.05

~

'\.

.

e 0.02

-

0:

;:l

~

lk

10k

~

'b

0.5
0.2
0.1

~~

'touT'1'0~ JP'
~o.sW~
~2.0W

0.05
0.02

1

0.01

lOOk

20

50 100200 500 lk 2k

100

1.0

..,.'"

'z~"

60

'""

40

w

~

~

0.1

"
"e....

>

~

0.01

Rt ·an

a;

!~.---o VOUT

2.m

TO.

1IlF

TUH17934-6

FIGURE 2. Operational Power Amplifier, Av = 1

1-224

External Components (Figure3)

1. R2, R5, R7, R10 Sets voltage gain Av = 1 + R2/R5 for
one channel and Av = 1 + R10/R7 for
the other channel.
2. R4, R8
Resistors set input impedance and supply bias current for the positive input.
Works with Co to stabilize output stage.
3.RO
4.C1
Improves power supply rejection (see
Typical Performance Characteristics).
5. C11

6.C4,C8

Input coupling capacitor. Pins 4 and 8
are at a DC potential of Vs/2. Low frequency pole set by:

7. C5, C7

Feedback capacitors. Ensure unity gain
at DC. Also low frequency pole at:

Stabilizes amplifier, may need to be larger depending on power supply filtering.

1
fL = 2'ITR5C5

Works with Ro to stabilize output stage.
Output coupling capacitor. Low frequency pole given by:

8. Co
9. C2, C10

1
fL = R'lTRLC2

Typical Applications (Continued)

lOOk

10k

2.m
lOOk

TO.'

2Dn
MOTOR

"F

IL.. _ _ _ _ .J

10k

2.m
RI
510

+

T

RIO
lOOk

TO.'

"F

CI
'O PF

TL/H17934-8

FIGURE 4. LM2878 Servo Amplifier in
Bridge Configuration

TL/H17934-7

FIGURE 3. Stereo Amplifier with Av = 200

1-225

II

Typical Applications (Continued)
Truth Table

lk

VIN

High

Low

<%V+
%V+ to%V+
>%V+

Off
Off
On

On
Off
Off

Zk

10

TLlH17934-9

FIGURE 5. Window Comparator Driving High, Low Lamps

1-226

~ Semiconductor
NatiOnal

Corporation

LM2879 Dual 8-Watt Audio Amplifier
General Description
The LM2679 is a monolithic dual power amplifier which offers high quality performance for stereo phonographs, tape
players, recorders, AM-FM stereo receivers, etc.
The LM2679 will deliver 6W/channel to an 6!l load. The
amplifier is designed to operate with a minimum of external
components and contains an internal bias regulator to bias
each amplifier. Device overload protection consists of both
internal current limit and thermal shutdown.

Features
•
•
•
•

Avo typical 90 dB
9W per channel (typical)
60 dB ripple rejection
70 dB channel separation

•
•
•
•

Self-centering biasing
4 M!l input impedance
Internal current limiting
Internal thermal protection

Applications
•
•
•
•
•
•
•

Multi-channel audio systems
Tape recorders and players
Movie projectors
Automotive systems
Stereo phonographs
Bridge output stages
AM-FM radio receivers

• Intercoms
• Servo amplifiers
• Instrument systems

Connection Diagram and Typical Application

Stereo Amplifier

Plastic Package

o

11
10
9
B
7
6

5

4
3
2

1

'lID'

Y·
OUTPUT 2
GND
INPUT 2
FEEDBACK 2
GND
FEEDBACK 1
INPUT 1
GND
OUTPUT 1
BIAS

-,
8Q

INPUTI-1I---......-<:.>-"'1
0.1,.f

'lID'
+

TLIH15291-1

c,

!2S0I'F

TDPYIEW
INPUT 2 ~

lOOk

t-='---.....-'O-.:.j

D.I"F

8Q

Order Number LM2879T
See NS Package Number TllA

'''''

TLlH/5291-2

FIGURE 1

1-227

II

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
3SV
Input Voltage (Note 1)
±0.7V
Operating Temperature (Note 2)
O'Cto + 70"C

Storage Temperature
Junction Temperature
Lead Temp. (Soldering, 10 seconds)
ESD rating to be determined.

Electrical Characteristics Vs = 28V, TTAB =
Parameter

2S·C, RL = 80, Ay = SO (34 dB), unless otherwise specified.

Conditions

Min

Total Supply Current
Operating Supply Voltage

Po=OW

Output Power/Channel
Distortion

f=1 kHz, THD=10%, TTAB= 2S·C

Output Swing
Channel Separation

mA
V

8

W

O.OS

CBVPASS=50 p.F, CIN=0.1 p.F
f = 120 Hz, Output Referred
VriDDle= 1 Vrms
Measured at DC, Input Referred
Split Supplies ± 1SV, Pin 1
Tied to Pin 11

1

%

Vs-6V

Vp-p

-so

-70

dB

-so

-60

dB

Equivalent Input Noise
Rs=O, CIN=0.1 p.F
BW=20 -20 kHz
CCIR-ARM
Output Noise Wideband
RS=O, CIN=0.1 p.F, Ay=200

Open Loop Gain

Units

6S

6

1=1 kHz,RL=80
Po= 1 W/Channel

Input Offset Voltage
Noise

Max

12

32

RL=80

PSRR Negative Supply
Common-Mode Range

Typ

6

CBVPASS=SO p.F, CIN=0.1 p.F
1= 1 kHz, Output Referred
Vo=4 Vrms

PSRR Positive Supply

-6S·Cto +1S0'C
1S0'C
260'C

-60

dB

±13.S

V

10

mV

2.S
3.0
0.8

p.V
p.V
mV

Rs=51O, f=1 kHz, RL =80

70

dB

Input Bias Current
Input Impedance

Open Loop

100
4

nA
MO

DC Output Voltage

Vs=28V

Slew Rate
Power Bandwidth

14

V

2
65

V/p.s
kHz

3 dB Bandwidth at 2.SW
Current Limit
1.S
A
Note 1: The Input voltage renge is normally limited to ±O.7V with respect to pin 1. This range may be extended by shorting pin 1 to the positive supply.

Note 2: For operation at ambient temperature greater than 2S"C, the LM2879 must be derated based on a maximum 150"C junction temperature. Thermal
resistance, junction to case, is 3"C/W. Thermal resistance, case to ambient, is 4rrC/W.

Typical Performance Characteristics

.

!:
z

i;;
lrl

I.

Device Dissipation vs
Ambient Temperature
22
INFINITE HEAT SINK
20
18
4·C/W
16
I'.. HEAT SINK
14
12
'""'"
10
8 10°C/W
HEAT SINK
r6
I I
4
2
0 10 20 30 40 50 60 70 80
TA-AMBIENT TEMPERATURE ('CI

-

Power Dissipation vs
Power Output

Open Loop Gain vs
Frequency
100

Iys

0

11

ZZy

10

RLoan

....

80

U
z'"

&0

fia1
!:z

40

is!
w ..

za

!!ii

~=

a
100

Ik

10k

tOOk

FREQUENCY IHII

1M

9

8

- 28.!,
I,l; ....

7

6
5
4
3

2
1
0

3:J"0

26V
24V

~

Ir'

",r..r ~2V

~~~20V
I-' 4V

~\I
THD

+
J

1=1 kHz
RL=8lI

Av=5O

0 123456 7 8 9 10
POWER DUTFUT (W/CHANNElI
TUH15291-3

1-228

,-----------------------------------------------------------------------------, r
is:
I\)
Typical Performance Characteristics (Continued)
CD
Supply Current vs Output
Power
700

",,,",0

~m
"-z 400
"-z

"'

.

w'"
~i

100

o

~~

t'

,

SOD

":z: 300
"':z:
:!;~ 200

80

...~ffi
... =
.. tt;
",

",w

ia:

Av=50, Vs=28V, RL=BO.I=I kHz

I

2

4
6
OUTPUT POWER (WI CHANNEl)

3D

~
~

~

.~
_

0.5

10

~ 0.2
~ 0.1
~ 0.05

~

0.D2
0.01

;::

'"

...~~

I
~~
~

porj~fI

'"

60

.

50

~

~CIN =L.do~¥

III I II

5

40

100
Ik
10k
FREQUENCY (Hz)

lOOk

2.0
1.0
0.5

10

~

0.2

,~

~ 0.1

~

"-

~ 0.05

§ 0.02

,

""-'

~

~

~

L

'"z

iii
'"
e:
'"'"

""

0-

Av,51

20 50 100 200 SOD Ik 2k 5k 10k 20k

IS

./

10

fI"

~

,/
10

15

20
25
V SUPPLY (V)

3D

35

Power Output/Channel vs
Supply Voltage

10

10

RL=BIl

9 THO=IO%

,I

1.0

lOOk

1=1 kHz
RL=80

FREQUENCY (Hz)

Total Harmonic Distortion
V5 Power Output

0.1

Ik
10k
FREQUENCY (Hz)

20

o

0.01

20 50 100 200 SOD Ik 2k 5k 10k 20k
FREOUENCY (Hz)

100

~

Output Swing vs Vs
25

Av=20~

l'

CBYPASS =50 ~F
Vee=28V
Av=50
Vour=4 VIm.
RL=811

ill

z
z

RL-80
Po=0.5W
Vee =2BV

z

0

~I

!;i

Total Harmonic Distortion
vs Frequency
10.0
~ 5.0

~ ~r-r

70

0

C VALUES ARE RIPPLE FILTER

10

Av=50
RL=BII
Vee=2r V

L

z

II
V~220V. Av=50

20

Total Harmonic Distortion
vs Frequency
10
5

:s

I ~F

o

3

1iJ

.....
CD

~lrFI
Tl'm..""

;;;

H

fil3: 50
~:= 40

/
'I
o

BO

JooIJ'
I I
60 20 ~F

70

m

:s

fI"

~~
w'" 600

"'w
.....

Supply Rejection vs
Frequency

..,t'

800

!~

Channel Separation
(Referred to the Output)
Frequency

o ....

10

I'

"

D

i.II

6 8 10 12 14 16 IB 20 22 24 26 28

POWER OUT (W/CHANNEL)

SUPPLY VOLTAGE (V)
TL/H/5291-4

1-229

LM2879

m

,Q

C

~'

CD

::J

W

::::T
CD

•

,

,

•

,

5k

,

11
' 0 V+

3

at)'
c

iii'

...

CCt

I»

3

30k
~

~

~

5k

GND03

5
-FEEDBACK 1

6
GND

4 01
+INPUT 1

08

+INPUT 2

7
-FEEDBACK 2
TL/H/5291-5

Typical Applications
Two·Phase Motor Drive

Ne

RI
27k

R3
27k
R4

2.7

2.7

TO.I~F

TO.I~F

2700

TL/H/5291-6

12W Bridge Amplifier

----II

O.IF

SIGNAL
INPUT

L-_ _-(;>-_ _ _ _ _ _ _ _ _ _--.

.-

1M

II

1M

10k
TLlH/5291-7

1·231

Typical Applications (Continued)
Simple Stereo Amplifier with Bass Boost
0.02,."

llIOk

r

11

r

2k

o()o

y.

+

-,

2.7

~D"l'F

5 ,."

':"

INPUTI-1
CF

llIOk

0.1,."

I

+

INPUT 2 -1

r

25DPF

lOOk

CF

0.1,."

8

L

211

r

I
I
I

+

lOOk

2.7

1lI0II

5pF

T

':"

0.1 "F

TLlH/5291-B

Power Op Amp (Using Split Supplies)
lOOk

y.

10k

INPUT-'"W\,...-4~:.j

2.7
-V0"l'F

v-

TO"PF
TLlH/5291-9

1·232

Typical Applications

(Continued)

Stereo Phonograph Amplifier with Bass Tone Control

0.33 pi'

1k

51k

510k
...."""",..,..-....- -... OC100k

STEREO
CERAMIC
CARTRIDGE

0.33 pi'
51k
1k

1'loopl'
+

TL/H/5291-10

II

Frequency Response of
Bass Tone Control
.,

e...

65

I I

:!!.

55

8

~

1=
...

co

z

45

35

g
~

15

g

25

rt-...

I I I
~~O~~UM_ ;--+-

cri~::O~ ~ESPONSE- c-rFLAT

~

,

t....o

4AX\MJM- -c-~ICUT
. 'ES~ONfE-

-I-

15

20 50 100 200 500 1k 2k

5k 10k 20k

FREQUENCY (Hz)
TL/H/5291-11

1-233

~
CO)

co
o
:E
...I

r----------------------------------------------------------------------------,
_

National

Semiconductor
Corporation

LMC835 Digital Controlled Graphic Equalizer
General Description

Features

The LMC835 is a monolithic, digitally-controlled graphic
equalizer CMOS LSI for Hi-Fi audio. The LMC835 consists
of a Logic section and a Signal Path section made of analog
switches and thin-film silicon-chromium resistor networks.
The LMC835 is used with external resonator circuits to
make a stereo equalizer with seven bands, ± 12 dB or ± 6
dB gain range and 25 steps each. Only three digital inputs
are needed to control the equalization. The LMC835 makes
it easy to build a p.P-controlied equalizer.
The signal path is designed for very low noise and distortion, resulting in very high performance, compatible with
PCM audio.

•
•
•
•
•
•

No volume controls required
Three-wire interface
14 bands, 25 steps each
±12 dB or ±6 dB gain ranges
Low noise and distortion
TTL, CMOS logic compatible

Applications
•
•
•
•
•

Hi-Fi equalizer
Receiver
Car stereo
Musical instrument
Tape equalization

• Mixer
• Volume controller

Connection Diagram
Dual·ln·Line Package

Order Number LMC835N
See NS Package N28B

\"J

f!.
F!-

A, ••

....l

AIN2
A'N3

...!
.2

AIM4

~

~

AIN7

...l!
...!
.2
-!

f!.

Lca

f!.

LC9

LCl
LC2
LC3
LC4

LC7

...!
2!!
..!:!

LC5
LC6

~

~

A,GND
A'NS
A'N6

LC1D

f!.
f!!.
f!.

LC12

t1!-

LC14

LCll

LC13

Vss

~

r1L

VDD

D,GND

~

~

DATA

CLOCK

~

~

STRDBE
TL/H/6753-1

Top View

1-234

_ _ 14
CLOCK

to

~
lEVEL
SHIFT
1

0'

4·TO-16 DECODER

n

~

C

iii'

16

ce

DATA
17

- . . 0 V+
12

iiJ
3

~V-

15
STROBE
13
O.GNO

'--

r-L-

rAIN1

RdC
7.3k
3

A2

A,., 00-

N

2
AI"Oo-

01

RdC
3.4k

qr-"
rt"'"

II

DR

Sb

RbC
3.4k
25

AIN7

RbO
7.3k
26
A"6~

Rb2
7.3k

A6

I

II I, U
:I 'I
" 1/ 'I
II 'I :: I,
II I I. " 'I
III' .:I H
II :,
II 'I II
II

:1:6 dB

2B
A.GND

A4,' A5

A7

I

1
AIN1

Rab
3.4k

A3

"

Rd2
7.3k

""

I

Rbb
3.4k

6-++..........~"C>--A.""'"'"

L

~

~

I
,

II

,I

,

II
II

"

,

II

"

'I

I,I,

,I

"

It I'

~~ ~
U
II h:: It:
II' ,I II ,I
II I
" 'I U I' U'
II I' 'I II II:
"I' ::I II: IIIt II'
"" II I,I ' "II ,'III , 'II
II II II II
II,'
I'

Bl

II

I I , " II ,I II
. 11
, II " " II
II I II , , II

R5b 55k
!o'O.......J\IVY-6R4b25k
R3b 16k

I, :.

II B2

"
"

,B3,

,I II
""

" "II
" ,I II

B4

'I I
',II

I,'
,I ,I

. I I "I Itr~~1rr~~~
II

R2b11k

~~_ ~

I

II

II

"

II

II

11 ,1

27
A,.5
lC2

lCl

07
lC3

OB
lC4

09
lC5

010 011
lC6
lC7

024
lca

023 022 021 020 019 018
lC9
lCl0 lC11 lC12 lC13 lC14
TUH/6753-2

S&9011111

iii

Absolute Maximum Ratings

Operating Ratings

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
18V
Supply Voltage, Voo-Vss
Allowable Input Voltage (Note 1)
Vss-0.3V
toVoo+0.3V
Storage Temperature, Tstg
- 60'C to + 150'C
Lead Temperature (Soldering, 10 see), TL
+ 260'C

5Vto 16V
Supply Voltage, Voo-Vss
Digital Ground (Pin 13)
Vssto Voo
Digital Input (Pins 14, 15, 16)
Vssto Voo
Analog Input (Pins 1, 2, 3, 4, 25, 26, 27)
(Note 1)
VsstoVoo
Operating Temperature, Topr
-40'C to + 85'C

Electrical Characteristics (Note 2) Voo=7.5V, Vss = -7.5V, A.GND=OV
LOGIC SECTION
Symbol

Parameter

Test Conditions

Typ

Tested
Limit
(Note 3)

Design
Limit
(Note 4)

Unit
(Limit)

0.Q1
0.01
1.3
0.9

0.5
0.5
5
5

0.5
0.5
5
5

mA(Max)
mA(Max)
mA(Max)
mA(Max)

IOOL
ISSL
IOOH
ISSH

Supply Current

Pins 14, 15, 16 are OV
Pins 14,15,16 are OV
Pins 14,15,16 are 5V
Pins 14,15,16 are 5V

VIH

High·Level Input Voltage

@Pins14, 15, 16

1.8

2.3

2.5

V (Min)

VIL

Low·Levellnput Voltage

@Pins 14,15,16

0.9

0.6

0.4

V (Max)

fo

Clock Frequency

@Pin 14

2000

500

500

kHz (Max)

twiS'fili

Width of STS Input

See Figure 1

0.25

1

1

,...s(Min)

tsetup

Data Setup Time

See Figure 1

0.25

1

1

,...s(Min)

thold

Data Hold Time

See Figure 1

0.25

1

1

,...s(Min)

Ie.

Delay from Rising Edge of CLOCK
toSTS

See Figure 1

0.25

1

1

,...s(Min)

liN

Input Current

@Pins 14, 15, 16 OV-.....-'V\/Ir------------------oQVOUT.

r--,I

~------=O=A=~~

WORD
GENERATOR

I
I

I
.J

O.GNO

L. __

lOOp

lOOk

>-..........M,-------------------oQVOUT.

+15V

-15V
TLlH/6753-5

FIGURE 3. Test Circuit for AC Measurement
Vl2J

Vl22

Vl21

Vl2D

V119

V118

+ 7.5V

DATA r - - ,
...----=::::"'I
I
WORD
GENERATOR
O.GNO

II

I
I

I

L.. __ .J
LMCB35

,
I

I

II/V I

·r
I

I

TL/H/6753-6

FIGURE 4. Test Circuit for Leakage Current Measurement

1-239

U) r-------------------------------------------------------------------------------~
CO)

CD
(J

Test Circuits (Continued)

:E

r------,

...I

IUN

o-.....-=-....-I~ >~t--I-o VLOUT

I
I
I

lk

I

lOOp

L____ ..!...J
VLOUT = IUN )( 107

Tl/H/6753-7

FIGURE 5. I to V Converter

v·
CLOCK

10

CLOCK

MM74HCOO
10
Q 9

11 ClK

DATA
MM74HCOO

MM74HC74
Q 5

Q8

12 D

RC 15

2 CLK

INH 15

MM74HC163

MM74HC163
lOAD 9

PR Q 5

CLKt-=2~1--+3~CLK

MM74HC74

Q~6~~---osmOBE

2 D

1 lOAD

v.

D7 D6 D5 D4 D3 D2 Dl OD
Tl/H/6753-8

FIGURE 6. Simple Word Generator

Typical Performance Characteristics

2.0
!A=25°C _
1.8 CE=DATA=STD=5V
C 1.6 D.GND=A.GNO=OV
E. 1.4
1.2

i...

1.0
0.8
~
t 0.6
0.4
0.2

.

1-1-

V

Input CapaCitance vs
Input Voltage

Supply Current vs
Temperature

Supply Current vs
Supply Voltage

~

J
IDO

I
~S

i.

.
...E
a:

.-

,.~.

1 2 3 4 5 6 7 8 9 10
SUPPLY VOLTAGE (:t VI

2.0
1.8
1.6
1.4
1.2

10

~: ;:i:~ STa a 5V
D.GNO=A.GNO-OV

1.0
0.8
0.6
0.4

laa

--

IsS

--

0.2

o

-50 -25

PINS 14. 15. 16

I

9 VS. :t7.5V. TA=250 C[

I-

"""
1

0 25 50 75 100 125
TEMPERATURE (OCI

o

~~

F--

J-l.
1--

-

r-

f-

. I-~

O.GND-A.GNO-OV
f-l MHz

.~-

I-

·f-

·-f-f-

- f-

F
. -1---

I--- .•

t-.

. 1--1---

D 1 2 3 4 5 6 7 8 9 10
INPUT VOLTAGE (VI
Tl/H/6753-9

1·240

Typical Performance Characteristics (Continued)

10

10r--~-~-r-~,

Vs= :t.7.5V

TA=25'C
: 12 dB RANGE FLAT -- I-1=1 kHz, THO1"1. - -

..

f-+-+---+--I---+- -

- l - t-

25 50 75 100 125
TEMPERATURE ('C)

0_05 ~RF~~E
o=3Vrm.

~O'Ollllii
E
0.805
is
0.002
0.001

'1:m~VF°:j:-~lv~r~m::s~!IW:r.Htt~

...

~
i!i

1110
lK
1011
FREQUENCY 1Hz)

0.1

~;di ~::D~A -

i!z

0.02

~
co

0.005

0.002 1-+-'1+l-t!'H~

10

1110

10K
lK
FREQUENCY (Hz)

lOOK

1

....
z

Ro-6IOII
=n'lllNGECUT

flAl

-It'
-TO

-1
-3

..

-5

-'"

-9
-11
-1
10

10

100
lK
10K
FREQUENCY (Hz)

lOOK

Gain vs Frequency
@ ± 6 dB Range (Cut)

...

:1:'"

!z

'~T

-150

n •

-1
-2

-lU

-IDa

1=

F

-~5',Ii

'D'.i

'" I-

-4

-UI.

-$Dill

-5

-5$ ••

'"

-6

-.0.1

10

E

100
lK
10K
FREQUENCY (Hz)

lK
10K
1110
FREQUENCY (Hz)

lOOK

Gain vs Temperature

~::~~~v

_

f--

OdB _
1

:12 dB RANGE

-is'.i
-io'.i

C -3
co

lOOK

IlAJfaEtUT

10

9

Ra_IIOU

+1"
III

-13

10

·s·:I: 'S'I,l,_25"t

.,..~'n.T,.H·t

100
lK
10K
FREQUENCY (Hz)

'&1 .. ::15WT._ZS'C

C
co -7

~

10

Gain vs Frequency
@ ± 12 dB Range (Cut)
3

....

Gain vs Frequency
@ ±6 dB Range (Boost)
110·
...•
:tIIII!WIG£'OGST

0.2 0.5
OUTPUT VOLTAGE (Yrm.)

Gain vs Frequency
@ ± 12 dB Range (Boost)

~

I Inl

10

;:: 0.005
0.01

f=

rf=C
0.001
0.1 0.2
0.5 1
OUTPUT VOLTAGE (Vrm.)

~

e!1:l ~~m~i~~=111

z

I~ ~

0.002

___--.-......

0.02 1--1--HH-+_-4--l-I-II-J.l.Il

15 r;;::-::IT.'I;~llllICll
13

I II
-

0.1 . - -_____-

0.001 Vo=-1Vrms

lOOK

=
-

--,,":1

~ 0.01

Distortion vs Output Voltage
@ ± 12 dB Range

0.002

25'C~

--FLAT

o 25 50 75 100 125
TEMPERATURE ('C)

i!i

0.01

Distortion vs Output Voltage
@ ±6dBRange
0.05

z 0.9&
0.95
-50 -25

~

0.02 H"t'T1"t111t"ffm,....,.;-,J.1IIl-

~ !IIIII~

Vo=3Vrms

-I--

0.05

~ 0.005

L.J,.J..LWLII...J..J..WLL.......................wJJll

10

0.98

0.05

~ 0.02 --_:t-ltt2tttdm-B-t1~IIl--f+
z

::i

0.1.--""",,,""=,,,",,,,=,,,,,,,=,,,,,,,

Vs= :7_5V, TA=25'C

co

1
0.99

Distortion vs Frequency
@ ±6dBRange

Distortion vs Frequency
@ ± 12 dB Range
0_1

~

~ 0.97

t

o 1 2 3 4 5 6 7 8 9 10
SUPPlY VOLTAGE (: V)

--

1.01

~

1-+--+--1-+--+--- -

~

1

1.05
... 1.04
3 1.03
~ 1.02

'"~

-

V

o

Nominal Resistor
vs Temperature

Maximum Output Voltage
vs Temperature

Maximum Output Voltage
vs Supply Voltage

1

o
lOOK

5 dB
4dB
3da
ZdB
1 dB
FLAT

-50 -25 0 25 50 75 100125
TEMPERATURE ('C)
TLIH16753-10

1-241

II

U)
C")

l3

r---------------------------------------------------------------------------------,
Typical Applications

:E
....I

27k
6.Sk

,>""'4I"-""''''''"TI

t---------------.. .o

lOOk
lOOp

~.---~

+ 7.5V

lOOp

You,"

+ 15VOCIN

27k

+

p-.p-.r-.p-~r-.r-

• 47"

.• -'

11111111111111

: ZI : : Z2 :: Z3 :: Z4 :: Z5 :

l 26:: Z7 :

WORD
GENERATOR

I
I

D.GND
I
L. __ .J

LMCS35

11111111111111

I 21 II Z2 II Z3 II Z4 II Z5 .. Z6 II Z7 I
47" 1
II
II
II
II
II
II
I

L_JL_JL_JL_JL_JL_JL_J

27k
~.....- -... - 15VoCI.

27k
VIN.o--IItIvY_--:I

,-JII-\I\r-<~;'

>,.....-""',."..,-11----------------0

VOUT.

10.

+15V

-15V
TLlH/6753-11

FIGURE 7. Stereo 7·Band Equalizer

TABLE I: Tuned Circuit Elements
PIN "LC"

Z1

fo (Hz)

Z1
22
23
24
25
26
27

63
160
400
lk
2.5k
6.3k
16k

Co (F)

CL(F)

RL(O)

Ro (!l)

'''

0.1,...
0.033,...
0.015,...
0.0068,.,.
0.0033,.,.
0.0015,.,.
680p

lOOk
lOOk
lOOk
82k
82k
62k
47k

680
680
680
680
680
680
680

0.47,...
0.15,...
0.068,.,.
0.022,.,.
0.01,.,.
0.0047,.,.

PIN 2. 3 OR 26

r -t R;;.K-1- - ,
Ico~
I

QO = 3.5, Q'2dB= 1.05

I

I~

I
L~

I

I
I

Lo=CL RL Ro
1

fO=2"'~

OO=~CoL~02
RoOo
012dB=Ro+1590

_ _ _ _ .JI

(15901l=55k#16k#11k#Sk/,13 kill
TLlH/6753-12

FIGURE 8. Tuned Circuit for Stereo
7-Band Equalizer (Figure 7)

1-242

.-----------------------------------------------------------------------------'r
3:
Typical Applications (Continued)
oco
Performance Characteristics (Circuit of Figure 7)
LMC835 Gain vs Frequency
LMC835 Gain vs Frequency
@ ± 12 dB Range
@ ± 12 dB Range
(All Boost or Cut)
(1 kHz Boost or Cut)

Co)
(II

Ert.EI

16 ~
12

16
12
0;

4

i'
::;:

0;

4

0

i"

0

~-4

"'-4

-8

-8

-12

-12

-16
10

100

lK

10K

-16

lOOK

10

100

FREOUENCY (Hz)

lK

10K

lOOK

FREQUENCY (Hz)

LMC835 Gain vs Frequency
@ ±6dB Range
(All Boost or Cut)

LMC835 Gain vs Frequency
@ ±6dBRange
(1 kHz Boost or Cut)

8~~.

;-2-'
-4fJ1t1
100

lK

10K

Ii

-4

-6~mI
-8 I:::t±MI
10

~

z

::;:
"'-2

-6

-8

lOOK

10

100

FREQUENCY (Hz)

lK

10K

lOOK

FREQUENCY (Hz)
TLlH/6753-13

+15V

6.8k
27k

....,.,,.,.-------------o You,

;>-cl.....

470

27k

':"

II

r-.r-"Ir-"r-"r-.
II
II
I
I
II
II

+

IZ811Z911Z10 1l Z11IIZ12 1
1111111111

10k

. - - - - -... +7.5V

.---+ DATA
28
A.GNO

27
AIN5

26
AIN6

STROBE

25
AINl

24
LC8

23
22
21
20
19
18
LC9 LC10 LC11 LC12 LC13 LC14

17

Voo

LMC835
LCI

LC2

5

LC3

LC4

6

LC5

8

LC6
10

LC7
11

Vss
12
CLOCK
....- -... D.GND
1....._ _ _....... -7.5V

..

..-..

11111111111111
I ZI I I Z2 II Z3 II Z4 II Z5 II Z6 I I Z7 I
11111111111111
~-

-~.-~.-

FIGURE 9. 12-Band Equalizer
1·243

-~.-~

TLlH/6753-14

Typical Applications

(Continued)

TABLE II. Tuned Circuit Elements
PIN

00=4.7, 012dB= 1.4

Z1
Z2
Z3
Z4
Z5
Z6
Z7
Z8
Z9
Z10
Z11
Z12

fo(Hz)

Co (F)

CL(F)

RL(n)

Ro(n)

16
31.5
63
125
250
500
1k
2k
4k
8k
16k
32k

3.3",
15",
1",
0.39",
0.22",
0.1",
0.047",
0.022",
0.01",
0.0068",
0.0033",
0.0015",

0.47",
0.22",
0.1",
0.068",
0.033",
0.015",
0.01",
0.0047",
0.0022",
0.001",
680p
470p

100k
110k
100k
91k
82k
100k
82k
91k
110k
82k
62k
68k

680
680
680
680
680
680
680
680
680
680
680
510

"LC"

--,I

PIN 26

r
Ico
I
IC'

I
I

Rl

L~

Lo~CL

RL Ro
1
fo~ 21Tv'LOCO

I
I

~

Qo~ CoRo2

I
I
____ J

RoQo

Q'2dB~ Ro+ 1590

(15901!=55kt16ktllkt8kn kn)
TL/H/6753-15

FIGURE 10. Tuned Circuit for
12-Band Equalizer (Figure 9)

Performance Characteristics (Circuit of Figure 9)
12 Band Equalizer Application
LMC835 Gain vs Frequency
@ ±6 dB Range
(All Boost or Cut)

LMC835 12 Band E.O. Application
Gain vs Frequency
@ ± 12 dB Range
(1 kHz Boost or Cut)
12

~

~

z

0

'"

-2

:;;:

4

z
;;;:

'" -4

-4

-8

-6

-12
-16

-8

10
10

100

lK

10K

100

lOOK

lK

10K

lOOK

FREQUENCY (Hz)

FREQUENCY (Hz)

12 Band Equalizer Application
LMC835 Gain vs Frequency
@ ± 12 dB Range
(All Boost or Cut)

LMC835 12 Band E.O. Application
Gain vs Frequency
@ ±6dB Range
(1 kHz Boost or Cut)

16~1I
12~

8rTTTTT1mr1""TT11nm-rm"",...TT1T111l1

.

!

z
;;;:

'"

:e
z

~-2

-4
-8

-4 • •

-12

-6

-16

-8
10

100

lK

10K

lOOK

10

FREQUENCY (Hz)

100

lK

10K

lOOK

FREQUENCY (Hz)
TLlH/6753-16

1-244

Typical Applications

(Continued)
PIN "LC"

PIN 2. J OR 26

La

r-t ~K-4--,
Ico~

I

I

I

IC'

I

I
I
I

I
I
I

Rl

v+

= CLo RLo RO

1

Fo = 21TWo
00

= JCoRQ2

012 dB =

ROaD
Ro + IS'C

l..I ____ J

(15901l=55k#16k#llk#Bk#J kill
TL/H/6753-25

v"
I.
VINS

o--1l-+~~-~"':

> .....--w__- ' - I I - - - - - - - - - - O V O U T B
lOOk

r-----+ v" BV TO 15V

v"

DATA
STROBE

V+o-_.....~'"""".....
2

100

,.F

CLOCK
O.GND

lOOk

>~~"VI"", ~----------O VOUlA

TLlH/6753-17

The

v+
"2
output is used to bias the gyrators

FIGURE 11. Single Supply Stereo Equalizer

1-245

II

It)
C")

~

Typical Applications

(Continued)

:E

...I

VOUTA

+14dB - -17dB
VIN2

EACH INPUT
SELECTABLE.
GAIN IS OFF.
-17 dB TO +14 dB

VOU'D

25
16
15
14
13

DATA
STROBE
CLOCK
O. GNO

TL/H/6753-18

TL/H/6753-19

FIGURE 12. Stereo 7-lnput/1-0utput Mixers
(THO is not as low as equalizer circuit)

FIGURE 13. Stereo Volume Control, Very Low THO

+5V

lOOk

+5V

;J;

IOn

LMC835
DATA

....- - - - t STR08E
O.GNO

TLlH/6753-20

FIGURE 14. LMC835-COP404L CPU Interface

1-246

Typical Applications

ris:

oCD

(Continued)

Sample Subroutine Program for Figure 14, LMC835-COP404L CPU Interface

c.:l
U1

HEX
CODE

LABEL

MNEMONICS

3F

LMC835:

LBI

05

SEND

LD

;RAMDATA TO A

SC

; SET CARRY

335F

OGI

;SET PORT G= 1111, OPEN THE AND GATES

4F

XAS

; SWAP A AND SIO, CLOCK START

05

LD

;RAMDATA TO A, MAKE SURE A = DATA
; SWAP A AND RAMDATA, RAMADDRESS=RAMADDRESS-1

22

COMMENTS
3F

;POINT TO RAMADDRESS 3F

07

XDS

05

LD

;RAMDATA TO A

4F

XAS

; SWAP A AND SIO

05

LD

;RAMDATA TO A, MAKE SURE A=NEWDATA

07

XDS

; SWAP A AND RAMDATA, RAMADDRESS=RAMADDRESS-1

32

RC

;RESET CARRY

4F

XAS

; SWAP A AND SIO, CLOCK STOP

335D

OGJ

13

;SET PORT G=llOl, MAKE STROBE LOW

335B

OGI

11

;SET PORT G=1011, MAKE STROBE HIGH, CLOSE THE

4E

CBA

GATES
43

AISC

48

RET

80

JP

;BDTOA
3

;RAMADDRESS<3C THEN RETURN

SEND

RAM
ADDRESS

COMMENTS

3C

DATA

;GAIN DATA D4-D7

3D

DATA

;GAIN DATA DO-D3

3E

DATA

;BAND DATA D4-D7

3F

DATA

;BAND DATA DO-D3

Application Hints
SWITCHING NOISE

SIMPLE WORD GENERATOR (Figure 6)

The LMC835 uses CMOS analog switches that have small
leakages (less than 50 nA). When a band is selected for flat
gain, all the switches in that band are open and the resonator circuit is not connected to the LMC835 resistor network.
It is only in the flat mode that the small leakage currents can
cause problems. The input to the resonator circuit is usually
a capacitor and the leakage currents will slowly charge up
this capacitor to a large voltage if there is no resistive path
to limit it. When the band is set to any value other than flat,
the charge on the capacitor will be discharged by the resistor network and there will be a transient at the output. To
limit the size of this transient, RLEAK is necessary.

Circuit operation revolves around an MM74HC165 parallelin/serial-out shift register. Data bits DO through 07 are applied to the parallel of the MM74HC165 from 8 toggle
switches. The bits are shifted out to the DATA input of the
LMC835 in sync with the clock. When all data bits have
been loaded, CLOCK is inhibited and a STROBE pulse is
generated: this sequence is initiated by a START pulse.
LMC835-COP404L CPU INTERFACE (Refer to Figure 14)
The diagram shows AND gates between the COP and the
LMC835. These permit G2 to inhibit the CLOCK and DATA
lines (SK and SO) during a STROBE (Gl) pulse. This function may also be implemented in software. As shown in Figure 2, the data groups are shifted in DO first. Data is loaded
on positive clock edges.

HOW TO AVOID SWITCHING NOISE DUE TO LEAKAGE
CURRENT (Refer to Figures 7 and 8)
To avoid switching noise due to leakage currents when
changing the gain, it is recommended to put RLEAK = 100
kO between Pin 3 and Pin 5-11 each, Pin 26 and Pin 1224 each. The resistor limits the voltage that the capacitor
can charge to, with minimal effects on the equalization. The
frequency response change due to RLEAK are shown in Figure 15. The gain error is only 0.2 dB and Q error is only 5%
at 12 dB boost or cut.

POWER SUPPLIES
These applications show LM317/337 regulators for the
± 7.5V supplies for the LMC835. Since the latter draws only
5 p.A max., 1k series dropping resistors from the ± 15V op
amp supply and a pair of 7.5V zeners and bypass caps may
also suffice.

1-247

II

U)
CI)

co

o

r---------------------------------------------------------------------------------,
Application Hints (Continued)

:!!

MODEL

..J

RESULT

V,N

> ....-OVOUT

,

12 dB

~-'L-----,,--

_ _....~_

11.& dB ~-...,r-I----;h_~o--

I
I

odB
10"'0

TL/H/6753-21

TL/H/6753-22

FIGURE 15. Effect of RLEAK

REDUCING EXTERNAL COMPONENTS
The typical application shown in Figure 7 is switching noise
free. The DC·coupled circuit in Figure 16 is also switching
noise free, except at 12 dB/6 dB switch turn ON/OFF. This
switching noise is caused by the Ibias and Voffsel of the op

amps. Selecting a low Ibias and Voffsel op amp can minimize
the switching noise due to the 12 dB/6 dB switch. The DC·
coupled application can also eliminate the RF= lOOk resistors with only a 0.5 dB gain error at 12 dB boost or cut.
DC COUPLING

ACCOUPLING
V,N
V,N
lOOk

LMC&35

TL/H/6753-24
TL/H/6753-23

FIGURE 16. Reducing External Components

1·248

rNatiOnal

~ Semiconductor

ADVANCED INFORMATION

s:

(')

......

CD
CD
N

Corporation

......
r-

s:
(')

LMC1992/LMC1993 Computer Controlled
Tone and Volume Circuits

......
CD
CD
Co)

General Description

Features

The LMC1992/3 is a tone (bass/treble), volume and fader
(front/rear) circuit for stereo hi fi audio. Control is accomplished by means of a three wire microprocessor interface.
Its applications include car radio, TV and remote audio systems.

II 28-pin package

The LMC1992/3 provides stereo source selection switching, volume, fade and tone controls with very few external
components. On-chip op amps enable these functions to be
accomplished in a 2B-pin package with minimal external
components. In addition, the LMC1993 provides a loudness
function with one less input source per channel.

II TTL, CMOS logic compatible

The LMC1992/3 was designed with most capacitors less
than 0.1 /LF to allow use of chip capacitors. The signal path
is comprised of analog switches and thin-film silicon-chromium resistor networks for very low noise and distortion. Additional tone control can be included by use of LMCB43/835
digitally-controlled stereo 3/7-band graphic equalizer circuits.

II Low noise and distortion
II Serial programmable: standard MICROWIRETM

interface
II Protection address (similar to DS B906)
II Inputs DC coupled
II Full boost and cut treble and bass tone control
II 40 Volume levels including mute
II Front/back fade control
II 20 Fader levels

.. All attenuators 2 dB/step
II Single supply operation
II Wide supply voltage range
II Minimal external components
.. Provisions for connection to DNR® and/or equalizer
II LMC1992 has 4 stereo source selection without loudness, LMC1993 has 3 with loudness
II Provisions for more stereo inputs
II Powers up with flat tone and min volume/fader

Equivalent Schematic (one channel shown) [LMC1993-loudness device]
0.1 p.F 0.0047 p.F

0.0047 p.F

330 pF

0.1 p.F

3.0k

~~~-{]-~C~
LOUDNESS
INPUT 1

V'ee

INPUT 2
INPUT 3 n---lH>+-<>---"
T

.......

FRONT
OUTPUT

Vee
DATA
CLOCK
ENABLE

LOGIC
CONTROL
CIRCUITRY

VOLUME
REAR
OUTPUT

Serial Control

Ports (MICROWIRETM)

TLiH/904B-l

FIGURE 1

1-249

II

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage +Vs Referred to -Vs
Ground
Maximum Operational Supply Voltage
Logical Input Voltage

TMIN < TA < TMAX
-40·Cto +85·C

Operating Temperature Range
LMC1992, LMC1993

-60·Cto + 150·C
125·C

Storage Temperature Range
Maximum Junction Temperature

+18V
+15V

300·C

Lead Temperature (Soldering. 10 sec.)
ESO rating is to be determined.

+Vs, -Vs

Electrical Characteristics v+ = 8V. T A = + 25·C unless otherwise noted
Parameter

Conditions
Volume = 0 dB, Faders = 0 dB
unless specified

Supply Current

LMC1992
Typ

Tested
Limit

Design
Limit

Units

15

rnA

Reference Voltage

Pin 27

4.7

Vdc

Maximum Input Signal

Clipping Level (1 % THO)

2.3

Vrms

Maximum Output Signal

Clipping Level (1 % THO)

1.0

Vrms

THO 1 kHz

0.3 Vrms Input Volume

%

0.03

%

7.0

,..Vrms

Min Noise

= 0 dB
= -20 dB
CCIR. Flat Tone. Volume = 0 dB
CCIR. Flat Tone. Volume = -80 dB

0.2

0.3 Vrms Input Volume

4.5

,..Vrms

Bass Range

Boost and Cut @ 50 Hz

12

±dB

Treble Range

Boost and Cut @ 15 kHz

12

±dB

Volume Range

Maximum Attenuation

80

dB

Fader Range

Maximum Attenuation

40

dB

Tracking

Attenuator Tracking

0.5

dB

TH01 kHz
Max Noise

Freq Response

High Frequency - 1 dB point

450

kHz

Separation

Channel Separation 1 kHz

80

dB

Isolation

Input-Input Isolation

90

dB

PSRR

100 Hz. 200 mVrms

40

Fclk

Maximum Clock Frequency

1.0

1-250

dB
0.50

MHz

r-

s::
o

Typical Performance Characteristics

.....

Bass Max Treble Max I Bass Min Treble Min
20

20

16

16

12

12

4
dB

Bass Max Treble Flat I Bass Min Treble Flat

~

0

-4

I---

-8
-12

..'"

8

-

4

r-

s::

o
.....

-

-4

"/

-8

•

Co)

~

- ....

'Z

"/

I-

-12

-16

CO
CO

"'"

0

dB

o:z;

-16

-20

-20
10

lK

100

10K

10

lK

100

TL/H/904B-3

TLiH/904B-2

Bass Min Treble Max I Bass Max Treble Min

Bass Flat Treble Max I Bass Flat Treble Min
20

20

16

16

12

12

v

8

8

4

4

~

0

-4
-8

./

r"'"

--"'"'...

•'"

i'o...~

0

dB

-8
1'0..

Z

1,..0

-16
-20
10

lK

100

10K

i-""

~

"/

-I-

-12

-16

:/'"
r,.;'"

f-

-4

-12

-20

10K

fREQUENCY (Hz)

fREQUENCY (Hz)

dB

CO
CO
N

10

100

lK

r--..
:-..

['..,

"
10K

fREQUENCY (Hz)

fREQUENCY (Hz)

TLiH/904B-5

TLiH/904B-4

Loudness Contours LMC1993 Only
REf LEVEL 0.000 dB

IDIV 10.000 dB

II
dB

10

lK

100

fREQUENCY (Hz)
Note: Above graphs are tentative and thus subject to change.

1-251

10K
TL/H/904B-6

~
0)
0)

[;

,---------------------------------------------------------------------------------,
Typical Applications

::::!!

...I
....
C'i

Vcc (+8V)

0)
0)

.,...

U

DATA

::::!!

...I

FROM I' P CONTROLLER

ENABLE
INPUT 1
INPUT 2

~

I

O.ll'f*

26

4

25
24
LMC1993

7

SELECT OUT
56 kD.

27

3

6

LOUDNESS

LOUDNESS
OPTION

8

SELECT IN

28

2

5

INPUT3
0.1 t f 3.0k.Cl

'-/

1

CLOCK

9

23
22
21
20

TONE IN
0.00471'fi=
10
330 pF:= =:
TONE OUT
11
, TO.0047 J.lF *
OP AMP OUT
12
REAR OUT
13
TO POWER AMPS
FRONT OUT
14

19
18
17
16

Vee

t

BYPASS

0.1~

10~
+

INPUT 1

-=

INPUT 2
INPUT3
3.0k.Cl OJ

LOUDNESS

I

SELECT OUT
SELECT IN

*O.ll'f

TONE IN

*o.00471'f

TONE OUT

56 kD.
: ~330pF

OP AMP OUT *0.0047 J.lF
REAR OUT
TO POWER AMPS

FRONT OUT

15~

LEFT

RIGHT
TL/H/9048-7

Vee (+8V)
DATA
FROIA J.lP CONTROLLER

ENABLE
INPUT 1
INPUT2
INPUT3
INPUT 4
SELECT OUT

O.IJ.1*

o.0047 J.lfr
o.0047 J.lf;;;::
TO POWER AMPS

'-/

1

CLOCK

SELECT IN

2

27

3

26

4

25

5

24

6

LMC1992
4 INPUT
OPTION

7
8
9

TONE IN
TONE OUT
OP AMP OUT
REAR OUT
FRONT OUT

28

23
22
21
20

veei
BYPASS

OJ
10 F

+

INPUT 1
INPUT 2
INPUT3
INPUT 4
SELECT OUT

~.1 J.lF

SELECT IN

T

TONE IN

~

~.O047 J.lF

*

13

0.0
047 J.lF
OP AMP OUT
18
REAR OUT
17
FRONT OUT TO POWER AIAPS
16

14

15n

10
11
12

LEFT

19

TONE OUT

RIGHT

FIGURE 7. Connection Diagrams Options with Minimal External Components
Order Number LMC1993 (loudness device), LMC1992 (4 Input device)
See NS Package Number N28B

1-252

TL/H/9048-8

r-----------------------------------------------------------------------------, r

3:

General Information

Application Hints-Digital

The LMC1992/3 is a CMOS/bipolar high quality building
block intended for high fidelity audio signal processing.
While the LMC1992/3 is manufactured with CMOS processing, unique NPN transistors exist which are used to build low
noise op amps. The combination of CMOS switches, bipolar
op amps and sichrome resistors make it possible to achieve
an order of magnitude quality improvement over standard
bipolar circuits.

In addition, a 12 bit data stream can be used if needed. The
first two bits and last nine bits remain the same while any
number of don't care bits can be inserted preceding the
MSB of the three bit function select. Since these don't care
bits are just shifted out internally, any number can be inserted to allow ease of programming. Thus the data stream
word length becomes simply 11 + (number of extra bits).
When the ENABLE input returns high, any further serial data
input is inhibited. Upon this positive transition of the
ENABLE, the data in the internal shift register is transferred
into the data latches. Note that until this time, the states of
the internal data latches have remained unchanged.

The LMC1992/3 has internal logic decoding which allows a
computer (",P) to communicate directly to the audio control
circuitry through a standard MICROWIRE interface. This 3
wire interface consists of DATA input line, a CLOCK input
line, and an ENABLE line. When the ENABLE line is low,
data can be shifted (serially) from the controller into the
audio control circuit. As the ENABLE line goes through the
low to high transition, data entry is disabled and data present in the internal shift register is latched and the instruction
is executed.
From the controller 11 bit serial data stream, the first two
bits address the device (LMC1992/3) permitting other devices (ie: PLL, equalizer) to share the same 3 wire bus. Of
the remaining 9 bits, the next 3 bits are used for the function
select (ie: volume, fader ... ). The remaining 6 bits are data
for the function being addressed.

...co

(')

co

N
......

r

s:
(')

...

co
co

w

SERIAL DATA FORMAT
The serial data format, bit assignment and sequence is
shown in Table I. Not shown in Table I are the protection
address bits (1, 0) which as discussed earlier must precede
the nine bit data word.
Note that not all the allotted data bits are used for all functions excluding volume. The extra bits are denoted with an
"X" for don't care. Even though these extra bits have no
effect on their respective controls, they still must be clocked
into the LMC1992/3 for proper operation. Otherwise erroneous results will occur.
DATA COMMUNICATION
The following routines apply to operation of the LMC1992/3
with COPSTM microcontrollers. The routines arbitrarily select register 0 as the 110 register. It is assumed that chip
select is high, SK (clock) is low, and SO (data) is low on
entry to the routines. The routines exit with chip select high,
SK low and SO low. Output port GO is arbitrarily chosen as
the chip select for the external device.
The 11 data bits intended to control the LMC1992/3 are
assumed to be in the 4 bit registers 13-15 with the 4 MSB
bits in register 13. This provides an extra bit (which works
fine also) resulting in a data stream 12 bits long.

Serial Data Entry into the
LMC1992/3
Serial information entry into the LMC1992/3 is enabled by a
low level on the ENABLE input. One bit is accepted from the
DATA input with each positive transition of the CLOCK input. The CLOCK input must be low preceding the negative
transition of the ENABLE input.
The first two bits accepted following the negative transition
of the ENABLE input are interpreted as an address. If these
bits are not 1,0 no further information will be accepted from
the DATA input, while the data latches will remain unchanged when the ENABLE line returns high.
If the first two bits are 1,0 then all succeeding bits are accepted as data, and are shifted successively into the internal shift register as long as ENABLE remains low.

CLOCK
DATA
DON'T CARE

DON'T CARE
ENABLE

CHIP SELECT
ADDRESS

FUNCTION ADDRESS

DATA WORD

TLlH/9049-9

Note 1: Negative transition on ENABLE clears previous address. Clock must be low during transition.

Nole 2: Additional don't care states may be inserted here for ease of programming. (Optional.)
Nole 3: Positive transition on ENABLE latches in new data if the LMC1992/3 has been addressed. Clock can either be high or low during transition.

FIGURE 8. Clocking Data into the Standard MICROWIRE Interface
(Minimum Number of Bits in Data Stream)
1-253

II

Applications Hints-Digital

(Continued)

DESTRUCTIVE DATA OUTPUT

This routine outputs the data under the conditions specified
above. The output data is destroyed after it is transmitted.
Note that this is a general purpose routine and handles all
the overhead except loading the data into the registers. The
routine takes a total of 17 ROM words and can be undoubtedly be reduced in specific applications.

NON DESTRUCTIVE DATA OUTPUT
This routine is identical to the destructive data routine except that the transmitted data is preserved in the microcontroller. The nondestructive routine takes 21 ROM words.
Four more than the destructive routine. Again this is a general purpose routine which can probably be reduced in specific applications.

OUT!:

:point to start of data word
:set C to enable SK clock
:select external device GO=O
:enable shift register output

OUT2:

;data transmission loop
;turn on clock

SEND1:XAS
SEND2:

SEND:

LBI
SC
OGI
LEI
LD
XAS
XIS
JP
RC
XAS
LEI
RET

0,13
14
8

SEND
15
0

:deselect external device
:set SO to 0

LBI
SC
OGI
LEI
JP
LD
XIS
JP
XAS
RC
CLRA
NOP
XAS
OGI
LEI
RET

0,13

;point to start of data word

14
8
SEND2

;select external device GO=O
;enable shift register output
;data output loop

SEND 1
;send last data
;wai t 4 cycles-data going aut

15
0

;turn SK clock off
;deseleat deviae
:set SO to 0

Nole: These routines are tentative and subiect to change.
START

Start raullne
Inillate new cycle
Reset counter

Clock rising edge

Output next dale
bit onto Lt.tC1992
DATA line

Increment counter
Clock failing edge

Check counter

Exit with CLOCK
and DATA high
End cycle
Start raullne
TLIH/9048-10

FIGURE 9. General Flowchart for Controlling LMC1992/3 MICROWIRE Serial Inputs

1-254

Application Hints-Digital

rES:

...

o

(Continued)

-...
CD
CD
N

TABLE I. Programming Codes for LMC1992/3
Address
A2
A1
AO
1

1

1

Function
Left Rear Fader

05

04

X

M

Oata
02
03
N

N

01

00

N

L

rES:

Values

o

CD
CD

-40 dB = XOOOOO
-20 dB = X01010
OdB = X101XX

1

1

a

Right Rear Fader

X

M

N

N

N

L

-40 dB = XOOOOO
-20 dB = X01010
OdB = X101XX

1

a

1

Left Front Fader

X

M

N

N

N

L

-40 dB = XOOOOO
- 20 dB = X01010
OdB = X101XX

1

0

a

Right Front Fader

X

M

N

N

N

L

-40 dB = XOOOOO
-20 dB = X01010
OdB = X101XX

a

1

1

Volume

M

N

N

N

N

L

-80 dB = 000000
-40 dB = 010100
OdB = 101XXX

a

1

a

Treble

X

X

M

N

N

L

-12 dB = XXOOOO
FLAT = XX0110
+ 12 dB = XX1100

a

a

1

Bass

X

X

M

N

N

L

-12 dB = XXOOOO
FLAT = XX0110
+12dB = XX1100

a

a

a

Input Select &
LOUDNESS

X

X

I

M

N

L

Co)

OPEN = XXIOOO
INPUT1 = XXI001
INPUT2 = XXI010
INPUT3 = XXI011
INPUT4 = XXI100
LOUDNESS ON: I = 1
LOUDNESS OFF: I =

'(see note)
'(see note)

a

'Nole 1: With LMC1993 loudness device, INPUT 4 is not available.
'Nole 2: With LMC1992 4 input device, 03 of input select must be low (0), and INPUT 4 is available.
Nole 3: M & L represent most and least significant data bits.
Nole 4: All attenuators 2 dB/step.
Nole 5: Tone controls 2 dBlstep

@

50 Hz and 15 kHz.

II

1-255

~
0)
0)

..-

o

:E
-'
......

'"..0)
0)

o

:E
-'

r----------------------------------------------------------------------,
Application Hints-Analog
INPUT CHANNEL SELECTION
When operating from a single positive power supply, the
LMC1992/3 signal inputs require a DC bias voltage for proper operation of the internal voltage followers and buffers.
This usually means that the signal sources, if operated off
the same single supply, can be directly coupled to the
LMC1992/3 without a coupling capacitor. For example, on
an 8 Vdc power supply, all signal inputs to the LMC1992/3
(pins 4-6, 24-26) should have a DC component of approximately 4 Vdc. Maximum signal levels of 2 Vrms (5.6V peakto-peak) would then swing from 1.2V to 6.8V.
For signal sources lacking in this requirement, such as
those derived from external input jacks to the system, the
bias voltage needs to be provided. A simple voltage divider
with filter for supply rejection as shown in Figure 10 will
suffice.
When the LMC1993 is used, input 4 is not available. That
pin becomes the loudness input. Selecting input 4 when using the LMC1993, or turning on the loudness function when
the LMC1992 is used can cause undesirable results, thus is
not suggested.
For best results, a separate bias circuit for each channel or
even one for each signal source lacking a DC component
should be used to prevent crosstalk between channels and
inputs. Though stereo sources can have bias circuits in
common for left and right signal and still maintain reasonable separation.

The typical tone response obtained in the standard application circuit (C2 = C3 = 0.0047 p.F) is shown in Figures 2-5
for each step of boost and cut. When modifying these
curves it is important to note that it is ratio of C3 to C2 that
determines the mid frequency gain. For example, with C3 =
2(C3) the tone response at "flat" setting would be approximately 0 dB at 20 Hz and 20 kHz while +6 dB at 1 kHz.
Thus C2 should equal C3 for a symmetric tone response.
The effect of altering the recommended values of the tone
shaping capacitors C2 and C3 is to shift the tone response
curve up or down in frequency. By increasing the capacitance of C2 and C3, the frequencies at which 2 dB/step is
achieved will decrease from 50 Hz to 35 Hz and from 15
kHz to 10kHz with a 0.0068 p.F capacitor. Likewise with a
decrease in capacitance of C2 and C3 the 2 dB/step frequencies will increase from 50 Hz to 70 Hz and from 15 kHz
to 20 kHz with a 0.0033 p.F capacitor.
From Figure 1 the turnover frequencies are approximately
Fhb = 1/sC2(13.8K) and Fib = 1/sCl (116.4K) for treble
and bass respectively at maximum boost. While the inflection frequencies (at which maximum boost and cut are within 3 dB of their final values) are Fh = 1/sC2(2.6K) and FI =
1/sC1 (625.6K) for treble and bass respectively at maximum
boost.

+Vcc
C

RIO
10k.D.

Depending upon the particular input source that is selected,
one of the three stereo inputs will be available at the select
output pins 8 and 22 (left and right channels respectively).
The DC bias voltage at those pins will be one base-emitter
voltage (approximately 0.7 Vdc) below the source due to the
internal emitter follower (see Figure 1). Thus, if the selected
input has a bias of 4.0 Vdc the DC component at pins 8 and
22 will be about 3.3 Vdc.
The use of an emitter follower for input selection allows
connection of additional sources to the system. For example, many radio IC's also have emitter follower outputs that
allow the user to wire-or multiple outputs together and control their selection by input or supply switching. The signal
output pin 8 and 22 of the LMC1992/3 are constructed similarly and may be treated in the same manner, consistent
with the same requirements. If another emitter follower output is driving these nodes, the LMC1992/3 input select
should be switched to either "XXXOOO" or "XXX11 X" open
input codes (see Table I).
The select output pins 8 and 22 may be directly coupled via
a capacitor to the select input (pins 9 and 21) as shown in
Figure 1 or connected to external noise reduction and/or
equalizer circuits as shown in Figure 11. Should both be
utilized, it is important that noise reduction (ie: DNR® using
the LM1894) be performed before equalization. Otherwise,
the equalization control settings could adversely affect or
even prevent the noise reduction systems from operating.
The input select switch can also be used as a mute function
with volume at -80 dB, the input select can be set to
"XXXOOO" open input to further mute the outputs to provide
greater than -100 dB attenuation if desired.
TONE RESPONSE
The tone function (bass and treble) is controlled by capacitors C1 and C2 (see Figure 1). The exact amount of boost
and cut obtained is determined by the data word as given in
Table I.

RI2

...-

.---+---'\Nu"v-......-I PIN 4

CI~~

RII.
I 0 J'F~

-==-

5°~~!l

0.1 J'F(.5

LMC1992

SIGNAi
TL/H/9048-11

FIGURE 10. DC Bias Input Circuit
LOUDNESS FUNCTION-LMC1993 ONLY
The loudness compensation as shown in Figure 1 is controlled by components R1, R2, C4, C5. If selected it will
introduce bass and slight treble boost (in addition to any
tone shaping requested) that is dependent upon the setting
of the volume control. The exact nature of the transfer function at -34 dB is given by:
Vo = _1_ (s*C5°R2+1)'(sOC4*(R1+112K)+I)
Vi
4.67 (s'C4'R1 + 1)*(s*C5°(R5+41.34K)+ 1)
If only bass boost is required the external components R 1
and C4 can be deleted, minimizing the external component
count.
If this device is selected only three inputs will be available to
input select (input 1-input 3). For systems where loudness
compensation is not required the user may choose the
LMC1992 or simply eliminate the components associated
with the loudness pin and being careful when programming
to always keep the loudness function off (see Table I).
The data bit used to enable or disable the loudness function
is embedded in the input data select data word as D3. Thus
care must be taken to send a complete data word (loudness
on/ off and input select data) in order to prevent erroneous
operation.

1-256

r-

;:

...

FADER FUNCTION

o

Since all four fader outputs LR, LF, RR, RF are all independently adjustable, a balance control would be redundant.
The balance function is accomplished via software by simultaneously changing both front and rear faders on the same
channel by the desired amount of balance. Since 40 dB of
attenuation is available this should satisfy most any balance
requirements.

CD
CD

N
......
r-

;:

...

o

CD
CD
Co)

SYSTEM CONNECTION
- - - - - , . ENABLE
~c~w~e~K~-------'
J
 Noise Reduction and Equalizer
(LMC843, LMC835) (One Channel Only-LMC1993).

II

1-257

Section 2
Radio Circuits

Section 2 Contents
Definition of Terms. . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM1800 Phase-Locked Loop FM Stereo Demodulator...... ....... .......... ... .........
LM1863 AM Radio System for Electronically Tuned Radio... .. .... ...... ... . .... ..... ...
LM1865/LM19651*LM2065 Advanced FM IF System...................................
LM1866 Low Voltage AM/FM Receiver ...............................................
LM1868 AM/FM Radio System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM 1870 Stereo Demodulator with Blend. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. . . . .. . . . .
LM1871 RC Encoder/Transmitter..... .. ........ .... ............................... ..
LM1872 Radio Control Receiver/Decoder... .. ........ ..... ...... .. ....... ..... .......
LM1884 TV Stereo Decoder........... .......... .............. ...... .......... .... ..
LM3089 FM Receiver IF System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM3189 FM IF System..... ................ ................... .. .... ... ....... ... ...
LM3361 A Low Voltage/Power Narrow Band FM IF System........ .. .... .......... ... ...
LM3820 AM Radio System ..........................................................
LM4500A High Fidelity FM Stereo Demodulator with Blend ..............................
TBA120S IF Amplifier and Detector...... ........ .. ... ................. ... .... ........

"Devices Not Covered In Last Publication

2-2

2-3
2-4
2-8
2-11
2-23
2-37
2-44
2-52
2-58
2-74
2-93
2-96
2-102
2-109
2-114
2-118
2-125

.-----------------------------------------------------------~~
CI)

_

Q.

National

o·

Semiconductor
Corporation

o

a'c

Radio Circuits
Definition of Terms

I
~

s·

::;:

o·
:::J
AGC de Output Shift: The shift of the quiescent Ie output
voltage of the AGe section for a given change in AGe central voltage.

-3 dB Limiting Sensitivity: In FM the input signal level
which causes the recovered audio output level to drop 3 dB
from the output level with a specified large signal input.

AGC Figure of Merit: The widest possible range of input
signal level required to make the output signal drop by a
specified amount from the specified maximum output level.
Typical F.O.M. numbers are from 40 dB to 50 dB, for domestic radios and about 60 dB for automotive radios (for
-10 dB output level change).

Lock In Range: That range of frequencies about the free
running frequency for which the phase locked loop will
come into lock if initially starting out of lock.
Maximum Sweep Rate: The maximum rate that the veo
may be made to vary its oscillating frequency over its
Sweep Range.
Output Resistance: The ratio of the change in output voltage to the change in output current with the output around
zero.
Output Voltage Swing: The peak output voltage swing, referred to zero, that can be obtained without clipping.

AGC Input Current: The current required to bias the central
voltage input of the AGe section.
AM Rejection Ratio: The ratio of the recovered audio output produced by a desired FM signal of specified level and
deviation to the recovered audio output produced by an unwanted AM signal of specified amplitude and modulating
index.
Channel Separation: The level of output signal of an undriven amplifier with respect to the output level of an adjacent
driven amplifier.
Detection Bandwidth: That frequency range about the free
running frequency of the tone decoder/phase locked loop
where a signal above a specified level will cause a detected
signal condition at the output.

Phase Detector Sensitivity: The change in the output voltage of the phase detector for a given change in phase between the two input signals to the phase detector.
Power Bandwidth: The power bandwidth of an audio amplifier is the frequency range over which the amplifier voltage gain does not fall below 0.707 of the flat band voltage
gain specified for a given load and output power.
Power bandwidth also can be measured by the frequencies
at which a specified level of distortion is obtained while the
amplifier delivers a power output 6 dB below the rated output. For example, an amplifier rated a 60W with :;;0.25%
THO, would make its power bandwidth measured as the
difference between the upper and lower frequencies at
which 0.25% distortion was obtained while the amplifier was
delivering 30W.

Detection Bandwidth Skew: The measure of how well the
detection bandwidth is centered about the free running frequency. It is equal to the maximum detection bandwidth frequency plus the minimum detection bandwidth frequency
minus twice the free running frequency.
Hold In Range: That range of frequencies about the free
running frequency for which the phase locked loop will stay
in lock if initially starting out in lock.

Power Supply Rejection: The ratio of the change in input
offset voltage to the change in power supply voltages producing it.
Slew Rate: The internally limited rate of change in output
voltage with a large amplitude step function applied to the
input.

Input Resistance: The ratio of the change in input voltage
to the change in input current on either input with the other
grounded.
Input Sensitivity: The minimum level of input signal at a
specified frequency required to produce a specified signalto-noise ratio at the recovered audio output.
Input Voltage Range: The range of voltages on the input
terminals for which the amplifier operates within specifications.
Large-Signal Voltage Gain: The ratio of the output voltage
swing to the change in input voltage required to drive the
output from zero to this voltage.

Supply Current: The current required from the power supply to operate the amplifier with no load and the output at
zero.
Sweep Range: That ratio of maximum oscillating frequency
to minimum operating frequency produced by varying the
central voltage of the veo from its maximum value to its
minimum value with fixed values of timing resistance and
capacitance.
VCO Sensitivity: The change in operating frequency for a
given change in veo central voltage.

2-3

..-nl
o

3en

~NatiOnal

Semiconductor
Corporation

Radio Circuits
Selection Guide

AM RF/IF Detector

Portable Home Auto Synthesized

LM1863

•

•

LM1866
LM1868

•
•

LM3820

•

•
•
•

•

Pin
Input
AM
Audio
Count
Supply Supply Sensitivity
Internal Meter
and
Power
Voltage Current for 20 dB
Detector Output
(Dip
FMIF Amplifier
Package)
SIN Ratio

•

•

20'

7-16

8.3 rnA

30 ",V

20

3-15

15mA

25 ",V

•

20

4.5-15

22 rnA

12 ",V

•

14

4.5-16

18mA

35 ",V

•

•
•

•

•

•

'SO Surface Mount Package Only

Stereo Decoder
Portable Home Auto

LM1800
LM1870

•

LM1884*
LM4500A

•

•
•
•
•

Pin Count
Supply Supply
Dip
Voltage Current
Package

•
•

THD

Separation Blend

16

10-18

21 mA

0.4%

45dB

20

7-15

26mA

0.05%

45dB

16

8-16

35mA

0.1%

-

16

8-16

35 rnA

0.1%

40 dB

•

ARI
High Lamp Output
Interference
Cut Driver Buffer
Rejection

•

•
•

•
•

•
•

•
•

•

'TV Stereo Decode,

Radio Remote Control
Function

Channels

Pin Count
(Dip Package)

Supply
Voltage

Supply
Current

Analog

Digital

Frequency
Range

LM1871

Encoder/T ransmitter

18

4.5-15V

14mA

upto6

2

upto 72 MHz

LM1872

Decoder/Receiver

18

2.5-7V

13mA

2

2

up to 72 MHz

2-4

FM IF/Detector
Portable

Home

LM1965

•
•

LM2065

•

LM1865

LM1866
LM1868

•
•

Auto

Synthesized

Pin Count
Dip

•

•

•
•

•

Pin Count
S.O.

Supply
Voltage

Supply
Current

- 3 dB Limiting
Sensitivity

THD

Mute

20

7.3·16

43mA

60/LV'

0.1%

20

7.3-16

43mA

60/LV'

0.1%

•
•
•
•

20

7.3-16

43mA

60/LV'

0.1%

•

20

3-15

17mA

12/LV

0.5%

0

20

4.5-15

19mA

15/LV

1.1%

LM3089

•

0

16

8-16

23mA

12/LV

0.5%

LM3189

0

•

16

8-16

31 mA

12/LV

0.5%

0

16

2·9

2.8mA

2/LV

-

LM3361At

•

16

AGC
Outputs

AFC

Meter
Output

•
•

Reverse
Reverse
Forward

0

0

•

AM/
FMIF

•
•
•
0

•
•

•
•
•

•

0

•

0

•

0

"'Exclusive of 26 dB Buffer
tNarrow·Band FM-IF

I})
01

-

-

------

- - - - - - -

--

---

-

--

---

- - - - - - -

-

9p!n~

-

--

---

UO!I:l919S-SI!n:)J!:l O!peH

&

:2
:s

Cordless Telephone Receiver

CJ

c

AUDIO AMP
LM 1895
LM 386
LM 389

0

:;::;
()

.!!
&

!·-s
~

TLlXX/OOll-l

U
0

Portable Radio (Stereo)

:g
as

FM

£C

AM/FM IF
LM 1866

AM

TL/XX/OOll-2

Portable Radio (Monaural)

Table/Clock Radio

FM

FM
AM/FM IF
LM 1868

AM/FM IF
LM 1866

AM

TLlXX/OOll-3

LM 1895
LM 2895
TLlXX/OOll-4

Auto Radio (Manually Tuned)
STEREO
DECODER
LM 1870
LM 4500

FM

TONEjVOLUME
LM 1035
LM 1036
LM 1040

AM

POWER AMPS
LM 383
LM 2002
LM 2005

CASSETTE
PREAMPS
LM 1837
LM 1897
TL/XX/OO11-5

2-6

Automotive Radio (Electronically Tuned)
STEREO
DEMOD
LM 1870
LM 4500

FM

POWER AMPS
LM 383
LM 2002
LM 2005

AUDIO
SWITCH
LM 1037
LM 1038

AM

CASSETTE
PREAMPS
LM 1837
LM 1897
TL/XX/OOll-6

Home Stereo System (Audio Power

< 10W)

FM

AM
TONE/VOLUME
LM 1035
LM 1036
LM 1040

POWER AMPS
LM 2879

PHONO
PREAMP
lM 381
LM 382
lM 387
TUXX/OOll-7

Home Component Stereo (Audio Power> 10W)
FM
POWER AMPS
LM 1875
LM 391

CASSETTE
PREAMP
lM 833
LM 1897

TAPE

PHONO
PREAMP
lM 833
TL/XX/OOll-B

2-7

C)
C)

co
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:::::i5

....I

r----------------------------------------------------------------------------,
NatiOnal

~ Semiconductor
Corporation

LM 1800 Phase-Locked Loop FM Stereo Demodulator
General Description

Features

The LM1800 is a second generation integrated FM stereo
demodulator using phase locked loop techniques to regen·
erate the 38 kHz subcarrier. The numerous features inte·
grated on the die make possible a system delivering high
fidelity sound while still meeting the cost requirements of
inexpensive stereo receivers. More information available in
AN·81.

•
•
•
•
•
•

Automatic stereo/monaural switching
45 dB power supply rejection
No coils, all tuning performed with single potentiometer
Wide operating supply voltage range
Excellent channel separation
Emitter follower output buffers

Connection Diagram
POWER
VCD
LOOP
LOOP
SUPPLY CONTROL FILTER FILTER

PHASE
DElEC·
THRESH· THRESH·
TOR
PILOT
OLD
OLD
INPUTS MONITOR FILTER FILTER

16

11

10

LEFT
RIGHT RIGHT
OUTPUT OUTPUT LOAD

LAMP
DRIVER

Order Number LM1800N
See NS Package Number N16A

COMPOSITE AUDIO
INPUT
AMP
OUTPUT

LEFT
LOAD
&

GNO

&

DEEMPHASIS

DEEMPHASIS
TL/HI78B8-1

Top View

Typical Application
Vee

STEREO
LAMP

IIOOmAI

':"

LEFT
RIGHT ':"
OUTPUT OUTPUT

':"
TL/H17888-2

2·8

r
3:

....

Absolute Maximum Ratings

Q)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

Operating Temperature Range
Operating Supply Voltage Range
Storage Temperature Range

18V

Power Dissipation (Note 3)

O'Cto +70'C
+ 10V to + 18V
-65'Cto + 150'C

Lead Temperature (Soldering, 10 sec)

260'C

1500 mW

Electrical Characteristics (Note 1)
Typ

Max

Units

Supply Current

Parameter
Lamp "Off"

21

30

mA

Lamp Driver Saturation

100 mA Lamp Current

1.3

1.8

Conditions

Min

Lamp Driver Leakage
Pilot Level for Lamp "ON"

Pin 11 Adjusted to 19.00 kHz

Pilot Level for Lamp "OFF"

Pin 11 Adjusted to 19.00 kHz

Stereo Lamp Hysteresis
Stereo Channel Separation

100 Hz (Note 2)
1000 Hz (Note 2)
10000 Hz (Note 2)

15

V
nA

1.0
20

mVrms

3.0

7.0

mVrms

3.0

6.0

dB

30

40
45
45

dB
dB
dB

0.3

1.5

dB

140

200

260

mVrms

Monaural Channel Unbalance

200 mVrms, 1000 Hz Input

Monaural Voltage Gain

200 mVrms, 400 Hz Input

Total Harmonic Distortion

500 mVrms, 1000 Hz Input

0.4

1.0

%

Total Harmonic Distortion

500 mVrms, 1000 Hz Input, 1800A Only

0.1

0.3

%

±6.0

%offo

Capture Range

25 mVrms of Pilot

Supply Ripple Rejection

200 mVrms of 200 Hz Ripple

±2.0

Dynamic Input Resistance
DynamiC Output Resistance

35

45

dB

20

45

kn

900

1300

2000

n

SCA Rejection

(Note 4)

70

dB

Ultrasonic Freq. Rejection

Combined 19 and 38 kHz, Ref. to Output

33

dB

Nole 1: TA ~ 25·C and V+ ~ 12V unless otherwise stated.
Nole 2: The stereo input signal is made by summing 123 mVrms LEFT or RIGHT modulated signal with 25 mVrms of 19 kHz pilot tone, measuring all voltages with
an average responding meter calibrated in rms. The resulting waveform is about 600 mVp-p.
Note 3: For operation in ambient temperatures above 2S"C, the device must be derated based on a 150°C maximum junction temperature and a thermal resistance
of 80"C/W junction

to ambient.

Note 4: Measured with a stereo composite signal consistency of 80% stereo, 10% pilot and 10% SeA as defined in the FCC Rules on Broadcasting.

Nole 5: VCO "OFF" curve represents the distortion attainable using good 19 kHz and 38 kHz filters.

2-9

o
o

o
~
..-

:::&

r-----------------------------------------------------------------------------,
Typical Performance Characteristics

.....

Supply Ripple Rejection

Channel Separation

60

60
RIPPLE = 200 mV,m.
1=200Hz

55

.

;;;

:s
co

...

!

50

;:

45

;;:
'"

40

-

~~

/

i-"""

z
CI
;:

50

'"~

45

.

40

...:z:

35

c

~

-'
w

I

z
c

35

1) VCO@

,9000.,0 Hz
2) PIN 6 OPEN
3) aOOmVp.p
COMPOSITE

55

C, = lQ.uFd

~/

~

I'

30

30
10

6

12

14

0.3

16

1.0

r"'"

Cl = INPUT COUPLING
CAPACITOR
3.0

10

30

AUDIO FREQUENCY (Hz X 100)

SUPPLY VOLTAGE (V)

TLlHI7BBB-4

TLlH/7B8B-3

Monaural Distortion
vs Input Amplitude

Monaural Distortion
vs Frequency
0.5

-

0.45 I- vco = 19 kHz
= 500 mV
OS 0.4 '- VIN
LM1800A
CI
;: 0.35

t~:8k:U~

..

0.8

~
zco 0.6

I
II

;:

'"co
In 0.4
0.2

o

I--"

~

0.2

......

'"

0.3

-'

0.2
0.15

c

V

Ci

co

In 0.25
Ci

'"c

:>

z
::;;

~

CI

NO FILTERJ

I

.v:

0.1

VCO "OFF"
NOTE5 -

0.05

o
0.4

0.6

0.8

20

1.2

50 100 200 500 lk 2k

""
-

5k 10k 15k

FREQUENCY (Hz)

INPUT SIGNAL LEVEL (V,m.)

TLlH/7B88-6

TLlHI7B8B-5

2-10

k:....

NatiOnal

~ Semiconductor

CD

en
Co)

Corporation

LM 1863 AM Radio System for
Electronically Tuned Radios
General Description
The LM1863 is a high performance AM radio system intended primarily for electronically tuned radios. Important to this
application is an on-chip stop detector circuit which allows
for a user adjustable signal level threshold and center frequency stop window. The IC uses a low phase noise. levelcontrolled local oscillator.
Low phase noise is important for AM stereo which detects
phase noise as noise in the L-R channel. A buffered output
for the local oscillator allows the IC to directly drive a phase
locked loop synthesizer. The IC uses a RF AGC detector to
gain reduce an external RF stage thereby preventing overload by strong signals. An improved noise floor and lower
THO are achieved through gain reduction of the IF stage.
Fast AGC settling time. which is important for accurate stop
detection. and excellent THO performance are achieved
with the use of a two pole AGC system. Low tweet radiation

and sufficient gain are provided to allow the IC to also be
used in conjunction with a loopstick antenna.

Features
•
•
•
•
•
•
•
•
•
•

Low supply current
Level-controlled. low phase noise local oscillator
Buffered local oscillator output
Stop circuitry with adjustable stop threshold and adjustable stop window
Open collector stop output
Excellent THO and stop time performance
Large amount of recovered audio
RF AGC with open collector output
Meter output
Compatible with AM stereo

Block Diagram
VA"
TDV'

TUNING
VOLTAGE

rh"l t

H

L-_-"l.

O•
TANK
IB

I

RF INPUT

1~
MIXER

IF

IN
20

INPut OUTPUT
11
14

IF

12

I.F.
DECOUPLE

'---I----I---i~o_"""'Ir__AUOlO

19
BUFFERED
L.O.OUT

T

TO SYNTHESIZER
(HI TO STOP)

TO SYNTHESIZER

...r

LOGIC
SUPPLY

TUH/51B5-1

Order Number LM1863M
See NS Package Number M20B
2-11

EI

Absolute Maximum Ratings
Supply Voltage
Package Dissipation (Note 1)
Storage Temperature Range

16V

Operating Temperature Range

O'Cto +70'C
Soldering Information
Small Outline Package
Vapor Phase (60 sec)
215'C
Infrared (15 sec)
220'C
See AN·450 "Surface Mounting Methods and Their Effect
on Product Reliability" (Appendix D) for other methods of
soldering surface mount devices.

1.7W
- 55'C to + 150'C

Electrical Characteristics
(Test Circuit, TA = 25'C, V+ = 12V, SW1 = Position 1, SW2 = Position 2, unless indicated otherwise)
Parameter

Conditions

Min

Typ

Max

Units

8.3

12.5

mA

STATIC CHARACTERISTICS
Supply Current

VIN = OmV

Pin 16, Regulator Voltage

5.6

V

Operating Voltage Range

(See Note 2)

Pin 3 Leakage Current

VIN = OmV

0.1

p.A

Pin 9, Low Output Voltage

VIN = 0 mV, SW2 = Position 1

.15

V

Pin 17, Output Voltage

VIN = OmV

0

V

7

16

V

DYNAMIC CHARACTERISTICS: (fMOD = 1 kHz, fiN = 1 MHz, M = 0.3)
Maximum Sensitivity

VIN For VAUDIO = 6 mVrms

7.5

20 dB Quieting Sensitivity

VIN for 20 dB SIN in Audio

15

Maximum Signal to Noise Ratio

VIN = 10mV

Total Harmonic Distortion

VIN = 10mV

.26

Total Harmonic Distortion

VIN = 10 mV, M = 0.8

.63

2

%

Audio Output Level

VIN = 10 mV

120

160

mVrms

Overload Distortion

VIN = 50 mV, M = 0.8

7.5

%

Meter Output Voltage

VIN = 100 p.V

0.5

V

Meter Output Voltage

VIN = 10mV

4.6

V

Local Oscillator Output Level
onPin19

(See Note 3), SW1 = Position 1

147

mVrms

Local Oscillator Output Level
on Pin 19

(See Note 3), SW1 = Position 2

125

mVrms

Stop Detector Valid Station
Frequency Window

VIN = 10 mV, difference between
the two frequencies at which
Pin 9 < 1V, SW2 = Position 1

Stop Detector Valid Station
Signal Level Threshold

Find VIN for which Pin 9
SW2 = Position 1

RF AGC Threshold

Find VIN that produces
10 p.A of current into Pin 3

Pin 3 Low Output Level

VIN = 30mV

40

80

> W,

100

/LV
30

54

/LV
dB
%

2.5

4

5.5

kHz

8

16

70

p.Vrms

3

6

10

mVrms

0.1

V

Pin 9 Leakage Current

VIN = 30mV

0.1

p.A

Pin 17 Output Resistance

VIN=10mV

825

n

1: Above TA = 2S'C derate based on Tj (MAX) = ISO'C and 8jA = 8S'C/W.
Note 2: All data sheet specHications are for v+ = 12Vand may change slightly with supply.
Note 3: The local oscillator level at Pin 19 is identical to the level at Pin 18 since Pin 19 is an emitter follower off of Pin 18.
Note

2·12

r-----------------------------------------------------------------------------,
Test Circuit

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TOKO
1NRES·A5621AAG

r-------,
I

I

I
I
I

I
I
I

J

01

t-_-'lN.-!1--.J 3
200k

VAUDIO

lk3

14 13
12
NC
IF
IF
DUT
DECOUPLE

\15
AUDID

'17
METER

VREG

II
IF
INPUT

50
RESON

V·

NC

STOP
OUT
9

MIXER
OUT
10
2---'

B2D

rI
I
I

0.1 pi'

I
I

I

I

12k

I
I

TO

47k

PIN
14

2
SW2

~;

L_

01
V'

4k1
V·

TL/H/5185-2

Typical Performance Characteristics (From Test Circuit)

,

~

~

8

10

r-1""""'1r-'1---.---,---,---.---."""'T'

:<;!.:;l -10

5=

I-Hr.'~+-fMOD=1

~ ~ -20
e g -30
'" cc
~~ -40

~ -60
~

S

I

J ~ --""

I

_

~

I

I

1 ~
-HMETER

NOIS~ -J .I
I

1 ~V 10 ~V 100 ~V 1 mV 10 mV 100 mV
ViN-MIXER INPUT VOLTAGE (VIm.)

o

t'N~

SUPPLY CURRENT
(mAl ;)..

~

"

-1

1/

I

-3
-4

I

--

M=0.3
fMOO=1 kHz
!rUNE=1 MHz
VIN =10 mV,m.

I

ViN-MIXER INPUT VOIJAGE (VIm.)

--

AUDIO OUTPUT
(dB)

-2

1 ~V 10 ~V 100 ~V 1 mV 10 mV 100 mV

2-13

I-

Y

!rUNE =1 MHz
NO MODULATION

Z -

THD+NOfS~ I
"

RFAGC
PIN 3

......

kHz

frurl Mr

I{

;;; !L50 ,.
~'"

I 11

I""'TM='0.3'
. I I
~

AUDIO ...

:E
0;>1'

r

3:
.....

o

4 6 8 10 12 14 16
SUPPLY VOLTAGE (V)

3

LM1863
LM1863: AM ETR Radio

l>

V'IIIIE

'0

"2-

~

O·

V'

:::I

o

~i"

c

f

::;

~:·....

'C27

'-~r

co

1,'

+I~
1l1li

KV~

1~~~

,'~

...

1124

ftAilli

v,"

1W!.......l!!
IF
Nt
JF

"

AUDIO

OUT

DECOUPlE

INPUT
"

STOP

MIXER
OUT

NON·DOMINANT
AGe
DEC

~
....

RFAGe

GN.
01'
DJ3,.F

R17

"

STOP

AGe

OUT

'.

••

POLE

He

11

OUT

10

+
_C2

2

l'~

n

TUKU
lNRES·A5112BEK

---7

!.C1
"};22 PF
R3

...""

'Ok

"'

HI

Cl1

""
50

C19

0.001".

J;'~

.DO

"'"

.."

V'

V·
fO tGNTROLUR

r-d-----...·

1
II ~..,:' II

'.'-20.'!*"
~
C21

C16

1101(0
'V123"

CII

L -________-+I~_~I

otl1.,F

C26

"""'1

DUMMY
ANTENNA

I

I
cn
I
IL ______
'2P'
.JI

RI.

220k
VrUIiE

CI7

;J; 1tD3 11

f

TUH/5185-8

r-

...3:

Performance Characteristics of Applications Circuit

CO

en
w
o rTrr-rr:;......"'I""!'..,..,""!""I

6

100

l.oI <.:t:1-+-H-l-+-H
5
'I'
(118)

-10

l-br.

4

!YOUls,
... r![ -3D H#f+~Hr-Cf++-H-l--l 3

JHD
~dB=125 mvrml+'~~I+-H:±+
NOISE

-40

,1\

'it
ItlI,NE,O,6IMH~"r~A:~:M..;t~~

:~R ~~~ULATION,
IMon=1I1Hz,

-50

I I

-60

0.3~ 3~

'd~'\

r

J.~HResHDLD

30~ 300~ 3m

~

'"

.£!
2

r-r"'...r-r-r--r-~""""

r- r-

30
20

1

10

I IGAi N 1\

SIN FOR

VGEN =10 ~V

30m 300m

0.53

TLlH/5185-12

0.73 0.93

1.13

CROSS MODULATION

~

-;:; 100 mV
~

L~O~

30 mV

looo..,.==F----l----i

10 mV

L-_ _..L_ _-'-_ _- '

1.33 1.53

Vs10kHZ

1 mV

CENTER FREQUENCY (MHz)

1fT

50

~

Cross modulation is

measured using the
following dummy an~
tenna:
...._t--.TO GATE
OF01
;,;82 pF

-1-,

VGEN11~5~

3 mV

10mV

30 mV

VGENI (Vrms)
TL/H/5185-14

TL/H/5185-13

VGENI < t p , , 7 ' 5

530 kHz

-~

v

300 mV

>

1

-1~ tjtt:t:t~:E:r:t:~~

0

1V

1""'9"'i""'k:-t-++-+~~i~TION

90
BO~-r~~~~~-r~
70 HH-t-+++-+-f"'Nid
60~-r~~~4-~~~
50 r- r- NORMALIZED
~
:!!.
40
SYSTEM

The following procedure was used to measure cross modulation:
1. Tune the radio to the center frequency of Interest and

~une

VGEN. to this same frequency.

2. Set at 0 dB audio reference with VGEN. = 10 mV RMS and 30% AM mod; fMOD = 1 kHz.

3. Remove the modulation from VGEN1 and set the level of VGEN1'
4. Set the modulation level of VGEN2 = 80% at fMOD = 1 kHz and tune VGEN2 ± 40 kHz away from
center frequency.

5. Increase the level of VGEN2 until -40 dB of audio Is recovered. The level of VGEN2 is the cross
modulation measurement.

J,J:

TLlH/5185-15

Additional Performance Information:
• THO for 80% modulation for fMOD= 1 kHZ at:
VGEN = 1V is 0.5%

~ -10 f-t-t-t-t--t-+~~:-l-H
~~ -20

,

VGEN=10 mV is 0.4%
oil

f-t-t-t-t--t--t--t'-\l-H

~ -30

r-t-t-t-t-t-+--+-++-l

-40

HH-+-+-++-+-++-l

-50 L......L.....!.......L.-L-.!..-L-...I-L....!......I
31
125 500
2k
Bk
10k

MODULATION FREOUENCY (Hz)
TL/H/5185-16

Tweet <2% at all input levels.

'" Typical time for valid stop indication < 50 ms.

Note: Tweet is an audio tone produced by the 2nd and 3rd harmonic of the IF beating against the received
signal. It is measured as an equivalent modulation level: ie, 30% tweet has the same amplitude at the
detector as a desired signal with 30% modulation.

EI

2-15

IC External Components (See Application Circuit)
Component

Typical Value

Cl

2.2J.'F

Comments
Sets dominant AGC pole, affects stop time
and THO.

C2

1 J.'F

Sets non-dominant AGC pole, affects stop
time and THO.

C3

0.33 J.'F

Stop level threshold decoupling, affects
stop time and sensitivity of stop detector to
large modulation peaks.

C4

10 J.'F

Supply decoupling, low frequency.

C5

0.1 J.'F

Supply decoupling, high frequency.

C6

1 J.'F

C7

0.005 J.'F

IF decouple, affects IF gain.
Audio output filter, removes IF ripple from
detector.
Regulator decouple, low frequency.

C8

10 J.'F

C9

0.1 J.'F

Regulator decouple, high frequency.

Cl0

470 pF

Pad capacitor for varactor, affects tracking.

Cll

2J.'F

C12

0.33 J.'F

C14

0.1 J.'F

C19

0.001 J.'F

RF AGC decouple, affects stop time and
THO.
RF AGC high frequency decouple.
Local oscillator output coupling.
Sets gain at high end of AM band.

C26

0.005 J.'F

Sets gain at low end of AM band.

C28

0.01 J.'F

Couples RF stage output to mixer input,
keep small to insure proper stop time
performance when RF AGC is active.

Rl

300k Pot.

R2

12k

Sets size of stop window.

R3

50k

Open collector pull up resistor.

Sets level stop threshold.

R4

lk3

IF filter termination, and gain set.

R5

10k

Sets RC time constant on audio outputs,
smaller values may cause distortion of high
frequencies.

R6

200k

Sets gain of IF stage, affects noise floor and
sensitivity.

R7

Meter Oependent

R8

lOOk

Sets gain and threshold of RF AGC.

R9

lOOn

Aids mixer output decoupling.

R19

10k

R21

1.2Mn

Sets full-scale deflection of meter.

Sets 2'nd pole in RF AGC, affects THO for
large input signals.
Biases pin 5 to 0.4 volts which permits
shorter stop time.

R24

820n

Sets system gain.

01,02,03,

TOKO
KV1235Z or
Equivalent

Varactor diodes.

Resonator

450 kHz ± 1 kHz
Murata', BFU450C4N

IF filter

MurataCFU450F5

Parallel type resonator.
Sets selectivity and tone response.

*Murata
2200 Lake Park Drive
Smyrna. GA 30080
(404) 436-1300

2-16

Performance Characteristics of Applications Circuit (Continued)
Part No. 5MFC-A087YRT
TOKO

Part No. 7TRS-A5610CI
TOKO

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TL/H/5185-17

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Center Frequency

TL/H/5185-18

2 MHz

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TL/H/5185-20

TL/H/5185-19

Center Frequency

=

Center Frequency

450 kHz

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450 kHz

au > 100 at 450 kHz

au> 100 at 450 kHz

Part No. 7TRS-A5609AO
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TL/H/5185-21

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Layout Considerations
Although the pinout of the LM1863 has been chosen to minimize layout problems, some care is required to insure proper performance. If the LM1863 is used with a loopstick antenna, care in the placement of C3 must be observed in
order to minimize tweet radiation. Orient C3 parallel to the
axis of the loopstick and as far away as possible. Keep C3
close to the IC. The ground on C6 should be located near
the ground terminal of the 450 kHz ceramic filter. C11
should be located near Q2 and C12 should be located near
the IC. Also, the resonator on Pin 7 and resistor R2 should
be located near the IC in order to minimize tweet radiation.

The mixer output, Pin 10 and the IF input, Pin 11, traces
should be as short as possible to prevent stray pick up from
the resonator.

Applications Information
(See typical application and LM1863 schematic diagram.)

STOP DETECTOR
There are two criteria that determine when an electronically
tuned radio is tuned to a valid station. The first criterion is
that the incoming signal be of sufficient strength to be listenable. The second criterion requires that the radio be tuned

PC Layout (Component Side)

TL/H/5185-22

2-18

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.....

Applications Information

(Continued)
to the center frequency of the incoming station. Both the
signal strength threshold and the center tune window are
externally adjustable.
The signal strength threshold is set by resistor R1. Increasing the value of this resistor will reduce the signal level
threshold. There is no difficulty in setting the signal strength
threshold, either above or below the AGC threshold.
Resistor R2 sets the center tune window. The incoming station is considered to be center tuned whenever the frequency of the signal at the IF output falls within the center tune
window. Increasing the value of R2 will narrow the window,
while decreasing R2 will widen the window. Since there is
some interaction between R2 and R1, R2 should be chosen
before R1. In the United States, stations within the AM band
are spaced no closer than 10kHz apart. Consequently, the
controller should be set up to stop every 10kHz within the
AM band when the ETR is in scan mode. A center tune
window anywhere less than ± 10kHz is therefore adequate
in determining the center tune condition, though a narrower
stop window is desirable in order to minimize the chance
that side bands from a strong adjacent channel will fall within the stop window.
Because of asymmetry in the resonator amplitude characteristic, the center tune stop window will not be symmetric
about the center frequency of the resonator. This is not a
problam as long as the stop window brackets the center
frequency of the IF and does not extend into the next channal. However, in order to avoid any problems in this regard it
is recommended that the resonator center frequency deviate no more than ± 1 kHz from the center frequency of the
IF.
The stop output, Pin 9, is an open collector NPN transistor.
This output must be taken to a positive voltage through a
load resistor, R3. A valid stop condition is indicated by a
high output level on Pin 9 (i.a., the NPN is turned off). The
voltage on this pin should not exceed 16 volts.

The addition of a second pole to the AGC response does
add some ringing to the AGC voltage following signal transients. The frequency, duration and amount of ringing are
dependent on where both AGC poles are placed and to
some extent the input signal conditions. The amount of ringing should be kept to a minimum in order to insure proper
stop indications. The amount of ringing can be reduced by
either reducing C2 (this will increase THO) or by increasing
C1 (this will improve THO but increase stop time).

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If the ratio of C1/C2 is made too small, an increase in low
frequency noise may be noticed resulting from the peaking
that a closed loop two pole system exhibits near the unity
gain frequency. The extent of this peaking can be observed
by examining the amount of recovered audio at various low
fraquency modulations. In general, the values shown reach
a good compromise between THO, stop time, ringing and
low frequency noise.
The center tuning detector on the LM1863 passes the signal at the IF output through a limiting amplifier which removes most of the modulation from the IF waveform. The
output of this limiter is then applied to the resonator on Pin
7. Unfortunately, large modulation peaks are not completely
removed by the limiting amplifier. Without C3, these large
modulation peaks would cause glitches on the stop output
when the LM1863 was tuned to a valid station. C3 acts to
reduce these glitches by filtering the output of the center
tune circuit. C3, however, also affects the stop time and
cannot be made arbitrarily large. A time constant of about
30 ms on Pin 5 gives the best compromise. R21 biases Pin
5 to about .4 volts, which is below the stop threshold at this
point. This biasing rasults in a shorter stop time.
Extra precaution can be taken within the software of the
controller IC to further insure accurate stop detector performance over a wide variety of input signal conditions. A
typical controller IC stop algOrithm is as follows:
The controller waits the first 10 ms after the LM1863 is
tuned to the next channel. The controller then samples
the LM1863 stop output 10 times within the next 40 ms.
If no high output is sensed within that time the controller concludes there is no valid station at the frequency
and moves to the next channel. If, however, at least
one high output is detected within the first 50 ms the
controller waits an additional 200 ms and at the end of
that time re-samples the stop output in order to make
its final stop determination.

STOP DETECTOR STOP TIME

The amount of time required for the LM1863 to output an
accurate stop indication on Pin 9 is defined as the stop time.
The stop time determines how quickly the ETR can scan
across the AM band. There are several factors that influence the stop time. Since the signal level stop function operates in conjunction with the Automatic Gain Control
(AGC), the AGC settling time is a critical factor. This settling
time is dominated by the low frequency AGC pole which is
set by C1 and internal IC resistances. Decreasing C1 will
decrease tha AGC settling time but increase total harmonic
distortion, THO, of the recovered audio. A good compromise
between AGC settling time and THO is very difficult to reach
with a Single pole AGC system. Consequently, the LM1863
has been deSigned with a second, higher frequency, AGC
pole. This non-dominant pole is externally set by capacitor
C2. As a result, C1 can be made much smaller than it otherwise could for an equivalent amount of THO. Reducing C1
will reduce the stop time. The combination of C1 and C2 as
shown in tha applications circuit results in a stop time of less
than 50 ms for most input conditions, while at the same time
the circuit achieves .9% THO at 80% modulation with 400
Hz modulation frequency at 10 mV input signal strength.
Had C2 not been present the stop time would still be 50 ms
but the THO for similar input conditions would be 8%. By
decreasing both C1 and C2 (keeping the ratio of C1/C2
constant) the stop time can be reduced at the axpense of
THO, while the converse is also true.

RFAGC
The RF AGC detector is designed to control the gain of an
external RF amplifier which is placed between the antenna
and the mixer input. The RF AGC operates by detecting
when the input Signal to the mixar reaches 6 mVrms, the RF
AGC threshold. When the mixer input signal reaches this
level the RF AGC is activated and will hold the mixer input
level relatively constant at the level of the RF AGC threshold. The gain of the RF AGC determines how constant the
RF AGC can control the RF output. The LM1863 RF AGC is
high gain and consequently the RF AGC output, Pin 3, will
transition from high to low over a very narrow input range to
the mixer when the LM1863 is examined in an OPEN LOOP
condition. However, in a radio where the RF AGC controls
the RF gain, a CLOSED LOOP negative feedback system is
established. In this application the RF AGC output will transition from high to low over a large range of Signal levels to
the input of the RF stage.

2-19

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.--------------------------------------------------------------------,
Applications Information

(Continued)

The RF AGC threshold has been carefully chosen to prevent overloading the mixer, which would cause distortion
and tweet problems. However, the threshold level is sufficiently large to minimize the possibility of strong adjacent
stations de-sensitizing the radio by activating the RF AGC
and thereby gain reducing the RF front end.

signal level at the IF input. Noise sources at the IF input
therefore become a larger percentage of the IF input signal
thereby degrading the SIN floor of the radio. For this reason, the LM1863 employs 20 dB of IF AGC. The IF gain of
the LM1863 is adjustable by changing the tap across the IF
ouput coil, or by changing the ratio of R24 to R4.

The RF AGC output, Pin 3, is an open collector NPN transistor. This collector must be tied to a positive voltage through
a load resistor, R8. Furthermore, decoupling is required
(Cll and C12) in order to insure that the RF AGC does not
induce significant distortion in the recovered audio. However, the tradeoff between good THD performance and fast
stop time is not too severe for the RF AGC because large
changes in the RF AGC level are unlikely when' moving between adjacent channels. This is because the selectivity in
the RF stage is not great enough to cause abrupt signal
level changes at the mixer input as the radio is tuned. Thus,
since the RF AGC does not have to follow abrupt signal
level changes, the time constant on the AGC output can be
relatively long which allows for good THD performance. C12
is required in order to insure good RF decoupling of signals
at the RF AGC output, and sets the non-dominant pole.
The RF AGC 10 /LA threshold is fixed at 6 mVrms at the
mixer input. However, due to the gain of the RF stage and
losses through the RF transformers, this level may be different when referenced to the antenna input. For the application circuit shown the RF threshold occurs at 2 mVrms at
the dummy antenna input. Thus, the RF AGC threshold can
effectively be adjusted by altering the gain of the RF stage.
The value of R8 also has some affect on the RF AGC
threshold of the application circuit. Smaller values will tend
to increase the threshold while larger values will tend to
reduce the threshold.

The gain distribution for the application circuit is as follows:
Gain Distribution

TLIH15185-23
vG = OdB
Vl = -16dB
V2=+10dB
V3=+33dB
vo= +84dB

(lO fLV)
(Pin 20)
(Pin 11)
(Pin 14)

The IF gain could also be varied by changing the value of
R6 across the IF output coil. However, it is a good idea to
maintain a high Q IF tank in order to achieve good adjacent
channel rejection. In order to prevent distortion due to overloading the IF amplifier, it is important that the impedance
Pin 14 sees looking into the IF output tank, T5, does not go
below 3K ohms.
The above gain distribution is prior to any AGC action in the
radio. This distribution represents a good compromise between the various tradeoffs outlined previously.
LEVEL CONTROLLED LOCAL OSCILLATOR
Tracking of the RF varactors with the local oscillator varactor is a serious consideration in order to insure adequate
performance of the ETR radio. Due to non-linear capacitance versus voltage characteristic of the varactor, large
signals across these varactors will tend to modulate their
capacitance and cause tracking problems. This problem is
compounded further if the level of the signals across the
varactors change. In an AM radio, the local oscillator frequency changes a ratio of two to one. The Q of the oscillator tank remains fairly constant over this range. Thus, since
Q = Rp/cvL = Constant, this implies that Rp(Rp = unloaded parallel resistance of the tank) must change two to
one. The internal level-control loop prevents the two to one
change in AC voltage across the tank which the change in
the Rp would otherwise cause.
Phase jitter of the local oscillator is very important in regard
to AM stereo, where L-R information is contained in the
phase of the carrier. Local oscillator jitter has the effect of
modulating the L-R channel with phase noise, thus degrading the stereo signal to noise performance. Great care has
been taken in the design of the LM1863 local oscillator to
insure that phase jitter is a minimum. In fact the dominant
source of phase jitter is the high impedance resistor drive to
the varactor. The thermal noise of the resistor modulates
the varactor voltage, thus causing phase jitter.

GAIN DISTRIBUTION
The purpose of this section is to clarify some of the tradeoffs involved in redistributing gain from one portion of the
radio to another. An AM radio basically has three gain
blocks consisting of the RF stage, the mixer, and the IF
stage. The total gain of these three blocks must be sufficiently large as to insure reception of weak stations. Given
then a fixed amount of required gain how does distributing
this gain among the three blocks affect the radio performance?
Large amounts of gain in the RF stage will have the effect of
decreasing the RF AGC threshold. A decreased RF AGC
threshold means that it is more likely that strong adjacent
stations can activate the RF AGC and desensitize the radio.
Also, a lot of RF gain implies large signals across the RF
varactor diodes, which is undesirable for good tracking and
can result in overloading these varactors which can cause
cross modulation. On the other hand, high RF gain insures
good noise performance and improved THD.
High mixer gain implies large signal swings at the mixer output, especially on AGC transients. These large signal
swings could cause the mixer ouput transistors to saturate
and also could overload the IF stage. On the other hand,
redistributing the gain from the IF to the mixer would improve the noise performance of the radio. The gain of the
mixer can be controlled moving the tap on the mixer output
transformer, T 4.
Since the output signal level of the IF is held constant by the
AGC, increasing gain in the IF has the effect of reducing the

VARACTOR TUNED RF STAGE
Electronically tuned car radios require the use of a tuned RF
stage prior to the mixer. Many of the performance charac-

2-20

.-----------------------------------------------------------------------------'r
Applications information

...

;:

(Continued)

eX)

teristics of the radio are determined by the design of this
stage. Generally speaking it is very difficult to design an
integrated RF stage in bipolar, as bipolar transistors do not
have good overload characteristics. Thus, the RF stage is
usually designed using discrete components. Because of
this there is a great deal of concern with minimizing the
number of discrete components without severely sacrificing
performance. The applications circuit RF stage does just
this.

or performance with respect to varactor overload by strong
adjacent channels. This results because of the way that
gain has been distributed between the 1'st and 2'nd stages.

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In summary, this front end offers two stages of RF gain with
the 2'nd stage acting to gain reduce the 1'st stage when RF
AGC is active. Furthermore, a unique coupling scheme is
employed from the output of the 1'st stage to the input of
the 2'nd stage. This coupling scheme equalizes the gain
from one end of the AM band to the other. Additional care
has been taken to insure that excellent cross modulation
performance, image rejection, signal to noise performance,
overload performance, and low distortion are achieved. Performance characteristics for this front end in conjunction
with the LM1 863 are shown in the data sheet. Also, information with regard to the bandwidth of the front end versus
tuned frequency are given below.

The circuit consists of only two active devices, an N-channel JFET, Q1 , which is connected in a cascode type of configuration with an NPN BJT, Q2. Both Q1 and Q2 are varactor tuned gain stages. Q2 also serves to gain reduce Q1
when Q2's base is pulled low by \he RF AGC circuit on the
LM1863. The gain reduction occurs because Q1 is driven
into a low gain resistive region as its drain voltage is reduced. R10 and C15 set the gain of the 1'st RF stage which
is kept high (about 19 dB) for good low signal, signal/noise
performance. The gain of the front end to the mixer input
referenced to the generator output is about + 10 dB.

TUNED FREQUENCY
530 kHz
600 kHz
1200 kHz
1500 kHz
1630 kHz

T2 in conjunction with 01, C21 and C26 form the 1'st tuned
circuit. C26 does not completely de-couple the RF Signal at
the cathode of the varactor. In fact, the combination of C26
and C19 act to keep the gain of the whole RF stage constant over the entire AM band. Without special care in this
regard the gain variation could be as high as 14 dB. This gain
variation would result from the increase in impedance at the
secondary's of T2 and T1 as the tuned frequency is increased. The increased impedance results from a constant
Q=Rp/(wL) of the tanks over the AM band. With C26 and
C19 the gain is held constant to within 6 dB (including the
tracking error) over the entire AM band.

-3 dB BANDWIDTH
6.6 kHz
7.2 kHz
20.6 kHz
26.4 kHz
36kHz

VARACTOR ALIGNMENT PROCEDURE

The following is a procedure which will allow you to properly
align the RF and local oscillator trim capacitors and coils to
insure proper tracking across the AM band.
1. Set the voltage across the varactors = 1 volt.
2. Set the trimmers to 50%.
3. Adjust the oscillator coil until the local oscillator is at 980
kHz.
4. Increase the varactor voltage until the local oscillator
(LO) is at 2060 kHz and check to see if this voltage is less
than 9.5 volts but greater than 7.5 volts. If it is then the
LO is aligned. If it is not then adjust the LO coil/trimmer
until the varactor voltage falls in this range.

C27 de-couples RF Signal from the top of T2's primary and
allows Q2 to operate properly. C18 is a coupling capacitor
which in conjunction with C19 couples the signal from the
1 'st RF stage to the 2'nd RF stage. R20 acts to isolate this
signal from AC ground at C11. R19 acts in conjunction with
C12 to set a high frequency (ie: non-dominant) RF AGC
pole which is important for low distortion when the RF AGC
is active. The dominant RF AGC pole is set by R8 and C11.
Q2 is a high beta transistor allowing for little voltage drop
across R20 and R8 due to base current. This keeps the
emitter of Q2 sufficiently high (in the absence of RF AGC) to
bias Q1 in its square law region.

5. Set the RF in to 600 kHz and adjust the tuning voltage
until the LO is at 1050 kHz. Peak all RF coils for maximum recovered audio at low input levels.
6. Set RF in to 1500 kHz and adjust the tuning voltage until
the LO is at 1950 kHz. Peak all RF trim capacitors for
maximum recovered audio at low input levels.
7. Go back to step 5 and iterate for best adjustment.

R13 acts to reduce the 2'nd stage gain and increase Q2's
signal handling. R13 must not get too large, however, (ie:
R13>100 0), or low level Signal/noise will be degraded. T3
in conjunction with C20, C27 and 02 form the 2'nd RF tuned
circuit. The output of Q2 is capacitively coupled through C28
to the mixer input. The output of Q2 is loaded not only by
the reflected secondary impedance but also by R22. R22 is
carefully chosen to load the 2'nd stage tuned circuit and
broaden its bandwidth. The increased bandwidth of the 2'nd
stage greatly improves the cross modulation performance of
the front end. In the absence of this increased bandwidth,
the relatively large AC Signals across varactor 02 result in
cross modulation. R22 also reduces the total gain of the
2'nd stage. R22 does slightly degrade (by about 6 dB) the
image rejection especially at the high end of the AM band.
However, the image rejection of this front end is still excellent and 6 dB is a small price to pay for the greatly increased
immuni\y to cross modulation.

8. Check the radio gain at 530 kHz and 750 kHz to make
sure that the gain is about the same at these two frequencys. If it is not, then slightly adjust the RF coils until
it is.
The above procedure will insure perfect tracking at 600 kHz,
950 kHz and 1500 kHz. The amount of gain variation across
the AM band using the above procedure should not exceed
6 dB.
ADDITIONAL INFORMATION

R5 and C7 act as a low pass filter to remove most of the
residual 450 kHz IF Signal from the audio output. Some residual 450 kHz signal is still present, however, and may
need to be further removed prior to audio amplification. This
need becomes more important when the LM 1863 is used in
conjunction with a loopstick antenna which might pick up an
amplified 450 kHz signal. An additional pole can be added
to the audio output after R5 and C7 prior to audio amplification if further reduction of the 450 kHz component is required.

R16 and C29 decouple unwanted signals on V+ from being
coupled into the RF stage. This front end also offers superi2-21

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LM1865/LM1965/LM2065 Advanced FM IF System
General Description
Reduced external component cost, improved performance,
and additonal functions are key features to the LM1865/
LM1965/LM2065 FM IF system. The LM1865 and LM2065
are designed for use in electronically tuned radio applications. These versions contain both deviation and signal level
stop circuitry in addition to an open-collector stop output.
The LM1865 and LM2065 differ only in the direction of the
AGe output voltage they generate on pin 18. The LM1865
generates a reverse AGe voltage (ie: decreasing AGe voltage with increasing signal) and the LM2065 generates a
forward AGe voltage (ie: increasing AGe voltage with increasing signal.) The LM1965 has a reverse AGe characteristic. The LM1965 is designed for use in manually tuned
radios and provides a deviation and signal level mute function in addition to a pin that disables the mute function when
grounded. All three versions are offered in both 20 pin D.I.P.
and S.O. packages.

Features
II On-chip buffer to provide gain and terminate two ce-

ramic filters

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II Low distortion 0.1 % typical with a single tuned quadrature coil for 100% modulation.
II Broad off frequency distortion characteristic
II Low THD at minimum AFT offset

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II Meter output proportional to signal level
II Mute function with mute disable and soft deviation

mute for LM1965
II Stop detector with open-collector output for LM 1865/
LM2065
II Adjustable signal level mute/stop threshold, controlled

either by ultrasonic noise in the recovered audio or by
the meter output
II Adjustable deviation mute/stop threshold
II Separate time constants for signal level and deviation

mute/stop
II Dual threshold AGe eliminates need for local/distance

switch and offers improved immunity from third order intermodulation products due to tuner overload
iii User control of both AGe thresholds
.. Excellent signal to noise ratio, AM rejection and system
limiting sensitivity

Block Diagram

v+

BUFFER
BUF
DECOUPLE OUT

IF
IN

IF
DECOUPLE

10

11

IF
OUT

COIL

0iiA0---

AFT OUT AND

DEVIATION MUTE/STOP
WINDOW ADJUST

fI

WIOEBAND~
AGC IN

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BAND
THRESHOLD
ADJUST

AGC
METER
OUT_ OUT_
18

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13

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MUTE/STOP
FILTE.!!.. _ _ _ _

MUTE DISABLE (LMI965)

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STOP!!!T!:!!!.(~86~L~6s.LJ

16

I

Order Number LM1865N,
LM1965N or LM2065N
See NS Package Number N20A
TL/HI7509-1

FIGURE 1
2-23

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Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, Pin 17

Soldering Information
Dual-In-Line Package
Soldering (10 seconds)
Small Outline Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

16V

Package Dissipation (Note 1)

2.0W
-55·Cto + 150·C

II)

Storage Temperature Range

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Operating Temperature Range

....I

Max Voltage on Pin 16 (Stop Output)
for LM1865, LM2065

260·C
215·C
2200C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

-20·Cto +85·C
16V

Electrical Characteristics
Test Circuit, TA

=

25·C, V+

= 12V; SI

in position 2; S2 in position 1; and S3 in position 2 unless indicated otherwise

Parameter

Conditions

I

IMinlTyplMaxl Units

STATIC CHARACTERISTICS
Supply Current

33

Pin 9, Regulator Voltage

5.7

Operating Voltage Range

(See Note 2)

7.3

=

Pin 18, Output Leakage Current

Pin 20 Open, VIF

Pin 16, Stop Low Output Voltage (LM1865 Only)

SI in Position I, S2 in Position 3

Pin 16, Stop High Output Leakage Current
(LM1865 Only)

S2 in Position 2, V14

rnA

16

V

V

0.1

0, S3 in Position 1

=

45

V9

Pin 15, Audio Output Resistance

p,A

0.3

V

0.1

p,A

4.7

kn

Pin I, Buffer Input Resistance

Measured at DC

350

n

Pin 3, Buffer Output Resistance

Measured at DC

350

n

Pin 20, Wide Band Input Resistance

Measured at DC

2

n

1

kn

Pin 8, Meter Output Resistance
DYNAMIC CHARACTERISTICS fMOD

=

400 Hz, fo

=

10.7 MHz, Deviation

-3 dB Limiting Sensitivity

IF Only (See Note 3)

Buffer Voltage Gain

VIN Pin 1

Recovered Audio

VIF

Signal-to-Noise

Minimum Total Harmonic Distortion

=

±75 kHz

10 mVrms at 10.7 MHz

= 10 mVrms, V14 = V9
VIF = 10 mVrms, V14 = V9 (See Note 4)
V14 = V9
VIF = 1 mV, 30% AM Mod
VIF = 10 mV, 30% AM Mod
VIF = 10mV
VIF = 10 mV, Tune until V14 = V9

AM Rejection

THD at Frequency where V14
(Zero AFT Offset)

=

=

V9

=

=

60

120

19

22

25

p,Vrms
dB

275

320

470

mVrms

70

84

dB

50
50

60
60

dB
dB

0.1

0.35

%

0.1

0.45

%

0.15

%

AFT Offset Frequency for Deviation Mute
(LM1965 Only)

VIF = 10 mV, Audio = -3 dB, S2 in Position 4
Offset = (Frequency for -3 dB Audio) (Frequency where V14 = V9)

±62

kHz

AFT Offset Frequency for Low Stop Output at
Pin 16 (LM1865 and LM2065 Only)

VIF = 10 mV, S2 in Position 3, fMOD = 0
Offset = (Frequency for Pin 16 Low) (Frequency where V14 = V9)

±50

kHz

Ultrasonic Mute/Stop Level Threshold

V14 = V9, SI in Position 3 (See Note 5)
VIF = 10mV
fMOD = 100 kHz
S2 in Position 4 (LMI965)
S2 in Position 3 (LMI865/LM2065)
Amount of Deviation where Audio Mutes (LMI965)
Amount of Deviation where V16 Low
(LM1865, LM2065)

60

kHz

THD ± 10 kHz from FrequencywhereV14

V9

VIF

10mV

2-24

r-

g

-,

Electrical Characteristics
=

Test Circuit, T A
(Continued)

=

25'C, V+

12V; S1 in position 2; S2 in position 1; and S3 in position 2 unless indicated otherwise

Parameter

Min

Conditions

DYNAMIC CHARACTERISTICS IMOD

=

=

400 Hz,lo

Typ

Units

mV

U'I
......

=

Amount 01 Muting (LM1965 Only)

S2 in Position 4, S 1 in Position 1, VIF

Amount of Muting with Pin 13 and
Pin 16 Grounded

S1 in Position 1
V14, = V9, VIF = 10 mV

Narrow Band AGC Threshold

Increase IF Input until I AGC = 0.1 mA
Pin 20 = 30 mVrms (See Note 6)

Wide Band AGC Threshold

VIF = 100 mVrms
Increase Signal to Pin 20 untillAGC
(See Note 6)

=

220

g

en
U'I

10 mV

66

dB

0

dB

100

210

300

/LVrms

5

12

22

mVrms

0.5

V

0.1 mA

VIN Pin 20

=

100 mY, VIF

=

100 mVrms

0.2

Pin 18, High Output Voltage (LM2065 only)

VIN Pin 20

=

100 mY, VIF

=

100 mVrms, (See Note 6)

11.7

V

Pin 8, Meter Output Voltage

VIF
VIF
VIF

0.1
1.1
2.6

V
V
V

~

Note 1: Above TA

25'C derate based on TJ(max)

~

10 /LV
300/LV
3mV

1500C and 9JA

~

rN
0

Pin 18, Low Output Voltage
(LM1865 and LM1965 only)

=
=
=

.....
CD
en

V14 = V9, S1 in Position 4
S2 in Position 4 (LM1965)
S2 in Position 3 (LM 1865, LM2065)
V13 where Audio Mutes (LM1965)
V13 where V16 -+ Low (LM1865, LM2065)

Pin 13 Mute/Stop Threshold Voltage

Max

= ± 75 kHz (Continued)

10.7 MHz, Deviation

co

en

U'I
......
rg

600C/W.

Note 2: All data sheet specifications are for V+ ~ 12V may change slightly with supply.
Note 3: When the

IF is preceded by 22 dB gain in the buffer, excellent system sensitivity is achieved.

Note 4: Measured with a notch at 60 Hz and 20 Hz to 100 kHz bandwidth.
Note 5: FM modulate RF source with a 100 kHz audio signal and find what modulation level, expressed as kHz deviation, results in audio mute for the LM1965 or
V16 --+ 12V for the LM1865/LM2065.
Note 6: 53 in Position 3 for LM2065.

Test Circuit

_~2~

~m~ f-cu:~~~

11k

~

:i.~

;-

I2V

cu:~~

"

C~~~T

5"f

5kl

~IF·~--~/'r---------~~---.

2

'-=~': J:rtJ: dr'*1J/~~
.,J;jr .!h
WIDE
BANO
AGe
BUfFER
IHPUT

BUFFER
GROUND

AGe

V'

,ur

I. .." I. }]. ~ ·

StOP OUT
(lM18&5, LM2D65)

BUFFER
OUT

IF
DECOUPLE

IF
IN
5

our

l"

MUTE/STOP

33'

FILTER

COil

THRESHOLD

IF
DECOUPLE

PDWER
GROUND

..l!

6

:rlQ·OI"~'·OI"t-1!."
'.01.' T,·m., r-f
J.,

!h
.:r' LEV:~ MU"~P Qu"'.~:---+-r"'1'"eBTH""-I/V\-"'-"'..,

AUDID

MUTE DISABLE
(lM1965)
BUFFER
DECOUPLE

EI

TOO'"I"""

METER

"' )'~

*VIf

8

'Ok

r.7
FIGURE 2
2-25

IF
VREG
OUT
9~...l!!!.

I
I

I
I

L ____ ...J

18"H

,·OI"T ~ ""

TOKD
KAC·K2318HM

U
TL/H/7S09-2

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CD

o

C'II

:5U;

Typical Performance Characteristics (from Test Circuit)

CD

m
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FM Limiting Characteristics
and AM Rejection

::::E

..J

.....

fII

CD
CO

0
frl~ -10
if -20
-30
;~ -40
e.; -50
""Ir -60

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::::E

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10

=

RLooa-3D;

1/

It;

II/'\.

j

/1\
\

,

£=

-70

AMR

o

-90

Ii:

1

10
100
lk
10k
IF INPUT VOLTAGE (pV)

lOOk

% THO vs OFF Tuning
(Single Tuned Quadrature
Coil)

1.2

§:

=

i=

0.8
0.6

I

~

....

100
80

lEe

~~
...
'"
1=

.

t--.. k'"

0

-20 0 20
60
100
AMOUNT OF OFF TUNING (kHz)
(0 CORRESPONDS TO 10.7 MHz)

; +3DD
Ii:

'iii +200

~

'"
t::

"

z

r-- I--

lOOk

~

"'"

'"'" '"

1/

V

35

10k
15k 20k 25k
LOAD RESISTANCE
(8ETWEEN PINS 9 AND 14) (0)

PlN9cu~RE;MEnfl
~,:N14

"J;

I

t::~

-100

~.,

c;
z

J
NoISE

II:

5k

",,,"

3

40

=>

!!i
Uw

it

I

Supply Current vs
Supply Voltage

'"u=>

\

~~ +100
w'"

z~

J

7 8

9 10 11 12 13 14 15 16
PIN 17 SUPPLY VOLTAGE (V)

Pin 14, AFT Current
vsTuning

..

:: i3

.......

10
100
lk
10k
IF INPUT VOLTAGE (pV)

""z

o

n,D+NOISE

~

1

::!

20

-60

,

1/

C

40

III 0
."

I

.!!.

60

Zen

!~
:$ z

/

0.2

~~

w=>
5~

/

V

45

I

fi 120

l3-

11

\

0.4

0.04
-100

I

QouAo=17

~

-60
-70
-80
-90

Deviation Mute/Stop
Threshold as a Function of
AFT Load Resistor
9-;:;

1\

~i
l!i

10 100
lk 10k lOOk
IF INPUT VOLTAGE (pV)

140

1.6
1.4

~~

/V
1

AUDIO

"'>I'

=8 -40
;;; -50

/

NOISE

10

~g -20
III lE -30

If

/

1

I"

~c -80

z

=

,r

FM Limiting Characteristics
+ THO

iii>_ 0
fd! -10

AUDIO

~_

~g

Pin 8, Meter Output Voltage
vs IF Input Level

-200

~ -30~100

.....

7~-

V

V

-60

-20 0 20

60

100

AMOUNT OF OFF TUNING (kHz)
(0 CORRESPONDS TO 10.7 MHz)
TL/H17509-3

Coils and ceramic filters are available from:
TokoAmerica

Murata

1250 Feehanville Drive

2200 Lake Park Drive

Mount Prospect, IL 60056

Smyrna, GA 30060

(312) 297-0070

(404) 436-1300

2-26

riii:

Application Circuit

-0.

CD

en
CJ1

.......
riii:
-0.

5V

CD

en

810

I,.

TQTU:~~

CJ1
.......
r
iii:
I\)

(LM1865AND LM21165
ONLY)

+-__--1_--'

___

V'

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CJ1
R5
5k1

TOKO
iCAC-K2138HM

'"
TOo1~: +-_0._01,;.."-+

+ C7

~

. '"

TLlHI7S09-4

FIGURE 3

IC External Components (See Application Circuit)
Component
C1
C2
C3,C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
R1
R2, R3
R4
R5
R6
R7
R8
R9

R10
R11
R12
R13
L1

T1

Typical Value
0.01 fLF
0.01 fLF
0.01 fLF
10 fLF
0.01 fLF
50 fLF
2.2 fLF
5 fLF
0.1 fLF
0.01 fLF
25 fLF
0.01 fLF
Tuner Dependent
Tuner Dependent
Meter Dependent
5k1
25k
5k
10k Pot
12k

10k
50k
3k9
620
18 fLH Qu>50 @ 10.7 MHz
TDK Electronics
TP041 0-180K or equivalent
QU>70@ 10.7 MHz, L to
,
resonate w/82 pF @ 10.7 MHz
14' .. ,F TOKO KAC-K2318HM or
equivalent

O

Comments
AC coupling for wide band AGC input
Buffer and AGC supply decoupling
IF decoupling capacitors
Meter decoupling capacitor
AC coupling for IF output
Regulator decoupling capacitor, affects SIN floor
Level mute/stop time constant
AFT decoupling, affects stop time
Disables noise mute/stop
AC coupling for noise mute/stop threshold adjust
Supply decoupling
AGC output decoupling capacitor
Wide band AGC threshold adjust
Gain set and bias for IF; R2 + R3 = 3300 to terminate ceramic filter
Sets full-scale on meter
Deviation mute/stop window adjustment
Mute/stop filter, affects stop time
Level mute/stop threshold adjustment
Level mute/stop threshold adjustment
Noise mute/stop threshold adjustment, decrease resistor for lower
SIN at threshold, for optimum performance over temp. and gain variation, set this resistor value so that the signal level mute/stop threshold
occurs in the radio at 45dB SIN (± 3 dB) in mono.
Load for open-collector stop output
AGC output load resistor for open-collector output
Sets Q of quadrature coil affecting THO, SIN and recovered audio
Optimises minimum THO
Sets signal swing across quadrature coil, High Q is important to minimize effect variation of Q has on both minimum THO and AFT offset.
10.7 MHz quadrature coil: QUL > 70

TLIHI7S09-S

CF1,CF2

Murata SFE1 O. 7ML or equivalent

10.7 MHz ceramic resonators provide selectivity; good group delay
characteristics important for low THO of system
2-27

fI

U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

~
:i
N

....I

.....
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CD

....

Q)

:i

Typical Application
LAYOUT CONSIDERATIONS
Although the pinout of the LM1865/LM1965/LM2065 has
been chosen to minimize layout problems, some care is required to insure stability. The ground terminal on CF1

should return to both the input signal ground and the buffer
ground, pin 19. The ground terminal on CF2 should return to
the ground side of C4. The quadrature coil T1 and inductor
L1 should be separated from the input circuitry as far as
possible .

....I

;.r;

PC Layout (Component Side)

CD

CO
....

:i
....I

TL/H/7509-6

PERFORMANCE CHARACTERISTICS OF TYPICAL
APPLICATION WITH TUNER

5.5 dB noise figure, and 30 dB of AGC range. The tuner was
driven from a 500. source. 75 /-'S of de-emphasis was used
on the audio output, pin 15. The 0 dB reference is for ± 75
kHz deviation at 400 Hz modulation.

The following data was taken using the typical application
circuit in conjunction with an FM tuner with 43 dB of gain, a
Meter Output and
Signal-to-Noise
vs Tuner Input
10

ffi
ffi

~;

AUDIOldBl

0

if g -20 ~
-10

Hi :IS -3~ 3V
a:;f!
mg -40

f
\

>-Ie

~~ -60
=:::::t -70 1V
-80

~

-90

METER

'I

OlTSI

; ' ; -50 2V

;<

,r-

\ f

I

Total Harmonic Distortion vs
Tuner Input

/:
.-

' - - I---

NOIJe IF NARROW BAND

lOOP IS ACTUATED

\ . - r-.... '/::::E~~~LD
/ "'\i NOise ''''

,"-

/
./ ,-

WIDE BAND
AGC THRESHOLD

10 100 lk 10k lOOk 100Dk
TUNER INPUT (~VI

0.1

fa
ffi

10
0

~~-10

~g -20
~: -30
!9 g -40
e;;; -50
>-Ii!
212 Ct -60
>-is
~a -70

.
z

Ii:

AUDIO

L

mB!
~g

~=

\\

'MOO =400 Hz

1"-

-THO+NDlSE

N~'SE

-80
-90

10 100 lk 10k lOOk 100Dk
TUNER INPUT (~VI

10

AUDIO

0
-10
-20

~

-30
-40
-50
-60
-70
-80

Ii:

-so

!g ~

~

0.1

.,

;-~
~~

is ~
z

AM Rejection vs Tuner
Input

L

l\

1\'

"- :\

'\I

0.1

AM (30% MODI

~

\

l~blSE

10 100 lk 10k lOOk lDDOk
TUNER INPUT (~VI
TLlHI7509-7

-3 dB limiting = 0.9,.V
30 dB quieting

=

1.4,.V

Level stop/mute threshold

= 1.4,.V

Deviation mute window (-3 dBI = ±45 kHz

2-28

r-----------------------------------------------------------------------------~r

is:

Application Notes

-"

sponds to a weaker signal at the antenna of the radio. In
choosing the correct value for R9 it is important to make
sure that recovered audio below 75 kHz is not sufficient to
cause mute/stop action. This is because stereo and SCA
information are contained in the audio signal up to 75 kHz.
Also note that the ultrasonic mute/stop circuit will not operate properly unless a tuner is connected to the IF. This is
because, at low signal levels, the noise at the tuner output
dominates any noise sources in the IC. Consequently, driving the IC directly with a 50n generator is much less noisy
than driving the IC with a tuner and therefore not realistic.
The RC filter on pin 12 not only filters out noise from the
comparator output but controls the "feel" when manually
tuning. For example, a very long time constant will cause
the mute to remain active if you rapidly tune through valid
strong stations and will only release the mute if you slowly
tune to a valid station. Conversely, a short time constant will
allow the mute to kick in and out as one tunes rapidly
through valid stations.
The advantage in using the noise mute/stop approach versus the meter driven approach is that the point at which
mute/stop action occurs is directly related to the signal-tonoise ratio in the recovered audio. Furthermore, the mute/
stop threshold is not subject to production and temperature
variations in the meter output voltage at low signal levels,
and thus might be able to be set without a production adjustment of the radio. The noise mute/stop threshold is very
insensitive to temperature and gain variations. Proper operation of this circuit requires that the signal level mute/stop
threshold be set at a signal level that achieves 45 dB SIN
(± 3 dB) in mono. in a radio. In an electronically tuned radio,
the signal level stop threshold can be set to a much larger
level by gain reducing the tuner (ie. pulling the AGC line) in
scan mode and then releasing the AGC once the radio
stops on a station. In an environment where temperature
variations are minimal and manual adjustment of the Signal
level mute/stop threshold is desired, then the meter driven
approach is the best alternative.

ADJUSTABLE MUTE/STOP THRESHOLD

The threshold adjustments for the mute and stop functions
are controlled by the same pins. Thus, the term mute/stop
will be used to designate either function.
The adjustable mute/stop threshold in the LM1865/
LM1965/LM2065 allows for user programming of the signal
level at which muting or stop indication takes place. The
adjustment can be made in two mutually exclusive ways.
The first way is to take a voltage divider from the meter
output (pin 8) to the off channel mute input (pin 13). When
the voltage at pin 13 falls below 0.22V, an internal comparator is tripped causing muted or causing the stop output to go
low. Adjustment of the voltage divider ratio changes the signal level at which this happens.
The second method of mute/stop detection as a function of
signal level is to use the presence of ultrasonic noise in the
recovered audio to trip the internal comparator. As the signal level at the antenna of the radio drops, the amount of
noise in the recovered audio, both audible and ultrasonic,
increases.
The recovered audio is internally coupled through a high
pass filter to pin 13 which is internally biased above the
comparator trip point. Large negative-going noise spikes will
drive pin 13 below the comparator trip point and cause
mute/stop action. A simplified circuit is shown in Figure 4.
Since the input to the comparator is noise, the output of the
comparator is noise. Consequently, a mute/stop filter on pin
12 is required to convert output noise spikes to an average
DC value. This filter is not necessary if pin 13 is driven from
the meter.
Adjustment of the mute/stop threshold in the noise mode is
accomplished by adjusting the pole of the high pass filter
coupled to the comparator input. This is done with a series
capacitor/resistor combination, R9 C11, from pin 13 to
ground. As the pole is moved higher in frequency (i.e., R9
gets smaller) more ultrasonic noise is required in the recovered audio in order to initiate mute/ stop action. This corre-

I

50k

I

+

I
I

-:J;

I

o.35V

I
I
'HIGH FOR MUTE OR I
STOP OUTPUT LOW I

I

IL _ _ _ _ _

TLlHI7509-B

FIGURE 4. Simplified Level Mute/Stop Circuit

2-29

00
CJ)

UI
.......

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is:

-"

CD

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Application Notes (Continued)
0.6V. The voltage at pin 12 follows an exponential decay
with RC time constant given by R6 CB. For example if R6 =
25k and CB = 2.2 jJ.F the stop time is given by

DEVIATION MUTE/STOP
As with the LM3189, the resistor connected between VREG
(pin 9) and the AFT (pin 14) sets the deviation mute/stop
window (see Typical Performance Characteristics). The
LM1965 was designed with a soft deviation mute. This
means that the audio is gradually muted as you off tune
from center frequency. Gradually muting avoids the problem
of an audio pop which would otherwise occur due to the
unavoidable OC voltage shift at the audio output that accompanies the muting action. Capacitor C9 on the AFT pin
sets the time constant for the deviation mute/stop independent of the level mute/ stop time constant. C9 should be
large enough to remove the audio from the AFT. The AFT
pulls high at low signal levels if the IF is driven directly from
a 500 generator and not a tuner. This is a result of a loss of
signal across the quad coil and a resulting phase shift in the
quadrature detector. This phase shift offsets the AFT. With
a tuner and sufficient IF gain, at low signal levels there will
be enough noise across the quad coil to prevent much of
this AFT shift. Thus, care should be taken when adjusting
the IF gain (which is done by adjusting the ratio of R3 to R2)
to minimize the AFT shift. Grounding pin 16 on the LM1965
will disable the mute function.

t = - (24k) (2.2 jJ.F)

t

0.6)
n ( O.B

which yields t = 15 ms. It should be noted that the 0.6V
threshold at pin 12 has a high temperature dependence and
can move as much as 100 mV in either direction.
Signal Level Stop Using the Meter Output, Pin 8
As mentioned previously, R6 C8 is not necessary when the
meter output is used to drive pin 13. Consequently, this time
constant is not a factor in determining the stop time. However, the speed at which the meter voltage can move may
become important in this regard. This speed is a function of
the resistive load on pin B and filter capacitance, C5.
AGC Time Constant
In tuning from a strong station to a weaker station above the
level stop threshold, the AGe voltage will move in order to
try to maintain a constant tuner output. The AGC voltage
must move sufficiently fast so that the tuner is gain increased to the point that the level stop indicates a valid
station. This time constant is controlled by R11 and C13.

STOP TIME
An electronically tuned radio (ETR) pauses at fixed intervals
across the FM band and awaits the stop indication from the
LM1B65/LM2065. If within a predetermined period of time,
no stop indication is forthcoming, the controller circuit concludes that there is no valid station at that frequency and
will tune to the next interval. There are several time constants that can affect the amount of time it takes the
LM1 B65/LM2065 to output a valid stop indication on pin 16.
In this section each time constant will be discussed.

DISTORTION COMPENSATION CIRCUIT
The quadrature detector of the LM1865/LM1965/LM2065
has been designed with a special circuit that compensates
for distortion generated by the non-linear phase characteristic of the quadrature coil. This circuit not only has the effect
of reducing distortion, but also desensitizes the distortion as
a function of tuning characteristic. As a result, low distortion
is achieved with a single tuned quad coil without the need
for a double tuned coil which is costly and difficult to adjust
on a production basis. The lower distortion has been
achieved without any degradation of the noise floor of the
audio output. Futhermore, the compensation circuit first-order cancels the effect of quadrature coil Q on distortion.
When measuring the total harmonic distortion (THO) of the
LM1865/LM1965/LM2065, it is imperative that a low distortion RF generator be used. In the past it has been possible
to cancel out distortion in the generator by adjustment of
the quadrature coil. This is because centering the quadrature coil at other than the point of inflection on the S-curve
introduces 2nd harmonic distortion which can cancel 2nd
harmoniC distortion in the generator. Thus low THO numbers may have been obtained wrongly. Large AFT offsets
asymmetrical off tuning characteristic, and less than minimum THO will be observed if alignment of the quadrature
coil is done with a high distortion RF generator.

Deviation Stop Time Constant
An offset voltage is generated by the AFT if the LM 1B65/
LM2065 is tuned to either side of a station. Since deviation
stop detection in the LM1865/LM2065 is detected by the
voltage at pin 14, it is important that this voltage move fast
enough to make the deviation stop decision within the time
allowed by the controller. The speed at which the voltage at
pin 14 moves is governed by the RC time constant, R5 C9.
This time constant must be chosen long enough to remove
recovered audio from pin 14 and short enough to allow for
reasonable stop detection time.
Signal Level Stop Using Ultrasonic NOise Detection
As previously mentioned, the R6 C8 time constant on pin 12
is necessary to filter the noise spikes on the output of the
internal comparator in the LM1865/LM1965/LM2065. This
time constant also determines the level stop time. When the
voltage at pin 12 is above a threshold voltage of about 0.6V,
the stop output is low. The maximum voltage at pin 12 is
about 0.8V. The level stop time is dominated by the amount
of time it takes the voltage at pin 12 to fall from O.BV to

Care must also be taken in choosing ceramic filters for the
LM1B65/LM1965/LM2065. It is important to use filters with
good group delay characteristics and wide enough bandwidth to pass enough FM sidebands to achieve low distortion.

2-30

r
s::
......

Application Notes (Continued)
With the LM1865/LM1965/LM2065 system, a low AGC
threshold is achieved whenever there are strong out-ofband signals that might generate an interfering 1M3 product,
and a high AGC threshold is achieved if there are no strong
out-of-band signals. The high AGC threshold allows the receiver to obtain its best signal-to-noise performance when
there is no possibility of an 1M3 product. The low AGC
threshold allows for weaker desired stations to be received
without gain-reducing the tuner. It should be noted that
when the AGC threshold is set low, there will be a signal-tonoise compromise, but is assumed that it is more desirable
to listen to a slightly noisy station than to listen to an undesired 1M3 product. The simplified circuit diagram (Figure 5)
of the AGC system shows how the dual AGC thresholds are
achieved.
Vm = 1V corresponds to a fixed in-band signal level (defined as VNB) at the tuner output. VNB will be referred to as
the "narrow band threshold". VWB also corresponds to a
fixed tuner output which can either be an in-band or out-ofband signal. This fixed tuner output will be called the "wide
band threshold". Always VWB > VNB. R11 and C13 define
the AGC time constant. A reverse AGC system is shown.
This means that VAGe decreases to gain-reduce the tuner.
The LM1865/LM1965 AGC output is an open-collector current source capable of sinking at least 1 mAo The LM2065
AGC output is also an open collector current source capable of sourcing at least 1 mA. The AGC voltage can move
over the full range of the V+ supply.

The LM1865/LM1965/LM2065 has been carefully designed
to insure low AFT offset current at the point of minimum
THO. AFT offset current will cause a non-symmetric deviation mute/stop window about the point of minimum THO. No
external AFT offset adjustment should be necessary with
the LM1 B65/LM1965/LM2065. The amount of resistance in
series with the 1B J.LH quadrature coil drive inductor, L1, has
a significant effect on the minimum THO. This series resistance is contributed not only by R13 but also by the 0 of L 1.
The 0 of L1 should be as high as possible (ie: 0>50) in
order to avoid production problems with the 0 variation of
L 1. Once R13 has been optimized for minimum THO, adjustment on a radio by radio basis should be un-necessary.
DUAL THRESHOLD AGC
(AUTOMATIC LOCAL/DISTANCE SWITCH)

There is a well recognized need in the field for gain reducing
(AGCing) the front end (tuner) of an FM receiver. This gain
reduction is important in preventing overload of the front
end which might occur for large Signal inputs. Overloading
the front end with two out-of-band signals, one channel
spacing apart and one channel spacing from center frequency, or, two channel spacings apart and two channel
spacings from center frequency, will produce a third order
intermodulation product (1M3) which falls inband. This 1M3
product can completely block out a weaker desired station.
The AGC in the LM1865/LM1965/LM2065 has been specially deSigned to deal with the problem of 1M3.
ANTENNA

•••
PIN 8
METER OUTPUT

Vwa >VHB

IV

V+

Rll
VAGe

I HIGH OUTPUT
~ CLOSE SW2

",--6=:::"PI 1V
otherwise 11

~

0

Gm1. VWB = constants
IAGe = Gm2 Vo where Gm2 = 11/26 mV and
Vo > VWB otherwise IAGe = 0

2-31

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Application Notes (Continued)
In Figure 7 there is no AGC output until the tuner output
equals the wide band threshold. At this point both SW2 and
SW1 are closed and the AGC holds the tuner output in Figure 6 relatively constant.

First examine what happens with a single in-band signal as
we vary the strength of this signal. Figures 6 and 7 illustrate
what happens at the tuner and AGC outputs.
TUNER OUTPUT

Another simple case to examine is that of the single out-ofband signal. Here there is no AGC output even if the signal
exceeds VWB. There is no output because the ceramic filters prevent the out-of-band signal from getting to the input
of the IF. With no signal at the IF input there is no meter
output and SW1 is open, which means No AGC .

SLOPE IS INVERSELY PROPORTIONAL
TO LOOP GAIN OF WIDE BAND AGC CIRCUIT

CD

....
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.....

Figures 8 and 9 illustrate what happens at the tuner and
AGC outputs when the strength of an in-band signal is varied in the presence of a strong out-of-band signal (i.e.,
greater than VWB) which is held constant at the tuner input.
For this example, the in-band signal at the tuner output will
be referred to as VD (desired signal), and the out-ol-band
signal as VUD (undesired signal).

,
"----i'.."...,.----------VANT
: VWB

FIGURE 6
REVERSE AGC OUTPUT

V+r----.. .

In Figure 9, we see that there is no AGC output until the
tuner output exceeds the narrow band threshold, VNB. At
this pOint Vm > 1V and SW1 closes. Further increase of the
desired signal at the tuner input results in an AGC current
that tries to hold the desired signal at the tuner output constant. This gain reduction of the tuner forces the undesired
signal at the tuner output to fall. At the point that VUD reaches the wide band threshold, no further gain reduction can
occur as Vo would fall below VWB (refer to Figure 5). At this
pOint, control of the AGC shifts from the meter output
(narrow band loop) to the out-of-band signal (wide band
loop). Here VUD is held constant along with the AGC

,
,,I
1----::-"7""-------~'--VANT

VWB

TL/H/7509-10

FIGURE 7

TUNER OUTPUT

------....
""\"

V.REACHES Ywa

'------7,!.-,---- IN·BAND SIGNAL

Vwa

i '\,

, ...
:, " ......

DESIRED SIGNAL
REACHES \INa

t,
,,

,,
I

i'-..

(V.)

...
...... OUT·OF BAND SIGNAL

I Vu. DROPS
: TO LEYEL
, OF Vwa

IYu.)

"---~'---4----~-------Y6

!,VWB
,,
,,
,

, VNB

(TUNER INPUT)

FIGURE 8

REVERSE AGC OUTPUT

Y+i----.....

L-_ _ _ _ _ _

~~

__

~

____

~=:=V6

(TUNER INPUT)
TLlH/7509-11

Prima indicates referenced to tuner input

FIGURE 9
2-32

r3:

....

Application Notes (Continued)

00

voltage, while Vo is allowed to increase. Vo will increase
until it reaches the level of the wide band threshold at the
tuner output. When this occurs Vuo is no longer needed to
keep Vo > VWB as Vo takes over the job. Thus Vuo will
drop as the amount of AGC increases, while Vo is held constant by the AGC.

NARROW BAND AGC THRESHOLD ADJUSTMENT

Both the narrow band and wide band AGC thresholds are
user adjustable. This allows the user to optimize the AGe
response to a given tuner. Referring to Figure 5, when the
meter output exceeds 1V a comparator closes SW1. A simplified circuit diagram of this comparator is shown in Figure
10.
The 1K resistor in series with pin 8 allows for an upward
adjustment of the narrow band threshold. This is accomplished by externally loading pin 8 with a resistor. Figure 11
illustrates how this adjustment takes place.
From Figure 11 it is apparent that loading the meter output
not only moves the narrow band threshold, but also decreases the meter output for a given input.
In general one chooses the narrow band threshold
based on what signal-to-noise compromise is considered
acceptable.

When compared to the simple case of a single in-band signal, we see that because of the presence of a strong out-ofband signal, AGC action has occurred earlier. For the simple
case, AGC started when Vo ;;;, VWB. For the two signal case
above, AGC started when Vo ;;;, VNB. Thus, the LM1865!
LM1965/LM2065 achieves an early AGC when there are
strong adjacent channels that might cause 1M3, and a later
AGC when these signals aren't present.
For the range of signal levels that the tuner was gain-reduced and Vo < VWB there was loss in signal-to-noise in
the recovered audio as compared to the case where there
was no gain reduction in this interval. Note, however, that
the tuner is not desensitized by the AGe to weak desired
stations below the narrow band threshold.

. ....--"oJv..-...----o~~~R OUTPUT
HIGH - SWI CLOSED
LOW - SWI OPEN
TL/H/7509-12

FIGURE 10. Narrow Band Threshold Circuit

- - - - - - - - - - - - - - - - - - - - - - METER LDAD=33k
I
I
I

I
I

I

'--"':::...----,F--~-----..:....+VO

TUNER
TL/H17509-13

FIGURE 11. Affect of Meter Load on Narrow Band Threshold

2-33

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Application Notes (Continued)
VUD2 = out-of-band Signal 800 kHz from center frequency and 400 kHz away from VUD1, applied to tuner input.

WIDE BAND AGe THRESHOLD ADJUSTMENT

There are a number of criteria that determine where the
wide band threshold should be set. If the threshold is set too
high, protection against 1M3 will be lost. If the threshold is
set too low, the front end, under certain input conditions,
may be needlessly gain-reduced, sacrificing signal-to-noise
performance. Ideally, the wide band threshold should be set
to a level that will insure AGe operation whenever there are
out-of-band signals strong enough to generate an 1M3 product of sufficient magnitude to exceed the narrow band
threshold. Ideally, this level should be high enough to allow
for a single in-band desired station to AGe the tuner, only
after the maximum signal-to-noise has been achieved.

In general, due to tuned circuits within the tuner, the tuner
gain is not constant with frequency. Thus, if the tuner is kept
fixed at one frequency while the input frequency is changed,
the output level will not remain constant. Figure 12 illustrates this.
It can be shown that for a given 1M3, the combination of
VUDI and VUD2 that produces the smallest rms sum at the
tuner output is given by the equations:

a

A2 IM3)%
VUDI = 1.12 ( A1

In order to insure that the wide band loop is activated whenever the 1M3 exceeds the narrow band threshold, VNB, determine the minimum signal levels for two out-of-band signals necessary to produce an 1M3 equal to VNB. Then, arrange for the wide band loop to be activated whenever the
tuner output exceeds the rms sum of these signals. There
are many combinations of two out-of-band signals that will
produce an 1M3 of a given level. However, there is only one
combination whose rms sum is a minimum at the tuner output. 1M3 at the tuner output is given according to the
equation:
1M3 = aVUD1 2 VUD2 (assuming no gain reduction) (1)

(2)

a

A12 IM3)%
VUD2 = 0.794 ( A22

(3)

Therefore, in order to guarantee that the AGe will be keyed
for an 1M3 = VNB we need only satisfy the condition:

2
VNB

Vws5:

+ [ (Al)(I.12) (A2VNB)V,]2
Ala
+ [ A2(O.794) (AI2VNB)
A22a Ya]2 (4)

where a = constant dependent on the tuner;
The right hand term of equation (4) defines an upper limit for
VWB called VWBUL. VWBUL is the rms sum of all the signals
at the tuner output for two out-of-band signals, VUDI and
VUD2 [as expressed in equations (2) and (3)1. applied to the
tuner input.

VUD1 = out-of-band signal 400 kHz from center frequency, applied to tuner input;

TUNER GAIN

I

I
___ ..1I __ _

A2

:

I
I

I

I
I
- - - - - - - - - - - - - ' - - - - - ' - - - - ' - - - - - - - T U N E R INPUT FREQUENCY

10

10+

10+

400 kHz

BOO kHz

= tuner gain at center frequency
AI = tuner gain at f 0 + 400 kHz
A2 = tuner gain at f 0 + 800 kHz

Define A

FIGURE 12

2-34

TLlH17509-14

.-3i:
.....
CD

Application Notes (Continued)
In order to make the calculation in equation (4), the constants a, A 1, A2 must first be determined. This is done by
the following procedure:

If the wide band threshold was set to VWBUL, then when a
single in-band station reached the level VWBUL at the tuner
output, AGC action would start to take place. For this reason it is hoped that VWBUL is above the level that will allow
for maximum signal-to-noise. If, however, this is not the
case, consideration might be given to improving the intermodulation performance of the tuner.

1. Connect together two RF generators and apply them to
the tuner input. Since the generators will terminate each
other, remove the 50n termination at the tuner input.
2. Connect a spectrum analyzer to the tuner output. Most
spectrum analyzers have 50n input impedances. To
make sure that this impedance does not load the tuner
output use a FET probe connected to the spectrum analyzer. The tuner output should be terminated with a ceramic filter.

The lower limit for VWB is the minimum tuner output that
achieves the best possible signal-to-noise ratio in the recovered audio. In general, it is desirable to set VWB closer to
the upper limit rather than the lower limit. This is done to
prevent AGC action within the narrow band loop except
when there is a possibility of an 1M3 greater than VNS.
The wide band threshold at the pin 20 input to the LM16651
LM1965/LM2065 is fixed at 12 mVrms. Generally speaking,
if pin 20 were driven directly from the tuner output. VWB
would be too low. Therefore, in general, pin 20 is not connected directly to the tuner output. Instead the tuner output
is attenuated and then applied to pin 20. Increasing attenuation increases the wide band threshold, VWB.
Pin 20 has an input impedance at 10.7 MHz that can be
modeled as a 500n resistor in series with a 19 pF capacitor,
giving a total impedance of 940n L - 56°. Thus an easy way
to attenuate the input to pin 20 is with the arrangement
shown in Agure 14.
Notice that pin 20 must be AC coupled to the tuner output
and that C1 is a bypass capaCitor. R 1 adjusts the amount of
attenuation to pin 20. The wide band threshold will roughly
increase by a factor of (R1 + 940n)/940n.

3. Disconnect the AGC line to the tuner. Make sure that the
tuner is not gain-reduced.
4. Adjust the two RF generators for about 1 mV input and to
frequencies 400 kHz and 600 kHz away from center frequency (Figure 13).
5. Note the three output levels in volts.
6. Knowing the tuner input levels for VUD1 and VUD2 and
the resulting 1M3 just measured, "a" is calculated from
the formula:
a=

1M3
VUD1 2VUD2

(5)

where all levels are in volts rms. A typical value for "a"
might be 2 x 106.
7. A 1 and A2 are calculated according to the following formulas
A1 =

V1
VINI
fo

A2 =

+ 400kHz
V2

VINI
fo

AGC CIRCUIT USED AS A CONVENTIONAL AGC
If for some reason the dual AGC thresholds are not desired,
it is easy to use the LM1665/LM1965/LM2065 as a more
conventional LM3169 type of AGC. This is accomplished by
AC coupling the pin 20 input after the ceramic filters rather
than before the filters. Thus, as with the LM3169, only inband signals will be able to activate the AGC.

(6)

(7)

+ 600kHz

3300 OUTPUT

V1

IMPEDANCE
/

--'~

L-..-TUN_ER

10 loHDD kHz lo+SDD kHz

yEm,,"
CERAMIC FILTER

-1-.

TL/H/7509-16

10=10.7 MHz

FIGURE 14. Wide Band Threshold Adjustment

TL/HI7509-15

FIGURE 13. Spectrum Analyzer Display of Tuner Output

2-35

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2-36

r-------------------------------------------------------------------------"
NatiOnal

~ Semiconductor

Q)
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Corporation

General Description

features

The LM1866 has been designed for high quality battery
powered medium wave AM ana FM receiver applications
requiring operation down to 3V. The AM section contains a
fully balanced, wide dynamic range, gain controlled mixer
stage buffered from a single pin local oscillator. A two pin
compound IF amplifier and internal detector provide a low
distortion high level audio output. An AM/FM signal strength
meter voltage is provided to a single output pin. The FM
section contains a six stage limiting IF amplifier, quadrature
detector, AFC output, deviation audio muting and noise operated audio muting. While designed for the high ripple, high
battery impedance conditions found at the end of life for
four "C" or "0" cells, the LM1866 will operate equally well
at supply voltages up to 15V.

I:J

Operation from 3V to 5V

I:J Excellent power supply ripple rejection
I:J
I:J
Cl
I:J
I:J
I:J
Cl
Cl

Fully balanced, wide dynamic range, AM mixer stage
Internal AM detector for minimum tweet interference
Single pole DC AM/FM mode switching
Six stage FM IF limiting amplifier for excellent AM
rejection
"Soft" FM deviation and noise operated audio muting
FM quadrature detector
Single pin AM/FM meter output
Single pin matched level AM/FM audio output

Block Diagram and Test Circuit

'"

50

:--

001

~001

~V

10.1Mtlz

TLlHI790B-1

Order Number LM1866N
See NS Package Number N20A
Coil Data:
T2, Toko 159GC·A3785
CF1, Toko CFU-90D

....3:

CD

T1. Toko KAC K2318HM
T4 = T5, Toko RB06A5105

2-37

Toko America
1250 Feehanville Drive
Mount Prospect. IL 60056
(312) 297·0070

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (Pin 14)
15V
Package Dissipation (Note 1)
1900mW

Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec.)

-55·Cto + 150·C
O"Cto +70·C
26O"C

Electrical Characteristics (Test Circuit, TA = 25·C)

I

Parameter
STATIC DC CHARACTERISTICS: elN

Conditions

= 0, RMUTE = 00, Vee = 6V

Operating Supply Range, V14
Supply Current, 114
Supply Current, 114
Regulator Output Voltage, V11
Meter Output Voltage, V18
Meter Output Voltage, V18
AFC Output Voltage, V17
AM/FM Audio Output Resistance, Ro 15
AM DYNAMIC CHARACTERISTICS: fAM
Maximum Sensitivity
20 dB Quieting Sensitivity
Signal to Noise Ratio
Total Harmonic Distortion
Total Harmonic Distortion
Audio Output Level
Overload Distortion
Meter Output Voltage
Meter Output Voltage
FM DYNAMIC CHARACTERISTICS: fFM

I

Min

3
AM Mode
FMMode
AM Mode
FMMode
FMMode

= 1 MHz, fMOD = 1 kHz, m = 0.3, Vee = 6V
eAM for eo = 6 mV
eAM for eo = 20 dB SIN
eAM = 10mV
eAM = 10mV
eAM = 10 mV, m = 0.8
eAM = 10 mY'
eAM = 50 mV, m = 0.8
eAM = 1 mV
eAM = 50mV

40

70

I

Typ

6
15
16
2.9
0
0
2.9
3

9
25
50
0.3
1
120
2
2.0
3.0

I

Max

15
27
24
0.2
0.2

2
12
3.0
3.5

I

Units

V
mA
mA
V
V
V
V
kO

/LV
/LV
dB
%
%
mV
%
V
V

= 10.7 MHz, fMOD = 400 Hz, af = ±75 kHz, Vee = 6V

eFM for - 3 dB Limiting Sensitivity
20
35
- 3 dB Limiting Sensitivity
/LV
Signal to Noise Ratio
60
76
dB
eFM = 10mV
AM Rejection
55
eFM = 10 mV, 30% AM Mod
40
dB
Total Harmonic Distortion
0.5
1
%
eFM = 10mV
Audio Output Level
eFM = 10 mY, 30% FM Mod
60
120
mV
Meter Output Level
1.3
2.3
V
eFM = 1 mV
Meter Output Level
2.0
2.8
V
eFM = 50mV
± Deviation Mute (Notes 2, 4)
40
kHz
eFM = 10 mY, RAFC = 10k
Set eFM for -3 dB Limiting Sensitivity
2
5
10
kO
RMUTE for Noise Mute (Notes 3, 4)
60
75
Max Audio Mute Attenuation
dB
Note 1: Above TA = 25"C. derate based on TJ(max) = 150"C and 8JA = 65·C/W.
Nole 2: RMUTE = 2 kO. eFM = 10 mV. adiust center frequency for VAFC = VREG. record fFM. adiust ± fFM for > 50 dB audio mute attenuation.
Nole 3: Ad/ust RMUTE from 2k to 10k for >50 dB audio mute attenuation. Set eFM = 10 mV and check for mute off.
Note 4: Whan RMUTE = 00. the deviation and noise operated mute functions ara disabled. When AMUTE = 2 kO, only the noise mute function is disabled. The
deviation mute bandwidth Is set by the AAFC resistor. The noise mute threshold is set by the RMUTE resistor. Test circuit noise bandwidth characteristics prevent
noise mute operation for IF input levels below the - 3 dB limHing threshold. When the FM IF Is used with a tuner. full noise mute capability Is accessible (See
Applications Information).

2-38

r-----------------------------------------------------------------------------,
Typical Performance Characteristics (Test Circuit)
AM Characteristics
Vee = 6V
10

~ -10
z
:: -20

'"

~ -3~

c

~ -40
~

I

1,=1 MHz. IMOO=l kHz
m=,.3 ~
SIGNAL+NOISE ~

~

lY

3.0

~OISE I

1

10

100

-50

1.0 z

~

:s
0

lk

'"~

.

10k lOOk

~

"

"~1~.7 ~~z. 1~~oJob H;'

2.0

....

)J

1

== -30
iic> =~ -40

.

z

§

1.0 ;;:

:s

I
I II ILL

I
rl

~

I"'C

=
~ -50

m
::!!

II\.

AM RF INPUT VOLTAGE (~V)

~<

~ -20
z

c

-

.Yr

-~

~-10

;r:

.6,f5kHZ II I
METER
NOISE

-70

1M

10

;e
3.0

;;: § -60

V

-~

::!!

;§
!:i

FM IF Characteristics
Vee = 6V

II SIGNAL+NOISE I
I'll II II II I

!-10

.
~

I

10

....

~
en

FM IF Characteristics
Vee = 6V

~ -20
z
~ -30
:= -40

!ll

2.0

'r-I

METER

-50

;r:
;r:

!!I

~

THD+NOISE

.

r
i:

SIGNAL + NOISE

10=10.7 MHz. fMoo=400 Hz
.6F= ± 75 kHz. m=0.3

-60

'\.

-70
-80

0

1

10 100 lk 10k lOOk 1M
FM IF INPUT VOLTAGE (p.V)

10

n

~H~+~J'SE~ ~r~

"
100

i
'"

0.32
0.1 _
z

JNO;;~-+ lk

~

10 ~
;r:
c
3.2 z

10k lOOk 1M

FM IF INPUT VOLTAGE (p.V)

Quiescent Supply Current
vs Supply Voltage

Recovered Audio vs Supply
10

28

!

~

~ -10

~

Ay/

..-.5.

F~/AM MOOE

i

~ -20 i-f-,,=1 MHz. !Moo =1 kHz
c
.,"=10 mV. m=0.3
c
I
I
I
I
I
is
~ -3~ f- t-~M MODE

G

-

~

2

FIM

16

AM MODE

/I

12

III

V

ill

o

-40
4 6 8 10 12 14 16
SUPPLY VOLTAGE (V)

M~DE t-- ,.......

20

g:

I, = 10. 7 MHz. IMOO = 400 Hz
.61= ±22.5 kHz ••,"=10 mV

o

24

o

2

4 6 8 10 12 14 16
SUPPlY VOLTAGE (V)
TLlHI790B-2

Applications Information
(See Typical Applications and LM1866 Schematic Diagram)
VOLTAGE REGULATOR SECTION
Because of the wide supply voltage range and high ripple
conditions expected in battery or low cost transformer supplies, the LM1866 uses a band gap referenced active voltage regulator which is externally compensated at pin 19.
This capaCitor, when made large enough, improves the supply rejection and decreases the noise bandwidth to a level
well below the AM reception frequencies. A 0.1 ,...F capacitor will compensate the regulator for low noise operation
while 50 ,...F (max) will improve supply rejection and the
maximum FM audio mute attenuation characteristics. During
power turn on, the pin 19 capaCitor is quick-charged to its
normal operating voltage so that the AM or FM sections are
in operation before the audio amplifier turn on delay has
timed out. See LM1895/LM2895 and LM1896/LM2896
data sheets for additional audio amplifier information.

the loopstick secondary winding. The mixer output 1st IF
transformer at pin 7 should be returned to Vee at pin 14 to
allow maximum undistorted output swing when tuning between stations. RF and AGC decoupling at pin 6 removes
noise and lowers audio distortion.
The mixer upper pairs are switched differentially by a buffer
amplifier from the pin 8 local oscillator. DC feedback is provided by the oscillator coil secondary winding to the pin 11
regulator voltage.
The oscillator frequency is given by:
0.159
fo = J[C'
and the peak swing is given by: Vp = IZ (I = 700 ,...A, Z =
tank impedance at resonance). Vp should be between 0.3V
and 0.5V to maintain an undistorted output at low supplies.
The two stage AM IF amplifier at pins 12 and 13 requires
output to input DC feedback and external decoupling. The
IF gain is given by:

AM SECTION
The AM section contains a fully balanced mixer stage with
the RF input applied to a differential, diode degenerated,
transistor pair at pins 5 and 6. DC feedback is provided by

2-39

fJ

~ .-------------------------------------------------------------------~
~

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..-

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....I

Applications Information (Continued)
where ZL equals resonant unloaded tank impedance in parallel with REXT. In most applications ZL = 10k and

audio output voltage via 056 to pin 15. The ± AFC current,
external load resistor (RAFcl and the 10 /-tF capacitor provide an audio decoupled AFC voltage to pin 17. The ±
noise current and internal load resistor R 114 provide a
wideband detector output that is limited in frequency by
CSTRAY. With the addition of internal C4 and R120 a band
pass filter (fo '" 1 MHz) is realized at the input of the peak
to peak detector. The output current, flowing in resistor
RMUTE and filtered by a capacitor, provides a mute voltage
at pin 16. When the mute voltage rises to approximately one
VSE, transistor 0139 will start to shunt the ± audio current
away from R84, muting the audio output. The value of the
RMUTE resistor will determine the minimum audio signal to
noise ratio at which one wishes to mute. The deviation mute
detector will output a current only when the AFC voltage is
offset above or below the VREG voltage. Load resistor R121
and transistor 0154 will convert this current to a mute voltage at pin 16. This is done to prevent interaction between
the two detector output currents. The external RAFC resistor
is used to set the deviation mute bandwidth so that the pin
16 mute voltage is one VSE at the desired frequency band
edge. When disabling the mute functions, pin 16 is shorted
to ground, preventing 0139 from becoming active.

ZL
OL=-=5
Xc
where REXT = an external IF gain setting resistor and Xc =
impedance of tank tuning capacitor. A rule of thumb for setting the IF gain would be to adjust REXT for 20 dB audio SIN
when the audio has dropped 10 dB below the level found at
the AGC threshold. (Because of the low OL, a non-tuned
coil is acceptable.)
The output of the IF amplifier drives an internal detector
which is operating at low currents. This results in very low
2nd and 3rd IF harmonic radiation for minimal tweet interference.
FMSECTION
The FM section contains a six stage limiting amplifier, quadrature detector, AFC output, deviation mute detector and a
high frequency noise mute detector. (See Figure 1 for the
Simplified Mute Circuit Schematic.) The output of the quadrature detector is split into three current source pairs. The ±
audio current and internal load resistor R84 provide the

PIN 15
AUDIO
OUT

2.9V

VnEG

PIN 11

R122
2k

8111
6k

±I
AUDIO
SHUNT

PEAK TO PEAK
OETECTOR
DC

PEAK TO PEAK
DETECTOR
1 MHz
Rl20a...._ _ _ _..1
20k

TL1H1790B-3

"'External component

FIGURE 1. Simplified Mute Circuit Schematic

2-40

.-----------------------------------------------------------------------------'r

:s:
....

Applications Information (Continued)
TABLE I. Typical Application External Coil and Component Selection Guide
Typical Value
Purpose
AM/FM tuning capacitor
330n, 0.01 ",F
FM IF decoupling, filter match and DC feedback
AM/RFI AGC decoupling
1 ",F-l0",F
27k,1 ",F
Sets AM AGC time constant
120k-150k
Optional: decreases AM audio output but improves AM meter threshold
0.1 ",F
Regulator output decoupling
0.1 ",F, 10 ",F
AM IF/audio decoupling
15k
Sets AM IF gain
lOn, 0.1 ",F, 100 ",F
Supply decoupling
3k,0.01 ",F
Sets FM de·emphasisl AM smoothing
0.159
Audio post filter pole is given by: f = - C'
RT 10
when RT = R3 + Ro 15 = R3 + 3 kn
o to 10k, 10 ",F
Sets noise mute threshold, filter. on will turn off mute function.
10k, 10 ",F
Sets deviation mute bandwidth, audio decoupling
Regulator decoupling and supply rejection filter
10 ",F

Component
C1A,B,C,D
Rl,C2,C3
C4
R5,C5
R6
C6
C7,C8
R4(REXT)
R7, C15, C14
R3,Cl0

RMUTE, Cll
RAFC, C12
C13

T2

T1

r-g-------l

r+~-~i,l

I

I
I
I

II I

I

I

I

I

IL ________ ...JI

l

c,

I
I
________ JI
242T

CT
au

CT~50pF

au ~ 80
I ~ 10.7 MHz
Part no. NS·l07C
Apollo Electronics Corp.

CF1

ig--------t:------\j------g------l

1
r-9---E-II
I

18T

TLIH/7908-6

~

180 pF
~ 14
f ~ 455 MHz
Part no. 159GC·A3785 Toko

T4 and T5 MW Oscillator Coil

: 0

I
II
I
IL __________ ..1I

TL/H17908-5

CT ~ 82 pF
au;" 70
I ~ 10.7 MHz
Part no. KAC K231 8HM Toko

"

r+:--~~C-~-1

" I
I
I

IIII

0

TUH/790B-4

I

T3

I
I

:

98T
"
I
IL _____ :..JI

I

,

TUH/7908-7

CT1

OT
8

II

"

761

II

9T

~

II

lOT

II

.14T

"

13T

CT2

I
I
I

I

I
I

I
I

I

I

~------------------------~
TUH17908-8

L~360fLH

I ~ 796 kHz
au ~ 160
Tuning Iraq. ~ 985 kHz-2105 kHz
Part no. RB06A5105 Toko

Toko CFU·0900 or equivalent
I ~ 455 kHz, BW > 4.8 kHz

MW Antenna Coil

Dummy Antenna for FM

:3;;[

~~::J:HA

FM

~

jll[
TLIH17908-9
L~650fLH

TLIHI7908-IO

Variable Tuning Capacitor
Type: aT·22124 Toko
Capacitance: AM C1A4 pF-142 pF, CIB 4-60 pF
FM 2.5 pF-20 pF
CI C, CfD

I ~ 796 kHz
au ~ 200
Tuning Iraq. ~ 530 kHz-1650 kHz
L7 SWG #20, N ~ 31/2T,I0 ~ 5 mm
L5 SWG #20, N ~ 31/2T.10 ~ 5 mm
L6 L ~ 0.44 fLH, N ~ 4 1/2T, au ~ 70

2-41

CI)

Q)
Q)

LM1866
See Table I for coil and numbered com~

AM Performance (525 kHz-I 650 kHz)

FM Performance (88 MHz-I08 MHz)

• Maximum sensitivity: 100 p.V/m

.30 dB quieting sensitivity: 3.5 p.V

ponent data.

• 20 dB quieting sensitivity: 250 p.V/m

• - 3 dB limiting sensitivity: 7 p.. V

See LMI895/LM2895 data sheet for

audio amp info.

• Tweet'" worst case: 5%
100 mVlm: 1.5%

"'0:1:

I

i""'l:;
!.C14

~ll1O"F

'10

~OOl"F
RJ

"

'00

~O.02,'

r--------o~~

002"~

I\:)

~

1f

=Ii

rtTI[__~j

,,
:

, i

100

~/

NR461fG

"'~'
C
t'%""
~

"Ok

~500"~"

L_________________

~

AM TUNING

::!:

.!.

"Tweet is an audio tone produced by the 2nd and 3rd harmonic of the IF beating against the received signal. It is measured as an equivalent modulation level: i.a., a 30% tweet has the same amplitude at the detector as a
desired signal with 30% modulation.

FIGURE 2. Typical AM/FM Radio Application

Equivalent Schematic Diagram

EI

2-43

co
CD

....
CO

::::E

....I

~ Semiconductor
NatiOnal

Corporation

LM 1868 AM/FM Radio System
General Description

Features

The combination of the LM1868 and an FM tuner will provide all the necessary functions for a 0.5 watt AM/FM radio.
Included in the LM 1868 are the audio power amplifier, FM
IF and detector, and the AM converter, IF, and detector.
The device is suitable for both line operated and 9V battery
applications.

• DC selection of AM/FM mode
• Regulated supply
• Audio amplifier bandwidth decreased in AM mode,
reducing amplifier noise in the AM band
• AM converter AGC for excellent overload
characteristics
• Low current internal AM detector for low tweet radiation

Block Diagram

O.D1 IJ F

I-_~)--I

t
~r: r==~_LM_'B66---;::::=========:b~~11

FM.F.J

INPUTI

OFM

~

VREGI

.2k

I

I
I

L_

iL_J'~~~"'
.tJ

I
I
I
I

1

I

li~
Vs

_ _ _ ":"_ _ _

":"

":"

I
...1

_...1":"

R9
240k

RB
.6k

r"
+ c.g

TL/H17909-1

Order Number LM1868N
See NS Package Number N20A
Note: See table for coil data

2-44

r-

s::
......

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (Pin 19)
15V
Package Dissipation
2.0W
Above TA = 25'C, Derate Based on
TJ(MAX) = 150'C and (JJA = 60'C/W

Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec.)

Electrical Characteristics Test Circuit, TA =

25'C, Vs = 9V, RL = 80 (unless otherwise noted)

Parameter

Min

Typ

Regulator Output Voltage (Pin 16)

3.5

Operating Voltage Range

4.5

Conditions

STATIC CHARACTERISTICS eAM

-55'C to + 150'C
O'Cto +70'C
260'C

Max

Units

22

30

mA

3.9

4.8

V

0)
Q)
0)

= 0, eFM = 0

Supply Current

AM Mode, S1 in Position 1

15

DYNAMIC CHARACTERISTICS-AM MODE
lAM = 1 MHz,lmod = 1 kHz, 30% Modulation, S1 in Position 1, Po = 50 mW unless noted
Maximum Sensitivity

Measure eAM lor Po = 50 mW,
Maximum Volume

8

Signal-to-Noise

eAM = 10mV

40

50

Detector Output

eAM = 1 mV
Measure at Top 01 Volume Control

40

60

85

mV

2

10

%

1.1

2

%

Overload Distortion

eAM = 50 mV, 80% Modulation

Total Harmonic Distortion (THD)

eAM = 10mV

16

/LV
dB

DYNAMIC CHARACTERISTICS-FM MODE IFM = 10.7 MHz, Imod = 400 Hz, III = ±75 kHz, Po = 50 mW, S1 in Position 1
-3 dB Limiting Sensitivity

15

Signal-to-Noise Ratio

eFM = 10 mV

50

64

Detector Output

eFM = 10 mV, III = ± 22.5 kHz
Measure at Top 01 Volume Control

40

60

AM Rejection

eFM = 10 mV, 30% AM Modulation

40

Total Harmonic Distortion (THO)

eFM = 10 mV

45

/LV
dB

85

mV
dB

50
1.1

%

2

DYNAMIC CHARACTERISTICS-AUDIO AMPLIFIER ONLY I = 1 kHz, eAM = 0, eFM = 0, S1 in Position 2
Power Output

THO = 10%, RL 80
Vs = 6V
Vs = 9V

250
500

325
700

mW
mW
kHz
kHz

Bandwidth

AM Mode, Po = 50 mW
FM Mode, Po = 50 mW

11
22

Total Harmonic Distortion (THO)

Po = 50 mW, FM Mode

0.2

%

41

dB

Voltage Gain

Typical Performance Characteristics (Test Circuit) All curves are measured at audio output
Quiescent Supply Current
vsVoltage

~

~

FM Limiting Characteristics

10r--r--~-.--.--.

o~-+.~+-~S~+N~4-~

~

-10 f--1f--f,·j"'H't----t---l

18

~

-20

V

~

-30

~
.......... ~

l'

;-40 1 -...

~

FMMQDE

~
~"

&
0

§

•

&

8

10

"

SUPPLY VOLTAGE IVI

I.

1&

'"

I I

_\

--eo
-10

N

1

10

100

lk

-

10k

IF INPUT VOLTAGE l/oIvl

2-45

'"

0

S+N

I--!..-+-+--+--I

-20

I-+t---+---+--+---I
/
1-/-I-t--1--+--+--I

3.2

~ -30

Il...--==-I'''''''','-+--+--f---l

U

;

0.32

!;
~,,-50

10.0

r\
-50

10.--.---r--~-.--~

~.

'm"4DOHz

THO+N

FM IF AM Rejection

~

0.1
lOOk

51

,g

-10

-401--+-~
~~-+--4---I

AMR+N
'"
.6f=:±15kHzt--'t'--t---t
'm"'40DHz
~ -&0
30%A M MOO~LATlO~
:i! -10 L---"1__- ' -__.l---'__- '
1

10

100

,.

10k

IF INPUTVOLTAG£ ~VI

lOOk

TL/H17909-2

PI

Typical Performance Characteristics

(Continued)

All curves are measured at audio output (Test Circuit)

Gain vs Frequency Audio

fa,

10

AM Characteristics

"

~

.....
Ii:
~

-10

S
:a

-20

10.D co
z

-40

~
co

-so

::>

-80

..
6

THD+N

!

10

100

1k

10k

.

0.32

5

-2
-3

~'f

..g

g

11
FMMODE

f m a , kHz
f o -1MHz
IIN-18mV

~;:~~!~H~L

Power Dissipation vs Power
Output, RL = 80
-

f= lk

r'

~
co
fi
~

~

'i'~TJD r-

"

.
.

s·g

~

I

4 s ' IV

0.8

0.4

I I

1

OA

..~
Z

..J'.;f"

co

!.,

lD%THD

;

~

0.2

~

Vs:"sv
0.8

1.2

1.&

2-D

Pour-sa mW
RL' an

6

3l1THD

Vs·gy

I

z

1/
AM/,

0.4

OUTPUT POWER !WI

0.6

0.8

1.0

12

/

~/FM

1

o

0.2

10M

Distortion vs Frequency
Amplifier Only

is 4
t;

11

/I

t

~
1M

lOOk

10k

& Audio

is

Vs= 12V

L

0.1

f

o

1k

FREQUENCY IHII

-'I

f-l kHz

11:

o

-20
16

Power Dissipation vs Power
Out,RL = 160
1.0

~S'12V

3l1TH

14

M

f

>

10.1MHr

12

r-

20

SUPPLY VOLTAGE IVI

RF INPUT VOLTAGE '"VI

1.2

f m =400Hz

10

40

~

AM MODE

4

1M

iii

;;:

II

31J%AMMDQ

-7

....
..."'

:a

AM""

1

~ -5
-6

0.1

lOOk

-1

60

FM

F

~

POU r .. &OmW
RL = an

11
1 1

~-4

:a
::!
co

1.0

"'l4.J.N
~~ ~::~~l;I~:Hz III I

"'Ii'

'n" !

3.2

:a

3
2

~

~

iii -3D

5

fa

....
co
....

S+N

~

90 Amplifier Only

Recovered Audio vs Supply

20

50 100 200 &00 1k 2k

1
&k 10k 20k

FREDUENCY (Hzl

OUTPUT POWER !WI

TLlH17909-3

Test Circuit

AUOIOO

OUTPUT

Z5DpI

8

,

D.lpf

VS-t--~~~AU~0~JD~-r------------~~------------~19
so F

"T ~"'

INPUT

"
17

"

~"M

LM1BSB

O.OI~F ~

15
16k

r-,

t4

.".

10k

I

13

Ir---'
II
II

1.._" .J I
I

L'!.._

~J
':'

Note: See table for coil data

'"

36pF

TLlH17909-4

2-46

~

5.6pF

"C

5'
e?

C12

ANTEN~~~ ~o.oD1

»

"C

"2-

4Jp'

5'
D)

JJIIF

....

l4

0'
~

C1C

0.D2

':"

(

1\:1

.j,.

III

"

*

I

FM

(

T'''"'

I

pe:,':nce (5;

~-1650 kH~

.30 dB qUieting senSItiVity: 3.5 p.,V

• Maximum senSItivity: 100 JLV/m

• -3 dB limiting sensitivity: 7 /J-V

.20 dB quieting sensitivity: 250 p.V/m

':"

I

L_

:

WJ

perfO''::C~8~HZ-108 -~M

~j
I
I

.22' ':"

I

M:j

,3D

22'
.. 'INor-vs
~I~·~/~--------~·C

C1A

I~'CZ

I
-

-

SIGNAL
GROUND

~

DtpF

---i

L.._

I~

-=

16k

• Tweet" worst case: 5%

100 mV/m: 1.5%
"Tweet is an audio tone produced by the 2nd and 3rd harmonic of the IF
beating against the received signal. It is measured as an equivalent modu·
latien level: i.e., a 30% tweet has the same amplitude at the detector as a
desired signal with 30% modulation.

I I
I AS
I
I
_-.J,:"

lf~

' , r ______
'
-.JI

':"

':"

l~~.

I

r
'"

TLlH/7909-5

898~l/IIl

II

~

CD

....
~

:E

,--------------------------------------------------------------------------,
PC Board Layout

....I

TL/H/7909-6

Component Side

Typical Performance Characteristics Typical Application
All curves are measured at audio output

5i
".....
a:

10

.'".
.....'"

S+N

~

E

iii
:s

...
::0

::

::0
C>
C>

..
C

::0

-10
-20
-30

r<

/
II

\

-60

-10

co

~ -30

...

\

::0

IO=98MHZ:~

"I = ±15 kHz
Im= 400 Hz

-10
1

S+N

!i:" -20

FM MODE

-40
-50

~

~

10

10

::

-40

::0

C>
C>

~

100

..
c;

::0

lk

10k

lOOk

RF INPUT VOLTAGE !!tV)

-50

. . .V

V
/ ---.
V

AM MODE

"-

'-

1m = 1 kHz
10 = 1 MHz
30%MDDULATION
0.1

10

N

100

lk

RF FIELD STRENGTH (mV/m)
TLlH17909-7

TL/HI7909-B

2-48

r-

:s:
.....

IC External Components (Application Circuit)
Typical

Component

Comments

Value

Typical

Component

}

100 pF

Removes tuner LO from IF input

R9

240k

C2

0.1,..F
0.01,..F

Antenna coupling capacitor

C19
C7

1,..F
10 ,..F

CB

0.1,..F

C20

0.1,..F

R10

50

C21

250,..F
6k2

C4,C5
C6,C9

FM IF decoupling capacitors

0.005 ,..F } AM smoothing/FM de-emphasis
1k
network, de-emphasis pole is
given by.

R5

f1

""
2'IT (C6

+ C9)

(R4 R6)
R4 + R6

C10

10,..F

C11

0.1,..F

Regulator decoupling capacitor

C12

10,..F

AC coupling to volume control

Comments

Value

C1

R1

IF coupling
IF coupling

}

Regulator decoupling capacitor

C13

0.1,..F

C14

50,..F

Power supply decoupling

C15

0.1,..F

Audio amplifier input coupling

R7
C16
C17

3k
} Roll off signals from detector in
0.001,..F the AM band to prevent radiation
100,..F
Power amplifier feedback
decoupling, sets low frequency
supply rejection

R8

16k

Power supply decoupling

Set AGC time constant

High frequency load for audio
amplifier, required to stabilize
audio amplifier
Output coupling capacitor
Sets Q of quadrature coil,
determining FM THD and
recovered audio

R2

12k

IF amplifier bias R

R3

5k6

Sets gain of AM IF and Q of AM
IF output tank

R4

10k

Detector load resistor

R6

50k

Volume control

C1B

0.02,..F

Power supply decoupling

R11, R12

1500

Terminates the ceramic filter,
biases FM IF input stage

D1

1N4148

Optional. Quickens the AGC
response during turn on

AM detector bias resistor

Coil and Tuning Capacitor Specifications
Cl

AM ANT 140 pF max 5.0 pF min
AM OSC 82 pF max 5.0 pF min

L1

640 p.H, Qu ~ 200
Ap ~ 3k5 @ F ~ 796 kHz
(At secondary)

FM 20 pF max 4.5 pF min
TOKO CY2·22124PT

Qu> 70@ 10.7 MHz, L to
resonate w/82 pF@ 10.7 MHz
TOKO KAC·K2318 or equivalent

Tl

Trimmers 5 pF

LO,L2 360 p.H, Qu

>

AM antenna
1 mV Imeter induces
approximately 100 P. V
open circuit at the secondary

80 @ F~ 796 kHz

TOKO AWO·6A5105 or

TLlH17909-10

equivalent

T2

Toka America

3f

Qu> 14@455kHz,Lto
resonate w/180 pF @455 kHz
TOKO 159GC-A3785 or
equivalent

1250 Feehanville Drive
Mount Prospect, IL 60056
(312) 297-0070

TLlH17909-9

L4

SWG #20, N

diameter
L5

3%T, inner

TL/H/7909-11

CFl

SWG # 20. N ~ 3%T, inner

diameter
~

= 5 mm

0.44 p.H, N

L6

L

L7

SWG #20, N

diameter
CF2

~

= 5 mm

~

~

4 %T, Qu

~

70

2 %T, inner

= 5 mm

10.7 MHz ceramic filter
MUAATA SFE 10.7 mA or

equivalent

~f11~
jJI

TOKO CFU·090D or equivalent
BW > 4.8 kHz @ 455 kHz

TL/H/7909-12

Murata
2200 Lake Park Drive
Smyrna, GA 30080
(404) 436·1300

T3

4T

51 pF

~

TL/H17909-13

2-49

Apollo Electronics NS·l 07C

or equivalent

co
CJ)
co

co
CD
CO

r---------------------------------------------------------------------------------,

....

Layout Considerations

Circuit Description

...I

AM SECTION
Most problems in an AM radio design are associated with
radiation of undesired signals to the loopstick. Depending
on the source, this radiation can cause a variety of problems
including tweet, poor signal-to-noise, and low frequency oscillation (motor boating). Although the level of radiation from
the LM1868 is low, the overall radio performance can be
degraded by improper PCB layout. Listed below are layout
considerations association with common problems.

AM SECTION
The AM section consists of a mixer stage, a separate local
oscillator, an IF gain block, an envelope detector, AGC circuits for contrOlling the IF and mixer gains, and a switching
circuit which disables the AM section in the FM mode.
Signals from the antenna are AC-coupled into pin 7, the
mixer input. This stage consists of a common-emitter amplifier driving a differential amp which is switched by the local
oscillator. With no mixer AGC, the current in the mixer is
330 p.A; as the AGC is applied, the mixer current drops,
decreasing the gain, and also the input impedance drops,
reducing the signal at the input. The differential amp connected to pin 8 forms the local oscillator. Bias resistors are
arranged to present a negative impedance at pin 8. The
frequency of oscillation is determined by the tank circuit, the
peak-to-peak amplitude is approximately 300 p.A times the
impedance at pin 8 in parallel with 8k2.
After paSSing through the ceramic filter, the IF signals are
applied to the IF input. Signals at pin 11 are amplified by two
AGC controlled common-emitter stages and then applied to
the PNP output stage connected to pin 13. Biasing is arranged so that the current in the first two stages is set by
the difference between a 250 p.A current source and the
Darlington device connected to pin 12.
When the AGC threshold is exceeded, the Darlington device
turns ON, steering current away from the IF into ground,
reducing the IF gain. Current in the IF is monitored by the
mixer AGC circuit. When the current in the IF has dropped
to 30 p.A, corresponding to 30 dB gain reduction in the IF,
the mixer AGC line begins to draw current. This causes the
mixer current and input impedance to drop, as previously
described.

:Ii!

1. Tweet: Locate the loopstick as far as possible from detector components C6, C9, R4, and R5. Orient C6, C9, R4,
and R5 parallel to the axis of the loopstick. Return R8, C6,
C9, and C19 to a separate ground run (see Typical Application PCB).
2. Poor Signal-to-Nolse/Low Frequency Oscillation:
Twist speaker leads. Orient R10 and C20 parallel to the axis
of the loopstick. Locate C11 away from the loopstick.

.-'>e.

\

\

\ 8 /

.

:0/

LDDPSTICK

/

/
/

1'-.

I""",

,

I

/

I

/

%
\

\\

\

~/
/

TL/H17909-14

In general, radiation results from current flowing in a loop. In
case 1 this current loop results from decoupling detector
harmonics at pin 17; while in case 2, the current loop results
from decoupling noise at the output of the audio amplifier
and the output of the regulator. The level of radiation picked
up by the loopstick is approximately proportional to: 1) 1/rS;
where r is the distance from the center of the loopstick to
the center of the current loop; 2) SI N 8, where 8 is the angle
between the plane of the current loop and the axis of the
loopstick; 3) I, the current flowing in the loop; and 4) A, the
cross-sectional area of the current loop.
Pickup is kept low by short leads (lOW A), proper orientation
(8 '" 0 so SIN 8 "" 0), maximizing distance from sources to
loopstick, and keeping current levels low.

(See Equivalent Schematic)

The IF output is level shifted and then peak detected at
detector cap C1. By loading C1 with only the base current of
the following device, detector currents are kept low. Drive
from the AGC is taken at pin 14, while the AM detector
output is summed with the FM detector output at pin 17.
FMSECTION
The FM section is composed of a 6-stage limiting IF driving
a quadrature detector. The IF stages are identical with the
exceptions of the input stage, which is run at higher current
to reduce noise, and the last stage, which is switched OFF
in the AM mode. The quadrature detector collectors drive a
level shift arrangement which allows the detector output
load to be connected to the regulated supply.

FMSECTION
The pinout of the LM1868 has been chosen to minimize
layout problems, however some care in layout is required to
insure stability. The input source ground should return to C4
ground. CapaCitors C13 and C18 form the return path for
signal currents flowing in the quadrature coil. They should
connect directly to the proper pins with short PC traces (see
Typical Application PCB). The quadrature coil and input circuitry should be separated from each other as far as possible.

AUDIO AMPLIFIER
The audio amplifier has an internally set voltage gain of 120.
The bandwidth of the audio amplifier is reduced in the AM
mode so as to reduce the output noise falling in the AM
band. The bandwidth reduction is accomplished by reducing
the current in the input stage.
REGULATOR
A series pass regulator provides biasing for the AM and FM
sections. Use of a PNP pass device allows the supply to
drop to within a few hundred millivolts of the regulator output and still be in re:;Julation.

AUDIO AMPLIFIER
The standard layout considerations for audio amplifiers apply to the LM 1868, that is: positive and negative inputs
should be returned to the same ground point, and leads to
the high frequency load should be kept short. In the case of
the LM1868 this means returning the volume control ground
(R6) to the same ground point as C17, and keeping the
leads to C20 and R10 short.

2-50

...ris:

Equivalent Schematic

CD

0)

CD

2-51

C) r----------------------------------------------------------------------------,
.....
CIO

.....

:E
....I

~ Semiconductor
NatiOnal

Corporation

LM1870 Stereo Demodulator with Blend
General Description

Features

The LM1870 is a phase locked loop FM stereo demodulator
with a DC control pin for reducing noise by decreasing separation during weak signal conditions.

.. Blend control
II Large input overload
.. Low beat note distortion
01 Low THD diode switching outputs
.. VCO stop function
II Wide supply range, 7V to 15V
II Mono override pin

Applications
.. Automobile radios
.. Hi Fi receivers and tuners
.. High performance portable radios

Typical Application and Test Circuit
12V

Order Number LM1870M or LM1870N
See NS Package Number M20B or N20A

A'9
, . -_ _---, 15k

19kHz
TEST POINT

CI4
O.OlpF

VlAMP
All
180
2W

A16
Ik

TUPIN 13

lM3189

BLEND
INPUT

r---+----o~~~T

VOLTAGE

"'---+,_,-0 ~~GTHT
~~~~~~~~~~~~~

A9

.U

"J

AIO

v'

TLlH/7910-1

FIGURE 1
Pin Functions
16. Blend Resistor and
19 kHz Test Point

1. Quick Mono

6. Loop Filter

12. Right Output

2. PLL Input

7. Loop Filter

13. Left Output

3. V+

8. VCO Tuning
9. VCO Tuning

14. Right Gain and
Deemphasis

17. Blend Filter

4. Lamp Filter and VCO
Stop

10. Ground

19. Audio Input

5. Lamp Filter

11. Lamp Driver

15. Left Gain and
Deemphasis

2-52

18. Blend Filter
20. Blend Control Voltage

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, Pin 3

15V

Lamp Driver Voltage, Pin 11

18V

Output Voltage, Pin 12, 13, Supply Off

Storage Temperature

7V

Quick Mono Input (Pin 1)

V+ (Pin 3)

Blend Input (Pin 20)
Operating Temperature Range

260·C
215·C
220·C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

15V
O·Cto +70·C

Power Dissipation (Note 1)

-65·C to + 125·C

Soldering Information
Dual-In-Line Package
Soldering (10 sec)
Small Outline Package
Vapor Phase (60 sec)
Infrared (15 sec)

1.9W

Electrical Characteristics TA = 25·C, V+ = 8V, Figure 1
Parameter

Conditions

Min

Typ

Max

Units

7

8
26
4
1.8
30
0.1
1.4
0.4
-30
-2
4
2
0.1

15
45

V
mA
V
V
dB
",A
V
V
",A
",A
V
",A
",A

DC
Operating Supply Voltage
Supply Current
Input DC Voltage
Input DC Voltage
Supply Rejection
Lamp Leakage Current
Lamp Saturation Voltage
VCO Stop Voltage
VCO Stop Current
Blend Input Bias Current
Quick Mono Switch Voltage
Quick Mono Bias Current
Output Leakage

Pin 19
Pin2
15
Lamp Off, Pin 11 = 16V
Lamp On, Pin 11 @ 75 mA
Voltage at Pin 4 to Stop VCO
Pin 4 = 0.2V
Pin 20 = OV
Pin 1 = 8V
Pin 12 or 13

=

6.5V, Pin 3

=

0.2

OV

100
2.0
-100
-20

20

Audio
Mono Gain
MonoTHD
Channel Balance
Gain Shift
Channel Separation
Output DC Shift
Input Resistance
Output Resistance
Ultrasonic Rejection
SCA Rejection
Signal to Noise

1 kHz
1 kHz

-4
@

200 mVrms

Mono to Stereo
Pin 20 ;;" 1.1V
Mono to Stereo
Pin 19
Pin 12, 13
19 kHz + 38 kHz
(Note 2)
1 kHz @ 200 mVrms Mono

30
20

-1
0.05
±0.4
±0.1
45
±15
40
65
30
70
68

+2
0.25
±1.5
±1.0
±100
200

dB
%
dB
dB
dB
mV
kfi
fi
dB
dB
dB

PLL
Lamp On Voltage
Lamp Off Voltage
Lamp Hysteresis
Capture Range
Hold In Range
Input Resistance

19 kHz on Pin 2
19 kHz on Pin 2
25 mVrms on Pin 2
25 mVrms on Pin 2
Pin 2

Blend

Pin 20 from 1.1V to O.2V

Stereo Gain Change
Mono Gain Change

1 kHz L = - R Input
1 kHz L = R Input
10 kHz L = R Input

2.5
±2
8

-25
-1.5
-8

Output DC Shift

15
5
10
±4
±12
14

-35
-0.5
-14
±40

20

±6

0.5
-20
±100

mV
mV
dB
%
%
kfi

dB
dB
dB
mV

Note 1: For operation in ambient temperatures above 25°C, the device must be derated based on a 150"C maximum junction temperature and a thermal resistance
of 65°C/W junction to ambient for the DIP and 75°C/W junction-to·ambient for the small outline package.
Note 2: Input is 10% SeA (74.5 kHz). 9% pilot and 1 kHz left or right. Rejection is ratio of 1 kHz output to 1.5 kHz output.

2-53

fI

~

co
.....

::::E

....I

External Components
Recommended
Value

Part #

Effect

Purpose

Remarks

Smaller

Larger

Rl

lOOk

Pull Up for
Quick Mono

OK

C2

2 p.F

PLL Input
Coupling

Loading of
Source Varies
with Frequency

C3

0.1 p.F

Supply Bypass

C4

0.22 p.F

Lamp Filter

R6
C6
C7

3k
0.047 p.F
0.33 p.F

Loop Filter

R8

33k

C8

0.0047 p.F

C9
R9
Rl0

1000 pF
8.2k
5k

SetsVCO
Free Running
Frequency

VCO Not Adjustable with C9

Rll

1800

Sets Lamp
Current

ExcesslC
Dissipation

Dim Lamp

R14
R15

7.5k
7.5k

Load Resistors

Low Output
Voltage

Output Clips
Earlier

C14
C15

0.01 p.F
0.01 p.F

Deemphasis

Errors Due to
Pin 1 Bias
Current

Pin 1 Can Be
Shorted to Supply
if Quick Mono is
Not Used
For Sources of Less
Than 1000, Can
useO.l p.F

Shorter Time to
Switch Mono to
Stereo

Longer Time to
Switch Mono to
Stereo

High Stereo
Distortion

Narrower
Capture Range

High Stereo
Distortion

Loop Doesn't Lock

Loop Filter

High Dielectric
Resistance

Narrower Capture
Range
High VCO Jitter

I

Narrower
Capture Range

NP05%
Metalfilm

R16

3k

Sets Blend Characteristic

C17
C18

0.0047 p.F
0.0047 p.F

Filter for
Blend

Insufficient
Blend

See Curves
Reduced Blend
Bandwidth

C19

2 p.F

Audio Input
Coupling

Poor Low Frequency Response
and Separation

Turn On Delay

R19

15k

AllowsVCO
Monitoring

ExcesslC
Dissipation

Reduces 19 kHz
Output Voltage

Only Need During
SetUp

Typical Performance Characteristics Blend off unless otherwise stated
Supply Current vs
Supply Voltage

Lamp Driver Voltage
vsCurrent

3D

Gain vs RL (Pin 14, 15)

4.0

29
28

,..,..

27
26

-~

26

CURRENVLIMIT

3.5
3.0

V

2.5

1.5

8

9

10

11

12

13

SUPPLY VOLTAGE (VI

14 15

/

/
RL <7.5k
NOT
RECOMMENDED

,

-2

",,'"

....

I--

/

.'
RL>9.1k
NOT
RECOMMENDED
FORVS'IV

-6

0
7

1

0

V

1.0

f"1 kHZ

4
2

V

2.0

0.5

24

6

0

50

100

150

200

PIN 11 CURRENT (rnA}

250

300

0

2~

5

7.5

10

12.5

15

LOAD RESISTOR (kn)
TUH/791 0-2

2-54

Typical Performance Characteristics Blend off unless otherwise stated (Continued)
Gain Change vs
Temperature

VCO Supply Sensitivity

VCO Temperature Stability

19,200

........

1.0

g

g 19,100

-......

0.5

~

....... -......

,

::;

'-...... .......
-1

~ 19,000

r-...

:l:
"...,
:>

~

19,200

1.0

g 19,100

0.5

~.. ~

, r-...

19.000

'" ~...,
~ ,."

i.

~

n

18,900

-0.5

18.800

-1.0

n

'"l;

1B,900

-0,5 ~

18,800

-1.0

~
-2
-25

25

1

15

50

9

10

11

12

13

14

~

15

-25

25

SUPPLY VOLTAGE IV)

Lamp On/Off vs
Temperature
2D

!.s
w

~

- -

10

,.
.s
~

";;:

40

0-

30

;;:

I
I

-25

;;;
ON

50

TEMPERATURE

10k

rc)

"~
'"~
:::

40

1M

Ii' ''\

r\ .... r-.,

.s>

Total Harmonic Distortion
vs Input Level

60

"
'"t;
'"
""z
"

40

0-

3D

";;:

~

3D

50

w

~

I

1\

20

~1D:H'

20k

VCO FREQUENCY IH,)

0.1

0.4

0.6

o.B

1.0

1.2

MONO INPUT LEVEL (Vrms!

EI

Power Supply Rejection
Ratio vs Frequency

Separation vs Frequency
60

50
VIN = SODmV
OUTPUT !ULTRASONICS) FILTEREO

0.4

1kHz

I
0.2

20k

FREQUENCY IHd

Total Harmonic Distortion
vs Frequency
0.5

19k

18k

.... c:;;.-

-"/

::""

."

'-f-.

-

0.01
19k

18k

15

50

rc)

1.0

20

,.......

.......

40

~

50
40

~

0.3

"'"~

0.2

"~

25
TEMPERATURE

g

10

~

-25

10
20mV

c-J~l '7

3D

20

lOOk

80
JILO)T
LEVEL

-

r- r-..

40

Capture Range vs Pilot
Level

&0

z

m

50

EXTERNAL RESISTANCE PIN 4 TO 5 Ill)

Separation vs VCO Tuning

50

~

......... "
m
I

f--

20

o

15

"

'\.

10

25

";::z

50

~

"

OFF

a

60

w

l

~

60

10

f-

I

~

Separation vs Temperature

80

I

50

TEMPERATURE I'C)

Lamp On/Off vs Resistance
Pin 4to 5

ON

15

"n
"~

3D

i

20

0.1

10

a
50 100 200

500

,.

2k

FREQUENCY IHd

5k 10k 15k

10

o

50 100 200

o
SOD

1k 2k

FREQUENCY IH,)

5k 10k15k

100

i
! !

[i

I

il!

I
lk

10k

FREOUENCY (Hz)

TL/H17910-3

2·55

o

t;
.,...
::E

r-----------------------------------------------------------------------------'
Typical Performance Characteristics Blend off unless otherwise stated (Continued)

....I

L + R Frequency Response
with Blend Control

L·R Gain vs Blend Control
10

OW1'6J,~

-10
;; -20

;;;;:
~
J

~IR1J=6k 'O/Y' ,
-

-30
-40
-50
-60

10

n

7f".

~V,

z -10
;;:

~

~'~k--

.:::. -20

-r'\IIT T '
H-f-"l'y-+-+-+-t--t--l

I l. j
V~'N 2hv;& ...
f-+--I--f--I-f---j;.'H--I
R16 =3k

I

0~V*P=,N~20~.~0~,7==*=I~I~~~
;; -10 1--1- VplN 2r 0,6

~

!

I /

1-+-+--+-~PINrO=O'~~)

VplN 20:: 0.5

-20 f-+--+---II--f-+---+-jH

1 VpIN 20 = 0,4

-70 L-L....J--L---L-l.-l.-l.--'---'-..J
o 0.1 0.2 0,3 0.4 0.5 0.6 0.7 O.B 0.9 1.0

H=+=t::::j::;:t::l;:~

-3~ I---+-t----I-+-'+
11'-"=-1----+-1

-30

-40 L--L-...L..---l__L-..l--l.---l-'

VpIN 20. 0,3
-40 L---.l.---I.---...JC-..L--'---I.--...J'-I
5k 10k 15k
50 100 200 500 1k 2'

1

H-+++-H-+H-1
1

1_

"I T

VP1N2o=0,6-11 \

I I

1.1VplN 20::: 0.8,j

R16·3k

o t-t--t--t_j-o'lliV~P1N~2!i0~"'::f0,=lB

~

RI6~,.5k-1-

'\1..1"

L·R Frequency Response
with Blend Control

10~~~_,--,_,__,_"

50 100 200

500 1.

2.

5k 10k 15k

I

FREQUENCY 1Hz!

BLEND CONTROL VOLTAGE IV)

FREOUENCY (Hz)

TLlH1791 0-4

Application Hints
Blend-What & Why?

The LM1870 reduces the gain of the L-R channel before it is
demodulated. This is done by a voltage controlled shelving
filter. The Bode plot of this filter is shown below:

The signal to noise of a weak FM stereo signal is worse
than that of an equally weak FM mono signal. For this reason FM mono radios often perform better than FM stereo
radios, unless the latter is forced into mono.
The typical quieting curves of an FM stereo radio look like
this:
Typical Radio Quieting
Characteristic
o
10

V

RECOVERED

k,--I-l-+HAiiUittoIO

+-+++++1lI
I

! - ,\'

111111-

z

III STEREOI-

~
-

-20

\

-40r--r~~~--~~~Hfl

-50

-3~ f--'.-- N~II:~fI,I'kI''''''_;:-IH+tttttl

MON~BLEND ~ ~
J

5

10

203050

100

RF INPUT (",Vl

TUH/7910-5

If an acceptable signal to noise is 40 dB, then 20 dB more
signal is required in stereo compared to mono, 30 /LV vs
3 /LV. The degradation in noise is due to the L-R or difference channel. If the gain of the L-R is reduced, then the
noise associated with it will be reduced. However, there will
also be a reduction in separation.

L·R Gain and Separation vs
RF Input Level with Blend

lU

0

Outputs

L·R

l><'

-10

GAIN

The LM1870 has emitter-follower outputs resulting in a low
output impedance. The output will sink or source one mA,
therefore it will drive AC coupled loads greater than 2 kO.

r\

-20

SEPARATION

-30

In AM-FM radios the switching can be cumbersome at best.
To ease the problem the outputs of the LM1870 (pins 12
and 13) are open circuit when the supply (pin 3) is open or
grounded. This reduces the number of switch poles required

!III
III

-40
-50
1

23

5

10

20 30 50

RF INPUT (~VI

TL/H/7910-7

Mono·Stereo Switching
The LM1870 automatically switches from mono to stereo
when the level of pilot at pin 2 is about 15 mV or more. This
value can be increased by putting a resistor between pins 4
and 5, as shown graphically in the Typical Performance
curves.
If it is desired to switch to mono without turning off the lamp
driver, pin 1 should be taken below 4V. This is a high impedance input that can be electronically switched by a transistor with a pull up resistor to the IC supply.

To maintain a 40 dB signal to noise in the above example,
the gain of the L-R signal should be reduced from 0 dB gain
@ 30 /LV downward to -20 dB at 3 /LV. If this is done
properly the dashed line will result. Below is a plot of L-R
gain and resulting separation.

10

10k 20k 30k 50k lOOk

FREQUENCY IHd

NT 1"tJI
2

2k 3k 5k

The full blend response is a two pole roll-off with each pole
set by an internal 6.8k resistor and the capacitance from
pins 17 and 18 to ground. The standard value for both capaCitors is 4.7 nF resulting in two 5 kHz poles. The blend
input (pin 20) is derived from the meter drive output of the
FM IF chip (LM3089 or LM3189 pin 13). To adjust for variations in RF gain and other IC parameters, it is recommended
that an adjustment be made on each radio.

-40
-50 '----'--........>..U.J.ll...----'---'-"'-'-'""'"
I

II-H-

'----'-..J....Ju.J..LJ.U_ _...I-..I....1-U.1>JJ

lk

:C!":40 NOISE

100

TUH/7910-6

2-56

rES:
.....

Application Hints (Continued)
Input Interface
There are two inputs to the LM1870, one for the PLL (pin 2)
and the normal audio input (pin 19). The input impedance of
the audio input is about 40 kn. The input coupling capacitor
works with this input resistance and sets the low frequency
response and separation.
The PLL input (pin 2) locks onto the 19 kHz pilot and rejects
the rest of the composite signal. For this reason it is only
necessary to use a coupling capacitor large enough to insure there is no phase shift at 19 kHz. The input resistance
of the PLL is 14 kn so a capacitor between 0.01 ",F and
0.1 ",F would be fine. However, the source driving this input
must not be affected by this load. This is true only when the
source is low impedance (less than 100n).
Typical FM IF circuits have detector output impedance of 5
kn or more. This will cause very poor low frequency response and separation unless the loading is made constant
over frequency. For this reason the typical input coupling
capacitor is 2 ",F.

since the outputs can remain connected at all times. This
technique is commonly called diode switching but the method used in the LM1870 results in substantially lower distortion than obtained with discrete diodes.
VCO
The stereo performance of the LM1870 is very constant for
small «2%) changes in the free running frequency of the
VCO. To insure that the frequency stays within 2%, low temperature coefficient components should be used for the tuning capacitor (1000 pF) and resistor (8.2k). The internal oscillator has a temperature coefficient of about 50 ppml'C
(see curve). With an NPO capacitor and a metalfilm resistor
the total variation in the free running frequency will be less
than 1 % over the full temperature range. Tuning the VCO is
done by adjusting the 5 kn potentiometer to get 19 kHz
± 50 Hz with no input on pin 2.

The VCO frequency is monitored at pin 16 when current is
supplied to the pin. During normal operation the 19 kHz
square wave is not available and the resistor from pin 16 to
ground programs the blend characteristics (see curves).
The VCO of the LM1870 can be stopped by taking pin 4 low.
In addition to being useful for turning off the stereo indicator
and forcing mono FM reception, this also allows other mono
sources, such as AM, to be fed into the decoder and come
out both channels. The signal will not be Inadvertently decoded with the VCO off and it will have the same gain and
balance characteristics as the FM. The deemphasis capacitors may need to be removed for proper frequency response. The voltage on pin 20 will also affect the freuqency
response.
It should be noted that a stopped VCO cannot radiate into
the rest of the radio and cause interference. Pin 4 can be
taken low with a mechanical switch or an NPN transistor. If
a transistor is used it must have low leakage, less than
100 nA at 3V VeE, and low saturation, less than 200 mVat
100 ",A collector current.

00
......

o

IF Correction
The separation in most radios is limited by the response of
the IF. The input lead network below can often be used to
improve radio separation.
IF Correction Lead Network
2 ~F

r-------If ~TO

ri f-

PIN 2

2

LM1870
2 ~F

~ +-I1.. I~ TO PIN 19

IF OETECTOR:o-...........,J\J20IlJlk...........
OUTPUT
/

.>27k
rl7

PLL

TL/H/7910-8

To properly demodulate the L-R signal the decoder must
generate a 38 kHz signal that is locked in phase with the 19
kHz pilot signal at the input. This is done with a phase
locked loop consisting of a phase detector, a loop filter (pins
6 and 7) and a VCO (pins 8 and 9).
The loop filter is similar to other standard decoders however
the VCO incorporates an additional low pass filter (4.7 nF
and 33 kn) to reduce beat note distortion an additional
20 dB.

Power Supply
The LM1870 is designed to work on supplies from 7V to
15V. For automotive applications a regulator is recommended to protect against transients; the LM2930-8V is the ideal
choice.

PI

2-57

r-------------------------------------------------------------------------------------,
.....
CD
~

NatiOnal

Semiconductor
:i ~ Corporation
~

LM1871 RC Encoder/Transmitter
General Description

Features

The LM1871 is a complete six-channel digital proportional
encoder and RF transmitter intended for use as a low power, non-voice, unlicensed communication device at carrier
frequencies of 27 MHz or 49 MHz with a field strength of
10,000 /J. V Imeter at 3 meters. In addition to radio controlled
hobby, toy and industrial applications, the encoder section
can provide a serial input of six words for hard wired, infrared or fiber optic communication links. Channel add logic is
provided to control the number of encoded channels from
three to six, allowing increased deSign flexibility. When used
with the LM1872 RC receiver/decoder, a low cost RF linked
encoder and decoder system provides two analog and two
ON/OFF decoded channels.

•
•
•
•
•
•
•
•

Low current 9V battery operation
On-chip RF oscillator/transmitter
One timing capaCitor for six proportional channels
Programmable number of channels
Regulated RF output power
External modulator bandwidth control
On-chip 4.6V regulator
Up to 80 MHz carrier frequency operation

Block and Connection Diagram
Dual-In-Llne Package
MOO
CH4

CH5

CH6

Rm

VCC

OUT

MOO
FILTER

RF
OUT

11

CH3

CH2

CHI

10

.

4.6V

REG

BIAS

CHANNEL
ADD LOGIC

Top View
Order Number LM1871N
See NS Package Number N18A

2-58

TL/H17911-1

r
iii:
......

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

10mA

DC Current Out of Pin 13

25 rnA

Electrical Characteristics TA =
Parameter

1600 mW

Pin 4 Externally Forced

6V

Operating Temperature Range

16V

DC Current Out of Pin 4

Symbol

Package Dissipation (Note 1)

-25'Cto +S5°C

Storage Temperature Range

- 65°C to + 150'C

Lead Temperature (Soldering, 10 sec.)

260'C

25°C, Vcc = + 9V, see Test Circuit and Waveforms
Conditions

Min

Typ

Max

Units

4.5
10
4.1
S
0.4
0.4

9
14
4.S
9.5
0.5
0.5
3.5
4.5
5.5
6.5
0.1
3.S
3.S
0.5
27
0.1
0.01
120
0.06
120

15
22
5.4
10.5
0.6
0.6

V
rnA
V
ms
ms
ms
ms
ms
ms
ms

Encoder Section, Close 51, 52, 54 Open 53
V14
114
V4
tf
tm
tch
ts
ts
ts
ts
Atn
AV13
AV12
112
RrN(B)
ITH(7)
ILEAK(15)
VSAT(15)
ILEAK(CH)
VSAT(CH)

Supply Voltage
Supply Current
Reference Voltage
Frame Time
Mod Time
Channel Time
Sync Time, Tx Channels 1-6
Sync Time, T x Channels 1-5
Sync Time, T x Channels 1 -4
Sync Time, Tx Channels 1-3
Supply Rejection, tm + tcH
Encoder Output Swing
Mod Filter Output Swing
Mod Filter Source/Sink Current
Pulse Timer Input Resistance
Frame Timer Threshold Current
Mod Timer Leakage Current
Mod Timer Saturation Voltage
Channel Timer Leakage Current
Channel Timer Saturation Voltage

Encoder Only
tf = RFCF + 0.63RMODCT
tm = 0.63RMODCT
tch = 0.63RCHCT
Close S1, Close S2
Open S1, Close S2
Close S1, Open S2
Open S1, Open S2
AVcc = 6Vto 12V

Pin 15 to OV
115 = 2 rnA, (V4-V15)
Pins 1, 2, 3,16,17,1St04.6V
ICH = 2mA

%N
V p_p
Vp_p
±mA
MO,
1
240
1
240

/LA
/LA
mV
/LA
mV

RF Oscillator Section, Collector Pin 11, Base Pin 10, Emitter Pin 9 Open 54
VOUT
114
ft
VSAT(II)
HFE
LVCEO

RF Output Level
Supply Current
Transistor
Transistor Saturation Voltage
Transistor BC Beta

Use RF Voltmeter Close S3
OpenS3,S4
VCE = +5V,lc = 10 rnA
fo = 49 MHz
Ic = 10 rnA
Ic = 1OI-'A

75
16

400
30
520
SOO
150
20

mVRMS
rnA
MHz
mV
350
V

Note 1: For operation in ambient temperatures above 25°C, the device must be derated based on a 150°C maximum junction temperature and a package thermal
resistance of 75°C/W junction to ambient.

2-59

~
......

Test Circuit and Switching Time Waveforms
r-__

2k

~~

__

~t-

______

~t-

__________________

-<)~~~OOER

C13
5000 pF

~'i'
D.l.F

~
16

15

14

'.
tloUT
ENCODfR

RESET

'"'

Rm
7.9k

RCH
7.9k

"f

C4
0l F
. •

..,
REG

CHANNEL
A ADOlDGI!: B

Rl0H
10k

tt

'f

CT
0•l • F

1000 pF

RF
90k

11----0 ~~:~~~EC

RF OSC
CW

YON

~

C,

l'"'
TLlH17911-2

Note: Test circuit has been configured for evaluation by oscilloscope. Use 1% timing components. RM. RCH. RF. Cr

3.SV

w-=t-t-~
TLlH/7911-S

L1: Taka E523LN-72100191ype MG117 7% lurns wilh lap 2% turns from lop
VI: 49.86 MHz crystal 3rd overtone
Encoder oulpul (pin 13) close 51, 52, 54, 0.5 msldiv sweep

2-60

Typical Performance Characteristics
33

2

~
~

21

~

12

"ili'"
....

TRANSMITTING

=>

II

~

=

ENCODER ONLY

'"=
=
i'5

u

I
~

I

:;;
o 3

5

1

9

II

13 15

RF Output Voltage Level
vs Supply Voltage

5A
5.0

2

L-H-M"

24

~:

Encoder Output Swing
vs Supply Voltage
~

30
27

B
~

Supply Current
vs Supply Voltage

I

4.6
4.2
3.8
3.4
3.0
2.6
2.2
1.8
1.4

1;1'

-I
-2
-3
-4
-5
-6

m

'"....
=>

~
~

'"

HM P~y)E~ plol~i-

-1

-8

-9
-10

1.0
3

11

5

9

1

13

II

15

3

t1

RF Transistor
Input Admittance
vs Collector Current
VCE: 5vl~

"i

I .•

III

I

1!

.;,1 I

oS

...150 MHz

V

gl 8'

/30MH,

bie

~

1.2

"1=<

1.0

u

511 MHz

~

0.8

~

0.6

I

0.2

<

bie
30MHz

V/

,.
20

50

9

II

13

15

11

II

VCE: 5V

,...

b..
5D~~z
bo,
!30MHz

V'

V

'"50MHz

'30~~'1
0.
II L

./

III

~ ....
10

100

1

RF Transistor
Output Admittance
vs Collector Current

g 0.4

III
III
11111
10

1.4

5

VI4 - SUPPLY VOLTAGE (VI

VI4 - SUPPL V VOLTAGE (VI

V14 - SUPPL Y VOLTAGE IVI

20

50

100

Ie - COLLECTOR CURRENT PIN 11 {mAl

IC - COllECTOR CURRENT PIN II (mAl

TLlH17911-4

Applications Information
Figure 1 (A) shows the encoder output waveform. The modulation time (tm) is fixed while the channel time (tch) is the
variable pulse width. In Figure 1 (C, 0) the recovered channel pulse (tn) is the sum of tm and tch at a rep rate set by the
frame time (t,). Because the frame time is fixed, the sync
time (ts) will vary inversely to the variable channel times.

The LM1871 has been designed to encode and transmit
27 MHz or 49 MHz carriers for remote radio control (RC) of
up to six independent analog functions. The encoder section converts a variable potentiometer setting to a variable
pulse width. The variable pulse widths, each preceded by a
fixed modulation pulse, are added together sequentially and
then followed by a synchronization pulse. Figure 1 shows
the digital proportional control format and how the channel
pulse widths, sync time and frame time are defined.

TL/HI7911-5

FIGURE 1. (A) Encoder Output (Pin 13)
(8) Transmitted RF Carrier Envelope
(C) Typical Receiver Channel 1 Output
(0) Typical Receiver Channel 2 Output

After detection by the RC receiver, the channel pulse widths
must now be converted back to the required analog functions, which might be a mechanical arm movement, motor
speed control or simply an ON/OFF transistor switch. In the
case of the mechanical arm movement, commercially available closed loop servo modules can be found in most hobby
shops. The input requirements of these servos will determine the transmitted frame time and channel pulse width
range. Usually the pulse width for arm at center will be
1.5 ms; for full left, 1.0 ms; and for full right, 2.0 ms, at a rep
rate of 20 ms. A motor speed control open loop servo can
be designed for the same input pulse widths: 1.0 ms for
maximum forward speed, 1.5 ms with some dead band for
motor OFF and 2.0 ms for maximum reverse speed. In both
servo systems the input pulse width being continuously variable allows full control of arm position, motor speed and
direction. The ON/OFF function could also use the same
input pulse width range (1 ms ON, 2 ms OFF).
The 1.0 ms to 2.0 ms pulse width range required by most
servo modules is a result of transmitted RF spectrum limitations required by the FCC. If the modulation time (1m) and
the channel time were made very short ('" 10 P.s each)

2-61

....
.....
co

....

:E
...J

Applications Information

(Continued)
many sidebands 5 kHz apart would be generated on each
side of the center frequency. The amplitude and number of
sidebands are determined by the depth and duration of the
modulation pulse. FCC regulations require that all sidebands greater than 10kHz from center frequency be less
than 500 ",V/meter at three meters. In the example cited
above, the 100% modulated carrier spectrum would not be
acceptable if the field strength of the carrier was
10,000 ",V/meter at three meters. If the modulation and
channel times were made much longer ('" 10 ms each) the
transmitted spectrum would be acceptable but now the
frame time would be longer than desirable for optimum servo designs. When the received channel pulse widths are

between 1.0 ms and 2.0 ms at a frame rate of 20 ms the
and 600
to
modulation time should be between 400
insure an acceptable transmitted RF spectrum.
Figure 2 shows the block diagram and a typical application
of the LM1871 utilizing two fully proportional (analog) channels and two uniquely encoded ON/OFF (digital) channels.
The LM1872 Receiver/Decoder, a companion IC to the
LM1871, has been designed to receive and decode two analog channels and two digital channels. The two digital
channel output states are determined by the number of
transmitted channels rather than by the width of a channel
pulse. Table I shows the digital output format as a function
of the number of transmitted channels.

"'S

"'S

C13A
1500 pF

~ 2~~::F
Note: See Figure 4 for RF components.

~ 1-----...

Rm
56k

11

"'

OUT

10

~62PF

RIO
47k

LM1871

TRANSMITTER

R.

:tIOUTH---f------'
ENUDER

CHI

4fiV

CHANNEl

REG

A ADD LOGIC 8

RF
200k

TL/H/7911-6

2-62

Applications Information

(Continued)

Rl
20

l~~~~~~~~-e~~~r--e~----------~----------------------~t--------------+e---C5----------~

T

~loo"F

4:1

Cl

o.01

C2
24

+
6V

-=-

Cl0

.

(DIGITAL OUTPUTS)

~.01

LO

V·

MIX IN
LM1872 RECEIVER/DECODER

MIX OUT
18

IF IN

AGC

IF OUT

17

15

GND

SYNC

14

13

SLJL
'::"

(ANALOG OUTPUTS)

C6
0.05
R2

lOOk

C7

~o.Ol

C9

~0.01
TL/H17911-7
Tl = Toko RMC 202313} 00
T2 = Toko RMC 402503
T3, L1 = Toko KEN 4028DZ

= 110

FIGURE 2. Two Channel Analog/Two Channel Digital Transmitter/Receiver Application

fJ

2·63

_
.....
co

::::E

...I

r---------------------------------------------------------------------------------~

Applications Information (Continued)
In the frame timer circuit the NPN transistor is held on for a
period determined by the modulation pulse (tm). This was
done to insure that the timing capacitor was fully discharged. The frame (tf}. modulation (tm) and channel time
(tch) can be calculated as follows:
1.S34
tf = - I n 4.6V (R~F) + tm = 1.1 RFCF + tm

LM1871 ENCODER TIMING
Agure 3 shows the two timing circuits and waveforms used
by the LM1871. The frame timer oscillator consists of a high
gain comparator and a saturating N PN transistor switch.
When the NPN transistor is turned OFF the timing capacitor
(CF) will charge up to % of the VREG voltage. The comparator will then turn ON the NPN transistor. discharging the
capacitor back to ground ending the liming cycle. The pulse
timing circuit is similar in operation except that the timing
capacitor (CT) is charged and discharged between 113 and
% of the VREG voltage. The saturating PNP transistor
switch pulls up the modulation timing resistor (RM) which
charges CT to % VREG and six independently switched NPN
transistors provide the discharge path through the channel
timing resistors (RCH)' The time constant for both circuits
can be found as follows:

1.S34
tm or Ich = - I n 3.06V (RM or RCH)CT
= 0.69 (RM or RCH) CT
The above calculated time constants will be modified by
transistor saturation resistances and comparator switching
voltages that are slightly different than the % and % VREG
reference. One time constant should be used for the frame
time (tf) and 0.63 time constant should be used for the modulation (t m) and channel (lch) times. Because the switching
voltages are a percentage of the VREG voltage the timer
accuracy will not be "affected by a low battery condition (Vcc
< S.6V). High and low temperature (- 2S·C to + 8S·C) operation also has little effect on timer accuracy.

-t = In V1
RC
V2

when V1 = Voltage across timing resistor at end of timing
cycle.
V2 = Voltage across timing resistor at beginning of
timing cycle.
4

4.6V

VnEG~--~-----------4~--------------~

13 ENCODER
OUTPUT

FRAME TIMER

"'External components
TL/H/7911-B

PI~A~

3.06V---

I

---

OV----~
3.06V-----...

(B)

PIN 8
1.53V-----J
SYNC

(A) Voltage on

CF

TL/H/7911-9

(B) Voltage on CT
(C) Encoder pulse train output

FIGURE 3. Simplified Encoder Timing Circuits and Waveforms

2-64

r-

Applications Information

(Continued)
The accuracy and temperature characteristics of the external components will determine the total accuracy of the system. The capacitors should be NPO ceramics or other lowdrift types.
As an example the following procedure can be used to determine the external timing components required for Figure
2.
Given: Frame time (t,) = 20 ms
Modulation time (tm) = 500 p.s
Recovered pulse width (tn) range = 1.0 ms to
2.0 ms with trim capability
Non variable channel pulse width (tn) = 1.0 ms
1. Frame Timer Components
ChooseCF = 0.1 p.F ±10%
t, - tm
20ms - 0.50ms
RF = - - =
= 195 kO (200 kO)
CT
0.1 p.F
2. Modulation Time Components
Choose CT = 0.01 p.F ± 10%

500 kO potentiometer that has 300' of end to end wiper arm
rotation could be used if mechanical stops limit this range.
(300')(156 kO)
Required angle of rotation =
500 kO
= 93.6'
In most applications the resistor and capacitor tolerances
prevent sufficient system accuracy without mechanical or
electrical trimming of the analog channel pulse widths. If a
500k potentiometer is used, two trim methods can be utilized. Rs can also be included as part of the potentiometer
resistance.
Potentiometer Body
for Mechanical Trim

Q ~ ~~~.HANICAL
~STOPs
I I I
all

RS

for Electrical Trim
MECHANICAL

J3lfll
1M 1 50k

TL/H17911-10

---.!!!L.

R =
=
500 X 10- 6 = 79.36 kO 82 kO
M 0.63CT
(0.63)(1 X 10-8)
()

RS

1001£

.
.
(300')(48k)
ReqUired Body Rotation =
500k
= ± 28.8'

4. Variable ChanneI1(t1) and Channel 2 (t2) Components
When the Rp wiper arm varies across the full potentiometer range, (aR = 00 to Rp value) Rs is found for 00
and minimum tn pulse width.

Channel Add Logic
Table I shows the number of transmitted channels as a
function of pin 5 and pin 6 conditions. The threshold voltage
for both pins is "" o. 7V. When grounded, the pins are sourcing "" 300 p.A from the internal pull up resistors. External
voltages may be applied to these pins but should be below
the VREG voltage by at least one volt and not less than the
pin 9 ground.

R = tn - tm = 1 ms - 0.50 ms = 79.36 kO (82k)
S
0.63CT
(0.63)(1 X 10-8)
Rp(aR) is found for maximum tn pulse width.
tn - tm
Rp=---Rs
0.63CT

Modulator and Crystal Oscillator/Transmitter Circuit
(FIGURE 4)

= 2 ms - 0.50 ms _ 82 kO
(0.63)(1 x 10- 8)
= 156kO

The modulator and oscillator consist of but two NPN transistors whose operation is quite straightforward. The base of
the modulator transistor is driven by a bidirectional current
source with the voltage range for the high condition limited
by a saturating PNP collector to the pin 4 VREG voltage and

The Rp value could have been chosen first and a CT calculated. Usually the 270' to 320' angle of potentiometer rotation is inconvenient especially if it is desired to spring return
the control to center, or if lever type knobs are required. A

TABLE I. Digital Channel Output Format as a Function of Transmitted Channels

Pin 5 (A)

Pin 6 (B)

OPEN
GND
OPEN
GND

OPEN
OPEN
GND
GND

I

TL/H17911-11

aR = 156 kO, Rs = 82 kO
If tn = 1.5 ms ± 30% is required:
aR
±RTRIM = 0.32" + Rs = 48 kO

3. Non-Variable Channel (3 through 6) Component
tch = tn - 1m = 1.0 ms - 0.50 ms = 500 ,...s
tch
500 X 10- 6
RCH = 0.63CT = (0.63)(1 X 10 8) = 79.36 kO (82k)

LM1871 Channel Add Logic
Pin Conditions

....
==
CD
......
....

Number of Channels
Transmitted

3
4
5
6

2-65

fJ

LM1872 Receiver
Digital Outputs

A

B

OFF
ON
OFF
ON

OFF
OFF
ON
ON

.....
.....
co
.....

:E

.....

Applications Information

(Continued)
low condition limited by a saturating NPN collector in series
with a diode to ground. A current source of ± 500 ",A was
chosen to provide a means for extemal modulator bandwidth control. When a capacitor is used at this node the
transmitted RF carrier is made to slew ON and OFF at a
time determined by:
Modulation slew time (tmo)
(AV12)(CM)
=

112

=

LC tank, while having little effect on oscillator frequency, will
control the conduction angle and oscillator efficiency. Tuning the LC tank for minimum Vee supply current while observing the carrier envelope on an oscilloscope would be
the best alignment method.
For most RC applications the carrier ON to OFF ratio must
be as high as possible to ensure preCise pulse width detection at the receiver. If we were to look at the base of the
oscillator transistor we would see that the crystal is still osCillating during the time that the carrier is OFF (tm). This is
because of the high 0 characteristic (10k to 30k) of crystals
in this application. We can roughly calculate the number of
cycles required for a decay or rise in amplitude for one time
constant (63% of final value) by:

(3.8V)(0.01 ",F)
500 ",A
= 76",s

when AV12 = peak to peak voltage swing of pin 12 = 3.8V

± 112 = source/sink currentfrom pin 12 = 500 ",A
CM = capacitance at pin 12 = 0.Q1 ",F
Figure 5 shows the advantage gained by this capacitor especially if adjacent channels are 10 kHz to 15 kHz away
from the desired channel.

40
Number of cycles = -:;

"'S

The crystal oscillator/transmitter is configured to oscillate in
a class C mode with the conduction angle being approximately 140" to 160·. Resistor R 10 provides the base bias
current from the pin 4 VREG voltage. This resistor value has
been optimized for most RC applications. When the emitter
of the modulation transistor is high ("" 3.8V) the collector
and tank coil are pulled up into the active range of the oscillator transistor. RF feedback to the base is via the series
mode crystal which determines the oscillator frequency. Because third overtone crystals are used for 27 MHz or
49 MHz applications a tuned collector load must be used to
guarantee operation at the correct frequency. Tuning the
Component
Tp
Ts
L1
LL
CA
RA
C1
C2
C3
R10

At 49 MHz this will be 15k cycles or 300
for a crystal 0 of
30k. At 27 MHz this time will be 560 ",s for the same crystal
O. If long carrier OFF times were required the oscillator start
up time would as a result also be quite long. The shorter
carrier OFF times overcome one problem but do suggest
that the crystal be isolated from the antenna circuit. During
the carrier OFF time the base of the modulator transistor is
held approximately 0.9V above ground such that the emitter
still supplies current to the now saturated collector of the
oscillator transistor. Both ends of the LC tank circuit now
"see" a low impedance to ground. Further isolation is provided by the split tuning capacitor.

27 MHz

49 MHz

2 Turns
3 Turns
TaKa KXN K4636 BJF
MILLER #4611
5.4pF
1.150
1000 pF
680pF
20pF
24k

6 Turns
1 Turn
TaKa KEN K4635 BJE
MILLER #9330-10
6.2pF
3.780
220pF
47pF
33pF
47k

Toko America
t 250 Feehanville Drive
Mount Prospect. IL 60056
(312) 297·0070

Vce
..._ _ _ _ _ _-I

4.5V~

0.9V

12

-10

t----t-t---tll-+-t---I

t----t-"hfli-\'(+-t---I
~ -3~ t--t-7tT-t-........N

;;; -20

27 MHz or 49 MHz
3rd Overtone Series
Mode Crystal

f,-10kHz

LL

4.6V .;:4--'W\r--+~-f

:

CAl

I

RA

TWO FOOT 0.023 DIAMETER WIRE
EQUIVALENT CIRCUIT

TUH/7911-12

FIGURE 4. 27 MHz and 49 MHz RF Oscillator/Transmitter

2-66

'c+10kHz
TL/H17911-13

FIGURE 5. Envelope of Transmitted
Spectrum for Circuit in Figure 2

r-

Applications Information

(Continued)
If the printed circuit board shown in Figure 6 is to be reproduced, it is recommended that the layout be followed as
closely as possible. The positions of pin 13 decoupling capacitors and coil components tend to be critical in regard to
undesired harmonic emissions. Short lead ceramic disc capacitors and short decoupled traces are recommended. A
number of boards with this configuration have successfully
met all requirements of the FCC as perceived only by National Semiconductor. Final approval of any unlicensed
transmitter is granted only by the FCC via certified test measurements.

tion of a 1:1 balun transformer (-6 dB) or loading (-6 dB)
and mismatch (720 to 500, -1.7 dB) of the voltage measuring instrument. We can now relate the induced voltage
(VIN) to a measured voltage (VMEA) by:
V

VIN L

MEA

= Losses or

where:VMEA

V
IN

=

(VMEA) (Losses)
L

Voltage measured by a spectrum analyzer or calibrated receiver.
Field intensity (volts/meter).

Losses

Field Strength Measurements
As noted above the maximum radiated RF energy of an
unlicensed transmitter operating in the 27 MHz or 49 MHz
frequency band must not be greater than 10k p.V per meter
at a distance of 3 meters from the transmitting antenna. In
addition to the carrier amplitude requirement, all sidebands
greater than 10kHz from the carrier and all other emissions
(harmonic or spurious) must be less than 500 p.V per meter
at a distance of 3 meters.

Half-wave length of antenna in meters.
All mismatch, loading and insertion
losses. (In this case = 13.7 dB = 4.87)

The length of a half-wave dipole antenna is found by:
Ck
L = -meters
2f
where: C = Speed of light in a vacuum.
k = A constant related to antenna length to width
ratios, end effects and surface effects. Use
k = 0.96 for practical antenna rods SA6" in
diameter.
f = Frequency of interest.

The term used for electrical field intensity (V/ meter at 3
meters) refers to the open circuit voltage induced at the
ouptut of a resonant half-wave dipole antenna in a single
dimensional one meter field, 3 meters distant from the
transmitter under test. When making field intensity measurements, the antenna length must be adjusted for resonance
at each frequency of interest and the induced voltage made
proportional to the one meter reference length. The induced
voltage value must not include losses caused by the inser-

Simplified: L = f

~~zmeters

TLlH17911-15

TLlH17911-14

FIGURE 6

2-67

s:
....
........
CD

,...
,...

.....
co
~

Applications Information

a fiber optic transmitter/receiver link, infra-red, tone keying
or transducer carrier modulation. If the encoder output is
hard wired to the Figure 10 serial input we can recover the
six analog channels. From Figure 11 we see that the data
input will appear during the sync time which is always longer
than any channel time (tn). Inverter X1 will discharge C1
each time the input goes high. During the longer sync time
C1 will charge up to the % Vee threshold of X2 and via X3
provide the data input. The Rand C components are calculated by:

(Continued)

Now that we have a way in interpreting the field strength
measurements we must deal with the technique used in
making these measurements. Usually all measurements are
done outside on a flat area away from trees, buildings, buried pipes or whatever. The test transmitter is placed on a
wooden stool or table approximately 3 feet high such that
the vertical antenna is in a vertical position. The receiving
dipole is adjusted for the frequency of interest and oriented
to the same plane as the transmitter and placed 3 meters
from the transmitter. The dipole may be mounted on a
wooden pole or ladder such that the height of the antenna
can easily be changed. The antenna length must always be
symmetrical about the center tapped balun transformer. The
operator and his test equipment must be "behind" the dipole by some 3 or more feet. If it is desired to have the
operator at a much more distant location the transmission
line must be characterized for additional losses. A number
of measurements should be made at each frequency for
different heights and orientations of both the transmitting
and receiving antennas. The highest reading should be considered the correct reading. In addition to fundamental,
sidebands and harmonic emissions, the frequency spectrum
from 25 MHz to 1000 MHz should also be scanned for spurious emissions greater than 50 ,...V/meter at 3 meters.

tdata delay = 0.565 R 1 C1
If large values of C1 (>0.01 JLF) are required the diode 01
should be replaced by a PNP transistor with the base on X1
output, emitter to X2 input and collector to ground.
In applications requiring ON/OFF decoding of a channel
pulse width the circuit shown below could be used.

R2

CHn INPUT
fROM FIGURE 11
t(min)

Additional Applications

t(max)

Figure 2 shows a typical application of the LM1872 Receiver/Decoder. The LM1872 consists of a crystal controlled
local oscillator, IF amplifier, AGC, detector, decoder logic
and digital channel output drivers. The supply voltage range
of 2.5V min to 7V max was chosen to allow battery operation by four "C" or "0" cells.

in output LO
in output HIGH
TUH17911-16

If the recovered channel pulse width is short (t(min» R2 and
C2 are selected such that the input to inverter X4 does not
rise to the % Vee threshold. The output of X4 will be high
and the output of X5 will be low. A longer input pulse (t(max»
will allow the output of X4 to go low pulling the input of X5
low. R3 and C3 are selected such that the input to X5 will
not rise past the % Vee threshold during the remainder of
the frame time. The Rand C values are found by:

Figure 7 shows how the LM 1871 encoder can be used to
frequency shift a 200 kHz carrier that is transmitted over the
110V AC line in a home or office. Agure 8 shows how ON/
OFF carrier modulation is also possible. An LM1872 could
be used as a receiver/decoder for the Figure 8 transmitter
circuit. When using an LM1872 the carrier frequencies
should be 50 kHz or greater to insure proper detector operation.

Given:

t(min)

= 1.0 ms, C2 = 0.01 JLF

t(max)

= 2.0 ms, C3 = 0.1 ,...F

tframe

= 20 ms

0.565R2C2 = !(min)

Figure 9 shows the LM1871 configured for six analog channels with a TIL compatible output. The VREG voltage at pin
4 has been shorted to Vee. This allows a Vee(MIN) of 3V
and Vee(MAX) of 6V. The encoder output could be used for

R2

=

R3 =

2-68

1.5ms
0.565C2

=

2

+ !(max) ;

70kO

!frame = 360 kO
0.565C3

!(min) = 1.5 ms

»

c.
c.
5.lk

;::;:

O·

5.lk

-AAA

V

03
IN4002

~~.~~.'---~8---,

ttt

j.
. Rm

o

15

14

II",

Vee

13

12
~t?~IH

'''''II~
Lr"

IUGUtArOH

I~~T

BIAS

r
~

lOUT

LMI871 TOP VIEW

C6
1000"F
25V

I:J "~
1000

7•

:

llOCK

~

•

..l.. 16V

R4
<18k

ICI
lM566CN

DEVIATION
ADJ
OND

~fC5 ':"

fty

RF

...

-AA

.-...

~CF

~

T82PF

"25'

CB

en
'§

ao·

0.1 "F
200V

:::l

gc:

CD

l'

R5

~2~00 ~~2222A

B

TI
TOKD
VAN·60027N

01
IN914

-L-C4

-!-

1I15VAC
LINE

R6) .-...C7
300?
!~00 •

5100

'"

»

"C

~

~IO"F

>R3
22k

HII ,

~Nl:ODER

~IOOk

et

Slil

IC2
LM78·
L12CZ

:lCg

10

II

~

T2
30 VCT

-=

f1

-=Capacitor values in pF
Resistor values in

n

tSelect for carrier freq .

ie
200 kHz
100 kHz

C4

C7

82
160

1000

3900

Note: See AN-146 for additional information.
TLlHJ7911-17

FIGURE 7. LM1871, LM566 200 kHz Line Carrier Transmitter with FSK Carrier Modulation

m

~L8~1N'

LM1871

:J:-

a.
a.
::;:
0'

~y
~-..~-..~~,~-,

03

LM78·

1-C9

L12CZ

..J..

'm
£NtOOEA

~

LLM1871 TOP VIEW

CLOCK

ON.
4

tty

.

AF

-~

'

f~
f

25V

t~
":"

0.1 ~F
200V

ICI
LM566CN

- ' - C4

~82PF

(i'

a
0'

~F

l'
:::J

5"
~
I:

IODD~F

6
5

A2
150k

C8

C6

SlBk

"2:::s

16V

~A4

115 VAC
LINE

(II

r--

" " " 19 ~F

A3
22k

"0

-4.~-IIL.-o

IC2

lID

T2

f3~:
+ip

~--+-----------~------~

IOLlTI

:::s
e!.
:J:-

5.1k

5.1k

A6S ~C7
•
300? .......... 1000

- I - pF

C5 _

~r~o5~~0 1.:.

01
PN2222A

Tl
TOKO
YAN·60027N

01
lN914

Capacitor values in pF

Resistor values in n
tSelect lor carrier Iraq.

CF

FIGURE 8. LM1871, LM566 200 kHz Line Carrier Transmitter with ON/OFF Carrier Modulation

Ie
200kHz
100 kHz

C4
82
160

C7
1000
3900
TUH17911-18

l>

c.
c.
5.1k

::::;:

5.1k

0'
::l

!!

5VVCC

l>

"CI

'2.

C:;'
D)

11

10

0'
rn

RF

OUT

VCC()(,lII---4ep-_
_--:-:~:.
5V

::l

I

CH6 CH5

'0
o

(CLOCK)

a:

14

::l

c:
CD

'.

.s

MM74C164
SERIAL SHIFT REGISTER

IUUT

ENCODER

RESn

~

-rJ~'"
CHI

REG

Idata delay = 0.565 RC
Note: See Figure 11 for Timing Waveforms.

RF

~

~CF

~~
TUH/7911-19

FIGURE 9, LM1871 Six Analog Channel Encoder with TTL Compatible Output

FIGURE 10. Six Analog Channel Detector

~l8~W'

1m

~

.....
co
~

r------------------------------------------------------------------------------------------,
Additional Applications

(Continued)

::i
-I

(ENCODER OUTPUT)
SERIAL INPUT_ _ _..J

____

~r-l~

______________________

~

______
____________________
____~----~r-l
~r--1~

________________

~r_l~

__________________

~r__l~

___________

r_l~

_________

______________________

~~

~r-l

rTL/H17911-20

FIGURE 11. Six Analog Channel Detector Waveforms
LM1871 Component Selection Guide
Component

Min

Typ

Max

RF

2kO

180kO

1M

CF

500pF

0.1 ",F

0.5",F

RM

2kO

150 kO

1M

Pin 15. Modulation timing resistor used with CT to set mod time
(tm). tm = 0.63 RMCT.

RCH

2kO

150kO

1M

Channel pins 1, 2, 3, 16, 17, 18. Variable or fixed resistor used
with CT to set channel pulse widths (tch)' tch = 0.63 RCHCT.

0.1 ",F

0.5",F

CT

500pF

Comments
Pin 7. Frame timer resistor used with CF to set frame time (tfl.
tf = RFCF + tm·
Pin 7. Frame timer capacitor used with RF.

Pin 8. Pulse timer capacitor used with RM and RCH.

CM

0.Q1 ",F

Pin 12. Modulation slew time (lms) capacitor used to decrease
modulator bandwidth. Reduces sideband emissions.
(IlV12)(CM)
= 7600CM
Ims =

C4

0.1 ",F

Pin 4. 4.6V regulator decoupling capacitor.

112

C13A
C13B

1500 pF
2700 PF

C14

0.1 ",F

R10

24 kO/51 kO

Pin 13. Modulator output RF decoupling capacitor. Improves
carrier ON to OFF ratio.
Pin 14. Vce decoupling capacitor.
Pin 10. RF oscillator Itransmitter bias resistor.

Note: See Figure 4 for RF components. All timing capacitors should be low-drift (NPO) types.

2-72

,-------------------------------------------------------------'r

...:s::co

Schematic Diagram

...
......

2-73

~

~
.....

:i
...I

r----------------------------------------------------------------------------,
NatiOnal

~ Semiconductor
Corporation

LM 1872 Radio Control ReceiverIDecoder
General Description

Features

The LM1872 is a complete RF receiver/decoder for radio
control applications. The device is well suited for use at either 27 MHz, 49 MHz or 72 MHz in controlling various toys
or hobby craft such as cars, boats, tanks, trucks, robots,
planes, and trains. The crystal controlled superhet design
offers both good sensitivity and selectivity. When operated
in conjunction with the companion transmitter, LM1871, it
provides four independent information channels. Two of
these channels are analog pulse width modulated (PWM)
types, while the other two are simple ON/OFF digital channels with 100 mA drive capability. Either channel type can
be converted to the other form through simple external circuitry such that up to 4 analog or up to 4 digital channels
could be created. Few external parts are required to complement the self-contained device which includes local oscillator, mixer, IF detector, AGC, sync output drivers, and all
decoder logic on-Chip.

• Four independent information channels; two analog and
two digital
• Completely self-contained
• Minimum of external parts
• Operation from 50 kHz to 72 MHz
• Highly selective and sensitive superhet design
• Operates from four 1.5V cells
• Excellent supply noise rejection
• 100 mA digital output drivers
• Crystal controlled
• Interfaces directly with standard hobby servos

Applications
•
•
•
•
•
•

Toys and hobby craft
Energy saving, remotely switched lighting systems
Burgler alarms
Industrial and consumer remote data links
IR data links
Remote slide projector control

Circuit Block and Connection Diagram
Dual-In-Line Package
LO

XTAL

GNO

VBIAS

MIX
OUT

IF IN

AGC

IF
OUT

MIX
IN

v+

CH A

CH A

CH B

GND

SYNC

CH 2

CH 1

CH B
TLlH17912-1

Bottom View

Order Number LM1872N
See NS Package Number N18A

2-74

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
Package Dissipation (Note 2)

Operating Temperature Range

-25·Cto +85·C
-65·C to + 150·C

Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)

260·C

7V

1600 mW
V+

Voltage@ Pin 7, 8, 9,10,11 or 12

DC Electrical Characteristics
v+

=

6V, TA

=

=

25·C, Test Circuit of Figure 1, flO

Parameter

49.890 MHz, flF

Conditions

=

Supply Voltage

Functional for VIN

Supply Current

CHA&BOff
CHA&BOn

VSIAS

@Pin4

Sync Timer Threshold

@ Pin 13, Going from
Low to High Voltage

100 P.V

=

455 kHz unless otherwise specified

Min

Typ

Max

2.5

6

7

V

9

13

18

mA

1.85

2.1

2.35

V

V+/2 - 0.4

V+/2

V+/2 + 0.3

V

0.4

0.7

27

Units

mA

DIGITAL CHANNELS A AND B
Saturation Voltage

@ Pins 7 & 9, RL

Saturation Resistance

@Pins7&9

=

1000

7

@ Pins 8 & 10,

Source Current

100

VPinB&Pinl0';;; 1V
Collector Pull-Up
Resistance

Pin7&Pin9toV+

Emitter Pull-Down
Resistance

Pin 8 & Pin 10 to GND

V

0
mA

5

10

20

kO

5

10

20

kO

0.45

0.7

ANALOG CHANNELS 1 AND 2

=

Saturation Voltage

@ Pins 11 & 12, RL

Saturation Resistance

@ Pins 11 & 12

Collector Pull-Up
Resistance

Pin 11 & Pin 12toV+

2 kO

160
5

10

V

0
20

kO

AC Electrical Characteristics
Typ

Max

Units

RF Sensitivity

Parameter

For "Solid" Decoded Outputs
(Note 1)

Conditions

Min

22

39

p.V

RF Sensitivity

Circuit of Figure 5 @49 MHz
with Antenna Simulation
Network of Figure 6

12

p.V

Voltage Gain

Pin 5 to Pin 15

58

dB

PSRR of RF Sensitivity

3V,;;; V+ ,;;; 6V

-1

%aN

BW

3 dB Down @ Pin 15

3.2

kHz

Noise

Referred to Input, Pin 5, VIN

0.35

p.Vrms

0.28

mVrms

AGC Threshold

Onset of AGC Relative to
RF Input, VIN, @ Pin 5

88

p.V

Referred to IF, Pin 15, VIN

=

=

0

0

Relative to IF Output @ Pin 15
Mixer Conversion
Transconductance

From Pin 5 to Pin 18

@ 1 MHz

V+ + 0.07

V+ + 0.100

V+ + 0.13

V

2.9

4.0

6.9

mmhos

@27MHz

3.7

mmhos

@49MHz

3.5

mmhos

2-75

fI

....co
....
::::E
C'I

....I

AC Electrical Characteristics (Continued)
Parameter

Min

Conditions

Typ

Max

Units

Mixer Input Impedance

Pin 5 to Pin 4 @ 49 MHz
(See Curves)

Mixer Output Impedance

Pin 18toGND

IF Transconductance

Pin 17 to Pin 15 (AGC Off) @455 kHz

IF Input Impedance

Pin 17toGND

5500

0

IF Output Impedance

Pin 15 to GND (AGC Off)

800

kO

2

MO

70

mVrms

20

p.V

20kO

+ 5pF

250

= 100 p.V

@ Pin 15, VIN
(AGCOn)

Detector Threshold

Relative to RF Input,
VIN,@Pin5

Analog Pulse Width
Accuracy

Ratio of Received Pulse Width
@Pins 11 & 12 to Transmitted
Pulse Width @Pin 5 for
VIN = 100 p.V

Relative to IF Output @Pin 15

V+

5.6

4.1

2.6

(AGCOn)
IF Carrier Level

kO

+ 0.015

V+

0.95

+ 0.025

mmhos

+ 0.040

V+

V

1.05

1.0

ms/ms

Note 1: The criteria for the outputs to be considered "solid" are as follows:
DIGITAL: In order to check the decoding section, four RF frames are inputted in sequence with the proper codes to exercise all four possible logical

output combinations at pins 7 and 9. For each Irame the proper output logic state must exist.
ANALOG: Each analog pulse width (measured at pins 11 & 12) in any 01 the above four successlvelrames must not vary more than ±5% from the pulse
widths obtained for Y,N = 100 p.V.
Note 2: For operation in ambient temperatures above 25D C, the device must be derated based on a 150"C maximum junction temperature and a package
thermal resistance of 75°C/W junction to ambient.
I

Typical Performance Characteristics

33

;;

.5
0-

I
~

~

30
21
24
21
18
15
12

Supply Current vs
Supply Voltage

-

DIGITAL
CHANNELSO~

./

./

...""

9

/'

-

-OIGITAL
._
CHANNELS OFF

I

2.0

~

.~
w

~

>

is
>=

~

0-

:l

5

~

1.8
1.8

2.0

~~~ Ip:~~211~8NuT
I
I

1.4
1.2
1.0

~
w

~
-

,,

I
I

3VS;

v' S;

~

&V

>=

~

0.8
0.&

,..
o

0.4
0.2

o

SUPPLY VOLTAGE IVI

~

3

4

5

6

7

~

V'

/

HIGH powEilfDISSIPATION REGION

0.2

"'"

o

I
40

-I-I-

80

I I
120

160

200

OUTPUT LOAD CURRENT (mAl

Mixer Transconductance (gm)
vs Input Frequency

IF Output Signal Level vs RF
Input Signal Level

6

TEST CIRCUIT OF FIGURE'

-'I
>!:
>

}

A

0.4

B 9 10

""~

30

;;

I
3V to exceed the duration (t'SYNC> of a receiver-based timer, thus allowing the
receiver to recognize this pulse for synchronization purposes. Taken in sequence, this collection of pulses constitutes
a single frame period (tF).

TX RF CARRIER (ASSUME PRIOR - - - fRAME CONTAINED 3 PULSES

REPRESENTlNGCHAANDCHBDffl ===~
RX DEMODULATED SIG

A FlIP·fLOP _ _ _- '
BFLlP·FlOP _ _ _ __

L--r-"lL_____________---'r
_ _ _ _--'r-"lL_____________

Cfllp·FLOP _ _ _ _ _ _ _- - - '
ANALOGCH 1 (PIN 11) _ _ _...

ANALOGCH2(PI.,,,

SYNC TIMER (PIN 13)

I----tSVNC---t

SYNC SIGNAL

----L--------.:==:..~It~::_..,
--e .--101ts

--,o::!n_L =;;:::--

READCDUNTERDNE-SHOT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
RESET COUNTER ONE·SHOT

::tC.::...-

~===============~====

OlGlTAlCHAIPINlI
DlGITAlCHBIPIN9) -

TLlH/7912-5

FIGURE 2. RX Timing Waveforms
LM1871
Pin Conditions

TX

LM1872

Transmitted Waveform

Binary
I----=...:::....::::;====---I------=..:...:::~----------t Pulse Count
Pin 5 (CH A) Pin 6 (CH B)

CHA

CHB

100

OFF

OFF

101

ON

OFF

110

OFF

ON

111

ON

ON

..1·----tF-----·~1

OPEN

OPEN

:J-O-[]-01"""----__

RX

Digital Outputs

TL/H/7912-6

GND

OPEN
TLlH17912-7

OPEN

GND

GND

GND
TLlH/7912-9

FIGURE 3. Digital Channel Encoding and Decoding via Pulse Count Modulation

2-78

Circuit Description

(Continued)

1.4V

AS
'iO

CHI

v'

i!A

·B

CH,

"'~--''''''--

TLlH17912-10
*Extemal parts
tDepending on layout, a small capacitance (10-47 pF)

may be required across pins 2 and 3 to ensure
oscilla1or s1art up.

FIGURE 4. Simplified Schematic Diagram

2-79

Circuit Description (Continued)
Thus either 3, 4, 5, or 6 channels are transmitted to represent the four possible codes that two digital channels represent. The receiver intrinsically counts channels with its decoder flip-flops by responding to the negative edges of the
demodulated RF waveform of which there is always one
more than the number of channels. The two LSBs of the
binary count are read, latched, and fed to the output drivers
which comprise digital channels A and B.

58 dB of gain using the suggested transformers in Figure 5.
The active digital detector provides an additional 30 dB gain
over a silicon diode resulting in an overall system gain of
88 dB. More or less gain can be obtained by using different
transformers. The frequency range of operation extends
from 50 kHz to 72 MHz encompassing a wide range of allocated frequency bands.
The short (1' to 2') vertical whip antenna that is typically
used has a very low radiation resistance (0.50 to 40) and
approximately 3 pF to 5 pF of capacitance. This antenna is
coupled to the mixer through a high Q tank consisting of C3

RECEIVER SECTION
The receiver circuit is a simple, single conversion design
with AGC which mixes down to 455 kHz and provides

.,
2D

----+---------.....-----.....------.
e5

::~~:~: o-....-'\M-...

"

T3

~100/.lF

1
01

eID

6V::::::::

~01
LD

MIX IN

v'

LM1872

TOOlC.

C1

~O.O1

TLlH/7912-11
Rl

Motor decoupling

R2

Sync timer, R2

t'

= o~;~~, R2 ,;; 470k

R3

Mixer decoupling

Cl

LO bypass; optional

C2

LO tank; C2 = 43 pF
= 24 pF

C3

Ant. input tank; C3

=
=

@
@

LO bypass

Ll

LO coil
Toko' 10k type (KXNA-4434 DZ) 9T; 0.8 p.H @ 27 MHz
Toko' 10k type (KEN·4028 DZ) 6T; 0.4 p.H @ 49 MHz
L 1 could be made a fixed coil, if desired.

Tl

-

455 kHz mixer transformer
Toko' 10 EZC type (RMC-202313 NO), Qu = 110
Pin 1-2, 131T; pin 2-3, 33T
Pin 1-3, 164T; pin 4-6, 5T

T2

-

455 kHz IF transformer
Toko' 10 EZC type (RMC-402503 NO), Qu
Pin 1-2, 98T; pin 2-3, 66T
Pin 1-3, 164T; pin 4-6, 8T

27 MHz
49 MHz

39 pF
24 pF

@
@

27 MHz
49 MHz

C4

VSIAS bypass

C5

Motor decoupling

C6

Sync timer, C6 = 0.7 R2' C6 ,;; 0.5 p.F

.

Cll

T3

t'SYNC

-

Ant. input transformer
Toko' 10k type (KXNA·4434 DZ), 3T sec. & 9T pri. of 0.8 p.H @ 27 MHz
Toko' 10k type (KEN·4028 DZ), 1 VoT sec. & 6T pri. of 0.4 p.H @ 49 MHz

C7

Mixer decouple; 0.01 p.F ,;; C7 ,;; 0.1 p.F

XI

3rd overtone parallel·mode crystal

C8

AGC

01

Electrostatic discharge (ESD) protection

C9

IF bypass; optional

cIa -

V+ bypass;

am

= 110

'Toke America
1250 Feehanville Drive
Mount Prospect, IL 60056
(312) 297·0070

p.F ,;; Cl0 ,;; 0.1 p.F

FIGURE 5. Typical Application Circuit for 27 MHz or 49 MHz

2-80

.-s:
......

Circuit Description (Continued)
and T3. This tank effectively keeps strong out-of-band signals such as FM and TV broadcast from cross-modulating
with the desired signal. When operating at 49 MHz or
72 MHz, CB interference is also effectively minimized. Image rejection is relatively low, however, being only 7 dB @
49 MHz, but this does not present a problem due to the
usual absence of strong interfering signals 910kHz below
the desired signal.

AGC is provided only to the IF; the mixer having sufficient
overload recovery for the magnitude of signals available
from a properly operating (i.e. good carrier ONIOFF ratio)
10,000 )LV/m transmitter. The AGC differential amplifier
regulates the peak carrier level to 100 mV by comparing it to
an internal 100 mV supply-referred voltage reference. The
resultant error signal is amplified and drives Q9 via rectifier
diode, D1, to shunt current away from Q10. C8 provides
compensation for the AGC loop which spans a 70 dB range.
The 100 mV AGC reference is accurately ratioed to the
25 mV detector reference to permit a controlled amount of
brief carrier loss before dropping below detector threshold.
Once into AGC, typically SO% amplitude modulation of the
PWM carrier is possible before the detector will recognize
the interference (see characteristic curves). This kind of
noise immunity is invaluable when the troublesome effects
of other physically close toys or walkie-talkies on the same
or adjacent frequencies are encountered.

The antenna signal is stepped down and DC coupled to the
mixer which consists of the emitter-coupled pair Q1 and Q2.
Emitter-follower, Q1, feeds the common-base device, Q2,
while effectively buffering the antenna from the LO energy
delivered by Q4. Mixer transconductance is 4 mmhos at low
frequency (1 MHz) falling to 3.3 mmhos at the upper end
(72 MHz).
The local oscillator utilizes an emitter coupled pair, Q3 and
Q4, for accurate control of mixer drive, 11. Quiescently, Q3
and Q4 share 11 set by 0.S9VIR5, but healthy voltage
swings at pin 2 due to oscillation of Q3 implement thorough
switching of the differential pair. As a reSUlt, the full 1.8 rnA
of drive "tailgates" (switches) the mixer emitter coupled
pair, Q1 and Q2. This current is well regulated from supply
voltage changes by the VSIAS circuitry. The TC of VSIAS is
positive by design in order to impress a positive TC on 11 so
as to compensate for the temperature dependence of bipolar transconductance in the mixer. Inasmuch as Q4 operates as an emitter-gated, common-base-connected device,
excellent isolation between local oscillator and mixer is obtained. As long as pin 4 is properly bypassed, Q5 presents a
low impedance to the base of Q4, resulting in low oscillator
noise. The oscillator easily operates up to 72 MHz with overtone crystals operating parallel mode.
The mixer signal is stepped down from the high Q mixer
tank, T1, and DC coupled to the IF via a secondary winding.
The IF stage consists of Q7, Q8 and Q10 and delivers a
transconductance of 4 mmhos @ 455 kHz. The quiescent
current, 12, is set at 120 )LA by VSIAS and a S.2k resistor.
Again, the positive TC of VSIAS is used to compensate for
the temperature dependence of transconductance. The impedance at the IF output, pin 15, is very high (:;;:800k) permitting the IF transformer, T2, to operate at near unloaded
Q (110). The overall 3 dB bandwidth of the receiver section
is 3.2 kHz (see characteristic curves); this is narrow enough
to permit adjacent channel operation without interference
yet wide enough to pass the 500 )Ls modulation pulses (tM
in Figure 2).
The IF signal is DC coupled to the digital detector which
consists of a high gain precision comparator, a 30 )Ls integrator, and a supply-referred 25 mV voltage reference.
Whenever the peak IF Signal exceeds 25 mV, the comparator drives Q11 to reset the digital envelope detector capacitor, C12. Since it takes 30 )Ls for the 1 ",A current source to
ramp C12 to the 3V (V+/2) necessary to fire the Schmitt
trigger, the presence of 455 kHz carrier (period = 2.2 ",s)
greater than 25 mVp will prevent C12 from ever reaching
this threshold. When the carrier drops out, the Schmitt trigger will respond 30 )Ls later. This delay (like that associated
with the burst response of the 455 kHz IF tanks) is constant
over the time interval of interest. Thus, it is of no consequence to timing accuracy because the LM1872 responds
only to negative edges in the decoder.

DECODER SECTION
The purpose of the decoder is to extract the time information from the carrier for the analog channels and the pulse
count information for the digital channels. The core of the
decoder is a three-stage binary counter chain comprising
flip-flops A, B, and C. The demodulated output from the detector Schmitt-trigger drives both the counter chain and the
sync timer (Q12, R2, CS, and another Schmitt trigger). When
the RF carrier drops out for the first modulation pulse, tM,
the falling edge advances the counter (see Figure 2). During the tM interval the sync timer capacitor is held low by
Q12. When the carrier comes up again for the variable
channel interval, tCH, CS begins to ramp towards threshold
(V+ 12) but is unable to reach it in the short time that is
available. At the end of the tcH period the carrier drops out
again, the counter advances one more, and the sequence is
repeated for the second analog channel. To decode the two
analog channels, 3-input NAND gates G1 and G2 examine
the counter chain binary output so as to identify the time
slots that represent those channels. Decoded in this manner, the output pulse width equals the sum of tM, a fixed
pulse, and tcH, a variable width pulse. A Darlington output
driver interfaces this repetitive pulse to standard hobby servos.
Following the transmission of the second analog channel, a
variable quantity from one to four, of fixed width pulses
(500 )Ls) are transmitted that contain the digital channel information. Up until the end of the pulse group frame period,
tF, the decoder responds as if these fixed pulses were analog channels but delivers no outputs. At the conclusion of
the frame the sync pulse, tSYNC, is sent. Since tSYNC is
always made longer than the sync timer period (t'SYNC =
3.5 ms), the sync timer will output a sync Signal to the first of
two cascaded 10 "'S one-shots. The first one-shot enables
AND gates G3 ~ GS to read the A and B flip-flops of the
counter into a pair of RS latches. The state of flip-flop A, for
example, is then stored and buffered to drive 100 mA sink or
source at the channel A digital output. An identical parallel
path allows the state of flip-flop B to appear at the channel
B power output. Upon conclusion of the 10 )Ls read pulse,
another 10 "'S one-shot is triggered that resets the counter
to be ready for the next frame.

2-81

co
......
N

~

~
..-

:E
....I

r--------------------------------------------------------------------------,
Application Hints
A typical application circuit for either 27 MHz or 49 MHz is
shown in Figure 5. Using the recommended antenna input
networks and driving the circuit through the antenna simulation network of Figure 6, a solid decoded output occurs for
10 p.V and 12 /LV input signals at 27 MHz and 49 MHz
respectively.

The primary tap on the IF transformer, T2, can also be adjusted (further from the supply side) for higher gain, but it is
possible to cause the AGC loop to oscillate with this method.
Narrow overall bandwidth is important for good receiver operation. The 3.2 kHz 3 dB bandwidth of the circuit in Figure
5 is just wide enough to pass 500 /Ls carrier dropout pulses,
tM, yet narrow enough to hold down electrical noise and
reject potentially interfering adjacent channels. In the
49 MHz band, the five frequencies available are only 15 kHz
apart. Should only two frequencies be used simultaneously,
these channels could be chosen 60 kHz apart. Should three
frequencies be used, the spacing could be no more than
30 kHz. At four or five frequencies, 15 kHz spacings must be
dealt with, making narrow bandwidth highly desirable. Even
at 27 MHz, where allocated frequencies are 50 kHz apart,
the proliferation of CB stations only 10kHz away represents
a formidable source of interference. The response of the
circuit of Figure 5 is 34 dB and 56 dB down at 15 kHz and
50 kHz away, respectively (see characteristic curves).

5 pF
41

GEN
10

3.9 @49 MHz
1@Z1MHz

H~""04
TLlH17912-12

FIGURE 6. Antenna Simulation Network
This sensitivity has been determined empirically to be optimum for toy vehicle applications. Less gain will reduce
range unacceptably and more gain will increase susceptibility to noise. However, should the application require greater
range (>50m for a land vehicle, for example), either the
antenna could be lengthened beyond 2' and/or receiver
sensitivity could be improved. There are a number of ways
to alter the sensitivity of the receiver. Decreasing the turns
ratio of input transformer, T3, for example, will couple more
Signal into the mixer at the expense of lower tank Q due to
mixer loading. Moving the primary tap on mixer transformer,
T1, further from the supply side and/or decreasing the primary to secondary turns ratio will also increase gain. For
example, just changing T1 from a 32:1 primary to secondary
ratio to a 5:1 turns ratio (Toko #RMC202202) will double
49 MHz sensitivity (6 /LV vs 12 /LV). Mixer tank Q will be
affected but overall 3 dB BW will remain largely unchanged.

The sync timer should have a timeout, t'SYNC, set longer
than the longest channel pulse transmitted, but shorter than
the shortest sync pulse, tSYNC, transmitted. Using the component values in Figure 5, t'SYNC, = 3.5 ms, which works
well with a transmitted sync pulse, tSYNC ;?: 5 ms.
Numerous bypass capacitors appear in the circuit of Figure
5, not all of which may be necessary for good stability and
performance. A low cost approach may eliminate one or
more of the capaCitors C1, C9, C10, and C11. The cleaner
and tighter the PCB layout used, the more likely is the case
that bypass capacitors can be eliminated. In the case of
marginal board stability, increasing the size of capacitors
C7, C9, and C10 to 0.1 /LF may prove helpful. If the PCB
layout and parts loading diagram shown in Figure 7 is used,
the circuit will be quite stable up to 72 MHz.

AN.

TL/H17912-13

FIGURE 7. PCB Layout, Stuffing Diagram and Complete
RX Module for Typical Application Circuit of Figure 5
2-82

TLlH/7912-14

Application Hints (Continued)
The digital channel output devices have significant drive capability; they can typically sink 100 mA and possess a 70.
saturation resistance. Through their emitters they can
source 100 mA up to 1V above ground for driving grounded
NPNs and SCRs. Unfortunately, this kind of drive capability
can cause thermally induced chip destruction unless total
power dissipation is limited to less than 1000 mW. It is good
practice and highly recommended to allow the digital output
devices to fully saturate at all times (sinking or sourcing) and
to limit the current at saturation to no more than 100 mA.
For extra drive the two digital outputs can always be
summed by connecting pin 7 to pin 9.
The IF frequency is not constrained to be 455 kHz. Operation is limited on the high end to about 1 MHz due to the
frequency response limitations of the active detector. The
low end is limited to about 50 kHz due to the envelope
detector integration time (Figure 4).

Applications
OPERATION AT 72 MHz
The licensed 72 MHz band is popular among hobby enthusiasts for controlling aircraft. The higher transmitted power
levels that the FCC allows yield much greater operating
range and the frequency band is uncluttered relative to
27 MHz. Elevated frequencies such as 72 MHz are no problem with the LM1872. The part is stable and will provide
good sensitivity and selectivity at that frequency. The application circuit in Figure 8 will provide a set of solid decoded
outputs for < 2 P.V of signal at the antenna input, which is
designed to match the 1000. resistive impedance of the y.,
wavelength antenna. IF bandwidth is a respectable 3.2 kHz.
For good immunity to overload from a very closely (antennas touching) operating high power transmitter, the transmitter design should emphasize a high carrier ON/OFF ratio. Using the LM1871 as a low power exciter to drive one or
more external class C power amplifier stages will result in a
simple, acceptable, low cost transmitter at 72 MHz.
Inasmuch as many hobby applications require more analog
channels than the LM1872 normally provides, particular attention should be paid to Figures 10 and 12 which describe
how to expand analog channel capacity up to 4 and 6 channels, respectively.

RECEIVER ALIGNMENT
The receiver alignment procedure is relatively straightforward because of an absence of interaction between the adjustments. First, the oscillator is tuned by adjusting L1 while
monitoring the LO Signal at pin 2 with a low capacity
("" 10 pF) probe. During tuning the amplitude will rise, peak,
and then abruptly quit. Adjust the coil away from the quitting
point and just below the amplitude peak.

OPERATION WITH AN IR CARRIER
An infra-red (or visible) light data link is a useful alternative
to its RF counterpart. Should the application demand that
the radiation not leave the room, or that it be directional, or
not involve FCC certification then a light carrier should be
given consideration. The principal drawbacks to this approach include short range (:;;;20 ft.) and high transmitter
power consumption. There is little that can be done to dramatically improve range, but short burst-type operation of
the transmitter will still permit battery operation.

In order to properly tune T1, T2, and T3, the RF Signal must
be provided through the receiver antenna by the specific
transmitter which is to be used with that specific receiver.
This is because the crystals which are commonly used with
these systems may have tolerances as loose as ± 0.01 %.
At 49 MHz the resultant ± 5 kHz deviation could easily put
the incoming signal out of the 3.2 kHz receiver IF bandpass.
The signal should be coupled through the receiving antenna
to ensure proper loading of the T3 input tank.
Alignment is easier with a defeated AGC, which is accomplished by merely grounding pin 16. The amplitude of the
455 kHz signal at pin 15 is used to guide alignment. Care
should be exercised that the signal swing not exceed roughly 400 mVp or diode, 02, in Figure 4 will threshold and
clamp the waveform. Also note that a standard 10 pF probe
at pin 15 will shift the IF tank frequency an undesirable
2 kHz. Unless a lower capacity probe is available, it is recommended that the signal be monitored at the unused secondary of T2. Although the Signal amplitude would be down
by a factor of 8.25 relative to pin 15, up to 50 pF probe
capacitance could be tolerated with negligible frequency
shift.
The incoming Signal is obtained by removing the antenna
from the transmitter and then locating the transmitter at a
sufficient distance from the receiver to give a convenient
signal level (~400 mVp) at pin 15. T3, T1, and T2 are then
tuned for maximum signal.

The information link (Figure 9a) consists of a light carrier
amplitude modulated by a 455 kHz subcarrier. The subcarrier in turn is modulated by the normal Pulse Width/Pulse
Count Scheme produced by the LM1871 encoder. A husky,
focused LED is used as the transmitter running Class A
100% modulated with an average current drain of 50 mA to
500 mA depending upon range requirements. The detector
consists of a large area silicon PN or PIN photodiode for
good sensitivity. The LM1872 will directly interface to such a
diode and give very good performance. Only a few nanoamps of photo current from 01 are required to threshold
the detector. Ambient light rejection is excellect due to the
very narrow bandwidth ("" 3 kHz) that results from the use
of three high Q 455 kHz transformers, T1, T2, and T3. Note
that the LO has been defeated and the mixer runs as a
conventional 455 kHz amplifier. Otherwise, circuit operation
is the same as if an RF carrier were being received.

2-83

PI

N
.....

CO
,....

:E

Applications (Continued)

..J

Rl

20

!~:~~::~~-t--~~--~-----------+-----------------------1~----------~'-------------'
+
C5
Tl00"F

+
Cl0

.

(DIGITAL OUTPUTSI

~'01
v'

MIX IN

LO

LM1872

AGC

16

IF OUT

SYNC

GNO

15

13

14

..ll.-JL
'::"

(ANALOG OUTPUTSI

C6

0.05
R2
lOOk

R3

200

To.

C7
01

TLlH/7912-15

Al

Motor decoupling

A2

Sync timer, A2

t'

= O~Y~~' A2 ,; 470k

A3

Mixer decoupling

Cl

La bypass; optional

=

22 pF

C12 -

Ant. input tank; C12 = 160 pF

L1

-

LOCoil
Toko 10k type (KENC) 4T; 0.2 I'H @ 72 MHz
L1 could be made a fixed coil, if desired

T1

-

455 kHz mixer transformer
Toko 10 EZC type (AMC-S02182). Qu = 110
Pin 1-2, 82T; pin 2-3, 82T
Pin 1-3, 164T; pin 4-6. 30T

72 MHz

T2

-

4SS kHz IF transformer
Toko 10 EZClype (AMC-S02S03), Qu
Pin 1-2, 82T; pin 2-3, 82T
Pin 1-3, 164T; pin 4-6, 8T

C2

La tank; C2

C3

Ant. input tank; C3

C4

VSIAS bypass

CS

Motor decoupling

C6

Sync timer, C6

C7

Mixer decouple; 0.01 I'F ,;; C7 ,;; 0.1 I'F

C8

AGC

Xl

Sth overtone crystal, parallel-mode. 72 MHz

C9

IF bypass; optional

Dl

Electrostatic discharge (ESD) protection

Cl0

V+ bypass; 0.01 I'F ,;; Cl0 ,; 0.1 I'F

@

72 MHz

@

= 24 pF @ 72 MHz

t'

= O~Y~~' C6 ,; O.S I'F

T3

-

= 110

Ant. input transformer
Toko 10k type (KENC), 4T sec &
2T pri. of 0.2 I'H @ 72 MHz

FIGURE 8. 72 MHz Receiver Circuit
In a practical remote data link, the transmitter could be battery operated and set up to transmit for brief intervals only in
order to save power. The brief transmission could be used
to set or reset the digital output latches in the LM1872 and/
or command new motor positions via the analog channels.
Alter transmission, the commands would be stored electri-

cally in the case of the digital channels and mechanically in
the case of the analog channels.
As a final note, if the case of D1 is connected to the anode
rather than the cathode, the circuit of Figure 9b should be
used at the input to maintain electromagnetic shielding.

2-84

r

s::
......

Applications (Continued)

CD

......

TO
LOADS

N
AI
20

DIGITAL
OUTPUTS

V+

LM1872

MIX OUT

IFIN

18

IF OUT

AGC

11

15

16

I O.'J

I

4

C8

6

':"

TO.

A2
lOOk

11 11

ANALOG
OUTPUTS

A3
20<1

C7

01

TL/H/7912-16

Bottom View
FIGURE 9a. IR Type Data Link
Rl

Load decoupling

R2

Sync limer; R2

~ _1_, R2
0.7C6

R3

Preamp decoupling

R5

Pholodiode decoupling

Cl

Photodiode decoupling

C2

VSIAS bypass

C3

V+ bypass

C4

Load decoupling

C5

IF bypass; oplional

C6

Sync limer, C6

~

Preamp decoupling

CB

AGC

T1

455 kHz preamp Iransformer
Toko 10 EZC type (RMC·502182), au
Pin 1-2, 82T; pin 2-3, 82T
Pin 1-3, 164T; pin 4·6, 30T

T3

01

-

-

-

Vactec
Vactec
UDT
UDT
Siemens

455 kHz IF Iransformer
Toko 10 EZC type (RMC·402503), au
Pin 1-2, 98T; pin 2-3, 66T
Pin 1-3, 164T; pin 4-6, 8T
455 kHz inpul transformer
Toko 10 EZC type (RMC-202313), au
Pin 1-2, 13IT; pin 2-3, 33T
Pin 1-3, 164T; pin 4-6, 5T

VTS5088
VTS6089
PIN6Dor6 DP
PIN 220 DP
BPY12

*

Cl
0.01

!sYNC, C6 :;; 0 5 f'F
0.7R2
.

C7

T2

Photodiode, 01

:;; 470k

-l

I

~

110

~

110

~

110

Active Area (cm2)
0.18
0.52
0.20
2.0
0.20

PI

R5
10k

...-.---'VIII\r--....::.o

If
TLlH17912-17

FIGURE 9b. Input Stage Where the Case of 01 is
Connected to the Anode

PN or PIN Silicon Pholodiode

2·85

Applications (Continued)
EXPANSION TO FOUR ANALOG CHANNELS

ceived between any two sync (or pseudo-sync!) pulses, the
channels are capable of toggling in step with the alternating
transmission of two and three channel pulse mini-groups
occurring within each half frame. Figure 10a reveals that
both digital channels A and B are high during the dual pulse
half frame and low during its triple pulse counterpart. Figure
10b shows just how simple the external circuitry can be.
Digital channel B drives the channel select pin of a quad 2input MUX that routes the LM1872 channels 1 and 2 outputs
to the four new outputs labeled analog 1 through 4.

For those applications that require more than the two analog channels that are normally provided, the LM1872 can
easily be expanded to 4 channels with appropriate external
circuitry. This is accomplished by creating a pseudo-sync
pulse (tps) among a six channel transmitted frame from the
LM1871 (Figure 10). The pseudo-sync pulse deceives the
decoder in the LM1872 causing premature recognition of
end·of-frame, effectively splitting a single frame into two.
The idea is to transmit analog channels 1 and 2 in the first
half of the normal frame period and analog channels 3 and
4 in the second half. External logic will then steer the four
channels from the LM1872's only two analog output pins
into four new analog outputs. Steering is accomplished with
the help of one of the digital channels. Inasmuch as the
digital channels respond only to the number of pulses re-

Although not the model of simplicity of Figure 10b, Figure
10c is a lower cost alternative that works just as well. The
diodes with the asterisk prevent a ground step from occurring that could false trip an excessively edge sensitive servo
and can be eliminated in many cases.

{i- - t F - - ' 1
4

TX

RX
OUTPUTS
PRIOR
TO
CHANNEL
SEPARATION

r A1 -r A2 j l-tps-I-A3-rA4-1

'--S-Y-NC--~

PSEUOO.SYNC

__~Il
____~Il

~L-_S_YN_C_ _

TX RF
SIGNAL

_______

CH 1
OUTPUT

_____

CH 2
OUTPUT

lL--

ANALOGL...---------.....IANALOG

1

3

Il~

ANALOGL...---------.....IANALOG

2

4
CH B
OUTPUT

Il
Il
__________________

---~ANALOG·L...-----------------------

ANALOG 1
(CH 1 OUTPUT)

1

AUXILIARY
DECODER
ANALOG
OUTPUTS

------~ANALOG·L...--------------------

2

________
Il

~IlL..._

ANALOG 2
(CH 2 OUTPUTI

ANALOG 3
(CH 1 OUTPUT)

ANALOG
3

-------------------~ANALOGL...-------

ANALOG 4
(CH 2 OUTPUT)

4
TUH17912-18

a) Transmitter, Receiver, and Auxiliary Decoder Timing Diagram
FIGURE 10. Deriving Four Analog Channels Through the Use of an Auxiliary Decoder

2-86

Applications (Continued)
v+
16

,.....--:.tSELECT

ANALOG I

CH B
(COll)
lMIB72

ANALOG 2

MM74C157
QUAD
2·INPUT

CH 2
12

MUX

ANALOG 3

ANALOG 4

Tl/H/7912-19

b) Simple Decoding of Four Analog Channels with CMOS
ANALOG

.

OUTPUTS

CH 1
CH2

II

10k

12

10k

v+

5k
10k

CH A (COll)
lM1B72

10k
CH A (EM)
lOOk

CH 8 (COll)
CH B (EM)

'See Text

c) Low-Cost Decoding of Four Analog Channels with DTL

Tl/H/7912-20

FIGURE 10. Deriving Four Analog Channels Through the Use of an Auxiliary Decoder (Continued)
11). Toggling digital channel A, either directly or through an
inversion, is used to suppress a given receiver's analog output when the undesired analog channels are transmitted. In
this manner, only the desired analog channel is outputted at
each receiver. The amount of external circuitry required to
do this is minimal; two receivers require a single transistor
apiece while the other two receivers need no extra parts at
all.

FOUR SINGLE CHANNEL RECEIVERS
DRIVEN FROM A SINGLE TRANSMITTER
When it is desired to control more than two vehicles or remote stations with the analog information from a single
transmitter, the LM1872 can be put to the task. By utilizing
the frame splitting technique previously described in Figure
10, up to four independent single analog channel receivers
can be made to operate from a single transmitter (Figure

2-87

Applications (Continued)

n

- - lr--1I

CHI
OUTPUT

ANALoG.....- - - - - - - -.......ANALoG......- - - - - - - - -

I

n

3

_ _ _ _ _.....

n

CH2
OUTPUT

ANALOG~--------.......ANALOG!-------

RX

2

4
....._ _ _ _ _ _ _ _ _ _ _ _ CHA
OUTPUT

CH B
L..._ _ _ _ _ _ _ _ _ _ _ _ _ OUTPUT

--.II

ANALOG~---------------------I

AUX

...,

!

!

-----~ANALOG·L...-------------------

DECODER

n

2

--------------~ANALOG......- - - - - - - 3

n

ANALOG I
OUTPUT

ANALOG 2
OUTPUT

ANALOG 3
OUTPUT

ANALOG 4
OUTPUT

- - - - - - - - - - - - - - - - - - - - - - - -.......A·NAlOG·L...------4
TL/H/7912-21

a) Transmitter, Receiver, and Separated Channels Timing Diagram

CH 1

ANALOG 1

CH I

LM1872

LM1872
RX NO.1

RX NO.3

CH A
(EM)

12

LMI872
RX NO.2

ANALOG 3

CH A
(COLL)
CH A
(EM)

-

CH 2 ....-

11

CH 1 ~--,,--o ANALOG 4

...--0 ANALOG 2
LMI872
RX NO.4

CH A
(COLL)

CH A
(COLL)

CH A
(EM)

TL/H/7912-22

b) Simple Channel Separation with Two External Transistors
FIGURE 11. Obtaining Four Independent Single Analog Channel Receivers from a Single Common Transmitter

2-88

r-

Applications

(Continued)

--....s::
00

EXPANSION TO SIX ANALOG CHANNELS
Still greater analog capacity can be obtained with an outboard auxiliary decoder. The LM1872, a simple comparator,
and an 8-bit parallel-out serial shift register comprise a six
analog channel receiver/decoder (Figure 12). The one transistor comparator reconstructs the detector output of the
LM1872 from the sync timer waveform and feeds it to the
clock input of the shift register. The channel 1 output then
loads a "one" into the register and the clock shifts the
"one" down the line of analog channel outputs in accordance with the time information from the detector output.
Note that the reconstructed detector waveform lags the
channel 1 output very slightly ("" 10 ,",s) due to the finite
slope of the sync capacitor discharge edge. This delay is
very important as it insures that channel 1 is high when the
clock strikes initially (thus loading a "1") and low for each
subsequent positive clock edge (thus preventing the loading
of extraneous "1's").

CONVERTING AN ANALOG CHANNEL
TO A DIGITAL CHANNEL
Either analog channel can be converted to a digital channel
with the aid of a low cost CMOS hex inverter (Figure 13).
The internal 10k resistor and external capacitor, C1, set a
time constant (1 ms) that falls between a short (0.5 ms) and
a long (2 ms) transmitted pulse option. For pulses longer
than 1 ms, the first inverter will pull low momentarily once
each frame. Repetitive discharges of C2 prevent it from ever
reaching threshold (V+ /2) because the R1 C2 time constant is set longer (70 ms) than the frame period. With the
inverter input below threshold, 01 will energize the load. For
analog output pulses shorter than 1 ms, the first inverter will
back bias D1 allowing C2 to ramp past threshold and 01 to
go off. For extra output drive, the remaining inverters in the
package can be paralleled to drive 01. Alternatively, for light
loads 01 can be eliminated altogether.

N

TX RF - - - - - - - ,
SIGNAL _ _ _ _ _ _.....
SYNC TIMER
ILMI812 PIN 131

RECONSTRUCTED
DETECTOR
OUTPUT
IMM14CI64PIN81 _ _ _ _ _ __
LMI812 CH I OUTPUT
ANALOG 1

~

------~
10",~"--~

--Ir-l...____________

ANALOG2 _ _ _ _ _ _ _ _

-....IIIL__________
r-,L-_______
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _...JIIL_____

ANALOG 3 _ _ _ _ _ _ _ _ _ _

ANALOG4 _ _ _ _ _ _ _ _ _ _ _ _ _...
ANALOGS

-'r-lL___

ANALOG6 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

TL/H/7912-23

a) Six Channel Timing Diagram
V+=6V

4.1k

....-+--+---"""'"18 CLOCK

PI

ANALOG

-1

4

SYNC 1'1;;.3..............

ANALOG

3
ANALOG

2

LM1812

ANALOG
I

210

14

TL/H/7912-24

b) Six Channel Auxiliary Decoder
FIGURE 12. Deriving Six Analog Channels

2-89

~

t;
....

:iii
...I

r---------------------------------------------------------------------------------,
Applications

(Continued)

Where only one of the two available analog channels needs
conversion to a digital format, the LM555 approach offers
simplicity combined with up to 150 rnA of output drive (Figure 14). The trailing edge of CH 1's output pulse is used to
reset the timer in preparation for comparing CH 2's pulse
width to the time constant (1.1 ms) set by the internal 10k
resistor and C1. For CH 2 pulse widths greater than 1.1 ms
C1 ramps to threshold, setting an internal latch in the

LM555 and causing the load to be energized. Due to the
timing of the reset pulse, however, the LM555 output will go
high again for 1.1 ms during the next pulse comparison cycle thus producing an ON state duty cycle of about 95%.
For most commonly encountered loads such as motors, solenoids, lamps, and horns, this is of little consequence. The
OFF state duty cycle is 100%.

v' =6V

TL/H17912-25

FIGURE 13. Conversion of an Analog Channel
to a Digital (On/Off) Channel

v' =6V

"'--1~

LMI872

__..__......;6~

THRESHOLD

LM555

v'
CONTROL

RI
lOOk

...-1----1 !-=O::::.O:::;OI~_-=-t TRIGGER

DISCHARGE 7

TL/H17912-26

FIGURE 14. Simple Conversion of an Analog to a Digital Channel

2-90

Applications (Continued)
BRIDGE DRIVING A MOTOR

come from the power feed leads and/or directly from the
brushes. Usually proper lead dress and board orientation
coupled with a good filter network (see Figure 16) will eliminate any problems. In particularly stubborn cases of motor
interference, the digital channels may experience more objectionable interference than the analog channels. This is
generally not because the digital channels are more susceptible, but rather because the type of load they typically drive
(i.e. a horn) will make more of a nuisance of itself than a
typical analog load (i.e. a steering servo) when subjected to
interference.

The two digital channels can be used to propel a car forward, off, and reverse without the need for a costly servo
(Figure 16). The 100 mA digital output capability is used to
drive a bridge of four transistors with 05 added as a protection device. Should an erroneous command to power both
sides of the bridge occur (as may happen due to noise with
the car out of range) the large motor drive transistors would
fight one another resulting in the thermal destruction of one
or more of those devices. But 05 will disable the left side of
the bridge whenever the right side is powered, preventing
the problem from ever occurring. The motor noise suppression network shown has proven to be especially effective in
reducing electrical noise and is therefore highly recommended.

Straightforward time integration of the digital channel outputs works very well with any type or degree of motor interference. The simple circuits of Figure 17 integrate over a
period of about three frames (70 ms) and have approximately equal delay either going off or coming on.

NOISE INTEGRATION OF A DIGITAL CHANNEL

Commonly available inexpensive DC motors are a formidable source of electromagnetic interference. Radiation can

v+

LM1872
10k

11

14

TUH/7912-27

FIGURE 15. Interfacing Directly to Standard Hobby Servos

2-91

~

IX;

....

r------------------------------------------------------------------------------------------,
Applications (Continued)

!l

lM1B72

v+
10

TUH17912-28

FIGURE 16. Digital Bridge Motor Drive

TL/H/7912-29

b) High Current Load

a) Low Current Load

FIGURE 17. Integrating a Digital Channel Output to Achieve Noise Immunity

2-92

~ Semiconductor
NatiOnal

Corporation

LM 1884 TV Stereo Decoder
General Description

Applications

The LM1884 is a decoder designed for television stereo. An
L·R output is provided to drive further audio processing.

•
•
•
•

Features
• Low impedance L + Rand L - R outputs
• Mono/Stereo switching and indication
• Low distortion-O.10% typical

Stereo television sets
Stereo adapters
Cable television
Auto sound

Block Diagram

COMPOSITE-l
INPUT

PILOT
DETECTOR

SCHMITT
TRIGGER

STEREO

IINO~~T\IR

~

I
I

REGULATOR

_____

H--

Vee

~_..J

lM1B84

l-R
OUT

TLlH/6759-1

Order Number LM1884N
See NS Package Number N16A

2·93

~ r-------------------------------------------------------------------------------------~

co
co

....--

:i!!

Absolute Maximum Ratings TA= + 25°C unless otherwise noted
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Supply Voltage
Power Dissipation (Package Umitation)
Derate Above T A= + 25°C

Operating Temp. Range (Ambient)

-400C to + 85°C

-65°C to + 150°C
Storage Temperature Range
Lamp Drive Voltage
Max Voltage at Pin 7 with Lamp "Off"
16V
Lamp Current
100mA
Lead Temperature (Soldering 10 sec.)
2600C

16V
1800mW
15mWrC

Electrical Characteristics
Parameters Guaranteed by Electrical Testing Test Circuit, TA= + 25°C, Vcc=12V unless noted

I

Parameter

I

Conditions

DC

I

Min

Typ

I

Max

I

Units

VIN = 0
Supply Current

Vcc=16V

15

33.5

50

mA

Output Voltage

Pin 4

1.7

3.5

5.0

V

Output Voltage

Pin 5

1.7

3.B

5.0

V

Output Impedance

Pins 4, 5

100

300

{}

Lamp Leakage

Lamp off, pin 7 voltage= 16V

0.1

mA

Lamp Saturation Voltage

Lamp on, pin 7 current= 100 mA

2.0

V

Audio Composite signal with 3B kHz subcarrier and 10% 19 kHz pilot, fmod = 1 kHz. Adjust P1 for 19 kHz ± 10Hz.
L+R Channel Gain

VIN=2.5VppL=R,pilotoff,pin4

L + R Channel THD

VIN = 2.5Vpp L = R, pilot off, pin 4

O.B

Gain Ratio, L + R Channel
to L - R Channel

VIN = 2.5Vpp, L only

Supply Rejection

100 mVrms, 1 kHz on supply, VIN=O

DC Output Shift,
Mono to Stereo

Pilot off to on, pins 4, 5

Input Impedance

Pin 1

1.0

1.2

0.1

1.0

%

-2.0

0.0

2.0

db

30

60
±20

mV

150

k{}

15

50

db

PLL
Pilot Level for Lamp On

12

20

mV

Pilot Level for Lamp Off

3

10

mV

Capture Range

±0.5

Pilot = 25 mVrms

%

Test Circuit

FM STEREO

"::"

COMPOSITE~.f- i--JI,
119kHz

~L~

~J

12

2C\

Y.~

•

0.0062pF

10'11

7k5

'Metal film. zero temperature

4

~1J" 6

C6

C7

0.01 pF

0.01 ,F

~
5.lk

"::"

coefficient resistor recommended

2-94

~
5.1k

L+R L-R
----...-......
OUTPUTS

FIGURE 1

R7

680

~

......"""..-tile-t-+vco
7k5

~

INDICATOR
LED

"::"
TUH/6759-3

Typical Application
Vee
BVue-16 Vue

PI
5k

VCO
ADJUST

COMPOSITE
INPUT

----i'7 ~+~+-----'
Cl
2.2.F
STEflEO

INOICATOR
LED
":'

•

L+R

L-R

J

":'

OUTPUTS

TLlH/6759-2

• Metal film, zero temperature
coefficient resistor recommended

35

<"
oS

~

35

I

34

MolD

a:

33

~

32

El
II:

ill

..

§
9a::

I
8

'"

...oS
is!

I
STEREO

3D

100
90
BO
70
60
50
40
3D
20
10

19.2

r-r--r-r-,---r---,r-r---,

~ lB.9

1-+--+--t--f--t--1f--t--l

W

f-- -

I

31

VCO Frequency vs
Supply Voltage

Capture Range vs
Pilot Level

Supply Current vs
Supply Voltage

\.
\..

o

lB

10 11 12 13 14 15 16

SUPPLY VOLTAGE (V)

,

ffi

fi! lB.B 1-+-++-+--+---'1-1--1
fE

/

"'" to'

18.7

19
FREQUENCY (kHz)

Power Supply Rejection
vs Supply Voltage

_ o. 7

:!

20

I-+--+--t--f--t-f--t--l

18.6 '--l.-l.-.l.-.l.-.J-..I-..I-...J
8
10 11 12 13 14 15 16

SUPPLY VOLTAGE (V)

Total Harmonic Distortion vs
Composite Input Level
r:-::-:-:-:--r~-r--'-'-r-r--,

z

0.6

...c;

0.4 HH-f+

III5 0.5

.

l§

0.3 H-I--f(I.-'

~ 0.2

....

H-t-fl--I--H,"__

~ 0.1

10~~~'--.l.-.J-.J-..I-...J

8

9 10 11 12 13 14 15 16

SUPPLY VOLTAGE (V)

HH-f±...t'9--+-1......9--l
o U!!!~:t:IIJ--LU
o 0.8 1.6 2.4 3.2 4.0
COMPOSITE INPUT LEVEL (Vp-p)
TL/H/6759-4

2-95

~r-----------------------------------------------------~

co
o
CW)

NatiOnal

Semiconductor
:l ~ Corporation

LM3089 FM Receiver IF System
General Description
The LM3089 has been designed to provide all the major
functions required for modern FM IF designs of automotive,
high-fidelity and communications receivers.

Features
• Three stage IF amplifierllimiter provides 12 fLV (typ)
-3 dB limiting sensitivity
• Balanced product detector and audio amplifier provide
400 mV (typ) of recovered audio with distortion as low
as 0.1 % with proper external coil designs.

• Four internal carrier level detectors provide delayed
AGC signal to tuner, IF level meter drive current and interchannel mute control
• AFC amplifier provides AFC current for tuner and/or
center tuning meters
• Improved operating and temperature performance, especially when using high Q quadrature coils in narrow
band FM communications receivers
• No mute circuit latchup problems
• A direct replacement for CA3089E

Connection Diagram
Dual-In-Line Package
NIC

116

A~C

115

GND

114

TUNE
MEIER

MUTE
LD~IC

113

112

REF
BlfS

110

QUAD
INPUT

19

D
J:
OUT

r

OUT

TL/H17149-2

Top View
Order Number LM3089N
See NS Package Number N16E

2-96

aJ

0'
n
~

KAC-K2318HM'

r------,

C

I-I

II
I

f±jOOPF

L ___

iii'

ea

II
I
-l

Dl
3

22"H
~~~'-~--~~--'REF

v'

IF OUTPUT

5.1k
~_BI_A_S------~IV~---------,
10

r

0.02"F

~

DELAYED
AGe FOR
RF AMPLIFIER

~
10k
14

MUTING
SENSITIVITY
TLlH/7149-1
Toka America
1250 Feehanville Drive
Mount Prospect, IL 60056
(312) 297-0070

m

680&W1

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage Between Pin 11 and Pins 4, 14
+16V
DC Current Out of Pin 12
5mA
DC Current Out of Pin 13
5mA
DC Current Out of Pin 15
2mA

Power Dissipation (Note 2)
Operating Temperature Range
Storage Temperature Range
Lead Temperature
(Soldering, 10 seconds)

Electrical Characteristics (TA = 25'C, Vee =

I

Symbol

I

Parameter

DC CHARACTERISTICS (VIN

I

= 0, NOT MUTED)

DYNAMIC CHARACTERISTICS fo

260'C

+ 12V, see Test Circuit)

Conditions

Supply Current
IF Input and Bias
Audio Output
AFCOutput
Reference Bias
Mute Control
IF Level
DelayedAGC

111

V1, 2, 3
V6
V7
V10
V12
V13
V15

1500mW
-40'Cto +85'C
-65'Cto + 150'C

Min

I

16
1.2
5.0
5.0
5.0
5.0

Typ

23
1.9
5.6
5.6
5.6
5.4
0
4.7

4.2

I

Max

30
2.4
6.0
6.0
6.0
6.0
0.5
5.3

I

Units

mA
V
V
V
V
V
V
V

= 10.7 MHZ, af = ±75 kHz @ 400 Hz

Input Limiting -3 dB
12
25
p.V
55
-dB
AM Rejection
VIN = 100 mY, AM: 30%
45
400
Recovered Audio
300
500
mVrms
VIN = 10mV
Total Harmonic Distortion
Single Tuned (Note 1)
1.0
%
0.5
VIN = 100mV
%
Double Tuned (Note 1)
0.1
0.3
VIN = 100mV
Signal to Noise Ratio
70
dB
60
S+NIN
VIN = 100mV
V
V12
Mute Control
0.5
0
VIN = 100mV
V13
IF Level
4.0
5.0
6.0
V
VIN = 100mV
V
1.5
V13
IF Level
1.0
2.0
VIN = 500 p.V
V15
DelayedAGC
0.1
0.5
V
VIN = 100 mV
DelayedAGC
2.5
V
V15
VIN = 30mV
-dB
Audio Muted
60
VO(AF)
VIN = 100mV, V5 = +2.5V
Note 1: Distortion is a lunction 01 quadrature coil used.
Note 2: For operation in ambient temperatures above 25'C. the device must be derated based on a 15O'C maximum junction temperature and a thermal resistance
of 8!Y'C/W iunction to ambient
VIN(LlM)
AMR
VO(AF)
THD

Typical Performance Characteristics
Typical AGC (Pin 15) and
Meter Output (Pin 13) vs
IF Input Signal

Typical S + N/N and IF Limiting
Sensitivity vs IF Input Signal
AUDIO OUTPUT! 15 kHz DEVIATION

0
10
20

1/11111111 III I

JIIIIIIIII 11111
,
NOISE OUTPUT

3\J

r-- HP334A DISTORTION ANALVZERI

40
5a

60
70
80

6
5

Pin 15

•
/

1
10 100 lk 10k lOOk
IF INPUT VOLTAGE (.VI

/

Pin 13

~

3
2

1

AM Rejection (30% Mod) vs
IF Input Signal

k;"

ZI

1

I \
\
,. ,

.

10 100'5 lk 10k lOOk
IF INPUT VOLTAGE -uV
z

5

2·98

0
10
20
30
40
50
60

70
1

10

,.

100
10k lOOk
IF INPUT VOLTAGE ,"VI
TUH17149-3

r----------------------------------------------------------------------, •
3:
w
oQC)
co

Schematic Diagram

.~~

~~

.l;;;
~~

~2

tt
ttlg

.l~
I
~~

~;



!

;::
::.
~

..
..

\
l\

4D
5D

C>

60

::.

\

3D

~

Q

1\

lD
2D

\

,
3

\

10

IO. J.1'

\

80

o

0.5

LM3089

1

2.6

1.5

2

MUTE INPUT VOLTAGE (PIN 5) (V)
TLlH17149-6

TL/H17149-7

AC Test Circuit
3k

.-I
KAC·K2318HM

'SINGLE TUNED
DETECTOR COIL

I
I
I

I

.------,
I-I I
I

I

I I

I

I I
I I
I I
_J L

I
I
L..
3.9k

~

"DDUBLE TUNED
DETECTOR COIL

---,

100 pF

'For single tuned dectector coil:

La tunes with 100 pF at 10.7 MHz
OUl (unloaded) .. 75
OLCloaded) '" 13 for V9 '" 150 mVrms

-

··For double tuned detector coil:

-"

OULPRI - QULSEC '" 75
kO '" 0.7 for V9 .. 150 mVrms

Note:

100 pF

The recovered audio output voltage wi)) be approximately 0.5 dB less when
using the double tuned detector coil.
For proper operation of the mule
150 mVrms ±30 mV.

8.2k
TLlH17149-8

2-100

circui~

the RF voltage at pin 9 should be

AC Test Circuit

(Continued)

TLlH17149-9

2-101

_

National

Semiconductor
Corporation

LM3189 FM IF System
General Description

Features

The LM31 B9N is a monolithic integrated circuit that provides
all the functions of a comprehensive FM IF system. The
block diagram of the LM31 B9N includes a three stage FM IF
amplifier/limiter configuration with level detectors for each
stage, a doubly balanced quadrature FM detector and an
audio amplifier that features the optional use of a muting
(squelch) circuit

• Exceptional limiting sensitivity: 12 p.V typ at -3 dB
point
• Low distortion: 0.1 % typ (with double-tuned coil)
• Single-coil tuning capability
• Improved (S + N)/N ratio
• Externally programmable recovered audio level
• Provides specific signal for control of inter-channel muting (squelch)
• Provides specific signal for direct drive of a tuning meter
• On channel step for search control
• Provides programmable AGC voltage for RF amplifier
• Provides a specific circuit for flexible audio output
• Internal supply voltage regulators
• Externally programmable ON channel step width, and
deviation at which muting occurs

The advanced circuit design of the IF system includes desirable deluxe features such as programmable delayed AGC
for the RF tuner, an AFC drive circuit, and an output signal
to drive a tuning meter and/or provide stereo switching logic. In addition, internal power supply regulators maintain a
nearly constant current drain over the voltage supply range
of +8.5V to + 16V.
The LM3189N is ideal for high fidelity operation. Distortion
in an LM3189N FM IF system is primarily a function of the
phase linearity characteristic of the outboard detector coil.
The LM3189N has all the features of the LM3089N plus
additions.
The LM31B9N utilizes the 16-lead dual-in-line plastic package and can operate over the ambient temperature range of
- 40'C to + 85'C.

Block Diagram

22,H

TO INTERNAL
REGULATORS

11

LM31nN

7

'"

AFt

OUTPUT

"

*10~F
AUDIO
OUTPUT

'"

12

,..

'10

"

13

TO STEREO

'}-01111,,"',-~T:::U'::::":::G-::M::ET::'R--o ~~:~~~i:UlTS
OUTPUT

U

ON CHANNEL

,0.

MUTING

SENSITIVITY

INDICATOR

u,
TUHI7960-1

All resistance values are in a
'L tunes wI1h 100 pF eC) at 10.7 MHz. 00 .. 75
(Toko No. KACS K586HM or equivalent)

2-102

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage Between Pin 11 and Pins 4, 14
16V
DC Current Out of Pin 12
5mA
DC Current Out of Pin 13
5mA
DC Current Out of Pin 15
2mA

Electrical Characteristics TA = 25·C, v+
Symbol

Power Dissipation (Note 2)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)

= 12V

Conditions
(See Single-Tuned Test Circuit)

Parameter

1500mW
-40·C to +85·C
-65·C to + 150·C
260·C

Min

Typ

Max

Units

20

31

44

mA

1.2
1.2
1.2
7.5
5

2.0
2.0
2.0
9.5
5.75

2.4
2.4
2.4
11
6

V
V
V
V
V

12

25

45

55

325

500

650

mV

0.5
0.1

1

%
%

STATIC (DC) CHARACTERISTICS
111

Quiescent Circuit Current

Vl
V2
V3
V15
Vl0

DC Voltages:
Terminal 1 (IF Input)
Terminal 2 (AC Return to Input)
Terminal 3 (DC Bias to input)
Terminal 15 (RF AGC)
Terminal 10 (DC Reference)

No Signal Input, Non Muted

DYNAMIC CHARACTERISTICS
V,(lim)

Input Limiting Voltage (-3 dB Point)

AMR

AM Rejection (Term. 6)

= 0.1V
AM Mod. = 30%

VIN

Vo(AF)

Recovered AF Voltage (Term. 6)

THO

Total Harmonic Distortion (Note 1)
Single Tuned (Term. 6)
Double Tuned (Term. 6)

S+ N/N

Signal Plus Noise to Noise Ratio
(Term. 6)

fOEV

Deviation Mute Frequency

V16

RF AGC Threshold

VIN

fa = 10.7 MHz,
fmod = 400 Hz,
Deviation ± 75 kHz

= O.lV
65
fmod

=0

fLY
dB

80

dB

±40

kHz

1.25

V

0
fOEV < ± 40 kHz
V
5.6
fOEV > ± 40 kHz
Note 1: THO characteristics are essantially a function of the phasa characteristics of the network connected between terminals 8,9, and 10.
Note 2: For operation in ambient temperatures above 25'C, the device must be derated based on a t 50'C maximum junction temperature and a thermal resistance
of 80'C/W junction to ambient.

V12

On Channel Step

VIN

= O.lV

Connection Diagram
Dual-In-Line Package
TUNE

AGe

116

AGe

115

GND

114

METER

113

MUTE
LOGIC

112

Vee

j;1

REF
BIAS

110

QUAD

INPUT

I,

P
),: DEcoi;PLE

r IF!:O MJ: Au!~D

BIAS

INPUT

OUT

J: J:
OUT

OUT

Tl/HI796D-2

Top View
Order Number LM3189N
See NS Package Number N16E
2-103

Test Circuits
Test Circuit for LM3189N Using a Single-Tuned Detector Coil

r----'I

I

All resistance values are in n

l'

I

'L tunes with 100 pF (C) at 10.7 MHz,
Qo(unloaded) '" 75 (Taka No. KACS K586HM
or equivalent)

c

I

'OOp'

I
I

"c =0.Q1 "F for 50 "s de-emphasis (Europe)
= 0.015 "F for 75 "s de-emphasis (USA)
3.9k

v+=t2V

5'

1"0#'

.>....::..-------.....---.-:~~~gT
1'c"
47D~

TO
PIN 13

-:::'0'1 0.#'
33

TUNING METER
15G,.!A

fULL· SCALE

TL1H17960-3

Test Circuit for LM3189N Using a Double-Tuned Detector Coil

r----,

I

All resistance values are in n

I
I
I

(squelch) clreuit "E" type slugs, spacing 4 mm

=

I

lOOp'

I
I __ T'_ I
I
I
cz
I
I

Above values permit proper operation of mute

"c =0.01 "F for 50

3'

I~'III

'T:PRI-Oo(unloaded-- '" 75 (tunes with 100 pF
(CI2» 20t of 34e on 7/32' dia form
SEC-Oo(unloaded) '" 75 (tunes with 100 pF
(C2» 201 of 34e on 7132" dia fOlm
kQ(pereent of critical coupling) '" 70%
(adjusted for coil voltage (Vel = 150 mV

"S

I

de-emphasis (Europe)
0.Q15 "F for 75 ". de-emphasis (USA)

,oOp'

I

8."

J
8.2k

v+", 12V

O,D5 PF *

5k

1'10#'

.>....::..-------...---.-~~~~~T
L--_H'~

1'C"
410.1

TO
PIN 13

-:::'0'1

0 33
. ,'

TUNING METER
150,1lA
FULL· SCALE

TL/HI7960-4

2-104

Complete FM IF System for High Quality Tuners
The circuit provides a complete FM IF system for a high
quality receiver. Either one or two stages of amplification
and bandpass filtering may be desired, depening on the

receiver requirements. See graph for Typical Limiting and
Noise Characteristics for each circuit configuration which
can be compared to the LM3189N alone.

Complete FM IF System for High Quality Receivers
Uk

---------------oI2.

. -....- -.......,........t - -....
10llf

l.llr

J9D

J.3.

390

T

"*

10nF

47

10nF

... AUDIO

~...!...._ _ _--<~-:-_...,..

,,'

!-

J.9nF

47k
10.1MHZ

FROM
TUNER

All resistance values are in

n

CF: Ceramic filters, Toko CSFE or equivalent
'L tune. with 100 pF (C) at 10.7 MHz
Qo(unloaded) '" 75 (Toko No. KACS K586 HM

-o.v

.....- ...- .....-+--<..-.--
t-

-10

;a

,

6

1\

1

~

0

CO

1

100

10

Il

10k

1

lOOk 1000k

IF INPUT VOLTAGE ,"V)

2

3

5

If

~:g
UW

-10

~!

5~ -20

"w
!2~

....."''''"
.

IPIlllj"PlNU'1

r-- .,...

~VOLTAOISllrrL'f

AIdIlllftTiMnUTURE

OITfUTtUFt
COORDIIATEI

10

20 30

f--

",

w2 -40

>t-

-60

-

TurCI::t~~~ I

UI SlIIGU TUlIlO

'I"'\.1""~ ~

l;~o
7'~~
1

10

100

1k

.
i
..

f---

G

,.,

f---

4

S

~

2

<
co

200
150

I!!

100

~

60

110

...

100

z

60

."
~"
..

W

o
-50

V

'"~ -100
-150
-100

~

80

0

.~..
w

2D
D
5

-

10

15

-1ZV

..-

/

/

V

/
-50

0

50

100

150

Typical Limiting and Noise
Characteristics

0

I'

40

3

AI - CHANGE IN FftEQUENCY (kH,)

ii
:!! -10

\
\

2.5

/

t-

0
10D1c

,

140

2

/

:I!

z

v·

~
,

~

co

1.5

:£8~:~~~::T~~JrftC~::'C ; - -

-'I

3.6V)
1 Vrms
Mute Function (pin 14)
-0.7t05Vp
Operating Ambient Temperature Range
O'Cto +70'C
Storage Temperature Range
- 55'C to + 150'C

Soldering Information
Dual-In-Line Package
Soldering (10 seconds)
260'C
Small Outline Package
Vapor Phase (60 seconds)
215'C
Infrared (15 seconds)
220'C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

Parameters Guaranteed By Electrical Testing
(Test ckt., TA=25'C, Vs=3.6V, fo= 10.7 MHz, af= ±3 kHz, fMOO=1 kHz, 500 source)
Parameter

Measure

Supply Voltage Range

Vs

Supply Current
Squelch Off
Squelch On

Is
Is

Min

Typ

Max

Units

2.0

3.6

9.0

V

2.8
3.6

5.0
6.0

mA
mA

2.0

6.0

RF Input for - 3 dB Limiting

RF Input

Recovered Audio at Audio Output

Audio Output

200

350

Audio Out DC

Vg

1.2

1.5

OpAmpGain

V11 IVIN

40

55

0.4

0.7

Op Amp Output DC

Vl0

Op Amp Input Bias Current

(Vl0- Vll)/1MO

Scan Voltage
Pin 12 high (2V)
Pin 12 Low (OV)

V13
V13

Mute Switch Impedance, Pin 12 = OV
Switch S1 from pos.1 to pos.2

3.0

aV14/al14

".V
mVRMs

1.8

Voc
dB
Voc

20

75

nA

0
3.4

0.5

Voc
Voc

15

30

0

Design Parameters Not Tested or Guaranteed
Typ
Mixer Conversion Gain (Note 2)
46
VIV
Mixer Input Resistance
3.6
kO
pF
Mixer Input Capacitance
2.2
Detector Output Impedance
500
0
Trigger Hysterisis
100
mV
Mute Off Impedance (measure pin 14 with pin 12 @ 2V)
10
MO
Squelch Threshold
0.65
Voc
Detector Center Frequency Slope
0.15
V/kHz
Note 1. For operation above 25"C ambient temperature, the device must be derated based on 150'C maximum junction temperature and a thermal resistance 8JA
of 80'C/W.

Note 2. Mixer gain is supply dependent and effects overall sensnivily accordingly (See Typical Performance Characteristics).
Filters:
Murata
2200 Lake Park Drive
Smyrna, GA 30080
(404) 436-1300

Coils:
Toko America
1250 Feehanville Orive
Mount Prospect, IL 60056
(312) 297·0070

2-110

Typical Performance Characteristics (Test Circuits)
20dB SIN SENSITIVITY AND
AUDIO OUT vs. Vs

10

IS vs Vs

10

"""'" '" ""'"

-;;;;JTE
ON

"

I'"

MUTE
OFF

6
Vs (VoHs)

400

I
~

SENSITIVITY

[.;00

I
II

~

-

~~~'D_

I
I

10
Vs (Voltsl

THO AND AUD OUT VS 0

FM IF CHARACTERISTIC
10

AUDloJ:::
OUT

S +N

·10 k'
·20

·30
·40

" \.\

·50
·60

O.S

0.001 0.01

~

f.-':"
THo
J

!;

/

.

~ 0.6

~ 0.4

~

I'
10
0.1
RF IN (mVrmsl

0.2

'/

J

0.6

.

~

0.4~
0.2

20
3D
QUAD COIL Q

100

o.S

o

40

TUH/5588-2

2-111

LM3361A

-

~

(D

""~

e!.

en

n

F:r

Rl 03
51K
04_

:::r
(D

02

'

~10K ~10K
R3

R4

~R5
~R&
10K 10K

~R7
~R8
10K 10K

~R9

~Rl0

10K

~Rll ~R12
10K
10K

10K

~R33
~27K

05..;

t"'0&

R2
7 1K8

3D)

R13
2K4

Y

~'

n'

H03&

R15
&K8

R22
R18 50K
13K

R17

Rl&
10K

13K

~

R19
13K

, T 035

R2&
33K

=15

~

I\)

R39
5K

a37~

R40
7K

~
1.11

044 L'

R41
7K

R42
10K

L'

R50
lK8

45 rE~58
~

R55
2K
R&D
220K
-(062

059

2._--l.-

"

048 049

057

1

56K
R49

11

054 -=-

12~72

~~~
22K

055
039
040

~071

"'"t-

I r

14

t--"Q75

056
R51
10K

-I15

R64

470

R65
51K
TLlH/5586-3

Applications Information

(See Internal Schematic)

OSCILLATOR

The Colpitts type oscillator is internally biased with a regulated current source which assures proper operation over a
wide supply range. The collector, base, and emitter terminals are at pins 4, 1, and 2 respectively. The crystal, which
is used in the parallel resonant mode, may be replaced with
an appropriate inductor if the application does not require
the stability of a crystal oscillator. In this case, the resonant
frequency will be determined by the inductor in parallel with
the series combination of C1 and C2.

10 ITO
T

r--_ _
Cl......

C2*

a::::::::J-

I

~
~

Vs

L

1

_----_

PINI

~

PIN 2
TLlH/55B6-4

so

Ct~(Cl)(C2)/(Cl

tic, also increases distortion (see Typical Performance
Characteristics). For proper operation, the voltage swing on
pin 8 should be adequate to drive the upper rank of the
multiplier into switching (about 100 mVrms). This voltage
level is dependent on the internal 10 pF capacitor and the
tank Rp voltage divider network. After detection and de-emphasis, the audio output at pin 9 is buffered by an emitter
follower.
OPAMP

The op amp inverting input (pin 10) which is internally referenced to 0.7V, receives dc bias from the output at pin 11
through the external feedback network. Because of the low
D.C. bias, maximum swing on the op amp output with 10%
distortion is 500 mVrms. This can be increased when operating on supplies over 2.3V by adding a resistor from the op
amp input to ground which raises the quiescent D.C. at the
output allowing more swing (see figure below for selection
of added resistor). The op amp is normally utilized as either
a bandpass filter to extract a specific frequency from the
audio output, such as a ring or dial tone, or as a high pass
filter to detect noise due to no input at the mixer. The latter
condition will generate a signal at the op amp output, which
when applied to pin 12 can mute the external audio amp.
For max swing: VOUT=(VS-VSE)/2 (from internal circuit)

+C2)

so (VS-VBE)/2=0.7( 1

and fo ~ .159/.J[(Gtj

+ :~)

therefore -R2 = (VS-VBE)
- - - -1
R3
1.4

MIXER

The mixer is double balanced to reduce spurious responses.
The upper pairs are switched by the oscillator while the RF
input is applied to the lower pair (pin 16). R43 sets the mixer
input impedance at 3.6 kll. The mixer output impedance of
1.8 kll will properly match the input impedance of a ceramic
filter which is used as a bandpass filter coupling the mixer
output to the IF limiting amplifier.

"'
R3

10J!l
R3

IF LIMITER
The IF amplifier consists of six differential gain stages, with
the input impedance set by R2 at 1.8 kll to properly terminate the ceramic filter driving the IF. The IF alone (without
mixer) has a -3 dB limiting sensitivity of approximately 50
",V. The system bandwidth is limited to about 5 MHz due to
high impedances in the IF which are necessary to meet low
power requirements. The IF output is connected to the external quad coil at pin 8 via an internal 10 pF capacitor.
FM DEMOD AUDIO OUT

A conventional quadrature detector is used to demodulate
the FM signal. The Q of the quad coil, which is determined
by the external resistor placed across it, has multiple effects
on the audio output. Increasing the Q increases output level
but because of nonlinearities in the tank phase characteris-

TLlH/5586-5

Increasing OP Amp Swing
SQUELCH TRIGGER CIRCUIT

The squelch trigger circuit is configured such that a low bias
on the input (pin 12) will force pin 13 high (200 mV below
supply), where it can support at least a 1 mA load, and pin
14 to be a low impedance, typically 151l to ground. Connecting pin 14 to a high impedance ground reference point
in the audio path between pin 9 and the audio amp will mute
the audio output. Pulling pin 12 above mute threshold
(0.65V) will force pin 13 to an impedance of about 60 kll to
ground and pin 14 will be an open circuit. There is 100 mV
of hysterisis at pin 12 which effectively prevents jitter.

2-113

C) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
C'I

~

NatiOnal

:::::!! ~ Semiconductor
....
Corporation

LM3820 AM Radio System
General Description

Features

The LM3820 is a 3-stage AM radio IC consisting of an RF
amplifier, oscillator, mixer, IF amplifier, AGC detector, and
zener regulator.

•
•
•
•
•
•
•
•

The device was originally designed for use in slug-tuned
auto radio applications, but is also suitable for capacitortuned portable radios.
The LM3820 is an improved replacement for the LM1820.

Input protection diodes
Good control on sensitivity
Improved SIN and tweet
Versatile building-block approach
Gain-controlled RF stage
Cascode IF amplifier
Regulated supply
Pin compatible with LM1820

Connection Diagram
Dual-In-Llne Package

•

MIXER INPUT

-4-~:j~:J--fl~4 MIXER OUTPUT
13

OSCILLATOR TANK -1i"""G~!EJ

RF OUTPUT
RF INPUT

MIXER BYPASS

RF BYPASS

-+I::..O AGC CAPACITOR

AGC DRIVE ....::jl+CiiII__...__

9

IF OUTPUT
IF INPUT ~I-__....J

RF GROUND

B SUBSTRATE AND
IF AMPL GROUND
TL/H/7967 -1

Order Number LM3820N
See NS Package Number N14A

Circuit Schematic
13

IZ

14

RI
950

05

RIl
BOO

RIZ
Uk

04

010

03

RZ
ZlO

RI3
600
Rl
5k

R3
Z5k
R4
Z5k

RIO
5.0k

06
RI6
10k

RB
5.6k

Rli
i.5k

01

05

II

R9
3.3k

RII
3.3k

RIB
Ik

R5

510
TL/H17967 -2

2-114

,-----------------------------------------------------------------------------, r
3:
Absolute Maximum Ratings
Co)
co
If Military/Aerospace specified devices are required,
Current into Supply Terminal (Pin 3)
35mA
N
o
contact the National Semiconductor Sales Office/
Operating Temperature Range
Storage Temperature Range

Distributors for availability and specifications.
Power Dissipation (Note 1)
Supply Voltage

1200 mW
16V

Electrical Characteristics
Symbol

Conditions

IS

Supply Current

Vz

Internal Zener Voltage

Signal to Noise Ratio

Overload Distortion

~

2S·C. derate based on TJIMax)

~

260'C

Min

Typ

Max

Units

12

18

24

rnA

7.0

7.5

8.0

V

I = 1 MHz. 30% Mod 400 Hz
Measure RF Input Level lor
10 mV Audio Output with
Tuning Peaked

15

35

70

/JoV

I = 1 MHz. 30% Mod 1 kHz
(S + N)/N at Audio Output
with 100 /JoV RF Input

22

28

-

dB

I = 1 MHz. 90% Mod 1 kHz
THD at Audio Output
with 30 mV RF Input

-

6

10

%

No RFlnput

Input Sensitivity

Nale 1: Above TA

Lead Temperature (Soldering. 10 sec.)

= 25'C. Vs = 6V unless noted)

(Figure 1. TA

Parameter

- 25'C to + 85'C
-65'C to + 150'C

150"C and 6JA

~

100 ·C/W.

Typical Applications
r - - - - -.,

I

SIMULATES
lOOPSTICK

II ~ 'OTI

98T

~II

_'"i'

~5"

II~

~ II

.1.---+-+...,:

~

II ~

) II

~-J ~lJ

~

II

":"

(1

r------------.,I
I

ZZO ":"

10"

r-n
*0.0' "

,4

13

'Z 11

~

,r---I...M-'X-'R-"t-_.....
___-,

1)
_1

10

AGC

DET

I

o:!:-

:;::r:

:
O.05 ",

I

:
I

~RAGC
"':,.21k
"I
I
I

~
~
3 4

-

LZ

L__

,

* *

zo.,

C,

19

PI

I
I
I
I

II
II

1\

fo.05"
'100,.V RF INPUT is equivalent to approx. 1 mY/meter field strength. See Applications Information for coil specifications.

FIGURE 1. Capacitor-Tuned Test Fixture

2-115

TL/H/7967 -3

Applications Information
The circuit shown in Figure 1 is recommended as a starting
point for portable radio designs. Loopstick antenna L 1 is
used in place of LO, and the RF amplifier is used with a
resistor load to drive the mixer. A double tuned circuit at the
output of the mixer provides selectivity, while the remainder
of the gain is provided by the IF section, which is matched to
the diode through a unity turns ratio transformer. RAGC may
be used in place of CAGC to bypass the internal AGC detector and provide more recovered audio.
vc

I
I

AM

)

pvc

c-fica

An AM automobile radio design is shown in Figure 2. Tuning
of both the input and the output of the RF amplifier and the
mixer is accomplished with variable inductors. Better selectivity is obtained through the use of double tuned interstage
transformers. Input circuits are inductively tuned to prevent
microphonics and provide a linear tuning motion to facilitate
push-button operation.
Coil specifications for Figure 1 are as follows:

.I

AMANT

I

lDDxlmm

CA= 140 pF

osc

·1 960 kHz·2105 kHz

lie: J::[
"0
II
II

110T

II

CB",60 pF

AM

LO, L2
525 kHz·1650 kHz

L=360 joIH
Qu= 110

L=65D ,.H

Qu=250

T11
1

AM 1.1 IF

AM 2nd IF
1

455 kHz

150pf EXT

~ [-~~-1)

lIT

11T

AM 3rd IF
T3 1

T21
455 kHz

II
II

IT

142T

II
II

[

II

II

C=I80pF

C=47 pF
Qu=120

Qu=140

1

11

455 kHz

,~,,[
II

111

liT

II

C=I80pF
Qu=140

TUH17967-4

PCB Layout for Figure 1 Circuit

TUH/7967-5

2-116

Applications Information

(Continued)

~lOo"F
680

'1' 0 OOJ ,.F / \
..1.
II
":'

II

D.02j,F

+- ____

----....I
lJo
14

13

''!it
'4V

100
AUDIO
OUTPUT
150k

s·.

-10

-

;

,.....

~

-20

~o.l"F

-3~

-40

-so

10= 1 MHz

TRANSFORMERS

1m :400 Hz
m"O.J

Tl: C = 130 pF primary & secondary
primary 10 secondary tap ratio-30:1
Q = 60

10

100

Ik

INPUT LEVEL /sJVRMS'

10k

coupling-critical

T2: C = 130 pF primary & secondary
primary lap rati0-8.5:1
secondary tap rali0-8.5:1
Q = 60

coupling-critical
TL/H/7967 -6

FIGURE 2. Slug-Tuned Auto Radio

fI

2-117

NatiOnal

~ Semiconductor
Corporation

LM4500A High Fidelity FM Stereo
Demodulator with Blend
General Description

Features

The LM4500A is an improved stereo demodulator IC offering very low audio distortion. A new demodulator technique
minimizes adjacent station interference caused by subcarrier harmonics and prevents lock-up problems from pilot carrier frequency harmonics. The IC features a blend circuit
which optimizes the signal-to-noise ratio under weak signal
conditions by gradually combining left and right channel information.

•
•
•
•
•
•
•
•
•
•
•
•

Low distortion-O.1 % typ
High subcarrier harmonic rejection
Large input dynamic range-2.5 Vp-p
Voltage controlled blend
High separation-fixed or adjustable
Adjustable gain
Reduced stereo-mono DC shift--5 mV typ
55 dB supply ripple rejection
Low output impedance
Requires no external inductors
Wide supply range 8V-16V
Excellent rejection of 57 kHz ARI subcarrier

Typical Application
Vcc

8- 16VOC

228 kHz

MONITOR

C3
220 pF
N220

PI
5k
VCO
ADJUST

COMPOSITE
INPUT

r - - i - - - f - - + - - + - -......
16

LM4500A

............

'--

SWI

0-----1 .....--it-......

....."V'VY-f:fOlllH... Vcc

R

STEREO
INDICATOR
LED

OUTPUTS
·Metal film, zero temperature coefficient resistor recommended

TL/H17973-1

FIGURE 1
Order Number LM4500AN
See NS Package Number N16A

2-118

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Storage Temperature Range

Power Supply Voltage

Lamp Current

16V

Power Dissipation (Package Limitation)
Derate above T A = + 25'C

1600mW
15 mWI'C

Operating Temperature Range (Ambient) -40'C to

-65'Cto

Lamp Drive Voltage
Max Voltage at Pin 7 with Lamp "Off"

30V
100mA

Blend Control Input Voltage (Pin 11)

10V

Lead Temperature (Soldering. 10 sec.)

+ 65'C

+ 150'C

260'C

Electrical Characteristics Unless otherwise noted: Vcc = 12 VDC. T A = 25'C. Vp-p standard multiplex composite signal with L or R channel only modulated at 1.0 kHz and with 10% pilot level. using circuit of Figure 1
Parameter
Stereo Channel Separation

Conditions

Min

Unadjusted
Optimized on Other Channel (Note 1)

30
40

Measured Voltage Gain (Note 1)

0.6

Typ

Max

Units
dB
dB

1

1.2
0.3

THO

2.5 Vp-p Composite Input Signal
1.5 Vp-p Composite Input Signal

0.15
0.06

Signal-to-Noise Ratio

DIN45405 Quasi Peak Reading
rms 20 Hz-15 kHz

63
66

dB
dB

Ultrasonic Frequency Rejection

19 kHz
36kHz

31
45

dB
dB

Stereo Switch Level

19 kHz Input Level for Lamp "On"

12

HystereSiS

16

20

mVrms

20

mVDC

6

Output Voltage Change

With Mono/Stereo Switching (Note 2)

Stereo Blend Control Voltage (Pin 11)
(See Figure 8)

3 dB Separation
30 dB Separation

3

dB

0.7
1.7

Minimum Separation

Pin 11 atOV

Monaural Channel Imbalance

Pilot Tone Off

Sub-Carrier Harmonic Rejection

76kHz
114 kHz
152 kHz

60
70
63

Supply Ripple Rejection

f = 1 kHz

0.03

%
%

V
V
1

dB

0.3

dB
dB
dB
dB

57

dB

Input Impedance

50

k!l

Output Impedance

100

!l

-100

Blend Control Current (Note 1)

Operating Supply Voltage
Current Drain

-300

±4

Capture Range
6
Lamp Disconnected

%
16

35

",A

V
mA

Note 1: See Applications Inlonnalion and Circuil Description.
Note 2: This test is done with Ihe slereo indicator lamp disconnected in order 10 remove DC shift due 10 thennal changes. These shifts have long lime constants
(100 ms) and therefore do not produce audible transients.

2-119

Typical Performance Characteristics
Supply Current vs
Supply Voltage- ..

4&

.-

70

'".

42

....
ill

..

40

~

3.

~

3&

t

ill

60

§..

~

34

l!.Ok f--:::.I--Io-f-+-+-f--I-ooI
z~ 19.9k 1-+-+-1-+-+-1-+-1
"
a:
~ 18.8k 1-+-+-1-+--+-1-+-1
~ f8.7k 1-+-+-1-+-+-1-+-1

li
40

ffi

STEjEO

...

30

~

30

20

8

10

11

12

13

14

15

9

16

10

Channel Separation vs
Supply Voltage
so ~

kH•• USING STEREO

ADJUSTING CIRCUIT

-

~

D•• Ii.MONO I

~

0.7 -.STEREO

C)

0.6

iii

0.5

..

0.4
0.3

ST{RE~

o

10

13

16

>,1.6kL......J........J.-L......J........J._L......J.........
8
9 10 11 12 13 14 15 16

SUPPLY VOLTAGE (VI

14

J-+MONO
STEREO

,"'V;:"
12VOC

Lamp Pin Saturation
Voltage vs Current
~

16

'"

14

~

~

i§

12
10

~

I

0.1
12

15

:ia:

02

20

11

14

Vce= 8.5 Voe

0.9

!
10

13

1.0

~

30

9

12

Total Harmonic Distortion
vs Composite Input Level

40

8

11

SUPPLY VOLTAGE (VI

SUPPLY VOLTAGE (VI

_ ,~ 1

~llUk

'" 19.2k

ill

3Z

:!!

a~ 11,lk 1-+--1--1-+--+-1-+--1
1-+-+-1-+-+-1-+-1

.....

50

~

MONO

.-r--i----r--.":""';--r--r--,

_ lUk

,J 1 kJ'.20~ mv~m.o~ PINI'6

iD

44

C
.!

VCO Free Running
Frequency vs
Supply Voltage

Power Supply Rejection vs
Supply Voltage

IS 18

i!!

§

~

::::IC'!"""

MONO

o

k' ......
~I--'
o
o 100

300

200

400

501

LAMP PIN CURRENT (mAl

COMPOSITE INPUT LEVEL (v ...1

SUPPLY VOLTAGE (VI

'"

veo Free Running
Stereo Separation vs
Temperature

iD

60

i

..

40

t

'"z
:i"

Input Impedance vs
Temperature

Frequency Drift vs
Temperature

108

,....,...,.....,......,-r-r...,.....

BOO

HH-++-I-1--'H-++-I-t-I

S-200

~~Ff~~~~~W

e: -400
-600

H-+++-I-HH++-I-H

~

50

i

40

II!
!!

l£MPERATURE (·el

!

">
"
"m
~

20

~ 2.0

~
:i"a:

10

LAMP Off

S

a:

o

-4
60

TEMPERATURE (·CI

80

-40 -20

60

10

ILAMP = 100 mA

1.5

>
z

....

-3

40

..'"

L':f!~

..

-2

20

Lamp Pin Saturation
Voltagevs
Temperature

z.S

15

40

-20

TEMPERATURE ('CI

25

.'"~ .....

r-

20

3D
-40

Stereo Switch Threshold
vs Temperature

.!

-40 -20

V"'"

TEMPERATURE ('CI

Gain vs Temperature

'"

~/

. . . 11

-100 L.!--L....L.L.L.!--L....L.LJL.L....I.J
-40 -20
20
40
60
10

D

~I

60

'"
l;l

200

iii

70

g

400

t~

i

-r-r-T"'T1

1.0

o
20

40

l£MPERATURE ('CI

80

10

I

0.5

-40

-zo

20

40

80

BOB5

l£MPERATURE (OCI
TLIH17973-2

2-120

Typical Performance Characteristics

g

1.0

Total Harmonic Distortion
vs Frequency

60

z

0.9
0.8

~

0.1
0.6

a;

~

0.5
0.4

i=

;l

0.3
0.2

'"~
is

...
;;;
~

;:

e

'"

.

ii

a:

~

STEREO

t-'

I

50 100 200

500

lk 2k

V

v

USING STEREO
ADJUSTING CIRCUIT
I

10

5k 10k 15k

I

'"'"z

45

e

35

..
i=

50

18.4

18.8

,"

19.2

'"ii
i=

i

tl\ \\

j

25
18.0

.

a;

...

1\ \

VIN
f- 758mVp
'-~ L~
100PILO

lk 2k

20 L.....L.J..J.WlIL.-...J...JUlJWIL-L..w.WlJI
10k
lOOk
lk
100

5k 10k 15k

FREQUENCY IH,)

Unadjusted Separation vs
VCO Free Running
Frequency

10 "rOT

Jl~

500

FREQUENCY 1Hz)

VIN' Z.5 V.·.

UI

a:

I

50 100 200

USING STEREO ADJUSTING C,~PP
O~TlMIZE? AT VCO • 19.0 IkH'

55 VIN"UV,·
lD%PILO,TJlIi'"

'"",,

3D

Adjusted Separation vs
VCO Free Running
Frequency

~

f',..
I,

FREQUENCY (Hz)

65

10v~s~F~re~q~u~e~n~c~y~m-~~~

V

20

J 1\

0.1 I-TONJ

Power Supply Rejection

Separation vs
Frequency

50
40

(Continued)

lB.6

20.0

VCO FREE RUNNING FREQUENCY 1kHz)

VIINJ5J.~

40

30

20

10% PILOT

JIN/,'0%
!15~ mJ.~
PILOT

t:

"yrt V

~ VIN' 2.5 Vp·p
~"PILOT

I
"\

18.4

1&.&

19.2

19.&

200

I>

160

~

120

oS
!5i

\
I
\
II
1~TCHES
1\
~~ rOMONO \ '

10
18.0

Capture Range vs
Pilot Level

w

~

80

0-

S

0:

\

40

-.o.OT

o
11.0

20.0

18.0

19.0

20.0

21.0

FREQUENCY 1kHz)

VCO FREE RUNNING FREQUENCY 1kHz)

TLlH17973-3

Block Diagram

3OkH,

-.S"L..r1.

REGULATOR

~vcc

BLEND CONTROL
INPUT

TL/H17973-4

FIGURE 2

2-121

Circuit Description
INTRODUCTION

The use of such drive waveforms produces the modulating
functions also shown in Figure 3. The usual square waveforms have been replaced in the PLL and decoder sections
by 3-level forms which contain no third harmonic (actually
no harmonics which are mulliples of 2 or 3 are present).
This eliminates the frequency translation of interference
from these bands into the low frequency region. Such translation may produce audible components in the decoder section from the sidebands of adjacent channel FM signals,
and may produce phase jitter, and consequent intermodulation distortion, in the PLL, from the modulated 57 kHz tones
of the ARI system. The LM4500A is inherently free from
these effects.

The LM4500A is a phase-lock-loop stereo decoder which
incorporates a variable separation control, and in which
sensitivity to the third harmonics of both the pilot and subcarrier frequencies has been eliminated by the use of appropriate, digitally generated, waveforms in the phase-lock-loop
and decoder sections.
The variable separation control may be operated manually,
or by a receiver's AGC or S meter signals, to provide
smooth transitions between monaural and stereo reception.
It operates only during stereo reception: the eircit switches
automatically to monaural if the 19 kHz pilot tone is absent.
The elimination of sensitivity to the third harmonic of the
sub-carrier (114 kHz) excludes interference from the sidebands of adjacent transmitters, while the elimination of sensitivity to the third harmonic of the pilot tone (57 kHz) excludes interference from the ARlo system which employs
this frequency.

The stereo switch section is of conventional form (e.g.
LM1310).
The decoder section consists of a modulator (driven by the
waveforms shown in Figure 3) whose outputs are the inverted and non-inverted channel difference signals. These signals pass to the output amplifiers via the variable blend circuit in which they are partially combined, and hence mutually attenuated, according to the control voltage applied.

CIRCUIT OPERATION
The block diagram of the circuit, shown in Figure 2, consists
of three sections, the phase-lock-loop, including the digital
waveform generator, the stereo switch, and the decoder, in
which the composite stereo signal is demodulated and matrixed to separate Land R channels.

Matrixing occurs at the inputs of the output amplifiers,
where the unmodified composite signal is added to the
blended channel difference signals. The stereo separation
may be progressively reduced from maximum to zero; dependent on the blending. The control law has been made
non-linear, as the major redistribution of sound energy occurs at very low separation levels. For monaural, or very
weak stereo signals, the modulator in the decoder section is
deactivated by the stereo switch circuit. The variable separation control is thus, also, automatically disabled.

In the phase-lock-loop the internal RC oscillator, operating
at 228 kHz, feeds a 3-stage Johnson counter, via a binary
divider, to generate a series of 19 kHz square waves. By the
use of suitably connected NAND and EXCLUSIVE OR
gates, the waveforms shown in Figure 3, which are used to
drive the various modulators in the circuit, are developed.
•Auto Radio Information· used in Europe

_---In. . .__n

Modulator Drive Waveform

Modulating Functions

PLL (19 kHz)

L

STEREO SWITCH
(19kHz!

DECODER
(38 kHz)

TL/H17973-5

FIGURE 3. Digital Waveforms

2-122

Applications Information
GAIN AND DE-EMPHASIS

SEPARATION ADJUSTMENT
A separation adjustment may be added, as shown in Figure
5, to compensate for the receiver's IF characteristics.

The gain and de-emphasis characteristics of the circuit are
defined by shunt feedback via the external RC networks
(R3, C5, R4, C7 of Figure 1) around the output amplifiers.
The gain is unity when resistors of 5.1 kO are used. Higher
gains may be obtained by using networks of the form shown
in Figure 4.
PIN4

PIN3

PIN5

This network reduces the amplification of the channel sum
signal in the decoder, to compensate the attenuation of the
channel difference signal in the receiver's IF section. The
network shown will compensate for up to 2 dB attenuation
at 38 kHz. The decoder gain is, obviously, reduced by an
amount equal to the compensation required. When used as
described, the adjustment also corrects the inherent separation of the decoder, which may be optimized on one channel. Optimization of both channels is possible if separate
potentiometers are used to feed each output amplifier.

PIN 6

C6

C7

R3

R4

R6

1
PIN 2

R7

PIN

3::J---.~6~

PIN 6
56k
5%

TL1H17973-6

FIGURE 5. Networking Providing Adjustable Separation

The resistors R6, R7 are added to correct the output quiescent voltage levels which are optimized for R3, R4 = 5.1 kO
and which would, if uncorrected, become too low with higher value resistors. Suitable network values are as follows:

0
3
6

R3,R4
5.1 kO
6.8kO
10k

C6,C7

VARIABLE SEPARATION (BLEND) CONTROL
AND 19 kHz OUTPUT
To retain the 16-Pin package the blend control has been
combined with the 19 kHz output on Pin 11. The internal
circuit providing this combination is shown in Figure 6.
If Pin 11 is left open-circuit the 19 kHz signal appears at a
mean DC level of 4V. The blend circuit is inoperative at this
level and the decoder provides full separation. The 19 kHz
signal can be used to tune the internal oscillator.

R6,R7

50 Jl-s

75 Jl-s

10 nF
6.8nF
4.7nF

15 nF
10nF
6.8 nF

':"
TLIH17973-7

FIGURE 4. Output Amplifier Feedback Networks

Gain (dB)

10k

47k ± 10%
27k ± 10%

To reduce the separation the voltage on Pin 11 is reduced.
At 3.2V T2 ceases conduction and the 19 kHz signal disappears.

The maximum output level is 1 Vrms; consequently the max
input is limited to 1.4 Vp-p if the gain is set to 6 dB.

At 2.0V the blend circuit comes into operation and the separation decreases according to the curve shown in Figure 8.

1---"'-0 PIN II
Ik
4V

2.5V

PI

19 kHz

:t.n.. ~+---1

T2

TLIHI7973-B

FIGURE 6. Blend Control Input Circuit

2-123

Applications Information

(Continued)

T

PIN 1&

f

-1-~~OPF

10k ~
2% •

TEST POINT
228 kHz MONITOR

100

TL/H/7973-9

FIGURE 7. Oscillator Network for Direct Frequency Measurement

Separation vs Blend (Pin 11) Voltage
50r-~'--r-'--r-'-~-'

40

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0.4 0.& 0.8 1.0 1.2 1.4 1.& 1.8 2.0
DC VOLTAGE APPLIED TO PIN 11 (Voe)
TL/H17973-10

FIGURE 8
EXTERNAL MONO·STEREO SWITCHING
AND OSCILLATOR KILLING
If required the LM4500A can be forced into mono mode
simply by grounding Pin 9 (see Figure 1). The 228 kHz oscillator will be automatically stopped.
The conditions governing mono/stereo switching on Pin 9
are the following:

Oscillator Tuning
If the variable separation facility is not required Pin 11 is left
open-circuit and the 19 kHz signal which then appears may
be used to indicate the oscillator frequency. If the variable
separation is used, and the drive circuit prevents access to
the 19 kHz Signal, then the oscillator frequency must be
measured directly. A test point should be obtained by modifying the oscillator RC network as in Figure 7.

Quiescent voltage: + 2.3 Voc
Current required to ensure mono operation (with
100 mVrms pilot level): 10 p.A (from Pin 9 to ground)

The output is a pulse train of appoximately 1.5V amplitude.
Connecting frequency counters of up to 300 pF input capacitance produces less than 0.3% change of the oscillator
frequency, which should be set to 228 kHz.

Hysteresis: 0.7 p.A
Stereo/mono switching & oscillator killing; less than
+500 mV
Maximum stray capacitance between Pin 9 and ground:
100 pF

HIGH LOOP GAIN COMPONENTS
For applications demanding operation under low pilot level
(e.g. car radio) the following component changes to Figure 1
are recommended.
R1 = 12k
C3 = 150pF
R2 = 1.5k
C4 = 330pF
R8 = 330
C5 = 150pF
P1 = 10k

EXTERNAL COMPONENT FUNCTIONS
P1
P2

19 kHz frequency adjustment.
Channel separation adjustment and compensation for IF roll-off.

R3, R6 Gain fixing resistors. The values shown in the
schematic are for unity gain.
C6, C7 De-emphasis capacitors. Value to give:
RC = 50 p.s.

2-124

r----------------------------------------------------------------------,
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TBA 1205 IF Amplifier and Detector
General Description
The TBA 120S is a monolithic integrated circuit specifically
designed for audio detection in TV and FM radio receivers.
It incorporates an 8-stage limiting IF amplifier and balanced
detector plus a DC operated volume control.
The TBA 120S is supplied in four groups depending on the
resistance required between pin 5 and ground to attenuate
the audio output by 30 dB. The group number as defined
below is marked on the package.
II

1

m

....
N

National

1 Group 1

~

III

1

IV

1

vii

1 R5-GND 11.9-2.2 1 2.1-2.5 1 2.4-2.9 1 2.8-3.3 1 kfi 1
Pins 3 and 4 are connected to the collector and base of a
transistor which may be used as an AF-preamplifier or as a
switch.

At pin 12 a zener-diode is accessible which can be used to
stabilize the supply voltage of this integrated circuit or the
voltage of other circuit elements in the set.

Features
• Electronic attenuator: replaces conventional AC volume
control
85 dB typ
• Volume reduction range
30 /LV typ
• Sensitivity: 3 dB limiting voltage
68 dB typ at 10 mV
• Excellent AM rejection
1V typ
• Audio output voltage
(6V-18V)
• Wide supply voltage range
• Internal zener diode regulator
• Very low external component requirement
• Simple detector alignment: one coil

Connection Diagram
Dual-In-Line Package
GND- 1

14 -INPUT

BIAS DECOUPLING -

2

13 -INPUT BIAS

TRANSISTOR COLLECTOR -

3

12 -ZENER

TRANSISTOR BASE -

4

11 -Vee

VOLUME CONTROL -

5

10 -IF AMPLIFIER OUTPUT

IF AMPLIFIER OUTPUT -

6

9 -PHASE SHIFT NETWORK

PHASE SHIFT NETWORK -

7

8 - AUDIO OUTPUT
TL/H/9319-1

Top View
Order NumberTBA120S II, TBA120S III, TBA120S IVorTBA120S V
See NS Package Number N14A

2-125

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, V11
18V
Volume Control Voltage, V5
4V
Zener Current, 112
20mA

Electrical Characteristics (vcc =
Symbol

Icc
Gv

IF Voltage Gain
IF Output Voltage, Each
Output at Limiting

Val

AF Output Voltage

1 kO
-15'Cto +70'C
- 65'C to + 150'C

Operating Temperature Range
Storage Temperature Range

Conditions
R5 =

Min
10

00

R5 = 0

Vo

5mA
2mA

Transistor Base Current, 14
Bias Resistance (Max), R13-14

12V, TA = 25'C)

Parameter
Supply Current

Transistor Collector Current, 13

Typ

Max

14

18

11

f = 5.5 MHz

f = 5.5 MHz, b.f = ± 50 kHz,
fMOD = 1 kHz, VI = 10 mV,
0= 45

68

dB

170

250

mVp-p

0.7

1.0

V

1.5

f = 10.7 MHz, ~f = ±50 kHz,
fMOD = 1 kHz, VI = 10 mV,
0=20

0.2

Input Voltage Before Limiting

f = 5.5 MHz, b.f = ±50 kHz,
fMOD = 1 kHz, 0 = 45

30

ZI

Input Impedance

f = 5.5 MHz

Ro

Output Resistance

Vafmax

--Vafmin

Volume Control Range

V8

DC Component of the
Output Signal

VI = 0

aAM

AM Rejection

f = 5.5 MHz, ~f = ± 50 kHz,
fMOD = 1 kHz, VI = 500 p.V
m = 30%

Distortion (10.7 MHz)

VLlM

aAM

AM Rejection

mA
20

f = 5.5 MHz, ~f = 25 kHz,
fMOD = 1 kHz, VI = 10 mV,
0=45

Distortion (5.5 MHz)

Units

%

60

p.V

15/6

40/4.5

1.9

2.6

70

85

6.2

7.3

50

60

dB

f = 5.5 MHz, ~f = ± 50 kHz,
fMOD = 1 kHz, VI = 10 mV,
m = 30%

68

dB

kO/pF
3.3

kO
dB

8.4

V

R5

Potentiometer Resistance

1 dB Attenuation

3.7

4.7

V5

Voltage

1 dB Attenuation

2.2

2.5

R5

Potentiometer Resistance

70 dB Attenuation

V5

Voltage

70 dB Attenuation

1.2

V

Noise Voltage at Output

VI = 10mV

30

p.V

V12

Zener Voltage

112 = 5mA

Rz

Zener Slope Resistance

Vcbo

Breakdown Voltage

45

65

V

Vceo

Breakdown Voltage

Is = 500 p.A

18

24

V

hIe

Current Gain

Is = 1 mA

50

100

1.0

11.2

2-126

1.4

kO
V
kO

12

13.4

V

30

50

0

500

.--------------------------------------------------------------------------, m
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Typical Application

~
.....

(5.5 MHz)

N

+15V

C

rn

120

TUH/9319-2

Test Circuit (5.5 MHz)
+12V

TLlH/9319-3

2-127

~....

Schematic Diagram

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2-128

Section 3
Video Circuits

Section 3 Contents
Definition of Terms ............ " . . . .. . . . .. . . . . . . .. . . . .. . . . . . . . . .. . . . . .. . . . . . . . . . . . .
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . .
* LM592 Differential Video Amplifier. . . . • . . . . • . . . . . . . . . • . . . . • . . . . . . . . . . • . . • . . . . • . . . . . . . .
LM733/LM733C Differential Video Amplifier ...........................................
* LM 1044 Analog Video Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . .
* LM1201 Video Amplifier System..... ......... ..... ..... ..... .... ............ .........
* LM1203 RGB Video Amplifier System.................... ........................ .... .
LM1391 Phase-Locked Loop ................................•.......................
LM1823 Video IF Amplifier/PLL Detection System........ ..... .... ....... ..... .........
LM1880 No-Holds Vertical/Horizontal ......•..... ,. .......... .........................
* LM1881 Video Sync Separator. ..... ........... .... ...... ......... .......... .........
LM1886 TV Video Matrix D to A ......................................................
LM1889 TV Video Modulator....................... ..... .......................... ...
LM2889 TV Video Modulator. . . . . . . . . . . • . • . . . . . . . • . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . .

·Devlces Not Covered In Last Publlcallon

3-2

3-3
3-5
3-8
3-13
3-18
3-22
3-23
3-34
3-39
3-46
3-54
3-61
3-68
3-78

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Video
Definition of Terms

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Aspect Ratio: The ratio of picture width to picture height.
For the NTSC system this is 4:3.

Deep red has more vividness or saturation (less white),
whereas dark red has less brightness. Similar terms are
used to describe non-spectral colors (a mixture of hues).

Back Porch: The section of the composite video signal between the trailing edge of the line (horizontal) sync pulse
and the end of the blanking pulse period (when picture information begins). For a monochrome signal the back porch is
simply at the blanking level. For a color signal, the color
burst is added within this section.

Color Burst: Normally refers to approximately 9 cycles of
the 3.58 MHz subcarrier superimposed on the back porch of
the composite video signal. The phase of this burst establishes the reference color phase for tint or hue, and the
amplitude provides a reference for the color saturation level.

Black Level: The DC voltage level in the picture signal
which corresponds to beam cut-off on the display tube. It
can be at the blanking level (given by the back porch) or
slightly higher (7.5% to 10% of the peak white signal above
the blanking level).

Color Subcarrler: A subcarrier at 3.579545 MHz (NTSC)
whose modulation sidebands are added to a monochrome
video signal to convey the color information. Similar subcarriers are used for SECAM and PAL.
Composite Video Signal: The complete video signal. For
monochrome, it consists of blanking and synchronizing signals, with a picture signal representing the scene brightness. For color, an additional subcarrier is added for color
synchronization and picture color content.

Blacker-than-Black: The amplitude region in the composite
video signal that extends below the reference black level in
the direction of the synchronizing pulses.
Blanking: A portion of the composite video signal whose
instantaneous amplitude makes the vertical and horizontal
scan retrace not visible on the display tube.

Compression: An undesired decrease in amplitude of one
portion of the composite video signal relative to another
portion.

Blanking Level: The level of the front and back porches of
the composite video signal.

Contrast: The range of dark and light values in a picture.
Cross-talk: An undesired signal interfering with a desired
signal.

Blanking Period: The period in the composite video signal
where the level is reduced to the blanking level, below
which the display electron beam is cut-off. This allows nonvisible retrace of the beam from the right side of the display
to the left side at the end of each scan line (horizontal
blanking) and non-visible return of the electron beam from
the bottom of the display to the top. Horizontal blanking
occurs for approximately 11 p.s between each scan line and
vertical blanking for 1.2 ms between each field.

Definition: See resolution.
Differential Gain: The amplitude change in the 3.58 MHz
color subcarrier as the picture signal varies from blanking to
peak white level. This is the result of system non-linearities
and is measured in percent change.
Differential Phase: The phase change, measured in degrees, of the 3.58 MHz color subcarrier as the picture signal
varies from blanking to peak white level.

Blooming: Defocussing of the picture in regions where the
brightness is too high.
Breezeway: The section in the signal blanking period between the end of the sync pulse and the start of the color
burst.

Equalizing Pulses: Pulses of one half the width of the line
(horizontal) sync pulses, transmitted at twice the line rate for
the three line periods before and after the field (vertical)
sync pulse. They are used to help the vertical sync system
of the receiver accommodate the half line difference in the
number of scan lines on successive fields.

C.C.I.R.: International Radio Consultative Committee-a
worldwide standards organization.
Chrominance Signal: That part of the NTSC signal that
contains the color information.

Field: One half of a complete picture interval. A field will
contain either all the odd numbered scanning lines or all the
even numbered scanning lines in the picture.

Clamping: A process that established a fixed DC voltage
level for the picture signal. This is important for proper RF
modulation and for maintaining the correct picture black level.

Field Frequency: The rate at which a complete field is
scanned. For NTSC color signals this is nominally 59.94 Hz.
Fly-back: See Horizontal Retrace.

Color: An attribute of an object being scanned that distinguishes it from other objects, apart from shape, texture, and
brightness. In television systems the color of an object is
further subdivided into hue (tint) and saturation. The hue or
tint refers to the dominant wavelength of a spectral color,
i.e., light red is the same hue as deep red and dark red.

Frame: A complete picture consisting of two interlocking
fields.
Frame Frequency: The rate at which a complete frame is
scanned. In the U.S. this is nominally 30 frames or pictures
per second.

3-3

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Front Porch: The section of the composite video signal between the end of the picture information on a scan line (start
of blanking) and the start of the line synchronization pulse.

signal. For U.S. television, the audio signal is increased at a
6 db/octave rate above 2.1 kHz.
Raster: The area on the face of the display tube that is
scanned by the electron beam. This is not always entirely
visible since commercial receivers employ overscan so that
the edges of the raster are hidden by the faceplate.

Horizontal Blanking: The blanking Signal at the end of
each scan line that prevents the retrace of the display tube
electron beam from being visible.
Horizontal Retrace: The rapid return of the scanning electron beam from the right side of the raster to the left side.

Reference Signals: See V.I.T.S. and V.I.R.S.
Resolution (Horizontal): The amount of resolvable detail in
the horizontal direction of the picture. This depends on the
high frequency and phase response of the transmission system and the receiver.
Resolution (Vertical): The amount of resolvable detail in
the vertical direction of the picture. This depends primarily
on the number of scan lines that are used and secondarily
on the size (shape) of the electron scanning beam.
Saturation (Color): The amplitude of the chrominance signal. Increased saturation means increased chrominance
signal level. Visibly, this refers to a color increasing from
pale or pastel to deep.
S.E.C.A.M.: Sequential Couleur Avec Memoire. The color
broadcasting system used predominantly in France which
utilizes sequential transmission of the color difference signals, which are FM modulated on two separate subcarriers
(1967).

Horizontal Hum Bars: Relatively broad horizontal bars drifting slowly up the screen as a result of interference from the
60 Hz main frequency.
Hue (Tint): Describes the color that is being represented on
the screen, i.e., red, blue, magenta, green, orange, etc.
Interlace: A scanning process in which each adjacent line
belongs to the alternate field.
I.R.E.: Institute of Radio Engineers. Now combined with the
AlEE to form the IEEE.
I.R.E. Scale: An oscilloscope scale calibrated for compOSite
video and divided vertically into 140 units. The picture signal
occupies the range from 0 to 1 00 with syncs in the range 0
to -40.
Luminance: The monochrome or brightness part of the color signal, composed of specific proportions of the three primary colors, red, blue, and green.

Setup: The difference in level between the blanking level
and the reference black level expressed as a percent of the
reference white level.
Smear: Smear describes a picture condition where objects
appear extended in the horizontal direction producing an illdefined, blurry picture. This often occurs when the receiver
is tuned slightly above the proper pix carrier frequency.
Sync: Abbreviation for synchronizing or synchronization.
Sync Level: The level of the synchronizing pulse tips.
Vertical Blanking: The blanking signal at the end of each
field starting three lines before the vertical sync pulse.
Vertical Retrace: The return of the electron beam from the
bottom of the display to the top after a complete field has
been scanned.
V.I.R.S.: Vertical Interval Reference Signal. A quality control
signal added to a horizontal scan line during the vertical
blanking period. It is used to provide a chrominance, luminance and black level reference.
V.I.T.S.: Vertical Interval Test Signals. A series of test signals that are added to horizontal lines during the vertical
blanking for in-service testing of the transmission equipment. They can be deleted or added at various points in the
transmission link, unlike the VIRS, which is added at program origination and stays with the program material.
Vestigal Sideband Transmission: A broadcast transmission technique wherein only one side band of an amplitude
modulated carrier is fully transmitted with the other sideband (usually lower) truncated.
Video: The visible portion of the transmitted signal representing the picture.

N.T.S.C.: National Television System Committee, used in
reference to the system adopted for color television broadcasting in the U.S. at the end of 1953.
Noise: In a television picture, 'noise' refers to random interference producing a salt and pepper pattern over the picture. Heavy noise totally obscuring the picture is called

"snow

ll

•

Overshoot: An (excessive) response to a unidirectional signal change. OVershoot is often used deliberately to enhance the luminance portion of a signal.
Pairing: A partial or complete failure of interlace in which
scan lines of alternate fields fall in pairs, one on top of the
other.
Pedestal Level: See Blanking Level.
Percentage Sync:
Video: The ratio in percent of the amplitude of the synchronizing pulse to the peak amplitude of the picture signal between blanking and reference white level. For a
properly constituted composite video signal this is 40%.
RF: The ratio is a percent of the amplitude of the synchronizing pulse to the peak amplitude of the modulated
RF signal. For correct modulation this is 25%.
P.A.L.: Phase Alternation Line. A variation of the NTSC system involving phase reversal of one of the color difference
signals on a line by line basis, introduced into the U.K. and
Germany in 1967.
Picture Signal: That portion of the composite video signal
which is above the blanking level and contains the picture
information.
Pre-emphasis: An increase in the level of a band of frequency components with respect to the remainder of the

3-4

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Video Selection Guide

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VIDEO AMPLIFIERS
Gain

Package

Supply Voltage

Comments

LM592

120 MHz

Bandwidth

100,400

14 Pin DIP
14 PIN SO

±3V-±6V

Differential IN, Differential OUT

LM733

120 MHz

10,100,400

14 Pin DIP

±3V-±6V

Differential IN, Differential OUT

LM1201
(Advanced Information)

100 MHz

4-10

16 Pin DIP

+12V

Single Amplifier with
Black Level and Contrast
Control

LM1203

50 MHz

4-10

28 Pin DIP

+12V

Triple Amplifier System
with Black Level and
Contrast Control

LM359
(Note 1)

400MHzGBW
30MHz@Av= 1

14 Pin DIP

5V-22V

Dual Norton Amplifiers

VIDEO TIMING
Package

Supply Voltage

LM1391

PLL

Function

8 Pin DIP

Internal Shunt Zener

Comments

-

LM1880

No-Holds Vert/Horiz

14 Pin DIP

Internal Shunt Zener

-

LM1881

Sync Separator

8 Pin DIP
8 Pin SO

5V-15V

Outputs Provided:
Composite Sync
Vertical
Burst Gate
Odd/Even Field

VIDEO MODULATORS/DEMODULATORS
Function

Package

Comments

LM1496
(Note 2)

Balanced Modulator-Demodulator
(Modulator-Suppressed Carrier, AM
Demodulator-Synchronous, FM
Phase Detection)

14 Pin DIP
10 Pin TO-5
14 Pin SO

Operating Frequency to 100 MHz
Balanced Inputs and Outputs

LM1889

Modulates Color Difference,
Luminance, Audio onto
Low-VHF Channels

18 Pin DIP

DC Channel Switching
Chroma Reference

LM2889

Modulates Composite Video,
Audio onto Low-VHF Channels

14 Pin DIP

DC Channel Switching,
Low Distortion FM Sound
Modulator, Video Clamp

Note 1: Data sheet in Linear 1.
Note 2: Data sheet in Linear 3-Special Functions Chapter 5.

3-5

CD
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VIDEO IFs
Application

Package

Comments

LM1211
(Note 3)

Broadband Demodulator

20 Pin DIP

Operating Range 20 MHz-80 MHz
Quasi-Synchronous Detector
25 MHz Output Amplifier

LM1823

Video IF

28 Pin DIP

Operating Range 20 MHz-70 MHz
Synchronous Detector using PLL
9 MHz Output Amplifier

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(/)

0
CD

~
OTHER VIDEO PRODUCTS
Package

Supply Voltage

Comments

LM1044

Video Switch

24 Pin DIP

8V-16V

• DC Switch between 3 Composite Video
Channels or 2 RGB Channels
• 60 dB Channel Separation

LM1884
(Note 4)

TV Stereo Decoder

16 Pin DIP

9V-15V

Provides L - R, L + R Outputs
from Composite Input

LM1886

TV Video Matrix 0 to A

20 Pin DIP

+5V, +12V

Function

Encodes Luminance and Color Difference
Signals from 3-Bit RGB Inputs

Note 3: Data Sheet in Unear 3.
Note 4: Data Sheet In Unsar 3.

r-_ _ _-oVIDEO
OUTPUT

R

LM1875
LM2005
LM2878
LM2879

>---OTELEt.tETRY OUTPUT

TL/XX/0012-1

3-6

V 0--+--1
SYNC IN

Ho--+--I

VERTICAL / HORIZONTAL SWEEP
AND POWER SUPPLY
CIRCUITS
LMC555
LM675
SYNC
LM1578
SEPARATION
LM1880
LM1881
LM1875

H
YOKE
V
YOKE

.----+-..:

•: CRT

VIDEO IN
R 0---1-1---1 VIDEO AMPLIFICATION
WITH GAIN / DC
G
CONTROL
LM1201
B
LM1203

CONTRAST

HV
CRT
VIDEO

••

t - - - -..

BRIGHTNESS

FIGURE 1. Typical RGB Color Monitor Block Diagram

Application Notes* Cross Reference
Device

AN#

LM359

AN-278, AB-24

LM1823

AN-391

LM1886

AN-402

LM1889

AN-402

LM2889

AN-391, AN-402

'National Semiconductor Corporation Linear Application Notes

3-7

TLlXX/0012-2

C'II

m

&n

:l

~ National

Semiconductor

Corporation

LM592 Differential Video Amp
General Description

Features

The LM592 is a two stage differential input, differential output, wideband video amplifier. The use of internal seriesshunt feedback gives wide bandwidth with low phase distortion and high gain stability. Emitter follower outputs provide
low output impedances necessary to drive capacitive loads.
This device offers fixed gains of 100 and 400 with no external components plus the flexibility of adjusting the gain from
o to 400 with the addition of a single resistor. This flexibility
also allows the device to be configured as a high pass, low
pass, or band pass filter.

•
•
•
•

120 MHz bandwidth
Adjustable gains from 0 to 400
Adjustable pass band
No frequency compensation required

Applications
•
•
•
•

The LM592 is ideal for use in magnetiC memory systems.
The device is also very useful as a video and pulse amplifier
in video recorders and other communications systems.

Disc file memories
Magnetic tape systems
Thin film or plated wire memories
Wide band video amplifiers

Connection Diagram
Dual-In-Line and Small Outline Package
INPUT
1

NC

GAIN
SELECT
G'A

y+

NC

Order Number LM592M or LM592N
See NS Package Number M14A or N14A

INPUT
2

NC

7
NC OUTPUT
2

G2B G, B
GAIN
SELECT
Top View

TLlH/6701-1

Disc/Tape Phase Modulated Readback Systems
+5Y
+6Y

Q
AMPLITUDE: 1-10mY p-p
FREQUENCY: 1-4 MHz
I

I
I
I

3·----- I

-6Y
READ HEAD

6_

DIFFERENnATOR
AMPLIFIER

3-8

I
I
I

----·

ZERO CROSSING DETECTOR
TlIH/6701-2

r-

s::
Con

Absolute Maximum Ratings
Operating Temperature Range
O'Cto +70'C
Soldering Information
Dual-In-Line Package
Soldering (10 seconds)
260'C
Small Outline Package
Vapor Phase (60 seconds)
215'C
Infrared (15 seconds)
220'C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Differential Input Voltage
±5V
Common Mode Input Voltage
±6V
±8V
Vsupply
Output Current
10mA
Power Dissipation (Note 1)
500mW
Junction Temperature
+ 150'C
Storage Temperature Range
- 65'C to + 150'C

Electrical Characteristics T A =

25'C, unless otherwise specified, see test circuits, Vs =

± 6.0V (Note 5)

LM592
Characteristics

Test
Circuit

Test Conditions

1

RL = 2kn, VOUT = 3Vpp

Differential Voltage Gain
Gain 1 (Note 2)

400

Gain 2 (Note 3)

100

Bandwidth
Gain 1
Gain 2

2

Rise Time
Gain 1
Gain 2

2

Propagation Delay
Gain 1
Gain 2

2

VOUT = 1 Vpp

VOUT = 1 Vpp

Input Capacitance

Gain 2

Input Bias Current
BW = 1 kHz to 10 MHz

Input Voltage Range

1

Common Mode Rejection Ratio
Gain 2
Gain 2

1

Output Offset Voltage
Gain 1

1

Units
(Limit)

250
600
80
120

210
620
75
120

(Min)
(Max)
(Min)
(Max)
MHz
MHz

VCM =
VCM =

10.5
4.5

12

ns
ns(Max)

7.5
6

10

ns
ns(Max)

4
23

10

kn
kn(Min)
pF

2

Input Offset Current
Input NOise Voltage

Design
Limit
(Note 7)

40
90

Input Resistance
Gain 1
Gain 2

Supply Voltage Rejection Ratio
Gain 2

Typ

Tested
Limit
(Note 6)

±1V
± 1V, f

= 5 mHz

I!.Vs = ±0.5V

",A (Max)

26

6
31

±1

±1

V (Min)

86
60

60

50

dB (Min)
dB

70

50

50

dB (Min)
V (Max)

mA(Min)
mA(Max)

0.4

5

9
12

",Vrms

4

3

3.6

2.5

0.75
2.4
3.4
3
2.3

24

24

1

RL =

00

0.35

0.75

Output Common Mode Voltage
(Note 4)

1

RL =

00

2.9

2.4
3.4

Output Voltage Swing

1

RL = 2k

Output Sink Current
Output Resistance
Power Supply Current

20
1

RL =

18

00

",A (Max)

V (Min)
V (Max)

V (Min)
n

Note 1: For operation at elevated temperatures, these devices must be derated based on a thermal resistance of 8jA and Tjmax. 9jA = 90 aC/W in the liN" package

and 13S'C/W in the "Moo package. Tjmax = ISO'C.
Note 2: Pins GIA and GI8 connected together.
Note 3: Pins G2A and G28 connected together.
Note 4: Gain select pins open. Output Common Mode Voltage
Note S: Boldface numbers apply at temperature extremes.

= (Vat + Vo2l/2.

Note 6: Guaranteed and 100% production tested.

Note 7: Guaranteed (but not 100% production tested) over the operating temperature and supply voltage ranges. These limits are not used to calculate outgoing
quality levels.
3-9

CD
N

Typical Applications
Filter Networks

Impedance
Network

Desired
Filter

~

Vo(S) Transfer
V1(S) Function

Low Pass

1.4 X 104 [ __
1_]
L
s + R/L

High Pass

1.4X104[
1
]
R
s + 1/RC

Band Pass

s
]
1.4X104 [
L
s2 + R/Ls + 1/LC

TL/H/6701-10

C

~I-o

TL/H/6701-3

VO(S)
V,(S)

1.4 x 1()4
Z(s) + 2,.

TL/H/6701-11

1.4 x 1()4
Z(s)

+ 32

C

~I-o

BASIC CONFIGURATION

TL/H/6701-12

L

~
c

Band Reject

1.4X104 [
s2+1/LC
]
R
s2 + 1/LC + s/RC

TL/H/6701-13

Note: In the networks above, the R value used is assumed to include 2,., 0' approximately 320

Test Circuits
Test Circuit 1

Test Circuit 2

VOUT

TL/H/6701-4
TL/H/6701-5

Voltage Gain Adjust Circuit

SUl

SID.

TL/H/6701-6

v. = ±6V
TA = 25'C

3-10

Schematic Diagram

TLlH16701-7

Typical Performance Characteristics
Pulse Response vs
Temperature

Pulse Response
1.6

Vs=t6V
TA=25OC
RL =1 kll

1.4
1.2

~ 1.0
til o.a

;;l
g

0.6

5

OA

S
0

GAIN 2

//
II

0.2

~

0

1.6

~

til

GAIN I

1/

0.6

5

0.4

~

I'.
-25

,

~

~

GAIN

-IDO

Differential Overdrive
Time

Vs=:l6V
TA=25OC

I

-150

!lI

~

.~

-200
-250

~\

10

IDO

FREQUENCY (WHz)

40

ill

~

2D

0

1000

VS=:l6V
60 TA=25OC
GAIN 2
50

3D

!i!

Il
I

!

1=

~GAIN2

-350
I 2 3 4 5 6 7 B 9 10
FREQUENCY (WHz)

70 Recovery

l'

-300

o

llWE (ns)

f=!:::S.

-50

€:

-20

,t.

-D.2
-D.4
-15-10-5 0 5 1015 2D 25 3D 35

Phase Shift vs
GAIN 2
Vs=t6V
TA=25OC

Vs=t6V

Vs.':!~_

i~

o Frequency

,

y

llWE (ns)

Phase Shift vs
oFrequency

I'

1.0

~ 0.&

-D.2
-D.4
-15-10 -5 0 5 10 15 2D 25 3D 35

llWE (ns)

-5

1.2

~ os

-TA=25OC
TA=7O"C

0

-D.2
-D.4
-15-10 -5 0 5 10 IS 2D 25 3D 35

2
I TGAIN
A=25OC
Vs=tBV-RL=1 kll

1.4

:E

"'"

0.2

1.6

GAIN 2
Vs=t6V
RL =1 kll

TA=O"C

o.a

;;l
g

S

I
I

1.4
1.2
1.0

Pulse Response vs
Supply Voltage

10

V

V-

V

/

I--

o
o

40

60

120

160

20D

DIFFERENllAL INPUT VOLTAGE (mV)
TLIHI6701-B

3-11

N

0)

~

Typical Performance Characteristics

(Continued)

....I

Voltage Gain vs
Frequency

Gain vs Frequency
Temperature

60

i,

~

~

z

1l

50
40

'-'

':l
is

1\

40

~

30

8

[5

~

~
5 10

50100

20
TA=25
10

500 1000

5 10

w

~

20

Jlill

10

Vs =t3V

in

11111111

-10

50 100

5001000

1

z

1l
w

'-'

':l

~100

0

>

1.05

""'=I'

1.00
9.5

Vs=t6V

~

"S;:r-- ~AINI

l'.

8.5

1.2

1l

1.1

!li

1.0

~

0.9

I

0.8

':l

"'-,

9.0

TA = 25"C

1.3

z

w

10

10K

GAIN 2

0

7JJ
6.0

z'-'

5JJ

i

1jj
'-'

3.0

5

2.0

5
0

~

s-

:::1
0>-

4.0

':l
~

Vs=t6V
TA=25"C
RL = 1 K.Il

zC1
w~
~~

~=>

=>"

10

20

GAIN 1

0.7
0.6

V

30

40

50

60

70

SUPPLY VOLTAGE (tV)

Supply Current, Output
Voltage and Current
Swing vs Supply Voltage

Output Voltage Swing vs
Load Resistance

24
22
20
18
16
14
12
10

6

5 10

50 100

7.0
0

~
:;
Cl

~

!

:5
0

1

SOD 1000

3.0

fREQUENCY (MHz)

4.0

5.0

6.0

7.0

0
8.0

0:

6.0

z'-'

5JJ

.l.
2:-

1jj
'-'

3.0

>-

2.0

~
6

1.0

o
1

80

~A =25OC

70

100

S

90
80

!li

70

~

':l

60
50

~
w

~

40
30

g

20
10

'"

>-

=>

III

o
10K

lOOK

1M

10M

fREQUENCY (Hz)

100M

50 100

500 1000

Supply Current and
Input Resistance vs
Temperature

Input Noise Voltage vs
Source Resistance

GAIN 2)!!11
Vs =±6V

11111111

rtTT11I1r-..

5 10

LOAD RESISTANCE (n)

Common Mode
Rejection Ratio vs
Frequency
90

I

4.0

':l
~

VS=t6V
TA =25"C

SUPPLY VOLTAGE (V)

100

I

3

i;;;

o

/

TEMPERATURE ("C)

""ffl

1.0

............

b--

0.4

Output Voltage Swing vs
Frequency
0:

k-'
r-l-

~

O.S
8.0

lK

5001000

1.4
"",GAIN 1

lK

50100

Voltage Gain vs
Supply Voltage

LtO

10

S 10

fREQUENCY (MHz)

Voltage Gain vs
Temperature

Voltage Gain vs RADJ

~

~

~

Vs=t8V
Vs=t6V:;-;J

fREQUENCY (MHz)

z

1l

30

~

llllilll
1

~

is

GAIN 2
TA=25"C
RL = 1 Kll

50

40

~

~

60

1l
w

_h~~~"C

fREQUENCY (MHz)

10K

z

~

-10
1

~

TA=O"C

in

-10

s

Vs=t6V
RL = 1 Kll
GAIN 2

50

1l
~

J

10

~

z

w

20

~

~

GAIN 2

30

~

s

Vs=t6V
TA =25°C
RL = 1 Kll

GlrN

Gain vs Frequency vs
Supply Voltage

60

lllGAIN 21111
Vs=t6V
TA =25"C
BW= 10MHz

Ul

21

60

Vs =±6V
GAIN 2

20

50

19

40

60

SUPPLY CURRENT

50

18

40
17

30
20
10

.,.

~

~

~

30

r- 20

INPIUT R~'S~CE

16

o
1

g
10

100

lK

SOURCE RESISTANCE (ll)

10K

10

o

z

S
iliin

~

~

~

0
10

20

30

40

50

60

70

TEMPERATURE ("C)
TL/H/6701-9

3-12

,-------------------------------------------------------------------------, r

3:
~
Co)

NatiOnal

~ Semiconductor

......

Corporation

r

3:
~
Co)

LM733/LM733C Differential Amp

o

General Description

Features

The LM733/LM733C is a two-stage, differential input, differential output, wide-band video amplifier. The use of internal
series-shunt feedback gives wide bandwidth with low phase
distortion and high gain stability. Emitter-follower outputs
provide a high current drive, low impedance capability. Its
120 MHz bandwidth and selectable gains of 10, 100 and
400, without need for frequency compensation, make it a
very useful circuit for memory element drivers, pulse amplifiers, and wide band linear gain stages.
The LM733 is specified for operation over the -55'C to
+ 125'C military temperature range. The LM733C is specified for operation over the O'C to + 70'C temperature range.

II

120 MHz bandwidth
.. 250 k!1 input resistance
.. Selectable gains of 10, 100, 400
II No frequency compensation
II High common mode rejection ratio at high frequencies

Applications
Magnetic tape systems
Disk file memories
II Thin and thick film memories
.. Woven and plated wire memories
.. Wide band video amplifiers
II
II

Connection Diagrams
DuaJ.ln-Line Package

Metal Can Package

GAIN
SELECT

INPUT

OUTPUT

1

14

1

13

TLlH/7866-2

Note: Pin 5 connected to case.

Top View
Order Number LM733H or LM733CH
See NS Package Number H10D
INPUT
2

NC

-GZB

G1B

V'

NC

GAIN
SELECT

OUTPUT
2
TL/HI7B66-1

Top View
Order Number LM733CN
See NS Package Number N14A

3-13

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Diffentiallnput Voltage
±5V
Common Mode Input Voltage
±6V
±8V
VCC
Output Current
10mA

Electrical Characteristics (TA =
Characteristics
Differential Voltage Gain
Gain 1 (Note 2)
Gain 2 (Note 3)
Gain 3 (Note 4)
Bandwidth
Gain 1
Gain 2
Gain 3
Rise Time
Gain 1
Gain 2
Gain 3
Propagation Delay
Gain 1
Gain 2
Gain 3

Test
Circuit

Power Dissipation (Note 1)

500mW
+ 150·C

Junction Temperature
Storage Temperature Range

-65·Cto + 1500C

Operating Temperature Range
LM733
LM733C

- 55·C to + 125·C
OOCto +70·C

Lead Temperature (Soldering, 10 sec.)

2600C

25·C, unless otherwise specified, see test circuits, Vs = ±6.0V)

LM733

Test Conditions

1
RL = 2 kO VOUT = 3 Vp-p

LM733C

Units

Min

Typ

Max

Min

Typ

Max

300
90
9.0

400
100
10

500
110
11

250
80
8.0

400
100
10

600
120
12

40
90
120

2

VOUT = 1 Vp-p
2

40
90
120

MHz
MHz
MHz

10.5
4.5
2.5

10

10.5
4.5
2.5

12

ns
ns
ns

7.5
6.0
3.6

10

7.5
6.0
3.6

10

ns
ns
ns

VOUT = 1 Vp-p
2

Input Resistance
Gain 1
Gain 2
Gain 3

20

Input Capacitance

4.0
30
250

10

2.0

Gain 2

4.0
30
250

kO
kO
kO

2.0

pF

Input Offset Current

0.4

3.0

0.4

5.0

Input Bias Current

9.0

20

9.0

30

Input Noise Voltage

BW = 1 kHz to 10 MHz

12

12

/LA
IJ.Vrms

±1.0

Input Voltage Range

1

Common Mode Rejection Ratio
Gain 2
Gain 2

1

VCM= ±1Vf:S:100kHz
VCM = ±1Vf = 5 MHz

60

86
60

60

86
60

dB
dB

50

70

50

70

dB

Supply Voltage Rejection Ratio
Gain 2

±1.0

/LA

1

ilVs = ±0.5V

Output Offset Voltage
Gain 1
Gain 2 and 3

1

RL =

00

Output Common Mode Voltage

1

RL =

00

Output Voltage Swing

1

RL = 2k

2.5

Output Sink Current

1.5
1.0

2.4

2.9

3.4

3.0

4.0
3.6
20

Output Resistance
Power Supply Current

0.6
0.35

1

RL =

18

00

3-14

V

0.6
0.35

1.5
1.5

V
V

2.4

2.9

3.4

V

3.0

4.0

2.5

3.6

mA

0

20
24

18

24

mA

Electrical Characteristics (Continued)
(The following specifications apply for -55·C < TA < 125·C for the LM733 and O·C
±6.0V)
Test
Circuit

Characteristics
Differential Voltage Gain
Gain 1
Gain 2
Gain 3

LM733

Test Conditions
Min

RL

1

< TA < 70·C for the LM733C, Vs =
LM733C

Typ

200
80
8.0

= 2 kfi, VOUT = 3 Vp-p

Input Resistance Gain 2

Max

Min

600
120
12.0

250
80
8.0

8

Typ

600
120
12.0

8

Input Offset Current

kfi

5

Input Bias Current

40

Input Voltage Range

1

Common Mode Rejection Ratio
Gain 2

1

VCM

Supply Voltage Rejection Ratio
Gain 2

Units
Max

6

/LA

40

/LA

±1

±1

V

= ±1Vf ~ 100 kHz

50

50

dB

= ±0.5V

50

50

dB

1

l!.Vs

Output Offset Voltage
Gain 1
Gain 2 and 3

1

RL

=

Output Voltage Swing

1

RL

= 2k

1.5
1.5

1.5
1.2

00

Output Sink Current

V
V

2.5

2.8

Vpp

2.2

2.5

rnA

27
27
rnA
Power Supply Current
1
RL = 00
Nole 1: The maximum iunction temperature of the LM733 is lSO'C, while that of the LM733C is l00'C. For operation at elevated temperatures devices in the TO100 package must be derated based on a thermal resistance of 1SO'C/W junction to ambient or 4soC/W junction to case. Thermal resistance of the dual-in-line
package is 90'C/W.
Nole 2: Pins G1A and Gl B connected together.
Nole 3: Pins G2A and G2B connected together.
Nole 4: Gain select pins open.
Nole 5: Aefer to AETS733X drawing for specifications of LM733H version.

Typical Performance Characteristics
Pulse Response

u

Vs .. :t.6V
1,,_25°C
RL " 1 Kn

1.4

12

~

~
~

~

...
1.0

GAIN I

GAIN 3

0

1.0

rr

T,,-2!j°C

I- TA "

'lIl"C

-15 -10 -5 0

51.1520253035

I'

-0.'-15-1.

-D.4
-5

a

0

IIII~

-50

"

-15

..,0
-25
•

1

2

3 •

5

fRE~UENCY

,

1

(MHd

"'00

Ys-.tIV
T -Z5"C

.

• ,.

-3011
GAIN 1

-350
1

5 "

50 lDO

FREOUENCY (MHz)

10

]

~

E

GAIN 3
"'50

II

Differential Overdrive
Recovery Time

,

-150

5 10 15 20 25 3035
TIME Ins)

[\

-10D

!i

-15-10 -5 0

5 10 15 28 25 3D 35

l,,'"ZS"C

-10

"

0

.o.z

Phase Shift
vs Frequency

-,

Vs .. :t.6V
Vs "i3V

o.z

IJ

Phase Shift
vs Frequency

C

IY

0..

OA

TIME(ns)

GAIN!
Vs"':t.6V

v~.lBV ~:~5~

...
0.,
1.0

TIME(ns)

0

GAINZ

12

TA "125"C

.o.z

-D.4

i

12
0.'
a&

Pulse Response vs
Supply Voltage
1.6
1.4

GAIN2
Vs·tOV
TA"'-55"C RL'", Kn

~ D.',

o.z
-12

Ii:

~

~

D.4

Pulse Response vs
Temperature

1.4

~

GAIN!

0.6

1.6

A~I'
50D1DIID

I
~

'0

Vs"z&V
T,,-2S"C
GAINZ

50

,I

'0

/

30

I•
2D

,I

10

I-

•

20 40 8D aD 100 120 148 110 liD zoo

DIFFERENTIAL INPUT VOLTAGE (mV)

TL/H/7866-6

3-15

o

C')
C')

"'"

Typical Performance Characteristics (Continued)

:iii:

...J
........
C')
C')

"'"

:iii:

6D

~
z

5D

w

4D

g
'"

~>

r--

llGAll,

2D I -

g

-

GAll3

4D

~

30

>

"w

2D

~
z

10

"z

6D

6D

RL" 1 KH
GAINl

-ID

'I

~

JD

"z

1.15
Vs= ±6V
TA =2S'C

w

IDD

f'.

..~

1,05

>
w
>

-

~

......

Ci

1.ID

g
w
'"

'"

'"

z

1"'lD
10

IDD

Voltage Gain vs
Supply Voltage

Vs '" ;;6V

IGAI~

L\

I.D

\f'
1\

.95
.90

\

.B5

n
D--L

z

g

1.2

'"

1.0
.9

w

""g

IGAI, 2

20

60

V

1.1

~>

3

NI
-20

TA "25C

1.3

II

\GAINI

..-r

M

.B

7.D
Vs

=±6V

I-H*-+-++tt-+TA" 25C

0-

~

5.0

~

4.0

t-H*-I--+-Ht-+-+l-tt---l
,...+-+*-+....t+l+-+-+l-+1--1

c e
cO-

~

3.0

I-H*-I--+-PiJ-+-+l-+1--1

~

2,0

I-H*-I--++I+'Irt
,-++++-+

'"

RL = 1 KH

g 1.0t-H*-I--++It--t-+l-tt---l
5 lD

50 100

~

~Ci

"'~~
0-"

"'~
~u
u"

i~

j,./J.

.6

VGAINI

.5
.4

100

140

4

~
~

~

i
"

c

"c
"~
z

tc:t-tH-I--+Ht+-++tt Vs = ! 6V
H-tH-I-"'I-ot:tt+-++tt TA =25 C

80

7DH-tH-++Hf"j..,Htl--H-H-H

:~ ~~~~=~=~~~~=~~~:t~~~~-1

H-tH-I--+H+++l-ll-H-+1-f"f
H-tH-I--+Ht+-++ll-H-ttH
H+tt-t--+ttt-H+H-I-+++H

4D
30
2D
10

o

4.D

5.D

6.D

7.0

tOOk

1M

tOM

FREQUENCY (Hz)

6.0

f-t-+*-I--+-+t+-i- TA =- 25

~
~

5.0

I--H-++--+-++tt--I--H-H--l

t!'

4.0
3.0

I-t-+*-+-+-H~+--H-tt---l

~

2.0

I-t-+*-+-+..H+-+-+l-tt---l

1.0

t-t-+*....
-tA-+t+-+-+l-tt---l
10

21

BD

w

70

BW= 10MHz

'"'"

6D

1
;;
.3

~>
w

~

0~

z

100M

Vs"

2D

"
.§

i

5D
40

>~

it

3D

iil

20

Gr 2

100

1k

lDk

6D

v'"
pc ......

V

5D

SUPPL V CURRENT

IB
17

nl~l~
,,-s,s~

16

4D
3D

f'

,,~

2D

PI
-60

-2D

~

'"

~

~

~

g

lD

II

14
10

7D

·sv
1

19

15

10

SOURCE RESISTANCE (\!)

5k 10k

Supply Current and Input
Resistance vs TemperatlJre

GAIN 2
Vs'" t6V
TA '" 25 C

9D

50100200 500 lk
LOAD RESISTANCE h!)

Input Noise Voltage vs
Source Resistance
IDD

C

~

B.O

~~~~~~~-L~~

10k

Vs" ~6V

'2

SUPPL Y VOLTAGE (V!

100 r-r"TT1-"T-'-rn-"'''''''''''-G~A~'N~2'''''''
90

7.0 r-TTTr"T""T"r-rr-r-r"TT..-,
_<>.

3.D

Common Mode Rejection
Ratio vs Frequency

=-

Output Voltage Swing vs
Load Resistance

§

5001000

5
SUPPL Y VOLTAGE (, V)

24
22
2D
lB
16
14
12
10
B

FREOUENCY (MHz)

-

GAIN2/

.7

Supply Current, Output Voltage
and Current Swing vs Supply
Voltage

~ 6.0

....

GAIN 3

TEMPERATURE IC)

Output Voltage Swing vs
Frequency

5DD IDDD

1.4

1\

.BD
-60

10k

1k

5D 10D

FREQUENCY (MHz!

Voltage Gain vs Temperature

IDDD

Vs" ;;3V

5 ID

SOD 1000

FREOUENCY (MHz)

Voltage Gain vs RADJ

g"

50 100

~8V

~V ~ ~ ';;6V

II
II

-10
5 ID

~\Vs =

1

lD

"'";;;

IT.o.:125C

SOD 1000

5D 100

,,~

2D

"

TA~wCt

FREQUENCY (MH,)

;

40

'"

-ID
5 ID

~>

III

T A =-55C

GAIN 2
TA = 25 C
RL = 1 K!!

5D

"g

TA ,,70'C __

;;;

;;;

~

Vs = !6V

5D

w

'"

lD

~z

z

GAIN2

3D

"
"z

~

Vs ":!:.6V
TA =2S"C
RL ", t Kn

-

Gain vs Frequency vs
Supply Voltage

Gain vs Frequency
Temperature

Voltage Gain vs Frequency

...J

20

60

100

14D

TEMPERATURE ( C)

TLIH/7866-7

3-16

Test Circuits
Test Circuit 1

Test Circuit 2

VOUT

510

510

TL/H/7866-4

TL/H17866-3

Voltage Gain Adjust Circuit

510

TLlH17866-5

Vs

~

6V, TA

~

25'C

(Pin numbers apply to TO-5 package)

Schematic Diagram
8(101

Rl

2.4K

R2
2.4K

R8
10K

1(141

RII

1.

1111

GAIN

SElECT

G,.

"

..

R'
R12

OUTPUT 1

OUTPUT 2

7181

&m

7.

10(12) G2A

R.

R6

590

'"

V-

Numbers in parentheses show DIP connections.

'lSI
TL/H/7B66-B

3-17

~
~

Q

.....

:i
...I

r---------------------------------------------------------------------,
NatiOnal

~ Semiconductor

PRELIMINARY

Corporation

LM 1044 Analog Video Switch
General Description

Features

The LM1044 is a monolithic D.C. controlled analog switch,
allowing the selection of anyone of three composite video
channels of voltage gain +6 dB or two R.G.B. channels
with voltage gains of 0 dB. Channel selection is achieved by
utilizing clocked, TTL compatible control logic which can interface to most micro-controllers. The device is supplied in a
24 pin dual-in-line package.

•
•
•
•

R.G.B. channels are level clamped
Wide bandwidth, typically 10 MHz @ 2 Vp.p
High signal to noise ratio, typically -60 dB
Excellent channel isolation and crosstalk
typically -60 dB and -50 dB respectively @ 5 MHz
• High RGB output currents, typically 4 mA peak
• Logically compatible with LM1038 audio select switch

Block Diagram
VIDEO I/P(I)

V. SUPPLY

>-t-..... >-__.......~23::..VIDEO/SYNC O/P

VIDEO I/P (2)

V/')Io_+t'2;;;;2_CLOCK ENABLE

VIDEO I/P (3)
R I/P(I)

21:"'CONTROL A
-1-...-++.:.

G I/P(I)

/]-.;...,.++.::20:"'CONTROL B
I I
• I

L-:'i-I-l-l:..:9~CONTROL C

B I/P(I)

SYNC(!)
R I/P(2)

>.....,-t--;r--t.:::~-t.;.;17~R O/P

G I/P(2)

>-..........-+--1

B I/P (2)

> ....--t--; :.>_~15::"B O/P

O/p

+-_-+"",14;"'COMPOSITE VIDEO BIAS

SYNC (2)
GROUND

>_~16:"'G

12

...-_r;13:... BIAS DECOUPLE

-

TUH/9252-1

Order Number LM1044N
See NS Package Number N24A

3-18

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
Vs = 17V
Operating Temperature Range
O·Cto +70·C

Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)

- 65·C to + 150·C
260·C

Electrical Characteristics Vs = 12V, TA = 25·C unless otherwise stated
Parameter

Test Limit

Conditions

Min
Supply Voltage

8

Supply Current
P.S.R.R.

Design Limit

Max

Min

16

8

60
Signal

=

1 Vp•p @ 1 kHz

50

Signal To Noise
Ratio
TTL High Level
(A,B,C Enable)

2.0

TTL Low Level
(A,B,C Enable)

Typ

Units
Max

12

16

V

42

60

rnA

50

dB

60

dB

2.0

V

0.8

0.8

V

Enable Pulse Length

5.0

p's

Channel Select Time

4.0

p.s

COMPOSITE VIDEO CHANNELS
Maximum Input
Voltage Swing

RL = 6000, Vs = 12V
Output T.H.D. = 1 %

1.5

1.5

Vp•p

Input Impedance

2.0

Dynamic Output Impedance

10

=

Voltage Gain

Signal

Bandwidth

-3 dB, RL

Channel Isolation In Mute

Signal

Crosstalk

Signal

=
=

500 mV

=

@

1 MHz

6000

kO
0

5.5

5.5

6.0

6.5

dB

6.0

6.0

10.0

MHz

500 mV

@

5 MHz

-60

dB

500 mV

@

5 MHz

-50

dB

Load Resistance

600

0

9.0

V

R.G.B. CHANNELS
Clamp Drive High
Level Threshold
Clamp Drive Low
Level Threshold

5.0

Clamp Pulse Delay
Input Voltage Swing

0.2
RL = 6000
Output T.H.D.

ns
3.0

= 1%

3·19

V

Vp.p

Electrical Characteristics Vs =

12V, TA

=

25'C unless otherwise stated (Continued)
Test Limit

Parameter

Design Limit

Condition

Units
Min

Max

Min

Typ

Max

Input Impedance

2.0

Dynamic Output Impedance

10

0

-0.5

0

dB

6.0

10.0

=

Voltage Gain

Signal

Input Bias Current

Clamp Drive Low. DC bias

Bandwidth

-3 dB, RL

500 mV @ 1 MHz

=

-0.5

=

7V

6000

50
6.0

Load Resistance
Channel Isolation

Signal

Crosstalk

Signal

=
=

kO

+0.5
50

/LA
MHz

600

0

500 mV @ 5 MHz

-60

dB

500 mV

-50

dB

@

5 MHz

Application Notes
Signal channel selection is achieved by the application of
D.C. voltages to control pins 19, 20, 21, and 22. Pin 22 is the
logic enable pin and may be used to clock in logic data on
pins 19, 20, and 21 by applying a pulse of > 5 /Ls. Alternatively pin 22 may be wired TTL HIGH and channels selected
directly by applying the appropriate logic levels on pins 19,
20 and 21.

The control logic of the LM1044 is designed to be compatible with that of the LM1038N four channel stereo audio
switch. The control pins of each device may be connected
in parallel to give stereo audio selection on Composite Video channels 1, 2 and 3 and RGB channell. This is
achieved by connecting pins 19, 20, 21 and 22 of the
LM1044 to pins 1,16,3 and 18 of the LM1038N respectively.

Control Logic

Channel Selected

Pin 22

Pin 19

Pin 21

Pin 20

1

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

1
1

1
1
1
1

1
0
1
0

1
1
0
0

0

X

X

X

1

3-20

Composite Video 1,
RGB outputs muted
Composite Video 2,
RGB outputs muted
Composite Video 3,
RGB outputs muted
RGB 1 with sync.
RGB 2 with sync.
Mute
Mute
Mute
Previous selection
retained

r-------------------------------------------------------------------------, r
....
Application Circuits
==
Q

""'""'

CV OR
SYNC OIP

.Y.

Coupling Capacitors
RGB and Sync ilps

100 nF

RGB and Sync olps

10I'F

Composite Video olp 10 I'F
Composite Video ilps 100 nF

TUH/9252-2

3-21

~ Semiconductor
NaHonal

ADVANCED INFORMATION

CorporaHon

LM 1201 Video Amplifier System
General Description

Features

The LM1201 is a wideband video amplifier system intended
for high resolution monochrome or RGB monitor applications. In addition to the wideband video amplifier the
LM1201 contains a gated differential input black level clamp
comparator for brightness control and an attenuator circuit
for contrast control. The LM1201 also provides a "Drive"
pin for setting system gain and peaking of the video amplifier. The LM1201 also contains a voltage reference for the
video input. For medium resolution RGB color monitor applications also see the LM1203 Video Amplifier System data
sheet.

•
•
•
•

Wideband video amplifier (100 MHz)
Attenuator circuit for contrast control (>40 dB range)
Externally gated comparator for brightness control
Provisions for external gain set and peaking of video
amplifier
• Video input voltage reference
• Low impedance output driver

Block and Connection Diagram
Video
IN
16

1
Gnd1

Contrast
Cap

14

Contrast
Cap
13

VCC2
12

2

5

Clamp
Cap

Clamp
Gate

Drive
11

6
Clamp(+)

Vcc3
10

Clam (-)
9

8
Video
OUT
TL/H/9289-1

Top View

3-22

rNatiOnal

~ Semiconductor

PRELIMINARY

Corporation

LM 1203 RGB Video Amplifier System
General Description

Features

The LM1203 is a wideband video amplifier system intended
for high resolution RGB color monitor applications. In addition to three matched video amplifiers, the LM1203 contains
three gated differential input black level clamp comparators
for brightness control and three matched attenuator circuits
for contrast control. Each video amplifier contains a gain set
or "Drive" node for setting maximum system gain (Av = 4
to 10) as well as providing trim capability. The LM1203 also
contains a voltage reference for the video inputs.

• Three wide band video amplifiers (70 MHz @ -3dB)
• Inherently matched (± 0.5 dB) attenuators for contrast
control
• Three externally gated comparators for brightness control
• Provisions for independent gain control (Drive) of each
video amplifier
• Video input voltage reference
• Low impedance output driver

Block and Connection Diagram
LM1203 RGB AMP
(TOP VIEW)
Vee l

28

Vee l

CONTRAST CAP

2

27

R DRIVE

CONTRAST CAP

3

26

R CLAMP(-)

R VIDEO IN

4

25

R VIDEO OUT

R CLAMP CAP

5

24 R CLAMP(+)

G VIDEO IN

6

23 VCC2

GROUND

7

22

G DRIVE

G CLAMP CAP

8

21

G CLAMP(-)

20

G VIDEO OUT

B VIDEO IN
B CLAMP CAP

10

19 G CLAMP(+)

VINREf

11

18 B DRIVE

CONTRAST

12

17 B CLAt.lP(-)

Vee l

13

16 B VIDEO OUT

CLAt.lP GATE

14

15 B CLAMP(+)

TL/H/9178-1

FIGURE 1
Order Number LM1203N
See NS Package Number N28B

3-23

:s::
.....
N

oCo)

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, Vee Pins 1, 13, 23, 28
(Note 1)
Voltage at Any Input Pin, VIN
Video Output Current, 116, 20 or 25

O·Cto +70·C

Storage Temperature Range, T8TG

-65·C to + 150·C

Lead Temperature, (Soldering, 10 sec.)

Vee ~ VIN ~ GND
28mA
2.5W

50·C/W
150·C

Electrical Characteristics Test Circuit, TA =

25·C; VCCl = Vee2 = 12V

DC Static Tests S17,21,260pen;V12 =

6V;V14 = OV;V15 = 2.0V unless otherwise stated

Label

Conditions

Parameter

Is

Supply Current

V11

Video Input Reference Voltage

265·C

ESD susceptibility
2kV
Human body model: 100 pF discharged through a 1.5 k.!1
resistor

13.5V

Power Dissipation, Pd
(Above 25·C) Derate Based on IIja and TJ
Thermal Resistance, IIja
Junction Temperature, Tj

Operating Temperature Range, T A

Vee 1 only

Typ

Tested
Limit (Note 2)

Design
Limit (Note 3)

(Limits)
Units

73

90.0

2.4

2.2

VMIN

2.6

VMAX
/LA Max

mAMax

Ib

Video Input Bias Current

Any One Amplifier

5.0

20

V141

Clamp Gate Low Input Voltage

Clamp Comparators On

1.2

0.8

VMIN

V14h

Clamp Gate High Input Voltage

Clamp Comparators Off

1.6

2.0

VMP;X

1141

Clamp Gate Low Input Current

V14 = OV

-0.5

-5.0

/LA Max

114 h

Clamp Gate High Input Current

V14 = Vee

0.005

1

/LA Max

Iclamp+

Clamp Cap Charge Current

V5, 8 or 10 = OV

850

/LA

Iclamp-

Clamp Cap Discharge Current

V5, 8 or 10 = 5V

-850

/LA

Vol

Video Output Low Voltage

V5, 8 or 10 = OV

1.2

V

Voh

Video Output High Voltage

V5,80r10 = 5V

8.9

V

AVo(2V)

Video Output Offset Voltage

Between Any Two Amplifiers
V15 = 2V

±0.5

±50

mVMax

AVo(4V)

Video Output Offset Voltage

Between Any Two Amplifiers
V15 = 4V

±0.5

±50

mVMax

AC Dynamic Tests S17, 21, 26 Closed; V14 =
Symbol

Parameter

OV; V15 = 4V; fiN = 10 KHz unless otherwise stated

Conditions

Typ

Tested
Limit (Note 2)

Design
Limit (Note 3)

Units
(Limits)

Avmax

Video Amplifier Gain

V12 = 12V, VIN = 560 mVp-p

6.6

VIV

Avmid

Video Amplifier Gain

V12 = 5V, VIN = 560 mVp-p

2

VIV

V1210w

V12 for Av Low

VIN = 1 Vp-p (Note 4)

2

V

AAvmax

Video Gain Match at Av max

V12 = 12V (Note 5)

±0.2

dB

AAvrnid

Video Gain Match at Av mid

V12 = 5V (Note 5)

±0.2

dB

AAvlow

Video Gain Match at Av low

V12 = V12 low (Notes 4, 5)

±0.3

dB

T.H.D

Video Amplifier Distortion

V12 = 3V, VIN = 1 Vp-p

0.5

%

f(-3dB)

Video Amplifier Bandwidth

V12 = 12V (Notes 6, 8)

70

MHz

3-24

AC Dynamic Tests S17,21,26Closed;V14 = OV;V15 = 4V;fIN = 10 kHz unless otherwise stated (Continued)
Symbol
Vsep

Parameter

Conditions

Typ

7)

Video Amplifier 10kHz Isolation

V12 = 12V (Note

Video Amplifier 10 MHz Isolation

V12 = 12V (Notes

10 kHz
Vsep

7, 8)

10MHz

Tested

Design

Units

Limit (Note 2)

Limit (Note 3)

(Limits)

-60

dB

-40

dB

Nole 1: Vee supply pins 1, 13,23.28 must be externally wired together to prevent internal damage during Vee power onloff cycles.
Nole 2: These parameters are guaranteed and 100% production tested.
Nole 3: Design limits are guaranteed (but not 100% production tested). These limits are not used to calculate outgoing quality levels.
Note 4: Determine V1210w for -40 dB attenuation of output. Reference to Av max.
~

Nole 5: Measure gain difference between any two amplifiers. VIN

1 Vp-p

Nole 6: Adjust Input frequency. fin. from 10kHz (Av max ref level) to the -3 dB corner frequency (f - 3 dB). VIN

~

560 mVp-p

Nole 7: VIN ~ 560 mVp-p at fiN ~ 10 kHz to anyone amplifier. Measure output levels of the other two undriven amplifiers relative to driven amplifier to determine
channel separation. Terminate the undriven amplifier inputs to simulate generator loading. Repeat test at fiN ~ 10 MHz for Vsep ~ 10 MHz.
Nole 8: Special test fixfUre without socket required.

Vee
+12V

0.01

J'F

1I
1?

~.

50.0.

~
~
~
10K

~

Vee l

0.1

Vee l

28

2

27

3

26

4

25

5

24

100.0.

J'F
0.1

J'F

0.1

J'F
6

Vee2

10K

23

Ltd

7

1203

22

D.U.T_

0.1

8

21

9

20

10

19

11

18

12

17

13Veel

16

14

15

J'F

50.0.

V12
CONTRAST

100.0.

V14
CLAtdP GATE

TLlHI9178-2

FIGURE 2. LM1203 Test Circuit

3-25

~ r-------------------------------------------------------------------------------------~

CI
C'II

.:::E
...I

+

~100JLF
28

RED DRIVE

0.1 JLF

~
R

5JLF

~JLF

Sl.n

2

27

3

26

4

25

0.1 JLF

~

I-I--,\M~W.~

1-1---....--1--+

TO RED
CASCaDE
DRIVER

390.n

5

24

TO HV
SUPPLY

lK

23

GREEN DRIVE
Sl.n

7
8

211-1-+----.

9

20

10

19

11

18

H+......---II---I
390.n

H-+-'\o/llv-...,
91.n

12

17

H-+----.

13

16

1-1-+-....+-.

14

15

~0.01 JLF

CONTRAST
CONTROL

~O.lJLF

1OK

10K

10K

BLACK LEVEL
(BRIGHTNESS)
CONTROL

V

;:;;BLAC;-;;;CK"'L;;::EV"'E:;-L
GATE IN

0.0lJLF
TL/H/9178-3

FIGURE 3. LM1203 Typical Application

3·26

.-----------------------------------------------------------------------------'r

s:
.....

LM 1203 RGB Video Amplifier Application Notes

N

C)

c.:I

Applications Information
Figure 4 shows the block diagram of a typical analog RGB
color monitor. The RGB monitor is used with CAD/CAM
work stations, PC's, arcade games and in a wide range of
other applications that benefit from the use of color display
terminals. The RGB color monitor characteristics may differ
in such ways as sweep rates, screen size, CRT color trio
spacing (dot pitch), or in video amplifier bandwidths but will
still be generally configured as shown in Figure 4. Separate
horizontal and vertical sync signals may be required or they
may be contained in the green video input Signal. The video
input signals are usually supplied by coax cable which is
terminated in 75!l. at the monitor input and internally ac cou-

pled to the video amplifiers. These input signals are approximately 1 volt peak to peak in amplitude and at the input of
the high voltage video section, approximately 6V peak to
peak. At the cathode of the CRT the video signals can be as
high as 60V peak to peak. One important requirement of the
three video amplifiers is that they match and track each
other over the contrast and brightness control range. The
Figure 4 block labeled "VIDEO AMPLIFICATION WITH
GAIN AND DC CONTROL" describes the function of the
LM1203 which contains the three matched video amplifiers,
contrast control and brightness control.

v 0---11---1
SYNC IN

Ho--+--t

VERTICAL / HORIZONTAL SWEEP
AND POWER SUPPLY
CIRCUITS

VIDEO IN

Ro--++--t
G 0---11-4---1
B

VIDEO At.tPLlFICAnON
WITH GAIN / DC
CONTROL

CONTRAST

BRIGHTNESS

FIGURE 4. Typical RGB Color Monitor Block Diagram

3-27

TlIH/9178-4

Circuit Description
Figure 5 is a block diagram of one of the video amplifiers
along with the contrast and brightness controls. The contrast control is a dc-operated attenuator which varies the ac
gain of all three amplifiers simultaneously while not introducing any signal distortions or tracking errors. The brightness
control function requires a "sample and hold" circuit (black
level clamp) which holds the dc bias of the video amplifiers
and CRT cathodes constant during the black level reference
portion of the video waveform. The clamp comparator,
when gated on during this reference period, will charge or
discharge the clamp capacitor until the plus input of the
clamp comparator matches that of the minus input voltage
which was set by the brightness control.

to the video input is through the 10 kO resistor which is
connected to the 2.4V reference at pin 11. The low frequency roll-off of the amplifier is set by these two components.
Transistor 01 buffers the video signal to the base of 02.
The 02 collector current is then directed to the Vee 1 supply directly or through the 1k load resistor depending upon
the differential DC voltage at the bases of 03 and 04. The
03 and 04 differential base voltage is determined by the
contrast control circuit which is described below. RF decoupiing capacitors are required at pins 2 and 3 to insure high
frequency isolation between the three video amplifiers
which share these common connections. The black level dc
voltage at the collector of 04 is maintained by 05 and 06
which are part of the black level clamp circuit also described
below. The video signal appearing at the collector of 04 is
then buffered by 07 and level shifted down by Z1 and 08 to
the base of 09 which will then provide additional system
gain.

Figure 6 is a simplified schematic of one of the three video
amplifiers along with the recommended external components. The IC pin numbers are circled with all external components shown outside of the dashed line. The video input
is applied to pin 5 via the 10 ,...F coupling capacitor. DC bias

LM1203
LOW VOLTAGE
VIDEO

EXTERNAL
HIGH VOLTAGE
VIDEO

~

_ _-....,CRT
CATHODE

l

LAMP
CAPACITOR

J
TLIHI9178-S

FIGURE 5. Block Diagram of LM1203 Video Amplifier with Contrast and Black Level Control

3-28

o

~.

+12VO

'"

Q

r:
;::;:

IjI

c

CD
UI

n

:::::!.

....
O·
;:,

"a

11

40

:::l

g.
c:
(1)

B

VIDEOi'
IN

HV

10 }IF

751l

~~6 2~~10RS

'f'

~ -= -----=----

I\)

co

16K
OPT.

~----

, """ ~o.,.,
----S-

CAP

10

.I

51~"lt '-1,,11

1001l

-

= =

--v

TO CLAMP COMPARATOR (-) INPUT
OR
TO CLAMP COMPARATOR (+) INPUT

TL/H/917B-6

FIGURE 6. Simplified LM1203 Video Amplifier Section with Recommended External Components

m

£OC:~IN'

C")

o

N

.....
.....

:E

Circuit Description (Continued)
The "Drive" pin will allow the user to trim the 09 gain of
each amplifier to correct for differences in the CRT and high
voltage cathode driver gain stages. A small capacitor
(33 pF) at this pin will extend the high frequency gain of the
video amplifier by compensating for some of the internal
high frequency roll off. To use this capacitor and still provide
variable gain adjustment, the 51n and series 100n pot
should be used with the red and green drive pins. The 91 n
resistor used with the blue drive pin will set the system gain
to approximately 6.5 and allow adjustment of the red and
green gains to 6.5 plus or minus 25%. The video signal at
the collector of 09 is buffered and level shifted down by
010 and 011 to the base ofthe output emitter follower 012.
Between the emitter of 012 and the video output pin is a
40n resistor which was included to prevent spurious oscillations when driving capacitive loads. An external emitter resistor must be added between the video output pin and
ground. The value of this resistor should not be less than
390.0 or package power limitations may be exceeded when
worst case (high supply, max supply current, max temp) calculations are made. If negative going pulse slewing is a
problem because of high capacitive loads (> 10 pF), a more
efficient method of emitter pull down would be to connect a
suitable resistor to a negative supply voltage. This has the
effect of a current source pull down when the minus supply
voltage is -12V and the emitter current is approximately
10 rnA. The system gain will also increase slightly because
less signal will be lost across the internal 40n resistor. Precautions must be taken to prevent the video output pin from

going below ground because IC substrate currents may
cause erratic operation. The collector currents from the video output transistors are returned to the power supply at
Vee 2 pin 23. When making power dissipation calculations
note that the data sheet specifies only the Vee 1 supply
current at 12V. The IC power dissipation contribution of VCC
2 is dependent upon the video output emitter pull down
load.
In normal operation the minimum black level voltage that
can be set at the video output pin is approximately 2V when
at maximum contrast. In applications that require a lower
black level voltage a resistor (approximately 16 k.o) can be
added from pin 11 to ground. This has the effect of raising
the dc voltage at the collector of 04 which will extend the
range of the black level clamp by allowing 05 to remain
active. In applications that require video amplifier shut down
because of fault conditions detected by monitor protection
circuits, pin 11 and the wiper arms of the contrast and
brightness controls can be grounded without harming the
IC. This assumes some series resistance between the top
of the control pots and Vce.
Figure 7 shows the internal construction of the pin 11 2.4V
reference circuit which is used to provide temperature and
supply voltage tracking compensation for the video amplifier
inputs. The value of the external DC biasing resistors should
not be larger than 10 kn because minor differences in input
bias currents to the individual video amplifiers may cause
offsets in gain.

.------------------------------

TO VIDEO INPUT
10K

,,:V~~~~~~~~--_1~----_,
R21
R28
12K
R29
8K

,,'4K3
,
, Z3

10K

.I

TLlH/917B-7

FIGURE 7. LM1203 Video Input Voltage Reference and Contrast Control Circuits

3-30

Circuit Description

(Continued)
the 11 850 p.A current to ground. When pin 14 is low ( < 1.3V)
the 021 switch is off and the 11 850 p.A current source is
mirrored or "turned around" by reference diode D5 and 026
to provide a 850 p.A current source for the clamp comparator(s). The inputs to the comparator are similar to the clamp
gate input except that an NPN emitter coupled pair is used
to control the current which will charge or discharge the
clamp capacitors at pins 5, 8, or 10. PNP transistors are
used at the inputs because they offer a number of advantages over NPNs. PNPs will operate with base voltages at or
near ground and will usually have a greater reverse emitter
base breakdown voltage (BVebo). Because the differential
input voltage to the clamp comparator during the video scan
period could be greater than the BVebo of NPN transistors a
resistor (R34) with a value one half that of R33 or R35 is
connected between the bases of 023 and 027. This resistor will limit the maximum differential input to 024, 25 to
approximately 350 mY. The clamp comparator common
mode range is from ground to approximately 9V and the
maximum differential input voltage is Vee and ground.

Figure 7 also shows how the contrast control circuit is configured. Resistors R23, 24, diodes D3, 4 and transistor 013
are used to establish a low impedance zero TC half supply
voltage reference at the base of 014. The differential amplifier formed by 015, 16 and feedback transistor 017 along
with resistors R27, 28 establish a diferential base voltage
for 03 and 04 in Figure 6. When externally adding or subtracting current from the collector of 016, a new differential
voltage is generated that reflects the change in the ratio of
currents in 015 and 016. To provide voltage control of the
016 current, resistor R29 is added between the 016 collector and pin 12. A capacitor should be added from pin 12 to
ground to prevent noise from the contrast control pot from
entering the IC.
Figure 8 is a simplified schematic of the clamp gate and
clamp comparator sections of the LM1203. The clamp gate
circuit consists of a PNP input buffer transistor (018), a PNP
emitter coupled pair referenced on one side to 2.1V (019,
20) and an output switch (021). When the clamp gate input
at pin 14 is high (> 1.5V) the 021 switch is on and shunts

CLAMP

CAP~

CLAMP
GATE
IN

Lf-_________-+___

OTHER
COMPARATORS

~TO

TUH/917B-B

FIGURE 8. Simplified Schematic of LM1203 Clamp Gate and Clamp Comparator Circuits

3-31

~ r-------------------------------------------------------------------------------~

o

N
.,...

:::E
...I

Additional Applications of the LM 1203
Figure 9 shows how the LM1203 can be set up as a video
buffer which could be used in low cost video switcher applications. Pin 14 is tied high to turn off the clamp comparators. The comparator input pins should be grounded as
shown. Sync tip (black level if sync is not included) clamping
is provided by diodes at the amplifier inputs. Note that the
clamp cap pins are tied to the Pin 11 2.4V reference. This
was done, along with the choice of 2000 for the drive pin
resistor, to establish an optimum DC output voltage. The

contrast control (Pin 12) will provide the necessary gain or
attenuation required for channel balancing. Changing the
contrast control setting will cause minor DC shifts at the
amplifier output which will not be objectionable as the output is AC coupled to the load. The dual NPN/PNP emitter
follower will provide a low impedance output drive to the AC
coupled 750 output impedance setting resistor. The dual
500 I£F capacitors will set the low frequency response to
approximately 4 Hz.
+12V

0.1

V

~

~

1 ItF

7~

01

28
200n.
2

27

3

26

4

25

5

24

6

23

7

22

B

21

+12V

II'F

7~
1 ItF

~1

20
03

10

19

11

18

12

17

13

16

14

15

04

~

V'

I'F

TUH19178-9

FIGURE 9. RGB Video Buffer with Diode Sync Tip Clamps and 750 Cable Driver

3-32

ri:
.....

Additional Applications of the lM 1203 (Continued)
When diode D4 at Pin 11 is switched to ground the input
video signals will be DC shifted down and clamped at a
voltage near ground (approximately 250 mV). This will disable the video amplifiers and force the output DC level low.
The DC outputs from other similarly configured LM1203s
could overide this lower DC level and provide the output
Signals to the 75n cable drivers. In this case any additional
LM1203s would share the same 390n output resistor. The
maximum DC plus peak white output voltage should not be
allowed to exceed 7V because the "off" amplifier output
stage could suffer internal zener damage. See Figure 3 and
text for a description of the internal configuration of the video amplifier.

N

Figure 10 shows the configuration for a three channel high
frequency amplifier with non gated DC feedback. Pin 14 is
tied low to turn on the clamp comparators (feedback amplifiers). The inverting inputs (Pins 17, 21, 26) are connected to
the amplifier outputs from a low pass filter. Additional low
frequency filtering is provided by the clamp caps. The drive
resistors can be made variable or fixed at values between 0
and 300n. Maximum output swings are achieved when the
DC output is set to approximately 4V. The high frequency
response will be dependent upon external peaking at the
drive pins.

+12V
0.1

V-

28
0-300.(1

~

~

'i

~

10K

~

2

27

3

26

4

25

5

24

6

23

7

22

8

21

0-300.(1

10K

,~

20
10

19

11

18

V-

12

17

GAIN
ADJUST

13

16

14

15

lj.£F'

DC OUTPUT
ADJUST

TL/H/9178-10

FIGURE 10. Three Channel High Frequency Amplifier with Non-gated DC Feedback (Non-video Applications)

3-33

Q

Co)

~ Semiconductor
NaHonal

CorporaHon

LM 1391 Phase-Locked Loop
General Description
• Output transistor with low saturation and high voltage
swing
• APe of the oscillator with a synchronizing signal
• De controlled output duty cycle
• ± 300 Hz typical pull-in
• Linear balanced phase detector
• Low thermal frequency drift
• Small static phase error
• Adjustable De loop gain

The LM1391 integrated circuit has been designed primarily
for use in the horizontal section of TV receivers, but may
find use in other low frequency signal processing applications. It includes a stable veo, linear pulse phase detector,
and variable duty cycle output driver.

Features
• Internal active regulator for improved supply rejection
• Uncommitted collector of output transistor

Schematic Diagram
PRE·ORIVER

OSCILLATOR

OSCILLATOR
TIMING

REGULATOR
REGULATOR
VOLTAGE

.

,.,

.,.

Ii

PHASE DETECTOR

.1<

'"

••

'6

Uk

5

PHASE
DETECTOR
DUlfUT

4'}

SAWTOOTH

INPUT

OUTPlIT

.3
RZ
Uk

.3
1.5.

••

u.

.7

'ZG

470

1.5.

.,

.13

'40

.21
86'

SYNC

INPUT

TL/H17889-1

(') Pin 4 Base of 016 (LM1391) for use with (+) flyback pulse

3-34

.-:s::

...

Absolute Maximum Ratings

Output Voltage
Output Current
Sync Input Voltage (Pin 3)

Electrical Characteristics TA =

5.0Vp-p

Flyback Input Voltage (Pin 4)
Power Dissipation (Package Limitation)
Plastic Package (Note 1)

1000 mW

Operating Temperature Range (Ambient)
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Lead Temperature (Soldering, 10 sec.)
260'C

40Voc
3OmAoc
5.0Vp-p

25'C (see test circuit, all switches in pOSition 1)

Parameter

Conditions

Regulated Voltage (Pin 6)

16 = 22mAoc

Min

Typ

Max

8.0

8.6

9.2

Supply Current (Pin 6)

Units
Voc

20

Collector-Emitter Saturation Voltage
of Output Transistor (Pin 1)

IC1 = 20mA

mAoc

0.30

Pin 4 Voltage

0.40

Voc

2.0

Voc

Oscillator Pull-in Range

AdjustRH

±300

Hz

Oscillator Hold-in Range

AdjustRH

±900

Hz

0.5

p.s

±3.0

HzlVoc

Static Phase Error

~f

Free-running Frequency Supply
Dependance

S1 in pOSition 2

Phase Detector Leakage (Pin 5)

All switches in position 2

= 300Hz

±1.0

p.A

Sync Input Voltage (Pin 3)

2.0

5.0

Vp-p

Sawtooth Input Voltage (Pin 4)

1.0

3.0

Vp-p

500

Maximum Oscillator Frequency

kHz

Note 1: For operation in ambient temperatures above 25°C. the device must be derated based on a 150°C maximum junction temperature and a thermal resistance
of 12C1'C/W junclion to ambient.

Typical Performance Characteristics
Frequency Drift vs Warm-Up
Time

g

..

~
t;

REFERENCE FREnUENCY
'0'" 15.150 Hz

10

-20

:::

-30

150
%

':i

~

0
-10

~

:;l

l -I -

I\,

-40

-- -

100

15

30

45

REFERENCE FREOUENCY

'0

=

6.5 I- ~oE:~~E7~~~:REQUENCY_ I-

15.150 Hz

]

50

<:
~

5 -500

a

'" -100
"~ -150

:-

~

.l:~a

~

15

TIME hi

90 105 120

x

106 - -200 ppm!- C

fs t--

:.:~~ :~2~OC~~~~~~~~= ~ ~

-200
60

-

6.0

-50
0

7.0

- r-- -

t;

-

Output Duty Cycle vs VM
Voltage

Frequency vs Temperature

30
20

...

Co)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Current
4OmAoc

0

10

20

30

40

50

60

70

AM8IENT TEMPERATURE ( CI

80

"

:-

5.5
5.0

k'"

4.5

,/

4.0

i"'"

3.5

V'

3.0
2.5

0

10 20 30 40 50 80 70 80 90
PIN 1 OUTPUT OUTY CYCLE (%1
TL/H/7889-3

3-35

CD

~

~
~

::::E
.....

r-----------------------------------------------------------------------------------------------,
Application Information
The following equations may be considered when using the
LM1391 in a particular application.

DC Loop Gain p./3 "" 3.2 x 10- 5 Rofo Hz/rad
Noise Bandwidth

R201 .,; R301 = Vee - 8.6
0.02
.0
1
fo "" 0.6 RoCo Hz 1.5k

s:

Ro

< 51k

Damping Factor
'lT

R204"" 10 Ro

Rx2

K "" --Ccp./3
2 Ry

1
C203 = C204 ~ 600fo(Hz)F

Test Circuit

Vee
30V

1k

2k

lk

&800pF

12k

02
S2
12JA PULSE}
{ +5DV FOR
LMl391 --...

TL/HI7BB9-4

Connection Diagram
Dual-In-Une Package
DUTY CYCLE
CONTROL

OSCILLATOR
TIMING

OUTPUT

GNO

REGULATOR
VOLTAGE

SYNC
INPUT

Top View
Order Number LM1391N
See NS Package Number NOSE
3-36

PHASE
DETECTOR
OUTPUT

SAWTOOTH
INPUT

TL/HI7BB9-2

Typical Applications
Vce

24V TYP

RIDI
620
IW

RI06
2.7k
RI07
2.4k

'::"

RI04
120k

RIOR
ISOk

RIIO
1.2k
1I2W

LM1J91

TO YOKE
R111

l.9k
12", Fl YBACK PULSE
+40V FOR LM1J91

-20V
NEG
SYNC
TUH/7889-5

FIGURE 1. TV Horizontal Processor
VCC
24VTYP

R201

R206
2.7k

R204

R20l
lk

-

R207
2.4k

FRED
TRIM
Co

Rv

'::"

~

R202
I.Sk

LM1J91

l Vp·p INPUT
SYNCHRONIZING SIGNAL
TL/H17889-6

FIGURE 2. General Purpose Phase-Lock Loop
(See Applications Information)

3-37

Typical Applications

(Continued)
Vee
24VTVP

FRED AOJ
Rl06
2Sk

R30S
2.Sk

RlOl

Rl02

1.7k

RlOJ
lk

Rl04
l.lk
Rl07
I.Sk

T

Cl01

PULSE·WIDTH
MODULATION
TL/HI7889-7

FIGURE 3. Variable Duty Cycle Oscillator
(See Applications Information)

3-38

NatiOnal

~ Semiconductor
Corporation

LM1823 Video IF Amplifier/PLL Detector System
General Description

Features

The LM1823 is a complete video IF signal processing system on a chip. It contains a 5-stage gain-controlled IF amplifier, a PLL synchronous amplitude detector, self-contained
gated AGC, and a switchable AFC detector. The increased
flexibility of the LM 1823 makes it suitable for a wide variety
of television applications where high quality video or sound
carrier recovery is required. These include home receiver
video IFs, cable and subscription TV decoders, and parallel
sound IF/intercarrier detector systems. Typical operating
frequencies are 38.9 MHz, 45.75 MHz, 58.75 MHz, and
61.25 MHz.

•
•
•
•
•
•
•
•
•
•
•
•

Low differential gain and phase
IF and detector pin compatible with LM1822
Common-base IF inputs for SAW filters
True synchronous video detector using PLL
Excellent stability at high system gains
Noise-averaged gated AGC system
Uncommitted AGC comparator input
Internal AGC gate generator
Superior small-signal detector linearity
AFC detector with adjustable output bias
9 MHz video bandwidth
Reverse tuner AGC output

Test Circuit Measure parameters at indicated test points
V28

10k

12V

30k

•

10k

V1o-.JV'~-+---.,

12V
50

.0

3

V3,V4o-..JVII\o-......JV'90.,..:.,'+----I
180
1/2W

SW1

2k 0.01~ VQ.'-'\;''VOkIM~::.j---,
O-'\/IIV----,

'"~T

H

lDk V23,V26

-+~..,..-----....I

''--I-''W.....

10k

V19,V2D

10k

V.O-Wlr-----......J

1m

"

12Y

60k

1°·22

"

30k

100

':"

VAGC

OV-1DV

4k

12V

Tl • son unbal to bal
Mini·Circuits Lab TM01-1T

Order Number LM1823N
See NS Package N28B

Ll - 9'12T} #22 wire
L2·4YzT
on 0/16" form with
L3 • 6%T

HF core. shielded

All caps in JLF unless noted

3-39

TUH/S222-1

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Supply Voltage, V2

Power Dissipation

AGC Gate Voltage, V14

O·Cto 70·C

Operating Temperature Range

±5V

Storage Temperature Range

10mA

PLL Filter Current, 118

125·C

Junction Temperature

60mA

Video Output Current, 116

2W
50· C/W

Thermal Resistance, 0JA

15V

IF Supply Current, Is

1 Vrms

Detector Input Signal, VDET

- 65·C to

+ 150·C
260·C

Lead Temp. (Soldering, 10 seconds)

5mA

DC Electrical Characteristics

PARAMETERS GUARANTEED BY ELECTRICAL TESTING

TA=25·C, Test Circuit, VIF=VDET=O, VPH=4V, VCOMP=4V, and all switches in position 0 (open) unless noted.
Parameter

Conditions

Min

Typ

Max

Units

12V Supply Current, 11 + 12

VAGc=6.7V. VCOMP=6V

35

60

80

mA

IF Regulator Voltage, V5

VAGc=6.7V, SW4 Position 1

5.8

6.4

7.0

V

IF Input Voltage, V7, V8

VAGc=2V, SW 2, 3, 4 Position 1

3.2

3.7

4.1

V

IF Decouple Offset, V6-V9

VAGC = 2V, SW 2, 3, 4 Position 1

0

±30

mV

IF Peaker Voltage (Max Gain), V3, V4

VAGc=2V, SW2, 3, 4 Position 1

2.3

3.0

3.6

V

IF Output Current, 11

VAGc=9V, SW 2, 3, 4 Position 1,
Measure V1, 11 = (12-V1)/50

3.1

5.5

7.8

mA

IF Peaker Voltage (Min Gain), V3, V4

VAGc=9V, SW 2, 3, 4 Position 1

5.5

6.2

V

Detector Input Voltage, V28

VAGC= 6.7V, SW 1,4 Position 1

4.3

4.9

5.5

Limiter Tank Voltage, V24, V25

VAGc=6.7V, SW 1, 4 Position 1

6.4

7.0

7.6

V

AFC Tank Voltage, V23, V26

VAGc=6.7V, SW 1, 4 Position 1

4.3

4.9

5.5

V

VCO Tank Voltage, V19, V20

VAGc=6.7V, SW 1, 4 Position 1

4.7

5.2

5.7

V

AGC Sync Threshold, V17

SW 1, 2 Position 1, Adjust VCOMP for 113 = 0

3.8

4.0

4.2

V

V

AGC Filter Leakage Current, 113

SW 1, 2, 4 Position 1

0

±5

p.A

AGC Filter Charge Current, 113

SW 1, 2 Position 1, VCOMP=3.5V

1.6

2.2

2.8

mA

AGC Filter Discharge Current, 113

SW 1, 2 Position 1, VCOMP=4.5V

-0.45

-0.70

-0.90

mA

RF AGC Leakage current, 111

VAGc=2V, All Switches Position 1,
Measure V11, 111 =(12-V11)/6000

0

20

".A

RF AGC Output Current, 111

VAGC = 10V, All Switches Position 1,
MeasureV11,111=(12-V11)/6000

3-40

1.5

1.8

mA

Detector AC Set-Up Procedure sw 1, 4 position 1, VAGC=OV
1. Apply vDET= 10 mVrms, 45.75 MHz CW at the detector input. Tune L1 for maximum AC signal at pin 25, measured with a 10x
FET probe or through a 1 pF capacitor to prevent loading of the limiter tank.
2. Increase VDET to 60 mVrms. Adjust L3 until the PLL locks, as indicated by a DC voltage at the video output pin 16.
3. With the detector locked, adjust L3 for 4.0V at pin 18.
4. Adjust VPH for maximum detector efficiency by monitoring pin 16 for a minimum DC voltage.
5. Adjust L2 for 3.0V at pin 27 (on sensitive slope of AFC curve).

AC Electrical Characteristics PARAMETERS GUARANTEED BY ELECTRICAL TESTING
TA = 25"C, Test Circuit, detector set-up as above, f = 45.75 MHz, VAGC = 6.7V, VCOMP = 4V, and all switches in position 0
(open) unless noted.
Min

Typ

IF Amplifier Gain, VOUT!vIF (Note 1)

VAGc=2V, sw 2,3,4 Position 1,
VIF=500 ".Vrms

25

35

VAGC for 15 dB Gain Reduction

SW 2,3,4 Position 1, vIF=2.8 mVrms,
Adjust VAGC for Same VOUT as Gain Test

4.2

4.6

5.0

V

VAGC for 45 dB Gain Reduction

SW 2,3,4 Position 1, VIF=89 mVrms,
Adjust VAGC for Same vOUT as Gain Test

5.1

5.5

6.1

V

Zero Carrier Level, V16

SW 1, 2, 4 Position 1, VDET=O

6.6

7.4

8.4

V

Detected Output Level, a V16

SW 1, 2, 4 Position 1, VDET=60 mlVrms,
Measure Change in V16 from Zero
Carrier Test

2

3

4.3

V

2

3

V

2.8

3.0

3.2

V

0.5

1.0

V

Parameter

Conditions

Overload Output Voltage, V16

SW 1, 2, 4 Position 1, VDET=600 mVrms

AFC Output Voltage (OFF), V27

SW 1, 2, 4 Position 1, VDET=O

AFC Minimum Output Voltage, V27

SW 1, 4 Position 1, VDET=60 mVrms,
46.75 MHz

AFC Maximum Output Voltage, V27

SW 1, 4 Position 1, vDET = 60 mVrms,
44.75 MHz

PLL Pull-In Range, af

9

10

Max

Units
dB

V

2
3
MHz
SW 1, 4 Position 1, VDET=60 mVrms,
Vary Frequency and Measure the
Difference between Lock Points
Note 1: The IF amplifier gain is specHied with the IF output connected to a 500 measurement system which results in a 250 loaded impedance. The gain in an
actual application will typically be 26 dB higher.

3-41

Design Parameters NOT TESTED OR GUARANTEED Typical Application Circuit
Parameter

Typ

Units

Maximum System Operating Frequency
IF Input Impedance (Differential Pin 7-8), 45 MHz
IF Output Impedance, 45 MHz
IF Gain Control Range
Detector Input Impedance, 45 MHz
Detector Output Bandwidth, - 3 dB
Detector Differential Gain (Note 2)
Detector Differential Phase (Note 2)
Detector Output Harmonic Levels below 3 Vp-p Video
veo Temperature Coefficient

70
60
10
55
2

MHz
0
kO
dB
kO
MHz
%
deg
dB
ppm/DC

9
3
1
-40
-150

Note: 2: Differential gain and phase measured with the limiter tank adjusted for minimum differential phase.

Typical Application

45.75 MHz (see Application Notes)

.IV
0.001

430

301<

•

_-+-o AFC
OUTPUT

r-.....

10k

IF INPUT

12V

60'
15k

O:~~~

...L

'1;;),
..,liF

2k

FX·l028

SW6

'::' 130 pF

lOOk

C>--AtI'IIIr-O -10V
2

" 16k
SW3

SW7

o
2

12V

7.5V
TUH17915-2

Order Number LM1880J
See NS Package Number J14A

Typical Performance Characteristics
Horizontal Free-Running
7

..
..

~

VCO Control Characteristic

I

6.5

)

g

V

a:c

N

;;:
w
to

6

5.5

>

5

0

I-

Z
0

...

...>z

4.5

(

4

14

14.5

10 r---+---+---+---+-~

o 1--=
-P-Io;;;:-1r---t---1

--t-t:":......~"'t::----1

W

-10

t---t--+-............

ffia:

-20

t----+---+---+--+---1

-30

1---+---+---+---+----1

:"

U.

I

3.5

20 r---+---+---+---+-~

::>

/

-J

a:

t;:

/

!:;
0

30 Frequency vs Temperature

15

...ro
15.5

16

16.5

17

~--~--~--~-~~

-25

HORIZONTAL FREQUENCY (kHz)

0

25

50

75

100

AMBIENT TEMPERATURE (OC)
TLlH17915-3

TL/H17915-4

3-48

Typical Application
Rgl
30k
Rf
(+)
3.9k
FL ~:e~.~ o--G--'V'''''--Q----i

1 FL YBACK
SAWTOOTH

BURST
GATE OUT

Rh
7.5k

HORIZ
SYNC
Ch
510 pF

(-:-1..J

BURST 13
GATE

COMPOSITE
SYNC 20 Vp·p

RU2
1.5k

Ry
lOOk

-=-

VERTICAL 12
OUT

L.----I~~F

VERTICAL
RAMP SWITCH

VERT RETRACE 11
TIMING

R.
16k
Rt
16k

Ro
2k

Ct
cloTO.05pF
O.1~IF-=

VERT 10
SYNC

0----1/45

R,
510

o-________

1I2w

---I~;O

V+

1----<)-JVV'I..-
=

u

~dI

;

¥

A;

;.

U

;!!

~
~

~

~! ~.

3-52

Ta
t-

it

5a

~#i

"

0

0

"

=

"

0

0

"

"'"

"

0

• "·

0

;!!!

0

"

0

~I.l'

\;;~

~~¢

g

•

~•~

~;;

~!

u

~~~

5" iii 1I

I").:t'

"
0

~

~~.

"
o

2;:

~
~~ U

!~

h

~~

~ P),.~

 10 kO input resistance
• < 10 mA power supply drain current
• Composite sync and vertical outputs
• Odd/even field output
• Burst gate/back porch output
• Resistor programmable horizontal scan rate (up to
64 kHz)
• Edge triggered vertical output
• Default triggered vertical output for non-standard video
signal (video games-home computers)

Connection Diagram
LM1881N

Vee

COMPOSITE
SYNC OUTPUT
COMPOSITE
VIDEO INPUT 0
VERTICAL
SYNC OUTPUT

8 t------OS-12V
2

7 t----::-=-::--o ODD/EVEN OUTPUT
RSET

3
4

5

1 - - - - - - - 0 BURST/BACK
OUTPUT

PORCH

COMPOSITE
VIDEO INPUT
COMPOSITE
SYNC OUTPUT
VERTICAL
SYNC OUTPUT
BURST OUTPUT
ODD/EVEN
OUTPUT
TUH/9150-1

Order Number LM1881M or LM1881N
See NS Package Number M08A or N08E

3-54

r!is:

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
13.2V
Input Voltage
3Vp-p
Output Sink Currents; Pins 1, 3, 5
5mA
Output Sink Current; Pin 7
2mA
Package Dissipation (Note 1)
1100 mW
Operating Temperature Range
O'C -70'C

Storage Temperature Range
-65'Cto +150'C
ESD Susceptibility (Note 2)
2kV
Soldering Information
260'C
Dual-In-Line Package (10 sec.)
Small Outline Package
Vapor Phase (60 sec.)
215'C
Infrared (15 sec.)
220'C
See AN-450 "Surface Mounting Methods and their Effect on
Product Reliability" for other methods of soldering surface
mount devices.

Electrical Characteristics
Vcc = 5V; Rset = 660 kn; TA = 25'C; Unless otherwise specified
Typ

Tested
Limit (Note 3)

Vee = 5V; Outputs at Logic 1

5.2

10

Vcc = 12V; Outputs at Logic 1

5.5

12

mAmax

1.5

1.3
1.6

Vmin
Vmax

70

55
65

mVmin
mVmax

11

6
16

,...Amin
,...Amax

Parameter
Supply Current

Conditions

DC Input Voltage

Pin2

Input Threshold Voltage

Note 5

Input Discharge Current

Pin 2; VIN = 2V

Input Clamp Charge Current

Pin 2; VIN = 1V

RSET Pin Reference Voltage

Pin 6; Note 6

Composite Sync. & Vertical
Outputs

lOUT = 40 ,...A; Logic 1
lOUT = 1.6 mA; Logic 1

Burst Gate & Odd/Even
Outputs

lOUT = 40 ,...A; Logic 1

Design
Limit (Note 4)

Units
(Limits)
mAmax

0.6

0.2

mAmin

1.22

1.10
1.35

Vmin
Vmax

4.5

4.0

Vmin

3.6

2.4

Vmin

4.5

4.0

Vmin
Vmax

Composite Sync. Output

lOUT = -1.6 mA; Logic 0; Pin 1

0.2

0.6

Vertical Sync. Output

lOUT = -1.6 mA; Logic 0; Pin 3

0.2

0.6

Vmax

Burst Gate Output

lOUT = -1.6 mA; Logic 0; Pin 5

0.2

0.6

Vmax

Odd/Even Output

lOUT = -1.6 mA; Logic 0; Pin 7

0.2

0.6

Vmax

230

190
300

,...smin
,...smax

2.5
4.7

,...smin
,...smax

Vertical Sync Width
Burst Gate Width

2.7 kn from Pin 5 to Vcc

Vertical Default Time

Note 7

4

32
,...smin
90
,...smax
Note 1: For operation In ambient temperatures above 25'C. the device must be derated based on a 150'C maximum junction temperature and a package thermal
resistance of 110' C/W, junction to ambient.
Note 2: ESD susceptibility test uses the "human body model, 100 pF discharged through a 1.5 kU resistor".
Note 3: These parameters are guaranteed and 100% production tested.
Note 4: Design Limits are guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels.
65

Note 5: Relative difference between the input clamp voltage and the minimum input voltage which produces a horizontal output pulse.

Note 6: Careful attention should be made to prevent parasitic capacitance coupling from any output pin (Pins
Note 7: Delay time between the start of vertical sync (at input) and the vertical output pulse.

3-55

I, 3,

5, and 7) to the RSET pin (Pin 6).

....
CO
CO
....

....
....
:l
co
co

Typical Performance Characteristics
Rset Value Selection
vs Composite Sync
1.0

Vertical Default
Sync Delay Time
vsRset

V

D.8

!

!

~

I;;

IQ

Q..I

o

COMPOSITE SYNC FREQUENCY

/

V

/

112

/

D.8

/

D.6

0.0

Burst/Black Level
Time vs Rset

1.0 Gate

/

112

~

~

~

0.0

m

~

o

VERTICAL DEfAULT SYNC
DELAY nME
(p.)

X fh (fh=15.734kHz)

Vertical Pulse
va Rset

10

BURSTI BLACK LEVEL
GATE nME
(1'.)

Supply Current vs
Voltage

Vertical Pulse
400 Width vs Temperature

1.0 Width

V

10 Supply

/
D.8
D.6

I

V

---r--

112
0.0

o

r-

-

10D
100

200

300

«Xl

VERTICAL PULSE WIDTH

500

o

20

~

TEMPERATURE(OC)

(1'.)

~

70

f

o
o

10

12

Vee
Tl/H/9150-2

3-56

Application Notes
The LM1881 is designed to strip the synchronization signals
from composite video sources that are in, or similar to, the
N.T.S.C. format. Input signals with positive polarity video (increaSing signal voltage signifies increasing scene brightness) from 0.5V (p-p) to 2V (p-p) can be accommodated.
The LM1881 operates from a single supply voltage between
5V DC and 12V DC. The only required external components
beside power supply and set current decoupling are the input coupling capaCitor and a single resistor that sets internal
current levels, allowing the LM1881 to be adjusted for
source Signals with line scan frequencies differing from
15.734 kHz. Four major sync Signals are available from the
IIC: compOSite sync including both horizontal and vertical
scan timing information; a vertical sync pulse; a burst gate
or back porch clamp pulse; and an odd/even output. The
odd/even output level identifies which video field of an interlaced video source is present at the input. The outputs from
the LM1881 can be used to gen-Iock video cameraIVTR
signals with graphics sources, provide identification of video
fields for memory storage, recover suppressed or contaminated sync signals, and provide timing references for the
extraction of coded or uncoded data on specific video scan
lines.
To better understand the LM1881 timing information and
the type of signals that are used, refer to Figure 2(a-e)
which shows a portion of the compOSite video signal from
the end of one field through the beginning of the next field.

from between 40 ns to as much as 200 ns due to this filter.
This much delay will not usually be significant but it does
contribute to the sync delay produced by any additional signal processing. Since the original video may also undergo
processing, the need for time delay correction will depend
on the total system, not just the sync stripper.
VERTICAL SYNC OUTPUT
A vertical sync output is derived by internally integrating the
composite sync waveform (Figure 3). Horizontal sync pulses
are not able to charge the integrating capaCitor sufficiently
because of their short duty cycle, but when the vertical retrace interval is reached, the broad serrated pulse charges
the capaCitor past a fixed threshold. Once the threshold is
reached, the next serration in the sync waveform triggers an
R-S flipflop and starts the vertical output pulse at Pin 3.
Simultaneously an internal oscillator begins clocking a
counter. When a count of eight is reached the vertical output pulse is terminated and the circuit resets. Both the time
required to reach the integrator threshold and the period of
the oscillator are programmed by an external resistor at Pin
6. For an N.T.S.C. signal with 32 P.s between serrations, a
680 kfl. resistor will ensure the vertical output pulse will start
coincident with the leading edge of the first vertical serration
(Figure 2c). If the resistor value gets too small it becomes
possible for the oscillator circuit to time out before the input
vertical sync period has ended. When this is the case, the
sequence will repeat and a double vertical output pulse will
appear. Therefore, the resistor value for a given horizontal
scan rate is chosen small enough to trigger the vertical output pulse on the first serration yet not so small as to give a
double pulse, rather than attempting to choose a value that
gives a specific output pulse width. If the incoming vertical
sync is not serrated, the integrating capaCitor is allowed to
charge to a second threshold which automatically initiates
the vertical output pulse sequence. In this instance, the start
of the vertical pulse as well as the pulse period will be dependent on the resistor value.

COMPOSITE SYNC OUTPUT

The composite sync output, Figure 2(b), is simply a reproduction of the signal waveform below the composite video
black level, with the video completely removed. This is obtained by clamping the video Signal sync tips to 1.5V DC at
Pin 2 and using a comparator threshold set just above this
voltage to strip the sync signal, which is then buffered out to
Pin 1. The threshold separation from the clamped sync tip is
nominally 70 mV which means that for the minimum input
level of 0.5V (p-p), the clipping level is close to the halfway
point on the sync pulse amplitude (shown by the dashed
line on Figure 2(a). This threshold separation is independent of the Signal amplitude, therefore, for a 2V (p-p) input
the Clipping level occurs at 11 % of the sync pulse amplitude. The charging current for the input coupling capaCitor is
0.8 mA, whereas the discharge current is only 11 p.A, typically. This allows relatively small capacitor values to be
used-O.1 p.F is generally recommended.
Normally the Signal source for the LM1881 is assumed to be
clean and relatively noise-free, but some sources may have
excessive video peaking, causing high frequency video and
chroma components to extend below the black level reference. Some video discs keep the chroma burst pulse present throughout the vertical blanking period so that the burst
actually appears on the sync tips for three line periods instead of at black level. A clean composite sync signal can
be generated from these sources by filtering the input signal. When the source impedance is low, typically 75fl., a
620fl. resistor in series with the source and a 510 pF capacitor to ground will form a low pass filter with a corner frequency of 500 kHz. This bandwidth is more than sufficient to
pass the sync pulse portion of the waveform; however, any
subcarrier content in the signal will be attenuated by almost
18 dB, effectively taking it below the comparator threshold.
Filtering will also help if the source is contaminated with
thermal noise. The output waveforms will become delayed

ODD/EVEN FIELD PULSE
An unusual feature of LM1881 is an output level from Pin 7
that identifies the video field present at the input to the
LM1881. This can be useful in frame memory storage applications or in extracting test Signals that occur only in alternate fields. For a composite video signal that is interlaced,
one of the two fields that make up each video frame or
picture must have a half horizontal scan line period at the
end of the vertical scan-i.e., at the bottom of the picture.
This is called the "odd field" or "field 1". The "even field"
or "field 2" has a complete horizontal scan line at the end of
the field. An odd field starts on the leading edge of the first
equalizing pulse, whereas the even field starts on the leading edge of the second equalizing pulse of the vertical retrace interval. Figure 2(a) shows the end of the even field
and the start of the odd field.

To detect the odd/even fields the LM1881 again integrates
the composite sync waveform (Figure 3). A capaCitor is
charged during the period between sync pulses and discharged when the sync pulse is present. The period between normal horizontal sync pulses is enough to allow the
capaCitor voltage to reach a threshold level of a comparator
that clears a flipflop which is also being clocked by the sync
waveform. When the vertical interval is reached, the shorter
integration time between equalizing pulses prevents this

3-57

~

co
co
:E
~

.------------------------------------------------------------------------------------------,
Application Notes (Continued)

....I

ST
__
ART
__
OF_F_IE_LD--.:l<,-OD_D.:,.)!+-___________ VERTICAL BLANKING INTERVAL ____________-1
EQUALIZING
PULSES

a

-+I

SERRATED
VERTICAL PULSE

-1- EQUALIZING --l
PULSES

I

PEAK

J{ WHITE

o
P--H~"'-I-p--_(CLIP

( BLACK
LEVEL

~J-~L.v.~JJ--llnr'r'rlnln

~IH-I

I

LEVEL

... 1---2-3-...J14--....5--S---7-8----9--10--l~21-'(SYNC

IT

..,.......,r--Ir--'r--In

h-l

-II-2.4J.1S

31.8J.1S

63.SJ.ls

TIPS

-II-4.7J.1'

.----~i~

~~==~----~i~
ODD FIELD
EVEN F1ELD

-II--

4J.1S typo
TL/H/9150-3

FIGURE 2. (a) Composite Vldeoj (b) Composite Syncj (c) Vertical Output Pulsej
(d) Odd/Even Field Indexj (e) Burst Gate/Back Porch Clamp

8

CONP~~ o--f.--ot[

VER~

SUPPLY
VOLTAGE

7

ODD/EVEN
FIELD
INDEX

5

BURST CATE/
BACK PORCH
CLAMP

0--+---1-1

'Components Optional.
See Text

TL/H/9150-4

FIGURE 3

3-58

Application Notes (Continued)
threshold from being reached and the Q output of the flipflop is toggled with each equalizing pulse. Since the half line
period at the end of the odd field will have the same effect
as an equalizing pulse period, the Q output will have a different polarity on successive fields. Thus by comparing the Q
polarity with the vertical output pulse, an odd/even field index is generated. Pin 7 remains low during the even field
and high during the odd field.

signal (VIRS) and line 21 is reserved for closed caption data
for the hearing impaired. The remaining lines are used in a
number of ways. Lines 17 and 18 are frequently used during
studio processing to add and delete vertical interval test
signals (VITS) while lines 14 through 18 and line 20 can be
used for Videotex/Teletext data. Several institutions are
proposing to transmit financial data on line 17 and cable
systems use the available lines in the vertical interval to
send decoding data for descrambler terminals.
Since the vertical output pulse from the LM1881 coincides
with the leading edge of the first vertical serration, sixteen
positive or negative transitions later will be the start of line
14 in either field. At this point simple counters can be used
to select the desired line(s) for insertion or deletion of data.

BURSTIBACKPORCH OUTPUT PULSE

In a composite video Signal, the chroma burst is located on
the backporch of the horizontal blanking period. This period,
approximately 4.8 ,...S long, is also the black level reference
for the subsequent video scan line. The LM1881 generates
a pulse at Pin 5 that can be used either to retrieve the chroma burst from the composite video signal (thus providing a
subcarrier synchronizing Signal) or as a clamp for the DC
restoration of the video waveform. This output is obtained
Simply by charging an internal capacitor starting on the trailing edge of the horizontal sync pulses. Simultaneously the
output of Pin 5 is pulled low and held until the capacitor
charge circuit times out-4 ,...s later. A shorter output burst
gate pulse can be derived by differentiating the burst output
using a series C-R network. This may be necessary in applications which require high horizontal scan rates in combination with normal (60-120 Hz) vertical scan rates.

VIDEO LINE SELECTOR
The circuit in Figure 4 puts out a single video line according
to the binary coded information applied to line select bits
bO-b7. A line is selected by adding two to the desired line
number, converting to a binary equivalent and applying the
result to the line select inputs. The falling edge of the
LM1881's vertical pulse is used to load the appropriate
number into the counters (MM74CI93N) and to set a start
count latch using two NAND gates. Composite sync transitions are counted using the borrow out of the desired number of counters. The final borrow out pulse is used to turn on
the analog switch (CD4066BC) during the desired line. The
falling edge of this signal also resets the start count latch,
thereby terminating the counting.
The circuit, as shown, will provide a single line output for
each field in an interlaced video system (television) or a
single line output in each frame for a non-interlaced video
system (computer monitor). When a particular line in only
one field of an interlaced video Signal is desired, the odd/
even field index output must be used instead of the vertical
output pulse (invert the field index output to select the odd
field). A single counter is needed for selecting lines 3 to 14;
two counters are needed for selecting lines 15 to 253; and
three counters will work for up to 2046 lines. An output buffer is required to drive low impedance loads.

APPLICATIONS

Apart from extracting a composite sync Signal free of video
information, the LM1881 outputs allow a number of interesting applications to be developed. As mentioned above, the
burst gate/backporch clamp pulse allows DC restoration of
the original video waveform for display or remodulation on
an R.F. carrier, and retrieval of the color burst for color synchronization and decoding into R.G.B. components. For
frame memory storage applications, the odd/even field level allows identification of the appropriate field ensuring the
correct read or write sequence. The vertical pulse output is
particularly useful since it begins at a precise time-the rising edge of the first vertical serration in the sync waveform.
This means that individual lines within the vertical blanking
period (or anywhere in the active scan line period) can easily be extracted by counting the required number of transitions in the composite sync waveform following the start of
the vertical output pulse.
The vertical blanking interval is proving popular as a means
to transmit data which will not appear on a normal T.V. receiver screen. Data can be inserted beginning with line 10
(the first horizontal scan line on which the color burst appears) through to line 21. Usually lines 10 through 13 are
not used which leaves lines 14 through 21 for inserting signals, which may be different from field to field. In the U.S.,
line 19 is normally reserved for a vertical interval reference

MULTIPLE CONTIGUOUS VIDEO LINE
SELECTOR WITH BLACK LEVEL RESTORATION

The circuit in Figure 5 will select a number of adjoining lines
starting with the line selected as in the previous example.
Additional counters can be added as described previously
for either higher starting line numbers or an increased number of contiguous output lines. The back porch pulse output
of the LM1881 is used to gate the video input's black level
through a low pass filter (10 kn, 10 ,...F) providing black level
restoration at the video output when the output selected
line(s) is not being gated through.

3-59

r3:
......
co
co
......

~

~
::E
~

r-----------------------------------------------------------------------------------------------,
Typical Applications
+~o-._----------~--._----~~------------~~----_,

....I

6BOk4

2k4

6204

O.II'F

~r+----------------~r---------------r~~~-------~
VIDEO

,-li-li-l..........................L..

SELECTED VIDEO

INPUT

LINE OUT

TL/H/9150-5

FIGURE 4. Video Line Selector

..

+5Vo-._---1~----.__.------~------------~~----~--------------------

68Dkll

2kll

I

I
I

I
I

62DIl

I
I

I
I
I

I
I

~~-------+-----------------~~--+----~
VIDEO
INPUT

.. -------------.
I

0.1

I
I
I

2kll

+5V

lDkll

0.001 !,F

L.....j----~

D.,!'F.b

......- - - - - '

D.l!'F:

I

I
I
I

I

:._----------_
-=
.

SELECTED VIDEO
L1NE(S) OUT

TUH/9150-6

FIGURE 5. Multiple Contiguous Video Line Selector With Black Level Restoration

3·60

r

is:
......

~ Semiconductor
NatiOnal

co
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Corporation

LM 1886 TV Video Matrix D to A
General Description

Features

The LM1BB6 is a TV video matrix D to A converter which
encodes luminance and color difference signals from 3-bit
red. green and blue inputs. The luminance output is encoded from the NTSC equation Y = 0.3R + 0.S9G + 0.11 B
and the R-Y and B-Y outputs are weighted to prevent overmodulation. A built-in R-Y and burst gate polarity switch allow European PAL compatible signals to be encoded. All
output levels including an RF 0 Carrier Bias Voltage have
been referenced to SV for direct connection to the LM1889
TV video modulator. When used in combination with the
LM1889 and a suitable sync generator. 3-bit. R. G and B
information may be encoded to both composite video and
RF channel carrier.

•
•
•
•
•
•
•
•

Complete digital to RF coding with LM1889
1-pin PALINTSC mode select
True NTSC matrix
8 levels of grey scale
Allows wide range of colorimetry
Low power TTL inputs
Wideband luminance output
Weighted R-Y. B-Y outputs

Connection Diagram
11

RED
INPUTS

r{

GNO

12

MSB

iiIANR INPUT

13

SYNC INPUT

7

LSB

"

GREEN
INPUTS

15

MSB

[

Y OUTPUT

16

12V SUPPLY

LSB.

BLUE
INPUTS

o CARRIER
REFERENCE

B·Y OUTPUT

"
18

R·Y OUTPUT

MSB

H/21NPUT
BURST GATE
INPUT

5V SUPPLY

Top View

FIGURE 1
Order Number LM1886N
See NS Package Number N20A

3-61

TLlH17916-1

&I

CD

CO
CO

....

::::i

...I

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
Pin 5
15V
Pin 20
6V
Input Voltage (Pins 1, 8, 9,11-19)
-0.5V, +12V

Electrical Characteristics TA =
Parameter

Pin 2 Voltage Relative to Pin 20
Output Current

0.8V
5mA

Power Dissipation, TA = 25'C (Note 1)
Storage Temperature Range

1900mW
-55'C to + 150'C

Operating Temperature Range
Lead Temperature (Soldering, 10 sec.)

O'Cto +70'C
260'

25'C, (Figure 2, Note 2)
Min

Typ

Max

Units

BLANK = 0.8V

7

11

16

mA

12V Supply Current (Pin 5)

BLANK = 0.8V

9

13

17

mA

Logic "1" Input Current
(Pins 1,2,8,9,11-19)

Input Voltage = 5.0V

0

10

/LA

Logic "0" Input Current
(Pins 1, 2, 8, 9,11-19)

Input Voltage = 0.3V

-0.01

-0.18

mA

Output Offsets

R, G, B, = 0.8V
0
0
0

±50
±50
±50

mV
mV
mV

5V Supply Current (Pin 20)

Conditions

l!Ny
AVR_Y
AVB_Y
R-Y Full Scale, (AVR-Y)FS

R = 2V; G, B = 0.8V

1.0

1.23

1.4

V

0.7

0.87

1.0

V

-0.85
-0.45

-1.03
-0.58

-1.2
-0.7

V
V

1.6

1.75
0
0

1.9
±100
±75

V
mV
mV

2.0

2.2

2.5

V

0

±50

mV

-0.67

-0.77

-0.87

V

0.26

0.35

0.46

V

-0.2
-0.2

-0.25
-0.25

-0.32
-0.32

V
V

-0.9

-1.0

-1.1

±1

±6

B-Y Full Scale, (AVB-Y)FS

B = 2V;R,G = 0.8V

Green Full Scale
AVR_Y
AVB_Y

G = 2V; R, B = 0.8V

Y Full Scale
(AVY)FS
AVR_Y
AVB_Y

R,G,B = 2V

o Carrier Reference, AVo
Blanking Level, AVy

BLANK = 0.8V

Sync Level, AVy

BLANK, SYNC = 0.8V

NTSC Burst, AVB_Y

BLANK, BURST GATE - 0.8V

PAL Burst
AVR_Y
AVB_Y

SW in PAL Position;
BLANK, BURST GATE,
H/2 = 0.8V

PAL Inversion Ratio
(AVR-Y)PAL/(AVR-Y)FS

R= 2V; G, B, H/2 = 0.8V
SW to PAL Position

Y Linearity Error

Figure 2b Input Connection

Y Switching Times
Rise Time, tR
FaliTime,tF
Settling Time ± 1 LSB

15 kHz Square Wave Switching
R, G, B in Parallel

35
30
50

Note 1: Above TA = 2S'C, derate based on TJ(MAX) = ISO'C and 6JA = 6S'C/W.
Note 2: Unless otherwise noted, BLANK, SYNC, BURST GATE 2V and SW is in NTSC position. All outputs are referenced to the
2a.

3-62

%FS
ns
ns
ns

+ SV supply as shown in Figure

r-

3:
....
co

Typical Input and Output Waveforms
BLANK
INPUT
(PIN 9)
SYNC
INPUT
(PIN 8)
BURST GATE
INPUT
(PIN I)
H/21NPUT
PAL ONLY
(PIN 2)

RED INPUTS
(PINS II, 12, 13)

GREEN INPUTS
(PINS 14, 15,16)

BLUE INPUTS
(PINS 17, IB, 19)

2.0VMIN

------------....,U
U

O.BV MAX - - - - - - - - - - - - -

co

LS

0'1

2.0V MIN - - - - - - - - - - - - -...
O.BV MAX
2.0V MIN

--------------!

------------+-n r--------------,

O.BV MAX

-------------+t

5.0V
2.0VMAX
MIN

--------------i
++-+-------------......

O.BV MAX - - - - - - - - - - - - - -...

O.BV MAX
2.0V MIN
O.BV MAX
2.0V MIN

--+---+---'
--+--/--r---!---...

--+--!-_..I
1.75V --+--+---+--

O.BV MAX

1.0lV ---+---I~-"
'::'Vy OUTPUT
(PIN 6)

O.71V

--+--1--+--1---

O.S7V

---+--f---

0.35V
O.5BV

--+----t--+----t-----+---

.:. VB-V OUTPUT
(PIN 4)

1.2lV--

'::'VR-Y OUTPUT
(PIN l)
020V - - + - - - - f - 1.0JV--+---

~

I

VR.Y OUTPUT
PAL MODE

O.25V
O.20V

===l~=::t:==:j:::==1====~=====t::==iI;;;;;;;;;;;;;;;_---

(PIN l)

O.20V
O.25V

=====1~=r:::::~--­

I.OJV----1.2lV - - - - - - - - - - - - - - - - TL/H17916-4

3-63

CD

CO
CO

..:E

Test Circuits

....I

11 L

R

10

v{

-

12
13

11
LSB

L

12

13

MSB

M

...,!!L

G

~

~r-!!

__________~____~~O.I(F ~

16

LM18B6
M

.....!.?L

~
19

M

.2!!.

5Vo-___..........:2;.:0:.t

TL/H17916-3

TL/H17916-2

FIGURE 2b. a-level Grey Scale
Input Connection

FIGURE 2a. 6-Color Input Connection

Application Notes (Refer to Figure 3)

TABLE I. Input Code Examples for Common Colors

SYNC, BLANK, and BURST GATE may be obtained from a
sync generator IC. For PAL operation, the H/2 square wave
may be obtained by a + 2 from horizontal sync.

InpulCode
Red
Color

All inputs are low-power TTL compatible. Because of the
very low typical input currents, the color inputs may be paralleled in various combinations. For simple color requirements, the Figure 28 input connection may be used to produce the 6 primary and complementary colors listed in Table I, along with black and white. To add complex colors
such as those at the bottom of Table I, all 9 input bits may
be required separately. When choosing input codes for other colors, always check the new color against both light and
dark backgrounds.
All outputs are referenced to the + 5V supply for direct connection to the LM1889. The resistor on the luminance output pin 6 is used to sum the chroma subcarrier from the
LM1889 and must be wired as tightly as possible to preserve the video bandwidth. For the addition of sound or a
second RF channel, refer to the LM1889 data sheet.

Black
Dark Grey
Light Grey
White

[
~ ~[
as
~

III

E

;:
lL

E c

o

(J

3-64

CD

E

Green

M

L

M

0 0
0 1
1 0
1 1

0
0
1
1

0
0
1
1

1 1
0 0
0 0

0
1
0

Blue

L

M

L

0
1
0
1

0
0
1
1

0 0
0 1
1 0
1 1

0
0
1
1

0
1
0

0
1
0

0
0
1

0
0
1

Red
Green
Blue

1
0
0

Cyan
Magenta
Yellow

0 0
1 1
1 1

0
1
1

1 1
0 0
1 1

1
0
1

1 1 1
1 1 1
0 0 0

Brown
Orange
Flesh Tone
Pink
Sky Blue

0
1

1
1

1
1

0
1

1

1

1

1
1

1
0

1

1
1

1

1

1
0
0
0
1

0 0
0 0
1 0
1 1
1 1

1
0
1
1
0

0
0
1

0
0

1
0

1

· I Application
TYPlca

COMPOSITE

...... ----+~~

~(

12V

(
~(
5V' 5%

ZO

+

U!JLl0"F*,

lk

TL/H17916-5

FIGURE 3

3-65

Circuit Description (Refer to Figure 4)
The 3-bit red, green, and blue inputs go to identical 3-bit
current-mode digital-to-analog converters (DACs). Each
DAC consists of three binary-weighted current sources controlled by diff-amp current switches. The DAC output currents are arbitrarily given a weighting factor of 0.59, which is
the green coefficient in the luminance equation. Portions of
the red and blue currents are split off, so that the remaining
currents combined with the green current form the luminance current Iv = 0.3 IR + 0.59 IG + 0.11 lB. Iv develops
the luminance voltage Vv across Ro in a summing amplifier
referenced to the + 5V supply. A current switch operated by
pin 8 adds (-) sync pulses to the V output at pin 6.
The portions of red and blue currents previously split off
flow through resistors Ro/0.29 and Ro/0.48, which are
weighted to form the red and blue voltages respectively.
Since the opposite ends of the 2 resistors are connected to
Vv, the red and blue voltages across the resistors subtract
from Vv to develop the color difference voltages VV-R and
VV-B' VV-B is coupled through a X.56 gain, 5V-referenced
inverting amplifier to the B-V output at pin 4. VV-R feeds
parallel inverting and non-inverting unity gain amplifiers
which allow either polarity to be coupled to the R-V output
pin 3. Switching between the 2 amplifiers is controlled by a
current switch activated by the H/2 pin 2. A (-) burst gate
pulse on pin 1 controls current switcl:1es which add the burst
pulse components to the B-V and R-V outputs.

The requirements for PAL and NTSC encoding differ in the
areas of burst gate operation and R-V polarity, both of which
are controlled via pin 2 as follows:
PAL, pin 2 fed by a half-line frequency TTL square wave-in
this mode a PNP switch between pin 2 and + 5V is held off
continuously, which results in equal burst pulse components
on the B-V and R-V outputs. In addition, the H/2 square
wave causes the R-V output polarity to reverse every line.
(When fed to the LM1889 chroma modulator this causes the
phase of the R-V subcarrier to change 180" as required in
PAL.)
NTSC, pin 2 tied through an external resistor to + 12V-this
turns on the PNP switch continuously, which eliminates the
burst pulse on the R-V output and increases the amplitude
of the B-V pulse. Since pin 2 is being held high, the R-V
output is locked in the positive polarity.
Blanking is activated by a low on pin 9, which de-biases the
left side of the DAC diff-amps, so that IR = IG = IB = 0
independent of the input states. When blanked, the V, B-V
and R-V outputs all go to + 5V. An additional amplifier produces a 0 carrier reference voltage at pin 7 which is 25%
above the peak white voltage on the V output, relative to
+5V.

3-66

SYNC

REF

•

m

5
12V

.Q

C

:;C.
D)

20

+--<>5V

iD
~

enn
:::r

VR.V

1k
~

~

3
- R-Y

5V

Co>

CD

3
~

n

~2~4V

~

':"

~,
':"

I I VB~Y

~~ B-Y

2Jr.85

5V

10
1
':"

':"

~

':"

~
TL/H/7916-6

FIGURE 4. LM1886 Equivalent Schematic

m

988~W'

en ,----------------------------------------------------------------------------,
~
~

.....

:E
...I

NatiOnal

~ Semiconductor

PRELIMINARY

Corporation

LM 1889 TV Video Modulator
General Description

Features

The LM1889 is designed to interface audio, color difference,
and luminance signals to the antenna terminals of a TV receiver. It consists of a sound subcarrier oscillator, chroma
subcarrier oscillator, quadrature chroma modulators, and
RF oscillators and modulators for two low-VHF channels.
The LM1889 allows video information from VTR's, games,
test eqUipment, or similar sources to be displayed on black
and white or color TV receivers. When used with the
MM57100 and MM53104, a complete TV game is formed.

•
•
•
•
•
•

Block Diagram

DC Test Circuit

dc channel switching
12V to 18V supply operation
Excellent oscillator stability
Low intermodulation products
5 Vp-p chroma reference Signal
May be used to encode composite video

Dual-In-Line Package
CH~~~~

_'+__---.

R.Y Z
INPUT

sw.

IB CHROMA
LAG

17 CHROMA OSC
OUTPUT

CHROMA 3
BIAS

16 CHROMA

SUPPLY

1.5V

..

OW, 1

,

0

eH,
11

13 CHROMA

1

SUBCARRIER

6

CHB
TANK

eH.
+

1

V,

n

+

sw.
1M

1k

1D 1k

-

IS
15V

~D.I/.!F

TLlH/7917-2

CHA
OUTPUT

TLlHI7917-1

Order Number LM1889N
See NS Package Number N18A

3-68

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage V14, V16 max

-55'Cto + 150'C
1OmAoc

19Voc
1BOO mW

Power Dissipation Package (Note 1)
Operating Temperature Range

Storage Temperature Range
Chroma Osc Current 117 max
(V16-V15) max

± 5Voc

(V14-V10) max

7V

(V14-V11)max

O'Cto +70'C

7V

Lead Temperature (Soldering, 10 sec.)

260'C

DC Electrical Characteristics (dc Test Circuit, All SW Normally Pos. 1, VA = 15V, VB = Vc = 12V)
Symbol

Parameter

Is

Supply Current

al15

Sound Oscillator, Current
Change

Conditions

Change VA from 12.5 to
17.5V

Min

Typ

Max

Units

20

35

45

mA

0.3

0.6

0.9

mA

V17

Chroma Oscillator Balance

9.5

11.0

12.5

V

V13

Chroma Modulator Balance

7.0

7.4

7.B

V

aV13

R· Y Modulator Output Level

SW 3, Pos. 2, Change SW 1
from Pos. 1 to Pos. 2

0.6

0.9

1.2

V

aV13

B-Y Modulator Output Level

SW 3, Pos. 2, Change SW 2
from Pos. 1 to Pos. 2

0.6

0.9

1.2

V

aV13/aV3

Chroma Modulator
Conversion Ratio

SW 3, Pos. 2, Change SW 0
from Pos. 1 to Pos. 2 Divide
aV13 by aV3

0.45

0.70

0.95

VIV

VB, V9

Ch. A Oscillator "OFF" Voltage

SW4, Pos. 2

1.0

3.0

V

19

Ch. A Oscillator Current Level

VB

3.0

4.0

5.5

rnA

V6,V7

Ch. B Oscillator "OFF" Voltage

1.0

3.0

V

Is

Ch. B Oscillator Current Level

SW 4, Pos. 2, VB
Vc = 13V

3.0

4.0

5.5

rnA

aV11/(V13-V12)

Ch. A Modulator Conversion Ratio

SW 1, SW2, SW 3, Pos. 2,
Measure aV11(V10) by
Changing from VB = 12.5V,
Vc = 11.5VtoVB = 11.5V, Vc
and Divide byV13-V12

0.35

0.55

0.75

VIV

0.35

0.55

0.75

VIV

aV10/(V13-V12)

Ch. B Modulator Conversion Ratio

=

12V, Vc

=

13V

=

12V,

=

12.5V

Divide as Above

AC Electrical Characteristics (AC Test Circuit, V = 15V)
Min

Typ

V17

Symbol

Chroma Oscillator Output Level

Parameter

CLOAO:5: 20pF

Conditions

4

5

Max

Units

V15

Sound Carrier Oscillator Level

Loaded by RC Coupling
Network

2

3

VB, V9

Ch. 3 RF Oscillator Level

Ch. SW. Pos. 3, f
Use FET Probe

=

61.25 MHz,

200

350

mVp-p

V6,V7

Ch. 4 RF Oscillator Level

Ch. Sw. Pos. 4, f
Use FET Probe

=

67.25 MHz

200

350

mVp-p

Vp-p
4

Vp-p

Note 1: For operation in ambient temperatures above 25°C, the device must be derated based on a 150" maximum junction temperature and a thermal resistance
of 70'C C/W junction to ambient.

3-69

i,..
::E
....

Design Characteristics (AC Test Circuit, V =
Parameter

Typ

Oscillator Supply Dependence
3
Chroma, fa = 3.579545 MHz
Sound Carrier, RF
See Curves
Oscillator Temperature Dependence (IC Only)
Chroma
0.05
Sound Carrier
-15
-50
RF
Chroma Oscillator Output, Pin 17
20
tRISE, 10-90%
30
tFALL,90-10%
Duty Cycle (+ ) Hall Cycle
51
(-) Hall Cycle
49
RF Oscillator Maximum Operating Frequency
100
(Temperature Stability Degraded)
Chroma Modulator (f = 3.58 MHz)
0.6
B-Y Conversion Gain V13/(V4-V3)
R-Y Conversion Gain V13/(V2-V3)
0.6
Gain Balance
±0.5
See Curve
Bandwidth

15V)

Units

Parameter

Typ

Units

RF Modulator
Conversion Gain, I = 61.25 MHz,
Hz/V
10
mVrms/V
VOUT/(V13-V12)
3.58 MHz Differential Gain
5
%
ppml'C
degrees
Differential Phase
3
ppml'C
2.5 Vp-p Video, 87.5% mod.
ppml'C Output Harmonics below Carrier
-12
2nd,3rd
dB
-20
4th and above
dB
ns
ns
Input Impedances
Chroma Modulator, Pins 2, 4
%
500k//2 pF
1MII2pF
RF Modulator, Pin 12
%
250k1l3.5 pF
MHz
Pin 13

Vp-p/V
Vp-p/V
dB

3-70

r-

:s:
.....

AC Test Circuit

co
co
co
Cl
43 pF

CZ

~43PF

R-Y
BIAS

7_5V

..1_7_ _ _ _ _-4~------o

16

0----,..--"""""1
B-Y
BIAS

T-=

~-~~~U~

0_01 pF

10pH

15

14

'J'

Z40

CH4

0_001 pF
Zk

13

VIDEO INPUT
(7_5V DC)

ZZ pF
lZ

Zk

11

75

VIDEO
BIAS

CH SW

10
TO_001PF

L---~:--------------------------------t----------------~+~15V

VOUT
TL/H/7917-3

3-71

m

co

co
....
::::i

,-------------------------------------------------------------------~

Typical Performance Characteristics

....I

Sound Carrier Oscillator
Supply Dependence

RF OSCillator Frequency
Supply Dependence

(fo = 4.5 MHz)

;;
~
~

(fo = 67.25 MHz)

4r-r-,-,,.......,--,--,~~~~

3 ~~-+~4-+-~~~
2 ~~~~~~~~~~
1 ~~~~~~-J~~-+~

~ ~ ~=t=~~~jv2j~j=j=j=jj

i
ffi

~ ~~I/+V~+-~~~

-4

1-Hl-1-l-l-l--1---l---l---l---l

~ ~ r,,1/~~4-4-+-+-+-+-~
I'l
~ ~ tt:i=oo=1:j=l:::±j
g

..

10

~

-10

~

..
!~

r-r-"ro-,-.-.~-r~

t- ...

0

;;

II

V

~

1\
1\

11: -20

;

!;

\

-3D
-40

'

\,

~

~ -15

-20 L......L..J...I.J.lJ.Ul_.L.LJ.WJ.lJ
2
5
10 2D
50 100

SUPPLY VOLTAGE (VI

FREOUENCY (MH"

RF Modulator
Common-Mode Input Range
Pins 12, 13 (Application Circuit)

~~~~~~~~~~

~~ 131.~
~
~~
~~~V'-t-+-+-I

.
...
..,"
.

~
w

z

«
0:

i1.~t~!~i~I0~~~~~~
10

-5

>

Chroma Modulator
Common·Mode Input Range
Pins 2,3,4

~

r-""'I"'!'ft!H*"2\-HH-H+fl1

~ -10

-60 L.....l.-L-J--L.....J......J......J......L....L..J
10 11 12 13 14 15 16 17 18 19 20

SUPPLY VOLTAGE (VI

0

~

1\

~ -50

10 11 12 13 14 15 16 17 18 19 20

14

Chroma Modulator
Transconductance Bandwidth
lOUT 13/V1 or 18

~

w

:;;

;;

"~

14
13
12
11

10
9
8

00

~j;%;~

~00V

I>'l
1'7-'

~

1

6
5
4
3
2
1
0

10 11 12 13 14 15 16 17 18 19 20

10 11 12 13 14 15 16 17 18 19 20

SUPPLY VOLTAGE (VI

SUPPLY VOLTAGE (VI
TUH17917-4

Circuit Description (Refer to Circuit Diagram)
The channel B oscillator consists of devices 056 and 057
cross·coupled through level·shift zener diodes 054 and
055. A current regulator consisting of devices 039-043 is
used to achieve good RF frequency stability over supply and
temperature. The channel B modulator consists of multiplier
devices 058, 059 and 050-053. The top quad is coupled
to the channel B tank through isolating devices 048 and
049. A dc offset between pins 12 and 13 offsets the lower
pair to produce an output RF carrier at pin 10. That carrier is
then modulated by both the chroma signal at pin 13 and the
video and sound carrier Signals at pin 12. The channel A
modulator shares pin 12 and 13 buffers 045 and 044 with
channel B and operates in an identical manner.
The current flowing through channel B oscillator diodes
054, 055 is turned around in 060, 061 and 062 to source
current for the channel B RF modulator. In the same manner, the channel A oscillator 071-074 uses turn around
077, 078 and 079 to source the channel A modulator. One
oscillator at a time may be activated by connecting its tank
to supply (see ac test circuit). The corresponding modulator
is then activated by its current turn-around, and the other
oscillator/modulator combination remains "OFF".

The sound carrier oscillator is formed by differential amplifier 03, 04 operated with positive feedback from the pin 15
tank to the base of 04.
The chroma oscillator consists of the inverting amplifier
016, 017 and Darlington emitter follower 011, 012. An external RC and crystal network from pin 17 to pin 18 provides
an additional 180 degrees phase lag back to the base of
017 to produce oscillation at the crystal resonance frequency. (See AC test circuit).
The feedback signal from the crystal is split in a lead-lag
network to pins 1 and 18, respectively, to generate the subcarrier reference signals for the chroma modulators. The RY modulator consists of multiplier devices 029, 030 and
021-024, while the B-Y modulator consists of 031,032
and 025-028. The multiplier outputs are coupled through a
balanced summing amplifier 037, 038 to the input of the RF
modulators at pin 13. With 0 offset at the lower pairs of the
multipliers, no chroma output is produced. However, when
either pin 2 or pin 4 is offset relative to pin 3 a subcarrier
output current of the appropriate phase is produced at pin
13.

3-72

Circuit Diagram

SOUND
TANK

CHROMA
LEAD

,

15

~~~
QJ

0'

'"

~

",02

~

1k

"

03D

"

~

:'

0"

"

..---

Qa

10k

A3

'00

QIZ

A"

AZ

0"

1i ri£¥¥~~r'l~ ~

~

.;.'

15

011

'"

15k

"
0"

2>

A.

SUPPLY

OSC

18

01

04

~ 'Q,

LAG

~

0'
11k
Al1
'Ok

U

t;;;.
~

Al
2k4

Q"~ ,-

t

':

.,
..,
~

A12

A15

"k

A15

A-Y
INPUT

,-

~Q15

~,

A21

A"
2>'

0"

'k4

~~1

'k4

'04

Q!r-

f-

")."

...

A26

A25

28.

AZl

A"

")."

."

02.

...... 019

01
56.

CHROMA

~Q" ~

......0.35 R24

A21

CH.B
OUTPUT
CH.B
TANK

,
,

---!o~;:UT

....~8

7

10

"~
056

9

0;.4

CH A

TANK
11

~h

;::

R40

A44
'Ok

~Q55

1l

eH A
DUTPUT

l3-r-!oCHA
065

Q~ ~,

.53

TANK

~~

'54

'Ok

10k

'JI

."

~ 'Q6D

'--.J5

'"

".
.41

~Q12

Q14

;::

'"

A49

'41
2k1

+

'J&
'Ok

56.

."

"k

013

~44~58

.ll

'45

+

~,

,

,-

OS}

-:~Q4D :.~
• roo

GROUND

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INPUT

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SOUND
CARRIER
INPUT

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TUH17917-5

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-I

43pF

-15VO

2.2k

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-=-

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0.033

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CHROMA 8

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17

LM1889N
MOOULATOR

CHROMA A 18

R·Y

VBIAS B

B·Y

VBIAS A

BIAS

14

3

-=-

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0.D1

-=-

n"

t1

CH 4
TANK

AUDIO
LEfT
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14
O.033

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151

AUDIO IN

PON
122

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CH 3
CH 3
TANK
43pFI

180k

12

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IT

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15 VOLT
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VESTIGIAL
SIOEBAND
FILTER

Note: All capacitors in p.F. All resistors in fl.
"CENTRALAB Model 2 ULTRALIFE potenti-

ometer or equivalenl

_

TLlH179t7-6

I

Applications Information
Subcarrier Oscillator

Sound Oscillator

The oscillator is a crystal-controlled design to ensure the
accuracy and stability required of the subcarrier frequency
for use with television receivers. Lag-lead networks (R2C2
and C1R1) define a quadrature phase relationship between
pins 1 and 18 at the subcarrier frequency of 3.579545 MHz.
Other frequencies can be used and where high stability is
not a requirement, the crystal can be replaced with a parallel resonant L-C tank circuit-to provide a 2 MHz clock, for
example. Note that since one of the chrominance modulators is internally connected to the feedback path of the oscillator, operation of the oscillator at other than the correct
subcarrier frequency precludes chrominance modulation.

Frequency modulation is achieved by using a 4.5 MHz tank
circuit and deviating the center frequency via a capaCitor or
a varactor diode. Switching a 5 pF capacitor to ground at an
audio frequency rate will cause a 50 kHz deviation from
4.5 MHz. A 1N5447 diode biassed -4V from pin 16 will give
± 20 kHz deviation with a 1 Vp-p audio Signal. The coupling
network to the video modulator input and the varactor diode
bias must be included when the tank circuit is tuned to center frequency.
A good level for the RF sound carrier is between 2% and
20% of the picture carrier level. For example, if the peak
video Signal offset of pin 12 with respect to pin 13 is 3V, this
corresponds to a 30 mVrms picture RF carrier. The source
impedance at pin 12 is defined by the external 2 kO resistor
and so a series network of 15 kO and 24 pF will give a
sound carrier level at -32 dB to the picture carrier.

When an external subcarrier source is available or preferred, this can be used instead. For proper modulator operation, a subcarrier amplitude of 500 mVp-p is required at
pins 1 and 18. If the quadrature phase shift networks shown
in the application circuit are retained, about 1 Vp-p subcarrier injected at the junction of C1 and R2 is sufficient. The
crystal, C4 and R3 are eliminated and pin 17 provides a
5 Vp-p signal shifted + 125·C from the external reference.

RF Modulation
Two RF channels are available, with carrier frequencies up
to 100 MHz being determined by L-C tank circuits at pins 6,
7,8 and 9. The signal inputs (pins 12, 13) to both modulators are common, but removing the power supply from an
RF oscillator tank circuit will also disable that modulator.
As with the chrominance modulators, it is the offset between the two signal input pins that determines the level of
RF carrier output. Since one signal input (pin 13) is also
internally connected to the chrominance modulators, the
2 kO load resistor at this paint should be connected to a
bias source within the common-mode input range of the video modulators. However, this bias source is independent of
the chrominance modulator bias and where chrominance
modulation is not used, the 2 kO resistor is eliminated and
the bias source connected directly to pin 13.

Chrominance Modulation
The simplest method of chroma encoding is to define the
quadrature phases provided at pins 1 and 18 as the color
difference axes R-Y and B-Y. A signal at pin 2 (R-Y) will give
a chrominance subcarrier output from the modulator with a
relative phase of 90·C compared to the subcarrier output
produced by a signal at pin 4 (B-Y). The zero signal de level
of the R-Y and B-Y inputs will determine the bias level required at pin 3. For example, a pin 2 signal that is 1V positive with respect to pin 3 will give 0.6 Vp-p subcarrier at a
relative phase of 90·C. If pin 2 is 1V negative with repsect to
pin 3, the output is again 0.6 Vp-p, but with a relative phase
of 2700C. When a simultaneous signal exists at pin 4, the
subcarrier output level and phase will be the vector sum of
the quadrature components produced by pin 2 and 4 inputs.
Clearly, with the modulation axes defined as above, a negative pulse on pin 4 during the burst gate period will produce
the chrominance synchronizing "burst" with a phase of
180·. Both color difference signals must be dc coupled to
the modulators and the zero signal dc level of both must be
the same and within the common-mode range of the modulators.

To preserve the dc content of the video Signal, amplitude
modulation of the RF carrier is done in one direction only,
with increasing video (toward peak white) decreasing the
carrier level. This means the active composite video signal
at pin 12 must be offset with respect to pin 13 and the sync
pulse should produce the largest offset (i.e., the offset voltage of pin 12 with respect to pin 13 should have the same
polarity as the sync pulses.
The largest video signal (peak white) should not be able to
suppress the carrier completely, particularly if sound transmission is needed. For example, a signal with 1V sync amplitude and 2.5V peak white (3.5 Vp-p, negative polarity
sync) and a black level at 5 Vdc will require a dc bias of 8V
on pin 13 for correct modulation. A simple way of obtaining
the required offset is to bias pin 13 at 4 x (sync amplitude)
from the sync tip level at pin 12.

The 0.6 Vp-p/Vde conversion gain of the chrominance modulators is obtained with a 2 kO resistor connected at pin 13.
Larger resistor values can be used to increase the gain, but
capacitance at pin 13 will reduce the bandwidth. Notice that
equi-bandwidth encoding of the color difference signals is
implied as both modulator outputs are internally connected
and summed into the same load resistor.

3-75

en

CD
CD

..::::!!

..I

Applications Information (Continued)
Split Power Supplies

DC Clamped Inputs
Utilizing a DC clamp will make matching the LM1BB9 to
available signal generator outputs a simple process. Figure
3 shows the LM1BB9 configured to accept the composite
video patterns available from a Tektronix Type 144 generator that has black level at ground and negative polarity
syncs. In this application, the chroma oscillator amplifier is
used to provide a gain of two. The 1OOk pot adjusts the
overall DC level of the amplified signal which determines the
modulation depth of the RF output. Clamping the input requires a minimum of DC correction to obtain the correct DC
output level. This allows the adjustment to be a high impedance that will have minimum effect on the amplifier closed
loop gain.

The LM1 BB9 is designed to operate over a wide range of
supply voltages so that much of the time it can utilize the
signal source power supplies. An example of this is shown
in Figure 2 where the composite video signal from a character generator is modulated onto an RF carrier for display on
a conventional home TV receiver. The LM1BB9 is biased
between the -12V and +5V supplies and pin 13 is put at
ground. A 9.1 kO resistor from pin 12 to -12V dc offsets
the video input signal (which has sync tips at ground) to
establish the proper modulation depth - R1/R2 = VIN/12
x 0.B75. This design is for monochrome transmission and
features an extremely low external parts count.

,,.

CHROMINANCE
INPUTS

...---....---..------JV'.>IIr.....-o

...

(B-V,'

(A-VI

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Z40

15V

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5DpF

11

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V1DEO

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L..-_ _ _...

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1.0

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c ..

0.7 :

0.35

~

0

o 20 40 60 80 100 120 140 160
AUDIO INPUT, PIN 1 (mVrms)

3-81

TLlH/5079-4

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Circuit Description

(Refer to Circuit Diagrams)

The sound carrier oscillator is formed by differential amplifier 03, 04 operated with positive feedback from the pin 13
tank to the base of 04. Frequency modulation is obtained
by varying the 90 degree phase shifted current of 09. 014's
emitter is a virtual ground, so the voltage at pin 1 determines the current R 11, which ultimately modulates the collector current of 09.

supply. The channel B modulator consists of multiplier devices 028-031, 034 and 035. The top quad is coupled to
the channel B tank through isolating devices 026 and 027.
A DC potential between pins 10 and 11 offsets the lower
pair to produce an output RF carrier at pin 8. That carrier is
then modulated by both the sound subcarrier at pin 10 and
the composite video signal at pin 11. The channel A modulator shares pin 10 and 11 buffers, 032 and 033, with channel B and operates in an identical manner.
The current flowing through channel B oscillator diodes
022, 023 is turned around in 036-038 to source current
for the channel B RF modulator. In the same manner, the
channel A oscillator 054-057 uses turn-around 049-051
to source the channel A modulator. One oscillator at a time
may be activated by its current turn-around, and the other
oscillator/modulator combination remains off.

The video clamp is comprised of devices 058-060. The
clamp voltage is set by resistors R40, R41, R49, and R50.
The aVSE/R42 current sets the capacitor discharge current. 059 and the above mentioned resistor string help
maintain a temperature stable clamp voltage.
The channel B oscillator consists of devices 024 and 025
cross-coupled through level-shift zener diodes 022 and
023. A current regulator consisting of devices 017-021 is
used to achieve good RF stability over temperature and

Circuit Diagrams
SOUND
TANK

SOUND
SUPPLY

13

14

R13

10k

C2
15 pF

~
R3
lk

R4
lk

RIO
510
TL/H/S079-S

3-82

o

~'

C
CHANNEL S
TANK

RF
SUPPLY

CHANNELS
OUTPUT

::;

CHANNEL A
TANK

CHANNEL A
OUTPUT

c

=--"""'='

=--"""'='

iii'

ce

iiJ

R45
360

R43

360

3
g>

til

R46
360

~

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c:

054

022

R16
620
':'

R23
220

R25
10k
':'

':'

':'

':'

':'

':'

R33

R34

220

220
':'

~

CLAMP
INPUT
055

R26
10k
':'

':'

TL/H/5079-6

688~W'

iii

Applications Information
SOUND FM MODULATOR
Frequency deviation is determined by the Q of the tank circuit at pin 13 and the current entering the audio input, pin 1.
This current is set by the input voltage VIN, the device input
impedance (1.5 kll), and any impedance network connected externally. A signal of 60 mVrms at pin 1 will yield about
± 25 kHz deviation when configured as shown in A"gure 2.

RF MODULATION
Two RF channels are available, with carrier frequencies up
to 100 MHz being determined by L-C tank circuits at pins
41 5 and 617. The signal inputs (pins 10 and 11) are common to both modulators, but removing the power supply
from an RF oscillator will also disable that modulator.
The offset between the two signal pins determines the level
of the RF carrier output. To preserve the DC content of the
video Signal, amplitude modulation of the RF carrier is done
in one direction only, with increasing video (toward peak
white) decreasing the carrier level. This means the active
composite video signal at pin 11 must be offset with respect
to pin 10 and the sync pulse should produce the largest
offset.
The largest video signal (peak white) should not be able to
suppress the carrier completely, particularly if sound transmission is needed. This requires that pin lObe biased
above the largest expected video Signal. Because peak
white level is often difficult to define, a good rule to follow is
to bias pin 10 at a level which is four times the sync amplitude above the sync tip level at pin 11. For example, the DC
bias at pin 10 with 0.5V sync clamped to 5.2V on pin II,
should be 5.2+ (4XO.5)=7.2V.

VIDEO CLAMP
When video is not available at DC levels within the RF modulator common-mode range, or if the DC level of the video is
not temperature stable, then it should be AC-coupled as
shown in the typical applications circuit (Rgure 2). The
clamp holds the horizontal sync pulses at 5.2V for Vs = 12V.
The clamp coupling capacitor is charged during every sync
pulse and discharged when video information is present.
The discharge current is approximately 20 pA This current
and the amount of acceptable tilt over a line of video determines the value of the coupling capacitor Cl. For most applications 1 p.F is sufficient.

Typical Application
C,
10,.F
AUDIO.--d +
INPUT ---,

SOUND S U P P L y + - F - + - _ - - - - - - - ,

R,2
3.9k

R,O
6.Bk

+-If=-----......_''h--+-1-~~~k
CH4

L.-+'--._ _ _'V2~V'7_ _ _...

CH3

C'O

JO.'.F.". ~:k

L4
0.47 "H
L5

0.47 ""

R,3
200

R6

'00

T

C4

O•oo ,

Vs
12V

TL/H/5079-7

FIGURE 2. Two Channel Video Modulator with FM Sound

3-84

......
Applications Information

(Continued)

When the signal inputs are exactly balanced, ideally there is
no RF carrier at the output. Circuit board layout is critical to
this measurement. For optimum performance, the output
and supply decoupling circuitry should be configured as
shown in Figure 3.

PIN 12 ~1--1_--"'--ovs
.LC12

~~~ O.1~F

PIN 8

h

*

~_""-II ~
I

RF OUTPUT
CONNECTOR
TLlH/5079-8

RF decouple supply directly to output ground.

FIGURE 3. Correct RF Supply Decoupling
The video clamp level is derived from a resistive divider connected to supply (Vs). To maintain good supply rejection,
pin 10, which is biased externally, should also be referenced
to supply (see Agure 2).

Pin Description (Refer to Figure 2)
Pin 1-Audio Input: Pin 1 is the audio input to the sound
FM generator. Frequency deviation is proportional to the
signal at this pin. A pre-emphasis network comprised of R1,
C2, and the device input impedance yields the following response with an 80 mVrms audio input.
Pre-Emphasis Network
Response
25

...
N

:c

:t!. 20
z

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:;:

15

w

...z>-'"

10

V

/

J

w

:::>

51

If

5

OL.-._ _ _...I-_ _ _....I
200

2k
20k
AUDIO INPUT FREQUENCY (Hzl
TLlH/5079-9

Increasing R1 lowers the boost frequency, and decreases
deviation below the boost frequency. Increasing C2 only
lowers the boost frequency. C1 is a coupling capacitor, and
must be a low impedance compared to the sum of R1 and
the device input impedance (1.5 kfi).

Pin 2-Video Clamp: The video clamp restores the DC
component to AC-coupled video. The video is AC-coupled
to the clamp via C3. Decreasing C3 will cause a larger tilt
between vertical sync pulses in the clamped video waveform.
Pin 3-Ground: Although separate on the chip level, all
ground terminate at pin 3.
Pins 4/5-Channel 4 Oscillator: Pins 4 and 5 are the collector outputs of the channel 4 oscillator. L1 and C5 set the
oscillator frequency defined by fo= 0.159/VL 1C5. Increasing L1 will decrease the oscillator frequency while decreasing L1 will increase the oscillator frequency. Decreasing C5
will increase the oscillator frequency and lower the tank Q
causing possible drift problems. R2 and R3 are the oscillator
loads which determine the oscillator amplitude and the tank
Q. Increasing these resistors increases the Q and the oscillator amplitude, possibly overdriving the RF modulator,
which will increase output RF harmonics. Decreasing R2
and R3 reduces the tank Q and may cause increased drift.
C4 is an RF decoupling capaCitor. Increasing C4 may result
in less effective decoupling at RF. Decreasing C4 may introduce RF to supply coupling.
Pins 617-Channel 3 Oscillator; Pins 6 and 7 are the channel 3 oscillator outputs. Every component at these pins has
the same purpose and effect as those at pins 4 and 5.
Pin 8-Channel 4 RF Output: Pin 8 is the channel 4 RF
output and R13 is the load resistor. The RF signal is AC
coupled via C15 to the output filter which is a two channel
VSB filter. L5 is parallel resonant with the filter input capacitance minimizing loss in the output network. R14 terminated
the filter output.
Pin 9-Channel 3 RF Output: Pin 9 is the channel 3 RF
output with all components performing the same functions
as those in the pin 8 description.
Pin 1D-RF Modulator Sound Subcarrier Input: Pin 10 is
one of the RF modulator inputs and may be used for video
or sound. It is used as a sound subcarrier input in Figure 2.
R8, R9, and R10 set the DC bias on this pin which determines the modulation depth of the RF output (see Application Notes). R12 and C11 AC-couple the sound subcarrier
from the sound modulator to the RF modulator. R12 and
R11 form a resistive divider that determines the level of
sound at pin 10; which in turn sets the picture carrier to
sound subcarrier ratio. Increasing the ratio of R11/R12 will
increase the sound subcarrier at the output. C10 forms an
AC ground, preventing R8, R9, and R10 from having any
effects on the circuit other than setting the DC potential at
pin 10. R11 and R12 also effect the FM sound modulator
(see pin 13 description).

3-85

3:
p,)
co
co
CD

Pin Description (Continued)
Pin 11-Video Input: Pin 11, when configured as shown, is
the RF modulator video input. In this application, video is
coupled directly from the video clamp. Alternatively, video
could be DC-coupled directly to pin 11 if it is already within
the DC common-mode input range of the RF modulator (see
curves). In any case, the video sync tip at pin 11 must have
a constant DC level independent of video content. Because
of circuit symmetry, pins 10 and 11 may be interchanged.
Pin 12-RF Supply: Pin 12 is the RF supply, with C12 and
C7 serving as RF decouple capacitors. Increasing C12 or
C7 may result in less effective RF decoupling, while decreasing them may cause supply interaction. It is important
that C7 be grounded at the RF output ground.
Pin 13-Sound Tank: Pin 13 is the collector output of the
sound oscillator. L3 and C13 determine the oscillating frequency by the relationship fo=0.159/VL3C13. Increasing
L3 or C13 will lower the operating frequency, while decreasing them will raise the frequency. L3 and C13 also help
define the Q of the tank, on which FM modulator deviation level depends. As C13 increases, Q increases, and
frequency deviation decreases. Likewise, decreasing C13
increases deviation. The other factor concerning Q is the

external resistance across the tank. The series combination
R11 + R12 usually dominates the tank Q. Decreasing this
resistive network will decrease Q and increase deviation. It
should be noted that because the level of phase modulation
of the 4.5 MHz signal remains constant, variation in Q will
not effect distortion of the frequency modulation process if
the audio at pin 1 is left constant. The amplitude of the
sound subcarrier is directly proportional to Q, so increasing
the unloaded Q or either of the resistors mentioned above
will increase the sound subcarrier amplitude. For proper operation of the frequency modulator, the sound subcarrier
amplitude should be greater than 2 Vp-p.
Pin 14-Sound Supply: Pin 14 is the sound supply and C14
is an RF decouple capaCitor. Decreasing C14 may result in
increased supply interaction.

Printed Circuit Layout
Printed circuit board layout is critical in preventing RF feedthrough. The location of RF bypass capacitors on supply is
very important. Figure 4 shows an example of a properly
layed out circuit board. It is recommended that this layout be
used.

TL/H/S079-10

FIGURE 4. Printed Circuit Board and Component Diagram
(Component Side 1X)

3-86

Section 4
Motion Control

Section 4 Contents
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
* LM621 Brushless Motor Commutator TC ..............................................
* LM622 Pulse Width Modulator .......................................................
* LM628 Precision Motion Controller ...................................................
* LM1 Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .
* LM 18298 Dual Full-Bridge Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

"Devices Not Covered In Last Publication

4-2

4-3
4-4
4-15
4-16
4-17
4-23

-23:

o

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O·

Semiconductor
Corporation

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Motion Control Selection Guide

en
CD
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Dedicated Motor Control Functions
Part Number

G)

Function

c
0:

Features

CD

LM621

Brushless D.C. Motor

Deadband Timer for Direction Reversal
40V Max. Operation
35 mA Outputs for Direct Drive of Bipolar Power Transistors

LM628

High Performance Position
Control for D.C. and Brushless
D.C. Motors

On Board 32-Bit Incremental Shaft Encoder Interface
256 ,...s Loop Time
Automatic Trajectory Generator
Velocity Programmable "On-the-Fly"
Internal Programmable PID Filter
Convenient 8-Bit Host Interface
8-Bit or 12-Bit Port to DAC (LM628)
8-Bit PWM Output (LM629)

P.W.M. Controller for
Brushless and Brush D.C. Motors

Flexible Output Structure Drives H-Switches or Commutators
Precision On-Board Reference
Flexible Error Amp/Feedback Structure

LM622

H-Switches
Output Current (Amps)
Device
Peak
(Typical)

Continuous
(Max)

4

2

LM18298

1.5

1

LM18293

Supply
Voltage
(Max)

Full Current
Saturation Voltage

Operating
Temp.
Range

Package

Description

Source
(Max)

Sink
(Max)

50

2.8

2.6

-40'Cto + 150'C 15-Pin TO·220 Quad

36

1.8

1.8

-40'C to + 125'C

16-Pin DIP

Yo H Switch

Dual Full H Switch

Power Op-Amps*
Output Current
Amps

Device

Continous
Peak
(Typical)
(Max)

Input
Supply
Offset
Voltage
Voltage
(Max)
(Max)

Quiescent
Current

Slew
Rate
(Typical)

Operating
Temp.
Range

Package

Features

5-Pin TO-220 Thermal Parole

3

1.5

LM675

60

10mV

50mA

8V1,...s

O'Cto +70'C

15

10

LM12L

60

15mV

80mA

9V1,...s

-55'C to + 125'C

4-PinTO-3

Fully Protected

15

10

LM12CL

60

20mV

120mA

9V1,...s

O'Cto +70'C

4-PinTO-3

Fully Protected

15

10

LM12

80

15mV

80mA

9V1,...s

-55'Cto + 125'C

4-PinTO-3

Fully Protected

15

10

LM12C

80

20 mV

120mA

9V1,...s

O'Cto +70'C

4-PinTO-3

Fully Protected

1

0.5

LM18272

28

100mV 15 mA (Typ) 0.5 V/,...s

O'Cto +85'C

8-Pin DIP

Dual (Bridge)

·For more information on Power Amps, see the Amplifier section of the Linear Oatabook. For more High Power Amplifiers, refer to the Audio Amplifier section.

4-3

II

.,...
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~ National

PRELIMINARY

Semiconductor
Corporation

LM621 Brushless Motor Commutator IC
General Description
The LM621 is a bipolar IC designed for commutation of
brush less DC motors. The part is compatible with both
three- and four-phase motors. It can directly drive the power
switching devices used to drive the motor. The LM621 provides an adjustable dead-time circuit to eliminate "shootthrough" current spiking in the power switching circuitry.
Operation is from a 5V supply. but output swings of up to
40V are accommodated. The part is packaged in an 16-pin.
dual-in-line package.

Features
• Adjustable dead-time feature eliminates current spiking
• On-chip clock oscillator for dead-time feature

• Outputs drive bipolar power devices (up to 35 mA base
current) or MOSFET power devices
• Compatible with three- and four-phase motors ...
- Bipolar drive to delta- or V-wound motors
- Unipolar drive to center-tapped V-wound motors
- Supports 30- and 60-degree shaft position sensor
placements for three-phase motors
- Supports SO-degree sensor placement for four-phase
motors
• Directly interfaces to pulse-width modulator output(s)
via OUTPUT INHIBIT (PWM magnitude) and DIRECTION (PWM sign) inputs
• Direct interface to Hall sensors
• Outputs are current limited
• Undervoltage lockout

Connection Diagram
+5 (V
VOLTS
CC1 )
DIRECTION
DEAD-TIME
ENABLE
CLOCK
TIMING

HSI

--:-F.~;;~=i~~~l-H
UNDER
2
3

30/60
SELECT

LOGIC
GROUND

5-40 MOTOR SUPPLY
VOLTAGE (Vcd

17

OUTPUT
INHIBIT

16

CURRENT
SINK OUT #1

15

CURRENT
SINK OUT #2

14

CURRENT
SINK OUT #3

13

CURRENT
SOURCE OUT #1

12

CURRENT
SOURCE OUT #2

11

CURRENT
SOURCE OUT #3

10

POWER
GROUND

DEAD-TIME
GENERATOR

5

DIR

7

COMMUTATION
DECODER
LOGIC

HS2
HS3

VOLTAGE
LOCKOUT

18

OE

8

9

TLlH/8679-1

Order Number LM621N
See NS Package Number N18A

4-4

Absolute Maximum Ratings

(See Notes)
If MilitarylAerospace specified devices are required,
contact the National Semiconductor Sales Officel
Distributors for availability and specifications.

VCC1

+7V

VCC2

+45V

Logic Inputs (Note 1)
Logic Input Clamp Current
Output Voltages
Output Currents

Operating Ambient Temperature Range
LM621
Storage Temperature Range
Junction Temperature
ESD Susceptibility (Note 10)

VCC1 +0.5V, -0.5V
20 rnA

-40·Cto +85·C
- 65·C to + 150·C
150·C
2000V

Lead Temperature, N pkg.
(Soldering, 4 sec.)

260·C

+45V, -0.5V
Internally current limited

Electrical Characteristics (See Notes)
Parameter

Tested
Limits

Design
Limits

Units

2.0
2.0

2.0
2.0

V min
V min

= VCC1
= VCC1

100
120

200
240

p.A max
p.A max

=
=

0.6
0.6
0.6

0.4
0.4
0.4

V max

-400
-100
-700

-600
-200
-800

p.A max
p.A max
p.Amax

Conditions

Typ

DECODER SECTION
High Level Input Voltage
HS1, HS2, HS3:
30/60 SELECT:
High Level Input Current
HS1, HS2, HS3:
30/60 SELECT:
Low Level Input Voltage
HS1, HS3 and HS2
HS1, HS3 and HS2
30/60 Select

VIH
VIH

30/60
30/60

5V
OV

HSI

= HS3 =

Low Level Input Current
HS1 and HS3:
HS2:
30/60 SELECT

VIL
VIL
VIL

= 0.35V
= O.4V
= O.OV

Input Clamp Voltage
(Pins 2, 3, 5, 6, 7, 8, 17)

lin
lin

= 1 rnA
= -1 rnA

Output Leakage Current
Sinking Outputs

Outputs Off
VCC2 = 40V,

Sourcing Outputs

Your =
Your =

5V

40V
OV

V max
V max

(VCC1 + 0.7)

V

(-0.6)

V

0.2

1.0

p.A

-0.2

-1.0

p.A

= 10V,
= 10V
= OV

50

35

rnA min

-50

-35

rnA min

1= 20 rnA
1= -20mA

0.83
1.7

Output Rise Time

(sourcing)
CL<10pF

50

ns

Output Fall Time

(sinking)
CL s: 10 pF

50

ns

Propagation Delay
(Hall Input to Output)

Dead-Time Off

200

ns

Short-Circuit Current
Sinking Outputs
Sourcing Outputs
V sat (sinking)

Vdrop (sourcing)

=

(VCC2 - Your)

VCC2
Your
Your

4-5

1.00
2.00

V max
V max

Electrical Characteristics (See Notes) (Continued)
Parameter

Tested
Limits

Design
Limits

Units

2.0
2.0
2.0

2.0
2.0
2.0

Vmin
V min
V min

100
SO
200

150
100
300

p.A max
poA max
p.A max

PinS = OV

0.5
0.5
O.S

0.4
0.4
0.2

V max
V max
V max

Vin = O.SV
Vin = 0.6V
Vin = OV

-100
-60
-200

-150
-100
-300

poA max
poAmax
p.Amax

Conditions

Typ

DEAD·TIME SECTION
High Level Input Voltage
DIRECTION:
OUTPUT INHIBIT:
DEAD·TIME ENABLE:
High Level Input Current
DIRECTION:
OUTPUT INHIBIT:
DEAD-TIME ENABLE:
Low Level Input Voltage
DIRECTION:
OUTPUT INHIBIT:
DEAD-TIME ENABLE:
Low Level Input Current
DIRECTION:
OUTPUT INHIBIT:
DEAD-TIME ENABLE:

PinS = OV
Pin 17 = OV
Vin = 5V
PinS = OV

Propagation Delays
(inputs to Outputs)
OUTPUT INHIBIT
DIRECTION

Dead-Time Off,
(PinS = OV)

Minimum Clock Period,
T ClK (Note S)

200
200

ns
ns

R = 11 kn
C = 200pF

2.2

pos

Clock Accuracy
f = 100 kHz

R = 30k
C = 400pF

±S

%

Minimum Dead-Time
Minimum Dead-Time

Dead-Time Off
Dead-Time On

15
2

TClK

ns

COMPLETE CIRCUIT
Total Current Drains

Outputs Off

ICCI
ICCI
ICC2
ICC2

15

10
22

30

mAmin
mAmax

3

2
6

9

mAmin
mAmax

VCC2 = 40V

Undervoltage Lockout

3.0
3.5
VMAX
VCCI
Note t. Unless otherwise noted ambient temperature (TpJ = 2S·C.
Note 2. Unless otherwise noted: VCC1 = + S.OV, "recommended operating range Vcc = 4.SV to S.SV" VCC2 = + 1O.OV, ambient temperature = 2S·C.
Note 3. Clock oscillator period, TClK = RC, where TClK is In !,S, R is in kO, and C is pF. Also see selection graph in Typical Characteristics for determining values
of Rand C. Note that the value of R should be no less than 11 kO and C no less than 200 pF.
Note 4. Tested limits are guaranteed and 100% production tested.
Note 5. Design limits are guaranteed (but not 100% production tested) at the indicated temperature and supply voltages. These limits are not used to calculate

outgoing quality levels.
Note 6. Specifications in boldface apply over junction temperature range of -40'C to +8S·C.
Note 7. Typical Thermal Resistances
OJA (see Note 8):
I100C/W
N pkg. board mounted
N pkg, socketed
118'C/W
Note 8. Package thermal resistance indicates the ability of the package to dissipate heat generated on the die. Givan ambient temperature and power dissipation,

the thermal resistence parameter can be used to determine the approximate operating Junction temperature. Operating Junction temperature directly effects
product performance and reliability.
Note 9. This part specifically does not have thermal shutdown protection to avoid safety problems related to an unintentional restart due to thermal time constant
variations. Care should be taken to prevent excessive power dissipation on the die.

Note 10: Human body model. 100 pF, discharged through a lS000 resistor.

4-6

Typical Performance Characteristics
Supply Currents
vs Temperature

Selection Graph for Rand C
60

R=~IK

50

30

/

20

/'

10

a

V

17

~

40

o

~ j::::
400

V

15
14

. / ~20K

1200

1600

(Hl=H2=H3-5V)
-50 -25 0

I

0.90

25 50 75 100 125

2.5

..-"

2.00

j

1.80

E

r- ....... .......

ii

~

[j

1.60

0.80

1.5

i'-::S20mA;

1.0

"r-:-

0.5

1.40
25 50 75 100 125

TEMP

-50 -25 0

'c

--

r-- -

~

""

I

>u

-50 -25 0

Typ. Vsat vs lout sink
Typ. Vdrop VS lout source
(@TA = 25'C)
3.0

~

>

25 50 75 100 125
TE~POC

Vdrop VS Temperature
>~

1\

-50 -25 0

TE~poC

2.20

\

-~

11

10

Vsat vs Temperature

........

I-

12

C(pf)

1.00

--

13

f-

BOO

r-

16

Rd30K

/" ~ ./" ~1~

-

Supply Currents
vs Temperature
4

25 50 75 100 125

TE~P

OC

....-...-

o

~,...-

~s6.\

~

0102030405060
rnA
TL/H/8679-2

Description of Inputs and Outputs
Pin 10: POWER GROUND. Ground for the output buffer
supply.
Pins 11 thru 13: SOURCE OUTPUTS. The three currentsourcing outputs which drive the external power devices
that drive the motor.
Pins 14 thru 16: SINK OUTPUTS. The three current-sinking
outputs which drive the external power devices that drive
the motor.
Pin 17: OUTPUT INHIBIT. This input disables the LM621
outputs. It is typically driven by the magnitude signal from an
external sign/magnitude PWM generator. Pin 17 = +5V =
outputs off.

Pin 1: VCC1 (+ 5V). The logic and clock power supply pin.
Pin 2: DIRECTION. This input determines the direction of
rotation of the motor; ie., clockwise vs. counterclockwise.
See truth table.
Pin 3: DEAD-TIME ENABLE. This input enables or disables
the dead-time feature. Connecting + 5V to pin 3 enables
dead-time, and grounding pin 3 disables it. Pin 3 should not
be allowed to float.
Pin 4: CLOCK TIMING. This pin provides for connecting an
external resistor and capacitor to control the period of the
clock oscillator, which determines the amount of dead-time.
See Figure 4 and text.
Pins 5 thru 7: HS1, HS2, and HS3 (Hall-sensor inputs).
These inputs receive the rotor-position sensor inputs from
the motor. Three-phase motors provide all three signals;
four phase motors provide only two, one of which is connected to both HS2 and HS3.
Pin 8: 30/60 SELECT. This input is used to select the required decoding for three-phase motors; ie, either ''3~-de­
gree" (+ 5V) or "SO-degree" (ground). Connect pin 8 to
+ 5V when using a four-phase motor.
Pin 9: LOGIC GROUND. Ground for the logic power supply.

Pin 18: VCC2 (+5 to +40V). This is the supply for the
collectors of the three current-sourcing outputs (pins 11 thru
13). When driving MOSFET power devices, pin 18 may be
connected to a voltage source of up to + 40V to achieve
sufficient output swing for the gate. When driving bipolar
power devices, pin 18 should be connected to + 5V to minimize on-Chip power dissipation. Undervoltage lockout automatically shuts down all outputs if the Vee1 supply is too
low. All outputs will be off if Vee1 falls below the undervoltage lockout voltage.

4-7

-,-------------------------------------------------------------------------------------N

co

Functional Description

....I

The commutation decoder receives Hall-sensor inputs HS1,
HS2, and HS3 and a 30/60 SELECT input. This block decodes the gray-code sequence to the required motor-drive
sequence.

:IE

LM621 Commutation Decoder Truth Table, which shows
both the 30- and 60-degree phasings (and the gO-degree
phasing for four-phase motors) and their required decoder
logic truth tables, respectively. Table I shows the phasing
(or codes) of the Hall-effect sensors for each 60-degree
(electrical) position range of the rotor, and correlates these
data to the commutator sink and source outputs required to
drive the power switches. These phasings are common to
several motor manufacturers. The 60-degree phasing is preferred to 30-degree phasing because the all-zeros and allones codes are not generated. The 60-degree phasing is
more failsafe because the all-zeros and all-ones codes
could be inadvertently generated by things like disconnected or shorted sensors.
Because the above terminology is not used consistently
among all motor manufacturers, Table II, Alternative Sensor-phasing Names, will hopefully clarify some of the differences. Table II shows a different 60-degree phasing, and
120-,240-, and 300-degree phasings. Comparison with Table I will show that these four phasings are essentially shifted and lor reversed-order versions of those used with the
LM621.
Figure 1 shows the waveforms associated with the commutation decoder logic for a motor which has 60-degree rotorposition phasing, along with the generated motor-drive
waveforms. As can be seen in the drawing, Hall-effect sensor signals HS1through HS3 are separated by 60 electrical
degrees, which is the required angular resolution for threephase motors.

The dead-time generator monitors the DIRECTION input
and inhibits the outputs (pins 11 thru 16) for a time sufficient
to prevent current-spiking in the external power switches
when the direction is reversed.
The six chip outputs drive external power switching devices
which drive the motor. Three outputs source current; the
remaining three sink current. The output transistors provide
up to 50 mA outputs for driving devices, or up to 40V output
swings for driving MOSFETs. The LM621 logic is powered
from 5V.
The undervoltage lockout section monitors the Vee supply
and if the voltage is not sufficient to permit reliable logic
operation, the outputs are shutdown.

Three-Phase Motor Commutation
There are two popular conventions for establishing the relative phasing of rotor-position signals for three-phase motors. While usually referred to as 30-degree and 60-degree
sensor placements, this terminology refers to mechanical
degrees of sensor placement, not electrical degrees. The
electrical angular resolution is the required 60 degrees in
both cases. The phasing differences can be noted by comparing the sequences of HS1 through HS3 entries in Table I,

o

ROTOR POSITION:
(ElEC. DEGREES)
DIRECTION INPUT:
HS1:
HAll-SENSOR [ HS2'
INPUTS
•
HS3:

SINK 2:
SINK 3:
OUTPUTS
SOURCE 1:
SOURCE 2:
SOURCE 3:

240

300

360

I

t

I

I

,

I

I

I

I

,
L..1
I

I

I

I

I

I

I

I

,

VOUT
GND
VOUT
GND
VOUT
GND

~

I

I

I

I

I

L

~

I

I

I

......-.

_

1.....1-.1.....

'

I

I

I

I

I

I

I

I

I

I

I

I

I

120

I

1~0

240

I

300

• REVERSE·

360

I

r

i--i--ir--ll--..-..........

lM621
PIN
NUMBERS

2

5

II~I

t.-.J".....J

:-1
I

I

I

I
I

I

r

L....II

I

I i i

,

I

I

I

I

~

I
I

I
I
,..--,-

111~1
,~,

J-...J

I

I

I

L....I-

I

I

I

I

I

I

7

16

15

I

~
, , ,

14

r:l~..........................

13

~

12

I

I

I

I

I

I

I

I

I

I

I

I

I

I

:

~

I

I

I

I

I

1

I

I

I

I

r-:-1 '
r--

I

11

r--+--I

-! :
I
I

: :

:--~--:

,
I

I

I
I

I

--1

II

I
I

.........

1 __ ' , , __ Jr------;
'
I
~

I

-

60

I

~I

+
o

I

,

+,

o

0

I
, FORWARD,

VCC2
VSAT 'I~
~III'
VCC2
VSAT ~
I
I
I
I
I
I
I
VCC2
~"
VSAT "'III~

+
MOTOR
DRIVE
CURRENTS

180

o~
,
I

SINK 1:

120

I

1

o '
1 '
o -I
~;
1

60

I

I

I

I

I

I

I

I

r;-1.'
L....:..J._, : '--L

'J.
: ,--, :, '--I
:
~'

II~II

I

r

.----.-.a

l--J

,
I

I

I

I

I

L __ ~'
I
'.

I

,

,

1

I

TL/H/8679-6

FIGURE 1. Commutation Waveforms for 60-degree Phasing

4-8

Three-Phase Motor Commutation (Continued)
TABLE I. LM621 Commutation Decoder Truth Table
Sensor
Phasing

30deg

60deg

90deg

Position
Range

Sensor Inputs

Source Outputs

Sink Outputs

HS1

HS2

HS3

1

2

3

1

2

3

0-60
60-120
120-180
180-240
240-300
300-360

0
0
0
1
1
1

0
0
1
1
1
0

0
1
1
1
0
0

ON
ON
off
off
off
off

off
off
ON
ON
off
off

off
off
off
off
ON
ON

off
off
off
ON
ON
off

ON
off
off
off
off
ON

off
ON
ON
off
off
off

0-60
60-120
120-180
180-240
240-300
300-360

1
1
1
0
0
0

0
0
1
1
1
0

1
0
0
0
1
1

ON
ON
off
off
off
off

off
off
ON
ON
off
off

off
off
off
off
ON
ON

off
off
off
ON
ON
off

ON
off
off
off
off
ON

off
ON
ON
off
off
off

0-90
90-180
180-270
270-360

0
0
1
1

1
0
0
1

HS2
HS2
HS2
HS2

off
ON
off
off

na
na
na
na

off
off
ON
off

off
off
off
ON

na
na
na
na

ON
off
off
off

5

6

7

16

15

14

13

12

11

Pin Numbers:

Note 1: The above outputs are generated when the Direction input, pin 2, is logic high. For reverse rotation (pin 2 logic low), the above sink and source output
states become exchanged.
Note 2: For four·phase motors sink and source outputs number two (pins 15 and 12) are not used; hense the "na" (not applicable) in the appropriate columns
above. Figure 6 shows how the required sink and source outputs for four-phase motors are derived.

TABLE II. Alternative Sensor-Phasing Names
Alternate
Phasing

"60 deg"

"120 deg"

"240 deg"

"300 deg"

Sensor Inputs

Corresponding LM621 Position
Range and/or Comments

Position
Range

HS1

HS2

HS3

0-60
60-120
120-180
180-240
240-300
300-360

0
1
1
1
0
0

0
0
1
1
1
0

0
0
0
1
1
1

Same as 30-degree phasing, but in reverse
order; i.e., only change is relative direction.

0-60
60-120
120-180
180-240
240-300
300-360

0
1
1
1
0
0

0
0
0
1
1
1

1
1
0
0
0
1

Same as 60-degree phasing, but with shifted
order of position ranges; i.e., only change is
relative phasing of sensor signals.

0-60
60-120
120-180
180-240
240-300
300-360
0-60
60-120
120-180
180-240
240-300
300-360

0
1
1
1
0
0

1
1
0
0
0
1

0
0
0
1
1
1

Same comment as above for "120 deg"
phasing.

0
1
1
1
0
0

1
1
1
0
0
0

1
1
0
0
0
1

Same as 30-degree phasing, but with shifted
order of position ranges, i.e., only change is
relative phasing of sensor signals.

Four-Phase Motor Commutation
Four-phase motors use a 90-degree (quadrature) rotor-position sensor phasing. This phasing scheme is also shown in
Table I. LM621 Commutation Decoder Truth Table. As
shown in Table I, the 90-degree phasing has only two rotor-

position-sensor signals, HS1 and HS2. When using the
LM621 to run a four-phase motor the HS2 signal is connected to both the HS2 and HS3 chip inputs.

4-9

~

N

CD

:E

.....

,------------------------------------------------------------------------------------------,
Dead-Time Feature
The DEAD-TIME ENABLE input is used to enable this feature (by connecting + 5V to pin 3). The reason for providing
this feature is that the external power switches are usually
totem-pole structures. Since these structures switch heavy
currents, if either totem-pole device is not completely turned
oil when its complementary device turns on, heavy "shootthrough" current spiking will occur. This situation occurs
when the motor DIRECTION input changes (when all output
drive polarities reverse), at which time device turn-oil delay
can cause the undesired current spiking.

by the graph in Typical Peformance Characteristics, the time
of one clock period (in ,",s) is approximately RC (R in k.!l and
C in pF); the period can be measured with an oscilloscope
at pin 4. The dead-time generator function monitors the DIRECTION input for changes, synchronizes the direction
changes with the internal clock, and inhibits the chip outputs
for two clock periods.
Flip-flops FF1 through FF3 form a three-bit, shift-register
delay line, the input of which is the DIRECTION input. The
flip-flops are the only elements clocked by the internal clock
generator. The shift register outputs must all have the same
state in order to enable gate G1 or G2, one of which must
be enabled to enable the chip outputs. As soon as a direction change input is sensed at the output of FF1, gates G 1
and G2 will be disabled, thereby disabling the drive to the
power switches for a time equal to two clock periods.

Figure 2 shows the logiC of the dead-time generator. The
dead-time generator includes an RC oscillator to generate a
required clock. Pin 4 (CLOCK TIMING) is used to connect
an external resistor and capaCitor to control the frequency
of this oscillator. The clock frequency should be adjusted so
that two periods of oscillation just slightly exceed the worstcase turn-oil time of the power switching devices. As shown

DIRECTION
(2)

I]------.-----------------------r-,
D1R

o

D

R

DEAD-TIME
ENABLE

(3)
OUTPUT
INHIBIT D-----f

(17)

)---+-+

>Cr--------------------"-J

OE

TO
COMMUTATION
DECODER

FIGURE 2. Dead·Tlme Generator Logic Diagram

r- TCLK

"1
CLOCK

I I I I I I I I I I IS

DIRECTION _ _ _ _

TL/H/8679-7

.j&I -'~

5

"

1........1__________

s 5-5---""'1

FF1-Q _ _ _ _ _~I

.....,1--1

s

-+_-'

S

FF2 - O(DIR) _ _ _ _ _

FF3- Q _ _ _ _ _

I I I I I I I I I I I I I I I I

OE~S

-I

I- DEAD TIME
TUH/8679-B

FIGURE 3. Dead·Time Generator Waveforms

4-10

Dead·Time Feature

Typical power switches and a simple implementation of an
overcurrent sensing circuit are also detailed in Figure 4. This
application example assumes a device turn-off time of about
4.8 I1s maximum, as evidenced by the choice or Rand C.
See Typical Performance Characteristics. The choice of RC
should be made such that two periods are at least equal to
the maximum device turn-off time.
The choice of the value for Rlimi! (the resistors which couple
the LM621 outputs to the power switches) depends on the
input current requirements of the power switching devices.
These resistors should be chosen to provide only the
amount of current needed by the device inputs, up to 50 mA
(typical). The resistors minimize the dissipation incurred ~y
the LM621. Although Figure 4 shows the 5-40V supply (Pin
18) connected to the motor supply voltage, this was done
only to emphasize the ability of the part to provide up to 40V
output swings. For the bipolar power switches shown, connecting pin 18 to a 5V supply would reduce on-chip power
dissipation. Driving FET power switches, how~ver, m~y require connecting pin 18 to a higher voltage. Figure ~ IS ~he
three-phase application built with MOSFET power-swl!chln.9
components. Note that since the output Vdrop (sourcing) IS
at least 1.5V, VCC2 can be chosen to avoid overdriving the
MOSFET gates.

(Continued)

Dead-time is defined as the time the outputs are blanked off
(to prevent shoot-through currents) after a direction change
input. See Figure 3. It can be seen that the dead-time is two
clock periods. Since the dead-time scheme introduces delay into the system feedback control loop, which could impact system performance or stability, it is important that the
dead-time be kept to a minimum. From Figure 3 it can be
seen that the time between a direction change signal and
the initiation of output blanking can vary up to one clock
period due to asynchronous nature of the clock and the
direction signal.

Typical Applications
THREE-PHASE EXAMPLES
Figure 4 is a typical LM621 application. This circuitry is for
use with a three-phase motor having 30-degree sensor
phasing, as indicated by connection of the 30/60 SELECT
input, pin 8, to a logic "1" (+ 5V). The same con~ection of
the DEAD-TIME ENABLE input, pin 3, enables this feature.

RUM IT (X6)

~"'~18"''''~

+5 VOLTS

POWER SWITCHES

MOTOR
SUPPLY
VOLTAGE
(5-40V)

~--------------~

SINK:
16~M""""-+--I

lK
DEAD-TIME
ENABLE
30/60 SELECT ....- - - 1 ~

#1
LM621
BRUSHLESS
MOTOR
COMMUTATOR

..-.....--;4

13~M,...L.I-"'-I
SOURCE

SINK

15

200pF

24K

*

~M";-+-""'-;

#2
SOURCE

DIR

SIGN

------12

SINK
14 I-'\M~"""""'-;
~C

#3

,.-----;5

..-----16
,.-----17

rROM
PULSE
WIDTH
MAG -I--I-~-4
MODULATOR

11

~M.-!-~_-I

SOURCE
I
I
I
I
I

OVERCURRENT

ROTOR POSITION
SENSORS

I
I
I

I
I

HSI
HS2
HS3
TUH/8679-9

FIGURE 4. Commutation of Three-Phase Motor (Bipolar Switches)

4-11

~

N

~

.....

,-------------------------------------------------------------------------------------,
Typical Applications (Continued)
POWER SWITCHES
+5 VOLTS

DEAD-TIME
ENABLE
30/60 SELECT

SINK
161--......-

lK

...-1

#1
131--~....--I

t:.:.::::~ ~

SOURCE'

LM621
BRUSHLESS
MOTOR
COMMUTATOR

.--t---I4

SINK
15 1--";-'1-1--1

200pF

11K

MOTOR
SUPPLY
VOLTAGE

18

--,

112
SOURCE

DIR
SIGN - - - - - - 1 2

.------15

....-----16

....----17
FROM
PULSE
WIDTH
MAG -IH-+-i
MODULATOR

SINK

14

I---!-+-<'-''''
.pC

113
11 I---HH--I
SOURCE

,,
,,,

ROTOR POSmON
SENSORS

,,
,,

OVERCURRENT ,

HSI
HS2
HS3
TUH/8679-10

FIGURE 5. Commutation of Three-Phase Motor (MOSFET Switches)

4-12

.-

Typical Applications

s:
en

(Continued)

FOUR-PHASE EXAMPLE

directly, and that these are also inverted to form the remaining four. SINK #2 and SOURCE #2 outputs are not used.

Figure 6 is typical of the circuitry used to commutate a fourphase motor using the LMS21. This application is seen to
differ from the three-phase application example in that the
LMS21 outputs are utilized differently. Four-phase motors
require four-phase power switches, which in turn require the
commutator to provide four current-sinking outputs and four
current sourcing outputs. The 18-pin package of the LMS21
facilitates only three sinking and three sourcing outputs. The
schematic shows the 30/S0 SELECT input in the 30-degree
select state (pin 8 high) and rotor-position sensor inputs
HS2 and HS3 connected together. This connection truncates the number of possible rotor-position input states to
four, which is consistent with the gO-degree quadrature rotor-position signals provided by four-phase motors. With the
L.MS21 outputs connected as shown, this approach provides the needed power-switch drive signals for a fourphase motor. Note that only four of the six LMS21 outputs
(SINK #1 and #3, and SOURCE #1 and #3) are used

HALF-WAVE DRIVE EXAMPLE
The previous applications examples involved delta-configured motor windings and full-wave operation of the motor.
The application shown in Figure 7 differs in that it features
half-wave operation of a motor with the windings in a Y-configuration. This approach is suitable for automotive and other applications where only low-voltage power supplies are
conveniently available. The advantage of this power-switching scheme is that there is only one switch-voltage drop in
series with the motor winding, thereby conserving more of
the available voltage for application to the motor winding.
Half-wave operation provides only unidirectional current to
the windings; in contrast to the bidirectional currents applied
by the previous full-wave examples.

SINK 2

+5 VOLTS

8+

18
DEAD-TIME
ENABLE
30/60 SELECT

SINK #1
16
Lt,4621 15

lK

POWER SWITCHES

3
8 BRUSHLESS
MOTOR
COMMUTATOR

CLOCK
TIMING

4

24K

MOTOR
SUPPLY
VOLTAGE

0C+

A
4-PHASE
BRUSHLESS
DC MOTOR

SINK #3
14

200pf

A-

D+
SOURCE #1
13
D1R
SIGN

B-

2
HSI
HS2
HS2

5
6
7

12
11
SOURCE #3

NC

8

ROTOR POSITION
SENSORS

fROM
PULSE
MAG
WIDTH
MODULATOR

....-...

0 __
-.
TLlH/8679-11

FIGURE 6. Commutation of Four-Phase Motor

4-13

I\)
.....

~

N
CD

:::2l

r------------------------------------------------------------------------------------------,
Typical Applications

..J

(Continued)

+5 VOLTS

MOTOR SUPPLY VOLTAGE

18

DEAD-TIME
ENABLE

I
I

HSI
HS2
HS3

lK

I

3-PHASE
Y-CONFIGURED
MOTOR

ROTOR
} POSITION

LM621
BRUSHLESS
MOTOR
COMMUTATOR
CLOCK TIMING

16
15 } NC
14

C
9
8

30/SO SELECT

SOURCE
#2

of>A

of>C

12

}

POWER
SWITCHES

DIR
SIGN

13

11 ~~---T---~

FROM

~~~i~

MAG
MODULATOR

---~

TL/H/B679-12

FIGURE 7. Half-Wave Drive of V-Configured Motor

4-14

NatiOnal

~ Semiconductor

ADVANCED INFORMATION

Corporation

LM622 Pulse Width Modulator
General Description
The LM622 is a Pulse-Width-Modulator circuit designed for
control of DC brush type and brushless motors. For control
of brush less motors, the LM622 must be used with a commutator chip such as the LM621. It can be used for unidirectional and bidirectional drive circuits. Other applications for
this flexible chip include amplifiers and switching regulators.
The chip consists of a general purpose Op Amp, three comparators followed by three latches, a triangle waveform oscillator, a ± 1% precision bandgap reference and a pulseby-pulse current limit. The protection circuitry consists of
under-voltage lockout, thermal shutdown or soft-start options.
The Op Amp will generate an error voltage which will be
added to the ramp voltage. The floating triangular waveform
that results is compared to user programmable threshold
voltages in the comparators. The signals from the comparators are gated by protection circuitry before reaching opencollector outputs. PWM signals are thus available to drive

top side and bottom side switches, and to provide a direction signal.
The three comparator outputs are active low, with 20 rnA
current sinking capability.

Features
•
•
•
•
•
•
•
•
•

Single or Dual Supply Operation
±4.5 to ±20V or 9.0 to 40V Input Supply Range
Three Comparators with Open Collector Outputs
5.0 Volt Bandgap Reference Trimmed to ± 1 %
Shutdown or Soft-Start
Thermal Limit Latch
Undervoltage Lockout
50 Hz to 350 kHz Oscillator Range
Pulse-By-Pulse Current Limit Amplifier with Wide Common-Mode Range

LM622 Functional Block and Connection Diagram
Vee

.----t-----------111

VREF

RSET1
SOFT-START/

Rsrn

Vp

I
I
I

--_.

VbUT
PWM

CT
Vn

vth+
VOUT
PWM

Vth-

PWM
DIRECTION
OUT

GND

V+
V-

2

JUl

VEE
TO ALL
INTERNAL
CIRCUITRY

+----G

VEE
TLfHf9216-1

4-15

~
CD

:l

~ National

ADVANCED INFORMATION

Semiconductor
Corporation

LM628 Precision Motion Controller
General Description

Features

The LM628' is a dedicated processor for motion control. It
can fully manage a position servo loop including quadrature
feedback decoding, desired profile generation, comparison
of desired position with actual position, compensation filtering of resulting error signal, and finally output of appropriate
control signal to power amplifier driving the motor. Motor
position is sampled and outputs generated at programmable
intervals of 256
to 4096 ",s. The LM628 has a digital
programmable PIO (proportional integral derivative) filter for
compensating motor response. Output data is available as
either 8 or 12 bits wide and is sent to a OAC via an 8-bit
OAC-port. Commands and data are sent to the LM628 via
an 8-bit host-port. The host can also use this port to read
information from the LM628. The LM628 can be programmed to interrupt the host processor when error conditions occur and send back information about itself and the
motor. All programming is done with commands that relate
specifically to motion control, making the LM628 easy to
use.

•
•
•
•
•
•
•
•
•
•
•
•
•

"'S

"'S

Programmable sample period (256
to 4096 ",s)
Internal trapezoidal velocity profile generator
12-bit or 8-bit OAC output data
Programmable digital PIO filter with 16-bit coefficients
32-bit position register
32-bit velocity register
32-bit acceleration register
Quadrature incremental shaft encoder interface
8-bit parallel asynchronous host communication
Operates at 8 MHz clock frequency
TTL Compatible
Filter coefficients can be updated during motion
Velocity and target position can be updated during motion

Block Diagram
:::-:::::::'::'::':'::'::':'::'::':'::'::':'::'::':':\~~~f::.::.:.::.::.:.::.::.:.::.::.:.::./.::.::.:.:
.:: .::.: HOSTPORT I/O
~""'I-""'~-+ TO HOST PROCESSOR

8

DACPORT

8

INDEX,A, B L-3_ _ _ _ _ _ _ _ _ _ _ _ _--{
TLfH19219-1

'LM62B incorporates the SOA core processor and SOA cells designed by SOA Systems

4-16

,-------------------------------------------------------------------------, r
NatiOnal

~ Semiconductor

PRELIMINARY

:s:
.....
CD
I\,)

CO

Corporation

Co)

LM 18293 Four Channel Push Pull Driver
General Description
The LM18293 is designed to drive DC loads up to one amp.
Typical applications include driving such inductive loads as
solenoids, relays and stepper motors along with driving
switching power transistors and use as a buffer for low level
logic signals. The four inputs accept standard TTL and DTL
levels for ease of interfacing. Two enable pins are provided
that also accept the standard TTL and DTL levels. Each
enable controls 2 channels and when an enable pin is disabled (tied low), the corresponding outputs are forced to the
TRI-STATE® condition. If the enable pins are not connected
(i.e., floating), the circuit will function as if it has been enabled. Separate pins are provided for the main power supply
(pin 8), and the logic supply (pin 16). This allows a lower
voltage to be used to bias up the logic resulting in reduced
power dissipation. The chip is packaged in a specially de-

signed 16 pin power DIP. The 4 center pins of this package
are tied together and form the die paddle inside the package. This provides much better heat sinking capability than
most other DIP packages available. The device is capable
of operating at voltages up to 36 volts.

Features
•
•
•
•
•
•

1A output current capability per channel
Pin for pin replacement for L2938
Special 16 pin power DIP package
36 volt operation
Internal thermal overload protection
Logical "0" input voltage up to 1.5 volts results in high
noise immunity

Typical Connection
J-!--...,

LM18293

vs __~--------------------------------~--~

TUH/B706-1

FIGURE 1. Application circuit showing bidirectional and on/off control of a single DC motor
using two outputs and unidirectional on/off function of two DC motors using a single output each.

Order Number LM18293N
NS Package Number N16A

4·17

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and speciflcatlons_
Output Drive Supply Voltage (Vs)

36V

Logic Supply Voltage (Vss)

36V

Input Voltage (VI)

7V

Enable Voltage (VE)

7V

Peak Output Current (Non-Repetitive t = 5 ms)

2A

Junction Temperature (TJ)

+ 150'C

Thermal Resistance Junction to Case (8Jcl

14'C/W

80'C/W
Thermal Resistance Junction to Ambient (8JN
Internally Limited
Internal Power Dissipation
Operating Temperature Range
- 40'C to + 125'C
Storage Temperature Range
-65'Cto +150'C
Lead Temperature (Solder 10 seconds)
260'C

Electrical Characteristics
Vs = 24V, Vss = 5V, T = 25'C, L = 0.4V, H = 3.5V, each channel,. unless otherwise noted
Symbol

Parameter

Conditions

Typical

Tested Limit
(Note 1)

Design Limit
(Note 2)

Units

Vs

Main Supply (Pin 8)

Maximum Supply Voltage

36

Vmax

Vss

Logic Supply (Pin 16)

Minimum Logic Supply Voltage
Maximum Logic Supply Voltage

4.5
36

Vmin
Vmax

Is

Total Quiescent
Supply Current

VI = L
VI = H

10= 0

Total Quiescent Logic
Supply Current
(pin 16)

VI = L
VI = H

10= 0

Input Voltage

Min Value of Low
Max Value of Low
Min Value of High
Max Value of High (Vss :;;: 7)
Max Value of High (Vss > 7)

Iss

VI

Input Current

II
VE

Enable Voltage
(Pins 1,9)

10 = 0

10 = 0

VE = H
VE = H
VE = L

2
16

6
24
4

mAmax
mAmax
mAmax

VE = H
VE = H
VE = L

44
16
16

60
22
24

mAmax
mAmax
mAmax

-0.3
1.5
2.3
Vss
7

Vmin
Vmax
Vmin
Vmax
Vmax

-10
100

,..Amax
,..Amax

-0.3
1.5
2.3
Vss
7

Vmin
Vmax
Vmin
Vmax
Vmax

VI = L
VI = H

30

Min Value of Low
Max Value of Low
Min Value of High
Max Value of High (Vss :;;: 7)
Max Value of High (Vss > 7)

IE

Enable Current

VE = L
VE = H

-30

-100
±10

,..Amax
,..Amax

VCEsatTop

Source Saturation
Voltage

10 = -1 amp

1.4

1.8

Vmax

VCE sat Bottom

Sink Saturation
Voltage

10 = 1 amp

1.2

1.8

Vmax

tr

Rise Time

10%-90% Vo

250

ns

tf

Fall Time

90%-10%Vo

250

ns

ton

Turn-On Delay

50% VI to 50% Vo

450

ns

toff

Turn-Off Delay

50% VI to 50% Vo

200

ns

Note 1: Tasted limits are guaranteed and 100% production tested.
Note 2: Design limits are guaranteed (but not 100% production tested) over the full supply and temperature range. These limHs are not used to calculate outgoing
quality levels.

4-18

Connection Diagram
\.J

Input/Output Truth Table

ENABLE 1

1

16

INPUT 1

2

15

VSS
INPUT 4

OUTPUT 1

3

14

OUTPUT 4

GROUND

4

13

GROUND

GROUND

5

12

GROUND

OUTPUT 2

6

11

OUTPUT 3

INPUT 2

7

10

INPUT 3

Vs

8

9

Enable 1 activates outputs 1 & 2

VE (•• )

VI (Each Channel)

Vo

H
H
L
L

H
L
H
L

H
L
X (*J
X (oJ

(0) High output impedance.
(") Relative to the pertinent channel.

ENABLE 2
TL/H/B706-2

Enable 2 activates outputs 3 & 4

Simplified Schematic

II
TLlH/B706-3

4-19

Typical Performance Characteristics Vs In all cases =
Output Voltage VB.
Input Voltage

Output Voltage VB.
Enable Voltage

Vs""~CE~T H
vss=V,~5V

~TOmh=25OC

{t

If,

-+ t2~OC

2D

t.5

......

§

~t,OA

0

t.o

0.5

,'!J

t.o

--

t.o

,o=O,IA

0

0

50
v,=L. Vr=H
48

j

'o=t,OA
'o=O.5A

...... V

48

l./

......

1/

44

42

JOj,tA

40

-50

tOO

50

52

-J

I

t.5

Quiescent Logic Supply
Currentvs.
LogiC Supply Voltage

~:'5A
-r.

i:i

'o=O,5A

0

0

I

2D

""

veE SAT L

,o(A)

V,=Vr=VSS=5V

,o=l,.5A

...... ~

-50

~ ......

-r-

2.5

3.0
V,=VE=VSS=5V

,'!J

VCESAl!-1.0_
~

Sink Saturation Voltage
vs. Ambient Temperature

3.0

i:i'"

2D

VE

Source Saturation Voltage
vs. Ambient Temperature

2D

~

y-4OOC
I

VCESAT L
t.o

VI

£

i

+t~OC

2.5'

2D

V,=VE=Vss =5V

f- Tomb =25OC

~

I

1.5

'II I

Y-40OC

VCE~TL
t.o

Saturation Voltage vs.
Output Current

VS-VCESAT H

I1II I

VSS=VE=5V

24V

0

Tamb{OC)

0

100

50

to

20

30

VSS(V)

Tamb{OC)

TUH/8706-4

Typical Applications
DC motor controls (with connections to
ground and to the supply voltages)
Vs

It

915

-:::!::-

-

L

V.

M1

H

H

H

Fast Motor Stop

Run

H

H

L

Fast Motor Stop

Fast Motor Stop

L

H

Run

Run

H

L

L

Run

Fast Motor Stop

X

Free Running
Motor Stop

Free Running
Motor Stop

~

Low H

~

High X

~

Don't care

-

It

14

159

~Vss

9

V.

-:::!::- 4,5,12,13

-

Inputs

M2

H

~~

It(:~,~

TL/H/8706-5

Pin
15

X

--

910

4,5,12,13

Pin
10

~

~~

..!

VE

L

~

..!20 Vss
9

~~
t.t
""""

~iI'

14

It(:~,~

-

8

Vs

f~

L~)
910

Bidirectional DC motor control

Function

Pin10 = H
Pin15 = L

TurnCCW

Pin 10 = Pin 15

Fast Motor Stop

Pin10 = X
Pin15=X

Free Running
Motor Stop

VE = L

4-20

Low H

~

TurnCW

Pin 10 = L
Pin15=H

VE = H

L~

TLIHI8706-6

High X

~

Don't care

Motor Control Block Diagram

Bipolar Stepping Motor Control

+Vs

Step Sequencing Tables
Full Step'
VIN 1

VIN2

Step

L

L

1

L

H

2

H

H

3

H

L

4

L

L

1

.--;-- 100'C) where comparator input current is predominately leakage. See typcial curves.
Note 5: Refer to RETS122X drawing of military LM122H version for specifications.

5-8

r-

s:
.....
I\)

Typical Performance Characteristics

....rI\)

Comparator Bias Current

Comparator Bias Current
(LMI22/LM322)

Comparator Bias Current

"ro-T-r-r.-.-,,-.~

s:

"r--.---r--r--.--~

•• ~-+~~+-+-~-+~

1.. -·55'C

Co)
I\)
I\)

I I

25=~

....r-

I
I I

"

o

1",·25C

T... -25'C
TRIGGEA"HI"

ZII
~~I~~2:~~'HI"
15 I-'POiTIEDTDV'

r-

-24
COMPARATOR INPUT VOLTAGE IVI

s:
I\)

I

•

tttittt~
o
Ui
2.5

f--

CO

I__-L__

oL-~

o

'---~

....rUI

__~

1.5

2.5

s:

COMPARATOR INPUT VDLTAGE IV)

COMPARATOR INPUT VULTAGE IV)

TLlH/776B-3

Supply Current

u

T.,·-55 C

/'

Trigger In ut Characterlstlcs

I
,

Trl

/"

·ZS·C

/

l,,-n5"C

r

1

16

V·,VI

24

32

r--~

-55

.60

Collector Output Saturation
Characteristics at High Cu rrent

'"

I

. .

'" '"

'01

..."::

,1.t

10

TAi"!,
II

.....

-10
-IS

,

II

1&

"

."

'."ZS·c

TA.~

-.

24
V·(V)

Short Output Pulse
(LMI22/LM322)

32

I I
I I

~

,.,"ewa.'UOlI

,.USC'.,,'I"

,..

...

.• """"'-1lL-:f.L.ll_...1L_J.J
lOOk

",
-2,
-4,
-60
-ID

,-

N

lOOk

........

lG

'00
10

,- 'v

R,

I

'M

~·"I'-

1... ·2S·C

...-,

IDOM

'~~j' ~::~, -:"'''''J2'

10~

.......

~

r..... 5s·C"

40

HIM

Suggested Timing Components
Ik

.'"
\G

k''\.

""

.,

"-

0"

10•

TIME (sKI

Short Output Pulse
(LMI22/LM322)

."

.DUOI

'00, "M

OUTPUT CURRENT (mAl

Lagle Pin Characteristics

100

~rr

~ THRESH""'"
~UTPUT SWITCHING
1150mVTYPICAL

I

-50

THI~:!R~ '~LO"

I

TRIGGER "HI"

I
I

-ISO
-20a

!

TA -1SC

-100

TIME IllS)

DI

V

100M

'"
'"
"

TIME I",)

1M

TIMING RESISTOR III)

Reference Regulation
10.

II

1D5

~:\."."... -:.:.,.....::"

SATURATION VOLTAGE (VI

Reference Regulation

&5

..l...l.

SATURATION VOLTAG! (mY I

IS

15

TAi"t'

•,

-I-'

r--

1... ·25·'

..

,

yr. . ·-u·c

I

Timing Error Due to
lao Comparator Bias CUrrent

II I

ID

1... " 25·C

••

-15

I

TEMPERATURE ( C)

T... -55 C

I-- 'rtT... ·t2S·C

./

TYP"~::..

Nl

,
40

b

N

... r-

TRIGGER VOLTAGE IV)

Output Transistor Saturation
Characteristics at Low Currents

WDHSTCASE"l

WDHST CASE "0"

I

VP'

• "----'-_'----L_-'-----'
a
1&
Z4
32
40

T~.Z5·C

UI

I

i'

I

,Juse

/, V V

I'

er Threshold

1... ··5S·C

Vy=V'r
I
I

I
I

o
LOGIC PIN VOLTAGE (V)

TL/HI776B-4

5-9

Co)

CO

o

LM1221LM322/LM2905/LM3905
CJ)

n

~

COLLECTOR
OUTPUT

CD

3

y'

S»

n'

R28
300

o

i'

cc
D1
3
R38

EMITIER
OUTPUT

1
•

3!l
R40

'VII\..,...---2K

YREF

• • • •

•

•

r~·

If"

RIO
25K

~

o

RIC

I I

•
R8
6K

R7

2K

R23
860

GNU

•

• • •
TRIGGER

•

•

•

••

••

•

LOGIC
TLlH/7768-5

Functional Diagram
v,

BOOST

r

VREF

r-o-........- - - - t
I
I

~,-~

~RI
I
I

-1
NON·INVERTING LATCHING BUFFER
(OUTPUT LATCHES HIGH WHEN
ORIVEN TO THE HIGH STATE IF
TRIGGER IS LOW· OUTPUT UNLATCHES
IF TRIGGER IS PULSEO HI)

.-----,

RIC

L -

GNO

I

lL-I-I_O

I
I

1

1

1

+--O--!I---~~--t

I

I

__-+-...:1---<0 co LL ECTO R

V1

--L
-,-C

I

I

LOGIC
CIRCUIT

I

0--'-----.

CURRENT

~I~~:~~

1
1

EMITTER

I
I
1

I
I
1

I
1

_________ ..J

L __ _
TRIGGER

LOGIC

TLlH/776B-9

Timing Diagram
SIGNAL ON RIC PIN

4V-----~::~~:::===~~~;_--------~~
OV

V1

V2, LOGIC PIN HIGH
V2, LOGIC PIN LOW
TIMER FUNCTION
(CAPACITOR FROM RIC TO GNO)

COMPARATOR FUNCTION
(NO CAPACITOR FROM RIC TO GNO,
R 21 kU IN SERIES WITH RIC PIN)

TL/H/776B-l0

Pin Function Description
Quiescent current drawn from the Y+ terminal is typically
2.5 mA, independent of the supply voltage. Of course, additional current will be drawn if the reference is externally
loaded.
The YREF pin is the output of a 3.15V series regulator referenced to the ground pin. Up to 5.0 mA can be drawn from
this pin for driving external networks. In most applications
the timing resistor is tied to YREF, but it need not be in
situations where a more linear charging current is required.
The regulated voltage is very useful in applications where
the LM122 is not used as a timer; such as switching regulators, variable reference comparators, and temperature con-

One of the main features of the LM122 is its great versatility.
Since this device is unique, a description of the functions
and limitations of each pin is in order. This will make it much
easier to follow the discussion of the various applications
presented in this note.
Y+ is the positive supply terminal of the LM122. When using a single supply, this terminal may be driven by any voltage between 4.5V and 40V. The effect of supply variations
on timing period is less than 0.005%1V, so supplies with
high ripple content may be used without causing pulse width
changes. Supply bypassing on Y+ is not generally needed
but may be necessary when driving highly reactive loads.

5-11

II

~r-----------------------------------------------------------~
G)
C')

::i
..J

it;
o

G)

N

::i

..J

C\i

N

C')

::i

..J
.....
N

....
N

::i
..J

Pin Function Description (Continued)
troilers. Typical temperature drift of the reference is less
than 0.01 %rc.

present a minimum load on external signals tied to V ADJ .
This resistor is a pinched type with a typical variation in
nominal value of -50%, + 100% and a TC ofO.7%rC. For
this reason, external signals (typically a pot between VREF
and ground) connected to VADJ should have a source resistance as low as possible. For small changes in VADJ, up
to several kO is all right, but for large variations, 2500 or
less should be maintained. This can be accomplished with a
1k pot, since the maximum impedance from the wiper is
2500. If a voltage is forced on VADJ from a hard source,
voltage should be limited to -0.5, and + 5.0V, or current
limited to ± 1.0 mA. This includes capacitively coupled signals because even small values of capacitors contain
enough energy to degrade the input stage if the capacitor is
driven with a large, fast slewing signal. The V ADJ pin may be
used to abort the timing cycle. Grounding this pin during the
timing period causes the timer to react just as if the capacitor voltage had reached its normal RC trigger point; the
capacitor discharges and the output charges state. An exception to this occurs if the trigger pin is held high, when the
V ADJ pin is grounded. In this case, the output changes
state, but the capaCitor does not discharge.

The trigger terminal is used to start a timing cycle (see
functional diagram). Initially, 01 is saturated, Ct is discharged and the latching buffer output (V1) is latched high.
A trigger pulse unlatches the buffer, V1 goes low and turns
01 off. The timing capacitor Ct connected from RIC to GND
will begin to charge. When the voltage at the RIC terminal
reaches the 2.0V threshold of the comparator, the comparator toggles, latching the buffer output (V1) in the high state.
This turns on 01, discharges the capacitor Ct and the cycle
is ready to begin again.
If the trigger is held high as the timing period ends, the
comparator will toggle and V1 will go high exactly as before.
However, V1 will not be latched and the capacitor will not
discharge until the trigger again goes low. When the trigger
goes low, V1 remains high but is now latched.
Trigger threshold is typically 1.6V at 25°C and has a temperature dependence of -5.0 mVloC. Current drawn from
the trigger source is typically 20 /LA at threshold, rising to
600 /LA at SOV, then leveling off due to FET action of the
series resistor, R5. For negative input trigger voltages, the
only current drawn is leakage in the nA region. The trigger
can be driven from supplies as high as ± 40V, even when
device supply voltage is only 5V.

If the trigger drops while V ADJ is being held low, discharge
will occur immediately and the cycle will be over. If the trigger is still high when V ADJ is released, the output mayor
may not change state, depending on the voltage across the
timing capaCitor. For voltages below 2.0V across the timing
capacitor, the output will change state immediately, then
once more as the voltage rises past 2.0V. For voltages
above 2.0V, no change will occur in the output. This pin is
not available on the LM2905/LMS905.
In noisy environments or in comparator-type applications, a
bypass capaCitor on the V ADJ terminal may be needed to
eliminate spurious outputs because it is high impedance
point. The size of the cap will depend on the frequency and
energy content of the noise. A 0.1 /LF will generally suffice
for spike suppression, but several /LF may be used if the
timer is subjected to high level 60 Hz EM\,
The emitter and the collector outputs of the timer can be
treated just as if they were an ordinary transistor with 40V
minimum collector-emitter breakdown voltage. Normally, the
emitter is tied to the ground pin and the Signal is taken
from the collector, or the collector is tied to V+ and the
Signal is taken from the emitter. Variations on these basic
con~.ections are possible. The collector can be tied to any
positive voltage up to 40V when the Signal is taken from the
emitter. However, the emitter will not be pulled higher than
the supply voltage on the V + pin. Connecting the collector
to a voltage less than the V+ voltage is allowed. The emitter should not be connected to a low impedance load other
than that to which the ground pin is tied. The transistor has
built-in current limiting with a typical knee current of 120 mAo
Temporary short circuits are allowed; even with collectoremitter voltages up to 40V. The power x time product, however, must not exceed 15 watt-seconds for power levels
above the maximum rating of the package. A short to SOV,

The RIC pin is tied to the non-inverting side of the comparator a~d t~ the collector of 01. Timing ends when the voltage
on this pin reaches 2.0V (1 RC time constant referenced to
the S.15V regulator). 01 turns on only if the trigger voltage
has dropped below threshold. In comparator or regulator
applications of the timer, the trigger is held permanently
high and the RIC pin acts just like the input to an ordinary
comparator. The maximum voltages which can be applied to
thi~ pin are + 5.5V and -0.7V. Current from the RIC pin is
typically SOO pA when the voltage is negative with respect to
the VADJ terminal. For higher voltages, the current drops to
leakage levels. In the boosted mode, input current is typically SO nA. Gain of the comparator is very high, 200,000 or
more, depending on the state of the logic reverse pin and
the connection of the output transistor.
The ground pin of the LM122 need not necessarily be tied
to system ground. It can be connected to any positive or
negative voltage as long as the supply is negative with respect to the V+ terminal. Level shifting may be necessary
for the input trigger if the trigger voltage is referred to system ground. This can be done by capacitive coupling or by
actual resistive or active level shifting. One point must be
kept in mind; the emitter output must not be held above the
ground terminal with a low source impedance. This could
occur, for instance, if the emitter were grounded when the
ground pin of the LM122 was tied to a negative supply.
The terminallabled VADJ is tied to one side of the comparator and to a voltage divider between VREF and ground. The
divider voltage is set at 6S.2% of VREF with respect to
grouncl---ilxactly one RC time constant. The impedance of
the divider is increased to about SOk with a series resistor to

5-12

r-

3:
.....
N

Pin Function Description

(Continued)
for instance, cannot be held for more than 4 seconds.
These levels are based on 40'C maximum initial chip temperature. When driving inductive loads, always use a clamp
diode to protect the transistor from inductive kick-back.
A boost pin is provided on the LM122 to increase the speed
of the internal comparator. The comparator is normally operated at low current levels for lowest possible input current.

N
.......

TRIGGER
INPUT

r-

"Vee
TRIGGER

3:

aOOST

Col

y'

LOGIC

N

R,
You,

C(llLECTDR

V REF

R,

For timing periods less than 1 ms, where low input current is
not needed, comparator operating current can be increased
several orders of magnitude. Shorting the boost terminal to
V+ increases the emitter current of the vertical PNP drivers
in the differential stage from 25 nA to 5 p.A. This pin is not
available on the LM2905/LM3905.

~---l
~

c,

L--L

INPUT

TL/H/7768-11

With the timer in the unboosted state, timing periods are
accurate down to about 1 ms. In the boosted mode, loss of
accuracy due to comparator speed is only about 800 ns, so
timing periods of several microseconds can be used. The
800 ns error is relatively insensitive to temperature, so temperature coefficient of pulse width is still good.

FIGURE 1. BasiC Timer-Collector
Output and Timing Chart
TRIGGER
INPUT
+Vee
~

TRIGGER
LOGIC

BOOST
V'

~

The Logic pin is used to reverse the signal appearing at the
output transistor. An open or "high" condition on the logic
pin programs the output transistor to be "off" during the
timing period and "on" all other times. Grounding the logic
pin reverses the sequence to make the transistor "on" during the timing period. Threshold for the logiC pin is typically
100 mV with 150 p.A flowing out of the terminal. If an active
drive to the logic pin is desired, a saturated transistor drive
is recommended, either with a discrete transistor or the
open collector output of integrated logic. A maximum VSAT
of 25 mV at 200 p.A is required. Minimum and maximum
voltages that may appear on the logic pin are 0 and + 5.0,
respectively.

VOUl

R,

~---l
~ INPUT

L--L
TLIHI7768-12

FIGURE 2. Basic Timer-Emitter Output and Timing Chart
,Vee

Typical Applications

V·I--+---.

Basic Timers

RELAY
COIL

Figure 1 is a basic timer using the collector output. Rt and Ct
set the time interval with RL as the load. During the timing
interval the output may be either high or low depending on
the connection of the logic pin. Timing waveforms are
shown in the sketch along side Figure 1. Note that the trigger pulse may be either shorter or longer than the output
pulse width.
Figure 2 is again a basic timer, but with the output taken
from the emitter of the output transistor. As with the collector output, either a high or low condition may be obtained
during the timing period.

TLlH/7768-13

FIGURE 3. Time Out on Power Up
(Relay Energized Rt Ct Seconds after Vee Is Applied)

Simulating a Thermal Delay Relay
Figure 3 is an application where the LM122 is used to simulate a thermal delay relay which prevents power from being
applied to other circuitry until the supply has been on for
some time. The relay remains de-energized for Rt Ct seconds after Vee is applied, then closes and stays energized
until Vee is turned off. Figure 4 is a similar circuit except that
the relay is energized as soon as Vee is applied. Rt Ct seconds later, the relay is de-energized and stays off until the
Vee supply is recycled.

+ 5V Supply Driving 28V Relay
Figure 5 shows the timer interfacing 5V logic to a high voltage relay. Although the V+ terminal could be tied to the
+28V supply, this may be an unnecessary waste of power
in the Ie or require extra wiring if the LM122 is on a logic
card. In either case, the threshold for the trigger is 1.6V.

5-13

N
.......
r3:
N
co
o
en
.......

r-

3:
Col
co
o
en

~r-------------------------------------------------------------~

o
~
:E

Typical Applications (Continued)
mined by the time required to discharge Ct through the inter·
nal discharge transistor. A conservative value for Ct can be
chosen from the graph included with Figure 20. For frequen·
cies below 1 kHz. the frequency error introduced by C, is a
few tenths of one percent or less for Rt ~ 500k.

...I

U;

+Vcc

o

0)

C\I

:E
...I

......
C\I
C\I

'SeeChart

v'

C")

:E
...I

......
C\I

....

C\I

.,

RElAY
COil

C,

R'

l.Ok

lN451

:E
...I

Rl

l.Ok

COLLECTOR

TUH/7768-14

1--...--.-0 VOUT

"

FIGURE 4. Time Out on Power Up (Relay Energized Until
Rt Ct Seconds After Vee is Applied)

I I I

2: lOOk

I

TRIGGER

I OUTPUT

:~

"28V

r:

INPUT

WAVEFORM

R, C,

1
f=-

R, C,

TLlH/7768-17
100

v

10

V

10

~

c,

'"

V

0.1

V

0.01

/

D.DDI

I

TL/H/7768-15

FIGURE 5. 5V Logic Supply Driving 28V Relay

0.001

0.01

10

10

100

TLlH/7768-18

Figure 6 indicates the ability of the timer to interface to digi·
tal logic when operating off a high supply voltage. VOUT
swings between + 5V and ground with a minimum fanout of
5 for medium speed TIL. If the logic is sensitive to rise/fall
time of the trailing edge of the output pulse. the trigger pin
should be low at that time.

FIGURE 7. OSCillator
One Hour Timer with Reset and Manual Cycle End
Figure 8 shows the LM122 connected as a one hour timer
with manual controls for start. reset. and cycle end. 81
starts timing, but has no effect after timing has started. 82 is
a center off switch which can either end the cycle prema·
turely with the appropriate change in output state and discharging of Ct. or cause Ct to be reset to OV without a
change in output. In the latter case. a new timing period
starts as soon as 82 is released.

TRIGGER
INPUT
+JOV
+5.0V

VRH

0.1
C,I"~

30V Supply Interfacing with 5V Logic

CDLLECTORI---4- VouT

R,

CLOSE TO

START
TIMING

t-J

TRIGGER
lOGIC

SI

BOOST
V'

R,

t - - - -.....--tVREF

C,

COLLECTOR

R,
END CYCLE

15M

sz--o-.A,/\fIr+--I
RESET

TL/H/7768-16

• Dearbom

FIGURE 6. 30V Supply Interfacing with 5V Logic

Electronics

Astable Operation

'::'

The LM122 can be made into a self·starting oscillator by
feeding the output back to the trigger input through a capac·
itor as shown in Figure 7. Operating frequency is 1/(Rt +
R1HCt). The output is a narrow negative pulse whose width
is approximately 2R2 Ct. For optimum frequency stability. Ct
should be as small as possible. The minimum value is deter·

LP9A1A476K
Polycarbonate
TL/H17768-19

FIGURE 8. One Hour Timer with Reset
and Manual Cycle End

5·14

r-

s:
......

Typical Applications (Continued)
The average charging current through Rt is about 30 nA, so
some attention must be paid to parts layout to prevent stray
leakage paths. The suggested timing capacitor has a typical
self time constant of 300 hours and a guaranteed minimum
of 25 hours at + 25'C. Other capacitor types may be used if
sufficient data is available on their leakage characteristics.
Two Terminal Time Delay Switch
The LM 122 can be used as a two terminal time delay switch
if an "on" voltage drop of 2V to 3V can be tolerated. In
Figure 9, the timer is used to drive a relay "on" Rt • Ct
seconds after application of power. "Off" current of the
switch is 4 mA maximum, and "on" current can be as high
as 50 mA.

N

r - -....-+ VCt

N
......

r-

R1
4.711
CI
001

s:
w
N

N
......

of-_..

TRIGGER-!I--._ _. . ._
INPUT

...

r-

s:
N
<0

o

v+

U1
......

r-

VIIEF

COLLECTOR

s:

1---....1

w

<0

o

U1

vo"

Zero Power Dissipation Between Timing Intervals
In some applications it is desirable to reduce supply current
drain to zero between timing cycles. In Figure 10 this is
accomplished by using an external PNP as a latch to drive
the V+ pin of the timer.
Between timing periods 01 is off and no supply current is
drawn. When a trigger pulse of 5V minimum amplitude is
received, the LM 122 output transistor and 01 latch for the
duration of the timing period. D1 prevents the step on the
V + pin from coupling back into the trigger pin. If the trigger
input is a short pulse, C1 and R2 may be eliminated. RL
must have a minimum value of (Vccl/(2.5 mAl.

TL/H/7768-21

FIGURE 10. Zero Power Dissipation
Between Timing Intervals

TRI,~~~~ -i-----.

. - -....-+vcc

v'

COLlECTORt---....I

VREI'

TRIGGER
LOGIC

. - -....- - 1

V AEF

BOOST

~:;:::

R,
10'

3.0 mA "OFF"

R'

lOOk

RIC

I EMITTER
GND

OUTPUT
I -..."",I'v-"'- DCD,IV/KHz

y+
COLLECTOR

VA'"

SO.'
lOY

10k TRIM
R3

:::: 2,OV"ON"
RIC

CI

R,
101

R2

R,
EMlnER

. .I

GND

Co

TLlH17768-22
..,.

FIGURE 11. Frequency to Voltage Converter.
(Tachometer) Output Independent of Supply Voltage .

TLlH/7768-20

FIGURE 9. 2-Terminal Time Delay Switch
Frequency to Voltage Converter
An accurate frequency to voltage converter can be made
with the LM122 by averaging output pulses with a simple
one pole filter as shown in Figure ". Pulse width is adjusted
with R2 to provide initial calibration at 10kHz. The collector
of the output transistor is tied to VREF, giving constant amplitude pulses equal to VREF at the emitter output. R4 and
C1 filter the pulses to give a dc output equal to,
(Rtl(C,HVREFHf). Linearity is about 0.2% for a OV to 1V output. If better linearity is desired R5 can be tied to the summing node of an op amp which has the filter in the feedback
path. If a low output impedance is desired, a unity gain buffer such as the LM11 0 can be tied to the output. An analog
meter can be driven directly by plaCing it in series with R5 to
ground. A series RC network across the meter to provide
damping will improve response at very low frequencies.

TTl

t~~I~-1-....-------...,
PULSE

INPUT
TRIGGER

...--....--1 LOGIC

BOOST

v+

RJ

50'
VREF

COLLECTOR

VOUT

R,
RIC

ENlmR

R2
5.6.

TLlH/7768-23

Pulse Width Detector
'VOUT

By driving the logiC terminal of the LM122 simultaneous to
the trigger input, a simple, accurate pulse width detector can
be made (Figure 12).

~

0 for W R, C,

Pulse Out

~

W - R, C, for W R,

FIGURE 12. Pulse Width Detector

5-15

c,

Typical Applications (Continued)
In this application the logic terminal is normally held high by
R3. When a trigger pulse is received, Q1 is turned on, driving the logic terminal to ground. The result of triggering the
timer and reversing the logic at the same time is that the
output does not change from its initial low condition. The
only time the output will change states is when the trigger
input stays high longer than one time period set by Rt and
Ct. The output pulse width is equal to the input trigger width
minus Rt • Ct. C2 insures no output pulse for short « RC)
trigger pulses by prematurely resetting the timing capacitor
when the trigger pulse drops. CL filters the narrow spikes
which would occur at the output due to propagation delays
during switching.

Grounding VADJ will end the timing cycle just as if the timing
capacitor had reached its normal discharge point. A new
timing cycle can be started by the trigger terminal as soon
as the ground is released. A switching transistor is best for
driving VADJ to as near ground as possible. Worst case sink
current is about 300 pA
A timing cycle may also be ended by a positive pulse to a
resistor (R ,;; Rt/100) in series with the timing capacitor.
The pulse amplitude must be at least equal to VADJ (2.0V),
but should not exceed 5.0V. When the timing capacitor discharges, a negative spike of up to 2.0V will occur across the
resistor, so some caution must be used if the drive pulse is
used for other circuitry.
TRIIr::~~o-_ _" ,

5V Switching Regulator
Figure 13 is an application where the LM122 does not use
its timing function. A switching regulator is made using the
internal reference and comparator to drive a PNP transistor
switch. Features of this circuit include a 5.5V minimum input
voltage at 1A output current, low part count, and good efficiency (> 75%) for input voltages to 10V. Line and load
regulation are less than 0.5% and output ripple at the
switching frequency is only 30 mY. Q1 is an inexpensive
plastic device which does not need a heatsink for ambient
temperature up to 50·C. D1 should be a fast switching diode. Output voltage can be adjusted between 1V and 30V
by choosing proper values for R2, R3, R4, and R5. For outputs less than 2V, a divider with 2500 Thevinin resistance
must be connected between VREF and ground with its tap
point tied to VADJ.

VREF

COLLECTOR

lOGIC



DlSCRET
TRANSISTOR
OR lOGIC
GATE

Using the LM122 as a Comparator
A built-in reference and zero volt common mode limit make
the LM122 very useful as a comparator. Threshold may be
adjusted from zero to three volts by driving the VADJ terminal with a divider tied to VREF. Stability of the reference
voltage is typically ± 1 % over a temperature range of
- 55·C to + 125·C. Offset voltage drift in the comparator is
typically 25 /LVrC in the boosted mode and 50 /LVrC unboosted. A resistor can be inserted in series with the input
to allow overdrives up to ± 50V as shown in Figure 15.
There is actually no limit on input voltage as long as current
is limited to ± 1 rnA. The resistor shown contributes a worst
case of 5 mV to initial offset. In the unboosted mode, the
error drops to 0.25 mV maximum. The capability of operating off a single 5V supply with internal reference should
make this comparator very useful.

...---1I---I---+-....W\rt-VOUT +5.0V
Uk

R/C

t---.....-OV

TL/H/7768-25

2N38811
FAST
RECOVERY

R'
1.5M

COllECTOR

FIGURE 14. Cycle Interrupt
The output of the timer can be wire ORed with a discrete
transistor or an open collector logic gate output. This allows
overriding of the timer output, but does not cause the timer
to be reset until its normal cycle time has elapsed.

.,

'l1

I.OMH

V'"

V ADJ

~-

v·

TUH/7768-24

FIGURE 13, 5V Switching Regulator with
1 Amp Output and 5.5V Minimum Input

Application Hints
Aborting a Timing Cycle
The LM122 does not have an input specifically allocated to
a stop-timing function. If such a function is desired, it may be
accomplished several ways:
• Ground VADJ
• Raise RIC more positive than VADJ
• Wire "OR" the output

5-16

r-

:s::
......

Application Hints (Continued)

N

.Yee

"high" is 2.5V. R2 may be calculated from the divider equation with R1 to give these levels.

NDN-ltMRTING

.,

INVERTING
VRlF

COllECTOR

ALTERNATE

VOU1

+15V

CD

D.D1j.1F

Q

c.n
.......
r-

:s::

10k

(,)

CD
Q

c.n
TL/H/776B-26

FIGURE 15. Comparator with OV to 3V Threshold

.............

Eliminating Timing Cycle Upon Initial
Application of Power

>-----~

__- . . . .

~-15V

TL/H/7768-28

The LM122 will normally start a timing cycle (with no trigger
input) when V + is first turned on. If this characteristic is
undesirable, it can be defeated by tying the timing capacitor
to VREF instead of ground as shown in Figure 16. This connection does not affect operation of the timer in any other
way. If an electrolytic timing capacitor is used, be sure the
negative end is tied to the RIC pin and the positive end to
VREF. A 1.0 kn resistor should be included in series with the
timing capacitor to limit the surge current load on VREF
when the capacitor is discharged.

"'Select for Proper Level Shift
Emitter Terminal or Emitter Load must be Tied to GND Pin of TImer

FIGURE 17. Operating Off Dual Supplies
Linearizing the Charging Sweep
In some applications (such as a linear pulse width modulator) it may be desirable to have the timing capacitor charge
from a constant current source. A simple way to accomplish
this is shown in Figure 18.
v'

v'

.,
LOGIC

r---1~-IVAEF

c,

.......

:s::
N

,.....,..~,.,....~~

Cl

N
N

r-

EMITTER

"Timer Protected
Against Damage
for up to 50V

:s::
(,)

~

1
r.,GG •• ~ 1-..1__- - - - - .
INPUT ---,

r.,GG •• -

N
.......
r-

.,

.,

.....,WH.....--1.'c

v·

.,

COLLECTOR

EMITTER

1--.....-

02 LM12D

01

.,
VOUT

.2

Uk

4.7k

TLlH17768-27

FIGURE 16. Eliminating Initial Timing Cycle

TLlH/7768-29

Using Dual Supplies

FIGURE 18. Temperature Compensated
Linear Charging Sweep

The LM122 can be operated off dual supplies as shown in
Figure 11. The only limitation is that the emitter terminal
cannot be tied to ground, it must either drive a load referred
to V- or be actually tied to V- as shown. Although capacitive coupling is shown for the trigger input (to allow 5V triggering), a resistor can be substituted for C1. R2 must be
chosen to give proper level shifting between the trigger signal and the trigger pin of the timer. Worst case "10" on the
trigger pin (with respect to V-) is 0.8V, and worst case

Q1 converts the current through R 1 to a current source independent of the voltage across Ct. R2, R3, 01, and 02 are
added to make the current through R1 independent of sup·
ply variations and temperature changes. (02 is a low TC
type) 02 and R3 can be omitted if the V+ supply is stable
and 01 and R2 can be omitted also if temperature stability is
not critical. With 01, 02, R2 and R3 omitted, the current
through R1 will change about 0.015%rC with a 15V supply
and 0.1 %rC with a 5.0V supply.

5-17

II)

o
en
('I)

==
......

Application Hints (Continued)

.,

...I

Triggering with Negative Edge

II)

Although the LM122 is triggered by a positive going trigger
signal, a differentiator tied to a normally "high" trigger will
result in negative edge triggering. In Figure 19, R 1 serves
the dual purpose of holding the trigger pin normally high and
differentiating the input trigger pulse coupled through C1.
The timing diagram included with Figure 21 shows that triggering actually occurs a short time after the negative going
trigger, while positive gOing triggers have no effect. The delay time between a negative trigger signal and actual starts
of timing is approximately (0.5 to 1.5) (R1 • C1) depending
on the trigger amplitude, or about 2.5 to 7.5 ,...S with the
values shown. This time will have to be increased for Ct
larger than 0.D1 ,...F because Ct is charged to VREF whenever the trigger pin is kept high and must reset itself during the
short time that the trigger pin voltage is low. A conservative
value for C1 is:

o
en
N

==

...I

~

N

('I)

==
......

...I
N
N

.,..

==

...I

C1 :;"

o.D01
TAIGGER - - \
INPUT

1--+----.
+Vcc

~

V+

I

R,

I
I

I

VIl£F

COLLECTOR

RIC

EMITTER

R,

.,

TUH/7768-30

FIGURE 19. Timer Triggered by Negative
Edge of Input Pulse
possible connections are shown. In both cases, the output
of the timer is low during the timing period so that the positive going signal at the end of the timing period can trigger
the next timer. There is no limitation on the timing period of
one timer with respect to any other timer before or after it,
because the trigger input to any timer can be high or low
when that timer ends its timing period.

Ct

10

Chain of Timers
The LM122 can be connected as a chain of timers quite
easily with no interface required. In Figure 20A and 20B, two
VOUTllI

VOUTI21

TLlH/7768-31

(a)
V OUTI1I

TRIGGER
INPUT

VOUT121

----,
:
r...l.--.l...,

v+

I

I
I

I

VAEF

t

I I
I I

"'--t

COLLECTOR

I

t--+

r-;

lOGIC

........

i l
I
I

t-.,.-

-1

-L

VOUTtnl

L"--r...l ~
I

I

~
TL/H/7788-32

u
--,

L---I
Jl

OUTPUT 3
OUTPUT 2

OUTPUT 1
TRIGGER INPUT

L.J

n....______

(b)
FIGURE 20. Chain of Timers
5-18

TUH/7768-33

~ Semiconductor
NatiOnal

Corporation

LM 194/LM394 Supermatch Pair
General Description
The LM194 and LM394 are junction isolated ultra wellmatched monolithic NPN transistor pairs with an order of
magnitude improvement in matching over conventional transistor pairs. This was accomplished by advanced linear processing and a unique new device structure.
Electrical characteristics of these devices such as drift versus initial offset voltage, noise, and the exponential relationship of base-emitter voltage to collector current closely approach those of a theoretical transistor. Extrinsic emitter
and base resistances are much lower than presently available pairs, either monolithic or discrete, giving extremely low
noise and theoretical operation over a wide current range.
Most parameters are guaranteed over a current range of
1 )LA to 1 mA and OV up to 40V collector-base voltage,
ensuring superior performance in nearly all applications.
To guarantee long term stability of matching parameters,
internal clamp diodes have been added across the emitterbase junction of each transistor. These prevent degradation
due to reverse biased emitter current-the most common
cause of field failures in matched devices. The parasitic isolation junction formed by the diodes also clamps the substrate region to the most negative emitter to ensure complete isolation between devices.
The LM194 and LM394 will provide a considerable improvement in performance in most applications requiring a closely

matched transistor pair. In many cases, trimming can be
eliminated entirely, improving reliability and decreasing
costs. Additionally, the low noise and high gain make this
device attractive even where matching is not critical.
The LM194 and LM394/LM394B/LM394C are available in
an isolated header 6-lead TO-5 metal can package. The
LM394/LM394B/LM394C are available in an B-pin plastic
dual-in-line package. The LM394C is also available in a B
pin plastic dual-in-line package. The LM194 is identical to
the LM394 except for tighter electrical speCifications and
wider temperature range.

Features
•
•
•
•
•

Emitter-base voltage matched to 50 )LV
Offset voltage drift less than 0.1 )LVI'C
Current gain (hFEl matched to 2%
Common-mode rejection ratio greater than 120 dB
Parameters guaranteed over 1 )LA to 1 rnA collector
current
• Extremely low noise
• Superior logging characteristics compared to
conventional pairs
• Plug-in replacement for presently available devices

Typical Applications
Low Cost Accurate Square Root Circuit
lOUT = 10- 5. 410 VIN

Low Cost Accurate Squaring Circuit
lOUT = 10- 6 (VIN)2

30 pF

INPUT
0::;V,N ::;+10V

lOOk'
1%

1%

0::; V,N ~~~~~ >-_'",50",k'.-.-:'i

---- .......
\

2k
5%

15 pF

LM394

300k
1% lN451

,

1I2LM394

100k- -

1%

--

I

-:/

LM394

-

-

150k
1%

-1.2k
5%

-15V
REGULATED

30 pF
TL/H/9241-1

"'Trim for full scale accuracy

5-19

-15V
REGULATED
TL/H/9241-2

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications_
(Note 4)
Collector Current

20mA

Collector-Emitter Voltage

VMAX
40V
20V

Collector-Emitter Voltage
LM394C
Collector-Base Voltage
LM394C

40V
20V

Collector-Substrate Voltage
LM394C

40V
20V

Collector-Collector Voltage
LM394C

40V
20V

Electrical Characteristics (TJ
Parameter
Current Gain (hFE)

Current Gain Match,
(hFE Match)
= 100 [alBl [hFE!MINll

Base-Emitter Current

±10mA

Power Dissipation

500mW

Junction Temperature
LM194
LM394/LM394B/LM394C

-55'C to + 125'C
-25'Cto +B5'C

Storage Temperature Range

-65'Cto + 150'C

Soldering Information
Metal Can Package (10 sec.)
Dual-In-Line Package (10 sec.)
Small Outline Package
Vapor Phase (60 sec.)
Infrared (15 sec.)

260'C
260'C
215'C
220'C

See AN-450 "Surtace Mounting and their Effects on Product Reliability" for other methods of soldering surtace
mount devices.

= 25'C)
LM194

Conditions
VCB = OV to VMAX (Note 1)
Ic = 1 mA
Ic=100",A
Ic = 10 ",A
Ic = 1 ",A
VCB = OV to VMAX
Ic = 10 ",A to 1 mA
Ic = 1 ",A

Min

Typ

500
400
300
200

700
550
450
300

LM394B/394C

LM394
Max

Min

Typ

300
250
200
150

700
550
450
300

Max

Min

Typ

225
200
150
100

500
400
300
200

Units

Max

0.5
1.0

2

0.5
1.0

4

1.0
2.0

5

%
%

25

50

25

150

50

200

",V

10

25

10

50

10

100

",V

5

25

5

50

5

50

",V

O.OB

0.3

O.OB

1.0

0.2

1.5

",VI'C

0.03

0.1

0.03

0.3

0.03

0.5

",V/'C

Ic
Emitter-Base Offset
Voltage

VCB = 0
Ic=l",AtolmA

Change in Emitter-Base
Offset Voltage vs
Collector-Base Voltage
(CMRR)

(Note 1)
Ic = 1 ",A to 1 mA,
VCB = OV to VMAX

Change in Emitter-Base
Offset Voltage vs
Collector Current

VCB = OV,
Ic = 1 ",A to 0.3 mA

Emitter-Base Offset
Voltage Temperature
Drift

Ic = 10 ",A to 1 mA (Note 2)
IC1 = IC2
Vos Trimmed to 0 at 25'C

Logging Conformity

Ic = 3 nA to 300 ",A,
VCB = 0, (Note 3)

150

150

150

",V

Collector-Base Leakage

VCB = VMAX

0.05

0.25

0.05

0.5

0.05

0.5

nA

Collector-Collector
Leakage

VCC = VMAX

0.1

2.0

0.1

5.0

0.1

5.0

nA

Input Voltage Noise

Ic = 100 ",A, VCB = OV,
f = 100 Hz to 100 kHz

1.B

1.B

1.B

nV/.JHZ

Collector to Emitter
Saturation Voltage

Ic = 1 mA, IB = 10 ",A
Ic = 1 mA, IB = 100 ",A

0.2
0.1

0.2
0.1

0.2
0.1

V
V

Note 1: Collector·base voltage Is swept from 0 to VMAX at a collector current of 1 p.A, 10 p.A, 100 p.A, and 1 mAo
Note 2: Offset voltage drift with Vos = 0 at TA = 2S'C is valid only when the ratio of ICI to IC2 is adiusted to give the initial zero offset. This ratio must be held to
within 0.003% over the entire temperature range. Measurements taken at + 25°C and temperature extremes.
Note 3: Logging conformity is measured by computing the bast fit to a true exponential and expressing the error as a base·emitter voltage deviation.
Note 4: Refer to RETS194X drawing of military LM194H version for specifications.

5-20

Typical Applications

(Continued)

Fast, Accurate Logging Amplifier, VIN

= 10V to 0.1 mV or liN = 1 mA to 10 nA
r----------~I\R611t-~VREF

9.76k
1%

TLlH/9241-3

'Tel labs type OBI +0.3%rC
VOUT

~

- log10

(~)
VREF

Voltage Controlled Variable Gain Amplifier

v'

+15V

Rll
15k
RJ

10k

~

R5

10k
ZERO

CJ
J pF

vR&

50k
R4

5

VOUT

R7
SDk

01
lN457

Cl
JOpF

R2
2k

R8*
L-------+<200

INPUT

.,,02
... lN451

R9
215

RIO
2.5k

L----...,j,II\J.....-

-15V

TL/H/9241-4

'RB-R 10 and 02 provide a temperalure Distortion < 0.1 %
independent gain control.
Bandwidth> 1 MHz
G ~ -336 VI (dB)
100 dB gain range

5-21

..
......
en
C')
::E

Typical Applications (Continued)

....I

.....

Precision Low Drift Operational Amplifier

en
::E
....I

+

.... ••..

"'••

.3
20lt
D.I"

OUTPUT

Common·mode range 10V
ISlAS 25 nA
lOS 0.5 nA
Vas (untrimmed) 12511V

(AVost An 0.2 )LVlC
CMRR 120 dB
AVOL 2,500,000

'C 200 pF for unity gain
C 30 pF for Ay 10

C 5 pF for Ay 100
C

o pF for Ay 1000

TLlH/9241-5

High Accuracy One Quadrant Multiplier/Divider

..,
.5

SO•

'.4M

(XI INPUT

(VII.rUT

Ur-'II'I""''''''1

IZ)INPUT

TLlH/9241-6

VOUT

~

(X)(Y)·w·
(Z);
pos. e .npuIs onIy.

'Typical linearity 0.1 %

5-22

Typical Applications

(Continued)
High Performance Instrumentation Amplifier
r---------~------~~lSV

Rl
8Dk
0.1%

R2
8Dk
0.1%

3

.>....- 0 OUTPUT

Rll
18k
0.1%

INPUTS

R3
18k
0.1%

RIO
Zk
0.1%

R4
2k
0.1%

RS
Zk
&%
106
·Gain=-

Rs

01
LMl13
1.2V
02
lN4&7
-l&V
TLlH/9241-7

Performance Characteristics
Linearity of Gain (± 10V Output)
Common-Mode Rejection Ratio (60 Hz)
Common-Mode Rejection Ratio (1 kHz)
Power Supply Rejection Ratio
+ Supply
-Supply
Bandwidth (- 3 dB)
Slew Rate
Offset Voltage Drift*·
Common-Mode Input Resistance
Differential Input Resistance

G = 10,OOOG
:;;;0.01
;;,120
;;,110
>110
>110
50
0.3
:;;;0.25
>10 9
>3x 10B

Input Referred Noise (100 Hz :;;; I :;;; 10kHz)
Input Bias Current
Input Offset Current
Common-Mode Range
Output Swing (RL = 10 kn)
.... Assumes

5
75
1.5
±11
±13

s: 5 ppmrc tracking of resistors

5-23

= 1,OOOG = 100 G = 10
:;;;0.02 :;;;0.05
:;;;0.01
;;'90
;;,120
;;, 110
;;,90
;;,70
;;, 110

%
dB
dB

>110
>110
>110
dB
dB
>110
>90
>70
50
50
50
kHz
0.3
0.3
0.3
V/p.s
:;;;0.4
:;;;10 p'vrc
2
>10 9
>10 9
>10 9
n
>3 x 108 >3x10 8 >3x108 n
nV
6
12
70
75
1.5
±11
±13

75
1.5
±11
±13

75
1.5
±10
±13

.JRZ
nA
nA
V
V

Typical Performance Characteristics
1000

Small Signal Current Gain vs
Collector Current

'200

z

~~A

~ 1000

f--l mA

~

z

w

~" 40D~~Hr~~~~+H-+~~

~

'"'"u

100pA

800

.....

f--1""A
I--'"A ..;;;. z../ I

~

u

600

c

400
200

H+ttl-+tHil-H-Itt+-H-H

0.001

0.01

0.1

~

zoo

10

-15

0.6

0.4
0.2

~

0

-0.6

TI"25"C+-~~~+lI-+~-W

a

H+Ht-+tHil-H-HI.-f-H-H

'"~

-100

100

~

05

~

zoo

J"

H~At+tHil-H-Itt+-H-H

~~I!!lIlI!~I1~~~

I

0.01
0.001

0;

'"'"

'~

0.01

10

w

10

r

u:

"'00~A

~

100

100

"mi

11111
R,'~\~

~

3D

;:
Rs '" lOOk

IJII
~

1,!\0

le·'~~,-m
10

10

f - FREQUENCV (kHz)

VeE =5V

::;

·10~A

0.1

Collector to Collector
Capacitance vs Reverse
Bias Voltage

~
~

mA

1- FREQUENCY 1kHz)

0.01

40

lilli'
11111

I

0.1

Ie' 1,;0,;.
Ie =1 mA

0.1

~

0.01
0.01

~

1111

Noise Figure vs
Collector Current

Ir"25"C

Ie

Ie '"1D,uA

I

Ie - COLLECTOR CURRENT (mA)

12

0.1

10

~

III

VeE" SV

Ie

-l!I.U-

w

;;
z

Ie _ 10I.
"-

100

le""

i

,I

~

0.01 l2r~tIt:tttltJ:±tlt±:tj
0.001
0.01
0.1
10

ilL
III

Rs ·100U

~

"'-

I.

~

10

Input Voltage Noise vs
Frequency

-rtffi:2
Ie

~z

0.1

VeE =5V

10

10

0.01

Ie - COLLECTOR CURRENT {mAl

VcE -5V

Base Current Noise
vs Frequency

~

tt:tJtIt:tttlt:l:tttt:t1tn

D.D01
O.DOf

100

Ie - COLLECTOR CURRENT (mAl

~:;

10.01

Collector-Emitter
Saturation Voltage
vs Collector Current

8~ ~
:3

~ ~~~~~~~ii~~~

Ie - COLLECTOR CURRENT (mAl

1 100eB

0.1

1:1:\:1!t!:a~~m:t~u

0.1

.<;

0.4 ............w.....L.J....LJLL-L...L..LL1....L....u.u
0.001
0.01
0.1
10

Small Signal Output Conductance
vs Collector Current

i

Vc =5V
f= 100Hz

~
w

0.6

~

Tj "'25"C

10

VeE =5V

~

0.01
0.1
10
Ie - COLLECTOR CURRENT ImA)

Small Signal Input
Resistance (hlel
vs Collector Current

0.7 n-rnr""'T"T1rT""lrTTIT-rTl11

INITIAL OFFSET VOL rAGE bNI

'i

re)

iii

L

-0,8
-1
-2UIl

0.1
0.001

115

'"

l/
",

V"

.., -0.4

125

~
>

l!l -0.2

15

...

;;

./

>

25

Base-Emitter On Voltage vs
Collector Current
;

0.8

~

lzLt11ttttJtjd:!Jttlttll

-25

T. - JUNCTION TEMPERATURE

Offset Voltage Drift vs Initial
Offset Voltage

U'

VeE ::5V

;;...-

Ie - COLLECTOR CURRENT (mAl

~

Unity Gain Frequency (ftl vs
Collector Current

DC Current Gain vs Temperature

1400

U

:.!
:'!I

'\.
ZO

J
10

0.001

0.01

0.1

Ie - COLLECTOR CURRENT (mAl

o

10

20

30

40

50

COLLECTOR TO COLLECTOR VOLTAGE (V)

TLlH/9241-B

5-24

Typical Performance Characteristics
Collector to Collector Capacitance
vs Collector-Substrate Voltage
3D

-Vcc=D-

u

"0:>-

"~

,

20

(Continued)

Emitter-Base Capacitance vs
Reverse Bias Voltage

Collector-Base Capacitance vs
Reverse Bias Voltage

60

r-~~
tv" :-

_

"' ......... .......

~

20

u

r---

10

Jl

"0:

-

~

~

10

40
10

20

30

40

50

0.1

COLLECTOR TO SUBSTRATE VOLTAGE IV)

0.2

0.3

0.4

0.5

10

0.6

Collector-Base Leakage vs
Temperature

Collector to Collector Leakage
vs Temperature

100

10

~VcB=2DV

!>-

:<
oS
>-

I,
j

~

10

Jl

./

0.1

10

./

~,

/

0.1

0.01

0.01
25

50

75

100

""
!;i
~

./

"

H

125

T,- JUNCTION TEMPERATURE ('CI

W

n
rn

!

g

5 rVeE·40V++++++--I

~

+20V

~

~
m

100

-5

I-I-I-I-I-I-I-I-HH

-10 L-L.....JL.....J-L............-1......L....J.....J
o 200 400 600 800 1000
TIME (HRSI
TL/H/9241-9

i- ~e,l. D~

0.3

'l

D2
0.1

ffi

0
~ -0.1

~

-0.2

-' -0.3
-0.4
-0.5
10-8

10-7

10- 5

10-6

10-4

10-3

Ie - COLLECTOR CURRENT (AI
TL/H/9241-10

Low Frequency Noise of Differential Pair"
veE J 1V. Ie = 100.uA. Rs

t 100.0.

1.AM

,~

""

'"

"'l"'"
~BW=0-10Hz
1=1 SEC OIY

T

~

'-BW=O-l Hz
1= 10 SEC/DIV

100nV
,
'

....

...

,.,.1.

.L

1·

'r

IBw-o-o.l Hz
1= 1 SEC/OIV
TIME (SEE GRAPH)
• Unit must be in still air environment so that differential
lead temperature is held to less than O.0003'C.

5-25

50

T,= 125"C
r Ie. 60.A + + + + + + - - 1

Emitter-Base Log Conformity
0.4

40

r-r-r-r-r-r-"",,-,

T,- JUNCTION TEMPERATURE ("CI

0.5

30

Offset Voltage Long Term
Stability at High Temperature

100

./

20

REVERSE BIAS VOLTAGE (Veal

REVERSE BIAS VOLTAGE (VI

TL/H/9241-11

~

en
~

-J
~

r----------------------------------------------------------------------------,
Connection Diagram
Metal Can Package

Dual-In-Llne and Small Outline Packages

en
.,...

1 •

:::i

B

-J

TL/H/9241-12
TL/H/9241-13

Top View

Top View

Order Number LM194H, LM394H, LM394BH or LM394CH
See NS Package Number H06C

5-26

Order Number LM394CM, LM394N, LM394BN or
LM394CN
See NS Package Number M08A or N08E

r3:
co

....

NatiOnal

~ Semiconductor

en
......

Corporation

r3:
co

I\)

LM195/LM295/LM395 Ultra Reliable Power Transistors
General Description
The LM195/LM295/LM395 are fast, monolithic power transistors with complete overload protection. These devices,
which act as high gain power transistors, have included on
the chip, current limiting, power limiting, and thermal overload protection making them virtually impossible to destroy
from any type of overload. In the standard TO-3 transistor
power package, the LM195 will deliver load currents in excess of 1.0A and can switch 40V in 500 ns.
The inclusion of thermal limiting, a feature not easily available in discrete designs, provides virtually absolute protection against overload. Excessive power dissipation or inadequate heat sinking causes the thermal limiting circuitry to
turn off the device preventing excessive heating.
The LM195 offers a significant increase in reliability as well
as simplifying power circuitry. In some applications, where
protection is unusually difficult, such as switching regulators,
lamp or solenoid drivers where normal power dissipation is
low, the LM195 is especially advantageous.
The LM195 is easy to use and only a few precautions need
be observed. Excessive collector to emitter voltage can destroy the LM195 as with any power transistor. When the
device is used as an emitter follower with low source imped-

ance, it is necessary to insert a 5.0k resistor in series with
the base lead to prevent possible emitter follower oscillations. Although the device is usually stable as an emitter
follower, the resistor eliminates the possibility of trouble
without degrading performance. Finally, since it has good
high frequency response, supply bypassing is recommended.
The LM195/LM295/LM395 are available in standard TO-3
power packages and solid Kovar TO-5. The LM195 is rated
for operation from - 55·C to + 150·C, the LM295 from
- 25·C to + 150·C and the LM395 from O·C to + 125·C.

Features
•
•
•
•
•
•
•
•

Internal thermal limiting
Greater than 1.0A output current
3.0 p.A typical base current
500 ns switching time
2.0V saturation
Base can be driven up to 40V without damage
Directly interfaces with CMOS or TTL
100% electrical burn-in

Simplified Circuit
Simplified Circuit of the LM195

,....-----I
I
I

----,

I
I

I
I

I

I

I
I

I

I

0.1

I
I
I

IL _ _ _ _ _ _ _ _ _
TLlH/6009-1

5-27

en
......

r3:
Co)
co

en

Connection Diagrams
TO-3 Metal Can Package

TO-220 Plastic Package
EMITTER

~I
I

6===:=1:::
TUH/S009-3

Case Is Emitter

Top View

TL/H/S009-2

Bottom View

Order Number LM395T
See NS Package Number T03B

Order Number LM195K,
LM295K or LM395K
See NS Package Number K02A

,

TO-5 Metal Can Package
,_~:---

TO-202 Plastic Package

EMITTER

EMITTER

CASE IS EMITTER

TLiH/S009-5
TL/H/6009-4

Top View

Bottom View
Order Number LM195H,
LM295H or LM395H
See NS Package Number H03B

Order Number LM395P
See NS Package Number P03A

5-28

r-

:s:
....

Absolute Maximum Ratings

CD

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Collector to Emitter Voltage
LM195, LM295
LM395

42V
36V

Collector to Base Voltage
LM195, LM295
LM395

42V
36V

Base to Emitter Voltage (Forward)
LM195, LM295
LM395

42V
36V

Base to Emitter Voltage (Reverse)

20V

Collector Current

Internally Limited

Power Dissipation

Internally Limited

Operating Temperature Range
LM195
LM295
LM395

- 55'C to + 150'C
- 25'C to + 150'C
O'C to + 125'C

Storage Temperature Range

- 65'C to + 150'C

Lead Temperature (Soldering, 10 sec.)

260'C

100% Burn-In In Thermal Limit

Electrical Characteristics (Note 1)
LM195, LM295

Conditions

Min
Collector-Emitter Operating Voltage
(Note 3)

10:5: Ic';; iMAX

Base to Emitter Breakdown Voltage

o :5: VCE :5: VCEMAX

42

VCE:5: 15V
VCE';; 7.0V

1.2
1.2

Collector Current
TO-3, TO-220
TO-5, TO-202

LM395

Max

Min

Typ

42

Saturation Voltage

Ic:5: 1.0A, TA = 25'C

Base Current

0:5: Ic:5: iMAX
0:5: VCE:5: VCEMAX

Quiescent Current (10)

Typ

Vbe = 0
0:5: VCE:5: VCEMAX

2.2
1.8

Units
Max
36

V

36

60

V

1.0
1.0

2.2
1.8

A
A

1.8

2.0

1.8

2.2

V

3.0

5.0

3.0

10

p.A

2.0

5.0

2.0

10

mA

Base to Emitter Voltage

Ic = 1.0A, TA = +25'C

0.9

0.9

V

Switching Time

VCE = 36V, RL = 360,
TA = 25'C

500

500

ns

Thermal Resistance Junction to
Case (Note 2)

TO-3 Package (K)

2.3

3.0

2.3

3.0

'C/W

TO-5 Package (H)

12

15

12

15

'C/W

TO-220 Package (T)

4

6

'C/W

TO-202 Package (P)

12

15

'C/W

Note 1: Unless otherwise specified, these specifications apply for -55'C ,;: TJ ,;: + 150'C for the LM195, -25'C ,;: TJ ,;: + 150'C for the LM295 and O'C ,;:
+ 125'C for the LM395.
Note 2: Without a heat sink, the thermal resistance of the TO-5 package is about + 150'C/W, while that of the T0-3 package is +35'C/W.
Note 3: Selected devices with higher breakdown available.
Note 4: Refer to RETS195H and RETS195K drawings of military LM195H and LM195K versions for specifications.

5-29

:s:
~

CD

U1

Preconditioning

Parameter

U1
.......
r-

.......

r-

:s:
Co)

CD

U1

Typical Performance Characteristics (for K and T Packages)
2.5

2.4

~

i
'"co

~

~

2.0

i

1.6

~
"~

1.2
O.B
0.4

ili

5.0

10

15

20

25

3D

Short Circuit Current

2.0
TA "+12S"C ~5.C-

1.0
0.5

~

iii
~

~

1.2

2.0

'"'"

1.0

w

~>

1.6

w
::'"

1.2

!

O.B

~

0.4
15

20

25

3D

10

~

2.0

'"'"

~>

1.5

~

1.0

~

0.5

O.B

tI-

0.6

-

I

1.2
TA

~

u

;

25

30

35

0.4

TA

. Irrp...

I.LI

0.2

3D

E-2.0

w

'"'"
!:;

l;

20

5

~

!li

1.5

10

'I
1.0

2.0

TIME (/Js)

·1

I

1.6

2.0

"

, ri

+125"cl

'TA

"

-55"C

r+-I-l

-0.8 -0.4

20

0

0.4

0.8

1.2

20

40

'OV
3.0

TA I. +2J.C

v' '35",

E

'"~

12

5

B.O

~

V
"

Response Time

r--

16

r-

/

P

V+(VI

l;

1

I

BASE EMITTER VOLTAGE IVI

.".

\
\

I

I

I-

-6.0

-7.0

~-V"35yr...

I

~TA =+25°&

I

-4.0

~ -5.0

Response Time
.
"...I TA"'25~C

I--

1.2

,. -,-

I

~ -3.0

I

-

0.8

Oi' -1.0

r- l- I- ...... Ic~
I- .....

-~

\

Base Current

1.0

I~' ,!5A

'I"

+125"C

COllECTOR CURRENT lAI

.3

0.4

40

:=

f---

0.8

TEMPERATURE rCI

~

1.0

20

f-- t-

--

~

0.5

'"'"

-55 -35 -15 5.0 25 45 65 85 105 125

Saturation Voltage

COLLECTOR CURRENT IA)

15

o

35

w

z
co

~

w

'_

-=T~

I

COLLECTOR VOLTAGE IV)

2.5

1.6

~ !-- TAl. -55··C ><"

__

z

Base Emitter Voltage

2.4

10

-

0.4

5.0

1.4

5.0

.3

1c

) A • '25

2.0

COLLECTOR·EMITTER VOLTAGE IVI

~

~

........

TAj-"·T/

35

2.8

....s:

;;:

~

1.5

COLLECTOR·EMITTER VOLTAGE IVI

;;:

Bias Current

2.4

TO·3

4.0

'rt

F= 1-'.

"

..

~-

.".CI.I ••

0.4

O.B

r-

1.2

TIME (/Js)

TLIH/6009-6

5-30

r-

i:
.....

Typical Performance Characteristics (for K and T Packages) (Continued)
10V Transfer Function
~

1.6

ffi
~

1.2

....

;;;
O.B

8

0.4

,

~
~

II TA :::- 55"C

~

IlL

O.B

1.2

TA

v+ '" J6V

1-t-+:!--Jrl--1t++·--~
0.4

i:
I\)

1.2

1'-

TA =+25"CJ

~

36V Transfer Function

,rr-=

2.0

CD

en
.....
r-

O.B

T
A

0.4

=

+25"C

CD

~
ri:
Co)

Ll"c
.f
I 1 I

CD

en

I-+-I---jj:/YI-+T_ t"_---155r-"_C+--;
A

I I
I } }

§

1.6

0.4

BASE·EMITTER VOLTAGE IV)

O.B

1.2

1.6

BASE·EMITTER VOLTAGE (V)

TLiH/6009-7

TLiH/6009-8

Transconductance

Small Signal Frequency
Response

0.1
0.01

0.1

1.0

10
lOOk

COLLECTOR CURRENT (A)

1.oM

10M

FREQUENCY (Hz)

TL/H/6009-9

TL/H/6009-10

II
5-31

LM195/LM295/LM395
t/)

n

:::r
CD

3

!

COLLECTOR

C:;"

c

~"

.J

45V

l
~I

I I r"l
R2

200k
oK.

5'

~ J~"'

to>

01

R8

I

I

I

I

3

R23
1.0k

I

I I

1

~R13
12k

~Rll
400

I

J

I

I

I

03
6.3V

012

I

I

I

I

I

I

L MJIi' tJ b'
05

01
6.lV

I»

~

(r I r 1
I

...

R6
100

R5
600

Rl
2.0k

013

......

I

I

500>

04
6.3V

014

06

n.,

RIO
4.7k

Rll
70k

R12
100

EMITTER

R24
500

R22
01

R21
30

BASE
TL/H/6009-11

r
3:
......

Typical Applications

<0
UI

......

r

1.0 Amp Voltage Follower

3:

N
<0
UI

C4
1.0i-lF*

+q

......

r
3:
w

r-------------......
~-- '15V
RF

<0
UI

10k

CI
15pF

Rs

10k
INPUT -~IA..........-

....-.::..j

L-~IA..........- -....-~..... OUTPUT

' - - - - - - - - - - -. . .- - - 1 5 V

C5'
~1.0!-lF
TLlH/6009-12

Time Delay

PowerPNP
RI
5.0k·

-",---",-'15V

. ...- -.....- - EMITTER

BASE -'VI""'~'---1

500pF"

OUTPUT
02
LMI95

01
LMI95

R2
10k

CI
10,uF

' - -......~- COLLECTOR
TL/H/6009-13

"Protects against excessive base drive
TL/H/6009-14

..... Needed for stability

1.0 Amp Lamp Flasher

1.0 MHz Oscillator

V' __...._ _ _ _ _ _ _ _ _ _

v'

JOV~....- - - - - - - - - - - - - - - - - ,

*

CI

-,--O.lJ.1F

C2

O.Oh,F

~

12V

.6
25

RI
510k
R2
150k

t-....- - - - - - - - - - -........- OUTPUT

.1

1.5k
01
lM195
01
IN914

CJ
100pF
RJ
47k

1003
BULB

TLlH/6009-15
TL/H/6009-16

5-33

II)
Q)
C")

:E

Typical Applications

(Continued)

...J

.......
II)

1.0 Amp Negative Regulator

Q)

N

:E
...J
.......
II)

.,...

+

Q)

:E
...J

) -. .---~...-

....-_O~J~~T

1.0A

R2
2.4k
01
lM19S

~---------------1~------V-

TL/H/B009-17

1.0 Amp Positive Voltage Regulator
VIN
J6V

TL/H/BOD9-18

Fast Optically Isolated Switch

Optically Isolated Power Transistor

r - - - -....--V+

~
01

OUTPUT

---

.-------4~--

+

~

--01
lM19S
Rl
JJk

Rl
JJk

--~------~---VTL/H/BD09-2D

TLiH/BOD9-19

5-34

Typical Applications
CMOS or TTL Lamp Interface

r
3:
co
c.n
.......
r
3:
N
co
c.n
.......
r
3:
(0)
co
c.n

....

(Continued)

Two Terminal Current Limiter

40VSwitch

---4_-+12V

--"'--40V

+

~
DRIVE"
TLiH/6009-22

TLiH/6009-23
TL/H/6009-2t

• Drive Voltage OV to :;, 10V :;; 42V

Two Terminal 100 mA Current Regulator

6.0V Shunt Regulator with Crowbar

+

Rs
Y,N -JV""~"",--",---,,,--VOUT

02
LM195

Cl
50 pF

TLiH/6009-2S
TLiH/6009-24

Power One-Shot

Low Level Power Switch

r--.------...-

t2V

y+

12Y

r--"'-~""""'-"'- OUTPUT
Cl

0.22.F
02
LM195
Ql

lM195

Tum ON = 350 mV
Turn OFF

OUTPUT

TLiH/6009-26

= 200 mV
RL

~12!l

T = RtC
R2 = 3Rl
R2 :;; 82k

':'
TLiH/6009-27

5·35

II

Typical Applications

(Continued)

Emitter Follower

High Input Impedance AC Emitter Follower
--~"'--+15V

--~P---V+

Rl

5.0k'

INPUT

-""''''''-+-1

Q1

01

LM195

LM195

OUTPUT

t - -....--OUTPUT
• Need for Stability

- -.....---15V

TLiH/S009-28

TL/H/SOO9-29

Fast Follower
- -....~-V+

Al
5.0k
INPUT

01

-"'VV\~t-+-I

LM195

L-jI4H~ OUTPUT

VTLlH/6009-30

·Prevents storage with fast fall time square wave drive

PowerOpAmp
R,

·15V

lOOk

R2

10k
L1

R4

S.lk
22TURNS

ON R6

OUTPUT

R5
RS
10k

Rl

10

10k

R6
1.0
2W

INPUT -'''',..,..........W''lr-. .'''"I

• Adjust for 50 mA quiescent current
tSolid Tantalum

-ISV
TLiH/S009-31

5-36

,-----------------------------------------------------------------------------,
Typical Applications

(Continued)

~

....s:CD

U1
......

6.0 Amp Variable Output Switching Regulator

~

s:

V+

J6V~.-------------------.,

I\)

CD

U1

......
~

s:
Co)

CD

U1

R9

01
LM10J

100

J.9V

+

TL/H/S009-32
·Sixty turns wound on Arnold Type A-083081-2 core.

"Four devices in parallel
t50lid tantalum

5-37

o

LI)

~

:::!!i

~

LI)
LI)
LI)

r------------------------------------------------------------------,
~NatiOnal

Semiconductor
Corporation

:i LM555/LM555C Timer
General Description
The LM555 is a highly stable device for generating accurate
time delays or oscillation. Additional terminals are provided
for triggering or reselling if desired. In the time delay mode
of operation, the time is precisely controlled by one external
resistor and capacitor. For astable operation as an oscillator, the free running frequency and duty cycle are accurately
controlled with two external resistors and one capacitor.
The circuit may be triggered and reset on falling waveforms,
and the output circuit can source or sink up to 200 mA or
drive TTL circuits.

Features
• Direct replacement for SE555INE555
• Timing from microseconds through hours
• Operates in both astable and monostable modes

•
•
•
•
•

Adjustable duty cycle
Output can source or sink 200 mA
Output and supply TTL compatible
Temperature stability beller than 0.005% per·C
Normally on and normally off output

Applications
•
•
•
•
•
•
•

Precision timing
Pulse generation
Sequential timing
Time delay generation
Pulse width modulation
Pulse position modulation
Linear ramp generator

Schematic Diagram

•

v"o-----__~~~----~~----~~--------------------~----_.~~--__,

0"
R3
5k

THRESHOLD

Rl1
6.2k

R6
1.5.

6

CONTROL S
VOLTAGE
1
GND

,
TRIGGER

R'
5k

3
OUTPUT

1113

R5
5k

DISCHARGE

7

TL/H/7851-1

5-38

r3l:

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

+18V

........

260'C

215'C
220'C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

Power Dissipation (Note 1)
LM555H, LM555CH 760 mW
Operating Temperature Ranges
LM555N, LM555CN 1180 mW
LM555C
O'Cto +70'C
-55'Cto + 125'C
LM555
Storage Temperature Range

C1I
C1I
C1I

Soldering Information
Dual-In-Line Package
Soldering (10 Seconds)
Small Outline Package
Vapor Phase (60 Seconds)
Infrared (15 Seconds)

-65'Cto + 150'C

Electrical Characteristics (TA = 25'C, Vee =

+ 5V to + 15V, unless othewise specified)
Limits

Parameter

Conditions

LM555
Min

Supply Voltage
Supply Current

Timing Error, Monostable
Initial Accuracy
Drift with Temperature

Typ

4.5
Vee = 5V, RL = 00
Vee = 5V, RL = 00
(Low State) (Note 2)

3
10

LM555C
Max

Min

18

4.5

5
12

Typ

3
10

Units
Max
16

V

6
15

mA
mA

%

0.5
30

1
50

ppml'C

Accuracy over Temperature
Drift with Supply

1.5
0.05

1.5
0.1

%N

Timing Error, Astable
Initial Accuracy
Drift with Temperature
Accuracy over Temperature
Drift with Supply

1.5
90
2.5
0.15

2.25
150
3.0
0.30

%
ppml'C
%

Threshold Voltage

0.667

0.667

x Vee

5
1.67

V
V

Trigger Voltage

RA, Rs = lkto 100 k,
C = O.l/-LF, (Note 3)

Vee
Vee

=
=

15V
5V

4.8
1.45

Trigger Current
Reset Voltage

0.4

Reset Current
Threshold Current

(Note 4)

Control Voltage Level

Vee
Vee

=
=

15V
5V

9.6
2.9

Pin 7 Leakage Output High
Pin 7 Sat (Note 5)
Output Low
Output Low

Vee
Vee

=
=

15V, 17 = 15 mA
4.5V, 17 = 4.5 mA

5-39

5
1.67

5.2
1.9

0.01

0.5

0.5

1

0.1

0.4

0.1

0.25

10
3.33

10.4
3.8

1
150
70

%

%N

0.5

0.9

0.5

1

V

0.1

0.4

mA

0.1

0.25

/-LA

10
3.33

11
4

V
V

100

1

100

nA

100

180
80

200

mV
mV

0.4

9
2.6

/LA

r3l:
C1I
C1I
C1I

o

Electrical Characteristics TA =

25°C, Vcc =

+ 5V to + 15V, (unless othewise specified) (Continued)
Limits

Parameter

Conditions

LM555
Min

Output Voltage Drop (Low)

Max

0.1
0.4
2
2.5

0.15
0.5
2.2

0.1

0.25

Vcc = 15V
ISINK = 10 mA
ISINK = 50mA
ISINK = 100 mA
ISINK = 200 mA
Vcc = 5V
ISINK = 8mA
ISINK = 5mA

Output Voltage Drop (High)

ISOURCE = 200 mA, Vcc = 15V
ISOURCE = 100 mA, Vcc = 15V
Vcc = 5V

13
3

LM555C

Typ

Min

12.5
13.3
3.3

12.75
2.75

Units

Typ

Max

0.1
0.4
2
2.5

0.25
0.75
2.5

0.25

0.35

V
V
V
V
V
V
V
V
V

12.5
13.3
3.3

Rise Time of Output

100

100

ns

Fall Time of Output

100

100

ns

+ 150"C maximum junction

Nole I: For operating at elevated temperatures the device must be derated above 25"C based on a
resistance of 164"c/w (TO.5). 106"'c/w (DIP) and 170"c/w (SO·8) Junction to ambient.
Nole 2: Supply current when output high typically 1 mA less at Vee
Nole 3: Tested at Vee

~

5V and Vee

~

~

temperature and a thermal

5V.

15V.

Nole 4: This will determine the maximum value of RA

+

RS for 15V operalion. The maximum total (RA

+

Rs) is 20 MO.

Note 5: No protection against excessive pin 7 current is necessary providing the package dissipation rating will not be exceeded.
Nole 6: Refer to RETS555X drawing of military LM555H and LM555J versions for specifications.

Connection Diagrams
Dual-In-Line and Small Outline Packages

Metal Can Package
Vee
GNO

TRIGGER

I

1
GND - "

1

2

6

TRIGGER....!.

THRESHOLO

3

OUTPUT

3

\...;I

h

OU11'UT ...;;.

" ..

8

~ ~ +Vee

OISCHARGE

~
..:::.
~~:,'

.

8--s-

2-

DISCHARGE

~6

•~

r-- THRESHOLD

4
RESET

RESET

..!.

..",,,,, .

TLlH17851-2

5

CONTROL
VOLTAGE

Top View
TL/H/7851-3

Order Number LM555H or LM555CH
See NS Package Number H08C

Top View
Order Number LM555J, LM555CJ,
LM555CM or LM555CN
See NS Package Number JOBA, M08A or NOBB

5-40

r-

:s:::

en
en
en
......

Typical Performance Characteristics
Minimuim Pulse Width
Required for Triggering

Supply Current vs
Supply Voltage

12

1.2

.,..;;
:;
'"
i

~

~

;§
i!!

,.

2

l.a

Vee "'15V

1.1
1.0
0.9

10

,

0.6
0.5
0.4
0.3
0.2
0.1

~i.-'

-55~

T-·,25"C

D.a
D.l

.... t::P +25"C

T'+~5!C __
.....

~~

r

T,'j' 5 C

~~

+125'C

0.3

0.2

1.4

~

D.B
0.6

~
':A _55lc

0.1

0.01

rr

ISINK

--

J f-

~

~
~

~

.

~

IE

Low Output Voltage vs
Output Sink Current

;x": ~

10
ISINK

!

1000

I

g

600

~ 600

400·

~

200

IE

~

!

100

!

t'-. o·c

W It (i..

200

o

~

+2~}L~
i II W

,

400

1000

r,

+125-C

+loc1 )1

BOD

0.3

IX vccl

= I5V

I

>

LOWEST VOLTAGE LEVEL OF TRIGGER PULSE

Discharge Transistor (Pin 7)
Voltage vs Sink Current

Output Propagation Delay vs
Voltage Level of Trigger Pulse

aoo

0.2

100

100

(mAl

1200

0.1

-55'C

I I

1.0

(mAl

P+H--+.-I-+-HI-+--HIM

I

~

0.01
100

Vee

1000

' +25"C

0.1

1200

>

100
(mAl

+125"C

Output Propagation Delay vs
Voltage Level of Trigger Pulse

!

ISDURCE

10

1.0

a

25'C

10

5V ~ Vee $15V

Vee = lOV

II II

~
1.0

f--

10

10

+125"C

./

15

Vee = 5V

-55'C

tTA ·+125"C

Low Output Voltage vs
Output Sink Current

10

1.0

1.2

SUPPLY VOLTAGE IVI

Low Output Voltage vs
Output Sink Current

o

TA. -+25"C

0.2
0
10

LOWEST VOLTAGE LEVEL OF TRIGGER PULSE IX Veel

en
en
en

0.4

5

0.4

:s:::

V

f-lT..a.c

1.6

a
J,

o
0.1

r-

High Output Voltage vs
Output Source Current

J

10

i551CI

o

0.1

0.2

0.3

0.1

LOWEST VOLTAGE LEVEL OF TRIGGER PULSE IX Vecl

1.0
ISINK

(mAl PIN

10

100

7

Discharge Transistor (Pin 7)
Voltage vs Sink Current
1000

z
0:

100

~
.;

10

1.0 L-J.J..WIII1-W
0.01
0.1

1.0

10

100

ISINK (mAl PIN 7
TL/H17851-4

5-41

Application Information
When the reset function is not in use, it is recommended
that it be connected to Vee to avoid any possibility of false
triggering.
Figure 3 is a nomograph for easy determination of R, C
values for various time delays.

MONOSTABLE OPERATION
In this mode of operation, the timer functions as a one-shot
(Figure 1J. The external capacitor is initially held discharged
by a transistor inside the timer. Upon application of a negative trigger pulse of less than 1/3 Vee to pin 2, the flip-flop is
set which both releases the short circuit across the capacitor and drives the output high.

NOTE: In monostable operation, the trigger should be driven high before the
end of timing cycle.

~______________e-~+5~V~TD~+~15~V~~-o+V~

Rf--

I
~g:!:'t~~~

~

t

TRIGGER

RL

4

"0=.

100

8

2

DISCHARGE
7

10

~

I
I

ASTABLE OPERATION
If the circuit is connected as shown in Figure 4 (pins 2 and 6
connected) it will trigger itself and free run as a

6

LM555

~

THRESHOLD

~

u

z
or

t

:!

0.1

~

!::

OUTPUT

:!

NORMALLY ~
"OFF" LOAD? RL

I

u

0.01

r

...,c::-

vvJ~f

I--

V VV V
'O~sI00j.ls

TLlH17851-5

1 ms 10 ms 100 ms Is 10 s 100 s
I. - TIME DELAY

FIGURE 1. Monostable
The voltage across the capacitor then increases exponentially for a period of t = 1.1 RA C, at the end of which time
the voltage equals 2/3 Vee. The comparator then resets
the flip-flop which in turn discharges the capacitor and
drives the output to its low state. Figure 2 shows the waveforms generated in this mode of operation. Since the charge
and the threshold level of the comparator are both directly
proportional to supply voltage, the timing internal is independent of supply.

r

V V 1/ /
V/
~VV
f---~;
~'" %. V
V-

TL/H/7851-7

FIGURE 3. Time Delay
multivibrator. The external capacitor charges through RA +
Rs and discharges through Rs. Thus the duty cycle may be
precisely set by the ratio of these two resistors.
+Vcc

i
I
I

I

I

r

~ RL

R.

8

4

-

7

2

I

R.

I

LM555

I

6

I
"r

II
vee ~ SV
TIME ~ 0.1 ms/DIV.
RA ~ 9.1 kO
C

~

~RL

II

5l

3

_ .... C

1
-ro:D1PJ'

TLlH17851-6

Top Trace: Input 5V1Div.
Middle Trace: Output SVlDiv.
Bottom Trace: CapaCitor Voltage 2V1Div.

TL/H17851-8

FIGURE 4. Astable
In this mode of operation, the capacitor charges and discharges between 113 Vee and 2/3 Vee. As in the triggered
mode, the charge and discharge times, and therefore the
frequency are independent of the supply voltage.

0.01 "F

FIGURE 2. Monostable Waveforms
During the timing cycle when the output is high, the further
application of a trigger pulse will not effect the circuit. However the circuit can be reset during this time by the application of a negative pulse to the reset terminal (pin 4). The
output will then remain in the low state until a trigger pulse is
again applied.

5-42

r-

Applications Information

==

(Continued)

I

Figure 5 shows the waveforms generated in this mode of
operation.

II

u

J

II

"

u

~

u

U1
U1
U1

......
r-

-

==
U1
U1
U1

V1

r

l

I

'\

V1

\ /:

r

o
I- ,..-

f...-t-"
i

......-f"'"""

TL/H/7851-11

Top Trace: Inpul4V10iv.
vee = SV
TIME = 20 f's/OIV. Middle Trace: Oulpul2V10iv.
Bottom Trace: Capacilor 2V/Oiv.
RA = 9.1 kn
C = 0.01 f'F
FIGURE 7. Frequency Divider

TLlH17851-9
Top Trace: Oulpul SVlOiv.
Vee = SV
TIME = 20 f's/OIV. Bottom Trace: Capacilor Vollage 1V/Oiv.
RA = 3.9 kn
Rs = 3 kn
C := 0.Q1 f'F
FIGURE 5. Astable Waveforms
The charge time (output high) is given by:

PULSE WIDTH MODULATOR
When the timer is connected in the monostable mode and
triggered with a continuous pulse train, the output pulse
width can be modulated by a signal applied to pin 5. Figure
8 shows the circuit, and in Figure 9 are some waveform
examples.

tl = 0.693 (RA + Rs) C
And the discharge time (output low) by:
t2 = 0.693 (Rs) C
Thus the total period is:

The duty cycle is:
100
10
~

~

w

'"'z
==
U
~

1
0.1

'"'

TRIGGER 0-- 2

i

0.1

THRESHOLD

SJC

1

~
TLlH/7851-12

FIGURE 8. Pulse Width Modulator

.....,

V

\'\\~~

0.001

DISCHARGE

MODULATION

Rs
RA + 2Rs

IR. ! 2R.)

6

R.

~UT

OUTPUT(>-- 3

~"\~~~~oQ)..~~

0.01

7

LM555

'\ '\ '\
'\ '\ '\ '\

5
I

=

~

B

4

T = tl + t2 = 0.693 (RA +2Rs) C
The frequency of oscillation is:
1.44
f =.!.. =
T
(RA + 2 RS) C
Figure 6 may be used for quick determination of these RC
values.
D

+Vcc

I

i'-

'\ '\ '\ '\

r n 11 n n n

lk 10k lOOk
1 10 100
f - FREE·RUNNING FREQUENCY (Hz)

I
I

TLlHI7851-10
FIGURE 6. Free Running Frequency

I
I

II
II

II
II

II
II

TLlH/7851-13

Top Trace: Modulation 1V10iv.
vee = SV
TIME = 0.2 ms/OIV. Bottom Trace: Capacilor Vollage 2V/Oiv.
RA=9.1kn
C = 0.01 f'F
FIGURE 9. Pulse Width Modulator

FREQUENCY DIVIDER
The monostable circuit of Figure 1 can be used as a fre·
quency divider by adjusting the length of the timing cycle.
Figure 7 shows the waveforms generated in a divide by
three circuit.

PULSE POSITION MODULATOR
This application uses the timer connected for astable opera·
tion, as in Figure 10, with a modulating signal again applied
to the control voltage terminal. The pulse position varies
with the modulating signal, since the threshold voltage and
hence the time delay is varied. Figure 11 shows the wave·
forms generated for a triangle wave modulation signal.

5-43

II

Applications Information

(Continued)

r-__.._....,;v.::cc::....._. ._~t--o +Vcc

r--~""----~t--o +Vcc

Rt
TRIGGER

R.
LM555

R2
MODULATION

OUTPUT

OUTPUT

TLlH17851-16

TL/H17851-14

FIGURE 12

FIGURE 10. Pulse Position Modulator

Figure 13 shows waveforms generated by the linear ramp.
The time interval is given by:

T = 2/3 Vee RE (R, + R2) C
R, Vee - VSE (R, + R2)
VSE '" 0.6V

r

I
..J
Vce = 5V
TIME = 0.1 ms/DIV.
RA = 3.9 kO
Rs = 3 kO
C = 0.01 I'F

U

.-

r

TL/H/7851-15
Top Trace: Modulation Input 1V1Div.
Bottom Trace: Output 2V IDiv.

./
V

FIGURE 11. Pulse Position Modulator

./

LINEAR RAMP

V

-

./

TLlHI7B5t-17
Vee = 5V
Top Trace: Input 3V1Div.
TIME = 20 I's/DIV. Middle Trace: Output 5VIDlv.
Rt = 47 kO
Bottom Trace: Capacitor Voltage lV/Div.
R2 = 100kO
RE = 2.7 kO
C = O.Ot I'F

When the pullup resistor, RA, in the monostable circuit is
replaced by a constant current source, a linear ramp is generated. Figure 12 shows a circuit configuration that will perform this function.

FIGURE 13. Linear Ramp
50% DUTY CYCLE OSCILLATOR
For a 50% duty cycle, the resistors RA and Rs may be
connected as in Figure 14. The time period for the out-

5-44

Applications Information

r
3:

(Continued)

put high is the same as previous, t1 = 0.693 RA C. For the
output low it is t2 =
[(RA R8)/(RA

+ R8)] CLn

[=~A-_2::]

ADDITIONAL INFORMATION
Adequate power supply bypassing is necessary to protect
associated circuitry. Minimum recommended is 0.1 fLF in
parallel with 1 fLF electrolytic.

Thus the frequency of oscillation is f = _1_
t1 + t2

Ir---...------t..--o

I

+vee

Lower comparator storage time can be as long as 10 fLs
when pin 2 is driven fully to ground for triggering. This limits
the monostable pulse width to 10 fLs minimum.

~~
51k

Re
22k

Delay time reset to output is 0.47 fLs typical. Minimum reset
pulse width must be 0.3 fLs, typical.
Pin 7 current switches within 30 ns of the output (pin 3)
voltage.

11--+-.M"......

'--- 2

LM555

Note that this circuit will not oscillate if R8 is greater than
1/2 RA because the junction of RA and R8 cannot bring pin
2 down to 1/3 Vee and trigger the lower comparator.

61-. .- -....

OUTPUT 0-- 3

TL/H/7851-18

FIGURE 14.50% Duty Cycle Oscillator

5-45

U1
U1
U1

......
r

3:

U1
U1

~

o ,------------------------------------------------------------------,
CD

:g ~ National

PRELIMINARY

Semiconductor
Corporation

:::i

:::::!
CD

II)
II)

:l LM556/LM556C Dual Timer
•
•
•
•
•

General Description
The LM556 Dual timing circuit is a highly stable controller
capable of producing accurate time delays or oscillation.
The 556 is a dual 555. Timing is provided by an external
resistor and capacitor for each timing function. The two timers operate independently of each other sharing only Vee
and ground. The circuits may be triggered and reset on failing waveforms. The output structures may sink or source
200 mAo

Applications
•
•
•
•
•
•
•

Features
•
•
•
•

Adjustable duty cycle
Output can source or sink 200 mA
Output and supply TTL compatible
Temperature stability better than 0.005% per ·C
Normally on and normally off output

Direct replacement for SE556/NE556
Timing from microseconds through hours
Operates in both astable and monostable modes
Replaces two 555 timers

Precision timing
Pulse generation
Sequential timing
Time delay generation
Pulse width modulation
Pulse position modulation
Linear ramp generator

Schematic Diagram
1141

v"o-------~~~------~------~----------------------._----~~~----,

022

Rl1
62k

RJ

"

R6

'"

12 1J Vccl

R.

CONTROL
VOL lAGE (3,11)
GNo

"

15,91
OUTPUT

f7I

TRIGGER
/6.B1

R'

"

TL/H17852-2

Connection Diagram
Dual-In-Line and Small Outline Packages
Vee

DISCHARGE

THRESH

CONTROL

OLD

VOL lAGE

Order Number LM556J or LM556CJ
See NS Package Number J14A

RESET

Order Number LM556CM
See NS Package Number M14A
Order Number LM556CN
See NS Package Number N14A

DISCHARGE THRESH
OLD

CONTROL

RESET

OUTPUT

VOLTAGE

lAlGGER

GND

TLlH17852-1

Top View
5-46

r-

s:

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

1785 mW
1620 mW

Operating Temperature Ranges
LM556C
LM556

Electrical Characteristics (TA =
Parameter

LM556C

LM556

Conditions

Supply Voltage

Timing Error, Monostable
Initial Accuracy
Drift with Temperature

215·C
220·C

25·C, Vee = + 5V to + 15V, unless otherwise specified)

Min

Supply Current
(Each Timer Section)

260·C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

O·Cto +70·C
-55·C to + 125·C

Typ

4.5
Vee = 5V, RL = 00
Vee = 15V, RL = 00
(Low State) (Note 2)

3
10

Max

Min

18

4.5

5
11

Typ

3
10

Units
Max
16

V

6
14

mA
mA

%

0.5
30

0.75
50

ppmrC

Accuracy over Temperature
Drift with Supply

1.5
0.05

1.5
0.1

%N

Timing Error, Astable
Initial Accuracy
Drift with Temperature
Accuracy over Temperature
Drift with Supply

1.5
90
2.5
0.15

2.25
150
3.0
0.30

Trigger Voltage

RA, Rs = 1k to 100k, C = 0.1 ",F,
(Note 3)

Vee = 15V
Vee = 5V

4.8
1.45

5
1.67

5.2
1.9

0.1

0.5

(Note 4)

0.4

0.5

1

Trigger Current
Reset Voltage
Reset Current
Threshold Current

VTH = V-Control (Note 5)
VTH = 11.2V

Control Voltage Level and
Threshold Voltage

Vee = 15V
Vee = 5V

9.6
2.9

Pin 1, 13 Leakage Output High
Pin 1, 13 Sat
Output Low
Output Low

(Note 6)
Vee = 15V, I = 15 mA
Vee = 4.5V, I = 4.5 mA

5-47

%

%
ppmrC

%

%N

4.5
1.25

5
1.67

5.5
2.0

V
V

0.2

1.0

",A

0.4

0.5

1

V

0.6

mA

0.1

0.4

0.1

0.03

0.1
250

0.03

0.1
250

",A
nA

10
3.33

10.4
3.8

10
3.33

11
4

V
V

1

100

1

100

nA

150
70

240
100

180
80

300
200

mV
mV

9
2.6

en
......

r-

Soldering Information
Dual-In-Line Package
Soldering (10 seconds)
Small Outline Package
Vapor phase (60 seconds)
Infrared (15 seconds)

+18V

Power Dissipation (Note 1)
LM556J, LM556CJ
LM556CN

-65·C to + 150·C

Storage Temperature Range

en
en

s:
en
en

en

o

u
CD
r.n
r.n

Electrical Characteristics (TA =

25'C, vcc =

+ 5V to + 15V, unless otherwise specified) (Continued)

:E
....I

.......
CD
r.n
r.n

:E

LM556

Conditions

Parameter

Min

Output Voltage Drop (Low)

....I

Output Voltage Drop (High)

Vcc = 15V
ISINK = 10 mA
ISINK = 50mA
ISINK = 100 mA
ISINK = 200 mA
Vcc = 5V
ISINK = BmA
ISINK = 5mA
ISOURCE = 200 mA, Vcc = 15V
ISOURCE = 100 mA, Vcc = 15V
Vce = 5V

13
3

LM556C

Typ

Max

0.1
0.4
2
2.5

0.15
0.5
2.25

0.1

0.25

12.5
13.3
3.3

Min

12.75
2.75

Units

Typ

Max

0.1
0.4
2
2.5

0.25
0.75
2.75

0.25

0.35

V
V
V
V
V
V

12.5
13.3
3.3

V
V
V

Rise Time of Output

100

100

ns

Fall Time of Output

100

100

ns

Matching Characteristics
Initial Timing Accuracy
Timing Drift with Temperature
Drift with Supply Voltage

(Note 7)
0.05
±10
0.1

0.2
0.2

0.1
±10
0.2

2.0

%
ppml'C

0.5

%/V

Note 1: For operating at elevated temperatures the device must be derated based on a + 150°C maximum junction temperature and a thermal resistance of
70'C/W (Ceramic), 77"C/W (Plastic DIP) and 11 rJ'C/W (SO·14 Narrow).

Note 2: Supply current when output high typically 1 mA less at Vee = 5V.
Note 3: Tested at Vce = 5V and Vee = 15V.
Note 4: As reset voltage lowers, timing is inhibited and then the output goes low.
Note 5: This will determine the maximum value of RA + RB for 15V operation. The maximum total (RA + RB) is 20 MU.
Note 6: No protection against excessive pin I, 13 current is necessary providing the package dissipation rating will not be exceeded.
Note 7: Matching characteristics refer to the difference between performance characteristics of each timer section.

Note 8: Refer to RETS556X drawing for specifications of military LM556J version.

5-4B

Typical Performance Characteristics

]

1.2
1.1
1.0

"

D.9
D.I

I;

i

w

~

Ie

!!i
!!i

i

Vee

II

High Output Voltage vs
Output Source Current

Supply Current vs Supply
Voltage (Each Section)

Minimum Pulse Width
Required for Triggering
12

2
1.8

10

1.6

15V

-SS~

T =+'25"C

0.1
0.8
0.5
0.4
0.3
0.2
0.1

T'

+~S!C

~~

T' -SS'C

0.2

0.3

0.4

~

./

I

J

0.8
0.6

10

SV~Vcc SISV

10

15

SUPPLY VOLTAGE IVI

10

100

'SOURCE (mA)

Low Output Voltage vs
Output Sink Current

Low Output Voltage vs
Output Sink Current

Low Output Voltage vs
Output Sink Current

j;;;

TA II +115"C

~

0.4
0.2

S

LOWEST VOLTAGE LEVEL OF TRIGGER PULSE IX Vccl

J.....-

TA • +25·C

1.4

S 1.2

~~ ~ +lZS'C

o
0.1

~L.,.o

~~+2S'C

f-i. !-~~'C

10

10
Vee = 5V

Vee" IOV

!=Vc< 'ISV

1

1.0

f-

+25"C

~1

~

r;.

11111111

1.0

- +125°C

~
S
~

-sS'C

+IZ5'C

f0.1

1--'+2S'C

~~

-tttt
10

0.01 ~
1.0

100

1,1

'SINK(mAI

>-

~

;g

..!:i~
II:

1000
Vee" 15V

+12S C
w

"" 1000

~

Vee" 5.0V

600

"co
z

..!:i

W

400

~

Vee -'OV. lSV

200

II I

0
0

0.1

0.2

It
co
II:

BO~

LOWEST VOLTAGE LEVEL OF TRIGOER PULSE IX Veel

+2~}Lz

600

/11/

400

i 55iC I
o

0.1

0.2

~

100

z

0:

;;

oS

'.'// f-n

200

o

0.3

'1

m·c-1.. ~

oS

>-

100

100
(mAl

Discharge Transistor
(Pin 1, 13)
Voltage vs Sink Current

1200

T =+25~C

1000

10
'SINK

Output Propagation Delay vs
Voltage Level of Trigger Pulse

1200

-SS'C

TllTI

~
1.0

100

ISlNK'mAI

Output Propagation Delay vs
Voltage Level of Trigger Pulse

g

0.01

10

ID

0.3

LOWEST VOLTAGE LEVEL OF TRIGGER PULSE IX Veel

}

10

1.0 LLUlJIILJ.jljllllL...llI.
0.01
0.1
1.0
10

100

ISINK (mA) PIN f.ll

Discharge Transistor (Pin 1, 13)
Voltage vs Sink Current

~

100

z

0:

;;-

oS

ISINK (mA) PIN 1.13

5-49

TLlH17852-3

ri:
en
en
en
.......
ri:
en
en

en

o

~

:8
:::is
~
II)

~ National

Semiconductor
Corporation

CD

II)

:l LM565/LM565C Phase Locked Loop
General Description
• Linear triangle wave with in phase zero crossings
available
• TTL and DTL compatible phase detector input and
square wave output
• Adjustable hold in range from ± 1% to > ± 60%

The LM565 and LM565C are general purpose phase locked
loops containing a stable, highly linear voltage controlled
oscillator for low distortion FM demodulation, and a double
balanced phase detector with good carrier suppression. The
vee frequency is set with an external resistor and capacitor, and a tuning range of 10:1 can be obtained with the
same capacitor. The characteristics of the closed loop system-bandwidth, response speed, capture and pull in
range-may be adjusted over a wide range with an external
resistor and capacitor. The loop may be broken between the
VCO and the phase detector for insertion of a digital frequency divider to obtain frequency multiplication.

Applications
• Data and tape synchronization
•
•
•
•
•
•
•
•
•
•

The LM565H is specified for operation over the - 55'C to
+ 125'C military temperature range. The LM565CH and
LM565CN are specified for operation over the O'C to
+ 70'C temperature range.

Features
• 200 ppm/'C frequency stability of the VCO
• Power supply range of ± 5 to ± 12 volts with
100 ppm/% typical
• 0.2% linearity of demodulated output

Modems
FSK demodulation
FM demodulation
Frequency synthesizer
Tone decoding
Frequency multiplication and division
SCA demodulators
Telemetry receivers
Signal regeneration
Coherent demodulators

Connection Diagrams
Dual-In-Llne Package

Metal Can Package

"vee

TIMING
RESISTOR

INPUT

NC

INPUT

NC

INPUT

NC

VCO
OUTPUT
PHASE COMPARATOR
VCO INPUT
REfERENCE
OUTPUT
VCO CONTROL
VOLTAGE

VCO CONTROL
VOLTAGE

INPUT

-Vee

PHASE COMPARATOR
VCO INPUT
TL/H/7B53-2

NC
+Vcc

TIMING
CAPACITOR
TIMING
RESISTOR
TL1H17B53-3

Order Number LM565CN
See NS Package Number N14A

Order Number LM565H or LM565CH
See NS Package Number H10C

5-50

r-

s::

Absolute Maximum Ratings

U1

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Operating Temperature Range
LM565H
LM565CH, LM565CN

- 55·C to + 125·C
O'Cto +70·C

Supply Voltage

Storage Temperature Range

- 65·C to + 150·C

±12V

Power Dissipation (Note 1)

1400mW

Differential Input Voltage

±1V

Electrical Characteristics AC Test Circuit, TA =
Parameter

25·C, Vee = ±6V
LM565

Conditions
Min

Power Supply Current

< V2, V3 < OV

Input Impedance (Pins 2, 3)

-4V

VCO Maximum Operating
Frequency

Co = 2.7pF

VCO Free-Running
Frequency

Co =1.5nF
Ro = 20k!l
fo = 10kHz

Max

8.0

12.5

10

300

500

-10

0

+10

Min

Triangle Wave Output Voltage

2

Triangle Wave Output Linearity
Square Wave Output Level

4.7

45

Square Wave Rise Time

1.0

2.4

3

5.4

kHz

-30

0

2

4.7

Square Wave Fall Time

40

VCO Sensitivity

fo = 10kHz

Demodulated Output Voltage
(Pin 7)

± 10% Frequency Deviation

Total Harmonic Distortion

± 10% Frequency Deviation

1

0.6

6600
250

Output Impedance (Pin 7)

300

400

0.2

0.75

200

3.5

DC Level (Pin 7)

4.25

Output Offset Voltage

val
val
30

AM Rejection
Phase Detector Sensitivity Ko

0.2

1.5

%/V

2.4

3

Vp-p

0.5

%

5.4

Vp.p

50

k!l
60

4.75

30

100

4.0

%
ns

50

ns

1

mA

6600

HzlV

300

450

0.2

1.5

3.5

4.5

%

ppml"C

20

50
0.6

+30

5
55

mA

500

20

Output Current Sink (Pin 4)

12.5

-200

0.1

50

8.0

250

5

Square Wave Duty Cycle

Max

k!l

0.2

Output Impedance (Pin 4)

Units

Typ

5

-100

Frequency Drift with
Supply Voltage

Temperature Drift of IV7 -

LM565C

Typ

7

Operating Frequency
Temperature Coefficient

IV7 -

260·C

Lead Temperature (Soldering, 10 sec.)

mVp_p
%
k!l

4.5

5.0

V

50

200

mV

500

500

40

40

p.V/'C
dB

.68

.68

V/radian

Note 1: The maximum junction temperature of the LMS6S and LMS6SC is + lSO"C. For operation at elevated temperatures. devices In the TO·S package must be

derated based on a thermal resistance of +ISO"C/W junction to ambient or +4S'C/W iunction to case. Thermal resistance of lhe dual·in·line package is
+8S·C/W.

5·51

en
U1
.......
r-

s::

U1

en

U1

o

Typical Performance Characteristics
Power Supply Current as a
Function of Supply Voltage
TA -25°C

1
i;

a:
=
- -

8

~

/

~ 10

~

~!

5"'
SE

.......

.-

0

2

..

./ .......
./

6
4

TA-,...

..lu

01""""" ~

. ...,3012 h

./2

Vcc· :!:&V

ii-

t;

-c-

TA - 25°'~1I
1111
1111
1111

160

I

TA'25°C

~

"'

J

Or....-

dV

...i~

3.0'0

60

I

~

-

s

'-

~~l.Dfo ;=
;;::::

I

-

l!i

r-

"'

c'-

100

~

r-

rc'-

It

Vee =:t:6V

2.0

f 1.a

co
! 0.5

I........ i'o.

r---. I'....

~-u

!!-2.D

:=
0.6

0.6
1.0
1.2
IA
NORMALIZED FREQUENCY

"'c~

-50 -25 0 Ii 50 76 100 126
TEMPERATURE I'C)

Hold in Range as a
Function of R6-7
Vee" z8V
T.-2rc

+1.0

,;:

~

111
II ..
III ['I.,.

I

,;

r'10k

1M

e 1.5
-0.&
~ -1.0

a

crc-

ffi
,.

1~~'~~r~1

lOOt
10k
FREIlUENCY IHIl

t;

co

'J

"

It

VCO Frequency as a
Function of Temperature

g

~

Vee· :!:&V

,

100

~,.

T. - 25~C'

Sz.a •• -

i~lI- D.l.F
lk

.."'W a

Loop Gain vs Load
Resistance

~
z

1=

~

60

m 4D
t:: 2t
iii 0

.),9V

Vcc=:!:12V/..

120
c 100

5.12

"'iii

10
100
1
lOBO
PEAK TO PEAK INPUT VOLTAGE ImVI

~

C-1OUpF

o

Vee II :t12V

S
Phase Shift vs Frequency
cliO

Ircc~dV
T... ·2S·C

~"Dk

lUI

1.1

E 140

I

..'"

§

Ti '1215:~1

~

ii"'

r....... V

l"'- I""'-

0

~1.3

c

z

Vcc =±8V

-1.0

ill

12 14 16 16 20 22 24 26
TOTAL SUHLY VOLTAGE IVI

+1.0

>-

~il!

-

Oscillator Output
Waveforms

c

~S'

Rl - 10k

'/
//
'/
10

....

91.4

/

~

a:

i

./

-Rl-~

VCO Frequency
lOOk

1111
~ 1.S-

:5!
"'1.5l:!
-

/

15

Lock Range as a Function
of Input Voltage

:=

.
..S

~

0

>
I;

lOOk

8dCi!ldlil:iD
n~;.N!

-"'r'"j'" I
-1.0

ro...llll
l'\ II
'I

I I
0.2

o.a

1.0
1.4
1.6
RELATIVE FREE RUNNING VCO FREQUENCY.

RESISTANCE BEtwEEN PINS 6 AND 71111

TLlHI7B53-4

5-52

en
n
:::T
CD

REFERENCE
OUTPUT

veo
CDNTROl
VOLTAGE

3

veo

TIMING
RESISTOR

...

OUTPUT

I»

(;'

R9
5.7k

Rl

RIO

R22

1.75k

4.3k

R2
7.2k

7.2k

c

iii'
cc

;

A21
16k

3

035

Rll
3.Bk

R26
B.4k

&:

'"

03&

R7
13k

RB
B.lk

R25
2.6k

~o)
"3
200

I

A24
5.Bk

A23
4.Bk

I, I

A5
2.4k

-Vee

TLIHI7B53-1

~S9SIlll'/S9SIlll'

iii

o
an

CD

an
:E
-'
.....
an
CD
an
:E
-'

AC Test Circuit
..v

--lf-"-I

J'."

SA~~~~~o-_ _ _ _ _ _ _ _ _

INPUT
(fREQUENCY..........J

MODULATED ~
SIGNAl)

499k

'-4t-+---<
I'"

>..::..4j.....-o VO:(TS:~E
(V,-Vsl
DEMODULATED
OUTPUT

499k

30pF

""*,
snUARE WAVE
OUTPUT

TLlH/7853-5

Note: 5, open for output offset voltage (V7 - V6) measurement.

Typical Applications
2400 Hz Synchronous AM Demodulator
+15V

33k

DEMODULATED
OUTPUT

'8k

ljlF~

oak
5\0

m

."
'jlF~

Uk

O.hF

TL/H17853-6

5-54

r

s:

Typical Applications (Continued)

(1'1

en
~
r

FSK Demodulator (2025-2225 cps)
+12V

s:
(1'1

en
(1'1

10k

o

2k

OUTPUT TO
PRINTER
MAGNET
DRIVER

Tl/H17853-7

FSK Demodulator with DC Restoration
+24V

820

'""" 5D$JF
15k

10k

..L

50~V

15V
2DOII:

r,. .

2k

OUTPUT TO
PRINTER
MAGNET
DRIVER

4.711:

5/JF

10k

Tl/H/7853-8

5-55

Typical Applications

(Continued)

Frequency Multiplier (X 10)

+6V

100nF

f'NPUT= 10kHz

o-J I-....- - - - {

t---E--------ofOUTPUT= 100kHz

9

8

MM74C90

'-----o+6V

TL/HI7BS3-9

IRIG Channel 13 Demodulator

..

r----~

-t~--------t.----~-_()+6V

.01

470k

lN~ I-~-t---{

OUTPUT

47k

-t______..__

L-_____________________________

~-6V

TL/HI7BS3-10

5-56

r

Applications Information
In designing with phase locked loops such as the LM565,
the important parameters of interest are:

The natural bandwidth of the closed loop response may be
found from:

FREE RUNNING FREQUENCY
f

=~
RcCo
Associated with this is a damping factor:

... ( radians! sec)
.
Ko = oscillator sensitivity
volt

vo~ts )

radian

The loop gain of the LM565 is dependent on supply voltage,
and may be found from:
Ko Ko = 33.6 fo
Vc
fo = VCO frequency in Hz

J...~

f n-

21T

KoKo
7, + 72

7, + 72 = (Rl +R2) Cl
R2 is selected to produce a desired damping factor 8, usually between 0.5 and 1.0. The damping factor is found from
the approximation:

Vc = total supply voltage to circuit
Loop gain may be reduced by connecting a resistor between pins 6 and 7; this reduces the load impedance on the
output amplifier and hence the loop gain.

8 ::::;

1T

72fn

These two equations are plotted for convenience.
Filter Time Constant vs Natural Frequency

HOLD IN RANGE: the range of frequencies that the loop will
remain in lock after initially being locked.
fH=

~~R,Cl~oKo

8 =

For narrow band applications where a narrow noise bandwidth is desired, such as applications involving tracking a
slowly varying carrier, a lead lag filter should be used. In
general, if 1!R,C, < Ko Ko, the damping factor for the loop
becomes quite small resulting in large overshoot and possible instability in the transient response of the loop. In this
case, the natural frequency of the loop may be found from

(...!...)
sec

Ko = phase detector sensitivity (

111"

8fo

±-

Vc
fo = free running frequency of VCO

THE LOOP FILTER
In almost all applications, it will be desirable to filter the
signal at the output of the phase detector (pin 7); this filter
may take one of two forms:

10'

Simple Lag Filter

10'

(~~~)

~

....

10"

RAD
SEC

10·

Vc = total supply voltage to the circuit

~

-It ....

....

~2
10-4

10

10"

10-'
T,

....
10-'

....
....
10

+ T2 (sec)
TLlH/7853-13

CI

HI = 3.Bk

~E

103

_--'"""11....-0 tVee

Damping Time Constant vs Natural Frequency

111"
LM565

~~ :D:~I~NG

TL/H17853-11

10" ~~

Lag-Lead Filter

r----__

~--~-()+vec

I-I--

10

102

C2
RI

=

......
r

3:
(J1
en
(J1

o

0-

LOOP GAIN: relates the amount of phase change between
the input signal and the VCO signal for a shift in input signal
frequency (assuming the loop remains in lock). In servo theory, this is called the "velocity error coefficient."
Loop gain = KoKo

3:
(J1
en
(J1

1\1 = 21

~

~ ~l1'

3.Bk

LM565

IIIIINI

10'
10-4

TLlH17853-12

A simple lag filter may be used for wide closed loop bandwidth applications such as modulation following where the
frequency deviation of the carrier is fairly high (greater than
10%), or where wideband modulating signals must be followed.

Ii

10'"

10"

10-'
TLlH/7853-14

Capacitor C2 should be much smaller than Cl since its function is to provide filtering of carrier. In general C2 s;; 0.1 C,.

5-57

~ Semiconductor
NatiOnal

Corporation

LM566C Voltage Controlled Oscillator
•
•
•
•

General Description
The LM566CN is a general purpose voltage controlled oscillator which may be used to generate square and triangular
waves, the frequency of which is a very linear function of a
control voltage. The frequency is also a function of an external resistor and capacitor.

High temperature stability
Excellent supply voltage rejection
10 to 1 frequency range with fixed capacitor
Frequency programmable by means of current, voltage,
resistor or capacitor

Applications

The LM566CN is specified for operation over the O·C to
+ 70·C temperature range.

• FM modulation

• Wide supply voltage range: 10V to 24V
• Very linear modulation characteristics

•
•
•
•

Connection Diagram

Typical Application

Features

Dual·ln·Line Package
GND

1

Signal generation
Function generation
Frequency shift keying
Tone generation

1 kHz and 10 kHz TTL Compatible
Voltage Controlled Oscillator
6V

8 Vee

7 TIMING CAPACITOR

SOU ARE WAVE
OUTPUT

6 TIMING RESISTOR

TRIANGLE
WAVE OUTPUT

MODULATION
INPUT

IOkD.~lt.7rE47nF
4.71cA

,"

2N2222

-"

L-__________

TLlHI7854-2

Order Number LM566CN
See NS Package Number N08E

-3VFOR 1kHz
-W for 10kHz

CON1R01.

-o~~~

3V TO 5.5V

~~----------------~g~~~
0IJ11'UT
'------;;;....--------------------o~
"c:'PATBLE
1IU1PUl
TL/H17854-3

5-58

r

:s::
U1

Absolute Maximum Ratings

en
en

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office!
Distributors for availability and specifications.
Power Supply Voltage
Power Dissipation (Note 1)
Operating Temperature Range, LM566CN

26V
1000 mW
O'C to + 70'C

Lead Temperature (Soldering, 10 sec.)

+ 260'C

Electrical Characteristics Vee =
Parameter

o

12V, TA = 25'C, AC Test Circuit
LM566C

Conditions
Min

Typ

Maximum Operating
Frequency

RO = 2k
CO = 2.7 pF

0.5

1

VCO Free-Running
Frequency

Co = 1.5 nF
Ro = 20k
fO = 10kHz

-30

0

% Vee

Input Voltage Range Pin 5
Average Temperature Coefficient
of Operating Frequency
Supply Voltage Rejection

Units
Max
MHz

+30
Vee

200
10-20V

0.1

Input Impedance Pin 5
VCO Sensitivity

For Pin 5, From
a-10V, fo = 10 kHz

FM Distortion

± 10% Deviation

ppml"C
2

0.5

1

6.0

6.6

7.2

0.2

1.5

Maximum Sweep Rate

%

%/V
Mn

1

kHz/V
%
MHz

10:1

Sweep Range
Output Impedance
Pin 3

50

Pin4

n
Vp-p

Square Wave Output Level

RLl = 10k

5.0

5.4

Triangle Wave Output Level

RL2 = 10k

2.0

2.4

40

50

Square Wave Duty Cycle

n

50

Vp-p
60

%

Square Wave Rise Time

20

ns

Square Wave Fall Time

50

ns

0.5

%

Triangle Wave Linearity

+ 1V Segment at

% Vee

Note 1: The maximum junction temperature of the LM566CN is 150"C. For operation at elevated junction temperatures, maximum power dissipation must be

derated based on a thermal resistance of 115'C/W, iunction to ambient

Applications Information
A 0.001 ,.,.F capacitor is connected between pins 5 and 6 to
prevent parasitic oscillations that may occur during VCO
switching.

The LM566CN may be operated from either a single supply
as shown in this test circuit, or from a split (±) power supply. When operating from a split supply, the square wave
output (pin 3) is TTL compatible (2 rnA current sink) with the
addition of a 4.7 kn resistor from pin 3 to ground.

fo=

_2._4('--V_+_----,'VS"'-)
RoCoV+

where
2K < RO < 20K
and Vs is voltage between pin 5 and pin 1.

5-59

LM566C

tn

MODULATION
INPUT

TIMING
RESISTOR

TIMING
CAPACITOR

n

::r

SQUARE WAVE

Vee

CD

OUTPUT

3

!.
(;'

RI5

c

4.3K

i'

CQ

D;

3

'f'
~
TRIANGLE
WAVE

OUTPUT

R4

lK
GND

'.

• •

•

••••
TUHI7854-1

.;:

Typical Performance Characteristics
Operating Frequency as a
Function of Timing Resistor
llIOK

.Iii

,

10

TA "2S"C
AC TEST CIR CUlT

;;;

~

UK
1.0

I

10

ID

III'

NORMALIZED FREQUENCY

Power Supply Current

.

II

§

2.5
2.0
1.1

~

1.0

!

1::
"
::l

RI -4K
fA =25"C

z

-1.0

~

-1.1

21

;~>

~,,-

~cE

iO
....

....
~

z

~
~

+6

iOE
a

21 50

.
..
..
....
..~
z

~

AC TEST CIRCUIT
T.-ZI··C
RLI '" 10K

I

4.0

l;!

10

10k

Ik

100

loa

Ru PIN 410 GROUND (U)

10k

Ik

Ret PIN no GROUND (Ill
TL/H/7854-4

AC Test Circuit
12V

/

2.J

I
I

z.z

>
....

i

""

/

5.0

>

2.4

...~

T... "25"C

~

!;;

-0.1
-0.8
10k

ACTEST CIRC ulf'

6.0

0:

./

Triangle Wave Output
Characteristics

~

""Square Wave Output
Characteristics

~

-0.8

RI.I PIN l TO GROUND tu)

"J

z.

J.O

a -0.5

Ik

r-r-

+8

t

0

~

3.0

I/L"\,.
1/
1\../ 1 1\..1/1

r--

J5 lao IZ5

ffi -0.4

"

2.5

+4

t -0.3

+4

z.o

1.5

TA " 25"C
AC TEST CIRCUIT

+12

;5~ +10
~S~ +8

: -0.1
~ -0.2

1110

+4

Frequency Stability vs Load
Impedance (Triangle Output)

§

Ru= 10K

+Z

/""\.

+5

>

+0.2
+0.1

AC TEST CIRCUIT
14 =25"C

1::

~

+6

TEMPERATURE rCI

Frequency Stability vs Load
Resistance (Square Wave
Output)

I.D

VCO Waveforms

6;:

SUPPLV VOLTAGE (VI

§

.5

~

-2.1
-Ji -50 -25

I

+8

,I

CONTROL VOLTAGE IY,-Vsl(Y)

-2.0

AC TEST, CiRCU1
ZO

1/

.5

III"

-G.I

~

~

IS

lOS

~

....

10

10

10'

+.1

:::

TVPlCAL

i:l

~z

Temperature Stability

MAXIMUM

~

III'

V'

II

FREQUENCY tHd

20

c

1.0

V

1\

.DOOI
0.1

~

.

Normalized Frequency as a
Function of Control Voltage
TA ,.25"C
AC TEST CIRCUIT

1.5

o

::l

"r\.

.001

z.o

~

~

"r-....

.01

!i

'"

S

u

'I\.

.1

z
~

13

oS

AC TEST CIRCUIT

u

10K

..

TA=25"C

['I,.

~

1<
z

en
en

Operating Frequency as a
Function of Timing Capacitor

:5
u

UI

2.1

II

10k.o.
1.5k.o.

AC TEST CIRCUIT

l;!

T... -25°C

SQUARE~P-----"lK

Z.O

WAVE OUTPUT

1110

Ik

10k

R" PIN 4 TO GROUND In)
TL/H/7854-5

lOkll

TL/H/7854-6

5-61

ur------------------------------------------------------------------.
.....
:8 ~ National

:E

~

Semiconductor
Corporation

CD

Il)

:5

LM567/LM567C Tone Oec.oder
General Description
The LM567 and LM567C are general purpose tone decoders designed to provide a saturated transistor switch to
ground when an input signal is present within the passband.
The circuit consists of an I and Q detector driven by a voltage controlled oscillator which determines the center frequency of the decoder. External components are used to
independently set center frequency, bandwidth and output
delay.

Features
• 20 to 1 frequency range with an external resistor
• Logic compatible output with 100 mA current sinking
capability

•
•
•
•
•

Bandwidth adjustable from 0 to 14%
High rejection of out of band signals and noise
Immunity to false signals
Highly stable center frequency
Center frequency adjustable from 0.01 Hz to 500 kHz

Applications
•
•
•
•
•
•
•

Touch tone decoding
Precision oscillator
Frequency monitoring and control
Wide band FSK demodulation
Ultrasonic controls
Carrier current remote controls
Communications paging decoders

Connection Diagrams
Metal Can Package

Dual-In-Llne and Small Outline Packages

OUTPUT
OUTPUT ....;,1+-_ _ _-..1
Fll TER
lOOP

2

Fll TER -+-If-....,

GNO

TIMING
CAPACITOR

INPUT

5 TIMING
RESISTOR

TL/H/6975-1

Top View

TL/H/6975-2

Top View

Order Number LM567H or LM567CH
See NS Package Number H08C

Order Number LM567CM
See NS Package Number M08A
Order Number LM567CN
See NS Package Number N08E

5-62

r-

s::

Absolute Maximum Ratings

UI
Q)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Officel
Distributors for availability and specifications.
Supply Voltage Pin

Soldering Information
Dual-In-Line Package
Soldering (10 sec.)
Small Outline Package
Vapor Phase (60 sec.)
Infrared (15 sec.)

9V

Power Dissipation (Note 1)

1100mW

Va

15V

V3

-10V
-65'Cto + 150'C

Operating Temperature Range
LM567H
LM567CH, LM567CM, LM567CN

-55'C to + 125'C
O'Cto +70'C

Electrical Characteristics AC Test Circuit, TA = 25'C, V+ =
Parameters
Power Supply Voltage Range
RL

=

20k

Power Supply Current
Activated

RL

=

20k

Input Resistance
Smallest Detectable Input Voltage
Largest No Output Input Voltage

= fa
100 mA, fi = fa

Bn

=

Max

Min

Typ

Max

4.75

5.0

9.0

4.75

5.0

9.0

V

6

8

7

10

mA

11

13

12

15

mA

25

mVrms

10

140 kHz
12

Largest Detection Bandwidth Skew
Largest Detection Bandwidth Variation with
Temperature
Largest Detection Bandwidth Variation with
Supply Voltage

25

4.75 - 6.75V
100

Center Frequency Shift with Supply Voltage 4.75V - 6.75V
4.75V - 9V

mVrms

6

6

dB

-6

-6

dB

10

14

16

1

2

10

±2

500

Output Saturation Voltage

ei
ei

= 15V
= 25 mV, Ie =
= 25mV,la =

30 mA
100mA

Output Fall Time

18

% offo

2

3

%offo

±1
100

1.0
2.0

fo/20
Va

14

±O.1

35 ± 60
35 ± 140
0.5

Fastest ON-OFF Cycling Rate
Output Leakage Current

k!l

15

15

±1

0

+V=515V

u

'"
~

1.0

~

0.5

'"

0

!

'"
:!!

0

'"

~

,.

'\

~

!

-1.0

12

10

10

~

-so

-25

0

25

so

5.0
4
2

TEMPERATURE I'CI

g
>

'"
~

r-- .......

~

'"

~

'"
'"

300

-2.5

-5

1>
oS
~

~

.,

~
~

-1.5

2SO

0

25

50

a

100

50

15 100 125

~

10'

==, ,

,suI'!
.3~

10'

1

10'
0

2

a

!!

!!

;;

•

N

-

:1-

TA

5'"

V '"

-0.5

4

6

8

~

10

::!

12

I.-at

14

-15 -50 -25

~
~ ~ ........

~

12

BANDWIDTH (% OF fo)

i
>

10

~

5
0

" "

:;'"
~
'"
:iI

5
TA

,.

0
100

10k

1M

tOOk

Greatest Number of Cycles
Before Output

100

I
~

Vee = sv
TA - 2S'C

BAN~W~H

~ '\

LIMITED BY C2

BANDWIDTH LIMITED BY
EXTERNAL RESISTOR
' - (MINIMUM C2)

SO
lO

'\.

20

f\.

10

• •

7

= 2S'C

Vee ,5V

300
200

V

6

100 125

"

10

soo

./

5

so 15

Largest Detection Bandwidth

1000

.-V ~\SCEN1 CUR~ENT

•

25

CENTER FREOUENCV IHII

V
V

0

:;;

16

J J

15

r-

-1.5

15

0

~

TA = 2s'cL
NO LOAD "ON" CURRENV

20

-

V

-1.0

Typical Supply Current vs
Supply Voltage

= ,S'C

~

:!

" ;; r-

-NOOU"UT

25

;;:

10

J J ..

11/ ~ ~
.,~ ~
.-. 1/. .- ~J~~~~~:::~~~i~~~

oS

• , •

'"
'"

1.

l

5

10

2030 50

100

BANDWIDTH (% OF fo)

SUPPLY VOLTAGE IVI

Typical Output Voltage vs
Temperature
1.0
0.'

~

'"0:
'"

~
~
~

0

-v~,.lv

0.'
0.1
0.6

-

I
I
I

--rI

0.4
O.l

0.2

V

~ k:: Il = 100mA-::iIfII' ~ f -

0.5

I

....

IL "'lOmA

0.1
0

-75 -50 -25

0

25

'"

50 75 100 125

TEMPERATURE C'CI

TL/H/6975-4

5-65

r-

s::

(II

en

o

TEMPERATURE I'CI

!!

I / VV

vee -;;-S-v

~~
i

I

BANDWIDTH (%OF fol

Detection Bandwidth as a
Function of C2 and C3

I,

15 100125

so

I J

150

TEMPERATURE C'CI

10'

25

:t-:: : t-:

•

~
0
2

-10

-15 -so -25

0

200

~

'"~"

0

Bandwidth vs Input Signal
Amplitude
!!

2.5
0

05

'"

TEMPERATURE I'CI

Typical Frequency Drift with
Temperature (Mean and S.D.)
+V = 7 av 11)

5

u

~

-

6

0
-15 -so -25

15 100 125

~

.......
......

.......

-+V=4.15V

1.0

~

BANDWIDTH AT 25·C

-75

Typical Frequency Drift with
(Mean and S.D.) Temperature
1.5

>

•

1.5

2.5

-15

g
u

12.5

0

~
~

~

Typical Bandwidth Variation
with Temperature

:!

.....
1/

-0.5

en

:;;

~

i

15

(II

Typical Applications
Touch-Tone Decoder
+
RJ
0.5 ~F

+

0.5~F

05mfd

100-200 mV,ms

+

0.5~F

1"~1'

+
1.. _ _ _ -'I
DM5401

0.5~F

***

+
Component values (typ)
Rl 6.8 to 15k
R2 4.7k
R3 20k
Cl 0.10 mfd
C2 1.0 mfd 6V
C3 2.2 mfd 6V
C4 250 mfd 6V

0.5 ~F

1'1'*,

+

TLlH/6975-5

5-66

Typical Applications

(Continued)

Oscillator with Quadrature Output

Oscillator with Double Frequency Output
+

+

~9D

LM567

..nnnfZlo

LM561

L..fL
RL >TOOOO

RT

-reT
Connect Pin 3 to 2.8V to Invert Output

TLIH16975-6

TLIH16975-7

Precision Oscillator Drive 100 mA Loads

+

LM561

veo
TERMINAL
(+6%)

TLIHI6975-B

AC Test Circuit

Applications Information
The center frequency of the tone decoder is equal to the
free running frequency of the VCO. This is given by

5V

T

RI
2.4K

1
fo " " - - 1.1 R1Cl
The bandwidth of the filter may be found from the approximation

CI"
.0033

BW = 1070

~foVci 2

in % of fo

Where:
4

Vi = Input voltage (volts rms), Vi
C2 = Capacitance at Pin 2 (fJoF)

TTT
c;
C;

SIGNAL +5V
INPUT
TLIH16975-9

Ii = 100kHz + 5V
'Note: Adjust Iorio = 100kHz.

5-67

S;

200 mV

~

g

:i
..J

,----------------------------------------------------------------------------,
~ National

Semiconductor
Corporation

LM903 Fluid Level Detector
General Description

Features

The LM903 uses the thermal-resistive probe technique to
measure the level of nonflammable fluids. A low fluid level is
indicated by a warning lamp operating in continuous or
flashing mode. All supervisory requirements to control the
thermal-resistive probe, including short and open circuit
probe detection, are incorporated within the device. The circuit has possible applications in the detection of hydraulic
fluid, oil level, etc., and may be used with partially conducting fluids.

•
•
•
•
•
•
•
•
•
•

Flashing or continuous warning indication
Warning threshold externally adjustable
Control circuitry for thermal-resistive probe
Switch on reset and delay to avoid transients
600 mA flashing lamp drive capability
Short and open circuit probe detection
70V transient protection on supply and control input
7V-18V supply range
Internally regulated supply
-40·C to +80·C operation

Connection Diagram
Dual·ln·Line Package

MEAS INPUT....!.

•

U

16

I - MEAS REFV
15
I - MEMORYC

MEAS GND2.

14

I - AUX OUTPUT

PROBE I REF.2.
PNP BASE-!

13
I - RAMPR

.....2.

12
I - RAMP C

PROBE

SUPPLY..!

11
I-V REG

..!..

~OSCC

START INPUT

8

9

GND-

I - LAMP DRIVER
TOP VIEW

Order Number LM903N
See NS Package Number N16E

5-68

TL/H/5699-1

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, Vee

18V

Control Input Voltage (Pin 7)

18V

Transient Voltage (Pins, 6, 7, 9) 10 ms (Note 1)

Operating Temperature Range

-40'Cto +85'C

Storage Temperature

-55'C to + 150'C

Maximum Junction Temperature

+150'C

Lead Temperature (Soldering, 10 sec.)

260'C

70V

Output Current (Pin 4) 14 (Sink)

10mA

Electrical Characteristics
Vee

= 12V, CT = 33 ,.,.F, RT = 7.5 kO, TA within operating range except where stated otherwise

Symbol

Parameter

Tested Limits
(Note 2)

Conditions

Min
Vee

Supply Voltage

Is

Supply Current

VREG

7.0

Max

Min

Typ

18

7.0

13

50

Regulated Voltage
Regulation
Temperature Drift

Design Limits
(Note 3)

5.5
Vee

= 7.2V-18V

6.2

5.3

5.8

Units
Max
18

V

50

mA

6.3

105

V
mV
,.,.VI'C

500

Va-V3

Probe Current
Reference Voltage

2.0

2.35

1.95

2.20

2.40

V

VREF

Measurement Reference Voltage

790

900

780

850

910

mV

RREF

Reference Input Resistor

V7

Start Input Logic High Level

V7

Start Input Logic Low Level

17

High Input Current

Latch Off

17

Latch Holding Current

Latch On

2.5

nA

R7

Resistance Pin 7

Latch On

22

kO

112

Ramp Current

See Timing Diagram

Charging

V12
V12

= OV-1V
= 1V-4V

V12

= 4.1V

V12

= 0.5V

V
1.0

V

100

nA

600

1100

590

1100

,.,.A

53

93

50

96

,.,.A

-700

-450

-710

-440

,.,.A

-650

-400

-660

-390

,.,.A

Probe Current Start

570

850

550

710

870

mV

First Measurement

910

1200

890

1055

1220

mV

Second Measurement

910

1240

890

1080

1270

mV

VREG-1.0

V

Discharging

V12

kO

1.2
1.6

Ramp Threshold

See Timing Diagram

= 7.5V-18V

V1

Probe Input Voltage Range

Vee

V5

Probe Open-Circuit Threshold

At Pin 5

V5

Probe Short-Circuit Threshold

11

Pin 1 Input Leakage Current

Pin 1

115

Pin 15 Leakage Current

V15

Pin 15 Charging Current

1

V

VREG-0.85 VREG-0.6
0.6

= 300 mV

= 2V, V7 = 12V

f9

Lamp Oscillation Frequency

= 4V, V7 = 12V
CL = 3.3,.,.F

19

Lamp Driver Current

Flashing Mode

V9

Lamp Driver Saturation

19

V15

= 200 rnA

-3.5

+3.5

-3.5

3.5

+5.0

V
nA
,.,.A

60

,.,.A
0.5

200
5-69

0.85

1.5

2.5

Hz

600

rnA

250

rnA

LI

~

o

m

::!
...I

r-------------------------------------------------------------------------------~

Electrical Characteristics (Continued)
Vee = 12V, CT = 33 p.F, RT = 7.5 kO, TA within operating range except where stated otherwise
Symbol

Parameter

Tested Limits
(Note 2)

Conditions

Max

Min
V14

VI

Design Limits
(Note 3)
Min

Typ

Units
Max

5.0

Auxiliary Output
Voltage

Lamp OFF

Alarm Level

(Difference Between First
and Second Measurement)

V

Lamp ON
230

260

1.2

V

330

mV

Sensitivity to Electrostatic Discharge: Pins 7,10,13, and 14 will withstand greater than 1500Vwhen tested using 100 pF and 1500n In accordance wHh National
Semiconductor standard ESO test procedures. All other pins will withstand in excess 012 kV.
Note 1: Test circuH for overvoltage capabiiity at pins 3, 6, 7.
Note 2: Guaranteed 100% production tested at 25"C. These limits are used to calculate outgoing quality levels.
Note 3: Umlts guaranteed to include parametric variations. TA
figures.

=

-40"C to +80"C and from Vee

=

7.5V-18V. These limits are not used to calculate AOQL

Note 4: Variations over temperature range are not production tested.
13V

LM903

TL/H/5699-2

In Lamp ON condition, 19 should be limited to 600 rnA.

Block and Application Circuit
Cy
33}'
10

12

13

TL/H/5699-S

Memory capacitor on pin 15 is set
High-Lamp off
Low-Lamp on

5-70

r
3:

Circuit Timing Diagram
V12
4.1V
4V

CD
0
Co)

tl

25ms

O.7V

Threshold

12

35ms

1.0V

15t Measurement

t3

12 + 1.5s

1.0V

2nd Measurement

t4

t3+10ms

O.BV

Measurement Latched

t5

14 + B ms

O.7V

Probe Current Off

tV h~------------':~I

PROBE CURRENT

t 3 1 ' - - - - - - - -_ _ _ __

LAMP CURRENT

r---,

,---

I

I

I

LAMP OFF OR FLASHING
OEPENOING ON MEASUREMENT

TLfH/S699-4

Circuit Operation
A measurement is initiated when the supply is applied, provided the control input pin 7 is low. Once a measurement is
commenced, pin 7 is latched low and the ramp capacitor on
pin 12 begins to charge. After 25 ms when switch-on transients have subsided, a constant current is applied to the
thermo-resistive probe. The value of probe current, which is
supplied by an external PNP transistor, is set by an external
resistor across an internally generated 21 V reference. The
lamp current is applied at the start of probe current.

Using resistance wire of 50 1L0cm resistivity, 8 cm of 0.08
mm (40 AWG) give approximately 80 at 25°C. Such a probe
will give about 500 mV change between first and second
measurements in air, and 100 mV change with oil, hydraulic
fluid, etc., in the application circuit. With an alarm threshold
of 280 mV (typ) lack of fluid can readily be detected. As the
probe current, measurement reference and measurement
period are all externally adjustable, there is freedom to use
different probes and fluids.

35 ms after switch-on, the voltage across the probe is sampled and held on external capacitor Cl (leakage current at
pin 1 less than 1 nA). After a further 1.5 seconds the difference between the present probe voltage and the initial
probe voltage is measured, multiplied by 3 and compared
with a reference voltage of 850 mV (externally adjustable
via pin 16). If the amplified voltage difference is less than
the reference voltage the lamp is switched off, otherwise
the lamp commences flashing at 1 Hz to 2 Hz. 10 ms later
the measurement latch operates to store the result and after a further 8 ms the probe current is switched off.

Another possibility is the use of high temperature coefficient
resistors made for special applications and positive temperature coefficient thermistors. The encapsulation must have
a sufficiently low thermal resistance so as not to mask the
change due to the different surrounding mediums, and the
thermal time constant must be quick enough to enable the
temperature change to take place between the two measurements. The ramp timing could be adjusted to assist this.
Probes in liquids must be able to drain freely.

A second measurement can only be initiated by interrupting
the supply. An external CR can be arranged on pin 7 to
prevent a second measurement attempt for 1 minute. The
measurement condition stored in the latch will control the
lamp.
PROBES

The circuit effectively measures the thermal resistance of
the probe. This varies depending on the surrounding medium (Figure 1). It is necessary to be able to heat the probe
with the current applied and, for there to be sufficient
change in resistance with the temperature change, to provide the voltage to be measured.

PROBE TEMPERATURE 1°C)

FIGURE 1. Typical Thermo-Resistive Probe

Probes require resistance wire with a high resistivity and
temperature coefficient. Nickel cobalt alloy resistance wires
are available with resistivity of 50 1L0cm and temperature
coefficient of 3300 ppm which can be made into suitable
probes. Wires used in probes for use in liquids must be designed to drain freely to avoid clogging. A possible arrangement is shown in Figure 2.
The probe voltage has to be greater than 0.7V to prevent
short circuit probe detection less than 5V to avoid open
circuit detection. With a 200 mA probe current this gives a
probe resistance range of 40 to 250. This low value makes
it possible to use the probe in partially conducting fluids.
TLfH/S699-S

FIGURE 2
5-71

o~~----------------------------------~
~

...J

Equivalent Schematic Diagram

...

~

~
wil!l

...

IV
b-/f

~

~F~
G;

_'1...0

~.L

~

""

yo

:~

[

g

:Vr
rolr~

~

n~
~

~
--:)-/1

k

rY
I

b-I'

41.f.L

~'\....,......

ill

1"'---

n

~

.

~

'\.

\:!
::l

yo

:m£

V
A

;;

.>

i\!i

i.

Supply Current vs
Supply Voltage
40

6. 1

2.32

35

E
w

<'

.§.

§
B

~

30

-

25

6.0

I-

~
~

20

-

5.9

iil
15

10

f..- ~

10

15

2.2B
2.26

!

-

2.24
2.22

SUPPLY VOLTAGE (V)

10

15

5

20

Output Voltage vs
Pin 7 Voltage

10

1

I

15

20

Output Voltage vs
Pin 14 Voltage

,...

6

J-+-1,... f--

IPIN 10
SHORT

I-

SUPPLY VOLTAGE(V)

SUPPLY VOLTAGE (V)

I

t.-- t.--

2.20

5

20

2.30

tl

5.B
5

N

Probe Reference V vs
Supply Voltage

Regulated Voltage vs
Supply Voltage

5

A

I--

J

PIN 10
OPEN

I

V

V

IV

1/

1//
o
o

V

o
o
PIN 7 VOLTAGE(V)

PIN 14 VOLTAGE(V)

TLlH/B709-3

Pin Function Description
Pin 1

Pin 2
Pin 3

Pin 4

Input amplifier for thermo-resistive probe with 5 nA
maximum leakage. Clamped to ground at the start of
a probe 1 measurement.
Device ground - OV.
This pin is connected to the emitter of an external
PNP transistor to supply a 200 mA constant current
to the thermo-resistive probe. An internal reference
maintains this pin at VSUPPLY - 2V.
Base connection for the external PNP transistor.

Pin 5

This pin is connected to the thermo-resistive probe
for short and open circuit probe detection.

Pin6

Supply pin, +7.5V to +18V, protected against
+ 50V transients.

Pin 7

High Impedance input for second linear voltage
probe with an input range from 1V to 5V. The gain
may be set externally using pin 10.
Probe select and control input. If this pin is taken to
a logic low level, probe 1 is selected and the timing
cycle is initiated. The selection logic is subsequently
latched low until the end of the measurement. If kept
at a low level one shot or repeating probe 1 measurements will be made depending upon pin 9 conditions. A high input level selects probe 2 except during a probe 1 measurement period.

Pin 8

Pin 9

Pin 10 A resistor may be connected to ground to vary the
gain of the probe 2 input amplifier. Nominal gain
when open circuit is 1.2 and when shorted to ground
3.4. DC conditions may be adjusted by means of a
resistor divider network to VREG and ground.
Pin 11 Regulated voltage output. Requires to be connected
to pin 15 to complete the supply regulator control
loop.
Pin 12 The capacitor connected from this pin to ground
sets the timing cycle for probe 1 measurements.
Pin 13 The resistor connected between this pin and ground
defines the charging current at pin 12. Typically 12k,
the value should be within the range 3k to 15k.
Pin 14 A low leakage capacitor, typical value 0.1 /LF and
not greater than 0.47 /LF, should be connected from
this pin to the regulated supply at pin 11 to act as a
memory capacitor for the probe 1 measurement.
The internal leakage at this pin is 2 nA max for a
long memory retention time.
Pin 15 Feedback input for the internal supply regulator, normally connected to VREG at pin 11. A resistor may
be connected in series to adjust the regulated output
voltage by an amount corresponding to the 1 mA
current into pin 15.
Pin 16 Linear voltage output for probe 1 and probe 2 capable of driving up to ± 10 mA. May be connected with
a 600n meter to VREG.

The repeat oscillator timing capaCitor is connected
from this pin to ground. A 2 /LA current charges up
the capacitor towards 4.3V when the probe 1 measurement cycle is restarted. If this pin is grounded
the repeat oscillator is disabled and only one probe
1 measurement will be made when pin 8 goes low.

5-77

~

-=:t

Q

r------------------------------------------------------------------------------------------,

.....

Application Notes

..J

THERMO-RESISTIVE PROBES CONSTRUCTION

::E

OPERATION AND

R=9A@25"C
1=200mA

6

These probes work on the principle that when power is dissipated within the probe. the rise in probe temperature is
dependent on the thermal resistance of the surrounding material and as air and other gases are much less efficient
conductors of heat than liquids such as water and oil it is
possible to obtain a measurement of the depth of immersion
of such a probe in a liquid medium. This principle is illustrated in Figure 1.

mm

4 LESS

DEEP
2

mm
DEEPER
0.0

.05

1.0

1.5

2.0

TIME (SECONDS)
TL/H/8709-5

FIGURE 2
current with very fine wires to avoid excessive heating and
this current may be optimized to suit a particular type of
wire. The temperature changes involved will give rise to noticeable length changes in the wire used and more sophisticated holders with tensioning devices may be devised to
allow for this.
900

!

RTH OIL-l!.T2

..... L

.. - --AR2 .... .t.V2 ".

~

SDD
700

~

. OIL·

~

~

0

>

TL/H/S709-4

I

FIGURE 1

During the measurement period a constant current drive I is
applied to the probe and the voltage across the probe is
sampled both at the start and just before the end of the
measurement period to give t.v. RTH Air and RTH Oil represent the different thermal resistances from probe to ambient
in air or oil giving rise fo temperature changes AT 1 and AT2
respectively. As a result of these temperature changes the
probe resistance will change by .:I.R1 or .:I.R2 and give corresponding voltage changes .:I. V1 or .:I. V2 per unit length.

nME (SECONDS)
TL/H/8709-6

FIGURE 3
Probes need not be limited to resistance wire types as any
device with a positive temperature coefficient and sufficiently low thermal resistance to the encapsulation so as not to
mask the change due to the different surrounding mediums.
could be used. Positive temperature coefficient thermistors
are a possibility and while their thermal time constant is likely to be longer than wire the measurement time may be
increased by changing CT to suit.

Hence
LA
.:I.V = T.:I.V1

(L - LA)

+ --L-.:I.V2

and for .:I.V1 > .:I.V2. RTH Air> RTH Oil • .:I.V will increase as
the probe length in air increases. For best results the probe
needs to have a high temperature coefficient and low thermal time constant. One way to achieve this is to make use
of resistance wires held in a suitable support frame allowing
free liquid access. Nickel cobalt iron alloy resistance wires
are available with resistivity 50 /-Lo.cm and 3300 ppm temperature coefficient which when made up into a probe with 4
x 2 cm 0.08 mm diameter strands between supports (10
cm total) can give the voltage vs time curve shown in Figure
2 for 200 mA probe current. The effect of varying the probe
current is shown in Figure 3. To avoid triggering the probe
failure detection circuits the probe voltage must be between
0.7V and 5.3V (VREG - 6V). hence for 200 mA the permissible probe resistance range is from 3.50. to 240.. The example given has a resistance at room temperature of 90.
which leaves plenty of room for increase during measurements and changes in ambient temperature.

USEFUL
RANGE
OF
PROBE

e.g.
16cm

Various arrangements of probe wire are possible for any
given wire gauge and probe current to suit the measurement
range required. some examples are illustrated schematically
in Figure 4. Naturally it is necessary to reduce the probe

TL/H/8709-7

FIGURE 4
5-78

r-----------------------------------------------------------------------------,
Application Notes (Continued)

r
3:
......

CIRCUIT OPERATION

~
p.)

o

1) Thermo-Resistive Probes

4.3V

These probes require measurements to be made of their
resistance before and after power has been dissipated in
them. With a probe connected as probe 1 in the connection
diagram the LM 1042 will start a measurement when pin 8 is
taken to a logic low level (Va < 0.5V) and the internal timebase ramp generator will start to generate the waveform
shown in A"gure 5. At 0.7V, Tl, the probe current drive is
switched on supplying a constant 200 mA via the external
PNP transistor and the probe failure circuit is enabled. At 1V
pin 1 is unclamped and Cl stores the probe voltage corresponding to this time, T2. The ramp charge rate is now reduced as Cr charges toward 4V. As the 4.1V threshold is
passed a current sink is enabled and Cr now discharges.
Between 1.3V and 1.0V, T3 and T4, the amplified pin 1 voltage, representing the change in probe voltage since T 2 (and
as the current is constant this is proportional to the resistance change) is gated onto the memory capacitor at pin 14.
At 0.7V, T5, the probe current is switched off and the measurement cycle is complete. In the event of a faulty probe
being detected the memory capacitor is connected to the
regulated supply during the gate period. The device leakage
at pin 14 is a maximum of 2 nA to give a long memory
retention time. The voltage present on pin 14 is amplifed by
1.2 to drive pin 16 with a low impedance, ± 10 mA capability, between 0.5V and 4.7V. A new measurement can only be
started by taking pin 8 to a low level again or by means of
the repeat oscillator.

V9

LOV

TL/H/B709-9

FIGURE 6
SO

e
::E
'"

;:

~
~

60

40

/

20

V

/

/

V

/
o

o

30

60

SO

100

120

CR(j.40 dB IF gain control range
25 MHz detector output bandwidth
Linear output phase response
Output swings ± 3.5V referenced to ground
Gateable peak-following AGC detector
DC-adjustable detection phase
DC-adjustable 0 carrier output level

Connection Diagram

11
l.r.OUTPUT---tI----,

10
, - - - - - ; - - - REr. LIMITER INPUT

.--+-- DETECTOR INPUT

12V SUPPLy_..;;12+-+
I.r. REGULATOR -~1--4_~

GROUND

,-;-++-- DET. PHASE ADJUST

I.r. DECOUPLE _--'L.. '<''''7

I.F. INPUTS [

--t----.. .
16

4
. . . - - - - - - + - - OUTPUT D.C. ADJUST

17
I.r. DECOUPLE ---11-----......

3
>--......--+--DETECTOR
OUTPUT

GROUND _.;.;18+---,

19
AGe FILTER ---It--....-{

2

SUPPLY DECOUPLE

L-----•.""...~-AGC THRESHOLD

20
AGC BIAS/GATE-~-------1

TUH/9127-1

Order Number LM1211N
See NS Package Number N20A

5-82

r-

s:
.....

Absolute Maximum Ratings

I\)

If MilitaryJ Aerospace specified devices are required,

Power Dissipation

contact the National Semiconductor Sales OfficeJ
Distributors for availability and specifications.

Thermal Resistance

Power Supply Voltage, V12

Junction Temperature

15V

IF Supply Current,I13

40mA

Detector Output Current, 13

15mA

Detector Input Signal, V9

1 Vrms

Ref. Limiter Input Signal, Vl 0

1 Vrms

AGC Bias/Gate Current, 120

1.67W
60°C/W
125°C

Operating Temperature Range

-40°C to +85°C

Storage Temperature Range

- 65°C to + 150°C

Lead Temp. (Soldering, 10 sec.)

260°C

ESD Susceptibility (Note 1)

3000V

3mA

DC Electrical Characteristics
TA

=

25°C, Test Circuit, VIF

Symbol

=

VDe!

Parameter

=

0, VAGG

=

0, VPH

=

4V, VaG

=

6V, all switches open unless noted.

Test Conditions

=
=

Typ

Is

Supply Current

SW 3 closed, VAGG

V13

IF Regulator Voltage

SW 3 closed, VAGG

V15/16

IF Input Voltage

SW 2, 3 closed

V14- V17

IF Decouple Vas

SW 2,3 closed, measure V14-V17

111

IF Output Current

V10

Limiter Input Bias

Vg

Tested
Limit
(Note 2)

Design
Limit
(Note 3)

Units
(Limit)

3V

67

80

mA(max)

3V

6.5

5.8
7.0

V (min)
V (max)

3.9

3.4
4.4

V (min)
V (max)

0

±50

mV(max)

4.0

2.5
5.0

mA(min)
mA(max)

SW 1, 2, 3 closed

5.1

4.5
5.5

V (min)
V (max)

Detector Input Bias

SW 1, 2, 3 closed

5.1

4.5
5.5

V (min)
V (max)

V5/6

Reference DC Voltage

SW 1, 2, 3 closed

4.6

4.0
5.2

V (min)
V (max)

V3

a Carrier Output Voltage

SW 1, 2, 3 closed

VaG

o Carrier Adjust Voltage

SW 1, 2, 3 closed, adjust VaG for V3

119(D)

AGC Discharge Current

SW 1, 3 closed, VAGG

=

119(C)

AGC Charge Current

SW 1, 4 closed, VAGG

=

119(L)

AGC Leakage Current

SW 1, 2, 4 closed, VAGG

SW 2, 3 closed, VAGG

=

6V, 111

=

12V - Vl1
50

0

±0.5

V (max)

6.0

1.0
11.0

V (min)
V (max)

2V

-11

-7
-16

p.A(min)
).'A(max)

6V

1.0

0.7
1.3

mA(min)
mA(max)

-25

±200

nA(max)

=

4V

=

OV

Note 1: Human body model, 100 pF discharged through a 1.5 kn resistor.
Note 2: Tested limits are guaranteed and 100% production tested.
Note 3: Design limits are guaranteed, but not 100% production tested. These limits are not used to determine outgoing quality levels.

5-83

.....
.....

Detector AC Set-up Procedure TA =

25°C, Test Circuit, Sw 1, 2, 3 closed, VAGC = 0, VPH = 4V.

1. With no input (VO et = 0), adjust VOC for V3 = OV.
2. Apply Voet = 100 mVrms, 60 MHz CW at the input. Tune L2 for maximum DC voltage at output Pin 3.

AC Electrical Characteristics T A =

25°C, Test Circuit, Follow AC set-up procedure, f = 60 MHz, VAGC = 0,

VPH = 4V, VOC as per set-up, all switches open unless noted.
Symbol

Parameter

Test Conditions

Z15/16

iF Input Impedance

Measure Differential Impedance between
Pins 15 and 16.

Av(IF)

Maximum IF Gain (Note 3)

SW 2 Closed, VIF = 0.5 mVrms, Measure Vaut.
Av(lF) = 20 log (

5

Vaut 4 )
10-

Typ

Tested Design
Limit
Limit
(Note 1) (Note 2)
40
BO

60

Units
(Limit)

n (min)
n (max)

30

20

dB (min)

x

VAGC20

20 dB Gain Reduction

SW 2 Closed, VIF = 5 mVrms, Adjust VAGC
for Same Vaut as in Av(lF) Test.

2.6

2.2
3.0

V (min)
V (max)

VAGC40

40 dB Gain Reduction

SW 2 Closed, VIF = 50 mVrms, Adjust VAGC
for Same Vaut as in Av(lF) Test.

3.B

3.3
4.3

V (min)
V (max)

1M

IF Intermodulation
(Note 3)

SW 2 Closed, f, = 60 MHz, f2 = 65 MHz,
VIF = 10 mVrms Ea, Adjust VAGC for
Vaut = 10 mVrms Ea, Measure 1M Products
Relative to Vaut.

-40

-30

dB (min)

Z9

Detector Input Impedance

Measure Impedance into Pin 9

3.0

2.0
5.0

Kn (min)

Z10

Reference Limiter
Input Impedance

Measure Impedance into Pin 10

2.0

1.3
5.0

Kn (min)

Av(D)

Detector Conversion Gain

SW 1, 2, 3 Closed, Voet = 100 mVrms,

Detector-6dB Linearity

Measure V30C. Av(D) = 20 log (V3 )
0.1
SW 1, 3 Closed, VOet = 50 mVrms,

LIN

Measure V3'. LIN = 20 log

(~:)

V3(Th)

AGC Threshold

V3(OLl

Detector Overload Capability SW 1, 2, 3 Closed, VOet = 1 Vrms, Measure V3.

PHA(+) DC Phase Adjust (+ )

PHA(-) DC Phase Adjust ( - )

SW 1, 3 Closed, Increase Voet until
119 = 100 ",A, Measure V3.

-6

pF(max)

20

dB (min)

30

dB (max)

-5

dB (min)

-7

dB (max)
2.6
3.0

2.B

V (min)
V (max)

4.1

3.5

V (min)

SW 1, 2, 3 Closed, VOet = 100 mVrms, Measure
Ratio of V3 with VPH = 6V to V3 with
VPH = 4V.

0.65

0.80

VIV(max)

SW 1, 2, 3 Closed, VOet = 100 mVrms, Measure
Ratio of V3 with VPH = 2V to V3 with
VPH = 4V.

0.30

0.60

VIV (max)

-3.7

-3.0

V (min)

V3(-)

Negative Output Swing

SW 1, 2, 3 Closed, f = 70 MHz, VOet = 300 mVrms,
VPH = 6V, Measure V3.

DBW

Detector Output Bandwidth

SW 1,2,3 Closed, Modulate VOet with 30% AM
Modulation. Increase Modulation Frequency Until
Pin 3 Signal Drops 3 dB.

DHL

24

pF(max)

Detector Harmonic Levels

SW 1, 2, 3 Closed, VOet = 100 mVrms, Measure
60 MHz and 120 MHz Levels Relative to V3
Note I: Tested limits are guaranteed and 100% production tested.

25

20

MHz (min)

-35

-20

dB (min)

Note 2: Design limits are guaranteed. but not 100% production tested. These limits are not used to determine outgoing quality levels.
Note 3: The IF amplifier output is measured with the IF output connected to a 50n measurement system resulting in a 25.0 loaded impedance. The gain in an

actual application will typically be 20 dB higher.

5-84

r3:

....
....
....

Test Circuit

N

Measure Parameters at Indicated Test Points

~
~O'OlP.Fr - - - - - - - - - - - - - - - ,0.01J.L~
VOUT

10 K

r-----i--~-J~r__oV10

V11o--'W'lr-4_-+---~

.:c.

1 0.0 1 p.F

20

+12V

•

10K

t-

SW3
0-0-5V
+12V

TLlH/9127-2

T1 =

son unbal. to bal. Mini-circuits Lab TMOH-H

L2 = 4% T #22 wire on

0/'611' form with HF core,

shielded

5-85

~
~

r------------------------------------------------------------------------------------------,

~

Typical Performance Characteristics

:::E

(All characteristics apply to the typical application circuit. Figure numbers are referenced in the applications information.)

C'I

-J

FIGURE 1
IF Amplifier Gain
o Reduction Characteristic

~

z

~

~

RL =200Jl
f=60MHz

\

-20

0

G

.......

"

-10

"iii"

-30

"iii"

-3

~

-6

5

-9

;::

-12

5

\

1\

\

-15

2

3

4

5

6

7

o

10 20 30 40

90

60

£

30

~
z
0

!

"-

"~

-30

:\

f\

60

I
~=It'H

"- 1-1'\

I

30

il:

-30

!il

"N

L2=2.21'

-60
L2= 3.9 I'H

-90
40 45

so

IF GAIN = 60 dB

o
o

60 70 80 90

10

--..

-,1\

- --

"

'!j5"

-2

50

60

:;!

-4

"- '\

PIN 7 VOLTAGE (V)

\

-3

-5

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

FREQUENCY (MHz)

-1

~

, r--.. f-

-90

55 60 65 70 75 80 85

"iii"

~

-

f=40t.tH~,

40

FIGURE 6
Output Amplifier
o Frequency Response

"- r-.!.~60MHz

-60

30

20

GAIN REDUcnoN (dB)

FIGURE 5
Detector Phase
90 Adjust Characteristic

V9=Vl0
V7=4V

~

so

FREQUENCV (MHz)

FIGURE 4
LM1211 Detection Phase

1/

i\

PIN 19 VOLTAGE (V)

g

/

RL=200Jl
GAIN REDUCTION -20 dB

o

FIGURE 3
IF Amplifier Noise
Figure vs AGC

10

0

......

-so

12

........

~

\

-40

-60

FIGURE 2
IF Amplifier
o Frequency Response

~\
o

\
5

10

20

15

25

30

35

FREQUENCY (MHz)
TL/H/9127-3

Typical Application Circuit
100

+12V

o---1p--1..:....---+.-.:.:+.....
+12V
9.1 K

10K

PHASE

r--t-+-+----......-+, then the filtered output is given by:

While the following description will apply to quasi-synchronous detection, the LM1211 can be made to function as a
true synchronous detector if an external phase-locked loop
(PLL) is used. In this mode, the reference limiter input Pin 10
is decoupled and the voltage-controlled oscillator (VCO) signal from the PLL is coupled into the reference port at Pins 5
and 6. Differential coupling of any external signal into the
reference port is critical to minimize feedback to the IF amplifier inputs.

2 RL
VOUT = ;: Re Fm(t)cos
The output depends on the amplitude of Vs(t) and relative
phase  between Vs(t) and Vr(t). If  is made 0 degrees so
cos is 1, then the multiplier acts as an amplitude detector
and can be used to detect the amplitude modulation Fm(t)
on the IF carrier. Note that around 0 degrees cos  changes
very little with phase. The multiplier can also be used as a
5-88

r-

s::
......

Detector (Continued)

I\)

phasing the detector is to first select the external components which produce the desired detection phase when the
phase adjust control is in the center of its range (V7 = 4V),
and then use the control to trim part-to-part and external
component variations.
The curves of Figure 4 give the multiplier detection phase
versus frequency for different values of L2 with Pins 9 and
10 shorted together. These curves can be used to select
the L2 value and to determine whether additional phase
shift between Pins 9 and 10 is required. The detection
phase versus temperature is approximately - 0.25 degrees/

·C.
A detection phase of e/> = 0 degrees corresponds to maximum (+) amplitude detection efficiency, i.e. the detector
output voltage increasing with Pin 9 input level. In the simplest case this can be obtained by choosing the L2 for
which the Figure 4 curve passes through 0 degrees at or
near the IF frequency. When the proper phaSing cannot be
obtained by this means, phase lead or lag must be introduced at Pin 10 relative to Pin 9. A simple RC lead-lag network which can provide up to ± 90 degrees phase shift is
shown in Figure 10.
When XC1 = XC2 = 240!1 in the Figure 10 circuit, approximately 90 degrees of phase difference between Pins 9 and
10 is produced with 3 dB additional attenuation. Pin 10 is
shown lagging Pin 9, but the two pins could be reversed to
produce phase lead. If C1 is increased or C2 is decreased,
the phase difference is reduced.
A wideband FM quadrature detector is implemented in Figure 11 by configuring the IF Amplifier for maximum gain and
replacing L2 with an LC tank tuned to the IF frequency.
Since the IF Amplifier performs the limiting function, the reference limiter is not used; rather, the quadrature Signal is
fed directly to the reference port via an RC phasing network.
The DC offset at Pin 10 (13 K!1 to 12V) prevents signal
leakage through the reference limiter to Pins 5 and 6.
The FM detector sensitivity depends on the phase slope of
the LC tank, which is determined by the Q. For example, the
tank in Figure 11 is resonant around 70 MHz and has a Q ""
2 defined by the internal 1 K!1 resistance across Pins 5 and
6 in parallel with the external resistor. Deviating the input
frequency produces an output characteristic given by:

TL/H/9127 - 7

FIGURE 9. Balanced Multiplier Circuit
phase or frequency detector if Vs(t) is limited to remove
amplitude information and e/> is centered at 90 degrees,
where cose/> produces the largest change in output for a
given change in phase.
Thus a vital part of setting up the detector will be to obtain
the correct relative phase for the type of demodulation desired.
Reference Limiter
The purpose of the reference limiter is to create the reference signal required for product detection by stripping AM
modulation off the input signal. This should not be confused
with the limiter required in an FM system, which is in the
main Signal path. FM limiting would be performed by locking
the IF amplifier at maximum gain as previously described, in
which case the reference limiter becomes redundant.
A single differential limiter stage is provided between Pin 10
and the reference port at Pins 5 and 6. Pin 10 is internally
biased from a 5.W source through a 3.3 K!1 resistor; the
detector input Pin 9 is biased from the same source through
5 K!1. By sharing a common bias point Pins 9 and 10 can be
directly shorted together when fed from the same Signal,
thus saving a coupling capacitor. Alternatively, Pins 9 and
10 may be fed separately allowing phase and/or amplitude
differences to be introduced.

V3 = Vpk[cos(90 ± aO)1
where Vpk is the theoretical peak output level set by the IF
Pin 11 load impedance, and ao is the combined phase
swing produced by the tank and detector. For the Figure 11
circuit, Vpk = 6V and a 0 "" 5 degrees/MHz, yielding an
output swing of ± 0.5 V /MHz.

The reference limiter output is a differential Signal across
the reference port Pins 5 and 6. Pins 5 and 6 are internally
biased at 4.6V and have a 1 K!1 differential impedance.
Limiting begins with 20 mVrms at Pin 10 and heavy limiting
occurs above 100 mVrms input. The maximum limited output voltage is 350 mVrms.

12V

Detector Phasing
As we have seen, the relative phase between the detector
and reference inputs of the multiplier determines the
LM1211 demodulation characteristic. The detector input
phase is known since it connects directly to Pin 9. However,
the reference phase depends on several factors: The external components at Pins 10, 5, and 6, the phase shift through
the reference limiter, and lastly the setting of the detector
phase adjust control at Pin 7. The general approach for

TL/H/9127 -8

FIGURE 10. Detector Input Phasing Network
5-89

......
......

~

.,...
N

:!l
....I

r---------------------------------------------------------------------~

Detector (Continued)
in Figure 12. The nominal 0 carrier (no input Signal) output
voltage is OV, and a negative supply is required as a return
point for the external load resistor R3. The output may be
biased at up to 5 mA in order to maintain the (-) slew rate
into capacitive loads.

Phase Adjust Control
Once the external components have been selected for the
correct nominal phasing, the detector phase adjust is used
to perform the final set-up by monitoring the detector output
either for maximum output in the case of AM detection or for
OV average level for FM detection. The phase adjust control
Pin 7 is externally biased via a potentiometer and resistor
from 12V and requires a 2V to 6V minimum range at Pin 7.
The amount of phase lead or lag added to the reference
path as a function of V7 is given in Figure 5. For example, at
70 MHz a cumulative phase error of ± 50 degrees could be
compensated for by the phase adjust control.

The 0 carrier output voltage is adjusted by the control voltage on a potentiometer at Pin 4. The center of the Pin 4
range is Yo supply with an adjustment sensitivity of approximately 0.1 VIV. Thus on a 12V supply up to ± 0.6V part-topart output variation can be trimmed out. The Pin 3 output is
capable of swinging up to ±4V; however, in certain AM detector applications the output will always remain above OV.
In these cases it may be possible to omit the negative supply and return the Pin 3 load resistor directly to ground. This
will result in some degradation in linearity at low output voltages which can be minimized by pre-biasing the 0 carrier
level high (V4 = 12V).

While the previously cited - 0.25 degrees/"C detection
phase temperature dependence is not noticeable in AM detection applications, it can cause the average DC level of
the FM detector output to drift. This can be reduced by using the phase adjust control in a feedback loop as shown in
Figure ". Finally, it should be re-emphasized that the Pin 7
adjustment is intended as a trim rather than a substitute for
correct detector phasing.

The output amplifier frequency response is shown in Figure
6. The output exhibits a linear phase response of approximately -5.5 degrees/MHz out to 30 MHz. The first 70 MHz
carrier harmonic is approximately -46 dB and the second
harmonic -40 dB referenced to a 3V peak output.

Detector Output
The LM1211 output amplifier has an NPN emitter follower
driving Pin 3 through a 500 damping resistor as shown
O.001uF

12V

12V
13K
10

O.22uH

12v'o--.----4--+--l
33K
0.1 uF RpH

10K

12V

INPUT ~I~IUF 82
~e.,
...

50

4

O.OluF

15K

OUTPUT

D.C.

O.OOluF 82

ADJUST

R3

1-----''----+-<> OUTPUT
-5V
IK

-5V
TL1H/9127-9
ALIGNMENT SEQUENCE:

1. With no input, adiust Roc for V3 =
2. Apply Vin ;;, 10 mVrms, Fa

=

ov.

70 MHz ±5 MHz Dev, Fm

= 100 kHz;

Tune Quadrature coil for best output linearity.
3. Adiust RpH for output DC centering.

FIGURE 11.70 MHz FM Detector Application

5-90

TL/H/9127 -10

FIGURE 12. Detector Output Amplifier

r-

Detector (Continued)

s:
....
........
N

cause of the large ratio of charge to discharge current, the
LM 1211 AGC has inherently faster recovery from a step
increase in signal than from a decrease. The overall speed
is inversely proportional to the AGe filter capacitor, with
0.05 ".F being a practical lower limit for 120 = 1 rnA. It is
important to use a quality (low Rs) capacitor at Pin 19 to
prevent AGe oscillation.

AGC Comparator
An AGC comparator is provided for use in AM systems. The
(+ ) input is internally connected to the detector output Pin 3
while the ( -) input is biased from an external resistive divider at AGC threshold Pin 1. An output current charges and
discharges the AGC filter capacitor at Pin 19 to control the
IF amplifier gain. The comparator is biased by a current into
bias/gate Pin 20. Internally, Pin 20 has a diode in series with
1 K!l to ground so that the current level from an external
resistor R20 to 12V is given by:

The AGe detector can be used at lower charge/discharge
ratios by reducing 120 which has a direct effect on the
charge current but only a second order effect on the discharge current. For 120 = 100".A a 15: 1 ratio is produced
and a 0.01 ".F minimum capacitor can be used. As the
charge/ discharge ratio is reduced, peak detection no longer
occurs and gating of Pin 20 may be necessary. This requires
an external gate pulse generator to turn on the Pin 20 bias
current only during the time the detector output is to be
sampled. In between gate pulses the Pin 19 output will be
tri-stated and the filter capacitor will hold the previous voltage until the next gate pulse. Permanently grounding Pin 20
turns off the AGe comparator, allowing an external AGe
signal at Pin 19 to control the IF amplifier gain.

120 =

11.3
R20 + 1000
Whenever the detector output exceeds the AGC threshold,
a current equal to the Pin 20 bias current is delivered to Pin
19 to charge the AGC filter capacitor. When the detector
output is below the AGC threshold, approximately 11 /LA
discharge current flows into Pin 19. Thus the charge to discharge current ratio at Pin 19 is given by 120/11 ".A, or 90:1
for 120 = 1 rnA. This large ratio creates a peak-detecting
action in which the AGC loop holds the detector ( +) output
peaks at the AGC threshold voltage, typically 1-3V. Be-

+12V

\;

TUH/9127-11

Printed Circuit Layout (component side)

5-91

U)

CD

oo:t
.,...

:E
....I

......

r----------------------------------------------------------------------------,
NatiOnal

~ Semiconductor
Corporation

U)

CD

.,...

II)

:E
....I

LM 1596/LM 1496 Balanced Modulator-Demodulator
General Description

Features

The LM1596/LM1496 are doubled balanced modulator-demodulators which produce an output voltage proportional to
the product of an input (signal) voltage and a switching (carrier) signal. Typical applications include suppressed carrier
modulation, amplitude modulation, synchronous detection,
FM or PM detection, broadband frequency doubling and
chopping.

• Excellent carrier suppression
65 dB typical at 0.5 MHz
50 dB typical at 10 MHz
• Adjustable gain and signal handling
• Fully balanced inputs and outputs
• Low offset and drift
• Wide frequency response up to 100 MHz

The LM1596 is specified for operation over the -55'C to
+ 125'C military temperature range. The LM1496 is specified for operation over the O'C to + 70'C temperature range.

Schematic and Connection Diagrams
Metal Can Package

V-

GAIN ADJUST

-CARRIER
INPUT

GAIN ADJUST

+CARRIER
INPUT

8(10)
CARRIER
INPUT
+

7(8)
4(4)

SIGNAL
INPUT
+

1(1)
GAIN
ADJUST

BIAS

5(5)

TL/H17887-2

BIAS

Top View
Note: Pin 10 is connected electrically to the
case through the device substrate.

Order Number LM1496H or LM1596H
See NS Package Number HOSC

v-

10(14)

Dual-In-Line and Small Outline Packages

TL/H17887 -1

Numbers in parentheses show DIP connections.

V-

+SIGNAL IN
GAIN ADJUST
GAIN ADJUST

3

12

-SIGNAL IN

4

11

BIAS

5

10

+OUTPUT

6

9

7

8

-OUTPUT
-CARRIER INPUT

+CARRIER INPUT
TL/H/7887 -3

Order Number LM1496M or LM1496N
See NS Package Number M14A or N14A

5-92

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Internal Power Dissipation (Note 1)

Soldering Information
• Dual-In-Line Package
Soldering (10 seconds)

500mW

Applied Voltage (Note 2)
Differential Input Signal (V7 - Ve)

30V
±5.0V

Differential Input Signal (V4 - V1)

±(5+lsRo)V

Input Signal (V2 - V1, V3 - V4)

Vapor Phase (60 seconds)

Bias Current (15)

See AN-450 "Surface Mounting Methods and their effects
on Product Reliability" for other methods of soldering surface mount devices.

12mA
- 55'C to + 125'C
O'Cto +70'C
-65'C to + 150'C

Electrical Characteristics (TA =

25'C, unless otherwise specified, see test circuit)

Parameter

LM1596

Conditions

Min Typ
Carrier Feedthrough

Carrier Suppression

Transadmittance Bandwidth

Ve = 60 mVrms sine wave
fe = 1.0 kHz, offset adjusted
Ve = 60 mVrms sine wave
fe = 10kHz, offset adjusted
Ve = 300 mVpp square wave
fe = 1.0 kHz, offset adjusted
Ve = 300 mVpp square wave
fe = 1.0 kHz, offset adjusted
fs
fe
fs
fe

=
=
=
=

215'C
220'C

Infrared (15 seconds)

5.0V

Operating Temperature Range LM1596
LM1496
Storage Temperature Range

260'C

• Small Outline Package

10 kHz, 300 mVrms
500 kHz, 60 mVrms sine wave offset adjusted
10kHz, 300 mVrms
10 MHz, 60 mVrms sine wave offset adjusted

50

RL = 50n
Carrier Input Port, Ve = 60 mVrms sine wave
fs = 1.0 kHz, 300 mVrms sine wave
Signal Input Port, Vs = 300 mVrms sine wave
V7 - Ve = 0.5Vdc

LM1496

Max Min Typ

Units
Min

40

40

p.Vrms

140

140

p.Vrms

0.04

0.2

0.04

20

100

20
50

65

0.2

mVrms

150 mVrms

65

dB

50

50

dB

300

300

MHz

80

80

MHz

3.5

VIV

Voltage Gain, Signal Channel

Vs = 100 mVrms, f= 1.0 kHz
V7 - Ve = 0.5 Vdc

Input Resistance, Signal Port

f = 5.0 MHz
V7 - Ve = 0.5 Vdc

200

200

kn

Input CapaCitance, Signal Port

f = 5.0 MHz
V7 - Ve = 0.5 Vdc

2.0

2.0

pF

40

40

kn

5.0

5.0

pF

Single Ended Output Resistance f=10MHz
Single Ended Output
CapaCitance

f=10MHz

2.5

3.5

2.5

Input Bias Current

(11 + 14)/2

12

25

12

30

/LA

Input Bias Current

(17 + le)/2

12

25

12

30

/LA
/LA

Input Offset Current

(11 -14)

0.7

5.0

0.7

5.0

Input Offset Current

(17 -Ie)

0.7

5.0

5.0

5.0

Average Temperature
Coefficient of Input
Offset Current

(-55'C 

-=mmr

f!l

-10

R~ II~rtUlk~= 1.0kll

~

-20

111111111 1IIIIIlll I

is

~

1000

1111111 11111111,111111111 III
RL =3.9 kll 11111111 l\R.=1.0kll
10 RL=3.9kll R.=500ll'\\111111
RL=3.9 kllR =2.0kll
o
1·11111111 I

'1+

"'i

RL
-30 Av= Re+2,.
0.01
0.1
1.0
10
FREQUENCY (MHz)

100
TLlHI7BB7-S

5-94

r-

:s::
......

Typical Application and Test Circuit

U1

CD

en
......

Suppressed Carrier Modulator

r:s::
......

lk
+12V
O.I). V5
Vl0 = O.OV
V5> V4
V8

=

1.5V, Is

=

200 mA

5.5
V+
V+

19

=

=
=

7.5V, Cl
7.5V, C1

=
=

10".F
10".F

1 mA

6.8
6.5

V
mA

3.6
0.4

V
mA

5.8
5
5.2
7

V
mVI'C
V
mVI'C

6.0
40
60
6
14.5

6.5
50
8

V
s
ms
".A
V

Note 1: For operating at elevated temperatures, the device must be derated based on a 12S C maximum junction temperature and a thermal resistance of 85°C/W
junction to ambient.
G

Note 2: RSET ~ 10 MO, V+ ~ 9V, TA ~ 2S'C, (Figure 1).
Note 3: Output OFF.

5-98

LOW BATIERY
DETECTOR 112
INPUT

I

D7

I

08

TIMING
CAPACITOR

-

SENSE PARALLEL
OUTPUT OUTPUT
COLLECTOR
DARL1NGTON
OUTPUT

v+

14

IBl

BIAS STRING

09
I
I

'f'
co

DID

SUPPLY
ZENER

co

05

13

GROUND

STEERING
LOGIC
LOW BATIERY
DETECTOR

BIAS

5.8V 5.2V

COMPARATOR
INPUTS

+ 15

REFERENCES

COMPARATOR
OUTPUT

EMInER
TL/H/9139-2

FIGURE 2. LM18011nternai Schematic

~09~Wl

iii

o~----------------------------------------------------~

GO
.,...

Applications Hints

:E

CIRCUIT OPERATION

....I

The output transistor is normally operated with the emitter
grounded. Under these conditions the collector is guaranteed to saturate no higher than 1.SV at 200 mA. 1.9V saturation voltage is typical at 500 mAo The emitter may also be
used as an output, and it can swing from ground potential up
to 5V on a 9V supply. Emitter swing in the positive direction
is limited in the parallel output mode.
A low battery detector with a 6V threshold is also included
on chip. This circuit consists of 016, 017, D11, and D12.
When pin 12, the battery sense input, is higher than 6V, D12
clamps the emitter of 016 to 6.6V, and the output from the
current source flows through the zener to ground. If pin 14
drops below 6V, 016 is biased ON, and current is drawn
away from the zener and into 016. The SeR formed by 016
and 017 is triggered when 016 is biased ON. The capacitor
at pin 14 is discharged, part of its charge flows to the steering logic to pulse the output transistor, and the remainder
holds the SeR in its ON state.
When the timing capacitor has discharged, conduction in
016 and 017 is commutated. Note that the output from the
current source is less than the sustaining current required
by the SeR. The current source slowly charges the capacitor until the voltage across it rises 0.6V above pin 12, where
the cycle repeats itself. If pin 12 rises above 6V, the zener
clamps the voltage at pin 14 and the low battery detector
remains OFF.
Pin 12 is biased from an external resistive divider. The divider should be designed to detect at no lower than V+ = 7V.
The detector will continue to work at lower voltages providing pin 12 is at least 1V below the supply. For a 9V alkaline
battery a threshold of 8.2V is common. A resistive divider of
2.7 MO and 7.5 MO provides the appropriate threshold.

The LM1801 includes a bias string, comparator, steering
logic, output transistor, supply clamp, low voltage detector,
and reference. An internal schematic is shown in Figure 2.
The chip is biased by a group of current sources that are
controlled externally by a fixed resistor, Rsat. In normal, or
standby operation the supply current drain is nominally 6
times the set current at pin 1. The voltage at pin 1 is two
forward diode potentials (D1 + D2 = 1.2V typical) less than
the positive supply voltage. Practical values of Rset range
from 100 kO to 10 MO. Higher currents are useful where
speed is important, while lower currents promote long battery life.
The total standby current drain of the LM1801 will include in
addition to the above, the current drawn by the exter~al
circuits connected at pins 2, S, and 12. These are the resistive dividers used to set the low battery threshold and comparator threshold.
The voltage comparator consists of devices 01 through
010. The input features a common mode range from less
than SOO mV to V+ - 1.2V. If the non-inverting input is
within this range, the output state remains valid for inverting
inputs of OV to V+. If the inverting input is within the common mode range, valid comparisons hold for non-inverting
inputs of SOO mV to V+. The comparator may not switch
low if the positive input is grounded.
With a set resistance of 10 MO, comparator input bias currents of 2 nA are typical. This allows the use of high-value
resistors (10 MO) at the comparator inputs which help minimize total supply current. The comparator's output is available through a steering diode (DS) for latching or hysteresis
functions.
The comparator output is also coupled internally to the
steering logic (011-01S). The comparator, low battery detector, and parallel output (pin 10) functions are OR'd in the
logiC circuit. In addition, the comparator output is steered to
the parallel output. If the parallel outputs (pin 10) of two or
more chips are wired together along with a common ground,
the comparator on anyone chip can cause all of the other
output stages to switch, as well as its own output. Outputs
are switched when the inverting comparator input is positive
with respect to the non-inverting input. Low battery functions are coupled to the steering logic via 012, and therefore do not affect the parallel output (01S).
If the sense outputs (pin 11) of two or more chips are wired
together, the comparator and low battery detector will cause
all outputs to switch.
The output transistor is a 0.5A Darlington. Included in this
structure are two clamp diodes. D4 clamps positive collector
voltage excursions to the supply, and D5 clamps negative
excursions to ground.

In many applications the on-Chip references can provide
bias points. The references are driven from D1S, and buffered by 018 and 019. If only one bias point is needed the
first reference (pin 2) should be used, and the unused output (pin S) may be left open. The tiny leakage currents in
018 can cause 019 (pin S) to drift upward if a 10 MO load
resistor is not included at pin 2. The combined output current from pins 2 and S should not exceed 1 mA. If neither
reference output is used, pins 2 and S should be left open.
The last section of the LM1801 is the supply zener. It is built
from a series combination of two diodes and two zeners.
The breakdown voltage at 1 mA is 14.5V, and the series
resistance is about 2000. In line operated applications the
zener may be used for supply regulation or transient protection. The zener is designed to carry up to 10 mA.

5-100

Applications Hints

.-s::

(Continued)

DESIGN HINTS

The output stage can drive lamps, LEOs, buzzers, beepers,
relays, motors, and solenoids. However, the low battery detector is not compatible with every load. Since the low battery detector generates only a short pulse (60 ms typical), it
is intended for use with buzzers and beepers. Depending on
the response time and resonant frequency, some buzzers
may only produce a single click. Self-oscillating beepers
usually start instantly and produce a recognizable "tweet"
when a low battery condition is detected. Incandescent
lamps, large relays and solenoids will do absolutely nothing
when pulsed by the low battery detector.
Self-oscillating beepers are readily available, such as the
Sonalert SNP428 and the Panasonic EAL-069A. These
units are guaranteed to self-start when power is applied.

If the comparator inputs are subjected to electrostatic discharges (ESD), a series resistance is recommended to provide protection. Given the low input bias currents, 100 kn
resistors can be added without affecting circuit performance, yet they greatly enhance static protection. The
LM1801 is not designed to withstand reverse battery.
With a 10 Mn Rset, the LM1801 responds to an input in
approximately 2.5 ILs, and turns OFF in 200 ILs. Higher set
currents decrease the response time. With Rset = 1 Mn,
the output switches low in 0.5 ILs, and high in 50 ILs, and
with Rset = 100 kn, the response times are reduced to
0.2 ILs and 12 ILs.
When the circuit is in the standby state (V5 > V4), the current consumption in a typical application such as Figure 1 is
less than approximately 7 ILA. However, when the comparator switches LOW (V4 > V5), the supply current increases
to 3 mA owing to the Darlington base current. Therefore, to
realize maximum battery life, any application should be devised so that V5 > V4 in the standby or resting state.

To defeat the low battery detector, short pins 12 and 14
together, and do not connect them to anything else.
Circuit board assembly procedures should include a thorough cleaning to remove flux and other residues. The input
pins are often biased by very high impedance sources and
even a 10 Mn leakage path can upset circuit operation.

tt

N.C.

SENSE
INPUT

S.BV ....._ _ _--:-••_ _•.,.
.. .J

Rl

10M!l

••.•••/**
,/"',"/.1 M!l

t

R2

TL/H/9139-3

R,

+ R2

~

10 Mn

R1 + R2)
VTRIP ~ ( ~ 5.SV
Minimum trip voltage = 5.8V
"'Use series resistor for supplies> 14V. Select for IZENER = 5 mA.
""Reverse connections and add 1 M!1 resistor for Qvervoltage indication.
'[Optional filter capacitor, 1 nF to lOa nF.
ttPush to reset. Eliminate pin 6 connection for non-latching operation.

FIGURE 3. Under (Over) Voltage Indicator

5-101

.....
IX)
o
.....

.,...
o
CO
.,...

Applications Hints (Continued)

:!!

v·

..J

100 JLF

*

+

14

10

SENSE
INPUT

Rl

CROWBAR
100

R2

RSET

10M.o.

t

I
TL/H/9139-4

Rl

+

R2

~

10 Mn

Rl + R2)
VTRIP ~ ( -R-2S.BV
'Use series resistor for supplies> 14V.
tOptional filter capacitor, 1 nF to 100 nF.

FIGURE 4. Overvoltage Crowbar

5-102

.-3:
....
o....

Applications Hints (Continued)

CC)

9V
I
I
I
I
I
I

51 k.o.

I
I

...--....._-+c: 20k'O'

:
RSENSOR I

1100 nF
: MYLAR

._----I

:

I
I

-------_ .

POTTED

I SENSOR

TL/H/9139-5

To set trip point, trim VAEF to 4.5V. Trim RSENSOA at room temperature (23°C) for:
273

VSENSOA

+

23)

= 4.5 ( TX + 273

where TX is the desired trip point temperature in ac. As shown. the alarm is activated for over temperature conditions. Reverse the comparator connections for
under temperature alarm. The 20 kO potentiometer allows an adjustment range of - 55°C to + SOGG. Add a 10k fixed resistance in series with the potentiometer for
a

+ 50°C to + 125°C adjustment range.

RSENSOR can be replaced by a fixed resistor once the desired value is found. VREF is used as a final adjustment.

FIGURE 5. Over (Under) Temperature Alarm

LI
5-103

T-

o

co
T-

:s
..J

r-----------------------------------------------------------------------------------------,
Applications Hints (Continued)

1 M.!l

lM.!l

RESET
SWITCH

(N.C.)
4.7M.!l
7.SM.!l

ALARM
SWITCH

(N.C.)

7.SM.!l

ALARM

~SWITCH

~(N.O.)

TL/H/9139-6

FIGURE 6. Simple Alarm Circuit

RSET
10M.!l

10M.!l

-§l ALARM
SWITCH
~(N.C.)

I

l

NORMAL

BYPASSO
10nF (RESET)l
TL/H/9139-7

FIGURE 7. Full-Featured Intrusion Alarm

5·104

.......
==
CD
......

~ Semiconductor
NatiOnal

N

Corporation

LM 1812 Ultrasonic Transceiver
General Description
The LM 1812 is a general purpose ultrasonic transceiver designed for use in a variety of ranging, sensing, and communications applications. The chip contains a pulse-modulated
class C transmitter, a high gain receiver, a pulse modulation
detector, and noise rejection circuitry.
A single LC network defines the operating frequency for
both the transmitter and receiver. The class C transmitter
output drives up to 1A (12W) peak at frequencies up to
325 kHz. The externally programmed receiver gain provides
a detection sensitivity of 200 J.'Vp-p. Detection circuitry included on-chip is capable of rejecting impulse noise with
external programming. The detector output sinks up to 1 A.
Applications include sonar systems, non-contact ranging,
and acoustical data links, in both liquid and gas ambients.

Features
• One or two-transducer operation
• Transducers interchangeable without realignment

•
•
•
•
•
•

No external transistors
Impulse noise rejection
No heat sinking
Protection circuitry included
Detector output drives 1A peak load
Ranges in excess of 100 feet in water, 20 feet in air

• 12W peak transmit power

Applications
• Liquid level measurement
• Sonar
• Surface profiling
•
•
•
•

Data links
Hydroacoustic communications
Non-contact sensing
Industrial process control

Typical Application
V+o----------------.----------u------~~~--------------------------------,

+- -- -

GAIN CONTROL

CAN·1A901HM

3D

T6

NC

14

V·

~ ~~V

13

18

10.-____________.... 15

MOTOR

-=

T14

719VXA·A018YSU·

+-----------------L6

1:10
C13

'---------------..... 250 pF
+16V

1.5 nF

C18
2.2 nF

~~70PF/16V
~AYNEON

Order Number LM1812N
See NS Package Number N18A

TLlH/7892-1

tNote: Echo returns are displayed by a neon lamp on a motor driven disc. Connections to the neon are made through brushes and slip rings. Rotating with
and counterbalancing the neon lamp is a permanent magnet whose field induces a pulse in a stationary coil (L8) as it passes by. This pulse keys the
LM1812's transmitter.
'Available from Toko America, 1250 Feehanville Drive, Mount Prospect, Illinois 60056 Tel. (312) 297-0070
"Available from Massa Products Corporation, 280 Lincoln Street, Hingham, Massachusetts 02043 Tel. (617) 749-4800

FIGURE 1.200 kHz Depth Sounder, 5 Feet to 100 Feet

5·105

r---------------------------------------------------------------------------------,
....
co
Absolute Maximum Ratings
....
~

:!l

.....

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, V+ (Pin 12)
1BV
Power Dissipation (Note 1)
Peak Current (Pins 6, 14)
Input Current (Pins 4, B)

Operating Temperature

O'Cto +70'C

Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)

- 65'C to + 150'C
260'C

1700mW
1A
50mA

Electrical Characteristics v+
Parameter

= 12V, TA = 25'C, unless otherwise noted

Conditions

Input Sensitivity (Note 2)
Input Noise
Transmitter Output, VSAT

Figure 2

Transmitter Output Leakage

V6 = 36V
V8 = OV

Min

Is = 1A

Detector Output, VSAT

114

Detector Output Leakage

V14 = 36V

Transmitter Key Threshold

Ie = 1 mA

Supply Current

Typ

Max

Units

200
10
1.3

600
3

/-LVp·p
/-LVp·p
V

0.01

1

mA

1.5

3

V

0.01

1

mA

0.55

0.7

0.9

V

11 + 112
Receive Mode

5

8.5

20

mA

Transmit Mode

200

325

=c 1A

VB for Receive Mode

0.3

Maximum Operating Frequency

V
kHz

Note 1: For operating at high temperatures, the LM1812 must be derated based upon a 125'C maximum junction temperature and a thermal resistance of
58'C C/W which applies for the device soldered in a printed circuit board and operating in a still air ambient. Due to the low duty cycle operation, only a small
average power is dissipated in the package.
Note 2: A 47k resistor is added in parallel with the receiver tank at pin 1 to swamp variations in the coil's unloaded C. The resistor reduces sensitivity (see equation
4) and Is unnecessary In an actual applications circuit.

Test Circuit
V+=12Vo---------~~--------------------------------~.__,

t~
I ~ 1.35 mH

'\
499

~bN

,~

VJN

1

loOk

1

12

~n~

Vo

.!!

LM1S12

.....2.

~F~'

]]15 rS .-ko117 r
..E2 nF

-r-

nF

-r-

• 5.1k

•

~O nF

-,--

IS

T

~O nF

TL/H/7892-2

fiN = 200 kHz
Input sensitivity

= minimum VIN for Va to go low
FIGURE 2. Sensitivity Test Circuit

5·106

r-

....s:::
....

Application Hints

QI)

External Component Descriptions
Typical Values

N

Pin

Component

1

Ll,Cl

500 fLH-50 mH
250 pF-2.2 nF

Second gain stage output!
transmitter oscillator

Pin Description

Component Function

2

C2

500 pF-l0 nF

Second gain stage input

Couples first and second gain stage

Set the operating frequency (fa) for
the transmit oscillator and receiver

3

R3

5.1 kfl

First gain stage output

Terminates emitter-follower output

4

C4

100pF-l0nF

First gain stage input

Input coupling for the first gain stage

6

L6

50 fLH-l0 mH

Transmitter output

Matches LM1812 to the transducer

7

-

-

Transmitter driver

-

8

R8

1 kfl-l0kfl

Transmitter key

Current limiter for keying pulses up to 12V

9

C9

100 nF-l0 fLF

Receiver second stage delay

Sets the receiver turn-on delay after
transmit (Figure 10)

11

Cll

220 nF-2.2 fLF

Detector output duty cycle limit

Limits the duty cycle of the detector
output (short to ground to defeat)

13

C13

100 fLF-l000 fLF

Transmitter supply decoupling

Decouples the transmitter power supply

14

T14

Lp;;' 50 mH
Ns/Np "" 10

Detector output

Drives neon display lamp

16

-

-

Output driver

-

17

RH, C17

22k-Open
10 nF-l0 fLF

Pulse integrator

Controls integration time constant
(Figure 19)

18

C18

1 nF-100 fLF

Pulse integrator reset

Controls integrator reset time constant
(Figure 14)

TRANSDUCERS
The most common transducer used with the LM1812 is the
piezo-ceramic type which is electrically similar to a quartz
crystal. Piezo-ceramic transducers are resistive at only two
frequencies, termed the resonant and antiresonant (fr, fal
frequencies. Elsewhere these transducers exhibit some
reactance as shown in Figure 3.

~

:>::

w

c
~

z
'"
'"
~

INDUCTIVE

900

'""- -911"

HT

The LM1812 is primarily used with a single transducer performing both transmit and receive functions. In this mode,
maximum echo sensitivity will occur at a frequency close to
resonance.
Transducer ringing is a troublesome phenomenon of single
transducer systems. After a transducer has been electrically
driven in the transmit mode, some time is required for the
mechanical vibrations to stop. Depending on the amount of
damping, this ringing may last from 10 to 1000 cycles. This
mechanical ring produces an electrical signal strong enough
(>200 fLVP-P) to hold the detector ON, thus masking any
echo signals occurring during this time.
A solution to this ring problem is to vary the receiver gain
from a minimum, just after transmit, to a maximum, when the
ring signal has dropped below the full-gain detection threshold. Since near-range echo signals are much stronger than
ring signals, close echos will still be detected in spite of the
reduced gain.
The gain is varied by attenuating the signal between pins 2
and 3 of the LM1812. Figure 4 shows such an arrangement.
An externally generated 12V pulse (Figure 17) keys the
transmitter and activates the attenuator. This pulse charges
C to a voltage set by P8, turning the FET OFF. C slowly
discharges through R, decreasing the gate voltage, which in
turn decreases the attenuation of the signal passing from
pin 3 to pin 2. Rand C are selected so that the FET is not

./

I

'",

(a)

CAPACITIVE

"\Vi'If

I.

(b)
I
TLlHI7B92-3

FIGURE 3_ Phase and Magnitude
of Transducer Impedance
For transmitting (to maximize electrical to mechanical elficiency), the transducer should be operated at its resonant
frequency. For receiving (to maximize mechanical to electrical efficiency), optimum operation is at antiresonance. In
two-transducer systems the resonant frequency of the
transmit transducer is matched to the antiresonant frequency of the receiver.

5-107

,..
co
,..

~ r-------------------------------------------------------------------------------~

Application Hints (Continued)

:E

The oscillator frequency is set by L 1-C1 and can be calculated from

...I

1
fo = 2," 4L1C1
12V-n
OV ..... L.....

(1)

The L1-C1 tank must have a minimum Rp of 10 kO where
Rp = 21TfoQL1

(2)

and Q = unloaded Q of L 1-C1 tank.
The output transformer (LS) is designed with the aid of Agure 6. Curves are shown for two common frequencies:
40 kHz and 200 kHz. For a given load impedance (RT, Figure 3b), a turns ratio for LS is determined. In order not to
exceed the transducer's specifications, the peak-to-peak
output voltage may need to be adjusted using the equation:

R3
5.1k

TL/H17892-4

*Available from National Semiconductor Corporation

FIGURE 4. Time Variable FET Attenuator
completely turned ON until all detectable ringing has
stopped. The duration of the ring is rarely specified by the
transducer manufacturer and must be experimentally determined.
When designing an ultrasonic ranging system, three
ducer parameters are very important:

Vp-p = 2V+

(~:)

(3)

To ensure that the output stage is not overloaded, a current
measurement must be made at pin S. While the first few
pulses of each transmit period may reach 2A or 3A, the
steady-state current spikes must not exceed 1A. Current
spikes are reduced by decreasing the turns ratio of LS.

trans-

1) resonant impedance (RT in Figure 3b)

The secondary of LS tunes with CS at the operating frequency, fo.

2) maximum peak-ta-peak voltage
3) resonant frequency, fr
This data, used in conjunction with the curves given in
Figure 6, results in a functional output stage design.

co

~
'"

TRANSMITTER

~

The transmitter (Figure S) consists of an oscillator, a 1 ".S
one-shot, and a power amplifier.

1

~I~

When the transmitter is keyed ON at pin 8 the L 1-C1 tank is
switched to the oscillator mode. An on-Chip 1 ".S one-shot is
triggered with each cycle of the oscillator and, in turn, drives
a power amplifier. This one-shot has a reset time of 2 ".S,
limiting the maximum operating frequency to about 325 kHz.
A transformer couples the transducer to the output stage.

6:1

200 kHz

5:1
4:1
3:1 . /

40 kHz

2:1
1:1

o

100

lk
RT-LOAD RESISTANCE (0)

10k
TL/H17892-5

FIGURE S. LS Turns Ratio vs Load Resistance

v+
12

t

I

10

Cl

13

7.5k
7

TRANSMIT

KEY

TL/H17892-6

FIGURE 5. Transmitter

5-108

r-

Application Hints

s:
......

(Continued)

Q)

pled to the transducer, some protection is necessary to limit
the input current spikes to less than 50 mA. Where the voltage across the transducer is less than 200 Vp-p, a C4 reactance of 5 k!l at the operating frequency is adequate protection. Above 200 Vp-p, a 5 k!l resistor should be inserted
in series with C4.

Where additional power is desired, a pulse amplifier or a
pulse stretcher can be used as shown in Figure 7. The pulse
amplifier (Figure 7a) increases output current up to 5A. The
pulse stretcher (Figure 7b) increases output current and
pulse width. The wider pulse of Figure 7b is especially useful
at lower frequencies where the relatively narrow 1 "'S pulse
creates a large peak current demand for a given power level. Pulse width as a function of R is plotted in Figure B.

Since the L l-Cl tank circuit is shared with the oscillator,
both the transmitter and receiver are always tuned to the
same frequency. The second stage voltage gain is given by:

Pin 8 performs the function of switching the LM1812 into
either the transmit or receive mode. When pin 8 is held high,
the chip is in the transmit mode. When held low, it is in the
receive mode. The input current at pin 8 should be deSigned
to operate within a 1 mA-1O mA range.

Av =

~ fIT

(4)

70Ve:;

where Q

=

unloaded Q of L1-Cl tank.

When the LM1812 is in the transmit mode, the second gain
stage is turned OFF. When switching back to the receive
mode, the gain stage does not turn ON immediately, but
instead turns ON after a slight delay as programmed by C9.
This delay blanks the receiver (and therefore the detector)
momentarily, giving the transducer time to stop ringing.

RECEIVER
The receiver section (Figure 9) contains two separate gain
stages.
In some applications large voltages are applied across the
transducer during transmit. Since the receiver input is cou-

v+

C6

TRANSDUCER

TL/H17892-7

FIGURE 7a. Pulse Amplifier
TL/H/7892-8

FIGURE 7b. Pulse Stretcher
10
8

t

ILl

v

I

V
1

/'

1

C4

~
4

6

8 10

PULSE WIDTH (~s)
TL/H17892-9

FIGURE 8. Pulse Stretcher
Resistance vs Pulse Width

Av

~

24dB

TL/H/7892-10

FIGURE 9. Receiver Section

5-109

......

I\)

Application Hints (Continued)
Delay as a function of C9 is plotted in Figure 10. The second
gain stage may be shut OFF independently of pin 8 by pulling pin 9 low.

PULSE DETECTOR
The pulse detector circuitry (Figure 12) consists of five distinct stages: 1) threshold detector, 2) pulse integrator reset,
3) pulse integrator, 4) output driver, 5) power output stage.

Due to the high gain of the receiver, care must be taken to
avoid oscillations. Oscillation problems are reduced by
keeping the components associated with pins 1 and 4 well
separated (Figure 11). The transducer must be connected
to the circuit with shielded cable. This not only helps avoid
oscillation, but also reduces electrical noise pick-up. As a
last resort, receiver gain can be reduced with R3 as in Figure 1.

The detector (01, 02) switches on all pin 1 signals th~t
exceed 1.4 Vp-p. Since noise pulses are also detected, filtering is done by an integrator stage, C17 and R17, :-v~ose
time constant is typically 10% to 50% of the transmit time.
Integration starts when 03 turns OFF, which occurs at the
same moment 01 and 02 detect a signal. Pins 16 and 14 go
low after the integration delay.

100

g

~

10

'">w

~

0.1

1

C4

10

TLlH17892-12

C9 (pF)

FIGURE 11. Component Side of Layout Showing
Isolation of Receiver Input and Output

TL/H17892-11

FIGURE 10. Receiver Delay vs C9

117

lk

R17

20k

20k

FROM
PIN 1

(I)

(2)

(3)

(4)
TLlH/7892-13

FIGURE 12. Simplified Circuit Diagram of Detector

5-110

,-----------------------------------------------------------------------------, r

s:
.....

Application Hints (Continued)
When the voltage at pin 1 becomes too small to activate the
detector « 1.4 Vp-p), the integrator is reset by 03 after a
delay introduced by C18. A delay of 1 to 10 cycles of the
transmitted frequency is typical. These integration and reset
delays, as a function of the external component values, are
shown in Figures 13 and 14.
Pin 16 provides a CMOS compatible logic output. For driving
high-intensity displays, pin 14 will sink up to 1A. When driving a transformer such as T14 in Figure 1, it is possible for
the primary current to integrate up to destructive levels under conditions of multiple echo reception. Pin 11 is employed to protect the power output (pin 14). C11 integrates
an internal current source while pin 14 is low. When V11
reaches a 0.7V threshold, the second gain stage is turned
OFF. With the receiver OFF, no signal will be applied to the

detector, and pin 14 will turn OFF. After another delay C11
is discharged and the receiver is then again activated. With
C11 = 680 nF and a continuous echo return, the receiver
will cycle ON and OFF every 6 ms. This function can be
defeated by grounding pin 11.
TYPICAL OPERATION
Figure 15 shows typical waveforms at pins 1 and 16 for
200 kHz operation, with pin 9 left open. The pin 1 oscillator
signal (5 Vp-p) lasts for 200 /Ls. The next 900 /Ls show a
ring signal so strong that it is clipped by the receiver. The
exponential nature of the decaying ring is seen for the next
500 /Ls. An echo return appears at 3.9 ms. Note that the
detector is held low during the transmit period and for the
duration of the ring.
10

10

I

!

;

\)~

~?

~

0.1

~~

0.01

ii5

~

tz.

i'"

,,"

~H

~

0.1

~

ii5

0.001
0.1

10

100

10

1000

100

1000

CIS (nF)

C17InF)

TL/H/7892-15

TL/H/7892-14

FIGURE 14. Integrator
Reset Delay vs C18

FIGURE 13. Integration
DelayvsC17

PIN 1, 5V/DIV

PIN 16, 5V/DIV

TlME=500 I's/DIV
TL/H17892-16

FIGURE 15. Typical Transmit/Receive Waveforms

5-111

co
.....
N

N
.....
co
..... Application Hints (Continued)

:::i!l

....I
V+=12Vo---....- - -....- - - - ,

tIl66

lM1B12

I
I
I

13

I
+ C13

x

I

C6
1.5 nF

470 pF

R3
5.1k

RB
10k

-n

12V
OV.....J

-I

L..

KEY INPUT

1-200ps
Tl/H/7B92-17

Ll = CAN·1A901HM (Toko)
L6 = 719VXA-A018YSU (Toko)
X = R2B3E (Massa Producls)

FIGURE 16.200 kHz Ultrasonic Ranging System for 4 Inches to 6 Feet in Air
V+=l~o-~~--_.-----~-------------~------~~--_,

t
R17
47k

I

Uk

C17
100 nF

t l6

lM1812

lM555

I

13

75k

lN914

I

I
I
C13
470pF

I
I

C6
15 nF

R8
10k
TL/HI7B92-1B
L1 = CLN-2A900HM (Toko)
L6 = 719VXA-A017AO (Toko)
X

= EFR-OTB40K2 (Available from Panasonic Company, 1 Panasonic Way, Secaucus, NJ 07094, Tel. (201) 392-4511)
FIGURE 17.40 kHz Ultrasonic Ranging System Covering a Range of 3 Feet to 20 Feet
5-112

r--------------------------------------------------------------------------------.
NatiOnal

~ Semiconductor

U'I

LM 1815 Adaptive Sense Amplifier
General Description

Features

The LM1815 is an adaptive sense amplifier and default gating circuit for motor control applications. The sense amplifier provides a one-shot pulse output whose leading edge
coincides with the negative-going zero crossing of a ground
referenced input signal such as from a variable reluctance
magnetic pick-up coil.

•
•
•
•
•
•

In normal operation, this timing reference signal is processed (delayed) externally and returned to the LM1815. A logic
input is then able to select either the timing reference or the
processed signal for transmission to the output driver stage.
The adaptive sense amplifier operates with a positive-going
threshold which is derived by peak detecting the incoming
signal and dividing this down. Thus the input hysteresis varies with input signal amplitude. This enables the circuit to
sense in situations where the high speed noise is greater
than the low speed signal amplitude. Minimum input signal
is 100 mVp-p.

Connection Diagram

Adaptive hysteresis
Single supply operation
Ground referenced input
True zero crossing timing reference
Operates from 2V to 12V supply voltage
Handles inputs from 100 mV to over 120V with external
resistor
• CMOS compatible logic

Applications
•
•
•
•
•

NC

GND

Position sensing with notched wheels
Zero crossing switch
Motor speed control
Tachometer
Engine testing

Truth Table
Signal
Input

Dual-In-Line Package
NC

......

co

Corporation

RC
TIMING

r3:

REFERENCE
PULSE OUT

INPUT
SELECT

GATED
OUTPUT

SIGNAL
INPUT

NC

THRESHOLD
ADJUST

TIMING
PULSE
INPUT

NC

v,

PEAK
DETECTOR
CAPACITOR
TL/HI7893-1

Top View
Order Number LM1815N
See NS Package Number N14A

5-113

Input
Select

Timing
Input

Gated
Output

Pulses

L

X

Pulses

X

H

Pulses

Pulses

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

Input Current

±30mA

Lead Temperature (Soldering, 10 sec.)

- 40'C to

25'C, Vee = 10V, unless otherwise specified, see Figure 1)

Conditions

Supply Current

fiN = 500 Hz, Pin 9 = 2V,
Pin 11 = 0.8V

Reference Pulse Width

fiN = 1 Hzto2kHz

Input Bias Current

VIN = 2V, (Pin 9 and Pin 11)

Input Bias Current

VIN = OV dc, (Pin 3)

Input Impedance

VIN = 5 Vrms, (Note 3)

Zero Crossing Threshold

VIN = 100 mVp·p, (Pin 3)

Min

Typ

Max

Units

2.5

10

12

V

3.6

6

mA

100

130

p.s

5

p.A

28

kfl

25

mV

2.0

V

70

200
12

20

Logic Threshold

(Pin 9 and Pin 11)

0.8

1.1

VourHigh

RL = 1 kfl, (Pin 10)

7.5

8.6

Vour Low

ISINK = 0.1 mA, (Pin 10)

Input Arming Threshold

Pin 5 Open, VIN ,;; 135 mVp-p

Saturation Voltage P12

260'C

+ 125'C

Operating Supply Voltage

Output Leakage Pin 12

-65'Cto

1250 mW

Electrical Characteristics (TA =
Parameter

+ 150'C
+ 125'C

Storage Temperature Range

12V

Power Dissipation (Note 1)
Operating Temperature Range

Junction Temperature (Note 2)

nA

V

0.3

0.4

V

30

45

60

mV

80

90

%OfV3Pk

25

mV

Pin 5 Open, VIN ;;, 230 mVp-p

40

Pin5toV+

200

Pin 5toGnd

-25

mV

V12 = 11V

0.Q1

10

p.A

112=2mA

0.2

0.4

V

Note 1: For operation at elevated temperatures, the device must be derated based on a 125"C maximum iunction temperature and a thermal resistance of 80"C/W
junction to ambient.

Note 2: Temporary excursions to 150°C can be tolerated.

Note 3: Measured at input to external 18 kll resistor. IC contains 1 kn in series with a diode to attenuate the input signal.
nWING
REFERENCE

v'
t =0.6730e 0

INPUT
SElECT

PULS~ OUT

L

,50.4

O'OO'I',F"

113

10
0I£-5HOT 0
TR~

5.6'4

PULSE

INPUT

. {-=

11

12

•

10

•

@

~

LM'8,5

-=

~
....
+

+ -

I'

..1£0
OUTPUT

~

3

1Sk.o.

v~9
IN

+

15

I'

SIGNAL

~

4-

16

~

~~
DETECTOR

CAPACITOR

FIGURE 1. LM1815 Adaptive Sense Amplifier

5-114

TLlH/7893-2

~--------------------------------------~r

::
.....

Schematic Diagram

co
.....

ii!!lg
..

U'I

'

1-::v

1\-8r{'

&H~

q%~

0

~

~

I
if-' '/
;--

r'

1..8

r-\.

rt

~

~J
~

K

~

"

I i~
~~

~~,~

~~
~A

~N

Yt~~

L.::r

~

y

,.p

~~

0

d:

~

~

:::~

~

*-v

~

~

)1

o

y

~

.:"

Q

,0-

r

2J~

~N

~~

§

§

i

j

~~

~~

-

~

~~

~:
0-

~~

~~{iL
0

rt

c:~

y
\y-

ri~

:~tr

c;c:::

~

~~

riL-

~

( 01

l~

~;i

L::r
~~

~~

~~

';.L

~l
o:~

iil~

~~

"

~:

2
TLlHI7B93-4

5-115

U) r---------------------------------------------------------------------------~

...-

co
...:IE

INPUT
THRESHOLD
VOLTAGE

-J

~

5V

IOO~s

+.OI2V

100~s

REFERENCE
PULSE
OUTPUT

1,1

NOISEY
INPUT
SIGNAL

l

n

1/

~

I

:\ J

200V

r

~[Ir

\rJ

TLlH17893-3

FIGURE 2. LM1815 Oscillograms

Application Hints
Input Clamp
The signal input at pin 3 is internally clamped. Current limit
is provided by an external resistor which should be selected
to allow a peak current of 3 mA in normal operation. Positive
inputs are clamped by a 1 ko' resistor and series diode,
while an active clamp limits pin 3 to -350 mV for negative
inputs (see R4, 012, 011 in internal schematic diagram).
Operation of Zero Crossing Detector
The LM1815 is designed to operate as a zero crossing detector, triggering an internal one shot on the negative-going
edge of the input signal. Unlike other zero crossing detectors, the LM1815 cannot be triggered until the input signal
has crossed an "arming" threshold on the positive-going
portion of the waveform. The arming circuit is reset when
the chip is triggered, and subsequent zero crossings are
ignored until the arming threshold is exceeded again. This
threshold varies depending on the connection at pin 5.
Three different modes of operation are possible:
MODE 1, Pin 5 open. The adaptive mode is selected by
leaving pin 5 open circuit. For input Signals of less than
135 mVp-p, the input arming threshold is typically 45 mY.
Under these conditions the input signal must first cross the
45 mV threshold in the positive direction to arm the zero
crossing detector, and then cross zero in the negative direction to trigger it. If the signal is less than 30 mV peak (minimum rating in Electrical Characteristics), the one shot is
guaranteed to not trigger.
Input signals of greater than 230 mVp-p cause the arming
threshold to track at 80% of the peak input voltage. A peak
detector (pin 7) stores a value relative to the positive input
peaks to establish the arming threshold. Input signals must
cross this threshold in the positive direction to arm the zero
crossing detector, which can then be triggered by a negative-going zero crossing. The peak detector tracks rapidly as

the input Signal amplitude increases, and decays by virtue of
the resistor connected externally at pin 7 to track decreases
in the input signal.
Note that since the input is clamped, the waveform observed at pin 3 is not identical to the waveform observed at
the variable reluctance sensor. Similarly, the voltage stored
at pin 7 is not identical to the peak voltage appearing at
pin 3.
MODE 2, Pin 5 connected to V +. The input arming threshold is fixed at 200 mV minimum when pin 5 is connected to
the positive supply. The chip has no output for signals of
less than 200 mV peak, and triggers on the next negativegoing zero crossing when the threshold is crossed.
MODE 3, Pin 5 grounded. With pin 5 grounded, the input
arming threshold is set to OV (± 25 mV maximum). PositivegOing zero crossings arm the chip, and the next negative
zero crOSSing triggers it.
The one shot timing is set by a resistor and capacitor connected to pin 14. The output pulse width is
pulse width = 0.673 RC
(1)
In some systems it is necessary to externally generate pulses, such as during stall conditions when the variable reluctance sensor has no output. External pulse inputs at pin 9
are gated through to pin 10 when the Input Select (pin 11) is
pulled high. Pin 12 is a direct output for the one shot and is
unaffected by the status of pin 11.
Input/output pins 9,11,10 and 12 are all CMOS logic compatible. In addition, pins 9,11 and 12 are TIL compatible.
Pin 10 is not guaranteed to drive a TIL load.
Pins 1, 4, 6 and 13 have no internal connections and can be
grounded.

5-116

ril!:
.....

NatiOnal

~ Semiconductor

.....
Q)

CD

Corporation

LM 1819 Air-Core Meter Driver
General Description

Features

The LM1819 is a function generator/driver for air-core
(moving-magnet) meter movements. A Norton amplifier and
an NPN transistor are included on chip for signal conditioning as required. Driver outputs are self-centering and develop ±4.5V swing at 20 mAo Better than 2% linearity is guaranteed over a full 305-degree operating range.

•
•
•
•

Self-centering 20 mA outputs
12V operation
Norton amplifier
Function generator

Applications
• Air-core meter driver
• Tachometers
• Ruggedized instruments

Typical Application
VBAT=14.4V

04
R5
R7
1N4a07 3.3k
3.3'
FROM --1"'-,\M~~---""'.J\II""'-,

SIGNAL

IS

POINTS

01'
lN4007

R6
10k

R3
lOt

02
2N4746t

+ C3

~~~,.Ft ....._ _-+.,

18Y

Rl
4.7k

lW

RZ"
330.

Cl'
10nF

MOVING MAGNET METER"
TLlH/5263-1

FIGURE 1. Automotive Tachometer Application. Circuit shown operates
with 4 cylinder engine and deflects meter pointer (270") at 6000 RPM.

Order Number LM1819N
See NS Package Number N14A
'TRW Type X463UW Polycarbonate Capacitor
"RNGOD Low TC Resistor (± 100 ppm)
tCompanents Required for Automotive Load Dump Protection

H Available from FARIA Co.
POBox 983, Uncasville, CT 06382
Tel. 203-848-9271

5-117

en
....
....:isco
....

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, V+ (pin 13)
20V
Power Dissipation (note 1)

Electrical Characteristics Vs =
Symbol
Is
VREG

VREF

hFE

1300mW

Conditions

13

Zero Input Frequency
(See Figure 1)

Min

Regulator Voltage

11

IREG = OmA

Regulator Output Resistance

11

IREG = OmAt03mA

Reference Voltage

4

IREF = OmA

Reference Output Resistance

4

Norton Amplifier Mirror Gain

5,6

NPN Transistor DC Gain

9, 10

Drive Voltage Extremes,
Sine and Cosine
Sine Output Voltage
with Zero Input

260'C
20VMIN

13.1VTA = 25'C unless otherwise specified
Pin(s)

Parameter

-40'Cto +85'C
-65'Cto -150'C

BVCEO

Supply Current

Function Generator Feedback
Bias Current

k

Operating Temperature
Storage Temperature
Lead Temp. (Soldering, 10 seconds)

1
2,12
2

Typ

8.1

8.5

Units

65

mA

8.9

V

13.5
1.9

2.1

n
2.3

V

5.3

IREF = 0 /LA to 50 /LA
0.9

IBIAS '" 20/LA

Max

1.0

kn
1.1

125
V1 = 5.1V
ILOAD = 20 mA
Va = VREF

Function Generator Linearity

FSD = 305'

Function Generator Gain

Meter Deflection/ b. Va

1.0

mA

±4

±4.5

V

-350

0

+350

mV

±1.7

%FSD

50.75

53.75

56.75

'/V

Note 1: For operation above 25°C, the LM1819 must be derated based upon a 125°C maximum junction temperature and a thermal resistance of 76°C/W which
applies for the device soldered in a printed circuit board and operating in a still·air ambient.

Application Hints
AIR·CORE METER MOVEMENTS

H fields (Figure 3(c)). H is proportional to the voltage applied
to a coil. Therefore, by varying both the polarity and magni·
tude of the coil voltages the axle assembly can be made to
rotate a full 360'. The LM1819 is designed to drive the me·
ter through a minimum of 305'.

Air·core meters are often favored over other movements as
a result of their mechanical ruggedness and their indepen·
dence of calibration with age. A simplified diagram of an air·
core meter is shown in Figure 2. There are three basic
pieces: a magnet and pointer attached to a freely rotating
axle, and two coils, each oriented at a right angle with respect to the other. The only moving part in this meter is the
axle assembly. The magnet will tend to align itself with the
vector sum of H fields of each coil, where H is the magnetic
field strength vector. If, for instance, a current passes
through the cosine coil (the reason for this nomenclature
will become apparent later) as shown in Figure 3(a), the
magnet will align its magnetic axis with the coil's H field.
Similarly, a current in the sine coil (Figure 3(b) causes the
magnet to align itself with the sine H field. If currents are
applied simultaneously to both sine and cosine coils, the
magnet will turn to the direction of the vector sum of the two

POINTER ~
fc--AXLE

MAGNET'i

f{ ~'",E'"

~-- if)
""'"

SINE COIL

TL/H/5263-2

FIGURE 2. Simplified Diagram of an Air Core Meter.

5·118

r
3:
.....

Application Hints (Continued)

co
.....
CD

E€~~l~~3=( SINE
COIL
I....,..
COSINE
COIL

COSINE
COIL

COSINE
COIL
TLlH/5263-3

W

00

00

FIGURE 3. Magnet and pOinter position are controlled by the H field generated by the two drive coils.
In an air-core meter the axle assembly is supported by two
nylon bushings. The torque exerted on the pOinter is much
greater than that found in a typical d' Arsonval movement. In
contrast to a d' Arsonval movement, where calibration is a
function of spring and magnet characteristics, air-core meter calibration is only affected by the mechanical alignment
of the drive coils. Mechanical calibration, once set at manufacture, can not change.

Comparing [3] to [2] we see that if HSINE varies as the sine
of 0, and HCOSINE varies as the cosine of 0, we will generate a net H field whose direction is the same as O. And since
the axle assembly aligns itself with the net H field, the pointer will always point in the direction of O.
THELM1819
Included in the LM1819 is a function generator whose two
outputs are designed to vary approximately as the sine and
cosine of an input. A minimum drive of ±20 rnA at ±4V is
available at pins 2 (sine) and 12 (cosine). The common side
of each coil is returned to a 5.1 V zener diode reference and
fed back to pin 1.

Making pOinter position a linear function of some input is a
matter of properly ratioing the drive to each coil. The H field
contributed by each coil is a function of the applied current,
and the current is a function of the coil voltage. Our desired
result is to have 0 (pointer deflection, measured in degrees)
proportional to an input voltage:

For the function generator, k"'54'1V (in equation 1). The
input (pin 8) is internally connected to the Norton amplifier's
output. VIN as considered in equation [1] is actually the difference of the voltages at pins 8 (Norton output/function
generator input) and 4. Typically the reference voltage at pin
4 is 2.1 V. Therefore,

[1]

O=kVIN

where k is a constant of proportionality, with units of degrees/volt. The vector sum of each coils' H field must follow
the deflection angle O. We know that the axle assembly
always points in the direction of the vector sum of HSINE
and HCOSINE. This direction (see Figure 4) is found from the
formula:
(O)=arctan ( I HSINE I / I HCOSINE II
Recalling some basic trigonometry,
(0) = arctan(sin (0) / cosIO
HCOSINE + HSINE

»

O=k(Va-VREF) = 54 (Va-2.1)

[4]

As Va varies from 2.1V to 7.75V, the function generator will
drive the meter through the chip's rated 305' range.

[2]

Air-core meters are mechanically zeroed during manufacture such that when only the cosine coil is driven, the pointer indicates zero degrees deflection. However, in some applications a slight trim or offset may be required. This is
accomplished by sourcing or sinking a DC current of a few
microamperes at pin 4.

[3]
HSINE

A Norton amplifier is available for conditioning various input
signals and driving the function generator. A Norton amplifier was chosen since it makes a simple frequency to voltage
converter. While the non-inverting input (pin 6) bias is at one
diode drop above ground, the inverting input (5) is at 2.1V,
equal to the pin 4 reference. Mirror gain remains essentially
fiat to IMIRROR = 5 rnA. The Norton amplifier's output (8) is
designed to source current into its load. To bypass the Norton amplifier simply ground the non-inverting input, tie the
inverting input to the reference, and drive pin 8 (Norton output/function generator input) directly.
HCOSINE

~

_ _ _ _-l._ _- "

An NPN transistor is included on chip for buffering and
squaring input signals. Its usefulness is exemplified in Figures 1 & 6 where an ignition pulse is converted to a rectangular waveform by an RC network and the transistor. The
emitter is internally connected to ground. It is important not
to allow the base to drop below -5Vdc, as damage may
occur. The 2.1 V reference previously described is derived
from an 8.5V regulator at pin 11. Pin 11 is used as a stable
supply for collector loads, and currents of up to 5 rnA are
easily accommodated.

TLlH/5263-4

FIGURE 4. The vector sum of HCOSINE and HSINE points
in a direction 0 measured in a clockwise direction from
HCOSINE·

5-119

....enco r---------------------------------------------------------------------------------,
.... Application Hints (Continued)

::e
....I

TACHOMETER APPLICATION

A measure of the operating level of any motor or engine is
the rotational velocity of its output shaft. In the case of an
automotive engine the crankshaft speed is measured using
the units "revolutions per minute" (RPM). It is possible to
indirectly measure the speed of the crankshaft by using the
signal present on the engine's ignition coil. The fundamental
frequency of this signal is a function of engine speed and
the number of cylinders and is calculated (for a four-stroke
engine) from the formula:
f=nw/120
(Hz)
(5)

The charge pump circuit in Figure 7 can be operated in two
modes: constant input pulse width (C1 acts as a coupling
capacitor) and constant input duty cycle (C1 acts as a differentiating capacitor). The transfer functions for these two
modes are quite diverse. However, deflection is always directly proportional to R2 and ripple is proportional to C2.
The following variables are used in the calculation of meter
deflection:
symbol description
n
number of cylinders

where n = number of cylinders, and w = rotational velocity of
the crankshaft in RPM. From this formula the maximum frequency normally expected (for an 8 cylinder engine turning
4500RPM) is 300 Hz. In certain specialized ignition systems
(motorcycles and some automobiles) where the coil waveform is operated at twice this frequency (f = wI60). These
systems are identified by the fact that multiple coils are used
in lieu of a single coil and distributor. Also, the coils have
two outputs instead of one.
A typical automotive tachometer application is shown in Figure 1. The coil waveform is filtered, squared and limited by
the RC network and NPN transistor. The frequency of the
pulse train at pin 9 is converted to a proportional voltage by
the Norton amplifier's charge pump configuration. The ignition circuit shown in Figure 5 is typical of automotive systems. The switching element "S" is opened and closed in
synchronism with engine rotation. When "S" is closed, energy is stored in Lp. When opened, the current in Lp diverts
from "S" into C. The high voltage produced in Ls when "S"
is opened is responsible for the arcing at the spark plug.
The coil voltage (see Figure 6) can be used as an input to
the LM1819 tachometer circuit. This waveform is essentially
constant duty cycle. D4 rectifies this waveform thereby preventing negative voltages from reaching the chip. C4 and
R5 form a low pass filter which attenuates the high frequency ringing, and R7 limits the input current to about 2.5mA.
R6 acts as a base bleed to shut the transistor OFF when
"S" is closed. The collector is pulled up to the internal regulator by RREG. The output at pin 9 is a clean rectangular
pulse.

ro, WIDLE engine speed at redline and idle, RPM
I}

pOinter deflection at redline, degrees

8

charge pump input pulse width, seconds

VIN
AI}
k

peak to peak input voltages, volts
maximum desired ripple, degrees
function generator gain, degrees/volt

f, flDLE input frequency at redline and idle, Hz
Where the NPN transistor and regulator are used to create a
pulse VIN=8.5V. Acceptable ripple ranges from 3 to 10 degrees (a typical pOinter is about 3 degrees wide) depending
on meter damping and the input frequency.
The constant pulse width circuit is designed using the following equations:
(1)
100 p.A< VIN<3 mA
R1
C 108
(2)
1:?:"R;
Rll}
120Rl1}
R2=--- =----VIN8kf VINnw6k
C2
1
1
(4)
R2AIJ flDLE R2 A1JnwiDLE
The constant duty cycle equations are as follows:
(3)

RREG :?: 3 ko.
Rl ,;; VINX104 -RREG
Cl ,;; 6I10(RREG+Rl)
Rz = I} 13.54nwCl = I} 1425fCl
C2 = 425Cl1 AO
The values in Figure 1 were calculated with n = 4,
w=6000RPM, 1}=270 degrees, 6=1 ms, VIN is
VREG-0.7V, and AI}=3 degrees in the constant duty cycle
mode. For distributorless ignitions these same equations will
apply if wl60 is substituted for f.

Many ignition systems use magnetic, hall effect or optical
sensors to trigger a solid state switching element at "S."
These systems (see the LM1815) typically generate pulses
of constant width and amplitude suitable for driving the
charge pump directly.

5-120

.-is:

......

Equivalent Schematic

())

<0

5-121

....co r-----------------------------------------------------------------------------,
.... Typical Applications
~

~

11

REG

Rm
OUTPUT
TO CHARGE
PUMP

SPAlIK
PLUG

R7

C4

LM1819

10

R6
7,14

TLlH/5263-9

FIGURE 5. Typical Pulse-Squaring Circuit for
Automotive Tachometers.

OPENED

"S"
CLOSED

COIL
WAVEFORM

---1

L

I

C2

':~I----I~~1P----1

L

V9 B.5V
OUTPUT TO
--,
CHARGE PUMP OV
...._ - - '

TL/H/5263-11
TLlH/5263-10

FIGURE 6. Waveforms Encountered in Automotive
Tachometer Circuit.

FIGURE 7. Tachometer Charge Pump.

Voltage Driven Meter with Norton Amplifier Buffer
V+ =13.1V

Rz
120
lW

R2"

130K
COSINE

IN4733
RI
lOOk

TL/H/5263-5
Deflection=54 (VIN-.7)R2/Rl

(degrees)

o to 305' deflection is obtained with .7 to 5V input.
'Full scale deflection is adjusted by trimming R2.

5·122

r-

Typical Applications

....s::

...

(Continued)

CI)

CD

Unbuffered Voltage Driven Meter
V+ =13.1V

TLlH/5263-6
Deflection = S4(VIN - 2.1)

(degrees)

o to 305' deflection is obtained for inputs of 2.1 to 7.7SV.
Full scale deflection is adjusted by trimming the input voltage.

Current Driven Meter
V+ =13.1V
NC

NC

NC

Hz

120
lW

H250k

COSINE

lN4733

liN

TLlH/5263-7
Deflection = 54R211N

(degrees)

Inputs of 0 to 100 f'A deflect the meter 0 to 270'.

·Full scale deflection is adjusted by trimming R2.

5-123

....
co
....
G)

Typical Applications

(Continued)

::::i
..J

Level Shifted Voltage Driven Meter

v+ = 13.1V

Rz
120
lW
COSINE

1M

1M

TL/H/5263-B

Deflection = 54VIN

(degrees)

Inputs of 0 to 5.65V deflect the meter through a range of 0 to 305".
FUll scale deflection is adjusted by trimming the input voltage.

5-124

r
:5:
.....

~ Semiconductor
NatiOnal

co

w
o

Corporation

LM1830 Fluid Detector
General Description

Features

The LM1830 is a monolithic bipolar integrated circuit de·
signed for use in fluid detection systems. The circuit is ideal
for detecting the presence, absence, or level of water, or
other polar liquids. An AC signal is passed through two
probes within the fluid. A detector determines the presence
or absence of the fluid by comparing the resistance of the
fluid between the probes with the resistance internal to the
integrated circuit. An AC signal is used to overcome plating
problems incurred by using a DC source. A pin is available
for connecting an external resistance in cases where the
fluid impedance is of a different magnitude than that of the
internal resistor. When the probe resistance increases
above the preset value, the oscillator signal is coupled to
the base of the open·collector output transistor. In a typical
application, the output could be used to drive a LED, loud
speaker or a low current relay.

•
•
•
•
•
•

Low external parts count
Wide supply operating range
One side of probe input can be grounded
AC coupling to probe to prevent plating
Internally regulated supply
AC or DC output

Applications
•
•
•
•
•

Beverage dispensers
Water softeners
Irrigation
Sump pumps
Aquaria

•
•
•
•

Radiators
Washing machines
Reservoirs
Boilers

Logic and Connection Diagram
Dual-In-Line Package

Vee

OSCILLATOR
OUTPUT
IRAEfI
OUTPUT

OSCILLATOR

Ne

Ne

GNO

DETECTOR
INPUT

FILTER
CAP

Ne

Ne

OSCILLATOR

~c

OSCILLATOR

CAPACITOR

OUTPUT
TOP VIEW

Order Number LM1830N
See NS Package Number N14A

5·125

CAPACITOR

TLlH/5700-1

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Supply Voltage

Output Sink Current
Storage Temperature Range

28V

Power Dissipation (Note 1)

20mA

+ 85·C
-40·C to + 150·C
- 40·C to

Operating Temperature Range

260·C

Lead Temp. (Soldering, 10 seconds)

1400 mW

Electrical Characteristics (V+ = 16V, TA = 25·C unless otherwise specified)
Typ

Max

Units

Supply Current

Parameter

5.5

10

mA

Oscillator Output Voltage
Low
High

1.1
4.2

Min

Conditions

Internal Reference Resistor
Detector Threshold Voltage
Detector Threshold Resistance

8
5

Output Saturation Voltage
Output Leakage
Oscillator Frequency

lo=10mA
VPIN12=16V
C1 =0.00 l/l-F

V
V

13
680
10

25
15

kO
mV
kO

0.5

2.0
10
12

/l-A
kHz

7

4

V

Note 1: The maximum iunction temperature rating of the LM1B30N is 150·C. For operation at elevated temperatures, devices in the dual·in-line plastic package
must be derated based on a thermal resistance of Bf¥'C/W.

Schematic Diagram
OSCILLATOR
OUTPUT

V~C
14

10k

OSCILLATOR
OUTPUT
IRREFI

S

OPTIONAL
DETECTOR
FILTER
INPUT CAPACITOR

13

~

10

OUTPUT

9

12

13k

10k

9.61<
2Sk

2Sk

7V~ l-t

~

~IDk

~

3Dk

1
Cl

.....

>-4:f-*t::

~

ll~

_~:1

1

GND

Cl

5·126

~

TL/H/S700-2

Typical Performance Characteristics
Normalized Oscillator Frequency
vs Supply Voltage

Threshold Resistance vs Supply
Voltage

;;; 1.15

i'"
:il

:::

25
TA'25"C

W

TA ·25"C
20

"iii

u

1.05

~
::i

.."

" -

r--

0.95

W

N

:;
0.9

~

I-

15

1\

10

10

15

20

~

::
~

""

~

I-

o

o

z

25

30

2

o

10

SUPPLY VOLTAGE (VI

15

20

Reference Resistor vs Ambient
Temperature

2

z

16

~

~

14
12
10

l,...--

-

V

V

-20

'"~

0.8

>
~

0.6

::i

I-""

~

.~

r-

--

r-

20

40

60

BO

"

100

a

vcc -16V

voH

13

u

12

.::i"~
~

0.2

o
-40

-20

20

0

40

60

80

"'- f"'.

11
10

-40

100

r-.......

........

Output Saturation Voltage vs
Output Current

-20

0

20

40

10

20

~

'"

~:il
"

I
100

10

TEMPERATURE (OCI

BO

100

V~C·'~V-

lB
16
14
12

-

10
B

!"-.

i;l

BO

60

Oscillator Frequency vs
Ambient Temperature

~

60

j"-..

AMBIENT TEMPERATURE (OCI

........

40

VCC ·16V

W

val

20

30

~

..

-40 -20

25

m

:::
....
"
o

\.

AMBIENT TEMPERATURE ("CI

Oscillator VOH and VOL
vs Ambient Temperature

20

!li
I-

AMBIENT TEMPERATURE (OCI

I

g

::i"

0.4

t;
0

15

10

Probe Threshold Resistance
vs Temperature

z

I-

~

-40

0

SUPPLY VOLTAGE (VI

VCC ·16V-

W

~

30

Detector Threshold Voltage
vs Temperature

lB

W

25

SUPPLY VOLTAGE (VI

20

u

10

oS

z

;

i

~

1.1

l5

~
"

Power Supply Current vs
Supply Voltage

100

OUTPUT CURRENT (PIN 121 (mAl

I

L

o
-40 -20

0

20

40

60

BO

100

AMBIENT TEMPERATURE ("CI

Equivalent Resistance vs
Concentration of Several
Solutions
500
450

W

u

z

~f

400
350

a~
z" 300
"CI
U

W

~

~O4

r-

N!CI

250

ffiN~ 200

",
~g
~-

:il

150
100
50

o

0.001

-

0.01

NaAc
CuS04

"Ttl-

0.1

CONCENTRATION (GRAM MOLECULAR
EQUIVAlENTs/LITREI
TL/H/5700-3

5-127

Application Hints
The LM1830 requires only an external capacitor to complete the oscillator circuit. The frequency of oscillation is
inversely proportional to the external capacitor value. Using
0.0011-'F capacitor, the output frequency is approximately 6
kHz. The output from the oscillator is available at pin 5. In
normal applications, the output is taken from pin 13 so that
the internal 13k resistor can be used to compare with the
probe resistance. Pin 13 is coupled to the probe by a blocking capacitor so that there is no net dc on the probe.

It is possible to calculate the resistance of any aqueous
solution of an electrolyte for different concentrations, provided the dimensions of the electrodes and their spacing is
known.
The resistance of a simple parallel plate probe is given by:
1000 dO
R=--ec.p A
where A=area of plates (cm2)

Since the output amplitude from the oscillator is approximately 4 VBE, the detector (which is an emitter base junction) will be turned "ON" when the probe resistance to
ground is equal to the internal 13 kO resistor. An internal
diode across the detector emitter base junction provides
symmetrical limiting of the detector input signal so that the
probe is excited with ± 2 VBE from a 13 kO source. In cases
where the 13 kO resistor is not compatible with the probe
resistance range, an external resistor may be added by coupling the probe to pin 5 through the external resistor as
shown in Figure 2. The collector of the detecting transistor
is brought out to pin 9 enabling a filter capacitor to be connected so that the output will switch "ON" or "OFF" depending on the probe resistance. If this capacitor is omitted,
the output will be switched at approximately 50% duty cycle
when the probe resistance exceeds the reference resistance. This can be useful when an audio output is required
and the output transistor can be used to directly drive a loud
speaker. In addition, LED indicators do not require dc excitation. Therefore, the cost of a capacitor for filtering can be
saved.

d = separation of plates (cm)
c=concentration (gm. mol. equivalent/litre)
p = equivalent conductance
(0-1 cm2 equiv. -1)
(An equivalent is the number of moles of a substance that
gives one mole of positive charge and one mole of negative
charge. For example, one mole of NaCI gives Na + + CI- so
the equivalent is 1. One mole of CaCI2 gives Ca + + + 2CIso the equivalent is 1/2.)
Usually the probe dimensions are not measured physically,
but the ratio d/ A is determined by measuring the resistance
of a cell of known concentration c and equivalent conductance of 1. A graph of common solutions and their equivalent
conductances is shown for reference. The data was derived
from DA Macinnes, "The Principles of Electrochemistry,"
Reinhold Publishing Corp., New York., 1939.
In automotive and other applications where the power
source is known to contain significant transient voltages, the
internal regulator on the LM1830 allows protection to be
provided by the simple means of using a series resistor in
the power supply line as illustrated in Figure 4. If the output
load is required to be returned directly to the power supply
because of the high current required, it will be necessary to
provide protection for the output transistor if the voltages
are expected to exceed the data sheet limits.

In the case of inductive loads or incandescent lamp loads, it
is recommended that a filter capacitor be employed.
In a typical application where the device is employed for
senSing low water level in a tank, a simple steel probe may
be inserted in the top of the tank with the tank grounded.
Then when the water level drops below the tip of the probe,
the resistance will rise between the probe and the tank and
the alarm will be operated. This is illustrated in Figure 3. In
situations where a non-conductive container is used, the
probe may be designed in a number of ways. In some cases
a simple phono plug can be employed. Other probe deSigns
include conductive parallel strips on printed circuit boards.

Conductive Fluids

City water
Seawater
Copper sulphate solution
Weak acid
Weak base
Household ammonia
Water and glycol mixture
Wet soil
Coffee

Although the LM1830 is designed primarily for use in sensing conductive fluids, it can be used with any variable resistance device, such as light dependent resistor or thermistor
or resistive position transducer.
The following table lists some common fluids which may
and may not be detected by resistive probe techniques.

Non-Conductive Fluids

Pure water
Gasoline
Oil
Brake fluid
Alcohol
Ethylene glycol
Paraffin
Dry soil
Whiskey

5-128

Typical Applications Vee =

r3:

....CO

16V

Co)

o

Vee
Vee

1200

1200
O.DDlpf

~ LED

14

O.OOluf

~ LED

12
14

Vee

12

Vee

TIMING
CAP.

RREF
I-lOOk

Q,05#F

FILTER

13

GROUND

10

11

FIGURE 2. Application Using External
Reference Resistor

FIGURE 1. Test Circuit

Vee
vee
1200
DODI"F

14
TIMING
CAP.

DOO1~F

~ LEO

LOUDSPEAKER

"Vee

12
TIMING
CAP.

Vee

13

FILTER
•

10

12

GROUND
11

r

Rp

~

PHOTO

L.a.H.

THERMISTOR

TRANSISTOR

TL/H/S700-4

Output is activated when Rp is approximately greater than

FIGURE 3. Basic Low Level Warning Device
with LED Indication

% RREF

FIGURE 4. Direct Coupled Applications

5-129

Typical Applications Vee =

16V (Continued)
Low Level Warning with Audio Output
Vee

""'500Hz
O.001pF

1500

14

12

Vee

High Level Warning Device
Vee

OPTIONAL

p~:::~~~~~

470

2k

RESISTOR

O.OOI/lF

14

Vee

TL/H/S700-S

The Output is suitable for driving a sump pump
or opening a drain valve, etc.

5-130

r-------------------------------------------------------------------------,
NatiOnal

~ Semiconductor

co

LM1851 Ground Fault Interrupter
General Description

Features

The LM1851 is designed to provide ground fault protection
for AC power outlets in consumer and industrial environments. Ground fault currents greater than a presettable
threshold value will trigger an external SCR-driven circuit
breaker to interrupt the AC line and remove the fault condition. In addition to detection of conventional hot wire to
ground faults, the neutral fault condition is also detected.
Full advantage of the U.S. UL943 timing specification is taken to insure maximum immunity to false triggering due to
line noise. Special features include circuitry that rapidly resets the timing capacitor in the event that noise pulses introduce unwanted charging currents and a memory circuit that
allows firing of even a sluggish breaker on either half-cycle
of the line voltage when external full-wave rectification is
used.

•
•
•
•
•

Internal power supply shunt regulator
Externally programmable fault current threshold
Externally programmable fault current integration time
Direct interface to SCR
Operates under line reversal; both load vs line and hot
vs neutral
• Detects neutral line faults

Block and Connection Diagram

SCR
TRIGGER

s:
.....
CJ'1
.....

Corporation

VCC

r

TIMING
CAPACITOR

INVERTING
INPUT

SENSITIVITY
SET RESISTOR

NON·INVERTING
INPUT
TOP VIEW

Order Number LM1851M or LM1851N
See NS Package Number M08A or N08E

5-131

SENSE AMPLIFIER
OUTPUT

GND
TL/H/5177-1

,...
co
,...

II)

::E

...I

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Current

Soldering Information
Dual-In-Line Package (10 sec.)
Small Outline Package
Vapor Phase (60 sec.)
Infrared (15 sec.)

215'C
220'C
See AN-450 "Surface Mounting and Their Effects on Product Reliability" for other methods of soldering surface
mount devices.

19mA

Power Dissipation (Note 1)

1250 mW

Operating Temperature Range

-40'Cto +70'C

Storage Temperature Range

-55'Cto +150'C

DC Electrical Characteristics
Parameter

260'C

TA=25'C, Iss=5 mA
Conditions

Power Supply Shunt
Regulator Voltage

Pin 8, Average Value

Min

Typ

Max

Units

22

26

30

V

Latch Trigger Voltage

Pin7

15

17.5

20

V

Sensitivity Set Voltage

Pin 8to Pin 6

.6

7

8.2

V

0.5

Output Drive Current

Pin 1, With Fault

1

2.4

rnA

Output Saturation Voltage

Pin 1, Without Fault

100

240

mV

Output Saturation Resistance

Pin 1, Without Fault

100

n

Output External Current
Sinking Capability

Pin 1, Without Fault,
Vpin 1 Held to 0.3V (Note 4)

2.0

5

rnA

Noise Integration
Sink Current Ratio

Pin 7, Ratio of Discharge
Currents Between No Fault
and Fault Conditions

2.0

2.8

3.6

/LAI/L A

Min

Typ

Max

Units

3

5

7

rnA

AC Electrical Characteristics TA = 25'C, Iss = 5 mA
Conditions

Parameter
Normal Fault Current
Sensitivity

Figure 1 (Note 3)

Normal Fault Trip Time

500n Fault, Figure 2 (Note 2)

18

ms

Normal Fault with
Grounded Neutral Fault
Trip Time

500n Normal Fault,
2n Neutral, Figure 2 (Note 2)

18

ms

Note 1: For operation in ambient temperatures above 25°C, the device must be derated based on a 12SOC maximum junction temperature and a thermal resistance

of BO'C/W junction to ambient for the DIP and
Note 2: Average of 10 trials.

16Z"C/W

for the SO Package.

Note 3: Required UL sensitivity tolerance is such that external trimming of LM1851 sensitivity will be necessary.

Note 4: This externally applied current is in addition to the internal "output drive current" source.

7 TIMING
CAP

T.
+

-

ISS

-'-C,
- r- 0.002 ~lk

1300mv

-IN 2

1 SCR
+IN
TRIGGER
LMl151
OPAMP
RSET
OUTPUT

..l.
B

I

GNO

Vcc

..

lOOk

0.j7"F

1

..!..

~

BOOHz "\.,

4

1.5M

-"':-31V

T
TL/H/5177-2

FIGURE 1. Normal Fault Sensitivity Test Circuit

5-132

r-

s:
....
co
....

Internal Schematic Diagram

U1

TL/H/5177-3

5-133

?-

,-----------------------------------------------------------------------------------------------,

II)

co
?:E

Typical Performance Characteristics

...J

Average Trip Time vs
Fault Current

Normal Fault Current
Threshold vs RSET

IOoo_~
;;.!l

~

100

100

'"
...'"o

1=,

~ ASH"

7V
Iflrms)* x (0.90

"SENSE TRANSFORMER 10 00,1

::;

~
~

~

10

i...

10

:0

~

:0
0.01

1.0

0.1

10

lOOk

TRIP TIME (SECONDS)

1M

10M

RSET(H)

* See Block Diagram

Output Drive Current vs
Output Voltage

1400

.--.----.---.---r---r----,,--,

:: 1200

I-+--+--I-+--!--Ii-----I

~

t-'"'=:4--I-+--!--II--l

_

'3.

z

1000

;

BOD

.....

600

Pin 1 Saturation Voltage vs
External Load Current, IL
10

~
w

u

~>

II
;::

~

0.1

~
z

0:

0.01

10

15

20

25

30

35

0.1

OUTPUT VOLTAGE@VpINl (V)

10

100

IL -EXTERNAL LOAD CURRENT (rnA)

TLlH/5177-4

Circuit Description
(Refer to Block and Connection Diagram)
The LM1851 operates from 26V as set by an internal shunt
regulator, 03. In the absence of a fault (If=O) the feedback
path status signal (Vs) is correspondingly zero. Under these
conditions the capacitor discharge current, 11, sits quiescently at three times its threshold value, ITH, so that noise
induced charge on the timing capacitor will be rapidly removed. When a fault current, If, is induced in the secondary
of the external sense transformer, the operational amplifier,
A 1, uses feedback to force a virtual ground at the input as it

extracts If. The presence of If during either half-cycle will
cause Vs to go high, which in turn changes 11 from 31TH to
ITH. Although ITH discharges the timing capacitor during
both half-cycles of the line, If only charges the capacitor
during the half-cycle in which If exits pin 2. Thus during one
half-cycle If-ITH charges the timing capacitor, while during
the other half-cycle ITH discharges it. When the capacitor
voltage reaches 17.5V, the latch engages and turns off 03
permitting 12 to drive the gate of an SCR.

5-134

ris:

Application Circuits
A typical ground fault interrupter circuit is shown in Figure 2.
It is designed to operate on 120 VAC line voltage with 5 rnA
normal fault sensitivity.
A full-wave rectifier bridge and a 15k/2W resistor are used
to supply the DC power required by the IC. A 1 I-'F capacitor
at pin B used to filter the ripple of the supply voltage and is
also connected across the SCR to allow firing of the SCR on
either half-cycle. When a fault causes the SCR to trigger,
the circuit breaker is energized and line voltage is removed
from the load. At this time no fault current flows and the IC
discharge current increases from ITH to 31TH (see Circuit
Description and Block Diagram). This quickly resets both
the timing capacitor and the output latch. At this time the
circuit breaker can be reset and the line voltage again supplied to the load, assuming the fault has been removed. A
1000:1 sense transformer is used to detect the normal fault.
The fault current, which is basically the difference current
between the hot and neutral lines, is stepped down by 1000
and fed into the input pins of the operational amplifier
through a 10 I-'F capacitor. The 0.0033 I-'F capacitor between pin 2 and pin 3 and the 200 pF between pins 3 and 4
are added to obtain better noise immunity. The normal fault
sensitivity is determined by the timing capacitor discharging
current, ITH. ITH can be calculated by:
7V
ITH=--+2
(1)
RSET
At the decision pOint, the average fault current just equals
the threshold current, ITH.
ITH= If(rmsl xo 91

2

.

start-up (S1 closure) with both a heavy normal fault and a
2!l grounded neutral fault present. This situation is shown diagramatically below.
1

7V

GFI

LINE "NEUTRAL

NEUTRAL

r--

I

RG

RN

R8

~ 0.4

(0.811

1.6

~ SOD

:;:~-L

' (0.211
-

TLlH/5177-5

UL943 specifies :>:25 ms average trip time under these conditions. Calculation of Ct based upon charging currents due
to normal fault only is as follows:
:>: 25 ms Specification
-3 ms GFI turn-on time (15k and 1 I-'F)
- 8 ms Potential loss of one half-cycle due to fault current
sense of half-cycles only
- 4 ms Time required to open a sluggish circuit breaker
:>:10 ms Maximum integration time that could be allowed
8 ms Value of integration time that accommodates component tolerances and other variables
Ix T
Ct=-y
(5)

(2)

where I'(rms) is the rms input fault current to the operational
amp and the factor of 2 is due to the fact that I, charges the
timing capacitor only during one half-cycle, while ITH discharges the capacitor continuously. The factor 0.91 converts the rms value to an average value. Combining equations (1) and (2) we have
%a=

HOT

~

(

where T = integration time
V = threshold voltage
I = average fault current into Ct
( 120 V:~(rms) )

1=

~

If(rms)XO.91
For example, to obtain 5 mA(rms) sensitivity for the circuit in
Figure 2 we have:
7V
RSET 5mAXO.91 1.5M!l
(4)

x

(RG
\.

'------v---J
heavy fault
current generated
(swamps ITH)

1000
The correct value for Rsa can also be determined from the
characteristic curve that plots equation (3). Note that this is
an approximate calculation; the exact value of RSET depends on the specific sense transformer used and LM1851
tolerances. Inasmuch as UL943 specifies a sensitivity "window" of 4 mA-6 rnA, provision should be made to adjust
Rsa on a per-product basis.
Independent of setting sensitivity, the desired integration
time can be obtained through proper selection of the timing
capaCitor, Ct. Due to the large number of variables involved,
proper selection of Ct is best done empirically. The following
design example, then should only be used as a guideline.
Assume the goal is to meet UL943 timing requirements.
Also assume that worst case timing occurs during GF1

x
\.

(

1turn )
1000 turns
T

current
division of
input sense
transformer
therefore:

Ctcharging
on halfcycles only

[(~) x (~)

C
t

Ct =

5-135

G)
'-v-I

x
}

x

(1iioo) x
17E

0.011-'F

~ RJ

)

T

portion of
fault current
shunted
aroundGFI

x

(0.91)

(6)

'---.r--J
rmsto
average
conversion

m

X(O.91)

1

XO.0008

(7)

......
()C)
en
......

..Il)

co
..:!
....I

Application Circuits (Continued)
in practice, the actual value of C1 will have to be modified to
include the effects of the neutral loop upon the net charging
current. The effect of neutral loop induced currents is difficult to quantize, but typically they sum with normal fault currents, thus allowing a larger value of C1.

For those GFI standards not requiring grounded neutral detection, a still larger value capacitor can be used and better
noise immunity obtained. The larger capacitor can be accommodated because RN and RG are not present, allowing
the full fault current, I, to enter the GFI.

For UL943 requirements, 0.015 JloF has been found to be
the best compromise between timing and noise.

In Figure 2, grounded neutral detection is accomplished by
feeding the neutral coil with 120 Hz energy continuously and
allowing some of the energy to couple into the sense transformer during conditions of neutral fault.

Typical Application
seNSE
COIL

GNU/NEUTRAL
COIL

LOAO {HOT
NEUTRAL

MQV

} LINE

0--+---+----<,-,0:>------/ t--;,;"..-+-+------------i

t---=-H-O

CIRCUIT
BREAKER

10~F

+

15k!2W

7 TIMING
CAP

-IN

r---1r----+-+--1"1~~~GGER

+IN

0.0033

1-'-----<.---'

LM1851
5 OPAMP
RSET
OUTPUT

C,
0.015 8

'------+--+-.....""Ivcc

TANT

200pF

GNO!-'-t--.
RSH*

001

+ 1.0pF
TANT

TLIH/5177-6

• Adjust RSET for desired sensitivity

FIGURE 2. 120 Hz Neutral Transformer Approach

5-136

,-----------------------------------------------------------------------------, r

...:s:

Definition of Terms
Normal Fault plus Grounded Neutral Fault: The combination of the normal fault and the grounded neutral fault, as
shown by the dashed lines.

[
{

~

NEUTRAL _

G F I . RLO) R,
-:::::::

c.n

HOT-

~~

HOT_
LINE

...
Q)

Normal Fault: An unintentional electrical path, Rs, between
the load terminal of the hot line and the ground, as shown
by the dashed lines.

LINE

NEUTRAL _

~

GFI

ADt

I

....._ _-1 NEUTRAL

~-~--±
":'"

/",7

TLlH/5177-7
TLlH/5177-9

Grounded Neutral Fault: An unintentional electrical path
between the load terminal of the neutral line and the
ground, as shown by the dashed lines.

LINE

I

HOT

HOT-

NEUTRAL_~

GFI

~RLOAD

~

I-'N;;.EU;.;.T;;;.RA;;.L_. . .

!

L......_-R-I
G

~RN

. . . --AM--i.

/",7

":"

TL/H/5177-8

II
5-137

~ Semiconductor
NatiOnal

BI-LINETM

Corporation

LM 1893/LM2893 Carrier-Current Transceivert
General Description
Carrier-current systems use the power mains to transfer information between remote locations. This bipolar carriercurrent chip performs as a power line interface for half-duplex (bi-directional) communication of serial bit streams of
virtually any coding. In transmission, a sinusoidal carrier is
FSK modulated and impressed on most any power line via a
rugged on-chip driver. In reception, a PLL-based demodulator and impulse noise filter combine to give maximum range.
A complete system may consist of the LM1893, a COPSTM
controller, and discrete components.

Features
•
•
•
•
•

Noise resistant FSK modulation
User-selected impulse noise filtering
Up to 4.8 kBaud data transmission rate
Strings of D's or 1's in data allowed
Sinusoidal line drive for low RFI

•
•
•
•
•

Output power easily boosted 10-fold
50 to 300 kHz carrier frequency choice
TTL and MOS compatible digital levels
Regulated voltage to power logic
Drives all conventional power lines

Applications
•
•
•
•
•
•
•
•

Energy management systems
Home convenience control
Inter-office communication
Appliance control
Fire alarm systems
Security systems
Telemetry
Computer terminal interface

Typical Application
y+

4.7

250V

O.22~

!Cr=

CONTROLLER
TX/RX
SELECT

h1~

560p

10k'V
18

17
Y+

12k
11

5.6Y

10k

12

3.3k
47.

TlIH/6750-1

FIGURE 1. Block diagram of carrier-current chip with a complement of discrete components making a complete
Fe = 125 kHz, fOATA = 360 Baud transceiver. Use caution with this circuit-dangerous line voltage Is present.
tCarrler-Current Transceivers are also called Power Una Carrier (PlC) transceivers.

5-138

Absolute Maximum Ratings
Maximum continuous dissipation, T A = 25'C,
plastic DIP N (Note 2): transmit mode
1.66W
receive mode
1.33W
-40 to 85'C
Operating ambient temp. range
-65 to 150'C
Storage temperature range
Lead temp., soldering, 7 seconds
260'C

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply voltage
Voltage on pin 12
Voltage on pin 10 (Note 1)
Voltage on pins 5 and 17
5.6 V DC zener current
Junction temperature: transmit mode
receive mode
Electro-Static Discharge (120 pF, 15000)

30V
55V
41 V
40V
100mA
150'C
125'C
1KV

Note: Absolute maximum ratings indicate limits beyond

which damage to the device may occur. Electrical specifications are not ensured when operating the device above
guaranteed limits but below absolute maximum limits, but
there will be no device degradation.

General Electrical Characteristics
(Note 3). The test conditions are: V +
#

1

= 18V and

Fo = 125 kHz, unless otherwise noted.

Parameter

Conditions

5.6 V Zener voltage, Vz

Pin 11,lz=2 rnA

Typical

Test
Limit
(Note 4)

5.6

Design
Limit
(NoteS)

Limit
Units

5.2
5.9

V min.
V max.

2

5.6 V Zener resistance, Rz

Pinll,Rz=(Vz@10mA-Vz@lmA)/(10mA-lmA)

5

3

Carrier lID peak survivable
transient voltage, VOT

Pin 10, discharge 1 fLF cap. charged to VaT
thru 

w

~

ii! 30

- ..

60

i

5

I

20
10 t PUlSE-f0
10' 10·' 10'
10 0 10'
PULSE TIME ISECONOS)

N~N.'TJITIVE

TX MODE

30

o

10
z

=
~

~

40 H++-t++-I--++-H+,N:-l

~

20 H++-t++-I--++-H+-H-l

t=

~

lbooliiAii'

...
~
'"~
Ci

a

:J:

1

~
~

-60 -30 0 30 60 90 110 150
TJ-JUNCTION TEMPERATURE I" C)

ALC Voltage vs
Junction Temperature

60 90 110 150

~

80 H+H"""oH--++-H+-H-l

H+H+-HM'''kH+H-J

30

Transmitter Sinusoid THO
vs Junction Temperature

100 1ooI;:+-+-t++-I--++-H+-H-l

60

0

TJ -JUNCTION TEMPERATURE I CI

,....,.-,--"...."rr.."r-rT"l-rT"l

a:

AX MDDE

-60 -30

90 120 150

....

~
-;:::o.~

IODC = IplNtO

50

Transmitter AC Output Current
vs Junction Temperature
110

---~
Voe

60

TJ-JUNCTION TEMPERATURE 1°C)

i§.
..... .....

50

~

10 ~ Ip'H15

o

50

,...

0
10 20 30 40
V' -SUPPLY VOLTAGE IV)

ffi 10

1

Transient Voltage Survival
vs Pulse Time

..... .....

....

~

PIN 10 VOLTAGE (V)

100
90
80
70
60
50
40

..-Sw

;g

V;'Hl0 > 3OV:
Vp'H15 ~ 30V

IplN15

Output Stage DC Current,
IODC,VS
Junction Temperature

...~

a

----

10

-1
-10

is
a: 40

TX MODE

a:
a:

RXMDDE~

~

RXiMbdE

~

w

1

10

10

....
z

IplNtO

4

Output Stage DC Current,
IODC, vs Output Voltage

60
50

TX MODE

a:

-60 -30 0 30 60 90 110 150
TJ-JUNCTION TEMPERATURE I'CI

50

10

ffia:

o
10
20
30
40
V' -SUPPLY VIlLTAGE (V)

11

..-S-

10

Trttl

0.1
-60-30 0 30 60 90 110 150
TJ-JUNCTION TEMPERATURE (",C)

ICO Frequency vs
Junction Temperature

Transmitter FSK Deviation
vs Junction Temperature
49

1?
100 PPM/"C
~ 1.02 PI.~f-=!-'"F-'R-4=-=!-'"F-f-=t-4=t-I
~ 1 01 I-+"H+t-l++-f-t+H-l

;E

48

~

47
46

: 1.00 H+.:H-1"'io.I--++-H+-H-J

~
o

Ei

45H+H+"-Id-+-H+M--I

ff

43H+H++-I--++-H+H--I

!!:

~ 0.99 I-+-ll-IW::!-::!::-!-:£"k-f-t+HfI

~

8
-60 -30 0 30 60 90 120 150
TJ-JUNGTION TEMPERATURE lOG)

0 98

l~~~~~:~_~HH~

I-+-FR'"F'FI4=FR'1"'I"'t-l

0.97
-60 - 30 0

30

60

90 110 150

TJ-JUNCTION TEMPERATURE I"C)

ii:i
o

44H+H++-I--+~l;;::Iirlf-H--I

t±l±titttl±titjj

41
·60-30 0 30 6090110150
TJ-JUNCTION TEMPERATURE I C)

TLiH/S7S0-38

5-141

~

en

....
:l
CIO

r--------------------------------------------------------------------------.
Typical Performance Characteristics

50

32

99 7% OF SO WAVEEOGES
WITHIN 40%-60% DUTY CYCLE

;;

28

14

~

24

12 '"

I:;:

20

10 ~

~

'"

~

'"
'"~
'"

16
12

8

~

50 kHz

6

'"
::>

NO TANK

[t±;~~T A~~~;gp 0F~~rn-

o L.J--'-'~........"""""-'-"""=.L.J....J
-60 -30 0

30

60

2

300 kHz

'"~
'"

o

90 120 150

FO • 300 kHz

-

~U+ O'F ~OJK

CAPTURE
PLL

III

!

,

~ -10

"
CAPTURE

-20
-30

rt

I~ L10C1K

III

OUT OF LOCK
'OIK,
HIGH 10ATA LOOP FILTER ", , ,

§ -40

,

[
;

2:
t::

§
~

-CHARGE

G

50

I5

40

~

!

DISCHARGE

>

~z

30
20

Ii

I

IN LOCK

~

>=

-30

10

30

~

OUT
OF
LOICK
N:i:.OOP FILTER

-30
-10
10
30
LOCK RANGE I % OF Fo)

Phase Detector Output
Voltage vs Junction
Temperature

Offset Hold Cap_ Charge
Currents vs Junction
Temperature

140i

VPD

120~

Vw

100

l00~>

80

80 fa

60

60

g

I:;:

40

~

20

20

I

o

o
-60 -30

30 60 90 120 150
TJ-JUNCTION TEMPERATURE I 'C)

Data Out. Low Voltage vs
Pull Down Current

£

50

80

160 ii:

OEV._4.4%

120

Offset Hold Cap_ Bias Current vs
Junction Temperature

~

LOCK RANGE (0/0 OF Fo)

~

-60 -30 0 30 60 90 120 150
TJ-JUNCTION TEMPERATURE I"C)

PLLIN
LOCK

LyK
1
-50

50

HIGH
'DATA
FI~TER

°O~T ~

~

fDATA

-10

10

'"

HIGH
LOOP
FILTER

1---"" ...

,

>-

IbuTIOF
LOCK

40

o

0

-30
300 kHz
-40
-150t,z
-50
-60 -30 0 30 60 90 120 150
T,-JUNCTION TEMPERATURE ("C)

Receiver Sensitivity vs
PLL Lock Range and Loop Filter

Ii
I

10

-10
-20

i

1
-50

-

Js~

IN LOCK

100

Fo
50 kHz
125 kHz
300 kHz-

ill'"

, , , Fo 125kHz

300 kHz

I--(&~~~FSI~':::L)

10

~ 140

60

9

MAX. 10"A COMPONENT VALUES
Fo = 125.300 kHz tOATA=2.4 kHz
100TA =12kHz
Fo = 50 kHz

80

i .,.
'"'"~

~

otiT dF
LOCK

Impulse Noise Filter
Current vs Junction
Temperature
70

0

u

E

-50
-60 -30 0 30 60 90 120 150
TJ-JUNCTION TEMPERATURE rC)

~

10

III
:i
rr

100

(LARGE SIGNAL)

rLO~KI-

i!:.

Receiver Sensitivity vs
PLL Lock Range and Fo

PLL Capture & Lock Range vs
Junction Temperature
50

IS

30
20

-60 -30 0 30 60 90 120 150
TJ-JUNCTION TEMPERATURE I' C)

TJ -JUNCTION TEMPERATURE I C)

;E 40
~ 30
~ 20
~ 10
0

125 kHz

~

HiGH 'OATA LOOP ~IIERJJ.
OUT OF LOCK 50 kHz

40
~

~

::>

~
!i

PLL Lock Range vs
Junction Temperature and Fo

Receiver Sensitivity vs
Junction Temperature

Maximum Data Rate vs
Junction Temperature

::>

(Continued)

~

Ig
i3
~

70
60

CHARGE

50
40
OISCHARGE'!.i'o;

30

f.,

20
IMCM

10

FULL SWITCHING

-60 -30
30 60 90 120 150
TJ-JUNCTION TEMPERATURE ("C)

Pin 7 Bias Voltage vs
Junction Temperature

1.0

-

E
~
~

~

~
'"

I

~

0.5

l.oo'

~
I

"

0.1
-110 -30 0

~
30

110

"'"

I.;

\II'

90 120 150

TJ-JUNCTION TIWPERATlJRE ('1:)

10
COLLECTOR CURRENT (rnA)

-60 -30 0

30

60

90 120 150

T, - JUNCTION TIWPERATlJRE ('1:)
TL/H/67S0-39

5-142

r-

s:
....
ClO

Dual-In-Line Package

Application Information *

<0

THE DATA PATH
The BI-LiNETM chip serves as a power line interface in the
carrier-current transceiver (CCT) system of Figure 3. Figure
4 shows the interface circuit now discussed. The controller
may select either the transmit (TX) or receive (RX) mode.
Serial data from the controller is used to generate a FSKmodulated 50 to 300 kHz carrier on the line in the TX mode.
In the RX mode line signal passes through the coupling
transformer into the PLL-based receiver. The recreated serial bit stream drives the controller.
With the IC in the TX mode (pin 5 a logic high), baseband
data to 5 kHz drive the modulator's Data In pin to generate
a switched 0.9781/1.0221 control current to drive the low TC,
triangle-wave, current-controlled oscillator to ± 2.2% deviation. The tri-wave passes through a differential attenuator
and sine shaper which deliver a current sinusoid through an
automatic level control (ALC) circuit to the gain of 200 current output amplifier. Drive current from the Carrier 1/0 develops a voltage swing on Tl'S (Figure 4) resonant tank
proportional to line impedance, then passes through the
step-down transformer and coupling capacitor Cc onto the
line. Progressively smaller line impedances cause reduced
signal swing, but never clipping-thus avoiding potential radio
frequency interference. When large line impedances threaten to allow excessive output swing on pin 10, the ALC
shunts current away from the output amplifier, holding the
voltage swing constant and within the amp's compliance
limit. The amplifier is stable with a load of any magnitude or
phase angle.
In the RX mode (pin 5 a logic low), the TX sections on the
chip are disabled. Carrier signal, broad-band noise, transient
spikes, and power line component impinge of the receiver'S
input highpass filter, made up of Cc and T1, and the tank
bandpass filter. In-band carrier signal, band-limited noise,
heavily attenuated line frequency component, and attenuated transient energy pass through to produce voltage swing
on the tank, swinging about the positive supply to drive the
Carrier 1/0 receiver input. The balanced Norton-input limiter
amplifier removes DC offsets, attenuates line frequency,
performs as a bandpass filter, and limits the Signal to drive
the PLL phase detector differentially. The differential demodulated output signal from the phase detector, containing AC and DC data Signal, noise, system DC offsets, and a
large twice-the-carrier-frequency component, passes
through a 3-stage RC lowpass filter to drive the offset cancel circuit differentially. The offset cancelling circuit worl(s
by insuring that the (fixed) ±50 mV Signal delivered to the
data squaring ("slicing") comparator is centered around the
o mV comparator switch point. Whenever the comparator
signal plus DC offset and noise moves outside the carefully
matched ± 50 mV voltage "window" of the offset cancel
circuit, it adjusts its DC correction voltage in series with the
differential signal to force the signal back into the window.
While the signal is within the ± 50 mV window, the DC offset
is stored on capaCitor CM. By grace of the highly non-linear
offset hold capaCitor charging during offset cancelling, the
DC cancellation is done much more quickly than with an AC
coupling capacitor normally used in place of the offset cancel circuit. Since impulse noise spikes normally ring the signal symmetrically around 0 V, the fully bilateral offset cancel
topology affords excellent noise rejection. The switched current output of the comparator drives the impulse noise filter
integrator capacitor that rejects all data pulses of less than
the integrator charge time. Noise appears as duly-cycle jitter
at the open collector serial data output.

ICD CAP 1

lB

ICD FREQUENCY

ICD CAP 2

17

DATA IN

PLL FILTER 1

16

LIMITER FILTER

PLL FILTER 2

15

V+

14

GRDUND

DFFSET HDLD CAP

13

NOISE INTEGRATOR

ALC STABILITY

12

DATA DUT

BDDST EMITTER

11

5.6V ZENER

BDDST BASE

10

CARRIER liD

LM1B93

TX/RX SELECT

TL/H/6750-2

Top View

Dual-In-Line Package
ICO CAP 1

ICO FREQU ENCY

ICO CAP 2

2

19

PLL FILTER 1

3

18

DATA IN
LIMITER FILTER

NO CONNECTION

4

17

v+

16

GROUND

15

CARRIER IN

7

14

NOISE INTEGRATOR

ALC STABILITY

8

13

DATA OUT

BOOST EMITTER

9

12

5.6V ZENER

10

11

CARRIER OUT

PLL FILTER 2

5

TX/RX SELECT

6

OFFSET HOLD CAP

BOOST BASE

LM2893

Top View
FIGURE 2. Connection Diagrams

TL/H/6750-41

'0 .:0-----'
POWER LINE

I

B

TLlH/6750-3

FIGURE 3. The block diagram of a carrier-current
system using the Bi·Line chip to interface digital
controllers via the power line
·Unless otherwise noted, al1 pin references refer to LM1893, but hold true
for equivalent LM2893 pin.

5-143

Co)

LM1893
:J>

't:I

"2-

n"

I»

0"

y.

-...
~

Cc

!.Cr~ ~

!
c.

~

CONTROLLER

TX

TX/iii(

DATA

SELECT

o

3

I»

0"

y+
18

117

~

g>

Rr

:::J

g

10

c:
CD

r...T

S.

~

~
~

RG

I
I

12
ftc

I
I
L. __ J
OPTIONAL
BOOST

R,

~CM
TL/H/6750-4

FIGURE 4. Block diagram of a CCT system with the boost and 5V supply options shown in dashed boxes

r-

Application Information
Recommended
Value

#

Purpose

s:
......

(Continued)

CCI

Effect of making the component value:

CQ

Notes

Larger

Smaller

Ca 560 pF
Ra 6.2kn

Together, Ca and Ra Increases Fa
set ICO Fa.
Increases Fa
<5.6 k not recommended.

± 5% NPO ceramic. Use low TC
Decreases Fa
2 k pot and 5.6 k fixed R.
Decreases Fa
>7.6 k not recommended. Poor Fa TC with <5.6 k Ra.

CF 0.047 J.LF

PLL loop filter pole

RF 3.3kn

PLL loop filter zero

Less noise immune, higher
fDATA, more PLL stability.
PLL less stable, allows
less CF. Less ringing.

More noise immune, lower
fDATA, less PLL stability.
PLL more stable, allows
more CF. More ringing.

Depending on RF value and
Fa, PLL unstable with large
CF. See Apps. Info. CF
and RF values not critical.

Cc 0.22J.LF

Couples Fa to line,
Cc and T, low-pass
attenuates 60 Hz.

Low TX line amplitude.
Less 60 Hz T 1 current.
Less stored charge.

Drives lower line Z.
More 60 Hz T, current.
More stored charge.

:;, 250 V non-polar. Use 2Cc
on hot and neutral for max.
line isolation, safety.

CQ 0.033 J.LF
T, Use
recommended
XFMR

Tank matches line Z,
bandpass filters,
isolates from line,
and attenuates
transients.

Tank Fa up or increase
Tank Fa down or decrease
L of T, for constant Fa.
L of T, for constant Fa.
Larger L: lower Fa or
Smaller L: higher Fa or
increase Cc; decreased Fa decrease Cc; increased Fa
line pull.
line pull.

100 V nonpolar, low TC, ± 10%
High large-signal Q needed.
Optimize for low Fa line
pull with control of Fa TC
andQ.

CA 0.1 J.LF
RA 10kn

ALCpoie
ALCzero

Noise spikes turn ALC off.
Less stable ALC.

Slower ALC response.
More stable ALC.

RA optional. ALC stable
forCA:;,100pF.

CL 0.047 J.LF

Limiter 50 kHz pole,
60 Hz rejection.

Higher pole F, more 60 Hz
reject. Fa attenuation?

Lower pole F, less 60 Hz
reject, more noise BW.

Any reasonably low TC cap.
300 pF guarantees stability.

CM 0.47 J.LF

Holds RX path Vas

Less noise immune, shorter More noise immune, longer Low leakage ±20% cap.
Vas hold, faster Vas aqui- Vas hold, slower Vas aqui- Scale with fDATA.
sition, longer preamble.
sition, shorter preamble.

CI 0.047,..F

Rejects short pulses Less impulse reject, less
like impulse noise.
delay, more pulse jitter.

Rc 10kn

Open-col. pull-up

Rz 12kn

5.6 V Zener bias

ZT :;,44 V BV
<60 V peak

Transient clamp

Dr

RT 4.7 n
:;'44VBV

More impulse reject, more
delay, less pulse jitter.

CI charge time '12 bit nom.
Must be < 1 bit worst-case.

Less available sink I.

Less available source I.

Rc:;'1.5 kn on 5.6 V

Larger shunt current,
more chip dissipation.

Smaller shunt current,
less V+ current draw.

1  200 MHz. Rs > 24 Ohm.
Less la, lower min. hie.
la=70[(10+RG)/RGl mApp.

Cs :;'47 J.LF

Supply bypass

Transients destroy chip.

Less supply spike.

V + never over abs. max.

ZA S.W

Stop ALC charge
in RXmode

ExcessALC
current flow

ALC RX charging
not inhibited over TJ

ZA optional - 5.W
± 20% low leakage type

Carbon compo recommended.
IRF 11DQ05 or 1N5819

FIGURE 5. A quick explanation of the external component function using the circuit of Figure 4. Values given are for V + =
18 V, Fo = 125 kHz, fDATA = 360 Baud (180 Hz), using a 115 V 60 Hz power line

Component Selection
ance considerations only, are: 1) the higher the Fa the better, 2) the lower the maximum data rate the better, and 3)
the more time and frequency filtering the better.

Assuming the circuit of Figure 4 is used with something other than the nominal 125 kHz carrier frequency, 180 Hz data
rate, 18V supply voltage, etcetera, the component values
listed in Figure 5 will need changing. This section will help
direct the CCT designer in finding the required component
values with emphasis placed on look-up tables and charts. It
is assumed that the designer has selected values for carrier
center frequency, Fa; data rate, fDATA; supply voltage, V +;
power line voltage, VL; and power line frequency, FL. If one
or more of those parameters is not defined, one may read
the data sheet and make an educated guess.

Use Figure 5 as a quick reference to the external component function.
THE TRANSMITTER
Co
Central to chip operation is the low TC of Fa emitter-coupled oscillator. With proper Ca, the Fa of the 2VSE amplitude triangle-wave oscillator output may vary from near DC
to above 300 kHz. While Ca may have any value, Ca should

Maxims to keep in mind, based on CCT electrical perform5-145

Co:!

~ r-------------------------------------------------------------------------------~

en
co
.,...
::::iE

..J

Component Selection

(Continued)

be made above 10 pF so that parasitic capacitance is not
dominant. Excessive or unbalanced common-mode-toground capacitance should be avoided. A low temperature
coefficient (TC) of capacitance «100 PPMI"C), such as a
monolithic NPO ceramic multilayer type, preserves low TC
of Fo. Figure 6 finds a Co value given Fo.

Tl
At this point, the CCT system designer may choose to use
one of the recommended transformers or to design custom
T1. Consult "The Coupling Transformer" section to help
with the design of Tl if a new or boost-capable transformer
is needed. The recommended 125 kHz transformer functions with an 10 of up to 600 mApp.

Ro
Resistor Ro is used by the IC to generate a VBE/R related
current that is multiplied by 2 to produce the 200 IJ-A ICO
control current that sets Fo. The control current TC "bucks"
the VBE related tri-wave amplitude across Co to ellect a low
TC of Fo. Vary Ro to trim Fo, within limits. Raising Fo more
than 20% above its untrimmed value by means of decreasing Ro more than 20% is not recommended. Low Ro, and
so high control current, risks ICO saturation and poor TC
under worst-case conditions. Raising Ro reduces the demodulated signal amplitude from the phase detector; raising
RO by more than a factor of 2 (1 octave) is not recommended.
Since lower TC pots are relatively costly, it is recommended
that Ro be made up of a 5.6 k fixed « 100 PPM/"C) resistor
with a 2 kO «250 PPMI"C) series pot.

It is recommended that CCT systems use the recommended
transformers, described in Figure 7, for T1. The 3 transformers are optimized for use in the ranges of 50-100 kHz, 100200 kHz, and 200-400 kHz with unloaded Q's (Qu) of about
35, and loaded Q's (Qu of about 12. Three secondary taps
are supplied with nominal 7.07, 10, and 14.1 turns ratios (N)
to drive industrial and residential power line impedances of
3.5, 7, and 140 respectively. All are inexpensive, all have
the same pin·outs for easy exchange in a PC board, and all
are small- on the order of 10 mm diameter at the base.
CQ
Tank resonant frequency Fo must be correct to allow passage of transmitter Signal to the line. Use Figure 8 to find
Co's value. Trimming Fo to equal Fo is done with T I'S trimming slug. The inductance of T 1 has a TC of + 150 PPMI"C
which may be cancelled by using a -150 PPMI"C cap such
as polystyrene. Since circulating current in the tank is %
ARMS, Co should have a low series resistance (a 1 0 series
resistance is too much). Polypropelene caps are excellent,
"orange drop" mylars are adequate, while many other mylars are inadequate. A 100V rating is needed for transient
protection.

CAand RA
Components CA and RA control the dynamic characteristics
of the transmitter output envelope. Their values are not critical. Use the values given in Figure 5. CA and RA are functions of loaded Tl tank Q, Ro, fDATA, and line impulse
noise. Any changes made in CA and RA should be made
based on empirical measurements of a CCT on the line.
Roughly, CA acts as an ALC pole and RA an ALC zero.

!
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100

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10

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1

10

100

Ll = 18.9 pH tift

500

z

0.1

1

(2nFo)2L,

108 pH

0.5
100

10

1000

1000

Fo-CARRIER FREOUENCY (kHz)

Fa -CARRIER CENTER FREQUENCY (kHz)

TL/H/6750-' 0

TL/H/6750-5

FIGURE 8. Find Co's value given Fo

FIGURE 6. Find Co's value knowing Fo

Bottom View

TLlH/6750-8

TL/H/6750-7

TlIH/6750-6

TL/H/6750-9

300 kHz

125 kHz

50 kHz

C2 10UL·001

C2 10UL·Q02

C210UL·003

Toko 707VX·A042YUK

Toko 707VX·A043YUK

Toko 161XN·A207YUK

FIGURE 7. The recommended T 1 transformers, available through:
1) C2 Electronics, 4010 Moorpark, Suite 105, San Jose, CA., 95117 (408) 248-9899
2) Toko America, 5520 W. Touhy Ave., Skokie, IL, 60077, (312) 677-3640.
5-146

Component Selection

(Continued)
neous power of greater than 1 kW has been measured using the recommended transformers). For self protection, the
Carrier 110 has an internal 44V voltage clamp with a 20n
series resistance. A parallel low impedance 44V external
transient suppression diode will then conduct the lion's
share of any current when transients force the Carrier 110 to
a high voltage.

Cc
Capacitor Ce's primary function is to block the power line
voltage from Tl'S line-side winding. Also, Ce and Tl'S lineside winding comprise a LC highpass filter. The self-inductance of T 1 is far too low to support a direct line connection.
Ce must have a low enough impedance at Fa to allow T1 to
drive transmitted energy onto the line. To drive a 14n power
line, the impedance of Ce should be below 14n.

1000
~

""~

Use Figure 9 to find the reactive impedance of Ce to check
that it is less than the line impedance. Then check Figure 10
to see that the power line current is small enough to keep
T 1 well out of saturation; the recommended transformers
can withstand a 10 Amp-turn magnetizing force (1 Amp
through the worst-case 10 turn line-side winding).

I~
:>

Ii:

100 ~

~

10

::J

1
C.-LINE COUPLING CAPACITANCE

1000

~

Ci

10 =0.0247[(10+RG)/l0RG]
TJ =25°C

.i
~

~

~

....
'"

:>

10

100

F

~~

i£

E;
I

co

...

TLlH/6750-12

100

~

~~

12

10

(~F)

FIGURE 10. The AC line-induced current passed by Cc

100

u

10

0.1

Rs
This base-bleed resistor turns as off quickly - important
since the amplifier output swing is about 200V I flos. An Rs
below about 24n will conduct excessive current and overload the chip amplifier and is not recommended.

e:

~
50H,-

~

Caution is required when choosing Ce to avoid series resonance of the series combination of Ce, the transformer inductance, and the reflected tank impedance. The low resistance of the network under series resonance will load the
line, possibly decreasing range. For your particular line coupling circuit, measure for series resonance using some expected line impedance load.

~

~F: 16~IJ)

10

0.1

kHz.

10

....
.z

=
co

1
100

"-

RG-GAIN·SETTING (0]

z

FIGURE 11. Output amplifier current and required min.
Qs h'e versus gain-setting resistor RG

co
~

:-..

~

TL/H/6750-13

!!5

100

~

0.1
0.1

1

z
co

10

~
iii

Cc-LlNE COUPLING CAPACITANCE (~F)
TLlH/6750-11

10

is

FIGURE 9. Cc's impedance should be,
as a rule-ot-thumb, smaller than the lowest
expected line impedance

~

"'
~

iii
O!

RG
This resistor, in paralle) with the internal 10n resistor, fixes
the current gain of the output amplifier, and so the output
current amplitude. Figure 11 gives output current and minimum AC current gain hie for as when RG is used to boost
output current.

0.1
10

100

1000

IO-OUTPUT CURRENT (mArms)

TL/H/6750-14

FIGURE 12. Boost transistor power dissipation versus
amplifier output current
2T must be used unless some precaution is taken to protect
the Carrier 110 pin from line transients or transients caused
when stored line energy in Ce is discharged by the random
phase of power line connection and disconnection. Worst
case, Ce may discharge a full peak-to-peak line voltage into
the tuned circuit. Another way to reduce the need for 2T is
by placing another magnetic circuit in the signal path that
relies on a high. but easily saturated, permeability to couple
a primary and secondary winding - a toroidal transformer for
example. Toroids cost more than 2T.
Use an avalanche diode designed specifically for transient
suppression - they have orders of magnitude higher pulse

Qs
The boost gain transistor as must be fast. Double-diffused
devices with 50 MHz FT'S work, slower transistors (epi-base
types) do not preserve a sinusoidal waveform when Fa is
high or will cause the output amp. to oscillate. as must have
a certain minimum hie for given boost levels, as shown in
Figure 11. Figure 12 shows the power as must dissipate
continuously operating with a shorted output. BVeER (R =
Rs) must be 60V or greater and as must have adequate
SOA for transient survival.

ZT
Unfortunately, potentially damaging transient energy passes
through transformer T 1 onto the Carrier 110 pin (instanta5-147

Component Selection (Continued)
differential inputs of the Norton amp. equally, while the single-ended input signal swings only the positive input. Overall
PSRR consists of the input CMRR (set by the input stage
component matching) and the ripple-frequency attenuation
of the input amplifier bandpass response that passes carrier
frequency but stops low frequencies. A typical 1% resistor
and 1 mV n-p-n mirror offsets give 26 dB of attenuation, the
bandpass gives 54 dB 120 Hz attenuation, for an overall 80
dB PSRR to allow tens of volts of ripple before impacting
ultimate sensitivity.

power capability than standard avalanche diodes rated for
equal DC dissipation. Metal oxide varistors have not proven
useful because of their inferior clamping coefficient and are
not recommended. Specifications for an example minimum
diode are given in Figure 13.
Breakdown Voltage
44-49V@ 1 mA
Maximum Leakage
lp.A @40V
300pF@BV
Capacitance
Maximum Clamp Voltage
Peak Non-Repetitive Pulse Power
(REA Standard Exponential Pulse)
Surge Current

64.5V@7.8A
10 kWfor 1 ,..S

Cc
A value was chosen earlier. Knowing T1'S secondary inductance allows a check of LC line attenuation using Figure 14.

70A for 1/120s

FIGURE 13. Key specifications for a recommended
transient suppressor ZT available from General
Semiconductor, 2001 West Tenth Place, Tempe, AZ
85281,602-968-3101, part no. SA40A

CL
The Norton input limiter amplifier has a bandpass filter for
enhanced receiver selectivity, noise immunity, and line frequency rejection. The nominal response curve for Fa = 50
kHz is shown in Figure 15. The 300 kHz pole is fixed. The 50
kHz pole is set by CL's value. After CL is found, the resulting
line frequency attenuation is found for the bandpass filter.

RT
RT acts as a voltage divider with ZT, absorbing transient
energy that attempts to pull the Carrier Input pin above 44V.
Make the resistor a carbon composition 1/4W. When experiments discharging Ce charged to the peak-to-peak 620V
AC thru a 1n power line were carried out, film resistors blew
open-circuit.

Use Figure 15 to find a CL value given for Fa. The approximate line frequency attenuation of the bandpass filter may
then be found in Figure 16. Figure 15 returns a value for CL
33% larger than nominal, giving a low frequency pole 33%
low to allow for component tolerances.
2110
III

OT
This Schottky diode is placed in parallel with the CCT chip's
substrate diode to pass the majority of the current drawn
from ground when the Carrier Input or Carrier Output is
pulled below ground by a larger-than-twice-the supply-swing
on the tank. Note that ZT is in parallel with the substrate
diode, but is ineffective due to its high forward voltage drop
and high diffusion capaCitance caused by its low forward
speed. Tests proved that a 1N5818 kept a receive-path
functional with a 20X boost transmitter with a 7:1 transformer attempted to swing the receiver's Carrier 110 to ± 100V
(300 mA peak ground current in the receiver). Without Dr,
the receiver momentarily stops functioning at a 100 times
lower ground current.
This diode is not needed if the Carrier liD never swings
below ground. If your CCT systems all run on the same
regulated voltage with all matched transformers and turns
ratios, it is not needed. Otherwise, it is.

!'180 -~

~

160

1,H

~

rnt-..

5 140

"'"III

~

In...

g 120

100

ill~01~
rnt-..

III
0.1

10
CC-COUPLING CAPACITANCE (/-IF)

TLlH/6750-15
FIGURE 14. The 60 Hz line rejection of the highpass
filter made up of Cc and T 1'S line-side winding
(neglecting capacitive coupling)

40

THE RECEIVER
The receiver and transmitter share components Ce, T1, Ca,
RT, ZT, Co, Ro, and peripheral supply and bias components
that are not in need of change for RX mode operation. Values for the balance of the components are now found.
TLlH/6750-16

Line-Frequency Rejection
To use the ultimate sensitivity of the device, fully 110 dB of
115 V, 60 Hz attenuation is required between the line and
the limiter amplifier output. Using the circuit topology of Figure 4, the combined attenuation of the CelT1 high pass, the
tuned transformer, and the bandpass filter attenuation of
the limiter amplifier give far more line rejection than the
above·stated minimum. However, if some other CCT line
coupling circuit is used, line rejection will become important
to the system designer.
Receiver input power supply rejection (PSRR) and commonmode rejection (CMRR) are one-in· the-same using the supply-referenced signal input of Figure 4. Ripple swings both

~ 1~~11~~11

I

~01 •

i

•

I

a 0.01

L......I...J..J..l.J.J.JJI_.I..-I...IlIU.wJ

10

100

11100

F,-CENTER FREQUENCY IkHzl

TL/H/6750-17
FIGURE 15. Given Fo, CL is found. Also shown Is the
input amplifier's small signal amplitude response
5-148

Component Selection

(Continued)
obvious way out is to then reduce the unfiltered loop bandwidth. That bandwidth is approximately proportional to the
value of Co. For a fixed Fo, unfiltered loop bandwidth reduction requires a larger Co and larger control current. With this
chip, changing the control current is not allowed. So one is
forced to choose a CF/RF combination with some minimum
capture range, say ±20%, that is within some guardband
from the point of loop instability. Happily, impulse noise
tends to last only fractions of a millisecond so that the lack
of low bandwidth loop response with low data rates is not a
heavy penalty. As long as there is adequate capture range,
the impulse noise filter performs admirably. Note that reducing Fa will reduce the no-filter loop bandwidth, and indeed
the maximum data rate falls below the limit set by the RC
lowpass filter as Fo falls below 100 kHz (Figure 1~.
The tuned transformer characteristics will affect the demodulated data waveform more than CF and RF at low data
rates. Tank Q and off-tuning will affect overshoot during the
FSK frequency steps. This is a property of tuned circuits.
The maximum data rate of Figure 19 is measured from the
receiver input to the Data Out and does not include the data
bandwidth reducing effects of TI.

CFand RF
These phase-locked loop (PLL) loop filter components remove some of the noise and most of the 2Fo components
present in the demodulated differential output voltage signal
from the phase detector. They affect the PLL capture range,
loop bandwidth, damping, and capture time. Because the
PLL has an inherent loop pole due to the integrator action of
the ICO (via CO), the loop pole set by CF and the zero set by
RF gives the loop filter a classical 2nd-order response.
"" 70

5
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30 1-+44+~~-+Htl~

20 '--.l...J.~WJL--'-,-u.uJJJ
0.01
0.1
1
CL-PDlE·smING CAPACITANCE ("FI

TLIH/6750-1B

FIGURE 16. The Norton-input limiter amplifier bandpass
filter line-frequency signal attenuation given CL

100
1000
F,,-1:ARRIER FREQUENCY IkH'1

CM
Capacitor CM stores a voltage corresponding to a correction
factor required to cancel the phase detector differential output DC offsets. The stored voltage is % of the DC offset
plus some bias level of about 2.2 V. A large CM value increases the time required to bias-up the receive path at the
beginning of transmission. A large CM does filter well and
store its bias voltage long. Because of the initial random
charge of CM, the receiver must be given a data transition to
charge to the proper bias voltage. Therefore, reduCing CM'S
value to one that may be charged in less than 2 bit-times will
not save biaSing time and is not recommended.

TL/H/6750-19

FIGURE 17. Find CF given Fo. Figure 19
gives the maximum data rate
No CF and RF give the most stable PLL with the fastest
response. Large CF'S with a too-small RF cause PLL loop
instability leading to poor capture range and poor step response or oscillation.
Calculation of CF and RF is quite difficult, involving not only
the 2nd-order loop step response, but also the PLL nondominant poles, the tuned transformer stepped-frequency
response, and the RC lowpass step response (for data rates
approaching 1 kHz). CF and RF values are best found empirically. Tolerance is not critical. Component values are selected to give the best possible impulse noise rejection
while preserving a ± 20% capture range and wide stability
margin. Figures 17 and 18 give CF and RF values versus Fa,
where "fDATA < < MAX DATA RATE" means that fDATA
should be less than the maximum data rate, in kHz, from
Figure 19 divided by 10.
Note that CF and RF are a function of data rate only for high
data rates and are not plotted against data rate - as one
might expect. The reason for this is important to understand
if the CCT system designer wishes to find CF and RF empirically. Data Signal is, loosely speaking, passed through the
PLL loop and is therefore potentially attenuated if the loop
bandwidth is on the order of the 3rd harmonic of the data
rate, or less. Overall loop bandwidth is held as low as possible for maximum noise rejection while passing the data.
Loop bandwidth is roughly proportional to the geometric
mean of the unfiltered loop bandwidth and the filter pole set
by CF. Therefore, CF is related to data rate. Unfortunately,
the loop capture range falls to critically low values when
large enough values of CF are used to reduce loop bandwidth down to the 1OO's of Hz range, for low data rates. The

100

E'±;"2~0%;"!CA~PT=U'!!RE~R~AN=';GE~--

100
1000
Fa-CARRIER fREQUENCV (kHz)

TLlH/6750-20

FIGURE 18. Find RF given Fo with FOATA a parameter

i

".

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~

20

10

10

5

6

,

,.
~

~

4D-fiDIIIr DATA OUT

I
2
10

IfriiElll1
100

~

..li~
"

1

1000

Fo-CARRIER FREQUENCY IkH2)

TL/H/67S0-21

FIGURE 19. The maximum data rate versus Fo using
loop filter components optimized for max. noise
performance while retaining a min. ± 20% capture
range (large signal)
Use Figure 20 to find CM'S value knowing fDATA' assuming
the standard 2 bit receive charge time is desired. The cap.
value and TC are not critical, but the capaCitor should have
low leakage.

5-149

Component Selection

I§

1000

~

100

i

10

;

(Continued)
ZA
The 5.1V silicon zener diode ZA is required when a short
RX-to-TX switch-over time is needed at the same time that
the chip is operating in the RX mode with a pin 10 input
signal swing approaching or exceeding twice the supply
voltage. Predominant causes of these large swings imping'
ing on the RX input are: 1) a transmitter's supply voltage
higher than the receiver's supply voltage, 2) a TX and RX
pair that are electrically close, or, 3) a higher RX T 1 step-up
turns ratio than the TX T1 step-down ratio.
Normally, when in the RX mode with small incoming signal
on pin 10, the ALC remains off with pin 7 at a BV
(Vz-2VSE) bias voltage. CA is then charged to BV. TX
mode may then be selected with BV on CA allowing 100%
TX power to pump Tl's tuned circuit, and so the AC line,
quickly for fast RX-to-TX switch time. As TX output swing
increases so that pin 10 swings below VALC (4.7V typically),
that ALC activates to charge CA to about B.BV to reduce TX
output drive. However, if in the RX mode pin 10 ever swings
below VALC, CA will charge to above B.BV. Now, when the
TX mode is selected with CA at B.BV, somewhere from 0 to
100% TX output drive is available to pump T1 's tuned circuit
resulting in a slower rising line signal - effectively reducing
the RX-to-TX switch time.

I

lJ
IDATA-OATA RAlt (Hz)

TL/H/6750-22

FIGURE 20. Size CM assuming a 2 bit-time
receive bias time
CI
The impulse noise filter integrator capacitor CI is used to
disallow the passage of any pulse shorter than the integra·
tor charge time. That charge time, set to a nominal % bit
time, is the time required for a ± 50 ",A charge current to
swing Clover a 2 VSE range. Charge time under worst case
conditions must never be greater than a bit time since no
signal could then pass. Using a ± 10% capacitor, full junction temperature range, and full specified current range, a
maximum nominal charge time of % bit is recommended.
Figure 21 gives CI versus data rate under those conditions.

Use a 5.1 V ZA driven by a 0 to O.SV logic low signal to
guarantee over-temp. operation. RA must be in series with
ZA to limit current flow and should never fall below 1 kfi. If
RA is less than 1 kfi, then put a 2 kfi resistor in series with
ZA. Logic high voltages above 10V will cause current flow
into pin 7 that must be limited to 1 mA (with RA or a
series R).

Rc
The collector pull-up resistor is sized to supply adequate
pull·up current drive and speed while preserving adequate
output low current drive.
~1000
w

!

Breadboarding Tips

~ 100

During CCT system evaluation, some techniques listed below will simplify certain measurements.

~

'"c
!:!

~I

10

-

is

100
1000
IDATA-OATA RATE (Hz)

10.000
TLlH/6750-24

FIGURE 21. Impulse noise filter cap. CI versus FOATA
where the charge time is % bit time

Use caution when working on this circuit - dangerous
line voltages may be present.
When evaluating PLL operation, offset cancel circuit operation, and loop filter values, use the filter of Figure 22
to view the demodulated signal minus the 2Fo and noise
components. This filter models the RC lowpass filter on
chip.

PIN 3

10k
1%

PIN 4

Vo

TL/H/6750-25

FIGURE 22. Circuit to view the differential demodulated data signal, minus the noise and 2Fo components,
conveniently with a single-ended gain-of-one output

5-150

Breadboarding Tips
-

-

-

-

(Continued)

When evaluating CCT system noise performance on a
real power line, it is desirable to vary the signal amplitude to the receiver. This is not easy. An in-line lineproof L-pad is fine except that the line impedance is unknown and variable and so the L-pad will rarely match.
Instead, the power output of a chip transmitter may be
controlled using the circuit of Figure 23. This circuit controls the ALC.

representing an average line impedance may be connected
to the line side of T1. The circuit of Figure 23 should then be
used to defeat the leveling effect of the ALC.

v+
75k

It is sometimes desirable to place impulse noise on the
line. A simple light dimmer with a 100 W light bulb load
produces representative impulse noise.
Do not allow peak currents of over 1 A through the 5.6 V
Zener. In other words, don't short charged capacitors
into this low-impedance device. Take care not to momentarily short pins 10 and 11 - chip damage may result.

ptN7-....-+~

TLlH/6750-26

FIGURE 23. A means of transmitter output amplitude
control is shown

Figure 24 shows some typical signals beginning with serial data transmitted to received signal.

Thermal Considerations

4. Place a scope on pin 10.
5. Adjust the transformer slug for the least envelope modulation.

It is desirable to place the largest possible signal on the
power line for maximum range, limited only by the chip power dissipation and maximum junction temperature TJ. The
falling output power at elevated TJ allows a more optimal
power output - high power at low T J and lower power at high
TJ for chip self-protection. However, it is still possible to
exceed the maximum TJ within the specified ambient temperature limit (TA = 85°C) under worst case conditions of
100% TX duty cyle, high supply, shorted load, poor PC
board layout (with small copper foil area), and an above
nominal current part. Under those conditions, a part may
dissipate 2140 mW, reaching a TJ = 170°C worst-case (admittedly a rare occurrence). Proper system design includes
the measurement or calculation of TJ max. to guarantee
function under worst-case operation. Like all devices with
failure modes modeled by the Arrhenius model, the high
chip reliability is further enhanced by keeping the die temperature mercifully below the absolute maximum rating.
A direct method of measuring operating junction temperature is to measure the VBE voltage on pin 18, which is always available under all operating modes. The graph of Figure25may be used to find TJ, knowing VBE at the operating
point in question and VBE at TA = TJ = 25°C. VBE is found
by powerin\l up a chip (in RX mode) that has been dissipating zero power at some TA for some time and measuring
VBE in less than 1 s (for better than 5°C accuracy).
Alternately, TJ may be calculated using:

In lieu of the 330 !1 resistive load, T1 may be coupled to the
power line to better simulate actual load and tank pull conditions during tank tuning. Alternatively, a passive network

(1)
TJ = TA + lIJAPD
where lIJA is 75°C/W for the plastic (N) package using a
socket. That lIJA value is for a high confidence level; nomi-

Tuning Procedure
This procedure applies to circuits similar to Figure 4 LM1893
or LM2893 circuit.
First, trim Fa by putting the chip in the TX mode, setting a
logical high data input, and measuring the TX high frequency, 1.022 Fa, on the Carrier 1/0 using these steps:
1. Take pin 17 to a logic low.
2. Take pin 5 to a logic high.
3. Place a counter on pin 10.
4. Adjust Ra on pin 18 for F = 1.022Fa.
Second, the line transformer is tuned. The chip is placed in
the TX mode, a resistive line load is connected to disable
the ALC by reducing tank voltage swing below its limit. FSK
data is then passed through the tank so that the tank envelope may be adjusted for equal amplitude for high and low
data frequency.
1. Take pin 5 to a logic high.
2. Place a logic-level square wave at or below the receiver's
maximum data rate on pin 17.
3. Temporarily place a 330 !1 resistor across the tank.

(1)

10 V/Oiv.

(2)

10 mY/Diy.

(3)

400 mY/DiY.

(4)
(5)

200 mY/DiY.
2 V/Div.

(6)

10 V/Div.

TLlH/6750-23

FIGURE 24. Oscillogram revealing signals at several important nodes under weak signal (0.5 mVRMS) conditions with
SCR spikes on an otherwise quiet 115 V, 60 Hz power line. The signals are: 1) transmitted data, 2) RX carrier on the
tuned transformer, 3) demodulated signal from the PLL after passing thru circuit of Figure 22,4) signal after RC
lowpass, 5) data at impulse noise filter integrator, and 6) received data. Horizontal scale is 10 ms per div.
5-151

~

...

,-------------------------------------------------------------------------~

0)

co

Thermal Considerations (Continued)

:::aE

nal (JJA for an N package is 60'C/W, lower with good PC
board layout. Since Po is a relatively strong function of TJ,
an iterative solution process starting with an initial guess for
TJ is used. With the estimated TJ, find the total supply current found in the typical performance characteristics.

...I

mended CF and RF (47 nF and 6.2 kO) with a ±4.4% AFa
(a ± 100 mV DC offset on CF and RF), lock was measured
to take less than 50 cycles of Fa. That is a 0.40 ms delay
(proportional to 1/Fa).
Acquisition is incomplete until the second order PLL loop
settles. For the above-mentioned CF and RF, the loop natural frequency FN and damping factor are found to be
2.3 kHz and 1.0 respectively. Settling to within ±25 mVof
the ±100 mV DC offset change requires 2.7 periods of FN,
or 1.2 ms (a function of CF and RF).
Third, the RC lowpass filter introduces a 0.12 ms delay.
Fourth, CM must charge up to ±(%)100 = 83 mV depending on the polarity of Fa. Borderline data squaring with zero
noise immunity is possible with only ± ("Is) 50 mV of charging. CM charge current is an asymptotic function approximated by assuming a 50 p.A charge current and the full 83
mV charge voltage. CM charge time is then 1.7 ms (proportional to 1/fOATA).
Fifth, the impulse noise filter adds a % bit-time delay. Total
TTR is 3.9 ms plus Y2 bit-time for a total of 1.9 bit-times at
360 Baud.

1.3
1.2

~ 1.1

lQ
11

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!\.. ~... -1.87 m~oC- t -

10

~.

~ 0,9

-i

1'\

0.8

"""

0.7

!\..

0.6
-60 - 30 0 30 60 90 120 150 180

TJ-JUNCTlDN TEMPERATURE lOCI

TL/H/6750-27

FIGURE 25. T J may be found by using the temperature
coefficient of pin 18 VBE if VBE is known at 25'C

Transmit-To-Receive
Switch-Over Time

Receive-To-Transmit
Switch-Over Time

An important figure-of-merit for a half-duplex CCT link, affecting effective data rate, is the TX-to-RX switch time TTR.
Using the recommended component values gives this part a
nominal 2 bit-time (1 bit time = 1/[2fOATAlJ over a wide
range of operating conditions, where the receiver requires 1
data transition. TTR cannot be decreased significantly but
does increase as noise filtering, especially via CM, is increased. Impulse noise at switch, signals near the limiting
sensitivity, poor Fa match between receiver and transmitter
because of poor trim or worst-case conditions, and the statistical nature of PLL signal acquisition may all contribute to
increase TTR to possibly 4 bit-times.
TTR is lower when a pair of LM1893's handshake rapidly.
The receiver was designed to "remember" the RX-mode
DC operating pOints on CM and CF while in the TX mode.
Under noisy worst case conditions, CM will discharge to the
point of false operation after 35 bit-times in the TX mode
(1400 bit times with no noise and a nominal part, fOATA =
180 Hz). TTR is about 0.8 ms (proportional to the selected
Fa) plus % bit-time.
The major components of TTR are described below for a
nominal 125 kHz Fa, 180 Hz fOATA, lightly-loaded tank with
a Q of 20, and the circuit of Figure 4. The remote CCT has
been operating in the TX mode with a 26.6 Vpp tank swing
and is now selected as a receiver. An incoming signal requiring the ultimate receiver sensitivity immediately is placed
on the line.
First, the tank stored energy at the transmit frequency must
decay to a level below the 2.8 mVpp swing caused by the
0.14 mVRMS incoming line signal containing the information
to be received.
decay time =
20

'IT

~In (.!'i)
'lTFa

Va

Power Line Impedance
Irrespective of how wide the limits on power line impedance
ZL are placed, there are no guarantees. However, since the
CCT design requires an estimate of the lowest expected line
impedance ZLN encountered for the most efficient transmitter-to-line coupling, line impedance should be measured
and ZL limits fixed to a given confidence level. Reasonable
values for T 1 turns ratio, loaded Q, and tank resonant frequency pull Fa may be found to enable a CCT system design that functions with the overwhelming majority of power
lines.
A limited sampling of ZL was made, during the LM1893 design, of residential and commercial 115V 60 Hz power line.
Data was also drawn from the research of Nicholson and
Malack (reference 1), among others, to produce Figures 26
and 21. All measured impedances are contained within the
shaded portions of Figure 21. A nominal 3.5, 7.0 and 14 0
ZLN is used throughout the application information with a
nominal 45' phase angle (0' is sometimes used for simplicity).
100

§:

=

I
!!

( 26.6 )

x 125000 In 0.0028

Assume the chip has been in the RX mode and the TX
mode is now selected. In less than 10 p's, full output current
is exponentially building tank swing. 50% of full swing is
achieved in less than 10 cycles - or under 80 P.s at 125 kHz.
In the same 10 P.s that the output amp went on, the phase
detector and loop filter are disconnected and the modulator
input is enabled. FSK modulation is produce'd in 10 p.s after
switching to TX mode.

= 0.466 ms

(2)

bl"9MEAN
10

!!'i

MAX

lo4-l-

t-MIN

I

.A

That is 0.47 ms of delay (proportional to IIFa and Q).
Second, the PLL must acquire the signal; it must lock and
settle. Acquisition time is statistical and may take any length
of time, but average acquisition time depends on the loop
filter components CF and RF and the difference in center
frequencies, AFa, of the TX/RX pair. Using the recom-

I

1

50

100

150

200

250

F.-CARRIER FREQUENCY IkHzI

300

TLlH/6750-28

FIGURE 26. Measured line impedance range for
residential and commercial 115V, 60 Hz lines
5-152

r-

s:
.....

Power Line Impedance (Continued)

CI)

~~

~~

50
40
3D
20
10

50
40
3D
20
10

BBo
6°

o H?%""'+-~RL (Il)

RL (Il)

-10
-20
-30
-40
-50

-3~

-40
-50

Co)

50
40
3D
20
10

RL (Il)

50

-10
-20

CD

JXL(Il)

-10
-20
-30
-40
-50

-BO°

TLlH16750-29

TLIH16750-30

TLlH16750-31

FIGURE 27. Complex-plane plots of measured 115V, 60 Hz line impedance where ZL = RL + jXL

Power Line Attenuation
The wiring in most US buildings is a flat 3 conductor cable
called Amerflex, BX, or Romex. All referenced line impedances refer to hot-to-neutral impedances with a grounded
center conductor. The cable has a 100 n characteristic impedance, a 125 kHz quarter-wavelength of 600 m (250 m at
300 kHz), and a measured 7 dB attenuation for a 50 m run
with a 10 n termination. Generally, line loads may be treated as lumped impedances. Instrument line cords exhibit
about 0.7 /-,H and 30 pF per meter.
Limited tests of CCT link range using this chip show extensive coverage while remaining on one phase of a distribution transformer (100's of m), with link failure often occuring
across transformer phases or through transformers unless
coupling networks are utilized. Total line attenuation allowed
from full signal to limiting sensitivity is more than 70 dB.
Typically, signal is coupled across transformer phases by
parasitic winding capacitance, typically giving 40 dB attenuation between phased 115 V windings. Coupling capacitors
may be installed for improved link operation across phases.
Power factor correcting capacitor banks on industrial lines
or filter capacitors across the power lines of some electronic
gear short carrier signal and should be isolated with inductors. Increasing range is sometimes accomplished by electing to install the isolating inductors (Figure 28) and coupling
capacitors, as well as by electing to use the boost option.
Frequency translating or time division multiplexed repeaters
will also increase range.

T 1 with a stable resonant frequency, Fa, that is little affected by the de-tuning effect of the line impedance Zl, and of
2) building a tightly line-coupled transformer for transmitted
carrier with loose coupling for transients, are somewhat mutually exclusive. The tradeoffs are exposed in the following
example for the CCT designer attempting a new boost-capable, or different core, transformer design.
The compromises are eased by separating the TX output
and RX input in the LM2893. An untuned TX coupling transformer with only core coupling (not air-coupled solenoid
windings) would employ a high permeability, high magnetic
field, low loss, square saturating, toroidal core. The resonant RX path would be isolated from line-pull problems by a
unilateral amplifier that operates at line voltages with much
more than 110 dB of dynamic range, or by a capacitively
coupled pulse transformer driving a unilateral amplifier and
filter, for increased selectivity. See the LM2893-specific applications section.
For a LM1893-style transformer application, first, choose
the turns ratio N based on an estimated lowest Zl likely
encountered, ZlN. Figure 29 shows graphically how N affects line signal. N should be as large as possible to drive
ZlN with full signal. If T1 has an unloaded Q, Qu, of well less
than 35, a guess of N somewhat high should be used and
later checked for accuracy. The recommended transformers
have secondary taps giving a choice of N = 7.07, 10, and
14.1 (nominally) for driving ZlN'S of 14, 7.0, and 3.5 n respectively (at TJ = 25°C, V+ = 18V, and Qu = 35).
The resonating inductance of the tuned primary, L1, is
sought. Note that, while standard transformer design gives a
transformer self-inductance with an impedance at operating
frequency well above load impedance, the tuned transformer requires a low L1 for adequate Qu and minimum line pull.
Result: relatively poor mutual coupling.

ISOLATED

AC
LINE

LDAD
50 ~H

50

~H

R

TLlH16750-40

L1=-(3)
2'ITFOQ
It is known that resonant frequency Fa
Fo and some
minimum bandwidth, or maximum Q, will be required to pass
signal under full load conditions.

FIGURE 28. An isolation network to prevent: 1) noise
from some device from polluting the AC line, and 2) to
stop some low impedance device (measured at Fo)
from shorting carrier signal. Component values given
as an example for Fo = 125 kHz on
residential power lines

L1 = Ra IllzlNI'
(4)
2'IT FOQl
IZLNI' is the reflected ZlN, Ql is the loaded Q, and parallel
resistance Ro models all transformer losses and sets Qo.

The Coupling Transformer
The design arrived at for T1 is the result of an unhappy
compromise - but a workable one. The goals of 1) building

Ro IllzlNI' is found knowing that it absorbs full rated power.

5-153

~ r-------------------------------------------------------------------------------~
Q)

CC)
.,...

::i

The Coupling Transformer (Continued)
Line pull IlFa was calculated (reference 3) for a ZL magnitude of 140 and up with any phase angle from -90" to 90".
IlFa was 6.4% - well above the 3.3% estimate. Referring to
(11), an l1.B% bandwidth is required, forcing L1 to be reduced to reduce Q. That fix was not implemented; some
signal attenuation under worst-case drift and IlFa is allowed. L1 is already so small that the 31 gauge winding
conducts a % ARMS circulating current.

...I

~.,.

!

...

I...

~

N-7.07
N-10-

,~

N=14.1

4

12

z

::;

~

I,..

o

Line Carrier Detection

~

o

16

20

While the addition of a carrier detection circuit (for a mute or
squelch function) will only decrease receiver ultimate sensitivity, there is sometimes good reason to employ it to free
the controller from watching for RX signal when no carrier is
incoming, or to employ it to reduce the probability of line
collisions (when multiple transmitters operate simultaneously to cause one or more transmissions to fail). Unless the
detector is heavily filtered or uses a high carrier amplitude
threshold, there will be false outputs that force the controller
to have Data Out data checking capability just as is required
when using no carrier detector. If false triggering is minimized, the probability of line collisions is increased due to
the inability to sense low carrier amplitudes and because of
sense delay. The property of the LMl B93 to change output
state infrequently (although the polarity is undefined) when
in the RX mode, with no incoming carrier, reduces the desire
to implement carrier detection and preserves the full ultimate sensitivity. Also, many impulse-noise insensitive transmission schemes, like handshaking, are easily modified to
recover from line collisions.
Regarding this, it should be stated that for very complicated
industrial systems with long signal runs and high line noise
levels, it is probably wise to use a protocol which is inherently collision free so that no carrier detect hardware or software is needed. A token passing protocol is an example of
such a system.
Figure 30 shows a low cost carrier amplitude detection circuit.

z.. -LINE IMPEDANCE (0)
TLlH/6750-32

FIGURE 29. Impressed line voltage for a given ZL
for each of the 3 taps available
on the recommended transformers
P =1 V =IOPP[2(-VALC+V+)]=(-4.7+V+)10
o 0 0 2,/2
2,/2
4

(5)

where 10 is in amps peak-to-peak at an elevated TJ
Po = (lB - 4.7) 0.06 = 0200 W

4

.

(6)

RalllzLNI' = V02 = (-VALC + V+),/2 = 4420
(7)
Po
10
Ra is found using ZLN and the value for N found when assuming Qu = 35.
IZLNI' = N2 ZLN = (7.07)2 13.9 = 695 0
(B)
Ra = - - 1 - - - - 1 -

1
---=12100
1
442 695

(9)

---

RoIllzLNI' - IZLNI'
Ra
1210
Ras = 1 + Qu2 = 1 + 352 = 1 0

(10)

Only QL remains to be found to calculate L1. QL is related to
the -3 dB (half-power) bandwidth by
1
QL = BW (% of Fo)

(11)

Audio Transmission

An iterative solution is forced where line pull, IlFa, must be
guessed to find QL and L1. L1 is then used to check the line
pull guess; a large error requires a new guess. Try a BW of
B.7% - that is 4.4% for deviation, 1% for TC of Fo, and
3.3% for IlFo - giving QL = 11.5.
L =
442
= 49.0 H
P.
1 21T X 125 000 X 11.5

The LM1B93 is designed to allow analog data transmission
and reception. Base-band audio-bandwidth signals FM
modulate the carrier passing through the tuned transformer
(placing a limit on the usable percent modulation) onto the
power line to be linearly demodulated by the receiver PLL.
Because the receiver data path beyond the phase detector
will pass only digital Signal, external audio filtering and amplification is required. Figure 31 shows a Simple audio transmitter and receiver circuit utilizing a carrier detection mute
circuit. A single LM339 quad. comparator may be used to
build the carrier detect and mute. Filter bandwidth is held to
a minimum to minimize noise, especially line-related correlated noise.

(12)

Knowing the core inductance per turn, L, and L1, the number of turns is found.
1
- =
~
L

49.0p.H
- - - = 4 9 % turns
(13)
20 nHIT
T is normally an integer, but these transformers require so
few turns that half-turns are specified, remembering that the
remaining % turn is completed on the P.C. board and is
loosely coupled. The secondary turns are calculated

T1 =

T2 =

T1

N

49.5
= 7.07 = 7.00 = 7 turns

Communication and System
Protocols

(15)

The development of communication and system protocols
has historically been the single most time consuming element in deSign of carrier current systems. The protocols are
defined as the following:
1. Communication protocof. a software method of encoding
and decoding data that remains constant for every transmis-

giving an L2 of 0.9B p.H. Note that the recommended 125
kHz transformer mirrors these specifications. The resonating capacitor is
1
Co = (21TFa)2 L1 = 33.1 X 10- 9 = 33 nF

(16)

5-154

r-~--~--~~~'f~ruR~

/t

1. tON OFF=O.2ms

CARRIER
DETECT

2. SENSITIVI!Y=5mV OR LESS
3. PARTS COUNT=11
4. NOISE INSENSITIVE

LM567

DATA OUT 12
RX SEL 6
DATA IN 17

TJ(

TL/H/67S0-33

FIGURE 30. A simple carrier amplitude detector with output low when carrier is detected

LM1893jPIN 3

PIN 4

-41---.I\IV'v-....-""'.-.....---4-~..:.t

2.7

1500~F

~O.l~F

PIN 18.-1
LM1893,

TRANSMITIER

1.6V

80

SPKR

U!O!_ !U1DJ~ IN
1""'---- ±2 5,.11

±2:2% DEV

TLIH/6750-34

FIGURE 31. A simple linear analog audio transmitter and receiver are shown.
The carrier and 1.GV inputs are derived from the carrier detector of Figure 30.
The remaining 2 LM339 comparators may be used to build the carrier detector Circuit.

Communication and System
Protocols (Continued)
sion in a system. Its first purpose is to put data in a baseband digital form that is more easily recognized as a real
message at the receive end. Secondly, it incorporates encoding techniques to ensure that noise induced errors do
not easily occur; and when they do, they can always be
detected. Lastly, the software algorithms that are used on
the receive end to decode incoming data prevent the reception of noise induced "phantom" messages, and insure the
recovery of real messages from an incoming bit stream that
has been altered by noise.
2. System protocol. the manner in which messages are coordinated between nodes in a system. Its first purpose is to

ensure message retransmission to correct errors (handshake). Secondly it coordinates messages for maximum utilization and efficiency on the network. Lastly, it ensures that
messages do not collide on the network. Common system
protocols include master-slave, carrier detect multiple access, and token passing. Token passing and master slave
have been found to be the most useful since they are inherently collision free.
Both protocols usually reside as software in a single microcontroller that is connected to the LM1893/2893 110. In any
case, some sort of intelligence is needed to process incoming and outgoing messages. UARTs have no usefulness in

5-155

~

~
,....
:::liE

...I

r---------------------------------------------------------------------------------~

the transmitter might choose to give up. Collision recovery is
achieved by waiting some variable amount of time before retransmission, using a random number of bits delay or a delay based on each transmitter's address, since each transceiver has a unique address.
An example of a simple transmission data packet is shown
in Figure 32. The 8 bit 50% duty-cycle preamble is long
enough to allow receiver biasing with enough bits left over
to allow the receiver controller to detect the square-wave
that signals the start of a transmission. If there had been no
transmission for some time, the receiver would simply need
to note that a data transition had occurred and begin its
watch for a square-wave. If the receive controller detected
the alternating-polarity data square-wave it would then use
the sync. bit to signal that the address and data were immediately following. The address data would then be loaded,
assuming the fixed format, and tested against its own. If the
address was correct, the receiver would then load and store
the data. If the address was not correct, either the transmission was not meant for this receiver or noise has fooled the
receiver. In the former case, when the transmission was not
meant for the receiver, the controller should immediately
return to watching the incoming data for its address. If the
later case were true, then the receive controller would continue to detect edges, tieing itself up by loading false data
and being forced to handshake. The square-wave detection
and address load and check routines should be fast to minimize the time spent in loops after being false-triggered by
noise. If the controller detects an error (a received data bit
that does not conform to the pre-defined encoding format) it
should immediately resume watching the LM1893's Data
Out for transmissions, the next bit would be shifted in and
the process repeated.
A line-synchronous CCT system passing 3 bits per half-cycle may replace the long 8 bit preamble and sync pulse with
a 2 bit start-of-transmission bias preamble. The receive controller might then assume that preamble always starts after
bit 1 (the first bit after zero-crossing) so that any data transition at a zero crossing must be the start of the address bits
and is tested as such. The line synchronous receiver operates with a simpler controller than an asynchronous system.
Discussion has assumed that the controller has always
known when the Data Out is high or low. The controller
must sample at the proper time to check the Data Out state.
Since noise shows itself as pulse width jitter, symmetrically
placed about the no-noise switch-points, optimum Data Out
sampling is done in the center of the received data pulse.
The receive data path has a time delay that, at low data
rates, is dominated by the impulse noise filter integrator and
is nominally y. bit. At a 2 kHz data rate, an additional delay
of approximately '110 bit is added because of the cumulative
delay of the remainder of the receiver. Figure 33 shows that
Data Out sampling occurs conveniently at the transmitted

Communication and System
Protocols (Continued)
carrier current applications since they do not have the intelligence needed to distinguish between real messages and
noise induced phantoms.
The difficulty in designing special protocols arises out of the
special nature of the AC line, an environment laden with the
worst imaginable noise conditions. The relatively low data
rates possible over the AC line (typically less than 9600
baud) make it even more imperative that systems utilize the
most sophisticated means available to ensure network efficiency.
With these facts in mind, the designer is referred to two
publications intended to aid in the development of carrier
current systems. The first is literature #570075 The Bi-Line
Carrier Current Networking System, a 200 pp. book that
functions as the "bible" of Bi-Line system design. It has
sections on LM1893 circuit optimization, protocol design,
evaluation kit usage, critical component selection, and the
Datachecker/DTS case study.
The second is AN-463 "A New Carrier Current Protocol Utilizing an Active Transponder for Consumer and Industrial
Applications." It details the communication and system protocols developed by Datachecker/DTS for an energy management system.

Basic Data Encoding (please refer to the previously mentioned publications for advanced techniques)
At the beginning of a received transmission, the first 0 to 2
bits may be lost while the chip's receiver settles to the DC
bias point required for the given transmitterIreceiver pair
carrier frequency offset. With proper data encoding,
dropped start bits can be tolerated and correct communication can take place. One simple data encoding scheme is
now discussed.
Generally, a CCT system consists of many transceivers that
normally listen to the line at all times (or during predetermined time windows), waiting for a transmission that directs
one or more of the receivers to operate. If any receiver finds
its address in the transmitted data packet, further action
such as handshaking with the transmitter is initiated. The
receiver might tell the transmitter, via retransmission, that it
received this data, waiting for acknowledgement before acting on the received command. Error detecting and correcting codes may be employed throughout. The transmitter
must have the capability to retransmit after a time if no response from the receiver is heard - under the assumption
that the receiver didn't detect its address because of noise,
or that the response was missed because of noise or a line
collision. (A line collision happens when more than 1 transmitter operates at one time - causing one or more of the
communications to fail). After many re-transmissions

DATA PACKET

PREAMBLE
BBITS

~

II
SYNC
BIT

ADDRESS

WORD

I

DATA

WORD

I
TLlH/6750-35

FIGURE 32_ A simple encoded data packet, generated by the transmit controller is shown.
The horizontal axis is time where 1 bit time is 1I(2fOATA)

5-156

,-----------------------------------------------------------------------------,
Because the coupling transformer is used as a filter, the
Basic Data Encoding (Continued)
LM 1893 circuit is susceptible to pulling of the center frequency under conditions of changing line impedances or
when several LM 1893 circuits are close in proximity on the
AC line. Because the tuned transformer has a high value of
"0", ringing also occurs in the presence of impulsive noise.
This ringing occurs at the center frequency and increases
the error rate of transmissions, especially at relatively high
data rates (> 2000 baud). Because it is the only tuned circuit
in the system, the selectivity characteristics leave a lot to be
desired.

POWER UN' jL---j---+---.3j,~__!--+_____,F..;:

RXH, PIN 13

The LM2893, having separate receive input and transmit
output pins, removes the limitations on coupling transformer
design, allowing the design of circuits devoid of the previous
limitations.

RXR OATAOUT

TL/H/67S0-36

FIGURE 33. Operating waveforms of a linesynchronized transceiver pair are shown. The diagram
shows how the transmitted data transitions may be
used as received data sampling points

The first enhancement that can be made with the LM2893
circuit is the use of a high permeability ferrite toroid for line
coupling along with a separate filter. The transformer would
be of broadband design (untuned) with two secondaries,
one for coupling to the transmit output and one for coupling
to the receive input. This allows impedance matching of
both the transmitter and receiver, with the result of quite a
bit more receive sensitivity.

data edges for the line synchronous data transmission
scheme mentioned in the previous paragraph. With the
asynchronous system suggested, the receive controller
must sample the Data Out pin often to determine, with several bits of accuracy, where the square-wave data transitions take place, average their positions assuming a
known data rate, and calculate where the center of the data
bits are and will continue to be as the address and data are
read. A long preamble is helpful. Software that continuously
updates the center-of-bit time estimate, as address and
data are received, works even better. Alternatively, a coding
scheme employing an embedded clock can be used.

Because of the increased Signal and separate receive signal
path, a 3 or 6 db pad can be used before the selective
stages to eliminate pulling of the center frequency due to
changes in line impedance.
Another advantage of the toroidal transformer is that it can
be designed for use at very low line impedances due to its
inherent tight coupling.
SEPARATE FILTER

LM2893 Application Hints

Because of the separate receive path of the LM2893, a relatively high quality bandpass filter can be used for selectivity.
Inexpensive ceramic filters are available that have bandpass and center frequency characteristics compatible with
carrier current operation. Futhermore, the use of these filters allows multichannel operation, previously made difficult
by the single tuned network of the LM1893. These filters are
easily cascaded for even more off-frequency rejection. If the
pad is added before the filter, there will be negligible pulling
due to changes in line impedance reflected through the coupling transformer.

The LM2893 is intended for advanced applications where
special circuitry is used in the transmit and receive paths.
The LM2893 makes this possible by featuring separate
transmit output and receive input pins.
Examples of enhancements that can be added to the basic
LM1893/2893 circuit include separate transmit and receive
windings on the coupling transformer, high quality ceramic
or LC filters in the receive path, and simple impulse noise
blanking circuits.
In many applications, the additional performance to be
gained outweighs the extra cost of the additional Circuitry.
More than likely, high performance industrial applications
such as building energy management will fit into this category, since they require the utmost in reliability.

Alternatively, a Butterworth/Chebyshev bandpass LC filter
or an active filter can be used in place of the ceramic filter.
IMPULSE NOISE BLANKER
Although the LM2893 has adequate impulse noise rejection
for most applications, there is reason to employ impulse
blanking to improve error rates in severe AC line environments. Typically, errors occur due to pulse jitter in the
LM1893/2893 data output that originates when the internal
time domain filter smooths out an incoming noise pulse.

Because of the specialized nature of individual LM2893 applications, it is not possible to give one circuit that will satisfy
all requirements for performance and cost effectiveness.
Therefore no specific application examples will be given.
Instead the subsequent text describes in general terms the
types of circuits that can be used to increase performance
along with their advantages and disadvantages. It is intended to be a springboard for ideas.

The solution involves removing the impulse completely and
not simply trying to filter it. Moreover, the pulse should be
removed in the receive Signal path before the selective portions of the circuit to eliminate ringing. This also allows the
receiver filter to smooth out the blanks that also occur in the
desired incoming carrier signal.

LM2893 COUPLING NETWORKS
The main disadvantages of the typical LM1893 coupling
network are that it functions as the bandpass filter, has
loose coupling between primary and secondary, and has a
single secondary. The LM1893 coupling network was designed this way mainly because of the restraint that the carrier input and output are tied together.

If a carrier detect circuit is desired in conjunction with the
LM2893 it can be located after the filter and impulse blanker. Because impulse noise is removed, the false triggering
that plagues these circuits will be greatly reduced.

5-157

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(7)

,...

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Simplified Schematic

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References
1. Nicholson, J.A. and J.A. Malack; "RF Impedance of Power Lines and Line Impedance Stabilization Network in
Conducted Interference Measurements;" IEEE Transactions on Electromagnetic Compatibility; May 1973; (line
impedance data)
2. Southwick, A.A.; "Impedance Characteristics of SinglePhase Power Lines;" Conference Rec.; 1973 IEEE In!.
Symp. on Electromagnetic Compatibility; (line impedance
data)

4. FCC, "Notice of Proposed Rule Making," Docket 20780,
adopted Apr. 14, 1976, (Proposed regulation)
5. Monticelli, Dennis M. and Michael E. Wright; "A Carrier
Current Transceiver IC for Data Transmission Over the
AC Power Lines;" IEEE J. Solid-State Circuits; vol. SC-17;
Dec. 1982; pp. 1158-1165; (LM1893 circuit description)
6. Lee, Mitchell; "A New Carrier Current Transceiver IC;"
IEEE Trans. on Consumer Electronics; vol. CE-28; Aug.
1982; pp. 409-414; (Application of LM1893)

3. Hayt, William H. Jr. and Jack E. Kemmerly; "Engineering
Circuit Analysis;" McGraw-Hili Books; 1971; pp. 447453; (linear transformer reflected impedance)

LI
5-159

~

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r------------------------------------------------------------------------------------,

~ Semiconductor
NatiOnal

Corporation

LM19211 Amp Industrial Switch
General Description

Features

The LM1921 Relay Driver incorporates an integrated power
PNP transistor as the main driving element. The advantages
of this over previous integrated circuits employing NPN
power elements are several. Greater output voltages are
available off the same supply for driving grounded loads;
typically 4.5 volts for a 500 mA load from a 5.0 volt supply.
The output can swing below ground potential up to 57 volts
negative with respect to the positive power supply. This can
be used to facilitate rapid decay times in inductive loads.
Also, the IC is immune to negative supply voltages or transients. The inherent Safe Operating Area of the lateral PNP
allows use of the IC as a bulb driver or for capacitive loads.
Familiar integrated circuit features such as short circuit protection and thermal shutdown are also provided. The input
voltage threshold levels are designed to be TTL, CMOS,
and LSTTL compatible over the entire operating temperature range. If several drivers are used in a system, their
inputs and/or outputs may be combined and wired together
if their supply voltages are also common.

• 1 Amp output drive
• Load connected to ground
• Low input-output voltage differential
• + 60 volt positive transient protection
• -50 volt negative transient protection
• Automotive reverse battery protection
• Short circuit proof
• Internal thermal overload protection
• Unclamped output for fast decay times
• TTL, LSTTL, CMOS compatible input
• Plastic TO-220 package
• 100% electrical burn-in

Applications
•
•
•
•
•
•

Relays
Solenoids
Valves
Motors
Lamps
Heaters

Typical Application Circuit

SUPPLY
VOLTAGE

VIN

-1""

11
J L '-"; ~TyN;. D_":,_; ,;GNr-;~;. . .! t ~ II"" .~,,~~_~
5

INPUT

OUTPUT 2 100 nF

o-------.....::.j",,'" ""'" J,

TL/H/5271-1

FIGURE 1. Test and Application Circuit

Connection Diagram

!

TO·220 5 LEAD

5
WLTAGE . "
4 IN'"
GROUND
3 GROUND
2 OUTPUT VOLTAGE (VOUT)
1 SUPPLY VOLTAGE (Vee)

Ic:.J I

TL/H/5271-2

Front View
Order Number LM1921T
See NS Package Number T05A

5-160

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Operating Temperature Range

Internal Power Dissipation

Internally Limited

Input Voltage
Operating Range
Overvoltage Protection (100 ms)

Storage Temperature Range
Lead Temp. (Soldering, 10 seconds)

-40'Cto + 125'C

Maximum Junction Temperature

26V
-50Vto +60V

150'C
- 65'C to + 150'C
230'C

Electrical Characteristics (Vee = 12V, 10 = 500 mA, TJ = 25'C, VIN = 2V, unless otherwise specified.)
Parameter

Supply Voltage
Operational
Survival
Transient
Supply Current
VIN=O
VIN=2V

Input to Output
Voltage Drop

Conditions

Typ

100 ms, 1 % Duty Cycle

10=OmA
10=250 mA
10=500 mA
10=1A

0.6
6
285
575
1.3

10=500 mA
10=1A

0.5
1.0

Short Circuit Current

1.4

Tested Limits
(Note 1)

Design Limits
(Note 2)

Min

Max

Min

Max

4.75
-15
-50

26
60

6

24

1.5

0.8
1.0

Output Leakage Current
Input Voltage
Threshhold

VIN=O

Input Current

15

Overvoltage Shutdown

32
/ljc
/lca

Inductive Clamp
Output Voltage

VIN=O, 10= 100 mA

Fault Conditions
Output Current
Input Floating
Ground Floating
Reverse Voltage
Reverse Transient
Overvoltage
Supply Current

Pin 5 Open
Pin 3 & Pin 4 Open
Vee= -15V
Vee = -50V
Vee= +60V
Pin 1 & Pin 2 Short, No load

A
A

50

/-LA

0.8

2.0

V
V

26

36

2.0

6V:S:Vee:S: 24V

Thermal Resistance
junction-case
case-ambient

3.0

2.0

0.1
0.8
10

30

/-LA

0.1
0.1
-0.01
-100
0.01
10

V
'C/W
'C/W

3
50
-60

mA
mA
mA
mA
A
V
V

.75

1.3

V
Voe
V

10
350
700
1.5

6V:S:Vee:S: 24V

Units

-120

-45

V

50
50

/-LA
/-LA
mA
mA
mA
mA

-1
1
40

Note 1: Guaranteed and 100% production tested.
Note 2: Guaranteed, not necessarily 100% production tested. Not used to calculate outgoing AQL. Limits are for the temperature range of -40°CS:Tj:S: 150°C.

5-161

Typical Performance Characteristics
Output Voltage Drop

Device Operating Current

...~

=
w

:i!

o.B

!:;

0.6

5

0.4

=
>

::
:!'"

0.2

ii!
2!

r---

IOUT-50omA

I
r---

I

I~

II

o .. Io-i"'"

o

BO

40

120

o

160

JUNCTION TEMPERATURE(OC)
TL/H/S271-3

~
>

o.S

~

=
2l
~

0.4

'"

0.3

...
~'
2!

~

JL~ 5till

;;-

25

VIN= 2V

~
~

20

=
>
....
~
:0
=

i/

/

0.2

/

0.1

o 1.0'
o 100

200 300 400 SOD 600 700 BOD

lB

~I-

16

~f-

~

12

~
is

10

I I

4

2

-10

o

w

-

I~

I

NO HEAT SINK

....

o 10

20 30 40 50 60 70 Bo 90
AMBIENT TEMPERATURE (OC)
TL/H/5271-B

TL/H/5271-7

_1.50

r- - l -

~r--~J HjAT jINK_ l -

-5
0
ro ~
SUPPLY VOLTAGE (V)

HEATSINK

14

I

1I

IN~INI~E r- f-f-

-

Input Current vs,
Input Voltage
30

~

~ 20

!:i

5!
~
~
i!:

/

15

110

It:

~

ill
0

~
~

-~·ro

30

li 1.45 f-+-f--+--+--+-l

iii

-50 -25

10
15 20
25
INPUT VOLTAGE (V)

TLlH/5271-5

Threshold Voltage vs,
Supply Voltage

3D VCC-12V
VIN=2V
25

o

Maximum Power
Dissipation (TO-220)

1/

5

Input Current vs,
Junction Temperature

i

I
I

o

1D00

1/

10

TLlH/S271-6

i:l

0.5

20

15

OUTPUT CURRENT(mA)

:

'"
=

Output Voltage (VOUT)
3D

,/

,,

BOD

600

1.0

TLlH/5271-4

35

0.9
0.8
0.7
0.6

400

I

/

,,-

OUTPUT CURRENT (mA)

Output Voltage Drop

1.0

200

1.5

....
~

,,'

lOUT LooJ

g

....

j

-40

~

Peak Output Current (Vour)

400

E

25

50

1.40

I--t--t--+--f--t--l
VCC=26V

1.35
1.30

125°\

250C

_

1-,d.;ooJ.~~~~:t:::J.-l

"'!:.:.:" ':':::: :":'':':1:''-400C I-1.25 1--t--t--+-c'-T

1.20 L--'-_L--l.._"--'----'
10
15
20 25 30

75 100 125

JUNCTION TEMPERATURE (OC)
TLlH/S271-13

SUPPLY VOUAGE (V)

t -U
II

f--

VCc~4:SV --

I

2
INPUT VOLTAGE (V)

TL/H/5271-14

TLlH/5271-15

Equivalent Block Diagram

Vee

Veeo---~~-----------.----------------------------.-~
OVERVOLTAGE
SHUTDOWN

1.2V
REF.

CHIP
THERMAL
SHUTDOWN
OUTPUT

INPUT

TLlH/5271-12

FIGURE 1
5-162

Q
~

(')

C

::;

vee

en
(')

:::r
C'D

..n'
3

S»

VOUT

TL/H/5271-9

~~6~1I\I1

II

Application Hints
HIGH CURRENT OUTPUT
The 1 Amp output is fault protected against overvoltage. If
the supply voltage rises above approximately 30 volts, the
output will automatically shut down. This protects the inter·
nal circuitry and enables the IC to survive higher voltage
transients than would otherwise be expected. The 1921 will
survive transients and DC voltages up to 60 volts on the
supply. The output remains off during this time, independent
of the state of the input logic voltage. This protects the load.
The high current output is also protected against short cir·
cuits to either ground or supply voltage. Standard thermal
shutdown circuits are employed to protect the 1921 from
over heating.

FLYBACK RESPONSE
Since the 1921 is designed to drive inductive as well as any
other type of load, inductive kickback can be expected
whenever the output changes state from on to off (see
waveforms on Figure 1). The driver output was left un·
clamped since it is often desirable in many systems to
achieve a very rapid decay in the load current. In applica·
tions where this is not true, such as in Figure 2, a simple
external diode clamp will suffice. In this application, the inte·
grated current in the inductive load is controlled by varying
the duty cycle of the input to the driver IC. This technique
achieves response characteristics that are desirable for cer·
tain automotive transmission solenoids, for example.
For applications requiring a rapid controlled decay in the
solenoid current, such as fuel injector drivers, an external
zener and diode can be used as in Figure 3. The voltage
rating of the zener should be such that it breaks down be·
fore the output of the LM1921. The minimum output break·
down voltage of the IC output is rated at -57 volts with
respect to the supply voltage. Thus, on a 12 volt supply, the

combined zener and diode breakdown should be less than
45 volts.
The LM1921 can be used alone as a simple relay or sole·
noid driver where a rapid decay of the load current is de·
sired, but the exact rate of decay is not critical to the sys·
tem. If the output is unclamped as in Figure 1, and the load
is inductive enough, the negative flyback transient will cause
the output of the IC to breakdown and behave similarly to a
zener clamp. Relying upon the IC breakdown is practical,
and will not damage or degrade the IC in any way. There are
two considerations that must be accounted for when the
driver is operated in this mode. The IC breakdown voltage is
process and lot dependent. Clamp voltages ranging from
- 60 to -120 volts (with respect to the supply voltage) will
be encountered over time on different devices. This is not at
all critical in most applications. An important consideration,
however, is the additional heat dissipated in the IC as a
result. This must be added to normal device dissipation
when considering junction temperatures and heat sinking
requirements. Worst case for the additional dissipation can
be approximated as:
Additional PD
where:

=

12 x Lx f (Watts)

I = peak solenoid current (Amps)
L

= solenoid inductance (Henries)

f = maximum frequency input signal (Hz)
For solenoids where the inductance is less than ten milli·
henries, the additional power dissipation can be ignored.
Overshoot, undershoot, and ringing can occur on certain
loads. The simple solution is to lower the Q of the load by
the addition of a resistor in parallel or series with the load. A
value that draws one tenth of the current or DC voltage of
the load is usually sufficient.

Output

Output

~~~~~i
(PIN 21

----.....-----.
LOAO ~III
~I

~I

.il> lN4001

.i~

1N4001

L

)~ 16V

TLiH/5271-10

TLiH/5271-11

FIGURE 2. Diode Clamp

FIGURE 3
Zener clamp for rapid controlled current decay

5·164

~NatiOnal

PRELIMINARY

: Semiconductor
Corporation

lM1946 Over/Under Current limit Diagnostic Circuit
General Description

Features

The LM1946 provides the industrial or automotive system
designer with over or under current limit detection superior
to that of ordinary transistor or comparator-based circuits.
Applications include lamp fault detection, motor stall detection, and power supply bus monitoring.

Five independent comparators
Capable of 30 mA per output
II Low power drain
II User set input threshold voltages
II Reverse battery protection
II 60V load dump protection on supply and all inputs
II Input common mode range exceeds Vee
II Short circuit protection
II Thermal overload protection
II Prove-out test pin
II Available in plastic DIP and SO packages

Each of the five independent comparators can be used to
monitor a separate load as either an over current or under
current limit detector. Two comparators monitoring a single
load can function as a current window monitor.
Current is sensed by monitoring the voltage drop across the
wiring harness, pc board trace, or external sense resistor
that feeds the load.
Provisions for compensating the user set limits for wiring
harness resistance variations over temperature and supply
voltage variations are also available.
When a limit is reached in one of the comparators, it turns
on its output which can drive an external LED or microprocessor.

III
III

One side of the load can be grounded (not possible with
ordinary comparator designs), which is important for automotive systems.

Typical Application Circuit-Lamp Fault Detector (lL>

1A)

Vee

OFF FOR ILAMP > 1AMP
ON FOR ILAMP < 1AMP

,Ise\ -

R5

,

30K

L...-1'T'""-"ITEST
-= GND

'I/IIIr-4

FIGURE 1

5-165

TL/H/8707-2

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (Vee and Input Pins)
Survival Voltage (T S; 100 ms)
Operational Voltage

Internal Power Dissipation (Note 1)

Internally Limited
Continuous

Output Short Circuit to Ground or Vee
Operating Temperature Range (TA)

-40'Cto +85'C
+ 150'C

Maximum Junction Temperature

-50Vto +60V
26V

Storage Temperature Range

- 65'C to + 150'C

Lead Temperature (Soldering, 10 sec.)

Electrical Characteristics 9V s; Vee s; 16V, Iset =
Parameter

Conditions
All Outputs "Off"

Reference Voltage

Iraf= 10p.A

Reference Voltage
Line Regulation

9V

Iset Voltage

Iset = 20 p.A

Input Offset Voltage

At Output Switch Point. Va = 2V
9V S; VeM S; 16V

Input Offset Current

IIN(+) - IIN(-), 9V

Input Bias Current

S;

Vee

S;

20 p.A, Tj = 25'C (unless otherwise specified)

Min

Quiescent Current

5.8
16V, Iraf = 10 p.A
1.20

IIN(+) orIIN(-), 9V

S;
S;

VeM
VeM

S;
S;

16V
16V

Input Common Mode
Voltage Range

18.00

Typ

Max

Units

1.40

3.00

m~c

6.4

7.0

Vdc

±5

±50

mVdc

1.40

1.60

Vdc

±1.0

±5.0

mVdc

±0.10

±1.00

P.Ade

20.00

22.00

P.Ade

26.0

Vde

4.00

Maximum Positive
Input Transient

Either Input. T

100 ms

Maximum Negative
Input Transient

Either Input. T :;;; 100 ms

Output Saturation
Voltage

10 = 2 mA, 5V

Output Short Circuit
Current

Va = OVde, Comparator "ON"

Output Leakage Current

Va = OVde. Comparator "Off"

Test Threshold
Voltage

At Switch Point on Any Output
Va = 2V (Note 2)

S;

S;

10 = 10 mA, 5V

Vee

S;

S;

Vee

60

70

V

-50

-60

V

16V

S;

16V
30

0.80

Test Threshold
Current

0.80

1.00

Vdc

1.00

1.20

Vde

45

120.0

mAde

0.01

1.00

P.Ade

1.25

2.00

Vde

0.2

Note 1: Thermal resistance from iunction to ambient is typically 53'C/W for LM1946 (board mounting).
Note 2: The test pin is an active high input, i.e. all five will be forced high when this pin is driven high.

5·166

+ 230'C

p.~c

riii:

....

Connection
Diagram
I

(Q
.j:o.
(JI

LM1946

+

20

In 1

+
In 2

19
4

+

18

In 3

OUTPUT 1

OUTPUT 2

OUTPUT 3
VCC
VREF

ISET
GROUND

+

13

In 4

+
In 5

12
10
11

OUTPUT 4

OUTPUT 5
TEST/RESET
TL/H/B707-20

Order Number LM1946N
See NS Package Number N20A

Typical Test Circuit
5VSVcc:S: 16V

OUTPUT
SECTION

VOUT

REFERENCE
SECTION

VREF (5V)

TL/H/B707 -23

Simplified Comparator Schematic

TL/H/B707-24

5-167

Typical Performance Characteristics

(Continued)

Quiescent Current
vsVee

Vsat vs 10

Quiescent Current
vsVee

5

4

1.6

:('

OB

§

_.-

OA

o
o

Ir-:-

E

v

..- ..-

1.2

a
§

I-

I
II

-2

!!l
:5

-4

'"

-6
10

15

20

25

10

loul(mA)

14

-so

16

-30

Vcc (volls)

Peak 10 vs Vee
2.0

50

-

1.6

_f-

1.2

30

DB

20

OA

10

30

50

Vref vs Temperature
7A

-....

i'oo.

f-~

-10

VCC (volls)

Vset vs Temperature

60

40

12

7/J

....

.,,-

6.6

/'

6.2

~

i-"'"

58

10

0
10

12

14

-40

16

40

Vcc (volls)

-

-- ---

j

:;

o
-40

60

120

R4=570K
VCC=12V

160

R3=510K
R4= 1.1M
Vcc=12V

40

30

30

20

20

10

10

-

o
-40

160

120

Iset vs Temperature

0
40

80

50
R3=oo

40

10

40

TEMP(OC)

Iset vs Temperature

40

20

-40

160

50

R3 = 270K
R4=oo

30

120

TEMP (OC)

Iset vs Temperature
50

80

40

TEMP(OC)

80

120

-40

160

40

60

120

160

TEMP (OC)

TEMP(OC)

Test Threshold

Common Mode Negative Limit
4!J

1.6

<:.
50

~

1A
1.2
1/J

~

-- -

:E
~

;:i
§!

,.g

3.6

2B

~

::E
::E

8

DB

I--"""

3.2

..-

./

,./

2A

2.0
40

60

120

160

-40

40

80

120

160

TEMP(OC)

TEMP(OC)

TLlHI8707-4

5-168

r-

s:
......

Application Hints
THEORY OF OPERATION: UNDER-CURRENT LIMIT
DETECTOR

10 mV threshold would alert the system only if both bulbs
failed). Yet a fixed threshold of 75 mV may not work if the
nominal 100 mV sense voltage can vary 3:1 due to the factors mentioned earlier. What is required is a comparator with
a threshold-detecting voltage that tracks the nominal sense
voltage as battery line and ambient temperature change.
Thus, while the sense voltage may nominally be anywhere
from 50 to 150 mY, the threshold voltage will always be
roughly 75% of it, or 37 mV to 112 mY, and will detect the
failure of either of two bulbs.

.....- - +

The LM1946 integrated circuit contains five comparators especially designed for lamp monitoring requirements. Since
all lamps in a system share the same battery voltage and
ambient temperature, accommodations for these variations
need to be made only once at the IC, and each threshold of
the five comparators then tracks these variations.

LOAD

TLlH/B707-6

Lamp Fault Detector

FIGURE 3. Equivalent Automotive Lamp Circuit
The diagram of Figure 3 represents the typical lamp circuit
found in most automobiles. Switch S1 represents a dashboard switch, discrete power device, relay and/or flasher
circuit used for turn signals. Sense resistor Rs can be an
actual circuit component (such as a 0.1 n 1W carbon resistor) or it can represent the resistance of some or all of the
wiring harness. The load, represented here as a single bulb,
can just as easily be two or more bulbs in parallel, such as
front and rear parking lights, or left and right highbeams, etc.

SETTING THE COMPARATOR THRESHOLD VOLTAGE
The comparator threshold voltage at which the comparator
output changes state is user-set in order to accommodate
the many possible system designs. The input bias currents
are purposely high to accomplish this, and are each equal to
the user-set current into the Iset pin (more on this later).
Typically around 20 p.A, the effect of this across the sense
resistor, Rs compared to a typical load measured in amps is
negligible and can be ignored. However, when resistors R1
and R2 (Figure 5) are added to the circuit a shift in the
threshold voltage is effected. This occurs since each input
has been affected by dilierent IR drops. The LM1946 comparator behaves like any other comparator in that the output
switches when the input voltage at the IC pins is zero millivolts (ignoring offset voltage for the moment). If the output
therefore has just switched states due to just the right
threshold voltage across the sense resistor, then the sum of
voltages around the resistor loop should equal zero:

One of the easiest methods to electronically monitor proper
bulb operation is to sense the voltage developed across Rs
by the bulb current IL. If a fault occurs, due to an open bulb
filament, the load current and sense voltage, Vs, drop to
zero (or to half their former values in the case of two bulbs
wired in parallel). A comparator type circuit can then monitor
this sense voltage, and alert the system or system user (e.g.
power an LED) if this sense voltage drops below a predetermined level (defined as the threshold voltage).
Typical sense voltages range from tens to hundreds of millivolts. Not only does this sense voltage vary nonlinearly with
the battery voltage. it may vary significantly with ambient
temperature depending on the temperature coefficient (TC)
of the sense resistor or wiring harness. Since these nonlinear characteristics can vary from system to system, and
sometimes even within a single system, provisions must be
made to accommodate them. There are two general methodologies to accomplish this.
The first method uses only one bulb per monitoring circuit. A
sense resistor is selected to give 50-100 mV of sense voltage in an operational circuit, and a comparator threshold
detecting voltage of approximately 10 mV is set. Even if
component tolerances, battery line variations, and temperature coefficients cause the sense voltage to vary 3:1 or
more, circuit operation will not be affected.
The second method must be used if two or more bulbs are
wired in parallel and it is necessary to detect if any single
lamp fails. This is often desirable as it reduces the number
of comparators and displays and system cost by at least a
factor of two. In this case, the sense voltage will drop by
only half (or less) of it's original value. For example, a nominal 100 mV drop across the sense resistor will drop to
50 mV if one of two bulbs fail. Therefore, a threshold detection voltage between 50 and 100 mV is required (since a

51

COMPARATOR
OUTPUT

LOAD

TL/H/B707-9

Vthrshld

Vthrshld

Iset (R 1 - R2)

FIGURE 4. Input Bias Current
+ Iset. R2 - Voffset - Iset. R1 = 0

Assuming Voliset <:: Vthrshld:
Vthrshld = Iset. R1 - Iset. R2
Vthrshld = Iset (R1 - R2)

5-169

~

CO
~

en

U)

"0:1'

....

en
:E
...J

r---------------------------------------------------------------------------------,

Application Hints (Continued)
VCC(PIN 17)

Typical values are:

R3

R2 = 1.2k ±5%
Iset = 20 ",A
Vthrshld

=

@

20 ",A (6.2k - 1.2k)

=

~

100 mV

~

Iset(P~
Iset = Vee - 1.2
R3
Isat

The current through a typical automotive lamp, whether a
headlight or dashboard illumination lamp, will vary as battery
voltage changes. The change, however, is nonlinear. Doubling the battery voltage does not double the lamp current.

r--r-,--;--.-....,--;---r--r--;

V
I-f--t-+--+-+-+A=---t-l

v-

V
I/
I-J1/H--+-+-+-f-l-lf-f--

OL-L-~~~~~-L-L_

o

2

4

6

8 10 12 14 16 18
VBAT(V)
TUH/8707-21

FIGURE 5
This occurs since a higher voltage will heat the filament
more, increaSing its resistance and allowing less current to
flow than expected. Figure 6 shows this effect. A best fit
straight line over the normal battery range of 9V to 16V for
this particular example can be given by:
IL (Amps) = 0.62

( 1

1 )
As + R4

If the sense resistors used in a system are perfect components with no temperature coefficient, then the compensation to be subsequenty detailed here is unnecessary. However, resistors of the very small values usually required in a
lamp outage system are sometimes difficult or expensive to
acquire. A convenient alternative is the wiring harness, a
length of wire, or even a trace on a printed circuit board. All
of these are of copper material and therefore can vary by as
much as 3900 ppml"C. The LM1946 has been deSigned to
accommodate a wide range of temperature compensation
techniques. If the Iset current is designed to increase or
decrease with temperature, nearly any temperature coefficient can be produced in the threshold voltage of the four
input pairs.

0.75 f----1V~-+--I--+--!--t-+---1

0.25

Vra!

Vee

= R3 + R4 -1.2

COMPENSATING FOR AMBIENT
TEMPERATURE VARIATION

1.25 1--f--f--t-/-t-V7"F--t--t--t--I

0.50

Vraf - 1.2
R4

FIGURE 6

COMPENSATING FOR BATTERY VOLTAGE

1.75

+

Thus, in actual use, the LM1946/1947 threshold voltages
should track the variations in bulb current with respect to
battery voltage. To accomplish this, Iset should have a component that varies with the battery. As shown in the LM1946
circuit schematic of Figure 18, the Iset pin is two diode
drops above ground, or appoximately 1.2V. A resistor from
this pin to the 6.5V reference sets the fixed component of
Iset; a resistor to the battery line sets the variable component. Thus, the best fit straight line in Rgure 5 can be realized exactly with only two resistors. The result is shown in
Figure 6, giving a nominal Iset of 20 ",A that tracks the bulb
current as supply varies from 9V to 16V. The graph of Figure
7 shows the final result comparing a typical sense voltage
across Rs with the comparator threshold voltage as the
supply varies.

R1 and R2 are necessary for another reason. These resistors protect the input terminals of the IC from the many
transients in an automobile found on the battery line, some
of which can exceed a thousand volts for a few microseconds. A minimum value of approximately 1 kO is therefore
recommended.

1.50

15)
TLlH/8707 -10

It's also important that the output of the comparator be in
the "off" state when the inputs are taken to ground, i.e. 51
is opened and the light is turned "off". The input section of
LM1946 has been designed to turn "off" when the inputs
are grounded and therefore not deliver an erroneous bulb
out indication. The comparator is only activated when the
inputs are above ground by at least 3V.

1.00

R4
470K

~ 1.1M

25·C

For values of sense voltages greater than 100 mV, the comparator output is off (low). Sense voltages less than 100 mV
turn the output on (high).

~

Vr.jCPIN 16)

~

R1 = 6.2k ±5%

240

I

160

+ 0.069 • Vbattery

Ir1f'

120
80

-

I-

I

VSENSE- I-(lL oRs)

200

t-

~

r- f-

f-

~

VTHRESHOLD-j(lSET o[RI + R2])

40
0
9 10 11 12 13 14 15 16 17
VBAT(V)
TL/H/8707-22

FIGURE 7

5-170

Application Hints (Continued)
One solution is to use a low cost thermistor in conjunction
with some low-TC resistors (see Figure 8).

approximate staight line TC generated. See Figure 9 for a
graphic representation of the ideal calculated values of Iset
and the actual measured values generated. Notice that
there is very close agreement between the two graphs. The
circuit actaully creates an S-shaped curve around the ideal.
The low-cost lhermistor is available from Keystone and is
listed as follows: RL2008-52.3K-155-D1.

There are three fixed resistors and one thermistor. This is
an NTC thermistor, since it has a negative temperature coefficient. This is what is required in order to have Iset increase as the temperature rises. The data sheet with the
thermistor described a number of ways to establish different
final TC's. The thermistor itself has a very large TC which is
somewhat difficult to describe mathematically. But, if it is
used with some other fixed resistors, such as Rmin and
Rmax, definite end point limits can be established and an

OVER-CURRENT LIMIT DETECTOR
Other applications include an over-current detector, as
shown in Figure 10. The load represented here can be either a single component or an entire system. Resistors R3
Vre~6.5V)

-c

Rmin.

430K
R3

101M

Rmax

T

270K
~I

Thermistor

Ire! ~

Keystone:

RL200a·S2.3K-155-Dl
100k@ 2S'C

Iset~ A.
Iset PIN( 1.2V)
TL/H/8707-11

FIGURE 8. Thermistor/Resistor Network
30

I'\ AbA~ MJSURE1O-

28
26

~~

24

<'
.3
]

22

CALCULAj~O

20 3900ppm °C
18
16
14

~

./

~

P'
~

12
-60 -40 -20

0

20

40

60

80 100 120

TEMPERATURE(OC)
TLlH/8707-12

FIGURE 9. Iset vs Temperature with Figure 8 Circuit

5-171

Application Hints (Continued)
Vee

,Isot ,

VTHRSHLD =Isot(Rl-R2)

R5
30K

. . ._,.._...1I

:END

'IN'v--4

TEST

TL/H/B707-7

FIGURE 10. Using the LM1946 as an Over·Current Limit Detector

and R4 again allow the system designer to tailor the thresh·
old limit to the V II characteristics of each particular system.
The input threshold voltage is determined by, and directly
proportional to, Iset into pin 20. R3, from the on·chip refer·
ence voltage, provides a current and threshold that is inde·
pendent of the supply voltage, Vee. R4 provides a current
directly proportional to supply. These resistors allow thresh·
olds to be either independent of, or directly proportional to
supply voltage, or anything in between. For example, the
values in Figure 10 are tailored to match the VII characteris·
tics of the bulb filament used in earlier examples. However,
if the load had purely resistive characteristics, Iset and the
threshold would be set with R4 only, eliminating R3. Like·
wise, if the load current was independent of supply, such as
in many systems powered by a voltage regulator, Iset would
be better set by R3 only, eliminating R4. Further details on
this and how to handle variations with ambient temperature
with resistor and thermistor combinations are discussed in
detail in previous sections. Compensation for temperature
variations, however, is rarely necessary since short circuit or
over·current values are usually much greater than the nomi·
nal value. For example, if the load in Figure 10 represented
a DC motor, the circuit could be used to detect the motor
stall condition. Stall current through the sense resistor, Rs,
would typically be five times the nominal running current. By
setting the threshold at three times the nominal current val·
ue, enough margin exists that minor variations due to tem·
perature can be ignored. The variation in stall current due to
battery or supply voltage can be significant, however. Being
approximately proportional, Iset would best be set in this
case by R4 only.

are approximately 3A and 1A respectively. The outputs can
be kept separate or wired·or, as shown, to a single output
load as a simple out·of·bounds detector.
Vee

Vee

Vthrshld·lo
Vthrohld·hi

~
~

loet. (Rl0 - Rll)
loet. (R13 - R12)

R5
0.111

R14

lK

TUH/B707-B

FIGURE 11. Current Limit Window Detector

COMPARATOR INPUT STAGE
The LM1946 IC consists of five specially designed compara·
tor input circuits to monitor the IR drop across the wiring
harness or the sense resistor between the battery and the
light bulb. These comparators have been designed to ac·
commodate a wide range of input signals without damage to
the IC or the load circuitry. The inputs can easily withstand a
common mode voltage above the positive supply since the
inputs are the emitters of two matched PNP devices (see
Figure 12). This is vital in a system which must operate in
the conditions present under the hood of an automobile.
The inputs can also survive when taken well below ground.
If a negative voltage is present at the inputs of the compara·
tor, the two emitter·base PNP junctions become reverse bi·
ased and block any current flow in or out of the device.

WINDOW DETECTOR

The availability of more than one comparator per IC allows
many other applications. One is the current sense window
detector. Many times it is useful to know that a certain cur·
rent is within both an upper and lower limit. USing two of the
LM1946 comparators and the circuit of Figure 11 will ac·
complish this. In this particular case, high and low limits

5·172

Application Hints (Continued)
-INPUT

+INPUT
INDICATOR
LAMP

TL/H/B707 -14

FIGURE 14
TESTIRESET PIN
The test pin is a high impedance logic input. Forcing this pin
high (:;;' 2V) forces all four comparator outputs on. This
is used to test the indicator LED display (or other output
load). The usual application circuit connects this pin to the
ignition crank line. During engine crank, therefore, the
LM1946 output display will light, similar to the usual dashboard indicators. The test pin was deSigned to operate with
the usual transient voltages found on the crank line as long
as a limiting resistor (e.g. 30k) separates them (Figure 1).

TL/H/8707 -13

FIGURE 12. Comparator Input Stage
THE OUTPUT SECTION
The output section of the LM1946 is different from most
automotive comparators as it employs high beta proprietary
PNP transistors which are very rugged and capable of higher output currents. Each of the four comparator outputs is
capable of about 25 mA of drive and are internally current
limited and protected against supply overvoltage. The
LM1946 is therefore capable of driving LED's directly and
larger bulbs via an external grounded base NPN (see Figures 13 and 14). The outputs can also be wired·or together
without harm.
For use in systems with a microprocessor flag instead of a
dashboard indicator, the LM1946 can be powered by a standard 5V logiC supply. This prevents the LM1946 output from
swinging above the microprocessor supply which might
cause latch problems. Since the input common mode range
is independent of supply, the inputs can still operate at any
level up to 26V. Since the outputs can source current only,
pull-down resistors as in Figure 15 are required, their value
depending on the input drive requirements of the particular
microprocessor used.

The test pin will also reset any comparator outputs that
have been latched or delayed in the high state (see next
section). This occurs on the falling edge of the test input
signal. The minimum pulse width to guarantee reset is dependent on largest capacitor connected to any control pin:
Minimum pulse width (ms) ;::: 0.01 + 1.5. Cl (J.LF)
Vcc(5V)

TL/H/B707 -15

FIGURE 15

TlIH/8707-19

FIGURE 13

5-173

U)

00:1'

en
,...
:::!E

...J

r-----------------------------------------------------------------------------------------~

Application Hints (Continued)
For extremely severe cases, additional filter stages can be
cascaded at the inputs (see Figure 17). Since the input bias
currents of the comparator are equal at the input threshold
level, the voltage drops across the 1k resistors cancel and
do not affect the DC operation of the circuit (ignoring resistor match tolerance and los). If an application circuit is noisy
enough to require such an elaborate filter, then ferrite
beads, shown here as L 1 and L2, will also probably help.

MORE NOISE FILTERING
The current flowing through the sense resistor and certain
loads can sometimes be very noisy, particularly when the
load is a DC motor, or switching supply. Large amounts of
noise on the supply line can also cause problems when
threshold voltages are set to very small values. In these
cases, while the average current level may remain well below the threshold trip pOint, noise peaks may exceed it. A
LED display could then flicker or appear dimly lit, or excessive software routines and processor time may be required
for a ,...p to disregard such noise. Noise transients can be
particularly annoying in application circuits employing the
output latch, as a sufficient noise spike will erroneously trip
the output and require resetting the circuit. While a capacitor
on the control pin can be effective for the infrequent noise
transient (see "Control Pin" section) such as during powerup, it is much less effective for suppressing other types of
noise. This occurs because C1 charges and discharges at
different rates, typically a 50:1 ratio. A regularly occurring
noise pulse would eventually "pump up" C1 to 1.2V and
trigger the output. Often such noise must be filtered directly
at the inputs, using the input resistors R 1 and R2 and a
capacitor. Care must be taken, however, that such a filter
will not cause an erroneous output state upon power-up or
whenever switch S1 is closed. The most effective general
methodology to achieve this is to split the resistor in the
positive input lead into two resistor values and connect a
capacitor from here to the negative input. For example, the
1.2k resistor R2 of Figure 1 could be replaced with 3.9k and
1.2k resistors as shown in Figure 168 (R1 increasing from
6.2k to 10k to compensate). The value of capacitor C2 depends upon the degree of filtering required, the amount of
noise present, and the response times desired. The choice
of values for the new resistors is almost arbitrary. Generally
the larger value is attached to the sense resistor for belter
decoupling. The smaller value must be large enough so that
the DC voltage across it upon power-up exceeds the maximum offset voltage expected of the comparator (i.e.
Iset*R2b> 5.0mV). It is this requirement that guarantees
that the output will not be in an erroneous high state upon
power-up or whenever S1 is closed. (Should this feature be
unnecessary to a particular application circuit, the methodology described can be replaced with a simple capacitor
across the comparator input pins).

Rl

"~~
R2a
3.9K

R2b
1.2K

TL/H/8707 -16

a. Open-Circuit Detector
Rla
5.1K

Rlb
lK

R5~

O.lA~
R2
lK
TL/H/8707 -17

b. Short-Circuit Detector
FIGURE 16. Input Noise Filters for
Various Application Circuits

TLlH/8707 -18

FIGURE 17. Additional Noise Filters

5-174

Vee
-0
17

0
:::;"
n
C

;::;:

en
n

:::T
CD

3SI)

....
n"

r

~

II Li?a26

~
.....
01

J:i 11-==

7030

t

7,37

~~

VOUT
.

.....
0

:l

-<

16

:17

PROVE OUT C>---'\I\I'\r-.
TEST PIN 11

GND
14
TL/H/8707-3

FIGURE 18

9f76~W'

iii

CD
"0:1'
CD

....

:E
...J

NatiOnal

~ Semiconductor
Corporation

LM1949 Injector Drive Controller
General Description

Features

The LM1949 linear integrated circuit serves as an excellent
control of fuel injector drive circuitry in modern automotive
systems. The IC is designed to control an external power
NPN Darlington transistor that drives the high current injector solenoid. The current required to open a solenoid is several times greater than the current necessary to merely hold
it open; therefore, the LM1949, by directly sensing the actual solenoid current, initially saturates the driver until the
"peak" injector current is four times that of the idle or "holding" current (Figure 3-Figure 7). This guarantees opening of
the injector. The current is then automatically reduced to the
sufficient holding level for the duration of the input pulse. In
this way, the total power consumed by the system is dramatically reduced. Also, a higher degree of correlation of
fuel to the input voltage pulse (or duty cycle) is achieved,
since opening and closing delays of the solenoid will be
reduced.
Normally powered from a 5V ± 10% supply, the IC is typically operable over the entire temperature range (- 55'C to
+ 125'C ambient) with supplies as low as 3 volts. This is
particularly useful under "cold crank" conditions when the
battery voltage may drop low enough to deregulate the 5volt power supply.
The LM1949 is available in the plastic miniDIP, (contact factory for other package options).

•
•
•
•
•
•
•
•
•
•
•
•
•

Low voltage supply (3V-5.5V)
22 mA output drive current
No RFI radiation
Adaptable to all injector current levels
Highly accurate operation
TTL/CMOS compatible input logic levels
Short circuit protection
High impedance input
Externally set holding current, IH
Internally set peak current (4 x IH)
Externally set time-out
Can be modified for full switching operation
Available in plastic 8-pin miniDIP

Applications
•
•
•
•
•

Fuel injection
Throttle body injection
Solenoid controls
Air and fluid valves
DC motor drives

Typical Application Circuit
0-

I
I
I

I
I
I

+-'1-----0 Vcc=5V

RS
O.l.n

2W

TLiH/S062-1

FIGURE 1_ Typical Application and Test Circuit
Order Number LM1949N
See NS Package Number NOSE

5-176

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
8V

Power Dissipation (Note 1)

1235 mW

Electrical Characteristics
Symbol
lee

Input Voltage Range
Operating Temperature Range
Storage Temperature Range

-0.3V to Vee
-40·C to + 125·C
-65·C to + 150·C

Junction Temperature
Lead Temp. (Soldering 10 sec.)

150·C
260·C

(Vee = 5.5V. VIN = 2.4V. Tj = 25·C. Figure 1. unless otherwise specified.)

Parameter
Supply Current
Off
Peak
Hold

Typ

Max

Units

VIN = OV
Pin8 = OV
Pin 8 Open

11
28
16

23
54
26

mA
mA
mA

1.4
1.2

2.4
1.6

V
V

Conditions

VOH

Input On Level

Vee = 5.5V
Vee = 3.0V

VOL

Input Off Level

Vee = 5.5V
Vee = 3.0V

Is

Input Current

lop

Output Current
Peak
Hold

Pin8 = OV
Pin 8 Open

Vs

Output Saturation Voltage

10 mAo VIN = OV

Vp
VH

Sense Input
Peak Threshold
Hold Reference

Vee = 4.75V

t

Time-out. t

t+RTCT

Min

1.0
0.7

1.35
1.15

-25

3

-10
-1.5

-22
-5

V
V
+25

",A
mA
mA

0.2

0.4

V

350
88

386
94

415
102

mV
mV

90

100

110

%

NOTE 1: For operation in ambient temperatures above 25°C, the device must be derated based on a 150°C maximum junction temperature and a thermal
resistance of 10QoC/W junction to ambient.

Typical Circuit Waveforms
BATTERY
V'An

VOLTAGE
IVI

15V _ _ _-::':'=-::':'=--:=~--,
IOV
NORMAL BATTERY VOLTAGE
"COLO CRANK" OR LOW BATTERY VOLTAGE
5V

I

OV
INPUT
PIN I

VOLTAGE
IVI

5V
Ov--.J

SENSE INPUT
VOLTAGEIVI
PIN 4

TIMER
PIN B

VOLTAGE
IVI

V,

OIV~~WGCET~~

15V
OV

4A
INJECTOR
CURRENT IAI

2A
OA

TL/H/5062-2

5-177

LM1949
tJ)
(')
~

.. ~

Vee

RI8

R7~

CD

3D)

043

rtitj

'!:

iil

( ;'

l--+--I-r 046

o

04

05

044 I--'

~

I

iii'

cc
Dl
3

~ R32

RI

~.rd
I~

tu--tt

TIMER

-

R3

R5

R2

06

08

03

O~

.----.
R33

RI9

R36

om~

IN

28
......0

"

I

t~

R22

Rill
R7

~R16

tl
~

~059

Ol~

tl

~21

01~01~

R23

041

R30

R24
825

R26

1

I 031

.

COMP

J
k

R27

047

R21

R9

834

R8

H

2

~r

GND

1....

SENSE
TL/H/50B2-3

FIGURE 2. LM1949 CIrcuit

Typical Performance Characteristics
Quiescent Current vs
Supply Voltage
12
VIN' OV
TI' 25'C

_ 30
«
~ 25
~

Supply Current vs
Supply Voltage

I

VIN' 2.4V
T,=25'C

PE~

g§ 20

./

...- .,/

/

a

~ 15

'"
~

10

~

'" 0

Input Voltage Thresholds
vs Supply Voltage
3.0

>400

T,'25'C

ON

~ 1.5

,.

~1.0
==

.::::; roFF
~

~

o

E
~

1.03

~

0:

:i! 1.00

./V

;:::

.99

0:

I

c

Z

.97

......

>

Vce = 5.5V

V~c ,13.0V
I I

~

VCC

510
c

5

o

J.
VCC

~

=3.0V

-

lVcc = 5.5V H~LO 0;;;::::

=3.0V 1 I

·60 ·30 0 30 60 90 120 150
JUNCTION TEMPERATURE I'CI

4
SUPPLY VOLTAGE IV)

l"'-

-

B
5 15r-~-+--1r-~~~~

17:--l--~~I:::-""k::+--11--i

'"

~loF;=N~~~
g

·60 ·30 0 30 60 90 120 150
JUNCTION TEMPERATURE I'CI

30 60 90 120 150
JUNCTION TEMPERATURE I'CI

Input Voltage Thresholds
vs Junction Temperature

Sense Input Peak Voltage
vs Junction Temperature

3.5

~2.5

=::::'AK

o

Quiescent Supply Current
vs Junction Temperature
So
~ 25
20

>

~3.0

~25

'"

VIN= OV

~

35

~ 15

80

.. 30

'" 0
'"

.. 30

20

90

35.-.-.-~-r-r~~

m

o

\

95

...~

..

o

10

Output Current vs
Junction Temperature

.

.......

~ 85

iil

I

TI =25 'C

is
== 100

'"
'"
~

!!

a

SUPPLY VOLTAGE IV)

i

I

......... r-....

Quiescent Supply Current
vs Junction Temperature

a:

--

105

14

~ 1.0 1

.98

,-

~

375

cc
.s. 12

TI=25'C

~

~

'i 110

TI=25'e

SUPPLY VOLTAGE (VI

1.02

~

o

!!

Normalized Timer Function
vs Supply Voltage

HOLO

~

Sense Input Hold Voltage
vs Supply Voltage

=
...

2 3
4
5
SUPPLY VOLTAGE IV)

I

~ 10

Sense Input Peak Voltage
vs Supply Voltage

390

~370

o

PEAK- I--

20
~ 15

01234567
SUPPLY VOLTAGE IVI

c

~

~

2
3
4
5
SUPPLY VOLTAGE (VI

is 385

..

~ 25

c

~380

~ 0.5

TI'25'e
E

I

o

~ 395

; 2.0

!!

..
i

So

~2,5

35
.. 30

~

1/ ~

fii

3
4
5
SUPPLY VOLTAGE IV)

-

HOLJ

:;

o
o

a

I

I

/

Output Current vs
Supply Voltage

~2.0

~ 395

!

.1

~C'5.5V

ON

~1.5 ~ON

~
§! 1.0

...

405

:400

I--

OFF

OFF
Vec = 3.0V

=

39

0-"';;:: ~

...

.......

;375

~O.5

~370

o
·60 ·30 0 30 60 90 120 150
JUNCTION TEMPERATURE I'CI

......

~ VCC ' 3.0V
'" 3BO I-- Vec '5.5~ ~
~
"
,
~

... 385

, I'-....
r---.

·60 ·30 0 30 60 90 120 150
JUNCTION TEMPERATURE I'C)
TLiH/S062-4

5-179

en
""it
en
:E

r------------------------------------------------------------------------------------------,

-

Typical Performance Characteristics

(Continued)

....I

Sense Input Hold Voltage
vs Junction Temperature

!=:

I I5

r--.---,--r--.---,--,--,

"0 \--\--\--I\--I\--\--f----l

f--t--tI--+--+I--+-+----1
~:- 100
i
105

I

=

!

I

VCC- 55V

:

~ 95f=~~~~~~~;:j
~ 90 f--tl--+,-vrc -tOY ~
~

85

I

I

80L-L-~-L~~L-L-~

LM1949N Junction
Temperature Rise Above
Ambient vs Supply Voltage

Normalized Timer Function
vs Junction Temperature
~ 1.04'-'--'--1'--:'--1r-,--,

i

1.03 f----,Ic---,--t----i-+--+--j

iii

>=

1

~ '.02f---!f-"':-+--+-+-~

i

1.01 f-.....-"VC-C---=5'"".5::-V-~t....,--::.......-!

>= I.OOf--~"""'=~=-"'-c--l
ffi

~

I Vcc

30V i -"--~~~---j

.99t=±;;:;.....

:i''''-

I

i I

·60 ·30 0 30 60 90 120
JUNCTION TEMPERATURE I CI

t--t---+---1f-+--t--t--t

f-+-+-IL-+--+-+--I

'" :on·'

0»1

t;~8f-+-+-Ir--+--+-+--I

"'<
=>w

"">
",0

"""
"'w
... <

6 I-- _90% DUTY"...L+71-----i
'"

4

I CYC~E....

~
1/ """iO% DUTY

-",

~98
l--...ll----,-i---LI-,I----,-I---LI-'
.97-

·60 ·30 0 30 60 90 120 150
JUNCTION TEMPERATURE i'C1

12

~ ~ 10

ISO

~a:

2

.~
CYCLE
O'--"'-...J...-"----'__"'-...J...-I

o

I

2 3 4 5
SUPPLY VOLTAGE IVI
TLiH/S062-S

Application Hints
The injector driver integrated circuits were designed to be
used in conjunction with an external controller. The LM1949
derives its input signal from either a control oriented processor (COPSTM), microprocessor, or some other system. This
input signal, in the form of a square wave with a variable
duty cycle and/or variable frequency, is applied to Pin 1. In
a typical system, input frequency is proportional to engine
RPM. Duty cycle is proportional to the engine load. The circuits discussed are suitable for use in either open or closed
loop systems. In closed loop systems, the engine exhaust is
monitored and the air-to-fuel mixture is varied (via the duty
cycle) to maintain a perfect, or stochiometric, ratio.

age and the saturation voltage of Q1. The drop across the
sense resistor is created by the solenoid current, and when
this drop reaches the peak threshold level, typically 365 mV,
the IC is tripped from the peak state into the hold state. The
IC now behaves more as an op amp and drives Q1 within a
closed loop system to maintain the hold reference voltage,
typically 94 mY, across Rs. Once the injector current drops
from the peak level to the hold level, it remains there for the
duration of the input signal at Pin 1. This mode of operation
is preferable when working with solenoids, since the current
required to overcome kinetic and constriction forces is often
a factor of four or more times the current necessary to hold
the injector open. By holding the injector current at one
fourth of the peak current, power dissipation in the solenoids and Q1 is reduced by at least the same factor.

INJECTORS

Injectors and solenoids are available in a vast array of sizes
and characteristics. Therefore, it is necessary to be able to
design a drive system to suit each type of solenoid. The
purpose of this section is to enable any system designer to
use and modify the LM1949 and associated circuitry to
meet the system specifications.

In the circuit of Figure 1, it was known that the type of injector shown opens when the current exceeds 1.3 amps and
closes when the current then falls below 0.3 amps. In order
to guarantee injector operation over the life and temperature range of the system, a peak current of approximately 4
amps was chosen. This led to a value of Rs of 0.10. Dividing the peak and hold thresholds by this factor gives peak
and hold currents through the solenoid of 3.65 amps and
0.94 amps respectively.

Fuel injectors can usually be modeled by a simple RL circuit.
Figure 3 shows such a model for a typical fuel injector. In
actual operation, the value of L1 will depend upon the status
of the solenoid. In other words, L1 will change depending

Different types of solenoids may require different values of
current. The sense resistor Rs may be changed accordingly.
An 6-amp peak injector would use Rs equal to .050, etc.
Note that for large currents above one amp, IR drops within
the component leads or printed circuit board may create
substantial errors unless appropriate care is taken. The
sense input and sense ground leads (Pins 4 and 5 respectively), should be Kelvin connected to Rs. High current
should not be allowed to flow through any part of these
traces or connections. An easy solution to this problem on
double-sided PC boards (without plated-through holes) is to
have the high current trace and sense trace attach to the
Rs lead from opposite sides of the board.

HI
~
2mH

In

TL/H/S062-6

FIGURE 3. Model of a Typical Fuel Injector

upon whether the solenoid is open or closed. This effect, if
pronounced enough, can be a valuable aid in determining
the current necessary to open a particular type of injector.
The change in inductance manifests itself as a breakpoint in
the initial rise of solenoid current. The waveforms on Page 2
at the sense input show this occurring at approximately 130
mY. Thus, the current necessary to overcome the constrictive forces of that particular injector is 1.3 amperes.

TIMER FUNCTION

The purpose of the timer function is to limit the power dissipated by the injector or solenoid under certain conditions.
Specifically, when the battery voltage is low due to engine
cranking, or just undercharged, there may not be sufficient
voltage available for the injector to achieve the peak current. In the Figure 2 waveforms under the low battery condition, the injector current can be seen to be leveling out at 3

PEAK AND HOLD CURRENTS

The peak and hold currents are determined by the value of
the sense resistor Rs. The driver IC, when initiated by a
logic 1 signal at Pin 1, initially drives Darlington transistor Q1
into saturation. The injector current will rise exponentially
from zero at a rate dependent upon L1, R1, the battery volt-

5-160

r-

Timer Function

(Continued)

L

INPUT VOLTAGE
PIN llVI

amps, or 1 amp below the normal threshold. Since continuous operation at 3 amps may overheat the injectors, the
timer function on the IC will force the transition into the hold
state after one time constant (the time constant is equal to
ATCT). The timer is reset at the end of each input pulse. For
systems where the timer function is not needed, it can be
disabled by grounding Pin 8. For systems where the initial
peak state is not required, (i.e., where the solenoid current
rises immediately to the hold level), the timer can be used to
disable the peak function. This is done by setting the time
constant equal to zero, (I.e., CT = 0). Leaving AT in place is
recommended. The timer will then complete its time-out and
disable the peak condition before the solenoid current has
had a chance to rise above the hold level.

INJECTOR
CURRENT (AI

4
3

0

4

01
CURRENT (AI
0

The actual range of the timer in injection systems will probably never vary much from the 3.9 milliseconds shown in
Figure 1. However, the actual useful range of the timer extends from microseconds to seconds, depending on the
component values chosen. The useful range of AT is approximately 1k to 240k. The capacitor CT is limited only by
stray capacitances for low values and by leakages for large
values.

ZENER
CURRENT (AI

The capacitor reset time at the end of each controller pulse
is determined by the supply voltage and the capacitor value.
The IC resets the capacitor to an initial voltage (VSE) by
discharging it with a current of approximately 15 mAo Thus,
a 0.1 ",F cap is reset in approximately 25 ",s.

01 COLLECTOR
VOLTAGE (VI

2

VZ·
VBATT

TLlH/5062-7

COMPENSATION

FIGURE 4. Circuit Waveforms

Compensation of the error amplifier provides stability for the
circuit during the hold state. External compensation (from
Pin 2 to Pin 3) allows each design to be tailored for the
characteristics of the system and lor type of Darlington power device used. In the vast majority of designs, the value or
type of the compensation capacitor is not critical. Values of
100 pF to 0.1 ",F work well with the circuit of Figure 1. The
value shown of .01 ",F (disc) provides a close optimum in
choice between economy, speed, and noise immunity. In
some systems, increased phase and gain margin may be
acquired by bypassing the collector of Q1 to ground with an
appropriately rated 0.1 ",F capacitor. This is, however, rarely
necessary.

amplifier keeps Q1 off until the injector current has decayed
to the proper value. The disadvantage of this particular configuration is that the ungrounded zener is more difficult to
heat sink if that becomes necessary.
The second purpose of Z1 is to provide system transient
protection. Automotive systems are susceptible to a vast
array of voltage transients on the battery line. Though their
duration is usually only milliseconds long, Q1 could suffer
permanent damage unless buffered by the injector and Z1'
This is one reason why a zener is preferred over a clamp
diode back to the battery line, the other reason being long
decay times.
VBATT

FLYBACK ZENER

--,I

The purpose of zener Z1 is twofold. Since the load is inductive, a voltage spike is produced at the collector of Q1 anytime the injector current is reduced. This occurs at the peakto-hold transition, (when the current is reduced to one fourth
of its peak value), and also at the end of each input pulse,
(when the current is reduced to zero). The zener provides a
current path for the inductive kickback, limiting the voltage
spike to the zener value and preventing Q1 from damaging
VOltage levels. Thus, the rated zener voltage at the system
peak current must be less than the guaranteed minimum
breakdown of Q1. Also, even while Z1 is conducting the
majority of the injector current during the peak-to-hold transition (see Figure 4), Q1 is operating at the hold current
level. This fact is easily overlooked and, as described in the
following text, can be corrected if necessary. Since the error
amplifier in the IC demands 94 mV across As, Q1 will be
biased to provide exactly that. Thus, the safe operating area
(SOA) of Q1 must include the hold current with a VeE of Z1
volts. For systems where this is not desired, the zener anode may be reconnected to the top of As as shown in Figure 5. Since the voltage across the sense resistor now accurately portrays the injector current at all times, the error

I

IIIIINJECTOR
I
I
---'

TL/H/5062-8

FIGURE 5. Alternate Configuration for Zener Z1
5-181

......
==

CO
~

CO

POWER DISSIPATION
The power dissipation of the system shown in Figure 1 is
dependent upon several external factors, including the frequency and duty cycle of the input waveform to Pin 1. Calculations are made more difficult since there are many discontinuities and breakpoints in the power waveforms of the
various components, most notably at the peak-to-hold transition. Some generalizations can be made for normal operation. For example, in a typical cycle of operation, the majority of dissipation occurs during the hold state. The hold state
is usually much longer than the peak state, and in the peak
state nearly all power is stored as energy in the magnetic
field of the injector, later to be dumped mostly through the
zener. While this assumption is less accurate in the case of
low battery voltage, It nevertheless gives an unexpectedly
accurate set of approximations for general operation.

The LM1949 can be easily modified to function as a switcher. Accomplished with the circuit of Figure 7, the only additional components required are two external resistors, RA
and Rs. Additionally, the zener needs to be reconnected, as
shown, to RS. The amount of ripple on the hold current is
easily controlled by the resistor ratio of RA to Rs. Rs is kept
small so that sense input bias current (typically 0.3 mAl has
negligible effect on VH. Duty cycle and frequency of oscillation during the hold state are dependent on the injector
characteristics, RA, Rs, and the zener voltage as shown in
the following equations.
VH
Hold Current ::::: RS

The following nomenclature refers to Figure 1. Typical values are given in parentheses:
Rs

= Sense Resistor (0.1.0.)

VH

=Sense Input Hold Voltage (.094V)

Vp

= Sense Input Peak Voltage (.385V)

Vz

=Z1 Zener Breakdown Voltage (33V)

VSATT

= Battery Voltage (14V)

L1

= Injector Inductance (.002H)

R1

= Injector Resistance (10)

n

= Duty Cycle of Input Voltage of Pin 1 (0 to 1)

Minimum Hold Current :::::

Rs
1
Ripple or AI Hold ::::: RA • Vz • Rs
f ::::: Rs. RA. VSATT • (1 _ VSATT)
o
L1 Rs
Vz
Vz
fo = Hold State Oscillation Frequency
VSATT
Duty Cycle of fo ::::: ~

= Frequency of Input (10Hz to 200Hz)

Component Power Dissipation

01 Power Dissipation:

VSATT) VSAT
Po ::::: n· ( 1 - - - • - - . VH
Vz
Rs
VSAT = 01 Saturation Volt @ - 1 Amp (1.5V)

VH
Po ::::: n • VSATT • Watts
Rs
Zener Dissipation:
(Vp2
Pz ::::: Vz • L1 • f •

(VH - :S .Vz)
R:

+ VH2)

Pz:::::n.

VSATT·VH
Rs

2 Watts
((VZ-VSATT) • Rs )
Vs·Vz
PRA:::::--R1
As shown, the power dissipation by 01 in this manner is
substantially reduced. Measurements made with a thermocouple on the bench indicated better than a fourfold reduction in power in 01. However, the power dissipation of the
zener (which is independent of the zener voltage chosen) is
increased over the circuit of Figure 1.

Injector Dissipation:
VH 2
PI ::::: n • R1 • RS2 Watts
Sense Resistor:
VH 2
PR ::::: n -2 Watts
Rs
Vp2
PR (worst case) ::::: n RS2 Watts

5V
INPUT VOLTAGE
PIN 1(V)

SWITCHING INJECTOR DRIVER CIRCUIT
The power diSSipation of the system, and especially of 01,
can be reduced by employing a switching injector driver circuit. Since the injector load is mainly inductive, transistor 01
can be rapidly switched on and off in a manner similar to
switching regulators. The solenoid inductance will naturally
integrate the voltage to produce the required injector current, while the power consumed by 01 will be reduced. A
note of caution: The large amplitude switching voltages that
are present on the injector can and do generate a tremendous amount of radio frequency interference (RFI). Because
of this, switching circuits are not recommended. The extra
cost of shielding can easily exceed the savings of reduced
power. In systems where switching Circuits are mandatory,
extensive field testing is required to guarantee that RFI cannot create problems with engine control or entertainment
equipment within the vicinity.

OV
400mV
SENSE INPUT VOLTAGE
PIN 41mVJ
OV
Vz

Vom
01 COLLECTOR

-

LlAAA

.A

-

-

~

VOLTAGE IV)
OV

TUH/5062-9

FIGURE 6. Switching Waveforms

5-182

r-------------------------------------------------------------------------.r
VBATT

s::
.....

:• LI

"'"

CD

CD

II : INJECTOR
...•
+1F=4--o Vee =5V

RO
Rs
O.lll
2W

TL/H/S062-10

FIGURE 7. Switching Application Circuit

I
5·183

~

Ln

en
~

:E
...J

r------------------------------------------------------------------------------------,

~ Semiconductor
NatiOnal

PRELIMINARY

Corporation

LM 1951 Solid State 1 Amp Switch
General Description

Features

The LM1951 is a high current, high voltage high side (PNP)
switch with a built-in error detection circuit.

• 0.1 poA typical quiescent current (OFF state)
• 1.1 Amp output current
• ± 85V supply voltage transients
• Reverse voltage protection
• Negative output voltage clamp
• Error flag output
• Internal overvoltage shutdown
• Internal thermal shutdown
• Short circuit proof
• High speed switching (up to 50 kHz)
• Inductive or resistive loads
• Low ON resistance (1,n maximum)
• TTL, CMOS compatible input with hysteresis
• Plastic TO-220 5-lead package
• ESD protected
• 4.5V to 26V operation

The LM1951 is guaranteed to deliver 1 Amp output current
and is capable of withstanding up to ± 85V transients. The
built-in error detection provides an error flag output under
the following fault conditions: output short to ground or supply, open load, current limit, overvoltage or thermal shutdown. The LM1951 will drive all types of resistive or inductive loads. The output has a built-in negative voltage clamp
(::::: - 30V) to provide a quick energy discharge path for
inductive loads. The LM1951 features TTL and CMOS compatible logic input with hysteresis. Switching times, both turn
on and turn off, are 2 pos (Cload < 0.005 poF). In addition, its
quiescent current in the OFF state is typically less than
0.1 poA at room temperature and less than 10 poA over the
entire operating temperature and voltage range.
The LM1951 features make it well suited for industrial and
automotive applications.

Typical Application Circuit and Connection Diagram
Vs = 5VT024V
,Il0nF

VIN

vo~
i~""oo
_.

SL o-=+-~-I

-.

VLOGIC

2kll.

I

ERROR 0--4--'='-'
FLAG

TLIH19133-1

VIN

o

Output

OFF

ON
5·Lead TO·220

5 VIN

4 ERROR FLAG

0

3 GROUND

2 Vo

0

1 Vs
TLIH19133-2

Order Number LM1951T
See NS Package Number T05A

5·184

.-3i:
......

Absolute Maximum Ratings

CD

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Load Inductance

1H

Operating Temperature Range (TA)

- 40·C to

+ 125·C

- 65·C to

+ 150·C

150·C

Maximum Junction Temperature

Supply Voltage
Operational Voltage
26Voc
Sustained Voltage
-40 Voc :<: Vs ,,; 85 Voc
Transient Voltage Protection
±85V
(T = 100 ms, 1 % Duty Cycle, RS :<: 100)
Pins 4, 5
26Voc
Power Dissipation (Note 1)
Internally Limited

Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)

230·C

ESD Tolerance (Note 4):
(Czap = 100 pF, Rzap = 15000)

2000V

Electrical Characteristics
Vs

=

12V, lout

=

500 mA, Cout

=

0.001 p.F, T A

=

Parameter

25·C unless otherwise specified

Conditions

Typical

Supply Voltage
Operational
Transient

T

=

100 ms, 1 % Duty Cycle, Rs :<: 100

Tested
Limit
(Note 2)

Design
Limit
(Note 3)

4.5

Vmin

26

V max

-85

V
V

85
Supply Current

=
lout =

lout

lout

=

=
lout =

lout
Voltage Drop
(VS - YO)

lout

=

0 mA, Yin

=

0.1

0.8V

10

100

p.Amax

250 mA, Yin

=

2.0V

260

270

mAmax

600 mA, Yin

=

2.0V

630

650

mAmax

1.06

1.2

Amax

400

600

mV max

0.7

1.0

V

1A, Yin

=

2.0V

600 mA, Yin
1A, Yin

=

=

2.0V

2.0V

Short Circuit Current

Input Threshold

Units

1.3

I TurnON
I TurnOFF

4.5V ,,; Vs ,,; 26V

Input Current

0.8V ,,; Yin ,,; 5.5V

Output Clamp

lout"; 600 mA

1.0

Amin

2.5

Amax

1.4

2.0

2.0

1.2

0.8

0.8

25

V max
Vmin

50

p.Amax

10

P.Amin

-40

Vmin

-24

V max

1

3

p'smax

1

3

p.smax

Rise Time

1

3

p'smax

Fall Time

1

3

p.smax

0.3

0.8

Vmax

10

3

mAmin

0.01

1

p.A

Delay
Time

td,ON
Id,OFF

Rload

=

-30

200, Cload

=

0.001 p.F

Error Flag Characteristics
Output Voltage

Error Condition, Pin 5 Low, Sinking 10 mA

Sink Current

Error Condition, Pin 5

Output Leakage Current

No Error, Pin 5

Response Time

VLOGIC

=

=

=

0.3V

26V

5V, RLOGIC

=

2 kO, CLOGIC

=

0 p.F

Note 1: Thermal resistance without a heatsink for junction~to·case temperature is 3°C/W. Thermal resistance

1
cas8~to-ambient

p.s
is 50°C/W.

Note 2: Tested Limits are guaranteed and 100% production tested.
Note 3: Design Limits are guaranteed (but not 100% production tested) over the operating temperature and supply voltage range. These limits are not used to
calculate outgoing quality levels.

Note 4: ESO testing performed per SOP·5-02B reqUirements.

5-185

U1

......

Typical Performance Characteristics
Quiescent Current
100

Quiescent Current
60

Vs=12V

90 V1n=2V

!

~
a

S
8

80

60

so
.co

30
20

50

~a

40

~

30

~

S

1/

10 =

5
0

o

6ooml- ::::
---Pr
10::

10::

10

o

-so

-25

Voltage Drop

I
I

10= 100mA
Q.2

o
-so

I I
I

--

lB

I
I

0

25

so

l/

~

III

!5

08

0

0.6

~

0.4
0.2

g

~

lD

o

o

Rload

60 Vln

~

g
!5

I

~

20

15

25

'"\3
0

I

20
10

/

-so

-25

~

'"

25

-

20

-

40

t_

r- orr!

JI

VI
/ I

30
25

r-t

20

15

5

10

0

5

lD 1.1

25

1.2

1.3

1.4

1.5

1.6

o
o

1.7

05

INPUT VOLTAGE (V)

~

Vs = 12V

I
II

1.0

1.5

2.0 25 3.0 35

INPUT VOLTAGE (V)

Output Voltage
Inductive Load

15
10

100

Vs=12V

35

I-I--

o
20

75

Input Current
ON_

\..-t'r

so

25

SUPPLY VOLTAGE (V)

45

Output Voltage
Resistive Load

>-~

30

30

Vs= 12V

SUPPLY VOLTAGE (V)

;:l
gs:-

!/

.co

-20
10

30

ia

= 40n

= 2.0V

so

-10

35

~

I
I

III

0.1 0.2 0.3 0.4 05 0.6 0.7 OB 0.9 lD

High Voltage Behavior

;:l

.co

15

....-

70

III

I
II

~

OUTPUT CURRENT (A)

Input Current

~

10

o

100 125

45

Yin TURN-orr
1.2

0.3

SUPPLY VOLTAGE (V)

I
I

1.3

75

:..-

o
o

100 125

75

Vin TURN-ON

;:l

50

....-

0.4
0.2
O.1 /

lD

\3

I
I

1.4

25

1.2

a

Input Threshold
15

0

1.4

TEMPERATURE (OC)

~

t250mA

Vin=2.0V

1.6

3:

I
I
-25

g

0.6
05

Peak Output Current

10=1A

lout = 600 rnA

;:l

0.7

TEMPERATURE (OC)

OUTPUT CURRENT (A)

1

III

lo=OmA

00.10.20.30.4050.60.7080.91.0

Vs = 12V
Yin = 2V

OB
~

20

.... ~ I-' "'"

10

Vs=12V
0.9 Vin=2V

'<

.§.

70

Voltage Drop
lD

1_
IlA- --\:

Vs = 12V
Vln = 2V

\

Rl =.coll

20

1~

g>--10

.... --20 f1t;A~2; 80 mH
~ -30
5 ..40 +4011 SERIES R

III

;:l

g~

~
12

16

200

TINE (ps)

400

600

BOO

TIME (ps)
TL/H/9133-3

5-186

ris:

Error Flag Output Characteristics
Open Load Threshold
10

9

Open Load Threshold
10

V,N =2V

Over Voltage Threshold
40

Vs= 12V
VIN =2V

Vs= 12V
V,N =2V

E

'"~
g

r-o
o

10

15

20

~

~

o

25

35

-so -25

SUPPLY VOLTAGE (V)

25

50

75

100 125

r-30
-so -25

0

25

50

75

100 125

TEUPERATURE (oe)

TEMPERATURE (oe)

Current Limit Threshold
2.0

3:
9

~

1.5

.........

ill

i!'

!:

Vs = 12V
V,N =2V

1.0

--

...... 1--.

'"

::J

~
a

0.5

o
-50 -25

25

so

75

100 125

TEMPERATURE (oe)
TL/H/9133-13

5-187

....co
....c.n

~

It)
G)
~

r-------------------------------------------------------------------------------------,
Truth Table

::::iE
....I

Fault Condition

Vln'

VOU!

Error Flag

0

0

1

1

1

1

0

0

0

1

0

0

0

0

0

1

0

0

0

0

1

1

0

0

Vo Short to Vsupply

0

1

0

1

1

0

Open Load

0

0

1

1

1

0

0

0

1

1

1

0

Normal

Overvoltage

Thermal Shutdown

Vo Short to GND

Current Limit

Typical Applications
Vs = 12V

,I10nF

ASCO
821002-12
12,1A
1/2" NPT NORMALLY
CLOSED VALVE
ERROR
FLAG

TLlH/9133-4

FIGURE 1. Solenoid Actuated Valve

VS=24V

,I10nF

3. 480V AC
SOA RESISTIVE
OR 15HP MOTOR
ERROR
FLAG
TLlH/9133-5

FIGURE 2. 60A 3-Phase Mercury Displacement Relay

5-188

r-

Typical Applications

:s:::
......

(Continued)

U)

C1I

......

Vs= 12V 0-......- - - - - - - - . . . ,
2N4277'

0-+--1-=-9---+-0 25A

OUTPUT

25A RECTIFIER
(NECESSARY FOR
INDUCTIVE LOADS)

TLlH/9133-6

'Available from Germanium Power Devices, Andover, MA, Tel. (617) 475·5982

FIGURE 3. 25A Switch with Short Circuit Foldback

Vs = 12V

0-+--1-=.....-0 OUTPUT
.I,1 nF

TL/H/9133-7

FIGURE 4. Latching Switch

VS= 12V

HEATER

TL/H/9133-8

FIGURE 5. Proportional Temperature Controller with Hysteresis

5-189

II

~

In
~
~

:iii

r------------------------------------------------------------------------------------------,
Typical Applications

(Continued)
Vs = 12V

..J

,Il0nr

orr

TL/H/9133-9

FIGURE 6. DC Motor Driver

THRESHOLD
ADJUST

>01-=+-.......
VOLTAGESENSITIVE
CIRCUITS

TL/H/9133-10

FIGURE 7. Over-Voltage Crowbar

Vs = 12V

*o--=l~-I

TUH/9133-11

Operation

Switch Type

Empty

Normally Open

Fill

Normally Closed

FIGURE 8. Fluid Level Controller

5-190

r-

5:
.....
CO
c.n
.....

Typical Applications (Continued)
Vs = 12V

.I10nF

TL/H/9133-12

FIGURE 9. Indicator Lamp Driver

Application Hints
When inductive loads are turned OFF, they produce a negative voltage spike. The LM1951 contains a voltage clamp
that limits these spikes to approximately -30V, thus an external clamp is not necessary in most applications.
Loads with an inductance of greater than 1H, driven to full
output current, may damage the clamp simply by exceeding
the power capabilities of the LM1951. An LM1951 can dissipate 25W continuous at 25'C ambient when mounted on a
large heatsink. If the load current is limited to BOO mA, the
sustained spike from an infinitely large inductance can be
handled. Sustained spikes produced by higher currents and
high inductances will exceed the 25W limit.
For inductances above 1H, care should be taken to see that
the output current does not exceed a value that could damage the clamp. While BOO mA is acceptable for the device
running at 25'C ambient on a heatsink, derate this current
for smaller heatsinks or higher ambient temperatures to limit
the junction temperature to 125'C. Alternatively, an external
clamp or resonating capacitor can be added to handle any
combination of load inductance, load current, and device
temperature. This is especially important if the output current is boosted, such as the application shown in Figure 3. A
peak power of 750W could be developed in the internal
clamp if an inductive load is switched without external
clamping.
Another case where the clamp's power capability may be
exceeded is when driving a solenoid. The inductance of a
solenoid is greatest when energized, with the plunger pulled
in. As the plunger is pulled out of the solenoid, the inductance goes down. Under certain conditions of high solenoid
inductance and fast mechanical time constants, the current
may actually increase when the solenoid is turned OFF.
Since the energy stored in an inductor cannot change instantaneously, the current must increase to conserve energy when the inductance decreases. This condition is traced
by observing the load current with a current probe and storage oscilloscope.
Load capacitances larger than 1 nF will slow rise and fall
times. Inductive loads having a capacitive component larger
than 1 nF will also exhibit overshoot. Furthermore, ringing

may be evident in a combination inductive/capacitive load,
or in an inductive load with supply decoupling capacitors in
the range of 100 nF to 1 /LF. For fast rise and fall times and
minimum ringing with inductive loads, a supply decoupling
capacitor of 10 nF and an output capacitor of 1 nF is recommended. These should be located as close to the IC pins as
possible.
The error flag is an open collector output that pulls low under certain fault conditions. These errors include overvoltage (Vs > 26V), overcurrent (lOUT > 1.3A), undercurrent
(lOUT < 2 mAl, output short circuit to ground, output short
circuit to supply, and junction temperature greater than
150'C. By connecting a 2 kn resistor from the error flag
output to a 5V supply a logic output to a microprocessor is
provided.
The error flag can give seemingly false indications in a number of situations. Slewing large capacitive loads (>100 nF)
can drive the LM1951 into temporary current limit, producing a momentary error indication. Incandescent lamps and
DC motors require an inrush current that will also cause a
temporary current limit and error indication. Large inductive
loads (> 50 mH) initially appear as open circuits, falsing the
error flag. The error flag pulses for about 1 /Ls when any
load is turned ON since the output is initially at ground. In
microprocessor systems these false indications are easily
ignored in software. In discrete logic circuits utilizing a latch
at the error flag output, some filtering may be required.
An internal current sink (10 /LA minimum) is connected to
the input, pin 5. If this pin is left open it is guaranteed to pull
low, switching the LM1951 OFF. This characteristic is important under certain fault conditions such as when the control line fails open cirucit.
Although the input threshold has hystereSiS, the switch
points are derived from a very stable band-gap reference. In
many applications, such as Figures 5 and 7, the LM1951
input can replace an extenal reference and comparator.
The input (pin 5) is clamped at -0.7V and includes a series
resistance of approximately 30 kn. This pin tolerates negative inputs of up to 1 mA without affecting the performance
of the chip.

5-191

II

-=r
CD
en
:!i!

....

....I

r----------------------------------------------------------------------------,
NatiOnal

~ Semiconductor
Corporation

LM1964 Sensor Interface Amplifier
General Description
The LM1964 is a precision differential amplifier specifically
designed for operation in the automotive environment. Gain
accuracy is guaranteed over the entire automotive temperature range (- 40·C to + 125·C) and is factory trimmed prior
to package assembly. The input circuitry has been specifically designed to reject common-mode signals as much as
3V below ground on a single positive power supply. This
facilitates the use of sensors which are grounded at the
engine block while the LM1964 itself is grounded at chassis
potential. An external capacitor sets the maximum operating
frequency of the amplifier, thereby filtering high frequency
transients. Both inputs are protected against accidental
shorting to the battery and against load dump transients.
The input impedance is typically 1 MO..

vided to detect open circuit conditions on either or both inputs and force the output to a "home" pOSition (a ratio of
the external reference voltage).

Features
• Normal circuit operation guaranteed with inputs up to
3V below ground on a single supply
• Gain factory trimmed and guaranteed over temperature
(±3% of full-scale from -40·C to + 125·C)
• Low power consumption (typically 1 rnA)
• Fully protected inputs
• Input open circuit detection
• Operation guaranteed over the entire automotive temperature range (- 40·C to + 125·C)
• Single supply operation

The output op amp is capable of driving capacitive loads
and is fully protected. Also, internal circuitry has been pro-

Schematic and Connection Diagrams
r---t"-......- -......- -......- - - t " - -.....- ......- -......------(:::JVcc

r-......--p-+----1i--;-t"--t---t-----1i--+--t---i---1>----DVm

,,..

L--.1'--W_nVOUT
14k

220k

4k

~-

__

--~-----------~----~---~---~~--£]~D
TL/H/6744-1

Plastic Chip Carrier Package
Q

I
INVERTING 5
INPUT

•

Order Number LM1964V
See NS Package Number V20A

•
•

NON-INVERTING 7
INPUT

·Pins 1, 3, 4, 6, 8, 9, 10, 11, 13, 14, 16, 18, 19 are
trim pins and should be left floating.

TL/H/6744-6

Top View
5-192

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VCC Supply Voltage (RVCC = 15 kO)
±60V

- 40·C to + 125·C

Operating Temperature Range
Storage Temperature Range

- 65·C to + 150·C

Soldering Information
Plastic Chip Carrier Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

215·C
220·C

VREF Supply Voltage
DC Input Voltage (Either Input)
InputTransients (Note 1)

-0.3Vto +6V
-3Vto +16V
±60V

Power Dissipation (see Note 6)
Output Short Circuit Duration

1350mW
Indefinite

Electrical Characteristics Vcc =

12V, VREF = 5V, TA = 25·C unless otherwise noted

Parameter
Differential Voltage Gain

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

(Note 2)

Conditions
VOIF=0.5V
-1V,;:VCM';:+W

(Note 3)

Min

Typ

Max

4.41

4.50

4.59

VOIF=0.5V, -40·C,;:TA,;:125·C
-3V,;:VCM';:+W
Gain Error (Note 5)

0

1.00

0.3

0

1.20

45

%/FS

MO

/LA
0.3

O,;:VOIF';:W
-W,;:VCM';:+1V

3

1.0

O,;:VOIF';:W
-3V,;:VCM';: + 1V
-40·C,;:TA';: + 125·C
Inverting Input Bias Current

VIV

MO
0.70

O,;:VOIF';:W
-W,;:VCM';:+W

4.64

1.20

O,;:VOIF';:W
-3V,;:VCM';:+W
-40·C,;:TA+125·C
Non-Inverting Input Bias
Current

4.50

%/FS
-3

0,;:VOIF';:1V
-W,;:VCM';:+W

Units
Max

2

O,;:VOIF';:W
-3V,;:VCM';:+W
-40·C,;:TA';: + 125·C
Differential Input Resistance

Typ

VIV
4.36

-2

O,;:VOIF';:W
-W,;:VCM';:+W

Min

1.5

100

/LA

OV,;:VOIF';:W
-3V,;:VCM';:+1V
-40·C,;:TA';: + 125·C

45

VCC Supply Current

VCC=12V, RVcc=15k

300

500

VREF Supply Current

4.75V,;:VREF,;:5.5V

0.5

1.0

Common-Mode Voltage
Range (Note 4)

-40·C,;:TA';: + 125·C

-1

DC Common-Mode
Rejection Ratio

Input Referred
-W,;:VCM';:+W
VOIF=0.5V

50

60

Open Circuit Output Voltage

One or Both Inputs
Open, -W,;:VCM';:+W

0.371

0.397

1

/LA

150

/LA

/LA
mA
-3

1

V
dB

0.423

-3V,;:VCM';:+W
-40·C,;:TA';: +125·C

XVREF
0.365

0.397

0.429

XVREF

Short Circuit Output Current

Output Grounded

1.0

2.7

VCC Power Supply Rejection
Ratio

Vcc=12V, RVcc= 15K
VOIF=0.5V

50

65

dB

VREF Power Supply
Rejection Ratio

VREF= 5VOC
VOIF=0.5V

60

74

dB

5.0

mA

Note 1: This test is performed with a 1aoon source impedance.
Note 2: These parameters are guaranteed and 100% production tested.
Note 3: These parameters will be guaranteed but not 100% production tested.

Note 4: The LMI964 has been designed to common·mode to

-3V, but production testing is only performed at ± W.

Note 5: Gain error is given as a percent of full-scale. Full-scale is defined as 1V at the input and 4.SV at the output.
Note 6: For operation in ambient temperatures above 2SClC the device must be derated based on a maximum junction temperature of 150°C and a thermal
resistance of 93°C/W junction to ambient.

5-193

II

~

CD

....
G)

r---------------------------------------------------------------------------------Typical Performance Characteristics

::E
....I

Inverting Input Bias Current
vs Temperature

Non-Inverting Input Bias
Current vs Temperature
800

150

..~

1125

zw 600

...'"'":::>

..'"

'":!§

ffiII§

I......

:::>

-

400

ii.'! 200

100

...
;

75

'"

~

I

+

~

50

!.

!.

~
~ r--..

25

o
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (OC)

-50-~

1

.
zw

'"
:::>
'"

...

I

r-

'"
~

0.4

-

~
~

-

i§

...

~

co

!::
:::>

~
0.1
-50-~

0 ~ 50 ~ 100 n5 ffiO
TEMPERATURE (OC)

Differential Gain vs
Temperature
4.700
4.650
z4.600

r;;1ooo..

.
!i
C

I"

::: 4.550

"

...... ~

w

4.500

450
m··4.400

~
i3

is

L...o

-

-""""

I-

4.350

Ii:

ii

0.3

~

Short Circuit Output
Current vs Temperature

"-

Vcc=12V

l - f- f-RVcc 15k

II:
~ 0.2

0.2
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (OC)

1

n5 ffiO

c

§. 0.4

0.6

roo

0.5

J.

0.8

...~

~

Vee Supply Current vs
Temperature

VREF=5.0V

:::>

50

TEMPERATURE (OC)

VREF Supply Current vs
Temperature

c
§.

~

0

r-...

4.300

0
-50 -25 0 25 50 75 100 125 150

-50-~

TEMPERATURE (OC)

5-194

0 ~ 50 ~lool~l50
TEMPERATURE (OC)

TUH/6744-3

r------------------------------------------------------------------------,
Typical Performance Characteristics

(Continued)

r

s:
.....
CD

en

Voltage Gain vs Frequency
1111 1111111

20

!

W
a:

~

VCM =1 Vrms

CF=1000 pF

0

~

40

~

20

:!;

'"

~ -10

I~
IC~=OPF

60

....

10

z
;;:

""

CMRR vs Frequency
80

a:
a:

I-+I+IIIHH-ttlIIIIII-+l+HlI!k,:++

~

.,:Ii;
0

- 20 H-HflIIII-I+
-20
10

100
Ik
10k
FREQUENCY (Hz)

lOOk

10

VREF Power Supply
Rejection
80

..~
z

I'

40

......

20

'"

0

~

..
::::0

Vee Power Supply Rejection

VREF=5 Voc
100mVrms
CF=O pF

!z

~

Ul

i"o

60

co

5w

40

'"

E 20

.
I

-+-H*Hf-IRVCC=15 kll
CF~O pF
-+-HIIIHf-I Vcc=12 Voc

::::0

w

~

-20

0

1I1111111~r~~1

-20
10

100

lOOk

80

lJ.lllIlll. J.III

60

;::
~
Ul
a:

100
lk
10k
FREQUENCY (Hz)

Ik
10k
FREQUENCY (Hz)

lOOk

100

10

Ik

10k

lOOk

FREQUENCY (Hz)
TL/H/6744-4

Test Circuit
Vcc
(9V-16V)
VREF
(4.75Vt50V)

15k

O'Ol~Fi

20

17

r'

~~

NON-INVERTlN~..2 r-- ~

,",'7

INPUT

12

Av =4.5
INVERTIN~.J.

INPUT

r--

V

I

15,j}
RF

- ""0.01 ~F

"J;

GND

1:"
TLlHI6744-S

5-195

~
.,...

t7)

N

::::E

....I

.....

,------------------------------------------------------------------------------------,
NatiOnal

~ Semiconductor
.

~

Corporation

C

t7)

N

::::E

LM2907/LM2917 Frequency to Voltage Converter

....I

General Description
The LM2907, LM2917 series are monolithic frequency to
voltage converters with a high gain op amp/comparator designed to operate a relay, lamp, or other load when the input
frequency reaches or exceeds a selected rate. The tachometer uses a charge pump technique and offers frequency
doubling for low ripple, full input protection in two versions
(LM2907-8, LM2917-8) and its output swings to ground for a
zero frequency input.

Advantages
•
•
•
•

Output swings to ground for zero frequency input
Easy to use; VOUT = fiN X Vee x R1 x C1
Only one RC network provides frequency doubling
Zener regulator on chip allows accurate and stable frequency to voltage or current conversion (LM2917)

Features
• Ground referenced tachometer input interfaces directly
with variable reluctance magnetic pickups
• Op amp/comparator has floating transistor output
• 50 mA sink or source to operate relays, solenoids, meters, or LEDs

• Frequency doubling for low ripple
• Tachometer has built-in hysteresis with either differential input or ground referenced input
• Built-in zener on LM2917
• ±0.3% linearity typical
• Ground referenced tachometer is fully protected from
damage due to swings above Vee and below ground

Applications
•
•
•
•
•
•
•
•
•
•
•

Over/under speed sensing
Frequency to voltage conversion (tachometer)
Speedometers
Breaker pOint dwell meters
Hand-held tachometer
Speed governors
Cruise control
Automotive door lock control
Clutch control
Horn control
Touch or sound switches

Block and Connection Diagrams Dual-In-Line and Small Outline Packages, Top Views
v'

TLlH/7942-1

TL/H17942-2

Order Number LM2907N-S
See NS Package Number NOSE
Ne

Ne

Order Number LM2917N-S
See NS Package Number NOSE

v'

Ne

Ne

Ne

Ne

v'

Ne

TL/H17942-3

Order Number LM2907N
See NS Package Number N14A

Ne
TL/H17942-4

Order Number LM2917M or LM2917N
See NS Package Number M14A or N14A

5-196

r-

3:

Absolute Maximum Ratings (Note 1)

N
CD

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications_
Supply Voltage

2BV

Supply Current (Zener Options)

2BV

Differential Input Voltage
Tachometer
Op Amp/Comparator

2BV
2BV

Input Voltage Range
Tachometer LM2907-B, LM2917-B
LM2907, LM2917
Op Amp/Comparator

1200 mW
15BO mW

Operating Temperature Range

25mA

Collector Voltage

-40'Cto +B5'C
- 65'C to + 150'C

Storage Temperature Range
Soldering Information
Dual-In-Line Package
Soldering (10 seconds)
Small Outline Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

±2BV
O.OVto +2BV
O.OVto +2BV

....

o

Power Dissipation
LM2907-B, LM2917-B
LM2907-14, LM2917-14
(See Note 1)

........

r-

3:

N
CD

.........

260'C
215'C
220'C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

Electrical Characteristics Vcc = 12Voc, TA = 25'C, see test circuit
Symbol

Parameter

Conditions

Min

Typ

Max

Units

±10

±25

±40

mV

TACHOMETER
Input Thresholds

VIN

Hysteresis

VIN

Offset Voltage
LM2907/LM2917
LM2907-B/LM2917-B

VIN

=
=
=

250 mVp-p

@

1 kHz (Note 2)

250 mVp-p

@

1 kHz (Note 2)

250 mVp-p

@

1 kHz (Note 2)

30

mV

3.5
5

10
15

mV
mV

1

p.A

12. 13

Output Current

13

Leakage Current

= ± 5OmVoc
= + 125 mVoc (Note 3)
VIN = -125 mVoc (Note 3)
V2 = V3 = 6.0V (Note 4)
12 = 0, V3 = 0

K

Gain Constant

(Note 3)

0.9

1.0

1.1

Linearity

fiN

=

-1.0

0.3

+1.0

%

Input Bias Current

VIN

0.1

VOH

Pin2

VIN

B.3

VOL

Pin2

1 kHz, 5 kHz, 10kHz (Note 5)

V
V

2.3
140

1BO

240

p.A

0.1

p.A

OP/AMP COMPARATOR
VOS

VIN

ISlAS

VIN

=
=

6.0V

3

10

mV

6.0V

50

500

nA

Input Common-Mode Voltage

0

Voltage Gain

=
=

Output Sink Current

Vc

Output Source Current

VE

Saturation Voltage

ISINK
ISINK
ISINK

40

1.0

Vcc- 1.5V

V/mV

50

mA

Vcc -2.0

10

=
=
=

0.1

5mA
20mA
50mA

V

200

1.0

mA
0.5

V

1.0

V

1.5

V

LI
5-197

Electrical Characteristics Vcc =
Symbol

12 VDC, TA = 25'C, see test circuit (Continued)

Parameter

Conditions

Min

Typ

Max

Units

15

0.

ZENER REGULATOR
Regulator Voltage

7.56

RDROP = 4700.

Series Resistance

10.5

Temperature Stability

+1

TOTAL SUPPLY CURRENT

3.8

V

mVI"C
mA

6

Note 1: For operation in ambient temperatures above 25°C, the device must be derated based on a 150"C maximum junction temperature and a thermal resistance

of 10l'C/W iunelion to ambient for LM2907·8 and LM2917·8, and 79'C/W iunction to ambient for LM2907-14 and LM2917-14.
Note 2: Hysteresis is the sum + VTH - (- VTH), offset voltage is their difference. See test circuit
Note 3: VOH is equal to % x Vee - I VSE, VOL is equat to % x Vee - I VSE therefore VOH - VOL ~ Vee/2. The difference, VOH - VOL. and the mirror gain,
12/13, are the two factors that cause the tachometer gain constant to vary from 1.0.
Note 4: Be sure when choosing the time constant RI X CI that R I is such that the maximum antiCipated output voltage at pin 3 can be reached with 13 X RI. The
maximum value for RI is limited by the output resistance of pin 3 which is greater than 10 MO typically.
Note 5: Nonlinearity is defined as the deviation of VOUT (@ pin 3) for fiN ~ 5 kHz from a straight line defined by the VOUT @ I kHz and VOUT @ 10 kHz.
CI ~ 1000 pF, RI ~ 6Sk and C2 ~ 0.22 mFd.

General Description (Continued)
The op amp/comparator is fully compatible with the tachometer and has a floating transistor as its output. This
feature allows either a ground or supply referred load of up
to 50 mA. The collector may be taken above Vcc up to a
maximum VCE of 28V.
The two basic configurations offered include an 8-pin device
with a ground referenced tachometer input and an internal
connection between the tachometer output and the op amp
non-inverting input. This version is well suited for single
speed or frequency switching or fully buffered frequency to
voltage conversion applications.

The more versatile configurations provide differential tachometer input and uncommitted op amp inputs. With this
version the tachometer input may be floated and the op
amp becomes suitable for active filter conditioning of the
tachometer output.
Both of these configurations are available with an active
shunt regulator connected across the power leads. The regulator clamps the supply such that stable frequency to voltage and frequency to current operations are possible with
any supply voltage and a suitable resistor.

Test Circuit and Waveform
TACHOMETER
INPUT

~

IOIAS

+

OPAMP
SECTION

TACHOMETER
SECTION

~
+

ISINK

Tachometer Input Threshold Measurement
V2

-

PUMP

+

NEGATIVE
INPUT

THRESHOLD

/J

/
POSITIVE
f./INPUT

/

THRESHOLD

VIN TACHOMETER

I

T

Cl-'-'- Ie
TACHOMETER
INPUT

TL/H17942-7

8-:",:'\

Rl!'

)

ISOURCE~

TC2

"*-=

TL/H17942-6

5-198

Typical Performance Characteristics
Zener Voltage vs
Temperature

Total Supply Current

Normalized Tachometer
Output vs Temperature

g 1.010

1.66
1.&4

Vcr.:" 12V

~

~

-40-C
+Z~·C ~

I::=~~n

N

1.50

ffi

II

~

1.

86Dn

~i-'

1.004
tul.00Z

I/.

470n

~ 0.996
:::i 0.994

~

~

V

25

45

65

85

-35 -15

Tachometer Currents 12
and 13 VS Supply Voltage

1.010

Z6D

~

240

ffi 1.004

"

~

::'

""" I'.

LM29DI

LM2117141D!I)

'" 0.'92
1

"z

.". liD

I'.

160
140

I

~ 0.990

-u

lZD

-15

5

25

45

&5

15

k::1"
I-'

I::::

D.9
0.1
0.1

a:

0.5

~

....~

"
S
C>

!!

'''100Hz

'"
'"'"
>
C>

RI • 10k
Cl: O.OSmFd

~

....

L""Z911(4JO!!)-

~z

:;;

0.4

LM29DI

D.J

'"

I
I
I

0.2
0.1

-35 -15

45

65

Vee" 12V
I" 1000Hz
RI = 7Dk

0.1

CI =0.01 mfd

D.9

!!

21

24V

~

'"

2&

l&V
12V

~

~

24
22

/ V.
/.

IV

20
-55 -35 -15

-

1.0
0.9
0.8

'"
'"'"
>

0.6

z

0.4

....

D.J

5C>

D.Z

....
a:
::;

LM29n IOJOnl LMZ9DI t-- t--

:;;

"

V

-35 -15

I
&5

IS

25

45

65

85

Vee" 12\1

1000 Hz
RICI" l.O -l.5ms

f=

0.7
0.5

IS b-,

LJ;;'D~

~

0.1

5

25

45

65

85

LM2911147Dl!)-':'
lOOk

J.D
2.1
2.6

~

2.4

~
>,

2.2

1.0

2.0
1.8

~13 ~
:6'

~

j

+85·C
10

ZD

JD

SOURCE CURRENT ImAI

1.2

~

1.0

D.'
O.Z

I I
40

1

1.4

z

~

"IS'

01

~M21' TV;'OC)

+25·C

~

J" 0.&

..... ""I

-4D'C

4QOlc

500k

~

1.6

LM29Dl

1.1
1.6

lOOk

Op Amp Output Transistor
Characteristics

~l

Z.D

ZOok

RII!!!

Op Amp Output Transistor
Characteristics

~

5

0

1.2
45

&V

1

Tachometer Linearity vs R 1

0.2

1.4

25

V
vy

-35 -15

C>

0.4

'"

>

5

12V

~

0.1

.

-......

V

V

TEMPERATURE I·CI

./

V ./

8S

TEMPE RATURE '''CI

0.5

85

I
I
30

65

ZDVV

160

!!

0.6

Tachometer Input Hysteresis
vs Temperature

5

45

120

TEMPERATURE I-Cl

'~

.".

-4D'C

~

0.1

~
....

2S

180

1.0

D.J

"5

5

200

oct

Tachometer Linearity
vs Temperature

Vee: 12V

0.&

:

ZI~

SUPPLY VOLTAGE (VI

10

C>

~

6 8 10 12 14 16 18 20 22 24 26 28

Tachometer Linearity
vs Temperature

'"
'"'"

p..-V'

1'0

TEMPERATURE '-CI

!!

Z6D
240

~ Z20

Z5'C~ lSOC

200

'"

I'.

1/

~ 0.99&

:; 0.994

ZS

280

il'

~

.3 ZZD

~a.gg8

5

Tachometer Currents 12
and 13 vs Temperature

210
FREQUENCY" ZOD Hz

~ 1.IDO

~

TEMPERATURE ('C)

51.00&

,. 1.002

~

0.992
~ 0.990
-J5 -15

Normalized Tachometer
Output vs Temperature
~ 1.001

LM2911141D!l)

~

SUPPLY VOL TAGE tV)

g

,

LM29077 ~

~

1.46

& 8 18 12 14 16 I. 20 22 24 26 28

1.000

~ D.991

1.48

o

FRE1QUENCV .. 1000 Hr

~ 1.006

7.&0

~ 7.58
~ 1.56
>
a: 7.54
z 7.52

~I::= 1"'' ""

~ 1.008

~

1.6Z

50

~

~

y.~
~

.........

~~
~
10

20

JD

40

SO

SINK CURRENT {mAl

TLfH17942-5

5-199

~
.,...

en
N
:E
...I

......
~

o
en
:E
N

...I

r-----------------------------------------------------------------Applications Information
The LM2907 series of tachometer circuits is designed for
minimum external part count applications and maximum versatility. In order to fully exploit its features and advantages
let's examine its theory of operation. The first stage of operation is a differential amplifier driving a positive feedback
flip-flop circuit. The input threshold voltage is the amount of
differential input voltage at which the output of this stage
changes state. Two options (LM2907-8, LM2917-8) have
one input internally grounded so that an input Signal must
swing above and below ground and exceed the input
thresholds to produce an output. This is offered specifically
for magnetic variable reluctance pickups which typically provide a single-ended ac output. This single input is also fully
protected against voltage swings to ±28V, which are easily
attained with these types of pickups.

The size of C2 is dependent only on the amount of ripple
voltage allowable and the required response time.
CHOOSING R1 AND C1

There are some limitations on the choice of R1 and C1
which should be considered for optimum performance. The
timing capacitor also provides internal compensation for the
charge pump and should be kept larger than 500 pF for very
accurate operation. Smaller values can cause an error current on R1, especially at low temperatures. Several considerations must be met when choosing R 1. The output current
at pin 3 is internally fixed and therefore Vo/R1 must be less
than or equal to this value. If R 1 is too large, it can become
a Significant fraction of the output impedance at pin 3 which
degrades linearity. Also output ripple voltage must be considered and the size of C2 is affected by R1. An expression
that describes the ripple content on pin 3 for a single R 1C2
combination is:

The differential input options (LM2907, LM2917) give the
user the option of setting his own input switching level and
still have the hysteresis around that level for excellent noise
rejection in any application. Of course in order to allow the
inputs to attain common-mode voltages above ground, input
protection is removed and neither input should be taken
outside the limits of the supply voltage being used. It is very
important that an input not go below ground without some
resistance in its lead to limit the current that will then flow in
the epi-substrate diode.

Vee
VRIPPLE = - -

2

.

Ic(AVG) = C1

x

Vee

"'2 x

(2fIN)

= Vee

x

x

fiN X C1 X R1

x

x

2

fiN X C1)

12

pk-pk

As a final consideration, the maximum attainable input frequency is determined by Vee, C1 and 12:
f

MAX -

12

C1 X Vee

USING ZENER REGULATED OPTIONS (LM2917)

For those applications where an output voltage or current
must be obtained independent of supply voltage variations,
the LM2917 is offered. The most important consideration in
choosing a dropping resistor from the unregulated supply to
the device is that the tachometer and op amp Circuitry alone
require about 3 rnA at the voltage level provided by the
zener. At low supply voltages there must be some current
flowing in the resistor above the 3 rnA circuit current to operate the regulator. As an example, if the raw supply varies
from 9V to 16V, a resistance of 470n will minimize the zener voltage variation to 160 mV. If the resistance goes under 400n or over 600n the zener variation quickly rises
above 200 mV for the same input variation.

fiN X C1

The output circuit mirrors this current very accurately into
the load resistor R 1, connected to ground, such that if the
pulses of current are integrated with a filter capacitor, then
Vo = ic x R1, and the total conversion equation becomes:
Va = Vee

C1
(
Vee
-C X 1 -

It appears R1 can be chosen independent of ripple, however response time, or the time it takes VOUT to stabilize at a
new voltage increases as the size of C2 increases, so a
compromise between ripple, response time, and linearity
must be chosen carefully.

Following the input stage is the charge pump where the
input frequency is converted to a dc voltage. To do this
requires one timing capacitor, one output resistor, and an
integrating or filter capacitor. When the input stage changes
state (due to a suitable zero crossing or differential voltage
on the input) the timing capacitor is either charged or discharged linearly between two voltages whose difference is
Vee/2. Then in one half cycle of the input frequency or a
time equal to 1/2 fiN the change in charge on the timing
capaCitor is equal to Vee/2 x C1. The average amount of
current pumped into or out of the capaCitor then is:
IlQ
T
=

x

K

Where K is the gain constant-typically 1.0.

Typical Applications
Minimum Component Tachometer
Vee

~

15V

+VOUT = 67 HIIV

'IN1RPMI

TLlH17942-8

5-200

Typical Applications

rii5:
N
co

(Continued)

"Speed Switch" Load is Energized When fiN
5k

5k

;0;

o
......

1
2RC

.....- - - - - - - -....--0 vee

rii5:

~ 6-24V

N
CO

.....
......

TLlH17942-9

Zener Regulated Frequency to Voltage Converter

vee

~

12V

+ VOUT

~

66 H,/V

10k

TLlH17942-10

Breaker Point Dwell Meter
B+~------t~--------.----,
10k

470

5k

POINTS

+---.,

GROUNO~

10k

TLlH17942-11

5-201

Typical Applications

(Continued)
Voltage Driven Meter Indicating Engine RPM
Vo = 6V @ 400 Hz or 6000 ERPM (8 Cylinder Engine)

B+o-----_1~----------_1~--------------_1~--~
410

DISTRIBUTOR

r

10k

+

~REAKER \ .

1

POINTS

VOUT

TL/H17942-12

Current Driven Meter Indicating Engine RPM
10 = 10 mA @ 300 Hz or 6000 ERPM (6 Cylinder Engine)
B+o-------~----------------~----,
10k

11

12

BREAKER
POINTS

10k

TL/H17942-13

VOUT

=

Capacitance Meter
1V-10V for Cx = 0.01 to 0.1 mFd
(R = 111k)
ISV

+

Sk

TL/H/7942-14

5-202

Typical Applications

(Continued)
Two-Wire Remote Speed Switch

~----~~----------------OGND

T

T
TL/H/7942-15

100 Cycle Delay Switch

v,,

V3

va steps up in voltage by the amount

Vee x C1
----c2

100

NO.

OF CYCLES

for each complete input cycle (2 zero crossings)

TLlH/7942-16

Example:
If C2 = 200 C1 after 100 consecutive input cycles.
V3 ~ 1/2 Vee

5-203

.....
.....
Q)
C'I

:E

Typical Applications (Continued)

....I

Variable Reluctance Magnetic Pickup Buffer Circuits

......
.....
o

Precision two-shot output frequency
equals twice input frequency.

C'I

Pulse width =

Q)

:E
....I

Pulse height

Vee~.
2

12

= VZENER
VARIABLE
RELUCTANCE

VARIABLE
RELUCTANCE

MAG.ETIC
L..r.---t.-----t;-_+._'
PICKUP",", 1

~
(())

C1

10k

":"SOOPFT
INPUT CAN BE
'20 mV TO '2av

~
(())

JlJill

MAGNETIC

PICKUP

"""V

1

':"
TL/H17942-39
TL/H17942-17

Finger Touch or Contact Switch
r-------------------9-------~~T01~V

o

INPUT
(60 Hzl
CONTACT
PLATE

o

TL/H/7942-19

TL/H/7942-18

Flashing LED Indicates Overspeed
---t~--------------~~--014V

430

68

1~0

Flashing begins when fiN ;" 100 Hz.

/l;

Flash rate increases with input frequency
increase beyond trip point.

LEO

TL/H/7942-20

5-204

Typical Applications

.-s:

(Continued)

I\)

CD

o
......

Frequency to Voltage Converter with 2 Pole Butterworth Filter to Reduce Ripple

.--.....s:

vee

I\)

..........
CD

T

0.707
fpOLE = 27rRC

2.57
'RESPONSE

=

R

21TfpOLE

+

2C
10k

VOUT

TL/H/7942-21

Overspeed Latch
Vee

Output latches when

-=

r

IC

f

IN - Rl

+

R

R2

+

1
R2RC

Reset by removing Vee.

O

-=

_

•

TL/H/7942-22

5-205

TL/H/7942-23

.....,...
~

Typical Applications

::::!E
..J

(Continued)

Some Frequency Switch Applications May Require Hysteresis in the
Comparator Function Which can be Implemented in Several Ways:

......
....
o

llY

CD
C'I

::::!E
..J

10k

'Y'

10k

LED

I,"
100k

Ja.4M
TL/H17942-24

llY

VR£F "6V

12V

+
VOUT

I,"

I

TUHI7942-25

TLlH17942-26

VOUT

VOUT

I

la.5~-"""r""\

llY

0.1 t::=~===i
5.94 6.06

V3

__
V3

TL/H17942-27

TLlH/7942-28

5-206

r-

Typical Applications

3:
co
o
......
.......
r3i:
N
co

(Continued)

N

Changing the Output Voltage for an Input Frequency of Zero

...-------0

10V

..........

VOUT

f'No---..1

""'T

+
10k VauT

lOOk
1

2

J

4

5

6

J

fiN 1kHz)

TL/H17942-30

200

TL/H17942-29

Changing Tachometer Gain Curve or Clamping the Minimum Output Voltage
10V

91k
VOUT
8V

JV

1------2tr

2V I---~".r

lV
f'No---~

VOUT
fiN 1kHz)
TL/H/7942-32

10k

TL/H/7942-31

5·207

Anti-Skid Circuit Functions
"Select-Low" Circuit
vcco-------------------------~----------------------------_,
WHEEL

I:~U~

0-------------------------+----------,

WHEEL SPEED

TL/H17942-34
lk

r-~~~----~.r----~~~--------+_------------.+
lk

Vour

VOUT is proportional to the lower of the
two input wheel speeds.

~TLlH17942-33

"Select-High" Circuit

vcco-------------------______~----------------------------_,
WHEElI~~U~

0-------------------------+-------__--,
VOUT

WHEEl SPEED

TL/H17942-36
VOUT is proportional to the higher of

~-

the two input wheel speeds.

TL/H17942-35

"Select-Average" Circuit

va'o---------------------------t-------------__________________,
f,o---------------____________+-__________-,
f,o----------+----,

p

c

TLlH17942-37

5-208

m

.Q
BIAS

r;:,--------------,
OP AMP COI\,PARATOR

r-------,
I

10

I

,

,

~9

,

"',

:;::'
SI)

1

ii'
j

1

1

e(')n

I

I
I

034

I
I
I

C

I

«;I.bk

'"

0:,-

"::"

1
1
1
1

:::r
(1)
3

a-

(;'

L.."::: __ ..J

e

Di'
ce

I

~

I

SI)

3

'"~
CO

0121

oill
1
1

1

I

"::"

~~DI
-

INPUT :VSTEruIS A";;L;;;R -

-

-II
IL

__________

_____

~

~

____

~

CHARGE PUMP

TLlH/7942-38

'This connection made on LM2907-8 and LM2917-8 only.
"This connection made on LM2917 and LM2917·8 only.

l ~6~W'/106~W'

iii

(D ~-------------------------------------------------------------------------------,

CD

o

('I)

:e
....I

U)

NatiOnal

~ Semiconductor
Corporation

g
:e
LM3045/LM3046/LM3086 Transistor Arrays
....I
('I)

;:n
00:1'

o

('I)

:e
....I

General Description

Features

The LM3045, LM3046 and LM3086 each consist of five
general purpose silicon NPN transistors on a common
monolithic substrate. Two of the transistors are internally
connected to form a differentially-connected pair. The transistors are well suited to a wide variety of applications in low
power system in the DC through VHF range. They may be
used as discrete transistors in conventional circuits however, in addition, they provide the very significant inherent integrated circuit advantages of close electrical and thermal
matching. The LM3045 is supplied in a 14-lead cavity dualin-line package rated for operation over the full military temperature range. The LM3046 and LM3086 are electrically
identical to the LM3045 but are supplied in a 14-lead molded dual-in-line package for applications requiring only a limited temperature range.

• Two matched pairs of transistors
VBE matched ± 5 mV
Input offset current 2 /kA max at Ie = 1 mA
• Five general purpose monolithic transistors
• Operation from DC to 120 MHz
• Wide operating current range
• Low noise figure
3.2 dB typ at 1 kHz
• Full military
temperature range (LM3045)
- 55'C to + 125'C

Applications
• General use in all types of signal processing systems
operating anywhere in the frequency range from DC to
VHF
• Custom designed differential amplifiers
• Temperature compensated amplifiers

Schematic and Connection Diagram
Dual-In-Line and Small Outline Packages
SUBSTRATE

14

13

12

11

10

Q3

Tl/H17950-1

Top View
Order Number LM3045J, LM3046M, LM3086M, LM3046N or LM3086N
See NS PaCkage Number J14A, M14A or N14A

5-210

Absolute Maximum Ratings

(TA = 25·C)

If Military/Aerospace specified devices are required, contact the National Semiconductor Sales Office/Distributors for
availability and specifications.
LM3045
LM3046/LM3086
Each
Total
Each
Total
Units
Transistor
Package
Transistor
Package
Power Dissipation:
TA = 25·C
300
750
300
750
mW
T A = 25·C to 55·C
300
750
mW
TA> 55·C
Derate at 6.67
mWI"C
T A = 25·C to 75·C
300
750
mW
TA> 75·C
mWI"C
Derate at 8
Collector to Emitter Voltage, VCEO

15

15

V

Collector to Base Voltage, VCSO

20

20

V

Collector to Substrate Voltage, VCIO (Note 1)

20

20

V

5

5

V

50

50

mA

Emitter to Base Voltage, VESO
Collector Current, Ic
Operating Temperature Range

- 55·C to

Storage Temperature Range

- 65·C to

Soldering Information
Dual·ln·Line Package Soldering (10 Sec.)

+ 125·C
+ 150·C

-40·Cto
-65·Cto

260·C

+ 85·C
+ 85·C

260·C

Small Outline Package
Vapor Phase (60 Seconds)
215·C
Infrared (15 Seconds)
220·C
See AN·450 "Surface Mounting Methods and Their Effect on Product Reliability" for other methods of soldering surface mount
devices.

Electrical Characteristics (TA =
Parameter

25·C unless otherwise specified)

Conditions

Limits

Limits

LM3045, LM3046

LM3086

Min

Typ

Max

Min

Typ

Units
Max

Collector to Base Breakdown Voltage (VCSRICSO)

Ic = 10 /LA, IE = 0

20

60

20

60

V

Collector to Emitter Breakdown Voltage (V(SR)CEO)

Ic=1mA,ls=0

15

24

15

24

V

Collector to Substrate Breakdown
Voltage (V(SR)CIO)

Ic = 10 /LA, ICI = 0

20

60

20

60

V

Emitter to Base Breakdown Voltage (V(BR)EBO)

IE 10 /LA,IC = 0

Collector Cutoff Current (icso)

VCS = 10V,IE = 0

Collector Cutoff Current (ICEO)

VCE = 10V,Is = 0

Static Forward Current Transfer
Ratio (Static Beta) (hFE)

VCE = 3V

{IC= 10mA
Ic=1mA
Ic = 10 /LA

Input Offset Current for Matched
Pair Ql and Q21101 - 11021

VCE = 3V, Ic = 1 mA

Base to Emitter Voltage (VSE)

VCE = 3V

{IE = 1 mA
IE = 10mA

Magnitude of Input Offset Voltage for
Differential Pair IVSEl - vSE21

VCE = 3V, Ic = 1 mA

Magnitude of Input Offset Voltage for Isolated
Transistors IVsE3 - VSE41,IvSE4 - vSEsI,
IVSES - VSE31

VCE = 3V, Ic = 1 mA

Temperature Coefficient of Base to
Emitter Voltage
~~E)

VCE = 3V, Ic = 1 mA

(.

400

C>
2

:.\

~,

Ie -1 mA

.JJ

JOO

~

r0-

il

200
100

.!:
10

I-

Vee

r- TA "25"C

600

~

".,

TA =25·C
VeE =3V

aDo
100

100

1

FREQUENCY IMHzl

2

J

•

5

6

1

agIO

Ie - CDLlECTDR (mAl

TL/H/7950-7

5-214

NatiOnal

~ Semiconductor
Corporation

LM3146 High Voltage Transistor Array
General Description

Features

The lM3146 consists of five high voltage general purpose
silicon NPN transistors on a common monolithic substrate.
Two of the transistors are internally connected to form a
differentially-connected pair. The transistors are well suited
to a wide variety of applications in low power system in the
dc through VHF range. They may be used as discrete transistors in conventional circuits however, in addition, they
provide the very significant inherent integrated circuit advantages of close electrical and thermal matching. The
lM3146 is supplied in a 14-lead molded dual-in-line package for applications requiring only a limited temperature
range.

• High voltage matched pairs of transistors, VSE matched
± 5 mV, input offset current 2 /LA max at Ie = 1 mA
• Five general purpose monolithic transistors
• Operation from dc to 120 MHz
• Wide operating current range
• low noise figure
3.2 dB typ at 1 kHz

Applications
• General use in all types of signal processing systems
operating anywhere in the frequency range from dc to
VHF
• Custom designed differential amplifiers
• Temperature compensated amplifiers

Connection Diagram
Dual-In-line and Small Outline Packages
SUBSTRATE

14

13

12

11

10

Q3

TL/H/7959-1

Top View
Order Number lM3146M or lM3146N
See NS Package Number M14A or N14A

5-215

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
LM3146

Units

Power Dissipation: Each transistor
TA = 25'C to 55'C
TA> 55'C

300
mW
Derate at 6.67 mWrC

Power Dissipation: Total Package
TA = 25'C
TA> 25'C

500
mW
Derate at 6.67 mWrC

Collector to Emitter Voltage, VCEO

30

Collector to Base Voltage, VCBO

40

V
V

Collector to Substrate Voltage,
VCIO (Note 1)

40

V

Emitter to Base Voltage, VEBO
(Note 2)

5

V

Collector to Current, Ic
Operating Temperature Range

50

mA

-40 to +85

'c

Storage Temperature Range

-65 to +150

'C

DC Electrical Characteristics TA =
Symbol

Soldering Information
Dual-In-Line Package
Soldering (10 seconds)

260'C

Small Outline Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

215'C
220'C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

25'C

Parameter

Limits

Conditions
Min

Typ

Units
Max

V(BR)CBO

Collector to Base Breakdown Voltage

Ic = 10 /LA, IE = 0

40

72

V

V(BR)CEO

Collector to Emitter Breakdown Voltage

Ic = 1 mA, IB = 0

30

56

V

V(BR)CIO

Collector to Substrate Breakdown
Voltage

ICI = 10 /LA. IB = 0,
IE =0

40

72

V

V(BR)EBO

Emitter to Base Breakdown Voltage
(Note 2)

Ic = 0, IE = 10 /LA

5

7

V

ICBO

Collector Cutoff Current

VCB = 10V, IE = 0

0.002

100

nA

ICEO

Collector Cutoff Current

VCE = 10V,IB = 0

(Note 3)

5

/LA

hFE

Static Forward Current Transfer
Ratio (Static Beta)

Ic = 10mA, VCE = 5V
Ic = 1 mA, VCE = 5V
Ic = 10 /LA, VCE = 5V

Input Offset Current for Matched
Pair 01 and 02

IC1 = 1C2 = 1 mA,
VCE = 5V

0.3

2

/LA

0.73

0.83

V

0.48

5

mV

IB1- IB2
VBE

Base to Emitter Voltage

Ic = 1 mA, VCE = 3V

VBE1-VBE2

Magnitude of Input Offset Voltage
for Differential Pair

VCE = 5V, IE = 1 mA

6.VBE/6.T

Temperature Coefficient of Base
to Emitter Voltage

VCE = 5V, IE = 1 mA

VCE(SAD

Collector to Emitter Saturation
Voltage

Ic = 10 mA, IB = 1 mA

6.V10/ 6.T

Temperature Coefficient of Input
Offset Voltage

Ic = 1 mA, VCE = 5V

30

0.63

85
100
90

-1.9

mVrC

0.33

V

1.1

/LvrC

Note 1: The collector of each transistor is isolated from the substrate by an integral diode. The substrate must be connected to a voltage which is more negative

than any collector voltage in order to maintain isolation between transistors and provide normal transistor action. To avoid undesired coupling between transistors,
Ihe subSlrale lerminal should be maintained al eilher de or signal (ac) ground. A suilable bypass capacilor can be used 10 establish a signal ground.
Note 2: If the transistors are forced into zener breakdown (V(BR)EBol, degradation of forward transfer current ratio (hFE> can occur.

Nole 3: See curve.

5-216

AC Electrical Characteristics
Symbol

Parameter

Limits

Conditions

Typ

Min
NF

Low Frequency Noise Figure

I = 1 kHz, VeE = 5V,
Ic = 100 fLA, Rs = 1 kfl

IT

Gain Bandwidth Product

VCE

CES

Emitter to Base Capacitance

VES

CCS

Collector to Base Capacitance

CCI

Collector to Substrate Capacitance

=

5V, Ic

=

300

3 rnA

= 5V, IE = 0
VCS = 5V, Ic = 0
VCI = 5V, Ic = 0

Units
Max

3.25

dB

500

MHz

0.70

pF

0.37

pF

2.2

pF

Low Frequency, Small Signal Equivalent Circuit Characteristics

= 1 kHz, VCE
= 1 kHz, VCE
I = 1 kHz, VeE
I = 1 kHz, VCE
Ic = 1 rnA

hIe

Forward Current Transler Ratio

I

hie

Short Circuit Input Impedance

I

hoe

Open Circuit Output Impedance

h,e

Open Circuit Reverse Voltage
Transler Ratio

=
=
=
=

3V, Ic
3V, Ic
3V, IC

=
=
=

1 rnA

100

1 rnA

3.5

kfl

15.6

fLmho

1 rnA

1.8 x 10- 4

3V,

Admittance Characteristics
Vie

Forward Transler Admittance

I

Vie

Input Admittance

I

Voe

Output Admittance

I

Reverse Transfer Admittance

f

=
=
=
=

1 MHz, VCE
1 MHz, VCE
1 MHz, VeE

=
=
=
=

3V, Ic
3V, Ic
3V, Ic

=
=
=
=

1 rnA

31 - j 1.5

mmho

1 rnA

+ jO.04
0.001 + j 0.03

mmho

1 rnA

0.3

mmho

mmho
(Note 3)
1 MHz, VCE
3V, Ic
1 rnA
Note 1: The collector of each transistor is isolated from the substrate by an integral diode. The substrate must be connected to a voltage which is more negative

V,e

than any collector voltage in ord'er to maintain isolation between transistors and provide normal transistor action. To avoid undesired coupling between transistors,
the substrate terminal should be maintained at either de or signal (ae) ground. A suitable bypass capacitor can be used to establish a signal ground.
Note 2: If the transistors are forced into zener breakdown (V(BR)ESo). degradation of forward transfer current ratio (hFE) can occur.
Note 3: See curve.

5-217

CD

"0:1"

~
::!

Typical Performance Characteristics

...J

ICEO vs TA for
Any Transistor

!....

10'

~

10'

!.

18 -0

ill

ICBO vs TA for
Any Transistor

102

~

140

~

.~
...,

~

~:::

VeE" IOV

10 '

I

0

.:; 10'

0

25
TA

-

75

50

100

125

AMBIENT TEMPERATURE I C)

.

~

0.8

~
.,

0.7

!

0.6

~~

....

VeE "'5V

.

~

f!~

....
.,.... "
"'"
:i~

~ ~'3mA
IE"I~ ~

0.75
0.5

~

~ffi
>::

-75 -50 -25

25

50

4

I

VeE" 5V

.....

~

V

l....

~

FE =10

*
~

;!

0.15

lJA

~ 0.50

i.--"

VeE

.
cO

i"""

25

50

I-

40

0.01

75 100 125

TA - AMBIENT TEMPERATURE I'CI

c::r

5-

I--'

,,2
-~

,,!;

z.,

I

.,~

e;:;

a~

S;§

INPUT OFFSET VOLTAGE

~

---rtlt1mi IV!"'I' Ii ~i~

OA
0.01

10

NF vs IC

1
0.5

0.1
Ie - COLLECTOR CURRENT ImAI

@

RS =

soon

3D

I
.1

0.6

:
,:

I
0

0.7

ill

:;;

-sv

TA " 25°C

~

~

0.1 mA

-75 -50 -25

3D

20

Ie - COLLECTOR CURRENT ImAI

I

J 0.25

0.1

I
0

0.01
10

O.B

I

.,

o

ILh
V

VBE and VIO vs
IE for Q1 and Q2

Ie S'OjA

Ic (Q1 and Q2)

025

TA - AMBIENT TEMPERATURE rCI

~....

110 VS

V

75 100 125

VIO VS TA for Q1 and Q2

10

Ie - COLLECTOR CURRENT ImAI

~

0.4

0.1

10

1.0

.

I

111

Jill

20
0.01

I

fA = 25°C

1.25

.:Ii

85
-"....

0.5

1.5

25'C

-SS'C

"

125

ill

40

VCE(SAT) vs Ic
for Any Transistor

I

~

100

60

TA - AMBIENT TEMPERATURE I CI

VBEvsTA for
Any Transistor
0.9

75

25

-

80

;.,

10'

lllllI

TAill'C~

100

I

5V

VeE =5V

120

....
~

..~

I

160

~

!!

10

.,

hFE vs Icfor
Any Transistor

"~

.."
'"
isz

TA = 25°C

20
15
'=0.1 kHz

~

10

~

"

0.01

I-"

1 kHz
10kHz

o
10

Ie - EMITTER (mAl

25
m

~

J 11111111 J WllliL
0.1

Vee" 5V
Rs = SOOn

0.1
Ie - COLLECTOR ImAI

TLlH17959-2

5-218

Typical Performance Characteristics
NF vs Ie @ Rs = 1 kO
30

NFvsle = RS = 10kO

'---'TT-rrmr-,-rrrrrm

30
VeE::II 5V
Rs" 10,DODH

VeE" 5V

25

;;;
:!!

R, • 1000n t-H-tft-++-If-H-ttti
TA

"

(Continued)

25'C

25

;;;

201--+++t+tt-H--H+l+I-lII

TA • 25'c I I

:!!

20

'""
'"

..

15

i5z

10

1 kHz

~

~

----

0.01

Ie - COLLECTOR CURRENT {mAl

.'"

,/

o

0.1

10

\; 0.10H,/

'm

,

-I i

Ie - COLLECTOR CURRENT (mAl

If - COLLECTOR CURRENT {mAl

Voe vsf

Vie vsf

Vfe VS f

II

g,.

.....

TA, "'" 25 C
VeE = SV

Til." 2S C
VeE" 5V

Ie -I mA

Ie'" 1 rnA

I

10

0.1

0.1

Til. 2SlC

I

II

VeE" 3V
Ie" 1 mA

inL

,

I"

~

j'i

Ii

IIIII

o

100

10

0.1

100

•- fREQUENCY IMHz}

b•

.J

I

~~

1.0::;

10

i

i
I

o

j

...

ko::

0.1

.00

10

t - FREQUENCY (MHz)

I-FREQUENCY (MHz)

CEB. CCB. CCI vs Bias
~

e" s
si

1.0

z

0.5

~. !s W!!I~T fJEJJE~IJWL
LESS THAN 500 MHz \

8:
~!

i~
:: ~
w,

~w

~

-0.5
-1.0

~ ~ -1.5

'"

Voltage

V.e VS f

i

I...
'"

~
z
Z

~,
.:

VeE" 5V

Ie "', rnA

-2.0
10
f-

100

fREQUENCY IMHz)

Til. = 25'C

VeE = 5V
TA ;; 25' C

;g 100

:;
Til. = 25'C

800

600

400
300

.......

-r--

i-'"

500

..... ~'

(
Cn

200

..... J:-r-

100

o
1

2

3

4

5

6

1

Ie - COLLECTOR (mA)

8

9 10

o

1

2

3 4

5

6

1

teB

f-

8

9 10

81AS VOLTAGE IV)

TUH/7959-3

5-219

en
o
en
('I)
:::!il

....I

r----------------------------------------------------------------------------,
NatiOnal

~ Semiconductor
Corporation

LM3909 LED Flasher/Oscillator
General Description

Features

The LM3909 is a monolithic oscillator specifically designed
to flash Light Emitting Diodes. By using the timing capacitor
for voltage boost, it delivers pulses of 2 or more volts to the
LED while operating on a supply of 1.5V or less. The circuit
is inherently self-starting, and requires addition of only a battery and capacitor to function as an LED flasher.

•
•
•
•
•
•

Packaged in an B-Iead plastic mini-DIP, the LM3909 will operate over the extended consumer temperature range of
- 25'C to + 70'C. It has been optimized for low power drain
and operation from weak batteries so that continuous operation life exceeds that expected from battery rating.
Application is made Simple by inclusion of internal timing
resistors and an internal LED current limit resistor. As
shown in the first two application circuits, the timing resistors supplied are optimized for nominal flashing rates and
minimum power drain at 1.5V and 3V.
Timing capacitors will generally be of the electrolytic type,
and a small 3V rated part will be suitable for any LED flasher
using a supply up to 6V. However, when picking flash rates,
it should be remembered that some electrolytics have very
broad capacitance tolerances, for example - 20% to
+100%.

Operation over one year from one C size flashlight cell
Bright, high current LED pulse
Minimum external parts
Low cost
Low voltage operation, from just over 1V to 5V
Low current drain, averages under 0.5 mA during
battery life .
• Powerful; as an oscillator directly drives an Bn speaker
• Wide temperature range

Applications
• Finding flashlights in the dark, or locating boat mooring
floats
• Sales and advertising gimmicks
• Emergency locators, for instance on fire extinguishers
• Toys and novelties
• Electronic applications such as trigger and sawtooth
generators
• Siren for toy fire engine, (combined oscillator, speaker
driver)
• Warning indicators powered by 1.4V to 200V

Schematic Diagram

Connection Diagram

Typical1.5V Flasher

RLiM

r---------,

Dual-In-Line Package

v'

SLOW
RC
9k

NC

•
3k

OUT

FAST
RC
TL1H17969-2

Top View
Order Number LM3909N
See NS Package Number NOSE

3k

L. _ _ _ _ _ _ _ _ _ .J
TLlH/7969-1

5-220

ris:

Absolute Maximum Ratings

Co)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Dissipation
500mW
V+ Voltage
6.4V

Operating Temperature Range
Lead Temperature (Soldering, 10 sec.)

- 25·C to

+ 70·C
260·C

Electrical Characteristics
Conditions
(Applications Note 3)

Parameter
Supply Voltage

Min

Typ

Max

Units

6.0

V

0.55

0.75

mA

1.0

1.3

(In Oscillation)

1.15

Flash Frequency

300 p.F, 5% Capacitor

0.65

High Flash Frequency

0.30 p.F, 5% Capacitor

Compatible LED Forward Drop

1 mA Forward Current

Peak LED Current

350 p.F Capacitor

45

mA

Pulse Width

350 p.F Capacitors at y. Amplitude

6.0

ms

Operating Current

1.1
1.35

2.1

Typical Applications (See applications notes on following page)
Triac Trigger

I
... .".
COM
3.3

~:+
I.F

75

:bB
O.OI5pF

\6

17

5
Provides 40 rnA. 10 I's pulses at about 8 kHz.
Triac gate may be pulse transformer isolated if

desired.

LM3909
Ik

I'

12

13

4

-1.4V FROM BATTERY OR
SOLAR CelL WITH SpF
BYPASS CAPACITOR. DRAIN
NOMINAll Y 5 mAo

5-221

Hz
kHz

TL/H17969-3

V

<0

o

<0

en
C
en
C')
:!i

-l

r---------------------------------------------------------------------------------,
Typical Applications (Continued)(See applications notes below)
Warning Flasher High Yoltage Powered

Rs

Typical Operating Conditions

~

Y+

Nominal
Flash Hz

CT

Rs

RFB

Y+RANGE

6V
15V

2
2

400",F
180 ",F

1.5k
1k

5V-25V
13V-50V

100V

1.7

180 ",F

1k
3.9k
43k
1W

1k

85V-200V

LM3909

TLlH17969-4

1.SY Flasher
0.7

..,-

0.6

::<
.§
z

0.5

....E

0.4

~

'"u
;;:

LM3909

+

1.5V

,

0.3

>
....

V

/

./

~

0.2
0.1
1.0

1.1

1.2

1.3

1.4

1.5

1.6

BATTERY VOLTAGE (VI
TLlH17969-6

Estimated Battery Life
(Continuous 1.SY Flasher Operation)
TL/H17969-5

Type

Size Cell

Note: Nominal flash rate: 1 Hz.

AA
C
D

Standard

Alkaline

3 months
7 months
1.3 years

6 months
15 months
2.6 years

Note: Estimates are made from our tests and manufacturers
data. Conditions are fresh batteries and room temperature. Clad
or "Ieak.proof" batteries are recommended for any application
of five months or more. Nickel Cadmium cells are not recommended.
APPLICATIONS NOTES
Note 1: All capacitors shown are electrolytic unless marked otherwise.

Note 2: Flash rates and frequencies assume a ±5% capacitor tolerance. Electrolytics may vary -20% to

+ 100% of their stated value.

Note 3: Untess noted. measurements above are made with a l.4V supply, a 2S'C ambient temperature, and an LED with a forward drop of 1.SV to 1.7V at 1 mA
forward current.
Note 4: Occasionally a flasher circuit will fail to oscillate due to an LED defect that may be missed because it only reduces light output 10% or so. Such LEOs can
be identified by a large increase in conduction between O.9V and 1.2V.

5-222

r

Typical Applications

s::
~

(Continued) (See applications notes on previous page)

3V Flasher

CD

o

Minimum Power at 1.5V

CD

NSLSOB2

NSlS027

LMJ909

-=-+

+

LMJ909

l.SV

JV

10DpF

JOOpF
JV

TLlHI7969-B
Note: Nominal flash rate: 1.1 Hz. Average IORAIN~O.32 mAo

TLIH17969-7
Note: Nominal flash rate: 1 Hz. Average IORAIN~O.77 mAo

Fast Blinker

TRANSLUCENT

LMJ909

------------~~~~~~
o D
l~<-

+
1.SV

TLlH17969-11

Note: Winking LED inside, locates light in total darkness.

lk

JOOpF

TLlH17969-9
Note: Nominal flash rate: 2.6 Hz. Average lORAIN ~ 1.2 mA.

LI
5-223

en

C)

~

Typical Applications (Continued) (See applications notes above)

:5

Flashlight Finder

...I

o

" ' - SHORT l-B FOR
SINGLE CELL LIGHTS
CONTACT STRIP, PASSES
(INSULATED) THROUGH
CASE BOTTOM

\
RING CONTACT ON
BULB ASSEMBL Y

TL/H17969-10

Note: LM3909, capacitor, and LED are installed in a white translucent cap on the flashlight's back end. Only one
contact strip (in addition to the case connection) is needed for flasher power. Drawing current through the bulb
simplifies wiring and causes negligible loss since bulb resistance cold is typically less than 2f1.

4 Parallel LEOs

~

High Efficiency Parallel Circuit

0

39
NSL50210R
NSL002 OR
NSL5024

39

~

39

0

39

~

39

~

39

~

39

+

~

1.5V

39

+

200

1.5V

200

lM3909

LM3909

4

150

5000vF
3V

TUH/7969-12

TL/H/7969-13

Note: Nominal flash rate: t.3 Hz. Average IDRAIN ~ 2 rnA.

Note: Nominal flash rate: 1.5 Hz. Average IDRAIN ~ 1.5 rnA.

5·224

r-

Typical Applications

s:

(Continued) (See applications notes above)

Co)

CD

o

1 kHz Square Wave

CD

1.2
1.0

.

~

SYMMETRY
10k

O.2~F

r

w

«

:;

LMJ909

0.8

0

0.6

~

0.4

...'"

...=>
0

+

0.2

t.5V

r- f01

r- f-"
m.

2m.
TLlH/7969-15

OUT

Note: Output voltage through a 10k load to ground.
TL/H/7969-14

"Buzz Box" Continuity and Coil Checker

Variable Flasher

~12-16n

o

SPEAKER
NSLS021

I
I

TEST
PROBES

lk

LMJ909

+
TLlHI7969-17
Note: Flash rate: 0 Hz-20 Hz.
1.5V

TLlH/7969-16

Note: Differences between shorts, coils, and a few ohms of resistance can be
heard.

5-225

Typical Applications

(Continued) (See applications notes above)

Incandescent Bulb Flasher

LED Booster

+6V

lM3909
lM3909

+

1.5V

#47

TLlH17969-18

Nole: High efficiency, 4 mA drain. Continuous appearing light obtained by supplying
shorl, high current, pulses (2 kHz) to LEOs with higher than battery voltage available.

TLlH17989- t 9

Nole: Flash rate: 1.5 Hz.

Emergency Lantern/Flasher
75

200~F

3V

PR13

+
LM3909

-=-

6V

TL/H17969-20

Nole: Nominal flash rate: 1.5 Hz.

5-226

NatiOnal

~ Semiconductor
Corporation

LM3914 Dot/Bar Display Driver
General Description
The LM3914 is a monolithic integrated circuit that senses
analog voltage levels and drives 10 LEOs, providing a linear
analog display. A single pin changes the display from a
moving dot to a bar graph. Current drive to the LEOs is
regulated and programmable, eliminating the need for resistors. This feature is one that allows operation of the whole
system from less than 3V.
The circuit contains its own adjustable reference and accurate 1O-step voltage divider. The low-bias-current input buffer accepts signals down to ground, or V-, yet needs no
protection against inputs of 35V above or below ground.
The buffer drives 10 individual comparators referenced to
the precision divider. Indication non-linearity can thus be
held typically to %%, even over a wide temperature range.
Versatility was designed into the LM3914 so that controller,
visual alarm, and expanded scale functions are easily added
on to the display system. The circuit can drive LEOs of many
colors, or low-current incandescent lamps. Many LM3914s
can be "chained" to form displays of 20 to over 100 segments. Both ends of the voltage divider are externally available so that 2 drivers can be made into a zero-center meter.
The LM3914 is very easy to apply as an analog meter circuit. A 1.2V full-scale meter requires only 1 resistor and a
single 3V to 15V supply in addition to the 10 display LEOs. If
the 1 resistor is a pot, it becomes the LEO brightness control. The simplified block diagram illustrates this extremely
simple external circuitry.
When in the dot mode, there is a small amount of overlap or
"fade" (about 1 mY) between segments. This assures that
at no time will all LEOs be "OFF", and thus any ambiguous
display is avoided. Various novel displays are possible.

Much of the display flexibility derives from the fact that all
outputs are individual, OC regulated currents. Various effects can be achieved by modulating these currents. The
individual outputs can drive a transistor as well as a LEO at
the same time, so controller functions including "staging"
control can be performed. The LM3914 can also act as a
programmer, or sequencer.
The LM3914 is rated for operation from O°C to + 70°C. The
LM3914N is available in an 18-lead molded (N) package.
The following typical application illustrates adjusting of the
reference to a desired value, and proper grounding for accurate operation, and avoiding oscillations.

Features
•
•
•
•
•
•
•
•
•
•

Orives LEOs, LCOs or vacuum fluorescents
Bar or dot display mode externally selectable by user
Expandable to displays of 100 steps
Internal voltage reference from 1.2V to 12V
Operates with single supply of less than 3V
Inputs operate down to ground
Output current programmable from 2 mA to 30 mA
No multiplex switching or interaction between outputs
Input withstands ±35V without damage or false outputs
LEO driver outputs are current regulated, open-collectors
• Outputs can interface with TTL or CMOS logic
• The internal 10-step divider is floating and can be referenced to a wide range of voltages

Typical Applications
OV to 5V Bar Graph Meter

r - · t _ - _ -.....-

I

:
I

-_--e-.. . .

- + -....

....

,~ ~,~,N

o--~t_-VLED

LED

LED

I NO.1
I
I

NO.1D

18

17

16

15

..L
2.hF",
I

L

"

13

11

"

10

LM3914

I
:

Note 1: Grounding method is typical of al/ uses.
The 2.2 I'F tantalum or 10 I'F aluminum electrolytiC capaCitor is needed if leads to the LED supply are 6" or longer.

f f,f f,f,{

vL...-Jl

2

y+
3

'"I

ALD

SIG

4

•

------~~
.

m

m

OUT

ADJ

!!.- 7

8

RHI

v+ 6.BV-lav

~

~
Ref Out V = 1.25 (1

"~"'
I

DV-'V

,

MODE

3.83'

SIGNAL
SOURCE

TLlH17970-1

5-227

+

l*)

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Dissipation (Note 5)
Molded DIP (N)

25V

Voltage on Output Drivers

25V

Input Signal Overvoltage (Note 3)
Divider Voltage

+ 150·C
260·C

Plastic Chip Carrier Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

215·C
220·C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

±35V
-100mVtoV+
10mA

Reference Load Current

Electrical Characteristics

Soldering Information
Dual-In-Line Package
Soldering (10 seconds)

1365 mW

Supply Voltage

- 55·C to

Storage Temperature Range

(Note 1)
Conditions (Note 1)

Parameter

Min

Typ

Max

Units

COMPARATOR
Offset Voltage, Buffer and First
Comparator

OV ,;; VRlO = VRHI ,;; 12V,
ILED = 1 mA

3

10

mV

Offset Voltage, Buffer and Any Other
Comparator

OV ,;; VRLO = VRHI ,;; 12V,
ILED = 1 mA

3

15

mV

=

=

Gain (aiLED/aVIN)

IL(REF)

Input Bias Current (at Pin 5)

OV';; VIN ,;; V+ - 1.5V

Input Signal Overvoltage

No Change in Display

2 mA, ILED

3

10 mA

8
25

-35

mA/mV
100

nA

35

V

VOLTAGE-DIVIDER
Divider Resistance

Total, Pin 6 to 4

Accuracy

(Note 2)

8

12

17

kO

0.5

2

%

1.28

1.34

V

VOLTAGE REFERENCE
Output Voltage

0.1 mA ,;; IL(REF) ,;; 4 mA,
V+ = VLED = 5V

Line Regulation

3V,;; V+ ,;; 18V

0.Q1

0.03

%IV

Load Regulation

0.1 mA ,;; IL(REF) ,;; 4 mA,
V+ = VLED = 5V

0.4

2

%

Output Voltage Change with
Temperature

O·C ,;; TA ,;;
V+ = 5V

1.2

+ 70·C, IL(REF) =

1 mA,

%

1
75

Adjust Pin Current

120

",A

mA

OUTPUT DRIVERS

=

=

LED Current

V+

LED Current Difference (Between
Largest and Smallest LED Currents)

VlED

LED Current Regulation

2V ,;; VlED ,;; 17V

VLED

=

5V, IL(REF)

5V

=

ILED
ILED
ILED
ILED

Dropout Voltage

ILED(ON) = 20 mA, VlED
ailED = 2mA

Saturation Voltage

ILED

Output Leakage, Each Collector

(Bar Mode) (Note 4)

=

2.0 mA, IL(REF)

=

5-228

=

=
=

7

10

13

0.12

0.4

20 mA

1.2

3

2 mA

0.1

0.25

20mA

1

3

1 mA

=
=

2mA

5V,

0.4 mA

1.5

mA

mA

V

0.15

0.4

V

0.1

10

",A

Electrical Characteristics (Note 1) (Continued)
Parameter

I

Ct.)

CD

I

Conditions (Note 1)

Min

I

Typ

I

Max

I

Units

10

I

/LA

OUTPUT DRIVERS (Continued)
Output Leakage

SUPPLY CURRENT
Standby Supply Current
(All Outputs Off)

1

(Dot Mode) (Note 4)

l

I

I
I

Pins 10-18
Pin 1

V+

= 5V, IL(REF) = 0.2 mA

V+

= 20V, IL(REF) = 1.0 mA

I
I
I
I

I
60

0.1

I

150

1
I

2.4
6.1

I
I
I
I

450

4.2
9.2

I

I
I

/LA

mA
mA

Note 1: Unless otherwise stated, all specifications apply with the following conditions:
VAEF. VAHI. VALO ,; (V+ - 1.5V)
3 Vee'; v+ ,; 20 Vee
3 Vee'; VLEe ,; V+
OV ,; V,N ,; V+ - 1.5V
-0.015V'; VRLO'; 12 Vee
TA = +25'C, IL(AEF) = 0.2 rnA. VLEe = 3.0V. pin 9 connected to pin 3 (Bar Mode).
-0.015V ,; VAHI ,; 12 Vec
For higher power dissipations, pulse testing is used.
Note 2: Accuracy is measured referred to
significant error.

+ 10.000 VDC at pin 6, with 0.000 VDC at pin 4. At lower full·scale voltages, buffer and comparator offset voltage may add

Note 3: Pin 5 input current must be limited to ±3 rnA. The addition of a 39k resistor in series with pin 5 allows ± 100V signals without damage.
Nole 4: Bar mode results when pin 9 is within 20 mV of V+. Dot mode results when pin 9 is pulled at least 200 mV below V+ or left open circuit. LED No. 10 (pin 10
output current) is disabled if pin 9 is pulled 0.9V or more below VLEe.
Note 5: The maximum junction temperature of the LM3914 is 100°C. Devices must be derated for operation at elevated temperatures. Junction to ambient thermal
resistance is 55'C/W for the molded DIP (N package).

Definition of Terms
LED Current Regulation: The change in output current
over the specified range of LED supply voltage (VLED) as
measured at the current source outputs. As the forward voltage of an LED does not change significantly with a small
change in forward current, this is equivalent to changing the
voltage at the LED anodes by the same amount.
Line Regulation: The average change in reference output
voltage over the specified range of supply voltage (V+).
Load Regulation: The change in reference output voltage
(VREF) over the specified range of load current (IL(REF»)'
Offset Voltage: The differential input voltage which must
be applied to each comparator to bias the output in the
linear region. Most significant error when the voltage across
the internal voltage divider is small. Specified and tested
with pin 6 voltage (VRHI) equal to pin 4 voltage (VRLO).

Accuracy: The difference between the observed threshold
voltage and the ideal threshold voltage for each comparator. Specified and tested with 10V across the internal voltage divider so that resistor ratio matching error predominates over comparator offset voltage.
Adjust Pin Current: Current flowing out of the reference
adjust pin when the reference amplifier is in the linear region.
Comparator Gain: The ratio of the change in output current
(lLED) to the change in input voltage (VIN) required to produce it for a comparator in the linear region.
Dropout Voltage: The voltage measured at the current
source outputs required to make the output current fall by
10%.
Input Bias Current: Current flowing out of the signal input
when the input buffer is in the linear region.

5-229

.-3:
....
.jlo,

Typical Performance Characteristics
Supply Current vs
Temperature

6.0

Operating Input Bias
Current vs Temperature

;;;
;;:
'"
e

..

I-- -

5.1

oS

....

"
"'
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5.4

~

5.0

i

.,

NOTE: REFERENCE LOAD
CURRENT = 1 rnA

5.2

~

"

50

25

Reference Adjust Pin
Current vs Temperature
;;
.3

~~
"c

....

..
ci

80

u

18

"'

76

"

~

"'

== .....

/'-..

""

--

~.~

1-

1--j--j--j--t----1

1.0

f---ii--i-i-i-i-hl%!

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::~

0.6

'-.....

~ t;

0.4

-"

IB
~~

15

0.2

j--I1-71I~---11--I1----i
f--i-~i-i--jf--i-i--t
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__
o
10
20 25

T.i.,)+

-

3

~

7 Irr~c

1.ZB

I--REF

.
_
N

'0

20

30

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~

I
I
lM39'V
OlYIOF R

1.08
1.08

~

~ 1.04

i
=

1.00

~

D.9a

0.96
-25

'L'
25

75

LED Driver Saturation
Voltage

~....

14

~

I.D

.

1.2

O~

~

0.6

c

0.4

z

~
~

,/

0.2
0

10

0

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20

25

11.0

i

15

,

m
n

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/

10

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1'.5

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c
c

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ill
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0.5 1.0 1.5 2.0 U

f--~~i-~~--~~-4 ZA ~

C::)::-:'f-=::t--II 2.3
10

3.0 3.5 4,0

',."

_15

DIVIDER PARALLel

100

~

15

20

LED SUPPL V VDLTAGE (VI

Common-Mode Limits

Output Characteristics
12

V+=5V

\mA

TA = 25°C

I-- ~EFER~EO TO ;OSITIV;_
SUPPLY VOL TAGE

I-

II

I

~

-Z.O

-

r--- NEGATIVE
COMMON MODE
LIMIT INCLUDES GROUND
20

40

TEMPERATURE I·C)

60

I

-

~DO""

/..

_

._-

~

lk RESISTOR
75

-0.5

~ -1.0

WITH STABLE

50

v'

§

VJ __ I-----

!

50

LED Driver Current
Regulation

V

It

~

A"- -

1.02

I
25

LED CURRENT (rnA)

20

40

Total Divider Resistance
vs Temperature

1.10

S

1.6

REFERENCE LOAD CURRENT ImAl

c

~

'D~ PIN GRrUNDEr-

1.27

I

-40 -30 -20 -10 0

1.12

<
c

11.5 , - - , , - - , _ - , - - , - - ,

26

I

-I

-3

~

30

1.0

:;1

1.29

LED Current vs
Reference Loading

1.5

I'
-2

i

I_

f - , REF ADJUSTED TO IDV

LED CURRENT (rnA)

;;
oS

~

i

I

DIVIDER v = IOV

L-~

"

100

Input Current Beyond
Signal Range (Pin 5)

Y':20J

;;:

~

TEMPERATURE I·C)

;;
oS

~

~

~c

50

25

I

IO.OD~

TEMPERATURE (-C)

12

o~~

-25

i

15

LED Current-Regulation
Dropout
I.' ,--=-.---,---,-.---,

c

~

50

i'"

TEMPERATURE rei

TEMPERATURE (·cl

" B6
"'"' 8.
"";;:z 82

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,-

75

~

~
u

;;

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10.20

10.10

~

..........

1

5.B

Reference Voltage vs
Temperature
!

~""

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ILlREF)"~DO""

I

V80

0.2

0.'

U

0.1

1.0

OUTPUT VOL TAGEIV)

TLlH/7970-2

5-230

.-----------------------------------------------------------------------------, r

s:

Block Diagram (Showing Simplest Application)

CA)

.....a:o.CD

r - -- - - -

LMJ914 -

1

- -

LED

- -,

COMPARATOR
1 OF 10

v+

I
10

1k

1k

1k

1k

REF

I

1k

7

OUT
THIS LOAD
DETERMINES
LED
BRIGHTNESS

+

REFERENCE
VOLTAGE
SOURCE

1.Z5V
1k

-

REF
AOJ

1
8

1k

1k

Y+--9 J

1k

1k
y.

FROM
PIN 11

MODE
SELECT
AMPLIFIER

I
I

CONTROLS
TYPE OF
DISPLAY, BAR
OR SINGLE
LED

V-~

1-=

I
1

L _ _ -_ _ _ _ _ _ _ _ _ _ .J

TLlH17970-3

5-231

Functional Description
spite supply voltage and temperature changes. Current
drawn by the internal 10-resistor divider, as well as by the
external current and voltage-setting divider should be included in calculating LED drive current. The ability to modulate LED brightness with time, or in proportion to input voltage and other signals can lead to a number of novel displays or ways of indicating input overvoltages, alarms, etc.

The simplifed LM3914 block diagram is to give the general
idea of the circuit's operation. A high input impedance buffer
operates with signals from ground to 12V, and is protected
against reverse and overvoltage signals. The signal is then
applied to a series of 10 comparators; each of which is biased to a different comparison level by the resistor string.
In the example illustrated, the resistor string is connected to
the internal 1.25V reference voltage. In this case, for each
125 mV that the input signal increases, a comparator will
switch on another indicating LED. This resistor divider can
be connected between any 2 voltages, providing that they
are 1.5V below V+ and no less than V-. If an expanded
scale meter display is desired, the total divider voltage can
be as little as 200 mY. Expanded-scale meter displays are
more accurate and the segments light uniformly only if bar
mode is used. At 50 mV or more per step, dot mode is
usable.

MODE PIN USE
Pin 9, the Mode Select input controls chaining of multiple
LM3914s, and controls bar or dot mode operation. The following tabulation shows the basic ways of using this input.
Other more complex uses will be illustrated in the applications.
Bar Graph Display: Wire Mode Select (pin 9) direct/yto pin
3 (V+ pin).
Dot Display. Single LM3914 Driver: Leave the Mode Select pin open circuit.
Dot Display, 20 or More LEDs: Connect pin 9 of the first
driver in the series (i.e., the one with the lowest input voltage comparison paints) to pin 1 of the next higher LM3914
driver. Continue connecting pin 9 of lower input drivers to
pin 1 of higher input drivers for 30, 40, or more LED displays. The last LM3914 driver in the chain will have pin 9
wired to pin 11. All previous drivers should have a 20k resistor in parallel with LED No.9 (pin 11 to VLEO).

INTERNAL VOLTAGE REFERENCE
The reference is designed to be adjustable and develops a
nominal 1.25V between the REF OUT (pin 7) and REF ADJ
(pin 8) terminals. The reference voltage is impressed across
program resistor R 1 and, since the voltage is constant, a
constant current 11 then flows through the output set resistor R2 giving an output voltage of:
Your = VREF

IL

I

r
T
+

(1 + :~) +

IAOJ R2

REF_ _ ADJ
REF _ _
OUT

J

~

B

Mode Pin Functional Description

I
I

LM3914

This pin actually performs two functions. Refer to the simplified block diagram below.

~

Block Diagram of Mode Pin Function
OUTPUT NO. 9

9

CONTROLLED DRIVE {
(FROM COMPARATORS)

~t---+----1-1
TL/H17970-4

Since the 120 p.A current (max) from the adjust terminal
represents an error term, the reference was deSigned to
minimize changes of this current with V + and load changes.
CURRENT PROGRAMMING
A feature not completely illustrated by the block diagram is
the LED brightness control. The current drawn out of the
reference voltage pin (pin 7) determines LED current. Approximately 10 times this current will be drawn through each
lighted LED, and this current will be relatively constant de-

5-232

Mode Pin Functional Description

(Continued)

DOT OR BAR MODE SELECTION

ticeable when using high-efficiency LEDs in a dark environment. If this is bothersome, the simple cure is to shunt LED
No. 11 with a 10k resistor. The 1V IR drop is more than the
900 mV worst case required to hold off LED No. 10 yet
small enough that LED No. 11 does not conduct significantly.

The voltage at pin 9 is sensed by comparator Cl, nominally
referenced to (V+ - 100 mY). The chip is in bar mode
when pin 9 is above this level; otherwise it's in dot mode.
The comparator is designed so that pin 9 can be left open
circuit for dot mode.
Taking into account comparator gain and variation in the
100 mV reference level, pin 9 should be no more than
20 mV below V+ for bar mode and more than 200 mV below V+ (or open circuit) for dot mode. In most applications,
pin 9 is either open (dot mode) or tied to V + (bar mode). In
bar mode, pin 9 should be connected directly to pin 3. Large
currents drawn from the power supply (LED current, for example) should not share this path so that large IR drops are
avoided.

OTHER DEVICE CHARACTERISTICS
The LM3914 is relatively low-powered itself, and since any
number of LEDs can be powered from about 3V, it is a very
efficient display driver. Typical standby supply current (all
LEDs OFF) is 1.6 mA (2.5 mA max). However, any reference
loading adds 4 times that current drain to the V+ (pin 3)
supply input. For example, an LM3914 with almA reference pin load (1.3k), would supply almost 10 mA to every
LED while drawing only 10 mA from its V+ pin supply. At
full-scale, the IC is typically drawing less than 10% of the
current supplied to the display.

DOT MODE CARRY
In order for the display to make sense when multiple
LM3914s are cascaded in dot mode, special circuitry has
been included to shut off LED No. 10 of the first device
when LED No.1 of the second device comes on. The connection for cascading in dot mode has already been described and is depicted below.

The display driver does not have built-in hysteresis so that
the display does not jump instantly from one LED to the
next. Under rapidly changing signal conditions, this cuts
down high frequency noise and often an annoying flicker.
An "overlap" is built in so that at no time between segments
are all LEDs completely OFF in the dot mode. Generally 1
LED fades in while the other fades out over a mV or more of
range (Note 2). The change may be much more rapid between LED No.1 0 of one device and LED No.1 of a second
device "chained" to the first.

As long as the input signal voltage is below the threshold of
the second LM3914, LED No. 11 is off. Pin 9 of LM3914
No. 1 thus sees effectively an open circuit so the chip is in
dot mode. As soon as the input voltage reaches the threshold of LED No. 11, pin 9 of LM3914 No. 1 is pulled an LED
drop (1.5V or more) below VLED. This condition is sensed by
comparator C2, referenced 600 mV below VLED. This forces
the output of C2 low, which shuts off output transistor Q2,
extinguishing LED No. 10.

The LM3914 features individually current regulated LED
driver transistors. Further internal circuitry detects when any
driver transistor goes into saturation, and prevents other circuitry from drawing excess current. This results in the ability
of the LM3914 to drive and regulate LEDs powered from a
pulsating DC power source, i.e., largely unfiltered. (Due to
possible oscillations at low voltages a nominal bypass capacitor consisting of a 2.2 /J-F solid tantalum connected from
the pulsating LED supply to pin 2 of the LM3914 is recommended.) This ability to operate with low or fluctuating voltages also allows the display driver to interface with logic
circuitry, opto-coupled solid-state relays, and low-current incandescent lamps.

VLED is sensed via the 20k resistor connected to pin 11.
The very small current (less than 100 /J-A) that is diverted
from LED No.9 does not noticeably affect its intensity.
An auxiliary current source at pin 1 keeps at least 100 /J-A
flowing through LED No. 11 even if the input voltage rises
high enough to extinguish the LED. This ensures that pin 9
of LM3914 No.1 is held low enough to force LED No. 10 off
when any higher LED is illuminated. While 100 /J-A does not
normally produce significant LED illumination, it may be no-

Cascading LM3914s in Dot Mode

'Ok

~

NO. 28

~~~~~~-c~~~~~~

__~__~I~D

Z2 +
LM3914
NO.1

MODE

TL/H/7970-6

5-233

~
.....

~
:E

r--------------------------------------------------------------------------,
Typical Applications (Continued)

...I

Zero-Center Meter, 20-5egment

•

430 (10 ).~

-

"

.'-

~

---',8

:

~

/iT /iT ~
u
u
.'~~
--: ~ ~

/i7
LED
NO.1

•

~

~17

N

I-

~

'iii

/i7

~,

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"116

~

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.'-

~~

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'h

14

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(i2

r'3

~

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("i1

JiT
~,

-'- LED
-=:lo.10
10

LM3914

2

l'

~.

I>

r-+~

lk* :

»27

~

l

LM337

I

:

LED

No.l1~

120

/'

f.-o'"~~

U

.'-

18

SIG
5

4

RHI

REF OUT REF AoJ MODE
9
8
7

I.!.-....

•

750

1,uF**

)~

Jv
N

RLo

3

i\

-::d.3V

N

v·

N

U
.'17

N
~,

-'-

16

,.

5Voc

N

.,,.

~,

f-

-f-

-'-

-.,

N

15

14

N

N

-~,

12

13

N
~

..;

~

N
~,

...
LED
NO.20

11

10

LM3914

L-Jl

2

y+

RLo

3

4

SIG
5

RHI

REF OUT REF AoJ MODE
9
8
7

L!...-

Uk

~

INPUTSIG
TLlH17970-7

5-234

Typical Applications

(Continued)
Expanded Scale Meter, Dot or Bar
/

VLED

III

III

III

III

N

N

III

N

III

N

LEO
NO.1

6 VAC TO 10VAC
CENTERTAPPED
Ii. 5-0-5 MAX)

t,

LEO
NO.l0
18

17

16

15

14

13

12

11

10
DOT

2.ZpF*

LM3914
REF OUT

7

'This application illustrates that the LED supply
needs practically no filtering
Calibration: With a precision meter between pins
4 and 6 adjust R1 for voltage Vo of 1.20V. Apply
4.94V to pin 5, and adjust R4 until LED NO.5 just
lights. The adjustments are non·interacting.

TLlH/7970-B

Applicatjon Example:
Grading 5V Regulators

Highest No.
LED on

Color

VOUT(MIN)

10
9
8
7
6

Red
Red
Yellow
Green
Green

5.54
5.42
5.30
5.18
5.06

5V
5
4
3
2
1

5·235

Green
Green
Yellow
Red
Red

4.94
4.82
4.7
4.58
4.46

oo:r
.,...

~

:E

Typical Applications

(Continued)
"Exclamation Point" Display

....I

/IJ

/IJ

/IJ

/IJ

/IJ

/IJ

III

/IJ

/IJ

150
LED
NO.1

LED
NO.l0

18

16

17

13

14

15

12

11

10

LM3914

5V--~--

____________-J
10k

SIG IN
3V-n

~-'I,""~---1""-"
1.5k

ov--l L1 kHz pulse rate at 10% duty cycle

~0.02"F

1.51

LEOs light up as illustrated with the upper lit LED
indicating the actual input voltage. The display
appears to increase resolution and provides an
analog indication of overrange.
TL/H/7970-9

Indicator and Alarm, Full·Scale Changes Display from Dot to Bar
V'3V

/IJ

/IJ

/IJ

/IJ

/IJ

/IJ

/IJ

/IJ

/IJ

/IJ
120

27k

LED

LED
NO.IO

NO.1
18

17

16

15

14

13

12

11

15k
01

10

DOT·BAR'
SWITCH

LM3914

2.2k

':'

'The input to the Dot-Bar Switch may be taken
from cathodes of other LEOs. Display will change
to bar as soon as the LED so selected begins to
light.

TLlHI7970-IO

5-236

Typical Applications

(Continued)
Bar Display wih Alarm Flasher
VLED 5V
• 100

N
~,

N

N

~~

V
,.;

~~

III

111

111

V

111

~~

V
,.;

~~

111

N

111

."

RI
Ik

."

LED
NO. I

LED
NO.IO

~

18

17

16

IS

14

13

12

II

10

;:~

lMJ914

L-JI

~

v+

RLO

3

.J;

RHI

SIG

P

6

REF OUT REF AOJ MODE
7
9

*

470

1.2k

Full-scale causes the full bar display to flash. If
. .
.
.
the Junction of R1 and C1 IS connected to a dlfferenl LED calhode, Ihe display will flash when
Ihal LED lights, and al any higher inpul signal.

TLIH17970-11

Adding Hysteresis (Single Supply, Bar Mode Only)

v'
15V)

1
II

IPFi

.., .. ..,
N

N

~

N

."

17

ADJ
VLED
OUT
LM337H

111
~,

LED
NO.1

I.

~

16

N

N

~~

~~

V

,.;

IS

N

14

N

N
~,

~~ -r LED
ND.IO

-."

13

N

12

11

10

REF
ADJ
D

MODE

I

IN

lMJ914
VL-JI

~

v'
3

RLO

SIG

4

1

5

RHI

REF OUT

l!.......;
Uk

7

9

r-liD ~
2.7
CARD ON
10

Hysteresis is 0.5 mV to 1 mV
~

TLIH17970-12

5-237

-.:r
.,...
~

:IE

Typical Application

.....

(Continued)
Operating with a High Voltage Supply (Dot Mode Only)

...

J9k
'W

The LED currents are approximately 10 mA, and
the LM3914 outputs operate in saturation for

minimum dissipation.

,9k
'w

.

lN~DZ

,

/1/
~,

#

N

~Ir

Ir

III

N

"

, "'I' ,, "
I!I

"I

"

LED
NO.1

8

III

,)/

LEO

NO.1

1B

"

"

15

,

RLD

"

"

"

"

"

LMJ914
REF

v'

-¥

L.....I'
J.4V*

-¥

,Ir
'This point is partially regulated and decreases in
voltage with temperature. Voltage requirements
of the LM3914 also decrease with temperature.

SID

l'

REF

OUT

AOJ

MODE

!!..- 1

-¥

I'

"H'

III

'" '~

ZN2905

TL/H17970-13

20-Segment Meter with Mode Switch

,

III

LEO

-The exact wiring arrangement of this schematic
shows the need for Mode Select (pin 9) to sense
the V + voltage exactly as it appears on pin 3.

III

"

1/1

1/1
~,

~

Ir

III

1/1
1/1
"'I' ,, "'I,

,

III

1/1

Ir

N

"

NO'

1B

"

"

"

15

"

"

"

".

LED
NO lQ

"

LMJ914

v'

-¥

L.....I'

,

RLD

SID

-¥

RH'

•

5

REF

REF

OUT

AOJ

:.2V

,

MODE

-¥

1.1 ....

o:!1/1

"

,

1/1

:} -r~

1B

N

N

" "

LEO
NO.lt

J

1/1

"

~r

"

15

1/1
~Ir

"

,"
1/1

.,

III

N

"

"

"

,

1/1
LEO
ND.2U

"

"

LMJ914

,

v2

v'

,

"LD
4

":"

SID
5

SIG OV-Z4V

RH'

REF

REF

OUT

AOJ

l!.-

I

24V

•

MODE

24k*

'Programs LEOs to 10 mA

5-238

•

TLlH17970-14

,-----------------------------------------------------------------------------, r
3:
Co)

Application Hints

....
"'"
cg

Three of the most commonly needed precautions for using
the LM3914 are shown in the first typical application drawing (see page 9-108) showing a OV-SV bar graph meter.
The most difficult problem occurs when large LED currents
are being drawn, especially in bar graph mode. These currents flowing out of the ground pin cause voltage drops in
external wiring, and thus errors and oscillations. Bringing the
return wires from signal sources, reference ground and bottom of the resistor string (as illustrated) to a single point
very near pin 2 is the best solution.

NON-INTERACTING ADJUSTMENTS FOR EXPANDED
SCALE METER (4.5V to 5V, Bar or Dot Mode)
This arrangement allows independent adjustment of LED
brightness regardless of meter span and zero adjustments.
First, VI is adjusted to 5V, using R2. Then the span (voltage
across R4) can be adjusted to exactly O.SV using R6 without
affecting the previous adjustment.
R9 programs LED currents within a range of 2.2 rnA to
20 rnA after the above settings are made.

Long wires from VLED to LED anode common can cause
oscillations. Depending on the severity of the problem
0.05 p.F to 2.2 p.F decoupling capacitors from LED anode
common to pin 2 will damp the circuit. If LED anode line
wiring is inaccessible, often similar decoupling from pin 1 to
pin 2 will be sufficient.

Greatly Expanded Scale (Bar Mode Only)
RLO

RHI

(:>:I-"'~

-

REF
OUT

REF
ADJ

-Q7•~ Rl

If LED turn ON seems slow (bar mode) or several LEDs light
(dot mode), oscillation or excessive noise is usually the
problem. In cases where proper wiring and bypassing fail to
stop oscillations, V+ voltage at pin 3 is usually below suggested limits (see Note 2, page 9-108). Expanded scale meter applications may have one or both ends of the internal
voltage divider terminated at relatively high value resistors.
These high-impedance ends should be bypassed to pin 2
with at least a 0.001 p.F capacitor, or up to 0.1 p.F in noisy
environments.

~

100

»

R2

~1%

""l
_
-

PINS OF
LM3914

....--+·C250
VI'I.IV

I

:

V2

~

Power dissipation, especially in bar mode should be given
consideration. For example, with a SV supply and all LEDs
programmed to 20 rnA the driver will dissipate over 600 mW.
In this case a 7.50 resistor in series with the LED supply will
cut device heating in half. The negative end of the resistor
should be bypassed with a 2.2 p.F solid tantalum capacitor
to pin 2 of the LM3914.
Turning OFF of most of the internal current sources is accomplished by pulling positive on the reference with a current source or resistance supplying 100 p.A or so. Alternately, the input signal can be gated OFF with a transistor
switch.
Other special features and applications characteristics will
be illustrated in the following applications schematics.
Notes have been added in many cases, attempting to cover
any special procedures or unusual characteristics of these
applications. A special section called "Application Tips for
the LM3914 Adjustable Reference" has been included with
these schematics.

fO. I 1F

»
~

R5

100

R3

200
1%

R4
15

VI

~ R6

909
1%

--=
TLlH/7970-15

ADJUSTING LINEARITY OF SEVERAL STACKED
DIVIDERS
Three internal voltage dividers are shown connected in series to provide a 30-step display. If the resulting analog meter is to be accurate and linear the voltage on each divider
must be adjusted, preferably without affecting any other adjustments. To do this, adjust R2 first, so that the voltage
across RS is exactly 1V. Then the voltages across R3 and
R4 can be independently adjusted by shunting each with
selected resistors of 6 kO or higher resistance. This is possible because the reference of LM3914 No.3 is acting as a
constant current source.
The references associated with LM3914s No.1 and No.2
should have their Ref Adj pins (pin 8) wired to ground, and
their Ref Outputs loaded by a 6200 resistor to ground. This
makes available similar 20 rnA current outputs to all the
LEDs in the system.
If an independent LED brightness control is desired (as in
the previous application), a unity gain buffer, such as the
LM310, should be placed between pin 7 and R1, similar to
the previous application.

APPLICATION TIPS FOR THE LM3914 ADJUSTABLE
REFERENCE
GREATLY EXPANDED SCALE (BAR MODE ONLY)
Placing the LM3914 internal resistor divider in parallel with a
section ('" 2300) of a stable, low resistance divider greatly
reduces voltage changes due to IC resistor value changes
with temperature. Voltage VI should be trimmed to 1.1 V first
by use of R2. Then the voltage V2 across the IC divider
string can be adjusted to 200 mV, using RS without affecting
VI. LED current will be approximately 10 rnA.

5-239

..,.,...
~
:Ii

Application Hints (Continued)

...I

Non-Interacting Adjustments for Expanded Scale Meter (4.5V to 5V, Bar or Dot Mode)

REF
OUT

REF
10V

R8

R7

2.4k

10k

ADJ

R9
20k
LED
BRIGHTNESS

R4
523

-

4.5V
R5
4.32k
1%

~0.02"F

R6
500
TUH17970-16

Adjusting Linearity of Several Stacked Dividers
Rl
549
1%

...

[

" ",

Other Applications
R2
200

•
•
•
•
•
•
•
•

"Slow"-fade bar or dot display (doubles resolution)
20-step meter with single pot brightness control
10-step (or multiples) programmer
Multi-step or "staging" controller
Combined controller and process deviation meter
Direction and rate indicator (to add to DVMs)
Exclamation point display for power saving
Graduations can be added to dot displays. Dimly light
every other LED using a resistor to ground
• Electronic "meter-relay"-display could be circle or
semi-circle
• Moving "hole" display-indicator LED is dark, rest of
bar lit
• Drives vacuum-fluorescent and LCDs using added passive parts

3V

R3
549
1%

{
,~. '" {

""..... ,

2V

R4
549
IV

R5
511
1%

-

TUH17970-17

5-240

Connection Diagrams
Dual-In-Line Package
Plastic Chip Carrier Package
1
LED NO.1 V- -

3

DIVIDER (LOW END) -

2

1 20 19

4

v+

18 r- LED 4

SIGNAL INPUT- 5

17 r-LED5

DIVIDER (HIGH END)- 6

16 r-LED6

N/C- 7

1Sr-LED7

REFERENCE OUTPUT- 8

14

t- LED8

9 10 11 12 13

U

18
r-

LED NO.2

17
LED NO.3
-

2

2-

-

16

LED NO.4

15

DIVIDER ~
(LOW END)
5
SIGNAL INPUT -

r- LED NO.6

DIVIDER 6
(HIGH ENDi-

r- LED NO.7

r- LED NO.5
14

13

REFERENCE OUTPUT

..!..

r!! LED NO.8

REFERENCE AOJUST

....!

~

9

10

MODE SELECT -

LEO NO.9

r- LED NO. 10

TL/H/7970-1B

TL/H/7970-19

Top View

TOp View

Order Number LM3914V
See NS Package Number V20A
(ADVANCED INFORMATION)

Order Number LM3914N
See NS Package Number N18A

5-241

....en
NatiOnal
Semiconductor
:i ~ Corporation

U) r-----------------------------------------------------------------------------------~
C')

LM3915 Dot/Bar Display Driver
General Description
The LM3915 is a monolithic integrated circuit that senses
analog voltage levels and drives ten LEOs, LCOs or vacuum
fluorescent displays, providing a logarithmic 3 dB/step analog display. One pin changes the display from a bar graph to
a moving dot display. LED current drive is regulated and
programmable, eliminating the need for current limiting resistors. The whole display system can operate from a single
supply as low as 3V or as high as 25V.

The LM3915 is very versatile. The outputs can drive LCOs,
vacuum fluorescents and incandescent bulbs as well as
LEOs of any color. Multiple devices can be cascaded for a
dot or bar mode display with a range of 60 or 90 dB.
LM3915s can also be cascaded with LM3914s for a linear/
log display or with LM3916s for an extended-range VU meter.

Features

The IC contains an adjustable voltage reference and an accurate ten-step voltage divider. The high-impedance input
buffer accepts signals down to ground and up to within 1.5V
of the positive supply. Further, it needs no protection
against inputs of ± 35V. The input buffer drives 10 individual
comparators referenced to the precision divider. Accuracy is
typically better than 1 dB.

•
•
•
•
•
•
•
•
•
•
•
•

3 dB/step, 30 dB range
Drives LEOs, LCOs, or vacuum fluorescents
Bar or dot display mode externally selectable by user
Expandable to displays of 90 dB
Internal voltage reference from 1.2V to 12V
Operates with single supply of 3V to 25V
Inputs operate down to ground
Output current programmable from 1 mA to 30 mA
Input withstands ± 35V without damage or false outputs
Outputs are current regulated, open collectors
Directly drives TTL or CMOS
The internal 10-step divider is floating and can be referenced to a wide range of voltages
The LM3915 is rated for operation from O'C to + 70'C. The
LM3915N is available in an 18-lead molded DIP package.

The LM3915's 3 dB/step display is suited for signals with
wide dynamic range, such as audio level, power, light intensity or vibration. Audio applications include average or peak
level indicators, power meters and RF signal strength meters. Replacing conventional meters with an LED bar graph
results in a faster responding, more rugged display with high
visibility that retains the ease of interpretation of an analog
display.
The LM3915 is extremely easy to apply. A 1.2V full-scale
meter requires only one resistor in addition to the ten LEOs.
One more resistor programs the full-scale anywhere from
1.2V to 12V independent of supply voltage. LED brightness
is easily controlled with a single pot.

Typical Applications
OV to 10V Log Display

rI

Cl

JV"'VLED .;;v'

I
LED
I NO.1
I
I

/1/

/1/

/1/

/1/

/1/

/1/

/1/

/1/

/1/

LED
NO.l0

17

18

,,

16

15

TANT~~~~-L

14

13

12

11

10

LMJ915

OR10IJ.F~

ALUMINUM
ELECTROL YTIC

/1/

v,

v-

RLO

SIG

J

I

L_____
Note 1: Capacitor CI is required if leads to the LED sup·
ply are 611' or longer.

v'

Note 2: Circuit as shown is

12V TO 20V
VAEF = 1.25V (I
I
LED

wired for dot mode. For bar
mode, connect pin 9 to pin 3.
VLED must be kept below 7V or
dropping resistor should be
used to limit IC power dissipa-

+1*) +

R2x80"A

=~+ VAEF
RI

2.2kn

tion.

5-242

TLlH/5104-1

r-

s:

Absolute Maximum Ratings

Co)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Dissipation (Note 5)
Molded DIP(N)

Input Signal Overvoltage (Note 3)

25V

Voltage on Output Drivers

25V

-100mVtoV+

Divider Voltage
Reference Load Current

10mA

Storage Temperature Range

1365mW

Supply Voltage

±35V

- 55'C to + 150'C
260'C

Lead Temperature (Soldering, 10 sec.)

Electrical Characteristics (Note 1)
Parameter

Conditions (Note 1)

Min

Typ

Max

Units

Comparators
Offset Voltage, Buffer and First
Comparator

OV :;;; VRLO = VRHI :;;; 12V,
ILED = 1 mA

3

10

mV

Offset Voltage, Buffer and Any Other
Comparator

OV :;;; VRLO = VRHI :;;; 12V,
ILED = 1 mA

3

15

mV

Gain (ll.ILED/ll.VIN)

IL(REF) = 2 mA, ILED = 10 mA

Input Bias Current (at Pin 5)

OV:;;; VIN :;;; (V+ - 1.5V)

Input Signal Overvoltage

No Change in Display

3

mA/mV

8
25

-35

100

nA

35

V

Voltage-Divider
Divider Resistance

Total, Pin 6 to 4

Relative Accuracy (Input Change
Between Any Two Threshold Points)

(Note 2)

Absolute Accuracy at Each Threshold Point

16

28

36

kfi

2.0

3.0

4.0

dB

(Note 2)
VIN = -3, -6 dB

-0.5

+0.5

dB

VIN = -9dB

-0.5

+0.65

dB

VIN = -12, -15, -18dB

-0.5

+1.0

dB

VIH = -21, -24, -27 dB

-0.5

+1.5

dB

Output Voltage

0.1 mA :;;; IL(REF) :;;; 4 mA,
V+ = VLED = 5V

1.2

1.28

1.34

V

Line Regulation

3V:;;; V+ :;;; 18V

0,01

0.03

%/V

Load Regulation

0.1 mA :;;; IL(REF) :;;; 4 mA,
V+ = VLED = 5V

0.4

2

%

Output Voltage Change with Temperature

O'C :;;; TA :;;; + 70'C, IL(REF) = 1 mA,
V+ = VLED5V

Voltage Reference

Adjust Pin Current

75

5-243

%

1
120

/LA

co
......
c.n

Electrical Characteristics (Note 1) (Continued)
Parameter

Conditions (Note 1)

Min

Typ

Max

Units

Output Drivers

=

=

LED Current

V+

lED Current Difference (Between Largest
and Smallest LED Currents)

VLED
VLED

LED Current Regulation

2V,;: VLED';; 17V, ILED
ILED

Dropout Voltage

VLED

=
=

ILED(ON)

=

~ILED

=

=

5V, IL(REF)

1 mA

7

5V, ILED = 2 mA
5V, ILED 20 mA

=

20 mA
2 rnA

Saturation Voltage

ILED

Output Leakage, Each Collector

Bar Mode (Note 4)

Output Leakage
Pins 10-18
Pin 1

Dot Mode (Note 4)

@

=
=

2 mA
20 rnA

VLED

2.0 rnA, IL(REF)

=

=

10

13

mA

0.12

0.4

mA

1.2

3

mA

0.1

0.25

mA

1

3

rnA

1.5

V

5V,

0.4 mA

60

0.15

0.4

V

0.1

10

)J-A

0.1

10

)J-A

150

450

)J-A

2.4

4.2

rnA

6.1

9.2

rnA

Supply Current
Standby Supply Current
(All Outputs Off)

V+
V+

=
=

+5V, IL(REF) = 0.2 rnA
+20V, IL(REF) = 1.0 rnA

Note 1: Unless otherwise stated, all specifications apply with the following conditions:

3 vee';; V+ ,;; 20 Vee
-0.015V ,;; VRLO ,;; 12 Vee
TA ~ 25'C. IL(REF) ~ 0.2 mAo pin 9 connected to pin 3 (bar mode).
3 Vee';; VLEe ,;; V+
VREF. VRHI. VRLO ,; ry+ - 1.5V) For higher power dissipations, pulse testing is used.
OV,; VIN ,; V+ - 1.5V
-0.015V ,; VRHI ,; 12 Vee
Note 2: Accuracy Is measured referred to 0 dB ~ + 10.000 Vee at pin 5. with + 10.000 Vee at pin 6. and 0.000 Vee at pin 4. At lower full scale voltages, buffer
and ocmparator offset voltage may add signijicant error. See table for threshold voltages.
Note 3: Pin 5 input current must be limited to ± 3 mAo The addition of a 39k resistor in series with pin 5 allows ± 100V signals without damage.
Note 4: Bar mode results when pin 9 is within 20 mV of V + . Dot mode results when pin 9 is pulled at least 200 mV below V +. LED #: 10 (pin 10 output current) is

disabled if pin 9 is pulled 0.9V or more below VLEe.
Note 5: The maximum junction temperature of the LM3915 is 100'C. Devices must be derated for operation at elevated temperatures. Junction to ambient thermal
resistance is 55'C/W for the molded DIP (N package).
THRESHOLD VOLTAGE (Note 2)
Output

dB

Min

Typ

Max

Output

dB

Min

Typ

Max

1
2
3
4
5

-27
-24
-21
-18
-15

0.422
0.596
0.841
1.189
1.679

0.447
0.631
0.891
1.259
1.778

0.531
0.750
1.059
1.413
1.995

6
7
8
9
10

-12
-9
-6
-3
0

2.372
3.350
4.732
6.683
9.985

2.512
3.548
5.012
7.079
10

2.819
3.825
5.309
7.498
10.015

5-244

Typical Performance Characteristics
Supply Current vs
Temperature
.--r--.,---,---,---.,

6.0
M

~

Operating Input Bias
Current vs Temperature

5.B 1---"l-::=;j;..-1""~~=-1

--....

o

~

5.6

z

54

.s....
'"

'"
B

t--t-:=oI--=r==;;.-;

.."

52

>

~

1--+--+--+-+--1

5.0

25

50

TEMPERATURE

75

25

rei

50

75

TEMPERATURE ('CI

Reference Adjust Pin
Current vs Temperature

LED Current-Regulation
Dropout

'<
3

....

I
z

lrici
"

~

B6

~

8.

TA"7~1E-

' ...........

82

'"

80
78
76

25

-25

,

'-....
~

50

75

.00

10

TEMPERATURE ('el

.1

1 1
e-

DIVIDER v '" IOV

'<

.s....
'"'"
u
~

~

!!!

TAI"7)C~,

-2
-3

-

~

-.

30

1.0

25

...<=~
"

~A=O~C

'"
0

'0

.s'<....

25

20

30

/""

/

20
TA " 25"'l

z

"m" '"u'"
-<

7 .II

-40 -30 -20 -10

20

LED Current vs
Reference Loading

...
0.5

z

15

LED CURRENT (mAl

Input Current Beyond
Signal Range (Pin 5)
V+=20V

TA'O·'C-

0

w

/

.0

o

40

V

15

~

1/
o

0.5

\.0 1.5 2.0 2.5 3.0 3.5 4.0

REFERENCE LOAD CURRENT (mAl

Total Divider Resistance
vs Temperature

~
~

i

t-

1.12
1.11)

-

--

1.08

1.06

-

r

-

LM39·V
DIVIDER

u

z

~

~
'"

'04

1.02

-

1.00

w

0

;;; 0.98

0

I--

V

--

Common-Mode Limits
~

v'

.2

-0.5

.0

~ -1.0

-

",.

_

~EFER~EO TO JOSlTlvi_

0
0

A'

DIVIDER PARALLEl

WITH STABLE
Ik RESISTOR

"~

50

TEMPERATURE ( C)

75

100

"mA

TA"'25"C

~

SUPPLY VOLTAGE

~OOpA

~OOpA

I

.~

-2.0

:!S

YL--25

V+=5V

:::; -1.5
w

-

NEGATIVE COMMON-MOOELIMIT INCLUDES GROUND

0.96

-25

Output Characteristics

20

40

TEMPERATURE I'C)

60

BO

J

1400pA
'L(REFI"

~OOpA

I

V-

0.2

0.4

0.6

0.8

'.0

OUTPUT VOL TAGE(V)

TL/H/S104-3

5-245

~
,..
0)
(')

::E

r---------------------------------------------------------------------------------,
Block Diagram

(Showing Simplest Application)

....I

r---

LED
y+

LMl9i5-----,
COMPARATOR
I OF 10

1

I

10

6.6lk

4.69k

3.llk
LED PROGRAM
CURRENT

REF
OUT
THIS LOAD
DETERMINES
LED
BRIGHTNESS

I1

1.66k
REFERENCE
VOLTAGE
SOURCE
1.2Y
1.17k

-

REF 1

ADJ

':'

0.8lk

B

I
0.S9k

1

I
Y+--1 3

0.41k

I
I
RLD I 4

Ik
y+

':'

~

FROM
PIN II

MODE
SELECT
AMPLIFIER

I
I

CONTROLS
TYPE OF
DISPLAY. BAR
OR SINGLE
LED

~
I':'

+

L____________ J

TL/H/S104-4

5-246

r-----------------------------------------------------------------------------'r
3:
Co)

Functional Description

TL/H/5104-6

Outputs may be run in saturation with no adverse effects,
making it possible to directly drive logic. The effective saturation resistance of the output transistors, equal to RE plus
the transistors' collector resistance, is about 500. It's also
possible to drive LEOs from rectified AC with no filtering. To
avoid oscillations, the LED supply should be bypassed with
a 2.2 ",F tantalum or 10 ",F aluminum electrolytic capacitor.

INTERNAL VOLTAGE REFERENCE
The reference is designed to be adjustable and develops a
nominal 1.25V between the REF OUT (pin 7) and REF ADJ
(pin 8) terminals. The reference voltage is impressed across
program resistor R1 and, since the voltage is constant, a
constant current 11 then flows through the output set resistor R2 giving an output voltage of:

',!

r

:~)

REF

REF

OUT_ _ ADJ _ _

7

~EF

8

..-l

MODE PIN USE
Pin 9, the Mode Select input, permits chaining of multiple
LM3915s, and controls bar or dot mode operation. The following tabulation shows the basic ways of using this input.
Other more complex uses will be illustrated in the applications.
Bar Graph Display: Wire Mode Select (pin 9) directly to pin
3 (V+ pin).

•

Dot Display, Single LM3915 Driver: Leave the Mode Select pin open circuit.

+ IAOJ R2

,M,...

U1

PIN I,PINS 10-18

In the example illustrated, the resistor string is connected to
the internal 1.25V reference voltage. In this case, for each
3 dB that the input signal increases, a comparator will
switch on another indicating LED. This resistor divider can
be connected between any 2 voltages, providing that they
are at least 1.5V below V+ and no lower than V-.

VOUT = VREF ( 1 +

CD
.....

LM3915 Output Circuit

The simplified LM3915 block diagram is included to give the
general idea of the circuit's operation. A high input impedance buffer operates with signals from ground to 12V, and is
protected against reverse and overvoltage signals. The signal is then applied to a series of 10 comparators; each of
which is biased to a different comparison level by the resistor string.

I
I

~

Dot Display, 20 or More LEOs: Connect pin 9 of the first
driver in the series (I.e., the one with the lowest input voltage comparison points) to pin 1 of the next higher LM3915
driver. Continue connecting pin 9 of lower input drivers to
pin 1 of higher input drivers for 30 or more LED displays.
The last LM3915 driver in the chain will have pin 9 left open.
All previous drivers should have a 20k resistor in parallel
with LED #9 (pin 11 to VLEO).

VI
TUH/5104-5

Since the 120 ",A current (max) from the adjust terminal
represents an error term, the reference was designed to
minimize changes of this current with V+ and load changes.
For correct operation, reference load current should be between 80 ",A and 5 mA. Load capacitance should be less
than 0.05 ",F.

Mode Pin Functional Description
This pin actually performs two functions. Refer to the simplified block diagram below.

CURRENT PROGRAMMING

Block Diagram of Mode Pin Function

A feature not completely illustrated by the block diagram is
the LED brightness control. The current drawn out of the
reference voltage pin (pin 7) determines LED current. Approximately 10 times this current will be drawn through each
lighted LED, and this current will be relatively constant despite supply voltage and temperature changes. Current
drawn by the internal 10-resistor divider, as well as by the
external current and voltage-setting divider should be included in calculating LED drive current. The ability to modulate LED brightness with time, or in proportion to input voltage and other signals can lead to a number of novel displays or ways of indicating input overvoltages, alarms, etc.

OUTPUT NO.9

OUTPUT NO. 10

CONTROLLED DRIVE {
(FROM COMPARATORSI

HI---+--+-I

The LM3915 outputs are current-limited NPN transistors as
shown below. An internal feedback loop regulates the transistor drive. Output current is held at about 10 times the
reference load current, independent of output voltage and
processing variables, as long as the transistor is not saturated.

I
"'High for bar

5-247

TLlH/5104-7

....
II')

~

::i

Mode Pin Functional Description
(Continued)
DOT OR BAR MODE SELECTION
The voltage at pin 9 is sensed by comparator C1, nominally
referenced to (V+ - 100 mY). The chip is in bar mode
when pin 9 is above this level; otherwise it's in dot mode.
The comparator is designed so that pin 9 can be left open
circuit for dot mode.

OTHER DEVICE CHARACTERISTICS
The LM3916 is relatively low-powered itself, and since any
number of LEDs can be powered from about 3V, it is a very
efficient display driver. Typical standby supply current (all
LEDs OFF) is 1.6 rnA. However, any reference loading adds
4 times that current drain to the V + (pin 3) supply input. For
example, an LM3916 with a 1 rnA reference pin load (1.3k)
would supply almost 10 rnA to every LED while drawing only
10 mA from its V + pin supply. At full-scale, the IC is typically
drawing less than 10% of the current supplied to the display.
The display driver does not have built-in hysteresis so that
the display does not jump instantly from one LED to the
next. Under rapidly changing signal conditions, this cuts
down high frequency noise and often an annoying flicker.
An "overlap" is built in so that at no time are all segments
completely off in the dot mode. Generally 1 LED fades in
while the other fades out over a mV or more of range. The
change may be much more rapid between LED # 10 of one
device and LED # 1 of a second device "chained" to the
first.

Taking into account comparator gain and variation in the
100 mV reference level, pin 9 should be no more than 20
mV below V+ for bar mode and more than 200 mV below
V+ (or open circuit) for dot mode. In most applications, pin
9 is either open (dot mode) or tied to V+ (bar mode). In bar
mode, pin 9 should be connected directly to pin 3. Large
currents drawn from the power supply (LED current, for example) should not share this path so that large IR drops are
avoided.
DOT MODE CARRY
In order for the display to make sense when multiple
LM3915s are cascaded in dot mode, special circuitry has
been included to shut off LED # 10 of the first device when
LED # 1 of the second device comes on. The connection for
cascading in dot mode has already been described and is
depicted below.

Application Hints

As long as the input signal voltage is below the threshold of
the second LM3915, LED # 11 is off. Pin 9 of LM3915 # 1
thus sees effectively an open circuit so the chip is in dot
mode. As soon as the input voltage reaches the threshold
of LED # 11, pin 9 of LM3915 # 1 is pulled an LED drop
(1.5V or more) below VLEO. This condition is sensed by
comparator C2, referenced 600 mV below VLEO. This forces
the output of C2 low, which shuts off output transistor Q2,
extinguishing LED # 1O.

The most difficult problem occurs when large LED currents
are being drawn, especially in bar graph mode. These currents flowing out of the ground pin cause voltage drops in
external wiring, and thus errors and oscillations. Bringing the
return wires from signal sources, reference ground and bottom of the resistor string to a single point very near pin 2 is
the best solution.
Long wires from VLEO to LED anode common can cause
oscillations. Depending on the severity of the problem
0.05 ".F to 2.2 ".F decoupling capacitors from LED anode
common to pin 2 will damp the circuit. If LED anode line
wiring is inaccessible, often similar decoupling from pin 1 to
pin 2 will be sufficient.
If LED turn ON seems slow (bar mode) or several LEDs light
(dot mode), oscillation or excessive noise is usually the
problem. In cases where proper wiring and bypassing fail to
stop oscillations, V+ voltage at pin 3 is usually below suggested limits. Expanded scale meter applications may have
one or both ends of the internal voltage divider terminated
at relatively high value resistors. These high-impedance
ends should be bypassed to pin 2 with at least a 0.001 ".F
capacitor, or up to 0.1 ".F in noisy environments.

VLEO is sensed via the 20k resistor connected to pin 11.
The very small current (less than 100 ".A) that is diverted
from LED # 9 does not noticeably affect its intensity.
An auxiliary current source at pin 1 keeps at least 100 ".A
flowing through LED # 11 even if the input voltage rises high
enough to extinguish the LED. This ensures that pin 9 of
LM3915 #1 is held low enough to force LED #10 off when
any higher LED is illuminated. While 100 ".A does not normally produce significant LED illumination, it may be noticeable when using high-efficiency LEDs in a dark environment.
If this is bothersome, the simple cure is to shunt LED # 11
with a 10k resistor. The 1V IR drop is more than the 900 mV
worst case required to hold off LED # 10 yet small enough
that LED # 11 does not conduct significantly.

Cascading LM3915s in Dot Mode
r-2Dk

,;M ~ ,;M~ ,;M~ ,;M
~ ,;M ~ ,;M~ ,;M
f'"

~ "'f1 ~ f'"
NO.1

"

11

"

15

"

13

VlED

,;M~ ,~~

12

11

NO.1U
10

rle. ~ ,;M ~ ,;M~ ,~~ r;M ~ ,;M , ,;M,,;M ~ F-',;M~- ¢.
f'"

NO. 11

18

11

16

f'"

15

L...-J1

v'

-:!:

I'

13

12

NO.20

11

10

'~~

LMJ915

LM3915
NO.1

v-

"
NO.2

RlO

SlG

RHI

REF
OUT

REF
AOJ

I'

I'

I'

I'

I'

v-

MODE

•

I

-:!:

v'

p

RlO

SIG

RHI

REF
OUT

REF
AOJ

MODE

I'

I'

I'

I'

I'

19

-r

TUH/5104-8

5-248

Application Hints (Continued)
Power dissipation, especially in bar mode should be given
consideration. For example, with a 5V supply and all LEDs
programmed to 20 mA the driver will dissipate over 600 mW.
In this case a 7.5fi resistor in series with the LED supply will
cut device heating in half. The negative end of the resistor
should be bypassed with a 2.2 J.LF solid tantalum capacitor
to pin 2.

Display circuits using two or more LM3915s for a dynamic
range of 60 dB or greater require more accurate detection.
In the precision half-wave rectifier of Figure 2 the effective
diode offset is reduced by a factor equal to the open-loop
gain of the op amp. Filter capacitor C2 charges through R3
and discharges through R2 and R3, so that appropriate selection of these values results in either a peak or an average
detector. The circuit has a gain equal to R2/Rl.

TIPS ON RECTIFIER CIRCUITS

It's best to capacitively couple the input. Audio sources frequently have a small DC offset that can cause significant
error at the low end of the log display. Op amps that slew
quickly, such as the LF351 , LF353, or LF356, are needed to
faithfully respond to sudden transients. It may be necessary
to trim out the op amp DC offset voltage to accurately cover
a 60 dB range. Best results are obtained if the circuit is
adjusted for the correct output when a low-level AC signal
(10 to 20 mV) is applied, rather than adjusting for zero output with zero input.
For precision full-wave averaging use the circuit in Figure 3.
Using 1% resistors for R 1 through R4, gain for positive and
negative signal differs by only 0.5 dB worst case. Substituting 5% resistors increases this to 2 dB worst case. (A 2 dB
gain difference means that the display may have a ± 1 dB
error when the input is a nonsymmetrical transient). The
averaging time constant is R5-C2. A simple modification
results in the precision full-wave detector of Figure 4. Since
the filter capacitor is not buffered, this circuit can drive only
high impedance loads such as the input of an LM3915.

The simplest way to display an AC signal using the LM3915
is to apply it right to pin 5 unrectified. Since the LED illuminated represents the instantaneous value of the AC waveform, one can readily discern both peak and average values
of audio signals in this manner. The LM3915 will respond to
positive half-cycles only but will not be damaged by signals
up to ± 35V (or up to ± 100V if a 39k resistor is in series
with the input). It's recommended to use dot mode and to
run the LEDs at 30 mA for high enough average intensity.
True average or peak detection requires rectification. If an
LM3915 is set up with 1OV full scale across its voltage divider, the turn-on point for the first LED is only 450 mV. A
simple silicon diode rectifier won't work well at the low end
due to the 600 mV diode threshold. The half-wave peak
detector in Figure 1 uses a PNP emitter-follower in front of
the diode. Now, the transistor's base-emitter voltage cancels out the diode offset, within about 100 mV. This approach is usually satisfactory when a single LM3915 is used
for a 30 dB display.

v' 15V TO 25VI
Rl
10k

RJ
lk

R2
tOOk

01

lN914

....-t"'-.....--1-

Cl
1 pF

OUTPUT

~

INPUT - .

R1
10k

.......JIM".........-

*""-.. . .

OUTPUT

02

I-A,/Iollr-+--...

01.02: lN914 or lN4148

R2
1M

'~C

Couple

TL/H/5104-9

FIGURE 1. Half·Wave Peak Detector

Average

Peak

R2

lk

lOOk

R3

100k

~

Rl
Cl

~

R2/Rl0 for Ay

~

10/Rl
TL/H/5104-10

R2 for Ay

FIGURE 2. Precision Half·Wave Rectifier
C2
0.41
Cl
~

--.J
INPUT I

M

~

200k

200k

1-4~--.I\IVv----4~--'\NII--"'"

OUTPUT

01,02: lN914 or lN4148

TLIH/5104-11

FIGURE 3. Precision Fu"·Wave Average Detector
5-249

lk

Rl

~

1
~

10

~r---------------------------------------------------------------'
.,...
0)
C')

:E

Application Hints (Continued)

R6
Ik

....

.....JI.JV......_ _ OUTPUT
R5
200k

Cl
0.2

---1

INPUT.

R4
200k

~,..--...JI,M_--""--~~--""
RI
lOOk R2
lOOk

01,02,03,04: lN9140r lN414B

TLIH/5104-12

FIGURE 4. Precision Full-Wave Peak Detector
to the lower LM3915 by 30 dB. Since two 1 % resistors can
set the amplifier gain within ± 0.2 dB, a gain trim is unnecessary. However, an op amp offset voltage of 5 mV will shift
the first LED threshold as much as 4 dB, so that an offset
trim may be required. Note that a single adjustment can null
out offset in both the precision rectifier and the 30 dB gain
stage. Alternatively, instead of amplifying, input signals of
sufficient amplitude can be fed directly to the lower LM3915
and attenuated by 30 dB to drive the second LM3915.
To extend this approach to get a 90 dB display, another 30
dB of amplification must be placed in the signal path ahead
of the lowest LM3915. Extreme care is required as the lowest LM3915 displays input signals down to 0.5 mY! Several
offset nulls may be required. High currents should not share
the same path as the low level signal. Also power line wiring
should be kept away from signal lines.

CASCADING THE LM3915
To display signals of 60 or 90 dB dynamic range, multiple
LM3915s can be easily cascaded. Alternatively, it is possible to cascade an LM3915 with LM3914s for a log/linear
display or with an LM3916 to get an extended range VU
meter.
A simple, low cost approach to cascading two LM3915s is
to set the reference voltages of the two chips 30 dB apart
as in Figure 5. Potentiometer R1 is used to adjust the full
scale voltage of LM3915 # 1 to 316 mV nominally while the
second IC's reference is set at 10V by R4. The drawback of
this method is that the threshold of LED # 1 is only 14 mV
and, since the LM3915 can have an offset voltage as high
as 10 mV,large errors can occur. This technique is not recommended for 60 dB displays requiring good accuracy at
the first few display thresholds.
A better approach shown in Figure 6 is to keep the reference at 10V for both LM3915s and amplify the input signal

LMJ915

LMJ915

NO.1

NO.2

SIG

RHI
RJ
Ik

2~~

INPUT (IOV FUll SCALE)

RI
50

TL/H/5104-13

FIGURE 5. Low Cost Circuit for 60 dB Display
5-250

Application Hints (Continued)

lM3915

lM3915

NO.1

NO.2

INPUT
(lOV FUll SCALE)

TLIH15104-14

FIGURE 6. Improved Circuit for 60 dB Display
TIPS ON REFERENCE VOLTAGE
AND LED CURRENT PROGRAMMING

The circuit in Figure 8 shows how to add a LED intensity
control which can vary LED current from 9 mA to 28 mAo
The reference adjustment has some effect on LED intensity
but the reverse is not true.

SINGLE LM3915
The equations in Figure 7 illustrate how to choose resistor
values to set reference voltage for the simple case where
no LED intensity adjustment is required. A LED current of 10
mA to 20 mA generally produces adequate illumination.
Having 10V full-scale across the internal voltage divider
gives best accuracy by keeping signal level high relative to
the offset voltage of the internal comparators. However, this
causes 450 p.A to flow from pin 7 into the divider which
means that the LED current will be at least 5 mAo R1 will
typically be between 1 kO and 2 kO. To trim the reference
voltage, vary R2.

MULTIPLE LM3915s
Figure 9 shows how to obtain a common reference trim and
intensity control for two LM3915s. The two ICs may be connected in cascade for a 60 dB display or may be handling
separate channels for stereo. This technique can be extended for larger numbers of LM3915s by varying the values
of R1, R2 and R3 in inverse proportion to the number of
devices tied in. The ICs' internal references track within 100
mV so that worst case error from chip to chip is only 0.1 dB
for VREF = 10V.

LM3915

lM3915
RlO 22k TYP

RLO

RHI

I

22k TYP RHI

r .J\I'II\r .,

r.J\l'll\r .,

I

I

1

Adiust R2 to vary VREF

Pick Rl =

Pick R2

=

12.5V
'LED - VREF/2.2 kn

(VR1~~5~ /~~5V) + 0.08 rnA

TUH15104-15

FIGURE 7. Design Equations for Fixed LED Intensity

'9 rnA < ILED < 28 rnA

@

VREF

=

10V

TUH15104-16

FIGURE 8. Varying LED Intensity

5-251

.,...

~r---------------------------------------------------------------'

0)
CI)

:!E

Application Hints (Continued)
10

..J

LM391S

LM3915
NO.2

NO.1

TLIH15104-17

FIGURE 9. Independent Adjustment of Reference Voltage and LED Intensity for Multiple LM3915s
The scheme in Figure 10 is useful when the reference and
LED intensity must be adjusted independently over a wide
range. The RHI voltage can be adjusted from 1.2V to 10V
with no effect on LED current. Since the internal divider here
does not load down the reference, minimum LED current is
much lower. At the minimum recommended reference load
of 80 ,..A, LED current is about 0.8 mA. The resistor values
shown give a LED current range from 1.5 mA to 20 mAo
At the low end of the intensity adjustment, the voltage drop
across the 5100 current-sharing resistors is so small that
chip to chip variation in reference voltage may yield a visible
variation in LED intensity. The optional approach shown of
connecting the bottom end of the intensity control pot to a
negative supply overcomes this problem by allowing a larger
voltage drop across the (larger) current·sharing resistors.

Other Applications
For increased resolution, it's possible to obtain a display
with a smooth transition between LEOs. This is accomplished by varying the reference level at pin 6 by 3 dBp·p as
shown in Figure 11. The signal can be a triangle, sawtooth
or sine wave from 60 Hz to 1 kHz. The display can be run in
either dot or bar mode.
When an exponentially decaying RC discharge waveform is
applied to pin 5, the LMS915's outputs will switch at equal
intervals. This makes a Simple timer or sequencer. Each
time interval is equal to RCfS. The output may be used to
drive logic, opto·couplers, relays or PNP transistors, for example.

Typical Applications
LM391S

LMJ915
NO.2

NO.1

r -;
I
I
I
I
I
I

REF ADJ

L;;;1S:- - ,
PIN 7

,....-.......
B.2k

B.2k

INTENS\~~

SDk

-15V

510

510

I

6... _ _ _ ...1

"Optional circuit for improved intensity
matching at low currents. See text.

2k
LED
INTENSITY

TLIH15104-18

FIGURE 10. Wide-Range Adjustment of Reference Voltage and LED Intensity for Multiple LM3915s

5-252

Typical Applications (Continued)

lMl915

1.St

INPUT
(OVTO'IV)

3.SVplI
60Hz TO ,.H,

TL/H/5104-19

FIGURE 11. OV to 10V Log Display with Smooth Transitions
Extended Range VU Meter
INUU,

LED
NO.1

LMl918
MODE

L----+--+------+--------....---+---+---_V+nzVT02Dvl
-t-------------------'
"'
sm

..

nov FULLSCALEI*·-....
This application shows that the LED supply requires minimal filtering.

L-____________________

·See Application Hints for optional Peak or Average Detector.
tAdiust R3 for 3 dB difference between LED #11
and LED #12.

-+~

~~:

...."
TL/H/5104-20

Vibration Meter

r--.....--:-....--;....-:-1>-.,.....~..,....t__:_........,..1_-....-~-y+ (3YTO 20V)

~~~D1D

LED
NO.1

LM3915

!

c:::::::::IPIEZOELECTRIC
TRANSDUCER

,.
TL/H/5104-21

5-253

LED

Threshold

1
2
3
4
5
6
7
B
9
10

60mV
BOmV
110mV
160mV
220mV
320mV
440mV
630mV
B90mV
1.25V

....

It)

~

::E

Typical Applications (Continued)

...I

Indicator and Alarm, Full-Scale Changes Display From Dot to Bar
v' ,v

.,

111~

r 111 ., ...F 111 ~ rl1l~ , 111 ,

r

,. 111 , , 111

111' 111 '

~

12.

FI1I

27k

lED

15k

ND.IU

lED
NO.1

18

17

14

15

16

Il

12

,

v'

-¥

HlD

SI.

D1

r

HEF
DUT

HH'

l!...-...
~ avJ~v
INPUT

7

HEF
ADJ

-¥

62.

1011**

Uk

'::"

I'
'The input to the' dot bar switch may be taken from cath·
odes of other LEOs.

p

5k
"BRIGHTNESS"

MODE

Dl

lN9'4

DDT·BAR*
SWITCH

lM3915

~.

~

2N29D~

10

"

~

Display will change to bar as soon as the LED so selected begins to light.
"'·Optional. Shunts 100 p.A auxiliary sink current away from
LED # 1.
TLIHI5104-22

60 dB Dot Mode Display

-&7

lED,
NO.1

-54

f-

16

, r ., "

-51

f ., r~

-48

.,

-42

f~

-F-

- F-

17

-45

16

15

14

R6
2Dk

-39

111

~u
13

-36 m-30
~

r'"

111

~tU

12 ..... "

f

L-Jl

-¥

v'.

RU

3

-¥

J;Cl

S'O
5

-21

oZ,

-21

-18

.,r, [ ~ r,
111

':~ED

1...•
10

111

f-

• ~u

17

II

-15

"H.

HEF
OUT

REF
AOJ

•

~'

-12

~ f .,

-9

... -,
f ., rL•
DdB

r, r ., r

ED
0~0

NO.l1

18

15

....

LM3115

v-

v'

(t2VT020YI

I'

I'

"

10

LM3915

v-

MODE

1

19

1.

-¥

,

v'

RLO

SIO

-¥

5

RH.

REF
OUl

I!.- 7

"EF
ADJ

•

MODE

I'

H'

1k

HI
1k

1'2.,

H5

H.

12Dk

Uk

~~

1~3

"'..

,~

*

*
INPUT
(lOV FULL-SCALE)

'Optional. Shunts 100 /LA auxiliary sink current away from LED # 11.

TLlHI5104-23

5-254

Typical Applications

(Continued)
Driving Vacuum Fluorescent Display
v'

lzvrQ 15V

ANODE

FILAMENT

fiLAMENT

HI

VACUUM FLUORESCENT
BAR GRAPH

LO

R"

RIO

'"

R'

R"

R'

R"

R'

R..

GRID

':"'

R"

~

1B

..

" "

17

4.1k

R"

11

12

"

10

lM3915
V-

LJ'

-¥

v'

RLO

•

J

SI.

s

RHI

REF
OUT

REF
AOJ

, , ,

-¥

MODE

r---- - - - - - --Ri---'
I

I

I
I
I
I
I
I
I

D.

AUDI0-j

INPUT

L
I

.,

lOOk

1k

R2

0,

lOOk

...L..,.

..... T

O!.,

....

I
I

R'

Uk

~

I

.S

I

7.5k

I
I
I
I
I

..li-'-,

l1>

r+ ·

':"'

R7 thru R15: 10k ±10%
Dl, D2: lN914 or lN414B

"Half-wave peak detector.
See Application Hints.

I
I
t
II!.. ______________
~D
I
J
-5V

-15V

TL/H/S104-24

Low Current Bar Mode Display

v+

~~~~~~%~~~LED

I22VTD~MM....""""",...~",,,,*,~~.....~.-IM"'."""""'.. ND.l0
25V)

LED
NO.1

"
LM3915

.2
8.06k

Supply current drain is only 15 rnA with ten LEDs illuminated.

5-255

TUH/5104-25

.,...

It)

~

::a5

Typical Applications

(Continued)
Driving Liquid Crystal Display

...J

L1nUID CRYSTAL BAR GRAPH

REF
ADJ
8

MODE
9

10k

'::'

lN4001

DOT

I

120 VAC
60 Hz

I

8AR

+

II

22 ~F

Tl

'::'
TLIH/5104-26

Bar Display with Alarm Flasher
~ 100

~
LED
NO.1

-

-

, N"
~N~ ~N~ , N" 'N~ 'N~
..; 'N~ ~N~ 'N~ ' N
~.

- ...

...

17

18

16

....

15

14

13

~

12

frED
NO.l0
10

11

+
;:.':!:

LM3915

L-.JI

-¥

v+

RLO

3

-#

SIG
15

Rl
lk

RHI
6

REF OUT REF ADJ MODE
1

9

-=1!
,A

Full-scale causes the full bar display to flash. If the
junction of R1 and C1 is connected to a different LED
cathode, the display will flash when that LED lights,
and at any higher mput signal.

.

.

.

410
1.2k

- ...
TLlH15104-27

5-256

Typical Applications

(Continued)
Precision Null Meter

V+\5VTO 18V}

fJ

LED
NO.11

LED
NO.20

lM3915

1k
lM336

SOk

LED
NO.1

4.7k

lMJ915

vi-5V TO -iaVI

+

"-:r

10k

10k

Logarithmic response allows coarse and fine ad·
justments without changing scale.

_

INPUT

Resolution ranges from 10 mV at VIN = 0 mV to

v-

± t .25V.

~

500 mV at V'N

(-5V TO -IHV)

TL/H/5104-28

Operating with a High Voltage Supply (Dot Mode Only)
48V

3.9k
lW

J.g~

lN~Z

lW

'111

'111

17 111"

'11I~ , 111

~

'111

, 111

~

, 111

~ ,. ~I

"

11

10

LED

LED
NO.1

NO. 10

18

11

16

15

14

13

12

lMl915

L-Jl

3.4V·
The LED currents are approximately 10 mA, and
the LM3915 outputs operate in sa turation for
minimum dissipation.
*This point is partially regulated and decreases in
voltage with temperature. Voltage re quirements

-¥

v'

RLO

3

-¥

SlG

IN~U5T

RH'

REf
OUT

~7

REf
AOJ

~ MJ:E

'111

2N2ge5~

of the LM3915 also decrease with te mperature.

620

-!TLlH/5104-29

5-257

U)
.....
en
CO)

:::E

r---------------------------------------------------------------------------------,
Typical Applications (Continued)

..J

Light Meter
LED~

NO.1

.,~~

.,fl1 ~ .,~~ .,~ ~ ,~~ rfl1 ~ r,~~-.,fl1
~ ,fl1~ Ir~ ~ ~~ Ir# ~ rfl1 ~ r;;\1 ~ .,~~ r~~ rfl1 ~ ,~~ r~~ .,!
F-'
f"' - f"' - F-'

-

18

17

"

15

14

"

"

11

18

10

17

"

LM3915

v-

L-.J'

-¥

v'
3

RLO

•

sm

I.

15

"

12

LED
ND.
I.

,.

LM3915

RH'

•

5

REF
OUT

REF
AOJ

l' *

,

MODE

I"

-='2k -=

v-

.¥

v'
3

"LD

•

S,.

,

RH'

5

REF
OUT
1

~22

OFF

J:.N

11

REF
ADJ

,

MODE

I'

15k

":"9V

~r

~

.

3.911

1M'

6.211

'2,%1Ik

-=

~~ ~~

~~

B'

LM3D8A

3+

LM

!08

"

3 +

~

-r

~ T

'ODPF

'OOPF

*Resistor value selects exposure

1/2 IIstop resolution
Ten flstop range (1000:1)
Typ,cal supply current's 8 mAo
TL/H/51 04-30

Audio Power Meter
12VTO 2DV

Connection Diagram
Dual-In-Line Package
18

LEO Na.1

v-

v'

LM3!115

DIVIDER
(lOW ENOl

!

16 LED NO.4

•

15

,.

SIGNAL INPUT

13

DIVIDER &
(HIGH ENOl

H.
"'

"'

LEONa.S
LEO NO.1

LEO NO."

1

12 LEONO ••

REFERENCE ADJUST I

11 LEO NO.'

REFERENCE OUTPUT

1D

MODE SELECT

LOUDSPEAKER

LEO NO.2

n LEONa.3

"'

LEONO.ID

2.7.

TL/H/5104-32

Top View

"'

10k

Order Number LM3915N
See NS Package Number N18A

TLlH/5104-31

Load
Impedance

R1

40

10k

80

18k

160

30k

See Application Hints for optional Peak
or Average Detector

5-258

Definition of Terms
Absolute Accuracy: The difference between the observed
threshold voltage and the ideal threshold voltage for each
comparator. Specified and tested with 10V across the internal voltage divider so that resistor ratio matching error predominates over comparator offset voltage.
Adjust Pin Current: Current flowing out of the reference
adjust pin when the reference amplifier is in the linear region.

measured at the current source outputs. As the forward voltage of an LED does not change significantly with a small
change in forward current, this is equivalent to changing the
voltage at the LED anodes by the same amount.
Line Regulation: The average change in reference output
voltage (VREF) over the specified range of supply voltage
(V+).
Load Regulation: The change in reference output voltage
over the specified range of load current (IL(REF).
Offset Voltage: The differential input voltage which must
be applied to each comparator to bias the output in the
linear region. Most significant error when the voltage across
the internal voltage divider is small. Specified and tested
with pin 6 voltage (VRHI) equal to pin 4 voltage (VRLO).
Relative Accuracy: The difference between any two adjacent threshold points. Specified and tested with 10V across
the internal voltage divider so that resistor ratio matching
error predominates over comparator offset voltage

Comparator Gain: The ratio of the change in output current
(ILED) to the change in input voltage (VIN) required to produce it for a comparator in the linear region.
Dropout Voltage: The voltage measured at the current
source outputs required to make the output current fall by
10%.
Input Bias Current: Current flowing out of the signal input
when the input buffer is in the linear region.
LED Current Regulation: The change in output current
over the specified range of LED supply voltage (VLED) as

5-259

National

_

Semiconductor
Corporation

LM3916 Dot/Bar Display Driver
General Description
The LM3916 is a monolithic integrated circuit that senses
analog voltage levels and drives ten LEOs, LCDs or vacuum
fluorescent displays, providing an electronic version of the
popular VU meter. One pin changes the display from a bar
graph to a moving dot display. LED current drive is regulated and programmable, eliminating the need for current limiting resistors. The whole display system can operate from a
single supply as low as 3V or as high as 25V.

The LM3916 is very versatile. The outputs can drive LCDs,
vacuum fluorescents and incandescent bulbs as well as
LEOs of any color. Multiple devices can be cascaded for a
dot or bar mode display for increased range and/or resolution. Useful in other applications are the linear LM3914 and
the logarithmic LM39l5.

The Ie contains an adjustable voltage reference and an accurate ten-step voltage divider. The high-impedance input
buffer accepts signals down to ground and up to within 1.5V
of the positive supply. Further, it needs no protection
against inputs of ± 35V. The input buffer drives 10 individual
comparators referenced to the preCision divider. Accuracy is
typically better than 0.2 dB.

•
•
•
•
•
•
•
•
•
•
•
•

Features
Fast responding electonic VU meter
Drivers LEOs, LCDs, or vacuum fluorescents
Bar or dot display mode externally selectable by user
Expandable to displays of 70 dB
Internal voltage reference from 1.2V to 12V
Operates with single supply of 3V to 25V
Inputs operate down to ground
Output current programmable from 1 mA to 30 mA
Input withstands ± 35V without damage or false outputs
Outputs are current regulated, open collectors
Directly drives TTL or CMOS
The internal 10-step divider is floating and can be referenced to a wide range of voltages
The LM3916 is rated for operation from O·C to + 70·C. The
LM39l6N is available in an lB-lead molded DIP package.

Audio applications include average or peak level indicators,
and power meters. Replacing conventional meters with an
LED bar graph results in a faster responding, more rugged
display with high visibility that retains the ease of interpretation of an analog display.
The LM3916 is extremely easy to apply. A 1.2V full-scale
meter requires only one resistor in addition to the ten LEOs.
One more resistor programs the full-scale anywhere from
1.2V to l2V independent of supply voltage. LED brightness
is easily controlled with a single pot.

Typical Applications
OV TO 10V VU Meter
-20
-10
-7
-5
-3
-1
0
+1
+2
+3
VU
r--~--~t----4~--~--~.----e----~--~'---"----~--03V~vLED~V+

:I ~~~~~~~~~~~~~~~~~~~i~
LED"

I NO.1
Cl I
TANT~~~~~

- ..

- ~

- ~

18

17

16

..

13

I :~.~k

v+

12.5V

fLED =

Fi1 +

1*) +

VREF
2.2 kO

R2 x 80 /LA

11

10

I

REF
ADJ

MODE

~7

12VT020V-

= 1.25V ( 1 +

..... NO. 10

12

OUT

SfG

L-Jl
L ____ -- ........--+--e

VREF

- ~

REF

v+

V-

I

-...

14

LM3916

OR10pF'I'

ELEti~:~;~f~ I

- ~

15

SIGNAL
SOURCE

I

'"l'~
~

Note I: CapaCitor CI is required If
leads to tile LED supply are 6" or
longer.
Note 2: Circuit as shown is wired for
dot mode, For bar mode, connect pin
9 to pin 3. VLED must be kept below
7V or dropping resistor should be
used to limit Ie power dissipation.

TL/H17971-1

5-260

Absoh.ate Maximum Ratings
If Military! Aerospace specified devices are required,
contact the National Semiconductor Sales Office!
Distributors for availability and specifications.

Divider Voltage

Power Dissipation (Note 5)
Molded DIP (N)

Storage Temperature Range

25V

Voltage on Output Drivers

25V

-100 mVtoV+

Relerence Load Current

1365mW

Supply Voltage

±35V

Input Signal Overvoltage (Note 3)

10mA
- 55'C to + 150'C

Lead Temperature (Soldering, 10 seconds)

260'C

Electrical Characteristics (Note 1)
Parameter

Conditions (Note 1)

Min

Typ

Max

Units

3

10

mV

3

15

COMPARATORS
Offset Voltage, Buffer and First
Comparator

OV ,;: VRLO = VRHI ,;: 12V,
ILED = 1 mA

=

Offset Voltage, Buffer and Any Other Comparator

OV ,;: VRLO

Gain (AILED/AVIN)

I(REF)

Input Bias Current (at Pin 5)

OV ,;: VIN ,;: (V+ -1.5V)

Input Signal Overvoltage

No Change in Display

=

VRHI ,;: 12V, ILED

=

2 mA, ILED

=

1 mA
3

10 mA

8
25

-35

mV
mA/mV

100

nA

35

V

VOLTAGE DIVIDER
Divider Resistance

Total, Pin 6 to 4

8

12

17

kO

Relative Accuracy (Input Change
Between Any Two Threshold Points)

(Note 2)
-1 dB ,;: VIN ,;: 3 dB
-7dB';: VIN';: -1 dB
-10dB';: VIN';: -7dB

0.75
1.5
2.5

1.0
2.0
3.0

1.25
2.5
2.5

dB
dB
dB

Absolute Accuracy

(Note 2)
VIN = 2,1,0, -1 dB
VIN = -3, -5 dB
VIN = -7, -10, -20dB

-0.25
-0.5
-1

+0.25
+0.5
+1

dB
dB
dB

1.28

1.34

V

0.01

0.03

%IV

0.4

2

%

VOLTAGE REFERENCE
Output Voltage

0.1 mA,;: Il(REF) ,;: 4mA,
V+ = VLED = 5V

Line Regulation

3V,;: V+ ,;: 18V

Load Regulation

0.1 mA ,;: IL(REF) ,;: 4mA,
V+ = VLED = 5V

Output Voltage Change with Temperature

O'C,;:TA';: +70'C,Il(REF)
V+ = VLED = 5V

1.2

=

%

1

1 mA,

Adjust Pin Current

75

120

/LA

10

13

mA

0.12
1.2

0.4
3

mA
mA

0.1
1

0.25
3

mA
mA

1.5

V

0.15

0.4

V

0.1

100

/LA

0.1

100

/LA

150

450

/LA

OUTPUT DRIVERS

=

=

LED Current

V+

LED Current Difference (Between Largest
and Smallest LED Currents)

VLED
VLED

LED Current Regulation

2V ,;: VLED ,;: 17V

Dropout Voltage

ILED(ON) = 20 mA
AILED = 2 mA

Saturation Voltage

ILED

Output Leakage, Each Collector

Bar Mode (Note 4)

Output Leakage

Dot Mode (Note 4)

VLED

=
=

=

=

5V, IL(REF)

5V, ILED
5V, ILED

=
=

1 mA

7

2 mA
20 mA
ILED = 2 mA
ILED = 20 mA

@

VLED

2.0 mA, IL(REF)

=

=

5V,

0.4 mA

Pins 10-18
Pin 1

60
5-261

Electrical Characteristics (Note 1) (Continued)

I

Parameter

I

Conditions (Note 1)

I

Min

Typ

I

Max

Units

SUPPLY CURRENT
Standby Supply Current
(All Outputs Off)

I

. V+ = +5V,IL(REF) = 0.2 mA
V+ = +20V,IL(REF) = 1.0 mA

I

I

2.4
6.1

I

4.2
9.2

Nole 1: Unless otherwise stated, all specifications apply with the following conditions:

I

mA
mA

= 25'C, IL(REF) = 0.2 rnA, pin 9 connected to pin 3 (bar mode).

3 Voe ,;; V+ ,;; 20 Voc

-0.015V ,;; VRLO ,;; 12 Voe

TA

3 Voe ,;; VLEO ,;; V+

VREF, VRHI. VRLO ,;; (V + - 1.5V)

For higher power dissipations, pulse testing is used.

-0.015V ,;; VRHI ,;; 12 Voe

OV ,;; VIN ,;; V+ - 1.5V

Nole 2: Accuracy is measured referred to + 3 dB

= + 10.000 Voe at pin 5, with + 10.000 Voe at pin 6, and 0.000 Voe at pin 4. At lower full·scale voltages, buffer
and comparator offset voltage may a.dd significant error. See table for threshold voltages.

Note 3: Pin 5 input current must be limited to ± 3 rnA. The addition of a 39k resistor in series with pin 5 allows ± 1DOV signals without damage.

Nole 4: Bar mode results when pin 9 is within 20 mV of V+. Dot mode results when pin 9 is pulled at least 200 mV below V+ . LED" 10 (pin 10 output current) is
disabled if pin 9 is pulled 0.9V or more below VLEO.
Note 5: The maximum junction temperature of the LM3916 is 100"C. Devices must be derated for operation at elevated temperatures. Junction to ambient thermal
resistance is 55'C/W for the molded DIP (N package).

LM3916 Threshold Voltage (Note 2)
Volts

dB

3
2 ± %
1 ± %
o± %
-1 ± %

Volts

dB

Min

Typ

Max

9.985
8.660
7.718
6.879
5.957

10.000
8.913
7.943
7.079
6.310

10.015
9.173
8.175
7.286
6.683

5-262

-3 ± %
-5± %
-7 ± 1
-10 ± 1
-20 ± 1

Min

Typ

Max

4.732
3.548
2.818
1.995
0.631

5.012
3.981
3.162
2.239
0.708

5.309
4.467
3.548
2.512
0.794

Typical Performance Characteristics
Supply Current vs
Temperature

6.0

Operating Input Bias
Current vs Temperature

'"
~

5.B

I---""f-=:;;;;i--Ir-"::+""::::-i

~

1

5.6

I--i-:=....-F-;;+:;

!Z

5.4

1--1--1--1--1--1

'"

'"
B

-.....

"

~

.,u

'"
'"
~

1--1--1----'1----'1--1
25

50

15

25

TEMPERATURE re)

""z
~

0:

82

z

~



0.6

;;

0.4

a

.......: K, ... c_

?'

.....

0.2

20

30

I
I
I

V

D

10

D

15

20

25

LED CURRENT (mAl

LED Driver Current
Regulation

II.' r--.,.---.,.---.,.---.,.----.
11.0
m

"c

~

TA"2S"C

~

15

10

2A

/

o

40

;:

1/

~

c

-1

75

/

20

~

-2

25

/'"

z

~

20

LED Current vs
Referenced Loading

,

-

~

~

15

50

LED Driver Saturation
Voltage
z

LED CURRENT (rnA)

Input Current Beyond
Signal Range (Pin 5)

;;

TA"r e -

,

TEMPERATURE (OCI

i

25

LED Current-Regulation
Dropout

.........

s

1.27

TEMPERATURE eel

0:

84

~

~

1.28

(~CI

B6

'"'"u

<

"

1.29

15

50

TEMPERATURE

Reference Adjust Pin
Current vs Temperature

,.

~-I-::;;-f--f-;;;:Il---l 10.00 ~

~

5.2
S.D

10.20
lD.l0~

~

>

I

Reference Voltage vs
rT_e_m"Tp_e_r_atru_r_e...--_r---.

o

•
~

2.3

0.5 1.0 1.6 2.0 2.5 3.0 3.5 4.0

10

15

20

LED SUPPLY VOLTAGE tV)

REFERENCE LOAD CURRENT {mAl

TL/HI7971-~

Total Divider Resistance
vs Temperature
1.12

<1

!

1.08

OIVIO,ER

~

~

1.04

ti

1.02

~

2 -o.S

LM39';T r-A

:!. 1.06

~ 1.00

;; 0.98
is

./.- J_- ./

Common-Mode Limits

Output Characteristics
12

I
I

S
~ 1.10

DIVIDER PARALLEL

WITH STABLE
1Ir: RESISTOR

~ -1.0

_

~EFER~EO TO JOSITIV\_
SUPPLY VOLTAGE

;;

25

50

TEMPERATURE

15
(~C)

100

V+=5V
TA"25°C

~ODpA

/.

g .

~OOpA

I

~DDpA

J:..

:Ii -2,0

~

I

1mA

_

::::i -15

-

NEGATIVE COMMON-MOOELIMIT INCLUDES GROUND

US

-25

10

o

20

40

TEMPERATURE ('CI

&0

BO

IL(REFI'~OOpA

J

V

I

0.2

0.4

0.6

0.8

1.0

OUTPUT VOLTAGE(VI
TL/H17971-3

5-263

.....

U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

~

:s

Block Diagram

(Showing Simplest Application)
.- -

I

-

-

-

LED
V+

LM39i6- - - - - ,
COMPARATOR
1 OF 10

,
10

1087

970

B64
LED PROGRAM
CURRENT
769

1298

REF'

OUT
THIS LOAD
DETERMINES
LED
BRIGHTNESS

7

REFERENCE
VOLTAGE
SOURCE
1.2V
1031

-

REF
AOJ

I8

B19

-,

,I

V+

923

,,

--I

3

1531

708
RLO , 4

MODE
SELECT
AMPLIFIER

SIG
IN

I

CONTROLS
TYPE OF
DISPLAY, BAR
OR SINGLE
LED

,

~
I ':"
L____________ J
5

+

TL/H/7971-4

5-264

Functional Description
LM3916 Output Circuit

The simplified LM3916 block diagram is included to give the
general idea of the circuit's operation. A high input impedance buffer operates with signals from ground to 12V, and is
protected against reverse and overvoltage signals. The signal is then applied to a series of 10 comparators; each of
which is biased to a different comparison level by the resistor string.
In the example illustrated, the resistor string is connected to
the internal 1.25V reference voltage. As the input voltage
varies from 0 to 1.25, the comparator outputs are driven low
one by one, switching on the LED indicators. The resistor
divider can be connected between any 2 voltages, providing
that they are at least 1.5V below V+ and no lower than V-.

TL/H/7971-6

Outputs may be run in saturation with no adverse effects,
making it possible to directly drive logic. The effective saturation resistance of the output transistors, equal to RE plus
the transistors' collector resistance, is about 500. It's also
possible to drive LEDs from rectified AC with no filtering. To
avoid oscillations, the LED supply should be bypassed with
a 2.2 p.F tantalum or 10 p.F aluminum electrolytic capacitor.

INTERNAL VOLTAGE REFERENCE
The reference is designed to be adjustable and develops a
nominal 1.25V between the REF OUT (pin 7) and REF ADJ
(pin B) terminals. The reference voltage is impressed across
program resistor R1 and, since the voltage is constant, a
constant current 11 then flows through the output set resistor R2 giving an output voltage of:
VOUT = VREF (1

IL

+

:~)

+ IADJ R2

I

I

I

LM3916

r
•

MODE PIN USE
Pin 9, the Mode Select input, permits chaining of multiple
devices, and controls bar or dot mode operation. The following tabulation shows the basic ways of using this input.
Other more complex uses will be illustrated in the applications.
Bar Graph Display: Wire Mode Select (pin 9) directly to pin
3 (V+ pin).

REF
REF
OUT_ _ ADJ
7Rl

~EF

8

=.J

VOlUT

-.J

--[9

Dot Display, Single LM3916 Driver: Leave the Mode Select pin open circuit.

9

Dot Display, 20 or More LEDs: Connect pin 9 of the first
drivers in the series (i.e., the one with the lowest input voltage comparison points) to pin 1 of the next higher LM3916
driver. Continue connecting pin 9 of lower input drivers to
pin 1 of higher input drivers for 30 or more LED displays.
The last LM3916 driver in the chain will have pin 9 left open.
All previous drivers should have a 20k resistor in parallel
with LED #9 (pin 11 to VLED).

IADJ

R2

TL/H17971-5

Since the 120 p.A current (max) from the adjust terminal
represents an error term, the reference was designed to
minimize changes of this current with V + and load changes.
For correct operation, reference load current should be between BO p.A and 5 mA. Load capacitance should be less
than 0.05 p.F.

Mode Pin Functional Description
This pin actually performs two functions. Refer to the simplified block diagram below.
Block Diagram of Mode Pin Function

CURRENT PROGRAMMING
A feature not completely illustrated by the block diagram is
the LED brightness control. The current drawn out of the
reference voltage pin (pin 7) determines LED current. Approximately 10 times this current will be drawn through each
lighted LED, and this current will be relatively constant despite supply voltage and temperature changes. Current
drawn by the internal 10-resistor divider, as well as by the
external current and voltage-setting divider should be included in calculating LED drive current. The ability to modulate LED brightness with time, or in proportion to input voltage and other signals can lead to a number of novel displays or ways of indicating input overvoltages, alarms, etc.

OUTPUT NO.9

OUTPUT NO. 10

CDNTROLLED DRIVE {
(FROM COMPARATORS) .....

+---4--_-1"

II

The LM3916 outputs are current-limited NPN transistors as
shown below. An internal feedback loop regulates the transistor drive. Output current is held at about 10 times the
reference load current, independent of output voltage and
processing variables, as long as the transistor is not saturated.

5-265

Mode Pin Functional Description

(Continued)

DOT OR BAR MODE SELECTION

more) below VLEO. This condition is sensed by comparator
C2, referenced 600 mV below VLEO. This forces the output
of C2 low, which shuts off output transistor Q2, extinguishing LED #10.

The voltage at pin 9 is sensed by comparator C1, nominally
referenced to (V+ -100 mV). The chip is in bar mode when
pin 9 is above this level; otherwise it's in dot mode. The
comparator is designed so that pin 9 can be left open circuit
for dot mode.

VLEO is sensed via the 20k resistor connected to pin 11.
The very small current (less than 100 p.A) that is diverted
from LED # 9 does not noticeably affect its intensity.

Taking into account comparator gain and variation in the
100 mV reference level, pin 9 should be no more than 20
mV below V+ for bar mode and more than 200 mV below
V+ (or open circuit) for dot mode. In most applications, pin
9 is either open (dot mode) or tied to V+ (bar mode). In bar
mode, pin 9 should be connected directly to pin 3. Large
currents drawn from the power supply (LED current, for example) should not share this path so that large IR drops are
avoided.

An auxiliary current source at pin 1 keeps at least 100 p.A
flowing through LED # 11 even if the input voltage rises high
enough to extinguish the LED. This ensures that pin 9 of
driver # 1 is held low enough to force LED # 10 off when
any higher LED is illuminated. While 100 p.A does not normally produce significant LED illumination, it may be noticeable when using high-efficiency LEOs in a dark environment.
If this is bothersome, the simple cure is to shunt LED # 11
(and LED #1) with a 10k resistor. The 1V 1R drop is more
than the 900 mV worst case required to hold off LED #10
yet small enough that LED # 11 does not conduct significantly.

DOT MODE CARRY
In order for display to make sense when multiple drivers are
cascaded in dot mode, special circuitry has been included
to shut off LED # 10 of the first device when LED # 1 of the
second device comes on. The connection for cascading in
dot mode has already been described and is depicted in
Figure 1.

In some circuits a number of outputs on the higher device
are not used. Examples include the high resolution VU meter and the expanded range VU meter circuits (see Typical
Applications). To provide the proper carry sense voltage in
dot mode, the LEDs of the higher driver IC are tied to VLEO
through two series-connected diodes as shown in Figure 2.
Shunting the diodes with a 1k resistor provides a path for
driver leakage current.

As long as the input signal voltage is below the threshold of
the second driver, LED # 11 is off. Pin 9 of driver # 1 thus
sees effectively an open circuit so the chip is in dot mode.
As soon as the input voltage reaches the threshold of LED
# 11, pin 9 of driver # 1 is pulled an LED drop (1.5V or

r-20'

,,flI ~ ,flI ~ ,flI ~ ,flI
vfll~ ,flI , ,flI ,,flI
F-'
••

17

v-

i..-...l'

~

'0

.11'

P

15

"LO

I'

"

13

12

VUD

,flI , ,;ff. ~ ,~~ ,flI ,,flI ,,flI ,,flI ,,flI
,flI ,,flI
, ,;ff.
r- ~
r rfll~
F-'
r
."
"
11

'0
'0

~

11

18

17

15

LM3914115116

lM3914115/1&

NO.1

NO.2

SlG

I'

"H.

10

REF

REF

OUT

AOJ

I'

I'

,

MODE

•

v-

~

II'

I'

"La

."

12

13

"G
I'

.0

11

20

2.:!~

RH'

REF

REF

OUT

AOJ

MODE

1

I'

I'

..~

6

l'

Nt

TLlH/7971-8

FIGURE 1. Cascading LM3914/15/16 Series in Dot Mode
IN9t4 IN9t4

III

12

"

III

,.

III

13

"

LM3915. lMJ916

LMJ9t5.lM3916

NO.1

NO.2

12

III

11

III

'0

TL/H/7971-9

FIGURE 2. Cascading Drivers in Dot Mode with Pin 1 of Driver #2 Unused

5-266

r

should be run at 20 mA to 30 mA for high enough average
intensity.

Mode Pin Functional
Description (Continued)

True average or peak detection requires rectification. If an
LM3916 is set up with 10V full scale across its voltage divider, the turn-on pOint for the first LED is only 450 mV. A
simple silicon diode rectifier won't work well at the low end
due to the 600 mV diode threshold. The half-wave peak
detector in Figure 3 uses a PNP emitter-follower in front of
the diode. Now, the transistor's base-emitter voltage cancels out the diode offset, within about 100 mV. This approach is usually satisfactory when a single LM3916 is used
for a 23 dB display.
Display circuits such as the extended range VU meter using
two or more drivers for a dynamic range of 40 dB or greater
require more accurate detection. In the precision half-wave
rectifier of Figure 4 the effective diode offset is reduced by a
factor equal to the open-loop gain of the op amp. Filter capacitor C2 charges through R3 and discharges through R2
and R3, so that appropriate selection of these values results
in either a peak or an average detector. The circuit has a
gain equal to R2/R1.
It's best to capacitively couple the input. Audio sources frequently have a small DC offset that can cause Significant
error at the low end of the log display. Op amps that slew
quickly, such as the LF351 , LF353 or LF356, are needed to
faithfully respond to sudden transients. It may be necessary
to trim out the op amp DC offset voltage to accurately cover
a 60 dB range. Best results are obtained if the circuit is
adjusted for the correct output when a lOW-level AC signal
(10 to 20 mV) is applied, rather than adjusting for zero output with zero input.

OTHER DEVICE CHARACTERISTICS
The LM3915 is relatively low-powered itself, and since any
number of LEOs can be powered from about 3V, it is a very
efficient display driver. Typical standby supply current (all
LEOs OFF) is 1.6 mA. However, any reference loading adds
4 times that current drain to the V + (pin 3) supply input. For
example, an LM3915 with a 1 mA reference pin load (1.3k)
would supply almost 10 mA to every LED while drawing only
10 mA from its V+ pin supply. At full-scale, the IC is typically
drawing less than 10% of the current supplied to the display.
The display driver does not have built-in hysteresis so that
the display does not jump instantly from one LED to the
next. Under rapidly changing signal conditions, this cuts
down high frequency noise and often an annoying flicker.
An "overlap" is built in so that at no time are all segments
completely off the dot mode. Generally one LED fades in
while the other fades out over a 1 mV range. The change
may be much more rapid between LED # 10 of one device
and LED # 1 of a second device cascaded.

Application Hints
The most difficult problem occurs when large LED currents
are being drawn, especially in bar graph mode. These currents flowing out of the ground pin cause voltage drops in
external wiring, and thus errors and oscillations. Bringing the
return wires from signal sources, reference ground and bottom of the resistor string to a single point very near pin 2 is
the best solution.
Long wires from VLED to LED anode common can cause
oscillations. The usual cure is bypassing the LED anodes
with a 2.2 ).£F tantalum or 10 ).£F aluminum electrolytic capacitor. If the LEd anode line wiring is inaccessible, often a
0.1 ).£F capaCitor from pin 1 to pin 2 will be sufficient.
If t~ere is a large amount of LED overlap in the bar mode,
OSCillation or excessive noise is usually the problem. In
cases where proper wiring and bypassing fail to stop oscillations, V+ voltage at pin 3 is usually below suggested limits.
When several LEOs are lit in dot mode, the problem is usually an AC component of the input signal which should be
filtered out. Expanded scale meter applications may have
one or both ends of the internal voltage divider terminated
at relatively high value resistors. These high-impedance
ends should be bypassed to pin 2 with 0.1 ).£F.

If (5V TO "VI

R.

+--I....~.....- _ OUTPUT

I.
INPUT *.~",,"""'''''-l

R2
1M

R3

lOOk

'DC Couple
TL/H/7971-IO

FIGURE 3. Half-Wave Peak Detector
R3
'I.

...---'l.M..--_ OUTPUT
"2
lOOk

Power diSSipation, especially in bar mode should be given
consideration. For example, with a 5V supply and all LEOs
programmed to 20 mA the driver will dissipate over 600 mW.
In this case a 7.50 resistor in series with the LED supply will
cut device heating in half. The negative end of the resistor
should be bypassed with a 2.2 ).£F solid tantalum or 10 ).£F
aluminum electrolytic capacitor to pin 2.

CI
INPUT

-II""

02

t-MI\r-+--~f--'"

01,02: lN914 or lN4148

TIPS ON RECTIFIER CIRCUITS
The simplest way to display an AC signal using the LM3916
is to apply it right to pin 5 unrectified. Since the LED illuminated represents the instantaneous value of the AC waveform, one can readily discern both peak and average values
of audio signals in this manner. The LM3916 will respond to
positive half-cycles only but will not be damaged by Signals
up to ± 35V (or up to ± 100V if a 39k resistor is in series
with the input). A smear or bar type display results even
though the LM3916 is connected for dot mode. The LEOs

Average Peak
R2

1k

100k

R3

100k

1k

Rl = R2forAv = 1
Rl = R2/10 for Av = 10
Cl = 10/RI
TL/H17971-11

FIGURE 4. Precision Half-Wave Rectifier
5-267

:s:
Co)

CD
-"

en

Application Hints (Continued)
For precision full-wave averaging use the circuit in Figure 5.
Using 1% resistors for R1 through R4, gain for positive and
negative signal differs by only 0.5 dB worst case. Substituting 5% resistors increases this to 2 dB worst case. (A 2 dB
gain difference means that the display may have a ± 1 dB
error when the input is a nonsymmetrical transient). The
averaging time constant is R5.C2. A simple modification
results in the precision full-wave detector of Figure 6. Since
the filter capacitor is not buffered, this circuit can drive only
high impedance loads such as the input of an LM3916.

fication C165. The LM3916's outputs correspond to the meter indications specified with the omission of the - 2 VU
indication. The VU scale divisions differ slightly from a linear
scale in order to obtain whole numbers in dB.
Some of the most important specifications for an AC meter
are its dynamic characteristics. These define how the meter
responds to transients and how fast the reading decays.
The VU meter is a relatively slow full-wave averaging type,
specified to reach 99% deflection in 300 ms and overshoot
by 1 to 1.5%. In engineering terms this means a slightly
underdamped second order response with a resonant frequency of 2.1 Hz and a Q of 0.62. Figure 7 depicts a simple
rectifierIfilter circuit that meets these criteria.

AUDIO METER STANDARDS
VUMeter
The audio level meter most frequently encountered is the
VU meter. Its characteristics are defined as the ANSI speci-

C2
OAI

R6
610
RS
200k

CI
0.2

R4
200k

-.J

R5
200k

Cl

INPUT. ~p---"",~-_.....__"",~_......

0.2
~

INPUT.
RI
lOOk R2
lOOk

R4

04

200k

~~--W'lr-,:,:",-+----l"--"
AI
lOOk R2
1011'

OUTPUT

01.02.03.04: lN914 OR lN414B
01.02: lN9140r lN414B

Attack and decay time to DIN PPM
spec. Response down 1 dB for 10 ms
tone burst. Decays 20 dB in 1.5s.

TL/H/7971-12

TL/H17971-13

FIGURE S. Precision Full-Wave Average Detector

CI
0.041 "F

FIGURE 6. Precision Full-Wave Peak Detector

GAIN

RS

10

100k
1M

R3
300K

AUOIO~
INPUT

A4

150k

RI

RS

R6

C2

C3

43k 2.0 0.56 p.F
100k 1.0 0.056 p.F

Design Equations

20k R2

1
R5 o R6oC2oC3

20k
01

= "'02 = 177 sec -

2

C3
1 ('
1
1
1)
"'0
C2
R3 + R4
+ As
+ As
=Q
= 21.5 sec -

R3 = 2R4
Rl = R2 -< R4
......-

..... OUTPUT

AI. A2:

'Iz LF353

01.02: lN914 OR lN414B
'Reaches 99% level at 300 ms aiter applied
tone burst and overshoots 1.2%.
TL1H17971-14

FIGURE 7. Full·Wave Average Detector to VU Meter Specifications'

5-268

1

r-

Application Hints

==

(Continued)

Co)

Peak Program Meter

namic range, the LM3916 may be cascaded with the 3 dB/
step LM3915s. Alternatively, two LM3916s may be cascaded for increased resolution over a 28 dB range. Refer to the
Extended Range VU Meter and High Resolution VU Meter in
the Typical Applications section for the complete circuits for
both dot and bar mode displays.
To obtain a display that makes sense when an LM3915 and
an LM3916 are cascaded, the - 20 dB output from the
LM3916 is dropped. The full-scale display for the LM3915 is
set at 3 dB below the LM3916's -10 dB output and the rest
of the thresholds continue the 3 dB/step spacing. A simple,
low cost approach is to set the reference vOltage of the two
chips 16 dB apart as in Figure 5. The LM3915, with pin 8
grounded, runs at 1.25V full-scale. R1 and R2 set the
LM3916's reference 16 dB higher or 7.89V. Variation in the
two on-chip references and resistor tolerance may cause a
± 1 dB error in the -10 dB to -13 dB transition. If this is
objectionable, R2 can be trimmed.
The drawback of the aforementioned approach is that the
threshold of LED #1 on the LM3915 is only 56 mY. Since
comparator offset voltage may be as high as 10 mY, large
errors can occur at the first few thresholds. A better approach, as shown in Figure 9, is to keep the reference the
same for both drivers (10V in the example) and amplify the
input signal by 16 dB ahead of the LM3915. Alternatively,

The VU meter, originally intended for signals sent via telephone lines, has shortcomings when used in high fidelity
systems. Due to its slow response time, a VU meter will not
accurately display transients that can saturate a magnetic
tape or drive an amplifier into clipping. The fast-attack peak
program meter (PPM) which does not have this problem is
becoming increasingly popular.
While several European organizations have specifications
for peak program meters, the German DIN specification
45406 is becoming a de facto standard. Rather than respond instantaneously to peak, however, PPM specifications require a finite "integration time" so that only peaks
wide enough to be audible are displayed. DIN 45406 calls
for a response of 1 dB down from steady-state for a 10 ms
tone burst and 4 dB down for a 3 ms tone burst. These
requirements are consistent with the other frequently encountered spec of 2 dB down for a 5 ms burst and are met
by an attack time constant of 1.7 ms.
The specified return time of 1.5s to -20 dB requires a 650
ms decay time constant. The full-wave peak detector of
FIGURE 6 satisfies both the attack and decay time criteria.
Cascading The LM3916
The LM3916 by itself covers the 23 dB range of the conventional VU meter. To display signals of 40 dB or 70 dB dy-31

-34

-31

-28

-25

-22

-19

-16

-13

-10

-1

CD
......

en

-5
10

LMJ915

VREFI
7.BSV
-1.25

~

1.25V

~

6.31

~

LMl916

VREF2 '" 7.BSV
16dB
R2
9.09k

INPUT (7.9V FULL·SCALE)

TLlH17971-15

FIGURE 8. Low Cost Circuit for 40 dB Display
-10

-7

-5

-3

+1

-1

+2

+3 dB

10

LMJ916

LM3915

SIG
5

RHI

6

"::"

RJ
1.5k

R2
33k

REF

REF

OUT

ADJ

1

8

MODE

9

R4
5k

Rl

6.2k

R5

II

7k

Rl

+

R2

-R-,-~6.3'
~

16dB

INPUT
(lOV FULL SCALE)

FIGURE 9. Improved Circuit for 40 dB Display

5-269

TL/HI7971-16

.,...
~

0)
C')

:E
....I

r-------------------------------------------------------------------------------~

causes 1 mA to flow from pin 7 into the divider which means
that the LED current will be at least 10 mA. R1 will typically
be between 1 k!l and 5 k!l. To trim the reference voltage,
vary R2.
The current in Figure 11 shows how to add a LED intensity
control which can vary LED current from 5 mA to 28 mA.
Choosing VREF = 5V lowers the current drawn by the ladder, increasing the intensity adjustment range. The reference adjustment has some effect on LED intensity but the
reverse is not true.

Application Hints (Continued)
instead of amplifying, input signals of sufficient amplitude
can be fed directly to the LM3916 and attenuated by 16 dB
to drive the LM3915.
To extend this approach to get a 70 dB display, another
30 dB of amplification must be placed in the signal path
ahead of the lowest LM3915. Extreme care is required as
the lowest LM3915 displays input signals down to 2 mY!
Several offset nulls may be required. High currents should
not share the same path as the low level signal. Also power
line wiring should be kept away from signal lines.

Multiple Drivers
Figure 12 shows how to obtain a common reference trim
and intensity control for two drivers. The two ICs may be
connected in cascade or may be handling separate channels for stereo. This technique can be extended for larger
numbers of drivers by varying the values of R1, R2 and R3.
Because the LM3915 has a greater ladder resistance, R5
was picked less than R7 in such a way as to provide equal
reference load currents. The ICs' internal references track
within 100 mV so that worst case error from chip to chip is
only 0.2 dB for VREF = 5V.

TIPS ON REFERENCE VOLTAGE AND LED CURRENT
PROGRAMMING
Single Driver
The equations in Figure 10 illustrate how to choose resistor
values to set reference voltage for the simple case where
no LED intensity adjustment is required. A LED current of
10 mA to 20 mA generally produces adequate illumination.
Having 10V full-scale across the internal voltage divider
gives best accuracy by keeping Signal level high relative to
the offset voltage of the internal comparators. However, this

lM391&

lM3916
RlO 10k TYP

AlO 10k TYP RHI

RHI

r-'Wlr.,

r..JVtAr .,

I

VRL R2

~ :-_.:.:12::..5;:.:V,--c'LED - VREF/1kfi

Pick R2 ~

I

RI

1

Adjust R2 to vary VREF
Pick R1

I

I

(VREF - 1.25V)
1.25V!R1 + 0.08 rnA

5 rnA ,; 'LED'; 28 rnA

TLlH/7971-17

@

VREF ~ 5V

FIGURE 10. Design Equations for Fixed LED Intensity
TLlH/7971-18

FIGURE 11_ Varying LED Intensity

lMl916

lM3915
RlO 22k TVP

ALO 10k TYP

RHI

Ir~'I

REF

REF

OUT

AOJ

"HI

r~'

I

I

REF
OUT

REF
ADJ

8

A'

A'

2.4k

2.2k

AS

A1

2.2k

"

MOOE

,

AJ
Jk

lEO
INTENSITY

Al
10k
REFERENCE
TRIM

RZ
2k

5 rnA ,; 'LED'; 28 rnA
@

VREF

~

5V

TLlH17971-19

FIGURE 12_ Independent Adjustment of Reference Voltage and LED Intensity for Multiple Drivers

5-270

,-------------------------------------------------------------------------------------, r-

5:
w

Application Hints (Continued)
The scheme in Figure 13 is useful when the reference and
LED intensity must be adjusted independently over a wide
range. The RHI voltage can be adjusted from 1.2V to 10V
with no effect on LED current. Since the internal divider here
does not load down the reference, minimum LED current is
much lower. At the minimum recommended reference load
of 80 /LA, LED current is about 0.8 rnA. The resistor values
shown give a LED current range from 1.5 rnA to 25 rnA.

connecting the bottom end of the intensity control pot to a
negative supply overcomes this problem by allowing a larger
voltage drop across the (larger) current-sharing resistors.

Other Applications
For increased resolution, it's possible to obtain a display
with a smooth transition between LEDs. This is accomplished by superimposing an AC waveform on top of the
input level as shown in Figure 14. The signal can be a triangle, sawtooth or sine wave from 60 Hz to 1 kHz. The display
can be run in either dot or bar mode.

At the low end of the intensity adjustment, the voltage drop
across the 510.0. current-sharing resistors is so small that
chip to chip variation in reference voltage may yield a visible
variation in LED intenSity. The optional approach shown of

lMJ916

lM3916

r -;L;;15:---'
PIN 7

,.......-......

I

6.Bk

6.Bk

INTENS~~~

SDk

-15V

I
I
I

SID

I
I
I

SID

b... _ _ _ ...J

1.25V';; VREF ,;; lOV

·Optional circuit for improved intenSity
matching at low currents. See text.

1.5 rnA ,,; ILED ,,; 25 rnA

TL/H/7971-20

FIGURE 13. Wide-Range Adjustment of Reference Voltage and LED intensity for Multiple Drivers

lM3916
REF

'OJ
INPUT

IOV TO 10VI

2.

lOOk

12.

0

0

~

: : ••

6oH.TolkH.

TLlH17971-21

FIGURE 14. OV to 10V VU Meter with Smooth Transitions

5-271

CD
.....

en

LM3916
-I
'<

Extended Range VU Meter (Bar Mode)

'0

IN4001

)~:

I:;O~I

-40

-37

-34

-31

-28

-25

-22

-19

c:r

!.
:I>

'0

'2.

-I:!:..
*2.2
-16

-13

,~,.+,~,.
,~~+,~
,~~+f"?
,~~+f"?
,~~+f"?
,~~
,~~..+f"?
N~~~+P
P +
P ..
+f"?
0?
.. -,~~+f"?
.. ~

'""

18

....

~

17

16

IS

'"14"

.. .

13

'""

12

- -'""
II

10

n:

~.

-

6.3 VAC CENTER·TAPPED

o::s·

In
-10

-7

-5

-3

V-

~

"'"

I\)

---'I

~

v+

3

RLD

*

SIG
5

0

+1

+2

+l d

,fl1
'"" ..

'§

~,~,.+~
,~~+~
,~~+,~~
,~~
,~~
,~~+~
~ ~g.DI9
P +
P+
P + P +~

+0?

-,""

18

-

fj7

-

Ts

-~

LMl915
01

-I

-'"" -'"" -'"" 14

13

12

II

'""

10

:::J

3<:
CD

.s

LM3916
RHI

REF
OUT

~7

REF
ADJ
8

MODE
9

V+

V-

NI~

R2
:.Ik

-¥

RLO
3

~

SIG
5

RHI

REF
OUT

~7

REF
ADJ
8

MODE
9

.RI
·.Ik
V+ (12V TO 20V)

INPUT (7.8V FULL·SCALE)*
R4
330k

--

R3
•• 62k

-""
TLlH17971-22

This application shows that the LED supply requires minimal filtering.
·See Application Hints for optional Peak or Average Detector.

t Adjust R3 for 3 dB difference between LED
and LED #12
R3
- - - ~ 0.158 ~ -16dB
R3 + R4

#

11

~

"!!!.
(i'
~

""2(i'

CI)

Extended Range VU Meter (Dot Mode)
R6
20k

-40

~
N~~~~ '•

R6
10k'

-37

·-34

-31

-28

-,'"

~

~ ~~ ~u

~ ~~
'-

lB

f-

17

-

-25

.

N

~16

N

15

-22

~

14

-19

r ~r
f-

- '-

13

12

,

~-13

01

11

D2

-10
R3
lk

~f ~ ...
'--<

0'

............
..- ,..yy

.~r
roo

.--

10

-7

., f...

-

18

-5

-3

-~ ,~ ~N

f-

16

17

-

15

-1

~

;"
...
14

.,

0

j

,"

+2

~ ~- ~ r~
'fN

13

12

+3
dB

~

-

til
N

o
t-~ 0.19

11

10

REF
AOJ
B

MODE

"0
o

aoj"
c:
(I)

.&

~

LM3916

lM3915

~

vL--.Jl

"c.>

-¥

v+
3

RLO

SIG

-¥

5

REF
OUT

REF
ADJ

~7

8

RHI

+

v-

MODE

I!..-

:
N1

v'
3

-¥

RLO

-¥

SIG
5

RHI

~7

R5
33k

R4
6.2k

.~J
p.,

ary

rent away from LED #: 1.

J:

~R2
• lk

Rl
lk

~~Cl

~2.2

REF
OUT

...~

y

*

~

3
INPUT
(1.25V FUll·SCALE)

tSee Application Hints for optional peak or aver-

age detector.

TL/H/7971-23

9~6ew,

II

Typical Applications (Continued)
Driving Vacuum Fluorescent Display
V'
IZYTOIIV
YACUUMfLUORESCE'T
BAR GRAPH

fiLAMENT
LO

flLAMENu
HI
RIB

':' RIOL-o_.,......._~O;;;ISr;;LA;;;YA;;:';:OO::;ES~_r-"'T'"-iGR?1D

IJO
Rl1

RI

RIZ

RI

R13

RT

RIB
RIS
IS

11

IS

«

IS

13

IZ

11

"

LM39IB

V'

Y-

RLO

SIG

RHI

REf
OUT

REf
AOJ MODE

r--------- ~-----,
I

I
I
I

D.1
AUDID-.J

I

::

1

Rl

RI

lOOk

R4

It

I
':' I
..
I
I~,
I
Lf35~ I
'/
I
V'
I

,ftIr....w..-++I"'M-.

INPUTI~

I

.L, I

:"1

IIDk

T1.0

~

I

I

R5
12k

r

I
I
I

R7 thru R1S: 10k±10%
01,02: lN914 or lN4148
'Half·wave peak detector.
See Application Hints.

I

II:. ______________
-IV:;-15V
JI
TLlH17971-24

Indicator and Alarm, Full-Scale Changes Display From Dot to Bar

N
LED
NO.1

N

N

N

N

N

N

N

N

m

120

LED
NO.l0

lB

17

16

15

14

13

12

11

10

LM3916

'The input to the Dot·Bar switch may
be taken from cathodes of other
LEOs. Display will change to bar as
soon as the LED so selected begins
to light.
"Optional. Shunts 100 ,.A auxiliary
sink current away from LED # 1.
TL/H17971-25

5-274

:J
"C

2'

l>

"C

"2C=;'

-

High Resolution VU Meter (Bar Mode)

....,.........

-23 VU

17LEOS

-18

-13

-8

-10

-5

-6

-3

-4

-2

-1

f~r!r!*N*NftN!/f·N
16

11

18

1.

15

13

12

m

OVU

10

"

+1

flC

NC

flO

117

116

NC

1,5

12

14

~

~

~

i

A7

m

01

.N

+

14

~N ~N
13

fN ~N T..1."

+4

12

+5VU

0'

3V::;VLEO::;6V

~

til

g;

10PF

11

;a
s·

10":'

c:

~

LM3916

LM3016

Jl

+3

+2

Jl

7

~

~

~7

3~

~R4
2k

A3
2k
...A.

(12V TO

2~~'

4 •

• •

INPUT*

(0 VU • 10V. ~
5 VU • 17.78V)

•

VII\,

•

Rl

R2

23.2k
1%

~30.1k

'f 1%

*See Application Hints for optional peak or average detector.

R2

- - - '" 0.562
Rl

+

R2

~

*

R5

Uk

*

TL/H/7971 -26

-5dB

orRl '" 0.788 o R2

9~6£W'

iii

LM3916

~

'0
(;'

High Resolution VU Meter (Dot Mode)

-23 VU

-13

-10

-8

-6

-3

-4

-1

-Z

., ,/1/ ., ,/1/ , /1/ ,/1/ , ,/1/., ,/1/, /1/ ,/1/.,

-.. -

F-18

- ~17 ~ 16
10.

_

F-15

-

'"14"

~13 ~

-

10.

lZ

OVU

,/1/ ,

_

F-

11

,

e!.

Dl
lN914

D2
lN914

....

.... ,

/1/...

,

:J>

'0

'2.
+1

NC

- F-

10

NC

118

117

NC
116

(;'

I»

lk

NC
115

+Z

+3

+5 VI

-+4

/1/ ,,/1/ , ,/1/ , ~/1/ ~~./1/

~~14

_10.

_

13

F-

12

..;

L

11

S'
:::::J

UI

'0
o

a..

::>

c:
CD

So
lM3916

lM3916

v+

v-

en

r\J

~1

-.J

m

~

3

RlD

4!

R8*
10k

5

•

REF
OUT

REF
ADJ

MODE

~7

8

19

RHI

SIG

~;k

V-

l

l
Nc

-¥

12 '-_ _--.;3+-+-....

40 kn

yeo
4

o
.....
U'I

Rt

TIMING
RESISTOR

LMC567

y s - - -.....~I--

TL/H/B670-1

Order Number LMC567CM or LMC567CN
See NS Package Number M08A or NOBE

5-283

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
2Vp _p
Input Voltage, Pin 3
Supply Voltage, Pin 4

10V

Output Voltage, Pin 8

13V

Voltage at All Other Pins

Storage Temperature Range

Vsto Gnd

Output Current, Pin 8

500mW

Operating Temperature Range (TA)

260'C
215'C
220'C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

30mA

Package Dissipation

-55'Cto +150'C

Soldering Information
Dual-ln·Line Package
Soldering (10 sec.)
Small Outline Package
Vapor Phase (60 sec.)
Infrared (15 sec.)

- 25'C to + 125'C

Electrical Characteristics
Test Circuit, TA

Symbol
14

=

25'C, Vs

=

5V, RtCt #2, Sw. 1 Pos. 0, and no input, unless otherwise noted.

Parameter
Power Supply Current

Conditions
RtCt # 1, Quiescent
or Activated

Min

=

Max

Units

0.5

0.8

mAdc

0.8

1.3

Typ

2V

0.3

Vs = 5V

=

Vs

Vs

9V

V3

Input D.C. Bias

0

R3

Input Resistance

40

18

Output Leakage

1

fo

Center Frequency,
Fosc + 2

RtCt # 2, Measure Oscillator
Frequency and Divide by 2

afo

Center Frequency
Shift with Supply

fol9V - fol2V X 100
7 folsv

Yin

input Threshold

Set Input Frequency Equal to fO
Measured Above, Increase Input
Level Until Pin 8 Goes Low.

Vs

=

2V

Vs

=

5V

Vs

=

9V

mVdc
k!l
100

nAdc

113

kHz

1.0

2.0

%N

98
92

103
105

Vs

=

2V

11

20

27

Vs

=

5V

17

30

45

Vs

=

9V

mVrms

45

aVin

Input Hysteresis

Starting at Input Threshold, Decrease Input
Level Until Pin 8 goes High.

V8

Output 'Sat' Voltage

Input Level> Threshold
Choose RL for Specified 18

18

=

2mA

0.06

18

=

20mA

0.7

Measure Fosc with Sw. 1 in
Pos. 0, 1, and 2;

Vs

=
=

2V

7

11

15

Vs

5V

11

14

17

%

Vs

=

9V

±1.0

%

L.D.B.W.

Largest Detection
Bandwidth

L.D.B.W

=

Fosclp2 - Fosclp1 X 100
Fosclpo

1.5

mVrms
0.15

Vdc

15

aBW

Bandwidth Skew

Skew

f max

Highest Center Freq.

RtCt #3, Measure Oscillator Frequency and
Divide by2

700

kHz

Yin

Input Threshold
atfmax

Set Input Frequency Equal to f max measured
Above, Increase Input Level Until Pin 8 goes Low.

35

mVrms

=

(Fosclp2 + Fosclp1 - 1) x 100
2 Fosclpo

5-284

0

r

s::
o

Test Circuit

U1

Vs

rl';~
_B.5k:dl~
1

SW.l
0

13
-=

0.01 jJf

-~:

D~
-= 0.001
V3

,:',,3:-

Rt

Ct

#1
#2
#3

lOOk
10k
5.1k

300pF
300pF
62pF

VB

7~

:J Q

LMC567

\J

3

14

--+

:J ~"'

8

2

jJf

SOD.

--

1

RtCt

S

4

WITH

MEASURE f osc
~ 10 pf PROBE

Rt-=
I

--.f
TLlH/8670-2

Typical Performance Characteristics
Supply Current vs.
Operating Frequency
1.2

0.8
Q.6

'"

OA

RI=5.1 kll
RI=100kll

1

....- /
'"

!

~g
~

35

0.2
0

17
TEST CIRCUIT,VS = 5V,
RIC! #2

250

10k

lOOk

~
~

0

~

150

i5

100

IN

2

i:'

"-

.

l:l

oJ?

103

-

102

Jxm

g

:

oJ?

0

2

4

6

12
11

8 10 12 14 16 18

8 10 12 14 16 18

BANDWIDTH (% OF F0)

-so

0

35

~
~

100

Frequency Drift
with Temperature

Frequency Drift
with Temperature

ISO

3.0
TEST CIRCUIT, RICI#2

2.0

, r-.... v!J

0.5
0

......

g

i\.

1.0

~

oJ?

,

-0.5

-1.5

50

TEMPERATURE (OC)

35
w

I

I'.

0

I'

-1.0

Vs=5V
-2.0

-1.0

10
0

13

TEST CIRCUIT, RIC! #1

~:

.......

14

BANDWIDTH (% OF F

1.0

,

6

1.5

\

104

4

15

ol

T. =25"C, Vs=5V

!

~

INPUT THRESHOLDJ 0

Bandwidth as
a Function of C2

105

~

/

50

INPUT FREQUENCY (Hz)

106

TEST CIRCUIT,Vs =5V,RIC!#2
16

200

0
lk

Largest Detection
Bandwidth vs. Temp.

300

T.= 25OC. Vs = 5V

1.0

]:

Bandwidth vs.
Input Signal Level

-so

-3.0
0

50

100

TEMPERATURE (OC)

150

-so

0

so

"100

150

TENPERATURE (OC)
TL/H/8670-3

5-285

aI

......

~

CD
10

r-------------------------------------------------------------------------------------,

o

Applications Information

....I

GENERAL

INPUT PIN

The LMC567 low power tone decoder can be operated at
supply voltages of 2V to 9V and at input frequencies ranging
from 1 Hz up to 500 kHz.

The input pin 3 is internally ground-referenced with a nominal 40 kD. resistor. Signals which are already centered on
OV may be directly coupled to pin 3; however, any d.c. potential must be isolated via a coupling capacitor. Inputs of
multiple LMC567 devices can be paralleled without individual d.c. isolation.

:E

(refer to Block Diagram)

The LMC567 can be directly substituted in most LM567 applications with the following provisions:
1. Oscillator timing capacitor Ct must be halved to double
the oscillator frequency relative to the input frequency
(See OSCILLATOR TIMING COMPONENTS).
2. Filter capacitors Cl and C2 must be reduced by a factor
of 8 to maintain the same filter time constants.
3. The output current demanded of pin 8 must be limited to
the specified capability of the LMC567.
OSCILLATOR TIMING COMPONENTS

The voltage-controlled oscillator (VCO) on the LMC567
must be set up to run at twice the frequency of the input
signal tone to be decoded. The center frequency of the
VCO is set by timing resistor Rt and timing capacitor Ct
connected to pins 5 and 6 of the IC. The center frequency
as a function of Rt and Ct is given by:

LOOP FILTER
Pin 2 is the combined output of the phase detector and
control input of the VCO for the phase-locked loop (PLL).
Capacitor C2 in conjunction with the nominal 80 kD. pin 2
internal resistance forms the loop filter.
For small values of C2, the PLL will have a fast acquisition
time and the pull-in range will be set by the built in VCO
frequency stops, which also determine the largest detection
bandwidth (LDBW). Increasing C2 results in improved noise
immunity at the expense of acquisition time, and the pull-in
range will begin to become narrower than the LDBW (see
Bandwidth as a Function of C2 curve). However, the maximum hold-in range will always equal the LDBW.
OUTPUT FILTER

F
= ___1___ Hz
osc - 1.4 RtCt
Since this will cause an input tone of half Fosc to be decoded,
1
Finpul '" 2.8 Rt Ct Hz

This equation is accurate at low frequencies; however,
above 50 kHz (Fosc = 100 kHz), internal delays cause the
actual frequency to be lower than predicted.
The choice of Rt and Ct will be a tradeoff between supply
current and practical capacitor values. An additional supply
current component is introduced due to Rt being switched
to Vs every half cycle to charge CI:
Isdueto Rt = Vs/(4Rt)
Thus the supply current can be minimized by keeping Rt as
large as possible (see supply current vs. operating frequency curves). However, the desired frequency will dictate an
RtCt product such that increasing Rt will require a smaller
Ct. Below Ct = 100 pF, circuit board stray capacitances
begin to playa role in determining the oscillation frequency
which ultimately limits the minimum Ct.
To allow for I.C. and component value tolerances, the oscillator timing components will require a trim. This is generally
accomplished by using a variable resistor as part of Rt, although Ct could also be padded. The amount of initial frequency variation due to the LMC567 itself is given in the
electrical specifications; the total trim range must also accommodate the tolerances of Rt and Ct.

Pin 1 is the output of a negative-going amplitude detector
which has a nominal 0 signal output of 7/9 Vs. When the
PLL is locked to the input, an increase in signal level causes
the detector output to move negative. When pin 1 reaches
2/3 Vs the output is activated (see OUTPUT PIN).
Capacitor Cl in conjunction with the nominal 40 kD. pin 1
internal resistance forms the output filter. The size of Cl is a
tradeoff between slew rate and carrier ripple at the output
comparator. Low values of Cl produce the least delay between the input and output for tone burst applications, while
larger values of Cl improve noise immunity.
Pin 1 also provides a means for shifting the input threshold
higher or lower by connecting an external resistor to supply
or ground. However, reducing the threshold using this technique increases sensitivity to pin 1 carrier ripple and also
results in more part to part threshold variation.
OUTPUT PIN
The output at pin 8 is an N-channel FET switch to ground
which is activated when the PLL is locked and the input tone
is of sufficient amplitude to cause pin 1 to fall below 2/3 Vs.
Apart from the obvious current component due to the external pin 8 load resistor, no additional supply current is required to activate the switch. The on resistance of the
switch is inversely proportional to supply; thus the 'sat' voltage for a given output current will increase at lower supplies.

SUPPLY DECOUPLING

The decoupling of supply pin 4 becomes more critical at
high supply voltages with high operating frequencies, requiring C4 to be placed as close as possible to pin 4.

5-286

r-------------------------------------------------------------------------,

~ Semiconductor
NatiOnal

ADVANCED INFORMATION

o
en
en

0)

Corporation

lMC568 low Power Phase-locked loop
General Description

Features

The LMC568 is an amplitude-linear phase-locked loop consisting of a linear VCO, fully balanced phase detectors, and
a carrier detect output. LMCMOSTM technology is employed
for high performance with low power consumption.

• Demodulates ± 15% deviation FM/FSK signals
• Carrier Detect Output with hysteresis
• Operation to 500 kHz input frequency
II Low THD-O.5% typo for ± 10% deviation
• 2V to 9V supply voltage range
• Low supply current drain

The VCO has a linearized control range of ± 30% to allow
demodulation of FM and FSK signals. Carrier detect is indicated when the PLL is locked to an input signal greater than
26 mVrms. LMC568 applications include FM SCA and TV
second audio program decoders, FSK data demodulators,
and voice pagers.

Typical Application

r

:s::

(100 kHz input frequency, refer to notes pg. 3)

RH

,,r------------~-----------~,,
:
Cl
0.05).1F

0--.::-8.....' -'\;"Iv-+14+-Vs

.x.

Ct
C3

~--~6--.....--~3~00~

DE - EMPHASIS INPUT>--1I---=:'-"+-~1

0.01 ).IF

9Kl
4
Vs C4

.I.

LMC568

1

Rt

< 10 kD.

L-~---t....

O.I).1F

SET Fose TO 2xlNPUT FREQ.---1
MEASURE WITH ~10 pF PROBE
TL/H/9135-1

Order Number LMC56SCM or LMC56SCN
See NS Package Number MOSA or NOSE

5-287

Absolute Maximum Ratings
If MIlitary/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
2Vp_p
Input Voltage, Pin 3
Supply Voltage, Pin 4
10V
Output Voltage, Pin 8
13V
Voltage at All Other Pins

Operating Temperature Range (TA)
Storage Temperature Range
Soldering Information
Dual-In-Line Package
Soldering (10 seconds)
Small Outline Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

Vs to Gnd
30 rnA

Output Current, Pin 8
Package Dissipation

-25'Cto +125'C
- 55'C to + 150'C

260'C
215'C
220'C

See AN-450 "Surface Mounting Methods and their Effect on
Product Reliability" for other methods of soldering surface
mount devices.

500mW

Electrical Characteristics
Test Circuit, TA = 25'C, Vs = 5V, RtC! # 2, Sw. 1 Pos. 0; and no input unless otherwise noted.
Symbol
14

Parameter
Power Supply Current

Min

Conditions
RtCt # 1, Quiescent
or Activated

Typ

Max

Units

mAdc

Vs = 2V

0.35

Vs = 5V

0.75

1.5

Vs = 9V

1.2

2.4

V3

Input D.C. Bias

0

mVdc

R3

Input Resistance

40

k!1

18

Output Leakage

fo

Center Frequency
Fosc +2

1
RtC! #2, Measure Oscillator
Frequency and Divide by 2

Vs = 5V

90

Center Frequency
Shift with Supply

fol9V - fol2V X 100
7 folsv

Yin

Input Threshold

Set Input Frequency Equal to fo
Measured Above, Increase Input
Level until Pin 8 Goes Low.

103

1.0

2.0

%/V

10

16

25

16

26

42

V8

Output 'Sat' Voltage

Input Level> Threshold
Choose RL for Specified 18

18 = 2mA

0.06

18 = 20 rnA

0.7

Measure Fosc with Sw. 1 in
Pos. 0, 1, and 2;

Vs = 2V
Vs = 5V
Vs = 9V

ABW

Bandwidth Skew

Skew = (Fosclp2 + Fosclpl - 1) x 100
2 Fosclpo

Vout

Recovered Audio

Typical Application Circuit
Input = 100 mVrms, F = 100 kHz
Fmod = 400 Hz, ± 10kHz Dev.

Vs

1.5

mVrms
0.15

Vdc

30
40

55

%

60
1

2V

170

Vs = 5V

270

Vs = 9V

400

=

mVrms

45

Vs = 9V
Starting at Input Threshold, Decrease Input Level
until Pin 8 Goes High.

L.D.B.W. = Fosclp2 - Fosclpl X 100
Fosclpo

kHz

Vs = 2V

Input Hysteresis

Largest Detection
Bandwidth

115

Vs= 5V

AVin

L.D.B.W.

nAdc

105

Vs = 9V
Mo

100

98

Vs = 2V

±5

%

mVrms

THD

Total Harmonic
Distortion

Typical Application Circuit
as Above, Measure Vout Distortion.

0.5

%

S+N
N

Signal to Noise Ratio

Typical Application Circuit
Remove Modulation, Measure Vn
(S + N}/N = 20 log (VoutlVn).

65

dB

f max

Highest Center Freq.

RtCt #3, Measure Oscillator Frequency
and Divide by 2

700

kHz

5-288

r3l:

Test Circuit

o
en

0)

co

Vs

SW.l
0

0.01 J.lr

1,

rif-

13

,",m%p'(

ri~
-= 0.001 J.lr
V3

Vs

--+

O.lJ.lr±

--

VB

2

7~

3

6

14

50n

--

8

5

4
MEASURE rose
WITH !:.10pr PROBE

- IQ

0

I

RtCt

Rt

Ct

#1
#2
#3

lOOk
10k
5.1k

300pF
300pF
62pF

Rt-=

~
TL/H/9135-3

Notes to Typical Application
SUPPLY DECOUPLING

OUTPUT TAKEOFF

The decoupling of supply pin 4 becomes more critical at
high supply voltages with high operating frequencies, requiring C4 to be placed as close to possible to pin 4. Also, due
to pin voltages tracking supply, a large C4 is necessary for
low frequency PSRR.

The output signal is taken off the loop filter at pin 2. Pin 2 is
the combined output of the phase detector and control input
of the VCO for the phase-locked loop (PLL). The nominal
pin 2 source resistance is 80 kn, requiring the use of an
external buffer transistor to drive nominal loads.

OSCILLATOR TIMING COMPONENTS

For small values of C2, the PLL will have a fast acquisition
time and the pull-in range will be set by the built-in VCO
frequency stops, which also determine the largest detection
bandwidth (LDBW). IncreaSing C2 results in improved noise
immunity at the expense of acquisition time, and the pull-in
range will become narrower than the LDBW. However, the
maximum hold-in range will always equal the LDBW. The 2
kHz de-emphasis pole shown may be modified or omitted as
required by the application.

The voltage-controlled oscillator (VCO) on the LMC568
must be set up to run at twice the frequency of the input
signal. The components shown in the typical application are
for Foso = 200 kHz (100 kHz input frequency). For operation at lower frequencies, increase the capacitor value; for
higher frequencies proportionally reduce the resistor values.
If low distortion is not a requirement, the series diode/resistor between pins 6 and 5 may be omitted. This will reduce
VCO supply dependence and increase You! by approximately 2 dB with THD = 2% typical. The center frequency as a
function of Rt and Ct is given by:

CARRIER DETECT

Pin 1 is the output of a negative-going amplitude detector
which has a nominal 0 signal output of 7/9 Vs. The output at
pin 8 is an N-channel FET switch to ground which is activated when the PLL is locked and the input is of sufficient
amplitude to cause pin 1 to fall below 2/3 Vs' The carrier
detect threshold is internally set to 26 mVrms typical on a
5V supply.
Capacitor Cl in conjunction with the nominal 40 kn pin 1
internal resistance forms the output filter. The size of Cl is a
tradeoff between slew rate and carrier ripple at the output
comparator. Optional resistor RH increases the hysteresis in
the pin 8 output for applications such as audio mute control.
The minimum allowable value for RH is 330 kn.

1
Foso "" 1.4 Rt Ct Hz

To allow for I.C. and component value tolerences, the oscillator timing components will require a trim. This is generally
accomplished by using a variable resistor as part of Rt, although Ct could also be padded. The amount of initial frequency variation due to the LMC568 itself is given in the
electrical specifications; the total trim range must also accommodate the tolerances of Rt and ct.
INPUT PIN
The input pin 3 is internally ground-referenced with a nominal 40 kn resistor. Signals that are centered on OV may be
directly coupled to pin 3; however, any d.c. potential must
be isolated via C3.

5-289

co
CD
Lt)

o

r-------------------------------------------------------------------------------~

LMC568 Typical Performance Characteristics

:!!
-I

Frequency Drift
with Temperature

Peak Deviation vs
Input Signal Level
t40

I

~

r'\.

~

z
0

~

"-

i!i
'"~

"

-2
-3
-50

~

t30

~

'\

50

100

TEMPERATURE(OC)

150

t40

APPLICAnON CIRCUIT. Vs =5V

TEST CIRCUIT Vs =5V. RI~ 2
1

Pull-In Range as
a Function of C2

I

t20

~

I

~

I!I

~

~

I

o

o

1\
\

t20

z

I

tl0

--+• r- ~~u5c:,~:; 1~~~rm.

t30

ii!
50

100

150

200

250

INPUT VOLTAGE (m Vrms)

300

tl0

\

.'-

o

1

10

102

r-103

104

loS

FoxC2 PRODUCT(Hz-l'rJ
TUH/9135-2

5-290

Section 6
Surface Mount

Section 6 Contents
Surface Mount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-2

6-3

r--------------------------------------------------------------------------,0
c

~

NatiOnal

~ Semiconductor

CD

Corporation

s::
o

-

C
::l

Surface Mount
Cost pressures today are forcing many electronics manufacturers to automate their production lines. Surface mount
technology plays a key role in this cost-savings trend because:

SURFACE MOUNT PACKAGING AT NATIONAL
To help our customers take advantage of this new technology, National has developed a line of surface mount packages. Ranging in lead counts from 3 to 360, the package
offerings are summarized in Table I.

1. The mounting of devices on the PC board surface eliminates the expense of drilling holes;

Lead center spacing keeps shrinking with each new generation of surface mount package. Traditional packages (e.g.,
DIPs) have a 100 mil lead center spacing. Surface mount
packages currently in production (e.g., SOT, SOIC, PCC,
LCC, LDCC) have a 50 mil lead center spacing. Surface
mount packages in production release (e.g., POFP) have a
25 mil lead center spacing. Surface mount packages in development (e.g., TAPEPAKTM) will have a lead center spacing of only 12-20 mils.

2. The use of pick-and-place machines to assemble the PC
boards greatly reduces labor costs;
3. The lighter and more compact assembled products resulting from the smaller dimensions of surface mount
packages mean lower material costs.
Production processes now permit both surface mount and
insertion mount components to be assembled on the same
PC board.

TABLE I. Surface Mount Packages from National
Package
Type

Package
Material
Lead Bend

Small Outline
Transistor
(SOT)

Small Outline
IC(SOIC)

,{t ~

Plastic Chip
Carrier (PCG)

Plastic Ouad
Flat Pack
(POFP)

f§J
~

V

TAPEPAKTM
(TP)

Leadless Chip Leaded Chip
Carrier (LCC) Carrier
(LDCC)

o

0

I

,

,Do 0

,III!!!!!!!!!!!!!"!! I

!lHHHHHHHf I

&;wd/4!)j

Ceramic

Ceramic

Plastic

Plastic

Plastic

Plastic

Plastic

-

Gull Wing

Gull Wing

J-Bend

Gull Wing

Gull Wing

Lead Center
Spacing

50 Mils

50 Mils

50 Mils

25 Mils

20,15,12 Mils

50 Mils

50 Mils

Tape & Reel
Option

Yes

Yes

Yes

tbd

tbd

No

No

Lead Counts SOT-23
High Profile
SOT-23
Low Profile

SO-8(*)
SO-14(0)

PCC-20(*)
PCC-2S(*)

SO-14 Wide(-)
SO-16(*)
SO-16 Wide(O)
SO-20(*)
SO-24(0)

PCC-44(-)
PCC-68
peC-84
PCC-124

POFP-84
POFP-100
POFP-132
POFP-196(-)
POFP-244

·In production (or planned) for linear products.

6-3

TP-40 (*)
TP-68
TP-84
TP-132
TP-172
TP-220
TP-284
TP-360

Gull Wing

LCC-18
LCC-20(*)

LDCC-44

LCC-28

LDCC-68

LCC-32
LCC-44(*)
LCC-4B
LCC-52
LCC-68
LCC-84
LCC-124

LDCC-84
LDCC-124

[II

..C r-----------------------------------------------------------------------------------------------,
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fn

LINEAR PRODUCTS IN SURFACE MOUNT
Linear functions available in surface mount include:

TABLE II: Surface Mount Package
Thermal Resistance Range'

• Op amps
• Comparators

Package

• Regulators
• References
• Data conversion
• Industrial
• Consumer
• Automotive
A complete list of linear part numbers in surface mount is
presented in Table III. Refer to the datasheet in the appropriate chapter of this databook for a complete description of
the device. In addition, National is continually expanding the
list of devices offered in surface mount. If the functions you
need do not appear in Table III, contact the sales office or
distributor branch nearest you for additional information.
Automated manufacturers can improve their cost savings by
using Tape-and-Reel for surface mount devices. Simplified
handling results because hundreds-to-thousands of semiconductors are carried on a single Tape-and-Reel pack (see
ordering and shipping information-printed later in this section-for a comparison of devices/reel vs. devices/rail for
those surface mount package types being used for linear
products). With this higher device count per reel (when compared with less than a 100 devices per rail), pick-and-place
machines have to be re-Ioaded less frequently and lower
labor costs result.

Thermal Resistance"
(OIA. 'C/W)

SO-8
SO-14
SO-14 Wide
SO-16
SO-16 Wide
SO-20
SO-24

120-175
100-140
70-110
90-130
70-100
60-90
55-85

PCC-20
PCC-28
PCC-44

70-100
60-90
40-60

• Actual thermal resistance for a particular device depends on die size.
Refer to the datasheet for the actual 8jA value.
"Test conditions: PCS mount (FR4 material), still air (room temperature),
copper traces (150 x 20 x 10 mils).

Given a max junction temperature of 150'C and a maximum
allowed ambient temperature, the surface mount device will
be able to dissipate less power than the DIP device. This
factor must be taken into account for new designs.
For board conversion, the DIP and surface mount devices
would have to dissipate the same power. This means the
surface mount circuit would have a lower maximum allowable ambient temperature than the DIP circuit. For DIP circuits where the maximum ambient temperature required is
substantially lower than the maximum ambient temperature
allowed, there may be enough margin for safe operation of
the surface mount circuit with its lower maximum allowable
ambient temperature. But where the maximum ambient temperature required of the DIP current is close to the maximum allowable ambient temperature, the lower maximum
ambient temperature allowed for the surface mount circuit
may fall below the maximum ambient temperature required.
The circuit designer must be aware of this potential pitfall so
that an appropriate work-around can be found to keep the
suJface mount package from being thermally overstressed
in the application.

With Tape-and-Reel, manufacturers save twice-once from
using surface mount technology for automated PC board
assembly and again from less device handling during shipment and machine set-up.
BOARD CONVERSION
Besides new designs, many manufacturers are converting
existing printed circuit board designs to surface mount. The
resulting PCB will be smaller, lighter and less expensive to
manufacture; but there is one caveat-be careful about the
thermal dissipation capability of the surface mount package.
Because the surface mount package is smaller than the traditional dual-in-line package, the surface mount package is
not capable of conducting as much heat away as the DIP
(i.e., the surface mount package has a higher thermal resistance-see Table II).
The silicon for most National devices can operate up to a
150'C junction temperature (check the datasheet for the
rare exception). Like the DIP, the surface mount package
can actually withstand an ambient temperature of up to
125'C (although a commercial temperature range device
will only be specified for a max ambient temperature of 70'C
and an industrial temperature range device will only be
specified for a max ambient temperature of 85'C). See
AN-336, "Understanding Integrated Circuit Package Power
Capabilities", (reprinted in the appendix of each linear databook volume) for more information.

SURFACE MOUNT LITERATURE
National has published extensive literature on the subject of
surface mount packaging. Engineers from packaging, quality, reliability, and surface mount applications have pooled
their experience to provide you with practical hands-on
knowledge about the construction and use of surface mount
packages.
The applications note AN-450 "Surface Mounting Methods
and their Effect on Product Reliability" is referenced on
each SMD datasheet. In addition, "Wave Soldering of Surface Mount Components" is reprinted in this section for your
information.

6-4

,--------------------------------------------------------------------------, 0

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TABLE III. Linear Surface Mount Current Device Listing

Amplifiers and Comparators
Part Number

LF347WM
LF351M
LF451CM
LF353M
LF355M
LF356M
LF357M
LF444CWM
LM10CWM
LM10CLWM
LM308M
LM308AM
LM310M
LM311M
LM318M
LM319M
LM324M
LM339M
LM346M
LM348M
LM358M
LM359M

Data Acquisition Circuits

Part Number

Part Number

ADC0802LCV
ADC0802LCWM
ADC0804LCV
ADC0804LCWM
ADC0808CCV
ADC0809CCV

LM392M
LM393M
LM741CM
LM1458M
LM2901M
LM2902M
LM2903M
LM2904M
LM2924M
LM3403M

ADC0811BCV
ADC0811CCV
ADC0819BCV
ADC0819CCV
ADC0820BCV
ADC0820CCV

LM4250M
LM324M
LM339M
LM365WM
LM607CM
LMC669BCWM
LMC669CCWM
LF441CM

DAC0808LCM
DAC0830LCWM
DAC0830LCV
DAC0832LCWM
DAC0832LCV

Industrial Functions

Part Number

Part Number

LM317LM
LF3334M

LM2931 M-5.0
LM3524M
LM78L05ACM
LM78L12ACM
LM78L15ACM

LM385M
LM385M-l.2

ADC1025BCV
ADC1025CCV
DAC0800LCM
DAC0801LCM
DAC0802LCM
DAC0806LCM
DAC0807LCM

ADC0838BCV
ADC0838CCV
ADC0841BCV
ADC0841CCV
ADC0848BCV
ADC0848CCV
ADC1005BCV
ADC1005CCV

Regulators and References

LM336M-2.5
LF336BM-2.5
LM336M-5.0
LM336BM-5.0
LM337LM

Part Number

LM79L05ACM
LM79L12ACM
LM79115ACM
LP2951ACM
LP2951CM

Part Number

Part Number

AH5012CM
LF13331M
LF13509M
LF13333M
LM555CM

LM13600M
LM13700M
LMC555CM
LM567CM
MF4CWM-50

LM556CM
LM567CM
LM1496M
LM2917M

MF4CWM-l00
MF6CWM-50
MF10CCWM
MF6CWM-l00
MF5CWM

LM3046M
LM3086M
LM3146M

LM385BM-l.2
LM385M-2.5
LM385BM-2.5
LM723CM
LM2931CM

Commercial and Automotive

6-5

Part Number

Part Number

LM386M-l
LM592M
LM831M
LM832M
LM833M

LM1837M
LM1851M
LM1863M
LM1865M
LM1870M

LM837M
LM838M
LMl131CM

LM1894M
LM1964V
LM2893M
LM3361AM
LM1881M

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Hybrids
Part Number

Part Number

LHOO02E
LH4002E

LH0032E
LH0033E

A FINAL WORD
National is a world leader in the deSign and manufacture of
surface mount components.
Because of deSign innovations such as perforated copper
leadframes, our small outline package is as reliable as our
DIP-the laws of physics would have meant that a straight
"junior copy" of the DIP would have resulted in an "S.O."
package of lower reliability. You benefit from this equivalence of reliability. In addition, our ongoing vigilance at each
step of the production process assures that the reliability we
deSigned in stays in so that only devices of the highest quality and reliability are shipped to your factory.

Package

Package
Designator

Max/Rail

Per Reel-

SO-8
SO-14
SO-14 Wide
SO-16
50-16 Wide
SO-20
SO-24

M
M
WM
M
WM
M
M

100
50
50
50
50
40
30

2500
2500
1000
2500
1000
1000
1000

V
V
V

50
40
25

1000
1000
500

PQFP-196

VF

TBD

-

TP-40

TP

100

TBD

E
E

50
25

PCL-20
PCL-28
PCL-44

LCC-20
LCC-44

Our surface mount applications lab at our headquarters site
in Santa Clara, California continues to research (and publish) methods to make it even easier for you to use surface
mount technology. Your problems are our problems.
When you think "Surface Mount"-think "National"!

-

-

*Incremental ordering quantities. (National Semiconductor reserves the right
to provide a smaller quantity of devices per Tape-and-Reel pack to preserve

lot or date code integrity. See example below.)

Example: You order 5,000 LM324M ICs shipped in Tapeand-Reel.
• Case 1: All 5,000 devices have the same date code

Ordering and Shipping Information

• You receive 2 SO-14 (Narrow) Tape-and-Reel
packs, each having 2500 LM324M ICs
• Case 2: 3,000 devices have date code A and 2,000 devices have date code B

When you order a surface mount semiconductor, it will be in
one of the several available surface mount package types.
Specifying the Tape-and-Reel method of shipment means
that you will receive your devices in the following quantities
per Tape-and-Reel pack: SMD devices can also be supplied
in conventional conductive rails.

• You receive 3 50-14 (Narrow) Tape-and-Reel
packs as follows:
Pack #1 has 2,500 LM324M ICs with date code A
Pack #2 has 500 LM324M ICs with date code A
Pack #3 has 2,000 LM324M ICs with date code B

Short-Form Procurement Specification
-+

TAPE FORMAT

Trailer (Hub End)-

Carrier"

IDirection of Feed I
Leader (Start End)-

Empty Cavities,
min (Unsealed
Cover Tape)

Empty Cavities,
min (Sealed
Cover Tape)

Filled Cavities
(Sealed
Cover Tape)

Empty Cavities,
min (Sealed
Cover Tape)

Empty Cavities,
min (Unsealed
Cover Tape)

SO-8 (Narrow)

2

2

2500

5

5

SO-14 (Narrow)

2

2

2500

5

5

SO-14 (Wide)

2

2

1000

5

5

SO-16 (Narrow)

2

2

2500

5

5

SO-16 (Wide)

2

2

1000

5

5

SO-20 (Wide)

2

2

1000

5

5

50-24 (Wide)

2

2

1000

5

5

5

Small Outline IC

Plastic Chip Carrier IC
PCC-20

2

2

1000

5

PCC-28

2

2

750

5

5

PCC-44

2

2

500

5

5

'The following diagram Identifies these sections of the tape and Pin # 1 device orientation.

6-6

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Short-Form Procurement Specification

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DEVICE ORIENTATION

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DIRECTION
OF FEED

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TRAILER --~.*t"I---------_CARRIER SECTlDN--------~..
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COVER TAPE

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PCC-IC
DEVICES
TLlXX/0026-8

o Reel:

MATERIALS

• Cavity Tape: Conductive PVC (less than 105 Ohms/Sq)

(1) Solid 80 pt fibreboard (standard)

• Cover Tape: Polyester
(1) Conductive cover available

(2) Conductive fibreboard available
(3) Conductive plastic (PVC) available

TAPE DIMENSIONS (24 Millimeter Tape or Less)
_

Po 10 PITCH CUMULATIVE
TAPE TOLERANCE ±0.2mm

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PIN
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TLlXX/0026-9

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Small Outline IC

80-B
(Narrow)

80-14
(Narrow)

80-14
(Wide)

80-16
(Narrow)

80-16
(Wide)

80-20
(Wide)

80-24
(Wide)

12±.30 B.0±.10

5.5±.05 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 6.4±.10

5.2±.10

2.1 ±.10 1.55±.05 30

16±.30 B.0±.10

7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 6.5±.10

9.0±.10

2.1 ±.10 1.55±.05 40

16±.30 12.0±.10 7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 10.9±.10

9.5±.10

3.0±.10 1.55±.05 40

16±.30 B.0±.10

10.3±.10 2.1 ±.10 1.55±.05 40

7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 6.5±.10

16±.30 12.0±.10 7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 10.9±.10 10.76±.10 3.0±.10 1.55±.05 40
24±.30 12.0±.10 11.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 10.9±.10 13.3±.10 3.0±.10 2.05±.05 50
24±.30 12.0±.10 11.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 10.9±.10 15.B5±.10 3.0±.10 2.05±.05 50

Plastic Chip Carrier IC

PCC-20

16±.30 12.0±.10 7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 9.3±.10

PCC-2B

24±.30 16.0±.10 11.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 13.0±.10 13.0±.10 4.9±.10 2.05±.05 50

9.3±.10

4.9±.10 1.55±.05 40

Nole 1: Ao. Bo and Ko dimensions are measured 0.3 mm above the inside wall of the cavity bottom.
Note 2: Tape with components shall pass around a mandril radius R without damage.
Note 3: Cavity tape material shall be PVC conductive (less than 105 Ohms/Sq).
Note 4: Cover tape material shall be polyester (30-65 grams peel· back force).

Note 5: 01 Dimension is centered within cavity.
Note 6: All dimensions are in millimeters.

REEL DIMENSIONS
TMAX

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DATE CODE
NON-MILITARY
2ND DIGIT - CALENDAR YEAR
3RD & 4TH DIGITS - CALENDAR WORK WEEK
MILITARY- 8838 &M38510
1ST & 2ND DIGITS - CALENDAR YEAR
3RD & 4TH DIGITS - CALENDAR WORK WEEK
(EXAMPLE: 8301 1ST WEEK OF 1983)

=

MILITARY ONLY
ESD
(ELECTROSTATIC DISCHARGE)
SENSITIVITY INDICATOR

MILITARY ONLY
INDICATE PLANT
OR MANUFACTURE

PART NUMBER

TL/XX/0027-2

7-3

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Appendix B

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APPLICATION NOTE REFERENCED BY PART NUMBER

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National Semiconductor Linear Application notes are normally written to explain
the operation and use of a particular device or family of IC's, or to present alterna·
tive technical solutions. The following PART NUMBER index references the published application notes that would offer application assistance for those specific
IC's.
The 1986 Linear Applications Handbook is a complete text for all current Application Notes for both Monolithic and Hybrid products. Specific Application Notes are
available upon request through National Semiconductor Sales Offices.

DEVICE NUMBER

APPLICATION NOTE

ADCXXXX .............................................................................AN-156
ADC80 ............................................................................... AN-360
ADC0801 ................................ AN-233, AN-271, AN-274, AN-280, AN-281, AN-294, LB-53
ADC0802 ............................................... AN-233, AN-274, AN-280, AN-281, LB-53
ADC0803 ............................................... AN-233, AN-274, AN-280, AN-281, LB-53
ADC0804 ........................................ AN-233, AN-274, AN-276, AN-280, AN-281, LB-53
ADC0805 ............................................... AN-233, AN-274, AN-280, AN-281, LB-53
ADC0808 .............................................................. AN-247, AN-280, AN-281
ADC0809 .....................................................................AN-247, AN-280
ADC0816 ...................................................... AN-193, AN-247, AN-258, AN-280
ADC0817 .............................................................. AN-247, AN-258, AN-280
ADC0820 .............................................................................AN-237
ADC0831 ..................................................................... AN-280, AN-281
ADC0832 ..................................................................... AN-280, AN-281
ADC0833 .....................................................................AN-280, AN-281
ADC0834 .....................................................................AN-280, AN-281
ADC0838 .....................................................................AN-280, AN-281
ADC1001 .............................................................. AN-276, AN-280, AN-281
ADC1005 ............................................................................. AN-280
ADC1210 .............................................................................AN-245
ADC3501 ..................................................................... AN-200, AN-202
ADC3511 ............................................................................. AN-200
ADC3701 .............................................................................AN-200
ADC3711 .............................................................................AN-200
AH0014 ................................................................................AN-38
AH0019 ................................................................................AN-38
CD4016 ................................................................................AB-10
DACXXXX .............................................................................AN-156
DAC0830 ............................................................................. AN-284
DAC0831 .....................................................................AN-271 , AN-284
DAC0832 ..................................................................... AN-271 , AN-284
DAC1000 ...................................................... AN-271, AN-275, AN-277, AN-284
DAC1001 ...................................................... AN-271, AN-275, AN-277, AN-284
DAC1002 ...................................................... AN-271, AN-275, AN-277, AN-284
DAC1006 ...................................................... AN-271, AN-275, AN-277, AN-284
DAC1007 ...................................................... AN-271, AN-275, AN-277, AN-284

7-4

»

DEVICE NUMBER
APPLICATION NOTE
DAC1008 ...................................................... AN-271, AN-275, AN-277, AN-284
DAC1020 .............................................. AN-263, AN-269, AN-293, AN-294, AN-299
DAC1021 ............................................................................. AN-269
DAC1022 ............................................................................. AN-269
DAC1208 ..................................................................... AN-271 , AN-284
DAC1209 ..................................................................... AN-271, AN-284
DAC1210 ..................................................................... AN-271, AN-284
DAC1218 ............................................................................. AN-293
DAC1220 ..................................................................... AN-253, AN-269
DAC1221 ............................................................................. AN-269
DAC1222 ............................................................................. AN-269
DAC1230 ............................................................................. AN-284
DAC1231 ..................................................................... AN-271, AN-284
DAC1232 ..................................................................... AN-271, AN-284
DAC1280 ..................................................................... AN-261, AN-263
DH0034 ............................................................................... AN-253
DH0035 ................................................................................ AN-49
DS8606 ....................................................................... AN-381 , AN-382
DS8608 ............................................................................... AN-382
DT1058 ............................................................................... AN-287
DT1060 ............................................................................... AN-287
DTSW250E2 .......................................................................... AN-287
DTSW250GI ........................................................................... AN-287
INS8070 .............................................................................. AN-260
LF111 .................................................................................. LB-39
LF155 ........................................................................ AN-263, AN-447
LF198 ........................................................................ AN-245, AN-294
LF311 ................................................................................ AN-301
LF347 ......................... AN-256, AN-262, AN-263, AN-265, AN-266, AN-301, AN-344, AN-447
LF351 ...................... AN-242, AN-263, AN-266, AN-271, AN-275, AN-293, AN-447, Appendix C
LF351A ............................................................................... AN-240
LF351 B ........................................................................... Appendix D
LF353 ........ AN-256, AN-258, AN-263, AN-264, AN-271, AN-285, AN-293, AN-447, LB-44, Appendix D
LF356 ................................. AN-253, AN-258, AN-260, AN-263, AN-266, AN-271, AN-272,
AN-275, AN-293, AN-294, AN-295, AN-301, AN-447
LF357 .................................................................. AN-263, AN-447, LB-42
LF398 ........................................... AN-247, AN-258, AN-266, AN-294, AN-298, LB-45
LF400 ........................................................................ AN-428, AN-447
LF411 ......................................................... AN-294, AN-301, AN-344, AN-447
LF412 ................................................. AN-272, AN-299, AN-301, AN-344, AN-447
LF441 ........................................................................ AN-301,AN-447
LF13006 .............................................................................. AN-344
LF13007 .............................................................................. AN-344
LF13331 ...................................................................... AN-294,AN-447
LF13508 .............................................................. AN-289, AN-360, AN-447
LF13509 .............................................................. AN-289, AN-295, AN-447
LH0002 .................................. AN-13, AN-63, AN-227, AN-244, AN-263, AN-272, AN-301
LH0022 ......................................................................... AN-63, AN-75
LH0023 ....................................................................... AN-245, AN-360
LH0024 ............................................................................... AN-253
LH0032 ............................................................... AN-242, AN-244, AN-253
LH0033 ........................................................ AN-48, AN-115, AN-227, AN-253
LH0042 ................................................................................ AN-63
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LH0043 ............................................................................... AN-245
LH0052 ................................................................................ AN-63
LH0053 ............................................................................... AN-245
LH0062 ................................................................................ AN-75
LH0063 ............................................................................... AN-227
LH0070 ............................................................................... AN-301
LH0071 ............................................................................... AN-245
LH0082 ....................................................................... AN-244, AN-266
LH0086 ....................................................................... AN-245, AN-360
LH0091 ............................................................................... AN-180
LH0094 ............................................................................... AN-301
LH0101 ...............................................................................AN-261
LH1605 ...............................................................................AN-343
LM10 .................................. AN-211, AN-247, AN-258, AN-271, AN-288, AN-299, AN-300
LM11 .................................................. AN-241, AN-242, AN-260, AN-266, AN-271
LM12 ................................................................................. AN-446
LM101 ...................................... AN-4, AN-13, AN-20, AN-24, AN-75, LB-42, Appendix A
LM101A .............................. AN-29, AN-30, AN-31, AN-79, AN-241, LB-1, LB-2, LB-4, LB-8,
LB-14, LB-16, LB-19, LB-28
LM102 .............................................. AN-4, AN-13, AN-30, LB-1, LB-5, LB-6, LB-11
LM103 .........................................................................AN-110,LB-41
LM104 .......................................................... AN-21, LB-3, LB-7, LB-10, LB-40
LM105 ................................................. AN-21, AN-23, AN-110, LB-3, LB-7, LB-10
LM106 .....................................................................AN-41, LB-6, LB-12
LM107 ............................................. AN-20, AN-31, LB-1, LB-12, LB-19, Appendix A
LM108 ................... AN-29, AN-30, AN-31, AN-63, AN-79, AN-211, AN-241, LB-14, LB-15, LB-21
LM108A .................................................................. AN-260, LB-15, LB-19
LM109 ..........................................................................AN-42, LB-15
LM109A ................................................................................ LB-15
LM 110 ........................................................................... LB-11, LB-42
LM111 ................................................ AN-41,AN-103, LB-12, LB-16, LB-32, LB-39
LM112 .......................................................................... AN-63,LB-19
LM113 ................................................ AN-56, AN-11 0, LB-21 , LB-24, LB-28, LB-37
LM117 ................................................... AN-178,AN-181,AN-182, LB-46, LB-47
LM117HV ........................................................................ LB-46, LB-47
LM118 ................................................... LB-17, LB-19, LB-21, LB-23, Appendix A
LM119 .........................................................................AN-115, LB-23
LM120 ................................................................................AN-182
LM121 ................................................... AN-79, AN-104, AN-184, AN-260, LB-22
LM121 A ................................................................................ LB-32
LM122 ..........................................................................AN-97, LB-38
LM125 ................................................................................. AN-82
LM126 ................................................................................. AN-82
LM129 ......................................................... AN-173,AN-178, AN-262, AN-266
LM131 ....................................................................AN-210, Appendix 0
LM131A ..............................................................................AN-210
LM134 ................................................................................. LB-41
LM135 ........................................................ AN-225, AN-262, AN-292, AN-298
LM137 ................................................................................. LB-46
LM137HV .............................................................................. LB-46
LM138 ................................................................................. LB-46
LM139 ................................................................................. AN-74
LM143 ........................................................................AN-127,AN-271
LM148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ............................................... AN-260

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General

Typical A + Flow is:

National Semiconductor Commercial Reliability Programs
provide a broad range of off-the-shelf enhanced semiconductor products that supply an extra measure of quality and
reliability needed in high-stress or difficult to service applications.

• SEM
• Assembly and Seal
• Four Hour 150'C Bake
• Five Temperature Cycles (O'C to + 100'C)
• High Temperature Electrical Test

National's A + and B + programs allow each individual customerto:

• Electrical Test
• Burn-In (160 hours at a minimum junction temperature of
125'C)

• Minimize the need for incoming electrical inspection
• Eliminate the need and associated costs of using independent testing laboratories

• DC Parametric and Function Tests
• Tightened Quality Control Inspection Plans

• Reduction in infant mortality rate

Note: Certain products may follow slightly different process flows dictated
by specific capabilities and device characteristics, consult NSC.

• Reduction in reworked board costs
• Reduction in warranty and service costs

P + Product Enhancement

A + Product Enhancement

The P+ product enhancement program applies to regulator
devices and offers an added advantage. P + involves a dynamic self-heating burn-in that tests the thermal shutdown
of the regulator. P + is proven more effective than the standard 125'C burn-in as an early screen for infant mortality
defects. It sharply reduces the cost of testing incoming components. Reliability Report L-140 further explains the P +
process. The following chart lists regulators which receive
P + prior to shipment and at no additional cost.

The A + Product Enhancement incorporates the benefits of
the Multiple-Pass and Elevated Temperature along with
"BURN-IN."
The A + Program provides:
• 100% Temperature Cycling
• 100% Electrical Testing at Room and High Temperature
• 100% Burn-In Testing Combining Increased Temperature with Applied Voltage
• Acceptable Quality Levels Greater than Industry Norm

Package Types
Device

TO-3
TO-39H TO-220T TO-202P TO-92Z
KSTEEL

LM109/309

X

X

LM117/317

X

X

LM117HV/317HV

X

X

X

X

X

X

X

X

X

X

X

LM120/320

X

LM123/323

X

LM137/337

X

X

LM 137HV/337HV

X

X

LM138/338

X

LM140/340

X

LM145/345

X

LM150/250/350

X

LM196/396

X

X

LM2930/2935/2940/2984

X

LM2931

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Appendix 0
Military Aerospace Programs
from National Semiconductor

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This appendix is intended to provide a brief overview of mili·
tary products available from National Semiconductor. For
further information, refer to our 1987 Reliability Handbook.

MIL-STD-883
Although originally intended to establish uniform test methods and procedures, MIL-STD-883 has also become the
general specification for non-JAN military product. Revision
C of this document defines the minimum requirements for a
device to be marked and advertised as 883-compliant. Included are design and construction criteria, documentation
controls, electrical and mechanical screening requirements,
and quality control procedures. Details can be found in paragraph 1.2.1 of MIL-STD-883.

MIL-M-38510
The MIL-M-38510 Program, which is sometimes called the
JAN IC Program, is administered by the Defense Electronics
Supply Center (DESC). The purpose of this program is to
provide the military community with standardized products
that have been manufactured and screened to governmentcontrolled specifications in government-certified facilities.
All 38510 manufacturers must be formally qualified and their
products listed on DESC's Qualified Products List (QPL) before devices can be marked and shipped as JAN product.

National offers both 883 Class Band 883 Class S product.
The screening requirements for both classes of product are
outlined in Table III.
As with DESC specifications, a manufacturer is allowed to
use his standard electrical tests provided that all critical parameters are tested. Also, the electrical test parameters,
test conditions, test limits, and test temperatures must be
clearly documented. At National Semiconductor, this information is available via our RETS (Reliability Electrical Test
SpeCification Program). The RETS document is a complete
description of the electrical tests performed and is controlled by our QA department. Individual copies are available
upon request.
Some of National's older products are not completely compliant with MIL-STD-883 but are still required for use in military systems. These devices are screened to the same
stringent requirements as 883 product but are marked
"-MIL".

There are two processing levels specified within MIL-M38510: Classes Sand B. Class S is typically specified for
space flight applications, while Class B is used for aircraft
and ground systems. National is a major supplier of both
classes of devices. Screening requirements are outlined in
Table III.
Tables I and II explain the JAN device marking system.
Copies of MIL-M-38510, the QPL, and other related documents may be obtained from:
Naval Publications and Forms Center
5801 Tabor Avenue
Philadelphia, PA 19120
(212) 697-2179

DESC Specifications

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Military Screening Program (MSP)

DESC specifications are issued to provide standardized versions of devices which are not yet available as JAN product.
MIL-STD-883 Class B screening is coupled with tightly controlled electrical specifications which have been written to
allow a manufacturer to use his standard electrical tests. A
current listing of National's DESC speCification offerings can
be obtained from our franchised distributors, sales offices,
or DESC. DESC is located in Dayton, Ohio.

National's Military Screening Program was developed to
make screened versions of advanced products such as gate
arrays and microprocessors available more quickly than is
possible for JAN and 883 devices. Through this program,
screened product is made available for prototypes and
breadboards prior to or during the JAN or 883 qualification
activities. MSP products receive the 100% screening of Table III but are not subjected to Group C and D quality conformance testing. Other criteria such as electrical testing
and temperature range will vary depending upon individual
device status and capability.

PI
7-11

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TABLE I. The MIL·M-38510 Part Marking

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' - - Device Number on
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' - - - Slash Sheet Number

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' - - - - - For radiation hard devices
this slash is replaced by the
Radiation Hardness Assurance
Designator (M, D, R, or H per
paragraph 3.4.1.3 of MIL-M38510)

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Lead Finish
A = Solder Dipped
B TIn Plate
C Gold Plate
X Any lead finish above
is acceptable

'------MIL-M-38510
' - - - - - - - - JAN Prefix
(which may be applied only to
a fully conformant device per
paragraphs 3.6.2.1 and 3.6.7 of
MIL-M-38510)

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sequence or after seal test. Catastrophic failures are defined as missing leads, broken packages, or lids off.

Note 6: When specified, all devices shall be tested for those parameters requiring delta calculations.
Note 7: Reverse bias burn-in is a requirement only when specified in the applicable device specification. The order of performing burn-in and reverse bias burn-in
may be inverted.
Note 8: For Class S devices, the seal test may be performed in any sequence between step 16 and step 19, but it shall be performed after all shearing and forming
operations on the terminals.
Note 9: For Class B devices, the fine and gross seal tests shall be performed separate or together in any sequence and order between step 6 and step 20 except
that they shall be performed after all shearing and forming operations on the terminals. When 100% seal screen cannot be performed after shearing and forming
(e.g. flatpacks and chip carriers) the seal screen shall be done 100% prior to these operations and a sample test (LTPO ~ 5) shall be performed on each
inspection lot following these operations. If the sample fails, 100% rescreening shall be required.
Nole 10: The radiographic screen may be performed in any sequence after step 19.
Nole 11: Samples shall be selected for testing in accordance with the specific device class and lot requirements of Method 5005
Note 12: External Visual shall be performed on the lot any time after step 19 and prior to shipment.

Note 13: Read and Record when past burn-in delta measurements are specified.
Note 14: PDA shall apply to all static, dynamic, functional, and switching measurements at either 25°C or maximum rated operating temperature.

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·Some older products are not completely compliant with MIL-STO-883 but are still required for use in military systems. These devices are screened to the same
stringent requirements as 883 product but are marked "-MIL".

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7-17

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Appendix E
Understanding Integrated Circuit
Package Power Capabilities

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INTRODUCTION

The short and long term reliability of National Semiconduc·
tor's interface circuits, like any integrated circuit, is very de·
pendent on its environmental condition. Beyond the mechanical! environmental factors, nothing has a greater influence on this reliability than the electrical and thermal stress
seen by the integrated circuit. Both of these stress issues
are specifically addressed on every interface circuit data
sheet, under the headings of Absolute Maximum Ratings
and Recommended Operating Conditions.
However, through application calls, it has become clear that
electrical stress conditions are generally more understood
than the thermal stress conditions. Understanding the importance of electrical stress should never be reduced, but
clearly, a higher focus and understanding must be placed on
thermal stress. Thermal stress and its application to interface circuits from National Semiconductor is the subject of
this application note.

Failure rate is the number of devices that will be expected to
fail in a given period of time (such as, per million hours). The
mean time between failure (MTBF) is the average time (in
hours) that will be expected to elapse after a unit has failed
before the next unit failure will occur. These two primary
"units of measure" for device reliability are inversely related:
MTBF =

. 1
FaliureRate
Although the "bathtub" curve plots the overall failure rate
versus time, the useful failure rate can be defined as the
percentage of devices that fail per-unit-time during the flat
portion of the curve. This area, called the useful life, extends
between t1 and t2 or from the end of infant mortality to the
onset of wearout. The useful life may be as short as several
years but usually extends for decades if adequate design
margins are used in the development of a system.
Many factors influence useful life including: pressure, mechanical stress, thermal cycling, and electrical stress. However, die temperature during the device's useful life plays an
equally important role in triggering the onset of wearout.

FACTORS AFFECTING DEVICE RELIABILITY

Figure 1 shows the well known "bathtub" curve plotting failure rate versus time. Similar to all system hardware (mechanical or electrical) the reliability of interface integrated
circuits conform to this curve. The key issues associated
with this curve are infant mortality, failure rate, and useful
life.

FAILURE RATES vs TIME AND TEMPERATURE
The relationship between integrated circuit failure rates and
time and temperature is a well established fact. The occurrence of these failures is a function which can be represented by the Arrhenius Model. Well validated and predominantly used lor accelerated life testing of integrated Circuits, the
Arrhenius Model assumes the degradation of a performance
parameter is linear with time and that MTBF is a function of
temperature stress. The temperature dependence is an exponential function that defines the probability of occurrence.
This results in a formula for expressing the lifetime or MTBF
at a given temperature stress in relation to another MTBF at
a different temperature. The ratio of these two MTBFs is
called the acceleration factor F and is defined by the following equation:

INFANT
MORTALITY
(SHADED AREA)

to

11
EARLY LIFE

12
USEFUL LIFE

WEAROUT TIME

(.!.. _.!..) ]

TL/H/9312-1

F = X1 = exp [~
X2
K T2

FIGURE 1. Failure Rate vs Time

Infant mortality, the high failure rate from time to to t1 (early
life), is greatly influenced by system stress conditions other
than temperature, and can vary widely from one application
to another. The main stress factors that contribute to infant
mortality are electrical transients and noise, mechanical
maltreatment and excessive temperatures. Most of these
failures are discovered in device test, burn-in, card assembly and handling, and initial system test and operation. Although important, much literature is available on the subject
of infant mortality in integrated circuits and is beyond the
scope of this application note.

T1

Where: X1 = Failure rate at junction temperature T1
X2 = Failure rate at junction temperature T2
T

=

Junction temperature in degrees Kelvin

E = Thermal activation energy in electron volts
(ev)
K = Boltzman's constant

7-18

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However, the dramatic acceleration effect of junction temperature (chip temperature) on failure rate is illustrated in a
plot of the above equation for three different activation energies in Figure 2. This graph clearly demonstrates the importance of the relationship of junction temperature to device failure rate. For example, using the 0.99 ev line, a 30°
rise in junction temperature, say from 130°C to 160°C, results in a 10 to 1 increase in failure rate.
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flows from the chip to the ultimate heat sink, the ambient
environment. There are two predominant paths. The first is
from the die to the die attach pad to the surrounding package material to the package lead frame to the printed circuit
board and then to the ambient. The second path is from the
package directly to the ambient air.
Improving the thermal characteristics of any stage in the
flow chart of Figure 4 will result in an improvement in device
thermal characteristics. However, grouping all these characteristics into one equation determining the overall thermal
capability of an integrated circuit/package/environmental
condition is possible. The equation that expresses this relationship is:

-0

TJ = TA + PD(IIJA)
Where: TJ = Die junction temperature
T A = Ambient temperature in the vicinity device
PD = Total power dissipation (in watts)

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60
90 120 150 160 210
JUNCTION TEMPERATURE (OC)

Thermal resistance junction-to-ambient

=

OJA, the thermal resistance from device junction-to-ambient
temperature, is measured and specified by the manufacturers of integrated circuits. National Semiconductor utilizes
special vehicles and methods to measure and monitor this
parameter. All circuit data sheets specify the thermal characteristics and capabilities of the packages available for a
given device under specific conditions-these package
power ratings directly relate to thermal resistance junctionto-ambient or 0JA.
Although National provides these thermal ratings, it is critical that the end user understand how to use these numbers
to improve thermal characteristics in the development of his
system using IC components.

TLlH/9312-2

FIGURE 2. Failure Rate as a Function
of Junction Temperature
DEVICE THERMAL CAPABILITIES
There are many factors which affect the thermal capability
of an integrated circuit. To understand these we need to
understand the predominant paths for heat to transfer out of
the integrated circuit package. This is illustrated by Figures
3 and 4.
Figure 3 shows a cross-sectional view of an assembled integrated circuit mounted into a printed circuit board.
Figure 4 is a flow chart showing how the heat generated at
the power source, the junctions of the integrated circuit

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FIGURE 3. Integrated Circuit Soldered into a Printed Circuit Board (Cross-Sectional View)

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FIGURE 4" Thermal Flow (Predominant Paths)

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Lead Frame Material
Agure 7 shows the influence of lead frame material (both
die attach and device pins) on thermal resistance. This
graph compares our same 16-pin DIP with a copper lead
frame, a Kovar lead frame, and finally an Alloy 42 type lead
frame-these are lead frame materials commonly used in
the industry. Obviously the thermal conductivity of the lead
frame material has a significant impact in package power
capability. Molded interface circuits from National Semiconductor use the copper lead frame exclusively.

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FIGURE 9. Thermal Resistance vs Air Flow

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Other Factors
A number of other factors influence thermal resistance. The
most important of these is using thermal epoxy in mounting
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When a high power situation exists and the ambient temperature cannot be reduced, the next best thing is to provide air
flow in the vicinity of the package. The graph of Figure 9
illustrates the impact this has on thermal resistance. This
graph plots the relative reduction in thermal resistance normalized to the still air condition for our 16-pin molded DIP.
The thermal ratings on National Semiconductor's interface
circuits data sheets relate to the still air environment.

FIGURE 6. Thermal Resistance vs Die Size

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TL/H/9312-B

4 567B910
DIE SIZE (kMIL2)

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TLlH/9312-7

FIGURE 7. Thermal Resistance vs
Lead Frame Material

Some confusion exists between the difference in thermal
resistance junction-to-ambient (6JA) and thermal resistance
junction-to-case (6Jcl. The best measure of actual junction
temperature is the junction-to-ambient number since nearly
all systems operate in an open air environment. The only
situation where thermal resistance junction-to-case is important is when the entire system is immersed in a thermal bath
and the environmental temperature is indeed the case temperature. This is only used in extreme cases and is the exception to the rule and, for this reason, is not addressed in
this application note.

Board vs Socket Mount
One of the major paths of dissipating energy generated by
the integrated circuit is through the device leads. As a result
of this, the graph of Figure 8 comes as no surprise. This
compares the thermal resistance of our 16-pin package soldered into a printed circuit board (board mount) compared
to the same package placed in a socket (socket mount).
Adding a socket in the path between the PC board and the
device adds another stage in the thermal flow path, thus
increasing the overall thermal resistance. The thermal capabilities of National Semiconductor's interface circuits are
specified assuming board mount conditions. If the devices
are placed in a socket the thermal capabilities should be
reduced by approximately 5% to 10%.

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NATIONAL SEMICONDUCTOR
PACKAGE CAPABILITIES

Figures 10 and 11 show composite plots of the thermal
characteristics of the most common package types in the
National Semiconductor Linear Circuits product family. Figure 10 is a composite of the copper lead frame molded
package. Figure 11 is a composite of the ceramic (cavity)
DIP using poly die attach. These graphs represent board
mount still air thermal capabilities. Another, and final, thermal resistance trend will be noticed in these graphs. As the
number of device pins increase in a DIP the thermal resistance decreases. Referring back to the thermal flow chart,
this trend should, by now, be obvious.

Maximum Power Dissipation" at 25·C
Cavity Package
1509 mW
Molded Package 1476 mW

RATINGS ON INTERFACE CIRCUITS DATA SHEETS

• Derate cavity package at 10 mWi'C above 25"C; derate molded package
at 11.8 mW1°C above 25·C.

If the molded package is used at a maximum ambient temperature of 70·C, the package power capability is 945 mW.
PD

@

70·C = 1476 mW - (11.8 mWrC) x (70·C - 25·C)
=

945mW

Molded (N Package) DIP'
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sheets reflect a 15% safety margin from the average numbers found in this application note. Insuring that total package power remains under a specified level will guarantee
that the maximum junction temperature will not exceed the
package maximum.

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4 5 6 7 8910

DIE SIZE (kMIL2)

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4 5 6 7 8910

DIE SIZE (kMIL')

'Packages from 8· to 20·pin 0.3 mil width

'Packages from 8· to 20·pin 0.3 mil width

TLlH/9312-10

22-pin 0.4 mil width

TLlH/9312-11

22·pin 0.4 mil width

24· to 40·pin 0.6 mil width

24· to 48·pin 0.6 mil width

FIGURE 10. Thermal Resistance vs Ole Size
vs Package Type (Molded Package)

FIGURE 11. Thermal Resistance vs Die Size
vs Package Type (Cavity Package)

DIE-SIZE (WIL2)

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TLlH/9312-12

FIGURE 12
7-22

NatiOna'

~ Semiconductor
Corporation

APPENDIX f
How to Get the Right Information From a Data Sheet
Not All Data Sheets Are Created Alike, and False Assumptions Could Cost an Engineer Time and Money
By Robert A. Pease
When a new product arrives in the marketplace, it hopefully
will have a good, clear data sheet with it.

Every year, for the last 20 years, manufacturers have been
trying to explain, with varying success, why they do not measure the lin per se, even though they do guarantee it.

The data sheet can show the prospective user how to apply
the device, what performance specifications are guaranteed
and various typical applications and characteristics. If the
data-sheet writer has done a good job, the user can decide
if the product will be valuable to him, exactly how well it will
be of use to him and what precautions to take to avoid
problems.

In other cases, the manufacturer may specify a test that can
be made only on the die as it is probed on the wafer, but
cannot be tested after the die is packaged because that
signal is not accessible any longer. To avoid frustrating and
confusing the customer, some manufacturers are establishing two classes of guaranteed specifications:
• The tested limit represents a test that cannot be doubted, one that is actually performed directly on 100 percent
of the devices, 100 percent of the time.

SPECIFICATIONS
The most important area of a data sheet specifies the characteristics that are guaranteed-and the test conditions that
apply when the tests are done. Ideally, all specifications that
the users will need will be spelled out clearly. If the product
is similar to existing products, one can expect the data
sheet to have a format similar to other devices.

• The design limit covers other tests that may be indirect,
implicit or simply guaranteed by the inherent design of
the device, and is unlikely to cause a failure rate (on that
test), even as high as one part per thousand.
Why was this distinction made? Not just because customers
wanted to know which specifications were guaranteed by
testing, but because the quality-assurance group insisted
that it was essential to separate the tested guarantees from
the design limits so that the AQL (assurance-quality level)
could be improved from 0.1 percent to down below
100 ppm.

But, if there are significant changes and improvements that
nobody has seen before, then the writer must clarify what is
meant by each specification. Definitions of new phrases or
characteristics may even have to be added as an appendix.
For example, when fast-settling operational amplifiers were
first introduced, some manufacturers defined settling time
as the time after slewing before the output finally enters and
stays within the error-band; but other manufacturers included the slewing time in their definition. Because both groups
made their definitions clear, the user was unlikely to be confused or misled.

Some data sheets guarantee characteristics that are quite
expensive and difficult to test (even harder than noise) such
as long-term drift (20 ppm or 50 ppm over 1,000 hours).
The data sheet may not tell the reader if it is measured,
tested or estimated. One manufacturer may perform a 100percent test, while another states, "Guaranteed by sample
testing." This is not a very comforting assurance that a part
is good, especially in a critical case where only a long-term
test can prove if the device did meet the manufacturer's
specification. If in doubt, question the manufacturer.

However, the reader ought to be on the alert. In a few cases, the data-sheet writer is playing a specsmanship game,
and is trying to show an inferior (to some users) aspect of a
product in a light that makes it look superior (which it may
be, to a couple of users).
GUARANTEES

TYPICALS

When a data sheet specifies a guaranteed minimum value,
what does it mean? An assumption might be made that the
manufacturer has actually tested that specification and has
great confidence that no part could fail that test and still be
shipped. Yet that is not always the case.

Next to a guaranteed speCification, there is likely to be another in a column labeled "typical".
It might mean that the manufacturer once actually saw one
part as good as that. It could indicate that half the parts are
better than that speCification, and half will be worse. But it is
equally likely to mean that, five years ago, half the parts
were better and half worse. It could easily signify that a few
parts might be slightly better, and a few parts a lot worse;
after all, if the noise of an amplifier is extremely close to the
theoretical limit, one cannot expect to find anything much
better than that, but there will always be a few noisy ones.

For instance, in the early days of op amps (20 years ago),
the differential-input impedance might have been guaranteed at 1 Mfi-but the manufacturer obviously did not measure the impedance. When a customer insisted, "I have to
know how you measure this impedance," it had to be explained that the impedance was not measured, but that the
base current was. The correlation between Ib and lin permitted the substitution of this simple dc test for a rather
messy, noisy, hard-to-interpret test.

If the specification of interest happens to be the bias current
(Ib) of an op amp, a user can expect broad variations. For
example, if the specification is 200 nA maximum, there
might be many parts where Ib is 40 nA on one batch (where
the beta is high), and a month later, many parts where the Ib
is 140 nA when the beta is low.

Reprinted by permission from Electronic Engineering Times.

7-23

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Appendix G
Obsolete Product Replacement Guide

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Some device types, individual temperature grades and package options have been discontinued. This guide is provided to help
design engineers select and specify an appropriate alternative.

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NSC Part Number

Replacement

Note

NSC Part Number

Replacement

Note

ADB1200
DAC1200/1201
LF352
LF13300
LHOOOl
LHOO05/LHOO05A
LH0037
LH0132
LH2011
LH21 08
LH2201A
LH2208
LH2208A
LH2308
LH24250
LM170/270/370
LM171 1271 1371
LM172/272/372
LM173/273/373
LM174/274/374
LM175/275/375
LM216/316
LM388N-2/N-3
LM377N
LM378N
LM379
LM1014
LM1017
LM1019

ADC3711
DAC1265
LM3631
ADC3711
LM4250
LHOO03
LH0036
LH0032
LMll
LM108
LM201A
LM208
LM208A
LM308
LMll
LM13600N
no replacement
no replacement
no replacement
no replacement
no replacement
LM11
LM388N-l
LM2877P
LM2878P
LM2879T
no replacement
no replacement
no replacement

2
2
2
2
2
2
3
2
2
2
2
2
2
2
2
2

LM1821S
LM1822
LM1828
LM1848
LM1877N-l/N-2/N-3
LM2003
LM280B
LM2831
LM3011
LM3064
LM3075
TBA120V
TBA440C
TBA51 0
TBA530
TBA540
TBA560C
TBA920
TBA950-2
TBA970
TBA990
TDA440
TDA2522/23
TDA2530
TDA2530/31
TDA2540/41
TDA2560
TDA2590
TDA3500

LM1823
LM1823
no replacement
no replacement
LM1877N-9
no replacement
no replacement
LM1851
no replacement
no replacement
no replacement
no replacement
LM1823
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement

2
3

2
2
3
3
3

Note 1: IMPROVED REPLACEMENT: Pin for Pin replacement with superior electrical specifications.
Note 2: FUNCTIONAL REPLACEMENT: Consult datasheet to determine suitability of the replacement for specific application.
Note 3: SIMILAR DEVICE with superior performance: Consult datasheet to determine suitability of the replacement for specific application.

7-27

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Appendix H
Products Not Recommended for New Designs

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The popular National Semiconductor Corporation monolithic IC's may have been designed into your systems. We believe that
there are more cost-effective circuits manufactured by National Semiconductor Corporation that should be considered in your
new designs. These recommendations are listed in this section. To eliminate the necessity to redesign proven equipment, we
are continuing to make these products for use in existing designs for which they were uniquely suitable.

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NSC Part Number

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AF100
AF150
AF151
AHOO14
AHOO15
AHOO19
LHOO23
LH2101A
LH2108A
LH2110
LH2111
LH2210
LH2211
LH2301A
LH2308A
LH231 0
LH2311
LM103
LM113
LM313
LM377N
LM377N
LM37BN
LM391N-60
LM391N-80
LM709
LM710
LM725
LM748

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