1988_National_Linear_Databook_Volume_2 1988 National Linear Databook Volume 2
User Manual: 1988_National_Linear_Databook_Volume_2
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NatiOnal
Semiconductor
Corporation
400042
Rev. 1
Linear
Databook
2
1988 Edition
General Information
Alphanumeric
Cross Reference Guide by Part Number
Package Cross Reference
Linear Databook 1 Selection Guides
Voltage Regulators
Operational Amplifiers
Buffers
Voltage Comparators
Instrumentation Amplifiers
Linear Databook 3 Selection Guides
Audio Circuits
Radio Circuits
Video Circuits
Motion Control
Special Functions
Voltage References
II
I
D
II
I
I
II
Surface Mount
[I
Active Fiiters
Analog Switches/Multiplexers
Analog-to-Digital Converters
Digital-to-Analog Converters·
Sample and Hold
Temperature Sensors
Appendices/Physical Dimensions
iii
a
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National does not assume any responsibility for use of any circuitry described, no circuH patent licenses are implied, and National reserves the right, at any time
without notice. to change said circuitry or specifications.
iv
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Linear Products
Introduction
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National Semiconductor Corporation first established itself
as the Linear Leader in 1967 with the introduction of the
FIRST MONOLITHIC VOLTAGE REGULATOR ... LM100. In
the 20 years since, many of our products were firsts in performance and function. Today, this catalog spans the traditional areas of Op Amps, Voltage Regulators, Voltage References and Temperature Sensors, to Data Acquisition, Communication, Automotive, and Power Plus Control. National
Semiconductor intends to remain a leader in the traditional
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specific application note has been provided. This handbook
and the 3-volume set of Linear Data Books represent a complete base of information to the National LINEAR product
line.
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Product Status Definitions
1)
:::a
'0
e
A.
Definition of Terms
Data Sheet Identification
Product Status
Definition
Formative or
In Design
This data sheet contains the design specifications for product
development. Specifications may change in any manner without notice.
First
Production
This data sheet contains preliminary data and supplementary data will
be published at a later date. National Semiconductor Corporation
reserves the right to make changes at any time without notice in order
to improve design and supply the best possible product.
Full
Production
This data sheet contains final specifications. National Semiconductor
Corporation reserves the right to make changes at any time without
notice in order to improve design and supply the best possible product.
National Semiconductor Corporation reserves the right to make changes without further notice to any products herein to
improve reliability, function or deSign. National does not assume any liability arising out of the application or use of any product
or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.
vi
Table of Contents
Alphanumeric Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cross Reference by Part Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Cross Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Linear 1 Selection Guides .....................................................
Voltage Regulators Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Regulators Selection Guide. . . . . . . . . . . . . • . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operational Amplifiers Definition ofTerms .......................................
Operational Amplifiers Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffers Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffers Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . • . . . . . . . . .
Voltage Comparator Definition ofTerms . ........ ...... .. ....... .. ..... ..........
Voltage Comparator Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instrumentation Amplifiers Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instrumentation Amplifiers Selection Guide ......................................
Linear 3 Selection Guides .....................................................
Audio Circuits Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audio Circuits Selection Guide .................................................
Radio Circuits Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Radio Circuits Selection Guide .................................................
Video Circuits Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Circuits Selection Guide .................................................
Motion Control Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Functions Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 1 Active Filters
Active Filters Definition ofTerms ...............................................
Active Filters Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AF100 Universal Active Filter ..................................................
AF150 Universal Wideband Active Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AF151 Dual Universal Active Filter..............................................
LMF60 6th Order LMCMOSTM Switched Capacitor Butterworth Lowpass Filter. . . . . . . .
* LMF90 4th-Order LMCMOSTM Programmable Elliptic Notch Filter. . . . . . . . . . . . . . . . . . .
* LMF100 Universal Monolithic Dual Switched Capacitor Filter.. ...... ..... ......... .
* LMF120 Mask Programmable Switched Capacitor Filter...... ...... .... ..... ..... .
MF4 4th Order Switched Capacitor Butterworth Lowpass Filter ............. . . . . . . . .
MF5 Universal Monolithic Switched Capacitor Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MF6 6th Order Switched Capacitor Butterworth Lowpass Filter . . . . . . . . . . . . . . . . . . . . .
* MF8 4th Order Switched Capacitor Bandpass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MF10 Universal Monolithic Dual Switched Capacitor Filter... ...... ... .... ........ .
Section 2 Analog Switches/Multiplexers
Analog Switches/Multiplexers Definition of Terms ...............................•
Analog Switches/Multiplexers Selection Guide. . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0014/ AH0014C DPDT, AH0015C Quad SPST, AH0019/ AH0019C Dual DPSTTTTL/PTLD Compatible MOS Analog Switch ..................................
AH5009/ AH501 0/ AH5011 / AH5012 Monolithic Analog Current Switch ..............
AH5020C Monolithic Analog Current Switch..... ... .. ............. ...... ........ .
CD4016C Quad Bi-Lateral Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . .
CD4051 BM/CD4051 BC Single 8-Channel Analog Multiplexer/Demultiplexer. . . . . . . . .
CD4052BM/CD4052BC Dual8-Channel Analog Multiplexer/Demultiplexer ..........
CD4053BM/CD4053BC Triple 8-Channel Analog Multiplexer/Demultiplexer. . . . . . . . . .
CD4066BM/CD4066BC Quad Bi-Lateral Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4529BC Dual 4-Channel or 8-Channel Analog Data Election. . . . . . . . . . . . . . . . . . . . .
"Devices Not Covered In Last Publication
vii
1
13
19
23
24
25
28
29
38
39
40
41
42
43
45
46
47
51
52
56
58
61
62
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
1-12
1-13
1-26
1-41
1-59
1-81
2-3
2-4
2-5
2-6
2-17
2-25
2-32
2-32
2-32
2-40
2-46
Table of Contents (Continued)
Section 2 Analog Switches/Multiplexers (Continued)
LF11331/LF13331/LF11332/LF1333/LF13333,LF11201/LF13201/LF112021
LF13202 Quad SPST JFET Analog Switches. . • . . . . . . . . . . . . . . . . . . . . . . . • . . • . • • . .
2-52
LF13508 8-Channel Analog Multiplexer. . . • . . • . . . . . • . . . . . • . . . . . • . . . . . • • . • . . • • . . . •
2-63
LF13509 4-9hannel Analog Multiplexer.. ....•.....•.....•..••.••.••.••.•..••....
2-63
• MM54HC4016/MM74HC4016 Quad Analog Switch...............................
2-77
• MM54HC4051/MM74HC4051 8-Channel Analog Multiplexer.......................
2-84
• MM54HC4052/MM74HC4052 Dual4-Channel Analog Multiplexer..................
2-84
• MM54HC4053/MM74HC4053 Triple 2-Channel Analog Multiplexer. . .. . . •. .. • .. • . • •
2-84
• MM54HC4066/MM74HC4066 Quad Analog Switch...............................
2-91
• MM54HC4316/MM74HC4316 Quad Analog Switch with Level Translator. ..•........
2-96
Section 3 Analog-to-Digital Converters
Analog-to-Digital Converters Definition ofTerms .••.••.•.. ....•• .••.......•••••...
3-3
Analog-to-Digital Converters Selection Guide. . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • • . .
3-4
ADC0800 8-Bit AID Converter .......................•................•........
3-7
ADC0801, ADC0802, ADC0803, ADC0804, ADC0805 8-Bit p.P Compatible AID
Converters .......•..•.........•.....•............•.....•.•..••••..•....•..
3-16
ADC0808, ADC0809 8-Bit p.P Compatible AID Converters with 8-Channel M~ltiplexer .
3-48
ADC0811 8-Bit Serial 1/0 AID Converter with 11-Channel Multiplexer. . • . . . . . . . . . • . .
3-59
ADC0816, ADC0817 8-Bit p.P Compatible AID Converters with 16-Channel Multiplexer
3-70
3-81
• ADC0819 8-Bit Serial 1/0 AID Converter with 19-C~annel Multiplexer. . . . . . . . . . . . . . .
ADC0820 8-Bit High Speed p.P Compatible A/D Converter with Track/Hold Function. •
3-91
ADC0829 p.P Compatible 8-Bit AID with 11-Channel MUX/Digitallnput . . . . . . . . • . . . . • 3-107
ADC0831, ADC0832, ADC0834 and ADC0838 8-Bit Serial 1/0 A/D 90nverters with
Multiplexer Options . . . • . . . . . • . . . • . . . . . . . . • . . • . . • . . • • . . • . . . . . • . . . . • . . . . . . . • . • 3-.115
ADC0833 8-Bit Serial 110 AID Converter with 4-Channel Multiplexer.. . . .. . • . .• .. . . . 3-140
• ADC0841 8-Bit p.P Compatible AID Converter. . • • . . . . . . . • . . . . • . . . . . . • . . . . . . . • • . • • 3-158
ADC0844/ADC0848 8-Bit p.P Compatible A/D Converters with Multiplexer Options. •.
3-171
ADC0852/ ADC0854 Multiplexed Comparator with 8-Bit Reference Divider . • • • . • • . . • • 3-188
ADC1 001, ADC1021 10-Bit p.P Compatible AID Converters. . . . . . • . . . . . . . . • . . . . . . . . 3-206
ADC1005, ADC1025 1O-Bit p.P Compatible AID Converters. . . . . . . . . . . . . . . . . . . . . . . . 3-213
ADC1205, ADC1225 12-Bit Plus Sign p.P Compatible AID Converters .•..••.•••••.•• 3-224
ADC1210, ADC1211 12-Bit CMOS AID Converters . . • . . . . . . • . . • • . . . . . . . . . . . . • • . . . 3-241
ADC3511 3Yz-Digit Microprocessor Compatible AID Converter. . . • . . . . . . . . • • . • • . . • . 3-252
ADC3711 3%-Digit Microprocessor Compatible AID Converter. . • . . . . . . . . . . . . . . . . . •. 3-252
ADD3501 3Yz-Digit DVM with Multiplexed 7-Segment Output. . . .. . . . • . . . . . .•. • .. . . . 3-261
ADD3701 3%-Digit DVM with Multiplexed 7-Segment Output....................... 3-270
DM2502, DM2503, DM2504 Successive Approximation Registers. . . . . . . . . . . . . . . . • . . 3-280
LM131A1LM131, LM231A1LM231, LM331A1LM331 Precision VOltage-to-Frequency
Converters •..•...•.•...•.........•..•.........................•.••..••••.. 3-285
MM74C905 12-Bit Successive Approximation Register .•.. • . . • . . • . . . • • . • • • • • . • • • • • 3-296
Section 4 Digital-to-Analog Converters
Digital-to-Analog Converters Definition of Terms. . . . . . . . • . . . • . • • . . . . . . . . . . . . • . . . . .
4-3
Digital-to-Analog Converters Selection Guide. . . . . . . . . . . . . . . • . . . • . . . . . • . . • • • . • . • • .
4-4
DAC0800, DAC0801, DAC0802 8-Bit Digital-to-Analog Converters . . . . . • . . • . . . . . . . . .
4-6
DAC0808, DAC0807, DAC0806 8-Bit D/A Converters.............................
4-15
DAC0830, DAC0831, DAC0832 8-Bit p.P Compatible Double-Buffered D to A
4-23
Converters .•...•..••.•...••..•..••.•..•.....••..........................•.
DAC1000, DAC1 001, DAC1002, DAC1006, DAC1 007, DAC1008, p.P Compatible,
4-41
Double-Buffered D to A Converters . • • . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
·Devlces Not Covered In Last Publication
viii
Table of Contents (Continued)
Section 4 Dlgltal-to-Analog Converters (Continued)
DAC1020, DAC1021 , DAC1022, DAC1220, DAC1221, DAC122212-Bit Binary
Multiplying D/A Converters .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC1208, DAC1209, DAC121 0, DAC1230, DAC1231 , DAC1232 12-Bit p.P Compatible
Double-Buffered D to A Converters.. ....... ... .... . ........ ................. .
DAC1218, DAC1219 12-Bit Multiplying D/ A Converters. . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC1265A, DAC1265 Hi-Speed 12-Bit DI A Converter with Reference. . . . . . . . . . . . . . .
DAC1266A, DAC1266 Hi-Speed 12-Bit D/ A Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
* DAC165516-Bit D/A Converter................................................
Section 5 Sample and Hold
Sample and Hold Definition ofTerms. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. ... . .
Sample and Hold Selection Guide ..............................................
LF198/LF298/LF198A1LF398A Monolithic Sample and Hold Circuits ...... . . . . . . . . .
LF13006/LF13007 Digital Gain Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LH0023/LH0023C/LH0043/LH0043C Sample and Hold Circuits ...................
LH0053/LH0053C High Speed Sample and Hold Amplifier. . . . . . . . . . . . . . . . . . . . . . . . .
LH0091 True RMS to DC Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LH0094 Multifunction Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 6 Temperature Sensor
Temperature Sensor Selection Guide ...........................................
LM34/LM34A1LM34C/LM34CAlLM34D Precision Fahrenheit Temperature Sensors. .
LM35/LM35A1LM35C/LM35CAlLM35D Precision Centigrade Temperature Sensors.
LM135/LM235/LM335/LM135A1LM235A1LM335A Precision Temperature Sensors..
LM3911 Temperature Controller ............................................ , . . .
Section 7 Voltage Reference
Voltage Reference Selection Guide................... ............... ... .. ......
LH0070 Series BCD Buffered Reference/LH0071 Series Precision Buffered Reference
LM103 Reference Diode......................................................
LM113/LM313 Precision Reference............................................
LM129/LM329 Precision Reference............................................
LM134/LM234/LM334 3-Terminal Adjustable Current Sources............... ......
LM136-2.5/LM236-2.5/LM336-2.5V Reference Diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM136-5.0/LM236-5.0/LM336-5.0V Reference Diode. . . . .. . . . . . . . . . . . . . . . . . . . . . . .
LM168/LM268/LM368 Precision Vol~ge Reference..... .............. . .... .... ..
* LM169/LM369 Precision Voltage Reference. .............. ....... ... .. ......... .
LM185-1.2/LM285-1.2/LM385-1.2 Micropower Voltage Reference Diode. . . . . . . . . . . .
LM185-2.5/LM285-2.5/LM385-2.5 Micropower Voltage Reference Diode.. ........ ..
LM185/LM285/LM385 Adjustable Micropower Voltage References.. ... .. ..........
LM199/LM299/LM399/LM3999 Precision Reference................... ..........
* LM368-2.5 Precision Voltage Reference ...... .......... .... .. .... ......... ......
* LM581 Voltage Reference Precision 10-Volt .....................................
Section 8 Surface Mount
Surface Mount ........... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 9 Appendices/Physical Dimensions
Appendix A General Product Marking and Code Explanation .......................
Appendix B Application Note Referenced by Part Number. . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix C Summary of Commercial Reliability Programs. . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix D Military Aerospace Programs from National Semiconductor. . . . . . . . . . . . . .
Appendix E Understanding Integrated Circuit Package Power Capabilities. . . . . . . . . . . .
Appendix F How to Get the Right Information from a Datasheet . . . . . . . . . . . . . . . . . . . . .
Appendix G Obsolete Product Replacement Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
"Device. Nol Covered In La.. Publlcllllon
ix
4-64
4-74
4-89
4-100
4-109
4-117
5-3
5-4
5-5
5-15
5-22
5-23
5-24
5-29
6-3
6-4
6-12
6-21
6-30
7-3
7-7
7-11
7-12
7-15
7-20
7-28
7-35
7-42
7-48
7-58
7-64
7-69
7-76
7-85
7-91
8-3
9-3
9-4
9-10
9-11
9-18
9-23
9-27
Table of Contents (Continued)
Section 9 Appendices/Physical Dimensions (Continued)
Appendix H Products Not Recommended for New Design. . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Dimensions ........................... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors
·Devlces Not Covered In Last Publication
x
9-28
9-29
Alpha-Numeric Index
ADC0800 8-Bit AID Converter .............................................................. 3-7
ADC0801 8-Bit J.LP Compatible AID Converters ............................................... 3-16
ADC0802 8-Bit J.LP Compatible AID Converters ............................................... 3-16
ADC0803 8-Bit J.LP Compatible AID Converters ............................................... 3-16
ADC0804 8-Bit J.LP Compatible AID Converters ............................................... 3-16
ADC0805 8-Bit J.LP Compatible AI D Converters ............................................... 3-16
ADC0808 8-Bit J.LP Compatible AID Converters with 8-Channel Multiplexer ....................... 3-48
ADC0809 8-Bit J.LP Compatible AID Converters with 8-Channel Multiplexer ....................... 3-48
ADC0811 8-Bit Serial 1/0 AID Converter with 11-Channel Multiplexer ........................... 3-59
ADC0816 8-Bit J.LP Compatible AID Converters with 16-Channel Multiplexer ...................... 3-70
ADC0817 8-Bit J.LP Compatible AID Converters with 16-Channel Multiplexer ...................... 3-70
ADC0819 8-Bit Serial 1/0 AID Converter with 19-Channel Multiplexer ........................... 3-81
ADC0820 8-Bit High Speed J.LP Compatible AID Converter with Track/Hold Function .............. 3-91
ADC0829 J.LP Compatible 8-Bit AID with 11-Channel MUX/Digitallnput. ........................ 3-107
ADC0831 8-Bit Serial 1/0 AID Converters with Multiplexer Options ............................ 3-115
ADC0832 8-Bit Serial 1/0 AID Converters with Multiplexer Options ............................ 3-115
ADC0833 8-Bit Serial 110 AID Converter with 4-Channel Multiplexer ........................... 3-140
ADC0834 8-Bit Serial 1/0 AID Converters with Multiplexer Options ............................ 3-115
ADC0838 8-Bit Serial 1/0 AID Converters with Multiplexer Options ............................ 3-115
ADC0841 8-Bit J.LP Compatible AID Converter ............................................... 3-158
ADC0844 8-Bit J.LP Compatible AID Converters with Multiplexer Options •....................... 3-171
ADC0848 8-Bit J.LP Compatible AID Converters with Multiplexer Options ........................ 3-171
ADC0852 Multiplexed Comparator with 8-Bit Reference Divider ...•............................ 3-188
ADC0854 Multiplexed Comparator with 8-Bit Reference Divider ................................ 3-188
ADC1001 1O-Bit J.LP Compatible AID Converters ............................................ 3-206
ADC1005 1O-Bit J.LP Compatible AID Converters ............................................ 3-213
ADC1021 1O-Bit J.LP Compatible AID Converters ............................................ 3-206
ADC1025 1O-Bit J.LP Compatible AID Converters ............................................ 3-213
ADC1205 12-Bit Plus Sign J.LP Compatible AID Converters .................................... 3-224
ADC1210 12-Bit CMOS AID Converters .................................................... 3-241
ADC1211 12-Bit CMOS AID Converters .................................................... 3-241
ADC1225 12-Bit Plus Sign J.LP Compatible AID Converters .................................... 3-224
ADC3511 3%-Digit Microprocessor Compatible AID Converter ................................ 3-252
ADC3711 3%-Digit Microprocessor Compatible AID Converter ................................ 3-252
ADD3501 3%-Digit DVM with Multiplexed 7-Segment Output .................................. 3-261
ADD3701 3%-Digit DVM with Multiplexed 7-Segment Output .................................. 3-270
AF100 Universal Active Filter ................................................................ 1-5
AF150 Universal Wideband Active Filter ...................................................... 1-6
AF151 Dual Universal Active Filter ........................................................... 1-7
AH0014 Dual DPST-TTTL/DTLD Compatible MOS Analog Switch ............................... 2-5
AH0014C DPDT Dual DPST-TTTL/DTLD Compatible MOS Analog Switch ........................ 2-5
AH0015C Quad SPST Dual DPST-TTTL/DTLD Compatible MOS Analog Switch ................... 2-5
AH0019 Dual DPST-TTTL/DTLD Compatible MOS Analog Switch ............................... 2-5
AH0019C Dual DPST-TTTL/DTLD Compatible MOS Analog Switch .............................. 2-5
AH5009 Monolithic Analog Current Switch ................................•................... 2-6
AH5010 Monolithic Analog Current Switch .................................................... 2-6
AH5011 Monolithic Analog Current Switch .................................................... 2-6
AH5012 Monolithic Analog Current Switch .................................................... 2-6
AH5020C Monolithic Analog Current Switch .................................................. 2-17
CD4016C Quad Bi-Lateral Switch ........................................................... 2-25
CD4051 BC Single 8-Channel Analog Multiplexer/Demultiplexer ................................ 2-32
Alpha-Numeric Index(continUed)
CD4051 BM Single 8-Channel Analog Multiplexer/Demultiplexer ................................ 2-32
CD4052BC Dual8-Channel Analog Multiplexer/Demultiplexer .................................. 2-32
CD4052BM Dual8-Channel Analog Multiplexer/Demultiplexer •................................ 2-32
CD4053BC Triple 8-Channel Analog Multiplexer/Demultiplexer ................................. 2-32
CD4053BM Triple 8-Channel Analog Multiplexer/Demultiplexer ................................. 2-32
CD4066BC Quad Bi-Lateral Switch ......................................................... 2-40
CD4066BM Quad Bi-Lateral Switch .................•....................................... 2-40
CD4529BC Dual 4-Channel or 8-Channel Analog Data Election ................................. 2-46
DAC0800 8-Bit Digital-to-Analog Converters ......................•...........•......•.•...... 4-6
DAC0801 8-Bit Digital-to-Analog Converters .................................................. 4-6
DAC0802 8-Bit Digital-to-Analog Converters .................................................. 4-6
DAC0806 8-Bit D/ A Converters ............•............................................... 4-15
DAC0807 8-Bit D/ A Converters ....................•.... '................................... 4-15
DAC0808 8-Bit D/ A Converters ............................................................ 4-15
DAC0830 8-Bit ,...p Compatible Double-Buffered D to A Converters .............................. 4-23
DAC0831 8-Bit,...P Compatible Double-Buffered D to A Converters .............................. 4-23
DAC0832 8-Bit ,...p Compatible Double-Buffered D to A Converters .............................. 4-23
DAC1000 ,...p Compatible, Double-Buffered D to A Converters .................................. 4-41
DAC1001 ,...p Compatible, Double-Buffered D to A Converters .................................. 4-41
DAC1002 ,...p Compatible, Double-Buffered D to A Converters .................................. 4-41
DAC1006 ,...p Compatible, Double-Buffered D to A Converters ...•.............................. 4-41
DAC1007 ILP Compatible, Double-Buffered D to A Converters ............•..........•.......... 4-41
DAC1008 ,...p Compatible, Double-Buffered D to A Converters .................................. 4-41
DAC1020 12-Bit Binary Multiplying D/ A Converters ........................................... 4-64
DAC1021 12-Bit Binary Multiplying D/ A Converters ....................... , ................... 4-64
DAC1022 12-Bit Binary Multiplying D/ A Converters ........................................... 4-64
DAC1208 12-Bit ,...p Compatible Double-Buffered D to A Converters ......................•...... 4-74
DAC1209 12-Bit ,...p Compatible Double-Buffered D to A Converters ............................. 4-74
DAC1210 12-Bit,...P Compatible Double-Buffered D to A Converters ......................•...... 4-74
DAC1218 12-Bit Multiplying D/ A Converters ................................................. 4-89
DAC1219 12-Bit Multiplying D/ A Converters ............................•.................... 4-89
DAC1220 12-Bit Binary Multiplying D/A Converters ........................................... 4-64
DAC1221 12-Bit Binary Multiplying D/A Converters ........................................... 4-64
DAC1222 12-Bit Binary Multiplying D/ A Converters ........................................... 4-64
DAC1230 12-Bit ,...p Compatible Double-Buffered D to A Converters .....................•....... 4-74
DAC1231 12-Bit,...P Compatible Double-Buffered D to A Converters ............................. 4-74
DAC1232 12-Bit,...P Compatible Double-Buffered D to A Converters ............................. 4-74
DAC1265 Hi-Speed 12-Bit D/ A Converter with Reference .................................... 4-100
DAC1265A Hi-Speed 12-Bit D/ A Converter with Reference ................................... 4-100
DAC1266 Hi-Speed 12-Bit D/ A Converter .................................................. 4-109
DAC1266A Hi-Speed 12-BitD/A Converter ......•.......................................... 4-109
DAC1655 16-Bit D/ A Converter ........................................................... 4-117
DM2502 Successive Approximation Registers ............................................... 3-280
DM2503 Successive Approximation Registers ............................................... 3-280
DM2504 Successive Approximation Registers .......•....................................... 3-280
HS7067 7 Amp, Multimode, High Efficiency Switching Regulator ............................. Linear 1
HS7107 7 Amp, Multimode, High Efficiency Switching Regulator' ............................. Linear 1
HS9151 Micro-Switching Off-Line Power Converter 1201VAC/ + 5V .......................... Linear 1
LF111 Voltage Comparators ..............................•............................. Linear 1
LF147 Wide Bandwidth Quad JFET Input Operational Amplifiers ............................. Linear 1
LF155 Low Supply Current .............................................................. Linear 1
2
Alpha-Numeric
Index(continUed)
LF155 Series Monolothic JFET Input Operational Amplifiers ................................. Linear 1
LF156 Series Monolothic JFET Input Operational Amplifiers ................................. Linear 1
LF156 Wide Band ...................................................................... Linear 1
LF157 Series Monolothic J FET Input Operational Amplifiers ................................. Linear 1
LF157 Wide Band Decompensated (AVMIN = 5) .......................................... Linear 1
LF198 Monolithic Sample and Hold Circuits ................................................... 5-5
LF198A Monolithic Sample and Hold Circuits ................•................................. 5-5
LF211 Voltage Comparators ............................................................ Linear 1
LF255 Low Supply Current .............................................................. Linear 1
LF256 Wide Band ...................................................................... Linear 1
LF257 Wide Band Decompensated (AVMIN = 5) .......................................... Linear 1
LF298 Monolithic Sample and Hold Circuits ................................................... 5-5
LF311 Voltage Comparators ............................................................ Linear 1
LF347 Wide Bandwidth Quad JFET Input Operational Amplifiers ............................. Linear 1
LF347A Wide Bandwidth Quad JFET Input Operational Amplifiers ............................ Linear 1
LF351 Wide Bandwidth JFET Input Operational Amplifier .................................... Linear 1
LF353 Wide Bandwidth Dual JFET Input Operational Amplifier ............................... Linear 1
LF355 Low Supply Current .............................................................. Linear 1
LF356 Wide Band ...................................................................... Linear 1
LF357 Wide Band Decompensated (AVMIN = 5) .......................................... Linear 1
LF398A Monolithic Sample and Hold Circuits .................................................. 5-5
LF400C Fast Settling JFET Input Operational Amplifier ..................................... Linear 1
LF401 Precision Fast Settling JFET Input Operational Amplifier ...............•.............. Linear 1
LF411 Low Offset, Low Drift JFET Input Operational Amplifier ............................... Linear 1
LF412 Low Offset, Low Drift Dual JFET Operational Amplifier ................................ Linear 1
LF441 Low Power JFET Input Operational Amplifier ........................................ Linear 1
LF442 Dual Low Power JFET Input Operational Amplifier .................................... Linear 1
LF444 Quad Low Power JFET Input Operational Amplifier ................................... Linear 1
LF455 Series Monolithic JFET Operational Amplifier ........................................ Linear 1
LF456 Series Monolithic JFET Operational Amplifier ........................................ Linear 1
LF457 Series Monolithic JFET Operational Amplifier ........................................ Linear 1
LF1333 Quad SPST JFET Analog Switches .................................................. 2-52
LF11201 Quad SPST JFET Analog Switches ................................................. 2-52
LF11202 Quad SPST JFET Analog Switches ................................................. 2-52
LF11331 Quad SPST J FET Analog Switches ................................................. 2-52
LF11332 Quad SPST JFET Analog Switches ................................................. 2-52
LF13006 Digital Gain Set .................................................................. 5-15
LF13007 Digital Gain Set .................................................................. 5-15
LF13201 Quad SPST JFET Analog Switches ................................................. 2-52
LF13202 Quad SPST JFET Analog Switches ................................................. 2-52
LF13331 Quad SPST JFET Analog Switches ................................................. 2-52
LF13333 Quad SPST JFET Analog Switches ................................................. 2-52
LF13508 8-Channel Analog Multiplexer ...................................................... 2-63
LF13509 4-Channel Analog Multiplexer ...................................................... 2-63
LF13741 Monolithic JFET Input Operational Amplifier ....................................... Linear 1
LH0002 Current Amplifier ............................................................... Linear 1
LH0003 Wide Bandwidth Operational Amplifier ............................................ Linear 1
LH0004 High Voltage Operational Amplifier ...................•..........•................ Linear 1
LH0020 High Gain Operational Amplifier .....•............................................ Linear 1
LH0021 1.0 Amp Power Operational Amplifier ............................................. Linear 1
LH0022 High Performance FET Op Amp ......................•........................... Linear 1
3
Alpha-Numeric
Index{continUed)
LH0023 Sample and Hold Circuits .......................................................... 5-22
LH0023C Sample and Hold Circuits ........................................•................ 5-22
LH0024 High Slew Rate Operational Amplifier ............................................. Linear 1
LH0032 Ultra Fast FET-Input Operational Amplifier ......................................... Linear 1
LH0033 Fast Buffer Amplifiers ............................•............................•. Linear 1
LH0036 Instrumentation Amplifier ........................................................ Linear 1
LH0038 True Instrumentation Amplifier .............................................••.... Linear 1
LH0041 0.2 Amp Power Operational Amplifier ..........................•.................. Linear 1
LH0042 Low Cost FET Op Amp ................................•......................... Linear 1
LH0043 Sample and Hold Circuits ...............................................•.......... 5-22
LH0043C Sample and Hold Circuits .........................•.....•.......•................. 5-22
LH0044 Series Precision Low Noise Operational Amplifiers .................................. Linear 1
LH0045 Two Wire Transmitter ........................................................... Linear 1
LH0052 Precision FET Op Amp .......................................................... Linear 1
LH0053 High Speed Sample and Hold Amplifier .............................................. 5-23
LH0053C High Speed Sample and Hold Amplifier ......................... '; ................... 5-23
LH0061 0.5 Amp Wide Band Operational Amplifier ..................................•...•.. Linear 1
LH0062 High Speed FET Operational Amplifier ............................................ Linear 1
LH0070 Series BCD Buffered Reference ...................................................... 7-7
LH0071 Series Precision Buffered Reference ................................................. 7-7
LH0075 Positive Precision Programmable Regulator ........................................ Linear 1
LH0076 Negative Precision Programmable Regulator ....................................... Linear 1
LH0082 Optical Communication Receiver/Amplifier ........................................ Linear 1
LH0084 Digitally-Programmable-Gain Instrumentation Amplifier .............................. Linear 1
LH0086 Digitally-Programmable-Gain Amplifier ............................................ Linear 1
LH0091 True RMS to DC Converter ......................................................... 5-24
LH0094 Multifunction Converter .............•.............................................. 5-29
LH0101 Power Operational Amplifier ..................................................... Linear 1
LH4001 Wideband Current Buffer .................................................•...... Linear 1
LH4002 Wideband Video Buffer ......................................................... Linear 1
LH4003 Precision RF Closed Loop Buffer ................................................. Linear 1
LH4004 Wideband FET Input Buffer/Amplifier ............ , ..........•.........•. , ......... Linear 1
LH4006 Precision RF Closed Loop Buffer ................................................. Linear 1
LH4101 Wide band High Current Operational Amplifier ...................................... Linear 1
LH41 01 C Wideband High Current Operational Amplifier ..................................... Linear 1
LH41 04 Fast Settling High Current Operational Amplifier .................................... Linear 1
LH41 05 Precision Fast Settling High Current Operational Amplifier ........................... Linear 1
LM10 Op Amp and Voltage Reference ................................•................... Linear 1
LM11 Operational Amplifiers .......•.......................•......•..................... Linear 1
LM12(L) 150W Operational Amplifier ..................................................... Linear 1
LM34 Precision Fahrenheit Temperature Sensors ................... ; .......................... 6-4
LM34A Precision Fahrenheit Temperature Sensors ............................................ 6-4
LM34C Precision FahrenheitTemperature Sensors ............... , ............................ 6-4
LM34CA Precision FahrenheitTemperature Sensors ................................•........ .-.. 6-4
LM34D Precision Fahrenheit Temperature Sensors ............................................ 6-4
LM35 Precision Fahrenheit Temperature Sensors ............................................. 6-12
LM35A Precision FahrenheitTemperature Sensors ........................................... 6-12
LM35C Precision FahrenheitTemperature Sensors ..................................•........ 6-12
LM35CA Precision FahrenheitTemperature Sensors .......................................... 6-12
LM35D Precision FahrenheitTemperature Sensors ...............................•........... 6-12
LM78LXX Series 3-Terminal Positive Regulator .........................•.................. Linear 1
4
Alpha-Numeric Index (Continued)
LM78XX Series Voltage Regulator ....................................................... Linear 1
LM79LXXAC Series 3-Terminal Negative Regulator ........................................ Linear 1
LM79XX Series 3-Terminal Negative Regulator ............................................ Linear 1
LM101A Operational Amplifiers .......................................................... Linear 1
LM102 Voltage Follower ................................................................ Linear 1
LM 103 Reference Diode .................................................................. 7-11
LM104 Negative Regulator .............................................................. Linear 1
LM105 Voltage Regulator ............................................................... Linear 1
LM106 Voltage Comparator .....................•....................................... Linear 1
LM 107 Operational Amplifiers ........................................................... Linear 1
LM 108 Operational Amplifiers ........................................................... Linear 1
LM 108A Operational Amplifiers ..................•....................................... Linear 1
LM109 5-Volt Regulator ....................•........................................... Linear 1
LM110 Voltage Follower ....................•........................................... Linear 1
LM111 Voltage Comparator ............................................................. Linear 1
LM 112 Operational Amplifiers ...............•........................................... Linear 1
LM 113 Precision Reference ............................................................... 7-12
LM117 3-Terminal Adjustable Regulator .................................................. Linear 1
LM117HV 3-Terminal Adjustable Regulator ........................................•....... Linear 1
LM118 Operational Amplifiers ..................................•........................ Linear 1
LM 119 High Speed Dual Comparator ..................................................... Linear 1
LM120 Series 3-Terminal Negative Regulator .............................................. Linear 1
LM122 Precision Timer •................................................................ Linear 3
LM123 3 Amp, 5-Volt Positive Regulator .....•....•....................................... Linear 1
LM 124 Low Power Quad Operational Amplifiers ............................................ Linear 1
LM125 Voltage Regulators .............................................................. Linear 1
LM126 Voltage Regulators .............•........•....................................... Linear 1
LM129 Precision Reference ............................................................... 7-15
LM131 Precision Voltage-to-Frequency Converters .......................................... 3-285
LM131A Precision Voltage-to-Frequency Converters ..............................•.......... 3-285
LM133 3-Amp Negative Adjustable Voltage Regulator ...................................... Linear 1
LM134 3-Terminal Adjustable Current Sources ............................................... 7-20
LM135 Precision Temperature Sensors ................................•..................... 6-21
LM135A Precision Temperature Sensors .................................................... 6-21
LM136-2.5V Reference Diode .............................................................. 7-28
LM136-5.0V Reference Diode .............................................................. 7-35
LM 137 3-Terminal Negative Adjustable Regulator .......................................... Linear 1
LM137HV 3-Terminal Negative Adjustable Regulators (High Voltage) ......................... Linear 1
LM138 5 Amp Adjustable Power Regulator ................................................ Linear 1
LM139 Low Power Low Offset Voltage Quad Comparators .................................. Linear 1
LM140 Series 3-Terminal Positive Regulators .............................................. Linear 1
LM140L Series 3-Terminal Positive Regulators ............................................ Linear 1
LM143 High Voltage Operational Amplifier ................................................ Linear 1
LM144 High Voltage, High Slew Rate Operational Amplifiers ................................. Linear 1
LM 145 Negative 3 Amp Regulator ....................................................... Linear 1
LM146 Programmable Quad Operational Amplifiers ........................................ Linear 1
LM148 Quad 741 Op Amps ................................................•............ Linear 1
LM149 Wide Band Decompensated (AV(MIN) = 5) ........................................ Linear 1
LM150 3 Amp Adjustable Power Regulator ................................................ Linear 1
LM158 Low Power Dual Operational Amplifiers ............................................ Linear 1
LM160 High Speed Differential Comparator .......•....................................... Linear 1
5
Alpha-Numeric Index(continued)
LM161 High Speed Differential Comparator .•...••...••..•••.•••...••..•.••.•..•..••...••. linear 1
LM168 Precision Voltage Reference ...•••..•..............••...........•................... 7-42
LM169 Precision Voltage Reference ................•...••.......••..•......•............... 7-48
LM185 Adjustable Micropower Voltage References ..•....•..............••.•.•....•.......... 7-69
LM185-1.2 MicropowerVoltageReference Diode ............................................. 7-58
LM185-2.5 MicropowerVoltage Reference Diode .....•.........•..•••...•...•.•..•..........• 7-64
LM192 Low Power Operational AmplifierlVoltage Comparator ..........•...................• linear 1
LM193 Low Power Low Offset Voltage Dual Comparator •...••...•....••..•••..•.•.......•.. linear 1
LM194 Super Match Pair ...•...•......••....•......•.•....••...•........................ linear 3
LM195 Ultra Reliable Power Transistors ..•...••..•.....•..........•....•.•............... linear 3
LM196 10 Amp Adjustable Voltage Regulator ........................................•....• linear 1
LM199 Precision Reference •.....................•......•..•.•..................•......... 7-76
LM201 A Operational Amplifiers ..•..•...••..•....•....•....•....•....••..•.••.......•.•.. linear 1
LM204 Negative Regulator ..........................•................................... linear 1
LM205 Voltage Regulator .....•...•..................................•..••...••....•.•.. linear 1
LM206 Voltage Comparator ............•............•..••................•.............. linear 1
LM207 Operational Amplifiers ...•...•......•.•............•...•.•.•.•..••.••••...•....•. linear 1
LM208 Operational Amplifiers ..........•.......•....•.............................•..... linear 1
LM208A Operational Amplifiers .........•.•....................•..•••...••...•........... linear 1
LM210 Voltage Follower .....................•........•.•••..••........••...•....•...... linear 1
LM211 Voltage Comparator ..........................................••.••...•...•...... linear 1
LM212 Operational Amplifiers ............................•....•......................... linear 1
LM218 Operational Amplifiers ......•..........................•....•.••.•...•....•...•.. linear 1
LM219 High Speed Dual Comparator ..........................................•.•..•..... linear 1
LM221 Precision Preamplifiers ...............•............•....•......................... linear 1
LM224 Low Power Quad Operational Amplifiers ........•................................... linear 1
LM231 Precision Voltage-to-Frequency Converters .....•...............•.......•...•........ 3-285
LM231 A Precision Voltage-to-Frequency Converters ......................................... 3-285
LM234 3-Terminal Adjustable Current Sources .....••.......•.................•...... , ..•.... 7-20
LM235 Precision Temperature Sensors ..........•......•.................................... 6-21
LM235A Precision Temperature Sensors ..................................•................. 6-21
LM236-2.5V Reference Diode ..........................................•...............•... 7-28
LM236-5.0V Reference Diode ................................... ; .............•....•....... 7-35
LM239 Low Power Low Offset Voltage Quad Comparators ...•..•...••....•....••........... linear 1
LM246 Programmable Quad Operational Amplifiers ....•.............................•..... linear 1
LM248 Quad 741 Op Amps ...............................••...•.•...................... linear 1
LM249 Wide Band Decompensated (AV(MIN) = 5) .•...•.....•.•...•.....•................ linear 1
LM258 Low Power Dual Operational Amplifiers ............................•....•.....•...• linear 1
LM260 High Speed Differential Comparator .................•••.........•................. linear 1
LM261 High Speed Differential Comparator ...•.....•.....•.........•..................... linear 1
LM268 Precision Voltage Reference ......................................••.........•...... 7-42
LM285 Adjustable Micropower Voltage References ..•......•......•........•................. 7-69
LM285-1.2 Micropower Voltage Reference Diode ....•...••....•..•..••....•...••....•....•... 7-58
LM285-2.5 Micropower Voltage Reference Diode •........••.................................. 7-64
LM292 Low Power Operational AmplifierlVoltage Comparator .•....•...•.•.....•.....•.• " .. linear 1
LM293 Low Power Low Offset Voltage Dual Comparator ..•.•..•............................ linear 1
LM295 Ultra Reliable Power Transistors ..............•..•...•••.........•....•........... linear 3
LM299 Precision Reference ....•...•.....•....•...•.....................•................. 7-76
LM301 A Operational Amplifiers ...........................•.......-.....••.•••.........•.. linear 1
LM302 Voltage Follower .....•........••..•....•••.....••............................... linear 1
LM304 Negative Regulator ......•........••....•...........................•..•......... linear 1
6
Alpha-Numeric
Index(continued)
LM305 Voltage Regulator ............................................................... Linear 1
LM305A Voltage Regulator ............................................................. Linear 1
LM306 Voltage Comparator ............................................................. Linear 1
LM307 Operational Amplifiers ........................................................... Linear 1
LM308 Operational Amplifiers ........................................................... Linear 1
LM308A Operational Amplifiers .......................................................... Linear 1
LM309 5-Volt Regulator ...............................................•................ Linear 1
LM310 Voltage Follower .........................................................•...... Linear 1
LM311 Voltage Comparator ............................................................. Linear 1
LM312 Operational Amplifiers ........................................................... Linear 1
LM313 Precision Reference ............................................................... 7-12
LM317 3-Terminal Adjustable Regulator .......................................•.......... Linear 1
LM317HV 3-Terminal Adjustable Regulator ................................................ Linear 1
LM317L 3-Terminal Adjustable Regulator ................................................. Linear 1
LM318 Operational Amplifiers ........................................................... Linear 1
LM319 High Speed Dual Comparator ..................................................... Linear 1
LM320 Series 3-Terminal Negative Regulator .............................................. Linear 1
LM320L 3-Terminal Negative Regulator ................................................... Linear 1
LM321 Precision Preamplifiers ........................................................... Linear 1
LM322 Precision Timer ................................................................. Linear 3
LM324 Low Power Quad Operational Amplifiers ............................................ Linear 1
LM325 Voltage Regulators .............................................................. Linear 1
LM326 Voltage Regulators .......................................................•...... Linear 1
LM329 Precision Reference .......................•....................................... 7-15
LM330 3-Terminal Positive Regulator .......................................... '" .•...... Linear 1
LM331 Precision Voltage-to-Frequency Converters .......................................... 3-285
LM331A Precision Voltage-to-Frequency Converters ......................................... 3-285
LM333 3-Amp Negative Adjustable Voltage Regulator ...................................... Linear 1
LM334 3-Terminal Adjustable Current Sources ............................................... 7-20
LM335 Precision Temperature Sensors ...................................................... 6-21
LM335A Precision Temperature Sensors ....................................•............... 6-21
LM336-2.5V Reference Diode .............................................................. 7-28
LM336-5.0V Reference Diode ........................................................•..... 7-35
LM337 3-Terminal Negative Adjustable Regulator .......................................... Linear 1
LM337HV 3-Terminal Negative Adjustable Regulators (High Voltage) .................•....... Linear 1
LM337L 3-Terminal Adjustable Regulator .........................................•....... Linear 1
LM338 5 Amp Adjustable Power Regulator ................................................ Linear 1
LM339 Low Power Low Offset Voltage Quad Comparators .......•.......................... Linear 1
LM340 Series 3-Terminal Positive Regulators ...................................•.......... Linear 1
LM340L Series 3-Terminal Positive Regulators ....................•..... , ................. Linear 1
LM343 High Voltage Operational Amplifier ................................................ Linear 1
LM344 High Voltage, High Slew Rate Operational Amplifiers ................................. Linear 1
LM345 Negative 3 Amp Regulator ................................•...................... Unear 1
LM346 Programmable Quad Operational Amplifiers ........................................ Linear 1
LM348 Quad 741 Op Amps ................... , ......................................... Linear 1
LM349 Wide Band Decompensated (AV(MIN) = 5) ........................................ Linear 1
LM350 3 Amp Adjustable Power Regulator ................................................ Linear 1
LM358 Low Power Dual Operational Amplifiers ............................................ Linear 1
LM359 Dual, High Speed, Programmable Current Mode (Norton) Amplifier .................... Linear 1
LM360 High Speed Differential Comparator ............................................... Linear 1
LM361 High Speed Differential Comparator .......•....................................... Linear 1
7
Alpha-Numeric
Index(continUed)
LM363 Precision Instrumentation Amplifier .•.....•.........•................•............. Linear 1
LM368 Precision Voltage Reference •......•........•.....•..•..•.••••..•..•.•••••..•.•.•..• 7-42
LM368-2.5 Precision Voltage Reference ...•..•..........•..........•.........•.............. 7-85
LM369 Precision Voltage Reference •.•....•.......•.•..•.....•....•.................•...... 7-48
LM376 Voltage Regulator .........•....•..•.....•..•....••....•.••..•.•.•••..•.•..•••..• Linear 1
LM377 Dual 2-Watt Audio Amplifier •.•..•.•.••.••.•.....•..•........•.................... Linear 3
LM378 Dual 4-Watt Audio Amplifier •.............•..•....•.•...•..•••••••..•.••....•..•.. Linear 3
LM380 Audio Power Amplifier .•.•..•...........•........................................ Linear 3
LM381 Low Noise Dual Preamplifier •..••••....•.••....•..•..•........••••..•.•........ ; .• Linear 3
LM382 Low Noise Dual Preamplifier •.........................•.........................•. Linear 3
LM383 7-Watt Audio Power Amplifier ...•..........•..•..•..•........•.................... Linear 3
LM384 5-Watt Audio Power Amplifier .•..••....•.••.•..•...•.••.••••.•.•.••••.....•.•..••• Linear 3
LM385 Adjustable MicropowerVoltage References ..................................•........ 7-69
LM385-1.2 MicropowerVoltage Reference Diode ••••.•.•.........•.••..••••..•.••.•..•.••.... 7-58
LM385-2.5 MicropowerVoltage Reference Diode •..•......................•.•................ 7-64
LM386 Low Voltage Audio Power Amplifier ....•.•..•................•.....•..•..••.•..•... Linear 3
LM387 Low Noise Dual Preamplifier ..•..•..•..•..•..•..•..•..•.....•..•...•...........••. Linear 3
LM388 1.5-Watt Audio Power Amplifier ...................................•............... Linear 3
LM389 Low Voltage Audio Power Amplifier with NPN Transistor Array .....•.•.••............. Linear 3
LM390 1-Watt Battery Operated Audio Power Amplifier ........•...•.••....•..•............. Linear 3
LM391 Audio Power Driver ...................•..........................•............... Linear 3
LM392 Low Power Operational Amplifier/Voltage Comparator .......•....•....•.•.••.....•.. Linear 1
LM393 Low Power Low Offset Voltage Dual Comparator .....•...•....•...•............•.... Linear 1
LM394 Super Match Pair ..•.....•...•...•..•..•.....•..•.....•.....•...••••.•....•..•... Linear 3
LM395 Ultra Reliable Power Transistors ..•....•....................•..................... Linear 3
LM396 10 Amp Adjustable Voltage Regulator ........................•..................... Linear 1
LM399 Precision Reference .......•.....•.......•......•..•.............•..•.•.•..... : .... 7-76
LM555 Timer ...•...............•..•...•.......•..•..•..•...........•........•......... Linear 3
LM555C Timer ........•..........•.................•...............•.................. Linear 3
LM556 Dual Timer ....•....•......•....•......•.....•..••.•..•...•.•................•.. Linear 3
LM556C Dual Timer .......••••.......•.•...•........••..•.....•....•..•................ Linear 3
LM565 Phase Locked Loop .......•....••.............•................................. Linear 3
LM565C Phase Locked Loop ..........................••..•.....•...........•........... Linear 3
LM566C Voltage Controlled Oscillator ...•...........................•.................... Linear 3
LM567 Low Power Tone Decoder ..•..•...............................•.................• Linear 3
LM567C Low Power Tone Decoder ......•.....•..•...•......•........................... Linear 3
LM581 Voltage Reference Precision 10-Volt .....•.••.•.•.•...•..•.•......•..••.............. 7-91
LM592 Differential Video Amplifier .........•.........................................•... Linear 3
LM6044 Channel MUX-Amp ...........................•..•..........•.......•.•..•..•.. Linear 1
LM607 Precision Operational Amplifier ...•.............•................................. Linear 1
LM611 Adjustable Micropower Floating Voltage Reference and Single-Supply Operational
Amplifier ........................••.....................................•............ Linear 1
LM614 Adjustable Micropower Floating Voltage Reference and Four Single-Supply Operational
Amplifiers .•..•......................•....•.•.........•.....•..............••....•... Linear 1
LM621 Brushless Motor Commutator TC ...•...........................•.....•........•... Linear 3
LM622 Pulse Width Modulator ........•..................•............................... Linear 3
LM628 Precision Motion Controller .....•........•.....•...........•.•........•........... Linear 3
LM675 Power Operational Amplifier ...•.....................................•............ Linear 1
LM723 Voltage Regulator ........................•.............•..•.........••.......... Linear 1
LM733 Differential Video Amplifier •.•..•..................•..•........................... Linear 3
LM733C Differential Video Amplifier .........................................•.....•...... Linear 3
8
Alpha-Numeric
Index(continued)
LM741 Operational Amplifier ............................................................ Linear 1
LM831 Low Voltage Audio Power Amplifier ................................................ Linear 3
LM832 Dynamic Noise Reduction System DNR ............................................ Linear 3
LM833 Dual Audio Operational Amplifier .................................................. Linear 1
LM837 Low Noise Quad Operational Amplifier ............................................. Linear 1
LM903 Fluid Level Detector ............................................................. Linear 3
LM1035 Dual DC Operated TonelVolume/Balance Circuit .................................. Linear 3
LM1036 Dual DC Operated TonelVolume/Balance Circuit .................................. Linear 3
LM1037 Dual Four-Channel Analog Switch ................................................ Linear 3
LM1038 Dual Four-Channel Analog Switch ................................................ Linear 3
LM1040 Dual DC Operated TonelVolume/Balance Circuit with Stereo Enhancement Facility .... Linear 3
LM1042 Fluid Level Detector ............................................................ Linear 3
LM1044 Analog Video Switch ........................................................... Linear 3
LM1112A Dolby B-Type Noise Reduction Processor ........................................ Linear 3
LM1131 A Dual Dolby B-Type Noise Reduction Processor ................................... Linear 3
LM1141 Dolby B-C Type Noise Reduction Processor ....................................... Linear 3
LM1201 Video Amplifier System ......................................................... Linear 3
LM1203 RGB Video Amplifier System .................................................... Linear 3
LM1211 Broadband Demodulator System ................................................. Linear 3
LM1391 Phase-Locked Loop ............................................................ Linear 3
LM 1458 Dual Operational Amplifier ...................................................... Linear 1
LM1496 Balanced Modulator Demodulator ................................................ Linear 3
LM1558 Dual Operational Amplifier ...................................................... Linear 1
LM1578 Switching Regulator ............................................................ Linear 1
LM1596 Balanced Modulator Demodulator ................................................ Linear 3
LM1800 Phase-Locked Loop FM Stereo Demodulator ...................................... Linear 3
LM1801 Battery Operated Power Comparator ............................................. Linear 3
LM1812 Ultrasonic Transceiver .......................................................... Linear 3
LM1815 Adaptive Sense Amplifier ....................................................... Linear 3
LM1818 Electronically Switched Audio Tape System ....................................... Linear 3
LM 1819 Air-Core Meter Driver ........................................................... Linear 3
LM1823 Video IF Amplifier/PLL Detection System ......................................... Linear 3
LM1830 Fluid Detector ................................................................. Linear 3
LM1837 Low Noise Preamplifier for Autoreversing Tape Playback Systems .................... Linear 3
LM1851 Ground Faultlnterrupter ........................................................ Linear 3
LM1863 AM Radio System for Electronically Tuned Radio ................................... Linear 3
LM1865 Advanced FM IF System ........................................................ Linear 3
LM 1866 Low Voltage AM/FM Receiver ................................................... Linear 3
LM 1868 AM/FM Radio System .......................................................... Linear 3
LM1870 Stereo Demodulator with Blend .................................................. Linear 3
LM1871 RC Encoder/Transmitter ........................................................ Linear 3
LM1872 Radio Control Receiver/Decoder ................................................ Linear 3
LM1875 20-Watt Power Audio Amplifier ................................................... Linear 3
LM 1877 Dual Power Audio Amplifier ...................................................... Linear 3
LM1880 No-Holds Vertical/Horizontal .................................................... Linear 3
LM 1881 Video Sync Separator .......................................................... Linear 3
LM1884 TV Stereo Decoder ............................................................. Linear 3
LM1886 TV Video Matrix D to A .......................... : ............................... Linear 3
LM1889 TV Video Modulator ............................................................ Linear 3
LM1893 Biline Carrier Current Transceiver ................................................ Linear 3
LM1894 Dynamic Noise Reduction System DNR ........................................... Linear 3
9
Alpha-Numeric Index (Continued)
LM 1895 Audio Power Amplifier ...............•....•..•...••.•••.•••••...•.•..•.......... Linear 3
LM 1896 Dual Power Audio Amplifier ...•...............•.••..•.•.••.•..•.•.••............. Linear 3
LM1897 Low Noise Preamplifier for Tape Playback Systems .•..•...........•.......•........ Linear 3
LM19211 Amp Industrial Switch ....•.................................................... Linear 3
LM1946 Over/Under Current Limit Diagnostic Circuits .......•..... : .•.••..•..••...••....•.. Linear 3
LM1949 Injector Drive Controller .........•...............•••..•.......••......•.......... Linear 3
LM 1951 Solid State 1 Amp Switch ......................•.....•..•.•.......•............. Linear 3
LM1964 Sensor Interface Amplifier ..•...................•.•.•.•..•.••.••.•.•.•...••..•... Linear 3
LM1965 Advanced FM IF System ..........•............................•................ Linear 3
LM2002 8-Watt Audio Power Amplifier ............•....................•.................. Linear 3
LM2005 20-Watt Automotive Power Amplifier ........•....•.....•............•.....•....... Linear 3
LM2065 Advanced FM IF System ................•...........•....•.....•...•............ Linear 3
LM2578 Switching Regulator ..........•..............•..•....••.....••.......•.......... Linear 1
LM2877 Dual4-Watt Power Audio Amplifier .•.....•.......•...................•....•..•.•. Linear 3
LM2878 Dual 5-Watt Power Audio Amplifier •.......................•...................... Linear 3
LM2879 Dual 8-Watt Audio Amplifier ...•.......................•..•...................... Linear 3
LM2889 TV Video Modulator ........•...........•.......•...•.•..•......•............... Linear 3
LM2893 Biline Carrier Current Transceiver .•...........•........•..•....•....•............ Linear 3
LM2900 Quad Amplifiers .................•....................•..•...................... Linear 1
LM2901 Low Power Low Offset Voltage Quad Comparators .....•.•..•.........•............ Linear 1
LM2902 Low Power Quad Operational Amplifiers .......•............................•..•.. Linear 1
LM2903 Low Power Low Offset Voltage Dual Comparator ........•...•.•..........•...•..••. Linear 1
LM2904 Low Power Dual Operational Amplifiers •............•.......................•..... Linear 1
LM2905 Precision Timer ..............••...•...................•.•.•....•...•........... Linear 3
LM2907 Frequency to Voltage Converter .....................•.....................•..... Linear 3
LM2917 Frequency to Voltage Converter ...................•.............•.........•..... Linear 3
LM2924 Low Power Operational AmplifierlVoltage Comparator .......•.....•................ Linear 1
LM2925 Low Drop-Out Regulator with Delayed Reset ......•...•........................... Linear 1
LM2930 3-Terminal Positive Regulator ..••.............•..•..............................• Linear 1
LM2931 Series Low Drop-Out Regulator ....•......•.........•.•...••.......•.....•....... Linear 1
LM2935 Low Drop-Out Dual Regulator ..•...•.....•...•............•.........•....••...... Linear 1
LM2940C 1A Low Drop-Out Regulator ........•...•.............•......................... Linear 1
LM2984C Microprocessor Power Supply System ......•......••.•..•••..............•...... Linear 1
LM3045 Transistor Arrays .......................••..•........•...•...........•....•..... Linear 3
LM3046 Transistor Arrays .•.....•..•..•...•....•••...••••....•..•....•.•.•.............. Linear 3
LM3080 Operational Transconductance Amplifier .......................................... Linear 1
LM3080A Operational Transconductance Amplifier ........................•................ Linear 1
LM3086 Transistor Arrays .............•........•.....••......•...•...................... Linear 3
LM3089 FM Receiver IF System ............•........•....•.•......•..................... Linear 3
LM3146 High Voltage Transistor Array .......•..•......................................... Linear 3
LM3189 FM IF System ..........•.•..•........•.•....•......•.•.•.....•................ Linear 3
LM3301 Quad Amplifiers .........•.....••...........•.•..••..•.•....•................... Linear 1
LM3302 Low Power Low Offset Voltage Quad Comparators ......•.......................... Linear 1
LM3361 A Low Voltage/Power Narrow Band FM IF System ......••..••.•••............••... Linear 3
LM3401 Quad Amplifiers .....................•......•.....•••..........•..........•..... Linear 1
LM3578 Switching Regulator ........................................•................... Linear 1
LM3820 AM Radio System ..•......•...•...............................•................ Linear 3
LM3900 Quad Amplifiers •.••.....•......•..•...•••...•••.....••••...••.•....•.......•... Linear 1
LM3905 Precision Timer ...........................•.....•..•.....•..................... Linear 3
LM3909 LED Flasher/Oscillator •...........•.............•...•....•.••......•......•.... Linear 3
LM3911 Temperature Controller .•...• " ...•.••...•.••.•••.••••..••.•......••......•...•.... 6-30
10
Alpha-Numeric
Index(continUed)
LM3914 Dot/Bar Display Driver ........................•................................. Linear 3
LM3915 Dot/Bar Display Driver .......................................................... Linear 3
LM3916 Dot/Bar Display Driver .......................................................... Linear 3
LM3999 Precision Reference .............................................................. 7-76
LM4250 Programmable Operational Amplifiers ............................................. Linear 1
LM4500A High Fidelity FM Stereo Demodulator with Blend .................................. Linear 3
LM6113 High Speed Operational Amplifiers Plus Power Buffer ............................... Linear 1
LM6121 High Speed Buffer ............................................................. Linear 1
LM6125 High Speed Buffer ............................................................. Linear 1
LM6161 High Speed Operational Amplifiers ............................................... Linear 1
LM6161 ILM6261 ILM6361 High Speed Operational Amplifiers ................. : ............. Linear 1
LM6164 High Speed Operational Amplifiers ............................................... Linear 1
LM6164/LM6264/LM6364 HIgh Speed Operational Amplifiers ............................... Linear 1
LM6165 High Speed Operational Amplifiers ............................................... Linear 1
LM6165/LM6265/LM6365 High Speed Operational Amplifiers ............................... Linear 1
LM6214 High Speed Operational Amplifiers Plus Power Buffer ............................... Linear 1
LM6221 High Speed Buffer ............................................................. Linear 1
LM6225 High Speed Buffer .•........................................................... Linear 1
LM6261 High Speed Operational Amplifiers ............................................... Linear 1
LM6264 High Speed Operational Amplifiers ............................................... Linear 1
LM6265 High Speed Operational Amplifiers .................•............................. Linear 1
LM6314 High Speed Operational Amplifiers Plus Power Buffer ............................... Linear 1
LM6321 High Speed Buffer ............................................................. Linear 1
LM6325 High Speed Buffer ............................................................. Linear 1
LM6361 High Speed Operational Amplifiers ............................................... Linear 1
LM6364 High Speed Operational Amplifiers ....•.......................................... Linear 1
LM6365 High Speed Operational Amplifiers ............................................... Linear 1
LM 13080 Programmable Power Operational Amplifiers ....................••............... Linear 1
LM13600 Dual Operational Transconductance Amplifiers with Linearizing Diodes and Buffers .... Linear 1
LM 13700 Dual Operational Transconductance Amplifier with Linearizing Diodes and Buffers ..... Linear 1
LM 18272 Dual Power Operational Amplifier ....................•.......................... Linear 1
LM18293 Four Channel Push Pull Driver .......•.......................................... Linear 3
LM18298 Dual Full-Bridge Driver ......................................................... Linear 3
LMC555 CMOS Timer .................................................................. Linear 3
LMC567 Low Power Tone Decoder ...........•.......................................... Linear 3
LMC568 Low Power Phase-Locked Loop ................................................. Linear 3
LMC660 CMOS Quad Operational Amplifier ............................................... Linear 1
LMC668 Chopper Stabilized Operational Amplifier .......................................... Linear 1
LMC669 Auto Zero ..................................................................... Linear 1
LMC835 Digital Controlled Graphic Equalizer .............................................. Linear 3
LMC1992 Computer Controlled Tone and Volume Circuits ................................... Linear 3
LMC1993 Computer Controlled Tone and Volume Circuits ................................... Linear 3
LMC7660 Switched Capacitor Voltage Converter .............................•............. Linear 1
LMC7669 Switched Capacitor Voltage Converter ........................................... Linear 1
LMF60 6th Order LMCMOSTM Switched Capacitor Butterworth Lowpass Filter ..................... 1-8
LMF90 4th-Order LMCMOSTM Programmable Elliptic Notch Filter ................................ 1-9
LMF100 Universal Monolithic Dual Switched Capacitor Filter ................................... 1-10
LMF120 Mask Programmable Switched Capacitor Filter ..•.................................... 1-12
LP124 Micropower Quad Operational Amplifier ............................................ Linear 1
LP165 Micropower Programmable Quad Comparator ....................................... Linear 1
LP311 Voltage Comparator ...................•.............................•........... Linear 1
11
Alpha-Numeric I ndex (Continued)
LP324 Micropower Quad Operational Amplifier ...................................... ; ..... Linear 1
LP339 Ultra-Low Power Quad Comparator .........................•...................... Linear 1
LP365 Micropower Programmable Quad Comparator ....................................... Linear 1
LP2902 Micropower Quad Operational Amplifier ........................................... Linear 1
LP2950 5V Adjustable Micropower Voltage Regulator ...............•...................... Linear 1
LP2951 Adjustable Micropower Voltage Regulator ......................................... Linear 1
MF4 4th Order Switched Capacitor Butterworth Lowpass Filter ................................. 1-13
MF5 Universal Monolithic Switched Capacitor Filter ........................................... 1-26
MF6 6th Order Switched Capacitor Butterworth Lowpass Filter ..... . . . . . . . . . . . . . . . . . . . • . . . . . . . . 1-41
MF8 4th Order Switched Capacitor Bandpass Filter .................•......................... 1-59
MF10 Universal Monolithic Dual Switched Capacitor Filter ........•................ , ........... 1-81
MM54HC4016 Quad Analog Switch ......................................................... 2-77
MM54HC4051 8-Channel Analog Multiplexer .............. , ................... , .............. 2-84
MM54HC4052 Dual 4-Channel Analog Multiplexer .........................................•.. 2-84
MM54HC4053 Triple 2-Channel Analog Multiplexer ..•........................................ 2-84
MM54HC4066 Quad Analog Switch .......................................................•. 2-91
MM54HC4316 Quad Analog Switch with Level Translator ...................•.................. 2-96
M M7 4C905 12-Bit Successive Approximation Register ....................................... 3-296
MM74HC4016 Quad Analog Switch ......................................................... 2-77
MM74HC4051 8-Channel Analog Multiplexer ................................................. 2-84
MM74HC4052 Dual4-Channel Analog Multiplexer .........................•.................. 2-84
MM74HC4053 Triple 2-Channel Analog Multiplexer ........................................... 2-84
MM74HC4066 Quad Analog Switch ......................................•.................. 2-91
M M7 4HC4316 Quad Analog Switch with Level Translator ...................................... 2-96
TBA 120S IF Amplifier and Detector ....•........................•.......•.........•...... Linear 3
TL081 CP Wide Bandwidth J FET Input Operational Amplifier ........•........................ Linear 1
TL082CP Wide Bandwidth Dual JFET Input Operational Amplifier ......•..•...............•.. Linear 1
12
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CROSS REFERENCE BY PART NUMBER
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A complete interchangeability list of Linear IC's offered by most Integrated Circuit
Manufacturers are listed in this section and reference the nearest National Semiconductor Corp. direct replacement or recommended replacement with either an
improved or functional replacement. The following notations are appended to assist you in finding the best option.
Z
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No reference note ...... "DIRECT REPLACEMENT"
Note (1) ............... "IMPROVED REPLACEMENT" Pinfor-Pin replacement with "SUPERIOR" Electrical Specifications.
Note (2) ............... "FUNCTIONAL
REPLACEMENT"
Similar device. Consult datasheet to
determine the suitability for specific
application.
Note (3) ............... "SIMILAR DEVICE" with superior
performance. Consult datasheet to
determine suitability of the replacement for specific application.
ANALOG
DEVICES
ADOP07
ADDAC-08
ADDAC-08
ADDAC-08
ADDAC80
ADDAC85
AD101A
AD201A
AD301A
AD506
AD509
AD521
AD521
AD524
AD537
AD562
AD563
AD565A
AD566A
AD567
AD573
AD573
AD581
AD581
AD582
AD583
AD588
AD589M
AD589U
AD590
AD590
AD590
AD590
AD611K
AD611J
AD614
NATIONAL
LM607
DAC0800
DAC0801
DAC0802
DAC1280+
DAC1280+
LM101A
LM201A
LM301A
LH0022
LHOO03
LM363
LH0036
LH0038
LM331
DAC1266
DAC1265
DAC1265
DAC1266
DAC1230
ADC1005
ADC1025
LM581
LH0070
LF398
LF198
LM369
LM385
LM185
LM135
LM34
LM134
LM35
LF411AC
LF411C
LH0086
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
(3)
(2)
(2)
(2)
(1)
(2)
(3)
(2)
(1)
(1)
(2)
(3)
(2)
(3)
(1)
(1)
(2)
AD624
AD650
AD651
AD654
AD673
AD741
ADLH0032
ADLH0033
AD0042
AD3542
AD5035
AD7502
AD7516
AD7523
AD7523
AD7523
AD7524
AD7524
AD7524
AD7533
AD7533
AD7533
AD7541A
AD7541A
AD7541
AD7541
AD7542
AD7542
AD7542
AD7545
AD7545
AD7545
AD7548
AD7548
AD7548
AD7552
AD7552
AD7571
LH0038
LM331
LM331
LM331
ADC0841
LM741
LH0032
LH0033
LH0042
LH0042
LH0042
LF13509
C04066B
DAC0832
DAC0831
DAC0830
DAC0830
DAC0831
DAC0832
DAC1020
DAC1022
DAC1021
DAC1218
DAC1219
DAC1219
DAC1218
DAC1210
DAC1209
DAC1208
DAC1209
DAC1210
DAC1208
DAC1230
DAC1232
DAC1231
ADC1225
ADC1205
ADC1005
13
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
(3)
(3)
(2)
(2)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
AD7571
AD7575
AD7576
AD7578
AD7578
AD7820
ADC1025
ADC0820
ADC0820
ADC1225
ADC1205
ADC0820
APEX
PA01
PA01
PA07
PA10
PA10
PA11
PA51
PA73
NATIONAL
LM12
LH0101
LM12
LM12
LH0101
LM12
LM12
LM12
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
BURR-BROWN
SHC80
SHC85
HOS-100
INA102
SHC298A
3507
3533
3542
3550
3551
3553
3554
3571
3572
3573
3606A6
3606A6
3626
3629
NATIONAL
LF398
LF398
LH0033
LH0038
LF398A
LM6361
LH0033
LH0042
LM6361
LM6361
LH0063
LH0032
LM675
LH0021
LM675
LH0084
LH0086
LH0036
LH0038
(2)
(2)
(2)
(2)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
..
-..
CI)
.CI
E
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Z
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D.
>-
.CI
CI)
..
..
u
cCI)
CI)
CI)
a:
II)
II)
0
0
CTS
CTSOOO2
CTSOOO4
CTSOO21
CTSOO24
CTSOO32
CTSOO33
CTSOO41
CTSOO42
CTS2101A
CTS2111
NATIONAL
LHOOO2
LHOOO4
LHOO21
LHOO24
LHOO32
LHOO33
LHOO41
LHOO42
LH2101A
LH2111
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
ELANTEC
ELHOOO2
ELHOO21
ELHOO32
ELHOO33
ELHOO41
ELH0101
EL2006C
EL2006
EHA2500
EHA2502
EHA2505
EHA2510
EHA2512
EHA2515
EHA2520
EHA2522
EHA2525
EHA2600
EHA2602
EHA2605
EHA2620
EHA2622
EHA2625
NATIONAL
LHOOO2
LHOO21
LHOO32
LHOO33
LHOO41
LH0101
LM6261
LM6161
LM6161
LM6161
LM6361
LM6161
LM6161
LM6361
LM6164
LM6164
LM6364
LM6161
LM6161
LM6361
LM6164
LM6164
LM6364
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
EXAR
XR084M
XR084
XR146
XR246
XR346
XR-1001
XR-1002
XR1458
NATIONAL
LF147
LF347
LM146
LM246
LM346
MF4C-100
MF4C-50
LM1458
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
FAIRCHILD
",A78XXKM
",78LXXACH
",78XXUC
",78XXUC
",A78LXXACLP
",A78LXXAWC
",78MXXCKC
",78MXXCKC
",A78MXXUC
",A78MXXCKC
",A78XXKC
",A79XXUC
",A79XXUC
",A79XXCKC
",A79XXCKC
",A79XXUC
",A79XXUC
",A79XXCKC
",A79XXCKC
",A79MXXAUC
",A79XXKM
NATIONAL
LM140K-XX
LM78LXXACH
LM340T-XX
LM78XXCT
LM78LXXACZ
LM78LXXACZ
LM78XXCK
LM78MXXCT
LM341P-XX
LM78XXCT
LM340K-XX
LM79LXXACZ
LM79MXXCP
LM79XXCT
LM79MXXCP
LM79MXXCH
LM320T-XX
LM79MXXCH
LM79LXXACZ
LM320MP-XX
LM120K-XX
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
",A79XXKC
",A79XXUC
",A101A
",A102
",A105HM
",A107
",A108A
",A108
",A109KM
",A110
",A111
",A124
",A139
",A139A
",A201A
",A207
",A208
",A208A
",A211
",A224
",A239
",A239A
",A248
",A249
",A301A
",A302
",A304HC
",A305HC
",A305AHC
",A307
",A308A
",A308
",A309KC
",A31 0
",A311
",A317KC
",A317UC
",A318
",A324
",A339
",A339A
",A348
",A349
",A376TC
",A555TC
",A556PC
",A709
",A709
",A71 0
",A71 0
",A711
",A714
",A723HM
",A723HC
",A723DC
",A723MJ
",A723CJ
",A723DM
",A723PC
",A723CN
",A725
",A725
",A733CN
",A733
",A741
",A741
",A747
",A747
",A748
LM320K-XX
LM79XXCT
LM101A
LM102
LM105H
LM107
LM108A
LM108
LM109K STEEL
LM110
LM111
LM124
LM139
LM139A
LM201A
LM207
LM208
LM208A
LM211
LM224
LM239
LM239A
LM248
LM249
LM301A
LM302
LM304H
LM305H
LM305AH
LM307
LM308A
LM308
LM309K STEEL
LM310
LM311
LM317K STEEL
LM317T
LM318
LM324
LM339
LM339A
LM348
LM349
LM376N
LM555CN
LM556CN
LM709
LM709
LM710
LM710
LM711
LM607
LM723H
LM723CH
LM723CJ
LM723J
LM723CJ
LM723J
LM723CN
LM723CN
LM725
LM725
LM733CN
LM733
LM741
LM741
LM747
LM747
LM748
14
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
",A748
",A760
",A771B
",A771
",A771 A
",A772B
",A772
",A772A
",A774
",A774B
",A776
",A1458
",C1496P
",C1496G
",A1558
",C1596G
TDA231 0
",A2901
",A2902
TCA3089
",A3301
",A3302
",C4558CD
",A7392
LM748
LM760
LF411
LF351
LF411
LF412A
LF353
LF412A
LF347
LF347B
LM4250
LM1458
LM1496N
LM1496H
LM1558
LM1596H
LM381
LM2901
LM2902
LM3089N
LM3301
LM3302
LM833CN
LM1014
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
HARRIS
HA-OP07
HF-10
HI-201
HI-300
LM741
HA2400
HA2404
HA2405
HA2406
HA2500
HA2502
HA2505
HA2510
HA2512
HA2515
HA2520
HA2520
HA2522
HA2522
HA2525
HA2525
HA2530
HA2535
HA2540
HA2541-5
HA2541-2
HA2542
HA2542-2
HA2542-5
HA2600
HA2602
HA2605
HA2620
HA2622
HA2625
HA2640
HA5033
HA5162
A5180
NATIONAL
LM607
MF10
LF13201
AH5020
LM741
LM604AM
LM604AM
LM604C
LM604C
LM6161
LM6161
LM6361
LM6161
LM6161
LM6361
LM6164
LHOOO3
LHOOO3
LM6164
LHOOO3
LM6364
LHOO24
LHOO24
LHOO32
LM6361
LM6161
LHOO32
LM6164
LM6164
LM6161
LM6161
LM6361
LM6164
LM6164
LM6364
LHOOO4
LHOO33
LHOO62
LHOO52
(2)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(2)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(2)
(1)
HEWLETT
PACKARD
HCTL-100
NATIONAL
LM628
(3)
(1)
HITACHI
NATIONAL
HA13421A
HA170B2
HA17082A
HA17084
HA170B4A
HA17094
HA17301
HA17324
HA17339
HA1735B
HA17393
HA1745B
HAl7741
HAl7747
HA17901
HA17902
HA17903
LM1B293
LF353
LF412
LF347
LF3478
LM2904
LM3301
LM324
LM339
LM35B
LM393
LM145B
LM741
LM747
LM2901
LM2902
LM2903
LINEAR
TECHNOLOGY
NATIONAL
REF-Ol
REF-Ol
LM129
LM134
LM185
LM199
LM234
LM329
LM334
LM3B5
LM399
AD581
AD5Bl
LT1001
LT1004C
LT1004M
LT1009M
LT1009C
LT1019C
LT1019M
LT1020
LT1021M
LT1021C
LT1029M
LT1029C
LT1031
LM16B
LM368
LM129
LM134
LM1B5
LM199
LM234
LM329
LM334
LM3B5
LM399
LM5Bl
LHOO70
LM607A
LM3B5
LM1B5
LM136-2.5
LM336-2.5
LM36B
LM16B
LP2951
LM169
LM369
LM136-5.0
LM336-5.0
LHOO70
LSI
COMPUTER
NATIONAL
LS7261
LS7263
LM621
LM621
MICRA
NATIONAL
MCOOO2
MCOOO3
MCOOO4
MCOO32
MCOO33
MCOO41
MCOO63
LHOOO2
LHOOO3
LHOOO4
LHOO32
LHOO33
LHOO41
LHOO63
(3)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(3)
(1)
(1)
(3)
(3)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
MICRO POWER
NATIONAL
SYSTEMS
MPOP07
MP108
MP108A
MP155A
MP155
MP156
LM607
LM108
LM10BA
LF155A
LF155
LF156
(1)
(1)
(1)
(1)
(1)
(1)
MP156A
MP157
MP157A
MP20BA
MP20B
MP30B
MP30BA
MP355A
MP356A
MP357A
MP210BA
MP5010H
MP5010L
MP5010G
MP5010H
MP5010L
MP5010G
LF156A
LF157
LF157A
LM208A
LM20B
LM30B
LM30BA
LF355A
LF356A
LF357A
LH210BA
LM3B5
LM3B5
LM1B5
LM1B5
LM185
LM3B5
MOTOROLA
NATIONAL
DAC-OB
DAC-OB
DAC-OB
MC7BXXACT
MC7BXXCK
MC7BLXXACP
MC7BMXXCT
MC7BMXXCT
MC78LXXACG
LM7BXXCT
MC78MXXCT
MC78XXCT
MC7BLXXCP
MX7BMXXCT
MC78LXXCG
MC79XXCK
MC79MXXCKC
MC79XXCK
MC79XXCKC
LM79XXCP
MC79XXCT
MC79LXXCP
MC79LXXACG
MC79LXXCLP
MC79XXCT
MC79LXXACP
MC79LXXCP
MC79XXCT
MC79XXCT
MC79XXCT
LM79XXCP
LM79XXCP
LM79XXCP
LM109K
LM109H
LMl17H
LM123K
LM137H
LM137K
LM140K
LM150K
LM285
LM309H
LM309H
LM309K
LM317H
LM317LZ
LM317T
LM317KC
LM317K
LM323K
DACOBOO
DACOB02
DACOBOl
LM340AT-XX
LM7BXXCK
LM7BLXXACZ
LM7BXXCK
LM341P-XX
LM7BLXXCH
LM7BLXXCH
LM7BMXXCT
LM7BXXCT
LM7BLXXACZ
LM342P-XX
LM7BLXXACH
LM320K-XX
LM320MP-XX
LM79XXCK
LM320T-XX
LM79XXCT
LM79MXXCH
LM320LZ-XX
LM320H-XX
LM320LZ-XX
LM79MXXCP
LM79LXXACZ
LM79LXXCZ
LM320T-XX
LM79XXCT
LM79LXXACZ
LM79LXXACZ
LM79MXXCH
LM79MXXCP
LM109K STEEL
LM109H
LMl17K STEEL
LM123K STEEL
LM137H
LM137K STEEL
LM140K-XX
LM150KSTEEL
LM285
LM309H
LM309K
LM309K STEEL
LM317H
LM317LZ
LM317T
LM317T
LM317K STEEL
LM323K STEEL
15
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
LM330-XKC
LM337H
LM337K
LM337KC
LM337T
LM340T-XX
LM340T-XX
LM340-XXKC
LM350T
LM350K
LM350KC
LM350KA
LM3B5
AD562A
AD563A
,.PC741
MC140B
MC140B
MC140B
MC1414
MC1436
MC145B
MC1496
MC150B
MC1514
MC1536
MC155B
MC1596G
MC1709
MC1709
MC1710
MC1723CL
MC1723CG
MC1723CP
MC1723CL
MC1723L
MC1723G
MC1733CG
MC1741
MC1741
MC1747
MC1747
MC174B
LM2930-XKC
MC3301
MC3302
MC3361
MC3401
MC341 0
MC3412
MC3510
MC4741
MC14442
MC14444
MC34001A
MC340018
MC34001
MC340028
MC34002
MC34002A
MC340048
MC34004
MC340048
MC34004
MC35001
MC35001A
MC350018
MC350028
MC35002
MC35002A
LM330T-XX
LM337H
LM337K STEEL
LM337T
LM337T
LM340T-XX
LM340K-XX
LM340T-XX
LM350T
LM350K STEEL
LM350T
LM350K STEEL
LM3B5
DAC1266
DAC1265
LM741
DACOB06
DACOBOB
DACOB07
LM1414
LM343
LM145B
LM1446
DACOBOB
LM1514
LM143
LM155B
LM1596CH
LM709
LM709
LM710
LM723CJ
LM723CH
LM723CN
LM723CM
LM723J
LM723H
LM723CH
LM741
LM741
LM747
LM747
LM74B
LM2930T-XX
LM3301
LM3302
LM3361AN
LM3401
DAC1020
DAC1265
DAC1020
LM34B
ADCOB29
ADC0830
LF411C
LF411C
LF351
LF412C
LF353
LF412A
LF3478
LF347
LF147
LF147
LF411M
LF411M
LF411M
LF412M
LF412M
LF412AM
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(1)
(2)
(1)
(2)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
..
n
~
(II
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CD
CD
CD
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CD
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0
0
MC145040
MC145041
PRECISIONMONOLITHIC
INC.
REF-01J
REF-Ol
AMP-Ol
DAC-02
DAC-02
REF-02
DAC-02
DAC-03
DAC-03
8UF03
DAC-03
OP05
DAC-05
DAC-05
DAC-05
SW068
SW06G
SW06F
OP07
DAC-08
DAC-08
MUX-08E
DAC-08
OP15
MUX-24E
REF-43
OP77
OP100
DAC100
DAC100
DAC100
OP105/111
PM108A
PM108
PM139A
PM139
PM155
PM155A
PM156
PM156A
PM157
PM157A
SW201G
SW2018
SW201F
SW202B
SW202F
SW202G
PM208A
PM208
OP215
PM308A
PM308
DAC312
PM339A
PM355
PM355A
PM356A
PM356
PM357A
PM357
PM420
OPA501/3573
PM725
ADC0811
ADC0811
NATIONAL
LM368-10
LM369
LHOO38
DAC1022
DAC1020
LM368-5.0
DAC1021
DAC1020
DAC1022
LHOO33
DAC1021
LM607
DAC1020
DAC1021
DAC1022
LFl1333
LF13333
LF13333
LM607
DAC0801
DAC0800
LF13508
DAC0802
LF411
LF13509
LM368-2.5
LM607
LHOO52
DAC1021
DAC1020
DAC1022
LHOO52
LM108A
LM108
LM139A
LM139
LF155
LF155A
LF156
LF156A
LF157
LF157A
LF13201
LF11201
LF13201
LFl1202
LF13202
LF13202
LM208A
LM208
LF412
LM308A
LM308
DAC1266
LM339A
LF355
LF355A
LF356A
LF356
LF357A
LF357
LF124
LH010l
LM725
(2)
(1)
(1)
(2)
(2)
(2)
(3)
(2)
(2)
(2)
(1)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(1)
PM-725
PM741
PM-741
PM-747
PM747
DAC888
DAC888
DAC888
ADC910
ADC910
DAC0812
DAC0812
DAC0812
DAC1408
DAC1408
DAC1408
PM2108A
PM7533
PM7533
PM7533
PM7541
PM7541
LM725
LM741
LM741
LM747
LM747
DAC0831
DAC0832
DAC0830
ADC1005
ADC1025
DAC1208
DAC1209
DAC1210
DAC0806
DAC0808
DAC0807
LH2108A
DAC1021
DAC1020
DAC1022
DAC1219
DAC1218
RAYTHEON
REF-Ol
REF-On
REF-02
REF-03
LP365
RC714
RC741
RC741
RC747
RC747
RC1458
RC1558
NATIONAL
LM369
LM368
LM368-5.0
LM368-2.5
LP365
LM607
LM741
LM741
LM747
LM747
LM1458
LM1558
RCAI
INTERSIL/G.E.
CA081C
CA08l A
CA08l
CA0818
CA082C
CA0828
CA082
CA082A
CA0848
CA084
CA084C
CA124
CA139
CA139A
CA158
CA158A
DG201
DG211
DG212
CA224
CA239
CA239A
CA258
CA258A
CA301A
CA307
CA311
CA324
CA339A
CA339
CA358A
NATIONAL
TL081C
LF411C
LF411M
LF411C
TL082C
LF412C
LF412M
LF412C
LF3478
LF147
LF347
LM124
LM139
LM139A
LM158
LM158A
LFl1201
LF13201
LF13202
LM224
LM239
LM239A
LM258
LM258A
LM301A
LM307
LM311
LM324
LM339A
LM339
LM358A
16
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(3)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
CA358
CA741
CA741
CA747
CA747
CA748
",A748
CA748
ADC0801
ADC0802
ADC0803
ADC0804
CA1458
CA1558
CA3105
CA3290
CA3401
IH5009
IH5010
IH5011
IH5012
IH6108
IH6208
ICL7114
ICL7114
AD7520
AD7520
AD7520
AD7521
AD7521
AD7521
AD7530
AD7530
AD7530
AD7531
AD7531
AD7531
AD7533
AD7533
AD7533
AD7541
AD7541
ICL7650
ICL8069
ICL8069
ICH8530
LM358
LM741
LM741
LM747
LM747
LM748
LM748
LM748
ADC0801
ADC0802
ADC0803
ADC0804
LM1458
LM1558
LM675
LF393
LM3401
AH5009
AH5010
AH5011
AH5012
LF13508
LF13509
ADC1205
ADC1225
DAC1021
DAC1020
DAC1022
DAC1221
DAC1220
DAC1222
DAC1020
DAC1021
DAC1022
DAC1220
DAC1221
DAC1222
DAC1020
DAC1021
DAC1022
DAC1219
DAC1218
LMC668
LM385-1.2
LM313
LH0101
SAMSUNG
LM741
NATIONAL
LM741
SGS
L78M12CV
L78M15CV
L78S12CV
L78S05CV
L78S15CV
L78M05CV
LM117K
L123CB
L272
L293
L298
LM317T
LM317K
LM748
TDA2310
LM2930A
LM2931A
TCA3089
L7805CT
NATIONAL
LM341P-12
LM341P-15
LM340T-12
LM340T-5.0
LM340T-15
LM341P-5.0
LMl17K
LM723CN
LM18272
LM18293
LM18298
LM317T
LM317K
LM748
LM381
LM2930T-5.0
LM2931AT-5.0
LM3089
LM7805CK
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(1)
(2)
(2)
(3)
(3)
(3)
(1)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
...0
(')
L7815CV
L7905ACV
L7905CT
L7905CV
L7912CT
L7912ACV
L7915CT
L7915ACV
LM7815CT
LM320T-5.0
LM7905CK
LM7905CT
LM7912CK
LM320T-12
LM7915CK
LM320T-15
SIEMENS
NATIONAL
TCA365
LH0101
SIGNETICS
NATIONAL
DAC-08
DAC-08
DAC-08
78LXXACS
78LXXADB
78LXXCDB
78LXXCS
78XXCU
78XXDA
79XXDA
79XXCU
LM109DB
TBA120S-4
TBA120S-3
TBA120S-2
LF198
LF298
LM309DA
LM309DB
LM340XXLL
LM340XXDA
LF398
NE529
SE529
SE532
SA532
NE532
SA534
NE555N
SE567
J.tA723CN
J.tA723CL
J.tA723L
J.tA723CF
J.tA723F
J.tA741
J.tA747
ADC0801
ADC0802
ADC0803
ADC0804
ADC0805
MC1408
MC1408
MC1408
MC1496N
MC1508
MC1596K
NE4558D
NE4558N
NE4558
NE5034
SE5118
NE5118
NE5410
SE5410
NE5532P
DAC0802
DAC0801
DAC0800
LM78XXACZ
LM78XXACH
LM78LXXCH
LM78LXXCZ
LM78XXCT
LM78XXCK
LM79XXCK
LM79XXCT
LM109H
TBA120SIV
TBA120SII1
TBA120S11
LF198
LF298
LM309K
LM309H
LM340TXX
LM340KXX
LF398
LM361
LM161
LM158
LM2904
LM358
LM2902
LM555CN
LM567
LM723CN
LM723CH
LM723H
LM723CJ
LM723J
LM741
LM747
ADC0801
ADC0802
ADC0803
ADC0804
ADC0805
DAC0808
DAC0807
DAC0806
LM1496N
DAC0808
LM1596H
LM833CM
LM833CN
LM833
ADC0841
DAC0830
DAC0830
DAC1020
DAC1020
LM833CN
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
NE5532
NE5532N
LM833
LM833CN
SILICON
GENERAL
NATIONAL
SG101
SG101A
SG107
SG124
SG201
SG201A
SG207
SG224
SG301A
SG307
SG324
SG741
SG741
SG1173
SG1436
SG1536
SG3173
LM101A
LM101A
LM107
LM124
LM201A
LM201A
LM207
LM224
LM301A
LM307
LM324
LM741
LM741
LM675
LM343
LM143
LM675
SILICONIX
NATIONAL
DG201
DG202
DG211
DG212
DG508
DG509
LF13201
LF13202
LF13201
LF13202
LF13508
LF13509
SPRAGUE
NATIONAL
UDN22933
LM18293
TELEDYNE
NATIONAL
TPOO32
TPOO33
LHOO32
LHOO33
TEXAS
INSTRUMENTS
NATIONAL
J.tA78XXCKC
J.tA78LXXACL
J.tA78MXXCKD
J.tA79MXXCKD
J.tA79XXCKC
TL061A
TL061B
TL061
TL062A
TL062B
TL062
TL064A
TL064
TL071B
TL071A
TL071
TL072
TL072A
TL072B
TL074
TL074A
TL081B
TL081
TL081 A
TL082B
TL082A
TL082
TL084A
TL084
LM78XXCT
LM78LXXACZ
LM78MXXCP
LM79MXXCP
LM79XXCT
LF441
LF441A
LF441
LF442
LF442
LF442
LF444
LF444
LF411
LF411
LF351
LF353
LF412
LF412
LF347
LF347B
LF411
TL081
LF411
LF412
LF412
TL082
LF3478
LF347
17
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(1)
(1)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
TL087
TL088
TLC274BI
TLC274BM
TLC274M
TLC274AC
TLC274BC
TLC274AM
TLC2741
TLC274C
TLC274AI
TL288
LM317KC
TL487N
TL489N
TL490N
TL491N
TL520
TL521
TL522
TL530
TL531
TL532
TLC532A
TLC533A
TL533
TLC540
TLC541
TLC549
J.tA709
J.tA723CN
J.tA723CJ
J.tA723MJ
J.tA733CN
J.tA741
J.tA747
ADC0801
ADC0802
ADC0803
ADC0804
ADC0805
ADC0808
ADC0809
ADC0831
ADC0832
ADC0834
ADC0838
RC4558
RV4558D
RC4558D
LF411A
LF411A
LMC660AI
LMC660AM
LMC660AM
LMC660AI
LMC660AI
LMC660AM
LMC660AI
LMC660C
LMC660AI
LF412A
LM317T
LM3915N
LM3914N
LM3914N
LM3914N
ADC0848
ADC0848
ADC0848
ADC0830B
ADC0830C
ADC0829B
ADC0829B
ADC0829C
ADC0829C
ADC0811
ADC0811
ADC0831
LM709
LM723CN
LM723CJ
LM723J
LM733CN
LM741
LM747
ADC0801
ADC0802
ADC0803
ADC0804
ADC0805
ADC0808
ADC0809
ADC0831
ADC0832
ADC0834
ADC0838
LM833
LM833CM
LM833CM
THOMSON
NATIONAL
LM105H
LM109K
LM117K
LM117H
LM123K
LM134
LM135
LM137K
LM137H
LM138K
LF198
LM234
LM235
LF298
LM305H
LM309H
LM309K
LM105H
LM109K STEEL
LM117KSTEEL
LM117H
LM123KSTEEL
LM134
LM135
LM137KSTEEL
LM137H
LM138KSTEEL
LF198A
LM234
LM235
LF298
LM305H
LM309H
LM309K STEEL
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
en
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LM317K
LM317H
LM323K
LM334
LM335A
LM335
LM337H
LM337K
LM338K
LF398
)J-A741
)J-A748
TBC0136
)J-A7805CK
)J-A7805MK
)J-A7812MK
)J-A7812CK
)J-A7815CK
)J-A7815MK
)J-A7905MK
)J-A7905CK
)J-A7912MK
)J-A7912CK
)J-A7915MK
)J-A7915CK
LM317K STEEL
LM317H
LM323K STEEL
LM334
LM335A
LM335
LM337H
LM337K STEEL
LM338KSTEEL
LF398A
LM741
LM748
LM336
LM7805KC
LM140K-5.0
LM140K-12
LM7812KC
LM7815KC
LM140K-15
LM120K-5.0
LM7905KC
LM120K-12
LM7912KC
LM120K-15
LM7915KC
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
TOSHIBA
TA7504
TA75339
TA75358
TA75393
TA75902
NATIONAL
LM741
LM2901
LM2904
LM2903
LM2902
(1)
(1)
(1)
(1)
UNITRODE
L293
L298
NATIONAL
LM18293
LM18298
(1)
(1)
(1)
(1)
(1)
(1)
(1)
18
~
Industry Package Cross-Reference Guide
CJ
'WWm
~=
~
1II0W
@
CJ
NSC
Signetics
Fairchild
Motorola
4/16 Lead
Glass/Metal DIP
0
I
0
L
Glass/Metal
Flat Pack
F
Q
F
F
TO-99, TO-100, TO-5
H
T,
K,
L,
DB
H
G
L
8-, 14- and 16-Lead
Low Temperature
Ceramic DIP
J
F
U
J
R,
0
TI
F,
5
RCA
Hitachi
NEC
LTC
0
C
0
0
K
F
5',
V1"
G
Q
A
H
0
J,
J8
'\fWWW
?
0
D
m
(Steel)
K
TO-3
KS
K
KC
OA
K
K
K
N
V,
A,
B
T,
P
P
P,
N
(Aluminum)
8-, 14- and 16-Lead
Plastic DIP
'WHh duaJ~n·llne formed leads
"WHh radically formed leads
19
E
P
C
N,
N8
NSC Signetlcs Fairchild Motorola
~~
~~
~=~
~~~
TO-202
(D-40, Durawatt)
TO-220
3-&5-Lead
TO-220
11-, 15- & 23-Lead
TI
P
T
RCA Hitachi NEC LTC
KD
U
U
KC
T
H
T
H
Z
G
8
T
Low Temperature
Glass Hermetic
Flat Pack
W
TO-92
(Plastic)
Z
M
F
F
W
8
W
P
LP
D
8
D
C3
~
ltJJiPijJ
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80
(Narrow Body)
(Wide Body)
WM
D
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1:11:11:11:11:11:11:11:11:11:1
btiUtR:PJJJUUtd
20
M
MP
NSC
Signetics
Fairchild
Motorola
TI
RCA
Hitachi
NEC
LTC
5'
a.
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CD
PCC
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LCC
Leadless Ceramic
Chip Carrier
E
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L1
11~~~~~~~11
21
U
FKI
FG/FH
BJ
CG
K
Linear 1 Databook
Selection Guides
Voltage Regulators
Operational Amplifiers
Buffers
Voltage Comparators
Instrumentation Amplifiers
23
Natlonal
~ Semiconductor
Corporation
Voltage Regulators
Definition of Terms
Current-Umlt Sense Voltage: The voltage across the current limit terminals required to cause the regulator to current-limit with a short circuited output. This voltage is used
to determine the value of the external current-limit resistor
when external booster transistors are used.
Output-Input Voltage Differential: The voltage difference
between the unregulated input voltage and the regulated
output voltage for which the regulator will operate within
specifications.
Output Noise Voltage: The RMS ac voltage at the output
with constant load and no inut ripple, measured over a
specified frequency range.
Output Voltage Range: The range of regulated output voltages over which the specifications apply.
Output Voltage Scale Factor: The output voltage obtained
for a unit value of resistance between the adjustment terminal and ground.
Quiescent Current: That par of input current to the regulator that is not delivered to the load.
Dropout Voltage: The input-output voltage differential at
which the circuit ceases to regulate against further reductions in input voltage.
Feedback Sense Voltage: The voltage, referred to ground,
on the feedback terminal of the regulator while it is operating in regulation.
Input Voltage Range: The range of dc input voltages over
which the regulator will operate within specifications.
Line Regulation: The change in output voltage for a
change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected.
Rlpply ReJection: The line regulation for ac inupt signals at
or above a given frequency with a specified value of bypass
capacitor on the reference bypass terminal.
Standby Current Drain: That part of the operating current
of the regulator which does not contribute to the load current. (See Quiescent Current)
Temperature Stability: The percentage change in output
voltage for a thermal variation from room temperature to
either temperature extreme.
Thermal Regulation: Percentage change in output voltage
for a given change in power dissipation over a specified time
period.
Load Regulation: The change in output voltage for a
change in load current at constant chip temperature.
Long Term Stability: Output voltage stability under accelerated life-test conditions ilt 12SoC with maximum rated voltages and power dissipation for 1000 hours.
Maximum' Power Dissipation: The maximum total device
dissipation for which the regulator will operate within specifications.
24
_NatiOnal
Semiconductor
Corporation
Voltage Regulators Selection Guide
Adjustable Positive Voltage Regulators
Amps
Device
Output Voltage
Package
10.0
LM196K
LM396K
1.25V-15V
1.25V-15V
TO-3
TO-3
5.0
LM138K
LM338K
1.2V-32V
1.2V-32V
TO-3
TO-3
3.0
LM150K
LM350K, T
1.2V-33V
1.2V-33V
TO-3
TO-3, TO-220
1.5
LM117K
LM117HVK
LM2941CT
LM317K, T
LM317HVK
1.2V-37V
1.2V-57V
5.0V-24V
1.2V-37V
1.2V-57V
TO-3
TO-3
TO-220
TO-3, TO-220
TO-3
0.5
LM117H
LM117HVH
LM317H
LM317HVH
LM317MP
1.2V-37V
1.2V-57V
1.2V-57V
1.2V-37V
1.2V-37V
TO-39
TO-39
TO-39
TO-39
TO-202
0.1
LM317LZ, M
LM2931CT
LP2951CN,J, H, M
1.2V-37V
3.0V-24V
1.24V-29V
TO·92,80-8
TO-220, 5-LEAD
DIP, CERDIP, HEADER, 80-8
Adjustable Negative Voltage Regulators
Output Voltage
Package
3.0
LM133K
LM333K, T
-1.2V - -32V
-1.2V - -32V
TO-3
TO-3, TO-220
1.5
LM137K
LM137HVK
LM337K, T
LM337HVK
-1.2V -1.2V -1.2V -1.2V -
-37V
-47V
-37V
-47V
TO-3
TO-3
TO-3, TO-220
TO-3
0.5
LM137H
LM137HVH
LM337H
LM337HVH
LM337MP
-1.2V -1.2V -1.2V -1.2V-1.2V -
-37V
-47V
-37V
-47V
-37V
TO-39
TO-39
TO-39
TO-39
TO·202
0.1
LM337LZ, M
-1.2V - -37V
Amps
Device
25
TO-92,80·8
Fixed Positive Voltage Regulators
Amps
Output Voltage
Package
3.0
LM123K
LM2943CP
LM323K
5V
5V
5V
T0-3
TO-220
TO-3
1.0
LM109K
LM140AK
LM140K
LM2940CT
LM309K
LM340AK, T
LM340K, T
LM78xxCK, T
5V
5V,12V,15V
5V,12V,15V
5V,12V,15V
5V
5V,12V,15V
5V, 12V, 15V
5V, 12V, 15V
TO-3
TO-3
TO-3
TO-220
TO-3
TO-3, TO-220
T0-3,T0-220
TO-3, TO-220
0.5
LM2984CT
LM341T, P
LM78MxxCT
5V,12V,15V
5V, 12V, 15V
5V,12V,15V
TO-220, T0-202
TO-220, TO-202
TO-220
0.2
LM109H
LM309H
LM342P
5V
5V
5V,12V,15V
TO-39
TO-39
TO-202
0.15
LM2930T
5V,8V
TO-220
0.1
LM140LAH
LM2931Z, T
LM340LZ, H
LM78lxxACZ, H, M
LP2950CZ
5V,12V,15V
5V
5V,12V,15V
5V,12V,15V
5V
TO-39
TO-92, TO-220
TO-92, TO-39
T0-92, TO-39, 80-8
TO-92
Device
'Future Product
Fixed Negative Voltage Regulators
Output Voltage
Package
-5V, -5.2V
-5V, -5.2V
TO-3
TO-3
LM120K
LM320K, T
LM79xxCT,K
-5V, -12V, -15V
-5V, -12V, -15V
-5V, -12V, -15V
TO-3
TO-3, TO-220
TO-3, TO-220
0.5
LM320MP
LM79MxxCP, K
-5V, -12V, -15V
-5V, -12V, -15V
TO-220
TO-202, TO-3
0.2
LM120H
LM320H
-5V, -12V, -15V
-5V, -12V, -15V
TO-39
TO-39
0.1
LM320LZ
LM79lxxACZ, M
-5V, -12V, -15V
-5V, -12V, -15V
TO-92
TO-92,80-8
Amps
Device
3.0
LM145K
LM345K
1.5
'The LM320 has better electrical characteristics than the LM79XlC.
LM100Series
+55'Cte +150"C
LM30DSeries
O'Cte + 125"C
26
Low Dropout Regulators
Amps
Device
Output Voltage
Package
0.100
LM2931T,Z
LP2950CZ
LP2951N, J, H
5V,ADJ
5V
ADJ
TO-220, TO-92
TO-92
DIP, CERDIP, HEADER
0.150
LM2930T
0.500
LM29B4CT
TRIPLE 5V
5V,BV
0.750
LM2925T
LM2935T
5V WITH DELAYED RESET
DUAL5V
TO-220, 5-LEAD
TO-220, 5-LEAD
+ WATCHDOG
TO-220
TO-220, 11-LEAD
1.5
LM2940CT
LM2941CT"
5V, 12V, 15V
ADJ
TO-220
TO-220, 5-LEAD
3.0
LM2943CT"
5V
TO-220
"Future Product
27
o
E
.---------------------------------------------------------------------------------~
~
o
c
o
NatiOnal
~ Semiconductor
Corporation
:z::
·c
Operational Amplifiers
Definition of Terms
~
~
Q.
~
"iii
c
o
~cg
8
Bandwidth: That frequency at which the voltage gain is reduced to 1/,f2 times the low frequency value.
Large-Signal Voltage Gain: The ratio of the output voltage
swing to the change in input voltage required to drive the
output from zero to this voltage.
Common-Mode Rejection Ratio: The ratio of the input
common-mode voltage range to the peak-ta-peak change in
input offset voltage over this range.
Harmonic Distortion: That percentage of harmonic distortion being defined as one-hundred times the ratio of the
root-mean-square (rms) sum of the harmonics to the fundamental. % harmonic distortion =
(V22
Output Impedance: The ratiO of output voltage to output
current under the stated conditions for source resistance
(Rs) and load resistance (RLl.
Output Resistance: The small signal resistance seen at the
output with the output voltage near zero.
Output Voltage Swing: The peak output voltage swing, referred to zero, that can be obtained without clipping.
+ V32 + V42 + .. .)1/2 (100%)
Offset Voltage Temperature Drift: The average drift rate
of offset voltage for a thermal variation from room temperature to the indicated temperature extreme.
Power Supply Rejection: The ratio of the change in input
offset voltage to the change in power supply voltages producing it.
Settling Time: The time between the initiation of the input
step function and the time when the output voltage has settled to within a specified error band of the final output voltage.
Slew Rate: The internally-limited rate of change in output
voltage with a large-amplitude step function applied to the
input.
Supply Current: The current required from the power supply to operate the amplifier with no load and the output midway between the supplies.
Transient Response: The closed-loop step-function response of the amplifier under small-signal conditions.
V1
where V1 is the rms amplitude of the fundamental and V2,
V3, V4, ... are the rms amplitudes of the individual harmonics.
Input Bias Current: The average of the two input currents.
Input Common-Mode Voltage Range: The range of voltages on the input terminals for which the amplifier is operational. Note that the specifications are not guaranteed over
the full common-mode voltage range unless specifically
stated.
Input Impedance: The ratio of input voltage to input current
under the stated conditions for source resistance (Rs) and
load resistance (RLl.
Input Offset Current: The difference in the currents into
the two input terminals when the output is at zero.
Input Offset Voltage: That voltage which must be applied
between the input terminals through two equal resistances
to obtain zero output voltage.
Input Resistance: The ratio of the change in input voltage
to the change in input current on either input with the other
grounded.
Input Voltage Range: The range of voltages on the input
terminals for which the amplifier operates within specifications.
Unity Gain Bandwidth: The frequency range from dc to the
frequency where the amplifier open loop gain rolls off to
one.
Voltage Gain: The ratio of output voltage to input voltage
under the stated conditions for source resistance (Rs) and
load resistance (RLl.
28
_NatiOnal
.
Semiconductor
. . Corporation
General Purpose Operational
Amplifier Selection Guide
Part #
Vas
mV(Max)
IB
GBW
nA(Max)
MHz (Typ)
Slew
Rate
V/p.s (Typ)
Military Temperature Range (-55"C to
LHOO44A
0.025
15
0.4
LMS07A
0.025
2
LHOO44
0.05
30
LMS07B
0.05
3
1.8
LM11
0.3
0.05
LF411A
0:5
0.2
4
LF441 A
0.5
0.05
LH0052
0.5
0.003
LM10BA
0.5
LF412A
Supply
Current
(Note 3)
mA(Max)
Min
V
+ 125"C) Specs at TA =
O.OS
3
1.8
0.7
1.5
0.4
O.OS
4
0.7
1.5
0.3
O.S
15
2.8
1
1
1
3
2
1
1
0.2
·
Supply
Voltage
Max
V
25"C (Note 1)
±3
·
·
·
±3
±20
±22
±20
±22
±20
±S
±22
0.2
±S
±22
3.5
±5
±22
0.3
0.4
±2
±20
4
15
5.S
±S
±22
Dual BiFet
1
1
0.4
±S
±22
Dual BiFet
±5
±45
LF442A
1
0.05
LHOO04
1
100
LMS04A
1
40
7
·
0.15
2
B
4
3S
LF155A
2
0.05
2.5
5
4
±5
±22
LF15SA
2
0.05
5
12
7
±5
±22
LF157A
2
0.05
25
50
7
±5
±22
LF411.
2
0.2
4
15
3.4
±S
±1B
LMC6S0A
2
0.02
1.5
1.7
2.2
5
15
LM10
2
20
LM101A
2
75
LM107
2
75
LM10B
2
LM112
·
·
1
·
0.4
0.5
3
±3
±22
1
0.5
3
±3
±22
2
1
0.3
0.4
±2
±20
2
2
1
0.2
O.S
±2
±20
•
LM124A
2
50
LM158A
2
50
•
•
LP124
2
4
0.1
2.5
250
LF412
3
0.2
LM741 A
3
BO
LH0022
4
0.01
LF155
5
0.1
LH0020
Special
Features
(Note 4)
Multiplexed OA
Minimum Gain of 5
Quad CMOS
OA
+ Reference
Compensated LM10B
3
3
32
1.2
3
32
Dual
0.05
0.13
3
32
Quad
•
5
±5
±22
4
15
S.B
±S
±22
1.5
0.7
2.B
±a
±22
1
3
3.5
±5
±22
2.5
5
4
±5
±22
·
·
29
Quad
Dual
General Purpose Operational Amplifier Selection Guide (Continued)
Part #
la
nA(Max)
vos
mV(Max)
GBW
MHz (Typ)
Slew
Rate
V/!£s(Typ)
Military Temperature Range (-55·C to
Supply
Current
(Note 3)
mA(Max)
Supply
Voltage
Min
V
+ 125·C) Specs atTA =
Special
Features
Max
V
25·C (contihued)
LF156
5
0.1
5
12
7
±5
±22
LF157
5
0.1
20
50
7
±5
±22
Minimum Gain of 5
LF147
5
0.2
4
13
11
±6
±22
Quad BiFet
Dual BiFet
LF412
5
0.2
4
15
6.8
±6
±18
LF442
5
0.1
1
1
0.5
±6
±18
Dual BiFet
LF444A
5
0.1
1
1
0.80
±6
±22
Quad BiFet
LHOO86
5
0.5
3
10
15.5
±8
±18
Programmable Gain OA
LM124
5
150
•
•
3
3
32
LM143
5
20
1
2.5
4
±4
±40
LM144
5
20
1
2.5
4
±4
±40
Minimum Gain of 10
LM146
5
100
1.2
0.4
2
±1.5
±22
(Note 5)
Quad
Quad
LM14B
5
100
1
0.5
3.6
±5
±22
LM149
5
100
4
2
3.6
±5
±22
LM15B
5
150
1.2
3
32
Dual
LM192
5
150
90mparator and Op Amp
LM741
5
500
·
·
··
·
·
2
3
32
0.5
2.B
±3
±22
·
Minimum Gain of 5, Quad
LM155B
5
500
5
±3
±22
Dual
LM4250
5
50
0.2
0.2
0.1
±1
±18
(Note 5)
LH0042
20
0.025
1
3
3.5
±5
±22
Vos
mV(Max)
la
nA(Max)
GBW
LMC669B
0.025
0.1
LH0044B
0.05
30
0.4
LHOO44C
0.05
30
LMC669C
0.05
0.1
LM20BA
0.5
2
Part #
MHz (Typ)
Slew
Rate
VII's (Typ)
Supply
Current
(!IIote 3)
mA(Max)
Industrial Temperature Range (- 2S·C to
·
Supply
Voltage
Min
V
+ as·C) (Note 1)
·
6
±8
±22
0.06
4
±3
±20
0.4
0.06
4
±3
±20
•
6
±8
±22
1
0.3
0.6
±2
±20
·
LH0052C
1
0.005
1
3
3.8
±5
±22
LMC660A
2
0.02
1.5
1.7
2.2
5
15
LM10B(L)
2
20
•
LM201A
2
75
1
0.5
LM207
2
75
1
LM20B
2
2
1
LM212
2
2
1
LM224A
3
BO
•
·
0.4
(Note 4)
3
±3
±22
0.5
3
±3
±22
0.3
0.6
±2
±20
0.3
0.6
±2
±20
2
3
32
·
30
Special
Features
Max
V
Autozero Block
Autozero Block
QuadCMO~
Op Amp and Reference
Compensated LM20B
Quad
o
'a
General Purpose Operational Amplifier Selection Guide (Continued)
Part #
Vos
mV(Max)
la
nA(Max)
GBW
MHz (Typ)
Slew
Rate
VIILS (Typ)
Supply
Current
(Note 3)
mA(Max)
Industrial Temperature Range (- 25·C to
LM258A
·
80
3
Supply
Voltage
Min
V
·
1.2
3
:::!l
0.1
2.5
5
4
±5
±22
0.1
5
12
7
±5
±22
LF257
5
0.1
20
7
±5
±22
LM224
5
150
2
3
LM258
5
150
1.2
3
LM292
5
250
·
·•
50
LH0020C
6
500
•
LH0022C
6
0.025
1
LM246
6
250
LM248
6
200
LM249
6
LH0086C
LH0042C
·•
·
·
CD
CD
ii"
o
:s
32
Quad
G)
32
Dual
Comparator and Op Amp
3
32
6
±5
±22
3
4
±5
±22
0.5
0.4
2.5
±2
±18
(Note 5)
1
0.5
4.5
±5
±18
Quad
200
4
2
4.5
±5
±18
Minimum Gain of 5, Quad
10
0.5
3
10
15.5
±8
±18
Programmable Gain 1 to 200
20
0.05
1
3
4
±5
±22
la
nA(Max)
GBW
Slew
Rate
VIILS (Typ)
Supply
Current
(Note 3)
mA(Max)
Supply
Voltage
Min
V
0.06
1
2.5
3.5
2.5
3.5
·
·
·
·
·
18
LM607A
0.025
2
1.8
LMC669C
0.05
0.1
•
LM607B
0.05
3
1.8
0.7
1.5
LM607
0.15
10
1.8
0.7
1.8
LF411A
0.5
0.2
4
15
2.8
±s
±22
LF441 A
0.5
0.05
1
1
0.2
±6
±22
LM308A
0.5
7
±2
±20
LM11C
0.6
LF412A
1
LF442A
0.06
1
0.1
•
0.7
Special
Features
Max
V
.
.
0.01
0.025
6
1.5
6
±8
±8
18
±22
Com mutating Autozero
Commutating Autozero
Autozero Block
±22
±22
Autozero Block
±22
±22
1
0.3
0.8
0.1
•
0.3
0.8
0.2
4
15
5.6
±6
±22
Dual
1
0.05
1
1
0.4
±6
±22
Dual
LM604A
1
40
5
3
9
4
36
LF355A
2
0.05
2.5
5
4
±5
±22
LF356A
2
0.05
5
12
10
±5
±22
LF357A
2
0.05
20
50
10
±5
±22
31
c
is:
CD
en
+ 70·C) (Notes 1 and 2)
0.005
LMC669B
a:
Minimum Gain of 5
2
Commercial Temperature Range (O"C to
LMC668
...
Dual
(/)
5
LMC668A
3
~
32
5
MHz (Typ)
:I>
+ 8S-C) (continued)
LF256
VOS
mV(Max)
~
:s
!!.
Special
Features
Max
V
LF255
Part #
CD
·
±20
Multiplexed Op Amp
Minimum Gain of 5
-
General Purpose Operational Amplifier Selection Guide (Continued)
G,BW
Slew
Rate
V/p.s(Typ)
Supply
Current
(Note 3)
mA(Max)
Supply
Voltage,
Special
Features
Vos
mV(Max)
la
nA(Max)
LF4tt
2
0.2
4
t5
3.4
±6
±22
LF4t2
3
0.2
4
t5
6.8
±6
±22
Dual
LM324A
3
100
3
3
32
Quad
LM358A
3
100
•
•
LM604
3
60
5
LM741E
3
80
1.5
LM1OC(L)
4
30
•
LP324
4
10
Part ""
MHz(Typ)
Commercial Temperl!ture Range (O"C to
·
·
Min
V
Max
V
+ 70"C) (continued)
2
3
32
Dual
7
9
4
36
Multiplexed Op Amp
0.7
2.8
±3
±22
0.1
0.05
0.15
3
32
·
0.5
(Note 4)
LF347B
5
0.2
4
13
11
±6
±22
LF355B
5
0.1
2.5
5
4
±5
±22
LF356B
5
0.1
5
12
4
±5
±22
LF357B
5
0.1
20
50
7
±5
±22.
LF441
5
0.1
1
1
0.25
±6
±22
LF442
5
0.1
1
1
0.5
±6
±22
LM11CL
5
0.2
0.3
0.8
•
±20
LM392
5
250
•
•
•
2
3
32
LM833
5
1000
10
5
8
•
±18
LMC660
6
0.02
1.5
1.7
2.7
5
15
LM346
6
250
0.5
0.4
2.5
±1.5
±22
LM348
6
200
1
0.5
4.5
±5
±18
,LM349
6
200
4
2
4.5
±5
±18
LM741C
6
500
1.5
0.5
2.8
±3
' ±18
LM1458
6
500
•
5.6
±3
±18
LM4250C
6
75
0.2
0.1
±1
±18
LM324
7
250
•
•
3
3
32
2
3
32
3
±3
±18
OA and Reference
Quad
Dual
Dual Low Noise
Quad CMOS
(Note 5)
7
250
·
·•
LM301A
7.5
250
1
0.5
LM307
7.5
250
1
0.5
3
±3
±18
LM308
7.5
7
1
0.3
0.8
±2
±18
LM312
7.5
7
1
0.2
0.8
±2
±18
LM343
8
40
1
2.5
5
±4
±34
LM344
8
40
1
2.5
5
±4
±34
Minimum Gain of 10
LF347
10
0.2,
4
13
11
±6
±18
Quad BiFet
LF351
10
0.2
4
13
3.4
±6
±18
LF353
10
0,2
4
13
6.8
±6
±18
LF355
10
0.2
2.5
5
4
±5
±18
LF356
10
0.2
5
12
10
±5
±18
LF357
10
0.2
20
50
10
±5
±18
LM358
0.2
32
(Note 5)
Compensated LM308
Dual BiFet
Minimum Gain of 5
General Purpose Operational Amplifier Selection Guide (Continued)
Vos
mV(Max)
Part '"
Supply
Current
(Note 3)
mA(Max)
Slew
Rate
VlILS (Typ)
GBW
18
nA(Max)
MHz (Typ)
Commercial Temperature Range (O"C to
Supply
Voltage
Min
V
Max
V
+ 70'C) (continued)
LF444
10
0.1
1
1
1
15
0.2
1
0.5
4
.
±18
LF13741
TL081C
15
0.2
4
13
2.8
±6
±18
TL082C
15
0.2
4
13
5.6
±6
±18
Part '"
Vos
mV(Max)
18
nA(Max)
GBW
MHz (Typ)
Slew
Rate
VllLs (Typ)
Special
Features
Supply
Current
(Note 3)
mA(Max)
Automotive Temperature Range (- 40'C to
±6
Supply
Voltage
Min
V
Quad BiFet
±18
Dual BiFet
Special
Features
Max
V
+ 85"C)
LM604
3
60
7
3
9
4
36
Multiplexed Op Amp
LP2902
4
20
0.1
0.05
0.15
3
26
Quad
LM2902
7
250
•
3
3
26
Quad
LM2904
7
250
2
3
26
Quad
7
250
2
3
26
Comparator Plus Op Amp
LM2924
'Not Specified.
·
·
·
·
·
Nole I: Datasheet should be referred to for test conditions and more detailed information.
Note 2: Those looking for a commercial part should also look at Ihe Industrial Temp Range guide as many Hybrids are listed there.
Note 3: Supply current is for all amplifiers In a package.
Note 4: The LMIO has 2 versions: one a high voltage part, good to 45V and a low voltage part, good to 7V. Refer to the datasheet for more information.
Note 5: The LM146 and LM4250 are programmable amplifiers. The dala shown is for Vs = ± 15V and ISET = 10 "A. Refer to the datasheets for more information.
33
~NaHonal
Semiconductor
CorporaHon
Low IBIAS Selection Guide
:5:5pA
I
:5:20pA
I
:5:50pA
I
:5:100pA
I
:5:200pA
I
:5:500 pA
I
:5: 1 nA
TA = 25°C
LHOO22
LMC668
LHOO32A
LHOO32
LF401A
LH4101
LHOO22C
LMC660
LF155A1156A
LF155/156
LF401
LHOO32C
LF400A
LHOO86
LF400
LHOO86C
LHOO42
LHOO42C
LHOO52
LF157A
LF355A1356A
LF357A
LHOO52C
LF441 A
LHOO62
LF442A
LF157
LF255/256
LF257
LF3558/3568
LF3578
TL081
LHOO32AC
LF351
LF444A
LF441
LF411A1411
LM11
LF442
LF355/356
LF444
LF357
LM11C
LF14713478/347
LHOO62C
LF353
LF412A1412
LF13741
LM11CL
Note: Datasheet should be referred to for conditions and more detailed information.
34
LH4104
_NaHonal
Semiconductor
CorporaHon
High Speed Operational
Amplifier Selection Guide
Part #
Slew Rate
V/p.s (Typ)
GBW
MHz (Typ)
Vos
mV(Max)
Is
mA(Max)
(Note 2)
Notes
GBW;?; 4 MHz, TA = 25"C
LH0024
500
70
8
15
LH0032
500
70
15
22
LM6361
300
50
20
6.8
LM6364
300
175
9
6.8
LM6365
300
725
7
6.8
Min Gain of 25
LH4101
250
40
15
40
Medium Power JFET
LF400
70
16
2.5
12
Fast Settling JFET
LF401
70
16
0.5
12
Precision Fast Settling JFET
LHOO03
70
30
3
3
LH0062
70
15
15
12
LM318
70
15
10
10
LF357
50
20
10
10
Min Gain of 5, JFET
LH41 04
40
16
10
Medium Power Fast Settling JFET
LM359
30
30
.
25
22
Dual Current Mode (Norton) Amp
LF411
15
4
2
3.4
JFET
LF412
15
4
3
6.8
DualJFET
LF347
13
4
10
11
QuadJFET
LF351
13
4
10
3.4
JFET
LF353
13
4
10
6.8
DualJFET
LF356
12
4.5
10
10
JFET
LM833
7
15
5
8
Dual Low Noise
FET Input
Min Gainof5
FET Input
·Nol specified.
Nole 1: Oatasheet should be referred to for conditions and more detailed information. Many versions with better DC specs are available in addition to those listed
above.
Note 2: Supply current is for all amplifiers in a package.
35
~NatiOnal
Semiconductor
Corporation
Medium and High Power Operational Amplifier
Selection Guide (~ 0.1 A Output)
Part "
lOUT
A (Typ)
Vos
mV(Max)
Is
mA(Max)
Slew Rate
V//J-S(Typ)
LH41 04
0.1
10
25
40
LH41 01
0.1
15
40
250
PBW
kHz (Typ)
·
·
LH0041
0.2
6
4
1
20
LH0061
0.5
15
15
25
1000
LH0021
1.0
6
4
1
20
LH0101A
2
. 3
35
10
300
LH0101
2
10
35
10
300
LM675
3
10
50
B
LM12(L)
(Note 2)
7
BO
9
60
LM12C(L)
(Note 2)
15
120
9
60
·
'Not Specified
Note 1: Refer to Datasheet for cond~ions and more detailed Information.
Note 2: lOUT for the LM12 is dependent on the amount of power dissipated in the output transistor. The datasheet should be referred to, to determine amount of
current available.
36
o
_
"a
National
CD
a
o·
Semiconductor
Corporation
~
!!!.
~
Special Amplifier Selection Guide
3
"2::;;
Ci·
...en
LH0045
LHOOB2
LHOOB6
CD
Two Wire Transmitter
20 MHz Transimpedance Amplifier
Programmable Gain Operational Amplifier
CD
2-
o·
~
Q
LM359
Dual Current Mode (Norton) Amplifier
LM2900, 3900, Quad Current Mode (Norton) Amplifier
3301,3401
LM3080
LM13600
13700
LM604
c
a:
CD
en
Operational Transconductance Amplifier
Dual Operational Transconductance Amplifier with Linearizing Diodes and Buffers
Improved Dual Operational Transconductance Amplifier with Linearizing Diodes and Buffers
4 In, lOut Multiplexed Op Amp
Note: Refer to the datasheet for specifications.
37
0r-----------------------------------------------------------------E
~
'0
c
_
NaHonal
Semiconductor
CorporaHon
o
:;=
c
!
~
::s
m
Buffers
Definition of Terms
Bandwidth: That frequency at which the voltage gain is reduced to 1/,j2 times the low frequency value.
Large-Signal Voltage Gain: The ratio of the output voltage
swing to the change in input voltage required to drive the
output from zero to this voltage.
Output Impedance: The ratio of output voltage to output
current under the stated conditions for source resistance
(Rs) and load resistance (RLl.
Common-Mode Rejection Ratio: The ratio of the input
common-mode voltage range to the peak-to-peak change in
input offset voltage over this range.
Harmonic Distortion: That percentage of harmonic distortion being defined as one-hundred times the ratio of the
root-mean-square (rms) sum of the harmonics to the fundamental.
% harmonic _ (V22 + V3 2 + V42 + .. , )1/2 (100%)
distortion VI
Output Resistance: The small signal resistance seen at the
output with the output voltage near zero.
Output Voltage Swing: The peak output voltage swing, referred to zero, that can be obtained without clipping.
Offset Voltage Temperature Drift: The average drift rate
of offset voltage for a thermal variation from room temperature to the indicated temperature extreme.
Power Supply ReJection: The ratio of the change in input
offset voltage to the change in power supply voltages producing it.
Settling Time: The time between the initiation of the input
step function and the time when the output voltage has settled to within a specified error band of the final output voltage.
Slew Rate: The internally-limited rate of change in output
voltage with a large-amplitude step function applied to the
input.
where V1 is the rms amplitude of the fundamental and V2,
V3, V4, ... are the rms amplitudes of the individual harmonics.
Input Bias Current: The average of the two input currents.
Input Common-Mode Voltage Range: The range of voltages on the input terminals for which the amplifier is operational. Note that the specifications are not guaranteed over
the full common-mode voltage range unless specifically
stated.
Input Impedance: The ratio of input voltage to input current
under the stated conditions for source resistance (Rs) and
load resistance (RLl.
Input Offset Current: The difference in the currents into
the two input terminals when the output is at zero.
Supply Current: The current required from the power supply to operate the amplifier with no load and the output midway between the supplies.
Transient Response: The closed-loop step-function response of the amplifier under small-signal conditions.
Unity Gain Bandwidth: The frequency range from dc to the
frequency where the amplifier open loop gain rolls off to
one.
Voltage Gain: The ratio of output voltage to input voltage
under the stated conditions for source resistance (Rs) and
load resistance (RLl.
Input Offset Voltage: That voltage which must be applied
between the input terminals through two equal resistances
to obtain zero output voltage.
Input Resistance: The ratio of the change in input voltage
to the change in input current on either input with the other
grounded.
Input Voltage Range: The range of voltages on the input
terminals for which the amplifier operates within specifications.
38
~NaHonal
Semiconductor
CorporaHon
Buffers Selection Guide (Notes 1 and 2)
-3dB
Device
Type
MHz (Typ)
LMll0, 210, 310
LH4001
LHOO02
S.R.
Vos
mV(Max)
Is
mA(Max)
Voltage
Gain (Typ)
VOUT
V (Min)
20
7.5
5.5
0.9999
±10
3.0
10
25
30
500
±30
10
10
0.97
0.97
±10
±10
125
100
200
200
LH0033
100
20
24
0.98
±9
1400
100
LH4002
LH0063
200
200
50
±50
35
65
0.85
0.93
±3
±10
1250
2400
40
250
'Not specified
Note 1: Datesheet should be referred to for test conditions and more detailed information.
Note 2: 200'C Temp Range Parts are available. Consult local sales office for information.
39
V/,.s (Typ)
lOUT
mA(Typ)
J~
'S
c
Natlonal
Semiconductor
CorporaHon
.2
:t:
c
i
Voltage Comparators
Definition of Terms
t
Input Bias Current: The average of the two input currents.
Input Offset Current: The absolute value of the difference
between the two input currents for which the output will be
driven higher than or lower than specified voltages.
at
Input Offset Voltage: The absolute value of the voltage
between the input terminals required to make the output
voltage greater than or less than specified voltages.
Input Voltage Range: The range of voltage on the input
terminals (common-mode) over which the offset specifications apply.
8CD
S
~
Response Time: The interval between the application of an
input step function and the time when the output crosses
the logic threshold voltage. The input step drives the comparator from some initial, saturated input voltage to an input
level just barely in excess of that required to bring the output
from saturation to the logic threshold voltage. This excess is
referred to as the voltage overdrive.
Saturation Voltage: The low-output voltage level with the
input drive equal to or greater than a specified value.
Strobe Current: The current out of the strobe terminal
when it is at the zero logic level.
Strobe Output Level: The DC output voltage, independent
of input conditions, with the voltage on the strobe terminal
equal to or less than the specified low state.
Strobe "ON" Voltage: The maximum voltage on either
strobe terminal required to force the output to the specified
high state independent of the input voltage.
Logic Threshold Voltage: The voltage at the output of the
comparator at which the loading logic circuitry changes its
digital state.
Negative Output Level: The negative DC output voltage
with the comparator saturated by a differential input equal to
or greater than a specified voltage.
Output Leakage Current: The current into the output terminal with the output voltage within a given range and the
input drive equal to or greater than a given value.
Output Resistance: The resistance seen looking into the
output terminal with the DC output level at the logic threshold voltage.
Strobe "OFF" Voltage: The minimum voltage on the strobe
terminal that will guarantee that it does not interiere with the
operation of the comparator.
Strobe Release Time: The time required for the output to
rise to the logic threshold voltage after the strobe terminal
has been driven from zero to the one logiC level.
Supply Current: The current required from the positive or
negative supply to operate the comparator with no output
load. The power will vary with input voltage, but is specified
as a maximum for the entire range of input voltage conditions.
Output Sink Current: The maximum negative current that
can be delivered by the comparator.
Positive Output Level: The high output voltage level with a
given load and the input drive equal to or greater than a
specified value.
Power Consumption: The power required to operate the
comparator with no output load. The power will vary with
signal level, but is specified as a maximum for the entire
range of input signal conditions.
.
Voltage Gain: The ratio of the change in output voltage to
the change in voltage between the input terminals producing it.
40
~
Sf
_NatiOnal
Semiconductor
Corporation
CC
CD
oo
3
"CI
Voltage Comparators Selection Guide
II)
iiJ
0'
Cil
en
CD
Response
Time (Typ)
ns
CD
Vos
mV(Max)
Is
mA(Max)
n
18
nA(Max)
Comments
o·
::::I
C)
T A = 2S'C (Notes 1 and 2)
C
LM361
LM360
12
16
5
5
25
32
30,000
20,000
High Speed w/Strobes
High Speed, Complementary Outputs
LM306
LM319
LF311
40
80
200
5
8
10
10
12.5
7.5
25,000
1000
0.15
High Speed, High Drive
High Speed Dual
FETlnput
LM311
LM339
LM392
200
1300
1300
10
5
10
7.5
2
1
300
400
400
General Purpose Single
General Purpose Quad
One Comparator Plus One Op Amp
LM393
LM2903
LM2901
1300
1300
1300
5
5
7
2.5
2.5
2
250
250
400
General Purpose Dual
Automotive Dual
Automotive Quad
LP365
LP311
LP339
4000
4000
5000
9
10
9
0.30
0.3
0.1
200
150
40
Programmable Quad
Low Power Single
Low Power Quad
'Not Specified
Note 1: Datasheet should be referred to for test conditions and more detailed information.
Note 2: This selection guide should be used to select for Response Time required. Industrial and Military Temperature Range types are available. The DC specs
are for the lowest Commercial Grade available.
41
a:
CD
o
E
CU
-
1-.
o
c
o
;;
r---------------------------------------------------------------------------------~
~ Semiconductor
NatiOnal
Corporation
"2
Instrumentation Amplifiers
Definition of Terms
ic
1:...
cu'
a...
==
E
c
of the change in output voltage to the change in
output current with the output around zero.
Output Voltage SwIng
The peak output voltage swing, referred to zero, that can be
obtained without clipping.
Class 0
A switching or sampling amplifier with extremely high efficiency (approaching 100%). The output devices are used as
switches, voltage appearing across them only while they are
off, and current flowing only when they are saturated.
Power BandwIdth
The power bandwidth of an audio amplifier is the frequency
range over. which the amplifier voltage gain does not fall
below 0.707 of the flat band voltage gain specified for a
given load and output power.
Crossover DIstortIon
Distortion caused in the output stage of a class B amplifier.
It can result from Inadequate bias current allowing a dead
zone where the output does not respond to the input as the
input cycle goes through its zero crossing point. Also for
IICs an inadequate frequency response of the output PNP
device can cause a turn-on delay giving crossover distortion
for negative gOing transition through zero at the higher audio frequencies.
Power bandwidth also can be measured by the frequencies
at which a specified level of distortion is obtained while the
amplifier delivers a power output 6 dB below the rated output. For example, an amplifier rated at 60 watts with
";;0.25% THD, would make its power bandwidth measured
as the difference between the upper and lower frequencies
at which 0.25% distortion was obtained while the amplifier
was delivering 30 watts.
Power Supply ReJection
The ratio of the change in input offset voltage to the change
in power supply voltages producing it.
DolbyB
Dolby B is a simplified version of the Dolby A professional
quality noise reduction system. The amplitude of low level
signals over a selected frequency range is increased prior to
recording to enhance them above tape noise. On playback
the original levels are restored causing a corresponding reduction in the audible tape noise. The major difference with
Dolby A which used four frequency bands, is the use of a
single variable frequency band with a cut-off frequency that
increases in the presence of high level high frequency signals.
SlewRate
The Internally limited rate of change in output voltage with a
large amplitude step function applied to the Input.
Supply Current
The current required from the power supply to operate the
amplifier with no load and the output at zero.
Thermal ResIstance (RTH)
An analogy for heat transfer where the ability of a heat conductive system to transfer heat is described in similar terms
to those used In an electrical system for power dissipated in
a resistor with a given applied voltage. The thermal resistance is given
by the temperature differential
established when a given amount of power is being dissipated (9 = T1 - T2/Po) with units of 'C/watt.
Dolby Level
Because of the complementary nature of the Dolby B noise
reduction system, the audio channel between the encoder
and the decoder must have a fixed gain such that the decoding signal level is within 2 dB of the encoding signal
level. Also if recordings are interchangeable the signals in
the noise reduction system must be related to the levels in
46
~
c
a.
O·
_NatiOnal
. Semiconductor
Corporation
en
CD
CD
!l
O·
Audio Selection Guide
~
C)
c
a:
CD
PREAMPLIFIERS
Application
Portable
Auto
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
LM382
LM387
LM1818
LM1837
LM1897
LM833
(Note 1)
LM837
(Note 1)
Equivalent
Input Noise
THO
PSR
Input
Coupling
14 Pin DIP
9V-40V
0.5 p,V
0.1%
120dB
AC
Stereo
14 Pin DIP
9V-40V
0.8 p,V
0.1%
120dB
AC
Stereo
Package
Home
LM381
Voltage
Range
Notes
8 Pin DIP
9V-30V
0.65 p,V
0.1%
110dB
AC
Stereo
20 Pin DIP
3.5V-18V
0.85 p.V
0.05%
85dB
AC
Tape System
18 Pin DIP
4V-18V
0.6 j£Vt
0.03%
105dB
DC
Autoreverse
16 Pin DIP
4V-18V
0.6 p.vt
0.03%
105 dB
DC
Few Externals
8Pin DIP
8 Pin SO
±5V-±15V
0.5 p.V
0.002%
100 dB
DC
Low Noise
DualOpAmp
14 Pin DIP
14 Pin SO
±5V-±15V
0.5 p.V
0.002%
100 dB
DC
Low Noise
QuadOpAmp
Drives 6000 Load
tCCIRI ARM in DIN circuR referred to unity gain at 2 kHz.
Note 1: Data sheet in Linear 1.
AUDIO POWER AMPLIFIERS
Application
Package
Portable Home Auto
•
LM380
LM383
•
LM384
8 Pin DIP
14 Pin DIP
•
•
•
Power·
ao
@
20
2.5W
5 Pin TO-220
14 Pin DIP
40
Voltage
5.5W 8.6W
14.4V
0.2%
Single 4V Operation
0.1%
Single Minimum
Externals
0.2%
Single Includes
Transistor
Array
0.2%
Single Battery
Operation
14Pin DIP
LM389
•
18 Pin DIP
0.33W
6V
LM390
•
14 Pin DIP
lW
6V
LM2877
•
•
•
•
•
LM1895
•
LM2895
•
12V
16 Pin DIP
Single Protected
6V
•
LM391
2 p,V
Single Fixed Gain
LM388
LM1877
0.2%
Single SeeAN-69
0.25%
•
2.2W
Yes
Notes
22V
LM386
0.33W
Input Singlel
Noise· Dual
0.2%
18V
5.5W
8 Pin DIP
8 Pin SO
Bridgeable THO·
60V-l00V
Yes
Yes
0.01%
3 p.V
Single Power Driver
•
•
14 Pin DIP
3W
20V
0.05% 2.5 p.V
Dual
6V-24V
11 Pin SIP
4.5W
20V
0.07% 2.5 p.V
Dual
Single-In-Line
Package
•
•
8 Pin DIP
1.lW
6V
•
•
11 Pin SIP
4.3W
12V
47
0.20/.
1.4 p.V
0.15% 1.4 p.V
Single Low AM
Radiation
Single 3V-15V
AUDIO POWER AMPLIFIERS (Continued)
Application
Power'
Package
ao
Portable Home Auto
40
@
20
Voltage
Bridgeable
THO'
Input Singlel
Noise' Dual
Notes
LM1896
•
•
•
14 Pin DIP
1.IW
6V
Yes
0.1%
1.4Jl.V
Dual
Low AM
Radiation
LM2896
•
•
11 Pin SIP
2.5W
9V
Yes
0.1%
1.4 Jl.V
Dual
No Pops
LM2002
•
•
•
LM831
5 Pin TO-220
•
LM2878
•
14.4V
Yes
0.1%
2Jl.V
11 Pin SIP
5.5W
5.2W 8W
22V
Yes
0.15%
2.5Jl.V
Dual
6V-32V
16 Pin DIP
20 Pin SO
O.44W
3V
Yes
0.2%
1.3 Jl.V
Dual
1.8V-6V
LM12
(Note 1)
•
TO-3
50W
LM675
(Note 1)
•
5 Pin TO-220
20W
±25V
LM1875
•
5 Pin TO-220
20W
±25V
•
LM2005
11 Pin TO-220
•
LM2879
11 Pin TO-220
±30V
85W
20W
8W
0.01%
Single Protected
Single Power
OpAmp
3Jl.V
Single Power
OpAmp
0.015%
3Jl.V
Single Low Crossover
Distortion
14.4V
Yes
0.3%
1.5 Jl.V
Dual
Protected
28V
Yes
0.05%
2.5Jl.V
Dual
6V-32V
'Note that all values shown are typical. Please refer to data sheets for test conditions.
Note 1: Data sheet in Linear 1.
AUDIO CONTROLS
Application
Package
Voltage
Range
Portab,e Home Auto
LM1035/
LM1036
•
•
•
20 Pin DIP
8V-18V
LM1037
•
•
18 Pin DIP
5V-30V
•
•
18 Pin DIP
5V-30V
LM1038
•
LM13600
(Note 1)
LM13700
(Note 1)
•
•
•
•
•
•
•
16PinSO
LM3080
(Note 1)
•
•
•
8 Pin DIP
LM1040
•
•
•
24 Pin DIP
LMC835
•
•
28 Pin DIP ±2.5V-±8V
LMC1992/
LMC1993
(Note 2)
•
•
28 Pin DIP
Volume
Signal to
THO Separation
Control Range Noise
80dB
75 dB
Dual DC Controlled
TonelVolume/Balance
100 dB 0.04%
100dB
DC Audio Switch
100dB 0.04%
100dB
BCD Logic Control
0.5%
100dB
Transconductance
Amplifiers
80dB
16 Pin DIP ±2V-±18V
0.05%
Transconductance
Amplifier
±2V-±18V
9V-16V
7V-15V
Notes
75dB
80dB
'Distortion determined by external op amps.
Note 1: Data sheet In Linear 1.
Note 2: LMC1992 selects 4 inputs.
LMC1993 selects 3 inputs and ~ a loudness control.
48
80dB
0.06%
114dB
.
105dB 0.03%
75 dB
Dual DC Controlled
TonelVolume/Balance
Stereo Enhancement
7 Band Graphic Equalizer
MICROWIRETM
Controlled
95dB
Stereo Volume/
Tone/Fade/Select
MICROWIRETM
Controlled
»
c
c.
o·
NOISE REDUCTION
Application
Voltage
Range
NR
Type
NR
Effect"
lV-20V
Dolby
10dS
4.5V-18V
DNR
12dS
6V-20V
Dolby
10 dS
28 Pin DIP, Quad
5V-16V
Dolby
Yes
Single
14 Pin DIP, SO
1.5V-9V
DNR
No
Dual
Package
Portable Home Auto
•
•
•
•
•
•
LMl131
LM1894
LMll12
LMl141
LM832
•
•
•
•
•
•
18 Pin DIP
14 Pin DIP, SO
·
16 Pin DIP
Encoding Singlel Decode
SINRequired Duall
12 dS
Notes
Dual
90dS
DC Switched
No
Dual
l6dS
NSCSystem
Yes
Single
83dS
Yes
NSCSystem
-Note that all values shown are typical. Please refer to data sheets for test conditions.
Monaural Cassette Player
CASSmE SYSTEM ~
LM1818
TAPE
AUDIO AMPLIFIER
LM1895
LM386
LM389
-;(]
TL/XX/OO13-1
Home Stereo System (Audio Power
FM
TUNER
I-
STEREO
DEMOD } LM1800
I
I
AM
TAPE
PREAMP
LM1897
TAPE
PHON0c::l
~
< 10W)
FM
AM/FM IF
LM1866
AMT
l
DOLBY
LMl131
DNR
LM1894
I--
TONE/VOLUME
LM1035
LM1036
LM1040
r--
POWER AMP
LM2879
r«J
M(]
l-
PHONO
PREAMP
LM381
LM382
LM387
TLlXX/OO13-2
Home Component Stereo (Audio Power> 10W)
FM
FM IF
LM1965
TUNER
STEREO
DEMOD
LM1870
~
I AM RF/W I
I LM1863 I
AMT
--
TONE/VOLUME
LM833
LM1035
LM1036
LM1040
I--
POWER AMPS
LM1875
LM391
-n::]
-n::]
lEQUALIZERJ
LMC835
TAPE:>--
~
CAssmE
PREAMP
LM833
LM1897
-1
DOLBY
LMl131
I-
PHONO
PREAMP
LM833
TL/XX/OO13-3
49
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:::J
G>
c
Dolby SIC
l6dS
en
CD
iii
a:
CD
ell
"a
·s
Automotive Radio (Electronically Tuned)
CJ
C
STEREO
DEMOD
LM1870
LM4500
FM
.2
( ,)
ell
'ii
tn
POWER AMPS
LM383
LM2002
LM2005
AUDIO
SWITCH
LM1037
LM1038
AM
0
=s::lI
CC
CASSETTE
PREAMP
LM1837
LM1897
TUXX/OOI3-4
Auto Radio (Manually Tuned)
STEREO
DECODER
LM1870
LM4500
FM
TONE/VOLUME
LM1035
LM1036
LM1040
AM
POWER AMPS
LM383
LM2002
LM2005
CASSETTE
PREAMPS
LM1837
LM1897
TL/XX/OOI3-5
50
:rJ
_
&
O·
National
Semiconductor
Corporation
o
:::;.
n
c
Radio Circuits
Definition of Terms
T
C
CD
S·
::;:
O·
j
AGC dc Output Shift: The shift of the quiescent Ie output
voltage of the AGe section for a given change in AGe central voltage.
-3 dB Limiting Sensitivity: In FM the input signal level
which causes the recovered audio output level to drop 3 dB
from the output level with a specified large signal input.
AGC Figure of Merit: The widest possible range of input
signal level required to make the output signal drop by a
specified amount from the specified maximum output level.
Typical F.O.M. numbers are from 40 dB to 50 dB, for domestic radios and about 60 dB for automotive radios (for
-10 dB output level change).
Lock In Range: That range of frequencies about the free
running frequency for which the phase locked loop will
come into lock if initially starting out of lock.
Maximum Sweep Rate: The maximum rate that the veo
may be made to vary its OSCillating frequency over its
Sweep Range.
Output Resistance: The ratio of the change in output voltage to the change in output current with the output around
zero.
Output Voltage Swing: The peak output voltage swing, referred to zero, that can be obtained without clipping.
AGC Input Current: The current required to bias the central
voltage input of the AGe section.
AM Rejection Ratio: The ratio of the recovered audio output produced by a desired FM signal of specified level and
deviation to the recovered audio output produced by an unwanted AM signal of specified amplitude and modulating
index.
Phase Detector Sensitivity: The change in the output voltage of the phase detector for a given change in phase between the two input signals to the phase detector.
Channel Separation: The level of output signal of an undriven amplifier with respect to the output level of an adjacent
driven amplifier.
Detection Bandwidth: That frequency range about the free
running frequency of the tone decoder/phase locked loop
where a signal above a specified level will cause a detected
signal condition at the output.
Detection Bandwidth Skew: The measure of how well the
detection bandwidth is centered about the free running frequency. It is equal to the maximum detection bandwidth frequency plus the minimum detection bandwidth frequency
minus twice the free running frequency.
Power Bandwidth: The power bandwidth of an audio amplifier is the frequency range over which the amplifier voltage gain does not fall below 0.707 of the flat band voltage
gain specified for a given load and output power.
Power bandwidth also can be measured by the frequencies
at which a specified level of distortion is obtained while the
amplifier delivers a power output 6 dB below the rated output. For example, an amplifier rated a 60W with ":0.25%
THD, would make its power bandwidth measured as the
difference between the upper and lower frequencies at
which 0.25% distortion was obtained while the amplifier was
delivering 30W.
Power Supply Rejection: The ratio of the change in input
offset voltage to the change in power supply voltages producing it.
Slew Rate: The internally limited rate of change in output
voltage with a large amplitude step function applied to the
input.
Supply Current: The current required from the power supply to operate the amplifier with no load and the output at
zero.
Sweep Range: That ratio of maximum oscillating frequency
to minimum operating frequency produced by varying the
central voltage of the veo from its maximum value to its
minimum value with fixed values of timing resistance and
capaCitance.
VCO Sensitivity: The change in operating frequency for a
given change in veo central voltage.
Hold In Range: That range of frequencies about the free
running frequency for which the phase locked loop will stay
in lock if initially starting out in lock.
Input Resistance: The ratio of the change in input voltage
to the change in input current on either input with the other
grounded.
Input Sensitivity: The minimum level of input signal at a
specified frequency required to produce a specified signalto-noise ratio at the recovered audio output.
Input Voltage Range: The range of voltages on the input
terminals for which the amplifier operates within specifications.
large-Signal Voltage Gain: The ratio of the output voltage
swing to the change in input voltage required to drive the
output from zero to this voltage.
51
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o
- -I
CD
.....
3
UI
~NatiOnal
Semiconductor
Corporation
Radio Circuits
Selection Guide
AM RF/IF Detector
Pin
Input
AM
Audio
Internal Meter
Count
Supply Supply Sensitivity
Portable Home Auto Synthesized
Power
and
(Dip
Voltage Current for 20 dB
Detector Output
FMIF Amplifier
Package)
SIN Ratio
LM1863
LM1866
LM1868
LM3820
•
•
•
•
•
•
•
•
•
•
20'
7-16
8.3mA
30,..V
20
3-15
15mA
25,..V
20
4.5-15
22 rnA
12,..V
14
4.5-16
18mA
35,..V
•
•
•
•
•
•
•
•
•
'SO Surface Mount Package Only
Stereo Decoder
Portable Home Auto
LM1800
LM1870
•
LM1884'
LM4500A
•
•
•
•
•
Pin Count
Supply Supply
Dip
Voltage Current
Package
•
•
THO
ARI
High Lamp Output
Interference
Cut Driver Buffer
Rejection
Separation Blend
16
10-18
21 rnA
0.4%
45 dB
20
7-15
26mA 0.05%
45 dB
16
8-16
35mA
0.1%
-
•
•
•
16
8-16
35mA
0.1%
40dB
•
•
•
•
•
•
•
•
·TV Stereo Decoder
Radio Remote Control
Channels
Function
Pin Count
(Dip Package)
Supply
Voltage
Supply
Current
Analog
Digital
Frequency
Range
LM1871
Encoder/Transmitter
18
4.5-15V
14mA
upl06
2
up 10 72 MHz
LM1872
Decoder/Receiver
18
2.5-7V
13mA
2
2
up to 72 MHz
52
FM IF/Detector
Portable
LM1865
LM1965
LM2065
LM1866
LM1868
•
•
Auto
Synthesized
•
•
•
•
•
•
LM3189
•
•
•
•
•
•
LM3089
LM3361At
Home
•
•
•
•
Pin Count
Pin Count
Dip
S.O.
Supply
Voltage
Supply
Current
- 3 dB Limiting
Sensitivity
THD
Mute
AGC
Outputs
20
7.3-16
43mA
60/LV'
20
7.3-16
43mA
60/LV'
0.1%
•
Reverse
•
0.1%
•
•
•
Reverse
•
•
•
20
7.3-16
43mA
60/LV'
0.1%
20
3-15
17mA
12/LV
0.5%
20
4.5-15
19mA
15/LV
1.1%
16
8-16
23mA
12/LV
0.5%
16
8-16
31 mA
12/LV
0.5%
2-9
2.8mA
2/LV
-
16
16
Forward
•
AFC
Meter
Output
AM/
FMIF
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
'Exclusive of 26 dB Buffer
tNarrow·Band FM·IF
..,'"
I
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Cordless Telephone Receiver
AUDIO AMP
LM 1895
LM 38S
LM 389
TLIXXIOOll-l
Portable Radio (Stereo)
FM
AM
TLIXXIOOII-2
Portable Radio (Monaural)
Table/Clock Radio
FM
FM
AM/FM IF
LM 18S8
AM
AM/FM IF
LM 186S
AM
TLIXXIOOII-3
LM 1895
LM 2895
TLIXXIOOII-4
Auto Radio (Manually Tuned)
STEREO
DECODER
LM 1870
LM 4500
FM
TONE/VOLUME
LM 1035
LM 1036
LM 1040
AM
POWER AMPS
LM 383
LM 2002
LM 2005
CASSETTE
PREAMPS
LM 1837
LM 1897
TLlXXIOOII-5
54
,-----------------------------------------------------------------,~
m
Automotive Radio (Electronically Tuned)
c.
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FM
AM
c
POWER AMPS
LM 383
LM 2002
LM 2005
AUDIO
SWITCH
LM1037
LM 1038
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CD
CD
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CD
TL/XX/0011-6
Home Stereo System (Audio Power < 10W)
FM
AM
TONEjVOLUME
LM 1035
LM 1036
LM 1040
POWER AMPS
LM 2879
PHONO
PREAMP
LM 381
LM 382
LM 387
TL/XX/0011-7
Home Component Stereo (Audio Power> 10W)
FM
TONEjVOLUME
LM 833
LM 1035
LM1036
LM 1040
AM
TAPE
POWER AMPS
LM1875
LM 391
CASSETTE
PREAMP
LM 833
LM 1897
TL/XX/0011-8
55
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Video
Definition of Terms
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Aspect Ratio: The ratio of picture width to picture height.
For the NTSC system this is 4:3.
Deep red has more vividness or saturation (less white),
whereas dark red has less brightness. Similar terms are
used to describe non-spectral colors (a mixture of hues).
Color Burst: Normally refers to approximately 9 cycles of
the 3.58 MHz subcarrier superimposed on the back porch of
the compOSite video signal. The phase of this burst establishes the reference color phase for tint or hue, and the
amplitude provides a reference for the color saturation level.
Back Porch: The section of the composite video signal be·
tween the trailing edge of the line (horizontal) sync pulse
and the end of the blanking pulse period (when picture infor·
mation begins). For a monochrome signal the back porch is
simply at the blanking level. For a color signal, the color
burst is added within this section.
Black Level: The DC voltage level in the picture signal
which corresponds to beam cut·off on the display tube. It
can be at the blanking level (given by the back porch) or
slightly higher (7.5% to 10% of the peak white signal above
the blanking level).
Color Subcarrler: A subcarrier at 3.579545 MHz (NTSC)
whose modulation sidebands are added to a monochrome
video Signal to convey the color information. Similar subcarriers are used for SECAM and PAL.
CompOSite Video Signal: The complete video signal. For
monochrome, it consists of blanking and synchronizing signals, with a picture signal representing the scene brightness. For color, an additional subcarrier is added for color
synchronization and picture color content.
Blacker-than-Black: The amplitude region in the composite
video signal that extends below the reference black level in
the direction of the synchronizing pulses.
Blanking: A portion of the composite video signal whose
instantaneous amplitude makes the vertical and horizontal
scan retrace not visible on the display tube.
Compression: An undesired decrease in amplitude of one
portion of the compOSite video signal relative to another
portion.
Contrast: The range of dark and light values in a picture.
Blanking Level: The level of the front and back porches of
the composite video signal.
Blanking Period: The period in the composite video signal
where the level is reduced to the blanking level, below
which the display electron beam is cut-off. This allows non·
visible retrace of the beam from the right side of the display
to the left side at the end of each scan line (horizontal
blanking) and non-visible return of the electron beam from
the bottom of the display to the top. Horizontal blanking
occurs for approximately 11 ,..S between each scan line and
vertical blanking for 1.2 ms between each field.
Cross-talk: An undesired signal interfering with a desired
signal.
Definition: See resolution.
Differential Gain: The amplitude change in the 3.58 MHz
color subcarrier as the picture Signal varies from blanking to
peak white level. This is the result of system non-linearities
and is measured in percent change.
Differential Phase: The phase change, measured in degrees, of the 3.58 MHz color subcarrier as the picture signal
varies from blanking to peak white level.
Blooming: Defocussing of the picture in regions where the
brightness is too high.
Breezeway: The section in the signal blanking period between the end of the sync pulse and the start of the color
burst.
C.C.I.R.: International Radio Consultative Committee-a
worldwide standards organization.
Equalizing Pulses: Pulses of one half the width of the line
(horizontal) sync pulses, transmitted at twice the line rate for
the three line periods before and after the field (vertical)
sync pulse. They are used to help the vertical sync system
of the receiver accommodate the half line difference in the
number of scan lines on successive fields.
Field: One half of a complete picture interval. A field will
contain either all the odd numbered scanning lines or all the
even numbered scanning lines in the picture.
Chromlnance Signal: That part of the NTSC Signal that
contains the color information.
Clamping: A process that established a fixed DC voltage
level for the picture signal. This is important for proper RF
modulation and for maintaining the correct picture black level.
Field Frequency: The rate at which a complete field is
scanned. For NTSC color signals this is nominally 59.94 Hz.
Fly-back: See Horizontal Retrace.
Color: An attribute of an object being scanned that distinguishes it from other objects, apart from shape, texture, and
brightness. In television systems the color of an object is
further subdivided into hue (tint) and saturation. The hue or
tint refers to the dominant wavelength of a spectral color,
i.e., light red is the same hue as deep red and dark red.
Frame: A complete picture consisting of two interlocking
fields.
Frame Frequency: The rate at which a complete frame is
scanned. In the U.S. this is nominally 30 frames or pictures
per second.
56
.-----------------------------------------------------------------------.<
a:
signal. For U.S. television, the audio signal is increased at a
Front Porch: The section of the composite video signal beCD
tween the end of the picture information on a scan line (start
of blanking) and the start of the line synchronization pulse.
6 db/octave rate above 2.1 kHz.
Raster: The area on the face of the display tube that is
scanned by the electron beam. This is not always entirely
visible since commercial receivers employ overscan so that
the edges of the raster are hidden by the faceplate.
Reference Signals: See V.I.T.S. and V.I.R.S.
Resolution (Horizontal): The amount of resolvable detail in
the horizontal direction of the picture. This depends on the
high frequency and phase response of the transmission system and the receiver.
Resolution (Vertical): The amount of resolvable detail in
the vertical direction of the picture. This depends primarily
on the number of scan lines that are used and secondarily
on the size (shape) of the electron scanning beam.
Saturation (Color): The amplitude of the chrominance signal. Increased saturation means increased chrominance
signal level. Visibly, this refers to a color increasing from
pale or pastel to deep.
S.E.C.A.M.: Sequential Couleur Avec Memoire. The color
broadcasting system used predominantly in France which
utilizes sequential transmission of the color difference signals, which are FM modulated on two separate subcarriers
(1967).
Setup: The difference in level between the blanking level
and the reference black level expressed as a percent of the
reference white level.
Horizontal Blanking: The blanking signal at the end of
each scan line that prevents the retrace of the display tube
electron beam from being visible.
Horizontal Retrace: The rapid return of the scanning electron beam from the right side of the raster to the left side.
Horizontal Hum Bars: Relatively broad horizontal bars drifting slowly up the screen as a result of interference from the
60 Hz main frequency.
Hue (Tint): Describes the color that is being represented on
the screen, I.e., red, blue, magenta, green, orange, etc.
Interlace: A scanning process in which each adjacent line
belongs to the alternate field.
I.R.E.: Institute of Radio Engineers. Now combined with the
AlEE to form the IEEE.
I.R.E. Scale: An oscilloscope scale calibrated for composite
video and divided vertically into 140 units. The picture signal
occupies the range from 0 to 100 with syncs in the range 0
to -40.
Luminance: The monochrome or brightness part of the color signal, composed of specific proportions of the three primary colors, red, blue, and green.
N.T.S.C.: National Television System Committee, used in
reference to the system adopted for color television broadcasting in the U.S. at the end of 1953.
Smear: Smear describes a picture condition where objects
appear extended in the horizontal direction producing an iIIdefined, blurry picture. This often occurs when the receiver
is tuned slightly above the proper pix carrier frequency.
Sync: Abbreviation for synchronizing or synchronization.
Noise: In a television picture, 'noise' refers to random interference producing a salt and pepper pattern over the picture. Heavy noise totally obscuring the picture is called
us'now".
Overshoot: An (excessive) response to a unidirectional signal change. Overshoot is often used deliberately to enhance the luminance portion of a signal.
Pairing: A partial or complete failure of interlace in which
scan lines of alternate fields fall in pairs, one on top of the
other.
Pedestal Level: See Blanking Level.
Percentage Sync:
Sync Level: The level of the synchronizing pulse tips.
Vertical Blanking: The blanking signal at the end of each
field starting three lines before the vertical sync pulse.
Vertical Retrace: The return of the electron beam from the
bottom of the display to the top after a complete field has
been scanned.
V.I.R.S.: Vertical Interval Reference Signal. A quality control
signal added to a horizontal scan line during the vertical
blanking period. It is used to provide a chrominance, luminance and black level reference.
V.I.T.S.: Vertical Interval Test Signals. A series of test signals that are added to horizontal lines during the vertical
blanking for in-service testing of the transmission equipment. They can be deleted or added at various pOints in the
transmission link, unlike the VIRS, which is added at program origination and stays with the program material.
Vestlgal Sideband Transmission: A broadcast transmission technique wherein only one side band of an amplitude
modulated carrier is fully transmitted with the other sideband (usually lower) truncated.
Video: The visible portion of the transmitted signal representing the picture.
Video: The ratio in percent of the amplitude of the synchronizing pulse to the peak amplitude of the picture signal between blanking and reference white level. For a
properly constituted composite video signal this is 40%.
RF: The ratio is a percent of the amplitude of the synchronizing pulse to the peak amplitude of the modulated
RF signal. For correct modulation this is 25%.
P.A.L.: Phase Alternation Line. A variation of the NTSC system involving phase reversal of one of the color difference
signals on a line by line basis, introduced into the U.K. and
Germany in 1967.
Picture Signal: That portion of the composite video signal
which is above the blanking level and contains the picture
information.
Pre-emphasis: An increase in the level of a band of frequency components with respect to the remainder of the
57
1
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CD
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3
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~NatiOnal
Semiconductor
Corporation
Video Selection Guide
VIDEO AMPLIFIERS
Gain
Package
Supply Voltage
Comments
LM592
120 MHz
Bandwidth
100,400
14 Pin DIP
14PINSO
±3V-±6V
Differential IN, Differential OUT
LM733
120 MHz
10,100,400
14Pin DIP
±3V-±6V
LM1201
(Advanced Information)
100 MHz
4-10
16PinDIP
+12V
Single Amplifier with
Black Level and Contrast
Control
LM1203
50 MHz
4-10
28 Pin DIP
+12V
Triple Amplifier System
with Black Level and
Contrast Control
LM359
(Note 1)
400MHzGBW
30MHz@Av= 1
14 Pin DIP
5V-22V
Dual Norton Amplifiers
Differential IN, Differential OUT
VIDEO TIMING
Function
Package
Supply Voltage
Comments
-
LM1391
PLL
8 Pin DIP
Internal Shunt Zener
LM1880
No-Holds Vert/Horiz
14Pin DIP
Internal Shunt Zener
LM1881
Sync Separator
8 Pin DIP
8 Pin SO
5V-15V
Outputs Provided:
Composite Sync
Vertical
Burst Gate
Odd/Even Field
VIDEO MODULATORS/DEMODULATORS
Function
Package
Comments
LM1496
(Note 2)
Balanced Modulator-Demodulator
(Modulator-Suppressed Carrier, AM
Demodulator-Synchronous, FM
Phase Detection)
14 Pin DIP
10 Pin TO-5
14PinSO
Operating Frequency to 100 MHz
Balanced Inputs and Outputs
LM1889
Modulates Color Difference,
Luminance, Audio onto
Low-VHF Channels
18 Pin DIP
DC Channel Switching
Chroma Reference
LM2889
Modulates Composite Video,
Audio onto Low-VHF Channels
14PinDIP
DC Channel Switching,
Low Distortion FM Sound
Modulator, Video Clamp
Nate 1: Data sheet in Linear 1.
Nole 2: Data sheet in Linear 3-Special Functions Chapter 5.
58
VIDEO IFs
Application
Package
Comments
LM1211
(Note 3)
Broadband Demodulator
20 Pin DIP
Operating Range 20 MHz-80 MHz
Quasi-Synchronous Detector
25 MHz Output Amplifier
LM1823
Video IF
28 Pin DIP
Operating Range 20 MHz-70 MHz
Synchronous Detector using PLL
9 MHz Output Amplifier
OTHER VIDEO PRODUCTS
Package
Supply Voltage
Comments
LM1044
Video Switch
Function
24 Pin DIP
8V-16V
• DC Switch between 3 Composite Video
Channels or 2 RGB Channels
• 60 dB Channel Separation
LM1884
(Note 4)
TV Stereo Decoder
16Pin DIP
9V-15V
Provides L - R, L + R Outputs
from Composite Input
LM1886
TV Video Matrix D to A
20 Pin DIP
+5V, +12V
Encodes Luminance and Color Difference
Signals from 3-Bit RGB Inputs
Note 3: Data Sheet in Linear 3.
Nole 4: Data Sheet in Linear 3.
r------o~~i~UT
LM1875
LM2005
LM2878
LM2879
'>---OTELEMETRY OUWUT
TI.IXX/OOI2-1
59
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SYNC IN
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VERTICAL / HORIZONTAL SWEEP
AND POWER SUPPLY
CIRCUITS
LIolC555
LM675
SYNC
LM1578
SEPARATION
LM1880
LIol1881
LM1875
H
YOKE
:;:
VIDEO IN
R
G
B
VIDEO AMPLIFICATION
WITH GAIN / DC
CONTROL
LM1201
LIol1203
CONTRAST
BRIGHTNESS
FIGURE 1, Typical RGB Color Monitor Block Diagram
Application Notes* Cross Reference
Device
AN#
LM359
AN·278, AB·24
LM1823
AN·391
LM1886
AN-402
LM1889
AN-402
LM2889
AN·391, AN·402
'National Semiconductor Corporation Linear Application Notes
60
TLfXXfOOI2-2
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~NatiOnal
Semiconductor
. Corporation
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Motion Control Selection Guide
en
CD
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CD
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Dedicated Motor Control Functions
Part Number
Ci)
c
Function
a:
CD
Features
LM621
Brushless D.C. Motor
Deadband Timer for Direction Reversal
40V Max. Operation
35 mA Outputs for Direct Drive of Bipolar Power Transistors
LM628
High Performance Position
Control for D.C. and Brushless
D.C. Motors
On Board 32-Bit Incremental Shaft Encoder Interface
256 }J.s Loop Time
Automatic Trajectory Generator
Velocity Programmable "On-the-Fly"
Internal Programmable PID Filter
Convenient 8-Bit Host Interface
8-Bit or 12-Bit Port to DAC (LM628)
8-Bit PWM Output (LM629)
P.w.M. Controller for
Brushless and Brush D.C. Motors
Flexible Output Structure Drives H-Switches or Commutators
Precision On-Board Reference
Flexible Error Amp/Feedback Structure
LM622
H-Switches
Output Current (Amps)
Device
Peak
(Typical)
Continuous
(Max)
4
2
LM18298
1.5
1
LM18293
Supply
Voltage
(Max)
Full Current
Saturation Voltage
Operating
Temp.
Range
Package
Description
Source
(Max)
Sink
(Max)
50
2.8
2.6
-40'C to + 150'C 15-Pin TO-220 Quad
36
1.8
1.8
-40'Cto + 125'C
Quiescent
Current
Slew
Rate
(Typical)
. Operating
Temp.
Range
50mA
8V/fJos
O'Cto +70'C
16-PinDIP
% H Switch
Dual Full H Switch
Power Op-Amps*
Output Current
Amps
Device
Peak
Continous
(Typical)
(Max)
3
1.5
Input
Supply
Offset
Voltage
Voltage
(Max)
(Max)
LM675
60
10mV
Package
Features
5-Pin TO-220 Thermal Parole
15
10
LM12L
60
15mV
80mA
9V/fJos
-55'Cto + 125'C
4-PinTO-3
Fully Protected
15
10
LM12CL
60
20mV
120mA
9V/fJos
O'Cto +70'C
4-PinTO-3
Fully Protected
15
10
LM12
80
15mV
80mA
9V/}J.s
-55'Cto + 125'C
4-PinTO-3
Fully Protected
15
10
LM12C
80
20mV
120mA
9V/}J.s
O'Cto +70'C
4-Pin TO-3
Fully Protected
1
0.5
LM18272
28
100mV 15 mA(Typ) 0.5V/fJos
O'Cto +85'C
8-PinDIP
Dual (Bridge)
·For more information on Power Amps, see the Amplifier section of the Linear Databook. For more High Power Amplifiers, refer to the Audio Amplifier section.
61
~NatiOnal
Semiconductor
Corporation
Building Blocks
Communications-Related Building Blocks
Modulators & Demodulators Selection Guide
LM1211
LM1496
LM1889
LM2889
Typical
Application
Broadband
Demodulator
Balanced ModulatorDemodulator
TV Video
Modulator
TV Video
Modulator
Key
Features
• Configurable
for AM orFM
Based Signals
• Wide Frequency
Response to
100 MHz
• Input Signals
-Audio Modulation
-Color Difference
-Luminance
• Input Signals
-Audio
-Composite Video
• 0 MHz-70 MHz Operating
Frequency Range
• Fully Balanced
Inputs and Outputs
• 25 MHz Detector
Output Bandwidth
• Adjustable Gain
and Signal Handling
• Channel 3
(61.25 MHz) or
Channel 4
(67.25 MHz) Output
• Companion Circuit
toLM1BB6TV
Video Matrix
DtoA
• Linear Output
Phase Response
• Channel 3
(61.25 MHz) or
Channel 4
(67.25 MHz) Output
• Video DC
Restoration
PLL's AND TONE DECODERS
General purpose PLL's and tone decoders are available for applications that include FSK demodulation, tone decoding, SAP
and SCA demodulation, and telemetry reception. Both bipolar and CMOS devices are offered. Special purpose PLL's for TV
synchronization and FM stereo demodulation are also available for use in other low frequency signal processing applications.
PLL and Tone Decoder Selection Guide
LM565
LM567
LMC567*
(CMOS LM567)
LMC568
Typical
Application
PLL
Tone
Decoder
Tone
Decoder
PLL
Center Frequency
Range
15Hz500kHz
0.01 Hz500kHz
0.01 Hz500kHz
0.01 Hz500 kHz
VCO Control Range
±30%
±7%
±7%
±30%
LM1391
LM1800, LM1870,
LM4500A
TV-Horizontal
PLL
FMStereo
Demodulator PLL
±300 Hz
Supply Voltage
±5Vto ±12V
4.75V-9V
2V-9V
2V-9V
BV-9.2V
BmA
12mA
O.BmA
1.2mA
20 rnA
Supply Current (Typ)
Lowest:7V
Highest: 16V
(See Datasheets)
Lowest: 21 rnA
Highest: 45 rnA
(See Datasheet)
'The CMOS LMC567 oscillator runs at twice the frequency of the bipolar LM567 oscillator. Refer to the datasheets for additional Information.
62
m
c
POWER LINE CARRIER
The LM2893/LM1893 Carrier-Current Transceiver performs as a power line interface for half-duplex (bi-directional) communication of serial bit streams of virtually any coding. Applications include energy management systems, inter-office control, fire alarm
systems, security systems, telemetry, and remote meter reading.
TIMERS
General purpose timers are available for generating accurate time delays or oscillation. Both bipolar and CMOS devices are
offered.
Timer Selection Guide
LM322
Trigger Pulse Relative
to Output Pulse
Can Be
Longer
LM2905
LM555
Can Be
Longer
LMC555·
(CMOS LM555)
Must Be
Shorter
Must Be
Shorter
LM556
(Dual LM555)
Must Be
Shorter
Typical Application
Monostable
Monostable
Astable
Astable
Astable
Supply Voltage
4.5V-40V
4.5V-40V
4.5V-15V
1.2V-12V
4.5V-15V
Supply Current
(Typical)
2.5mA
2.5mA
10mA
0.15mA
10mA
(Each Timer Section)
·The CMOS LMC555 can handle -lOrnA 10 + 50 rnA 01 oulpul currenl and Ihe bipolar LM555 can handle up 10 ± 200 rnA 01 outpul current.
VCO AND FUNCTION GENERATOR
The LM566 is a general purpose voltage controlled oscillator which may be used to generate square and triangle waves. Typical
applications include FM modulation, signal generation, function generation, frequency shift keying, and tone generation. The
LM566 has very linear modulation characteristics.
Drive-Related Building Blocks
DISPLAY DRIVERS
LED flasher/oscillator and dot/bar display drivers are offered.
Display Driver Selection Guide
LM3914
LM3915
LM3916
Typical
Application
Flasher/
Oscillator
Dot/Bar
Display Driver
Dot/Bar
Display Driver
Dot/Bar
Display Driver
Display Scale
N/A
Linear
Log
VU Meter
Display Type
LED,
Incandescent
LED, LCD,
Vacuum
Fluorescent
LED, LCD,
Vacuum
Fluorescent
LED, LCD,
Vacuum
Fluorescent
LM3909
METER DRIVERS
The LM1819 Air-Core Meter Driver is a function generator/driver for air-core (moving-magnet) meter movements in tachometers
and ruggedized instruments. Driver outputs are self-centering and belter than 2% linearity is guaranteed over a full 305·
deflection range. Signal conditioning circuitry is included on chip.
TEMPERATURE CONTROLLER
The LM3911 (Note 1) is a temperature controller containing a precision temperature sensor, op amp, and reference. It is
designed for temperature sensing and closed loop temperature control applications over the -25·C to +85·C range.
Note 1: See Unear 2 lor datasheet.
63
a:5'
ea
m
&
Precision-Related Building Blocks
CHOPPER BLOCK
The LMC669 Auto Zero Block (Note 1) is a universal com mutating auto-zero block that can be used with any operational
amplifier to correct offset voltage.
Note 1: See Unear 2 for dalasheet.
TRANSISTOR ARRAYS
A variety of matched and power transistors are offered.
Transistor Array Selection Guide
LM394
LM395
LM3046
Description
NPN Transistor Pair
Power Transistor
Key Features
• Emitter-Base
Voltage Matched
to 50,...V
• Collector Current: 1A
• Current Gain
Matched to 2%
• Quiescent Current:
10mA
• Switching Time:
2,...s
5 NPN Transistors
LM3146
5 NPN Transistors
• Emitter-Base
Voltage Matched
to ±5mV
• Emitter-Base
Voltage Matched
to ±5mV
• Breakdown Voltages
-V(BR)(CBO): 20V
-V(BR)(CEO): 15V
-V(BR)(CIO): 20V
-V(BR)(EBO): 5V
• Breakdown Voltages
-V(BR)(CBO): 40V
-V(BR)(CEO): 30V
-V(BR)(CIO): 40V
-V(BR)(EBO): 5V
·DC-120MHz
• DC-120 MHz
• Current Limit
• Thermal Limit
• Safe Area
Protection
Sensing-Related Building Blocks
LIQUID LEVEL SENSORS
A variety of liquid level sensing circuits are offered.
Liquid Level Sensor Selection Guide
LM903
Output
Type
Digital HIILO
Operation
Method
Thermoresistive
Probe
LM1812
LM1830
Analog
Pulse-Echo
Timing
Digital HIILO
Thermoresistive
Probe
Acoustic
Transducer
Conductive
Liquid
LM1042
64
m
5.
SPECIAL AMPLIFIERS
a::
S·
A variety of special sensor amplifiers are offered.
CD
Special Amplifiers Selection Guide
m
LM1815
Typical Application
LM1964
Adaptive Sense Amplifier
Sensor Interface Amplifier
Sensor
Inductive Pickup
Lambda Sensor
Key Features
- Operates from
2.5V to 12V Supply
- Normal Operation Guaranteed
with Inputs up to 3V Below
Ground on a Single Supply
- Adaptive Hysteresis
- Fully Protected Inputs
- True Zero Crossing
Timing Reference
- Input Open Circuit
Detection
SPECIAL COMPARATOR
The LM1801 Battery Operated Power Comparator is an extremely low power comparator with a high current, open collector
output stage. Typical applications include intrusion alarms, water leak detectors, gas leak detectors, overvoltage crowbars and
battery operated monitors. The LM1801 is designed to operate in a standby mode for 1 year, powered by a 9V alkaline battery.
SPECIAL CONVERTERS
A variety of special converters for signal transformation applications are offered.
Special Converters Selection Guide
LH0091 (Note 1)
Converter
Type
True RMS-to-DC
Key
Features
- 0.1 % Accuracy with
External Trim
- Uncommitted Amplifier
for Filtering, Gain
or High Crest
Factor Configuration
- True RMS Conversion
LH0094 (Note 1)
Multifunction
- OUT=
INYC~~)m,
0.1 s: m s: 10,
m Continuously
Adjustable
LM331 (Note 1)
Frequency-toVoltage
-1 Hz to 100kHz
Frequency Range
- Operates Relay,
Lamp or Other Load
when Input Exceeds
a Selected Rate
- Split or Single
Supply Operation
- Applications
-Precision Divider,
Multiplier
-Square Root
-Square
-Trigonometric
Function Generator
-Companding
-Linearization
-Control Systems
-Log Amp
LM2907, LM2917
Voltage-toFrequency
- Ground Referenced
Tachometer Fully
Protected from Damage
Due to Swings
Above Supply or
Below Ground
Nota 1: See Linear 2 for datasheets.
ULTRASONIC TRANSCEIVER
The LM1812 Ultrasonic Transceiver is a general purpose ultrasonic transceiver designed for use in a variety of ranging, sensing,
and communications applications. Typical uses include liquid level measurement, sonar, surface profiling, data links, hydroacoustic communications, non-contact sensing and industrial process control. Depending on the acoustic transducer, typical
performance capabilities include 5 feet to 100 feet in water and 4 inches to 35 feet in air.
65
0'
n
~
Section 1
Active Filters
II
Section 1 Contents
Active Filters Definition of Terms .....................................................
Active Filters Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AF100 Universal Active Filter ........................................•.............•.
AF150 Universal Wideband Active Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AF151 Dual Universal Active Filter. . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LMF60 6th Order LMCMOSTM Switched Capacitor Butterworth Lowpass Filter .............
* LMF90 4th-Order LMCMOSTM Programmable Elliptic Notch Filter. . . . . . . . . • . . . . . . . . . . . . . . .
* LMF100 Universal Monolithic Dual Switched Capacitor Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
* LMF120 Mask Programmable Switched Capacitor Filter... ... ..... ..... .•... ............
MF4 4th Order Switched Capacitor Butterworth Lowpass Filter.. ..... ... .. ... .. .... .... ..
MF5 Universal Monolithic Switched Capacitor Filter.......... .. ......... ......... .......
MF6 6th Order Switched Capacitor Butterworth Lowpass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . .
* MF8 4th Order Switched Capacitor Bandpass Filter.. .... .. ... .. ... .... ...... ...... .... .
MF10 Universal Monolithic Dual Switched Capacitor Filter...............................
"Devices Not Covered In Last Publication
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
1-12
1-13
1-26
1-41
1-59
1-81
_
~
National
~-
Semiconductor
Corporation
."
;:
1-
Active Filters
Definition of Terms
CD
S'
::i:
o·
::::lI
-...
o
'12
fCLK: the switched capacitor filter external clock frequency.
HOHp: the gain in (V IV) of the highpass output of each
fo: center of frequency of the second order function com-
MF10 as f --+ fCLK/2.
plex pole pair. fo is measured at the bandpass output of
each '12 MF10, and it is the frequency of the bandpass peak
occurrence.
Qz: the quality factor of the 2nd order function complex zero
pair, if any. (Oz is a parameter used when an allpass output
is sought and unlike 0 it cannot be directly measured).
Q: quality factor of the 2nd order function complex pole pair.
fz: the center frequency of the 2nd order function complex
zero pair, if any. If fz is different from fo, and if the Oz is
quite high it can be observed as a notch frequency at the
allpass output.
o is also measured at the bandpass output of each '12 MF10
and it is the ratio of fo over the -3 dB bandwidth of the 2nd
order bandpass filter. The value of 0 is not measured at the
lowpass or highpass outputs of the filter, but its value relates to the possible amplitude peaking at the above outputs.
fnotch: the notch frequency observed at the notch output(s)
of the MF10.
HON1: the notch output gain as f --+ 0 Hz.
Hosp: the gain in (V IV) of the bandpass output at f = fo.
HOLP: the gain in (VIV) of the lowpass output of each
~
3
til
HON2: the notch output gain as f --+ fCLK/2.
'12
MF10 at f --+ 0 Hz.
II
1-3
~NatiOnal
Semiconductor
Corporation
Active Filter Selection Guide
Device #
Type
MF10(S, T)
Universal
Bandpass
MF8(T)
Max
Order
Accuracy
Freq
Range
Typ.Q
Accuracy
Max
FxQ
Universal
4th
±O.S%
0.1-30 kHz
±2%
200 kHz
Chebyshev
Butterworth
4th
±1.0%
0.1-20 kHz
±2%
5MHz
Function
Max Freq
MF6(S,n
Lowpass
Butterworth
6th
±1.0
0.1-20 kHz
N/A
N/A
MF5(S)
Universal
Universal
2nd
±1.0%
0.1-30 kHz
±6%
200kHz
MF4(S)
Lowpass
Butterworth
4th
±O.S%
0.1-20 kHz
N/A
N/A
*LMF100
Universal
Universal
4th
±O.S%
40kHz
±2%
1.8 MHz
*LMFSO
Lowpass
Butterworth
Sth
±O.S%
40kHz
N/A
N/A
S Surface Mount Available
T Extended Temperature Available
, Advance Information
1-4
l>
....o'TI
~National
o
~ Semiconductor
AF100 Universal Active Filter
General Description
Features
The AF100 state variable active filter is a general second
order lumped RC network. Only four external resistors are
required to program the AF100 for specific second order
functions. Lowpass, highpass, and bandpass functions are
available simultaneously at separate outputs. Notch and allpass functions are available by summing the outputs using
the uncommitted output summing amplifier. Higher order
systems are realized by cascading AF100 active filters.
Any of the classical filter configurations, such as Butterworth, Bessel, Cauer, and Chebyshev can be implemented.
•
•
•
•
•
•
•
•
•
•
•
Military or commercial specifications
Independent Q, cutoff frequency
Low sensitivity to external component variation
Separate lowpass, high pass, bandpass outputs
Inputs may be differential, inverting, or non-inverting
Allpass and notch outputs may be formed using the uncommitted amplifier
Operates to 10kHz
Q range to 500
Power supply range
± 5V to ± 18V
Frequency accuracy
± 1% unadjusted
Q frequency product ,;; 50,000
Connection Diagrams
Ceramic Dual-In-Line Package
NO
PIN
NO
PIN
INT I
BANDPASS
OUTPUT
-v
Plastic Dual-In-Line Package
AMP
OUTPUT
INT I
BANDPASS HIGHPASS
OUTPUT OUTPUT
INPUT
INPUT
lOOk
II
INPUT
INPUT HIGHPASS
OUTPUT
+V
lOWPASS AMP
OUTPUT + INPUT
TOP VIEW
INT 2
-v
NO
PIN
TLlH/5642-1
AMP
AMP
+ INPUT -INPUT
GNO
AMP
OUTPUT
+V
INT 2
lOWPASS
OUTPUT
TOP VIEW
'Note: Internally connected. Do not use.
AF100-1CJ, AF100-2CJ
See NS Package Number HV13A
AF100-1CN, AF100-2CN
See NS Package Number N16A
1-5
TL/H/5642-2
C) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
....
Il)
cc ~National
~
~ Semiconductor
AF150 Universal Wideband Active Filter
General Description
Features
The AF150 wide band active filter is a general second order
lumped RC network. Only four external resistors are required to program the AF150 for specific second order functions. Low pass, high pass and band pass functions are
available simultaneously at separate outputs. Notch and all
pass functions can be formed by summing the outputs using
an external amplifier. Higher order filters are realized by cascading AF150 active filters.
•
•
•
•
•
•
•
•
•
Independent Q cutoff frequency
Low sensitivity to external component variation
Separate low pass, high pass, band pass outputs
Inputs may be differential, inverting or non-inverting
All pass and notch outputs may be formed
Operates to 100 kHz
Q range to 500
±5V to ±18V
Power supply range
± 1% unadjusted
High accuracy
2X10 5
• Q frequency product
Any of the classical filter configurations, such as Butterworth, Bessel, Cauer and Chebyshev can be implemented.
Connection Diagram
Ceramic Dual-In-Line Package
NO
PIN
NO
PIN
INT 1
BANDPASS
OUTPUT
-v
GND
10
INPUT
INPUT HIGHPASS
OUTPUT
+V
INT2
TOP VIEW
Order Number AF150-1CJ or AF150-2CJ
See NS Package HY13A
'Note: Internally connected. DO NOT USE.
1-6
NO
PIN
TLlH/5643-1
):0
."
.....
U1
.....
~National
~ Semiconductor
AF151 Dual Universal Active Filter
General Description
Features
The AF151 consists of 2 general purpose state variable active filters in a single package. By using only 4 external resistors for each section, various second order functions may
be formed. Low pass, high pass and band pass functions
are available simultaneously at separate outputs. In addition, there are 2 uncommitted operational amplifiers which
are available for buffering or for forming all pass and notch
functions. Any of the classical filter configurations, such as
Butterworth, Bessel, Cauer and Chebyshev can be easily
formed.
•
•
•
•
•
•
•
•
Independent Q, frequency and gain adjustment
Very low sensitivity to external component variation
Separate low pass, high pass and band pass outputs
Operation to 10kHz
Q range to 500
Wide power supply range-±5V to ±18V
Accuracy-± 1 %
Fourth order function in one package
Circuit Diagrams (Unlisted pins are not connected.)
lOOk
1000 pF
10k
1000 pF
6~5
7~
>-....-04
21..,............,...,.
LOW PASS
OUTPUT
8
lOOk
24
1
'::'
12
20
Y
Y
Y
v+
v+ v-
lOOk
1000 pF
10k
II
1000 pF
15
'>"'-016
LOW PASS
OUTPUT
18:t>-o
19
17
+
lOOk
TLlH/5644-1
Ceramic Dual-In-Line Package
Order Number AF151-1CJ or AF151-2CJ
See NS Package Number HY24A
1-7
C)
CD
II.
:5
r--------------------------------------------------------------------------------,
~ National
ADVANCED INFORMATION
Semiconductor
Corporation
LMF60 6th Order LMCMOSTM Switched
Capacitor Butterworth Lowpass Filter
General Description
Features
The LMF60 is a high-performance precision 6th Order Butterworth lowpass active filter. It is fabricated using National's LMCMOS process, which is an improved silicon-gate
CMOS process specifically designed for analog products.
Switched capacitor techniques eliminate external component requirements and allow a clock tunable cutoff frequency. The ratio of the clock frequency to the lowpass cutoff
frequency is internally set to 50 to 1 (LMF60-50) or 100 to 1
(LMF60-100). A Schmitt trigger clock input stage allows
two clocking options, either self-clocking (via an external
resistor and capacitor) for stand-alone applications, or for
tighter cutoff frequency control, a TTL or CMOS logic compatible clock can be directly applied. The maximally flat
passband frequency response together with a DC gain of 1
VIV allows cascading LMF60 sections for higher order filtering. In addition to the filter, two independent CMOS op amps
are included on the die and are useful for any general signal
conditioning applications.
•
•
•
•
•
•
•
•
Low DC offsets (less than 20 mV typical)
Low clock feedthrough (5 mV typical)
Cutoff frequency accuracy of ±0.3%
Cutoff frequency range of 0.1 Hz to 25 kHz
Two uncommitted op amps available
5V to 14V operation
Cutoff frequency set by external or internal clock
No external components
The LMF60 is pin-compatible with tlie MF6.
Block and Connection Diagrams
Dual-In-Line Package
FlIJER~--".L~1
N.lNn
14
INY2
Vaz
11
INVI
INLJ~~I
Vas
ASND
ADJ
FlIJER
LB~
OUT
¥tI
CLMR
V-
AIIND
INVZ
cue
CLM
IN
V'
FILlER
IN
VoaADJ
IN
N.INVZ
TUH/9294-2
Top View
cue.
U~
y.
,TL/H/9294-1
1-8
.-------------------------------------------------------------------------, r
_
National
Semiconductor
Corporation
ADVANCED INFORMATION
s:::
."
CD
o
LMF90 4th-Order LMCMOSTM Programmable
Elliptic Notch Filter
General Description
Features
The LMF90 is a fourth-order elliptiC notch (band-reject) filter
based on switched-capacitor techniques. No external components are needed to define the response function. The
depth and width of the notch are set using two separate
three-level logic inputs. Three different notch depths and
three different ratios of notch width to center frequency may
be programmed by connecting these pins to V+, ground, or
V-. Another three-level logic pin sets the ratio of clock frequency to notch frequency.
• Center frequency set by external clock or on-board
oscillator
• No external components needed to set response
characteristic
• Notch bandwidth, attenuation, and c1ock-to-center
frequency ratio independently programmable
• Reduced aliasing compared to other switched-capacitor
filter topologies
Key SpeCifications
An internal crystal oscillator is provided. Used in conjunction
with a low-cost color TV crystal and the internal logic divider, a notch filter can be built with center frequency at 50 Hz,
60 Hz, 100 Hz, 120 Hz, 150 Hz, or 180 Hz. Several LMF90s
can be operated from a single crystal. An additional input is
provided for an externally-generated clock signal.
•
•
•
•
•
•
•
fo range:
0.1 Hz to 30 kHz
Supply range:
4V to 14V
Passband ripple:
0.25 dB
Attenuation at fo:
30 dB, 40 dB or 50 dB
felK: fo ratio: 100:1, 50:1, or 33.33:1
Notch bandwidth:
0.1 fo, 0.2 fo, or 0.4 fo
fo accuracy over full temperature range:
± 1%
Typical Application and Connection Diagrams
60 Hz Notch Filter
+5V
Your
W
v+
GND
Y,N1
LMF90
Y,N2
D
YOUT
YTL/H/9268-14
LD
XTAL2
XTALI
4
5
0
eLK
XLS
+5V
3.57945 MHz
TLlH/9268-1
1-9
a
C)
C)
.,...
LI.
:!!
...I
r----------------------------------------------------------------------------,
~ Semiconductor
NatiOnal
ADVANCED INFORMATION
Corporation
LMF100 Universal Monolithic Dual LMCMOSTM
Switched Capacitor Filter
General Description
The LMF100 consists of two independent general purpose
high performance switched capacitor filters. With an external clock and 2 to 4 resistors, various second order filtering
functions can be realized by each filter block. Each block
has three outputs. One output can be configured to perform
either an allpass, highpass or a notch function. The other
two outputs perform bandpass and lowpass functions. The
center frequency of each filter can be tuned by an extemal
clock or by both an external clock and an external resistor
ratio. Up to a 4th order biquadratic function can be realized
with a single LMF100. Higher order filters are implemented
by simply cascading additional packages and all the classical filters (such as Butterworth, Bessel, Cauer and Chebyshev) can be realized.
The LMF1 00 is fabricated on National Semiconductor's high
performance analog silicon gate CMOS process,
LMCMOS. This allows for the production of a very low offset, high frequency filter building block.
Features
• Wider power supply range: 4V to 14V
• Operation up to 100 kHz
• Low offset voltages (50:1 or 100:1 mode)
typically VOSI = ±5 mV
VOS2 = ±10 mV
VOS3 = ±15 mV
• Low crosstalk
• Clock to center frequency ratio accuracy ±0.3%
• fo X Q up to 1.8 MHz
• Pin-compatible with the MF10
System Block Diagram
~NDLJ~------t---------Qf
6
5O/1DD
+-Os.
CDNTRDL
I
LSb
eLKs
TO ~ND +-------_~-------c,.
INV.
Vi
Vi N/AP/HPa SI.
TUH/9266-1
1-10
r-
s:::
4th Order Butterworth Lowpass Filter
."
......
IN
39KA
2
19
3
18
100KA
4
17
5
16
51K.o.
LMF100
6
-5V
CI
CI
OUT
20
47KA
51K.o.
24.9 KA
15
8
+5V
12
+5V
11
3.5MHz
TL/H/9266-2
10
0
-10
V +) the absolute value of current at that pin should be lim~ed
to 5 mA or less. The 20 mA package input current limns the number of pins that can exceed the power supply boundaries ~h a 5 mA current limit to four.
Note 15: Thermal Resistance
9JA
(Junction to Ambient) N Package .••.....•. • 105"C/W.
9JA
M Package •.............................. 95"C/W.
1-16
Typical Performance Characteristics
4.0
<'
3.6
~
3.2
~
a
i
~
Power Supply Current
vs Power Supply Voltage
TA =25OC .1,
II
:1
§
i
1/
V
/
3.4
a
I
~
2A
1.6
/
I
2.B
2.0
L
FCLK =250kHz
Power Supply Current
vs Clock Frequency
~
~
V
Iv
3.2
[....1"
3.0
,.. '"
2.6
2A
2.2 ~
/
1.6
_I--'
,
~
FCLK =250kHz
RLOAO = 10 k!l
II I I
~
"-
2.5 3.0 3.5 4.Q 4.5 5.0 5.5 6.0 6.5 7.0
POWER SUPPLY VOLTAGE(tV)
..:
0.1
1\
\ I
\
0.0
,....
,.-
125
-1
1
-3
-4
.......
-5
1
l!i
.....
r- TAMF4-100
1+2~OC
100
-15
25
B5
125
TEMPERATURE (OC)
fClKlfe Deviation
vs Power Supply Voltage
TA=25OC_~
FClJ(= 250 kHz
MF4- 50
0.2
0.1
,..
\
\
I-
2.5 3.0 3.5 4.Q 4.5 5.0 5.5 6.0 6.5 7.0
POWER SUPPLY VOLTAGE (tV)
POWER SUPPLY VOLTAGE (:tV)
fClKlfe Deviation
vs Temperature
0.6
Vs =:t5.0V"
1
V
-0.2
16
14
12
10
/
1- I
-2
"
,
3.80
V
2.5 3.0 3.5 4.Q 4.5 5.0 5.5 6.0 6.5 7.0
vs Clock Frequency
I- I'-Vs=t2·5V~
-- -
./
-0.1
fClKlfe Deviation
1/1'"
125
V
0.0
vs Clock Frequency
1
B5
I
FCLK =250kHz
RLOAO = 10k!l
-55
i.--'
",
fClK/fe Deviation
-,
-- -
25
Vs =:ts.OV
I--c-
4.QO
3.B5
TA =25ocL
FClK = 250 kHz
MF4-100
TEMPERATURE(OC)
M
4.G5
ii!
-0.1
B5
4.10
3.90
-0.2
25
-15
D.3
0.2
~ -4.55
-15
4.15
fClKlfe Deviation
vs Power Supply Voltage
/
-55
""N...
4.20
~
D.3
~
~ -4.50
..... Vs =t2.5V
1.6
1.4
3.95
"-
POWER SUPPLY VOLTAGE(tV)
~ -4.45
1.8
~
!=
2.5 3.0 3.5 4.Q 4.5 5.0 5.5 6.0 6.5 7.0
RLOAD= 10kfi
'--
Positive Voltage Swing
vs Temperature
'"
"- r'\
"
TEMPERATURE (OC)
z
"-
VS =t5.0V
.
-55
2
TA:;: 25°
Negative Voltage Swing
vs Temperature
-4.40
2A
2.2
2.0
Negative Voltage Swing
vs Power Supply Voltage
/
'"z~
I
to-...
2.6
1000
500
I'..
CLK
FeLK = 250 kHz
,
2.B
1.2
V
V~F =~5VJ
••1.
= 250 kHz
,
3.0
CLOCK FREQUENCY(kHz)
I'
~ -4.35
I I
100
V
-4.30
'"~
Vs =t2.5V
/
/
I
e;
1.8
Positive Voltage Swing
vs Power Supply Voltage
V
:1
;;:
POWER SUPPLY VOLTAGE (t V)
J I
3.2
~
2.0
2.5 3.0 3.5 4.Q 4.5 5.0 5.5 6D 6.5 7.0
TA=250
TA=25OC
Vs=t5.0V
2.B
1.4
t- FCLK =250kHZ
t- RLOAD=10k!l
Power Supply Current
vs Temperature
,
1\
1
~
"
0.4
MF4- 50
TA=+25OC
l!i
8
0
-2
-4
-
r- Ii
Vs =:t:2.SV
r-
f- -
_~=t5.0V
-,.....
t--
MF4-1001
1
FeLK;; 250 kHz
0.2
~
"
0.0
-0.2
VS=:t5.0~
~.
.
!'.Vs =:t2.5V
1'\ ,,
-0.4
-0.6
,
-0.8
-1.0
500
CLOCK FREQUENCY(kHz)
1000
100
500
CLOCK FREQUENCY(kHz)
1000
-55
-15
25
B5
125
TEMPERATURE(OC)
TLiH/5064-9
1·17
II
Lf
::::E
Typical Performance Characteristics
DC Gain Deviation
vs Power Supply Voltage
fCLKlfc Deviation
vs Temperature
0.3
o:l
_
~'"J
,
-0.1
0.04
,
WF4-50 I
fCLK=250kH
0.1
0.0
'CD' 0.02
~ 0.01
/v:ltJ.ov
IS I I
i
u
\VS= t2.5V
-<12
1"\
-0.3
,
-oA
-o.s
-55
-15
25
~
g
.
B5
~
-0.02
!
i
:!:
<1
g -0,08
-0.1
-0.03
g
I.A
t-
-0.04
2.5 3.D 3.5 4.0 4.5 5.D 5.5 6.0 6.5 7.0
POWER SUPPLY VOLTAGE (tV)
POWER SUPPLY VOLTAGE (tV)
I
0.12
!
,
1\
\
III
~
,
~
g
, ,-
I
I
0.10
0,08
,
,
~F4-100
fClK = 250 kHz
,
,
0.06
0.04
0.02
-~ !.,-,-VS = t2.5V
-
h
'--r-
Vs =t5.0V
-o.D2
25
~PERAT1JRE
I
I
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.D
~Vs=1:5.0V
-15
"0.03
i-"
DC Gain Deviation
vs Temperature
- 4 l
r-I- ~ v~I=t2.5V\ I\.
I
I
,...
f-
-O.DS
DC Gain Deviation
vs Temperature
~~! :5~5OkH!
~F4-50-
~ -0.D2
-0.05
I
I
TA=25OC _I.
fCLK2 = 250 kHz
0.02
~ -0.01
I
I
II
-0.02
125
-55
~
~
-0.Q1
-0.04 i-
-0.04
-o.os
0.D4
0.D3
~ 0.01
TEWPERATURE (OC)
o
DC Gain Deviation
vs Power Supply Voltage
TA=25OC.I.
fCLK = 250 kHz
WF4-100 -
0.1)3
,'f
1'\
(Continued)
B5
-55
125
-15
25
~PERAT1JRE
(OC)
B5
'.
125
(OC)
TL/H/5064-10
1-18
50:1) of the clock frequency supplied to the filter. Internal
integrator time constants set the filter's cutoff frequency.
The resistive element of these integrators is actually a capacitor which is "switched" at the clock frequency (for a
detailed discussion see Input Impedance Section). Varying
the clock frequency changes the value of this resistive element and thus the time constant of the integrators. The
clock-to-cutoff-frequency ratio (fCLKfcl is set by the ratio of
the input and feedback capacitors in the integrators. The
higher the clock-to-cutoff-frequency ratio the closer this approximation is to the theoretical Butterworth response. The
MF4 is available in fCLK/fc ratios of 50:1 (MF4-50) or 100:1
(MF4-100).
Pin Descriptions
(Numbers in ( ) are for 14-pin package.)
PIn
PIn
Function
#
Name
ClKIN A CMOS Schmitt-trigger input to be used
1
(1)
with an external CMOS logic level clock.
Also used for self clocking Schmitt-trigger
oscillator (see section 1.1).
2
ClK R A TTL logic level clock input when in split
(3)
supply operation (± 2.5V to ± 7V) with L. Sh
tied to system ground. This pin becomes a
low impedance output when L. Sh is tied to
V - . Also used in conjunction with the ClK
IN pin for a self clocking Schmitt-trigger
oscillator (see section 1.1). The TTL input
signal must not exceed the supply voltages
by more than 0.2V.
3
L. Sh level shift pin; selects the logic threshold
(5)
levels for the clock. When tied to V- it
enables an internaltri-state buffer stage
between the Schmitt trigger and the internal
clock level shift stage thus enabling the
ClK IN Schmitt-trigger input and making the
ClK R pin a low impedance output. When
the voltage level at this input exceeds 25%
(V+ - V-I + V- the internal tri-state
buffer is disabled allowing the ClK R pin to
become the clock input for the internal
clock level-shift stage. The ClK R threshold
level is now 2V above the voltage on the L.
Sh pin. The ClK R pin will be compatible
with TTL logic levels when the MF4 is
operated on split supplies with the L. Sh pin
connected to system ground.
5
(8)
1.1 CLOCK INPUTS
The MF4 has a Schmitt-trigger inverting buffer which can be
used to construct a simple RIC oscillator. Pin 3 is connected to V- which makes Pin 2 a low impedance output. The
oscillator's frequency is nominally
1
(1)
fCLK = -R-C-In-[.(T.V-:-C-C----:-V:-t-....,);--;(~~:-+....,):-;"]
VCC - Vt +
1
fCLK "" 1.69 RC
(1a)
forVcc = 10V.
Note that fCLK is dependent on the buffer's threshold levels
as well as the resistorlcapacitor tolerance (see Figure 1).
Schmitt-trigger threshold voltage levels can change significantly causing the RIC oscillator's frequency to vary greatly
from part to part.
Where accurate cutoff frequency is required, an external
clock can be used to drive the ClK R input of the MF4. This
input is TTL logic level compatible and also presents a very
light load to the external clock source (- 2 JIoA). With split
supplies and the level shift (L. Sh) tied to system ground,
the logic level is about 2V. (See the Pin Description for L.
Sh).
FILTER The output of the low-pass filter. It will
OUT
typically sink 0.9 mA and source 3 mA and
swing to within 1V of each supply rail.
AGND The analog ground pin. This pin sets the DC
bias level for the filter section and must be
tied to the system ground for split supply
operation or to mid-supply for single supply
operation (see section 1.2). When tied to
mid-supply this pin should be well
bypassed.
7,4 V+, V- The positive and negative supply pins. The
(7, 12)
total power supply range is 5V to 14V.
Decoupling these pins with 0.1 JIoF
capacitors is highly recommended.
6
(10)
8
(14)
Vt -
which, is typically
1.2 POWER SUPPLY
The MF4 can be powered from a single supply or split supplies. The split supply mode shown in Figure 2 is the most
flexible and easiest to implement. Supply voltages of ± 5V
to ± 7V enable the use of TTL or CMOS clock logic levels.
Figure 3 shows AGND resistor-biased to V+ 12 for single
supply operation. In this mode only CMOS clock logic levels
can be used, and input signals should be capacitor-coupled
or biased near mid-supply.
1.3 INPUT IMPEDANCE
The MF4 low-pass filter input (FILTER IN) is not a high impedance buffer input. This input is a switched-capacitor resistor equivalent, and its effective impedance is inversely
proportional to the clock frequency. The equivalent circuit of
the filter's input can be seen in Figure 4. The input capacitor
charges to Yin during the first half of the clock period; during
the second half the charge is transferred to the feedback
capacitor. The total transfer of charge in one clock cycle is
therefore
= CinYin, and since current is defined as the
flow of charge per unit time, the average input current becomes
FILTER The input to the low-pass filter. To minimize
IN
gain errors the source impedance that
drives this input should be less than 2K (see
section 3). For single supply operation the
input signal must be biased to mid-supply or
AC coupled through a capacitor.
1.0 MF4 Application Hints
The MF4 is a non-inverting unity gain low-pass fourth-order
Butterworth switched-capacitor filter. The switched-capacitor topology makes the cutoff frequency (where the gain
drops 3.01 dB below the DC gain) a direct ratio (100:1 or
a
lin = a/T
1-19
II
~
::::E
1.0 MF4 Application Hints (Continued)
(where T equals one clock period) or
which will become noticeable when the clock frequency exceeds 250 kHz. The response of the MF4 is still a good
approximation of the ideal Butterworth low-pass characteristic shown in Figure 5.
CinVin
lin = -T- = CinVinfCLK
The equivalent input resistor (Rin) then can be expressed as
2.0 Designing With The MF4
Yin
1
Rin=-=--lin
CinfCLK
The input capacitor is 2 pF for the MF4-50 and 1 pF for the
MF4-100, so for the MF4-100
Given any low-pass filter specification, two equations will
come in handy in trying to determine whether the MF4 will
do the job. The first equation determines the order of the
low-pass filter required to meet a given response specification:
n = log [(100.1Amin - 1)/(100.1Amax - 1)]
(2)
R. = 1 X 1012 = 1 X 1012 = 1 X 1010
In
fCLK
fe X 100
fe
and
2 log (fs/fb)
where n is the order of the filter, Amin is the minimum stopband attenuation (in dB) desired at frequency fs, and Amax is
the passband ripple or attenuation (in dB) at cutoff frequency fb. If the result of this equation is greater than 4, more
than a single MF4 is required.
5 X 1011
5 X 1011
1 X 1010
R-n = - - - = - - - = - - I
fCLK
fe X 50
fe
for the MF4-50. The above equation shows that for a given
cutoff frequency (fel, the input resistance of the MF4-50 is
the same as that of the MF4-100. The higher the clock-tocutoff-frequency ratio, the greater equivalent input resistance for a given clock frequency.
The attenuation at any frequency can be found by the following equation:
Attn (I) = 10 log [1 + (100.1Amax - 1) (f/fb)2n] dB (3)
This input resistance will form a voltage divider with the
source impedance (Rsouree). Since Rin is inversely proportional to the cutoff frequency, operation at higher cutoff frequencies will be more likely to load the input signal which
would appear as an overall decrease in gain to the output of
the filter. Since the filter's ideal gain is unity, the overall gain
is given by:
where n = 4 for the MF4.
2.1 A LOW-PASS DESIGN EXAMPLE
Suppose the amplitude response specification in Figure 6 is
given. Can the MF4 be used? The order of the Butterworth
approximation will have to be determined using (1):
Av-
Rin
Rin + Rsouree
If the MF4-50 or the MF-l00 were set up for a cutoff frequency of 10kHz the input impedance would be:
1 X 1010
Rin = 10kHz = 1 MO
Amin = 18 dB, Amax = 1.0 dB, fs = 2 kHz, and fb = 1 kHz
log [(101.B - 1)/(100.1 - 1)]
n=
210g(2)
= 3.95
Since the maximum overall gain error for the MF4 is
± 0.15 dB with Rs ,;;; 2 kO the actual gain error for this case
would be +0.06 dB to -0.24 dB.
Since n can only take on integer values, n = 4. Therefore
the MF4 can be used. In general, if n is 4 or less a single
MF4 stage can be utilized.
Likewise, the attenuation at fs can be found using (3) with
the above values and n = 4:
Attn (2 kHz) = 10 log [1 + 100.1 - 1) (2 kHz/1 kHz)B] =
18.28 dB
This result also meets the design specification given in Figure 6 again verifying that a single MF4 section will be adequate.
1.4 CUTOFF FREQUENCY RANGE
The filter's cutoff frequency (fel has a lower limit due to
leakage currents through the internal switches draining the
charge stored on the capacitors. At lower clock frequencies
these leakage currents can cause millivolts of error, for example:
Since the MF4's cutoff frequency (fel, which corresponds to
a ·gain attenuation of -3.01 dB, was not specified in this
example, it needs to be calculated. Solving equation 3
where f = fe as follows:
[(100 .1(3.01 dB) - 1 ]1/(2n)
_
fe - fb (100.1Amax _ 1)
In this example with a source impedance of 10K the overall
gain, if the MF4 had an ideal gain of 1 or 0 dB, would be:
1 MO
Av = 10 kO + 1 MO = 0.99009 or -0.086 dB
fCLK = 100 Hz, Ileakage = 1 pA, C = 1 pF
1 pA
V= 1 pF (100 Hz) = 10 mV
100 .301 - 1
= 1 kHz [ 100.1 _ 1
]1/8
= 1.184 kHz
The propagation delay in the logic and the settling time required to acquire a new voltage level on the capacitors limit
the filter's accuracy at high clock frequencies. The amplitude characteristic on ± 5V supplies will typically stay flat
until fCLK exceeds 750 kHz and then peak at about 0.5 dB
at the corner frequency with a 1 MHz clock. As supply voltage drops to ± 2.5V, a shift in the fCLK/fe ratio occurs
where fe = fCLK/50 or fCLK/100. To implement this example for the MF4-50 the clock frequency will have to be set to
fCLK = 50(1.184 kHz) = 59.2 kHz, or for the MF4-100, fCLK
= 100 (1.184 kHz) = 118.4 kHz.
2.2 CASCADING MF4s
When a steeper stopband attenuation rate is required, two
MF4s can be cascaded (Figure 7) yielding an 8th order
1-20
2.0 Designing With The MF4 (Continued)
slope of 48 dB per octave. Because the MF4 is a Butterworth filter and therefore has no ripple in its passband when
MF4s are cascaded, the resulting filter also has no ripple in
its passband. Likewise the DC and passband gains will remain at 1V1V. The resulting response is shown in Figure 9.
MF4-50 has a 100 kHz clock making fe = 2 kHz; when this
signal goes high the clock frequency changes to 50 kHz
yielding fe = 1 kHz. As the Figure illustrates, the output
signal changes quickly and smoothly in response to a sudden change in clock frequency.
In determining whether the cascaded MF4s will yield a filter
that will meet a particular amplitude response specification,
as above, equations 3 and 4 can be used, shown below.
The step response of the MF4 in Figure 10 is dependent on
f e. The MF4 responds as a classical fourth-order Butterworth low-pass filter.
n=
log[(100 .05A min - 1)/(10.0 .05A max - 1)]
Attn (f) = 10 log [1
2 log (fs/fel
+ (10 0.05Amax -
2.4 ALIASING CONSIDERATIONS
(2)
Aliasing effects have to be considered when input signal
frequencies exceed half the sampling rate. For the MF4 this
equals half the clock frequency (fCLK)' When the input signal contains a component at a frequency higher than half
the clock frequency fCLK/2, as in Figure 11a, that component will be "reflected" about fCLK/2 into the frequency
range below fCLK/2, as in Figure 11b. If this component is
within the passband of the filter and of large enough amplitude it can cause problems. Therefore, if frequency components in the input signal exceed fCLK2 they must be attenuated before being applied to the MF4 input. The necessary
amount of attenuation will vary depending on system requirements. In critical applications the signal components
above fCLK/2 will have to be attenuated at least to the filter's residual noise level.
1) (flfel 2] dB (3)
where n = 4 (the order of each filter).
Equation 2 will determine whether the order of the filter is
adequate (n ,:;; 4) while equation 3 can determine the actual
stopband attenuation and cutoff frequency (fel necessary to
obtain the desired frequency response. The design procedure would be identical to the one shown in section 2.0.
2.3 CHANGING CLOCK FREQUENCY
INSTANTANEOUSLY
The MF4 will respond favorably to an instantaneous change
in clock frequency. If the control signal in Figure 9 is low the
f=
1
FCln[(Vec- v ,-)
Vee - Vt +
(~)l
Vt -
,,,,_1_
1.69Re
(Vce = 10V)
TL/H/S064-11
FIGURE 1. Schmitt Trigger RIC Oscillator
1-21
II
sv-n n
-sv...J U L
eLK IN
FILTER IN
eLK R
3
MF4
5V:.rL..rL.
OV
Y+~-""-5V
0.11'F
2
AGNO
3
FILTER OUT
4
L.SH
-5V
eLK IN
FILTER IN
8
eLK R
+5V
0.11'F
MF4
L.SH
v'
FILTER OUT
5
TUH/5064-13
VIH ;" 0.8 Vee
VIL'; 0.2 Vee
Vee ~ V+ - V-
TLlH/5064-12
(a)
(b)
FIGURE 2. Split Supply Operation with CMOS Level Clock (a) and TTL Level Clock (b)
10V-n n
ov-I U L
eLK IN
FILTER IN
I- VIN
8
y+ 7
eLK R
3
10V
I O .l ).1F
MF4
AGND
6
10 k.n
0.1 ).IF
FILTER OUT 5 VOUT
TLlH/5064-14
FIGURE 3. Single Supply Operation. ANGD Resistor Biased to V+ 12
FILTERo-.JVV\ro.......
INPUT
R _ _l _
IN - elN 'eLK
! AGND
TL/H/5064- 15
! AGND
TL/H/5064-20
a) Equivalent Circuit for MF4 Filter Input
b) Actual Circuit for MF4 Filter Input
FIGURE 4. MF4 Filter Input
1-22
100
1,DOO
10,DOO 5O,DOO
100
FREQUENCY (Hz)
10,00
10,DOO 50,DOO
FREQUENCY (Hz)
FIGURE 5b, MF4-50 Amplitude
Response with ± 5V Supplies
FIGURE 5a. MF4-100 Amplitude
Response with ± 5V Supplies
100
1,000
10,000 50,000
FREQUENCY (Hz)
FIGURE 5c. MF4-100 Amplitude
Response with ± 2.5V Supplies
10r--..----.--.-~~
o "'1-'-I=~::Is.=~:;::_IH
100
1,DOO
10,000 50,000
FREQUENCY (Hz)
TL/H/5064-21
FIGURE 5d. MF4-50 Amplitude
Response with ± 2.5V Supplies
o~~~~~~~~~~
AMAX =-1 ~..l..:I..lo..l..l.~~I..lo..l..l.4..
2
~
~
5
II
a.
:i
AMIN =-18 - - - - - - - - - - - - - - - - - - --
o
fb
=1 kHz f. =2 kHz
FREQUENCY (Hz)
TL/H/5064-22
FIGURE 6. Design Example Magnitude Response Specification where the Response of
the Filter Design must fall within the shaded area of the specification
1-23
~
u..
r-------------------------------------------------------------------------------------,
:E
8
MF4
V- CLK R
IN
5
MF4
FILTER
7
4
FIlTER
FILTER
OUT
IN
2
V- CLK R
7
4
2
FIlTER
OUT
~=+5Vo_--~~--~--~--+_--------------~~~~
~=-5Vo_--~------~~~--------------~~------~
feu<
0_----------------___-----------------------------'
TL/H/S064-23
FIGURE 7. Cascading Two MF4s
10
I
1
1
-10
!
l!l
I"
-20
-30
fa.K =20 kHz
VS=tSv
I
00
I
"'
-1000
1
Y-2!!LGI!..
-3OD"
-so
1
1
-60
-70
I
-80
10
100
-5000
1\
\
-6000
\
-7000
1\ \.
1000
-BOO"
50DD
FREQUENCY (Hz)
\
Vs-tSV
fcuc=20kHz _
\
\
\
~-4000
-40
CASCADED-
\
-2000
o
" ...... FREQUENCY (kHz)
TL/H/S064-18
FIGURE 8b. Phase Response
of Two Cascaded MF4-50s
FIGURE 8a. One MF4-50
vs Two MF4-50s Cascaded
TLiH/S064-24
TLlH/5064-19
FIGURE 10. MF4-50 Input Step Response
FIGURE 9. MF4-50 Abrupt Clock Frequency Change
1-24
.----------------------------------------------------------------.g
"11
""
w
CI
:>
5
A.
::&
l
co:
t
Is
2
~+I
t
Is
~-I
2
2
FREQUENCY
1
Is
2
1
~+I
FREQUENCY
TL/H/S064-16
(a) input signal spectrum
Is
2
TL/H/S064-17
(b) Output signal spectrum. Note that the input signal at
fc/2 + f causes an output signal to appear at fc/2 - f.
FIGURE 11. The phenomenon of aliasing In sampled-data systems. An input signal whose
frequency is greater than one·half the sampling frequency will cause an output to appear
at a frequency lower than one-half the sampling frequency. In the MF4, fs = felK.
II
1-25
_
National
Semiconductor
Corporation
MF5 Universal Monolithic Switched Capacitor Filter
General Description
Features
The MF5 consists of an extremely easy to use, general purpose CMOS active filter building block and an uncommitted
op amp. The filter building block, together with an extemal
clock and a few resistors, can produce various second order
functions. The filter building block has 3 output pins. One of
the output pins can be configured to perform highpass, allpass or notch functions and the remaining 2 output pins
perform bandpass and lowpass functions. The center frequency of the filter can be directly dependent on the clock
frequency or it can depend on both clock frequency and
external resistor ratios. The uncommitted op amp can be
used for cascading purposes, for obtaining additional allpass and notch functions, or for various other applications.
Higher order filter functions can be obtained by cascading
several MF5s or by using the MF5 in conjuction with the
MF10 (dual switched capacitor filter building block). The
MF5 is functionally compatible with the MF10. Any of the
classical filter configurations (such as Butterworth, Bessel,
Cauer and Chebyshev) can be formed.
• Low cost
• 14-pin DIP or 14-pin Surface Mount (SO) wide-body
package
• Easy to use
• Clock to center frequency ratio accuracy ±0.6%
• Filter cutoff frequency stability directly dependent on
external clock quality
• Low sensitivity to external component variations
• Separate highpass (or notch or allpass), bandpass, lowpass outputs
• foxQ range up to 200 kHz
• Operation up to 30 kHz (typical)
• Additional uncommitted op-amp
Block and Connection Diagrams
v-
BP
SI
LP
14
INYI
AGNO
elK
2
50/100
INY2
~
13
- A2
AGNO
V
02
lShnl---..I
TLIH/S066-1
All Packages
BP
N/AP/HP
14
2
lP
Y02
INY2
INYl
AGND
81
YY+
Order Number MF5CN
See NS Package Number N14A
Order Number MF5CWM
See NS Package Number M14B
50/100
elK
l8h
Top View
1-26
TL/H/5066-2
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V+ - V-)
14V
Power Dissipation TA = 25'C (note 1)
500mW
Storage Temp.
150'C
Soldering Information:
N Package:
10 sec.
260'C
SO Package: Vapor phase (60 sec.)
215'C
Infrared (15 sec.)
220'C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.
V- ,,; Vin"; V+
Input Voltage (any pin)
Operating Temp. Range
TMIN ,,; TA"; TMAX
MF5CN, MF5CWM
O'C,,; TA"; 70'C
Electrical Characteristics v+ = 5V ± 0.5%, V- = -5V ± 0.5% unless otherwise noted. Boldface limits
apply over temperature, TMIN ,,; TA ,,; TMAX. For all other limits TA = 25'C.
Parameter
~
Supply Voltage
(V+ - V-)
Tested
Limit
(Note 7)
I
I
Design
Limit
(Note 8)
Units
8
V
14
Max
Maximum Supply Current
Clock
Feedthrough
Typical
(Note 6)
Conditions
Clock applied to Pin 8
No Input Signal
4.5
6.0
V
mA
Filter Output
10
mV
Op-amp Output
10
mV
Filter Electrical Characteristics v+ = 5V± 0.5%, V- = -5V± 0.5% unless otherwise noted. Boldface
limits apply over temperature, TMIN ,,; TA ,,; TMAX. For all other limits TA = 25'C.
Parameter
Typical
(Note 6)
Conditions
Center Frequency
Range (fo)
~
30
Min
0.1
Clock Frequency
Range (fClK)
Max
1.5
-
Min
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
20
0.2
1.0
10
5.0
Units
kHz
Hz
MHz
Hz
II
Clock to Center
Frequency Ratio
(fClK/fo)
Ideal
Q=10
Model
fClK/fo Temp.
Coefficient
Vpin9 = +5V
(50:1 ClK ratio)
±10
ppm/'C
Vpin9 = -5V
(100:1 ClK ratio)
±20
ppml'C
Q Accuracy (Max)
(Note 2)
Ideal
Q=10
Model
Q Temperature
Coefficient
DC lowpass Gain
Accuracy (Max)
DC Offset
Voltage (Max)
(Note 3)
Vpin9 = +5V
FClK = 250 kHz
50.11 ± 0.2%
50.11 ± 1.5%
Vpin9 = -5V
FClK=500 kHz
100.04 ± 0.2%
100.04 ± 1.5%
Vpin9 = +5V
FClK = 250 kHz
±6
%
Vpin9 = -5V
FClK = 500 kHz
±6
%
Vpin9 = +5V
(50:1 ClK ratio)
-200
ppml'C
Vpin9 = -5V
(100:1 ClK ratio)
-70
ppml'C
Mode 1
Rl = R2 = 10 kO
±0.2
Yost
I Vos2
Vos3
Vpin9 = +5V
(50:1 ClK ratio)
I Vos2
Vos3
Vpin9 = -5V
(100:1 ClK ratio)
1-27
dB
±5.0
mV
-185
mV
+115
mV
-310
mV
+240
mV
Filter Electrical Characteristics v+ = 5V± 0.5%, V- = -5V± 0.5% unless otherwise noted. Boldface
limits apply over temperature, T MIN :s; T A :s; T MAX. For all other limits TA = 25°C. (Continued)
Parameter
I
I
Output
Swing (Min)
Conditions
Typical
(Note 6)
Tested
Limit
(Note 7)
BP, lPpins
RL = 5kO
±4.0
±3.8
N/AP/HPpin
RL = 3.5kO
±4.2
±3.8
Dynamic Range
(Note 4)
Maximum Output Short Circuit
Current (Note 5)
Design
Limit
(Note 8)
Units
V
V
Vpin9= +5V
(50:1 ClK ratio)
83
dB
Vping= -5V
(100:1 CLK ratio)
80
dB
I
Source
20
mA
I
Sink
3.0
mA
OP-AMP Electrical Characteristics v+ = +5V ±0.5%, v- = -5V ±0.5% unless other noted. Bold·
face limits apply over temperature, T MIN :s; T A :s; T MAX. For all other limits TA = 25°C.
Parameter
Conditions
Typical
(Note 6)
RL = 3.5kO
±4.2
Gain Bandwidth Product
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
2.5
Output Voltage Swing (Min)
Slew Rate
MHz
±3.8
V
7.0
DC Open-loop Gain
V/p,s
80
db
±5.0
Input Offset Voltage (Max)
Units
±20
mV
Input Bias Current
10
pA
Maximum Output
Short Circuit
Current (Note 5)
20
mA
3.0
mA
Source
Sink
Logic I nput Characteristics Boldface limits apply over temperature, TMIN :s; TA :s; TMAX'
All other limits TA = 25°C.
Parameter
CMOS Clock
Input
Min logical "1"
Input Voltage
Max Logical "0"
Input Voltage
Min logical "1"
Input Voltage
Max Logical "0"
Input Voltage
TTL Clock
Input
Min logical "1"
Input Voltage
Conditions
Typical
(Note 6)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Units
3.0
V
-3.0
V
8.0
V
2.0
V
2.0
V
V+ = +5V, V- = -5V,
VL.Sh. =OV
V+ = +10V, V- = OV,
VL.Sh. = +5V
V+ = +5V, V- = -5V,
Max logical "0"
0.8
V
VL.Sh. = OV
Input Voltage
Note 1: The Iypicallunction.to·ambient thermal resistance (8JN of the 14 pin N package Is 160'C/W, and 82'C/W for the M package.
Note 2: The accuracy of the Q value is a function of the center frequency (fo). This is Illustrated in the curves under the heading "Typical Performance
Characteristics".
Note 3: Vos1. Vos2. and V0s3 refer to the internal offsets as discussed in the Application Information section 3.4.
Note 4: For ± 5V supplies the dynamic range is referenced to 2.82V rms (4V peak) where the wideband noise over a 20 kHz bandwidth Is typically 200 p.V rms for
the MF5 with a 50:1 ClK ratio and 280 p.V rms for the MF5 with a 100:1 ClK ratio.
Note 5: The short circuit source current Is measured by forcing the output that is being tasted to its maximum positive voltage swing and then shorting that output to
the negative supply. The short circuit sink current is measured by forcing the output that Is being tested to Its maximum negative voltage swing and then shorting
that output to the positive supply. These are the worst case conditions.
Note 6: Typicals are at 25°C and represent most likely parametric norm.
Note 7: Guaranteed and 100% tested.
Note 8: Guaranteed, but not 100% tested. These limits are not used to calculate outgOing quality levels.
1-28
Pin Description
lP(14), BP(1),
N/AP/HP(2):
The second order lowpass, bandpass,
and notch/allpass/highpassoutputs. The
lP and BP outputs can typically sink 1 rnA
and source 3 mA. The NI AP/HP output
can typically sink 1.5 rnA and source 3
rnA. Each output typically swings to within
1V of each supply.
The inverting input of the summing op
amp of the filter. This is a high impedance
input, but the non-inverting input is
internally tied to AGND, making INV1
behave like a summing junction (low
impedance current input).
S1 is a signal input pin used in the all pass
filter configurations (see modes 4 and 5).
The pin should be driven with a source
impedance of less than 1 kn. If S1 is not
driven with a signal it should be tied to
AGND (mid-supply).
This pin activates a switch that connects
one of the inputs of the filter's second
summer to either AGND (SA tied to V-I
or to the lowpass (lP) output (SA tied to
V + ). This offers the flexibility needed for
configuring the filter in its various modes
of operation.
This pin is used to set the internal clock to
center frequency ratio (fCLK/fo) of the
filter. By tying the pin to V + an fCLK/fo
ratio of about 50:1 (typically 50.11 ±
0.2%) is obtained. Tying the 50/100 pin to
either AGND or V - will set the fCLK/fo
ratio to about 100: 1 (typically 100.04 ±
0.2%).
This is the analog ground pin. This pin
should be connected to the system
ground for dual supply operation or biased
to mid-supply for single supply operation.
For a further discussion of mid-supply
biasing techniques see the Applications
Information (Section 3.2). For optimum
filter performance a "clean" ground must
be provided.
INV1 (3):
S1 (4):
SA(5):
50/100(9):
AGND(11):
V+(6), V-(10):
ClK(8):
L. Sh(7):
INV2(12):
V02(13):
These are the positive and negative
supply pins. The MF5 will operate over a
total supply range of 8V to 14V.
Decoupling the supply pins with 0.1 ",F
capacitors is highly recommended.
This is the clock input for the filter. CMOS
or TTL logic level clocks can be
accomodated by setting the L. Sh pin to
the levels described in the L. Sh pin
description. For optimum filter
performance a 50% duty cycle clock is
recommended for clock frequencies
greater than 200 kHz. This gives each op
amp the maximum amount of time to
settle to a new sampled input.
This pin allows the MF5 to accommodate
either CMOS or TTL logic level clocks. For
dual supply operation (i.e., ± 5V), a CMOS
or TTL logic level clock can be accepted if
the L. Sh pin is tied to mid-supply (AGND),
which should be the system ground.
For single supply operation the L. Sh pin
should be tied to mid-supply (AGND) for a
CMOS logic level clock. The mid-supply
bias should be a very low impedance
node. See Applications Information for
biasing techniques. For a TTL logic level
clock the L. Sh pin should be tied to Vwhich should be the system ground.
This is the inverting input of the
uncommitted op amp. This is a very high
impedance input, but the non-inverting
input is internally tied to AGND, making
INV2 behave like a summing junction
(low-impedance current input).
This is the output of the uncommitted op
amp. It will typically sink 1.5 mA and
source 3.0 mAo It will typically swing to
within 1V of each supply.
II
Typical Performance Characteristics
Deviation of
F~~K vs Nominal Q
Fo
1.0
0.5
. =
. =
=
~
0.0
z
-
~-50.11
~
i§
~.e
iii
I
~I.e
0.0
1111111
r-Icuc -100.04
-"D'
Iii!
Iii! -1.0
-2.0
"
-0.5
-1.0
-3.0
0.1
1.0
10
NOMINALQ
100
OPAMP Output Voltage
Swing vs Temperature
Deviation of FCLK vs Nominal Q
0.1
1.0
10
NOMINAL Q
100
,.
4.6
'"j
'"
4.4
lIi!
4.0
.~
4.Z
~
3.8
I I
r- ~±
= ±5V
RL=3.5 k{!
kWI~G
~EGISWlrG
~-
i'oo..
i"""
~
I'
",..
3.6
-55
-
. ~OS
I
-15
Z5
85
TEMPERATURE ('C)
"
lZ5
TL/H/S066-3
1-29
~,---------------------------------------------------------------------
II.
:!5
observed as the frequency of a notch at the allpass output.
(Figure 10).
Typical Performance
Characteristics (Continued)
Q: "quality factor" of the 2nd order filter. Q is measured at
the bandpass output of the MF5 and is equal to fo divided by
the - 3dS bandwidth of the 2nd order bandpass filter (Figure 1). The value of Q determines the shape of the 2nd
order filter responses as shown in Figure 6.
Supply Current vs Temperature
6.0
;0-
.§.
>-
~
5.6
v1=15J
leLk =250 kHz
...... "- ......
5.2
i:l 4.8 f-f- 50:~
1"'-0
!:;
.,8::
'"
Qz: the quality factor of the second order complex zero pair,
if any. Qz is related to the all pass characteristic, which is
written:
100:1 I- l - I--
100...
4.4
.....
.... """
""'"
.....
4.0 L-L......JI-.J.---L....J..-J......L....L..J
-55 -15
25
85
125
where Qz = Q for an all-pass response.
TEMPERATURE (OC)
HOBP: the gain (in VIV) of the bandpass output at f
TL/H/S066-4
1.0 Definitions of Terms
HOlP: the gain (in V IV) of the lowpass output as f (Figure 2).
felK: the frequency of the external clock signal applied to
pin B.
1-
0 Hz
HOHP: the gain (in V IV) 01 the high pass output as
fclk/2 (Figure 3).
HON: the gain (in VIV) of the notch output as 1 0 Hz and
fclk/2, when the notch filter has equal gain above
as f and below the center frequency (Figure 4). When the lowfrequency gain differs from the high-frequency gain, as in
modes 2 and 3a (Figures 11 and 8), the two quantities below are used in place of HON.
fo: center frequency of the second order function complex
pole pair. fo is measured at the bandpass output of the MF5,
and is the frequency of maximum bandpass gain. (Rgure 1).
fnotch: the frequency of minimum (ideally zero) gain at the
notch output.
fz: the center frequency of the second order complex zero
pair, if any. If fz is different from fo and if Qz is high, it can be
>
= f o.
HON1: the gain (in V/V) of the notch output as f -
0 Hz.
HON2: the gain (in VIV) of the notch output as f -
fClk/2.
HOBP I----~
~ 0.707 HOBP I---~~:"""~
~
~"
IL 10 IH
IL I, IH
(a)
I (LOG SCALE)
(b)
TL/H/5066-S
I (LOG SCALE)
TLlH/5066-6
FIGURE 1. 2nd-Order Bandpass Response
>
~O~
HOp t;;;:::;;;:;;;;;;;~
~
HOLP
i" 0.707 HOLP
~
I-----l--'lI'l'' '-
~ -90
-180
Ip
(a)
Ip
I,
I (LOG SCALE)
10
TL/H/S066-7
(b)
I (LOG SCALE)
TL/H/S066-8
FIGURE 2. 2nd-Order Low-Pass Response
i
>
[?f
HOp~=:::::;~~_ _
HOHP l0.707 HOHP
~-90
~--1.---I_______
I,
(a)
-180
I
/1
I---""""" ·1
10
Ip
I (LOG SCALE)
TL/H/S066-9
0 ~ (1 - 2~2) + ~ (1 - 2~r + 1
Ie = 1 X
,"-
(b)
I (LOG SCALE)
FIGURE 3. 2nd-Order High-Pass Response
1-30
TL/H/5066-10
= 10~1
-
2~2
HOp=HOLPX 1 ~
1
Q 1- 402
==
."
1.0 Definition of Terms (Continued)
en
~
HN(S)
HON(S2
90
>"
;;
i" 0.707 HON
S2
Q
~ 45
HON
I---~.--~'-----
~
0
"
~
if: -45 I---~
-90 ~____~~~____~
fl fo
+
+ SllJo + wo2
"'02)
fH
fL fo f.
f (LOG SCALE)
Q
~ fH ~ fL;
fL
~ fo (;~ + ~ (~r + 1)
fH
~ fa (~+ ~ (~r +1 )
f (LOG SCALE)
TLlH/5066-11
fo
~ ./iliH
TL/H/5066-12
(a)
(b)
FIGURE 4. 2nd-Order Notch Response
;;; HAP
~
1----..,.---
~
w
~-180
:z
~
t::::===t==~:
-360
fO
fo
f (LOG SCALE)
f (LOG SCALE)
TL/H/5066-14
TL/H/5066-13
(b)
(a)
FIGURE 5. 2nd-Order All-Pass Response
(a) Bandpass
(b) Low-Pass
20
20
10
10
i" -10
~
-20
-30
-40
V
~
t$
."
a-~
{!10
I'
I"
19i0=2j
1
FREOUENCY (Hz)
~~-!±
~0=1
.......
~
iii
~
.....
1- 0=0.2
-20
..... I '
0.1
0.2
0.5 1.0 2.0
I~
.,/
~
II'
-40
0.1 0.2
10
0-~.5_
i::::O=~.L
0.5 1.0
2
5
10
FREOUENCY (Hz)
(e) All-Pass
1-+-+--+-+--1--1
-60
.
o
.....
5
~-120
:!!!.
z -10 I-+-+~
iii
.L IL
FREQUENCY (Hz)
(d) Notch
10
5.0
t-
. ...,
.,..;
-3D
~
-40
10
~
-20
I'OlIro.
0=10_
'-l.
b.t,00=;2-..
-.! ~
1-0 0.707
'" -10
i'
iii
'".....
C:±O=~~
10
~=0.707-
0-0.5'
-3D
...... l"'oo.
0.5
.I.
i" -10
"'I
'" I7J
0.1
~~ ".,
!*"0=5-T-
.
0=1
i"'OI.
~
Ii
20 (c) High-Pass
t-- /--0=10
~
-180
.......
... -240
"0 1
1-+-+--+-+-+--1
-300
-40 ~..I-....L.__..J......J..__~--'
10
1.0 0.2 0.5
0.1 2
-360
-3D
~ 0-0.2
:z:
-20 I-+-+--\'I---"i-~';
.xi
......
"
0.1 0.2
FREOUENCY (Hz)
0.5
1
2
10
FREOUENCY (Hz)
TLlH/5066-15
FIGURE 6. Responses of various 2nd-order filters
as a function of Q. Gains and center frequencies
are normalized to unity.
1-31
II
~
:E
2.0 Modes of Operation
The MF5 is a switched capacitor (sampled data) filter. To
fully describe its transfer functions, a time domain approach
is appropriate. Since this is cumbersome, and since the
MF5 closely approximates continuous filters, the following
discussion is based on the well known frequency domain.
Each MF5 can produce a full 2nd order function. See Table
1 for a summary of the characteristics of the various modes.
MODE 1: Notch I, Bandpass, Lowpass Outputs:
fo
fnotch
BW
BW
= the -3 dB bandwidth of the bandpass output.
HOlP
fClK fClK
= 100 or 50
fClK fClK
roo
or SO
Bandpass gain (at f
o
}
R3
=R2
-1; HOlP(peak) '" 0 X HOlP (for high O's)
R3
R2
= fo) = - :~
HON = Notch output gain as f -+ 0
Hosp
aor Hosp = HOlP X 0 = HON X O.
HOlP(Peak) "" 0 X HOlP (for high O's)
= center frequency of the imaginary zero pair = fo.
=
=
MODE la: Non-Inverting BP, LP (See Figure 8)
R2
HOlP = Lowpass gain (as f -+ 0) = - Rl
Hosp
R3
R2
Circuit dynamics:
Inotch = 10 (See Figure 7)
= center frequency of the complex pole pair
=
...!2...=
o
HOSP2 = 1 (non-inverting)
Circuit dynamics: HOSP1 = 0
Note: VIN should be driven from a low impedance «1 kO)
= _ R2
R1
f -+ fClK/2
TLIH/5066-16
FIGURE 7. MODE 1
TLiH/5066-17
FIGURE 8. MODE la
1-32
s:::
."
U1
2.0 Modes of Operation (Continued)
MODE 2: Notch 2, Bandpass, Lowpass: fnolch 5 kHz.
100:1
50:1
TL/H/S066-32
FIGURE 21. The Sampled-Data Output Waveform
1-40
r----------------------------------------------------------------.~
"11
en
NatiOnal
~ Semiconductor
Corporation
MF6 6th Order Switched Capacitor
Butterworth Lowpass Filter
General Description
Features
The MF6 is a versatile easy to use, precision 6th order Butterworth lowpass active filter. Switched capacitor techniques eliminate external component requirements and alIowa clock tunable cutoff frequency. The ratio of the clock
frequency to the lowpass cutoff frequency is internally set to
50 to 1 (MF6-50) or 100 to 1 (MF6-100). A Schmitt trigger
clock input stage allows two clocking options, either selfclocking (via an external resistor and capacitor) for standalone applications, or an external TTL or CMOS logic compatible clock can be used for tighter cutoff frequency control. The maximally flat passband frequency response together with a DC gain of 1 V IV allows cascading MF6 sections for higher order filtering. In addition to the filter, two
independent CMOS op amps are included on the die and
are useful for any general Signal conditioning applications.
•
•
•
•
•
•
•
No external components
14-pin DIP or 14-pin wide-body S.D. package
Cutoff frequency accuracy of ±0.3% typical
Cutoff frequency range of 0.1 Hz to 20 kHz
Two uncommitted op amps available
5V to 14V total supply voltage
Cutoff frequency set by external or internal clock
Block and Connection Diagrams
AIJER
OUT
All Packages
INV,
N.INV2
14
INV2
Yoz
13
INVI
FILTER
OUT
12
Vol
L...-----......
------F~.
I AGND
LS~
CLKR
y-
AGND
CLK
IN
FILTER
IN
Y·
Vas ADJ
IIIV2
TLiH/5065-2
Top View
N.lNV2
L.Sb
v+
vTL/H/5065-'
Order Number MFSCWM-50
or MFSCWM-l00
See NS Package Number M14B
Order Number MFSCN-50
or MFSCN-100
See NS Package Number N14A
Order Number MFSCJ-50
or MFSCJ-100
See NS Package Number J14A
1-41
II
Absolute Maximum Ratings (Note 11)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" (Appendix D) for other methods of
soldering surface mount devices.
14V
V- - O.2V. V+ + O.2V
Voltage at Any Pin
Input Current at Any Pin (Note 13)
5mA
Package Input Current (Note 13)
20mA
Power Dissipation (Note 14)
Operating Ratings (Note 11)
Temperature Range
MFSCWM-50. MFSCWM-100
500mW
Storage Temperature
TA";; +70'C
5Vto 14V
2SO'C
300'C
215'C
220'C
Filter Electrical Characteristics The following specifications apply for felK
otherwise specified. Boldface limits apply for T MIN to TMAX; all other limits TA = TJ = 25'C.
MF6CWM-50. MF6CWM-100,
MF6CN-50, MF6CN-100
Parameter
S;;
-40'C,,;; TA";; +85'C
SupplyVoltage(Vs = V+-V-)
800V
Soldering Information
N Package (10 sec.)
J Package (10 sec.)
SO Package
Vapor Phase (SO sec.)
Infrared (15 sec.)
O'C
MFSCJ-50. MFSCJ-100
-S5'Cto +150'C
ESD Susceptibility (Note 12)
TMIN S;; TA S;; TMAX
O'C,,;; TA S;; +70'C
MFSCN-50. MFSCN-100
Conditions
Typical
(Note 8)
Tested
Limit
(Note 9)
Design
Limit
(Note 10)
S;;
250 kHz (see Note 3) unless
MF6CJ-50, MF6CJ-100
Typical
(Note 8)
Tested
Limit
(Note 9)
Design
Limit
(Note 10)
Units
V+ = +5V, V- = -5V
fe.Cutoff
Frequency
Range
(Note 1)
MF6·S0
MF6·100
Min
Max
Min
Max
Total Supply Current
Maximum Clock
Feedthrough
fCLK = 2S0 kHz
Filter Output
OpAmp 1 Out
Op Amp 2 Out
Ho•
DC Gain
MF6·S0
MF6-100
DC
Offset Voltage
MF6-S0
MF6·100
Minimum Output
Voltage Swing
Maximum Output
Short Circuit
Current (Note 6)
Dynamic Range
(Note 2)
Additional
Magnitude
Response Test
Points (Note 4)
6.0
0.1
20k
0.1
0.1
10k
10k
8.5
30
2S
20
Rsouree
,;; 2 ko.
fCLKlfe.
Clock to Cutoff
Frequency Ratio
4.0
0.1
20k
0.0
4.0
8.5
30
2S
20
±0.30
±0.30
0.0
Hz
mA
mV
(peak-topeak)
±0.30
dB
49.27±0.3% 49.27±1% 49.27±1% 49.27±0.3% 49.27±1%
98.97±0.3% 98.97±1% 98.97±1% 98.97±0.3% 98.97±1%
-200
-400
-200
-400
mV
+4.0
-4.1
+3.S
-3.8
+3.5
-3.5
+4.0
-4.1
+3.5
-3.5
Source
Sink
SO
1.S
60
2.0
80
3.0
SO
1.S
3.0
MF6-S0
MF6-100
83
81
RL =10ko.
80
83
81
V
rnA
dB
MF6-S0 fCLK = 2S0 kHz
f=6000 Hz
f=4S00Hz
-9.47
-0.92
-9.47±0.S -9.47±0.65
-0.92±0.2 -0.92±0.3
-9.47
-0.92
-9.47±0.65
-0.92±0.3
dB
MF6-100 fCLK=2S0 kHz
f=3000 Hz
f=22S0 Hz
-9.48
-0.97
-9.48±0.S -9.48 ± 0.65
-0.97±0.2 -0.97±0.3
-9.48
-0.97
-9.48±0.85
-0.97±0.3
dB
1-42
Filter Electrical Characteristics (Continued) The following specifications apply for fCLK 5: 250 kHz (see
Note 3) unless otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25'C.
MFSCWM-SO, MFSCWM-100
MFSCN-SO, MF6CN-100
Parameter
Conditions
MFSCJ-SO, MFSCJ-100
Design
Limit
(Note 10)
MFS-SO fCLK = 2S0 kHz
f, =6000 Hz
f2=8000 Hz
-36
-36
-36
dB!
octave
MFS-100 fCLK = 2S0 kHz
I, =3000 Hz
f2=4000 Hz
-36
-36
-36
dB!
octave
Typical
(Note 8)
Tested
Limit
(Note 9)
Design
Limit
(Note 10)
Units
Tested
Limit
(Note 9)
Typical
(Note 8)
V+ = +SV,V- = -SV(Continued)
Attenuation Rate
V+ = +2.SV, V- = -2.5V
fe.Cutoff
Frequency
Range
(Note 1)
MFS-SO
Min
Max
Min
Max
MFS-100
Total Supply Current
fCLK = 2S0 kHz
Maximum Clock
Filter Output
Feedthrough
OpAmp lOut
OpAmp 2 Out
Ho. DC Gain
MF6-S0
MF6-100
DC
Offset Voltage
MF6-S0
MFS-l00
Minimum Output
Voltage Swing
Attenuation
Rate
4.0
0.0
2.S
4.0
20
15
10
±0.30
±0.30
0.0
mA
mV
(peak-topeak)
±0.30
-200
-400
-200
-400
Source
Sink
Dynamic Range (Note 2)
Additional
Magnitude
Response Test
Points (Note 4)
4.0
Hz
dB
49.45±0.3% 49.45±1% 49.45±2.5% 49.45±0.3% 49.45±2.5%
99.35±0.3% 99.3S±1% 99_35 ± 1.25% 99.3S±0.3% 99.35 ± 1.25%
RL=10kfl
Maximum Output
Short Circuit
Current (Note 6)
2.S
20
15
10
Roouree:;;: 2 kfl
fCLK!fe• Clock to
Cutoff Frequency
Ratio
0.1
10k
0_1
5k
0.1
10k
0.1
5k
mV
+1.S
-2.2
+1.0
-1.7
+1.0
-1.5
+1.S
-2.2
+1.0
-1.5
V
28
O.S
40
1.0
50
1_5
28
O.S
50
1.5
rnA
77
77
dB
MFS-50 fCLK = 2S0 kHz
1=6000 Hz
f=4500 Hz
-9.S4
-0.96
-9.S4±0.S -9.54±0.65
-0.9S±0.2 -0.96±0.3
-9.54
-0.9S
-9_54±0.65
-0.96±0.3
dB
MFS-l00 fCLK = 2S0 kHz
1=3000 Hz
1=22S0 Hz
-9.67
-1.01
-9.S7±0.S -9.67±0.65
-1.01 ±0.2 -1.01±0_3
-9.S7
-1.01
-9.67±0_65
-1.01±0.3
dB
MFS-SO fCLK = 250 kHz
f, =6000 Hz
12=8000 Hz
-36
-36
-36
dB!
octave
MF6-100 ICLK = 2S0 kHz
f, =3000 Hz
f2=4000 Hz
-3S
-36
-36
dB!
octave
1-43
II
Op Amp Electrical Characteristics
Boldface limits apply for TMIN to TMAXi all other limits T A = TJ = 25'C.
MF6CN·50, MF6CN·100,
MF6CWM·50, MF6CWM·100
Parameter
Condltlon8
MF6CJ·50, MF6CJ·100
Typical
(Note 8)
Te8ted
Limit
(Note 9)
De81gn
Umit
(Note 10)
Typical
(Note 8)
Te8ted
Umlt
(Note 9)
±8.0
±20
±20
±8.0
±20
De81gn
Limit
(Note 10)
Unlt8
V+ = +5V, V- = -5V
Input Offset Voltage
Input Bias Current
10
CMRR (Op Amp #2 Only)
VCM1 = 1.8V,
VCM2 = -2.2V
Output Voltage Swing
RL =10 kn
mV
pA
10
60
55
+4.0
-4.5
+3.8
-4.0
Maximum Output Short Source
Circuit Current (Note 6)
Sink
54
2.0
65
4.0
Slew Rate
7.0
DC Open Loop Gain
72
Gain Bandwidth Product
1.2
60
55
dB
+3.8
-4.0
+4.0
-4.5
+3.8
-4.0
V
80
8.0
54
2.0
80
8.0
rnA
7.0
85
V//J-s
85
72
1.2
dB
MHz
V+ = +2.5V, V- = -2.5V
Input Offset Voltage
±20
±8.0
Input Bias Current
±20
10
CMRR (Op·Amp #2 Only)
VCM1 = +0.5V,
VCM2 = -0.9V
Output Voltage Swing
RL = 10kn
±8.0
±20
mV
pA
10
60
55
+1.5
-2.2
+1.3
-1.7
Maximum Output Short Source
Circuit Current (Note 6)
Sink
24
1.0
35
2.0
Slew Rate
6.0
DC Open Loop Gain
67
Gain Bandwidth Product
1.2
60
55
dB
+1.1
-1.7
+1.5
-2.2
+1.1
-1.7
V
50
4.0
24
1.0
50
4.0
rnA
6.0
80
67
1.2
1-44
V//J-s
80
dB
MHz
Logic Input-Output Electrical Characteristics The following specifications apply for V(see Note 5) unless otherwise specified. Boldface limits apply for T MIN to T MAX; all other limits T A
MF6CN-SO, MF6CN-100
MF6CWM-SO, MF6CWM-100
Parameter
Conditions
=
TJ
=
=
OV
25°C.
MF6CJ-SO, MF6CJ-100
Tested
limit
(Note 9)
Design
limit
(Note 10)
Maximum VIL, Logical "0"
Input Voltage
0.8
0.8
0.8
V
Minimum VIH, Logical "1"
Input Voltage
2.0
2.0
2.0
V
2.0
2.0
2.0
IJ.A
Typical
(Note 8)
Typical
(Note 8)
Tested
Limit
(Note 9)
Design
Limit
(Note 10)
Units
TTL CLOCK INPUT, ClK R PIN (Note 7)
Maximum Leakage Current
atCLKR Pin
LShPinat
Mid-Supply
SCHMITT TRIGGER
VT +. Positive Going
Threshold Voltage
VT -. Negative Going
Threshold Voltage
Hysteresis (VT + -
VT -)
Min V+
Max
=
10V
7.0
6.1
8.9
6.1
8.9
7.0
6.1
8.9
V
Min
Max
V+
=
5V
3.5
3.1
3.1
4.4
3.5
3.1
4.4
V
Min
Max
V+
1.3
3.8
3.0
3.B
1.3
3.8
V
Min
Max
V+
=
5V
1.5
0.6
1.9
0.6
1.9
1.5
0.6
1.9
V
Min
Max
V+
=
10V
4.0
2.3
2.3
7.6
4.0
2.3
7.6
V
Min
V+
1.2
3.8
2.0
3.B
1.2
3.8
V
10V
5V
9.0
4.5
9.0
4.5
9.0
4.5
V
10V
5V
1.0
0.5
1.0
0.5
1.0
0.5
V
4.4
=
10V
3.0
1.3
7.6
=
5V
2.0
Max
Minimum Logical "1" Output
Voltage (Pin 11)
10
=
-1OIJ.A
V+
V+
Maximum Logical "0" Output
Voltage (Pin 11)
10
=
10"A
V+
V+
Minimum Output Source
Current (Pin 11)
CLK R Tied
to Ground
V+
V+
Maximum Output Sink
Current (Pin 11)
CLKRTied
toV+
V+
V+
=
=
=
=
=
=
=
=
1.2
10V
5V
6.0
1.5
3.0
0.75
3.0
0.75
6.0
1.5
3.0
0.75
rnA
10V
5.0
1.3
2.5
0.65
2.5
0.65
5.0
1.3
2.5
0.85
rnA
5V
Note 1: The cutoff frequency of the filter Is defined as the frequency where the magnitude response Is 3.01 dB less than the DC gain of the finer.
Note 2: For ±5V supplies the dynamic range Is referenced to 2.82 Vrms (4V peak) where the wldeband noise over a 20 kHz bandwidth is typically 200 ",Vrms for
the MF6-50 and 250 ",Vrms for the MF8·100. For ± 2.5V supplies the dynamic range Is referenced to 1.06 Vrms (1.5V peak) where the wldeband noise over a 20
kHz bandwidth is typically 140 '"Vrrns for both the MF6-50 and the MF6·100.
Nole 3: The spec~ications for the MF6 have been given for a clock frequency (fcLKl of 250 kHz and less. Above this clock frequency the cutoff frequency begins to
deviate from the specified error band of ± 1.0% but the filter still maintains Its magnitude characteristics. See Application Hints. Section 1.5.
Note 4: Besides checking the cutoff frequency (fe) and the stopband attenuation at 2 fe, two additional frequencies are used to check the magnnude response of
the finer. The magnitudes are referenced to a DC gain of 0.0 dB.
Note 5: For simplicity all the logic levels have been referenced to Vlevels).
= OV and will scale accordingly for ±5V and ± 2.5V supplies (exceptlor the TIL Input logic
Nole 6: The short circuit source current Is measured by forcing the output that Is being tested to Its maximum positive voltage swing and then shorting that output to
the negative supply. The short circuit sink current Is measured by forcing the output that Is being tested to Its maximum negative voltage swing and then shorting
that output
to the positive supply. These
are the worst-case conditions.
Note 7: The MF6 is operating with symmetrical split supplies and L.Sh Is tied to ground.
Note 8: Typicals are at 25'C and represent most likely parametric norm.
Note 9: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level.
Note 10: Design limits are guaranteed, but not 100% tested. The.. limits are not used to calculate outgoing quality levels.
Note 11: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when
operating the device beyond its speCified conditions.
Note 12: Human body model, 100 pF discharged through a 1.5k n resistor.
Note 13: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V- or VIN > V+) the absolute value of current at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four.
Note 14: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, 9JA, and the ambient temperature, TA. The
maximum allowable power dissipation at any temperature is Po = (TJMAX - TpJI9JA or the number given in the Absolute Maximum Ratings, whichever is lower.
For this device, TJMAX = 125'C, and the typlcallunctlon·to·amblent thermal resistance of the MF6CN when board mounted is 67'C/W. For the MF6CJ this number
decreases to 6Z'C/W. For MF6CWM, 9JA = 78'C/W.
1-45
II
:e::IE
Typical Performance Characteristics
Schmitt Trigger Threshold Voltage
vs Power Supply Voltage
13
V-=OV
12
TA=25"C
11
10
9
8
7
6
4
....
3
2
1
~~
Ed
~~
./
V
......
~~
q,..
",....
~~
i;
-
00:
"-0
~~
o
5
6
-.4Or-rTTTT1mr-rmmTr"TT1~~rmmI
-20 ro"M"T11mr-rm111lr"r---r-rmmI
~m- -~ H+HtttIt-+t+ttllHftI
v
5
Crosstalk from Either Op-Amp
to Filter Output (MF6-S0)
Crosstalk from Filter
to Op-Amps (MF6-100)
7
8
Ill)
9 10 11 12 13 14
V+ POWER SUPPLY VOLTAGE (V)
lK
Ill(
FREQUENCY (Hz)
FREQUENCY (Hz)
Crosstalk from Filter
to Op-Amps (MF6-S0)
-20 rrrmmrn-rmmrn,----r"TTm"l
Crosstalk from Either Op-Amp
to Filter Output (MF6-100)
t;
:teD
-40
';:-
,5.
;:::
500
-6)
§!
!!j
<400
0
-70
%
3Il)
~
200
tll
~;!;
s'li
J!:1
=>"-
00
~o
;!;
-60
~I0:
FREQUENCY (Hz)
lID(
700
-90
10
Ill)
IK
Ill(
FREQUENCY (Hz)
lID(
I
8
VS=10V
TA=25"C
GIll
~~
dS
1(1(
Equivalent Input NOise
Voltage of Op-Amps
-so
1:;"-
IK
@:
1:l~
~~
Ill)
-90 LLillJlllLl.l..ll.LillLLllLillIL.L1llillU
Ill)
Ill(
lID(
10
IK
lID(
Ill)
....
o
10
Ill)
IK
Ill(
lID(
FREQUENCY (Hz)
TLlH/5065-9
1-46
Typical Performance Characteristics (Continued)
Positive Voltage Swing vs
Power Supply Voltage
(Op Amp Output)
E
~
~
!:;
g
~
Ii'!
511
T.=25OC
5.4 R = 10kll
L
5.0
4.6
4.2
3.8
3.4
/
E
V
~
~
g
/
3.0
2.6
2.2
III
1.4
Positive Voltage Swing vs
Power Supply Voltage
(Filter Output)
~
,.- 1/
4.1
TA= 250C
3.7 'eLK = 250 kHZ
RL=10kll
~
~
./
5.0
~
~
!:lg
-3.2
-3.6
-4.0
-4,8
8.0
7.0
-.4.3
9.0
10.0
V
TEMPERATURE OC
Power Supply Current vs
Clock Frequency
4.90
1
ag;
"
i3
.
POWER SUPPLY VOLTAGE (V)
s.o
.s"<'
~
6
~
iil
i
4.7
2.0
TA =25OC
4AlJ
4.15
r-
3.90
Vs= 10V
....
.".
....
3.4Q
3.15
~
2.90
Ii'!
2.65 --.Vs=5V
2.40
-55 -35 -15 5 25 45 65 85 105 125
o 100 200 300 400 500 600 700 800 900 1000
TEMPERATURE (OC)
Power Supply Current
vs Temperature
CLOCK FREQUENCY (kHZ)
Power Supply Current
vs Power Supply Voltage
,
5.5
"
4.4
...1
3.8
.l.5
3.2
2.9
2.6
2.3
:t
iil
1/
4.65
3.65
~
/
I
'"
1/
V
M
./
5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0
1/
-55-35-155 25 45 65 85 105125
11.0
,.
Vs= 10v_1
'CLK = 250 kHZ
RL=10kll
1'1'..
-6..4
,
Negative Voltage Swing vs
Temperature (Filter and
Op Amp Outputs)
I'..
. --
311
6Jl
POWER SUPPLY VOLTAGE
T.=25OC
ftLK = 250 kHZ
RL= 10kll
"-
~
.....
/
3.9
1=
2.1
1.7
I'..
4.0
!:lg
2.5
Negative Voltage Swing vs
Power Supply Voltage
(Filter and Op Amp Outputs)
-2.11
4.1
!£
.J
Vs=10V
'tLK = 250 kHZ
RL=10kll
~
POWER SUPPLY VOLTAGE (V)
-2.4
E
2.9
5.0 6Jl 7.0 8.0 9.0 10.0 11.0 12.0 13.0
E
4.2
.......
/
3.3
Ii'!
'"
Positive Voltage Swing vs
Temperature (Filter and
Op Amp Outputs)
I'
5.1
Vs=10V
"-
D
""
'.
Vs=5V
...,..."
..... ..
-55-35-15 5 25 45 65 85 105125
5
6
7
8
9
10
11
12
13
POWER SUPPLY VOLTAGE (V)
TEMPERATURE (OC)
TLiH/5065-35
1-47
~
==
Typical Performance Characteristics (Continued)
felK/fe Deviation
vs Clock Frequency
3.0
-"
.....
II
~
0
~
0
;
felK/fe Deviation
vs Temperature
OJ!
D.6 Mrs-so .1,
TA=25"': _
w
~~~i~-
... ,
,
1.0
~
-1.0
-3.0 f- f-Vs =5V
-4D
-5.0
-6.D
II
,vs= lOY f-
~
1\
'\
-7.0
-8.0
RL=~1b. V~= 10V
0
--
-D.2
i~
0-
\I
..
-
I'- 1--0
-9.0
100 200 300 .fOO 500 600 700 IlOO 900 1000
,
-1.2
,
-1.4
-1.6
-106
-55 -35 -IS 5 25 -45 65 85 105 125
.
~
""
-1.0 -Vs=5V
::;;
-2.0
~
::
~..15
w
~
0
-
1.0
I
f--.
vs=~
-
1.0
5
S
::;
0.4
i
I
-6.D
-7.0
1/
,.,'\..V...... r-
V
"
-0.2
Vs=5V
-0.4
T.=25OC ..
'ClJ(= 250 kHZ
3.0 MrS-IOO
::;
""
w
i
1.0
:!i
/
,
'::'" .'
VSi,or-
-o.s
CLOCK FREQUENCY (kHZ)
12 13
II
L
-"
.....
I
I
r.....
-
5
S
I
-1.0
-DB
-55 -35 -IS 5 25 015 65 85 105 125
100 200 300 .fOO 500 600 700 IlOO 900 1000
10
9
felK/fe Deviation
vs Power Supply Voltage
,
O,S RL=10 kll
o.z
8
4.11
OJ! 'CLK = 250 kHZ
;
7
POWER SUPPLY VOLTAGE (V)
MrS-IOO
-"
.....
/
-1.0
felK/fe Deviation
vs Temperature
T.=25OC_
MrS-IOORL=I MlI-
.~
::;
TEMPERAlURE (OC)
felK/fe Deviation
vs Clock Frequency
1.0
T.=25OC ..
'ClJ(= 250 kHZ
3.0 Mrs-so
tll
---;
-1.0
L
-"
.....
II
"
Vs~';~ -
CLOCK rREQUENCY (kHZ)
;:;:
4.11
,
'ClJ( = 250 kHZ
~ ~
::;
-w
felK/fe Deviation
vs Power Supply Voltage
TEMPERAlURE (OC)
7
8
10 11
9
12 13
POWER SUPPLY VOLTAGE (V)
TLlH/506S-36
DC Gain Deviation
vs Temperature
0.12
0.D9
~
I
u
o.os
0.D3
~:~:5~0'kHi
DC Gain Deviation
vs Power Supply Voltage
T.=25OC .. L
,
1 1
0.08
o.os 'CLK = 250 kHZ
0.04 Mrs-so
0.02 RL= 10kll
::-:~--r--.( )-~V~
sty
....
'\Ly
tll
/I~
-0.02
a!: -0.04
<1 -0.D6
g -0.08
RL=10kll-,
-o.D3
~ -o.os
v =',OJ
~
~
'"
g -o.os
JS I I
-0.12
1 1
-0.15
1 1
-55-35-15 5 25 015 65 85 105125
"
,
,
·
0
I
i
-0.02
~ -0.D4
~ -0.06
u
-0.08
g
-0.10
-0.12
~
-0.1.
-o.IS
1/k)'S=5V
I
.
I-r.
,/
Vs=IOY
1
0.4 f- -f-Vs =5V
~
g
o.z
'--
-D.2
-0.4
-0.6
-,
" ,
··
S
7
8
9
10 II
12 13
o 100 200 300 400 500 600 700 IlOO 900 1000
CLOCK FREQUENCY (kHZ)
RL=IOk~
tll -0.2
/
-
1/
1/
!
tll
~
-0.4
~
L
g
1 1
1 1
1 1
-55-35-15 5 25 -45 65 85105125
DC Gain Deviation
vs Clock Frequency
,.,
.L
0.2 T.=25OC .
'ClJ( = 250 kHZ
MrS-IOO
~
/
..... 1/
r-""'"
-DB
-1.0
5
DC Gain Deviation
vs Power Supply Voltage
1-1--:- -_R~::1~~~HZ_
=10kll
TEMPERAlURE (OC)
tll
~
POWER SUPPLY VOLTAGE (V)
VI
--.J.
~s="O?r-
....
-0.10
-0.12
DC Gain Deviation
vs Temperature
o
-
1.2
T =25OC
1.0 A
Mrs-so
OJ!
D.6
~
/
TEMPERAlURE (OC)
0.02
J
DC Gain Deviation
vs Clock Frequency
1.2
TA=25OC
1.0
MrS-l00
OJ!
I
D.6
-
~s='l0J~1:::
I"
0.4 f- -f-Vs =5V
o.z
0
-D.2
-0.4
......
/
1/
-0.6
-006
-o.B
-1.0
-0.10
5
S
7
8
9
10 II
12 13
POWER SUPPLY VOLTAGE (V)
o 100 200 3OO.fOO 500 600 700 IlOO 900 1000
CLOCK rREQUENCY (kHZ)
TL/H/S05S-39
1-48
Crosstalk Test Circuits
From Filter to Opamps
20Hz-20kHz
tvRWS
TL/H/S06S-l0
From Either Opamp to Filter Output
20Hz-20kHz '"
lVRWS
TL/H/S06S-ll
Pin Descriptions (Pin Numbers)
Pin
FilTER OUT (3)
FilTER IN (8)
VOsADJ (7)
AGND(5)
V01 (4),
INV1 (13)
Description
The output of the lowpass filter.
It will typically sink 0.9 rnA and
source 3 mA and swing to within
1V of each supply rail.
The input to the lowpass filter.
To minimize gain errors the
source impedance that drives
this input should be less than 2k
(see section 1.4). For Single
supply operation the input signal
must be biased to mid-supply or
ACcoupled.
This pin is used to adjust the DC
offset of the filter output; if not
used it must be tied to the
AGND potential. (See section
1.3)
The analog ground pin. This pin
sets the DC bias level for the
filter section and the noninverting input of Op-Amp # 1
and must be tied to the system
ground for split supply operation
or to mid-supply for single
supply operation (see section
1.2). When tied to mid-supply
this pin should be well
bypassed.
V01 is the output and INV1 is
the inverting input of Op-Amp
# 1. The non-inverting input of
this Op-Amp is internally
connected to the AGND pin.
Pin
V02(2),
INV2(14),
NINV2(1)
Description
V02 is the output, INV2 is the
inverting input, and NINV2 is the
non-inverting input of Op-Amp
V+(6), V-(1O)
The positive and negative
supply pins. The total power
supply range is 5V to 14V.
Decoupling these pins with
0.1 ",F capacitors is highly
recommended.
A CMOS Schmitt-trigger input to
be used with an external CMOS
logic level clock. Also used for
self-clocking Schmitt-trigger
oscillator (see section 1.1).
A TTL logic level clock input
when in split supply operation
(± 2.5V to ± 7V) and L. Sh tied
to system ground. This pin
becomes a low impedance
output when L. Sh is tied to V - .
Also used in conjunction with
the ClK IN pin for a self
clocking Schmitt-trigger
oscillator (see section 1.1).
level shift pin, selects the logic
threshold levels for the desired
clock. When tied to V- it
enables an internal tri-state
buffer stage between the
Schmitt trigger and the internal
clock level shift stage thus
enabling the ClK IN Schmitttrigger input and making the
ClK R pin a low impedance
output.
#2.
ClKIN (9)
ClK R (11)
L. Sh (12)
1-49
II
Pin Descriptions (Pin Numbers) (Continued)
Pin
L. Sh (cont.)
Description
When the voltage level at this
input exceeds [25%(V+ - V-)
+ V-] the internal tri-state
buffer is disabled allowing the
CLK R pin to become the clock
input for the internal clock level
shift stage. The CLK R
threshold level is now 2V above
the voltage applied to the L. Sh
pin. Driving the CLK R pin with
TTL logic levels can be
accomplished through the use
of split supplies and by tying the
L. Sh pin to system ground.
3.01 dB below the DC gain) a direct ratio (100:1 or 50:1) of
the clock frequency supplied to the lowpass filter. Internal
integrator time constants set the filter's cutoff frequency.
The resistive element of these integrators is actually a capacitor which is "switched" at the clock frequency (for a
detailed discussion see Input Impedance Section). Varying
the clock frequency changes the value of this resistive element and thus the time constant of the integrators. The
clock to cutoff frequency ratio (fClK/fel is set by the ratio of
the input and feedback capacitors in the integrators. The
higher the clock to cutoff frequency ratio (or the sampling
rate) the closer this approximation is to the theoretical Butterworth response. The MFS is available in fClK/fe ratios of
50:1 (MFS-50) or 100:1 (MFS-100).
1.1 CLOCK INPUTS
The MFS has a Schmitt-trigger inverting buffer which can be
used to construct a simple R/C oscillator. The oscillator's
frequency is dependent on the buffer's threshold levels as
well as on the resistor/capacitor tolerance (see Figure 1).
1.0 MF6 Application Hints
The MFS is comprised of a non-inverting unity gain lowpass
sixth order Butterworth switched capacitor filter section and
two undedicated CMOS Op-Amps. The switched capacitor
topology makes the cutoff frequency (where the gain drops
C
R
r-11-----1--Wv----,
ClK IN
to VfelK
1
RCln[ (Vee - VT- )VT+
Vee - VT+ VTTypically for Vee ~ V+ - V- ~ 10V:
ClK R
11
9
~
1
1
felK ~ 1.69 RC
MF6
Tl/H/S06S-12
FIGURE 1. Schmitt Trigger RIC Oscillator
N.INV2
V02
FilTER OUT
VOl
AGND
+5.0V
y+
VosADJ
14
INV2
2
13
3
12
INVI
L.Sh
4
11
5
10
6
9
7
8
N.INV2
V02
ClKR
VClKIN
FILTER
IN
-5.0V
JUl+5V
-SV
+5.0V
FilTER OUT
VOl
AGND
V+
VosADJ
14
INV2
2
13
3
12
INVI
L.Sh
4
11
5
10
JUlSV
OV
-S.OV
6
7
8
Tl/H/5065-4
TUH/S06S-3
FIGURE 3. Dual Supply Operation
MF6 Driven with TTL Logic Level Clock
FIGURE 2. Dual Supply Operation
MF6 Driven with CMOS Logic Level Clock
(V'H ;" 0.8 Vee and V,l ,,; 0.2 Vee where Vee = y+ - y-)
1-50
s:::
Application Hints
."
CD
(Continued)
VOSADJ
OV
7
A
I
I~
0.1 J.LF
JUL
10V
OV
CMOS
CLOCK
LEVELS
TL/H/5065-14
a) Resistor Biasing of AGND
Vas ADJ
7
MF6
II
JUL
0.1 J.LF
10V
OV
CMOS
CLOCK
LEVELS
TLlH/5065-15
b) Using Op-Amp 2 to Buffer AGND
FIGURE 4. Single Supply Operation
1-51
~
:::::!!!
Application Hints (Continued)
24k.o.
Sk.o.
22k.o.
V-~V+
FilTER
OUT
VOSADJ
7
3
FilTER
Vos
IN
ADJ
filTER
OUT
3
7
8
STH ORDER
BUTTERWORTH
filTER
6 TH ORDER
BUTTERWORTH
filTER
MFS
OP-AMPI/l
(a)
AGND
TUH/5065-16
(b)
TL/H/5065-17
FIGURE 5. Vos Adjust Schemes
Schmitt-trigger threshold voltage levels can change significantly causing the RIC oscillator's frequency to vary greatly
from part to part.
FilTER
Where accuracy in fe is required an external clock can be
used to drive the ClK R input of the MF6. This input is TIL
logic level compatible and also presents a very light load to
the external clock source (- 2 /LA) with split supplies and
L. Sh tied to system ground. The logic level is programmed
by the voltage applied to level shift (L. Sh) pin (See the Pin
description for l. Sh pin).
INPUT
r-VI/\,..-e---j
TLlH/5065-18
a) Equivalent Circuit for MF6 Filter Input
1.2 POWER SUPPLY BIASING
The MF6 can be biased from a single supply or dual split
supplies. The split supply mode shown in Figures 2 and 3 is
the most flexible and easiest to implement. As discussed
earlier split supplies, ± 5V to ± 7V, will enable the use of
TIL or CMOS clock logic levels. Figure 4 shows two
schemes for single supply biasing. In this mode only CMOS
clock logic levels can be used.
1.3 OFFSET ADJUST
The VosADJ pin is used in adjusting the output offset level
of the filter section. If this pin is not used it must be tied to
the analog ground (AGND) level, either mid-supply for single
ended supply operation or ground for split supply operation.
This pin sets the zero reference for the output of the filter.
The implementation of this pin can be seen in Figure 5. In
5(a), DC offset is adjusted using a potentiometer; in 5(b), the
Op-Amp integrator circuit keeps the average DC output level at AGND. The circuit in 5(b) is therefore appropriate only
for AC-coupled signals and signals biased at AGND.
TL/H/5065-19
b) Actual Circuit for MF6 Filter Input
FIGURE 6. MF6 Filter Input
transferred to the feedback capacitor. The total transfer of
charge in one clock cycle is therefore = CinVin, and since
current is defined as the flow of charge per unit time the
average input current becomes
a
1.4 INPUT IMPEDANCE
The MF6 lowpass filter input (FilTER IN pin) is not a high
impedance buffer input. This input is a switched capacitor
resistor equivalent, and its effective impedance is inversely
proportional to the clock frequency. The equivalent circuit of
the input to the filter can be seen in Figure 6. The input
capacitor charges to the input voltage (Vin) during one half
of the clock period, during the second half the charge is
lin = OIT
(where T equals one clock period) or
lin
CinVin
= - T - = CinVinfCLK
The equivalent input resistor (Rin) then can be defined as
1
Rin = Vin/lin = - C
f
in ClK
The input capacitor is 2 pF for the MF6-50 and 1 pF for the
1-52
.--------------------------------------------------------------,~
-n
Application Hints
en
(Continued)
MFB-l00, so for the MFB-l00
1 X 1012
1 X 1012
1 X 1010
fCLK
fe X 100
fe
5 X 1011
5 X 1011
1 X 1010
Since the maximum overall gain error for the MFB is
± 0.3 dB with a Rs ,,; 2 kO the actual gain error for this case
would be +0.21 dB to -0.39 dB.
R· = - - - = - - - = - - on
1.5 CUTOFF FREQUENCY RANGE
The filter's cutoff frequency (fel has a lower limit caused by
leakage currents through the internal switches discharging
the stored charge on the capacitors. At lower clock frequencies these leakage currents can cause millivolts of error, for
example:
and
R- = - - - = - - - = - - -
fCLK
fe X 50
fe
for the MFB-50. As shown in the above equations for a given
cutoff frequency (fel the input impedance remains the same
for the MFB-50 and the MFB-l00. The higher the clock to
center frequency ratio, the greater equivalent input resistance for a given clock frequency. As the cutoff frequency
increases the equivalent input impedance decreases. This
input resistance will fOI m a voltage divider with the source
impedance (Rsouree). Since Rin is inversely proportiona! to
the cutoff frequency, operation at higher cutoff frequencies
will be more likely to load the input signal which would appear as an overall decrease in gain to the output of the filter.
Since the filter's ideal gain is unity its overall gain is given
by:
on
1 pA
V = 1 pF (100 Hz) = 10 mV
The propagation delay in the logic and the settling time required to acquire a new voltage level on the capacitors increases as the MFB power supply voltage decreases. This
causes a shift in the fCLK/fe ratio which will become noticeable when the clock frequency exceeds 250 kHz. The amplitude characteristic will stay within tolerance until fCLK exceeds 500 kHz and will peak at about 0.5 dB at the corner
frequency with a 1 MHz clock. The response of the MFB is
still a reasonable approximation of the ideal Butterworth
lowpass characteristic as can be seen in Figure 7.
Rin
A -
+
Rin
v -
fCLK = 100 Hz, Ileakage = 1 pA, C = 1 pF
Rsource
If the MFB-50 or the MFB-l00 were set up for a cutoff frequency of 10kHz the input impedance would be:
2.0 Designing with the MF6
Given any lowpass filter specification two equations will
come in handy in trying to determine whether the MF6 will
do the job. The first equation determines the order of the
lowpass filter required:
1 X 1010
Rin = 10kHz = 1 MO
In this example with a source impedance of 10k the overall
gain, if the MFB had an ideal gain of 1 or 0 dB, would be:
n=
1 MO
Av = 10 kO + 1 MO = 0.99009 or - 8B.4 mdB
log (10°·1 Amin_l) -log (100.1 Amax - l )
(1)
2 log (fs/fb)
10
0
-10
2
-Zl
i!l
-30
~
~
~
-«I
~
\ 1l
s ~~
W \ i~~ ~-~ \~
\
-50
.1
-00
\
-70
i
.1
I
i
-so
10
.1
i
.1
-50
1
\
J
I1I1
II I
-70
51(
50
5IXl
lK
100
Ill<
FREQUENCY (Hz)
-so
5a<
50
10
lOll<
II
1\
-ill
51(
5IXl
100
lK
Ill<
FREQUENCY (Hz)
5a<
lOll<
TLlH/506S-20
TL/H/S06S-21
FIGURE 7a. MF6·100 ± 5V Supplies
Amplitude Response
10
0
~Id
.I~~
-Zl r--~
! -30
r--\1i
i\
-10
i
~
-«I
.1
-50
I
-60
j
-70
-so
10
50
.1
I
FIGURE 7b. MF6·50 ± 5V Supplies
Amplitude Response
rI
~
~
~
"'
1\
jI~
51(
5IXl
100
lK
Ill<
FREQUENCY (Hz)
-1~ ~I-I.~
~!!. _I~
~
s
m- ..2IJ!!"
~\1i-
'"
-30"
0
\1i
\ )\
-<0
-50
-60
-70
t-
\1i
\
\
1---+4-++-II-tII ...1..f-l
I---tt+-M-ttt-II-t-l
-so '---:50!:"-.....5IXl!:¥---:5I('::l'-----.5a<'""
50K
10
lOll<
TL/H/5065-22
100
lK
Ill<
FREQUENCY (Hz)
lOll<
TL/H/5065-23
FIGURE 7c. MF6·100 ± 2.5V Supplies
Amplitude Response
FIGURE 7d. MF6·50 ± 2.5V Supplies
Amplitude Response
1-53
~
::E
Designing with the MF6 (Continued)
where n is the order of the filter, Amin is the minimum stopband attenuation (in dB) desired at frequency fs, and Amax is
the passband ripple or attenuation (in dB) at frequency fb. If
the result of this equation is greater than 6, then more than
a single MF6 is required.
The attenuation at any frequency can be found by the following equation:
Attn(f) = 10 log [1
+ (100.1Amax_l) (flfb)2n] dB
To implement this example for the MF6-50 the clock frequency will have to be set to feLK = 50(1.116 kHz) = 55.8
kHz or for the MF6-100 feLK = 100(1.116 kHz) = 111.6
kHz.
2.2 CASCADING MF6s
In the case where a steeper stopband attenuation rate is
required two MF6's can be cascaded (Figure 9) yielding a
12th order slope of 72 dB per octave. Because the MF6 is a
Butterworth filter and therefore has no ripple in its passband, when MF6s are cascaded the resulting filter also has
no ripple in its passband. Likewise the DC and passband
gains will remain at 1VIV. The resulting response is shown
in Figure 10.
In determining whether the cascaded MF6s will yield a filter
that will meet a particular amplitude response specification,
as above, equations 3 and 4 can be used, shown below.
(2)
where n = 6 (the order of the filter).
2.1 A LOWPASS DESIGN EXAMPLE
Suppose the amplitude response specification in Figure 8 is
given. Can the MF6 be used? The order of the Butterworth
approximation will have to be determined using eq. 1:
Amin = 30 dB, Amax = 1.0 dB, fs = 2 kHz, and fb = 1 kHz
n=
log (103 - 1) -log(100.1 - 1)
2 log(2)
= 5.96
n =
Since n can only take on integer values, n = 6. Therefore
the MF6 can be used. In general, if n is 6 or less a single
MF6 stage can be utilized.
log (10°. 05 Amin-l) - log (10°.05 Amax -l)
2 log (fslfb)
Attn(f) = 10 log [1
+ (10°.05 Amax -
l ) (flfb)2n] dB
(3)
(4)
where n = 6 (the order of each filter).
Likewise, the attenuation at fs can be found using equation
2 with the above values and n = 6 giving:
Alten (2 kHz) = 10 log [1 + (100.1 - 1) (2 kHz/l kHz)12]
= 30.26 dB
Equation 3 will determine whether the order of the filter is
adequate (n ~ 6) while equation 4 can determine if the
required stopband attenuation is met and what actual cutoff
frequency (fel is required to obtain the particular frequency
response desired. The design procedure would be identical
to the one shown in section 2.1.
This result also meets the design specification given in Figure 8 again verifying that a single MF6 section will be adequate.
2.3 IMPLEMENTING A "NOTCH" FILTER WITH THE MF6
A "notch" filter with 60 dB of attenuation can be obtained by
using one of the Op-Amps, available in the MF6, and three
external resistors. The circuit and amplitude response are
shown in Figure 11.
The frequency where the "notch" will occur is equal to the
frequency at which the output Signal of the MF6 will have
the same magnitude but be 180 degrees out of phase with
its input signal. For a sixth order Butterworth filter 180·
phase shift occurs where f = fn = 0.742 fc. The attenuation
at this frequency is 0.12 dB which must be compensated for
by making R1 = 1.014 X R2.
fb=lk
Since Rl does not equal R2 there will be a gain inequality
above and below the notch frequency. At frequencies below
the notch frequency (f < < f n), the signal through the filter
has a gain of one and is non-inverting. Summing this with
the input signal through the Op-Amp yields an overall gain
of two or + 6 dB. For f > > fn' the signal at the output of the
filter is greatly attenuated thus only the input signal will appear at the output of the Op-Amp. With R3 = R1 = 1.014
R2 the overall gain is 0.986 or -0.12 dB at frequencies
above the notch.
f.=2k
FREQUENCY (Hz)
TUH/5065-24
FIGURE 8. Design Example Magnitude Response
Specification Where the Response of the Filter Design
Must Fall Within the Shaded Area of the Specification
Since the MF6's cutoff frequency fe, which corresponds to a
gain attenuation of -3.01 dB, was not specified in this example it needs to be calculated. Solving equation 2 where f
= fc as follows:
fc = fb
[
(100.1(3.01 dB) - 1)]1/(2n)
(100.1 Amax _ 1)
= 1 kHz
[
100.301 - 1 ]1/12
100.1 _ 1
= 1.119kHz
where fc = feLK/50 or feLK/l00.
1-54
Designing with the MF6 (Continued)
MF6
MF6
3....
.... 8
....
....
FILTER FILTER
OUT
IN
("1.!.1-....
FILTER
IN
VOSADJ AGND
7
5
v+
LSh
V_
r2
CLKR
10
3 ....
....
FILTER
OUT
VosADJ AGND
11
7
-==
5
LSh
J
V+
6
12
V_ CLKR
10
11
O.IJ'F*
v+=+5Vo-----------~--t_--t_------------~~_i------~
O.I~F=r
V_=-5Vo---------------~--t_----------------~~--------~
fCLK
>-----------------~~---------------------------------I
TIL LOGIC LEVELS
TUH/5065-25
FIGURE 9. Cascading Two MF6s
10r--r.-nnTmr---~=_~
o l-+~f++~c-V.cr:::.......-V-=IOV
-10
~
f.,k =50kHz
1\\
1
~
-~r-_r~rH~HHM_~~~
3
-30
~~SINGLE
\
t;:
-40 t--+-I-+t+tttt-~
\\rl-t+HtH
-50 t--+-I-+t+tttt--\\+\!-I-ttttH
iii
""~
-OO~~~~~,~IH+\#ffl
-70 r-+-t::\+l-t:H+--t-!-+HtItf
-00 r-_r+-TW~OHM+Ftt6sf_---..:___1H__l\I+H+l
i 1u.J.11IIIL---J..:...i\.J...J...J.-U..W
-90 '--"--'-.J...J
II...J..J
0.1
1
5
10
=
OO_~ f. ,k 50 kHz
-1800 Vcc=V+-V-= 10V
-3600
-
IL
-5400
o
O.~k
'!
1.0k
FREQUENCY (Hz)
TUH/50B5-27
FREQUENCY (kHz)
TUH/50B5-26
FIGURE lOb. Phase Response of
Two Cascaded MF6·50s
FIGURE lOa. One MF6·50 vs. Two MF6·50s Cascaded
1-55
II
~
::IE
Designing with the MF6
(Continued)
VOSADJ
MF6
I----+< 5Vs
0V
R3
fCLK
R2
Rl
SIGNAL
INPUT
~""'
-+_______....J
______
" NOTCH"
FILTER OUTPUT
TL/H/S065-2B
FIGURE 118. "Notch" Filter
+10
tr=ltI5i~YI
o
f clkI": 10kHz
-40
-so
10
50
100
500
lK
FREQUENCY (Hz)
TLiH/5065-29
FIGURE 11 b. MF6·50 "Notch" Filter Amplitude Response
1·56
Designing with the MF6
(Continued)
2.4 CHANGING CLOCK FREQUENCY
INSTANTANEOUSLY
The MFS will respond favorably to a sudden change in clock
frequency. Distortion in the output signal occurs at the transition of the clock frequency and lasts approximately three
cutoff frequency (fe) cycles. As shown in Figure 12, if the
control signal is low the MFS-50 has a 100 kHz clock making fe = 2 kHz; when this signal goes high the clock frequency changes to 50 kHz yielding 1 kHz f e.
The transient response of the MFS seen in Figure 13 is also
dependent on the fe and thus the fCLK applied to the filter.
The MF6 responds as a classical sixth order Butterworth
lowpass filter.
TLlH/5065-31
FIGURE 13. MF6-50 Step Input Response, Vertical =
2V/div., Horizontal = 1 ms/div., fClK = 100 kHz
the input signal contains a component at a frequency higher
than half the clock frequency, as in Figure 14a, that component will be "reflected" about fCLK/2 into the frequency
range below fCLK/2 as in Figure 14b. If this component is
within the passband of the filter and of large enough amplitude it can cause problems. Therefore if frequency components in the input signal exceed fCLK/2 they must be attenuated before being applied to the MFS input. The necessary
amount of attenuation will vary depending on system requirements. In critical applications the signal components
above fCLK/2 will have to be attenuated at least to the filter's residual noise level. An example circuit is shown in
Figure 15 using one of the uncommitted Op-Amps available
in the MFS.
TLlH/5065-30
fiN ~ 1.5 kHz (scope time base ~ 2 ms/div)
FIGURE 12. MF6-50 Abrupt Clock Frequency Change
2.5 ALIASING CONSIDERATIONS
Aliasing effects have to be taken into consideration when
input signal frequencies exceed half the sampling rate. For
the MFS this equals half the clock frequency (fCLK)' When
II
Is
2
~+I
~-I
Is
2
2
IS
2
~+I
IS
2
FREQUENCY
FREQUENCY
TLlH/5065-37
TLlH/5065-38
(a) Input Signal Spectrum
(b) Output Signal Spectrum. Note that the input signal at
f5/2 + f causes an output signal to appear at f5/2 - f.
Figure 14. The phenomenon of aliasing in sampled-data systems. An input signal whose frequency is greater than onehalf the sampling frequency will cause an output to appear at a frequency lower than one-half the sampling frequency.
In the MF6, fs = fClK.
1-57
:e~
Designing with the MF6 (Continued)
VOSADJ
7
WF6
VOUT
FILlER 8
IN
C2
R4
R1
R2
R3
INV1
TLIHIS06S-34
10
=
Ho
1
2".,lRIR2CI~
= R,1R3 (Ho =
1 when R3 and R. are omitted and V02 is directly tied to INV2).
Design Procedure:
pickCI
R2=_I_
20CI"'0
lor a 2nd Order Butterworth 0
R2
= 0.707
= 0.113
Clio
make RI
= R2
and
C2
=
1
(2".loRIl2CI
Note: The parallel combination 01 R, (il used), RI and R2 should be ;, 10 kG In order not to load Op-Amp #2.
FIGURE 15_ Second Order Butterworth Anti-Aliasing Filter Using Uncommitted Op-Amp #2
1-58
NatiOnal
~ Semiconductor
Corporation
MFa 4th-Order Switched Capacitor Bandpass Filter
General Description
Features
The MF8 consists of two second-order bandpass filter
stages and an inverting operational amplifier. The two filter
stages are identical and may be used as two tracking second-order bandpass filters, or cascaded to form a single
fourth-order bandpass filter. The center frequency is controlled by an external clock for optimal accuracy, and may
be set anywhere between 0.1 Hz and 20 kHz. The ratio of
clock frequency to center frequency is programmable to
100:1 or 50:1. Two inputs are available for TTL or CMOS
clock signals. The TTL input will accept logic levels referenced to either the negative power supply pin or the ground
pin, allowing operation on single or split power supplies. The
CMOS input is a Schmitt inverter which can be made to selfoscillate using an external resistor and capacitor.
By using the uncommitted amplifier and resistors for negative feedback, any all-pole (Butterworth, Chebyshev, etc.)
filter can be formed. This requires only three resistors for a
fourth-order bandpass filter. 0 of the second-order stages
may be programmed to any of 31 different values by the five
"0 logic" pins. The available 0 values span a range from
0.5 through 90. Overall filter bandwidth is programmed by
connecting the appropriate 0 logic pins to either V+ or V-.
Filters with order higher than four can be built by cascading
MF8s.
• Center frequency set by external clock
• 0 set by five-bit digital word
• Uncommitted inverting op amp
• 4th-order all-pole fillers using only three external
resistors
• Cascadable for higher-order filters
• Bandwidth, response characteristic, and center
frequency independently programmable
• Separate TTL and CMOS clock inputs
• 18 pin 0.3" wide package
Key Specifications
• Center frequency range 0.1 Hz to 20 kHz
• 0 range 0.5 to 90
• Supply voltage range 9V to 14V (±4.5V to ±7V)
• Center frequency accuracy 1% over full temperature
range
Typical Application & Connection Diagrams
Dual-In-Line Package
120k!l
VOUT
30k!l
30k!l
A
+5V
+5V
..JLSLr
18
D
17
E
16
Fl IN
AGND
4
15
F1 OUT
A OUT
F2 IN
5
14
F2 OUT
6
13
A IN
TTl CLK
7
12
V+
CMOS CLK
11
V-
RC
10
50/100
TLlH/8694-2
-5V
CLOCK IN
-5V
+5V
Order Number MFBCCJ
orMFBCCN
See NS Package Number
J18A or N18A
-5V
Tl/H/8694-1
Fourth-Order Butterworth Bandpass Filter
1-59
Top View
II
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (Vs = V+ - V-I
-0.3Vto +15V
Voltage at any Input (Note 2)
V- -0.3VtoV+ +0.3V
Input Current at any Input Pin (Note 2)
±1 mA
Output Short-Circuit Current (Note 7)
±1 mA
Power Dissipation (Note 3)
500mW
Storage Temperature
-65'C to + 150'C
Soldering Information:
J Package:
10 sec.
260'C
N Package:
10 sec.
300'C
SO Package:
Vapor Phase (60 sec.)
215'C
Infrared (15 sec.)
220'C
ESD rating is to be determined.
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.
Operating Ratings (Note 1)
Temperature Range
TMIN ,,; TA"; TMAX
MF8CCN
O'C,,; TA"; +70'C
MF8CCJ
-40'C ,,; TA"; +85'C
Supply Voltage (Vs = V+ - V-I
+9Vto +14V
fCLK X 0 Range
for 10Hz"; fCLK ,,; 250 kHz
for 250 kHz,,; fCLK ,,; 1 MHz
any 0
fClK X 0 ,,; 5 MHz
Filter Electrical Characteristics The following specifications apply for V+ =
50 pF and RLOAD
TA = TJ = 25'C.
+ 5V, V- = -5V, CLOAD =
= fiO kD. on filter output unless otherwise specified. Boldface limits apply for TMIN to T MAX; all other limits
MF8CCN
Parameter
(Notes 4, 5)
Symbol
Ho
0
Gain atfo
R
fClK/fo
Gain atfo
Ho
0
R
Ho
0
R
Ho
0
0
fCLK/fo
Gain atfo
0
fCLK/fo
Gainatfo
aO/OTH o Deviation from
Theoretical
(See Table I)
Conditions
fClK = 250 kHz
100:1
ABCDE = 11100
fClK = 250 kHz
100:1
ABCDE = 10011
fCLK = 250 kHz
50:1
ABCDE = 00001
Vs = ±5V ±5%
fClK ,,; 250 kHz
Vs = ±5V ±5%
fCLK ,,; 250 kHz, 0 > 1
fCLK"; 100 kHz,
1 < 0 < 57
aR/RTH fCLK/fo Deviation Vs = ±5V ±5%
from Theoretical fCLK ,,; 250 kHz
(See Table I)
0
0
fCLK = 250 kHz, 50:1
ABCDE = 00110
Dynamic Range ABCDE = 11100
ABCDE = 10011
(Note 6)
ABCDE = 00001
Clock
Feedthrough
Filter and Op Amp
fCLK ,,; 250 kHz
0,,; 1
0>1
IS
Maximum Supply fCLK = 250 kHz, no
Current
loads on outputs
Vos
Maximum Filter
Output Offset
Voltage
fCLK = 250 kHz, Q = 4
50:1
100:1
Minimum Filter
Output Swing
RLOAD = 5 kD.
(Note 6)
VOUT
Typical
(Note 9)
Tested
Limit
(Note 10)
MF8CCJ
Design
Limit
(Note 11)
Typical
(Note 9)
Tested
Limit
(Note 10)
6.02 ±.05 6.02 ±0.2
6.02 ±0.05 6.02 ±0.2
3.92 ±2% 3.92 ±6%
3.92 ±2%
99.2 ±0.3% 99.2 ±1%
dB
3.92 ±6%
99.2 ±0.3% 99.2 ±1%
6.02 ±0.2 6.02 ±0.5
6.02 ±0.2
6.02 ±0.5
15.5 ±3% 15.5 ±8%
15.5 ±3%
15.5 ±8%
dB
99.7 ±0.3% 99.7±1%
99.7 ±0.3% 99.7 ±1%
5.85 ±0.4
5.85 ± 1
5.85 ±0.4
5.85 ±1
55 ±5%
55 ±10%
55 ±5%
55 ±10%
49.9 ±0.2% 49.9 ±1%
6.02 ±0.5
Design Units
Limit
(Note 11)
dB
49.9 ±0.2% 49.9 ±1%
6.02 ±1.5 6.02 ±0.5
6.02 ±1.5 dB
±5%
±15%
±5%
±15%
±2%
±60.4
±2%
±60.4
±0.3%
± 1%
±0.3%
± 1%
10.6 ±2%
10.6 ±60.4 10.6 ±2% 10.6 ±80.4
86
80
75
86
80
75
dB
dB
dB
80
40
80
40
mV
mV
9
12
±40
±80
±120
±240
±4.1
±3.8
1-60
12
±3.8
9
13
mA
±40
±80
±120
±240
mV
mV
±4.1
±3.6
V
Op Amp Electrical Characteristics The following specifications apply for V+
= + 5V, V- = -5V and no
load on the Op Amp output unless otherwise specified. Boldface limits apply for T MIN to T MAX; all other limits T A = TJ = 25'C.
MF8CCN
Symbol
Parameter
Conditions
MF8CCJ
Typical
Tested
Design
Tested
Design
Typical
Units
Limit
Limit
Limit
Limit
(Note 9) (Note 10) (Note 11) (Note 9) (Note 10) (Note 11)
Vos
Maximum Input Offset Voltage
±8
Is
Maximum Input Bias Current
10
VOUT
Minimum Output Voltage Swing RLOAD
AVOl
Open Loop Gain
80
80
dB
GBW
Gain Bandwidth
Product
1.8
1.8
MHz
SR
Slew Rate
10
10
V/",s
= 5 kfl
±20
±8
±20
mV
10
±3.8
±3.5
±3.4
pA
±3.8
±3.1
Logic Input and Output Characteristics The following specifications apply for V+
V
= + 10V and V-
= OV unless otherwise specified. Boldface limits apply for T MIN to T MAX; all other limits T A = TJ = 25'C.
MF8CCN
Symbol
VT+
VT-
Parameter
VOL
10H
I~
10l
Conditions
Min Vs = V+ - V- referred
to V- = OV (Note 8)
0.7Vs
0.58Vs
Voltage on pin 8
Max
0.7Vs
0.89Vs
Negative Threshold
Min Vs = V+ - V- referred
to V- = OV (Note 8)
Max
0. 35Vs
0. 11Vs
0. 35Vs
0.47Vs
0. 35Vs
Positive Threshold
-
Voltage on pin 8
I~
Output Voltage on Min High
pin 9 (Note 12)
Max Low
Vil
Min High
Max Low
0. 89Vs
V
0. 11Vs
V
0.47Vs
V
9.0
9.0
V
10
= +10",A
1.0
1.0
1.0
V
Min High
pins: 1,2,3,10,
Max Low
17, & 18 (Note 12)
pin 7
0.7Vs
0.35Vs
9.0
Output Current on Min Source Pin 9 tied to Vpin 9
Pin 9 tied to V+
Min Sink
I~ Input Voltage on
V
= -10",A
6.0
3.0
6.0
3.0
mA
5.0
2.5
5.0
2.5
mA
7.0
9.0
7.0
9.0
V
3.0
1.0
3.0
1.0
V
Input Current on pins: 1, 2,
3,7,8,10,17, & 18
liN
0. 58Vs
0.7Vs
10
I~ Input Voltage on
Vil
MF8CCJ
Typical Tested Design Typical Tested Design Units
Limit
Limit
Limit
Limit
(Note 9) (Note 10 (Note 11) (Note 9) (Note 10) (Note 11)
V+ -- +10V, V- = OVor
V+ = +5V, V- = -5V
10
10
10
",A
2.0
2.0
2.0
V
0.8
0.8
0.8
V
Note 1: Absolute Maximum Raings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: When the applied voltage at any pin faUs outside the power supply voltages (VIN
limited to 1 rnA or less.
<
V- or VIN > V+), the absolute value of current at that pin should be
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T JMAX. 0JA, and the ambient temperature, T A. The maximum
allowable power dissipation at any temperature is Po = (TJMAX ~ TA)/0JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJMAX = 125°C, and the typical junction-to-ambient thermal resistance of the MF8CCN when board mounted is 50°C/W. For the MFBCCJ, this number
increases to 65°C/W.
Note 4: The center frequency of each 2nd-order filter section is defined as the frequency where the phase shift through the filter is zero.
Note 5: Q is defined as the measured center frequency divided by the measured bandwidth, where the bandwidth is the difference between the two frequencies
where the gain is 3 dB less than the gain meo.sured at the center frequency.
Note 6: Dyr,amic range is defined as the ratio of the tested minimum output swing of 2.75 Vrms (± 3.BV peak-to-peak) to the wide band noise over a 20 kHz
bandwidth. For Os of 1 or less the dynamic range and output swing will degrade because the gain at an internal node is 2/0. Keeping the input signal level below
1.23xO Vrms will avoid distortion in this case.
1-61
II
Note 7: If it is possible for a signal output (pin 6. 14. or 15) to be shorted to V+. V- or ground. add a series resistor to limit output current.
Note 8: If V- is anything other than OV then the value of V- should be added to the values given in the table. For example forV+ ~ +5V and V- ~ -5V the
typical VT+ ~ 0.7 (10V) + (-5V) ~ +2V.
Note 9: Typicals are at 25'C and represent the most likely parametric norm.
Note 10: Tested Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 11: Design
Lim~s
are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 12: These logic levels have been referenced to V-. The logic levels will shift accordingly for split supplies.
Pin Descriptions
Q logic Inputs
A,B,C,D,E
(3,2,1,18,17):
AGND(4):
y+ (12),
y- (11):
These inputs program the Os of the two
2nd-order bandpass filter stages. Logic
"1" is V+ and logic "0" is V-.
This is the analog and digital ground pin
and should be connected to the system
ground for split supply operation or biased to mid-supply for single supply operation. For best filter performance, the
ground line should be "clean".
These are the positive and negative
power supply inputs. Decoupling the
power supply pins with 0.1 ,...F or larger
capacitors is highly recommended.
F11N (16),
F21N (5):
These are the inputs to the bandpass filter stages. To minimize gain error the
source impedance should be less than 2
kfi. Input signals should be referenced
to AGND.
F1 OUT (15),
F20UT(6):
A IN (13):
These are the outputs of the bandpass
filter stages.
A OUT (14):
50/100 (10):
TTL ClK (7):
CMOS ClK (8):
RC(9):
This pin allows the MF8 to generate its
own clock signal. To do this, connect an
external resistor between the RC pin and
the CMOS Clock input, and an external
capacitor from the CMOS Clock input to
AGND. The TIL Clock input should be
connected to V- or V+. When the MF8
is driven from an external clock, the RC
pin should be left open.
1.0 Application Information
1.1 INTRODUCTION
A simplified block diagram for the MF8 is shown in Figure 1.
The analog signal path components are two identical 2ndorder bandpass filters and an operational amplifier. Each
filter has a fixed voltage gain of 2. The filters' cutoff frequency is proportional to the clock frequency, which may be applied to the chip from an external source or generated internally with the aid of an external resistor and capacitor. The
proportionality constant fClK/fo can be set to either 50 or
100 depending on the logic level on pin 10. The "0" of the
two filters can have any of 31 values ranging from 0.5 to 90
and is set by the logic levels on pins 1, 2, 3, 17, and 18.
Table I shows the available values of 0 and the logic levels
required to obtain them. The operational amplifier's non-inverting input is internally grounded, so it may be used only
for inverting applications.
This is the inverting input to the uncommitted operational amplifier. The non-inverting input is internally connected to
AGND.
This is the output of the uncommitted
operational amplifier.
This pin sets the ratio of the clock frequency to the bandpass center frequency. Connecting this pin to V+ sets the
ratio to 100:1. Connecting it to V- sets
the ratio to 50: 1.
This is the TTL-level clock input pin.
There are two logic threshold levels, so
the MF8 can be operated on either single-ended or split supplies with the logic
input referred to either V- or AGND.
When this pin is not used (or when
CMOS logic levels are used), it should
be connected to either V + or V - .
The components in the analog signal path can be interconnected in several ways, three of which are illustrated in Figures 2a, 2b and 2c. The two second-order filter sections can
be used as separate filters whose center frequencies track
very closely as in Figure 2a. Each filter section has a high
input impedance and low output impedance. The op amp
may be used for gain scaling or other inverting functions. If
sharper cutoff slopes are desired, the two filter sections
may be cascaded as in Figure 2b. Again, the op amp is
uncommitted. The circuit in Figure 2c uses both filter sections with the op amp and three resistors to build a "multiple
feedback loop" filter. This configuration offers the greatest
flexibility for fourth-order bandpass designs. Virtually any
fourth-order all pole response shape (Butterworth, Chebyshev) can be obtained with a wide range of bandwidths,
simply by proper choice of resistor values and O. The three
connection schemes in Figure 2 will be discussed in more
detail in Sections 1.4 and 1.5.
This pin is the input to a CMOS Schmitt
inverter. Clock Signals with CMOS logic
levels may be applied to this input. If the
TTL input is used this pin should be connected to V-.
1-62
Typical Performance Characteristics
fCLKlfo Ratio vs Clock
Frequency-50:1 Mode
50
100
0=90
0=15.8liI
49
99
,~,?
Vs=i5V
TA=2SOC
NO LOAD
-
~
III
,~
47
I I II
loS
98
lru
-
96
106
~
om 1-7-""".-1-
!C
IIII II
IIII
r--.---r:---r-:-:::-:""--,-,
/'
~
loS
is
125,t-
o.lS
~
!C
'CLK=
Vs=iSV
RL= 50 kll;----:
c,.=50pF
I
0.10
~-
~
Q=I
-0.03 '---'---'_-'---'_...1...--1
-50 -25
0
25
50 7S 100
-
.,
-0.05
-50 -25
1.0
~
-
..
il;
o.s
,.
'"e:
~
/
-o.s
~
III
~
~
TA=2SOC
NOlOAD
lii'
~
"\
10
103
i
f~Mrp~
a
104
Q=57\
0
25
50
7S
100
-S
-10
-IS
-20
-25
lOS
FREQUENCY (Hz)
rrIr-
II
-20
~
-30
Ii:
-40
-50
~~~rpi
Negative Power
Supply Rejection
~
z
'"
I
~ 50:1
i=-'
[
103
CLOCK FREQUENCY (Hz)
lii'
II
100:1
Q=S7
TA=+2SOC
Vs=iSV
RL=so kll
20
r-..
1
I
\.
102
z
VS=i5V!.
10 'eL~2S0kHz
Q=15,8
TA= 250C
-10
~
it
"\.
20
10
~
Q=4
TA=+2SJ
Vs=iSV
RL=SOkll
20
iii
"\.
30
o
-1.0
-50 -25
100
Positive Power
Supply Rejection
[
"\.
40
"\.
~ -o.s
a
CLOCK FREQUENCY (Hz)
[
50
~=15.8
"" ,
25
20
15
10
-
Vs~
"\.
"\.
~
-D.2
-0.4
-il.6
i7
"\
Q::!3~
0 0=4
Q vs Clock Frequency50:1 and 100:1
-
is
60
~
;:'"
VS=i5V.L
r-RL=50 kll
CL=50pFr-
Q=4
Op Amp-Open Loop
Frequency Response
~
D.2
'CLJ(=125kHz
Q vs Clock Frequency50:1 and 100:1
SUPPLY VOLTAGE (V)
lii'
7S
a
!C
0.4
~
TEMPERATURE (Oc)
-1.0
100
90
80
70
50
~
z
i""
D.8
D.6
0=IS.8
V
U
25
g
10
.A
L. / '
1-'
a
~
Q=57
- -
!C
0
50:1 and 100:1
1.0
15
'CLK= 125kHz
i-TA=25OC
I- RL=SO kll
CL=SO pF
g
Q vs Temperature-
TEMPERATURE (OC)
TEMPERATURE (OC)
Q vs Supply Voltage50:1 and 100:1
L
i7
i6
SUPPLY VOLTAGE (V)
/
Q=S7
Q=4
,/
,/
fCLK/fo Ratio vs
Temperature-50:1 Mode
g
L
,/
~
CLOCK FREQUENCY (Hz)
fCLK/fo Ratio vs
Temperature-100:1 Mode
0Jl3
III
103
CLOCK FREOUENCY (Hz)
g
[~j2
Vs=iSV
TA=2SOC
NO LOAD
97
III
104
'w= 125 kHz
TA=2SOC
-RL=50kll
-c,.=50pF
0=15.8lm
:m
-
fCLK/fo Ratio vs Supply
Voltage-50:1 and
100:1 Mode
fCLK/fo Ratio vs Clock
Frequency-100:1 Mode
106 107
FREQUENCY (Hz)
!
Vs=t5V.'.
10 'eLK= 250 kHz
0=15,8
TA=250 C
-10
-20
~
-30
Ii:
-40
it
,.
V
V
-50
-60
102
FREQUENCY (Hz)
TL/H/8694-24
1-63
~
:E
Typical Performance Characteristics (Continued)
Positive Swing vs
Load Resistance
!
JJ.llll
VS=i5V
TA=25OC
100
IIII
~
OP-AUP
on
~
..
-200
\
IIII
IIII
104
SUPPLY VOLTAGE (V)
Negative Swing vs Temperature
(Filter and Op Amp)
VS=i5V
D.3 Rl =5kll
,/
~
r.
,/ ,/
02
,/
0.1
Positive Swing vs Temperature
(Filter and Op Amp)
~
'OP-AWP
V
V
/
V
-so
i7
'"
~
/
0
~
z
25
50
75
100
-0.05
(!I
-0.10
!
I'\.
'\
I'\..
~
V
-1
-10
25
0
50
75
100
~
o
/
::Ii
~
z
/
-so -25
!
~
14
12
~
10
!.;(
~
8
\
~
z
e
o
100
~
t:;
~
i7
!:l'"0:
~
100:1
2D
-10
-20
-30
/. , /
V
~50:1
10
A
./
-40
U
V
i5
i7
is
SUPPLY VOLTAGE (V)
Filter Offset Voltage vs
Temperature-50:1 and 100:1
TA=25"C
Vs=i5V
NO lOAD
5.0 f-0=4
VS=i5V
!CLK= 250 kHz
NO LOAD
V,N=OV
-0=4
10.0
7~
~
0.0
-~
I-""
-5.0
~ -7~
t:; -10.0
-6
~ -1~
~
0:
75
12.5
-4
o
50
50
!.;(
i5
25
TA=25OCI
so !CLK= 250 kHz
40 NO LOAD
3D -0=4
Filter Offset Voltage vs Clock
Frequency-50:1 and 100:1
-2
102
0
Q
SUPPLY VOLTAGE (V)
Filter Offset Voltage vs
0-50:1 and 100:1
o
V
U
TEWPERATURE (OC)
10-1
!.;(
t:;
/
/
"- I'\.
-2
-4
-6
-8
"
/
Filter Offset Voltage
vs Supply Voltage
...
TA=25OC
!elK= 250 kHz
NO LOAD
f--V,N=OV
V
/
Supply Current vs
Supply Voltage
Vs=i5V
!CLK= 250 kHz
NO LOADVIN=OV -
V
TEWPERATURE (OC)
i!;
'\
/'
2
TEWPERATURE (OC)
Supply Current vs
Temperature
..
0.D5
::Ii
~
-25
VS=i5V
Rl = 5 kll
0.10
!.;(
/
SUPPLY VDLTAG!: (V)
-25
..........
i5
105
i5
-so
,
........
LOAD RESISTANCE (Il)
-0.3
2
OP-AWP
,......
~
FILTER/.
~
~
FILl!R
-6
IIIIII
105
TA=25OC
Rl =5kll
"
~
-5
TA=~517
Positive Swing vs
Supply Voltage
10
TA=25OC
Rl =5kll
Op..AWP
Vs=i5V
LOAD RESISTANCE (Il)
~
~
-4
FILTER
V
-3
i,(r\!~
!C( -100
II
Negative Swing vs
Supply Voltage
Negative Swing vs
Load Resistance
-1
103
104
-
-2
.,-
-3
105
CLOCK FREOUENCY (Hz)
....
-
-so -25
/
0
i/
/
V
25
50
75
100
TEWPERATURE (OC)
TL/H/8694-25
1-64
1.0 Application Information
(Continued)
AGND
50/100
TTL
ClK
RC
CMOS
3
18
ClK
TLlH/8694-3
FIGURE 1. Simplified Block Diagram of the MF8
TLlH/8694-4
FIGURE 2a. Separate Second-Order "Tracking" Filters
Your
4
AGND
10
7
m
ClK
TL1H/8694-5
FIGURE 2b. Fourth-Order Bandpass Made by Cascading Two Second-Order Stages
1-65
II
~r------------------------------------------------------------------------
:IE
1.0 Application Information
(Continued)
R2
r-~VV~------------------------------~Vom
TL/H/8694-6
FIGURE 2c. Multiple Feedback Loop Connection
1.2 CLOCKS
Clock signals derived from a crystal-controlled oscillator are
recommended when maximum center frequency accuracy
is desired, but in less critical applications the MF8 can generate its own clock signal as in Figures 3c and 4c. An external resistor and capacitor determine the oscillation frequency. Tolerance of these components and part-to-part variations in Schmitt-trigger logic thresholds limit the accuracy of
the RC clock frequency. In the self-clocked mode the TIL
Clock input should be connected to either pin 11 or pin 12.
The MF8 has two clock input pins, one for CMOS logic levels and the other for TIL levels. The TIL (pin 7) input automatically adjusts its switching threshold to enable operation
on either single or split power supplies. When this input is
used, the CMOS logic input should be connected to pin
11(V-). The CMOS Schmitt trigger input at pin 8 accepts
CMOS logic levels. When it is used, the TIL input should be
connected to either pin 11 (V-) or pin 12 (V+). The basic
clock hookups for single and split supply operation are
shown in Figures 3 and 4.
A
1.
18
1.
18
2
17
2
17
16
AGND
F2 IN
F20UT
-5V
5V.JlJL
-5V
15
MF8
14
13
mCLK
12
CMOS CLK
11
RC
10
F1 IN
A
FlOUT
F2 IN
A OUT
A IN
5V.JlJL
OV
+5V
V-
MF8
-5V
mCLK
CMOS ClK
-5V
RC
50/100
FlOUT
15
F2 OUT
V+
F1 IN
16
AGND
A OUT
14
A IN
13
V+
12
10
TLlH/8694-8
(b) MFa Driven with TTL Logic Level Clock
fCLK =
A
AGND
F2 IN
F2 OUT
v
C
-5V
50/100
TL/H/8694-7
(a) MFa Driven with CMOS Logic Level Clock
-5V
+5V
v-
II
TTl ClK
CMOS ClK
RC
2
17
3
16
4
15
5
MF8
14
13
6
Fl IN
F1 OUT
A OUT
A IN
V+
12
V11
50/100
10
7
8
9
'Vs = V+ - V-
+5V
-5V
TL/H/BS94-9
(c) MFa Driven with Schmitt Trigger Oscillator
FIGURE 3. Dual Supply Operation
1-66
1
RClnl (VS - VT _) rT+)1
Vs - VT+
VT_
Typically for VS' = 10V
1
fCLK = 1.69 RC
1.0 Application Information
(Continued)
pled to the filter input or biased to V+ /2. It is strongly recommended that each power supply pin be bypassed to
ground with at least a 0.1 f'F ceramic capacitor. In single
supply applications, with V- connected to ground, V+ and
AGND should be bypassed to system ground.
1.3 POWER SUPPLIES AND ANALOG GROUND
The MFa can be operated from single or dual-polarity power
supplies. For dual-supply operation, the analog ground (pin
4) should be connected to system ground. When single supplies are used, pin 4 should be biased to V+ /2 as in Figures
3 and 4. The input signal should either be capacitively cou-
lOY
10k
10k
J1J[
C
1
B
2
•
18
0
17
E
A
3
16
AGND
4
15
FllN
FlOUT
F2 IN
5
14
A OUT
F2 OUT
6
t.tF8
10':'Y~...r~~
~5YDC
13
A IN
12
Y+
11
Y-
10
50/100
+10Y
OY
TUHf8694-10
(a) MFa Driven with CMOS Logic Level Clock
lOY
C
1
B
2
18
•
A
3
16
AGND
4
15
F1 OUT
F2 IN
5
14
A OUT
t.tF8
F1 IN
13
A IN
12
V+
Ct.tOS ClK
11
Y-
RC
10
50/100
J1J[+5V
OY
0
17
+10Y
TUHf8694-11
(b) MFa Driven with TTL Logic Clock
10V
C
B
2
A
3
AGND
4
F2 IN
5
•
t.tF8
18
0
17
E
16
F1 IN
15
F1 OUT
14
A OUT
fClK
1
I =
RC'N (VS VT-) (VT+)
Vs VT+
VTTypically for Vs ~ 10V
1
fClK ~ 1.69 RC
F2 OUT
6
13
A IN
TTL ClK
7
12
Y+
Ct.tOS ClK
8
11
v-
10
50/100
RC
~
+10Y
TlfHf8694-12
(c) MFa Driven with the Schmitt Trigger Oscillator
FIGURE 4. Single supply operation. The AGND pin must be biased to mid-supply.
The input signal should be dc biased to mid-supply or capacitor-coupled to the input pin.
1-67
I
II
~
u.
:::E
,--------------------------------------------------------------------------,
1.0 Application Information (Continued)
1.4 MULTIPLE FEEDBACK LOOP CONFIGURATION
HOBP
The multi·loop approach to building bandpass filters is high·
Iy flexible and stable, yet uses few external components.
Figure 5 shows the MF8's internal operational amplifier and
two second-order filter stages with three external resistors
in a fourth-order multiple feedback configuration. Higher-order filters may be built by adding more second-order sections and feedback resistors as in Figure 6. The filter's response is determined by the clock frequency, the clock-tocenter-frequency ratio, the ratios of the feedback resistor
values, and the Os of the second-order filter sections. The
design procedure for multiple feedback filters can be broken
down into a few simple steps:
1) Determine the characteristics of the desired filter. This
will depend on the requirements of the particular application. For a given application, the required bandpass response can be shown graphically as in Figure 7, which
shows the limits for the filter response. Figure 7 also makes
use of several parameters that must be known in order to
design a filter. These parameters are defined below in terms
of Figure 7.
..l
T
AMAX
~
"I
..........
...:....:.
........
.: •••••• ··f4"-BW-.... .1 "
....:....
.....:...
.........
..........
.... ....
:.........
........
.:........
........ ~~
~~ ....... ....
.1 ,'_ ,'_ •• ' •
saw
14
.' ......... .,' " .' ...:...:....
T
,I ,'_
,
T
•
0'
,I
"
AMIN
AMIN
• 1
•
•
ICI
IOBP
IS2
fC2
FREQUENCY
TLlH/8694-15
FIGURE 7. Graphical representation of the amplitude
response specifications for a bandpass filter. The
filter's response should fall within the shaded area.
R2
VOUT
IDENTICAL SECOND ORDER STAGES
TL/H/8694-13
FIGURE 5. General fourth-order multiple-feedback bandpass filter circuit. MF8 pin numbers are shown.
RN
RN- 1
R3
R2
Ro
Rr
VIN
VOUT
TL/H/8694-14
FIGURE 6. By adding more second-order filter stages and feedback resistors,
higher order multiple-feedback filters may be built.
1-68
1.0 Application Information
(Continued)
Table I shows the available Q values; the nearest value is
8.5, which is programmed by tying pins 1, 2, 3, and 18 to V +
and pin 17 to V-.
fCl and fC2: The filter's lower and upper cutoff frequencies.
These define the filter's passband.
fSl and fS2: The boundaries of the filter's stopband.
BW: The filter's bandwidth. BW = fC2 -
Note that the resistor values obtained from the tables are
normalized for center frequency gain Hasp = 1. For different gains, simply divide Ro by the desired gain.
fc1.
SBW: The width of the filter's stopband. SBW = fS2 - fSl.
fo: The center frequency of the filter. fo is equal to the geometric mean of fCl and fC2: fo = ~fClfC2' fo is also equal to
the geometric mean of fSl and fS2.
5) Choose the clock-to-center-frequency ratio. This will
nominally be 100:1 when pin 10 is connected to pin 12(V+)
and 50:1 when pin 10 is connected to pin 11(V-). 100:1
generally gives a response curve nearer the ideal and fewer
(if any) problems with aliasing, while 50:1 allows operation
over the highest octave of center frequencies (10kHz to 20
kHz). Supply the MF8 with a clock signal of the appropriate
frequency to either the TTL or CMOS input, depending on
the available clock logic levels.
Hosp: The nominal passband gain of the bandpass filter.
This is normally taken to be the gain at fo.
fo/BW: The ratio of the center frequency to the bandwidth.
For second-order filters, this quantity is also known as "Q".
SBW/BW: The ratio of stopband width to bandwidth. This
quantity is also called "Omega" and may be represented by
the symbol "0.".
TABLE I. Q and Clock-to-Center-Frequency Ratio
Versus Logic Levels on "Q-set" Pins
Amax: The maximum allowable gain variation within the filter
passband. This will depend on the system requirements, but
typically ranges from a fraction of a dB to 3 dB.
100:1 mode
50:1 mode
Amin: The minimum allowable attenuation in the stopband.
Again, the required value will depend on system constraints.
ABCDE
2). Choose a Butterworth or Chebyshev response characteristic. Butterworth bandpass filters are monotonic on either side of the center frequency, while Chebyshev filters
will have "ripple" in the passband, but generally faster attenuation outside the passband. Chebyshev filters are specified according to the amount of ripple (in dB) within the
passband.
10000
11000
01000
10100
00100
01100
11100
01010
10010
10110
00010
11110
00110
11001
11010
11101
01001
10011
10101
01110
10001
10111
11011
11111
00101
01011
00111
00001
01101
00011
01111
3) Determine the filter order necessary to meet the response requirements defined above. This may be done with
the aid of the nomographs in Figures 8 and 9 for Butterworth and Chebyshev filters. To use the nomographs, draw
a line through the desired values on the AMAXI AMIN scales
to the left side of the graph. Draw a horizontal line to the
right of this pOint and mark its intersection with the vertical
line corresponding to the required ratio SBW/BW. The required filter order will be equal to the number of the curve
falling on or just above the intersection of the two lines. This
is illustrated in Figure 10 for a Chebyshev filter with 1 dB
ripple, 30 dB minimum attenuation in the stopband, and
SBW/BW = 3. From the Figure, the required filter order is
6.
4) The design tables in section 2.0 can now be used to find
the component values that will yield the desired response
for filters of order 4 through 12. The "Kn" give the ratios of
resistors "Rn" to RF, and KQ is Q divided by fo/BW.
As an example of the Tables' use, consider a fourth-order
Chebyshev filter with 0.5 dB ripple and fo/BW = 6. Begin by
choosing a convenient value for RF, such as 100 kn. From
the "0.5 dB Chebyshev" filter table, Ko = Ro/RF = 1.3405.
This gives Ro = RF X 1.345 = 134.05k. In a Similar manner, R2 is found to equal 201.61 k. Q is found using the
column labeled KQ. This gives Q = KQ x fo/BW = 8.4174.
1-69
FCLK/Fo
Q
FCLK/Fo
Q
43.7
45.8
46.8
48.4
48.7
48.9
49.2
49.3
49.4
49.4
49.5
49.6
49.6
49.6
49.7
49.7
49.7
49.7
49.7
49.7
49.8
49.8
49.8
49.8
49.8
49.8
49.8
49.9
49.9
49.9
49.9
0.45
0.71
0.96
2.0
2.5
3.0
4.0
5.0
5.7
6.4
7.6
8.5
10.6
11.7
12.5
13.6
14.7
15.8
16.5
17
19
22
27
30
33
40
44
57
68
79
90
94.0
95.8
96.8
98.4
98.7
98.9
99.2
99.3
99.4
99.4
99.5
99.6
99.6
99.6
99.7
99.7
99.7
99.7
99.7
99.7
99.8
99.8
99.8
99.8
99.8
99.8
99.8
99.9
99.9
99.9
99.9
0.47
0.73
0.98
2.0
2.5
3.0
4.0
5.0
5.7
6.4
7.6
8.5
10.6
11.7
12.5
13.6
14.7
15.8
16.5
17
19
22
27
30
33
40
44
57
68
79
90
II
Ie
:E
1.0 Application Information (Continued)
Higher-order filters are designed in a similar manner. An
eighth-order Chebyshev with 0.1 dB ripple, center frequency
equal to 1 kHz, and 100 Hz bandwidth, for example, could
be built as in Figure 11 with the following component values:
Ao = 79.86k
AF = 100k
A2 = 57.82k
A3 = 188.08k
A4 = 203.42k
Pins 1, 3, 17 and 18 high, pin 2 low. For 100:1 clock-to-center-frequency ratio, pin 10 is tied to V+ and the clock frequency is 100 kHz. For 50:1 clock-to-center-frequency ratio,
pin 10 is tied to V- and the clock frequency is 50 kHz.
in numerical order: Filter 1 (pins 16 and 15) should always
precede Filter 2 (pins 5 and 6). If a second MF8 is used,
Filter 2 of the first MF8 should precede Filter 1 of the second MF8, and so on.
Dynamic Considerations
Some filter response characteristics will result in high gain
at certain internal nodes, particularly at the op amp output.
This can cause clipping in intermediate stages even when
no clipping is evident at the filter output. The consequences
are significant distortion and degradation of the overall
transfer function. The likelihood of clipping at the op amp
output becomes greater as RF/Ro increases. As the design
tables show, AF/Ro increases with increasing filter order
and increasing ripple. It is good practice to keep out-of-band
input Signal levels small enough that the first stage can't
overload.
When building filters of order 4 or higher, best performance
will always be realized when the filter blocks are cascaded
1-70
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BW
TL/H/8694-16
FIGURE 8. Butterworth Bandpass Filter Design Nomograph
1-71
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TLlH/B694-17
FIGURE 9. Chebyshev Bandpass Filter Design Nomograph
1·72
2
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3
4
5
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TLlH/8694-18
FIGURE 10. Example of Chebyshev Bandpass Nomograph Use.
SBW
Amax = 1 dB, Amin = 30 dB, and BW = 3, resulting in n = 6.
1-73
If
:E
1.0 Application Information (Continued)
R4
r-~R3~~~--------------------------------------------------~~~~
-SV
-5V
CLOCK IN
J1.JI.....fL
TL/H/8894-19
FIGURE 11. Eighth-Order multiple-feedback bandpass filter using two MFSs. The circuit shown
accepts a TTL-level clock signal and has a clock-to-center-frequency ratio of 100:1.
1.5 TRACKING AND CASCADED SECOND-ORDER
BANDPASS FILTERS
The individual second-order bandpass stages may be used
as "stand-alone" filters without adding external feedback
resistors. The clock frequency and Q logic voltages set the
center frequency and bandwidth of both second-order
bandpass filters, so the two filters will have equivalent responses. Thus, they may be used as separate "tracking"
filters for two different signal sources as in Figure 2a, or
cascaded as in Figure 2b. For individual or cascaded second-order bandpass filters, the -3 dB bandwidth and the
amplitude response are given by the following two equations:
~42(1/N) -
BW(-3) =
2
(1)
(2)
7
8
9 10
Q
= the Q of each second order bandpass stage
fo
wo
= the center frequency of the filter in Hertz
= 2 '/Tfo = the center frequency of the filter in radians
per second
n
= the number of cascaded second-order stages =
N
2
H(s) ,= the overall filter transfer function
20
H(s) for a second order bandpass filter is plotted in Figure
12. Curves are shown for several different values of Q. Center frequency is normalized to 1 Hz and center-frequency
gain is normalized to 0 dB.
To find the necessary order n for cascaded second-order
bandpass filters using the nomograph in Figure 13, first determine the -3 dB bandwidth BW(-3), stopband width
SBW, and minimum stopband attenuation Amin. Draw a vertical line up from SBW/BW(-3), and a horizontal line
across from Amin. The required order is shown on the curve
just above the pOint of intersection of the two lines. Remember that each second-order filter section will have a center
frequency gain of 2, so the overall gain of a cascaded filter
will be 2N.
10
Q_l
-10
-20 . /
-
-40
6
FIGURE 13. Design Nomograph for Cascaded
Identical Second-Order Bandpass Filters
where
BW( - 3) = the - 3 dB bandwidth of the overall filter
-30
5
SBW
YW
s2+6 s + w02
~
4
TL/H/8694-21
1
H(s) = [2 X --=--6
s _]N
lz
3
"
-"
-"
.... .....
"I.
=5
~{!'o
[7 ~Q-2'
0.1
0.5
.......
, ............ ......
I
" ' .....
1
r....
5
10
FREQUENCY (Hz)
TUH/8694-20
FIGURE 12. H(s) For second-order bandpass filters with
various values of Q. Ho normalized In each case to 0 dB.
Cascading filters in this way may provide acceptable performance when minimum external parts count is very impor-
1-74
1.0 Application Information
(Continued)
tant, but much greater flexibility and better performance will
be obtained by using the feedback techniques described in
was fs/2 - 10 Hz. This phenomenon is known as "aliasing". Aliasing can be reduced or eliminated by limiting the
input signal spectrum to less than f s /2. This may in some
cases require the use of a bandwidth-limiting filter (a simple
passive RC network will generally suffice) ahead of the MFa
to attenuate unwanted high-frequency signals. However,
since the clock frequency is much greater than the center
frequency, this will usually not be necessary.
1.4.
1.6 INPUT IMPEDANCE
The input to each filter block is a switched-capacitor circuit
as shown in Figure 14. During the first half of a clock cycle,
the input capacitor charges to the input voltage Vin, and
during the second half-cycle, its charge is transferred to a
feedback capacitor. The input impedance approximates a
resistor of value
Output Steps
Another characteristic of sampled-data circuits is that the
output voltage changes only once every clock cycle, resulting in a discontinuous output Signal (Figure 15). The "steps"
are smaller when the clock-to-center-frequency ratio is
100:1 than when the ratio is 50:1.
1
Rin " ' - - - .
CinfClK
Cin depends on the value of Q selected by the Q logic pins,
and varies from about 1 pF to about 5 pF. For a worst-case
calculation of Rin, assume Cin = 5 pF. Thus,
Clock Frequency Limitations
The performance characteristics of a switched-capacitor filter depend on the switching (clock) frequency. At very low
clock frequencies (below 10Hz), the internal capacitors begin to discharge slightly between clock cycles. This is due to
very small parasitic leakage currents. At very low clock frequencies, the time between clock cycles is relatively long,
allowing the capacitors to discharge enough to affect the
filters' output offset voltage and gain. This effect becomes
stronger at elevated operating temperatures.
R. (min) '"
1
In
- 5 X 1O-12fClK
At higher clock frequencies, performance deviations are primarily due to the reduced time available for the internal integrating op amps to settle. For this reason, the clock waveform's duty cycle should be as close as possible to 50%,
especially at higher frequencies. Filter Q shows more variation from the nominal values at higher frequencies, as indicated in the typical performance curves. This is the reason
for the different maximum limits on Q accuracy at fClK =
250 kHz and fClK = 100 kHz in the table of performance
specifications.
TLlH/B694-22
FIGURE 14. Simplified MF& Input Stage
At the maximum clock frequency of 1 MHz, this gives
Rin '" 200k. Note that Rin increases as fClK decreases, so
the input impedance should never be less than this number.
Source impedance should be low enough that the gain isn't
significantly affected.
Center Frequency Accuracy
Ideally, the ratio fClK/fo should be precisely 100 or 50, depending on the logic voltage on pin 10. However, as Table I
shows, this ratio will change slightly depending on the Q
selected. As the table shows, the largest errors occur at the
lowest values of Q.
1.7 OUTPUT DRIVE
The filter outputs can typically drive a 5 kll load resistor to
over ±4V peak-to·peak. Load resistors smaller than 5 kll
should not be used. The operational amplifier can drive the
minimum recommended load resistance of 5 kll to at least
±3.5V.
1.& SAMPLED-DATA SYSTEM CONSIDERATIONS
100:1
Aliasing
The MFa is a sampled-data filter, and as such, differs in
many ways from conventional continuous-time filters. An important characteristic of sampled-data systems is their effect on signals at frequencies greater than one-half the
sampling frequency. (The MFa's sampling frequency is the
same as its clock frequency). If a Signal with a frequency
greater than one-half the sampling frequency is applied to
the input of a sampled-data system, it will be "reflected" to
a frequency less than one·half the sampling frequency.
Thus, an input signal whose frequency is fs/2 + 10 Hz will
cause the system to respond as though the input frequency
50:1
TL/H/B694-23
FIGURE 15. Output Waveform of
MF& Showing Sampling Steps
1-75
II
2.0 Design Tables for Multiple Feedback Loop Bandpass Filters
BUTTERWORTH RIPPLE3dB
Order
Ko
K2
4
6
8
10
'12
2.0000
2.3704
2.9142
3.6340
4.5635
4.0000
2.6667
2.0000
1.6000
1.3333
Ka
K4
9.1429
5.8284
4.4112
3.5800
K5
14.3145
6.9094
4.3198
27.2014
11.5043
K6
KQ
49.0673
1.4142
1.5000
1.5307
1.5451
1.5529
CHEBYSHEV RIPPLE 0.01 dB
Order
Ko
K2
4
6
8
'10
1.9041
1.8277
1.4856
1.0171
3.6339
1.8450
0.9919
0.5740
Order
Ko
K2
4
6
8
'10
1.8644
1.7024
1.2893
0.8163
3.4922
1.6787
0.8707
0.4934
Ka
K4
6.6170
3.1209
1.7484
5.0414
1.2943
K5
K6
KQ
0.4489
0.9438
1.4257
1.8908
4.8814
CHEBYSHEV RIPPLE 0.02 dB
Ka
K4
6.0772
2.7661
1.5155
4.0779
0.9879
Ks
K6
KQ
0.5393
1.0849
1.6106
2.1179
3.7119
CHEBYSHEV RIPPLE 0.03 dB
Order
Ko
K2
4
6
8
*10
1.8341
1.6183
1.1688
0.7034
3.3871
1.5713
0.7977
0.4467
K3
K4
5.7231
2.5491
1.3786
3.5270
0.8252
K5
K6
KQ
0.6016
1.1808
1.7362
2.2724
3.0938
CHEBYSHEV RIPPLE 0.04 dB
Order
Ko
K2
4
6
8
'10
1.8085
1.5535
1.0814
0.6264
3.3009
1.4908
0.7454
0.4139
K3
K4
5.4548
2.3919
1.2818
3.1471
0.7181
Ks
K6
KQ
0.6508
1.2560
1.8348
2.3940
2.6883
CHEBYSHEV RIPPLE 0.05 dB
Order
Ko
K2
K3
4
6
8
'10
1.7860
1.5002
1.0129
0.5686
3.2268
1.4260
0.7046
0.3888
5.2373
2.2685
1.2072
K4
2.8609
0.6402
Ks
K6
KQ
0.6923
1.3191
1.9175
2.4961
2.3938
CHEBYSHEV RIPPLE 0.06 dB
Order
Ko
K2
4
6
8
'10
1.7657
1.4548
0.9566
0.5230
3.1612
1.3717
0.6713
0.3685
Ka
K4
5.0536
2.1670
1.1467
2.6336
0.5800
1-76
Ks
2.1666
K6
KQ
0.7285
1.3741
1.9897
2.5852
3:
."
co
2.0 Design Tables for Multiple Feedback Loop Bandpass Filters (Continued)
CHEBYSHEV RIPPLE .07 dB
Order
Ko
K2
4
6
8
*10
1.7471
1.4150
0.9089
0.4856
3.1020
1.3249
0.6431
0.3516
K3
K4
4.8943
2.0808
1.0959
2.4466
0.5316
K5
Ks
KQ
0.7609
1.4232
2.0543
2.6649
1.9842
CHEBYSHEV RIPPLE .08 dB
Order
Ko
K2
4
6
8
1.7298
1.3795
0.8675
3.0478
1.2837
0.6187
K3
K4
4.7534
2.0060
Ks
Ks
KQ
0.7905
1.4679
2.1130
2.2887
CHEBYSHEV RIPPLE .09 dB
Order
Ko
K2
K3
K4
4
6
8
1.7136
1.3475
0.8311
2.9978
1.2469
0.5973
4.6271
1.9400
Ks
Ks
KQ
0.8177
1.5090
2.1671
2.1529
CHEBYSHEV RIPPLE 0.1 dB
Order
Ko
K2
4
6
8
1.6983
1.3183
0.7986
2.9512
1.2137
0.5782
K3
K4
4.5125
1.8809
Ks
Ks
KQ
0.8430
1.5473
2.2176
2.0343
CHEBYSHEV RIPPLE 0.2 dB
Order
Ko
K2
4
6
8
1.5757
1.1128
0.5891
2.5998
0.9894
0.4551
K3
K4
3.7271
1.4954
Ks
K6
KQ
1.0378
1.8413
2.6057
1.3309
CHEBYSHEV RIPPLE 0.3 dB
Order
Ko
K2
4
6
'8
1.4833
0.9835
0.4732
2.3575
0.8560
0.3861
K4
K3
3.2501
1.2760
Ks
Ks
KQ
1.1804
2.0568
2.8914
0.9885
CHEBYSHEV RIPPLE 0.4 dB
Order
Ko
K2
4
6
'8
1.4067
0.8888
0.3956
2.1698
0.7618
0.3391
K3
K4
2.9088
1.1250
Ks
K6
KQ
1.2988
2.2363
3.1299
0.7792
CHEBYSHEV RIPPLE 0.5 dB
Order
Ko
K2
4
6
'8
1.3405
0.8143
0.3389
2.0161
0.6897
0.3040
K3
K4
2.6447
1.0114
1-77
0.6365
Ks
K6
KQ
1.4029
2.3944
3.3406
II
2.0 Design Tables for Multiple Feedback Loop Bandpass Filters (Continued)
CHEBYSHEV
Order
Ko
K2
4
6
'8
1.2816
0.7530
0.2952
1.8857
0.6316
0.2762
Order
Ko
K2
4
6
'8
1.2283
0.7012
0.2601
1.7727
0.5834
0.2535
Order
Ko
K2
4
6
'8
1.1797
0.6564
0.2314
1.6731
0.5424
0.2344
Order
Ko
K2
4
6
'8
1.1347
0.6171
0.2073
1.5841
0.5068
0.2181
Order
Ko
K2
4
6
'8
1.0930
0.5822
0.1869
1.5039
0.4756
0.2038
RIPPLE 0.6 dB
K3
K4
2.4305
0.9212
0.5326
CHEBYSHEV
RIPPLE 0.7 dB
K3
K4
2.2515
0.8471
0.4535
CHEBYSHEV
RIPPLE 0.8 dB
K3
K4
2.0983
0.7846
0.3913
CHEBYSHEV
RIPPLE 0.9 dB
K3
K4
1.9650
0.7309
0.3413
CHEBYSHEV
RIPPLE 1.0 dB
K3
K4
1.8475
0.6840
0.3002
CHEBYSHEV
RIPPLE 1.1 dB
Order
Ko
K2
K3
4
6
'8
1.0539
0.5509
0.1693
1.4310
0.4479
0.1913
1.7428
0.6426
0.2660
CHEBYSHEV
RIPPLE 1.2 dB
Order
Ko
K2
4
6
'8
1.0173
0.5226
0.1540
1.3643
0.4231
0.1801
Order
Ko
K2
4
6
'8
0.9828
0.4969
0.1406
1.3029
Q.4006
0.1701
K4
K4
K3
1.6487
0.6056
0.2372
CHEBYSHEV
RIPPLE 1.3 dB
K3
K4
1.5634
0.5724
1-78
0.2125
Ks
Ks
KQ
1.4975
2.5385
3.5329
Ks
Ks
KQ
1.5852
2.6724
3.7119
Ks
Ks
KQ
1.6678
2.7989
3.8811
Ks
Ks
KQ
1.7464
2.9194
4.0426
Ks
Ks
KQ
1.8219
3.0354
4.1981
Ks
Ks
KQ
1.8949
3.1476
4.3487
Ks
Ks
KQ
1.9657
3.2567
4.4952
Ks
Ks
KQ
2.0348
3.3633
4.6385
2.0 Design Tables for Multiple Feedback Loop Bandpass Filters (Continued)
CHEBYSHEV
Order
Ko
K2
4
6
0.9501
0.4733
1.2461
0.3803
RIPPLE 1.4 dB
Ko
K2
4
6
0.9192
0.4515
1.1934
0.3616
Ko
K2
4
6
0.8897
0.4315
1.1443
0.3445
Ko
K2
4
6
0.8617
0.4128
1.0983
0.3287
Order
Ko
K2
4
6
0.8350
0.3955
1.0553
0.3141
Ko
K2
4
6
0.8095
0.3793
1.0148
0.3005
Ko
K2
4
6
0.7850
0.3641
0.9767
0.2878
Ko
K2
4
6
0.7616
0.3498
0.9407
0.2759
Order
Ko
K2
4
6
0.7391
0.3364
0.9067
0.2648
K4
Ks
Ks
KQ
2.2341
3.6717
RIPPLE 1.7 dB
K4
Ks
Ks
KQ
2.2986
3.7717
RIPPLE 1.8 dB
Ks
K4
Ks
Ks
KQ
2.3624
3.8706
1.2321
RIPPLE 1.9 dB
K4
Ka
Ks
Ks
Ka
2.4255
3.9687
1.1797
RIPPLE 2.0 dB
Ka
K4
Ks
Ks
Ka
2.4881
4.0660
1.1308
RIPPLE 2.1 dB
Ka
K4
Ks
Ks
Ka
2.5503
4.1628
1.0850
CHEBYSHEV
KQ
RIPPLE 1.6 dB
1.2883
CHEBYSHEV
Order
Ks
2.1688
3.5705
Ka
CHEBYSHEV
Order
Ks
1.3490
CHEBYSHEV
Order
K4
Ka
CHEBYSHEV
KQ
RIPPLE 1.5 dB
1.4145
CHEBYSHEV
Order
Ks
2.1024
3.4678
Ka
CHEBYSHEV
Order
Ks
1.4857
CHEBYSHEV
Order
K4
Ka
RIPPLE 2.2 dB
Ka
1.0420
1·79
K4
Ks
Ks
Ka
2.6122
4.2591
II
2.0 Design Tables for Multiple Feedback Loop Bandpass Filters (Continued)
RIPPLE 2.3 dB
CHEBYSHEV
Order
Ko
K2
4
6
0.7176
0.3237
0.8744
0.2544
K3
K4
Ko
K2
4
6
0.6968
0.3118
0.8438
0.2446
Ko
K2
4
6
0.6769
0.3005
0.8148
0.2353
RIPPLE 2.4 dB
K4
K3
Ko
K2
4
6
0.6577
0.2897
0.7871
0.2265
Ko
K2
4
6
0.6392
0.2796
0.7607
0.2182
Ko
K2
4
6
0.6213
0.2699
0.7356
0.2104
K3
K4
Ko
K2
4
6
0.6041
0.2607
0.7116
0.2029
Ko
K2
4
6
0.5875
0.2519
0.6886
0.1959
K6
0.9275
KQ
RIPPLE 2.6 dB
K3
K4
Ks
K6
KQ
2.8573
4.6415
0.8935
RIPPLE 2.7 dB
K3
K4
Ks
K6
KQ
2.9183
4.7368
0.8612
RIPPLE 2.8 dB
K3
K4
Ks
K6
KQ
2.9792
4.8322
0.8306
RIPPLE 2.9 dB
K3
K4
Ks
K6
KQ
3.0402
4.9276
0.8016
CHEBYSHEV
Order
Ks
2.7962
4.5462
CHEBYSHEV
Order
KQ
RIPPLE 2.5 dB
CHEBYSHEV
Order
Ks
2.7350
4.4507
CHEBYSHEV
Order
Ks
0.9635
CHEBYSHEV
Order
KQ
2.6737
4.3550
CHEBYSHEV
Order
K6
1.0016
CHEBYSHEV
Order
Ks
RIPPLE 3.0 dB
K3
0.7739
K4
Ks
K6
KQ
3.1013
5.0231
Note: Multiple feedback loop filters of higher order than those specified in the tables will oscillate due to phase shift at the output of the summing amplmer. This
phase shift is not the fault of the MFa; it is inherent in this type of multiple feedback loop topology. In addition, all filters marked w~h an asterisk (.) will be unstable
for Q ,;; I, due to phase shifts caused by the MFa's switched-capacitor design approach.
1-80
3:
...
."
~ Semiconductor
NatiOnal
Q
Corporation
MF10 Universal Monolithic Dual Switched Capacitor Filter
General Description
Features
The MF10 consists of 2 independent and extremely easy to
use, general purpose CMOS active filter building blocks.
Each block, together with an external clock and 3 to 4 resistors, can produce various 2nd order functions. Each building
block has 3 output pins. One of the outputs can be configured to perform either an allpass, highpass or a notch function; the remaining 2 output pins perform lowpass and bandpass functions. The center frequency of the lowpass and
bandpass 2nd order functions can be either directly dependent on the clock frequency, or they can depend on both
clock frequency and external resistor ratios. The center frequency of the notch and all pass functions is directly dependent on the clock frequency, while the highpass center frequency depends on both resistor ratio and clock. Up to 4th
order functions can be performed by cascading the two 2nd
order building blocks of the MF10; higher than 4th order
functions can be obtained by cascading MF10 packages.
Any of the classical filter configurations (such as Butterworth, Bessel, Cauer and Chebyshev) can be formed.
• Easy to use
• Clock to center frequency ratio accuracy ±0.6%
• Filter cutoff frequency stability directly dependent on
external clock quality
• Low sensitivity to external component variation
• Separate highpass (or notch or allpass), bandpass, lowpass outputs
• fo x Q range up to 200 kHz
• Operation up to 30 kHz
• 20-pin 0.3" wide Dual-In-Line package
• 20-pin Surface Mount (SO) wide-body package
System Block Diagram
INVA
II
AGNO
CLKA
50/100/CL
LSh
CLKa
TO AGNO
INVa
20
Vii
VA N/AP/HPa Sla
LPa
TL/H/5645-1
Order Number MF10AJ or MF10CCJ
See NS Package Number J20A
Order Number MF10CCWM
See NS Package Number M20B
1-81
Order Number MF10ACN or
MF10CCN
See NS Package Number N20A
o
.....
u..
Soldering Information
N Package: 10 sec.
J Package: 10 sec.
SO Package: Vapor Phase (SO sec.)
Infrared (lS sec.)
Absolute Maximum Ratings (Note 1)
:::&
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Officel
Distributors for availability and specifications.
Supply Voltage (V+ - V-I
14V
Voltage at Any Pin
V+ + 0.3V
V- - 0.3V
Input Current at any pin (Note 2)
SmA
Package Input Current (Note 2)
20mA
Power Dissipation (Note 3)
SOOmW
Storage Temperature
lS0·C
ESD Susceptability (Note 11)
2000V
2S0·C
300·C
21S·C
220·C
See AN-4S0 "Surface Mounting Methods and Their Eff!lct
on Product Reliability" (appendix D) for other methods of
soldering surface mount devices.
Operating Ratings (Note 1)
Temperature Range
MF10ACN, MF10CCN
MF10CCWM
MF10CCJ
MF10AJ
TMIN';: TA';: TMAX
O·C,;: TA';: 700C
O·C,;: TA';: 700C
-40·C ,;: TA ,;: 8S·C
-SS·C ,;: TA';: 12S·C
Electrical Characteristics v+
= +S.OOVandV- = -S.OOV unless otherwise specified.
Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 2S·C.
MF10ACN, MF10CCN,
MF10CCWM
Symbol
Parameter
Is
Maximum Supply Current
fa
Center Frequency Range
Tested Design
Tested Design Units
Typical
Typical
Limit
limit
Limit
Limit
(Note 8)
(Note 8)
(Note 9) (Note 10)
(Note 9) (Note 10)
Conditions
V+ -Y- Supply Voltage
MIN
8
8
V
MAX
14
14
V
Clock Applied to Pins 10 & 11
No Input Signal
~
fa X Q
< 200kHz
MAX
fCLK
fCLK/fo
fCLK/fo
Clock Frequency Range
mA
0.1
0.2
0.1
0.2
Hz
30
20
30
20
kHz
10
5.0
10
Hz
1.5
1.0
MHz
Q = 10
Mode 1
Q Error (MAX)
(Note 4)
Q = 10
Mode 1
DC Offset Voltage
(Note 5)
12
1.0
Clock Feedthrough
Yos2
8
5.0
~
DC Offset Yoltage (Note 5)
12
1.5
100: 1 Clock to Center FreQ = 10
quency Ratio Deviation
MF10C Model
DC Lowpass Gain
12
MAX
50:1 Clock to Center Fre- IMF10A Q = 10
quency Ratio Deviation
MF10C Model
HOlP
8
MIN
t--
VOS1
MF10CCJ, MF10AJ
Ypin12 = 5V
fCLK = 250 kHz
±0.2
±O.S
±0.6
±0.2
±1.0
%
±0.2
±1.S
±1.5
±0.2
±1.5
%
Ypin12 = OV
fClK = SOO kHz
±0.2
±0.6
±0.6
±0.2
±1.0
%
±0.2
±1.5
±1.5
±0.2
±1.5
%
10
mV
Ypin12 = 5Y
fClK = 250 kHz
±2
±6
±6
±2
±6
%
Ypin12 = OY
fClK=500 kHz
±2
±6
±6
±2
±6
%
Model Rl = R2 = 10k
MIN Ypin12= +5V SAIS = Y+
MAX (fClK/fo = 50)
t--
~ Ypin12=+5V
10
SAIS = Y-
0
±0.2
±0.2
0
±0.2
dB
±5.0
±15
±15
±5.0
±15
mV
-150
-185
-185
-150
-185
-85
-85
-70
mY
-85
-70
mV
MAX (fClK/fo = 50)
Vos3
VOS2
Yos3
DC Offset Yoltage
(Note 5)
DC Offset Yoltage
(Note 5)
DC Offset Yoltage
(Note 5)
~ Ypin12= +5Y
All Modes
-70
MAX (fClK/fo = 50)
-100
-100
-20
-20
-70
-100
mY
-20
SAIS = Y+
Ypin12 = OY
(fClK/fo = 100)
-300
-300
mV
SAIS = YYpln12=OY
(fClK/fo = 100)
-140
-140
mV
All Modes
Vpin12=OY
(fClK/fo = 100)
-140
-140
mV
1-82
:s::
""......
Electrical Characteristics (Continued)V+
= +S.OOVandV- = -S.OOV unless otherwise specified.
Boldface limits apply for T MIN to T MAX; all other limits T A = T J = 2SoC.
MF10ACN, MF10CCN,
MF10CCJ, MF10AJ
MF10CCWM
Symbol
Parameter
Conditions
Typical
(Note 8)
V out
Minimum Output
IBP, LPPINS
Voltage Swing
I N/ AP /HP PIN
GBW
Op Amp Gain BW Product
SR
Op Amp Slew Rate
Limit
(Note 9) (Note 10)
Typical
(Note 8)
Tested
Design
Limit
Limit
(Note 9) (Note 10)
±3.8
±4.2S
±3.8
V
RL = 3.Sk
±4.2S
±3.8
±3.8
±4.2S
±3.6
V
Vpin12 = +SV
(fClK/fo = SO)
(fClK/fo = 100)
2.S
2.S
MHz
7
7
V/p.s
83
83
dB
80
80
dB
I Source
20
20
rnA
ISink
3.0
3.0
mA
Logic Input Characteristics Boldface limits apply for TMIN to TMAX; all other limits TA =
MF10ACN, MF10CCN,
MF10CCWM
Parameter
Conditions
Typical
(Note 8)
CMOS Clock
Input Voltage
TTL Clock
Input Voltage
Units
±3.8
(Note 6)
Circuit Current (Note 7)
Design
Limit
±4.2S
Dynamic Range
Maximum Output Short
Tested
RL = Sk
Vpin12 = OV
Ise
CI
Tested
Design
Limit
Limit
(Note 9)
(Note 10)
TJ = 2SoC.
MF10CCJ, MF10AJ
Typical
(Note 8)
Tested
Design
Limit
Limit
(Note 9)
(Note 10)
Units
MIN Logical "1"
V+ = +SV, V- = -SV,
+3.0
+3.0
+3.0
V
MAX Logical "0"
VlSh = OV
-3.0
-3.0
-3.0
V
MIN Logical "1"
V+ = +10V, V- = OV,
+8.0
+8.0
+8.0
V
MAX Logical "0"
VlSh = +SV
+2.0
+2.0
+2.0
V
MIN Logical "1"
V+ = +SV,V- = -SV,
+2.0
+2.0
+2.0
V
MAX Logical "0"
VlSh = OV
+0.8
+0.8
+0.8
V
MIN Logical "1 "
V+ = +10V, V- = OV,
+2.0
+2.0
+2.0
V
MAX Logical "0"
VlSh = OV
+0.8
+0.8
+0.8
V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V- or VIN > V+) the absolute value of current at that pin should be limited
to 5 rnA or less. The 20 rnA package input current limits the number of pins that can exceed the power supply boundaries with a 5 rnA current limit to four.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, 8JA, and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is Po ~ (TJMAX - T,.)18JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJMAX ~ 125'C, and the typical iunction·la-ambient thennal resistance of the MF10ACN/CCN when board mounted is 55"C/W. For the MFI OAJ/CCJ, this
number increases to 95'C/W and for the MF10CCWM this number is 66"C/W.
Note 4: The accuracy of the 0 value is a function of the center frequency (fal. This is illustrated in the curves under the heading "Typical Peformance Characteristics".
Note 5: Vos1, Vos2. and Vos3 refer to the internal offsets as discussed in the Applications Information section 3.4.
Note 6: For ±5V supplies the dynamic range is referenced to 2.B2V rms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 p.V nns for
the MF10 with a 50:1 ClK ratio and 2BO p.V rms for the MF10 with a 100:1 ClK ratio.
Note 7: The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to
the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting
that output to the positive supply. These are the worst case conditions.
Note 8: Typicals are at 25'C and represent most likely parametric nonn.
Note 9: Tested limits are guaranteed to National's AOOl (Average OutgOing Quality level).
Note 10: Design limits are guaranteed but not 100% tested. These
lim~s
are not used to calculate outgoing quality levels.
Note 11: Human body model, 100 pF discharged through a 1.5 kfl resistor.
1-83
D
r---------------------------------------------------------------------------------,
....
LI.
C)
:::E
Typical Performance Characteristics
Power Supply Current vs.
Power Supply Voltage
14.0
'.C'
oS
ia
~
g;
ill
~
TA=25'C
13.0 I-- MODE I
l--'o=5KHz
12.0
I
/
11.0
10.0
8.0
5.4
5.2
~ ~~
~
10.0
+(7 5•5 VOLT
~ ::~
11.0
12.0
13.0
14.0
-
....
11111
10K
IK
~
!5
~
!
-3,9
I I
I I
-4.0
-4.1
-4.2
-4.3
-4.4
-4.5
-4.6
-4.7
-
VJ5V
~NO+CH~
(RL=3.5K Ohm)
,
,,
,,
"?
..
E
~
15.0~ Ohi)
25
~
4.30
~
04.20
B5
2.0
MODE 1
0.20
1.5
fOlK
fo-!.QiL-
0.0
-1.0
'CLK:~
!il::;
..
u
\
-IS
r-- .....
V
~
J .1
~
0.15
0.10
.....
0.00
-70
100
moO
..... ~
125
Vs=t.~V
5.0
TA=25OC
4.5
~g~~~L 9=10.0
4.0
I.
3.5
3.0
2.5
2.0
1.5
1.0
D.5
0.0
VS=t.S~
hi
~ :~ :=!~~=50:1
fCLK?~~_
'
~100:1
0. _ _ _
=
f
0.00
~:
8.0
8.0
I
4.0
2.0
0.0
1'0
-2.0
100 21Xl31Xl41Xl500 1iOO 71Xl BIXl91XlIIXlO
t±::
NOMINlt2t=
MODE I
0D3
0D2
0.01
,,-0.03
-D.04
1\
-o.D5
-o.os
-oD7
-o.os
-0.09
..... .,
lOO21Xl31Xl41Xl500 1iOO 71Xl BIXl91XlIIXlO
o.os
0.05
fClklfo Deviation vs.
Temperature
I
VS=t.SV
NOMINAl Q=IO.O
I
'ClK=2fOKHZ
0D4 MODE I
0D3
0,02
0.01
0.00
-0.01
-0,02
f~~_50:1
I
I
I'..
V
.....
V
/
-0.03
-ss
II
f~:_:OO:\
CLOCK fREQUENCY (KHz)
fClk/fo Deviation vs.
Temperature
0D4
I
CLOCK fREQUENCY (KHz)
,- V
B5
25
0.05
I.
..... ....
6.0
s.s
-1.0
-IS
1000
Q Deviation vs.
Clock Frequency
TEMPERATURE (OC)
o.os
500
-o.s
-55
22.0
100:1
CLOCK fREQUENCY (KHz)
-0.15
125
/
r---
125
~~-50:1 c-
0.05
5dil-
/
B5
1M
VS =t5V
TA= 250C
MODE I
NOMINAL Q= 10.0
NOMIN~
MODE I
fOlK=250KHz _
f
1
i\
\
lOOK
Crosstalk vs. Clock
Frequency
-0.10
Q Deviation vs.
Clock Frequency
"
10K
LOAD RESISTANCE(Ohms)
V~~
TEMPERATURE (OC)
r-VS=t.5V
1M
r-TA=25OC
•L
1M f-NOMINAL Q=IO.O
14.0 f-MODE 1
25
-IS
-0.05
/
B5
25
+/-6.5 VOLT SUPPUES
IK
NOTCl!:-t(RL=3.6KOhm)
0.25
NOMIN~_~
-ss
+ -6.0 VOLT SUPPLIES
-5.5
-6.0
Q Deviation vs.
Temperature
0.30
-o.s
-5.0
TEMPERATURE (OC)
VS~
"'- ..... ~ ......
+ -5.0 VOLT SUPPLIES
+/-5.5 VOLT SUPPUES
~
,~
-55
125
2.5
1.0
-4.5
1M
,~
Q Deviation vs.
Temperature
0.5
1111
+ -4.5 VOLT SUPPLIES
Vs~t ~v- I-
TEMPERATURE(OC)
3.0
~
i
4AO BJDPlssiND ILOJPASf,\-;
I- (RL=5.0K Ohm)
,
4.10
-IS
-4.0
0
11111
lOOK
0
t;;;:
, ~ f=rANJp",:S AND LO~~
-ss
!5
Positive Output Swing
Temperature
Ib'
1 RL
1111
-3.0
4.50 VS.
A'
I
TArI5~
-2.5
LOAD RESISTANCE(Ohms)
Negative Output Swing
vs. Temperature
-3.8
E
s~~r~
+/-4.5 VOLT SUPPUES
POWER SUPPLY VOLTAGE(V)
-3.7
~
.1J.1l
-2.0
!5 -3.5
!:: e. +/-5.0 VOLT sM~(\~s
3.B
3.6
9.0
8.0
E
~ 5.6 ~ ~~~IYOL~ k~m:~s
••
...
Negative Output Voltage Swing
vs. Load Resistance
(N/AP/HP Output)
-1.5
TA=25OC
r- +(76.5 VOLT SUPPLIES
E ~:~
I
V
/
7.0
6.4
6.2
J
/
9.0
Positive Output Voltage Swing
vs. Load Resistance
(N/AP/HP Output)
-0,04
-15
25
TEMPERATURE(OC)
B5
125
-55
-IS
25
B5
125
TEMPERATURE(OC)
TL/H/5645-14
1-84
s:
....
o
."
Typical Performance Characteristics (Continued)
fCLK/fo Deviation vs.
Clock Frequency
....
....
.,.
VS" t5V--=+=+:
0J5
D.3O
TA=Z5~+-h
NODE 1
~IS
~ ~•
......
lA
Ysjf.5~
,.
TA=2SOC
12
NOM1N'J±Q=10~.
-<>.1.
...,.
....,
I
..,•
-oz;
0.0
-,=50:1
D.2
-<>'15
V± - ±5V
r7
NDWINAL 0=10.0
WODE t
feu< '
:...
~
f~~1-
Deviation of fCLK vs.
NominalQ
fo
fCLK/fo Deviation vs.
Clock Frequency
,.
TA 25"C
VPINI2 +5V
~
fi
1i:
II
-1.0
i
T
~I.E -2.0
ICD2003QO«Jl5006Xl7Ol1lO9IXIICXXJ
1(XJ200300400SOOEOO700aXJ9001DX1
a.OCl( FREQUENCY (IOU)
CLOCK F'REQUENCY (KHz)
TL/H/5645-15
-3.0
0.1
1.0
10
100
NOMINAL Q
TL1H/5645-16
Deviation of f~LK vs.
NomlnalQ
0
0.5
§:
i§
0.0
iii
ill
i
~ls-O.5
_1.o81.E
0.1
1.0
10
NOMINAL Q
100
TLlH/5645-17
Connection Diagram
INV(4,17)
Surface Mount and
Dual-In-Llne Package
lPA
SPA
N/ AP/HPA
INVA
1
20
19
2
81(5,16)
1NVS
SIA
sA/S
VA+
VD+
lSh
ClKA
lPS
BPs
N/ AP/HP S
Sis
AGND
VA-
9
10
12
VD50/100/Cl
11
ClKs
TL/H/5645-18
Top View
Pin Descriptions
LP(1,20), BP(2,19), The second order lowpass, bandN/AP/HP(3,18)
pass and notch/allpass/highpass
outputs. These outputs can typically
sink 1.5 mA and source 3 mAo Each
output typically swings to within 1 V
of each supply.
1-85
The inverting input of the summing
op-amp of each filter. These are high
impedance inputs, but the non·inverting input is internally tied to
AGND, making INVA and INVs behave like summing junctions (low impedance, current inputs).
81 is a signal input pin used in the
all pass filter configurations (see
modes 4 and 5). The pin should be
driven with a source impedance of
less than 1 kG. If 81 is not driven
with a signal it should be tied to
AGND (mid-supply).
This pin activates a switch that connects one of the inputs of each fifter's second summer to either AGND
(8A1s tied to V-) or to the lowpass
(LP) output (8A1s tied to V+). This
offers the flexibility needed for configuring the filter in its various modes
of operation.
II
C) r-------------------------------------------------------------------------------------,
....
U.
:'iii
Pin Descriptions (Continued)
VA + (7), Vo + (8) . Analog positive supply and digital
positive supply. These pins are internally connected through the IC substrate and therefore VA + and Vo +
should be derived from the same
power supply source. They have
been brought out separately so they
can be bypassed by separate capacitors, if desired. They can be externally tied together and bypassed by a
single capacitor.
Analog and digital negative supplies.
The same commentS as for VA - and
Vo- apply here.
LSh(9)
Level shift pin; it accommodates various clock levels with dual or single
supply operation. With dual ± 5V
supplies, the MF10 can be driven
with CMOS clock levels (± 5V) and
the LSh pin should be tied to the system ground. If the same supplies as
above are used but only TTL clock
levels, derived from OV to + 5V supply, are available, the LSh pin should
be tied to the system ground. For single supply operation (OV and + 10V)
the VA -, Vo - pins should be connected to the system ground, the
AGND pin should be biased at + 5V
and the LSh pin should also be tied
to the system ground for TTL clock
levels. LSh should be biased at + 5V
for CMOS clock levels in 10V singlesupply applications.
CLKA(10),
Clock inputs for each switched caCLKB(11)
paCitor filter building block. They
should both be of the same level
(TTL or CMOS). The level shift (LSh)
pin description discusses how to accommodate their levels. The duty cycle of the clock should be close to
50% especially when clock frequencies above 200 kHz are used. This
allows the maximum time for the internal op-amps to settle, which yields
optimum filter operation.
50/100/CL(12)
By tying this pin high a 50:1 clock-tofilter-center-frequency ratio is obtained. Tying this pin at mid-supplies
(i.e., analog ground with dual supplies) allows the filter to operate at a
100:1 clock-to-center-frequency ratio. When the pin is tied low (i.e., negative supply with dual supplies), a
simple current limiting circuit is triggered to limit the overall supply current down to about 2.5 mAo The filtering action is then aborted.
AGND(15)
This is the analog ground pin. This
pin should be connected to the system ground for dual supply operation
or biased to mid-supply for single
supply operation. For a further discussion of mid-supply biasing techniques see the Applications Information (Section 3.2). For optimum filter
performance a "clean" ground must
be provided.
1.0 Definitions of Terms
feLK: the frequency of the external clock Signal applied to
pin 10 or 11.
fo: center frequency of the second order function complex
pole pair. fo is measured at the bandpass outputs of the
MF10, and is the frequency of maximum bandpass gain.
(Figure 1).
fnotch: the frequency of minimum (ideally zero) gain at the
notch outputs.
fz: the center frequency of the second order complex zero
pair, if any. If fz is different from fo and if Oz is high, it can be
observed as the frequency of a notch at the allpass output.
(Figure 1OJ.
Q: "quality factor" of the 2nd order filter. 0 is measured at
the bandpass outputs of the MF10 and is equal to fo divided
by the -3 dB bandwidth of the 2nd order bandpass filter
(Figure 1). The value of 0 determines the shape of the 2nd
order filter responses as shown in Figure 6.
Qz: the quality factor of the second order complex zero pair,
If any. Oz is related to the allpass characteristic, which is
written:
HAP(S) =
HOAP ( s2 - s;o
z
S2
+ 6>02 )
+ S6>o + 6>02
o
where Oz = 0 for an all-pass response.
HOBP: the gain (in VIV) of the bandpass output at f = f o.
HOLP: the gain (in VIV) of the lowpass output as f 0 Hz
(Figure 2).
HOHP: the gain (in VIV) of the highpass output as f fclk/2 (Figure 3).
HON: the gain (in VIV) of the notch output as f 0 Hz
and as f fclK/2, when the notch filter has equal gain
above and below the center frequency (Figure 4). When the
low-frequency gain differs from the high-frequency gain, as
in modes 2 and 3a (Figures 11 and 8), the two quantities
below are used in place of HON.
HON1: the gain (in VIV) of the notch output as f 0 Hz.
HON2: the gain (in VIV) of the notch output as f -
1-86
fClk/2.
!!:
."
.-
1.0 Definitions of Terms (Continued)
>"
Ho..
6
o
iE90~
e.
io.mH~~
HBP(S) =
45
0
..
HOBPS
--='-'-S2 + SIIIO + 11102
Q
~ -45
-90
'l
fL', fH
fo
'H
I (LOG SCALE)
I (LOG SCALE)
TL/H/5645-20
TL/H/5645-19
(b)
(a)
H"~
-O~
H01.'
0.101HD"
; -90
-190
I, Ie
I (LOG SCALE)
Iu
I (LOG SCALE)
TUH/5645-21
TUH/5645-22
(a)
(b)
HOp = HOlP X
!.~1 _ 1
o
402
FIGURE 2. 2nd-Order Low-Pass Response
i
>"
H"brc
iE
HOHP
i-90o
0.707 HDH'
IE
-190
La::
II
Iu
I,
Ip
f (LOB SCALE)
I (LOB SCALE)
TL/H/5645-24
TLlH/5645-23
(b)
(a)
1p = 10 x
[~1 - 2~2]-1
1
HOp = HOHP X !.~1 _
o
1
402
FIGURE 3. 2nd..()rder Hlgh·Pass Response
1·87
....o
La.
:!
r-----------------------------------------------~----------------------------,
1.0 Definitions of Terms
(Continued)
;;
~
HON
i" 0.707 HON
I---~-#-----
~
45
:ll
0
HON(S2
Q
iE -451----'1\,.
iii
+ (00 2 )
S2 + SOOo + 000 2
=
HN(S)
90
fo
fL 10 IH
I (LOG SCALE)
Il 10 IH
I (LOG SCALE)
TL/H/5645-25
fL = fo
(;~ + ~(~)2 + 1 )
fH = fo
C~ + ~(2~)2 + 1 )
TL/H/5645-26
(a)
I7"r
Q = -f---,;fo = ~fLfH
H- L
-90 '--_ _.1.-:'-'-_ _.....
(b)
FIGURE 4. 2nd-Order Notch Response
>"
HAP I----~-_
~
~
1-
~
180
-360
~
I (LOG SCALE)
t::::==:::t===:
~
I (LOG SCALE)
TL/H/5645-27
TUH/5645-28
(b)
FIGURE 5. 2nd-Order All-Pass Response
(a)
(a) Bandpass
(b) Low Pass
20
20
10
10
!r
!z
.
;;:
iii
-20
-30
.....
-10
-20
Q-0.5
1
0.1
10
0.2
"'..:".......
(d) Notch
1---1--+-+-+-+--1
-60
Q=~.2
V
~
-40
10
Q-0.5
"
0.1
0.2
0.5
1.0
2
5
10
FREQUENCY (Hz)
(e) AII·Pass
Q-5
~
Ii" -120
i" -10
iii
I .
-30
!Go..
5.0
o
...
~
2.0
i0o'i:
I ./
-20
~
0.5 1.0
0.707
FREOUENCY (Hz)
FREOUENCY (Hz)
10
r-Q
I--
'-l..
~
;; -10
I
-40
0.5
. c=h • ,
"'
iii
,
"""
-30
0-10_
Q 2
Q-i
- -i
~=O.707-
r- 0 =0.2
C±:-Q=~"'"
10
L Jo-_~.
,...Q=1
Q=1
iii
;- -10
(c) Hlgh·Pass
20
-- I-- Q=10 ~Q=5t
~
I-+--+~
~
-180
r..... 0-0.2
.......
iE -240
-20 I--+-+---'w--~
\{-1
-300
-360
0.1
0.2
0.5
1.0
2
10
0.1
FREQUENCY (Hz)
0.2
0.5
1
"""""
2
5
10
FREQUENCY (Hz)
TLlH/5645-29
FIGURE 6. Response of various 2nd-order filters as a function of Q. Gains
and center frequencies are normalized to unity.
1-88
s:::
."
......
2.0 Modes of Operation
The MF10 is a switched capacitor (sampled data) filler. To
fully describe its transfer functions, a time domain approach
is appropriate. Since this is cumbersome, and since the
MF10 closely approximates continuous fillers, the following
discussion is based on the well known frequency domain.
Each MF10 can produce a full 2nd order function. See Table 1 for a summary of the characteristics of the various
modes.
MODE 1: Notch 1, Bandpass, Lowpass Outputs:
a
CI
= JL= R3
BW
R2
= quality factor of the complex pole pair
BW
= the - 3 dB bandwidth olthe bandpass
output.
Circuit dynamics:
HOlP =
fnotch = fo (See Figure 7)
= center frequency of the complex pole pair
Hosp
-a
or Hosp = HOlP X a
=HONxa.
HOlP(peak) '" a x HOlP (for high a's)
MODE 1a: Non-Inverting BP, LP (See Figure 8)
= fClK or fClK
100
50
fClK
fnotch
= center frequency of the imaginary zero pair = fo.
HOlP
= Lowpass gain (as f -+ 0) = _ R2
R1
HOSp
= Bandpass gain (at f = fo) = -
HON
= Notch output gain as f -+ 0
} = - R2
f-+ fClK/2
Rl
=
Q
:~
fClK
100 or "50
R3
R2
= -1; HOlP(peak) '" a x HOlP (for high a's)
R3
R2
HOSP2 = 1 (non-inverting)
Circuit dynamics: HOSPl = Q
Note: VIN should be driven from a low impedance « 1 kn) source.
II
FIGURE 7. MODE 1
TLlH/5645-4
FIGURE 8. MODE 1a
1-89
0
....
u..
::::&
2.0 Modes of Operation (Continued)
MODE 2: Notch 2, Bandpass, Lowpass: fnotch
(See Figure 9)
fa
<
MODE 3: Highpass, Bandpass, Lowpass Outputs
(See Figure 1{fJ
fo
= center frequency
=
fa
fClK~ fClK~
100
R4 + 10r Go
R4 + 1
fClK
a
fClK
= 100 arGo
a
= quality factor of the complex pole pair
= Lowpass output gain (as f
-+ 0)
R2/R1
+1
HOBP
= Bandpass output gain (at f = fa) = - R3/R1
HONI
= Notch output gain (as f
JR2 X R3
V'R4
R2
HOBP
= Bandpass gain (at f = fa) = -
HOlP
= Lowpass gain (as f
-+ 0)
:~
= _ R4
R1
· . d ynamlcs:
. -R
R2 =--;
HOHP HOBP =.JHOHP X HOlP X a
CIrcUit
4 HOlP
HOlP(peak) "" a X HOlP (for high a's)
-+ 0)
R2/R1
R2/R4 + 1
HON2
V'R4
HOHP = Highpassgain (au -+ fClK) = _ R2
2
R1
4R2/R4 + 1
R2/R3
R2/R4
V'R4
=
fnotch
HOlP
= fClK X (R2 or fClK X (R2
100
50
= quality factor of the complex pole pair
HOHP(peak) "" a X HOHP (for high a's)
= Notch output gain (asf
fC~K)
-+
= -R2/R1
Filter dynamics: HOBP = a 4 HOlP HON2 = 4 HONI HON2
R4
Rl
V,M
SA,.
9
6
v+
TL/H/5645-36
FIGURE 9. MODE 2
c,·
r ~~
-,
R4
HP.
51.
BPo
LP.
Rl
'In Mode 3, the feedback loop is closed
around the input summing amplifier, the
finite GBW product of this op amp causes a slight Q enchancemenl If this is a
problem, connect a small capacitor
(10 pF-l00 pF) across R4 to provide
some phase lead.
V,M
SAl.
9
6
v-
TL/H/5645-5
FIGURE 10, MODE 3
1-90
==
....
."
2.0 Modes of Operation (Continued)
Q
MODE 3a: HP, BP, LP and Notch with External Op Amp
MODE 4: Allpass, Bandpass, Lowpass Outputs
(See Figure 11)
= fClK X
100
o
=
(See Figure 12)
fR2 or fClK x (R2
V"R4 50 V"R4
(R2 x
V"R4
= fClK or fClK.
100
R3
R2
o
R1
R3
HOSp
R4
= notch Irequency = IClK
100
VA;
II o(:~ HOlP -
Hn1
= gain 01 notch (as I
Hn2
. 01 notch ( as f
= gain
Rg
--x
Rh
= quality lactor of compIex zero pair. = R3
R1
. (
HOAP' = Allpass gain at 0
fRh or IClK fRh
50
vA;
-+ 0)
-+ 0)
= Lowpass gain (as I
Hosp
= Bandpass gain (at I = fo)
=-
:~ HOHP) II
fClK)
< I <"'2
= - R2
R1 = - 1
HOlP
= gain 01 notch at
=
R3
For AP output make R1 = R2
R1
1= 10 =
10
= BW = R2;
Oz
R1
HOlP
50 •
I z' = center Irequency 01 the complex zero :::: fo
R2
HOHP
HON
= center frequency
(:~ + 1) = -
R
= -l! X HOlP
= _
RI
R3 (1
R2
+ R2)
=
R1
2
-2 (R3)
R2
Circuit dynamics: Hosp = (HOlP)
IClK)
-+ 2'"
x 0
= (HOAP
+
1)0
'Due to the sampled data nature of the filter, a slight mismatch of fz and fo
occurs causing a 0.4 dB peaking around fa of the allpass filter amplitude
response (which theoretically should be a straight line). If this is unacceptable, Mode 5 is recommended.
HOHP
84
II
HI
NOTCH
OUT
FIGURE 11_ MODE 3a
TUH/5645-6
FIGURE 12_ MODE 4
1-91
....o r---------------------------------------------------------------------------------,
U.
:IE
2.0 Modes of Operation (Continued)
MODE 5: Numerator Complex Zeros, BP, LP
(See Figure 13)
fa
=
~1
fz
=
~1
Q
=
41
Qz
=41
MODE 6a: Single Pole, HP, LP Filter (See Figure 14)
= cutoff frequency of LP or HP output
+ R2 X fClKor~1 + R2 X fClK
R4
100
R4
50
R2 fClK R2 fClK
= RS 100 or RSW
- R1 X fClKor~1 _ R1 X fClK
R4
100
R4
50
RS
+ R2/R4 X R2
RS
R1
R2
HOHP
R1
MODE 6b: Single Pole LP Filter (Inverting and Non-Inverting) (See FIgure 15)
= cutoff frequency of LP outputs
HOlP
RS
R1/R4 X R1
= gain at C.Z. output (as f --+ 0 Hz)
-R2(R4 - R1)
R1(R2 + R4)
= gain at C.Z. output ( as f --+
HOSp
= _ (R2 + 1) X RS
R1
R2
HOlP
=_(R2+R1)xR4
R2 + R4
R1
fC~K)
'" R2 fClK or R2 fClK
RS 100
R3 50
=
~2
= 1 (non-inverting)
RS
R2
R4
FIGURE 13. MODE 5
FIGURE 14. MODE 6a
TL/H/5645-7
FIGURE 15. MODE 6b
1-92
2.0 Modes of Operation
s:
"T1
.....
(Continued)
C
TABLE I. Summary of Modes. Realizable filter types (e.g. low-pass) denoted by asterisks.
Unless otherwise noted, gains of various filler outputs are inverting and adjustable by resistor ratios.
Mode
BP
LP
*
*
1
HP
N
AP
Number of
resistors
Adjustable
3
No
2
No
*
(2)
1a
HOBP1
HOBP2
= -0
= +1
+
HOlP
1
May need input buffer. Poor dynamics
for high O.
Yes (above
,
2
*
3
*
*
*
3a
*
*
*
4
*
*
5
*
*
*
.
6a
Notes
felK/fo
3
fClK/50 or
fClK/100)
4
Yes
Universal StateVariable Filter. Best
general-purpose mode.
7
Yes
As above, but also
includes resistortuneable notch.
*
3
No
Gives Allpass response with HOAP = -1
and HOlP = - 2.
*
4
Gives flatter all pass
response than above
if R1 = R2 = 0.02R4.
3
Single pole .
2
Single pole.
*
,
(2)
6b
HOlP1
HOlP2
= +1
=
-R3
R2
3.0 Applications Information
The MF10 is a general-purpose dual second-order state
variable filter whose center frequency is proportional to the
frequency of the square wave applied to the clock input
(fClK)' By connecting pin 12 to the appropriate DC voltage,
the filter center frequency fa can be made equal to either
fClK/100 or fClK/50. fa can be very accurately set (within
± 6%) by using a crystal clock oscillator, or can be easily
varied over a wide frequency range by adjusting the clock
frequency. If desired, the fClK/fo ratio can be altered by
external resistors as in Figures 9, 10, 11, 13, 14 and 15. The
filter 0 and gain are determined by external resistors.
As an example, let's assume that a system requires a
fourth-order Chebyshev low-pass filter with 1 dB ripple, unity
gain at dc, and 1000 Hz cutoff frequency. As the system
order is four, it is realizable using both second-order sections of an MF10. Many filter design texts (and National's
Switched Capacitor Filter Handbook) include tables that list
the characteristics (fa and 0) of each of the second-order
filter sections needed to synthesize a given higher-order filter. For the Chebyshev filter defined above, such a table
yields the following characteristics:
All of the five second-order filter types can be built using
either section of the MF1 O. These are illustrated in Figures 1
through 5 along with their transfer functions and some related equations. Figure 6 shows the effect of 0 on the shapes
of these curves. When filter orders greater than two are
desired, two or more MF10 sections can be cascaded.
fOB
faA
= 529 Hz
= 993 Hz
OA
OB
= 0.785
= 3.559
For unity gain at dc, we also specify:
HOA
= 1
HOB = 1
The desired clock-to-cutoff-frequency ratio for the overall
filter of this example is 100 and a 100 kHz clock signal is
available. Note that the required center frequencies for the
two second-order sections will not be obtainable with clockto-center-frequency ratios of 50 or 100. It will be necessary
3.1 DESIGN EXAMPLE
In order to design a second-order filter section using the
MF1 0, we must define the necessary values of three parameters: fa, the filter section's center frequency; Ho, the passband gain; and the filter's O. These are determined by the
characteristics required of the filter being designed.
to adjust fClK externally. From Table I, we see that Mode 3
fa
can be used to produce a low-pass filter with resistor-adjustable center frequency.
1-93
II
....o
u.
::iii
3.0 Applications Information
(Continued)
In most filter designs involving multiple second-order
stages, it is best to place the stages with lower Q values
ahead of stages with higher Q, especially when the higher Q
is greater than 0.707. This is due to the higher relative gain
at the center frequency of a higher-Q stage. Placing a stage
with lower Q ahead of a higher-Q stage will provide some
attenuation at the center frequency and thus help avoid clipping of signals near this frequency. For this example, stage
A has the lower Q (0.785) so it will be placed ahead of the
other stage.
For the first section, we begin the design by choosing a
convenient value for the input resistance: R1A = 20k. The
absolute value of the passband gain HOLPA is made equal
to 1 by choosing R4A such that: R4A = - HOLPAR1 A = R1 A
= 20k. If the 50/1 OO/CL pin is connected to mid-supply for
nominal 100:1 clock-to-center-frequency ratio, we find R2A
by:
R2A
=
R4A
fOA2
(fCLK/100)2
=2X
(529)2
104 X - - - = 5.6kand
(1000)2
R3A = QA ~R2AR4A = 0.785~5.6 X 103 X 2 X 104 = 8.3k
The resistors for the second section are found in a similar
fashion:
R1B = 20k
R4B = R1B = 20k
R2B
=
fOB2
R4B(fCLK/100)2
(993)2
= 20k(1OoOj2 =
19.7k
R3B = QB~R2BR4B =3.559b.97 X 104 X 2 X 104 = 70.6k
The complete circuit is shown in Figure 16 for split ± 5V
power supplies. Supply bypass capacitors are highly recommended.
RIB
VOUT
20k
LP,
F ......R'I
3'.....
70.6k
NI AP/HPA NI AP/HP,
V,N
INVA
20k
INVB
SI A
-5V
51,
t.lFl0
AGND
SAl'
VA-
VA'
'5V
10
-5V
VD-
VD'
0.1
14
L Sh.
50/100/CL
ClKA
elKs
0.1
11
.J1J1.
CLOCK IN
f cLle = 100 kHz
TL/H/5645-30
FIGURE 16. Fourth-order Chebyshev low-pass filter from example in 3.1.
± 5V power supply. 0-5V TTL or - 5V ± 5V CMOS logic levels.
RIB
VOUT
20k
LP,
BP,
N/ AP/HP,
INVB
Mr10
SAl'
17
51,
AGND
0.1
VAVD-
50/100/CL
elK"
elKB
11
TL/H/564S-31
FIGURE 17. Fourth-order Chebyshev low-pass filter from example In 3.1. Single + 10V power supply. 0-5V TTL logic
levels. Input signals should be referred to half-supply or applied through a coupling capacitor.
1-94
3.0 Applications Information
V+
V+
hE
R
~
T
~
C
...ii:
"T1
(Continued)
Q
~10V
V+
V+
TYPI:AL VALUES:
2ksR,,100k
4.7 ~F:sCs470 ""
TL/H/5645-33
TL/H/5645-32
(a) Resistive Divider with
Decoupllng Capacitor
(b) Voltage Regulator
TLlH/5645-34
(c) Operational Amplifier
with Divider
FIGURE 18. Three Ways of Generating V2+ for Single-Supply Operation
gain (Figure 6). As an example, a lowpass filter with a Q of
10 will have a 20 dB peak in its amplitude response at f o. If
the nominal gain of the filter HOlP is equal to 1, the gain at
fo will be 10. The maximum input signal at fo must therefore
be less than aoo mVp. p when the circuit is operated on ±5
volt supplies.
Also note that one output can have a reasonable small voltage on it while another Is saturated. This is most likely for a
circuit such as the notch in Mode 1 (Figure 7). The notch
output will be very small at fo, so it might appear safe to
apply a large signal to the input. However, the bandpass will
have its maximum gain at fo and can clip if overdriven. If one
output clips, the performance at the other outputs will be
degraded, so avoid overdriving any filter section, even ones
whose outputs are not being directly used. Accompanying
Figures 7 through 15 are equations labeled "circuit dynamics", which relate the Q and the gains at the various outputs.
These should be consulted to determine peak circuit gains
and maximum allowable signals for a given application.
3.2 SINGLE SUPPLY OPERATION
The MF10 can also operate with a single·ended power supply. Figure 17 shows the example filter with a single-ended
power supply. VA + and Vo + are again connected to the
positive power supply (a to 14 volts), and VA - and Vo- are
connected to ground. The AGNO pin must be tied to V+ 12
for single supply operation. This half-supply pOint should be
very "clean", as any nOise appearing on it will be treated as
an input to the filter. It can be derived from the supply voltage with a pair of resistors and a bypass capacitor (Figure
18a), or a low-impedance half-supply voltage can be made
using a three-terminal voltage regulator or an operational
amplifier (Figures 18b and 18e). The passive resistor divider
with a bypass capacitor is sufficient for many applications,
provided that the time constant is long enough to reject any
power supply noise. It is also important that the half-supply
reference present a low impedance to the clock frequency,
so at very low clock frequencies the regulator or op-amp
approaches may be preferable because they will require
smaller capacitors to filter the clock frequency. The main
power supply voltage should be clean (preferably regulated)
and bypassed with 0.1 J.l.F.
3.4 OFFSET VOLTAGE
The MF10's switched capacitor integrators have a higher
equivalent input offset voltage than would be found in a
typical continuous-time active filter integrator. Figure 19
shows an equivalent circuit of the MF10 from which the output dc offsets can be calculated. Typical values for these
offsets with SAIB tied to V + are:
Vosl = opamp offset = ±5mV
-300 mV @ 100:1
Vos2 = -150 mV @ 50:1
-140mV@100:1
Vos3 = -70 mV@ 50:1
3.3 DYNAMIC CONSIDERATIONS
The maximum signal handling capability of the MF10, like
that of any active filter, is limited by the power supply voltages used. The amplifiers in the MF10 are able to swing to
within about 1 volt of the supplies, so the input signals must
be kept small enough that none of the outputs will exceed
these limits. If the MF1 0 is operating on ± 5 volts, for example, the outputs will clip at about avp•p• The maximum input
voltage multiplied by the filter gain should therefore be less
than avp•p.
Note that if the filter Q is high, the gain at the lowpass or
highpass outputs will be much greater than the nominal filter
When SAIB is tied to V-, Vos2 will approximately halve. The
dc offset at the BP output is equal to the input offset of the
lowpass integrator (Vos3). The offsets at the other outputs
depend on the mode of operation and the resistor ratios, as
described in the following expressions.
1-95
II
o.... .-----------------------------------------------------------------------,
LL.
:::::I!!
3.0 Applications Information (Continued)
Mode 1 and Mode 4
Mode 2 and Mode 5
(~+ 1 +IIHOlPII) _ V~S3
VOS(N)
= VOSI
VOS(BP)
= Vosa
VOS(lP)
= VOS(N) - VOS2
VOS(N)
R2)
= ( Rp + 1 VOSI X 1
1
Vosa
Rp = R111R311R4
+~) VOSI _ V~S3
VOS(BP)
= Vosa
VOS(lP)
= VOS(N) - VOS2
= VOS3
= Vos(N.lNV.BP) - VOS2
Mode 3
Vos(N.INV.BP) = (1
Vos(LP)
1
R2/R4
+ VOS2 1 + R4/R2 - ~1 + R2/R4
Mode 1a
VOS(INV.BP)
+
VOS(HP)
=VOS2
VOS(BP)
=Vosa
VOS(lP)
= VOSI [1
+
:;1 -
VOS2(::)
- Vosa(::)
Rp = R111R211R3
4(17)
TLlH/5645-12
FIGURE 19. MF10 Offset Voltage Sources
5V SUPPLY
H
1M
H4
H2
4(17)
HI
VIN
L-__
H3 ______ •••
~~
TL/H/5645-13
FIGURE 20. Method for Trimming Vos
1-96
iii:
"T1
.....
3.0 Applications Information
(Continued)
For most applications, the outputs are AC coupled and DC
offsets are not bothersome unless large signals are applied
to the filter input. However, larger offset voltages will cause
clipping to occur at lower ac signal levels, and clipping at
any of the outputs will cause gain nonlinearities and will
change fa and Q. When operating in Mode 3, offsets can
become excessively large if R2 and R4 are used to make
fClKlfo significantly higher than the nominal value, especially if Q is also high. An extreme example is a bandpass filter
having unity gain, a Q of 20, and fClK/fo = 250 with pin 12
tied to ground (100:1 nominal). R4/R2 will therefore be
equal to 6.25 and the offset voltage at the lowpass output
will be about + 1V. Where necessary, the offset voltage can
be adjusted by using the circuit of Figure 20. This allows
adjustment of Vos1, which will have varying effects on the
different outputs as described in the above equations. Some
outputs cannot be adjusted this way in some modes, however (VoS(BP) in modes 1a and 3, for example).
was fs/2 - 100 Hz. This phenomenon is known as "aliasing", and can be reduced or eliminated by limiting the input
signal spectrum to less than fs/2. This may in some cases
require the use of a bandwidth-limiting filter ahead of the
MF10 to limit the input spectrum. However, since the clock
frequency is much higher than the center frequency, this will
often not be necessary.
Another characteristic of sampled-data circuits is that the
output Signal changes amplitude once every sampling period, resulting in "steps" in the output voltage which occur at
the clock rate. (Figure 21) If necessary, these can be
"smoothed" with a simple R-C low-pass filter at the MF10
output.
o
The ratio of fClK to fe (normally either 50:1 or 100:1) will
also affect performance. A ratio of 100:1 will reduce any
aliasing problems and is usually recommended for wideband input signals. In noise sensitive applications, however,
a ratio of 50:1 may be better as it will result in 3 dB lower
output noise. The 50: 1 ratio also results in lower DC offset
voltages, as discussed in 3.4.
3.5 SAMPLED DATA SYSTEM CONSIDERATIONS
The MF10 is a sampled data filter, and as such, differs in
many ways from conventional continuous-time filters. An important characteristic of sampled-data systems is their effect on signals at frequencies greater than one-half the
sampling frequency. (The MF10's sampling frequency is the
same as its clock frequency.) If a signal with a frequency
greater than one-half the sampling frequency is applied to
the input of a sampled data system, it will be "reflected" to
a frequency less than one-half the sampling frequency.
Thus, an input signal whose frequency is fs/2 + 100 Hz will
cause the system to respond as though the input frequency
The accuracy of the fClK/fo ratio is dependent on the value
of Q. This is illustrated in the curves under the heading
"Typical Performance Characteristics". As Q is changed,
the true value of the ratio changes as well. Unless the Q is
low, the error in fClK/fo will be small. If the error is too large
for a specific application, use a mode that allows adjustment
of the ratio with external resistors.
It should also be noted that the product of Q and fa should
be limited to 300 kHz when fa < 5 kHz, and to 200 kHz for
fa> 5 kHz.
100:1
II
50:1
Tl/H/5645-35
FIGURE 21. The Sampled-Data Output Waveform
1-97
Section 2
Analog Switchesl
Multiplexers
PI
Section 2 Contents
Analog SWitches/Multiplexers Definition of Terms ......................................
Analog Switches/Multiplexers Selection Guide. . . . . . • . . . . . . • . . . . . . . . . . . • . • . . . . . . . . . . . . .
AH0014/ AH0014C DPDT, AH0015C Quad SPST, AH0019/ AH0019C Dual DPST-TTTL/
DTLD Compatible MOS Analog Switch . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . .
AH5009/ AH501 0/ AH5011/ AH5012 Monolithic Analog Current Switch ......... . . . . . . . . . . .
AH5020C Monolithic Analog Current Switch. . . . . . . . . • . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . .
CD4016C Quad Bi-Lateral Switch.... ... .. .... ......... ....... ....... ............. ....
CD4051 BM/CD4051 BC Single 8-Channel Analog Multiplexer/Demultiplexer. . . . . . . . . . . . . . .
CD4052BM/CD4052BC Dual8-Channel Analog Multiplexer/Demultiplexer......... .. . .. ..
CD4053BM/CD4053BC Triple 8-Channel Analog Multiplexer/Demultiplexer ...............
CD4066BM/CD4066BC Quad Bi-Lateral Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4529BC Dual4-Channel or 8-Channel Analog Data Election. . . . . . . . . . . . . . . . . . . . . . . . . . .
LF11331/LF13331/LF11332/LF1333/LF13333,LF11201/LF13201/LF11202/LF13202
Quad SPST JFET Analog Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LF13508 8-Channel Analog Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LF13509 4-Channel Analog Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
* MM54HC4016/MM74HC4016 Quad Analog Switch... . ..... ......... .. .. . ..... . .... ....
* MM54HC4051/MM74HC4051 8-Channel Analog Multiplexer. . . .. . . . . . . . . . . . . . . . . . . . . . . . .
* MM54HC4052/MM74HC4052 Dual4-Channel Analog Multiplexer........................
* MM54HC4053/MM74HC4053 Triple 2-Channel Analog Multiplexer..... ..... ... . .... .....
* MM54HC4066/MM74HC4066 Quad Analog Switch.....................................
* MM54HC4316/MM74HC4316 Quad Analog Switch with Level Translator.... . ... .. ... .. ...
"Devices Not Covered In Last Publication
2-2
2-3
2-4
2-5
2-6
2-17
2-25
2-32
2-32
2-32
2-40
2-46
2-52
2-63
2-63
2-77
2-84
2-84
2-84
2-91
2-96
l>
_
::J
II)
National
0"
Semiconductor
Corporation
CO
~
s:
Analog Switch
Definition of Terms
=r
I
C
!!.
S·
;:;:
O·
-...
::J
RON: Resistance between the output and the input of an
addressed channel.
Cs: Capacitance between any open terminal "S" and
ground.
10-15: Leakage current that flows from the closed switch
into the body. This leakage is the difference between the
current ID going into the switch and the current Is gOing out
of the switch.
tRAN: Delay time when switching from one address state to
another.
tON: Delay time between the 50% points of an enable input
and the switch ON condition.
Co: Capacitance between any open terminal "D" and
ground.
tOFF: Delay time between the 50% points of the enable
input and the switch OFF condition.
Is: Current at any switch input. This is leakage current when
the switch is ON.
10: Current at any switch input going into the switch. This is
leakage current when the switch is OFF.
2-3
o
~
3
en
~NaHonal
.
Semiconductor
CorporaHon
Analog Switch/Multiplexer Selection Guide
Part Number
Function
Logic Input
AH5011
AH5012
CD4016
CD4066
LF11201/LF13201
LF11202/LF13202
LF11331/LF13331
LF11332/LF13332
LF11333/LF13333
MM74HC4016
QUADSPST
TTL,CMOS
TTL,CMOS
CMOS
CMOS
TTL
TTL
TTL
TTL
TTL
CMOS
AH5020
DUALSPDT
TTL,CMOS
TRIPLESPDT
CMOS
CMOS
CD4053
MM74HC4053
AH5009
AH5010
4-CHANNEL
TTL,CMOS
TTL,CMOS
Vs
(Typ)
±7.5
±7.5
±15
±15
±15
±15
±15
±12
±7.5
±6.0
-
CD4052
CD45298
LF13509
MM74HC4052
4-CHANNEL
DIFFERENTIAL
CMOS
CMOS
TTL,CMOS
CMOS
±7.5
±7.5
±18
±6.0
CD4051
CD45298
LF13508
MM74HC4051
8-CHANNEL
CMOS
CMOS
TTL,CMOS
CMOS
±7.5
±7.5
±18
±6.0
2-4
TON/TOFF
ns(Typ)
RON
150/300
90/500
90/500
90/500
90/500
90/500
5/8
100
150
850
280
200
200
200
200
200
40
150/300
150
160/75
300
40
150/300
20/40
25/50
15/16
150/300
150/300
160/75
50
1600/200
15/16
160175
50
1600/200
15/16
n
100
150
300
350
350
40
300
350
350
40
:J>
::c
0
~National
0
......
~ Semiconductor
.j:o.
.......
:J>
::c
0
AH0014/AH0014C DPDTI AH0015/AH0015C Quad
SPSTI AH0019/AH0019C Dual DPST-TTL/DTL
Compatible MOS Analog Switches
General Description
Features
This series of TTLlDTL compatible MaS analog switches
feature high speed with internal level shifting and driving.
The package contains two monolithic integrated circuit
chips: the MaS analog chip consists of four MaS analog
switch transistors; the second chip is a bipolar I.C. gate and
level shifter. The series is available in hermetic dual-in-line
package.
•
•
•
•
•
•
•
•
These switches are particularly suited for use in both military
and industrial applications such as commutators in data acquisition systems, multiplexers, AID and D/A converters,
long time constant integrators, sample and hold circuits,
modulators/demodulators, and other analog signal switching applications.
The AH0014, AH0015 and AH0019 are specified for operation over the - 55°C to + 125°C military temperature range.
The AH0014C, AH0015C and AH0019C are specified for
operation over the - 25°C to + 85°C temperature range.
0
......
.j:o.
0
.......
:J>
::c
0
0
±10V
500 ns
Large analog voltage switching
Fast switching speed
Operation over wide range of power supplies
Low ON resistance
High OFF resistance
Analog signals in excess of
Fully compatible with DTL or TTL logic
Includes gating and level shifting
20011
1011 11
25 MHz
......
U1
.......
:J>
::c
0
0
......
U1
0
.......
:J>
::c
0
0
......
CD
.......
:J>
::c
0
0
......
CD
0
Block and Connection Diagrams
OualOPST
QuadSPST
r-- ------,
ANALOG
IN AI
ANALOG
IN 81
ANALOG
IN A2
ANALOG
INB2
8 I
I
9 I
I
"--,I
I
7:I
I
:
~
~~ I
i
~I
~___
I 10 ANALOG
OUT 1
--r-I
I
I5
ANALOG
----t-"-OUT 2
at~~
_ __ 1"-GNO
12 13
LOGIC
ANALOG 11
IN 1
ANAI;ll~
10
ANALOG _7
r---------,
I
....,.. ..j.!!... ANALOG
I
L _ __
IN3~
ANALOG ~
IN4 -----.:
I
I
I
OUT 1
j"
I
!
:
I
I
I:
I
I
I
I
I
I
I
•
B
I
15
ANALOG
OUT 3
ANALOG
OUT4
f,\-v+
t¥.- v-
L.ri-.
6_6
L:~j=~~
,.nehst--
LOGIC
4
A lOGIC
B
I
'i --f--+L ~~OG
i
I
I
LOGIC
3
lOGIC
2
lOGIC
1
TLiH/5563-2
TLiH/5563-1
Note: All logic inputs shown at logic "I".
AN~~~n------"1
ANALOG
IN BI
ANAlOG
IN A2
n :
~o ~ANALOG
I
I
I
ANAlOG~
IN B2
I
lOUT I
I
I
~I
10 ANALOG
I
OUTZ
~I ~I ill:~~
I:
I
0
l!!.-vcc
L
__
ll.-GNO
__..J
1 2
13 12
LOGIC
LOGIC
AI
A2
lOGIC
lOGIC
81
82
TL/H/5563-3
Note: All logic inputs shown at logic "I".
Note: All logic inputs shown at logic "I".
Order Number AH00140 or
AH0014CO
See NS Package Number 0140
Order Number AH00150 or
AH0015CO
See NS Package Number 016C
2-5
Order Number AH00190 or
AH0019CO
See NS Package Number 0140
PI
NatiOnal
~ Semiconductor
Corporation
AH5009, AH5010, AH5011, AH5012 Monolithic
Analog Current Switches
General Description
A versatile family of monolithic JFET analog switches economically fulfills a wide variety of multiplexing and analog
switching applications.
Even numbered switches may be driven directly from standard 5V logic, whereas the odd numbered switches are intended for applications utilizing 10V or 15V logic. The monolithic construction guarantees tight resistance match and
track.
For voltage switching applications see LF13331, LF13332,
and LF13333 Analog Switch Family, or the CMOS Analog
Switch Family.
Applications
•
•
•
•
•
AID and D/A converters
Micropower converters
Industrial controllers
Position controllers
Data acquisition
•
•
•
•
•
•
•
•
Active filters
Signal multiplexers/demultiplexers
Multiple channel AGC
Quad compressors/ expanders
Choppers/demodulators
Programmable gain amplifiers
High impedance voltage buffer
Sample and hold
Features
•
•
•
•
•
•
•
Interfaces with standard TIL and CMOS
"ON" resistance match
Low "ON" resistance
Very low leakage
Large analog signal range
High switching speed
Excellent isolation between
channels
20
.1000
50 pA
±10V peak
150 ns
80 dB
at 1 kHz
Connection and Schematic Diagrams (All switches shown are for logical "1 " input)
Dual-In-Llne Package
Dual-In-Llne Package
..
14
1J
15
"
LOGIC DRIVE
11
5VLOGIC
15V LOGIC
10
4 CHANNEL
MUX
4SPST
SWITCHES
AH5010C
AH5009C
AH5012C
AH5011C
14
1J
"
11
10
TOPVIEW
AH5009C and AH5010C MUX Switches
(4-Channel Version Shown)
Order Number AH5009CM,
AH5009CN, AH5010CM or AH5010CN
See NS Package Number M14A or N14A
TOP VIEW
AH5011C and AH5012C SPST Switches
(Quad Version Shown)
Order Number AH5011CM,
AH5011CN, AH5012CM or AH5012CN
See NS Package Number M16A or N16A
CO_EIISATING FEY
o
I'
100--+----'
120--+---'
,,0--4----'
130--+----'
"
"
COMMON DRAINS
IS
UReOMMlnED DRAINS TLlH/5659-1
Note: All diode cathodes are internally connected to the substrate.
2-6
»
::E:
Absolute Maximum Ratings (Note 1)
U1
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Input Voltage
AH50091 AH501 01 AH5011 1AH5012
Positive Analog Signal Voltage
30V
30V
Drain Current
30mA
Soldering Information:
N Package 10 sec
SO Package Vapor Phase (60 sec.)
Infrared (15 sec.)
300'C
215'C
220'C
CD
Power Dissipation
500mW
Negative Analog Signal Voltage
-15V
Operating Temperature Range
Diode Current
10mA
Storage Temperature Range
-25'C to +B5'C
- 65'C to + 150'C
Electrical Characteristics AH5010 and AH5012 (Notes 2 and 3)
Symbol
Parameter
Typ
Max
Units
IGSX
Input Current "OFF"
4.5V,,;VGO";11V, Vso=0.7V
TA=B5'C
0.01
0.2
10
nA
nA
IO(OFF)
Leakage Current "OFF"
Vso=0.7V, VGs=3.BV
TA=B5'C
0.02
0.2
10
nA
nA
IG(ON)
Leakage Current "ON"
VGo=OV,ls=1 mA
TA=B5'C
O.OB
1
200
nA
nA
IG(ON)
Leakage Current "ON"
VGo=OV,ls= 2 mA
TA=B5'C
0.13
5
10
nA
/LA
IG(ON)
Leakage Current "ON"
VGo=OV,ls= -2 mA
TA=B5'C
0.1
10
20
nA
/LA
rOS(ON)
Drain-Source Resistance
VGs=0.35V,ls=2 mA
TA=+B5'C
90
150
240
0.
0.
VOIOOE
Forward Diode Drop
lo=0.5mA
rOS(ON)
Match
VGs=O,lo=1 mA
TON
Turn "ON" Time
See AC Test Circuit
TOFF
Turn "OFF" Time
See AC Test Circuit
CT
CrossTalk
See AC Test Circuit
120
O.B
V
20
0.
150
500
ns
300
500
4
ns
dB
Electrical Characteristics AH5009 and AH5011 (Notes 2 and 3)
Parameter
Conditions
Typ
Max
Units
IGSX
Input Current "OFF"
11V,,;VGO,,;15V, Vso=0.7V
TA=B5'C
0.D1
0.2
10
nA
nA
IO(OFF)
Leakage Current "OFF"
Vso=0.7V, VGs=10.3V
TA=B5'C
0.01
0.2
10
nA
nA
IG(ON)
Leakage Current "ON"
VGo=OV,ls= 1 mA
TA=B5'C
0.04
0.5
100
nA
nA
IG(ON)
Leakage Current "ON"
VGo=OV,ls=2 mA
TA=85'C
2
1
nA
JJ-A
IG(ON)
Leakage Current "ON"
VGo=OV,ls= -2 mA
TA=B5'C
5
2
nA
JJ-A
rOS(ON)
Drain-Source Resistance
VGs=1.5V,ls=2 mA
TA=B5'C
100
160
0.
0.
VOIOOE
Forward Diode Drop
lo=0.5mA
O.B
V
rOS(ON)
Match
VGs=,lo=1 mA
10
0.
TON
Turn "ON" Time
See AC Test Circuit
150
50
ns
TOFF
Turn "OFF" Time
See AC Test Circuit
300
500
CT
CrossTalk
See AC Test Circuit. f = 100 Hz.
120
60
ns
dB
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: Test conditions 25°C unless otherwise noted.
Note 3: "OFF" and "ON" notation refers to the conduction state of the FET switch.
Note 4: Thermal Resistance:
N14A,N16A
M14A,M16A
6JA
92'C/W
11S'C/W
2-7
i>
::E:
U1
«:)
......
«:)
.......
»
::E:
U1
«:)
.....
......
.......
Conditions
Symbol
«:)
«:)
»
::E:
U1
«:)
.....
N
~
.....
r-------------------------------------------------------------------------------------~
~
Test Circuits and Switching Time Waveforms
;:::
Cross Talk Test Circuit
~
C;
i
'( 1
~-----+~1~5V~---------,
10k
::J:
~
>=-6______. .-0 VOUT
10k
I:)
In
::J:
::I:
Typical Performance Characteristics
U'I
o
o(Q
r-.!.;;
...oo
10k
VOS(OFFI @Vas '" -15V,lo:: -1 nA
U'I
~
los@lo::-lrnA,Vas=DV
!It.@Ves::-15V. Ves" OV PULSED
200
.......
l>
::I:
Leakage Current, IO(OFF)
vs Temperature
Parameter Interaction
1000
*
100~
I
10
.......
l>
::I:
./
lk
.9
10ss+-H++ttH
......o
.......
U'I
./
100
~
;
1--+-I-+t+Hit---jH+t+tttl
20
l>
::I:
;:i
'os
1.0
10
Vas
25
45
125
~p
:;:::.. r-
~~ClA?S
OS
-rtll\O.\~~
-
r- ~
35
45
55
65
-
~
~ -10
"...
-60
-50
-40
-30
-20
~
-10
85
100
lk
TA = 25°C
TA
..
2m~
25°C
::
Veo = -5V
f= 1 kHz
.5
w
u
100
Z
~
"
lo - 1 rnA
-f-
I
~
;:i
;
~ "1'
10
w
H=
~
1.0
10
::
I
5.0
10
10
~ VOS(OFF) = 2V
g
D.' mA-
I
o
~
I
15
M
1
-0.1
20
I
z
~
\
-15
1\
Ves = -IOV_
z
"
In
~
raSb
=
1
20
=~I=I
'os
~
II
VOSIOFF)
W
N
\
\
50
0
\1\
\
VOS (OFF)@-IOV,-10pA
u
f =1 kHz
TA=25°C -
\
-10
-5
Normalized Drain
Resistance vs Bias Voltage
100
1\
-20
-10
-1.0
DRAIN CURRENT (mAl
Drain Current vs Bias
Voltage
-25
~ ~VGS(OFF)=5V
~~110'''~1.5vllll
ORAIN·GATE VOLTAGE IVI
".5
1M
lOOk
Transconductance vs
Drain Current
100
lo~
10k
FREQUENCY IH.I
Leakage Current vs
Drain-Gate Voltage
z
I\)
t; -80
1000
'"'"
u
B5
VA:: ±10V
TEMPERATURE rCI
%
...
15
Cross Talk, CT vs Frequency
....-
15
65
-120
-110
-100
-90
o
25
55
TEMPERATURE rCI
"ON" Resistance, rOS(ON)
vs Temperature
100
35
GATE SOURCE CUTOFF VOLTAGE IV)
150
S
~
.e
o
10
100
10 =-1 rnA
...
U'I
10 L-._IILL...1.-U..uL-"----'---'-J....LJ.J.J..U 1.0
\. "\.
"'
1.0
::;
10
"
5.0
~
z
I
"'- t---.
.......
2.0
.e
-_.....
2.0
1.0
o
3.0
GATE·SOURCE VOLTAGE IVI
0.2
0.4
./
0.6
0.8
1.0
1VosIVOS(OFF)I- NORMALIZED GATE·
TO-SOURCE VOLTAGE IV)
2-9
TLiH/5659-3
~
g
::z:::
........~
o
It)
::z:::
oCt
,o
....o
It)
::z:::
~~
::z:::
oCt
r-------------------------------------------------------------------------------~
Applications Information
Theory of Operation
The AH series of analog switches are primarily intended for
operation in current mode switch applications; i.e., the
drains of the FET switch are held at or near ground by oper·
ating into the summing junction of an operational amplifier.
Limiting the drain voltage to under a few hundred millivolts
eliminates the need for a special gate driver, allowing the
switches to be driven directly by standard TTL (AH5010),
5V-l0V CMOS (AH5010), open collector 15V TTL/CMOS
(AH5009).
Two basic switch configurations are available: 4 independent switches (SPST) and 4 pole switches used for multiplexing (4 PST-MUX). The MUX versions such as the
AH5009 offer common drains and include a series FET operated at VGS= OV. The additional FET is placed in the
feedback path in order to compensate for the "ON" resistance of the switch FET as shown in Figure 1.
The closed-loop gain of Figure 1 is:
"OFF" state. With VIN=15V and the VA=10V, the source
of 01 is clamped to about 0.7V by the diode (VGs=14.3V)
ensuring that ac signals imposed on the 10V input will not
gate the FET "ON."
Selection of Gain Setting Resistors
Since the AH series of analog switches are operated in current mode, it is generally advisable to make the signal current as large as possible. However, current through the FET
switch tends to forward bias the source to gate junction and
the signal shunting diode resulting in leakage through these
junctions. As shown in Figure 2, IG(ON) represents a finite
error in the current reaching the summing junction of the op
amp.
Secondly, the rOS(ON) of the FET begins to "round" as Is
approaches loss. A practical rule of thumb is to maintain Is
at less than YIO of loss.
Combining the criteria from the above discussion yields:
Avel = R2 + rOS(ON)02
- Rl +rOS(ON)Ol
For Rl = R2, gain accuracy is determined by the rOS(ON)
match between 01 and 02. Typical match between 01 and
02 is 4 ohms resulting in a gain accuracy of 0.05% (for Rl
= R2 = 10 kn).
Rl . :2: VA(MAX) Ao
min
IG(ON)
(2a)
or:
:2: VA(MAX)
(2b)
loss/l0
whichever is larger.
Noise Immunity
The switches with the source diodes grounded exhibit improved noise immunity for positive analog signals in the
Rl
ANALOG V
INPUT A
10k
R2
10k
ANALOG
OUTPUT
-
-
FIGURE 1. Use of Compensation FET
--
--
VA
Is'"
Rl
VA =+10V
iii
ID = Is - IOIDN)
R2
TLfHf5659-4
FIGURE 2. On Leakage Current, IG(ON)
2-10
.-----------------------------------------------------~~
Applications Information
::r:
U1
(Continued)
o
o
Where: VA(MAX)
AD
= Desired accuracy
IG(ON)
loss
= Leakage at a given Is
= Saturation current of the FET
switch
CD
Accordingly:
= Peak amplitude of the analog
input signal
i>
::r:
Rl MAX $: VA(MIN) AD
(
) (N) IO(OFF)
Where: VA(MIN)
""20 mA
In a typical application, VA might = ±10V, Ao=O.I%,
O'C$:TA$:85'C. The criterion of equation (2b) predicts:
(10V)
Rl(MIN)" (201~A) 5 kn
U1
AD
= Minimum value of the analog
input signal
= Desired accuracy
N
= Number of channels
IO(OFF)
= "OFF" leakage of a given FET
switch
As an example, if N = 10, AD = 0.1 %, and IO(OFF) $: 10 nA
at 85'C for the AH5009. Rl(MAX) is:
10k
(1V)(10- 3)
Rl(MAX)$:(10)(10Xl0 9)
For Rl = 5k, Is "" 10V/5k or 2 mA. The electrical characteristics guarantee an IG(ON) $: 1p.A at 85'C for the AH5010.
Per the criterion of equation (2a):
(10V)(10- 3)
Rl(MIN)" lXl0 6 ,,10kn
....
o
o
i>
::r:
U1
........o
i>
::r:
U1
....o
N
Selection of R2, of course, depends on the gain desired and
for unity gain Rl =R2.
Lastly, the foregoing discussion has ignored resistor tolerances, input bias current and offset voltage of the op ampall of which should be considered in setting the overall gain
accuracy of the circuil.
Since equation (2a) predicts a higher value, the 10k resistor
should be used.
The "OFF" condition of the FET also affects gain accuracy.
As shown in Figure 3, the leakage across Q2, IO(OFF) represents a finite error in the current arriving at the summing
junction of the op amp.
TTL Compatibility
The AH series can be driven with two different logic voltage
swings: the even numbered part types are specified to be
driven from standard 5V TTL logic and the odd numbered
types from 15V open collector TTL.
--
ID '" Is + IDIDFFI
RI
Q2
fI
I~
"OFF"
VIN ·5V
TL/H/5659-5
FIGURE 3
2-11
~
..-
C)
In
:::E:
~
..-
..C)
~
c(
.....
C)
..C)
In
,---------------------------------------------------------------------------------,
Applications Information
(Continued)
Standard TIL gates pull-up to about 3.5V (no load). In order
to ensure turn-off of the even numbered switches such as
AH5010, a pull:up resistor, REXT, of at least 10 k!l should
be placed between the 5V Vee and the gate output as
shown in Figure 4 .
Likewise, the open-collector, high voltage TIL outputs
should use a pull-up resistor as shown in Figure 5. In
both cases, t(OFF) is improved for lower values of REXT at
the expense of power dissipation in the low state.
Definition of Terms
The terms referred to in the electrical characteristics tables
are as defined in Figure 6.
:::E:
c(
.....
en
C)
C)
In
:::E:
c(
r---------,
I
I
I
I
I
I
ANALOG
INPUT (VA)
+5V
10k
RUT
>""'''''''0 ANALOG
OUTPUT
(2k
TO
10k)
LOGIC
INPUT
I
(VIN)
I
I
I
I
__ I
l.!!.~~ __-_ -=--.1
FIGURE 4. Interfacing with
+5V OR +15V
ANALOG
INPUT (VA)
.-------,
I
I
I
I
I
+ 5V TTL
I
I
I
I
I
10k
>""'''''''0 ANALOG
OUTPUT
+15V
REXT
(ZkTO
10k)
LOGIC
INPUT
IV ..)
TL/H/5659-6
FIGURE 5. Interfacing with
+ 15V Open Collector TTL
2-12
.--------------------------------------------------------------------.~
Applications Information
::I:
(Continued)
U1
Q
Q
CD
);
COMPENSATING
ELEMENT
RDSIDNI
::I:
U1
Q
.....
Q
......
Is
R,
~
R,
::I:
U1
Q
.....
.....
);
SHUNT - '
ELEMENT
::I:
U1
Q
.....
I\)
FIGURE 6. Definition of Terms
Typical Applications
De-Glltched Switch for Noiseless Audio Switching
OFF
5V
r
AUDIO
SIGNAL
INPUT
R
RC TYPICAllY
(1 ms-l0 msl
Rf
0--""""1\1"'""-.........
PI
>-4'---<> OUT
TL/H/5659-7
2-13
Typical Applications (Continued)
3-Channel Multiplexer with Sample and Hold
10k
11
I
10k
ANALOG
INPUTS
I
10k
IL__ •
4
I
_ _ _ _ _ ...JI
12
1
SAMPLE/HOLD
SELECT
CHARACTERISTICS: TYPICAL OUTPUT
VOLTAGE DRIFT
14
I '. . .
~---'
CHANNEL
SELECT
-.....--,
E1N4
141
o-"VV'...:-:.>-......
--,
I
II":"
~
13
::::c
UI
o.....
II
I\)
15
'-- _ _ _ _
_ ---1
J
r--AH50ii'""-ll
I
I
IB
I
EIN7
E1N8
I
11
I9
14
EOUT
E1N9
E1N10
EINll
EIN12
Jr--AH50ii'""--' 1
I
I
I
I
61
IB
I
I
I
I
I
CHARACTERISTICS:
I
Note: The analog switch between the op amp and the 16 input
I
I9
111
ERROR~O.4I'V
TYPICAL
10I'V TYPICAL
@
@
25"C
70"C
1,6
141
I
I 13
L~
I
switches reduces the errors due to leakage.
__I~_J
All resistors are 10k.
2-15
TLlH/5659-9
('II
..-
oLt)
:J:
Typical Applications
(Continued)
«
......
Gain Programmable Amplifier
....-
oLt)
~
:J:
«
......
o
..oLt)
10'
':"
:J:
«
......
en
o
oLt)
:J:
«
11
r
llIk
I
I
I
6
100.
9
1M
13
10M
I
I
I
I
I
I
I
I
--1 CHARACTERISTICS: GAIN '"
L_
12
GAIN SELECT
-EOUT ..,
RFB
"N
TLlH/5659-10
2-16
r----------------------------------------------------------------,~
::J:
~ Semiconductor
NatiOnal
U1
o
o
I\)
Corporation
o
AH5020C Monolithic Analog Current Switch
General Description
Applications
This versatile dual monolithic JFET analog switch economically fulfills a wide variety of multiplexing and analog switching applications.
• AID and D/A converters
• Micropower converters
• Industrial controllers
• Position controllers
• Data acquisition
• Active filters
• Signal multiplexers/demultiplexers
• Multiple channel AGC
• Quad compressors/expanders
• Choppers/demodulators
• Programmable gain amplifiers
• High impedance voltage buffer
• Sample and hold
For voltage switching applications see LF13201, LF13202,
LF13331, LF13332, and LF13333 Analog Switch Family, or
the CMOS Analog Switch Family.
These switches may be driven directly from standard 5V
logic.
The monolithic construction guarantees tight resistance
match and track.
Features
•
•
•
•
•
•
•
Interfaces with standard TTL
"ON" resistance match
Low "ON" resistance
Very low leakage
Large analog signal range
High switching speed
Excellent isolation between
channels
20
1500
50 pA
± 10V peak
150 ns
80 dB
at 1 kHz
Connection and Schematic Diagrams (All switches shown are for logical "1 ")
Dual-In-Llne Package
TLlH/5166-1
Top View
Order Number AH5020CJ
See NS Package Number J08A
3
TLlH/5166-2
Nole: All diode cathodes are internally connected to the substrate.
2-17
Absolute Maximum Ratings
(Note 1)
If MIlitary/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Input Voltage
30V
Positive Analog Signal Voltage
30V
-15V
Negative Analog Signal Voltage
Diode Current
10mA
Drain Current
Power Dissipation
Operating Temp. Range
Storage Temperature Range
Lead Temp. (Soldering, 10 seconds)
30mA
500mW
- 25'C to + B5'C
- 65'C to + 150'C
300'C
Electrical Characteristics (Notes 2 and 3)
Symbols
Parameter
Conditions
Typ
Max
Units
0.Q1
0.01
0.1
0.2
10
nA
nA
nA
0.Q1
0.2
10
nA
nA
= 1 mA
O.OB
1
200
nA
nA
VGD = OV, Is
TA = 85'C
= 2 mA
0.13
5
10
nA
IJ.A
Leakage Current "ON"
VGD = OV, Is
TA = 85'C
= -2 mA
0.1
10
20
nA
IJ.A
rDS(ON)
Drain-Source Resistance
VGS = 0.5V, Is
TA = +B5'C
90
150
240
n
n
VDIODE
Forward Diode Drop
ID
rDS(ONI
Match
VGS
TON
Turn "ON" Time
TOFF
CT
IGSX
Input Current "OFF"
VGD = 4.5V, VSD = 0.7V
VGD = llV, VSD = 0.7V
TA = B5'C, VGD = l1V, VSD
ID(OFF)
Leakage Current "OFF"
VSD = 0.7V, VGS
TA = B5'C
IG(ON)
Leakage Current "ON"
VGD = OV, Is
TA = 85'C
IG(ON)
Leakage Current "ON"
IG(ON)
= 3.BV
= 2 mA
= 0.5mA
= 0, ID = 1 mA
= 0.7V
0.8
V
2
20
n
See ac Test Circuit
150
500
ns
Turn "OFF" Time
See ac Test Circuit
300
500
CrossTalk
See ac Test Circuit
120
ns
dB
Nota 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical spacHlcatlons do not apply when operating
the device beyond Its specified operating conditions.
Nota 2: Test conditions 25'C unless otherwise noted.
Note 3: "OFF" and "ON" notation refers to the conduction state of the FET switch.
Note 4: Thermal Resistance:
8JA (Junction to Ambient) .......... N/A
8JC (Junction to Case) ............. N/A
2-1B
>
::J:
Test Circuits
U1
oI\)
o
o
AC Test Circuit
Cross Talk Test Circuit
15V D.l ""
~
VA=±IDV
.---.....-00 VOUT
(CLslDpF)
lDk
>=--....-VOUT
10k
D.l ""
lDk
-15V
TLlH/5166-4
~
TL/H/5166-3
Switching Time Waveforms
VIN
I,
= If'; D.l,..
DV
D.BV
--+-'"
--i--I'.....
VOUT
VA = +IDV
DV
ov
VOUT
VA~ - I D V - - I I - - t " - - - + - _ J
TL/H/5166-5
2-19
Typical Performance Characteristics
Leakage Current, IO(OFF)
vs Temperature
Parameter Interaction
1000
100
VaS(OFF) @ ¥Os = 15V,Io- -1 nA
IDS @1o=-lmA,Vas=OV
§:
...uc-
!GIs @Vas--15V, Vas=OV pu~~
zE
e~ 200
loss
Wo"'"
!~ 100
II: II:
10
:Zz
i::
10k
...
~
i!
S
z
!Z
i
I
:II
II:
..
m
?:!
~'"
a
... ros
iii
20
./
100
I
I
J
........-"I
lk
=>
u
co
c::
J
10
1.0
100
1.0
S 10
VGS-GATE-SOURCE CUTOFF VOLTAGE (V)
10
25
35
45 55 65 75
TEMPERATURE rC)
85
TL/H/5166-6
TL/H/5166-7
"ON" Resistance, rOS(ON)
vs Temperature
1S0
.t
ID= -1 mA
5VTTL
~
P
5Vs=.
Cross Talk, CT vs Frequency
-120 rr~~rrnr~~~~
-110 H..rI-H--+-t+lt-t-+ VA = ±10V
......
~-100 ~-R~+44*~++~~+H
:!5!. -90 ~-H*",N,,*~++fI--'~+H
~-ooHH~~~~++~
~
I: -70 1+-I+H-H+It""".alH~~
Ii! -60
i-"~TTL/l0~-I5V CMOS
1+-I+H-H+It++I'I!Ic::I~1H
'i' -50 1+-I+H-H+It++tIH"'I'1'H
t; -40 I+-++++-H-H+++HH-t-I+I
-30 t-+tffi+ttit+ttit+ttH
-20 1++f,1H-t-H+-+-I+It++I+I
o
-10~~~~~~w-~~
25
35
45 55 65 75
TEMPERATURE rC)
85
lk
10k
lOOk
FREQUENCY (Hz)
100
1M
TLlH/5166-B
TL/H/5166-9
Leakage Current vs
Drain-Gate Voltage
Transconductance vs
Drain Current
100
; l000~~
ffi~
I...
100
!il
=>
u
~ 10
...
I...
I
10
:i
5.0
10
15
20
DRAlN.(lATE VOLTAGE (V)
TA 25·C
Voo=-5V
1=1 kHz
II
FV6S(IIfFI=2V ~~
:--V6S(OFF) -
1
1/ . . .
-0.1
25
II
V6S(DFf) =I 7.SV
sv
II
-10
-1.0
DRAIN CURRENT (mA)
TLlH/5166-11
TL/H/5166-10
Drain Current vs Bias
Voltage
-25
1
!Z
~ -15
u
1-
1.
\
\
-5
o
z~
.e...
, '-
~
10
S100
VDS=-IDV
1=1 kHz
TA=25"C
\
i- 20
Normalized Drain Resistance
vs Bias Voltage
II:
\
o
"-
"'
Vos(OFf) ~~OV,_-10""
IDSb =
~
""- """
'-
1.0
iii
co
z
: i=
l-Vos(OFF)
--
20
J
5.0
I 2.0
~
!oo.
§
----vas
'" 10
::I
1\
~
50
.... ~"'" ""
0.2 0.4
0.6 0.8 1.0
IVas IVGS(IIfFII-NORMALIZEO
GATE-TCJ.SOURCE VOLTAGE (V)
2.0
3.0
GATE-SOURCE VOLTAGE (V)
TLlH/5166-12
TLlH/5166-13
2-20
l>
:J:
Applications Information
en
Q
N
THEORY OF OPERATION
NOISE IMMUNITY
The AH5020 analog switches are primarily intended for operation in current mode switch applications; i.e., the drains
of the FET switch are held at or near ground by operating
into the summing junction of an operational amplifier. Limiting the drain voltage to under a few hundred millivolts eliminates the need for a special gate driver, allowing the
switches to be driven directly by standard TTL.
The switches with the source diodes grounded exhibit improved noise immunity for positive analog signals in the
"OFF" state. With VIN = 15V and the VA = 10V, the
source of 01 is clamped to about 0.7V by the diode (VGS =
14.3V) ensuring that ac signals imposed on the 10V input
will not gate the FET "ON".
SELECTION OF GAIN SETTING RESISTORS
If only one of the two switches in each package is used to
apply an input signal to the input of an op amp, the other
switch FET can be placed in the feedback path in order to
compensate for the "ON" resistance of the switch FET as
shown in Figure 1.
Since the AH5020 analog switches are operated in current
mode, it is generally advisable to make the signal current as
large as possible. However, current through the FET switch
tends to forward bias the source to gate junction and the
signal shunting diode resulting in leakage through these
junctions. As shown in Figure 2, IG(ON) represents a finite
error in the current reaching the summing junction of the op
amp.
The closed-loop gain of Figure 1 is:
A
-
R2
Q
o
+ rOS(ON)02
veL - - R1 + rOS(ON)01
Secondly, the rOS(ON) of the FET begins to "round" as Is
approaches loss. A practical rule of thumb is to maintain Is
at less than '110 of loss.
Combining the criteria from the above discussion yields:
For R1 = R2, gain accuracy is determined by the rOS(ON)
match between 01 and 02. Typical match between 01 and
02 is 20 resulting in a gain accuracy of 0.02% (for R 1 = R2
= 10 kO).
R1 MIN
()
~
VA(MAX) Ao
IG(ON)
(2a)
or:
~ VA(MAX)
1055 /10
whichever is larger.
VA
81
10k
(2b)
82
10k
ANALOG ~W_....- - - .
INPUT
>--~~=~
TL/H/5166-14
FIGURE 1. Use of Compensation FET
IS!!!
:~
81VA=10V --'Wlr-o-....-....,
R2
TL/H/5166-15
FIGURE 2. On Leakage Current, IG(ON)
2-21
fJ
Applications Information
Where VA(MAX)
AO
IG(ON)
loss
(Continued)
Accordingly:
= Peak amplitude of the analog input
signal
= Desired accuracy
= Leakage at a given Is
= Saturation current of the FET switch
= 20mA
VA(MIN) Ao
(N) IO(OFF)
Where VA(MIN) = Minimum value for the analog input signal
Ao
= Desired accuracy
N
= Number of channels
IO(OFF)
= "OFF" leakage of a given FET switch
As an example, if N=10, Ao=0.10/0, and IO(OFF) s: 10 nA
at 85'C for the AH5020. R1(MAX) is:
(1V)(10- 3)
R1(MAX) s: (10)(10 X 10 9) 10k
(AX)
In a typical application, VA might = ±10V, Ao =0.1%, O'C
s: TA s: 85'C. The criterion of equation (2b) predicts:
10V
R1(MIN);;' 20 mA =5 kO
10
For R1 = 5k, Is "" 10Vl5k or 2 mAo The electrical characteristics guarantee an IG(ON) s: 1jJ.A at 85'C for the
AH5020. Per the criterion of equation (2a):
R1
(MIN)
s:
R1 M
Selection of R2, of course, depends on the gain desired and
for unity gain R1 = R2.
;;, (10V)(10- 3) ;;, 10 kO
1 X 10-6
Lastly,
ances,
amp overall
Since equation (2a) predicts a higher value, the 10k resistor
should be used.
the foregoing discussion has ignored resistor tolerinput bias current and offset voltage of the op
all of which should be considered in setting the
gain accuracy of the circuit.
The "OFF" condition of the FET also affects gain accuracy.
As shown in Figure 3, the leakage across Q2, IO(OFF) represents a finite error in the current arriving at the summing
junction of the op amp.
'sal
R1VA1-W_o-....-
R1
R2
.....
IDI!!!.f
TL/H/5166-16
FIGURE 3. Off Leakage Current, IO(OFF)
2-22
Applications Information
(Continued)
TTL COMPATIBILITY
DEFINITION OF TERMS
Standard TTL gates pull-up to about 3.5V (no load). In order
to ensure turn-off of the AH5020, a pull-up resistor, REXT of
at least 10 k!l. should be placed between the 5V Vcc and the
gate output as shown in Figure 4.
The terms referred to in the electrical characteristics tables
are as defined in Figure 5.
r------'5V
ANALOG
INPUT (VA)
10k
Rm
(2k
TO
10k)
I
I
I
I
ANALOG
OUTPUT
LOGIC
INPUT (VIN)
1.::
_ _ _ _"::""::"
_ _ -.1I
IsvmGATE
TL/H/5166-17
FIGURE 4. Interfacing with
+ SV TTL
VA .......W'r-.....--~
~:':-
TL/H/5166-18
FIGURE 5. Definition of Terms
2-23
o ,------------------------------------------------------------------,
o
S Typical Applications
It)
:J:
c:(
Deglltched Switch for NOiseless Audio Switching
OFF
rON
HC TYPICALLY
1 ms-l0 ms
AUDIO
SIGNAL -""",,Mr-"'-:-:~
INPUT
OUT
TL/H/5166-19
Gain Programmable Amplifier
10k
>'----..- EoUT
r
10k
l
I
I
I
I
I
I
I
lOOk
Characteristics: Gain
L __ _
~
- EOUT
liN
~
RFS
2
GAIN SELECT
TL/H/5166-20
2-24
o
c
NatiOnal
~ Semiconductor
.j:o.
o
......
a>
Corporation
m
3:
......
o
c
CD4016BM/CD4016BC Quad Bilateral Switch
.j:o.
o
......
General Description
a>
The CD4016BM/CD4016BC is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with CD4066BM/
CD4066BC.
Features
3V to 15V
Wide supply voltage range
Wide range of digital and analog switching ±7.5 VPEAK
4000. (typ.)
"ON" resistance for 15V operation
Matched "ON" resistance over 15V
signal input
ARON = 100. (typ.)
0.4 % distortion (typ.)
• High degree of linearity
@flS = 1 kHz, VIS=5V p•p,
•
•
•
•
Voo-VSS= 10V, RL = 10 ko.
• Extremely low "OFF" switch leakage
0.1 nA (typ.)
@Voo - Vss=10V
TA=25°C
• Extremely high control input impedance
10120.
• Low crosstalk between switches
- 50 dB
@IIS=0.9 MHz, RL =
• Frequency response, switch "ON"
40 MHz
(typ.)
(typ.)
1 ko.
(typ.)
Applications
• Analog signal switching/multiplexing
• Signal gating
• Squelch control
• Chopper
• Modulator/Demodulator
• Commutating switch
• Digital signal switching/multiplexing
• CMOS logic implementation
• Analog-to-digital/digital-to·analog conversion
• Digital control of frequency, impedance, phase, and analog·signal gain
Schematic and Connection Diagrams
Dual-In-Line Package
14 Voo
IN/OUT
OUT/IN -=-If-_....I
CONTROL---t----[:><_--...,
~==~i13::"'CONTROLA
OUT/IN
I N / O U T - - I r f · - OUT/IN
12 CONTROL 0
11
IN/OUT
CONTROL B
IN/OUT
OUTIIN
CONTROL C
......--+:.... OUT/IN
Vss
IN/OUT
....;.t----,
TOP VIEW
TL/F/5661-1
Cavity Dual-In-Line Package (J)
Order Number CD4016BMJ or CD4016BCJ
See NS Package Number J14A
Small Outline Package (M)
Order Number CD4016BCM
See NS Package Number M14A
Molded Dual-In-Line Package (N)
Order Number CD4016BMN or CD4016BCN
See NS Package Number N14A
2-25
m
o
~
CD
.,...
o
~
C
(J
.....
:E
In
CD
.,...
o
~
C
(J
Absolute Maximum Ratings
Recommended Operating
Conditions (Note 2)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications•
(Note 7)
(Notes 1 and 2)
Voo Supply Voltage
-0.5Vto +18V
VIN Input Voltage
-0.5Vto Voo + 0.5V
Ts Storage Temperature Range
-65'Cto + 150'C
Po Package Dissipation
500mW
Lead Temperature (Soldering. 10 seconds)
260'C
Voo Supply Voltage
VIN Input Voltage
TA Operating Temperature Range
CD4016BM
CD4016BC
3V to 15V
OVtoVoo
- 55'C to + 125'C
-40'Cto +85'C
DC Electrical Characteristics CD4016BM (Note 2)
Symbol
Parameter
-55'C
Conditions
Min
100
Quiescent Device Current
Max
25'C
Min
125'C
Typ
Max
Min
Units
Max
Voo=5V. VIN=VOoorVss
Voo= 10V. VIN=VOO orVss
Voo= 15V. VIN = Voo or Vss
0.25
0.5
1.0
0.01
0.01
0.01
0.25
0.5
1.0
7.5
15
30
/LA
/LA
/LA
RL =10knto Voo-Vss
2
Vc=Voo. VIS=VSS orVoo
Voo= 10V
Voo=15V
600
360
250
200
660
400
960
600
n
n
RL =10knto Voo-Vss
2
Vc=Voo
Voo= 10V. VIS=4.75 to 5.25V
Voo=15V. VIS=7.25t07.75V
1870
775
850
400
2000
850
2600
1230
n
n
Signal Inputs and Outputs
RON
~RON
liS
"ON" Resistance
Resistance
Between any 2 of
4 Switches
(In Same Package)
RL =10knto Voo-Vss
2
Vc=Voo. VIS=VSS to Voo
Voo=10V
Voo=15V
Input or Output Leakage
Switch "OFF"
Vc=O. Voo=15V
VIS= 15V and OV.
Vos=OVand 15V
~"ON"
15
10
±50
±0.1
n
n
±50
±500
nA
0.7
0.7
0.7
0.5
0.5
0.5
V
V
V
Control Inputs
VILe
VIHC
liN
Low Level Input Voltage
High Level Input Voltage
Input Current
VIS=VSS and Voo
Vos=Voo and Vss
Ils= ± 10 /LA
Voo=5V
Voo=10V
Voo=15V
Voo=5V
Voo=10V
Voo=15V
0.9
0.9
0.9
(see Note 6 and
Figure 8)
3.5
7.0
11.0
3.5
7.0
11.0
±0.1
Voo-Vss=15V
VOO;;;,VIS;;;'VSS
Voo;;;'Vc;;;'Vss
2-26
3.5
7.0
11.0
±10-5
±0.1
V
V
V
±1.0
/LA
o
c
DC Electrical Characteristics CD4016BC (Note 2) (Continued)
Symbol
Parameter
-40'C
Conditions
Min
100
Quiescent Device Current
.j:>,
Max
25'C
Min
1.0
2.0
4.0
Voo = 5V, VIN = Voo or Vss
Voo= 10V, VIN=VOO orVss
Voo=15V, VIN=VooorVss
85'C
Typ
Max
0.01
0.01
0.01
1.0
2.0
4.0
Min
Units
Max
7.5
15
30
p.A
p.A
p.A
Signal Inputs and Outputs
RON
aRON
610
370
275
200
660
400
840
520
n
n
1900
790
850
400
2000
850
2380
1080
n
n
RL = 10 kn to Voo-Vss
2
Vc=Voo, VIS=VSS to Voo
Voo= 10V
Voo=15V
n
n
15
10
±50
Vc=O, Voo=15V
I VIS=OVor15V,
±0.1
±50
±200
nA
0.7
0.7
0.7
0.4
0.4
0.4
V
V
V
Vos= 15VorOV
Control Inputs
VILC
VIHC
liN
Low Level Input Voltage
High Level Input Voltage
Input Current
VIS=VSS and Voo
Vos=Voo and Vss
IIS= ±10 p.A
Voo=5V
Voo=10V
Voo=15V
Voo=5V
Voo=10V
Voo=15V
0.9
0.9
0.9
(see Note 6 and
FigureS)
3.5
7.0
11.0
3.5
7.0
11.0
±0.3
VCc-Vss= 15V
VOO:2:VIS:2:VSS
Voo:2:Vc:2:Vss
V
V
V
3.5
7.0
11.0
±10- 5
±0.3
±1.0
p.A
AC Electrical Characteristics TA = 25'C, t,=tf= 20 ns and Vss= OV unless otherwise specified
Typ
Max
Units
Vc=Voo, CL =50 pF, (Figure 1)
RL =200k
Voo=5V
Voo=10V
Voo=15V
58
27
20
100
50
40
ns
ns
ns
Propagation Delay Time
Control Input to Signal
Output High Impedance to
Logical Level
RL = 1.0 kn, CL = 50 pF, (Figures 2
and 3)
Voo=5V
Voo=10V
Voo=15V
20
18
17
50
40
35
ns
ns
ns
Propagation Delay Time
Control Input to Signal
Output Logical Level to
High Impedance
RL = 1.0 kn, CL = 50 pF, (Figures 2
and 3)
VOO=5V
Voo=10V
Voo=15V
Vc=Voo=5V, Vss=-5
RL = 10 kn, VIS=5 Vp_p, f= 1 kHz,
(Figure 4)
15
11
10
0.4
40
25
22
ns
ns
ns
Symbol
Parameter
tpHL, tpLH
Propagation Delay Time
Signal Input to Signal Output
tpZH, tpZL
tpHZ, tpLZ
o
c
"'"
o
......
en
OJ
a"ON" Resistance
Between any 2 of
4 Switches
Input or Output Leakage
Switch "OFF"
OJ
.......
==
o
RL = 10 kn to voo -vss
2
Vc=Voo, VIS=VssorVoo
Voo=10V
Voo=15V
RL = 10 kn to Voo-Vss
2
Vc=Voo
Voo= 10V, Vls=4.75 to 5.25V
Voo= 15V, Vls=7.25 to 7.75V
"ON" Resistance
(In Same Package)
liS
o
......
en
Sine Wave Distortion
Conditions
2-27
Min
%
AC Electrical Characteristics (Continued)
TA=25°C, t,=tf=20 ns and Vss=OV unless otherwise specified
Symbol
Parameter
Min
Conditions
Frequency Response - Switch
"ON" (Frequency at - 3 dB)
VC=VOO=5V, Vss= -5V,
RL = 1 kO, VIS=5 Vp.p,
20 Log,o VoslVos (1 kHz) -dB,
(Figure4j
Voo=5V, Vc=Vss= -5V,
RL = 1 kO, VIS = 5 Vp.p,
20 Log,o (VOSIVIS)= -50 dB,
(Figure4j
VOO=VC(A)=5V; VSS=VC(B)= -5V,
RL = 1 kOVIS(A) = 5 Vp.p,
20 Log,o (VOS(8)IVOS(A)= -50 dB,
(FigureS)
Voo= 10V, RL = 10 kO
RIN=1 kO, Vcc=10V Square Wave,
CL = 50 pF (Figure 6)
RL = 1 kO, CL = 50 pF, (Figure 7)
VOS(f) = % Vos(1 kHz)
Voo=5V
Voo=10V
Voo=15V
Feedthrough - Switch "OFF"
(Frequency at -50 dB)
Crosstalk Between Any Two
Switches (Frequency at -50 dB)
Crosstalk; Control Input to
Signal Output
Maximum Control Input
Signal Input Capacitance
Cos
CIN
Signal Output Capacitance
VOO=10V
Feedthrough Capacitance
VC=OV
Typ
Max
Units
40
MHz
1.25
MHz
0.9
MHz
150
mVp.p
6.5
8.0
9.0
MHz
MHz
MHz
4
pF
4
pF
0.2
Control Input Capacitance
pF
7.5
5
pF
Note ,: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Recommended Operating Conditions" and "Electrical Characteristics" provide conditions for actual device
operation.
Note 2: Vss=OV unless otherwise specHied.
Note 3: These devices should not be connected to circuits wHh the power "ON".
Note 4: In all cases, there is approximately 5 pF of probe and jig capacitance on the output; however, this capacitance is included in CL wherever it is specified.
Note 5: VIS is the voltage at the in/out pin and Vos is the voltage at the outlin pin. Vc is the voltage at the control input.
Note 6: If the switch input is held at VCD, VIHC is the control input level that will ceuse the switch output to meet the standard "B" series VOH and IOH output levels.
If the analog switch input is connected to Vss. VIHC is the control input level-which allows the switch to sink standard "B" series
maintain a VOL ~ "B" series. These currents are shown in Figure 8.
IIOHI, high level current, and still
Note 7: Refer to RETS40168X for milHary specifications.
AC Test Circuits and Switching Time Waveforms
ve.v •• ~
vI"
VDD~-"~D%
-..I''
,"""e''''N~T.:;;'';---::v,l.••
VIS
1 Of 4 OUT/IN
IN/OIlT SWITCHES
Vss
.
~
-"-
v's
1--""'--"""1r-VOS
1
I ..Le,"::"
!~._,
I""
50%
DV
111%
VDD~-tpLH
tpHl
r
Vos
50%
DV
Figure 1, tpLH. tpLH Propagation Delay Time Signal Input to Signal Output L
tpZH
CONTROL
VOU
..I
.1.
I"""
INIOUT ~~~:ES OUT/INI-.....- _ -
VSS
~
-I ..LCL
-,-VDS
VDD~
..
DV~_tpZH
VD.
VDD~VDD
'"
'V~PHZ
VD.
".
DV
.V
ID"
TUF/5661-2
FIGURE 2. tpZH. tpHZ Propagation Delay Time Control to Signal Output
2·28
.-----------------------------------------------------------------------,0
C
AC Test Circuits and Switching Time Waveforms (Continued)
.Do
....
o
en
m
3:
......
tpZL
VDD
o
tPLl
""
VDD~
..
VDD~
DV~.,PZl
__
VD.
Vou
""
DV
'Pll_-
90%
VDD
VDl
~
""
VDl
FIGURE 3. tpZH' tpHZ Propagation Delay Time Control to Signal Output
ve----.
25V_~
VIS
ov
1
/ \
-2.5V~~
'J
I
Vc=Voo for distortion and frequency response tests
-5V
Vc=Vss for feedthrough test
FIGURE 4. Sine Wave Distortion, Frequency Response and Feedthrough
VeIAI' Vou - - - . ,
IN/OUT
S~I~~:ES DUT/INI--.-- VoslAJ
Vss
RL
Ik
-5V
VIS(1)
VeI B' - VSS - - - - . . . ,
,
2.::-t=-r\~C\
V
-2.5V-~
1-----1/1
VISIB'- ov
RL
Ik
-5V
FIGURE 5. Crosstalk Between Any Two Switches
Ve
',-20,,,
Voo
It- =\1-
Ve
RIN
Ik
':"
OV
'N/OUT S~'~~:ES OUT/IN
VIS
10%
VOS
Vss
':"
'1- 20 ,,,
90Y.
RL
10k
I
CL
50.'
VOS
':"
I
r
C-,
'
CROSSTALK
I
TUF/5661-3
FIGURE 6. Crosstalk - Control to Input Signal Output
2-29
C
.Do
o
....
en
m
o
(.)
m
CD
.,...
o
..,.
AC Test Circuits and Switching Time Waveforms
T
VC~
Q
(.)
.......
::E
CONTROL
m
.,...
CD
VIS~ VOD- IN/OUT
o
..,.
90%
av
S~I~~~ES OUT/IN
""
Vos
Vss
.LCl
t
Q
(.)
l"I--1"I""
v"
v,
Voo
90%
''''
---1/1
~Rl
1
1k
ISo"
-,VDS@llkHz
vos
~
'::-
(Continued)
T
TLlF/5661-4
FIGURE 7. Maximum Control Input Frequency
Temperature
Range
Switch Output
Switch Input
Voo
MILITARY
COMMERCIAL
VOS(V)
liS (mA)
VIS
TLOW
25'C
THIGH
Min
5
5
10
10
15
15
0
5
0
10
0
15
0.25
-0.25
0.62
-0.62
1.8
-1.8
0.2
-0.2
0.5
-0.5
1.5
-1.5
0.14
-0.14
0.35
-0.35
1.1
-1.1
5
5
10
10
15
15
0
5
0
10
0
15
0.2
-0.2
0.5
-0.5
1.4
-1.4
0.16
-0.16
0.4
-0.4
1.2
-1.2
0.12
-0.12
0.3
-0.3
1.0
-1.0
Max
0.4
4.6
0.5
9.5
1.5
13.5
0.4
4.6
0.5
9.5
1.5
13.5
FIGURE 8. CD4016B Switch Test Conditions for VIHC
Typical Performance Characteristics
'ON' Resistance Temperature
Variation for Voo-VSS= 15V
'ON' Resistance Temperature
Variation for Voo- VSS = 10V
'ON' Resistance vs. Signal
Voltage T A = 25'C
900
J...
800
700
'"'z~ 600
'" 500
m 400
z
!? 300
.......z
..
z
5
200
100
900
800
1\ VOD-Vss=10V
\
\
'\~
/
~:::..
1/
~
SOD
VD. - Vss = 15V
400
300
I'-
200
I ......
100
-8 -6 -4 -2
0
2
4
SIGNAL INPUT (V,sIlVI
6
8
i...
II.~
\~
700
600
VII
V
VJ
1,1'/'
'"'z
~
l~
i~
~
Ii.;:::
~
.""-
@+125'C
'@+8S'C
,,@ +2S'C
~ @ -40'C
-@-SS'C
~
500
400
300
Z 200
!?
.......z
.
z
100
1
@ +125'C
@ +85'C
@ +25'C
/
'/
'- /
P== ~
.7 I\,
:1" I\,:
J
~V
~
~
"
~~
@-40'CZ
@ -55'C
I
~
5
-8 -6 -4 -2
0
2
4
S'GNAllNPUT {V"IIVI
6
8
-8 -6 -4 -2
0
2
4
6
8
SIGNAL INPUT (V,sIlVI
TL/F/5661-5
2-30
,-----------------------------------------------------------------------.0
c
Typical Applications
....~
4 Input Multiplexer
G)
m
.....
==
CHANNEL 1
o
c
~
....
<:)
G)
m
o
CHANNEL 2
COMMON
CHANNEL 3
CHANNEL 4
3
2
1
CONTROL
Sample/Hold Amplifier
OUTPUT
INPUT
TLlF/5661-6
Special Considerations
supply voltages, ~5V, the CD4016S's on resistance becomes non-linear. It is recommended that at 5V, voltages
on the in/out pins be maintained within about tV of either
Voo or Vss; and that at 3V the voltages on the in/out pins
should be at Voo or Vss for reliable operation.
The CD4016B is composed of 4, two-transistor analog
switches. These switches do not have any linearization or
compensation circuitry for "RON" as do the CD4066B's. Because of this, the special operating considerations for
the CD4066B do not apply to the CD4016S, but at low
2-31
PI
or------------------------------------------------------------------.
m
C")
&I)
o
~
o
.....
NatiOnal
~ Semiconductor
Corporation
:::i
m CD4051BM/CD4051BC Single 8-Channel Analog
f3
MultiplexerIDemultiplexer
o CD4052BM/CD4052BC Dual 4-Channel Analog
.....
MultiplexerIDemultiplexer
~
N
CD4053BM/CD4053BC Triple 2-Channel Analog
~
C
MultiplexerIDemultiplexer
o
o
'Oil'
C
&I)
.....
:::i
m
General Description
N
&I)
o
~
o
.....
....~
&I)
o
'Oil'
C
o.....
:::i
m
....
&I)
~
C
o
These analog multiplexers/demultiplexers are digitally controlled analog switches having low "ON" impedance and
very low "OFF" leakage currents. Control of analog signals
up to 15Vp_p can be achieved by digital signal amplitudes of
3-15V. For example, if VOO=5V, Vss=OV and VEE= -5V,
analog signals from - 5V to + 5V can be controlled by digital inputs of 0-5V. The multiplexer circuits dissipate extremely low quiescent power over the full Voo-Vss and
VOO-VEE supply voltage ranges, independent of the logic
state of the control signals. When a logical "1" is present at
the inhibit input terminal all channels are "OFF".
CD4051BM/CD4051BC is a single 8-channel multiplexer
having three binary control inputs. A, B, and C, and an inhibit
input. The three binary signals select 1 of 8 channels to be
turned "ON" and connect the input to the output.
CD4052BM/CD4052BC is a differential 4-channel multiplexer having two binary control inputs, A and B, and an inhibit
input. The two binary input signals select 1 or 4 pairs of
channels to be turned on and connect the differential analog inputs to the differential outputs.
CD4053BM/CD4053BC is a triple 2-channel multiplexer
having three separate digital control inputs, A, B, and C, and
Connection Diagrams
an inhibit input. Each control input selects one of a pair of
channels which are connected in a single-pole double-throw
configuration.
Features
• Wide range of digital and analog signal levels: digital
3-15V, analog to 15Vp.p
• Low "ON" resistance: 800 (typ.) over entire 15Vp_p signal-input range for VOO-VEE=15V
• High "OFF" resistance: channel leakage of ± 10 pA
(typ.) at VOO-VEE= 10V
• Logic level conversion for digital addressing signals of
3-15V (Voo-Vss=3-15V) to switch analog signals to
15 Vp_p (VOO-VEE= 15V)
• Matched switch characteristics: ARON = 50 (typ.) for
VOO-VEE= 15V
• Very low quiescent power dissipation under all digitalcontrol input and supply conditions: 1 p.W (typ.) at
Voo-Vss=VOO-VEE= 10V
• Binary address decoding on chip
Dual-In-Line Packages
CD4052BM/CD4052BC
CD4051 BM/CD4051BC
CD4053BM/CD4053BC
IN/OUT
~N/OU~
OUT/IN
:N/OU;
INH
TOP VIEW
Cavity Dual-In-Line Package (J)
Order Number CD4051BMJ,
CD4051 BCJ, CD4052BMJ,
CD4052BCJ, CD4053BMJ, or
CD4053BCJ
See NS Package Number J16A
Oy
2v
v
3v
Iv
INiiiiiT OUT/IN INiOiiT
INH
TOP VIEW
Small Outline Package (M)
Order Number CD4051 BCM,
CD4052BCM or CD4053BCM
See NS Package Number M16A
2-32
TOP VIEW
TL/F/5662-1
Molded Dual-In-Llne Package (N)
Order Number CD4051BMN,
CD4051 BCN, CD4052BMN,
CD4052BCN, CD4053BMN, or
CD4053BCN
See NS Package Number N16E
o
c
Recommended Operating Conditions c
+5 Vdc to + 15 Vdc
U1
Voo DC Supply Voltage
.....
OVto Voo Vdc
VIN Input Voltage
m
Operating Temperature Range
Absolute Maximum Ratings
~
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(Note 4)
-0.5 Vdc to + 18 Vdc
Voo DC Supply Voltage
-0.5 Vdc to Voo+0.5 Vdc
VIN Input Voltage
-65·Cto + 150·C
Storage Temperature Range
Ts
Package Dissipation
500mW
Po
260·C
Lead Temperature (soldering, 10 seconds)
TL
DC Electrical Characteristics
Symbol
Parameter
TA
4051BM/4052BMl4053BM
4051 BC/4052BC/4053BC
~
.....
m
o
.....
o
c
(Note 2)
-55·C
Conditions
Quiescent Device Current Voo=5V
Voo=10V
Voo=15V
ARON
"ON" Resistance (Peak
forVEE:5:VIS:5:Voo)
A"ON" Resistance
Between Any Two
Channels
RL=10kO
(any channel
selected)
RL =10kO
(any channel
selected)
Max
+25·
Min
Typ
+ 125·C
Max
5
10
20
5
10
20
Min
~
Units
c
",A
",A
",A
3:
.....
Max
150
300
600
o
c
8U1
270
1050
1300
0
o
......
Voo=5V
VEE=-5V
orVoo=10V,
VEE=OV
310
120
400
550
0
U1
Voo=7.5V,
VEE=-7.5V
orVoo=15V,
VEE=OV
200
N
80
240
320
0
U1
10
0
Voo=7.5V,
VEE=-7.5V
orVoo=15V,
VEE=OV
5
0
±50
±0.01
±50
±500
nA
±200
±0.08
±200
±2000
nA
±2000
nA
CD4052
±200
±0.04
±200
CD4053
±200
±0.02
±200
±2000
nA
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
VEE=VssRL=1 kOtoVss
liS < 2 ",A on all OFF channels
VIS = Voo thru 1 kO
Voo=5V
Voo=10V
Voo=15V
High Level Input Voltage
operation.
Note 2: All voltages measured with respect to Vss unless otherwise specified.
2-33
~
c
Voo=5V,
VEE=-5V
orVoo=10V,
VEE=OV
CD4051
o
c
(0)
0
Inhibit=7.5V
Voo=7.5V,
VEE=-7.5V,
O/I=OV,
1/0= ±7.5V
(0)
m
10
"OFF" Channel Leakage
Current, all channels
"OFF" (Common
OUT/IN)
c
3:
.....
Voo=2.5V,
VEE= -2.5V
orVoo=5V,
VEE=OV
VEE= -7.5V
Voo=7.5V,
0/1= ±7.5V, I/O=OV
m
o
c
~
1.5
3.0
4.0
3.5
3.5
3.5
V
Voo=5
7
7
V
7
Voo=10
11
11
V
11
Voo=15
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be opemted at these limits. The table of "Electrical Characteristics" provides conditions for actual device
VIH
m
800
"OFF" Channel Leakage
Current, any channel
"OFF"
Low Level Input Voltage
U1
N
Voo=2.5V,
VEE=-2.5V
orVoo=5V,
VEE=OV
Control Inputs A, B, C and Inhibit
VIL
o
c
U1
Signal Inputs (VIS) and Outputs (VOS)
RON
3:
.....
c
Min
100
-55·C to + 125·C
- 40·C to + 85·C
m
o
DC Electrical Characteristics
Symbol
Parameter
(Note 2) (Continued)
-40·C
Conditions
Min
liN
100
Input Current
Quiescent Device Current
Voo=15V,
VIN=OV
Voo=15V,
VIN=15V
VEE=OV
VEE=OV
+2S·C
Max
-0.1
-10- 5
-0.1
0.1
10- 5
Min
20
40
80
Voo=5V
Voo=10V
Voo=15V
+85"C
Typ
Max
Min
Units
Max
-1.0
p.A
0.1
1.0
p.A
20
40
80
150
300
600
p.A
p.A
p.A
Signal Inputs (VIS) and Outputs (VOS)
RON
aRON
"ON" Resistance (Peak
for VEE:S:VIS:S:VOO)
a"ON" Resistance
Between Any Two
Channels
RL =10 kn
(any channel
selected)
RL =10 kn
(any channel
selected)
Voo=2.SV,
VEE= -2.5V
orVoo=5V,
VEE=OV
850
270
1050
1200
n
Voo=5V,
VEE=-5V
or Voo= 10V,
VEE=OV
330
120
400
520
n
Voo=7.5V,
VEE= -7.5V
orVoo=15V,
VEE=OV
210
80
240
300
n
Voo=2.5V,
VEE= -2.5V
or Voo= 5V,
VEE=OV
10
n
Voo=5V
VEE= -5V
or Voo= 10V,
VEE=OV
10
n
Voo=7.5V,
VEE= -7.5V
orVoo=15V,
VEE=OV
5
n
"OFF" Channel Leakage
Voo=7.5V,
VEE= -7.5V
Current, any channel "OFF" 0/1= ±7.5V, I/O=OV
"OFF" Channel Leakage
Current, all channels
"OFF" (Common
OUT/IN)
Inhibit = 7.5V
Voo=7.5V,
VEE= -7.5V,
O/I=OV
1/0= ±7.5V
±50
±0.01
±50
±500
nA
CD4051
±200
±0.08
±200
±2000
nA
CD4052
±200
±0.04
±200
±2000
nA
CD4053
±200
±0.02
±200
±2000
nA
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
Control Inputs A, B, C and Inhibit
VIL
VIH
Low Level Input Voltage
High Level Input Voltage
VEE=VSS RL = 1 kn to VSS
liS < 2 p.A on all OFF Channels
VIS=VOO thru 1 kn
Voo=5V
Voo=10V
Voo=15V
1.5
3.0
4.0
3.5
7
11
Voo=5
Voo=10
Voo=15
3.5
7
11
3.5
7
11
V
V
V
-0.1
Voo=15V,
VEE=OV
-10- 5
-1.0
-0.1
p.A
VIN=OV
Voo=15V,
VEE=OV
10-5
0.1
0.1
1.0
p.A
VIN=15V
Nole I: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to Imply that the devices should be operated at these limits. The tsble of "Electrical Characteristics" provides conditions for actual device
liN
Input Current
operation.
Note 2: All voltages measured with respect to Vss unless otherwise specified.
2-34
AC Electrical Characteristics
~
TA=25'C, tr =tf=20 ns, unless otherwise specified.
UI
Symbol
Parameter
Q
Typ
Max
Units
Propagation Delay Time from
Inhibit to Signal Output
(channel turning on)
VEE=VSS=OV
RL =1 k!l
CL =50pF
5V
10V
15V
600
225
160
1200
450
320
ns
ns
ns
tpHz
tpLZ
Propagation Delay Time from
Inhibit to Signal Output
(channel turning off)
VEE=VSS=OV
RL =1 k!l
CL =50pF
5V
10V
15V
210
100
75
420
200
150
ns
ns
ns
CIN
Input Capacitance
Control input
Signal Input (IN/OUT)
5
10
7.5
15
pF
pF
tPZH
tpZL
COUT
...m
Conditions
Vpp
Min
.....
==
o
c
.j:o,
...m
Q
UI
~c
.j:o,
Q
Output Capacitance
(common OUTIIN)
UI
I\)
m
==
.....
o
c
.j:o,
CD4051
CD4052
CD4053
CIOS
Feedthrough Capacitance
CPD
Power Dissipation Capacitance
10V
10V
10V
VEE=VSS=OV
CD4051
CD4052
CD4053
30
15
8
pF
pF
pF
0.2
pF
110
140
70
pF
pF
pF
Q
~
m
Q
o
~
Q
UI
Co)
m
.....
==
o
c
Signal Inputs (VIS) and Outputs (Vos)
.j:o,
tpHL
tpLH
~
Sine Wave Response
(Distortion)
RL =10 k!l
f1S=1 kHz
VIS=5Vp_p
VEE=VSI=OV
10V
0.04
%
Frequency Response, Channel
"ON" (Sine Wave Input)
RL =1 k!l, VEE=OV, VIS=5Vp_p,
20 IOg10 VosIVIS= -3 dB
10V
40
MHz
Feedthrough, Channel "OFF"
RL =1 k!l, VEE=VSS=OV, VIS=5Vp_p,
20 log10 VosIVIS= -40 dB
10V
10
MHz
Crosstalk Between Any Two
Channels (frequency at 40 dB)
RL =1 k!l, VEE=VSS=OV, VIS(A)= 5Vp_p
20 10glO Vos(B)lVls(A) = -40 dB (Note 3)
10V
3
MHz
Propagation Delay Signal
Input to Signal Output
VEE=VSS=OV
CL=50pF
5V
10V
15V
25
15
10
10V
65
5V
10V
15V
500
180
120
Co)
55
35
25
ns
ns
ns
Control Inputs, A, B, C and Inhibit
tpHL,
tpLH
Control Input to Signal
Crosstalk
VEE=VSS=OV, RL = 10 k!l at both ends
of channel.
Input Square Wave Amplitude = 10V
Propagation Delay Time from
Address to Signal Output
(channels "ON" or "OFF")
VEE=VSS=OV
CL =50pF
Note 3: A, B are two arbitrary channels with A turned "ON" and B "OFF".
Note 4: Refer to RETS4051 BX, RETS4052BX, RETS4053BX for military specifications.
2-35
mV(peak)
1000
360
240
ns
ns
ns
m
o
Block Diagrams
CD4051 BM/CD4051BC
CHANNE ~ IN/OUT
VDD
12
A
15
11
10
COMMON
OUTIIN
BINARY
TO
LOGIC
LEVEL
CONVERSION
1 OF B
DECODER
WITH
INHIBIT
INH
Vss
CD4052BM/CD4052BC
.
X CHANNELS IN/OUT
i
3
1
11
°
15
VDD
COMMON X
OUT/IN
A
LOGIC
LEVEL
CONVERSION
INH
COMMON Y
OUT/IN
10
BINARY
TO
1 OF 4
DECODER
WITH
INHIBIT
VEE
Y CHANNELS IN/OUT
TL/F/5662-2
2-36
.-----------------------------------------------------------------------,0
c
Block Diagrams (Continued)
....""0:1
o
CD4053BM/CD4053BC
CI1
3:
......
IN/OUT
VDD
cv
ex
by
o
c
bx
""o....
0:1
CI1
A
iilX
BINARY TO
1 OF 2
DECODER
WITH INHIBIT
11
o
......
o
c
----10
OR ay
15
LOGIC
LEVEL
CONVERSION
OUT/IN
bx OR by
""o
CI1
N
0:1
3:
......
o
c
----ex OR cy
""o~
0:1
o
......
INH
o
c
""ow
CI1
VEE
Vss
0:1
TLiF/5662-3
3:
......
o
c
""ow
CI1
0:1
o
Truth Table
"ON" CHANNELS
INPUT STATES
INHIBIT
C
B
A
CD4051B
CD4052B
CD4053B
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
OX,OY
1X,1Y
2X,2Y
3X,3Y
1
1
1
1
0
0
cX,bx,ax
cX,bx,ay
cX,by,ax
cX,by,ay
cy,bx,ax
cy,bx,ay
cY,by,ax
cy, by, ay
NONE
NONE
1
1
1
1
1
2
3
0
4
1
0
1
5
6
7
...
NONE
'Don't Care condition.
2-37
o
III
C")
It)
Switching Time Waveforms
o
'0:1'
Q
Voo
o
.....
::::E
III
C")
It)
If
o
ADDRESS
INPUTS
A,B or C VOO
'0:1'
Q
~
oIII
C'I
1----
It)
Voo
'0:1'
Q
VOS
o
~
I
o
.....
I
::::E
I
I
C'I
I
III
Voo
I
I
SIGNAL INPUTTO SIGNAL OUTPUT
It)
o
I
VOS
'0:1'
Q
I
I
o.....
I
ADDRESS TO SIGNAL OUTPUT
o
....
III
It)
o
~
~
::::E
....
III
Voo
It)
o
'0:1'
Q
o
IN/OUT or
OUTJlN
ANY CHANNEL
Voo
VOO
90%
lK.I1
0
IN/OUT or
OUT/IN
OUT/IN or
IN/OUT
r
IpZL
-.
VOO
50PF
Vas
a
TL/F/5662-4
2-38
o
c
Special Considerations
~
In certain applications the externalload·resistor current may
include both Voo and signal·line components. To avoid
drawing Voo current when switch current flows into IN/OUT
pin, the voltage drop across the bidirectional switch must
not exceed O.6V at TA';; 25°C, or O.4V at TA>25°C (calcu·
lated from RON values shown). No Voo current will flow
through RL if the switch current flows into OUT/IN pin.
o
U\
-'"
ID
3:
......
o
c
~
o
U\
-'"
Typical Performance Characteristics
ID
"ON" Resistance vs Signal
Voltage for T A = 2SoC
S
-
IIIIII
400
i'"
2So
111111
tU JEEI"lsJ~H++H
200
1++t+I+¥t-HI\t-+++t-i
z
1
~
I+-H-HI++-++I+H-HH
3So
~
150
~
'DO
'00 1--t~+J::I-++-4-jo<:j::+++H
50
t+i-ti-++++-H9
I J..I.J+t-i
l l'T'l"
oj
~
~
0 L..L..L.J...J...l....I.."-1...JV_DDL..-L..V
...., ....
, ".J.'..JSV...J
5
~
I+~=F~++~~~~~I~~
6
c
In
~ ,SO I-++t+t+t+v~.~o~
4
ID
3:
......
o
:i 2S0 I+-H-HI++++I+++-HH
200
2
U\
N
~ 300 1++-t-HH--t++I+t+-H-l
~
-8·6-4-20
c
o
40D """"""'"T""1-'-TT""r-T""rr"T""1n
H--H++++-++I++-+-HH
3So
~30o
o
......
o
"ON" Resistance as a
Function of Temperature for
VOO-VEE= 1SV
~
50
TA"+~
0
TA=-55~C
·8
8
o
~
T... =~
SIGNAL VOLTAGE (Vos) (V)
-6 -4 -2
ID
o
........
o
0
2
4
6
c
8
~
o
SIGNAL VOLTAGE (VIS) tV)
U\
Co)
"ON" Resistance as a
Function of Temperature for
VOO-VEE= 10V
£;
400 rT-T-r,...n-TT"T""1r-T""rr,....,..,
1
350
400
1
1-++t+H-t++lI+t++t-l
!:
~
=
150
1++t+I+t++lI+t++t-l
1++t+H-t+-HH::;;Id+t-l
H-T+
•.-t
.•-j'2:o5j;o·C+-+......9-t++-t-H
~
'00
-(i rn
~
50
~ 20a
k:
t;
~
o
c
.-T-T,...,..,:.:::;......"T"T"T.,...,..,
11""T1""n
1
~
o
3S0 1++t+r+t+-¥I'-Tl-.+.+"-+2S-l"C-l
U\
Co)
ID
o
TA " +2S"C
200 I-++t+t-'l--ft~~t++t.,
'"
~+t+~~+~,lT·I=~L55..lc
~'50'I·IITi
T~.~C
f'
3:
........
; : : ~:1~=~~~~~~iII:~:I::I:I:I~
JOO
250
ID
"ON" Resistance as a
Function of Temperature for
VOO-VEE=SV
~ 'DO
~
0L...L.L.l...L.J..J...JL.l...L..L.L.l..J...J..J...J
·8 ·6 --4 -2 0
2 4 6 8
SO
H-+-+-H-II+H-++I-HIH-I-HI
I III
OL...L.L.l...J..JL.l...LLL..L..L.J..J...J...J...J
·8 ·6 ·4 -2 D 2 4 6 8
SUPPLY VDLTAGE (V's) (V)
S'GNAL VOLTAGE (Vos) (V)
TLlF/5662-5
2·39
o
m
CD
CD
Q
~
C
o
......
NatiOnal
~ Semiconductor
Corporation
:t
m CD4066BM/CD4066BC Quad Bilateral Switch
CD
CD
Q
~
C
o
General Description
• Extremely low "OFF"
0.1 nA (typ.)
@ VDD-Vss=10V, TA=25°C
switch leakage
10120(typ.)
• Extremely high control input impedance
.
-50 dB (typ.)
• Low crosstalk
@ fis = 0.9 MHz, RL = 1 kO
between switches
• Frequency response, switch "ON"
40 MHz (typ.)
The CD4066BM/CD4066BC is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with CD4016BM/
CD4016BC, but has a much lower "ON" resistance, and
"ON" resistance is relatively constant over the input-signal
range.
Features
Applications
3V to 15V
• Wide supply voltage range
0.45 VDD (typ.)
• High noise immunity
• Wide range of digital and
±7.5 VPEAK
analog switching
BOO
• "ON" resistance for 15V operation
aRON=50 (typ.)
• Matched "ON" resistance
over 15V signal input
• "ON" resistance flat over peak-to-peak signal range
• High "ON"/"OFF"
65 dB (typ.)
@ fis = 10kHz, RL = 10 kO
output voltage ratio
• High degree linearity
0.1 % distortion (typ.)
High degree linearity
@ fis=1 kHz, Vis=5V p_p,
High degree linearity
VDD-Vss=10V, RL =10 kO
• Analog signal switching/multiplexing
• Signal gating
• Squelch control
• Chopper
• Modulator/Demodulator
• Commutating switch
• Digital signal switching/multiplexing
• CMOS logic implementation
• Analog-to-digital/digital-to-analog conversion
• Digital control of frequency, impedance, phase, and analog-signal-gain
Schematic and Connection Diagrams
IN/OUT
CONTROL
Dual-In-Llne Package
Cavity Dual-In-Line Package (J)
Order Number CD4066BMJ or
CD4066BCJ
See NS Package Number J14A
IN/OUT
vD.
OUlIIN
CONTROL A
OUT/IN
12 CONTROL D
IN/OUT
Molded Dual-In-Llne Package (N)
Order Number CD4066BMN or
CD4066BCN
See NS Package Number N14A
Small Outline Package (M)
Order Number CD4066BCM
See NS Package Number M14A
CONTROL B
CONTROL C
DUTflN
Vss
INfOUT
TLlF/5665-1
Top View
2-40
n
Absolute Maximum Ratings
(Notes 1 and 2)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(Note 7)
Voo Supply Voltage
VIN Input Voltage
-0.5V to + 1BV
-0.5V to Voo+0.5V
- 65·C to + 150·C
Ts Storage Temperature Range
Po Package Dissipation
T L Lead Temperature (Soldering. 10 seconds)
DC Electrical Characteristics
Symbol
Parameter
Quiescent Device Current
8en
en
3V to 15V
VIN Input Voltage
TA Operating Temperature Range
CD4066BM
CD4066BC
OVtoVoo
......
==
n
-55·C to + 125·C
-40·Cto +B5·C
8en
c
ARON
"ON" Resistance
A"ON" Resistance
Between any 2 of
4 Switches
liS
Input or Output Leakage
Switch "OFF"
500mW
300·C
CD4066BM (Note 2)
-55·C
Conditions
125·C
25·C
Max
Min
Typ
Max
Min
Units
Max
Voo=5V
Voo=10V
Voo=15V
0.25
0.5
1.0
0.01
0.01
0.01
0.25
0.5
1.0
7.5
15
30
".A
".A
p.A
RL =10knto Voo-VSS
2
Ve=Voo. VIS = VSS to Voo
Voo=5V
Voo=10V
Voo=15V
BOO
310
200
270
120
BO
1050
400
240
1300
550
320
n
n
n
RL = 10 kn to Voo VSS
2
Ve=Voo. VIS=VSS to Voo
Voo=10V
Voo=15V
10
5
Ve=O
Vls=15V and OV.
Vos=OVand 15V
n
n
±50
±0.1
±50
±500
nA
1.5
3.0
4.0
2.25
4.5
6.75
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
Control Inputs
VILe
Low Level Input Voltage
VIS = VSS and Voo
VOS = Voo and Vss
Ils= ±10".A
Voo=5V
Voo=10V
Voo=15V
VI He
High Level Input Voltage
Voo=5V
Voo= 10V (see note 6)
Voo=15V
liN
Input Current
Voo-Vss=15V
3.5
7.0
11.0
3.5
7.0
11.0
±0.1
3.5
7.0
11.0
2.75
5.5
8.25
±10- 5
V
V
V
±0.1
±1.0
".A
VOO~VIS~VSS
Voo~Ve~Vss
DC Electrical Characteristics CD4066BC (Note 2)
Symbol
Parameter
Conditions
-40·C
Min
100
Quiescent Device Current
en
m
n
Signal Inputs and Outputs
RON
m
Voo Supply Voltage
Min
100
c
Recommended Operating
Conditions (Note 2)
Max
1.0
2.0
4.0
Voo=5V
Voo=10V
Voo=15V
2-41
25·C
Min
85·C
Typ
Max
0.Q1
0.01
0.01
1.0
2.0
4.0
Min
Units
Max
7.5
15
30
".A
".A
".A
DC Electrical Characteristics
Symbol
Parameter
(Continued) CD4066BC (Note 2)
-40·C
Conditions
Min
Max
2S·C
Min
8S·C
Typ
Max
270
120
80
1050
400
240
Min
Units
Max
Signal Inputs and Outputs
RON
aRON
"ON" Resistance
a "ON" Resistance
Between Any 2 of
4 Switches
liS
Input or Output Leakage
Switch "OFF"
RL =10 kO to Voo-VSS
2
Vc=Voo. Vss to Voo
Voo=5V
Voo=10V
Voo=15V
850
330
210
RL =10kOto Voo-Vss
2
VCc=Voo. VIS=VSStoVoo
Voo=10V
Voo=15V
1200
520
300
0
0
n
0
10
5
n
Vc=O
±50
±0.1
±50
±200
nA
VIS=VSS and Voo
Vos = Voo and Vss
Ils= ±10p.A
Voo=5V
Voo=10V
Voo=15V
1.5
3.0
4.0
2.25
4.5
6.75
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
Control Inputs
VILC
Low Level Input Voltage
VIHC
High Level Input Voltage
Voo=5V
Voo = 10V (See note 6)
Voo=15V
liN
Input Current
Voo-Vss= 15V
VOO:2:VIS:2:VSS
Voo:2:Vc:2:Vss
3.5
7.0
11.0
3.5
7.0
11.0
±0.3
2.75
5.5
8.25
3.5
7.0
11.0
±10- 5
±0.3
V
V
V
±1.0
p.A
AC Electrical Characteristics TA = 25·C. t,=t,=20 ns and Vss= OV unless otherwise specified
Symbol
Parameter
tpHL. tpLH
Propagation Delay Time Signal
Input to Signal Output
tPZH. tPZL
tpHZ. tpLZ
Conditions
Vc=Voo. CL =50 pF. (Figure 1)
RL =200k
Voo=5V
Voo=10V
Voo=15V
Propagation Delay Time
Control Input to Signal
Output High Impedance to
Logical Level
RL = 1.0 kn. CL = 50 pF. (Figures 2 and 3)
Voo=5V
Voo=10V
Voo=15V
Propagation Delay Time
Control Input to Signal
Output Logical Level to
High Impedance
Sine Wave Distortion
RL = 1.0 kn. CL = 50 pF. (Figures 2 and 3)
Voo=5V
Voo=10V
Voo=15V
Vc=Voo=5V. Vss= -5V
RL = 10 kO. Vls=5Vp_p• f= 1 kHz.
{Figure 4)
Vc=Voo=5V. Vss= -5V.
RL = 1 kO. VIS=5Vp_p•
20 Logl0 VoslVos (1 kHz)-dB.
(Figure 4)
Frequency Response-Switch
"ON" (Frequency at -3 dB)
2-42
Min
Typ
Max
Units
25
15
10
55
35
25
ns
ns
ns
125
60
50
ns
ns
ns
125
60
50
0.1
ns
ns
ns
%
40
MHz
AC Electrical Characteristics (Continued) TA = 25'C, tr= tf= 20 ns and VSS = OV unless otherwise noted
Symbol
Parameter
Conditions
Feedthrough - Switch "OFF"
(Frequency at -50 dB)
Min
Crosstalk; Control Input to
Signal Output
Maximum Control Input
Units
1.25
Voo=5.0V, Vcc=VSS= -5.0V,
RL = 1 k!1, VIS=5.0Vp_p, 20 Loglo,
VosIVIS = - 50 dB, (Figure 4)
VOO=VC(A)=5.0V; VSS=VC(8)=5.0V,
RL 1 k!1, VIS(A) = 5.0 Vp_p, 20 Loglo,
VOS(8)IVIS(A)= -50 dB (Figure 5)
Voo=10V, RL =10 k!1, RIN=1.0 k!1,
VCC= 10V Square Wave, CL =50 pF
(Figure 6)
RL = 1.0 k!1, CL = 50 pF, (Figure 7)
VOS(f) = % Vos(1.0 kHz)
Voo=5.0V
Voo=10V
Voo=15V
Crosstalk Between Any Two
Switches (Frequency at - 50 dB)
Max
Typ
0.9
MHz
150
mVp_p
6.0
8.0
8.5
MHz
MHz
MHz
8.0
pF
CIS
Signal Input Capacitance
Cos
Signal Output Capacitance
Voo=10V
8.0
pF
CI05
Feedthrough Capacitance
Vc=OV
0.5
pF
Control Input Capacitance
5.0
7.5
pF
CIN
Note I: "Absolute Maximum Ratings" are those values beyond which tha safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of "Recommended Operating Conditions" and "Electrical Characteristics" provide conditions for actual device
operation.
Note 2: Vss=OV unless otherwise specified.
Note 3: These devices should not be connected to circuits with the power "ON" .
Note 4: In all cases, there Is approximately 5 pF of probe and jig capacitance In the output; however. this capacitance is included in CL wherever it is specified.
Note 5: VIS is the voltage at the inlout pin and Vas is the voltage at the oullin pin. Vc is the voltage at the control input.
Note 6: Conditions for VIHC: aJ VIS=VDD. los=standard 8 sarias IOH
b) VIS = OV. IOL = standard 8 serias IOL.
Note 7: Refer to RETS4066BX for military specifications.
AC Test Circuits and Switching Time Waveforms
we.voD
I
T..I
CONTROL
VIS
Voo
Voo
r
IDf4
INIOUT ..,,"" OUT.' 1
VIS
-1-
J
-
ov
Vos
A,
ft .,
.".
Vo, Yao
~
C
~
511'\
'"
-'PL'
-J
/Sa"l.
av
FIGURE 1. tpHL. tpLH Propagation Delay Time Signal Input to Signal Output
tpZH
TL
v'l
CONTROL
VIS'YOD
I
Voo
IOF4
r
IN OUT sw",""
..
-1- ,
OU""I
J~"
vo.
R,
"
voa~
...
VOO~v ..
av~
Vo.
,
av
.
Vo.
.v~
...
ov
.".
FIGURE 2. tPZH. tpHZ Propagation Delay Time Control to Signal Output
tpzL
v,
I
caN,.O'
VIS'OV
INlaUT
Vao
':1:~H4ES
Vos
.".
T
~
tpLZ
Voo
tPlL
R,
Nr-:"
OUTIIN
..
tpHZ
~VDS
_'-.,
Jso"
I'll
voa~
s..
.v~
Vao
1ft
...
v"1s:-
v~
•
Vao
VOL
vo'
FIGURE 3. tpZLo tpLZ Propagtlon Delay Time Control to Signal Output
2-43
'"
'
TLlF/5665-2
o
m
CD
§
C
....:::i!io
AC Test Circuits and Switching Time Waveforms (Continued)
VC---'
m
CD
..
v,s
CD
Q
'N/OUT ~'~~:ES
OUT/lNI---4~-VOS
Vss
C
o
VC=VOD for distortion and frequency response tests
-SV
VC~VSS
for feedlhrough lesl
FIGURE 4. Sine Wave Distortion, Frequency Response and Feedthrough
VCIII' Voo - - - ,
V'SIII
'N/OUT ~'~~H4ES OUT/lNI-~~-VOS(1)
Vss
-SV
VC(Z)"
vSS-----.
V'SIZ)" DV
'NIOUT ~'~~:ES
OUT1'NI---4~- VOS(2)
Vss
-SV
FIGURE 5. Crosstalk Between Any Two Switches
yc----,
_I-I-""""*[".,-_J....,l
Voo _,,_.z_a..
Vc
'N/OUT ':'~::ES
K
av ____...
l a.,
r '"
"'L
2a no
OUTn"I-~~---"'-- VoS
Vss
Vos
FIGURE 6. Crosstalk: Control Input to Signal Output
Vc
V,S'Voo
v,
'NIOUT n:,~~:ES
'aa
'v
ouml--4~--"' vos
Vss
CL
I
RL
Il
SQPF
':"
v.
1
vose
--,I 11Hz
T
TLlF/5665-3
FIGURE 7. Maximum Control Input Frequency
2-44
o
c
Typical Performance Characteristics
~
"ON" Resistance as a Function
of Temperature for
Voo-Vss= 1SV
"ON" Resistance vs Signal
Voltage for T A = 25°C
aZ 350
..
.'"
400
5 300
~
E
IIIIIII
IIIIIII
~ 350
u
In
..
250
fii
200
i.
l'
150
400 rT-'-""-'-'-TT"T1-'--TT"-'-'
~
lOD
~
250
~
O~~~~~~~~-U
III
--
150
TA" +IZ5°C
TA'" +25°C
0
-8
-8-6-4-202468
SIGNAL VOLTAGE IVlsllVI
400
E
350
~ 350
;
300
~
250
:a~
z
250
.
20D
~
150
~
100
~
50
'"
~
zoo
~
150
..
TA' +125'C
l'
.... 100
""
~
50
o
-ir~
TA"-55"C
-8-6-4-20
-6 -4 -2
0
2
4
6
8
400
.11111
TA"'+125~C
300
~
6
,~_I.IJ5'~
11 I I I
IIIII
IIIII
-8-6-4-20
8
SIGNAL VOLTAGE (V,sIIVI
IIIII
TA;; +Z5'C
o
2
4
"ON" Resistance as a Function
of Temperature for
Voo-Vss=SV
'"~
"
TA" _55°C
SIGNAL VOLTAGE IVlsllVI
"ON" Resistance as a Function
of Temperature for
Voo-Vss= 10V
2
4
6
8
SUPPLY VOLTAGE IVlsllVI
TLlF/5665-4
Special Considerations
drawing Voo current when switch current flows into terminals 1, 4, 8 or 11, the voltage drop across the bidirectional
switch must not exceed O.6V at TA";25°C, or O.4V at
TA>25°C (calculated from RON values shown).
No Voo current will flow through RL if the switch current
flows into terminals 2, 3, 9 or 10.
In applications where separate power sources are used to
drive Voo and the signal input, the Voo current capability
should exceed Voo/RL (RL = effective external load of the 4
CD4066BM/CD4066BC bilateral switches). This provision
avoids any permanent current flow or clamp action of the
Voo supply when power is applied or removed from
CD4066BM/CD4066BC.
In certain applications, the external load-resistor current
may include both Voo and signal-line components. To avoid
2-45
o
c
o
200
50
VOO - VSS" 15V
s:
~
100
50
III
.......
o
en
en
I-+-H-H-I-H-HH-H-HH
z
~
o
en
en
o
ED
re ~ Semiconductor
Corporation
NatiOnal
II)
"O:t'
C
o
......
:::E
ED
CJ)
N
II)
"O:t'
CD4529BM/CD4529BC Dual 4-Channel or Single
a-Channel Analog Data Selector
C
o
General Description
Features
The CD45298 is a dual 4-channel or a single 8-channel
analog data selector, implemented with complementary
MOS (CMOS) circuits constructed with N- and P-channel
enhancement mode transistors. Dual 4-channel or 8-channel mode operation is selected by proper input coding, with
outputs Z and W tied together lor the single 8-bit mode. The
device is suitable lor digital as well as analog applications,
including various 1-01-4 and 1-01-8 data selector lunctions.
Since the device is analog and bidirectional, it can also be
used lor dual binary to 1-01-4 or single 1-01-8 decoder applications.
3.0V to 15V
• Wide supply voltage range
0.45 Voo (typ.)
• High noise immunity
0.005/lW/package
• Low quiescent
(typ.) @ 5.0 Voc
power dissipation
• 10 MHz Irequency operation (typ.)
• Data paths are bidirectional
• Linear ON resistance [120n (typ.) @ 15V]
• TRI-STATE® outputs (high impedance disable strobe)
• Plug-in replacement lor MC145298
Connection Diagram
Logic, Diagram
Dual-In-Line Package
X,
I
l
ITx
XI
XI
X.
Xl
VIS
XI
lOP VIEW
Order Number CD4529BCJ, N or CD4529BMJ, W
See NS Package J16A, N16E, or W16A
XI
•
Xl
•
Truth Table
STx STy B A
0
0
0
0
0
0
0
0
0
0
0
X
~
0
0
1
0
Z
W
XO
X1
X2
X3
YO
Y1
Y2
Y3
0 0
0
0
1
XO
X1
X2
X3
0
0
YO
Y1
Y2
Y3
0
1
0
X X
Dual
4-Channel
Mode
2 Outputs
}
Single
8-Channel Mode
1 Output
(ZandW
tied together)
14
YO
.,
yz
11
11
11
Y3
High
Impedance
(TRI-STATE)
Tl/F/5999-1
Don'l care
2-46
o
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(Notes 1 and 2)
VDD DC Supply Voltage
VDD DC Supply Voltage
T A Operating Temperature Range
CD4529BM
VIN Input Voltage
Ts Storage Temperature Range
CI1
I\)
CD
3Vto 15V
m
OtoVDD
........
-55·C to + 125·C
....c
-40·Cto +85·C
CD
VIN Input Voltage
-0.5Vto +18V
-0.5VtoVDD +0.5V
- 65·C to + 150·C
PD Package Dissipation
....c
Recommended Operating
Conditions (Note 2)
CD4529BC
500mW
T L Lead Temp. (Soldering, 10 seconds)
260·C
DC Electrical Characteristics CD4529BM (Note 2)
Symbol
Parameter
-55·C
Conditions
Min
IDD
Quiescent Device
Current
VDD = 5V
VDD = 10V
VDD = 15V
VOL
Low Level Output
Voltage
VIL = OV, VIH = VDD, 1101
VDD = 5V
VDD = 10V
VDD = 15V
< 1 )LA
High Level Output
Voltage
VIL = OV, VIH = VDD, 1101
VDD = 5V
VDD = 10V
VDD = 15V
< 1 )LA
VOH
VIL
Low Level Input Voltage VDD = 5V
(Note 3)
VDD = 10V
VDD = 15V
VIH
High Level Input Voltage VDD = 5V
(Note 3)
VDD = 10V
VDD = 15V
liN
Input Current
RON
10FF
ON Resistance
Max
25·C
1.0
1.0
2.0
0.001
0.002
0.003
1.0
1.0
2.0
60
60
120
)LA
)LA
)LA
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
4.95
9.95
14.95
3.5
7.0
11.0
VDD = 5V, Vss = -5V
VIN = 5V
VIN = -5V
VIN = ±0.25V
VDD = 7.5V, Vss = -7.5V
VIN = 7.5V
VIN = -7.5V
VIN = ±0.25V
VDD = 10V, Vss = OV
VIN = 10V
VIN = 0.25V
VIN = 5.6V
VDD = 15V, Vss = OV
VIN = 15V
VIN = 0.25V
VIN = 9.3V
Input to Output Leakage Vss = -5V, VDD = 5V, VIN = 5V,
Current
VOUT = -5V
Vss = -5V, VDD = 5V, VIN = -5V,
VOUT = 5V
Vss = -7.5V, VDD = 7.5V,
VIN = 7.5V, VOUT = -7.5V
Vss = -7.5V, VDD = 7.5V,
VIN = -7.5V, VOUT = 7.5V
2-47
2.25
4.50
6.75
3.5
7.0
11.0
-0.1
0.1
5.0
10.0
15.0
Min
Units
Max
1.5
3.0
4.0
VDD = 15V
VIN = OV
VIN = 15V
125·C
Typ
4.95
9.95
14.95
Min
Max
4.95
9.95
14.95
1.5
3.0
4.0
2.75
5.50
8.25
V
V
V
1.5
3.0
4.0
3.5
7.0
11.0
-10- 5 -0.1
10-5
0.1
V
V
V
V
V
V
-1.0
1.0
)LA
)LA
400
400
400
165
100
155
480
480
480
640
640
640
.n
.n
.n
240
240
240
135
75
100
270
270
270
400
400
400
.n
.n
.n
400
400
400
165
100
160
480
480
480
640
640
640
.n
.n
.n
250
250
250
135
75
110
270
270
270
400
400
400
.n
.n
.n
±125
±0.001
±125
±1250
nA
±125
±0.001
±125
±1250
nA
±250
±0.0015 ±250
±2500
nA
±250
±0.0015 ±250
±2500
nA
==
o
CI1
I\)
m
o
DC Electrical Characteristics CD4529BC (Note 2) (Continued)
Symbol
Parameter
-40"C
Conditions
Min
100
Quiescent Device Current Voo = 5V
Voo = 10V
Voo = 15V
VOL
Low Level Output Voltage VIL = OV. VIH = Voo.llol
Voo = 5V
Voo = 10V
Voo = 15V
< 1 ,...A
High Level Output Voltage VIL = OV. VIH = Voo.llol
Voo = 5V
Voo = 10V
Voo = 15V
< 1 /LA
VOH
VIL
Low Level Input Voltage
(Note 3)
Voo = 5V
Voo = 10V
Voo = 15V
VIH
High Level Input Voltage
(Note 3)
Voo = 5V
Voo = 10V
Voo = 15V
liN
Input Current
Voo = 15V
VIN = OV
VIN = 15V
RON
IOFF
ON Resistance
Vss =
VIN =
VIN =
Vss =
VIN =
VIN =
Min
5.0
5.0
10.0
4.95
9.95
14.95
4.95
9.95
14.95
1.5
3.0
4.0
-5V. Voo = 5V
5V. VOUT = -5V
-5V. VOUT = 5V
-7.5V. Voo = 7.5V
7.5V. VOUT = -7.5V
-7.5V. VOUT=7.5V
Units
Max
0.001
0.002
0.003
5.0
5.0
10.0
70
70
140
,...A
,...A
,...A
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
5.00
10.00
15.00
2.25
4.50
6.75
3.5
7.0
11.0
3.5
7.0
11.0
85'C
Typ
0.05
0.05
0.05
Voo = 5V. Vss = -5V
VIN = 5V
VIN = -5V
VIN = ±0.25V
Voo = 7.5V. Vss = -7.5V
VIN = 7.5V
VIN = -7.5V
VIN = ±0.25V
Voo = 10V. Vss = OV
VIN = 10V
VIN = 0.25V
VIN = 5.6V
Voo = 15V. Vss = OV
VIN = 15V
VIN = 0.25V
VIN = 9.3V
Input-Output Leakage
Current
Max
25'C
Min
Max
4.95
9.95
14.95
1.5
3.0
4.0
V
V
V
1.5
3.0
4.0
3.5
7.0
11.0
2.75
5.50
8.25
V
V
V
V
V
V
-0.3
0.3
-10- 5
10-5
-0.3
0.3
-1.0
1.0
/LA
,...A
410
410
410
165
100
155
480
480
480
560
560
560
n
n
n
250
250
250
135
75
100
270
270
270
350
350
350
n
n
n
410
410
410
165
. 100
160
480
480
480
560
560
560
n
n
n
250
250
250
135
75
110
270
270
270
350
350
350
n
n
n
±125
±125
±0.001
±0.001
±125
±125
±500
±500
nA
nA
±250
±250
±0.0015 ±250
±0.0015 ±250
±1000
±1000
nA
nA
Nole 1: "Absolute Maximum Ratings" are those values beyond which the safely of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The tables of "Recommended Operating Conditions" and "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Vss = OV unless otherwise specified.
Nole 3: Switch OFF is defined as
1101 ,;:
10 ,.A. switch ON as defined by RON specification.
2-48
AC Characteristics CD4529BM/CD4539BC
TA
=
25°C, RL
=
1 kO, tr
Symbol
tpLH, tpHL
tpLH, tpHL
fMAX
=
tf = 20 ns, unless otherwise specified.
Parameter
VIN to VOUT Propagation Delay
Control to Output Propagation Delay
Maximum Control Input Pulse Frequency
Crosstalk, Control to Output
Noise Voltage
Sine Wave (Distortion)
ILOSS
Insertion Loss,
VOUT
ILOSS = 20 L0910V-IN
BW
Bandwidth, -3dB
Feedthrough and Crosstalk,
VOUT
20 Log10--= -50db
VIN
Conditions
Vss =
Vee =
Vee =
Vee =
Min
OV, CL = 50 pF
5V
10V
15V
VIN = Vee or Vss, CL
VIN s;; 10V
Vee = 5V
Vee = 10V
Vee = 15V
=
Max
Units
20
10
8
40
20
15
ns
ns
ns
200
80
50
400
160
120
ns
ns
ns
50 pF
Vss = OV,CL = 50pF
Vee = 5V
Vee = 10V
Vee = 15V
ROUT = 10 kO, CL = 50 pF, Vss
Vee = 5V
Vee = 10V
Vee = 15V
f = 100Hz, Vss = OV
Vee = 5V
Vee = 10V
Vee = 15V
f = 100 kHz, Vss = OV
Vee = 5V
Vee = 10V
Vee = 15V
VIN = 1.77Vrms Centered
atOV, RL = 10 kO, f = 1 kHz,
Vss = -5V, Vee = 5V
VIN = 177Vrms Centered
atOVdc, Vss = -5V, Veo = 5V
RL = 1 kO
RL = 10kO
RL = 100kO
RL = 1 MO
Vss = -5V, Voo = 5V
RL = 1 kO
RL = 10kO
RL = 100kO
RL = 1 MO
10
12
MHz
MHz
MHz
5.0
5.0
5.0
mV
mV
mV
24
25
30
nV!4cycle
nVl4cycle
nV!4cycle
12
12
15
0.36
nV!4cycle
nVl4cycie
nVNcycie
%
2.0
0.8
0.25
0.01
dB
dB
dB
dB
5
=
0
VIN = 177Vrms Centered
atOV, Vss = -5V, Voo = 5V
RL = 1 kO
RL = 10kO
RL = 100kO
RL = 1 MO
2-49
Typ
35
28
27
26
MHz
MHz
MHz
MHz
850
100
12
1.5
kHz
kHz
kHz
Khz
o
m
en
N
Test Circuits and Switching Time Waveforms
It)
-.:I'
C
o.......
:E
m
en
Output Voltage
UT
N
It)
-.:I'
C
fl'.
RON Characteristics
Vss
'.
o
Noise Voltage
.
-'
VIN
Vss
VOO
OUAN·TECH
MOOEL
2213
OR EOUIV
-
Frequency Response
Crosstalk
VSS
A OR B
VOO
x, V INPUT
lk
Propagation Delay
ru
RL
VSS
Turn-ON Delay Time
..../"\..-.
UT VOO
VIN
_
-
1
CL
STX. STy.
A OR B
-
Vx
VOO
VOO
Vss
Vss
STX. STy
A DR B
VIN
VOUT
YOUT
VIN
II
Voo
Vx '" OVdc
TLiF/5999-2
2-50
o
C
Typical Performance Characteristics
01:>0
U1
J\)
Typical RON vs VIN
250
~,~
225
V;sl.
z
"in
200
175
VOD~5V
z
100
u
~
,
~
z
0
'"
30
125
i i'i
jOt 7
50
IIIII
IIIII
25
a
-0
-6
-4 -2
a
2
4
6
o
C
\
20 1--'0Vd,
01:>0
U1
~
J\)
CD
I'
~
Vss' -7.5V
75
tIl
:s:
.....
v~~I!I!I~ vJ,
~
25
.."
:.
150
0
CD
Typical Noise Characteristics
35
~
>
10
~
5
"
I
a
B
10
VIN - INPUT VOLTAGE rVdcJ
tIl
o
5 Vdc
11
II
100
I
lk
10k
lOOk
1- fREQUENCY (Hz!
Typical Insertion Loss/
Bandwidth Characteristics
2
RL
~'!I~"AN~\'~Ok"
0
-,
I III
Ik!!
-4
l 'Ok " 11
jl~li~~ .1,IM'" ~
~~I
-J dB fRl 1 k!!I
-6
,,,,,,,'
-8
=
""
JlllillilWl
II!IIIIIIIIII
-10
-12
10k
lOOk
1M
10M
100M
'IN -INPUT FREQUENCY (Hz)
TL/F/5999-3
2-51
,.. r--------------------------------------------------------------------------------,
oCN
,..
CO)
II.
~
C\i
o
NatiOnal
~ Semiconductor
Corporation
BI.FET II ™ Technologv
CN
,..
Quad SPST JFET Analog Switches
,..
II.
~
......
,..
o
CN
,..
CO)
LF11331. LF13331 4 Normally Open Switches with Disable
LF11332. LF13332 4 Normally Closed Switches with Disable
LF11333. LF13333 2 Normally Closed Switches and 2 Normally Open Switches with Disable
LF11201. LF13201 4 Normally Closed Switches
LF11202. LF13202 4 Normally Open Switches
~
......
,.. General Description
~
,..
.....
II.
~
......
CO)
CO)
CO)
CO)
.....
II.
~
......
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CO)
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.....
.....
Features
These devices are a monolithic combination of bipolar and
JFET technology producing the industry's first one chip
quad JFET switch. A unique circuit technique is employed to
maintain a constant resistance over the analog voltage
range of ± 1OV. The input is designed to operate from minimum TTL levels, and switch operation also ensures a breakbefore·make action.
These devices operate from ± 15V supplies and swing a
± 1OV analog signal. The JFET switches are designed for
applications where a dc to medium frequency analog signal
needs to be controlled .
II.
~
......
CN
• Analog signals.are not loaded
• Constant "ON" resistance for signals up to ±10V and
100 kHz
• Pin compatible with CMOS switches with the advantage
of blowout free handling
• Small signal analog signals to 50 MHz
• Break-belore-make action
!oFF < !oN
-50 dB
• High open switch isolation at 1.0 MHz
<1.0 nA
• Low leakage in "OFF" state
• TTL, DTL, RTL compatibility
• Single disable pin opens all switches in package on
LFl1331. LFl1332, LF11333
• LFl1201 is pin compatible with DG201
CO)
CO)
CO)
..... Test Circuit and Schematic Diagram
II.
~
......
r-------,
CO)
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Is
CN
.....
.....
II.
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,..
IL
~
~I
I
LOGI;'-o"_...I--I
__ J
INPUT V,N
(LOGIC "0" < O.BV)
(LOGlC"T' > 2.0V)
;.J
......
.....
,..
.....
II.
W
...
_
I
L- - fV!!.. ri ~c':.-
I
I
I.
.J
IEEl_15v leet .,5V
CO)
CO)
TLIH15667-2
FIGURE 1. Typical Clrc,ult for One Switch
~
LOGIC
IN
VRo---~--~----~
.....--_-----0 -v..
FIGURE 2. Schematic Diagram (Normally Open)
2-52
TLIHI5667-12
r......
."
Absolute Maximum Ratings
......
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Officel
Distributors for availability and specifications.
(Note 1)
Supply Voltage (Vee - VEE)
36V
Reference Voltage
VEE,,;VR,,;Vee
Logic Input Voltage
VR-4.0V,,;VIN,,;VR+6.0V
Analog Voltage
500mW
900mW
IIAI<20 mA
-55"Cto + 125"C
O"Cto +70"C
Storage Temperature
-65"C to + 150"C
Parameter
215"C
220"C
LFl1331/2/3
LFl120112
Conditions
"ON" Resistance
RON Match "ON" Resistance Matching
Analog Range
VA
Leakage Current in "ON" Condition
IS(ON) +
10(ON)
VA=O,lo=l mA
LF13201/2
TA=25"C
Switch "ON," Vs=Vo= ± 10V
Switch "OFF," Vs= + 10V,
Vo= -10V
Switch "OFF," Vs= +10V,
Vo= -10V
150 200
150 250
200 300
200 350
5
20
10 50
TA=25"C
±10 ± 11
±10 ±11
0.3 10
TA=25"C
0.3
5
3
30
3 100
IS(OFF)
Source Current in "OFF" Condition
10(OFF)
Drain Current in "OFF" Condition
VINH
VINL
IINH
Logical "1" Input Voltage
Logical "0" Input Voltage
Logical "1" Input Current
VIN=5V
TA=25"C
IINL
Logical "0" Input Current
VIN=O.B
TA=25"C
0.4
3
0.1
3
TA=25"C
TA=25"C
W
W
W
......
.......
r-
5
100
5
100
2.0
0.4
3
0.1
3
10
30
10
30
2.0
O.B
3.6
10
25
0.1
1
O.B
3.6
40
100
0.1
1
......
......
W
W
N
.......
r."
......
W
W
W
LF13331/2/3
N
Units
.......
r-
."
Min Typ Max Min Typ Max
RON
."
."
300"C
Electrical Characteristics (Note 3)
Symbol
......
.......
r-
......
Operating Temperature Range
LFl1201, 2 and LFl1331, 2, 3
LF13201, 2 and LF13331, 2, 3
Soldering Information
Nand 0 Package (10 sec.)
SO Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
VEE,,;VA,,;Vee+ 6V;
VA,,;VEE+36V
Analog Current
W
W
Power Dissipation (Note 2)
Molded DIP (N Suffix)
Cavity DIP (0 Suffix)
n
n
n
......
......
W
W
W
.......
r......
V
nA
nA
."
nA
nA
nA
nA
.......
r."
......
V
V
".A
".A
".A
".A
toN
toFF
toN-tOFF
CS(OFF)
CO(OFF)
CS(ON) +
COrON)
Delay Time "ON"
Delay Time "OFF"
Break·Before·Make
Source Capacitance
Drain Capacitance
Active Source and Drain Capacitance
Vs= ± 10V, (FigureS)
Vs= ± 10V, (FigureS)
Vs= ±10V, (FigureS)
Switch "OFF," Vs= ±10V
Switch "OFF," Vo= ± 10V
Switch "ON," Vs=Vo=OV
TA=25"C
TA=25"C
TA=25"C
TA=25"C
TA=25"C
TA=25"C
500
90
500
90
BO
BO
4.0
3.0
5.0
4.0
3.0
5.0
ISO(OFF)
CT
SR
lOIs
"OFF" Isolation
Crosstalk
Analog Slew Rate
Disable Current
(Rgure 4), (Note 4)
(Figure 4), (Note 4)
TA=25"C
TA=25"C
TA=25"C
TA=25"C
-50
-65
50
0.4 1.0
0.6 1.5
-50
dB
-65
dB
50
V/".s
0.6 1.5 mA
0.9 2.3 mA
lEE
Negative Supply Current
All Switches "OFF," Vs= ±10V TA=25"C
IR
Reference Supply Current
All Switches "OFF," Vs= ± 10V TA=25"C
3.0
4.2
2.0
lee
Positive Supply Current
All Switches "OFF," Vs= ± 10V TA=25"C
4.3 7.0 mA
6.0 10.5 mA
2.7 5.0 mA
3.B 7.5 mA
7.0 9.0 mA
9.B 13.5 mA
ns
ns
ns
pF
pF
pF
W
W
W
W
......
o
......
.......
N
r-
."
......
W
N
o......
.......
r-
."
......
......
N
o
N
.......
r-
."
(Note 5)
(Figure 5), (Note 6)
2.B
4.5
6.3
5.0
7.5
4.0
6.0
6.0
9.0
Nole 1: Referto RETSF11201X, RETSFI1331X. RETSF11332X and RETSF11333X for military specifications.
Note 2: For operating at high temperature the molded DIP products must be derated based on a
+ 10QoC maximum junction temperature and a thermal resistance
of + IS0'C/W, devices in the cavity OIP are based on a + ISO'C maximum junction temperature and are derated at ± 100'C/W.
Nole 3: Unless otherwise specified, VCC= + ISV, VEE= -ISV, VR=OV. and limits apply for -SS'C':TA': + 12S'C for the LF11331/2/3 and the LFI1201/2.
-2S'C':TA': +8S'C for the LFI3331/2/3 and the LFI3201/2.
Nole 4: These parameters are limited by the pin to pin capacitance of the package.
Note 5: This is the analog signal slew rate above which the signal is distorted as a result of finite internal slew rates.
Nole 6: All switches in the device are tumed '"OFF'" by saturating a transistor at the disable node as shown in Figure 5. The delay time will be approximately equal
to the !oN or !oFF plus the delay introduced by Ihe external transistor.
Note 7: This graph indicates the analog current at which 1 % of the analog current is lost when the drain is positive with respect to the source.
Nole 8: 8JA (Typical) Thermal Resistance
Molded OIP (N)
8S'C/W
Cavity OIP (D)
100'C/W
Small Outline (M)
10S'C/W
2·53
~fJ
Connection Diagrams (Top View for SO and Dual-In-Line Packages) (All Switches Shown are For Logical "0")
LF113311LF13331
IN.
04
S3
LF11332/LF13332
03
IN,
04
54 Dl5ABLE .Vee
53
03
52
02
14
IN,
01
51
VA
-VEE
52
02
IN,
IN,
01
51
VA
-VEE
LF11333/LF13333
IN.
04
IN,
01
51
VA
-VEE
LF11201/LF13201
S3
D3
52
02
IN,
IN,
.Vee
Ne
53
54
.V ee
Ne
53
03
01
51
-VEE
VA
52
02
IN,
Order Number LF13201D, LF11201D, LF13202D,
LF11202D,LF13331D,LF11331D,LF13332D,LF11332D,
LF13333D or LF11333D
See NS Package Number D16C
LF11202/LF13202
54
04
TLlH/5667 -15
TUH/5667-14
04
IN,
TL/H/5667-13
TUH/5667-1
03
Order Number LF13201M, LF13202M, LF13331M,
LF13332M or LF13333M
See NS Package Number M16A
Order Number LF13201N, LF13202N, LF13331N,
LF13332N or LF13333N
See NS Package Number N16A
IN,
01
51
-VEE
VA
52
02
IN,
TL/H/5667-16
2-54
r-
"'TJ
....
....
Test Circuit and Typical Performance Curves
Delay Time, Rise Time, Settling Time, and Switching Transients
Co)
Co)
•y,
-wsv
v! .+~V
V.I'+I~V
I
I
Co)
Co)
Co)
Vo
I
f
J'N
11
1\
c- t- VIN
\
\
I-
I\.
11Vo r-
t-J I
-1'1
r
..k
I
ZOOnsldi,
J••~v
Vo
vl. _Isv
-.l
I
Vo
II
t- JON 1\
.......
r-
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....
......
r-
........"'TJ
Co)
Co)
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I
V~N
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II.)
Co)
Co)
Co)
II.)
v.'. -Iov
Vo
IA
....
......
r"'TJ
....
....
......
r"'TJ
....
....
t-
.......
JON
r-
....
"'TJ
\
VONt- f-f-
Co)
Co)
Co)
Co)
......
r-
200nsJdiv
200ns/div
ZDDnsldi,
TL/H/5667-3
Additional Test Circuits
vw
l.DY
+1SV
-15V
·v,
""
ov
vu~'30:JU1
........"'TJ
C
....
.......
r"'TJ
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C
....
......
r"'TJ
....
....
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Co)
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...
Vo
II.)
vD-·,av
C
II.)
.......
IOV
r-
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v,.
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~g
uv
V.
-I.OV
Vo
Uk
·V... -Z,gy
T
-tOV
'DPF
-Yo
1,.-
2.0
ii!
1.0
t
i
0.4
0.2
~
~
WW~~~~~Lll~~
10
IDa
1.Ok
10k lOOk
I.OM
1 1.--'-_..1-_1.--'-_...1
-100
50
50
100
150
0.'
~~~~~-4~~~=j
10
2.0
Maximum Accurate
Analog Current
VB Temperature
c,o",
""'
ATTENUATION = 20 lOG
801--1-----1-
(SEE FIGURE 4)
I - - 1---
o L-_'---'_-'-_--'---'-'
'UO
HiD
6.0
~
'.0
:l
10M
t:-
~I+COIONI
r'" -
C~COfFI
~
c
2.0
10
10
2.0
6.0
100M
2.0
6.0
10
Logical "'''Input Bias
Current
. -j--
"
-100
511
8.0
I---
i
I.......... ~
i
50
100
150
6.0
4.0
~.
~
..
Vee -nv
Vu: 15V
VIN =+5.0V
VA "OV
1-
1\
.3
TEMPERATURE I C)
FREQUENCY (Hzl
Vee" 15V
Vu" ·15V
VA (VOLTS)
o
1M
6.0
10
'"i'-
20
&0
u
i.OTE al
40
TEMPERATURE ( CI
an
·20
N'
~
IV,.,1
aD
50
2.0
Small Signal Response
6
-100
6.0
VA IVOLTS)
100
.....
o
TEMPERATURE I C)
FREQUENCY (Hri
Slew Rate of Analog
Voltsge Above Which
Signal Loading Occurs
02
10
~
~
o
...I
:~
.....
~~,.....--~-~-
1l
o
-~
o.a
~
'.0
" '.0
.!
i
Switch CapaCitances
Switch Leakage Current
Switch Leakege Currents
Supply Current
so
I---
\
f---- f----
..........
t-- f-
2.0
•
-100
50
&0
100
150
TEMPERATURE ( C)
TUH/5667-5
2-56
r
-n
Application Hints
GENERAL INFORMATION
LEAKAGE CURRENTS
The drain and source leakage currents, in both the ON and
the OFF states of each switch, are typically less than 1 nA
at 2SoC and less than 100 nA at 12SoC. As shown in the
typical curves, these leakage currents are Dependent on
power supply voltages, analog voltage, analog current and
the source to drain voltage.
These devices are monolithic quad JFET analog switches
with "ON" resistances which are essentially independent of
analog voltage or analog current. The leakage currents are
typically less than 1 nA at 2SoC in both the "OFF"and "ON"
switch states and introduce negligible errors in most applications. Each switch is controlled by minimum TTL logic
levels at its input and is designed to turn "OFF" faster than
it will turn "ON." This prevents two analog sources from
being transiently connected together during switching. The
switches were designed for applications which require
break-before-make action, no analog current loss, medium
speed switching times and moderate analog currents.
DELAY TIMES
The delay time OFF (tOFF) is essentially independent of
both the analog voltage and temperature. The delay time
ON (tON) will decrease as either (Vee-VA) decreases or
the temperature decreases.
Because these analog switches are JFET rather than
CMOS, they do not require special handling.
POWER SUPPLIES
The voltage between the positive supply (Vecl and either
the negative supply (VEE) or the reference supply (VR) can
be as much as 36V. To accommodate variations in input
logic reference voltages, VR can range from VEE to
(Vee-4.SV). Care should be taken to ensure that the power
supply leads for the device never become reversed in polarity or that the device is never inadvertantly installed backwards in a test socket. If one of these conditions occurs, the
supplies would zener an internal diode to an unlimited current; and result in a destroyed device.
LOGIC INPUTS
The logic input (IN), of each switch, is referenced to two
forward diode drops (1.4V at 2S0C) from the reference supply (VR) which makes it compatible with DTL, RTL, and TTL
logic families. For normal operation, the logic "0" voltage
can range from O.BV to -4.0V with respect to VR and the
logic "1" voltage can range from 2.0V to 6.0V with respect
to VR, provided VIN is not greater than (Vee-2.SV). If the
input voltage is greater than (Vee - 2.SV), the input current
will increase. If the input voltage exceeds 6.0V or -4.0V
with respect to VR, a resistor in series with the input should
be used to limit the input current to less than 100ILA.
SWITCHING TRANSIENTS
When a switch is turned OFF or ON, transients will appear
at the load due to the internal transient voltage at the gate
of the switch JFET being coupled to the drain and source by
the junction capacitances of the JFET. The magnitude of
these transients is dependent on the load. A lower value RL
produces a lower transient voltage. A negative transient occurs during the delay time ON, while a positive transient
occurs during the delay time OFF. These transients are relatively small when compared to faster switch families.
ANALOG VOLTAGE AND CURRENT
Analog Voltage
Each switch has a constant "ON" resistance (RON) for analog voltages from (VEE+SV) to (Vee-SV). For analog voltages greater than (Vee-SV), the switch will remain ON independent of the logic input voltage. For analog voltages
less than (VEE+SV), the ON resistance of the switch will
increase. Although the switch will not operate normally
when thE! analog voltage is out of the previously mentioned
range, the source voltage can go to either (VEE + 36V) or
(Vee + 6V), whichever is more positive, and can go as negative as VEE without destruction. The drain (D) voltage can
also go to either (VEE+36V) or (Vee+6V), whichever is
more positive, and can go as negative as (Vee-36V) without destruction.
DISABLE NODE
This node can be used, as shown in Figure 5, to turn all the
switches in the unit off independent of logic inputs. Normally, the node floats freely at an internal diode drop (::::: 0.7V)
above VR. When the external transistor in Figure 5 is saturated, the node is pulled very close to VR and the unit is
disabled. Typically, the current from the node will be less
than 1 mA. This feature is not available on the LF11201 or
LF11202 series.
Analog Current
With the source (S) positive with respect to the drain (D), the
RON is constant for low analog currents, but will increase at
higher currents (> SmA) when the FET enters the saturation region. However, if the drain is positive with respect to
the source and a small analog current loss at high analog
currents (Note 6) is tolerable, a low RON can be maintained
for analog currents greater than S mA at 2SoC.
r----I
I
}VOISABlI ,IV
TL/H/5667-6
FIGURE 5_ Disable Function
2-S7
.....
.....
......
Co)
Co)
r
-n
.....
Co)
Co)
Co)
.....
.......
r
-n
.....
.....
Co)
Co)
N
......
r
-n
.....
Co)
Co)
Co)
~
r
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BI·FET II ™ Technology
LF13508 8-Channel Analog Multiplexer
LF13509 4-Channel Differential Analog Multiplexer
Co)
en
o
CD
General Description
The LF13508 is an 8·channel analog multiplexer which con·
nects the output to 1 of the 8 analog inputs depending on
the state of a 3·bit binary address. An enable control allows
disconnecting the output, thereby providing a package se·
lect function.
This device is fabricated with National's BI·FET technology
which provides ion·implanted JFETs for the analog switch
on the same chip as the bipolar decode and switch drive
circuitry. This technology makes possible low constant
"ON" resistance with analog input voltage variations. This
device does not suffer from latch·up problems or static
charge blow·out problems associated with similar CM05
parts. The digital inputs are designed to operate from both
TTL and CM05 levels while always providing a definite
break·before·make action.
The LF13509 is a 4·channel differential analog multiplexer.
A 2·bit binary address will connect a pair of independent
analog inputs to one of any 4 pairs of independent analog
outputs. The device has all the features of the LF13508
series and should be used whenever differential analog in·
puts are required.
Features
•
•
•
•
•
•
•
•
•
•
JFET switches rather than CM05
No static discharge blow·out problem
No 5CR latch·up problems
Analog signal range 11V, -15V
Constant "ON" resistance for analog signals between
-11V and 11V
"ON" resistance 380 n typ
Digital inputs compatible with TTL and CM05
Output enable control
Break·before·make action: toFF=0.2 /Ls; toN=2 /Ls typ
Lower leakage devices available
Functional Diagrams and Truth Tables
LF13508
AZ
EN
AI
AD
-VEE
GND
Vee
S8
S7
S6
S5
S4
S3
SZ
SI
EN
A2
A1
AO
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
L
L
H
H
H
X
H
X
H
H
H
H
X
L
L
L
L
L
SWITCH
ON
51
52
53
54
55
56
57
58
NONE
LF13509
AI
EN
DB
54B
S3B
SZB
SIB
S4A
SlA
SZA
SIA
DA
TL/H/566B-l
2·63
EN
A1
AO
L
X
X
H
H
H
H
L
L
L
H
H
H
H
L
....
."
SWITCH
PAIR ON
None
51
52
53
54
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Positive Supply - Negative Supply (Vee- VEE)
36V
Positive Analog Input Voltage (Note 1)
Vee
Negative Analog Input Voltage (Note 1)
-VEE
Positive Digital Input Voltage
Vee
Negative Digital Input Voltage
-5V
Analog Switch Current
ilsi<10mA
Power Dissipation (Po at 25°C)
(Notes 2 & 7)
Molded DIP (N)
500mW
Po
Cavity DIP (D)
900mW
Po
100°C
Maximum Junction Temperature (TjMAxl
Operating Temperature Range
O°C,;;TA';; +70°C
-65°C to + 150°C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)
300°C
Electrical Characteristics (Note 3)
Symbol
Parameter
LF13508
LF13509
Conditions
Min
"ON" Resistance
RON
aRON with Analog Voltage
Swing
aRON
VOUT=OV, Is=100 p.A
-10V,;;VOUT';; + 10V,ls= 100 p.A
TA=25°C
TA=25°C
Units
Typ
Max
380
650
500
850
n
n
0.D1
1
%
20
150
n
5
nA
50
nA
20
nA
RON Match
RON Match Between Switches
Source Current in "OFF"
Condition
VOUT=OV,ls= 100 p.A
Switch "OFF", Vs=11, Vo= -11,
(Note 4)
TA = 25°C
IS(OFF)
IO(OFF)
Drain Current in "OFF"
Condition
Switch "OFF", Vs=11, Vo= -11,
(Note 4)
TA=25°C
IO(ON)
Leakage Current in "ON"
Condition
Switch "ON" Vo= 11V, (Note 4)
TA=25°C
VINH
Digital "1" Input Voltage
VINL
Digital "0" Input Voltage
IINL
Digital "0" Input Current
VIN=0.7V
TA=25°C
1.5
IINL(EN)
Digital "0" Enable Current
VEN=0.7V
TA=25°C
1.2
TA=25°C
0.09
0.6
1
500
nA
20
nA
500
nA
2.0
V
0.7
V
30
p.A
40
p.A
30
p.A
40
p.A
tTAAN
Switching Time of Multiplexer
(Figure 1), (Note 5)
TA=25°C
1.8
tOPEN
Break-Before-Make
(FigureS)
TA=25°C
1.6
p.s
tON(EN)
Enable Delay "ON"
(Figure 2)
TA=25°C
1.6
p's
tOFF(EN)
Enable Delay "OFF"
(Figure 2)
TA=25°C
ISO(OFF)
CT
"OFF" Isolation
(Note 6)
TA=25°C
dB
Crosstalk
LF13509 Series, (Note 6)
TA=25°C
0.2
-66
-66
CS(OFF)
Source CapaCitance ("OFF")
Switch "OFF", VOUT=OV,
Vs=OV
TA=25°C
2.2
pF
CO(OFF)
Drain Capacitance ("OFF")
TA=25°C
Icc
Positive Supply Current
Switch "OFF", VOUT=OV,
Vs=OV
All Digital Inputs Grounded
lEE
Negative Supply Current
All Digital Inputs Grounded
TA=25°C
TA=25°C
p's
p.s
dB
pF
11.4
7.4
12
mA
7.9
15
mA
2.7
5
mA
2.8
6
mA
1: II the analog input voltage exceeds this limi~ the input current should be limited to less than 10 mA.
Note 2: The maximum power dis~ipation lor these devices must be derated at elevated temperatures and is dictated by TjMAX. 9jA, and the ambient temperature,
TA. The maximum available power dissipation at any temperature is Po~ (ljMAX - TA)19jA or the 2S'C POMAX, whichever is less.
Note
Note 3: These speCifications apply for Vs= ±15V and over the absolute maximum operating temperature range (TL::;;:TA::s;;TH) unless otherwise noted.
Note 4:
Conditions applied to leakage tests insure worse casa leakages. Exceeding 11V on the analog input may causa an "OFP' channel to turn "ON".
Note 5: Lots are sample tested to this parameter. The measurement conditions of Figure 1 insure worse case transition time.
"OFF" isolation Is measured with all switches "OFF" and driving a source. Crosstalk is measured with a pair 01 switches "ON", driving channel A and
measuring channel B. RL ~200, CL~7 pF, Vs~3 Vrms, I~SOO kHz.
Note 7: Thermal Resistance 9jA (Junction to Ambient)
Molded DIP (N)
lS0'C/W
Cavity DIP (D)
100'C/W
Note 6:
2-64
r-
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Connection Diagrams
-"
Co)
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LF13508
Dual-In-Llne Package
AI
GNU
A2
1,6
15
Vee
55
13
\4
56
12
57
11
AI
58
2
EN
3
-VEE
4
51
6
5
52
53
7
Vee
15
14
51B
52B
13
12
53B
"r-
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I
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AD
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9
10
r-
2
EN
TOP VIEW
3
4
5
-VEE
51A
52A
6
S3A
7
54A
18
TUPVIEW
TL/H/5668-2
Order Number LF13508D
See NS Package Number D16C
Order Number LF13508N
See NS Package Number N16A
Order Number LF13509D
See NS Package Number D16C
Order Number LF13509N
See NS Package Number N16A
AC Test Circuits and Switching Time Waveforms
15V
Vec
0----.
52-S7 .....
LF13508
LOGIC
INPUT
10M,:"
T
10 pF
-15V
TL/H/5668-3
FIGURE 1. Transition Time
2-65
U1
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CQ
1
B
54
-"
54B
-
l-
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GNU
1,6
9
10
-
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LF13509
Dual-In-Llne Package
CD
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AC Test Circuit and Switching Time Waveforms (Continued)
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ENA8LE
INPUT
-15V
10pF
FIGURE 2. Enable Times
15V
10V
EN
A2
,...-.....0...<;>-1 AI
LFI3508
S2-S11-0-+.,
S8
AO
LOGIC
INPUT
INPUT
DRIVE
3V~
OV
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FIGURE 3. Break·Before·Make
Transition Times and Transients
VA=10V
VA=5V
VIN
Y,N
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GNo
Vo
Vo
lpSJDIV
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TLlHIS668-S
TLIHIS668-6
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TLlHIS688-7
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TLIHIS668-8
Test Circuit
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VIN
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10M
':"
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Il0PF
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TL/HIS668-10
TLIHIS668-9
2-66
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......
Typical Performance Characteristics
(0)
U'I
"ON" Resistance
"ON" Resistance
800
400
-z 400
'"= 300
i!J
a: 340
VCC'15V
VEE' -15V
IA'O
TA' 25"C
320
TA '25'C
VCC '15V
VEE' -15V
600
,.-
500
360
......
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VCC '15V
600 -VEE' -15V
380
S
"ON" Resistance
_I~.ioo"~
100
o
(X)
"T1
......
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500
,/
§
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400
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200
200
100
100
o
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300
i""'"
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300
-10 -8 -6 -4 -2 0
2
4
6
-55 -35 -15 5
8 10
-2
TEMPERATURE I'CI
ANALOG INPUT VOLTAGE IVI
Switch Leakage
Currents
10
25 45 65 85 105 125
-1
ANALOG INPUT CURRENT ImAI
Switch Leakage
Currents
Switch Leakage
Currents
1000
100
VCC '15V
r-- VEE' -15V
TA' 25'C
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1
10:ONI
0.1
%
....
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-10
-5
10
15
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2.5
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-10
10
-5
15
-55
./iSIOFFI
h~
~
95
65
125
-30
'/
-40
tONEy
-50
V
tOPEN
35
"OFF" Isolation and
Crosstalk
3
VdC"5t
-VEE'-15V
-25
TEMPERATURE I"CI
Enable Delay Times
(Figure 2)
A
~V
V
0.1
ANALOG VOLTAGE IVI
Switching Times
(Figures 1 and 3)
)-
-IOIOFFI
0.01
-15
ANALOG VOLTAGE IVI
3.5
m
w
10
-15
r-- -
'"
B
-1
-10
IOIONI
:5
'OIONI
-"""";;'OIOFFI
100
a
-0.1
/,
10
~
~
-60
i!J
-10
5
./'
!!
V
-80
-90
'OFFEN-
0.5
-100
-110
-55
-25
35
65
95
125
-55
-25
TEMPERATURE I'CI
35
65
95
10k
125
9
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'EN
........... ~lpPLY
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"....
r- r-
10M
Switch Capacitances
10
VCC '15V
VEE '-15V VLOGIC' OV
1M
FREQUENCY IH"
Supply Currents
Bias Currents
t\.
lOOk
TEMPERATURE I"CI
-ISUPPLY
~
-
24
22
20
18
16
14
12
10
8
C~IONI
COIOFFI
r-
CSIOFFI
2
o
-55
-25
35
65
TEMPERATURE rCI
95
125
-55
-25
35
65
TEMPERATURE I'CI
95
125
-12-10-8-6-4-2024681012
ANALOG VOLTAGE IVI
TL/H/5668-11
2-67
Application Hints
The LF11508 series is an 8-channel analog multiplexer
which allows the connection of a single load to 1 of 8 different analog inputs. These multiplexers incorporate JFETs in
a switch configuration which insures a constant "ON" resistance over the analog voltage range of the device. Four TIL
compatible inputs are provided; a 3-bit binary decode to select a particular channel and an enable input used as a
package select. The switches operate with a break-beforemake action preventing the temporary connection of 2 analog inputs during switching. Because these multiplexers are
fabricated with the BI-FET process rather than CMOS, they
do not require special handling.
LEAKAGE CURRENTS
Leakage currents will remain within the specified value as
long as the drain and source remain within the specified
analog voltage range. As the switch terminals exceed the
positive analog voltage range "ON" and "OFF" leakage
currents increase. The "ON" leakage increases due to an
internal clamp required by the switch structure. The "OFF"
leakage increases because the gate to source reverse bias
has been decreased to the point where the switch becomes
active. Leakage currents vary slightly with analog voltage
and will approximately double for every 1O·C rise in temperature.
The LF11509 series is a 4-channel differential multiplexer
which allows two loads to be connected to 1 of 4 different
pairs of analog inputs. The LF11509 series also has all the
features of the LF11508.
SWITCHING TIMES AND TRANSIENTS
These multiplexers operate with a break-before-make
switch action. The turn off time is much faster than the turn
on time to guarantee this feature over the full range of analog input voltage and temperature. Switching transients are
introduced when a switch is turned "OFF". The amplitude of
these transients may be reduced by increasing the load capacitance or decreasing the load resistance. The actual
charge transfer in the transient may be reduced by operating on reduced power supplies. Examples of switching times
and transients are shown in the typical characteristic
curves. The enable function switching times are specified
separately from switch-to-switch transition times and may
be thought of as package-to-package transition times.
ANALOG VOLTAGE AND CURRENT
The "ON" resistance, RON, of the analog switches is constant over a wide input range from positive (Vee) supply to
negative (- VEE) supply.
The analog input should not exceed either positive or negative supply without limiting the current to less than 10 mA;
otherwise the multiplexer may get damaged. For proper operation, however, the positive analog voltage should be kept
equal to or less than Vee - 4V as this will increase the
switch leakage in both "ON" and "OFF" state and it may
also cause a false tum "ON" of a normally "OFF" switch.
This limit applies over the full temperature range.
LOGIC INPUTS AND ENABLE INPUT
Switch selection in the LF11508 series is accomplished by
using a 3-bit binary decode while the LF11509 series uses a
2-bit decode. These binary logic inputs are compatible with
both TIL and CMOS logic voltage levels. The maximum
positive voltage applied to these inputs may exceed Vee but
should not exceed -VEE + 36V. The maximum negative
voltage should not be less than 4V below ground as this will
cause an internal device to zener and all the switches will
turn "ON".
The maximum allowable switch "ON" voltage (the drop
across the switch in the "ON" condition) is ± 0.4V over temperature. If this number is to exceed the input current should
be limited to 10 mA.
The "ON" resistance of the multiplexing switches varies
slightly with analog current because they are JFETs running
at OV gate to source. The J FET characteristics shown in
Figure 4 indicates how RON tends to vary with current. A
lower RON is possible when the source voltage is negative
with respect to the drain voltage because the JFET becomes enhanced. Caution should be used when operating
in this mode as this may forward-bias an internal transistor
and cause high currents to flow in the switches. Thus, the
drain voltage should never be greater than 0.4V positive
with respect to the source voltage without limiting the drain
current to less than 10 mAo
As shown in the schematic diagram, the logic low bias current will flow until the PNP input is raised above the 3 diode
reference (::::: 2.1 V). Above this voltage the input device becomes reverse biased and the input current drops to the
leakage of the reverse biased junction «0.1 /LA).
-p
S
I.B
..'".
1.2
1.8
O.B
-2
D
J!'
I'
0.4
VSD
oS
D
2
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3.6
J...o"
I'
/
-1.8
- ""
I
-3.B
-1
-2
VSDIVI
-1
VSDIVI
FIGURE 4. JFET Characteristics
2-68
TlIH/5668-12
.-
...
'T1
Typical Applications
(0)
U1
o
DATA ACQUISITION SYSTEM
A SIMPLIFIED SYSTEM DISCUSSION
Analog multiplexers (MUX) are usually used for mUlti-channel Data Acquisition Units (DAU). Figure 5 shows a system
in which 8 different analog inputs are sampled and converted into digital words for further processing. The sample and
hold circuit is optional, depending on input speed requirements and on AID converter speed.
.
Parameters characterizing the system are:
System Channels: The number of multiplexer channels.
Accuracy: The conversion accuracy of each individual sample with the system operating at the throughput rate.
a. The error, (El, caused by the finite "ON" resistance, RON, of the multiplexing switches is given
by:
100
+ RIN/(RoN + Rs + ~RON)
where:
RIN = following stage input impedance
~RON = "ON" resistance modulation which is
negligible for JFET switches like the LF11508
Example: Let RON = 450 n, ~RON = 0, Rs = 0, TA
= 25'C and allowable E = 0.01 % which is equivalent
to 1/2 LSB in a 12-bit system:
RIN
Imin =
RON(100 - E)
E
ERROR %
BITS
0.2
0.05
0.01
0.0008
8
10
12
16
6.2t
7.6t
9t
11.8t
+
Rs) II RIN
The "accuracy" of the AID converter is the best possible
system accuracy. In most data acquisition systems, the
AID converter is the most expensive single component,
so its error will often dominate system error. Care should
be taken that MUX, S/H and input source errors do not
exceed system error requirements when added to AID
errors. For instance, if an 8-bit accuracy system is desired
and an 8-bit AID converter is used, the accuracy of the
MUX and S/H should be far better than 8 bits.
For details on AID converter specifications, see AN-156.
= 4.5Mn
Note that if temperature effects are included, some
gain (or full scale) drift will occur; but effects on linearity
are small.
b. Multiplexer settling time (ts):
ts(ON): is the time required for the MUX output to
settle within a predetermined accuracy, as
shown in Table I.
Cs (Figure 6): MUX output capacitance + following stage input capaCitance + any stray capacitance at this node.
V,N
PRECONDITIONED [
ANALOG INPUTS
} n BITS WORD
CONVERSION COMPLETE
TLlH/566B-13
FIGURE 6. a-Channel MUX
FIGURE 5. Random-Addressed, Multiplexed DAU
2-69
...
'T1
(0)
U1
o
co
ts(OFF): is the time it takes to discharge Cs within
a tolerable error. The "OFF" settling time should
be taken into account for bipolar inputs where its
effects will appear as a worse case of doubling
of the ts(ON)'
2. Sample and Hold Influence on System Accuracy
The sample and hold, if used, also introduces errors into
the system accuracy due to:
• Offset voltage of sample and hold
• Droop rate in the Hold mode
• TA: Aperture time or time delay between the time of a
digital Hold command and the actual Hold occurance
• Taq: Acquisition time or time it takes to acquire an
analog input and settle within a predetermined error
band
• Hold step: Error created during the Sample to Hold
mode caused by an undesirable charge injected into
the Hold capacitor Ch.
For more details on sample and hold errors, see the
LF198/LF298/LF398 data sheet.
3. AID Converter Influence on System Accuracy
A. ACCURACY CONSIDERATIONS
1. Multiplexer's Influence on System Accuracy (Figure 6).
1
.-
ts(ON)
TO 112 LSB
t = Cs (RON
Speed or Throughput Rate: Number of samples/secondl
channel the system can handle.
For a discussion on system structure, addressing mode and
processor interfacing, see application note AN-159.
E(%) =
co
......
TABLE I.
en
o
r---------------------------------------------------------------------------------,
In
Typical Applications (Continued)
I.L
B. SPEED CONSIDERATIONS
In the system of Figure 5 with the S/H omitted, if n-bit accuracy is desired, the change of the analog input voltage
should be less than ± 1/2 LSB over the A/D conversion
time Te. In other words, the analog input slew rate, (rate of
change of input voltage), will cause a slew-induced error
and its magnitude, with respect to the total system error, will
depend on the particular application.
C')
.....
-'
.......
co
o
In
C')
.....
I.L
-'
where T A is the aperture time of the S/H. This represents an input slew rate improvement by a factor: T e/
TA. Here again, the slew rate error is not affected by
the acquisition time of the Sample and Hold since conversion will start after the S/H has settled. An important thing to notice is that the sample and hold errors
will add to the total system e"or budget; therefore, the
inequality of the AV/N/At expression should become
more stringent.
Example: Te = 40 ,.,.S, TA = 0.5 ,.,.S, n = 8: Te/TA = 80
So the use of a S/H allows a speed improvement by
nearly two orders of magnitude.
The maximum throughput rate can be calculated by:
<±1/2LSB=~
AVINI
At max
Te
2n X Te
where VFS is the full scale voltage of the AID. Note that
slew induced errors are not affected by the MUX switch time
since we can let the unit settle before starting conversion.
Th. R
AVIN I
--At
max
1mV'
<-,.,.S
1
The LF398 S/H with a 1000 pF hold capacitor, has an acquisition time of 4 ,.,.S to 0.1 % (1/4 LSB error for 8 bits) and
an aperture time of less than 200 ,.,.S. On the other hand,
after the hold command, the output will settle to ±0.05 mV
in 1 ,.,.S. This, together with the acquisition time, introduces
approximately a ± 1/4 LSB error. Allowing another 1/4 LSB
error for hold step and gain non-linearity, the maximum slew
error (AVIN/ At) should not exceed 1/4 LSB or:
Th. R I
=
1T
= 3k samples/sec/
max
8(Te + MUX)
channel
AVIN 1
1
1
--";;-X X - =5mV/,.,.s
At
4 256 TA
(which is the maximum slew rate of a 5 V peak sine wave.
Also notice that, due to the above input slew restrictions,
the analog delay caused by the finite BW of the S/H and the
digital delay caused by the response time of the controller
will be negligible. The maximum throughput rate of the system is:
+ TS(ON)
Also notice that Nyquist sampling criteria would allow
each channel to have a signal bandwidth of 1.5 kHz max,
while the slew limit dictates a maximum frequency of 32
Hz. If the input signal has a peak-to-peak voltage less
than 10V, the allowable maximum input frequency can be
calculated by:
f
=
C. SYSTEM EXAMPLE (Figure 7)
which is a very small number. A 10 Vp-p sine wave of a
frequency greater than 32 Hz will have higher slew rate
than this. The maximum throughput rate of the above 8channel system would be calculated using both the AID
conversion time and the sum of MUX switch "ON" time
and settling time, i.e.:
TMUX = TON
I
max
8(TA + Taq + Tel
Notice that TMUX does not affect the AVIN/At expression
nor the throughput rate of the system since it may be
switched and settled while the Sample and Hold is in the
Hold mode. This is true, provided that: TMUX < TA + Te.
Example: Let Te = 40 ,.,.s (MM4357), VFS = 10V and n
= 8.
Th. R Imax = 8(5
_ (Slew Rate)max
MAX 7TVp-p
+ ~0)10-6 =
2800 samples/sec/ch.
If the system speed requirements are relaxed, but the AID
converter is still too slow, then an inexpensive S/H can be
built by using just a capacitor and a low cost FET input op
amp as shown in Figure 8.
On the other hand, if the input voltage is not band-limited a
low pass filter with an attenuation of 30 dB or better at 1.5
kHz, should be connected in front of the MUX.
1. Improving System Speed with a Sample and Hold
The system speed can be improved by using the
S/H shown in Figure 5. This allows a much greater
rate of change of VIN.
aVIN I
VFS
max <2n XTA
At
2-70
r-----------------------------------------------------------------------;r
."
...
Typical Applications (Continued)
Co)
UI
15V
o
CD
.......
r
-15V
15V
...
."
Co)
UI
o
r-l;;--~IW-'
I
I
I
I
I
I
CO
VIN
12
ADC0800PC
I
I
I
ClK
SC
I
lF13508
EN
AD
16
15
AI
A2
EOC: End of Conversion
I
I
I
lk
'::' I
L _______
.J
2.4k
15V
EDC
11
SC: Start Conversion
-12V
SfH
r l-4 - - -....o. . ........;~
FIGURE 7a. Sequentially Multiplexed DAU with Sample and Hold
n.nn.rmnnruuu1.JU1IUlnJUUUU1.IUlMIUUUtnJlIlruUlr .
"0" - - - ,
r,
r1
r1
IJ
IJ
,J
SfH -..J
rL
n
~~~I------1n...- - - -
SC _ _ _ _ _ _
DCC
L-J
r,
ClKEN _ _ _ _ _.....
AD _ _ _ _ _ _--',1
Al ________________
I
Ir--L-J
r1
r1. . ___. . . rL
.
L-!I-I---.. . .r'
.
~~----------~~'
,r
II
L-_
L_
A2 _ _ _ _ _ _ _ _ _ _~I~I------------~l/i~--------------~I"------------~~TlIH/566B-14
FIGURE 7b. Timing Diagram
2-71
~~--------------------------------------------------------~
C)
It)
(Continued)
C'I)
.,...
~
.....
~
s
C'I)
Typical Applications
An alternate way to increase the system channel is shown
in Figure 10, where the enable pins are used to disable one
MUX while the other is sampling. With this method, many 8channel multiplexers can be connected, but the parasitic
capacitance at the common output node will keep increasing and will eventually degrade the settling time, Is(ON)'
Also, the MUX speed will now affect the system throughput.
If, for instance, this method was used instead of second
level multiplexing, the system of Figure 9 will lose half of its
speed. If, however, speed is not the prime system requirement, the approach of Figure 10 is more cost effective.
D. DOUBLING THE SYSTEM CHANNEL CAPABILITY
This is done in two different ways. First, we can use second
level multiplexing with speed benefits, as shown in Figure 9.
A fast 2-channel multiplexer, made by the dual analog
switch AM182, accepts the outputs of each 8-channel MUX,
LF13508, and then feeds them sequentially into an 8-bit
successive approximation AID converter. With this technique, the throughput rate of the system can again be made
independent of the LF13508 speed. Looking at the timing
diagram, when the AID converter converts the analog value
of an upper multiplexer channel, we switch channels in the
lower multiplexer for the next conversion. This can be done
provided that:
E. DIFFERENTIAL INPUT SYSTEMS
Systems operating in industrial environments may require
an instrumentation amplifier to separate the desired analog
signal from any common-mode signal present. The
LF11509 was designed to provide 4 pairs of differential input Signals to the input of an instrumentation amplifier for
further process. A 4-channel preconditioning circuit is
shown in Figure 11 and a complete system is shown in Figure 12.
TMUX:;;; Tc + 1 CP
The LF356 connected as unity gain buffers are used because of the low input impedance of the A/D; they are connected between multiplexers for speed optimization. With a
maximum clock frequency of 4.5 MHz:
106
Th. R = 16 x 2 = 31.25k samples/sec/channel
and
&VIN I
10
At
max < 256 X
1
2,..s = 19.5 mV /,..s for 10VFS
15V
-15V
-
-
"'TOA/D
r
SAMPLE--,
HOLD ____ L.J
EN
AD
AI
A2
CHANNEL SELECT
TLIHI566B-15
o The acquisition time. TA. of the Sample and Hold depends upon: RON. lOSS of switches. ZOUT of switches
0'055"'1.5 mAo ZOUT=40 kO
o VIN= 10V, Ch=IOOO pF. TA=20 fLs to 0.10/0
o Error created by charge injection during Hold mode: aVE'" 10 pF (14.5V-VIN)ICh
FIGURE 8. Inexpensive Sample and Hold
2-72
.-----------------------------------------------------------------------,r
."
.....
Typical Applications (Continued)
Co)
~
r------~-----------,
CD
.....
r
I
15V
."
.....
Co)
~_AJIIII_+_O() 5. I
-lSV
U1
I
I
I
I
I
o
CD
I
I
I
I
S2
L _______ _
____
r--------
I
I
I
I
I
-15V
------,
I
I
10
DM25D2
I
I
I
15V
Lsa o,.,~="..
MSBO:-=="'-I----+
I
I
I
I
I
I
15V
~N!.!!.!!.L~IC..J
I
I
IL
15V
5.
l.9M
O.OIIlF":"
I
I
-
-15.
______
_S.A.
_AID
15V_ _
-15V_ _ _ _ _ _ _
- _ _ _8.BIT
I
~
FIGURE 9a. A Fast 16-Channel DAU with Second Level Multiplexing
eLK
..JUUUUU1IlfLflJUUUUUUlJUUUUUUUUUUUUl
I
PI
I
I
I
AD
I
I
AI
I
I
AZ
I
I
1
I
ace I
,.
U
I-9CP-~1
l'
U
Z.
U
Zb
u "
U
3b
U
4.
U
I
4b
L
TUH/566B-16
FIGURE 9b. Timing Diagram
2·73
~
....u..
C')
-'
.........
co
Typical Applications (Continued)
ISV
15V
C
~
....
u..
-'
.-1-'-0-....-0 TO S1H OR AID
MM74CI93
15V
-15V
TL/H/566B-17
FIGURE 10. A 16-Channel Multiplexer with Sequential Multiplexing
2-74
------------------------------------------~5
Schematic Diagrams
LF13508
Co)
~
QC)
.......
r
....'TI
Co)
en
o
CO
2-75
0)
oII)
C")
.....
..J
......
u..
Schematic Diagrams (Continued)
LF13509
CO
oII)
C")
.....
LL
..J
2-76
NatiOnal
~ Semiconductor
\
Corporation
J
microCMOS
MM54HC40 16/MM7 4HC40 16
Quad Analog Switch
General Description
Features
These devices are digitally controlled analog switches implemented in microCMOS Technology, 3.5 micron silicon
gate P-well CMOS. These switches have low "on" resistance and low "off" leakages. They are bidirectional
switches, thus any analog input may be used as an output
and vice-versa. The '4016 devices allow control of up to
12V (peak) analog signals with digital control signals of the
same range. Each switch has its own control input which
disables each switch when low. All analog inputs and outputs and digital inputs are protected from electrostatic damage by diodes to Vee and ground.
•
•
•
•
•
•
Connection Diagram
Truth Table
Typical switch enable time: 15 ns
Wide analog input voltage range: 0-12V
Low "on" resistance: 50!} typo
Low quiescent current: 80 poA maximum (74HC)
Matched switch characteristics
Individual switch controls
Dual·ln·Line Package
Vee
1CTL
4CTL
41/0
40/1
30/1
31/0
Input
Switch
8
CTL
1/0·0/1
L
H
"OFF"
liON"
7
1110
1011
20/1
21/0
2CTL
3CTL
GND
TL/F/5350-1
Top View
Order Number MM54HC4016J or MM74HC4016J, N
See NS Package J14A or N14A
Schematic Diagram
TUF/5350-2
2-77
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage {Vcel
Operating Conditions
-0.5 to +15V
DC Control Input Voltage (VIN)
-1.5toVcc+1.5V
Supply Voltage (Vcel
DC Switch 110 Voltage (VIO)
-0.5 to Vcc+0.5V
DC Input or Output Voltage
(VIN, VOUT)
Clamp Diode Current (11K, 10K)
±20mA
DC Output Current, per pin (lOUT)
±25mA
DC Vee or GND Current, per pin (Icel
±50mA
- 65·C to + 150·C
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temp.
Operating Temp. Range
MM74HC
MM54HC
Max
12
Units
V
0
Vee
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
(TAl
Input Rise or Fall Times
(tr, ttl
Vee=2.0V
Vee = 4.5V
Vee=6.0V
500mW
(TU (Soldering 10 seconds)
Min
2
260·C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25"C
Typ
74HC
54HC
TA= -40 to 85"C TA= -55to 125"C Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
9.0V
12.0V
1.5
3.15
6.3
8.4
1.5
3.15
6.3
8.4
1.5
3.15
6.3
8.4
V
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
9.0V
12.0V
0.3
0.9
1.8
2.4
0.3
0.9
1.8
2.4
0.3
0.9
1.8
2.4
V
V
V
V
RON
Maximum 'ON' Resistance VCTL =VIH,ls=1.0 rnA 4.5V 100
(See Note 5)
9.0V
50
Vls=VcctoGND
(Figure 1)
12.0V 30
170
85
70
200
105
85
220
120
100
2.0V 100
40
VCTL =VIH,ls=1.0mA 4.5V
9.0V
35
VIS=VCC or GND
(Figure 1)
12.0V 20
180
80
60
40
215
100
75
60
240
120
80
70
15
10
10
20
15
15
20
15
15
n
n
n
n
n
n
n
n
n
n
RON
Maximum 'ON' Resistance VCTL =VIH
Matching
Vls=VcctoGND
4.5V
9.0V
12.V
liN
Maximum Control
Input Current
VIN = Vcc or GND
6.0V
±0.1
±1.0
±1.0
p.A
liZ
Maximum Switch 'OFF'
Leakage Current
Vos=Vce or GND
Vls=GNDorVee
VCTL = VILCFigure 2)
6.0V
9.0V
12.0V
±60
±80
±100
±600
±800
±1000
±600
±800
±1000
nA
nA
nA
liZ
Maximum Switch 'ON'
Leakage Current
Vos=VceorGND
6.0V
9.0V
12.0V
±40
±50
±60
±150
±200
±300
±150
±200
±300
nA
nA
nA
Maximum Quiescent
Supply Current
VIN = Vec or GND
IOUT=O p.A
6.0V
9.0V
12.0V
2.0
4.0
8.0
20
40
·80
40
80
160
p.A
p.A
p.A
Icc
VeTL =VIH
(Figure 3)
10
5
5
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI"C from 65"C to 85"C; ceramic "J" package: -12 mWrc from 100"C to 125"C.
Note 4: For a power supply of 5V ± 10% the worst case on resistances (RON) occurs for HC at4.5V. Thus the 4.5V values should be used when designing with
this supply. Worst case VIH and VIL occur at Vee~ 5.5V and 4.5V respectively. (The VIH value at5.5V is 3.85V.) The worst case leakage current occur for CMOS al
the higher voltage and so these values should be used.
Note 5: At supply vollages (Vee-VEE) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended thai these
devices be used to transmit digital only when using these supply voltages.
2-78
AC Electrical Characteristics
Symbol
Parameter
Vee = 2.0V-12.0V, CL = 50 pF (unless otherwise specified), (Notes 6 and 7)
Vee
Conditions
TA=25"C
Guaranteed Limits
Typ
tpHL, tpLH Maximum Propagation
Delay Switch In to
Out
54HC
74HC
TA= -40 to 85"C TA= -55 to 125"C Units
2.0V
4.5V
9.0V
12.0V
25
5
4
3
50
10
8
7
62
13
12
11
75
15
14
13
ns
ns
ns
ns
tpZL, tpZH Maximum Switch Turn
"ON" Delay
RL =1 kn
2.0V
4.5V
9.0V
12.0V
32
8
6
5
100
20
12
10
125
25
15
13
150
30
18
15
ns
ns
ns
ns
tpHZ, tpLZ Maximum Switch Turn
"OFF" Delay
RL = 1 kn
2.0V
4.5V
9.0V
12.0V
45
15
10
8
168
36
32
30
210
45
40
38
252
54
48
45
ns
ns
ns
ns
Minimum Frequency
RL = 600n, VIS = 2Vpp
Response (Figure 7)
at (Vce/2)
20 log (VOS/VIS) = -3 dB (Notes 6 & 7)
4.5V
9.0V
40
100
MHz
MHz
Control to Switch
Feedthrough Noise
(Figure 8)
RL = 600n, F = 1 MHz
CL = 50 pF
(Notes 7 & 8)
4.5V
9.0V
100
250
mV
mV
Crosstalk Between
any Two Switches
(Figure 9)
RL = 600n, F = 1 MHz
4.5V
9.0V
-52
-50
dB
dB
Switch OFF Signal
Feedthrough
Isolation
(Figure 10)
RL = 600n, F = 1 MHz
VCTL = VIL
(Notes 7 &8)
4.5V
9.0V
-42
-44
dB
dB
Sinewave Harmonic
Distortion
(Figure 11)
RL = 10 kn, CL = 50 pF,
F = 1 kHz
VIS = 4Vpp 4.5V 0.013
VIS = 8Vpp 9.0V 0.008
%
%
THD
CIN
Maximum Control
Input CapaCitance
5
pF
CIN
Maximum Switch
Input Capacitance
15
pF
CIN
Maximum Feedthrough
Capacitance
VeTL =GND
5
pF
CPD
Power Dissipation
CapaCitance
(per switch)
15
pF
Note 6:
Adjust 0 dBm for F = 1
kHz
(Null RLIRON Attenuation)
Note 7: VIS is centered at Vcc/2
Note 8:
Adjust input for 0 dBm
2·79
AC Test Circuits and Switching Time Waveforms
Vee
Ven =Vee - - - - - - ,
VeTL=OV - - - - - . ,
liD
VIS
1 DF 4
SWITCHES
011
AMMETER
t-....--Vos
GND
1"
1 DF 4
SWITCHES
Vls=GND OR Vee
0 / 1 1 - - - - Vos=VeeORGND
GND
":'
~---i~t----~
TLIF15350-4
FIGURE 2. "OFF" Channel Leakage Current
TLIF15350-3
FIGURE 1. "ON" Resistance
Vee
Vrn-VIH _ _ _--.,
AMMETER
CONTROL
Vee
1 OF 4
SWITCHES
Vls=Vee
TOGND
O/lt------
Vas (OPIN)
GND
TLIFIS350-S
FIGURE 3. "ON" Channel Leakage Current
VeTL=VIH
Vee
VIS
OV
VIS
110
vos
":'
J
VOH
CL
Vos
50 PF
VOL
TLIFI53S0-7
TLIFIS3S0-6
FIGURE 4. tpHL. tpLH Propagation Delay Time Signal Input to Signal Output
VeTL-----'
Vee
VIS=OV
IpU
IPZL
RL
lK
VCTLvee~
I-+--Vos
T
v::~PZL
90%
CL
50 PF
Vas
VOL
O%
~
OV~pu
Voo
10%
VOL
TLIFIS3S0-9
TLIFIS3S0-B
FIGURE 5. tPZL. tpLZ Propagation Delay Time Control to Signal Output
2·80
.-----------------------------------------------------------------,~
~
U1
AC Test Circuits and Switching Time Waveforms (Continued)
:::c
""
o
IpZH
VeTL----.
~
Vee
V,s=Vee
Vos
"I_
CL
50pF
RL
1 kU
""c
.....
IpHZ
OV~tPZH
VOH
ee~
Voo
~
~
v::~r:%
ov·
....
:::c
""
o
•
Vcel 2
TL/F/5350-11
TL/F/5350-10
FIGURE 6. tpZH. tpHZ Propagation Delay Time Control to Signal Output
Vee
CONTROL
IN/OUT
OUT/IN
t - -.....- .......-
GND
Vos
50pF
I
SODA
=
Vcc /2
TLlF/5350-20
FIGURE 7. Frequency Response
tr =6ns
VCTL----...,
If=6ns
Vee;----t-~---':Ij..
OV---~
V,s
Vos
RIM
tk
Vce l2
RL
lOkU
Vecl2
J
CL
50
PF
Vos
- -.. .·y---.
.
. . .F
+
CROSSTALK
t
TLlF/5350-13
TLlF/5350-12
FIGURE 8. Crosstalk: Control Input to Signal Output
2-81
~
.......
--~
to"!.
OV
V
""c
.....
m
....
U)
~
o
'-~----------------------~------------------------------------------------------.
AC Test Circuits and Switching Time Waveforms (Continued)
:::E:
r:!
::E
::E
......
....
=
VCTL(l) Vee - - - . . ,
U) ,
~
o
:::E:
Boon
CONTROL
Vee
-Jo/O""'-~IN/OII\~I~~:ESOIIT/INI-""-- VaSil)
"II'
Ln
GNO
::E
::E
":'
V,SI'I
TL/F/5350-l4
TLlF/5350-l5
Vee
VeTL(2)=OV-----,
Vee
INIOIIT S~I~~:ES OIlTIINII---t_- VOSIII
VISII) = OV
GNO
Boon
TL/F/5350-l6
FIGURE 9. Crosstalk Between Any Two Switches
FIN IS A SINE WAVE
F'N IS A SINE WAVE
CONTROL
600,n
CONTROL Vee
IN/OUT
OUT/IN
t - -....--1~ Vas
GND
SOOll.
OUT/INt--....- -..... Vas
IN/OUT
GND
50pF
I
.....-
Vcc /2
......" T " " - -... 10k,n
50pF
VCC /2
TL/F/5350-2l
I
TL/F/5350-22
FIGURE 10. Switch OFF Signal Feedthrough Isolation
FIGURE 11. Sinewave Distortion
2·82
Typical Performance Characteristics
Typical "On" Resistance
Typical Frequency Response
160
0.0
t
140
S
tj
:z:
~
i!i
'"Z
?
+
"l 1
J
-1.0
120
100
'"
~
-2.0
z
80
A
60
40
/
/'"
Vcc=9.0V -
{:
a
~
=>
f.( "\J
-3.0
Vcc =9.0V -
~~~
-4.0
~
Vee= 12.0V
a
=1
~
Vcc=4.5V
,...,
20
J
i\
I
i'--..
VCC=4.5V~
4
6
8
10
1M
lOOK
12
10M
fRE~UENCY
INPUT VOLTAGE (V)
TLlF15350-19
TLIF15350-23
Typical Crosstalk Between
Any Two Switches
-30
h+
-35
#~-
-40
Vee=9.0~
2
-45
IJ
~
~>0
-50
-60
-65
-70
V
Vcc =4.5V
j
-55
L
f'
~
lOOK
lOOt.{
(Hz)
1M
10M
100M
fREOUENCY (Hz)
TLIF15350-24
2-83
~
an
..,.o
o
r----------------------------------------------------------------------------,
National
_
PRELIMINARY
Semiconductor
Corporation
..,.
.....
:::J:
\ ' - - _ ----'j
J
microCMOS
:E
:E
~
an
o
MM54HC4051/MM74HC4051
..,. a. Channel Analog Multiplexer
o
:::J:
..,.an MM54HC4052/MM74HC4052
:E Dual4-Channel Analog Multiplexer
:E
...... MM54HC4053/MM74HC4053
N
an
o..,. Triple 2-Channel Analog Multiplexer
o
..,. General Description
.....
:::J:
:E
:E
......
N
an
o
..,.
o
:::J:
..,.
an
:E
:E
......
.....
..,.oan
o
..,.
.....
:::J:
:E
:E
......
.,...
an
o..,.
o
..,.
:::J:
an
:E
:E
These multiplexers are digitally controlled analog switches
implemented in microCMOS Technology, 3.5 micron silicon
gate powell CMOS. These switches have low "on" resistance and low "off" leakages. They are bidirectional
switches, thus any analog input may be used as an output
and vice-versa. Also these switches contain linearization circuitry which lowers the on resistance and increases switch
linearity. These devices allow control of up to ± 6V (peak)
analog Signals with digital control signals of 0 to 6V. Three
supply pins are provided for Vee, ground, and VEE. This
enables the connection of 0-5V logic signals when
Vee=5V and an analog input range of ±5V when
VEE=5V. All three devices also have an inhibit control
which when high will disable all switches to their off state.
All analog inputs and outputs and digital inputs are protected from electrostatic damage by diodes to Vee and ground.
MM54HC4051/MM74HC4051: This device connects together the outputs of 8 switches, thus achieving an 8 channel Multiplexer. The binary code placed on the A, S, and C
select lines determines which one of the eight switches is
"on", and connects one of the eight inputs to the common
output.
a pair of 4-channel multiplexers. The binary code placed on
the A, and S select lines determine which switch in each 4
channel section is "on", connecting one of the four inputs in
each section to its common output. This enables the implementation of a 4-channel differential multiplexer.
MM54HC4053/MM74HC4053: This device contains 6
switches whose outputs are connected together in pairs,
thus implementing a triple 2 channel multiplexer, or the
equivalent of 3 single-pole-double throw configurations .
Each of the A, S, or C select lines independently controls
one pair of switches, selecting one of the two switches to be
"on".
Features
• Wide analog input voltage range: ±6V
• Low "on" resistance: 50 typo (Vee-VEE=4.5V)
30 typo (Vee-VEE=9V)
• Logic level translation to enable 5V logic with ± 5V
analog signals
• Low quiescent current: 80 /LA maximum (74HC)
• Matched Switch characteristic
MM54HC4052/MM74HC4052: This device connects together the outputs of 4 switches in two sets, thus achieving
Connection Diagrams
Dual-In-Line Packages
IN/OUT
Vee
V2
VI
IN/OUT
YO
Y3
Vee
A
zx--Tx"
OUT/IN
x
IN/OUT
DX'"Tx'
A
13
I
Y4
4
Y6 OUT/IN Y7
INiOiiT
Y5
INiOiiT
INH
V,,
I
OV2YYlYIY
INiOuT OUT/IN INiOiiT
TLlF/5353-1
Top View
INH
VEE
IN/OUT
TLlFf5353-3
TL/Ff5353-2
Top View
Order Number MM54HC4051J, MM54HC4052J, MM54HC4053J,
MM74HC4051J, N, MM74HC4052J, N or MM74HC4053J, N
See NS Package J16A or N16E
2-84
Top View
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
Supply Voltage (Veel
Supply Voltage (VEE)
Supply Voltage (Veel
-0.5 to +7.5V
+0.5 to -7.5V
Control Input Voltage (VIN)
Switch 1/0 Voltage (VIa)
Clamp Diode Current (11K. 10K)
Output Current. per pin (lOUT)
±25mA
±50mA
-65·C to + 150·C
Vee or GND Current. per pin (Ieel
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temp. (TLl (Soldering 10 seconds)
Min
2
Supply Voltage (VEE)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
-1.5 to Vee + 1.5V
VEE-0.5 to Vee+0.5V
±20mA
Input Rise or Fall Times
(tr• tf)
500mW
260·C
3:
3:
U1
Max
6
-6
0
0
Vee
Units
V
:r:
o"'"
V
V
....
.....
3:
3:
-40
-55
+85
+125
·C
·C
Vee=2.0V
Vee=4.5V
Vee=S.OV
1000
500
400
ns
ns
ns
.....
:r:
o"'"
o
........."'"
U1
3:
3:
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
U1
VEE
Vee
T =25.C
74HC
54HC
A
TA= -40 to 85·C TA= -55 to 125·C Units
Typ
VIH
VIL
RON
Guaranteed Limits
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
200
100
90
250
125
112
300
150
135
GND 2.0V 100 230
VeTL =VIH.ls=I.0 mA GND 4.5V 40 110
-4.5V 4.5V 20
90
Vls=VeeorVEE
-6.0V 6.0V 15 80
(Figure 1)
290
138
110
100
350
165
135
120
15
10
10
20
15
15
20
15
15
n
n
n
n
n
n
n
n
n
n
±0.1
±1.0
±1.0
/LA
±60
±100
±600
±1000
±600
±1000
nA
nA
RON
Maximum "ON"Resistance
Matching
VeTL =VIH
Vls=VeetoGND
liN
Maximum Control
Input Current
VIN=VeeorGND
Vcc=2-6V
liZ
Maximum Switch "OFF"
Leakage Current
(Switch Input)
Vas = Vee or GND
Vls=GNDorVce
VINH=VIH (Figure 2)
liZ
Maximum Switch
"ON" Leakage
Current
GND 4.5V 10
-4.5V 4.5V 5
-6.0V 6.0V 5
o
"'"
o
....3:
I\)
2.0V
4.5V
6.0V
VeTL =VIH.ls=I.0 mA GND 4.5V 40
-4.5V 4.5V 30
VIS=VeetoVEE
-S.OV 6.0V 20
(Figure 1)
:r:
"'"
U1
Minimum High Level
Input Voltage
Maximum "ON" Resistance
(See Note 5)
"'o"
U1
3:
.....
:r:
o"'"
"'o"
U1
.....
I\)
3:
3:
U1
:r:
"'"
o
"'o"
U1
Co)
.....
3:
3:
:i::!
:r:
o
"'o"
U1
Co)
GND 6.0V
-6.0V 6.0V
Vos=Vec or GND
HC4051 VINH=VIL
(Figure 3)
GND 6.0V
-6.0V 6.0V
/LA
/LA
Vas = Vee or GND
HC4052 VINH=VIL
(Figure 3)
GND 6.0V
-6.0V S.OV
/LA
/LA
GND S.OV
Vas = Vee or GND
-6.0V 6.0V
HC4053 VINH=VIL
(Figure 3)
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
/LA
/LA
Nole 2: Unless otherwise specified all voltages are referenced to ground.
Nota 3: Power Dissipation temperature derating - plastic "N·' package: -12 mWI"C from 65°C to 85°C; ceramic "J" package: -12 mW/oC from 100°C to 125°C.
Note 4: For a power supply of 5V ± 10% the worst case on resistances (RON) occurs lor HC at4.5V. Thus the 4.5V values should be used when designing with
this supply. Worst case VIH and VIL occur at Vcc= 5.5V and 4.5V respectively. (The VIH value at5.5V is 3.85V.) The worst case leakage current occur lor CMOS at
the higher voltage and so the 5.5V values should be used.
Nole 5: At supply voltages (Vee-VEE) approaching 2V the analog switch on resistance becomes extremely non·linear. Therefore it is recommended that these
devices be used to transmit digital only when using these supply voltages.
2-85
DC Electrical Characteristics (Note 4) (Continued)
Symbol
Parameter
TA=25'C
VEE Vee
Conditions
Guaranteed Limits
Typ
Maximum Switch
"OFF" Leakage
Current (Common
Pin)
liZ
ICC
74HC
54HC
TA= -40 to 85'C TA= -55 to 125'C Units
Vos=VccorGND GND 6.0V
HC4051 Vls=GNDorVcc -6.0V 6.0V
VINH=VIH
",A
/LA
VOS=VCCorGND GND 6.0V
HC4052 VIS=GNDorVCC -6.0V 6.0V
VINH=VIH
/LA
/LA
Vos=VCCorGND GND 6.0V
HC4053 VIS=GNDorVCC -6.0V 6.0V
VINH=VIH
/LA
",A
Maximum Quiescent
Supply Current
VIN=VccorGND
IOUT=O",A
GND 6.0V
-6.0V 6.0V
8
16
80
160
160
320
",A
",A
AC Electrical Characteristics Vcc=2.0V-6.0V VEE = OV-6V, CL =50 pF (unless otherwise specified)
Symbol
Parameter
Conditions
VEE
Vee
TA=25'C
Maximum Propagation
Delay Switch In to
Out
tpZL, tpZH
Maximum Switch Turn
"ON" Delay
tpHZ, tpLZ
fMAX
Units
Guaranteed Limits
Typ
tpHL, tpLH
74HC
54HC
TA=-40t085'C TA= -55 to 125'C
GND
GND
-4.5V
-6.0V
2.0V
4.5V
4.5V
6.0V
25
5
4
3
GND
GND
-4.5V
-6.0V
2.0V
4.5V
4.5V
6.0V
92
18
16
15
ns
ns
ns
ns
Maximum Switch Turn
"OFF" Delay
GND
GND
-4.5V
-6.0V
2.0V
4.5V
4.5V
6.0V
65
28
18
16
ns
ns
ns
Minimum Switch
Frequency Response
20 log {VllVo)=3 dB
GND 4.5V
-4.5V 4.5V
30
35
MHz
MHz
180
mVp_p
RL =1 kO
Cross Talk Control
to Switch
(Figure 7)
-4.5V 4.5V
Cross Talk Between
any Two Switches
(Frequency at - 50 dB)
(Figure 8)
-4.5V 4.5V
Feed Through, Switch
Input to Output
F=5MHz
F=10MHz
CIN
Maximum Control
Input Capacitance
CIN
Maximum Switch
Input Capacitance
CIN
Maximum Feedthrough
Capacitance
50
10
8
7
62
13
12
11
75
15
14
13
ns
ns
ns
ns
MHz
dB
dB
5
Input
4051 Common
4052 Common
4053 Common
2-86
10
10
10
pF
15
90
45
30
pF
5
pF
Truth Tables
'4051
'4053
'4052
"ON"
Input
Inputs
Input
"ON" Channels
Inh
C
B
A
Channel
Inh
B
A
X
V
H
L
L
L
L
L
L
L
L
X
X
X
None
X
X
None
None
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
H
L
L
L
L
L
L
H
H
L
H
L
H
OX
1X
2X
3X
OY
1Y
2Y
3Y
"ON" Channels
Inh C B A
H
L
L
L
L
L
L
L
L
X X X
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
C
a
b
None None None
CX
CX
CX
CX
CY
CY
CY
CY
BX
BX
BY
BY
BX
BX
BY
BY
AX
AY
AY
AY
AY
AY
AY
AY
AC Test Circuits and Switching Time Waveforms
Ven ~VIH _ _ _--,
(Internal)
Ven ~VIL
(Internal) - - - - - ,
VIS--.....-IV
TEST
SWITCH
011
t-.....- -
VDS
AMMETER
VEE
TEST
SWITCH
VIS ~ GNO DR Vee
......- - - Vos=VeeOR GND
VEE
'-------(-1-----'
TLIF15353-4
TLIF15353-5
FIGURE 1. "ON" Resistance
FIGURE 2. "OFF" Channel Leakage Current
Vos (OPEN)
TLIFI5353-6
FIGURE 3. "ON" Channel Leakage Current
Vee
v,s
OV
Vos
Voo
Vos
OV
TLIF15353-7
FIGURE 4. tpHL, tpLH Propagation Delay Time Signal Input to Signal Output
2-87
~ .-----------------------------------------------~------------------------------~
an
~
o
AC Test Circuits and Switching Time Waveforms
(Continued)
:c
'Oil'
.....
::::Ii!
::::Ii!
.....
IpZL
VCC~IPZL
50%
~
an
~
~O%
OV~'ZL
Vos
o
:c
'Oil'
VDD
-I~
OV
VDD~
90%
10%
an
::::Ii!
::::Ii!
'N
VOL
VOL
TLlF/5353-B
FIGURE 5. tPZL. tpLZ Propagation Delay Time Control to Signal Output
8
'Oil'
o
:c
'Oil'
IpZH
VCTL
tpHZ
VCC~
50%
.....
::::Ii!
::::Ii!
.....
I-+--...-Vo.
V
cc
an
~
~~
OV~ZH
v::~r:%
OV
OV
VOH
N
~5D%
10%
~
o
TL/F/5353-9
:c
'Oil'
an
::::Ii!
::::Ii!
'an
....
FIGURE 6. tpZH. tpHZ Propagation Delay Time Control to Signal Output
VCTL----..,
1,=60'
o
'Oil'
o
:c
'Oil'
Vc
~
VEE
RL
60011
80011
VEE
"::"
J
CL
50
j
PF
Vos
Y'
"::"
F
+
CROSSTALK
t
TLlF/5353-10
o
:c
'Oil'
an
::::Ii!
::::Ii!
OV
Vos
INIOUT SWITCHES OUTliN
RIN
::::Ii!
:::i
an
10F4
VIS
.....
.....
....
VOD
FIGURE 7. Crosstalk: Control Input to Signal Output
VCTL(1I= vcc---.,
600n
t-.....-VOS(ll
OV
1/1
y
11--........-VOS(2)
600n .....-....;.!j~-...I
TLlF/5353-11
FIGURE 8. Crosstalk Between Any Two Switches
2·88
Logic Diagrams
MM54HC4051/MM74HC4051
CHANNEL INIOUT
Vee
Y1
Y&
Y5
Y4
Yl
YZ
YI
YO
BINARY
TO
I OF B
DECODER
WITH
INHIBIT
LOGIC
LEVEL
CONVERSION
COMMON
OUTIIN
INH
GND
VEE
TLlF/5353-19
MM54HC4052/MM74HC4052
X CHANNELS INIOUT
I
\
Xl
Xl
XI
XO
Vee
COMMON X
OUTIIN
BINARY
TO
1 OF 4
DECODER
WITH
INHIBIT
LOGIC
LEVEL
CONVERSION
COMMON Y
OUTIIN
YO
GND
Y1
YZ
Y3
YCHANNELS INIOUT
VEE
TL/F/5353-20
MM54HC4053/MM74HC4053
BINARYTO
1 OF 2
DECODERS
WITH
CONVE\:ON r - - -......- - - , INHIBIT
LOGIC
LEVEL
INIOUT
I
CY
ex
\
BY
BX
AY
AX
/
INH
TL/F/5353-21
2-89
~
In
..,.
o
o
r---------------------------------------------------------------------------------,
Typical Performance Characteristics
:::E:
~
::::!E
Typical "On" Resistance
vs Input Voltage
90
::::!E
......
75
In
60
o
45
11
~ Vcc~4.~V
~
o
..,.
..,.
3D
::::!E
15
:::E:
In
::::!E
.....
~
o
..,.
o
-6
~v
.
"
~~ ~j"9.0V
...
I-vc~t--
111
-4 -2
0
2
4
INPUT VOLTAGE (VOLTS)
Vee
= -VEE
:::E:
~
::::!E
::::!E
~
In
o
..,.
o
:::E:
..,.
In
::::!E
::::!E
......
.,..
In
o
..,.
o
:::E:
..,.
::::!E
"""
::::!E
......
.,..
In
..,.o
o
..,.
:::E:
In
::::!E
:E
2-90
TL/F/5353-18
NatiOnal
~ Semiconductor
Corporation
microCMOS
MM54HC4066/MM74HC4066
Quad Analog Switch
General Description
Features
These devices are digitally controlled analog switches utilizing microCMOS Technology, 3.5 micron silicon gate P-well
CMOS. These switches have low "on" resistance and low
"off" leakages. They are bidirectional switches, thus any
analog input may be used as an output and visa-versa. Also
the '4066 switches contain linearization circuitry which lowers the "on" resistance and increases switch linearity. The
'4066 devices allow control of up to 12V (peak) analog signals with digital control signals of the same range. Each
switch has its own control input which disables each switch
when low. All analog inputs and outputs and digital inputs
are protected from electrostatic damage by diodes to Vee
and ground.
•
•
•
•
•
•
Connection Diagram
Truth Table
Typical switch enable time: 15 ns
Wide analog input voltage range: 0-12V
Low "on" resistance: 30 typo ('4066)
Low quiescent current: 80 /J-A maximum (74HC)
Matched switch characteristics
Individual switch controls
Dual-In-Line Package
vee
11/0
lCTL
10/1
4CTL
ZO/I
41/0
ZI/O
40/1
ZCTL
30/1
3CTL
31/0
Input
Switch
CTL
110-0/1
L
H
"OFF"
"ON"
GNO
TLIF/5355-1
Top View
Order Number MM54HC4066J or MM74HC4066J, N
See NS Package J14A or N14A
Schematic Diagram
0/1
CONTROL
TLIF/5355-2
2-91
Absolute Maximum Ratings (Noles 1 & 2)
Operating Conditions
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Vollage (Veel
Supply Vollage {Veel
DC Conlrollnpul Vollage (VIN)
DC Swilch I/O Vollage (VIO)
-1.510 Vee + 1.5V
VEE-0.510 Vee+0.5V
Clamp Diode Currenl (11K. 10K)
±20mA
DC OUlpul Currenl. per pin (lOUT)
±25mA
DC Vee or GND Currenl. per pin (Ieel
±50mA
Siorage Temperalure Range (TSTG)
Power Dissipation (PD) (Note 3)
DC Inpul or Oulpul Vollage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
-0.510 + 15V
Min
2
Max
12
Units
V
0
Vee
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
Inpul Rise or Fall Times
(Ir• If)
Vee=2.0V
Vee=4.5V
Vee=9.0V
-65'C 10 + 150'C
500mW
Lead Temperature (TLl
(Soldering 10 seconds)
260'C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25'C
74HC
54HC
TA= -40 to 85'C TA= -55to 125'C Units
Guaranteed Limits
Typ
VIH
Minimum High Level
Inpul Voltage
2.0V
4.5V
9.0V
12.0V
1.5
3.15
6.3
8.4
1.5
3.15
5.3
8.4
1.5
3.15
6.3
8.4
V
V
V
V
VIL
Maximum Low Level
Inpul Vollage
2.0V
4.5V
9.0V
12.0V
0.3
0.9
1.8
2.4
0.3
0.9
1.8
2.4
0.3
0.9
1.8
2.4
V
V
V
V
RON
Maximum "ON" Resislance VCTL =VIH. Is=I.0 mA
(See Note 5)
Vls=VeeloGND
(Figure 1)
4.5V
9.0V
12.0
100
50
30
170
85
70
200
105
85
220
110
90
2.0V 120
VeTL =VIH. Is=I.0 rnA 4.5V 50
9.0V 35
Vls=VeeorGND
(Figure 1)
12.0V 20
180
80
60
40
215
100
75
60
240
120
80
70
15
10
10
20
15
15
20
15
15
n
n
n
n
n
n
n
n
n
n
±0.1
±1.0
±1.0
/LA
RON
Maximum "ON" Resistance VeTL =VIH
Matching
Vls=VeetoGND
4.5V
9.0V
12.0V
10
5
5
liN
Maximum Conlrol
Input Current
VIN=VeeorGND
Vee=2-6V
liZ
Maximum Swilch "OFF"
Leakage Current
Vos = Vee or GND
Vls=GNDorVee
VCTL =VIL (Figure 2)
6.0V
9.0V
12.0V
10
15
20
±60
±80
±100
±600
±800
±1000
±600
±800
±1000
nA
nA
nA
liZ
Maximum Swilch "ON"
Leakage Currenl
Vos = Vee or GND
VeTL =VIH
(Figure 3)
6.0V
9.0V
12.0V
10
15
20
±40
±50
±60
±150
±200
±300
±150
±200
±300
nA
nA
nA
Icc
Maximum Quiescent
Supply Currenl
VIN=VeeorGND
IOUT=O /LA
6.0V
9.0V
12.0V
2.0
4.0
8.0
20
40
80
40
80
160
/LA
/LA
/LA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mW re from 6S'C to 8S'C; ceramic "J" package: -12 mWrc from 100"C to 125"C.
Note 4: For a power supply of SV ± 1 0% the worst case on resistance (RON) occurs for HC at 4.SV. Thus the 4.SV values should be used when designing with this
supply. Worst case VIH and VIL occur at VCC~ S.SV and 4.SV respectively. (The VIH value at S.SV is 3.8SV.) The worst case leakage current occurs for CMOS at the
higher voltage and so the S.SV values should be used.
Note 5: At supply voltages (Vee-VEE) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that these
devices be used to transmit digital only when using these supply voltages.
2-92
AC Electrical Characteristics
Vee = 2.0V -6.0V VEE = OV -12V, CL = 50 pF (unless otherwise specified)
Symbol
Parameter
tpHL, tpLH
Maximum Propagation
Delay Switch In to
Out
tpZL' tPZH
Maximum Switch Turn
"ON" Delay
tpHZ, tpLZ
74HC
54HC
TA = -40 to 85'C TA= -55to 125'C Units
TA=25'C
Vee
Conditions
Typ
THD
Guaranteed Limits
2.0V
4.5V
9.0V
12.0V
25
5
4
3
50
10
8
7
30
13
10
11
75
15
12
13
ns
ns
ns
ns
RL = 1 ko.
2.0V
4.5V
9.0V
12.0V
30
12
6
5
100
20
12
10
125
25
15
13
150
30
18
15
ns
ns
ns
ns
Maximum Switch Turn
"OFF" Delay
RL = 1 ko.
2.0V
4.5V
9.0V
12.0V
60
25
20
15
168
36
32
30
210
45
40
38
252
54
48
45
ns
ns
ns
Minimum Frequency
Response (Figure ?)
20 10g(VolVl) = -3 dB
RL = 6000.
VIS=2 Vpp at (Vee/2)
(Notes 6 & 7)
4.5V
9.0V
40
100
MHz
MHz
Crosstalk Between
any Two Switches
(Figure 8)
RL=6000.,F=1 MHz
(Notes? &8)
4.5V
9.0V
-52
-50
dB
dB
Peak Control to Switch
Feedthrough Noise
(Figure 9)
RL = 6000., F = 1 MHz
CL=50 pF
4.5V
9.0V
100
250
mV
mV
Switch OFF Signal
Feedthrough
Isolation
(Figure 10)
RL =6000., F=1 MHz
VIeT) VIL
(Notes 7 &8)
4.5V
9.0V
-42
-44
dB
dB
Total Harmonic
Distortion
(Figure 11)
RL =10 ko., CL =50 pF,
F=1 kHz
VIS=4 Vpp
VIS=8 Vpp
4.5V
9.0V
.013
.008
%
%
Maximum Control
Input Capacitance
5
CIN
Maximum Switch
Input Capacitance
20
pF
CIN
Maximum Feedthrough VeTL =GND
Capacitance
0.5
pF
15
pF
Power Dissipation
Capacitance
Note 6: Adiust 0 dBm for F ~ 1 kHz (Null RL/RoN Attenuation).
Note 7: VIS is centered at Vcc/2.
Note 8: Adjust input for 0 dBm.
CPD
10
10
CIN
10
pF
AC Test Circuits and Switching Time Waveforms
VeIL -VIH
I
CONTROL
VIS
I/O
T
1 OF 4
SWITCHES
011
I I
Vas
AMMETER
GND
Vls-GNO OR Vee
0:!-
-
Vce
VCll ~VIL
Vee
-0-
CONTROL
liO
Vee
1 OF 4
SWITCHES
all
Vas-Vee OR GND
GND
~
TUF/5355-3
FIGURE 1. "ON" Resistance
TL/F15355-4
FIGURE 2. "OFF" Channel Leakage Current
2-93
U) r---------------------------------------------------------------------------~
U)
o
•
Co)
AC Test Circuits and Switching Time Waveforms
::E:
•.....
::!5
VeTL - VIH - - - . . . . ,
::!5
(Continued)
vee
AMMETER
I
10F4
SWITCHES
110
t - - - - Vos
011
GND
Co)
::E:
•
Ln
::!5
::!5
TL/F/5355-5
FIGURE 3. "ON" Channel Leakage Current
VeTL = Vee
vee----+-.Jr~i""""_L
110
OV---"
.........- - - - - V o s
VOH V O O ' - - - - - + _ - - - -
Vas
OV----",
VOL
TL/F/5355-6
FIGURE 4. tpHL. tpLH Propagation Delay Time Signal Input to Signal Output
.. V::~ZL
~~
tPZL
90%
Vos
VOL
O%
~
OV~LZ
VOO
10%
VOL
TLlF/5355-7
FIGURE 5. tPZL. tpLZ Propagation Delay Time Control to Signal Output
VIS=VCC
IpHZ
tPZH
VCll
........- -....-VO$
50%
VCC~
OV~H
VOH
OV
VCC~50%
~~
v::~r:.I
VDO
.
ov-------~
10%
Vee/ 2
TL/F/5355-B
FIGURE 6. tpzH. tpHZ Propagation Delay Time Control to Signal Output
Vee
VCTL= Vcc ---"'"
GND
600.o.
Vee 12
I
50 Pf
TLlF/5355-19
FIGURE 7. Frequency Response
2·94
==
==
U1
.,..
::I:
o.,..
o
VCIL-----,
Ven
'N/OUTS~'~~:ESOUT/'NI--t~---t~-VDS
VIS
R,.
GNO
.oon
en
en
.......
RL
VDS
CROSSTALK
t
Vee/ 2
VCC f2
==
•
Boon
Vec/2
TL/F/5355-9
FIGURE 8. Crosstalk: Control Input to Signal Output
CONTROL
BOOIl
en
en
Vee
VCTLClpaVC C - - - . ,
Vee
.-""~-IIN/OUT Sv:.~~:ESoUT/lNI-"'--V"'lI
At
BOOIl
ViSlll
Vccl2
VISI')
Vee
CONTROL
Vee
IN/OUT n:'~~:ESOUTlINI-"'--'V"121
Vml2)=DV
BOOIl ....._....;;GN"'O_ _.J
RL
BOOIl
VcC/ 2
TLlF/5355-1O
FIGURE 9. Crosstalk Between Any Two Switches
F,N IS A SINE WAVE
Vrn = Vee - - - - . ,
I -....- -....
F,N IS A SINE WAVE
VCTl= GND - - - - ,
I-....--.-Vos
Vos
SOOD.
TLlF/5355-21
TLlF/5355-20
FIGURE 10. Switch OFF Signal Feedthrough Isolation
FIGURE 11. Sinewave Distortion
Typical Performance Characteristics
Typical Crosstalk Between
Any Two Switches
Typical "ON" Resistance
-30
100
-35
s:
BO
~
BO
~
40
~
-
;,
P
R
-40
20
o
o
I-/" .......-
Vce=4.5V
--
I-- I-Vee =9.0V
......
S
~
-45
~
-so
......
~
-BO
-65
vee= 12.0V
10
INPUT VOLTAGE (V)
12
-70
,
~
~
#
;
VCC=9.0V~ -
-4.0
1M
_\
/\
-2.0
~ -3.0
'f'
lOOK
Vcc=4.5V \
S
ff Vcc=4.5V
\.
i'o..
-1.0
Vee=9.OV
-55
Typical Frequency Response
0.0
~
.....
10M
FREQUENCY (Hz)
100M
1
lOOK
IU
10M
100U
FREQUENCY (Hz)
TLlF/5355-18
2-95
.,..==......
::I:
o.,..
o
.... ,-------------------------------------------------------------------------,
~
C")
-.:r
o
:::c
-.:r
"
NatiOnal
~ Semiconductor
PRELIMINARY.4-....
Corporation
4.A
\
~
)
microCMOS
:::E
:::E
.....
.... MM54HC4316/MM74HC4316
~
C")
-.:r
o
:::c
-.:r
an
:::E
:::E
Quad Analog Switch with Level Translator
General Description
Features
These devices are digitally controlled analog switches implemented in microCMOS Technology, 3.5 micron silicon
gate P-well CMOS. These switches have low "on" resistance and low "off" leakages. They are bidirectional
switches, thus any analog input may be used as an output
and vice-versa. Three supply pins are provided on the '4316
to implement a level translator which enables this circuit to
operate with 0-6V logic levels and up to ± 6V analog switch
levels. The '4316 also has a common enable input in addition to each switch's control which when low will disable all
switches to their off state. All analog inputs and outputs and
digital inputs are protected from electrostatic damage by
diodes to Vee and ground.
• Typical switch enable time: 20 ns
• Wide analog input voltage range: ± 6V
• low "on" resistance: 50 typo (VCC-VEE=4.5V)
30 typo (VCC-VEE=9V)
• low quiescent current: 80 p.A maximum (74HC)
• Matched switch characteristics
• Individual switch controls plus a common enable
Connection and Logic Diagrams
Truth Table
Dual-In-Line Package
1cn 4cn
41/0 40/1
1110
30/1
3CTL
Switch
Inputs
31/0
En'
En
CTL
1/0-0/1
H
l
l
X
"OFF"
"OFF"
"ON"
l
H
GND
TL/F/5369-1
Top View
Order Number MM54HC4316J or MM74HC4316J,N
See NS Package J 16A or N16E
....--+-00/1
cn o------II"'~--"'.... ~~J
TUF/5369-2
2-96
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
Supply Voltage (Veel
Supply Voltage (VEE)
Supply Voltage (Veel
DC Control Input Voltage (VIN)
DC Switch I/O Voltage (Via)
Clamp Diode Current (11K. loKl
DC Output Current. per pin (lOUT)
-0.5 to + 7.5V
+0.5to -7.5V
Supply Voltage (VEE)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
-1.5 to Vee+ 1.5V
VEE-0.5 to Vee+0.5V
±20mA
DC Vee or GND Current. per pin (Ieel
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temperature (Td
(Soldering 10 seconds)
±25mA
±50mA
- 65"C to + 150"C
Min
2
0
Max
6
-6
Units
V
V
0
Vee
V
-40
-55
+85
+125
"C
"C
1000
500
400
250
ns
ns
ns
ns
Input Rise or Fall Times
(tr• ttl
Vee=2.0V
Vee=4.5V
Vee=6.0V
Vee = 12.0V
500mW
260"C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VEE Vee
TA=25"C
Typ
54HC
74HC
TA= -40 to 85"C TA= -55 to 125"C Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
Vil
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
RON
Minimum "ON" Resistance VeTl =VIH. Is=1.0 mA GND 4.5V 100
(See Note 5)
-4.5V 4.5V 40
VIS = Vee to VEE
(Figure 1)
-6.0V 6.0V 30
170
85
70
200
105
85
220
110
90
GND 2.0V 100
VCTl =VIH. Is=1.0 mA GND 4.5V 40
-4.5V 4.5V 50
VIS = Vee or VEE
(Figure 1)
-6.0V 6.0V 20
180
80
60
40
215
100
75
60
240
120
80
70
15
10
10
20
15
15
20
15
15
n
n
n
n
n
n
n
n
n
n
RON
Maximum "ON" Resistance VCTl =VIH
Matching
VIs=Vee to GND
GND 4.5V 10
-4.5V 4.5V 5
-6.0V 6.0V 5
liN
Maximum Control
Input Current
VIN=Vee or GND
GND 6.0V
±0.1
±1.0
±1.0
/LA
liZ
Maximum Switch "OFF"
Leakage Current
Vos=VccorGND
VIS= GND or Vee
VeTl =VIl (Fig 2)
GND 6.0V
-6.0V 6.0V
±60
±100
±600
±1000
±600
±1000
nA
nA
liZ
Maximum Switch "ON"
Leakage Current
Vas = Vee or GND
VeTl=VIH
(Figure 3)
GND 6.0V
-6.0V 6.0V
±40
±60
±150
±300
±150
±300
nA
nA
2.0
40
GND 6.0V
20
Maximum Quiescent
VIN = Vee or GND
/LA
-6.0V 6.0V
Supply Current
8.0
80
160
IOUT=O /LA
/LA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mW I'C from 6S'C to 8S'C; ceramic "J" package: -12 mWI'C from 1OO'C to 12S·C.
Note 4: For a power supply of SV ± 10% the worst case on resistances (RON) occurs for HC at4.SV. Thus the 4.SV values should be used when designing with
this supply. Worst case VIH and VIL occur at Vee = S.SV and 4.SV respectively. (The VIH valUe at S.SV is 3.BSV.) The worst case leakage current occurs for CMOS
at the higher voltage and so the S.SV values should be used.
Note 5: At supply voltages (Vee-VEE! approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that these
devices be used to transmit digital only when using these supply voltages.
ICC
2-97
AC Electrical Characteristics
Vee = 2.0V-6.0V, VEE = OV-6V, CL = 50 pF (unless otherwise specified)
Symbol
Parameter
74HC
54HC
TA= -40°C TA= -55°C
to +85"C
to + 125°C Units
Typ
Guaranteed Limits
VEE
Vee
GND
GND
-4.5V
-6.0V
2.0V
4.5V
4.5V
6.0V
25
5
4
3
50
10
8
7
63
13
12
11
75
15
14
13
ns
ns
ns
ns
Conditions
tpHL, tpLH Maximum Propagation
Delay Switch In to
Out
TA= + 25°C
tpZL, tpzH Maximum Switch Turn
"ON" Delay
(Control)
RL =1 kn
GND
GND
-4.5V
-6.0V
2.0V
4.5V
4.5V
6.0V
30
20
15
14
165
35
32
30
206
43
39
37
250
53
48
45
ns
ns
ns
ns
tpHZ, tpLZ Maximum Switch Turn
"OFF" Delay
(Control)
RL =1 kn
GND
GND
-4.5V
-6.0V
2.0V
4.5V
4.5V
6.0V
45
25
20
20
250
50
44
44
312
S3
55
55
375
75
66
66
ns
ns
ns
tpZL, tPZH Maximum Switch
Turn "ON" Delay
(Enable)
GND
GND
-4.5V
-6.0V
2.0V
4.5V
4.5V
6.0V
35
20
19
18
205
41
38
36
256
52
48
45
308
62
57
54
ns
ns
ns
ns
tpLZ, tpHZ Maximum Switch
Turn "OFF" Delay
(Enable)
GND
GND
-4.5V
-S.OV
2.0V
4.5V
4.5V
6.0V
58
28
23
21
265
53
47
47
330
67
59
59
400
79
70
70
ns
ns
ns
ns
THD
Minimum Frequency
RL = 600n, VIS = 2Vpp
Response (Figure 7)
at (Vee-VEE/2)
20 log (VOSIVIS)= -3 dB (NotesS,7)
OV
4.5
-4.5V 4.5V
40
100
MHz
MHz
Control to Switch
Feedthrough Noise
(Figurel!)
RL = 600n, F = 1 MHz
CL = 50pF
(Notes 7,8)
4.5V
OV
-4.5V 4.5V
100
250
mV
mV
Crosstalk Between
any Two Switches
(Figure9j
RL = soon, F = 1 MHz
OV
4.5V
-4.5V 4.5V
-52
-50
dB
dB
Switch OFF Signal
Feedthrough
Isolation
(Figure 1{}J
RL = 600n, F = 1 MHz
VeTL = VIL,
OV
4.5V
-4.5V 4.5V
-42
-44
dB
dB
Sinewave Harmonic
Distortion
(Figure 11)
RL = 10 Kn, CL = 50 pF,
F = 1 KHz
OV
4.5V 0.013
VIS = 4Vpp
VIS = 8Vpp -4.5V 4.5V 0.008
%
%
(Notes 7, 8)
CIN
Maximum Control
Input Capacitance
5
pF
CIN
Maximum Switch
Input Capacitance
35
pF
CIN
Maximum Feedthrough
Capacitance
0.5
pF
15
pF
VeTL=GND
Power Dissipation
Capacitance
Note 6: Adjust 0 dBm fer F = 1 KHz (Null RL/Ren Attenuation).
Note 7: VIS is centered at Vee-VEE/2.
Note 8: Adjust for 0 dBm.
CPO
2-98
AC Test Circuits and Switching Time Waveforms
Vee
VeTL =VIH - - - - - .
VIS - -......--f 110
1 DF 4
SWITCHES
D/I
1-....- - Vos
1 OF 4
VIS - GND OR Vee
Vee
SWITCHES
0 / 1 1 - - - - VOl-Vee 011 GND
VEE
TLlF/5369-3
TL/F/5369-4
FIGURE 1. "ON" Resistance
FIGURE 2. "OFF" Channel Leakage Current
Vee
VeTL = VIH - - - - ,
AMMETER
Vls=Vee
TD GND
1 OF 4
SWITCHES
110
D / I I - - - - Vos
VEE
VEE
TL/F/5369-5
FIGURE 3. "ON" Channel Leakage Current
VeTL=VIH
Vee
VIS
VIS
liD
DV
Vos
VOH
VOS
VOL
Vee
TLlF/5369-6
FIGURE 4. tpHL. tpLH Propagation Delay Time Signal Input to Signal Output
tpZL
vcnvee~
vos
90%
::~PZL
VOL
TL/F/5369-7
FIGURE 5. tPZL. tpu Propagation Delay Time Control to Signal Output
2-99
....
~ r-----------------------------------------------------------------------------~
C")
tS
AC Test Circuits and Switching Time Waveforms (Continued)
::l:
j:!
IpHZ
IpZH
VCTl----'
::E
::E
V
VCC~
50%
U;
....
VOK
::l:
OV
o
Voo
V::~~%
OV~K
1-. .- - - 4....-Vos
~
~
::E
::E
CC~
OV~
10%
TLlF/5369-8
FIGURE 6. tpZH. tpHZ Propagation Delay Time Control to Signal Output
Vee
F,N
OUT/IN
t---9--.....-
VEE
' - - - - - - - - ' 600n
Ves
50pF
I
VEE
TL/F/5369-16
FIGURE 7. Frequency Response
Vcn-----,
VIS
VCC_~=_80._-,t__.Je_t-j~ 1,=80'
_1/90%
OV
INIOUT S~,~~~ESOUT/IN ....-1....- - -....--vos
VEE
RL
60011
J
-----r¥
10%
CL
50
PF
Vos
+
CROSSTALK
t
Vcc/2
TL/F/5369-9
FIGURE 8. Crosstalk: Control Input to Signal Output
Vee
VCTL(lj = Vee - - - - .
600n
CONTROL
Vee
r-ON\--IIN/OUTS~,~~:ESOUTIINI-....-VOS(l)
VEl
RL
BOOn
VlSIll
VCTLf2) = OV - - - - ,
CONTROL
VlSfll
Vee
Vee
1-....-V0S(2l
RL
lOon
TL/F/5369-10
FIGURE 9: Crosstalk Between Any Two Switches
2-100
AC Test Circuits and Switching Time Waveforms
(Continued)
Vee
Vee
VeR = Vee
r lN IS A SINE WAVE
rlN
CONTROL Vee
CONTROL Vee
IN/OUT
OUT/IN
600.0.
IS A SINE WAVE
t - -.....- -......
IN/OUT
Vas
50pr
....- - . , . . - - - - ' 600.0.
OUT/IN
1--....- -...... Vas
50 pr
~--~---~ 10k.o.
I
I
TL/F/5369-20
TL/F/5369-19
FiGURE 11. Sinewave Distortion
FIGURE 10. Switch OFF Signal Feedthrough Isolation
Typical Performance Characteristics
Typical Crosstalk Between
Any Two Switches
Typical "ON" Resistance
0.0
160
t
140
l:l
z
~
CI)
i:i
'"Z
f'
I
I.o- J
~I\.
\
vee-VEE= 4.5V\
100
\
Oi'
~
~,;'
80
J\ Vee-VEE= 4.5V
80
r/
40
20
~
-1.0
120
s:
+
~
ro
V~
2
I
Vee-VEE= 9.0V ---
-4.0
~
12
10
1M
lOOK
10M
TlIF/5369-22
TL/F/5369-21
FJ
Typical Frequency Response
-30
k+
p~-
-35
-40
~
Vee-VEE=9.0V~
V
-45
!JVee-VEE= 4.5V
:f' -50
......
'"
,;'
100M
rREQUENCY (Hz)
INPUT VOLTAGE (V)
Oi'
,
r-'
1
I
~f-,
6
\
1\
-3.0
~~
4
I
Vee-VEE= 9.0V
Vee-V EE- 12.0V
o
-2.0
j
-55
-60
-65
-70
;/
f'
~
lOOK
1M
10M
100M
rREQUENCY (Hz)
TL/F/5369-23
2·101
Section 3
Analog-to-Digital
Converters
Section 3 Contents
Analog-to-Digital Converters Definition of Terms. . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . . . . .
Analog-to-Digital Converters Selection Guide ..........................................
ADC0800 8-Bit AID Converter. ..................... ..... ... ..... .. .... ..... ..... ....
ADC0801, ADC0802, ADC0803, ADC0804, ADC0805 8-Bit /LP Compatible AID Converters..
ADC0808, ADC0809 8-Bit p.P Compatible AID Converters with 8-Channel Multiplexer. . . . . . .
ADC0811 8-Bit Serial 110 AID Converter with 11-Channel Multiplexer . . . . . . . . . . . . . . . . . . . . .
ADC0816, ADC0817 8-Bit /LP Compatible AID Converters with 16-Channel Multiplexer. . . . . .
* ADC0819 8-Bit Serial 1/0 AID Converter with 19-Channel Multiplexer. . . . . . . . . . . . . . . . . . . . .
ADC0820 8-Bit High Speed /LP Compatible AID Converter with Track/Hold Function. . . . . . . .
ADC0829/LP Compatible 8-Bit AID with 11-Channel MUX/Digitallnput.. .... .. ........ ....
ADC0831, ADC0832, ADC0834 and ADC0838 8-Bit Serial 1/0 AID Converters with
Multiplexer Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC0833 8-Bit Serial 1/0 AID Converter with 4-Channel Multiplexer . . . . . . . . . . . . . . . . . . . . . .
* ADC0841 8-Bit /LP Compatible AID Converter.. .. . .. .. .. . .. . .. .. .. .. .. .. .. . .. .. .. .. .. ..
ADC08441 ADC0848 8-Bit /LP Compatible AID Converters with Multiplexer Options ... . . . . ..
ADC08521 ADC0854 Multiplexed Comparator with 8-Bit Reference Divider. . . . . . . . . . . . . . . ..
ADC1 001, ADC1021 10-Bit /LP Compatible AID Converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ADC1005, ADC1025 10-Bit /LP Compatible AID Converters.... .......... .......... . .. ...
ADC1205, ADC122512-Bit Plus Sign /LP Compatible AID Converters. .. .. .... ....... ... ..
ADC1210, ADC1211 12-Bit CMOS AID Converters.. .. .. .. .. .. .. .. . .. . . .. .. .. .. .. . .. ...
ADC3511 31,4-Digit Microprocessor Compatible AID Converter. . . . . . . .. . . . .. . . . . . .. . .. . ..
ADC3711 3%-Digit Microprocessor Compatible AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . .
ADD3501 3'1,4-Digit DVM with Multiplexed 7-Segment Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADD3701 3%-Digit DVM with Multiplexed 7-Segment Output. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM2502, DM2503, DM2504 Successive Approximation Registers ........................
LM131A/LM131, LM231A1LM231, LM331A/LM331 Precision Voltage-to-Frequency
Converters ... . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM74C905 12-Bit Successive Approximation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
'Devices Not Covered In Last Publlcellon
3-2
3-3
3-4
3-7
3-16
3-48
3-59
3-70
3-81
3-91
3-107
3-115
3-140
3-158
3-171
3-188
3-206
3-213
3-224
3-241
3-252
3-252
3-261
3-270
3-280
3-285
3-296
cCD
~ Semiconductor
NatiOnal
S·
::;:
O·
Corporation
::::I
-
o
Definition Of Terms
AID Converters
'..,.;}
3
Ic
......
Conversion Time: The time required for a complete measurement by an analog-to-digital converter.
DC Common-Mode Error: This specification applies to
ADCs with differential inputs. It is the change in the output
code that occurs when the analog voltages on the two inputs are changed by an equal amount. It is expressed in
LSBs.
Differential Nonlinearity: Ideally, any two adjacent digital
codes correspond to measured analog voltages that are exactly one LSB apart. Differential non-linearity is a measure
of the worst case deviation from the ideal 1 LSB step. For
example, a DAC with a 1.5 LSB output change for a 1 LSB
digital code change exhibits '12 LSB differential non-linearity.
Differential non-linearity may be expressed in fractional bits
or as a percentage of full scale. A differential non-linearity
greater than 1 LSB will lead to a non-monotonic transfer
function in a DAC and missing codes in an ADC.
Gain Error (Full Scale Error): For an ADC, the difference
(usually expressed in LSBs) between the input voltage that
should ideally produce a full scale output code and the actual input voltage that produces that code. For DACs, it is the
difference between the output voltage (or current) with full
scale input code and the ideal voltage (or current) that
should exist with a full scale input code.
Multiplying DAC: In a sense, every DAC is a multiplying
DAC since the output voltage (or current) is equal to the
reference voltage times a constant determined by the digital
input code divided by 2n (n is the number of bits of resolution). In a two quadrant multiplying DAC the reference voltage or the digital input code can change the output voltage
polarity. If both the reference voltage and the digital code
change the output voltage polarity four quadrant multiplication exists.
Offset Error (Zero Error): In a DAC, this is the output voltage that exists when the input digital code is set to give an
ideal output of zero volts. In the case of an ADC, this is the
difference between the ideal input voltage ('12 LSB) and the
actual input voltage that is needed to make the transition
from zero to 1 LSB. All the digital codes in the transfer curve
are offset by the same value. Many converters allow nulling
of offset with an external potentiometer. Offset error is usually expressed in LSBs.
Power Supply Rejection (Power Supply Sensitivity): The
sensitivity of a converter to changes in the dc power supply
voltages.
Quantizing Error: The error inherent in all AID conversions. Since even an "ideal" converter has finite resolution,
any analog voltage that falls between two adjacent output
codes will result in an output code that is inaccurate by up to
'12 LSB.
Ratlometric Operation: Many AID applications require a
stable and accurate reference voltage against which the input voltage is compared. This approach results in an absolute conversion. Some applications, however, use transducers or other signal sources whose output voltages are
proportional to some external reference. In these ratlometric applications, the reference for the signal source should
be connected to the reference input of the converter. Thus,
any variations in the source reference voltage will also
change the converter reference voltage and produce an accurate conversion.
Resolution: The smallest analog increment corresponding
to a 1 LSB converter code change. For converters, resolution is normally expressed in bits, where the number of analog levels is equal to 2n. As an example, a 12-bit converter
divides the analog signal into 212 = 4096 discrete voltage
(or current) levels.
Gain Temperature Coefficient (Full Scale Temperature
Coefficient): Change in gain error divided by change in
temperature. Usually expressed in parts per million per degree Celsius (ppml"C).
Integral Nonlinearity (Linearity Error): Worst case deviation from the line between the endpoints (zero and full
scale). Can be expressed as a percentage of full scale or in
fractions of an LSB.
LSB (Least-Significant Bit): In a binary coded system this
is the bit that carries the smallest value or weight. Its value
is the full scale voltage (or current) divided by 2n, where n is
the resolution of the converter.
Missing Codes: When an incremental increase or decrease
in input voltage causes the converter to increment or decrement its numeric output by more than one LSB the converter is said to exhibit "missing codes". If there are missing
codes, there is a numeric value on the output on the converter which cannot be reached by any input voltage value.
Monotonicity: A monotonic function has a slope whose
sign does not change. A monotonic DAC has an output that
changes in the same direction (or remains constant) for
each increase in the input code. The converse is true for
decreasing codes.
Settling Time: The time from a change in input code until a
DAC's output signal remains within ± '12 LSB (or some other
specified tolerance) of the final value.
MSB (Most Significant Bit): In a binary coded system this
is the bit that has the largest value or weight. Its value is one
half of full scale.
3-3
~
::::I
~
i
til
II
~NatiOnal
Semiconductor
Corporation
AID Converter Selection Guide
Part
No.
Absolute
Input
Resolution
Conversion
Accuracy
Voltage
(Bits)
Time
(Max)
Range
Output
Logic
Levels
Supplies
(V)
Temperature
Range'
M
I
Package
Comments
C
AID CONVERTER
TTL,
+5, -12
TRI·STATE
•
5V
TTL,
TRI·STATE
+5
•
•
110JLs
5V
TTL,
TRI-STATE
+5
•
•
•
20·Pin DIP
20·PinSO Differential Input
20-Pin PCC
±%LSB
110JLs
5V
TTL,
TRI-STATE
+5
•
•
•
20-Pin DIP
20-PinSO Differential Input
20-Pin PCC
B
±1 LSB
110JLs
5V
TTL,
TRI-STATE
+5
•
•
20-Pin DIP
20-PinSO Differential Input
20-PinPCC
ADCOB05
B
±1 LSB
110JLs
5V
TTL,
TRI-STATE
+5
•
20-PinDIP
ADCOBOB
B
±%LSB
100 JLs
5V
TTL,
TRI-STATE
+5
•
2B-Pin DIP
B-Channel MUX
2B-PinPCC
ADCOB09
B
±1 LSB
100 JLs
5V
TTL,
TRI-STATE
+5
•
2B-Pin DIP
B-Channel MUX
2B-Pin PCC
ADCOB11B
B
±%LSB
32 JLs
5V
TTL
+5
•
•
20·PinDIP 11-Channel
20-Pin PCC Serial 1/0
ADCOB11C
B
±1 LSB
32 JLs
5V
TTL
+5
•
•
20-Pin DIP 11-Channel
20-PinPCC Serial 1/0
ADCOB16
B
±%LSB
100 JLs
5V
TTL,
TRI-STATE
+5
ADCOB17
B
±1 LSB
100 JLs
5V
TTL,
TRI-STATE
ADCOB19B
B
±%LSB
16 JLs
5V
ADCOB19C
B
±1 LSB
16 JLs
ADCOB20B
B
±%LSB
ADCOB20C
B
±1 LSB
ADCOBOO
B
±2LSB
50 JLs
±5V
ADCOB01
B
±%LSB
110 JLs
ADCOB02
B
±%LSB
ADCOB03
B
ADCOB04
•
•
•
1B-Pin DIP
20-Pin DIP Differential Input
Ratiometric
Operation
•
40-PinDIP 16-Channel MUX
+5
•
40-Pin DIP 16-Channel MUX
TTL
+5
•
•
2B-PinDIP 19-Channel
2B-Pin PCC Serial 1/0
5V
TTL
+5
•
•
2B-PinDIP 19-Channel
2B·Pin PCC Serial 1/0
1.2 JLs
5V
TTL,
TRI-STATE
+5
•
•
•
20·Pin DIP
Built-In Track and
20-PinSO
Hold Function
20-PinPCC
1.2 JLs
5V
TTL,
TRI-STATE
+5
•
•
•
20·PinDIP
Built-In Track and
20-PinSO
Hold Function
20-Pin PCC
3-4
~
AID Converter Selection Guide (Continued)
Part
No.
Absolute
Input
Resolution
Conversion
Accuracy
Voltage
(Bits)
Time
(Max)
Range
Output
Logic
Levels
C
Supplies
(V)
Temperature
RangeM
I
oo
Package
Comments
C
.,
AID CONVERTER (Continued)
ADC0829B
8
±%LSB
100 ",5
5V
TTL.
TRI-STATE
ADC0829C
8
±1 LSB
100 ",5
5V
TTL,
TRI-STATE
+5
+5
-
•
(j)
•
28-Pin DIP
Additional Digital
Input Capability
::I
G)
C
ADC0831B
8
±%LSB
32 ",S
5V
TTL
+5
8
±1 LSB
32 ",S
5V
TTL
+5
·• ·•
ADC0832B
8
±%LSB
32 ",S
5V
TTL
+5
•
ADC0832C
8
±1 LSB
32 ",5
5V
TTL
+5
ADCOB33B
8
±%LSB
32",5
5V
TTL
ADCOB33C
B
±1 LSB
32",5
5V
ADCOB34B
8
±%LSB
32",5
ADCOB34C
B
±1 LSB
ADC083BB
B
ADCOB3BC
8-Pin DIP
Serial 1/0
8-PinDIP
Serial 1/0
•
8-Pin DIP
2-Channel
Serial 1/0
•
•
8-Pin DIP
2-Channel
Serial 1/0
+5
•
•
14-Pin DIP
4-Channel
Serial 1/0
TTL
+5
•
•
14-Pin DIP
4-Channel
Serial 1/0
5V
TTL
+5
•
•
14-Pin DIP
4-Channel
Serial 1/0
32",s
5V
TTL
+5
•
•
14-Pin DIP
4-Channel
Serial 1/0
±%LSB
32 "'S
5V
TTL
+5
•
•
20-Pin DIP B-Channel
20-Pin PCC Serial 1/0
8
±1 LSB
32",s
5V
TTL
+5
•
•
20-Pin DIP B-Channel
20-Pin PCC Serial 1/0
ADCOB41B
B
±%LSB
40 "'S
5V
TTL,
TRI-STATE
+5
•
•
20-Pin DIP Differential Input,
20-Pin PCC Internal Clock
ADCOB41C
8
±1 LSB
40 "'S
5V
TTL,
TRI-STATE
+5
•
•
20-Pin DIP Differential Input,
20-Pin PCC Internal Clock
ADCOB44B
B
±%LSB
40 ",5
5V
TTL,
TRI-STATE
+5
•
•
20-Pin DIP
4-Channel MUX,
Internal Clock
ADCOB44C
B
±1 LSB
40 ",5
5V
TTL,
TRI-STATE
+5
•
•
20-Pin DIP
4-Channel MUX,
Internal Clock
ADC0848B
8
±%LSB
40 ",5
5V
TTL,
TRI-STATE
+5
•
•
28-Pin DIP 8-Channel MUX,
28-Pin PCC Internal Clock
ADC0848C
8
±1 LSB
40",5
5V
TTL,
TRI-STATE
+5
•
•
28-Pin DIP 8-Channel MUX,
28-Pin PCC Internal Clock
ADC1001C
10
±1 LSB
200 "'S
5V
TTL,
TRI-STATE
+5
•
•
B-Bit Bus
20-Pin DIP Compatible,
Differential Input
ADC1005B
10
±%LSB
50 ",S
5V
TTL,
TRI-STATE
+5
•
•
8-Bit Bus
20-Pin DiP
Compatible,
20-Pin PCC
Differential Input
3-5
en
CD
Additional Digital
28-Pin DIP
Input Capability
ADC0831C
•
~::1
CD
n
O·
a:
CD
cu
"C
·s
CJ
c
o
1;
cu
"iii
en
~
~o
o
Q
.....
c(
AID Converter Selection Guide (Continued)
Part
No.
Absolute
Input
Resolution
Conversion
Accuracy
Voltage
(Bits)
Time
(Max)
Range
Output
Logic
Levels
Supplies
(V)
Temperature
Range'
Package
Comments
M
I
C
•
•
•
8-BitBus
20-Pin DIP
Compatible,
20-PinPCC
Differential Input
•
•
24-Pin DIP Differential Input
AID CONVERTER (Continued)
ADC1005C
10
±1 LSB
50/Ls
5V
TTL,
TRI-STATE
+5
ADC1021C
10
±1 LSB
200/Ls
5V
TTL,
TRI-STATE
+5
ADC1025B
10
±%LSB
50/Ls
5V
TTL,
TRI-STATE
+5
•
•
•
24-Pin DIP
Differential Input
28-Pin PCC
ADC1025C
10
±1 LSB
50/Ls
5V
TTL,
TRI-STATE
+5
•
•
•
24-Pin DIP
Differential Input
28-PinPCC
ADC1205B
12+sign
±%LSB
100/Ls
±5V
TTL,
TRI-STATE
+5, ±5
•
•
8-Bit Bus
24-Pin DIP Compatible,
Differential Input
ADC1205C 12+sign
±1 LSB
100/Ls
±5V
TTL,
TRI-STATE
+5, ±5
•
•
8-Bit Bus
24-Pin DIP Compatible,
Differential Input
ADC1210
12
±%LSB
200/Ls
10.2V
CMOS
+5to±15
ADC1211
12
±2LSB
200/Ls
10.2V
CMOS
+5to ±5
12+sign
±%LSB
100/Ls
±5V
TTL,
TRI-STATE
+5, ±5
•
•
28-Pin DIP
Differential
Input
ADC1225C 12+sign
±1 LSB
100/Ls
±5V
TTL,
TRI-STATE
+5, ±5
•
·
28-Pin DIP
Differential
Input
ADC3511
3%-Digit
0.05%
200ms
2V
TTL,
TRI-STATE
+5
•
24-Pin DIP
Integrating
/LP Compatible
AOC3711
3%-Digit
0.05%
400ms
2V
TTL,
TRI-STATE
+5
•
24-Pin DIP
Integrating
/LP Compatible
•
VOltage-to8-Pin DIP or Frequency
TO-99 Can Converter
100 kHz Max
ADC1225B
LM131
V-F
0.01%
N/A
Open
Vcc - 2V
Collector
+5to +40
•
•
•
•
•
•
24-Pin DIP
24-Pin DIP
DIGITAL VOLTMETER
AOD3501
3%-Oigit
0.05%
200ms
2V
7-Segment
LED Drive
+5
•
28-Pin DIP
3%-Oigit
LED DVM
AOD3701
3%-Oigit
0.05%
400ms
2V
7-Segment
LED Drive
+5
•
28-Pin DIP
3%-Digit
LED DVM
'Temperature ranges: ""M"" is -55'C to + 125'C ambient; ""'"" is -40'C to + 85'C or -25'C to + 85'C; ""C"" is O'C to +70'C.
3-6
~
C
NatiOnal
~ Semiconductor
o
o
Q)
o
o
Corporation
ADC0800 8-Bit AID Converter
General Description
Features
The ADC0800 is an 8-bit monolithic AID converter using Pchannel ion-implanted MOS technology. It contains a high
input impedance comparator, 256 series resistors and analog switches, control logic and output latches. Conversion is
performed using a successive approximation technique
where the unknown analog voltage is compared to the resistor tie points using analog switches. When the appropriate tie point voltage matches the unknown voltage, conversion is complete and the digital outputs contain an a-bit
complementary binary word corresponding to the unknown.
The binary output is TRI-STATE® to permit bussing on common data lines.
•
•
•
•
•
Low cost
±5V, 10V input ranges
No missing codes
Ratiometric conversion
TRI-STATE outputs
•
•
•
•
•
•
•
•
Fast
Contains output latches
TTL compatible
Supply voltages
Resolution
Linearity
Conversion speed
Clock range
The ADC0800PD is specified over - 55°C to + 125'C and
the ADCOaOOPCD is specified over O·C to 70"C.
TC=50 /.los
5 Voc and -12 Voc
a bits
±1 LSB
40 clock periods
50 to 800 kHz
Block Diagram
Vss
(PMOS
BODY)
R·NETWORK
TOP
15
10
r - ...__-__:::_-_-_-...~:~~-=-~-~:::-:::--::..- -r--_-_-__
+1_1o()CLOCK
I
I
P.RESISTOR
N·BODY
: : :~"':::1dI
I
I
I
I
ANALOG
SWITCHE~
16
START
,CONVERSION
I
SelECTION
AND
CONTROL
LOGIC
.-J_
....-+---+-
I
t
150
I
Is
I
I
I
L
END OF
CONVERSION
(EDC)
300
O-VGG
17
8·BIT
LATCH
..J
5--R·NETWORK
BOTTOM
12
4
3 2
1
MS8
VIN
ANALOG
INPUT
DIGITA;'=';RDUND
17 16 14 13
LSB
COMPLEMENTARY
DIGITAL OUTPUT
TL/H/5670-1
(00000000 ~ + fuJl·scale)
TRI-STATE8I is a registered trademark of National Semiconductor Corp.
3-7
o
o
CO
o
Absolute Maximum Ratings
C
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
o
Y+) the absolute value of current at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, 8JA, and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is Po ~ (TJMAX - TAl/8JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJMAX ~ 12S'C, and the typical junction·to·ambient thermal resistance of the ADC0800PD and ADCOBOOPCD when board mounted is 66'C/W.
Note 4: Human body model, 100 pF discharged through a 1.5 kO resistor.
Note 5: Typicals are at 2S'C and represent most likely parametric norm.
Note 6: Tested limits are guaranteed to National's AOQl (Average OutgOing Quality Level).
Note 7: DeSign limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 8: Non.linearity specifications are based on best straight line.
Note 9: Guaranteed by design only.
Note 10: Start conversion pulse duration greater than 3V2 clock periods will cause conversion errors.
3-8
l>
C
Timing Diagram
oo
CC)
o
o
CLOCK
INPUT
+5V-n
START
CONVERSION
EDC
OV~
~I~I
+5V\
\ - - - - - 4DX
OV'
_____________________________
11/11,----1
II
,
•
+5V
OUTPUT
ENABLE
50%
OV
+5V
DATA
1\50%
!
-
-
-
-
-
ITRTSTATEI -
-
-
~
-
OV
ENABLE
DELAY-
1 90'10
90'10
"10'10
10%
1·-
--
DISABLE
DELAY-
1TL/H/567D-2
Data is complementary binary (full scale is all "O's" output).
Application Hints
R-network (pin 15). The analog input voltage and the voltage that is applied to the bottom of the R-network (pin 5)
must be at least 7V above the -VGG supply voltage to
ensure adequate voltage drive to the analog switches.
Other reference voltages may be used (such as 10.24V). If a
5V reference is used, the analog range will be 5V and accuracy will be reduced by a factor of 2. Thus, for maximum
accuracy, it is desirable to operate with at least a 10V reference. For TTL logic levels, this requires 5V and - 5V for the
R-network. CMOS can operate at the 10 VDe Vss level and
a single 10 Voe reference can be used. All digital voltage
levels for both inputs and outputs will be from ground to
Vss·
OPERATION
The ADC0800 contains a network with 256-3000 resistors
in series. Analog switch taps are made at the junction of
each resistor and at each end of the network. In operation,
a reference (10.00V) is applied across this network of 256
resistors. An analog input (VIN) is first compared to the center point of the ladder via the appropriate switch. If VIN is
larger than VREF/2, the internal logic changes the switch
points and now compares VIN and % VREF. This process,
known as successive approximation, continues until the
best match of VIN and VREF/N is made. N now defines a
specific tap on the resistor network. When the conversion is
complete, the logic loads a binary word corresponding to
this tap into the output latch and an end of conversion
(EOC) logic level appears. The output latches hold this data
valid until a new conversion is completed and new data is
loaded into the latches. The data transfer occurs in about
200 ns so that valid data is present virtually all the time in
the latches. The data outputs are activated when the Output
Enable is high, and in TRI-STATE when Output Enable is
low. The Enable Delay time is approximately 200 ns. Each
conversion requires 40 clock periods. The device may be
operated in the free running mode by connecting the Start
Conversion line to the End of Conversion line. However, to
ensure start-up under all possible conditions, an external
Start Conversion pulse is required during power up conditions.
ANALOG INPUT AND SOURCE RESISTANCE
CONSIDERATIONS
The lead to the analog input (pin 12) should be kept as short
as possible. Both noise and digital clock coupling to this
input can cause conversion errors. To minimize any input
errors, the following source resistance considerations
should be noted:
No analog input bypass capacitor reFor Rs:5:5k
quired, although a 0.1 ,...F input bypass
capacitor will prevent pickup due to unavoidable series lead inductance.
For 5k < RS:5: 20k A 0.1 ,...F capacitor from the input (pin
12) to ground should be used.
For RS> 20k
Input buffering is necessary.
If the overall converter system requires lowpass filtering of
the analog input Signal, use a 20 kO or less series resistor
for a passive RC section or add an op amp RC active lowpass filter (with its inherent low output resistance) to ensure
accurate conversions.
REFERENCE
The reference applied across the 256 resistor network determines the analog input range. VREF = 1O.OOV with the top
of the R-network connected to 5V and the bottom connected to -5V gives a ±5V range. The reference can be level
shifted between Vss and VGG. However, the voltage, applied to the top of the R-network (pin 15), must not exceed
Vss, to prevent forward biasing the on-chip parasitic silicon
diodes that exist between the P-diffused resistors (pin 15)
and the N-type body (pin 10, Vss). Use of a standard logic
power supply for Vss can cause problems, both due to initial
voltage tolerance and changes over temperature. A solution
is to power the Vss line (15 mA max drain) from the output
of the op amp that is used to bias the top of the
CLOCK COUPLING
The clock lead should be kept away from the analog input
line to reduce coupling.
LOGIC INPUTS
The logical "1" input voltage swing for the Clock, Start Conversion and Output Enable should be (Vss-1.0V).
3-9
c
c
co
c
Application Hints
~r_____J')c_"";:'SL::!.....!:~~
CONVERSION
"'---~CARRV
START CONVERSION
(TO AlDI
MMnC161
ADC0800
CLOCK
READY FOR
NEXT CONVERSION
GND
Vee
1
Vee
1
GND
0
Vee
1
TL/H/5670-10
FIGURE 2. AID Control Logic
3·10
~
Application Hints
C
(Continued)
Full-Scale Adjustment: This is the offset voltage required
at the top of the R-network (pin 15) to make the 00000001
to 00000000 transition when the input voltage is 1 % LSB
from full-scale (60 mV less than full-scale for a 10.24V
scale). This voltage is guaranteed to be within ± 2 LSB for
the ADCOBOO without adjustment. In most cases, adjustment can be accomplished by having a 1 ko. pot on pin 15.
ZERO AND FULL-SCALE ADJUSTMENT
Zero Adjustment: This is the offset voltage required at the
bottom of the R-network (pin 5) to make the 11111111 to
11111110 transition when the input voltage is Y2 LSB (20
mV for a 10.24V scale). In most cases, this can be accomplished by having a 1 ko. pot on pin 5. A resistor of 4750.
can be used as a non-adjustable best approximation from
pin 5 to ground.
Typical Applications
Ratiometrlc Input Signal with Tracking Reference
General Connection
DV
+5V .....- - -..
15
lD
+5V
-12V CLOCK
II
11
.D
OUTPUT ENABLE
AOCDIDD
SC
POTENTIOMETRIC ....
V._N_ _+-...;.:j2
TRANSDUCER .,
ADCDlOD
TLlH/5670-11
Hi-Voltage CMOS Output Levels
+tOV
-IZV
TLlH/5670-4
12
AOCD8DD
ov to
10V V1N range
OV to 10V output levels
TLlH/5670-12
3-11
o
o
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o
o
C) ~~--------------------------------------------------------------------------------------~
C)
!
oQ
Typical Applications
(Continued)
«
VREF= 10 VOC With TTL Logic Levels
2.n
ANAlDG
INPUT
t5Voc
Uk
1%
LM329DZ
EO.
HOC
15VOC
OUTPUT
ENABLE
4.99k
1%
'" See application hints
-uv
TLlH/S670-13
A 1 and A2 ~ LM3SBN dual op amp
VREF= 10 VOC With 10V CMOS Logic Levels
ISV
1k
LM329DZ
5,"
1%
EO.
ENABlE
DUTPUT
- lV oc
"'See application hints
TL/H/S670-14
Input Level Shifting
15V
-5V TO BV INPUT
TOADcoaao
• Permits TIL compatible outputs with
OV to 10V Input range (OV 10 -10V
input range achieved by reversing
polarity of zener diodes and returning
the 6.Bk resistor to V-).
'"
ADJUST FOR -5V
OUT WITH OV INPUT
TL/H/S670-S
3-12
Typical Applications
l>
C
(Continued)
zero adjust potentiometer should be set to provide a flicker
on the LSB LED readout with all the other display LEDs
OFF.
To adjust the full-scale adjust potentiometer, an analog input that is 1% LSB less than the reference (10.240-0.060
or 10.180 VDcl should be applied to the analog input and
the full-scale adjusted for a flicker on the LSB LED, but this
time with all the other LEDs ON.
A complete circuit for a simple AID tester is shown in Figure
4. Note that the clock input voltage swing and the digital
output voltage swings are from OV to 10.24V. The
MM74C901 provides a voltage translation to 5V operation
and also the logic inversion so the readout LEDs are in binary.
TESTING THE AID CONVERTER
There are many degrees of complexity associated with testing an AID converter. One of the simplest tests is to apply a
known analog input voltage to the converter and use LEDs
to display the resulting digital output code as shown in Figure 3. Note that the LED drivers invert the digital output of
the AID converter to provide a binary display. A lab DVM
can be used if a preCision voltage source is not available.
After adjusting the zero and full-scale, any number of pOints
can be checked, as desired.
For ease of testing, a 10.24 VDC reference is recommended
for the AID converter. This provides an LSB of 40 mV
(10.240/256). To adjust the zero of the AID, an analog input
voltage of % LSB or 20 mV should be applied and the
START
AID
UNDER TEST
I
...I
GJ
OUTPUT
ENABLE
BINARY DISPLAY
TL/H/567D-15
FIGURE 3. Basic AID Tester
IPDWE~D·~tDp~e~) 0 - - -....- - -....- - -......... +
'J1D.F
1k
FUll·SCAlE
ADJUST
OV....J
.-
LJ
.= 800kHz
11
SVDC
10
15
10.24V-n
Vss
OUT EN
MSB
ClK
AOCOBOO
UNDER TEST
ANALOG
INPUT
1k
':"
ZERO
ADJUST
"E
2EA MM74C901
{CMOS TO TTL)
10 F
•
v- .. ":"
-Hoc
TL/H/567D-7
FIGURE 4. Complete Basic Tester Circuit
3-13
oc
co
c
c
0
0
CD
0
0
e
~
Typical Applications
(Continued)
The digital output LED display can be decoded by dividing
the 8 bits into the 4 most significant bits and 4 least significant bits. Table I shows the fractional binary equivalent of
these two 8-bit groups. By adding the decoded voltages
which are obtained from the column: "Input Voltage Value
with a 10.240 VREF" of both the MS and LS groups, the
value of the digital display can be determined. For example,
for an output LED display of "1011 0110" or "B6" (in hex)
the voltage values from the table are 7.04 + 0.24 or
7.280 Voe. These voltage values represent the center values of a perfect AID converter. The input voltage has to
change by ± % LSB (± 20 mV), the "quantization uncertainty" of an AID, to obtain an output digital code change. The
effects of this quantization error have to be accounted for in
the interpretation of the test results. A plot of this natural
error source is shown in Figure 5 where, for clarity, both the·
analog input voltage and the error voltage are normalized to
LSBs.
TABLE I. DECODING THE DIGITAL OUTPUT LEOs
INPUT VOLTAGE
VALUE WITH
10.24 VREF
FRACTIONAL BINARY VALUE FOR
BINARY
HEX
LSGROUP
MSGROUP
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
•
0
1
0
1
0
1
0
1
0
15/16
MSGROUP
LSGROUP
9.600
8.960
8.320
7.680
7.040
6.400
5.760
5.120
4.480
3.840
3.200
2.560
1.920
1.280
0.640
0
0.600
0.560
0.520
0.480
0.440
0.400
0.360
0.320
0.280
0.240
0.200
0.160
0.120
0.080
0.040
0
15/256
7/8
7/128
13/16
13/256
3/4
3/64
11/16
11/256
5/8
5/128
9/256
1/2
1/32
7/16
7/256
3/8
3/128
5/16
5/256
1/64
1/4
3/16
3/256
1/8
1/128
1/16
~
i
~
~
1/256
1
In r -
~-- "Z--",3
0" ""
...~ -In 1 - - ' - - - -
~
-I
--~I--
ANALOG INPUT VOLTAGE (IN LSB.,
TL/H/5670-8
FIGURE 5. Error Plot of a Perfect AID Showing Effects of Quantization Error
3-14
Typical Applications
»
c
(Continued)
A low speed ramp generator can also be used to sweep the
analog input voltage and the LED outputs will provide a binary counting sequence from zero to full-scale.
For operation with a microprocessor or a computer-based
test system, it is more convenient to present the errors digitally. This can be done with the circuit of Figure 7 where the
output code transitions can be detected as the 1O-bit DAC is
incremented. This provides y.. LSB steps for the 8-bit AID
under test. If the results of this test are automatically plotted
with the analog input on the X axis and the error (in LSB's)
as the Y axis, a useful transfer function of the AID under
test results. For acceptance testing, the plot is not necessary and the testing speed can be increased by establishing
internal limits on the allowed error for each code.
The techniques described so far are suitable for an engineering evaluation or a quick check on performance. For a
higher speed test system, or to obtain plotted data, a digitalto-analog converter is needed for the test set-up. An accurate 1O-bit DAC can serve as the precision voltage source
for the AID. Errors of the AID under test can be provided as
either analog voltages or differences in two digital words.
A basic AID tester which uses a DAC and provides the error
as an analog output voltage is shown in Figure 6. The 2 op
amps can be eliminated if a lab DVM with a numerical subtraction feature is available to directly readout the difference
voltage, "A-C".
ANALOG INPUT
VOLTAGE
"A"
IDDXANALOIi
ERROR VOLTAGE
.".
All R·s=O.OS% tolerance
TL/H/5670-16
FIGURE 6_ AID Tester with Analog Error Output
DIGITAL
DIGITAL
INPUT
OUTPUT
TLlH/S670-17
FIGURE 7_ Basic "Digital" AID Tester
Connection Diagram
Dual-In-Llne Package
R·
NET·
WORK
Voo
11
2-5
17
2-6
TOP
" "
LSB
2-1
2-8
"
13
"IN
"
CLOCk
Vss
11
10
L-.
I-
r--
f-
1
,
3
•
,-. ,-3 ,-, ,-I
MSB
5
•
1
•
R·
,
EDC
NET·
WORK
BOTTOM
Top View
Order Number ADC0800PD
or ADC0800PCD
See NS Package Number D18A
3-15
TL/H/5670-9
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Semiconductor
Corporation
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ADC0801, ADC0802, ADC0803, ADC0804,
OIFF INPUTS
DB4
DB'
'Ok
CUCIN 4
11m
DB.
y
"
'9
ADCOB03
±Yz LSB
±Yz LSB
DATA
ADCOB04
ADCOB05
TL/H/5671-31
3-16
±1 LSB
±1 LSB
l>
Absolute Maximum Ratings
IC
(Notes 1 & 2)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
875mW
Package Dissipation at T A = 25'C
ESD Susceptibility (Note 10)
Supply Voltage (Vce> (Note 3)
6.5V
Voltage
Logic Control Inputs
-0.3Vto +18V
At Other Input and Outputs
-0.3V to (Vee+0.3V)
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
260'C
Dual·ln-Line Package (ceramic)
300'C
Surface Mount Package
Vapor Phase (60 seconds)
Infrared (15 seconds)
- 65'C to + 150'C
Storage Temperature Range
800V
Operating Ratings
TMINS;TAS;TMAX
-55'CS;TAS; + 125'C
-40'CS;TAS; +85'C
-40'CS;TAS; + 85'C
O'CS;TAS; + 70'C
O'CS;TAS; +70'C
O'CS;TAS; + 70'C
4.5 Vee to 6.3 Vee
ADC0801/02/03/04LCJ
ADC0801/02/03/05LCN
ADC0804LCN
ADC0802/03/04LCV
ADC0802/03/04LCWM
Range of Vce
215'C
220'C
co
o
......
.....
l>
IC
oo
(Notes 1 & 2)
Temperature Range
ADC0801/02LJ
oo
co
o
N
.....
l>
IC
oo
co
oCo)
.....
l>
IC
oo
Electrical Characteristics
co
The following specifications apply for Vee=5 Vee. TMINS;TAS;TMAX and fCLK=640 kHz unless otherwise specified.
o
Max
Units
With Full-Scale Adj.
(See Section 2.5.2)
±%
LSB
.....
»
IC
ADC0802: Total Unadjusted Error (Note 8)
VREF/2 = 2.500 Vee
±%
LSB
co
ADC0803: Total Adjusted Error (Note 8)
With Full-Scale Adj.
(See Section 2.5.2)
±%
LSB
Parameter
Conditions
ADC0801: Total Adjusted Error (Note 8)
Typ
Min
ADC0804: Total Unadjusted Error (Note 8)
VREF/2=2.500 Vee
±1
LSB
ADC0805: Total Unadjusted Error (Note 8)
VREF/2-No Connection
±1
LSB
VREF/2 Input Resistance (Pin 9)
ADC0801/02/03/05
ADC0804 (Note 9)
2.5
0.75
8.0
1.1
k!l
k!l
Analog Input Voltage Range
(Note 4) V(+) orV(-)
DC Common-Mode Error
Over Analog Input Voltage
Range
±Yt6
±Ya
Vec
LSB
Power Supply Sensitivity
Vee=5 Vee ±10% Over
Allowed VIN( + ) and VIN( -)
Voltage Range (Note 4)
±Y16
±Ya
LSB
Gnd-0.05
Vee+ 0.05
AC Electrical Characteristics
The following specifications apply for VCC=5 Vec and TA=25'C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Te
Conversion Time
fClK = 640 kHz (Note 6)
103
114
,...s
Te
Conversion Time
(Note 5. 6)
66
73
1/felK
felK
Clock Frequency
Clock Duty Cycle
Vcc=5V. (Note 5)
(Note 5)
100
40
1460
60
kHz
%
CR
Conversion Rate in Free-Running
Mode
INTR tied to WR with
CS=O Vee. felK=640 kHz
9708
conv/s
640
8770
tW(Wi'l)l
Width of WR Input (Start Pulse Width)
CS=O Vee (Note 7)
tAce
Access Time (Delay from Falling
Edge of RD to Output Data Valid)
Cl =100pF
100
135
200
ns
t1H. tOH
TRI-STATE Control (Delay
from Rising Edge of RD to
Hi-ZState)
Cl =10 pF. Rl =10k
(See TRI-STATE Test
Circuits)
125
200
ns
tWlotRI
Delay from Falling Edge _ _
of WR or RD to Reset of INTR
300
450
ns
CIN
Input Capacitance of Logic
Control Inputs
5
7.5
pF
COUT
TRI-STATE Output
Capacitance (Data Buffers)
5
7.5
pF
ns
CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmit! trigger circuit and is therefore specified separately]
VIN (1)
Logical "1" Input Voltage
(Except Pin 4 CLK IN)
Vee=5.25 Vee
3-17
2.0
15
Vee
~
oo
o
U1
AC Electrical Characteristics (Continued)
The following specifications apply for VCC = SVOC and T MIN';: TA ,;: T MAX, unless otherwise specified.
Symbol
I
Parameter
I
Conditions
I
Min
I
Typ
I
Max
I
Units
CONTROL INPUTS [Note: ClK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]
VIN(O)
logical "0" Input Voltage
Vcc=4.7SVoc
0.8
VOC
1
",Aoc
(Except Pin 4 ClK IN)
liN (1)
logical "I" Input Current
O.OOS
VIN=S VOC
(All Inputs)
liN (0)
logical "0" Input Current
VIN=OVOC
-1
-O.OOS
2.7
3.1
3.S
VOC
I.S
1.8
2.1
VOC
0.6
1.3
2.0
VOC
0.4
Voc
",Aoc
(All Inputs)
CLOCK IN AND CLOCK R
VT+
ClK IN (Pin 4) Positive Going
Threshold Voltage
VT-
ClK IN (Pin 4) Negative
Going Threshold Voltage
VH
ClK IN (Pin 4) Hysteresis
(VT+)-(Vr)
VOUT(O)
VOUT (1)
logical "0" ClK R Output
10=360 ",A
Voltage
Vcc=4.7S Voc
logical "I" ClK R Output
10=-360 ",A
Voltage
Vcc=4.7S Voc
2.4
VOC
DATA OUTPUTS AND INTR
VOUT (0)
logical "0" Output Voltage
Data Outputs
IOUT=I.6mA. Vcc=4.7SVoc
0.4
VOC
INTROutput
10UT= 1.0 rnA, Vcc=4.7S Voc
0.4
Voc
VOUT(I)
Logical "I" Output Voltage
10= -360 ",A, Vcc=4.7S Voc
2.4
VOUT (1)
logical "I" Output Voltage
10= -10 ",A, Vcc=4.7SVoc
4.S
Voc
lOUT
TRI-STATE Disabled Output
-3
",Aoc
leakage (All Data Buffers)
VOUT=OVOC
Voc
3
VOUT=S Voc
",Aoc
ISOURCE
VOUT Short to Gnd, T A = 2S"C
4.S
6
mAoc
ISINK
VOUT Short to Vcc, T A = 2S"C
9.0
16
mAoc
POWER SUPPLY
Icc
Supply Current (Includes
fCLK=640 kHz,
ladder Current)
VREF/2=NC, TA=2S"C
andCS=SV
ADC0801/02/03/04lCJ/OS
1.1
1.8
ADC0804lCN/lCV IlCWM
1.9
2.S
rnA
rnA
Note 1: Absolute Maximum Ratings indicate lim~s beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd pOint should always be wired to the 0 Gnd.
Note 3: A zener diode exists, internally, from Vcc to Gnd and has a typical breakdown voltage of 7 Voc.
Note 4: For VIN(-):?: VIN(+) the digital output code will be 0000 0000. Two on·chlp diodes are tied to each analog input (see bloc\< diagram) which will forward
conduct for analog input voltages one diode drop below ground or one diode drop greater than the Vee supply. Be careful, during testing at low Vcc levels (4.5V),
as high level analog inputs (5V) can cause Ihis input diode 10 conduct-especially al elavaled lemperalures, and cause errors for analog inputs near full·scale. The
spec allows 50 mV forward bias of either diode. This means Ihat as long as Ihe analog VIN does not exceed Ihe supply vollage by more Ihan 50 mV, the output
code will be correct. To achieve an absolule 0 Voc to 5 Vee inpul voltage range will therefore require a minimum supply voltage of 4.950 Voc over temperature
variations, initial tolerance and loading.
Note 5: Accuracy is guaranteed al fClK ~ 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limils can be
extended so long as Ihe minimum clock high lime interval or minimum clock low lime inlerval is no less Ihan 275 ns.
Note 6: With an asynchronous start pulse, up to 8 clock periods may be required before Ihe inlernal clock phases are proper to start Ihe conversion process. The
start request is intemally latched. see Figure 2 and section 2.0.
Note 7: The CS input is assumed 10 bracket the WR strobe input and Iherefore liming is dependent on Ihe WR pulse width. An arbitrarily wide pulse width will hold
the converter in a reset mode and the start of conversion is Initialed by the low to high Iransition of the WR pulse (see timing diagrams).
Note 8: None of these AIDs requires a zero adiust (see section 2.5.1). To obtain zero code at olher analog input voltages see section 2.5 and Rgure 5.
Note 9: The VREF/2 pin is the center point of a two resistor divider connected from VCC 10 ground. Each resistor Is 2.2k, excepl for the AOC0804LCJ where each
resistor is 16k. Total ladder input resistance is the sum of the two equal resistors.
Note 10: Human body model, 100 pF discharged Ihrough a 1.5 kll resistor.
3-18
»
c
Typical Performance Characteristics
~
~
>
c
~
c
'"0:
~
~
3.5
w
i"
'"~""
400
l.-'
1.6
c
>
c
""
"">~
1.5
1.4
300
1.3
4.50
5.00
5.25
'"
i-"'
_55°C < TA < +125°C
~
2.3
~
1.9
400
200
VCC -SUPPLY VOLTAGE (VDcl
600
800
CD
(")
1.5
4.50
1000
o
oCo)
.....
»
c
VT_
d
0
5.50
(")
I-
100
4.75
2.7
o
CD
o
c
VT+
~
200
l..-
3.1
(")
N
....
»
I
I
C
"
~
ClK IN Schmitt Trip levels
vs. Supply Voltage
~
1.7
~
i!:
l>
c
500
-55°C::; TA~ +125°C
w
'"
o
CD
o
......
Delay From Falling Edge of
RD to Output Data Valid
vs. load Capacitance
logic Input Threshold Voltage
vs. Supply Voltage
1.8
(")
5.00
4.75
LOAD CAPACITANCE (pFI
5.25
5.50
VCC - SUPPLY VOLTAGE (Voci
o
CD
o
....
»
0I:loo
c
(")
o
CD
o
UI
Full-Scale Error vs
Conversion Time
fCLK vs. Clock Capacitor
1000
8
;a
=1 k
R= Ok
..
~
1\
\
~
.!f'
ffi
4
~
3
~
2
:li
r\
10
5
>-
R =2,,,,
100
6
0:
0:
I
~
1000
oS
....
ffi
Is~u~e~
..,...
I
VOUT =2.4 VDC
0:
o:
il
....
.,~
5
4
1:
2.0
~
~
1.6
....
~
~
2
-50 -25
~I
f-V~~~K·~C
0
25
50
75
100 125
TA - AMSIENTTEMPERATURE ('CI
2.4
""
oS
0:
3
t-
V,N(+I =V,N(-I = OV.
ASSUMES VOS = 2 mV.
THIS SHOWS THE NEED
FOR A ZERO ADJ, IF
THE SPAN IS REDUCED.
Stt614
2
~
60
I-
SO
120
100
0
0.01
140
0.1
""
-r-t-+.
14
1~
Vcc~t:
0803 AND ADC080lcc' f.SV
1.2
O.S
0.4
t-
'5. V
Vc =sv
r-~cc=4.5V
0
-50 -25
0
25
.-.a
t-kocbS01- 'I LSB-j
0:
"0:
ffi
~
:li
;0
0.5
1.22
50
~-4.
100 125
TA - AMSIENT TEMPERATURE rCI
256
_
+.t-
-l-I(9,fTSI
Y
0
19,53
(S SITSI
!'\["
II
1.1.
0
75
4.88
~'2 SITtl~ I 9.77
:::;
1 I~
2(~REFf2I' -
I
I ~~~~~ ~~~:S~~~,1-t-1'·S~V~LUE (mVI
~
0:
~ ~K=640kH•
CIS"I '
5
linearity Error at low
VREF/2 Voltages
1.0
4bcij-
:gg080~ ~
1.0
VREFf2 (VDCI
Power Supply Current
vs Temperature (Note 9)
~~~:E~~TPUT:
6
!tc
12
10
t-
TCo CONVERSION TIME (P.I
vec - SYoc
7
i;;
~ Vec'5.0V
40
Output Current vs
Temperature
..
ffi
"r'i/Kj
CLOCK CAPACITOR (pFI
S
~
Vee '4.5V
0
100
14~
TC= 73/IcLK
7
~
c
Effect of Unadjusted Offset Error
vs. VREF/2 Voltage
16
JL Ll.
1
2
2.5
VREF/2 VOLTAGE (VDcl
Tl/H/5671-2
3-19
II)
o
CO
o
o
TRI-STATE Test Circuits and Waveforms
c
~o
tOH. CL = 10 pF
tOH
Vcc
Vcc
CO
o
o
c
Vcc
ill!
«
.....
('I)
o
CO
o
DATA :::
o
OUTPUTS
c
«
C\i
o
~~1H
~
DATA
OUTPUT
ill!
------=
OND
TL/H/5671 -3
tr=20 ns
CO
o
o
c
«
.......
.....
o
CO
o
Timing Diagrams (All timing is measured from the 50% voltage points)
START
CDNVERSI: _ _ _ _ _. , \..._ _ _ _.....
o
c
_
«
/
II-I----J·
~I-~
IWI-
-
I-I--
IW(WiiIL
ACTUAL INTERNAL
STATUS OF THE
CONVERTER
"BUSV"
t\ ~~~~J~ ~:~~~:~
"NOT BUSV"
r---- I TO 8x lIfCLK
~ ---INTERNAL T C -
(LAST DATA WAS READI
V
__
_ WAS
__
___
(LAST
DATA
NOT_
READI
~
~ 1\ INT ASSERTED
J
-
_1/2TCLK
Output Enable and Reset INTR
iilfii RESET
~
'RI
-
~-------NDTE,j---~::::t-_~
DATA
OUTPUTS
TRI·STATE'~J
--------1
~----
- ----
- - tAce
Note: Read strobe must occur 8 clock periods (8/1CLKl after assertion of interrupt to guarantee reset of iNTR.
3-20
TLlH/5671-4
l>
c
oo
Typical Applications (Continued)
co
6800 Interface
....o
Ratlometric with Full-Scale Adjust
i;
C
oo
Vee
fSVocl
cs.--,---~
co
o
.......
l>
r------,
__
I\)
I
Vee ~-+--...,.-.,
"
"
c
oo
"
~C
VOA
&800,
6802,
6502.
ETC.
+
P4----------~mm
r---i)oo--ojRl!
T
AID
AID
~-4-----.~WR
co
o
,oIIF
DATA
,,
oo
,
........
L. ____ .J
.~.
fSAOJUST
co
o
""'"
i;
C
oo
OPTIONAL
Note: before using caps at YIN or YREF/2,
see section 2.3.2 Input Bypass Capacitors.
co
o
U1
Absolute with a 2.S00V Reference
Absolute with a SV Reference
Vee
VCC-VREF
(SYnc)
15Vocl
:-----,
Vee ~-4----.
Vee 1--4---'--,
+
~lhF
AID
AID
"
r--......I--i·~1D·
I
I
V",,, ~----4"";;="
I
I
"
.,..
L. ____ J
'"
FS
AOJ
OPTIONAL
FSADJUST
'For low power. see also LM385·2.5
Zero-Shift and Span Adjust: 2V S; VIN S; SV
Span Adjust: OV S; VIN S; 3V
Vee
(5Vocl
Vee
(5Vocl
vccl-~"""-------"""
r--<>--iVlNf+1
Vee~-+------"""
+
T'h
V'N
AID
F
1.2k
"
r- - - - - - - -.,
I
I
~:k
I
I
ADJ
LM'"
V,.
AID
I
I
I
..k
FS
I
+
SETS ZERO
CODE VOLTAGE
"D
1k
I
I
SET"DLTA'ES'A'
(SEE SECTION 2.4)
I
lM33&
AOJ
~I~F
I
L _________ J
2Voc
Uk
ZERO ADJ
TL/H/5671-5
3-21
LI)
o
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o
o
Typical Applications (Continued)
c
~
~
Directly Converting a Low-Level Signal
;
o
A ",p Interfaced Comparator
Vee
Vee
!5V oc l
15Vocl
C')
oco
+
o
~'D~F
o
c
cc
......
A/D
Uk
C'I
o
co
o
lM3lB
o
"
c
cc
......
.,..
FS
AOJ
o
co
o
For: V,N(+»V,N(-)
Oulpul~ FFHEX
o
c
For: V,N(+)
eLlR
eLK IN
CO
External Clocking
....
«:)
~! ~ftf--_'C~~
-----'.7VOINI
,.------,
-.--
NC~ eLK R
AlD#1
i>
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.
-- -- --- ----1.5VMAXD
o
«:)
CO
«:)
.....
'"):0
SIk-
AID
C
'eLK.......- elK IN
o
AiD
«:)
CO
CLKIN
«:)
W
.....
):0
r-NCO-- eLK R
--"pf
C
J;
o
«:)
100 kHz<:fCLK<:1460 kHz
CO
«:)
AJO#Z
~
~
·Use a large R value
to reduce loading
at elK Routput.
i>
c
g
eLKIN
I
I
CO
+
«:)
U1
IF MORETHAN 5 ADDITIONAL
Alas. USE A CMOS BUFFER (NOT T2U
Self-Clocking In Free-Running Mode
p.P Interface for Free-Running AID
'Ok
eLKIN
AID
RESET
;,;-15DPF
'·STAGE
AID
elK R
1--....--1.~CLK B~N~~:4~~R
Vo7·
'Ok
NO
eLKIN
1STAHTO
;:J;'
150pF
READY
{TOpP}
• After power-up, a momentary grounding
of the WR input is needed to guarantee operation.
-I 1--IB
·VOl
n
.
n
L----...J
t
lt
1lfCLKl
PREVENTSRD
LOURINGAID
DATA UPDATE
t
~T'----I
RESET
(12 It l/felKI
RESET
Operating with "Automotive" Ratiometric Transducers
Vee
(SVacl
Ratiometric with VREF/2 Forced
Vee
(SYnc)
"k
VXDR
Vee
VIN{+)
1k
ZERO
ADJ
+
VIN{+)
~tDJ.lF
VIN(-)"
Vee
AID
3k
ADtl80S
'6k
AID
':'
1-_-._ _ _ _..
"k
':'
VREFI2
"k
·VIN(-)=0.15 Vee
15% of Vee <:VXDR<:S5% of Vee
TL/H/5671-7
3-23
.."
o
CO
o
o
Typical Applications (Continued)
C
....----------..,
.--....-'II'\I\ro--1r...--!V,.,.1
LM33SU
IUIV.Z5°C,
10 ..Vfll
.
AID
TAMIN
VREF"
"I'··V
"OJ
t--.>--t-<:.
'"
'Circuit values shown are for crCS:TAS: + 128"C
• ·Can calibrate each sensor to allow easy replacement. then
AID can be calibrated with a pre-set input voltage.
,n·
Z.7k-
1k
T"MAX
2.SV
LM338
'OJ
"D'
TL/H/5671-8
3-24
l>
C
Typical Applications (Continued)
oQ
Handling ± 5V Analog Inputs
CCI
Read-Only Interface
Q
.....
ItPIUS
VCC
(5V nc)
l>
c
oQ
DATA
""r------..,
r--o-.....""-....-IVINI+)
CCI
Q
I\)
Vee
l>
AID
c
oQ
+
V'N
~'aPF
CCI
Q
AID
Co)
l>
c
oQ
iiii~
CCI
r---
Q
.j:Io
DATA I S / ~ '""-..,STARTS NEW
OUTPUT
CONVERSION
TL1H15671-33
TLIH15671-34
l>
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·8eckman Instruments #694-3-R10K resistor array
JLP Interfaced Comparator with Hysteresis
o
Q
Protecting the Input
CCI
Q
U1
Vee
(5 VDC)
V,.I+I
MS'ID81II---...,
AID
Vee
+
.;;!;1DI'r
-15 VDC
AID
V.NH
":"
Diodes are lN914
",VAEF
VIN (-)
os
TLlH15671-9
CLK
JIll
A Low-Cost, 3-Decade Logarithmic Converter
RFB
TLlH15671-35
> ....._ .....""--\VINI+)
'DO
Analog Self-Test for a System
VA
AID
•
CHANNEL
AID
ANALOG
MUX
C04D51
C CHANNEL
SELECT
fROM OUTPUT
PORT Of p.P
TLlH15671-36
'LM3B91ransislors
A. B. C. D
3-25
= LM324A quad op amp
Typical Applications
(Continued)
3·Decade Logarithmic AID Converter
A, B, C, D = LM324A
> ....--w\r----!VINI+1
'"
AID
'00
"'101FT.".
Uk
4311
'Ok
;~~f-'II''II'''''''H
-5V
AOJ
Multiplexing Differential Inputs
Noise Filtering the Analog Input
'.'
•
CHANNEL
DiffERENTIAL
AID
.ux
CD4D5Z
AID
fC~20
Hz
Uses Chebyshev implementation for steeper roll-off
unily-gain, 2nd order, tow-pess filter
B CHANNEL
SELECT
=--~---"
Adding a separate filter for each channel increases
system response time if an analog multiplexer
is used
FRGMOUTPUT
POATOApP
Output Buffers with AID Data Enabled
Increasing Bus Drive andlor Reducing Time on Bus
eI
AID
DATA*
cr_
eI _ _
iVJI_--,-",--/
AID
CI
TOIAP
DATA BUS
TRI·STATf~
TOpP
iVJI
BUFFERS
~-------------------------------------~
DATA IUS
DATA OUT
\Wi
AID
TRI-sTAT~
BUFFERS
~~-------------------------~
TLIH15671-10
• Allows output data to set-up at falling edge of CS
'AID output data is updated 1 ClK penod
prior to assertion of INTR
3-26
l:C
Typical Applications (Continued)
oo
...
CD
o
.....
Sampling an AC Input Signal
l:C
...
oo
'IN MAX
CD
o
SAMPLE
N
.....
AND
HOLD
LF391
l:C
fi.
lDW-PASS, MULTI·POLE
FILTER
CONTROL
1"
oo
Af.
c,
CD
o(0)
.....
l:C
oo
-I 1Jl..-'
_I tn, 1_ ....- -....._ _ _ _ _ _ _...J
CD
TC
o
.....
""
l:C
Nole 1: Oversample whenever possible [keep fs > 2f(-60)1to eliminate input frequency folding
(aliasing) and to allow for the skirt response of the filter.
o
o
Nole 2: Consider the amplitude errors which are introduced within the passband of the filter.
o
CD
U1
70% Power Savings by Clock Gating
(Complete shutdown takes'" 30 seconds.)
TO AID
Power Savings by AID and VREF Shutdown
5V~ON
.-
...-----()~C~DCI
r-------- 1
kO). If input bypass capacitors are necessary for noise filtering and high source resistance is desirable to minimize capacitor size, the detrimental effects of the voltage drop
across this input resistance, which is due to the average
value of the input current, can be eliminated with a full-scale
adjustment while the given source resistor and input bypass
capacitor are both in place. This is possible because the
average value of the input current is a precise linear function of the differential input voltage.
co
o
co
2.4 Reference Voltage
Fault Mode
If the voltage source applied to the VIN( +) or VIN( -) pin
exceeds the allowed operating range of Vee + 50 mY, large
input currents can flow through a parasitic diode to the Vee
pin. If these currents can exceed the 1 mA max allowed
spec, an external diode (1 N914) should be added to bypass
this current to the Vee pin (with the current bypassed with
this diode, the voltage at the VIN( +) pin can exceed the
Vee voltage by the forward voltage of this diode).
oo
......
"""
»
c
oo
co
o
U1
~r---------------------------------------------------------~
o
CO
8
c
Functional Description (Continued)
--
o
.....
......
»
c
oo
CI)
VANALOG OUTPUT
o
....»
N
c
oo
R
ANAL~g~~!g~ 0 -
""B""
1
R
""A""
R
A.I
R
CI)
o
"C"
AI
Co)
......
»
c
+
IOOR
1"
~
':'
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1
CI)
o
...."'»"
IOOX ANALOG
ERROR VOLTAGE
c
oo
CI)
FIGURE 8. AID Tester with Analog Error Output
".".,.,.,.,.A
DIGITAL
INPUT---y
OACIOOO
IO·BIT
OAC
r
o
U'I
AID UNDER
TEST
~OIGITAL
OUTPUT
TUH/5671-19
FIGURE 9. Basic "Digital" AID Tester
TABLE I. DECODING THE DIGITAL OUTPUT LEOs
FRACTIONAL BINARY VALUE FOR
BINARY
HEX
MSGROUP
F
OUTPUT VOLTAGE
CENTER VALUES
WITH
VREF/2 = 2.560 Voc
E
D
C
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
B
A
9
8
1
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
7
6
5
4
0
0
0
0
1
1
1
1
1
1
0
0
1
0
1
0
3
2
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
'Display Output= VMS Group
VLSGROUP'
4.800
4.480
4.160
3.840
0.300
0.280
0.260
0.240
11/256
3.520
3.200
9/256
2/880
2/560
0.220
0.200
0.180
0.160
71256
2.240
1.920
1.600
15/256
7/128
7/8
13/256
13/16
3/64
3/4
11/16
5/128
5/8
9/16
1/2
1/32
7/16
3/128
3/8
2/256
5/16
1/64
1/4
3/256
3/16
1/128
1/8
1/256
1/16
+
VMS GROUP'
LSGROUP
15/16
VLS Group
3-35
1/280
0.140
0.120
0.100
0.080
0.960
0.640
0.320
0
0.060
0.040
0.020
0
U) r-------------------------------------------------------------------------------~
o
CO
o
o
Functional Description (Continued)
c
0
~
..,.
~
INT(14)
I7lfWl\ (27)"
o
:g
I7lfIfIj (26)"
lDk
o
c
~
1
aoco
~
o
4
C
5
,
.......
»
c
CXI
..l!D
.".
0410
oo
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15 Dp'
AD
»
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o
$""'
Vee
CXI
....o
.......
oo
SVoc
2D
oo
: Program starts at addr 10
; Interrupt jumpvector
; Main program
; Chip select
;Readinthelstdata
; to reset the intr
; Set port pin high
; Data address
; Dummy address
; Counter for 16 bytes
; Set ACC for intr loop
; Send CS (bit 0 of Pl)
; Send WR out
; Enable interrupt
; Wai t for interrupt
; If 16 bytes are read
; go to user's program
; Input data, CS still low
; Store in memory
; Increment storage counter
; Reset CS signal
; ClearACCto get out of
; the interrupt loop
II)
i:
CI
o
C
c(
......
oo:r
i:
8c
c(
......
CO)
i:
CI
g
c(
......
i
4.2 Interfacing the Z-80
The Z·80 control bus is slightly different from that of the
8080. General RD and WR strobes are provided and separate memory request, MREQ, and 1/0 request, 10RQ, signals are used which have to be combined with the generalized strobes to provide the equivalent 8080 signals. An advantage of operating the AID in 1/0 space with the Z-80 is
that the CPU will automatically insert one wait state (the RD
and WR strobes are extended one clock period) to allow
more time for the 1/0 devices to respond. Logic to map the
AID in 1/0 space is shown in Figure 13.
CI
.....
....
i:
CI
o
cc(
The following subroutine performs essentially the same
function as in the case of the 8080A interface and it can be
called from anywhere in the user's program.
In Figure 15 the ADC0801 series is interfaced to the M6800
microprocessor through (the arbitrarily chosen) Port B of the
MC6820 or MC6821 Peripheral Interface Adapter, (PIA).
Here the CS pin of the AID is grounded since the PIA is
already memory mapped in the M6800 system and no CS
decoding is necessary. Also notice that the AID output data
lines are connected to the microprocessor bus under program control through the PIA and therefore the AID RD pin
can be grounded.
jjjj ...._ . . n J -....
AID
o
c
c(
ready decoded 4/5 line is brought out to the common bus at
pin 21. This can be tied directly to the CS pin of the AID,
provided that no other devices are addressed at HX ADDR:
4XXX or 5XXX.
Functional Description (Continued)
A sample interface program equivalent to the previous one
is shown below Figure 15. The PIA Data and Control Registers of Port B are located at HEX addresses 8006 and 8007,
respectively.
i'iii~-"VI._'"
MMJ4C3Z
TUH/5671-23
FIGURE 13. Mapping the AID as an 1/0 Device
for Use with the Z-80 CPU
5.0 GENERAL APPLICATIONS
Additional 110 advantages exist as software DMA routines
are available and use can be made of the output data transfer which exists on the upper 8 address lines (A8 to A 15)
during 110 input instructions. For example, MUX channel
selection for the AID can be accomplished with this operating mode.
The following applications show some interesting uses for
the AID. The fact that one particular microprocessor is used
is not meant to be restrictive. Each of these application circuits would have its counterpart using any microprocessor
that is desired.
5.1 Multiple ADC0801 Series to MC6800 CPU Interface
4.3 Interfacing 6800 Microprocessor Derivatives
(6502, etc.)
To transfer analog data from several channels to a single
microprocessor system, a multiple converter scheme presents several advantages over the conventional multiplexer
single-converter approach. With the ADC0801 series, the
differential inputs allow individual span adjustment for each
channel. Furthermore, all analog input channels are sensed
simultaneously, which essentially divides the microprocessor's total system servicing time by the number of channels,
since all conversions occur simultaneously. This scheme is
shown in Figure 16.
The control bus for the 6800 microprocessor derivatives
does not use the RD and WR strobe Signals. Instead it employs a single R/W line and additional timing, if needed, can
be derived fom the 2 clock. All 110 devices are memory
mapped in the 6800 system, and a special Signal, VMA,
indicates that the current address is valid. Figure 14 shows
an interface schematic where the AID is memory mapped in
the 6800 system. For simplicity, the CS decoding is shown
using % DM8092. Note that in many 6800 systems, an al-
,-----------------+1iiQ(4)*ID1**
.---------0< 1-+----.... RII'i 13'1 161
Of (321 (291
.N.lDG
INPUTS
0-+-1---;-;
021:111 (K)
AID
03(30) IH]
0-+-t---:-1
0'1"1 1321
085
12
00&
11
081
05 (28) 130J
061211 ILl
D11261 Iii
<:J-----<:J------
AIZ (22) [34]
A13 123) [iiI
'''12'1 IMI
AI5 (ZSI (33)
VMA (5) If I
Note 1: Numbers in parentheses refer to MC6S00 CPU pin out.
Note 2: Number or letters in brackets refer to standard M6BOO system common bus code.
lGNDUlll'IHI
414243
FIGURE 14. ADC0801-MC6800 CPU Interface
3-38
TL/H/5671-24
l>
C
0
0
co
Functional Description (Continued)
SAMPLE PROGRAM FOR FIGURE 14 ADC0801-MC6800 CPU INTERFACE
DF36
DATA IN
STX
TEMP2
; Save contents of X
CE 00 2C
LDX
; Upon IRQ low CPU
#$002C
FFFFFB
; jumps to 002C
STX
$FFFB
B7 50 00
STAA
; Start ADCOBOl
$5000
OE
CLI
3E
CONVRT
WAI
; Wait for interrupt
DE 34
LDX
TEMPl
BC 02 OF
CPX
; Is final data stored?
#$020F
2714
ENDP
BEQ
B7 50 00
STAA
; Restarts ADCOBOl
$5000
08
INX
DF34
STX
TEMPl
20FO
BRA
CONVRT
DE 34
INTRPT
LDX
TEMPl
B6 50 00
LDAA
; Read data
$5000
A700
STAA
X
: Store i t at X
3B
RTI
0200
TEMPl
: Starting address for
FDB
$0200
: data storage
TEMP2
FDB
0000
$0000
: Reini tialize TEMPl
CE 02 00
ENDP
LDX
#$0200
DF34
STX
TEMPl
DE 36
LDX
TEMP2
39
RTS
: Return from subroutine
: To user's program
0010
0012
0015
OOlB
OOlB
OOlC
OOlD
OOlF
0022
0024
0027
002B
002A
002C
002E
0031
0033
0034
0036
003B
003B
003D
003F
Note 1: In order for the microprocessor to service subroutines and interrupts, the stack pOinter must be dimensioned in the user's program.
lB
19
CBl
CB2
10k
r~ iiiiCS
\...J
VCC ~5V
19
ClK R
oBo 18
A~ Wii
081 17
ClK IN
150 PF
oB2 16
12
DB3 15
13
B
VINH
AGND
oB4 14
DBS 13
14
0;;
VREF/2
oB6 12
16
o GND
oB7 11
17
7
T
J,-;:
11
VIN(.)
5
6
ANALOG
INPUTS
10
INTR
AID
15
PBO
PIA
PBl
P82
PB3
PB4
PBS
PB6
PB7
Tl/H/5671-25
FIGURE 15. ADC0801-MC6820 PIA Interface
3-39
0
....
......
l>
C
0
0
CO
0
N
......
l>
C
0
0
CO
0
Co)
......
l>
C
0
0
CO
0
......
"'"
l>
C
0
0
CO
0
U1
U)
o
CD
o
o
c
~o
CD
o
o
C
Functional Description
c
o
C)
(Continued)
co
C)
5Voc
....
);
C
o
C)
co
C)
5V
'----:+\ VINltJ
,---'+I
AI.
N
.......
l>
VIN(-I
c
o
C)
co
w
.......
l>
C)
c
o
C)
co
If
C)
-12V
"'"
);
if
v"
5VUC
lOOk
if
SWI
C
o
200.
if
190.
if
FRQMDUTPUT
PDRTIBUfFER
(FIGURE")
"
C)
co
C)
U1
....--'\/""--.......
In•
1.56M
+--.J\I'''''''-_ii"
J.16M
'--J\f',"""'-_H
FROMDUTPUT
PORTC
IFIBUREIIi}
[~
sw.
ff'-~-----------------------~-~
Nole I: R2
= 49.5 R1
Nole 2: Switches are LMC13334 CMOS analog switches.
Note 3: The 9 resistors used in the
auto~zero
section can be ± 5% tolerance.
FIGURE 17. Gain of 100 Differential Transducer Preamp
..
Aii 85
At 84
80l1lAADDRESSBUS
:u
INVERTING
ADDRESS
BUFFERS
83
Ai 82
T5
OMI13I
AJ 81
Af"
T3
T1
T1
OUTPUT
T'
5V
5V
ts
AURO AD
A/DOUTPUT DATA
ADRI At
...
.]
"
RIC
151JpF
-;J;'
If}
•
~
TO "SAR"
RESISTORS
f1 TOSWI
corOSW2
TL/H/5671-27
FIGURE 18. Microprocessor Interface Circuitry for Differential Preamp
\
\
\~
3-43
It)
C)
co
C)
g
c(
....
oo:r
C)
co
8
c
c(
....
Cf)
C)
co
C)
o
~
N
C)
co
C)
g
c(
....
,..
C)
co
C)
o
cc(
A flow chart for the zeroing subroutine is shown in Figure
19. It must be noted that the ADC0801 series will output an
all zero code when it converts a negative input [VIN( -) ~
VIN( + )1. Also, a logic inversion exists as all of the I/O ports
are buffered with inverting gates.
Basically, if the data read is zero, the differential output voltage is negative, so a bit in Port B is cleared to pull Vx more
negative which will make the output more positive for the
next conversion. If the data read is not zero, the output voltage is positive so a bit in Port B is set to make Vx more
positive and the output more negative. This continues for 8
approximations and the differential output eventually converges to within 5 mV of zero.
The actual program is given in Figure 20. All addresses
used are compatible with the BLC 80/10 microcomputer
system. In particular:
Port A and the ADC0801 are at port address E4
Port B is at port address E5
Port C is at port address E6
PPI control word port is at port address E7
Program Counter automatically goes to ADDR:3C3D upon
acknowledgement of an interrupt from the ADC0801
5.3 Multiple AID Converters In a Z-BO Interrupt
Driven Mode
In data acquisition systems where more than one A/D converter (or other peripheral device) will be interrupting program execution of a microprocessor, there is obviously a
need for the CPU to determine which device requires servicing. Figure 21 and the accompanying software is a method
of determining which of 7 ADC0801 converters has completed a conversion (INTR asserted) and is requesting an
interrupt. This circuit allows starting the AID converters In
any sequence, but will input and store valid data from the
converters with a priority sequence of AID 1 being read first,
AID 2 second, etc., through AID 7 which would have the
lowest priority for data being read. Only the converters
whose INT is asserted will be read.
The key to decoding circuitry is the DM74LS373, 8-bit D
type flip-flop. When the Z-80 acknowledges the interrupt,
the program is vectored to a data input Z-80 subroutine.
This subroutine will read a peripheral status word from the
DM74LS373 which contains the logic state of the INTR outputs of all the converters. Each converter which initiates an
interrupt will place a logic "0" in a unique bit position in the
status word and the subroutine will determine the identity of
the converter and execute a data read. An identifier word
(which indicates which AID the data came from) is stored in
the next sequential memory location above the location of
the data so the program can keep track of the identity of the
data entered.
··EXCLUSIVE-OR··
REG BWITH REG C
TO SET NEXT BIT
IN PORTH
TL/H/5671-2B
FIGURE 19. Flow Chart for Auto-Zero Routine
3-44
.--------------------------------------------------------------------.~
:moo
3D02
3D04
3D06
3D07
3D09
3DOB
3DOD
3DOE
3D10
3D13
3D15
3D16
3D17
3D1A
3D1B
3D1D
3D20
3D21
3D23
3D24
3D26
3D29
3D2A
3D2D
3D2E
3D2F
3D30
3D33
3D34
3D37
3D38
3D39
3D3B
3D 3D
3C3D
3C3F
3C41
3C42
3C43
3C45
3C48
3E90
D3E7
2601
7C
D3E6
0680
3E7F
4F
D3E5
31AA3D
D3E4
FB
00
C3163D
7A
C600
CA2D3D
78
F600
IF
FEOO
CA373D
47
C3:533D
79
BO
4F
C3203D
A9
C30D3D
47
7C
EE03
D3E6
DBE4
EEFF
57
78
E6FF
C21A3D
C33D3D
MVI90
Out Control Port
MVI HOl
MOV A,H
OUT C
MVI B 80
MVIA 7F
MOV C,A
OUTB
LXI SP 3DAA
OUT A
IE
NOP
JMP Loop
MOVA,D
ADIOO
JZ Set C
MOVA,B
ORIOO
RAR
CPIOO
JZ Done
MOVB,A
JMPNewC
MOVA,C
ORAB
MOV C,A
JMP Shift B
XRAC
JMPReturn
MOVB,A
MOVA,H
XRI03
OUT C
•
•
•
c
; Program PPI
CI)
Auto-Zero Subroutine
; Close SWl open SW2
; Initialize SAR bit pointer
; Initialize SAR code
Return
=
; Port B SAR code
; Dimension stack pointer
; Start AID
Start
Loop
; Loop until INT asserted
Auto-Zero
; Test AID output data for zero
Shift B
~
c
(')
Q
CI)
Q
I\)
......
~
c
Q
CI)
Q
Co)
......
~
c
(')
Q
CI)
;
;
;
;
Clear carry
Shift "1" in B right one place
Is B zero? I f yes last
approximat ion has been made
Q
01:00
i>
c
(')
Q
CI)
Q
en
Set C
; Set bit in C that is in same
; posi tion as "1" in B
; Clear bit in C that is in
; same posi tion as "1" in B
; then output new SAR code.
; Open SW1, close SW2 then
; proceed with program. Preamp
; is now zeroed.
NewC
Done
Read AID Subroutine
; Read AID data
; Invert data
=
; Is B Reg O? If not stay
; in auto zero subroutine
Note: All numerical values are hexadecimal representations.
FIGURE 20. Software for Auto·Zeroed Differential AID
5.3 Multiple AID Converters in
Mode (Continued)
Q
.....
......
(')
Normal
Program for processing
proper data values
INA
XRI FF
MOVD,A
MOVA,B
ANI FF
JNZ Auto-Zero
JMPNormal
(')
Q
a Z-80® Interrupt Driven
The following notes apply:
5) The peripherals of concern are mapped into I/O space
1) It is assumed that the CPU automatically performs a RST
7 instruction when a valid interrupt is acknowledged (CPU
is in interrupt mode 1). Hence, the subroutine starting address of XOOSB.
with the following port assignments:
HEX PORT ADDRESS
PERIPHERAL
00
MM74C374 8-bit flip-flop
01
AID 1
02
AlD2
03
AlD3
04
AlD4
AID 5
05
06
AlD6
07
AlD7
This port address also serves as the AID identifying word in
the program.
2) The address bus from the Z-80 and the data bus to the Z80 are assumed to be inverted by bus drivers.
3) AID data and identifying words will be stored in sequential memory locations starting at the arbitrarily chosen address X SEOO.
4) The stack pOinter must be dimensioned in the main program as the RST 7 instruction automatically pushes the
PC onto the stack and the subroutine uses an additional
6 stack addresses.
3-45
U) r---------------------------------------------------------------------------------~
o
CO
o
.y
o
C
~
DM'''M
(Note 3)
Temperature Range (Note 1)
ADCOBOBCCJ, ADCOBOBCCN,
ADCOB09CCN
-0.3V to (Vee+0.3V)
-40'C:S;TA:S; + BS'C
-40'C:s; TA:S; +BS'C
ADCOBOBCCV, ADCOB09CCV
Except Control Inputs
Voltage at Control Inputs
(")
TMIN:S;TA:S;TMAX
-SS'C:S;TA:S; + 12S'C
ADCOBOBCJ
6.SV
Voltage at Any Pin
»
c
Operating Conditions (Notes 1 & 2)
(Noles 1 & 2)
Range of Vee (Note 1)
-0.3Vto +1SV
4.S Voe to 6.0 Voe
(START, OE, CLOCK, ALE, ADD A, ADD B, ADD C)
Storage Temperature Range
- 6S'C to + 1S0'C
Package Dissipation at T A= 2S'C
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
Molded Chip Carrier Package
Vapor Phase (60 seconds)
Infrared (1S seconds)
ESD Susceptibility (Note 11)
B7SmW
260'C
300'C
21S'C
220'C
400V
Electrical Characteristics
Converter Specifications: Vee=S Voe=VREF+, VREF(-)=GND, TMIN:S;TA:S;TMAX and feLK=640 kHz unless otherwise
stated.
Symbol
Parameter
ADCOBOB
Total Unadjusted Error
(NoteS)
Conditions
Min
Typ
Max
Units
±%
±%
LSB
LSB
±1
±1%
LSB
LSB
Vee+ O.1O
Voe
Vee
Vee + 0.1
V
Vee/2
Vee/2 + O.1
V
2
/LA
2S'C
TMINtoTMAX
ADCOB09
Total Unadjusted Error
(NoteS)
TMIN toTMAX
O'Cto 70'C
Input Resistance
From Ref( + ) to Ref( -)
1.0
Analog Input Voltage Range
(Note 4) V(+) orV(-)
GND-0.10
VREF(+)
Voltage, Top of Ladder
Measured at Ref( + )
VREF1+I+VREF1-1
2
Voltage, Center of Ladder
VREF(-)
Voltage, Bottom of Ladder
Measured at Ref( -)
-0.1
0
liN
Comparator Input Current
fe = 640 kHz, (Note 6)
-2
±O.S
Vee/2-O.1
2.S
kO
V
Electrical Characteristics
Digital Levels and DC Specifications: ADCOBOBCJ 4.SV:S;Vee:S;S.SV, -SS'C:S;TA:S;+12S'C unless otherwise noted
ADCOBOBCCJ, ADCOBOBCCN, ADCOBOBCCV, ADCOB09CCN and ADCOB09CCV, 4.7S:S;Vee:S;S.2SV, -40'C:S;TA:S; + BS'C unless otherwise noted
Symbol
Parameter
Conditions
OFF Channel Leakage Current
Vee=SV, VIN=SV,
TA=2S'C
TMINtoTMAX
Min
Typ
Max
Units
10
200
1.0
/LA
ANALOG MULTIPLEXER
IOFF(+)
IOFF(-)
OFF Channel Leakage Current
Vee=SV, VIN=O,
TA=2S'C
TMINtoTMAX
3-49
-200
-1.0
-10
nA
nA
/LA
oQ)
oQ)
.......
»
c
(")
oQ)
o
CD
Electrical Characteristics
(Continued)
Digital Levels and DC Specifications: ADC0808CJ 4.5V~Vcc~5.5V, - 55"C~TA ~ + 125"C unless otherwise noted
ADC0808CCJ, ADC0808CCN, ADC0808CCV, ADC0809CCN and ADC0809CCV, 4.75~Vee~5.25V, -40"C~TA~ + 85"C unless otherwise noted
Symbol
I
Parameter
I
Conditions
I
I
Min
Typ
I
Max
I
Units
CONTROL INPUTS
VIN(I)
Logical "1" Input Voltage
VIN(O)
Logical "0" Input Voltage
1.5
V
IIN(I)
Logical "1" Input Current
(The Control Inputs)
VIN=15V
1.0
p.A
IIN(O)
Logical "0" Input Current
(The Control Inputs)
VIN=O
lee
Supply Current
feLK=640 kHz
V
Vee- 1.5
-1.0
p.A
0.3
3.0
mA
DATA OUTPUTS AND EOC (INTERRUPT)
VOUT(I)
Logical "1" Output Voltage
IO=-360p.A
VOUT(O)
Logical "0" Output Voltage
lo=1.6mA
0.45
V
V
VOUT(O)
Logical "0" Output Voltage EOC
lo=1.2mA
0.45
V
lOUT
TRI-STATE Output Current
Vo=5V
Vo=O
3
p.A
p.A
Vee- 0•4
-3
Electrical Characteristics
Timing Specifications VCC=VREF(+)=5V, VREF(-)=GND, t,=tf=20 ns and TA=25"C unless otherwise noted.
Symbol
Typ
Max
Units
tws
Minimum Start Pulse Width
(Figure 5)
Conditions
100
200
ns
Parameter
Min
twALE
Minimum ALE Pulse Width
(Figure 5)
100
200
ns
is
Minimum Address Set-Up Time
(Figure 5)
25
50
ns
tH
Minimum Address Hold Time
(Figure 5)
25
50
ns
to
Analog MUX Delay Time
From ALE
Rs =
1
2.5
p.S
ns
on (Figure 5)
tHl, tHO
OE Control to Q Logic State
CL =50 pF, RL =10k(Agure8)
125
250
tlH, tOH
OE Control to Hi-Z
CL = 10 pF, RL =10k (Agure8)
125
250
ns
te
Conversion Time
fe = 640 kHz, (Figure 5) (Note 7)
90
100
116
p.S
fe
Clock Frequency
10
640
1280
kHz
tEoe
EOC Delay Time
(Agure5)
8+2 p.S
Clock
Periods
CIN
Input Capacitance
At Control Inputs
15
pF
0
10
TRI-STATE Output
AtTRI-STATE Outputs, (Note 12)
10
15
pF
CaUT
Capacitance
Note 1: Absolute Maximum Ratings indicate IimHs beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating condHions.
Note 2: All voltages are measured with respect to GND. unless othewise specified.
Note 3: A zener diode exists. internally, from Vee to GND and has a typical breakdown voltage of 7 Vee.
Note 4: Two on·chip diodes are tied to each analog Input which will forward conduct for analog input voltages one diode drop below ground or one diode drop
greater than the Vccn supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage
by more than 100 mV, the output code will be correct To achieve an absolute OVec to SVec input voltage range will therefore require a minimum supply voltage of
4.900 Vee over temperature variations, initial tolerance and loading.
Note 5: Total unadjusted error includes offset, full·scale, linearity, and multiplexer errors. See F'lfJure 3. None of these AIDs requires a zero or full·scale adiust.
However, ff an all zero code is desired for an analog input other than O.OV, or if a narrow full·scale span exists (for example: O.SV to 4.SV full·scale) the ,eference
voltages can be adjusted to achieve this. See Figure 13.
Note 6: Comparator input current Is a bias current Into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has
IHUe temperature dependence (Figure 6). See paragraph 4.0.
Note 7: The outputs of the data register are updated one clock cycle before the rising edge of EOC.
Note 8: Human body model, 100 pF discharged through a 1.5 kO resistor.
3-50
r-----------------------------------------------------------------------,~
C
Functional Description
Multiplexer. The device contains an a·channel single-ended analog signal multiplexer. A particular input channel is
selected by using the address decoder. Table I shows the
input states for the address lines to select any channel. The
address is latched into the decoder on the low-to-high transition of the address latch enable signal.
TABLE I
SELECTED
to give fast, accurate, and repeatable conversions over a
wide range of temperatures. The converter is partitioned
into 3 major sections: the 256R ladder network, the successive approximation register, and the comparator. The converter's digital outputs are positive true.
The 256R ladder network approach (Figure 1) was chosen
over the conventional R/2R ladder because of its inherent
monotonicity, which guarantees no missing digital codes.
Monotonicity is particularly important in closed loop feedback control systems. A non-monotonic relationship can
cause oscillations that will be catastrophic for the system.
Additionally, the 256R network does not cause load variations on the reference voltage.
ADDRESS LINE
ANALOG CHANNEL
C
B
A
INO
IN1
IN2
IN3
IN4
IN5
IN6
IN7
L
L
L
L
L
L
H
H
H
H
L
L
H
H
H
H
H
H
H
H
L
L
The bottom resistor and the top resistor of the ladder network in Figure 1 are not the same value as the remainder of
the network. The difference in these resistors causes the
output characteristic to be symmetrical with the zero and
full-scale points of the transfer curve. The first output transition occurs when the analog signal has reached + % LSB
and succeeding output transitions occur every 1 LSB later
up to full-scale.
L
L
CONVERTER CHARACTERISTICS
The successive approximation register (SAR) performs a iterations to approximate the input voltage. For any SAR type
converter, n-iterations are required for an n-bit converter.
Figure 2 shows a typical example of a 3-bit converter. In the
ADCOaOa, ADCOa09, the approximation technique is extended to a bits using the 256R network.
The Converter
The heart of this single chip data acquisition system is its abit analog-to-digital converter. The converter is designed
CONTROLS FROM S.A.R.
I
REF(+)
TO
COMPARATOR
INPUT
256R
REFH
TL/H/5672-2
FIGURE 1. Resistor Ladder and Switch Tree
3-51
oc
co
c
co
.......
~
c
oc
co
c
CD
~
I
o
Q
0
...J
::l
>
0
c..
:>
TL/H/5672-11
0
Order Number ADC0808CCN, ADC0809CCN,
ADC0808CCJ or ADC0808CJ
See NS Package J28A or N28A
TLiH/5672-12
Order Number ADC0808CCV or ADC0809CCV
See NS Package V28A
Timing Diagram
I-,n--l
CLOCK
r---I
START
sa.
'''''
I
I--IWS-
ALE
-'''''~N
I
I
-IWALE-I
STABLE ADDRESS
I-- C
ADDRESS
I
SO.
S""
-
ts l- i -
ANALOG
INPUT
I
'.
;
STABLE
S~f.COMPARATOR
INPUT
CINTERNAL NODE)
X
:
X
i-
X
'0-
OUTPUT
ENABLE
/
I
Eoe
--tEOt
I
-±
I
te
SO'1
.J}_
OUTPUTS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .!.R!!"~E_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _{\._ _ _ _ _
TL/H/5672-4
FIGURE 5
3-53
en
o
!
o
C
r---------------------------------------------------------------------------------,
Typical Performance Characteristics
-1
o L -_ _- ' -_ _---L_ _ _ _. L -_ _....I
1.25
2.5
o
3.75
VIN (V)
1.25
2.5
3.75
VIN(V)
TL/H/5672-5
FIGURE 6. Comparator liN vs VIN
FIGURE 7. Multiplexer RON vs VIN
(Vee = VREF= 5V)
(Vee = VREF= 5V)
TRI-STATE Test Circuits and Timing Diagrams
Vee
OUTPUT
Vee
ENABLE
GND ---!!!~'-------
OUTPUT
VOH~:IH
ENABLE
~
OUTPUT
GND
/5-0
-----.1
%
-
tHO. CL = 50 pF
tOH. CL = 10 pF
toH. tHO
vee
------------'==
I~
10H
vee
OUTPUT
vee
ENABLE
GND
OUTPUT
ENABLE
Vee
OUTPUT
':"
VOL
~
-10%
.{
TUH/5672-6
FIGURES
3-54
Applications Information
Ratiometric transducers such as potentiometers, strain
gauges, thermistor bridges, pressure transducers, etc., are
suitable for measuring proportional relationships; however,
many types of measurements must be referred to an absolute standard such as voltage or current. This means a system reference must be used which relates the full-scale
voltage to the standard volt. For example, if
VCC=VREF=5.12V, then the full-scale range is divided into
256 standard steps. The smallest standard step is 1 LSB
which is then 20 mY.
OPERATION
1.0 RATIOMETRIC CONVERSION
The ADCOBOB, ADCOB09 is designed as a complete Data
Acquisition System (DAS) for ratiometric conversion systems. In ratiometric systems, the physical variable being
measured is expressed as a percentage of full-scale which
is not necessarily related to an absolute standard. The voltage input to the ADCOBOB is expressed by the equation
VIN
Dx
Vls-VZ DMAX-DMIN
VIN = Input voltage into the ADCOBOB
(1)
Vis = FUll-scale voltage
Vz = Zero voltage
Dx=Data point being measured
DMAX=Maximum data limit
DMIN = Minimum data limit
A good example of a ratiometric transducer is a potentiometer used as a position sensor. The position of the wiper is
directly proportional to the output voltage which is a ratio of
the full-scale voltage across it. Since the data is represented as a proportion of full-scale, reference requirements are
greatly reduced, eliminating a large source of error and cost
for many applications. A major advantage of the ADCOBOB,
ADCOB09 is that the input voltage range is equal to the supply range so the transducers can be connected directly
across the supply and their outputs connected directly into
the multiplexer inputs, (Figure 9).
2.0 RESISTOR LADDER LIMITATIONS
The voltages from the resistor ladder are compared to the
selected into B times in a conversion. These voltages are
coupled to the comparator via an analog switch tree which
is referenced to the supply. The voltages at the top, center
and bottom of the ladder must be controlled to maintain
proper operation.
The top of the ladder, Ref( +), should not be more positive
than the supply, and the bottom of the ladder, Ref( -),
should not be more negative than ground. The center of the
ladder voltage must also be near the center of the supply
because the analog switch tree changes from N-channel
switches to P-channel switches. These limitations are automatically satisfied in ratiometric systems and can be easily
met in ground referenced systems.
Figure 10 shows a ground referenced system with a separate supply and reference. In this system, the supply must
be trimmed to match the reference voltage. For instance, if
a 5.12V is used, the supply should be adjusted to the same
voltage within 0.1 V.
)o-"'--411cc
I - -...- - - - - - - - - - I R E F ( + )
la7
·••
laD
REFH
L-------------~~~GND
DIGITAL OUTPUT
REFERENCED TO
GROUND
QOUT~~
VREF
4.7SV ,; vee - VREF ,; S.2SV
ADCOBoa
TL/H/5672-B
FIGURE 11: Ground Referenced Conversion System with
Reference Generating Vee Supply
3·56
)0
Applications Information
C
g
(Continued)
10-15VoC
C»
o
C»
.....
)0
lk
C
o
o
1000 pF
RI
C»
o
CD
LM3Z9B
Vcc
RZ
lOT
> ...._ ...-.REF(+)
DIGITAL OUTPUT
PROPORTIONAL TO
ANALOG INPUT
1.Z5V::; VIN ::; 3.7SV
RA=Re
*Ratiometric transducers
TL/H/5672-9
FIGURE 13. Symmetrically Centered Reference
3.0 CONVERTER EQUATIONS
4.0 ANALOG COMPARATOR INPUTS
The transition between adjacent codes Nand N + 1 is given
by:
The dynamic comparator input current is caused by the peri·
odic switching of on·chip stray capacitances. These are
connected altemately to the output of the resistor ladderl
switch tree network and to the comparator input as part of
the operation of the chopper stabilized comparator.
VIN=
{(VREF(+)-VREF(-))L~6 + 5~2) ±VTUE} +VREF(-)
(2)
The center of an output code N is given by:
VIN{
(VREF(+)-VREF(-))[2~6] ±VTUE} +VREF(-)
The average value of the comparator input current varies
directly with clock frequency and with Y,N as shown in Figure6.
(3)
The output code N for an arbitrary input are the integers
within the range:
N
VIN-VREFI-) X256±AbsoluleAccuracy
VREF(+)-VREF(-)
If no filter capacitors are used at the analog inputs and the
signal source impedances are low, the comparator input
current should not introduce converter errors, as the transient created by the capacitance discharge will die out before the comparator output is strobed.
(4)
where: V'N=Voltage at comparator input
VREF(+)=Voltage at Ref(+)
If input filter capacitors are desired for noise reduction and
signal conditioning they will tend to average out the dynamic
comparator input current. It will then take on the characteristics of a DC bias current whose effect can be predicted
conventionally.
VREF(-)=Voltage at Ref(-)
VTUE=Total unadjusted error voltage (typically
VREF(+)+512)
3-57
Typical Application
~--~r-'>o-
______________________,
t-_...-----+INTERRUPT
ADDRESS
mm
(AD4-AD15)*
MSB
ADCII8O.
ADCG809
LSB
....._--!VCC
..---fGND
VINB}
1I-5V
ANALOG
INPUT RANGE
•
VIN'
Tl/H/5672-10
•Address latches needed for 8085 and SC/MP Interfacing 1he ADC0808 to a microprocessor
MICROPROCESSOR INTERFACE TABLE
PROCESSOR
8080
8085
Z-80
SC/MP
6800
READ
MEMR
RD
WRITE
INTERRUPT (COMMENT)
MEMW
lID
WR
WR
NRDS
VMA-.,.2-R/W
NWDS
VMA-.,.-R/W
INTR (Thru RST Circuit)
INTR (Thru RST Circuit)
INT (Thru RST Circuit, Mode 0)
SA (Thru Sense A)
IROA or IROB (Thru PIA)
Ordering Information
- 40"C to
TEMPERATURE RANGE
Error
+8SoC
± Yz LSB Unadjusted
ADC0808CCN
ADC0808CCV
± 1 LSB Unadjusted
ADC0809CCN
ADC0809CCV
N28A Molded DIP
V28A Molded Chip Carrier
Package Outline
3-58
-S5"Cto
+ 125"C
ADC0808CCJ
ADC0808CJ
J28A Ceramic DIP
J28A Ceramic DIP
.-----------------------------------------------------------,~
c
oc
~ Semiconductor
NatiOnal
......
Q)
Corporation
ADC0811 8-Bit Serial 110 AID Converter
With 11-Channel Multiplexer
General Description
The ADC0811 is an 8-Bit successive approximation AID
converter with simultaneous serial 1/0. The serial input controls an analog multiplexer which selects from 11 input
channels or an internal half scale test voltage.
An input sample-and-hold is implemented by a capacitive
reference ladder and sampled data comparator. This allows
the input signal to vary during the conversion cycle.
Separate serial 1/0 and conversion clock inputs are provided to facilitate the interface to various microprocessors.
Features
• Separate asynchronous converter clock and serial data
1/0 clock.
• II-Channel multiplexer with 4-Bit serial address logic.
• Built-in sample and hold function.
Connection Diagrams
•
•
•
•
•
•
Ratiometric or absolute voltage referencing.
No zero or full-scale adjust required.
Internally addressable test voltage.
OV to 5V input range with single 5V power supply.
TTLIMOS input/output compatible.
0.3" standard width 20-pin dip or 20-pin molded chip
carrier
Key Specifications
•
•
•
•
•
8-Bits
Resolution
Total unadjusted error
Single supply
Low Power
Conversion Time
± 'hLSB and ± 1LSB
5VDC
15mW
32 ",S
Functional Diagram
Dual-In-Line Package
Vee
120
CHo
20
Vee
CHI
19
2CLK
01'
CH2
18
SeLK
CH3
17
01
CH4
16
DO
CH5
15
CS
CH6
14
VREF
CH7
13
AGND
12
CHID
11
CH9
CH8
GNO
10
Top View
ADDRESS
LATCH AND
DECODER
1+_-+_ _ _~15 CS
CONTROL
AND
TIMING
18 SeL'
1+_-+_....___
TL/H/5587-1
Molded Chip Carrier (PCC) Package
SeL' 01
DO
CS VREF
2CL'
19
AGNo
Vee
20
CHID
CHo
CH9
CHI
GND
CH2
CH8
VTEST
110
GND
1
13
AGND
TLlH/5587-3
CH3 CH4 CH5 CH6 CH7
Top View
TLlH/5587-2
Order Number ADC0811J,N,V
See NS Packages J20A, N20A, V20A
Use Ordering Information
3-59
....co
8c
c(
Absolute Maximum Ratings (Notes 1 & 2)
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
Molded Chip Carrier Package
Vapor Phase (SO seconds)
Infrared (1S seconds)
ESD Susceptibility (Note 11)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (Veel
S.SV
Voltage
Inputs and Outputs
-0.3VtoVee +0.3V
Input Current Per Pin (Note 3)
±SmA
Total Package Input Current (Note 3)
±20mA
Storage Temperature
-SS'C to + 1S0'C
Package Dissipation at TA = 2S'C
87SmW
2S0'C
300'C
21S'C
220'C
2000V
Operating Ratings (Notes 1 & 2)
Supply Voltage (Veel
Temperature Range
ADC0811 BCN, ADC0811 CCN
ADC0811 BCJ, ADC0811 BCV
ADC0811CCJ, ADC0811CCV
ADC0811BJ, ADC0811CJ
4.S Voe to S.O Voe
TMIN~TA~TMAX
O'C~TA~70'C
-40'C~TA~8S'C
-40'C~TA~8S'C
-SS'C~TA~ 12S'C
Electrical Characteristics
The following specifications apply for Vee = 4.7SV to 5.25V, VREF = +4.SV to (Vee + O.W), 2 eLK = 2.097 MHz unless
otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA = TJ = 2S'C.
ADC0811BCJ, ADC0811BJ
ADC0811CCJ, ADC0811CJ
Parameter
Conditions
Typical
(Note 6)
Tested
Limit
(Note 7)
ADC0811 BCN, ADC0811BCV
ADC0811CCN, ADC0811CCV
Design
Typical
Limit
(Note 6)
(Note 8)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Units
±'h
±%
±1
±1
LSB
LSB
LSB
LSB
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Maximum Total
VREF = 5.00 Voe
Unadjusted Error
(Note 4)
ADC0811 BCN, ADC0811 BCV
ADCOB11 BCJ, ADC0811 BJ
ADC0811 CCN, ADC0811 CCV
ADC0811CCJ, ADC0811CJ
±%
±1
Minimum Reference
Input Resistance
8
Maximum Reference
Input Resistance
8
Maximum Analog Input Range
(NoteS)
Minimum Analog Input Range
On Channel Leakage Current
ADC0811 BCJ, CCJ, BCN, CCN, On Channel = SV
BCV,CCV Off Channel = OV
ADC0811CJ, BJ
ADC0811BCJ, CCJ, BCN, CCN, On Channel = OV
BCV,CCV Off Channel = SV
ADC0811 BJ, CJ
(Note 9)
Off Channel Leakage Current
ADC0811BCJ, CCJ, BCN, CCN, On Channel = 5V
BCV,CCV Off Channel = OV
ADC0811CJ, BJ
ADC0811BCJ, CCJ, BCN, CCN, On Channel=OV
BCV,CCV Off Channel = 5V
ADC0811BJ, CJ
(Note 9)
5
11
Vee + 0.05
GND-0.05
1000
8
8
11
5
kO
11
kO
Vee+ O.OS Vee + 0.05
GND-O.OS GND-0.05
400
1000
1000
-1000
-400
-1000
nA
nA
nA
-400
1000
-1000
1000
V
nA
-1000
-1000
V
nA
nA
400
1000
nA
1000
nA
Minimum VTEST
Internal Test Voltage
VREF=Vee,
CH 11 Selected
125
125
125
(Note 10)
Counts
Maximum VTEST
Internal Test Voltage
VREF=Vee,
CH 11 Selected
130
130
130
(Note 10)
Counts
3-S0
:J>
Electrical Characteristics
C
The following specifications apply for Vee = 4.7SV to S.2SV. VREF = +4.6V to (VCC + 0.1V). <1>2 ClK = 2.097 MHz unless
otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA = TJ = 2SoC. (Continued)
co
....
....
ADC0811BCN, ADC0811BCV
ADC0811CCN, ADC0811 CCV
ADC0811BCJ, ADC0811BJ
ADC0811CCJ, ADC0811CJ
Parameter
Conditions
Typical
(Note 6)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Typical
(Note 6)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Units
DIGITAL AND DC CHARACTERISTICS
VIN(1). Logical "1" Input
Voltage (Min)
Vcc=S.2SV
2.0
2.0
2.0
V
VIN(O). Logical "0" Input
Voltage (Max)
Vcc=4.7SV
0.8
0.8
0.8
V
IIN(1). Logical "1" Input
Current (Max)
VIN=S.OV
IIN(O). Logical "0" Input
Current (Max)
VIN=OV
VOUT(1t Logical "1"
Output oltage (Min)
Vcc=4.7SV
lOUT = - 360 /LA
IOUT= -10 /LA
VOUT(Ot Logical "0"
Output oltage (Max)
Vcc=S.2SV
IOUT=1.6mA
lOUT. TRI-STATE Output
Current (Max)
VOUT=OV
VOUT=SV
-0.01
0.01
-3
3
ISOURCE. Output Source
Current (Min)
VOUT=OV
-12
O.OOS
2.5
O.OOS
2.S
2.5
",A
-O.OOS
-2.5
-O.OOS
2.S
-2.5
",A
2.4
4.S
V
V
0.4
2.4
4.5
0.4
-0.Q1
0.01
-3
3
-3
3
",A
",A
-6.5
-14
-6.S
-6.5
mA
8.0
2.5
1
16
8.0
1
2.S
mA
0.7
1
8.0
2.5
1
2.4
4.5
0.4
ISINK. Output Sink Current (Min)
VOUT=VCC
18
Icc. Supply Current (Max)
CS=l. VREFOpen
1
IREF(Max)
VREF=SV
0.7
V
mA
mA
AC CHARACTERISTICS
Parameter
<1>2 ClK. <1>2 Clock Frequency
SClK. Serial Data Clock
Frequency
Tc. Conversion Process Time
Conditions
MIN
0.70
MAX
3.0
-
Falling Edge to DO Data Valid
700
Not Including MUX
Addressing and
Analog Input
MAX
Sampling Times
48
48
64
64
MIN
MIN
1
MAX
3
t---
~
MAX
tHOO. Minimum DO Hold Time from SClK
Falling Edge
0
Rl =30k.
Cl =100 pF
3-61
MHz
KHz
525
MAX
tHCS. CS Hold Time After the Falling
EdgeofSclK
tHOI> Minimum DI Hold Time from
SClK Rising Edge
S2S
Units
2.1
5.0
tSET-UP. Minimum Set-up Time of CS Falling
Edge to SClK Rising Edge
t CS. Total CS Low Time
Design
Limit
(Note 8)
1.0
2.0
MIN
-
t--tACC. Access Time Delay From CS
Tested
Typical
Limit
(Note 6) (Note 7)
<1>2 cycles
<1>2 cycles
1
4/2CLK+UCLK
sec
0
ns
tsat.up + 8/SCLK
sec
t cs(mln) + 48/ 2CLK
sec
0
ns
10
ns
oc
Electrical Characteristics
The following specifications apply for Vcc = 4.75V to 5.25V, "REF = +4.6V to (VCC + 0.1V), <1>2 CLK = 2.097 MHz unless
otherwise specified. Boldface limits apply from T MIN to TMAX; all other limits T A = T J = 25°C. (Continued)
Parameter
Tested
Typical
Conditions
(Note 6)
Design
Limit
Limit
(Note
Units
(Note 8)
7)
AC CHARACTERISTICS (Continued)
1$010 Minimum 01 Set-up Time to SCLK
200
Rising Edge
toDO, Maximum Delay From SCLK
RL =30k,
Falling Edge to DO Data Valid
tTRI, Maximum DO Hold Time,
CL=100pF
400
ns
180
400
400
ns
90
150
150
ns
4/ScLK+1 ",.
sec
RL =3k,
(CS Rising edge to DO
CL=100pF
TRI-STATE)
tCA,Analog
Sampling Time
After Address Is Latched
CS=Low
tROD, Maximum DO
RL =30 k!l,
"TRI-STATE" to "HIGH" State
75
150
150
Rise Time
CL=100pf
"LOW" to "HIGH" State
150
300
300
tFOO, Maximum DO
RL =30k!l,
"TRI-STATE" to "LOW" State
Fall Time
CL=100pf
"HIGH" to "LOW" State
CIN, Maximum Input
Analog Inputs, ANO-AN10 and VREF
Capacitance
All Others
75
150
150
150
300
300
11
55
5
15
ns
ns
pF
Nate 1: Absolute Maximum Ratings indicate limits beyond which damage 10 the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Nate 2: All voltages are measurad with respect to ground.
Nate 3: Under over voltage conditions (VINVcclthe maximum input current at anyone pin is ±S mA.1f the voltage at more than one pin exceeds
Vee + .3V the total package current must be limited to 20 mAo For example the maximum number of pins that can be over driven at the maximum current level of
±S mA Is four.
Nate 4: Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors.
Nate 5: Two on·chip diodes are tied 10 each analog Input, which will forward-canduct for analog input voltages one diode drop below ground or one diode drop
greater than Vee supply. Be careful during testing at low Vee levels (4.SV), as high level analog inputs (SV) can cause this input diode to conduct, especially at
elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows SO mV forward bias of either diode. This means that as long as the
analog VIN does not exceed the supply voltage by more than SO mV,the output code will be correct. To achieve an absolute 0 Voc to S Voc Input voltage range will
therefore require a minimum supply voltage of 4.9S0 Voe over temperature variations, initial tolerance and loading.
Nale 6: Typicals are at 2S'C and represent most likely parametric norm.
Nale 7: Guaranteed and 100% production tested under worst case condition.
Nale 8: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Nale 9: Channel leakage current Is measured after the channel selection.
Nate 10: 1 count = VREF/2S6.
Nate 11: Human body model, 100 pF discharged through a 1.5 kn resistor.
Test Circuits
DO Except "TRI-5TATE"
Leakage Current
5Y
5.0Y
~I
.0A
Fil!
I
I
I
I
CHANNEL
SELECT
I
I
I
•
TEST POINT
AUCOSII DO
l'~
CHI (OFF)
Rl
T
Cl
CH2 (OFF)
•
•
••
&.-.:.-
2.2k
MMO 6150
OR EQUIVA~NT
CHO ION)
,,
~,
,
':"
CHID (OFF)
TLlH/5587-17
3-62
~RM:Q~:LENT
TL/H/5587 -6
»
c
oo
Test Circuits (Continued)
tTRI "TRI-STATE"
TEST
POINT
Q)
!
Rl
ADeOB!! DO
.....
.....
5.OV
~
TLlH/5587-22
Typical Performance Characteristics
Unadjusted Offset Error vs
VREF Voltage
j
16
...
15
.it
Ii;
1.5
'~~+,!;;~
14
x
1",12
-lila 10
,;;
~
il
Linearity Error vs VREF
Voltage
...
I
8
6
4
;- 1.0
15 0.75
~
h!i 0.5
z
1.0
0.1
VREF (Voc)
iD 0.4
.......
~
5
0
>-
i...
0.5
Scuc=525 kHz
1/>2=2.1 MHz
VeC='III'F=5V
1
--
.~
4
5
0.2
---
:::; 0.1
h!i
z
:::;
-25
25
75
125
TEMPERATURE ('C)
_ 1.5
:{ 1.4
....
ill 1.3
::l 1.2
'" 1.1
!:i
II: 1.0
iil 0.9
0.8
0.7
J; 0.6
0.5
C 1.5
--...
1
2
3
1/>2 CLK (MHz)
..,
0
..".
/'
1
3
2
I/>z(MHz)
!l
5
Vee =5.25V
1
I'
Vcc =5.0V
1',]
....
.... ........
.... 7' """
VCrr5~ """
0.5
-55
Vec =4.5V
25
65
105
-15
TEMPERATURE ('C)
Resistive Ladder Reference
Current vs Temperature
0.8
vce=~F=5V
1 0.7
...
i...
0.6
~
0.5
It...
0.4
...'"
,4
4
'III'F=VCC_
"",- ~
I,
55iC-
Vcc=VREF=5V
SCLK =525 kHz
T.=25'C
...
iil
25'C
0.1
0
1 1 1
.t.. ~ !V+:2 Clock Frequency
...
~,
5
...
a
r--
..........
Vour -,oV
'SOURC' Vour = 2.4V
.!.
...~
~
h
Power Supply Current
vs Temperature
il 0.3
15
~ 0.2
~c,
.L
Vcc-svoc
ISINKVour=5V
I
2
3
VREF (V)
SClK-525 kHz
Vec ='III'F=5V
iii' 0.4
0.3
lli
z
15
Linearity vs <1>2 Clock
Frequency
15
Ii!
,
1
i'..
20
8
.... 10
0
Linearity vs Temperature
0.5
\
:::; 0.25
0
0.01
25
1/>2=2.1 MH2
kHz
Vcc=5V
To=25'C
_~CLK =525
1.25
il
2
Output Current vs
Temperature
~
0.3
-55
5
z=ov
SClK=oV
~
-15
65
25
TEMPERATURE ('C)
105
TL/H/5587-16
3-63
.,...
.,...
co
o
o
~
Timing Diagrams
DO "TRI-STATE" Rise & Fall Times
DO High to Low State
DO Low to High State
DO
DO 1.2V-TRI-STATE-li,--f------
l
lRDO
i4~v----
---_Oil 0.4V
00
--tt
3.5V
IFOO
0.4V
TUH/5587-14
TL/H/5587-15
IFOO
TLiH/5587 -13
Timing with a continuous SCLK
SeLIC
t:IAec
DO
~
07
X!:3<
DO
TL/H/5587 -11
'Slrobing CS High and Low will abort Ihe presenl conversion and initiale a new serial 110 exchange.
Timing with a gated SCLK and CS Continuously Low
SeLIC
Cl(lOW)
----------.-----+----.---~-
DO _ _ _D_7_ _~e>c
___
_f_-J,~D-7-
&__. .
TLiH/5587-9
Using CS To TRI·STATE DO
TL/H/5587-10
Note: Strobing CS Low during this time interval will abort the conversion in process.
3·64
»
c
Timing Diagrams (Continued)
oo
........
Q)
CS High During Conversion
tCA
Ag~:~T~~N--1-64 "'2 CLOCKS~·'----A~~I~~~D~~E~~~N
I
(MIN)
SCU<
I
5
r
~-,~----------------~
DO
L - -_ _ _ _ _---II
00
TL/H/5587-4
CS Low During Conversion
SCLK
~l~
_______________________ ____________________
~
48
DO
~r
"'2 CLOCKS-I~-TLlH/5587-5
Note: DO and 01 lines share the B·bit 1/0 shift register(see Functional Block Diagram). Since the MUX address bits are shifted in on SCLK rising edges while SCLK
falling edges shift out conversion data on DO, the eighth falling edge of SCLK will shift out the MSB MUX address bit (A7) on DO. Thus, if addressing channels
CHB-CH10, a high DO will occur momentarily (one <1>2 clock period) until the B·bit 110 shift register is cleared by the internal EOC signal.
Channel Addressing Table
TABLE I. ADC 0811 Channel Addressing
MUXADDRESS
ANALOG CHANNEL
SELECTED
A7 A6 As A4 A3 A2 At AO
CHO
0 0 0
0 X X X X
CHI
0 0 0
1 X X X X
0 0
1 0 X X X X
CH2
0 0
1
1 X X X X
CH3
CH4
0 1 0
0 X X X X
CH5
0
1 0
1 X X X X
0
1 1 0 X X X X
CH6
I' 1
0
CH7
1 X X X X
CH8
0 X X X X
1 0 0
1 0 0
1 X X X X
CH9
CH10
1 0 X X X X
1 0
1 0
1
1 X X X X
VTEST
1 1 X X X X X X LOGIC TEST MODE"
• Analog channel inputs CHO thru CH3 are logic outputs
3-65
ADC0811
"11
C
::s
~
0"
::s
e!m
0"
tCOMP
n
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CONVERSION
TIMING GENERATORS
iii"
SAR
SAR
CC
Dl
3
CC
SCll(
'lsl
~I
Co)
i
m
01117]
v.. I
YTYYTYX~
f!!'
00 . . . . . . . . . . . .
(141 VREF
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1
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I
1131AGNO
EOC~
E2JGNO
16100
TL/H/5587 -8
»
c
Functional Description
(")
cCIt)
1.0 DIGITAL INTERFACE
The AOC0811 uses five input/output pins to implement the
serial interface. Taking chip select (CS) low enables the I/O
data lines (DO and 01) and the serial clock input (SCLK). The
result of the last conversion is transmitted by the AID on the
DO line, while simultaneously the 01 line receives the address data that selects the mux channel for the next conversion. The mux address is shifted in on the rising edge of
SCLK and the conversion data is shifted out on the falling
edge. It takes eight SCLK cycles to complete the serial I/O.
A second clock (<1>2) controls the SAR during the conversion
process and must be continuously enabled.
this mux address/sample cycle, data from the last conversion is also clocked out on DO. Since 07 was clocked out
on the falling edge of CS only data bits 06-00 remain to be
received. The following seven falling edges of SCLK shift out
this data on DO.
The 8th SCLK falling edge initiates the beginning of the AID's
actual conversion process which takes between 48 to 64 <1>2
cycles (Tel. During this time CS can go high to TRI-STATE
DO and disable the SCLK input or it can remain low. If CS is
held Iowa new I/O exchange will not start until the conversion sequence has been completed, however once the conversion ends serial I/O will immediately begin. Since there is
an ambiguity in the conversion time (Tel synchronizing the
data exchange is impossible. Therefore CS should go high
before the 48th <1>2 clock has elasped and return low after
the 64th <1>2 to synchronize serial communication.
A conversion or I/O operation can be aborted at any time by
strobing CS. If CS is high or low less than one <1>2 clock it will
be ignored by the AID. If the CS is strobed high or low
between 1 to 3 <1>2 clocks the AID mayor may not respond.
Therefore CS must be strobed high or low greater than 3 <1>2
clocks to ensure recognition. If a conversion or I/O exchange is aborted while in process the consequent data
output will be erroneous until a complete conversion sequence has been implemented.
1.1 CONTINUOUS SCLK
With a continuous SCLK input CS must be used to synchronize the serial data exchange (see Figure 1). The AOC0811
recognizes a valid CS one to three <1>2 clock periods after
the actual falling edge of CS. This is implemented to ensure
noise immunity of the CS signal. Any spikes on CS less than
one <1>2 clock period will be ignored. CS must remain low
during the complete I/O exchange which takes eight SCLK
cycles. Although CS is not immediately acknowledged for
the purpose of starting a new conversion, the falling edge of
CS immediately enables DO to output the MSB (07) of the
previous conversion.
The first SCLK rising edge will be acknowledged after a setup time (tset.up) has elapsed from the falling edge of CS.
This and the following seven SCLK rising edges will shift in
the channel address fortheanalog multiplexer. Since there are
12 channels only four address bits are utilized. The first four
SCLK cycles clock in the mux address, during the next four
SCLK cycles the analog input is selected and sampled. During
SERIAL DATA
INPUT
4 MSB OUTPUT
1.2 DISCONTINUOUS SCLK
Another way to accomplish synchronous serial communication is to tie CS low continuously and disable SCLK after its
8th falling edge (see Figure 2). SCLK must remain low for
ANALOG VOLTAGE
ACQUISITION WINDOW
4 LSB DATA OUTPUT
CONVERSION PROCESS
Sm
DI
TL/H/5567-16
FIGURE 1
CONVERSION PROCESS
SERIAL DATA
INPUT
4 MSB OUTPUT
CS (LOW)
Seu<
ANALOG VOLTAGE
ACQUISITION WINDOW
4 LSB DATA OUTPUT
48TH <1>,
CLOCK
DATA MAY
BE OUTPUT
BETWEEN
48th AND 64th
64TH <1>,
<1>, CLOCKS - - CLOCK
------~--------~---------+------~~---+----------!
DO
TL/H/5567-19
FIGURE 2
3-67
.....
.....
~
~
,------------------------------------------------------------------------------------------,
CIO
Functional Description
~
at least 64 2
CHID
ELEVEN ANALOG
INPUTS
I-
TLIH155B7-21
3-68
»
o
ADC0811 FUNCTIONAL CIRCUIT
n
Q
......co
5V
CHD
CHI
CH2
CH3
CH4
~
SCLK
CH5
CH6
CH7
CHB
CH9
SHIFT/LOAD 1
CHID
QA
12
11
5V
1 12 2 3
INa OA AOI AOl
14
MSB
INA 74LS93 Qo 11
LSB
'::'
CHANNEL SELECT
'::'
5V
'::'
14
5V
ICLK
TL/H/55B7-20
Ordering Information
Temperature Range
Total
Unadjusted
Error
O·Cto 70'C
±Yz LSB
ADCOB11BCN
±1 LSB
ADCOBllCCN
Package Outline
N20A
3-69
-40'C to +85·C
ADCOB11BCJ
ADCOBllBCV
ADCOBllCCJ
ADCOB11CCV
J20A, V20A
-55·C to + 125·C
ADCOBllBJ
ADCOB11CJ
J20A
.....
,...
8
c
_
co
o
ADC0816, ADC0817 8-Bit JLP Compatible AID Converters
with 16-Channel Multiplexer
C
(")
o
.....
CI)
.....
.....
.,..
co
Q
oQ
~
.,..
Electrical Characteristics (Continued)
Digital Levels and DC Specifications: ADC0816CJ--4.5V ";Vcc"; 5.5V, - 55'C,,;TA"; + 125'C unless otherwise noted.
ADC0816CCJ, ADC0816CCN, ADC0817CCN--4.75V,,;Vee ,,; 5.25V, -40'C";TA"; + 85'C unless otherwise noted.
CD
CO
Symbol
o
Q
CONTROL INPUTS (Continued)
c(
IIN(I)
logical "1" Input Current
(The Control Inputs)
VIN=15V
IIN(O)
logical "0" Input Current
(The Control Inputs)
VIN=O
Icc
Supply Current
feLK=640 kHz
Parameter
Conditions
Min
Typ
Max
Units
1.0
p.A
Q
-1.0
p.A
0.3
3.0
rnA
DATA OUTPUTS AND EOC (INTERRUPT)
VOUT(I)
logical "1" Output Voltage
10 - 360 p.A, TA = 85'C
10= -300 p.A, TA=125'C
VOUT(O)
logical "0" Output Voltage
10=1.6mA
0.45
V
Vee- 0.4
V
VOUT(O)
logical "0" Output Voltage EOC
10=1.2mA
0.45
V
lOUT
TRI-STATE Output Current
Vo=Vee
VO=O
3.0
p.A
p.A
-3.0
Electrical Characteristics
Timing Specifications: Vee=VREF(+)=5V, VREF(-)=GND, l,-=t,=20 ns and TA=25'C unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tws
Minimum Start Pulse Width
(Figure 5) (Note 7)
100
200
ns
tWALE
Minimum ALE Pulse Width
(Figure 5)
100
200
ns
ts
Minimum Address Set-Up Time
(Figure 5)
25
50
ns
TH
Minimum Address Hold Time
(Figure 5)
25
50
ns
tD
Analog MUX Delay Time
from ALE
Rs = O!l(Figure 5)
1
2.5
p.S
tHl, tHO
OE Control to Q logic State
CL =50 pF, RL = 10k (Figure 8)
125
250
ns
tlH, tOH
OE Control to Hi-Z
CL = 10 pF, RL = 1Ok (Figure 8)
125
250
ns
te
Conversion Time
fe = 640 kHz, (Figure 5) (Note 8)
fe
Clock Frequency
tEoe
EOC Delay Time
(Figure 5)
CIN
Input Capacitance
At Control Inputs
90
100
116
p's
10
640
1280
kHz
8+2,...s
Clock
Periods
15
pF
0
10
TRI-STATE Output
At TRI-STATE Outputs (Note 8)
15
pF
10
Capacitance
Note 1: Absolute Maximum Ratings indicate limijs beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
COUT
the device beyond its specified operating cond(tions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: A zener diode exists, internally, from Vce to GND and has a typical breakdown voltage of 7 Voc.
Note 4: Two on·chip diodes are tied to each analog input which will forward conduct for analog input Yoltages one diode drop below ground or one diode drop
greater than the Vee supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage
by more than 100 mV, the output code will be correct. To achieve an absolute 0 VOC to 5 VDC input voltage range will therefore require a minimum supply voltage of
4.900 Voc over temperature variations, initial tolerance and loading.
Note 5: Total unadjusted error includes offset, full-scale, and linearity errors. See Figure 3. None of these AIDs requires a zero or full-scale adjust. However, if an
all zero code is desired for an analog input other than o.av, or if a narrow full-scale span exists (for example: O.5V to 4.5V full-scale) the reference voltages can be
13.
adiusted to achieve this. See Figure
Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has
little temperature dependence (Figure 6). See paragraph 4.0.
Note 7: If start pulse is asynchronous with converter clock the minimum start pulse width is 8 clock periods plus 2 ,...S.
Note 8: The outputs of the data register are updated one clock cycle before the rising edge of EOC.
Note 9: Human body model, 100 pF discharged through a 1.5 kfl resistor.
3-72
»
Functional Description
Multiplexer: The device contains a 16-channel single-ended analog signal multiplexer. A particular input channel is
selected by using the address decoder. Table 1 shows the
input states for the address line and the expansion control
line to select any channel. The address is latched into the
decoder on the low-to-high transition of the address latch
enable signal.
TABLE 1
Selected
Analog Channel
INO
IN1
IN2
IN3
IN4
IN5
IN6
IN7
INB
IN9
IN10
IN11
IN12
IN13
IN14
IN15
All Channels OFF
Address Line
0
C
B
A
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
H
H
L
L
H
H
H
H
L
L
H
H
H
X
H
X
H
H
H
H
H
H
H
H
X
H
H
H
H
L
L
L
L
H
H
H
H
X
L
L
L
L
L
L
L
L
Additional single-ended analog signals can be multiplexed
to the AID converter by disabling all the multiplexer inputs
using the expansion control. The additional external signals
are connected to the comparator input and the device
ground. Additional signal conditioning (I.e., prescaling, sampie and hold, instrumentation amplification, etc.) may also
be added between the analog input signal and the comparator input.
Expansion
Control
CONVERTER CHARACTERISTICS
The Converter
The heart of this single chip data acquisition system is its Bbit analog-to-digital converter. The converter is designed to
give fast, accurate, and repeatable conversions over a wide
range of temperatures. The converter is partitioned into 3
major sections: the 256R ladder network, the successive
approximation register, and the comparator. The converter's
digital outputs are positive true.
The 256R ladder network approach (Figure 1) was chosen
over the conventional R/2R ladder because of its inherent
monotonicily, which guarantees no missing digital codes.
Monotonicily is particularly important in closed loop feedback control systems. A non-monotonic relationship can
cause oscillations that will be catastrophic for the system.
Additionally, the 256R network does not cause load variations on the reference voltage.
The bottom resistor and the top resistor of the ladder network in Figure 1 are not the same value as the remainder of
the network. The difference in these resistors causes the
output characteristic to be symmetrical with the zero and
full-scale points of the transfer curve. The first output transition occurs when the analog signal has reached + V. LSB
and succeeding output transitions occur every 1 LSB later
up to full-scale.
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
x = don't care
REF!.)
,.
0--
CONTROLS FROM S.A.R.
I
•i
lY,R
.=-'J-7-·
R
.
.
256R :
R
R
%R
HEFH
·
·
·
·
·
·
·
·
··
=-'J-~
·
·
:':J-
...
~gMPARATOR
INPUT
·
·
·
0--
TL/H/5277 -2
FIGURE 1_ Resistor Ladder and Switch Tree
3-73
c
oo
....
CD
0)
);;
C
oo
CD
....
.....
........
!
g
c:c
.....
....
8c
CD
00
c:c
Functional Description
(Continued)
The successive approximation register (SAR) performs 8 iterations to approximate the input voltage. For any SAR type
converter, n-iterations are required for an n-bit converter.
Figure 2 shows a typical example of a 3-bit converter. In the
ADC0816, ADC0817, the approximation technique i~ extended to 8 bits using the 256R network.
The AID converter's successive approximation register
(SAR) is reset on the positive edge of the start conversion
(SC) pulse. The conversion is begun on the falling edge of
the start conversion pulse. A conversion in process will be
interrupted by receipt of a new start conversion pulse. Continuous conversion may be accomplished by tying the endof-conversion (EOC) output to the SC input. If used in this
mode, an external start conversion pulse should be applied
after power up. End-of·conversion will go low between 0
and 8 clock pulses after the rising edge of start conversion.
The most important section of the AID converter is the
comparator. It is this section which is responsible for the
ulimate accuracy of the entire converter. It is also the comparator drift which has the greatest influence on the repeatability of the device. A chopper-stabilized comparator provides the,most effective method of satisfying all the converter requirements.
The chopper-stabilized comparator converts the DC input
signal into an AC signal. This signal is then fed through a
high gain AC amplifier and has the DC level restored. This
technique limits the drift component of the amplifier since
the drift is a DC component which is not passed by the AC
amplifier. This makes the entire AID converter extremely
insensitive to temperature, long term drift and input offset
errors.
Figure 4 shows a typical error curve for the ADC0816 as
measured using the procedures outlined in AN-179.
INFINITE RESOLUTION
PERFECT CONVERTER
111
110
!-FULL.SCALE
- - ERROR =1/2LSB
111
...
~ 101
g
'"
..=
u
~ 100
~
110
I
_J
101
L
~ 100
-1LSB
ABSOLUTE
ACCURACY
~
011
'" 011
'"
I\-- QUANTIZATION
-1/2 LSB
Cf
'" 010
~ 010
001
\.1.1.-11-8-2-/8-3-/8-4/-8-5/-8-61-8-)-/8- V1N
ERROR
000018"""1-18-218-3-18-418-5-/8-6-18-)/-8- - VIN
VIN AS FRACTION OF FULL·SCALE
VI~
TLfHf5277 -3
AS FRACTION OF FULL·SCALE
TUHf5277-4
FIGURE 2. 3-Bit AID Transfer Curve
FIGURE 3. 3-Bit AID Absolute Accuracy Curve
FIGURE 4. Typical Error Curve
3-74
l>
c
Connection Diagram
(")
g....
Dual-In-Package
~C
•
INl
IN4
(")
o
Order Number
ADC0816CCN,
ADC0817CCN,
ADC0816CCJ or
ADC0816CJ
IN1
INa
IN9
IN10
INll
IN12
INll
IN14
ADDC
ADD D
ALE
10
See NS Package Number
J40AorN40A
2- 1 Msa
2-2
2-l
11
12
EOC
INI'
MULTIPLEXER
OUT
START
VCC
2-4
2-'
2-6
2-1
2-6 LSB
2l
REFI-!
22
CLOCK
21
DUTPUT
ENABLE
COMPARATOR IN
REFI+!
GNO
TDP VIEW
TUH/52n-6
Timing Diagram
CLOCK
r---1
START
.l1li
5l1li
I
t--tws
-+---->
ALE
50%
50%\
~t--twALE
ADDRESS .l1li
- C=
I
STABLE ADDRESS
I
.l1li
I
'5
ANALOG
INPUT
'N
;
STABLE
1\
\~~MULTIPLEXER
OUT
I--
X
X
:
.J
'0--
OUTPUT
/
I
ENABLE
Eoe
~'rOC
....
...,
CD
IN.
IN6
±
I
'-
50~1
'e
OUTPUTS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ..!.R!!'~E_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _{\,_ _ _ _ _ _....}-
TL/H/52n-7
FIGURE 5
3-75
.....
....
gc:c
CIO
Typical Performance Characteristics
1.5 . - - - - , - - - , - - . . . . . - - - - . .
U;
....
o
g
CIO
j
.3
0.5
1--+--I--d-t"..O-.j
z
.'"
~
c:c
~
co
-0.5
c
u
~-.d<+-F--t---t---;
...is
-1
o '--_..J......_--'-_ _"-_....J
-1.5 L-_...J..._ _1-._...J..._~
1.25
2.5
o
3.75
VIN(VI
1.25
2.5
3.75
VIN (VI
TLlH/5277-B
FIGURE 6. Comparator lIN vs VIN
(Vee = VREF= 5V)
FIGURE 7. Multiplexer RON vs VIN
(Vee = VREF= 5V)
TRI-STATE Test Circuits and Timing Diagrams
OUTPUT
ENABLE
Vee
GNU ----""'t-~-----
OUTPUT
ENABLE
-,
VOH ---~L
OUTPUT
-
GNU
-------=
___.."f.-O%--TLlH/5277-9
tOH' tHO
Vee
Vee
Vee
90%
50%
10%
OUTPUT
ENABlE
GNU
OUTPUT
ENABLE
~
10H
Vee
OUTPUT
":"
VOL
10%
TL/H/5277-10
FIGURES
3-76
l>
C
Applications Information
oo
....
01)
OPERATION
1.0 RATIOMETRIC CONVERSION
Ratiometric transducers such as potentiometers, strain
gauges, thermistor bridges, pressure transducers, etc., are
suitable for measuring proportional relationships; however,
many types of measurements must be referred to an absolute standard such as voltage or current. This means a system reference must be used which relates the full-scale
voltage to the standard volt. For example, if Vee = VREF =
5.12V, then the full-scale range is divided into 256 standard
steps. The smallest standard step is 1 LSB which is then 20
mV.
The ADCOB16. ADCOB17 is designed as a complete Data
Acquisition System (DAS) for ratiometric conversion sys·
tems. In ratiometric systems, the physical variable being
measured is expressed as a percentage of full-scale which
is not necessarily related to an absolute standard. The voltage input to the ADCOB16 is expressed by the equation
VIN
Vls-VZ
Dx
DMAX-DMIN
(1)
VIN = Input voltage into the ADCOB16
2.0 RESISTOR LADDER LIMITATIONS
VIs = Full-scale voltage
The voltages from the resistor ladder are compared to the
selected input B times in a conversion. These voltages are
coupled to the comparator via an analog switch tree which
is referenced to the supply. The voltages at the top, center
and bottom of the ladder must be controlled to maintain
proper operation.
Vz = Zero voltage
Dx = Data pOint being measured
DMAX = Maximum data limit
DMIN = Minimum data limit
The top of the ladder, Ref( +), should not be more positive
than the supply, and the bottom of the ladder, Ref( -),
should not be more negative than ground. The center of the
ladder voltage must also be near the center of the supply
because the analog switch tree changes from N-channel
switches to P-channel switches These limitations are automaticaly satisfied in ratiometric systems and can be easily
met in ground referenced systems.
A good example of a ratiometric transducer is a potentiometer used as a position sensor. The position of the wiper is
directly proportional to the output voltage which is a ratio of
the full-scale voltage across it. Since the data is represented as a proportion of full-scale, reference requirements are
greatly reduced, eliminating a large source of error and cost
for many applications. A major advantage of the ADCOB16,
ADCOB17 is that the input voltage range is equal to the supply range so the transducers can be connected directly
across the supply and their outputs connected directly into
the multiplexer inputs, (Figure 9).
Figure 10 shows a ground referenced system with a separate supply and reference. In this system, the supply must
be trimmed to match the reference voltage. For instance, if
a 5.12V reference is used, the supply should be adjusted to
the same voltage within O.W.
Vcc
REF(-)
MSB
1015
OIGITAL
OUTPUT
PROPORTIONAL
TO ANALOG
INPUT
DOUT
100
REFH
GND
':'
LSB
COUT= ~=~
VREF Vcc
4.75V sVCC=VREFs5.25V
* Ratlometrlc transducers
AOC0816,17
FIGURE 9. Ratiometric Conversion System
3-77
TL/H/5277 -11
aI
.......
l>
C
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....
......
01)
.... r------------------------------------------------------------------------------------------,
~
CIO
CI
(.)
C
~....
CIO
CI
(.)
C
c(
Applications Information
(Continued)
The ADC0816 needs less than a milliamp of supply current
so developing the supply from the reference is readily accomplished. In Figure 11 a ground references system is
shown which generates the supply from the reference. The
buffer shown can be an op amp of sufficient drive to supply
the mililiamp of supply current and the desired bus drive, or
if a capacitive bus is driven by the outputs a large capacitor
will supply the transient supply current as seen in Figure 12.
The LM301 is overcompensated to insure stability when
loaded by the 10 /LF output capacitor.
The top and bottom ladder voltages cannot exceed Vee
and ground, respectively, but they can be symmetrically less
than Vee and greater than ground. The center of the ladder
voltage should always be near the center of the supply. The
sensitivity of the converter can be increased, (i.e., size of
the LSB steps decreased) by using a symmetrical reference
system. In Figure 13, a 2.5V reference is symmetrically centered about Vee/2 since the same current flows in identical
resistors. This system with a 2.5V reference allows the LSB
to be half the size of the LSB in a 5V reference system.
1 - - - - - - - - 1 vcc
t - - - - - f REF!+)
DIGITAL
OUTPUT
REFERENCED
TO
GROUND
.
' n15
InO
REFH
VIN
QOUT= VREF
4.7SV ",vee = VREFS5.2SV
TLlH/5277-12
FIGURE 10. Ground Referenced
Conversion System Using Trimmed Supply
>--4~--f
vcc
DIGITAL OUTPUT
REFERENCED TO
GROUND
Y,N
QOUT= VREF
4.7SV sVee=vREFSS.2SV
ADCDSI6,17
TL/H/5277-13
FIGURE 11. Ground Referenced Conversion System with
Reference Generating Vee Supply
3-78
Applications Information
(Continued)
1D-15VDC
Ik
RI
1000 pF
LM329B ~""'---I
RZ
lOT
VCC
>"'-"'~~REF(+)
R3
REFH
TL/H/5277-14
FIGURE 12. Typical Reference and Supply Circuit
5V
r-__...__-.___...
_"",..,.....--t Vce
__..;3:;;.7:.::.5V=-t REF(+)
_~~
~""'---1I--+-----t 10 15
DIGITAL OUTPUT
P~OPORTIONAL TO
ANALOG INPUT
1.25V" VIN:::; 3.75V
1----1100
....._ _....._ _....._ _ _. ._~..-_ _..;I;;;;.Z;;.5V~REFH
2.5V
REFERENCE
RB
RA=Re
* Ratiometrlc transducers
TL/H/5277-15
FIGURE 13. Symmetrically Centered Reference
3.0 CONVERTER EQUATIONS
The output code N for an arbitrary input are the integers
within the range:
The transition between adjacent codes Nand N + 1 is
given by:
VIN= {
(VAEF(+)-VAEF(-»L~6 + 5~2) ±VTUE} +VREF(-)
N=
V'N-VREF(-l x256±Absolute Accuracy
VREF(+)-VREF(-)
where: V)N = Voltage at comparator input
(2)
The center of an output code N is given by:
VIN= {
(VREF(+)-VAEF(-I)[2~6] ±VTUE] +VREF(-l
VREF = Voltage at Ref( + )
VREF = Voltage at Ref( -)
VTUE = Total unadjusted error voltage (typically
(3)
VREF(+) +512)
3-79
(4)
II
~
-o
r---------------------------------------------------------------------------------,
co
Applications Information
C
4.0 ANALOG COMPARATOR INPUTS
.....
CD
The dynamic comparator input current is caused by the periodic switching of on-chip stray capacitances These are connected alternately to the output of the resistor ladderI switch
tree network and to the comparator input as part of the
operation of the chopper stabilized comparator.
Q
OIl(
-CO
Q
oC
OIl(
(Continued)
If no filter capacitors are used at the analog or comparator
inputs and the signal source impedances are low, the comparator input current should not introduce converter errors,
as the transient created by the capacitance discharge will
die out before the comparator output is strobed.
If input filter capacitors are desired for noise reduction and
Signal conditioning they will tend to average out the dynamic
comparator input current. It will then take on the characteristics of a DC bias current whose effect can be predicted
conventionally. See AN-258 for further discussion.
The average value of the comparator input current varies
directly with clock frequency and with VIN as shown in Figure6.
Typical Application
READ----~~}o
________________________
ADDRESS
DECODE
(AD4-ADI5I'
~
I---. .------~ INTERRUPT
MSB
WRITE---"lL.._
LSB
IN
V I6]
0-5V
ANALOG
INPUT RANGE
VINI
TL/H/5277-16
'Address latches needed lor 8085 and SC/MP interlacing the ADC0816, 17 to a microprocessor
Microprocessor Interface Table
PROCESSOR
8080
8085
l-80
SC/MP
6800
READ
WRITE
INTERRUPT (COMMENT)
MEMR
RD
RD
NRDS
VMAec/>2 eR/W
MEMW
WR
WR
NWDS
VMAe02eR/W
INTR (Thru RST Circuit)
INTR (Thru RST Circuit)
INT (Thru RST Circuit, Mode 0)
SA (Thru Sense A)
IRQA or IROB (Thru PIA)
Ordering Information
TEMPERATURE RANGE
Error
- 40"C to
± 'h Bit Unadjusted
ADC0816CCN
± 1 Bit Unadjusted
ADC0817CCN
Package Outline
N40A Molded DIP
3-80
+ 85"C
-55'C to
+ 125"C
ADC0816CCJ
ADC0816CJ
J40A Hermetic DIP
J40A Hermetic DIP
:J>
c
PRELIMINARY n
o
~ Semiconductor
NatiOnal
CI)
.....
Corporation
CD
ADC0819 8-Bit Serial 1/0 AID Converter
with 19-Channel Multiplexer
General Description
The ADC0819 is an 8-Bit successive approximation AID
converter with simultaneous serial 1/0. The serial input controls an analog multiplexer which selects from 19 input
channels or an internal half scale test voltage.
An input sample-and-hold is implemented by a capacitive
reference ladder and sampled data comparator. This allows
the input signal to vary during the conversion cycle.
Separate serial 1/0 and conversion clock inputs are provided to facilitate the interface to various microprocessors.
Features
• Separate asynchronous converter clock and serial data
1/0 clock.
• 19-Channel multiplexer with 5-Bit serial address logic.
• Built-in sample and hold function.
Connection Diagrams
•
•
•
•
•
•
Ratiometric or absolute voltage referencing.
No zero or full-scale adjust required.
Internally addressable test voltage.
OV to 5V input range with single 5V power supply.
TTL/MOS input/output compatible.
28-pin molded chip carrier or 28-pin molded DIP
Key Specifications
•
•
•
•
•
8-Bits
Resolution
Total unadjusted error
Single supply
Low Power
Conversion Time
± 'hLSB and ± 1LSB
5VDC
15mW
16
"'S
Functional Diagram
Molded Chip Carrier (PCC) Package
V"
SClK
26
I.
CH16
~
Vet
CHO
CHI
27
2.
17
16
IS
CHIS
CH2
CH3
I
2
3
4
S 6 7 •
•
.....
II)
UI "
113
:r.
:::c
:z::
:r. ::c
c.>
IUo
to)
(.)
U
14
13
12
128
0"
ADDRESS
lATCH AND
DECODER
CH14
CH13
1+--t---23;.;;.cs
GNO
2.
CHI2
CHII
L':;:'J<"""'1ir-""
Seu<
ID 11
m
ClIO I
CHI 2
CH2 3
xU -0
a
TLlH/9287 -I
Top View
Order Number ADC0819BCV, CCV
See NS Package Number V28A
CH3
~
~:
8
CH. 7
CH1
8
CH8 9
Dual-In-Line Package
CHO
CHI
CH2
CH3
CH.
CHS
I
2
3
4
S
2.
27
26
2S
24
23
22
21
CH6
CH7
CH.
V",
.2CLK
SCLK
01
00
cs
VR£F<+)
vR£F<-)
20
I.
CHll
11
12
I.
17
CH15
CH12
13
16
IS
CH13
GNO
,.
CH10 ~!
CHII 13
ANALOG
INPUT
MUX
. - -_ _ _ _-""22 VII(f+
CHI2 15
CM13 '8
CH14 '7
CHIS I.
CH16 '9
CH17 20
CHI.
CH18
10
CH'
CHIO
CH' 10
CH17
1'4
GNO
CH16
TLlH/9287-2
CHI4
TLlH/9287 -20
Top View
Order Number ADC0819BCN, CCN
See NS Package Number N28B
3-81
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (Vecl
Voltage
Inputs and Outputs
Input Current Per Pin (Note 3)
Lead Temperature (Soldering, 10 sec.)
Dual-In-Line Package (Plastic)
Surface Mount Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
ESD Susceptibility (Note 11)
6.5V
-0.3VtoVee +0.3V
±5mA
Total Package Input Current (Note 3)
±20mA
Storage Temperature
Package Dissipation at TA = 25·C
260·C
215·C
220·C
2000V
Operating Ratings (Notes 1 & 2)
Supply Voltage (Vee)
Temperature Range
- 65·C to + 150·C
875mW
4.5 VDC to 6.0 Voe
TMIN"; TA"; TMAX
-40·C"; TA"; +85·C
O·C,,; TA"; +70·C
ADC0819BCV,ADC0819CCV
ADC0819BCN, ADC0819CCN
Electrical Characteristics
The following specifications apply for Vee = 4.75V to 5.25V, VREF = +4.6V to (Vee + .1V), <1>2 elK = 2.097 MHz unless
otherwise specified. Boldface limits apply from T MIN to T MAX; all other limits TA = TJ = 25·C.
ADC0819BCV, ADC0819BCN
ADC0819CCV, ADC0819CCN
Parameter
Conditions
Typical
(Note 6)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Units
±%
±x,
±1
LSB
LSB
5
kO
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Maximum Total
Unadjusted Error
ADC0819BCV, BCN
ADC0819CCV, CCN
VREF = 5.00 Voe
(Note 4)
±1
Minimum Reference
Input Resistance
8
Maximum Reference
Input Resistance
Maximum Analog Input Range
8
(Note 5)
Minimum Analog Input Range
On Channel Leakage Current
ADC0819BCV,CCV,BCN,CCN
ADC0819BCV,CCV, BCN,CCN
Off Channel Leakage Current
ADC0819BCV,CCV, BCN,CCN
On Channel = 5V
Off Channel = OV
On Channel = OV
Off Channel = 5V
(Note 9)
11
11
kO
Vee + 0.05
GND-0.05
Vee + 0.05
GND-0.05
V
400
1000
nA
-400
-1000
nA
-400
-1000
nA
400
1000
nA
V
ADC0819BCV,CCV, BCN,CCN
On Channel = 5V
Off Channel = OV
On Channel=OV
Off Channel = 5V
(Note 9)
Minimum VTEST
Internal Test Voltage
VREF=Vee,
CH 19 Selected
125
125
(Note 10)
Counts
Maximum VTEST
Internal Test Voltage
VREF = Vee,
CH 19 Selected
130
130
(Note 10)
Counts
2.0
2.0
V
0.8
0.8
V
2.5
2.5
/LA
-2.5
-2.5
/LA
DIGITAL AND DC CHARACTERISTICS
VIN(I), Logical "1" Input
Voltage (Min)
Vee=5.25V
VIN(O). Logical "0" Input
Voltage (Max)
Vee = 4.75V
IIN(I). Logical "1 " Input
Current (Max)
VIN=5.0V
IIN(O). Logical "0" Input
Current (Max)
VIN=OV
0.005
-0.005
3-82
l>
Electrical Characteristics (Continued)
The following specifications apply for Vcc = 4.75V to 5.25V. VREF = +4.6V to (Vcc + .W). <1>2 CLK = 2.097 MHz unless
otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA = TJ = 25'C.
ADC0819BCV, ADC0819BCN
ADC0819CCV, ADC0819CCN
Parameter
Conditions
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Units
2.4
4.5
2.4
4.5
V
V
0.4
0.4
V
-3
3
-3
3
p,A
p,A
-6.5
-6.5
mA
16
8.0
B.O
mA
1
2.5
2.5
mA
0.7
1
1
rnA
Typical
(Note 6)
DIGITAL AND DC CHARACTERISTICS (Continued)
VOUT(1). Logical "1"
Output Voltage (Min)
Vcc=4.75V
IOUT= -360 p,A
IOUT= -10 I-'A
VOUT(O). Logical "0"
Output Voltage (Max)
VCc=5.25V
IOUT=1.6mA
lOUT. TRI-STATE Output
Current (Max)
VOUT=OV
VOUT=5V
-0.01
0.01
ISOURCE. Output Source
Current (Min)
VOUT=OV
-14
ISINK. Output Sink Current (Min)
VOUT=VCC
IcC. Supply Current (Max)
CS=1. VREFOpen
IREF(Max)
VREF=5V
AC CHARACTERISTICS
Parameter
<1>2 CLK. <1>2 Clock Frequency
SCLK. Serial Data Clock
Frequency
Conditions
MIN
0.70
4.0
2.0
2.1
1.0
MAX
1000
525
525
MIN
26
26
32
32
MIN
5.0
-
Not Including MUX
Addressing and
Analog Input
MAX
Sampling Times
-
Falling Edge to DO Data Valid
-
MIN
1
MAX
3
tSET-UP. Minimum Set-up Time of CS Falling
Edge to SCLK Rising Edge
tHCS. CS Hold Time After the Falling
EdgeofScLK
t CS. Total CS Low Time
~
MAX
tHOI. Minimum DI Hold Time from
SCLK Rising Edge
tHOO. Minimum DO Hold Time from SCLK
Falling Edge
Design
Limit
(Note 8)
MAX
-
TC. Conversion Process Time
tACC. Access Time Delay From CS
Tested
Typical
Limit
(Note 6) (Note 7)
0
RL =30k.
CL =100pF
tSOI. Minimum DI Set-up Time to SCLK
Rising Edge
200
Units
MHz
KHz
<1>2 cycles
<1>2 cycles
1
4/cj>2CLK+--2SCLK
sec
0
ns
tset-up + B/SCLK
sec
tcs(min) + 26/cj>2CLK
sec
0
ns
10
ns
400
ns
toOO. Maximum Delay From SCLK
Falling Edge to DO Data Valid
RL =30k.
CL =100 pF
180
200
250
ns
tTRI. Maximum DO Hold Time.
(CS Rising edge to DO TRI-STATE)
RL =3k.
CL =100pF
90
150
150
ns
3-83
c
oo
Q)
......
(Q
a»
..-
8
g
Electrical Characteristics The following specifications apply for Vcc=4.75V to 5.25V, tr=tf= 20 ns, VREF=
4.6V to (Vcc+0.1V), unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA=TJ=25'C.
c(
Parameter
Typical
(NoteS)
Conditions
Tested
Limit
(Note 7)
Design
Limit
(NoteS)
Units
AC CHARACTERISTICS (Continued)
teA, Analog
Sampling Time
After Address Is Latched
CS=Low
tRDO, Maximum DO
RL =30kn,
"TRI-STATE" to "HIGH" State
75
150
150
Rise Time
CL =100pf
"LOW" to "HIGH" State
150
300
300
tFDO, Maximum DO
RL =30 kn,
"TRI-STATE" to "LOW" State
75
150
150
Fall Time
CL=100pf
"HIGH" to "LOW" State
150
300
300
3/SCLK+ 1
CIN, Maximum Input
Analog Inputs, ANO-AN10 and VREF
11
55
Capacitance
All Others
5
15
"'S
sec
ns
ns
pF
Note 1: Absolute Maximum Ratings Indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to ground.
Note 3: Under overvollage conditions (VINVCC) the maximum input current at anyone pin is ±5 mAo If the voltage at more than one pin exceeds
Vec + .3V the total package current must be limited to 20 mA. For example the maximum number of pins that can be over driven at the maximum current level of
± 5 mA is four.
Note 4: Total unadlusted error includes offset, full-scale, linearity, multiplexer, and hold step errors.
Note 5: Two on-chip diodes are tied to each analog input, which will forward-conduct for analog input voltages one diode drop below ground or one diode drop
greater than Vee supply. Be careful during testing at low Vce levels (4.5V), as high level analog inputs (5V) can cause this Input diode to conduct, especially at
elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows SO mV forward bias of either diode. This means that as long as the
analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 Vee to 5 Vee input voltage range will
therefore require a minimum supply voltage of 4.9S0 Vee over temperature variations, initial tolerance and loading.
Note 6: Typicals are at 2S'C and represent most likely parametric norm.
Note 7: Tested Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 8: Design limits are guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 9: Channel leakage current is measured after the channel selection.
Note 10: 1 count
= VREF/256.
Note 11: Human body model; 100 pF discharged through a 1.5 kO resistor.
Test Circuits
DO Except "TRI-STATE"
Leakage Current
5.oV
5V
TEST POINT
ION
~---0-
b-.i.
.,. . --r-0-
OR EQUlVA....
LENT
ADC0819
OOt--+--....-+IIt-...
I ""
-!-,
10FF
~
I
I
I
CH NNEL
SELECT
u
TeL ~ ,~
CHlloFFI
CH210FFI
:
:
•
L-!....
2.2k
MMo 6150
CHo ION)
MM07000
OR EQUIVALENT
-=
TL/H/92B7-4
CH18 (OFF)
TL/H/9287-3
tTRI "TRI-STATE"
Timing Diagrams
TEST
POllNT
AOC0819 DO I-_...._-I\I\RI\L.--C>"
P
DO "TRI-STATE" Rise & Fall Times
5.oV
!
, / 2.4V
DO 1.2V-TRI-STATE-I'41------
';..,!I.4V
-
~tFDD
TLlH/9287-6
TL/H/9287-5
3-84
»
c
oo
Timing Diagrams (Continued)
DO Low to High State
CO
......
DO High to Low State
CD
_~:-IRDD
00 _ _....., O.4V
2.4V
00
TL/H/9287 - 7
TLlH/9287 -8
Data Input and Output Timing
SCLK
01
00
----!n-TLlH/92B7-9
Timing with a continuous SCLK
SCLK
00
- t:IACC
~ 07 :)(2!::!D<_~.oiI
TL/H/9287-10
"'Strobing CS High and Low will abort the present conversion and initiate a new serial 110 exchange.
Timing with a gated SCLI( and CS Continuously Low
SCLK
CS (LOW)
----------.-----+---=~---~-
OO _ _ _
07_ _lE~~
__
07
TL/H/9287-11
Using CS To TRI-STATE DO
SCLK
E(:~:~~-_,jooTRI.STATE-' The
result of the last conversion is transmitted by the AID on the
DO line, while simultaneously the 01 line receives the address data that selects the mux channel for the next conversion. The mux address is shifted in on the rising edge of
SCLK and the conversion data is shifted out on the falling
edge. It takes eight SCLK cycles to complete the serial I/O.
A second clock (21 controls the SAR during the conversion
process and must be continuously enabled.
this mux address/sample cycle, data from the last conversion is also clocked out on DO. Since 07 was clocked out
on the falling edge of es only data bits 06-00 remain to be
received. The following seven falling edges of SCLK shift out
this data on DO.
The 8th SCLK falling edge initiates the beginning of the AID's
actual conversion process which takes between 26 and 32
2 cycles (Tc). During this time es can go high to TRISTATE DO and disable the SCLK input or it can remain low.
" CS is held Iowa new I/O exchange will not start until the
conversion sequence has been completed, however once
the conversion ends serial I/O will immediately begin. Since
there is an ambiguity in the conversion time (Tcl synchronizing the data exchange is impossible. Therefore es should
go high before the 26th 2 clock has elasped and return low
after the 32nd 2 to synchronize serial communication.
1_1 CONTINUOUS SCLK
With a continuous SCLK input es must be used to synchronize the serial data exchange (see Figure 1). The ADe0819
recognizes a valid CS one to three 2 clock periods after
the actual falling edge of es. This is implemented to ensure
noise immunity of the es signal. Any spikes on es less than
one 2 clock period will be ignored. CS must remain low
during the complete I/O exchange which takes eight SCLK
cycles. Although es is not immediately acknowledged for
the purpose of starting a new conversion, the falling edge of
CS immediately enables DO to output the MSB (07) of the
previous conversion.
A conversion or I/O operation can be aborted at any time by
strobing es. "CS is high or low less than one 2 clock it will
be ignored by the AID. " the CS is strobed high or low
between 1 to 3 2 clocks the AID mayor may not respond.
Therefore es must be strobed high or low greater than 3 2
clocks to ensure recognition. If a conversion or I/O exchange is aborted while in process the consequent data
output will be erroneous until a complete conversion sequence has been implemented.
The first SCLK rising edge will be acknowledged after a setup time (tset-up) has elapsed from the falling edge of CS.
This and the following seven SCLK rising edges will shift in
the channel address forthe analog multiplexer. Since there are
19 channels only five address bits are utilized. The first five
SCLK cycles clock in the mux address, during the next three
SCLK cycles the analog input is selected and sampled. During
1.2 DISCONTINUOUS ScLK
Another way to accomplish synchronous serial communication is to tie es low continuously and disable SCLK after its
8th falling edge (see Figure 2). SCLK must remain low for
ANALOG VOLTAGE
ACOUISITION WINDOW
3lS8 DATA OUTPUT
SERIAL DATA
INPUT
5MSBOUTPUT
I
CONVERSION PROCESS
I
Te (MIN) -ITc(MAX)-j
~____-+____~r·~:Jr~
1M
SCLlt
TL1H/92B7-16
FIGURE 1
CONVERSION PROCESS
Te (MAX)
SERIAL DATA
INPUT
5 MSB OUTPUT
CS (LOW)
_
~ZOHC~2
------~--------+-----~----------~~--SCLK
DO
---.......
---07
06
05
D4
D3
02
'--.1 .......1
D7
TL/H/92B7 -17
FIGURE 2
3-88
.--------------------------------------------------------------------,~
Functional Description
(Continued)
at least 32 <1>2 clocks to ensure that the AID has completed
its conversion. If SCLK is enabled sooner, synchronizing to
the data output on DO is not possible since an end of conversion signal from the AID is not available and the actual
conversion time is not known. With CS low during the conversion time (32 <1>2 max) DO will go high or low after the
eighth falling edge of SCLK until the conversion is completed. Once the conversion is through DO will transmit the
MSB. The rest of the data will be shifted out once SCLK is
enabled as discussed previously.
eighth SCLK falling edge. The hold mode is initiated with the
start of the conversion process. An acquisition window of
3tsCLK + 1 JLsec is therefore available to allow the ladder
capacitance to settle to the analog input voltage. Any
change in the analog voltage before or after the acquisition
window will not effect the A/D conversion result.
In the most simple case, the ladder's acquisition time is determined by the Ron (3K) of the multiplexer switches and the
total ladder capacitance (90pf). These values yield an acquisition time of about 2 JLsec for a full scale reading. Therefore the analog input must be stable for at least 2 JLsec
before and 1 JLsec after the eighth SCLK falling edge to
ensure a proper conversion. External input source resistance and capacitance will lengthen the acquisition time and
should be accounted for.
Other conventional sample and hold error speCifications are
included in the error and timing specs of the AID. The hold
step and gain error sample/hold specs are taken into account in the ADC0819's total unadjusted error, while the
hold settling time is included in the AID's max conversion
time of 32 <1>2 clock periods. The hold droop rate can be
thought of as being zero since an unlimited amount of time
can pass between a conversion and the reading of data.
However, once the data is read it is lost and another conversion is started.
If CS goes high during the conversion sequence DO is tristated, and the result is not affected so long as CS remains
high until the end of the conversion.
1.2 MULTIPLEXER ADDRESSING
The five bit mux address is shifted, MSB first, into DI. Input
data corresponds to the channel selected as shown in table
1. Care should be taken not to send an address greater than
or equal to twenty four (11XXX) as this puts the AID in a
digital testing mode. In this mode the analog inputs CHO
thru CH4 become digital outputs, for our use in production
testing.
2.0 ANALOG INPUT
2.1 THE INPUT SAMPLE AND HOLD
The ADC0819's sample/hold capacitor is implemented in its
capacitive ladder structure. After the channel address is received, the ladder is switched to sample the proper analog
input. This sampling mode is maintained for 1 JLsec after the
Typical Applications
ADC0819-INS8048 INTERFACE
PIO t - - -..
~LK
P12
DO
IN88048 Pll
.......
roo--
~~~~}
DI ADC0819
,
•
NINETEEN ANALOG
:
INPUTS
•
CH18t-
~-
TlIH/9287-18
3-89
c
oo
....
CO
Q)
....
co
8C
G)
ADC0819 FUNCTIONAL CIRCUIT
5V
cc
6V
CHO
CHI
CH2
b..
CH3
':"
CH4
CH5
tP2CLK
CH8
CH7
CH8
CH9
28
~
SCLK
CHID
5V
CHll
CH12
CH13
CHI.
74C165
00
CH15
DH
CH18
•
6
14
13
12
D.
11
CH17
CH18
1 12 2 3
5V
INa 0. ROI R02
14
IN. 74LS93 Do 11
TLIHI9287-19
Ordering Information
Temperature Range
Total Unadjusted
Error
crCto +7crC
-4crC to +85°C
I
±'h LSB
ADC0819BCN
ADC0819BCV
I
±1 LSB
ADC0819CCN
ADC0819CCV
N28B
V28A
Package Outline
3-90
r-------------------------------------------------------~~
C
NatiOnal
~ Semiconductor
ADC0820 8-Bit High Speed p.P Compatible
A/D Converter with Track/Hold Function
General Description
Features
By using a half-flash conversion technique, the 8-bit
ADC0820 CMOS AID offers a 1.5 "'S conversion time and
dissipates only 75 mW of power. The half-flash technique
consists of 32 comparators, a most significant 4-bit ADC
and a least significant 4-bit ADC.
The input to the ADC0820 is tracked and held by the input
sampling circuitry eliminating the need for an external sample-and-hold for signals moving at less than 100 mVl",s.
For ease of interface to microprocessors, the ADC0820 has
been designed to appear as a memory location or 1/0 port
without the need for external interfacing logic.
•
•
•
•
•
•
•
•
•
Key Specifications
8 Bits
2.5 "'S Max (RD Mode)
1.5
Max (WR-RD Mode)
• Input signals with slew rate of 100 mVi
converted
without external sample-and-hold to 8 bits
75 mW Max
• Low Power
± Yo LSB and ± 1 LSB
• Total Unadjusted Error
• Resolution
• Conversion Time
--;
\
Corporation
"'S
"'S
•
•
•
•
•
microCMOS
Built-in track-and-hold function
No misSing codes
No external clocking
Single supply-5 VDe
Easy interface to all microprocessors, or operates
stand-alone
Latched TRI-STATE® output
Logic inputs and outputs meet both MOS and T2L voltage level specifications
Operates ratio metrically or with any reference value
equal to or less than Vee
OV to 5V analog input voltage range with single 5V
supply
No zero or full-scale adjust required
Overflow output available for cascading
0.3" standard width 20-pin DIP
20-pin molded chip carrier package
20-pin small outline package
Connection and Functional Diagrams
Dual-In-Line and Small
Outline Packages
Y,N
1
20
DBO
2
19
Vee
NC
OBI
3
18
on:
DB2
4
17
OB7
OB3
5
16
086
WR/ROY
6
15
DB5
UODE
7
14
iiii
8
13
cs
iNi'
9
12
GND
10
11
VREF (+)
VREF (-)
VREF!+)
OF[
OFL
4·BIT
FLASH
ADC
(4 MSBS)
087
086
OB5
0",
VREFt-1
DB4
OUTPUT
LATCH
TL/H/5501-1
4-BIT
AND
0'"
TRI-STATE
BUFFERS
Top View
V*I+)
Molded Chip Carrier
Package
083
4·81T
FLASH
082
AOC
(4lSBs)
081
OBO
VREF(-)
cs
NC
vee
20
Y,N
DBO
OBI
3
12
V,Er(»
11
10
V'Er(-)
GND
1Nf
J!ij
TL/H/5501-2
FIGURE 1
iNi'
TUH/5501-33
3-91
See Ordering Information
oCI
co
N
CI
o
N
CO
o
Absolute Maximum Ratings
CC
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
o
c
(Notes 1 & 2)
Supply Voltage (Vee)
lead Temp. (Soldering, 10 sec.)
Dual-In-line Package (plastic)
Dual-In-line Package (ceramic)
Surface Mount Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
10V
logic Control Inputs
Voltage at Other Inputs and Output
-0.2VtoVee +0.2V
-0.2V to Vee + 0.2V
Storage Temperature Range
675mW
Input Current at Any Pin (Note 5)
1 mA
Package Input Current (Note 5)
4mA
1200V
ESD Susceptability (Note 9)
215'C
220'C
Operating Ratings ,(Notes 1 & 2)
-65'C to + 150'C
Package Dissipation at T A = 25'C
260'C
300'C
Temperature Range
TMINS:TAS:TMAX
-55'CS:TAS: + 125'C
ADC0620BD, ADC0620CJ
ADC0620BCD, ADC0620CCJ
-40'CS:TAS: + 65'C
ADC0620BCN, ADC0620CCN
0'CS:TAS:70'C
ADC0620BCV, ADC0620CCV
0'CS:TAS:70'C
ADC0620BCWM, ADC0620CCWM
0'CS:TAS:70'C
4.5Vt06V
Vee Range
Converter Characteristics The following specifications apply for RD mode (pin 7 = 0), Vee = 5V,
VREF( +) = 5V, and VREF( -) = GND unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits
TA =Tj=25'C.
ADC0820BD, ADC0820CJ
ADC0820BCD, ADC0820CCJ
Parameter
Conditions
Typ
(Note 6)
Resolution
Total Unadjusted Error
(Note 3)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
ADC0820BCN, ADC0820CCN
ADC0820BCV, ADC0820CCV
ADC0820BCWM, ADC0820CCWM
Typ
(Note 6)
8
ADC0620BD, BCD
ADC0620BCN
ADC0620CD, CCD
ADC0620CCN
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
6
8
±1f2
±1f2
±1f2
±1
±1
±1
Limit
Units
Bits
lSB
lSB
LSB
lSB
Minimum Reference
Resistance
2.3
1.00
2.3
1.2
Maximum Reference
Resistance
2.3
6
2.3
5.3
6
kO
kO
Maximum VREF( +)
Input Voltage
Vee
Vee
Vee
V
Minimum VREF( -)
Input Voltage
GND
GND
GND
V
Minimum VREF( +)
Input Voltage
VREF(-)
VREF(-)
VREF(-)
V
Maximum VREF( -)
Input Voltage
VREF(+)
VREF(+)
VREF(+ )
V
Maximum VIN Input
Voltage
Vee + 0.1
Vcc+ 0.1
Vee+ 0•1
V
Minimum VIN Input
Voltage
GND-0.1
GND-O.l
GND-O.l
V
3
-3
0.3
-0.3
3
-3
p,A
p,A
±y..
±y..
lSB
Maximum Analog
Input leakage Current
CS = Vee
VIN = Vee
VIN=GND
Power Supply
Sensitivity
Vee=5V±5%
±1J16
±y..
3-92
±1J1e
l>
C
DC Electrical Characteristics
(")
The following specifications apply for VCc= 5V, unless otherwise specified.
Boldface limits apply from T MIN to T MAX; all other limits T A = TJ = 25°C.
c
co
N
ADC0820BD, ADC0820CJ
ADC0820BCD, ADC0820CCJ
Parameter
Conditions
Tested
Limit
(Note 7)
Typ
(Note 6)
Design
Limit
(Note 8)
ADC0820BCN, ADC0820CCN
ADC0820BCV, ADC0820CCV
ADC0820BCWM, ADC0820CCWM
Typ
(Note 6)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
C
Limit
Units
CS,WR,RD
2.0
2.0
2.0
V
Mode
3.5
3.5
3.5
V
CS,WR,RD
0.8
0.8
0.8
V
Mode
1.5
1.5
1.5
V
0.3
170
1
3
200
p.A
p.A
p.A
-1
p.A
VIN(1), Logical "1"
Input Voltage
Vcc=5.25V
VIN(O), Logical "0"
Input Voltage
Vcc=4.75V
IIN(1), Logical "1"
Input Current
VIN(1)=5V; CS, RD
VIN(1)=5V;WR
VIN(1) = 5V; Mode
IIN(O), Logical "0"
Input Current
VIN(O) = OV; CS, RD, WR,
Mode
0.005
0.1
50
1
3
200
0.005
0.1
50
-0.005
-1
-0.005
VOUT(1), Logical "1" VCC= 4.75V, IOUT= -360 p.A;
Output Voltage
DBO-DB7, OFL, INT
Vcc=4.75V, IOUT= -10 p.A;
DBO-DB7, OFL, INT
2.4
2.8
2.4
V
4.5
4.6
4.5
V
VOUT(O), Logical "0" Vcc=4.75V, IOUT= 1.6 mA;
Output Voltage
DBO-DB7, OFL, INT, RDY
0.4
0.34
0.4
V
3
lOUT, TRI-STATE
Output Current
VOUT=5V; DBO-DB7, RDY
VOUT=OV; DBO-DB7, RDY
0.1
-0.1
-3
0.1
-0.1
0.3
-0.3
-3
p.A
p.A
ISOUACE, Output
Source Current
VOUT= OV; DBO-DB7, OFL
INT
-12
-9
-6
-4.0
-12
-9
-7.2
-5.3
-6
-4.0
mA
mA
ISINK, Output Sink
Current
VOUT=5V; DBO-DB7, OFL,
INT, RDY
14
7
14
8.4
7
mA
Icc, Supply Current
CS=WR=RD=O
7.5
15
7.5
13
15
mA
3
AC Electrical Characteristics The following specifications apply forVcc=5V, t r =tf=20 ns, VAEF(+)=5V,
VAEF( -) = OV and T A = 25°C unless otherwise specified.
Parameter
Conditions
Typ
(Note 6)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Units
tCAO, Conversion Time for RD Mode
Pin 7 = 0, (Figure 2)
1.6
2.5
p.s
tACCQ, Access Time (Delay from
Falling Edge of RD to Output Valid)
Pin 7 = 0, (Figure 2)
tcAO+20
tCAO+50
ns
tCWA.AO, Conversion Time for
WR-RDMode
Pin 7 = VCC; tWA = 600 ns,
tAO= 600 ns; (Figures 3a and 3b)
1.52
p.s
tWA, Write Time
tAD, Read Time
I
I
Min
Pin 7 = Vcc; (Figures 3a and 3b)
Max
(Note 4) See Graph
Min
Pin 7 = VCC; (Figures3a and 3b)
(Note 4) See Graph
tAcC1, Access Time (Delay from
Falling Edge of RD to Output Valid)
tACC2, Access Time (Delay from
Falling Edge of RD to Output Valid)
600
ns
50
p.s
600
ns
Pin 7 = Vcc, tAOtl; (Figure3b)
CL= 15 pF
70
120
ns
CL =100 pF
90
150
ns
3-93
o
N
CIO
o
g
AC Electrical Characteristics
(Continued) The following specifications apply for Vcc= 5V, tr=tf= 20 ns,
VREF( +) = 5V, VREF( -) = OV and T A = 25°C unless otherwise specified.
c(
Parameter
Conditions
Tested
Limit
(Note 7)
Typ
(Note 6)
Design
Limit
(Note 8)
Units
t" Internal Comparison Time
Pin 7=Vee; (Figures 3b and 4)
CL =50pF
800
1300
ns
tl H, toH, TRI-STATE Control
(Delay from Rising Edge of RD to
Hi-ZState)
RL = 1k, CL =10 pF
100
200
ns
trN'i'L, Delay from Rising Edge of
WR to Falling Edge of INT
Pin 7 = Vee, CL = 50pF
tRO>t,; (Figure3b)
tRO V+) the absolute value of current at that pin should be lim~ed
to 1 mA or less. The 4 mA package input current limits the number of pins that can exceed the power supply boundaries with almA current limit to four.
Nole 6: Typicals are at 2S'C and represent most likely parametric norm.
Nole 7: Tested lim~ are guaranteed to National's AOQL (Average Outgoing Quality Level).
Nole 8: Design lim~s are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 9: Human body model, 100 pF discharaged through a I.S kll resistor.
TRI-STATE Test Circuits and Waveforms
t1H
Vee
Rli
I'H' CLm 10 pF
1,1--
vee
DATA
Cl
OUTPUT
GNO
el.L
I
.... ....
lk
DATA VOH
OUTPUTS
GNO
t r =20ns
....
tOM
TUH15501-3
tOH
_
el
":"":"
l!Ii
GND
TLlH15501-4
!,I90%
50%
10%
~
Vee - - - - - - DATA
OUTPUTS
T
":"
90%
vee - -
DATA
OUTPUT
CS
~
=
M
Rli
50%
10%
tOH' CL 10 pF
vee
vee
90%
Rli
t,=20 ns VOL
TLIH15501-5
3-94
10%
TLIH15501-6
Timing Diagrams
\
,., 1
ROY
;·:~::Ij-,..ll_'U_P_____
1-
-t-------r-h----------tACCO-~-tlH.tDH
1, , 0 -1
OBO·OB7- -
- -
-
'------
'
TL/H/5501-7
FIGURE 2. RD Mode (Pin 7 Is Low)
-tiNTl
080-087- -
-
-
--
TLlH/5501-8
FIGURE 3a. WR-RD Mode (Pin 715 High and tRO------ "'-____
080.087 _ _ _ _ _ _ _
-J
TL/H/5501-10
DBO-DB7- - - - - - - - - -
FIGURE 4. WR-RD Mode (Pin 71s High)
Stand-Alone Operation
TL/H/5501-9
FIGURE 3b. WR-RD Mode (Pin 71s High and tRO>t,)
3·95
Typical Performance Characteristics
Logic Input Threshold
Voltage vs Supply Voltage
~
1.7
-55'~"TA" 1125'C
w
~
!:i 1.6
g
'"
S
1.5
"
lil
~ 1.4
>-
~
;;5
/
1.3
./
~
:c
:IE
>-
S
w
;:::
~
~z
..,'"
!:i
.
8::
'"
I
11
I
~
1.2
4.5
4.75
5.0
5.25
Vee-SUPPLY VOLTAGE (V)
Accuracy vs tWR
2.0
~
1.5
\
'"
m 1.0
\
1:
!z
::I
0.5
2.0
i
~
'"'"'"
1.0
z
0.5
i
::I
500
600
700
tWR (n.)
BOO
900
Accuracy vs VREF
[VREF=VREF (+)-VREF (-)1
2.0
\
1.5
VCC I=5V
TA =25'C
\
11.0
1\
i
~
ffi 1.0
1:
!z
0.5
::I
300 400
500 600 700 BOO 900
IRD (n.)
2.0
,---,r---r---,---r--,
1.5
1--11--+--+--+---;
500 600 700
1p (ns)
BOO
900
Output Current vs
Temperature
10 , - - , - - - , - . , - - , - - - ,
w
~
!ii
~
m
T
<=
VREF (V)
!\..
0.5
:IE
~
o
,
1\
Vec=5V
VREF=5V
TA=25·C
IWR=600 ns
tRD=600 ns
::I
tb Internal Time Delay vs
Temperature
-
I
1.5
...'"
co
~
o
300 400
I
"- -r-
1:
o
\
2.0
o
400
~
Vee=5V
VREF=5V
TA=25'C
1p=500 n.
IWR=600 n.
\
1.5
w
'"
o
•~
Accuracy vs tp
Accuracy vs tRD
Vee =5V
VREF=5V
TA=25'C
1p=500 n.
tRD =600 n.
\
5
-100 -50
50
100 150
TA-AMBIENT TEMPERATURE ('C)
1
-100 -50
50
100 150
TA-AMBIENT TEMPERATURE ('C)
5.5
10
'i1:l
z
~
~
9
V
V
./
/
,/
Power Supply Current vs
Temperature (not including
reference ladder)
Conversion Time (RD Mode)
vs Temperature
1
>-
...~
1.0
1:l
0.5
I
6
r--Ir--'!=-.....=-+---j
OL--L_..L----l_--L.--'
oL...-l._-L_.L---I_-I
-100 -50
0
50
100 150
TA-AMBIENT TEMPERATURE ('C)
-100 -50
0
50
100
150
TA-AMBIENT TEMPERATURE ('C)
TlIH/5501-11
'I LSB= VREF
256
3·96
»
c
Description of Pin Functions
Pin Name
1
2
3
4
5
6
VIN
DBO
DB1
DB2
DB3
WR/RDY
7
Mode
8
RD
0
Pin Name
Function
Analog input; range =GNDS:VINS:Vee
TRI-STATE data output-bit 0 (LSB)
TRI-STATE data output-bit 1
TRI-STATE data output-bit 2
TRI-STATE data output-bit 3
WR-RD Mode
WR: With CS low, the conversion is started on the falling edge of WR. Approximately 800 ns (the preset internal time
out, tl) after the WR rising edge, the result
of the conversion will be strobed into the
output latch, provided that RD does not
occur prior to this time out (see Figures
3a and 3b).
RDMode
RDY: This is an open drain output (no internal pull-up device). ROY will go low after the falling edge of CS; ROY will go
TRI-STATE when the result of the conversion is strobed into the output latch. It is
used to simplify the interface to a microprocessor system (see Figure 2).
Mode: Mode selection input-it is internally tied to GND through a 50 ".A current
source.
RD Mode: When mode is low
WR-RD Mode: When mode is high
WR-RDMode
With
low, the TRI-STATE data outputs
(DBO-DB7) will be activated when RD
goes low (see Figure 4). RD can also be
used to increase the speed of the converter by reading data prior to the preset
internal time out (tl, - 800 ns). If this is
done, the data result transferred to output
latch is latched after the falling edge of
the RD (see Figures 3a and 3b).
RDMode
With CS low, the conversion will start with
RD going low, also RD will enable the
TRI-STATE data outputs at the completion of the conversion. ROY going TRISTATE and INT going low indicates the
completion of the conversion (see Figure
Function
WR-RDMode
INT going low indicates that the conversion is completed and the data result is in
the output latch. INT will go low, - 800 ns
(the preset internal time out, tl) after the
rising edge of WR (see Figure 3b); or INT
will go low after the falling edge of RD, if
RD goes low prior to the 800 ns time out
(see Figure 3a). INT is reset by the rising
edge of RD or CS (see Figures 3a and
3b).
RDMode
INT going low indicates that the conversion is completed and the data result is in
the output latch. INT is reset by the rising
edge of RD or CS (see Figure 2).
10 GND
Ground
11 VREF(-) The bottom of resistor ladder, voltage
range: GNDS:VREF(-)S:VREF(+) (Note
5)
12 VREF(+) The top of resistor ladder, voltage range:
VREF(-)S:VREF(+)S:Vee (Note 5)
CS must be low in order for the RD or WR
13 CS
to be recognized by the converter.
TRI-STATE data output-bit 4
14 DB4
TRI-STATE data output-bit 5
15 DB5
16 DB6
TRI-STATE data output-bit 6
TRI-STATE data output-bit 7 (MSB)
17 DB7
Overflow output-If the analog input is
18 OFL
higher than the VREF( +), OFL will be low
at the end of conversion. It can be used to
cascade 2 or more devices to have more
resolution (9, 1O-bit). This output is always
active and does not go into TRI-STATE
as DBO-DB7 do.
19 NC
No connection
Power supply voltage
20 Vee
9
cs
INT
2).
1.0 Functional Description
1.1 GENERAL OPERATION
The ADC0820 uses two 4-bit flash AID converters to make
an S-bit measurement (Figure 1). Each flash ADC is made
up of 15 comparators which compare the unknown input to
a reference ladder to get a 4-bit result. To take a full 8-bit
reading, one flash conversion is done to provide the 4 most
significant data bits (via the MS flash ADC). Driven by the 4
MSBs, an internal DAC recreates an analog approximation
of the input voltage. This analog signal is then subtracted
from the input, and the difference voltage is converted by a
second 4-bit flash ADC (the LS ADC), providing the 4 least
significant bits of the output data word.
The internal DAC is actually a subsection of the MS flash
converter. This is accomplished by using the same resistor
ladder for the AID as well as for generating the DAC signal.
The DAC output is actually the tap on the resistor ladder
which most closely approximates the analog input. In addition, the "sampled-data" comparators used in the ADC0820
provide the ability to compare the magnitudes of several
analog signals simultaneously, without using input summing
amplifiers. This is especially useful in the LS flash ADC,
where the signal to be converted is an analog difference.
3-97
0
CD
I\)
0
o
C'I
~
~
r-------------------------------------------------------------------~
1.0 Functional Description (Continued)
1.2 THE SAMPLED·DATA COMPARATOR
Each comparator in the ADC0820 consists of a CMOS inverter with a capacitively coupled input (Figure 5). Analog
switches connect the two comparator inputs to the input
capacitor (C) and also connect the inverter's input and output. This device in effect now has one differential input pair.
A comparison requires two cycles, one for zeroing the comparator, and another for making the comparison.
In the first cycle, one input switch and the inverter's feedback switch (Figure 58) are closed. In this interval, C is
charged to the connected input (V1) less the inverter's bias
voltage (VB, approximately 1.2V). In the second cycle (Figure 5b), these two switches are opened and the other (V2)
input's switch is closed. The input capacitor now subtracts
its stored voltage from the second input and the difference
is amplified by the inverter's open loop gain. The inverter's
input (VB') becomes
C
VB-(V1-V2)-C+Cs
and the output will go high or low depending on the sign of
VB'-VB·
The actual circuitry used in the ADC0820 is a simple but
important expansion of the basic comparator described
above. By adding a second capacitor and another set of
switches to the input (Figure 6), the scheme can be expanded to make dual differential comparisons. In this circuit, the
feedback switch and one input switch on each capacitor (Z
switches) are closed in the zeroing cycle. A comparison is
then made by connecting the second input on each capacitor and opening all of the other switches (5 switches). The
change in voltage at the inverter's input, as a result of the
change in charge on each input capacitor, will now depend
on both input signal differences.
1.3 ARCHITECTURE
In the ADC0820, one bank of 15 comparators is used in
each 4-bit flash AID converter (Figure 7). The MS (most
significant) flash ADC also has one additional comparator to
detect input overrange. These two sets of comparators operate alternately, with one group in its zeroing cycle while
the other is comparing.
·~L'~.,
~
VI--o--'""'E}C.
·~-r
TV>o+.VD
.-0/,
I~'
.
TL/H/5501-13
TLlH/5501-12
• Vo
'VB'-VB
VB
• V on C = Vl- VB
• Cs = stray input
=
=
(V2-Vl)-Cc+cs
= ~ [CV2-CV1]
c+cs
.vo' is dependent on V2-Vl
.vo'
node capacitor
• Va = inverter input
bias voltage
FIGURE 5b. Compare Phase
FIGURE 5a. Zeroing Phase
FIGURE 5. Sampled-Data Comparator
Z
(VI) --tl)
r
~,-______
Stand·Alone
For stand-alone operation in WR-RD mode, CS and RD can
be tied low and a conversion can be started with WR. Data
will be valid approximately 800 ns following WR's rising
edge.
\'-_...J/
.J}---------
DBD-DB7 - - - - - - - - - - - - - - ( ' -_ _
When in RD mode, the comparator phases are internally
triggered. At the falling edge of RD, the MS flash converter
goes from zero to compare mode and the LS ADC's comparators enter their zero cycle. After 800 ns, data frolT1 the
MS flash is latched and the LS flash ADC enters compare
mode. Following another 800 ns, the lower 4 bits are recovered.
-
-
-
-
-
-
-
WR·RD Mode (Pin 7 is High) Stand·Alone Operation
TL/H/55DI-16
-
1!Jj~'----....../
ROY
''-____r
\I....____----J! \ "------
W
Cf
--c=:>-----
FIGURE A. WR·RD Mode (Pin 7 Is High and tRD ----i REFI + I
IN+
Uk
REFI +1
SV -"'V'IIIr-----i REFI + I
REFI-I
V,. 1 - 1 - - - - + - - 1 REFI-I
LM38S·2.S
REFI-I
c~
• c·
":"
"
TL/H/5501-22
TLIH/5501-21
-:;!;:* Current path must
stili exist from V'NI-)
to ground
TLIH/5501-23
FIGURE 9. Analog Input Options
*
o.r.l
l
vl._.....,.R"'S.,.....+-'\IIROII·~_(,
15LS8
RD.
TO MSB
R·LADDER
1: F T 1 pF
~
COMPARATOR;~
<>-f""l
-o>r"o-J ,.
VIN
. .
~.l _~ ~J..
....r...
12~~T
RD.
V
32 PF-:;r
TlfH/5501-25
pF
•
.·T
1 pF
":"
16 MSB COMPARATORS
TLIH/5501-24
FIGURE 10a
FIGURE 10b
2.3 INPUT FILTERING
Sampled-data comparators, by nature of their input switching, already accomplish this function to a large degree (Section 1.2). Although the conversion time for the ADC0820 is
1.5 "'s, the time through which VIN must be 1/2 LSB stable
is much smaller. Since the MS flash ADC uses VIN as its
"compare" input and the LS ADC uses VIN as its "zero"
input, the ADC0820 only "samples" VIN when WR is low
(Sections 1.3 and 2.2). Even though the two flashes are not
done simultaneously, the analog Signal is measured at one
instant. The value of VIN approximately 100 ns after the
rising edge of WR (100 ns due to internal logic prop delay)
will be the measured value.
Input signals with slew rates typically below 100 mV /
can
be converted without error. However, because of the input
time constants, and charge injection through the opened
comparator input switches, faster signals may cause errors.
Still, the ADC0820's loss in accuracy for a given increase in
signal slope is far less than what would be witnessed in a
conventional successive approximation device. An SAR
type converter with a conversion time as fast as 1 "'S would
still not be able to measure a 5V 1 kHz sine wave without
the aid of an external sample-and-hold. The ADCOB20, with
no such help, can typically measure 5V, 7 kHz waveforms.
It should be made clear that transients in the analog input
signal, caused by charging current flowing into VIN, will not
degrade the AID's performance in most cases. In effect the
ADCOB20 does not "look" at the input when these transients occur. The comparators' outputs are not latched
while WR is low, so at least 600 ns will be provided to
charge the ADC's input capacitance. It is therefore not necessary to filter out these transients by putting an external
cap on the VIN terminal.
2.4 INHERENT SAMPLE-HOLD
Another benefit of the ADC0820's input mechanism is its
ability to measure a variety of high speed signals without the
help of an external sample-and-hold. In a conventional SAR
type converter, regardless of its speed, the input must remain at least V. LSB stable throughout the conversion process if full accuracy is to be maintained. Consequently, for
many high speed signals, this Signal must be externally
sampled, and held stationary during the conversion.
"'S
3-102
l>
c
3.0 Typical Applications
n
o
8-Bit Resolution Configuration
01)
N
o
V",(+I
VREF(-I
12
5V
II
TOol"F
.".
18
iiTI
GNO
10
.".
TLlH/5501-26
9-Bit Resolution Configuration
c;
ts
~~------.---------------------~r;------'~CC~~5V
,,,1-'---------.----,,,
iiii ...
13
WR
,
....
WR
B<
Jc>--! Rii
,,
DB'
,,.• 'DB'B2
B5
15
"
16
BO
BI
~
B2
".i.B3
MODE ff25V
Vm! + }I-"------;~+-...
.L-D5~ I'F
"*
DB'
B7
'B<
'BS
VREFt
1/""-'--;--1--1-..,
$"'"
DB'
17
'B7
BB
1k
un:
18
m:
GND~
' - -_ _---II
'"
*
f+:
Sk
H
1k
c;
'Wl!
13
I
VCC fT-5V
,,,..,...--+-t--'
)o--!- iiii
,,
'BO
'BI
•,
,. DB'
DB'
DB.
15
16
17
18
DB'
DB'
DB'
I!F[
MODE~5V
VREFI + It''---+-t--.
"'-----+.".11._'"",
VAEFt}~
TLlH/5501-27
Multiple Input Channels
Telecom AID Converter
25k
AN
CH'
15V
15Dk
15V
CS
VIN
13
'Ok
40k
VIN
Viii
5V
'0
20 kHz
SAMPLE RATE
Vee
0.01
AN
CH2
WA 6
iiii
ACCOB20
'0 GNO
Rii
iNf
ADCD820
-=5V
iNf9
'~---'-~Vee
12
IJII(+}
DBO 10087
11
CHANNELS
• VIN=3 kHz max ± 4Vp
12 Vmlt}
11 VREF!
• No track-and-hold needed
• Low power consumption
(2-5)
N TDTALINPUT
TL/H/5501-28
DBOloDB7
-~DDEI14-171
,
TL/H/5501-29
3-103
~
~
g
3.0 Typical Applications
(Continued)
a-Bit 2-Quadrant Analog Multiplier
.J1..r
c(
ClK
400 kHz
X,N
(OV TO S~)
Y,N
(-10V TO +10V)
8
lSB
10 GND
13
7
AGND 3
cs
10
lM34D·5.0lAZ
15
16
16
15
'::'
Vee
14
17
18 MSB 13
20
19
15V
IlE
VOUT=
-r
VOUT =Y for
X",Z
22 pF
TL/H/5501-30
Fast Infinite Sample-and-Hold
1.2/ls
Y,N .., r(OV TO 5V) L..I
10 GND
lSB 12
2
cs
11
8l11!
10
13
11
'::'
5V
lM340·5.0lAZ
Vee
20
12
13
~---""-15V
T
O.1/'F
~--""''''''--15V
VREF( -)
AOC0820
15V
'::'
WR
MOOE
VREF( +)
DAC0800
15
16
1---""",,--5V
17
H"""""
1.8k
18 MSB
1.82k
1%
5
> ....--~~~~V
-15V
1.82k
1%
3-104
TL/H/5501-31
(0)
b
~
Digital Waveform Recorder
-tr
INPUT
OV TO 5V
5V
-
ATOD
CONVERTERS
MEMORY
n"
A TO 0 CONTROL lOGIC
et
:I>
DM74LS393
2K X BRAM
l --
*1
'tS
ADDRESS
COUNTERS
'tS
lA
"2-
ClR1~
it
AID
AID
10
n"
ClR2
I\)
ZA
0"
:::J
(I)
m.m.
AD
DBO
--1 YIN
elx
eLKl
AOCB820
I I
AD
5V
1&J1B
A7.
AID
A7
pO
eLR1
ClR2
~
I
DM74LS393
~
a
;;;J
01
Lc.
1Vii.
c:
(D
m.
So
OZ
WII,
03
00,
RO,
DM74LS164 04
0
01
'0
0
fFiD,
iilI,
EIiii,
fix
STORED
DIGITIZED
OUTI'UT
OV TO -5V
-+
5V
'='
":"
5V~
5V ---#tt,y"
•
• 1.3M samples/sec
.4k memory
.".
TRIGGER
TLlH/5501-S2
0(,;80:>OV
II
C) r---------------------------------------------------------------------------~
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cc
Ordering Information
Part Number
ADCOS20BD
ADCOS20BCD
ADCOS20BCV
Total
Unadjusted Error
±%LSB
ADCOS20BCM
ADCOS20BCN
ADCOS20CJ
ADCOS20CCJ
ADCOS20CCV
ADCOS20CCM
ADCOS20CCN
±1 LSB
Package
D20A-Cavity DIP
D20A-Cavity DIP
V20A-Molded Chip
Carrier
M20B-Wide Body Small
Outline
N20A-Molded DIP
J20A-Cerdip
J20A-Cerdip
V20A-Molded Chip
Carrier
MJ20B-Wide Body Small
Outline
N20A-Molded DIP
3-106
Temperature
Range
-55·Cto + 125·C
-40·C to + SO·C
O·Cto +70·C
O·Cto +70·C
O·Cto +700C
-SS·C to + 12S·C
-40·Cto +S5·C
O·Cto +700C
O·Cto +70·C
O·Cto +70·C
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National
Semiconductor
Corporation
_
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t.)
CD
ADC0829 j.tP Compatible 8-Bit AID
with 11-Channel MUX/Digitallnput
General Description
Features
The ADCOB29 is an B-bit successive approximation AID
converter with an ll-channel multiplexer of which six can
be used as digital inputs, as well as, analog inputs.
• Easy interface to all microprocessors or operates
"stand alone"
• Operates ratio metrically or with analog span adjusted
voltage reference
• ll-Channel multiplexer with latched control logic of
which six can be used as digital inputs
• 0 to 5V analog input range with single 5V supply
• TTL/MOS input/output compatible
• No zero or full scale adjusts required
• Standard 2B-pin DIP
• Temperature range -40'C to +B5'C
This AID is designed to operate from the ".p data bus using
a single 5V supply.
Channel selection, conversion control, software configuration and bus interface logic are all contained on this monolithic CMOS device.
This device contains three 16-bit registers which are accessed via double byte instructions. The control register is a
write only register which controls the start of a new conversion, selects the channel to be converted, configures the Bbit 1/0 port as input or output, and provides information for
the B-bit output register.
The conversion results register is a read only register which
contains the current status and most recent conversion results. The discrete input register is also a read only register
which contains the four address bits of the selected channel, and the six discrete inputs which are connected to the
analog multiplexer.
Key Specification
•
•
•
•
•
B Bits
±% LSB and ±1 LSB
256 ".S
5VDC
50mW
Resolution
Total Unadjusted Error
Conversion Time
Single Supply
Low Power
Connection and Block Diagrams
AGNO- 1
'-./
GNO- 2
28 r-V REr (CH1)
OB7- 3
27 r-Vcc
26 r-CHO
OB6- 4
25 r-CH2
MUX
r'"
OB5- 5
24 r-CH3
OB4- 6
23 f-CH4
OB3- 7
22 f-CH5
OB2- 8
21 f-PO(CH10)
OB1- 9
20 r-Pl (CHll)
r----.
a·BIT AID
SUCCESSIVE
APPROXIMATION
EOC
OBO- 10
19 r-P2 (CH8)
R/W-l1
18 r-P3 (CH9)
1/12 CLOCK- 12
17 r-P4(CH6)
RS1- 13
16 f-P5 (CH7)
cs- 14
T
CHO. 11 11
CH2-CH11 ..i.... ~
PO-PS ----
ANALOG
OATA
REGISTER
(READ ONLY)
....
OIGITAL
4
CONTROL
DATA
AO-A3
REGISTER I+~""""--+";';;:"':'::~ REGISTER
(WRITE ONLY)
(REAO ONLY)
a
,.
I
15 f- RESET
8
TL/H/5508-1
Top View
Ordering Information
Error
II
I
± 1/2 Bit Unadjusted
ADCOB29BCN
± 1 Bit Unadjusted
ADCOB29CCN
Package Outline
BUS
CONTROL
LOGIC
~DBO-DB7
+--cs
+--R/W
+--R81
+--RE8ET
+--"'2
....._...
N2BB
3-107
TLiH/5508-2
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Absolute Maximum Ratings
(Notes 1 and 2)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Package Dissipation
at T A = 25'C (Board Mount)
Lead Temp. (Soldering, 10 seconds)
260'C
Supply Voltage, Vee (Note 3)
Voltage
Logic Inputs
Analog Inputs
ESD Susceptability (Note 8)
2000V
6.5V
Input Current Per Pin
Package
-0.3V to Vee + 0.3V
-0.3VtoVee + 0.3V
Storage Temperature
875mW
±5mA
+20 rnA
Operating Conditions (Notes 1 and 2)
- 65'C to + 150'C
Supply Voltage, Vee
4.75 Voe to 5.5 Voe
-40'Cto + 85'C
Temperature Range
Converter and Multiplexer Electrical Characteristics Vee=5Voe=VREF(+), VREF(-)=GND,
SCLK <1>2=1.048 MHz, -40'C"; TA + 85'C unless otherwise noted.
Parameter
Total Unadjusted Error; (Note 3)
ADC0829BCN
ADC0829CCN
Conditions
Typ
(Notes)
Min
VREF Forced to 5.000 Voe
VREF Forced to 5.000 Voe
Reference Input Resistance
1.0
Analog Input Voltage Range
(Note 4) V( + ) or V( -)
VREF( +) Voltage, Top of Ladder
Measured at REF( +)
Units
±%
±1
LSB
LSB
4.5
kll
GND-0.10
VREF(+) + VREF(-)Voltage
2
'
Center of Ladder
Max
Vee+ 0.1O
V
Vee
Vee+ 0.01
V
Veel2- 0.1
Vee/2
Vee/2+ 0.01
V
-0.1
0
VREF( -) Voltage,
Bottom of Ladder
Measured at REF( - )
IOFF, Off Channel
ON Channel = 5V
ADC0829BCN
±400
nA
Leakage Current (Note 6)
OFF Channel = OV
ADC0829CCN
±1
p.A
ION,On Channel
ON Channel = OV
ADC0829BCN
±400
nA
Leakage Current (Note 6)
OFF Channel = 5V
ADC0829CCN
±1
p.A
V
AC Characteristics Vee=VREF(+)=5V, t r =tf=20 ns and TA=25'C (Note 7) unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Units
10.0
p.s
teyC(2). <1>2 Clock Cycle Time (1/1<1>2)
0.943
PWH(2). <1>2 Clock Pulse Width. High
440
ns
PWL<2). <1>2 Clock Pulse Width. Low
410
ns
1r<2 Rise. Time
25
ns
tM2). <1>2 Fall Time
30
ns
335
ns
tAS, Address Set Up Time
RS1.R/W,CS
tOOR, Data Delay (Read)
DBO-DB7
tosw, Data Delay Setup (Write)
DBO-DB7
185
ns
tAH, Address Hold Time
RS1, R/W,CE
20
ns
tOHW, Input Data Hold Time
DBO-DB7
20
ns
tOHR, Output Data Hold Time
DBO-DB7
10
ns
Analog Channel Settling Time
32
Clocks
t e, Conversion Time
256
Clocks
3-108
145
ns
)0
Digital and DC Characteristics
I
Parameter
Bus Control Inputs
(R/W,
c
n
o
Vcc=4.SV to S.SV and -40'C:S:TA:S:8S'C unless otherwise noted.
I
Conditions
I
Min
Typ
I
Max
I
Units
ENABLE RESET, RS1, CS) and Peripheral Inputs (PO·PS)
VIN(1), Logical "1" Input Voltage
V
2.0
VIN(O), Logical "0" Input Voltage
0.8
V
liN, Input Leakage Current
±1
/Jo A
2 CLOCK INPUT
VIN(1), Logical "1" Input Voltage
V
Vce- O•B
VIN(O), Logical "0" Input Voltage
0.4
V
Data Bus (DBO·DB7)
VIN(1), Logical "1" Input Voltage
2.0
V
O.B
V
VOUT=OV
-10
/Jo A
VOUT=SV
10
/Jo A
0.4
V
VIN(O), Logical "0" Input Voltage
lOUT, TRI·STATE® Output Current
VOUT(1), Logical "1" Output Voltage
IOUT=-1.6mA
VOUT(O), Logical "0" Output Voltage
IOUT=1.6mA
V
2.4
Power Supply Requirements
I
Icc, Supply Current
I
I
I
10
I
mA
Note 1: Absolute Maximum Ratings Indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to ground.
Note 3: Total unadjusted error Includes offset. full·scale, linearity, and multiplexer error.
Note 4: For VIN( -);, VIN( +) the digital output code will be 0000 0000. Two on·chip diodes are tied to each analog input, which will forward·conduct for analog input
voltages one diode drop below ground or one diode drop greater than Vee supply. Be careful during testing at low Vee levels (4.SV), as high level analog inputs
(SV) can cause this Input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full·scale. The spec allows 100 mV forward
bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 100 mV, the output code will be correct. To
achieve an absolute a Vee to 5 Vee input voltage range will therefore require a minimum supply voltage of 4.90 Vee over temperature variations, initial tolerance
and loading.
Note 5: Typicals are at 2S'C and represent most likely parametric norm.
Note 6: Off channel leakage current is measured after the channel selection.
Note 7: The temperature coefficient Is 0.3%I'C.
Note 8: Human Body Model, 100 pF discharged through a 1.5 kU resistor.
Timing Diagram
.,
Icyclazl
I:
/.
Ci,
IIIIJIIAz.ov
HSI
0.8V
HtW,
011
Vee- O.BV
Vee- O.BV
0.4V
d 1-1,1
PWHI.21
PWlI.,lj"
1
--l
0.4V
-~I.,I
- + t=I.oH
1.01
2'°fllla
0.8
--1"'--"1
-+
Z.4t
epu
UT
WHITE
epu~
READ
DBO·DBI
Ifu
..F--~
:..:.--)" ...
a.'
3·109
~IDH'
t2.4
0.'
.
TUH/550B-3
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2_0 STATE DESCRIPTIONS
There are three internal states within the AID converter: the
NO OP state; the sample state; and the converting state.
Pin Descriptions
ANALOG AND DIGITAL INPUTS
CHO, CH2-CH5-These are dedicated analog inputs. They
are fed directly to the internal 12 to 1 multiplexer which
feeds the AID converter.
080-087-The bi-directional data lines for the data bus
connect to the poP's main data bus to enable data transfer to
and from the ,.P. DBO-DB7 remain in a high impedance
state unless the ADC0829 is read.
The NO OP state is a stable state since the external stimulus (e.g. start conversion signal) is needed for a state transition.
The first transient state is sampling the input. The first 32
clocks of the conversion are used for acquiring the channel;
this settling time allows any transients to decay before conversion begins. The second transient state is the actual conversion. The conversion is completed in 256 clocks and the
conversion results register is updated. The converter then
returns to the stable NO OP state awaiting further instructions.
The device has no comparator bias current and draws minimal power during the NO OP state.
2 Clock-This signal is used for two purposes. First it synchronizes data transfer in and out of the ADC. Second, it is
the master clock for the AID converter logic and all other
timing signals are derived from it.
R/W-The read/write pin controls the direction of data
transfer on 00-07.
3.0 INITIALIZATION
The device is initialized by an active low on RESET. All outputs are initialized to the inactive state and the converter
placed in its NO OP state. The data register is not affected
by RESET. System TRI-STATE outputs are initialized to the
high impedance state.
PO-P5/CHS-CH II-These 6 pins are dual purpose and may
be used as either TTL compatible digital inputs, or analog
inputs. When used as digital inputs they may be read via the
discrete input register. When they are used as analog inputs
they function like CH-O, CH2-5.
MICROPROCESSOR INTERFACE SIGNALS
RESET-A low on this pin forces the ADC0829 into a
known state. The start bit is cleared, Channel CHO is selected and the internal byte counter is reset to the MS Byte. The
AID data register is not reset. Reset must be held low for at
least 3 clocks.
4_0 CONVERSION CONTROL
The program normally initiates a conversion cycle with a
double write command. (See control word format.) The control word selects a channel, configures the peripheral I/O,
and provides peripheral data information. The conversion is
initiated by setting the SC bit in the control word high.
Cs-Ghip Select must be low in order for data transfer between the ADC0829 and the ,.p to occur.
The converter then resets the start conversion bit and begins the conversion ~ycle.
When the conversion is complete and the new conversion
results transferred to the data register, the status bit is set.
The status bit is not reset when the conversion status is
read. A full double byte write into the control word will reset
the status bit, or a low level at master RESET.
If a new conversion command occurs during a conversion,
the conversion is aborted and a new channel acquisition
phase will immediately begin.
RS1-The Register Select pin is used to address the internal registers.
POWER SUPPLY PINS
Vee-This is the positive 5V supply pin. It powers the digital
load and the sample data comparator. Care should be exercised to ensure that supply noise on this pin is adequately
filtered, by using a bypass capaCitor from Vee to DGND.
DGNo-Digital ground should be connected to the systems
digital ground.
VREF and AGNo-The positive reference pin attaches to
the top of the 256R resistor ladder and sets the full scale
conversion voltage value. The AGND connects to the bottom of the ladder. The conversion result is ratiometric to
VREF - AGND and hence both VREF and AGND should be
noise free. Ideally the VREF and AGND should be single
point connected to the analog transducer's supply. The
VREF and AGND voltages typically are 5V and Ground but
they may be varied so long as (VREF-AGND)/2=
Vee/2 ±0.1V.
5.0 CONTROL STRUCTURE
The control logic continually monitors the control bus waiting for CS to go low and 2 to go high. When this condition
occurs, the internal decoder, which has already selected the
proper function, activitates.
The byte counter will always select the most significant (MS)
half first, and the least significant (LS) half second. Single
byte instructions will always access the MSB portion of any
word. After a single byte instruction the byte counter will
return to the MSB portion of a word when CS is high for a
full clock cycle. A 16-bit read or write is accomplished by
using a 16-bit load or store instruction which transfers each
byte on consecutive clock cycles. This timing is shown in
Figure 1. A Single byte instruction is especially useful for
reading the status bit during a polled interrupt. Figure 2
shows the basic AID conversion timing sequence and flow.
Functional Description
1_0 CONTROL LOGIC
The Control Logic interprets the microprocessor control signals and decodes these signals to perform the actual functions of selecting, reading, writing, enabling the outputs, etc.
3-110
Functional Description (Continued)
Timing for a Typical ,...p 16 Byte Access
TQMSmE
Timing for a Typical ,...p 8 Byte Access
I+-----::;r~-----I
INTERNAL mE
COUIITERIS RESfT
TUH/5508-4
TO MI ME
FIGURE 1
~.
'I'
·I:;·~
. CWCKnJUlfUlflI1JUlJ1JlnJ1I1
W
os
®
®
'/,
lL.-.--..I
lL..----I
RS1flj
~
_
......,
IIIlOF
cmERIIDN
MSUlJI
REG'' ' '
I
I
:m~ ______________WD__m_O_._~_~_IO_U'_CO_N_vm_S_'~______________JXL_____mw__OW__O~
________
Q)S1MT CONVERSION
@SErSCIlTlOA1
@ LOAD ADDRESS
®ANAlDG INPUT InniNG TIME AUOWS INTERNAL MULTIPLEXER TO SWCT A CHANNR AND
STAlIUUI-3ZCLOClS).
@AlDCORVERSIONTIME 1-258 ClOCkS)
IDRtAO END OF COIiVERSION DIll
@ EDC BIT READ IF A1 CONVERSION COMPUTE.
@ AID DATA REGISTER READ. IF EOC = 1, THEN NEW YAUD DATA.
FIGURE 2. AID Conversion Timing Sequence
3·111
TL/H/5508-5
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Functional Description
7.0 ANALOG TO DIGITAL CONVERTER
The ADC0829 AID Converter is composed of three major
sections: the successive approximation register (SAR); the
256R ladder and analog decoder; and the sample-data
comparator.
(Continued)
6.0 WORD FORMAT
c(
6.1 Control Register Word Format
+- MSB Word -+
+- LSB WORD-+
7.1 Successive Approximation
~ DB6 DBs DB4 DBa DB2 ~ Dilo DB7 DB& DBs DB4 DBa DB2 DB, DB
X:
SC:
CH3·CHO:
Hex Value
0
2-5
6-9
A
B
C
D
E
F
The analog signal at the AID input is compared eight times
to various ladder voltages to determine which of the 256
voltages in the ladder most closely approximates the input
voltage. This stochastic technique is accomplished by converging on the proper tap in the ladder by simple iterative
convergence. There are nine posting registers in the SAR
which contain the position of the bit being tested and eight
latching registers which remember if the comparison was
high or low. Starting with the MSB and continuing downward
each bit is set high by the posting register. The analog tree
decoder selects the corresponding tap in the ladder and the
AID input is compared to that voltage. If the comparison is
positive the latch remains set, so higher voltages in the ladder are checked next. If the comparison is negative the bit is
reset so lower ladder voltages are sought.
Don't Care
Start Conversion
1 = Start new conversion
o = Do not start new conversion
Channel Address
Definition
SelectCHO
Select V,ef( + )
Select Channels CH2-CH5
Undefined
CH10
CH11
CH8
CH9
CH6
CH7
After all eight comparisons are made, the contents of the
latching register are transferred to a data register, thus the
AID can perform a new conversion while the previous results remain available.
7.2 256R Ladder
The ladder is a very accurate voltage divider which divides
the reference voltage into 256 equal steps. Special consideration was given to the ladder terminations at each end,
and also the center, to ensure consistent and accurate voltage steps. The use of a 256R ladder guarantees monotonicity since only a single voltage gradient across the ladder
exists. Shorted or unequal resistors in the ladder may cause
non-uniform steps but cannot cause a nonmonotonic response so often fatal in closed loop system applications.
(See Figure 3.)
6.2 Conversion Results Register Word Format
S:
Status
1 = Data is valid
(conversion complete)
o = Data is not valid
8 bit converted result
CONTROLS
FROM S.A.R.
I
VREF(+)
/
\
6.3 Discrete Input Word Format
l'hR
+- MSB Word -+
+- LSB WORD-+
B7 DB6 DBs DB4 DBa DB2 DBI DBa D~ DB& DBs DB4 DBa D~ DBI D
R
R
CH3·CHO:
P5-PO:
Status of channel address
Status of P5-PO interpreted as
discrete digital inputs
..
250 R •
R
ADU ADDRESS SELECTION
R
CSO·
R/W
RSI
Description
1
0
0
0
0
X
X
0
0
1
1
0
1
0
1
Do not respond
Write NOOP
Write Control Word
Read Conversion Results
Read Discrete Inputs
J-:,·
·•
·
TO
COMPARATOR
INPUT
J-~
'hR
VREf(.)
TL/H/5508-6
FIGURE 3. Resistor Ladder and Switch Tree
Note: All words are transferred as two B·bit bytes, MSB transferred first LSB
transferred second.
3-112
]>
the drift signal is a dc component blocked by the ac amplifier.
The comparator has very high input impedance to dc voltages since it looks like a capaCitor. Because the comparator
is chopping the dc voltages at the input, the difference between the AID input voltage and ladder voltage appears on
the comparator's input capacitor. The input voltage difference, chopping frequency, and comparator input capacitor
causes a CVF current. The CVF current is a small bias current which will not produce any error when the AID input is
connected to a low impedance voltage source. If the voltage source has an output impedance of less than 10k, the
error is still insignificant since the bias current exponentially
decays.
Adding a capacitor to the input of the comparator integrates
the exponential charging current converting it into dc bias
current. (See Figure 1.) Two main considerations on the integration capaCitor are charge sharing with a filter capacitor
and settling time.
Functional Description (Continued)
Actually of the 256 resistors in the ladder, 254 have the
same value while the end point resistors are equal to 11/2R and 1/2R. This ensures the system output characteristic is symmetrical with the zero and full scale points of its
input to output, or transfer curve.
The tree decoder routes the 256 voltages from the ladder to
a single pOint at the comparator input. This allows comparisons between the AID input and any voltage the SAR directs the decoder to route to the comparator.
Since the ladder is dependent upon only the matching of
resistors, the voltages it generates are very stable with temperature and have excellent repeatability and long term drift.
B.O MULTIPLEXER
B.1 Analog Inputs
The analog multiplexer selects one of 11 channels and directs them to the input of the AID converter. The multiplexer was designed to minimize the effects of leakage currents
and multiplexer output capacitance.
9.0 BUS INTERFACE
The ADC0829 communicates to the microprocessor
through an 8-bit I/O port. The I/O port is composed of a
TTL to CMOS buffer and a TRI-STATE® output driver.
The TTL to CMOS Buffer translates the TTL voltage levels
into CMOS levels very rapidly and is quite stable with supply
and temperature. The buffer has a small amount of hysteresis (about 100 mY) to improve both noise immunity and internal rise and fall times.
The TRI-STATE bus driver is a bipolar and N-channel pair
that easily drive the bus capacitance. Since the bus drivers
collectively can sink or source a quarter of an amp total, a
non-overlap circuit is used which guarantees that only one
of the two drive transistors is on at a time.
Since this output drives the bus capaCitance, even the nonoverlapping circuit cannot prevent noise on Vee. The
amount of noise depends on the Vee current used to
charge the bus capaCitance.
Special input protection is used to prevent damage from
static voltages or voltages exceeding the specified range
from -0.3V to Vee+0.3V. However, normal precautions
are recommended to avoid such situations whenever
possible.
B.2 Digital Inputs
Six of the analog inputs can also be used as digital inputs to
sense TTL voltage levels. Care must be taken when these
inputs are interpreted since TTL levels may not always be
present.
B.3 AID Comparator
Probably the most important section of the AID converter is
the comparator since the comparator's offset voltage and
stability determine the converter's ultimate accuracy. The
low voltage offset of the chopper-stabilized comparator of
this converter optimizes performance by minimizing temperature dependent input offset errors as well as drift.
The dc signal appearing at the amplifier input is converted
to an ac Signal, amplified by an ac amplifier and restored to
a dc signal. The drift of the comparator is minimized since
Application Information
The extemal filter capacitor on Vee provides some of the
transient current while the bus is being driven. A capacitor
with good ac characteristics and low series resistance is a
good choice to prevent Vee transients from affecting
accuracy.
Recommended Supply
SUPI'L'
lINESTU
OTHEA
IlEYltES
TLIH15508-7
Comparator liN VB VIN
(Vee = VREF= SV, 10= 1.048 MHz)
Multiplexer RON VB VIN
(Vee=VREF=SV)
~
~
2.5
r----r--,--,.--,.--.
2.0
f---1f--+--+--l---l
450
300
5
5 1.0 1--~~~=~~4"'..;;::::j
~-150
~
0.5
S;"'-;;:""-+--+-+-=--J
2.0
3.0
YIN (V)
4.0
V'"
V
l/
-300
-450
1.0
.N
~ 150
1.5 f---1r-A="+:"'k--l---l
5.0
o
1.25
2.50
YIN (V)
TLIH15508-8
3-113
3.75
5.0
TLIH15508-9
C
g
CD
N
CD
~
~
(.)
Data Bus Test Circuit
c V +) the absolute value of current at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four.
Note 5: Human body model, 100 pF discharged through a 1.5 kll resistor.
Note 6: Total unadiusted error includes offset, full-scale, linearity, and multiplexer errors.
Note 7: Cannot be tested for ADCOB32.
Note 8: For VIN(-);"VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are lied to each analog input (see Block Diagram) which will forward
conduct for analog input voltages one diode drop below ground or one diode drop greater then the Vee supply. Be careful, during testing at low Vee levels (4.5V),
as high level analog inputs (5V) can cause this input diode to conduct-especially at elevated temperatures, and cause errors for analog inputs near full·scale. The
spec allows 50 mV forward bias of eHher diode. This means Ihat as long as the analog VIN or VREF does not exceed the supply voltage by more than 50 mY, the
output code will be correct. To achieve an absolute 0 Vec to 5 Vee input voltage range will therefore require a minimum supply voltage of 4.950 Vee over
temperature variations, initial tolerance and loading.
Note 9: Leakage current is measured with the clock not switching.
Note 10: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of
these limits, the minimum, lime the clock is high or the minimum time the clock is low must be at least 1 p.s. The maximum time the clock can be high is 60 p.s. The
clock can be stopped when low so long as the analog input voltage remains stable.
Nole 11: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an addHional delay is built in (see Block Diagram) to
allow for comparator response time.
Note 12: Typicals are at 25'C and represent most likely parametric norm.
Note 13: Tested limits are guaranteed to National's AOOL (Average Outgoing Quality Level).
Note 14: Guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels.
3-118
~
C
g
00
....
....
Typical Performance Characteristics
Co)
Unadjusted Offset Error
vs VREF Voltage
18
Ix
_~
11
.;
1~
~
12 l -
0.50 r-.......~-r-""T'"-'T"""---,
1.5
Y,N(+)=Y,N(-)=OY
YA,.C'2.mv .
TA 2S'C
I-
JCC=5yl- f--
~
i
10
1.0
~ O.S
z
::::; 0.Z5
l-
t;
o
0.1
1.0
VREF (Voc)
~ 0.25 I---i--t--+--F==---i
....~
~
n
Q
VREF=5.0V
felK=25O kHz
c
00
Co)
.....
.110
OL-~_~_.L-~_~
o
oQ
00
z
::::;
'-
~
C
Co)
I'\)
'"
~
(ZSO kHz)
TA=25'C- I -
ffi 0.75
~
0.01
~
iii'1.25
~
o
Unearlty Error vs
Temperature
Linearity Error vs VREF
Voltage
50
-100 -50
2
YREF (V)
100
150
TEMPERATURE ('C)
~
C
o
Q
00
TL/H/5583-2
Output Current vs
Temperature
Linearity Error vs felK
25
3.0
iii' 2.5
VREF=5V
Vcc=5V
1
>-
lZ5'C
~ 2.0
iii
::l 1.0
...
..E 0.5
~
::>
ffi 1.5
I
~
~ 1.0
10 100 ZOO 300 400 500
felK (kHz)
I
15
~
10
.
I
25'C
20
~
::>
I lL
-55'C
::::; 0.5
:!
J
~~~=l~~~~__
ISOURCE Voc=2.4V
islNK VOC = 0.4Y
Ol----L-_-'--'_-'----I
OL-.L-.L-.L-.L-.L-.L-.L......I
-75 -50 -25 0 25 50 75 100 125
600
r--ir-,...-,.---,-...,
-100 -50
0
so 100
TEMPERATURE ('C)
TEMP£RATURE ('C)
Note: For ADC0832 add 'REF.
12S
TL/H/5583-40
Power Supply Current
VSfCLK
1.5
vcc!SV
]:
I
1.0
::::0
<..>
~
::::0
en
~
0.5
--
Leakage Current Test Circuit
o~S"C
5V
ADCOi3X
~
CH A ION CHANNEL)
,.
~
o
a
100
ZOO
300
400
500
CHANNEL
VOLTAGE
tCLdKHz)
SELECT
TLlH/5583-29
.+_________.:
.------1::: ]
to--------.. ---------
OFF
CHANNELS
I
TLlH/5583-3
3-119
Co)
00
~
8
c
TRI-STATE Test Circuits and Waveforms
c(
......
'OS'
C")
co
C)
Co)
c
~
C\I
DDAND :::
C")
co
SARSOUTPUTS
C)
Co)
GND------=
c
~
..-
toH
C")
co
8
c
~~IH
~
tOH
Vee
Vee
c(
GND
DATA
OUTPUT
IDH
DDAND vee
~
SARS DUTPUTS
--
10%
VOL
TL/H/5583-4
TL/H/5583-23
Timing Diagrams
Data Input Timing
Data Output Timing
elK
DATA
DUTIDDI
TUH/5583-24
TL/H/5583-25
ADC0831 Start Conversion Timing
eLK
START CONVERSION
00-----'\1
BIT 7
(MSB)
BIT 6
TL/H/5583-26
3·120
):0
c
oo
Timing Diagrams (Continued)
Q)
(0)
.....
.......
):0
ADC0831 Timing
10
C
oo
11
Q)
(0)
CLOCK (CLK)
N
-II-tm •up
CHIP SELECT (CS)
l~
.......
):0
___________________
C
oo
--I
Q)
(0)
.,.........
):0
C
TRI·STATE
oo
o
(LSB)
TUH/5583-27
'LSB lirst output not available on ADC0831.
ADC0832 Timing
TliH/5583-28
ADC0834 Timing
SAR STATUS
DATA O U T ( D D I - - - - - - - - - I
TliH/5583-5
3-121
Q)
(0)
Q)
ADC08311ADC08321ADC08341ADC0838
::!
3
s·
CO
CI
ADC0838 Timing
cZ
iii
3
o
'§
a
:::>
c:
m
S:
DATA IN
SAR STATUS (SARS)
~
~
lIl!="O"
DATA OUT (00)
---~:::-:=:----....,
-t____
L-_ _ _ _ _
,TR~STATE
TO USINGlIl!{lIl!
CONTROL
LSB FIRST
OUTPUT
00---------.. .
7
(MSB)
MUX
TUH/5583-6
• Make sure clock edge # 18 clocks in the LSB before BE is taken low
11
oz
00
oiD
~~
Gl"
zo
~
en g.
m",
~
»
c
oo
18
0--
en
0
3
CD
0
(X)
-
w
E; ~
Qg ~
(X)
~~ ~
SO"
~.
""
"'
d 9: a
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2: 2-
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Ol
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r
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~
s.0
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~
0
~
...
ce
ANALOG
MUX
(EOUIVALENTI
.1 ~ ~
'"'"
~
ci"
:J
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C
:J
~Ui' ~
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."
STAAT CONV AND ENABLE ISl OUTPUT BUFFER
16
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3
en
m
r-
m
~
.r
[
CH
S-
CO
o
cs
I
CH
.7
.6
"
.,
.,
VR
TO INTERNAL
CIRCUITRY
Q'
5'
(l)
»
g
ex>
'"
.-
'::'
~
13 INPUT
g
o GND
S
0.
@"
~
.2
.,
19
V·
.N
~.
.3
7V ZENER
lD
J,
16
17
18
'::'
11
-
TO
INTERNAL
CIRCUITS
~
•
•
g·8fT
SHIFT
REGISTER
.D
INPUT PROTECTION - All lOGIC INPUTS
A GND
S5'
(l)
'::'
g
TL/H/5583-7
s-
l
9.
8&8000V /P&8000V /(;&80:::>OV / ~ &80:::>OV
IrI
CD
Cf)
CD
0
(,)
Q
<
.....
...
Connection Diagrams
ADC0838 8-Channel MUX
ADC0834 4-Channel MUX
Dual-In-Llne Package
Dual-In-Llne Package
Cf)
CD
0
(,)
CHO
Vee
Q
CHI
v+
Cs
y+
1
14
Vee
2
13
01
3
12
ClK
Cs
CHO
CD
CH3
01
CHI
11
SARS
0
(,)
CH4
ClK
CH2
10
DO
Q
CH5
~
N
Cf)
~
....
Cf)
CD
8Q
<
CH2
CH6
7
15
SARS
14
DO
CH7
S
13
SE
COM
9
12
OGNO
10
11
YREF
AGNO
CH3
9
DGND
S
YREF
AGND
TLlH/5583-30
Top View
COM Internally connected to A GND
TL/H/S583-8
Top View
ADC0831 Single Differential Input
ADC0832 2-Channel MUX
Dual-In-Une Package
CsOs
Dual-In-Llne Package
Vee(VREF)
CHO
2
7
CHI
3
6
DO
ClK
GND
4
5
01
TL/H/5583-32
TL/H/5583-31
Top View
Top View
COM internally connected to GND.
VREF internally connected to Vee.
ADC0838 8-Channel MUX
Molded Chip Carrier (PCC) Package
y+
SE
Vee
CHO
11
YREF
AGND
CHI
10
OGND
COM
CH2
TL/H/5583-33
3-124
Functional Description
1.0 MULTIPLEXER ADDRESSING
The design of these converters utilizes a sample-data comparator structure which provides for a differential analog input to be converted by a successive approximation routine.
The actual voltage converted is always the difference between an assigned" +" input terminal and a "-" input terminal. The polarity of each input terminal of the pair being
converted indicates which line the converter expects to be
the most positive. If the assigned" +" input is less than the
"-" input the converter responds with an all zeros output
code.
A unique input multiplexing scheme has been utilized to provide multiple analog channels with software-configurable
single-ended, differential, or a new pseudo-differential option which will convert the difference between the voltage at
any analog input and a common terminal. The analog signal
conditioning required in transducer-based data acquisition
systems is significantly simplified with this type of input flexibility. One converter package can now handle ground referenced inputs and true differential inputs as well as signals
with some arbitrary reference voltage.
A particular Input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single-ended or dlfferen-
tial. In the differential case, it also assigns the polarity of the
channels. Differential inputs are restricted to adjacent channel pairs. For example channel 0 and channel 1 may be
selected as a different pair but channel 0 or 1 cannot act
differentially with any other channel. In addition to selecting
differential mode the sign may also be selected. Channel 0
may be selected as the positive input and channel 1 as the
negative input or vice versa. This programmability is best
illustrated by the MUX addressing codes shown in the following tables for the various product options.
The MUX address is shifted into the converter via the DI
line. Because the ADC0831 contains only one differential
input channel with a fixed polarity assignment, it does not
require addressing.
The common input line on the ADC0838 can be used as a
pseudo-differential input. In this mode, the voltage on this
pin is treated as the .. -" input for any of the other input
channels. This voltage does not have to be analog ground;
it can be any reference potential which is common to all of
the inputs. This feature is most useful in single-supply application where the analog circuitry may be biased up to a
potential other than ground and the output signals are all
referred to this potential.
TABLE I. Multiplexer/Package Options
Part
Number
Single-Ended
Differential
Package Pins
ADC0831
1
1
8
ADC0832
2
1
8
ADC0834
4
2
14
ADC0838
8
4
20
Number of Analog Channels
3-125
Number of
co
~
B
r---------------------------------------------------------------------------------,
Functional Description
(Continued)
TABLE II. MUX Addressing: AOC0838
~
.......
Single-Ended MUX Mode
Analog Single-Ended Channel #
MUXAddress
"1:1'
CO)
co
SGLI
OIF
0001
~
C'I
1
0
0
0
1
0
0
1
8
1
0
1
0
1
0
1
1
~
....
1
1
0
1
1
0
0
1
co
1
1
1
0
1
1
1
1
CI
(.)
Q
SELECT
SIGN
CO)
Q
CO)
CI
oQ
1
0
0
1
2
4
3
5
6
COM
7
-
+
-
+
+
-
+
-
+
+
-
+
+
c(
Differential MUX Mode
MUXAddress
Analog Differential Channel-Pair #
SGLI
OIF
0001
SIGN
1
0
0
1
0
0
0
0
+
-
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
SELECT
0
-
2
1
2
3
+
-
-
0001
SIGN
+
-
6
7
+
-
-
+
+
-
+
TABLE IV. MUX Addressing:
AOC0832
Channel #
MUXAddress
5
+
TABLE III. MUX Addressing: AOC0834
Single-Ended MUX Mode
SGLI
OIF
3
4
Single-Ended MUX Mode
SELECT
1
1
0
0
1
0
1
1
1
0
1
1
1
0
1
2
3
+
+
+
MUXAddress
SGLI
OIF
0001
1
0
1
1
+
SIGN
Channel #
0
1
+
+
COM is internally tied to A GND
COM is Internally tied to A GND
Differential MUX Mode
Differential MUX Mode
MUXAddress
Channel #
MUXAddress
SGLI
OIF
0001
SELECT
SIGN
1
0
1
0
0
0
+
-
0
0
0
1
1
0
0
1
1
-
2
3
+
-
-
+
+
3-126
Channel #
SGLI
OIF
0001
0
1
0
0
+
-
0
1
-
+
SIGN
l:o
Functional Description
C
(Continued)
Since the input configuration is under software control, it
can be modified, as required, at each conversion. A channel
can be treated as a single-ended, ground referenced input
for one conversion; then it can be reconfigured as part of a
differential channel for another conversion. Figure 1 illustrates the input flexibility which can be achieved.
To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate diagram is shown of each device.
1. A conversion is initiated by first pulling the CS (chip select) line low. This line must be held low for the entire conversion. The converter is now waiting for a start bit and its
MUX assignment word.
2. A clock is then generated by the processor (if not provided continuously) and output to the AID clock input.
3. On each rising edge of the clock the status of the data in
(DI) line is clocked into the MUX address shift register. The
start bit is the first logic "1" that appears on this line (all
leading zeros are ignored). Following the start bit the converter expects the next 2 to 4 bits to be the MUX assignment word.
The analog input voltages for each channel can range from
50 mV below ground to 50 mV above Vee (typically 5V)
without degrading conversion accuracy.
2.0 THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system improvements; it allows more function to be included in the
converter package with no increase in package size and it
can eliminate the transmission of low level analog signals by
locating the converter right at the analog sensor; transmitting highly noise immune digital data back to the host processor.
8 Single-Ended
8 Pseudo-Differential
+
+
+
+
+
+
+
+
COM I-I
+
COM I-I
V'IAS-=-
~
Mixed Mode
4 Differential
.'j
+1-1
0.1
+
2,3
+
2,3
+
+
4,5
+1-1
+
-1+1
+
6,7
+
COM I-I
VSIAS-=-
*
FIGURE 1. Analog Input Multiplexer Options for the ADC0838
3-127
TL/H/5583-9
oQ
co
(,)
.....
......
l:o
c
o
Q
co
(,)
N
i>
c
9co
(,)
-'="
......
l:o
c
oQ
co
co
(,)
~ r-------------------------------------------------------------~
C")
~
o
oQ
~
'<:I'
C")
~
o
oQ
c(
C\i
C")
~
o
oQ
c(
.....
....
C")
~
o
oQ
c(
Functional Description
(Continued)
4. When the start bit has been shifted into the start location
of the MUX register, the input channel has been assigned
and a conversion is about to begin. An interval of % clock
period (where nothing happens) is automatically inserted to
allow the selected MUX channel to settle. The SAR status
line goes high at this time to signal that a conversion is now
in progress and the 01 line is disabled (it no longer accepts
data).
The 01 and DO lines can be tied together and controlled
through a bidirectional processor I/O bit with one wire. This
is possible because the 01 input is only "looked-at" during
the MUX addressing interval while the DO line is still in a
high impedance state.
3.0 REFERENCE CONSIDERATIONS
The voltage applied to the reference input to these converters defines the voltage span of the analog input (the difference between VIN(MAX) and VIN(MIN» over which the 256
possible output codes apply. The devices can be used in
either ratiometric applications or in systems requiring absolute accuracy. The reference pin must be connected to a
voltage source capable of driving the reference input resistance of typically 3.5 kn. This pin is the top of a resistor
divider string used for the successive approximation conversion.
5. The data out (DO) line now comes out of TRI-STATE and
provides a leading zero for this one clock period of MUX
settling time.
6. When the conversion begins, the output of the SAR comparator, which indicates whether the analog input is greater
than (high) or less than (low) each successive voltage from
the internal resistor ladder, appears at the DO line on each
falling edge of the clock. This data is the result of the conversion being shifted out (with the MSB coming first) and
can be read by the processor immediately.
In a ratiometric system, the analog input voltage is proportional to the voltage used for the AID reference. This voltage is typically the system power supply, so the VREF pin
can be tied to Vee (done internally on the ADC0832). This
technique relaxes the stability requirements of the system
reference as the analog input and AID reference move together maintaining the same output code for a given input
condition.
7. After 8 clock periods the conversion is completed. The
SAR status line returns low to indicate this % clock cycle
later.
8. If the programmer prefers, the data can be provided in an
LSB first format [this makes use of the shift enable (SE)
control line]. All 8 bits of the result are stored in an output
shift register. On devices which do not include the SE control line, the data, LSB first, is automatically shifted out the
DO line, after the MSB first data stream. The DO line then
goes low and stays low until CS is returned high. On the
ADC0838 the SE line is brought out and if held high, the
value of the LSB remains valid on the DO line. When SE is
forced low, the data is then clocked out LSB first. The
ADC0831 is an exception in that its data is only output in
MSB first format.
For absolute accuracy, where the analog input varies between very specific voltage limits, the reference pin can be
biased with a time and temperature stable voltage source.
The LM385 and LM336 reference diodes are good low current devices to use with these converters.
The maximum value of the reference is limited to the Vee
supply voltage. The minimum value, however, can be quite
small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing less than a
5V output span. Particular care must be taken with regard to
noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 LSB equals VREFI
256).
9. All internal registers are cleared when the CS line is high.
If another conversion is desired, CS must make a high to
low transition followed by address information.
r-------1Tr--~
5V
r--------------~-------1~5V
Vee
Vee
20k
TRANSDUCER
~+--
+
ADC0834
I-_O:..;V...;-1~.2~5V;""-l +
VREF
ADC0832
r--
VREF ~ 1.25V
~ ~LM385
GND
GND
TL/H/5583-10
a) Ratiometric
b) Absolute with a Reduced Span
FIGURE 2. Reference Examples
3-128
Functional Description
»
c
oo
(Continued)
4.0 THE ANALOG INPUTS
The most important feature of these converters is that they
can be located right at the analog signal source and through
just a few wires can communicate with a controlling processor with a highly noise immune serial bit stream. This in itself
greatly minimizes circuitry to maintain analog signal accuracy which otherwise is most susceptible to noise pickup.
However, a few words are in order with regard to the analog
inputs should the input be noisy to begin with or possibly
riding on a large common-mode voltage.
5.2 Full-Scale
The full-scale adjustment can be made by applying a differential input voltage which is 1 % LSB down from the desired
analog full-scale voltage range and then adjusting the magnitude of the VREF input (or Vec for the ADC0832) for a
digital output code which is just changing from 1111 1110 to
1111 1111.
5.3 Adjusting for an Arbitrary Analog Input Voltage
Range
If the analog zero voltage of the AID is shifted away from
ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference
should be properly adjusted first. A VIN (+) voltage which
equals this desired zero reference plus % LSB (where the
LSB is calculated for the desired analog span, using
1 LSB = analog span/256) is applied to selected" +" input
and the zero reference voltage at the corresponding "-"
input should then be adjusted to just obtain the OOHEX to
01 HEX code transition.
The full-scale adjustment should be made [with the proper
VIN( -) voltage applied] by forcing a voltage to the VIN( +)
input which is given by:
The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
to both selected" +" and" -" inputs for a conversion (60
Hz is most typical). The time interval between sampling the
" +" input and then the "-" input is % of a clock period.
The change in the common-mode voltage during this short
time interval can cause conversion errors. For a sinusoidal
common-mode signal this error is:
0.5 )
Verror(max)= VPEAK(27rfCM) ( - fCLK
where fCM is the frequency of the common-mode signal,
VPEAK is its peak voltage value
and fCLK' is the AID clock frequency.
For a 60 Hz common-mode signal to generate a % LSB
error U" 5 mV) with the converter running at 250 kHz, its
peak value would have to be 6.63V which would be larger
than allowed as it exceeds the maximum analog input limits.
Due to the sampling nature of the analog inputs short spikes
of current enter the" +" input and exit the" -" input at the
clock edges during the actual conversion. These currents
decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period. Bypass capacitors at the inputs will average these currents and cause
an effective DC current to flow through the output resistance of the analog signal source. Bypass capacitors should
not be used if the source resistance is greater than 1 kO.
This source resistance limitation is important with regard to
the DC leakage currents of input multiplexer as well. The
worst-case leakage current of ± 1 /LA over temperature will
create a 1 mV input error with a 1 kO source resistance. An
op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance
Signal source be required.
V
IN
(+)fsad· = V
-1.5 [(VMAX-VMIN)]
J
MAX
256
where:
VMAX = the high end of the analog input range
and
VMIN = the low end (the offset zero) of the analog
range.
(Both are ground referenced.)
The VREF (or Vccl voltage is then adjusted to provide a
code change from FEHEX to FFHEX. This completes the adjustment procedure.
6.0 POWER SUPPLY
A unique feature of the ADC0838 and ADC0834 is the inclusion of a zener diode connected from the V+ terminal to
ground which also connects to the Vec terminal (which is
the actual converter supply) through a silicon diode, as
shown in Figure 3. (See Note 3)
R
Ys
5.0 OPTIONAL ADJUSTMENTS
Y+
......
5.1 Zero Error
The zero of the AID does not require adjustment. If the
minimum analog input voltage value, VIN(MIN), is not ground
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biasing any VIN (-) input at this VIN(MIN) value. This
utilizes the differential mode operation of the AID.
The zero error of the AID converter relates to the location
of the first riser of the transfer function and can be measured by grounding the VIN( -) input and applying a small
magnitude positive voltage to the VIN( +) input. Zero error is
the difference between the actual DC input voltage which is
necessary to just cause an output digital code transition
from 0000 0000 to 0000 0001 and the ideal % LSB value
(% LSB=9.8 mV for VREF=5.000 VDcl.
Vee
ACTUAL
CDNVERTER
SUPPLY
~~7Y
GND
TL/H/5583-11
FIGURE 3. An On-Chip Shunt Regulator Diode
3-129
-
··
··
·
cs+-
CHo
CLK
+-
>-
GO
··
•
··
SK
AoCo838
COP42O
DI+-
SO
•
>-
CH7
DO
--+
csi+-
CHo
>-
CD
Co)
I\)
......
CLK
I+-
CH7
~
P12
AoCo838
c
(')
INS8048
DI
I+-
Ph
DO
f-+
PIg
•
SI
o
PI3
o
CD
Co)
~
......
~
c(')
o
CD
Co)
TLlH/5583-13
COP CODING EXAMPLE
Mnemonic
LEI
SC
OGI
CLRA
AISC1
XAS
LDD
NOP
XAS
8048 CODING EXAMPLE
Instruction
ENABLES SIO's INPUT AND OUTPUT
C=1
GO=O(CS=O)
CLEARS ACCUMULATOR
LOADS ACCUMULATOR WITH 1
EXCHANGES SIO WITH ACCUMULATOR
AND STARTS SK CLOCK
LOADS MUX ADDRESS FROM RAM
INTO ACCUMULATOR
Mnemonic
P1, #OF7H
ANL
MOV B, #5
MOV A, #ADDR
LOOP 1: RRC A
ONE
JC
START:
ZERO:
ORl
CALL
DJNZ
CALL
MOV
LOOP 2: CALL
IN
RRC
RRC
MOV
RLC
MOV
DJNZ
RETR
t
8 INSTRUCTIONS
.J,
XIS
CLRA
RC
XAS
XIS
OGI
LEI
ANL
JMP
ONE:
CONT:
LOADS MUX ADDRESS FROM
ACCUMULATOR TO SIO REGISTER
XAS
CD
READS HIGH ORDER NIBBLE (4 BITS)
INTO ACCUMULATOR
PUTS HIGH ORDER NIBBLE INTO RAM
CLEARS ACCUMULATOR
C=O
READS LOW ORDER NIBBLE INTO
ACCUMULATOR AND STOPS SK
PUTS LOW ORDER NIBBLE INTO RAM
GO=1 (CS=1)
DISABLES SIO's iNPUT AND OUTPUT
Instruction
;SELECT AID (CS= 0)
;BIT COUNTER ~ 5
;A ~ MUX ADDRESS
;CY ~ ADDRESS BIT
;TESTBIT
;BIT=O
P1, #OFEH ;DI~O
;CONTINUE
CONT
;BIT=1
P1, #1
;DI~1
;PULSE SK 0 ~ 1 ~ 0
PULSE
B, LOOP 1 ;CONTINUE UNTIL DONE
;EXTRA CLOCK FOR SYNC
PULSE
;BIT COUNTER ~ 8
B,#8
;PULSESKO~ 1 ~ 0
PULSE
;CY~DO
A,P1
A
A
;A~RESULT
A,C
;A(O) ~ BIT AND SHIFT
A
;C~RESULT
C,A
B,LOOP2 ;CONTINUE UNTIL DONE
;PULSE SUBROUTINE
PULSE:
3-131
ORl
NOP
ANL
RET
P1, #04
;SK~1
;DELAY
P1, #OFBH
;SK~O
II
Applications (Continued)
A "Stand-Alone" Hook-Up for ADC0838 Evaluation
MUX ADDRESS
fiVDC
_START liT
mi.)
saL/DIF
J J "J J
13
"
3
PARALLEL INPUTS
NO
INPUT SttlFT REGISTER
74Clili
Vee
DO
II
'0
lVoc
IVoe
OUTPUT SHIFT REGISTER
74C114
DO
11
"
,0
L
••-.---4~--~----·DO-T-'D-'~-L~.~y--~~--~----~L7...~IiVDt
'Pinouts shown for ADC0838.
For all other products tie to
pin functions as shown.
Low-Cost Remote Temperature Sensor
LM331
O"v'V..----o-.....-------j V,.I_'
Vee 1-.....-:,.-"
T'='
tDPF
ADCDl3'
11k
V... I-----+·~lt.·oX
TL/H/55B3-14
3-132
r--------------------------------------------------------------------.~
o
g
co
....
Applications (Continued)
Co)
Digitizing a Current Flow
v
0.1
);
----....:;;..::.::::..--;:;;.;=:..:.::=---------...,
_
I&Vo~~ o-"'""-Wlf-....
'LOAD
IZA FULL.seALEI
o
oo
100
CO
Co)
V e e t - - - - -..........- - - - - - ,
N
.....
~
o
oo
Zk
Z401
AoeOS31
CO
a.lk
Co)
~
.....
~
100
ZERO ~"I------f V'NI+I
AOJ
VREF
o
oo
LM33&
1-....- -..<
CO
Co)
CO
.-
IZOI
TLIHI55B3-15
Operating with Ratlometric Transducers
Vee
15Voel
ZOI
,,"V..;X;:O::,R+----iV,NI+1
Vee
11
ZERO
AOJ
ADCOII31
10k
-c.
VREF I-::'~....
0.1 vee +
r
'"F
lk
.......,r--_. . ~~J
':" Z4k
TLIHI55B3-37
'V'N(-) ~ 0.15 Vee
15% of Vee ,;: VXDR ,;: 85% of Vee
3·133
co
CO)
co
8
c
Applications (Continued)
--IVIN(+)
12k
----,I
AUC0831
r-":'=~-'
I
I
I
SETS ZERO
COOE VOLTAGE
2.7k
LM336
330
I
I
_J
lk
ZVOC
ZERO AO!
TL/H/55B3-16
3·134
»
Applications
c
oQ
(Continued)
co
Co)
....
Obtaining Higher Resolution
.......
»
c
~c-1~---f-----------1~---------------'
Vee
V,N
+
-
'-
-
+
:}
:}
:}
:}
R
>2.5V ,;;2.5V
V'EF
AOC0832
o
Q
~
R
co
Co)
3R
i;
C
oQ
co
Co)
-1::10
.......
»
c
o
Q
co
Co)
co
1
TL/H/5583-17
Controiler performs a routine to determine which input polarity (9-bit example) or which channel pair (lO-bit example) provides a non-zero output code.
This information provides the extra bits.
a) 9-Bit AID
b)10-Bit AID
Protecting the Input
Vec
15Voc)
1SVOC
-15 Voc
AoeOBlZ
Diodes are IN914
TLlH/5583-18
High Accuracy Comparators
5V
Vee
+ }
SYSTEM
TEST
POINTS
)---1
YtH 3
+
}
~
1
TO
CONTROLLER
AOCOB38
COM
DO ~ allIs if +V'N
> -Y,N
DO ~ all Os if +V'N
< -Y,N
TL/H/5583-38
3-135
N
co
Cf)
co
C)
0
Applications (Continued)
..
C
Convert 8 Thermocouples with only One Cold..Junction Compensator
CC
......
Cf)
co
+
C)
0
C
TYPEJ
IREF
T,
••
•
CC
.....
·
C'I
Cf)
CO
•
C)
0
C
•
•
•
CC
......
.,...
Cf)
CO
C)
0
lk
Vee
2k
C
CC
CH7
AOC0838
MICROWlRE
910
VREF
,
ILM335
I
L
Ta
Vee
22k
r
IREF
CHO
":'
.J
IREF
":'
Vee
lk
LM385
3k
'":'
":'
Uses the 'pseudo-differential mode to keep the differential inputs constant with changes in reference temperature (TREF).
330
Digital Load Cell
TLlH/5583-19
• Uses one more wire than load cell itself
• Two mini-DIPs could be mounted inside load cell for digital output transducer
• Electronic offset and gain trims relax mechanical specs for gauge factor and offset
• Low level cell output is converted immediately for high noise immunity
3·136
»
c
Applications (Continued)
oo
CD
....
4 mA-20 mA Current Loop Converter
(0)
........
lOOk
»
c
oo
=50 kHz
CD
(0)
N
........
INP
24k
6.2k
»
c
oo
Yee
CD
200k r----::VCLe----,
(0)
"""
»
c
........
+IN
oo
CD
(0)
~1-t--t---1-IN
CD
AOC0831
10k
5k ;>oI,....t----I YREF
...t-F-Jy""'- Yee
00 ~~t-
L;.._ _ _ _
47k
3.9k
300k
Y+
"'------Vo
! ~-6-----J
L...------GNO
• All power supplied by loop
TL/H/55B3-20
• 1500V isolation at output
Isolated Data Converter
lN414B
Yee OUT
10k
CLK-W__~
lN4148
'::'
6Y
ClK
470
cs
Yee
~
lOOk
AOC0838
01
Vee
DO
6.8k
'::'
• No power required remotely
• 1500V isolation
TLlH/55B3-39
3-137
ADC0831!ADC0832!ADC0834! ADC0838
~
'0
Two Wire Interface for 8 Channels
"2..
..
n"
I»
ci"
0.1 "F
~
en
10V
"0
0
lk
"g.c:
<11
.s
47k
18k
~Ve
18k
•
CLK/CS
lk
':'
':'
10V
,
'./I~'"
10k > lOOk
t
Vee
lN4148
lOOk
16k
~"
lM393
DUAL CDMP.
ClK
':'
T560PF
47k
':'
68k
~
I
lM393
DUAL CDMP.
':'
~
Ve
c.>
co
lOOk
10k
01
':'
ADC0838
rJ·.·
V+
220
-r
+
T
O. l "F
':'
• No additional connections
" as derived from extended high on ClK line> loo"s rt.rLr""---uuu• Timing arranged for 40 kHz, could be changed up or down by component change
• 10% ClK frequency change without component change OK
c
~
~I
~
lOO "F
veehvee
r
-,
33k
Ve
O. l "F
)0.
C
Applications (Continued)
oo
co
Co)
Two Wire 1·Channellnteriace
rl~
12V
CLK
C
vL
27k
18k
AND
C S - ,2V
10k
18k
12V
I
~
68k
C
~=
47k
l00~
":"
-
DO-
)0.
lk
V
112 lM393
.....
.....
o
o
.-J2N2222
co
Co)
N
.....
)0.
lOOk
C
":"
oo
II
Vee
~
00
10k
*r
":'
10k
lOOk
~ '" lN4148
~
ll
-
16k
I--
":'
47k
~
ff}
~,~,
18k
ClK
Vee
~
ADC0831
Cl
lM393
":" DUAL COMPARATOR
-:r
• Simpler version of B-channel
• CS derived from long ClK pulse
co ...
200
.a:o.
.....
)0.
C
oo
co
Co)
co
lOOk
+
- ' - 560 pF
co
Co)
~ ~ lN4148
.
,
Vee I--
~ r5.1V
-=
~
~
TUH/5583-22
Ordering Information
Total
Unadjusted Error
Package
Temperature
Range
±%
Hermetic (J)
Hermetic (J)
Molded(N)
-55'Cto + 125'C
-40'Cto + 85'C
O'Cto +70'C
ADC0831CCJ
ADC0831CCN
±1
Hermetic (J)
Molded(N)
-40'Cto +85'C
O'Cto +70'C
ADC0832BJ
ADC0832BCJ
ADC0832BCN
±%
Hermetic (J)
Hermetic (J)
Molded (N)
- 55'C to + 125'C
-40'Cto +85'C
O'Cto +70'C
ADC0832CCJ
ADC0832CCN
±1
Hermetic (J)
Molded(N)
-40'Cto +85'C
O'Cto +70'C
ADC0834BJ
ADCOB34BCJ
ADC0834BCN
±%
Hermetic (J)
Hermetic (J)
Molded(N)
- 55'C to + 125'C
-40'Cto +85'C
O'Cto +70'C
±1
Hermetic (J)
Molded(N)
- 40'C to + B5'C
O'Cto +70'C
±%
Hermetic (J)
Hermetic (J)
PCC(V)
Molded(N)
-55'Cto +125'C
- 40'C to + B5'C
O'Cto +70'C
O'Cto +70'C
±1
Hermetic (J)
PCC(V)
Molded(N)
- 40'C to + 85'C
O'Cto +70'C
O'Cto +70'C
Part Number
ADC0831BJ
ADC0831BCJ
ADC0831BCN
Analog Input
Channels
1
2
4
ADCOB34CCJ
ADC0834CCN
ADC0838BJ
ADC083BBCJ
ADC0838BCV
ADC083BBCN
ADC0838CCJ
ADC0838CCV
ADC0838CCN
8
See NS Package Number J08A, J14A, J20A, N08E, N14A, N20A or V20A
3-139
II
~ ~---------------------------------------------------------------------------,
~
~
g
~NatiOnal
Semiconductor
c:r:
Corporation
ADC0833 8-Bit Serial 110 AID Converter
with 4-Channel Multiplexer
General Description
Features
The ADC0833 series is an a-bit successive approximation
AID converter with a serial 1/0 and configurable input multiplexer with 4 channels. The serial 110 is configured to comply with the NSC MICROWIRETM serial data exchange standard for easy interface to the COPSTM family of processors,
as well as with standard shift registers or ,..Ps.
• NSC MICROWIRE compatible-direct interface to COPS
family processors
• Easy interface to all microprocessors, or operates
"stand alone"
• Works with 2.5V (LM336) voltage reference
• No full-scale or zero adjust required
• Differential analog voltage inputs
• 4-channel analog multiplexer
• Shunt regulator allows operation with high voltage
supplies
• OV to 5V input range with single 5V power supply
• Remote operation with serial digital data link
• TTL/MOS input/output compatible
• 0.3" standard width 14-pin DIP package
The 4-channel multiplexer is software configured for singleended· or differential inputs when channel assigned by a 4bit serial word.
The differential analog voltage input allows increasing the
common-mode rejection and offsetting the analog zero input voltage value. In addition, the voltage reference input
can be adjusted to allow encoding any smaller analog voltage span to the full a bits of resolution.
Key Specifications
•
•
•
•
•
a Bits
1 LSB
5 Voc
23 mW
32,..s
Resolution
Total Unadjusted Error
Single Supply
Low Power
Conversion Time
± "h LSB and ±
Connection and Functional Diagrams
Dual-In-Llne Package
cs
2
13
Vee
01
CHO
3
12
CLK
CHI
..
4
AOC0833
11
SARS
10
DO
CH2
5
CH3
6
9
OGNO
7
8
VREF/2
AGNO
SARS
ADDRESS
LATCH
AND
DECODER
01
CHO
CH1
TL/H/5607 -14
Top View
Order Number ADC0833BCJ,
ADC0833BJ, ADC0833CJ,
ADC0833CCJ, ADC0833BCN or
ADC0833CCN
See NS Package Number
J14AorN14A
'CS
ClK
CH2
DO
4-CHANNEl S.E.
OR
2·CHANNEl
DIFF.
MULTIPlIER
CH3
Y'
(SHUNT
REG)
Yee
(5Y)
YREF/2
A GND
TL/H/5607-1
3-140
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Current into V+ (Note 3)
15mA
Supply Voltage, Vee (Note 3)
Voltage
Logic Inputs
Analog Inputs
Input Current per Pin (Note 4)
Package Input Current (Note 4)
Storage Temperature
Package Dissipation at
TA = 25'C (Board Mount)
Lead Temperature (Soldering, 10 sec.)
Dual·ln·Line Package (PlastiC)
Dual·ln·Line Package (Ceramic)
ESD Susceptibility (Note 5)
6.5V
-0.3V to Vee + 0.3V
-0.3VtoVee + 0.3V
±5mA
0.8W
260'C
300'C
2000V
Operating Conditions (Notes 1 & 2)
Supply Voltage, Vee
Temperature Range
ADC0833BJ, ADC0833CJ
ADC0833BCJ, ADC0833CCJ
ADC0833BCN, ADC0833CCN
±20mA
-65'Cto + 150'C
4.5 Vee to 6.3 Vee
TMIN,;:;TA:S;TMAX
-55'C:S;TA';:; 125'C
-40'C:S;TA:S;85'C
0'C,;:;TA:S;70'C
Electrical Characteristics
The following specifications apply for Vee = v+ = 5V, felK = 250 kHz and
VREF/2 ,;:; (Vee + 0.1 V) unless otherwise specified. Boldface limits appl, from TMIN to TMAXi all other limits
TA = Tj = 25'C.
Parameter
Typ
(Note 6)
Conditions
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
±Yz
±%
±1
±1
±%
Units
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Total Unadjusted Error
ADC0833BCN
ADC0883BJ, BCJ
ADC0833CCN
ADC0833CJ, CCJ
VREF/2 Forced to 2.500 Vee
±1
LSB
LSB
LSB
LSB
Minimum Total Ladder
Resistance (Note 9)
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
7.0
7.0
2.6
2.6
2.6
kO
kO
Maximum Total Ladder
Resistance (Note 9)
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
7.0
7.0
11.8
10.8
11.8
kO
kO
GND-0.05
V
V
Vee + 0.05
Vee + 0.05
V
V
±%
±1f4
±%
LSB
LSB
1
1
1
LSB
LSB
Minimum Common·Mode
Input Range (Note 10)
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
All MUX Inputs and COM Input
Maximum Common·Mode
Input Range (Note 10)
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
All MUX Inputs and COM Input
GND-0.05
GND-0.05
Vee + 0.05
DC Common·Mode Error
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
Change In Zero
Error From Vee=5V
To Internal Zener
Operation (Note 3)
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
±v'a
±V,6
15mAlntoV+
Vee = N.C.
VREF/2 = 2.500V
3-141
Electrical Characteristics
The following specifications apply for Vee = V+ = 5V. fClK = 250 kHz and
VREF/2 S; (Vee + 0.1V) unless otherwise specified. Boldface limits apply from tMIN to !MAX; all otherlimitsTA = Tj = 25'C.
(Continued)
Parameter
Typ
(Note 6)
Conditions
Tested
Umlt
(Note 7)
Design
Limit
(Note 8)
Units
CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued)
Vz. Minimum Internal
Diode Breakdown
(At V +) (Note 3)
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
15mAlntoV+
Vz. Maximum Internal
Diode Breakdown
(At V +) (Note 3)
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
15mAlntoV+
Power Supply Sensitivity
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
Vee=5V±5%
IOFF. Off Channel Leakage
Current (Note 11)
ADC0833BCJ/CCJ/BJ/CJ
On Channel = 5V. Off Channel = OV
8.3
8.3
V
V
8.5
8.5
V
V
±y,.
±%
±y,.
LSB
LSB
6.3
8.5
± 1f1a
±Y,6
-1
pA
-200
-1
ADC0833BCN/CCN
-200
nA
p.A
nA
On Channel = OV. Off Channel = 5V
1
ADC0833BCJ/CCJ/BJ/CJ
200
p.A
nA
p.A
nA
1
pA
200
1
ADC0833BCN/CCN
ION. On Channel Leakage
Current (Note 11)
ADC083BCJ/CCJ/BJ/CJ
On Channel = 5V. Off Channel = OV
200
1
ADC0833BCN/CCN
200
nA
p.A
nA
On Channel = OV. Off Channel = 5V
-1
ADC083BCJ/CCJ/BJ/CJ
-200
-1
ADC0833BCN/CCN
-200
p.A
nA
p.A
nA
DIGITAL AND DC CHARACTERISTICS
VIN(l). Logical "1" Input
Voltage
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
Vcc=5.25V
VIN(O). Logical "0" Input
Voltage
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
Vcc=4.75V
IIN(l). Logical "1" Input
Current
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
VIN=VCC
2.0
2.0
2.0
V
V
0.8
V
V
1
p.A
p.A
0.8
0.8
0.005
0.005
3·142
1
1
Electrical Characteristics The following specifications apply for VCC =
VREF/2:S; (Vcc
(Continued)
V+ = SV. fCLK = 250 kHz and
Tj = 2S"C.
+ 0.1V) unless otherwise specified. Boldface limits apply from tMIN totMAXi all otherlimitsTA =
Parameter
Conditions
Typ
(Note 6)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
-O.OOS
-O.OOS
-1
-1
-1
Units
DIGITAL AND DC CHARACTERISTICS (Continued)
IIN(O). Logical "0" Input
Current
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
VIN=OV
VOUT(l). Logical "1" Output
Voltage
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
Vcc=4.7SV
VOUT(O). Logical "0" Output
Voltage
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
IOUT=1.6mA. Vcc=4.7SV
lour. TRI-STATEOulput
Current (DO. SARS)
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
2.4
IOUT= -360",.A
2.4
4.5
V
V
V
V
0.4
V
V
-3
",.A
",.A
3
",.A
",.A
-8.5
mA
mA
8.0
mA
mA
4.5
mA
mA
2.4
4.5
IOUT= -10",.A
4.5
0.4
0.4
VOUT=0.4V
Vour=SV
ISOURCE
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
VOUT Short to GND
ISINK
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
VOUT Short to Vcc
Icc. Supply Current (Note 3)
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
VREF/2 Open Circuit
.).
3-143
-0.1
-0.1
0.1
0.1
-3
-14
-14
-8.5
16
16
8.0
0.9
0.9
4.5
-3
3
3
-7.S
9.0
4.S
",.A
",.A
AC Electrical Characteristics
The following specifications apply for Vee
unless otherwise specified. These limits apply for T A = Ti = 25°C.
Parameter
fClK. Clock Frequency
Conditions
Tested
Typ
(Note
Min
= v+ = 5V and 1,- = tf = 20 ns
6)
Limit
(Note
c. Conversion Time
Clock Duty Cycle (Note 12)
Limit
kHz
400
8
Not including MUX Addressing Time
Units
(Note 8)
10
Max
T
7)
Design
kHz
1lfClK
Min
40
Max
60
%
%
250
ns
90
ns
tSET-UP. CS Falling Edge or
Data Input Valid to ClK
Rising Edge
tHOlD. Data Input Valid
after ClK Rising Edge
= 100pF
t pdl. tpdo-ClK Falling
Cl
Edge to Output Data Valid
Data MSB First
650
1500
ns
(Note 13)
Data lSB First
250
600
ns
tl H. tOH-Rising Edge of CS
Cl
125
250
ns
to Data Output and SARS
= 10 pF. Rl = 10k
CL = 100 pF. Rl = 2k
500
ns
Hi-Z
(see TRI-STATE Test Circuits)
500
CIN. Capacitance of logic
5
pF
5
pF
Input
COUTo Capacitance of logic
Outputs
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical spacifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respact to the ground pins.
Note 3: Internal zener diodes (appro.. 7V) are connected from V+ to GND and Vee to GND. The zener at V+ can operate as a shunt regulator and is connected to
Vee via a conventional diode. Since the zener voHage equals the AID's breakdown voHage, the diode Insures that Vee will be below breakdown when the device is
powered from V+. Functionality is therefore guaranteed for V+ oparation even though the resultant voltage at Vee may exceed the specified Absolute Max. of
6.5V. It Is recommended that a resistor be used to limit the max. current into V+.
Note 4: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V- or VIN > V+) the absolute value of current at that pin should be limited
to 5 rnA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four.
Note 5: Human body model, 100 pF discharged through a 1.5 kll resistor.
Note 6: Typicals are at 25'C and represent most likely parametric norm.
Note 7: Tested IIm"s are guaranteed to National's AOOl (Average Outgoing Ouality Level).
Note 8: Design lim"s are guaranteed but not 100% tested. These limits are not used to calculate outgoing qualHy levels.
Note 9: See Applications, section 3.0.
Note 10: For VIN( -):> VIN( +) the digHaI output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward
conduct for analog input voHages one diode drop below ground or one diode drop greater than the Vee supply. Be careful, during testing at low Vee levels (4.5V),
as high level analog inputs (5V) can cause this input diode to conduCI--especially at elevated temperatures, and cause errors for analog Inputs near full-scale. The
spec allows 50 mV forward bias of eHher diode. This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 50 mY, the
output code will be correct. To achieve an absolute 0 Vee to 5 Vee input voHage range will therefore require a minimum supply voltage of 4.950 Vee over
temperature variations, initial tolerance and loading.
Note 11: Leakage current Is measured with the clock not switching.
Note 12: A 40% to 60% clock duty cycle range insures propar operation at all clock frequencies. In the case that an available clock has a duty cycle outside of
these limits, the minimum time the clock is high or the minimum time the clock Is low must be at least 1",s. The maximum lime the clock can be high Is 60 ",s. The
clocked can be stoppad when low so long as the analog Input voHage remains stable.
Note 13: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to
allow for comparator response time.
3-144
r--------------------------------------------------------------------.~
C
Timing Diagrams
o
c
CD
Co)
Co)
Data Input Timing
Data Output Timing
CLK
DATA
OUT 1001
TRI-STATE Test Circuits and Waveforms
~~'H
~
DDANo:::
SARSDUTPUTS
GNo------=
',=20ns
tOH
Vcc
Vcc
GND
DATA
OUTPUT
DUND Vcc
SARS OUTPUTS VOL
:P.
10%
',=20 ns
Leakage Current Test Circuit
iV
ADCD833
CH A ION CHANNELl
CHANNEL
. .----1:::
L.........
j:::NNELS
CH 0
VOLTAGE
SELECT
TUH/5607-2
3-145
Typical Performance Characteristics
Effect of Unadjusted Offset
Error VS. VREF/2 Voltage
~
::
VIN(+)=VIN(-)=OV
'-'
~~U~~~E2 ::'~D
12
10 ; -
FOR A ZERO ADJ. IF
THE SPAN IS REDUCED.
=
j"
0.01
Linearity Error vs
VREF Voltage
~
'"
~
~~
1~r--+---r--+---~-1
Vcc=5V
(250KHz) _
1.0
TA=25OC
0.75
1\
O~
I1:
illz
::l
e'"
1"--
0.25
Vcc=5V
VrtrF/2= 2.5V
fcue 250 KHt'
2~
i __
1
-100 -50
~
0
__
L-~
Power Supply Current
vs Temperature
__
100
50
TE~PERATURE
VREFEl2(V)
Linearity Error vs fCLK
~
,,~
...~
oL-~
0
~
150
(OC)
Output Current
vs Temperature
25,----.".--,--....,...-..,.-----,
3.0
2~
0.50 ,----...---,--....,.--,..--,
~~
'-
O~
0
1.0
0.1
Linearity Error
vs Temperature
1~~~--.---.--.--,
VRFF/2= 2.5V
VCC=5V
1250C
2.0
1.5
1.0
O~
I
-55OC
L
L
250C
o
0
10 100
200
300
o4OD
-100 -50
500 600
50
100
125
TEIIPERATURE (OC)
TEIIPERATURE (OC)
fCLK (KIlz)
Power Supply
Current vs fCLK
2~
1
I
vcc
1sv
@i5oc
2.0
~
~
1~_
el
'"
:i!
1.0
0
100
200
300
o4OD
500
tCLKZ. ·=."
s••m
~~_~.:M~U:X~C~O::.~"~.U~RA~·;~:O'~.:...W~O~RO~'t::t:::-----------1-__________.l-____~S~~:!i!~E
CARE
(SARs) TRI.
MUX
STATE
SEnLiNG-t----t--TIME
TRI·
STATE
DATA~~1---TRI-STATE'----I
Tl/H/5607-5
acquisition systems is significantly simplified with this type
of input flexibility. One converter package can now handle
ground referenced inputs and true differential inputs.
A particular input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single-ended or differential. In the differential case, it also assigns the polarity of the
channels. Differential inputs are restricted to adjacent channel pairs. For example channel 0 and channel 1 may be
selected as a differential pair. Channel 0 or 1 cannot act
differentially with any other channel. In addition to selecting
differential mode the sign may also be selected. Channel 0
may be selected as the positive input and channel 1 as the
negative input or vice versa. This programmability is best
illustrated by the MUX addressing codes shown in the following table. The MUX address is shifted into the converter
through the DI line.
Functional Description
1.0 MULTIPLEXER ADDRESSING
The design of the ADC0833 utilizes a sample-data comparator structure which provides for a differential analog input
to be converted by a successive approximation routine.
The actual voltage converted is always the difference between an assigned" +" input terminal and a .. -" input terminal. The polarity of each input terminal of the pair being
converted indicates which line the converter expects to be
the most positive. If the assigned" +" input is less than the
.. -" input the converter responds with an all zeros output
code.
A unique input multiplexing scheme has been utilized to provide multiple analog channels with software-configurable
single-ended (ground referred) or differential inputs. The analog signal conditioning required in transducer-based data
TABLE 1_ MUX Addressing
Single-Ended MUX Mode
Channel #
Address
SGLI
0001
OIF
SIGN
1
0
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
SELECT
0
1
2
3
+
+
+
+
COM is Internally ties to a GND
Differential MUX Mode
Channel #
Address
SGL/.
0001
OIF
SIGN
1
SELECT
0
1
+
-
2
3
+
-
-
+
0
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
3-148
-
+
Functional Description
(Continued)
Since the input configuration is under software control. it
can be modified. as required. at each conversion. A channel
can be treated as a single-ended. ground referenced input
for one conversion; then it can be reconfigured as part of a
differential channel for another conversion. Figure 1 illustrates the input flexibility which can be achieved.
ting highly noise immune digital data back to the host processor.
To understand the operation of these converters it is best to
refer to the Timing Diagram and Functional Block Diagram
and to follow a complete conversion sequence.
1. A conversion is initiated by first pulling the CS (chip select) line low. This line must be held low for the entire conversion. The converter is now waiting for a start bit and its
MUX assignment word.
2. A clock is then generated by the processor (if not provided continuously) and output to the AID clock input.
3. On each rising edge of the clock the status of the data in
(01) line is clocked into the MUX address shift register. The
start bit is the first logic "1" that appears on this line (all
leading zeros are ignored). Following the start bit the converter expects the next 4 bits to be the MUX assignment
word.
The analog input voltages for each channel can range from
50 mV below ground to 50mV above Vcc(typically 5V) without degrading conversion accuracy.
2.0 THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system improvements; it allows more function to be included in the
converter package with no increase in package size and it
can eliminate the transmission of low level analog signals by
locating the converter right at the analog sensor; transmit-
4 Single-Ended
o
2 Differential
+
+
D.l{
2.3{
+(-)
-(+)
+(-)
-(+)
A GND
Mixed Mode
O.l{
+
+
3
+
AGND
':'
TLIH/5607-6
FIGURE 1. Analog Input Multiplexer Options for the ADC0833
3-149
~ r-------------------------------------------------------------------~
~
8
c
cc
inputs vary between very specific voltage limits and the reference voltage for the AID converter must remain stable
with time and temperature. For ratio metric applications, an
ADC0834 is a pin-for-pin compatible alternative since it has
a VREF input (note the ADC0834 needs one less bit of mux
addressing information).
Functional Description (Continued)
4. When the start bit has been shifted into the start location
of the MUX register, the input channel has been assigned
and a conversion is about to begin. An interval of 112 clock
period (where nothing happens) is automatically inserted to
allow the selected MUX channel to settle. The SAR status
line goes high at this time to signal that a conversion is now
in progress and the 01 line is disabled (it no longer accepts
data).
The voltage applied to the VREF/2 pin defines the voltage
span of the analog input [the difference between VIN( +)
and VIN( -)1 over which the 256 possible output codes apply. A full-scale conversion (an all 1s output code) will result
when the voltage difference between a selected "+" input
and "-" input is approximately twice the voltage at the
VREF/2 pin. This internal gain of 2 from the applied reference to the full-scale input voltage allows biasing a low voltage reference diode from the 5Voe converter supply. To
accommodate a 5V input span, only a 2.5V reference is
required. The LM385 and LM336 reference diodes are good
low current devices to use with these converters. The output code changes in accordance with the following equation:
5. The data out (DO) line now comes out of TRI-STATE and
provides a leading zero for this one clock period of MUX
settling time.
6. When the conversion begins, the output of the SAR comparator, which indicates whether the analog input is greater
than (high) or less than (low) each successive voltage from
the internal resistor ladder, appears at the DO line on each
falling edge of the clock. This data is the result of the conversion being shifted out (with the MSB coming first) and
can be read by the processor immediately.
7. After 8 clock periods the conversion is completed. The
SAR status line returns low to indicate this 112 clock cycle
later.
VIN(+) - VIN(-»)
Output Code = 256 (
2(VREF/2)
where the output code is the decimal equivalent of the 8-bit
binary output (ranging from 0 to 255) and the term VREF/2 is
the voltage from pin 9 to ground.
8. If the programmer prefers, the data can be read in an LSB
first format. All 8 bits of the result are stored in an output
shift register. The conversion result, LSB first, is automatically shifted out the DO line, after the MSB first data stream.
The DO line then goes low and stays low until CS is returned high.
The VREF/2 pin is the center point of a two resistor divider
(each resistor is 3.5 kO) connected from Vee to ground.
Total ladder input resistance is the sum of these two equal
resistors. As shown in Figure 2, a reference diode with a
voltage less than Vee/2 can be connected without requiring
an external biasing resistor if its current requirements meet
the indicated level.
9. All internal registers are cleared when the CS line is high.
If another conversion is desired, CS must make a high to
low transition followed by address information.
The 01 and DO lines can be tied together and controlled
through a bidirectional processor I/O bit with one wire. This
is possible because the 01 input is only "looked-at" during
the MUX addressing interval while the DO line is still in a
high impedance state.
The minimum value of VREF/2 can be quite small (see Typical Performance Characteristics) to allow direct conversions
of transducer outputs providing less than a 5V output span.
Particular care must be taken with regard to noise pickup,
circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of
the converter (1 LSB equals VREF/256).
3.0 REFERENCE CONSIDERATIONS
The ADC0833 is intended primarily for use in circuits requiring absolute accuracy. In this type of system, the analog
Vee
Vee
5V
CHO
-
CHO
3.5k
CHI1-
VRE
ADC0833
3.5k
,-
CHI
+
VREF!2
ADC0833
CH2i -
CH2I -
CH3I -
-
5V
3.5k
GND
~~LM385-1.2V
1
CH3I -
1
...
3.5k
':~M336-2.5V
• L
.!!o
GND
TLlH!5607-7
VFULL.SCALE"'2.4V
VFULL.SCALE"'S.OV
Vee
Vcc!2 - Vz
Not.: No extemal biasing resistor needed if Vz < Tand Iz min < ~
FIGURE 2. Reference Biasing Examples
3-150
l>
c
Functional Description (Continued)
is necessary to just cause an output digital code transition
from 0000 0000 to 0000 0001 and the ideal V. LSB value
(V. LSB=9.8 mV for VREF/2=2.500 VDcl.
4.0 THE ANALOG INPUTS
The most important feature of these converters is that they
can be located right at the analog signal source and through
just a few wires can communicate with a controlling proces·
sor with a highly noise immune serial bit stream. This in itself
greatly minimizes circuitry to maintain analog signal accuracy which otherwise is most susceptible to noise pickup.
However, a few words are in order with regard to the analog
inputs should the inputs be noisy to begin with or possibly
riding on a large common-mode voltage.
The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
to both selected" +" and" -" inputs for a conversion (60
Hz is most typical). The time interval between sampling the
"+" input and then the "-" input is V. of a clock period.
The change in the common-mode voltage during this short
time interval can cause conversion errors. For a sinusoidal
common-mode signal this error is:
5.2 Full-Scale
The full-scale adjustment can be made by applying a differential input voltage which is 1 V. LSB down from the desired
analog full-scale voltage range and then adjusting the magnitude of the VREF input or VCC for a digital output code
which is just changing from 1111 1110 to 1111 1111.
5.3 Adjusting for an Arbitrary Analog Input Voltage
Range
If the analog zero voltage of the AID is shifted away from
ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference
should be properly adjusted first. A VIN( +) voltage which
equals this desired zero reference plus V. LSB (where the
LSB is calculated for the desired analog span, using
1 LSB=analog span/256) is applied to selected "+" input
and the zero reference voltage at the corresponding "-"
input should then be adjusted to just obtain the OOHEX to
01 HEX code transition.
The full-scale adjustment should be made [with the proper
Vln(-) voltage applied] by forcing a voltage to the VIN(+)
input which is given by:
0.5 )
Verror(max) = VPEAK(21TfCM) ( fClK
where fCM is the frequency of the common·mode signal,
VPEAK is its peak voltage value
and fClK is the AID clock frequency.
For a 60 Hz common-mode signal to generate a % LSB
error (~5 mY) with the converter running at 250 kHz, its
peak value would have to be 6.63V which would be larger
than allowed as it exceeds the maximum analog input limits.
.
[ (VMAX - VMIN) ]
VIN ( + ) fs adJ = VMAX - 1.5
256
where:
VMAX= the high end of the analog input range
Due to the sampling nature of the analog inputs short spikes
of current enter the" + .. input and exit the" -" input at the
clock edges during the actual conversion. These currents
decay rapidly and do not cause errors as the internal com·
parator is strobed at the end of a clock period. Bypass capacitors at the inputs will average these currents and cause
an effective DC current to flow through the output resistance of the analog signal source. Bypass capacitors should
not be used if the source resistance is greater than 1 kO.
This source resistance limitation is important with regard to
the DC leakage currents of input multiplexer as well. The
worst-case leakage current of ± 1 p.A over temperature will
create a 1 mV inut error with a 1 kO source resistance. An
op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance
signal source be required.
and
VMIN = the low end (the offset zero) of the analog
range.
(Both are ground referenced.)
The VREF/2 voltage is then adjusted to provide a code
change from FEHEX to FFHEX. This completes the adjustment procedure.
6.0 POWER SUPPLY
A unique feature of the ADC0833 is the inclusion of a 7V
zener diode connected from the V+ terminal to ground
which also connects to the VCC terminal (which is the actual
converter supply) through a silicon diode, as shown in Figure3.
5.0 OPTIONAL ADJUSTMENTS
R y+
5.1 Zero Error
The zero of the AID does not require adjustment. If the
minimum analog input voltage value, VIN(MIN), is not ground
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biasing any VIN (-) input at this VIN(MIN) value. This
utilizes the differential mode operation of the AID.
Va
..... ,
... ,
Vee
ACTUAL
CONVERTER
SUPPLY
~~7Y
The zero error of the AID converter relates to the location
of the first riser of the transfer function and can be measured by grounding the VIN( -} input and applying a small
magnitude positive voltage to the VIN( + ) input. Zero error is
the difference between the actual DC input voltage which
GND
TLlH/5607 -8
FIGURE 3. An On-Chip Shunt Regulator Diode
3-151
iw
w
~
~
8
c
cr:
r---------------------------------------------------------------------------------,
Functional Description (Continued)
This zener is intended for use as a shunt voltage regulator
to eliminate the need for any additional regulating components. This is most desirable if the converter is to be remotely located from the system power source. F/{Jures 4
and 5 illustrate two useful applications of this on-board zener when an external transistor can be afforded.
to be derived from the clock. The low current requirements
of the AID (- 3 mAl and the relatively high clock frequencies used (typically in the range of 10k-400 kHz) allows using the small value filter capacitor shown to keep the ripple
on the Vee line to well under 1,4 of an LSB. The shunt zener
regulator can also be used in this mode. This requires a
clock voltage SWing which is in excess of Vz. A current limit
for the zener is needed, either built into the clock generator
or a resistor can be used from the CLK pin to the V+ pin.
An important use of the interconnecting diode between V+
and Vee is shown in Figures 6 and 7. Here, this diode is
used as a rectifier to allow the Vcc supply for the converter
Applications
12Y
. . - -.....- SYSTEM
SUPPLY
1.6k
Y. 7V
AllC0833
J2V
lk
:;.---1>-i---.............+- Vee
SYsn;M ......WIr-.....-~
SUPPlY
6.4
Vee 6.4
A0C0833
T
O1
•
CMOS
OR
NMOS
CIRCUITS
ANALOG
CIRCUITS
GNO
TL/H/5607-16
TLlH/5607-15
FIGURE 5. Using the AID as the
System Supply Regulator
FIGURE 4. Operating with a Temperature
Compensated Reference
yt'
.........
vee
f10'J.I F
--
TRANSDUCER
AOC0833
100 MHz
CLOCK
S.3V:Jlf ..
1k
,
CLK
GND
~
-
3.9k
~7
TLlH/5607 -9
TLlH/5607-17
FIGURE 7. Remote Senslng-Clock
and Power on 1 Wire
'Note 4.5V ,;: vee ,;: 6.3V
FIGURE 6. Generally Vee from the Converter Clock
3-152
Applications
»
c
(Continued)
(')
o
CD
(0)
(0)
Digital Link and Sample Controlling Software for the
Serially Oriented COP420 and the Bit Programmable 1/0 INS8048
CHO
CHO
GO
•
•
5K
•
AOC0833
•
COP420
so
•
CH3
DO
AOC0833
IN5B048
•
51
CH3
TLiH/S607-10
COP CODING EXAMPLE
Mnemonic
LEI
SC
OGI
CLRA
AISC1
XAS
LDD
NOP
XAS
8048 CODING EXAMPLE
Instruction
ENABLES SIO's INPUT AND OUTPUT
C=1
GO=O(CS=O)
CLEARS ACCUMULATOR
LOADS ACCUMULATOR WITH 1
EXCHANGES SIO WITH ACCUMULATOR
AND STARTS SK CLOCK
LOADS MUX ADDRESS FROM RAM
INTO ACCUMULATOR
Mnemonic
ANL
P1, #OF7H
MOV B, #5
MOV A,#ADDR
LOOP 1: RRC A
JC
ONE
START:
ZERO:
ONE:
CONT:
ORL
CALL
DJNZ
CALL
MOV
LOOP 2: CALL
IN
RRC
RRC
MOV
RLC
MOV
DJNZ
RETR
LOADS MUX ADDRESS FROM
ACCUMULATOR TO SIO REGISTER
t
8 INSTRUCTIONS
.J,
XAS
XIS
CLRA
RC
XAS
XIS
OGI
LEI
ANL
JMP
READS HIGH ORDER NIBBLE (4 BITS)
INTO ACCUMULATOR
PUTS HIGH ORDER NIBBLE INTO RAM
CLEARS ACCUMULATOR
·C= 0
READS LOW ORDER NIBBLE INTO
ACCUMULATOR AND STOPS SK
PUTS LOW ORDER NIBBLE INTO RAM
GO=1 (CS=1)
DISABLES SIO's INPUT AND OUTPUT
PULSE:
3·153
ORL
NOP
ANL
RET
Instruction
;SELECT AID (CS=O)
;BIT COUNTER +- 5
;A - MUX ADDRESS
;CV - ADDRESS BIT
;TESTBIT
;BIT=O
P1, #OFEH ;DI-O
CONT
;CONTINUE
;BIT=1
P1, #1
;DI-1
PULSE
;PULSE SK 0 - - 1 - - 0
B, LOOP 1 ;CONTINUE UNTIL DONE
;EXTRA CLOCK FOR SYNC
PULSE
B,#8
;BIT COUNTER +- 8
PULSE
;PULSE SK 0 - - 1 - - 0
A,P1
;CV+-DO
A
A
;A-RESULT
A,C
A
;A(O) - BIT AND SHIFT
C,A
;C-RESULT
B, LOOP 2 ;CONTINUE UNTIL DONE
;PULSE SUBROUTINE
;SK+-1
;DELAV
P1, #OFBH ;SK+-O
P1, #04
Applications (Continued)
A "Stand-Alone" Hook-Up for ADC0833 Evaluation
MUM ADDRESS
;::==::;:===;:==~==:;..-o 5VDC
-START lIT
5111(4)
SGuiffi:
,£ ,£ ,£ ,£
s
12
13
IS
.4
PARALLEL IllPUTS
3
INPUT SHIFT REGISTER
74C185
5Vac
lVoc
IVoe
OUTPUTSHrFT REGISTER
'l4ell4
'2
".
no
"
NSUOU(I!
I'/2ne')'.
...-t~",~",~~",~",,,,~,,,~~,,,~,,,-o'V.e
~
DATA DISPLAY
MSI
LSI
Low Cost Remote Temperature Sensor
·e.
IIVae)
.,,1-......,..+-.
llQU
~lhf
.,..
ADCII31
7.511
IVae
TL/H/5607-11
3-154
Applications (Continued)
Digitizing a Current Flow
VCC
0.1
_
'LOAD
(ZA FULL·SCALE)
(SVoC) o-~P-¥o.""~P-----"';;'''';;;=--''';;'';';';'';;';;'';;';';';'~----------'''
VCC
(SVoC)
VCC~-----~------~
CHO
J
+
AoC0833
100
ZERO
AoJ
>~""------4 CHI
Z.
'O I'F
9.1.
LM336
-c:
VREF/Z ~...- -.....
Operating with Automotive Ratiometric Transducers
VCC
(SVDC'
ZOk
Vccl--....
XDR
+
~'0I'F
ADCD833
1&.
VREF/Z
0.35 VCC
lk
~_........... FS
AoJ
8.2k
'VIN(-)=O.15 Vcc
15% of VCC<:VXDA<:85% of Vcc
TL/H/5607-12
3-155
~
~
~
r---------------------------------------------------------------------------------,
Applications
(Continued)
8cc
Span Adjust: OV",;VIN",;3V
Vee
CIVDe)
Vee~-1~------------_,
+
~101lF
ADCII33
TL/H/5607-1B
Zero-Shift and Span Adjust: 2V",; VIN"'; 5V
Vee
(5VDe)
Vee ~-1~----------------'"
,.....-:>---1 V,NI-)
1.2'
ADCOIl3
r- - - - - - - - ,
I
1
I
I
.---...---.1
I
SETS ZERO
CODE VOLTAGE
Uk
1
I
330
_J
11
2Yoc
':"
':"
':"
ZERO ADJ
TL/H/5607 -19
Protecting the Input
High Accuracy Comparators
Vee
5V
Vee
(5 Voc)
-['
mT
POINTS
Yr"
: to"~
ADCOI33
I
'intI
TO
CONTROLLER
: }I,a
-15 Voc
ADC0833
DO = alllsif + VIN
DO
= all Os If +
D)ode. are I N914
TLlH/5607 -20
For additional application Ideas, refer to the data sheet for the ADCOS31 family of serial data converters,
3-156
> -VIN
VIN < -VIN
TL/H/5607 -13
Ordering Information
Part Number
Temperature
Range
ADCOB33BCJ
-40'Clo +B5'C
ADCOB33BCN
O'Clo +70'C
ADCOB33BJ
-55'C 10 + 125'C
ADCOB33CCJ
-40'Clo +B5'C
ADCOB33CCN
ADCOB33CJ
O'Clo +70'C
-55'Clo + 125'C
3-157
Total
Unadjusted
Error
±1/2LSB
±1 LSB
..... r--------------------------------------------------------------------------------,
~
_NatiOnal
Semiconductor
cc
Corporation
g
ADC0841
8-Bit p.P Compatible AID Converter
General Description
Features
The ADC0841 is a CMOS 8-bit successive approximation
AID converter. Differential Inputs provide low frequency input common mode rejection and allow offsetting the analog
range of the converter. In addition, the reference input can
be adjusted enabling the conversion of reduced analog
ranges with 8-bit resolution.
• Easy interface to all microprocessors
• Operates ratiometrically or with 5 Vee
voltage reference
• No zero or full-scale adjust required
• Internal clock
• OV to 5V input range with single 5V power supply
• 0.3" standard width 20-pin package
• 20 Pin Molded Chip Carrier Package
The AID is designed to operate with the control bus of a
variety of microprocessors. TRI-STATE output latches that
directly drive the data bus permit the AID to be configured
as a memory location or 1/0 device to the microprocessor
with no interface logic necessary.
Key Specifications
•
•
•
•
•
8 Bits
Resolution
Total Unadjusted Error
Single Supply
Low Power
Conversion Time
±Yz LSB and
± 1 LSB
5 Vee
15mW
40,",s
Block and Connection Diagrams
INm
(5)
+
8-BIT
S.A.R.
VIN(+) --;----+(
(6)
'------.I\) TRI-STATE
OUTPUT
LATCHES
r
AID
080(18)-087(11)
V1N(-) - - ; - - -....
(7)
TUH/B557-1
Dual-In-Llne Package
cs
1
20
Ali
WR
2
19
Vee
N.C.
3
18
DBO
N.C.
4
17
DBl
111m
5
16
OB2
VIN(+)
VIN(-)
6
15
083
7
14
OB4
AGNO
8
13
085
VREF
OGNO
9
12
OB6
10
11
087
Molded Chip Carrier Package
DBD
DBl
DB2
DB3
DB4
18
17
16
15
14
N.C.
19
13
DB5
Vee
20
12
OB6
cs
11
OB7
RO
10
OGNO
9
VREF
WR
3
TL/H/B557-2
Top View
N.C.
(N.C.-No Connection)
INm VIN(+) V1k) AGNO
TL/H/B557-3
Top View
3-158
l>
c
Absolute Maximum Ratings
(Notes 1 & 2)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (Vecl
Voltage
Logic Control Inputs
At Other Inputs and Outputs
Input Current Per Pin (Note 3)
-0.3V to Vee+0.3V
-0.3V to Vee+0.3V
±5mA
Input Current Per Package (Note 3)
co
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (Plastic)
Dual-In-Line Package (CeramiC)
Molded Chip Carrier Package
Vapor Phase (60 seconds)
Infrared (15 seconds)
ESD Susceptibility (Note 10)
6.5V
Storage Temperature
Package Dissipation at TA = 25'C
o
o
260'C
300'C
215'C
220'C
800V
Operating Conditions (Notes 1 and 2)
±20mA
-65'Cto +150'C
875mW
Supply Voltage (Vecl
Temperature Range
ADC0841 BCN, ADC0841CCN
ADC0841 BCJ, ADC0841CCJ,
ADC0841 BCV, ADC0841 CCV
ADC0841 BJ, ADC0841 CJ
4.5 Voe to 6.0 Voe
TMIN:;;TA:;;TMAX
O'C:;;TA:;;70'C
-40'C:;;TA:;;85'C
-55'C:;;TA:;;125'C
Electrical Characteristics The following specifications apply for Vee= 5 Voe unless otherwise specified.
Boldface limits apply from TMIN to TMAX; all other limits TA=Tj=25'C.
ADC0841 BJ, ADC0841 BCJ
ADC0841CJ, ADC0841CCJ
Parameter
Conditions
Typ
(Note 6)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
ADC0841 BCN, ADC0841CCN
ADC0841 BCV, ADC0841CCV
Typ
(Note 6)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Units
±'Iz
±%
±1
±1
LSB
LSB
LSB
LSB
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Maximum Total
Unadjusted Error
ADC0841 BCN, BCV
ADC0841 BJ, BCJ
ADC0841CCN, CCV
ADC0841CJ, CCJ
VREF= 5.00 Voe
(Note 4)
±%
±1
Minimum Reference
Input Resistance
2.4
1.1
2.4
1.2
1.1
kO
Maximum Reference
Input Resistance
2.4
5.9
2.4
5.4
5.9
kO
Maximum Common-Mode
Input Voltage
(Note 5)
Vee + 0.05
Vee + 0.05
Vee + 0.05
V
Minimum Common-Mode
Input Voltage
(Note 5)
GND-0.05
GND-0.05
GND-0.05
V
DC Common-Mode Error
Differential Mode
±1f.6
±y..
±1j'6
±%
±y..
LSB
Power Supply Sensitivity
Vcc=5V±5%
±1f.6
±%
±1f.6
±'Is
±%
LSB
3-159
....""
Electrical Characteristics The following specifications apply for Vee = 5 Voe unless otherwise speCified.
Boldface limits apply from T MIN to T MAX; all other limits T A = Tj = 25°C. (Continued)
ADC0841BJ, ADC0841BCJ
ADC0841CJ, ADC0841CCJ
Symbol
Parameter
Conditions
Typ
(Note 6)
Tested
Umit
(Note 7)
Design
Limit
(Note 8)
ADC0841BCN, ADC0841CCN
ADC0841 BCV, ADC0841CCV
Typ
(Note 6)
Tested
Umlt
(Note 7)
Design
Umlt
(Note 8)
Units
DIGITAL AND DC CHARACTERISTICS
VIN(1)
logical "1" Input
Voltage (Min)
Vee=5.25V
2.0
2.0
2.0
V
VIN(O)
logical "0" Input
Voltage (Max)
Vee=4.75V
0.8
0.8
0.8
V
IIN(1)
logical "1" Input
Current (Max)
VIN=5.0V
IIN(O)
logical "0" Input
Current (Max)
VIN=OV
VOUT(1)
logical "1"
Output Voltage (Min)
Vee = 4.75V
IOUT= -360 p.A
IOUT=-10p.A
VOUT(O)
logical "0"
Output Voltage (Max)
Vcc=4.75V
IOUT=1.6mA
lOUT
TRI-STATE Output
Current (Max)
VOUT=OV
VOUT=5V
-0.01
0.01
-3
3
ISOURCE
Output Source
Current (Min)
VOUT=OV
-14
ISINK
Output Sink
Current (Min)
VOUT= Vcc
Icc
Supply Current (Max)
CS=1, VREFOpen
0.005
1
0.005
1
p.A
-0.005
-1
-0.005
-1
p.A
2.4
4.&
2.8
4.6
2.4
4.&
V
V
0.4
0.34
0.4
V
-0.01
0.01
-0.3
0.3
-3
3
p.A
/LA
-6.&
-14
-7.5
-6.5
mA
16
8.0
16
9.0
8.0
mA
1
2.&
1
2.3
2.5
mA
3-160
AC Characteristics The following specificalions apply for Vcc =
5Voc,lr = If = 10 ns unless olherwise specified.
Boldface limits apply from T MIN to T MAX; all olher Iimils T A = T J = 25'C.
Parameter
Typ
Conditions
tc
Maximum Conversion Time (See Graph)
Iv.tlWRL
Minimum WR Pulse Width
(Note 9)
tACC
Maximum Access Time (Delay from Falling Edge of
CL = 100pF
RD to Output Data Valid)
(Note 9)
tWI,IRI
30
TRI-STATE Control (Maximum Delay from Rising
CL = 10 pF, RL = 10k,
Edge of RD 10 Hi-Z State)
tr = 20 ns (Note 9)
Maximum Delay from Falling Edge of WR or RD to
(Note 9)
(Note
7)
0l:Io
......
Design
Limit
(Note 6)
t'H, toH
oo
CO
Tested
Symbol
»
c
Limit
Units
(Note 8)
60
40
,..S
50
150
ns
145
225
ns
200
125
200
ns
ns
400
Resel of INTR
CIN
Capacitance of Logic Inputs
5
pF
COUT
Capacitance of Logic Outputs
5
pF
Nole 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Nole 2: All voltages are measured with respect to the ground pins.
Nole 3: During over-voltage conditions (V,NVee) the maximum input current at anyone pin is ±5 mAo If the current is limited to ±5 mA at all the
pins no more than four pins can be in this condition in order to meet the Input Current Per Package (± 20 rnA) specification.
Note 4: Total undajusted error includes offset, full-scale, and linearity.
Nole 5: For Y,N (-) ;;, Y,N (+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input, which will forward-conduct for analog
input voltages one diode drop below ground or one diode drop greater than Vee supply. Be careful during testing at low Vce levels (4.5V), as high level analog
inputs (5V) can cause this input diode to conduct especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV
forward bias of either diode. This means that as long as the analog V,N does not exceed the supply voltage by more than 50 mV, the output code will be correct. To
achieve an absolute 0 Voe to 5 Voe input voltage range will therefore require a minimum supply voltage of 4.950 Voc over temperature variations, initial tolerance
and loading.
Note 6: Typicals are at 25'C and represent most likely parametric norm.
Nole 7: Tested limits are guaranteed to National's AOQL (Average OutgOing Quality Level).
Note 8: Design limits are guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 9: The temperature coefficient is 0.3%/"C.
Note 10: Human body model. 100 pF discharged through 1.5 kG resistor.
Timing Diagram
&5\
Wii
-
~~
I
J
/I
11
iiii
---
tWI
INTR _____ J
I--I!
tc
JL
}}
,
,
-
'l
tR11---
1\
'{
}
.
r- - - - - - - - - - '1
NOTE 1
DBD-DB7
II
~~
If
\.
r
\
------ --------------
..,
TRI-STATE
tACC-
.
tlH. tOH·
OBD-OB7
~-
I--TL/H/8557 -9
Nole 1: Read strobe must occur at least 600 ns after the assertion of interrupt to guarantee reset of INTR.
3-161
..8.-
r-------------------------------------------------------------------------------------~
Typical Performance Characteristics
cc(
Logic Input Threshold .
Voltage vs Supply Voltage
~
1.1
i. .
1.1
9
1.1
0-
1.1
_
-BI'C
i..
Ycc,:"SY
i
I
f"
~
~
~
u
ii
4.1i
i.1I
1.21
20
15
~~±=+'=+:~~d-;
10
~~~~~p'-~~
1.10
Linearity Error vs VREF
60
Ycc~5V
I
I
-
\..
....
3:
a
2
a
3
4.5
V!EF (VI
4.15
5
5.25
SUPPlY VOLTAGE IV)
5.5
Vcc=~
~
40
- I:
11!
lD
a
~
D.5
10
~
.........
Conversion Time vs
Temperature
10
40
r- .... "'"
D
-n-IO-250 25 10 nl00125
TEMPERATURE ('C)
TA=25'C
I: 3:
TAan'C
(ZERO AHa FULL-SCALEADJUSTEDI
I
Conversion Time vs VSUPPLY
1.0
&!
iii
0.5
I
TEM~REI'CI
Vcc -SUPPLY VOLTAGE lYocl
!
i '·5
ol-.l..-.l..-I--I--I--I--L-I
-75 -50 -25 a 25 50 75 100 125
9 1.1
UI
Power Supply Current vs
Temperature
s: TA -s; +IZI'C
~
I
Output Current vs
Temperature
30
10-"1"""
i.;o'
~"
I'"
a
-TS-IO-25 a 25 10 75 100 125
TEMPElIATURE I'CI
TLlH/8557-4
Unadjusted Offset Error vs
VREF Voltage
14
!
I
m
co
TRI-STATE Test Circuits and Waveforms
~~:!!'vn.t_I~:'1
12
10
a
4
a
0.01
rr-
VOI=2mV
TA = 2S'C
rr-
"
0.1
1.0
VlEF IVI
TLlH/8557 -5
TL/H/B557-22
tOH. CL = 10 pF
tOH
Vee
Vee
Vee
DATA :::
OUTPUTS
GND
~~'H
~
OH
vee
DATA
OUTPUTS
---------==
~
----10%
VOL
TL/H/8557 -6
TL/H/8557 -8
I, = 20ns
TL/H/8557 -7
3-162
I, = 20n8
."
C
::s
n
VREF AGND
90
08
0'
::s
e!.
Vee
m
START
LADDER AND DECODER
rlr
0'
n
DAC
~
C
0-..--+----.
6
V1N (+)
iii'
ea
DJ
9-BIT
3
SHIrT REGISTER
7
V1N(-) 0
•
~
ONE SHOT
~
TRI-STATE
OUTPUT LATCHES
,
,
xrER If
,
1-6oons
TRI 141-----,
....
, "1 "=OUTPUT
I
ENABLE
DELAY
LSB
t.4SB
11 12 13 14 15 16 17 18
DB7 DB6 DB5 DB4 DB3 DB2 DB 1 DBa
DIGITAL OUTPUTS
~t800a"
II
.., r------------------------------------------------------------------------------------------,
~
8
c
C
(Continued)
(')
oCC)
5V
....""
5V
~
2.7k.o.
1.25V
ADC0841
Lt.t385
AGND
AGNO
1
TLlH/8557 -11
TLlH/8557 -12
a) Ratiometric
b) Absolute with a Reduced Span
FIGURE 1. Referencing Examples
The full-scale adjustment should be made [with the proper
Y,N (-) voltage applied] by forcing a voltage to the V,N( +)
input which is given by:
V
IN
(+)fsadl'=V
VMIN=the low end (the offset zero) of the analog range.
(Both are ground referenced.)
The VREF (or Vecl voltage is then adjusted to provide a
code change from FEHEX to FFHEX. This completes the adjustment procedure.
-1.5 [(VMAX-VMIN)]
MAX
256
For an example see the Zero-Shift and Span Adjust circuit
below.
where VMAX=the high end of the analog input range and
Zero-Shift and Span Adjust (2V,;;V,N';;SV)
vcc
(5 vocl
Vcct--Q----------.
+
Uk
ADCOB41
SETS ZERO
CODE VOLTAGE
(lVI
330
Ik
Z.lk
Hoc
ZERO AOJ
TL/H/8557-13
3-165
~
"0'
CD
CI
g
r-----------------------------------------------------------------------------------------------,
Applications Information
(Continued)
Span Adjust OV:5:VIN:5:3V
CI:
Vee
15Voe)
vee
V'NI+)
+
V,N
1"0"
ADCD841
V'NI-)
VRE'
":'
TUH/8557-14
Protecting the Input
High Accuracy Comparator
Vcc
5V
(5Voc)
Vee
ADCD841
TLlH/8557-18
DO~a1l1s
TL/H/8557-15
DO~all
nV,N(+»V,N(-)
Os if VIN(+)S5% of vee
3-166
Ik
0.1 Vee
r'"
FS
ADI
,..
....
TL/H/8557 -17
l>
Applications Information
c
o
o
(Continued)
m
....
"'"
Converting a Thermocouple with Cold-Junction Compensation
lIEF
>-.------------tVIN(+)
Vee
Vcc(+5V)
AOtU841
lk
Vee
2k
910
22k
,
ILM335
..I
'::'
TL/H/8557-18
Continuous Conversion
+5V
10 )'F
TANTALUM
CS
Ro
18
WR
N.C.
INTR
INPUT 0-5V
ADC0841
VREF
DGND
DB2
DB3
V1N(+)
7
V1N(-)
8
AGND
10
OBI
DB4
DB5
DB6
(MSB)DB7
-
1.3K
1.3K
17
16
1.3K
UK
15
14
1.3K
1.3K
13
12
11
1.3K
UK
L.E.D.
XC1017
(8)
3-167
TL/H/8557-19
...._
!
o
r-----------------------------------------------------------------------------~
Applications Information
(Continued)
Q
c(
ADC0841-INS8039 Interface
5V
5V
40
DBD
OBI
DB2
DB3
DB4
INS8039
DB5
DB6
DB7
WR
Rii
PID
Pll
12
18
13
17
14
16
15
15
16
14
17
13
18
12
19
11
8
3
10
2
6
27
5
DBO
OBI
DB2
DB3
DB4
DB5
VIN(+)
+
ADCD841
DB6
DB7
6
Vlk)
7
WR
Rii
Cs
INTR
TUH18557-20
0000
0410
0010
B9FF
0012
0014
0016
0018
B820
89FF
2300
1450
SAMPLE PROGRAM FOR ADC0841-INS8039 INTERFACE
CONVERTING TWO RATIOMETRIC, DIFFERENTIAL SIGNALS
OH
ORG
JMP
BEGIN
;START PROGRAM AT ADDR 10
ORG
10H
;MAIN PROGRAM
R1,#OFFH
;LOAD R1 WITH A UNUSED AD DR
BEGIN:
MOV
;LOCATION
;AlD DATA ADDRESS
RO,#20H
MOV
ORL
P1,#OFFH
;SET PORT 1 OUTPUTS HIGH
;LOAD THE ACC WITH 00
MOV
A,OOH
CALL
CONV
;CALL THE CONVERSION SUBROUTINE
;CONTINUE MAIN PROGRAM
;CONVERSION SUBROUTINE
;ENTRY:ACC-AID MUX DATA
;EXIT: ACC-CONVERTED DATA
0050
0052
0053
0054
0056
0057
0059
005A
99 FE
91
09
3253
81
8901
AO
83
CONV:
LOOP:
ORG
ANL
MOVX
IN
JB1
MOVX
ORL
MOV
RET
50H
P1,#OFEH
@R1,A
A,P1
LOOP
A,@R1
P1,&01H
@RO,A
3-168
;CHIP SELECT THE AID
;START CONVERSION
;INPUT INTR STATE
;IF INTR = 1 GOTO LOOP
;IF INTR = 0 INPUT AID DATA
;CLEAR THE AID CHIP SELECT
;STORE THE AID DATA
;RETURN TO MAIN PROGRAM
Applications Information (Continued)
1/0 Interface to NSC800TM
SV
J1
sv
:+-
SV
VREF
Vee
~
DBO
OBI
DB2
DB3
DB4
DBS
DB6
DB7
VIN (+)
;; ADO
~
~
SV
ADC0841
r--
VIN(-)
~
~
~ AGND
Tl
Bl
T2
B2
T3
B3
T4 DM8131 B4
TS
BS
T6
B6
5TB
I
CS
DGND
OUT
WR
RD
ADI
AD2
AD3
AD4
ADS
AD6
AD7
~ AD12
AD13
ADll
I
I
?
~
AD14
ADIS
101M
... WR
~
RD
1
-L
TLlH/8557-21
SAMPLE PROGRAM FOR ADC0841-NSC800 INTERFACE
0010
NCONV
EQU
16
OOOF
001F
3COO
DEL
CS
ADDTA
EQU
EQU
EQU
15
lFH
003CH
DTA:
START:
DB
LD
LD
LD
LD
OUT I
EX
OSH
C,CS
B,NCONV
HL,DTA
DE,ADDTA
LD
DEC
JP
INI
A,DEL
A
NZ,WAIT
EX
JP
DE,HL
NZ,STCONV
0000'
0001'
0003'
0005'
OOOS'
OOOB'
OOOD'
00
OE1F
0616
210000'
11003C
EDA3
EB
OOOE'
0010'
0011'
0014'
3EOF
3D
C20013'
EDA2
0016'
0017'
EB
C2000E'
STCONV:
WAIT:
DE,HL
;TWICE THE NUMBER OF REQUIRED
;CONVERSIONS
;DELAY 60 J.Lsec CONVERSION
;THE BOARD ADDRESS
;START OF RAM FOR AID
;DATA
; DATA
;START A CONVERSION
;HL= RAM ADDRESS FOR THE
;AlDDATA
;WAIT 60 J.Lsec FOR THE
;CONVERSION TO FINISH
;STORE THE AID'S DATA
;THE REQUIRED CONVERSIONS COMPLETED?
;IF NOT GOTO STCONV
END
Note: A conversion is started, then a 60 p.s wait for the AID to complete a conversion and the data is stored at address ADDTA for the first conversion,
ADDTA + 1 for the second conversion, etc. for a total of B conversions.
3-169
.oo:t
~
u
cc(
,----------------------------------------------------------------------------,
Ordering Information
Teniperature
Range
Total Unadjusted Error
Package
Outline
±Yz LSB
±1 LSB
O·Cto +70·C
ADC0841BCN
ADC0841CCN
-40·Cto +85·C
ADC0841BCJ
ADC0841CCJ
ADC0841BCV
ADC0841CCV
V20A
Molded Chip Carrier
ADC0841BJ
ADC0841CJ
J20A
Cerdip
-55·Cto
+ 125·C
3·170
N20A
Molded Dip
J20A
Cerdip
.----------------------------------------------------------------.~
_
c
o
o
National
Semiconductor
Corporation
CD
~
~
~
ADC08441 ADC0848 8-Bit f..LP Compatible AID Converters
with Multiplexer Options
c
oo
General Description
Features
CD
The ADC0844 and ADC0848 are CMOS B-bit successive
approximation A/D converters with versatile analog input
multiplexers. The 4-channel or B-channel multiplexers can
be software configured for single-ended, differential or
pseudo-differential modes of operation.
• Easy interface to all microprocessors
• Operates ratiometrically or with 5 Voe
voltage reference
• No zero or full-scale adjust required
• 4-channel or B-channel multiplexer with address logic
The differential mode provides low frequency input common
mode rejection and allows offsetting the analog range of the
converter. In addition, the AID's reference can be adjusted
enabling the conversion of reduced analog ranges with 8-bit
resolution.
•
•
•
•
The AI Ds are designed to operate from the control bus of a
wide variety of microprocessors. TRI-STATE® output latches that directly drive the data bus permit the AIDs to be
configured as memory locations or I/O devices to the microprocessor with no interface logic necessary.
Internal clock
OV to 5V input range with single 5V power supply
0.3" standard width 20-pin or 24-pin DIP
28 Pin Molded Chip Carrier Package
Key Specifications
•
•
•
•
•
Resolution
Total Unadjusted Error
Single Supply
low Power
Conversion Time
±Yz lSB and ±
B Bits
1 lSB
5 Voe
15mW
40/-Ls
Block and Connection Diagrams
AGNOll01 VCCI241 OGNOl121
' , - - - WRI221
111
INTRI211
B·OIT
{ 000120I-0071131•
MAOI20I-MA41161
U.R.
'CHI121-CHBI91
AID
• ADC0848 shown in
DIP Package
CH5·CH8 not included
on the ADC0844
TL/H/SOI6-1
Dual·/n·Llne Package
Rli
I
cs
CHI
CH2
~
CH3
AOCOB#
CH~
AGHD
7
VRU
(MSO)DB7
DGND
Dual·ln·Line Package
Molded Chip Carrier Package
~
~
Ul
i
20
Va:
Rli
1
2~
19
ViR
CHI
2
23
10
INTH
CH2
3
22
17
OBO/MAO
CH3
~
21
ViR
iiffii
16
OB1/loiAl
CH~
5
20
D60/loiAO
iiffii
ViR
27
17
0B7
15
OB2/MA2
CH5
6
19
OOl/loiAl
16
DGHO
DB3/101A3
CH6
10
002/101A2
cs
28
I~
15
NC
13
OB4
CH7
17
003/101A3
14
VREF
12
OB5
CHO
9
16
004/loiM
AGHO
VREr
10
15
065
11
14
006
DGNO
12
13
007
TUH/5016-30
10
11 086
' - -_ _ _..... TL/H/5016-2
AOCOO48
Top View
Top View
Va:
"C;-':::=-~
cs
';;;-~IO
!!~~!~I!
DB6
AOC08~B
NC
Va:
Rli
3
CHI
~
5
6
7
B
13
AGNO
12
CHO
9 10 11
TUH/5016-29
Top View
See Ordering Information
3-171
CD
~
co
'0:1'
co
8c
V+) the absolute value of the current at that pin should be
limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four.
Nate 4: Human body model, 100 pF discharged through a 1.5 kn resistor.
Nate 5: Typicals are at 25'C and represent most likely parametric norm.
Nate 6: Tested limits are guaranteed to National's AOQL (Average OutgOing Quality Level).
Note 7: Design limits are guaranteed by not 100% tested. These IimHs are not used to calculate outgOing quality levels.
Nate 8: Total unadjusted error includes offset, full-scale, linearity, and multiplexer error.
3-173
Note 9: For VIN (-) ., VIN (+) the digital output code will be 0000 0000. Two on-chip diodes are lied to each analog Input. which will forward·conduct for analog
input voltages one diode drop below ground or one diode drop greater than Vet; supply. Be careful during testing at low Vet; levels (4.5V), as high level analog
inputs (5V) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near ful~scale. The spec allows 50 mV
forward bias of either diode. This means that as long as the analog VIN does not exceed the supply vottage by more than 50 mV, the output code will be correct. To
achieve an absolute 0 Voe to 5 Voe Input voltage range will therefore require a minimum supply voltage 014.950 Voe over temperature variations, Initial toierance
and loading.
Note 10: 011 channel leakage current is measured after the channel selection.
Note 11: The temperature coefficient is 0.3%I'C.
Typical Performance Characteristics
Logic Input Threshold
Voltage vs Supply Voltage
~
1.'
..
.....
S
25
_55°e STA -S:+12Soc
~
.
..'"'"
1.1
!
20
1.1
iii
15
>
9
co
z
'"
::l
z
1.5
i.
1A
...
2
JVce=5Yue
I I
~ K,Yuc=5V-
US
5.DD
US
Linearity Error vs VREF
60
i
i!
15
j
VcC~5V
w
TA=25"C
(ZERO AND FULL-SCALE- I-ADJUSTED)
0.5
i
\.
z
i!lz
I.
0
40
30
I--
20
j
Ii
;:
1
2
3
4
0
5
4.5
20
e>
10
;z
..
14
i.;o"
30
iii
'"'"
0
-75-50-25 0 25 50 75100 125
TEMPERATURE ("C)
-
""'"
r-
..... 1'
~
....
5
4.75
5.25
SUPl'lY VOLTAGE (V)
5.5
Unadjusted Offset Error vs
VREF Voltage
¥CC=5V
40
z
~
10
Conversion Time vs
Temperature
w
-- r--
TA=25"C
50
'IMF (V)
50
E 0.5
e>
:I
0
r- 1""-1000.
Conversion Time vs VSUPPLY
1.0
.
1
0
-75-50-25 0 25 50 75 100 125
TEMPERATURE ('C)
5.50
Vee -SUPPLY VOLTAGE !Voel
~
..
-
5
Vcc,;,5V
1.5
i
'"
co
'"
~RCtYuc=2.4~
IS+v4=¥t'
1.3
4.50
!
.... .....
~,tJ
10
~
e>
'"
~
~ .....
a
9
Power Supply Current vs
Temperature
Output Current vs
Temperature
",
I'"
111111 VIN:~:~~INI-I~A'
12
i
..
~
IiIii
Ite>
6
rrr-
4
l-
2
r-
10
8
o .....
0
-75-50-25 0 25 50 75 100 125
TEMPERATURE ("C)
0.01
~
,
VOS=2mV
TA=26"C
-
r-
-
0.1
!!!
1.0
5
YJiEF (V)
TLlH/5016-3
3·174
r--------------------------------------------------------------------,~
C
g
TRI-STATE Test Circuits and Waveforms
CD
".
~
VCC
~
c
g
CD
".
CD
10k
DATA : : :
TUHIS01S-4
~~IH
~
OUTPUTS
GND - - - - - - - - - - "
TLIH/S01S-S
1,= 20 no
toH. CL = 10 pF
tOH
VCC
VCC
GND
OH
VCC
DATA
OUTPUTS
~
--10%
VOL
TL/H/501S-7
1,= 20 no
TL/HI501S-S
Leakage Current Test Circuit
5V
ADC0848
r"'----.....-t
CHANNEL
VOL1lIGE
SELECT
CH2 (ON/OFF)
CH3 (ON/OFF)
CH4 (ON /OFf)
CH5 (ON/OFF)"
CH6 (ON/OFF)"
CH7 (ON/OFF)"
CHB (ON/OFF)"
"NDT INCWOEO ON AOC0844
3-175
TLIHIS01S-B
co
•oco
g
r---------------------------------------------------------------------------------,
Timing Diagrams
Programming New Channel Configuration and Starting a Conversion
~
------,-------;-
•~
g
,-,
cC
iiii
~----------tC:----------~
080-087 _ _ _ _ _ _
MAO·MM
TLlH/5016-9
Note 1: Read strobe must occur at teast 600 ns after the assertion of interrupt to guarantee reset of tNTR.
Note 2: MA stands for MUX address.
Using the Previously Selected Channel Configuration and Starting a Conversion
CS\__....JI
iiii
,
f
_ _--.J
1_-++-_Ic_={__....J1
------------{
OBO-OB7
READING THE RESULT
OF THE LAST
CONVERSION
3-176
~TL/H/5016-10
l>
CII1
CH2
CH3
CH4
C
"
J
~
j(
__ ~c
1D
CI)
~
CI)
lADDER AND DECODER
DAC
....c"
oc
D~ __
~
~~:
START
ClK ~r+
F/F
."
~
C
:::J
Sl
0'
:::J
!!.
CH5
CH6
SIGN
SELECT
~ +(-)
":
J(iI\.
CH7
~X
CHB
l.-
+(-)
f(
-
l
G
~
~I-
+
SAR lATCH
~
/
~
MUX
DECODER
TRI-STATE-'
OUTPUT LATCHES
0'
n
~
C
S'
~
eQ
ONE SHOT
3
iii
xm
rn
~
MUX
ADDRESS
LATCH
m
9-BIT
SHIFT REGISTER
/~
AGND
-.J
-.J
4
-I
"I" = OUTPUT
ENABLE
r6DDns
DELAY
INTH
MAD
MAl
MA2
MA3
MA4
,LSB
MBB,
DIGITAL OUTPUTS
~
\.
C--
~
TUH/5016-11
m
8178000\#/17178000\#
Functional Description
The ADC0844 and ADC0848 contain a 4-channel and 8channel analog input multiplexer (MUX) respectively. Each
MUX can be configured into one of three modes of operation differential, pseudo-differential, and single ended.
These modes are discussed in the Applications Information
Section. The specific mode is selected by loading the MUX
address latch with the proper address (see Table I and Table II). Inputs to the MUX address latch (MAO-MA4) are
common with data bus lines (DBO-DB4) and are enabled
when the RD line is high. A conversion is initiated via the CS
and WR lines. If the data from a previous conversion is not
read, the INTR line will be low. The falling edge of WR will
reset the INTR line high and ready the AID for a conversion
cycle. The riSing edge of WR, with RD high, strobes the data
on the MAO/DBO-MA4/DB4 inputs into the MUX address
latch to select a new input configuration and start a conversion. If the RD line is held low during the entire low period of
WR the previous MUX configuration is retained, and the
data of the previous conversion is the output on lines DBODB7. After the conversion cycle (te ,;; 40 ,...s), which is set
by the internal clock frequency, the digital data is trans-
ferred to the output latch and the INTR is asserted low.
Taking CS and RD low resets INTR output high and outputs
the conversion result on the data lines (DBO-DB7).
Applications Information
1.0 MULTIPLEXER CONFIGURATION
The design of these converters utilizes a sampled-data
comparator structure which allows a differential analog input
to be converted by a successive approximation routine.
The actual voltage converted is always the difference between an assigned" +" input terminal and a "-" input terminal. The polarity of each input terminal of the pair being
converted indicates which line the converter expects to be
the most positive. If the assigned" +" input is less than the
" -" input the converter responds with an all zeros output
code.
A unique input multiplexing scheme has been utilized to provide multiple analog channels. The input channels can be
software configured into three modes: differential, single-
TABLE I. ADC0844 MUX ADDRESSING
MUXAddress
CS
WR
MA3
MA2
MA1
MAO
X
X
X
X
L
L
L
L
L
L
H
H
L
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
L
L
L
L
H
H
H
H
H
H
L
L
H
L
H
L
L
L
L
U
X
X
X
X
L
U
Channel #
RD
CH1
U
U
H
H
H
H
+
H
H
H
H
+
H
H
H
+
-
CH2
CH3
CH4
AGND
-
+
Differential
-
+
-
+
-
+
-
+
-
PseudoDifferential
-
+
-
+
Single-Ended
-
+
L
MUX
Mode
Previous Channel Configuration
x = don't care
4 Single-Ended
CH1CHZCH3CH4-
r
2 Differential
(+)
(+)
(+)
(+)
CHI. CHZ {
ADCD844
=
=
+(-)
-(+)
ADC0844
+(-)
CH3,CH4{
AGND(-)
-(+)
TUH/5016-12
TL/H/5016-13
3 Pseudo-Differential
CH1- (+)
CHZ- (+)
CH3- (+)
Combined
CH1,CHZ {_
_
-+
CH3CH4-
ADC0844
r
CH4- 1-1
TL/H/5016-14
+
+
ADC0844
AGND(-)
TL/H/5016-15
FIGURE 1. Analog Input Multiplexer Options
3-178
r--------------------------------------------------------------------.~
C
Applications Information
(Continued)
ended, or pseudo-differential. Figure 1 shows the three
modes using the 4-channel MUX ADC0844. The eight inputs
of the ADC0848 can also be configured in any of the three
modes. In the differential mode, the ADC0844 channel inputs are grouped in pairs, CHI with CH2 and CH3 with CH4.
The polarity assignment of each channel in the pair is interchangeable. The single-ended mode has CH1-CH4 assigned as the positive input with the negative input being the
analog ground (AGND) of the device. Finally, in the pseudodifferential mode CH1-CH3 are positive inputs referenced
to CH4 which is now a pseudo-ground. This pseudo-ground
input can be set to any potential within the input commonmode range of the converter. The analog signal conditioning
required in transducer-based data acquisition systems is
significantly simplified with this type of input flexibility. One
converter package can now handle ground referenced inputs and true differential inputs as well as signals with some
arbitrary reference voltage.
divider string used for the successive approximation conversion.
In a ratio metric system (Figure 2a), the analog input voltage
is proportional to the voltage used for the AID reference.
This voltage is typically the system power supply, so the
VREF pin can be tied to Vee. This technique relaxes the
stability requirements of the system reference as the analog
input and AID reference move together maintaining the
same output code for a given input condition.
For absolute accuracy (Figure 2b), where the analog input
varies between very specific voltage limits, the reference pin
can be biased with a time and temperature stable voltage
source. The LM385 and LM336 reference diodes are good
low current devices to use with these converters.
The maximum value of the reference is limited to the Vee
supply voltage. The minimum value, however, can be quite
small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing less than a
5V output span. Particular care must be taken with regard to
noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 LSB equals
VREF/256).
The analog input voltages for each channel can range from
50 mV below ground to 50 mV above Vee (typically 5V)
without degrading conversion accuracy.
2.0 REFERENCE CONSIDERATIONS
The voltage applied to the reference input of these converters defines the voltage span of the analog input (the difference between VIN(MAX) and VIN(MIN» over which the 256
possible output codes apply. The devices can be used in
either ratiometric applications or in systems requiring absolute accuracy. The reference pin must be connected to a
voltage source capable of driving the minimum reference
input resistance of 1.1 kil. This pin is the top of a resistor
3.0 THE ANALOG INPUTS
3.1 Analog Differential Voltage Inputs and CommonMode Rejection
The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
to both selected .. +" and" -" inputs for a conversion (60
Hz is most typical). The time interval between sampling the
TABLE II. ADC0848 MUX Addressing
MUX Address
--"--""T"""--r---.---l CS
MA4
MA3
MA2
MA1
MAO
x
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
H
U
H
H
L
H
H
X
X
X
X
X
Differential
+
+
+
+
+
+
H
H
U
+
+
H
Single-Ended
+
H
H
+
+
+
H
U
H
L
H
U
+
+
+
PseudoDifferential
+
H
H
L
L
+
H
L
L
L
L
+
H
H
H
L
+
H
H
H
MUX
Mode
+
H
L
L
L
H
H
L
L
H
H
L
L
L
L
H
H
Channel
RD t---,.--,.--,.--,--,---r---r---r-----I
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 AGND
L
H
L
H
L
H
L
H
H
H
H
H
H
H
L
L
H
L
L
H
L
H
L
H
L
H
H
H
L
L
L
L
H
H
H
L
L
L
L
L
L
L
L
WR
+
+
+
L
Previous Channel Configuration
3-179
oo
CD
~
~
;;
c
oo
CD
~
CD
Applications Information
(Continued)
.. +" input and then the" -" inputs is % of a clock period.
4.0 OPTIONAL ADJUSTMENTS
The change in the common-mode voltage during this short
time interval can cause conversion errors. For a sinusoidal
common-mode signal this error is:
VERROR(MAX)=Vpeak (2'IT fOM)xO.5X
4.1 Zero Error
The zero of the AID does not require adjustment. If the
minimum analog input voltage value, VIN(MIN), is not ground,
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biasing any VIN (-) input at this VIN(MIN) value. This is
useful for either differential or pseudo-differential modes of
input channel configuration.
(~)
where fOM is the frequency of the common-mode signal,
Vpeak is its peak voltage value and to is the conversion time.
For a 60 Hz common-mode signal to generate a % LSB
error (== 5 mV) with the converter running at 40 ,...S, its peak
value would have to be 5.43V. This large a common-mode
signal Is much greater than that generally found in a well
designed data acquisition system.
The zero error of the AID converter relates to the location
of the first riser of the transfer function and can be measured by grounding the V- input and applying a small magnitude positive voltage to the V+ input. Zero error is the
difference between actual DC input voltage which is necessary to just cause an output digital code transition from 0000
0000 to 0000 0001 and the ideal % LSB value (% LSB= 9.8
mV for VREF=5.000 Vocl.
3.2 Input Current
Due to the sampling nature of the analog inputs, short duration spikes of current enter the" +" input and exit the" -"
input at the clock edges during the actual conversion. These
currents decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period. Bypass capacitors at the inputs will average these currents
and cause an effective DC current to flow through the output resistance of the analog signal source. Bypass capacitors should not be used if the source resistance is greater
than 1 kO.
4.2 Full-Scale
The full-scale adjustment can be made by applying a differential input voltage which is 1 % LSB down from the desired
analog full-scale voltage range and then adjusting the magnitude of the VREF input for a digital output code changing
from 11111110 to 1111 1111.
4.3 Adjusting for an· Arbitrary Analog Input Voltage
Range
If the analog zero voltage of the AID is shifted away from
ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference
should be properly adjusted first. A VIN (+) voltage which
equals this desired zero reference plus % LSB (where the
LSB is calculated for the desired analog span, 1 LSB =
analog span/256) is applied to selected "+ .. input and the
zero reference voltage at the corresponding "-" input
should then be adjusted to just obtain the OOHEX to 01 HEX
code transition.
3.3 Input Source Resistance
The limitation of the Input source resistance due to the DC
leakage currents of the input multiplexer is important. A
worst-case leakage current of ± 1 ,...A over temperature will
create a 1 mV input error with a 1 kO source resistance. An
op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance
Signal source be required.
5.
5V
.1
.1
y
1
Vcc
CH1(+)
CH2(+)
CH3(+)
CH.(+)
rh
vmU
ov~rf'WI.
1.
25.
CH5(+1 ADCOB48
E+-
f+:
vce
CII1I+)
CH2(+)
CH3(+)
~[Jx3'
.25' ov~"]:.~:...
U'Y
CHI(+)
CH7(+)
CH8(+)
ovun
L X5
ov~
1x'r
.... v DY~~xn:1::'"
~'-Ii
UBV OY-
~D
U5Y
1
,
r-1.
.JK
YREF
CH.,+) ADCD848
CH5(+)
CH5( +)
CH7,+)
. .,
25Y
~~ LM385
(-)ABND .
.L
...1..
TL/H/5016-16
TL/H/5016-17
a) Ratlometrlc
b) Absolute with a Reduced Span
FIGURE 2. Referencing Examples
3-180
Applications Information (Continued)
The full-scale adjustment should be made [with the proper
VIN (-) voltage applied) by forcing a voltage to the VIN (+)
input which is given by:
VMIN=the low end (the offset zero) of the analog range.
(Both are ground referenced.)
The VREF (or Vccl voltage is then adjusted to provide a
code change from FEHEX to FFHEX. This completes the acjjustment procedure.
For an example see the Zero-Shift and Span Adjust circuit
below.
.
[(VMAX-VMIN)]
VIN(+)fsadJ=VMAX -1.5
256
where VMAX=the high end of the analog input range and
Zero-Shift and Span Adjust (2V:5:VIN:5:5V)
Vcc
(5Vocl
...---<>--IVIN(+I
vcct--4----------,
SETS ZERO
CODE VOLTAGE
(2V)
Ik
Z.lk
2Voc
ZERO AOJ
TL/H/5016-18
3-181
Applications Information
(Continued)
Differential Voltage Input 9-Blt AID
r------------------4...----1 VINI.)
Vee 1-.....- - - - - - - ,
+
1'1DPF
2k
ADC0848
Ik
VREF
1-"'*-<
LM336·2.5
TUH/5016-20
High Accuracy Comparators
Protecting the Input
5V
Vee
(5 Voe)
SYSTEM
TEST
POINTS
TUH/5016-21
Diodes are 1N914
TL/H/5016-22
DO~allls
DO~all
3-182
if VIN(+»VIN(-)
Os if VIN(+)
Applications Information
c
o
Q
(Continued)
CO
""""
i;
Operating with Automotive Ratlometric Transducers
vee
(SVDel
C
o
Q
CO
""
CO
ADeOB44
3k
tOk
tk
""'l:l-.....,.... ~~J
14k
TL/H/5016-23
·VIN(-)=O.15 Vee
15% of VCC,;VXDR,;85% of Vee
Converting 3 Thermocouples with only One Cold·Junction Compensator
TREF
+ ~T.;..;Y.;..;PE;;..;J~-C)--I-_ _ _-.
Tt
> .....- - - - - - - - - - - - t C H 1
Vee
r------------~CH2
r - - - - - - - - - - - - . ; CH3
1k
Vee
2k
ADCD844
91D
22k
,
r
ILM335
I
L
oJ
TREf
":"
TLlH/5016-24
Uses the pseudo-differential mode to keep the differential inputs constant with changes in reference temperature (TREF).
3·183
m
~
m
o
o
r---------------------------------------------------------------------------------~
Applications Information
(Continued)
C
A Stand Alone Circuit
--:
~
r~
CH6
OB7
DB6
DB5
MA4/0B4
D.U.T.
MA3/0B3
CH7
CH8
MA2/0B2
AGNO
MAI/DBI
MAO/OBO
OGNO
(9113
(11114
4
(12115
7
(13116
8
(14117
13
(15118
14
(16119
17
(17120
18
iiii !MTR
fSWii
(191
U ( 2231 22
to
OUT
3 DIS
DI
VREF
Uk
Vee
01
DZ
02
D3
03
04
04
MM74C374
D5
05
06
06
07
Q7
DB
DB
NSL50Z7
(8 PLI
5
.~I:..J
6
":..J
9
.:.:
12
....:.:
tl
.
(8 PLI
Z
"(\I
"['.I
IS
~I
"~I
16
19
.. rJ7
116
A
1/6
(11~C14
1
21
~
11
~
5V
"7
11 9 7 5 3
25k
~,I '~.
1/6
MM74C14 .....
5.1k
5.1k
5.1k
5.1k
05 04 03 02 01
r
T200PF
5.1k
0lS2
INS
IN4
12
M~
0-
10
MA':""
6
M~
-0-
0-
MM80C95
IN3
rJ 7
1
DlS1
IN2
IN1
MA2..,.
4
0-
MA~
0-
2
1'.7
TL/H/SOI6-2S
Note: OUT pin numbers in parentheses are for ADC0844. others are for ADC0848.
Start a Conversion without Updating the Channel Configuration
~>---------------~~
WiI)-------r""'\
ADCDa48
TL/H/SOI6-26
CS:.WR will update the channel configuration and start a conversion.
cs-R5 will read the conversion data and start a new conversion without updating the channel configuration.
Waiting for the end of this conversion is not necessary. A CS-WR can immediately follow the CSoAD.
3-184
l>
Applications Information
C
oC)
(Continued)
CO
""""
.....
ADC0844-INS8039 Interface
5V
l>
5V
C
o
40
Vee
CO
""
Vee
OBO
OBI
DB2
DB3
DB4
INSB039
C)
20
DB5
DB6
DB7
Wii
iiii
12
.13
17
16.
14
15
15
14
16
13
17
12
lB
11
19
10
27
OBI/MAl
DB2/MA2
DB3/MA3
DB4
DB5
ADCOB44
DB6
DB7
19
PIO
Pll
CO
OBO/MAO
lB
Wii
iiii
cs
iiffii
TLiH/5016-27
0000
0410
0010
B9FF
0012
0014
0016
B820
89FF
2300
0018
001A
1450
2302
001C
0010
18
1450
SAMPLE PROGRAM FOR ADC0844-INS8039 INTERFACE
CONVERTING TWO RATIOMETRIC, DIFFERENTIAL SIGNALS
ORG
OH
JMP
BEGIN
;START PROGRAM AT ADDR 10
ORG
;MAIN PROGRAM
10H
R1,#OFFH
BEGIN:
MOV
;LOAD R1 WITH A UNUSED ADDR
;LOCATION
;AlD DATA ADDRESS
RO,#20H
MOV
ORL
P1,#OFFH
;SET PORT 1 OUTPUTS HIGH
A,OOH
;LOAD THE ACC WITH AID MUX DATA
MOV
;CH1 AND CH2 DIFFERENTIAL
;CALL THE CONVERSION SUBROUTINE
CALL
CONV
MOV
A,#02H
;LOAD THE ACC WITH AID MUX DATA
;CH3 AND CH4 DIFFERENTIAL
INC
RO
;INCREMENTTHE AID DATA ADDRESS
;CALL THE CONVERSION SUBROUTINE
CALL
CONV
;CONTINUE MAIN PROGRAM
;CONVERSION SUBROUTINE
;ENTRY:ACC-AID MUX DATA
;EXIT: ACC-CONVERTED DATA
0050
0052
0053
0054
0056
0057
0059
005A
99 FE
91
09
3253
81
8901
AO
83
CONV:
LOOP:
ORG
ANL
MOVX
IN
JB1
MOVX
ORL
MOV
RET
SOH
P1,#OFEH
@R1,A
A,P1
LOOP
A,@R1
P1,&01H
@RO,A
3-185
;CHIP SELECT THE AID
;LOAD AID MUX & START CONVERSION
;INPUT INTR STATE
;IF INTR = 1 GOTO LOOP
;IF INTR = 0 INPUT AID DATA
;CLEAR THE AID CHIP SELECT
;STORE THE AID DATA
;RETURN TO MAIN PROGRAM
co .---------------------------------------------------------------------------------,
00:1'
co
Applications Information (Continued)
8....cc
1/0 Interface to NSC800
00:1'
00:1'
VREF
5V
5V
8
ADCD848
~
AD/D8D
::Jfg:~
Q
cc
CHII +)
~--ofCH21+) MA3/DB3
~ADD
:~
AD3
T-~~~~::::::::J CH31+)
CH41 +)
~g:
MA4/g:
OB6
...----ICH51+)
DB7
r---ofCH6.1+)
CH71+)
AD6
AD7
A011
AD12
AD13
AD14
AD15
101M
TLlH/5016-26
SAMPLE PROGRAM FOR ADC0848-NSC800 INTERFACE
0008
OOOF
001F
3COO
0000'
0004'
0008'
OOOA'
OOOC'
OOOF'
0012'
08 09 OA OB
OCODOEOF
OE 1F
0616
210000'
11003C
EDA3
0014'
EB
0015'
0017'
0018'
001B'
3EOF
3D
C20013'
EDA2
0010'
001E'
EB
C2000E'
NCONV
DEL
CS
ADDTA
Eau
Eau
Eau
Eau
16
15
1FH
003CH
MUXDTA:
DB
DB
LD
LD
LD
LD
OUTI
08H,09H,OAH,OBH
OCH,ODH,OEH,OFH
C,CS
B,NCONV
HL,MUXDTA
DE,ADDTA
EX
DE,HL
LD
DEC
JP
INI
A,DEL
A
NZ,WAIT
EX
JP
DE,HL
NZ,STCONV
START:
STCONV:
WAIT:
;DELAY 50 ,...sec CONVERSION
;THE BOARD ADDRESS
;START OF RAM FOR AID
;DATA
;MUXDATA
;LOAD AID'S MUX DATA
;AND START A CONVERSION
;HL= RAM ADDRESS FOR THE
;AlDDATA
;WAIT 50 ,...sec FOR THE
;CONVERSION TO FINISH
;STORE THE AID'S DATA
;CONVERTED ALL INPUTS?
;IF NOT GOTO STCONV
END
Note: This rouline sequentially programs Ihe MUX dalalalch in Ihe signai.ended mode. For CHI·CHB a conversion is slarted, Ihen a 50 pos wail for Ihe AID 10
complele a conversion and the dalais slored al address ADDTA for CHI, ADDTA + I for CH2, elc.
3·186
»
c
oo
Ordering Information
Temperature
Range
Total Unadjusted Error
±% LSB
±1 LSB
ADC0844BCN
ADC0844CCN
O'Cto +70'C
ADC0848BCN
ADC0848CCN
ADC0844BCJ
ADC0844CCJ
-40'Cto +85'C
ADC0848BCJ
ADC0848CCJ
ADC0848BCV
ADC0848CCV
ADC0844BJ
ADC0844CJ
- 55'C to + 125'C
ADC0848BJ
ADC0848CJ
3-187
MUX
Channels
Package
Outline
4
N20A
Molded Dip
8
N24C
Molded Dip
4
J20A
Cerdip
8
J24F
Cerdip
8
V28A
Molded Chip Carrier
4
J20A
Cerdip
8
J24F
Cerdip
00
.1:10
.1:10
»
c
oo
00
.1:10
00
~
II)
CD
CI
I
,----------------------------------------------------------------------------,
~ Semiconductor
NatiOnal
Corporation
CD
g ADC08521 ADC0854
CI
011(
Multiplexed Comparator with 8-Bit Reference Divider
General Description
The ADCOB52 and ADCOB54 are CMOS devices that combine a versatile analog input multiplexer, voltage comparator, and an B-blt DAC which provides the comparator's
threshold voltage (VTH). The comparator provides a "I-bit"
output as a result of a comparison between the analog Input
and the DAC's output. This allows for easy implementation
of set-point, on-off or "bang-bang" control systems with
several advantages over previous devices.
once each clock cycle up to a maximum clock rate of
400 kHz.
Features
•
•
•
•
•
•
The ADCOB54 has a 4 input multiplexer that can be software
configured for single ended, pseudo-differential, and full-differential modes of operation. In addition the DAC's reference input is brought out to allow for reduction of the span.
The ADCOB52 has a two input multiplexer that can be configured as 2 single-ended or 1 differential input pair. The
DAC reference input is internally tied to Vee.
The multiplexer and B-bit DAC are programmed via a serial
data input word. Once programmed the output is updated
2 or 4 channel multiplexer
Differential or Single-ended input, software controlled
Serial digital data interface
256 programmable reference voltage levels
Continuous comparison aiter programming
Fixed, ratiometric, or reduced span reference capability
(ADC OB54)
Key Specifications
• Accuracy, ± Yz LSB or ± 1 LSB of Reference (0.2%)
• Single 5V power supply
• Low Power, 15 mW
ClK
yREF----I
AGNO
>-----00
------I
-v·
01--...- -.......
-Vee
e8-
-OGNO
CHO
CHI
CH2
CH3
COM
TL/H/5521-1
FIGURE 1. ADC0854 Simplified Block Diagram (ADC0852 has 2 Input channels.
COM tied to GND. VREF tied to Vee. V + omitted. and one GND connection)
2 Channel and 4 Channel Pin Out
ADC0852 2-CHANNEL MUX
Dual-In-Llne Package
cs
ADC0854 4-CHANNEL MUX
Dual-In-Llne Package
cs
Vee (VREF)
CHO
CHI
3
GNO (COU)
4
AOC0852
ClK
CHO
2
6
DO
CHI
3
5
01
CH2
4
TlIH/5521-10
Top View
CH3
5
COM
6
DGNO
7
AOC0854
14
Vee
13
y+
12
01
11
ClK
10
DO
8
VREF
AGNO
AGND and COM Internally connected to GND
VREF Internally connected to Vee
TL/H/5521-11
Top View
Order Number ADC0852
See NS Package Number J08A or N08E
Order Number ADC0854
See NS Package Number J14A or N14A
3-1BB
~
Absolute Maximum Ratings (Notes 1 and 2)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Officel
Distributors for availability and specifications.
Current into V+ (Note 3)
15mA
Supply Voltage, Vee (Note 3)
Voltage
Logic and Analog Inputs
Input Current per Pin
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
ESD Susceptibility (Note 14)
6.5V
CD
260'C
300'C
2000V
Operating Conditions
Supply Voltage, Vee
Temperature Range
ADC0854BJ, ADC0854CJ
-0.3VtoVee +0.3V
±5mA
±20mA
Input Current per Package
Storage Temperature
Package Dissipation
at T A = 25'C (Board Mount)
oo
0.8W
TMIN S; TA S; TMAX
-55'C S; TA S; 125'C
-40'C :5: T A :5: 85'C
O'C:5: TA:5: 70'C
Electrical Characteristics The following specifications apply for Vee
VREF :5: Vee + 0.1V, fCLK
= TJ = 25'C.
=
= v+ = 5V (no v+ on ADC0852),
250 kHz unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA
ADC0852BCJ/CCJ/BJ/CJ
ADC0854BCJ/CCJ/BJ/CJ
Conditions
Parameter
Typ
(Note 4)
Tested
Limit
(Note 5)
ADC0852BCN/CCN
ADC0854BCN/CCN
Design
Typ
Limit
(Note 4)
(Note 6)
Tested
Limit
(Note 5)
Design
Limit
(Note 6)
Units
±%
±%
±1
±1
LSB
LSB
LSB
LSB
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Total Unadjusted
Error (Note 7)
ADC0852/4/BCN
ADC0852/4/BJ/BCJ
ADC0852/4/CCN
ADC0852/4/CJ/CCJ
VREF Forced to
5.000VDe
±%
±1
Comparator Offset
ADC0852/4/BCN
ADC0852/4/BJ/BCJ
ADC0852/4/CCN
ADC0852/4/CCJ
2.5
2.5
2.5
2.5
20
2.5
2.5
2.5
2.5
Minimum Total Ladder
Resistance
3.5
1.3
3.5
1.3
1.3
kO
3.5
5.9
3.5
5.4
5.9
kO
GND-0.05
GND-0.05
V
Maximum Total Ladder
Resistance
Minimum Common-Mode
Input (Note 8)
All MUX Inputs
and COM Input
Maximum Common-Mode
Input (Note 8)
All MUX Inputs
and COM Input
GND-0.05
Vee + 0.05
DC Common-Mode Error
=
Power Supply Sensitivity
Vee
Vz, Internal
diode
breakdown
at V+ (Note 3)
15 mA into V+
10
5V ±5%
± 'j,.
±%
±'j,.
±%
6.3
MIN
MAX
IOFF' Off Channel Leakage On Channel
Current (Note 9)
Off Channel
On Channel
Off Channel
=
=
=
=
10
20
Vee + 0.05 Vee + 0.05
±V,.
±V,.
V
±%
LSB
±%
±%
LSB
6.3
8.5
5V,
OV
-1
-200
-200
OV,
5V
+1
+200
+200
3-189
mV
mV
mV
mV
±%
8.5
)0
C
oo
CD
4.5Voe to 6.3Voe
ADC0852BJ, ADC0852CJ
ADC0854BCJ, ADC0854CCJ
ADC0852BCJ, ADC0852CCJ
ADC0854BCN, ADC0854CCN
ADC0852BCN, ADC0852CCN
- 65'C to + 150'C
UI
~
V
V
-1
",A
nA
+1
",A
nA
UI
,a:o.
Electrical Characteristics (Continued)
The following specifications apply for Vcc = V+ = 5V (no V+ on ADC0852), fClK
Boldface limits apply from TMIN to TMAX; all other limits TA = TJ = 25°C.
ADC0852BCJ/CCJ/BJ/CJ
ADC0854BCJ/CCJ/BJ/CJ
Parameter
Conditions
Typ
(Note 4)
Tested
Limit
(Note 5)
Design
Limit
(Note 6)
= 250 kHz unless otherwise specified.
ADC0852BCN/CCN
ADC0854BCN/CCN
Typ
(Note 4)
Tested
Limit
(Note 5)
Design
Limit
(Note 6)
Units
+1
",A
nA
-1
",A
nA
CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued)
ION, On Channel Leakage
Current (Note 9)
= 5V,
= OV
On Channel = OV,
Off Channel = 5V
On Channel
Off Channel
+1
+200
+200
-1
-200
-200
DIGITAL AND DC CHARACTERISTICS
VIN(l), Logical "1" Input
Voltage
Vee
= 5.25V
2.0
2.0
2.0
V
VIN(O), Logical "0" Input
Voltage
VCC
= 4.75V
0.8
0.8
0.8
V
IIN(l), Logical "1" Input
Current
VIN
= VCC
0.005
1
0.005
1
1
",A
IIN(O), Logical "0" Input
Current
VIN
= OV
-0.005
-1
-0.005
-1
-1
",A
VOUT(l), Logical "1" Output
Voltage
Vcc = 4.75V
lOUT = - 360 ",A
lOUT = -10 ",A
2.4
4.5
2.4
4.5
2.4
4.5
V
V
VOUT(O), Logical "0" Output
Voltage
lOUT = 1.6 mA,
Vcc = 4.75V
0.4
0.4
0.4
V
lOUT, TRI·STATE® Output
Current (DO)
CS = Logical "1"
VOUT = 0.4V
VOUT = 5V
-0.1
0.1
-3
3
-0.1
0.1
-3
3
-3
3
",A
",A
ISOURCE
VOUT Short to GND
-14
-6.5
-14
-7.5
-6.5
mA
ISINK
VOUT Short to Vee
16
8.0
16
9.0
8.0
mA
Icc Supply Current
ADC0852
Includes DAC
Ladder Current
2.7
8.5
2.7
6.5
8.5
rnA
Icc Supply Current
ADC0854 (Note 3)
Does not Include DAC
Ladder Current
0.9
2.5
0.9
2.5
2.5
mA
3·190
l>
AC Characteristics tr =
c
oo
tf = 20 ns, T A = 25'C
01)
Symbol
fClK
Parameter
Conditions
Clock Frequency
MIN
(Note 12)
MAX
Typ
(Note 4)
Tested
Design
limit
Limit
(Note 5)
(Note 6)
U1
Units
......
kHz
o
o
l>
c
10
CL = 100pF
tD1
Rising Edge of Clock
650
tr
Comparator Response
Not Including
Time (Note 13)
Addressing Time
400
kHz
CO
1000
ns
"'"
to "DO" Enabled
tSET-UP
2
+
1
/Ls
1lfCLK
%
%
Clock Duty Cycle
MIN
40
(Note 10)
MAX
60
CS Falling Edge or
MAX
250
ns
MIN
90
ns
1000
ns
250
ns
500
ns
Data Input Valid to
ClK Rising Edge
tHOLD
Data Input Valid after
ClK Rising Edge
t pd1, tpdo
ClK Falling Edge to
MAX
CL = 100pF
650
MAX
CL = 10 pF, Rl = 10k
125
Output Data Valid
(Note 11)
t1H,IoH
Rising Edge of CS to
Data Output Hi-Z
CL = 100 pF, RL = 2k
500
(see TRI-STATE Test Circuits)
CIN
Capacitance of logic
5
pF
5
pF
Input
COUT
Capacitance of logic
Outputs
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when
operating the device beyond ils specified operating conditions.
Note 2: AI' voltages are measured with respect to ground.
Note 3: Inlernal zener diodes (approx. 7V) are connected from V + 10 GND and Vee 10 GND. The zener al V + can operate as a shunl regulator and is connecled
to Vee via a convenlional diode. Since Ihe zener vollage equals Ihe A/D's breakdown vollage, the diode ensures thai Vee will be below breakdown when Ihe
device is powered trom V +. Functionality is therefore guaranteed for V + operation even though the resultant voltage at Vee may exceed the specified Absolute
Max of 6.5V. II is recommended that a resistor be used 10 limilthe max current inlo V +.
Note 4: Typicals are at 25C>C and represent most likely parametric norm.
Note 5: Tested and guaranleed to Nalional AOQl (Average Oulgoing Quality level).
Note 6: Guaranleed, bul noll 00% production lesled. These limils are nol used 10 calculale oulgoing quality levels.
Note 7: Tolal unadiusted error includes comparator offsel, DAC linearity, and multiplexer error. It is expressed In lSBs of Ihe Ihreshold DAC's inpul code.
Note 8: For V,N( -);" V,N( +) Ihe oulpul will be O. Two on-chip diodes are lied 10 each analog inpul (see Block Diagram) which will forward conduct for analog inpul
voltages one diode drop below ground or one diode drop grealer Ihan Ihe Vee supply. Be careful, duringlesting allow Vee levels (4.5V), as high level analog inputs
(5V) can cause this inpul diode 10 conduct-especially al elevaled lemperalures, and cause errors for analog inpuls near full-scale. The spec allows 50 mV forward
bias of eilher diode. This means thai as long as Ihe analog VIN or VREF does nol exceed Ihe supply vollage by more Ihan 50 mV, the output code will be correc\. To
achieve an absolute 0 Voe to 5 Vee input voltage range will therefore require a minimum supply voltage of 4.950 Vee over temperature variations, initial tolerance
and loading.
Note 9: leakage current is measured with the clock not switching.
Note 10: A 40% 10 60% clock duty cycle range ensures proper operalion al ail clock frequencies. In Ihe case that an available clock has a duty cycle oulside of
Ihese limils Ihen 1.6 "S "ClK low" 60 "S and 1.6 "S "ClK HIGH" "".
Note 11: With CS low and programming complete, DO is updaled on each falling ClK edge. However, each new oulpul is based on Ihe comparison compleled 0.5
clock cycles prior (see Figure 5).
Note 12: Error specs are nolguaranleed al400 kHz (see graph: Comparalor Error vs. felK).
Note 13: See lext, section 1.2.
Note 14: Human body model, 100 pF discharged Ihrough a 1.5 kfl resislor.
3-191
I\)
U1
Typical Performance Characteristics
Internal DAC Linearity
Error vs VREF Voltage
1.5
..
0.50
Internal DAC Linearity
Error vs Temperature
1.25
ICLK ~ 250 kHz
'"
iii
~
TA~25"C
~ 1.0
0
'"
'"
'"
~
0
'" 0.75
III
>-
i
Ii!
0.5
~
z
::;
"
z
::; 0.25
25
C
20
....
~
15
So
'"
13
....
~
5
1
2
3
VREF (VDC)
4
1:1:
3
..
0
'"
I<
2
...
1
i:E
-
ISINK VDc=O.4V
0
-100 -50
0
50
100
TEMPERATURE I"C)
iti
4
0
VDC~
0
0-
~
...'"
::0
..
'I-~ .....
!:l
~
::0
iIj!.
i"""r-..
1.0 Vcc~5V
r i4.5V
CC
0.5
'I lL
-----
I
0
-75-50-25 0 25 50 75 100 125
TEMPERATURE ("C)
,,
100 2DD 300 COO 500
Icu< (kHz)
600
IREF. Reference
Current vs. Temp. ADC0854
ifi
...'"'"
::0
2.0
1.5
.- -...
vt~.o ~DC
""- to-.
~
...z~
m
'"
~
1.0
-50 -25 0
25 50 75 100 125
TEMPERATURE ("C)
-50-25 0 25 50 75100 125
TEMPERATURE ("C)
Icc. Power Supply
Current vs. fClK. ADC0854*
1.5
ICLK J50 k'HZ
9="1"
0
150
cg
~
150
Icc. Power Supply Current
vs. Temperature. ADC0854'
._t~CC~5'5~
t'-i'r-..
100
5_1\
. ··1~VDC~iV
ISOURCE
50
Comparator Offset vs
Temperature
.L.VCC~5V
"
0
TEMPERATURE ("C)
Output Current vs
Temperature
5
1.5
-25"C
10
0
0
-100 -50
5
ISOURCE VDC = 2.4V
g
3D
'"
liil
III 2D
VREF ~5.0V
125"C
40
25"C
10
C
i
10-
IcLKf50kr
0
0
50 I-VCc~5V
~ ..........
0.25
60 Comparator Error vs fClK
Vw~~5V
"
Vcc~5V
VCC~15V @2~C
C
g
0-
z
..'"
l:! 1.0
::0
",-
E
., 0.5
::0
'"
~
0
0
100
200
300
400
500
'cu«kHz)
TL/H/5521-2
'For ADC0852 add IREF
3-192
Timing Diagrams
..
Data Input Timing
Data Output Timing
DATA OUT (001 _ _ _ _ .I
TLlH/5521-4
TL/H/5521-3
TRI-STATE Test Circuits an dWaveforms
Vee
DO
Vee
90%
50%
10%
GND~tOH
Vee
DO
VOL
10%
TLlH/5521-5
Leakage Test Circuit
TL/H/5521-6
3-193
ADC0852/ ADC0854
ClK
"n
cs'11
ClK
OI.E.
NOTE 1
Vee
CHO 2 I
CHI
I'
0
NOTE1'CH2'1
:::.,.
'
CH3 5
I
•
6
_ , ,I ,
I
,
Q
I ,
0
I I
I I , I I
CS
0
•
~cl
r
<0
DO
SL
PARAllEL
XFR TO
LATCH
".
•
•
,
ANALOG
MUX
(MUX CODE 0, 0, 0)
• TO INTERNAL
CIRCUITRY
7V ZENER
INPUT
11
':'
7
OGND~
F
9
VREF.....,.ITO
INTERNAL
CIRCUITS
BV=30V
12
,V
'l/1li.;...:..--,- 1
LADDER AND DECODER
':' AGNO
Note 1: For AOC0852; 01 is input directly to the 0 input of
ODD/SIGN, select: is forced to a "1", AGND and COM are inter-
nally tied to DGND. only Vee is brought out, VREF is internally
tied to Vee, only CH2 and CH3 are brought out.
INPUT PROTECTION-ALL LOGIC INPUTS
TLIH/5521-7
FIGURE 2. Detailed Block Diagram
10
ClK
11
12
13
14
15
14
15
-. -. -. -. -. -. -. -. - . -. -. -. - . - . - .
16
r
cs
ADCOB54
r
r
DO
~
Vo = Ve
VonC = V1-Ve
Cs = Stray Input Node Cap.
Ve = Inverter Input Bias Voltage
TL/H/5521-8
FIGURE 4a. Zeroing Phase
V1--Q)C~~
~J-vo'
C
• Ve,-Ve = (V2- V 1) C+Cs
VB
T
-A
CS
V2--Q
• Vo = - - [CV2- CV1l
C+ Cs
• Vo is dependent on V2-V1
TLlH/5521-9
FIGURE 4b. Compare Phase
A
VIN(+I
VIN(-)
V1~
·VTH(+)
A
V2~Y ~
A
·VTH(-)
.r
Vo
...- .....-t>"1
A
0+- Vo
V3~C2~
V4~Y
~ l'
=
-A
[C1 (V2 - V1) + C2 (V4 - Vall
C1 + C2 + Cs
-A
[aOC1 + aOC2l
C1 + C2 + Cs
'-Cs
I
• Comparator Reads VTH from Internal DAC Differentially
TLlH/5521-14
FIGURE 4c. Multiple Differential Inputs
3-196
r--------------------------------------------------------------------,~
C
Functional Description
(Continued)
In actual practice, the devices used in the AOC0852!4 are a
simple but important expansion of the basic comparator described above. As shown in Figure 4c, multiple differential
comparisons can be made. In this circuit, the feedback
switch and one input switch on each capacitor (A switches)
are closed in the first cycle. Then the other input on each
capacitor is connected while all of the first switches are
opened. The change in voltage at the inverter's input, as a
result of the change in charge on each input capacitor (C1,
C2), will now depend on both input signal differences.
vide multiple analog channels with software-configurable
single-ended, differential, or pseudo-differential operation.
The analog signal conditioning required in transducer-input
and other types of data acquisition systems is significantly
simplified with this type of input flexibility. One device package can now handle ground referenced inputs as well as
signals with some arbitrary reference voltage.
On the ADC0854, the "common" pin (pin 6) is used as the
"-" input for all channels in single-ended mode. Since this
input need not be at analog ground, it can be used as the
common line for pseudo-differential operation. It may be tied
to a reference potential that is common to all inputs and
within the input range of the comparator. This feature is
especially useful in single-supply applications where the analog circuitry is biased to a potential other than ground.
1.2 Input Sampling and Response Time
The input phases of the comparator relate to the device
clock (ClK) as shown in Figure 5. Because the comparator
is a sampling device, its response characteristics are somewhat different from those of linear comparators. The VIN( + )
input is sampled first (ClK high) followed by VIN( -) (ClK
low). The output responds to those inputs, one half cycle
later, on ClK's falling edge.
A particular input configuration is assigned during the MUX
addressing sequence which occurs prior to the start of a
comparison. The MUX address selects which of the analog
channels is to be enabled, what the input mode will be, and
the input channel polarity. One limitation is that differential
inputs are restricted to adjacent channel pairs. For example,
channel 0 and 1 may be selected as a differential pair but
they cannot act differentially with any other channel.
The comparator's response time to an input step is dependent on the step's phase relation to the ClK signal. If an
input step occurs too late to influence the most imminent
comparator decision, one more ClK cycle will pass before
the output is correct. In effect, the response time for the
VIN( +) input has a minimum of 1 ClK cycle + 1 p.S and a
maximum of 2 ClK cycles + 1 p.S. The VIN( -) input's delay
will range from 1!2 ClK cycle + 1 p.S to 1.5 ClK cycles +
1 p.S since it is sampled after VIN( +).
The sampled inputs also affect the device's response to
pulsed signals. As shown in the shaded areas in Figure 5,
pulses that rise and! or fall near the latter part of a ClK halfcycle may be ignored.
The channel and polarity selection is done serially via the 01
Input. A complete listing of the input configurations and corresponding MUX addresses for the AOC0852 and ADC0854
is shown in tables I and II. Figure 6 illustrates the analog
connections for the various input options.
The analog input voltage for each channel can range from
50 mV below ground to 50 mV above Vee (typically 5V)
without degrading accuracy.
1.3 Input Multiplexer
A unique input multiplexing scheme has been utilized to pro-
A VIN( + I AND VTHI-) SAMPLED IlERDlNG)
B VIN(-) AND VTH(+) SAMPLED
C VIN(+) AND VTH(-) FDR
NEXT COMPARISDN
D OUTPUT UPDATED
BASED Oil A AND B
E VIN(_)ANDVTH(+)FOR
NEXT COMPARISON
OUTPUT BASED
ONCANOE
ClK
SAMPLING UNCERTAINTY FOR TRANSIENTST
ON VIN( +) INPUT DURING THIS TIME
L
SAMPLING UNCERTAINTY FDR TRANSIENTS
ON VINI-l INPUT DURING THIS TIME
TL/H/5521-13
FIGURE 5. Analog Input Timing
3-197
oo
OG
C11
N
......
~
C
o
o
OG
C11
.j::a.
Functional Description (Continued)
TABLE I. MUX Addressing: ADC0854
Single-Ended MUX Mode
MUXAddress
SGLI
OIF
0001
1
1
Channel
SELECT
0
0
0
+
0
1
1
1
0
1
1
1
SIGN
TABLE II. MUX Addressing: AOC0852
Single Ended MUX Mode
1
2
MUXAddress
3
+
COM
0001
-
1
0
-
1
1
-
+
+
Channel
SGU
OIF
SIGN
+
+
COM is internally tied to A GND
-
Differential MUX Mode
MUXAddress
Differential MUX Mode
MUXAddress
Channel
SGLI
DIF
0001
0
0
0
0
1
0
1
0
0
1
1
SIGN
SELECT
0
1
0
+
-
-
+
2
3
+
-
-
+
Channel
SGLI
OIF
0001
0
0
0
1
4 Single-Ended
SIGN
0
1
+
-
+
4 Pseudo-Differential
0-+
0-+
1-+
1-+
2- +
2-+
3-+
3-+
~
1
0
~
COM(-)
COM (-)
VBIAS -=-
-!
'2 Differential
Mixed Mode
O,l {
_ - +
l
-
+(-)
0.1{= -(+)
+(-)
2.3{=
-(+)
2- +
3- +
~
COM (-)
VBIAS-=-
*
FIGURE 6. Analog Input Multiplexer Options for the ADC0854
3-198
TLlH/5521-15
Functional Description
»
c
o
Q
(Continued)
be done indefinitely, without reprogramming the device, as
long as CS remains low. Each new comparator decision will
be shifted to the output on the falling edge of the clock.
However, the output will, in effect, "lag" the analog input by
0.5 to 1.5 clock cycles because of the time required to make
the comparison and latch the output (see Figure 5).
8. All internal registers are cleared when the CS line is
brought high. If another comparison is desired CS must
make a high to low transition followed by new address and
threshold programming.
2.0 THE DIGITAL INTERFACE
An important characteristic of the ADC0852 and ADC0854
is their serial data link with the contrOlling processor. A serial communication format eliminates the transmission of low
level analog signals by locating the comparator close to the
signal source. Thus only highly noise immune digital signals
need to be transmitted back to the host processor.
To understand the operation of these devices it is best to
refer to the timing diagrams (Figure 3) and functional block
diagram (Figure 2) while following a complete comparison
sequence.
1. A comparison is initiated by first pulling the CS (chip select) line low. This line must be held low for the entire addressing sequence and comparison. The comparator then
waits for a start bit, its MUX assignment word, and an 8-bit
code to set the internal DAC which supplies the comparator's threshold voltage (VTH).
2. An external clock is applied to the CLK input. This clock
can be applied continuously and need not be gated on and
off.
3.0 REFERENCE CONSIDERATIONS I RATIOMETRIC
OPERATION
The voltage applied to the "VREF" input of the DAC defines
the voltage span that can be programmed to appear at the
threshold input of the comparator. The ADC0854 can be
used in either ratiometric applications or in systems with
absolute references. The VREF pin must be connected to a
source capable of driving the DAC ladder reSistance (typ.
2.4 kG) with a stable voltage.
In ratiometric systems, the analog input voltage is normally
a proportion of the DAC's or AID's reference voltage. For
example, a mechanical position servo using a potentiometer
to indicate rotation, could use the same voltage to drive the
reference as well as the potentiometer. Changes in the value of VREF would not affect system accuracy Since only the
relative value of these Signals to each other is important.
This technique relaxes the stability requirements of the system reference since the analog input and DAC reference
move together, thus maintaining the same comparator output for a given input condition.
In the absolute case, the VREF input can be driven with a
stable voltage source whose output is insensitive to time
and temperature changes. The LM385 and LM336 are good
low current devices for this purpose.
3. On each rising edge of the clock, the level present on the
DI line is clocked into the MUX address shift register. The
start bit is the first logic "1" that appears on this line. All
leading zeroes are ignored. After the start bit, the ADC0852
expects the next 2 bits to be the MUX assignment word
while the ADC0854, with more MUX configurations, looks
for 3 bits.
4. Immediately after the MUX assignment word has been
clocked in, the shift register then reads the next eight bits as
the input code to the internal DAC. This eight bit word is
read LSB first and is used to set the voltage applied to the
comparator's threshold input (internal).
5. After the rising edge of the 11 th or 12th clock (ADC0852
or ADC0854 respectively) following the start bit, the comparator and DAC programming is complete. At this pOint the
DI line is disabled and ignores further inputs. Also at this
time the data out (DO) line comes out of TRI-STATE and
enters a don't care state (undefined output) for 1.5 clock
cycles.
The maximum value of VREF is limited to the Vee supply
voltage. The minimum value can be quite small (see typical
performance curves) allowing the effective resolution of the
comparator threshold DAC to also be small (VREF = 0.5V,
DAC resolution = 2.0 mY). This in turn lets the deSigner
have finer control over the comparator trip point. In such
instances however, more care must be taken with regard to
noise pickup, grounding, and system error sources.
6. The result of the comparison between the programmed
threshold voltage and the difference between the two selected inputs (VIN (+) - VIN (-)) is output to the DO line on
each subsequent high to low clock transition.
7. After programming, continuous comparison on the same
selected channel with the same programmed threshold can
1-;:::::;C=;1-"
5V
Vee
Vee
2k
:-+
I-
j"""
ADC0854
IIV-1.25V
v,"
VREF~
+
r-
GND
*
ADC0854
1.2SV
,l--l"3"
GNO
TLlH/5521-16
b) Absolute with a Reduced Span
a) Ratiometric
FIGURE 7. Referencing Examples
3-199
CI)
UI
;;
C
oQ
CI)
UI
~
~
II)
co
,---------------------------------------------------------------------
CI
Functional Description
C
4.0 ANALOG INPUTS
o
~
~
~
o
C
c
Typical Applications (Continued)
0
0
CO
U1
V·
~
Io..J
I\)
I'ce
~.
......
Vee
....!,!. lDpI'
J>
vee
l'
C
0
TRANSDUCER
ClK
ADCIUI54
cs
ADCD854
100kHz
DI
5VnrClDCK
ClK
GND
DV
DD
~
DD
GND
GND
TL/H/5521-19
FIGURE 10. Generating Vee from the Comparator Clock
TLlH/5521-20
FIGURE 11. Remote Sensing-Clock
and Power on One Wire
15V
> .....WIr-....-IVIN(+)
Vee
+ 5V
TIDpi'
'110(-)
TLlH/5521-21
FIGURE 12. Protecting the Analog Input
ADCIUI52
GND
'::"
CHD
CHI
~------------f.2~~3~-----------I
--------
ANALOG INPUT
FIGURE 13. One Component Window Comparator
Requires no additional parts. Window comparisons can be accomplished by
inputting the upper and lower window limits into 01 on successive comparisons and observing the two outputs:
Two high outputs -- input> window
Two low outputs -i> input < window
One low and one high -i> input is within window
3-201
TL/H/5521-22
0
CO
....
U1
Typical Applications
(Continued)
110V"C
HI
9 VREF
DO 10
5V 14 V,C
GND
~ ~____________~~~~HD~;CH~I________~CD~M~~
5V
lk
2.73V
LM335
TEMP
1l0VM:
LD
SENSOR
4k
2k
FULL·
SCAlf
2k
OFFSET
LM103
3.3V
2k
4k
TLIH15521-23
FIGURE 14. Serial Input Temperature Controller
Note 1: ADC08S4 does not require constant service from computer. Self controlled after one write to DI if CS remains low.
Note 2: U,: Solid State Relay. Potter Brumfield #EOM1DB22
Note 3: Set Temp via. DI. Range: 0 to 12S'C
330
w.,...-------,
1DV-
o
oo
Typical Applications (Continued)
CO
U1
N
.....
l>
o
DO 10
(")
o
CO
U1
~
Vee
22k
r
,
L
oJ
I
lOk
2k
ILM335
Vcc-wo_P-I
Ik
3k
TL/H/5521-25
FIGURE 16. 4 Channel Temperature Alarm
• Uses pseudo-differential input MUX mode
• 4 Thermocouple channels need only 1 cold-junction compensation network (TREF)
• Range 0 to 300"C
TLlH/5521-29
Hysteresis band
• 01 used in inverted mode for low VSAT
FIGURE 17. Adding Comparator Hysteresis
3-203
= 50 mV
'OIl'
Ln
co
o
o
Typical Applications (Continued)
c
cc
.....
N
SV
Ln
co
o
Vee
g
CC
, r
TRIGGER
INPUT
SV
~______D_D+6_Jlii
..
111 000
VREf
11--
U~OV
1N4148
\£
----SV
- --- VTH
OV
TL/H/5521-27
FIGURE 18. Pulse-Width Modulator
• Aange of pulse-widths controlled via AI. Cl
250 kHz
100k
DD 6
SV
OUTPUT
OV-5V
10k
10k
ADC08S2
':'
GND
':'
CHO
':'
CH1
~--------~~~--------~
':'
1k
1N4148
82011
SV
TL/H/5521-28
FIGURE 19. Serial Input 8-Bit DAC
3-204
)it
C
Ordering Information
Part Number
Analog Input
Channels
oo
Total
Unadjusted Error
ADC0852BJ
J08A
ADC0852BCJ
ADC0852BCN
2
±1
ADC0852CCN
ADC0854BJ
ADC0854BCJ
ADC0854CCJ
±1
ADC0854CCN
3-205
-55'C to + 125'C
N08E
O'Cto 70'C
J08A
-40'Cto + 85'C
N08E
O'Cto 70'C
J14A
-55'Cto + 125'C
-40'Cto +85'C
±Yz
4
Temperature
Range
-40'Cto + 85'C
±Yz
ADC0852CCJ
ADC0854BCN
Package
N14A
O'Ct070'C
J14A
-40'Cto +85'C
N14A
O'Ct070'C
co
(II
I\)
i>
c
o
o
co
(II
.I=fo,
-~
--8....
N
o
U
C
10k
~
• 100
)
•
,., ~LM336
.
--
-5V
TLlH/5675-9
NOTE: VIN( -) should be biased so
that VIN( -);" - O.05V when potentiometer
wiper is set at most negative
voltage position.
FIGURE 3. Full-Scale Adjust
FIGURE 2. Zero Adjust Circuit
3-211
TLlH/5675-10
o....
o
o
....
......
~
c
o
....
o
....
I\)
.-
C'I
Q
.0
Typical Application
Q
5V
cr:
.....
.-
20
VCC
Q
Q
.-
ClK R
Q
ClK IN
0
cr:
19
TRANSDUCER
10k
10·BIT RESDlUTION
DVER ANY DESIRED
ANALOG INPUT
VOLTAGE RANGE
V,N!"
ADC1001
DIFF INPUTS
V,NH
AGND
VREFIZ
D GND
10
TL/H/5675-1
Block Diagram
«
SET
.-"-
~I
WlI
"
RESET
D
INPUT PROTECTION
FOR ALL lOGIC INPUTS
INPUT
ClK R
~~..
ClK IN
-::~.
GEN
ClKDSC
Gl
F·'·'"~'
I
ClKS
Vee (VREF'
STARTF/F
I
D
J
cr
0
~
LADDER
AND
DECODER
R
0
F/F I
BV ~30V
RESET
--
'£GND
ClKS
CIRCUITS
SAR
lATCH
(NOTE 21
REF/Z
R
:=
:::
;::
START CONVERSION
/ ' F RESET' "0"
10·BIT
SHIFT R
REGISTER
~
I
~
DAC
V(DUT!
~
--
*AGND
[;>
T-
G2
~~ ~ ~+-~
V'N(+I
INH
~~ ~~
I
Iili
XFER
BYTE SEQUENCER AND
TAl-STATE
OUTPUT lATCHES
l!!
MSB
,
,
C!IN OTE 11
In
''']
Vce
~
Q
,
I+lSB
ADCIOOI ZO·PIN
I
ADCIOZI 24·PIN
~I
TRI-STATE CONTROL
~
SHOT
~J
-I
INTR F/F
I
~
1IITlf
1-4Dons
RESET
"1'" OUTPUT ENABLE
Note 1: Cl! shown twice for clarity.
Note 2: SAR = Successive Approximation Register.
TUH/5675-13
FIGURE 1
3·212
r----------------------------------------------------------------.~
II
C
o
.....
National
Semiconductor
Corporation
Q
Q
~
C
ADC1005, ADC1025 10-Bit I-LP Compatible AID Converters o.....
~
General Description
The ADC1005 and ADC1025 are CMOS 10-bit successive
approximation AID converters. The 20-pin ADC1005 outputs 10-bit data in a two-byte format for interface with B-bit
microprocessors.
The 24-pin ADC1025 outputs 10 bits in parallel and is Intended for 16-bit data buses or stand-alone applications.
Both A-to-Ds have differential inputs to permit rejection of
common-mode signals, allow the analog input range to be
offset, and also to permit the conversion of signals not referred to ground. In addition, the reference voltage can be
adjusted, allowing smaller voltage spans to be measured
with 10-bit resolution.
• Operates ratiometrically or with 5 Voc voltage reference or analog span adjusted voltage reference
• OV to 5V analog input voltage range with single
5V supply
• On-chip clock generator
• TLL/MOS input/output compatible
• 0.3" standard width 20-pin DIP or 24-pin DIP with 10bit parallel output
• Available in 20-pin or 2B-pin molded chip carrier
package
Features
• Resolution
• Linearity Error
• Conversion Time
• Easy interface to all microprocessors
• Differential analog voltage inputs
Key Specifications
10 bits
±% LSB and ±1 LSB
50,...s
Connection Diagrams
ADC1005 (for an a-bit data bus)
ADC1025 (10-blt parallel outputs)
Dual-In-Llne Package
'-/
Dual-In-Llne Package
20 ~Vee
CS-l
24 -Vee
iW-2
19 '-CLKR
iW-
23,...CLKR
Wii-3
lB~
BIT2 0
Wii-3
CLKIN- 4
17,..
BIT3 0
CLKIN- 4
INlR- 5
16 '-
BIT4 0
CS-l
2
22 -0'
21
"-0'
20i-B1T2
5
INl1l
V,N (+)- 6
15
f-
BIT5 0
V,N(+)- 6
19i-BIT3
V,N(_)- 7
14~
BIT6 0
V,N(_)
7
lB r-BIT4
AGNO- B
13 r-
BIT7 0
AGND- B
17 r-BIT5
VREF - 9
12
f-
BITB BIT 0 (L5B)
VREF
9
16 r-BIT6
BIT 1
10
15 r-BIT7
(l5B)BITO
11
14 r-BITB
OGND
12
13 r-BIT9(~SB)
11 r-(~SB) BIT9 BIT 1
OGND- 10
lSTBYTE 2ND BYTE
TL/H/5261-1
TL/H/5261-2
Top View
Top View
ADC1025 Molded Chip Carrier Package
ADC1005 Molded Chip Carrier Package
25 24 23 22 21 20 19
0'-26
CLKR- 19
Vee -
20
CS- 1
iW-2
Wii-3
4
5
6
7
B
17 -BIT7
Vcc - 2B
16 -BITB
cs-
1
15 -B1T9
iW-
2
14 -OGND
Wii-3
13 "- BITD
12 i-BIT1
CLKIN- 4
~I'~ ~ ~ J,
5 6 7
da;J'~~
TUH/5261-19
Top View
·TRI·STATE~ output buffers which output 0 during
lB-NC
CLKR- 27
'I!t=
B 9 10 11
~ !...!... J, ~
Top View
AD
See Ordering Information
3-213
L
~zij-~Z~
TL/H/5261-20
Absolute Maximum Ratings
Operating Ratings
(Notes 1 & 2)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (Vee!
Logic Control Inputs
Voltage at Other Inputs and Outputs
Input Current Per Pin
Input Current Per Package
Storage Temperature Range
6.SV
-0.3Vto +lSV
4.SVt06.0V
TMNS:TAS:TMAX
-SS·CS:TAS: + 12S·C
ADC102SBJ, ADC102SCJ
ADCl OOSBCJ, ADCl OOSCCJ
-0.3Vto Vcc +0.3V
±SmA
-40"CS:TAS: + 8S·C
ADC102SBCJ, ADC102SCCJ
ADCl OOSBCJ-l, ADC100SCCJ-l
±20mA
- 6S·C to + lS0·C
Package Dissipation at TA = 2S·C
Lead Temperature
(Soldering, 10 seconds)
Dual-In-Line Package (Plastic)
Dual-In-Line Package (Ceramic)
Surface Mount Package
Vapor Phase (60 seconds)
Infrared (lS seconds)
ESD Susceptibility (Note 8)
(Notes 1 & 2)
Supply Voltage (Vee!
Temperature Range
ADCl OOSBJ, ADC100SCJ
0·CS:TAs:70·C
ADCl 02SBCJ-l, ADC1025CCJ-l
ADC100SBCN, ADC100SCCN
87SmW
ADC102SBCN, ADC102SCCN
ADC100SBCV, ADC100SCCV
ADC1025BCV,ADC102SCCV
260·C
300·C
21S·C
220·C
800V
Electrical Characteristics The following specifications apply for Vee = SV, VREF = SV, feLK = 1.8 MHz
unless otherwise specified. Boldface limits apply from T MIN to T MAX; All other limits TA = Tj = 2S·C.
ADC10X5BCJ·l, ADC10X5CCJ·l
ADC10X5BCN, ADC10X5CCN
ADC10X5BCV, ADC10X5CCV
Limit
Units
Design
Design
Tested
Typ
Limit
Limit
Limit
(Note 5)
(Note 7)
(Note 7)
(Note 6)
ADC10X5BJ,ADC10X5BCJ
ADC10X5CJ, ADC10X5CCJ
Parameter
Conditions
Typ )1
(Note 5)
Tested
Limit
(Note 6)
I
I
Converter Characteristics
Linearity Error (Note 3)
ADC10X5BJ, ADC10XSBCJ
ADClOXSBCJ-l, BCN, BCV
ADC10X5CJ, ADC10XSCCJ
ADC10X5CCJ-l, CCN, CCV
±O.5
±O.S
±O.5
±1
±1
±O.S
±O.5
±1
±1
±O.S
±O.5
±1
Zero Error
ADCl OXSBJ, ADCl OXSBCJ
ADC1OX5BCJ-1, BCN, BCV
ADC1 OX5CJ, ADC10X5CCJ
ADC10XSCCJ-1, CCN, CCV
±O.5
±1
Fullscale Error
ADC1 OX5BJ, ADC1 OXSBCJ
ADC10X5BCJ-l, BCN, BCV
ADC1 OX5CJ, ADC1 OXSCCJ
ADC1 OX5CCJ-1, CCN, CCV
±O.5
MIN
MAX
Common-Mode
Input (Note 4)
MIN
MAX
2.2
8.3
4.8
4.8
4.8
4.8
±1
±1
2.4
7.6
2.2
8.3
kO
kO
Vce+ O.OS Vee + 0.05
GND-O.OS GND-O.05
Vee + 0.05
GND-O.05
VIN(+) orVIN(-)
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
±1
Reference
Input
Resistance
LSB
LSB
LSB
LSB
V
V
DC Common-Mode
Error
Over Common-Mode
Input Range
±Ya
±y..
±Ya
±%
±y..
LSB
Power Supply Sensitivity
Vcc= 5Voc±S%
VREF = 4.7SV
±Ya
±y..
±Ya
±%
±y..
LSB
3-214
»
c
Electrical Characteristics (Continued) The following specifications apply for Vcc =
SV, VREF = SV, fClK =
1.8 MHz unless otherwise specified. Boldface limits apply from T MIN to T MAX; All other limits TA = Tj = 2S'C.
Parameter
Conditions
Typ
(Note 5)
Tested
limit
(NoteS)
o
ADC10XSBCJ-1, ADC10XSCCJ-1
ADC10XSBCN, ADC10XSCCN
ADC10XSBCV,ADC10XSCCV
ADC10XSBJ,ADC10XSBCJ
ADC10XSCJ, ADC10X5CCJ
Design
limit
(Note 7)
Typ
(NoteS)
o
.....
o
U1
......
Tested
limit
(Note S)
Design
limit
(Note 7)
limit
Units
N
U1
VIN(1) logical "1" Input
Voltage MIN
VCC=S.2SV
(except ClKIN )
2.0
2.0
2.0
V
VIN(O), logical "0" Input
Voltage MAX
Vcc=4.7SV
(Except ClKIN )
0.8
0.8
0.8
V
liN, logical "1" Input
Current MAX
VIN=S.OV
1
/-LA
liN, logical "0" Input
Current MAX
VIN=OV
O.OOS
1
O.OOS
-0.005
-1
-O.OOS
-1
-1
/-LA
VT + (MIN), Minimum ClKIN
Positive going Threshold
Voltage
3.1
2.7
3.1
2.7
2.7
V
VT(MAX), Maximum ClKIN
Positive gOing Threshold
Voltage
3.1
3.5
3.1
3.S
3.5
V
VT-(MIN), Minimum ClKIN
Negative going Threshold
Voltage
1.8
1.5
1.8
1.S
1.5
V
VT -(MAX), Maximum ClKIN
Negative going Threshold
Voltage
1.8
2.1
1.8
2.1
2.1
V
VH(MIN), Minimum ClKIN
Hysteresis (VT+-VT-)
1.3
0.6
1.3
O.S
0.6
V
VH(MAX), Maximum ClKIN
Hysteresis (VT + -VT-)
1.3
2.0
1.3
2.0
2.0
V
2.4
4.5
2.8
4.6
2.4
4.5
V
V
0.4
0.34
0.4
V
Vcc=4.7SV
IOUT= -3S0 /-LA
IOUT= -10 /-LA
VOUT(1), logical "1"
Output Voltage
MIN
VOUT(O), logical "0"
Output Voltage
MAX
Vcc=4.7SV
IOUT=1.6mA
lOUT, TRI-STATE Output
Current
MAX
VOUT = OV
VOUT = SV
-0.Q1
0.01
-3
3
-0.01
0.01
-0.3
0.3
-3
3
/-LA
/-LA
ISOURCE, Output Source
Current
VOUT=OV
MIN
-14
-6.5
-14
-7.S
-6.5
mA
ISINK, Output Sink
Current
MIN
16
8.0
16
9.0
8.0
mA
1.S
3
1.S
2.S
3
mA
VOUT=SV
Icc, Supply Current
fClK = 1.8 MHz
MAX
CS="1"
AC Electrical Characteristics The following specifications apply for VCC =
SV, VREF = SV, t, = tf = 20 ns
unless otherwise specified. Boldface limits apply from TMIN to TMAX; All other limits T A = Tj = 2S'C.
T~sted
limit
(Note 6)
Design
limit
(Note 7)
limit
Units
'ClK, Clock FrequencyMIN
MAX
0.2
2.S
0.2
2.S
MHz
MHz
Clock Duty Cycle
40
SO
40
60
%
%
Parameter
Conditions
Typ
(Note 5)
MIN
MAX
3-21S
o
.....
o
DC Characteristics
1
»
c
AC Electrical Characteristics
The following specifications apply for VCC = 5V. VREF = 5V. t, = tf = 20 ns
.unless otherwise specified. Boldface limits apply from T MIN to TMAX; All other limits T A = Tj = 25°C. (Continued)
Parameter
Typ
Conditions
(Note 5)
Tested
Design
Limit
Limit
Limit
Units
(Note 6)
(Note 7)
MIN
80
80
1/fcLK
MAX
90
90
1/fCLK
te. Conversion Time
MIN
fCLK= 1.8 MHz
45
45
/Ls
MAX
fCLK = 1.8 MHz
50
50
/Ls
100
150
150
ns
170
300
300
ns
tw(WR)L' Minimum WR Pulse Width
CS=O
tACC. Access Time (Delay from falling
CS=O
edge of RD to Output Data Valid)
CL = 100 pF. RL = 2k
t1H. toH. TRI-STATE Control (Delay
RL =10k.CL =10pF
125
200
ns
from Rising Edge of RD to Hi-Z State)
RL =2k.CL =100pF
145
230
230
ns
300
450
450
ns
400
550
twh tRI. Delay from Falling Edge of
WR or RD to Reset of INTR
tIRS. INTR to 1 st Read Set-up TIme
550
ns
CIN. CapaCitance of Logic Inputs
5
7.5
pF
COUTo Capacitance of Logic Outputs
5
7.5
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage 10 the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to ground.
Note 3: Unearity error Is defined as the deviation of the analog value. expressed in LSBs. Irom the stralghlline which passes through the end points of the transfer
characteristic.
Note 4: For VIN(-);"VIN(+) the digital oulput code will be 00 0000 0000. Two on-chip diodes are tied 10 each analog Input which will lorward conduct lor analog
input voltages one diode drop below ground or one diode drop greater than Vee supply. Be carelul. during testing at low Vee levels (4.5V). as high level analog
inputs (5V) can cause this input diode 10 conduct. especially at elevated temperatures, and cause errors lor analog inputs near lull·scale. The spec allows 50 mV
lorward bias 01 either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To
achieve an absolute 0 Vee to 5 Vee input voltage range will therefore require a minimum supply voltage 01 4.950 Voe over temperature variations, Initiallolerance
and loading.
Note 5: Typlcals are at 25'C and represent most likely parametric norm.
Note 6: Tested and guaranteed 10 National's AOQL (Average OutgOing Quality Level).
Note 7: Guaranteed, but not 100% production tested. These limits are not used to calculate outgOing quality levels.
Note 8: Human body model, 100 pF discharged through a 1.5 kfl reslstor.
Functional Diagram
cs
1i" r.=:
CONTROL
AIID
nMING
tt>I
VI.(-)
-iiilli
!
~
~
+
SAR
BYTE
SEIIUENCER
AND
-
I
.......
,
~
TRl·smE"
OUT1'\lT
LATCH
LADDER
1
3-216
~
f-
TWO BYTE
ADCIDti5
ONLY
I1-.
AIID
DECDDER
AL
~l
~
~
I
DGND
I
Vee
(5V)
TUH/5261-3
):.
Typical Performance Characteristics
1.8
"'
~
..
1.1
~
1.6
~
1.5
~
..'"
.
..=....=
!:;
>
:g
>
5
u
~
..~
~
ZOO
L
1A
1.3
4.50
I-"
VT+
Z.7
::l
2.3
i!!
1.9
en
VT_
I
I
~
100
4.75
5.00
5.Z5
5.50
0
ZOO
400
600
BOD
1000
LOAU CAPACITANCE (pF)
VCC - SUPPLy VOLTAGE (VOC)
Output Current vs
Temperature
8
IS~U~C~
0
25
50
75
0.8 i----ii----if- ..::_...:
z
0.4
~
I
5.25
5.50
1--'":"-+-'1'<--+----1
0.2
~
0
ffi -0.2
~UT=Z.4Vuc
-lSINK
VOUT' 0.4 VOC
5.00
1.----.-----.~~~
iii
~
:II 0.6
OATAOUTPUT
BUFFERS
2
4.75
VCC -SUPPLY VOLTAGE (VUC)
Typical linearity Error
vs Clock Frequency
VCC= 5V OC
-50 -25
1.5
4.50
~ -0.4 1---+---+----1
~ -0.61---+---+---;
!!i -0.8 1 - - - + - - - + - - - ;
.
-1 L-__
0.2
100 125
~
____
1.0
~
____
1.8
~
2.6
CLOCK FREQUENCY (MHz)
TA - AMBIENT TEMPERATURE ('C)
TUH15261-4
Timing Diagrams
Start Conversion
\
/
~_~_(W_R)_L
~
__________ ______________
~
(LAST DATA WAS READ)
(LAST DATA WAS NOT READ)
TLIH15261-5
Output Enable and Reset INTR
INTR RESET
iiii
2NORO\
/
\...-.- - - - I
'IRS
-
TRloSTATE"
-- -
-
-
-<. . __
_
L_S_.J}- _ _
BYTE
•
TLIH15261-6
'The 24-pin ADC1025 outputs all 10 bits on each RD
Note: All timing Is measured from the 50% voltage points.
3-217
):.
C
N
-5SoCSTA $+125°C
9
300
a
9
I
3.1
o
o
en
.......
o
....
o
I
~
"''"
400
>
=
::l
ClK IN Schmitt Trip levels
vs Supply Voltage
3.5
SOD
17
-.-!-55'cdAk+lz5!C
o....
Delay from Falling Edge of
RD to Output Data Valid vs
load Capacitance
logic Input Threshold
Voltage vs Supply Voltage
~
C
Timing Diagrams (Continued)
Byte Sequencing for the 20-Pin ADC100S
Byte
Order
8-Blt Data Bus Connection
DB7 DB6 DBS DB4 DB3 DB2 DB1 DBO
1st
MSB
Bit 9 Bit 8 Bit7 BitS BitS Bit4 Bit3 Bit2
2nd
LSB
Bit 1 BitO
0
0
0
0
0
0
Block Diagram
__
n~::::::::::~~::~ ~SE~T__~~~~>-~~::::::::::::::~__!O'ESrET~__.,
WR"
INPUT PROTECTION
FOR ALL LOGIC INPUTS
TO INTERNAL
CIRCUIT
eLKR
elKB
INPUT,
STARTF/F
vcc=-----r--:00,"
AND
START CONVERSION
IF RESET· "0"
DECODER
SAO
vo"o--------+lI-...,
LATCH
INOTE2)
oAC
V(OUT)
AGND
VINI-Io-+~,-.....I
RINOTE 1IO;:::::::::::~~::)-____--""::=:;:;;;:;:;.;:~~_____---_. . .~
ADC102524·PIN
iiliC
Note 1: CS shown twice for clarity.
TRloSTATE CONTROL
'T'II OUTPUT ENABLE
Note 2: SAR ~ Successive Approximation Register.
FIGURE 1.
3-218
RESET
TL/H/5261-11
:I>
c
Functional Description
o
.....
o
1.0 GENERAL OPERATION
o
UI
1.4 Free-Running and Self-Clocking Modes
A block diagram of the AID converter is shown in Figure 1
All of the inputs and outputs are shown and the major logic
control paths are drawn in heavier weight lines.
For operation in the free-running mode an initializing pulse
should be used, following power-up, to ensure circuit operation. In this application, the CS input is grounded and the
WR input is tied to the INTR output. This WR and INTR
node should be momentarily forced to logiC low following a
power-up cycle to ensure start up.
1.1 Converter Operation
The ADC1005. ADC1025 use an advanced potentiometric
resistive ladder network. The analog inputs, as well as the
taps of this ladder network are switched into a weighted
capacitor array. The output of this capacitor array is the input to a sampled data comparator. This comparator allows
the successive approximation logic to match the analog input voltage [VIN(+) - VIN(-)] to taps on the R network.
The most significant bit is tested first and after 10 comparisons (80 clock cycles) a digital 10-bit binary code (all "1 "s
= full-scale) is transferred to an output latch.
The clock for the AID can be derived from the CPU clock or
an external RC can be added to provide self-clocking. The
CLK IN makes use of a Schmitt trigger as shown in Figure 2.
ClK R
19
R
1.2 Starting a Conversion
ClK IN
4
The conversion is initialized by taking CS and WR simultaneously low. This sets the start flip-flop (F IF) and the resulting "1" level resets the 1O-bit shift register, resets the interrupt (INTR) F IF and inputs a "1" to the D flop, FIF1, which
is at the input end of the 10-bit shift register. Internal clock
signals then transfer this "1" to the Q ouput of F/F1. The
AND gate, G1, combines this "1" output with a clock signal
to provide a reset signal to the start F/F. If the set signal is
no longer present (either WR or CS is a "1 ") the start F IF is
reset and the 10-bit shift register then can have the "1"
clocked in, allowing the conversion process to continue. If
the set signal were still present, this reset pulse would have
no effect and the 1O-bit shift register would continue to be
held in the reset mode. This logic therefore allows for wide
CS and WR signals. The converter will start after at least
one of these signals returns high and the internal clocks
again provide a reset signal for the start F/F.
~
ClK
c-'-
r
AID
TLlH/5261-12
1
fClK "'1.1 RC
FIGURE 2. Self-Clocklng the AID
2.0 REFERENCE VOLTAGE
The voltage applied to the reference input of these converters defines the voltage span of the analog input (the difference between VIN(MAX) and VIN(MIN» over which the 1024
possible output codes apply. The devices can be used in
either ratiometric applications or in systems requiring absolute accuracy. The reference pin must be connected to a
voltage source capable of driving the reference input resistance of typically 4.8 kfi. This pin is the top of a resistor
divider string used for the successive approximation conversion.
To summarize. on the high-to-Iow transition of the WR input
the internal SAR latches and the shift register stages are
reset. As long as the CS input and WR input remain low, the
AID will remain in a reset state. Conversion will start after at
least one of these inputs makes a low-to-high transition.
In a ratiometric system (Figure 3a) the analog input voltage
is proportional to the voltage used for the AID reference.
This voltage is typically the system power supply, so the
VREF pin can be tied to Vee. This technique relaxes the
stability requirements of the system references as the analog input and AID reference move together maintaining the
same output code for a given input condition.
1.3 Output Control
After the "1" is clocked through the 1O-bit shift register
(which completes the SAR search) it causes the new digital
word to transfer to the TRI-STATE output latches. When the
XFER signal makes a hlgh-to-Iow transition the one shot
fires, setting the INTR F/F. An inverting buffer then supplies
the INTR output Signal.
For absolute accuracy (Figure 3b), where the analog input
varies between very specific voltage limits, the reference pin
can be biased with time and temperature stable voltage
source. The LM385 and LM336 reference diodes are good
low current devices to use with these converters.
a
Note that this SET control of the INTR F/F remains low for
approximately 400 ns. If the data output is continuously enabled (CS and RD both held low) the INTR output will still
signal the end of the conversion (by a high-to-Iow transition). This is because the SET input can control the Q
output of the INTR F/F even though the RESET input is
constantly at a "1" level. This INTR output will therefore
stay low for the duration of the SET signal.
The maximum value of the reference is limited to the Vee
supply voltage. The minimum value, however, can be small
to allow direct conversions of transducer outputs providing
less than a 5V output span. Particular care must be taken
with regard to noise pickup, circuit layout, and system error
voltage sources when operating with a reduced span due to
the increased sensitivity of the 90nverter (1 LSB equals
VREFI1024).
When data is to be read, the combination of both CS and
RD being low will cause the INTR F/F to be reset and the
TRI-STATE output latches will be enabled.
3-219
l>
c
o
.....
oI\)
UI
Functional Description (Continued)
5V
5V
Vee
Vee
~ViNI+)
XOR
;J
OV-2.5V
VINI+)
VREF
I--
2.5V
~ ~ LM385·2.5
~----IVINI-)
-ViNH
AGND
AGND
1
1
FIGURE 3a. Ratlometric
TL/H/5261-18
TUH/5261-17
FIGURE 3b. Absolute with a Reduced Span
3.0 THE ANALOG INPUTS
input at 5V, this DC current is at a maximum of approximately 5 pA Therefore, bypass capacitors should not be used at
the analog inputs or the VREFpin for high resistance sources (> 1 kn). If input bypass capacitors are necessary for
noise filtering and high source resistance is desirable to
minimize capacitor size, the detrimental effects of the voltage drop across this input resistance, which is due to the
average value of the input current, can be eliminated with a
full-scale adjustment while the given source resistor and input bypass capacitor are both in place. This is possible because the average value of the input current is a linear function of the differential input voltage.
3.1 Analog Differential Voltage Inputs and
Common-Mode Rejection
The differential inputs of these converters reduce the effects of common-mode input noise, which is defined as
noise common to both selected" + " and" -" inputs (60 Hz
is most typical). The time interval between sampling the
" +" input and the "-" input is half of an internal clock
period. The change in the common-mode voltage during this
short time interval can cause conversion errors. For a sinusoidal common-mode signal, this error is:
4
VERROR(MAX) = VPEAK (2'11' fCM) X fCLK
3.4 Input Source Resistance
large values of source resistance where an input bypass
capacitor is not used, will not cause errors if the input currents settle out prior to the comparison time. If a low pass
filter is required in the system, use a low valued series resistor (S: 1 kn) for a passive RC section or add an op amp RC
active low pass filter. For low source resistance applications
(S:0.1 kO) a 4700 pF bypass capacitor at the inputs will
prevent pickup due to series lead induction of a long wire. A
1000 series resistor can be used to isolate this capacitor both the R and the C are placed outside the feedback loop
- from the output of an op amp, if used.
where fCM is the frequency of the common-mode signal,
VPEAK is its peak voltage value and fCLK is the clock frequency at the ClK IN pin.
For a 60 Hz common-mode signal to generate a 1/4 lSB
error (1.2 mY) with the converter running at 1.8 MHz, its
peak value would have to be 1.46V. A common-mode signal
this large is much greater than that generally found in data
aquisition systems.
3.2 Input Current
Due to the sampling nature of the analog inputs, short duration spikes of current enter the" +" input and exit the" -"
input at the clock rising edges during the conversion. These
currents decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period.
3.5 Noise
The leads to the analog inputs (pins 6 and 7) should be kept
as short as possible to minimize input noise coupling. Both
noise and undesired digital clock coupling to these inputs
can cause system errors. The source resistance for these
inputs should, in general, be kept below 1 kO. larger values
of source resistance can cause undesired system noise
pickup. Input bypass capacitors, placed from the analog inputs to ground, can reduce system noise pickup but can
create analog scale errors. See section 3.2, 3.3, and 3.4 if
input filtering is to be used.
3.3 Input Bypass Capacitors
Bypass capacitors at the inputs will average the current
spikes noted in 3.2 and cause a DC current to flow through
the output resistances of the analog signal sources. This
charge pumping action is worse for continuous conversions
with the VIN( +) input voltage at full scale. For continuous
conversions with a 1.8 MHz clock frequency with the VIN( + )
3-220
.--------------------------------------------------------------------.~
Functional Description
c(")
....
(Continued)
o
o
4.0 OFFSET AND REFERENCE ADJUSTMENT
4.1 Zero Offset
zero reference voltage at the corresponding "-" input
should then be adjusted to just obtain the OOOHEX 001HEX
code transition.
The full·scale adjustment should be made [with the proper
VIN( -) voltage applied] by forcing a voltage to the VIN( + )
input given by:
The zero error of the AID converter relates to the location
of the first riser of the transfer function and can be mea·
sured by grounding the V( -) input and applying a small
magnitude positive voltage to the V( +) input. Zero error is
the difference between the actual DC input voltage that is
necessary to just cause an output digital code transition
from 00 0000 0000 to 0000000001 and the ideal 112 LSB
value (1/2 LSB = 2.45 mV for VREF = 5.0 Voe!.
The zero of the AID normally does not require adjustment.
However, for cases where VIN(MIN) is not ground and in
reduced span applications (VREF < 5V), an offset adjust·
ment may be desired. The converter can be made to output
an all zero digital code for an arbitrary input by biasing the
AID's VIN( -) input at that voltage. This utilizes the differen·
tial input operation of the AID.
V (+) FS ad] = V
- 1 5 [(VMAX - VMIN)]
IN
MAX·
1024
where VMAX = the high end of the analog input range and
VMIN = the low end (the offset zero) of the analog range.
(Both are ground referenced).
The VREF (or Vee! voltage is then adjusted to provide a
code change from 3FFHEX to 3FEHEX. This completes the
adjustment procedure.
For an example see the Zero-Shift and Span-Adjust circuit
below.
4.2 Full Scale
The full·scale adjustment can be made by applying a differential input voltage that is 1% LSB down from the desired
analog full-scale voltage range and then adjusting the magnitude of the VREF input for a digital output code that is just
changing from 1111111110 to 11 11111111.
5.0 POWER SUPPLIES
Noise spikes on the Vee supply line can cause conversion
errors as the comparator will respond to this noise. A low
inductance tantalum filter capaCitor should be used close to
the converter Vee pin and values of 1 p.F or greater are
recommended. If an unregulated voltage is available in the
system, a separate LM340LAZ-5.0, TO-92, 5V voltage regulator for the converter (and the other analog circuitry) will
greatly reduce digital noise on the Vee supply.
A Single point analog ground that is separate from the logic
ground points should be used. The power supply bypass
capaCitor and the self-clocking capacitor (if used) should
both be returned to the digital ground. Any VREF bypass
capaCitors, analog input filters capacitors, or input signal
shielding should be returned to the analog ground point.
4.3 Adjusting for an Arbitrary Analog
Input Voltage Range
If the analog zero voltage of the AID is shifted away from
ground (for example, to accommodate an analog input signal that does not go to ground), this new zero reference
should be properly adjusted first. A VIN( +) voltage that
equals this deSired zero reference plus 1/2 LSB (where the
LSB is calculated for the desired analog span, 1 LSB =
analog span/1024) is applied to selected "+" input and the
VCC
(5V oc)
I ~r---<>--IVIN(+)
' 'I
VCCt--1----------,
AOC1005
AOC1025
*·1.2k
r---I
I
VREF M,-'-::3V::<'
SETS ZERO
COOE VOLTAGE
2.1k
J-
1/2 LM358
lk
A
+
SETS VOLTAGE SPAN
LM336'2.5'.:j~
330
lk
2 VOC
ZERO AOJ
TL/H/5261-16
Figure 4. Zero-Shift and Span-Adjust (2V :5: VIN :5: 5V)
3-221
~C
....
(")
2
U'I
an
S
....
0
Typical Applications
5V
Q
~
an
20
cs
0
0
....
Vee
ii1i
0
Q
11
c(
12
13
14
15
16
11
18
elK R
Wii
iNfii
19
TRANSDUCER
10k
elK IN
lo·BIT RESOLUTION
OVER
ANALOG INPUT
VOLTAGE RANGE
087
086
085
AOC1D05
V1NI'1
7 >D1FF INPUTS
084
V1NI-1
083
AGNO
082
VREF
081
080
o GNO
10
TUH/5261-13
Handling ± 5V Analog Inputs
Operating with Ratlometrlc Transducera
Vee (5 Yoe)
Vee (5 Voel
Vee
2k
Vee
I---if--IVINI +I
Uk
":'
20k
1k
ZERO
0.7 Vee
lk
10 TURN
TRIM POT
VREF
VlII1-1
AOJ
J1
F
±5V
7.Sk
AGND
V1N(-)
AGND
= 0.15 Vee
TUH/5261-14
TLlH/5261-15
15% of Vee ,; VXDR .: 85% of Vee
TRI-STATE Test Circuits and Waveforms
trH. CL = 10 pF
Vee
DATA :::
OUTPUTS
~:IH
~
GNO - - - - - - " : : : :
TUH/5261-9
1,=20 ns
TUH/5261-7
toH
Vcc
trH. CL = 10 pF
VCC
RL
oH
DATA
OUTPUT
vee
DATA
OUTPUTS
~
--
lOll
VOL
1,=20 ns
TUH/5261-8
3-222
TUH/5281-10
~
Ordering Information
Part Number
Package
Outline
Temperature
Range
....o
Linearity
Error
Part Number
Package
Outline
ADC1005BCN
N20A
ADC1005CCN
N20A
ADC1025BCN
N24C
ADC1025CCN
N24C
ADC1005BCV
V20A
ADC1005CCV
V20A
ADC1025BCV
V28A
ADC1025CCV
V28A
ADC1005BCJ-1
J20A
ADC1005CCJ-1
J20A
ADC1025BCJ-1
J24F
ADC1025CCJ-1
J24F
ADC1005BCJ
J20A
ADC1005CCJ
J20A
ADC1025BCJ
J24F
ADC1025CCJ
J24F
ADC1005BJ
J20A
ADC1005CJ
J20A
ADC1025BJ
J24F
ADC1025CJ
J24F
O'Cto +70'C
±%LSB
- 40'C to + 85'C
-55'C to + 125'C
3-223
Temperature
Range
Linearity
Error
C)
C)
U'1
i>
c
o....
C)
I\)
U'1
O'Cto +70'C
±1 LSB
-40'Cto +85'C
-55'Cto + 125'C
~
C'I
r----------------------------------------------------------------------------,
C'I
.._
g
~
~
..-
National
Semiconductor
CorporaHon
ADC1205/ADC1225 12-Bit Plus Sign
g IlP Compatible AID Converters
c(
General Description
Key Specifications
The ADC1205 and ADC1225 are CMOS, 12-bit plus sign
successive apprOximation AID converters. The 24-pin
ADC1205 outputs the 13'bit data result in two 8-bit bytes,
formatted high-byte first with sign extended. The 28-pin
ADC1225 outputs a 13-bit word in parallel for direct interface to a 16-bit data bus.
• Resolution-12 bits plus sign
• Unearity Error-± Ya LSB and ± 1 LSB
• Conversion Time-100 p.s
Features
Negative numbers are represented in 2's complement data
format. All digital signals are fully TTL and MOS compatible.
A unipolar input (OV to 5V) can be accommodated with a
Single 5V supply, while a bipolar input (-5V to +5V) requires the addition of a 5V negative supply.
•
•
•
•
•
•
The ADC1205B and ADC1225B have a maximum non-linearity over temperature of 0.Q12% of Full Scale, and the
ADC1205C and ADC1225C have a maximum non-linearity
of 0.0224% of Full Scale.
Compatible with all p.Ps
True differential analog voltage inputs
OV to 5V analog voltage range with single 5V supply
TTUMOS input/output compatible
Low power-25 mW max
Standard 24-pin or 28-pin DIP
Connection and Functional Diagrams
Dual-In-Une Package
v-
DIBlTALVa:
\\Itt-)
23
D87/DB12
ANALODGND
"21
D8&/OB12
VA"
2D
OB4!DB12
'9
083/0811
II
DB2/DB10-BYST
17
0811DB9
\\Nt.)
ANALOGVcc
¥O.
,
ADC1.
eLKIN
DBO/D8B
IN
cs
iii Wii
READY
OUT
mTiiS
10
JIii'
I
I
I
I
I
I
Va.
Iil!
"12
fil!iii
READY OUT
¥vet >1
Vc1:
I 1Jjf
I
I
I
I
e!
DIGITAl.
-4",
I
I
085/0B12
Wi!
DIGITALGND
ClK
DSND
r-y------
I
I
SUCCESSIVE
APPROXIMAnDN
REllISTER
TlIH/5676-1
Top View
~'I-l
Dllal-ln-L1ne Package
v-
DlDITAl Vee
ADe1225
..
...
...0
12
DB'
21
DI8
II
11
13
18
DB.
IRT
l'
'$
DID
Top View
ONLY
LADDER
AND
oa:oDER
L~
."...
IlEADYDUT
1
ADCl205
I
I
I
011
.R
TWO BYTE
I
.u
17
AHD
TRl·STATE"
OUTPUT
LATCH
I
DB"
"..
8YTE
SEQUENCER
I
DI12
11
I
I
___________
ADNO
VlEF
I
~--~
ANALOG
Vc1:
TL/H/5676-3
See Ordering Information
TL/H/5676-2
3-224
:J:-
Absolute Maximum Ratings
C
Operating Conditions (Notes 1 & 2)
(Notes 1 & 2)
Temperature Range
ADC1205BCJ, ADC1205CCJ
ADC1225BCJ, ADC1225CCJ
ADC1205BCJ-l, ADC1205CCJ-l
ADC1225BCJ-l, ADC1225CCJ-l
Supply Voltage (DVee and AVeC>
Negative Supply Voltage (V-)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (DVee and AVeC>
6.5V
Negative Supply Voltage (V-)
-15VtoGND
Logic Control Inputs
-0.3Vto +15V
Voltage at Analog Inputs
(V-)-0.3V to Vee+0.3V
[VIN(+), VIN(-)l
Voltage at All Outputs, VREF, Vas
-0.3Vto (Vee+0.3)V
Input Current per Pin
±5mA
Input Current per Package
±20mA
Storage Temperature Range
-65"Cto + 150'C
Package Dissipation at TA = 25'C
875mW
Lead Temp. (Soldering, 10 seconds)
300'C
ESD Susceptibility (Note 12)
800V
TMINS:TAS:TMAX
-40"CS:TAS: + 85'C
Conditions
Typ
(Note 8)
Tested
Design
Limit
Limit
(Note 9) (Note 10)
ADC1205BCJ·1. ADC1205CCJ·1
ADC1225BCJ·1. ADC1225CCJ·1
Design
Tested
Typ
Limit
Limit
(Note 8)
(Note 9)
(Note 10)
Limit
Units
CONVERTER CHARACTERISTICS
Linearity Error
Unipolar Input
ADC1205BCJ, ADC1225BCJ
Range
ADC1205BCJ-l, ADC1225BCJ-l (Note 11)
ADC1205CCJ, ADC1225CCJ
ADC1205CCJ-l, ADC1225CCJ-l
±%
±1
±1
LSB
LSB
LSB
LSB
Unadjusted Zero Error
±2
±2
±2
LSB
±30
±30
±30
LSB
±%
LSB
±%
Unadjusted Positive and Negative Unipolar Input
Full-Scale Error
Range
Unipolar Input
Negative Full-Scale Error
Range, Full
Scale Adj. to
Zero
Linearity Error
Bipolar Input
ADC1205BCJ, ADC1225BCJ
Range
ADC1205BCJ-l, ADC1225BCJ-l (Note 11)
ADC1205CCJ, ADC1225CCJ
ADC1205CCJ-l, ADC1225CCJ-l
±%
±1.5
LSB
LSB
LSB
LSB
±1.5
±1.5
±2
±2
±2
±2
±2
±30
±30
±30
LSB
±2
±2
±2
LSB
±2
Unadjusted Zero ~rror
Bipolar Input
Range
Unadjusted Positive and Negative Bipolar Input
Full-Scale Error
Range
Negative Full-Scale Error
Bipolar Input
Range, Full
Scale Adj. to
Zero
Maximum Gain Temperature
Coefficient
±%
±1
Unipolar Input
Range
LSB
6
15
6
15
ppml"C
Maximum Offset Temperature
Coefficient
0.5
1.5
0.5
1.5
ppm/'C
Minimum VREF Input Resistance
Maximum VREF Input Resistance
4.0
4.0
2
8
3-225
.......
:J:C
O'CS:TAS:70'C
4.5 Voe to 6.0 VDe
-15VtoGND
Electrical Characteristics
Parameter
N
Q
U1
The following specifications apply for DVee = AVec = 5V, VREF = 5V, felK = 1.0 MHz, V- = -5V for bipolar input range, or
V- = GND for unipolar input range unless otherwise specified. Bipolar input range is defined as -5.05V s: VIN(+) s: 5.05V;
-5.05V s: VIN(-) s: 5.05V and IVIN(+) - vIN(-)1 s: 5.05V. Unipolar input range is defined as -0.05V s: VIN(+) s: 5.05V;
-0.05V s: VIN(-) s: 5.05Vand IVIN(+) - vIN(-)1 s: 5.05V. Boldface limits apply from TMIN to TMAX; all other limits TA = TJ
= 25'C (Notes 3, 4, 5, 6, 7).
ADC1205BCJ, ADC1205CCJ
ADC1225BCJ, ADC1225CCJ
o......
4.0
2
2
kfl
4.0
8
8
kfl
o......
N
N
U1
Electrical Characteristics (Continued)
The following specifications apply for DVcc = AVcc = 5V, VREF = 5V, fClK = 1.0 MHz, V- = -5V. for bipolar input range, or
V- = GND for unipolar input range unless otherwise specified. Bipolar input range is defined as -5.05V ,;;: VIN(+) ,;;: 5.05V;
-5.05V ,;;: VIN(-) ,;;: 5.05V and IVIN(+) - vIN(-)1 ,;;: 5.05V. Unipolar input range is defined as -0.05V ,;;: VIN(+) ,;;: 5.05V;
-0.05V ,;;: VIN(-) ,;;: 5.05V and IVIN(+) - vIN(-)1 ,;;: 5.05V. Boldface limits apply from TMIN to TMAX; all other limits TA = TJ
= 25'C (Notes 3, 4, 5, 6, 7).
ADC120SBCJ, ADC120SCCJ
ADC122SBCJ, ADC122SCCJ
Parameter
Conditions
Typ
(Note 8)
Tested
Limit
(Note 9)
Design
Limit
(Note 10)
ADC120SBCJ·1, ADC120SCCJ·1
ADC122SBCJ·1, ADC122SCCJ·1
Typ
(Note 8)
Tested
Limit
(Note 9)
Design
Limit
(Note 10)
GND-0.05
GND-O.OS
Limit
Units
CONVERTER CHARACTERISTICS (Continued)
Minimum Analog Input
Voltage
Maximum Analog Input
Voltage
Unipolar Input
Range
Bipolar Input
Range
Unipolar Input
Range
Bipolar Input
Range
DC Common-Mode Error
Power Supply Sensitivity
GND·O.OS
-VC- 0.05 -Vee- O•OS
V
Vee + 0.05
Vee+ O•OS
V
Vcc+ 0.05
Vce+ 0•05
V
±%
±%
LSB
±%
±%
±%
±%
±%
±%
LSB
lSB
±%
±%
±%
LSB
-Vee- O•OS
Vee + O.OS
Vee+ O•OS
±Ys
V
±%
±Ys
AVec = DVcc=
5V±5%,
V-=-5V±5%
Zero Error
Positive and Negative
Full-Scale Error
Linearity Error
DIGITAL AND DC CHARACTERISTICS
VIN(1), logical "1" Input
Voltage (Min)
Vcc=5.25V,
All Inputs except
ClKIN
2.0
2.0
2.0
V
VIN(O), logical "0" Input
Voltage (Max)
Vcc= 4.75V,
All Inputs except
ClKIN
0.8
0.8
0.8
V
IIN(1), logical "1" Input
Current (Max)
VIN=5V
0.005
1
0.005
1
p.A
IIN(O), logical "0" Input
Current (Max)
VIN=OV
-0.005
-1
-0.005
-1
p.A
VT+ (Min), Minimum PositiveGOing Threshold Voltage
ClKIN
3.1
2.7
3.1
2:7
2.7
V
VT+ (Max), Maximum Positive- ClKIN
Going Threshold Voltage
3.1
3.S
3.1
3.5
3.S
V
VT- (Min), Minimum NegativeGOing Threshold Voltage
ClKIN
1.8
1.4
1.8
1.4
1.4
V
VT- (Max), Maximum Negative- ClKIN
Going Threshold Voltage
1.8
2.1
1.8
2.1
2.1
V
VH(Min), Minimum Hysteresis
[VT+(Min)-VT-(Max)]
ClKIN
1.3
0.6
1.3
0.6
0.6
V
VH(Max), Maximum Hysteresis
[VT+ (Max)-VT-(Min)]
ClKIN
1.3
2.1
1.3
2.1
2.1
V
3-226
):.
Electrical Characteristics
C
(Continued)
The following specifications apply for DVcc = AVcc = SV. VREF = SV. fCLK = 1.0 MHz. V- = -SV for bipolar input range. or
V- = GND for unipolar input range unless otherwise specified. Bipolar input range is defined as -S.OSV ,,;: VIN(+) ,,;: S.OSV;
-S.OSV ,,;: VIN(-) ,,;: S.OSV and IViN(+) - VIN(-)I ,,;: S.OSV. Unipolar input range is defined as -O.OSV ,,;: VIN(+) ,,;: S.OSV;
-O.OSV ,,;: VIN(-) ,,;: S.OSVand IVIN(+) - VIN(-)I ,,;: S.OSV. Boldface limits apply from TMIN to TMAX; all other limits TA = TJ
= 2SoC (Notes 3. 4. S. 6. 7).
ADC1205BCJ. ADC1205CCJ
ADC1225BCJ, ADC1225CCJ
Parameter
Conditions
Typ
(Note 8)
Tested Design
Limit
Limit
(Note 9) (Note 10)
ADC1205BCJ·1, ADC1205CCJ·1
ADC1225BCJ·1, ADC1225CCJ·1
Design
Limit
(Note 10)
2.4
4.5
2.4
4.S
2.4
4.5
V
V
0.4
0.4
0.4
V
DIGITAL AND DC CHARACTERISTICS (Continued)
VOUT(I). Logical "1" Output
Voltage (Min)
Vcc=4.75V
lOUT = - 360 p.A
IOUT= -10 p.A
VOUT(O). Logical "0" Output
Voltage (Max)
Vcc=4.7SV
lOUT = 1.6 mA
lOUT. TRI-STATE Output Leakage VOUT=OV
Current (Max)
VOUT=SV
-0.01
0,01
-3
3
-0.01
0.01
-0.3
0.3
-3
3
p.A
p.A
ISOURCE. Output Source Current
(Min)
VOUT=OV
-12
-6.0
-12
-7.0
-6.0
mA
ISINK. Output Sink Current (Min)
VOUT=5V
16
8.0
16
9.0
8.0
mA
Dicc. DVcc Supply Current (Max) fCLK=1 MHz.CS=1
1
3
1
2.S
3
mA
Aicc. AVcc Supply Current (Max) fCLK=1 MHz.CS=1
1
3
1
2.S
3
mA
1-. V- Supply Current (Max)
10
100
10
100
100
p.A
fCLK=1 MHz.CS=1
AC Electrical Characteristics
The following specifications apply for DVcc=AVcc=S.OV. t r =tl=20 ns and TA=25°C unless otherwise specified.
Parameter
Conditions
Typ
(Note 8)
Tested
Limit
(Note 9)
1.0
1.0
0.3
1.5
Design
Limit
(Note 10)
Limit
Units
fCLK. Clock Frequency
MIN
MAX
Clock Duty Cycle
MIN
MAX
40
60
%
%
T C. Conversion Time
MIN
MAX
MIN
MAX
108
109
108
109
1/fCLK
1/fcLK
p's
p's
fCLK=1.0 MHz
fCLK=1.0MHz
MHz
MHz
220
3S0
ns
tACC. Access Time (Delay from
Falling Edge of RD to
Output Data Valid) (Max)
CL =100pF
210
340
ns
tiH. toH. TRI-STATE Control (Delay
from Rising Edge of RD to
Hi-Z State) (Max)
RL=2k. CL = 100 pF
170
290
ns
tPD(READYOUn. RD or WR to
READYOUT Delay (Max)
2S0
400
ns
tpD(INn.RD or WR to Reset of INT
(Max)
2S0
400
ns
tW(WR)L. WR Pulse Width
MAX
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating ratings.
Note 2: All voltages are measured with respect to ground, unless otherwise specified.
Note 3: A parasitic zener diode exists internally Irom AVec and DVcc to ground. This parasitic zener has a typical breakdown voltage 01 7 Voc.
3-227
N
Q
;;
C
o.....
N
N
U'I
Limit
Units
Tested
Limit
(Note 9)
Typ
(Note 8)
o
.....
AC Electrical Characteristics (Continued)
Note 4: Two on-chip diodes are tied to each analog input as shown below.
DIGITAL Vee
VINI +1 n~i--4--. TO INTERNAL CIRCUITRY
DR YlNI-I
V-
TLlH/5676-4
Errors in the AID conversion can occur If these diodes are forward biased more than 50 mV. This means that If AVec and DVcc are minimum (4.75 Vee> and V- Is
minimum (-4.75Vec), full-scale must be :s; 4.8Vec.
Note 5: A diode exists between analog Vcc and digital Vc.
I
I
AVec
DVee
~
B--l---!-+
TO INTERNAL CIRCUITRY
TO INTERNAL CIRCUITRY
I
I
TL/H/5678-20
To guarantee accuracy, it is required that the AVec and DVcc be connected together to a power supply with separate bypass filters at each Vee pin.
Note 6: A diode exists between analog ground and digital ground.
ANALOG GROUND ~ TO INTERNAL CIRCUITRY
DIGITAL GROUNO
o------t-..
TO INTERNAL CIRCUITRY
TL/H/5678-21
To guarantee accuracy, it is required that the analog ground and digital ground be connected together externally.
Note 7: Accuracy Is guaranteed at fCLK= 1.0 MHz. At higher clock frequencies accuracy may degrade.
Note 8: Typicals are at 25'C and represent most likely parametriC norm.
Note 9: Tested and guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 10: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 11: Linearity error is defined as the deviation of the analog value, expressed In LSBs, from the straight line which passes through positive full scale and zero,
after adjusting zero error. (See Figures Ib and Ie).
Note 12: Human body model; 100 pF discharged through a 1.5 kn resistor.
(4095) 0,1111,1111,1111
(4094) 0,1111,1111,1110
POSITIVE
FULL-SCALE
TRANSITION
w
co
8
~co
+VREF
-VREF
".'"
".'"
",'" '"
".'"
",'"
1,0000,0000,0001 (- 4095)
1,0000,0000,0000 (-4096)
L V E FULL-SCALE TRANSITION
ANALOG INPUT VOLTAGE [VINI +1- VINI-I I
FIGURE 1a. Transfer Characteristic
3-228
TL/H/5676-B
»
c
....o
N
o
U1
.......
»
c
o
....
N
N
U1
-3 LSD
OUTPUT CODE
(FROM - 4096 TO +4095)
TL/H/5676-22
FIGURE 1b. Simplified Error Curve vs. Output Code Without Zero and Fullscale Adjustment
~
ffi
+3 LSD
+2 LSD
NEGATIVE
FULLSCALE
ERROR
I
LINEARITY ERROR
+1 LSD
UNEARITY ERROR
POSITIVE
FULLSCAlf
ERROR
-1 LSD
-2 LSD
-3 LSD
OUTPUT CODE
(FROM - 4096 TO + 4095)
TLlH/5676-23
FIGURE 1c. Simplified Error Curve vs. Output Code after Zero/Fuliscale Adjustment
Vee
....- ...---t- ~~~~UT
Vee
iiii
----il-...II!~~
GNO
Rl
VoH ---~~
DATA OUTPUT
ONO - - - -
#T
Vee
Vee
l
RD
Vee ---+:r.~-
iiii
DATA
OUTPUT
aND
Cl
~
Vee
10%
-toH~
DATA OUTPUT
VOL _ _ _ _..011 10%
TL/H/5676-7
FIGURE 2. TRI-STATE Test Circuits and Waveforms
3·229
U)
C'oI
C'oI
..-
g
~
U)
r---------------------------------------------------------------------------------,
Timing Diagrams
Transfer Characteristic for ADC1205 and ADC1225 Unipolar Input Range and Bipolar Input Range (digital output codes vs the
difference of the analog inputs [ VIN( +) - VIN( -) ])
CI
C'oI
..-
oQ
ClKIN~
CC
/--1-1
~
CS
~
Wi.
00
iiii
--J''--------.11
,,'-_ _
,----------~I~I------------------------------------------------------
'\J~~"~~'===~===:;:::::l
(;
\'-_~k..l~__I---------------
10~
I~I----------------~"----"
OB.------------------------CJ-------c::::>-----HIGH BYTE ON AOC1205
13-BIT DATA ON AOC1225
LOW BYTE ON AOC1205
13·BIT DATA ON AOCl225
Tl/H/5676-15
FIGURE 3. Timing Diagram
iiii OR Wi
READY OUT
TUH/5676-13
FIGURE 4. Ready Out
TLlH/5676-14
FIGURE 5. Data Out
3·230
»
C
l1NOSZZL:lQ\fUO,i
~ ~ ;;: ;;: ;;:
!! iii iii !il Ii i!l
i!!
I
;;:
~
iii
~
~
~
"'I
;0
~
i!i iii iii iii
:;:
2
....
0
N
0
CI1
.....
»
c
....
0
N
N
CI1
r".----IS
I~
i'i
III
r----,;:!
I
I
I
I
!~~+-4---+-------~HH
t;
:;
;1
91
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iii
:
I
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~:
3-231
U) r-------------------------------------------------------------------------------~
N
N
.....
o
c
~o
N
.....
o
C
output buffers. The conversion result is
represented in 2's complement format.
1.2 THE CONVERSION PROCESS (Numbers designated
by [ ] refer to portions of Figure 6.)
The SARS LOGIC [2] controls the A·to·D conversion pro·
cess. When 'sars' goes high the clock (clk) is gated to the
TIMING GENERATOR [9]. One of the outputs of the TIMING GENERATOR, Tz• provides the clock for the Succes·
sive Approximation Register, SAR LOGIC [S]. The Tz clock
rate is Va of the CLK IN frequency.
Inputs to the 12·BIT DAC [111 and control of the SAMPLED
DATA COMPARATOR [10] sign logic are provided by the
SAR LOGIC. The first step in the conversion process is to
set the sign to positive (logic '0') and the input of the DAC to
000 (HEX notation). If the differential input, VIN(+)-VIN(-),
is positive the sign bit will remain low. If it is negative the
sign bit will be set high. Differential inputs of only a few
hundred microvolts are enough to provide full logic swings
at the output of the SAMPLED DATA COMPARATOR.
The ADC120S makes the conversion result available in two
eight-bit bytes. The output format is 2's complement with
extended sign. Data is right justified and presented high
byte first. With CS low and STATUS high, the high byte
(DBI2-DB8) will be enabled on the output buffers the first
time RD goes low. When RD goes Iowa second time, the
low byte (DB7-DBO) will be enabled. On each read opera·
tion, the 'byst' flip·flop is toggled so that on successive
reads alternate bytes will be available on the outputs. The
'byst' flip-flop is always reset to the high byte at the end of a
conversion. Table 1 below shows the data bit locations on
the ADCI20S.
The ADC120S's STATUS pin makes it possible to read the
conversion status and the state of the 'byst' flip-flop. With
RD, STATUS and CS low, this information appears on the
data bus. The 'byst' status appears on pin 18 (DB2/DB10).
A low output on pin 18 indicates that the next data read will
be the high byte. A high output indicates that the next data
read will be the low byte. A high status bit on pin 22 (DB6/
DB12) indicates that the conversion is in progress. A high
output appears on pin 17 (DB1/DB9) when the conversion
is completed and the data has been transferred to the out·
put latch. A high output on pin 16 (DBO/DB8) indicates that
the conversion has been completed and the data is ready to
read. This status bit is reset when a new conversion is initia·
ted, data is read, or status is read. When reading a conver·
sion result, STATUS should always be brought high at least
600 ns before RD goes low. If the conversion status information is not needed, the STATUS pin should be hardwired
to V+. Table 2 summarizes the meanings of the four status
bits.
The sign bit indicates the polarity of the differential input. If it
is set high, the negative input must have been greater than
the positive input. By reversing the polarity of the differential
input, VIN(+) and VIN(-) are interchanged and the DAC
sees the negative input as positive. The input polarity rever·
sal is done digitally by changing the timing on the input sampling switches of the SAMPLED DATA COMPARATOR.
Thus, with almost no additional circuitry, the AID is extended from a unipolar 12-bit to a bipolar 12·bit (12-bit plus sign)
device.
After determining the input polarity, the conversion pro·
ceeds with the successive approximation process. The SAR
LOGIC successively tries each bit of the 12-BIT DAC. The
most Significant bit (MSB), Bll, has a weight of 'h of VREF.
The next bit, Bl0, has a weight of '14 VREF. Each successive
bit is reduced in weight by a factor of 2 which gives the least
significant bit (LSB) a weight of 1/4096 VREF.
When the MSB is tried, the comparator compares the DAC
output, VREF/2, to the analog input. If the analog input is
greater than VREF/2 the comparator tells the SAR LOGIC to
set the MSB. If the analog input is less than VREF/2 the
comparator tells the SAR LOGIC to reset the MSB. On the
next bit-test the DAC output will either be % VREF or '14
VREF depending on whether the MSB was set or not. Fol·
lowing this sequence through for each successive bit will
approximate the analog input to within 1-bit (one part in
4096).
TABLE II. Status Bit Locations and Meanings
On completion of the LSB bit·test the conversion·complete
flip·flop (CC) is set, signifying that the conversion is finished.
The end-of·conversion (EOC) and interrupt (I NT) lines are
not changed at this time. Some internal housekeeping tasks
must be completed before the outside world is notified that
the conversion is finished.
3-232
Status
Bit
Location
Status
Bit
DB6
SARS
"High" indicates that
the conversion is in
progress
DB2
BYST
"Low" indicates that
the next data read is
the high byte.
"High" indicates that
the next data read is
the low byte
Meaning
Condition to
Clear Status
Bit
Status write
or toggle it
with data
read
J:-
Functional Description
(Continued)
TABLE II. Status Bit Locations and Meanings
(Continued)
Status
Status
Bit
Bit
Location
DB 1
DBD
EOC
INT
Condition to
Clear Status
Bit
Meaning
_____f
N
C)
U1
.....
J:-
-
iiiiORWii
"High" indicates that
the conversion is
completed and data is
transferred to the
output latch.
"High" indicates that
it is the end of the
conversion and the
data is ready to read
\
cs
o
o....
o
o
....
N
N
U1
3112T
CC
\.
ilii'
Data read or
status read
or status
write
KEADY
OUT
'1-
""(READY OUTI -
3.0 INTERFACE
'- ,
3.1 RESET OF INTERRUPT
-
tpO(REAOY DUTI
TLlH/5676-10
FIGURE 8. READY OUT Timing Oiagram
INT goes low at the end of the conversion and indicates that
data is transferred to the output latch. By reading data, INT
will be reset to high on the leading edge of the first read (RD
going low). INT is also reset on the leading (falling) edge of
WR when starting a conversion.
3.3 RESETTING THE AID
All the internal logic can be reset, which will abort any conversion in process and reset the status bits. The reset function is achieved by performing a status write (CS, WR and
STATUS are low).
3.2 READY OUT
3.4 ADDITIONAL TIMING AND INTERFACE OPTIONS
To simplify the hardware connection to high speed microprocessors, a READY OUT line is provided. This allows the
A-to-D to insert a wait state in the ,...P's read cycle. The
equivalent circuit and the timing diagram for READY OUT is
shown in Figures 7 and 8.
ADC1225
1. WR and RD can be tied together with CS low continuously or strobed. The previous conversion's data will be
available when the WR and RD are low as shown below.
One drawback is that, since the conversion is started on the
falling edge and the data read on the rising edge of WR/RD,
the first data access will have erroneous information depending on the power-up state of the internal output latches.
CS'RD~
CS'WR
READY OUT
CC
If the WR/RD strobe is longer than the conversion time,
INTR will never go low to Signal the end of a conversion.
The conversion will be completed and the output latches will
be updated. In this case .the READY OUT signal can be
used to sense the end of the conversion since it will go low
when the output latches are being updated.
TL/H/5676-9
FIGURE 7•. READY OUT Equivalent Circuit
I
I
L..J
LJ
~
__________
I
I
I
I
I
I
I
I
~'r--l~
(
______
)
TL/H/5676-24
3-233
Functional Description
cs
(Continued)
-,I ____________ _
~L.._ _ _ _ _ _ _ _ _ _ _
+
WR
f
Rii
INTR
U
READY OUT
(
DATA
(OBO-OB12)
OLD DATA
I
~
TC
TL/H/5676-25
FIGURE 10
cs ---,
WRT
e.
I
L.J
Tc
LJ
Rii
INTR
'Il
READY OUT
c::>
DATA
(OBO-DB12)
TLlH/5676-26
FIGURE 11
cs
WR
L-J
Rii
INTR
U
READY OUT
DATA
(DBO-DB12)
X
OLD DATA
NEW DATA
TL/H/5676-27
FIGURE 12
3·234
»
c
Functional Description (Continued)
o....
cs
ViR
I\)
o
en
.....
! l,
! l,
,
,
"
iID
READY OUT
II
en
,
,
,
,
,
,I
,,
,
I
I
LJ
DATA
(080-0812)
o
....
I\)
I\)
,
,
Tc
,I
,
INTR
»
c
LJ
X
X
OLD DATA
NEW DATA
TL/H/5676-2B
AOCI225
cs
1
~>_
re> -
.!.6 74C
iID
INTR
ViR
READY OUT
Er+~ATA
(080-0812)
+5Vo-- STATUS
TL/H/5676-29
FIGURE 13
When using this method of conversion only one strobe is
necessary and the rising edge of WR/RD can be used to
read the current conversion results. These methods reduce
the throughput time of the conversion since the RD and WR
cycles are combined.
3. Tying CS and RD low continuously and strobing WR to
initiate a conversion will also yield valid data. The INTR will
never go low to signal the end of a conversion and the
digital outputs will always be enabled, so using INTR to
strobe the WR line for a continuous conversion cannot be
done with this part.
2. With the standard timing WR pulse width longer than the
conversion time a conversion is completed but the INTR will
never go low to signal the end of a conversion. The output
latches will be updated and valid information will be available when the RD cycle is accomplished.
cs
I
ViR
L-J
LJ,,
I,, ,,,
11
iID
I
I
INTR
READY OUT
DATA
(080-087)
I
)
(
MOST
SIGNIFICANT
A simple stand-alone circuit can be accomplished by driving
WR with the inverse of the READY OUT signal using a simpie inverter as shown below.
I
I
L-J
,
LJ
,
,
,
I
I
,I
,I
,
I,
,
,
..
I
Tc
"
11
(
)
LEAST
SIGNIFICANT
BYTE
BYTE
FIGURE 14
3-235
TLlH/5676-30
Functional Description (Continued)
ADC1205
Case 1 would be the only one that would appy to the
ADC1205 since two RD strobes are necessary to retrieve
the 13 bits of information on the B bit data bus. Simultaneously strobing WR and RD low will enable the most significant..!Te on DBO-DB7 and start a conversion. Pulsing
WR/RD low before the end of this conversion will enable
the least significant byte of data on the outputs and restart a
conversion.
through the output resistance of the analog signal source.
This charge pumping action is worse for continuous conversions with the VIN( +) input voltage at full-scale. For continuous conversions with a 1 MHz clock frequency and the
VIN(+) input at 5V, the average input current is approximately 5 poA. For this reason bypass capacitors should not be
used at the analog inputs for high resistance sources
(RSOURCE 100 n).
If input bypass capacitors are necessary for noise filtering
and high source resistance is desirable to minimize capacitor
size, the detrimental effects of the voltage drop across this
input resistance, due to the average value of the input current, can be minimized with a full-scale adjustment while the
given source resistance and input bypass capacitor are both
in place. This is effective because the average value of the
input current is a linear function of the differential input voltage.
4.0 REFERENCE VOLTAGE
The voltage applied to the reference input of the converter
defines the voltage span of the analog inputs (the difference
between VIN(+) and VIN(-), over which 4096 positive output codes and 4096 negative output codes exist. The
A-to-D can be used in either ratiometric or absolute reference applications. VREF must be connected to a voltage
source capable of driving the reference input resistance
(typically 4 kO).
In a ratiometric system, the analog input voltage is proportional to the voltage used for the AID reference. When this
voltage is the system power supply, the VREF pin can be
tied to Vcc. This technique relaxes the stability requirement
of the system reference as the analog input and AID reference move together maintaining the same output code for a
given input condition.
For absolute accuracy, where the analog input varies between very specific voltage limits, the reference pin can be
biased with a time and temperature stable voltage source.
In general, the magnitude of the reference voltage will require an initial adjustment to null out full-scale errors.
5.4 INPUT SOURCE RESISTANCE
Large values of source resistance where an input bypass
capacitor is not used, will not cause errors as the input currents settle out prior to the comparison time. If a low pass
filter is required in the system, use a low valued series resistor (R s: 100 n) for a passive RC section or add an op amp
RC active low pass filter. For low source resistance applications, (RSOURCES: 100 n) a 0.001 poF bypass capacitor at
the inputs will prevent pickup due to series lead inductance
of a long wire. A 100 n series resistor can be used to isolate
this capacitor - both the Rand C are placed outside the
feedback loop - from the output of an op amp, if used.
5.5 NOISE
The leads to the analog inputs should be kept as short as
possible to minimize input noise coupling. Both noise and
undesired digital clock coupling to these inputs can cause
errors. Input filtering can be used to reduce the effects of
these sources, but careful note should be taken of sections
5.3 and 5.4 if this route is taken.
5.0 THE ANALOG INPUTS
5.1 DIFFERENTIAL VOLTAGE INPUTS AND COMMON
MODE REJECTION
The differential inputs of the ADC1225 and ADC1205 actually reduce the effects of common-mode input noise, i.e.,
signals common to both VIN(+) and VIN(-) inputs (60 Hz is
most typical). The time interval between sampling the" + "
and" -" input is 4 clock periods. Therefore, a change in the
common-mode voltage during this short time interval may
cause conversion errors. For a sinusoidal common-mode
signal the error would be:
4
VERROR(MAX) = VPEAK (21T fCM) -fClK
where fCM is the frequency of the common-mode signal,
VPEAK is its peak voltage value and fClK is the converter's
clock frequency. In most cases VERROR will not be significant. For a 60 Hz common-mode signal to generate a 1f4
LSB error (300 /LV) with the converter running at 1 MHz its
peak value would have to be 200mV.
6.0 POWEI'I SUPPLIES
Noise spikes on the Vee supply line can cause conversion
errors as the comparator will respond to this noise. Low
inductance tantalum capacitors of 1 /LF or greater are recommended for supply bypassing. Separate bypass caps
should be placed close to the DVcc and AVcc pins. If an
unregulated voltage source is available in the system, a separate LM340LAZ-S.0 voltage regulator for the A-to-D's VCC
(and other analog circuitry) will greatly reduce digital noise
on the supply line.
7.0 ERRORS AND REFERENCE VOLTAGE
ADJUSTMENTS
7.1 ZERO ADJUST
The zero error of the AID converter relates to the location
of the first riser of the transfer function and can be measured by grounding the VIN(-) input and applying a small
magnitude positive voltage to the VIN( +) input. Zero error is
the difference between the actual DC input voltage necessary to just cause an output digital code transition from all
zeroes to 0,0000,0000,0001 and the ideal Yz LSB value (Yz
LSB=0.61 mV for VREF=S Vocl. Zero error can be adjusted as shown in Figu/'9 15. VIN(+) is forced to 0.61 mV, and
VIN(-) is forced to OV. The potentiometer is adjusted until
the digital output code changes from all zeroes to
0,000,0000,0001.
5.2 INPUT CURRENT
Due to the sampling nature of the analog inputs, short duration spikes of current enter the" +" input and exit the" -"
input at the leading clock edges during the actual conversion. These currents decay rapidly and do not cause errors
as the internal comparator is strobed at the end of a clock
period.
5.3 INPUT BYPASS CAPACITORS
Bypass capacitors at the inputs will average the current
spikes mentioned in 5.2 and cause a DC current to flow
3-236
r--------------------------------------------------------------------.~
C
Functional Description (Continued)
tude of the VREF input so that the output code is just changing from 0,1111,1111,1110 to 0,1111,1111,1111.
A simpler, although slightly less accurate, approach is to
ground VIN(+) and VIN(-), and adjust for all zeros at the
output. Error will be well under % LSB if the adjustment is
done so that the potentiometer is "centered" within the
0,000,000 range. A positive voltage at the Vos input will
reduce the output code. The adjustment range is +4 to
-30 LSB.
0.61 mV
0.1
I
V1N(+)
V1N(-)
VREr
Vos
15K
0.1
I
Do the same procedure outlined above for the unipolar case
and then change the differential input voltage so that the
digital output code is just changing from 1,0000,0000,0001
to 1,0000,0000,0000. Record the differential input voltage,
Vx. the ideal differential input voltage for that transition
should be;
( -VF
+.Y.L)
8192
Calculate the difference between Vx and the ideal voltage;
a = Vx - (-VF
200K
+.Y.L)
8192
Then apply a differential input voltage of;
TL1H/5676-11
(Vx -
FIGURE 15. Zero Adjust Circuit
7.2 POSITIVE AND NEGATIVE FUI.L-SCAI.E
ADJUSTMENT
%)
and adjust the magnitude of VREF so the digital output
code is just changing from 1,0000,0000,0001 to
1,0000,0000,0000. That will obtain the positive and negative
full-scale transition with symmetrical minimum error.
Unipolar Inputs
Apply a differential input voltage which is 1.5 LSB below the
desired analog full-scale voltage NF) and adjust the magni-
Typical Applications
-Input must have some
current return path to
signal ground
....
vIN(+1
DVcc
YiNH
AVec
.
•'*
.:
~
V-
YilEF
CI
Wii
AOND
lID
lIlT
HEADY OUT
DONO
OBI
TL/H/5676-12
3-237
~
UI
i;
Bipolar Inputs
+5V
o
....
C
o
....
N
N
UI
~
eN
.....
o
cc(
-
Typical Applications (Continued)
Protecting the Input
I I)
~
.....
Vcc
(5Vocl
g
c(
+
1;'0#
ADC1205
ADC1225
TLfHf5676-16
Diodes are lN914
Operating with Ratlometrlc Transducers
Vec
(5Voc)
4k
VXUR
VINI+)
50D
VIIII-)·
ZERO
ADJ
5DD
'='
AVec
AOCI2D5
+
T O.,",*,0,.F
OVec
3.9lc
ADC1225
'::'
VREF
lk
FS
ADJ
'VIN(-)
= 0.15 Vee
8.2k
15% of Vee ,;: VXDR ,;: 85% of Vee
TLfHf5676-17
3-238
3>
Typical Applications
c
o
....
(Continued)
~
Bipolar Input Temperature Converter
UI
);
C
o
....
5V
N
~
10V
DVec
DVec
I"---...=~ VREF
ADC1205
ADC1225
10V
2.5k
......_ _... c;:SCALE
ADJUST
10k"
TLiH/5676-16
+ 150 to
- SS"C with 0.04"C resolution
Note: • resistors are 1% metal film types
Strain Gauge Converter with .025% Resolution and Single Power Supply
330
10V~~--------~~_____~~__, -__~-
3.3k"
5.tV
ZENER
~-p-t--"----I VREF
DVCC
AVce
ADC1205
ADC1225
TL/H/5676-19
Note: 1)· resistors afe 1% metal film types
2) LF412 power
+ 1OV and ground
3·239
Ordering Information
Temperature Range
Non-Linearity
I
I
OOCto 70"C
- 400C to
+ 85"C
0.012%
ADC1205BCJ-1
ADC1225BCJ-1
ADC1205BCJ
ADC1225BCJ
0.024%
ADC1205CCJ-1
ADC1225CCJ-1
ADC1205CCJ
ADC1225CCJ
J24A
J28A
J24A
J28A
Package Outline
3-240
r----------------------------------------------------------------.~
_
CI
......
~
......o
...
National
Semiconductor
Corporation
o
~
CI
ADC 121 0, ADC 1211 12-Bit CMOS AID Converters
~
General Description
The ADC121 0, ADC1211 are low power, medium speed, 12bit successive approximation, analog-to-digital converters.
The devices are complete converters requiring only the application of a reference voltage and a clock for operation.
Included within the device are the successive approximation
logic, CMOS analog switches, precision laser trimmed thin
film R-2R ladder network and FET input comparator.
Both devices are available in military and industrial temperature ranges.
Features
•
•
•
•
•
•
•
The ADC121 0 offers 12-bit resolution and 12-bit accuracy,
and the ADC1211 offers 12-bit resolution with 1O-bit accuracy. The inverted binary outputs are directly compatible with
CMOS logic. The ADC121 0, ADC1211 will operate over a
wide supply range, convert both bipolar and unipolar analog
inputs, and operate in either a continuous conversion mode
or logic-controlled START-STOP conversion mode. The devices are capable of making a 12-bit conversion in 100 P.s
typ, and can be connected to convert 10 bits in 30 p.s.
12-bit resolution
±% LSB or ±2 LSB nonlinearity
Single + 5V to ± 15V supply range
100 p.s 12-bit, 30 p.s 10-bit conversion rate
CMOS compatible outputs
Bipolar or unipolar analog inputs
200 kG analog input impedance
Block Diagram
Y+(yREFlo;;ZZ._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...._ _- ,
RZ9
ZOk
Al
CLOCK
START
CONYERSION
COMPLETE
D/A &SAR LOGIC
COMPARATOR
OUTPUT
MS8
Z-IZ
RZ&
ZOOk
RZ5
ZOOk
RZ8
ZOk
DIGITAL OUTPUTS
19
18
17
1&
15
Y-
TL/H/5677 -1
Connection Diagram
Dual-In-Llne Package
(LSBI
.-12
CLOCK
2-11
2J COMPARATOR
2-1D
22 .V(VREFI
OUTPUT
Order Number ADC1210HD,
ADC1210HCD, ADC1211HD,
ADC1211HCD
See NS Package D24D
"
" v-
GND
,-I
,-1
'9 H21
,"I
I. HZS
,-.
"
,.
'IN
1& H28
2_3'0
15 HZ7
2-2 II
14
2 1 IZ
13 START (If)
(""
'--------'
TOP VIEW
~~::~~:~O(~I
TLlH/5677 -2
3-241
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Maximum Reference SuppiyVoltage (V+)
16V
Maximum Negative Supply Voltage (V-)
-20V
Voltage At Any logic Pin
V++0.3V
Analog Input Voltage
±15V
Maximum Digital Output Current
±10mA
Maximum Comparator Output Current
50mA
Comparator Output Short·Circuit Duration
5 Seconds
Power Dissipation
See Curves
Operating Temperature Range
ADC121 OHD, ADC1211 HD
- 55'C to + 125'C
ADC1210HCD, Abc1211HCD
- 25'C to + 85'C
Storage Temperature Range
-65'C to + 150'C
lead Temperature (Soldering, 10 seconds)
3000C
ESD Susceptibility (Note 4)
TBDV
DC Electrical Characteristics (Notes 1 and 2)
Parameter
ADt1210
Conditions
Min
Resolution
linearity Error
Typ
ADC1211
Max
12
Min
Bits
Full Scale Error
Zero Scale Error
TA = 25°C, Unadjusted
Quantization Error
Input Resistor Values
Input Resistor Values
R27, R28
20
20
R25, R26
R25/R26, R27/R28
200
200
±0.0488
%FS
%FS
0.20
0.50
0.20
0.50
%FS
%FS
±1/2
lSB
VIN=10.24V
VIN=OV
logic "I" Output Voltage
lOUT s: -1 /LA
logic "0" Output Voltage
IOUTS:l/LA
V+ = 15V, fCLK=65 kHz,
TA=25'C
V-= -15V, TA=25°C
kO
0.8
0.8
8
logic "1" Input Current
logic "0" Input Current
Negative Supply Current
±0.0183
±0.0366
±1/2
logic "I" Input Voltage
logic "0" Input Voltage
Positive Supply Current
Max
12
(Note 3)
fCLK = 65 kHz', TA = 25'C
fCLK=65 kHz
TA= 25'C, Unadjusted
Input Resistor Ratios
Units
Typ
kO
%
8
V
2
2
V
1
-1
1
-1
IlA
0.5
/LA
V
V
5
8
5
8
mA
4
6
4
6
mA
9.2
9.2
0.5
AC Electrical Characteristics TA = 25'C, (Notes 1 and 2)
Parameter
Conditions
Min
Conversion Time
Maximum Clock Frequency
Clock Pulse Width
100
Typ
Max
Units
100
130
200
65
/Ls
kHz
50
ns
Propagation Delay From Clock to Data Output
(00 to Qll)
trs:tfS: 10 ns
60
150
ns
Propagation Delay from Clock to Conversion
trs:tfS: IOns
60
150
ns
5
/Ls
pF
Complete
Clock Rise and Fall Time
Input CapaCitance
10
Start Conversion Set·Up Time
30
ns
Note 1: Unless otherwise noted,these specifications apply for V+ =10.240V, V-= -15V, over the temperature range -SS'C to + 12S'C lor the ADC1210HD,
ADC1211HD, and -2S'C to +8S'C lor the ADC1210HCO, ADCI211HCD.
Note 2: All typical values are lor T" = 2S'C.
Note 3: Unless otherwise noted, this specification applies over the temperature range - 2S'C to + 85'C. Provision Is made to adjust zero scale error to OV and lull·
scale to 10.237SV during testing. Standard linearity test circuit is shown In FigUfB 58.
Note 4: Human body model, 100 pF discharged through a I.S kU resistor.
3·242
.--------------------------------------------------------------------,~
c
Schematic Diagram
o
....
.,.
v-
....
N
"
COMPARATOR
OUTPUT
IS
19
H25
2Dllk
R28
20011
s:!
~
c
o....
IS
R21
2011
RZI
20'"
N
....
....
23
• 24
200k
......--+_
v+IVREFlo.::22+---......>----~---+---...,..
CP
START
CONVERSION
COMPLETE
GNO~
CONTROL
LOGIC
14
TLlH/5677 -3
Note: 3 bits shown for clarity
Power Dissipation vs
Temperature
Supply Current vs
Supply Voltage
2.25
100 Hz ~ IClK ~ jO kHz
TA-2S"C
OJA= &O°CIW
§
1.75
~
1.5
;:
I"\"
I
I-" ~
v'. piN 23 -;t:;~ic "I" I---'" f..--"
v', PIN 23 AT LOGIC:;J!:.
"' "\..
f 1.25
~
is
ffi
It
;0
v
~
0.75
0.50
0.25
o
o
o
25
SO
75
100
125
150
o
10
15
SUPPLY VOLTAGE I'VI
TEMPERATURE (""CI
TL/H/5677-5
TLlH/5677-4
1.0 THEORY OF OPERATION
The AOC1210, AOC1211 are successive approximation analog-to-digital converters, i.e., the conversion takes place 1
bit at a time by comparing the output of the internal 01 A to
the (unknown) input voltage. The START input (pin 13),
when taken low, causes the register to reset synchronously
on the next CLOCK low-to-high transition. The MSB, Q11 is
set to the low state, and the remaining bits, QO through Q10,
will be set to the high state. The register will remain in this
state until the SC input is taken high. When START goes
high, the conversion will begin on the low-to-high transition
of the CLOCK pulse. Q11 will then assume the state of pin
23. If pin 23 is high, Q11 will be high; if pin 23 is low, Q11 will
remain low. At the same time, the next bit Q10 is set low. All
remaining bits, QO-Q9 will remain unchanged (high). This
process will continue until the LSB (QO) is found. When
the conversion process is completed, it is indicated by CONVERSION COMPLETE (CC) (pin 14) going low. The logic
levels at the data output pins (pins 1-12) are the complemented-binary representation of the converted analog signal with Q11 being the MSB and QO being the LSB. The
register will remain in the above state until the SC is again
taken low.
An application example is shown in Figure 1. In this case, a
o to -10.2375V input is being converted using the
AOC1210 with V+ =10.240V, V- = -15V. Figure 1b is the
timing diagram for full scale input. Figure 1c is the timing
diagram for zero scale input, Figure 1dis the timing diagram
for -3.4125V input (010101010101 = output).
3-243
..C'I
.-
o
c
~
.C'I
.-
g
'V(VREFI-IDl4V 0=22+_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.,
R24
CLOCK
START
CONVERSION
COMPLETE
COMPARATOR
OUT
C
o....
10
....
N
Cp
....
l>
«:)
C
o
....
PIN 23
....
....
N
011
010
0'
01
OJ
0&
05
03
OZ
01
DO
L-
cc.--J
f.1--------CDNVERSlDNTIME--------1
TL/H/5677-8
FIGURE 1c. T!:-;;:7011 Diagram for VIN = Zero Scale
Cp
PIN23
011
010
os
08
OJ
06
D.
04
O.
QZ
01
QO.--J
cc~
f-I-------
CONVERSION TIME
TL/H/5877-9
FIGURE 1d. Timing Diagram for VIN= -3.4125V (010101010101)
3-245
..-
TABLE 1. Pin Assignments and Explanations
N
.0
Pin Number
Mnemonic
011(
.....
0
1-12
011-00
Digital (data) output pins. This information is a parailel 12·bit complemented binary representation of the converted analog signal. All data is valid when "Conversion Complete"
goes low. Logic levels are ground and V+.
0
13
SC
Start Conversion is a logic input which causes synchronous reset of the successive
approximation register and initiates conversion. Logic levels are ground and V+.
14
CC
"Conversion Complete" is a digital output signal which indicates the status of the converter. When CC is high, conversion is taking place, when low conversion is completed.
Logic levels are ground and V + .
15,16
R27, R28
R27 and R28 are two application resistors connected to the comparator non-inverting
input. The resistors may be used in various modes of operation. Their nominal values are
20 kO each. See Applications section.
17
+IN
Non-inverting input of the analog comparator. This node is used in various configurations
and for compensation of the loop. See Applications section.
18,19
R25,R26
R25 and R26 are two application resistors that are tied internally to the inverting input of
the comparator. Their nominal values are 200 kO each. See Applications section. The R2R ladder network wiii have the same temperature coefficient as these resistors.
20
V-
Negative supply voltage for bias of the analog comparator. Optionally may be grounded
or operated with voltages to -20V.
21
22
GND
V+(VREF)
Ground for both digital and analog signals.
V+ sets both maximum full scale and input and output logic levels.
23
CO
Comparator output.
24
Cp
Clock is an input which causes the successive approximation (shift) register to advance
through the conversion sequence. Logic levels are ground and V + .
Q
.N
.-
Q
011(
Function
10-bit conversion accuracy is taking place. The 02 output
should be "OR'd" with CONVERSION COMPLETE (CC) in
order to ensure that the register does not lock-up upon power turn-on.
2.0 APPLICATIONS
2.1
Power Supply Considerations and
Decoupllng
~24Y"Y"YZlY"Y"~'Yll~.~,I,~
Pin 22 is both the positive supply and voltage reference
input to the ADC1210, ADC1211. The magnitude of V+ determines the input logic "1" threshold and the output voltage from the CMOS SAR. The device wiii operate over a
range of V + from 5V to 15V. However, in order to preserve
12-bit accuracy, V+ should be well regulated (0.01 %) and
isolated from external switching transients. It is therefore
recommended that pin 22 be decoupled with a 4.7 /LF tantalum capaCitor in parallel with a 0.1 /LF ceramic disc capacitor.
The V- supply (pin 20) provides negative bias for the FET
comparator. Although pin 20 may be grounded in some applications, it must be at least 2V more negative than the
most negative anaiog input signal. When a negative supply
is used, pin 20 should also be bypassed with 4.7 /LF in parallel with 0.1 /LF.
Grounding and circuit layout are extremely important in preserving 12-bit accuracy. The user is advised to employ separate digital and analog returns, and to make these PC
board traces as "heavy" as practical.
2.2 Short Cycle for Improved Conversion
I
co
~,I'14MM7ICOI
ADeIZ"
OD 01 OZ OJ 04
as DB
Q1 08 01 DID 011
l' 'lA4b'l'b7b'b'b"b"i~
DIGITAL OUTPUTS
TL/H/5677-10
FIGURE 2. Short Cycling the ADC1211 to Improve
10-Blt Conversion Time (Continuous Conversion)
2.3 Logic Compatibility
The ADC1210, ADC1211 is intended to interface with
CMOS logic levels: i.e., the logic inputs and outputs are directly compatible with series 54C/74C and CD4000 family
of logic components. The outputs of the ADC1210,
ADC1211 will not drive LPTTL, TTL or PMOS logic directly
without degrading accuracy. Various recommended interface techniques are shown in Figures 3 and 4.
2.4 Operating Configurations
Several recommended operating configurations are shown
in Figure 5.
Time (Figure 2)
The ADC1210, ADC1211 counting sequence may be truncated to decrease conversion time. For example, when using the ADC1211, 2 clock intervals may be "saved" if
3-246
l>
~
....
Applications Information (Continued)
....
~C
o....
....
....
N
N
DIGITAL OUTPUTS
TTL OR 5V CMOS
COMPATIBLE
H&MM14CIOI
ORMM74C9Q2
TLlH/5677-11
> Vee. Example: V+
FIGURE 3. Interfacing an ADC1210, ADC1211 Running on V+
= 10.24V, System Vee =
sv
VCC· 15V
15VJUl
OV SYSTEM 0CLOCK
~
H>-
14
h
.r
Ill">o-t r;: I-I--....+-'-ll-+-o
12
01,
.10 II
L....!!
r-
Cp
: +_
,~I+--H-++o()
~1-I-----4""'-o
V
., I _
01 1 _
MM14CIDI
OR
MM14Claz
OR
'::n :;:
STARTo-
MM14CI06
AOC121D,
ADCI211
--V-.....!!
R
-----"
•. +.4 .;.14 C1:
_
OJ
.!.-
..
r 1-1-1--1-1-1,
I
I/'R~~~;1
L.
~~G~:~
_ _ .J
MM14C9DB
., .!....., .!.....O.!..-
L -......_..J
-¥.
,..
V"o-"""'........
-o
I~ONVERSID
LSI
w
"""
....... COMPLETE
~----~~--------~lQ~
.~
I/SMM74C808
TL/H/5677-12
FIGURE 4. Interfacing an ADC1210, ADC1211 Running on V+
2.S Offset and Full Scale Adjust
< Vee. Example: V+ = SV, Vee = 1SV
puts must be stable logic "0"). Offset Null is accomplished
by then applying an analog input voltage equal to % LSB at
pins 18 and 19. R2 is adjusted until the LSB output flickers
equally between logic "1" and logic "0" (all other bits are
stable). In the circuit of Figure 6. the ADC121 0, ADC1211 is
configured for Complementary Binary logic and the values
shown are for V+ = 10.240V, VFS = 10.2375V,
LSB = 2.5 mY.
A variety of techniques may be employed to adjust Offset
and Full Scale on the ADC121 0, AD.C1211. A straight-forward Full Scale Adjust is to incrementally vary V+ (VREF) to
match the analog input voltage. A recommended technique
is shown in Figure 6. An LM199 and low drift op amp(e.g.,
the LH0044) are used to provide the precision reference.
The ADC1210, ADC1211 is put in the continuous convert
mode by shorting pins 13 and 14. An analog voltage equal
to VREF minus 1% LSB (10.23625V) is applied to pins 18
and 19, and R1 is adjusted until the LSB flickers equally
between logic "1" and logic "0" (all other out-
An alternate technique is shown in Figure 7. In this instance,
an LH0071 is used to provide the reference Voltage. An
analog input voltage equal to VREF minus 1% LSB
(10.23625V) is applied to pins 18 and 19.
3-247
....
....
N
....
o
Applications Information (Continued)
c
....c
....
N
....
---------,
r-
CI
I AQC1ZID,ADC1Z11
... I
~
II
CloeKPULSE
START
CONVERSION
COMPLETE
D/A AND SAA lOGIC
l~,,""T""I'""1r-r""'T"T'"T"""-"'""'TMS.J,
141
~lf,
211
1
3.5
& 7
RU
1125
2n
2n
Rli
19101112
R27
'.
"
ZoOk
;~-~"~~~~DI~ClT~'-L~~~~'-'
OUTPUTS
5V,;V+,;15V
OV,;VIN';V+
Logical "1"'; 0.5V
Logical "0" "'V+
TL/H/5677-13
FIGURE 5a. Single Supply Configuration, Complementary Logic
,...... _ _ _ _ ......2!
-----------,
I ADcnlO,ADC1ZtI
I
,,.
START
It
CONVERSION
EC
COMPLEtE
II
C,
CLOCK PULSE
"I
D/AANOSARLDGIC
l.'::,,:TT'"nn""'T'T""-"'""'T-.,'.
~liD
l11
."2R ."2R
Z
J
4
5
6
1
19101112
'lB
" "
;~-~"-------D1-Cl-T'-L--~~~'-'
""
I
___ -.I
-- "
" "
11
OUTPUTS
C.
":'
ANALOG
INPUT
V+~15.000V
-15V
0,;VIN';10V
Logical "1" :>14V
Logical "0" ,; 0.5V
'.
",.
Nt
-15V
IDOpF
V-~
":'
TLlH/5677-14
FIGURE 5b. High Voltage CMOS Compatible, OV to 10V Input
v+: 10Z4GV
f~~~-------------
,,.
I
I
CLOtKPULSE
c,
START
Ie
fC
CDNVERSION
COMPUTE
II
;-12
X•
OIA AND SAR lOGIC
L"
21'
~
COMPARATOR
.so
/-'
." ." ." ."
2R
,
3 •
5
" ••
DIGITAL
OUTPUTS
1011 1 2 - - -
I
I
I123
COMPARATOR
i"
__ J
;;- ;;- l;;- I;;- n 2R
OUTPUT
lIIDk
20
...............
NC
,
,-I
":' J L
~1
ANALOG
'NPUT
V+~10.24V
-5.12V,;VIN'; +5.12V
Logical "1 "';0.5V
Logical "0""1 OV
"
--l
V+=ID.24V
1
T
,,-
''''''
,0.
""
TLlH/5677-15
FIGURE 5c. Bipolar Input, Complementary Logic
3-248
~
C
Applications Information (Continued)
o
....
....
....
C
o
....
........
N
o
~
N
-15V
TL/H/5677-16
FIGURE 6. Offset and Full Scale Adjustment for Complementary Binary
Rl is adjusted until the LSB output flickers equally between
logic "I" and logic "0" (all other outputs must be a stable
logic "0"). For Offset Null, an analog voltage equal to 1/2
LSB (1.25 mY) is then applied to pins 1Band 19, and R2, is
adjusted until the LSB output flickers equally between logic
"1" and
The circuit insures that in no case can the ADC1210 make
an error in the Most Significant Bit (MSB) decision. Without
the circuit, it is possible for energy from the trailing edge of
an asynchronous START pulse to be coupled into the
ADC1210's comparator. If the analog input is near halfscale, the charge injected can force an error in the MSB
decision. The circuit allows one clock period for this energy
to dissipate before the decision is recorded.
"on.
INPUT VOLTAGE
{DV TO lU31SVI
15V
-15V
2.7 ADC1210 CONVERSION AT 26 fLs
The ADC121 0 can run at 500 kHz clock frequency, or 12-bit
conversion time of 26 fLs (Figure 9). The comparator output
is clamped low until the successive approximation register
(SAR) is ready to strobe in the data at the rising edge of the
conversion clock. Comparator oscillation is suppressed and
kept from influencing the conversion decisions, eliminating
the need for the AC hysteresis circuit above clock frequency
of 65 kHz that is recommended.
CLOCK
-15V
TL/H/5677-17
FIGURE 7. Offset and Full-Scale Adjustment
Technique Using LH0071
CLOCK
-1---------..:'::j'
V
Cp
011
MS.
5V
In both techniques shown, adjusting the Full·Scale first and
then Offset minimizes adjustment interaction. At least one
iteration is recommended as a self·check.
ADC1Zl0
DIGITAL
• OUTPUT
COUT
2.6 START PULSE CONSIDERATIONS
To assure reliable conversion accuracy, the START (SC)
pulse applied to pin 13 of the ADC1210 should be synchro·
nized to the conversion clock. One simple way to do that is
the circuit shown in Figure 8. Note that once a conversion
cycle is initiated, the START signal cannot effect the conversion operation until it is completed.
r.:-----1~....... V+I\tAEFI
"
..
'SI
TL/H/5677-18
FIGURE 9. Conversion at 26 fLs
A complementary phased clock is required. The positive
phase is used to clock the converter SAR as is normally the
case. The same signal is buffered and inverted by the transistor. The open collector is wire-ORed to the output of the
comparator. During the first half of the clock cycle (50%
duty cycle), the comparator output is clamped and disabled,
though its internal operation is still in normal working order.
The last half cycle of the clock unclamps the comparator
output. Thus, the output is permitted to slew to the final logic
state just before the decision is logged into the SAR. The
MM74C906 buffer (or with two inverting buffers) provides
adequate propogation delay such that the comparator output data is held long enough to resolve any internal logic
setup time requirements.
ADC1.l'tI
TUH/5677 -19
FIGURE 8. Synchronizing the START Pulse
3-249
.,..
.,..
N
.,..
~.,...,..
N
o
c
c
Applications Information
(Continued)
The 500 kHz clock implies that the absolute minimum
amount of time for the comparator output is unclamped is 1
p,s. Therefore, if the clock is not 50% duty cycle, this 1 p,s
requirement must be observed.
Zero Scale Error (or Offset): Zero Scale Error is a measure of the difference between the output of an ideal and
the actual AID for zero input voltage. As shown in Figure
12, the effect of Zero Scale Error is to shift the transfer
characteristic to the right or left along the abscissa. Any
voltage more negative than the LSB transition gives an output code of 000. In practice, therefore, the voltage at which
the 000 to 001 transition takes place is ascertained, this
input voltage's departure from the ideal value is defined as
the Zero Scale Error (Offset) and is expressed as a percentage of FS. In the example of Figure 12, the offset is 2 LSB's
or 0.286% of FS.
3.0 DEFINITION OF TERMS
Resolution: The Resolution of an AID is an expression of
the smallest change in input which will increment (or decrement) the output from one code to the next adjacent code. It
is defined in number of bits, or 1 part in 2". The ADC121 0
and ADC1211 have a resolution of 12 bits or 1 part in 4,096
(0.0244%).
Quantlzatlon.Uncertalnty: Quantization Uncertainty is a direct consequence of the resolution of the converter. All analog voltages within a given range are represented by a single digital output code. There is, therefore, an inherent conversion error even for a perfect AID. As an example, the
transfer characteristic of a perfect 3-bit AID is shown in
Figure 10.
e
I
'"
5a
RESPONSE
WITH OFFSET
'01
ID'
.11
IDEAL
RESPONSE
'"
~E~s~;Cs1L:~~RDIR
DO'
DO'
-2 -I
:-
I-RANGE
I
Z
3
4
5
G
1
•
TL/H/5677-21
FIGURE 10. Quantization Uncertainty
of a Perfect 3-Blt AID
,
iULL~CAh
B ,,
1,00
11
01
DI
-
,
I
i
TL/H/5677-20
2
3
4
&
&
ANALOG INPUT VOLTAGE
Uti
010
k:L
lD'I"Lj,spr"rI
DO'
.~, I- '12 LSI .FFSET I I
1
~
CI
~
DO
o
-"
IDa
II U~IRA'I'MIi"D1t"T
,
"
7 I
GAi,26:
,hRDh-
8 ::~
~ 101
II
10
~
5 &
Full Scale Error (or Gain Error): Full Scale Error is a measure of the difference between the output of an ideal AID
converter and the actual AID for an input voltage equal to
full scale. As shown in Figure 13, the Full Scale Error effect
is to rotate the transfer characteristic angularly about the
origin. Any voltage more positive than the Full Scale transition gives an output code of 111. In practice, therefore, the
voltage at which the transition from 111 to 110 occurs is
ascertained. The input voltage's departure from the ideal
value is defined as Full Scale Error and is expressed as a
percentage of FS. In the example of Figure 13, Full Scale
Error is 1 1/2 LSB's or 0.214% of FS.
As can be seen, all input voltages between OV and 1V are
represented by an output code of 000. All input voltages
between 1V and 2V are represented by an output code of
001, etc. If the midpoint of the range is assumed to be the
nominal value (e.g., 0.5V), there is an Uncertainty of ± 1/2
LSB. It is common practice to offset the converter 1/2 LSB
in order to reduce the Uncertainty to ± 1/2 LSB is shown in
Figure 11, rather than + 1, - 0 'shown in Figure 10. Quantization Uncertainty can only be reduced by increasing Resolution. It is expressed as ± 1/2 LSB or as an error percentage of full scale (±0.0122% FS for the ADC1210).
a
3 4
The Zero Scale Error of the ADC121 0, ADC1211 is caused
primarily by offset voltage in the comparator. Because it is
common practice to offset the AID 1/2 LSB to minimize
Quantization Error, the offsetting techniques described in
the Applications Section may be used to null Zero Scale
Error and accomplish the 1/2 LSB offset at the same time.
ZERO SCALE
D
ANALOG INPUT VOLTAGE
11
2
FIGURE 12. AID Transfer Characteristic with Offset
10.
'DD
0 1
ANALOG INPUT VOLTAGE
10'
,01
;;
~
11D
ia '"01'
~
111
11.
FuiLSC~LE I-
RANGE-ILSB
~
0
0
II
7
8
.1
.1
DO.
1
2
J
4
5
G
7
ANAlOG INPUT VOLTAGE
TL/H/5677-22
B
•
TL/H/5677-23
FIGURE 13. Full Scale (Gain Error)
FIGURE 11. Transfer Characteristic Offset
112 LSB to Minimize Quantizing Uncertainty
Full Scale Error of the ADC1210, ADC1211 is due primarily
to mismatch in the R-2R ladder equivalent output impedance and input resistors R25, R26, R27, and R28. The gain
error may be adjusted to zero as outlined in section 2.5.
Linearity Error: Linearity Error is the maximum deviation
from a straight line passing through the end pOints of the
AID transfer characteristic. It is measured after calibrating
Zero and Full Scale Error. Linearity is a performance characteristic intrinsic to the device and cannot be externally
adjusted.
3-250
r--------------------------------------------------------------------,~
Applications Information
o
o
(Continued)
Monotoniclty and Missing Codes: Monotonicity is a property of a DI A which requires an increasing or constant output voltage for an increasing digital input code. Monotonicity
of a DI A converter does not, in itself, guarantee that an AID
built with that DI A will not have missing codes. However,
the ADC1210 and ADC1211 are guaranteed to have no
missing codes.
modifying the hysteresis network around the comparator,
conversions with 10-bit accuracy can be made in 30 p.s.
Replace RA, Rs and CA in Figure 5 with a 10 Mn resistor
between pin 23 (Comparator Output) and pin 17 (+ IN), and
increase the clock rate to 366 kHz.
In order to prevent errors during conversion, the analog input voltage should not be allowed to change by more than
± 1/2 LSB. This places a maximum slew rate of 12.5 p.V1p's
on the analog input voltage. The usual solution to this restriction is to place a Sample and Hold In front of the AID.
For additional application information, refer to application
note AN245.
Conversion Time: The ADC1210, ADC1211 are successive approximation AID converters requiring 13 clock intervals for a conversion to specified accuracy for the ADC121 0
and 11 clocks for the ADC1211. There is a trade-off between accuracy and clock frequency due to settling time of
the ladder and propagation delay through the comparator. By
3-251
-0.
~
-0.
s:!
~
g
-0.
~
-0.
-0.
..- r--------------------------------------------------------------------------------.
....
NatiOnal
PRELIMINARY
g ~ Semiconductor
C')
~
..-
Corporation
5
ADC3511 3%-Digit Microprocessor C;ompatible AID
.
~ Converter
ADC3711 3314-Digit Microprocessor Compatible AID
Converter
General Description
The ADC3511 and ADC3711 (MM74C937, MM74C93B-1)
monolithic AID converter circuits are manufactured using
standard complementary MOS (CMOS) technology. A pulse
modulation analog-to-digital conversion technique is used
and requires no external precision components. In addition,
this technique allows the use of a reference voltage that is
the same polarity as the input voltage.
One 5V (TTL) power supply is required. Operating with an
isolated supply allows the conversion of positive as well as
negative voltages. The sign of the input voltage Is automatically determined and indicated on the sign pin. If the power
supply is not isolated, only one polarity of voltage may be
converted.
The conversion rate is set by an internal oscillator. The frequency of the oscillator can be set by an external RC network or the oscillator can be driven from an external frequency source. When using the external RC network, a
square wave output is available.
The ADC3511 and ADC3711 have been designed to provide addressed BCD data and are intended for use with
microprocessors and other digital systems. BCD digits are
selected on demand via 2 Digit Select (00,01) inputs. Digit
Select inputs are latched by a low-to-high transition on the
Digit Latch Enable (OLE) input and will remain latched as
long as OLE remains high. A start conversion input and a
conversion complete output are included on both the
ADC3511 and the ADC3711.
Features
•
•
•
•
•
•
•
•
•
•
Operates from single 5V supply
ADC3511 converts 0 to ± 1999 counts
ADC3711 converts 0 to ± 3999 counts
Addressed BCD outputs
No external precision components necessary
Easily interfaced to microprocessors or other digital
systems
Medium speed-200 ms/conversion
TTL compatible
Internal clock set with RC network or driven externally
Overflow indicated by hex "EEEE" output reading as
well as an overflow output
Applications
• Low cost analog-to-digital converter
• Eliminate analog multiplexing by using remote
AI 0 converters
• Convert analog transducers (temperature, pressure, displacement, etc.) to digital transducers
Connection Diagram
Dual-In-Llne Package
VCC ...l
U
~21
~20
ANALOG VCC ..l
r!!- VSS
22..1
..!
~Dl
OVERFLOW....!.
~DO
23
~OLE
CONVERSION COMPLETE ..!
~fDUT
START CONVERSION ..2.
~flN
SIGN..!
~VREF
VmTER ..!
~SWI
VINH.!!!.
~SW2
VIN(+I..l!.
VFB Jl
Order Number ADC3511CCN
or ADC3711CCN
NS Package N24A
..!!. ANALOG GNO
TOP VIEW
3-252
TL/H/5678-1
Absolute Maximum Ratings (Note 1)
If MllltarylAerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Voltage at Any Pin
Operating Temperature Range (TA)
Package Dissipation at TA = 25·C
Absolute Maximum Vee
Storage Temperature Range
Lead Temp. (Soldering, 10 seconds)
ESD Susceptibility (Note 5)
-0.3V to Vee +0.3V
-40·Cto +85·C
500mW
Operating Vee Range
6.5V
-65·C to + 150·C
260·C
TBDV
4.5Vt06.0V
DC Electrical Characteristics
ADC3511 CC, ADC3711 CC
4.75V,;:Vee';:5.25V, -40·C,;:TA';: + 85·C, unless otherwise specified.
Symbol
Parameter
Conditions
Typ
(Note 2)
Min
Max
Units
VIN(l)
Logical "1" Input Voltage
(Except fiN)
VIN(O)
Logical "0" Input Voltage
(Except fiN)
VIN(l)
Logical "1" Input Voltage
(fiN)
VIN(O)
Logical "0" Input Voltage
(fiN)
VOUT(l)
Logical "1" Output Voltage
(Except 20,21, 22, 23)
10=360 iotA
Vee- O.4
V
VOUT(l)
Logical "1" Output Voltage
(20,21,22,23)
10=360 iotA
Vee- 1.O
V
VOUT(O)
Logical "0" Output Voltage
lo=1.6mA
IIN(l)
Logical "1" Input Current
(SC, DLE, DO, Dl)
VIN=Vee
IIN(O)
Logical "0" Input Current
(SC, DLE, ~O, Dl)
VIN=OV
ICC
Supply Current
All Outputs Open
V
Vee- 1.5
V
1.5
V
Vee- 0.6
0.6
0.005
-1.0
V
0.4
V
1.0
ILA
-0.005
0.5
iotA
5.0
rnA
AC Electrical Characteristics AOC3511 CC, ADC3711 CC
Vec=5V; TA=25·C, CL =50 pF; t r =t,=20 ns; unless otherwise specified.
Symbol
Parameter
fose
Oscillator Frequency
fiN
Clock Frequency
feONV
Conversion Rate
tsCPW
Start Conversion Pulse Width
tpdO, tpdl
Propagation Delay
DO, 01, to 20, 21, 22, 2 3
tpdO, tpd1
Propagation Delay
OLE to 2 0, 2 1, 22, 23
tSET-UP
Set-UpTime
~O, 01, to OLE
tpWOLE
Minimum Pulse Width
Digit Latch Enable (Low)
Conditions
Min
Typ
(Note 2)
Max
0.6/RC
100
AOC3511CC
AOC3711CC
tHOLO=O ns
3-253
Hz
640
kHz
conversions/sec
conversions/sec
fIN/64,512
fIN/129,024
200
DLE=OV
Units
DC
ns
2.0
5.0
lots
2.0
5.0
ILs
100
200
ns
100
200
ns
EI
..- r-----------------------------------------------------------------------------------------------,
r...;
~
..-
Converter Characteristics ADC3511CC, ADC3711CC 4.75:;;;Vcc:;;;5.25V; -40"C:;;;TA:;;; + 85"C,
f c =5 conv.lsec (ADC3511CC); 2.5 conv.lsec (ADC3711CC); unless otherwise specified.
Symbol
Parameter
Units
±0.025
+0.05
-1
-0.5
+1.0
+0
+3.0
-0
-5
±1
+0
+5
% of Full-Scale
(Note 3)
Counts
mV
(Note 4)
Counts
nA
Min
V'N=0-2V Full Scale
Y,N = 0-200 mV Full Scale
-0.05
an
~
Non-Linearity
Quantization Error
Offset Error
V'N=OV
Rollo.ver Error
Analog Input Current
TA=25"C
Typ
Max
Conditions
(Note 2)
Note 1: Absolute Maximum Ratingslndlca1e limits beyond which damage 10 the device may occur. DC and AC electrical specifications do not apply when opereting
the device beyond lis specifled opereting conditions.
Note 2: All typicals are given for TA= 25'C.
Note 3: For the ADC3511CC: full·scale=1999 counts: therefore 0.025% of full-scale=Yz count and 0.05% of full-scale = 1 count. For the ADC3711CC: fullscale = 3999 counts; therefore 0.025% of full-scaie= 1 count and 0.05% of full-scaie=2 count.
Nate 4: For full-scaie=2.000V: 1 mV=1 count for the ADC3511CC: 1 mV=2 counts for the ADC3711CC.
Nate 5: Human body model, 100 pF discharged through a 1.50 resistor.
Block Diagram
ADC3511 3 YrDlglt AID (0 ADC3711 3 %-Digit AID)
1---1)><>-_,1
STARTCDNV
1&:4
MU'
ROMBtD
DECODER
I--I~><>--+"
DIGITAL TIMING
FREDIN
AND CONtROL
DO
rD'
1:4
DECODER
FREGOUT
D.
103
OLE
10.
COMPARATOR
TIMING
+
GND "'--Vss
..
DIGITAL Vee ~-+--+-------
..
ANALOG Vee ~--+--+-------
---+-+--.......,
ROM
1--______________________________+ OVERFLOW
1--_________________________________ CONY COMPLETE
'-------------------------------------+ &lGN
.00
YFILTER
OVERFLOW
------
r-+----_----I~.VR"
I=1Lsw.
•M
./--<1--+--\-----4........-----------------------------........... -VR"
v"
~--------I
TUH/5678-2
3-254
»
c
Applications Information
oCo)
....
UI
THEORY OF OPERATION
A schematic for the analog loop is shown in Figure 1. The
output of SW1 is either at VREF or zero volts, depending on
the state of the D flip-flop. If Q is at a high level,
VOUT=VREF and if Q is at a low level VOUT=OV. This voltage is then applied to the low pass filter comprised of R1
and C1. The output of this filter, VFB, is connected to the
negative input of the comparator, where it is compared to
the analog input voltage, VIN. The output of the comparator
is connected to the D input of the D flip-flop. Information is
then transferred from the D input to the Q and Q outputs on
the positive edge of clock. This loop forms an oscillator
whose duty cycle is precisely related to the analog input
voltage, VIN.
An example will demonstrate this relationship. Assume the
input voltage is equal to 0.500V. If the Q output of the D flipflop is high then VOUT will equal VREF (2.000V) and VFB will
charge toward 2V with a time constant equal to R1C1. At
some time VFB will exceed 0.500V and the comparator output will switch to OV. At the next clock rising edge the Q
output of the D flip-flop will switch to ground, causing VOUT
to switch to OV. At this time, VFB will start discharging
toward OV with a time constant R1C1. When VFB is less
than 0.5V the comparator output will switch high. On the
rising edge of the next clock the Q output of the D flip-flop
will switch high and the process will repeat. There exists at
the output of SW1 a square wave pulse train with positive
amplitude VREF and negative amplitude OV.
The DC value of this pulse train is:
tON
= VREF (duty cycle)
tON + tOFF
The lowpass filter will pass the DC value and then:
VOUT = VREF
VFB=VREF (duty cycle)
Since the closed loop system will always force VFB to equal
VIN, we can then say that:
VIN=VFB=VREF (duty cycle)
or
VVIN = (duty cycle)
REF
The duty cycle is logically ANDed with the input frequency
fiN. The resultant frequency f equals:
f=(duty cycle) X (fIN)
Frequency f is accumulated by counter no. 1 for a time determined by counter no. 2. The count contained in counter
no. 1 is then:
f
_(dutycycle)X(fIN)
) _
(
count - (fIN)1N (fIN)1N
= VIN X N
VREF
For the ADC3511 N = 2000.
For the ADC3711 N = 4000.
o
flip·
flOP
fiN
0--"'-+.
L--_
COUNTER
_
NO.1
_(+N)
_....I+--+-RESET
COUNTER NO.2 (+2N)
TL/H/5678-3
V'N~VFB~VREFX(duty
cycle)
f=(duty cycle)XI,N
.
__
I __ (duty cycle) x fiN _ ~ x N
Count In counter no. 1 - (f'N)/N (fIN)1N
- VREF
FIGURE 1_ Analog Loop Schematic Pulse Modulation AID Converter
3-255
....»....
c
o
.........
Co)
....
~
~
r...
CO)
o
Q
>G.
C(z z:E
t-O 0 0
Cl')Y u u
"!!.n°
23 22 21 20 01 DO OLE
tl
»
"n°
"2-
5V
-
I»
l....L.l0l'F
1"+r-l0VOC
....
vcc
21~
ioo.-
ANALOG VCC
2° !---
22
23
AOC3511CC
(ADC3711CC)
OVERflOW
''""
01
SIGN
(Xl
VSS
D1
00
CONVERSION
COMPLETE
START
CONVERSION
OLE
&7;.5k
'_OUT
·VVV
ir
250 pF
fiN
lOOk
O'~~I'F1-
NOTE 3 - r -
VREF
VFILTER
VINH
SWI
VIN(+)
SW2
ANALOG
r - - VFB
lOOk
-~
T 0.47 I'F
NOTE 3
GND
0°
2V REFERENCE
r . - - - - """--I
f--
-" ~3&
'YO
200
I
I
I
I
I
I 232 ±1% •
I 20.
I
~
'"""J/~~
~
II
1
gJ
3-
s·
c
.eo'"
I
lN914~
I
~ I r- tI
, }~G ~ ,
I
L __
til
I
I
I
'> 680
}
,1000 ±1%'
::::J
lOki
lN914 ~
~
"""--"""-- I-.J
,
I
I
I
r++:
omETI
ADJUST
;. lOOk
~
>50k
I
I
I
I
L_ I--.J
>22M
Note l:A resistors % watt, and
±5%, unl ess otherwise specified.
Note 2: A capacitors±10%.
Note 3: L
Note 4: R
IW
leakage capacitor.
R1R2
Rl + R2
~---±25n.
GND
TlIH/5678-8
FIGURE 4. 3 Yo-Digit AID; + 1999 Counts, + 2.000 Volts Full Scale
(3 %-Digit AID; + 3999 Counts, + 2.000 Volts Full Scale)
z
2",
~
~
~
~
=...
......
.....
....
co
"0
~ m
en CI
5i
Uc.J
g'
23 2Z Zl zO DI DO DLE
t
,..---_---I
1
:J>
"0
r
r----------+++-+-I--------....- - - -.....~I
LM309
LM~:0.5
-1
T"'Ir
1....I-1DI'F
,
+
1-:- ..... 10VDC
+
2V REFERENCE
..... 1-- VCC
~
ANALDG VCC
ZO
AOC3511CC
Vss
&...----123
(AOC3711CCI
Dl
OVERFLOW
OLE
c.>
COMPLETE
CD
START
CONVERSION
fOUT
-~~---1SIGN
......
..
V,NH
.
~~
:~~p~ ~
I---
DO
_-+_____.....jCONVERSION
roU1
r - - - . f- -
211-
- - - - t 2Z
"""-----1
"2-
,....
I
_•
fiN
t
I
I
I
I
I
I'
.lA5!. - ~I
Z~OPF'
y
V,NH
51k
VIN(+I .....JVV\t-+---IV,N(+1
SWI
'~~A
SW2
ZOO
::~t~g
r - VFB
,•
232"%>
~ I~~
!'~ "
10,0:
}
Ir ,
IN914"
'_ ~
RI
20)0
"}
LM336
,
G~
,'.,4 ~
>10k I
r
_I-
,
L. -
omETI
ADJUST,
• lOOk
,
R2
__
-~
iE
en
'§
~
"
!
I
, .
I
r- 15V DC:
-
0'
:J
I
,•
1000 "%.
R3
~ 1000 pF
·
I
' I
~
r++:~
VREF
-
I
I
I
'>680
I
VFILTER
+.'
- ~ I pF
- , T'OVDC
g'
-I- -
I
50k
-I- -I
L..~ -
•
IN914 ~r
'-~
-I- -
"h watt, and
±5%,unl, 55 otherwise specified.
Note 1: AI resistors
capacitors±10%.
,Note2:AI
Note 3: Lc IW leakage capacitor.
I
I
Nole 4: R: --~±
Rl + R2 250.
~
>22M
_~~~---~yW'y~~n~---~\\
T:·~~~~
1
\'---__
-----J
TLlH/567B-6
FIGURE 5. 3 %-Diglt AID; ± 1999 Counts, ± 2.000 Volts Full Scale
(3 %-Digit AID; ± 3999 Counts, ± 2.000 Volts Full Scale)
~~
iii
LeOOVI ~ ~ seoov
ADC3511/ADC3711
zz
;J
=~=
II: 11: . .
"g"
,..WI&I-,
~~~Ii
,..0
eCi
MU ULI
Z
!:!
23 22 21 20 01 DO OLE
rn
----~tl
VCC
21~
20~
_t______
123
A0C35I1CC
(AOC3711CC)
....-----tIOVERFLDW
-tICONVERSION
COMPLETE
~~~~RSION
Cf'
SIGN
I\J
~
vssl
11 I
001......- -.....
OLEI~---'"
O
rL
·5k
'IN
VIN(_) "'-"\I""~r--"""1
R3
51k
VIN(+)
I
swlt-I--"'I
~VFB
lOOk tl%
_ ~4_
~ ~n;
I
I
swzl--iVV\r-4
VIN(+)
680
I
I
I
I
Note 1: All resistors Yo watt, and
± 5%, unless otherwise speci-
: 232 tl"
250 pF
VREFI
51k
I
I
I
I
I
OIl---
'OUT
jE
s
r---- --,
2V REFERENCE
ANALOGVCC
...._-'"'1 22
l..
:I>
OFFSET'
ADJUST
I
I
RI
~~<
;i~RZ
roz:"-v_
lOki
I
I
J
I
l..
22M
f
_.J
fied.
Note 2: All capacitors ± 10%
Note 3: low leakage capacitor.
R1R2
Note 4: Ra ~ Rl + R2 ±50n
Note 5: R4 ~ 900k ± 1% for the
ADC3511CC, 200.0 mV FullScale.
R4~400k±l% for the
ADC3711 CC, 400.0 mV FullScale.
'~_---.J
TlIH/567B-7
FIGURE 6. 3 %-Diglt AID; ± 1999 Counts, ±200.0 mY Full Scale
(3 %-Digit AID; ± 3999 Counts, ± 400.0 mY Full-Scale)
""2~
0"
:::s
en
g>
a
:::I
c:
e
l>
C
C
NatiOnal
~ Semiconductor
Co)
UI
....
Q
Corporation
ADD3501 3% Digit DVM with
Multiplexed 7-Segment Output
General Description
Features
The ADD3501 monolithic DVM circuit is manufactured using
standard complementary MOS (CMOS) technology. A pulse
modulation analog-to-digital conversion technique is used
and requires no external precision components. In addition,
this technique allows the use of a reference voltage that is
the same polarity as the input voltage.
•
•
•
•
•
•
•
•
•
One 5V (TTL) power supply is required. Operating with an
isolated supply allows the conversion of positive as well as
negative voltages. The sign of the input voltage is automatically determined and output on the sign pin. If the power
supply is not isolated, only one polarity of voltage may be
converted.
The conversion rate is set by an internal oscillator. The frequency of the oscillator can be set by an external RC network or the oscillator can be driven from an external frequency source. When using the external RC network, a
square wave output is available. It is important to note that
great care has been taken to synchronize digit multiplexing
with the AID conversion timing to eliminate noise due to
power supply transients.
The ADD3501 has been designed to drive 7-segment multiplexed LED displays directly with the aid of external digit
buffers and segment resistors. Under condition of overrange, the overflow output will go high and the display will
read + OFL or -OFL, depending on whether the input voltage is positive or negative. In addition to this, the most significant digit is blanked when zero.
A start conversion input and a conversion complete output
are included on all 4 versions of this product.
Operates from single 5V supply
Converts OV to ± 1.999V
Multiplexed 7-segment
Drives segments directly
No external precision component necessary
Accuracy specified over temperature
Medium speed - 200ms/conversion
Internal clock set with RC network or driven externally
Overrange Indicated by +OFL or -OFL display reading and OFLO output
• Analog inputs in applications shown can withstand
±200 Volts
Applications
•
•
•
•
Low cost digital power supply readouts .
Low cost digital multimeters
Low cost digital panel meters
Eliminate analog multiplexing by using remote AID converters
• Convert analog transducers (temperature, pressure, displacement, etc.) to digital transducers
Connection Diagram
Vee ANALOG Vee -
I
2
2B""" S,
27 - Sf
Sd- 3
S, 4
26'-S,
25 .... GND
Sb -
5
24 I- DIGIT I IMSDI
S, -
6
23,..... DIGIT2
OFLO CONVERSION COMPLETE START CONVERSION _
7
B
9
SIGN -
10
19 I - fiN
VmTER VINI-I -
11
12
IB
VREF
111- SWI
ADD3501
r
VINI+I_ 13
VFB -
22 r- DIGIT 3
21 I - DIGIT 4 ILSDI
20 r- lOUT
161- SW2
L
14 -_ _ _ _--'
lSI- ANALOG GNO
TL/H/5681-1
Order Number ADD3501CCN
See NS Package Number N28B
3-261
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage at Any Pin
-0.3VtoVcc +0.3V
Operating Temperature Range (TA)
-40·Cto +85·C
ESD Susceptibility (Note 3)
TBDV
Package Dissipation at TA = 25·C
derate at 6JA(MAX) = 125·C/Watt
above TA= 25·C
800mW
Operating Vce Range
Absolute Maximum Vee
Lead Temp. (Soldering, 10 seconds)
Storage Temperature Range
4.5Vt06.0V
6.5V
2600C
- 65·C to + 1500C
Electrical Characteristics ADD3501
4.75V:s: Vce :s: 5.25V, -400C :s: TA :s: +B5°C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ(2)
Max
Units
1.5
V
0.4
V
0.4
V
V
VIN(I)
Logical "1" Input Voltage
VINCO)
Logical "0" Input Voltage
VOUT(O)
Logical "0" Output Voltage
(All Digital Outputs except
Digit Outputs)
10=1.1 mA
VOUT(O)
Logical "0" Output Voltage
(Digit Outputs)
10=0.7mA
VOUT(I)
Logical "1" Output Voltage
(All Segment Outputs)
10=50 mA@TJ=25·CVcc=5V
10=30 mA@TJ=1000C
Vcc- 1.6
Vcc- 1.6
VOUT(I)
Logical "1" Output Voltage
(All Digital Outputs except
Segment Outputs)
10 = 500/LA (Digit Outputs)
10 = 360/LA (Conv. Complete,
+ 1-, 0110 Outputs)
Vec- 0.4
V
ISOURCE
Output Source Current
(Digit Outputs)
VOUT=1.0V
2.0
mA
IIN(I)
Logical "1" Input Current
(Start Conversion)
VIN=1.5V
IIN(O)
Logical "0" Input Current
(Start Conversion)
VIN=OV
IcC
Supply Current
Segments and Digits Open
fose
Oscillator Frequency
fiN
Clock Frequency
fe
Conversion Rate
fMUX
Digit Mux Rate
tBLANK
Inter Digit Blanking Time
Vcc- 1.5
V
V
Vcc- 1.3
Vcc- 1.3
1.0
-1.0
/LA
/LA
0.5
10
kHz
0.6/RC
100
mA
640
kHz
fIN/64,512
conv.lsec
flN/256
Hz
1/(32fMUX>
sec
Start Conversion Pulse Width
200
DC
ns
tscpw
Note 1: Absolute Maximum Ratings Indicate IImHs beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond Its specified operating conditions.
Note 2: All typicals given for TA = 25"C.
Note 3: Human body model, 100 pF discharged through a 1.5 kfl resistor.
3-262
»
c
Electrical Characteristics ADD3501
tC=5 conversions/second,
0°C~TA~70°C,
Co)
U1
0
.....
Conditions
Min
Typ
Max
Units
V'N=0-2V Full Scale
V'N=O-200mV Full Scale
-0.05
-0.05
±0.025
±0.025
+0.05
+0.05
%of
full scale
+0
counts
+3
mV
+0
counts
+5
nA
Parameter
Non-Linearity
c
unless otherwise specified.
-1
Quantization Error
Offset Error, V,N = OV
-0.5
Rollover Error
-0
Analog Input Current
(V,N+, V'N-)
-5
+1.5
±0.5
Block Diagram
ADD3501 3Y.-Digit DVM Block Diagram
3%·DlIII1
LATCH
Al;-
r--
~
C1~
01 ~
r--r--f---r---
B2f-
-
Bl
A21--+
LSD
I---
e2r-D2r--f---A3r-B3r-e3r-D3r--_-
STARTCOOV_
.......
' •• 0 1 0 _
DIGITAL TIMING
B. . . .
AND CONTROL
C4.....
MSD
16:4
MUX
- >--r--
~L..r-r~
-
1D11-----I--=-~>+++_-lK++_--r~
...........-~- DIGIT 1 IMSD)
lD21-----t----1-t-tt---1r-t-t-r.H-)o-h
.... .a--.
I
~I)c
' •• 0 O U T _
10'
DIGITOLAOK
COMPARATOR
TIMING
GNO~vSS
100
VFlLT.A
---+-+----,
r ;:....+-'1
1 ........
-I--I+HI--+-I+
'V,N _
......
LI
1"""1 I
I ::: I
-V,O
rr;;r
I-----+----i-+++---il-t+. . . . ~
--
'""--r
eOMPAAA~~
,_ . /
Vi
OIGI13
- . . . DIGIT 4 (LSDI
OVERflOW ROM_
YL------------------....
L-_
_________________
L-__________________
.....
- - - l l - K - - - -........
ANALOG V e e _ - - - - I - + - - - - 4
01G1T2
tb:r~
~
+
OIGlTAL Vee
~::::
103
~~---------------__I ~
OV.RFlOW
CDNVCOMPLETE
SlGN
VAEF
'U-SWI
~SW2
I
0
~I-_ _ _ _ _ _ _ _ _ _ _ _ _- I
-
. . . .~---CANALOGGNO
_--'+-I.±+:Hf--....+---~---------------------L_::...J
VFB _ - - - - - - -....
TL/H/5681-2
3-263
~
~
8
~
r------------------------------------------------------------------------------------------,
Theory of Operation
A schematic for the analog loop is shown in Figure 1. The
output of SW1 is either at VREF or zero volts, depending on
the state of the D flip-flop. If Q is at a high level
VOUT=VREF and if Q is at a low level VOUT=OV. This voltage is then applied to the low pass filter comprised of R1
and C1. The output of this filter, VFB, is connected to the
negative input of the comparator, where it is compared to
the analog input voltage, VIN. The output of the comparator
is connected to the D input of the D flip-flop. Information is
then transferred from the D input to the Q and Q outputs on
the positive edge of clock. This loop forms an oscillator
whose duty cycle is precisely related to the analog input
voltage, VIN.
The lowpass filter will pass the DC value and then:
VFB = VREF(duty cycle)
Since the closed loop system will always force VFB to equal
VIN, we can then say that:
VIN = VFB = VREF(duty cycle)
or
VVIN = (duty cycle)
REF
The duty cycle is logically ANDed with the Input frequency
fiN. The resultant frequency f equals:
An example will demonstrate this relationship. Assume the
input voltage is equal to 0.500V. If the Q output of the D flipflop is high then VOUT will equal VREF (2.000V) and VFB will
charge toward 2V with a time constant equal to R1Cl. At
some time VFB will exceed 0.500V and the comparator output will switch to OV. At the next clock riSing edge the Q
output of the D flip-flop will switch to ground, causing VOUT
to switch to OV. At this time VFB will start discharging toward
OV with a time constant R1C1. When VFB is less than 0.5V
the comparator output will switch high. On the rising edge of
the next clock the Q output of the D flip-flop will switch high
and the process will repeat. There exists at the output of
SW1 a square wave pulse train with positive amplitude VREF
and negative amplitude OV.
f = (duty cycle) x (clock)
Frequency f is accumulated by counter no. 1 for a time determined by counter no. 2. The count contained in counter
no. 1 is then:
(duty cycle) x (clock)
(clock)/N
f
(count) = (clock)/N
= VIN XN
VREF
For the ADD3501, N = 2000.
The DC value of this pulse train is:
TON
VOUT= VREF(T
)=VREF(dutycycle)
ION+ OFF
Schematic Diagram
IINQ--...._
..
RESET
TL/H/5681-3
1- (duty cycle) x liN
Count in Counter No. 1
liNIN
(dutycycle)xlln VIN XN
liNIN
VREF
Figure 1. Analog Loop Schematic
Pulse Modulation AID Converter
3-264
»
c
General Information
c
The timing diagram, shown in Figure 2, gives operation for
the free running mode. Free running operation is obtained
by connecting the Start Conversion input to logic "I" (Vecl.
In this mode the analog input is continuously converted and
the display is updated at a rate equal to 64,512 x I/fiN.
The rising edge of the Conversion Complete output indicates that new information has been transferred from the
internal counter to the display latch. This information will
remain in the display latch until the next low-to-high transition of the Conversion Complete output. A logic "I" will be
maintained on the Conversion Complete output for a time
equal to 64 x I/fiN.
Figure 3 gives the operation using the Start Conversion input. It is important to note that the Start Conversion input
and Conversion Complete output do not influence the actual
analog-to-digital conversion in any way.
Internally the ADD3501 is always continuously converting
the analog voltage present at its inputs. The Start Conversion input is used to control the transfer of information from
the internal counter to the display latch.
An RS latch on the Start Conversion input allows a broad
range of input pulse widths to be used on this signal. As
shown in Figure 3, the Conversion Complete output goes to
a logic "0" on the rising edge of the Start Conversion pulse
and goes to a logic "I" some time later when the new conversion is transferred from the internal counter to the display latch. Since the Start Conversion pulse can occur at
any time during the conversion cycle, the amount of time
from Start Conversion to Conversion Complete will vary.
The maximum time is 64,512Xl/fiN and the minimum time
is 256 x I/fiN.
Timing Waveforms
fiN
.fiR
r:
"'.-0-----------
I - - - - - - - - - - 6 4 , 5 1 2 x I/flN
64,000 x lIflN
•
-------i.~1
r--
CONVERSION CYCLE - - - - - - - - - - - - - - - - - - - - ' .
(INTERNAL SIGNAL)
~
1.
0----------- 64,256 x l/fIN-------~I-t
I
r-64/f1N
nL___
CONVERSION
r -
w~mr
NEW
CONVERSION
CONVERSION
ENDS
I
ST7TS
TUH/S681-4
Figure 2. Conversion Cycle Timing Diagram for Free Running Operation
----------"'U
CONVERSION CYCLE
(INTERNAL SIGNAill
r-,
n
START CDNVERSIDN...·_....._.....
u
.-.
L ____!'--...
! ________________
i
CONVERSION
r------~
COMPLETE - - - - - - - ...
- -------TL/H/5681-5
Figure 3. Conversion Cycle Timing Diagram Operating with Start Conversion Input
3-265
Co)
U1
o.....
_ r-----------------------------------------------------------------------------,
C)
&I)
C")
c
c
cc
Applications
SYSTEM DESIGN CONSIDERATIONS
Perhaps the most important thing to consider when designing a system using the ADD3501 is power supply noise on
the Vee and ground lines. Because a single power supply is
used and currents in the 300 mA range are being switched,
good circuit layout techniques cannot be overemphasized.
Great care has been exercised in the design of the
ADD3501 to minimize these problems but poor printed circuit layout can negate these features.
Figures 4, 5, and 6 show schematics of DVM systems. An
attempt has been made to show, on these schematics, the
proper distribution for ground and Vee. To help isolate digital and analog portions of the circuit, the analog Vee and
ground have been separated from the digital Vee and
ground. Care must be taken to eliminate high current from
flowing in the analog Vee and ground wires. The most effective method of accomplishing this is to use a single ground
point and a single Vee point where all wires are brought
together. In addition to this the conductors must be of sufficient size to prevent significant voltage drops.
To prevent switching noise from causing jitter problems, a
voltage regulator with good high frequency response is necessary. The LM309 and the LM340-5 voltage regulators
both function well and are shown in Figures 4, 5, and 6.
Adding more filtering than is shown will in general increase
the jitter rather than decrease it. The most important characteristic of transients on the Vee line is the duration of the
transient and not its amplitude.
Figure 4 shows a DPM system which converts OV to 1.999V
operating from a non-isolated power supply. In this configuration the sign output could be + (logic "1") or - (logic
"0") and it should be ignored. Higher voltages could be converted by placing a fixed divider on the input; lower voltages
could be converted by placing a fixed divider on the feedback, as shown in Figure 6.
Figures 5 and 6 show systems operating with an isolated
supply that will convert positive and negative inputs. 60 Hz
common mode input becomes a problem in this configuration and a transformer with an electrostatic shield between
primary and secondary windings is shown. The necessity for
using a shielded transformer depends on the performance
requirements and the actual application.
The filter capacitors connected to VFB (pin 14) and VFLT
(pin 11) should be low leakage. In the application examples
shown every 1.0nA of leakage current will cause O.lmV error (1.0X 10- 9 Ax 100ko'=0.lmV). if the leakage current in
both capacitors is exactly the same no error will result since
the source impedances driving them are matched.
(
3-266
NSB5388
8-45n
...-.=
r:; .l/l-1 l-I l-/r--t"VVV't"
>IV
_____......--1
3DOmA
j •i __________•
2V REFERENCE
!
LM34IJ.5
~lr'N914
-~
i
O.I.F
I
T
'
I
F-{
I R
L~l09
10k
T!;'~: I ~"N914
1
'-.
I
I
I
IfiOt
Y
fiOt
I
R2
I
L....-
I
232 1
~kl.1
-"I
1
~ ~). ~).
OSI5492
A
A
Vss
U L
L-======:::-t--i---1r---t---t------j
--"
115 ..
~=
f';s
~
Q~
18
11
I
:;:
~
~
18
z
20
21
go
r
I
~~--C'"1200n~MR31 2510~->1.5k
I
I
I
IL ______ -.JI
22Mn
I
~LM:: r;r';~1 I --d A ~ ~
~ ~
[ ------ h
~
r:
voe l -f-"
POWERGNO
(,)
820,-
~ 1l=ll:=l1I:=1.
' ' ' '"
I
r
1
I
;;
,r;::::==1
22
;;
23
;;
-t::j::j
~
A
N
lOOk
24
25
~
f:
::::j
Q
28
G
21
-
128
..
ADD3501
~~~~~15)
i
s
SIGNAL
GNO
IIT~~I
$
~
::;
i14
m
$
<
=!.
;!!
~13 ~12~1I
*
en
iii
jl0
n~ ~n
~~
I:
~~
~:
g
c
;!!
;1
Os
Vs
14
~3
~
~
n2
;1
Ll~~i~~~
11
L---------f-I
I
131
0.4M
lOOk
: ~ ~I~DC
~----------------+-------------------~
VIN
OVTO
+UIIV
TL/H/5681-6
NOTES:
1. ALL RESISTORS
'I. WATT
± 5% UNLESS OTHERWISE
SPECIFIED.
2. ALL CAPACITORS ±10%.
3. LOW LEAKAGE CAPACITOR REQUIRED.
4. R1R2
Rl+ R2
Figure 4. 3%-0Igit OPM,
~R3±25n
+ 1.999 Volts Full Scale
~os£aa\f
III
ADD3501
12011
NSB53BB
'"~
IX>
ADD35D1
GUARD
vc...
GVTI[J:!:1.999V
NOTES:
VI-)
_ 5% UNLESS OTHERWISE
1. ALL RESISTORS '/.4. WAIT +
SPECIFIED.
2. ALL CAPACITORS ± 10%.
3. LOW LEAKAGE CAPACITOR REQUIRED.
R,R2
4.--~R3±2511
R,+ R2
Figure 5. 3'h-Digit DPM, ± 1.999 Volts Full Scale
TLlH/56BI-7
120n
NSB5388
r--
JJO
hIT
31 ....
..-------------,I
f--4 __-...:2:..;V:..:R,;:;EFERENCE
LMJ09
DR
I
LM34I).5
I
232 1
,\%1
1..:0
0515492
lr-l9 A 11
Iii , . II >
~f~
~~25tt;r
~ ~
I
~
-pr
I
\klr
'1%i
~25DO
.F
T'5VDC
.---
I
,
I
Co>
150k
~
ADJUST
90>
!. 01%
lOOk
»------'
"
"'.. OffSET
.-J
GUARD
I
v55
SDk
,
co
"
L~
il
22 . - - -
MIl
r1il &'iltr!1' I II J
2V
0- vlOV
a
~
", ,
dol ,~,..
90.
I'"
.
HT~ . .
100k~.Ol%
~>
,
TLlH/5681-8
R,R2
4.--=R3±2Sfl
R,+R2
Figure 6. 3%-Digit DVM, Four Decade, ± O.2V, ± 2V, ± 20V and
± 200V Full Scale
~os£aa"
1;1
....
~
8
(II)
c(
_NatiOnal
Semiconductor
Corporation
ADD3701 3% Digit DVM with Multiplexed 7-Segment
Output
General Description
Features
The ADD3701 (MM74C936-1) monolithic DVM circuit is
manufactured using standard complementary MOS (CMOS)
technology. A pulse modulation analog-to-digital conversion
technique is used and requires no' external precision components. In addition, this technique allows the use of a reference voltage that is the same polarity as the input voltage.
•
•
•
•
•
•
•
•
•
One 5V (TTL) power supply is required. Operating with an
isolated supply allows the conversion of positive as well as
negative voltages. The sign of the input voltage is automatically determined and output on the sign pin. If the power
supply is not isolated, only one polarity of voltage may be
converted.
The conversion rate is set by an internal oscillator. The frequency of the oscillator can be set by an external RC network or the oscillator can be driven from an external frequency source. When using the external RC network, a
square wave output is available. It is important to note that
great care has been taken to synchronize digit multiplexing
with the AID conversion timing to eliminate noise due to
power supply transients.
The ADD3701 has been designed to drive 7-segment multiplexed LED displays directly with the aid of external digit
buffers and segment resistors. Under condition of overrange, the overflow output will go high and the display will
read + OFL or -OFL, depending on whether the input voltage is positive or negative. In addition to this, the most significant digit is blanked when zero.
Operates from single 5V supply
Converts 0 to ± 3999 counts
Multiplexed 7-segment
Drives segments directly
No external precision components necessary
Accuracy specified over temperature
Medium speed - 400 ms/conversion
Internal clock set with RC network or driven extemally
Overrange indicated by +OFL or -OFL display reading and OFLO output
• Analog inputs in applications shown can 'withstand
±200 Volts
Applications
•
•
•
•
Low cost digital power supply readouts
Low cost digital multimeters
Low cost digital panel meters
Eliminate analog multiplexing by using remote AID converters
• Convert analog transducers (temperature, pressure, displacement, etc.) to digital transducers
• Indicators and displays requiring readout up to 3999
counts
A start conversion input and a conversion complete output
are included.
Connection Diagram
VCC- I
ANALOG VCC- Z
s.-
s..-
3
4
Sb- 5
s,- 8
OFLO- 7
CONVERSION COMPLETE -
8
START CONVERSION -
9
ADD3701
zgt-s.
Z7t'-st
Z&t-SI
Z5t'-GND
24t'-OIGIT IIMSO)
Z3 t ' - DIGIT2
ZZt'-DIGIT3
ZI ~ DIGIT 4ILSO)
za~fOUT
SIGN- 10
19~IIN
VFlLTER- 11
18!-VREF
VINH- IZ
17~SWI
VINI+)- 13
1& i--SWZ
15 -ANALOG GNO
VFB- 14
TL/H/5682-1
Order Number ADD3701CCN
See NS Package Number N28B
3-270
Absolute Maximum Ratings
l>
C
(Note 1)
C
Co)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage at Any Pin except
Start Conversion
Operating Temperature Range (TA)
Package Dissipation at T A = 25'C
- 0.3V to + 15.0V
ESD Susceptibility (Note 5)
TBDV
800mW
4.5Vt06.0V
Operating Vcc Range
Absolute Maximum Vcc
-O.3Vto Vcc+0.3V
Voltage at Start Conversion
-40'Cto + 85'C
6.5V
Lead Temp. (Soldering, 10 seconds)
Storage Temperature Range
260'C
- 65'C to
+ 150'C
Electrical Characteristics
4.75VS;VccS;5.25V, -40'CS;TAS; + 85'C, unless otherwise specified.
Parameter
VIN(l)
Logical "1" Input Voltage
VIN(O)
Logical "0" Input Voltage
VOUT(O)
Logical "0" Output Voltage
(All Digital Outputs Except
Digital Outputs)
VOUT(O)
Conditions
Min
Typ2
Max
Units
V
Vcc- 1.5
.
1.5
V
10=1.1 mA
0.4
V
Logical "0" Output Voltage
(Digit Outputs)
10=0.7mA
0.4
V
VOUT(l)
Logical "1 " Output Voltage
(All Segment Outputs)
10=50 mA@TJ=25'CVcc=5V
10=30 mA@ TJ= 100'C
Vcc- 1.6
Vcc- 1.6
VOUT(l)
Logical "1" Output Voltage
(All Digital Outputs Except
Segment Outputs)
10 = 500 p.A (Digit Outputs)
10=360 p.A (Conv. Complete,
+ /-, OFLO Outputs)
Vcc- 0.4
V
ISOURCE
Output Source Current
(Digital Outputs)
VOUT=1.0V
2.0
mA
IIN(l)
Logical "1 " Input Current
(Start Conversion)
VIN=15V
IIN(O)
Logical "0" Input Current
(Start Conversion)
VIN=OV
Icc
Supply Current
Segments and Digits Open
fosc
Oscillator Frequency
fiN
Clock Frequency
fc
Conversion Rate
fMUX
Digit Mux Rate
tBLANK
Inter Digit Blanking Time
V
V
Vcc- 1.3
Vcc- 1.3
1.0
p.A
-1.0
p.A
0.5
10
mA
0.6/RC
kHz
kHz
640
100
f1N/129,024
conv.lsec
flN/512
Hz
1/(32fMUX)
seconds
Start Conversion Pulse Width
200
DC
ns
tscpw
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All typicals given for TA = 25'C.
Note 3: Full scale = 4000 counts; therefore 0.025% of full scale =1 count and 0.05% of full scale = 2 counts.
Note 4: For 2.000 Volts full scale, 1 mV=2 counts.
Note 5: Human body model, 100 pF discharged through a 1.5 kO resistor.
:,.
3-271
c:l
....
Electrical Characteristics (Continued)
tc;= 2.5 conversions/second, O'CS:TAS: + 70"C, unless otherwise specified.
Parameter
Conditions
Min
Typ2
Max
Units
Non-Linearity of Output
Reading
VIN=0-2V Full Scale
VIN=0-200 mV Full Scale
-0.05
-0.05
±0.025
±0.025
±0.05
±0.05
% full scale
(Note 3)
-1
Quantization Error
-0.5
Offset Error, VIN = OV
+1.5
-0
Rollover Error
Analog Input Current
(VIN+, VIN-)
-5
TA=25'C
±1
+0
counts
+3
mV(Note4)
+0
counts
+5
nA
Block Diagram
ADD37013o/4-Digit DVM
.
3%-0161T
~
"j+
,~
j+
DI~
LSD
CI
srARTCDNV_
.Z~
-
BZj+'
czfDZrA3~
-
B3
C3 f -
DIGITAL TIMING
AND CONTROL
'REDI._
MSD
'-IDC
~
...
ROM
1&:4
MU.
I
SEGMENT
DECODER
H>o-.~
-,r
"'"-
......
'--
6:" :::.
101
DIGITILANk
COMPARATQR
TIMING
....
......
IDZ
,....--L-,
+
-
~7
GND ""'--Vss
--s"
H>o-.s.
::r'" :::
=':::'
r-r---
..
r1>-s.
,.---
103
'REDDUT_
S.
~
"'"-
D3~ ' - -
......
....
'----
j+'
A4f•• f ccr-
r--
------
OVERFLOW
ROM
--
-
....
So
DIGIT 1 (MSD)
DIGIT!
0lGI13
DlGIT4(LSDI
OVERFLOW
DIGITAL Vee
CONY COMPLETE
SIGN
I.
,..---
ANALOGYCC
VFlLTER
+VIN
C
r ~1
~I<
1 .... 1
-V,."
I
l..r.L'
.!..
L __
.J
CVRE'
0
SWI
+ .....
CDMP'RA~ l>- •
J~:LD
~~
••••
V,a
TL/H/5682-2
3-272
"Theory of Operation
A schematic for the analog loop is shown in Figure 1. The
output of SW1 is either at VREF or zero volts, depending on
the state of the D flip-flop. If Q is at a high level,
VOUT=VREF and if Q is at a low level VOUT=OV. This voltage is then applied to the low pass filter comprised of R1
and C1. The output of this filter, VFB, is connected to the
negative input of the comparator, where it is compared to
the analog input voltage, VIN. The output of the comparator
is connected to the D input of the D flip-flop. Information is
then transferred from the D input to the Q and Q outputs on
the positive edge of clock. This loop forms an oscillator
whose duty cycle is precisely related to the analog input
voltage, VIN.
An example will demonstrate this relationship. Assume the
input voltage is equal to 0.500 V. If the Q output of the D flipflop is high then VOUT will equal VREF (2.000 V) and VFB will
charge toward 2 V with a time constant equal to R1C1. At
some time VFB will exceed 0.500 V and the comparator
output will switch to OV. At the next clock rising edge the Q
output of the D flip-flop will switch to ground, causing VOUT
to switch to OV. At this time VFB will start discharging toward
OV with a time constant R1C1. When VFB is less than 0.5 V
the comparator output will switch high. On the rising edge of
the next clock the Q output of the D flip-flop will switch high
and the process will repeat. There exists at the output of
SW1 a square wave pulse train with positive amplitude VREF
and negative amplitude OV.
The DC value of this pulse train is:
VOUT=VREF
toN
toN+tOFF
The lowpass filter will pass the DC value and then:
VFB=VREF (duty cycle)
Since the closed loop system will always force VFB to equal
VIN, we can then say that:
VIN=VFB=VREF (duty cycle)
or
VVIN = (duty cycle)
REF
The duty cycle is logically ANDed with the input frequency
fiN. The resultant frequency f equals:
f = (duty cycle) x (clock)
Frequency f is accumulated by counter no. 1 for a time determined by counter no. 2. The count contained in counter
no. 1 is then:
f
(duty cycle) x (clock)
(count) (clock)/N
(clock)/N
= VIN xN
VREF
For the ADD3701 N = 4000.
VREF (duty cycle)
Schematic Diagram
liN
0--+-...
RESET
TL/H/5682-3
VIN = VFB = VREF x (duty cycle)
1= (duty cycle)xllN
Count in Counter No.1
I
liNIN
(dutycycle)xIIN VIN
liNIN
VREF x N
FIGURE 1_ Analog Loop Schematic Pulse Modulation AID Converter
3-273
~ r-----------------------------------------------------~----------------------------------_,
~
Q
Q
cc
General Information
The timing diagram, shown in Figure 2, gives operation for
the free running mode. Free running operation is obtained
by connecting the Start Conversion input to logic "1" (Vcel.
In this mode the analog input is continuously converted and
the display is updated at a rate equal to 129,024 x 1/f,N.
The rising edge of the Conversion Comple\e output indicates that new information has been transferred from the
internal coiJnter to the display latch. This information will
remain in the display latch until the next low-to-high transition of the Conversion Complete output. A logic "1" will be
maintained on the Conversion Complete output for a time
equal to 128 x 1/f,N.
Figure 3 gives the operation using the Start Conversion input. It is important to note that the Start Conversion input
and Conversion Complete output do not influence the aclual
analog-to-digital conversion in any way.
Internally the ADD3701 is always continuously converting
the analog voltage present at its input. The Start Conversion
input is used to control the transfer of information from the
internal counter to the display latch.
An RS latch on the Start Conversion input allows a broad
range of input pulse widths to be used on this signal. As
shown in Figure 3, the Conversion Complete output goes to
a logic "0" on the rising edge of the Start Conversion pulse
and goes to a logic "1" some time later when the new conversion is transferred from the internal' counter to the display latch. Since the Start Convllrsion pulse can occur at
any time during the conversion cycle, the amount of time
from Start Conversion to Conversion Complete will vary.
The \Y1aximum time is 129,024 X 1IfIN and the minimum time
is 512X 1If,N.
Timing Waveforms
'IN
1Ul
r:
--------------"Z9.QZ4 x
'"'N
"I
"'.--------------,Za.oOO'II'IN---------"1
CONVERSION CYCLE - - - - - - - - - - - - - - - - - - - , .
(INTERNAL SIGNAL)
L--J. - - - -
r---------------
CONVERSION
COMPLETE
1ZS•51Z x ""N-------------i~'i-+I
l-
'ZSf'lN
~
f
t
I
CONVERSION
NEW
CONVERSION
STARTS
ENDS
TL/H/5682-4
FIGURE 2. COrlverslon Cycle Timing Diagram for Free Running Operation
U,..--------u
CONVERSION CYCLE .....- - - - - - - - . . ,
(INTERNAL SIGNAill
.
n
-~
START CONVERSION:,.'...........
_..
i
.-.
...._ _..
'--.'_ _ _ _ _ _ _ _ _ _ _ _ _ __
CONVERSION
J.r_-_-_-_-_-_-..;~
COMPLETE - - - - - - - -
__
_I
TLlH/5682-5
FIGURE 3. Conversion Cycle Timing Diagram Operating with Start Conversion Input
3-274
3>
C
C
Applications
Co)
.....
SYSTEM DESIGN CONSIDERATIONS
....
Q
Perhaps the most important thing to consider when designing a system using the ADD3701 is power supply noise on
the Vee and ground lines. Because a single power supply is
used and currents in the 300 rnA range are being switched,
good circuit layout techniques cannot be overemphasized.
Great care has been exercised in the design of the
ADD3701 to minimize these problems but poor printed circuit layout can negate these features.
The most important characteristics of transients on the Vee
line is the duration of the transient and not its amplitude.
Figure 4 shows a DPM system which converts 0 to + 3.999
counts operating from a non-isolated power supply. In this
configuration the sign output could be + (logic "1 ") or (logiC "0") and it should be ignored. Higher voltages could
be converted by placing a fixed divider on the input; lower
voltages could be converted by placing a fixed divider on
the feedback, as shown in Figure 5.
Figures 4, 5, and 6 show schematics of DVM systems. An
attempt has been made to show, on these schematics, the
proper distribution for ground and Vee. To help isolate digital and analog portions of the circuit, the analog Vee and
ground have been separated from the digital Vee and
ground. Care must be taken to eliminate high current from
flowing in the analog Vee and ground wires. The most effective method of accomplishing this is to use a single ground
point and a single Vee point where all wires are brought
together. In addition to this the conductors must be of sufficient size to prevent significant voltage drops.
Figures 5 and 6 show systems operating with an isolated
supply that will convert positive and negative inputs. 60 Hz
common mode input becomes a problem in this configuration and a transformer with an electrostatic shield between
primary and secondary windings is shown. The necessity for
using a shielded transformer depends on the performance
requirements and the actual application.
The filter capacitors connected to VFB (pin 14) and VFLT
(pin 11) should be low leakage. In the application examples
shown every 1.0 nA of leakage current will cause 0.1 mV
error (1.0X1O- 9 A x 100 kfi=O.1 mV). If the leakage current in both capacitors is exactly the same no error will result since the source impedances driving them are matched.
To prevent switching noise from causing jitter problems, a
voltage regulator with good high frequency response is necessary. The LM309 and the LM340-5 voltage regulators all
function well and are shown in Figures 4, 5, and 6. Adding
more filtering than is shown will in general increase the jitter
rather than decrease it.
3-275
ADD3701
'~Ul
.---
1V
:nimA )
IlMlD9
t LMO~1J.5
v~
~ERGND>---------------------!---~~JL~~~::~~~~~--LJ ~--------------~--~
~I
r--+---.,200n
_LL11~
~
'".....
,;,
I
I
I
'"
22Mn
L _____
GND
SIGNAL
I
I
I
J
~ R3
~~
0>
g
~
No
2SOpf
I
_111
~
...
f7.Sk
18
~
20
119
~
L
21
~
co
~
w
23
S
2,126
24
:!
'"
Z
21
r2a
m
co
lOOk
ADD3701
ADJUST
,.
Z
~
DFFSET
II
;
114
e:
~
"113
e:
iii
:;::
.f2
G"
~
~
~
~
lID
• _ _ _ _ _ _ _-/......J
......
~~
0,.
Zoo
~
~
5~
e: ....
me:
19
Is
0
~
~
0
b
O.41~F
(31
'6
I-
13
~
LI'
"
lOOk
....I.!.
~
10llF
TW~
DYTO )
+UtlV
TL/H/56B2-6
NOTES:
1. ALL RESISTORS
V. WATT ±
2. ALL CAPACITORS
5% UNLESS OTHERWISE SPECIFIED
± 10%
3. LOW LEAKAGE CAPACITOR REQUIRED.
Rf R2
4. R,
Figure 4. 3%-Digital DPM,
+ 3.999 Count Full Scale
+ R2
~
R3 ±25!l
.... ill
Co)
~
.....
ADD37Dt
GUARD
+ 10 F
10'VOC
VI'I
VI-I
OTES.
OY TO !.IllY
10-3.998 CD UNTSI
1. ALL RESISTORS
Yo WATT
±5% UNLESS OTHERWISE SPECIFIED
2. ALL CAPACITORS ± 10%.
TUH/5682-7
3. LOW LEAKAGE CAPACITOR REQUIRED.
4. RIR2
RI +R2 ~R3±25n.
Figure 5. 3%-Digit DPM,
± 3.999 Counts Full Scale
~OL&aa"
1;1
ADD3701
B-4Sn
IZon
r---
31
r
r
SDk
I
~I1
I
I
I
Co)
~
1
I
IiFmf---
>>-----.....
e
2
....
I
22Mn
I
rJ
400vE9
.,%
4DDk
_.J
ADD3701
ADJUST
tMn:!1"
to.01%
>
Z
S
'"
....
...... 5=
n~
,,>
ilM"
e
e
....
N
O.4VO 4V
VI+) )
=
~
ZZZlZ4ZS
I
II
GUARD
I
,0
~-1-+-4-.j-..J
II
m ..
IB
"6
5
~
j7
~
~
IS 15 14 j3 Iz I'
~~
~~~~I----------~
Tm~
NOTES:
VH)
,
1. ALL RESISTORS % WATT ±5% UNLESS OTHERWISE SPECIFIED
2. ALL CAPACITORS ±10%.
3. LOW LEAKAGE CAPACITOR REQUIRED.
4 R,R2 =R ±25!l
. R,+ R2
3
.
Figure 6. 3%-Dlglt DVM, Four Decade, ±O.4V, ±4V, ±40V, and ±400V Full Scale
TLlH/56B2-B
r--------------------------------------------------------------------,~
C
C
Co)
.....
o
....
LCD
DlSPLAV
f a
•
J 111111
I
• bed
I
IIUIJ
• bed. la
~
~
CD4543
!~
T""LD
A
8
C
D
II
BI
I II
I I
111111
r-
I I II
-PH
CD4543
":'
ABC
I I I
I I
I I
I
I
' - - PH
roo- BI
~ -LD
CD4543
~BI
-LD
~KPLANE
•
I bed. f 9
III
I
,1-- PH
.--81
•
LD
ABC
D
D
ABC
SODk
SOak
8
D
I
.1 I
I
A
CD4543
C
D
DE
1
* ": "
Jo---..,
II ~"'I (=i
•
bed.
f
I
DF~I---'"
ADDml
DISPLAY 9.999 WHEN OVERFLOWED.
ALL DIGITS CAN ALSO BE BLANKED AT
OVERFLOW BY TYING OFL TO 81 ON THE
C045430.
Figure 7. ADD3701 Driving Liquid Crystal Display
3-279
TL/H/56B2-9
~
~
COol
::E
Q
ctf
~
COol
::E
Q
N
~
COol
::E
Q
r----------------------------------------------------------------------------,
_
National
Semiconductor
Corporation
DM2502, DM2503, DM2504 Successive Approximation
Registers
General Description
The DM2502, DM2503 and DM2504 are 8-bit and 12-bit
TIL registers designed for use in successive approximation
AID converters. These devices contain all the logic and
control circuits necessary in combination with a Of A converter to perform successive approximation analog-to-digital
conversions.
The DM2502 has 8 bits with serial capability and is not expandable. The DM2503 has 6 bits and is expandable without serial capability. The DM2504 has 12 bits with serial
capability and expandability.
All three devices are available in ceramic DIP, ceramic flatpak, and molded Epoxy-S DIPs. The DM2502, DM2503 and
DM2504 operate over - 55°C to + 125°C; the DM2502C,
DM2503C and DM2504C operate over OOC to + 700C.
Features
• Complete logic for successive approximation AfD converters
• 8-bit and 12-bit registers
• Capable of short cycle or expanded operation
• Continuous or start-stop operation
• Compatible with Of A converters using any logic code
• Active low or active high logic outputs
• Use as general purpose serial-to-parallel converter or
ring counter
Logic Diagram
;:I:~~,-
ninO!
C.----"""'::',:Z
~,'
- -;;,;;:,- --"I
I
I
I
I
I
I
I
I
"
1------+-----....l...L-_-_-_._-_-_-_-_-_-_-_-JI....-...J
Connection Diagrams (Dual-In-Line and Flat Packages)
N... I: CtlllaptlS""".dtarn...... 'hlH-
g;::~~:~.DMZ503
N•• 2, •• _ " ..' .........
,".M....
DM2504
DM2502, DM2503
"
I.. " " "
ZD
"
11
17
16
"
.
"
r-
1
-I:
2
DO
, • • •
lla:
01
01
02
7
01
• ,
04
as
.
Nt
11
D
rz
GNO
TOP VIEW
TLlF/5702-1
Order Number DM2502J, DM2502CJ, DM2503J
orDM2503CJ
See NS Package J16A
Order Number DM2502CN or DM2503CN
See NS Package N16A
Order Number DM2502W, DM2502CW, DM2503W,
orDM2503CW
See NS Package W16A
3-280
Order Number DM2504F or DM2504CJ
See NS Package F24D
Order Number DM2504J or DM2504CJ
See NS Package J24A
Order Number DM2504CN
See NS Package N24A
c
Absolute Maximum Ratings
==
Operating Conditions
(Note 1)
Supply Voltage
7V
Input Voltage
5.5V
Output Voltage
5.5V
Storage Temperature Range
- 65·C to + 150·C
Lead Temperature (Soldering, 10 seconds)
300·C
Supply Voltage, Vee
DM2502C, DM2503C,
DM2504C
DM2502, DM2503,
DM2504
Min
Max
Units
4.75
5.25
V
4.5
5.5
V
+70
·C
0
Parameter
Conditions
Vee = Min
Logical "1" Input Current (IIH)
CPlnput
D, E, S Inputs
All Inputs
Vee = Max
VIH=2.4V
VIH=2.4V
VIH=5.5V
Logical "0" input Voltage (VILl
Vee = Min
Logica!"O" Input Current (11Ll
CP,S Inputs
D, E Inputs
Vee = Max
VIL=0.4V
VIL =0.4V
+125
·C
Max
Vee=Max; VOUT= O.OV;
Output High; CP, D, S, High; E Low
Logical "0" Output Voltage (VoLl
Vee=Min,IOL =9.6 mA
Supply Current (Ieel
DM2502C
DM2502
DM2503C
DM2503
DM2504C
DM2504
Vee = Max, All Outputs Low
Propagation Delay to a Logical "0"
From CP to Any Output (tpdO)
2.4
-10
10
CP High, SLow
DM2503, DM2503C, DM2504,
DM2504C Only
Propagation Deiay to a Logical "1"
From CP to Any Output (tedl)
10
CP High, SLow
DM2503, DM2503C, DM2504,
DM2504C Only
Units
V
40
80
1.0
/LA
/LA
mA
0.8
V
-1.6
-3.2
mA
mA
-20
-45
mA
0.2
0.4
V
65
65
60
60
90
90
95
85
90
80
124
110
mA
mA
mA
mA
mA
mA
18
28
ns
16
24
ns
26
38
ns
13
19
ns
ns
-1.0
-1.0
Vee = Min, 10H = 0.48 mA
Propa.l!ation Delay to a Logical "1"
From E to 07 (011) Output (tpdl)
Typ
6
6
Logical "1" Output Voltage (VOH)
3.6
V
Set-Up Time Data Input (!seDl)
-10
4
8
Set-Up Time Start Input (ts(s)
0
9
16
ns
Minimum Low CP Width (tpwLl
30
42
ns
Minimum High CP Width (tpWH)
17
24
ns
15
21
MHz
Maximum Clock Frequency (fMAXl
Note 1: "Absolute Maximum Ratings" are those values beyond which the salety 01 the device cannot be guaranteed. Except lor "Operating Temperature Range"
they afB not meant to imply that the devices should be operated at thess limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the -55'C to + 125'C temperature range lor the DM2502. DM2503 and DM2504, and across the
O'C to +70'C range lor the DM2502C, DM2503C and DM2504C. All typicals are given lorVcc~5.0V and TA~25'C.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
3-281
Q
~
==
N
U'J
~
-55
2.0
Output Short Circuit Current
(Note 4) (los)
Propa.l!ation Deiay to a Logical "0"
From E to 07 (011) Output (!PdO)
Min
==
N
U'J
Q
Electrical Characteristics (Notes 2 and 3) Vee = 5.0V, TA= 25·C, CL = 15 pF, unless otherwise specified.
Logical "1" Input Voltage (VIH)
j')
C
C
Temperature, TA
DM2502C, DM2503C,
DM2504C
DM2502, DM2503
DM2504
N
U'J
Q
~
~
C"I
~
r------------------------------------------------------------------------------------------,
Application Information
OPERATION
The registers consist of a set of master latches that act as
the control elements in the device and change state on the
input clock high-to-Iow transition and a set of slave latches
that hold the regi1$ter data and change on the input clock
low-to-high transition. Externally the device acts as a special
purpose serial-to-parallel converter that accepts data at the
D input of the register and sends the data to the appropriate
slave latch to appear at the register output and the DO output on the DM2502 and DM2504 when the clock goes from
low-to-high. There are no restrictions on the data input; it
can change state at any time except during a short interval
centered about the' clock low-to-high transition. At the same
time that data enters the register bit the next less significant
bit register is set to a low ready for the next iteratio'n.
very slow dV/dt rates at the clock input (such as from relatively weak comparator outputs), improper logic operation
will not result.
LOGIC CODES
All three, registers can be operated with various logic codes.
Two's complement code is used by offsetting the comparator Yz full range + Yz LSB and using the complement of the
MSB (Q7 or 011) with a binary DI A converter. Offset binary
is used in the same manner but with the MSB (07 or 011).
BCD DI A converters can be used with the addition of illegal
code suppression logic.
ACTIVE HIGH OR ACTIVE LOW LOGIC
The register can be used with either 01 A converters that
require a low voltage level to turn on, or DI A converters that
require a high voltage level to turn the switch on. If DI A
converters are used which turn on with a low logic level, the
resulting digital output from the register is active low. That
is, a logic "1" is represented as a low voltage level. If D/A
converters are used that turn on with a high logic level then
the digital output is active high; a logic "1" is represented as
a high voltage level.
The register is reset by holding the S (Start) signal low during the clock low-to-high transition. The register synchronously resets to the state Q7 (11) low, and all the remaining
register outputs high. The Qee (Conversion Complete) signal is also set high at this time. The S signal should not be
brought back high until after the clock low-to-high transition
in order to guarantee correct resetting. After the clock has
gone high resetting the register, the S Signal must be removed. On the next clock low-to-high transition the data on
the D input is set into the Q7 (11) register bit and the Q6
(10) register bit is set to a low ready for the next clock cycle.
On the next clock low-to-high transition data enters the Q6
(10) register bit and Q5 (9) is set to a low. This operation is
repeated for each register bit in turn until the register has
been filled. When the data goes into QO, the Qce signal
goes low, and the register is inhibited from further change
until reset by a Start signal.
EXPANDED OPERATION
An active low enable input, E, on the DM2503 and OM2504
allows registers to be connected together to form a longer
register by connecting the clock, D, and S inputs in parallel
and connecting the Qee output of one register to the E input
of the next less Significant register. When the start resets
the register, the E signal goes high, forCing the Q7 (11) bit
high and inhibiting the register from accepting data until the
previous register is full and its Qee goes low. If only one
register is used the E input should be held at a low logic
level.
The OM2502, DM2503 and OM2504 have a specially tailored two-phase clock generator to provide nonoverlapping
two-phase clock pulses (i.e., the clock waveforms intersect
below the thresholds of the gates they drive). Thus, even at
Timing Diagram
DM2502, DM2503
INPUTS
[":L-.J
0"
0",
I
I
o. I
I
0'1
I
OlL:]
L--.I
L-.l
OUTPUTS
0.r::::J
0.r::::J
ooL::]
Dc"
I
00
TUF/5702-2
3-282
Application Information
Definition of Terms
(Continued)
CP: The clock input of the register.
SHORT CYCLE
If all bits are not required, the register may be truncated and
conversion time saved by using a register output going low
rather then the ace signal to indicate the end of conversion.
If the register is truncated and operated in the continuous
conversion mode, a lock-up condition may occur on power
turn-on. This condition can be avoided by making the start
input the OR function of ace and the appropriate register
output.
0: The serial data input of the register.
DO: The serial data out. (The D input delayed one bit).
E:
The register enable. This input is used to expand the
length of the register and when high forces the a7 (11)
register output high and inhibits conversion. When not used
for expansion the enable is held at a low logic level
(ground).
01 1=7 (11) to 0: The outputs of the register.
Occ: The conversion complete output. This output remains
high during a conversion and goes low when a conversion is
complete.
COMPARATOR BIAS
To minimize the digital error below ± Yz LSB, the comparator must be biased. If a Df A converter is used which requires a low voltage level to turn on, the comparator should
be biased + Yz LSB. If the Df A converter requires a high
logic level to turn on, the comparator must be biased - Yz
LSB.
07 (11): The true output of the MSB of the register.
Q7 (11): The complement output of the MSB of the register.
S: The start input. If the start input is held low for at least a
clock period the register will be reset to a7 (11) low and all
the remaining outputs high. A start pulse that is low for a
shorter period of time can be used if it meets the set-up time
requirements of the S input.
Truth Table
DM2502, DM2503
Time
Outputs 1
Inputs
tn
0
S
E2
003
Q7
06
05
04
03
02
01
00
0
1
2
S
4
5
6
7
X
L
H
H.
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
X
L
D7
D7
D7
D7
D7
07
07
07
07
H
L
D6
D6
D6
D6
D6
D6
D6
D6
H
H
L
D5
D5
D5
D5
D5
D5
D5
H
H
H
L
D4
D4
D4
D4
D4
D4
H
H
H
H
L
DS
DS
DS
DS
DS
H
H
H
H
H
L
D2
D2
D2
D2
H
H
H
H
H
H
L
Dl
Dl
Dl
H
H
H
H
H
H
H
L
DO
DO
H
H
H
H
H
H
H
H
L
L
X
H
X
H
NC
NC
NC
NC
NC
NC
NC
NC
D7
D6
D5
D4
DS
D2
Dl
DO
8
9
X
X
10
X
D7
D6
D5
D4
DS
D2
Dl
DO
Occ
= High Voltage Level
L = Low Voltage Level
X = Don't Care
NC = No Change
Note 1: Truth table for DM2504 is extended to include 12 outputs.
H
Note 2: Truth table for DM2502 does not include E column or last line in truth table shown.
Note 3: Truth table for DM2503 does not include DO column.
Typical Applications
BCD Illegal Code Suppression
Active High
ClOe«
.
I
•
i
DMZlaz
Active Low
I
:cJ
•
CLOCK-
i
aMZ5az
··tJ
Dc,
Cl7 01 a5 a. B3 QZ 01 GO
G.7 alGID. 03 lIZ D1aD
~
".....
COMPARATOR
O/A CONVERTfR
a/A caliVERTER
3-283
~
~
TL/F/5702-3
Typical Applications (Continued)
Fast Precision Analog-to-Olgltal Converter
15V
BIPOLAR UNIPOLAR
100.
Rl (UNIPOLARI
50k
100
100
-15V
VCC
BIPOLAR GFF
':"
11
: ) ANALOG INPUTS
20VSPAN
R2
100
9.95k
5k
1&V
10
5V
IDVSPAN
5k
11
OAC
4-'---
10
B.
lOUT" 4 II 'REF
II
CODe
CODE INPUT
LSB
¥-{
GIG OUT 12
13
MSB
-...::LS::B-+::+++++'::T.:-t-t-Hr-t
21
16 B
11
mwrnll'--~U
SERIAL OUT --""';:-1
DATA IN
14 mIlT
DMZ5D4 SAR
CLOCK
INPUT RANGES
12
Unipolar
01010
0105
01020
Bipolar
±5
±2.5
±10
Switching Time Waveforms
Equlv.
Connect
DAC loUT
Input to A
2.36 kO
Inpul 10 A
1.90 kO
Inpul 10 B
3.08 kO
BloDACQUT
TL/F/5702-4
ATlEAST
===-.J,------t===:J.
----1.5V
INPUTS
DUTPUTS
Must bl Sll1dy
Will b.smdy
WAVEFORMS
071111
061101
---:---+---'t'UT
DD
IDM2502.DM25Q41 _ _ _ _ _ _ _!JJ.~1.\:=====:t1/1/J1-------1
IDM25D3.
f--------t---------- '·
~_1UJ.M
I· ~~,~I:..:'=
DM25~1_____________-J_
071111 _ _ _ _ _ _
5V
_
''''''EIM''
...='"'=MA=X=='.5V
3·284
...
•
-
Mav chanp from
Willblchlnginl
H to l
from H 10 L
Mlych.npltom
L 10 H
Will beeh.n''''
hom Lto H
Don't Clrl: .ny
chlngl permitted
unknown
Chlnging: ".tl
CP'"
ENABLETO 071111
I'L
TLlF/5702-5
~ Semiconductor
NatiOnal
Corporation
LM131A/LM131, LM231A/LM231, LM331A/LM331
Precision Voltage-to-Frequency Converters
General Description
The LM131/LM231/LM331 family of voltage-to-frequency
converters are ideally suited for use in simple low-cost circuits for analog-to-digital conversion, precision frequencyto-voltage conversion, long-term integration, linear frequency modulation or demodulation, and many other functions.
The output when used as a voltage-lo-frequency converter
is a pulse train at a frequency precisely proportional to the
applied input voltage. Thus, it provides all the inherent advantages of the voltage-to-frequency conversion techniques, and is easy to apply in all standard voltage-to-frequency converter applications. Further, the LM131 AI
LM231A1LM331A attains a new high level of accuracy versus temperature which could only be attained with expensive voltage-to-frequency modules. Additionally the LM131
is ideally suited for use in digital systems at low power supply voltages and can provide low-cost analog-to-digital conversion in microprocessor-controlled systems. And, the frequency from a battery powered voltage-to-frequency converter can be easily channeled through a simple photoisolator to provide isolation against high common mode levels.
The LM131/LM231/LM331 utilizes a new temperaturecompensated band-gap reference circuit, to provide excellent accuracy over the full operating temperature range, at
power supplies as low as 4.0V. The precision timer circuit
has low bias currents without degrading the quick response
necessary for 100 kHz voltage-to-frequency conversion.
And the output is capable of driving 3 TIL loads, or a high
vollage oUlput up to 40V, yet is short-circuit-proof against
Vee·
Features
• Guaranteed linearity 0.01 % max
• Improved performance in existing voltage-Io-frequency
conversion applications
• Split or single supply operation
• Operates on single 5V supply
• Pulse output compatible with all logic forms
• Excellent temperature slability, ±50 ppml'C max
• Low power dissipation, 15 mW typical at 5V
• Wide dynamic range, 100 dB min at 10kHz full scale
frequency
• Wide range of full scale frequency, 1 Hz to 100 kHz
• Low cost
Typical Applications
BIN
'00"'0%
lovFu~lr -'V\fIr......_ _ _ _~1
~CIN**
~O.I.F
l
r-JVl./\,-- VLOGIC
3
fOUT
~-4I---l0kHz
"~
+1.5
ill
+0.5
ffi
r-
1.920
r-.
> 1.918
1.916
:E
...
I' '"
~
1.914
9.96 hP~":"-+-+--t-'
9.94 L....J.-..J.-..J.-..J.....J.....J.....J.....L....J
1.910
-15
+125
-25
TEMPERATURE. ·C
+1.0
~..uIII
f-I-
100 kHz Nonlinearity Error,
LM131 Family (Figure 4)
J"'II\ I,UiII
0
r.iii f'IIIIII
-0.5
I--f-+-t-r--r---r..,
t--t--t--t--Ir--t-;--1
I--f--j--t-r--r---r"-'
"'~ -0.01 t--t-f-"'_==I;;.,c..+--I
c:::--iii -0.02 I--f--j--t-r--r---r-,
~
+0.01
~ -0.03
-0.04
t--t--t--t--Ir--t--1
t-+-t--t-t--t--;
20
40
60
80
100
~
'"
+25
+75
;
-0.01
~
-0,02
Input Current (Pins 6, 7) vs
Temperature
150
:
........
..... '"
10
10 15
~~
i
~
VSUPPLY, V
35
>
a
>
40
-55'C:
2.4
f
+0.04
+25°C
:i1a:a: +0.02
"'~
+0.01
..
~
-0.02
~ -0.03
-0.04
20
30
lOUT, mA
+15
'"
'"
+125 +150
1--1-+-+-1--1-"
1--1-+-+-1--1-"
~-+--MAXIJUM-+-+--l
1"""1"1,,1,","", """"""1",""",1"""1"1111'
""'"
~ -0.01
Z
V
10
+25
~
;,'LZ..
II~iMIT
~. +0.03
w
I-- -}"'J(."
SPEC
-25
'~S
Nonlinearity Error, Precision
F-to-V Converter (Figure 6)
J
II
I
jI/
1.6
rt- -
TEMPERATURE.oc
" .L
2.0
0.8
25 30
--
-75
Output Saturation Voltage vs
lOUT (Pin 3)
1.2
20
12
r-...
t-
!!!
FREQUENCY, kHz
f6S" . "- 1'+125'C
........
50
!;
120
0.4
5
100
-50
2.8
"'"
~
V
3.2
~
z
w
a:
1/
-0.04
5
.d!
'..."
oS
~ -D.DJ
Power Drain vs VSUPPLY
-55!C,
10 15 20 25 30 35 40
VSUPPLY. V
..... +0.01
"'
~
1-
+125 +150
~ +0.02
fREQUENCY, kHz
+L
40
[1I'mII
5
+0,04
+O.OJ
~
~:Al
-1.5
Nonlinearity Error, LM131
(Figure 1)
t--t-i--ir--+-t--l
:. +0.03
35
1"'' "1 InI!t.
-1.0
200
w
I-L,i~
TEMPERATURE. ·C
~ +0.02
30
-2.0
1.912
+01l4
25
+2.0
1.924
9.98
20
1.930
~ 10.02
~ '0.00
15
Output Frequency vs
VSUPPLY
VREF vs Temperature,
LM131A
1.928
~.
10
POWER SUPPLY VOLTAGE. Vs
1.926
+15
VV
z
I+HtIIIII+titlllt-ttltlH-tttIIHltllllt-Ht1lll
0.00010.0010.01
10.04
~
~ 0.010
!+tttt!lrttttHlfl-ttillH-HtIlHiltlfllt-l
-0.03 UJllllllU.ll!IIIII...LWIUUJllIILWlllluiJllllll
12
SPEC LIMIT
z
0.01
Frequency vs Temperature,
LM131A
10.06 ,'-"""T--r-,r-T""""""-'-'
c:r:
,...
"~·0.015
...>-
fREQUENCY, kHz
..J
0.020
g;'
z -0.02
10
('I)
..J
t-
0.025
HlIllllil-lt\\IIIII-ltlIIl!HtllIIIHtllf-t
+ISV
A,
&.Ilk!."-
.Il...J1..
11.-l .....-=-----=--I
41QpF
lIN
--11-+------=--1
..n.nn.
CI.41Dpf
RF
IOQkW
r-_-_..Jy..,.,..~p_v.U,
j-:--1-......- - VOUT
A. {
lOOk
C4,O.02 .. F
'Uh'"
12k" ••
R, {
".
Sk'
TLlH/5680-7
VOUT
~ fiN X 2.09V x !:!h x (RM>
vour ~ -fiN x 2.09V x
Rs
'Use stable components with low temperature coefficients.
SELECT Rx
RF
As
x (R,c,)
TLlH/5680-B
~ (Vs - 2AV)
0.2m
FIGURE 5. Simple Frequency-to-Voltage Converter,
10 kHz Full-Scale, ±0.06% Non-Linearity
'Use stable components with low temperature coefficients.
FIGURE 6. Precision Frequency-to-Voltage Converter,
10 kHz Full-Scale with 2-Pole Filter, ±0.01%
Non-Linearity Maximum
3-291
...
C")
C")
:i
•...
Typical Applications
(Continued)
Light Intensity to Frequency Converter
C")
C")
+5VTO+15V
:!!
.....
......
....
C")
N
'OUTo).
1"--+-....._IOD
..H2
FULL SCALE
:!!
.....
.....
c(
...~
.....
.....
...
,..
"
:!!
"
C")
TL/H/5680-9
:!!
•
.....
,..
'L14F-1, L14G-1 or L14H-1, photo transistor (General Electric Co.) or similar
,..
:!!
.....
C")
Temperature to Frequency Converter
v,
'"
r--t-...........~
fOUTo TEMP
LMalt
a.llkt '''Rt
10HzrK
"
Q,OIj.jF
TL/H/5680-10
Basic Analog-to-Dlgital Converter Using
Voltage-to-Frequency Converter
Long-Term Digital Integrator Using VFC
'V,
'V,
DATA
}
DATA
VIN
OUTPUTS
}
V,N
TODISPLAV
OUTPUT
TO
COMPUTER
OR COMPUTER
TL/H/5680-11
TL/H/5680-12
3-292
r-
....
....
»
l!:
Typical Applications (Continued)
Co)
.....
r-
Analog-to-Digltal Converter with Microprocessor
....
....
.....
l!:
C>-_~ ~R COUNTER
TO F-TD·V
CONVERTER
USING LM131
fOUT
DPTOISDLATDR
4NZB DR
SIMILAR
TL/H/5880-18
3-293
Typical Applications (Continued)
VOltage-to-Frequency Converter with Isolators
tVs
tVLOGIC
';"
COMPARATOR
WITH
HVSTERESIS
TUH/56BO-17
Voltage-to-Frequency Converter with Isolators
tVs
+VLOGIC
....~., ~--
I
fOUT
TELEMETRV
USING
RF LINK
TL/H/56BO-IB
Voltage-to-Frequency Converter with Isolators
+Vs
+VLOGIC
lk
TO COMPUTER
OR
TO COUNTER
OR
TO HO·V
CONVERTER
USING LM131
VIN
TL/H/56BO-19
Connection Diagrams
Dual-In-Llne Package
Metal Can Package
Vs
GNO
TOP VIEW
CURRENT
OUTPUT
1
REFERENCE
CURRENT
Z
COMPARATOR
INPUT
FREQUENCV
OUTPUT
3
THRESHOLD
Vs
GNO
TL/H/SBBO-20
RIC
TOP VIEW
Note: Metal case is connected to pin 4 (GND.)
TUH/56BO-21
Order Number LM131AH, LM131H, LM231AH,
LM231H, LM331AH or LM331H
See NS Package Number HOSC
Order Number LM231AN, LM231N, LM331AN,
orLM331N
See NS Package Number NOSE
3·294
~-----------------------------------------------------'r
s:
....
....~
Schematic Diagram
c.:I
......
r
s:
....
....
......
c.:I
r
s:
I\)
....~
c.:I
......
r
s:
I\)
....
......
c.:I
r
s:
~#
~--------~---r----~a~ar-J=-~~--------------~
9
~,1'---------+-----+------~__'II1IIr___i
I z~
.
12;"1
r\S.
L.:'""'
~----------------~~~
TlIH/5680-22
3·295
c.:I
c.:I
....
~
......
r
s:
c.:I
....
c.:I
~NatiOnal
Semiconductor
Corporation
MM54C905/MM74C905 12-Bit Successive Approximation
Register
General Description
Features
The MM54C905/MM74C905 CMOS 12-bit successive approximation register contains all the digit control and storage necessary for successive approximation analog-ta-digital conversion. Because of the unique capability of CMOS to
switch to each supply rail without any offset voltage, it can
also be used in digital systems as the control and storage
element in repetitive routines.
•
•
•
•
3.0V to15V
Wide supply voltage range
1.0V
Guaranteed noise margin
0.45Vcc typ
High noise immunity
fan out of 2
Low power TTL
compatibility
driving 74L
• Provision for register extension or truncation
• Operates in START/STOP or continuous conversion
mode
• Orive ladder switches directly. For 10 bits or less
with 50k/100k R/2R ladder network
Connection Diagram
Dual·ln·Llne Package
t
~
M W ~
M Hun
M
~
H
n
mUM
"
u
"
"
~
i
"
I
E
Order Number MM74C905N
See NS Package Number N24C
u
l-
2
DO
..
3
•
00
•
5
01
02
I
03
•
DC
9
05
la
Ne
11
o
J~Z
GND
TLlF/5712-1
Top View
Truth Table
TIME
IN~UTS
tn
0
S
E
DO
011
010
09
08
07
06
05
04
03
02
01
00
C
0
1
2
3
4
5
6
7
B
9
10
11
12
13
14
X
011
010
09
08
07
06
05
04
03
02
01
DO
X
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
X
011
010
09
08
07
06
05
04
03
02
01
DO
X
X
X
L
011
011
011
011
011
011
011
011
011
011
011
011
011
H
X
H
L
010
010
010
010
010
010
010
010
010
010
010
010
NC
X
H
H
L
09
09
09
09
09
09
09
09
09
09
09
NC
X
H
H
H
L
OB
OB
OB
OB
08
DB
DB
DB
08
DB
NC
X
H
H
H
H
L
07
07
07
07
07
07
07
07
07
NC
X
H
H
H
H
H
L
06
06
06
06
D6
06
06
06
NC
X
H
H
H
H
H
H
L
05
05
05
05
05
05
05
NC
X
H
H
H
H
H
H
H
L
04
X
H
H
H
H
H
H
H
H
L
03
03
03
03
03
NC
X
H
H
H
H
H
H
H
H
H
L
02
02
02
02
NC
X
H
H
H
H
H
H
H
H
H
H
L
01
01
01
NC
X
H
H
H
H
H
H
H
H
H
H
H
L
DO
DO
NC
X
H
H
H
H
H
H
H
H
H
H
H
H
L
L
NC
OUTPUTS
H ~ High level
L ~ Low level
X ~ Don'l care
NC ~ No change
3-296
D4
04
04
04
04
NC
s:
s:
en
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage at Any Pin
Operating Temperature Range
MM74CS05
Storage Temperature Range
ESD Susceptibility (Note 4)
400V
Package Dissipation
500mW
Operating Vcc Range
-0.3toVcC +0.3V
3.0Vto 15V
16V
260'C
Absolute Maximum Vcc
Lead Temperature (Soldering, 10 seconds)
-40'Cto +85'C
-65'C to + 150'C
t;
CO
c
en
.....
s:
s:
.......
"'o"
CO
c
en
DC Electrical Characteristics
Parameter
MinImax limits apply across temperature range, unless otherwise noted.
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
Logical "1" Input Voltage (VIN(l»
Vcc=5.0V
Vcc=10V
3.5
8.0
Logical "O"lnput Voltage (VIN(O»
Vcc=5.0V
VcC=10V
Logical "1" Output Voltage (VOUT(l»
VcC=5.0V, 10= -10",A
Vcc=10V,10=-10",A
Logical "0" Output Voltage (VOUT(O»
Vcc=5.0V,10=10",A
Vcc=10V,10=10",A
Logical "1" Input Current (IIN(l»
Vcc=15V, VIN=15V
Logical "0" Input Current (IIN(O»
Vcc=15V, VIN=OV
Supply Current (Icc>
Vcc=15V
V
V
1.5
2.0
4.5
S.O
V
V
0.005
-1.0
V
V
0.5
1.0
V
V
1.0
",A
-0.005
0.05
",A
300
",A
CMOS/LPTIL INTERFACE
Logical "1" Input Voltage (VIN(l»
MM54CS05
MM74CS05
Vcc=4.5V
Vcc=4.75V
Logical "0" Input Voltage (VIN(O»
MM54CS05
MM74CS05
Vcc=4.5V
Vcc=4.75V
Logical "1" Output Voltage (VOUT(l»
MM54CS05
MM74C905
Vcc=4.5V, 10= -360",A
Vcc=4.75V, 10= -360",A
Logical "0" Output Voltage (VOUT(O»
MM54CS05
MM74CS05
VCC=4.5V, 10 = 360",A
VCC=4.75V, 10= 360",A
V
V
Vcc- 1.5
Vcc- 1.5
0.8
0.8
2.4
2.4
V
V
V
V
0.4
0.4
V
V
OUTPUT DRIVE (See 54C174C Family Characteristics Data Sheet)
Output Source Current (ISOURCE)
(P-Channel)
Vcc=5.0V, VOUT=OV
TA=25'C
-1.75
-3.3
mA
Output Source Current (ISOURCE)
(P-Channel)
Vcc=10V, VOUT=OV
TA=25'C
-8.0
-15
mA
Output Sink Current (ISINKl
(N-Channel)
VCC=5.0V, VOUT=VCC
TA=25'C
1.75
3.6
mA
Output Sink Current (ISINK)
(N-Channel)
Vcc=10V, VOUT=VCC
TA=25'C
8.0
16
mA
011-00 Outputs
Vcc=10V ±5%
VOUT=VCC- 0.3V
TA=25'C
150
350
n
Vcc=10V ±5%
VOUT=0.3V
TA=25'C
80
230
n
RSOURCE
RSINK
3-2S7
AC Electrical Characteristics TA= 25'C,CL = 50pF, unless olherwise specified.
Typ
Max
Units
Propagation Delay Time From Clock
Parameter
Vcc=5.0V
Conditions
Min
200
350
ns
Input To Outputs (00-011)(lpd(Q»
Vcc=10V
80
150
ns
Propagation Delay Time From Clock
Vcc=5.0V
180
325
ns
Inpul To Do(lpd(On»
Vcc=10V
70
125
ns
Propagalion Delay Time From Regisler
Vcc=5.0V
190
350
ns
Enable (E) To OUlput (011) (tpd(E»
Vcc=10V
75
150
ns
Propagalion Delay Time From Clock
Vcc=5.0V
190
350
ns
To CC (lpd(CC)
Vcc=10V
75
0.50
ns
Dala Inpul Sel-UpTime (tos)
Vcc=5.0V
Vcc=10V
80
30
ns
ns
Slart Inpul Set-Up Time (Iss)
Vcc=5.0V
Vcc=10V
80
30
ns
ns
Minimum Clock Pulse Widlh (tpwL,tpWH)
Vcc=5.0V
Vcc=10V
250
100
Maximum Clock Rise and Fall Time (Ir, tt)
Vcc=5.0V
Vcc=10V
Maximum Clock Frequency (fMAX)
Vcc=5.0V
Vcc=10V
Clock Inpul Capacitance (CCLIO
Inpul Capacitance (CIN)
Power Dissipation Capacitance (Cpo)
(Note 3)
125
40
ns
ns
15
5
2
5
'"'S
,",S
4
10
MHz
MHz
Clock Inpul (Note 2)
10
pF
Any Other Input (Nole 2)
5
pF
100
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CPO determines the no load ae power consumption of any CMOS device, For complete explanation see 54C174C Family Characteristics application note,
AN-gO.
Note 4: Human body model. 100 pF discharged through a 1.5 kn resistor.
Typical Performance Characteristics
RSINK vs Temperature
RSOURCE vs Temperature
:::~LIJ.J
.
J
""''"
GOD
500
400
a 400
300
200
100
~~
~~~
j
~
~~~~~ ~~~ ~
300
200
100
0
-55 -35 -15 5 25 45 65 65 IDS 125
I- fcc llo,l,
i~ ~~
0
-55 -35 -15 5
TA - AMBIENT TEMPERATURE ("CI
'5~
fA -
I
II
II
25 45 65 65 IDS 125
AMBIENT TEMPERATURE (·C)
Tl/F/5712-2
-These pOints are guaranteed by automatic testing
-These points are guaranteed by automatic testing.
3-298
i:
i:
Timing Diagram
UI
0l:IO
o
CD
C)
.....
UI
i:
i:
.....
~
oCD
C)
011:=:1
..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
UI
Ol.:.:.::r-L..j--------------------O.::::r----l~
OI::::J
____________________
LJ
81=:]
OI::..:J
LJ
8'=:]
D4::::J
D3
LJ
:::::J
az::::J
O.::=:J
.
LJ
u
~
~::.:::J
Do
Switching Time Waveforms
Vee
Vee
v'"
I
.
-'
011
•
v",
01.
•
v'"
Do
•
V'"
!
V",
8"
•
TUF/5712-3
3·299
-~
§
~
::::E
::::E
;;,
~...
~
::::E
::::E
r----------------------------------------------------------------------------,
Typical Performance Characteristics
USER NOTES FOR AID CONVERSION
The register can be used with either current switches that
require a low voltage level to turn the switch ON or current
switches that require a high voltage level to turn the switch
ON. If current switches are used which turn ON with a low
logic level, the resulting digit output from the register is active low. That is, a logic "1" is represented as a low voltage
level. If current switches are used which turn ON with a high
logic level, the resulting digit output is active high. A logic
"1" is represented as a high voltage level.
If the register is truncated and operated in the continuous
conversion mode, a lock-up condition may occur on powerON. This situation can be overcome by making the START
input the "OR" function of CC and the appropriate register
output.
The register, by suitable selection of register ladder network, can be used to perform either binary or BCD conversion.
The register outputs can drive the 10 bits or less with 50kl
lOOk R/2R ladder network directly for Vcc=10V or higher.
In order to drive the 12-bit 50k/l00k ladder network and
have the ± 1/2 LSB resolution, the MM54C902/MM74C902
or MM54C904/MM74C904 is used as a bUffer, three buffers
for MSB (Qll), two buffers for Ql0, and one buffer for Q9.
For a maximum error of ± 1/2 LSB, the comparator must be
biased. If current switches that require a high voltage level
to turn ON are used, the comparator should be biased
+ 1/2 LSB and if the current switches require a low logic
level to turn ON, then the comparator must be biased -1/2
LSB.
The register can be used to perform 2's complement conversion by offsetting the comparator one half full range
+ 1/2 LSB and using the complement of the MSB Qll as
the sign bit.
Typical Applications
12·Blt Successive Approximation A·
to·D Converter Operating In Contln·
uous 8·Bit Truncated Mode
12·Bit Successive Approximation A·to-D Converter, Operating In Contlnu·
ous Mode, Drives the SOk/l00k Ladder Network Directly
IDV---,
"."
MM54CIOZ
IMM14CIIZ
OIlMM54C91J4
IMM74C1D4
~
•
v"
CP
.11 "0
.
.0
. ••
,
..
MMMe,aSIMM14Clas
•5
., .,
.,
I
Do
C"C
Iff Ie 'I
,,,.
•
QI
ERIAL
DATA
OUT
} PA.AlLEL
DATA OUT
r-
.i
110_
...
50'
lau
RZRLAOOER
~
... ~'MM"CI"
.
AIllALOGINP UT
TLIF15712-4
Definition of Terms
CP: Register clock input.
011: Complement of register MSB output.
CC: Conversion complete-this output remains at VOUT(1)
during a conversion and goes to VOUT(O) when conversion
is complete.
S:
0: Serial data input-connected to comparator output in A·
to-O applications.
E: Register enable-this input is used to expand the length
of the register. When E is at VIN(1) Qll is forced to VOUT(ll
and inhibits conversion. When not used for expansion E
must be connected to VIN(O) (GNO).
Q11: True register MSB output.
QI (I = 0 to 11): Register outputs.
Start input-holding start input at VIN(O) for at least one
clock period will initiate a conversion by setting MSB (Q11) at
VOUT(O) and all other output (Q-l0-00) at VOUT(1). If set-up
time requirements are met, a conversion may be initiated by
holding start input at VIN(O) for less than one clock period.
DO: Serial data output-O input delayed by one clock period.
3·300
Section 4
Digital-to-Analog
Converters
II
Section 4 Contents
, Digital-to-Analog Converters Definition of Terms. . . . . . . . . . . . . . . . . • . . . . . . . . . • . . . . . . • . . . . •
Digital-to-Analog Converters Selection Guide .......•..................................
DAC0800, DAC0801, DAC0802 8-Bit Digital-to-Analog Converters. . • . . . . . . . . . . . . . . . . . . . . .
DAC0808, DAC0807, DAC0806 8-Bit DfA Converters...................................
DAC0830, DAC0831, DAC0832 8-Bit p.P Compatible Double-Buffered D to A Converters ....
DAC1000, DAC1001, DAC1()02; DAC1006, DAC1007, DAC1008, p.P Compatible, DoubleBuffered D to A Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC1020, DAC1 021, DAC1022, DAC1220, DAC1221, DAC1222 12-Bit Binary Multiplying
Df A Converters. ; ........................................................ : . . • . . . . .
DAC1208, DAC1209, DAC1210, DAC1230, DAC1231, DAC123212-Bit p.P Compatible
Double-Buffered D to A Converters....... ....... .... ........ .. .... .... ... ..........
DAC1218, DAC1219 12-Bit Multiplying Df A Converters. . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . .
DAC1265A, DAC1265 Hi-Speed 12-Bit Df A Converter with Reference ....................
DAC1266A, DAC1266 Hi-Speed 12-Bit Df A Converter ..................•...............
* DAC165516-Bit DfA Converter......................................................
"Devices Not Covered In Last Publication
4-2
4-3
4-4
4-6
4-15
4-23
4-41
4-64
4-74
4-89
4-100
4-109
4-117
~ Semiconductor
NatiOnal
Corporation
Definition of Terms
OJ A Converters
Conversion Time: The time required for a complete measurement by an analog-to-digital converter.
Multiplying DAC: In a sense, every DAC is a multiplying
DAC since the output voltage (or current) is equal to the
reference voltage times a constant determined by the digital
input code divided by 2" (n is the number of bits of resolution). In a two quadrant multiplying DAC the reference voltage or the digital input code can change the output voltage
polarity. If both the reference voltage and the digital code
change the output voltage polarity, four quadrant multiplication exists.
Offset Error (Zero Error): In a DAC, this is the output voltage that exists when the input digital code is set to give an
ideal output of zero volts. In the case of an ADC, this is the
difference between the ideal input voltage (V. LSB) and the
actual input voltage that is needed to make the transition
from zero to 1 LSB. All the digital codes in the transfer curve
are offset by the same value. Many converters allow nulling
of offset with an external potentiometer. Offset error is usually expressed in LSBs.
Power Supply Rejection (Power Supply Sensitivity): The
sensitivity of a converter to changes in the dc power supply
voltages.
Quantizing Error: The error inherent in all AID conversions. Since even an "ideal" converter has finite resolution,
any analog voltage that falls between two adjacent output
codes will result in an output code that is inaccurate by up to
V. LSB.
Ratiometric Operation: Many AID applications require a
stable and accurate reference voltage against which the input voltage is compared. This approach results in an absolute conversion. Some applications, however, use transducers or other signal sources whose output voltages are
proportional to some external reference. In these ratiometric applications, the reference for the signal source should
be connected to the reference input of the converter. Thus,
any variations in the source reference voltage will also
change the converter reference voltage and produce an accurate conversion.
Resolution: The smallest analog increment corresponding
to a 1 LSB converter code change. For converters, resolution is normally expressed in bits, where the number of analog levels is equal to 2". As an example, a 12-bit converter
divides the analog signal into 212 = 4096 discrete voltage
(or current) levels.
DC Common-Mode Error: This specification applies to
ADCs with differential inputs. It is the change in the output
code that occurs when the analog voltages on the two inputs are changed by an equal amount. It is expressed in
LSBs.
Differential Nonlinearity: Ideally, any two adjacent digital
codes correspond to measured analog voltages that are exactly one LSB apart. Differential non-linearity is a measure
of the worst case deviation from the ideal 1 LSB step. For
example, a DAC with a 1.5 LSB output change for a 1 LSB
digital code change exhibits V. LSB differential non-linearity.
Differential non-linearity may be expressed in fractional bits
or as a percentage of full scale. A differential non-linearity
greater than 1 LSB will lead to a non-monotonic transfer
function in a DAC and missing codes in an ADC.
Gain Error (Full Scale Error): For an ADC, the difference
(usually expressed in LSBs) between the input voltage that
should ideally produce a full scale output code and the actual input voltage that produces that code. For DACs, it is the
difference between the output voltage (or current) with full
scale input code and the ideal voltage (or current) that
should exist with a full scale input code.
Gain Temperature Coefficient (Full Scale Temperature
Coefficient): Change in gain error divided by change in
temperature. Usually expressed in parts per million per degree Celsius (ppml'C).
Integral Nonlinearity (Linearity Error): Worst case deviation from the line between the endpOints (zero and full
scale). Can be expressed as a percentage of full scale or in
fractions of an LSB.
LSB (Least-Significant Bit): In a binary coded system this
is the bit that carries the smallest value or weight. Its value
is the full scale voltage (or current) divided by 2n, where n is
the resolution of the converter.
Monotonicity: A monotonic function has a slope whose
sign does not change. A monotonic DAC has an output that
changes in the same direction (or remains constant) for
each increase in the input code. The converse is true for
decreasing codes.
MSB (Most Significant Bit): In a binary coded system this
is the bit that has the largest value or weight. Its value is one
half of full scale.
Settling Time: The time from a change in input code until a
DAC's output signal remains within ± V. LSB (or some other
specified tolerance) of the final value.
4-3
~NatiOnal
Semiconductor
Corporation
01 A Converter Selection Guide
Part
No.
Resolution
(Bits)
Linearity
@2SoC
% (Max)
Settling
Time
(+%LSB)
Supplies
(V)
Temperature
Range"
M
Package
I
C
Comments
ADC0852
8
0.19
5
•
•
8-Pin DIP
DAC, Comparator,
Serial Input
ADC0854
8
0.19
5
•
•
14-PinDIP
DAC, Comparator,
Serial Input
DAC0800
8
0.19
100 ns
±5to±15
•
•
16·Pin DIP
16·PinS.O.
High·Speed
Multiplying
DAC0801
8
0.39
100 ns
±5to ±15
•
•
16·Pin DIP
16·PinS.O.
High·Speed
Multiplying
DAC0802
8
0.10
100 ns
±5to ±15
•
•
16·Pin DIP
16·PinS.O.
High-Speed
Multiplying
DAC0806
8
0.78
150 ns
±5to±15
•
16-PinDIP
16-PinS.O.
Multiplying
DAC0807
8
0.39
150 ns
±5to ±15
•
16-Pin DIP
16-PinS.O.
Multiplying
DAC0808
8
0.19
150 ns
±5to ±15
•
•
16-Pin DIP
16-PinS.O.
Multiplying
DAC0830
8
0.05
1
"'S
5to 15
•
•
20-PinDIP
20-PinS.O.
20-Pin PCC
",p Compatible
4-Quadrant
Multiplying
DAC0831
8
0.10
1
"'S
5to 15
•
20-Pin DIP
",p Compatible
4-Quadrant
Multiplying
DAC0832
8
0.20
1
"'S
5to 15
•
•
20-Pin DIP
20-PinS.O.
20-PinPCC
",p Compatible
4-Quadrant
Multiplying
DAC1000
10
0.05
500ns
5to 15
•
•
24-PinDIP
",p Compatible
Double Buffered
DAC1001
10
0.1
500 ns
5to 15
•
24-Pin DIP
",p Compatible
Double Buffered
DAC1002
10
0.2
500ns
5to 15
•
•
•
24~PinDIP
",p Compatible
Double Buffered
DAC1006
10
0.05
500ns
5to 15
•
•
•
20-PinDIP
",p Compatible
Double Buffered
DAC1007
10
0.1
500ns
5to 15
•
•
20-PinDIP
",p Compatible
Double Buffered
DAC1008
10
0.2
500ns
5to 15
•
•
20-PinDIP
",p Compatible
Double Buffered
4-4
•
•
•
"
01 A Converter Selection Guide (Conlinued)
Part
No.
Resolution
(Bits)
Linearity
@25'C
% (Max)
Settling
Time
(+y. LSB)
Supplies
(V)
Temperature
Range'
M
I
C
Package
Comments
DAC1020
10
0.05
500n5
51015
•
•
•
16·Pin DIP
4·Quadrant
Multiplying
DAC1021
10
0.1
500 n5
5to 15
•
•
•
16-Pin DIP
4·Quadranl
Mulliplying
DAC1022
10
0.2
500 n5
5to 15
•
•
•
16·Pin DIP
4-Quadrant
Multiplying
DAC120B
12
0.012
1,...5
51015
•
•
24·PinDIP
,...p Compatible
4·Quadrant
Multiplying
DAC1209
12
0.024
1,...5
5to 15
•
•
24·PinDIP
,...p Compatible
4·Quadrant
Multiplying
DAC1210
12
0.05
1,...5
51015
•
•
24·PinDIP
,...p Compatible
4·Quadrant
Multiplying
DAC121B
12
0.012
1,...5
5to 15
•
•
1B·Pin DIP
4·Quadrant
Multiplying
DAC1219
12
0.024
1,...5
51015
•
•
1B·PinDIP
4·Quadrant
Multiplying
DAC1220
12
0.05
500n5
5to 15
•
•
1B-Pin DIP
4·Quadrant
Multiplying
DAC1221
12
0.1
500 n5
5to 15
•
1B-Pin DIP
4-Quadranl
Multiplying
DAC1222
12
0.2
500n5
5to 15
•
•
18-Pin DIP
4-Quadranl
Multiplying
DAC1230
12
0.012
1,...5
5to 15
•
•
20-PinDIP
,...p Compatible
4-Quadranl
Multiplying
DAC1231
12
0.024
1,...5
5to 15
•
•
20-PinDIP
,...p Compatible
4-Quadranl
Multiplying
DAC1232
12
0.05
1 ,...5
5to 15
•
•
20-Pin DIP
,...p Compatible
4-Quadrant
Multiplying
DAC1265A
12
0.006
200n5
±15
24-PinDIP
High-Speed
12
0.012
200n5
±15
•
•
•
DAC1265
•
24-Pin DIP
High-Speed
DAC1266A
12
0.006
200n5
±12to ±15
•
High-Speed
12
0.012
200n5
±12to ±15
•
•
•
24-Pin DIP
DAC1266
24-Pin DIP
High-Speed
• Ambient temperature range for "M" is - 55'C to
+ 125'C. "I" is
- 25'C to
+85'C or -
4-5
•
•
40"C to
+ 85'C. "C" O"C to + 70"C.
II
~
o
,----------------------------------------------------------------------------,
CO
NatiOnal
~ Semiconductor
g
Corporation
....
o
'P'"
o
~....
C
I
DAC0800/DAC080 1/DAC0802 8-Bit Digital-to-Analog
Converters
General Description
The DACOSOO series are monolithic S-bit high-speed current-output digital-to-analog converters (DAC) featuring typical settling times of 100 ns. When used as a multiplying
DAC, monotonic performance over a 40 to 1 reference current range is possible. The DACOSOO series also features
high compliance complementary current outputs to allow
differential output voltages of 20 Vp-p with simple resistor
loads as shown in Figure 1. The reference-to-full-scale current matching of better than ± 1- LSB eliminates the need for
full-scale trims in most applications while the nonlinearities
of better than ± 0.1 % over temperature minimizes system
error accumulations.
The DACOSOO, DACOS02, DACOSOOC, DACOS01C and
DACOS02C are a direct replacement for the DAC-OS, DACOSA, DAC-OSC, DAC-OSE and DAC-OSH, respectively.
Features
•
•
•
•
•
•
•
•
•
•
The noise immune inputs of the DACOSOO series will accept
TTL levels with the logic threshold pin, VLC, grounded.
Changing the VLC potential will allow direct interface to other logic families. The performance and characteristics of the
device are essentially unchanged over the full ± 4.5V to
± 1SV power supply range; power dissipation is only 33 mW
with ± 5V supplies and is independent of the logic input
states.
100 ns
Fast settling output current
±1 LSB
Full scale error
±0.1%
Nonlinearity over temperature
±10 ppml'C .
Full scale current drift
-10V to +1BV
High output compliance
Complementary current outputs
Interface directly with TTL, CMOS, PMOS and others
2 quadrant wide range multiplying capability
Wide power supply range
± 4.5V to ± 1BV
Low power consumption
33 mW at ± 5V
• Low cost
Typical Applications
10V
DIGITAL INPUTS
'MS8
LSB'
¥yy?yyyy
10k
10k
lOUT
"':" : : :l:~:'f-·~l~·-D-A:-!i0.1-: -1 -'~2.34tL~- -
10V 0 ...
-
-4:-
-o)
. ...
3
1.
13
~'LLc~ tJ·~
-
~~'.F
VOUT TO 20
v,.,
1 2
r-
lOUT
TUH/5686-1
FIGURE 1. ±20 Vp_p Output Digltal-to-Analog Converter (Note 4)
Ordering Information
Non-Linearity
±0.1% FS
±0.1% FS
±0.19% FS
±0.19% FS
±0.39% FS
Temperature
Range
-55'C s: TA s: +125'C
O'C s: TA s: +70'C
-55'C S; TA S; +125'C
O'C S; TA s: +70'C
O'C s: TA s: +70'C
Order Numbers
J Package (J16A)*
DACOB02W
DACOB02LCJ
DACOBOOW
DACOBOOLCJ
DACOB01LCJ
DAC-OBAQ
DAC-OBHQ
DAC-OBQ
DAC-OBEQ
DAC-OBCQ
-Devices may be ordered by using either order number.
4-6
N Package (N16A)*
SO Package (M16A)
DACOB02LCN
DAC-OBHP
DACOB02LCM
DACOBOOLCN
DACOB01LCN
DAC-OBEP
DAC-OBCP
DACOBOOLCM
DACOB01LCM
Absolute Maximum Ratings
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
Surface Mount Package
Vapor Phase (60 seconds)
Infrared (15 seconds)
Is
tPLH,
tPHL
TCIFS
VOC
IFS4
IFSS
Izs
IFSR
VIL
VIH
I,L
I'H
V'S
VTHR
115
Parameter
Resolution
Monotonicity
Nonlinearity
Settling Time
Propagation Delay
Each Bit
All Bits Switched
Full Scale Tempco
260'C
300'C
215'C
220'C
Operating Conditions (Note 1)
Temperature (TA)
DAC0802L
DACOBOOL
DACOBOOLC
DACOB01LC
DACOB02LC
Electrical Characteristics The following specifications apply for Vs =
T MAX unless otherwise specified. Output characteristics refer to both lOUT and lOUT.
Symbol
~
(Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V+ - V-I
±18Vor36V
Power Dissipation (Note 2)
500mW
Reference Input Differential Voltage
V- toV+
(V14 to V15)
Reference Input Common-Mode Range
V- toV+
(V14, V15)
Reference Input Current
5mA
Logic Inputs
V- to V- plus 36V
Analog Current Outputs (Vs- = -15V)
4.25mA
ESD Susceptibility (Note 3)
TBDV
Storage Temperature
-65'Cto +150'C
8
8
To ± y. LSB, All Bits Switched
"ON" or "OFF", TA=25'C
DAC0800L
DAC0800LC
8
8
8
8
±0.1
100
135
C
1;
-55
-55
0
0
0
+125
+125
+70
+70
+70
'C
'C
'C
'C
'C
o
8
8
8
8
±0.19
DAC0801LC
Min
Typ
Max
8
8
8
8
8
8
±0.39
150
100
60
60
±50
-10
Output Voltage Compliance Full Scale Current Change
18
20 Mn Typ
Full Scale Current
VREF=10.000V, R14=5.000 kn 1.984 1.992 2.000
R1S=S.000 kn, TA=2S'C
Full Scale Symmetry
±O.S ±4.0
IFS4-IFS2
0.1
1.0
Zero Scale Current
V-=-5V
Output Current Range
0
2.0
2.1
V-=-8Vto-18V
0
2.0
4.2
Logic Input Levels
Logic "0"
0.8
VLC=OV
Logic "1"
2.0
Logic Input Current
VLC=OV
-2.0 -10
Logic "0"
-10VS:V,NS: +0.8V
Logic "1"
2VS:V,NS:+18V
0.002 10
V-=-1SV
Logic Input Swing
-10
18
-10
Logic Threshold Range
13.S
Vs= ±1SV
Reference Bias Current
-1.0 -3.0
100
100
135
150
35
35
±10
60
60
±SO
dlldt
Reference Input Slew Rate (Figure 12)
4.5VS:V+ s: 18V
~ Power Supply Sensitivity
-4.SVs:V-S:18V
PSSIFSIREF=1mA
Power Supply Current
Vs= ±SV, IREF= 1 mA
1+
1-
4.0
-10
1.94
0
0
oCIC)
N
Units
Bits
Bits
%FS
ns
ns
ns
18
35
35
±10
-10
60
ns
60
ns
±80 ppml"C
18
V
1.99
2.04 1.94
1.99
2.04
mA
±1
0.2
±8.0
2.0
±16
4.0
p.A
p.A
2.0
2.0
2.1
4.2
±2
0.2
2.0
2.0
2.1
4.2
mA
mA
0.8
V
V
-10
10
18
p.A
_p.A
0
0
0.8
2.0
2.0
-2.0
0.002
-10
-10
-1.0
-10
-2.0
10
0.002
18 -10
13.S -10
-3.0
-1.0
13.S
-3.0
V
V
0.01
8.0
0.0001
0.01
p.A
mAlp.s
0/0/%
0.01
0.0001
0.01
%1%
2.3
-4.3
3.8
-S.8
2.3
-4.3
3.B
-S.8
mA
mA
2.4
3.8
-6.4. -7.8
2.4
-6.4
3.8
-7.8
2.4
-6.4
3.8
-7.8
mA
mA
2.5
3.8
-6.S -7.8
2.S
-6.S
3.8
-7.8
2.S
-6.S
3.8
-7.8
rnA
mA
8.0
0.0001 0.01
8.0
0.0001
0.0001
2.3
3.8
-4.3 -S.8
0.0001 0.01
4.0
4.0
Vs=SV, -ISV, IREF=2 mA
1+
1-
Vs= ±1SV, IREF=2 mA
1+
1-
4-7
o
......
......
Units
TA=25'C
35
35
±10
~o
CIC)
Max
± 15V, IREF = 2 mA and T MIN s: T A s:
8
8
'"
Min
DAC0800L/
DAC0802LI
DAC0802LC
DAC0800LC
Min Typ Max Min Typ Max
Conditions
oCIC)
o
o
N
C)
co
C)
g
......
...
C)
co
C)
g......
C)
C)
co
C)
g
Electrical Characteristics (Continued)
± 15V,
The following specifications apply for Vs =
IREF = 2 rnA and T MIN';: T A ,;: T MAX unless otherwise specified. Output
characteristics refer to both lOUT and lOUT•
Symbol
Parameter
DAC0802LI
DAC0802LC
Conditions
Min
PD
Power Dissipation
±5V, IREF= 1 rnA
5V,-15V, IREF=2 rnA
±15V, IREF=2 rnA
DAC0800LI
DAC0800LC
Typ
Max
33
108
135
48
136
174
Min
DAC0801LC
Typ
Max
33
108
135
48
136
174
Min
Units
Typ
Max
33
108
135
48
136
174
rnW
rnW
rnW
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: The maximum junction temperature of the DACOBOO, DACOBOI and DACOB02 is 125"C. For operating at elevated temperatures, devices in the Dual·ln·Line
J package must be derated based on a thermal resistance of 100"C/W, junction·to·ambient. 175"C/W for the molded Dual-ln·Line N package and 1OO"C/W for the
Small Outline M package.
Note 3: Human body model, 100 pF discharged through a 1.5 kn resistor.
Note 4: Pin-out numbers for the DACOBOX represent the Dual-In-Line package. The Small Outline package pin·out differs from the Dual·ln·Line package.
Connection Diagrams
Dual-In-Line Package
THRESHOLO 1
CONTROL, VLC
Small Outline Package
y+
1
16
B8 LSB
VREF(+)
2
15
B7
16 COMPENSATION
•
'OUT
VREF(-)
3
14
B6
COMPENSATION
4
13
Bs
THRESHOLD CONTROL, VLC
5
12
B4
11
B3
v'OUT
MSB B'
lOUT
B2
y-
7
B3
lOUT
8
B4
10
B2
Bl MSB
B5
TL/H/5686-14
Top View
TLlH/5686-13
Top View
See Ordering Information
Block Diagram
4)
(Note
Msa
v'
BI
"
B4
"
B5
"
"
"B
"
15
VREFH ......, - - " " "
DACOI
"
COMP
y-
TLlH/5686-2
4-8
c
o>
o
Typical Performance Characteristics
00
Full Scale Current
vs Reference Current
LSB Propagation Delay Vs IFS
450
«
.s...
"
'"'"
"...
"...
",
0
TA '" TMIN TO TMAX
6
ALL BITS
HIG~
,
LIMIT FOR
-V" -15V
5
4
/
l50
"
0
~
LIMIT FOR-
v" -5V -
./
>-
1/
/
1
400
g
/
2
0
-I--I-
]
r--f--f--
/
3
-
1
2
3
4
-
200
100
~
50
150
IlSB=7.8/JA
III IJII
0
0.010.2 0.050.10.02 0.5 1
5
2
I"-
g
5 10
C
o>
o
2
'\
,
} '{J~
00
o
N
0.1
0.2
0.5
'FS - OUTPUT FULL SCALE CURRENT (rnA)
'REF - REFERENCE CURRENT (rnA)
00
....o
......
,/
"
llSB = 78 nA
C
o>
o
R14'" R1S" lk
Rl::::, 500
All BITS "ON"
VRt5" OV
"...
250
o
......
Frequency Response
12
10
8
6
4
2
0
0
-2
> -4
0::
-6
-8
-10
-12
-14
--...
300
i,
V
0
o
Reference Input
1
2
10
5
FREOUENCY (MHz)
Curve 1: Cc~15 pF, VIN~2 Vp-p
centered at 1V.
Curve 2: Cc~15 pF, VIN~50 mVp-p
centered at 200 mY.
Curve 3: Cc~O pF, VIN~ 100 mVp-p
at OV and applied through 50 n connected to pin 14.2V applied to R14.
Reference Amp
Logic Input Current
Common-Mode Range
vs Input Voltage
.,
4
«
.s...
"
'"'"
..."
~
"
l.6
3.2
I
I
2.8
2.4
2
g
1.6
I
0.8
E
TA = TMIN TO TMAX
ALL 8ITS"ON"
-"
...
i
I
+V= 15V
V=-15V -V=-5V
-
IREF"lmA
IRE~·012mA-
0.4
0
-14 -10 -6
-2
2
6
10
14
~
4
~
IREF = 2 rnA
1.2
6
~,
>
,
.-
2
...
>"
l
0
-12-10-8 -6-4-2 02 4 6 81012141618
18
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
VLC vs Temperature
"-
-50
r--
"-
50
0
100
150
TA - TEMPERATURE ( CI
Vi - LOGIC INPUT VOLTAGE (VI
VIS - REFERENCE COMMON-MOOE VOLTAGE IVI
VTH -
Note. Positive common-mode range is
always (V+) -
1.5V
Output Current vs Output
Voltage (Output Voltage
Output Voltage Compliance
vs ,,,.,,
Compliance)
2.8
«
.s...
"
'"
"'"u
...
"
",
ALL BITS "ON"
2.4
2
-V;-IJV
20
~
~V'~5V
w
IREF=2mA
1.2
~
0.8
E
0.4
I
""
~
>
~
tREIF "limA
~,
~
I
16
12
~ ~~
8
SHp~~~:S~~8EtE I~~~;~~ES: -I--
4
-i-
0
VOLTAGE RANGE FOR
-V = -15V, JREF::;; 2 rnA.
I- FOR ,0~~~EttG~~~~R~ ~REF'
-I--
-4
0
>
IRE)" D.2 mA
0
-14 -10 -6
1.4
TA -TMIN TO TMAX
II
1.6
-8
m,-'I\.'-'I\.'-'l:
~
-12
-2
Bit Transfer
Characteristics
,""""'U' "
2
6
10
14
Vo - OUTPUT VOLTAGE (VI
18
-50
0
50
100
TA - TEMPERATURE rCI
150
«
.s...
~
B
...
"
1.2
IREF =2mA
811
1
0.8
,12
0.6
~,
0.4
!2
0.2
-V, 15V
H-It- -V,
5V
'l
84
-l:'
-1i
0
-12-10-8-6-4-20 24 6 8 1012141618
VL - LOGIC INPUT VOLTAGE (VI
TL/H/5686-3
Note. 81-88 have identical transfer characteristics_ Bits are fully switched with less than
y, LSB
error, at less than ± 100 mV from actual threshold. These switching paints are guaranteed to lie
between 0.8 and 2V over the operating temperature range (VLC ~ OV).
4-9
Typical Performance Characteristics
Power Supply Current
vs +y
(Continued)
Power Supply Current
vs Temperature
Power Supply Current
vs -y
I- -r-II-~IT~IR~F'~mA--
;;
A
r--- ~UITJIR~F'U--
i
ALL BITS MAY BE HIGH OR LOW
ALL BITS HIGH OR LOW
l-
l-
~
'"~
4
6
~
1+
I
o
2
8 10 12 14 16 18 20
I I
-I-
r-1v J
I
-1;V
1-1- I-~V!15~
1+-
JI
J I
;;:
-50
o -2 -4 -6 -B -10-12-14-16-1B-20
1-)-
I I I
I I I
.1
50
100
150
TA - TEMPERATURE ("CI
V - NEGATIVE POWER SUPPLY IVI
Vcc - POSITIVE POWER SUPPL Y IVI
ALL 81TS HIGH OR LOW
IREF;2mA
~
I~WltH I~EFI. 0.1 mA
It
10
TL/H/5686-4
Equivalent Circuit
-v
TL/H/5686-15
Typical Applications
FIGURE 2
(Continued)
DIGITAL INPUTS
MSB
Lsa'
Bl B2 838485 B6 87 B8
10
+R~::F x ~~:
iO = IFS for all
logic states
~I,if
A15
IFS '"
10 +
For fixed reference, TIL operation,
typical values are:
-VREF
if'
VREF
= 10.000V
RREF
=
5.000k
R15 '" RREF
Cc = 0.01 /LF
VLC
-v
=
OV (Ground)
TLlH/5686-5
FIGURE 3. Basic Positive Reference Operation (Note 4)
DACDIOO
DACUIOIl
"15
TLlH/5686-16
IFS '" -VREF x 255
RREF
256
TL/H/5686-21
Note. RREFsets IFS; R15 is
for bias current cancellation
FIGURE 5. Basic Negative Reference Operation (Note 4)
FIGURE 4. Recommended Full Scale Adjustment Circuit
(Note 4)
4·10
c
~
C
Typical Applications (Continued)
co
DIGITAL INPUTS
MSB
C
C
LSa'
81 B2 BJ B4 B5 B6 81 BI
EO
~
C
...
co
C
IREF=ZmA
......
C
~
c
TLlH/5686-17
B1 B2 B3 B4 B5 B6 B7 B8 lornA
1 1
1
1
1 1
1 1 1.992
1
1 1
1
1
1 1 0 1.984
1 0
0
0
0
0 0
1 1.008
Half Scale
1 '0
0
0
0
0 0 0 1.000
Half Scale - LSB
0
1 1
1
1
1 1 1 0.992
Zero Scale + LSB 0
0
0 0
0
0 0
1 0.008
Zero Scale
0 0
0
0 0
0
0 0 0.000
Full Scale
Full Scale - LSB
Half Scale + LSB
co
lornA
Eo
Eo
0.000 -9.960 0.000
0.008 -9.920 -0.040
0.984 -5.040 -4.920
0.992
1.000
1.984
1.992
-5.000
-4.960
-0.040
0.000
-4.960
-5.000
-9.920
-9.960
FIGURE 6. Basic Unipolar Negative Operation (Note 4)
r-------;;I,"'.~&-.Je~~ +lD.ODOV
"
DACDBOD
Iii •
TL/H/5686-6
B1 B2 B3 B4 B5 B6 B7 B8
Eo
Eo
POs. Full Scale
1 1 1 1 1 1 1 1 -9.920 +10.000
POs. Full Scaie-LSB 1 1 1 1 1 1 1 0 -9.840 +9.920
1 0 0 0 0 0 0 1 -0.080 +0.160
Zero Scale + LSB
Zero Scale
1 0 0 0 0 0 0 0
0.000
+0.080
Zero Scale - LSB
0.000
0 1 1 1 1 1 1 1 +0.080
Neg. Full Scale+ LSB 0 0 0 0 0 0 0 1 +9.920 -9.840
Neg. Full Scale
0 0 0 0 0 0 0 0 +10.000 -9.920
FIGURE 7. Basic Bipolar Output Operation (Note 4)
Sk
R,
I, •
Eo '" VREF (-Z55
'Ts6 + i5'2X)
6
DACDIOO
Iii
where X is the input code and
2
RL·~ FiL ~ RREF
TL/H/5686-18
If RL ~
Fii: within ± 0.05%, output is symmetrical about ground
B1 B2 B3 B4 B5 B6 B7 B8
Pos. Full Scale
Pos. Full Scale-LSB
( + )Zero Scale
( - )Zero Scale
Neg. Full Scale+ LSB
Neg. Full Scale
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
EO
+9.960
+9.880
+0.040
-0.040
-9.880
-9.960
FIGURE 8. Symmetrical Offset Binary Operation (Note 4)
4-11
C
N
Typical Applications (Continued)
DACOBDD
255
256 IREF
TLIH/5686-19
For complementary output (operation as negative logic DAC), connect invertIng Input of OP amp to iO (pin 2), connect 10 (pin 4) to ground.
FIGURE 9. Positive Low Impedance Output Operation (Note 4)
255
IFS '" 256 IREF
DActllla
"
TL/H/5686-20
For complementary output (operation as a negative logic DAC) connect non·inverting input of op am to iO (pin 2); connect 10 (pin 4) to ground.
FIGURE 10. Negative Low Impedance Output Operation (Note 4)
VTH
= VLC +
l.4V
15V CMOS, HTL, HNIL
= 7.6V
VTH
I'MO'
VTH=DV
t
I
VLC
&.2V
ZENER
":'"
!·
fr,··..
12V TO::
Vu:
Uk
":'"
':"
T":"
G.1"F
I
I
I
IDk
"'REF
9
-SVTO-IDV
RREF
-5v~-+-~_-T--oo~--VTH-UV
I
Vn,-SV
I
I
I
I
I
I
R'N
r:-------~_1-'\1""'...,
o-JltJ.,.,.-+-.-.....
'4
VTM ,,--utv
DVIl.
I.3k
3.11<
-SlV
REO -200
DACOSOD
Rp
NO tAP
n
Il.
I
I
~{OPTI0NAL
RESISTOR
~ FOR OFFSET 'NPUTS
TL/H/5686-10
VLe
TL/H/5688-9
Note. Do not exceed negative logic input range of DAC.
FIGURE 12, Pulsed Reference Operation (Note 4)
FIGURE 11. InterfaCing with Various logic Families
4·12
Typical Applications
~
(Continued)
io
o
.....
(a) IREF ~ peak negative swing of liN
~
(b)
-
+ VREF must be above peak positive swing of VIN
'VREf o-_>l'r--t 14
liN
VIN~
~
DACOIOO
A15
VIN~
o
IOPTIONAL!
o-JII\h--t15
CD
o
N
HIGH INPUT------.
DACOBOO
IMPEDANCE
TL/H/5686-12
TL/H/5686-11
FIGURE 13. Accommodating Bipolar References (Note 4)
,...-1
FORTURN "ON", VL =2.IV V C........
FOR TURN "OFF", VL =o.IV
L
5V
HPSOBH800
SCHOTTKY DIODES
-,::O.4V
VOUT
1 X PROBE
VCLo-+-_......
o.IV
OV
OV
L-
O.4V
15k
2k
lOOk
R15
_"""'\1\00--115
13
T
-
DAC0800
ID.U.T.I
lOUT
-15V
TO o.U.T.
O.l "F
15V
-15V
TL/H/5686-7
FIGURE 14. Settling Time Measurement (Note 4)
4-13
o
!....
.....
I
Typical Applications
(Coot;,,,_
.....
.....
r5V STOP
CONVERSION
ov -I
CI
~
FREE
RUN
16
5V
§
Vee
OMI501
SAR
CI
~
GNO
OD 01 OZ Q3 04 05 08 07
3 4 5 8 1111 13 14
'='
LSB
t
15V
5V
B·BIT DIGITAL
WORD
15V
R4
UM
MSB
RI
VREF
"
RZ
5k
'='
R3
&k
lk
12 11 10 9 I 7 & 5
14 LS8 87 86 85 84 83 82 MS8
2
VR+
Iii
DACOlOO
1k
15 VR-
-15V
&1
-15V
lOOk
Note. For I ,",S conversion time with S·bit resolution and 7·bit accuracy, an
LM361 comparator replaces the LM319 and the reference current i. doubled
by reducing RI, R2 and R3 to 2.5 kn and R4 to 2 Mn.
TLIH/S686-8
FIGURE 15. A Complete 2 p.s Conversion Time, a·Blt AID Converter (Note 4)
4·14
Ij
~
NatiOnal
Semiconductor
Corporation
C)
CO
Q
CO
.....
~
DAC0808, DAC0807, DAC0806 8-Bit D/A Converters
C)
General Description
CO
The DACOBOB series is an B-bit monolithic digital-to-analog
converter (DAC) featuring a full scale output current settling
time of 150 ns while dissipating only 33 mW with ± 5V supplies. No reference current (IREF) trimming is required for
most applications since the full scale output current is typically ± 1 LSB of 255 IREF! 256. Relative accuracies of better than ±0.19% assure B-bit monotonicity and linearity
while zero level output current of less than 4 ",A provides
B-bit zero accuracy for IREF:<:2 rnA. The power supply currents of the DACOBOB series are independent of bit codes,
and exhibits essentially constant device characteristics over
the entire supply voltage range.
The DACOBOB will interface directly with popular TIL, DTL
or CMOS logiC levels, and is a direct replacement for the
MC150B!MC140B. For higher speed applications, see
DACOBOO data sheet.
C)
•
•
•
•
•
C)
Relative accuracy: ± 0.19% error maximum (DACOBOB)
Full scale current match: ± 1 LSB typ
7 and 6-bit accuracy available (DACOB07, DACOB06)
Fast settling time: 150 ns typ
Noninverting digital inputs are TIL and CMOS compatible
• High speed multiplying input slew rate: B mAl
• Power supply voltage range: ± 4.5V to ± lBV
• Low power consumption: 33 mW @ ± 5V
"'S
...
Dual-In-Line Package
Y¥ y y y y y y
RANGE
CONTROL
II
R-2RLADD£R
VAEf!"'1
VREF(-) V'
L..
Nt INOTE 3)..l.
....",.
CURRENT SWITCHES
alAS CIRCUIT
~ NPNCU~~
SOURCE PAIR
REF~NCE ~
.~
CURRENT AMP
Order Number
DAC0808,DAC0807,
orDAC0806
See NS Package
NumberJ16A,
M16AorN16A
•ND
ro
Vee
U
GNO..!.
'D-..!
Msa A1..!.
Tl/H/5687-1
~&OMPENSATION
r!!-VREFI_I
v., 2.
~VREFf+)
DACDID•
SERIU
f1!.. vcc
r!!-AI LSI
r!!-Al
u...!.
.,.2.
~A6
~.,
•• ..!
r-oCOMPEN
V~E
~
Features
Block and Connection Diagrams
MSB
~
C
TOP VIEW
TLlH/5887-2
Small-Outline Package
Vcc - l
16 f-AS ,SB
VREF (+)- 2
15 r-A7
VREF (-)- 3
COMPENSATION- ~
14 f-A6
13 f-AS
NC- 5
121-M
11 f-AS
10 f-A2
91-Al MSB
GND- 6
Va- 7
10- 8
Tl/H/5687-13
Top View
Ordering Information
ACCURACY OPERATINGTEMPERATURE~______________.-~O~R~D~E~R~N~U~M~B~E~R~S~--r-------------RANGE
J PACKAGE (J16A)*
N PACKAGE (N16A)*
SO PACKAGE (M16A)
B-bit
-55'C,;;TA,;;+125'C
DACOBOBLJ MC150BLB
B-bit
DACOBOBLCM
O'C,;;TA,;;+75'C
DACOBOBLCJ MC140BLB DACOBOBLCN MC140BPB
DACOB07LCJ MC140BL7 DACOB07LCN MC140BP7
DACOB07LCM
7-bit
O'C,;;TA,;;+75'C
DACOB06LCJ MC140BL6 DACOB06LCN MC140BP6
DACOB06LCM
6-bit
O'C,;;TA,;;+75'C
·Note. Devices may be ordered by using either order number.
4-15
CO
en
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications_
Power Supply Voltage
Vec
VEE
Digital Input Voltage, VS-V12
-10Vocto +1SVoc
Applied Output Voltage, Va
-11 Vocto + 1S Voc
Storage Temperature Range
+1SVoc
-1SVoc
Reference Current, 114
Power Dissipation (Note 3)
Vcc, VEE
1000mW
ESD Susceptibility (Note 4)
TBD
260'C
300'C
21S'C
220'C
Operating Ratings
SmA
Reference Amplifier Inputs, V14, V1S
-6S'Cto +1S0'C
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (Plastic)
Dual-In-Line Package (Ceramic)
Surface Mount Package
Vapor Phase (60 seconds)
Infrared (1S seconds)
TMIN ~ TA ~ TMAX
-SS'C ~ TA ~ +12S'C
o ~TA ~ +7S'C
Temperature Range
DACOSOSL
DACOSOSLC Series
Electrical Characteristics
(Vcc = SV, VEE = -1S Voc, VREF/R14 = 2 mA, DACOSOS: TA = -SS'Cto + 12S'C, DACOSOSC, DACOS07C, DACOS06C, TA
= O'C to + 7S'C, and all digital inputs at high logic level unless otherwise noted.)
Symbol
Er
Parameter
Conditions
T A = 2S'C (Note 6),
(Figure 5)
TA
=
tpLH, tpHL
Propagation Delay Time
TClo
Output Full Scale Current Drift
MSB
VIH
VIL
Digital Input Logic Levels
High Level, Logic "1"
Low Level, Logic "0"
(Figure 3)
MSB
Digital Input Current
High Level
Low Level
(Figure 3)
VIH = SV
VIL = O.SV
Reference Input Bias Current
{Figure 3)
Output Current Range
{Figure 3)
VEE = -SV
VEE = -1SV, TA = 2S'C
115
10
Output Current
Output Current, All Bits Low
Output Voltage Compliance (Note 2)
VEE= -SV, IREF= 1 mA
VEE Below -1 OV
Min
Typ
Max
{Figure 4)
Relative Accuracy (Error Relative
to Full Scale 10)
DACOSOSL (LM1S0S-S),
DACOSOSLC (LM140S-S)
DACOS07LC (LM140S-7), (Note S)
DACOS06LC (LM140S-6), (Note S)
Settling Time to Within % LSB
(I ncludes tpLH)
%
±0.19
%
±0.39
±0.7S
%
%
ns
1S0
2S'C, (Figure 5)
30
100
ns
ppml'C
±20
2
VREF = 2.000V,
R14 = 10000,
(Figure 3)
(Figure 3)
Units
O.S
Voc
Voc
0
-0.003
0.040
-O.S
mA
mA
-1
-3
/LA
0
0
2.0
2.0
2.1
4.2
mA
rnA
1.9
1.99
0
2.1
4
mA
/LA
-O.SS, +0.4
-S.O, +0.4
Voc
Voc
Er ~ 0.19%, TA = 2S'C
4-16
Electrical Characteristics (Continued)
(Vcc = 5V, VEE = -15 VDC, VREF/R14 = 2 mA, DAC0808: TA = -55'Cto + 125'C, DAC0808C, DAC0807C, DAC0806C, TA
= O'C to + 75'C, and all digital inputs at high logic level unless otherwise noted.)
Symbol
Parameter
SRIREF
Reference Current Slew Rate
(Figure 6)
Conditions
Output Current Power Supply
Sensitivity
-5V';; VEE';; -16.5V
Power Supply Current (All Bits
Low)
(Figure 3)
Min
Typ
4
8
Icc
lEE
Power Supply Voltage Range
,
0.05
2.7
MAN
2.3
-4.3
22
-13
mA
mA
5.0
-15
5.5
-16.5
VDC
VDC
33
106
90
160
170
305
mW
mW
mW
mW
4.5
-4.5
VCC
VCC
VCC
VCC
All Bits High
Units
mAIMs
T A = 25'C, (Figure 3)
Vcc
VEE
Power Dissipation
All Bits Low
Max
=
=
=
=
5V, VEE = -5V
5V, VEE = -15V
15V, VEE = -5V
15V, VEE = -15V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operatin'g conditions.
Nole 2: Range control is not required.
Nole 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, 8JA, and the ambient temperature, TA' The maximum
allowable power dissipation at any temperature is Po = (TJMAX - TA)/OJA or the number given in the Absolute Maixmum Ratings. whichever is lower. For this
device, TJMAX = 12S'C, and the typical iunction·to·ambient thermal resistance of the dual·in·line J package when the board mounted is 100'C/W. For the dual·in·
line N package, this number Increases to 175'C/W and for the small outline M package this number is 100'C/W.
Nole 4: HUman body model, 100 pF discharged through a 1.5 kn resistor.
Note 5: All current switches are tested to guarantee at least 50% of rated current.
Nole 6: All bits switched.
Nole 7: Pin·out numbers for the DAL080X represent the dual·in·line package. The small outline package pinout differs from the dual·in·line package.
Typical Application
13
f"""'D-_'",'O,,,",,'- - - 0 lD.DDOV=VREF
MSI Ale-;
.,~
DIGITAL
INPUTS
::~
A'~
5k
'~l ;>1',"00
OACOIOI;'
~'~-----4';-
A7~
ro-,
LSI Alo1!
Va
LF3S1
T'
=r
6
0
""
f+
Vo=10V
OUTPUT
(A1
A2
A8)
"2+"4+" '256
vEE" -15V
FIGURE 1.
TL/H15687-3
+ 10V Output Digital to Analog Converter (Note 7)
4·17
Typical Performance Characteristics
=
Vee
5V, VEE
=
=
-15V, TA
25°C, unless otherwise noted
Logic Input Current vs
Input Voltage
Bit Transfer Characteristics
1.4
"oSill....
=
~
!;
I
I
..=
0.6
I 11
!:
0.2
H-Ii
6
I I
I
AL~BITrON"
0
I
VEE" -5vl
II
~
!t~
-1t'
~
:::
I
0.4
D.!
~
~
111D.L
14
"ill
~
t
lEE
iii
4.0
= 2.0
-8
1.0
~
- ' - f-
Y
L-L.,..JL.......I--L-J.-J.-L.................I
50
-50
18
100
150
-SO
TEMPERATURE ('C)
Typical Power Supply
Current vs VEE
-
3.0
-4
Vo - OUTPUT VOLTAGE (V)
ALL 81TS HIGH DR LOW
ALL BITS HIGH DR LOW
1'4"'2 mA
oS
.... 6.0
5.0
=
~
-12
o
Typical Power Supply
Current vs Temperature
B.O
~
..
& 10
...... r-.,
TA - TEMPERATURE ('C)
7.0
12
......r-.,
-55 -31-19 -1 17 35 53 71 a9 107125
16
w
0.8
!: 0.4
......
a
20 ~~~-r-r'-~~~
'"~
I
2
12
Output Voltage Compliance
vs Temperature
~
1'4"'2mA
1!4.,1mA
-14 -10 -& -2
"
.
~
2.4
VEE -15V
g
--
VL - LOGIC INPUT VOLTAGE (V)
Output Current vs Output
Voltage (Output Voltage
Compliance)
= 1.6
~....
= 1.2
I!:
A3
A4
-Vo-5V
2
1.8
1.6
1.4
-12-10-8-&-4-2024 & 81012141618
VL - LOGIC INPUT VOLTAGE (V)
"oSill....
~
~2
1.11
-12-10-B-6-4-20 246 Bl01214161B
2.B
~,
-v- -lSV
OA
I
~
~
DB
I!:
AI THROUGH AB
"4-2mA
1.2
Logic Threshold Voltage vs
Temperature
-
ALL 81TS HIGH DR LOW
',4"ZrnA
_f-:-"EE'W'T~ 11~ - 2 rnA
100
150
Reference Input
Frequency Response
Typical Power Supply
Current vs Vee
.1 ,J- I-
50
TEMPERATURE rC)
lEE
- I - IE'E WiTH!) I JA - I -
I
8
'-A
I'\.
'\
- f - lEE WITH "4'0.2 rnA
ICC
o
II
0-2 -4 -6 -B -10-12-14-1&-18-20
VEE - NEGATIVE POWER SUPPLY (V)
C
'fC
a
a
-14
-1&
2
4 6
8 10 12 14 16 18 ZO
VCC - POSITIVE POWER SUPPLY (V)
0.1
0.3
10
f - FREQUENCY (MHz)
TL/H/5687-5
Unless otherwise specified: R14 =
R15 = 1 kO, C = 15 pF, pin 16 to
VEE; RL = 500, pin 4 to ground,
Curve A: Large Signal Bandwidth
Method of Figure 7, VREF = 2 Vp-p
offset 1 V above ground,
Curve B: Small Signal Bandwidth
Method of Figure 7, RL = 2500, VREF
= 50 mVp-p offset 200 mV above
ground.
Curve C: Large and Small Signal
Bandwidth Method of Figure 9 (no op
amp, AL = 500), As = 500, VREF =
2V, Vs = 100 mVp-p centered at OV.
4-18
Vee
MS'
GND
AI
~
1J
A2
A3
A4
A.
A'
1D
Al
"
~9TPUT
A6
A'
A'
( A1
AN = "0" if AN is at low level
'EEl
VEE
TL/H/56B7-6
FIGURE 3. Notation Definitions Test Circuit (Note 7)
.sa
AI
A'
BaIT
COUNTER
TL/H/56B7-7
FIGURE 4. Relative Accuracy Test Circuit (Note 7)
"N
"
15
,.
UV--.,..-----"""'
D.4V
2Voc
"
D.1V
USE Rl TO OND FOR TURN "OFF"
MEASUREMENT (SEE TEXTI
SETTLING TIME
"T'D.1/o1F
,,(FIGURE 5)
1k~
fOR SETTLING TIME
t,-1&DnsTYP
10 :t11lLSI
t-'-'D---....-t-OOeo :~~~~M:: i~l~,~~JS
~CO$;25PF
TRANSIENT
RESPONSE
1N44M (LOW CAPACITANCE,
FAST RECOVERY DIODE)
-----..Ij
Al-sD
PlNUD OND
-l00mV---W.....
TUH/56B7-B
FIGURE 5. Transient Response and Settling Time (Note 7)
4-20
C
l>
0Q
Test Circuits (Continued)
Vee
vee
CD
Q
CD
.....
R142> R15
Al
j..;.;.o-_M-"II~O VREF
- nL-
2V
o .....J
R14
R15
A2
15
AJ
1
Q
A6
A7
Q
1ii "'LI
CD
RL
AS
":'
SLEWING
TIME
dl
SEE TEXT FOR VALUES OF e
dV
VEE
dt"=Ridi"
TL/H/56B7-10
FIGURE 7. Positive VREF (Note 7)
TL/H/56B7-9
FIGURE 6. Reference Current Slew Rate Measurement (Note 7)
Vee
Vs
R14" R15
RS
R14
Al
A2
15
R14
H15
"",.....-D
t-<>-......
AJ
""'-IVV\I-O
":'
-VRE F
vnEF
""L...1"
A4
A5
Al
A6
A2
A7
A3
AS
A4
A5
When Vs = 0,114 = 2.0 mA
VREF
VO= [ - + -Vs ] ( A ) RO
R14
RS
A6
A7
SEE TEXT FOR VALUES OF e
AS
RO
VEE
TL/H/56B7-11
FIGURE 8. Negative VREF (Note 7)
TL/H/56B7-12
FIGURE 9. Programmable Gain Amplifier or
Digital Attenuator Circuit (Note 7)
Application Hints
REFERENCE AMPLIFIER DRIVE AND COMPENSATION
The reference amplifier provides a voltage at pin 14 for converting the reference voltage to a current, and a turn-around
circuit or current mirror for feeding the ladder. The reference
amplifier input currrent, 114, must always flow into pin 14,
regardless of the set-up method or reference voltage polarity.
R15 can be tied to a negative voltage corresponding to the
minimum input level. It is possible to eliminate R15 with only
a small sacrifice in accuracy and temperature drift.
The compensation capacitor value must be increased with
increases in R14 to maintain proper phase margin; for R14
values of 1, 2.5 and 5 kn, minimum capacitor values are 15,
37 and 75 pF. The capacitor may be tied to either VEE or
ground, but using VEE increases negative supply rejection.
Connections for a positive voltage are shown in Figure 7.
The reference voltage source supplies the full current 114.
For bipolar reference signals, as in the multiplying mode,
4-21
CD
......
.....
C
l>
0Q
A5
2m!tr--'
.I""1..
2
A4
SCOPE
'VREF
C
l>
0Q
Q)
U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
CI
CD
CI
g
i
CI
g
U;
CI
g
Application Hints (Continued)
A negative reference voltage may be used if R14 is grounded and the reference voltage is applied to R15 as shown in
Figure 8. A high input impedance is the main advantage of
this method. Compensation involves a capacitor to VEE on
pin 16, using the values of the previous paragraph. The negative reference voltage must be at least 4V above the VEE
supply. Bipolar input signals may be handled by connecting
R 14 to a positive reference voltage equal to the peak positive input level at pin 15.
When a DC reference voltage is used, capacitive bypass to
ground is recommended. The 5V logic supply is not recommended as a reference voltage. If a well regulated 5V supply which drives logic is to be used as the reference, R14
should be decoupled by connecting it to 5V through another
resistor and bypassing the junction of the 2 resistors with
0.1 /-LF to ground. For reference voltages greater than 5V, a
clamp diode is recommended between pin 14 and ground.
If pin 14 is driven by a high impedance such as a transistor
current source, none of the above compensation methods
apply and the amplifier must be heavily compensated, decreasing the overall bandwidth.
OUTPUT VOLTAGE RANGE
The voltage on pin 4 is restricted to a range of -0.55 to
0.4V when VEE = -5V due to the current switching methods employed in the DAC0808.
the excellent temperature tracking of the monolithic resistor
ladder. The reference current may drift with temperature,
causing a change in the absolute accuracy of output current. However, the DAC0808 has a very low full-scale current drift with temperature.
The DAC0808 series is guaranteed accurate to within ± %
LSB at a full-scale output current of 1.992 mAo This corresponds to a reference amplifier output current drive to the
ladder network of 2 mA, with the loss of 1 LSB (8 /-LA) which
is the ladder remainder shunted to ground. The input current
to pin 14 has a guaranteed value of between 1.9 and 2.1
mA, allowing some mismatch in the NPN current source
pair. The accuracy test circuit is shown in Figure 4. The 12bit converter is calibrated for a full-scale output current of
1.992 mAo This is an optional step since the DAC0808 accuracy is essentially the same between 1.5 and 2.5 mAo Then
the DAC0808 circuits' full-scale current is trimmed to the
same value with R14 so that a zero value appears at the
error amplifier output. The counter is activated and the error
band may be displayed on an oscilloscope, detected by
comparators, or stored in a peak detector.
Two 8-bit D-to-A converters may not be used to construct a
16-bit accuracy D-to-A converter. 16-bit accuracy implies a
total error of ± % of one part in 65,536 or ± 0.00076%,
which is much more accurate than the ±0.019% specification provided by the DAC0808.
The negative output voltage compliance of the DAC0808 is
MULTIPLYING ACCURACY
extended to - 5V where the negative supply voltage is more
The DAC0808 may be used in the multiplying mode with
negative than -10V. Using a full-scale current of 1.992 mA
8-bit accuracy when the reference current is varied over a
and load resistor of 2.5 kn between pin 4 and ground will
range of 256:1. If the reference current in the multiplying
yield a voltage output of 256 levels between 0 and
mode 'ranges from 16 /-LA to 4 mA, the additional error con-4.980V. Floating pin 1 does not affect the converter
speed or power dissipation. However, the value of the load . tributions are less than 1.6 /-LA. This is well within 8-bit accuracy when referred to full-scale.
resistor determines the switching time due to increased voltage swing. Values of RL up to 5000. do not significantly
A monotonic converter is one which supplies an increase in
affect performance, but a 2.5 kn load increases worst-case
current for each increment in the binary word. Typically, the
settling time to 1.2 /-Ls (when all bits are switched ON). Refer
DAC0808 is monotonic for all values of reference current
to the subsequent text section on Settling Time for more
above 0.5 mA. The recommended range for operation with
a DC reference current is 0.5 to 4 mAo
details on output loading.
OUTPUT CURRENT RANGE
SETTLING TIME
The output current maximum rating of 4.2 mA may be used
only for negative supply voltages more negative than -8V,
due to the increased voltage drop across the resistors in the
reference current amplifier.
The worst-case switching condition occurs when all bits are
switched ON, which corresponds to a low-to-high transition
for all bits. This time is typically 150 ns for settling to within
± % LSB, for 8-bit accuracy, and 100 ns to % LSB for 7 and
6-bit accuracy. The turn OFF is typically under 100 ns.
These times apply when RL S; 5000. and Co S; 25 pF.
ACCURACY
Absolute accuracy is the measure of each output current
level with respect to its intended value, and is dependent
upon relative accuracy and full-scale current drift. Relative
accuracy is the measure of each output current level as a
fraction of the full-scale current. The relative accuracy of the
DAC0808 is essentially constant with temperature due to
Extra care must be taken in board layout since this is usually
the dominant factor in satisfactory test results when measuring settling time. Short leads, 100 /-LF supply bypassing
for low frequencies, and minimum scope lead length are all
mandatory.
4-22
~
~ Semiconductor
NatiOnal
CI
CD
Co)
Corporation
CI
......
~
DAC0830/DAC0831/DAC0832 8-Bit JLP
Compatible, Double-Buffered D to A Converters
CI
CD
.....
......
Co)
General Description
Features
The DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplying
DAC designed to interface directly with the 8080, 8048,
8085, Z80®, and other popular microprocessors. A deposited silicon-chromium R-2R resistor ladder network divides
the reference current and provides the circuit with excellent
temperature tracking characteristics (0.05% of Full Scale
Range maximum linearity error over temperature). The circuit uses CMOS current switches and control logic to
achieve low power consumption and low output leakage
current errors. Special circuitry provides TTL logic input voltage level compatibility.
• Double-buffered, single-buffered or flow-through digital
data inputs
• Easy interchange and pin-compatible with 12-bit
DAC1230 series
• Direct interface to all popular microprocessors
• Linearity specified with zero and full scale adjust onlyNOT BEST STRAIGHT LINE FIT.
• Works with ± 10V reference-full 4-quadrant
multiplication
• Can be used in the voltage switching mode
• Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)
• Operates "STAND ALONE" (without ,...P) if desired
• Available in 20-pin small-outline or molded chip carrier
package
Double buffering allows these DACs to output a voltage corresponding to one digital word while holding the next digital
word. This permits the simultaneous updating of any number of DACs.
The DAC0830 series are the 8-bit members of a family of
microprocessor-compatible DACs (MICRO-DACTM). For applications demanding higher resolution, the DAC1000 series
(10-bits) and the DAC1208 and DAC1230 (12-bits) are available alternatives.
Key Specifications
1 ,...S
8 bits
8,9, or 10 bits
• Current settling time
• Resolution
• Linearity
(guaranteed over temp.)
• Gain Tempco
• Low power dissipation
• Single power supply
0.0002% FS/"C
20 mW
5 to 15 Voc
Typical Application
CONTROL BUS
'Allows easy upgrade to 12-blt DAC1230,
See application hints
cs
'lE'
DB7
~
VOUT
DOD
Lsa
8080 BUS
TL/H/5608-1
Connection Diagrams (Top Views)
Molded Chip Carrier Package
Dual-In-Llne and
Smail-Outline Packages
cs
tThis is necessary for the
zo
Vee
19
Iu (IYTE1/BYTEl)t
12·bit DAC1230 series to
'LE (BYTEI / BYTE2)t
permit interchanging from
vee
XFER
an B·bit to a 12·bit DAC
Dh
"
"
Wiii
15
01,
D10fLSBJ
14
01,
and no software changes,
13
Dh[MSB)
See applications section.
"
loun
1-
WR,
"0
17
01,
01,
VREF
RIO
GND
10
"
01,
with No PC board changes
Dl7 (MSB)
20
12
cs
1
11
IOUlI
lYR,
2
10
GND
GND
3
9
Rib
4
5
6
7
'DUll
8
TLlH/5608-22
IOUlI
TL/H/5608-21
4-23
g
oCI
CD
Co)
N
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and speclfications_
Supply Voltage {Vee>
Voltage at Any Digital Input
Lead Temperature (soldering, 10 sec.)
Dual-In-Line Package (plastic)
Dual-in-Line Package (ceramic)
Surface Mount Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
17VDe
VeetoGND
±25V
Voltage at VREF Input
Storage Temperature Range
215'C
220'C
Operating Conditions
- 65'C to + 150'C
Package Dissipation
at TA = 25'C (Note 3)
DC Voltage Applied to
IOUT1 or IOUT2 (Note 4)
ESD Susceptability (Note 14)
260'C
300'C
Temperature Range
Part numbers with 'LCN' suffix
Part numbers with 'LCWM' suffix
Part numbers with 'LCV' suffix
500mW
-100 mVto Vee
800V
Part numbers with 'LCJ' suffix
Part numbers with 'LJ' suffix
Voltage at Any Digital Input
TMIN:5:TA:5:TMAX
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
-40'Cto +85'C
-55'Cto +125'C
VeetoGND
Electrical Characteristics
VREF= 10.000 VDe unless otherwise noted. Boldface limits apply over temperature, TMIN:5:TA:5:TMAX. For all other limits TA=25'C.
Parameter
See
Note
Conditions
Vee = 5 Voe ±5%
Vee = 4_75 Voe
Vee = 12 Voe ±5%
Vee = 15_75 Voe
to15Voe±5%
Tested
Typ
Limit
(Note 12)
(Note 5)
Limit
Units
Design Limit
(Note 6)
CONVERTER CHARACTERISTICS
Resolution
8
Linearity Error Max
Zero and full scale adjusted
-10V:5:VREF:5: + 10V
DAC0830LJ & LCJ
DAC0832LJ & LCJ
DAC0830LCN, LCWM & LCV
DAC0831LCN
DAC0832LCN, LCWM & LCV
Differential Nonlinearity
Max
DAC0830LJ & LCJ
DAC0832LJ & LCJ
DAC0830LCN, LCWM & LCV
DAC0831LCN
DAC0832LCN, LCWM & LCV
Zero and full scale adjusted
-10V:5:VREF:5: + 10V
Monotonicity
-10V:5:VREF
:5: +10V
Using Internal Rib
-10V:5:VREF:5: + 10V
Gain Error Tempco Max
Using internal Rib
Power Supply Rejection
All digital inputs latched high
Vee = 14.5V to 15.5V
11.5V to 12.5V
4.5Vt05.5V
Reference Input
8
bits
0.05
0.2
0.05
0.1
0.2
0.05
0.2
0.05
0.1
0.2
%FSR
%FSR
%FSR
%FSR
%FSR
0.1
0.4
0.1
0.2
0.4
0.1
0.4
0.1
0.2
0.4
%FSR
%FSR
%FSR
%FSR
%FSR
8
8
8
8
bits
bits
±1
±1
%FS
0.0006
%
FSI'C
4,8
LJ&LCJ
LCN, LCWM & LCV
Gain Error Max
8
4,8
4
7
±0.2
0.0002
0.0002
0.0006
0.013
0.0025
%
FSRIV
0.015
I
Max
15
20
20
kO
I
Min
15
10
10
kO
Output Feedthrough Error
VREF=20 Vp-p, f= 100 kHz
All data inputs latched low
3
4-24
mVp-p
Electrical Characteristics VREF= 10.000 Voc unless otherwise noted. Boldface limits apply over tempera'
ture, T MIN:;;; T A:;;; T MAX. For all other limits TA = 25°C. (Continued)
Parameter
See
Note
Conditions
Vee = 4.75 Voe
Vee = 15.75 Voe
Typ
(Note 12)
Vee = 5 Voe ±5%
Vee = 12 Voe ± 5%
to 15 Voe ±5%
co
Co)
o
......
C
Limit
Units
Tested
Limit
(Note 5)
Design Limit
(Note 6)
100
50
100
100
nA
100
50
100
100
nA
Output
Capacitance
~
All data inputs
latched low
LJ& LCJ
LCN, LCWM & LCV
IOUT2
All data inputs
latched high
LJ & LCJ
LCN, LCWM & LCV
IOUT1
IOUT2
All data inputs
latched low
45
115
pF
IOUT1
IOUT2
All data inputs
latched high
130
30
pF
Digital Input
Currents
Supply Current
Drain
Max
Logic Low
10
LJ
4.75V
LJ
15.75V
LCJ
4.75V
LCJ
15.75V
LCN, LCWM, LCV
0.6
0.8
0.7
0.8
0.95
0.8
LJ&LCJ
LCN, LCWM, LCV
2.0
1.9
2.0
2.0
Voc
Voc
Min
Logic High
Max
Digital inputs <0.8V
LJ & LCJ
LCN, LCWM, LCV
-50
-200
-160
-200
-200
/J- A
/J- A
Digital inputs> 2.0V
LJ & LCJ
LCN, LCWM, LCV
0.1
+10
+8
+10
+10
/J- A
1.2
3.5
3.5
1.7
2.0
Max
co
Co)
....
......
o
IOUT1
DIGITAL AND DC CHARACTERISTICS
Digital Input
Voltages
~
o
C
CONVERTER CHARACTERISTICS (Continued)
Output Leakage
Current Max
c
»
oo
LJ & LCJ
LCN, LCWM, LCV
4·25
rnA
co
Co)
N
Electrical Characteristics
VREF= 1 0.000 Voc unless otherwise noted. Boldface limits apply over temperature, T MIN:S: T A,;:TMAX. For ali other limits T A = 25°C. (Continued)
Vcc = 15.75 Voc
Symbol
Parameter
Conditions
See
Note
Typ
(Note 12)
Vcc= 12Voc±5%
Vcc= 4.75 Voc
to 15 Voc ±5%
Tested
Design
Limit
Limit
(Note 5)
(Note 6)
Typ
(Note 12)
Tested
Vcc= 5Voc
±5%
Design
Limit
Limit
(Note 5)
(Note 6)
Limit
Units
AC CHARACTERISTICS
Current Setting
ts
VIL =OV, VIH=5V
1.0
Time
Write and XFER
tw
VIL =OV, VIH=5V
Pulse Width Min
tDS
Data Setup Time
Data Hold Time
VIL = OV, VIH = 5V
VIL =OV, VIH=5V
Min
tcs
Control Setup Time VIL =OV, VIH=5V
Min
tcH
Control Hold Time
Min
100
VIL =OV, VIH=5V
9
100
9
110
",s
600
900
375
320
900
30
50
50
600
250
0
0
320
0
900
ns
900
1100
10
900
600
30
320
0
375
320
250
320
9
9
250
320
9
Min
tDH
11
1.0
1100
0
0
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured wHh respect to GND, unless otherwise specHied.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX. 9JA. and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is Po = (TJMAX - TAll8JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJMAX = 125'C (plastic) or 150'C (ceramic), and the typlcal/unction-to-ambient thermal resistance of the J package when board mounted is BO'C/W. For
the N package, this number increases to 100'C/W and for the V package this number is 120'C/W.
Note 4: For current switching applications, both loun and IOUT2 must go to ground or the "Virtual Ground" of an operational amplifier. The linearity error Is
degraded by approximately Vos .,. VREF. For example, if VREF = 10V then a 1 mV offset, Vos, on 10l1T1 or IOUT2 will introduce an addiUonal 0.01 % linearity error.
Note 5: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 6: Guaranteed, but not 100% produclion tested. These limits are not used to calculate outgoing quality levels.
Note 7: Guaranteed at VREF= ±to Voc and VREF= ±1 Voc.
Note 8: The unit "FSR" stands for "Full Scale Range." "Unearity Error" and "Power Supply Rejection" specs are based on this unit to eliminate dependence on a
particular VREF value and to indicate the true performance of the part. The "Linearity Error" speCification of the DAC0830 is "0.05% of FSR (MAX)". This
guarantees that ailer performing a zero and full scale adjustment (see Sections 2.5 and 2.6), the plot of the 256 analog voltage outputs will each be within
0.05% XVREF of a straight line which passes through zero and full scale.
Note 9: Boldface tested limits apply to the Wand LCJ suffix parts only.
Note 10: A 100nA leakage current with Rfb=20k and VREF=10V corresponds to a zero error of (tOOxl0- 9 X20Xl03)Xl00110 which is 0.02% of FS.
Note 11: The entire write pulse must occur within the valid data interval for the specHied tw, tos, tOH, and
Note 12: Typicals are at 25'C and represent most likely parametric norm.
Nole 13: Human body model, 100 pF discharged through a 1.5 kfl resistor.
4-26
Is to apply.
g
Switching Waveform
oo
co
Co)
o
......
I
V,"
ILE,
&S,
50%1:~~~~~~_ICS_-_-_-_-_-_--1.~.j.I..-_tC_"-J
50%
~
V,L
Wii
o
co
Co)
v," ---------50-%~~·~~~'5-0-%---------
....
......
V,L
~o
!--tos_
DATA BITS
"-10"
v,"
VALID DAC DATA
V,L
I7tfVv
s-
loun IOUT2
J-
-----~
-"'k:.50%
co
Co)
....r
N
F
SETTLED TO
±'hLSB
TL/H/5608-2
Definition of Package Pinouts
Control Signals (All control signals level actuated)
CS:
Chip Select (active low). The CS in combination with ILE will enable WR1.
ILE:
Input Latch Enable (active high). The ILE in
combination with CS enables WR1'
WR1:
Write 1. The active low WRl is used to load the
digital input data bits (01) into the input latch.
The data in the input latch is latched when WRl
is high. To update the input latch-CS and WRl
must be low while ILE is high.
WR2:
Write 2 (active low). This signal, in combination
with XFER, causes the S-bit data which is available in the input latch to transfer to the OAC
register.
XFER:
Transfer control signal (active low). The
XFER will enable WR2.
Vee:
GNO:
Other Pin Functions
010-017: Digital Inputs. 010 is the least significant bit
(LSB) and 017 is the most significant bit (MSB).
IOUT1:
OAC Current Output 1. IOUT1 is a maximum
for a digital code of all 1's in the OAC register,
and is zero for all O's in OAC register.
IOUT2:
OAC Current Output 2. IOUT2 is a constant
minus IOUT1, or IOUTl + IOUT2 = constant (I full
scale for a fixed reference voltage).
Rfb:
Feedback Resistor. The feedback resistor is
provided on the IC chip for use as the shunt
feedback resistor for the external op amp which is
used to provide an output voltage for the OAC.
This on-chip resistor should always be used (not
an external resistor) since it matches the resistors
which are used in the on-chip R-2R ladder and
tracks these resistors over temperature.
Reference Voltage Input. This input connects an
external preCision voltage source to the internal R2R ladder. VREF can be selected over the range of
+ 10 to -10V. This is also the analog voltage input for a 4-quadrant multiplying OAC application.
Digital Supply Voltage. This is the power supply
pin for the part. Vcc can be from + 5 to + 15VDC.
Operation is optimum for + 15VDC.
The pin 10 voltage must be at the same ground
potential as IOUT1 and IOUT2 for current switching
applications. Any difference of potential (Vos pin
10) will result in a linearity change of
Vos pin 10
3VREF
For example, if VREF = 10V and pin 10 is 9mV
offset from IOUTl and IOUT2 the linearity change
will be 0.03%.
Pin 3 can be offset ± 100mV with no linearity
change, but the logic input threshold will shift.
4-27
Linearity Error
DIGITAL INPUT
DIGITAL INPUT
DIGITAL INPUT
TL/H/5608-3
a) End point test after
zero and fs adj.
c) Shifting fs adj. to pass
best straight line test
b) Best straight line
Definition of Terms
Resolution: Resolution is directly related to the number of
switches or bits within the DAC. For example, the DAC0830
has 26 or 256 steps and therefore has 8-bit resolution.
Linearity Error: Linearity Error is the maximum deviation
from a straight line passing through the endpoints of the
DAC transfer characteristic. It is measured after adjusting
for zero and full-scale. Linearity error is a parameter intrinsic
to the device and cannot be externally adjusted.
Settling Time: Settling time is the time required from a code
transition until the DAC output reaches within ± %LSB of
the final output value. Full-scale settling time requires a zero
to full-scale or full-scale to zero output change.
Full-Scale Error: Full scale error is a measure of the output
error between an ideal DAC and the actual device output.
Ideally, for the DAC0830 series, full-scale is VREF -1 LSB.
For VREF= 10V and unipolar operation, VFULL-SCALE=
10.0000V-39mV=9.961V. Full-scale error is adjustable to
zero.
National's linearity "end point test" (a) and the "best
straight line" test (b,c) used by other suppliers are illustrated
above. The "end point test" greatly simplifies the adjustment procedure by eliminating the need for multiple iterations of checking the linearity and then adjusting full scale
until the linearity is met. The "end pOint test" guarantees
that linearity is met after a single full scale adjust. (One adjustment VS. multiple iterations of the adjustment.) The "end
point test" uses a standard zero and F.S. adjustment procedure and is a much more stringent test for DAC linearity.
Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output.
Differential Nonlinearity: The difference between any two
consecutive codes in the transfer curve from the theoretical
1 LSB is differential nonlinearity.
MonotoniC: If·the output of a DAC increases for increasing
digital input code, then the DAC is monotonic. An 8-bit DAC
which is monotonic to 8 bits simply means that increasing
digital input codes will produce an increasing analog output.
r--------------------l
IMSB) 01,
13 1
IB
01,0---,'",4t----I
01,0---,'",,5t----I
B·BIT
MULTIPLYING
01,0---"",,61----1
CON~tnTER 1---,.....,1--0 IDUTI
01, o-~I----,I
01, 0--'-1>-----,1
01, 0-"":'1-----1
I
I
ILSB) DID 0-"":'1-----1
I
I
ILE
[E'"
I
h
'91
r----o GND
I
I
I
I
,I
I
I
I
21
,B I
120
r----o Vee
~'c:~t::::::::[==>
illii C 17
,
I
"0
11 = '"''". Q OUTPUTS FOLLOW 0 INPUTS; ~ GND
~E~~~·".:..D~A~ ~'~LA~~~ _ _ J
'NOTE: WHEN
L ______
TL/H/S608-4
FIGURE 1. DAC0830 Functional Diagram
4-28
Typical Performance Characteristics
Digital Input Threshold
vs. Temperature
2.4
~
~
r-r-r-'r--r-r-r--r-,--,
201-1-t-t-+-~~-r-r-i
1.6 t-t--rt-.,::;--..;;;::-t-t-::l-I-,--l--j
t'--r--r--.., . . . . . ~r-!'~15VDC
~ 1.2
--!:"-I"'--:
v" = 5Voc 1"-1:!'
a
is
O.B I-t-t-+-+-++-r-f""'l
0.4 I-t-t-+-+-++-r+-i
Gain and Linearity Error
Variation vs. Temperature
Digital Input Threshold
vs. Vee
2.4
!!ll
;--;--,-,---,--r--r-.
2.0 r-----t----t-t---r-TL -ls.c
~ ~:5'C
1.6
1.2 1--r-i_1'1--==-t-I-""TTA = 1. 25'C
~
l--I--~
i!:
:!' O.B I - - r - t - ' F + - I - + - j
~
0.1
0.4 I - + - j - + - + - j - + - j
~
'"0
'"ffi
~
w
~
z
...'"'"
Gain and Linearity Error
Variation vs. Supply Voltage
i
_
z
w
+0.025
0.000
r--r-,--r--r';"':""":--r-
0
.......
......... ;::.
-0.05
V
j" =
,'S Vye-
Data Hold Time
~
!;1
250 I-+-++-r-r+-+-t-j
~
200 1-+-+--+--+--+--+-+-+-1
-0.05 I--+---t-+--+-f---+_--,
'"
~
;::
-0.075
~
z
~
5 -0.100
~
-0.125 f---+_-+---1-+-TA = 25 'c-
o
11
5
10
15
Vee. SUPPLY VOLTAGE (Vocl
150 VCC=5~'_t- VCC=12V. 1-1VIH=3~
VIH\=3V Ycc=5V.
100 _YCC=15Y. r12V,15V
V,H=3V
Y,H =5V
50~~~=$~m~
1\1
-55-35-15 5 25 45 65 B5 105.125
TA. AMBIENT TEMPERATURE ('CI
-~-~-~
5 ~ ~ ~ ~1~1~
TA, AMBIENT TEMPERATURE ('CI
TL/H/5608-5
DAC0830 Series Application Hints
system to be updated to their new analog output levels
simultaneously via a common strobe signal.
These DAC's are the industry's first microprocessor compatible, double-buffered 8-bit multiplying D to A converters.
Double-buffering allows the utmost application flexibility
from a digital control point of view. This 20-pin device is also
pin for pin compatible (with one exception) with the
DAC1230, a 12-bit MICRO-DAC. In the event that a system's analog output resolution and accuracy must be upgraded, substituting the DAC1230 can be easily accomplished. By tying address bit Ao to the ILE pin, a two-byte p.P
write instruction (double precision) which automatically increments the address for the second byte write (starting
with Ao = "1 ") can be used. This allows either an 8-bit or the
12-bit part to be used with no hardware or software changes. For the simplest 8-bit application, this pin should be tied
to Vee (also see other uses in section 1.1).
Analog signal control versatility is provided by a precision R2R ladder network which allows full 4-quadrant multiplication of a wide range bipolar reference voltage by an applied
digital word.
The timing requirements and logic level convention of the
register control signals have been designed to minimize or
eliminate external interfacing logic when applied to most
popular microprocessors and development systems. It is
easy to think of these converters as 8-bit "write-only" memory locations that provide an analog output quantity. All inputs to these DAC's meet TTL voltage level specs and can
also be driven directly with high voltage CMOS logic in nonmicroprocessor based systems. To prevent damage to the
chip from static discharge, all unused digital inputs should
be tied to Vee or ground. If any of the digital inputs are
inadvertantly left floating, the DAC interprets the pin as a
logic "1".
1.1 Double-Buffered Operation
Updating the analog output of these DAC's in a double-buffered manner is basically a two step or double write operation. In a microprocessor system two unique system addresses must be decoded, one for the input latch controlled
by the CS pin and a second for the DAC latch which is
controlled by the XFER line. If more than one DAC is being
driven, Figure 2, the CS line of each DAC would typically be
decoded individually, but all of the converters could share a
common XFER address to allow simultaneous updating of
any number of DAC's. The timing for this operation is
shown, Figure 3.
1.0 DIGITAL CONSIDERATIONS
A most unique characteristic of these DAC's is that the 8-bit
digital input byte is double-buffered. This means that the
data must transfer through two independently controlled 8bit latching registers before being applied to the R-2R ladder 'network to change the analog output. The addition of a
second register allows two useful control features. First, any
DAC in a system can simultaneously hold the current DAC
data in one register (DAC register) and the next data word in
the second register (input register) to allow fast updating of
the DAC output on demand. Second, and probably more
important, double-buffering allows any number of DAC's in a
It is important to note that the analog outputs that will
change after a simultaneous transfer are those from the
DAC's whose input register had been modified prior to the
XFER command.
4-29
C
J>
oo
OC)
Co)
......
.....
~
o
f-.L~ ERJORI-t-t--l
-0.0251--
OC)
Co)
o
.....
C
-0.025
TA. AMBIENT TEMPERATURE ('CI
Write Pulse Width
... ~'NEAR'TY ERROR
0.025
-0.1 ' -......"'-..L...-'-....I........L.,_~'--_.I-...Il
-55-35-15 5 25 45 65 B5 105125
5
10
15
Vee. SUPPLY VOLTAGE (VI
TA. AMBIENT TEMPERATURE ('CI
LINEARITY ERROR
0.05 f---+-+-+-+,':':"'\GAIN ERROR
-0.075
O.L-~~~~~~~~
-55-35-15 5 25 45 65 B5 105 125
r-,---r-r-r-r--r-,-.,....,
0.075
~
oo
OC)
Co)
N
N
CO)
~
~.,.........
DAC0830 Series Application Hints (Continued)
ANALOG
OUTPUT 1
CO)
ex)
CI
o
j§
......
CI
CO)
ex)
CI
o
ct
C
ANALOG
OUTPUT n
SYSTEM·
OAC OISABLE ) - - - ,
SYSTmo~
>-______~_--------l
'TIE TO LOGIC 1 IF NOT NEEDED (SEE SEC. 1.1).
FIGURE 2. Controlling Mutiple DACs
cs
WRi
& Wli2
\
\
II
/
L
II
'INPUT LATCH
UPOATEO
mR
\
r-
ANALOG OUTPUT ~\ - - - - - - - ' , (lAC REGISTER LATCHEO
UPOATEO
,'I
\
ILE =LOGIC "1"
TL/H/5608-6
FIGURE3
one contrOlling the DAC's to take over control of the data
bus and control lines. If this second system were to use the
same addresses as those decoded for DAC control (but for
a different purpose) the ILE function would prevent the
DAC's from being erroneously altered.
The ILE pin is an active high chip select which can be de·
coded from the address bus as a qualifier for the normal CS
signal generated during a write operation. This can be used
to provide a higher degree of decoding unique control sig·
nals for a particular DAC, and thereby create a more effi·
cient addressing scheme.
In a "Stand-Alone" system the control signals are generated by discrete logic. In this case double-buffering can be
controlled by simply taking CS and XFER to a logic "0", ILE
to a logic "1" and pulling WRI low to load data to the input
latch. Pulling WR2 low will then update the analog output. A
logic "1" on either of these lines will prevent the changing
of the analog output.
Another useful application of the ILE pin of each DAC in a
multiple DAC system is to tie these inputs together and use
this as a control line that can effectively "freeze" the outputs of all the DAC's at their present value. Pulling this line
low latches the input register and prevents new data from
being written to the DAC. This can be particularly useful in
multiprocessing systems to allow a processor other than the
4-30
DAC0830 Series Application Hints (Continued)
DATA BUS _ _ _
~~.,.\.._ _ __
&8-----.\
----~/
'--.
!
W R 1 - -___\
ANA:-:LD::'G-----D::-::A~TA
DUTPUT UPDATED
LATCHED
TL/H/S608-7
ILE=LOGIC "1"; WR2 and XFER GROUNDED
FIGURE 4
1.2 Single-Buffered Operation
In a microprocessor controlled system where maximum
data throughput to the DAC is of primary concern, or when
only one DAC of several needs to be updated at a time, a
Single-buffered configuration can be used. One of the two
internal registers allows the data to flow through and the
other register will serve as the data latch.
be met or erroneous data can be latched. This hold time is
defined as the length of time data must be held valid on the
digital inputs after a qualified (via CS) WR strobe makes a
low to high transition to latch the applied data.
If the controlling device or system does not inherently meet
these timing specs the DAC can be treated as a slow memory or peripheral and utilize a technique to extend the write
strobe. A simple extension of the write time, by adding a
wait state, can simultaneously hold the write strobe active
and data valid on the bus to satisfy the minimum WR pulsewidth. If this does not provide a sufficient data hold time at
the end of the write cycle, a negative edge triggered oneshot can be included between the system write strobe and
the WR pin of the DAC. This is illustrated in Figure 5 for an
exemplary system which provides a 250ns WR strobe time
with a data hold time of less than 10ns.
Digital signal feedthrough (see Section 1.5) is minimized if
the input register is used as the data latch. Timing for this
mode is shown in Figure 4.
Single-buffering in a "stand-alone" system is achieved by
strobing WR, low to update the DAC with CS, WR2 and
XFER grounded and ILE tied high.
1.3 Flow-Through Operation
Though primarily designed to provide microprocessor interface compatibility, the MICRO-DAC's can easily be config·
ured to allow the analog output to continuously reflect the
state of an applied digital input. This is most useful in applications where .the DAC is used in a continuous feedback
control loop and is driven by a binary up-down counter, or in
function generation circuits where a ROM is continuously
providing DAC data.
The proper data set-up time prior to the latching edge (La to
HI transition) of the WR strobe, is insured if the WR pulsewidth is within spec and the data is valid on the bus for the
duration of the DAC WR strobe.
Simply grounding CS, WR" WR2, and XFER and tying ILE
high allows both internal registers to follow the applied digi·
tal inputs (flow-through) and directly affect the DAC analog
output.
1.5 Digital Signal Feedthrough
When data is latched in the internal registers, but the digital
inputs are changing state, a narrow spike of current may
flow out of the current output terminals. This spike is caused
by the rapid switching of internal logic gates that are responding to the input changes.
1.4 Control Signal Timing
When interfacing these MICRO-DAC to any microprocessor,
there are two important time relationships that must be con·
sidered to insure proper operation. The first is the minimum
WR strobe pulse width which is specified as 900 ns for all
valid operating conditions of supply voltage and ambient
temperature, but typically a pulse width of only 180ns is
adequate if Vee = 15Voe. A second consideration is that
the guaranteed minimum data hold time of 50ns should
There are several recommendations to minimize this effect.
When latching data in the DAC, always use the input register as the latch. Second, reducing the Vee supply for the
DAC from + 15V to + 5V offers a factor of 5 improvement in
the magnitude of the feedthrough, but at the expense of
internal logic switching speed. Finally, increasing Ce (Figure
8) to a value consistent with the actual circuit bandwidth
requirements can provide a substantial damping effect on
any output spikes.
4-31
II
~ r---------------------------------------------------------------------------------~
C")
!
g
DAC0830 Series Application Hints (Continued)
DATA BUS
"....
C")
co
C)
g
......
DNE
SHDT
C)
C")
co
C)
g
~J~ ~___________D_~_A_~_L_ID___________~
WRITE
~~~~~~
----,
I
NDRMAL
DNE WAIT
-WRITE STRDBE----- STATE 125Dn.)
Wli
~
I-
SYSTEM DATA HDLD TIME 1< lDn,)
125Dn,)
IDUTPUT DF - - - - - - ,
DNE·SHDT)
DACWR
1
1-PULSE
WIDTH135Dn,)
_I
DAC
DATA HDLD TIME
(16Dn,)
TL/H/5608-8
FIGURE 5. Accommodating a High Speed System
2.0 ANALOG CONSIDERATIONS
The fundamental purpose of any D to A converter is to pro·
vide an accurate analog output quantity which is representa'
tive of the applied digital word. In the case of the DACOa30,
the output, IOUTI' is a current directly proportional to the
product of the applied reference voltage and the digital input
word. For application versatility, a second output, IOUT2' is
provided as a current directly proportional to the comple·
ment of the digital input. Basically:
Figure 6. The MOS switches operate in the current mode
with a small voltage drop across them and can therefore
switch currents of either polarity. This is the basis for the 4quadrant multiplying feature of this DAC.
2.2 Basic Unipolar Output Voltage
To maintain linearity of output current with changes in the
applied digital code, it is important that the voltages at both
of the current output pins be as near ground potential
(OVocl as possible. With VREF= + 10V every millivolt ap·
pearing at either IOUTI or IOUT2 will cause a 0.01 % linearity
error. In most applications this output current is converted to
a voltage by using an op amp as shown in Figure 7.
I
- VREF x Digital Input.
OUTI- 15 kO
256'
I
VREF 255-Digitallnput
OUT2= 15 kO x
256
The inverting input of the op amp is a "virtual ground" created by the feedback from its output through the internal 15
kO resistor, Rib' All of the output current (determined by the
digital input and the reference voltage) will flow through Rib
to the output of the amplifier. Two-quadrant operation can
be obtained by reversing the polarity of VREF thus causing
IOUT1 to flow into the DAC and be sourced from the output
of the amplifier. The output voltage, in either case, is always
equal to IOUTI X Rib and is the OPPOSite polarity of the reference voltage.
The reference can be either a stable DC voltage source or
an AC signal anywhere in the range from -10V to + 10V.
The DAC can be thought of as a digitally controlled attenuator: the output voltage' is always less than or equal to the
applied reference voltage. The VREF terminal of the device
presents a nominal impedance of 15 kO to ground to external circuitry.
where the digital input is the decimal (base 10) equivalent of
the applied a·bit binary word (0 to 255), VREF is the voltage
at pin a and 15 kO is the nominal value of the internal resist·
ance, R, of the R·2R ladder network (discussed in Section
2.1).
Several factors external to the DAC itself must be consid·
ered to maintain analog accuracy and are covered in subse·
quent sections.
2.1 The Current Switching R·2R Ladder
The analog circuitry, Figure 6, consists of a silicon·chromium (SiCr or Si-chrome) thin film R-2R ladder which is deposited on the surface oxide of the monolithic chip. As a result,
there are no parasitic diode problems with the ladder (as
there may be with diffused resistors) so the reference voltage, VREF, can range -10V to +10V even if Vcc for the
device is 5Voc.
The digital input code to the DAC simply controls the position of the SPDT current switches and steers the available
ladder current to either IOUTI or IOUT2 as determined by the
logic input level ("1" or "0") respectively, as shown in
Always use the internal Rib resistor to create an output volt·
age since this resistor matches (and tracks with tempera,
ture) the value of the resistors used to generate the output
current (lOUTI)'
4-32
DAC0830 Series Application Hints (Continued)
VREF
O-""-"""'Ir-+-~v.._
•••••••
r-JoAf'v-......- -.......
2R
"1"
'--t-....-t--....-t----'-+-.....-~---J.._-....~ vour = -(IOUTt X R'bl
=
\
FIGURE 7
vm (DlGI::~ INPUT!Jo
Vos ADJUST
Vee
TL/H/560B-9
2.3 Op Amp Considerations
This configuration features several improvements over existing circuits for bipolar outputs with other multiplying
DACs. Only the offset voltage of amplifier 1 has to be nulled
to preserve linearity of the DAC. The offset voltage error of
the second op amp (although a constant output voltage error) has no effect on linearity. It should be nulled only if
absolute output accuracy is required. Finally, the values of
the resistors around the second amplifier do not have to
match the internal DAC resistors, they need only to match
and temperature track each other. A thin film 4-resistor network available from Beckman Instruments, Inc. (part no.
694-3-Rl0K-D) is ideally suited for this application. These
resistors are matched to 0.1 % and exhibit only 5 ppml"C
resistance tracking temperature coefficient. Two of the four
available 10 kO resistors can be paralleled to form R in
Pigure 9 and the other two can be used independently as
the resistances labeled 2R.
The op amp used in Figure 7 should have offset voltage
nulling capability (See Section 2.5).
The selected op amp should have as Iowa value of input
bias current as possible. The product of the bias current
times the feedback resistance creates an dutput voltage error which can be significant in low reference voltage applications. BI-FET op amps are highly recommended for use
with these DACs because of their very low input current.
Transient response and settling time of the op amp are im• portant in fast data throughput applications. The largest stability problem is the feedback pole created by the feedback
resistance, Rill, and the output capacitance of the DAC.
This appears from the op amp output to the (-) input and
includes the stray capacitance at this node. Addition of a
lead capacitance, Cc in Figure 8, greatly reduces overshoot
and ringing at the output for a step change in DAC output
current.
Finally, the output voltage swing of the amplifier must be
greater than VREF to allow reaching the full scale output
voltage. Depending on the loading on the output of the amplifier and the available op amp supply voltages (only ± 12
volts in many development systems), a reference voltage
less than 10 volts may be necessary to obtain the full analog output voltage range.
2.5 Zero Adjustment
For accurate conversions, the input offset voltage of the
output amplifier must always be nulled. Amplifier offset errors create an overall degradation of DAC linearity.
The fundamental purpose of zeroing is to make the voltage
appearing at the DAC outputs as near OVoc as possible.
This is accomplished for the typical DAC - op amp connec·
tiort (Figure 7) by shorting out Rib, the amplifier feedback
resistor, and adjusting the Vas nulling potentiometer of the
op amp until the output reads zero volts. This is done, of
course, with an applied digital code of all zeros if IOUT1 is
driving the op amp (all one's for IOUT2). The short around
Rib is then removed and the converter is zero adjusted.
2.4 Bipolar Output Voltage with a Fixed Reference
The addition of a second op amp to the previous circuitry
can be used to generate a bipolar output voltage from a
fixed reference voltage. This, in effect, gives sign significance to the MSB Of the digital input word and allows twOquadrant multiplication of the reference voltage. The polarity
of the reference can also be reversed to realize full 4-quadrant multiplication: ±VREFX ±Digital Code= ±VOUT. This
circuit is shown in Figure 9.
4-33
II
DAC0830 Series Application Hints (Continued)
Cc
OPAmp
LF356
LF351
LF357*
DACOB30
ts
(0 to Full Scale)
Cc
22pF
22pF
10pF
'2.4 kO RESISTOR ADDED FROM-INPUT TO
GROUND TO INSURE STABILITY
FIGURE 8
v
-V
(DIGITALCODE-128)
OUT- REF
128
TLlH/5608-10
"1 LSB=JVREFI
128
Input Code
IDEALVOUT
MSB .......... LSB
'THESE RESISTORS ARE AVAILABLE FROM
BECKMAN INSTRUMENTS, INC. AS THEIR
PART NO. 694-3-R10K-D
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
+VREF
-VREF
VREF-1 LSB
VREF/2
0
-1 LSB
-IVREFI+1 LSB
-IVREFI/2
0
+1 LSB
1
1
1
0
1
1
0
1
o
o
0 1 1 1 1 1 1 JVREFI_ 1 LSB
2
0 0 0 0 0 0 0
-IVREFI
IVREFI + 1 LSB
2
+IVREFI
FIGURE 9
2.6 Full-Scale Adjustment
In the case where the matching of Rib to the R value of the
R-2R ladder (typically ±0.2%) is insufficient for full-scale
accuracy in a particular application, the VREF voltage can be
adjusted or an external resistor and potentiometer can be
added as shown in Figure 10 to provide a full-scale adjustment.
The temperature coefficients of the resistors used for this
adjustment are an important concern. To prevent degradation of the gain error temperature coefficient by the external
resistors, their temperature coefficients ideally would have
to match that of the internal DAC resistors, which is a highly
impractical constraint. For the values shown in Figure 10, if
the resistor and the potentiometer each had a temperature
coefficient of ± 100 ppml"C maximum, the overall gain error
temperature coefficent would be degraded a maximum of
0.0025%I"C for an adjustment pot setting of less than 3%
of Rib.
manner from the standard current switching configuration.
The reference voltage is connected to one of the current
output terminals (loUT1 for true binary digital control, IOUT2
is fOr complementary binary) and the output voltage is tak~n
from the normal VREF pin. The converter output is now a
voltage in the range from OV to 255/256 VREF as a (unction
of the applied digital code as shown in Figure 11.
2.7 Using the DAC0830 in a Voltage Switching
Configuration
The R-2R ladder can also be operated as a voltage switching network. In this mode the ladder is used in an inverted
TL/H/5608-11
FIGURE 10. Adding Full-Scale Adjustment
4-34
DAC0830 Series Application Hints (Continued)
8 (Vml
R
2ft
O""""1~'W"r-........JlM....._
DV .. YoUT ..
•••••
~:: Vm
2R
"""1~'W"r-....-'lM.......
2R
2R
(~1~81 TL-t--I-I-_l>-l-·-·-·-·~I-I.j--l_t_(~-~:_I~(:;:IO::':UT~II..;I_1
.____•____
-
-
-
-0
-
~5 Voe REFERENCE
~->-----~---~-~(~lo::.:Un~I..;I~2.~~~
TL/H/560B-12
FIGURE 11. Voltage Mode Switching
This configuration offers several useful application advantages. Since the output is a voltage, an external op amp is
not necessarily required but the output impedance of the
DAC is fairly high (equal to the specified reference input
resistance of 10 kO to 20 kO) so an op amp may be used
for buffering purposes. Some of the advantages of this
mode are illustrated in Figures 12, 13, 14 and 15.
gain error on the voltage difference between Vee and the
voltage applied to the normal current output terminals. This
is a result of the voltage drive requirements of the ladder
switches. To ensure that all B switches turn on sufficiently
(so as not to add significant resistance to any leg of the
ladder and thereby introduce additional linearity and gain
errors) it is recommended that the applied reference voltage
be kept less than +5VDC and Vec be at least 9V more
positive than VREF. These restrictions ensure less than
0.1 % linearity and gain error change. Figures 16, 17 and 18
characterize the effects of bringing VREF and Vee closer
together as well as typical temperature performance of this
voltage switching configuration.
There are two important things to keep in mind when using
this DAC in the voltage switching mode. The applied reference voltage must be positive since there are internal parasitic diodes from ground to the IOUTl and IOUT2 terminals
which would turn on if the applied reference went negative.
There is also a dependence of conversion linearity and
,........--O+15V Vee
r-f---o+15V
r.....;""'--~~~~1,1,...
___...:+~2.• 5V REFERENCE
LM336
8 Vm
8 ¥m
LM336
R10k
+15V
254\
-2.5 Voe .. YoUT .. 2.5 ¥DC( 256J
-15
3Dk
TLlH/5BOB-13
o
Voltage switching mode eliminates output signal inversion and therefore a
need for a negative power supply.
oVOUT=2.5V
Zero code output voltage is limited by the low level output saturation volt·
age of the op amp. The 2 kll pull·down resistor helps to reduce this voltage.
o Vos of the op amp has no effeci on DAC linearity.
(I~B -1)
o
o Slewing and settling time for a full scale output change Is '" I.B p.s
FIGURE 13. Obtaining a Bipolar Output from a Fixed
Reference with a Single Op Amp
FIGURE 12. Single Supply DAC
4-35
N
C")
8
r-----------------------------------------------------------------------------~
DAC0830 Series Application Hints (Continued)
~
.......
.,...
C")
co
Q
-10V < YouT < +10Y(~::)
(.)
g
.......
Q
t
C")
~
o< VIIAC < ~:: (2.5VI
AY=+8
FIGURE 14. Bipolar Output with Increased Output Voltage Swing
+15V
1=~ 120k
DAC0830
IOUT2
8 YREF
UNO
10 3
12
t---~i1Ok
Vo
+15Y
>--..-o=VMuL::=UT
=YMIN
......- - - - - '
o
CODE (01
255
TL/H/S608-14
o Only a single + 15V supply required
• Norrinteractive full-scale and zero code output adjustments
o VMAX and VMIN must be';; +5VDC and ;;'OV.
1
o Incremental Output Step = 256 (VMAX- VMINI.
OVOUT="£"(VMAX-VMINI+ 255VM1N
256
256
FIGURE 15. Single Supply DAC with Level Shift and SpanAdjustable Output
0.4
YOLTAGE MODE
~
0.2
VREF;"5V
1\
il
15
~
:lI
l-i
REF
:!i
~ -0.2
T2.5V
TR=25°C
0.4
OPi'l.l'Jrl~IT~ ER~OR
YREF=2.5Y
a:
~
Gain and Linearity Error
Variation vs. Reference Voltage
Gain and Linearity Error
Variation vs. Supply Voltage
~
II'"
I
~ 0.2 AUNEARITY
ERROR
a:
...
~
I
0.100
0.015
~=15Y
I
Ycc=15Y
i'
..
~
a:
a:
0.050
~
!
-0.025
-0.015
TR=25°C
~:E MODE OPERATION
I
6UNEARITY ERROR ..:::::::
Ycc=15Y, VREF=5V
Ycc=12Y, VREF=2.5Y-
0.025
15
G -0.050
AGAIN ERROR
-0.4
Ycc, SUPPLY YOLTAGE (Yocl
I
J
l--~cc=12f'\ ""\.
jljERjOnf-
0246810121416
I
II
YeC=~ V
il
a:
YREF=5Y
-0.4
YOLTAGE MOD
r- OPERATION
Gain and Linearity Error
Variation vs. Temperature
-
~
I:;:::: i===""
V
~ :>" V
..,
I I"
6GAIN ERROR
YcC=15Y, VREF=5V OR
YeC = 12Y, VREF = 2.5Y
1 1
o
10
YREF, REFl:RENCE VOLTAGE (Yoc)
-0.100
-55 -35 -15 5 25 45 65 85 105 125
TR, AMBIENT TEMPERATURE (OC)
TUH/S608-1S
FIGURE 16
FIGURE 17
Note: For these curves, VREF is the voltage applied to pin 11 (Ioun) with pin 12 (Ioun)
grounded.
4-36
FIGURE 18
DAC0830 Series Application Hints (Continued)
2.8 Miscellaneous Application Hints
These converters are CMOS products and reasonable care
should be exercised in handling them to prevent catastrophic failures due to static discharge.
Overall noise reduction and reference stability is of particular concern when using the higher accuracy versions, the
DAC0830 and DAC0831, or their advantages are wasted.
Conversion accuracy is only as good as the applied reference voltage so providing a stable source over time and
temperature changes is an important factor to consider.
3.0 GENERAL APPLICATION IDEAS
The connections for the control pins of the digital input registers are purposely omitted. Any of the control formats discussed in Section 1 of the accompanying text will work with
any of the circuits shown. The method used depends on the
overall system provisions and requirements.
A "good" ground is most desirable. A single paint ground
distribution technique for analog signals and supply retums
keeps other devices in a system from affecting the output of
the DACs.
The digital input code is referred to as D and represents the
decimal equivalent value of the 8-bit binary input, for example:
During power-up supply voltage sequencing, the -15V (or
-12V) supply of the op amp may appear first. This will
cause the output of the op amp to bias near the negative
supply potential. No harm is done to the DAC, however, as
the on-chip 15 kO feedback resistor sllfficiently limits the
current flow from IOUll when this lead is internally clamped
to one diode drop below ground.
Binary Input
Pin 13
MSB
1
1
0
0
0
Careful circuit construction with minimization of lead lengths
around the analog circuitry, is a primary concern. Good high
frequency supply decoupling will aid in preventing inadvertant noise from appearing on the analog output.
1
0
0
0
0
Pin 7
LSB
1
0
0
0
0
1
1
0
1
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
0
D
DeCimal Equivalent
1
0
0
0
0
255
128
16
2
0
Applications
CapaCitance Multiplier
DAC Controlled Amplifier (Volume Control)
+15V
IOUT2
Vee
DACD83D
loun
VREf
20
+15V
8
10
C2
":"
+15V
'>:.....---....-0 Vour
c,
~CEOUIV
-15V
I
-V'N(256)
TL/H/560B-16
256)
( 1+ 0
• VOUT=--O--
.CEaUlv~Cl
• When 0 ~ 0, the amplifier will go open loop and the output will saturate.
• Maximum voltage across the equivalent capacitance is
• Feedback impedance from the -Input to the output varies from 15 kfl to
00 as the input code changes from full-scale to zero.
limited to Va MAX (op amp)
256
1+0
• C2 is used to Improve settling time of op amp.
4-37
II
Applications (Continued)
Variable fO. Variable 00. Constant BW Bandpass Filter
R5
TUH/5608-17
{KD
· _§
_
fo - 2".RIC'Oo whereCI
• Ho
=
(KD(2Ro + Rn.
_
Ro(K + I)
Ro(K + I)' 3dbBW - 2".RIC(2Ro + RI)
"256
= C:! = C;K = ~and RI = R of DAC = 15k
I for RIN
= R4 = RI
• Range of fo and 0 is :::: 16 to 1 for circuit shown. The
range can be extended to 255 to 1 by replacing RI wRh a
second DAC0830 driven by the same digRal input word.
• Maximum fo
x0
product should be ;: 200 kHz.
DAC Controlled FunctIon Generator
+15V
+15V
",v~l_w'lr-""_"'C
I
p ..
TRIM
-15V
WAVESHAPE..-""
TRIM
2k
+15V 2 0 r - - - - " ' - - - -.....::-..;.;._...;;.I
OAC0830
.., I':" +15
U
-15
SQUARE WAVE
OUTPUT
TL/H/5608-18
• DAC controls the frequency of sine, square, and triangle outputs.
• f
o
= 256(20k)C for VOMAX = VOMIN of square wave output and R, = 3 R2·
• 255 to 1 linear frequency range; osciliator stops with 0 = 0
• Trim symmetry and wave-shape for minimum sine wave distortion.
4-38
Applications (Continued)
Two Terminal Floating 4 to 20 mA Current Loop Controller
INPUT
IN4001
LM334
2012
50012
LM3290
LM3290
H3
109
~ 4mA .. lOUT" 20mA
TUH/5608-19
lOUT = VREF
[2.. +
Rl
_0_] [1
256Rfb
+
!:!g]
R3
• OAC0830 linearly controls the current flow from the input terminal to the
outputtenninalto be 4 mA (for 0 = 0) to 19.94 mA (for 0 = 255).
• Circuit operates with a terminal voltage differential of 16V to 55V.
• P2 adjusts the magnitude of the output current and PI adjusts the zero
to full scala range of output current.
• Digital inputs can be supplied from a processor using epta isolators on
each input or the OAC latches can flow-through (connect control lines to
pins 3 and lOaf the OAC) and the input data can be set by SPST toggle
switches to ground (pins 3 and 10).
DAC Controlled Exponential Time Response
10UT1I.....~---------------------.
r
OAC0830
10U12 " ' ' - -....-0 VIN
VREF
VINITIAl
VFINAL
.....J
10
II
YoUT
i
f\VFlNAL
10k
VINITIAl
V = 2~6(VOUT - VIN) + ~~vtN
\
Tc-L
I
I r--------.,
2 ,
20 ,I4RFB
MICRO·OAC'·
.t
b-
+V C,I+'5V OCI
11
.FER
20
Pt\o
~
lOUT'
'2:>Io
0UT2
11
11
_.
-
OA
YoUT
+
NOTE: FOR DETAILS OF BUS
CONNECTION SEE SECTION 6.0
TL/H/5688-1
4·41
CD
g
....
~
o
o
....
~....
CD
o
o
....
(.)
~
§....
~........
o
o
....
~
Absolute Maximum Ratings
(Notes 1 & 2)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and speclflcllltions.
Supply Voltage (Vce>
17Voc
Voltage at Any Digital Input
VcctoGND
±25V
- 65·C to + 150"C
Package Dissipation at TA = 25·C (Note 3)
500mW
DC Voltage Applied to loun or IOUT2
(Note 4)
800V
260·C
300·C
Operating Ratings (Note 1)
Voltage at VREF Input
Storage Temperature Range
Temperature Range
Part numbers with 'LCN' suffix
Part numbers with 'LCJ' suffix
Part numbers with 'LJ' suffix
Voltage at Any Digital Input
-100 mVto Vee
TMIN :>: TA :>: TMAX
O"Cto 70·C
- 40·C to + 85·C
- 55·C to + 125·C
VeetoGND
Electrical Characteristics
Tested at Vee = 4.75 Voc and 15.75 Voc, TA=25·C, VREF= 10.000 Voc unless otherwise noted
Parameter
Conditions
See
Note
Vcc= 12Voc±5%
to 15Voc±5%
Min.
Typ.
Resolution
Linearity Error
go
....
~
ESD Susceptibility (Note 11)
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
Differential
Nonlinearity
Monotonicity
EndpOint adjust only
TMIN:VREF:>: +10V
DAC1000 and 1006
DAC1001 and 1007
DAC1 002 and 1008
4,7
6
5
Endpoint adjust only
TMIN:VREF:>: + 10V
DAC1000 and 1006
DAC1001 and 1007
DAC1002 and 1008
4,6
5
Using internal Rib
-10V:>:VREF:>: +10V
5
Gain Error Tempco
TMIN:TMAX
4-42
Typ.
10
bits
0.05
0.1
0.2
0.05
0.1
0.2
0/0 of FSR
0/0 of FSR
0/0 of FSR
0.1
0.2
0.4
0.1
0.2
0.4
% of FSR
% of FSR
%ofFSR
±0.3
1.0
-0.0003
-0.001
0.003
0.004
0.008
0.010
15
Units
Max.
10
9
8
20
-1.0
bits
bits
bits
±0.3
-0.0006
10
1.0
0/0 of FS
-0.002 %ofFS/·C
0.033
0.10
% FSRIV
% FSRIV
% FSRIV
15
20
kG
130
90
130
90
mVp•p
mVp-p
60
250
250
60
60
250
250
60
pF
pF
pF
pF
0.5
6
Min.
10
10
9
8
Gain Error
Output Feedthrough
Error
Max.
Vcc= 5Voc±5%
3.5
0.5
3.5
mA
Electrical Characteristics
Tested at Vee = 4.7S Voe and 1S.7S Voe, TA=2SoC, VREF= 10.000 Voe unless otherwise noted (Continued)
Parameter
Conditions
Vcc= 12Voc±50f0
to 15Voc±50f0
See
Note
Min.
Output Leakage
Current IOUT1
TMIN,;;TA,;;TMAX
All data inputs
latched low
All data inputs
latched high
IOUT2
Digital Input
Currents
Current Settling
Time
ts
Write and XFER
Pulse Width
tw
Data Set Up Time
tos
Typ.
Units
Max.
Q
Q
10
TMIN,;;TA,;;TMAX
Low level
LJ suffix
LCJ, LCN suffix
High level (all parts)
6
200
200
nA
200
200
nA
TMIN,;;TA,;;·TMAX
Digital inputs <0.8V
Digital inputs> 2.0V
6
2.0
0.6
0.7,0.8
2.0
-40
1.0
-40
1.0
-1S0
+10
SOO
VIL =OV, VIH=SV
~....
-1S0
+10
Voe
Voe
Voe
~Aoe
~Aoe
SOO
ns
~....
g
en
.....
~....
Q
VIL =OV, VIH=SV,
TA=2SoC
TMIN,;;TA,;;TMAX
VIL =OV, VIH=SV,
TA=2SoC
8
9
tOH
VIL =OV, VIH=SV
TA=2SoC
tas
VIL =OV, VIL =SV,
TA=2SoC
taH
VIL=OV, VIH=SV,
TA=2SoC
1S0
320
60
100
320
SOO
200
2S0
ns
ns
9
1S0
320
80
120
320
SOO
170
2S0
ns
ns
9
200
2S0
100
120
320
SOO
220
320
ns
ns
9
1S0
320
60
100
320
SOO
180
260
ns
ns
9
10
10
0
0
10
10
0
0
ns
ns
TMIN,;;TA,;;TMAX
TMIN,;;TA,;;TMAX
Note 1: Absolute Maximum Ratings Indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: This 500 mW specification applies for all packages. The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify
the power dissipation) removes concern for heat sinking.
Note 4: For current switching applications, both IOUT1 and IOUT2 must go to ground or the "Virtual Ground" of an operational amplifier. The linearity error is
degraded by approximately Vos+ VREF· For example, if VREF= 10V then a 1 mV offset, Vos, on IOUT1 or IOUT2 will introduce an additional 0.Q1% linearity error.
Note 5: Guaranteed at VREF= ±10 Voe and VREF= ±1 VocNote 6: TMIN=O"C and
.........
S
.....
0.8
0.8,0.8
TMIN,;;TA,;;TMAX
Control Hold Time
Min.
6
TMIN,;;TA,;;TMAX
Control Set Up
Time
Max.
Q
Digital Input
Voltages
Data Hold Time
Typ.
Vcc= 5Voc±50f0
~....
~
~....
TMAX~70'C
for "LCN" suffix parts.
TMIN= -40'C and TMAX=85'C for "LCJ" suffix parts.
TMIN=55'C and TMAX=125'C for "W" suffix parts.
Note 7: The unit "FSR" stands for "Full Scale Range." "Linearity Error" and "Power Supply Rejection" specs are based on this unit to eliminate dependence on a
particular VREF value and to indicate the true performance of the part. The "Linearity Error" specification of the DAC1000 is "0.05% of FSR (MAX)." This
guarantees that after performing a zero and full scale adjustment (See Sections 2.5 and 2.6), the plot of the 1024 analog voltage outputs will each be within
0.05% XVREF of a straight line which passes through zero and full scale.
Note 8: This specification implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (tw) cif 320 ns. A typical part will operate with tw
of only 100 ns. The entire write pulse must occur within the valid data Interval for the specified tw, tos, tOH, and Is to apply.
Note 9: Guaranteed by design but not tested.
Note 10: A 200 nA leakage current with RIb=20K and VREF=10V corresponds to a zero error of (200Xl0- 9 x20Xl03)xl00+l0 which is 0.04% of FS.
Note 11: HUman body model, 100 pF discharged through a 1.5 kll resistor.
4-43
~
~....
Q
Q
CO
CD ,..------------------------------------------------------------------------------------------,
o
o
..-
~.....
.....
Switching Waveforms
VIH
CS. BYTElIBYTE2
8..-
50%
VIL
CD
8
..-
r-
hIS::!
jV'..-r.
I , . - - - - FS
"SETTLED TO
,"'HSB
.
----'
TL/H/568B-2
Typical Performance Characteristics
o·
..-
~
50%
I
VIL
o
§
F
~Ios-IIOHI-
VIH~
DATA BITS
~C'III
.....
8..~
5~
I;:
::~~r-IW
I
~......
~..-......
I-Ics-IICH
Errors vs. Supply Voltage
0.000
~
-.025
'"
- .050
~z
ll:
z
"
Errors vs. Temperature
0.100
L:HEA~ITY E~ROR
~
0.075
V
II
-.075
O.DlO
'"
iI
iii
0.025 r-
i!
;
II"'GAIH ERROR
c
:z: -.100
~
!
u
-.125
0.000
w
500
!t;::
..'"
!iJ
300
c
200
i
100
~
)NL~OVI
o
.!. _I.
VCC=5V
-
S
Lk-
VCC=10V
\
~~
......
!t;::
.
-
I--
Ei
~z
8
5DD
i
I~
I 1
I I
JNLlovl
3DO
200
100
.1
I
VCC=10V VCC=15VVCC=5V
.... -
......
.l- r~
JINL!OVI
SOD
I
1-1NHtVITO jV
400
J J.
300
VCC= 5V'
200
I-
o
-55 -35 -15 5 25 45 65 85 105 125
--
V~C=15V
vJc =ll0V
~
~~
-55-35-15 5 25 45 65 85 105125
TA. AM81ENT TEMPERATURE lOCI
TA. AMBIENT TEMPERATURE ,·C)
Digital Input Threshold
vs. Temperature
2.4
2.01-+--+--4---1-+-+--1
2.0
E
9 1.6
~
...'"'"
1.2
I
0.8
1.2
r--...
............
r- ....
i" ......
0.8
c
u
0.0
-
I
8 100 ....
o
E
~
~
!
9'"
ui
!a..
Ei
i:I
e:
L.
u,..--r-"-i--'-r--,-T-r-,
;!
~ I-
Data Hold Time, tOH
Digital Threshold
vs. Supply Voltage
....
J-P-
100
I- '\
VCC=15V-
-55 -35 -15 5 25 45 65 85 105 125
AMBIENT TEMPERATURE 'OC)
400
AM81ENT TEMPERATURE 'OC)
i!'
200
o
-jNHfYOjV
-55 -35 -15 5 25 45 65 85 105 125
;
II
VC~ = Jv Vec _10V
Data Setup Time, tos
V
VCC=15V
400
~
"BAIH ERROR
S
1 ty i
!
I
- VINH T3V ITO jV
,.; 300
Tl '
-D.050
v!NLlovl
500
-0.11!!55_35_15 5 25 45 65 05 105125
AMBIEHT TEMPERATURE (OC)
I
o
NH
400
"
-0.025
Control Setup Time, tcs
g
- r-
-0.075
10
15
SUPPLY VOLTAGE Vcc 'Voc)
oS
-
Write Width, tw
I L
I I
lIN~RIT~ ER~OR 'iT
0.4
5
10
0.0
-65-35-15 5 25 45 65 85 105125
TEMPERATURE, ·C)
15
SUPPLY VOLTAGE VCC 'V)
4-44
TUH/568B-3
~
....
o
Block and Connection Diagrams
DAC1000/10D1/1002 (24-Pin Parts)
15
(MSB) Dl9 11
DiS 10
017 9
016 B
DI5 7
Dl4 21
DI3 20
DI2 19
Dll 18
(LSB) D1D 17
13
14
16
1st
IOUT2
10UTl
Wiii
RFB
24
VCC
WlRJ
23
WRl
22
NC
NC
Byl81/Byl82
21
014
WR2
20
Dl3
iffi
iffi
BYTE 11
BYTE 2
WI
DAC 1000.
1001.lD02
19
DI2
015
18
011
016
17
DID (LSB)
01)
16
RFB
lD
15
VREF
(MSB) DI9
11
14
loUTl
GND
12
13
loUT2
6
Dl8
CONTROL LOGIC
WR2
C
CS
~
....
o
o....
......
~....
o
o
N
......
C
....o~
o
Q)
......
TOP VIEW
23
fS
o
......
±V8EF
XFER
STROBE
2nd
BYTE
BYTE
STROBE STROBE
o
DAC100D/1001/1002
(24-Pin Parts)
Dual-In-Line Package
C
TL/H/5688-4
NC
RJ
~
....
o
o
DAC1006/10D7/1008 (2D-Pin Parts)
(MSB) Dig
018
g
017
8
7
016
6
015
014
Dl3
5
19
18
012
17
Dll
(LSB) DID
16
15
1 - _ +1:,::3... ± VREF
MSB
1-_~1.:.1~
10UTZ
1'--.l..-.....OOVOUT
IK
":'
LSB
'A TOTAL OF 10
INPUT SWITCHES
& I K RESISTORS
17
VOUT 0 TO VREF(tm)
-15VOC
TLIHI5688-6
Notes:
I. For VREF = -10.240 Vee the output voltage steps are approximately 10 mV each.
2. Operation Is set up for flow through-no latching of dignal input data.
3. Single point ground is strongly recommended.
DAC1006/1007/100S-Simple Hookup for a "Quick Look"
+~VOC~'\~~__________~
SWI
+15VOC
IK
+15VOC
VOS
25K
>....:........_+VOUT
IK
_
LSB
'A TOTAL OF 10
INPUT SWITCHES
& IK RESISTORS
oVoc "
1.5
VOUT " + VREF
(tBH)
-15VOC
Notes:
I. ForVREF= -10.240 Vee the output vollsge steps are approximately 10 mVeach.
2. SWI Is a normally closed switch. While SWI is closed, the DAC register Is latched and new data
can be loaded Into the Input latch via the 10 SW2 switches.
When SWI Is momentarily opened the new dais is transferred from the input latch to the DAC register and Is latched when SWt again closes.
4·46
TLIHI5668-7
1.0 DEFINITION OF PACKAGE PINOUTS
1.1 Control Signals (All control signals are level actuated.)
CS: Chip Select - active low, it will enable WR (DAC10031008) or WR1 (DAC1000-1002).
WR or WR1: Write - The active low WR (or WR1 DAC1000-1002) is used to load the digital data bits (DI) into
the input latch. The data in the input latch is latched when
WR (or WR1) is high. The 10-bit input latch is split into two
latches; one holds 8 bits and the other holds 2 bits. The
Byte1/Byte2 control pin is used to select both input latches
when Byte1 /Byte2 = 1 or to overwrite the 2-bit input latch
when in the low state.
RFS: Feedback Resistor - This is provided on the IC chip
for use as the shunt feedback resistor when an external op
amp is used to provide an output voltage for the DAC. This
on-chip resistor should always be used (not an external resistor) because it matches the resistors used in the on-chip
R-2R ladder and tracks these resistors over temperature.
VREF: Reference Voltage Input - This is the connection for
the external precision voltage source which drives the R-2R
ladder. VREF can range from -10 to + 10 volts. This is also
the analog voltage input for a 4-quadrant multiplying DAC
application.
Vee: Digital Supply Voltage - This is the power supply pin
for the part. Vee can be from + 5 to + 15 Voe. Operation is
optimum for + 15V. The input threshold voltages are nearly
independent of Vee. (See Typical Performance Characteristics and Description in Section 3.0, T2L compatible logic
inputs.)
GNO: Ground - the ground pin for the part.
1.3 Definition of Terms
WR2: Extra Write (DAC1 OQO-1 002) - The active low WR2
is used to load the data from the input latch to the DAC
register while XFER is low. The data in the DAC register is
latched when WR2 is high.
BytellByte2: Byte Sequence Control- When this control
is high, all ten locations of the input latch are enabled. When
low, only two locations of the input latch are enabled and
these two locations are overwritten on the second byte
write. On the DAC1006, 1007, and 1008, the Byte1/Byte2
must be low to transfer the 10-bit data in the input latch to
the DAC register.
XFER: Transfer Control Signal, active low - This signal, in
combination with others, is used to transfer the 10-bit data
which is available in the input latch to the DAC register see timing diagrams.
Resolution: Resolution is directly related to the number of
switches or bits within the DAC. For example, the DAC1000
has 210 or 1024 steps and therefore has 10-bit resolution.
Linearity Error: Linearity error is the maximum deviation
from a straight line passing through the endpOints of the
DAC transfer characteristic. It is measured after adjusting
for zero and full-scale. Linearity error is a parameter intrinsic
to the device and cannot be externally adjusted.
LJ/RJ: Left Justify/Right Justify (DAC1 000-1 002) - When
LJ/RJ is high the part is set up for left justified (fractional)
data format. (DAC1 006-1 008 have this done internally.)
When LJ/RJ is low, the part is set up for right justified (integer) data.
1.2 Other Pin Functions
National's linearity test (a) and the "best straight line" test
(b) used by other suppliers are illustrated below. The "best
straight line" requires a special zero and FS adjustment for
each part, which is almost impossible for user to determine.
The "end point test" uses a standard zero and FS adjustment procedure and is a much more stringent test for DAC
linearity.
Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output (which is the worst case).
011 (i = 0 to 9): Digital Inputs - Dlo is the least significant bit
(LSB) and Dig is the most significant bit (MSB).
IOUT1: DAC Current Output 1 - IOUT1 is a maximum for a
digital input code of all 1s and is zero for a digital input code
of all Os.
IOUT2: DAC Current Output 2 IOUT1' or
1023 VREF
IOUT1 + IOUT2 = 1024 R
IOUT2 is a constant minus
where R "" 15 kO.
b. Best Straight Line
a. End Point Test After Zero and FS Adj.
DIGITAL INPUT
DIGITAL INPUT
TL/H/5688-8
4-47
....~
Q
Q
Q
.....
C
J>
....o
....
.....
Q
Q
....~
~
.....
g
o
....
Q
~
~....
Q
Q
.....
~
....~
Ii
I
Ia
...
§
...
I...
...~
...
CI
CI
~
I
~
Settling Time: Settling time is the time required from a code
transition until the DAC output reaches within ± Yz LSB of
the final output value. Full-scale settling time requires a zero
to full-scale or full-scale to zero output change.
Full-Scale Error: Full scale error is a measure of the output
error between an ideal DAC and the actual device output.
Ideally, for the DAC1000 series, full-scale is VREF-1 LSB.
For VREF= -10V and unipolar operation, VFULLSCALE = 10.OOOOV - 9.BmV = 9.9902V. FUll-scale error Is
adjustable to zero.
Monotonlclty: If the output of a DAC increases for increasing digital input code, then the DAC is monotonic. A 10-bit
DAC with 10-bit monotonicity will produce an increasing analog output when all 10 digital inputs are exercised. A 10-bit
DAC with 9-bi! monotoniclty will be monotonic when only
the most !lignificant 9 bits are exercised. Similarly, B-bit
monotonicity Is guaranteed when only the most significant B
bits are exercised.
3.0 TTL COMPATIBLE LOGIC INPUTS
To guarantee TTL voltage compatibility of the logic Inputs, a
novel bipolar (NPN) regulator circuit is used. This makes the
input logic thresholds equal to the forward drop of two diodes (and also matches the temperature variation) as occurs naturally in TTL The basic circuit is shown in Figure 1.
A curve of digital input threshold as a function of power
supply voltage is shown in the Typical Performance Characteristics section.
4.0 APPLICATION HINTS
The DC stability of the VREF source is the most important
factor to maintain accuracy of the DAC over time and temperature changes. A good single point ground for the analog
signals is next in importance.
These MICRO-DAC converters are CMOS products and
reasonable care should be exercised in handling them prior
to final mounting on a PC board. The digital inputs are protected, but permanent damage may occur if the part is subjected to high electrostatic fields. Store unused parts in conductive foam or anti-static rails.
2.0 DOUBLE BUFFERING
These DACs are double-buffered, microprocessor compatible versions of the DAC1020 10-bit multiplying DAC. The
addition of the buffers for the digital input data not only allows for storage of this data, but also provides a way to
assemble the 10-bit input data word from two write cycles
when using an B-bit data bus. Thus, the next data update for
the DAC output can be made with the complete new set of
1O-bit data. Further, the double buffering allows many DACs
in a system to store current data and also the next data. The
updating of the new data for each DAC is also not time
critical. When all DACs are updated, a common strobe signal can then be used to cause all DACs to switch to their
new analog output levels.
4.1 Power Supply Sequencing & Decoupllng
Some IC amplifiers draw excessive current from the Analog
inputs to V - when the supplies are first turned on. To prevent damage to the DAC - an external Schottky diode connected from loun or IOUT2 to ground may be required to
prevent destructive currents in IOUT1 or IOUT2. If an LM741
or LF356 is used - these diodes are not required.
The standard power supply decoupling capacitors which are
used for the op amp are adequate for the DAC.
+VCC
(3+ + VTHN)
./
./
ValAS
(TO OTHER INPUTS)
~
CMOS LOGIC
o S··VTHRESHDLO=241
TLlHI56BB-9
FIGURE 1. Basic Logic Threshold Loop
4-4B
4.2 Op Amp Bias Current & Input Leads
able ladder current to the IOUTl output pin. These MOS
switches operate in the current mode with a small voltage
drop across them and can therefore switch currents of either polarity. This is the basis for the 4-quadrant multiplying
feature of this DAC.
The op amp bias current (IB) CAN CAUSE DC ERRORS. BIFETTM op amps have very low bias current, and therefore
the error introduced is negligible. BI-FET op amps are
strongly recommended for these DACs.
The distance from the IOUTl pin of the DAC to the inverting
Input of the op amp should be kept as short as possible to
prevent inadvertent noise pickup.
5.1.1 Providing II Unipolar Output Voltage with the
DAC In the Current Switching Mode
A voltage output is provided by making use of an external
op amp as a current-to-voltage converter. The idea is to use
the internal feedback resistor, RFB, from the output of the
op amp to the inverting (-) input. Now, when current is
entered at this inverting input, the feedback action of the op
amp keeps that input at ground potential. This causes the
applied input current to be diverted to the feedback resistor.
The output voltage of the op amp is forced to a voltage
given by:
5.0 ANALOG APPLICATIONS
The analog section of these DACs uses an R-2R ladder
which can be operated both in the current switching mode
and in the voltage switching mode.
The major product changes (compared with the DAC1020)
have been made in the digital functioning of the DAC. The
analog fl.Jnctioning is reviewed here for completeness. For
additional analog applications, such as multipliers, attenuators, digitally controlled amplifiers and low frequency sine
wave oscillators, refer to the DAC1020 data sheet. Some
basic circuit ideas are presented in this section in addition to
complete applications circuits.
VOUT = -(IOUTI XRFB)
Notice that the sign of the output voltage depends on the
direction of current flow through the feedback resistor.
In current switching mode applications, both current output
pins (lOUTl and IOUT2) should be operated at 0 Voc. This is
accomplished as shown in Figure 3. The capacitor, Cc, is
used to compensate for the output capacitance of the DAC
and the input capaCitance of the op amp. The required feedback resistor, RFB, is available on the chip (one end is internally tied to IOUT1) and must be used since an external
resistor will not provide the needed matching and temperature tracking. This circuit can therefore be simplified as
5.1 Operation In Current Switching Mode
The analog circuitry, Figure 2, consists of a silicon-chromium (Si-Cr) thin film R-2R ladder which is deposited on the
surface oxide of the monolithic chip. As a result, there is no
parasitic diode connected to the VREF pin as would exist if
diffused resistors were used. The reference voltage input
(VREF) can therefore range from -10V to + 10V.
The digital input code to the DAC simply controls the position of the. SPOT current switches, SWO to SW9. A logical 1
digital input causes the current switch to steer the avail-
DIGITAL INPUT CODE
(MBB)
Dig
Ola
0
1
017 • • • • •
0
R
2R
010 (LSB)
1
0
-----
±VREF
2R
011
2R
2R
TERMINATION
R
2R
":'
2R
RIB
•••••
SWI
....--ir---t-----t---i---.....-c IOUTl
....- - - - -......-----~-....---~IOUT2
R" 15k"
FIGURE 2. Current Mode Switching
Vcc
(INTERNAL) RFB
lOUT 1
(+15VOC)
+VREF
MICRO-DAC
>--OVOUT = -(IOUTI X RIB)
OP AMP Cc pF Rj
FIGURE 3. Converting lOUT to VOUT
4-49
ts ILS
LF356
22
LF351
24
00
4
LF357
10
2.4k
1.5
00
3
r----+---r--+---,
~....
g
.....
Q
~....
o
....o
.....
....o~
o
N
.....
~....
o
o
en
.....
~....
o
o
:::!
~....
o
o01)
shown in Figure 4, where the sign of the reference voltage
has been changed to provide a positive output voltage. Note
that the output current, IOUT1' now flows through the RFB
pin.
where VREF can be positive or negative and 0 is the signed
decimal equivalent of the 2's complement processor data.
(-512:0;;0:0;; + 511 or 1000000000,;;0,;;0111111111). If the
applied digital input is interpreted as the decimal equivalent
of a true binary word, VOUT can be found by:
5.1.2 Providing a Bipolar Output Voltage with the
DAC In the Current Switching Mode
0-512)
VO=VREF ( !i12
The addition of a second op amp to the circuit of Figure 4
can be used to generate a bipolar output voltage from a
fixed reference voltage Figure 5. This, in effect, gives sign
significance to the MSB of the digital input word to allow two
quadrant multiplication of the reference voltage. The polarity
of the reference can also be revE!Tsed to realize the full four·
quadrant multiplication.
The applied digital word is offset binary which includes a
code to output zero volts without the need of a large valued
resistor common to existing bipolar multiplying OAC circuits.
Offset binary code can be derived from 2's complement
data (most common for signed processor arithmetic) by in·
verting the state of the MSB in either software or hardware.
After doing this the output then responds in accordance to
the following expression:
0:0;;0:0;;1023
With this configuration, only the offset voltage of amplifier 1
need be nulled to preserve linearity of the OAC. The offset
voltage error of the second op amp has no effect on Iineari·
ty. It presents a constant output voltage error and should be
nulled only if absolute accuracy is needed. Another advan·
tage of this configuration is that the values of the external
resistors required do not have to match the value of the
internal OAC resistors; they need only to match and temper·
ature track each other.
A thin film 4 resistor network available from Beckman Instru·
ments, Inc. (part no. 694·3·R10K·0) is ideally suited for this
application. Two of the four available 10 kfl. resistor can be
paralleled to form R in Figure 5 and the other two can be
used separately as the resistors labeled 2R.
o
Operation is summarized in the table below:
VO=VREFX 512
2'sComp.
(DeCimal)
+511
+256
0
-1
-256
-512
2'sComp.
(Binary)
Applied
Digital Input
Applied
True Binary
(DeCimal)
+VREF
-VREF
0111111111
0100000000
0000000000
1111111111
1100000000
1000000000
1111111111
1100000000
1000000000
0111111111
0100000000
0000000000
1023
768
512
511
256
0
VREF-1 LSB
VREF/2
0
-1 LSB
-VREF/2
-VREF
-IVREFI + 1 LSB
-IVREFI/2
0
+1 LSB
+IVREFI/2
+IVREFI
with: 1 LSB = IVREFI
512
VOUT
vcc
IOUTl
( +15Vocl
RIB
-VREF
MICRO·OAC
VOUT
o VOC .. VOUT .. + VREF
'::'
'::'
CdH)
FIGURE 4. Providing a Unipolar Output Voltage
VCC
±VREF
MICRO·OAC
IOUTy.::;...._...~
'-----:::r:---
VOUT
TLlH/5688-11
FIGURE 5. Providing a Bipolar Output Voltage with the DAC In the Current Switching Mode
4·50
5.2 Analog Operation In the Voltage Switching Mode
Some useful application circuits result if the R-2R ladder is
operated in the )/Oitage switching mode. There are two very
important things to remember when using the DAC in the
voltage mode. The reference voltage ( + V) must always be
positive since there are parasitic diodes to ground on the
IOUTl pin which would turn on if the reference voltage went
negative. To maintain a degradation of linearity less than
±O.005%, keep +V ~ 3 Voe and Vee at least 10V more
positive than + V. Figures 6 and 7 show these errors for the
voltage switching mode. This operation appears unusual,
since a reference voltage (+ V) is applied to the IOUTl pin
and the voltage output is the VREF pin. This basic idea is
shown in Figure 8.
Notice that this is unipolar operation since all voltages are
positive. A bipolar output voltage can be obtained by using a
single op amp as shown in Figure 10. For a digital input
code of all zeros, the output voltage from the VREF pin is
zero volts. The external op amp now has a single input of
+ V and is operating with a gain of -1 to this input. The
output of the op amp therefore will be at - V for a digital
input of all zeros. As the digital code increases, the output
voltage at the VREF pin increases.
Notice that the gain of the op amp to voltages which are
applied to the (+) input is + 2 and the gain to voltages
which are applied to the input resistor, R, is -1. The output
voltage of the op amp depends on both of these inputs and
is given by:
This VOUT range can be scaled by use of a non-inverting
gain stage as shown in Figure 9.
VOUT=(+V) (-1)+VREF(+2)
+.1
~
b. LINEARITY ERROR
II:
......r-
a:
a:
...
i!
...
.
.
0
I
...o~
~...
, b. LINEARITY ERROR
~ +.05
1-+--+--+--\+
\~-!-+----J
a:
li!
b. BAIN ERRIiii
N
.....
o
.~
........
~
o~~t-+-tl~
~~-4~
~
-.0&
o
I'-.T
m
z
cz
...oo
...
.....
~...
o
o
en
.....
If
co
C
~
C
r-..-.......-,.-.--...--,--,---,
+.05
~...
o
o
o
.....
,. MAIN ERROR
-.05
...~
1--1-+-+-11-4-+-+-1
r-V~C=15V
-.1 "-"'--"'--..1.....-'--'-...1-....1-....1
o 1 234 5 6 7 a
REFERENCE VOLTAGE. +V IVoc)
-.1 0
2
4
6
a
10 12 14
i
16
SUPPLY VOLTAGE, Vec IVoc)
FIGURE 7
FIGURE 6
DIGITAL INPUT CODE
019
0
(VREF)
R
Ola
1
(MBB)
017 • • • • •
0
R
VOUT
~
C~)
Bw-r"--o
~
~
~
SW!~~ SW~
r
~
0
J
I
R" 15k!2
SWy.
SWo
- I( +15VOC)
I
MICRO·OAC
.. >
.....-b'-:----..../
"IOUTZ"
Z 5V
+
('+v~c
2!!..
(IOUT
II
~~500 VOC) ~r
+
"IOUT1"
"VREF" ....
~
Y Y Y ) (lOUTll
FIGURE 8. Voltage Mode Switching
Vcco
1
•••••
Y
T
I
DID (LSB)
R
-----
''''~
0" VOUT" UVoc
011
0
OA
~
r- -
VOUT
Rl
~2
Ovoc" VOUT" +Z.5VOC (1 + ~)(lgm
TL/H/5686-12
FIGURE 9. Amplifying the Voltage Mode Output (Single Supply Operation)
4-51
g.....
VCC
~
(511)
-2.5VUC" VOUT" 2.5VOC ill
......
r...
o
o.....
"VREF"
VOUT
~
:go
+V
( +2.500Vocl
(LM3361
.....
FIGURE 10. Providing a Bipolar Output Voltage with a Single Op Amp
~
......
C\I
+V
(+2.500 VUC)
o
o
.....
~...........
o
o
.....
R4 = 133K
>---oVOUT
"VREF"
g
......
o
o
o
.....
o
~
0 .. VOAC .. +2.5 VUC
(WzJ)
TLlH/5BBB-13
FIGURE 11. Increasing the Output Voltage Swing
The output voltage swing can be expanded by adding 2
resistors to Figure 10 as shown in Figure 11. These added
resistors are used to attenuate the + V voltage. The overall
gain, Av( -), from the + V terminal to the output of the op
amp determines the most negativli/ output voltage, -4(+ V)
(when the VREF voltage at the + input of the op amp is
zero) with the component values shown. The complete dynamic range of VOUT is provided by the gain from the (+)
input of the op amp. As the voltage at the VREF pin ranges
from OV to +V(1023/1024) the output of the op amp will
range from -10 Vee to + 10V (1023/1024) when using a
+ V voltage of + 2.500 Vee. The 2.5 Vee reference voltage
can be easily developed by using the LM336 zener which
can be biased through the RFB internal resistor, connected
to Vee.
If the Vos is to be adjusted there are a few points to consid·
er. Note that no "dc balancing" resistance should be used
in the grounded positive input lead of the op amp. This reo
sistance and the input current of the op amp can also create
errors. The low input biasing current of the BI-FET op amps
makes them ideal for use in DAC current to voltage applications. The Vos of the op amp should be adjusted with a
digital input of all zeros to force lOUT = 0 mAo A 1 kn resistor
can be temporarily connected from the inverting input to
ground to provide a dc gain of approximately 15 to the VOS
of the op amp and make the zeroing easier to sense.
5.4 Full-Scale Adjust
The full-scale adjust procedure depends on the application
circuit and whether the DAC is operated in the current
switching mode or in the voltage switching mode. Techniques are given below for all of the possible application
circuits.
5.3 Op Amp Vos Adjust (Zero Adjust) for Current
Switching Mode
Proper operation of the ladder requires that all of the 2R
legs always go to exactly 0 Vee (ground). Therefore offset
voltage, Vos, of the external op amp cannot be tolerated as
every millivolt of Vos will introduce 0.01 % of added linearity
error. At first this seems unusually sensitive, until it becomes
clear the 1 mV is 0.01 % of the 10V referencel High resolution converters of high accuracy require attention to every
detail in an application to achieve the available performance
which is inherent in the part. To prevent this source of error,
the VOS of the op amp has to be initially zeroed. This is the
"zero adjust" of the DAC calibration sequence and should
be done first.
5.4.1 Current Switching with Unipolar Output Voltage
After doing a "zero adjust," set all of the digital input levels
HIGH and adjust the magnitude of VREF for
1023
.
VOUT= -(Ideal VREF) 1024
This completes the DAC calibration.
4-52
5.4.2 Current Switching with Bipolar Output Voltage
The circuit of Figure 12 shows the 3 adjustments needed.
The first step is to set all of the digital inputs LOW (to force
IOUT1 to 0) and then trim "zero adj." for zero volts at the
inverting input (pin 2) of OA 1. Next. with a code of all zeros
still applied, adjust "-FS adj.", the reference voltage, for
VOUT= ± I(ideal VREF)I. The sign of the output voltage will
be opposite that of the applied reference.
Finally, set all of the digital inputs HIGH and adjust "+FS
adj." for VOUT=VREF (511/512). The sign of the output at
this time will be the same as that of the reference voltage.
The addition of the 200n resistor in series with the VREF pin
of the DAC is to force the circuit gain error from the DAC to
be negative. This insures that adding resistance to RIb, with
the soon pot, will always compensate the gain error of the
DAC.
5.4.3 Voltage Switching with a Unipolar Output Voltage
Refer to the circuit of Figure 13 and set all digital inputs
LOW. Trim the "zero adj." for VOUT=O Voc±1 mY. Then
set all digital inputs HIGH and trim the "FS Adj." for:
c
~
.....
o
o
o
.....
~
R1)1023
VOUT=(+V) ( 1 + R2 1024
5.4.4 Voltage Switching with a Bipolar Output Voltage
Refer to Figure 14 and set all digital inputs LOW. Trim the
"-FS Adj." for VOUT= -2.5 Voc. Then set all digital inputs
HIGH and trim the "+FS Adj." for VOUT= +2.5 (511/512)
Voc. Test the zero by setting the MS digital input HIGH and
all the rest LOW. Adjust Vos of amp #3, if necessary, and
recheck the full-scale values.
.....
o
o
.....
C
~
.....
o
o
N
.....
~.....
o
o
(+FS AoJ)
.....
G)
500
g
(-FS AoJ)
:!:YREF
o.....
o
o
.....
.....
200
....JVIIIr-lYREF
C
Your
~
(")
.....
o
oQ)
511 )
-VREF.:VOUT': +VREF ( 512
FIGURE 12. Full Scale Adjust - Current Switching with Bipolar Output Voltage
Ycc
( +15YOC)
"YREF"'
MICRO·oAC
~:"""_-oYour
OYoc" Your" 2.5YoC (1 +~)C~)
FS ADJ.
TL/H/568B-14
FIGURE 13. Full Scale Adjust - Voltage Switching with a Unipolar Output Voltage
4-53
CIO
o
....o
g....
+V
....
8....
g
....
r-
MICRO·OAC
CD
o
....o
g
....
o
....o
g
........
o
o....
(2.56VDC)
+FS ADJ.
~I
~
-FS ADJ .
1-0.-.: ~OOg
~1
~_
~
+
rV I
~OOt
R" MATCH TO 0.01 %
R"
R"
15K
15K
1.78K
t>-~~
":"
N
g
§....
g
-2.5V
~ VOUT ~ 2.5(m) V
TL/H/56Sa.15
FIGURE 14. Voltage Switching with a Bipolar Output Voltage
6.0 DIGITAL CONTROL DESCRIPTION
The DAC1000 series of products can be used in a wide
variety of operating modes. Most of the options are shown
in Table 1. Also shown in this table are the section numbers
of this data sheet where each of the operating modes is
discussed. For example, if your main Interest in interfacing
to a ""p with an B-bit data bus you will be directed to Section
6.1.0.
transfer, or updating, of more than one DAC.
For operating without a ""p in the stand alone mode, three
options are provided: 1) using only a single digital data buffer, 2) using both digital data buffers - "double buffered," or
3) allowing the input digital data to "flow through" to provide
the analog output without the use of any data latches.
To reduce the required reading, only the applicable sections
of 6.1 through 6.4 need be considered.
The first consideration is "will the DAC be interfaced to a ""p
with an B-bit or a 16-bit data bus or used in the stand-alone
mode?" For the B-bit data bus, a second selection is made
on how the 2nd digital data buffer (the DAC Latch) is updated by a transfer from the 1st digital data buffer (the Input
Latch). Three options are provided: 1) an automatic transfE!r
when the 2nd data byte is written to the DAC, 2) a transfer
which is under the control of the ""p and can include more
than one DAC in a simultaneous transfer, or 3) a transfer
which is under the control of external logic. Further, the data
format can be either left justified or right justified.
6.1 Interfacing to an 8-Blt Data Bus
,Transferring 10 bits of data over an B-bit bus requires two
write cycles and provides four possible combinations which
depend upon two basic data format and protocol decisions:
1. Is the data. to be left justified (considered as fractional
binary data with the binary point to the left) or right justified (considered as binary weighted data with the binary
point to the right)?
2. Which byte will be transferred first, the most Significant
byte (MS byte) or the least significant byte (LS byte)?
When interfacing to a ""p with a 16-bit data bus only two
selections are available: 1) operating the DAC with a single.
digital data buffer (the transfer of one DAC does not have to
be synchronized with any other DACs in the system), or 2)
operating with a double digital data buffer for simultaneous
Table 1
Operating Mode
Data Bus
B-Bit Data Bus (6.1.0)
Right Justified (6.1.1)
Left Justified (6.1.2)
. ""p Control Transfer
Automatic Transfer
Section
6.2.1
6.2.1
Figure No.
(24-Pin)
(20-Pin)
16
17
Section
lB
6.2.2
6.2.2
20
6.3.2
20
6.4.2
Single Buffered
16-Bit Data Bus (6.3.0)
6.3.1
19
6.4.1
19
16
17
1B
External Transfer
Section
.6.2~3
6.2.3
Double Buffered
Single Buffered
Stand Alone (6.4.0)
Figure No.
(24-Pin)
(20-Pin)
19
4-54
16
17
18
Flow Through
20
Not Applicable
Double Buffered
19
Figure No.
(24·Pln)
(20·Pln)
Flow Through
20
6.4.3
19
NA
These data possibilities are shown in Figure 15. Note that
the justification of data depends on how the 10-bit data
word is located within the 16-bit data source (CPU) register.
In either case, there is a surplus of 6 bits and these are
shown as "don't care" terms (" x ") in this figure.
6.1.2 For Left Justified Data
For applications which require left justified data, DAC10061008 (20-pin parts) can be used. A simplified logic diagram
which shows the external connections to the data bus and
the internal functions of both of the data buffer registers
(Input Latch and DAC Register) is shown in Figure 18.
These parts require the MS or Hi Byte data group to be
transferred on the 1st write cycle.
All of these DACs load 10 bits on the 1st write cycle. A
particular set of 2 bits is then overwritten on the 2nd write
cycle, depending on the justification of the data. This requires the 1st write cycle to contain the LS or LO Byte data
group for all right justified data options. For all left justified
data options, the 1st write cycle must contain the MS or Hi
Byte data group.
6.2 Controlling Data Transfer for an 8-Bit Data Bus
Three operating modes are possible for controlling the
transfer of data from the Input Latch to the DAC Register,
where it will update the analog output voltage. The simplest
is the automatic transfer mode, which causes the data
transfer to occur at the time of the 2nd write cycle. This is
recommended when the exact timing of the changes of the
DAC analog output are not critical. This typically happens
where each DAC is operating individually in a system and
the analog updating of one DAC is not required to be synchronized to any other DAC. For synchronized DAC updating, two options are provided: IlP control via a common
XFER strobe or external update timing control via an external strobe. The details of these options are now shown.
6_1.1 Providing for Optional Data Format
The DAC1000/1/2 (24-pin parts) can be used for either
data formatting by tying the W/RJ pin either high or low,
respectively. A simplified logic diagram which shows the external connections to the data bus and the internal functions
of both of the data buffer registers (Input Latch and DAC
Register) is shown in Figure 16 for the right justified data
operation. Figure 17 is for left justified data.
~....
Q
Q
Q
......
....~
....
......
g
o
....
Q
Q
Q
Q
N
......
....~
Q
Q
0)
......
g
o
....
Q
Q
~
g
1-----II-8IT BYTt----~~--B.BIT BYTE
o....
,I
Q
Q
CI)
HI BYTE
1
I
LO BYTE
I
!MSBEHLEFT:JU++TAEEILSB! x! x! xI x! xI x!
1
HI BYTE
I
LO BYTE
I
! x! xI x! x! x! x!MSB&++US1'FIEO;OATH+SB!
FIGURE 15. Fitting a 10·Blt Data Word into 16 Available Bit Locations
DAC100011001/1002 (24·Pln Parts)
"I
DIg
eMSBI
10
DB
I
,I
B
TO
7
8-BIT
DATA BUS
I
IB
CURRENT
SWITCHES
B-BIT
INPUT
LATCH
TL/H/56BB-16
FIGURE 16. Input Connections and Controls for DAC1000-1002 Right Justified Data Option
4-55
DAC1000/100111002 (24·Pln Parts)
11 Dig
10
g
DBT
B·BIT
DATA BUS
IMSBI
HIT
INPUT
LATCH
T
21
TO
CURRENT
SWITCHES,
20
DB$
101•
ILSBI
I
17
BII.1I!iiilo-....t - - - - - f ,
•
WHEN:
B~~c:~~~-----J
\lI1!iOo
Ilm:R !1iIItE= 1,0
OUTPUTS FOLLOW 0 INPUTS,
Ilm:R !1iQ[l=0. DATA
AT 0 IS LATCHED,
1~lmmO:~~c=)-----------------------.J
WR20
I
v+~
UfIlJ !INTERNAL LUUIC IS SHOWN FOR
lFIRJ = I-LEFT JUSTIFIEDI
FIGURE 17. Input Connections and Controls for DAC1000-1002 Left Justified Data Option
J
DAC1006/1007/1008 (20·Pln Parts for Left Justified Data)
I
DBT
9
I
DIB
IMSBI
B
T
B·BIT
INPUT
LATCH
6
I.I.
8-BIT
DATA BUS
TO
CURRENT
SWITCHES
1
DB.
I
lS'
15
01. ILSBI
BII.1I!iiil
C!
'1/11
Iml
mlI
TUHI5688-17
FIGURE 18. Input Connections and Controls for DAC10061100711008 Left Justified Data
4-56
6.2.1 Automatic Transfer
This makes use of a double byte (double precision) write. The first byte (8 bits) is strobed into the input latch and the second
byte causes a simultaneous strobe of the two remaining bits into the input latch and also the transfer of the complete 1Q·bit word
from the input latch to the DAC register. This is shown in the following timing diagrams; the point in time where the analog output
is updated is also indicated on these diagrams.
DAC1000/1001/1002 (24-Pln Parts)
DAC1006/100711008 (20·Pin Parts)
~....
o
o
o
......
C
....o~
....o
......
c
--\-"j
-.'- ~_
\lJLOAD B", 1
·WIfi & Wli2
LOAD Byt. 2
LATCt-i--)-"-
'Wii&
)LJ- ~~f:TER
~.l;~t
-,'\lJ-
LOAD Bytl 1
~H OAC
LOAD Byte 2 " XFER
iffi~-J r!:_
LATCH~"1 - - ~ DAC
r,l.C~1
ANALOG
ANALOG
) \ OUTPUT
(
UPDATED
~\ UPDATED
OUTPUT
Byt. 11 6iii1&
)LJ- REOISTER
TLlH/5688-18
'SIGNIFIES CONTROL INPUTS WHICH ARE DRIVEN IN PARALLEL
6.2.2 Transfer Using ,...p Write Stroke
The input latch is loaded with the first two write strobes. The XFER signal is provided. by external logic, as shown below, to cause
the transfer to be accomplished on a third write strobe. This is shown in the following diagrams:
DAC1006/1007/1008 (2D-Pin Parts)
DAC1000/1001/1002 (24-Pln Parts)
r\'------Jr:.~LOG
CI "
LOAD Byt. 1
OUTPUT
UPDATED
LOAD Byl' 2
CI
OUTPUT
UPDATED
LATCH DAC
\EGISTER
LATCH Byt. 2
2\jJ
2\
LOAD Byt. 2
,2t-----
• 22-----
r----
2\
Byte 1/B". 2
I
2\i.}
?2
iffi
I
c~-----
WHERE THE XFEII CONTROL CAN BE GENERATED BY USING A SECOND CHIP SELECT AS:
~gg====~O)o-----ooXl'!ll
AND THE BYTE CONTROL CAN BE DERIVED FROM THE ADDRESS BUS SIGNALS,
TLlH/5688-19
6,2.3 Transfer Using an External Strobe
This is similar to the previous operation except the XFER signal is not provided by the ,...P. The timing diagram for this is:
DAC1000/1001/1002 (24-Pin Parts)
DAC1006/1007/1008 (20-Pin Parts)
LOAD 8Vi' 1
LOAD Byt, 2
e----
Wii~~HByt'2
ByI.lIByI.2
2~,--_~,
-
WR2 OR iffi
mil OR Wii2 = 0
2~FER
~~~~3~
I LATCH DAC
,r ----
2~-----
r
2,\
ANALOG
UPDATED
Byt.lI
~
3~:~~0 ./
t
XFER
8yii2
LATCH OAC
REGISTER
?~
REGISTER
,'-----
~2L_----TL/H/5688-20
4-57
......
....o~
o
aI
......
~....
o
o
.....
......
c
....~
WI~tr
LATCH Byt. 2
B", lIB", 2
-
LOAD Byt. 1
m&WftVPa~~
??
\L.......---J(\'-----JI:LG
-
LATCH OAC
REGISTER
o
o
N
C
Bytll/Byt.2
XI'!II'
~
....
o
o
co
6.3 Interfacing to a 16-Blt Data Bus
The interface to a 1S-bit data bus is easily handled by connecting to 10 of the available bus lines. This allows a wiring selected
right justified or left justified data format. This is shown in the connection diagrams of Figures 19 and 20, where the use of DBS
to DB15 gives left justified data operation. Note that any part number can be used and the Byte1/Byte2 control should be wired
Hi.
JUSTIFIED
Rifa~T
~:~
I
1"
019 IMSB)
o
o
o
o
o 10·BIT
o RE8ts~ER
10
9
16·BIT
DATA BUS
21
t=:::l~20~===:1
10·BIT
DATA
LATCH
TO
CURRENT
SWITCHES
o
19
"
17
B"·tl:tfM~o-....::t-----rl
WHEN:
!l'ICR Mm=D. DATA
WIIl~----,r-L-"
AT 0 IS LATCHED,
ICS2)XFm'a::j~t==>-------------~
Wii21l
I
I
I
I
I
I
I
UlIil=x_
!l'ICR EHlim = 1,0
OUTPUTS FOLLOW 0 INPUTS,
fI_-"I-oft......
21
IDON'T CARE)---V
I
I
FIGURE 19. Input Connections and Logic for DAC1000-1002 with 16-Bit Data Bus
LEFT I
JUSTIFIED I
DB15 91 DlgIMSB)
B
DAC1006110071100B 120·PIN PARTS)
5
DATA
BUS
16·BIT
)~=,~gE=====1
lB
10-BIT
INPUT
LATCH
10·BIT
DAC
REGISTER
TO
CURRENT
SWITCHES
17
16
15
DB61 DI",ILSB)
1
cs 1 ':=4::::{~
Wjj2,
mfIi
OOBIT
I
CO:J~OL
WHEN:
[)irnUIiDrr= 1,0
OUTPUTS FOLLOW 0 INPUTS,
:
I
1~)~4+-_~~~~~----------~
I
OllClrElil\l[£=o, DATA
AT 0 IS LATCHED,
31
+VCC~I IEOUIVALENT LOGIC SHOWN
Byte lIByt. 2 I FOR THIS PIN HIGH)
TUH/56B8-21
FIGURE 20. Input Connections and Logic for DAC1006/1007/1008 with 16-Blt Data Bus
4-58
Three operating modes are possible: flow through, single buffered, or double buffered. The timing diagrams for these are shown
below:
~...
6.3.1 Single Buffered
DAC1000/1001/1002 (24-Pin Parts)
c
......
c
DAC1006/1007l100B (20-Pin Parts)
\.._____JI,
"
L....J,
J
Wiii & iiiiii
ANALOG
\
OUTPUT ~~, LATCHES DATA IN
UPDATED
OAC REGISTER
ANALOG
OUTPUT ___
UPDATED
1
ByttIlByt.2=1
Mho
c
"
\
C
la-
XFER AND LATCH
OAC REGISTER
...c
c
l;
...c
......
INPUT DATA IS
LATCHED
LOAD INPUT LATCH
LOAD INPUT LATCH"
...c
o
XFER TO OAC REGISTER
C
N
......
6.3.2 Double Buffered
DAC 1000/1001/1002 (24-Pln Parts)
C
...
c
c
en
......
Wii-----,U
INPUT DATA IS LATCHED
C
INPUT DATA IS LATCHED
Wiii~2
r -------
......... LOAD INPUT LATCH
Bytl1/Bytl2
l;
DAC1006/10071100B (20-Pin Parts)
-
----~2~--------\
c
c
LDAO INPUT LATCH
.....
......
iffi
,---------
...~
Bytt IIBytt 2=1
XFER
iffi DR iiiiii
c
c
co
ANALOG
~~~J--.:
XFER
TL/H/5688-22
6.4 Stand Alone Operation
For applications for a DAC which are not under p.P control (stand alone) there are two basic operating modes, single buffered
and double buffered. The timing diagrams for these are shown below:
6.4.1 Single Buffered
DAC1000/1 0011 1002 (24-Pin Parts)
Wii1
DAC1006/1007/100B (20-Pln Parts)
XFER TO OAC REGISTER
"""\L-..Jr----?2
....
Bytl l/B,,1 2
LATCH INPUT LATCH
~D INPtJT
LATCH
'\
\/
1'---,-
ANALOG!
LATCHES DATA IN OAC REGISTER
U~~~L'r~~N:,UEjT REMAIN VALID
~m~Jo
LOAD INPUT LATCH
6.4.2 Double Buffered
DAC1000/1001/1002 (24-Pln Parts)
Wii1
DAC1006/1007l100B (20-Pln Parts)"
LOAD INPUT LATCHr-_ _ _ _ _ __
"""\L-..Jr----?2
....
Wii \ / 1_
LATCH INPUT LATCH
'\
LATCH INPUT LATCH
LOAD INPtJT LATCH
B"I1/B,,12
WI!!
Cl=irnI=D
B"IIIBytt 2=1
2~FER
ANALOG
OUTPUT
UPDATED-
I
l;
...
....... LATCH OAC
REGISTER
TL/H/568B-23
'For a connection diagram of this operating mode use FlfJure 18 for the Logic and Figure 20 for the Data Input connections.
4-59
co
CI
CI
r---------------------------------------------------------------------------------~
....
g
.....
6.4.3 Flow Through
This operating mode causes the 10·bit input word to directly create the DAC output without any latching involved.
S
CI
DAC1000/100111002 (24-Pin Parts)
~
.....
Byte l/Byte 2 ~ 1
....
Q
~
....
CI
g
.....
N
CI
CI
....
g
......
7.0 MICROPROCESSOR INTERFACE
The logic functions of the DAC1000 family have been oriented towards an ease of interface with all popular I£PS. The
following sections discuss in detail a few useful interface
schemes.
The circuit will perform an automatic transfer of the 10 bits
of output data from the CPU to the DAC register as outlined
in Section 6.2.1, "Controlling Data Transfer for an 8-Bit Data
Bus."
Since a double byte write is necessary to control the DAC
with the INS8080A, a possible instruction to achieve this is a
PUSH of a register pair onto a "stack" in memory. The 16bit register pair word will contain the 10 bits of the eventual
DAC input data in the proper sequence to conform to both
7.1 DAC100111/2 to INS8080A Interface
Figure 21 illustrates the simplicity of interfacing the
DAC1000 to an INS8080A based microprocessor system.
....
....
CI
CI
g
.....
CI
g
....
g
Your
TLIH/S888-24
NOTE: DOUBLE BYTE STORES CAN BE USED.
e.g. THE INSTRUCTION SHLD FOOl STORES THE L
REG INTO Bl AND THE H REG INTO B2 AND
TRANSFERS THE RESULT TO THE DAC REGISTER.
THE OPERAND OF THE SHLD INSTRUCTION MUST
BE AN ODD ADDRESS FOR PROPER TRANSFER.
FIGURE 21. InterfaCing the DAC1000 to the INS8080A CPU Group
4-60
the requirements of the DAC (with regard to right or left
justified data) and the implementation of the PUSH instruction which will output the higher order byte of the register
pair (i.e., register B of the BC pair) first. The DAC will actually appear as a two-byte "stack" in memory to the CPU. The
auto-decrementing of the stack pointer during a PUSH allows using address bit 0 of the stack pOinter as the Byte11
Byte2 and XFER strobes if bit 0 of the stack pOinter address
-1, (SP-1), is a "1" as presented to the DAC. Additional
address decoding by the DM8131 will generate a unique
DAC chip select (CS) and synchronize this CS to the two
memory write strobes of the PUSH instruction.
PIA, and the LOW byte is loaded into ORB. The 10-bit data
transfer to the DAC and the corresponding analog output
change occur simultaneously upon CB2 going LOW under
program control. The 10-bit data word in the DAC register
will be latched (and hence VOUT will be fixed) when CB2 is
brought back HIGH.
If both output ports of the PIA are not available, it is possible
to interface the DAC1000 through a single port without
much effort. However, additional logic at the CB2(or CA2)
lines or access to some of the 6800 system control lines will
be required.
7.3 Noise Considerations
To reset the stack pOinter so new data may be output to the
same DAC, a POP instruction followed by instructions to
insure that proper data is in the DAC data register pair before it is "PUSHED" to the DAC should be executed, as the
POP instruction will arbitrarily alter the contents of a register
pair.
In low frequency or DC applications, low pass filtering can
reduce these noise spikes. This is accomplished by overcompensating the DAC output amplifier by increasing the
value of the feedback capacitor (Cc in Figure 3).
In applications requiring a fast transient response from the
DAC and op amp, filtering may not be feasible. Adding a
latch, DM74LS374, as shown in Figure 23 isolates the device from the data bus, thus eliminating noise spikes that
occur every time the data bus changes state. Another method for eliminating noise spikes is to add a sample and hold
after the DAC op amp. This also has the advantage of eliminating noise spikes when changing digital codes.
7.2 DAC1000 to MC6820/1 PIA Interface
In Figure 22 the DAC1000 is interfaced to an M6800 system
through an MC6820/1 Peripheral Interface Adapter (PIA). In
this case the CS pin of the DAC is grounded since the PIA is
already mapped in the 6800 system memory space and no
decoding is necessary. Furthermore, by using both Ports A
and B of the PIA the 10-bit data transfer, assumed right
justified again in two 8-bit bytes, is greatly simplified. The
HIGH byte is loaded into Output Register A (ORA) of the
o.....
o
o
o
.......
c
,»
o
.....
o
o.....
.......
~.....
o
A typical digital/microprocessor bus environment is a tremendous potential source of high frequency noise which
can be coupled to sensitive analog circuitry. The fast edges
of the data and address bus signals generate frequency
components of 10's of megahertz and can cause noise
spikes to appear at the DAC output. These noise spikes
occur when the data bus changes state or when data is
transferred between the latches of the device.
Another double byte write instruction is Store Hand L Direct
(SHLD), where the HL register pair would temporarily contain the DAC data and the two sequential addresses for the
DAC are specified by the instruction op code. The auto incrementing of the DAC address by the SHLD instruction
permits the same simple scheme of using address bit 0 to
generate the byte number and transfer strobes.
g
o
N
.......
g
o.....
o
o
.......
0)
~
.....
o
o
.....
.......
C
r;;.....
o
o
OCI
_ _ _ _ _ _ _ _--.
PAo"z'--_ _ _ _ _ _ _ _...,
PA1~3,.....
PB7t-:1-:-7_ _ _ _ _ _ _--,
PIA
CBZ
1-:6- - - - - - - ,
PB6t-:
PB51-l1iO!-5
_ _ _ _ _ _-.
PB41-l1.;4_ _ _ _ _....
PB31-'1~3----__.
PBzt-:1!:-Z- - - - - ,
PB1H1*1_ _ _,
pBOl-'l:.::.D_ _-..
r-"''''''''.::.c:I-..:L:...&::...I::..a.:.::'L.:.;",.
II
VDUT
+15V
TLlH/5688-25
FIGURE 22. DAC1000 to MC6820/1 PIA Interface
4-61
8.....
g
.....
.....
CI
CI
.....
g.....
8
CI
.....
~
c
....
~
CI
.....
g
.....
.....
CI
CI
.....
MALUS
OUTPUT
"1..f'" CI fROM '---+---,
=~~~=>-"::::::'t1:)c>-l-t>o.J
NOTE: DATA HOLD TIME REDUCED TO THAT OF DM74LS374 (:::: 10 ns)
SYSTEIIWA.
ADDRE::~1~~>_-=:t.,):1023.
VOUT= - VIN where M = Digital input (expressed as a
M fractional binary number).
O I
j~
l r'1 1
I
0
0
(LSII
I
2.
;~ 1;~1
I
I
I
I
t·
GN.
IOUT2
IOUTt
1II
0
L':'_~
AID
AI
2.
I 1
I
I 1
I 0
I
I
R
I •
1I
1I
.7.",.:.::.:.;:,-,
I
I
•
"
__ ..J
RFEEDBACK
TL/H/5689-1
Ordering Information
Temperature Range
0.05%
NonLinearity
10-BIT DI A CONVERTERS
0'Ct070'C
- 40"C to
+ 8S'C
-SS'C to
+ 125"C
DAC1020LCN AD7520LN,AD7530LN DAC1020LCJ AD7520LD,AD7530LD DAC1020LJ AD7520UD
0.10%
DAC1021LCN AD7520KN,AD7530KN DAC1021LCJ AD7520KD,AD7530KD DAC1021LJ AD7520TD
0.20%
DAC1022LCN AD7520JN,AD7530JN DAC1022LCJ AD7520JD,AD7530JD bAC1022LJ AD7520SD
Package Outline
N16A
J16A
J16A
12-BIT DI A CONVERTERS
Temperature Range
NonLinearity
0.05%
..; 40"C to
O"Cto 70"C
+ 8S'C
- S5"C t~
+ 12S'C
DAC1220LCN AD7521 LN,AD7531 LN DAC1220LCJ AD7521 LD,AD7531 LD DAC1220LJ AD7521UD
0.10%
DAC1221LCN AD7521 KN,AD7531 KN
0.20%
DAC1222LCN AD7521 IN,AD7531 IN DAC1222LCJ AD7521JD,AD7531JD DAC1222LJ AD7521SD
Package Outline
N18A
J18A
Note. Devices may be ordered by eilher part number.
4-64
J1/iA
Absolute Maximum Ratings
Operating Ratings
(Note 5)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V+ toGnd
17V
Temperature (TA)
DAC1020LJ, DACl 021 LJ
DAC1022LJ, DAC1220LJ
DAC1222LJ
DAC1020LCJ, DACl 021 LCJ
DAC1022LCJ, DAC1220LCJ
DAC1222LCJ
DAC1020LCN, DACl 021 LCN
DAC1022LCN, DAC1220LCN
DAC1221 LCN, DAC1222LCN
±25V
VREFto Gnd
Digital Input Voltage Range
V+ toGnd
DC Voltage at Pin 1 or Pin 2 (Note 3)
-100mVtoV+
Storage Temperature Range
-65'C to + 150'C
Lead Temperature (Soldering, 10 sec.)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
260'C
300'C
ESD Susceptibility (Note 4)
Parameter
= 15V, VREF
= 10.000V, TA =
-10VS:VREFS: + 10V,
(Notes 1 and 2)
Full-Scale Error
-10VS:VREFS: + 10V,
(Notes 1 and 2)
Full-Scale Error Tempco
TMIN
...
...
oe[
;;
1.5
I
0.10
----
t- ~V
t- t- _V+o SV
1
~
z 0.05
CI
-
!ia:
oe[
>
0
'"
...'"'"'"
~-O.05
0.6
c;
.,-
.,.
/
'"
-0.10
0
0
20
40
60
80
5.0
10.0
15.0
v+ (VOLTS)
TA - TEMPERATURE ('C)
TL/H/5689-2
FIGURE 2. Gain Error Variation vs V+
FIGURE 1. Digital Input Threshold vs
Ambient Temperature
4-66
Typical Applications
The following applications are also valid for 12-bit systems
using the DAC1220 and 2 additional digital inputs.
Operational Amplifier Vos Adjust (Figure 3)
Connect all digital inputs, A 1-A10, to ground and adjust the
potentiometer to bring the op amp VOUT pin to within ± 1
mV from ground potential. If VREF is less than 10V, a finer
Vos adjustment is required. It is helpful to increase the resolution of the Vos adjust procedure by connecting a 1 kn
resistor between the inverting input of the op amp to
ground. After Vos has been adjusted, remove the 1 kn.
OperatIonal Amplifier Bias Current (Figure 3)
The op amp bias current, Ib' flows through the 15k internal
feedback resistor. SI-FET op amps have low Ib and, therefore, the 15k x Ib error they introduce is negligible; they are
strongly recommended for the DAC1020 applications.
Vos Considerations
The output impedance, ROUT, of the DAC is modulated by
the digital input code which causes a modulation of the operational amplifier output offset. It is therefore recommended to adjust the op amp Vos. ROUT is -15k if more than 4
digital inputs are high; ROUT is - 45k if a single digital input
is high, and ROUT approaches infinity if all inputs are low.
Full-Scale Adjust (Figure 4)
Switch high all the digital inputs, A1-A10, and measure the
op amp output voltage. Use a 500n potentiometer, as
shown, to bring IlvoUT11 to a voltage equal to VREF X
1023/1024.
CF
R,
P
Vw
Circuit Settling
Time, ts
Circuit Small
SlgnalBW
LF357
LF356
LF351
LM741
10 pF
22pF
24pF
0
2.4k
25k
25k
10k
10k
V+
V+
VV-
1.5,..s
3,..s
4,..s
40,..s
1M
0.5M
0.5M
200 kHz
00
~
......
~
......
.......
~......
Q
N
N
.......
~......
.......
OpAmpFamlly
00
~
C
~
SELECTING AND COMPENSATING THE OPERATIONAL AMPLIFIER
00
~......
Q
~
......
N
N
......
......
~......
~
MSB
LSB
AI A2 A3 A4 AS A6 A7 AB A9 AID
TL/H/5689-3
AI
A2 A3
AIO)
VOUT= -VREF ( '2+'4+'8+"'1024
-IOV ,;; VREF ,;; 10V
1023 V
o ,;; VOUT ,;; - 'i024
REF
where AN
=I
il the AN digital input is high
AN = 0 il the AN digital input Is low
FIGURE 3. Basic ConnectIon: Unipolar or 2-Quadrant MultIplying
Configuration (Digital Attenuator)
4-67
Typical Applications (Continued)
Msa
LSB
At A2 A3 At AS A6 A7 A' AI AID
VOUT
R~S2 sou ..--------3l=~.J.:::..:._I
FULL·SCALE
DECREASE
FIGURE 4. Full-Scale Adjust
Msa
LSI
A1 A2 A3 A4 AS AI A7 AI AI AtD
FIGURE 5. Alternate Full-Scale Adjust: (Allows Increasing or Decreasing the Gain)
DIGITAL WOAD A
, MSB
LSB
AI A2 AJ A4 AS A6 Al AI AI AtD
DIGITAL WORD B
~ Msa
LSI
At A2 A3 A4 AS A6 A7 AI A9 AtD
v-
Al0 )
Al A2 A3
VOUTI = -VREF ( "2+"4+"8+···1024
Al
VOUT2 = VREF (
A2
A3
Al0)
"2 + "'4 + "8 + ••• 1024
x,
(61
62
63
610)
2" + ""4 + '"8 + ••• 1024
where VREF can be an AC Signal
FIGURE 6. Precision Analog-to-Dlgital Multiplier
4-68
TL/H/5689-4
g
Typical Applications (Continued)
(")
COMPLEMENTARY OFFSET BINARY
(BIPOLAR) OPERATION
MSI
LSI
AI AZ Al A4 A5 Ai AJ AI All AU
DIGITAL INPUT
."
VOUl
Al
A2
AID
1)
-VREF ( "2 +"4 + ••• + 1024 - 1024
~
+ 1 if AN input is high
AN
~
-1 if AN input is low
0
0
1
0
0
1
0
0
1
0
0
1
0
+VREF
1 VREF X 1022/1024
1
VREF X 2/1024
0
0
1 -VREF X 2/1024
1 -VREF (1022/1024)
Switch all the digital inputs high; adjust the Vos potentiometer of op amp B to bring its output to a value equal
to-(VREF/1024) (V).
b) Switch the MSB high and the remaining digital inputs
low. Adjust the Vos potentiometer of op amp A, to bring
its output value to within a 1 mV from ground potential.
For VREF < 10V, a finer adjust is necessary, as already
mentioned in the previous application.
Assuming that the external 10k resistors are matched to
better than 0.1 %, the gain adjust of the circuit is the same
with the one previously discussed.
MSB
LS8
AI A2 AJ A4 AS A6 Al AI AS AID
MS.
LS8
AI A2 A] A4 A5 Ai A7 AI AS AID
ISV
I5V
VREF_1V
VOUT (SWING)
, 'VREf
."
MATCHED 10k RESISTORS
TLIH15689-6
TRUE OFFSET BINARY OPERATION
DIGITAL INPUT
1
1
0
ts
1
0
0
~
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
o
VOUT
1
0
0
1
0
0
1
0
0
R2
AyR4 ~ (2Ay - -l)R'R1 ~ Ay- -I'
R3
VREF X 1022/1024
0
-VREF
o
+
Rl ~R2
~
Example: VAEF
Then R4
R3
~
~
~ VOUT!PEAKI, R ~ 2Dk
VAEF
2V, VOUT (swing) '" ± lDV: Ay-
R; Ay~
9R, Rl
~
0.8 R2. If Rl
~
~
O,2R then R2
SV
~
0.2SR,
O.64R
1.81's
FIGURE 9. Bipolar Configuration with
Increased Output Swing
use LM336 for a voltage reference
FIGURE 8. Bipolar Configuration with a Single Op Amp
4-69
g
o.....
C)
I\)
.....
.......
g
o
.....
.......
~.....
I\)
I\)
C)
.......
g
(")
.....
.....
.....
I\)
I\)
o
.....
Gain Adjust (Full-Scale Adjust)
a)
~
g
FIGURE 7. Bipolar 4-Quadrant Multiplying Configuration
Operational Amplifiers Vos Adjust (Figure 7)
C)
I\)
C)
I\)
I\)
VREF
(1023)
• IOUT1 + IOUT2 = - - - X - RLADDER
1024
• By doubling the output range we get half the
resolution
• The 10M resistor, adds a 1 LSB "thump", to
allow full offset binary operation where the output reaches zero for the half-scale code. If
symmetrical output excursions are required,
omit the 10M resistor.
TUH/5689-5
where: AN
o 0 0
0 0 0
1 1 1
0 o 0
000
1 1 1
Note that:
MATCtlED lD11 RESISTORS
VOUT =
0 o 0
0 0 0
1 1 1
000
000
1 1 1
0
0
0
1
1
1
VOUT
.....
I\)
I\)
I\)
Typical Applications
(Continued):
MSI
LSI
AI A2 A3 A4 A5 A6 Al AI A9 AID
15V
15
VOUT
---.....;<
0-....
V-
VOUT
~
(AI
A2 A3
Al0 )
-+-+-+
,2
4
8
"1024
where: VREF can be an AC signal
• By connecting the DAC in the feedback loop of an operational amplifier a linear digitally control gain block can be
realized
• Note that with all,digital inputs low, the gain of the amplifier
is infinity, that is, the op amp will saturate. In other words, we
cannot divide the VREF by zero!
FIGURE 10. Analog-to-Digital Divider (or Digitally Gain Controlled Amplifier)
MSB
LSI
AI AZ AJ A4 A5 A6 Al AS AS AID
15V
V-
V-
TLlHI5689-7
Ai' Ai! .. , +
Al0]
-+-+
-
~ VREF [ ~ + ~ +'" +~
2
VOUT
2
4
4
~ VREF ( - - N - )
1023 - N
1024
orVOUT
1024
where: 0 :;: N :;: 1023
N
~
0 for AN
N
~
1 for Al0
N
~
1023 for AN
~
~
all zeros
1, Al-A9
~
~
aliI's
FIGURE 11. Digitally controlled Amplifier-Attenuator
4-70
0
Typical Applications
(Continued)
I5V
'Ok
SINE WAVE OUT
CLOCK
(FREQUENCY
CONTROLI
TUH/5689-8
• Output frequency =
f~1L;;
fMAX "" 2 kHz
• Output voltage range = OV - 10V peak
• THO < 0.2%
• Excellent amplitude and frequency stability with temperature
• Low pass filter shown has a 1 kHz corner (for output frequencies below 10Hz,
filter corner should be reduced)
• Any periodic function can be implemented by modifying the contents of the look
up table ROM
• No start up problems
FIGURE 12. Precision Low Frequency Sine Wave Oscillator Using Sine Look-Up ROM
4·71
Typical Applications (Continued)
15V
LSB
~""Y\"",-o15V
o
OVERFLOW
n.
TO DAC1020
DIGITAL INPUTS
15V
UP OWN
nAI-4~"'O
Msa
MM74COO - NAND gates
MM74C32 - OR gates
MM74C74 - D flip-flop
MM74C193 - Binary upl
down counters
TL/H/5689-9
• Binary up/down counter digitally "ramps" the DAC
output
• Can stop counting at any desired 10-bit input code
• Senses up or down count overflow and automatically
reverses direction of count
FIGURE 13. A Useful'Olgltallnput Code Generator for OAC AHenuator or Amplifier Circuits
4-72
Definition of Terms
Power Supply Sensitivity: Power supply sensitivity is a
Resolution: Resolution is defined as the reciprocal of the
measure of the effect of power supply changes on the Of A
full-scale output.
number of discrete steps in the Of A output. It is directly
related to the number of switches or bits within the Of A. For
example, the OAC1020 has 2 10 or 1024 steps while the
OAC1220 has 212 or 4096 steps. Therefore, the OAC1020
has 10-bit resolution, while the OAC1220 has 12-bit resolution.
Settling Time: FUll-scale settling time requires a zero to fullscale or full-scale to zero output change. Settling time is the
time required from a code transition until the Of A output
reaches within ± % LSB of final output value.
Full-Scale Error: Full-scale error is a measure of the output
error between an ideal Of A and the actual device output.
Ideally, for the OAC1020 full-scale is VREF-1 LSB. For
and
unipolar
operation,
VFULLVREF= 10V
SCALE=10.0000V-9.B mV=9.9902V. Full-scale error is
adjustable to zero as shown in Figure 5.
Linearity Error: Linearity error is the maximum deviation
from a straight line passing through the endpoints of the
OfA tlflnsfer characteristic. It is measured after calibrating
for zero (see Vas adjust in typical applications) and fullscale. Linearity error is a design parameter intrinsic to the
device and cannot be externally adjusted.
OAC FAILS END POINT TEST
LlNEARITV ERROR:::: I LSB
IN
DIGITAL INPUT
IN
TLlH/5689-10
a
b1
(a) End point test after zero and full-scale adjust.
b2
(b) By shifting the full-scale calibration on of the OAC of
Figure (bt) we could pass the "best straight line" (b2)
test and meet the ± Yz linearity error specification.
The OAC has 1 LSB linearity error.
Note. (a), (b1) and (b~) above illustrate the difference between "end paint" National's linearity test (a) and "best straight line" test. Note that both devices in (a) and
(b2) meet the ± Y. LSB linearity error specHication but the end pOint test is a more "reallile" way 01 characterizing the CAe.
Connection Diagrams
DAC102X
DAC122X
Dual-In-Line Package
Dual-In-Line Package
lOUT I 1
Ii AFEEDBACK
IOUT2 Z
I.
GND 1
AI (MSB'
lOUT'
15 VAEF IN
y+
15
Al(M~1
14
12 AI
A'
11 AI
,M '
AS I
,
ID A7
A.
•
A' •
A.
AI2!LS&1
A11
U AID
AI •
A3 •
VAEF IN
tIS y.
GND
13 AID (LSBJ
4
A2,,'
"
10UTZ
12 AI
"
..
10 A7
A. •
TO'VllW
TOP VIEW
4-73
TLlH/5689-11
~
C")
....
,---------------------------------------------------------------------,
~
~....
NaHonal
~ Semiconductor
CorporaHon
.... MICRO-DACTM.DAC1208, DAC1209, DAC1210, DAC1230,
~
~....
~
....
~
g
C;
....
....
~
~
....ie
g
!....
~
DAC 1231, DAC 1232 12-Bit, J-LP Compatible,
Double-Buffered D to A Converters
General Description
Features
The DAC1208 and the DAC1230 series are 12-bit multiplying D to A converters designed to interface directly with a
wide variety of microprocessors (8080, 8048, 8085, Z-80,
etc.). Double buffering input registers and associated control lines allow these DACs to appear as a two-byte "stack"
in the system's memory or 1/0 space with no additional interfacing logic required.
The DAC1208 series provides all 12 input lines to allow single buffering for maximum throughput when used with 16-bit
processors. These input lines can also be externally configured to permit an 8-bit data interface. The DAC1230 series
can be used with an 8-bit data bus directly as it internally
formulates the 12-bit DAC data from its 8 input lines. All of
these DACs accept left-justified data from the processor.
The analog section is a precision silico.n-chromium (Si-Cr)
R-2R ladder network and twelve CMOS current switches.
An inverted R-2R ladder structure is used with the binary
weighted currents switched between the IOUT1 and IOUT2
maintaining a constant current in each ladder leg independent of the switch state. Special circuitry provides TTL logic
input voltage level compatibility.
The DAC1208 series and DAC1230 series are the 12-bit
members of a family of microprocessor compatible DACs
(MICRO-DACSTM). For applications requiring other resolutions, the DAC1000 series for 10-bit and DAC0830 series
for 8-bit are available alternatives.
• Linearity specified with zero and full-scale adjust only
• Direct interface to all popular microprocessors
• Double-buffered, single-buffered or flow through digital
data inputs
• Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)
• Works with ± 1OV referenc~full 4-quadrant
multiplication
• Operates stand-alone (without /LP) if desired
• All parts guaranteed 12-bit monotonic
• DAC1230 series is pin compatible with the DAC0830
series 8-bit MICRO-DACs
Key Specifications
• Current Settling Time
• Resolution
• Linearity (Guaranteed
over temperature)
• Gain Tempco
• Low Power Dissipation
• Single Power Supply
1 /Ls
12 Bits
10,11, or 12 Bits of FS
1.3 ppm/oC
20mW
5 VDC to 15 Voc
Typical Application
CONTROL IUS
VCC
cs
lOll
FULL· SCALE
AD.lUST
tSV
MICRO·OACTM
>-4~-VOUT
20 PINS
':'
-15V
TUH/569D-t
4-74
~
Absolute Maximum Ratings
Operating Conditions
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(Notes 1 and 2)
Lead Temperature (Soldering, 10 seconds)
Supply Voltage (Vcel
Voltage at Any Digital Input
Temperature Range
TMIN ,;; TA';; TMAX
DAC1208LCJ, DAC1209LCJ,
DAC1210LCJ, DAC1230LCJ,
-40'C';; TA';; +85'C
DAC1231LCJ,DAC1232LCJ
DAC1208LCJ-l, DAC1209LCJ-l,
DAC~ 21 OLCJ-l, DAC1230LCJ-l,
DAC1231LCJ-l, DAC1232LCJ-l
O'C,;; TA';; +70'C
17Voc
VcctoGND
±25V
Voltage at VREF Input
Storage Temperature Range
-65'C to + 150'C
Package Dissipation at TA = 25'C
(Note 3)
RangeofVcc
Voltage at Any Digital Input
500mW
DC Voltage Applied to IOUTl or IOUT2
(Note 4)
ESD Susceptability
4.75 Voc to 16 Voc
VcctoGND
Notes
Conditions
Resolution
Zero and Full·Scale
Adjusted
DAC1208, DAC1230
DAC1209, DAC1231
DAC1210, DAC1232
4,7,13
Zero and Full·Scale
Adjusted
DAC1208, DAC1230
DAC1209, DAC1231
DAC1210, DAC1232
4,7,13
Monotonicity
Gain Error (Min)
Using Internal RFb
Vref = ±10V, ±1V
Gain Error (Max)
Gain Error Tempco
Power Supply Rejection
All Digital Inputs
Latched High
Reference Input Resistance (Min)
Reference Input Resistance (Max)
Output Feedthrough Error
Output Capacitance
VREF=20 Vp·p, f= 100 kHz
All Data Inputs Latched
Low
"
All Data Inputs
Latched High
All Data Inputs
Latched Low
IOUT2
Tested
Limit
(Note 5)
l
~
~.....
N
Q
CD
......
~.....
N
.....
All Data Inputs Latched
Low
All Data Inputs Latched
High
Units
~.....
N
W
.....
12
Bits
0.012
0.024
0.050
0.012
0.024
0.05
% ofFSR
% ofFSR
% ofFSR
N
W
N
0.018
0.024
0.050
0.018
0.024
0.05
% ofFSR
% ofFSR
%ofFSR
12
12
12
7
-0.1
0.0
7
-0.1
-0.2
7
±1.3
7
±3.0
±30
13
15
15
10
20
9
3.0
~.....
Bits
% ofFSR
% ofFSR
±6.0
ppm of FSI'C
ppm of FSRIV
10
20
kO
mVp·p
200
70
70
200
pF
pF
pF
pF
2.0
2.5
mA
11,13
0.1
15
15
nA
11,13
0.1
15
15
nA
Digital Input Threshold
Low Threshold
High Threshold
13
13
0.8
2.2
0.8
2.2
Voc
Voc
Digital Input Currents
Digital Inputs <0.8V
Digital Inputs > 2.2V
13
13
-200
10
-200
10
I'AOC
I'AOC
4-75
~
12
4
13
Design
Limit
(Note 6)
N
W
......
IOUT1
IOUT2
IOUT1
IOUT2
Supply Current Drain
Output Leakage Current
IOUTl
Typ
(Note 10)
12
Differential Non·Linearity
Q
~.....
VREF= 10.000 voc, Vcc= 11.4 Voc to i 5.75 Voc unless otherwise noted. Boldface limits apply from TMIN to TMAX (see
Note 13); all other limits TA = TJ = 25'C.
Linearity Error
(End Point Linearity)
N
Q
......
-100 mVto Vcc
800V
Electrical Characteristics
Parameter
.....
300'C
II
Electrical Characteristics (Continued)
VREF = 10.000 Voc, Vee = 11.4 Voc to 15.75 Voc unless otherwise noted. Boldface limits apply from TMIN to TMAX (see
Note 13); all other limits TA = TJ = 25"C.
Symbol
Parameter
Conditions
See
Typ
Note
(Note 10)
Tested
Design
Limit
Limit
(Note 5)
(Note 6)
Units
AC CHARACTERISTICS
ts
Current Setting Time
tw
Write and
=
=
OV, VIH
1.0
OV, VIH
=
=
5V
VIL
5V
50
VIL
=
OV, VIH
=
5V
VIL
XFER
Pulse Width Min.
tos
Data Setup Time Min.
8
p's
320
320
70
320
320
tOH
Data Hold Time Min.
VIL
=
OV, VIH
=
30
5V
90
90
tcs
Control Setup Time Min.
tCH
Control Hold Time Min.
VIL
=
OV, VIH
=
320
60
5V
ns
320
VIL
=
OV, VIH
=
10
0
5V
Note I: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specH/cations do not apply when operating
the device beyond its speCified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise speeifled.
Note 3: This 500 mW speeRication applies for all peckages. The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify
the power dissipation) removes concern for heat sinking.
Note 4: Both 10UT1 and IOUT2 must go to ground or the virtual ground of an operational amplifier. The linearity error is degraded by approximately Vos'" VREF. For
example, if VREF= 10V then a I mV offset, Vos, on IOUT1 or IOUT2 will Introduce an additional 0.01 % linearity error.
Note 5: Tested and guaranteed to National's AOQL (Average OUtgOing Quality Level).
Note 6: DeSign IimRs are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels. Guaranteed for Vee = II.4V to 15.75V
and VREF = -IOV to + 10V.
Note 7: The unR FSR stands for full-scale range. Linearity Error and Power Supply Rejection specs are based on this unit to eliminate dependence on a particular
VREF value to indicate the true performance of the part. The Linearity Error specification of the OACI208 is 0.012% of FSR(max). This guarantees that after
performing a zero and full·scale adjustment, the plot of the 4096 analog voltage outputs will each be within 0.012% x VREF of a straight line which passes through
zero and full-scale. The unit ppm of FSR(parts per million of full-scale range) and ppm of FS(parts per million of full-scale) are used for convenience to define spees
of very small percentage values, typical of higher accuracy converters. In this Instance, I ppm of FSR=VREF/I(J6 is the conversion factor to provide an actual
output voltage quantRy. For example, the gain error tempco spec of ± 6 ppm of FS/'C represents a worst·case full-scale gain error change with temperature from
-40'C to +85'C of ±(6)(VREFI1(J6)(125'C) or ±0.75 (10- 3) VREF which Is ±0.075% of VREF.
Note 6: This spec implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (Ivi) of 320 ns. A typical part will operate with tw of only
100 ns. The entire write pulse must occur within the valid data interval for the specified tw, tos, tOH and Is to apply.
Note 9: To achieve this low feedthrough In the 0 package, the user must ground the metal lid. If the lid is left floating the feedthrough is typically 6 mY.
Note 10: Typicals are at 25'C and represent the most likely parametric norm.
Note 11: A 10 nA leakage current with RFb=20k and VREF=IOV corresponds to a zero error of (IOXIO-9X20XI03)XIOO% 10V or 0.002% of FS.
Note 12: Human body model, 100 pF discharged through a 1.5 kO resistor.
Note 13: Tested limit for -I sufiix parts applies only at 25'C.
Connection Diagrams
Dual·ln·Llne Package
cs....!
jijji..!
.N•
Dual·ln·Une Package
CS...!.
.!!.vcc
..!
DII...!
jijji..!.
.!!. BYTE 118YTE 2
I'!-liiii
.ND...!.
.!!.\iiiZ
..!.
.l!. XfER
r!Lxm
DIJ
~DI.
D~ ...!.
01,
..!
01,
..!
DIZ
..!.
rILD11
DI,..!
~DI.
DAeUGI,
DAC1Z11.
DACUID
I'!-.r,
.~
~Dll.
DlaIU1)...!
.!!. Vee
!!. IYTE "mfi
...!.
0"
...l.
VREF
..!
VR"
..!!
!LDlu",l •
R.. .,!
Rf •
..!l
!!.laUT2
••a..!!
••• ..!!
.!!.Ioun
0"C123O,
DAtlZ31,
DAC1Z32
.ll. DI,IOIDI
f!!,.DltIDIII
f1!.DI'I ID1z)
rll-DI1IIMSIIIDI31
rE- 1DUT2
fll.loun
TOP VIEW
TL/H/5690-2
TOP VIEW
See Ordering Information
4-76
c
l:;
......
Switching Waveforms
N
'Cs-----l
CS. BYTE llBYTE 2
50%
V I L - - - - - - ' -______________
oOC)
.....
'CH
50%
~......
~----'
VIH
N
Viii
o
~
50%
VIL
g
'DH
VIH
50%
DATA BITS
o
......
SO%
N
......
VIL
o
.....
_'S_~
_ ________________
IDun. IDU12
C
J~~~~----S-ET-T-LE-D-T-D--------
l:;
......
± 112 LSB
N
TL/H/569D-3
(0)
o
.......
Typical Performance Characteristics
Digital Input Threshold
2.4
~
"
Q
m
.. 12
1=
i!
TA'?5 C
Q
TA· BSoC
~
;;
Ci
--
-
J
TA!-40 C
1.8
d.•
0.4
o
,..- I - ~
r- r-
o
~ 2.0
t-t-+-++-+--t--t--l-l
~
1.&
l-002......r--+-+-
ii!1=
1.2
1---t--t--l"""r..;;~~:t-+--1
10
I-+-+-+--+
c; 0.4
t-t-+-++-+--t--t--l-l
~ 0.005
i!
; -0.005
::1
5
I--
-4~ERR~R- I--
400
~
300
500
~
4~RRJR
~
"....'"
I
bI
200
~
100 I--I-- :h-lDV
15
]
:!
5
25
45
65
~
"
ffi
lOD
VI~L =~V
I
Vlt"jVTrV
"'·'m
JCC-~v-'
2DD
I
-f-- --
I
100
-1====
-l5 -15
5
25
45
f - I--
~ rI--I--
65
85
TA -AMBIENT TEMPERATURE (OC)
Data Set-Up Time, loS
VINL'~V I
VINH = lV TD 5V
1
VI~L
.Jv I
VINH" lV TD 5V
SOD
Ii30
300
:::
JF
200 r -
~
lDO
~ lOO
-
.
;:!
<
;:: ~
-
200
-
~
r-~CC'5V
I
M
I-Vcc -10V
~
10D
f f i . c c -IDV_ I--I-VCC=15V
VcC- 15V
-l5 -15
5
25
45
55
-l5 -15
B5
5
25
45
65
85
TA - AMBIENTTEMPERATURE (OC)
TA - AMBIENTTEMPERATURE (OC)
TLlH/5690-4
4-77
......
.....
g
o......
N
4 LINEARITY
VCC-15V,
B5
~
;: 400
~
~
TA - AMBIENTTEMPERATURE CC)
400
::I:
;: 400
--
Write Pulse Width, tw
500
.
500
VCC = 15V
-l5 -15
Vcc -SUPPLY VOLTAOE (Voc)
-,,"-
Data Hold Time, IOH
~
I
"
-0.01
"
r- -
-l5 -15 5 25 45 65 85
TA - AMBIENTTEMPERATURE (OC)
VI~L'~V I
VINH = lV TD 5V
VCC" 5V
8,
-0.01
10
::1~
Control Set-Up Time, tcs
]
~
....
4Gb
i!
TA - AMBIENT TEMPERATURE (OC)
TA· Z5°t
lli
0.01
~ 0.005
-l5 -15 5 25 45 65 85
15
Gain and Linearity Error
Variation vs Supply Voltage
0.01
..
!!
~ -0.005
~ 0.•
~
......
N
(0)
VCC-15VDC
~
Vcc -SUPPLY VDLTAGE (V)
g
Gain and Linearity Error
Variation vs Temperature
Temperature
2.4 r-'-1-'-'-'--'---"--"--'
vsVcc
2.D
C
Digital Input Threshold vs
(0)
N
the DAC1230, DAC1231, and DAC1232 must be connected
to ground. It is important that lOUT1 and lOUT are at ground
potential for current switching applications. ~ny difference
of potential (Vos on these pins) will result in a linearity
change of
Definition of Package Pinouts
CONTROL SIGNALS (all control signals are level actuated)
CS: Chip Select (active low). The CS will enable WR1.
WR1: Write 1. The active low WRl is used to load the digital
data bits (DI) into the input latch. The data in the input latch
is latched when WRl is high. The 12-bit input latch is split
into two latches. One holds the first 8 bits, while the other
holds 4 bits. The Byte 11 Byte 2 control pin is used to· select
both latches when Byte llByte 2 is high or to overwrite the
4-bit input latch when in the low state.
Byte l/Byte 2: Byte Sequence Control. When this control is
high, all 12 locations of the input latch are enabled. When
low, only the four least significant locations of the input latch
are enabled.
WR2: Write 2 (active low). The WR2 will enable XFER.
For example, if VREF = 10V and these ground pins are 9
mV offsE!l from lOUT1 and IOUT2' the linearity change will be
0.03%.
Definition of Terms
Resolution: Resolution is defined as the reciprocal of the
number of discrete steps in the DAC output. It is directly
related to the number of switches or bits within the DAC. For
example, the DAC120B has 212 pr 4096 steps and therefore
has 12-bit resolution.
XFER: Transfer Control Signal (active low). This Signal, in
combination with WR2, causes the 12-bit data which is
available in the input latches to transfer to the DAC register.
010 to 0111: Digital Inputs. DID is the least significant digital
input (LSB) and Dill is the most significant digital input
(MSB).
Linearity Error: Linearity error is the maximum deviation
from a straight line passing through the endpOints of the
DAC transfer characteristic. It is measured after adjusting
for zero and full-scale. Linearity error is a parameter intrinsic
to the device and cannot be externally adjusted.
National's linearity test (a) and the best straight line test (b)
used by other suppliers are illustrated below. The best
straight line (b) requires a special zero and FS adjustment
for each part, which is almost impossible for the user to
determine. The end point test uses a standard zero FS adjustment procedure and is a much more stringent test for
DAC linearity.
Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output.
Settling Time: Full-scale current settling time requires zero
to full-scale or full-scale to zero output change. Settling time
is the time required from a code transition until the DAC
output reaches within ± Yz LSB of the final output value.
Full-Scale Error: Full-scale error is a measure of the output
error between an ideal DAC and the actual device output.
Ideally, for the DAC120B or DAC1230 series, full-scale is
VREF-l LSB. For VREF=10V and unipolar operation,
VFULL.SCALE = 1O.OOOOV - 2.44 mV = 9.9976V. Full-scale
error is adjustable to zero.
Differential Non-Linearity: The difference between any
two consecutive codes in the transfer curve from the theoretical 1 LSB is differential non-linearity.
Monotonic: If the output of a DAC increases for increasing
digital input code, then the DAC is monotonic. A 12-bit DAC
which is monotonic to 12 bits simply means that input increaSing digital input codes will produce an increaSing analog output.
IOUT1: DAC Current Output 1. IOUTl is a maximum for a
digital code of all 1s in the DAC register, and is zero for all
Os in the DAC register.
loun: DAC Current Output 2. IOUT2 is a constant minus
IOUT1' or IOUTl + IOUT2 = constant (for a fixed reference
voltage). This constant current is
VREF X ( 1 -
40~6)
divided by the reference input resistance.
RFb: Feedback Resistor. The feedback resistor is provided
on the IC chip for use as the shunt feedback resistor for the
external op amp which is used to provide an output voltage
for the DAC. This on-chip resistor should always be used
(not an external reSistor) since it matches the resistors in
the on-Chip R-2R ladder and tracks these resistors over
temperature.
VREF: Reference Voltage Input. This input connects an external precision voltage source to the internal R-2R ladder.
VREF can be selected over the range of 10V to -10V. This
is also the analog voltage input for a 4-quadrant multiplying
DAC application.
Vee: Digital Supply Voltage. This is the power supply pin for
the part. Vee can be from 5 VOC to 15 VOC. Operation is
optimum for 15 VOC.
GND: Pins 3 and 12 of the DAC1208, DAC1209, and
DAC1210 must be connected to ground. Pins 3 and 10 of
DIGITAL INPUT
TLIH/5690-5
b) Shifting FS Adjust to PailS
Best Straight Line Test
a) End Pol"t Test After Zero
and FS Adjust
4-78
All of the digital inputs to these DACs contain a unique
threshold regulator circuit to maintain TTL voltage level
compatibility independent of the applied Vee to the DAC.
Any input can also be driven from higher voltage CMOS
logic levels in non·microprocessor based systems. To prevent damage to the chip from static discharge, all unused
digital inputs should be tied to Vee or ground. As a troubleshooting aid, if any digital input is inadvertently left floating,
the DAC will interpret the pin as a logic "1 ".
Application Hints
1.0 DIGITAL INTERFACE
These DACs are designed to provide all of the necessary
digital input circuitry to permit a direct interface to a wide
variety of microprocessor systems. The timing and logic level convention of the input control signals allow the DACs to
be treated as a typical memory device or 1/0 peripheral with
no external logic required in most systems. Essentially
these DACs can be mapped as a two-byte stack in memory
(or 1/0 space) to receive their 12 bits of input data in two
successive 8-bit data writing sequences. The DAC1230 series is intended for use in systems with an 8-bit data bus.
The DAC1208 sE1ries provicjes all 12 digital input lines which
can be externally configurad to be controlled from an 8-bit
bus or can be driven directly from a 16-bit data bus.
,.
Oll1lMS11
'I
"
,.
11
0
0
0
a
a
a
of---
0
0
0
0
o~
0
0
o~
Q~
0
0
0
0
of---
0
0
0
.0
•
•
Double buffered digital inputs allow the DAC to internally
format the 12-bit word used to set the current switching R2R ladder network (see section 2.0) from two 8-bit data
write cycles. Figures 1 and 2 show the internal data registers and their controlling logic circuitry. The timing diagrams
for updating the DAC output are shown in sections 1.1, 1.2
and 1.3 for three possible control modes. The method used
depends strictly upon the particular application.
I·BIT
INPUT
LATCH
0
•
•
0
,....-.!!
..... ~.!!
O~
12·811
OAe
D REGISTER
12·111
MULTIPLYING
OIA
.~
Q
,....-2-
MS.
f---
CONVERTER
VREF
loun
loun
I-.!!
"..
.!!
l.
!!.
GNO
LE
I
01,
0
7
I
01,
01,
o
D
9
Ol,llSl1
0
p-
23
BYTE lIiYTE1
fS
WR,
,
~,
iFIii
::J
4·811
~~~~~
r
o~
of--of---
0-0
lSI
Vee
GNO
lE
E
When
"~
~,
WR,
o~
0-0
Q -0
0 _0
When
-
CE=1, Q outputs follow 0 Inputs
CE =0, Q outputs are latched
FIGURE 1. DAC120B, DAC1209, DAC1210 Functional Diagram
,.
,.
'3
DIU(MSBICDI3I
01,0101,I
01.101, I
0
0
0
0
OI.COIOI 'I
01 7
01I
I
01 i
7
01
•
0
0
0
•
•
8-81T
INPUT
LATCH
0
0
0
0
0
0
0 - MS.
0-
a
0
o
0
0
000_
0
0
0
0
0
o
012·81T
OAe
REGISTER
-
0-
a
-
-......
12-811
MULTIPLYING
OIA
CONVERTER
,!..
i!!fl!!..
VREF
loun
IOUT1
a
RF.
lE
0
o
IYTE 1/BYTE Z
es
WR'
XFEA
a ~:;~1
o
,.
,
~,
11
WRi ~I
4·IIT
::l
::l
p-
of---
0
0 ~O
0
0
o '-----
f---
of---
0~0
o~ LSI
r
o~
i!- Vee
f!- GNO
fl!-
GNO
lE
When
When
"
CE=1, Q outputs follow D Inputs
CE =0, Q outputs are latched
TL/H/5690-6
FIGURE 2. DAC1230, DAC1231, DAC1232 Functional Diagram
4-79
Application Hints (Continued)
1.1 Automatic Transfer
The 12-bit DAC word is automatically transferred to the DAC register and the R-2R ladder when the second write (the 4 LSBs of
the data) occurs.
DATA BUS - - - ( ' , ,_ _ _V_AL_'D_ _. . . J » - - - - - - « , ,_ _V_A_Ll_D_...J»------
----:====___
B Y T E I / m I T - - - - - - - - - - - - - - -......\
ANOirni
..._ _ _ _ _
ANALOG OUTPUT
PDATED
\,-_~I
WIil ANDlVliZ
/l
\
LOAD B·BIT INPUT
LATCH I4-BIT INPUT
LATCH ALSO CHANGEDI
i;::'=A:::N::-AL:-:D:::G~DU::::T::::PU::;T""-
._
LATCHED
OVERWRITE THE 4·BIT
INPUT LATCH AND TRANSFER
ALL 'Z BITS TO THE OfA
TUH/5690-7
1.2 Independent Proce~sor Transfer Control
In this case a separate address is decoded to provide the XFER signal. This allows the processor to load the next required DAC
word but not change the analog output until some time later, most useful for the simultaneous updating of several DACs in a
system where their XFER lines would be tied together.
DATA BUS
----« ...__VA_L_'D_...J)>------« ..._ _VA_Ll_D_.J>- _ - - -_ _ _ _ _ _ _ __
\ ....- - - -_ _ _..J.''-o.,
1 1--------_ ________ _
BYTE 1IBYTEZ
\",,-_ _~I
ANALOG OUTPUT
UPDATED
ANALOG OUTPUT
LATCHED
iViii ANDiYRI
LOAD .·BIT INPUT
LATCH 14·BIT INPUT
LATCH ALSO CHANGEDI
OVERWRITE 4·BIT
INPUTLATCH
TRANSFER '2-IIT DAC
WORD TO THE OfA
TL/Hf5690-9
1.3 Transfer via an External Strobe
This method is basically the same as the previous operation except the XFER signal is provided by a device other than the
processor. This allows the DAC to hold the code for a conditional analog output signal which will be required on demand from an
external monitoring device (an analog voltage comparator for instance).
DATA BUS - - - - « ...._ _V_AL_ID_....J)>------«'--_V_A_LlD_....J)>---......- - - - - - - -_ _
\"---_______ ,r-------
BYTE 1IiY'iTI
---------
-
XFER
LOAD .·8IT INPUT
LATCH 14-8IT INPUT
LATCH ALSO CHANGEDI
.
OVERWRITE 4-BIT
INPUTLATCH
WR2 tied to a logic low (OV)
ANALOG OUTPUT UPDATED
AND LATCHED
TUH/5690-9
4-80
Application Hints (Continued)
1.4 Left-Justified Data Format
It is important to realize that the input registers of these
DACs are arranged to accept a left-justified data word from
the microprocessor with the most significant' 8 bits coming
first (Byte 1) and the lower 4 bits second. Left justification
simply means that the binary pOint is assumed to be located
to the left of the most significant bit. Figure 3 shows how the
12 bits of DAC data should be arranged in 2 8-bit registers
of an 8-bit processor before being written to the DAC.
1.516-Blt Data Bus Interface
The DAC1208 series provides all 12 digital input lines to
permit a direct parallel interface to a 16-bit data bus. In this
instance, double buffering is not always necessary (unless a
simultaneous updating of several DACs or a data transfer
via an external strobe is desired) so the 12-bit DAC register
can be wired to flow-through whereby its Q outputs always
reflect the state of its D inputs. The external connections
required and the timing diagram for this single buffered application are shown in Figure 4. Note that either left or rightjustified data from the processor can be accommodated
with a 16-bit data bus.
r-HI IVTE-j-LO IVTE-I
I
MSI -OAC DATAE LSI x X x x
.
1.6 Flow-Through Operation
Through primarily designed to provide microprocessor interface compatibility, the MICRO·DACs can easily be configured to allow the analog output to continuously reflect the
state of an applied digital input. This is most useful in appli-
IVTEZ
BYTE 1
x=
I
TL/H/5690·10
don't care
FIGURE 3. Left-Justified Data Format
Interface Timing
JUSTIFIED
.- -
-
- DAciioa:iiAc,ZD9. DAC;ZID- -
-
-
-
~~~.~~~~________~1~5~'=MS~B~
IS-BIT
DATA IUS ~--------o()o-"'---i
TO
CURRENT
SWITCHES
DII;II
DM
VCC
SVSTEM
i'iiiSTROBE
II·BIT
DATA BUS
Ci
WRI
(
VALID
~
>
I
ANALOG OUTPUT
UPDATED
ANALOG OUTPUT
LATCHED
TL/H/5690·11
l---------.J
TL/H/5690-13
FIGURE 7. Isolating Data Bus from DAC Circuitry to Eliminate Digital Noise Coupling
4-83
Application Hints (Continued)
5V
-
~~
DID IUS
AlB
A14
A13
A12
A11
AID
T&
T5
~
u-<
14
B3
T4
T3
~
B2
T2
II
T1
:::.....
OMI1LS95S
BUFFER
~G
05
04
03
02
01
i'iif
AD
i-
~
~
5V
A4
V4
~G2
AI
VB
V5
r----c
r-c
01
DO
A3
CSZ
3
CS3
SELEC~
AI
AI
GNO
~:O".F
V4
V3
VZ
VI
B'::I
101
OAC1230
'02
1 1 1 1 1°iOoo
•
m
L.;~7~I~ER
02
WR2
5.1.
•
OAC
IUS
•
O~
03
CSl
5V
Z
05
Gl
A4
I
5V
m
A
°iOoo
~ WRI
°
1
04
102
xm
BlIQ
I
101
OAC1230
l~i: 1 I I I I I
Wli
C
TRANSFER
CSlI
miIf
WRI
'WRr
(
03
rr
'-- 0
A2
I
02
V3
01
VZ
DO
VI
O.m:.~rcoOER
A3
~
V
.
1°.1·F
1113 OM70L97 IUFFER
AB
A5
~
5."
A&
A5
A3
A2
AI
DO
::
07
VI
0&
V7
05
V&
04
VB
AI
A7
DB
...
1&
IS
~Z
07
BOARD
SELECT
5.n
OMI131
IUSCOMP
_
XFR3
XFRZ
5V
,~
,.....~,....
~
--<
5.1.
en
101
XFR3
--CWRf
OAC1Z30
~'WliT
10Z
XFRI
XFRO
IB,:27111111°L
VCC~BV
I
....
TLiH/569()'14
FIGURE 8. TRI·STATE@ Buffers Isolate the Data and Control Lines from the DACs.
A Transfer Word Provides a Flexible Update.
4·84
c
~
.....
Application Hints (Continued)
2.0 ANALOG APPLICATIONS
The inverting input of the op amp is a virtual ground created
by the feedback from its output through the internal 15 kn
resistor, RFb. All of the output current (determined by the
digital input and the reference voltage) will flow through RFb
to the output of the amplifier. Two-quadrant operation can
be obtained by reversing the polarity of VREF thus causing
IOUT1 to flow into the DAC and be sourced from the output
of the amplifier. The output voltage, in either case, is always
equal to IOUT1 X RFb and is the opposite polarity of the reference voltage.
The analog output signal for these DACs is derived from a
conventional R-2R current switching ladder network. A detailed description of this network can be found on the
DAC1000 series data sheet. Basically, output IOUT1 provides a current directly proportional to the product of the
applied reference voltage and the digital input word. A second output, IOUT2 will be a current proportional to the complement of the digital input. Specifically:
The reference can be either a stable DC voltage source or
an AC signal anywhere in the range from -10V to +10V.
The DAC can be thought of as a digitally controlled at\enuator: the output voltage is always less than the applied reference voltage. The VREF terminal of the device presents a
nominal impedance of 15 kn to ground to external circuitry.
I
VREF
D
OUT1 =
x 4096;
R"
I
VREF 4095 - D
OUT2 =
x 4096
R"
where D is the decimal equivalent of the applied 12-bit binary word (ranging from 0 to 4095), VREF is the voltage applied to the VREF terminal and R is the internal resistance of
the R-2R ladder. R is nominally 15 kn.
Always use the internal RFb resistor to create an output
voltage since this resistor matches (and tracks with temperature) the value of the resistors used to generate the output
current (Ioun).
The selected op amp should have as Iowa value of input
bias current as possible. The product of the bias current
times the feedback resistance creates an output voltage error which can be significant in low reference voltage applications. BI-FETTM op amps are highly recommended for use
with these DACs because of their very low input current.
2.1 Obtaining a Unipolar Output Voltage
To maintain linearity of output current with changes in the
applied digital code, it is important that the voltages at both
of the current output pins be as near ground potential (0
VDcl as possible. With VREF= + 10V every millivolt appearing at either IOUT1 or IOUT2 will cause a 0.01 % linearity
error. In most applications this output current is converted to
a voltage by using an op amp as shown in Figure 9.
15V
15V
>~"""OVDUT
DAC12DB
VREF
GND
12
TUH/5690-15
VOUT ~ -(Ioun x RFb)
~ -VREF(D)
4096
forO,. 0,. 4095
FIGURE 9. Unipolar Output Configuration
4-85
N
oQ)
g
o
.....
-~
-g
N
o
CD
C
~
.....
N
.....
o
.....
N
W
o
o
.....
N
W
.....
C
):0
o
.....
N
W
N
Application Hints (Continued)
Transient response and settling time of the op amp are im·
portant in fast data throughput applications. The largest sta·
bility problem is the feedback pole created by the feedback
resistance, RFb, and the output capacitance of the DAC.
This appears from the op amp output to the (-) input and
includes the stray capacitance at this node. Addition of a
lead capacitance, Cc in Figure 9, greatly reduces overshoot
and ringing at the output for a step change in DAC output
current.
internal feedback resistor, RFb, matches the R·2R ladder
resistors. A negative gain error indicates that RFb is a small·
er resistance value than it should be. To adjust this gain
error, some resistance must always be added in series with
RFb. The son potentiometer shown is sufficient to adjust
the worst·case gain error for these devices.
2.2 Bipolar Output Voltage from a Fixed Reference
The addition of a second op amp to the unipolar circuit can
generate a bipolar output voltage from a fixed reference
Voltage. This, in effect, gives Sign significance to the MSB of
the digital input word to allow two quadrant multiplication of
the reference voltage. The polarity of the reference can also
be reversed to realize full 4·quadrant multiplication. This circuit is shown in Figure 10.
This configuration features several improvements over existing circuits for a bipolar output shown with other multiplying DACs. Only the offset voltage of amplifier 1 affects the
linearity of the DAC. The offset voltage error of the second
op amp (although a constant output error) has no effect on
linearity. In addition, this configuration offers a non·interac·
tive positive and negative full·scale calibration procedure.
2.1.1 Zero and Full-Scale Adjustments
For accurate conversions, the input offset voltage of the
output amplifier must always be nulled. Amplifier offset errors create an overall degradation of DAC linearity.
The fundamental purpose of zeroing is to make the voltage
appearing at the DAC outputs as near 0 VDC as possible.
This is accomplished by shorting out RFb, the amplifier feed·
back resistor, and adjusting the vos nulling potentiometer of
the op amp until the output reads zero volts. This is done, of
course, with an applied digital code of all zeros if loun is
driving the op amp (all ones for IOUT2). The short around
RFb is then removed and the converter is zero adjusted.
A unique feature of this series of DACs is that the full·scale
or gain error is guaranteed to be negative. The gain error
specification is a measure of how close the value of the
(+FULL-SCALE
ADJUSTI
2R
10k
15V
24
Vee
DAC1Z01
±VREF
(-FULL-SCALE
ADJUST!
10
VREF
VOUT
ZR
10k
v
-
forO
s: 0 s: 4095
= IVREFI
OUT -
V
REF
(D - 204B)TL/H/5690.16
2048
1 LSB
2048
Input Code
MSB•••••• LSB
IdealVOUT
+VREF
-VREF
111111111111
VREF -1 LSB
-IVREFI +1 LSB
110000000000
VREF/2
-IVREFI/2
100000000000
0
0
011111111111
-1 LSB
- VREF _ 1 LSB
2
-VREF
+1 LSB
IVREFI + 1 LSB
2
+IVREFI
001111111111
000000000000
FIGURE 10. Bipolar Output Voltage Configuration
4·86
~....
Application Hints (Continued)
~
2.2.1 Zero and Full-Scale Adjustments
To calibrate the bipolar output circuit, three adjustments are
required. The first step is to set all of the digital inputs LOW
(to force loun to 0) then null the Vos of amplifier 1 by
setting the voltage at its inverting input (pin 2) to zero volts.
Next, with a code of all zeros still applied, adjust "-fullscale adjust", the reference voltage, for VOUT= ±IVREF
ideall. The polarity of the output voltage at this time will be
opposite that of the applied reference. Finally, set all of the
digital inputs HIGH and adjust "+ full-scale adjust" for
2047
VOUT = VREF 2048'
o
The polarity of the output will be the same as that of the
reference voltage.
3.0 APPLICATION IDEAS
In this section the digital input word is represented by the
letter D and is equal to the decimal equivalent of the 12-bit
binary input. Hence D can be any integer value between 0
and 4095.
00
.....
g
o
....
~
o
~
g
o
....
....o
.....
g
o
....
~
Composite Amplifier for Good DC Characteristics and Fast Output Response
~
Co)
o
.....
11
g
o....
....
.....
g
o....
15k
~
Co)
:!:.IDV
REFERENCE
3,12
• Combines the low Vos.
':"
O.47pF
low vos drift and low
...-
bias current of the
....MI-O-15V
~
Co)
~
LMII with the fast
response of the LF351,
~~---. . ..()VOUT
• Settling time'" B "S
for a zero to fuU-
seale transition
High Voltage, Power DAC
.-----.o--....-'IoMr-io_--o()
lk
120V
15V
VOUT
100VMAX
@lDOmA
15V
-lOY
REFERENCE
Rl
-VREFD [
R2
R2]
1+-+4096
RFb RI
VOUT~---
Uk
TL/H/S690-17
4-87
II
Application Hints (Continued)
High Current Controller
LF3511
2N3I&9A
1",;;;,--- 1
I
I
I
I
Lr' I
~.....
I
I
I
'-- I
L ___ :J
1
o
= 1 Amp(D)
4096
TLlH/5690-18
B-Blt Course, 4-Blt Vernier DAC
I;\:-
DDWNIl.
..:
~
""---j-_r-_;-_.,.A......
ENABLE
•
•
LOAD
IBIT
..[i
Vee
CLOCK
CLOCK
UP
DATA
15V~
MM14t:193
C
I.
·'3
I,
,"
I.
"I
I.
LSO
I"
DACI288
WRi
y,
XFER
y..
Will
y..
;\:-
fSFROM
A"'''~>
VOUT
t / j .."n51
DECODER
~TlNE
SYSTEM
WiiSTRDBE
TLlH/5690-20
Ordering Information
Temperature
Range
Non-Linearity
Package
DAC1208LCJ
0.012%
J24ACerdip
-40'Cto +85'C
DAC1208LCJ·1
0.012%
J24ACerdip
O'Cto +70'C
DAC1209LCJ
0.024%
J24ACerdip
-40'C to + 85'C
DAC1209LCJ·1
0.024%
J24ACerdip
O'Cto +70'C
DAC1210LCJ
0.050%
J24ACerdip
-40'Cto +85'C
DAC1210LCJ·1
0.050%
J24ACerdip
O'Cto +70'C
Part Number
DAC1230LCJ
0.012%
J20ACerdip
-40'Cto +85'C
DAC1230LCJ·1
0.012%
J20ACerdip
O'Cto +70'C
DAC1231LCJ
0.024%
J20ACerdip
- 40'C to + 85'C
DAC1231 LCJ·1
0.024%
J20ACerdip
O'Cto +70'C
DAC1232LCJ
0.050%
J20ACerdip
-40'Cto +85'C
DAC1232LCJ·1
0.050%
J20ACerdip
O'Cto +70'C
4·88
c
»
o......
NatiOnal
~ Semiconductor
N
......
Corporation
.....
c
»
o
QC)
OAC1218,OAC1219
12-Bit Binary Multiplying 01 A Converter
......
......
N
CD
General Description
The DAC1218 and the DAC1219 are 12-bit binary, 4-quadrant multiplying D to A converters. The linearity, differential
non-linearity and monotonicity specifications for these converters are all guaranteed over temperature. In addition,
these parameters are specified with standard zero and fullscale adjustment procedures as opposed to the impractical
best fit straight line guarantee.
This level of precision is achieved though the use of an
advanced silicon-chromium (SiCr) R-2R resistor ladder network. This type of thin-film resistor eliminates the parasitic
diode problems associated with diffused resistors and allows the applied reference voltage to range from -25V to
25V, independent of the logic supply voltage.
CMOS current switches and, drive circuitry are used to
achieve low power consumption (20 mW typical) and minimize output leakage current errprs (10 nA maximum).
Unique digital input circuitry maintains TTL compatible input
threshold voltages over the full operating supply voltage
range.
The DAC1218 and DAC1219 are direct replacements for
the AD7541 series, AD7521 series, and AD7531 series with
a significant improvement in the linearity specification. In
applications where direct interface of the D to A converter to
a microprocessor bus is desirable, the DAC1208 and
DAC1230 series eliminate the need for additional interface
logic.
Features
• Linearity specified with zero and full-scale adjust only
• Logic inputs which meet TTL voltage level specs (1.4V
logiC threshold)
• Works with ± 1OV reference-full 4-quadrant
multiplication
• All parts guaranteed 12-bit monotonic
Key Specifications
1 JLs
12 Bits
12 Bits (DAC1218)
11 Bits (DAC1219)
1.5 ppml'C
20 mW
5 Voc to 15 Voc
• Current Settling Time
• Resolution
• Linearity (Guaranteed
over temperature)
• Gain Tempco
• Low Power Dissipation
• Single Power Supply
Typical Application
Connection Diagram
Dual-In-Line Package
'CUll
18
•
R'b
11
IOUT2
VRE'
16
GND
Vee
15
A1(MSB!
±1DV
14
A2
Al1
13 A1D
A3
12
A4
A9
11 AS
A5
TLlH15691-1
A121LSBI
10
A6
A7
TLIH15691-15
where: AN = 1 if digital input is high
Top View
AN = 0 if dlgitallnpul is low
Ordering Information
O·Cto +70·C
-40·C to +85·C
0.012%
DAC1218LCJ-1
DAC1218LCJ
J1BACerdip
0.024%
DAC1219LCJ-1
DAC1219LCJ
J18A Cerdip
Temperature Range
Non
Linearity
I
I
4-89
Package Outline
Absolute Maximum Ratings (Notes 1 and 2)
Operating Conditions
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (Vee)
17Voe
Temperature Range
DAC1218LCJ,DAC1219LCJ
DAC1218LCJ·1, DAC1219LCJ·1
Voltage at Any Digital Input
Voltage at VREF Input
Storage Temperature Range
TMIN S; TA S; TMAX
-40"C S; TA s: +85·C
O·C S; TA S; 70"C
Range of Vee
Voltage at Any Digital Input
VeetoGND
±25V
5 Voe to 16 Voe
VeetoGND
- 65·C to + 150·C
Package Dissipation at TA = 25·C (Note 3)
500mW
DC Voltage Applied to IOUT1 or IOUT2
(Note 4)
-100 mVto Vee
Lead Temp. (Soldering, 10 seconds)
ESD Susceptibility (Note 11)
300·C
800V
Electrical Characteristics
VREF = 10.000 Voe, Vee = 11.4 Voe to 15.75 Voe unless otherwise noted. Boldface limits apply from TMIN to TMAX (see
Note 9); all other limits TA = TJ = 25·C.
Parameter
Conditions
Notes
Resolution
Linearity Error
(End Point Linearity)
Differential Non·Linearity
Zero and Full·Scale
Adjusted
DAC1218
DAC1219
4,5,9
Zero and Full·Scale
Adjusted
DAC1218
DAC1219
4,5,9
Monotonicity
Gain Error (Min)
Gain Error (Max)
Using Internal RFb,
VREF = ±10V, ±1V
Gain Error Tempco
Typ
(Note 10)
Tested
Limit
(Note 11)
Design
Limit
(Note 12)
Units
12
12
12
Bits
0.012
0.024
0.012
0.024
%ofFSR
%ofFSR
0.018
0.024
0.018
0.024
%ofFSR
%ofFSR
12
4
12
12
5
-0.1
0.0
5
-0.1
-0.2
5
±1.3
Bits
% ofFSR
% ofFSR
±6.0
ppm of FSI"C
Power Supply Rejection
All Digital Inputs High
5
±3.0
±30
Reference Input Resistance
(Min)
9
15
10
10
kO
(Max)
9
15
20
20
kO
Output Feedthrough Error
VREF= 120 Vp·p, f= 100 kHz
All Data Inputs Low
6
3.0
Output Capacitance
All Data Inputs
High
All Data Inputs
Low
mVp·p
200
70
70
200
pF
pF
pF
pF
2.0
2.5
mA
10
10
10
10
nA
nA
IOUT1
IOUT2
IOUT1
IOUT2
Supply Current Drain
Output Leakage Current
IOUT1
IOUT2
9
ppm of FSRIV
7,9
All Data Inputs Low
All Data Inputs High
Digital Input Threshold
Low Threshold
High Threshold
9
0.8
2.2
0.8
2.2
Voe
Voe
Digital Input Currents
Digital Inputs <0.8V
Digital Inputs > 2.2V
9
-200
10
-200
10
IotAoe
IotAoe
ts Current Settling Time
RL = 1000, Output Settled
to 0.Q1 %, All Digital Inputs
Switched Simultaneously
1
4·90
lots
c
Electrical Characteristics Notes
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 3: This 500 mW specification applies for all packages. The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify
the power dissipation) removes concern for heat sinking.
Note 4: Both loun and IOUT2 must go to ground or the virtual ground of an operational amplifier. The linearity error is degraded by approximately Vas-=- VREF- For
example. il VREF~ 10V then a I mV oHset, Vas, on IOUT1 or IOUT2 will introduce an additional 0.01 % linearity error.
Note 5: The unit FSR stands for full-scale range. Linearity Error and Power Supply Rejection specs arB based on this unit to eliminate dependence on a particular
VREF value to indicate the true performance 01 the part. The Linearity Error specification 01 the DACI21 B is 0.012% 01 FSR. This guarantees that after performing a
zero and lull·scale adjustment, the plot 01 the 4096 analog voltage outputs will each be within 0.012% x VREF of a straight line which passes through zero and lullscale. The unit ppm 01 FSR (parts per million 01 lull·scale range) and ppm 01 FS (parts per million 01 lull·scale) are used lor convenience to define specs 01 very
small percentage values, typical of higher accuracy converters. 1 ppm of FSR =VREF/1 06 is the conversion factor to provide an actual output voltage quantity. For
example, the gain error tempeo spec of ±6 ppm of FS/oC represents a worst-case full-scale gain error change with temperature from -40°C to +85°C of
±(6)(VREFfI06)(125'C) or ±0.75 (10- 3) VREF which is ±0.075% of VREF.
Note 6: To achieve this low leedthrough in the D package, the user must ground the metal lid. If the lid is left floating the leedthrough Is typically 6 mY.
Note 7: A 10 nA leakage current with RFb~20k and VREF~IOV corresponds to a zero ernor 01 (IOXIO-9X20XI03)XIOO% 10V or 0.002% 01 FS.
Note 8: Human body model, 100 pF discharged through 1.5 kn resistor.
Note 9: Tested limit lor -I sulfix parts applies only at 25'C.
Note 10: Typicals are at 25'C and represent the most likely parametric norm.
Note 11: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 12: DeSign limits are guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Typical Performance Characteristics
Digital Input Threshold
vsVcc
Digital Input Threshold
vs Temperature
Z.4
2.4
~
~
~
....
"
l;"
I
1.&
TA. I-40'C_
12
TA=25°C
~
i!
0.8
I
i.--
TA"85'C -
f--
OA
I
0
I
0
----
....
~
~
~
i!:
..
II
z.o
1.&
I.Z
~
~
i!
0.8
0.4
II
0
10
5
-35 -t5
15
5
25 45 65 85
TA - AM81ENT TEMPERATURE I'C)
VCC-SUPPLYVOLTAGE IV)
Gain and Linearity Error
Variation vs Temperature
Gain and Linearity Error
Variation vs Supply Voltage
TA'25'C
~ -0.005
!
1-+:.,:;+""+-1-1-+:+-+-1
-0.011-=+-+-+-1-1-+-+-+-1
-55 -35 -15
5
10
Z5 45 65 85 t05 t25
TA - AM81ENT TEMPERATURE I'CI
15
VCC - SUPPLY VOLTAGE IVocl
TLfHf5691-2
4-91
N
......
c»
.....
Note 2: All voltages are measured with respect to GNO. unless otherwise specified.
2.0
l;
......
g
o
......
N
......
CD
~.-----------------------------------------------------~
..N
DAC transfer characteristic. It is measured after adjusting
Definition of Package Pinouts
..-
~
"..-co
N
..-
~
for zero and full scale. Linearity error is a parameter intrinsic
to the device and cannot be externally adjusted.
National's linearity test (a) and the best straight line test (b)
used by other suppliers are illustrated below. The best
straight line (b) requires a special zero and FS adjustment
for each part, which is almost impossible for the user to
determine. The end point test uses a standard zero FS adjustment procedure and is a much more stringent test for
DAC linearity.
Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output.
Settling Time: Full-scale current settling time requires zero
to full-scale or full-scale to zero output change. Settling time
is the time required from a code transition until the DAC
output reaches within ± 1/2 LSB of the final output value.
(A1-A12): Digital Inputs. A12 is the least significant digital
input (LSB) and A 1 is the most significant digital input
(MSB).
IOUT1: DAC Current Output 1. IOUTl is a maximum for a
digital input of all 1s, and is zero for a digital input of all Os.
IOUT2: DAC Current Output 2. IOUT2 is a constant minus
IOUT1' or loun + IOUT2 = constant (for a fixed reference
voltage).
RFb: Feedback Resistor. The feedback resistor is provided
on the IC chip for use as the shunt feedback resistor for the
external op amp which is used to provide an output voltage
for the DAC. This on-chip resistor should always be used
(not an external resistor) since it matches the resistors in
the on-chip R-2R ladder and tracks these resistors over
temperature.
VREF: Reference Voltage Input. This input connects to an
external precision voltage source to the internal R-2R ladder. VREF can be selected over the range of 10V to -10V.
This is also the analog voltage input for a 4-quadrant multiplying DAC application.
Full-scale Error: Full-scale error is a measure of the output
error between an ideal DAC and the actual device output.
Ideally, for the DAC1218 full-scale is VREF-1 LSB. For
VREF= 10V
and
unipolar
operation,
VFULLSCALE=10.0000V-2.44 mV=9.9976V. Full-scale error is
adjustable to zero.
Differential Non-Linearity: The difference between any
two consecutive codes in the transfer curve from the theoretical 1 LSB is differential non-linearity.
Monotonic: If the output of a DAC increases for increasing
digital input code, then the DAC is monotonic. A 12-bit DAC
which is monotonic to 12 bits simply means that input increasing digital input codes will produce an increasing analog output.
Vee: Digital Supply Voltage. This is the power supply pin for
the part. Vcc can be from 5 Voc to 15 Voc. Operation is
optimum for 15 Voc.
GND: Ground. This is the ground for the circuit.
Definition of Terms
Resolution: Resolution is defined as the reciprocal of the
number of discrete steps in the DAC output. It is directly
related to the number of switches or bits within the DAC. For
example, the DAC1218 has 212 or 4096 steps and therefore
has 12-bit resolution.
Linearity Error: Linearity error in the maximum deviation
from a straight line passing through the endpoints of the
b) Shifting FS adjust to pass best straight line test
a) End point test after zero and FS adjust
TL/H/5691-3
4-92
~
o....
Application Hints
The DAC1218 and DAC1219 are pin·for-pin compatible with
the DAC1220 series but feature 12 and 11-bit linearity specifications. To preserve this degree of accuracy, care must
be taken in the selection and adjustments of the output amplifier and reference voltage. Careful PC board layout is important, with emphasis made on compactness of components to prevent inadvertent noise pickup and utilization of
single point grounding and supply distribution.
2.0 CREATING A UNIPOLAR OUTPUT VOLTAGE
(A DIGITAL ATTENUATOR)
To generate an output voltage and keep the potential at the
current output terminals at OV, an op amp current to voltage
converter is used. As shown in Figure 2, the current from
loun flows through the feedback resistor, forcing a proportional voltage at the amplifier output. The voltage at loun is
held at a virtual ground potential. The feedback resistor is
provided on the chip and should always be used as it
matches and tracks the R value of the R-2R ladder. The
output voltage is the oppOSite polarity of the applied reference voltage.
1.0 BASIC CIRCUIT DESCRIPTION
Figure 1 illustrates the R-2R current switching ladder network used in the DAC1218 and DAC1219. As a function of
the logic state of each digital input, the binarily weighted
current in each leg of the ladder is switched to either IOUT1
or IOUT2. The voltage potential at IOUT1 and IOUT2 must be
at zero volts to keep the current in each leg the same, independent of the switch state.
2.1 Amplifier Considerations
To maintain linearity of the output voltage with changing
digital input codes the input offset voltage of th~. amplifier
must be nulled. The resistance from IOUT1 to ground
(R1oun) varies non·linearly with the a~plied digit~1 code
from a minimum of R with all ones applied to the Input to
near 00 with an all zeros code. Any offset voltage between
the amplifier inputs appears at the output with a gain of
The switches operate with a small voltage drop across them
and can therefore conduct currents of either polarity. This
permits the reference to be positive or negative, thereby
allowing 4-quadrant multiplication by the digital input word.
The reference can be a stable DC source or a bipolar AC
signal within the range of ± 1OV, for specified accuracy, with
an absolute maximum range of ±25V. The reference can
also exceed the applied Vee of the DAC.
The maximum output current from either IOUT1 or IOUT2 is
equal to
1+~.
R1oUT1
Since R1oUT1 varies with the input code, any offset will ~e
grade output linearity. (See Note 4 of Electrical Characteristics.)
If the desired amplifier does not have offset balancing pins
available (it could be part of a dual or quad package) the
nulling circuit of Figure 3 can be used. The voltage at the
non-inverting input will be set to - Vos initially to force the
inverting input to OV. The common technique of summing
current into the amplifier summing junction cannot be used
as it directly introduces a zero code output current error.
VREF(max) (4095)
R
4096'
where R is the reference input resistance (typically 15 kO).
A high level on any digital input steers current to loun and
a low level steers current to IOUT2.
VREFIN
2"
GND
r
lour2
I
I
I
&
AI
A
A2
I
~
A3
I
I
I
I
b
A4
A
A5
I
I
I
~
A6
I
I
I
I
I
I
A
b
~
I
I
A
Al
Aa
A9
AID
I
I
I
I
I
b
All
b
An
ILSBI
(Msal
lour1
RFEEDBACK
TL/H/5691-4
Nole: Switches shown in digital high state.
FIGURE 1. The R-2R Current Switching Ladder Network
4-93
....CO
N
......
C
....~
....
CO
N
Application Hints (Continued)
FULL-SCALE
ADJUST
RFb
(INTERNAL) 18
Msa
IBV
1& VCC
DACI218
tiDY
REFERENCE
A1
VOUT = -VREF ( -
2
A2.
A3
YOUT
17 YREF
A12 )
+ -4 + -8 + "'4096
-
where: AN = 1 II digital inpul is high
-1&V
AN = 0 H digital inpul is low
TLlH/5691-5
FIGURE 2. Unipolar Output Voltage
OACI!18
VOUT
TLlH/5691-6
FIGURE 3. Zeroing an Amplifier Which Does Not Have Balancing Provisions
2.3 Output Settling Time
The selected amplifier should have as Iowan input bias
current as possible since input bias current contributes to
the current flowing through the feedback resistor. BI-FETTM
o~ amps such as the LF356 or LF351 or bipolar op amps
with super {3 input transistors like the LM11 or LM308A produce negligible errors.
The output voltage settling time for this circuit in response
to a change of the digital input code (a full-scale change is
the worst case) is a combination of the DAC's output current
settling characteristics and the settling characteristics of the
output amplifier. The amplifier settling is further degraded by
a feedback pole formed by the feedback resistance and the
D.AC output capacitance (which varies with the digital code).
First order compensation for this pole is achieved by adding
a feedback zero with capacitor Cc shown in Figure 2.
2.2 Zero and Full-Scale Adjustments
The fundamental purpose is to make the output voltages as
near 0 Voc as possible. This is accomplished in the circuit
of Figure 2 by shorting out the amplifier feedback resistance, an~ adjusting the Vos nulling potentiometer of the op
amp until the output reads zero volts. This is done, of
course, with an applied digital input of all zeros if IOUT1 is
driving the op amp (all ones for IOUT2). The feedback short
is then removed and the converter is zero adjusted.
In many applications output response time and settling is
just as important as accuracy. It can be difficult to find a
single op amp that combines excellent DC characteristics
(low Vos, Vos drift and bias current) with fast response and
s~ttling ti~e. BI-FET op amps offer a reasonable compromise of high speed and good DC characteristics. The circuit
of Figure 4 illustrates a composite amplifier connection that
combines the speed of a BI-FET LF351 with the excellent
DC input characteristics of the LM 11. If output settling time
is not so critical, the LM11 can be used alone.
A unique characteristic of these DACs is that any full-scale
or gain error is always negative. This means that for a fulls~ale input code the output voltage, if not inherently correct,
will always be less than what it should be. This ensures that
adding an appropriate resistance in series with the internal
feedback resistor, RFb, will always correct for any gain error.
The 50n potentiometer in Figure 2 is all that is needed to
adjust the worst case DAC gain error.
Figure 5 is a settling time test circuit for the complete voltage output DAC circuit. The circuit allows the settling time of
the DAC amplifier to be measured to a resolution of 1 mV
out of a zero to ± 10V full-scale output change on an oscilloscope. Figure 6 summarizes the measured settling times
for several output amplifiers and feedback compensation
capaCitors.
Conversion accuracy is only as good as the applied reference voltage, so providing a source that is stable over time
and temperature is important.
4-94
~.....
Application Hint (Continued)
N
.....
~
C
~
.....
N
.....
CQ
±VREF
OAC1Z18
17 VREF
0.1
-15V
Z
>:.....--......-0 VOUT
-15V
TL/H/5691-7
FIGURE 4. Composite Output Amplifier Connection
15V
PULSE GENERATOR
INPUT
OV-5V
(0.....-
...
±1DV
.50
SETILE
SIGNAL
OUT
(TO SCOPE)
Diode. are lN4148
TL/H/6691-8
FIGURE 5. DAC Settling Time Test Circuit
Amplifier
Cc
Settling Time to 0.010/0
LM11
LF351
LF351
Composite
LM11-LF351
LF356
20pF
15 pF
30pF
30 p.s
8 p.s
5 p.s
20pF
8 p.s
15 pF
6 p.s
FIGURE 6. Some Measured Settling Times
4-95
~r---------------------------------------------------~--~
..CN
Application Hints (Continued)
..-
~......
CD
..-
CN
..o
C§
where 0 is the decimal equivalent of the true binary input
word. This configuration inherently accepts a code (halfscale or 0 = 2048) to provide OV out without requiring an
external % LSB dffset as needed by other bipolar multiplying DAC circuits.
Only the offset voltage of amplifier A 1 need be nulled to
preserve linearity. The gain setting resistors around A2 must
match and track each other. A thin film, 4-resistbr network
available from Beckman Instruments, Inc. (part no. 694-3R10K-D) is ideally suited for this application. Two of the four
r~istors can be paralleled to form R and the other two can
be used separately as the resistors labeled 2R.
Operation is summarized in the table below:
3.0 OBTAINING A BIPOLA~ OUTPUT VOLTAGE
FROM A FIXED REFERENCE
The addition of a second op amp to the circuit of Figure 2
can generate a bipolar output voltage from a fixed reference
voltage (Figure 7). This, in effect gives sign significance to
the MSB of the digital input word to allow two quadrant mUltiplication of the reference voltage. The polarity of the reference voltage can also be reversed to realize full 4-quadrant
multiplication.
The output responds in accordance to the following expression:
vo --
V
REF
(0 -
2048)
2048
,OS: 0
s: 4095
Applied
Digital Input
MSB
1
0
0
1
0
0
0
0
0
0
Decimal
Equivalent
LSB
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
4095
3072
2048
2047
1024
0
0
1
0
0
0
VOUT
+VREF
-VREF
VREF-1 LSB
VREF/2
0
-1 LSB
-VREF/2
-VREF
- VREFI + 1 LSB
-IVREFI/2
0
+1 LSB
+IVREFI/2
+IVREFI
Where 1 LSB = IVREFI
2048
_FULL·SCALE
ADJUST
2H"
15Y
16
2H"
lDk
2H"
:!:VnEF
-FULL-SCALE
ADJUST
. 1 " -........ YDUT
t
2H"
lDk
15k
ZEHD
ADJUST
15Y
TL/H/5691-9
·0.1 % matching
FIGURE 7. Obtaining a Bipolar Output from a Fixed Reference
4-96
.-----------------------------------------------------------------------,0
Application Hints (Continued)
3.1 Zero and Full-Scale Adjustments
4.0 MISCELLANEOUS APPLICATION HINTS
The three adjustments needed for this circuit are shown in
Figure 7. The first step is to set all of the digital inputs LOW
(to force IOUTI to 0) and then trim "zero adjust" for zero
volts at the inverting input (pin 2) of OA 1. Next, with a code
of all zeros still applied, adjust "- full-scale adjust", the reference voltage, for VOUT = ± \(ideal VREF)\. The sign of the
output voltage will be opposite that of the applied reference.
The devices are CMOS products and reasonable care
should be exercised in handling them to prevent catastrophic failures due to electrostatic discharge.
During power·up supply voltage sequencing, the negative
supply of the output amplifier may appear first. This will typically cause the output of the op amp to bias near the negative supply potential. No harm is done to the DAC, however,
as the on·chip 15 kO feedback resistor sufficiently limits the
current flow from IOUTI when this lead is clamped to one
diode drop below ground.
Finally, set all of the digital inputs HIGH and adjust "+ fullscale adjust" for VOUT=VREF (511/512). The sign of the
output at this time will be the same as that of the reference
voltage. This + full·scale adjustment scheme takes into account the effects of the Vas of amplifier A2 (as long as this
offset is less than 0.1 % of VREF) and any gain errors due to
external resistor mismatch.
As a general rule, any unused digital inputs should be tied
high or low as required by the application. As a troubleshooting aid, if any digital input is left floating, the DAC will
interpret that input as a logical 1 level.
Additional Application Ideas
For the circuits shown, D represents the decimal equivalent of the binary digital input code. D ranges from 0 (for an all zeros
input code) to 4095 (for an all ones input code) and for any code can be determined from:
D = 2048(A1)
+
1024(A2)
+
512(A2)
+ ... 2(A11) +
1(A12)
where AN = 1 if that input is high
AN = 0 if that input is low
DAC Controlled Amplifier
VIN
~
IB
Vcc
16
15V
DACl218
VREF 11
GND
":'
3
510
":'
15V
0.1 pF
>--<>-0
VDUT =-VIN(4D96)
D
TL/H/5691-10
4-97
1;
...
...
o
1;
......
N
.....
(XI
N
CD
r----------------------------------------------------------------------.
....
C'II
~
~
Additional Application Ideas (Continued)
;0
....
....
OHseHing the Zero Code Output Voltage
C'II
~
15V
16 VCC
17 VREF
>-1.....0VOUT
R2
v
_ 2VREFR2
Zero Shift - Rl + R2
TLlH/5691-11
High Current Controller
5V->50V
I&V
-IV
REFERENCE
18
I
I
I
I
I _ 1 Amp (D)
0- 4096
L__ _
\
TL/H/5691-12
4-98
~....
Additional Application Ideas (Continued)
....
g
o
....
....
CD
I\)
~
DAC Controlled Function Generator
I5V
I\)
• C1 controls maximum frequency
• <0.5% sine wave THO over range
• Range 30 kHz maximum
• Linearily-OAC limit
• f =
==,..,0=--::::-
I
4096 (4/3 RFb C)
15V
15k
a....l0VPK
Z5k
OFFSET
ADJUST
-15V
,.
!IV
Jl...
SQUARE OUT
Vee
DAeIZ,.
11 VREF
TUH/5691-13
Digitally Programmable Pulse-Width Generator
SVTL INITIALIZING
INPUT
10
'5V
2.711
STRO.Eo-~_----"M,.....---......,
ov
"
2.111
'SV
,.
loun
DAe,z ••
-VREF
17 VREF
IOUT2y!~-",-..:.j
~'5V
2D'
MtN PULSE WIDTH
CALIBRATE
-ISVOC
PW '" C(7.5V) (4096) (RFb)
OIVREF
4·99
NatiOnal
~ Semiconductor
Corporation
DAC1265A, DAC1265 Hi-Speed 12-Bit D/A Converter
with Reference
General Description
Features
The DAC1265A and DAC1265 are fast 12-bit digital to analog converters with internal voltage reference. These DACs
use 12 precision high speed bipolar current steering
switches, control amplifier, thin film resistor network, and
buried zener voltage reference to obtain a high accuracy,
very fast analog output current. The DAC1265A and
DAC1265 have 10%-90% full-scale transition time under
35 ns and settle to less than 'h LSB in 200 ns. The buried
zener reference has long-term stability and temperature drift
characteristics comparable to the best discrete or separate
IC references.
These digital to analog converters are recommended for
applications in CRT displays, preCision instruments and data
acquisition systems requiring throughput rates as high as 5
MHz for full range transitions.
• Bipolar current output DAC and voltage reference
• Fully differential, non-saturating preCision current switch
- ROUT and COUT do not change with digital input
code.
• Internal buried zener reference - 1OV ± 1 % max
• Precision thin film resistors for use with external op
amp for voltage out or as input resistors for a successive approximation AID converter
• Superior replacement for 12-bit DIA converters of this
type
Key Specifications
12 Bits
• Resolution and Monotonicity
• Linearity
12 Bits
(Guaranteed over temperature)
• Output Current Settling Time
400 ns max to 0.Q1 %
• Gain Tempco
± 15 ppml'C max
• Power Supply Sensitivity ± 10 ppm of FS/% VSUPPLY
Block and Connection Diagrams
PWR
NC
+Vs GNO
to.DY
REFERENCE 4
OUT
REFERENCE
'j t
NC
Z
1
o
o
10
r------O_LA."_'",oo,,,'
....
500
'DO
-15V
BIPOLAR OFF
"::'
----o: )
11
r-~..!!.(>-__
ZOV RANGE
"2
100
ANALOG INPUTS
5k
9.950
'5V
'0
5V
10V RANGE
5k
-
OAC
1k
10
80
'OUT· 4 II 'REF x CODE
CODE INPUT
..
LSS
13
" 9
r-~~~~~~~~~-L--'~'~'~O~AT~A~IN~
_ _ _ _ _ _ _ _~
14
"Sm!T
CLOCK
TL/H/5242-8
INPUT RANGES
Unipolar
0105
Bipolar
01010
01020
±5
±10
±2.5
FIGURE 6. Fast Precision Analog to Digital Converter
4-107
Connect
InputtoA
BloDACOUT
InputtoA
Inpullo B
Equlv.
DACZOUT
1.60kll
2.35kll
3.08kll
II
~
CD
r-------------------------------------------------------------------------------------,
....
Definition of Terms
"~
Digital Inputs: The OAC126SA and OAC126S accept digital
input codes in binary format and may be user connected for
anyone of three binary codes: straight binary, two's complement, or offset binary.
N
g
~
....
o
~
Digital
Input
MSBLSB
Analog Output
Straight
Binary
Offset
Binary
Two's
Complement'
000 .. 000
zero
-FS (Full-Scale)
011. .. 111 %FS-1 LSB
zero-1 LSB
100 .. 000
zero
%FS
111 ... 111 +FS-1 LSB
+FS-1 LSB
zero
+FS-1 LSB
-FS
zero-1 LSB
'Invert MSB with external inverter to obtain Two's Complement coding
Linearity Error: Linearity error of a 01 A converter is an
important measure of its accuracy. It describes the deviation
from an ideal straight line transfer curve drawn between
zero (all bits OFF) and full-scale (all bits ON).
Differential Non-Linearity: For a 01 A converter, it is the
difference between the actual output voltage change and
the ideal (1 LSB) voltage change for a one-bit change in
code. A differential non-linearity of ± 1 LSB or less guarantees monotonicity; i.e., the output always increases and never decreases for an increasing input. It is guaranteed by
testing the major carry transitions, i.e., 100...000 to
011 ... 111, etc.
Settling Time: Settling time is the time required for the output to settle to within the specified error band for any input
code transition. It is usually specified for a full-scale or major
carry transition.
Gain Tempco: The change in full-scale analog output over
the specified temperature range expressed in parts per million of full-scale per "C (ppm of FSrC). Gain error is measured with respect to 2S"C at high (TMAX> and low (TMIN)
temperatures. Gain tempco is calculated for both high
(TMAx-2S"C) and low (2S"C-TMIN) ranges by dividing the
gain error by the respective change in temperature. The
specification is the larger of the two representing worstcase drift.
Offset Tempco: The change in analog output with all bits
OFF over the specified temperature range expressed in
parts per million of full-scale per "C (ppm of FSrC). Offset
error is measured with respect to 2S"C at high (TMAX) and
low (TMIN) temperatures. Offset tempco is calculated for
both high (TMAX-2S"C) and low (2S"C-TMIN) ranges by
dividing the offset error by the respective change in temperature. The specification given is the larger of the two, representing worst-case drift.
Power Supply Sensitivity: Power supply sensitivity is a
measure of the change in gain and offset of the 01 A converter resulting from a change in -1SV or + 1SV supplies.
It is specified under OC conditions and expressed as parts
per million of full-scale per percent of change in power supply (ppm of FSI %).
Ordering Information
Temperature Range
Linearity Error
Over Temperature
I
I
O"Cto 70"C
- SS"C to + 12S"C
±%Bit
OAC126SACJ
OAC126SAJ
±%Bit
OAC126SLCJ
OAC126SLJ
4-108
r---------------------------------------------------------------------~
C
»
o....
NatiOnal
~ Semiconductor
N
en
en
Corporation
}>
DAC1266A, DAC1266 Hi-Speed 12-Bit D/A Converter
General Description
The DAC1266A and DAC1266 are fast 12-bit digital to analog converters. These DACs use 12 precision high speed
bipolar current steering switches, control amplifier, and a
thin film resistor network to obtain a high accuracy, very fast
analog output current. The DAC1266A and DAC1266 have
10%-90% full-scale transition time under 30 ns and settle
to less than % LSB in 200 ns.
These digital to analog converters are recommended for
applications in CRT displays, precision instruments and data
acquisition systems requiring throughput rates as high as 5
MHz for full range transitions.
Features
• Bipolar current output DAC
• Fully differential, non-saturating precision current switch
- ROUT and COUT do not change with digital input
code
• Precision thin film resistors for use with external op
amp for voltage out or as input resistors for a successive approximate AID converter
• Superior replacement for 12-bit 01 A converters of this
type
c
o»
....
N
en
en
Key Specifications
• Resolution and Monotonicity
12 Bits
• Linearity
12 Bits
(Guaranteed over temperature)
• Output Current Settling Time
400 ns max to 0.01 %
• Full-Scale Transition Time (10%-90%)
30 ns
• Power Supply Sensitivity ±15 ppm of FS/% VSUPPLY
Block and Connection Diagrams
NS
2
o
O--~::::~--~__~~--__~----~
.----------010 10V RANGE
11
20V RANGE
CURRENT OUWUT
.....----------~_o9 (SUMMING
JUNCTION)
2423222120191817161413
(MSB)
(lSB)
TL/H/506B-7
Dual-In-Line Package
NC
1
24
(MSB)BIT1
Ne
2
23
BIT2
ANALOG GROUND
3
22
BIB
AMP I~N~:~~
RErERENCE IN
4
5
21
BIT 4
20
BIT 5
-Vs
6
19
BIT 6
BIPOLAR OFFSET
7
18
BIT7
NC
8
17
BIT 8
lOUT (-2 rnA FS)
9
16
BIT9
BIT 10
10V RANGE
10
15
20V RANGE
11
14
BIT 11
POWER GROUND
12
13
(lSB) BIT 12
II
Order Number
DAC1266AJ, DAC1266ACJ,
DAC1266LJ or DAC1266LCJ
See NS Package Number J24A
TL/H/506B-l
Top View
4-109
Absolute Maximum Ratings
(Note11)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V-)
OVto -18V
Current Output (Pin 9) Voltage
Logic Input Voltage
-1V,7V
±12V
±1V
Bipolar Offset
10VRange
±12V
±12V
1000mW
TMIN:S:TA:S:TMAX
- 55·C to + 125·C
DAC1266AJ, DAC1266W
DAC1266ACJ, DAC1266LCJ
Storage Temperature Range
-3V,12V
Reference Input Voltage (Pin 5)
Analog GND to Power GND
V- to +24V
20VRange
Power Dissipation (Note 1)
Operating Temperature Range
O"Cto +70"C
-65·C to + 150·C
150·C
300·C
Maximum Junction Temperature
Lead Temp. (Soldering, 10 sec.)
ESD Susceptibility (Note 12)
TBD
Electrical Characteristics VSUPPLY= -15V± 5% and VREF= 1O.OOOV unless otherwise noted. Boldface limits apply over temperature, TMIN :>:TA:S:TMAX' For all other limits TA = 25·C.
DAC1266A
Parameter
Conditions
See
Note
Typ
DAC1266
Tested Design
Limit
Limit
(Note 2) (Note 3)
Typ
Tested Design
Limit
Limit
(Note 2) (Note 3)
Units
CONVERTER CHARACTERISTICS
Resolution
Linearity Error
Max
12
12
Zero and Full-Scale Adjusted
±Ya
±%
±%
±%
±%
AJ and LJ Suffix Parts
ACJ and LCJ Suffix Parts
Differential
Non-Linearity
Max
Zero and Full-Scale Adjusted
Monotonicity
AJ and W Suffix Parts
ACJ and LCJ Suffix Parts
Bits
LSB
4
±%
±%
±%
±%
±%
±%
±%
12
12
±0.1
±0.20
6
±0.01
7
±0.05
±0.05
12
12
12
Full-Scale
(Gain) Error
Max
R2 = 500 in Figure 1
Offset Error Max
All Bits OFF,
Logic"O"
Unipolar (Figure 1 Pin 7 Open)
Bipolar (R1 and R2=500 in
Figure 2)
Zero Error Max
MSBON
Bipolar (R1 and R2=500 in
Figure 2)
8
Gain
Adjustment
Range Min
R2 = 500 ± 500 in Figure 1
±0.2
±0.2
Bipolar Offset
Adjustment
Range Min
R1 = 500 ±500 and R2=500 in
Figure 2
±0.15
±0.15
Full-Scale (Gain)
Temperature
Coefficients Max
AJ and W Suffix
ACJ and LCJ Suffix
Unipolar Offset
Temperature
Coefficients Max
5
±0.1
±0.20
±0.05
±0.Q1
±0.05
±0.1
±0.05
±0.15
±0.1
±0.05
±O.15
% FullScale
5
5
10
3
1
1
2
2
5
5
10
10
6\0 10
7.5
6to 10
kO
-2
-1.6to
-2.4
-2
-1.6to
-2.4
mA
±1.0
±0.8to
±1.2
±1.0
±0.8to
±1.2
1
1
3
AJ and W Suffix
ACJ and LCJ Suffix
1
1
2
Bipolar Zero
Temperature
Coefficients Max
AJ and LJ Suffix
ACJ arid LCJ Suffix
5
5
10
Output
Resistance
Exclusive of Offset and Range Rs
7.5
Current Output
Unipolar
Bipolar
9
Bits
12
4-110
ppml"C
10
2
10
Electrical Characteristics
(Continued) VSUPPLY = -15V ± 5% and VREF = 1O.OOOV unless otherwise noted.
Boldface limits apply over temperature, T MIN s:TA s:TMAX. For all other limits TA = 25°C.
DAC1266A
Parameter
DAC1266
Tested Design
See
Tested Design
LImit
Limit
Limit Typ
Note Typ
Limit
(Note 2) (Note 3)
(Note 2) (Note 3)
Conditions
Output
Capacitance
25
25
Using Internal Offset and Range Rs
TypOutput
Voltage Ranges
Units
pF
±2.5, ±5, ±10, Oto 5, 0 to 10
Reference Input
Resistance
20.8 15t025
V
-1.510
10
-1.510
10
Output
Compliance
Voltage
kO
20.8 15 to 25
V
DIGITAL AND DC CHARACTERISTICS
Logic High
Bit ON
AJ and LJ Suffix
ACJ and LCJ Suffix
Logic Low
Max Bit OFF
AJ and LJ Suffix
ACJ and LCJ Suffix
Logic High
AJ and LJ Suffix
LogiC Input
Voltage
I
2105.5
1.9to 5.5 2105.5
1.0
300
ACJ and LCJ Sufix
AJ and LJ Suffix
ACJ and LCJ Suffix
45
45
100
Power Supply
Current Max
V- Supply= -15V± 10%
-12
Power
Dissipation Max
V- Supply= -15V
Power Supply
Sensitivity Max
V- Supply= -12V±5%
V- Supply= -15V± 10%
Logic Low
0.8
0.8
150
150
Logic Input
Current Max
V
2105.5
1.9to 5.5 2105.5
0.8
1.0
0.8
300
300
150
150
45
45
100
100
-18
-12
-16
mA
180
270
180
270
mW
10
±15
±25
±15
±25
ppmofFS/
10
±15
±25
±15
±25
% VSUPPLY
280
90
280
90
p.A
300
100
AC CHARACTERISTICS
Settling
Time Max
FSRChange
200
400
Full-scale
Transition Max
200
400
Delay Plus 10% to 90% Rise Time
15
Delay Plus 90% to 10% Fall Time
30
30
15
30
50
30
50
ns
ns
Note 1: The typical IJJA of the 24-pin package is 80' C/W.
Nota 2: Tested and guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 3: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 4: Linearity error
= VOUT - VOFF~~B- (0 x
Note 6: Unipolar offset error for 10V range
Note 7: Bipolar offset error for 10V range
Note 9: Gain error tempeo
= (VFS -
= VFS ~:;FSET and 0 is the digital Input (0 to 4095) which produced VOUT'
= (VFS -
Note 5: Percent gain error for 10V range
Note 8: Bipolar zero error for 10V range
VLSB) where VLSB
=
VOFFSET) - (4095/4096)VREF X 100.
VREF
(VOUTIVREF) x 100 In percent of full·scale.
= VOUT -V(-VREF/2)
=
X 100 in percent of full·scale.
REF
(VOUTIVREF) x 100 in percent of full-scale.
VOFFSET) at (TMAXorTMIN) - (VFS - VOFFSET) at 25'C X lOS In ppmrC.
10V rl!"ge x (TMAX or TMIN - 25'C)
Note 10: Power supply sensitivity for 10V range = lOS X (VFS - VOFFSET)at (-13.5V) - (VFS - VOFFSET) at (-16.5V) in ppm of FS/% Vs.
VREF X 20%
Note 11: Absclute Maximum Ratings Indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when
operating the device beyond Its specified operating conditions.
Note 12: Human body model, 100 pF discharged through a 1.5 kn resistor.
4-111
Functional Description and
Applications
1.2 Bipolar Configuration (Figure 2)
1.0 BUFFERED VOLTAGE OUTPUT CONNECTION
The standard current·to·voltage conversion connections us·
ing an operational amplifier are shown here with the pre·
ferred trimming techniques. If a low offset operational amplifier (LF401A) is used, excellent performance can be obtained in many situations without trimming (an op amp with
less than 0.5 mV maximum offset voltage should be used to
keep offset errors below % LSB). Unipolar zero will typically
be within ± % LSB (plus op amp offset), and if a 500 fixed
resistor is substituted for the 1000 trimmer (R2, Figure 1),
full-scale accuracy will be within 0.1 % (0.20% maximum).
Substituting a 500 resistor for the 1000 bipolar offset trimmer (R1, Figure 2) will give a bipolar zero error typically
within ±2 LSB (0.05%).
This configuration will provide a bipolar output voltage from
-5.000V to 4.9976V, with positive full-scale occurring with
all bits ON (all 1s).
Step 1-offset Adjust
Turn OFF all bits. Adjust 1000 offset trimmer, R1, to give
-5.000Voutput.
Step 2-Galn Adjust
Turn ON all bits. Adjust 1000 gain trimmer, R2, to give a
reading of 4.9976V.
Please note that it is not necessary to trim the op amp to
obtain full accuracy at room temperature. In most bipolar
situations, an op amp trim is unnecessary unless the untrimmed offset drift of the op amp is excessive. Bipolar zero
error (MSB bit ON) is not adjusted separately and is typically
< ± 0.05% of FS after offset and gain adjust.
1.1 Unipolar Configuration (Figure 1)
This configuration will provide a unipolar OV to 9.9976V output range.
1.3 Other Voltage Ranges (Figure 3)
The DAC1266A and DAC1266 can also be easily configured
for a unipolar OV to 5V range or ± 2.5V and ± 1OV bipolar
ranges by using the additional 5k application resistor provided at the 20V range R terminal, pin 11. For a 5V span (OV to
5Vor ±2.5V), the two 5k resistors are used in parallel by
shorting pin 11 to pin 9 and connecting pin 10 to the op amp
output and the bipolar offset either left open for unipolar or
connected through a 1000 pot to the external
Step 1-offset Adjust (Zero)
Turn all bits OFF and adjust zero trimmer, R1, until the output reads O.OOOV (1 LSB = 2.44 mY). In most cases this trim
is not needed.
Step 2-Galn Adjust
Turn all bits ON and adjust 1000 gain trimmer, R2, until the
output is 9.9976V (full-scale adjusted to 1 LSB less than
nominal full-scale of 10.000V). If a 10.2375V full-scale is
desired (exactly 2.5 mVfbit), insert a 1200 resistor in series
with the gain resistor at pin 10 to the op amp output or use
the LH0071 voltage reference.
15V
lOOk
50k
i"'
100
-15V
-=
BIPOLAR OFF
II
DAC1266A
oACl266
5k
9.95k
-
20V RANGE
IREF
B.SmA
5k
V+
oAC
-
OUTPUT
OVTD 10V
'0
ANA
GNO
6
8k
13
-VS
- - - - - - - . - lSB
TL/H/5068-2
FIGURE 1. OV to 10V Unipolar Voltage Output
4-112
-Power and analog ground must have
a common current return path. See
section 3.0 for proper connections.
Functional Description and Applications
(Continued)
Rl
100
BIPOLAR OFF
zav RANGE
11
DAC1Z66A
9,95k
5k
DAC1266
10
OUTPUT
5k
y+
I'::.~
DAC
-5V TO 5Y
___t--t-<>-~
10
8k
ANA
GND
lOUT = 4 x 'REF
lit
CODE
13
-Ys
LS8
TLiH/S068-6
'Power and analog ground must have
a common current return path. See
section 3.0 for proper connections.
FIGURE 2. ± 5V Bipolar Voltage Output
Rl
100
BIPOLAR OFF
11
ZOV RANGE
DAC1266A
9,9Sk
5k
DAC1266
AMP
10
SUMMING
JUNCTION
tOV RANGE
19.9Sk
tOpF
5k
REF IN
y+
DAC
20k
--
OUTPUT
-10VTO
10
ANA
GND
10V
Ok
'OUT" 4 II: 'REF x COOE
CODE INPUT
':'
':'
13
-Vs
LSB
TL/H/S068-3
FIGURE 3. ± 10V Voltage Output
"Power and analog ground must have
a common current return path. See
section 3.0 for proper connections.
4-113
Functional Description and
Applications (Continued)
reference for the bipolar range. For the ± 10V range use the
5k resistors in series by connecting only pin 11 to the op
amp output and connecting the bipolar offset as shown. The
± 10V option is shown in Figure 3.
The analog ground at pin 3 is the ground reference point for
the internal reference and is thus the "high quality" ground;
it should be connected directly to the analog reference point
of the system. The power ground at pin 12 can be connected to the most convenient ground reference pOint; analog
power return is preferred, but digital ground is acceptable. If
power ground contains high frequency noise beyond 200
mV, this noise may feed through the converter, so that
some caution will be required in applying these grounds.
2.0 DIGITAL INPUT
The DAC1266A and DAC1266 use a standard positive true
straight binary code for unipolar outputs (all 1s give fUllscale output), and an offset binary code for bipolar output
ranges. In the bipolar mode, with all Os on the inputs, the
output will go to negative full-scale; with 100•.. 00 (only the
MSB on), the output will be O.OOV; with all1s, the output will
go to positive full-scale.
4.0 OUTPUT VOLTAGE COMPLIANCE
The DAC1266A and DAC1266 have a typical output compliance range from -2V to 10V. The current-steering output
stages will be unaffected by changes in the output terminal
voltage over that range. However, there is an equivalent
output impedance of 8k in parallel with 25 pF at the output
terminal which produces an equivalent error current if the
voltage deviates from power ground. This is a linear effect
that does not change with input code. Operation beyond the
compliance limits may cause either output stage saturation
or breakdown which results in non-linear performance.
Compliance limits are a function of output current and negative supply.
The threshold of the digital input circuitry is set at 1.4V and
does not vary with supply voltage. The input lines can interface with any type of 5V logic, nLlDTL or CMOS, and. have
sufficiently low input currents to interface easily with unbuffered CMOS logic. The configuration of the input circuit is
shown in Figure 4. The input line can be modelled as a 30
kO resistance connected to a -0.7V rail.
5.0 DIRECT UNBUFFERED VOLTAGE OUTPUT FOR
CABLE DRIVING
The wide compliance range allows direct current-to-voltage
conversion with just an output resistor. Figure 5 shows a
connection using the gain and bipolar output resistors to
give a ± 1.60V bipolar SWing. In this situation, the digital
code is complementary binary. Other combinations of internal and external output resistors (Ax) can be used to scale
to alternate voltage ranges, simply by appropriately scaling
the 0 mA to -2 mA unipolar output current and using the
10.0V reference voltage for bipolar offset. For example, setting Ax = 2.67 kO gives a ± 1V range with a 1 kO equivalent
output impedance.
This connection is espeCially useful for directly driving a
long cable at high speed. Using a 500 resistor for Ax would
allow interface to a 500 cable with a ± 50 mV full-scale
swing.
DIGITAL
INPUTS
(PINS 13TD 24)
30k
-O.lV
)---() TD LDGIC
TLlH/5068-4
FIGURE 4. Equivalent Digital Input Circuit
3.0 APPLICATION OF ANALOG AND POWER GROUND
The DAC1266A and DAC1266 have separate analog and
power ground pins to allow optiinum connections for low
noise and high speed performance. The two ground lines
can be separated by up to 200 mV without any loss in performance. There may be some loss in linearity beyond that
level. If these DACs are to be used in a system in which the
two grounds will be ultimately connected at some distance
from the device, it is recommended that parallel back-toback diodes be connected between the ground lines near
the device to prevent a fault condition.
6.0 HIGH SPEED 12-BIT AID CONVERTERS
The fast settling characteristics of the DAC1266A and
DAC1266 make them ideal for high speed successive approximation AID converters. Shown in Figure 6 is a configuration using standard components; this system completes a
full 12-bit conversion in 10 ,",S unipolar or bipolar. This converter will be accurate to ± Yz LSB of 12 bits and have a
typical gain TC of 10 ppmrC.
'
4-114
Functional Description and Applications (Continued)
50
~O.t"F
BIPOLAR OFF
"
11
zov RANGE
DACl266A
"
995k
DAC1266
1O
IREF
IOV RANGE
E.~m~
19 9~k
5k
REF IN
V·
ANA
GNU 3
-- "
DAC
20.
OAC OUT
'D
lOUT" 4 II IREF
It
CODE
RX
CODE INPUT
13
-Vs
lS8
FIGURE 5. Unbuffered Bipolar Voltage Output
BIPOLAR UNIPOLAR
lOOk
1O.........IWIr-...
R3
lOa
f
ISV
~;k(UNIPOlAR}
tao
-15V
BIPOLAR OFF
.".
11
: ) ANALOG INPUTS
20VRANGE
9.95k
DAC1266A
"
QAel266
AMP
SUMMING
JUNCTION
ISV
1O
5V
IOVRANGE
19.95k
REF
V·
'N
DAC
20k
ANA
GND
--
"
"
'0
lOUT;; 4111REF II CODE
CODE INPUT
MS.
to
US
13
II
-VS
DIG out
~ --"LS",'++++-+-bI-:-1H-f-+
...
"""7"(
21
16 9
mlii~ --2.0
SERIAL OUT
11
"f'f
----.,;!~OD
DM25D4 SAR
~~E~~__________~~
DATA IN
14 'STAiiT
CLOCK
TL/H/50S8-5
Input Ranges
Unipolar Bipolar
0105
±2.5
01010
01020
±IO
FIGURE 6. Fast Precision Analog to Digital Converter
4-115
±5
Connect
InpulloA
BloDACQUT
Inpul 10 A
Inpullo B
Equlv.
DACZOUT
I.S0kO
2.35kO
3.08kO
Functional Description and
Applications (Continued)
In the unipolar mode, the system range is OV to 9.9976V,
with each bit having a value of 2.44 mV. For true conversion
accuracy, an AID converter should be trimmed so that a
given output code results from input levels from 112 LSB below to 112 LSB above the exact voltage represented by that
code. Therefore, the converter zero point should be
trimmed with an input voltage of 1.22 mV; trim R1 until the
LSB just begins to appear in the output code (all other bits
"0"). For full-scale, use an input voltage of 9.9963V (10V-l
LSB-1f2 LSB); then trim R2 until the LSB just begins to appear (all other bits "1 ").
The bipolar signal range is -5.0V to 4.9976V. Bipolar offset
trimming is done by applying a -4.9988V input signal and
trimming R3 for the LSB transition (all other bits "0").
Full-scale is set by applying a 4.9963V and trimming R2 for
the LSB transition (all other bits "1 "). In many applications,
the pretrimmed internal resistors are sufficiently accurate
that external trimmers will be unnecessary, especially in situations requiring less than full 12-bit ± 112 LSB accuracy.
For fastest operation, the impedance at the comparator
summing node must be minimized. However, lowering the
impedance will reduce the voltage signal to the comparator
(at an equivalent impedance at the summing node of 1 kO,
1 LSB = 0.5 mV), to the point that comparator performance
will be sacrificed. The contribution to this impedance from
the OAC will vary with the input configuration (Figure 6, Input
Ranges Table).
To prevent dynamic errors, the input signal should have a
low dynamic source impedance, such as that of the LF411 A
op amp.
Definition of Terms
Digital Inputs: The OAC1266A and OAC1266 accept digital
input codes in binary format and may be user connected for
anyone of three binary codes: straight binary, two's complement, or offset binary.
Analog Output
Digital
Input
MSBLSB
Straight
Binary
Offset
Binary
- FS (Full-Scale)
000... 000
zero
011 ... 111 112 FS-l LSB
zero-I LSB
100...000
zero
112 FS
111...111 + FS-l LSB
+FS-l LSB
Two's
Complement·
Linearity Error: Linearity Error of a 01 A converter is an
important measure of its accuracy. It describes the deviation
from an ideal straight line transfer curve drawn between
zero (all bits OFF) and full-scale (all bits ON).
Differential Non-Linearity: For a Of A converter, it is the
difference between the actual output voltage change and
the ideal (1 LSB) voltage change for a one-bit change in
code. A differential non-linearity of ± 1 LSB or less guarantees monotonicity; i.e., the output always increases and never decreases for an increasing input. It is guaranteed by
testing the major carry transitions; i.e., 100...000 to
011 ... 111 etc.
Settling Time: Setting time is the time required for the output to settle to within the specified error band for any input
code transition. It is usually specified for a full-scale or major
carry transition.
Gain Tempeo: The change in full-scale analog output over
the specified temperature range expressed in parts per million of full-scale per DC (ppm of FSrC). Gain error is measured with respect to 25DC at high (TMAX> and low (TMIN)
temperatures. Gain tempco is calculated for both high
(TMAX-25DC) and low (25DC-T MIN) ranges by dividing the
gain error by the respective change in temperature. The
speCification is the larger of the two representing worstcase drift.
Offset Tempeo: The change in analog output with all bits
OFF over the specified temperature expressed in parts per
million of full-scale per DC (ppm of FSrC). Offset error is
measured with respect to 25DC at high (TMAX) and low
(TMIN) temperatures. Offset tempco is calculated for both
high (TMAX-25DC) and low (25DC- TMIN) ranges by dividing
the offset error by the respective change in temperature.
The speCification given is the larger of the two, representing
worst-case drift.
Power Supply Sensitivity: Power supply sensitivity is a
measure of the change in gain and offset of the OfA converter resulting from a change in -15V supply. It is specified under DC conditions and expressed as parts per million
of full-scale per percent of change in power supply (ppm of
FSf%).
zero
+FS-l LSB
-FS
zero-I LSB
·'nvert MSB with external inverter to obtain Two's Complement coding
Ordering Information
O"C to 70"C
-S5"C to + 12SDC
± 112 Bit
OAC1266ACJ
OAC1266AJ
±% Bit
OAC1266LCJ
OAC1266LJ
Temperature Range
Linearity Error
OverTemperature
I
I
~~~--~-----------+--------------;
4-116
~ Semiconductor
NatiOnal
ADVANCED INFORMATION
c):0o......
en
U1
U1
Corporation
OAC1655 16-Bit 01 A Converter
General Description
Features
The OAC1655 is a 16-bit digital-to-analog converter. The
OAC1655 consists of CMOS switches and thin film SiCr resistors connected to form a 4k potentiometer with an output
impedance of 40 k!l. This 16-bit 01 A converter is monotonic to 16 bits over the specified temperature range. Force
and sense functions minimize gain and offset errors.
•
•
•
•
The analog output voltage range is GNO to the applied voltage reference.
The power diSSipation is 28 mW at 10V supply. The power
dissipation of each internal resistor does not change regardless of input data code which results in very low superposition error.
These digital-to-analog converters are recommended as
16-bit digitally controlled potentiometers. They look identical
to mechanical potentiometers within the digital supply common mode voltage range.
The OAC1655 is also ideal for applications in precision instruments and data acquisition systems.
•
•
•
•
•
•
•
•
16-bit monotonicity over temperature
Full potentiometer capability
Single 5V to 15V supply operation
OV to 10V output with constant 40 k!l output impedance
Offset error: ± 0.002% of full scale
Full scale error: ±0.003% of full scale
Full scale tempco: ± 0.3 ppml"C
Integral nonlinearity: ±0:012% or ±0.05%
Settling time: 14 I-'s to 16 bits
Output noise: 25 nV I,JHZ
Supply current: 300 ",A
STD 0.6" 24-pin dual-in-line package
Typical Application
Connection Diagram
Dual-In-Line Package
HIGH
SENSE
20
HIGH
FORCE
68.0.
4K
(~S8) D,S
24
DIGITAL GND
D'4
D'3
23
LOW FORCE
3
22
LOW SENSE
D12
4
21
DIGITAL Vee
D"
D'0
5
20
HIGH FORCE
19
HIGH SENSE
D9
23
LOW
FORCE
D8
71.0.
8
NC
16
Do (LS8)
15
D,
Ds
11
14
D2
D4
12
13
D3
D6
TLlH/9286-1
TLlH/9286-2
Top View
4-117
OUTPUT
17
10
D7
LOW
SENSE
18
II
Section 5
Sample and Hold
Section 5 Contents
Sample and Hold Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample and Hold Selection Guide .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LF198/LF298/LF198A/LF398A Monolithic Sample and Hold Circuits.... .................
LF13006/LF13007 Digital Gain Set. ...... .... .... .. ... ..... ..... ... . . ..... ..... ..... .
LH0023/LHo023C/LH0043/LH0043C Sample and Hold Circuits .........................
LH0053/LH0053C High Speed Sample and Hold Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LH0091 True RMS to DC Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LH0094 Multifunction Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5·2
5·3
5·4
5·5
5·15
5·22
5·23
5·24
5·29
r-------------------------------------------------------------~~
DI
3
CD
~ Semiconductor
NatiOnal
"C
Corporation
DI
:::s
c.
Sample and Hold
Definition of Terms
::z::
o
fc
=
CD
:::s
~
Acquisition Time: The time required to acquire a new analog input voltage with an output step of 10V. Note that acquisition time is not just the time required for the output to
settle, but also includes the time required for all internal
nodes to settle so that the output assumes the proper value
when switched to the hold mode.
-Gain Error: The ratio of output voltage swing to input voltage swing in the sample mode expressed as a percent difference.
Aperture Time: The delay required between "Hold" command and an input analog transition, so that the transition
does not affect the held output.
Hold Step: The voltage step at the output of the sample
and hold when switching from sample mode to hold mode
with a steady (DC) analog input voltage. Logic swing is 5V.
Hold Settling Time: The time required for the output to
settle within 1 mV of final value after the "hold" logic command.
DynamiC Sampling Error: The error introduced into the
held output due to a changing analog input at the time the
hold command is given. Error is expressed in mV with a
given hold capaCitor value and input slew rate. Note that
this error term occurs even for long sample times.
5-3
o·
:::s
9.
~
...3
(II
~National
Semiconductor
Corporation
.
Sample and Hold Selection Guide
LF198A
LF398A
LF198
LF398
LF298
Units
0.01
0.01
0.02
0.02
0.02
% Max
Offset Voltage
2
3
5
10
5
mVMax
Droop Rate (25°C)
Cs == 1000pF
Cs = 10000pF
30
3
30
3
30
3
30
3
30
3
mVlsec
Acquisition Time (25°C)
Cs = 1000pF
Cs = 10000pF
4
4
4
4
4
,..s
20
20
20
20
20
Accuracy
Gain/Offset Error
Aperture Time (25°C)
25
25
25
25
25
ns
Temperature Range
-55to +125
Oto +70
-55 to +125
Oto +70
-25to +85
°C
Low Drift
Low Drift
General
Purpose
General
Purpose
Low Drift
Comment
5-4
r---------~------------------------------------------------------------__.
r
...
."
NatiOnal
~ Semiconductor
CQ
co
......
r
Corporation
."
N
CQ
co
......
r
LF198/LF298/LF398,LF198A/LF398A
."
Monolithic Sample 'and Hold Circuits
Co)
CQ
co
......
General Description
Features
The LF19B/LF29B/LF39B are monolithic sample and hold
circuits which utilize BI-FET technology to obtain ultra-high
dc accuracy with fast acquisition of signal and low droop
rate. Operating as a unity gain follower, dc gain accuracy is
0.002% typical and acquisition time is as low as 6 p.s to
0.01 %. A bipolar input stage is used to achieve low offset
voltage and wide bandwidth. Input offset adjust is accomplished with a single pin, and does not degrade input offset
drift. The wide bandwidth allows the LF19B to be included
inside the feedback loop of 1 MHz op amps without having
stability problems. Input impedance of 1010n allows high
source impedances to be used without degrading accuracy.
P-channel junction FET'sare combined with bipolar devices in
the output amplifier to give droop rates as low as 5 mVImin
with a 1 p.F hold capacitor. The JFET's have much lower
noise than MOS devices used in previous designs and do
not exhibit high temperature instabilities. The overall design
guarantees no feed-through from input to output in the hold
mode, even for input signals equal to the supply voltages.
• Operates from ± 5V to ± 1BV supplies
• Less than 10 p.s acquisition time
• TTL, PMOS, CMOS compatible logic input
• 0.5 mV typical hold step at Ch = 0.01 p.F
• Low input offset
• 0.002% gain accuracy
• Low output noise in hold mode
• Input characteristics do not change during hold mode
• High supply rejection ratio in sample or hold
• Wide bandwidth
Logic inputs on the LF19B are fully differential with low input
current, allowing direct connection to TTL, PMOS, and
CMOS. Differential threshold is l.4V. The LF19B will operate from ± 5V to ± 1BV supplies. It is available in an B-Iead
TO-5 package.
An "An version is available with tightened electrical specifications.
r
Typical Connection and Performance Curve
ID~_
iiiIii.
OUTPUT
1000
0.001
0.01
HOLD CAPACITOR I.F)
0.1
TL/H/5692-2
Connection Diagrams
Metal Can Package
LOGIC
Dual-In-Line Package
V+
I
OFFSET
ADJUST
2
LOGIC
7
LOGIC
REFERENCE
INPUT
OUTPUT
VTOP VIEW
TOP VIEW
Order Number LF398N or LF398AN
See NS Package Number N08E
Order Number LF198H, LF298H,
LF398H, LF198AH or LF398AH
See NS Package Number H08C
5-5
TL/H/5692-11
...
."
CQ
co
»
......
r
."
Co)
CQ
;
~
en
C')
LL.
...J
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
......
~
en
.,...
Supply Voltage
LL.
...J
Power Dissipation (Package Limitation) (Note 1)
......
co
en
C')
LF298
co
en
LF398/LF398A
C\I
LL.
...J
Output Short Circuit Duration
500mW
- 55'C to + 125'C
Indefinite
Hold Capacitor Short Circuit Duration
10sec
Lead Temperature (Soldering, 10 seconds)
260'C
Thermal Resistance (/lJA) (typicals)
-25'Cto +85'C
H package
215'C/W (Board mount in still air)
N package
115'C/W
O'Cto +70'C
Storage Temperature Range
+7V, -30V
(Note 2)
±18V
LF198/LF198A
Equal to Supply Voltage
Logic To Logic Reference Differential Voltage
Operating Ambient Temperature Range
LL.
...J
......
Input Voltage
85'C/W (Board mount in 400LF/min air flow)
-65'C to + 150'C
......
/I JC (typical) 20'C/W
co
en
.,...
LL.
...J
Electrical Characteristics (Note 3)
Parameter
LF198/LF298
Conditions
Min
LF398
Typ
Max
Min
Units
Typ
Max
Input Offset Voltage, (Note 6)
Tj = 25'C
Full Temperature Range
1
3
5
2
7
10
mV
mV
Input Bias Current, (Note 6)
Ti = 25'C
Full Temperature Range
5
25
75
10
50
100
nA
nA
Input Impedance
Tj
Gain Error
Tj = 25'C, RL = 10k
Full Temperature Range
Feedthrough Attenuation Ratio
at 1 kHz
Tj
Output Impedance
Tj = 25'C, "HOLD" mode
Full Temperature Range
"HOLD" Step, (Note 4)
Tj
Supply Current, (Note 6)
Tj:<:25'C
Logic and Logic Reference Input
Current
Tj
Leakage Current into Hold
Capacitor (Note 6)
Tj = 25'C, (Note 5)
Hold Mode
Acquisition Time to 0.1 %
~VOUT
Hold Capacitor Charging Current
VIN-VOUT
Supply Voltage Rejection Ratio
VOUT
Differential Logic Threshold
Tj
=
=
=
=
=
1010
25'C
25'C, Ch
25'C, Ch
=
=
0.002
86
0.01 p.F
0.01 p.F, VOUT
=
0
25'C
=
=
10V, Ch
Ch
=
=
=
0.005
0.02
96
0.004
80
dB
0.5
4
6
n
n
0.5
2.0
1.0
2.5
mV
4.5
5.5
4.5
6.5
mA
2
10
2
10
p.A
30
100
30
200
pA
0
80
110
25'C
0.8
1.4
5-6
90
%
%
2
4
5
2V
0.01
0.02
0.5
4
20
1000 pF
0.01 p.F
n
1010
2.4
4
20
p.s
p.s
5
mA
80
110
dB
0.8
1.4
2.4
V
r-
...."T1co
Electrical Characteristics (Continued) (Note 3)
Parameter
Min
Input Offset Voltage, (Note 6)
Tj = 25°C
Full Temperature Range
Input Bias Current, (Note 6)
Tj = 25°C
Full Temperature Range
Input Impedance
Tj
=
LF398A
LF198A
Conditions
Typ
Min
Max
Units
Typ
Max
2
2
3
mV
mV
10
25
50
nA
nA
2
25
75
.n
1010
1010
25°C
Feedthrough Attenuation Ratio
at 1 kHz
Tj = 25°C, Ch = 0.01 ,...F
Output Impedance
Tj = 25°C, "HOLD" mode
Full Temperature Range
0.5
"HOLD" Step, (Note 4)
Tj = 25°C, Ch = 0.01,...F, VOUT = 0
0.5
Supply Current, (Note 6)
Tj;;"25°C
Logic and Logic Reference Input
Current
0.002
86
0.005
0.01
0.004
96
86
0.005
0.01
90
%
%
dB
1
6
n
n
4.5
6.5
mA
10
2
10
,...A
30
100
30
100
pA
4
20
6
25
4
20
6
25
,...s
,...s
4.5
5.5
Tj = 25°C
2
Leakage Current into Hold
Capacitor (Note 6)
Tj = 25'C. (Note 5)
Hold Mode
Acquisition Time to 0.1 %
aVOUT = 10V, Ch = 1000 pF
Ch = 0.Q1 ,...F
1.0
5
Hold Capacitor Charging Current
VIN-VOUT = 2V
Supply Voltage Rejection Ratio
VOUT = 0
90
110
Differential Logic Threshold
Tj = 25'C
0.8
1.4
2.4
mV
5
mA
90
110
dB
0.8
1.4
2.4
V
Note 1: The maximum iunctlon temperature olthe LF19B/LF198A is 150"C. for the LF29B. 115·C. and for the LF39B/LF39BA. 100"C. When operating at elevated
ambient temperature•. the power dissipation must be derated based on a thermal resistance (ejAl of 150"C/W.
Note 2: Although the differential voltage may not exceed the limits given. the common-mode voltage on the logic pins may be equal to the supply voltages without
causing damage to the circuit. For proper logiC operation, however, one of the logic pins must always be at least 2V below the positive supply and 3V above the
negative supply.
Note 3: Unless otherwise specified. the following conditions apply. Unit is in "sample" mode. Vs = ± 15V. Tj = 25·C. -11.5V ,; VIN ,; + 11.5V.Ch = 0.01 "F.
and RL = 10 kn. Logic reference voltage = OV and logic voltage = 2.5V.
Note 4: Hold step is sensitive to stray capaCitive coupling between input logiC signals and the hold capacitor. 1 pF, for instance, will create an additional 0.5 mV
step with a 5V logic swing and a O.o1"F hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value.
Note 5: Leakage current is measured at a junction temperature of 2SD C. The effects of junction temperature rise due to power dissipation or elevated ambient can
be calculated by doubling the 25'C value for each 11'C increase in chip temperature. Leakage is guaranteed over full input signal range.
+ 3.5V ~ VIN :s:: + Vs -
Note 6: These parameters guaranteed over a supply voltage range of ± 5 to ± 18V, and an input range of -Vs
3.5V.
Typical Performance Characteristics
Dielectric Absorption
Error in Hold Capacitor
Aperture Time-
NEGATIVE
;;:
25 O~
200
INPUT STEP
~
10
'".......
O~
0
25
~
a...
z
....
.... POSITIVE
INPUT STEP
50
75 100 125 150
JUNCTION TEMPERATURE I'CI
~
g
I--'
0
-50 -25
10
V
I I
I I
10
::!
.........
./
150
100
100
500
45 o v+ '" v-" 15V
:g
co
OCI
.......
r-
...."T1
OCI
l>
.......
r"T1
Cto)
CO
0.5
I
"T1
OCI
1
4
I
co
OCI
.......
r-
CO
Tj = 25°C, RL = 10k
Full Temperature Range
30 0,---
"T1
N
Cto)
5
Gain Error
400 I1VOUT ~1 mV
AVIN" 1DV
350
OCI
.......
r-
0.1 L-LJ.L.I.lJIIIL..-'-.L.I..I,wo---,....u..ww 0.1
100
10
0.1
SAMPLE TIME (m,1
·See Definition of Terms
;;
.!
'"
~
'1
ffi
-10
0.1
10
100
1000
INPUT SLEW RATE (V/ms)
TUH/5692-3
5-7
l>
Typical Performance Characteristics (Continued)
Output Droop Rate
Hold Step
100
"Hold" Settling Time·
100
_,f-v--nv
1.1
10
1.4
1.2
...-'"
;;
oS
L
i....
In
~
'"
I- SETTLING TO 1 mV
1.&
1
0.1
.... ""
i""'"
0••
0.&
-I"""
0.4
D.2
10-4
100 pF' 1000 pF
O.OM
1000 pF
O.M
Leakage Current Into Hold
Capacitor
100
O.OM
•
O.I.F
-51 -25 0
HOLO CAPACITOR
HOLD CAPACITOR
Phase and Gain (Input to
Output, Small Signal)
5
10
-5
&0
....
co
50
~
VS"'±15V
70
~
VOUT' 0
HOLO MOOE
10
'"S
~
co -10
co
....
/
40
S
!ir
3D
..
~
25
50
lk
75 100 125 150
10k
JUNCTION TEMPERATURE rc)
140
120
100
80
&0
40
20
!r.z;~C_15V
VOUT=OV
1
POSITIVE
I
~UPPLV
NEGATIVE
SUPPLY
r-::
lk
10k
lOOk
~ -0.8
!! -I
..,...,..1
~
r--..
If""-.
SINKING
-0.6
25 50
......
az
MODE
10
&0
i'
40
SAMPLE
li~fI~1
20
a
75 100 125 150
10
lDO
HtlHfttt-ttiIHH-t V,N -10 Vp·p
'"
~
......
-10
-15
75 100 125 150
-80
V7." 0
Tj=25"C
~~tu!l1ltlrd
~~~=~",**",*:$~llI-l
f-ttH-tttt-+tttHHtHtttt-Hflt-I
-&0 f-ttH-tttt-+t-Hl-"HtHtttt-H1lH
-50 L.J..IJII....L.J..UI..J...J.J.Il.."-.J..UL...u.UI....L-WI.J
1
10 100 1k
10k lOOk 1M
FREQUENCV (Hz)
llJ11k
Hold Step vs Input Voltage
e
w
I
~
2
1.1
1.6
1.4 ~
1.2
~ i"..!T' .ioo"c r---- -
_Tj'25''c'--
co
~
~
Q
-10
lk
FREQUENCY (Hz)
Feedthrough Rejection Ratio
(Hold Mode)
......
15
IJ
100
JUNCTION TEMPERATURE I"C)
a; -100
co -90
10
Output Noise
I I
-50 -25 0
1M
-5
-Ii -10
I ""t-
-110
50
>
~w
-120
25
~
t-.
120
15
a
::;
...\::
-
...... b.
-0.2
~
20
JUNCTION TEMPERATURE rC)
.1,
...
0
140
rnll"'T'T11T"Tlnril"TT-v7'+=~V~-~-~'5-V'"
-50 -25
~
SAMPLE MODE
INPUT VOLTAGE IV)
-130
-5
0.2
10
SOURCING
10
Input Bias Current
...... 1"'-.
~
I I
25
r---.
0.4
S
~ -11.4
I I
I I
12
FREQUENCY IH.)
10
~
~
.
RL -'Ok
0.&
180
1&
14
o
100
~
co
:!
Tj • 25"C
0.'
~
Output Short Circuit Current
20
18
•
~
FREQUENCY IH.)
Power Supply Rejection
1&0
50 75 lDO 125 150
Gain Error
;;
oS
li:
0
10M
1M
lOOk
iii;
20
Ck=O
10-2
-50 -25 0
25
JUNCTION TEMPERATURE I"C)
·See definition
~
!.
D••
0.6
0.4
0.2
I""'-+..
-
I"'-..
......... ::-...
Tj =-55"C
1--1
1
...
~
o
-15 -10
-5
10
15
INPUT VOLTAGE (V)
TLlH/5692-4
5-8
Typical Performance Characteristics (Continued)
Output Transient at Start
of Sample Mode
I'
I
D~
0
~
-0. 2
,
-0. 4
of Hold Mode
1\
D.6
D. 4
~
Output Transient at Start
60
40
,\
ll/
!
~
",,=D.DDlp'
~
1/\
D. 4
~oI- II.....
\ .(IAUi RArr'r-t--
-0.2
o
II-'
-20
-60
RAJ[ > 3kH, I
o
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
TINE (ps)
.F
V
-40
=D.Dlpf
I~SAIIPL£
20
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
TL/H/5692-12
TIME
(I's)
TL/H/5692-13
Logic Input Configurations
TTL & CMOS
3V ~ VL (HI State) ~ 7V
Y'
RI'
n
..J
Threshold
~
2.BV
HOLO
R2
LSAMPLE
I.4V
Uk
Threshold
~
1.4V
'Select for 2.BV at pin B
CMOS
7V ~ VL (HI State) ~ 15V
v'
y'
2Dk
3Dk
n
HDLD
..J
Threshold ~ 0.6 (V+)
+
I.4V
2Dk
LSAMPLE
Threshold
~
0.6 (V+) - I.4V
II
Op Amp Drive
+IJ~
D
:MPLE
Uk
+IJYj{0LO
':' B.n
-_Nl,.......-..
_13 J-LHOLO
SAMPLE
-13V
Threshold ::::
4.1k
+ 4V
Threshold
5-9
~
-4V
TUH/5692-6
i
Application Hints
II.
....I
Hold Capacitor
~
Hold step, acquisition time, and droop rate are the major
trade-offs in the selection of a hold capacitor value. Size
and cost may also become important for larger values. Use
of the curves included with this data sheet should be helpful
in selecting a reasonable value of capacitance. Keep in
mind that for fast repetition rates or tracking fast signals, the
capacitor drive currents may cause a significant temperature rise in the LF198.
....
c»
,..
~
....
co
c»
5'"co
gt
II.
....I
....
co
c»
,..
II.
....I
tor on the chip. This means that at the moment the "hold"
command arrives, the hold capacitor voltage may be somewhat different than the actual analog input. The effect of
these delays is opposite to the effect created by delays in
the logic which switches the circuit from sample to hold. For
example, consider an analog input of 20 Vp-p at 10kHz.
Maximum dV/dt is 0.6 V/",s. With no analog phase delay
and 100 ns logic delay, one could expect up to (0.1 ",s)
(0.6V/",s) = 60 mV error if the "hold" signal arrived near
maximum dV/dt of the input. A positive-going input would
give a + 60 mV error. Now assume a 1 MHz (3 dB) bandwidth for the overall analog loop. This generates a phase
delay of 160 ns. If the hold capaCitor sees this exact delay,
then error due to analog delay will be (0.16 ",s) (0.6 VI ",s)
= -96 mY. Total output error is +60 mV (digital) -96 mV
(analog) for a total of -36 mY. To add to the confusion,
analog delay is proportioned to hold capaCitor value while
digital delay remains constant. A family of curves (dynamic
sampling error) is included to help estimate errors.
A curve labeled Aperture Time has been included for sampling conditions where the input is steady during the sampling period, but may experience a sudden change nearly
coincident with the "hold" command. This curve is based on
a 1 mV error fed into the output.
A second curve, Hold Settling Time indicates the time required for the output to settle to 1 mV after the "hold" command.
A significant source of error in an accurate sample and hold
circuit is dielectric absorption in the hold capacitor. A mylar
cap, for instance, may "sag back" up to 0.2% after a quick
change in voltage. A long "soak" time is required before the
circuit can be put back into the hold mode with this type of
capacitor. Dielectrics with very low hysteresis are polystyrene, polypropylene, and Teflon. Other types such as mica
and polycarbonate are not nearly as good. Ceramic is unusable with> 1% hysteresis. The advantage of polypropylene
over polystyrene is that it extends the maximum ambient
temperature from 85·C to 100·C. "NPO" or "COG" capacitors are now available for 125·C operation and also have
low dielectric absorption. For more exact data, see the
curve Dielectric Absorption Error. The hysteresis numbers
on the curve are final values, taken after full relaxation. The
hysteresis error can be significantly reduced if the output of
the LF198 is digitized quickly after the hold mode is initiated.
The hysteresis relaxation time constant in polypropylene, for
instance, is 10-50 ms. If A-to-D conversion can be made
within 1 ms, hysteresis error will be reduced by a factor of
ten.
Digital Feedthrough
Fast rise time logic signals can cause hold errors by feeding
externally into the analog input at the same time the amplifier is put into the hold mode. To minimize this problem,
board layout should keep logic lines as far as possible from
the analog input. Grounded guarding traces may also be
used around the input line, especially if it is driven from a
high impedance source. Reducing high amplitude logic signals to 2.5V will also help.
DC and AC Zeroing
DC zeroing is accomplished by connecting the offset adjust
pin to the wiper of a 1 kn potentiometer which has one end
tied to V + and the other end tied through a resistor to
ground. The resistor should be selected to give "" 0.6 mA
through the 1k potentiometer.
AC zeroing (hold step zeroing) can be obtained by adding
an inverter with the adjustment pot tied input to output. A
10 pF capacitor from the wiper to the hold capaCitor will give
±4 mV hold step adjustment with a 0.01 ",F hold capaCitor
and 5V logic supply. For larger logic swings, a smaller capaCitor « 10 pF) may be used.
Guarding Technique
v'
Logic Rise Time
For proper operation, logic signals into the LF198 must have
a minimum dV/dt of 1.0 V/",s. Slower Signals will cause
excessive hold step. If a RIC network is used in front of the
logic input for signal delay, calculate the slope of the waveform at the threshold point to ensure that it is at least
1.0 V/",s.
Sampling Dynamic Signals
Sample error to moving input signals probably causes more
confusion among sample-and-hold users than any other parameter. The primary reason for this is that many users
make the assumption that the sample and hold amplifier is
truly locked on to the input Signal while in the sample mode.
In actuality, there are finite phase delays through the circuit
creating an input-output differential for fast moving signals.
In addition, although the output may have settled, the hold
capacitor has an additional lag due to the 300n series resis-
BonOM VIEW
TL/H/5692-5
Use 10-pin layout. Guard around Ch is tied to output.
5-10
r
....'TI
Functional Diagram
CD
.....
r
0)
'TI
OFFSET
,,
,
,,I
,,I
N
-------------,
Z
,
INPUT
3
+
,
LOGlcn>'
LOGIC
REFERENCE
1
71
/'
300
_./
CD
.....
r
0)
'TI
to)
CD
.....
r
0)
OUTPUT
....
'TI
CD
0)
»
.....
r
'TI
to)
CD
0)
»
I
1.. _ _ _ _ _ _ _ _ _ _
_ _ _ _ .....J
6
HOLD
CAPACITOR
TL/H/5692-1
Typical Applications (Continued)
X1000 Sample & Hold
Sample and Difference Circuit
(Output Follows Input in Hold Mode)
Your
OFF1::~
If' ' -'\,~I\,~fIr' ' ' ' ': . j
ADJUST~
O.OlJ.1F
Y,N
VOUT
-15V
~
......W\r-+--_.......
r-t
.J
VOUT = Va
Y,N
':"
'For lower gains, the LM10B must be frequency compensated
100
Use '" Av pF from camp 2 to ground
5-11
RESET
L.TRACK
+ il.V,N(HOLD MODE)
TLlH/5692-7
~
en
C")
u.
Typical Applications
....I
:;c
CD
(Continued)
Ramp Generator with Variable Reset Level
15V
en
.....
u.
v+
Rl
B.n
-ISV
....I
Dl
LM113
1.2V
CO
~
RESET
LEVEL
INPUT
U.
....I
......
CD
en
~
Integrator with Programmable Reset Level
RESET
lEVEL
INPUT
>:""'-I--.4j....oOOUTPUT
OUTPUT
R2
200 •
1%
RESET
Sv-n
Ov-J L...
....I
......
RAMP
CD
en
.....
Rl
1M
1%
DIFFERENTIAL [
INTEGRATING
u.
INPUT
....I
O-.JV'wI'll--+-----=-i
HJ
1M
1%
H4
200k
1%
Output Holds at Average of Sampled Input
Increased Slew Current
V+
OUTPUT
D2
ChT'N4S7
Reset Stabilized Amplifier (Gain of 1000)
"
1%
Fast Acquisition, Low Droop Sample & Hold
1M
ISV
ISV
1%
OUTPUT
INPUT
OUTPUT
-ISV
INPUT
-J 1....rL
":'
'0
SAMPLE
.'
SV TO 15V
SV-n
OV~
--I
r--
RESET PULSE
~lms
Vos ,;; 20",V (No trim)
Z,N""
-J
L...
Mfi
A~~s '" 30",V Isec
I-'
6
o.OM
AVos", 0 ,,,,VI'e
AT
.
T
I-
J.Jk
1.2M
Uk
12m,
s-L
LMJ90S
TIMER
":'
":'
TL/H/5692-B
5-12
r-
."
.....
co
......
Typical Applications
(Continued)
Synchronous Correlator for Recovering
Signals Below Noise Level
co
r-
2-Channel Switch
I&V
~
co
15V
co
......
OUTPUT FREQUENCY
r-
SET BY SWEEP RATE
."
~---J~~--~-oo~
.A
.. -V:it...
SIIGNAL
'\INPUT
Co)
co
co
"A" INPUT
......
r-
."
.....
co
"A" SELECT
5V-n
OV.....J
;......
~
"S" SELECT
r-
"B"INPUT
A
B
Gain
± 0.02% 1 ± 0.2%
10100.
47ko.
liN
BW
"" 1 MHz "" 400 kHz
-90dB
Crosstalk -90 dB
@ 1 kHz
:O::6mV
:0:: 75mV
Offset
RZ
1M
R5
12k
LMI22H
TIMER
LMI22H
TIMER
R6
4.7k
20k
5 10
C2**
R4
&00
4
C3
470,F
6
5 10
co
):0
NC
'Select C1 to filter lowest Irequency
TO SCOPE SWEEP
OUTPUT. SCALE R3
component of input noise
TO OBTAIN"", 0 TO 3V
AT PIN 6.
"Select C2
@ '"
5 x 10-6/1IN
DC & AC Zeroing
DC
VOS
ZERO
~
co
Staircase Generator
15V
15V
RESET
:~::rL
RI
....-o OUTPUT
~..;;...--~------
4.7k
OJ
LMI13
CLOCK
5V-1'I 1'1
ov-l W
1.2V
R6*
5Dk
LR5
11k
T
C2
3DDpF
R4
15V
S.2k
I
R8
12k
"'J\J""~"""OI5V
02
IN914
TLlH/5692-9
'Select lor step height
50k --> '" 1V Step
5-13
Typical Applications (Continued)
Differential Hold
Capacitor Hysteresis Compensation
v'
INPUT
>':.....-.....0
OUTPUT
Rl
Ch
LOGIC
ZOOk
RZ
200k
·Select for time constant Cl = 1;Ok
"Adjust for amplHude
TL/H/5692-10
Definition of Terms
Hold Step: The voltage step at the output of the sample
and hold when switching from sample mode to hold mode
with a steady (dc) analog input voltage. Logic swing is 5V.
Hold Settling Time: The time required for the output to
settle within 1 mV of final value after the "hold" logic command.
Dynamic Sampling Error: The error introduced into the
held output due to a changing analog input at,the time the
hold command is given. Error is expressed in mV with a
given hold capacitor value and input slew rate. Note that
this error term occurs even for long sample times.
Aperture Time: The delay required between "Hold" command and an input analog transition, so that the transition
does not affect the held output.
Acquisition Time: The time required to acquire a new analog input voltage with an output step of 10V. Note that acquisition time is not just the time required for the output to
settle, but also includes the time required for all internal
nodes to settle so that the output assumes the proper value
when switched to the hold mode.
Gain Error: The ratio of output voltage Swing to input voltage swing in the sample mode expressed as a per cent
difference.
5-14
r-----------------------------------------------------------------------~
r
.....
."
~ Semiconductor
NatiOnal
PRELIMINARY
Corporation
Co)
o
o
CD
......
r
."
.....
LF13006/LF13007 Digital Gain Set
Co)
oo
.....
General Description
The LF13006 and LF13007 are preCision digital gain sets
used for accurately setting non-inverting op amp gains.
Gains are set with a 3-bit digital word which can be latched
in with WR and CS pins. All digital inputs are TTL and CMOS
compatible.
The LF13006 shown below will set binary scaled gains of 1,
2, 4, B, 16, 32, 64, and 12B. The LF13007 will set gains of 1,
2,5,10,20,50, and 100 (a common attenuator sequence).
In addition, both versions have several taps and two uncommitted matching resistors that allow customization of the
gain.
The gains are set with precision thin film resistors. The low
temperature coefficient of the thin film resistors and their
excellent tracking result in gain ratios which are virtually independent of temperature.
The LF13006, LF13007 used in conjunction with an amplifier not only satisfies the need for a digitally programmable
amplifier in microprocessor based systems, but is also useful for discrete applications, eliminating the need to find
0.5% resistors in the ratio of 100 to 1 which track each
other over temperature.
Features
•
•
•
•
•
•
Block Diagram and Typical Application
TTL and CMOS compatible logic levels
Microprocessor compatible
Gain error 0.5% max
Binary or scope knob gains
Wide supply range + 5V to ± 1BV
Packaged in 16-pin DIP
(LF13006)
LFl3G06
~--------------~En
r-----+- 80u.
AOUT
OIGIN
2
OIGIN
LSB '.
OAJA BUS
CONTROL
Vou.
LINES
Tl/H/5114-1
Note: R'" 15 kll
Order Number LF13006N or LF13007N
See NS Package Number N16A
5-15
.....
Q
Q
....u..
C")
..J
.....
CD
Q
Q
....
C")
u..
..J
Absolute Maximum Ratings
Operating Ratings (Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, V + to V36V
Lead Temp. (Soldering, 10 seconds)
Supply Voltage, V+ to GND
Voltage at Any Digital Input
Analog Voltage
-40·Cto +85·C
260·C
Operating Temperature Range
25V
V+ toGND
V+ to (V- + 2V)
Electrical Characteristics
Parameter
(Note 2)
Conditions
Typ
(Note 3)
Tested
Limit
(Note 4)
Design
Limit
(Note 5)
Units
0.5
0.5
% (max)
Gain Error
AOUT= ±10V
ANAGND=OV
IINPUT<10 nA
0.3
Gain Temperature Coefficient
AoUT= ±10V
ANAGND=OV
0.001
Digital Input Voltage
Low
High
%rC
1.4
1.6
0.8
2.0
0.8
2.0
V(max)
V(min)
-38
0.0001
-100
1
/-tA(max)
/-tA(max)
5
-5
-100
1
5
-5
Digital Input Current
Low
High
VIL =OV
VIH=5V
Positive Power Supply Current
All Logic Inputs Low
2
Negative Power Supply Current
All Logic Inputs Low
-1.7
Write Pulse Width, tw
VIL =OV, VIH=5V
40
100
ns(min)
Chip Select Set-Up Time, tcs
VIL =OV, VIH=5V
60
120
ns(min)
Chip Select Hold Time, tCH
VIL =OV, VIH=5V
0
ns(min)
DIG IN Set-Up Time, tos
VIL =OV, VIH=5V
80
0
150
DIG IN Hold Time, tOH
VIL =OV, VIH=5V
0
0
Switching Time for Gain Change
(Note 4)
mA(max)
mA(max)
ns(min)
ns(min)
200
ns(max)
Switch On Resistance
3
Unit Resistance, R
15
12-18
0.3
0.5
Rl and R2 Mismatch
Rl IR2 Temperature Coefficient
kn
kn
% (max)
0.5
%rC
0.001
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: Parameters are specified at V+ = ISV and V- = -ISV. Min V+ to ground voltage is SV.
operating temperature ranges. All other numbers apply at TA = Ti = 2S'C.
Note 3: Typicals Bre at 25°C and represent most likely parametric norm.
Min V+ to V- voltage is SV. Boldface number. apply over full
Note 4: Guaranteed and 100% production tested.
Note 5: Guaranteed (but not 100% production tested) over the operating temparature. Thesa limits ara not used to calculate outgoing quality levals.
Note 6: Settling time for gain change is the switching time for gain change plus settling tima (see section on Settling Time).
Note 7: WR minimum high threshold voltage increases to 2.4V undar the extreme conditions when all thrae digital inputs are simultaneously taken from OV to SVat
a slew rata of greater than SOOVlI'S.
Connection Diagram
Dual·ln·Line Package
GAIN TABLE
Gain
Digital Input
LF13006
DIG In 1
DIGln2
DIGin3
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AOUT
1
2
4
8
16
32
64
128
BOUT
1
1.25
2.5
5
10
20
40
80
DlGGND- 1
LF13007
AOUT
1
1.25
2
5
10
20
50
100
BOUT
1
1
1.6
4
8
16
40
80
5·16
V
16 -
ANAGND
INPUT- 2
15-R2
V-- 3
14-Rc
V'-4
13-R1
EXT- 5
12-AOUT
BOUT- 6
Wii-
11-Cs'
7
10 -DlOIN3
DIGIN1- B
9TDPVIEW
DIOIN2
TLlH/5114-2
.-----------------------------------------------------------------------------'r
-n
......
Switching Waveforms
Co)
o
o
C»
......
r
-n
......
Co)
o
V,H
o
.....
CS
VIH
Viii
50%
V,l
DATA BITS
VIH~
.-~
tDS
50%
V,l
TL/H/5114-3
Block Diagram and Typical Application
(Continued) (LF13007)
rT- -=r:- -l- _Rf_ -i- -YI
r
~
r
LF13007
--,
...---------......-EXT
r------......
BOUT
DECODE
I
-1- - -I-
L
DIG IN
MSB 3
DIG IN
2
DIG IN
Wil
f!
lSB 1
DATA BUS
CONTROL
LINES
TL/H/5114-4
Note: R '" 15 kfl
5-17
~
..-
Typical Performance Characteristics
LL.
Positive Power Supply
Current vs Temperature
-I
.....
CD
~
..-
LL.
-I
I-'IM-+-+-+-+-+-I--l
5.0
!
Negative Power Supply
Digital Input Threshold vs
Temperature
o Current vs Temperature
-1.0
<-2.0
4.0
~ 3.0 """t-':Hrlrl""'ld-t-l
...~~-3.0
"'G
G-4.0
2.0
1.0
VS-+5V
I
~
E
Vs- ±lOV .... ~ -Vs=±15V
..... ,.,..
..... ~
~
'"
ill'"i=
...
!a
Q
-15
25
65
105
TEMPERATURE ('C)
-55
Logical 0 Input Bias Current
vs Temperature
2.4
~
~
...ili
50
...'"
a:
a:
..,
40
~
30
III'"
......'"
...
1.6
I
r-- 1
!;
20
10
-55
0.4
o
-15
25
65
TEMPERATURE ('C)
o
105
-55
105
o
C
I
..... ....
..... ~ i--'"
..... ~
~
!;
j 200
I;
10
15
SUPPLY VOLTAGE (V)
~ 400
~
~
100
o
. . ~tr
Vs-±loV
-55
~
Vs
~
300
-55
..l.
I
-15
25
65
TEMPERATURE ('C)
..... ~
...
Vs= ±5V ~ .....
I~ 100
~OV
;::
-
~ 200
±2oV
-15
25
65
TEMPERATURE ('C)
....
~vttr
~
.... ~ ....
....
~
Vs= ±5V ~
100
j....-
Chip Select Set-Up Time, tcs
~ 400
~ 200
105
Vs= ±5V.... ~
Vs= ±15V
Vs'= ±2o~\
o r-
20
500
300
300
:r
Data Set-Up Time, tos
...=i'~
-15
25
65
TEMPERATURE ('C)
400
~
500
...
L-
Write Width, tw
.
--
T
0.8
~
!;
~
-55'C ~
1.2 -i5'C
'"
-
500
I
I
_ 2.0
60
:>
-15
25
65
TEMPERATURE ('C)
Digital Input Threshold vs
Supply Voltage
7o~~~-r-r-r-r'-~
-
Vs=±15V
0.5
o tljt::!::j±~E3
-55
....
1.5
1!
1'1'
-5.0
2.5
~
o
-55
105
"'"
vSi ±1 5v
Vs- +20V
-15
25
65
105
TEMPERATURE ('C)
TL/H/5114-5
5-18
105
r-
"T1
......
Application Information
(,,)
use of a lead capacitor from the inverting input to the output
of the amplifier. A lead capacitor is effective whenever the
feedback around an amplifier is resistive, whether with discrete resistors or with the LF13006/7. It compensates for
the feedback pole created by the parallel resistance and
capacitance from the inverting input of the op amp to AC
ground.
Settling Time Test Circuit
FLOW-THROUGH OPERATION
THE LF13006, LF13007 can be opera1ed with control lines
CS and WR grounded. In this mode new data on the digital
inputs will immediately set the new gain value. Input data
cannot be latched in this mode.
INPUT CURRENT
Current flowing through the input (pin 2) due to bias current
of the op amp will result in a gain error due to switch impedance. Normally this error is very small. For example, 10 nA
of bias current flowing through 3 kfl of switch resistance will
result in an error of 30 p.V at the summing node. However,
applications that have significant current flowing through the
input must take this effect into account.
LF13DD6
r---~
L _ _ .:..J
SETTLING TIME
Settling time is a function of the particular op amp used with
the LF13006/7 and the gain that is selected. It can be optimized and stability problems can be prevented through the
lD/6AIN:r
o
DUT
IN
TLlH/5114-6
Typical Settling Time Curves
~
:;;
:g,
1k
100
3:
:=~w
:1
lk
6-64
6 32
6 16
--
:E
6
;:::
'"z
1
~
o
6~
~
~
w
s*I-"T~
6 4* 6 1
S 10 12
LEAD CAPACITDR IpF)
~ i::::::==
10
:E
6 2*
6 4*-6 1
S*
F=F=F6
;:::
'"
i
14
100
~
<>
J....-:::
lk
~
""
~'"
~
~ i.--
10
w
In
6 64
6 32
6=16 l'--,
""E lDD
612s
~
WITH LF351
~
~
;
~
WITH LF156
1
4
D
6
S
10
12
14
LEAD CAPACITDR (pF)
;:!
:=w
10
:E
;:::
'"z
~
S
'"
lD
12
14
LEAD CAPACITDR (pF)
TL/H/5114-7
'II
Unstable at CL less than 2 pF
Typical Applications
Variable Time Constant Filter
Variable Capacitance Multiplier
.
Ceffective = C1(gain set #)
Time constant =
Note: Output swing at input op amp
R
N
C1
N = setting of LF13006
is multiplied by set gain. Signal
VIN
range may be limited.
(range
IN
1
= 126 to 1)
12
AOUT
12
ADUT
15
LF13D06
LF13DD7
DIGITAL
CDNTRDL
14
2 INPUT
'::'
14
13
Cl
ANA
6ND
16
ANA
6ND
+-DI6ITAL
CDNTRDL
16
SUFFERED
FILTERED ~~~=':':'!'C
DUTPUT
1/2 LF412
DUAL Op·AMP
'::'
TLlH/5114-9
TL/H/5114-B
5-19
CI
CI
Q)
......
r-
"T1
......
(,,)
CI
CI
.....
Typical Applications
(Continued)
Switchable Gain of ± 1
Programmable Current Source
DIGITAL
IN
15V
+
30k
12
15
lF13006
Aou,
lF13006
lF13007
YOUT
DIGITAL ........
CONTROL....,.
lM385·1.2Y
INPUT
Tl/H/5114-11
Note: Digital
Digital
code~OOO, VOUT~VIN;
cod9~OOI, VOUT~
-VIN
Programmable Differential Amp
TLlH/5114-10
1OUT
~
DIGITAL
~
1.2V [
1
]
1200 gain sel #
Inverting Gains
-IN
lF13006
lF13DD7
ANA
16 GND
Aou, 12
DIGITAL
CONTROL
+
INPUT
2
+IN
lF13006
lF13007
12 13
16
ANA
GND
14
lF130D6
lF13DD7
15
DIGITAL
IN
Vou,
....
INPUT
2~IA
lInu,
+
TLlH/5114-12
Inverting gain with high input im·
AOUT
_ 12
pedance can be obtained with the
LF13006, LF13007 by using the two
TLlH/5114-13
on·board resistors and a dual op
amp as shown.
Note 1: Actual gain = set gain-1
since LF13006s afe in
"inverting mode".
Note 2: Set gain must be
same on both LF1300Ss.
5·20
Typical Applications
Altered Gain Range
IN
r-n
w
c
c
Q)
....
(Continued)
One Octave per Bit Function Generator
Variable Gains of Almost 1
.....
r-
....-nw
OUT
1216
AOUT
c
c
......
16
ANA
GND
I
BOUT
15
15
12
LF13006
LF13006
AOUT
':'
':'
2 INPUT
2 INPUT
LF13006
INPUT 2
13
OIGITAL
CONTROL
13
OIGlTAL'"
CONTROL
ANA
GNO
16
AOUT
12
ANA
GNO
16
TL/H/5114-14
TLlH/5114-16
10k
10k
TRIANGLE
WAVE
OUTPUT
TLlH/5114-15
GAINS
9
GAINS
AOUT
BOUT
1
1
1.8
3
4.5
1.2
1.8
1.29
1.125
1.059
1.029
1.014
1.007
2
3
4
4.8
5.33
5.65
6
7.2
8
8.47
Programmable Instrumentation Amp
Attenuator (0 dB to -42 dB in 6 dB steps)
INPUT
12
AoUT
10k
LF13006
ANA
16 GND
LF13006
LF13007
ADUT
12
10k
OUTPUT
tOk
ANA
GHD
16
TL/H/5114-17
Note 1: VOUT~N (A-B),
N~set
gain.
TLlH/5114-16
Note 2: All 10k resistors 0.1 % matched.
5-21
~National
~ Semiconductor
LH0023/LH0023C/LH0043/LH0043C Sample
and Hold Circuits
General Description
Features
The LH0023/LH0023C and LH0043/LH0043C are complete sample and hold circuits including input buffer amplifier, FET output amplifier, analog signal sampling gate, TTL
compatible logic circuitry and level shifting. They are designed to operate from standard ± lSV DC supplies, but
provision is made on the LH0023/LH0023C for connection
of a separate + SV logic supply in minimum noise applications. The principal difference between the LH00231
LH0023C and the LH0043/LH0043C is a 10:1 trade-off in
performance between sample accuracy and sample acquisition time. Devices are pin compatible except for TTL logic
polarity.
LH0023/LH0023C
• Sample accuracy-O.Ol % max
• Hold drift rate-O.S mVIsec typ
• Sample acquisition time-l00 "'S max for 20V
• Aperture time-1S0 ns typ
• Wide analog input range- ± 10V min
• Logic input-TTL/DTL compatible
• Offset adjustable to zero with single 10k pot
• Output short circuit proof
The LH0023/LH0023C and LH0043/LH0043C are ideally
suited for a wide variety of sample and hold applications
including data acquisition, analog to digital conversion, synchronous demodulation, and automatic test setup. They offer significant cost and size reduction over equivalent module or discrete designs. Each device is available in a hermetic TO-8 package and is completely specified over both
full military and industrial temperature ranges.
The LH0023 and LH0043 are specified for operation over
the -SsoC to +12SoC military temperature range. The
LH0023C and LH0043C are specified for operation over the
- 2SoC to + 8SoC temperature range.
LH0043/LH0043C
• Sample acquisition time-1S
max for 20V
4 "'S typ for SV
• Aperture time-20 ns typ
• Hold drift rate-l mV/sec typ
• Sample accuracy-O.l % max
• Wide analog input range- ± 1OV min
• Logic input-TTLlDTL compatible
• Offset adjustable to zero with Single 10k pot
• Output short circuit protection
"'S
Connection Diagrams
LH0043/LH0043C
LH0023/LH0023C
N,C.
AIIALOG
INPUT
OUTPUT
LOGIC
INPUT
·Tie for operation •
with V+ = 15Vonly
N.C.
TOP VIEW
TOP VIEW
TUK/5693-8
TL/K/5693-1
Order Number LH0023G or
LH0023CG or LH0043G or
LH0043CG
See Package Number G12B
S-22
_
r
o
o
en
Co)
::I:
National
Semiconductor
Corporation
......
r
::I:
o
o
en
Co)
LH0053/LH0053C High Speed
Sample and Hold Amplifier
o
General Description
Features
The LH0053/LH0053C is a high speed sample and hold
circuit capable of acquiring a 20V step signal in under
5.0 J.Ls.
The device is ideally suited for a variety of high speed data
acquisition applications including analog buffer memories
for A to D conversion and synchronous demodulation.
•
•
•
•
•
•
Sample acquisition time 10 J.Ls max. for 20V signal
FET switch for preset or reset function
Sample accuracy null
Offset adjust to OV
DTLlTTL compatible FET gate
Single storage capacitor
Schematic and Connection Diagrams
FEEDBACK
Metal Can Package
STORAGE
CAPACITOR
v·
OFFSET
ADJUST
FEEDBACK
I---,
STORAGE
OUTPUT
1:NOE11E
C
U
GATE 1
TL/H/9251-2
GND
TUH/9251-1
AC Test Circuit
Acquisition Time Test Circuit
20kn.
47 kn.
SCO~~ 0+--+------.-_-_~
___________~__+
.-----i
3
47kn.
.----- --------------,
10 kn.
4'
IN
Cr
5
--------~
10kn.
o+----,!-''Mr--<--t
12'
+15VO--O
,
-15V
10'
___________ _
o---:.L!I'!.O~3
6
TL/H/9251-3
5·23
....
G)
o
o
NatiOnal
Semiconductor
:5 ~ Corporation
PRELIMINARY
LH0091 True RMS to DC Converter
General Description
Features
The LH0091, rms to dc converter generates a dc output
equal to the rms value of any input per the transfer function:
•
•
•
•
•
•
•
EOUT(DC) =
.r:
~~
EIN 2(t) dt
The device provides rms conversion to an accuracy of 0.1 %
of reading using the external trim procedure. It is possible to
trim for maximum accuracy (0.5 mV±0.05% typ) for decade
ranges i.e., 10 mV -+ 100 mY, 0.7V -+ 7V, etc.
Low cost
True rms conversion
0.5% of reading accuracy untrimmed
0.05% of reading accuracy with external trim
Minimum component count
Input voltage to ± 15V peak for Vs= ± 15V
Uncommitted amplifier for filtering, gain, or high crest
factor configuration
• Military or commercial temperature range.
Block and Connection Diagrams
Dual-In-Line Package
M
VIN
FEEDBACK A11-)
I"
I.
15
M
v+
~
(OUTI
12
OJ
OUT
"
A3-
10
FEEDBACK
9
EOUT
,.-
Dual-In-Line Package
Order Number LH00910 or LH0091CD
See Package 0160
2
I
NC
1
V-
NC
,
•
AS (+1
AS H
6
,
A2 (-I
A41-1
I'
GND
TOP VIEW
TL/H/5694-1
Simplified Schematic
CEXT
r--)~---'
r
I
I
I
O-.--'\IIIIr---o--f
15
I.
I -<)-'\M
"
'1.0- ...
....-r.:~
v+o!!--o
v-oL-o
GND~
~
~
TL/H/5694-2
Note: Dotted lines denote external connections.
5-24
r:J:
o
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Temperature Range
LH0091
LH0091C
TMIN
-55'C
-25'C
Supply Voltage
Storage Temperature Range
LH0091
LH0091C
- 65'C to + 150'C
-25'C to +85'C
±22V
Input Voltage
±15V peak
Output Short Circuit Duration
Continuous
Electrical Characteristics Vs =
Transfer Function = EO(DC) =
~~
fa
Lead Temp. (Soldering. 10 seconds)
TMAX
125'C
85'C
260'C
± 15V, T A = 25'C unless otherwise noted
EIN2(t) dt
Parameter
Conditions
Min
Typ
Max
Units
20, ±0.5
40, ±1.0
mV,%
0.5, ±0.05
1, ±0.2
ACCURACY (See Definition of Terms)
Total Unadjusted Error
50 mVrmsS:VINS:7Vrms (Figure 1)
Total Adjusted Error
50 mVrmsS:VINS:7Vrms (Figure 3)
Total Unadjusted Error vs Temperature
-25'C';;;TA';;; +70'C
Total Unadjusted Error vs Supply Voltage
mV,%
0.25, ±0.2%
mV, %rC
1
mVIV
AC PERFORMANCE
Frequency for Specified Adjusted Error
Input = 7Vrms, Sinewave (Figure 3)
Input = 0.7Vrms, Sinewave (Agure 3)
Input = 0.1 Vrms, Sinewave (Figure 3)
30
70
40
20
kHz
KHz
kHz
Frequency for 1 % Additional Error
Input = 7Vrms, Sinewave (Figure 3)
Input = 0.7Vrms, Sinewave (Figure 3)
Input = 0.1 Vrms, Sinewave (Figure 3)
100
200
75
50
kHz
kHz
kHz
Bandwidth (3 dB)
Input = 7Vrms, Sinewave (Figure 3)
Input = 0.7Vrms, Sinewave (Figure 3)
Input = 0.1 Vrms, Sinewave (Agure 3)
2
1.5
0.8
MHz
MHz
MHz
Crest Factor
Rated Adjusted Accuracy Using the High
Crest Factor Circuit (Figure 5)
5
10
INPUT CHARACTERISTICS
Input Voltage Range
For Rated Performance
Input Impedance
±0.05
4.5
±11
Vpeak
5
kn
22
rnA
1
.n
OUTPUT CHARACTERISTICS
Rated Output Voltage
RL:;;'2.5kn
10
Output Short Circuit Current
Output Impedance
V
POWER SUPPLY REQUIREMENTS
±5
Operating Range
Quiescent Current
14
Vs= ±15V
5-25
±20
V
18
rnA
o
CD
......
Op Amp Electrical Characteristics Vs =
Parameter
± 1SV, T A = 2SoC unless otherwise noted
Conditions
Vos
Input Offset Voltage
Min
Rs:S;10kO
Typ
Max
Units
1.0
10
mV
nA
los
Input Offset Current
4.0
200
18
Input Bias Current
30
SOO
RIN
Input Resistance
2.S
MO
15
160
Vlmv
±10
±1::l
V
dB
nA
AOL
Large Signal Voltage Gain
Vour= ±10V, RL~2kO
Vo
Output Voltage Swing
R=10 kO
VI
Input Voltage Range
CMRR
Common-Mode Rejection Ratio
Rs:S;10 kO
90
PSRR
Supply Voltage Rejection Ratio
Rs:S;10kO
96
dB
Isc
Output Short-Circuit Current
25
rnA
Sr
Slew Rate (Unity Gain)
0.5
V/ILs
BW
Small Signal Bandwidth
1.0
MHz
±10
V
Refer to RETS0091 D drawing for Military specifications.
Typical Performance Characteristics
Error vs Frequency
'"z0;
~
-
~
-
~
0
~
:;
Error vs Frequency
10
1=
'.7V,ms
'"0;z
~
0.1
...ffi
=
~
C·l.F
0.2
0
~
~
-=
t-
0.01
=
~I
~
.
.=
~
2Vrms
~
lk
13
~
~ il'ml
10k
lOOk
II
BASllc
CONNECTION
IIIC-Z.F
-
tl
0.1
1M
FREOUENCY IHzl
~V"
1/
"",,"""
I
"""
~
~IGHCREST
"""
-
FACTOR CIRCUIT
I
I
1
I
THISTESTISDDNEWITMAPIILSETAAIN
JI
~
10
0.1
C·4.F
r4
"
Error vs Crest Factor
0.3
,
V,~IIIV.PW·20D;,s.OUTVCYClECHANGED
TO DITAIN DtFFERENT CREST FACTORS
0
100
lk
10k
1
FREOUENCY IHzI
2
3
4
5
6
7
B
9 10
CRESTFACTOR
TL/H/5694-3
Typical Applications (All applications require power supply by-pass capacitors.)
'OUT
t-,.
.r
'IN
1&
15
v· CEXT
1t4 Y13
T
Itz 111
1D
9
LHDD91
P ~~ 13 14 15 1&
P.J:
TUH/5694-4
CEXT;' If'F;
frequency;' 1 kHz
FIGURE 1. LH0091 Basic Connection (No Trim)
5-26
r-
::I:
o
Typical Applications (Continued)
o
....
(Q
Rl
10k
V+ 0-....1\l1li,,"-0 VRT
~
240k
~------t-------~--O'OUT
CEXT ~ I,..F, f ~ I kHz
lM
R4
500
Note. The easy trim procedure is used for ae coupled input signals. It involves two trims and can achieve accuracies of 2 mVoffset ± 0.1 % reading.
Procedure:
I, Apply 100 mV rms (sine wave) to input, adjust R3 until the output reads
100 mVoc.
2. Apply 5 Vrms (sine wave) to input, adjust R4 until the output reads 5 Voc.
3. Repeat steps 1 and 2 until the desired initial accuracy is achieved.
LH0091
FIGURE 2. LHDD91 "Easy Trim" (For ac Inputs Only)
Rl
10k
RI
~
de symmetry balance
R2
~
Input offset
Note. This procedure will give accuracies of 0.5 mV offset ±O.05% reading
for inputs from O.05V peak to 10V peak.
R3 ~ Output offset
R4
~
3M
Procedure:
I. Apply 50 mVoe to the input. Read and record the output.
Gain adjust
R2
10k
2. Apply - 50 mVoe to the input. Use R2 to adjust for an output of the same
CEXT
magnitude as in step 1.
v+Q-""""""",.....OV"'-1--+--0 'OUT
3. Apply 50 mV to the input. Use R3 to adjust the output for 50 mY.
4. Apply -50 mV to input. Use R2 to adjust the output for 50 mY.
5. Apply ± I OV alternately to the input. Adjust RI until the output readings
for both polarities are equal (not necessary that they be exactly 10V).
'tN
6. Apply 10V to the input. Use R4 to adjust for 10V at the output.
7. Repeat this procedure to obtain the desired accuracy.
LH0091
FIGURE 3. LHDD91 Standard dc Trim Procedure
FILTERED
OUTPUT ...__________.,
Note. The additional op amp in the LH0091 may be used as a low pass filter
as shown in Figure 4.
LHDD91
Cl
Rl
RI
~R2~16k
CI~C2~I,..F
Rl
fo"'IO Hz
TL/H/5694-6
FIGURE 4. Output Filter Connection Using the Internal Op Amp
5·27
~ r-----------------------------------------------------------------------------------------~
G)
g Typical Applications (Continued)
:::z::
..J
10k
v+o-....JI\N\r--ovNote. When converting signals with a crest factor '" 2, the LH0091 should
be connected as shown. Note that this circuit utilizes a 20k resistor to drop
the input current by a factor of five. The frequency response will correspond
to a voltage which is 1/5 eiN.
3M
Note that the extra op amp in the LH0091 may be used to build a gain of 5
amplifier to restore the output voltage.
10k
10.F
v+~v-
'IN
tOUT
ZOk
1':':'-+'::-+':-+=-...+-0 'OUT
LH0D91
LH0091
v-
10k
10k
TUH/5694-7
Note. Respond time of the dc output voltage is dominated
by the RC time constant consisting of the total resistance
between pins 9 and 10 and the external capacitor, CEX.
FIGURE 5. High Crest Factor Circuit
Definition of Terms
True rms to dc Converter: A device which converts any
signal (ac, dc, ac + dc) to the dc equivalent of the rms value.
Error: is the amount by which the actual output differs from
the theoretical value. Error is defined as a sum of a fixed
term and a percent of reading term. The fixed term remains
constant, regardless of input while the percent of reading
term varies with the input.
Total Unadjusted Error: The total error of the device with·
out any external adjustments.
Bandwidth: The frequency at which the output dc voltage
drops to 0.707 of the dc value at low frequency.
Frequency for Specified Error: The error at low frequency
is governed by the size of the external averaging capacitor.
At high frequencies, error is dependent on the frequency
response of the internal circuitry. The frequency for specified error is the maximum input frequency for which the out·
put will be within the specified error band (i.e., frequency for
1% error means the input frequency must be less than 200
kHz to maintain an output with an error of less than 1 % of
the initial reading.
Crest Factor: is the peak value of a waveform divided by
the rms value of the same waveform. For high crest factor
signals, the performance of the LH0091 can be improved by
using the high crest factor connection.
5-28
r-------------------------------------------------------------------------.r
::I:
o
NatiOnal
~ Semiconductor
o
CD
~
Corporation
LH0094 Multifunction Converter
General Description
• Minimum component count
• Internal matched resistor pair for setting m=2 and
m=0.5
The LH0094 multifunction converter generates an output
voltage per the transfer function:
Eo = Vy
(~~)m. 0.1 S:mS:10. m continuously adjustable
Applications
m is set by 2 resistors.
•
•
•
•
•
•
•
•
Features
•
•
•
•
Low cost
Versatile
High accuracy-0.05%
Wide supply range- ±5V to ±22V
Precision divider. multiplier
Square root
Square
Trigonometric function generator
Companding
Linearization
Control systems
Log amp
Block and Connection Diagrams
Dual·ln·Line Package
v,
V.
E.
LH0094
Vy
Ra
Order Number LH0094D or LH0094CD
See NS Package Number D16D
E.
Vc
Vv
A4-
V-
RA
RCOMMON
Ra
TOP VIEW
Simplified Schematic
12
13
v. o-JtI\,.,......p ..
lOOk
V,
lOOk
lOOk
16
1
E.
Vy
lOOk
":"
TL/H/5695-1
5-29
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
±22V
Input Voltage
±22V
Output Short-Circuit Duration
Continuous
Operating Temperature Range
LH0094CD
LH0094D
- 25°C to + 85°C
- 55°C to + 125°C
Storage Temperature Range
LH0094D
LH0094CD
-65°C to
-55°C to
Lead Temperature
(Soldering, 10 seconds)
Electrical Characteristics
Vs = ± 15V, T A = 25°C unless otherwise specified. Transfer function: Eo = Vy
Parameter
2600C
J
vm
x ' 0.1 :S: m :S: 10; OV :S: Vx, Vy, Vz :S: 10V
LHOO94
Conditions
Min
+ 150°C
+ 125°C
LH0094C
Typ
Max
0.25
0.10
0.2
Units
Typ
Max
0.45
0.45
0.1
0.2
0.9
0.25
0.10
0.2
0.45
0.45
0.1
0.2
0.9
%F.S.
%F.S.
mVrC
0.25
0.15
0.45
0.45
0.15
0.9
%F.S.
%F.S.
2.0
%F.S.
%F.S.
Min
ACCURACY
Multiply
Untrimmed
External Trim
Divide
Untrimmed
ExtemalTrim
Square Root
Untrimmed
External Trim
Square
Untrimmed
External Trim
Low Level
Square Root
Exponential
Circuits
OUTPUT OFFSET
EO = VzVy (0.03:S:Vy:S: 10V; 0.01 :S:Vz:S: 10V)
(Figure 2)
(Figure 3)
vs. Temperature
Eo=10VzlVx
(Figure 4), 0.5:S:Vx:S:10; 0.01 :S:Vz:S:l0)
(Figure 5), (0.1 :S:Vx:S:10; 0.Q1 :S:Vz:S:l0)
vs. Temperature
Eo=l0Nz7j0
(Figure8), (0.03:S:Vz:S:l0
(Figure 9), (0.Q1 :S:Vz:S:l0
Eo= 10 (Vz/l0)2 (0.1 :S:Vz:S:l0)
(Figure 6)
(Figure 7)
Eo=.Jl0Vz; 5.0mV:S:Vz:S: 10V, (Figure 10)
1.0
0.5
0.15
m=0.2, Eo=10 (Vz/10)2 (Figure 11), (0.1 :S:Vz:S:10)
m=5.0, Eo= 10 (Vz/10)5 (Figure 11), (1.0:S:Vz:S:l0)
I
I
Vx=10V, Vy=Vz=O
I
1.0
0.15
%F.S.
(10V)
%F.S.
mVioC
0.05
0.05
%F.S.
0.05
0.05
0.08
0.08
%F.S.
%F.S.
2.0
I I
I
5.0
5.0
I
10
I
mV
AC CHARACTERISTICS
3 dB Bandwidth
Noise
m=1.0, Vx=10V, Vy=O.l Vrms
10 Hz to 1.0 kHz, m= 1.0, Vy=Vz=OV
Vx=10V
Vx=O.1V
10
10
kHz
100
300
100
300
p.V/rms
p.V/rms
EXPONENT
m
Io:.~o I ~o I Io:.~o I I
I
I
O·;oto
0.;
INPUT CHARACTERISTICS
Input Voltage
Input Impedance
(For Rated Performance)
(All Inputs)
0
98
10
100
0
98
10
100
V
kO
12
1.0
3.0
V
0
mA
OUTPUT CHARACTERISTICS
Output Swing
Output Impedance
Supply Current
(RL:S: 1Ok)
10
(Vs= ±15V) (Note 1)
Note 1: Refer to RETS0094D drawing for spectflcatlons of the military LH00940 version.
5-30
12
1.0
3.0
10
5.0
5.0
r-----------------------------------------------------------------------------,
I
:£:
Applications Information
o
o
<0
"'"
(b)m<1
GENERAL INFORMATION
Power supply bypass capacitors (0.1 ".F) are recommended
for all applications.
The LH0094 series is designed for positive input signals
only. However, negative input up to the supply voltage will
not damage the device.
R2
m=--R1+R2"'200n
R1+R2
A clamp diode (Figure 1) is recommended for those applications in which the inputs may be subjected to open circuit or
negative input signals.
For basic applications (multiply, divide, square, square root)
it is possible to use the device without any external adjustments or components. Two matched resistors are provided
internally to set m for square or square root.
When using external resistors to set m, such resistors
should be as close to the device as possible.
(c)m>1
R1+R2
m=-R2
TLlH/5695-4
ACCURACY (ERROR)
The accuracy of the LH0094 is specified for both externally
adjusted and unadjusted cases.
SELECTION OF RESISTORS TO SET m
Internal Matched Resistors
Although it is customary to specify the errors in percent of
full-scale (10V), it is seen from the typical performance
curves that the actual errors are in percent of reading. Thus,
the specified errors are overly conservative for small input
voltages. An example of this is the LH0094 used in the mUltiplication mode. The specified typical error is 0.25% of fullscale (25 mV). As seen from the curve, the unadjusted error
is :::: 25 mV at 10V input, but the error is less than 10 mV for
inputs up to tV. Note also that if either the multiplicand or
the multiplier is at less than 10V, (5V for example) the unadjusted error is less. Thus, the errors specified are at fullscale-the worst case.
The LH0094 is designed such that the user is able to externally adjust the gain and offset of the device-thus trim out
all of the errors of conversion. In most applications, the gain
adjustment is the only external trim needed for super accuracy-except in division mode, where a denominator offset
adjust is needed for small denominator voltages.
RA and Rs are matched internal resistors. They are
100!l±10%, but matched to 0.1%.
(a) m=2*
~3
10
6
(b) m=O_5*
~14
6.A~~
)
3
Ra
7.AAA
-9
""".. -:::!:-
EXPONENTS
TL/H/5695-2
The LH0094 is capable of performing roots to 0.1 and powers up to 10. However, care should be taken when applying
these exponent-otherwise, results may be miSinterpreted.
For example, consider the y.,oth power of a number: i.e.,
0.001 raised to 0.1 power is 0.5011; 0.1 raised to the 0.1
power is 0.7943; and 10 raised to the 0.1 power is 1.2589.
Thus, it is seen that while the input has changed 4 decades,
the output has only changed a little more than a factor of 2.
It is also seen that with as little as 1 mV of offset, the output
will also be greater than zero with zero input.
·No external resistors required, strap as indicated
External Resistors
The exponent is set by 2 external resistors or it may be
continuously varied by a single trim pot. (Rl + R2,;;5000.
(a) m= 1
TLlH/5695-3
5-31
g
C)
Applications Information (Continued)
....I
1. CLAMP DIODE CONNECTION
::c
01
lN914
V+
--*--+-----,
Vxo------4--~-,
Eo=Vy
LH0094
(~) m
O.1.:m':10
Note. This clamp diode connection is
recommended for those applications
in which the inputs may be subject to
ED
open circuit or negative signals.
Vyo--_..a
FIGURE 1. Clamp Diode Connection
2. MULTIPLY
V+
0.4
MULTIPLY
ED = VyVz
10
0.3
10.0~~ o - - + - - - t - - + - . . ,
r--+--o Vz
WITHOUT EXTERNAL
ADJUSTMENTS
~
~
a:
Q
a:
a:
III
0.2
Vy = 10V
w
LH0094
1/
0.1
L,..oo
ED = Vy V.
10
Vy
o
0--+---1
0--+---.....
o
~
=5V
rlllill
0.1
10
Vz(V)
FIGURE 2a. LH0094 Used to Multiply (No External Adjustment)
10V REF
(LH0070 OR
LH0075)
~~
FIGURE 2b. Typical Performance of
LH0094 In Multiply Mode Without
External Adjustment
0--------------------1-......,
Vz
~
Rl
2M
ED = Vy Vz
10
10
o----~I-I-.....
Trim Procedure
RZ
Set Vz=Vy=10V
10k
Adjust R2 until output= 10.000V
TLIH15695-5
FIGURE 3. Precision Multiplier (0.02% Typ) with 1 External Adjustment
5-32
Applications Information
3. DIVIDE
r
o
::I:
(Continued)
o
co
01
IN914
r--*--
0.4
I
I
0.3
""
DIVIDE
I
I
Eo= 10
r-----~--------~Vx
.,;
0::
0
0::
Vx
AOJIYITiI~TS -t--hH+tl:HI-H+HJj!
u:
C
~
WITHOUT EXTERNAL
0.2
Vx =0.5V/
~
0.1
LH0094
E. = 10!!!.
Vx
o 1O:::~:!:::t!:ttIIIL"'..lJ1WJIII.I.lI.L...l..IIII.llIIWlll
o
0.1
10
0--+---'
Vz (VI
Vy = 10V REF
0---------'
FIGURE 4a. LH0094 Used to Divide (No External Adjustment)
FIGURE 4b. Typical Performance,
Divide Mode,
Without External Adjustments
-.
I
_
*01
IN914
- +
I
r-------~._~--~--+-_4~-~
Trim Procedures
Apply 10V to Vy, O.W to Vx and Vz.
Adjust R3 until EO~ 10.000V.
Vz
Apply 10.000V to all inputs.
Adjust R2 until Eo~ 10.000V
Repeat procedure.
RI
2M
m=I
Eo = 10
~
o---------+-+---'
Vx
R2
10V REF
(LH0070 OR
LH00751
10k
o-......'V\/'Ir~....--~
FIGURE 5. Precision Divider (O.OS% Typ)
4. SQUARE
01
IN914
Vx
Vz) 2
EO~Vy (
0.5
r-------...--*-Vxo-----+_~
SQUARING
Eo=IO
0.4
Vz
~
"~
0::
0
0::
0::
w
0.3
L
2
WITHOUT EXTERNAL
ADJUSTMENT
'-
j
0.2
0.1
o
Eo
Vyo--_....
(~)
o
-I
~~
2
3
..,.
4
5
If
V
6
7
8
9 10
Vz(VI
TLiH/5695-6
FIGURE 6b. Squaring Mode without
External Adjustment
FIGURE 6a. Basic Connection of LH0094 (m = 2) without
External Adjustment Using Internal Resistors to Set m
5-33
~
en
CI
CI
:::E:
....
r---------------------------------------------------------------------------------,
Applications Information
(Continued)
,..
01
4. SQUARE (Continued)
--
lN914
--~~
Vx
'"' 10V
REF
V+
r- H16
14
Y15
A3Al
2M.
11
112
10 19
Vz
LHDD94
Eo
Eo
13
Vx
,...
Jl
• RA
A4-
Vy
2
3
14
VZ)2
(10
EO=10
~:
RS
7-:;
6
V-
R2
Vy
lDV REF
,...
Tr1m Procedure
11lk
- L
Apply 10V to Vz
Y
Ad just R2 for 10.000V at output
FIGURE 7. Precision Squaring Circuit (0. 15% Typ)
5. SQUARE ROOT
0.4
SIlRDO
Eo=ID
Vxo-----t--t-,
0.3
V,
~
~
10
368
...
M-'
z
;\
f:::
.
iii
Tj " -55'C
TI·125"C.
~
~
.A
"
"z
100
100
lk
10k
lOOk
FREQUENCY (HII
Thermal Response
in Still Air
40
U
'- 300
~
"""
10
Thermal Time Constant
4D0
..ill'"
lOOk
45
~
....'"
10k
lk
FREQUENCY 1Hz!
Thermal Resistance
Junction to Air
~
"-
240
200
100
TIME 1..1
zoo
~
r\.
Tj"25'C10
.~
280
~
z
>
0.1
~
Co)
Co)
320
I
10
i...
,tjUT
is:
'z·'mA
Tj • 25'C
g
w
]>
.....
r-
Noise Voltage
Dynamic Impedance
100
,
ll!0-
3D
i
20
0-
lD
z
\
TQ-4&
~
~
TO·12
35
25
15
800
1200
1&UG
100
=>
~
60
>
~
60
'"
...
z
1\
1\
!
TO-46
1'1"-+
TO·92
400
i!
400
2000
AIR VHOCITY (FPMI
800
1200
1600
40
~
I
20
4
2000
TIME IMINUTESI
AIR VELOCITY (FPMI
Thermal Response in
Stirred Oil Bath
Forward Characteristics
1.4
i!
w
100
=>
~
80
>
~
60
'"
....
z
~
0-
...z
40
20
111111
1.2
.,'"
E
w
...'"~
I
II
>
;"
~
"
L
1.0
f.I.I~~·C
--Ti"'25°C
0.6
0.4
~
I - r--
0.2
--
1_
0.6
I
Tj" 125'C
1111111
0.1
TIME ISECONOSI
10
FORWARD CURRENT ImAI
TL/H/5698-3
6-23
~r-------------------------------------------------------------~
~
Application Hints
~
CALIBRATING THE LM135
~
;;
N
::::E
::::::!
~
~
::::E
.....I
.,;
~
~
u;
This single pOint calibration works because the output of the
LM135 is proportional to absolute temperature with the extrapolated output of sensor going to OV output at O'K
( - 273. 15'C). Errors in output voltage versus temperature
are only slope (or scale factor) errors so a slope calibration
at one temperature corrects at all temperatures.
VOUTT = VOUTTo X To
.....I
where T is the unknown temperature and To is a reference
temperature, both expressed in degrees Kelvin. By calibrating the output to read correctly at one temperature the output at all temperatures is correct. Nominally the output is
calibrated at 10 mVI'K.
::::E
.,....
::::E
.....I
WATERPROOFING SENSORS
Meltable inner core heat shrinkable tubing such as manufactured by Raychem can be used to make low-cost waterproof sensors. The LM335 is inserted into the tubing about
Yz' from the end and the tubing heated above the melting
point of the core. The unfilled Yz' end melts and provides a
seal over the device.
T
N
~
If the sensor is used in an ambient where the thermal resistance is constant, self heating errors can be calibrated out.
This is possible if the device is run with a temperature stable
current. Heating will then be proportional to zener voltage
and therefore temperature. This makes the self heating error proportional to absolute temperature the same as scale
factor errors.
The output of the device (calibrated or uncalibrated) can be
expressed as:
CO)
CO)
To insure good sensing accuracy several precautions must
be taken. Like any temperature sensing device, self heating
can reduce accuracy. The LM135 should be operated at the
lowest current suitable for the application. Sufficient current,
of course, must be available to drive both the sensor and
the calibration pot at the maximum operating temperature
as well as any extemal loads.
Included on the LM135 chip is an easy method of calibrating
the device for higher accuracies. A pot connected across
the LM135 with the arm tied to the adjustment terminal allows a 1-point calibration of the sensor that corrects for
inaccuracy over the full temperature range.
Typical Applications
Basic Temperature Sensor
Calibrated Sensor
y+
Wide Operating Supply
v+
V·
5V-40V
OUTPUT
10mVfK
6---..- - OUTPUT 10 mVfK
LM335
~-.....~ 10k·
TUH/5698-2
TUH/5698-9
'Calibrate for 2.982V at 25'C
Minimum Temperature Sensing
TL/H/5698-IO
Average Temperature Sensing
Remote Temperature Sensing
15V
15V
6k
6k
r-_ _ _..._ _ _...........~TMIN
TAVG (30mV/"K)
10 mVfK
LM335
TUH/5698-4
TL/H/5698-19
Wire length for ,'C error due to wire drop
TL/H/5698-18
AWG
14
16
18
20
22
24
IR = 1 mA
FEET
4000
2500
1600
1000
625
400
IR = 0.5 mA'
FEET
8000
5000
3200
2000
1250
800
'For IR = 0.5 mA, the trim pot must be deleted.
6-24
Typical Applications
(Continued)
Isolated Temperature Sensor
lM33S
15V
SDk
3k
L~]BOURNS
---
4258-0001
•
15V
r-____~-t,N~.5t'_1~D.,~
2k
5111
lN914
10k
1
1Ooo
lN914
-15V
"::.-
'F
-15V
TLIH/S698-20
Simple Temperature Controller
IOV-3DV_1'"""------------------------~~_1~------...,
HEATER
lM329C
lM395
TL/H/S698-S
Simple Temperature Control
lU3lS
5V-40V
SET
TEMPERATURE
311:
LM329C
3k
1k
-lOY
TL/H/S698-21
6-25
Typical Applications
(Continued)
Ground Referred Fahrenheit Thermometer
Centigrade Thermometer
,.
ISY
15Y
16Y
"
..
R'"
I
OUTPUT
R2"
'Ok
20k
LM335
,2k
10mVl"C
t----6~.~."~k~~~:~~l
8.5k
LM33B
Ik
."
-1SV
TL/H/569B-22
'::'
'::'
'Adjust R2 for 2.554V across LM336.
..k
r'
Adjust RI for correct output.
'::'
TL/H/569B-23
'Adjus!lor 2.7315V at output of LM308
Fahrenheit Thermometer
I5Y
"k
'Ok
,.
.,
4.55"
OUTPUT
} 'mVff
~--~~~~~~~~
LM33S
"
R2 •
'Ok
LU33S
'Ok
TL/H/5698-24
'To calibrate adjust R2 for 2.554V across LM336.
Adjust RI for correct output.
THERMOCOUPLE COLD JUNCTION COMPENSATION
Compensation for Grounded Thermocouple
·Select R3 for proper thermocouple type
THERMOR3
(± 10/0)
COUPLE
3770
J
30S0
T
15V
4.Jk
200k
",
K
S
R3*
,:~ » 1.0 MO. This is
the feedback sense voltage and includes errors in both the sensor and op amp. This voltage is specified for the sensor in a rapidly stirred oil bath. The output is
referred to V+.
Note 3: The output leakage current is specified with:> 100 mV overdrive. Since this voltage changes with temperature,the voltage drive for turn·off changes and Is
defined as VOUT (with output and input shorted) -100 mY. This specification applies for VOUT=36V.
Application Hints
Although the LM3911 is designed to be totally trouble-free,
certain precautions should be taken to insure the best possible performance.
As with any temperature sensor, internal power dissipation
will raise the sensor's temperature above ambient. Nominal
suggested operating current for the shunt regulator is 1.0
mA and causes 7.0 mW of power dissipation. In free, still, air
this raises the package temperature by about 1.2·K. AIthough the regulator will operate at higher reverse currents
and the output will drive loads up to 5.0 mA, these higher
currents will raise the sensor temperature to about 19' K
above ambient-degrading accuracy. Therefore, the sensor
should be operated at the lowest possible power level.
With moving air, liquid or surface temperature sensing, selfheating is not as great a problem since the measured
media will conduct the heat from the sensor. Also, there are
many small heat sinks designed for transistors which will
improve heat transfer to the sensor from the surrounding
medium. A small finned clip-on heat sink is quite effective in
free-air. It should be mentioned that the LM3911 die is on
the base of the package and therefore coupling to the base
is preferable.
The internal reference regulator provides a temperature stable voltage for offsetting the output or setting a comparison
point in temperature controllers. However, since this reference is at the same temperature as the sensor temperature,
changes will also cause reference drift. For application
where maximum accuracy is needed an external reference
should be used. Of course, for fixed temperature controllers
the internal reference is adequate.
6-31
....
....
....
....
~
:E
Typical Performance Characteristics
...I
Temperature
Conversion
Op Amp Input Current
1
T FAHRENHEIT = T F
40
I-
35
E
V
.,..'/
~
5
~
+ TF) 9 -40
+ Tel
i:l
~
a;
TKELVIN = TK
TK = Tc + 273.16
TF = (40
0.6
45
i.
TCENTIGRADE = TC
Tc = (40
Power Supply Current
0.1
50
"..
3D
"
V
1/
"
.!! 0.5
I-
ill u
~>-
~I'
T.· 25"C
0.3
~
0.2
0.1
~
"
9
o
25
-55 -35 -15 5.0 25 45 65 85 105 125
5 -40
o
TEMPERATURE ('CI
Output Saturation
Voltage
C
Thermal Time Constant
in Stirred Oil Bath
i!
w
16
"
I-
ill
~
.
z
in
~
12
~
1/
T.·25"~_
~
8.0
/
5
~
>
..""
..."'"
~
4.0
/
o /
o
T01&
100
80
60
/'
I /
20
2.0
3.0
4.0
~~
~w
.....
~i
;<
24
8.0
C
20
6.0
~5
4.0
I!:"'
gB
2.0
Ii
iii
~
w
V
2.0
4.0
~
4.0
f-! V
i...
Reference Regulation
~
"w
~~
w
'"'"
!:;
20
>
10
'"
~
..
ill
20
10
12
14
./
T. =25"C
/'
. . .V
.....o
>
6.0
1.0
SUPPLY CURRENT (mAl
10
12
1.0
...-rii'.s
// K
~/ 'M,N, Dip
V /
V
/
'V
-&.0
I-
-3.0
5
~
III
,/
a:
4.0
§
2.0
u
~
~
..
r
200
TIME ""I
300
V ./
",
TO·5
~V
~
o~
o 1.0 2.0
3.0 4.0
5.0
6.0 1.0
OUTPUT SINK CURRENT (mAl
!:l
w
r\
rr-~.Rs"UkI
100
14
Amplifier Output Impedance
R.=1.5k'
J
12
16V L
8.0
10
~
1'1
10
100
I
r
10
:;: '.0
!
r
8.0
Device Temperature Rise
...;<.
~
P'
J.
8.0
~
,0V
rB3;~.~
4.0
TIME (MINUTESI
> -8.0
o~
4.0
-2.U
-4.0
5~-1.O
!; ~ -2.0
V
2.0
::I'"
~
TO~~
2.0
TA = 25'C
40
w
40
Turn "ON" Response
.!!
30
60
~
2.0
4.0
6.0
8.0
10
SHUNT REGULATOR CURRENT (mAl
50
"''"
8.0
TO""
12
4.0 5.0 &.0 1.0 2.0 3.0 4.0 5.0
~~
SUPPLY
SUPPLY
VOLTAGE IVI
CURRENT ImAI
S
6.0
/T
B.O
!!!
,/
-
z
'...."
16
.g;
w
o
80
Device Temperature Rise
10
5t;
100
"
TIME (SECONDSI
~
~
6.0
[;!
o
5.0
.....
5.0
~
Supply Sensitivity
tw
i!
w
">~
1/
SATURATION VOLTAGE (VI
(REFFERED TO V-I
.ei" .."
.......
~
1.0
3.0 4.0
Thermal Time Constant In
Stili Air
TO·5
40
2.0
L
DEVICE VOLTAGE IVI
20
.!!
IL
1.0
V
/~
400
1.0
100
Uk
10k
lOOk
FREOUENCY (Hzl
TUH/5701-2
6-32
r-
3:
c;,.)
Schematic Diagram
CD
.....
.....
v'
R1
5.0k
02
Typical Applications
(Continued)
Basic Thermometer for Negative Supply
Basic Thermometer
for Positive Supply
Increasing Gain and Output Drive
15V
15V
v'
V·
R,
1.Sk
R,
7.Sk
) 10mvrK
Note: Load current to GND
is supplied through RS
~
(V- - 6.8V) X 103n
Rs
External Frequency Compensation
for Greater Stability when Driving
Capacitive Loads
~
l.Ok
r-~+~*-....-+-... )~OU!~~K
OUTPUT
RS
t-----,
(V- - 6.8V) x 103n
Operating With External Zener for
Lower Power Dissipation
Temperature Controller With Hysteresis
+15V
15V
1.Sk
R,
1.Sk
15V
R,'
20k
+
1100
OUTPUT
) lDmVt'K
lOOk
~
INPUT
OUTPUT
LMJ911
lN821
rl-f'
R,
10
~ OUTPUT*
22M
·Output goes positive on temperature increase
·Depends on Zener current.
6-33
"lSet temperature
TL/H/5701-3
Typical Applications
(Continued)
Meter The~mometer With Trimmed Output
Thermometer With Meter Output
AI' ~
(Vz) O.OI~T "
1M (Vz - 0.01 TO)
IIV
v'
Select 10 .:
R.
3."
R,"
2V
Ai"
A2 ~ 0.Q1 TO - laAI
10
sa.
+
OUTPUT
~
LM3911
~~~7k
R3
RZ'
2V )
(la.:A1
28.21.
=
~-
~
so.
RI"
LM3911
R2"
INPUT
-
R3"
Shunt regulator voltage (use 6.85)
Meter temperature span rK)
Meter full scale current (A)
Meter zero temperature rK)
Current through A I, A2, A3 at zero
meter current (10 p.A to 1.0 mAl (A)
03'
38.1.
v'Rs"~
D.001A+IM +10
B.DII
OUTPUT-~
R1 - R2
10
INPUT
-
+
~
SOOI
·Values shown for:
To
1M
~
~
300'K,
~T ~
1.0 mA, 10
~
'Selected as for meter thermometer except To should
be S'K more than desired and 10 ~ 100 p.A
100'K,
100 p.A
tCalibrates To
"The 0.Q1 In the above and following equations Is in units of VI"K or W'C,
and is a result of the basic 0.01 W'K sensitivity of the transducer
Ground Referred Thermometer
....- ...._ - - -_ _...;;~sv AI ~
(Vz)(10mV)(bon
0.Q1 To)
AL
Ground Referred Centigrade Thermometer
!'Q (VZ RI
ZOO
1%
A2 ~ 0.01 To -la AI
10
R2
LM3911
INPUT
A3
t--....,I-....,I--..
~~-
AI - A2
10
Shunt regulator voltage
Temperalure span rK)
Temperature for zero output ('K)
Full scale output voltage': 1OV
Uk
-15V_"",.,......_ - -....
Currentthrough Rl, A2, A3
at zero output voltage
(typically 100 p.A to 1.0 mAl
Vz
~T
TO
Vo
10
.3
OUTPUT
1.5k
lDmvrC
OUTPUT
30pF
·Setzero
Two Terminal Temperature to Current Transducer'
~~ +
~~
~ ~LMII3
INHO~
100:"-
..!...~
-'
"I
+
12k
30.
+12VTO +4 ov
A4
1
(vz - 0.01 TLl(A2)
[ (A2)(0.01TLl+
Rl
)]
( Vz - 0.01 TL
A2
-IL
..!... ..!...
_..!...
A2
A2 + A3
INPUT
LM3111
*20.F
OUTPUT
....
....~~
~
-
~NH05
.4
115.211
"Z
61.4k
R3
1l1li
lOOk
TL
TH
Vz
IL
IH
TemperatureforlL< K)
Temperature for IH ( K)
Zener voltage (V)
Low temperature output current (A)
High temperature output current (A)
'Values shown for
10UT~ 1
mA to 10 rnA for 100F to 100'F
tSeI temperature
TLlH!5701-4
"The 0.01 in the above and following equations is in units of V!'K or V!'C, and Is a result of the basic 0.01 V!'K sensRivity of the transducer
6-34
Typical Applications (Continued)
Over Temperature Detectors With Common Output
"V
v'l
As
As
1.5k
+
Al
OUTPUT
~ INPUT
J
Al
Al
DU:.UT
~ INPUT
.L
J
'.D
AZ
OUTPUT
~ INPUT
T' P'
rip Oint ~
lMJ911
AZ
.L
.L
+
Al
LM3911
lMl911
AZ
A,
Uk
OUTPUT
DU:.UT
INPUT
lMl911
AZ
..
As
7,5k
7.5k
V
z Rl
R1
+ R2
RS ~ _.!.(V=-.+_-..;6:::.B7V::,),.,-6.BV
0.001 A + Rl + R2
.L
TL/H/5701-5
Two-Wire Remote A.C. Electronic Thermostat (Gas or Oil Furnace Control)
2.2/'F
IN457
10k
~II
S.C.RS.
CI06A2
DA
IRIDGAl
2&VAC
CONTROL
TRANSFORMER
60Hz
TRIM
SET t
T'~:~~~~~~~~~~
J~~k
4W-WN
'--r---'
4.n.
4JM
lN457
JUII
1%
I.Sk
II.
O.O'pF
51D
REMOTE
TL/H/5701-B
·Solenoid or 6-1SW heater
tPot will provide about a 50"F to 90'F setting range. The trim resistor (lOOk) is selected
to bring 70'F near the middle of the pot rotation.
seR heating. by proper positioning. can preheat the sensor giving control anticipation as is presently used in many home thermostats.
Electronic Thermostat
BLACK
I~-l
_a}
LOAD
SENSITIVE GATE TRIAC
+
AC
115V
&0 Hz
IGT~"5
ZlD
~DW
50.
rnA
RCA T2300, 40529
LM3911
OR SIMILAR
·Set temperature
WHITE
5.111
tSCR turns on power to fan or
cooler when temperature increases.
6-35
TlIH/5701-9
....
....
~
:i
Typical Applications
(Continued)
Three-Wire Electronic Thermostat
lN40D4
J.n
LOAD (HEATER: to rnA TO 35AI
821
'DO
'12W
16.211
'%'
'OM
'01
>.1--...----+-.....'11\0-.....
2N5D&4
TO 'ZDVAC
105M
'Divider is set for a nominal O'C -125'C range.
Wire wound resistors will provide maximum
temperature stability.
"Almost any TRIAC rated 1 to 35 amperes
usable with appropriate load.
Differential Thermometer
.,sv
R2
150k
Kelvin Thermometer With
Ground Referred Output
OUTPUT
R4
41
I5V
v'
R.
~
3.0k
fiAI.
,......-JL.+;""'.,
0."
I.
LM3911
NO.1
INPUT
R'
n,I"
v'
3.Ok
e,
*L
0.00'
DUT~yF~
V·
v'
IN
lM39',
NO.2
OUT
V·
~ R!
R5
5.!1
7.51
2001
RS = Vs+ - a.BV x 103n
2
= 0.01
R,
+
R2
(T2 -
f
-+IIV
-, V
T,l"~; ~~~D
VOUT
R,
TRIM
Output can swing ± 3V at ± 50 ",A
with low output impedance
-'5V
"The 0.01 In the above equation Is in units of V/'K or VI'C, and Is a result
of the basic 0.01 V/'K sensitivity of the transducer
Connection Diagrams
TO-46 Package
Dual-In-Llne Package
V-
Ne
OUT
Ne
IN
Ne
v'
Ne
DUTPUT~V
INPUT~V'
TOP VIEW
Nott: Pin 41:oRnected to CISI.
TOP VIEW
Order Number LM3911 N
See NS Package N08E
6-36
TLlH/5701-6
TLIH1570'-7
Order Number LM3911 H-46
See NS Package H04A
Section 7
Voltage References
Section 7 Contents
Voltage Reference Selection Guide...................................................
LH0070 Series BCD Buffered Reference/LH0071 Series Precision Buffered Reference.....
LM103 Reference Diode ....................................................•.......
LM113/LM313 Precision Reference..................................................
LM129/LM329 Precision Reference..................................................
LM134/LM234/LM334 3-Terminal Adjustable Current Sources...........................
LM136-2.5/LM236-2.5/LM336-2.5V Reference Diode............ ......................•
LM136-5.0/LM236-2.5/LM336-2.5V Reference Diode..................... ..............
LM168/LM268/LM368 Precision Voltage Reference...................... ..............
* LM169/LM369 Precision Voltage Reference............................. ..............
LM185-1.2/LM285-1.2/LM385-1.2 MicropowerVoltage Reference Diode..................
LM185-2.5/LM285-2.5/LM385-2.5 Micropower Voltage Reference Diode. . . . . . . . . . . . . . . . . .
LM185/LM285/LM385 Adjustable Micropower Voltage References ...... '" . . .. .. . . ... . . .
LM199/LM299/LM399/LM3999 Precision Reference.................. .................
* LM368-2.5 Precision Voltage Reference. .. . . . . . . . . . .. .. . . .. . .. .. . .. . . . .. . . . . .. .. ... . . .
* LM581 Voltage Reference Precision 10-Volt ......................... ..................
·Devlces Not Covered In Last Publication
7-2
7-3
7-7
7-11
7-12
7-15
7-20
7-28
7-35
7-42
7-48
7-58
7-64
7-69
7-76
7-85
7-91
~NatiOnal
Semiconductor
Corporation
Voltage Reference Selection Guide
Shunt Type
Reverse Breakdown
Voltage (VR)
Device
Temperature
Operating
Voltage
Drift
Temp.
Tolerance
ppml'C
Over
Range" Max, TA = 25'C
(Max)
Range
1.22
1.22
1.22
1.22
LM113·2
LM113·1
LM113
LM313
M
M
M
C
±1%
±2%
±5%
±5%
1.235
1.235
1.235
1.235
1.235
1.235
1.235
1.235
1.235
1.235
LM185BX-1.2
LM185BY-1.2
LM185-1.2
LM285BX-1.2
LM285BY-1.2
LM285-1.2
LM385BX-1.2
LM385BY-1.2
LM385B-1.2
LM385-1.2
M
M
M
I
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
+2%, -2.4%
30
50
150
30
50
150
30
50
150
150
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
LM185B
LM185BX
LM185BY
LM285BX
LM285BY
LM285
LM385BX
LM385BY
LM385
M
M
M
±1%
±1%
±1%
±1%
±1%
±2%
±1%
±1%
±2%
2.49
2.49
2.49
2.49
2.49
2.49
LM136A
LM136
LM236A
LM236
LM336
LM336B
M
M
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
LM185BX-2.5
LM185BY-2.5
LM185B-2.5
LM285BX-2.5
LM285BY-2.5
LM285-2.5
LM385BX-2.5
LM385BY-2.S
LM385B-2.5
LM385-2.5
M
M
M
I
I
C
C
C
C
I
I
I
C
C
C
I
I
I
C
I
I
I
C
C
C
C
50 (Typ) -55'Cto + 125'C
50 (Typ) -55'Cto + 125'C
100 (Typ) - 55'C to + 125'C
100 (Typ)
O'Cto +70'C
Output
Operating
Dynamic
Current Range, IR Impedance
(Typ)
500 p.A to 20 mA
500 p.A to 20 mA
500 p.A to 20 mA
500 p.A to 20 mA
0.8
0.8
0.8
0.8
- 55'C to + 125'C
-55'C to + 125'C
- 55'C to + 125'C
-40'Cto +85'C
-40'C to + 85'C
-40'C to + 85'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
10 p.A to 20 mA
10 p.A to 20 mA
10 p.A to 20 mA
10 p.A to 20 mA
10 p.A to 20 mA
10 p.A to 20 mA
15 p.A to 20 mA
15 p.A to 20 mA
15 p.A to 20 mA
15 p.A to 20 mA
1
1
1
1
1
1
1
1
1
1
150
50
50
30
50
150
30
50
150
-55'C to + 125'C
-55'C to + 125'C
- 55'C to + 12S'C
-40'Cto +8S'C
-40'Cto +85'C
-40'Cto +85'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
10 p.A to 20 mA
10 p.A to 20 mA
10 p.A to 20 mA
10 p.A to 20 mA
10p.At020mA
10 p.A to 20 mA
13 p.A to 20 mA
13 p.A to 20 mA
13 p.A to 20 mA
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
±1%
±2%
±1%
±2%
±4%
±2%
72
72
72
72
54
54
- 55'C to + 125'C
-55'Cto + 125'C
-25'C to +85'C
-25'Cto +85'C
O'Cto +70'C
O'Cto +70'C
±1.5%
±1.5%
±1.5%
±1.5%
±1.5%
±1.5%
±1.5%
±1.5%
±1.5%
±3%
30
50
150
30
50
150
30
50
150
150
-55'Cto +125'C
-55'C to + 125'C
- 55'C to + 125'C
-40'C to + 85'C
-40'Cto +85'C
-40'Cto +85'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
7-3
400 p.A to
400 p.A to
400 p.A to
400 p.A to
400 p.A to
400 p.A to
10 rnA
10 mA
10 mA
10 mA
10 mA
10 mA
20 p.A to 20 mA
20 p.A to 20 mA
20 p.A to 20 rnA
20 p.A to 20 rnA
20 p.A to 20 rnA
20 p.A to 20 rnA
20 p.A to 20 rnA
20 p.A to 20 rnA
20 p.A to 20 mA
20 p.A to 20 rnA
0.4
0.4
0.4
0.4
0.4
0.4
1
1
1
1
1
1
1
1
1
1
fI
Shunt Type (Continued)
Reverse Breakdown
Voltage (VR)
Device
Temperature
Voltage
Operating
Drift
Temp.
Tolerance
ppmrC
Over
Range' Max, TA = 25"C
(Max)
Range
Output
Operating
Dynamic
Current Range, IR Impedance
(Typ)
5.0
5.0
5.0
5.0
5.0
5.0
LM136A
LM136
LM236A
LM236
LM336B
LM336
M
M
I
I
C
C
±1%
±2%
±1%
±2%
±2%
±4%
72
72
72
72
54
54
- 55°C to + 125°C
- 55°C to + 125°C
- 25°C to + 85°C
-25°C to +85°C
O°Cto +70°C
OOCto +70°C
400 p.A to 10 mA
400 p.A to 10 mA
400 p.A to 10 mA
400 p.A to 10 mA
400 p.A to 10 mA
400 p.A to 10 mA
0.8
0.8
0.8
0.8
0.8
0.8
6.9
6.9
6.9
6.9
6.9
6.9
LM129A
LM129B
LM129C
LM329B
LM329C
LM329D
M
M
M
C
C
C
+3%,-2%
+3%,-2%
+3%,-2%
±5%
±5%
±5%
10
20
50
50
20
100
- 55°C to + 125°C
- 55°C to + 125°C
- 55°C to + 125°C
OOCto +700C
O°Cto +700C
O°Cto +700C
600 p.A to 15 mA
600 p.A to 15 mA
600 p.A to 15 mA
600 p.A to 15 mA
600 p.A to 15 mA
600 p.A to 15 mA
0.6
0.6
0.6
0.8
0.8
0.8
6.95
6.95
6.95
6.95
6.95
6.95
6.95
6.95
6.95
6.95
LM199A
LM199A·20
LM199
LM299A
LM299A·20
LM299
LM399A
LM399A·50
LM399
LM3999
M
M
M
±2%
0.5
- 55°C to + 125°C 500 p.A to 10 mA
Same as LM199A with 20 ppm guaranteed long term drift.
±2%
1.0
-55°Cto + 125°C 500 p.A to 10 mA
±2%
0.5
- 25°C to + 85°C
500 p.A to 10 mA
Same as LM299A with 20 ppm guaranteed long term drift.
±2%
500 p.A to 10 rnA
1
- 25°C to + 85°C
±5%
1
O°Cto +700C
500 p.A to 10 rnA
Same as LM399A with 50 ppm guaranteed long term drift.
±5%
2
O°Cto +70°C
500 p.A to 10 mA
±5%
5
O°Cto +70°C
600 p.A to 10 mA
0.5
I
I
I
C
C
C
C
0.5
0.5
0.5
0.5
0.5
0.6
= O"C to 70"C, I (Industrial) = - 25'C 10 + 85'C for Ihe LM236 and LM299, I = - 40"C 10 + 85'C for all others.
= - 55'C 10 + 125'C
'C (Commercial)
M (Military)
Current References
Output Current
Range
2 p.A to 10 rnA
2 p.A to 10 mA
2p.At010mA
2p.At010mA
2p.At010mA
2p.At010mA
2p.At010mA
Device
LM134
LM134·3
LM134·6
LM234
LM234·3
LM234·6
LM334
Set Current Error
Operating
Temperature
Range
2 p.A to 10 p.A
10 p.A to 1 mA
-55°C to + 125°C
- 55°C to + 125°C
- 55°C to + 125°C
- 25°C to + 1000C
- 25°C to + 100°C
-25°C to +1000C
O°Cto +70°C
±8%
N/A
N/A
±8%
N/A
N/A
±12%
±3%
±1%
±2%
±3%
±1%
±2%
±6%
'Sel current changes linearly wilh temperalure al a rale of O.33%I'C.
7·4
1 mAtoSmA
Operating
Voltage
Range
Set Current
Temperature
Dependence"
±5%
N/A
N/A
±5
N/A
N/A
±8%
Wt040V
Wt040V
Wt040V
1Vt040V
Wt040V
1Vt040V
Wt040V
0.96T to 0.1 04T
0.98TtoO.102T
0.97T to 0.1 03T
0.96Tto 0.104T
0.98Tto 0.102T
0.97T to 0.1 03T
0.96TtoO.104T
Series Type (Buffered Output)
Output
Voltage
Device
Temperature
Oper.
Voltage
Drift
Temp.
Tolerance
ppml'C
Over
Range· Max, T A = 25'C
(Max)
Range
Load Reg.
ppm/mA
Over
Current
Range
Quiescent
Current
(mA)
2.5
2.5
LM368Y-2.5
LM368-2.5
C
C
±0.2%
±0.2%
20
30
O'Cto +70'C
O'Cto +70'C
25
25
OmAto+10mA
OmAto+10mA
0.55
0.55
5.0
5.0
5.0
5.0
LM168BY-5.0
LM268BY-5.0
LM368BY-5.0
LM368-5.0
M
I
C
C
±0.05%
±0.05%
±0.1%
±0.1%
10
15
20
30
-55'Cto + 125'C
-40'Cto + 85'C
O'Cto +70'C
O'Cto +70'C
10
10
10
10
-10 mA to +10 mA
-10mAto+10mA
-10 mAto +10 mA
-10 mAto +10 mA
0.35
0.35
0.35
0.35
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
LM169B
LM168BY-10
LH0070-2
LM169
LM581U
LH0070·0
LM581T
LH0070-1
LM5815
LM268BY-10
LM581L
LM369C
LM369
LM369B
LM581K
LM368Y-10
LM368-10
LM369D
LM581J
M
M
M
M
M
M
M
M
M
I
C
C
C
C
C
C
C
C
C
±0.05%
±0.05%
±0.05%
±0.05%
±0.05%
±0.1%
±0.1%
±0.1%
±0.3%
±0.05%
±0.05%
±0.05%
±0.05%
±0.05%
±0.1%
±0.1%
±0.1%
±0.1%
±0.3%
3
10
8
5
10
40
10
20
30
15
5
10
5
3
10
20
30
30
30
- 55'C to + 125'C
- 55'C to + 125'C
- 40'C to + 85'C
- 55'C to + 125'C
- 55'C to + 125'C
-40'Cto +85'C
- 55'C to + 125'C
-40'Cto +85'C
-55'Cto + 125'C
-40'Cto +85'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
8
10
60
8
50
60
50
60
50
10
50
8
8
8
50
10
10
8
50
-10 mAto +10 mA
-10 mAto +10 mA
Ot05 mA
-10mAto +10mA
OmAt05mA
OmAt05mA
OmAt05mA
OmAt05mA
OmAt05mA
-10mAto +10mA
OmAt05mA
-10mAto +10mA
-10mAto +10mA
-10mAto+10mA
OmAt05mA
-10mAto +10mA
-10mAto +10mA
-10mAto +10mA
OmAt05mA
1.8
0.35
5
1.8
1.8
5
1.8
5
1.8
0.35
1.8
1.8
1.8
1.8
1.8
0.35
0.35
2
1.8
10.24
10.24
10.24
LH0071-2
LH0071-1
LH0071-0
M
M
M
±0.05%
±0.1%
±0.1%
8
20
30
-40'Cto + 85'C
-40'C to + 85'C
-40'Cto + 85'C
60
60
60
OmAt05mA
OmAt05mA
OmAt05mA
5
5
5
'C (Commercial)
= O"C to 70"C. I (Industrial)
= -40"C to +8S"C. M (Military) = -SS"C to +12S"C
Low Current Reference Diodes
Output
Voltage
Device
3.0
3.3
3.6
3.9
LM103-3.0
LM103-3.3
LM103-3.6
LM103-3.9
Operating
Temp"
Range·
Voltage
Tolerance
Max, T A = 25'C
M
M
M
M
±10%
±10%
±10%
±10%
Temperature
Drift
ppml'C
(Max)
-1700
-1500
-1400
-1300
'M (Military) = -SS"C to + 125"C
7-5
Over
Range
- 55'C to
- 55'C to
- 55'C to
-55'Cto
+
+
+
+
125'C
125'C
125'C
125'C
Operating
Current Range, IR
Output
Dynamic
Impedance
(Typ)
10 ",A to 10 mA
10",At010mA
10",At010mA
10 ",A to 10 rnA
25
25
25
25
"Reference Grade" Voltage Regulators*
Output
Voltage
Adjustable:
1.235V to 30V
Device
Operating
Temperature
Range
LP2951
- 55'C to + 150'C
LP2951AC -40'C to + 125'C
LP2951C -40'C to + 125'C
Output
Output
Voltage
Quiescent
Load Reg. Line Reg.
Variation
Tolerance
Current
Current
Over Operating ppm/mA ppm/V
(Max)
Max, T A = 25'C
Range
±0.5%
±0.5%
±1%
±0.5%
±0.5%
±1%
100
100
200
42
42
83
100mA
100mA
100mA
120/LA
120/LA
120/LA
Programmable:
LH0075
5V,6V, 10V, 12V, 15V LH0075C
-55'Cto + 125'C
O'Cto +70'C
.±0.5%
± 1%
± 0.14 % (Typ)
±0.3% (Typ)
15
25
200
400
200mA
200mA
8mA
10mA
Programmable
-5V, -6V, -10V
-10V, -15V
LH0076
LH0076C
-55'Cto + 125'C
O'Cto +70'C
±0.5%
±1%
±0.14% (Typ)
± 0.3% (Typ)
15
25
200
400
200mA
200mA
15mA
15mA
5V
5V
LP2950AC -40'C to + 125'C
LP2950C - 40'C to + 125'C
±0.5%
±1%
±0.5%
±1%
100
200
42
83
100mA
100mA
120/LA
120/LA
'For more information on these circuits, refer to the Voltage Regulator section of the Databook.
7·6
_
.::J:
o
National
o
.....
o
......
Semiconductor
Corporation
.-::J:
o
o
LH0070 Series Precision BCD Buffered Reference
LH0071 Series Precision Binary Buffered Reference
.....
.....
General Description
The LH0070 and LH0071 are precision, three terminal, voltage references consisting of a temperature compensated
zener diode driven by a current regulator and a buffer amplifier. The devices provide an accurate reference that is virtually independent of input voltage, load current, temperature
and time. The LH0070 has a 10.000V nominal output to
provide equal step sizes in BCD applications. The LH0071
has a 10.240V nominal output to provide equal step sizes in
binary applications.
them ideal choices as reference voltages in precision D to A
and A to D systems.
Features
The LH0070 and LH0071 series combine excellent long
term stability, ease of application, and low cost, making
• Accuracy output voltage
10V±0.02%
LH0070
10.24V ±0.02%
LH0071
11.4V to 40V
• Single supply operation
0.20
• Low output impedance
0.1 mVIV
• Excellent line regulation
20/LVp-p
• Low zener noise
• S-Iead TO-S (pin compatible with the LM109)
• Short circuit proof
SmA
• Low standby current
Equivalent Schematic
Connection Diagram
The output voltage is established by trimming ultra-stable,
low temperature drift, thin film resistors under actual operating circuit conditions. The devices are shortcircuit proof in
both the current sourcing and sinking directions.
'
U
r----
.... 1-":: Ir'
9
200'C
JA"
r'\..
SOD
:i!
ili0;
Quiescent Current vs Input
Voltage
--w-
100
50
75
100
125
0
ISO
IS
20
25
3D
Q
.........
1-+--1--+--+--+--+--1
35
-25
25
50
75
100 125
13V::; VIN '$ 30V
TA • +125'J_..\
..~
E
TA" +Z5 C
Y
~
TA'-55'C,~
",.!;
I I I
....
0
CASE TEMPERATURE ('CI
10
CL -IOpF
~
CL '0.01 ,F
~
\
i\'~
~
~ -SOD
~
-0.2
12
I I I
LL
1""-1 I
It-
"
"
0.1
s:
Output Short Circuit
Characteristics
I I I
500
"
;:z
I
10
~ -SOD
~
Q
INPUT VOLTAGE (VI
1::
'"~
1-+--1-+--+-+-+-1
~e -0.1
Step Load Response
SOD
0.2
!;!!
f
LI
AMBIENT TEMPERATURE ('CI
~
i!i
~
~~
/'
25
~
""
ffi~
" '\
f
_r-
IF-
r\.
~ 200
....-
0.3
~
i"""' J...--
Q
Q
Normalized Output Voltage
vs Temperature
r-""T'"--,-,--,.--r--r--.
1\\ \
\\ \
DELTA CURRENT' 5 m A H +
PULSE WIDTH' 2 pi
10
IS
20
25
30
OUTPUT CURRENT (mAl
TL/H/5550-2
Noise Voltage
VERT:
10?!V
DiY.'
HORIZ:~
DIV.
BW"O.1HzT010Hz
TL/H/5550-6
Typical Applications (Continued)
Expanded Scale AC Voltmeter
1N400.
140-1BOVPEAK
NOMINAL
l1JV,ms
10"F
AC LINE
ZOOV
II
"
.........-'II..,..-.S,DOV CAL
3.
TL/H/5550-4
7-9
Typical Applications (Continued)
Dual Output Bench Power Supply
+--.---------~------~------~------------~
2J-lZVOC
AAWINPUT
...
r-~~~----~~------+_------+_----~~~~Tl
Precision Process Control Interface
,---------------------1----...------+
4-Z0mA\
INPUT ~
1SV
n
VOUT' IOV FOR ZD mA
IIVFDA4mA
lOOk
+-----04- -IS.
100k
le9k
I •. a.
....."""~---------+
".~-Vli'Y-ZERO
'"
Boosted Reference For
Low Input Voltages
Negative 10V Reference
0--1"",",--..,..-0 +12V
5Bon
r--<~-oVOUT
t----OVOUT
-15V
TL/H/5550-5
7-10
_
r:s::::
.....
National
Semiconductor
Corporation
<:)
Co)
LM103 Reference Diode**
General Description
• Performance guaranteed over full military temperature
range
• Planar, passivated junctions for stable operation
• Low capacitance.
The LM103, packaged in a hermetically sealed, modified
TO-46 header is useful in a wide range of circuit applications
from level shifting to simple voltage regulation. It can also
be employed with operational amplifiers in producing breakpoints to generate nonlinear transfer functions. Finally, its
unique characteristics recommend it as a reference element
in low voltage power supplies with input voltages down to
4V.
The LM103 is a two-terminal monolithic reference diode
electrically equivalent to a breakdown diode. The device
makes use of the reverse punch-through of double-diffused
transistors, combined with active circuitry, to produce a
breakdown characteristic which is ten times sharper than
single-junction zener diodes at low voltages. Breakdown
voltages from 3.0V to 3.9V are available; and, although the
design is optimized for operation between 100 ",A and 1
mA, it is completely specified from 10 ",A to 10 mA.
Features
• Exceptionally sharp breakdown
• Low dynamic impedance from 10 ",A to 10 mA
Schematic and Connection Diagrams
+
Metal Can Package
AI
10K
RECOMMEND
R NEW DESIGt.l.S'.:"~'dto . . .
LI-........---4-~ -SEE LM 185
TOP VIEW
T
H/6170-2
OrderNumberLM103H-3.0,
LM103H·3.3, LM103H·3.6
or LM103H·3.9
See NS Package H02A
TL/H/6170-1
Typical Applications
200 mA Positive Regulator
Saturating Servo Preamplifier
with Rate Feedback
r---------.-....
-~~--
R7
•••
Y1,.>5.5V
...----1~--
DZ
VOUy - IV
2M3954
·Solid tantalum
tSelect for minimum
temperature drift,
OUTPUT
if necessary
O.
C2
3DpF
UIID3
UV
+
••
22.
CI'
tZflF
'3
'&2
TL/H/6170-3
.%
TL/H/6170-4
"Covered by U.S. Patent Number 3,571.630
7-11
- rij
;;;
LM 113/LM313 Reference Diode
~.---------------------------------------------------------------~
C ")
~
National
Semiconductor
Corporation
~
General Description
The LM113/LM313 are temperature compensated, low voltage reference diodes. They feature extremely-tight regulation over a wide range of operating currents in addition to an
unusually-low breakdown voltage and good temperature
stability.
• Dynamic impedance of 0.30 from 500 p.A to 20 mA
• Temperature stability typically 1% over-55·C to 125·C
range (LM113),
to 70·C (LM313)
• Tight tolerance: ±5%. ±2% or ±1%
The characteristics of this reference recommend it for use in
bias-regulation circuitry, in low-voltage power supplies or in
battery powered equipment. The fact that the breakdown
voltage is equal to a physical property of silicon-the energy-band gap voltage-makes it useful for many temperature-compensation and temperature-measurement functions.
o·e
The diodes are synthesized using transistors and resistors
in a monolithic integrated circuit. As such, they have the
same low noise and long term stability as modern IC op
amps. Further, output voltage of the reference depends only
on highly-predictable properties of components in the IC; so
they can be manufactured and supplied to tight tolerances.
Features
• Low breakdown voltage: 1.220V
Schematic and Connection Diagrams
Metal Can Package
.,
UK
.,
'D"'O
Nate: Pi"Z eennectn 10 Clse.
TOP VIEW
'"
Order Number LM113H or
LM113-1H or LM113·2H or LM313H
See NS Package Number H02A
Q'
TUH/5713-1
Typical Applications
Low Voltage Regulator
Level Detector for Photodiode
,----4--t- ."
.
..
ZNZ905
50
TTL
OUTPUT
"
lM31l
IZV
...,....••
.....-vou,·zv
>Nv+~--
11.311.
1.111.
1%
cz,
,",
TL/H/5713-2
7-12
r-
:s::
....
Absolute Maximum Ratings
....
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(Note 3)
Power Dissipation (Note 1)
100mW
Reverse Current
50mA
Forward Current
Storage Temperature Range
-65'Cto +150'C
c.:I
.......
300'C
:s::
c.:I
Lead Temperature
(Soldering. 10 seconds)
Operating Temperature Range
LM113
LM313
r-
....
c.:I
-55'Cto+ 125'C
O'Cto +70'C
50mA
Electrical Characteristics (Note 2)
Parameter
Min
Typ
Max
Units
1.160
1.210
1.195
1.220
1.22
1.22
1.280
1.232
1.245
V
V
V
6.0
15
mV
= 1 mA
= 10mA
0.2
0.25
1.0
0.8
0.
0.
= 1.0 mA
0.67
1.0
V
Conditions
Reverse Breakdown Voltage
LMl13/LM313
LMl13-1
LMl13-2
IR
Reverse Breakdown Voltage
Change
0.5 mA ,;; IR ,;; 20 mA
Reverse Dynamic Impedance
IR
IR
Forward Voltage Drop
IF
RMS Noise Voltage
10Hz';; f,;; 10kHz
IR = 1 mA
Reverse Breakdown Voltage
Change with Current
0.5 mA ,;; IR ,;; 10 mA
TMIN ,;; TA';; TMAX
Breakdown Voltage Temperature
Coefficient
1.0 mA ,;; IR ,;; 10 mA
TMIN ,;; TA ,;; TMAX
= 1 mA
jJ-V
5
mV
15
0.01
%rC
Note 1: For operating at elevated temperatures, the device must be derated based on a 150"C maximum junction and a thermal resistance of 80°C/W junction to
case or 440"C/W junction to ambient.
Note 2: These specifications apply for T A = 25°C, unless stated otherwise. At high currents. breakdown voltage should be measured with lead lengths less than 114
inch. Kelvin contact sockets are also recommended. The diode should not be operated with shunt capacitances between 200 pF and 0.1 J-tF, unless isolated by at
least a 100n resistor, as it may oscillate at some currents.
Note 3: Refer to the following RETS drawings for military specifications: RETSI13-1X for LMI13-1. RETSI13-2X for LM113·2 or RETS113X for LM113.
Typical Performance Characteristics
Temperature Drift
..~
~ 1.230
t-t-t-t-t--t--+-+--t-;
§: 1.220
I-r
.....
-::b;;oj.-I--t-t-l-.....,.,.j
~
ffi
~~~-r-r-+-+-+~~-1
~ 1.210
t-t-t-t-t-t-t--t--t--l
>
Reverse Dynamic Impedance
Reverse Characteristics
21-++ttitl---++H.ii/ffi'--H
1.200 ~.I.-.l.-.l.-.l.--'---'--..l--'-...J
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE {' C)
REVERSE CURRENT ImA)
REVERSE CURRENT {mAl
TLlH/5713-3
7-13
II
.... r---------------------------------------------------------------------------------,
~
~
:&
Typical Performance Characteristics (Continued)
-'
c;;
....
....
Reverse Characteristics
Reverse Dynamic Impedance
lit'
100
:&
-'
'"...""
z
"~
.
u
~
liMI Vj
ZioC
111"
0.2
0.4
o.a
~OCI
10
.!-4t--_ 6.9 ::; VOUT ::; 6.9
LM129
50k>o....--......;:.t
6.9V
-15V
30 pF
570
TLiH/5714-B
150
-10V
TL/H/5714-7
OV to 20V Power Reference
25vTo4ov'---.---------_________~----------__,
LMI9Sk
LM129
6.9V
•~--t---~-JV~~----t_--OVT020V
lA
lk
-SV
TL/H/5714-9
External Reference for Temperature Transducer
15V
lk
OUTPUT
LMI29
6.9V
OUTPUT
} 10mV/oK
fI
lM3911H-46
INPUT
IN457
TL/H/5714-2
7-17
Typical Applications
(Continued)
PosItIve Current Source
lDVTO 4DV'-....- -....-
_ _ _ _- ._ _ _ _ _..,
2Dk
0.1%
LM129
B.9V
2Dk
0.1%
4.30
TLlH/5714-11
Buffered Reference wIth SIngle Supply
+15V-t---------,
9k
7.5k
>~~-lDV
LM129
6.9V
TLlH/5714-3
Schematic Diagram
03
6.3V
30 pF
10k
2k
30k
~------~--~--------~~------------~--_i2
7-18
-
TLlH/5714-10
Typical Performance Characteristics
Reverse Characteristics
10-'
Response Time
Forward Characteristics
r---.--,--.,....-r---.---,
1.2
OUTPUT
~
10-2
I---+-+-+--HH---I
,.
3 10-
JTj 2S'C- I---
j!
0
.. ..-
'"z
3
~
1---+-+-
/
1
'"
~
~ 10~ I---+~~~~~F---+---I
6.75
6.85
6.9S
~>
I---
UK
I
INPUT
I--I---
::::I.
~ OUTPUT r-.!-......J. I---
20
10
INPUT- I---
7.0S
100
REVERSE VOLTAGE IVI
200
300
j!
~
~
>
,."
~
~
Dynamic Impedance
ODD
0.01
Tj'~SS'C
..
::l
r---
TI'12S'C
1.0
~
~
/.
10
!u
0.1
10
FORWARD CURRENT ImAI
Zener Noise Voltage
ISO
w
"ill
0.0
0.2
Reverse Voltage Change
:;
z
0.8
0.6
TIME ($oIs)
100
u
1.0
w
Tj
/.y\
~
Tj: -5S'C
--
=Tj'2S'C
10
100
lk
FREQUENCV IH,)
10k
lOOk
@
~
100
~'2S'C
w
~
-
".
o
0.1
O
~
~2S'CI2S;a:;
./
o
10
SO
10
REVERSE CURRENT (mA)
100
lk
10k
lOOk
FREQUENCY (Hz)
TL1H/5714-12
Low Frequency Noise Voltage
0.01 HlstSl Hl
10
TIME 1M IN UTES)
TLlH/5714-5
fI
7-19
~
(W)
(W)
r----------------------------------------------------------------------------,
NatiOnal
-I
~ Semiconductor
....
Corporation
:E
~
(W)
N
:E
.... LM 134/LM234/LM334
-I
~
(W)
.,...
:E
-I
3-Terminal Adjustable Current Sources
General Description
The LM134/LM234/LM334 are 3-terminal adjustable current sources featuring 10,000:1 range in operating current,
excellent current regulation and a wide dynamic voltage
range of 1V to 40V. Current is established with one external
resistor and no other parts are required. Initial current accuracy is ±3%. The LM134/LM234/LM334 are true floating
current sources with no separate power supply connections.
In addition, reverse applied voltages of up to 20V will draw
only a few dozen microamperes of current, allowing the devices to act as both a rectifier and current source in AC
applications.
LM234-3 and LM134-6/LM234-6 are specified as true temperature sensors with guaranteed initial accuracy of ± SOC
and ±6·C, respectively. These devices are ideal in remote
sense applications because series resistance in long wire
runs does not affect accuracy. In addition, only 2 wires are
required.
The LM134 is guaranteed over a temperature range of
- 55·C to + 125·C, the LM234 from - 25·C to + 1000C and
the LM334 from O·C to + 70·C. These devices are available
in TO-46 hermetic, TO-92 and 80-8 plastic packages.
The sense voltage used to establish operating current in the
LM134 is 64 mV at 25·C and is directly proportional to absolute temperature rK). The simplest one external resistor
connection, then, generates a current with z +0.33%I"C
temperature dependence. Zero drift operation can be obtained by adding one extra resistor and a diode.
Applications for the new current sources include bias networks, surge protection, low power reference, ramp generation, LED driver, and temperature sensing. The LM134-31
•
•
•
•
•
•
Features
Operates from tV to 40V
0.02%1V current regulation
Programmable from 1 IJ-A to 10 mA
True 2-terminal operation
Available as fully specified temperature sensor
±3% initial accuracy
Connection Diagrams
SO-8
Surface Mount Package
TO-46
Metal Can Package
TO-92
Plastic Package
o
v+
y+
-Or
R
V-
TUH/5697-10
Bottom View
TL/H/5697 -12
Bottom View
Pin 3 is electrically connected to case.
TLlH/5697 -24
Order Number LM334M
See NS Package Number M08A
Order Number LM134H, LM134H-3,
LM134H-6, LM234H, LM234H-3,
LM234H-6, or LM334H
See NS Package Number H03H
Order Number LM334Z, LM234Z-3
orLM234Z-6
See NS Package Number Z03A
Typical Application
Basic 2-Terminal Current Source
+YIN
Iv'
a.
'-l
R
RSET
Y-
TL/H/5697-1
7-20
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V+ to V- Forward Voltage
LM134/LM234
40V
LM334/LM134-3/LM134-6/LM234-3/LM234-6
30V
V+ to V- Reverse Voltage
20V
R Pin to V- Voltage
Operating Temperature Range (Note 4)
LM134/LM134-3/LM134-6
-55·Cto +125·C
-25·C to + 100·C
LM234/LM234-3/ LM234-6
O·Cto +70·C
LM334
Soldering Information
260·C
TO-92 Package (10 sec.)
300·C
TO-46 Package (10 sec.)
SO Package
215·C
Vapor Phase (60 sec.)
220·C
Infrared (15 sec.)
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" (Appendix D) for other methods of
soldering surface mount devices.
5V
Set Current
10mA
Power Dissipation
400mW
Electrical Characteristics (Note 1)
Parameter
Min
Set Current Error, V + = 2.5V,
(Note 2)
10 ",AS:ISETS:1 mA
1 mA
..'"
.§
~
..
~
>
10k
18
14
IL
/
10
I-
62
64
,.
;:::'SET" 5mA
!
66
58
~
i
V
/
r'SET" ImA
100
r'SET" 100,,",
10
I='SET·IO"A
Lli
50
45
-50 -25
I
0
25
50
15
TEMPERATURE I'C)
100 125
10
100
,.
10k
lOOk
FREQUENCY 1Hz)
TUH15697-2
7-22
Typical Performance Characteristics (Continued)
Ratio of ISET to V- Current
Turn-On Voltage
IOmA
20
I - _ I -__""/P!:....--+-RSE~· 14n
ImA
...
RSET= 6Bn-
.;
I--H'~+--RS~T = 6&Jn-
100pA
18
<>
;::
~=a~/:t~~~~~~
16
"''"
I--J~-+RSET ~ 6.Bk - -
1/
~
'\
14
,II
0.4
\
1\
10llA
lpA
\
12
0.6
0.&
1.0
1.2
10pA
1.4
100pA
Y+TOY-YOLTAGE
ImA
IOmA
ISET
TL/H/5697-3
Application Hints
The LM134 has been designed for ease of application, but a
general discussion of design features is presented here to
familiarize the designer with device characteristics which
may not be immediately obvious. These include the effects
of slewing, power dissipation, capacitance, noise, and contact resistance.
will be increased by about 12 dB. In many cases, this is
acceptable and a single stage amplifier can be built with a
voltage gain exceeding 2000.
LEAD RESISTANCE
The sense voltage which determines operating current of
the LM134 is less than 100 mV. At this level, thermocouple
or lead resistance effects should be minimized by locating
the current setting resistor physically close to the device.
Sockets should be avoided if possible. It takes only 0.70.
contact resistance to reduce output current by 1 % at the
1 mA level.
SLEW RATE
At slew rates above a given threshold (see curve), the
LM134 may exhibit non-linear current shifts. The slewing
rate at which this occurs is directly proportional to ISET. At
ISET=10 p.A, maximum dV/dt is O.01V/p.s; at ISET=1 mA,
the limit is 1VI p.s. Slew rates above the limit do not harm
the LM134, or cause large currents to flow.
SENSING TEMPERATURE
The LM134 makes an ideal remote temperature sensor because its current mode operation does not lose accuracy
over long wire runs. Output current is directly proportional to
absolute temperature in degrees Kelvin, according to the
following formula:
THERMAL EFFECTS
Internal heating can have a significant effect on current regulation for ISET greater than 100 p.A. For example, each 1V
increase across the LM134 at ISET=1 mA will increase
junction temperature by ::::: OA'C in still air. Output current
(ISET) has a temperature coefficient of ::::: 0.33%/'C, so the
change in current due to temperature rise will be (004)
(0.33)=0.132%. This is a 10:1 degradation in regulation
compared to true electrical effects. Thermal effects, therefore, must be taken into account when DC regulation is critical and ISET exceeds 100 p.A. Heat sinking of the TO-46
package or the TO-92 leads can reduce this effect by more
than 3:1.
(2_27-:p.::-V_I'_K",,)(T)....:.
.:....
RSET
Calibration of the LM1.34 is greatly simplified because of the
fact that most of the initial inaccuracy is due to a gain term
(slope error) and not an offset. This means that a calibration
consisting of a gain adjustment only will trim both slope and
zero at the same time. In addition, gain adjustment is a one
point trim because the output of the LM134 extrapolates to
zero at O'K, independent of RSET or any initial inaccuracy.
ISET=
SHUNT CAPACITANCE
In certain applications, the 15 pF shunt capacitance of the
LM134 may have to be reduced, either because of loading
problems or because it limits the AC output impedance of
the current source. This can be easily accomplished by buffering the LM134 with an FET as shown in the applications.
This can reduce capacitance to less than 3 pF and improve
regulation by at least an order of magnitude. DC characteristics (with the exception of minimum input voltage), are not
affected.
INITIAL OUTPUT I
I
I
I
I
I
I
ISET
t
I
I
I
I'
NOISE
OOK
Current noise generated by the LM134 is approximately 4
times the shot noise of a transistor. If the LM134 is used as
an active load for a transistor amplifier, input referred noise
lb'
I
I
I
1
1
1
I
I
I
Tl
T2
I
I
I
"
DESIRED
OUTPUT
I
I
I
1
I
I
T3
TLlH/5697-4
This property of the LM134 is illustrated in the accompanying graph. Line abc is the sensor current before trimming.
7-23
~ .---------------------------------------------------------------------------------~
C')
C')
!l
~
C')
('II
::::i!i
....I
;;r
.,..
C')
::::i!i
....I
Application Hints (Continued)
Line a'b'c' is the desired output. A gain trim done at T2 will
move the output from b to b' and will simultaneously correct
the slope so that the output at T1 and T3 will be correct.
This gain trim can be done on RSET or on the load resistor
used to terminate the LM 134. Slope error after trim will normally be less than ± 1 %. To maintain this accuracy, however, a low temperature coefficient resistor must be used for
A 33 ppml"C drift of RSET will give a 1% slope error be-
cause the resistor will normally see about the same temperature variations as the LM134. Separating RSET from the
LM134 requires 3 wires and has lead resistance problems,
so is not normally recommended. Metal film resistors with
less than 20 ppml"C drift are readily available. Wire wound
resistors may also be used where best stability is required .
RSET·
Typical Applications (Continued)
Zero Temperature Coefficient Current Source
Terminating Remote Sensor for Voltage Output
+VIN
R
r
Rl*
..10 RSET
RL
TL/H/5697 -13
VOUT - (lSET)(RLI
" 10mvrK FOR
RSET c 230n
RL '10 kn
'Select ratio of Rl to RSET to obtain zero drift. 1+ :::: 21SET
TLlH/5697-14
Low Output Impedance Thermometer
Ground Referred Fahrenheit Thermometer
VIN~4.8V
R4
56k
r--'\IV\,.......- - - - - - - - +VIN ~3V
R3*
)CI(+-j~~.....ltJ60Vo\t-_
Rl
230
1%
t-~~-------- VOUT" 10 mVrF
10°FS;TS;260'F
Rl
8.25k
1%
+VREF
VOUT -10 mvrK
ZOUTS;10on
R2
10k
1%
Cl
LM336Z
2.5V*
TL/H/5697-6
'Output Impedance of the LM134 at the "ROO pin Is
TL/H/5697-15
approximately -
'Select R3 = VREF/583 ,.A. VREF may be any stable positive voltage "?2V
Trim R3 to calibrate
~~n
where Ro Is the equivalent
external resistance connected to the V- pin. This
negative resistance can be reduced by a factor of 5
or more by inserting an equivalent resistor in series
with the output.
7-24
,-----------------------------------------------------------------------------, r
is:
Typical Applications
....
(Continued)
CAl
Low Output Impedance Thermometer
~
.....
r
Higher Output Current
is:
+YIN
+VIN - -....- - - . . . . . ,
N
CAl
~
.....
~
CAl
CAl
RI*
CI
0.0022
)0(4--+.;;...-4.....-
VOUT= 10mVfK
ZOUT$ZU
~
R
RSET
TL/H/5697-5
'Select Rl and Cl for optimum stability
TLlH/5697-16
Micropower Bias
+VIN
Low Input Voltage Reference Driver
+VIN;:: VREF + 200 mV - _....- - - - - . . . . ,
VOUT = Vz + 64 mV!ilI 25'C
IOUT~3 mA
-VIN
TL/H/5697-17
TL/H/5697-18
Ramp Generator
+VIN
"'---+-VOUT
RESETJL
TL/H/5697-19
7-25
~
~
~
==
....
....
~
~
N
r------------------------------------------------------------------------------------------,
Typical Applications
(Continued)
1.2V Reference Operates on 10 p,A and 2V
VIN~1.8V
....
....==
~
~
....
:5
1.2V Regulator with 1.8V Minimum Input
+VIN~2V
R3
Uk
R
)a*-+';';"-4I~""''V\'''''-- VOUT = 1.2V
lOUT :;;hA
R2*
Uk
1%
lN451
TL/H/5697-20
'Select ratio of RI to R2 to obtain zero temperature drift
TLlH/5697 -7
'Select ratio of RI to R2 for zero temperature drift
Zener Biasing
Alternate Trimming Technique
Buffer for Photoconductive Cell
R
1.5V
RSET
"'--~""-VOUT
TLlH/5697-8
'For ± 10% adjustment, select RSET
10% high, and make RI :::: 3 RSET
FET Cascoding for Low CapaCitance and/or Ultra High Output Impedance
+VIN
R
v-
RSEl
TLlH/5697 -21
TL/H/5697 -22
'Select 01 or 02 to ensure al least IV across the LM134. Vp (I - ISET"oss);" 1.2V.
7·26
Typical Applications
(Continued)
Generating Negative Output Impedance
In-Line Current Limiter
+vIN
RSET
R
Rl*
RSET
TL/H/5697-23
'ZoUT :::: -16 • R1 (R11V1N must not exceed ISET)
TlIH/5697-9
·Use minimum value required to ensure stability of protected device. This
minimizes inrush current to a direct short.
Schematic Diagram
~------~--------------v-
TlIH/5697-11
II
7-27
~
N
ch
('I)
('I)
:i
..J
.....
r----------------------------------------------------------------------------,
~ Semiconductor
NatiOnal
Corporation
~
~
LM 136-2.5/LM236-2.5/LM336-2.5V Reference Diode
iii
The LM136-2.5/LM236-2.5 and LM336-2.5 integrated circuits are precision 2.5V shunt regulator diodes. These
monolithic IC voltage references operate as a low-temperature-coefficient 2.5V zener with 0.2,n dynamic impedance. A
third terminal on the LM136-2.5 allows the reference voltage and temperature coefficient to be trimmed easily.
N
:;
N
ch
('I)
:i
..J
General Description
The LM136-2.5 series is useful as a precision 2.5V low voltage reference for digital voltmeters, power supplies or op
amp circuitry. The 2.5V make it convenient to obtain a stable reference from 5V logic supplies. Further, since the
LM136-2.5 operates as a shunt regulator, it can be used as
either a positive or negative voltage reference.
The LM136-2.5 is rated for operation over -55·C to
+ 125·C while the LM236-2.5 is rated over a - 25·C to
+ 85·C temperature range.
Both are packaged in a TO-46 package. The LM336-2.5 is
rated for operation over a O·C to + 70·C temperature range
and is available in a TO-92 plastic package.
Features
• Low temperature coefficient
• Wide operating current of 400 p.A to 10 mA
• 0.2,n dynamic impedance
• ± 1 % initial tolerance available
• Guaranteed temperature stability
• Easily trimmed for minimum temperature drift
• Fast turn-on
• Three lead transistor package
Connection Diagrams
TO-92
Plastic Package
TO-46
Metal Can Package
SO Package
+
NC
NC
NC
NC
ADJ
8
TL/H/5715-8
Bottom View
TL/H/5715-20
Order Number LM336Z-2.5
or LM336BZ-2.5
See NS Package Number Z03A
3
Bottom View
NC
Order Number LM136H-2.5,
LM236H-2.5, LM336H-2.5,
LM136AH-2.5 or LM236AH-2.5
See NS Package Number H03H
4
TLlH/5715-12
Top View
Order Number LM336M-2.5
or LM336BM-2.5
See NS Package Number M08A
Typical Applications
2.5V Reference with Minimum
Temperature Coefficient
2.5V Reference
sv
Wide Input Range Reference
sv
VIN 3.S - 40V
IN4S7*
.....- ....- - vour' 2.SV
lM336·2.S
._......,~
TL/H/5715-9
IN457*
t Adjust to 2.490V
• Any silicon signal diode
-=-
TLlH/5715-10
7-28
TL/H/5715-11
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Reverse Current
15mA
Forward Current
Storage Temperature
Operating Temperature Range
LM136
LM236
LM336
Soldering Information
TO-92 Package (10 sec.)
260'C
TO-46 Package (10 sec.)
300'C
SO Package
Vapor Phase (60 sec.)
215'C
Infrared (15 sec.)
220'C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" (Appendix D) for other methods of
soldering surface mount devices.
10mA
-60'Cto + 150'C
- 55'C to + 150'C
- 25'C to + 85'C
O'Cto +70'C
Electrical Characteristics (Note 1)
Parameter
LM136A-2.S/LM236A-2.S
LM136-2.S/LM236-2.5
Conditions
Reverse Breakdown Voltage
TA=25'C,IR=1 mA
LM136/LM236/LM336
LM136A1LM236A, LM336B
LM336B-2.S
LM336-2.5
Units
Min
Typ
Max
Min
Typ
Max
2.440
2.465
2.490
2.490
2.540
2.515
2.390
2.440
2.490
2.490
2.590
2.540
V
V
Reverse Breakdown Change
With Current
TA=25'C,
400 ILAS:IRS:10 mA
2.6
6
2.6
10
mV
Reverse Dynamic Impedance
TA=25'C, IR=1 mA
0.2
0.6
0.2
1
n
Temperature Stability
(Note 2)
VR Adjusted to 2.490V
IR = 1 mA, (Figure 2)
0'CS:TAS:70'C (LM336)
-25'CS:TAS: +85'C (LM236)
-55'CS:TAS: + 125'C (LM136)
1.8
6
3.5
12
9
18
mV
mV
mV
3
10
3
12
mV
1
0.4
1.4
Reverse Breakdown Change
With Current
400 ILAS:IRS:10 mA
Reverse Dynamic Impedance
IR=1 mA
0.4
Long Term Stability
TA=25'C ±0.1·C, IR=1 mA
20
n
ppm
20
Note 1: Unless otherwise specified, the LM 136·2.5 is specified from - 55'C ,; TA ,; + t 25'C, the LM236-2.5 from - 25'C ,; TA ,; + 85'C and the LM336-2.5 from
O'C ,; TA ,; +70·C.
Note 2: Temperature stability for the LM336 and LM236 family is guaranteed by design. Design limits are guaranteed (but not 100% production lested) over the
indicated temperature and supply voltage ranges. These limits are not used to calculate outgoing quality levels. Stability is defined as the maximum change in Vref
from 25'C to TA (min) or TA (max).
Note 3: For elevated temperature operation. Tj max is:
LMt36
t50"C
LM236
125'C
LM336
100'C
Thermal Resistance
TO-92
TO-46
SO-8
6ja (Junction to Ambient)
180"C/W (0.4" leads)
17O"C/W (0.125" lead)
44O"C/W
165'C/W
n/a
80'C/W
n/a
910 (Junction to Case)
Typical Performance Characteristics
Reverse Voltage Change
Dynamic Impedance
Zener Noise Voltage
3.S
ZSD
3.0
Tj "12S'C
2.5
~
/. V
Z
~
I.S
~
1.0
O.S . /
~j.-SS·C
~
I
Tj"Z5'C_
I
~
!
w
100
'R"'lmA
TI·ZS·C -
zoo \
~
'R-lmA
150
Tj:~~S'C,~
"-
M
~
2
~
1
100
Tj" -5S'C
Tj'ZS'C-
50
0
0
I
10
\
4
B
B
REVERSE CURRENT ImAI
10
10
100
1k
10k
FREQUENCY 1Hz)
0.1
lOOk
10
100
lk
10k
lOOk
FREQUENCY (Hz)
TL/H/5715-2
7-29
fI
Ln
~
r---------------------------------------------------------------------------------,
Typical Performance Characteristics
(Continued)
CO)
::E
Response Time
..J
......
-tl
II!
3
CD
Z-~r
~
CO)
-~.J
C'I
IDU!rU!
Reverse Characteristics
I
. : ,..
;;::r:-t--+--t--I
l ~"DUl'UT-+-I-H
::E
I -
......
Ln
o --
~
,..
o H'-+I tII''1NP!,,-UT'I-t--J
tr I H - r - l
~ j J I I
..J
N
~
5
-
Forward Characteristics
1.2,--....--,---,---,
....T
I
I
I
I
1---t----t----t--7~~
1--+---:b_~~<......J
0.&
r-- Tj"-W:-
.... //
. . " . //
OA~ /V
0.2
~125'C-r--I
I
4
1.0
0.1
I
0L-_..L...._...l...._...l..._...J
2.B
•
0.001
TlMEC.sl
O.Dl
0.1
11
FORWARD CURRENT ImAI
Temperature Drift
s:
2.590
2.510
2.&&0
;;; 2.530
~ 2.S10
r::::~bJ:~~~I==j::j
I..... - -
....
"""F....
'-::b,...-+--+--+--+--+--l
1"'....
'1::1'"'";;;1..-+--+-+--+-+-....;;;1
~ !::~: I-r-"-+-+-t--t-+"",,-t;=t---j
iii 2.450 I-t-t-t-I-k!::_:+:--'F"'I
~ 2.430
~
2.418
~~~~~~~~ki
F
~ ......
-,....
2.390 IRI" I ~A +-+-+-PNt-I'--o'
2.310
-55 -35 -15 5 2& 45 65 15 IDS 12&
TEMPERATURE I'CI
TLlH/5715-3
Application Hints
The LM136 series voltage references are much easier to
use than ordinary zener diodes. Their low impedance and
wide operating current range simplify biasing in almost any
circuil. Further, either the breakdown voltage or the temperature coefficient can be adjusted to optimize circuit performance.
Figure 1 shows an LM136 with a 10k potentiometer for adjusting the reverse breakdown voltage. With the addition of
R1 the breakdown voltage can be adjusted without affecting
the temperature coefficient of the device. The adjustment
range is usually sufficient to adjust for both the initial device
tolerance and inaccuracies in buffer circuitry.
If minimum temperature coefficient is desired, two diodes
can be added in series with the adjustment potentiometer
as shown in Figure 2. When the device is adjusted to 2.490V
the temperature coefficient is minimized. Almost any silicon
signal diode can be used for this purpose such as a 1N914,
1N4148 or a 1N457. For proper temperature compensation
the diodes should be in the same thermal environment as
the LM136. It is usually sufficient to mount the diodes near
the LM 136 on the printed circuit board. The absolute resistance of Rl is not critical and any value from 2k to 20k will
work.
y+
Rs
y+
~ ~IN914
TL/H/5716-4
FIGURE 1. LM136 With Pot for Adjustment
of Breakdown Voltage
(Trim Range = ± 120 mV typical)
FIGURE 2. Temperature Coefficient Adjustment
(Trim Range = ±70 mV typical)
7-30
Typical Applications (Continued)
Low Cost 2 Amp Switching Regulator t
VIN
6V TO 20V - .....- .....---.....:;l.:
r--.....-1~------~I-~~.~Ll~~.....- -.....-VOUT
5V
600/-oH
+
+
VARO
VSK3JO
620
390
TL/H/5715-5
'L 1 60 turns # 16 wire on Arnold Core A-254168-2
tEfficiency :::: 80%
Precision Power Regulator with Low Temperature Coefficient
~-~~------1~VOUT
RI
315
IN451
.2
2k
OUTPUT
ADJUST
'Adjust for 3.75V across Rl
-=
TL/H/5715-13
Trimmed 2.5V Reference with Temperature
Coefficient Independent of Breakdown Voltage
5VCrowbar
V·-------t-------t-------
10V
5k
100
O.Ol#-lf
SENSITIVE GATE
seR
-==-
200
'Does not affect temperature coefficient
TUH/5715-14
7-31
TUH/57t 5-15
II
~ ~----------------------------------------------------------------------------,
~
Typical Applications (Continued)
C")
~
~
Adjustable Shunt Regulator
RS
6VT040V--~Ar~~------~~--------------t--~~V~~V
~
~
;t;
~,..
::E
....I
TLlH/5715-6
Linear Ohmmeter
y+
3Ii
Uk
'"
'Ok
CALIBRATE
>--+-VOUT
TL/H/5715-16
7-32
Typical Applications (Continued)
Op Amp with Output Clamped
Bipolar Output Reference
5V
RF
10k
2k
1%
'1.25V
.....-J"",..,..-OV·
10k
1%
TUH/5715-17
5k
-5V
TL/H/5715-1B
2.5V Square Wave calibrator
5V
_ - - -. .- - -. .- - OUTPUT
A:---+< CALIBRATE
TLlH/5715-19
II
7-33
U)
~
r---------------------------------------------------------------------------------,
Typical Applications
Cf)
:E
....
(Continued)
5V Buffered Reference
Low Noise Buffered Reference
....I
U)
~
5V
IV ~VIN ~3BV -
....----:20:"".-'
1%
C'I
2.2k
:E
.....
....I
U)
IV
~
Cf)
.,...
:E
....I
2.IV
10k
CAL
10k
CAL
TL/H/5715-7
Schematic Diagram
~---------------~~~---.-----------.-~------+
Rl
5Dk
R5
24k
R6
24k
R7
6.6.
Cl
30pF
RB
600
ADJ
R9
3Dk
RID
6.6k
R2
2k
R3
Uk
TLlH/5715-1
7-34
r------------------------------------------------------------------------, ;:
r
...
NatiOnal
~ Semiconductor
Co)
C)
·
Corporation
CI1
Q
......
LM 136-5.0/LM236-5.0/lM336-5.0, 5.0V Reference Diode
The LM136-S.0 series is useful as a precision S.OV low voltage reference for digital voltmeters, power supplies or op
amp circuitry. The S.OV makes it convenient to obtain a stable reference from low voltage supplies. Further, since the
LM136-S.0 operates as a shunt regulator, it can be used as
either a positive or negative voltage reference.
The LM136-S.0 is rated for operation over -SS'C to
+ 125'C while the LM236-S.0 is rated over a - 2S'C to
+ B5'C temperature range. Both are packaged in a TO-46
package. The LM336-S.0 is rated for operation over a O'C to
+ 70'C temperature range and is available in a TO-92 plastic package. For applications requiring 2.SV see LM136-2.S.
features
•
•
•
•
Co)
C)
·
•
•
•
III
III
TO-92
Plastic Package
TO-46
Metal Can Package
SO Package
+
NC
NC
NC
NC
ADJ
TL/H/5716-4
TL/H/5716-5
NC
Bottom View
Order Number LM136H-S_O,
LM236H-S_O, LM136AH-S_O or
LM236AH-S_O
See NS Package Number H03H
"
TL/H/5716-7
Order Number LM336M-S_O or
LM236BM-S.O
See NS Package Number H03H
Typical Applications
S.OV Reference with Minimum
Temperature Coefficient
IOV
10V
Trimmed 4V to 6V Reference
with Temperature Coefficient
Independent of Breakdown Voltage
IOV
TL/H/5716-1
LM336-5.0
LM136·5.01
LM336·5.0
IOk*
A--+'< CALIBRATE
t Adlusll0 5.00V
TL/H/5716-3
•Any silicon signal diode
"Does not affect temperature coefficient
':'
TL/H/5716-15
7-3S
r
;:
Co)
Co)
C)
·
CI1
8
Bottom View
Q
......
Q
Adjustable 4V to 6V
Low temperature coefficient
Wide operating current of 600 p.A to 10 mA
0.60 dynamic impedance
± 1% initial tolerance available
Guaranteed temperature stability
Easily trimmed for minimum temperature drift
Fast turn-on
Three lead transistor package
Connection Diagrams
S_OV Reference
N
CI1
General Description
The LM136-S.0/LM236-S.0/LM336-5.0 integrated circuits
are precision S.OV shunt regulator diodes. These monolithic
IC voltage references operate as a low temperature coefficient S.OV zener with 0.60 dynamic impedance. A third terminal on the LM136-S.0 allows the reference voltage and
temperature coefficient to be trimmed easily.
Order Number LM336Z-S.0 or
LM336BZ-S.O
See NS Package Number Z03A
r
;:
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Reverse Current
15mA
Forward Current
10mA
Storage Temperature
-60'Cto + 150"C
Operating Temperature Range
LM136-5.0
- 55'C to + 150'C
LM236-5.0
- 25'C to + 85'C
LM336-5.0
O'Cto +70"C
Soldering Information
TO-92 Package (1 0 sec.)
260"C
TO-46 Package (10 sec.)
300'C
SO Package
215'C
Vapor Phase (60 sec.)
Infrared (15 sec.)
220'C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" (appendix D) for other methods of
soldering surface mount devices.
Electrical Characteristics (Note 1)
Parameter
Reverse Breakdown Voltage
LM136A-S.O/LM236A-S.O
LM136-S.0/LM236-S.0
Conditions
TA=25'C,IR=1 mA
LM136-5.0/LM236-5.0/LM336-5.0
LM136A-5.0/LM236A-5.0, LM336B-5.0
LM336B-S.O
LM336-S.0
Units
Min
Typ
Max
Min
Typ
Max
4.9
4.95
5.00
5.00
5.1
5.05
4.8
4.90
5.00
5.00
5.2
5.1
V
V
Reverse Breakdown Change
With Current
TA=25'C,
600 ,..A05:IR05:10 mA
6
12
6
20
mV
Reverse Dynamic Impedance
TA=25'C,IR=1 mA
0.6
1.2
0.6
2
n
Temperature Stability
VR Adjusted 5.00V
IR = 1 mA, (Figure 2)
O'C05:TA05:70'C (LM336-5.0)
- 25'C 05:TA05: + 85'C (LM236-5.0)
-55'C05:TA05: + 125'C (LM136-5.0)
4
12
7
20
18
36
mV
mV
mV
6
17
6
24
mV
1.6
0.8
2.5
n
Reverse Breakdown Change
With Current
600 ,..A05: IR 05: 10 mA
Adjustment Range
Circuit of Figure 1
±1
Reverse Dynamic Impedance
IR = 1 mA
0.8
±1
V
Long Term Stability
TA=25'C±O.1'C,IR=1 mA
20
20
ppm
Note 1: Unless otherwise specified, the lMI36·S.0 is specified from -SS'C,;TA';+ 12S'C, the lM236·S.0 from -2S'C,;TA'; +8S'C and the lM336-S.0 from
O'C,;TA';+70'C.
Note 2: Temperature stability for the lM336 and LM236 family is guaranteed by design. Design limits are guaranteed (but not 100% percent production tested)
over the indicated temperature and supply voltage ranges. These limits are not used to calculate outgoing quality levels. Stability is defined as the maximum charge
in VREF from 2S'C to TA(min) or TA(max).
Note 3: For elevated temperature operation, TI max is:
lM136
ISO'C
lM236
12S'C
lM336
100'C
Thermal Resistance
TO·92
To-46
SO-8
01. (Junction to Ambient)
180'C/W (0.4" Leads)
170'C/W (0.125" leads)
440'C/W
165'C/W
0i. (Junction to Case)
N/A
80'C/W
N/A
7-36
rE:
....
~
enb
Typical Performance Characteristics
Reverse Voltage Change
Zener Noise Voltage
400
350
~
:s
~
c;
z
Dynamic Impedance
\
300
250
200
='R"mA
TJ o 25'C
1\
£[
Tj'125'C~
w
\
I,
~
100
I
-Tj'25'C_
~z
1--;0'//''Tj= -55'C
>
"
REVERSE CURRENT (mAl
lk
10k
100
FREQUENCY (Hzl
10k
lk
lOOk
FREQUENCY (Hz!
TL/H/5716-2
Reverse Characteristics
1 1 1 1 1 Tj~2~'C
.1 OUTPUT
.
.'"
~1h
~
~
r-r
r- ,....'NPUT "
~
>
--
w
10
0
S
!;;
I
I
I
.----,---r---;-..,..--,
'0-2
1--1--+--+-+...-1
::!
=10-3
~
!>
OUTPUT
-I-j
10-1
I
~ 10-4
'NPUT
1 11 11
1.5
TlME!..1
Temperature Drift
5.080
..
;;;
~ 5.000
"i2> 4.960
4.5
5.5
Forward Characteristics
1.2 ,..--..,-_-,._--,,-----.
J..-r-"
~
I'
~
,....
;-
t--+---+--t-~
r- .....
A
4.840
-55 -35 -15
~
0.8 t--+---I:_""'-I--"oL-j
"~
D.8
i= 0.4
-I"--
'1'7
'.0
w
~ 4.920
4.B8o
3.5
REVERSE VOLTAGE (VI
5.120
:; 5.040
2.5
~
..... ......
5 25 45 &5 B5 105 125
0.2
b_"F0.01
0.1
10
fORWARD CURRENT (mAl
TEMPERATURE eCI
TUH/5716-8
Application Hints
The LM136-5.0 series voltage references are much easier
to use than ordinary zener diodes. Their low impedance and
wide operating current range simplify biasing in almost any
circuil. Further, either the breakdown voltage or the temperature coefficient can be adjusted to optimize circuit performance.
If minimum temperature coefficient is desired, four diodes
can be added in series with the adjustment potentiometer
as shown in Figure 2. When the device is adjusted to 5.00V
the temperature coefficient is minimized. Almost any silicon
signal diode can be used for this purpose such as a 1N914,
1N4148 or a 1N457. For proper temperature compensation
the diodes should be in the same thermal environment as
the LM136-5.0. It is usually sufficient to mount the diodes
near the LM136-5.0 on the printed circuit board. The absolute resistance of the network is not critical and any value
from 2k to 20k will work. Because of the wide adjustment
range, fixed resistors should be connected in series with the
pot to make pot setting less critical.
Figure 1 shows an LM 136-5.0 with a 10k potentiometer for
adjusting the reverse breakdown voltage. With the addition
of R1 the breakdown voltage can be adjusted without affecting the temperature coefficient of the device. The adjustment range is usually sufficient to adjust for both the
initial device tolerance and inaccuracies in buffer circuitry.
7-37
b
.....
rE:
w
w
m
1
10
lOOk
Response Time
N
W
UI
~
u
0.1
10
E:
m
10
150
10
....r-
100
In- 1mA
en
b
Application Hints (Continued)
v,
--+<- ~~k
LMI36·5.0 . .
-
TLiH/5716-9
FIGURE 1. LM136-S.0 with Pot for Adjustment of
Breakdown Voltage (Trim Range = ± 1.0V Typical)
v+
1 mAJ.
RS
lN914
5k
LMI36·5.D
.--+.~ ~~
5k
lN914
_
TLiH/5716-10
FIGURE 2. Temperature Coefficient Adjustment
(Trim Range = ±O.SV Typical)
Typical Applications
(Continued)
Precision Power Regulator with Low Temperature Coefficient
LM317
INPUT
OUT~---__------~--VOUT
Rl
625
• Adjust for 6.25V across RI
7·38
TLiH/5716-11
Typical Applications
(Continued)
5VCrowbar
V+-------4~----~.-------
LMJJ6·5.0
SENSITIVE GATE
SCR
100
200
TLlH/5716-12
Adjustable Shunt Regulator
RS
VIN > 2V + VOUT
-J\f'.~-""--------""--------------,,,- ~~J~~~ov
'::"
TLlH/5716-13
Linear Ohmmeter
LMJ34
30n
5k
1%
50k
1%
O.5M
1%
5M
1%
10k
CALIBRATE
10kIV
lklV
>~"'-VOUT
'::"
TLlH/5716-14
7-39
Typical Applications
(Continued)
Op Amp with Output Clamped
Bipolar Output Reference
IV
I.
10.
1%
2k
dV
LM138·
&,0
±I.IV
"'-'\I'VII-V·
10k
1%
I.
-IV
5.0V Square Wave Calibrator
10V Buffered Reference
,ZV:!iV,N :!i38V-....- - - Z - o . - - .
lDV
1%
2.
~---""--"'-OUTPUT
10V
• .A..--KCALIBRATE
LM138U
10k
CAL
Wide Input Range Reference
Low Noise Buffered Reference
7.IV
Y,N • 7V TO cov
LM334
IV
....-
....--VOUT·6.0V
1Il10
CAL
TL/H/S716-6
7·40
en
n
::J'
CD
3
RI
t 1
T
T
5Dk
~ 25k
I»
c;'
+
c
ii'
cc
~ADJ
...
5Dk
I»
3
08
C2
2DpF
R4
10k
1
R5
l24k
CI
3DpF
-:-.a
~
02
RIO
6.6k
TUH/5716-16
O'S·geeI/ll1/0'S·ge~1/II1/0'S·ge ~ 1/111
iii
co .----------------------------------------------------------------------------,
~
NatiOnal
!I;;a ~ Semiconductor
~
PRELIMINARY
Corporation
!I;;a LM168/LM268/LM368 Precision Voltage Reference
....
fD
!I
General Description
Features
The LM168/LM368 are precision, monolithic, temperaturecompensated voltage references. The LM168 makes use of
thin-film technology enhanced by the discrete laser trimming of resistors to achieve excellent Temperature coefficient (Tempco) of VOUT (as low as 5ppmI"C), along with
tight initial tolerance, (as low as 0.02%). The trim scheme is
such that individual resistors are cut open rather than being
trimmed (partially cut), to avoid resistor drift caused by electromigration in the trimmed area. The LM168 also provides
excellent stability vs. changes in input voltage and output
current (both sourcing and sinking). This device is available
in output voltage options of 5.0V and 1O.OV and will operate
in both series or shunt mode. Also see the LM368-2.5 data
sheet for a 2.5V output. The devices are short circuit proof
when sourcing current. A trim pin is made available for fine
trimming of VOUT or for obtaining intermediate values without greatly affecting the Tempco of the device.
•
•
•
•
•
•
•
•
•
300 ",A operating current
Low output impedance
Excellent line regulation (.0001 %IV typical)
Single-supply operation
Externally trimmable
Low temperature coefficient
Operates in series or shunt mode
10.0V or 5.0V
Excellent initial accuracy (0.02% typical)
Connection Diagram
Dual-In-Llne Package (N)
or S.O. Package (M)
NcOa
y+
2
7
NC
NC
NC
3
6
OUTPUT
y-
4
5
ADJ
Metal Can Package
Ne
TL/H/5522-19
Top View
Order Number LM368N-S.O,
LM368M-S.O or LM268BYN-S.O
See NS Package Number M08A or N08E
TL/H/5522-1
Top View
·case connected 10 VOrder Number LM168BYH-10, LM168BYH-S_O,
LM268BYH-10, LM268BYH-S.O,
LM368YH-10, LM368YH-S.O, LM368H-10, LM368H-S.O
See NS Package Number H08C
Typical Applications
Series Regulator
Shunt Regulator
1 mA-10mA
!
2
5.0DOV
TL/H/5522-2
TUH/5522-3
7-42
r
Absolute Maximum Ratings
Input Voltage (Series Mode)
35V
Reverse Current (Shunt Mode)
Soldering Information
DIP (N) Package, 10 sec.
TO-5 (H) Package, 10 sec.
SO (M) Package, Vapor Phase (60 sec.)
Infrared (15 sec.)
50mA
Power Dissipation
Storage Temperature Range
...en==
(Note 8)
600mW
- 60'C to + 150'C
Operating Temperature Range
LM168
- 55'C to + 125'C
LM268
-40'Cto +85'C
LM368
O'Cto +70'C
+ 260'C
+300'C
+215'C
+ 220'C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" (Appendix D) for other methods of
soldering surface mount devices.
Electrical Characteristics (Note 1)
LM168/LM268/LM368
Parameter
Conditions
Your Error: LM16BB, LM268B
LM36B
Design
Limit
(Note 3)
Units
(Max. unless
noted)
±0.02
±0.02
±0.05
±0.1
%
%
Line Regulation
(Vour + 3V)
s: 30V
±0.0001
±0.0005
%/V
Load Regulation
(Note 4)
o mA s: ISOURCE s: 10 mA
±0.0003
±0.003
±0.001
±0.008
%/mA
%/mA
Thermal Regulation
T=20 mS (Note 5)
±0.005
±0.Q1
%/100mW
250
350
/-LA
3
5
/-LAN
±5
±7.5
±11
±15
±10
±15
±20
±30
ppml'C
ppml'C
ppml'C
ppml'C
30
70
100
mA
-10 mA
s:
s:
Typical
Tested
Limit
(Note 2)
VIN
ISINK
s: 0 mA
Quiescent Current
s:
s:
Change of Quiescent Current vs. VIN
(Vour +3V)
Temperature Coefficient
ofVOUT (see graph): LM168BY
(Note 6)
LM268BY
LM368Y
LM368
-55'C s: TA s: 125'C
-40'C s: TA s: 85'C
O'C s: T A s: 70'C
O'C s: T A s: 70'C
Short Circuit Current
Your = 0
Noise:
VIN
30V
10.0V: 0.1 -10Hz
100Hz -10 I(Hz
6.2V: 0.1 - 10Hz
100Hz -10 kHz
5.0V: 0.1 - 10Hz
100Hz - 10 kHz
VOUT Adjust Range: 10.000V
5.000V
30
1100
20
700
16
575
OV
s:
VPIN5
s:
4.5-17.0
4.4-7.0
Your
uVp-p
nV/.JFfi,
uVp-p
nV/.JFfi,
uVp-p
nV/.JFfi,
6.0-15.5
4.5-6.0
Vmin.
V min.
Note 1: Unless otherwise noted. these specifications apply: TA ~ 25°C. V,N ~ 15V, ILOAD ~ 0, D ,;; CL ,;; 200 pF, Circuit is operating in Series Mode. Or, circuit is
operating in Shunt Mode, V,N ~ + 15V or V,N ~ VOUT, TA ~ +25°C, ILOAD ~ -1.0 rnA, 0 ,;; CL ,;; 200 pF.
Note 2: Tested Limits are guaranteed and 100% tested in production.
Note 3: Design Limits are guaranteed (but not 100% production tested) over the indicated temperature and supply voltage ranges. These limits are not used to
calculate outgoing quality levels.
Note 4: The LM168 has a Class B output, and will exhibit transients at the crossover point. This point occurs when the device is asked to sink approximately
120 [.LA. In some applications it may be advantageous to preload the output to either VIN or Ground, to avoid this crossover point.
Note 5: Thermal Regulation is defined as the change in the output Voltage at a time T after a step change in power dissipation of 100 mW.
Note 6: Temperature Coefficient of VOUT is defined as the worst case delta-VOUT measured at Specified Temperatures divided by the total span of the Specified
Temperature Range (See graphs). There is no guarantee that the Specified Temperatures are exactly at the minimum or maximum deviation.
Note 7: In metal can (H), 9J-c is 75°C/W and 9J-A is 150°C/W. In plastic DIP, 9J-A is 160°C/W. In SO-B, 9J_A is 1BO°C/W, in TO·92, 9J_A is 160°C/W.
Note 8: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its Rated Operating Conditions (see Note 1 and Conditions).
7-43
00
......
r
==
en
N
00
......
r
==
en
Co)
00
CD
CD
Cf)
::iU;
r---------------------------------------------------------------------------------,
Typical Performance Characteristics
Quiescent Current vs. Input
Voltage and Temperature
CD
C'I
...::::!!~
E
400
~3OD
CD
....
::i
iG
200
!ll
100
~
a
126'C
.....
i-""
~
o
o
~
10
20
30
INPUT VOLTAGE (V)
I
40
o
§: 10
w
~
I
~4
~
!i
~
0
~
o
--
!
0.1
!f
0.01
a:
10
Temperature Coefficient:
LM368-10 (Curve A)
10
i
w
~,o.ooov
~
0-
~
~
~
I
I
1-
-5
--, I.
~.7·1j
1-170' - :,
-10
~
-55 -40
,.....
I
o
~
~=
4
I
o
lk
10k lOOk
FREDUENCY (Hz)
10
25
7085 126
TEMPERATURE ('C)
Typical Temperature Coefficient Calculations:
LM368·10 (see Guove A)
T.C.=7.7 mV/(70"Xl0V)
=11 XIOE-6=llppm/'C
100
lk
10k
FREQUENCY (Hz)
lOOk
Temperature Coefficient:
LM168-10 (Curve C)
10
n.jmv ---
15
~
=r
0.1
1M
10
~
~10.000V
0-
~
0.01
100
~
~
~
!i
Temperature Coefficient:
LM268-10 (Curve B)
!
10
3l~
10
I
3
V"
0.0001
lOOk
a:
§
2
I~
iii
0
OUTPUT CURRENT (mA)
Output Impedance vs. Frequency
(Sinking Current)
~
'f'
/
i1 0.001
100
lk
10k
FREQUENCY (Hz)
-10
100
UI
~
SOURCING
-1
Ripple Rejection vs. Frequency
~
"-
-2
10
8
OUTPUT CURRENT (mA)
;;-
0.01
10
~
50
I
3\. ~
..
"
SINKING
i
:c
-3
-4
I
0.1
w
...~
100
i
.!!.
,...~~I""" 1"""1-1"'"
Output Impedance vs. Frequency
(Sourcing Current)
~
.
.
I-
--rz5'C
r
"-
;;-
_~51,c'
i
-55'C
Output Change vs.
Output Current
3
S
{S
--" .
~
25'C'"
t:. ....
~
(Note 1)
Dropout Voltage vs. Output Current
(Series Mode Sourcing Current)
19
-5
~
-10
-
~ 10.DODV
I
~
I
~
126'- ..j
o
I
0 25
70 85
TEMPERATURE ('C)
125
LM268·10 (see Cuove B)
T.C.=9.35 mV/(125'xIOV)
=7.5xIOE·6=7.5ppm/'C
Output Noise vs. Frequency
(I) LM368 alone.
(2) with 0.01 1'1 Mylar, Trim to Gnd.
(3) with Ion in series with 10 1'1, VOUT to Gnd.
(4) with Both.
........
"
J
I
"'" ...... -.,!OV
5V
o
10
100
lk
FREQUENCY (Hz)
10k
TLlH/5522-5
7-44
,-~
w
~
I
--- ,.....
i
-55 -40
I
I
-5
-10
If
::-J
~
,,
t'.
9.35 mV
I
,
-55 -40
f--
---
'"
---
180'
-
---
l
1:
~1
0 25
70 85
TEMPERATURE ('C)
,
125
TLlH/5522-4
LM168·10 (see Guovs C)
T.C.=9.35 mVl(18O"Xl0V)
=5.2Xl0E·6=5.2ppm/'C
r-
Typical Applications
:s::
.....
CO
.....
r:s::
N
CJ)
Wide Range Trimmable Regulator
Narrow Range Trimmable Regulator (± 1% min.)
Y+
Y+
r-oI.,.;;.-~---
-2
§
I
I
LM369 (see curve at left):
T.C. ~ 0.5 mV/(7S0 x 10V)
~ 6.7 x 10-7 ~ 0.67 ppm/oC
I
I
-3
_4~~~~~-L~-L-L~
-75 -50 -25
a
25 50 75 100 125 150
TEMPERATURE (OC)
7-51
TLlH/91 I 0-27
Application Hints
the circuits shown, to provide an output trim range of ± 10
millivolts. Trimming to a wider range is possible, but is not
recommended as it may degrade the Tempco and the
Tempco linearity at temperature extremes. For example, if
the output were trimmed up to 10.240V, the Tempco would
be degraded by 8 ppml'C. As a general rule, Tempco will
be degraded by 1 ppml'C per 30 mV of output adjustment.
The output can sink current as well as source it, but the
output impedance is much better for sourcing current. Also,
the LM169/369 requires a 0.1 p.F tantalum capacitor (or,
0.1 p.F in series with 1On) bypass from the output to ground,
for stable operation in shunt mode (output sinking current).
The output has a class-B stage, so if the load current changes from sourcing to sinking, an output transient will occur.
To avoid this transient, it may be advisable to preload the
output with a few milliamperes of load to ground. The
LM169/369 does have an excellent tolerance of load capacitance, and in cases of load transients, electrolytic or
tantalum capacitors in the range 1 to 500 microfarads have
been shown to improve the output impedance without degrading the dynamic stability of the device. The LM169/369
are rated to drive an output of ± 10 mA, but for best accuracy, any load current larger than 1 mA can cause thermal
errors (such as, 1 mA x 5V x 4 ppm/100 mW = 0.2 ppm
or 2 microvolts) and degrade the ultimate precision of the
output voltage.
The output is short-circuit-proof to ground. However, avoid
overloads at high ambient temperatures, as a prolonged
short-circuit may cause the junction temperature to exceed
the Absolute Maximum Temperature. The device does not
include a thermal shut-down circuit. If the output is pulled to
a positive voltage such as + 15 or + 20V, the output current
will be limited, but overheating may occur. Avoid such overloads for voltages higher than + 20 V, for more than 5 seconds, or, at high ambient temperatures.
The LM169/369 has an excellent long-term stability, and is
suitable for use in high-resolution Digital Voltmeters or Data
Acquisition systems. Its long-term stability is typically 3 to 10
ppm per 1000 hours when held near T max, and slightly better when operated at room temperature. Contact the factory
for availability of devices with proven long-term stability.
The LM169/LM369 can be applied in the same way as any
other voltage reference. The adjacent Typical Applications
Circuits suggest various uses for the LM169/LM369. The
LM169 is recommended for applications where the highest
stability and lowest noise is required over the full military
temperature range. The LM369 is suitable for limited-temperature operation. The curves showing the Noise vs. Capacitance in the Typical Performance Characteristics section show graphically that a modest capacitance of 0.1 to
0.3 microfarads can cut the broadband noise down to a level of only a few microvolts, less than 1 ppm of the output
voltage. The capacitor used should be a low-leakage type.
For the temperature range 0 to 50'C, polyester or Mylar@
will be suitable, but at higher temperatures, a premium film
capacitor such as polypropylene is recommended. For operation at + 125'C, a Teflon@ capacitor would be required, to
ensure sufficiently low leakage. Ceramic capacitors may
seem to do the job, but are not recommended for production use, as the high-K ceramics cannot be guaranteed for
low leakage, and may exhibit piezo-electric effects, converting vibration or mechanical stress into excessive electrical
noise.
Additionally, the inherent superiority of the LM169/369's
buried Zener diode provides freedom from low-frequency
noise, wobble, and jitter, in the frequency range 0.Q1 to 10
Hertz, where capacitive filtering is not feasible.
Pins 1, 3, 7, and 8 of the LM169/369 are connected to
internal trim circuits which are used to trim the device's output voltage and Tempco during final testing at the factory.
Do not connect anything to these pins, or improper operation may result. These pins would not be damaged by a
short to ground, or by Electrostatic Discharges; however,
keep them away from large transients or AC signals, as
stray capaCitance could couple noises into the output.
These pins may be cut off if desired. Altematively, a shield
foil can be laid out on the printed circuit board, surrounding
these pins and pin 5, and this guard foil can be connected to
ground or to Vou\, effectively acting as a guard against AC
coupling and DC leakages.
The trim pin (pin 5) should also be guarded away from noise
signals and leakages, as it has a sensitivity of 15 millivolts of
.6.Vou\ per microampere. The trim pin can also be used in
Typical Applications
Series Reference
Shunt Reference with Optional Trim
Series Reference with
Optional Filter
for Reduced Noise
13V:S V :S 30V
f2
13'(,:SV :S30V
r2
r:;2---t-----~~~OV
IN
Lt.4369
OUT
~ ~~~;OV
GND
IN
Lt.4369
GNO
~
TUH/911 0-2
2M
50 K
TRIM t=-t-WO,.....~ ~
O~r~T
==~A!.~F
(t 10mV)
'--';;1'~4---'
IN
~
OUT 6
TRIM
=~.lI'F
LOW LEAKAGE
Lt.4369
OUT.!....-
~~:'~;OV
GND
14
-:!:-
-b
TLlH/9110-4
TL/H/9110-3
7-52
.-------------------------------------------------------------------------------------, riii:
Typical Applications (Continued)
en
...
± 10V Reference
CD
.....
r-
± 5V Reference
V+
iii:
w
en
+15
2
CD
IN
:10.IP.F
LM369
I--
OUTPUT
+10.000V
OUT 6
4
2
IN
LM369
OUT
TRIM
6
+5V
2M
5
50K
TRIM
GNO
2
1OK
4
LM369
a.1 %
OUT 6
71.'-' 2
6 """lM607
GND
!
0.01 p.fb
~~~
-
L-_ _ _ _....._ _ _ _ _ ~~1J:~60v
1=2mA
-r
1OK
a.1 %
-5V
VTLlH/9110-7
-15
Tl1H/9110-8
Multiple Output Voltages
23V :s VIN :s 35V
23V :s VIN :s 30V
1
2
J2
IN
OUT
t!.. 20V
TRIM
~
LM369
GND
6
OUT t-"--......-
IN
LM369
GND
TRIM
5
20V
10K
4
4
2
IN
2
IN
OUT
LM369
GND
TRIM
6
~
OUT t-"--+-10V
LM369
10V
0.1 p.F
TANTALUM
4.7K
4
..L
Tl/H/9110-10
Tl/H/9110-9
24V :s VIN :s 30V
R
20V
~
Thin Film Resistor Network
0.05% Matching and 5 ppm Tracking
(Beckman 694·3·R·10K·A).
(Caddock T·914-10K-100-05)
(Allen Bradley F08B103A)
or similar.
II
~-""'--++--10V
TLlH/9110-11
7-53
Typical Applications (Continued)
Precision Wide-Range Current Source
+15
2
IN
10K"
10K"
LM369 OUT
GND
4
0.1 J'F
TANTALUM
10 K"
10K"
AI = LF411A, LM607, LM30BA
or similar
01, 02
= high /3 PNP,
PN4250, 2N3906,
or similar
• = Part of Precision Resistor Network,
± 0.05% Matching,
(Allen Bradley F08Bl03A)
(Caddock T-914·10K·l00·05)
(Beckman 694·3·R·l0K·A)
or similar
B.2K
5%
(+12V 2:: VOUT 2::-20V)
I
t
-15
10UT=
2V
RX
TL/H19110-18
±10V, ±5VReferences
+15V
+5V
A =
R
=
-5V
Thin Film Resistor Network
0.05% Matching and 5 ppm Tracking
(Beckman 694·3·R·l0K·A),
(Caddock T-914·1 OK·l 00·05)
(Allen Bradley F08B 103A)
V. LF444A or
Yo LF412A or
LM607
-10V
or similar.
-15V
Reference with Booster
TL/H/9110-12
100 mA Boosted Reference
V+
14V::SVIN ::S31V
3.3
470
Ql
2N2907
100-200
lW
IN
OUT~-+_,_-VOUT
LM369
5
~-+-.....-VOUT
I
I
<:(OPTIONAL
+
PRE-LOAD)
:f
(OPTIONAL
PRE-LOAD)
I
I
TL/H/9110-13
TL/H/9110-14
7-54
Typical Applications
(Continued)
Precision Programmable Supply
+15V
+15V
~~~--~-------------'21
DAC1655
18
16 BIT DAC
PINS 1-16
DIGITAL
INPUTS---------...I
A1, A2, A3 = LF411A, LM607, or similar
-15V
TL/H/9110-21
Current Source
-3 TO
-15V
+IL=W
RX
-30V
2k,. Rx,. 10M
TL/H/9110-16
Precision Current Source
+15
0.1 }.If
LOW
LEAKAGE
Rx
GND
0.1 }.If
4
10D.
10K
5%
-15
IOUT= 10V
Rx
010 02 = high P PNP,
PN4250, 2N3906
or similar
A1 = LM607, LMll, LF411A
or similar
TL/H/9110-17
7-55
Typical Applications (Continued)
Oscilloscope Calibrator
12
TO
SCOPE
........
,
ir
1K
t - - - ; 0 t------'
49.9K
[:>0 =
224
SI
WM74HC04
FREQUENCY
SELECTOR
(IMHz, 976Hz)
49.94
,
,,,
,,
,,
,
S2
A~PL1TUDE
SELECTOR
(10V,10mV)
TLIH19110-22
Precision Wide-Range Current Sink
1 _ 10V
out - Rx
At = LMll, LM607 or similar.
(V3 + 2V) s: VOUl s: + 20V.
01, 02 = high Bela NPN, 2N3707, 2N3904 or similar.
-20V
TLIH19110-19
Digitally Variable Supply
+15V
2
IN
LM369
OUT
Voul = -10V x (Digitally Set Gain).
AI = LMllA, LM607, or similar.
MDAC = DAC1220, DAC120B, DAC1230, or similar.
TLlHI911 0-20
7·56
Typical Applications (Continued)
Ultra-Low-Nolse Statistical Reference
+15V
REPEAT
t-:;---.....- - -.....- -...... - - - - - -. - - - - -AS
DESIRED
• __ .1. _ •
I
I
: Lt.l369:--.
I
I
I
I
. . . . . _.
•
:
......
-=
SEE
NOTE
R
I
I
I
I
I
l
::R
"I
....- - -....- - -....- - -.....- - -......-OUTPUT
OPTIONAL OUTPUT BUFFER
10K
BUFFERED
OUTPUT
10K
.::r:.
1 ).IF
POLYPROPYLENE
TL/H/9110-23
20011 ,; R ,; lk
When N pieces of LM369 are used,the Vout noise Is decreased by a factor of
iN
If the output buffer is not used, for lowest noise add 0.1 ,.F Mylar"' from ground to pin 5 of each LM369.
LM169 Block Diagram
+VS
VOUT
400.11
10K
- - - \~,
_, •
.. ---
OUTPUT
TRIMS
-,.
.....~,
r-~rl-+--~~~=:t:::t---:....:+---I5
TRIM AND
FILTER
22K
L--.l--------~t:===:t==~
4
•• PATENT PENDING
'00 not connect; intemal connection for factory trim.
7-57
GROUND
TL/H/91 t 0- t 5
_
National
Semiconductor
Corporation
LM185-1.2/LM285-1.2/LM385-1.2 Micropower Voltage
Reference Diode
General Description
The LM185-1.2/LM285-1.2/LM385-1.2 are micropower 2terminal band-gap voltage regulator diodes. Operating over
a 10 ,.,.A to 20 mA current range, they feature exceptionally
low dynamic impedance and good temperature stability. Onchip trimming is used to provide tight voltage tolerance.
Since the LM185-1.2 band-gap reference uses only transistors and resistors, low noise and good long term stability
result.
Further, the wide operating current allows it to replace older
references with a tighter tolerance part.
The LM 1B5-1.2 is rated for operation over a - 55·C to
125·C temperature range while the LM2B5-1.2 is rated
-40·Cto B5·C and the LM3B5-1.2 O·Cto 70·C. The LM1B51.2/LM285-1.2 are available in a hermetic TO-46 package
and the LM2B5-1.2/LM385-1.2 are also available in a lowcost TO-92 molded package, as well as S.O.
Careful deSign of the LM185-1.2 has made the device exceptionally tolerant of capacitive loading, making it easy to
use in almost any reference application. The wide dynamic
operating range allows its use with widely varying supplies
with excellent regulation.
Features
The extremely low power drain of the LM185-1.2 makes it
useful for micropower circuitry. This voltage reference can
be used to make portable meters, regulators or general purpose analog circuitry with battery life approaching shelf life.
•
•
•
•
•
•
Operating current of 10 ,.,.A to 20 mA
1 % and 2% initial tolerance
1n dynamic impedance
Low temperature coefficient
Low voltage reference-1.235V
2.5V device also available-LM385-2.5
Connection Diagrams
TO·92
Plastic Package (Z)
TO·46
Metal Can Package (H)
SO Package
+
NC
8
TL/H/5518-10
Bottom View
TL/H/5518-6
Order Number LM385Z·1.2,
LM385BZ·1.2, LM385BXZ·1.2,
LM385BYZ·1.2, LM285BXZ·1.2,
LM285BYZ·1.2 or LM285Z·1.2
See NS Package Number Z03A
3
Bottom View
NC
Order Number LM185H·1.2,
LM185BXH·1.2, LM185BYH·1.2,
LM285H·1.2, LM285BXH·1.2
or LM285BYH·1.2
See NS Package Number H02A
Ne
4
NC
TL/H/5518-9
Order Number LM285M·1.2,
LM385M·1.2 or LM385BM·1.2
See NS Package Number M08A
Applications
Wide Input Range
Reference
Centigrade Thermometer
VIN =2.JV TO JOV
Calibration
I. Adjusl AI so that VI
I mVI"K
=
temp at
2. Adjusl V2 to 273.2 mV
1.5yt
tlQ for 1.3V to 1.6V battery volt·
age = 50 p.A to 150 /LA
27k
TUH/5518-8
TLlH/5518-1
7-5B
r-
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(Note 6)
Reverse Current
Storage Temperature
30mA
10mA
Forward Current
Operating Temperature Range
LM185-1.2
-55'C to
LM285-1.2
+ 150'C
260'C
300'C
215'C
220'C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" (appendix D) for other methods of
soldering surface mount devices.
+ 125'C
+ 85'C
-40'C to
LM385-1.2
-55'Cto
Soldering information
TO-92 package: 10 sec.
TO-46 package: 10 sec.
SO package: Vapor phase (60 sec.)
Infrared (15 sec.)
O'Cto 70'C
5:
.....
CO
U1
.....•
N
......
r-
5:
.
N
CO
U1
.....
N
......
r5:
Co)
CO
C{I
.....
Electrical Characteristics (Note 1)
Parameter
N
LM185-1.2
LM185BX-1.2
LM185BV-1.2
LM285-1.2
LM285BX-1.2
LM285BV-1.2
Conditions
Typ
Reverse Breakdown
Voltage
TA = 25'C, IMIN S; IR S; IMAX
LM185-1.2/LM285-1.2/LM385B-1.2
1.235
Tested
Limit
(Note 2)
LM385-1.2
LM385B-1.2
LM385BX-1.2
LM385BV-1.2
Design
Limit
(Note 3)
1.223
1.247
Typ
1.235
LM385-1.2
1.235
Minimum Operating
Current
8
10
20
8
Tested
Limit
(Note 2)
Units
Limit
Design
Limit
(Note 3)
1.223
1.247
1.205
1.260
VMIN
VMAX
VMIN
VMAX
15
20
",A
Reverse Breakdown
IMINS;IRS;1 mA
1
1.5
1
1.5
mV
Voltage Change with
Current
1 mAS;IRs;20 mA
10
20
20
25
mV
Reverse Dynamic
Impedance
IR=100 ",A. f=20 Hz
Wideband NOise (rms)
Long Term Stability
Average Temperature
Coefficient (Note 4)
1
1
n
IR=100",A
10 HzS;fs; 10 kHz
60
60
)JoV
IR=100 ",A, T=1000 Hr
TA=25'C±0.1'C
20
20
ppm
IR=100",A
30
50
X Series
Y Series
Other Versions
30
50
150
150
ppml'C
ppm/'C
ppml'C
Note 1: Parameters Identified with boldface type apply at temperature extremes and for IMIN < IR <20 mA, unless otherwise specified. All other numbers apply at
TA~TJ~25'C.
Note 2: Guaranteed and 100% production tested.
Note 3: Guaranteed (but not 100% production tested) over the operating temperature and input current ranges. These limits are not to be used to calculate
outgoing quality levels.
Note 4: The average temperature coefficient Is defined as the maximum deviation of reference voltage at all measured temperatures between the operating TMAX
and TMIN, divided by TMAX - TMIN. The measured temperatures are -55'C, -40'C, O'C, 25'C, 70'C, 85'C. 125'C.
Note 5: For elevated temperature operation, T, max is:
LM185
150'C
LM285
125'C
LM385
100'C
Thermal Resistance
TO-92
TO-46
SO-8
8j. ijunction to ambient)
180'C/W (0.4" leads)
170'C/W (0.125" leads)
440'C/W
165'C/W
n/a
80'C/W
n/a
8,e ijunction to case)
Note 6: Refer to RETS185H·1.2 for military specifications.
7-59
fI
C"!
,..
Ib
~
Typical Performance Characteristics
:5
'"
C"!
,..
Reverse Characteristics
C'I
..
...I
iii
Ib
co
:i
'"
C"!
,..
Ib
co
,..
~
Reverse Characteristics
lDD
,.oS
1.2
..5
..
.
E
~
.3
....
Forward Characteristics
10
10
~
or
=
=
or
B
Q
or
>
>
I;
=
or
;I:
=
~
~
~
1::
=
D.'
~
~
Q
~
0.4
Q
0.1
0.4
Dl
0.6
0.1
1.0
1.2
1.4
0.1
REVERSE VOLTAGE IV)
Temperature Drift
1.260
.
~ 1.250
w
~
~
..,w
ill
:li
1.240
r-
-"","""
r-
1.230
r-....
~
"'"
.....
u
Ii:
~
u
;;;
~
u
.
.
;;;
D.l
D.l
.
lD
,.
.
~
~
~
3DD
ZDD
or
=
~
1\
lDD
I
lD
I
lDD
lk
100
lk
lDk
lDDk
1M
FREQUENCY 1Hz)
Response Time
2.D
1.5
ID
..
5D
E
I.D
40
~
D.5
Q
D
lD
lDD
1D
.3
4DD
--
~
>
Filtered Output Noise
SDD
V
/
lD
REVERSE CURRENT 'mAl
IDD
L
100
Q
Noise Voltage
is
IR -IDD"A
or
~
100
~
!
or
IR -IDD"A
fA =25°C
1k
~
lD
TEMPERATURE I'C)
:s
10k
u
-55-35-15 5 25 45 65 85105125
~
Reverse Dynamic Impedance
r-rTlTnnr"TI1Ir1mnnr:-,.r:Z"S""1
Hz
§
or
.....
1.220
FORWARD CURRENT ImA)
~
.
10
D.l
lDD
Reverse Dynamic Impedance
lDD
'~=I~O~IA -
1.,..00 i""
lD
REVERSE CURRENT ImA)
~
3D
:l
2D
Q
~
>
lD
lD
'-
lDk
FREDUENCY 1Hz)
lDDk
lk
1l1li
CUTDFF FREDUENCY 1Hz)
lDOk
2DD
4DD
6DD
TIME '",)
TL/H/5518-3
7-60
r-----------------------------------------------------------------------------,
Applications
(Continued)
Mlcropower Reference
from 9V Battery
~
.....
Reference from
1.SV Battery
~
3:
co
I.SV
gVSOOk
~
....i\).
N
k
1.2V
':' LMlBS-1.2
~
3:
....
co
Cf1
....
i\)
U'I
.....
1.2V
~
3:
Co)
co
':' LMlBS-1.2
.
U'I
....
i\)
TLlH/5518-2
LM385 Applications
Micropower· SV Regulator
-
Mlcropower· 10V Reference
-
IQ
r-;:------...
-------~I----V,N?5.2V
IQ
r---~~--VIN
=15V
1M
>~""-_~10V
r - - -...- t - Vo = 5V
'L ~ loomA
150 pF
+ 4.7"F
500k
TANTALUM
LMl85-1.2
10M
l.5M
2k
·10
~
20 p.A standby current
'10" 30 p.A
Precision 1 fLA to 1 mA Current Sources
LMl85·1.2
LMl85-1.2
Cl
150pF
fI
1.5VTo 2 7 V - - - -. .- - - - " " , . " .....
-1.5V TO -27V - - . . ; . . -...---1-"",."....
-lOV
"OUT~~
R2
7-61
TLlH/5518-4
LM385 Applications
(Continued)
METER THERMOMETERS
O·C -1000C Thermometer
Lower Power Thermometer
ISO
1.3T0
1.6V1
8k TO
12kt
1.5V
t
(1.3-1.6V)
• 2N3638 or 2N2907 select for inverse HFE '" 5
t Select for operation at 1.3V
*'0 '"
600 ".A to 900 pA
Calibration
1. Short LM385-1.2, adjust A3 for
10UT~temp
at I pA/'K
2. Remove short, adjust R2 for correct reading in centigrade
tlo at 1.3Vo< 500 ".A
10 at 1.6V '" 2.4 mA
O·F - 50·F Thermometer
Mlcropower Thermocouple Cold Junction Compensator
V'
2k
ISO
til
5.lk
MERCURY
CELL
1.345V
1M
1%
v-
+
ZERO AOJ
LM385-1.2
1.3-1.6V
R2
R4
100
TCAOJ
500
lOOk
THERMOCOUPLE
RI
+
\_,
COLD JUNCTION
ISOTHERMAL
WITH LM334
Calibration
TL/H/55IB-5
I. Short LM385-1.2, adjust A3 for lOUT ~ temp at I.B ".A/'K
2. Aemove short, adjust A2 for correct reading in 'F
Adlustment Procedure
I. Adjust TC ADJ pot until vollage across AI equals Kelvin temperature
multiplied by the thermocouple Seebeck coefficient.
2. Adjust zero ADJ pot until voltage across A2 equals the thermocouple
Seebeck coefficient multiplied by 273.2.
Seebeck
Rl
R2
Voltage
Voltage
Thermocouple
Type
Coefficient (Il)
(Il)
AcroasRI AcroaaR2
(my)
(".VI'C)
iii 25'C
(mY)
J
52.3
523 1.24k
15.60
14.32
T
42.8
lk
12.77
432
11.78
K
40.8
12.17
412 9530
11.17
S
6.4
63.4 1500
1.908
1.766
Typical supply current 50 ".A
7-62
r-
...3:co
...N·
Schematic Diagram
U1
~----~--~---t----~1-~~--~----+
......
r3:
R6
200k
N
co
...·
N
U1
......
r-
3:
c.:I
co
R7
50k
...N·
U1
RB
lOOk
TLlH/5518-7
7-63
~
~
co
Cf)
::E
...U;
,---------------------------------------------------------------------,
~ Semiconductor
NatiOnal
Corporation
~ LM 185-2.5/LM285-2.5/LM385-2.5 Micropower
co
C\I
::E
...U;
~
co
....
...
::E
Voltage Reference Diode
General Description
The LM185-2.5/LM285-2.5/LM385-2.5 are micropower 2terminal band-gap voltage regulator diodes. Operating over
a 20 /LA to 20 mA current range, they feature exceptionally
low dynamic impedance and good temperature stability. Onchip trimming is used to provide tight voltage tolerance.
Since the LM-185-2.5 band-gap reference uses only transistors and resistors, low noise and good long term stability
result.
Further, the wide operating current allows it to replace older
references with a tighter tolerance part. For applications requiring 1.2V see LM185-1.2.
The LM185-2.5 is rated for operation over a -55'C to
125'C temperature range while the LM285-2.5 is rated
- 40'C to 85'C and the LM385-2.5 O'C to 70'C. The LM1852.5/LM285-2.5 are available in a hermetic TO-46 package
and the LM285-2.5/LM385-2.5 are also available in a lowcost TO-92 molded package, as well as S.O.
Careful deSign of the LM185-2.5 has made the device exceptionally tolerant of capacitive loading, making it easy to
use in almost any reference application. The wide dynamic
operating range allows its use with widely varying supplies
with excellent regulation ..
Features
The extremely low power drain of the LM185-2.5 makes it
useful for micropower circuitry. This voltage reference can
be used to make portable meters, regulators or general purpose analog circuitry with battery life approaching shelf life.
•
•
•
•
•
Operating current of 20 /LA to 20 mA
1.5% and 3% initial tolerance
1n dynamic impedance
Low temperature coefficient
Low voltage reference-2.5V
Applications
Wide Input Range Reference
Mlcropower Reference from 9V Battery
VIN' l.7V TO lDV
9V
l.lk
. . ._
. ._OUT
2.5V
TL/H/5519-2
TL/H/5519-12
Connection Diagrams
10-46
TO-92
Plastic Package
SO Package
Metal Can Package
+
Ne
Ne
8
TL/H/5519-8
Bottom View
Order Number LM285BXZ-2.5,
LM285BYZ-2.5, LM285Z-2.5,
LM385Z-2.5, LM385BZ-2.5,
LM385BXZ-2.5 or LM385BYZ-2.5
See NS Package Number Z03A
TL/H/5519-13
Bottom View
Order Number LM185H-2.5,
LM185BXH-2.5, LM185BYH-2.5,
LM285H-2.5, LM285BXH-2.5 or
LM285BYH-2.5
See NS Package Number H02A
7-64
3
Ne
4TLlH/5519-11
Order Number LM285M-2.5,
LM385M-2.5 or LM385BM-2.5
See NS Package Number M08A
Absolute Maximum Ratings
Storage Temperature
- 55'C to + 150'C
Soldering Information
TO·92 Package (10 sec.)
260'C
TO·48 Package (10 sec.)
300'C
SO Package
Vapor Phase (60 sec.)
21S'C
Infrared (15 sec.)
220'C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" (Appendix D) for other methods of
soldering surface mount devices.
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(Note 6)
Reverse Current
30mA
Forward Current
10mA
Operating Temperature Range
LM185-2.5
-55'Cto + 125'C
LM285-2.5
-40'C to + 85'C
LM385-2.5
O'Cto 70'C
Electrical Characteristics (Note 1)
Parameter
LM18S·2.S
LM18SBX·2.S
LM18SBY·2.S
LM28S·2.5
LM28SBX·2.S
LM28SBY·2.S
Conditions
Typ
Reverse Breakdown
Voltage
TA=25'C.IMIN,;;IR,;;IMAX
LM185·2.5/LM285-2.5/LM385B-2.5
2.5
Tested
Limit
(Note 2)
LM38S·2.5
LM38SB·2.S
LM38SBX·2.S
LM38SBY·2.S
Design
Limit
(Note 3)
2.462
2.538
2.5
LM385-2.5
Minimum Operating
Current
20 /LA,;; IR';; 1 mA
1 mA,;;IR';;20 mA
Reverse Dynamic
Impedance
IR= 100 /LA, f=20 Hz
Wideband Noise (rms)
Long Term Stability
Average Temperature
Coefficient (Note 4)
2.5
13
Reverse Breakdown
Voltage Change with
Current
Typ
20
30
1
10
1.S
20
13
Tested
Limit
(Note 2)
Units
Limit
Design
Limit
(Note 3)
2.462
2.538
2.425
2.575
VMIN
VMAX
VMIN
VMAX
20
30
/LA
2.0
20
2.S
2S
mV
mV
1
1
n
IR= 100 /LA
10 Hz,;;f,;; 10 kHz
120
120
/LV
IR=100 /LA, T= 1000 Hr
TA=25'C±0.1·C
20
20
ppm
IR= 100 /LA
ppml'C
ppml'C
lS0
ppml'C
Other Versions
lS0
Note 1: Parameters identified with boldface type apply at temperature extremes and for IMIN < IR < 20 rnA, unless otherwise specified. All other numbers apply at
TA = TJ = 25'C.
Note 2: GUaranteed and 100% production tested.
Note 3: Guaranteed (but not 100% production tested) over the operating temperature and input current ranges. These limits are not to be used to calculate
outgoing quality levels.
Note 4: The average temperature coefficient is defined as the maximum deviation of reference voltage at all measured temperatures between the operating TMAX
and TMIN, divided by TMAX-TMIN. The measured temperatures are - 55'C, - 40'C, O'C, 25'C, 70'C, 85'C, 125'C.
Note 5: For elevated temperature operation, TJ max is:
LM185
150'C
LM285
125'C
LM385
100'C
Thermal Resistance
TO·92
T0-46
SO-&
8ia (Junction to Ambient) 180'C/W (0.4' leads) 440'C/W 165'C/W
170'C/W (0.125' leads)
80'C/W
nla
81a (Junction to Case)
n/a
X Series
Y Series
30
SO
Note 6: Refer to RETSI85H-2.5 for military specifications.
7·65
30
SO
fI
It)
!:'Ii
&b
co
C')
:::E
Typical Performance Characteristics
Reverse Characteristics
16
...J
iii
.
1~~),I~~k
""
,
...=>
\
;;
oS
!:'Ii
It)
co
N
:::E
12
~w
~
>
......
It)
!:'Ii
•
It)
co
.,...
:::E
2w
I'~ A • 2~,I~IL
"z
...J
Forward Characteristics
1.6 r-TTT11111r-rrrmmrTT1mm..-;-rnmlll
...J
0.1
1
10
1.2
1-t++tItlt--HttttHt-tHittltH-t
0.8
co
~
~
I~rriill
~
co
-4
0.01
;g
0.4
100
0.1
0.01
REVERSE CURRENT (mAl
Reverse Dynamic
Impedance
Temperature Drift
2.530
~
w
...~ 2.500
~
l""-
V
2.490
t---
~
2.470
2.460
100
10
!!
"~
~ 2.480
~
TA • 25'C
1ft::: 100p.A
f1
"z
~
~
w
~
Reverse Dynamic
Impedance
IR" lDOp.A
2.520
"
;;
;;
0.1 L..J..LUJWIL-U.J.JIUJJL-Ll.WJIIILUJ.lllW
5 25 45
Ik
V
100
10
~
z
2.450
-55 -35 -IS
65 85 IDS 125
0,01
TEMPERATURE ('CI
0.1
10
./
V
Noise Voltage
10
100
lk
Filtered Output Noise
~
~w
~
3. 0
1-H-+++l1H---+-J
1000
2
800
"~
~co
600
400
tOOk
1M
Response Time
120
100
10k
FREQUENCY (Hz)
AI
li';"OO"A
1200
/
V
0.1
100
REVERSE CURRENT (mAl
1400
100
10k
1000 rTTnlllll""Trmmr"TTTTTTlrr-;n-rrnm
~2.510
10
FORWARD CURRENT (mAl
I.0
10
200
I
OUTPUT
~'}~
r---r---r---- ~
o~
>
11\
I
2.0
~ '"""
"7
J INPUT
I
10
100
Ik
10k
FREQUENCY (Hz)
lOOk
100
Ik
10k
CUTOFF FREQUENCY (Hz)
lOOk
200
400
600
TlMEl#,Isl
TL/H/5519-3
7-66
r-
...s::
LM385-2.5 Applications
CO
·
(II
Mlcropower' 5V Regulator
Micropower' 10V Reference
-
IQ
r:------....--------.·---VIN~5.2V
N
u-.
......
IQ
r-
. . . - - - - . - - - V I N =15V
Ei:
N
CO
500k
·
(II
N
>~P--4~10V
~
r-
Ei:
...-__+-_+_ Vo = 5V
IL
u-.
......
150pF
100mA
c.:I
CO
1.5M
·
(II
N
u-.
500k
LMJ85·2.5
10M
TUH/5519-10
'10 '" 30 I"A standby current
TL/H/5519-9
'10'" 40I"A
Precision 1 p.A to 1 mA Current Sources
lMJ85·2.5
LMJ85·2.5
Cl
150 pF
.....'V'I,..,.....
-1.5V TQ -21V --......;~~~---.....""'V\o,.....J
1.5V TO 21V ----~t----
-JOV
TUH/5519-4
METER THERMOMETERS
O'C-100'C Thermometer
O'F-50'F Thermometer
lk
lk
R4
R4
100
220
TL/H/5519-5
Calibration
Calibration
I. Short LM385-2.5, adjust R3 for IOUT=temp at 'I"A/'K
2. Remove short, adjust R2 for correct reading in centigrade
2. Remove short, adjust R2 for correct reading in 'F
I. Short LM385-2.5, adjust R3 for IOUT=temp at 1.81"AI'K
7-67
LM385-2.5 Applications (Continued)
Mlcropower Thermocouple Cold Junction Compensator
3V
LITHIUM
Adlustment Procedure
1. Adjust TC ADJ pol unlil voltage across RI equals Kelvin lemperaltJre
multiplied by Ihe Ihermocouple Seebeck coefficient
2. Adjust zero ADJ pot unlil vollage across R2 equals Ihe Ihermocouple
Seebeck coefficienl multiplied by 273.2.
2>
I"
18k
1M
I"
V-
+
TC AOJ
SOD
2ERO AOJ
100>
LM3BS-2.S
RI
R2
,-,
THERMOCOUPLE
+
+
METER
'-'
COLO JUNCTION
ISOTHERMAL
WITH LM334
TUH/5519-6
SeebeCk
Coefficient
(,.vrC)
J
52.3
T
42.8
40.8
K
S
6.4
Typical supply current 50 )LA
Thermocouple
Type
R1
(0)
R2
(11)
523
432
412
63.4
1.24k
1k
95311
15011
Voltage
AcrossR1
@25°C
(my)
15.60
12.77
12.17
1.908
Voltage
AcrossR2
(mV)
Improving Regulation of Adjustable
Regulators
14.32
11.78
11.17
1.766
TUH/5519-7
Schematic Diagram
RS
200k
R7
SDk
SOOk
RB
JOOk
SOOk
TL/H/5519-1
7·68
~-------------------------------------------------------------------------------.
~ Semiconductor
NatiOnal
r-
3:
....
co
U'I
......
Corporation
r3:
I\)
co
U'I
.....
r-
LM185/285/385 Adjustable Micropower Voltage
Reference
3:
Co)
co
U'I
General Description
The LM185/LM285/LM385 are micropower 3-terminal adjustable band-gap voltage reference diodes. Operating from
1.24 to 5.3V and over a 10 p.A to 20 mA current range, they
feature exceptionally low dynamic impedance and good
temperature stability. On-chip trimming is used to provide
tight voltage tolerance. Since the LM185 band-gap reference uses only transistors and resistors, low noise and
good long-term stability result.
Careful design of the LM185 has made the device tolerant
of capacitive loading, making it easy to use in almost any
reference application. The wide dynamic operating range
allows its use with widely varying supplies with excellent
regulation.
The extremely low power drain of the LM185 makes it useful
for micropower circuitry. This voltage reference can be used
to make portable meters, regulators or general purpose an-
alog circuitry with battery life approaching shelf life. Further,
the wide operating current allows it to replace older references with a tighter tolerance part.
The LM185 is rated for operation over a -55'C to 125'C
temperature range, while the LM285 is rated -40'C to 85'C
and the LM385 O'C to 70'C. The LM185 is available in a
hermetic TO-46 package and the LM285/LM385 are available in a low-cost TO-92 molded package, as well as S.O.
Features
•
•
•
•
•
Adjustable from 1.24V to 5.30V
Operating current of 10 p.A to 20 mA
1% and 2% initial tolerance
1 n dynamic impedance
Low temperature coefficient
Connection Diagrams
TO-92
Plastic Package
TO-46
Metal Can Package
~
TUH/5250-9
Bottom View
SO Package
+
8
\::Y
TL/H/5250-1
BoHomView
Order Number LM285BXZ,
LM285BYZ, LM285Z, LM385BXZ,
LM385BYZ or LM385Z
See NS Package Number Z03A
Order Number LM185BH,
LM185BXH or LM185BYH
See NS Package Number H03A
3
He
He
4
He
TL/H/5250-10
Order Number LM285M or LM385M
See NS Package Number M08A
Block Diagram
Typical Applications
1.2V Reference
5.0V Reference
9Y
9V
R1 VOUT= 1.24
5Dk
HI
500k
(~+ 1)
",--,,-5V
"'--1.2V
+
H2
12Dk
R3
364k
TL/H/5250-13
TUH/5250-14
TUH/5250-2
7-69
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(Note 6)
Reverse Current
30mA
Forward Current
10mA
Operating Temperature Range
LM185 Series
-55'Cto 125'C
LM285 Series
-40'C to 85'C
LM385 Series
O'Cto 70'C
Storage Temperature
- 55'C to 150'C
Soldering Information
TO-92 Package (10 sec.)
260'C
TO-46 Package (10 sec.)
300'C
SO Package
Vapor Phase (60 sec.)
215'C
Infrared (15 sec.)
220'C
See An-450 "Surface Mounting Methods and Their Effect
on Product Reliability" (Appendix D) for other methods of
soldering surface mount devices.
Electrical Characteristics (Note 1)
Parameter
Conditions
LM185BX, LM185BV
LM185B, LM285BX
LM285BV, LM285
Typ
Reference Voltage
1.240
IR=100/-LA
Tested
Limit
(Note 2)
Design
Limit
(Note 3)
1.252
LM385BX, LM385BV
LM385
Unit
Limit
Typ
Tested
Limit
(Note 2)
Design
Limit
(Note 3)
1.240
1.252
1.255
Vmax
1.228
1.215
Vmin
1.265
1.215
1.270
1.205
1
15
1.5
25
Vmax
Vmin
mVmax
mVmax
1.255
B-Series
1.228
1.215
LM285 and
LM385
1.240
1.265
1.215
1
10
Reference Voltage
Change with Current
Imin
I
~
'"
III
10
II
o
5 ~ ~ 55 55W51~
TEMPERATURE (OC)
T
V~=51v\
t:!
r--.~
......
....
ill
......
WORST
CASELM385 .......
160
: 15
-50 - 25
ill 50
~
=> 40
:E
=> 3D
:E
V"/
Z 20
~
.-,
i2
10
o
0 25 50 75 100 125
TEMPERATURE (OC)
I'/wORST
b
.,,""
r-
~
TYP@25°C
1
Forward Characteristics
lo~Trrmr~nm~~mr~mmm
1.2 r-T"mm.........,.
VR=VREF
1
15 10 t-+-i~+-t-+--tl1-I
....
.~
=>
w
'"
-2~uw~~~uw~~
0.2 0.4 0.6 0.8 1.0 1.2 1.4
REVERSE VOLTAGE (V)
0.01
Output Noise Voltage
oL-LJUWlIL....L.1.LWIIIL...Ju..u.LIIL.u.
0.1
1
10
REVERSE CURRENT (mA)
100
0.01
Dynamic Output Impedance
0.1
1
10
FORWARD CURRENT (mA)
100
Response Time
100 E;"""-,.---.---::--,:-----.
10,000
§:
i
i
1,000
w
S
z
...zw
g
~--~---+~~
10
E
...'"w
~
!!
100 ~--I------l---I--~H
12Dk
~
...........=>
=>
C>
364K
>
C>
lor-~~~~~--~~
0 _.......----1_ _ _ _- ' -_ _ __
lo~UW~~~~~-U~
10
100
lk
10k
FREQUENCY (Hz)
100
lk
10k
FREQUENCY (Hz)
lOOk
lOOk
50
100 150
TIME ("s)
200
TL/H/S2S0-3
LM185
Temperature Coefficient Typical
LM285
Temperature Coefficient Typical
;f-
o
>
E
Or---~~~------,
LM385
Temperature Coefficient Typical
i
(1.24)
-s. =e
o
o~
__~~---.
!l.Y
-5
-5
5000 -0.5
7000
-10~~--~~--~~~
-55 -25
0.035
0.0028
@]
0 +25
+70 +85 +125
TEMPERATURE (OC)
mV/oC
-55-40
mV/oC
0 +25
+70+85 +125
TEMPERATURE (OC)
0.025
"101°C -+-.L...%/oC _
0.002
ppm/oC
ppm/oC~ TEMPCO =
TDTA~:A~ ,:/pm
7000
Q~ -~OO 0
+25
+70
mV/oC~0.032
'Io/ C--'O.0026
J. Y
ppm/oc-[ID TEMPCO = !l.T
TL/H/S2S0-4
7-71
==
co
.....
r==
co
UI
Co)
CASE LM185
OUTPUT VOLTAGE (V)
Reverse Characteristics
.---.---r---,--,--,.--",.-,
UI
.....
r-
N
70
....
Reverse Characteristics
100
IR!,00'pA
~ 20
i""'"
-55-~-~
Minimum Operating Current
80
25
1~=l~OJA -
I!;
~ 1.240
i5
Feedback Current
UI
Typical Applications (Continued)
Precision 10V Reference
Low AC Noise Reference
15V
15V
HI
HI
5K
lOOK
...__..._~g~T
H2
301K
H2
+
1%
120k
r--...........,
H3
6B.1K
1%
Cl
0.47 "F
H4
33
25V Low Current Shunt Regulator
H3
360 kl!
200 mA Shunt Regulator
V+
V+
H4
H3
---4. . . .
r - -.....
50pA .....- ..--,
HEAT SINK
-,
HI
22k
I
I
12N2905
Iq=70"A
0< lOUT < 50mA
L._ _.J
VoUT=5V
R2
3k
R3
1M
R7
332k
1%
H4
10K
Cl
o.I"F
+
R5
10k
RB
1M
C2
50o"F
1%
-15V
R6
22k
TL/H/5250-5
7-72
Typical Applications (Continued)
Voltage Level Detector
Voltage Level Detector
HI
120k
H2
1M
> -12V
H3
330
-5V
-5V
Fast Positive Clamp
2.4V + ~VDl
I
LEO ON
Bidirectional Clamp
±2.4V
~
VOUT
H2
01
IN914
50"A
...-......_ . , FB
H2
510K
FB ...-......"'-.,
02
IN914
01
IN457
H3
240K
H3
510K
H4
240K
Bidirectional Adjustable Clamp
± 1.8V to ±2.4V
Bidirectional Adjustable Clamp
±2.4Vto ±6V
Y,N
Y,N
HI
HI
r----...----.......
H2
330K
VOUT
02
IN457
fI
Dl
IN457
TLlH/5250-6
7·73
U)
co
C")
:E
....I
.....
U)
co
N
~
;:;,
co
..:E
....I
r------------------------------------------------------------------------------------------,
Typical Applications
-
(Continued)
Simple Floating Current Detector
Current Source
+15V
OT020mA
Rl
390!}
±2%
Rl
lN4002
02
01·
~
1 itA < lOUT < 100 rnA
(OUT= 1.24V
Rl
Precision Floating Current Detector
-
OT020mA
+5V
Rl
332!l
±1%
02
lN4002
R3
lOOk
01·
N.C.
(THRESHOLD = 1.::V =3.7mA±2%
TLlH/5250-7
• 01 can ba any LED, VF= I.SV to 2.2V at 3 rnA. 01 may act as an
indicator. 01 will be on if ITHRESHOLD falls below tha threshold currant,
axcept with 1=0.
7-74
Typical Applications
(Continued)
Centigrade Thermometer, 10 mVI'C
Freezer Alarm
. - - - - - - -....-9V
R5
5Dk
Rl
10k
Rl
lOOk
R2
18Dk
4.5V ,;;,
r-I
I
I
II
TEMP
L!2!!2.R
----,
FB
V+
I
I
I
I
I
J
R5
12k
TL/H/5250-11
BEEPS AT TEMPERATURES ABOVE THAT SET
BY Rl (RANGE IS - 30°F 10 +120°F)
TL/H/5250-12
Schematic Diagram
REFERENCE
FEED8ACK
(FB)
TL/H/5250-6
7-75
en
en
en
M
::i
-I
.....
en
r----------------------------------------------------------------------------,
_
National
Semiconductor
Corporation
en
M
::i
-I
LM 199/LM299/LM399/LM3999 Precision Reference
.....
g:
('II
:5
g.,...
::i
-I
General Description
The LM199 series are precision, temperature-stabilized
monolithic zeners offering temperature coefficients a factor
of ten better than high quality reference zeners. Constructed on a single monolithic chip is a temperature stabilizer
circuit and an active reference zener. The active circuitry
reduces the dynamic impedance of the zener to about 0.5!!
and allows the zener to operate over 0.5 rnA to lOrnA current range with essentially no change in voltage or temperature coefficient. Further, a new subsurface zener structure
gives low noise and excellent long term stability compared
to ordinary monolithic zeners. The package is supplied with
a thermal shield to minimize heater power and improve temperature regulation.
The LM 199 series references are exceptionally easy to use
and free of the problems that are often experienced with
ordinary zeners. There is virtually no hysteresis in reference
voltage with temperature cycling. Also, the LM199 is free of
voltage shifts due to stress on the leads. Finally, since the
unit is temperature stabilized, warm up time is fast.
The LM199 can be used in almost any application in place
of ordinary zeners with improved performance. Some ideal
applications are analog to digital converters, calibration
standards, precision voltage or current sources or precision
power supplies. Further in many cases the LM199 can replace references in existing equipment with a minimum of
wiring changes.
Connection Diagrams
The LM199 series devices are packaged in a standard hermetic TO-46 package inside a thermal shield. The LM199 is
rated for operation from - 55'C to + 125'C while the LM299
is rated for operation from - 25'C to + 85'C and the LM399
is rated from O'C to + 70'C.
The LM3999 is packaged in a standard TO-92 package and
is rated from O'C to + 70'C
Features
Guaranteed 0.0001 %I'C temperature coefficient
Low dynamic impedance - 0.5!!
Initial tolerance on breakdown voltage - 2%
Sharp breakdown at 400 /LA
Wide operating current - 500 /LA to lOrnA
Wide supply range for temperature stabilizer
Guaranteed low noise
Low power for stabilization - 300 mW at 25'C
Long term stability - 20 ppm
Proven reliability, low-stress packaging in TO-46 integrated-circuit hermetic package, for low hystereSis after
thermal cycling. 33 million hours MTBF at TA = + 25'C
(TJ = +86'C)
• Certified long term stability available
•
•
•
•
•
•
•
•
•
•
Functional Block Diagrams
LM199/LM299/LM399
Metal Can Package
+
TLlH/5717 -14
Top View
LM199/LM299/LM399 (See Table on fourth page)
NS Package Number H04D
TL/H/5717-15
LM3999
PlastiC Package TO·92
~
o
TL/H/5717 -10
Bottom View
LM3999 (See Table on fourth page)
NS Package Number Z03A
TL/H/5717-11
7-76
r-
i:
.....
Absolute Maximum Ratings
Specifications for Military/Aerospace products are not
contained in this datasheet. Refer to the following Reliability Electrical Test Specifications documents:
RETS199X for LM199, RETS199AX for LM199A.
Temperature Stabilizer Voltage
LM199/LM299/LM399
LM3999
40V
36V
Reverse Breakdown Current
20mA
Forward Current
LM199/LM299/LM399
LM3999
40V
-0.1V
Reference to Substrate Voltage V(RS) (Note 1)
Operating Temperature Range
LM199
LM299
LM399/LM3999
-55·C to + 125·C
-25·Cto +85·C
-O·Cto +70·C
Storage Temperature Range
-55·Cto +150·C
Soldering Information
TO-92 package (10 sec.)
TO·46 package (10 sec.)
1 mA
-0.1 mA
+ 260·C
+300·C
LM199/LM299
Conditions
Reverse Breakdown Voltage
0.5mA,;; IR';; 10mA
Reverse Breakdown Voltage
Change with Current
0.5 mA ,;; IR ,;; 10 mA
Reverse Dynamic Impedance
IR = 1 mA
Reverse Breakdown
Temperature Coefficient
-55·C,;;TA';; + 85·C }
+ 85·C,;;TA';; + 125·C
-25·C,;;TA,;;85·C
0·C,;;TA';;+70·C
Max
Min
Typ
Max
6.8
6.95
7.1
6.6
6.95
7.3
V
6
9
6
12
mV
0.5
1
0.5
1.5
n
0.00003
0.0005
0.00003
0.0001
0.0015
0.0001
0.00003
0.0002
%I"C
%I"C
%I"C
%I"C
7
20
7
50
/LV
LM299
LM399
10Hz';; f,;; 10kHz
Long Term Stability
Stabilized,22"C,;;TA';;28·C,
1000 Hours, IR = 1 mA ± 0.1 %
20
Temperature Stabilizer
Supply Current
TA = 25·C, Still Air, Vs = 30V
TA=-55·C
8.5
22
Vs = 30V, TA = 25·C
Initial Turn-on Current
9,;;Vs,;;40, TA= + 25·C, (Note 3)
14
28
8.5
15
9
3
140
ppm
20
40
9
Warm-Up Time to 0.05%
Units
Typ
LM199
Temperature Stabilizer
Supply Voltage
LM399
Min
RMSNoise
40
3
200
mA
V
sec.
140
mA
200
Electrical Characteristics (Note 2)
LM3999
Parameter
Units
Conditions
Reverse Breakdown Voltage
0.6 mA ,;; IR ,;; 10 mA
Reverse Breakdown Voltage
Change with Current
0.6 mA ,;; IR ,;; 10 mA
Reverse Dynamic Impedance
IR = 1 mA
Reverse Breakdown
Temperature Coefficient
O·C,;; TA';; 70·C
i:
N
CD
~
ri:
Co)
CD
CD
"r-
i:
Co)
CD
CD
CD
Electrical Characteristics (Note 2)
Parameter
CD
CD
"r-
Min
Typ
Max
6.6
6.95
7.3
V
6
20
mV
0.6
2.2
n
0.0002
0.0005
%I·C
RMSNoise
10Hz';; f,;; 10kHz
7
/LV
Long Term Stability
Stabilized, 22·C ,;; T A ,;; 28·C,
1000 Hours, IR = 1 mA ±0.1 %
20
ppm
Temperature Stabilizer
T A = 25·C, Still Air, Vs = 30V
12
Temperature Stabilizer
Supply Voltage
Warm-Up Time to 0.05%
Vs = 30V, TA = 25·C
Initial Turn-On Current
9 ,;; Vs ,;; 40, T A = 25·C
18
mA
36
V
sec.
5
7-77
140
200
mA
Electrical Characteristics (Note 2)
Parameter
LM199A, LM299A
Conditions
Reverse Breakdown Voltage
O.S mA:S: IR :S: 10 mA
Reverse Breakdown Voltage
Change with Current
O.S mA:S: IR :S: 10 mA
Reverse Dynamic Impedance
IR = 1 mA
Reverse Breakdown
Temperature Coefficient
-SS'C:S:TA:S: +8S'C }
+8S'C:S:TA:S: + 12S'C
-2S'C:S:TA:S:8S'C
O'C:S:TA:S: +70'C
Typ
Max
Min
Typ
Max
6.8
6.9S
7.1
6.6
6.9S
7.3
V
6
9
6
12
mV
O.S
1.S
n
0.00003
0.0001
%/'C
%/'C
%/'C
%/'C
7
SO
p.V
LM299A
LM399A
O.S
1
0.00002
O.OOOS
0.00002
O.OOOOS
0.0010
O.OOOOS
20
RMSNoise
10Hz:s: f:S: 10kHz
7
Long Term Stability
Stabillzed,22'C:S:TA:S:28'C,
1000 Hours,IR=1 mA±0.1%
20
Temperature Stabilizer
Supply Current
TA=2S'C, Still Air, Vs=30V
TA =- SS'C
8.S
22
20
14
28
9
Warm-Up Time to O.OS%
Vs = 30V, TA = 2S'C
Inltlal Turn-on Current
9:S:Vs:S:40, TA= +2S'C, (Note 3)
Units
Min
LM199A
Temperature Stabilizer
Supply Voltage
LM399A
8.S
40
9
ppm
1S
40
3
3
140
V
sec.
140
200
mA
200
mA
Electrical Characteristics (Note 2)
Parameter
Conditions
Reverse Breakdown Voltage
O.S mA:S:IR:S:10 mA
Reverse Breakdown Voltage
Change With Current
0.5 mA:S:IR:S: 10 mA
LM 199AH-20, LM299AH-20
LM399AH-50
Units
Min
Typ
Max
Min
Typ
Max
6.8
6.95
7.1
6.6
6.9S
7.3
V
6
9
6
12
mV
0.5
1
O.S
1.5
n
0.00002
O.OOOS
0.00002
O.OOOOS
0.0010
O.OOOOS
Reverse Dynamic Impedance IR = 1 mA
Reverse Breakdown
Temperature Coefficient
-SS'C:S:TA:S:8S' }
LM199A
8S'C:S:TA:S:12S'C
-2S'C:S:TA:S:8S'C LM299A
LM399A
O'C:S:TA:S:70'C
RMSNoise
10 Hz:S:f:S:10 kHz
7
20
7
SO
p.V
Long Term Stability
Stabilized, 22'C:s: TA:S: 28'C,
1000 Hours, IR= 1 mA±0.1%
8
20
9
50
ppm
Temperature Stabilizer
Supply Current
TA=2S'C, Still Air, Vs=30V
TA=SS'C
8.S
22
14
28
8.5
1S
0.00003 0.0001
Temperature Stabilizer
Supply Voltage
9
Warm-Up Time to O.OS%
Vs=30V, TA = 2S'C
Initial Turn-on Current
9:S:Vs:S:40, TA = 2S'C, (Note 3)
40
3
140
9
140
mA
40
V
200
mA
3
200
%/'C
%/'C
%l'C
%/'C
s
Note 1: The substrate Is electrically connected to the negative terminal of the temperature stabilizer. The voltage that can be applied to either terminal of the
reference is 40V more positive or O.tV more negative than the substrate.
Note 2: These specifications apply for 30V applied to the temperature stabilizer and - 55"C';;TA';; + I 25"C for the LM199; - 25"C';;TA';; + 85"C for the LM299 and
O"C';;TA';; +70"C lor the LM399 and LM3999.
Note 3: This initial current can be reduced by adding an appropriate resistor and capacitor to the heater circuit. See the performance characteristic graphs 10
determine values.
Note 4: Do not wash the LMI99 with its polysullone thermal shield In TCE.
7-78
Ordering Information
Initial
Tolerance
NS
Package
O"Cto +70"C
- 2SDC to + 85"C
- SSDC to + 12SDC
LM299AH
LM199AH
H04D
5%
LM399H
LM399AH
LM299H
LM199H
H04D
5%
LM3999Z
2%
Guaranteed Long
Term Stability
Z03A
LM399AH-50
LM299AH-20
LM199AH-20
H04D
Certified Long Term Drift
The National Semiconductor LM199AH-20, LM299AH-20,
and LM399AH-50 are ultra-stable Zener references specialIy selected from the production runs of LM199AH,
LM299AH, LM399AH and tested to confirm a long-term stability of 20, 20, or 50 ppm per 1000 hours, respectively. The
devices are measured every 168 hours and the voltage of
each device is logged and compared in such a way as to
show the deviation from its initial value. Each measurement
is taken with a probable-worst-case deviation of ±2 ppm,
compared to the Reference Voltage, which is derived from
several groups of NBS-traceable references such as
LM199AH-20's, 1N827's, and saturated standard cells, so
that the deviation of anyone group will not cause false indications. Indeed, this comparison process has recently been
automated using a specially prepared computer program
which is custom-designed to reject noisy data (and require a
repeat reading) and to record the average of the best 5 of 7
readings, just as a sagacious standards engineer will reject
unbelievable readings.
The typical characteristic for the LM199AH-20 is shown below. This computerized print-out form of each reference's
stability is shipped with the unit.
Typical Characteristics
National Semiconductor
Certified Long Term Drift
Hrs
Drift
168
336
504
672
840
1008
-20
-24
-36
-34
-40
-36
120
LM199AH-20
Part #6849
Limits
LM199AH-20
LM299AH-20
LM399AH-20
140/LV
140/LV
350/LV
0
R
I
F
T
.L'V
80
40
0
----
-40
---
-813
Testing Conditions
Heater Voltage
30V
Zener Current
1 mA
Ambient Temp.
25DC
-1213
0
168
336
504
672
840 113138
HOURS
TUHI5717 -12
PI
7-79
Typical Performance Characteristics
Reverse Characteristics
Dynamic Impedance
Reverse Voltage Change
1l1li
....
..,..
a.
5
I
I
10-'
~
ID-'
i:
T,' ZI"C
I000o"''I'
10"
V
~
H
~
A1f.ABILlZ~1
IT, ,IUC)
-
10""
&.15
&.is
&.45
~
,.1"'
1
~
/
:>
.!!
J
10
"
-I
~
"
STABILIZED IT, ,10 C) _
T. -25 C
-Z
~
E
!!
11liii0
Heater Current
--
c
60
.!!
....
..
40
,
.,~
zo
::;
i::
i
I
VH 15V
o~~~~~~~~~
-4
100
Ik
10k
a
lOOk
zo
IZ
16
HEATER ON TIME -ISEC)
-55 -35 -Ii 5 Z5 45 65
TEMPERATURE I"C)
Heater Current (To Limit This
Surge, See Next Graph)
..~
S
160
VH I.4Jv
.,~
10k
FREQUENCV 1Hz)
~
Initial Heater Current
~
Ik
100
10
.
-3
Z5D
C IZD
...... 1'-
.!!
....
...... 1'-
100
.
..B
100
.,~
40
::;
t"--
~
sa
.... -
a
TA "'25 C
140
zoo
150
/
L.......... -{'Z5"CE
1.0
/ ,
FREQUENCV IH.)
..i::
..
I
STA'ILlZE~
IT"IO"C)
0.1
/ ,,,~~.-J5C
....
~
100
50
::;
."
Stabilization Time
\
w
....
.,ic
I
80
2!
.!!
i..
I
TAl,s c
C
II
c
REVERSE CURRENT ImA)
Zener Noise Voltage
:i
w
10
zoo
~
'"Ii!
ZI"C _
1.05
US
REVERSE VOLTAGE IV)
~ ISO
./
STA81L1Z~
IT, ,1j"C)
I I
I'-
I'v
10
ZO
o
Z 4
TURN QN TEMPERATURE I"C)
6 8 II
~ ~
.. 100
- 600
I-.I-;±-±",d--l-hl'f--I
500
:e 40D
:;
~ 300 1-+--+--+-:;l"-:;jiD~~::;ooo1
;: zoo I--t-+--J.~~ofio"'f'--l-l
~
! 100
i
1
-51 -35 -Ii 5 Z5 45 65 85 IDS IZ5
.-,---r-r-.-,---r-r---,
E
~~ ~tl1 1 1
~
60
Heater Surge Limit Resistor vs
Minimum Supply Voltage at
Various Minimum Temperatures
800
li!
VVH )IOJVH'ZD~_
!--VH'
30V
\\~YI..1
85 IDS
Ii ID
20
10
TIME ISEC)
40
MINIMUM SUPPLY VQLTAGE IV)
TL/H/S717-2
• Heater must be bypassed with a 2
"F or larger tantalum capacitor if resistors are used.
Response Time
Low Frequency Noise Voltage
QliTPUT
ff~~'
Y""
"'~
"1-:;
'"
-0
i"'
"
0.01 Hz:>t:>1 Hz
STABILIZED
IT, ·90"C)
":b
I'
~
">
I~'
I'''UI
,
10
10
TIME
TL/H/S717-3
OIll'Ul
-
e--e---
"""'-
-
INPUT- r---
100
10
TIME IMINUTES)
cy. rI T,.15 C- -
E
"\{+;@.,!JI %:< ~ ~
(
STAIILlZED
IT, '190
ZOO
300
400
(~sl
TL/H/5717-7
7-80
Typical Applications
Single Supply Operation
Split Supply Operation
+ 15V--....- - - - ,
9V TO 4 0 V - - 1 . - - - - - ,
".
TEMPERATURE
HMPERATURE
STABILIZER
STABILIZER
695V
69SV
-ISV
Negative Heater Supply with
Positive Reference
Buffered Reference
With Single Supply
.
·1~V-------.,
• 15V--....- - - -....- - - - - - - . . . ,
ISk
TEMPERATURE
STABILIZER
TEMPERATURE
IOV
STABILIZER
695V
695V
9V TO
3lV
Positive Current Source
lOV T040V-....- - - -....- -....-----"""'I~----....,
,SO
0.196
TEMPE RATURE
STABILIZER
69&V
lM199
43.
Standard Cell Replacement
15VT02DV--....- - - - - . - - - - - - - - - - - - - . . . ,
1% REGULATED
7.5k
...--.....---, ~gJ~~:
lOOk
TEMPERATURE
STABILIZER
OUTPUT
6.95V
TL/H/5717-4
7-81
Typical Applications (Continued)
Negative Current Source
1.5.
!G'
-"V--_~---~~-~~---""--------"'"
Square Wave Voltage Reference
Portable Calibrator'
-L
8.811
1%
tlSV
\OF
1Sk
SUI~
..........N>I'-_~-""'N--....-+'i
TEMPERATURE
STABILIZER
~
.OUTPUT
"".r
200k
18V--
ISDk
lN4S1
LMI99
+
19k
TEMPERATURE
1%
STAIIILIUR
6.95V
oTO IOV
INPUT
SQUARE WAVE
3k
L::+_~L;;;M;.;;19;;;'_-lI-..... TRIM
'Warm-up time 10 seconds; intermittent operation does not degrade longterm stability.
14V Reference
Precision Clamp'
CLAMP
INPUT
R,
TEMPERATURE
STABILIZER
t-------....
--OUTPUT
69SV
lN914
+lSV--. . .- - - - - ,
lMt99
ISk
+
TEMPERATURE
STABILIZER
TEMPERATURE
STABILIZER
69SV
6.9SV
lM199
LM199
IN9"
":' 'Clamp will sink 5 mA when input goes more posHive than reference
TLlH/5717-5
7-82
Typical Applications (Continued)
OV to 20V Power Reference
IIV'04IV'--_t----_t---------------...-------,
LM1951C
t---t--i--"""'I'v---+-:m l~V
IV
Bipolar Output Refarenca
SDk
.'5V---4.....- - - - - .
7,5k
OUrPU' 'I.9V
TEMPERATURE
SfA81LIlER
~Dk)~""'--~
no~v
l~V
LM199
ISV
TL/H/5717-6
Voltage Reference
....---....-----------__,
TO:~~--
Uk
'"
0,1"
TEMPERATURE
STAIILlZER
8.I&V
LM3111
,..
OUTPUT
t01V
"UK
TLlH/5717-9
I
7·B3
CD , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
CD
CD
C")
:i
a;
CD
C")
Schematic Diagrams
Temperature Stabilizer
r-----~--------------_.------------_.~--------~J v'
....a;:::::E
CD
C'I
....
a;
CD
....
:::::E
....
:::::E
2k
42
~----------~--~--~~--~~----~~--_4----~4
V
TL/H/5717-01
Reference
OJ
6.JV
JO pF
10k
2k
JOk
~------4_--~--------~------------~--~2
7-84
-
TLlH/5717-13
r-------------------------------------------------------------------------, r
NatiOnal
~ Semiconductor
PRELIMINARY
s:::
c.)
en
00
N
Corporation
U,
LM368-2.5 Precision Voltage Reference
General Description
Features
The LM368-2.5 is a precision, monolithic, temperature-compensated voltage reference. The LM368-2.5 makes use of
thin-film technology enhanced by the discrete laser trimming of resistors to achieve excellent Temperature coefficient (Tempco) of VOUT (as low as 11 ppmI"C), along with
tight initial tolerance, (as low as 0.02%). The trim scheme is
such that individual resistors are cut open rather than being
trimmed (partially cut), to avoid resistor drift caused by electremigration in the trimmed area. The LM368-2.5 also provides excellent stability vs. changes in input voltage and
output current. The output is short circuit proof. A trim pin is
made available for fine trimming of VOUT or for obtaining
intermediate values without greatly affecting the Tempco of
the device.
•
•
•
•
•
•
•
•
400 !LA operating current
Low output impedance
Excellent line regulation (.0001 %/V typical)
Single-supply operation
Externally trimmable
Low temperature coefficient
Excellent initial accuracy (0.02% typical)
Best reference available for low-voltage operation
(Vs = 5V, VREF = 2.500V)
Connection Diagrams
Dual-In-Line Package (N)
or S.O. Package (M)
Metal Can Package
Ne
y+NcOaNC
NC
2
y-
7
3
6
OUTPUT
4
5
ADJ
TLlH/8446-15
Top View
Order Number LM368M-2.5 or LM368N-2.5
See NS Package Number M08A or N08E
TL/H/8446-1
Top View
"'case connected to vOrder Number LM368H-2.5 LM368YH-2.5
See NS Package Number H08C
Typical Applications
Low Voltage Reference
4.5V-30V
2
TL1H/8446-2
7-85
I
Absolute Maximum Ratings (Note 7)
If MIlitary/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Input Voltage
35V
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Soldering Information
DIP (N) Package (10 sec.)
+ 260·C
TO-5 (H) Package (10 sec.)
+300·C
+215·C
SO (M) Package, Vapor Phase (60 sec.)
Infrared (15 sec.)
+ 220·C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" (Appendix D) for other methods of
soldering surface mount devices.
600mW
- 60·C to + 150·C
O·Cto +70·C
Electrical Characteristics (Note 1)
LM368-2.5
Parameter
Conditions
VOUT Error: LMS6B
Typical
Tested
Limit
(Note 2)
±0.02
±0.2
Design
Limit
(Note 3)
Units
(Max. unless
noted)
%
Line Regulation
5.0V ~ VIN ~ SOV
±0.0001
±0.0005
%N
Load Regulation (Note B)
o mA ~ ISOURCE ~ 10 mA
±O.OOOS
±0.0025
%/mA
Thermal Regulation
T = 20 mS (Note 4)
±0.005
±0.02
%/100mW
S50
550
p,A
p,AN
Quiescent Current
Change of Quiescent Current vs. VIN
5.0V ~ VIN ~ SOV
S
5
Temperature Coefficient
of VOUT (see graph): LMS6BY-2.5
(Note 5)
LM36B-2.5
O·C ~ TA ~ 700C
O·C ~ TA ~ 70·C
±11
±15
±20
Short Circuit Current
VOUT = 0
SO
70
Noise:
0.1-10Hz
100 Hz-10 kHz
12
420
±30
100
ppm/·C
ppmrc
mA
uVp-p
nV/.jHz
1.9-5.2
2.2-5.0
V min.
VOUT Adjust Range
o ~ VPIN5 ~ VOUT
Note 1: Unless otherwise noted. Ihese speclficallans apply: TA = 25'C,4.9V ,,; VIN ,,; 10.5V, 0"; ILOAD ,,; 0.5 mA, 0,,; CL ,,; 200 pF.
Nole 2: Tesled Umlls are guaranteed and 100% tested in production.
Note 3: DeSign Limits are guaranteed (but not 100% production tested) over the indicaled temperature and supply voltage ranges. These limits are nat used to
calculate outgoing quality levels.
Note 4: Thermal Regulation Is defined as the change In the aulput Voltage at a time Taller a slep change In power dissipation of 100 mW.
Note 5: Temperalure Coeificienl of Your Is defined as Ihe worsl case delta-Vour measured al Specified Temperalures divided by Ihe lotal span of Ihe Specified
Temperalure Range (See graphs). There is no guaranlee thallhe Specified Temperalures are exactly allhe minimum or maximum deviation.
Note 6: In melal can (H), 6J-C is 75'C/W and 6J.A is 150'C/W. In plaslic DIP, 6J.A is lBO'C/W. In SO-B, 6J.A is 180'C/W, in TO-92, 9J.A Is lBO'C/W.
Note 7: Absolule Maximum Ratings Indicate limits beyond which damage 10 Ihe device may occur. DC and AC electrical specificalions do nol apply when operallng
the device beyond its Raled Operallng Condilions (see Nole 1 and Conditions).
Note 6: Load regulation is measured on the oulpul pin at a paint Va" below the base of the package. Regulation is measured at constant junction tamperature,
using pulse tesling with a low duty cycle. Changes in output vollage due to heating effects are covered under the specification for thermal regulation.
7-B6
r-----------------------------------------------------------------------------'r
a:::::
Typical Performance Characteristics (Note 1)
Quiescent Current vs. Input
Voltage and Temperature
Dropout Voltage vs.
Output Current
Output Change vs.
Output Current
500
...:
25°C'" 1,...00
-55°C
-
~
S
;: ....
.
--
i-""
il
_~5~oCI
~
;::
J!:l .... ~~ .......
o
i§
0
o
..
~
~
0.1
Si
ii!
~
i'
0.01
lOOk
IDD
(3) with Ion in series with 10 ,.1,
VOUTto Gnd.
(4) with Both.
"
~
ID
as is.
(2) with 0.01 ,.1 Mylar, Trim to Gnd.
4
LJ'
D.GOOI
100
lk
10k
FREDUENCY (Hz)
(1) LM368
~ 31-
/
ii!
0.01
l.oiii
I~
~0.001
100'"
10
10
OUTPUT CURRENT (mA)
I
0.1
~
~ 4
~
o
10
8
OUTPUT CURRENT (mA)
I
>
~~
!!
-0.2
Ripple Rejection vs.
Frequency
3, ~
~
SOURCING
...~ -0.1
~
I
u
0.1
c
~
-0.3
-D.4
Output Impedance vs.
Frequency
10
0.2
~
~
10
20
30
INPUT VOLTAGE (V)
100
>
~
z:
.... 25°C
~
~
~
i.n
0.3
2
.e
i\,
0.4
125°C
lao
~
co
Ik
10k lOOk
FREDUENCY (Hz)
Temperature Coefficient:
LM368-2.5 (Curve A)
1M
Output NOise vs.
Frequency
1600
~
~--
"
I
I
1-
!T.
fl20D
;
N.l.7mv
___ I
1-70 0 _
1
: I
o 25
I
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I
!i!800
~J
~
~
.. 400
I
7085
TEMPERATURE (OC)
D
lD
125
......
lao
lk
FREDUENCY (Hz)
lot
TL/H/8446-3
Typical Temperature Coefficient Calculations:
LM368·2.5 (see Curve A)
T.C.~1.7
~9.7
mVl(70"x2.5V)
ppml'C
7-87
i
Typical Applications
~
Wide Range Trlmmable Regulator
Narrow Range Trlmmable Regulator (± 1"10 min.)
r .........'.!...--.....
-VOUT
VOUT
...._~..r......;~
5
Rl
2M
L..""T'!~r--'lV'W"~ 2Uk
20k
TLlH/B446-5
TLlH/B44B-B
Improved Noise Performance
r .....~'.!...---.....
VOUT
10pf
TL/H/8446-7
± 2.5V. ± 1.25V References
U50V
-USGV
t>
R~
~
y. LM324A or
y. LM358A
TLlH/8446-B
Thin Film Resistor Network.
±O.05% Matching and 5 ppm Tracking
(Beckman 694-3-R-l0K-A),
(Caddock T-914-10K-l00-05)
or similar.
7-88
Typical Applications (Continued)
Multiple Output Voltages
Y·
r--~"'l.!!.... 5.000Y
r .....--'1!.-~-- 2.S00V
Uk
TLlH/8446-9
Y·
5.000V
R
~
Thin Film Resistor Network
0.05% Malching and 5 ppm Tracking
(Beckman 694-3-R-l0K·A),
(Caddock T-914·10K-l00-05)
or similar.
r ........,.L'---I-~I-- 2.SDOV
TLlH/8446-10
Reference with Booster
100 mA Boosted Reference
Y+~S.OV
Y·;;'5.5V
3.3
680
2N2907
100-200
r....ll.o..'.!...._~
lW
____
...._
~ (OPTIONAL
~ PRE-LOAD)
-----_.
Your ~ 2.S00V
r-....-,~-~-----t-
+
!50/JoF
VOUT - 7.S00V
TL/H/8446-11
TLlH/8448-12
7-89
i
U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
Typical Applications
(Continued)
~
Buffered High-Current Reference with Filter
+i.1V
10k
10k
3.3
L---+--Ir---~....--_1~ Vour-2•50OV
3.3k
TLlH/8446-13
Simplified Schematic Diagram
~------------------------~-_.-V+
20
-t---"""'!r- VDUT
1811
1.5k
75k
SDk
5 pF
5Dk
I - -.....wv- TRIM
55k
12k
~----------~--~~--~--~~_~--~-----V'Reg.
u.s. Pal. Off.
7-90
TL/H/6446-14
,-------------------------------------------------------------------------, r
3:
NatiOnal
ADVANCED INFORMATION en
~ Semiconductor
.....
CD
Corporation
LM581 Precision 10-Volt Voltage Reference
General Description
Features
The LM581 Series are precision monolithic temperaturecompensated voltage references. They are based on a buried zener reference as pioneered in the LM199 references,
but do not require any heater, as they rely on special temperature-compensation techniques (Patent Pending). The
LM581 makes use of thin-film technology enhanced by the
discrete laser trimming of resistors to achieve excellent
Temperature coefficient (Tempco) of Vout (as low as 1
ppml"C), along with tight initial tolerances (as low as
0.01 %). The trim scheme is such that individual resistors
are cut open rather than being trimmed (partially cut), to
avoid resistor drift caused by electromigration in the
trimmed area. The LM581 also provides excellent stability
vs. changes in input voltage and output current (both sourcing and sinking). The devices have a 10.000V output and
will operate in either series or shunt mode; the output is
short-circuit-proof to ground.
• Low Tempco of Vout
• Excellent initial accuracy (0.008%)
iii Excellent line regulation (2 ppmlV)
• Excellent output impedance
• Excellent thermal regulation
• Low noise
• Low dissipation - 20 mW
• Operates in series or shunt mode
• Direct replacement for AD581
Connection Diagram
Typical Applications
Metal Can Package
Series Regulator
OUTPUl
~ GND
~
INPUT~~ 0 !1~ICASEI
+YS
~
BOTTOM VIEW
TLIH19217-1
TLIH19217-2
(Case is connected to ground.)
Order Number LM581JH, LM581KH,
LM581LH, LM581SH, LM581TH or LM581UH
See NS Package Number H03S
Shunt Regulators
+10.000Y
TLIH19217-4
-10.000Y
TLIH19217-3
fI
7-91
Section 8
Surface Mount
Section 8 Contents
Surface Mount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . .
8·2
8-3
r--------------------------------------------------------------------------, c0
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::::.
National
II)
Semiconductor
Corporation
n
CD
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-
Surface Mount
Cost pressures today are forcing many electronics manufacturers to automate their production lines. Surface mount
technology plays a key role in this cost-savings trend because:
1. The mounting of devices on the PC board surface eliminates the expense of drilling holes;
2. The use of pick-and-place machines to assemble the PC
boards greatly reduces labor costs;
3. The lighter and more compact assembled products resulting from the smaller dimensions of surface mount
packages mean lower material costs.
SURFACE MOUNT PACKAGING AT NATIONAL
To help our customers take advantage of this new technology, National has developed a line of surface mount packages. Ranging in lead counts from 3 to 360, the package
offerings are summarized in Table I.
Lead center spacing keeps shrinking with each new generation of surface mount package. Traditional packages (e.g.,
DIPs) have a 100 mil lead center spacing. Surface mount
packages currently in production (e.g., SOT, SOIC, PCC,
LCC, LDCC) have a 50 mil lead center spacing. Surface
mount packages in production release (e.g., PQFP) have a
25 mil lead center spacing. Surface mount packages in development (e.g., TAPEPAKTM) will have a lead center spacing of only 12-20 mils.
Production processes now permit both surface mount and
insertion mount components to be assembled on the same
PC board.
TABLE I. Surface Mount Packages from National
Package
Type
Small Outline
Transistor
(SOT)
Small Outline
IC(SOIC)
Plastic Chip
Carrier (PCC)
Plastic Quad
Flat Pack
(PQFP)
f§J
o
ti, ~
"
Package
Material
Lead Bend
TAPEPAKTM
(TP)
Leadless Chip Leaded Chip
Carrier (LCG) Carrier
(LDCC)
,DoD
V ,'", ," , ", ',
a
~o
tIiIID&iJIJ{!j
"""HR'"
Plastic
Plastic
Plastic
Plastic
Plastic
Ceramic
-
15' '
Ceramic
Gull Wing
Gull Wing
J-Bend
Gull Wing
Gull Wing
Lead Center
Spacing
50 Mils
50 Mils
50 Mils
25 Mils
20,15,12 Mils
50 Mils
50 Mils
Tape & Reel
Option
Yes
Yes
Yes
tbd
tbd
No
No
TP-40 (»
TP-68
TP-84
TP-132
TP-172
TP-220
TP-284
TP-360
LCC-18
LCC-20(»
LDCC-44
LCC-28
LDCC-68
LCC-32
LCC-44(*)
LCC-48
LCC-52
LCC-68
LCC-84
LCC-124
LDCC-84
Lead Counts SOT-23
High Profile
SOT-23
Low Profile
50-8(»
50-14(»
PCC-20(»
PCC-28(»
50-14 Wide(»
50-16(*)
SO-16Wide(*)
50-20(*)
50-24(*)
PCC-44(»
PCC-68
PCC-84
PCC-124
PQFP-84
PQFP-100
PQFP-132
PQFP-196(*)
PQFP-244
·In production (or planned) for linear products.
8-3
Gull Wing
LDCC-124
D
LINEAR PRODUCTS IN SURFACE MOUNT
Linear functions available in surface mount include:
• Op amps
TABLE II: Surface Mount Package
Thermal Resistance Range'
Package
• Comparators
• Regulators
• References
• Data conversion
• Industrial
• Consumer
• Automotive
A complete list of linear part numbers in surface mount is
presented in Table III. Refer to the datasheet in the appropriate chapter of this databook for a complete description of
the device. In addition, National is continually expanding the
list of devices offered in surface mount. If the functions you
need do not appear in Table III, contact the sales office or
distributor branch nearest you for additional information.
Automated manufacturers can improve their cost savings by
using Tape-and-Reel for surface mount devices. Simplified
handling results because hundreds-to-thousands of semiconductors are carried on a single Tape-and-Reel pack (see
ordering and shipping information-printed later in this section-for a comparison of devices/reel vs. devices/rail for
those surface mount package types being used for linear
products). With this higher device count per reel (when compared with less than a 100 devices per rail), pick-and-place
machines have to be re-Ioaded less frequently and lower
labor costs result.
Thermal Resistance'·
(BIA. ·C/W)
SO-8
SO-14
SO-14 Wide
SO-16
SO-16 Wide
SO-20
SO-24
120-175
100-140
70-110
90-130
70-100
60-90
55-85
PCC-20
PCC-28
PCC-44
70-100
60-90
40-60
"Actual thermal resistance for a particular device depends on die size.
Refer to the datasheet for the actual 8jA value.
"Test conditions: PCB mount (FR4 material), still air (room temperature),
copper traces (150 x 20 x 10 mils).
Given a max junction temperature of 150·C and a maximum
allowed ambient temperature, the surface mount device will
be able to dissipate less power than the DIP device. This
factor must be taken into account for new designs.
For board conversion, the DIP and surface mount devices
would have to dissipate the same power. This means the
surface mount circuit would have a lower maximum allowable ambient temperature than the DIP circuit. For DIP circuits where the maximum ambient temperature required is
substantially lower than the maximum ambient temperature
allowed, there may be enough margin for safe operation of
the surface mount circuit with its lower maximum allowable
ambient temperature. But where the maximum ambient temperature required of the DIP current is close to the maximum allowable ambient temperature, the lower maximum
ambient temperature allowed for the surface mount circuit
may fall below the maximum ambient temperature required.
The circuit designer must be aware of this potential pitfall so
that an appropriate work-around can be found to keep the
surface mount package from being thermally overstressed
in the application.
With Tape-and-Reel, manufacturers save twice-once from
using surface mount technology for automated PC board
assembly and again from less device handling during shipment and machine set-up.
BOARD CONVERSION
Besides new designs, many manufacturers are converting
existing printed circuit board designs to surface mount. The
resulting PCB will be smaller, lighter and less expensive to
manufacture; but there is one caveat-be careful about the
thermal dissipation capability of the surface mount package.
Because the surface mount package is smaller than the traditional dual-in-Iine package, the surface mount package is
not capable of conducting as much heat away as the DIP
(i.e., the surface mount package has a higher thermal resistance-see Table II).
The silicon for most National devices can operate up to a
150·C junction temperature (check the datasheet for the
rare exception). Like the DIP, the surface mount package
can actually withstand an ambient temperature of up to
125·C (although a commercial temperature range device
will only be specified for a max ambient temperature of 70·C
and an industrial temperature range device will only be
specified for a max ambient temperature of 85·C). See
AN-336, "Understanding Integrated Circuit Package Power
Capabilities", (reprinted in the appendix of each linear databook volume) for more information.
SURFACE MOUNT LITERATURE
National has published extensiVe literature on the subject of
surface mount packaging. Engineers from packaging, quality, reliability, and surface mount applications have pooled
their experience to provide you with practical hands-on
knowledge about the construction and use of surface mount
packages.
The applications note AN-450 "Surface Mounting Methods
and their Effect on Product Reliability" is referenced on
each SMD datasheet. In addition, "Wave Soldering of Surface Mount Components" is reprinted in this section for your
information.
8-4
U)
c
TABLE III. Linear Surface Mount Current Device Listing
Amplifiers and Comparators
Part Number
LF347WM
LF351M
LF451CM
LF353M
LF355M
LF356M
LF357M
LF444CWM
LM10CWM
LM10CLWM
LM308M
LM308AM
LM310M
LM311M
LM318M
LM319M
LM324M
LM339M
LM346M
LM348M
LM358M
LM359M
Data Acquisition Circuits
Part Number
Part Number
LM392M
LM393M
LM741CM
LM1458M
LM2901M
ADC0802LCV
ADC0802LCWM
ADC0804LCV
ADC0804LCWM
ADC0808CCV
ADC0809CCV
LM2902M
LM2903M
LM2904M
LM2924M
LM3403M
ADC0811BCV
ADC0811CCV
ADC0819BCV
ADC0819CCV
ADC0820BCV
ADC0820CCV
LM4250M
LM324M
LM339M
LM365WM
LM607CM
LMC669BCWM
LMC669CCWM
LF441CM
DAC0808LCM
DAC0830LCWM
DAC0830LCV
DAC0832LCWM
DAC0832LCV
Industrial Functions
Part Number
Part Number
LM317LM
LF3334M
LM2931M·5.0
LM3524M
LM78L05ACM
LM78L12ACM
LM78L15ACM
LM385M
LM385M·1.2
ADC1025BCV
ADC1025CCV
DAC0800LCM
DAC0801LCM
DAC0802LCM
DAC0806LCM
DAC0807LCM
ADC0838BCV
ADC0838CCV
ADC0841BCV
ADC0841CCV
ADC0848BCV
ADC0848CCV
ADC1005BCV
ADC1005CCV
Regulators and References
LM336M·2.5
LF336BM·2.5
LM336M·5.0
LM336BM·5.0
LM337LM
Part Number
LM79L05ACM
LM79L12ACM
LM79L15ACM
LP2951ACM
LP2951CM
Part Number
Part Number
AH5012CM
LF13331M
LF13509M
LF13333M
LM555CM
LM13600M
LM13700M
LMC555CM
LM567CM
MF4CWM·50
LM556CM
LM567CM
LM1496M
LM2917M
MF4CWM·100
MF6CWM-50
MF10CCWM
MF6CWM-100
MF5CWM
LM3046M
LM3086M
LM3146M
LM385BM·1.2
LM385M·2.5
LM385BM-2.5
LM723CM
LM2931CM
Commercial and Automotive
8-5
Part Number
Part Number
LM386M·1
LM592M
LM831M
LM832M
LM833M
LM1837M
LM1851M
LM1863M
LM1865M
LM1870M
LM837M
LM838M
LM1131CM
LM1894M
LM1964V
LM2893M
LM3361AM
LM1881M
~
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Hybrids
Part Number
Part Number
LHOO02E
LH4002E
LH0032E
LH0033E
A FINAL WORD
National is a world leader in the design and manufacture of
surface mount components.
Because of design innovations such as perforated copper
leadframes, our small outline package is as reliable as our
DIP-the laws of physics would have meant that a straight
"junior copy" of the DIP would have resulted in an "S.O."
package of lower reliability. You benefit from this equivalence of reliability. In addition, our ongoing vigilance at each
step of the production process assures that the reliability we
designed in stays in so that only devices of the highest quality and reliability are shipped to your factory.
Package
Package
Designator
Max/Rail
Per Reel"
SO-8
SO-14
SO-14 Wide
SO-16
SO-16 Wide
SO-20
SO-24
M
M
WM
M
WM
M
M
100
50
50
50
50
40
30
2500
2500
1000
2500
1000
1000
1000
V
V
V
50
40
25
1000
1000
500
PQFP-196
VF
TBD
TP-40
TP
100
E
E
50
25
PCL-20
PCL-28
PCL-44
LCC-20
LCC-44
Our surface mount applications lab at our headquarters site
in Santa Clara, California continues to research (and publish) methods to make it even easier for you to use surface
mount technology. Your problems are our problems.
TBD
-
·Incremental ordering quantities. (National Semiconductor reserves the right
to provide a smaller quantity of devices per Tape·and·Reel pack to preserve
lot or date code integrity. See example below.)
Example: You order 5,000 LM324M ICs shipped in Tapeand-Reel.
When you think "Surface Mount"-think "National"l
• Case 1: All 5,000 devices have the same date code
Ordering and Shipping Information
• You receive 2 SO-14 (Narrow) Tape-and-Reel
packs, each having 2500 LM324M ICs
When you order a surface mount semiconductor, it will be in
one of the several available surface mount package types.
Specifying the Tape-and-Reel method of shipment means
that you will receive your devices in the following quantities
per Tape-and-Reel pack: SMD devices can also be supplied
in conventional conductive rails.
• Case 2: 3,000 devices have date code A and 2,000 devices have date code B
• You receive 3 SO-14 (Narrow) Tape-and-Reel
packs as follows:
Pack # 1 has 2,500 LM324M ICs with date code A
Pack # 2 has 500 LM324M ICs with date code A
Pack #3 has 2,000 LM324M ICs with date code B
Short-Form Procurement Specification
- IDIrection ~ Feed I
TAPE FORMAT
Trailer (Hub End)'
Carrier'
Leader (Start End)'
Empty Cavities,
min (Unsealed
Cover Tape)
Empty Cavities,
min (Sealed
Cover Tape)
Filled Cavities
(Sealed
Cover Tape)
Empty Cavities,
min (Sealed
Cover Tape)
Empty Cavities,
min (Unsealed
Cover Tape)
Small Outline IC
80-8 (Narrow)
2
2
2500
5
5
SO-14 (Narrow)
2
2
2500
5
5
SO-14 (Wide)
2
2
1000
5
5
SO-16 (Narrow)
2
2
2500
5
5
SO-16 (Wide)
2
2
1000
5
5
80-20 (Wide)
2
2
1000
5
5
80-24 (Wide)
2
2
1000
5
5
PCC-20
2
2
1000
5
5
PCC-28
2
2
750
5
5
PCC-44
2
2
500
5
5
Plastic Chip Carrier IC
'The following diagram Identifies these sections of the tape and Pin # 1 device orientation.
8-6
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Short-Form Procurement Specification
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(Continued)
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DEVICE ORIENTATION
DIRECTION
OFFEED
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ORIENTATION
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DEVICES
TUXX/0026-B
o Reel:
MATERIALS
• Cavity Tape: Conductive PVC (less than 105 Ohms/Sq)
(1) Solid 80 pt fibreboard (standard)
(2) Conductive fibreboard available
• Cover Tape: Polyester
(3) Conductive plastic (PVC) available
(1) Conductive cover available
TAPE DIMENSIONS (24 Millimeter Tape or Less)
_
Po 10 PITCH CUMULATIVE
TAPE TOLERANCE ±O.2mm
DEVICE ORIENTATION
\
PIN
1
SO·IC
PCC·IC
TL/XX/0026-9
8-7
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Short-Form Procurement Specification
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80-8
12±.30 8.0±.10
(Narrow)
5.5±.05 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 6.4±.10
5.2±.10
2.1±.10 1.55±.05 30
80-14
16±.30 8.0±.10
(Narrow)
7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 6.5±.10
9.0±.10
2.1±.10 1.55±.05 40
9.5±.10
3.0±.10 1.55±.05 40
80-14
(Wide)
16±.30 12.0±.10 7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 10.9±.10
80-16
16±.30 8.0±.10
(Narrow)
80-16
(Wide)
80-20
(Wide)
80-24
(Wide)
7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 6.5±.10
10.3±.10 2.1 ±.10 1.55±.05 40
16±.30 12.0±.10 7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 10.9±.10 10.76±.10 3.0±.10 1.55±.05 40
24±.30 12.0±.10 11.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 10.9±.10 13.3±.10 3.0±.10 2.05±.05 50
24±.30 12.0±.10 11.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 10.9±.10 15.85±.10 3.0±.10 2.05±.05 50
Plastic Chip Carrier IC
PCC-20
16±.30 12.0±.10 7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 9.3±.10
PCC-28
24±.30 16.0±.10 11.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 13.0±.10 13.0±.10 4.9±.10 2.05±.05 50
9.3±.10
4.9±.10 1.55±.05 40
Note 1: ~, Bo and Ko dimensions are measured 0.3 mm above the inside wall of the cavity bottom.
Note 2: Tape with components shall pass around a mandril radius R without damage.
Note 3: Cavity tape material shall be PVC ccnductive (less than 105 Ohms/Sq).
Note 4: Cover tape material shall be polyester (30-65 grams peel·back force).
Note 5: D1 Dimension is centered within cavity.
Note 6: All dimensions are in millimeters.
REEL DIMENSIONS
TMAX
-
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A
/
"
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((0) )
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STARTM· Surface Mount Tape and Reel
8-8
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TL/XX/OO26-10
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Short-Form Procurement Specifications (Continued)
CD
A (Max)
12mmTape
SO-8 (Narrow)
(13.00)
(330)
16mmTape
24 mm Tape
32mmTape
SO-14 (Narrow)
SO-14 (Wide)
SO-16 (Narrow)
SO-16 (Wide)
PCC-20
SO-20 (Wide)
SO-24 (Wide)
PCC-28
C
D(Min)
N(Min)
G
T(Max)
--
.059
.795
--
1.969
--50
0.4B8~:g6g
1.5
.512±.002
13±0.05
.724
-18.4
--
---
.795
-20.2
---
(13.00)
(330)
--
.059
.512±.002
1.5
13±0.05
(13.00)
.059
-1.5
.512±.002
.059
-1.5
.512±.002
(330)
(13.00)
PCC-44
B(Min)
(330)
13±0.05
13±0.05
20.2
.795
20.2
.795
-20.2
1.969
50
1.969
50
1.969
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12.4~~
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16.4 ~~
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24.4~~
1.276~:g6g
32.4~~
.882
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1.197
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1.512
--38.4
Inches
Units: Millimeters
Material: Paperboard (Non-Flaking)
LABEL
Wave Soldering of Surface
Mount Components
Human and Machine Readable Label is provided on reel. A
variable (C.P.I) density code 39 is available. NSC STD label
(7.6 C.P.I.)
ABSTRACT
In facing the upcoming surge of "surface mount technology", many manufacturers of printed circuit boards have taken steps to convert some portions of their boards to this
new process. However, as the availability of surface mount
components is still limited, may have taken to mixing the
lead-inserted standard dual-in-line packages (DIPs) with the
surface mounted devices (SMDs). Furthermore, to take advantage of using both sides of the board, surface-mounted
components are generally adhered to the bottom side of the
board while the top side is reserved for the conventional
lead-inserted packages. If processed through a wave solder
machine, the semiconductor components are now subjected to extra thermal stresses (now that the components are
totally immersed into the molten solder).
FIELD
Lot Number
Date Code
Revision Level
National Part No. I.D.
Qty.
EXAMPLE
LOT
(NUMBER
DATE
(CODE
REVISION
( NUMBER
ole: M8644
LOT: EP639363K027
R:
1IIIRlililll~II~I~~III~~III~lill!liI1Iilllill!ilillllm IIIIIII~IIIII~II!IIIIII~
163
QTY:
2500
A discussion of the effect of wave soldering on the reliability
II~I UI~ Ullil il l l l l !i ~1~1111~liilllllllll~i Illil!IIIW !i~llll~ II!IIIIII~II~II! 111~~~llil!i~~ I!
of plastic semiconductor packages follows. This is intended
to highlight the limitations which should be understood in
the use of wave soldering of surface mounted components.
NATIONAL SEMICONDUCTOR PART NUMBER
TL/XX/0026-11
Fields are separated by at least one blank space.
ROLE OF WAVE-SOLDERING IN
APPLICATION OF SMDs
Future Tape-and-Reel packs will also include a smaller-size
bar code label (high-density code 39) at the beginning of the
tape. (This tape label is not available on current production.)
The generally acceptable methods of soldering SMDs are
vapor phase reflow soldering and IR reflow soldering, both
requiring application of solder paste on PW boards prior to
placement of the components. However, sentiment still exists for retaining the use of the old wave-soldering machine.
National Semiconductor will also offer additional labels containing information per your specific specification.
8-9
i:
oC
:I
Wave Soldering of Surface Mount Components (Continued)
C) VaporliR rellowonly.
1. Components on the same side of PW Board.
Trim and form standard DIPs in "gull wing" configuration
Solder paste screened on PW Board
Pick and place SMDs and DIPs
The reasons being:
1) Most PC Board Assembly houses already possess wave
soldering equipment. SWitching to another technology
such as vapor phase soldering requires substantial investment in equipment and people.
2) Due to the limited number of devices that are surface
mount components, it is necessary to mix both lead inserted components and surface mount components on
the same board.
Bake
Vapor/lR reflow
Clean
2. Components on opposite sides of PW Board.
Solder paste screened on SMD-side of Printed
Wire Board
Adhesive dispensed at central location of each
component
Pick and place SMDs
Bake
Solder paste screened on all pads on DIP-side or
alternatively apply solder rings (performs) on
leads
Lead insert DI Ps
Vapor/IR reflow
Clean and lead trim
D) Wave Soldering Only
1. Components on opposite sides of PW Board.
Adhesive dispense on SMD side of PW Board
Pick and place SMDs
Cure adhesive
Lead insert top side with DIPs
Wave solder with SMDs down and into solder bath
Clean and lead trim
All of the above assembly procedures can be divided into
three categories for I.C. Reliability considerations:
1) Components are subjected to both a vapor phase/IR
heat cycle then followed by a wave-solder heat cycle or
vice versa.
2) Components are subjected to only a vapor phase/IR
heat cycle.
3) Components are subjected to wave-soldering only and
SMDs are subjected to heat by immersion into a solder
pot.
Of these three categories, the last is the most severe regarding heat treatment to a semiconductor device. However, note that semiconductor molded packages generally
possess a coating of solder on their leads as a final finish
for solderability and protection of base leadframe material.
Most semiconductor manufacturers solder-plate the component leads, while others perform hot solder dip. In the latter
case the packages may be subjected to total immersion into
a hot solder bath under controlled conditions (manual operation) or be partially immersed while in a 'pallet' where automatic wave or DIP soldering processes are used. It is, therefore, possible to subject SMDs to solder heat under certain
conditions and not cause catastrophic failures.
3) Some components such as relays and switches are
made of materials which would not be able to survive the
temperature exposure in a vapor phase or IR furnace.
PW BOARD ASSEMBLY PROCEDURES
There are two considerations in which through-hole ICs may
be combined with surface mount components on the PW
Board:
a) Whether to mount ICs on one or both sides of the board.
b) The sequence of soldering using Vapor Phase, IR or
Wave Soldering Singly or combination of two or more
methods.
The various processes that may be employed are:
A) Wave Solder before Vapor/IR reflow solder.
1. Components on the same side of PW Board.
Lead insert standard DIPS onto PW Board Wave
solder (conventional)
Wash and lead trim
Dispense solder paste on SMD pads
Pick and place SMDs onto PW Board
Bake
Vapor phase/IR rellow
Clean
2. Components on opposite side of PW Board.
Lead insert standard DIPs onto PW Board
Wave Solder (conventional)
Clean and lead trim
Invert PW Board
Dispense solder paste on SMD pads
Dispense drop of adhesive on SMD sites (optional
for smaller components)
Pick and place SMDs onto board
Bake/Cure
Invert board to rest on raised fixture
Vapor/lR reflow soldering
Clean
B) Vapor/lR reflow solder then Wave Solder.
1. Components on the same side of PW Board.
Solder paste screened on SMD side of Printed
Wire Board
Pick and place SMDs
Bake
Vapor/lR reflow
Lead insert on same side as SMDs
Wave solder
Clean and trim underside of PCB
8-10
en
c
Wave Soldering of Surface Mount Components (Continued)
THERMAL CHARACTERISTICS OF
MOLDED INTEGRATED CIRCUITS
Since Plastic DIPs and SMDs are encapsulated with a thermoset epoxy, the thermal characteristics of the material
generally correspond to a TMA (Thermo-Mechanical Analysis) graph. The critical parameters are (a) its Linear thermal
expansion characteristics and (b) its glass transition temperature after the epoxy has been fully cured. A typical TMA
graph is illustrated in Figure 1. Note that the epoxy changes
to a higher thermal expansion once it is subjected to temperatures exceeding its glass transition temperature. Metals
(as used on lead frames, for example) do not have this characteristic and generally will have a consistent Linear thermal
expansion over the same temperature range.
EFFECT ON PACKAGE PERFORMANCE BY
EPOXY-METAL SEPARATION
In wave soldering, it is necessary to use fluxes to assist the
solderability of the components and PW boards. Some facilities may even process the boards and components through
some form of acid cleaning prior to the soldering temperature. If separation occurs, the flux residues and acid residues (which may be present owing to inadequate cleaning)
will be forced into the package mainly by capillary action as
the residues move away from the solder heat source. Once
the package is cooled, these contaminants are now trapped
within the package and are available to diffuse with moisture
from the epoxy over time. It should be noted that electrical
tests performed immediately after soldering generally will
give no indication of this potential problem. In any case, the
end result will be corrosion of the chip metallization over
time and premature failure of the device in the field.
In any good reliable plastic package, the choice of lead
frame material should be such to match its thermal expansion properties to that of the encapsulating epoxy. In the
event that there is a mismatch between the two, stresses
can build up at the interface of the epoxy and metal. There
now exists a tendency for the epoxy to separate from the
metal lead frame in a manner similar to that observed on bimetallic thermal range.
VAPOR PHASEIIR REFLOW SOLDERING
In both vapor phase and IR reflow soldering, the risk of
separation between epoxy/metal can also be high. Operating temperatures are 21S·C (vapor phase) or 240·C (IR) and
duration may also be longer (30 sec-SO sec). On the same
theoretical basis, there should also be separation. However,
in both these methods, solder paste is applied to the pads
of the boards; no fluxes are used. Also, the devices are not
immersed into the hot solder. This reduces the possibility of
solder forcing itself into the epoxy-lead frame interface. Furthermore, in the vapor phase system, the soldering environment is "oxygen-free" and considered "contaminant free".
Being so, it could be visualized that as far as reliability with
respect to corrosion, both of these methods are advantageous over wave soldering.
In most cases when the packages are kept at temperatures
below their glass transition, there is a small possibility of
separation at the expoxy-metal interface. Howerver, if the
package is subjected to temprature above its glass-transition temperature, the epoxy will begin to expand much
faster than the metal and the probability of separation is
greatly increased.
CONVENTIONAL WAVE-80LDERING
Most wave-soldering operations occur at temperatures between 240-2S0·C. Conventional epoxies for encapsulation
have glass-transition temperature between 140-170·C. An
I.C. directly exposed to these temperatures risks its long
term functionality due to epoxy/metal separation.
BIAS MOISTURE TEST
A bias moisture test was designed to determine the effect
on package performance. In this test, the packages are
pressured in a stream chamber to accelerate penetration of
moisture into the package. An electrical bias is applied on
the device. Should there be any contaminants trapped within the package, the moisture will quickly form an electrolyte
and cause the electrodes (which are the lead fingers), the
gold wire and the aluminum bond-pads of the silicon device
to corrode. The aluminum bond-pads, being the weakest
link of the system, will generally be the first to fail.
This proprietary accelerated bias/moisture pressure-test is
significant in relation to the life test condition at 8S·C and
Fortunately, there are factors that can reduce that element
of risk:
1) The PW board has a certain amount of heat-sink effect
and tends to shield the components from the temperature of the solder (if they were placed on the top side of
the board). In actual measurements, DIPs achieve a temperature between 120-1S0·C in a S-second pass over
the solder. This accounts for the fact that DIPs mounted
in the conventional manner are reliable.
2) In conventional soldering, only the tip of each lead in a
DIP would experience the solder temperature because
the epoxy and die are standing above the PW board and
out of the solder bath.
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100 110 120 130 140 150 160 ,170 180
19
FIGURE 1. Thermal Expansion and Glass Transition Temperature
8-11
TUXX/0026-12
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Wave Soldering of Surface Mount Components (Continued)
85% relative humidity. Once cycle of approximately 100
hours has been shown to be equivalent to 2000 hours in the
85/85 condition. Should the packages start to fail within the
first cycle in the test, it is anticipated that the boards with
these components in the harsh operating environment
(85'C/85% RH) will experience corrosion and eventual
electrical failures within its first 2000 hours of operation.
Whether this is significant to a circuit board manufacturer
will obviously be dependent on the products being manufactured and the workmanship or reliability standards. Generally in systems with a long warranty and containing many
components, it is advisable both on a reputation and cost
basis to have the most reliable parts available.
Since the package is of very small mass and experiences a
rather sharp thermal shock followed by stresses created by
the mismatch in expansion, the results show the package
being susceptible to failures after being immersed in excess
of 6 seconds in a solder pot. In the second case where the
packages were mounted, the effect of severe temperature
excursion was reduced. In the second case where the packages were mounted, the effect of severe temperature excursion was reduced. In any case, because of the repeated
treatment, the package had failures when subjected in excess of 6 seconds immersion in hot solder. The safety margin is therefore recommended as maximum 4 seconds immersion. If packages were immersed longer than 4 seconds, there is a probable chance of finding some long term
reliability failures even though the immediate electrical test
data could be acceptable.
Finally, Table VI examines the bias moisture test performed
on surface mount (SOIC) components manufactured by various semiconductor houses. End point was an electrical test
after an equivalent of 6000 hours in a 85/85 test. Failures
were analyzed and corrosion was checked for in each case
to detect flaws in package integrity.
TEST RESULTS
The comparison of vapor phase and wave-soldering upon
the reliability of molded Small-Outline packages was performed using the bias moisture test (see Table IV). It is
clearly seen that vapor phase reflow soldering gave more
consistent results. Wave-soldering results were based on
manual operation giving variations in soldering parameters
such as temperature and duration.
TABLE IV. Vapor Phase vs. Wave Solder
TABLE VI. U.S. Manufacturers Integrated Circuits
Reliability In Various Solder Environments
(# Failure/Total Tested)
1. Vapor phase (60 sec. exposure @215'C)
= 9 failures/1723 samples
= 0.5% (average over 32 sample lots)
2. Wave solder (2 sec total immersion @260'C)
= 16 failures/1201 samples
= 1.3% (average over 27 sample lots)
Package: SO-14lead
Test:
Bias moisture test 85% R.H.,
85'C for 2000 hours
Device:
LM324M
In Table V we examine the tolerance of the Small-Outlined
(SOl C) package to varying immersion time in a hot solder
pot. SO-14 lead molded packages were subjected to the
bias moisture test after being treated to the various soldering conditions and repeated four (4) times. End pOint was an
electrical test after an equivalent of 4000 hours 85/85 test.
Results were compared for packages by itself against packages which were surface-mounted onto a FR-4 printed wire
board.
Unmounted
Mounted
0/114
·0/84
Solder Dip
2 sec @260'C
2/144 (1.4%)
0/85
Solder Dip
4 sec @260'C
-
0/83
Solder Dip
6 sec @260'C
13/248 (5.2%)
1/76(1.3%)
Solder Dip
10 sec @ 260'C
14/127 (11.0%)
3/79(3.8%)
Package:
Device:
Vapor
Phase
30 sec
Wave
Solder
2 sec
Wave
Solder
4 sec
Wave
Solder
6 sec
Wave
Solder
10 sec
ManufA
ManufB
ManufC
8/30'
2/30'
0/30
1/30'
8/30'
0/29
0.30
2/30'
0/29
12/30'
22/30'
0/30
16/30'
20/30'
0/30
ManufD
ManufE
ManufF
ManufG
1/30'
1/30"
0/30
0/30
0/30
0/30
12/30'
0/30
0/30
0/30
14/30'
0/30
0/30
0/30
2130'
0/30
0/30
0/30
0/30
0/30
·Corrosion-failures
··No Visual Defecis-Non-corrosion failures
Test Accelerated Bias Moisture Test; 85% R.H.l8S'C. 6000 equivalent
hours.
SUMMARY
Based on the results presented, it is noted that surfacemounted components are as reliable as standard molded
DIP packages. Whereas DIPs were never processed by being totally immersed in a hot solder wave during printed circuit board soldering, surface mounted components such as
SOICs (Small Outline) are expected to survive a total immersion in the hot solder in order to capitalize on maximum
population on boards. Being constructed from a thermoset
plastic of relatively low Tg compared to the soldering temperature, the ability of the package to survive is dependent
on the time of immersion and also the cleanliness of material. The results indicate that one should limit the immersion
time of package in the solder wave to a maximum of 4 seconds in order to truly duplicate the reliability of a DIP. As the
package size is reduced, as in a SO-8 lead, the requirement
becomes even more critical. This is shown by the various
manufacturers' performance. Results indicate there is room
for improvement since not all survived the hot solder immersion without compromise to lower reliability.
TABLE V. Summary of Wave Solder Results
(85% R.H./85'C Bias Moisture Test, 2000 hours)
(# Failures/Total Tested)
ControllVapor Phase
15 sec @215'C
Package
SO-8
SO-14 lead
LM324M
8-12
Small Outline (SO) Package Surface Mounting MethodsParameters and Their Effect on Product Reliability
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The SO (small outline) package has been developed to
meet customer demand for ever-increasing miniaturization
and component density.
In order to achieve reliability performance comparable to
DIPs-SO packages are deSigned and built with materials
and processes that effectively compensate for their small
size.
All SO packages tested on 85%RA, 85'C were assembled
on PC conversion boards using vapor-phase reflow soldering. With this approach we are able to measure the effect of
surface mounting methods on reliability of the process. As
illustrated in Figure A no significant difference was detected
between the long term reliability performance of surface
mounted S.O. packages and the DIP control product for up
to 6000 hours of accelerated 85%/85'C testing.
COMPONENT SIZE COMPARISON
S.O. Package
_I 1-
SURFACE-MOUNT PROCESS FLOW
The standard process flowcharts for basic surface-mount
operation and mixed-lead insertion/surface-mount operations, are illustrated on the following pages.
Usual variations encountered by users of SO packages are:
TYPICALLY 0.050" LEADSPACING
TL/XX/0026-13
Standard DIP Package
• Single-sided boards, surface-mounted components only.
• Single-sided boards, mixed-lead inserted and surfacemounted components.
• Double-sided boards, surface-mounted components only.
• Double-sided boards, mixed-lead inserted and surfacemounted components.
1_
In consideration of these variations, it became necessary for
users to utilize techniques involving wave soldering and adhesive applications, along with the commonly-used vaporphase solder reflow soldering technique.
PRODUCTION FLOW
TYPICALLY 0.100" LEADS PACING
TL/XX/0026-14
Basic Surface-Mount Production Flow
Because of its small size, reliability of the product assembled in SO packages needs to be carefully evaluated.
SO packages at National were internally qualified for production under the condition that they be of comparable reliability performance to a standard dual in line package under
all accelerated environmental tests. Figure A is a summary
of accelarated bias moisture test performance on 30V bipolar and 15V CMOS product assembled in SO and DIP (control) packages.
V+=15VCMOS
30V BIPOLAR
85%RH/850C
TEST CONDITION
DIP
o
2000
4000
6000
TEST TIME (HRS)
TL/XX/0026-15
FIGURE A
8-13
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Mixed Surface-Mount and Axial-Leaded Insertion
Components Production Flow
Thermal stress of the packages during surface-mounting
processing is more severe than during standard DIP PC
board mounting processes. Figure B illustrates package
temperature versus wave soldering dwell time for surface
mounted packages (components are immersed into the
molten solder) and the standard DIP wave soldering process. (Only leads of the package are immersed into the molten solder).
~
~
SOLOER TEMPERATURE 260"C
o
1 2 3 4 5 6 7 8 9 10 SEC.
DWELL TIME
TL/XX/0026-18
FIGUREB
For an ideal package, the thermal expansion rate of the
encapsulant should match that of the leadframe material in
order for the package to maintain mechanical integrity during the soldering process. Unfortunately, a perfect matchup
of thermal expansion rates with most presently used packaging materials is scarce. The problem lies primarily with the
epoxy compound.
Normally, thermal expansion rates for epoxy encapsulant
and metal lead frame materials are linear and remain fairly
close at temperatures approaching 160'C, Figure C. At lower temperatures the difference in expansion rate of the two
materials is not great enough to cause interface separation.
However, when the package reaches the glass-transition
temperature (Tg) of epoxy (typically 160-165'C), the thermal expansion rate of the encapsulant increases sharply,
and the material undergoes a transition into a plastiC state.
The epoxy begins to expand at a rate three times or more
greater than the metal leadframe, causing a separation at
the interface.
TL/XX/0026·17
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TLlXX/0026-19
FIGUREC
8-14
When this happens during a conventional wave soldering
process using flux and acid cleaners, process residues and
even solder can enter the cavity created by the separation
and become entrapped when the material cools. These
contaminants can eventually diffuse into the interior of the
package, especially in the presence of moisture. The result
is die contamination, excessive leakage, and even catastrophic failure. Unfortunately, electrical tests performed immediately following soldering may not detect potential flaws.
Most soldering processes involve temperatures ranging up
to 260'C, which far exceeds the glass-transition temperature of epoxy. Clearly, circuit boards containing SMD packages require tighter process controls than those used for
boards populated solely by DIPs.
The basic component-placement systems available are
classified as:
(a) In-line placement
-
Fixed placement stations
Boards indexed under head and respective components placed
(b) Sequential placement
-
Either a X-V moving table system or a 8, X-V moving
pickup system used
-Individual components picked and placed onto boards
(c) Simultaneous placement
- Multiple pickup heads
- Whole array of components placed onto the PCB at
the same time
(d) Sequential/simultaneous placement
Figure D is a summary of accelerated bias moisture test
performance on the 30V bipolar process.
Group 1 - Standard DIP package
Group 2 - SO packages vapor-phase reflow soldered on
PC boards
Group 3-6 SO packages wave soldered on PC boards
Group 3 - dwell time 2 seconds
4 - dwell time 4 seconds
5 - dwell time 6 seconds
6 - dwell time 10 seconds
- X-V moving table, multiple pickup heads system
- Components placed on PCB by successive or simultaneous actuation of pickup heads
The SO package is treated almost the same as surfacemount, passive components requiring correct orientation in
placement on the board.
Pick and Place Action
#6(10 SEC)
...'"
!;1
#5 (6 SEC)
'"3
~
#4(4 SEC)
,.11
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J]
o
2000
4000
6000
TEST TIME (HRS)
TL/XX/0026-20
FIGURED
It is clear based on the data presented that SO packages
soldered onto PC boards with the vapor phase reflow process have the best long term bias moisture performance
and this is comparable to the performance of standard DIP
packages. The key advantage of reflow soldering methods
is the clean environment that minimized the potential for
contamination of surface mounted packages, and is preferred for the surface-mount process.
TL/XX/0026-21
BAKE
This is recommended, despite claims made by some solder
paste suppliers that this step be omitted.
The functions of this step are:
When wave soldering is used to surface mount components
on the board, the dwell time of the component under molten
solder should be no more than 4 seconds, preferrably under
2 seconds in order to prevent damage to the component.
Non-Halide, or (organic acid) fluxes are highly recommended.
• Holds down the solder globules during subsequent reflow
soldering process and prevents expulsion of small solder
balls.
• Acts as an adhesive to hold the components in place during handling between placement to reflow soldering.
• Holds components in position when a double-sided surface-mounted board is held upside down going into a vapor-phase reflow soldering operation.
PICK AND PLACE
The choice of automatic (all generally programmable) pickand-place machines to handle surface mounting has grown
considerably, and their selection is based on individual
needs and degree of sophistication.
• Removes solvents which might otherwise contaminate
other equipment.
• Initiates activator cleaning of surfaces to be soldered.
• Prevents moisture absorption.
8-15
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The process is moreover very simple. The usual schedule is
about 20 minutes in a 65'C-95'C (dependent on solvent
system of solder paste) oven with adequate venting. Longer
bake time is not recommended due to the following reasons:
In-Line Conveyorlzed Vapor-Phase Soldering
J
• The flux will degrade and affect the characteristics of the
paste.
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• Solder globules will begin to oxidize and cause solderability problems.
• The paste will creep and after reflow, may leave behind
residues between traces which are difficult to remove and
vulnerable to electro-migration problems.
COILS
COILS
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LIQUID
REFLOW SOLDERING
There are various methods for reflowing the solder paste,
namely:
IMMERSION HEATER
TLlXX/0026-22
The question of thermal shock is asked frequently because
of the relatively sharp increase in component temperature
from room temperature to 215'C. SO packages mounted on
representative boards have been tested and have shown
little effect on the integrity of the packages. Various packages, such as cerdips, metal cans and TO-5 cans with glass
seals, have also been tested.
• Hot air reflow
• Infrared heating (furnaces)
• Convectional oven heating
• Vapor-phase reflow soldering
• Laser soldering
For SO applications, hot air reflow/infrared furnace may be
used for low-volume production or prototype work, but vapor-phase soldering reflow is more efficient for consistency
and speed. Oven heating is not recommended because of
"hot spots" in the oven and uneven melting may result. laser soldering is more for specialized applications and requires a great amount of investment.
Vapor-Phase Furnace
HOT GAS REFLOW/INFRARED HEATING
A hand-held or table-mount air blower (with appropriate orifice mask) can be used.
The boards are preheated to about 100'C and then subjected to an air jet at about 260'C. This is a slow process and
results may be inconsistent due to various heat-sink properties of passive components.
Use of an infrared furnace is the next step to automating the
concept, except that the heating is promoted by use of IR
lamps or panels. The main objection to this method is that
certain materials may heat up at different rates under IR
radiation and may result in damage to these components
(usually sockets and connectors). This could be minimized
by using far-infrared (non-focused) system.
TLlXX/0026-23
VAPOR-PHASE REFLOW SOLDERING
Currently the most popular and consistent method, vaporphase soldering utilizes a fluoroinert fluid with excellent
heat-transfer properties to heat up components until the solder paste reflows. The maximum temperature is limited by
the vapor temperature of the fluid.
Batch-Fed Production Vapor-Phase Soldering Unit
SECONDARY
COILS
The commonly used fluids (supplied by 3M Corp) are:
PRIMARY COILS
• FC-70, 215'C vapor (most applications) or FX-38
• FC-71 , 253'C vapor (low-lead or tin-plate)
HTC, Concord, CA, manufactures equipment that utilizes
this technique, with two options:
• Batch systems, where boards are lowered in a basket and
subjected to the vapor from a tank of boiling fluid.
• In-line conveyorized systems, where boards are placed
onto a continuous belt which transports them into a concealed tank where they are subjected to an environment
of hot vapor.
Dwell time in the vapor is generally on the order of 15-30
seconds (depending on the mass of the boards and the
loading density of boards on the belt).
IMMERSION HEATER
TLlXX/0026-24
8-16
,--------------------------------------------------------------------------, m
Solder Joints on a SO-14 Package on PCB
Solder Joints on a SO-14 Package on PCB
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TL/XX/0026-25
TL/XX/0026-26
The SO package is molded out of clean, thermoset plastic
compound and has no particular compatibility problems with
most printed circuit board substrates.
The typical lithographic "footprints" for SO packages are
illustrated below. Note that the 0.050" lead center-center
spacing is not easily managed by commercially-available air
pressure, hand-held dispensers.
PRINTED CIRCUIT BOARD
Using a stainless-steel, wire-mesh screen stencilled with an
emulsion image of the substrate pads is by far the most
common and well-tried method. The paste is forced through
the screen by a V-shaped plastic squeegee in a sweeping
manner onto the board placed beneath the screen.
The package can be reliably mounted onto substrates such
as:
• G10 or FR4 glass/resin
• FR5 glass/resin systems for high-temperature
applications
The setup for SO packages has no special requirement
from that required by other surface-mounted, passive components. Recommended working specifications are:
• Polymide boards, also high-temperature
applications
• Ceramic substrates
• Use stainless-steel, wire-mesh screens, #80 or #120,
wire diameter 2.6 mils. Rule of thumb: mesh opening
should be approximately 2.5-5 times larger than the average particle size of paste material.
General requirements for printed circuit boards are:
• Mounting pads should be solder-plated whenever
applicable.
• Use squeegee of Durometer 70 .
• Solder masks are commonly used to prevent solder bridging of fine lines during soldering.
• Experimentation with squeegee travel speed is recommended, if available on machine used.
The mask also protects circuits from processing chemical
contamination and corrosion.
• Use solder paste of mesh 200-325.
If coated over pre-tinned traces, residues may accumulate
at the mask/trace interface during subsequent reflow,
leading to possible reliability failures.
• Emulsion thickness of 0.005" usually used to achieve a
solder paste thickness (wet) of about 0.008" typical.
Recommended application of solder resist on bare, clean
traces prior to coating exposed areas with solder.
• Snap-off height of screen should not exceed
damage to screens and minimize distortion.
• Mesh pattern should be 90 degrees, square grid.
General requirements for solder mask:
-
Good pattern resolution.
-
Complete coverage of circuit lines and resistance to
flaking during soldering.
-
Adhesion should be excellent on substrate material to
keep off moisture and chemicals.
-
Compatible with soldering and cleaning requirements.
'Is" , to avoid
SOLDER PASTE
Selection of solder paste tends to be confusing, due to numerous formulations available from various manufacturers.
In general, the following guidelines are sufficient to qualify a
particular paste for production:
• Particle sizes (see photographs below). Mesh 325 (approximately 45 microns) should be used for general purposes, while larger (solder globules) particles are preferred for leadless components (LCC). The larger particles
can easily be used for SO packages.
SOLDER PASTE SCREEN PRINTING
With the initial choice of printed circuit lithographic design
and substrate material, the first step in surface mounting is
the application of solder paste.
8-17
~ ~----------------------------------------------------------------------------------------~
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• Uniform particle distribution. Solder globules should be
spherical in shape with uniform diameters and minimum
amount of elongation (visual under 100/200 x magnification). Uneven distribution causes uneven melting and subsequent expulsion of smaller solder balls away from their
proper sites.
• Composition, generally 60/40 or 63/37 Sn/Pb. Use 62/36
Sn/Pb with 2% Ag in the presence of Au on the soldering
area. This formulation reduces problems of metal leaching
from soldering pads.
• RMA flux system usually used.
• Use paste with aproximately 88-90% solids.
RECOMMENDED SOLDER PADS FOR SO PACKAGES
so-a, SO-14, SO-16
SO-16L, SO-20
0.045" :to.005"
r····~
L-I••••
J:~
1- -I
0.245"
0.160"
0.030" :to.005"
!-0.050"YYP
TL/XX/0026-27
0.030"
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1-
:to.005"~
-.1 I-:ryyp
TL/XX/0026-28
TLlXX/0026-29
Comparison of Particle Size/Shape of Various Solder Pastes
200 x Alpha (62/36/2)
200 x Kester (63/37)
TLlXX/0026-30
TL/XX/0026-31
8-18
,--------------------------------------------------------------------------,
Comparison of Particle Size/Shape of Various Solder Pastes (Continued)
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Solder Paste Screen on Pads
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TL/XX/0026-33
TL/XX/0026-32
200 ESL (63/37)
TUXX/0026-34
8-19
Hot-Air Rework Machine
CLEANING
The most critical process in surface mounting SO packages
is in the cleaning cycle. The package is mounted very close
to the surface of the substrate and has a tendency to collect
residue left behind after reflow soldering.
Important considerations in cleaning are:
• Time between soldering and cleaning to be as short as
possible. Residue should not be allowed to solidify on the
substrate for long periods of time, making it difficult to
dislodge.
• A low surface tension solvent (high penetration) should be
employed. Solvents commercially available are:
Freon TMS (general purpose)
Freon TE35/TP35 (cold-dip cleaning)
Freon TES (general purpose)
TL/XX/OO26-36
lead tips or, if necessary, solder paste can be dispensed
onto the pads using a varimeter. After being placed into
position, the solder is reflowed by a hot-air jet or even a
standard soldering iron.
It should also be noted that these solvents generally will
leave the substrate surface hydrophobic (moisture repellent), which is desirable.
Prelete or 1,1,1-Trichloroethane
Kester 5120/5121
WAVE SOLDERING
In a case where lead insertions are made on the same
board as surface-mounted components, there Is a need to
include a wave-soldering operation in the process flow.
Two options are used:
• A defluxer system which allows the workpiece to be subjected to a solvent vapor, followed by a rinse in pure solvent and a high-pressure spray lance are the basic requirments for low-volume production.
• Surface mounted components are placed and vapor
phase reflowed before auto-insertion of remaining components. The board is carried over a standard wave-solder
system and the underside of the board (only lead-inserted
leads) soldered.
• For volume production, a conveyorized, multiple hot solvent spray/jet system is recommended.
• Rosin, being a natural occurring material, is not readily
soluble in solvents, and has long been a stumbling block
to the cleaning process. In recent developments, synthetic flux (SA flux), which is readily soluble in Freon TMS
solvent, has been developed. This should be explored
where permissible.
The dangers of an inadequate cleaning cycle are:
• Surface-mounted components are placed in position, but
no solder paste is used. Instead, a drop of adhesive about
5 mils maximum in height with diameter not exceeding
25% width of the package is used to hold down the package. The adhesive is cured and then proceeded to autoinsertion on the reverse side of the board (surface-mounted side facing down). The assembly is then passed over a
"dual wave" soldering system. Note that the surfacemounted components are immersed into the molten solder.
• Ion contamination, where ionic residue left on boards
would cause corrosion to metallic components, affecting
the performance of the board.
• Electro-migration, where ionic residue and moisture present on electrically-biased boards would cause dentritic
growth between close spacing traces on the substrate,
resulting in failures (shorts).
Lead trimming will pose a problem after soldering in the
latter case, unless the leads of the insertion components
are pre-trimmed or the board specially designed to localize
certain areas for easy access to the trim blade.
The controls required for wave soldering are:
REWORK
Should there be a need to replace a component or re-align
a previously disturbed component, a hot air system with appropriate orifice masking to protect surrounding components may be used.
When rework is necessary in the field, specially-designed
tweezers that thermally heat the component may be used to
remove it from its site. The replacement can be fluxed at the
• Solder temperature to be 240-260·C. The dwell time of
components under molten solder to be short (preferably
kept under 2 seconds), to prevent damage to most components and semiconductor devices.
• RMA (Rosin Mildly Activated) flux or more aggressive OA
(Organic Acid) flux are applied by either dipping or foam
fluxing on boards prior to preheat and soldering. Cleaning
procedures are also more difficult (aqueous, when OA flux
is used), as the entire board has been treated by flux (unlike solder paste, which is more or less localized). Nonhalide OA fluxes are highly recommended.
Hot-Air Solder Rework Station
MASeK
RETRACT POSITION
,
// 0
• Preheating of boards is essential to reduce thermal shock
on components. Board should reach a temperature of
about 100"C just before entering the solder wave.
---~------ / /
.-'-
• Due to the closer lead spacings (0.050' vs 0.100' for
dual-in-line packages), bridging of traces by solder could
occur. The reduced clearance between packages also
causes "shadowing" of some areas, resulting in poor solder coverage. This is minimized by dual-wave solder systems.
HEAT SHIELD
BOARD ON X-Y TABLE
HOT AIRTLlXX/OO26-35
8-20
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ADHESIVE
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(b) Opposite Sides
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PREHEAT
SOLDER FLOW
TL/XX/0026-37
A typical dual-wave system is illustrated below, showing the
various stages employed. The first wave typically is in turbulence and given a transverse motion (across the motion of
the board). This covers areas where "shadowing" occurs. A
second wave (usually a broad wave) then proceeds to perform the standard soldering. The departing edge from the
solder is such to reduce "icicles," and is still further reduced
by an air knife placed close to the final soldering step. This
air knife will blow off excess solder (still in the fluid stage)
which would otherwise cause shorts (bridging) and solder
bumps.
Dual Wave
AQUEOUS CLEANING
• For volume production, a conveyorized system is oiten
used with a heated recirculating spray wash (water temperature 130'C), a final spray rinse (water temperature
45-55'C), and a hot (120'C) air/air-knife drying section.
• For low-volume production, the above cleaning can be
done manually, using several water rinses/tanks. Fastdrying solvents, like alcohols that are miscible with water,
are sometimes used to help the drying process.
• Neutralizing agents which will react with the corrosive materials in the flux and produce material readily soluble in
water may be used; the choice depends on the type of flux
used.
.......
~
TL/XX/0026-38
CONFORMAL COATING
Conformal coating is recommended for high-reliability PCBs
to provide insulation resistance, as well as protection
against contamination and degradation by moisture.
Requirements:
• Final rinse water should be free from chemicals which are
introduced to maintain the biological purity of the water.
These materials, mostly chlorides, are detrimental to the
assemblies cleaned because they introduce a fresh
amount of ionizable material.
• Complete coating over components and solder joints.
• Thixotropic material which will not flow under the packages or fill voids, otherwise will introduce stress on solder
joints on expansion.
• Compatibility and possess excellent adhesion with PCB
material/components.
• Silicones are recommended where permissible in
application.
8-21
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SMD Lab Support
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FUNCTIONS
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Technlques-Develop techniques for handling different
materials and processes in surface mounting.
Demonstration-Introduce first-time users to surfacemounting processes.
Equipment-In conjunction with equipment manufacturers.
develop customized equipments to handle high density.
new technology packages developed by National.
Service-Investigate problems experienced by users on
surface mounting.
In-House Expertise-Availability of in-house expertise on
semiconductor research/development to assist users on
packaging queries.
Reliability Build&-Assemble surface-mounted units for reliability data acquisition.
8-22
Section 9
Appendices/
Physical Dimensions
Section 9 Contents
Appendix A General Product Marking and Code Explanation .............................
Appendix B Application Note Referenced by Part Number ......................•........
Appendix C Summary of Commercial Reliability Programs ...............................
Appendix D Military Aerospace Programs from National Semiconductor ...................
Appendix E Understanding Integrated Circuit Package Power Capabilities. . . . . . . . . . . . . . . . . .
Appendix F How to Get the Right Information from a Datasheet. . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix G Obsolete Product Replacement Guide. . . . . . . . .. . . .. . . . . . . . . . . . . . . . . . . . . . . . .
Appendix H Products Not Recommended for New Design ...............................
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors
9-2
9-3
9-4
9-10
9-11
9-18
9-23
9-27
9-28
9-29
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Appendix A
General Product Marking & Code Explanation
LF
II
356
N
Package Type*
/A+
L
D
E
F
PACKAGE TYPE (SEE BELOW)
DEVICE NUMBER (GENERIC TYPE) AND
SUFFIX LETTER (OPTIONAL)
A: INPROVED ELECTRICAL SPECIFICATION
C: COMMERCIAL TEMPERATURE RANGE
(2ND SOURCE PRODUCTS)
G
H
H-05
H-46
J
DEVICE FAMILY (SEE BELOW)
Data Conversion
Active Filter
Analog Switch (Hybrid)
Analog Switch (Monolithic)
DAC
DM
Data Conversion
Digital (Monolithic)
HS
LF
Hybrid
Linear (Bifet)
Linear (Hybrid)
LH
LM
LMC
LP
MF
SL
LMF
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4 Lead M/C (TO-5) } Shipped with
4 Lead M/C (TO-46)
Thermal Shield
Lo-Temp Ceramic DIP (Sometimes referred to as
!!.
available in -B pkg).
P
Q
T
V
W
WM
3 Lead TO-202 PWR Pkg
Cerdip with UV Window
3,5,11,15 & 23 Lead TO-220 PWR Pkg (Epoxy B)
Multi-lead Plastic Chip Carrier (PCC)
Lo-Temp Ceramic Flat Pak
Wide Body Small Outline Package
DATE CODE
NON-MILITARY
2ND DIGIT - CALENDAR YEAR
3RD & 4TH DIGITS - CALENDAR WORK WEEK
MILITARY - 883B & 1.43851 0
lST&2ND DIGITS-CALENDAR YEAR
3RD & 4TH DIGITS - CALENDAR WORK WEEK
(EXAMPLE:8301 =lST WEEK OF 1983)
MILITARY ONLY
ESD
(ELECTROSTATIC DISCHARGE)
SENSmVITY INDICATOR
MILITARY ONLY
INDICATE PLANT
OR MANUFACTURE
PART NUMBER
TL/XX/0027 -2
9-3
CD
product is also available in -B pkg).
TO-3 M/C in Steel, except LM309K
which is shipped in Aluminum
TO-3 M/C (Aluminum)
KSteel TO-3 M/C (Steel)
Small Outline Package
M
Molded DIP (EPOXY B)
N
N-01
Molded DIP (Epoxy B) with Staggered Leads
N-B
B Lead Molded DIP (Epoxy B) ("Mini-DIP")
14 Lead Molded DIP (Epoxy B)
N-14
(-14 used only when product is also
Special Linear
Linear Monolithic Filter
c..
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KC
Linear (Monolithic)
Linear CMOS
Linear (Low Power)
Linear (Monolithic Filter)
RO
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Integrated Circuits (IC's)
AF
AH
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J-14
J-B
ADC
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B Lead Ceramic DIP ("Mini DIP")
14 Lead Ceramic DIP (-14 used only when
TL/XX/0027-1
Device Family
CD
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Glass/Metal DIP
Ceramic Leadless Chip Carrier (LCC)
Glass/Metal Flat Pak
12 Lead TO-B M/C
Multi-Lead M/C
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IC's Only
RELIABILITY PROGRAM (OPTIONAL)
(REFER TO PROGRAM)
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Appendix B
APPLICATION NOTE REFERENCED BY PART NUMBER
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National Semiconductor Linear Application notes are normally written to explain
the operation and use of a particular device or family of IC's, or to present alterna·
tive technical solutions. The following PART NUMBER index references the pub·
lished application notes that would offer application assistance for those specific
IC's.
The 1986 Linear Applications Handbook is a complete text for all current Applica·
tion Notes for both Monolithic and Hybrid products. Specific Application Notes are
available upon request through National Semiconductor Sales Offices.
DEVICE NUMBER
APPLICATION NOTE
ADCXXXX ............................................................................. AN·156
ADC80 ...............................................................................AN·360
ADC0801 ................................ AN·233, AN·271, AN·274, AN·280, AN·281, AN·294, LB·53
ADC0802 ............................................... AN·233, AN·274, AN·280, AN·281, LB·53
ADC0803 ............................................... AN·233, AN-274, AN·280, AN·281, LB·53
ADC0804 ........................................ AN·233, AN·274, AN·276, AN·280, AN·281, LB·53
ADC0805 ............................................... AN·233, AN·274, AN·280, AN·281, LB·53
ADC0808 .............................................................. AN·247, AN·280, AN·281
ADC0809 .....................................................................AN·247, AN·280
ADC0816 ...................................................... AN·193, AN·247, AN·258, AN·280
ADC0817 .............................................................. AN·247, AN·258, AN·280
ADC0820 .............................................................................AN·237
ADC0831 ..................................................................... AN·280, AN·281
ADC0832 ..................................................................... AN·280, AN·281
ADC0833 .....................................................................AN·280, AN·281
ADC0834 .....................................................................AN·280, AN·281
ADC0838 .....................................................................AN·280, AN·281
ADC1001 .............................................................. AN·276, AN·280, AN·281
ADC1005 ............................................................................. AN·280
ADC1210 ............................................................................. AN·245
ADC3501 ..................................................................... AN·200, AN·202
ADC3511 .............................................................................AN·200
ADC3701 ............................................................................. AN·200
ADC3711 ............................................................................. AN·200
AH0014 ................................................................................ AN·38
AH0019 ................................................................................ AN·38
CD4016 ................................................................................AB·10
DACXXXX .............................................................................AN·156
DAC0830 ............................................................................. AN·284
DAC0831 .....................................................................AN·271, AN·284
DAC0832 ..................................................................... AN·271 , AN·284
DAC1000 ...................................................... AN·271, AN·275, AN·277, AN·284
DAC1001 ...................................................... AN·271, AN·275, AN·277, AN·284
DAC1002 ...................................................... AN·271, AN·275, AN·277, AN·284
DAC1006 ...................................................... AN·271, AN·275, AN·277, AN·284
DAC1007 ...................................................... AN·271, AN·275, AN·277, AN·284
9·4
»
APPLICATION NOTE
"C
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DAC1008 ...................................................... AN-271, AN-275, AN-277, AN-284
DAC1020 .............................................. AN-263, AN-269, AN-293, AN-294, AN-299
DAC1021 ............................................................................. AN-269
DAC1022 ............................................................................. AN-269
DAC1208 ..................................................................... AN-271, AN-284
DAC1209 ..................................................................... AN-271, AN-284
DAC1210 ..................................................................... AN-271, AN-284
DAC1218 ............................................................................. AN-293
DAC1220 ..................................................................... AN-253, AN-269
DAC1221 ............................................................................. AN-269
DAC1222 ............................................................................. AN-269
DAC1230 ............................................................................. AN-284
DAC1231 ..................................................................... AN-271, AN-284
DAC1232 ..................................................................... AN-271 , AN-284
DAC1280 ..................................................................... AN-261, AN-263
DH0034 ............................................................................... AN-253
DH0035 ................................................................................ AN-49
DS8606 ....................................................................... AN-381, AN-382
DS8608 ............................................................................... AN-382
DT1058 ............................................................................... AN-287
DT1060 ............................................................................... AN-287
DTSW250E2 .......................................................................... AN-287
DTSW250GI ........................................................................... AN-287
INS8070 .............................................................................. AN-260
LF111 .................................................................................. LB-39
LF155 ........................................................................ AN-263, AN-447
LF198 ........................................................................ AN-245, AN-294
LF311 ................................................................................ AN-301
LF347 ......................... AN-256, AN-262, AN-263, AN-265, AN-266, AN-301, AN-344, AN-447
LF351 ...................... AN-242, AN-263, AN-266, AN-271, AN-275, AN-293, AN-447, Appendix C
LF351A ............................................................................... AN-240
LF351 B ........................................................................... Appendix D
LF353 ........ AN-256, AN-258, AN-263, AN-264, AN-271, AN-285, AN-293, AN-447, LB-44, Appendix D
LF356 ................................. AN-253, AN-258, AN-260, AN-263, AN-266, AN-271, AN-272,
AN-275, AN-293, AN-294, AN-295, AN-301, AN-447
LF357 .................................................................. AN-263, AN-447, LB-42
LF398 ........................................... AN-247, AN-258, AN-266, AN-294, AN-298, LB-45
LF400 ........................................................................ AN-428, AN-447
LF411 ......................................................... AN-294, AN-301, AN-344, AN-447
LF412 ................................................. AN-272, AN-299, AN-301, AN-344, AN-447
LF441 ........................................................................ AN-301, AN-447
LF13006 .............................................................................. AN-344
LF13007 .............................................................................. AN-344
LF13331 ...................................................................... AN-294, AN-447
LF13508 .............................................................. AN-289, AN-360, AN-447
LF13509 .............................................................. AN-289, AN-295, AN-447
LH0002 .................................. AN-13, AN-63, AN-227, AN-244, AN-263, AN-272, AN-301
LH0022 ......................................................................... AN-63, AN-75
LH0023 ....................................................................... AN-245, AN-360
LH0024 ............................................................................... AN-253
LH0032 ............................................................... AN-242, AN-244, AN-253
LH0033 ........................................................ AN-48, AN-115, AN-227, AN-253
LH0042 ................................................................................ AN-63
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DEVICE NUMBER
APPLICATION NOTE
LH0043 ...............................................................................AN-245
LH0052 ..............................................................................•. AN-63
LH0053 ...............................................................................AN-245
LH0062 ............................................................•..................•AN-75
LH0063 ............. , ................................................................. AN-227
LH0070 .................................. " ..... , ...... , . " ... , ....................... AN-301
LH0071 ...............................................................................AN-245
LH0082 .......................................................................AN-244, AN-266
LH0086 .......................................................................AN-245, AN-360
LH0091 ............................................................................ , .. AN-180
LH0094 ...............................................................................AN-301
LH0101 ............................................................................... AN-261
LH1605 .............................................................. , ...... , ...... , .. AN-343
LM10 .................................. AN-211, AN-247, AN-258, AN-271, AN-288, AN-299, AN-300
LM11 .................................................. AN-241, AN-242, AN-260, AN-266, AN-271
LM12 ......................................................... , ....................... AN-446
LM101 ...................................... AN-4, AN-13, AN-20, AN-24, AN-75, LB-42, Appendix A
LM101A .............................. AN-29, AN-30, AN-31 , AN-79, AN-241, LB-1, LB-2, LB-4, LB-8,
LB-14, LB-16, LB-19, LB-28
LM102 .............................................. AN-4, AN-13, AN-30, LB-1, LB-5, LB-6, LB-11
LM103 .........................................................................AN-11 0, LB-41
LM104 .......................................................... AN-21 , LB-3, LB-7, LB-10, LB-40
LM105 ................................................. AN-21,AN-23, AN-110, LB-3, LB-7, LB-10
LM106 .....................................................................AN-41, LB-6, LB-12
LM107 ............................................. AN-20, AN-31 , LB-1, LB-12, LB-19, Appendix A
LM108 ................... AN-29, AN-30, AN-31, AN-63, AN-79, AN-211, AN-241, LB-14, LB-15, LB-21
LM108A .................................................................. AN-260, LB-15, LB-19
LM109 .......................................................................... AN-42, LB-15
LM109A ................................................................................ LB-15
LM110 ........................................................................... LB-11, LB-42
LM 111 ................................................ AN-41 , AN-1 03, LB-12, LB-16, LB-32, LB-39
LM112 ..........................................................................AN-63,LB-19
LM113 ................................................ AN-56, AN-11 0, LB-21, LB-24, LB-28, LB-37
LM117 ................................................... AN-178, AN-181, AN-182, LB-46, LB-47
LM117HV ........................................................................ LB-46, LB-47
LM118 ................................................... LB-17, LB-19, LB-21, LB-23, Appendix A
LM119 ......................................................................... AN-115,LB-23
LM120 ................................................................................ AN-182
LM121 ................................................... AN-79, AN-104, AN-184, AN-260, LB-22
LM121A ................................................................................ LB-32
LM122 ..........................................................................AN-97, LB-38
LM125 .................................................................................AN-82
LM 126 ................................................................................. AN-82
LM129 ......................................................... AN-173,AN-178, AN-262, AN-266
LM131 ....................................................................AN-210, Appendix D
LM131A .............................................................................. AN-210
LM134 ................................................................................. LB-41
LM135 ........................................................ AN-225, AN-262, AN-292, AN-298
LM137 ....................•............................................................ LB-46
LM137HV .............................................................................. LB-46
LM138 ............. '.................................................................... LB-46
LM139 ................................................. , ............•.................. AN-74
LM143 .......................................... , ............................. AN-127, AN-271
LM148. .. . .... .. .. .... ..... .. ... .. . .. .. ... .. ........ .. . . . .......................... AN-260
9-6
DEVICE NUMBER
APPLICATION NOTE
LM150 ................................................................................. LB-46
LM 158 ................................................................................ AN-116
LM160 .................................................................................AN-87
LM161 .........................................................................AN-87, AN-266
LM163 ................................................................................ AN-295
LM194 ......................................................................... AN-222, LB-21
LM195 ................................................................................ AN-11 0
LM199 ................................................................ AN-161, AN-260, AN-360
LM199A .............................................................................. AN-161
LM211 ................................................................................. LB-39
LM216A ................................................................................ LB-37
LM231 ................................................................................ AN-210
LM231A ..............................................................................AN-225
LM235 ................................................................................ AN-225
LM239 .......................•......................................................... AN-74
LM258 ................................................................................AN-116
LM260 .................................................................................AN-87
LM261 ...................... " ......................................................... AN-87
LM301 A ............................................................... AN-178, AN-181 , AN-222
LM304 ................................................................................. LB-40
LM308 ......................................... AN-88, AN-184, AN-272, LB-22, LB-28, Appendix D
LM308A ........................................................................ AN-225, LB-24
LM309 ........................................................................ AN-178, AN-182
LM311 ......................................... AN-41 , AN-1 03, AN-260, AN-263, AN-288, AN-294,
AN-295, AN-307, LB-12, LB-16, LB-18, LB-39
LM313 ................................................................................ AN-263
LM316 ................................................................................ AN-258
LM317 ................................................... " .............. AN-178, LB-35, LB-46
LM317H ................................................................................ LB-47
LM318 .................................................................. AN-115, AN-299, LB-21
LM319 ................................................................ AN-115, AN-271, AN-293
LM320 ................................................................................ AN-288
LM321 ................................................................................. LB-24
LM324 ......................... AN-88, AN-258, AN-274, AN-284, AN-301, LB-44, AB-25, Appendix C
LM329 ................................................ AN-256, AN-263, AN-284, AN-295, AN-301
LM329B .............................................................................. AN-225
LM330 ................................................................................ AN-301
LM331 ............ AN-21 0, AN-240, AN-265, AN-278, AN-285, AN-311, LB-45, Appendix, C Appendix D
LM331A ................................................................... AN-210, Appendix C
LM334 .....................................•.......................... AN-242, AN-256, AN-284
LM335 ................................................................ AN-225, AN-263, AN-295
LM336 ................................................................ AN-202, AN-247, AN-258
LM337 ................................................................................. LB-46
LM338 ........................................................................... LB-49, LB-51
LM339 ................................................................. AN-74, AN-245, AN-274
LM340 ........................................................................AN-103,AN-182
LM340L ............................................................................... AN-256
LM342 ................................................................................ AN-288
LM346 ......................................................................... AN-202, LB-54
LM347 ................................................................................. LB-44
LM348 ......................................................................... AN-202, LB-42
LM349 ................................................................................. LB-42
LM358 ............................. AN-116, AN-247, AN-271, AN-274, AN-284, AN-298, Appendix C
LM358A ...........................................................................Appendix D
9-7
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DEVICE NUMBER
APPLICATION NOTE
LM359 .........................................................................AN-278, AB-24
LM360 ................................................................................. AN-87
LM361 .........................................................................AN-87, AN-294
LM363 ................................................................................AN-271
LM380 .........................................................................AN-69, AN-146
LM381 .........................................................................AN-64, AN-1 04
LM382 ................................................................................ AN-147
LM385 ........................................................ AN-242, AN-256, AN-301, AN-344
LM386 •...................................................................•............ LB-54
LM389 ........................................................ AN-256, AN-263, AN-264, AN-274
LM391 ................................................................................AN-272
LM392 ........................................................................AN-274, AN-286
LM393 ................................................................ AN-271 , AN-274, AN-293
LM394 .......................... AN-262, AN-263, AN-264, AN-271, AN-293, AN-299, AN-311, LB-52
LM395 .................................. AN-178, AN-181, AN-262, AN-263, AN-266, AN-301 , LB-28
LM399 ................................................................................AN-184
LM555 ..................................................................................AB-7
LM556 .................................................................................. AB-7
LM565 .........................................................................AN-46,AN-146
LM566 ................................................................................ AN-146
LM567 .................................................................................AN-46
LM709 ..........................................................................AN-24, AN-30
LM710 ..........................................................................AN-41, LB-12
LM725 ................................................................................. LB-22
LM741 ............................................................. AN-75, AN-79, LB-19, LB-22
LM832 ..........................................•.............................AN-386, AN-390
LM833 ................................................................................AN-346
LM1036 ...............................................................................AN-390
LM1310 ................................................................................AN-81
LM 1524 ....................................................... AN-272, AN-288, AN-292, AN-293
LM1800 .................................................•...................... AN-81,AN-147
LM1812 ................................................................................ AB-20
LM1818 ...............................................................................AN-407
LM1820 ................................................................................ LB-29
LM 1823 ...............................................................................AN-391
LM 1828 ...........................................................................Appendix B
LM1830 ................................................................................ AB-10
LM1837 ...............................................................................AN-407
LM 1845 ...........................................................................Appendix B
LM 1863 .......................................................................AN-381 , AN-382
LM 1865 .......................................................................AN-382, AN-390
LM 1870 ...............................................................................AN-382
LM 1886 ...............................................................................AN-402
LM 1889 ...........•...................................................................AN-402
LM1894 ............................................................... AN-384, AN-386, AN-390
LM1897 ...............................................................................AN-407
LM2878 ...............................................................................AN-14 7
LM2889 ...................................................................•...AN-391, AN-402
LM2907 .........................................•.....................................AN-162
LM2917 ...............................................................................AN-162
LM2931 ...................................................................•............AB-12
LM2931CT .............................................................................AB-11
9-8
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DEVICE NUMBER
APPLICATION NOTE
LM3045 ............................................................................... AN-286
LM3046 ....................................................................... AN-146, AN-299
LM3089 ............................................................................... AN-147
LM3524 ....................................................... AN-272, AN-288, AN-292, AN-293
LM3820 ........................................................................ AN-147, LB-29
LM3900 ........................................... AN-72, AN-263, AN-274, AN-278, LB-20, AB-24
LM3909 ............................................................................... AN-154
LM3911 ................................................................................ LB-27
LM3914 ......................................................................... LB-48, AB-25
LM3915 ............................................................................... AN-386
LM3999 ................................................................................ AN161
LM4250 ......................................................................... AN-88, LB-34
LM7800 ............................................................................... AN-178
LM78L12 ............................................................................. AN-146
LMC835 .............................................................................. AN-435
LP324 ................................................................................ AN-284
MF10 ................................................................................. AN-307
MM1458 .............................................................................. AN-116
MM1558 .............................................................................. AN-116
MM1558C ............................................................................. AN-116
MM2716 ............................................................................... LB-54
MM54104 ............................................................... AN-252, AN-287, LB-54
MM57110 ............................................................................. AN-382
MM74COO .............................................................................. AN-88
MM74C02 .............................................................................. AN-88
MM74C04 .............................................................................. AN-88
MM74C948 ............................................................................ AN-193
MM74LS138 ............................................................................ LB-54
2N4339 ................................................................................ AN-32
LH4101 ............................................................................... AN-480
LM34/35 .............................................................................. AN-460
LM32900 .............................................................................AN-478
LM3578 ................................................................................ AB-30
LPXXXX .............................................................................. AN-462
LM34 ................................................................................. AN-462
LM35 ................................................................................. AN-462
LM385 ................................................................................ AN-462
LMC13334 ............................................................................ AN-462
LP2950 ............................................................................... AN-462
LP2951 ............................................................................... AN-462
LP311 ................................................................................ AN-462
LP324 ................................................................................ AN-462
LP339 ................................................................................ AN-462
LP365 ................................................................................ AN-462
9-9
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Appendix C
Summary of Commercial Reliability Programs
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Typical A + Flow is:
General
• SEM
• Assembly and Seal
National Semiconductor Commercial Reliability Programs
provide a broad range of off-the-shelf enhanced semiconductor products that supply an extra measure of quality and
reliability needed in high-stress or difficult to service applications.
• Four Hour 150·C Bake
National's A + and B + programs allow each individual cus·
tomerto:
• Electrical Test
• Five Temperature Cycles (O·C to + 100·C)
• High Temperature Electrical Test
• Burn-In (160 hours at a minimum junction temperature of
125·C)
• Minimize the need for incoming electrical inspection
• Eliminate the need and associated costs of using independent testing laboratories
• DC Parametric and Function Tests
• Tightened Quality Control Inspection Plans
• Reduction in infant mortality rate
Note: Certain products may follow slightly different process flows dictated
by specific capabilities and device characteristics, consult NSC.
• Reduction in reworked board costs
• Reduction in warranty and service costs
P + Product Enhancement
A + Product Enhancement
The P+ product enhancement program applies to regulator
devices and offers an added advantage. P + involves a dynamic self-heating burn-in that tests the thermal shutdown
of the regulator. P + is proven more effective than the standard 125·C burn-in as an early screen for infant mortality
defects. It sharply reduces the cost of testing incoming components. Reliability Report L-140 further explains the P +
process. The following chart lists regulators which receive
P + prior to shipment and at no additional cost.
The A + Product Enhancement incorporates the benefits of
the Multiple-Pass and Elevated Temperature along with
"BURN-IN."
The A + Program provides:
• 100% Temperature Cycling
• 100% Electrical Testing at Room and High Temperature
• 100% Burn-In Testing Combining Increased Temperature with Applied Voltage
• Acceptable Quality Levels Greater than Industry Norm
Package Types
Device
TO-3
TO-39H TO-220T TO-202 P TO-92Z
KSTEEL
LM109/309
X
X
LM117/317
X
X
LM117HV/317HV
X
X
LM120/320
X
LM123/323
X
LM137/337
LM137HV /337HV
LM138/338
X
LM140/340
X
LM145/345
X
LM150/250/350
X
LM196/396
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
LM2930/2935/2940/2984
X
LM2931
X
LM78XX
X
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Appendix 0
Military Aerospace Programs
from National Semiconductor
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This appendix is intended to provide a brief overview of military products available from National Semiconductor. For
further information, refer to our 1987 Reliability Handbook.
MIL-STD-883
Although originally intended to establish uniform test methods and procedures, MIL-STD-883 has also become the
general speCification for non-JAN military product. Revision
C of this document defines the minimum requirements for a
device to be marked and advertised as 883-compliant. Included are design and construction criteria, documentation
controls, electrical and mechanical screening requirements,
and quality control procedures. Details can be found in paragraph 1.2.1 of MIL-STD-883.
National offers both 883 Class Band 883 Class S product.
The screening requirements for both classes of product are
outlined in Table III.
As with DESC specifications, a manufacturer is allowed to
use his standard electrical tests provided that all critical parameters are tested. Also, the electrical test parameters,
test conditions, test limits, and test temperatures must be
clearly documented. At National Semiconductor, this information is available via our RETS (Reliability Electrical Test
Specification Program). The RETS document is a complete
description of the electrical tests performed and is controlled by our QA department. Individual copies are available
upon request.
Some of National's older products are not completely compliant with MIL-STD-883 but are still required for use in military systems. These devices are screened to the same
stringent requirements as 883 product but are marked
"-MIL".
MIL-M-38510
The MIL-M-38510 Program, which is sometimes called the
JAN IC Program, is administered by the Defense Electronics
Supply Center (DESC). The purpose of this program is to
provide the military community with standardized products
that have been manufactured and screened to governmentcontrolled specifications in government-certified facilities.
All 38510 manufacturers must be formally qualified and their
products listed on DESC's Qualified Products List (QPL) before devices can be marked and shipped as JAN product.
There are two processing levels specified within MIL-M38510: Classes Sand B. Class S is typically specified for
space flight applications, while Class B is used for aircraft
and ground systems. National is a major supplier of both
classes of devices. Screening requirements are outlined in
Table III.
Tables I and II explain the JAN device marking system.
Copies of MIL-M-38510, the QPL, and other related documents may be obtained from:
Naval Publications and Forms Center
5801 Tabor Avenue
Philadelphia, PA 19120
(212) 697-2179
DESC Specifications
Military Screening Program (MSP)
DESC specifications are issued to provide standardized versions of devices which are not yet available as JAN product.
MIL-STD-883 Class B screening is coupled with tightly controlled electrical speCifications which have been written to
allow a manufacturer to use his standard electrical tests. A
current listing of National's DESC specification offerings can
be obtained from our franchised distributors, sales offices,
or DESC. DESC is located in Dayton, Ohio.
National's Military Screening Program was developed to
make screened versions of advanced products such as gate
arrays and microprocessors available more quickly than is
possible for JAN and 883 devices. Through this program,
screened product is made available for prototypes and
breadboards prior to or during the JAN or 883 qualification
activities. MSP products receive the 100% screening of Table III but are not subjected to Group C and D quality conformance testing. Other criteria such as electrical testing
and temperature range will vary depending upon individual
device status and capability.
9-11
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TABLE I. The MIL-M-38510 Part Marking
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JM38510/XXXXXYYY
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A = Solder Oipped
B =Tin Plate
C= Gold Plate
X = Any lead finish above
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' - - - Slash Sheet Number
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Designator (M, 0, R, or H per
paragraph 3.4.1.3 of MIL-M38510)
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Package
Designation
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A
Microcircuit Industry
Description
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B
C
D
E
F
G
H
I
J
K
L
M
N
P
Q
R
S
T
U
V
W
X
Y
Z
2
3
14·Pin 1/4" X 1/4" (metal) flat pack
14-Pin 3/16" X 1/4" flat pack
14-Pin 1/4" X 3/4" dual·in·line
14-Pin 1/4" X 3/8" (ceramic) flat pack
16·Pin 1/4" X 3/8" dual·in·line
16·Pin 1/4" X 3/8" (metal or ceramic)
flat pack
8·pin TO·99 can or header
10-pin 1/4" x 1/4" (metal) flat pack
1O-pin TO·1 00 can or header
24·pin 1/2" x 1·1/4" dual-in·line
24-pin 3/8" x 5/8" flat pack
24-pin 1/4" x 1·1/4" dual·in·line
12·pin TO·101 can or header
(Note 1)
8-pin 1/4" x 3/8" dual·in·line
40-pin 3/16" x 2·1/16" dual·in·line
20·pin 1/4" x 1·1/16" dual·in·line
20'pin 1/4" x 1/2" flat pack
(Note 1)
(Note 1)
18·pin 3/8" x 15/16" dual·in·line
22'pin 3/8" x 1·1/8" dual-in·line
(Note 1)
(Note 1)
(Note 1)
20·terminaI0.350" x 0.350" chip carrier
28-terminaI0.450" x 0.450" chip carrier
Note 1: These letters are aSSigned to packages by individual detail specifi~
cations and may be assigned to different packages in different specifica-
tions.
9·12
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TABLE 111.100% Screening Requirements
ClassS
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ClassB
Screen
Method
Reqmt
Method
Reqmt
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1.
Wafer Lot Acceptance
5007
All Lots
-
2.
Nondestructive Bond Pull
2023
100%
-
3.
Internal Visual (Note 1)
2010, Condition A
100%
2010, Condition B
100%
4.
Stabilization Bake
100B, Condition C,
24 hrs. Min.
100%
100B, Condition C,
24 hrs. Min.
100%
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Temp. Cycling (Note 2)
1010, Condition C
100%
1010, Condition C
100%
6.
Constant Acceleration
2001, Condition E (Min.)
y 1 Orientation Only
100%
2001, Condition E, (Min.),
y 1 Orientation Only
100%
7.
Visual Inspection (Note 3)
100%
100%
B.
Particle Impact Noise Detection (PIND)
2020, Condition A (Note 4)
100%
-
9.
Serialization
(NoteS)
100%
10.
Interim (Pre·Burn·ln) Electrical
Parameters
Per Applicable Device
Specification (Note 13)
100%
Per Applicable Device
Specification (Note 6)
-
11.
Burn·ln Test
1015
240 Hrs. @ 12S'C Min.
(Cond. F Not Allowed)
100%
1015
160 Hrs.
Interim (Post-Burn·ln) Electrical
Parameters
Per Applicable Device
Specification (Note 13)
100%
Reverse Bias Burn·ln (Note 7)
1015; Test Condition A, C,
72 Hrs. @ lS0'C Min.
(Cond. F Not Allowed)
100%
All Lots
12.
13.
15.
PDA Calculation
5% Parametric (Note 14),
3% Functional -2S'C
16.
Final Electrical Test
a) Static Tests
1) 2S'C (Subgroup 1, Table I, 5005)
2) Max & Min Rated Operating Temp.
(Subgroups 2, 3, Table I, 5005)
b) Dynamic Tests & Switching Tests, 2S'C
(Subgroups 4, 9, Table I, 5005)
c) Functional Test, 2S'C
(Subgroup 7, Table I, 5005)
Per Applicable Device
Specification
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100%
100%
100%
100%
100%
100%
100%
100%
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TABLE III. 100% Screening Requirements (Continued)
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ClassS
Screen
Method
Reqmt
100%, (Note 8)
17.
Seal Fine, Gross
1014
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18.
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2012 Two Views
100%
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19.
Qualification or Quality Conformance
Inspection Test Sample Selection
(Note 11)
Samp.
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100%
Note 1: Unless otherwise specified, at the manufacturer's option, test samples for Group B, bond strength (Method 5005) may be randomly selected prior to or
following internal visual (Method 5004). prior to sealing provided all other specification requirements are satisfied (e.g. bond strength requirements shall apply to
each inspection lot, bond failures shall be counted even if the bond would have failed internal visual).
E
Note 2: For Class B devices, this test may be replaced with thermal shock method 1011, test condition A, minimum.
C)
Note 3: At the manufacturer's option, visual inspection for catastrophic failures may be conducted after each of the thermal/mechanical screens, after the
sequence or after seal test. Catastrophic failures are defined as missing leads, broken packages, or lids off.
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Note 4: The PI NO test may be performed in any sequence after step 6 and prior to step 16. See MIL·M·3B510, paragraph 4.6.3.
Note 5: Class S devices shall be serialized prior to interim electrical parameter measurements.
Note 6: When specified, all devices shall be tested for those parameters requiring delta calculations.
Note 7: Reverse bias burn-in is a requirement only when specified in the applicable device specification. The oreler of performing burn-in and reverse bias burn-in
may be inverted.
Note 8: For Class S devices, the seal test may be performed in any sequence between step 16 and step 19, but it shall be performed after all shearing and forming
operations on the terminals.
Note 9: For Class B devices, the fine and gross seal tests shall be performed separate or together in any sequence and order between step 6 and step 20 except
that they shall be performed after all shearing and forming operations on the terminals. When 100% seal screen cannot be performed after shearing and forming
(e.g. flatpacks and chip carriers) the seal screen shall be done 100% prior to these operations and a sample lest (LTPO ~ 5) shall be performed on each
inspection lot following these operations. If the sample fails, 100% rescreening shall be required.
Note 10: The radiographic screen may be performed In any sequence after step 19.
Note 11: Samples shall be selected for testing in accordance with the specific device class and lot requirements of Method 5005
Note 12: External Visual shall be performed on the lot any time after step 19 and prior to shipment.
Note 13: Read and Record when past burn·in delta measurements are specified.
Note 14: POA shall apply to all static, dynamic, functional, and switching measurements at either 25°C or maximum rated operating temperature.
'a
'a
CD
Military Analog Products Available From National Semiconductor
Listed below are the military class B Analog devices available from National Semiconductor. Many of these are also available as
Class S product. Additional information including new product plans can be obtained from our sales offices.
DevieeType
Mil'
ClassB
883
ClassB
Dese
JAN
DevieeType
Mil'
ClassB
AHOO14D
X
LHOO32G
X
AHOO15D
X
LHOO33AG
X
AHOO19D
X
LHOO33G
X
LF111H
X
LHOO36G
X
883
ClassB
Dese
JAN
X
::s
Q,
;Co
f
~
::;:
DI
-<
X
~
ao
LF11201D
X
LHOO38D
X
'a
DI
LF11202D
X
LHOO41G
X
CD
LF11331D
X
LHOO42D
X
LF11332D
X
LHOO42H
X
LF11333D
X
LHOO43G
X
LF11508D
X
LHOO44AH
X
LF11509D
X
LHOO44H
X
LHOO52H
X
LF147D
X
LF155AH
X
LF155H
X
LHOO53G
X
X
LHOO61K
X
X
LHOO62D
X
X
LHOO62H
X
LHOO63K
X
X
LHOO70-0H
X
LF156J-8
X
LHOO70-1H
X
LF156W
X
LHOO70-2H
X
LF155J-8
LF155W
LF156AH
X
LF156H
X
LF157AH
X
LHOO71-0H
X
LF157H
X
LHOO71-1H
X
LF198H
X
LHOO71-2H
X
LF411MH
X
X
LHOO75G
X
X
LHOO76G
X
X
X
LHOO82D
X
LHOO84D
X
LF411W
LF412MH
LF441MH
X
LF442MH
X
LHOO86D
X
LF444MD
X
LHOO91D
X
LHOOO2H
LHOO94D
X
LHOOO3H
X
LHOO101AK
X
X
X
X
n
-a
cc
a
iiJ
3
-a
o
3
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~
3
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....
LHOOO4H
X
LH0101K
LHOO20G
X
LH2101AD
X
LHOO21K
X
LH2108AD
X
LHOO22D
X
LH2108D
X
LHOO22H
X
LH2110D
X
LHOO23G
X
LH2111D
LHOO24H
X
LH2111F
X
X
'Some older products are not completely compliant with MIL·STD·B83 but are stili required for use in military systems. These devices are screened to the same
stringent requirements as 883 product but are marked ""·MIL".
9-15
f:t
iii
~ r-------------------------------------------------------------------------------------~
~
8
-g
'ECP
Military Analog Products Available From National Semiconductor
listed below are the military class B Analog devices available from National Semiconductor. Many of these are also available as
Class S product. Additional information including new product plans can be obtained from our sales offices.
Device Type
(I)
Ci
c:
LH24250F
Mil"
883
ClassB
ClassB
LM10H
X
Z
LM101AH
X
E
LM101AJ-14
X
LM101AJ
X
2
f I)
E
LM101AW
01
E
Device Type
JAN
Mil"
883
ClassB
ClassB
Desc
X
X
LM117HVKSTL
X
X
X
LMl17KSTEEL
X
X
X
LM118H
X
X
LM118J-8
X
X
LM118J
X
X
e
a..
LM102H
X
Uvi103H-3.0
X
X
LM119H
X
X
CP
LM103H-3.3
X
X
LM119J
X
X
~
LM103H-3.6
X
X
LM120H-12
X
2CP
LM103H-3.9
X
X
LM120H-15
X
LM104H
X
LMI20H-5.0
X
LM105H
X
LM120K-12
X
LM106H
X
LM120K-15
X
LM107H
X
LMI20K-5.0
X
LM107J-14
X
LM121AH
X
LM107J
X
LM121H
X
LM108AH
X
X
LM122H
X
LM108AJ-8
X
X
LM123KSTEEL
X
LM108AJ
X
LM124AJ
X
u
fI)
CC
~
~
~
.!:!!
1:1
c:
CP
CI..
CI..
CC
LM118W
LM108AW
LM124J
X
X
LM125H
X
LM108J-8
X
LM126H
X
LM108J
X
LM129AH
X
LM109H
X
LM129BH
X
LM109KSTEEL
X
LM131AH
X
LM11H
X
LM131H
X
LM110H
X
LM135H
X
LM110J-8
X
LMI36AH-2.5
X
LM110J
X
LMI36H-2.5
X
LM111H
X
X
LMI36H-5.0
X
LM111J
X
X
LM137H
X
X
X
LM137HVH
X
X
X
X
X
LM112H
X
LM137HVKSTEEL
X
X
LM113-1H
X
X
LM137KSTEEL
X
X
LM113-2H
X
X
LM138KSTEEL
X
LM113H
X
X
LM139AJ
X
LM139J
X
LM117H
X
X
X
X
X
LM108H
LM111W
JAN
LM117HVH
X
o
:;:;
as
Desc
X
'Some older products are not completely compliant with MIL-STO-883 but are still required for use in military systems. These devices are screened to the same
stringent requirements as B83 product but are marked" -MIL".
9-16
Military Analog Products Available From National Semiconductor
Listed below are the military class B Analog devices available from National Semiconductor. Many of these are also available as
Class S product. Additional information including new product plans can be obtained from our sales offices.
OeviceType
Mil"
883
ClassB
ClassB
Oesc
LM139W
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
LM140AK-12
LM140AK-15
LMI40AK-5.0
LM140K-12
LM140K-15
LMI40K-5.0
LM140LAH-12
LMI40LAH-15
LMI40LAH-5.0
LM143H
LMI44H
LMI45K-5.0
LMI45K-5.2
LM146J
LM148J
LM149J
LM150KSTEEL
LM1558J
LM158AH
LM158AJ
LM158H
LM158J
LM160J
LMI85BXH-l.2
LMI85BYH-1.2
883
ClassB
x
x
x
LM193AH
LM193H
LM193J-8
LM193W
LM195H
LM195K
LM199AH-20
LM199AH
x
x
LM199H
LM4250H
LM4250J
x
x
x
x
x
x
LM567H
x
LM709H
LM710H
LM723H
x
LM723J
x
LM725H
LM733H
LM741AJ-14
LM741AJ
LM741H
LM7415-14
LM741J
x
x
x
x
x
x
x
LM741W
x
x
x
x
LM747H
LM747J
LM748H
LM748J
x
x
x
x
x
LM555J
LM556J
JAN
x
x
LM555H
x
Oese
x
x
x
x
x
x
LM194H
x
x
x
LM160J-14
LM161J
LMI85H-l.2
x
LM160H
LM161H
x
Mil'
ClassB
LM709AH
x
x
x
x
x
x
x
LM1558H
LM161F
OevleeType
x
LM1536H
LM1596H
JAN
x
x
x
x
x
x
x
x
'Some older products are not completely compliant with MIL-STD-B83 but are still required for use in military systems. These devices are screened to the same
stringent requirements as 883 product but are marked "-MIL".
9-17
.;
==
:s
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~NaHonal
Semiconductor
CorporaHon
I
Appendix E
Understanding Integrated Circuit
Package Power Capabilities
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INTRODUCTION
The short and long term reliability of National Semiconductor's interface circuits, like any integrated circuit, is very dependent on its environmental condition. Beyond the mechanical/environmental factors, nothing has a greater influence on this reliability than the electrical and thermal stress
seen by the integrated circuit. Both of these stress issues
are specifically addressed on every interface circuit data
sheet, under the headings of Absolute Maximum Ratings
and Recommended Operating Conditions.
Failure rate is the number of devices that will be expected to
fail in a given period of time (such as, per million hours). The
mean time between failure (MTBF) is the average time (in
hours) that will be expected to elapse after a unit has failed
before the next unit failure will occur. These two primary
"units of measure" for device reliability are inversely related:
MTBF =
1
Failure Rate
Although the "bathtub" curve plots the overall failure rate
versus time, the useful failure rate can be defined as the
percentage of devices that fail per-un it-time during the flat
portion of the curve. This area, called the useful life, extends
between t1 and t2 or from the end of infant mortality to the
onset of wearout. The useful life may be as short as several
years but usually extends for decades if adequate design
margins are used in the development of a system.
Many factors influence useful life including: pressure, mechanical stress, thermal cycling, and electrical stress. However, die temperature during the device's useful life plays an
equally important role in triggering the onset of wearout.
However, through application calls, it has become clear that
electrical stress conditions are generally more understood
than the thermal stress conditions. Understanding the importance of electrical stress should never be reduced, but
clearly, a higher focus and understanding must be placed on
thermal stress. Thermal stress and its application to interface circuits from National Semiconductor is the subject of
this application note.
FACTORS AFFECTING DEVICE RELIABILITY
Figure 1 shows the well known "bathtub" curve plotting failure rate versus time. Similar to all system hardware (mechanical or electrical) the reliability of interface integrated
circuits conform to this curve. The key issues associated
with this curve are infant mortality, failure rate, and useful
life.
FAILURE RATES vs TIME AND TEMPERATURE
The relationship between integrated circuit failure rates and
time and temperature is a well established fact. The occurrence of these failures is a function which can be represented by the Arrhenius Model. Well validated and predominantly used for accelerated life testing of integrated circuits, the
Arrhenius Model assumes the degradation of a performance
parameter is linear with time and that MTBF is a function of
temperature stress. The temperature dependence is an exponential function that defines the probability of occurrence.
This results in a formula for expressing the lifetime or MTBF
at a given temperature stress in relation to another MTBF at
a different temperature. The ratio of these two MTBFs is
called the acceleration factor F and is defined by the following equation:
INFANT
MDRTALITY
(SHADED AREA)
to
II
EARLY LIFE
12
USEFUL LIFE
WEARDUT TIME
TL/H/9312-1
(...!. _...!.)]
T1
F = X1 = exp [~
X2
K T2
FIGURE 1. Failure Rate vii Time
Infant mortality, the high failure rate from time to to t1 (early
life), is greatly influenced by system stress conditions other
than temperature, and can vary widely from one application
to another. The main stress factors that contribute to infant
mortality are electrical transients and noise, mechanical
maltreatment and excessive temperatures. Most of these
failures are discovered in device test, burn-in, card assembly and handling, and initial system test and operation. Although important, much literature is available on the subject
of infant mortality in integrated circuits and is beyond the
scope of this application note.
Where: X1 = Failure rate at junction temperature T1
X2 = Failure rate at junction temperature T2
T = Junction temperature in degrees Kelvin
E = Thermal activation energy in electron volts
(ev)
K = Boltzman's constant
9-18
r-----------------~~------------------------------------------------_.~
However, the dramatic acceleration effect of junction temperature (chip temperature) on failure rate is illustrated in a
plot of the above equation for three different activation energies in Figure 2. This graph clearly demonstrates the importance of the relationship of junction temperature to device failure rate. For example, using the 0.99 ev line, a 30'
rise in junction temperature, say from 130'C to 160'C, results in a 10 to 1 increase in failure rate.
flows from the chip to the ultimate heat sink, the ambient
environment. There are two predominant paths. The first is
from the die to the die attach pad to the surrounding package material to the package lead frame to the printed circuit
board and then to the ambient. The second path is from the
package directly to the ambient air.
Improving the thermal characteristics of any stage in the
flow chart of Figure 4 will result in an improvement in device
thermal characteristics. However, grouping all these characteristics into one equation determining the overall thermal
capability of an integrated circuit/package/environmental
condition is possible. The equation that expresses this relationship is:
!;>1000k
:il
:=
!
~
lOOk
f--t---I----II--+.....,.~-l
10k
f--t---I----II-~'!;-:;h...-!
lk
1--+--t-"""7I~~~+--{
TJ = TA + PD (OJN
Where: TJ = Die junction temperature
TA = Ambient temperature in the vicinity device
~
~
a:
100 I--+--;.,..~Ft--+I--+--{
::l
:3
10 I-~Oo£-t---jt:L."""F=t--{
PD = Total power dissipation (in watts)
if
0JA = Thermal resistance junction-to-ambient
60 90 120 150 180 210
JUNCTION TEMPERATURE ('C)
OJA, the thermal resistance from device junction-to-ambient
temperature, is measured and specified by the manufacturers of integrated circuits. National Semiconductor utilizes
special vehicles and methods to measure and monitor this
parameter. All circuit data sheets specify the thermal characteristics and capabilities of the packages available for a
given device under specific conditions-these package
power ratings directly relate to thermal resistance junctionto-ambient or 0JA.
Although National provides these thermal ratings, it is critical that the end user understand how to use these numbers
to improve thermal characteristics in the development of his
system using IC components.
TL/H/9312-2
FIGURE 2, Failure Rate as a Function
of Junction Temperature
DEVICE THERMAL CAPABILITIES
There are many factors which affect the thermal capability
of an integrated circuit. To understand these we need to
understand the predominant paths for heat to transfer out of
the integrated circuit package. This is illustrated by Figures
3 and 4.
Figure 3 shows a cross-sectional view of an assembled integrated circuit mounted into a printed circuit board.
Figure 4 is a flow chart showing how the heat generated at
the power source, the junctions of the integrated circuit
DEVICE LEAD
TLlH/9312-3
FIGURE 3, Integrated Circuit Soldered into a Printed Circuit Board (Cross-Sectional View)
DIE
JUNCTION
(ENERGY
SOURCE)
r-+
DIE
r-+
DIE
ATIACH
PAD
r--+
PACKAGE
MATERIAL
r--+
LEAD
FRAME
f-+
PRINTED
CIRCUIT
BOARD
AIRFILM
AROUND
PACKAGE
f-+
AMBIENT
f-+
AMBIENT
TLlH/9312-4
FIGURE 4, Thermal Flow (Predominant Paths)
9-19
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The slope of the straight line between these two points is
minus the inversion of the thermal resistance. This is referred to as the derating factor.
1
Derating Factor = - n-
DETERMINING DEVICE OPERATING
JUNCTION TEMPERATURE
From the above equation the method of determining actual
worst-case device operating junction temperature becomes
straightforward. Given a package thermal characteristic,
6JA, worst-case ambient operating temperature, TA(max),
the only unknown parameter is device power dissipation,
PD' In calculating this parameter, the dissipation of the integrated circuit due to its own supply has to be considered,
the dissipation within the package due to the external load
must also be added. The power associated with the load in
a dynamic (switching) situation must also be considered.
For example, the power associated with an inductor or a
capacitor in a static versus dynamic (say, 1 MHz) condition
is significantly different.
UJA
As mentioned, Figure 5 is a plot of the safe thermal operating area for a device in a 16-pin molded DIP. As long as the
intersection of a vertical line defining the maximum ambient
temperature (70DC in our previous example) and maximum
device package power (600 mW) remains below the maximum package thermal capability line the junction temperalure will remain below 150"C-the limit for a molded package. If the intersection of ambient temperature and package
power falls on this line, the maximum junction temperature
will be 150DC. Any intersection that occurs above this line
will result in a junction temperature in excess of 150DC and
is not an appropriate operating condition.
The junction temperature of a device with a total package
power of 600 mW at 70"C in a package with a thermal resistance of 6SDC/W is 10SDC.
TJ = 70"C + (63"C/W) x (0.6W) = 10SDC
2.4
The next obvious question is, "how safe is 10SDC?"
~
MAXIMUM ALLOWABLE JUNCTION TEMPERATURES
2.0 111,,:--+--1---+--;-'---1---1
~ 1.6
What is an acceptable maximum operating junction temperature is in itself somewhat of a difficult question to answer.
Many companies have established their own standards
based on corporate policy. However, the semiconductor industry has developed some defacto standards based on the
device package type. These have been well accepted as
numbers that relate to reasonable (acceptable) device lifetimes, thus failure rates.
ls-p,N
I
I--I---II--t-MO~OEO PACKAGE
Ci.i
.,. 1.2
is
...
~ 0.8
O4
•
t-"I!rl--'IMAXIMUM PACbGE
~I~
OPERATING" LINE
AREA
~
'---
THERMAL CAPABILITY
I'
_~
Po-6DOnMI
OPERATING
POINT t
r--
r--
i
SLOPE= __1 ; _
8JA
I'
70 D e
~
I'
~
A= j
~
0 ............._ .......--.1.--'---'""---'
25 50 75 100 125 150 175
National Semiconductor has adopted these industry-wide
standards. For devices fabricated in a molded package, the
maximum allowable junction temperature is 150"C. For
these devices assembled in ceramic or cavity DIP packages, the maximum allowable junction temperature is
175"C. The numbers are different because of the differences in package types. The thermal strain associated with the
die package interface in a cavity package is much less than
that exhibited in a molded package where the integrated
circuit chip is in direct contact with the package material.
TEMPERATURE (DC)
TL/H/9312-5
FIGURE 5_ Package Power Capability
vs Temperature
The thermal capabilities of all integrated circuits are expressed as a power capability at 25°C still air environment
with a given derating factor. This simply states, for every
degree of ambient temperature rise above 25DC, reduce the
package power capability stated by the derating factor
which is expressed in mWI"C. For our example-a 6JA of
6soC/W relates to a derating factor of 15.9 mWI"C.
Let us use this new information and our thermal equation to
construct a graph which displays the safe thermal (power)
operating area for a given package type. Figure 5 is an example of such a graph. The end points of this graph are
easily determined. For a 16-pin molded package, the maximum allowable temperature is 150DC; at this point no power
dissipation is allowable. The power capability at 25DC is
1.9SW as given by the following calculation:
FACTORS INFLUENCING PACKAGE
THERMAL RESISTANCE
As discussed earlier, improving any portion of the two primary thermal flow paths will result in an improvement in
overall thermal resistance junction-to-ambient. This section
discusses those components of thermal resistance that can
be influenced by the manufacturer of the integrated circuit. It
also discusses those factors in the overall thermal resistance that can be impacted by the end user of the integrated
circuit. Understanding these issues will go a long way in
understanding chip power capabilities and what can be
done to insure the best possible operating conditions and,
thus, best overall reliability.
P @25DC= TJ(max)-TA = 150DC-25DC = 19SW
D
6JA
6SDC/W
.
9-20
l>
Ole Size
't:J
't:J
CD
::I
110
Figure 6 shows a graph of our 16-pin DIP thermal resistance
as a function of integrated circuit die size. Clearly, as the
chip size increases the thermal resistance decreases-this
relates directly to having a larger area with which to dissipate a given power.
l!l_
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.....
Lead Frame Material
130
-
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-....
90
70
0.7
0.6
A~
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Kr VAR
,
DIE
lk MIL2
One of the major paths of dissipating energy generated by
the integrated circuit is through the device leads. As a result
of this, the graph of Figure 8 comes as no surprise. This
compares the thermal resistance of our 16-pin package soldered into a printed circuit board (board mount) compared
to the same package placed in a socket (socket mount).
Adding a socket in the path between the PC board and the
device adds another stage in the thermal flow path, thus
increasing the overall thermal resistance. The thermal capabilities of National Semiconductor's interface circuits are
specified assuming board mount conditions. If the devices
are placed in a socket the thermal capabilities should be
reduced by approximately 5% to 10%.
9-21
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500
1000
AIR FLOW (LINEAR FEETI MINUTE)
Some confusion exists between the difference in thermal
resistance junction-to-ambient (6JA) and thermal resistance
junction-to-case (6Jcl. The best measure of actual junction
temperature is the junction-to-ambient number since nearly
all systems operate in an open air environment. The only
Situation where thermal resistance junction-to-case is important is when the entire system is immersed in a thermal bath
and the environmental temperature is indeed the case temperature. This is only used in extreme cases and is the exception to the rule and, for this reason, is not addressed in
this application note.
Board vs Socket Mount
"U
III
n
III
Other Factors
TLlH/9312-7
c::;:
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flZF
A number of other factors influence thermal resistance. The
most important of these is using thermal epoxy in mounting
ICs to the PC board and heat sinks. Generally these techniques are required only in the very highest of power applications.
FIGURE 7. Thermal Resistancevs
Lead Frame Material
:::;'
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CD
TLlH/9312-9
2
3 4 5 6 7 8910
DIE SIZE (kMIL2)
~
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MOLDED jCiiE
FIGURE 9. Thermal Resistance vs Air Flow
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16·PlN MOLDED DIP
~ BOARD MOUNT-STILL AIR
c..
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S·
CQ
AirFlow
Figure 7 shows the influence of lead frame material (both
die attach and device pins) on thermal resistance. This
graph compares our same 16-pin DIP with a copper lead
frame, a Kovar lead frame, and finally an Alloy 42 type lead
frame-these are lead frame materials commonly used in
the industry. Obviously the thermal conductivity of the lead
frame material has a significant impact in package power
capability. Molded interface circuits from National Semiconductor use the copper lead frame exclusively.
~~ti
CD
!a
III
When a high power situation exists and the ambient temperature cannot be reduced, the next best thing is to provide air
flow in the vicinity of the package. The graph of A'gure 9
illustrates the impact this has on thermal resistance. This
graph plots the relative reduction in thermal resistance normalized to the still air condition for our 16·pin molded DIP.
The thermal ratings on National Semiconductor's interface
circuits data sheets relate to the still air environment.
TLlH/9312-6
~Ciii
c..
TL/H/9312-B
FIGURE 6. Thermal Resistance vs Die Size
150
~""'"
::I
FIGURE 8. Thermal Resistance vs
Board or Socket Mount
2
3 4 5 6 78910
DIE SIZE (kMIL2)
w
70
ic:
SOCKET
2
3 4 5 6 7 8910
DIE SIZE (kMIL2)
50
z ....
"'-
~ r--.,~
60
.... r--.,
60
170
80
90
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90 ~
i~
:!IE::!.
w
c..
100
o
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r-------------------------------------------------------------------------------~
NATIONAL SEMICONDUCTOR
PACKAGE CAPABILITIES
i
i
Figures 10 and 11 show composite plots of the thermal
characteristics of the most common package types in the
National Semiconductor Linear Circuits product family. Figure 10 is a composite of the copper lead frame molded
package. Figure 11 is a composite of the ceramic (cavity)
DIP using poly die attach. These graphs represent board
mount still air thermal capabilities. Another, and final, thermal resistance trend will be noticed in these graphs. As the
number of device pins increase in a DIP the thermal resistance decreases. Referring back to the thermal flow chart,
this trend should, by now, be obvious.
OS
RATINGS ON INTERFACE CIRCUITS DATA SHEETS
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In conclusion, all National Semiconductor Linear Products
define power dissipation (thermal) capability. This information can be found in the Absolute Maximum Ratings section
of the data sheet. The thermal information shown in this
application note represents average data for characterization of the indicated package. Actual thermal resistance can
vary from ± 10% to ± 15% due to fluctuations in assembly
quality, die shape, die thickness, distribution of heat sources
on the die, etc. The numbers quoted in the linear data
~
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rc above 2S'C; derate molded package
If the molded package is used at a maximum ambient temperature of 70'C, the package power capability is 945 mW.
Po@70'C=1476mW-(11.8mW/'C)X(70'C-25'C)
= 945mW
Cavity (J Package) DIP"
Poly Ole Attach Board
Mount-Stlll Air
130
w
'tJ
c
• Derate cavity package at 10 mW
at II.B mW/'C above 2S'C.
Molded (N Package) DIP"
Copper Leadframe-HTP
Ole Attach Board MountStili Air
CU
at
.!S
sheets reflect a 15% safety margin from the average numbers found in this application note. Insuring that total package power remains under a specified level will guarantee
that the maximum junction temperature will not exceed the
package maximum.
The package power ratings are specified as a maximum
power at 25'C ambient with an associated derating factor
for ambient temperatures above 25'C. It is easy to determine the power capability at an elevated temperature. The
power specified at 25'C should be reduced by the derating
factor for every degree of ambient temperature above 25'C.
For example, in a given product data sheet the following will
be found:
Maximum Power Dissipation" at 25'C
Cavity Package
1509 mW
Molded Package 1476 mW
140 ,----r--r--r--r-I"T"T"n
110
w
120 I--""''''''''=-+-+-++H-H
~;
100
~i
90
~"fli
~~~
70
;~~
80
~t;
50
m~
60 f---I-+l-F
"'2.
30
~~
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7~
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Absolute Maximum Ratings (Note 11)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications_
Supply Voltage
+35Vto -0.2V
Output Voltage
+6Vto -1.0V
Output Current
10mA
Storage Temperature,
TO-46 Package
Lead Temp. (Soldering, 4 seconds)
TO-46 Package
TO-92 Package
Specified Operating Temp. Range (Note 2)
-76'F to + 356'F
TO-92 Package
*
+300'C
+ 260'C
LM34, LM34A
TMINto TMAX
-50'Fto +300'F
LM34C, LM34CA
LM34D
+ 32'Fto +212'F
-40'Fto +230'F
- 76'F to + 300'F
DC Electrical Characteristics (Note 1, Note 6)
LM34A
Conditions
Parameter
Accuracy (Note 7)
=
=
=
=
Typical
Tested
Limit
(Note 4)
+77'F
O'F
TMAX
TMIN
±0.4
±0.6
±0.8
±0.8
Nonlinearity (Note 8)
TMIN ,;; TA';; TMAX
±0.35
Sensor Gain
(Average Slope)
TMIN ,;; TA';; TMAX
+10.0
+9.9,
+10.1
Load Regulation
(Note 3)
TA = +77'F
TMIN ,;; TA';; TMAX
0,;; IL';; 1 mA
±0.4
±O.5
±1.0
Line Regulation (Note 3)
TA = +77'F
5V,;; Vs';; 30V
±0.01
±0.02
±0.05
75
131
76
132
90
+0.5
+1.0
2.0
Quiescent Current
(Note 9)
Change of Quiescent
Current (Note 3)
TA
TA
TA
TA
=
=
=
=
Vs
Vs
Vs
Vs
+5V, +77'F
+5V
+30V. +77'F
+30V
4V ,;; Vs ,;; 30V, + 77'F
5V,;; Vs';; 30V
Temperature Coefficient
of Quiescent Current
Minimum Temperature
for Rated Accuracy
In circuit of Figure 1,
IL = 0
Long-Term Stability
Tj
=
TMAX for 1000 hours
LM34CA
Design
Limit
(Note 5)
±1.0
Typical
±0.4
±0.6
±0.8
±0.8
±2.0
±2.0
±0.7
Tested
Limit
(Note 4)
±1.0
±2.0
±2.0
±3.0
'F
+10.0
+9.9,
+10.1
mVI'F, min
mVI'F, max
±3.0
mVlmA
mV/mA
±O.1
mVIV
mVIV
±1.0
±0.01
±0.02
±0.05
±O.1
90
163
75
116
76
117
2.0
3.0
0.5
1.0
+0.30
+0.5
+3.0
+5.0
±0.16
'F
'F
'F
'F
±0.6
±0.4
±O.5
92
Units
(Max)
±0.30
±3.0
160
Design
Limit
(Note 5)
",A
139
142
",A
",A
",A
3.0
",A
",A
+0.30
+0.5
",AI'F
+3.0
+5.0
'F
±0.16
92
'F
Nole 1: Unless olhelWise noted, these specifications apply: -SO"F " TJ " + 300"F for Ihe LM34 and LM34A; -40"F " Tj " + 230"F for Ihe LM34C and
LM34CA; and +32"F "Tj " + 212"Fforlhe LM34D. Vs = +S Vdc and ILOAD = SO I'A in the circuijof Figure2; +6 Vdc for LM34 and LM34A for 230"F" Tj "
300"F. These specfficalions also apply from + S"F to TMAX in Ihe circuij of Figure I.
Nole 2: Thermal resistance of Ihe TO·46 package is 292"F IW junction to ambient and 43"FIW Junction to case. Thermal resislance of Ihe TO-92 package is
324"F/W junclion to ambient.
Nole 3: Regulation is measured al con slant junction lemperature using pulse lesting wilh a low duty cycle. Changes in output due to heating effects can be
computed by multiplying the internal dissipation by the thermal resistance.
Nole 4: Tested limits are guaranteed and 100% tested in production.
Note 5: Design limits are guaranteed (but not 100% production tested) over the indicated lemperature and supply voltage ranges. These limits are not used 10
calculate outgoing quality levels.
Nole 6: Specification in BOLDFACE TYPE apply over the full rated temperalure range.
Note 7: Accuracy is defined as the Brror between the output voltage and 10 mVJOF times the device's case temperature at specified conditions of voltage, current.
and temperature (expressed in oF).
Nole 8: Nonlinearity is defined as Ihe deviation of the output·voltage-versus·temperature curve Jrom the best-fit straight line over the device's rated lemperature
range.
Nole 9: Quiescent current is defined in the circuit of Figure I.
Nole 10: Contact factory for availability of LM34CAZ.
**
Nole 11: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when
operating Ihe device beyond ils rated operating conditions (see Nole 1).
9-24
Another example is the application hint for the LF156 family:
"Exceeding the negative common-mode limit on either input
will cause a reversal of the phase to output and force the
amplifier output to the corresponding high or low state. Exceeding the negative common-mode limit on both inputs will
force the amplifier output to a high state. In neither case
does a latch occur, since raising the input back within the
common-mode range again puts the input stage and, thus
the amplifier, in a normal operating mode."
A Point-By-Point Look
Let's look a little more closely at the data sheet of the National Semiconductor LM34, which happens to be a temperature sensor.
Note 1 lists the nominal test conditions and test circuits in
which all the characteristics are defined. Some additional
test conditions are listed in the column "Conditions", but
Note 1 helps minimize the clutter.
Note 2 gives the thermal impedance, (which may also be
shown in a chart or table).
That's the kind of information a manufacturer should really
give to a data-sheet reader because no one could ever
guess it.
Note 3 warns that an output impedance test, if done with a
long pulse, could cause significant self-heating and thus,
error.
Sometimes, a writer slips a quirk into a characteristic curve,
but it's wiser to draw attention to it with a line of text. This is
because it's better to make the user sad before one gets
started, rather than when one goes into production. Conversely, if a user is going to spend more than 10 minutes
using a new product, one ought to spend a full five minutes
reading the entire data sheet.
Note 6 is intended to show which specs apply at all rated
temperatures.
Note 7 is the definition of the "Accuracy" spec, and Note 8
the definition for non-linearity. Note 9 states in what test
circuit the quiescent current is defined. Note 10 indicates
that one model of the family may not be available at the time
of printing (but happens to be available now), and Note 11 is
the definition of Absolute Max Ratings.
FINE PRINT
What other fine print can be found on a data sheet? Sometimes the front page may be marked "advance" or "preliminary." Then on the back page, the fine print may say something such as:
"This data sheet contains preliminary limits and design
specifications. Supplemental information will be published
at a later date. The manufacturer reserves the right to make
changes in the products contained in this document in order
to improve design or performance and to supply the best
possible products. We also assume no responsibility for the
use of any circuits described herein, convey no license under any patent or other right and make no representation
that the circuits are free from patent infringement."
In fact, after a device is released to the marketplace in a
preliminary status, the engineers love to make small improvements and upgrades in specifications and characteristics, and hate to degrade a specification from its first published value-but occasionally that is necessary.
Another item in the fine print is the manufacturer's telephone number. Usually it is best to refer questions to the
local sales representative or field-applications engineer, because they may know the answer or they may be best able
to put a questioner in touch with the right person at the
factory.
Occasionally, the factory's applications engineers have all
the information. Other times, they have to bring in product
engineers, test engineers or marketing people. And sometimes the answer can't be generated quickly-data have to
be gathered, opinions solidified or policies formulated before the manufacturer can answer the question. Still, the
telephone number is the key to getting the factory to help.
•. Note-the "4 seconds" soldering time is a new standard
for plastic packages.
•• Note-the wording of Note 11 has been revised-this is
the best wording we can devise, and we will use it on all
future datasheets.
APPLICATIONS
Another important part of the data sheet is the applications
section. It indicates the novel and conventional ways to use
a device. Sometimes these applications are just little ideas
to tweak a reader's mind. After looking at a couple of applications, one can invent other ideas that are useful. Some
applications may be of no real interest or use.
In other cases, an application circuit may be the complete
definition of the system's performance; it can be the test
circuit in which the specification limits are defined, tested
and guaranteed. But, in all other instances, the performance
of a typical application circuit is not guaranteed, it is only
typical. In many circumstances, the performance may depend on external components and their precision and
matching. Some manufacturers have added a phrase to
their data sheets:
"Applications for any circuits contained in this document are
for illustration purposes only and the manufacturer makes
no representation or warranty that such applications will be
suitable for the use indicated without further testing or modification."
In the future, manufacturers may find it necessary to add
disclaimers of this kind to avoid disappointing users with
circuits that work well, much of the time, but cannot be easily guaranteed.
ORIGINS OF DATA SHEETS
Of course, historically, most data sheets for a class of products have been closely modeled on the data sheet of the
forerunner of that class. The first data sheet was copied to
make new versions.
The applications section is also a good place to look for
advice on quirks-potential drawbacks or little details that
may not be so little when a user wants to know if a device
will actually deliver the expected performance.
For example, if a buffer can drive heavy loads and can handle fast signals cleanly (at no load), the maker isn't doing
anybody any favors if there is no mention that the distortion
goes sky-high if the rated load is applied.
That's the way it happened with the UA709 (the first monolithic op amp) and all its copies, as well as many other similar families of circuits.
9-25
»
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Even today, an attempt is made to build on the good things
learned from the past and add a few improvements when
necessary. But, it's important to have real improvements,
not just change for the sake of change.
So, while it's not easy to get the format and everything in it
exactly right to please everybody, new data sheets are continually surfacing with new features, applications ideas,
specifications and aids for the user. And, if the users complain loudly enough about misleading or inadequate data
sheets, they can help lead the way to change data sheets.
That's how many of today's improvements came aboutthrough customer demand.
WHEN TO WRITE DATA SHEETS
A new product becomes available. The applications engineers start evaluating their application circuits and the test
engineers examine their production test equipment.
But how can the users evaluate the new device? They have
to have a data sheet-which is still in the process of being
written. Every week, as the data sheet writer tries to polish
and refine the incipient data sheet, other engineers are reporting, "These spec limits and conditions have to be revised," and, "Those application circuits don't work like we
thought they would; we'll have one running in a couple of
days." The marketing people insist that the data sheet must
be finalized and frozen right away so that they can start
printing copies to go out with evaluation samples.
Who writes data sheets? In some cases, a marketing person does the actual writing and engineers do the checking.
In other companies, the engineer writes, while marketing
people and other engineers check. Sometimes, a committee seems to be doing the writing. None of these ways is
necessarily wrong.
For example, one approach might be: The original designer
of the product writes the data sheet (inside his head) at the
same time the product is designed. The concept here is, if
one can't find the proper ingredients for a data sheet-good
applications, convenient features for the user and nicely
tested specifications as the part is being designed-then
maybe it's not a very good product until all those ingredients
are completed. Thus, the collection of raw materials for a
good data sheet is an integral part of the deSign of a product. The actual assembly of these materials is an art which
can take place later.
These trying conditions may explain why data sheets always
seem to have been thrown together under panic conditions
and why they have so many rough spots. Users should be
aware of the conflicting requirements: Getting a data sheet
"as completely as possible" and "as accurately as possible" is compromised if one wants to get the data sheet "as
quickly as possible."
The reader should always question the manufacturer. What
are the alternatives? By not asking the right question, a misunderstanding could arise; getting angry with the manufacturer is not to anyone's advantage.
Robert Pease has been staff scientist at National Semiconductor Corp., santa Clara, Calif., for eleven years. He has
designed numerous op amps, data converters, voltage regulators and analog-circuit functions.
9-26
»
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Appendix G
Obsolete Product Replacement Guide
C-
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CD
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Some device types, individual temperature grades and package options have been discontinued. This guide is provided to help
design engineers select and specify an appropriate alternative.
c..
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g,
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NSC Part Number
Replacement
Note
NSC Part Number
Replacement
Note
ADB1200
DAC1200/1201
lF352
lF13300
lHOO01
lHOO05/lHOO05A
lH0037
lH0132
lH2011
lH21 08
lH2201A
lH2208
lH2208A
lH2308
lH24250
lM170/270/370
lM171/271 1371
lM172/272/372
lM173/273/373
lM174/274/374
lM175/275/375
lM216/316
lM388N·2/N·3
lM377N
lM378N
lM379
lM1014
lM1017
lM1019
ADC3711
DAC1265
lM3631
ADC3711
lM4250
lHOO03
lH0036
lH0032
lM11
lM108
lM201A
lM208
lM208A
lM308
lM11
lM13600N
no replacement
no replacement
no replacement
no replacement
no replacement
lM11
lM388N·1
lM2877P
lM2878P
lM2879T
no replacement
no replacement
no replacement
2
2
2
2
2
2
3
2
2
2
2
2
2
2
2
2
lM1821S
lM1822
lM1828
lM1848
lM1877N·11N·2/N·3
lM2003
lM2808
lM2831
lM3011
lM3064
lM3075
TBA120V
TBA440C
TBA51 0
TBA530
TBA540
TBA560C
TBA920
TBA950·2
TBA970
TBA990
TDA440
TDA2522/23
TDA2530
TDA2530/31
TDA2540/41
TDA2560
TDA2590
TDA3500
lM1823
lM1823
no replacement
no replacement
lM1877N·9
no replacement
no replacement
lM1851
no replacement
no replacement
no replacement
no replacement
lM1823
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
2
3
2
2
3
3
3
Nole 1: IMPROVED REPLACEMENT: Pin for Pin replacement wHh superior electrical specilicalions.
Nole 2: FUNCTIONAL REPLACEMENT: Consult datesheet to detelmine suitability of the replacement for specific application.
Nole 3: SIMILAR DEVICE with superior performance: Consult datesheet to demlmine suitability of the replacement for specific application.
9·27
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~ Semiconductor
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Appendix H
Products Not Recommended for New Designs
.2
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The popular National Semiconductor Corporation monolithic IC's may have been designed into your systems. We believe that
there are more cost-effective circuits manufactured by National Semiconductor Corporation that should be considered in your
new designs. These recommendations are listed in this section. To eliminate the necessity to redesign proven equipment, we
are continuing to make these products for use in existing designs for which they were uniquely suitable.
o
1:)
::::II
NSC Part Number
Recommended
Replacement
LH221 0
LH2301A
LH2308A
LH231 0
LM103
LM113
LM313
LM377N
LM377N
LM378N
LM391N-60
LM391N-80
LM709
LM710
LM725
LM748
LM210
LM301A
LM308A
LM310
LM185
LM1851-2
LM3851-2
LM1877N-9
LM2877P
LM2878P
LM391N-100
LM391N-100
LF441
LM106
LM607
LF441
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Note
2
2
2
2
3
1
1
2
3
3
1
1
3
2
3
3
Notes:
Note 1: IMPROVED REPLACEMENT: Pin for Pin replacement with superior electrical specifications.
Note 2: FUNCTIONAL REPLACEMENT: Consult datasheet to determine suitability of the replacement for specific application.
Note 3: SIMILAR DEVICE with superior performance: Consult datasheet to determine suitability of the replacement for specific application.
9-28
"U
NatiOnal
~ Semiconductor
All dimensions are in inches (millimeters)
Corporation
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0.005
(0.121)
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(1 210 '0121) TVP - ' -
~
f-:-
(4.512)
MAX
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R=:,4:~
1...1
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0.290-0.320
(1.366-8.12S)
0.015-0.023
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0.020-0.060
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0.100 '0.010
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(0.100/(2.540) sse
TVP REL TO LEADS
1 AND 16)
0.125-0.200
0.150
(3.115-5.0S0)
(3.810)
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(1.620,0.254)
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(2.540) TVP
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9-29
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0.100 ±0.010
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9-30
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0.620
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0.090
(2.286)
MAX
0.010-0.040
(0.254-1.016)
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0.030
0.250-0.350
(6.350-8.890)
(0.782)
MIN
PIN NO.1
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(6.350-8.890)
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0.003-0.008
(0.076-0.152)
0.360-0.420
(9.144-10.67)
-11..0.005
(0.127)
MIN
All ENDS
L
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0.015-0.019
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-11- (0.406
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9-32
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9-42
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•
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This bookshelf is a compilation of books that are currently available. The listing that follows shows the publication year and
section contents for each book.
Please contact your local National sales office for possible complimentary copies. A listing of sales offices follows this
bookshelf.
We are interested in your comments on our technical literature and your suggestions for improvement.
Please send them to:
Technical Communications Dept. M/S 23-200
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090
For a recorded update of this listing plus ordering information for these books from National's Literature Distribution operation,
please call (408) 749-7378.
ALS/AS LOGIC DATABOOK-1987
Introduction to Bipolar logic • Advanced low Power Schottky. Advanced Schottky
ASIC DESIGN MANUAL/GATE ARRAYS & STANDARD CELLS-1987
SSI/MSI Functions. Peripheral Functions. lSllVlSI Functions. Design Guidelines. Packaging
DATA CONVERSION/ACQUISITION DATABOOK-1984
Selection Guides. Active Filters. Amplifiers. Analog Switches. Analog-to-Digital Converters
Analog-to-Digital Display (DVM) • Digital-to-Analog Converters • Sample and Hold. Sensors/Transducers
Successive Approximation Registers/Comparators. Voltage References
HYBRID PRODUCTS DATABOOK-1982
Operational Amplifiers. Buffers. Instrumentation Amplifiers. Sample & Hold Amplifiers • Comparators
Non-Linear Functions. Precision Voltage Regulators and References. Analog Switches
MOS Clock Drivers. Digital Drivers. A-D Converters. D-A Converters • Fiber-Optic Products
Active Filters & Telecommunication Products. Precision Networks • 883/RETS
INTERFACE DATABOOK-1986
Transmission Line Drivers/Receivers. Bus Transceivers. Peripheral/Power Drivers. Display Controllers/Drivers
Memory Support • Microprocessor Support • level Translators/Buffers • Frequency Synthesis
INTERFACE/BIPOLAR LSI/BIPOLAR MEMORY/PROGRAMMABLE LOGIC
DATABOOK-1983
Transmission Line Drivers/Receivers. Bus Transceivers. Peripheral/Power Drivers
level Translators/Buffers. Display Controllers/Drivers. Memory Support. Dynamic Memory Support
Microprocessor Support. Data Communications Support. Disk Support. Frequency Synthesis
Interface Appendices. Bipolar PROMs. Bipolar and ECl RAMs. 2900 Family/Bipolar Microprocessor
Programmable logic
INTUITIVE IC CMOS EVOLUTION-1984
Thomas M. Frederiksen's new book targets some of the most significant transitions in semiconductor technology since the
change from germanium to silicon. Intuitive IC CMOS Evolution highlights the transition in the reduction in defect densities and
the development of new circuit topologies. The author's latest book is a vital aid to engineers, and industry observers who need
to stay abreast of the semiconductor industry.
INTUITIVE IC OP AMPS-1984
Thomas M. Frederiksen's new book, Intuitive Ie Op Amps, explores the many uses and applications of different IC op amps.
Frederiksen's detailed book differs from others in the way he focuses on the intuitive groundwork in the basic functioning
concepts of the op amp. Mr. Frederiksen's latest book is a vital aid to engineers, designers, and industry observers who need to
stay abreast of the computer industry.
LINEAR APPLICATIONS HANDBOOK-1986
The purpose of this handbook is to provide a fully indexed and cross-referenced collection of linear integrated circuit
applications using both monolithic and hybrid circuits from National Semiconductor.
Individual application notes are normally written to explain the operation and use of one particular device or to detail various
methods of accomplishing a given function. The organization of this handbook takes advantage of this innate coherence by
keeping each application note intact, arranging them in numerical order, and providing a detailed Subject Index.
LINEAR 1 DATABOOK-1988
Voltage Regulators. Operational Amplifiers. Buffers. Voltage Comparators. Instrumentation Amplifiers. Surface Mount
LINEAR 3 DATABOOK-1988
AudiO Circuits. Radio Circuits. Video Circuits. Motion Control. Special Functions. Surface Mount
LINEAR SUPPLEMENT DATABOOK-1984
Amplifiers. Comparators • Voltage Regulators • Voltage References • Converters. Analog Switches
Sample and Hold. Sensors • Filters. Building Blocks. Motor Controllers. Consumer Circuits
Telecommunications Circuits. Speech. Special Analog Functions
LOGIC DATABOOK VOLUME 1-1984
CMOS AC Switching Test Circuits and Timing Waveforms. CMOS Application Notes. MM54HC/MM74HC
MM54HCT/MM74HCT. CD4XXX. MM54CXXX/MM74CXXX. lSllVlSI
LS/S/TTL DATABOOK-1987
Introduction to Bipolar logic. low Power Schottky. Schottky. TTL. low Power
MASS STORAGE HANDBOOK-1986
Disk Interface Design Guide and User Manual • Winchester Disk Support. Winchester Disk Data Controller
Floppy Disk Support. Drive Interface Support Circuits
MEMORY SUPPORT HANDBOOK-1986
Dynamic Memory Control· Error Checking and Correction· Microprocessor Interface and Applications
Memory Drivers and Support
MICROCOMMUNICATION ELEMENTS DATABOOK-1987
CPU • Peripherals. Evaluation Board • logic Devices
NON-VOLATILE MEMORY DATABOOK-1987
CMOS EPROMs • EEPROMs • Bipolar PROMs
SERIES 32000 DATABOOK-1986
Introduction. CPU-Central Processing Unit. Slave Processors. Peripherals. Data Communications and LAN's
Disk Control and Interface. DRAM Interface. Development Tools. Software Support. Application Notes
RANDOM ACCESS MEMORY DATABOOK-1987
Static RAMs. TTL RAMs • TTL FIFOs • ECl RAMs
RELIABILITY HANDBOOK-1986
Reliability and the Die • Internal Construction. Finished Package. MIL-STD-883. MIL-M-38510
The Specification Development Process. Reliability and the Hybrid Device. VLSIIVHSIC Devices
Radiation Environment. Electrostatic Discharge • Discrete Device. Standardization
Quality Assurance and Reliability Engineering. Reliability and Documentation. Commercial Grade Device
European Reliability Programs. Reliability and the Cost of Semiconductor Ownership
Reliability Testing at National Semiconductor. The Total Militaryl Aerospace Standardization Program
883B/RETSTM Products. MILS/RETSTM Products. 883/RETSTM Hybrids. MIL-M-3851 0 Class B Products
Radiation Hardened Technology. Wafer Fabrication. Semiconductor Assembly and Packaging
Semiconductor Packages. Glossary of Terms. Key Government Agencies. ANI Numbers and Acronyms
Bibliography. MIL-M-3851 0 and DESC Drawing Cross Listing
TELECOMMUNICATIONS-1987
Line Card Components • Integrated Services Digital Network Components. Modems
Analog Telephone Components. Application Notes
THE SWITCHED-CAPACITOR FILTER HANDBOOK-1985
Introduction to Filters. National's Switched-Capacitor Filters. Designing with Switched-Capacitor Filters
Application Circuits. Filter Design Program. Nomographs and Tables
TRANSISTOR DATABOOK-1982
NPN Transistors. PNP Transistors. Junction Field Effect Transistors. Selection Guides. Pro Electron Series
Consumer Series. NAINB/NR Series. Process Characteristics Double-Diffused Epitaxial Transistors
Process Characteristics Power Transistors. Process Characteristics JFETs. JFET Applications Notes
VOLTAGE REGULATOR HANDBOOK-1982
Product Selection Procedures. Heat Flow & Thermal Resistance. Selection of Commercial Heat Sink
Custom Heat Sink Design. Applications Circuits and Descriptive Information. Power Supply Design
Data Sheets
48-SERIES MICROPROCESSOR HANDBOOK-1980
The 48-Series Microcomputers. The 48-Series Single-Chip System. The 48-Series Instruction Set
Expanding the 48-Series Microcomputers. Applications for the 48-Series • Development Support
Analog 1/0 Components. Communications Components. Digital 1/0 Components. Memory Components
Peripheral Control Components
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NatiOnal
Semiconductor
Corporation
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