1988_National_Microcontrollers_Databook 1988 National Microcontrollers Databook
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~ National
~
Semiconductor
400069
Rev. 1
A Corporate Dedication to
Quality and Reliability
National Semiconductor is an industry leader in the
manufacture of high quality, high reliability integrated
circuits. We have been the leading proponent of driving down IC defects and extending product lifetimes.
From raw material through product design, manufacturing and shipping, our quality and reliability is second
to none.
We are proud of our success ... it sets a standard for
others to achieve. Yet, our quest for perfection is ongoing so that you, our customer, can continue to rely
on National Semiconductor Corporation to produce
high quality products for your design systems.
Charles E. Sporck
President, Chief Executive Officer
National Semiconductor Corporation
Wir flihlen uns zu Qualitat und
Zuverlassigkeit verpflichtet
Un Impegno Societario di Qualita e
Affidabilita
National Semiconductor Corporation ist fUhrend bei der Herstellung von integrierten Schaltungen hoher Qualitat und
hoher Zuverlassigkeit. National Semiconductor war schon
immer Vorreiter, wenn es galt, die Zahl von IC Ausfallen zu
verringern und die Lebensdauern von Produkten zu verbessern. Vom Rohmaterial Ober Entwurf und Herstellung bis zur
Auslieferung, die Qualitat und die Zuverliissigkeit der Produkte von National Semiconductor sind unObertroffen.
National Semiconductor Corporation e un'industria al vertice nella costruzione di circuiti integrati di alta qualM ed
affidabilita. National e stata iI principale promotore per I'abbattimento della difettosita dei circuiti integrati e per I'allungamento della vita dei prodotti. Dal materiale grezzo attraverso tutte Ie fasi di progettazione, costruzione e sped izione, la qualita e affidabilita National non e seconda ~ ne~
sune'.
Wir sind stolz auf unseren Erfolg, der Standards setzt, die
fOr andere erstrebenswert sind. Auch ihre AnsprOche steigen stiindig. Sie als unser Kunde konnen sich auch weiterhin
auf National Semiconductor verlassen.
Noi siamo orgogliosi del nostro successo che fissa per gli
altri un traguardo da raggiungere. II nostro desiderio di perfezione e d'altra parte illimitato e pertanto tu, nostro cliente,
puoi continuare ad affidarti a National Semiconductor Corporation per la produzione dei tuoi sistemi con elevati livelli
di qualita.
La Qualite et La Fiabilite:
Une Vocation Commune Chez National
Semiconductor Corporation
National Semiconductor Corporation est un des leaders industriels qui fabrique des circuits integres d'une tres grande
qualite et d'une fiabilite exceptionelle. National a ete Ie premier a vouloir faire chuter Ie nombre de circuits integres
detectueux et a augmenter la duree de vie des produits.
Depuis les matieres premieres, en passant par la conception du produit sa fabrication et son expedition, partout la
qualite et la fiabilite chez National sont sans equivalents.
Nous sommes fiers de notre succes et Ie standard ainsi
detini devrait devenir I'objectif a atteindre par les autres societes. Et nous continuons a vouloir faire progresser notre
recherche de la perfection; iI en resulte que vous, qui ~tes
notre client, pouvez toujours faire confiance a National
Semiconductor Corporation, en. produisant des systemes
d'une tres grande qualite standard.
Charles E. Sporck
President, Chief Executive Officer
National Semiconductor Corporation
MICROCONTROLLER
DATABOOK
1988 Edition
COP400 Family
COP800 Family
COPS Applications
HPCTM Family
HPC Applications
MICROWIRETM and MICROWIRE/PLUSTM
Peripherals
Display/Terminal Management
Processor (TMP)
Microcontroller Development Support
Appendices/Physical Dimensions
iii
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TRADEMARKS
Following is the most current list of National Semiconductor Corporation's trademarks and registered trademarks.
Abuseable™
AnadigTM
ANS-R-TRANTM
APPSTM
Auto-Chem DeflasherTM
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BI-FETTM
BI-FET IITM
BI-LiNETM
BIPLANTM
BLCTM
BLXTM
Brite-Lite™
BTLTM
CheckTrackTM
CIMTM
CIMBUSTM
Cloc~ChekTM
COMBOTM
COMBO ITM
COMBO IITM
COPSTM microcontrollers
Datachecker®
DENSPAKTM
DIBTM
Digitalker®
DISCERNTM
DISTILLTM
DNR®
DPVMTM
ELSTARTM
E-Z-LlNKTM
FACTTM
FASTTM
5-Star Service™
GAL®
GENIXTM
GNXTM
HEX 3000™
HPCTM
ICMTM
INFOCHEXTM
Integral ISETM
IntelisplayTM
ISETM
ISE/06TM
ISE/08TM
ISE/16TM
ISE32TM
KeyScanTM
LMCMOSTM
M2CMOSTM
Macrobus™
MacrocomponentTM
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NURAMTM
OXISSTM
P2CMOSTM
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POSitalker™
Power & ControlTM
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Mea~ChekTM
Microbus™ data bus
MICRO-DACTM
J.Ltalker™
Microtalker™
MICROWIRETM
MICROWIRE/PLUSTM
MOLETM
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883B/RETSTM
883S/RETSTM
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRIDEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions
for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
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device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
National Semiconductor Corporation 2900 Semiconductor Drive, P.O. Box 58090, Santa Clara, California 95052-8090 (408) 721-5000
TWX (910) 339-9240
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied, and National reserves the right, at any time
without notice, to change said circuitry or specifications.
iv
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Microcontroller Introduction
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Practical Solutions to Real Problems
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Microcontrollers have always been driven by customer need
rather than technological capability.
That's why we're including our 8-bit and 16-bit controller
cores in our standard-cell library.
That's why we're scaling our common M2CMOSTM process
for submicron feature sizes, hypermegahertz frequencies,
and unparalleled performance levels.
They were designed to meet specific needs with specific
performance in specific applications with specific cost.
That also meant, however, that your choices were limited to
what was available on the market-which meant possibly
having to compromise your design objectives because you
couldn't get exactly the microcontroller you needed.
That's why we offer you "Hot-Line" applications support
and a 24-hour-a-day digital information service.
That's why we offer you IBM®-PC and DECTM- VAXTMbased development tools and high-level-language (C) compilers
No more.
Now you can get a microcontroller from National that spans
a wide range of system solutions-to go almost anywhere
your design imagination takes you.
And that's why we've committed the full resources of our
company to provide you with the most complete, most reliable, most cost-effective systems solution for all your
needs.
This databook is a reflection of that committment.
Whether you need a low-cost 4-bit workhorse or a 16-bit
30 MHz powerhouse, whether you want % kbyte of ROM or
over 64 kbytes, whether you're building a simple singing
greeting card or a complex telecommunications network, we
have a microcontroller for the job.
With on-board CPU, memory, internal logic, and II0s, National microcontrollers are helping more and more designers lower system costs and shrink system size.
And as technology brings more peripheral functions onto
the chip, including user-programmable memory, fast SRAM,
timers, UARTs, comparators, AID converters, and LAN interfaces, the microcontroller will become the cost-efficient
choice for even such real-time "microprocessor" applications as laser printers, ISDN, and digital signal processing.
That's why National continues to lead the industry in the
development of microcontroller technology.
It will give you an overview of microcontrollers in general
and of National's microcontrollers in particular.
It will help you evaluate your microcontroller options from
both a business perspective and an engineering perspective.
It will help you make reasoned judgements about selecting
the best microcontroller for your needs.
And it will show you what the microcontroller future holds in
store for all of us.
If you'd like more information, or you'd like to find out how to
put a microcontrolier to work in your own application, just
contact your local National Semiconductor Sales Office.
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How to Select a Microcontroller
Microcontrollers have evolved far beyond their origins as
control chips in calculators.
4. Is it supported by a comprehensive family of development
tools that run on standard platforms such as the IBM-PC
and DEC VAX?
Today, microcontrollers can be the perfect solution for simplifying a wide range of designs. And for giving those designs a clear competitive advantage in the marketplace.
5. Is it backed by a dedicated team of professionals who are
available not only to provide expert training for new users,
to get them on-line quickly and efficiently, but also to provide technical guidance for even the most experienced
user?
Whether used for simple logic replacement or as an integral
part of a high performance system, a microcontroller can
reduce system costs, shrink system size, and shorten system design cycles. And yet deliver performance often superior to "traditional" digital solutions.
6. Is it designed for the future, with the capability of on-chip
gate arrays and with the planned implementation of the
controller core as a standard-cell functional block?
Still, all microcontrollers are not created equal. And it's important to consider a number of factors before committing
to a particular device:
If you answered "yes" to all these questions, then you already know that there's only one company with the product
depth and technology capability to provide you with a microcontroller optimized for your specific application.
1. Is the microcontroller optimized for your specific application in terms of speed, performance, features, and cost?
National Semiconductor.
2. Is it code-efficient, and based on a true microcontroller
architecture for the highest performance and efficiency?
3. Is it fabricated in the most advanced CMOS process
technology, and is it fully scalable to maintain its performance edge in the future?
You'll find National Microcontrollers in:
Laser Printers
Disc Controllers
Telecommunications Systems
Keyboards
Airplane Multiplex Systems
Car Radios
Engine Control Systems
Anti-Skid Brake Systems
Armaments
Factory Automation
Medical Equipment
Fuses
Scales
Refrigerators
Security Systems
Garage Door Openers
Camera Aperture Controls
Office Copiers
Cable TV Converters
Televisions
Video Recorders
Solar Heating Controls
Thermostats
Climate Control Systems
Intelligent Toys
Kitchen Timers
vi
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Why Select a National Microcontroller
National has created the most complete selection of 4-, 8-,
and 16-bit microcontrollers of any company in the industry.
Our COP800 family offers low-cost, feature-rich, 8-bit solutions.
Which means that no matter what the specific needs of your
application are, you can find a National microcontroller to
meet them.
And our High Performance microControlier (HPCTM) family
offers the highest performance with the world's fastest 16bit CMOS solution.
Our COP400 family offers the lowest-cost, 4-bit solutions for
timing, counting, and control functions.
Mlcrocontroller Family of Products
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With a full range of performance- and feature-options,
National's micro controller families can be customized
to meet the needs of your specific application.
This unique core approach allows us to offer you a microcontroller with the exact combination of CPU power and
peripheral function you need for your specific application.
So you don't have to compromise your design parameters
by using an inappropriate device, and you don't have to
compromise your cost parameters by paying for performance and features you don't need.
1.0 COMMON FEATURES FOR A CUSTOM FIT
All our microcontrollers are designed to provide not just a
one-time-only solution, but a continuum of solutions to meet
the changing demands of your product and the marketplace.
Our COP400 family, for example, which consists of over 60
devices, is designed with a common instruction set, so you
can migrate from one member of the family to others without having to recode, so you can take efficient advantage of
the application-specific flexibility of the COP400 family's
programmable 110 options.
This core concept also allows us to bring new microcontroller products to market fast and at a lower cost to help you
keep pace with the rapidly changing conditions in your own
market.
And it allows us to implement both the COP800 and the
HPC cores as standard cells, for the highest levels of integration and flexibility in your own proprietary design.
Our COP800 and HPC families, on the other hand, are each
designed around a common CPU core that then can be surrounded by a variety of standard functional building blocks
such as RAM, ROM, user programmable memory, fast
SRAM, DMA, UART, comparator, AID, HDLC, and liD.
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2.0 TRUE MICROCONTROLLER ARCHITECTURE
Our microcontrollers are designed as true controllers, not
modified microprocessors.
technology LSI and VLSI products, including microprocessors, gate arrays, standard cells, telecommunications devices, linear devices and, of course, microcontrollers.
The COP400 family is designed with a two-bus Harvard architecture; the COP800 family with a memory-mapped,
modified Harvard architecture, and the HPC family with a
memory-mapped, von Neumann architecture.
Post-Metal Programming (PMP). This is a new process
technology available from no other semiconductor manufacturer in the world. It offers the fastest, guaranteed prototype
programmed-ROM turn-time in the industry.
All three control-oriented families, however, are optimized
for high code efficiency. Most instructions are only 1 byte
long-yet each can typically execute several functions. This
"function-dense" code provides a substantial increase in
memory efficiency and processing speed.
PMP is a high-energy implantation process that allows microcontroller ROM to be programmed after final metallization.
This is a true innovation, because ROM is usually implemented in the second die layer, with nine or ten other layers
then added on top. And that means the ROM pattern must
be specified early in the production process, and completed
prototype devices won't be available typically for six weeks.
3.0 ADVANCED PROCESS AND PACKAGING
TECHNOLOGIES
National offers you not only the right microcontroller for your
needs, but also the right process technology for your microcontroller.
With PMP, however, dice can be fully manufactured through
metallization and electrical tests (only the passivation layers
need to be added), and held in inventory. Which means
ROM can be programmed late in the production cycle, making prototypes available In only two weeks!
COP400 devices are available in both high-speed NMOS
and low-power CMOS fabrications, while the higher-performance COP800 and HPC families are both fabricated in
National's advanced M2CMOS process.
And production parts can follow in as little as four weeks.
PMP allows you to adapt to fast-changing market conditions
and to take maximum advantage of narrow windows of opportunity.
M2CMOS. This double-metal CMOS process offers significant design advantages. It combines the speed of NMOS,
the ruggedness of bipolar, and the low power consumption
of bulk CMOS to produce fast, dense, highly efficient, highly
scalable devices for a wide variety of integrated-circuit designs.
And shorter production lead times can simplify your inventory control and reduce safety stock by up to 20%, giving you
significant cost reductions.
Currently, Post-Metal Programming is available for selected
members of the COP400 family, and will be expanded to the
COP800 and HPC familes in the near future.
It's for these reasons that M2CMOS has become the standard process technology for all of National's advanced-
viii
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Military versions. All National microcontrollers have CMOS
parts available in the full military temperature range (- 55°C
to + 125°C).
In addition, parts are available that have been certified under MIL-STD-883, Rev. C, the most rigorous non-JAN
screening flow in the electronics industry.
Packaging. One major reason that National micro controllers demonstrate such consistently high levels of reliability is
that we've developed special advanced packaging processes to protect the die.
For example, we've designed a unique leadframe with
"locking holes" that helps block any penetrating moisture
from reaching the die itself.
And the leadframes themselves are made of an unusual
high-strength copper alloy that has a lower thermal resistance (9JA) than typical Alloy 42-leadframes.
We've also employed a unique low-stress, high-purity epoxy
molding compound for our packages, which gives them a
coefficient of expansion that nearly matches that of the
leadframes. As a result, many of our microcontrollers are
also offered in plastic packages for military-temperaturerange operation.
Reliability is built-in at the die level as well. Our M2CMOS
microcontrollers are fabricated on dedicated lines at our
world-class, six-inch wafer-fab facility in Arlington, Texas.
With its Class-1 0 clean rooms and automated-handling system, Arlington has set a standard of reliability equalled by
few other companies in the industry.
And this reliability is available to you in a wide variety of
microcontroller packages, ranging in size from 20 to 84 pins.
Package types include plastic and ceramic DIPs, small outline (S.O.) surface mounts, plastic and ceramic leaded chip
carriers, and pin grid arrays.
Or, you can select the world's most advanced, high-density
packaging option, TapePakTM.
TapePak comines the advantages of an automated tapeand-reel-type delivery system with built-in testing pads for
reliability and a unique plastic package carrier. The result is
a surface-mounted package that can be as small as 1110 the
size of conventional surface mounts, with lead spacings of
20 mils.
4.0 FULL DEVELOPMENT SUPPORT
Even the right microcontroller, of course, is useless without
the right development tool to put that controller to work in
your application.
That's why National offers you a full range of development
support. Ready-to-run evaluation boards. Emulators. Software. Prototyping devices. Training and seminars for beginning and advanced users. Everything you need to take your
design from concept to reality.
And you don't need an expensive development environment
to do it. With our exclusive Microcontroller On-Line Emulator
(MOLETM), a standard IBM PC or DEC VAX becomes a fullfeatured platform.
And with our comprehensive library of pre written routines,
from keyboard scanners to Fast Fourier Transforms, you
can reduce software programming to a minimum. This
"user-friendly" service can help you bring your design to
market quickly and cost-effectively.
5.0 FULL APPLICATIONS SUPPORT
At National, we believe that applications support should be
immediate and "hands-on".
That's why we established the unique Dial-A-Helper program.
With a computer, modem, and telephone, you can tie directly into our Microcontroller Applications Group for fast, direct
assistance in developing your design.
You can leave messages on our electronic bulletin board for
our Applications Engineers, who will respond to you directly.
You can access applications files.
You can download those files for later reference.
Or, if you're having a real problem, you can actually turn the
control of your Microcontroller On-Line Emulator development system over to our engineering staff, who can perform
remote diagnostic routines to locate and eliminate any bugs.
The point is, when you buy a microcontroller from National,
you're buying more than silicon-you're buying the commitment of an entire company of dedicated professionals who
share a single goal: to help you put that silicon to work.
Systems In the Future-Integration Path
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Both "evolutions," however, are leading to the same goal:
the complete "system-on-chip" solution. Already, the glue
logic that ties a microcontroller to its peripheral functions
can be replaced with a gate array. And soon, all three functions (microcontroller "core", logic, and peripherals) will be
available as a single standard-cell functional block.
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The key to achieving this goal, of course, is a common,
advanced, scalable process technology.
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COP800 and HPC cores will not only be available as part of
our standard-cell library, but will also be able to support one
of the broadest range of functional blocks available from
any semiconductor manufacturer-all aligned on the same
set of design rules.
National's microcontrollers were designed to meet two objectives: to adapt to your evolving needs, and to adapt to
evolving technology.
So you can standardize your designs on just one or two core
processors, and, as we introduce new technologies and
functions, you can maintain that design knowledge base
while taking advantage of these new, higher levels of functional integration.
And because National (and only National) gives you the
option of using standard parts or designing your own customized solutions-both supported by common design tools
and a common process-you can create highly competitive,
highly secure, highly optimized solutions in minimal space at
minimal cost in minimal time.
That's why both the COP800 and HPC families are fabricated in our high-performance double-metal CMOS process.
This is a highly scalable technology that can accommodate
die shrinks to submicron feature sizes, increasing performance and cutting power consumption with each step.
And that's the name of the game.
Moreover, because M2CMOS is now the standard process
technology for all new National LSI and VLSI devices, the
x
Table of Contents
Section 1 COP400 Family
COP400...................... ...............................................
ROM'd Devices
COP21 OC/COP211 C Single-Chip CMOS Microcontrollers .........................
COP224C/COP225C/COP226C/COP244C/COP245C Single-Chip 1k and 2k CMOS
Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP41 OC/COP411 C/COP31 OC/COP311 C Single-Chip CMOS Microcontrollers. . . . . .
COP41 OL/COP411 LlCOP31 OLlCOP311 L Single-Chip N-Channel Microcontrollers . . .
COP413L/COP313L Single Chip Microcontrollers ................................
COP413C/COP413CH/COP313C/COP313CH Single-Chip CMOS Microcontrollers...
COP414L/COP314L Single-Chip N-Channel Microcontrollers ......................
COP420/COP421 ICOP422/COP320/COP321 ICOP322 Single-Chip N-Channel
Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP420LlCOP421 L/COP422L1COP320LlCOP321 LlCOP322L Single-Chip NChannel Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP424C/COP425C/COP426C/COP324C/COP325C/COP326CI and COP444CI
COP445C/COP344C/COP345C Single-Chip 1k and 2k CMOS Microcontrollers ....
COP440/COP441 ICOP442/COP340/COP341 ICOP342 Single-Chip N-Channel
Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP444L/COP445L/COP344L/COP345L Single-Chip N-Channel Microcontrollers . . .
ROM less Devices
COP401 L ROMless N-Channel Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP401 L-X13/COP401 L-R 13 ROM less N-Channel Microcontrollers . . . . . . . . . . . . . . . .
COP402/COP402M ROMless N-Channel Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . .
COP404 ROMless N-Channel Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP404C ROM less CMOS Microcontroller ......................................
COP404LSN-5 ROM less N-Channel Microcontroller ..............................
COP420P/COP444CP/COP444LP Piggyback EEPROM Microcontrollers............
Section 2 COP800 Family
COP800C ...................................................................
COP820C/COP821 C/COP822C/COP840C/COP841 C/COP842C/COP620CI
COP621 C/COP622C/COP640C/COP641 C/COP642C Single-Chip microCMOS
Microcontrollers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP820CP-X/COP840CP-X Piggyback EPROM Microcontroller . . . . . . . . . . . . . . . . . . . .
COP8720C/COP8721 C/COP8722C Single-Chip microCMOS Microcontrollers .......
COP888CL Single-Chip microCMOS Microcontroller ..............................
COP888CF Single-Chip microCMOS Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP888CG Single-Chip microCMOS Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 3 COPS Applications
COP Brief 2 Easy Logarithms for COP400 . . . . . . . . . . . . .. . . . . . . . . . .. .. .. . . . . . . . . . ..
COP Brief 4 L-Bus Considerations............. ... ..... .........................
COP Brief 5 Software and Opcode Differences in the COP444L Instruction Set .......
COP Brief 6 RAM Keep-Alive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP Note 1 Analog to Digital Conversion Techniques with COPS Family
Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP Note 4 The COP444L Evaluation Device 444L-EVAL .........................
COP Note 5 Oscillator Characteristics of COPS Microcontrollers . . . . . . . . . . . . . . . . . . . .
COP Note 6 Triac Control Using the COP400 Microcontroller Family.................
COP Note 7 Testing of COPS Chips...... ...... . ... ..... ......... .. .... .........
AB-3 Current Consumption in NMOS COPS Microcontrollers . . . . . . . . . . . . . . . . . . . . . . .
AB-4 Further Information on Testing of COPS Microcontrollers .....................
xi
1-3
1-8
1-20
1-37
1-52
1-70
1-83
1-97
1-112
1-135
1-161
1-181
1-204
1-227
1-241
1-254
1-272
1-279
1-296
1-310
2-3
2-7
2-27
2-36
2-56
2-85
2-116
3-3
3-14
3-15
3-16
3-17
3-49
3-54
3-71
3-79
3-88
3-90
Table of Contents (Continued)
Section 3 COPS Applications (Continued)
AB-6 COPS Interrupts ........................................................ .
AB-15 Protecting Data in the NMC9306/COP494 and NMC9346/COP495 Serial
EEPROMs ................................................................ .
AB-28 COPS Peripheral Chips ................................................. .
AN-326 A Users Guide to COPS Oscillator Operation ............................. .
AN-329 Implementing an 8-bit Buffer in COPS ................................... .
AN-338 Designing with the NMC9306/COP494 a Versatile Simple to Use E2PROM .. .
AN-400 A Study of the Crystal Oscillator for CMOS-COPS ........................ .
AN-401 Selecting Input/Output Options on COPS Microcontrollers ................. .
AN-440 New CMOS Vacuum Fluorescent Drivers Enable Three Chip System to
Provide Intelligent Control of Dot Matrix V.F. Display ........................... .
AN-452 MICROWIRE Serial Interface .......................................... .
AN-453 COPS Based Automobile Instrument Cluster ............................. .
AN-454 Automotive Multiplex Wiring ........................................... .
AN-521 Dual Tone Multiple Frequency (DTMF) ................................. ..
Section 4 HPC Family
HPC Introduction ............................................................ .
HPC16083/HPC26083/HPC36083/HPC46083/HPC16003/HPC260031HPC360031
HPC46003 High-Performance Microcontrollers ................................ .
HPC16164/HPC26164/HPC36164/HPC46164/HPC16104/HPC261041HPC361 041
HPC46104 High-Performance Microcontrollers ................................ .
HPC16400/HPC36400/HPC46400 High-Performance Microcontrollers ............. .
HPC16900/HPC26900/HPC36900/HPC46900 PEARL Port Expander and Re-creation
Logic .................................................................... .
Section 5 HPC Applications
AN-474 HPC MICROWIRE/PLUS Master-Slave Handshaking Protocol ............. .
AN-484 Interfacing Analog Audio Bandwidth Signals to the HPC ................... .
AN-485 Digital Filtering Using the HPC ........................................ ..
AN-486 A Floating Point Package for the HPC ................................... .
AN-487 A Radix 2 FFT Program for the HPC .................................... .
AN-497 Expanding the HPC Address Space .................................... ..
AN-510 Assembly Language Programming for the HPC ........................... .
Section 6 MICROWIRE and MICROWIRE/PLUS Peripherals
MICROWIRE and MICROWIRE/PLUS Peripherals Selection Guide ................ .
COP452L1COP352L Frequency Generator and Counter .......................... .
COP470/COP370 V.F. Display Driver ......................................... ..
COP472-3 Liquid Crystal Display Controller .................................... ..
COP498/COP398 Low Power CMOS RAM and Timer (RATTM) COP499/COP399 Low
Power CMOS Memory ..................................................... .
Section 7 Display/Terminal Management Processor (TMP)
TMP ....................................................................... .
NS405 Series Display Terminal Management Processor (TMP) .................... .
AB-14 Throughput Considerations in NS405 System Planning ..................... .
AB-16 NS405-Series TMP External Interrupt Processing .......................... .
AN-354 TMP Rowand Attribute Table Lookup Operation ......................... .
AN-355 TMP-Dynamic RAM Interfacing ......................................... .
AN-367 TM P External Character Generation .................................... .
AN-369 NS405 TMP Logic Analyzer ............................................ .
AN-374 Building an Inexpensive But Powerful Color Terminal ...................... .
AN-399 TM P Extended Program Memory ....................................... .
xii
3-92
3-93
3-95
3-97
3-101
3-105
3-111
3-115
3-125
3-135
3-146
3-151
3-155
4-3
4-5
4-35
4-67
4-89
5-3
5-11
5-21
5-36
5-89
5-114
5-125
6-3
6-7
6-37
6-44
6-52
7-3
7-4
7-43
7-44
7-46
7-53
7-58
7-61
7-68
7-73
Table of Contents (Continued)
Section 8 Mlcrocontroller Development Tools
Mole........................................................................
AN-456 Microcontroller Development Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPC Software Support Package................................................
Section 9 Appendices/Physical Dimensions
Industry Package Cross Reference .............................................
Surface Mount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLCC Packaging .............................................................
TapePak Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Bookshelf
Authorized Distributors
xiii
8-3
8-4
8-17
9-3
9-5
9-7
9-11
9-12
Alpha-Numeric Index
AB-3 Current Consumption in NMOS COPS Microcontrollers ................................... 3-88
AB-4 Further Information on Testing of COPS Microcontrollers ................................. 3-90
AB-6 COPS Interrupts ..................................................................... 3-92
AB-14 Throughput Considerations in NS405 System Planning .................................. 7-43
AB-15 Protecting Data in the NMC9306/COP494 and NMC9346/COP495 Serial EEPROMs ....... 3-93
AB-16 NS405-Series TMP External Interrupt Processing ....................................... 7-44
AB-28 COPS Peripheral Chips .............................................................. 3-95
AN-326 A Users Guide to COPS Oscillator Operation .......................................... 3-97
AN-329 Implementing an 8-bit Buffer in COPS ............................................... 3-101
AN-338 Designing with the NMC9306/COP494 a Versatile Simple to Use E2PROM .............. 3-105
AN-354 TMP Rowand Attribute Table Lookup Operation ...................................... 7-46
AN-355 TMP-Dynamic RAM Interfacing ..................................................... 7-53
AN-367 TMP External Character Generation ................................................. 7-58
AN-369 NS405 TMP Logic Analyzer ......................................................... 7-61
AN-374 Building an Inexpensive But Powerful Color Terminal ................................... 7-68
AN-399 TMP Extended Program Memory .................................................... 7-73
AN-400 A Study of the Crystal Oscillator for CMOS-COPS .................................... 3-111
AN-401 Selecting Input/Output Options on COPS Microcontrollers ............................ 3-115
AN-440 New CMOS Vacuum Fluorescent Drivers Enable Three Chip System to Provide Intelligent Control
of Dot Matrix V.F. Display ............................................................... 3-125
AN-452 MICROWIRE Serial Interface ...................................................... 3-135
AN-453 COPS Based Automobile Instrument Cluster ......................................... 3-146
AN-454 Automotive Multiplex Wiring ....................................................... 3-151
AN-456 Microcontroller Development Support ................................................. 8-4
AN-474 HPC MICROWIRE/PLUS Master-Slave Handshaking Protocol ........................... 5-3
AN-484 Interfacing Analog Audio Bandwidth Signals to the HPC ................................ 5-11
AN-485 Digital Filtering Using the HPC ...................................................... 5-21
AN-486 A Floating Point Package for the HPC ................................................ 5-36
AN-487 A Radix 2 FFT Program for the HPC ................................................. 5-89
AN-497 Expanding the HPC Address Space ................................................ 5-114
AN-510 Assembly Language Programming for the H PC ....................................... 5-125
AN-521 Dual Tone Multiple Frequency (DTMF) .............................................. 3-155
COP Brief 2 Easy Logarithms for COP400 ..................................................... 3-3
COP Brief 4 L-Bus Considerations .......................................................... 3-14
COP Brief 5 Software and Opcode Differences in the COP444L Instruction Set ................... 3-15
COP Brief 6 RAM Keep-Alive ............................................................... 3-16
COP Note 1 Analog to Digital Conversion Techniques with COPS Family Microcontrollers .......... 3-17
COP Note 4 The COP444L Evaluation Device 444L-EVAL ..................................... 3-49
COP Note 5 Oscillator Characteristics of COPS Microcontrollers ................................ 3-54
COP Note 6 Triac Control Using the COP400 Microcontroller Family ............................. 3-71
COP Note 7 Testing of COPS Chips ......................................................... 3-79
COP210C Single-Chip CMOS Microcontroller ................................................. 1-8
COP211 C Single-Chip CMOS Microcontroller ................................................. 1-8
COP224C Single-Chip CMOS Microcontroller ................................................ 1-20
COP225C Single-Chip CMOS Microcontroller ................................................ 1-20
COP226C Single-Chip CMOS Microcontroller ................................................ 1-20
COP244C Single-Chip CMOS Microcontroller ................................................ 1-20
COP245C Single-Chip CMOS Microcontroller ................................................ 1-20
COP31 OC Single-Chip CMOS Microcontroller ................................................ 1-37
COP310L Single-Chip N-Channel Microcontroller ............................................. 1-52
COP311 C Single-Chip CMOS Microcontroller ................................................ 1-37
xiv
Alpha-Numeric
Index(continUed)
COP311 L Single-Chip N-Channel Microcontroller , , , , , . , ............. , , .. , .. , .. , .. , , .. , .. , , .. , 1-52
COP313C Single-Chip CMOS Microcontroller ., ... , .......... " .. , .... , .... , .. , .. , .. , , , , , , , .. 1-83
COP313CH Single-Chip CMOS Microcontroller , .. " .. " .. , " " , .... ,', .. , ........ " .. ,""'" 1-83
COP313L Single Chip Microcontroller ............ , .. , ........ , .... , .. , , ........... , .. , .. , , .. 1-70
COP314L Single-Chip N-Channel Microcontroller " ........ " .. " .... , .... , .. , ........ ,', .. ," 1-97
COP320 Single-Chip N-Channel Microcontroller • , , , , , , , , , , , , , . , . , , , , , , , , , , , , . , , , . , , , , , , , , , , , 1-112
COP320L Single-Chip N-Channel Microcontroller , , , , , , , , , , , , , .. , , , , , , , , , , . , . , , , , . , , , , , , , , , , , 1-135
COP321 Single-Chip N-Channel Microcontroller ... , .. , .. , .... , , .... , , , .. , ..... , .. , , .. , , , , ... 1-112
COP321 L Single-Chip N-Channel Microcontroller , , , , . , , , , , , , , , , , , , , , , , , , , , , , , , , , . , , , , , , , , , , . 1-135
COP322 Single-Chip N-Channel Microcontroller .,",.,',.,""',.,""".,.,'" ... , ... ,"',. 1-112
COP322L Single-Chip N-Channel Microcontroller , , , , , , , , , , , , , , , , , , , , , , , , , , . , , , , , , . , , , , , , , , , , 1-135
COP324C Single-Chip CMOS Microcontroller , , . , , , , . , , , , , , , , . , , . , , , , , , , . , . , , . , , , . , , . , , , , , , , 1-161
COP325C Single-Chip CMOS Microcontroller , ................ , , .. , .. , , ...... , , ...... , , , .. , , 1-161
COP326C Single-Chip CMOS Microcontroller , .... , , .. , , ...... , , .. , , , , , .. , .. , ........ , , , .. , , 1-161
COP340 Single-Chip N-Channel Microcontroller . , , , , , . , , , , , , , . , , . , , . , , , , , . , , . , , , ... , . , .. , ... 1-181
COP341 Single-Chip N-Channel Microcontroller , .. , , , .... , , , .......... , .. , .. , ........ , , , .. , , 1-181
COP342 Single-Chip N-Channel Microcontroller ... , .. , , .... , , ........... , ........ , , .. , .. , .. , 1-181
COP344C Single-Chip CMOS Microcontroller , .... , , , , , .... , , .. , .... , ....... , .......... , .. , , 1-161
COP344L Single-Chip N-Channel Microcontroller , , , , , , , , , , , , , , . , , . , , , , , , , . , , , , , , . , , , , , , , , , ., 1-204
COP345C Single-Chip CMOS Microcontroller , , ... , .......... , .......... , .. , .. , .. , , .. , .. , .. , 1-161
COP345L Single-Chip N-Channel Microcontroller , , , , , , , , , , . , , . , . , , , , , , , , . , . , , , , , . , , , , , , , , , , . 1-204
COP352L Frequency Generator and Counter, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , " , , , , , , , , , , , , , , , 6-7
COP370 V,F. Display Driver"",,""",.,"""""",.,.,.,""",.,""'" ,.,"',.",.,,6-37
COP398 Low Power CMOS RAM and Timer (RATTM) " .. ,', .... " .. " ....... , ......... , .. " .. 6-52
COP399 Low Power CMOS Memory " , , .. , , , , , , , , , , , , , , , , , .. , , , , , , , , , , , , . , , , , , , , , , , , , , . , , , . 6-52
COP400",.,""""""""""', .. ,.,'" ""',.,.,.,.,"""",.,"',.,""""""",,1-3
COP401 L ROM less N-Channel Microcontroller , . , , , , , , , , , , , , , . , , , , , , . , , , , , , , , , , , , . , , , , , , , . , , 1-227
COP401 L-R13 ROMless N-Channel Microcontroller " " " " ' , . , " " " " ' , . , " " ' , . , " " " ' " 1-241
COP401 L-X13 ROMless N-Channel Microcontroller , , , , , , , , , , , . , , , , , , , , , , , , , , , , , , , , , , , , , , , , . , 1-241
COP402 ROMless N-Channel Microcontroller , , . , , , , . , , , , , , , .. , , , , , , , , , , , . , , , , , , . , , , , , , , , , . , 1-254
COP402M ROMless N-Channel Microcontroller .,' , , , , . , , , , , .. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 1-254
COP404 ROM less N-Channel Microcontroller , , . , , , , , , , , , , , , , . , , , , , , , , , , , . , , , , , , . , , , , , . , , , .. 1-272
COP404C ROM less CMOS Microcontroller " , , . , , , , , , , , , , , , . , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 1-279
COP404LSN-5 ROM less N-Channel Microcontroller "",.,'".,"',',',',.,"" , . , , , , , , , , , , . 1-296
COP41 OC Single-Chip CMOS Microcontroller " " " " " " " " ' , . , " ' , ' , " " ' , " , , , , , , , . , , , . , , 1-37
COP41 OL Single-Chip N-Channel Microcontroller , , , , , , , , , , , , .. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 1-52
COP411 C Single-Chip CMOS Microcontroller " " " " " ' , ' " .. ,",',,',",",,',.,""""'" 1-37
COP411 L Single-Chip N-Channel Microcontroller , , , , , , , , , , , , .. , , , , , , , , , , , . , , , , , , , , , , , , , , . , , , , 1-52
COP413C Single-Chip CMOS Microcontroller " " " ' , . , ' , " ' , . , " " " " " " " " , . , " " " " ' " 1-83
COP413CH Single-Chip CMOS Microcontroller , , , , , , , , , , , , , , , . , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , . 1-83
COP413L Single Chip Microcontroller .. , .... , , .. , , , , .......... , .. , , , ...... , .. , , , , .. , , , , .. , , , 1-70
COP414L Single-Chip N-Channel Microcontroller , , , , , , , , , , , , , . , , , , , , , , , , , , . , , , , , , , , , , , , , , , . , , 1-97
COP420 Single-Chip N-Channel Microcontroller . , , , , , , , , , , , , , .. , , . , , , , , . , , , , , , , , . , , , , , , , , , , , 1-112
COP420L Single-Chip N-Channel Microcontroller , , , , , , , , , , . , , . , , , . , , , , , , , , , , , , , , . , , , , , , , , , , . 1-135
COP420P Piggyback EEPROM Microcontroller , . , , , , . , , , , , , , , ... , , , , , , , . , , , , , , , , . , , , , , , , , , , , 1-310
COP421 Single-Chip N-Channel Microcontroller .. , , .. , , , , , ......... , , , ........... , .. , , , .. , , , 1-112
COP421 L Single-Chip N-Channel Microcontroller , , , , , , , , , , , , , .. , , , , , , , , , , , , , , , , , , , , , , , , , .. , , 1-135
COP422 Single-Chip N-Channel Microcontroller . , , , , , , , , , , , , , , . , , , , , , , , , , , , , , , , , , . , , , , , , .. , , 1-112
COP422L Single-Chip N-Channel Microcontroller , , , , , , , , , , , , , ... , , , , , , , , , . , , , , , , , , , , , , , , , .. , 1-135
COP424C Single-Chip CMOS Microcontroller , , . , , , , , , , , , , , , , .. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 1-161
COP425C Single-Chip CMOS Microcontroller , .... , , , ...... , ................ , ....... , .. , .. , , 1-161
xv
Alpha-Numeric
Index(continued)
COP426C Single-Chip CMOS Microcontroller ............................................... 1-161
COP440 Single-Chip N-Channel Microcontroller ............................................. 1-181
COP441 Single-Chip N-Channel Microcontroller ............................................. 1-181
COP442 Single-Chip N-Channel Microcontroller ............................................. 1-181
COP444C Single-Chip CMOS Microcontroller ............................................... 1-161
COP444CP Piggyback EEPROM Microcontroller ............................................ 1-310
COP444L Single-Chip N-Channel Microcontroller ............................................ 1-204
COP444LP Piggyback EEPROM Microcontroller ............................................. 1-310
COP445C Single-Chip CMOS Microcontroller ............................................... 1-161
COP445L Single-Chip N-Channel Microcontroller ............................................ 1-204
COP452L Frequency Generator and Counter .................................................. 6-7
COP470 V.F. Display Driver ................................................................ 6-37
COP472-3 Liquid Crystal Display Controller .................................................. 6-44
COP498 Low Power CMOS RAM and Timer (RATTM) ......................................... 6-52
COP499 Low Power CMOS Memory ........................................................ 6-52
COP620C Single-Chip microCMOS Microcontroller ............................................. 2-7
COP621 C Single-Chip microCMOS Microcontroller ............................................. 2-7
COP622C Single-Chip microCMOS Microcontroller ............................................. 2-7
COP640C Single-Chip microCMOS Microcontroller ............................................. 2-7
COP641 C Single-Chip microCMOS Microcontroller ............................................. 2-7
COP642C Single-Chip microCMOS Microcontroller ............................................. 2-7
COP820C Single-Chip microCMOS Microcontroller ............................................. 2-7
COP820CP-X Piggyback EPROM Microcontroller ............................................. 2-27
COP821C Single-Chip microCMOS Microcontroller ..........................•.................. 2-7
COP822C Single-Chip microCMOS Microcontroller .........................•................... 2-7
COP840C Single-Chip microCMOS Microcontroller ............................................. 2-7
COP840CP-X Piggyback EPROM Microcontroller ............................................. 2-27
COP841 C Single-Chip microCMOS Microcontroller ............................................ ; 2-7
COP842C Single-Chip microCMOS Microcontroller ............................................. 2-7
COP888CF Single-Chip microCMOS Microcontroller .......................................... 2-85
COP888CG Single-Chip microCMOS Microcontroller ......................................... 2-116
COP888CL Single-Chip microCMOS Microcontroller .......................................... 2-56
COP8720C Single-Chip microCMOS Microcontroller ..........•............................... 2-36
COP8721C Single-Chip microCMOS Microcontroller ..................•....................... 2-36
COP8722C Single-Chip microCMOS Microcontroller ..................•.•..................... 2-36
HPC Software Support Package ......................................•..................... 8-17
HPC16003 High-Performance Microcontroller .......................•...•..................... 4-5
HPC16083 High-Performance Microcontroller ................................................. 4-5
HPC16104 High-Performance Microcontroller ................................................ 4-35
HPC16164 High-Performance Microcontroller ................................................ 4-35
HPC16400 High-Performance Microcontroller ................................................ 4-67
HPC16900 PEARL Port Expander and Re-creation Logic ...................................... 4-89
HPC26003 High-Performance Microcontroller ................................................. 4-5
HPC26083 High-Performance Microcontroller .....................•........................... 4-5
HPC26104 High-Performance Microcontroller ................................................ 4-35
HPC26164 High-Performance Microcontroller ................................................ 4-35
HPC26900 PEARL Port Expander and Re-creation Logic ...................................... 4-89
HPC36003 High-Performance Microcontroller .............•......................•..•......... 4-5
HPC36083 High-Performance Microcontroller ................................................. 4-5
HPC36104 High-Performance Microcontroller ................................................ 4-35
HPC36164 High-Performance Microcontroller ................................................ 4-35
xvi
Alpha-Numeric
Index(continUed)
HPC36400 High-Performance Microcontroller ................................................ 4-67
HPC36900 PEARL Port Expander and Re-creation Logic ...................................... 4-89
HPC46003 High-Performance Microcontroller ......................................•.......... 4-5
HPC46083 High-Performance Microcontroller ......................................•.......... 4-5
HPC46104 High-Performance Microcontroller ................................................ 4-35
HPC46164 High-Performance Microcontroller ................................................ 4-35
HPC46400 High-Performance Microcontroller ................................................ 4-67
HPC46900 PEARL Port Expander and Re-creation Logic ...................................... 4-89
Mole ..........................................................................•.......... 8-3
NS405 Series Display Terminal Management Processor (TMP) .................................. 7-4
TMP ..................................................................................... 7-3
xvii
Section 1
COP400 Family
Section 1 Contents
COP400...........................................................................
COP21 OC/COP211 C Single-Chip CMOS Microcontrollers ...............................
COP224C/COP225C/COP226C/COP244C/COP245C Single-Chip 1k and 2k CMOS
Microcontrollers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP41 OC/COP411 C/COP31 OC/COP311 C Single-Chip CMOS Microcontrollers ...........
COP41 OL/COP411 L/COP31 OL/COP311 L Single-Chip N-Channel Microcontrollers . . . . . . . . .
COP413L1COP313L Single Chip Microcontrollers ......................................
COP413C/COP413CH/COP313C/COP313CH Single-Chip CMOS Microcontrollers. . . . . . . . .
COP414L/COP314L Single-Chip N-Channel Microcontrollers ......................... . . .
COP420/COP421 ICOP422/COP320/COP321 ICOP322 Single-Chip N-Channel
Microcontrollers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP420L/COP421 L/COP422L1COP320LlCOP321 LlCOP322L Single-Chip N-Channel
Microcontrollers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP424C/COP425C/COP426C/COP324C/COP325C/COP326CI and COP444CI
COP445C/COP344C/COP345C Single-Chip 1k and 2k CMOS Microcontrollers ......... ,
COP440/COP441 ICOP442/COP340/COP341 ICOP342 Single-Chip N-Channel
Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP444L/COP445L/COP344L/COP345L Single-Chip N-Channel Microcontrollers ........ ,
COP401 L ROM less N-Channel Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP401 L-X13/COP401 L-R13 ROMless N-Channel Microcontrollers ..................... ,
COP402/COP402M ROM less N-Channel Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
COP404 ROM less N-Channel Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP404C ROM less CMOS Microcontroller . . . . .. .. .. .. . . .. .. . .. .. . . . . . . . . . . . .. .. .. . .. .
COP404LSN-5 ROMless N-Channel Microcontroller ....................................
COP420P/COP444CP/COP444LP Piggyback EEPROM Microcontrollers ................. ,
1-2
1-3
1-8
1-20
1-37
1-52
1-70
1-83
1-97
1-112
1-135
1-161
1-181
1-204
1-227
1-241
1-254
1-272
1-279
1-296
1-310
....
::r
.
CD
~National
.c:a.
m
D Semiconductor
~
The 4-Bit COP400 Family:
Optimized for Low-Cost Control
National's COP400 family offers the broadest range of lowpriced, 4-bit microcontrollers on the market.
Key Applications
• Consumer electronics
Key Features
• High-performance 4-bit microcontroller
• Automotive
• Industrial control
• 4 ,.,.s-16 ,.,.s instruction-cycle time
• ROM-efficient instruction set
• Toys/games
• Telephones
• On-chip ROM from 0.5k to 2k
Wide Acceptance
• On-chip RAM from 32 x 4 to 160 x 4
COPS wide acceptance comes from innovative products.
National has built on this established family with continued
and enhanced devices.
• More than 60 compatible devices in family
• Common pin-outs
• NMOS and p2CMOSTM
• MICROWIRETM serial interface
• The first under-a-dollar microcontroller led to a broader
range of automotive and consumer applications.
• Wide operating voltage range: + 2.4V to + 9V
• Military temp range available: -55°C to + 125°C
• The first high-speed, low-power CMOS microcontrollers
with 0.5k ROM provides design flexibility at low cost.
• 20- to 28-pin packages
(inc!. 20-, 24-pin SO and 28-pin PLCC)
• The first microcontroller implementing MICROWIRE/
PLUSTM allowing two-way communication across only
three lines.
And far from being "old technology," 4-bit microcontrollers
are meeting significant market needs in more applications
than ever before. In fact, National shipped more than 40
million 4-bit devices last year alone. The reason for the continuing strength of the COP400 family is its versatility. You
can select from over 60 different, compatible devices. You
can select devices with unit costs below 50 cents-the
lowest-priced microcontrollers in the world. You can select
devices with a wide variety of ROM and RAM combinations,
from 0.5k ROM and 32 x 4 RAM to 2k ROM and 160 x 4
RAM.
And every COP400 family member shares the same powerful, ROM-efficient instruction set and the same pin-out, so
you can migrate between devices without re-engineering.
And like all of National's microcontrollers, the COP400 can
be optimized to meet your specific application needs, with a
variety of I/O options, pin-outs, and package types, from
DIPs to SMDs.
• The first under $.50 microcontroller providing excellent
cost/performance benefits for applications impossible
before.
• The first microcontroller implementing Post-Metal Programming (PMPTM) for quick turns prototyping and production.
PMP
Post-Metal Programming (PMP), another NSC microcontroller first. Takes advantage of:
• Seasonal or volatile market demand
• Narrow windows of opportunity in highly competitive markets
• Simplified inventory control
• Reduced safety stock
Get all the advantages of custom-programmed microcontrollers with all the business advantages of low cost, quickturn prototyping and production.
The secret is an entirely new process technology called
Post-Metal Programming.
COPSTM microcontrollers can be used to replace discrete
logic in high-volume consumer products and low-volume industrial products allowing you to add features, miniaturize
and reduce component count.
1-3
~
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I-
PMP
(Continued)
INSIDEPMP
And when you consider the additional cost-savings of being
able to reduce your safety stock in inventory, knowing you
can get quick-turns in a few weeks, the PMP process and
National Semiconductor microcontrollers not only make
good engineering sense, they make good business sense.
Post-Metal Programming is a high energy implantation process that allows the ROM layer of a microcontroller to be
programmed after final metallization. That means every die
layer can be fully fabricated, except for the passivation layers, and held in inventory. Then when you request a ROM
pattern, a ROM implant mask is generated and the buried
ROM layer is programmed with an ion beam.
System Solutions
The COP400 family provides a flexible, cost-effective system solutions to all applications requiring timing, counting,
or control functions.
The wafer is passivated and cut into dice which are then
packaged on a quick-turn line.
And, bottom line, if a 4-bit controller can do the job, why pay
more?
So in only two weeks, you've got prototypes.
4-WEEK PRODUCTION QUANTITIES
Wafer fab accounts for the majority of prototyping and production time for integrated circuits.
Development Support
With PMP, however, the dice are essentially complete and
in inventory.
MOLETM DEVELOPMENT SYSTEM
The MOLE (Microcomputer On-Line Emulator) is a low cost
development system and emulator for all microcontroller
products. These include COPs, and the HPCTM family of
products. The MOLE consists of a BRAIN Board, Personality Board and optional host software.
So we can take your approved prototypes right into full production in as little as four weeks.
WINNING THE TIME"TO-MARKET RACE
The electronics market won't wait for anyone. If your competitors make a move, you've got to respond now.
The purpose of the MOLE is to provide the user with a tool
to write and assemble code, emulate code for the target
microcontroller and assist in both software and hardware
debugging of the system.
You can't wait around for proof-of-design prototypes. Even
a week can make a difference between success or failure.
Between gaining market share or losing it. Between staying
ahead of the other guys or falling behind. With PMP, you
can stretch that lead by weeks. In fact, if you compare the
quick-turn PMP process to conventional prototype-and-production timetables, you'll see that you can actually gain as
much as 3~ months over your competitors!
It is a self contained computer with its own firmware which
provides for all system operation, emulation control, communication, PROM programming and diagnostic operations.
It contains three serial ports to optionally connect to a terminal, a host system, a printer or a modem or to connect to
other MOLEs in a multi-MOLE environment.
NO EXTRA COST
MOLE can be used in either a stand alone mode or in conjunction with a selected host system using PC-DOS communicating via a RS-232 port.
PMP is available at no extra cost.
That means, for example, that National's COP413L, the
world's lowest-priced microcontroller at $.49 in quantity, is
available in the PMP process for ... $.49 in quantity.
See AN-456 for more information.
HOW TO ORDER
Compare that with the traditional "alternative" for quick-turn
prototyping of user-programmable ROM. EPROM and
EEPROM can easily drive your unit costs up to as much as
$6!
Microcontroller
COP400
Order
Part Number
To order a complete development package, select the section for the microcontroller to be developed and order the
parts listed.
Description
Includes
Manual
Number
MOLE-BRAIN
Brain Board
Brain Board Users Manual
420408188-001
MOLE-COPS-PB 1
Personality Board
COP400 Personality Board
Users Manual
420408189-001
MOLE-COPS-IBM
Assembler Software
for IBM
COP400 Software Users
Manual and Software Disk
PC-DOS
Communications Software
Users Manual
424409497-002
424410284-001
Programmers Manual
1-4
420040416-001
424410284-001
COP400 Family of Microcontrollers
Description
Commercial
Industrial
Military
Temp Version Temp Version
Temp Version
IrCto +70·C - 40·C to + 85·C - 55·C to + 125·C
......
0,
Technology
Development Tools
Features
1/0
Memory
RAM 1/0 Serial Interrupt
ROM
(Bytes) (Digits) Pins 1/0
Time
Typ.5V
Max
Size
Micro
Stack
Base
Operat. Standby
(Pins)
Bus
Power at3.3V
Counter
ROM less
Device
Piggyback
Data
Sheet
Page
COP413L·
COP313L
NMOS Low Power
0.5k
32
15
Yes
No
2 Level
No
No
15mW
7.5mW
20
COP414L·
COP410L
COP411L
COP314L
COP310L
COP311L
NMOS Low Power
NMOS Low Power
NMOS Low Power
0.5k
0.5k
0.5k
32
32
32
15
19
16
Yes
Yes
Yes
No
No
No
2 Level
2 Level
2 Level
No
No
No
No
No
No
15mW
15mW
15mW
7.5mW
7.5mW
7.5mW
20
24
20
COP401LX13/R13
COP401LN
COP401LN
COP401LN
COP413C
COP413CH
COP410C
COP411C
COP313C
COP313CH
COP310C
COP311C
CMOS Low Power
CMOS Hi Speed
COP210C (Note 1) CMOS Hi Speed
COP211C (Note 1) CMOS Hi Speed
0.5k
0.5k
0.5k
0.5k
32
32
32
32
15
15
19
16
Yes
Yes
Yes
Yes
No
No
No
No
2 Level
2 Level
2 Level
2 Level
No
No
No
No
No
No
No
No
lmW
lmW
lmW
lmW
0.1 mW
O.lmW
0.1 mW
0.1 mW
20
20
24
20
COP404CN
COP404CN
COP404CN
COP404CN
COP444CP
COP444CP
COP444CP
COP444CP
1-83
1-83
1-37
1-37
COP420
COP421
COP422
COP320'
COP321
COP322
NMOS Hi Speed
NMOS Hi Speed
NMOS Hi Speed
1.0k
1.0k
1.0k
64
64
64
23
19
16
Yes
Yes
Yes
1 Source 3 Level
3 Level
No
3 Level
No
Yes
Yes
Yes
Yes
No
No
100mW N/AmW
100mW N/AmW
100mW N/AmW
28
24
20
COP402N
COP402N
COP402N
COP420P
COP420P
COP420P
1-112
1-112
1-112
COP424C·
COP425C·
COP426C·
COP324C
COP325C
COP326C
COP224C (Note 2) CMOS Hi Speed
COP225C (Note 2) CMOS Hi Speed
COP226C (Note 2) CMOS Hi Speed
1.0k
1.0k
1.0k
64
64
64
23
19
16
Yes
Yes
Yes
1 Source 3 Level
3 Level
No
3 Level
No
Yes
Yes
Yes
Yes
No
No
lmW
lmW
lmW
O.lmW
O.lmW
0.1 mW
28
24
20
COP404CN
COP404CN
COP404CN
COP444CP 1-161
COP444CP 1-161
COP444CP 1-161
COP420L·
COP421L·
COP422L·
COP320L
COP321L
COP322L
NMOS Low Power
NMOS Low Power
NMOS Low Power
1.0k
1.0k
1.0k
64
64
64
23
19
16
Yes
Yes
Yes
1 Source 3 Level
3 Level
No
3 Level
No
Yes
Yes
Yes
Yes
No
No
45mW
45mW
45mW
9.9mW
9.9mW
9.9mW
28
24
20
COP404LSN-5 COP444LP 1-135
COP404LSN-5 CO P444 LP 1-135
COP404LSN-5 COP444LP 1-135
COP440
COP441
COP442
COP340
COP341
COP342
NMOS Hi Speed
NMOS Hi Speed
NMOS Hi Speed
2.0k
2.0k
2.0k
160
160
160
35
23
19
Yes
Yes
Yes
4 Sources 4 Level
4 Sources 4 Level
2 Sources 2 Level
Yes
Yes
Yes
Yes
Yes
No
205mW 9.9mW
205mW 9.9mW
205mW 9.9mW
40
28
24
COP404N
COP404N
COP404N
COP440R
COP440R
COP440R
COP444C·
COP445C·
COP344C
COP345C
COP244C (Note 2) CMOS Hi Speed
COP245C (Note 2) CMOS Hi Speed
2.0k
2.0k
128
128
23
19
Yes
Yes
1 Source 3 Level
3 Level
No
Yes
Yes
Yes
No
lmW
1mW
0.1 mW
0.1 mW
28
24
COP404CN
COP404CN
COP444CP 1-161
COP444CP 1-161
COP444L
COP445L
COP344L
COP345L
2.0k
2.0k
128
128
23
19
Yes
Yes
1 Source 3 Level
3 Level
No
Yes
Yes
No
No
65mW
65mW
9.9mW
9.9mW
28
24
COP404LSN-6 COP444LP 1-204
COP404LSN-6 COP444LP 1-204
NMOS Low Power
NMOS Low Power
1-70
1-97
1·52
1-52
1-181
1-181
1-181
Note 1: Datasheet found on page 1-8.
Note 2: Datasheet found on page 1-20.
'Microcontrollers available with Quick-Turns Prototype Post-Metal Programming (PMP).
AIIWe.:l OOtdO:lIIS-t all!
The 4-Bit COP400 Family
COPS Family Development Tools
Description
Commercial
Temp Version
O"Cto +70·C
Technology
Features
Memory
1/0
ROM
RAM
1/0 Serial
(Bytes) (Digits) Pins
1/0
Interrupt
Stack
Typ.5V
Time
Max
Micro
Size
Operat. Standby (Pins)
Base
Bus
Power
at3.3V
Counter
Supplementary
Description
Data
Sheet
Page
ROM less
COP401 L-X13
COP401 L-R13
COP401L
COP402
COP402M
COP404LSN-5
COP404
COP404C
NMOS Low Power
NMOS Low Power
NMOS Low Power
NMOS Hi Speed
NMOS Hi Speed
NMOS Low Power
NMOS Hi Speed
CMOS Hi Speed
0.5k
0.5k
0.5k
1.0k
1.0k
1.0k
2.0k
2.0k
32
32
32
63
63
128
160
128
16
16
16
20
16
20
23
23
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
1 Source
Yes
1 Source
4 Sources
1 Source
2 Level
2 Level
2 Level
3 Level
3 Level
3 Level
4 Level
3 Level
No
No
No
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Yes
No
Yes
Yes
100mW 7.5mW
100mW 7.5mW
100mW 7.5mW
50mW N/AmW
125mW N/AmW
125mW N/AmW
35mW
15mW
1mW
0.1 mW
40
40
40
40
40
40
48
48
Has XTAL Oscillator Option
Has RC Oscillator Option
ROMless Version of COP41 OL
Has Interrupt, No Microbus
No Interrupt, Has Microbus
W/Push-Pull Mem Interface
ROM less Version of COP440
CMOS ROMless Device
1-241
1-241
1-227
1-254
1-254
1-296
1-272
1-279
NMOS Hi Speed
NMOS Low Power
CMOS Hi Speed
1.0k
2.0k
2.0k
64
128
128
23
23
23
Yes
Yes
Yes
3 Sources 3 Level
3 Sources 3 Level
1 Source 1 Level
Yes
Yes
Yes
No
No
Yes
50mW N/AmW
125mW N/AmW
1mW
1mW
28
28
28
Includes: CPU, RAM, 1/0
and EPROM Socket
Will Accept Standard EPROM
1-310
1-310
1-310
PIGGYBACK
COP420P
COP444LP
COP444CP
Development Support (Continued)
DIAL·A·HELPER
Order PIN: MOLE·DIAL·A·HLP
Dial-A-Helper is a service provided by the MOLE (Microcontroller On-Line Emulator) applications group. It consists of
both an electronic bulletin board information system and a
method by which applications can take control of a MOLE
Development System at a remote site via modem in order to
resolve any problems.
o"tJ
01:1-
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"T1
FACTORY APPLICATIONS SUPPORT
Do)
Dial-A-Helper also provides immediate factory applications
support. If a user is having difficulty in getting a MOLE to
operate in a particular mode or something peculiar is occurring, he can contact us via his system and modem. He can
leave messages on our electronic bulletin board, which we
will respond to, or he can arrange for us to actually take
control of his system via modem for debugging purposes.
INFORMATION SYSTEM
The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION mode
that can be used to search out and retrieve application data
about NSC Microcontrollers. The user needs as a minimum,
a Dumb terminal, 300 or 1200 baud Modem, and a telephone.
If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk for
later use.
Voice:
o
Information System Package Contains
DIAL-A-HELPER Users Manual PIN
Public Domain Communications Software
The applications group can then cause his system to execute various commands and try to resolve the customers
problem by actually getting customers system to respond.
Both parties see exactly what is occurring, as it is happening.
This allows us to respond in minutes when applications help
is needed.
(408) 721-5582
Modem: (408) 739-1162
Baud:
300 or 1200 baud
Setup:
Length:
a-Bit
Parity:
None
Stop Bit: 1
Operation: 24 Hrs. 7 Days
DIAL·A·HELPER
NATIONAL SEMICONDUCTOR SITE
USER SITE
TLlXX/0072-1
1-7
~.
~
o
....
....
N
Q.
o
o
......
o
o
~National
D Semiconductor
.... COP210C/COP211C Single-Chip CMOS
N
Q.
o Microcontrollers
o
General Description
Features
The COP210C and COP211 C fully static, single-chip CMOS
microcontrollers are members of the COPSTM family, fabricated using double-poly, silicon-gate CMOS technology.
These controller-oriented processors are complete microcomputers containing all system timing, internal logic, ROM,
RAM, and I/O necessary to implement dedicated control
functions in a variety of applications. Features include single
supply operation, a variety of output configuration options,
with an instruction set, internal architecture, and I/O
scheme designed to facilitate keyboard input, display output, and BCD data manipulation. The COP211 C is identical
to the COP210C but with 16 I/O lines instead of 20. They
are an appropriate choice for use in numerous human interface control environments. Standard test procedures and
reliable high-density fabrication techniques provide the medium to large volume customers with a customized controller-oriented processor at a low end-product cost.
• Lowest power dissipation (500 IlW typical)
The COP404C should be used for exact emulation.
Low cost
Power-saving HALT mode with Continue function
Powerful instruction set
512 x 8 ROM, 32 x 4 RAM
20 I/O lines (COP210C)
Two-level subroutine stack
DC to 4.4 Ils instruction time
Single supply operation (4.5V to 5.5V)
General purpose and TRI-STATE® outputs
Internal binary counter register with MICROWIRETM
compatible serial 110
• LSTTL/CMOS compatible in and out
• Software/hardware compatible with other members of
the COP400 family
• Military temperature (- 55°C to + 125°C) devices
•
•
•
•
•
•
•
•
•
•
Block Diagram
L
CoO
CKI
GND
VCC
L
tz
L
CLOCK
INSTRUCTION CLOCK ISYNCI
GENERATOR
SK
I
r-------+..:.::- so IMICROWIRE 1/0
SI
TLlDD/8444-1
FIGURE 1. COP210C
1-8
(')
o"tJ
Absolute Maximum Ratings
If MilitaryI Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Operating Temperature Range
- 55°C to + 125°C
Storage Temperature Range
- 65°C to + 150°C
Lead Temperature (Soldering, 10 sec.)
300°C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electri·
cal specifications are not ensured when operating the de·
vice at absolute maximum ratings.
Maximum Allowable Voltage
Vee = 6V
Voltage at Any Pin
- 0.3V to Vee + 0.3V
Total Allowable Source Current
25mA
Total Allowable Sink Current
25mA
Maximum Allowable Power Consumption
150mW
DC Electrical Characteristics
Parameter
- 55°C
~
TA ~ + 125°C unless otherwise specified
Conditions
Operating Voltage
Supply Current (Note 1)
Min
Max
4.5
5.5
V
4
rnA
Vee = 5.0V, tc = Min
(tc is instruction cycle time)
Units
Power Supply Ripple (Notes 3,4)
Peak to Peak
0.25
V
HALT Mode Current (Note 2)
Vee = 5.0V, FIN = 0 kHz
120
p.A
0.1 Vee
V
V
0.2 Vee
V
V
+10
p.A
7
pF
0.6
V
V
0.2
V
V
5
rnA
Input Voltage Levels
RESET, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
0.9 Vee
0.7 Vee
-10
Hi·Z Input Leakage
Input Capacitance (Note 4)
Output Voltage Levels
LSTTL Operation
Logic High
Logic Low
CMOS Operation
Logic High
Logic Low
Standard Outputs (except CKO)
Vee = 5.0V ± 10%
IOH = -100 p.A
IOL = 400 p.A
2.7
Vee- 0.2
IOH = -10 p.A
IOL = 10 p.A
Allowable SinklSource Current
per Pin (Note 5)
CKO Current Levels (As Clock Out)
+4
Sink
+8
+16
Source
+4
+8
+16
CKI = Vee, VOUT = Vee
CKI = OV, VOUT = OV
Allowable Loading on CKO
(as HALT 1/0 pin)
Current Needed to
Override HALT (Note 6)
To Continue
To Halt
VIN = 0.2 Vee
VIN = 0.7 Vee
rnA
rnA
rnA
rnA
rnA
rnA
0.2
0.4
0.8
-0.2
-0.4
-0.8
50
pF
2.0
3.0
rnA
rnA
TRI·STATE or Open Drain
-10
Leakage Current
+10
p.A
Note 1: Supply Current is measured after running for 2000 cycle times with a square-wave clock on CKI, CKO open, and all other pins pulled up to Vee with 5k
resistors. See current drain equation.
Note 2: The HALT mode will stop CKI from OSCillating in the AC and crystal configurations. Test conditions: all inp~ts tied to Vee. L lines in TAl-STATE mode and
tied to ground, all other outputs low and tied to ground.
Note 3: Voltage change must be less than 0.25V in alms period.
Note 4: This parameter is only sampled and not 100% tested. Variation due to the device included.
Note 5: SO Output sink current must be limited to keep VOL less than 0.2 Vee.
Note 6: When forcing HALT, current is only needed for a short time (approximatey 200 ns) to flip the HALT flip-flop.
1·9
N
.....
«:)
(')
........
(')
o"tJ
N
.....
.....
(')
o
....
....
C'I
AC Electrical Characteristics - 55°C ~ T A ~ + 125°C unless otherwise specified
D.
oo
......
o
o
....
C'I
Min
Max
Instruction Cycle Time (tc)
Parameter
4.4
DC
p,s
Operating CKI
Frequency
DC
DC
DC
0.9
1.8
3.6
MHz
MHz
MHz
6
18
p,s
+ 4 mode
+ 8 mode
+ 16 mode
D.
o
o
Conditions
Instruction Cycle Time
RC Oscillator (Note 4)
R = 30k ±5%
C = 82pF ±5%
Inputs (See Figure 3)
tSETUP (Note 4)
G InputS}
Sllnput
All Others
Output Propagation
Delay
tpD1, tpDO
(+4 Mode)
Units
tc/4 + 0.8
0.33
1.9
0.40
Vee ~ 4.5V
p,s
p,s
p,s
p,s
1.4
VOUT = 1.5V, CL = 100 pF, RL = 5k
p,s
Connection Diagrams
s.o. Wide and DIP
S.O. Wide and DIP
L4
L5
Vec
L&
L3
L2
GND
CKO
CKI
L7
RmT
Iimf
CKI
L7
L&
SO
SK
DO
D1
G2
L5
L4
Gl
VCC
GND
GO
L1
LO
SI
L3
L2
Ll
TL/DD/B444-2
Order Number COP211C-XXX/D,
See NS Hermetic Package Number D20A
TL/DD/B444-3
Order Number COP211C-XXXIN,
See NS Molded Package Number N20A
Order Number COP210C-XXX/D,
See NS Hermetic Package Number D24C
Order Number COP211C-XXX/WM
See NS Surface Mount Package Number M20B
Order Number COP210C-XXXIN,
See NS Molded Package Number N24A
Order Number COP210C-XXX/WM
See NS Surface Mount Package Number M24B
Pin Descriptions
Pin
SK
Description
8-bit bidirectional 1/0 port with TRI-STATE
4-bit bidirectional 1/0 port
(G2-GO for 20-pin package)
4-bit general purpose output port
(01-00 for 20-pin package)
Serial input (or counter input)
Serial output (or general purpose output)
Pin
L7-Lo
G3- GO
03- 0 0
SI
SO
CKI
CKO
RESET
Vee
GND
Description
Logic-controlled clock
(or general purpose output)
System oscillator input
Crystal oscillator output, or HALT mode
1/0 port (24-pin package only)
System reset input
System power supply
System Ground
FIGURE 2
CKI
G3-Go.
03-00. _ _ _ _ _ _ _ _ _
L7-Lo.SO.SK
..£.I.'./.L~
OUTPUTS
TLIDD/B444-4
FIGURE 3. Input/Output Timing Diagrams (Divide-by-8 Mode)
1-10
0
Functional Description
Bd VALUE
0
RAM DIGIT
"0
I\)
.....
lS-
A block diagram of the COP210C is given in Figure 1. Data
paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. Positive logic is
used. When a bit is set, it is a logic "1"; when a bit is reset, it
is a logic "0".
0
14-
13-
0
......
12-·
0
0
"0
l\)
.....
.....
Il10-
PROGRAM MEMORY
0
9-
Program memory consists of a 512-byte ROM. As can be
seen by an examination of the COP21 OC/211 C instruction
set, these words may be program instructions, program
data, or ROM addressing data. Because of the special characteristics associated with the JP, JSRP, JID, and LQID instructions, ROM must often be thought of as being organized into a pages of 64 words (bytes) each.
ROM ADDRESSING
ROM addressing is accomplished by a 9-bit PC register. Its
binary value selects one of the 512 a-bit words contained in
ROM. A new address is loaded into the PC register during
each instruction cycle. Unless the instruction is a transfer of
control instruction, the PC register is loaded with the next
sequential 9-bit binary count value. Two levels of subroutine
nesting are implemented by two 9-bit subroutine save registers, SA and SB.
0-
• Can be directly addressed by
LSI instruction (See Table III)
TL/DD/8444-5
FIGURE 4. RAM Digit Address to
Physical RAM Digit Mapping
The G register contents are outputs to four general purpose
bidirectional liD ports.
ROM instruction words are fetched, decoded, and executed
by the instruction decode, control and skip logic circuitry.
The Q register is an internal, latched, a-bit register, used to
hold data loaded from RAM and A, as well as a-bit data from
ROM. Its contents are output to the L liD ports when the L
drivers are enabled under program control. (See LEI instruction.)
DATA MEMORY
Data Memory consists of a 12a-bit RAM, organized as four
data registers of ax 4-bit digits. RAM addressing is implemented by a 6-bit B register whose upper two bits (Br) selects one of four data registers and lower three bits of the 4bit Bd select one of eight 4-bit digits in the selected data
register. While the 4-bit contents of the selected RAM digit
(M) are usually loaded into or from, or exchanged with, the A
register (accumulator), they may also be loaded into the Q
latches or loaded from the L ports. RAM addressing may
also be performed directly by the XAD 3, 15 instruction. The
Bd register also serves as a source register for 4-bit data
sent directly to the D outputs.
The eight L drivers, when enabled, output the contents of
latched Q data to the L liD ports. Also, the contents of L
may be read directly into A and RAM.
The SID register functions as a 4-bit serial-in/serial-out shift
register or as a binary counter, depending upon the contents of the EN register. (See EN register description
below.) Its contents can be exchanged with A, allowing it to
input or output a continuous serial data stream. With SID
functioning as a serial-in/serial-out shift register and SK
as a sync clock, the COP210C/211C is MICROWIRE
compatible.
The most significant bit of Bd is not used to select a RAM
digit. Hence, each physical digit of RAM may be selected by
two different values of Bd as shown in Figure 4. The skip
condition for XIS and XDS instructions will be true if Bd
changes between 0 to 15, but not between 7 and a (see
Table III).
The D register provides four general purpose outputs and is
used as the destination register for the 4-bit contents of Bd.
The XAS instruction copies C into the SKL latch. In the
counter mode, SK is the output of SKL; in the shift register
mode, SK is a sync clock, inhibited when SKL is a logic "0".
INTERNAL LOGIC
The EN register is an internal 4-bit register loaded under
program control by the LEI instruction. The state of each bit
of this register selects or deselects the particular feature
associated with each bit of the EN register (EN3-ENO).
The internal logic of the COP21 OC/211 C is designed to ensure fully static operation of the device.
The 4-bit A register (accumulator) is the source and destination register for most liD, arithmetic, logic and data memory
access operations. It can also be used to load the Bd portion of the B register, to load four bits of the a-bit Q latch
data and to perform data exchanges with the SID register.
1. The least significant bit of the enable register, ENO, selects the SID register as either a 4-bit shift register or as a
4-bit binary counter. With ENO set, SID is an asynchronous binary counter, decrementing its value by one upon
each low-going pulse ("1" to "0") occurring on the SI
input. Each pulse must be at least two instruction cycles
wide. SK outputs the value of SKL. The SO output is
equal to the value of EN3. With ENO reset, SID is a serial
shift register, shifting left each instruction cycle time. The
data present at SI is shifted into the least significant bit of
SID. SO can be enabled to output the most significant bit
of SID each instruction cycle time. (See 4, below.) The
SK output becomes a logic-controlled clock.
The 4-bit adder performs the arithmetic and logic functions
of the COP21 OC/211 C, storing its results in A. It also outputs the carry information to a 1-bit carry register, most often employed to indicate arithmetic overflow. The C register,
in conjunction with the XAS instruction and the EN register,
also serves to control the SK output. C can be outputted
directly to SK or can enable SK to be a sync clock each
instruction cycle time. (See XAS instruction and EN register
description below.)
1-11
....
(.)
N
Functional Description
D.;
o(.)
(Continued)
TABLE I. Enable Register Modes- Bits ENO and EN3
......
(.)
ENO
EN3
o
....
0
0
N
D.
0
o(.)
SIO
SI
Shift Register
Shift Register
0
1
Binary Counter
Bina~ Counter
Input to Shift
Register
Input to Shift
Register
Input to Counter
In~ut to Counter
2. EN1 is not used, it has no effect on the COP210C/211C.
SO
0
Serial
out
0
1
SK
If SKL = 1, SK
If SKL = 0, SK
If SKL = 1, SK
If SKL = 0, SK
SK = SKL
SK = SKL
= clock
=0
= clock
=0
COP211C
If the COP210C is bonded as a 20-pin package, it becomes
the COP211 C, illustrated in Figure 2, COP21 OC/211 C Connection Diagrams. Note that the COP211 C does not contain
D2, D3, G3, or CKO. Use of this option, of course, precludes
use of D2, D3, G3, and CKO options. All other options are
available for the COP211 C.
3. With EN2 set, the L drivers are enabled to output the data
in Q to the L 1/0 ports. Resetting EN2 disables the L
drivers, placing the L I/O ports in a high impedance input
state.
4. EN3, in conjunction with ENO, affects the SO output. With
ENO set (binary counter option selected), SO will output
the value loaded into EN3. With ENO reset (serial shift
register option selected), setting EN3 enables SO as the
output of the SIO shift register, outputting serial shifted
data each instruction time. Resetting EN3 with the serial
shift register option selected, disables SO as the shift
register output; data continues to be shifted through SIO
and can be exchanged with A via an XAS instruction but
SO remains reset to "0".
HALT MODE
The COP21 OC/211 C is a fully static circuit; therefore, the
user may stop the system oscillator at any time to halt the
chip. The chip also may be halted by the HALT instruction or
by forcing CKO high when it is used as a HALT 1/0 port.
Once in the HALT mode, the internal circuitry does not receive any clock signal, and is therefore frozen in the exact
state it was in when halted. All information is retained until
continuing. The HALT mode is the minimum power dissipation state.
The HALT mode has slight differences depending upon the
type of oscillator used.
INITIALIZATION
The internal reset logic will initialize the device upon powerup if the power supply rise time is less than 1 ms and if the
operating frequency at CKI is greater than 32 kHz, otherwise the external RC network shown in Figure 5 must be
connected to the RESET pin. The RESET pin is configured
as a Schmitt trigger input. If not used, it should be connected to Vee. Initialization will occur whenever a logic "0" is
applied to the RESET input, providing it stays low for at
least three instruction cycle times.
a. 1-pin oscillator-RC or external
The HALT mode may be entered into by either program
control (HALT instruction) or by forcing CKO to a logic
"1" state.
The circuit may be awakened by one of two different
methods:
1) Continue function. By forcing CKO to a logic "0", the
system clock is re-enabled and the circuit continues to
operate from the point where it was stopped.
When Vee power is applied, the internal reset logic will keep
the chip in initialization mode for up to 2500 instruction cycles. If the CKI clock is running at a low frequency, this
could take a long time, therefore, the internal logic should
be disabled by a mask option with initialization controlled
solely by RESET pin.
2) Restart. Forcing the RESET pin to a logic "0" will restart the chip regardless of HALT or CKO (see initialization).
Note: If CKI clock is less than 32 kHz, the internal reset logic (Option 25 = 1)
must be disabled and the external RC network must be present.
b. 2-pin oscillator-crystal
The HALT mode may be entered into by program control
(HALT instruction) which forces CKO to a logic "1" state.
The circuit can be awakened only by the RESET function.
Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, D, EN, and G registers are cleared.
The SK output is enabled as a SYNC output, providing a
pulse each instruction cycle time. Data memory (RAM) is
not cleared upon initialization. The first instruction at address 0 must be a CLRA (clear A register).
HALT 110
HALT
INSTRUCTION
p + -....~....- - -.......
o
W
vee
E
RESET---LJ
R
S
U
p
P
L
V
...............-IRESET C0P21DC
GND
TL/DD/8444-7
Halt I/O Port
CKO PIN OPTIONS
TL/DD/8444-6
RC
> 5 x Power Supply Rise Time and RC > 100 x CKI Period
In a crystal-controlled oscillator system, CKO is used as an
output to the crystal network. CKO will be forced high during
the execution of a HALT instruction, thus inhibiting the crystal network. If a 1-pin oscillator system is chosen (RC or
FIGURE 5. Power-Up Clear Circuit
1-12
o
Functional Description
COP210C/COP211C Instruction Set
(Continued)
external), CKO will be selected as HALT and is an 1/0 flipflop which is an indicator of the HALT status. An external
signal can override this pin to start and stop the chip. By
forcing a high level to CKO, the chip will stop as soon as
CKI is high and the CKO output will go high to keep the chip
stopped. By forcing a low level to CKO, the chip will continue and CKO output will go low.
Table II is a symbol table providing internal architecture, instruction operand and operational symbols used in the instruction set table.
Table III provides the mnemonic, operand, machine code,
data flow, skip conditions and description associated with
each instruction in the COP21 OC/211 C instruction set.
A
OSCILLATOR OPTIONS
There are three options available that define the use of CKI
and CKO.
CKI
CKO
R2
a. Crystal-Controlled Oscillator. CKI and CKO are connected to an external crystal. The instruction cycle time
equals the crystal frequency divided by 16 (optionally by 8
or 4).
...ru-
HAll
EXTERNAL
CLOCK
b. External Oscillator. CKI is configured as LSTTL-compatible input accepting an external clock signal. The external
frequency is divided by 16 (optionally by 8 or 4) to give
the instruction cycle time. CKO is the HALT 1/0 port.
C
c. RC-Controlled Oscillator. CKI is configured as a single pin
RC-controlled Schmitt trigger oscillator. The instruction
cycle equals the oscillation frequency divided by 4. CKO
is the HALT 1/0 port.
The RC oscillator is not recommended in systems that require accurate timing or low current. The RC oscillator
draws more current than an external oscillator (typically an
additional 100 IJ.A at 5V). However, when the part halts, it
stops with CKI high and the halt current is at the minimum.
TL/DD/8444-8
FIGURE 6. COP210C Oscillator
RC-Controller
OSCillator
Crystal or Resonator
R1
32kHz
455 kHz
3.58 MHz
220k
5k
1k
Cycle
Time
20M
10M
1M
30
80
30
5-36
40
6-36
17-25 }J.s
6-181J.s
TABLE II. COP210C/211C Instruction Set Table Symbols
Symbol
Definition
Symbol
Definition
INTERNAL ARCHITECTURE SYMBOLS
INSTRUCTION OPERAND SYMBOLS
A
B
d
Br
8d
C
o
EN
G
L
M
PC
Q
SA
S8
SIO
SK
I\)
-10
o
o
......
o
o-a
I\)
-10
-10
o
All features associated with the CKO 1/0 pin are available
with the 24-pin package only.
Crystal
Value
o-a
4-bit Accumulator
6-bit RAM Address Register
Upper 2 bits of 8 (register address)
Lower 4 bits of 8 (digit address)
1-bit Carry Register
4-bit Data Output Port
4-bit Enable Register
4-bit Register to latch data for G 1/0 Port
a-bit TRI-STATE 1/0 Port
4-bit contents of RAM Memory pOinted to by 8
Register
9-bit ROM Address Register (program counter)
a-bit Register to latch data for L 1/0 Port
9-bit Subroutine Save Register A
9-bit Subroutine Save Register 8
4-bit Shift Register and Counter
Logic-Controlled Clock Output
4-bit Operand Field, 0-15 binary (RAM Digit Select)
2-bit Operand Field, 0-3 binary (RAM Register
Select)
a
9-bit Operand Field, 0-511 binary (ROM Address)
y
4-bit Operand Field, 0-15 binary (Immediate Data)
RAM(s) Contents of RAM location addressed by s
ROM(t) Contents of ROM location addressed by t
OPERATIONAL SYMBOLS
+
-+
~
A
e
1-13
Plus
Minus
Replaces
Is exchanged with
Is equal to
The one's complement of A
Exclusive-OR
Range of values
o
.,..
.,..
N
a..
o
o
'"
o
o
.,..
Instruction Set (Continued)
TABLE III. COP210C/211C Instruction Set
Mnemonic Operand
Machine
Hex
Language Code
Code
(Binary)
DataFlow
Skip Conditions
Description
N
a..
o
o
ARITHMETIC INSTRUCTIONS
ASC
30
10011100001
A + C + RAM(8)
Carry ~ C
ADD
31
10011100011
A + RAM(8)
5-
10101 1
A+y
CLRA
00
10000100001
CaMP
40
Nap
~
~
A Carry
A
Add with Carry, Skip on
Carry
None
Add RAMtoA
Carry
Add immediate, Skip on
Carry (y '* 0)
O~A
None
Clear A
10100100001
A~A
None
One's complement of A to A
44
10100101001
None
None
No Operation
RC
32
10011100101
"0"
~
C
None
ResetC
SC
22
10010100101
"1"
~
C
None
SetC
XOR
02
10000100101
A E9 RAM(8)
A
None
Exclusive-OR RAM with A
~
None
Jump Indirect (Note 2)
None
Jump
None
Jump within Page
(Note 1)
AISC
y
Y..
1
~
A
~
TRANSFER OF CONTROL INSTRUCTIONS
JID
JMP
a
FF
11111111111
6-
1011O lOOOIaei
1
1 aZ'Q
JP
a
-
JSRP
a
-
ROM (PCs, A,M)
PC7:0
a
~
PC
111 as·Q 1 a ~ PC6:0
(pages 2,3 only)
or
111 1 as·Q 1 a ~ PC5:0
(all other pages)
110 1
a5'Q
1 PC
+1
~
SA
~
S8
None
Jump to Subroutine Page
(Note 2)
~
S8
None
Jump to Subroutine
Return from Subroutine
010 ~ PCS:6
a ~ PC5:0
JSR
a
6-
-
1011011001 ae 1 PC + 1 ~ SA
1 a ~ PC
1 aZ'Q
RET
48
10100110001
S8
~
SA
~
PC
None
RETSK
49
10100110011
S8
~
SA
~
PC
Always Skip on Return Return from Subroutine
then Skip
HALT
33
38
10011 10011 1
10011110001
None
1-14
Halt processor
o
o"C
Instruction Set (Continued)
N
.....
TABLE III. COP210C/211C Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
o
o.......
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
N
.....
.....
MEMORY REFERENCE INSTRUCTIONS
CAMO
33
3C
1001110011 I
1001111100 I
A -+ 07:4
RAM (B) -+ 03:0
None
Copy A, RAM to 0
COMA
33
2C
1001110011 I
1001011100 I
07:4 -+ RAM (B)
03:0 -+ A
None
Copy 0 to RAM, A
-5
100lrl01011
RAM (B) -+ A
Br ED r -+ Br
None
Load RAM into A
Exclusive-OR Br with r
BF
11011 11111
ROM(PCa,A,M) -+ Q
SA -+ SB
None
Load 0 Indirect
LD
r
LOID
o
o"C
I
RMB
0
1
2
3
4C
45
42
43
1010011100 I
10100101011
10100100101
1010010011 I
o -+
o -+
o -+
o -+
RAM(B)o
RAM(B)1
RAM(B)2
RAM(Bh
None
Reset RAM Bit
5MB
0
1
2
3
40
47
46
4B
10100111011
10100101111
10100101101
10100110111
1
1
1
1
-+
-+
-+
-+
RAM(B)o
RAM(Bh
RAM(B)2
RAM(Bh
None
Set RAM Bit
STII
y
7-
10111 1
y -+ RAM(B)
Bd + 1 -+ Bd
None
Store Memory Immediate
and Increment Bd
X
r
-6
100 1r I0110 I
RAM (B) +-+ A
Br ED r -+ Br
None
Exchange RAM with A,
Exclusive-OR Br with r
XAD
3,15
23
BF
RAM(3,15) +-+ A
None
Exchange A with RAM
(3,15)
XDS
r
-7
1001010011 I
11011 11111 I
100 1r 10111 I
RAM (B) +-+ A
Bd -1 -+ Bd
Br ED r -+ Br
Bd decrements past 0
Exchange RAM with A
and Decrement Bd
Exclusive-OR Br with r
XIS
r
-4
100 Ir I0100 I
RAM (B) +-+ A
Bd + 1 -+ Bd
Br ED r -+ Br
Bd increments past 15
Exchange RAM with A
and Increment Bd
Exclusive-OR Br with r
y.
I
REGISTER REFERENCE INSTRUCTIONS
CAB
50
10101100001
A -+ Bd
None
Copy A to Bd
CBA
4E
10100111101
Bd -+ A
None
Copy BdtoA
LBI
r,d
-
100 1r 1(d - 1) 1
(d = 0,9:15)
r,d -+ B
Skip until not a LBI
Load B Immediate with
r,d
LEI
y
33
6-
1001110011 I
10110 1 y I
y -+ EN
None
Load EN Immediate
1-15
o
o
....
N
Instruction Set (Continued)
~
o
(:)
....o
'"
D.
8
TABLE III. COP210C/211C Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Description
Skip Conditions
-
TEST INSTRUCTIONS
SKC
20
1001010000
C = "1"
SKE
21
1001010001
A
SKGZ
33
21
1001110011
1001010001
G3:0
0
1
2
3
33
01
11
03
13
1001110011
1000010001
1000110001
1000010011
1001010011
0
1
2
3
01
11
03
13
1000010001
1000110001
1000010011
1000110011
SKG8Z
SKM8Z
Skip if C is True
= RAM(8)
=0
Skip if A Equals RAM
Skip if G is Zero
(all 4 bits)
Skip if G 8it is Zero
1st byte
Go
G1
G2
G3
} 2nd byte
=0
=0
=0
=0
RAM(8)0
RAM(8h
RAM(8)2
RAM(8)3
=0
=0
=0
=0
Skip if RAM 8it is Zero
INPUTIOUTPUT INSTRUCTIONS
ING
33
2A
10011100111
10010110101
G-+A
None
Input G Ports to A
INL
33
2E
10011100111
10010111101
L7:4 -+ RAM(8)
L3:0 -+ A
None
Input L Ports to RAM, A
08D
33
3E
10011100111
10011 11110 1
8d -+ D
None
Output 8d to D Outputs
OMG
33
3A
10011100111
10011110101
RAM(8) -+ G
None
Output RAM to G Ports
XAS
4F
10100111111
A
None
Exchange A with SID
or 3. The JP instruction,
~
SIO,C -+ SKL
Note 1: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2
otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of Pl. A JSRP may not be used when in pages 2 or 3. JSRP
may not jump to the last word In page 2.
Note 2: A JSRP
Description of Selected
Instructions
The following information is provided to assist the user in
understanding the operation of several unique instructions
and to provide notes useful to programmers in writing
COP21 OC/211 C programs.
ROM address register PC with the contents of ROM addressed by the 9-bit word, PCa, A, M. PCa is not affected by
this instruction.
Note: JID uses two instruction cycles if executed, one if skipped.
XAS INSTRUCTION
XAS (Exchange A with SID) exchanges the 4-bit contents of
the accumulator with the 4·bit contents of the SID register.
The contents of SID will contain serial·in/serial·out shift register or binary counter data, depending on the value of the
EN register. An XAS instruction will also affect the SK output. (See Functional Description, EN Register). If SID is selected as a shift register, an XAS instruction must be performed once every four instruction cycle times to effect a
continuous data stream.
LQID INSTRUCTION
LaiD (Load a Indirect) loads the a-bit a register with the
contents of ROM pointed to by the 9-bit word PCa, A, M.
LaiD can be used for table look-up or code conversion such
as 8CD to 7-segment. The LaiD instruction "pushes" the
stack (PC + 1 -+ SA -+ S8) and replaces the least
significant eight bits of the PC as follows: A -+ PC7:4,
RAM(8) -+ PC3:0, leaving PCa unchanged. The ROM data
pointed to by the new address is fetched and loaded into
the a latches. Next, the stack is "popped" (S8 -+ SA -+
PC), restoring the saved value of the PC to continue sequential program execution. Since LaiD pushes SA -+
S8, the previous contents of S8 are lost.
Note: LQID uses two instruction cycles If executed, one if skipped.
JID INSTRUCTION
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location pointed
to indirectly by A and M. It loads the lower eight bits of the
1-16
o
o
"tJ
I\)
.....
Description of Selected
Instructions (Continued)
o
If using an external squarewave oscillator, the following
equation can be used to calculate the COP210C current
drain.
Ic = Iq + (V X 35 X Fi) + (V X 2195 X Fi/Dv)
where Ic = chip current drain in microamps
Iq = quiescent leakage current (from curve)
Fi = CKI frequency in megahertz
V = chip Vee in volts
Dv = divide by option selected
For example, at 5V Vee and 400 kHz (divide by 4),
Ic = 10 + (5 X 35 X 0.4) + (5 X 2195 X 0.4/4)
Ic = 10 + 50 + 1097.5 = 1157.5 /-LA
INSTRUCTION SET NOTES
a. The first word of a COP21 OC/211 C program (ROM address 0) must be a CLRA (Clear A) instruction.
b. Although skipped instructions are not executed, one instruction cycle time is devoted to skipping each byte of
the skipped instruction. Thus all program paths take the
same number of cycle times whether instructions are
skipped or executed (except JID and LaiD).
c. The ROM is organized into eight pages of 64 words each.
The program counter is a 9-bit binary counter, and will
count through page boundaries. If a JP, JSRP, JID, or
LaiD instruction is located in the last word of a page, the
instruction operates as if it were in the next page. For
example: A JP located in the last word of a page will jump
to a location in the next page. Also, a LaiD or JID located
in the last word in page 3 or 7 will access data in the next
group of four pages.
1/0 OPTIONS
COP21 OC/211 C outputs have the following optional configurations, illustrated in Figure 7:
a. Standard. A CMOS push-pull buffer with an N-channel
device to ground in conjunction with a P-channel device
to Vee, compatible with CMOS and LSTTL.
b. Open Drain. An N-channel device to ground only, allowing external pull-up as required by the user's application.
POWER DISSIPATION
The lowest power drain is when the clock is stopped. As the
frequency increases so does current. Current is also lower at lower operating voltages. Therefore, to minimize power consumption, the user should run at the lowest speed
and voltage that his application will allow. The user should
take care that all pins swing to full supply levels to ensure
that outputs are not loaded down and that inputs are not at
some intermediate level which may draw current. Any input
with a slow rise or fall time will draw additional current. A
crystal- or resonator-generated clock will draw additional
current. An RC oscillator will draw even more current since
the input is a slow rising signal.
c. Standard TRI-STATE L Output. A CMOS output buffer
similar to (a) which may be disabled by program control.
d. Open-Drain TRI-STATE L Output. This has the N-channel
device to ground only.
The SI and RESET inputs are Hi-Z inputs (Figure 7e).
When using either the G or L 1/0 ports as inputs, an external pull-up device is necessary.
a. Standard Push-Pull Output
b. Open Drain Output
Vee
D=t>;f
c. Standard TRI-STATE
OIL" Output
d. Open Drain TRI-STATE
OIL" Output
Vee
e. Hi-Z Input
TLlDD/8444-9
FIGURE 7. I/O Configurations
to allow the designer to effectively use these 1/0 configurations.
All output drivers uses one or two common devices numbered 1 to 2. Minimum and maximum current (lOUT and
VOUT) curves are given in Figure 8 for each of these devices
1-17
o
.......
o
o
"tJ
I\)
.....
.....
o
o
.,...
.,...
N
a.
Typical Performance Characteristics
oo
......
.,...
N
a.
o
o
Minimum Sink Current
(Except CKO)
oo
Minimum Source Current
(Except CKO)
2.4 .------r----r--,-----,--,..----,
1.2 .------r----r--,-----,--,...----,
2.0 I---t---+--t--+-t----I
1.0 I---t---+--t--+-t----I
1.6 1--+----+-+--+-+--1
]:
~
__ 0.8
~
~~ ":'ee=4.5V
~ ,.,.-
0.8
1.0
~4.5V""""""~
-~~
0.4
0.4;~
o
V =5.5V
ee
!0.6~
Vee=5.5V
I-"::"""
1.2
0.2
2.0
3.0
4.0
5.0
o
6.0
I\.
......
1.0
2.0
3.0
~~
4.0
5.0
6.0
VOH (VOLTS)
VOL (VOLTS)
TLIOO/8444-10
Maximum Quiescent Current
140
120
- - I!SOC-
-'"~
100 I--+--+---If--+--t----l
~ 801--+--+---If--+--t----l
~
60 I---+--+--If---f=r-+----I
_~---8~OC
401---+--+--If--_+~-700ct--~
-r-
201-!-~~~~~2tSOC~.
4.0
5.0
6.0
Vee (VOLTS)
TL/OO/8444-11
FIGURES
1-18
o
o
Option List
"'C
The COP21 OC/211 C mask-programmable options are assigned numbers which correspond with the COP210C pins.
Option 10: L3 Driver. (Same as Option 5.)
N
......
Option 11: L2 Driver. (Same as Option 5.)
The following is a list of COP21 OC options. When specifying
a COP211 chip, options 20,21, and 22 must be set to o. The
options are programmed at the same time as the ROM pattern to provide the user with the hardware flexibility to interface to various 1/0 components using little or no external
circuitry.
Option 12: L1 Driver. (Same as Option 5.)
,o
Option 1:
0 = Ground Pin. No options available.
Option 15: SO Output.
Option 2:
CKO 1/0 Port Determined by Option 3. = 0 no
option (a. is crystal oscillator output for two pin
oscillator b. is HALT 1/0 for one pin oscillator)
Option 3:
Option 13: Lo Driver. (Same as Option 5.)
No option available.
= 0: Standard push-pull output.
= 2: Open-drain output.
Option 16: SK Driver. (Same as Option 15.)
CKI Input.
Option 17: Go 1/0 Port. (Same as Option 15.)
Option 18: G1 1/0 Port. (Same as Option 15.)
Option 19: G2 1/0 Port. (Same as Option 15.)
= 2: External oscillator input (7 4).
Option 20: G3 1/0 Port. (Same as Option 15.)
= 3: Crystal oscillator input (7 8).
Option 21: 03 Output. (Same as Option 15.)
= 4: External oscillator input (7 8).
Option 22: 02 Output. (Same as Option 15.)
= 5: Crystal oscillator input (7 16).
= 6: External oscillator input (7 16).
Option 23: 01 Output. (Same as Option 15.)
Option 24: Do Output. (Same as Option 15.)
RESET Input = 1: Hi-Z input. No option
Option 25: Internal Initialization Logic.
available.
= 0: Normal operation.
= 1: No internal initialization logic.
L7 Driver
= 0: Standard TRI-STATE push-pull output.
Option 26: No option available.
= 2: Open-drain TRI-STATE output.
Option 6:
L6 Driver. (Same as Option 5.)
Option 7:
Ls Driver. (Same as Option 5.)
Option 8:
L4 Driver. (Same as Option 5.)
Option 9:
Vee Pin = 0 no option.
o
= 1: Hi-Z input.
= 1: Single-pin RC-controlled oscillator (7 4).
Option 5:
o
o"'C
N
......
......
Option 14: SI Input.
= 0: Crystal-controlled oscillator input (7 4).
Option 4:
o
Option 27: COP Bonding
= 0: COP21 OC (24-pin device).
= 1: COP211 C (20-pin device). See Note.
= 2: COP210C and COP211C. See Note.
Note: If option 27 = 1 or 2 then option 20 must
=
o.
Option Table
Please fill out a photocopy of the Option Table and send along with your EPROM.
Option Table
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
1 Value
2 Value
3 Value
4 Value
5 Value
6 Value
7 Value
8 Value
9 Value
10 Value
11 Value
12 Value
13 Value
14 Value
=
=
o
o
=
=
=
=
=
=
=
=
=
=
=
=
o
is:
is:
is:
is:
is:
is:
is:
is:
Ground Pin
CKO Pin
CKllnput
RESET Input
L7 Driver
L6 Driver
Ls Driver
L4 Driver
is:
is:
is:
is:
is:
is:
Vee Pin
L3 Driver
L2 Driver
L1 Driver
Lo Driver
Sllnput
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
15 Value
16 Value
17 Value
18 Value
19 Value
20 Value
21 Value
22 Value
23 Value
24 Value
25 Value
=
=
=
=
=
=
=
=
=
=
=
Option 26 Value =
Option 27 Value =
1-19
0
is: SO Output
is: SK Driver
is: Go 1/0 Port
is: G1 1/0 Port
is: G2 1/0 Port
is: G3 1/0 Port
is: 03 Output
is: 02 Output
is: 01 Output
is: Do Output
is: Internal
Initialization Logic
is: No Option
is: COPS Bonding
III
o
il)
~
C'I
D-
O
o
......
o
~
~
C'I
D-
O
o
......
o
CD
C'I
C'I
D-
O
o
......
o
il)
C'I
C'I
D-
O
o
......
o
~
C'I
C'I
D-
O
o
~National
U Semiconductor
COP224C/COP225C/COP226C/COP244C/COP245C
Single-Chip 1k and 2k CMOS Microcontrollers
General Description
Features
The COP224C, COP225C, COP226C, COP244C and
COP245C fully static, Single-Chip CMOS Microcontrollers
are members of the COPSTM family, fabricated using double-poly, silicon gate microCMOS technology. These Controller Oriented Processors are complete microcomputers
containing all system timing, internal logic, ROM, RAM, and
I/O necessary to implement dedicated control functions in a
variety of applications. Features include single supply operation, a variety of output configuration options, with an instruction set, internal architecture and I/O scheme designed to facilitate keyboard input, display output and BCD
data manipulation. The COP224C and COP244C are 28 pin
chips. The COP225C and COP245C are 24-pin versions (4
inputs removed) and COP226C is 20-pin version with 15 I/O
lines. Standard test procedures and reliable high-density
techniques provide the medium to large volume customers
with a customized microcontroller at a low end-product cost.
These microcontrollers are appropriate choices in many demanding control environments especially those with human
interface.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Lowest power dissipation (600 p.W typical)
Fully static (can turn off the clock)
Power saving IDLE state and HALT mode
4.4 p's instruction time
2k x 8 ROM, 128 x 4 RAM (COP244C/COP245C)
1k x 8 ROM, 64 x 4 RAM (COP224C/COP225C/
COP226C)
23 I/O lines (COP244C and COP224C)
True vectored interrupt, plus restart
Three-level subroutine stack
Single supply operation (4.5V to 5.5V)
Programmable read/write 8-bit timer/event counter
Internal binary counter register with MICROWIRETM
serial I/O capability
General purpose and TRI-STATE® outputs
LSTTL/CMOS output compatible
Software/hardware compatible with COP400 family
Military temperature (- 55°C to + 125°C) operation
Block Diagram
MmiiON------DIlLY
ZI
...
11
••
J
I
U
n
14
IIIJ IMZ 1111 1111
11
• Not available on COP226C
TLIDD/8422-1
FIGURE 1
1-20
o
o-a
Absolute Maximum Ratings
~
~
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (Vee)
- 55·C to + 125·C
Storage Temperature Range
-65·C to + 150·C
o
.......
300·C
o-a
Lead Temperature
6V
Voltage at any Pin
(soldering, 10 seconds)
-0.3VtoVee +0.3V
Total Allowable Source Current
25 rnA
Total Allowable Sink Current
25 rnA
Total Allowable Power Dissipation
DC Electrical Characteristics
Parameter
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
150mW
0I:loo
Operating Temperature Range
Conditions
Peak to Peak
Supply Current
(Note 1)
Vee=5.0V, tc=4.4 p.s
(tc is instruction cycle time)
HALT Mode Current (Note 2)
Vee = 5.0V, FIN = 0 kHz
~
~
U1
o
.......
o
o-a
~
~
-55·C:>:TA:>: + 125·C, +4.5V:>:Vee:>: +5.5Vunless otherwise specified
Operating Voltage
Power Supply Ripple (Note 5)
o
Min
Max
Units
4.5
5.5
0.25 Vee
V
V
5
rnA
200
p.A
en
o
.......
o
o-a
~
0I:loo
0I:loo
o.......
o
o-a
~
0I:loo
Input Voltage Levels
RESET, CKI, Do (clock input)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
U1
o
-10
Input Capacitance (Note 4)
CKO Current Levels (As Clock Out)
Sink
+4
+8
+16
+4
Source
+8
+16
}
}
V
V
0.2 Vee
V
V
+10
p.A
7
pF
0.6
V
V
0.2
V
V
0.7 Vee
Hi-Z Input Leakage
Output Voltage Levels (except CKO)
LSTIL Operation
Logic High
Logic Low
CMOS Operation
Logic High
Logic Low
0.1 Vee
0.9 Vee
Standard Outputs
Vee=5.0V± 10%
IOH= -100 p.A
IOl =400 p.A
IOH= -10 p.A
IOl =10 p.A
CKI=Vee, VOUT=Vee
CKI=OV, VOUT=OV
2.7
Vee- 0.2
rnA
rnA
rnA
rnA
rnA
rnA
0.2
0.4
0.8
-0.2
-0.4
-0.8
Allowable Sink/Source Current per Pin
(Note 6)
5
rnA
Allowable Loading on CKO (as HALT)
50
pF
2.0
3.0
rnA
rnA
+10
p.A
Current Needed to Over-Ride HALT
(Note 3)
To Continue
To Halt
VIN=0. 2Vee
VIN=0. 7Vee
TRI-STATE or Open Drain
Leakage Current
-10
1-21
II
u
LI)
'III:t
N
Q.
o
U
.....
U
'III:t
'III:t
N
Q.
o
U
.....
AC Electrical Characteristics
-55°C:5:TA:5: + 125°C. +4.5V:5:Vcc:5: +5.5V unless otherwise specified.
Parameter
Conditions
Instruction Cycle Time (tc)
Operating CKI
Frequency
+ 4 mode
+ 8 mode
+ 16 mode
}
Min
Max
4.4
DC
Units
DC
DC
DC
0.9
1.8
3.6
MHz
MHz
MHz
40
60
%
U
Duty Cycle (Note 4)
11 =3.6 MHz
Rise Time (Note 4)
11 =3.6 MHz External Clock
60
ns
o
Fall Time (Note 4)
11 =3.6 MHz External Clock
40
ns
LI)
Instruction Cycle Time
RC Oscillator (Note 4)
R=30k ±5%
C=82 pF ±5% (+4 Mode)
18
JJ-s
CD
N
N
Q.
U
.....
U
N
N
Q.
o
.....
U
U
'III:t
N
N
Q.
o
U
6
Inputs: (See Figure 3) (Note 4)
tSETUP
Output Propagation Delay
G Inputs
Sllnput
All Others
tc/4+0.8
0.33
1.9
0.4
VOUT= 1.5V. CL = 100 pF. RL =5k
1.4
tpD1. tpDo
Note 1: Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI, eKO open, and all other pins pulled up to Vee with 5k
resistors. See current drain equation on page 13.
Note 2: The HALT mode will stop CKI from oscillating in the RC and crystal configurations. Test conditions: all inputs tied to Vee, L lines in TRI·STATE mode and
tied to ground, all outputs low and tied to ground.
Note 3: When forcing HALT. current is only needed for a short time (approx. 200 ns) to flip the HALT flip-flop.
Note 4: This parameter is not tested but guaranteed by design. Variation due to the device included.
Note 5: Voltage change must be less than 0.25 volts in alms period.
Note 6: SO output sink current must be limited to keep VOL less than 0.2 Vee when part is running in order to prevent entering test mode.
1-22
o
o"'D
Connection Diagrams
S.O. Wide and DIP
I\)
I\)
S.O. Wide and DIP
GND
aND
24
CKO
23
CKI
22
CKI
02
RESET
03
IfrnT
21
L7
G3
L7
20
L6
G2
L6
6 • COP225C
COP245C
L5
COP226C
L4
17
L4
SO
Vec
16
Vee
SI
LO
L1
L3
10
15
L2
11
14
L1
12
13
Top View
Top View
I\)
I\)
o
......
o
o
19
18
SK
L3
o"'D
U1
L5
L2
~
o
......
o
"'D
I\)
I\)
en
o
......
o
o"'D
I\)
~
~
TL/DD/8422-3
Order Number COP225C·XXX/N
or COP245C·XXXIN
See NS Molded Package Number N24A
TL/DD/8422-2
Order Number COP226C·XXX/N
See NS Molded Package Number N20A
Order Number COP225C·XXX/D
or COP245C·XXX/D
See NS Hermetic Package Number D24C
Order Number COP226C·XXX/D
See NS Hermetic Package Number D20A
o
......
o
o"'D
I\)
~
U1
o
Order Number COP226C·XXX/WM
See NS Surface Mount Package Number M20B
DIP
GND
DO
CKO
01
CKI
02
ifmT
03
L7
L6
L5
COP224C
COP244C
L4
IN1
PLCC
Q
N
Q
Q
0
8 is lS
8
I~
24
G3
23
G2
D3
L7
22
01
G3
L6
21
GO
G2
L5
20
IN3
Gl
L4
GO
INI
IN3
IN2
INO
vee
IN2
10
19
INO
VCC
L3
11
18
SK
12
17
SO
L2
13
16
SI
L1
14
15
LO
Top View
TL/DD/B422-13
TLlDD/8422-4
Order Number COP224C·XXX/V
or COP244C·XXX/V
See NS PLCC Package Number V28A
Order Number COP224C·XXX/N
or COP244C·XXX/N
See NS Molded Package Number N28B
Order Number COP224C·XXX/D
or COP244C·XXX/D
See NS Hermetic Package Number D28C
FIGURE 2
1·23
•
o
Ion
~
N
a.
Pin Descriptions
Pin
Description
Pin
Description
......
L7-LO
8·bit bidirectional
port with TRI·STATE
SK
Logic controlled
clock output
~
G3-GO
4·bit bidirectional
1/0 port
CKI
Chip oscillator input
CKO
Oscillator output,
HALT 1/0 port or
general purpose input
oo
o
~
N
a.
o
o
......
o
CD
D3-DO
4·bit output port
IN3-INO
4·bit input port
(28 pin package only)
RESET
Reset input
a.
SI
Serial input or
counter input
Vee
Most positive
power supply
......
SO
Serial or general
purpose output
GND
Ground
N
N
oo
o
Ion
N
N
a.
oo
......
o
~
N
N
a.
o
o
Functional Description
The internal architecture is shown in Figure 1. Data paths
are illustrated in simplified form to depict how the various
logic elements communicate with each other in implement·
ing the instruction set of the device. Positive logic is used.
When a bit is set, it is a logic "1", when a bit is reset, it is a
logic "0".
Caution:
The output options available on the COP224C/225C/226C
and COP244C/245C are not the same as those available
on the COP324C/325C/326C, COP344C/345C, COP424CI
425C/426C and COP444C/445C. Options not available on
the COP224C/225C/226C and COP244C/245C are: Option
2 value 2; Option 4 value 0; Option 5 value 1; Option 9 value
0; Option 17 value 1; Option 3D, Dual Clock, all values; Ope
tion 32, Microbus™, all values; Option 33 values 2, 4, and 6;
Option 34 all values; and Option 35 all values.
RAM addressing is implemented by a 7·bit B register whose
upper 3 bits (Br) select 1 of 8 data registers and lower 4 bits
(Bd) select 1 of 16 4·bit digits in the selected data register.
Data memory consists of a 256·bit RAM for the COP224CI
225C/226C, organized as 4 data registers of 16 x 4·bits
digits. The B register is 6 bits long. Upper 2 bits (Br) select 1
of 4 data registers and lower 4 bits (Bd) select 1 of 16 4·bit
digits in the selected data register. While the 4·bit contents
of the selected RAM digit (M) are usually loaded into or
from, or exchanged with, the A register (accumulator), it
may also be loaded into or from the Q latches or T counter
or loaded from the L ports. RAM addressing may also be
performed directly by the LDD and XAD instructions based
upon the immediate operand field of these instructions.
The Bd register also serves as a source register for 4·bit
data sent directly to the D outputs.
PROGRAM MEMORY
INTERNAL LOGIC
Program Memory consists of ROM, 1024 bytes for the
COP224C/225C/226C and 2048 bytes for the COP244CI
245C. These bytes of ROM may be program instructions,
constants or ROM addressing data.
ROM addressing is accomplished by an 11·bit PC register
which selects one of the 8·bit words contained in ROM. A
new address is loaded into the PC register during each in·
struction cycle. Unless the instruction is a transfer of control
instruction, the PC register is loaded with the next sequen·
tial 11·bit binary count value.
Three levels of subroutine nesting are implemented by a
three level deep stack. Each subroutine call or interrupt
pushes the next PC address into the stack. Each return
pops the stack back into the PC register.
The processor contains its own 4·bit A register (accumula·
tor) which is the source and destination register for most 1/0,
arithmetic, logic, and data memory access operations. It can
also be used to load the Br and Bd portions of the B regis·
ter, to load and input 4 bits of the 8·bit Q latch or T counter,
to input 4 bits of Lila ports data, to input 4·bit G, or IN
ports, and to perform data exchanges with the SIO register.
A 4·bit adder performs the arithmetic and logic functions,
storing the results in A. It also outputs a carry bit to the 1·bit
C register, most often employed to indicate arithmetic over·
flow. The C register in conjunction with the XAS instruction
and the EN register, also serves to control the SK output.
The 8·bit T counter is a binary up counter which can be
loaded to and from M and A using CAMT and CTMA instruc·
tions. This counter may be operated in two modes depend·
ing on a mask·programmable option: as a timer or as an
external event counter. When the T counter overflows, an
DATA MEMORY
Data memory consists of a 512·bit RAM for the COP244CI
245C, organized as 8 data registers of 16 x 4·bit digits.
1·24
o
Functional Description
o
(Continued)
'"C
overflow flag will be set (see SKT and IT instructions below).
The T counter is cleared on reset. A functional block diagram of the timer/counter is illustrated in Figure 7.
SIO. SO can be enabled to output the most significant bit
of SIO each cycle time. The SK outputs SKL ANDed with
the instruction cycle clock.
Four general-purpose inputs, IN3-INO, are provided.
1. With EN1 set, interrupt is enabled. Immediately following
an interrupt, EN1 is reset to disable further interrupts.
2. With EN2 set, the L drivers are enabled to output the data
in Q to the L I/O port. Resetting EN2 disables the L drivers, placing the L I/O port in a high-impedance input
state.
The D register provides 4 general-purpose outputs and is
used as the destination register for the 4-bit contents of Bd.
The G register contents are outputs to a 4-bit general-purpose bidirectional I/O port.
The Q register is an internal, latched, 8-bit register, used to
hold data loaded to or from M and A, as well as 8-bit data
from ROM. Its contents are outputted to the L I/O ports
when the L drivers are enabled under program control.
3. EN3, in conjunction with ENO, affects the SO output. With
ENO set (binary counter option selected) SO will output
the value loaded into EN3. With ENO reset (serial shift
register option selected), setting EN3 enables SO as the
output of the SIO shift register, outputting serial shifted
data each instruction time. Resctting EN3 with the serial
shift register option selected disables SO as the shift register output; data continues to be shifted through SIO and
can be exchanged with A via an XAS instruction but SO
remains set to "0".
The 8 L drivers, when enabled, output the contents of
latched Q data to the L I/O port. Also, the contents of L may
be read directly into A and M.
The SIO register functions as a 4-bit serial-in/serial-out shift
register for MICROWIRE I/O and COPS peripherals, or as a
binary counter (depending on the contents of the EN register). Its contents can be exchanged with A.
____~~_JI
L7-Lo, ----------....:.-""'-i,...-..;;;,;,;.;;,;..--~,..------.:....
CKOG3-GO,
& SIINPUTS
_ _ _ _ _ _ _ _ _ _ _ _"-_ _ _ _ _...,j"-_ _ _ _ _ __
l-tPoo-~
G3-GO.03-00.
L7-lo. SD. SK
OUTPUTS
,
_
VOL
TLlDD/8422-5
FIGURE 3. Input/Output Timing Diagrams (divide by 8 mode)
TABLE I. Enable Register Modes - Bits END and EN3
END EN3
0
0
0
1
1
0
1
1
510
Shift
Register
Shift
Register
Binary
Counter
Binary
Counter
U1
o.......
o
o'"C
I\)
I\)
en
o
.......
o
o
."
I\)
~
~
o
.......
o
o
~
U1
o
III
,
CKI
~~~
I\)
I\)
a. The interrupt, once recognized as explained below,
pushes the next sequential program counter address
(PC + 1) onto the stack. Any previous contents at the bottom of the stack are lost. The program counter is set to
hex address OFF (the last word of page 3) and EN1 is
reset.
b. An interrupt will be recognized only on the following conditions:
1. EN1 has been set.
2. A low-going pulse ("1" to "0") at least two instruction
cycles wide has occurred on the IN1 input.
3. A currently executing instruction has been completed.
O. The least significant bit of the enable register, ENO, selects the SIO register as either a 4-bit shift register or a
4-bit binary counter. With ENO set, SIO is an asynchronous binary counter, decrementing its value by one upon
each low-going pulse ("1" to "0") occurring on the SI
input. Each pulse must be at least two instruction cycles
wide. SK outputs the value of SKL. The SO output equals
the value of EN3. With ENO reset, SIO is a serial shift
register left shifting 1 bit each instruction cycle time. The
data present at SI goes into the least significant bit of
SK (AS A
CLOCK) _ _.........-..j
o
o'"C
I\)
The following features are associated with interrupt procedure and protocol and must be considered by the programmer when utilizing interrupts.
EN is an internal 4-bit register loaded by the LEI instruction.
The state of each bit of this register selects or deselects the
particular feature associated with each bit of the EN register:
~
o
.......
."
INTERRUPT
The XAS instruction copies C into the SKL latch. In the
counter mode, SK is the output of SKL; in the shift register
mode, SK outputs SKL ANDed with the clock.
I\)
I\)
51
50
5K
Input to Shift
0
If SKL = 1,SK = clock
If SKL=O,SK=O
Register
Input to Shift Serial If SKL = 1,SK = clock
Register
out If SKL=O,SK=O
Input to
SK=SKL
0
Counter
Input to
SK=SKL
1
Counter
' - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-----1
1-25
oU)
"'1:1'
o'"
r:a..
o.......
o
"'1:1'
"'1:1'
'"
o
r:a..
o
.......
o
CD
'"
r:a..
o'"
o
.......
o
U)
'"
'"
r:a..
o
o.......
o"'1:1'
'"
r:a..
'"
o
o
Functional Description
(Continued)
4. All successive transfer of control instructions and successive LBls have been completed (e.g. if the main
program is executing a JP instruction which transfers
program control to another JP instruction, the interrupt
will not be acknowledged until the second JP instruction has been executed).
TIMER
There are two modes selected by mask option:
a. Time-base counter. In this mode, the instruction cycle frequency generated from CKI passes through a 2-bit divideby-4 prescaler. The output of this prescaler increments
the 8-bit T counter thus providing a 10-bit timer. The prescaler is cleared during execution of a CAMT instruction
and on reset.
c. Upon acknowledgement of an interrupt, the skip logic
status is saved and later restored upon popping of the
stack. For example, if an interrupt occurs during the execution of ASC (Add with Carry, Skip on Carry) instruction
which results in carry, the skip logic status is saved and
program control is transferred to the interrupt servicing
routine at hex address OFF. At the end of the interrupt
routine, a RET instruction is executed to pop the stack
and return program control to the instruction following the
original ASC. At this time, the skip logic is enabled and
skips this instruction because of the previous ASC carry.
Subroutines should not be nested within the interrupt
service routine, since their popping of the stack will enable any previously saved main program skips, interfering
with the orderly execution of the interrupt routine.
d. The instruction
a~ hex
For example, using a 3.58 MHz crystal with a divide-by-16
option, the instruction cycle frequency of 223.70 kHz increments the 1O-bit timer every 4.47 p,s. By presetting the
counter and detecting overflow, accurate timeouts between 17.88 p,s (4 counts) and 4.577 ms (1024 counts)
are possible. Longer timeouts can be achieved by accumulating, under software control, multiple overflows.
b. External event counter. In this mode, a low-going pulse
("1" to "0") at least 2 instruction cycles wide on the IN2
input will increment the 8-bit T counter.
Note: The IT instruction is not allowed in this mode.
H
address OFF must be a Nap.
e. An LEI instruction may be put immediately before the
RET instruction to re-enable interrupts.
A
CKI
INITIALIZATION
The internal reset logic will initialize the device upon powerup if the power supply rise time is less than 1 ms and if the
operating frequency at CKI is greater than 32 kHz, otherwise the external RC network shown in Figure 4 must be
connected to the RESET pin (the conditions in Figure 4
must be met). The RESET pin is configured as a Schmitt
trigger input. If not used, it should be connected to Vee.
Initialization will occur whenever a logic "0" is applied to the
RESET input, providing it stays low for at least three instruction cycle times.
CKO
R2
..
.
~
R1
~
~~ C2
J-:::::t
1/1
C
~C1
p +
0
:~ ~~
E
R
f
T . . . VCC
~ HALT
J;
GENERAr~URPOSE
INPUT
U
P
P
::~
L
y
TLIDD/8422-7
I
Vee
Crystal or Resonator
RESEf COP244CI
224C
S
Crystal
Value
R1
R2
C1(pF)
C2(pF)
32 kHz
455 kHz
2.096 MHz
3.6 MHz
220k
5k
2k
1k
20M
10M
1M
1M
30
80
30
30
6-36
40
6-36
6-36
GNO
I
-
CKO
CKI
-==-
Note: If CKI clock is less than 32 kHz, the internal reset logic (option
# 29 = 1) MUST be disabled and the external RC circuit must be used.
w
HALT
OR
GENERAL PURPOSE
INPUT
JlJ
EXTERNAL
CLOCK
RC~5X POWER SUPPLY RISE
RC~100X CKI PERIOD.
TIME
AND
Component Values
TL/DD/8422-6
FIGURE 4. Power-Up Circuit
RC Controlled Oscillator
Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, 0, EN, IL, T and G registers are
cleared. The SKL latch is set, thus enabling SK as a clock
output. Data Memory (RAM) is not cleared upon initialization. The first instruction at address 0 must be a CLRA
(clear A register).
R
C
Cycle
Time
3Dk
82 pF
6-18 p,s
Vee
~4.5V
Note: 15k,,;;R,,;;150k
50 pF,,;;C";;150 pF
FIGURE 5. Oscillator Component Values
1-26
~-----------------------------------------------------------------.o
Functional Description
o"a
(Continued)
the external driver returns to high impedance state.
By forcing a low level to CKO, the chip will continue
and CKO will stay low.
HALT MODE
The COP244C/245C/224C/225C/226C is a FULLY STATIC circuit; therefore, the user may stop the system oscillator
at any time to halt the chip. The chip may also be halted by
the HALT instruction or by forcing CKO high when it is
mask-programmed as a HALT I/O port. Once in the HALT
mode, the internal circuitry does not receive any clock signal and is therefore frozen in the exact state it was in when
halted. All information is retained until continuing. The chip
may be awakened by one of two different methods:
•
OSCILLATOR OPTIONS
There are three basic clock oscillator configurations available as shown by Figure 5.
a. Crystal Controlled Oscillator. CKI and CKO are connected to an external crystal. The instruction cycle time equals
the crystal frequency optionally divided by 4, 8 or 16.
• Continue function: by forcing CKO low, if it mask-programmed as a HALT I/O port, the system clock is re-enabled and the circuit continues to operate from the point
where it was stopped.
• Restart: by forcing the RESET pin low (see Initialization).
The HALT mode is the minimum power dissipation state.
CKO PIN OPTIONS
a. Two-pin oscillator-(Crystal). See Figure 6a.
~
o
.......
o
o"a
N
N
UI
o
.......
o
o"a
N
N
0)
o
.......
o
b. External Oscillator. The external frequency is optionally
divided by 4, 8 or 16 to give the instruction cycle time.
CKO is the HALT I/O port or a general purpose input.
o"a
c. RC Controlled Oscillator. CKI is configured as a single pin
RC controlled Schmitt trigger oscillator. The instruction
cycle equals the oscillation frequency divided by 4. CKO
is the HALT I/O port or a general purpose input.
o.......
Figure 7 shows the clock and timer diagram.
In a crystal controlled oscillator system, CKO is used as
an output to the crystal network. The HALT mode may be
entered by program control (HALT instruction) which
forces CKO high, thus inhibiting the crystal network. The
circuit can be awakened only by forcing the RESET pin to
a logic "a .. (restart).
COP245C AND COP225C 24-PIN PACKAGE OPTION
N
~
~
o
o
"a
N
~
UI
o
If the COP244C/224C is bonded in a 24-pin package, it becomes the COP245C/225C, illustrated in Figure 2, Connection diagrams. Note that the COP245C/225C does not contain the four general purpose IN inputs (lN3-INO). Use of
this option precludes, of course, use of the IN options, interrupt feature, external event counter feature.
b. One-pin oscillator-(RC or external). See Figure 6b.
If a one-pin oscillator system is chosen, two options are
available for CKO:
•
As another option, CKO can be a general purpose input, read into bit 2 of A (accumulator) upon execution
of an INIL instruction.
N
N
Note: If user selects the 24·pin package, options 9, 10, 19 and 20 must be
selected as a "2"'. See option list.
CKO can be selected as the HALT I/O port. In that
case, it is an I/O flip-flop which is an indicator of the
HALT status. An external signal can over-ride this pin
to start and stop the chip. By forcing a high level to
CKO, the chip will stop as soon as CKI is high and
CKO output will stay high to keep the chip stopped if
COP226C 20-PIN PACKAGE OPTION
If the COP225C is bonded as 20-pin device it becomes the
COP226C. Note that the COP226C contains all the
COP225C pins except 00,01, Go, and G1•
Block Diagram
III
TO CLOCK GENERATOR
HALT
INSTRUCTION
TL/DD/B422-B
FIGURE 6a. Halt Mode-Two-Pin Oscillator
1-27
o
it)
"'I::t
N
a.
o
o
......
o
"'I::t
Block Diagrams (Continued)
- H-A-LT-I -0-P-ORo()lj:P~T I . c~o AC UMU~T"
"'I::t
N
a.
oo
......
o
(D
HALT
INSTRUCTION
N
N
a.
o
o
......
o
it)
I
--..""-.....---JOo...
Rmf - - - - - I L - . J
N
N
a.
o
o
......
o
"'I::t
N
N
TO CLOCK GENERATOR
CKI
TL/DD/8422-9
FIGURE 6b. Halt Mode-One-Pln Oscillator
a.
oo
TO SKT
LATCH
INSTRUCTION
CYCLE CLOCK
IT
TLIDD/8422-10
FIGURE 7. Clock and Timer
1-28
o
o"'C
Instruction Set
Table II is a symbol table providing internal architecture, instruction operand and operation symbols used in the instruction set table.
~
d
r
4-bit operand field, 0-15 binary (RAM digit select)
3(2)-bit operand field, 0-7(3) binary
(RAM register select)
a
11-bit operand field, 0-2047 (1023)
y
4-bit operand field, 0-15 (immediate data)
RAM (x) RAM addressed by variable x
ROM(x) ROM addressed by variable x
TABLE II. Instruction Set Table Symbols
Symbol
N
N
Instruction Operand Symbols
Definition
Internal Architecture Symbols
A
B
Br
4-bit accumulator
7.-bit RAM address register (6-bit for COP224C)
Upper 3 bits of B (register address)
(2-bit for COP224C)
Bd
Lower 4 bits of B (digit address)
C
1-bit carry register
D
4-bit data output port
EN
4-bit enable register
G
4-bit general purpose I/O port
IL
two 1-bit (lNO and IN3) latches
IN
4-bit input port
L
8-bitTRI-STATE I/O port
M
4-bit contents of RAM addressed by B
PC
11-bit ROM address program counter
Q
8-bit latch for L port
SA,SB,SC 11-bit 3-level subroutine stack
SIO
4-bit shift register and counter
SK
Logic-controlled clock output
SKL
1-bit latch for SK output
T
8-bit timer
Mnemonic
Operand
30
o
~
.........
=
A
ED
:
N
~
~
o
......
o
o"'C
N
~
en
o
Table III provides the mnemonic, operand, machine code
data flow, skip conditions and description of each instruction.
Skip
Conditions
Data Flow
Description
A+C+RAM(B)
~
A
Carry
Add with Carry, Skip on
Carry
ADD
31
100111 0001 1
A+RAM(B)~A
None
Add RAMtoA
ADT
4A
10100110101
A+1010~A
None
Add Ten to A
5-
10101 1 y 1
A+y~A
Carry
Add Immediate. Skip on
Carry (y =1= 0)
10
10001100001
A+RAM(B)+C~ A
Carry
Complement and Add with
Carry, Skip on Carry
CASC
Y
o"'C
o"'C
Plus
Minus
Replaces
Is exchanged with
Is equal to
One's complement of A
Exclusive-or
Range of values
+
Carry~C
AISC
o
......
o
0)
Machine
Language
Code
(Binary)
10011100001
N
N
en
o
......
Operational Symbols
ARITHMETIC INSTRUCTIONS
ASC
"'C
N
N
TABLE III. COP244C/245C Instruction Set
Hex
Code
o
......
o
o
Carry~
C
CLRA
00
10000100001
O~A
None
Clear A
COMP
40
10100100001
A~A
None
Ones complement of A to A
NOP
44
10100101001
None
None
No Operation
RC
32
10011100101
"O"~C
None
ResetC
SC
22
10010100101
"1"~C
None
SetC
XOR
02
10000100101
A E9 RAM (B)
None
Exclusive-OR RAM with A
1-29
~
A
o
it)
•
N
Instruction Set (Continued)
D-
O
TABLE III. COP244C/245C Instruction Set (Continued)
o
.......
o
•D-•
Mnemonic
N
Operand
Hex
Code
O
o
.......
o
CD
JID
D-
JMP
N
N
ROM (PC10:a A,M) -+ PC7:0
None
Jump Indirect (Notes 1, 3)
a
6-
10110101 ajQ"el
a-+PC
None
Jump
a
---
JP
a-+ PC6:0
None
Jump within Page (Note 4)
D-
~
o
~
~
(pages 2, 3 only)
or
--
O
o
.......
•
Description
11111111111
N
N
N
Skip
Conditions
FF
it)
o
DataFlow
TRANSFER CONTROL INSTRUCTIONS
O
o
(3
Machine
Language
Code
(Binary)
JSRP
a
JSR
a
--
111 1 aQ"Q 1
(all other pages)
a-+ PCs:o
110 1 aQ"Q 1
PC + 1 -+ SA -+ 58 -+ SC
00010 -+ PC10:6
a-+ PCs:o
None
Jump to Subroutine Page
(Note 5)
10110111ajQ"el
PC+1 -+ SA -+ 58 -+ SC
a-+PC
None
Jump to Subroutine
L!z:lLJ
o
6-
-RET
48
1010011000 I
SC-+ 58 -+ SA -+ PC
None
Return from Subroutine
RETSK
49
10100110011
SC -+ 58 -+ SA -+ PC
Always Skip
on Return
Return from Subroutine
then Skip
HALT
33
38
33
39
1001110011 I
10011 11000 I
1001110011 I
10011 11001 I
None
HALT Processor
None
IDLE till Timer
Overflows then Continues
IT
MEMORY REFERENCE INSTRUCTIONS
33
3F
1001110011 I
10011 11111 I
A -+ T7:4
RAM(8) -+ T3:0
None
Copy A, RAM to T
CTMA
33
2F
10011100111
1001011111 I
T7:4 -+ RAM(8)
T3:0 -+ A
None
Copy T to RAM, A
CAMO
33
3C
1001110011 I
10011111001
A-+ 07:4
RAM(8) -+ 03:0
None
Copy A, RAM to 0
COMA
33
2C
1001110011 I
10010111001
07:4 -+ RAM(8)
03:0-+ A
None
Copy 0 to RAM, A
-5
100 Ir 10101 1
(r=0:3)
RAM(8)-+A
8rEllr -+ 8r
None
Load RAM into A,
Exclusive-OR 8r with r
23
1001010011 I
10 I r I d I
RAM(r,d) -+ A
None
--
Load A with RAM pointed
to directly by r,d
8F
11011111111
ROM(PC10:a,A,M) -+ 0
S8-+SC
None
Load 0 Indirect (Note 3)
CAMT
LD
LDD
r
r,d
LOID
RM8
0
1
2
3
4C
45
42
43
1010011100 I
1010010101 I
10100100101
10100100111
0-+
0-+
0-+
0-+
RAM(8)0
RAM(8)1
RAM(8)2
RAM(8)3
None
Reset RAM 8it
SM8
0
1
2
3
4D
47
46
48
10100111011
1010010111 I
10100101101
10100110111
1 -+
1 -+
1 -+
1 -+
RAM(8)0
RAM(8)1
RAM(8)2
RAM(8)3
None
Set RAM 8it
1-30
o
o"0
Instruction Set (Continued)
N
N
TABLE III. COP244C/245C Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
Machine
Language
Code
(Binary)
Skip
Conditions
Data Flow
.1=10
o
......
o
Description
o"0
N
N
U1
MEMORY REFERENCE INSTRUCTIONS (Continued)
STII
y
7-
10111 1
X
r
-6
1001 r 101101
(r=0:3)
XAD
r,d
XDS
r
XIS
r
Y..
I
y~
RAM(B)
Bd+ 1 ~ Bd
None
Store Memory Immediate
1 and Increment Bd
RAM(B)~A
None
Exchange RAM with A,
Exclusive-OR Br with r
Br E9 r
~
Br
o
......
o
o"0
N
N
0)
o
......
o
23
1001010011 I
11 I r 1 d I
RAM(r,d)~A
None
Exchange A with RAM
Pointed to Directly by r,d
-7
100 Ir I0111
(r=0:3)
RAM(B)~
Bd
decrements
past 0
Exchange RAM with A
and Decrement Bd.
Exclusive-OR Br with r
o
......
Bd+1 ~ Bd
Br E9 r ~ Br
Bd
increments
past 15
Exchange RAM with A
and Increment Bd,
Exclusive-OR Br with r
.1=10
U1
--
-4
I
A
Bd-1 ~ Bd
Br E9 r ~ Br
100 1 r 10100 I
(r=0:3)
RAM(B)~A
o"0
N
.1=10
.1=10
o
o"0
N
o
REGISTER REFERENCE INSTRUCTIONS
CAB
50
10101100001
A~Bd
None
Copy A to Bd
CBA
4E
1010011110 I
Bd~A
None
Copy BdtoA
100Irl(d-1)1
(r=0:3:
d=O,9:15)
or
10011 10011 I
111 r i d 1
(any r, any d)
r,d~B
Skip until
not a LBI
Load B Immediate with r,d
(Note 6)
33
6-
10011100111
10110 1 Y.. I
y~EN
None
Load EN Immediate (Note 7)
12
10001100101
A~Br
None
Exchange A with Br (Note 8)
SKC
20
10010100001
C="1"
Skip if C is True
SKE
21
10010100011
A=RAM(B)
Skip if A Equals RAM
SKGZ
33
21
10011 10011 I
10010100011
G3:0=0
Skip if G is Zero
(all 4 bits)
LBI
r,d
-33
-LEI
Y
XABR
TEST INSTRUCTIONS
SKGBZ
SKMBZ
SKT
0
1
2
3
33
01
11
03
13
1000110001 I
1000010011 I
10001100111
0
1
2
3
01
11
03
13
10000100011
10001100011
10000100111
10001100111
41
1010010001
10011100111
Skip if G Bit is Zero
1st byte
10000100011 )
2nd byte
I
1-31
Go=O
G1=0
G2=0
G3=0
RAM(B)o=O
RAM(B)1 =0
RAM(B)2=0
RAM(Bb=O
Skip if RAM Bit is Zero
A time-base
counter carry
has occurred
since last test
Skip on Timer
(Note 3)
•
0
in
-..:t
N
a.
0
Instruction Set (Continued)
TABLE III. COP244C/245C Instruction Set (Continued)
0
0
"-..:t
-..:t
Mnemonic
N
Operand
a.
0
0
0
"CD
Hex
Code
Machine
Language
Code
(Binary)
Data Flow
Skip
Conditions
Description
INPUTIOUTPUT INSTRUCTIONS
ING
33
2A
10011100111
10010110101
G~A
None
Input G Ports to A
ININ
33
28
10011100111
10010110001
IN~A
None
Input IN Inputs to A
(Note 2)
N
N
INIL
33
29
10011100111
10010110011
IL3, CKO, "0", ILo ~ A
None
Input IL Latches to A
(Note 3)
0
INL
33
2E
10011 10011 1
10010111101
L7:4 ~ RAM(8)
None
Input L Ports to RAM,A
33
3E
10011100111
10011 11110 1
8d~D
None
Output 8d to D Outputs
33
10011 10011 1
10101 1 y 1
y~G
None
5-
Output to G Ports
Immediate
OMG
33
3A
10011100111
10011110101
RAM(8)~G
None
Output RAM to G Ports
XAS
4F
1010011111 1
A +--+ SIO, C ~ SKL
None
Exchange A with SIO
(Note 3)
N
N
a.
0
0
0
"
in
a.
0
"0-..:t
N
N
a.
0
0
OBD
OGI
y
L3:0~A
Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to N where
o signifies the least significant bit (low-order, right-most bit). For example, A3 indicates the most significant (left-most) bit of the 4-bit A register.
Note 2: The ININ instruction is not available on the 24-pin packages since these devices do not contain the IN inputs.
Note 3: For additional information on the operation of the XAS, JID, LaiD, INIL, and SKT instructions, see below.
Note 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction,
otherwise, permits a jump to a ROM location within the current 54-word page. JP may not jump to the last word of a page.
Note 5: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P)_ A JSRP may not be used when in pages 2 or 3. JSRP
may not jump to the last word in page 2.
Note 6: LBI is a single-byte instruction if d = 0, 9, 10, 11, 12, 13, 14, or 15. The machine code for the lower 4 bits equals the binary value of the "d" data minus 1,
e.g., to load the lower four bits of B(Bd) with the value 9 (10012), the lower 4 bits of the LBI instruction equal 8 (10002)' To load 0, the lower 4 bits of the LBI
instruction should equal 15 (11112)'
Note 7: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a "1" or "0" in each bit of EN corresponds
with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
Note 8: For 2K ROM devices, A -
Br (0 -
A3). For 1K ROM devices, A -
Br (0,0 -
1·32
A3, A2).
o
o-a
Description of Selected Instructions
pulse stays low for at least two instruction cycles. Execution
of an INIL inputs IL3 and ILO into A3 and AO respectively,
and resets these latches to allow them to respond to subsequent low-going pulses on the IN3 and INO lines. If CKO is
mask programmed as a general purpose input, an INIL will
input the state of CKO into A2. If CKO has not been so
programmed, a "1" will be placed in A2. AO is input into A1.
IL latches are cleared on reset. IL latches are not available
on the COP245C/225C, and COP226C,
XAS INSTRUCTION
XAS (Exchange A with SIO) copies C to the SKL latch and
exchanges the accumulator with the 4-bit contents of the
SIO register. The contents of SIO will contain serial-in/seriai-out shift register or binary counter data, depending on the
value of the EN register. If SIO is selected as a shift register,
an XAS instruction can be performed once every 4 instruction cycles to effect a continuous data stream.
LQID INSTRUCTION
INSTRUCTION SET NOTES
a. The first word of a program (ROM address 0) must be a
CLRA (Clear A) instruction.
LQID (Load Q Indirect) loads the a-bit Q register with the
contents of ROM pointed to by the 11-bit word
PC10:PCa,A,M. LQID can be used for table lookup or code
conversion such as BCD to seven-segment. The LQI D instruction "pushes" the stack (PC + 1 ~ SA ~ SB ~ SC)
and replaces the least significant a bits of the PC as follows:
A ~ PC7:4, RAM (B) ~ PC3:0, leaving PC10, PC9 and
PCS unchanged. The ROM data pointed to by the new address is fetched and loaded into the Q latches. Next, the
stack is "popped" (SC ~ SB ~ SA ~ PC), restoring the
saved value of PC to continue sequential program execution. Since LQID pushes SB ~ SC, the previous contents
of SC are lost.
b. Although skipped instructions are not executed, they are
still fetched from the program memory. Thus program
paths take the same number of cycles whether instructions are skipped or executed except for JID, and LQID.
c. The ROM is organized into pages of 64 words each. The
Program Counter is a 11-bit binary counter, and will count
through page boundaries. If a JP, JSRP, JID, or LaiD is
the last word of a page, it operates as if it were in the next
page. For example: a JP located in the last word of a
page will jump to a location in the next page. Also, a JID
or LQID located in the last word of every fourth page (Le.
hex address OFF, 1FF, 2FF, 3FF, 4FF, etc.) will access
data in the next group of four pages.
Note: LQID uses 2 instruction cycles if executed, one if skipped.
JID INSTRUCTION
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location pointed
to indirectly by A and M. It loads the lower S bits of the ROM
address register PC with the contents of ROM addressed by
the 11-bit word, PC10:S,A,M. PC10,PC9 and PCS are not
affected by JID.
SKT INSTRUCTION
Note: If the most significant bit of the T counter is a 1 when a CAMT instruction loads the counter, the overflow flag will be set. The following
sample of codes should be used when loading the counter:
; load T counter
; skip if overflow flag is set and reset it
o
o-a
~
~
U1
o
.......
o
o-a
~
~
Q)
o
.......
o
o-a
~
~
~
o
.......
o
o-a
~
~
U1
o
Power Dissipation
The lowest power drain is when the clock is stopped. As the
frequency increases so does current. Current is also lower
at lower operating voltages. Therefore, the user should run
at the lowest speed and voltage that his application will allow. The user should take care that all pins swing to full
supply levels to insure that outputs are not loaded down and
that inputs are not at some intermediate level which may
draw current. Any input with a slow rise or fall time will draw
additional current. A crystal or resonator generated clock
input will draw additional current. For example, a 500 kHz
crystal input will typically draw 100 p.,A more than a squarewave input. An R/C oscillator will draw even more current
since the input is a slow rising signal.
The SKT (Skip On Timer) instruction tests the state of the T
counter overflow latch (see internal logic, above), executing
the next program instruction if the latch is not set. If the
latch has been set since the previous test, the next program
instruction is skipped and the latch is reset. The features
associated with this instruction allow the processor to generate its own time-base for real-time processing, rather than
relying on an external input signal.
SKT
o
.......
Note: The COP224C/225C/226C needs only 10 bits to address its ROM.
Therefore, the eleventh bit (P1 0) is ignored.
Note: JID uses 2 instruction cycles if executed, one if skipped.
CAMT
~
~
~
If using an external squarewave oscillator, the following
equation can be used to calculate operating current drain.
Ico=lo+VX70XFi+VX2400XFi/Dv where:
Ico = chip operating current drain in microamps
10 = quiescent leakage current (from curve)
Fi = CKI frequency in MegaHertz
V=chip Vcc in volts
Dv = divide by option selected
NOP
IT INSTRUCTION
The IT (idle till timer) instruction halts the processor and
puts it in an idle state until the time-base counter overflows.
This idle state reduces current drain since all logic (except
the oscillator and time base counter) is stopped. IT instruction is not allowed if the T counter is mask-programmed as
an external event counter (option #31 = 1).
For example at 5 volts Vcc and 400 kHz (divide by 4)
Ico= 120+ 5X70X0.4+ 5X2400X0.4/4
INIL INSTRUCTION
Ico= 120+ 140+ 1200= 1460 p.,A
INIL (Input IL Latches to A) inputs 2 latches, IL3 and ILO,
CKO and 0 into A. The IL3 and ILO latches are set if a lowgoing pulse ("1" to "Ott) has occurred on the IN3 and INO
inputs since the last INIL instruction, provided the input
1-33
III
o
Lt)
"11:1'
Power Dissipation
D.
If an IT instruction is executed, the chip goes into the IDLE
mode until the timer overflows. In IDLE mode, the current
drain can be calculated from the following equation:
C\I
oo
"o
"11:1'
"11:1'
(Continued)
1/0 OPTIONS
Outputs have the following optional configurations, illustrated in Figure 8:
Ici= la+Vx70XFi
a. Standard - A CMOS push-pull buffer with an N-channel
device to ground in conjunction with a P-channel device
to Vee, compatible with CMOS and LSTTL.
C\I
D.
oo
"-
o
CD
C\I
C\I
For example, at 5 volts Vee and 400 kHz
Ici=120+5x70x0.4=260 ,..,A
b. Open Drain - An N-channel device to ground only, allowing external pull-up as required by the user's application.
The total average current will then be the weighted average
of the operating current and the idle current:
c. Standard TAl-STATE L Output - A CMOS output buffer
similar to a. which may be disabled by program control.
D.
o
o
o
Lt)
To
Ti
Ita = leo x To+Ti + Ici x To+Ti
"C\I
C\I
D.
o
o
o
"11:1'
"C\I
C\I
where:
d. Open-Drain TRI-STATE L Output nel device to ground only.
This has the N-chan-
Ita = total average current
All inputs have the following option:
Ico = operating current
e. Hi-Z input which must be driven by the users logic.
Ici = idle current
All output drivers use two common devices numbered 1 to
2. Minimum and maximum current (lOUT and VOUT) curves
are given in Figure 9 for each of these devices to allow the
designer to effectively use these 110 configurations.
To = operating time
Ti = idle time
D.
o
o
b. Open-Drain Output
a. Standard Push-Pull Output
Vee
D~r.
C. Standard TRI-STATE
"L" Output
d. Open Drain TRI-STATE
"L" Output
FIGURE 8. Input/Output Configurations
1-34
e. Hi-Z Input
o
Power Dissipation
2.4
o"'a
(Continued)
I\)
I\)
Minimum Sink Current
(Except CKO)
1.2
Minimum Source Current
(Except CKO)
Maximum Quiescent Current
140
100
0.8
1.6
1.§ 1.2
0.8
I.~
V
1.0
/
--
1 0.6 ~ r--
5.5V
~ 4.5V
"..-
.Ii
0.4
~
............
j"...
0.2
2.0
3.0
4.0
5.0
-.......-
120
1.0
2.0
0.4
.c:a.
o
......
6.0
j
2.0
--
~ 60
'" '\
r-....
20
'\. i\
1.0
80
3.0
4.0
5.0
6.0
4.0
- l t5OC -
"'a
I\)
N
U1
o
......
I
o
_8~OC
i-7~OC
o"'a
_I- 250C
en
l--
--
I\)
I\)
I
6.0
5.0
VOH (VOLTS)
VOL (VOLTS)
-
o
o
Vee (VOLTS)
o
......
o
o"'a
I\)
TL/DO/8422-12
FIGURE 9. Input/Output Characteristics
o
o
Option List
"'a
The COP244C/245C/224C/225C/COP226C mask-programmable options are assigned numbers which correspond with the COP244C/224C pins.
I\)
.c:a.
Option 4: RESET input
U1
o
= 1: Hi-Z input
Option 5: L7 Driver
The following is a list of options. The options are programmed at the same time as the ROM pattern to provide
the user with the hardware flexibility to interface to various
I/O components using little or no external circuitry.
=0: Standard TRI-STATE push-pull output
=2: Open-drain TRI-STATE output
Caution:
The output options available on the COP224C/225C/226C
and COP244C/245C are not the same as those available
on the COP324C/325C/326C, COP344C/345C, COP424C/
425C/426C and COP444C/445C. Options not available on
the COP224C/225C/226C and COP244C/245C are: Option
2 value 2; Option 4 value 0; Option 5 value 1; Option 9 value
0; Option 17 value 1; Option 30, Dual Clock, all values; Option 32, Microbus, all values; Option 33 values 2 4, and 6;
Option 34 all values; and Option 35 all values.
Option 6: L6 Driver -
(same as option 5)
Option 7: L5 Driver -
(same as option 5)
Option 8: L4 Driver -
(same as option 5)
Option 9: IN1 input
= 1: Hi-Z input, mandatory for 28 Pin Package
= 2: Mandatory for 20 and 24 Pin Packages
Option 10: IN2 input -
(same as option 9)
Option 11 =0: Vee Pin - no option available
Option 12: L3 Driver - (same as option 5)
PLEASE FILL OUT THE OPTION TABLE on the next page.
Photocopy the option data and send it in with your disk or
EPROM.
Option 1 = 0: Ground Pin -
.c:a.
.c:a.
o
......
Option 13: L2 Driver -
(same as option 5)
Option 14: L1 Driver -
(same as option 5)
Option 15: LO Driver -
no options available
Option 16: SI input -
Option 2: CKO Pin
(same as option 5)
(same as option 4)
Option 17: SO Driver
= 0: clock generator output to crystal/resonator
= 1: HALT I/O port
= 0: Standard push-pull output
= 2: Open-drain output
= 3: general purpose input, high-Z
Option 18: SK Driver -
(same as option 17)
Option 19: INO Input -
(same as option 9)
= 0: Crystal controlled oscillator input divide by 4
Option 20: IN3 Input -
(same as option 9)
= 1: Crystal controlled oscillator input divide by 8
= 2: Crystal controlled oscillator input divide by 16
Option 21: GO I/O Port Option 22: G1 I/O Port -
(same as option 17)
(same as option 17)
= 4: Single-pin RC controlled oscillator (divide by 4)
Option 23: G2 I/O Port -
(same as option 17)
= 5: External oscillator input divide by 4
Option 24: G3 I/O Port -
= 6: External oscillator input divide by 8
Option 25: D3 Output -
(same as option 17)
= 7: External oscillator input divide by 16
Option 26: D2 Output -
(same as option 17)
Option 27: D1 Output -
(same as option 17)
Option 3: CKI input
1-35
(same as option 17)
o
Lt)
~
C'II
D.
o
o
.......
o
~
~
C'II
D.
o
o
.......
o
CD
C'II
C'II
D.
o
Option List (Continued)
Option 28: DO Output -
Option 33: COP bonding. See note.
(same as option 17)
(1 k and 2k Microcontroller)
Option 29: Internal Initialization Logic
= 0: Normal operation
= 0: 28-pin package
= 1: No internal initialization logic
= 1: 24-pin package
Option 30 = 0: No Option Available
(1 k Microcontroller only)
Option 31: Timer
= 3: 20-pin package
= 0: Time-base counter
= 5: 24- and 20-pin package
Note:-If opt. #33=0 then opt. #9, 10, 19, and 20
must= 1.
= 1: External event counter
Option 32 = 0: No Option Available
o
.......
o
Lt)
If opt. #33=1 then opt. #9,10,19 and 20 must=2, and
option #31 must= O.
C'II
C'II
If opt. #33=3 or 5 then opt. #9, 10, 19,20 must=2 and
opt. #21,22,31 must=O.
o
Option 34 = 0: No Option Available
D.
o
.......
o
~
C'II
C'II
Option 35 = 0: No Option Available
D.
Option Table
o
The following option information is to be sent to National along with the EPROM.
o
OPTION DATA
OPTION
1 VALUE =
OPTION
0
OPTION DATA
IS: GROUND PIN
OPTION 19 VALUE =
IS: INO INPUT
2 VALUE =
IS:CKOPIN
OPTION 20 VALUE =
IS: IN3 INPUT
OPTION
3 VALUE =
IS: CKIINPUT
OPTION 21 VALUE =
IS: GO I/O PORT
OPTION
4 VALUE =
IS: RESET INPUT
OPTION 22 VALUE =
IS: G1 I/O PORT
OPTION
5 VALUE =
IS: L7 DRIVER
OPTION 23 VALUE =
IS: G2 1/0 PORT
OPTION
6 VALUE =
IS: L6 DRIVER
OPTION 24 VALUE =
IS: G3 1/0 PORT
OPTION
7 VALUE =
IS: L5 DRIVER
OPTION 25 VALUE =
IS: 03 OUTPUT
OPTION
8 VALUE =
IS: L4 DRIVER
OPTION 26 VALUE =
IS: 02 OUTPUT
OPTION
9 VALUE =
IS: IN1 INPUT
OPTION 27 VALUE =
IS: 01 OUTPUT
OPTION 10 VALUE =
IS: IN21NPUT
OPTION 28 VALUE =
IS: DO OUTPUT
IS: VCC PIN
OPTION 29 VALUE =
IS: INT INIT LOGIC
OPTION 12 VALUE =
IS: L3 DRIVER
OPTION 30 VALUE =
OPTION 13 VALUE =
IS: L2 DRIVER
OPTION 31 VALUE =
OPTION 14 VALUE =
IS: L 1 DRIVER
OPTION 32 VALUE =
OPTION 15 VALUE =
IS: LO DRIVER
OPTION 33 VALUE =
OPTION 16 VALUE =
IS: SIINPUT
OPTION 34 VALUE =
0
IS: NIA
OPTION 17 VALUE =
IS: SO DRIVER
OPTION 35 VALUE =
0
IS: NIA
OPTION 18 VALUE =
IS: SK DRIVER
OPTION 11 VALUE =
0
1-36
0
IS:N/A
IS: TIMER
0
IS: NIA
IS: COP BONDING
o
o
~National
"tJ
0l:Io
.....
o
o
.....
o
o"tJ
0l:Io
.....
.....
D Semiconductor
COP41 OC/COP411 C/COP31 OC/COP311 C
Single-Chip CMOS Microcontrollers
o
.....
o
General Description
Features
The COP410C, COP411C, COP310C, and COP311C fully
static, single-chip CMOS microcontrollers are members of
the COPSTM family, fabricated using double-poly, silicongate CMOS technology. These controller-oriented processors are complete microcomputers containing all system
timing, internal logic, ROM, RAM, and I/O necessary to implement dedicated: control functions in a variety of applications. Features include single supply operation, a variety of
output configuration options, with an instruction set, internal
architecture, and I/O scheme deSigned to facilitate keyboard input, display output, and BCD data manipulation. The
COP411 C is identical to the COP410C but with 16 I/O lines
instead of 20. They are an appropriate choice for use in
numerous human interface control environments. Standard
test procedures and reliable high-density fabrication techniques provide the medium to large volume customers with
a customized controller-oriented processor at a low endproduct cost.
• Lowest power dissipation (40 p.W typical)
The COP310C/COP311C is the extended temperature
range version of the COP41 OC/COP411 C.
The COP404C should be used for exact emulation.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
o"tJ
Low cost
Power-saving HALT Mode with Continue function
Powerful instruction set
512 x a ROM, 32 x 4 RAM
20 I/O lines (COP410C)
Two-level subroutine stack
DC to 4 p.s instruction time
Single supply operation (2.4V to 5.5V)
General purpose and TRI-STATE~ outputs
Internal binary counter register with MICROWIRETM
compatible serial I/O
LSTILICMOS compatible in and out
Software/hardware compatible with other members of
the COP400 family
Extended temperature (- 40°C to + a5°C) devices
available
The military temperature range devices (- 55°C to
+ 125°C) are specified on COP21 OC/211 C data sheet.
Block Diagram
SKI
r-------i-+-.:.:.. so
I
MICROWIRE I/O
SI
TLIDD/S015-1
FIGURE 1. COP410C
1-37
Co.)
.....
o
o
.....
o
o"tJ
.....
.....
Co.)
o
o
....
....
('I)
COP410C/COP411C
0.
o
o
o
C)
"-
....
('I)
0.
o
o
"o
....
....
~
Absolute Maximum Ratings
If Military I Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Supply Voltage
6V
Voltage at Any Pin
- 0.3V to Vee + 0.3V
Total Allowable Source Current
25mA
Total Allowable Sink Current
25mA
Operating Temperature Range
O°Cto + 70°C
Storage Temperature Range
- 65°C to + 150°C
Lead Temperature (Soldering, 10 sec.)
300°C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
0.
oo
......
o
C)
....
~
a.
oo
DC Electrical Characteristics O°C ~ TA ~ 70°C unless otherwise specified
Parameter
Conditions
Operating Voltage
Min
Max
Units
2.4
5.5
V
Power Supply RippleS
Supply Current
Vee = 2.4V, tc = 125,.,.s
Vee = 5.0V, tc = 16,.,.s
Vee = 5.0V, tc = 4 ,.,.s
(tc is instruction cycle time)
HALT Mode Current2
Vee
Vee
= 5.0V, FIN = 0 kHz
= 2.4V, FIN = a kHz
Input Voltage Levels
RESET, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
.Source (Standard
Option)
Source (Low
Current Option)
CKO Current Levels
(As Clock Out)
Sink
+4
+8
+16
Source
+4
+8
+16
p.A
p.A
p.A
30
10
p.A
,.,.A
0.1 Vee
V
V
0.2 Vee
V
V
+1
,.,.A
7
pF
0.4
V
V
0.2
V
V
-330
-80
mA
mA
mA
mA
p.A
p.A
0.7 Vee
-1
Hi-Z Input Leakage
Output Current Levels4
(Except CKO)
Sink
V
80
500
2000
0.9 Vee
Input CapaCitance
Output Voltage Levels
LSTTL Operation
Logic High
Logic Low
CMOS Operation
Logic High
Logic Low
0.1 Vee
Standard Outputs
Vee = 5.0V ±10%
IOH = -25,.,.A
IOL = 400,.,.A
IOH
IOL
2.7
= -10,.,.A
= 10,.,.A
Vee- 0.2
1.2
0.2
-0.5
-0.1
-30
-6
4.5V, VOUT = Vee
Vee
Vee
Vee
Vee
Vee
Vee
=
Vee
= 4.5V, CKI =
Vee, VOUT
Vee
= 4.5V, CKI
OV, VOUT
= 2.4V, VOUT = Vee
= 4.5V, VOUT = OV
= 2.4V, VOUT = OV
= 4.5V, VOUT = OV
= 2.4V, VOUT = OV
=
= Vee
= OV
Allowable Sink/Source
Current Per Pin 4
0.3
0.6
1.2
-0.3
-0.6
-1.2
mA
mA
mA
mA
mA
mA
5
1-38
mA
o
o"'0
COP41 OC/COP411 C
~
-&.
DC Electrical Characteristics
o
(Continued)
o
o
........
Parameter
Conditions
Min
Allowable Loading on CKO
(as HALT liD pin)
Max
Units
100
pF
0.6
1.6
Vee = 4.5V. VIN = 0.2 Vee
Vee = 4.5V. VIN = 0.7 Vee
TAl-STATE or Open Drain
Leakage Current
mA
mA
-2
+2
Jl-A
Note 4: SO output sink current must be limited to keep VOL less than 0.2 Vee when part is running in order to prevent entering test mode.
Note 5: Voltage change must be less than 0.5V in alms period.
Note 6: This parameter is only sampled and not 100% tested.
Note 7: Variation due to the device included.
COP410C/COP411C
AC Electrical Characteristics O°C :s: T A :s: 70°C unless otherwise specified
Min
Max
Units
Vee ~ 4.5V
4.5V > Vee ~ 2.4V
4
16
DC
DC
Jl-s
Jl-s
}
}
DC
DC
DC
DC
DC
DC
1.0
2.0
4.0
250
500
1.0
MHz
MHz
MHz
kHz
kHz
MHz
Jl-s
Conditions
Vee ~ 4.5V
4.5V
> Vee
~ 2.4V
Instruction Cycle Time
AC Oscillator?
A = 30k ± 5%. Vee = SV
C = 82 pF ± S% (+4 Mode)
8
16
DutyCycle6
fl = 4 MHz
40
60
%
AiseTime 6
fl = 4 MHz External Clock
60
ns
Fall Time 6
fl = 4 MHz External Clock
40
ns
Inputs (See Figure 3)
tSETUP
tHOLD
Output Propagation
Delay
tpD1. tpDO
tpD1. tpDO
G Inputs }
Sllnput
All Others
Vee ~ 4.SV
Vee ~ 2.4V
tc/4+0.7
Vee ~ 4.5V
VOUT = 1.5V. CL = 100 pF. RL = 5k
Vee:S: 4.SV
Vee:S: 2.4V
1-39
W
-&.
o
o
........
o"'0
W
o
Note 3: When forcing HALT, current is only needed for a short time (approximately 200 ns) to flip the HALT flip· flop.
Parameter
o"'0
-&.
-&.
Note 2: The Halt mode will stop CKI from oscillating in the RC and crystal configurations.
+4 mode
+8 mode
+ 16 mode
+4 mode
+8 mode
+ 16 mode
-&.
-&.
o
Note 1: Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI, CKO open, and all other pins pulled up to Vee with 5k
resistors. See current drain equation on page 13.
Operating CKI
Frequency
~
o
........
o
Current Needed to
Override HALT3
To Continue
To Halt
Instruction Cycle Time (td
o"'0
Jl-s
Jl-s
Jl-s
Jl-s
Jl-s
0.3
1.7
0.25
1.0
1.0
4.0
Jl-s
Jl-s
(.)
,....
,....
Cf)
COP310C/COP311C
D.
o
(.)
Ab~olute
(.)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
6V
Voltage at Any Pin
- 0.3V to Vee + 0.3V
Total Allowable Source Current
25mA
Total Allowable Sink Current
25mA
.......
o,....
Cf)
D.
o
(.)
.......
,....
,....
(.)
•
Maximum Ratings
Operating Temperature Range
- 40°C to + 85°C
Storage Temperature Range
- 65°C to + 150°C
Lead Temperature (Soldering, 10 sec.)
300°C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
D.
o(.)
.......
(.)
o
,....
•
o
DC Electrical Characteristics
Parameter
D.
Operating Voltage
(.)
Power Supply RippleS
-40·C :5: TA :5: + 85°C unless otherwise specified
Conditions
Supply Current
Vee = 3.0V, to = 125,....s
Vee = 5.0V, to = 16,....s
Vee = 5.0V, to = 4,....s
(to is instruction cycle time)
HALT Mode Current2
Vee
Vee
Input Voltage Levels
RESET,CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Max
3.0
5.5V
V
0.1 Vee
V
100
600
2500
,....A
,....A
,....A
50
20
,....A
,....A
0.1 Vee
V
V
0.2 Vee
V
V
+2
,...A
7
pF
0.4
V
V
0.2
V
V
-440
-200
mA
mA
mA
mA
,...A
,....A
= 5.0V, FIN = 0 kHz
= 3.0V, FIN = 0 kHz
"
0.9 Vee
0.7 Vee
-2
Hi-Z Input Leakage
Input Capacitance
Output Voltage Levels
LSTIL Operation
Logic High
Logic Low
CMOS Operation
Logic High
Logic Low
Output Current Levels4
(Except CKO)
Sink
Source (Standard
Option)
Source (Low
Current Option)
CKO Current Levels
(As Clock Out)
Sink
+4
+8
+16
Source
+4
+8
+16
Units
Min
Standard Outputs
Vee = 5.0V ±10%
10H = -25,....A
101: = 400,....A
10H
IOL:
2.7
= -10,....A
= 10,....A
Vee- 0.2
Vee
Vee
Vee
Vee
Vee
Vee
= 4.5V, VOUT = Vee
= a.ov, YOUT = Vee
= 4.5V, VOUT = OV
= a.ov, VOUT = OV
= ~.5V, VOUT = OV
= 3.0V, VOUT = OV
1.2
0.2
-0.5
-0.1
-30
-8
Vee
= 4.5V, CKI = Vee, VOUT = Vee
Vee
= 4.5V, CKI = OV, VOUT = OV
0.3
0.6
1.2
-0.3
-0.6
-1.2
..
Allowable SinklSource
Current Per Pin 4
mA
mA
mA
mA
mA
mA
5
1-40
mA
o
o-0
COP310C/COP311C
....o
~
DC Electrical Characteristics
(Continued)
Parameter
Conditions
Min
Allowable Loading on CKO
(as HALT I/O pin)
Max
Units
100
pF
-4
0.8
2.0
rnA
rnA
+4
JlA
Note 1: Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI. CKO open. and all other pins pulled up to Vee with 5k
resistors. See current drain equation on page 13.
Note 2: The Halt mode will stop CKI from oscillating in the RC and crystal configurations.
Note 3: When forcing HALT. current is only needed for a short time (approximately 200 ns) to flip the HALT flip-flop.
Note 4: SO output sink current must be limited to keep VOL less than 0.2 Vee when part is running in order to prevent entering test mode.
Note 5: Voltage change must be less than 0.5V in alms period.
Note 6: This parameter is only sampled and not 100% tested.
Note 7: Variation due to the device included.
COP310C/COP311C
AC Electrical Characteristics
- 40°C ~ T A ~ + 85°C unless otherwise specified
Parameter
+4 mode
+8 mode
+16 mode
+4 mode
+8 mode
+16 mode
Conditions
Min
Max
Units
Vee ~ 4.5V
4.5V> Vee ~ 3.0V
4
16
DC
DC
Jls
Jls
}
}
DC
DC
DC
DC
DC
DC
1.0
2.0
4.0
250
500
1.0
MHz
MHz
MHz
kHz
kHz
MHz
8
16
Jls
40
60
%
Vee ~ 4.5V
4.5V> Vee ~ 3.0V
Instruction Cycle Time
RC Oscillator7
R = 30k ±5%. Vee = 5V
C = 82 pF ±5% (+4 Mode)
DutyCycle 6
fl = 4 MHz
Rise Time 6
fl = 4 MHz External Clock
60
ns
Fall Time 6
fl = 4 MHz External Clock
40
ns
Inputs (See Figure 3)
tSETUP
tHOLD
Output Propagation
Delay
tpDl. tpDO
tpDl. tpDO
....
....
~
o
Vee ~~ 4.5V. VIN = 0.2 Vee
Vee = 4.5V. VIN = 0.7 Vee
TRI-ST ATE or Open Drain
Leakage Current
Operating CKI
Frequency
o"tJ
o
.......
Current Needed to
Override HALT3
To Continue
To Halt
Instruction Cycle Time (tel
o
.......
o
G Inputs }
Sllnput
All Others
Vee ~ 4.5V
Vee ~ 3.0V
Vee ~ 4.5V
VOUT = 1.5V. CL = 100 pF. RL = 5k
Vee ~ 4.5V
Vee ~ 3.0V
1-41
tc/4+ 0.7
0.3
1.7
0.25
1.0
Jls
Jls
Jls
Jls
Jls
1.0
4.0
Jls
Jls
o
"tJ
....o
W
o.......
o
o"tJ
........
o
w
o,....
,....
C")
a.
Connection Diagrams
o
S.O. Wide and DIP
S.O. Wide and DIP
o
.......
oo
L4
,....
GNo
L5
L6
VCC
C")
a.
L3
L7
oo
L2
Rmf
.......
L1
LO
CKI
DO
01
o,....
,....
SI
SO
SK
~
a.
oo
G2
G1
GO
GNo
,....
~
a.
oo
RrnT
03
L7
L6
L5
L4
G3
G2
G1
GO
SK
SO
VCC
.......
L3
L2
L1
TL/DD/S01S-2
oo
DO
01
02
CKO
CKI
SI
LO
Top View
TLIDD/S01S-3
Order Number COP311 C-XXX/D or COP411 C-XXX/D
See NS Hermetic Package Number D20A
Top View
Order Number COP310C-XXX/D or COP410C-XXX/D
See NS Hermetic Package Number D24C
Order Number COP311 C-XXX/N or COP411 C-XXX/N
See NS Molded Package Number N20A
Order Number COP310C-XXX/N or COP410C-XXX/N
See NS Molded Package Number N24A
Order Number COP311C-XXX/WM or
COP411C-XXX/WM
See NS Surface Mount Package Number M20B
Order Number COP310C-XXX/WM or
COP410C-XXX/WM
See NS Surface Mount Package Number M24B
FIGURE 2
Pin Descriptions
Pin
SK
Description
8-bit bidirectional I/O port with TRI-STATE
4-bit bidirectional I/O port
(G2-GO for 20-pin package)
4-bit general purpose output port
(01-00 for 20-pin package)
Serial input (or counter input)
Serial output (or general purpose output)
03- DO
SI
SO
CKI
CKO
RESET
Vee
GND
Description
Logic-controlled clock
(or general purpose output)
System oscillator input
Crystal oscillator output, or HALT mode
I/O port (24-pin package only)
System reset input
System power supply
System Ground
Timing Diagram
CKI
G3-Ga.
L7-La.03-00.
SD.SK _ _ _ _ _ _ _ _ _
.lJ.I....I..I.~
OUTPUTS
TLIDD/S015-4
FIGURE 3_ Input/Output (Divide-by-8 Mode)
1-42
o
o
Functional Description
"tJ
To ease reading of this description, only COP410C and/or
COP411 C are referenced; however, all such references apply equally to COP310C and/or COP311C, respectively.
oI:loo
......
INTERNAL LOGIC
A block diagram of the COP410C is given in Figure 1. Data
paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. Positive logic is
used. When a bit is set, it is a logic "1"; when a bit is reset, it
is a logic "0".
o
.......
The 4-bit A register (accumulator) is the source and destination register for most I/O, arithmetic, logiC and data memory
access operations. It can also be used to load the Bd portion of the B register, to load four bits of the 8-bit a latch
data and to perform data exchanges with the SID register.
"tJ
The 4-bit adder performs the arithmetic and logic functions
of the COP41 OCt 411 C, storing its results in A. It also outputs the carry information to a 1-bit carry register, most often employed to indicate arithmetic overflow. The C register,
in conjunction with the XAS instruction and the EN register,
also serves to control the SK output. C can be outputted
directly to SK or can enable SK to be a sync clock each
instruction cycle time. (See XAS instruction and EN register
description below.)
PROGRAM MEMORY
Program memory consists of a 512-byte ROM. As can be
seen by an examination of the COP41 OCt 411 C instruction
set, these words may be program instructions, program
data, or ROM addressing data. Because of the special characteristics associated with the JP, JSRP, JID, and LaiD instructions, ROM must often be thought of as being organized into 8 pages of 64 words (bytes) each.
The G register contents are outputs to four general purpose
bidirectional I/O ports.
ROM ADDRESSING
ROM addressing is accomplished by a 9-bit PC register. Its
binary value selects one of the 512 8-bit words contained in
ROM. A new address is loaded into the PC register during
each instruction cycle. Unless the instruction is a transfer of
control instruction, the PC register is loaded with the next
sequential 9-bit binary count value. Two levels of subroutine
nesting are implemented by two 9-bit subroutine save registers, SA and SB.
The a register is an internal, latched, 8-bit register, used to
hold data loaded from RAM and A, as well as 8-bit data from
ROM. Its contents are output to the L I/O ports when the L
drivers are enabled under program control. (See LEI instruction.)
The eight L drivers, when enabled, output the contents of
latched a data to the L I/O ports. Also, the contents of L
may be read directly into A and RAM.
ROM instruction words are fetched, decoded, and executed
by the instruction decode, control and skip logic circuitry.
Bd VALUE
DATA MEMORY
IS*
Data Memory consists of a 128-bit RAM, organized as four
data registers of 8 x 4-bit digits. RAM addressing is implemented by a 6-bit B register whose upper two bits (Br) selects one of four data registers and lower three bits of the 4bit Bd select one of eight 4-bit digits in the selected data
register. While the 4-bit contents of the selected RAM digit
(M) are usually loaded into or from, or exchanged with, the A
register (accumulator), they may also be loaded into the a
latches or loaded from the L ports. RAM addressing may
also be performed directly by the XAD 3, 15 instruction. The
Bd register also serves as a source register for 4-bit data
sent directly to the D outputs.
14*
RAM DIGIT
13*
12*'
11*
10*
0*
The most significant bit of Bd is not used to select a RAM
digit. Hence, each physical digit of RAM may be selected by
two different values of Bd as shown in Figure 4. The skip
condition for XIS and XDS instructions will be true if Bd
changes between 0 to 15, but not between 7 and 8 (see
Table III).
• Can be directly addressed by
LSI instruction (See Table 3)
0*
TLlDD/5015-5
FIGURE 4. RAM Digit Address to Physical
RAM Digit Mapping
1-43
o
The internal logic of the COP41 OCt 411 C is designed to ensure fully static operation of the device.
o
o
oI:loo
......
......
o
.......
o
o"tJ
w
......
o
o.......
o
o"tJ
W
......
......
o
o
.....
.....
C")
c..
o
o
'o
C)
.....
C")
c..
o
o
'o
.....
.....
"Ii:t'
c..
Functional Description
(Continued)
The SIO register functions as a 4·bit serial-in/serial-out shift
register or as a binary counter, depending upon the contents of the EN register. (See EN register description
below.) Its contents can be exchanged with A, allowing
it to input or output a continuous serial data stream. With
SIO functioning as a serial-in/serial-out shift register and SK
as a sync clock, the COP410C/411C is MICROWIRE compatible.
The 0 register provides four general purpose outputs and is
used as the destination register for the 4-bit contents of Bd .
oo
The XAS instruction copies C into the SKL latch. In the
counter mode, SK is the output of SKL; in the shift register
mode, SK is a sync clock, inhibited when SKL is a logic "0".
.....
"Ii:t'
c..
o
The EN register is an internal 4-bit register loaded under
program control by the LEI instruction. The state of each bit
of this register selects or deselects the particular feature
associated with each bit of the EN register (EN3-ENO).
o'C)
o
INITIALIZATION
The internal reset logic will initialize the device upon powerup if the power supply rise time is less than 1 ms and if the
operating frequency at CKI is greater than 32 kHz, otherwise the external RC network shown in Figure 5 must be
connected to the RESET pin. The RESET pin is configured
as a Schmitt trigger input. If not used, it should be connected to Vee. Initialization will occur whenever a logic "0" is
applied to the RESET input, providing it stays low for at
least three instruction cycle times.
When Vee power is applied, the internal reset logic will keep
the chip in initialization mode for up to 2500 instruction cycles. If the CKI clock is running at a low frequency, this
could take a long time, therefore, the internal logic should
be disabled by a mask option with initialization controlled
solely by RESET pin.
Note: If CKI clock is less than 32 kHz, the internal reset logiC (Option 25= 1)
must be disabled and the external RC network must be present.
1. The least significant bit of the enable register, ENO, selects the SIO register as either a 4-bit shift register or as a
4-bit binary counter. With ENO set, SIO is an asynchronous binary counter, decrementing its value by one upon
each low-going pulse ("1" to "0") occurring on the SI
input. Each pulse must be at least two instruction cycles
wide. SK outputs the value of SKL. The SO output is
equal to the value of EN3. With ENO reset, SIO is a serial
shift register, shifting left each instruction cycle time. The
data present at SI is shifted into the least significant bit of
SIO. SO can be enabled to output the most significant bit
of SIO each instruction cycle time. (See 4, below.) The
SK output becomes a logic-controlled clock.
Upon initialization. the PC register is cleared to 0 (ROM address 0) and the A, B, C, D, EN, and G registers are cleared.
The SK output is enabled as a SYNC output, providing a
pulse each instruction cycle time. Data memory (RAM) is
not cleared upon initialization. The first instruction at address 0 must be a CLRA (clear A register).
p +
0
E
R
S
U
P
P
L
Y
2. EN 1 is not used, it has no effect on the COP41 OCI 411 C.
3. With EN2 set, the L drivers are enabled to output the data
in Q to the L 1/0 ports. Resetting EN2 disables the L
drivers, placing the L 1/0 ports in a high impedance input
state.
I
.~ -~
w
vee
:~ ~~
RESET COP410C
::r:
GND
I
-
TL/DD/S01S-6
RC
4. EN3, in conjunction with ENO, affects the SO output. With
ENO set (binary counter option selected), SO will output
the value loaded into EN3. With ENO reset (serial shift
register option selected), setting EN3 enables SO as the
output of the SIO shift register, outputting serial shifted
data each instruction time. Resetting EN3 with the serial
shift register option selected, disables SO as the shift
register output; data continues to be shifted through SIO
and can be exchanged with A via an XAS instruction but
SO remains reset to "0".
>
5 x Power Supply Rise Time
and RC > 100 x CKI Period
FIGURE 5. Power-Up Clear Circuit
COP411C
If the COP41 OC is bonded as a 20-pin package, it becomes
the COP411 C, illustrated in Figure 2, COP41 OCI 411 C Connection Diagrams. Note that the COP411 C does not contain
02, 03, G3, or CKO. Use of this option, of course, precludes
use of 02, 03, G3, and CKO options. All other options are
available for the COP411 C.
TABLE I. Enable Register Modes -
Bits ENO and EN3
ENO
EN3
SIO
SI
SO
SK
0
0
Shift Register
0
If SKL = 1, SK = clock
0
1
Shift Register
1
1
0
1
Binary Counter
Binary Counter
Input to Shift
Register
Input to Shift
Register
Input to Counter
Input to Counter
1-44
Serial
out
°
1
°
If SKL = 0, SK =
If SKL = 1, SK = clock
If SKL = 0, SK = 0
SK = SKL
SK = SKL
o
Functional Description
o-a
(Continued)
flip-flop which is an indicator of the HALT status. An external signal can override this pin to start and stop the chip. By
forcing a high level to CKO, the chip will stop as soon as
CKI is high and the CKO output will go high to keep the chip
stopped. By forcing a low level to CKO, the chip will continue and CKO output will go low.
All features associated with the CKO 110 pin are available
with the 24-pin package only.
HALT MODE
The COP41 OCt 411 C is a fully static circuit; therefore, the
user may stop the system oscillator at any time to halt the
chip. The chip also may be halted by the HALT instruction or
by forcing CKO high when it is used as a HALT I/O port.
Once in the HALT mode, the internal circuitry does not receive any clock signal, and is therefore frozen in the exact
state it was in when halted. All information is retained until
continuing. The HALT mode is the minimum power dissipation state.
OSCILLATOR OPTIONS
There are three options available that define the use of CKI
and CKO.
a. Crystal-Controlled Oscillator. CKI and CKO are connected to an external crystal. The instruction cycle time
equals the crystal frequency divided by 16 (optionally by 8
or 4).
The HALT mode has slight differences depending upon the
type of oscillator used.
a. 1-pin oscillator-RC or external
The HALT mode may be entered into by either program
control (HALT instruction) or by forCing CKO to a logic
"1" state.
b. External Oscillator. CKI is configured as LSTIL-compatible input accepting an external clock signal. The external
frequency is divided by 16 (optionally by 8 or 4) to give
the instruction cycle time. CKO is the HALT I/O port.
The circuit may be awakened by one of two different
methods:
1) Continue function. By forcing CKO to a logic "0", the
system clock is re-enabled and the circuit continues to
operate from the point where it was stopped.
~
.....
Q
o
.......
o
o-a
~
.....
.....
o
.......
o
o-a
w
.....
Q
o
.......
o
o-a
w
.....
.....
o
c. RC-Controlled Oscillator. CKI is configured as a single pin
RC-controlled Schmitt trigger oscillator. The instruction
cycle equals the oscillation frequency divided by 4. CKO
is the HALT 1/0 port.
2) Restart. Forcing the RESET pin to a logic "0" will restart the chip regardless of HALT or CKO (see initialization).
b. 2-pin oscillator-crystal
The RC oscillator is not recommended in systems that require accurate timing or low current. The RC oscillator
draws more current than an external oscillator (typically an
additional 100 p.A at 5V). However, when the part halts, it
stops with CKI high and the halt current is at the minimum.
The HALT mode may be entered into by program control
(HALT instruction) which forces CKO to a logic "1" state.
The circuit can be awakened orily by the RESET function.
HALT 110
A
HALT
INSTRUCTION
CKI
CKO
R2
...ru-
HALT
EXTERNAL
III
CLOCK
CKI
TL/DD/5015-7
Halt 1/0 Port
CKO Pin Options
In a crystal-controlled oscillator system, CKO is used as an
output to the crystal network. CKO will be forced high during
the execution of a HALT instruction, thus inhibiting the crystal network. If a 1-pin oscillator system is chosen (RC or
external), CKO will be selected as HALT and is an I/O
TLlDD/5015-B
FIGURE 6. COP410C Oscillator
RC-Controlled
Oscillator
Crystal or Resonator
Crystal
Value
R1
32 kHz
455 kHz
2.096 MHz
4.0 MHz
220k
5k
2k
1k
Component Value
C1pF
C2pF
R2
20M
10M
1M
1M
30
80
30
30
5-36
40
6-36
6-36
1-45
R
C
Cycle
Time
15k
82 pF
4-9 P.s
82 pF
30k
8-16 P.s
47k
100 pF
16-32 p.s
Note: 15k ~ R ~ 150k,
50 pf ~ C ~ 150 pF
Vee
~4.5V
~4.5V
2.4 to 4.5
o
....
....
('I)
D.
oo
.......
oo
COP410C/COP411C Instruction Set
Table III provides the mnemonic, operand, machine code,
data flow, skip conditions and description associated with
each instruction in the COP41 OCt 411 C instruction set.
Table II is a symbol table providing internal architecture, instruction operand and operational symbols used in the instruction set table .
....
('I)
D.
oo
.......
o
....
....
TABLE II. COP41 OCt 411 C Instruction Set Table Symbols
Symbol
Definition
Symbol
Definition
INTERNAL ARCHITECTURE SYMBOLS
INSTRUCTION OPERAND SYMBOLS
D.
A
o.......
oo
B
d
r
-.::t
o
....
-.::t
D.
o
o
Br
Bd
C
D
EN
G
L
M
PC
Q
SA
SB
SIO
SK
4-bit Operand Field, 0-15 binary (RAM Digit Select)
2·bit Operand Field, 0·3 binary (RAM Register
Select)
a
9·bit Operand Field, 0·511 binary (ROM Address)
y
4·bit Operand Field, 0-15 binary (Immediate Data)
RAM(s) Contents of RAM location addressed by s
ROM(t) Contents of ROM location addressed by t
4-bit Accumulator
6-bit RAM Address Register
Upper 2 bits of B (register address)
Lower 4 bits of B (digit address)
1-bit Carry Register
4-bit Data Output Port
4-bit Enable Register
4-bit Register to latch data for G I/O Port
8·bitTRI·STATE I/O Port
4·bit contents of RAM Memory pointed to by B
Register
9·bit ROM Address Register (program counter)
8-bit Register to latch data for L I/O Port
9·bit Subroutine Save Register A
9·bit Subroutine Save Register B
4·bit Shift Register and Counter
Logic·Controlied Clock Output
OPERATIONAL SYMBOLS
+
-
-.
+--+
=
A
e
:
Plus
Minus
Replaces
Is exchanged with
Is equal to
The one's complement of A
Exclusive·OR
Range of values
TABLE III. COP410C/411C Instruction Set
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
DataFlow
Skip Conditions
Description
ARITHMETIC INSTRUCTIONS
ASC
30
10011100001
A + C + RAM(B) - . A
Carry - . C
Carry
Add with Carry, Skip on
Carry
ADD
31
10011100011
A + RAM (B) - . A
None
Add RAMtoA
A+y-.A
Carry
Add immediate, Skip on
Carry (y =1= 0)
AISC
y
5-
1
0101 1 y
1
CLRA
00
10000100001
O-.A
None
Clear A
COMP
40
10100100001
'A-.A
None
One's complement of A to A
NOP
44
10100101001
None
None
No Operation
RC
32
10011100101
"0" - . C
None
ResetC
SC
22
10010100101
"1" - . C
None
SetC
XOR
02
10000100101
A e RAM (B) - . A
None
Exclusive-OR RAM with A
1·46
o
o-a
Instruction Set (Continued)
....o"'"
TABLE III. COP410C/411C Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
o.......
Skip Conditions
Description
TRANSFER OF CONTROL INSTRUCTIONS
JID
JMP
a
FF
11111111111
6-
JP
a
-
JSRP
a
-
ROM (PCa, A,M) -+
PC7:0
None
Jump Indirect (Note 2)
1011O lOOOlaai
aZ"O
1
1
a -+ PC
None
Jump
111
aQ"O
1
(pages 2,3 only)
or
111 1 a5"O
1
(all other pages)
a -+ PC6:0
None
Jump within Page
(Note 1)
110 1
PC
a5"O
1
None
Jump to Subroutine Page
(Note 2)
PC + 1 -+ SA -+ SB
a -+ PC
None
Jump to Subroutine
-+ SA -+ SB
010 -+ PCa:6
a -+ PCs:o
6-
-
1011011001 as 1
aZ"O
1
1
RET
48
10100110001
SB -+ SA -+ PC
None
Return from Subroutine
RETSK
49
101001100111
SB -+ SA -+ PC
Always Skip on Return
Return from Subroutine
then Skip
HALT
33
38
10011100111
10011110001
None
Halt processor
JSR
a
MEMORY REFERENCE INSTRUCTIONS
CAMO
33
3C
10011100111
10011 11100 1
A -+ 07:4
RAM (B) -+ 03:0
None
Copy A, RAM to 0
COMA
33
2C
10011100111
10010111001
07:4 -+ RAM (B)
None
Copy 0 to RAM, A
-5
100lrl01011
RAM (B) -+ A
Br ED r -+ Br
None
Load RAM into A
Exclusive-OR Br with r
BF
11011 11111 1
ROM(PCa,A,M) -+ 0
SA -+ SB
None
Load 0 Indirect
LD
r
LOID
03:0-+ A
RMB
0
1
2
3
4C
45
42
43
10100111001
10100101011
10100100101
10100100111
o -+
o -+
o -+
o -+
RAM(B)o
RAM(B)1
RAM(B)2
RAM(B)3
None
Reset RAM Bit
5MB
0
1
2
3
40
47
46
4B
10100111011
10100101111
10100101101
10100110111
1
1
1
1
RAM(B)o
RAM(B)1
RAM(B)2
RAM(B)3
None
Set RAM Bit
STII
y
7-
10111 1
y -+ RAM (B)
Bd + 1 -+ Bd
None
Store Memory Immediate
and Increment Bd
X
r
-6
100lrl 0110 1
RAM (B) ~ A
Br ED r -+ Br
None
Exchange RAM with A,
Exclusive-OR Br with r
XAD
3,15
23
BF
10010100111
11011 11111 1
RAM(3,15) ~ A
None
Exchange A with RAM
(3,15)
y.
1
-+
-+
-+
-+
1-47
........o"'"
.......
o
a -+ PCs:o
+1
o
o-a
o-a
....ow
o
.......
o
o-a
w
....o....
o
....
....
CW)
c..
Instruction Set (Continued)
oo
TABLE III. COP410C/411C Instruction Set (Continued)
.......
o
Q
....
Mnemonic
Operand
Hex
Code
CW)
c..
oo
.......
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
MEMORY REFERENCE INSTRUCTIONS (Continued)
XDS
r
-7
100 1r 10111 1
RAM (B) ~ A
Bd - 1 --. Bd
Br E9 r --. Br
Bd decrements past 0
Exchange RAM with A
and Decrement Bd
Exclusive-OR Br with r
XIS
r
-4
100 1r 10100 1
RAM(B) ~ A
Bd + 1 --. Bd
Br E9 r --. Br
Bd increments past 15
Exchange RAM with A
and Increment Bd
Exclusive-OR Br with r
o
....
....
-.::t
c..
oo
.......
o
Q
....
-.::t
c..
o
o
REGISTER REFERENCE INSTRUCTIONS
CAB
50
10101100001
A --. Bd
None
Copy A to Bd
CBA
4E
10100111101
Bd --. A
None
Copy Bd toA'
-
100 1r 1(d - 1) 1
(d = 0,9:15)
r,d --. B
Skip until not a LBI
Load B Immediate with
r,d
33
10011100111
10010 1 Y 1
Y --. EN
None
Load EN Immediate
6SKC
20
1001010000
C
=
"1"
Skip if C is True
SKE
21
1001010001
A
=
RAM(B)
Skip if A Equals RAM
SKGZ
33
21
1001110011
1001010001
G3:0
=
Skip if G is Zero
(all 4 bits)
0
1
2
3
33
01
11
03
13
1001110011
1000010001
1000110001
1000010011
1001010011
0
1
2
3
01
11
03
13
1000010001
10001100011
10000100111
10001100111
LBI
r,d
LEI
y
TEST INSTRUCTIONS
SKGBZ
SKMBZ
0
Skip if G Bit is Zero
1st byte
} 2nd byte
Go
G1
G2
G3
=
=
=
=
0
0
0
0
RAM(B)o
RAM(B)1
RAM(B)2
RAM(B)a
=
=
=
=
0
0
0
0
Skip if RAM Bit is Zero
INPUTIOUTPUT INSTRUCTIONS
ING
33
2A
10011100111
10010110101
G--.A
None
Input G Ports to A
INL
33
2E
100 11 10011 1
10010111101
L7:4 --. RAM (B)
L3:0 --. A
None
Input L Ports to RAM, A
OBD
33
3E
10011100111
10011111101
Bd --. D
None
Output Bd to D Outputs
OMG
33
3A
10011100111
10011 11010 1
RAM(B) --. G
None
Output RAM to G Ports
XAS
4F
10100111111
A
None
Exchange A with SID
~
SID, C --. SKL
Note 1: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction,
otherwise, permits a jump to a ROM location within the current S4-word page. JP may not jump to the last word of a page.
Note 2: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of Pl. A JSRP may not be used when in pages 2 or 3. JSRP
may not jump to the last word in page 2.
1-48
o
o"tJ
Description of Selected
Instructions
0l:Io
.....
o
The following information is provided to assist the user in
understanding the operation of several unique instructions
and to provide notes useful to programmers in writing
COP41 OC/411 C programs.
POWER DISSIPATION
The lowest power drain is when the clock is stopped. As the
frequency increases so does current. Current is also lower
at lower operating voltages. Therefore, to minimize power
consumption, the user should run at the lowest speed and
voltage that his application will allow. The user should take
care that all pins swing to full supply levels to ensure that
outputs are not loaded down and that inputs are not at
some intermediate level which may draw current. Any input
with a slow rise or fall time will draw additional current. A
crystal- or resonator-generated clock will draw additional
current. An RC oscillator will draw even more current since
the input is a slow rising signal.
XAS INSTRUCTION
XAS (Exchange A with SIO) exchanges the 4-bit contents of
the accumulator with the 4-bit contents of the SIO register.
The contents of SIO will contain serial-in/serial-out shift register or binary counter data, depending on the value of the
EN register. An XAS instruction will also affect the SK output. (See Functional Description, EN Register). If SIO is selected as a shift register, an XAS instruction must be performed once every four instruction cycle times to effect a
continuous data stream.
If using an external squarewave oscillator, the following
equation can be used to calculate the COP410C current
drain.
JID INSTRUCTION
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location pointed
to indirectly by A and M. It loads the lower eight bits of the
ROM address register PC with the contents of ROM addressed by the 9-bit word, PCa, A, M. PCa is not affected by
this instruction.
Ic = Iq
+ (V x 20 x
Fi)
+
(V
x
1280
x FI/Dv)
where Ic = chip current drain in microamps
Iq = quiescent leakage current (from curve)
FI = CKI frequency in megahertz
V = chip Vee in volts
Note: JID uses two instruction cycles if executed. one if skipped.
Dv = divide by option selected
LQID INSTRUCTION
LaiD (Load a Indirect) loads the 8-bit a register with the
contents of ROM pointed to by the 9-bit word PCa, A, M.
LaiD can be used for table look-up or code conversion such
as 8CD to 7-segment. The LaiD instruction "pushes" the
stack (PC + 1 --+ SA --+ S8) and replaces the least
significant eight bits of the PC as follows: A --+ PC7:4,
RAM(8) --+ PC3:0, leaving PCa unchanged. The ROM data
pointed to by the new address is fetched and loaded into
the a latches. Next, the stack is "popped" (S8 --+ SA --+
PC), restoring the saved value of the PC to continue sequential program execution. Since LaiD pushes SA --+
S8, the previous contents of S8 are lost.
For example, at 5V Vee and 400 kHz (divide by 4),
Ic = 10
Ic = 10
+
+
(5
40
x 20 x 0.4) + (5 x
+ 640 = 690 J-lA
1280
x
0.4/4)
1/0 OPTIONS
COP41 OC/411 C outputs have the following optional configurations, illustrated in Figure 7:
a. Standard. A CMOS push-pull buffer with an N-channel
device to ground in conjunction with a P-channel device
to Vee, compatible with CMOS and LSTTL.
b. Low Current. This is the same configuration as (a) above
except that the sourcing current is much less.
Note: LQID uses two instruction cycles if executed. one if skipped.
c. Open Drain. An N-channel device to ground only, allowing external pull-up as required by the user's application.
INSTRUCTION SET NOTES
a. The first word of a COP41 OC/411 C program (ROM address 0) must be a CLRA (Clear A) instruction.
d. Standard TRI-STATE L Output. A CMOS output buffer
similar to (a) which may be disabled by program control.
b. Although skipped instructions are not executed, one instruction cycle time is devoted to skipping each byte of
the skipped instruction. Thus all program paths take the
same number of cycle times whether instructions are
skipped or executed (except JID and LaiD).
e. Low-Current TRI-STATE L Output. This is the same as
(d) above except that the sourcing current is much less.
f. Open-Drain TRI-STATE L Output. This has the N-channel device to ground only.
The SI and RESET inputs are Hi-Z inputs (Figure 7g).
c. The ROM is organized into eight pages of 64 words
each. The program counter is a 9-bit binary counter, and
will count through page boundaries. If a JP, JSRP, JID, or
LaiD instruction is located in the last word of a page, the
instruction operates as if it were in the next page. For
example: A JP located in the last word of a page will
jump to a location in the next page. Also, a LaiD or JID
located in the last word in page 3 or 7 will access data in
the next group of four pages.
When using either the G or L 1/0 ports as inputs, a pull-up
device is necessary. This can be an external device or the
following alternative is available: Select the low-current output option. Now, by setting the output registers to a logic
"1" level, the P-channel devices will act as the pull-up load.
Note that when using the L ports in this fashion, the a registers must be set to a logic "1" level and the L drivers must
be enabled by an LEI instruction.
1-49
o
......
o
o"tJ
0l:Io
.....
.....
o
......
o
o"tJ
eN
.....
o
o
......
o
o"tJ
eN
.....
.....
o
o
....
....
Cf)
a..
Functional Description
(Continued)
~} ~}
o
o......
o
o
....
Cf)
a..
oo
......
o
....
a. Standard Push-Pull Output
b. Low Current Push-Pull Output
DlSre:} Dlwre}
....
"'I:t'
a..
oo
......
oo
....
"'I:t'
a..
o
d. Standard TRI-STATE
"L" Output
o
e. Low Current TRI-STATE
"L" Output
c. Open Drain Output
Vee
D~f
f. Open Drain TRI-STATE
"L" Output
vee
~ -!~~
~
g. Hi-Z Input
TlIDD/5015-9
FIGURE 7.110 Configurations
Typical Performance Characteristics
2.4
Minimum Sink curre~t
2.0
H+-+-++-f--++-l-5~.5~~-l
.
1/,
o UV
1 1
1.0
2.0
- ....
3.0
4.0
5.0
o
6.0
1.0
600
500 t-UV
L
0
~V r-...
i:z:
1.0
COP310C/COP311C
Low Current Option
Maximum Source Current
1\
'"
2.0
1.0
2.0
3.0
1\
1\
4.0
5.0
6.0
• Maximum Quiescent Current
60~+--+--~+--+~
/
1\
3.0
4.0
VOH (VOLTS)
,
5.0
~
300
200
~
~
1
'soc
.~+--+--~~~~+-~
14!
0
o
VOH (VOLTS)
I'
200
100
o
B.O
~
I"
300
5.0
500~'~
I-+L-+-+-+-+-+-+~+-+-+--l
1
,
4.0
10 2.4Y
YoH (VOLTS)
COP41 OC/COP411 C
Low Current Option
Maximum Source Current
400
\
'~
I'..
- ...... '\
2.0 3.0
VOL (VOLTS)
600
I'..
r-....
3¥ __ . .
0.2
1
o
r-
1
4.~V't-f-+-~r-....--"'I<-I'\-+-I-+-+--l
0.6
0.4:
'/
-~
0.4 11 /' ... "2.41 f-+--+--l--+-+-+-l
o.
f4!
:
0' 5.5V
~
Low Current Option
Source Current
60 Minimum
1
1.0
1.6 I-+-+-+-+--bot<=(...+'""""-+-+-+-+--l
0.8
Standard
Minimum Source Current
12
•
I
I
I
100
0
6.0
I'..
3.0V
0
1"1--,
1\
1'\
1.0
2.0
3.0
10
1\
4.0
VOH (VOLTS)
3Q
1--+--+---l-V-J)4V----:.l-7-0OC-l
2t1--+--+---Jt.-'7'G--+--I
5.0
B.O
-
1--+--+-.L./'-+::::V.....-t~==___+=~=-sOC--=-!
4
Vee (VOLTS)
TL/DD/5015-10
FIGURE 8
1-50
0
All output drivers uses one or more of three common devices numbered 1 to 3. Minimum and maximum current (lOUT
and VOUT) curves are given in Figure 8 for each of these
devices to allow the designer to effectively use these I/O
configurations.
Option 6:
L6 Driver. (Same as Option 5.)
Option 7:
L5 Driver. (Same as Option 5.)
Option 8:
L4 Driver. (Same as Option 5.)
Option 9:
Vee Pin
=
0 no option.
Option 10: L3 Driver. (Same as Option 5.)
Option List
The COP41 OC/ 411 C mask-programmable options are assigned numbers which correspond with the COP410C pins.
The following is a list of COP41 OC options. When specifying
a COP411 chip, options 20, 21, and 22 must be set to O. The
options are programmed at the same time as the ROM pattern to provide the user with the hardware flexibility to interface to various I/O components using little or no external
circuitry.
Option 1:
0 = Ground Pin. No options available.
Option 2:
CKO I/O Port. (Determined by Option 3.)
Option 3:
.......
Option 14: Sllnput.
a"'0
=
=
=
0
0: Standard push-pull output.
1: Low-current push-pull output.
2: Open-drain output.
Option 17: Go I/O Port. (Same as Option 15.)
Option 18: G1 I/O Port. (Same as Option 15.)
Option 19: G2 I/O Port. (Same as Option 15.)
Option 20: G3 I/O Port. (Same as Option 15.)
= 0: Crystal-controlled oscillator input (-:- 4).
Option 21: D3 Output. (Same as Option 15.)
= 1: Single-pin RC-controlled oscillator (-:- 4).
Option 22: D2 Output. (Same as Option 15.)
= 2: External oscillator input (-:- 4).
Option 23: D1 Output. (Same as Option 15.)
= 3: Crystal oscillator input (-:- 8).
Option 24: Do Output. (Same as Option 15.)
= 4: External oscillator input (-:- 8).
Option 25: Internal Initialization Logic.
= 5: Crystal oscillator input (-:- 16).
= 0: Normal operation.
= 6: External oscillator input (-:- 16).
= 1: No internal initialization logic.
Option 4:
RESET Input = 1: Hi-Z input. No option available.
Option 5:
L7 Driver
Option 26: No option available.
Option 27: COP Bonding
= 0: COP41 OC (24-pin device).
= 0: Standard TRI-STATE push-pull output.
= 1: COP411 C (20-pin device). See note.
= 1: Low-current TRI-STATE push-pull output.
= 2: COP41 OC and COP411 C. See note.
= 2: Open-drain TRI-STATE output.
Note: If opt. # 27 = 1 or 2 then opt # 20 must = o.
Option Table
Please fill out a photocopy of the option table and send it along with your EPROM.
Option Table
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
1 Value
2 Value
3 Value
4 Value
5 Value
6 Value
7 Value
8 Value
9 Value
10 Value
11 Value
12 Value
13 Value
14 Value
=
=
=
=
=
=
=
=
=
=
=
=
=
=
0
0
0
is: Ground Pin
is: CKO Pin
is: CKI Input
is: RESET Input
is: L7 Driver
is: L6 Driver
is: L5 Driver
is: L4 Driver
is: Vee Pin
is: L3 Driver
is: L2 Driver
is: L1 Driver
is: Lo Driver
is: Sllnput
15 Value
16 Value
17 Value
18 Value
19 Value
20 Value
21 Value
22 Value
23 Value
24 Value
25 Value
=
=
=
=
=
=
=
=
=
=
=
Option 26 Value
Option 27 Value
=
=
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
1-51
0
0
w
.....
1: Hi-Z input.
Option 16: SK Driver. (Same as Option 15.)
CKI Input.
a"'0
Option 13: Lo Driver. (Same as Option 5.)
Option 15: SO Output.
b. is HALT I/O for one pin oscillator.)
0
0
.......
0
0I:loo
.....
.....
=
(a. is crystal oscillator output for two pin
oscillator.
0I:loo
.....
Option 11: L2 Driver. (Same as Option 5.)
Option 12: L1 Driver. (Same as Option 5.)
No option available.
= 0: No option.
a"'0
0
is: SO Output
is: SK Driver
is: Go I/O Port
is: G1 I/O Port
is: G2 I/O Port
is: G3 I/O Port
is: D3 Output
is: D2 Output
is: D1 Output
is: Do Output
is: Internal
Initialization
Logic
is: N/A
is: COP Bonding
0
.......
0
a"'0
w
.....
.....
0
....I
.....
.....
C")
a..
o
o
......
o
.....
C")
....I
a..
~National
a
Semiconductor
COP41 Ol/COP411 l/COP31 Oll COP311 l
oo Single-Chip N-Channel Microcontrollers
......
General Description
.....
.....
Features
....I
"II:J'
a..
o
o
::J
o
.....
"II:J'
a..
oo
The COP41 OL and COP411 L Single-Chip N-Channel Microcontrollers are members of the COPSTM family, fabricated
using N-channel, silicon gate MOS technology. These Controller Oriented Processors are complete microcomputers
containing all system timing, internal logic, ROM, RAM and
110 necessary to implement dedicated control functions in a
variety of applications. Features include single supply operation, a variety of output configuration options, with an instruction set, internal architecture and I/O scheme designed to facilitate keyboard input, display output and BCD
data manipulation. The COP411 L is identical to the
COP410L, but with 16 I/O lines instead of 19. They are an
appropriate choice for use in numerous human interface
control environments. Standard test procedures and reliable
high-density fabrication techniques provide the medium to
large volume customers with a customized Controller Oriented Processor at a low end-product cost.
The COP310L and COP311 L are exact functional equivalents but extended temperature versions of COP410L and
COP411 L respectively.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low cost
Powerful instruction set
512 x 8 ROM, 32 x 4 RAM
19 110 lines (COP410L)
Two-level subroutine stack
16 IJ-s instruction time
Single supply operation (4.5V-6.3V)
Low current drain (6 rnA max)
Internal binary counter register with MICROWIRETM seriall/O capability
General purpose and TRI-STATE® outputs
LSTTLICMOS compatible in and out
Direct drive of LED digit and segment lines
Software/hardware compatible with other members of
COP400 family
Extended temperature range device
- COP310LlCOP311 L (-40°C to + 85°C)
Wider supply range (4.5V-9.5V) optionally available
The COP401 L should be used for exact emulation.
Block Diagram
CKI
GNO
VCC
L
L
, 1
CKO
tz
INSTRUCTION CLOCK (SYNCI
...--------+---l,,"'w'", "
TL/DD/6919-1
FIGURE 1. COP410L
1-52
o
COP410L/COP411L
a"'tJ
Absolute Maximum Ratings
o
~
.....
If Militaryl Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Voltage at Any Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
- O.5V to
O°C to
- 65°C to
Lead Temperature
(Soldering, 10 seconds)
r.......
Power Dissipation
COP410L
O.75W at 25°C
0.4Wat70°C
0.65W at 25°C
0.3W at 70°C
COP411L
+ 10V
+ 70°C
+ 150°C
Total Source Current
120 mA
Total Sink Current
100mA
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
300°C
DC Electrical Characteristics O°C ~ TA ~ + 70°C, 4.5V ~ Vee ~ 9.5V unless otherwise noted
Parameter
Standard Operating Voltage (Vee)
Conditions
(Note 1)
Optional Operating Voltage (Vee)
Power Supply Ripple
Peak to Peak
Operating Supply Current
All Inputs and Outputs Open
o
a"'tJ
.....
.....
~
r.......
o
a"'tJ
.....
o
CA)
r.......
o
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CA)
Min
Max
Units
4.5
6.3
V
4.5
9.5
V
0.5
V
6
mA
3.0
2.0
-0.3
0.4
V
V
V
0.7 Vee
-0.3
0.6
V
V
0.7 Vee
-0.3
0.6
V
V
2.0
2.5
V
0.8
V
V
V
V
V
.....
.....
r-
Input Voltage Levels
CKllnput Levels
Ceramic Resonator Input (+ 8)
Logic High (VIH)
Logic High (VI H)
Logic Low (VIU
Vee = Max
Vee = 5V ±5%
Schmitt Trigger Input (+ 4)
Logic High (VIH)
Logic Low (VIU
RESET Input Levels
Logic High
Logic Low
(Schmitt Trigger Input)
SO Input Level (Test Mode)
(Note 2)
All Other Inputs
Logic High
Logic High
Logic Low
Logic High
Logic Low
Vee = Max
With TTL Trip Level Options
Selected, Vee = 5V ±5%
With High Trip Level Options
Selected
3.0
2.0
-0.3
3.6
-0.3
Input Capacitance
-1
Hi-Z Input Leakage
1.2
7
+1
p.A
0.4
V
V
0.2
V
V
pF
Output Voltage Levels
LSTTL Operation
Logic High (VOH)
Logic Low (VOU
Vee = 5V ±10%
IOH = -25 p.A
IOL = 0.36 mA
2.7
CMOS Operation (Note 3)
Logic High
Logic Low
IOH = -10 p.A
IOL = + 10 p.A
Note 1: Vee voltage change must be less than 0.5V in a 1 ms period to maintain proper operation.
Note 2: 50 output "0" level must be less than O.BV for normal operation.
Note 3:
TRI-5TATE~
and LED configurations are excluded.
1-53
Vee - 1
--
,..
,..
....I
CIt)
a..
o(.)
:::l
Q
,..
COP41 OL/COP411 L
DC Electrical Characteristics o·c =:;: T A=:;:+ 70·C, 4.5V =:;: Vee =:;: 9.5V unless otherwise noted (Continued)
Parameter
CIt)
Output Current Levels
o
Output Sink Current
a..
(.)
......
SO and SK Outputs (Iou
,..
,..
....I
~
a..
Lo-L7 Outputs, GO-G3 and
LSTTL 00-03 Outputs (Iou
Q
,..
00-03 Outputs with High
Current Options (Iou
o(.)
:::l
~
a..
o(.)
00-03 Outputs with Very
High Current Options (Iou
CKI (Single·Pin RC Oscillator)
CKO
Conditions
= O.4V
= O.4V
= O.4V
Vee = 9.5V, VOL = O.4V
Vee = 6.3V, VOL = O.4V
Vee = 4.5V, VOL = O.4V
Vee = 9.5V, VOL = 1.0V
Vee = 6.3V, VOL = 1.0V
Vee = 4.5V, VOL = 1.0V
Vee = 9.5V, VOL = 1.0V
Vee = 6.3V, VOL = 1.0V
Vee = 4.5V, VOL = 1.0V
Vee = 4.5V, VIH = 3.5V
Vee = 4.5V, VOL = 0.4V
Vee = 9.5V, VOL
Vee = 6.3V, VOL
Vee = 4.5V, VOL
Min
Max
Units
1.8
1.2
0.9
rnA
rnA
rnA
0.4
0.4
0.4
rnA
rnA
rnA
15
11
7.5
rnA
rnA
rnA
30
22
15
rnA
rnA
rnA
2
0.2
rnA
rnA
Output Source Current
Standard Configuration,
All Outputs (I0H)
Push·Puli Configuration
SO and SK Outputs (I0H)
LED Configuration, Lo-L7
Outputs, Low Current
Driver Option (I0H)
= 9.5V, VOH
= 6.3V, VOH
= 4.5V, VOH
Vee = 9.5V, VOH
Vee = 6.3V, VOH
Vee = 4.5V, VOH
Vee = 9.5V, VOH
Vee = 6.0V, VOH
Vee
Vee
Vee
-140
-75
-30
-800
-480
-250
-1.4
-1.4
-1.2
p,A
p,A
p,A
rnA
rnA
rnA
-1.5
-1.5
-18
-13
rnA
rnA
= 9.5V, VOH = 2.0V
= 6.0V, VOH = 2.0V
-3.0
-3.0
-35
-25
rnA
rnA
= 9.5V, VOH = 5.5V
= 6.3V, VOH = 3.2V
= 4.5V, VOH = 1.5V
Vee = 9.5V, VOH = 5.5V
Vee = 6.3V, VOH = 3.2V
Vee = 4.5V, VOH = 1.5V
Vee = 5.0V, VIL = OV
-0.75
-0.8
-0.9
rnA
rnA
rnA
-1.5
-1.6
-1.8
rnA
rnA
rnA
LED Configuration, Lo-L7
Outputs, High Current
Driver Option (I0H)
Vee
Vee
TRI·STATE Configuration,
Lo-L7 Outputs, Low
Current Driver Option (I0H)
Vee
Vee
Vee
TRI·STATE Configuration,
La-L7 Outputs, High
Current Driver Option (IOH)
= 2.0V
= 2.0V
= 2.0V
= 4.75V
= 2.4V
= 1.0V
= 2.0V
= 2.0V
-140
p,A
1.5
rnA
+2.5
p,A
Total Sink Current Allowed
All Outputs Combined
Port
L7-L4, G Port
L3-La
Any Other Pin
100
100
4
4
2.0
rnA
rnA
rnA
rnA
rnA
Total Source Current Allowed
All I/O Combined
L7- L4
L3-La
Each L Pin
Any Other Pin
120
60
60
25
1.5
rnA
rnA
rnA
rnA
rnA
Input Load Source Current
-10
CKO Output
RAM Power Supply Option
Power Requirement
VR = 3.3V
TRI·STATE Output Leakage
Current
-2.5
o
1·54
o
o
-a
~
COP31 OL/COP311 L
....o
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage at Any Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
r.......
Power Dissipation
COP310L
0.75W at 25·C
0.25W at 85·C
0.65W at 25·C
0.20W at 85·C
COP311L
-0.5V to + 10V
- 40·C to + 85·C
- 65·C to + 150·C
Lead Temperature
(Soldering, 10 seconds)
-40·C
Parameter
Standard Operating Voltage (Vee)
120mA
Total Sink Current
100mA
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
300·C
DC Electrical Characteristics
Total Source Current
~ TA ~ + 85·C, 4.5V ~ Vee ~ 7.5V unless otherwise noted
Conditions
(Note 1)
Optional Operating Voltage (Vee)
Power Supply Ripple
Peak to Peak
Operating Supply Current
All Inputs and Outputs Open
o
o-a
........
r~
.......
o
o-a
....o
Cot)
C
o
o-a
........
rCot)
Min
Max
Units
4.5
5.5
V
4.5
7.5
V
0.5
V
8
mA
3.0
2.2
-0.3
0.3
V
V
V
0.7 Vee
-0.3
0.4
V
V
0.7 Vee
-0.3
0.4
V
V
2.2
2.5
V
3.0
2.2
-0.3
3.6
-0.3
0.6
V
V
V
V
V
7
pF
-2
+2
,..,A
0.4
V
V
0.2
V
V
Input Voltage Levels
Ceramic Resonator Input ( -:- 8)
Crystal Input
Logic High (VIH)
Logic High (VIH)
Logic Low (VIU
Vee = Max
Vee = 5V ±5%
Schmitt Trigger Input (-:- 4)
Logic High (VIH)
Logic Low (VIlJ
RESET Input Levels
Logic High
Logic Low
(Schmitt Trigger Input)
SO Input Level (Test Mode)
(Note 2)
All Other Inputs
Logic High
Logic High
Logic Low
Logic High
Logic Low
Vee = Max
With TIL Trip Level Options
Selected, Vee = 5V ±5%
With High Trip Level Options
Selected
Input Capacitance
Hi-Z Input Leakage
1.2
Output Voltage Levels
LSTIL Operation
Logic High (VOH)
Logic Low (VoU
Vee = 5V ±10%
IOH = -20,..,A
IOL = 0.36 mA
2.7
CMOS Operation (Note 3)
Logic High
Logic Low
IOH = -10,..,A
IOL = +10,..,A
Note 1: Vee voltage change must be less than 0.5V In a 1 ms period to maintain proper operation.
Note 2: SO output "0" level must be less than 0.6V for normal operation.
Note 3: TRI·STATE and LED configurations are excluded.
1-55
Vee - 1
III
..J
,...
,...
('t)
COP31 OL/COP311 L
D..
o
o
.......
..J
o
,...
DC Electrical Characteristics
Parameter
('t)
D..
o
o
.......
..J
,...
,...
(Continued)
-40·C ::::;; T A ::::;; + 85·C, 4.5V ::::;; Vee::::;; 7.5V unless othewise noted
Conditions
Min
Max
Units
Output Current Levels
Output Sink Current
SO and SK Outputs (IoU
oo
Vee = 7.5V, VOL = O.4V
Vee = 5.5V, VOL = O.4V
Vee = 4.5V, VOL = O.4V
1.4
1.0
0.8
mA
mA
mA
Lo-L7 Outputs, GO-G3 and
LSTTL 00-03 Outputs (IoU
Vee = 7.5V, VOL = O.4V
Vee = 5.5V, VOL = O.4V
Vee = 4.5V, VOL = O.4V
0.4
0.4
0.4
mA
mA
mA
"'I::t
D..
00-03 Outputs with High
Current Options (IoU
Vee = 7.5V, VOL = 1.0V
Vee = 5.5V, VOL = 1.0V
Vee = 4.5V, VOL = 1.0V
12
9
7
mA
mA
mA
00-03 Outputs with Very
High Current Options (IoU
Vee = 7.5V, VOL = 1.0V
Vee = 5.5V, VOL = 1.0V
Vee = 4.5V, VOL = 1.0V
24
18
14
mA
mA
mA
CKI (Single-Pin RC Oscillator)
CKO
Vee = 4.5V, VIH = 3.5V
Vee = 4.5V, VOL = O.4V
1.5
0.2
mA
mA
Standard Configuration,
All Outputs (IOH)
Vee = 7.5V, VOH = 2.0V
Vee = 5.5V, VOH = 2.0V
Vee = 4.5V, VOH = 2.0V
-100
-55
-28
Push-Pull Configuration
SO and SK Outputs (IOH)
Vee = 7.5V, VOH = 3.75V
Vee = 5.5V, VOH = 2.0V
Vee = 4.5V, VOH = 1.0V
-0.85
-1.1
-1.2
LED Configuration, Lo-L7
Outputs, Low Current
Driver Option (IOH)
Vee = 7.5V, VOH = 2.0V
Vee = 5.5V, VOH = 2.0V
-1.4
-0.7
-27
-15
mA
p.A
LED Configuration, Lo-L7
Outputs, High Current
Driver Option (IOH)
Vee = 7.5V, VOH = 2.0V
Vee = 5.5V, VOH = 2.0V
-2.7
-1.4
-54
-30
mA
p.A
TRI-STATE Configuration,
Lo-L7 Outputs, Low
Current Driver Option (IOH)
Vee = 7.5V, VOH = 4.0V
Vee = 5.5V, VOH = 2.7V
Vee = 4.5V, VOH = 1.5V
-0.7
-0.6
-0.9
mA
mA
mA
TR I-STATE Configuration,
Lo-L7 Outputs, High
Current Driver Option (IOH)
Vee = 7.5V, VOH = 4.0V
Vee = 5.5V, VOH = 2.7V
Vee = 4.5V, VOH = 1.5V
-1.4
-1.2
-1.8
mA
mA
mA
Input Load Source Current
Vee = 5.0V, VIL = OV
-10
CKO Output
RAM Power Supply Option
Power Requirement
VR = 3.3V
"'I::t
D..
.......
..J
o,...
oo
Output Source Current
-900
-600
-350
p.A
p.A
p.A
mA
mA
mA
-200
p.A
2.0
mA
+5
p.A
All Outputs Combined
100
mA
o Port
100
mA
LrL4, G Port
4
mA
L3- LO
Any Other Pins
4
mA
1.5
mA
All 1/0 Combined
120
mA
Lr L4
L3- LO
60
mA
60
mA
Each L Pin
25
mA
Any Other Pins
1.5
mA
TRI-STATE Output Leakage
Current
-5
Total Sink Current Allowed
Total Source Current Allowed
1-56
0
0
AC Electrical Characteristics
COP41 OLl411 L: o·c ~ TA ~ 70·C, 4.5V ~ Vee ~ 9.5V unless otherwise noted
COP310L/311 L: -40·C
~
TA
~
+ 85·C, 4.5V
~
Vee
~
."
~
...I.
0
7.5V unless otherwise noted
Parameter
r......
Conditions
Instruction Cycle Time - te
CKI
Input Frequency - fl
Min
Max
Units
16
40
!-,-S
0.2
0.1
30
0.5
0.25
60
500
200
MHz
MHz
%
ns
ns
."
~
+8 Mode
+4 Mode
Duty Cycle
Rise Time
Fall Time
CKI Using RC (+4)
(Note 1)
Instruction Cycle Time
CKO as SYNC Input
tSYNe
INPUTS
G3- GO, L7- LO
tSETUP
tHOLD
SI
tSETUP
tHOLD
OUTPUT PROPAGATION DELAY
fl = 0.5 MHz
16
28
!-,-S
Test Condition:
CL = 50 pF, RL
ns
8.0
1.3
!-,-s
!-,-s
2.0
1.0
!-,-S
!-,-S
= 20 k!1, VOUT = 1.5V
4.0
!-,-S
5.6
!-,-S
Connection Diagrams
so Wide and DIP
so Wide and DIP
GNO- 1
24~00
CKO- 2
CKI- 3
231-- D1
221-- 0 2
211-- 03
20l--G3
191--G2
181--GI
I1I--GO
161--SK
5
6
1
8
VCC- 9
l 3 - 10
l 2 - 11
COP410LI
C0P310L
r......
0
0
."
w
...I.
0
0
0
."
W
400
Note 1: Variation due to the device included.
1ITm- 4
...I.
...I.
r......
R = 56 k!1 ±5%
C = 100pF ±10%
SO, SK Outputs
tpd1, tpdO
All Other Outputs
tpd1, tpdO
L7l6l5l4-
0
0
l4-1
VCC- 2
l3- 3
l2_ 4
11- 5
lO_ 6
51- 1
SO- 8
SK- 9
GNO- 10
15~SO
14~SI
U - ...1_2_ _ _ _1.....
3 ~lD
COP411L1
COP311L
20l-L5
191-L6
181--Ll
11I-RESET
161--CKI
151--00
141-01
131-G2
12I-Gl
l1J--GO
TL/DD/6919-3
Top View
TL/DD/6919-2
Top View
Order Number COP311 L·XXX/D or COP411 L·XXX/D
Order Number COP310L.XXX/D or COP410L.XXX/D
See NS Hermetic Package Number D24C
See NS Hermetic Package Number D24C
Order Number COP311 L·XXXIN or COP411 L·XXXIN
Order Number COP310L.XXX/N or COP410L.XXX/N
See NS Molded Package Number N20A
Order Number COP311 L·XXX/WM or COP411 L·XXX/WM
See NS Molded Package Number N24A
Order Number COP310L.XXX/WM or COP410L.XXX/WM
See NS Surface Mount Package Number M24B
See NS Surface Mount Package Number M24B
FIGURE 2
Pin Descriptions
Pin
CKI
CKO
Description
System oscillator input
System oscillator output (or RAM power supply or
SYNC input) (COP410L only)
RESET System reset input
Vee
Power supply
GNO
Ground
Pin
L7-Lo
Description
8 bidirectional I/O ports with TRI-STATE
G3- GO 4 bidirectional I/O ports (G2-GO for COP411 L)
03- 0 0 4 general purpose outputs (01 - Do for COP411 L)
SI
Serial input (or counter input)
Serial output (or general purpose output)
SO
Logic-controlled clock (or general purpose output)
SK
1-57
...I.
...I.
r-
-J
"P"P-
C")
r------------------------------------------------------------------------------------,
Timing Diagrams
D.
o
o.......
I·
CKI
-J
o
"P-
C")
s~t~~~
VOH
I""''"V~O:.::.L----~~J.I
- I 1l-tSETUP
D.
o
o
.......
tHOLD
-J
"P"P-
"'11:1'
D.
TLfDD/6919-4
o
FIGURE 3. Input/Output Timing Diagrams (Ceramic Resonator Dlvlde-by-S Mode)
o
.......
-J
o
"P-
"'11:1'
CKI
D.
o
o
TL/DD/6919-5
FIGURE 3a. Synchronization Timing
Functional Description
A block diagram of the COP410L is given in Figure 1. Data
paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. Positive logic is
used. When a bit is set, it is a logic "1" (greater than 2V).
When a bit is reset, it is a logic "0" (less than 0.8V).
may also be loaded into the Q latches or loaded from the L
ports. RAM addressing may also be performed directly by
the XAD 3,15 instruction. The Bd register also serves as a
source register for 4-bit data sent directly to the 0 outputs.
The most significant bit of Bd is not used to select a RAM
digit. Hence each physical digit of RAM may be selected by
two different values of Bd as shown in Figure 4 below. The
skip condition for XIS and XDS instructions will be true if Bd
changes between 0 and 15, but NOT between 7 and 8 (see
Table III).
All functional references to the COP41 OLlCOP411 L also
apply to the COP31 OLlCOP311 L.
PROGRAM MEMORY
Program Memory consists of a 512-byte ROM. As can be
seen by an examination of the COP41 OLl411 L instruction
set, these words may be program instructions, program data
or ROM addressing data. Because of the special characteristics associated with the JP, JSRP, JID and LQID instructions, ROM must often be thought of as being organized into
8 pages of 64 words each.
Bd VALUE
RAM DIGIT
15*
14*
13*
12*
ROM addressing is accomplished by a 9-bit PC register. Its
binary value selects one of the 512 8-bit words contained in
ROM. A new address is loaded into the PC register during
each instruction cycle. Unless the instruction is a transfer of
control instruction, the PC register is loaded with the next
sequential 9-bit binary count value. Two levels of subroutine
nesting are implemented by the 9-bit subroutine save registers, SA and SB, providing a last-in, first-out (LIFO) hardware subroutine stack.
11*
10*
9*
ROM instruction words are fetched, decoded and executed
by the Instruction Decode, Control and Skip Logic circuitry.
DATA MEMORY
Data memory consists of a 128-bit RAM, organized as 4
data registers of 8 4-bit digits. RAM addressing is implemented by a 6-bit B register whose upper 2 bits (Br) select 1
of 4 data registers and lower 3 bits of the 4-bit Bd select 1 of
8 4-bit digits in the selected data register. While the 4-bit
contents of the selected RAM digit (M) is usually loaded into
or from, or exchanged with, the A register (accumulator), it
4
3
·Can be directly addressed by
LSI instruction (see Table III)
2
0*
TL/DD/6919-6
FIGURE 4. RAM Digit Address to
Physical RAM Digit Mapping
1-58
o
Functional Description
o"'tJ
(Continued)
~
INTERNAL LOGIC
each low-going pulse ("1" to "0") occurring on the SI
input. Each pulse must be at least two instruction cycles
wide. SK outputs the value of SKL. The SO output is
equal to the value of EN3. With ENo reset, SIO is a serial
shift register shifting left each instruction cycle time. The
data present at SI goes into the least significant bit of
SIO. SO can be enabled to output the most significant bit
of SIO each cycle time. (See 4 below.) The SK output
becomes a logic-controlled clock.
The 4-bit A register (accumulator) is the source and destination register for most I/O, arithmetic, logic and data memory
access operations. It can also be used to load the Bd portion of the B register, to load 4 bits of the a-bit Q latch data,
to input 4 bits of the a-bit L I/O port data and to perform
data exchanges with the SIO register.
A 4-bit adder performs the arithmetic and logic functions of
the COP41 OL/ 411 L, storing its results in A. It also outputs a
carry bit to the 1-bit C register, most often employed to indicate arithmetic overflow. The C register, in conjunction with
the XAS instruction and the EN register, also serves to control the SK output. C can be outputted directly to SK or can
enable SK to be a sync clock each instruction cycle time.
(See XAS instruction and EN register description, below.)
2. EN1 is not used. It has no effect on COP41 OL/COP411 L
operation.
3. With EN2 set, the L drivers are enabled to output the data
in Q to the L I/O ports. Resetting EN2 disables the L
drivers, placing the L I/O ports in a high-impedance input
state.
4. EN3, in conjunction with ENo, affects the SO output. With
ENo set (binary counter option selected) SO will output
the value loaded into EN3. With ENo reset (serial shift
register option selected), setting EN3 enables SO as the
output of the SIO shift register, outputting serial shifted
data each instruction time. Resetting EN3 with the serial
shift register option selected disables SO as the shift register output; data continues to be shifted through SIO and
can be exchanged with A via an XAS instruction but SO
remains reset to "0." Table I provides a summary of the
modes associated with EN3 and ENQ.
The G register contents are outputs to 4 general-purpose
bidirectional I/O ports.
The Q register is an internal, latched, a-bit register, used to
hold data loaded from M and A, as well as a-bit data from
ROM. Its contents are output to the L I/O ports when the L
drivers are enabled under program control. (See LEI instruction.)
The a L drivers, when enabled, output the contents of
latched Q data to the L I/O ports. Also, the contents of L
may be read directly into A and M. L I/O ports can be directly connected to the segments of a multiplexed LED display
(using the LED Direct Drive output configuration option) with
Q data being outputted to the Sa-Sg and decimal point
segments of the display.
-&.
o
r
.......
o
o"'tJ
~
-&.
-&.
r
.......
o
o"'tJ
W
-&.
o
r
.......
o
o"'tJ
W
-&.
-&.
r
INITIALIZATION
The Reset Logic will initialize (clear) the device upon powerup if the power supply rise time is less than 1 ms and greater than 1 J-Ls. If the power supply rise time is greater than
1 ms, the user must provide an external RC network and
diode to the RESET pin as shown below (Figure 5). The
RESET pin is configured as a Schmitt trigger input. If not
used it should be connected to Vee. Initialization will occur
whenever a logic "0" is applied to the RESET input, provided it stays low for at least three instruction cycle times.
The SIO register functions as a 4-bit serial-in serial-out shift
register or as a binary counter depending on the contents of
the EN register. (See EN register description, below.) Its
contents can be exchanged with A, allowing it to input or
output a continuous serial data stream. SIO may also be
used to provide additional parallel I/O by connecting SO to
external serial-in/parallel-out shift registers.
The XAS instruction copies C into the SKL Latch. In the
counter mode, SK is the output of SKL in the shift register
mode, SK outputs SKL ANDed with internal instruction cycle
clock.
p +
0
RESET
u
p
p
L
y
::::
III
Vee
:~ ~~
E
R
S
The EN register is an internal 4-bit register loaded under
program control by the LEI instruction. The state of each bit
of this register selects or deselects the particular feature
associated with each bit of the EN register (EN3-ENo).
1. The least significant bit of the enable register, ENo, selects the SIO register as either a 4-bit shift register or a
4-bit binary counter. With ENo set, SIO is an asynchronous binary counter, decrementing its value by one upon
I
"I:t'
a.
o
........
-1.2
DEVICE a. (;2
DEVICE d (;2
AND I (;2
C")
oo
Source Current for
Standard Output
- 0.4
t--p.,rl--+-+--"Irl--+~--I
-0.2 I-.",......c~++--+--¥=---J--I
O'--__....,I;;;=-_'--__-I.........::~
4
,....
"I:t'
a.
o
o
5
o
6
0.5
VIN (VOLTS)
Source Current for SO
and SK In Push-Pull
Configuration
I--I\-_+_-t+-+I--++-+--+--i
1.5
..
~
0.5
0.5
....&...-=---..
o
0'---'---'-.::::000_......
1
3
4
..
VOH(VOLTS)
IMIN ([,
VCC=7.SV
I
-
!---l IMAX ~l
o
1
I
1.0
t--t+_+_-t--1I--++_+__t--t
j
I
:'Ii :m"
3
4
r--
7
0.5
8
3
VOH(VOLTS)
LED Output Source
Current (for Low Current
LED Option)
5
1.5 r-T""""~-rr....,...r--~D=-=E~VI':':CE:-g-:#~5
1.0
IMIN@'
VCC=4.5V
4
Source Current for LO-L7
In TRI-STATE Configuration
(Low Current Option)
DEVICE g#5
E
o
3
VOH (VOLTS)
Source Current for LO-L7
In TRI-STATE Configuration
(High Current Option)
1.5 I"""'T-r-~~r-r--"""""':':DE::-:V""IC::-E-c#~2
AND #3
1.0
1.5
VI/O (VOLTS)
4
7
8
VOH(VOLTS)
LED Output Source
Current (for High Current
LED Option)
Output Sink Current for
SO and SK
-30r-'-~-'~~~'--r~
- 50 f-+--A.--+-I--+--+--t-----l
-20
- 40
C
t--~._+_-\t-t---+--+--t--I
c
§.
§. - 30 I-H-+--f\--r'!--\-I--+--+--+-----l
:z: -15
§
0
-10
- 20
f-+--+--\t~~+--+--+-----l
-5
-10
I-+----t-''I-t~~ct--t--t---(
0
0
3
6
4
0"---'----'---'---'----'
o
7
VOH (VOLTS)
VOH (VOLTS)
Output Sink Current for
LO-L7 and Standard Drive
Option for 00-03 and GO-G3
4r-rrr----,....---~r_~__,
VOL!VOLTS)
Output Sink Current
for 00-03 with Very High
Current Option
120
Output Sink Current
for 00-03 (for
High Current Option)
120 r-T""TI---r--,---,---.---.----,
,........,rT"T-r~--:-=:_::_......,...,..,.,.".-.,
100 1-+-t..:..:r=-:r:""":":T'-+-+---t--i
100
80
c
~
40
HT+-~__i-+-_+__t-+-~
60
40
itJlllt:::t:::4;;;:;t;=-i
20
0---'----'----"---.......---1
o
3
VOL(VOLTS)
4
VOL(VOLTS)
FIGURE ab. COP310L/COP311L Input/Output Characteristics
1-64
3
4
7
8
VOL!VOLTS)
TL/DD/6919-23
o
o
COP410L/411 L Instruction Set
"tJ
Table II is a symbol table providing internal architecture, in·
struction operand and operational symbols used in the in·
struction set table.
Table III provides the mnemonic, operand, machine code,
data flow, skip conditions and description associated with
each instruction in the COP41 OLl411 L instruction set.
....o
0l:Io
r........
o
o
"tJ
........
0l:Io
TABLE II. COP410L/411L Instruction Set Table Symbols
Symbol
Definition
Symbol
r........
o
DefInItion
o
INTERNAL ARCHITECTURE SYMBOLS
INSTRUCTION OPERAND SYMBOLS
A
8
8r
8d
C
D
EN
G
L
M
4·bit Operand Field, 0-15 binary (RAM Digit Select)
2·bit Operand Field, 0-3 binary (RAM Register
Select)
9·bit Operand Field, 0-511 binary (ROM Address)
a
y
4·bit Operand Field, 0-15 binary (Immediate Data)
RAM(s) Contents of RAM location addressed by s
ROM(t) Contents of ROM location addressed by t
PC
Q
SA
S8
SID
SK
"tJ
d
r
4·bit Accumulator
6·bit RAM Address Register
Upper 2 bits of 8 (register address)
Lower 4 bits of 8 (digit address)
1·bit Carry Register
4·bit Data Output Port
4·bit Enable Register
4·bit Register to latch data for G I/O Port
8·bitTRI·STATE I/O Port
4·bit contents of RAM Memory pointed to by 8
Register
9·bit ROM Address Register (program counter)
8·bit Register to latch data for L I/O Port
9·bit Subroutine Save Register A
9·bit Subroutine Save Register 8
4·bit Shift Register and Counter
Logic·Controlied Clock Output
OPERATIONAL SYMBOLS
+
~
~
=
A
G)
:
Plus
Minus
Replaces
Is exchanged with
Is equal to
The one's complement of A
Exclusive·OR
Range of values
TABLE III. COP410L/411L InstructIon Set
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
DescriptIon
SkIp Conditions
Data Flow
ARITHMETIC INSTRUCTIONS
Carry
Add with Carry, Skip on
Carry
None
Add RAMtoA
Carry
Add Immediate, Skip on
Carry (y *- 0)
A
None
Clear A
10100100001
A~A
None
One's complement of A to A
44
10100101001
None
None
No Operation
RC
32
10011100101
"0"
C
None
ResetC
SC
22
10010100101
"1"~C
None
SetC
XOR
02
10000100101
A ED RAM(8)
None
Exciusive·OR RAM with A
ASC
30
10011100001
A + C + RAM(8)
Carry ~ C
ADD
31
10011100011
A+ RAM(8)
5-
10101 1 y 1
A+y
~
CLRA
00
10000100001
o~
COMP
40
NOP
AISC
y
~
~
~
A
A
1·65
~
A
A
....o
W
r........
o
o
"tJ
........
rW
..J
---o
C")
Q.
Instruction Set (Continued)
TABLE III. COP41 OL/411 L Instruction Set (Continued)
o
"..J
Q
--
Mnemonic
Operand
Hex
Code
C")
Q.
o
o
:::J
---~
Skip Conditions
DataFlow
Description
TRANSFER OF CONTROL INSTRUCTIONS
JID
JMP
a
JP
a
Q.
o
o
"..J
Machine
Language Code
{Binary}
-o
1111111111 I
6-
1011O lOOOIaei
a7:0
I
I
a
11 I a6:0
I
(pages 2,3 only)
or
111 I a5:0
I
(all other pages)
a ~ PC6:0
---
Q
~
--
Q.
o
JSRP
a
ROM (PCs.A,M) ~
PC7:0
FF
--
110 I
I
a5:0
~
PC
None
Jump Indirect (Note 2)
None
Jump
None
Jump within Page
(Note 3)
a ~ PC5:0
PC+ 1
~
SA
~
SB
None
Jump to Subroutine Page
(Note 4)
~
SB
None
Jump to Subroutine
010 ~ PCS:6
a ~ PC5:0
JSR
a
PC + 1 ~ SA
a ~ PC
--
6-
101101100 I ael
a7:0
I
I
RET
48
1010011000 I
SB
~
SA
~
PC
None
Return from Subroutine
RETSK
49
10100110011
SB
~
SA
~
PC
Always Skip on Return
Return from Subroutine
then Skip
A ~ Q7:4
RAM (B) ~ Q3:0
None
Copy A, RAM to Q
MEMORY REFERENCE INSTRUCTIONS
CAMQ
LD
r
LQID
10011 I
11100 I
33
3C
10011
10011
-5
100lrl01011
RAM (B) ~ A
Br e r ~ Br
None
Load RAM into A,
Exclusive-OR Br with r
BF
11011111111
ROM(PCa,A,M) ~ Q
SA ~ SB
None
Load Q Indirect (Note 2)
RMB
0
1
2
3
4C
45
42
43
10100111001
1010010101 I
10100100101
1010010011 I
o~
o~
o~
o~
RAM(B)o
RAM(B)1
RAM(B)2
RAM(Bb
None
Reset RAM Bit
5MB
0
1
2
3
4D
47
46
4B
10100111011
1010010111 I
10100101101
10100110111
1 ~ RAM(B)o
1 ~ RAM(B)1
1 ~ RAM(B)2
1 ~ RAM(Bb
None
Set RAM Bit
STII
y
7-
10111 I y
y ~ RAM (B)
Bd + 1 ~ Bd
None
Store Memory Immediate
and Increment Bd
X
r
-6
100lrl 0110 1
RAM (B) ~ A
Br e r ~ Br
None
Exchange RAM with A,
Exclusive-OR Br with r
XAD
3,15
23
BF
1001010011 I
11011111111
RAM(3,15)
None
Exchange A with RAM
(3,15)
XDS
r
-7
100 I r I 0111
I
RAM (B) ~ A
Bd-1 ~ Bd
Br e r ~ Br
Bd decrements past 0
Exchange RAM with A
and Decrement Bd,
Exclusive-OR Br with r
XIS
r
-4
100 I r I 0100 I
RAM(B) ~ A
Bd + 1 ~ Bd
Br e r ~ Br
Bd increments past 15
Exchange RAM with A
and Increment Bd
Exclusive-OR Br with r
I
~
1-66
A
0
a"'0
Instruction Set (Continued)
0l:Io
-A.
TABLE III. COP410L/411L Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
0
r
Skip Conditions
Description
'"
0
a"'0
0l:Io
-A.
-A.
REGISTER REFERENCE INSTRUCTIONS
CAB
50
10101 10000 I
A ~ Bd
CBA
4E
10100111101
Bd
~
--
100 I r I (d - 1) I
(d = 0,9:15)
r,d
~
None
Copy A to Bd
A
None
Copy Bd to A
B
Skip until not a LBI
Load B Immediate with
r,d (Note 5)
r
0
'"
a
"'0
W
-A.
LBI
LEI
r,d
y
33
6-
10011 10011 I
10110 1 y I
y
~
EN
Load EN Immediate
(Note 6)
None
10010100001
C
=
"1"
Skip if C is True
I
A
=
RAM(B)
Skip if A Equals RAM
=
Skip if G is Zero
(all 4 bits)
SKC
20
SKE
21
1001010001
SKGZ
33
21
10011100111
1001010001 I
0
1
2
3
33
01
11
03
13
10011 10011 I
10000100011
1000110001 I
10000100111
10001 10011 1
0
1
2
3
01
11
03
13
10000100011
1000110001 I
1000010011 I
10001 10011 I
SKMBZ
G3:0
0
Skip if G Bit is Zero
1st byte
} 2nd byte
Go
G1
G2
G3
=
=
=
=
0
0
0
0
RAM(B)o
RAM(Bh
RAM(B)2
RAM(Bb
=
=
=
=
0
0
0
0
Skip if RAM Bit is Zero
INPUTIOUTPUT INSTRUCTIONS
10011 10011 I
10010110101
G~A
None
Input G Ports to A
2A
INL
33
2E
10011 10011 1
10010111101
L7:4 ~ RAM (B)
L3:0 ~ A
None
Input L Ports to RAM, A
OBO
33
3E
10011 10011 I
10011111101
Bd
None
Output Bd to 0 Outputs
OMG
33
3A
10011 10011 I
10011110101
RAM (B) ~ G
None
Output RAM to G Ports
A ~ SIO,C ~ SKL
None
ING
33
~
D
Exchange A with SIO
(Note 2)
Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to N where
XAS
r
0
'"
a
"'0
w
-A.
-A.
r
TEST INSTRUCTIONS
SKGBZ
0
4F
1010011111 1
o signifies the least significant bit (low-order, right-most bit). For example, A3 indicates the most significant (left-most) bit of the 4-bit A register.
Note 2: For additional information on the operation of the XAS, JID, and LQID instructions, see below.
Note 3: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction,
otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Note 4: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of Pl. A JSRP may not be used when in pages 2 or 3. JSRP
may not jump to the last word in page 2.
Note 5: The machine code for the lower 4 bits of the LBI instruction equals the binary value of the "d" data minus 1, e.g., to load the lower four bits of B (Bd) with
the value 9 (10012), the lower 4 bits of the LBI instruction equal 8 (10002). To load 0, the lower 4 bits of the LBI instruction should equal 15 (11112).
Note 6: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a "1" or "0" in each bit of EN corresponds
with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
1-67
........
...I
C")
a..
o
o
......
o
...I
....
Description of Selected Instructions
Option List
The following information is provided to assist the user in
understanding the operation of several unique instructions
and to provide notes useful to programmers in writing
COP41 OLl411 L programs.
The COP41 OLl411 L mask-programmable options are assigned numbers which correspond with the COP410L pins.
The following is a list of COP41 OL options. The LED Direct
Drive option on the L Lines cannot be used if higher Vee
option is selected. When specifying a COP411 L chip, Option
2 must be set to 3, Options 20, 21, and 22 to O. The options
are programmed at the same time as the ROM pattern to
provide the user with the hardware flexibility to interface to
various I/O components using little or no external circuitry.
C")
a..
o
......
o
XAS INSTRUCTION
o
....
XAS (Exchange A with SIO) exchanges the 4-bit contents of
the accumulator with the 4-bit contents of the SIO register.
The contents of SIO will contain serial-in/serial-out shift register or binary counter data, depending on the value of the
EN register. An XAS instruction will also affect the SK output. (See Functional Description, EN Register, above.) If
SIO is selected as a shift register, an XAS instruction must
be performed once every 4 instruction cycles to effect a
continuous data stream .
a..
JID INSTRUCTION
....
....
...I
~
a..
o
......
o
...I
~
oo
Option 1 = 0: Ground Pin -
no options available
Option 2: CKO Output (no option available for COP411 L)
= 0: Clock output to ceramic resonator
= 1: Pin is RAM power supply (VR) input
= 3: No connection
Option 3: CKI Input
= 0: Oscillator input divided by 8 (500 kHz max)
= 1: Single-pin RC controlled oscillator divided by 4
= 2: External Schmitt trigger level clock divided by 4
Option 4: RESET Input
= 0: Load device to Vee
= 1: Hi-Z input
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location pointed
to indirectly by A and M. It loads the lower 8 bits of the ROM
address register PC with the contents of ROM addressed by
the 9-bit word, PCa, A, M. PCa is not affected by this instruction.
Option 5: L7 Driver
= 0: Standard output
= 1: Open-drain output
= 2: High current LED direct segment drive output
= 3: High current TRI-STATE push-pull output
= 4: Low-current LED direct segment drive output
= 5: Low-current TRI-STATE push-pull output
Note that JID requires 2 instruction cycles to execute.
LQID INSTRUCTION
LQID (Load Q Indirect) loads the 8-bit Q register with the
contents of ROM pointed to by the 9-bit word PCa, A, M.
LQID can be used for table lookup or code conversion such
as 8CD to seven-segment. The LQID instruction "pushes"
the stack (PC + 1 -+ SA -+ S8) and replaces the least
significant 8 bits of PC as follows: A -+ PC7:4, RAM(8)
-+ PC3:0, leaving PCa unchanged. The ROM data pointed
to by the new address is fetched and loaded into the Q
latches. Next, the stack is "popped" (S8 -+ SA -+ PC),
restoring the saved value of PC to continue sequential program execution. Since LQID pushes SA -+ S8, the previous contents of S8 are lost. Also, when LQID pops the
stack, the previously pushed contents of SA are left in S8.
The net result is that the contents of SA are placed in S8
(SA -+ S8). Note that LQID takes two instruction cycle
times to execute.
Option 6: L6 Driver
same as Option 5
Option 7: Ls Driver
same as Option 5
Option 8: L4 Driver
same as Option 5
Option 9: Operating voltage
COP41XL
= 0: + 4.5V to + 6.3V
= 1: +4.5V to +9.5V
Option 10: L3 Driver
same as Option 5
INSTRUCTION SET NOTES
a. The first word of a COP41 OLl411 L program (ROM address 0) must be a CLRA (Clear A) instruction.
Option 11: L2 Driver
same as Option 5
Option 12: L1 Driver
same as Option 5
b. Although skipped instructions are not executed, one instruction cycle time is devoted to skipping each byte of
the skipped instruction. Thus all program paths except
JID and LQID take the same number of cycle times
whether instructions are skipped or executed. JID and
LQID instructions take 2 cycles if executed and 1 cycle if
skipped.
Option 13: Lo Driver
same as Option 5
Option 14: SI Input
= 0: load device to Vee
= 1: Hi-Z input
Option 15: SO Driver
= 0: Standard Output
= 1: Open-drain output
= 2: Push-pull output
c. The ROM is organized into 8 pages of 64 words each.
The Program Counter is a 9-bit binary counter, and will
count through page boundaries. If a JP, JSRP, JID or .
LQID instruction is located in the last word of a page, the
instruction operates as if it were in the next page. For
example: a JP located in the last word of a page will jump
to a location in the next page. Also, a LQID or JID located
in the last word of page 3 or 7 will access data in the next
group of 4 pages.
Option 16: SK Driver
same as Option 15
1-68
COP31XL
+ 4.5V to + 5.5V
+4.5V to +7.5V
o
Option List
o"'a
(Continued)
Option 17: Go 1/0 Port
= 0: Standard output
= 1: Open-drain output
Option 25: L Input Levels
= 0: Standard TTL input levels ("0" = 0.8V, "1" = 2.0V)
= 1: Higher voltage input levels ("0" = 1.2V, "1" = 3.6V)
Option 18: G1 1/0 Port
same as Option 17
Option 26: G Input Levels
same as Option 25
Option 19: G2 1/0 Port
same as Option 17
Option 27: SllflPut Levels
same as Option 25
Option 20: G3 1/0 Port (no option available for COP411 L)
same as Option 17
Option 28: COP Bonding
= 0: COP410L (24-pin device)
= 1: COP411 L (20-pin device)
= 2: Both 24- and 20-pin versions
Option 21: D3 Output (no option available for COP411 L)
= 0: Very-high sink current standard output
= 1: Very-high sink current open-drain output
= 2: High sink current standard output
= 3: High sink current open-drain output
= 4: Standard LSTTL output (fanout = 1)
= 5: Open-drain LSTTL output (fanout = 1)
"'a
0l:Io
...A.
...A.
r.......
o
o
"'a
W
...A.
The SO output has been configured to provide for standard
test procedures for the custom-programmed COP410L.
With SO forced to logic "1", two test modes are provided,
depending upon the value of SI:
a. RAM ~nd Internal Logic Test Mode (SI = 1)
b: ROM Test Mode (SI = 0)
Option 23: D1 Output
same as Option 21
These special test modes should not be employed by the
user; they are intended for manufacturing test only.
Option 24: Do Output
same as Option 21
Option Table
The following option information is to be sent to National along with the EPROM.
OPTION
1 VALUE =
OPTION
Option Data
0
Option Data
IS: GROUND PIN
OPTION 15 VALUE =
IS: SO DRIVER
2 VALUE =
IS: CKO PIN
OPTION 16 VALUE =
IS: SK DRIVER
OPTION
3 VALUE =
IS: CKI INPUT
OPTION 17 VALUE =
IS: Go 1/0 PORT
OPTION
4 VALUE =
IS: RESET INPUT
OPTION 18 VALUE =
IS: G1 1/0 PORT
OPTION
5 VALUE =
IS: L(7) DRIVER
OPTION 19 VALUE =
IS: G2 1/0 PORT
OPTION
6 VALUE =
IS: L(6) DRIVER
OPTION 20 VALUE =
IS: G3 1/0 PORT
OPTION
7 VALUE =
IS: L(5) DRIVER
OPTION 21 VALUE
OPTION
8 VALUE =
IS: L(4) DRIVER
OPTION 22 VALUE =
IS: D2 OUTPUT
OPTION
9 VALUE =
OPTION 23 VALUE =
IS: D1 OUTPUT
OPTION 10 VALUE =
IS: Vee PIN
IS: L(3) DRIVER
=
IS: Do OUTPUT
OPTION 11 VALUE =
IS: L(2) DRIVER
OPTION 25 VALUE =
OPTION 12 VALUE =
IS: L(1) DRIVER
IS: L INPUT LEVELS
OPTION 13 VALUE =
IS: L(O) DRIVER
OPTION 26 VALUE =
OPTION 14 VALUE =
IS: SIINPUT
IS: G INPUT LEVELS
OPTION 27 VALUE =
IS: SIINPUT LEVELS
OPTION 28 VALUE =
IS: COPS BONDING
OPTION 24 VALUE
1-69
=
0
o
TEST MODE (NON-STANDARD OPERATION)
Option 22: D2 Output (no option available for COP411 L)
same as Option 21
0l:Io
...A.
~
IS: D3 OUTPUT
o
r.......
o
o"'a
W
...A.
...A.
r-
..J
C")
'9"'"
C")
D.
o
o
.......
~National
~ Semiconductor
..J
C")
'9"'"
-.::t
D.
o
o
COP413L/COP313L Single Chip Microcontrollers
General Description
Features
The COP413L and COP313L Single-Chip N-Channel Microcontrollers are members of the COPSTM family, fabricated
using N-channel, silicon gate MOS technology. These Control Oriented Processors are complete microcomputers containing all system timing, internal logic, ROM, RAM, and I/O
necessary to implement dedicated control functions in a variety of applications. Features include single supply operation, 15 I/O lines with an instruction set, internal architecture
and I/O scheme designed to facilitate keyboard input, display output and BCD data manipulation. They are an appropriate choice for use in numerous human interface control
environments. Standard test procedures and reliable highdensity fabrication techniques provide the medium to large
volume customers with a customized Control Oriented Processor at a very low end-product cost.
•
•
•
•
•
•
•
•
•
The COP313L is an exact functional equivalent but extended temperature version of the COP413L.
•
•
•
•
Low cost
Powerful instruction set
512 x 8 ROM, 32 x 4 RAM
15 I/O lines
Two-Level subroutine stack
16,."s instruction time
Single supply operation (4.5V-6.3V)
Low current drain (6 mA max.)
Internal binary counter register with MICROWIRETM
serial I/O capability
General purpose outputs
High noise immunity Inputs (VIL = 1.2V, VIH=3.6V)
Software/hardware compatible with other members of
COP400 family
Extended temperature range device COP313L (-40·C
to +85·C)
The COP401 L-R 13 and COP410L-X13 should be used for
exact emulation.
Block Diagram
CK)
GND
VCC
L
La
~1O
CKD
t"
INSTRUCTION CLOCK (SYNC)
SK
l
,...--------t.....::..- so, M{CROW)RE 110
51
1.
11
20
1
3
•
,
a
TL/DD/8371-1
FIGURE 1
1-70
o
o-a
COP413L Absolute Maximum
Ratings
DC Electrical Characteristics
Parameter
Standard Operating Voltage
(Vee)
Total Source Current
25mA
Total Sink Current
25mA
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
o°c =:; T A=:;+ 70°C, 4.5V =:; Vee =:; 6.3V unless otherwise noted.
Conditions
(Note 1)
Power Supply Ripple
Peak to Peak
Operating Supply Current
All Inputs and Outputs
Open
Input Voltage Levels
CKllnput Levels
Ceramic Resonator Input (-+- 8)
Logic High (VIH)
Logic Low (VIU
CKI (RC), Reset Input Levels
Logic High
Logic Low
SO Input Level (Test Mode)
Sllnput Level
Logic High
Logic Low
L, G Inputs
Logic High
Logic Low
Min
Max
Units
4.5
6.3
V
0.4
V
6
mA
0.4
V
V
3.0
(Schmitt Trigger Input)
0.7 Vee
0.6
(Note 2)
2.5
(TTL Level)
2.0
(High Trip Levels)
-1
Reset Input Leakage
V
V
V
0.8
V
V
1.2
V
V
3.6
Input Capacitance
Output Current Levels
Output Sink Current
SO and SK Outputs (IoU
LO-L7 Outputs, GO-G3
CKO(loU
Output Source Current
LO-L7 and GO-G3
SO and SK Outputs (IOH)
Push-Pull
0.3 Watt at 70°C
Power Dissipation COP413L
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Offlce/
Distributors for availability and specifications.
Voltage at Any Pin Relative to GND
-0.3 to +7V
Ambient Operating Temperature
O°Cto + 70°C
Ambient Storage Temperature
- 65°C to + 150°C
Lead Temp. (Soldering, 10 seconds)
300°C
7
pF
+1
p.A
VOL =O.4V
VOL =O.4V
VOL =O.4V
0.9
0.4
0.2
mA
mA
mA
VOH=2.4V
VOH=1.0V
VOH= 2.4V
-25
-1.2
-25
p.A
mA
p.A
VIL =OV
-10
-140
p.A
Total Sink Current Allowed
L7-L4, G Port
L3-LO
Any Other Pin
4
4
2.0
mA
mA
mA
Total Source Current Allowed
Each Pin
1.5
mA
Sllnput Load Source Current
Note 1: Vee voltage change must be less than O.SV in a 1 ms period to maintain proper operation.
Note 2: SO output
"a .. level must be less than O.BV for normal operation.
1-71
~
.....
w
r.......
o
o-a
w
.....
w
r-
..J
....
C")
C")
D-
oo
......
..J
....
C")
~
D-
O
o
COP313L Absolute Maximum
Ratings
Power Dissipation COP313L
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Dlstrlbutor~ for availability and specifications•
Voltage at Any Pin Relative to GND '
-0.3 to +7V
Ambient Operating Temperature
- 40°C to + 85°C
Ambient Storage Temperature
- 65°C to + 150°C
Lead Temp. (Soldering, 10 seconds)
300°C
DC ElectriC?al Characteristics
Paraineter
Standard Operating Voltage
(Vee>
-40°C
25mA
Total Sink Current
25mA
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specific'!.tions are not ensured when operating the device at absolute '!'aximum ratings.
~ TA ~ +85°C,4.5V ~ Vee ~ 5.5V unless otherwise noted.
Conditions
{Note 1)
'Nlln
Max
Units
'4.5
5.5
V
..
Power Supply Ripple
Peak to Peak
Operating Supply Current
All Inputs and Outputs
Open
Input Voltage L~vels
Ceramic Resonator Input (-;- 8)
Logic Hig~ (VIH)
Logic Low (VIU
CKI (RC), Reset Input Levels
Logic High
Logic Low
SO Input (Test Mode)
Sllnput Level
Logic High
Logic Low
L, G Inputs
Logic High
Logic Low
0.20 Watt at 85°C
Total Source Current
0.4
V
8
mA
0.3
V
V
3.0
(Schmitt Trigger Input)
0.7 Vee
0.4
(Note 2)
2.5
(TTL Level)
2.2
(High Trip Levels)
0.6
V
V
1.2
V
V
3.6
Input Capacitance
-2
Reset Input Leakage
V
V
V
7
pF
+2
/LA
Output Current Levels
Output Sink Current
SO and SK Outputs (Iou
LO-L7 Outputs, GO-G3 (Iou
CKO(lou
Output Source Current
LO-L7 and GO-G3
SO and SK Outputs (IOH)
(Push-Pull)
VOL =O.4V
VOL =9.4V
VOL=O.4V
0.8
0.4
0.2
mA
mA
mA
VOH=2.4V
VOH=1.0V
VOH=2.4V
-23
-1.0
-23
/LA
mA
/LA
Sllnput Load Source Current
VIL ~OV
-10
-200
/LA
Total Sink Current Allowed
L7-L4, G Port
L3-LO
Any Other Pin
4
4
1.5
mA
mA
mA
Total Source Current Allowed
Each Pin
1.5
mA
Note 1: Vee voltage change must be less than 0.5V in a 1 ms period to maintain proper operation.
Note 2: SO 'output "0" level must be less than O.6V for normal operation.
1-72
0
a"C
AC Electrical Characteristics COP413L: o·c ~ TA ~ 70·C, 4.5V ~ Vee ~
6.3V
COP313L: -40·C ~ TA ~ + 85·C, 4.5V ~ Vee ~ 5.5V
Parameter
Min
Conditions
Instruction Cycle Time - tc
CKI
Input Frequency - fi
Duty Cycle
Rise Time
Fall Time
+8 Mode
Max
Units
16
40
p's
0.2
30
0.5
60
500
200
MHz
%
ns
ns
16
28
p.s
1.3
p's
p's
fi=0.5 MHz
CKI Using RC (+ 4)
oI:lIo
.......
w
R=56 kO ±5%
C= 100 pF ± 10%
Instruction Cycle Time (Note 1)
Inputs:
G3-GO, L7-LO
tSETUP
tHOLD
8.0
tSETUP
tHOLD
2.0
1.3
SI
p.s
p.s
1.0
Output Propagation Delay
Test Condition:
CL =50 pF, RL =20 kO, VOUT= 1.5V
SO, SK Outputs
tpd1, tpdO
All Other Outputs
tpd1, tpdO
4.0
p's
5.6
p.s
Note 1: Variation due to the device included.
Connection Diagram
Pin Descriptions
Pin
Description
L7-LO
G3-GO
8-bit bidirectional 1/0 port
4-bit bidirectional 1/0 port
Serial input (or counter
input)
Serial output (or general
purpose output)
Logic-controlled clock (or
general purpose output)
System oscillator input
System oscillator output or
NC
System reset input
Power Supply
Ground
S.O. Wide and DIP
L4
lS
l6
l7
vee
LJ
SI
L2
SO
L1
LO
SI
SK
sa
SK
GND
CKI
CKO
TL/DD/8371-2
FIGURE 2
RESET
Order Number COP313L-XXX/D or COP413L-XXX/D
See NS Hermetic Package Number D20A
Vee
GND
Order Number COP313L-XXX/WM or
COP413L-XXX/WM
See NS Surface Mount Package Number M20B
Order Number COP313L-XXX/N or COP413L-XXX/N
See NS Molded Package Number N20A
FIGURE 3. Input/Output Timing Diagrams (Ceramic Resonator Dlvlde-by-8 Mode)
1-73
r
........
0
a"C
w
.......
w
r
..J
C")
,...
C")
c..
oo
.......
..J
,...
C")
~
c..
o
o
Functional Description
Bd VALUE
A block diagram of the COP413L is given in Figure 1. Data
paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. Positive logic is
used. When a bit is set, it is a logic "1" (greater than 2V).
When a bit is reset, it is a logic "0" (less than 0.8V).
All functional references to the COP413L also apply to the
COP313L.
RAM DIGIT
IS'
14'
13'
12'
II'
10'
g'
PROGRAM MEMORY
Program Memory consists of a 512-byte ROM. As can be
seen by an examination of the COP413L instruction set,
these words may be program instructions, program data, or
ROM addressing data. Because of the special characteristics associated with the JP, JSRP, JID and LaiD instructions, ROM must often be thought of as being organized into
8 pages of 64 words each.
ROM addressing is accomplished by a 9-bit PC register. Its
binary value selects one of the 512 8-bit words contained in
ROM. A new address is loaded into the PC register during
each instruction cycle. Unless the instruction is a transfer of
control instruction, the PC register is loaded with the next
sequential 9-bit binary count value. Two levels of subroutine
nesting are implemented by the 9-bit subroutine save registers, SA and SB, providing a last-in, first out (LIFO) hardware subroutine stack.
0'
'CAN BE DIRECTl Y ADDRESSED BY
lBIINSTRUCTION (SEE TABLE 3)
TLlDD/8371-4
FIGURE 4. RAM Digit Address to
Physical RAM Digit Mapping
The a register is an internal, latched, 8-bit register, used to
hold data loaded from M and A, as well as 8-bit data from
ROM. Its contents are output to the L 1/0 ports when the L
drivers are enabled under program control. (See LEI instruction.)
ROM instruction words are fetched, decoded and executed
by the Instruction Decode, Control and Skip Logic circuitry.
DATA MEMORY
Data memory consists of a 128-bit RAM, organized as 4
data registers of 8 4-bit digits. RAM addressing is implemented by a 6-bit B register whose upper 2 bits (Br) select 1
of 4 data registers and lower 3 bits of the 4-bit Bd select 1 of
8 4-bit digits in the selected data register. While the 4-bit
contents of the selected RAM digit (M) is usually loaded into
or from, or exchanged with, the A register (accumulator), it
may also be loaded into the a latches or loaded from the L
ports. RAM addressing may also be performed directly by
the XAD 3, 15 instruction.
The 8 L drivers, when enabled, output the contents of
latched a data to the L 1/0 ports. Also, the contents of L
may be read directly into A and M.
The most significant bit of Bd is not used to select a RAM
digit. Hence each physical digit of RAM may be selected by
two different values of Bd as shown in Figure 4 below. The
skip condition for XIS and XDS instructions will be true if Bd
changes between 0 and 15, but NOT between 7 and 8 (see
Table III).
The XAS instruction copies C into the SKL Latch. In the
counter mode, SK is the output of SKL in the shift register
mode, SK outputs SKL ANDed with internal instruction cycle
clock.
The SIO register functions as a 4-bit serial-in/serial-out shift
register or as a binary counter depending on the contents of
the EN register. (See EN register description, below.) Its
contents can be exchanged with A, allowing it to input or
output a continuous serial data stream. SIO may also be
used to provide additional parallel 1/0 by connecting SO to
external serial-in/parallel-out shift registers.
The EN register is an internal 4-bit register loaded under
program control by the LEI instruction. The state of each bit
of this register selects or deselects the particular feature
associated with each bit of the EN register (EN3-ENo).
INTERNAL LOGIC
The 4-bit A register (accumulator) is the source and destination register for most 1/0, arithmetic, logic and data memory
access operations. It can also be used to load the Bd portion of the B register, to load 4 bits of the 8-bit a latch data,
to input 4 bits of the 8-bit L 1/0 port data and to perform
data exchanges with the SIO register.
1. The least significant bit of the enable register, ENo selects the SIO register as either a 4-bit shift register or a 4bit binary counter. With ENo set, SIO is an asynchronous
binary counter, decrementing its value by one upon each
low-going pulse ("1" to "0") occurring on the SI input.
Each pulse must be at least two instruction cycles wide.
SK outputs the value of SKL. The SO output is equal to
the value of EN3. With ENo reset, SIO is a serial shift
register shifting with each instruction cycle time. The data
present at SO goes into the least significant bit of SIO.
SO can be enabled to output the most significant bit of
SIO each cycle time. (See 4 below.) The SK output becomes a logic-controlled clock.
A 4-bit adder performs the arithmetic and logic functions of
the COP413L, storing its results in A. It also outputs a carry
bit to the 1-bit C register, most often employed to indicate
arithmetic overflow. The C register, in conjunction with the
XAS instruction and the EN register, also serves to control
the SK output. C can be outputted directly to SK or can
enable SK to be a sync clock each instruction cycle time.
(See XAS instruction and EN register description, below.)
2. EN1 is not used. It has no effect on COP413L operation.
The G register contents are outputs to 4 general purpose
bidirectional 1/0 ports.
1-74
0
Functional Description
0
(Continued)
"tJ
~
-4
TABLE I. Enable Register Modes· Bits EN3 and ENo
w
r......
EN3
ENo
SIO
SI
SO
SK
0
0
Shift Register
0
1
0
Shift Register
Input to Shift
Register
Input to Shift
Register
Input to Binary
Counter
Input to Binary
Counter
If SKL= 1, SK= Clock
IfSKL=O,SK=O
If SKL= 1, SK=Clock
If SKL=O, SK=O
IfSKL=1,SK=1
IfSKL=O, SK=O
IfSKL=1,SK=1
If SKL=O, SK=O
0
1
Binary Counter
1
1
Binary Counter
Serial
Out
0
1
3. With EN2 set, the L drivers are enabled to output the data
in Q to the L 1/0 ports. Resetting EN2 disables the L
drivers, placing the L 1/0 ports in a high impedance input
state.
There are two basic clock oscillator configurations available
as shown by Figure 6.
4. EN3, in conjunction with ENo, affects the SO output. With
ENo set (binary counter option selected) SO will output
the value loaded into EN3. With ENo reset (serial shift
register option selected), setting EN3 enables SO as the
output of the SIO shift register, outputting serial shifted
data each instruction time. Resetting EN3 with the serial
shift register option selected disables SO as the shift register output; data continues to be shifted through SIO and
can be exchanged with A via an XAS instruction but SO
remains reset to "0". Table I provides a summary of the
modes associated with EN3 and ENo.
b. RC Controlled Oscillator. CKI is configured as a single pin
RC controlled Schmitt trigger oscillator. The instruction
cycle equals the oscillation frequency divided by 4. CKO
becomes no connection.
OSCILLATOR
a. Resonator Controlled Oscillator. CKI and CKO are connected to an external ceramic resonator. The instruction
cycle frequency equals the resonator frequency divided
by 8.
A
B
INITIALIZATION
eKI
The Reset Logic will initialize (clear) the device upon powerup if the power supply rise time is less than 1 ms and greater than 1 /Ls. If the power supply rise time is greater than 1
ms, the user must provide an external RC network and diode to the RESET pin as shown below (Figure 5). The
RESET pin is configured as a Schmitt trigger input. If not
used it should be connected to Vee. Initialization will occur
whenever a logic "0" is applied to the RESET input, provided it stays low for at least three instruction cycle times.
CKO
~
.. ~~!-
:~
S
.
~
-ta -I
-J-
y -
Vee
t
(N/C)
*
~
~
A __
yyy
~
.~ RI
:: ~e2
CKO
-I.I.A
..,y
C'
TLlDD/8371-6
I
FIGURE 6. COP413L Oscillator
VCC
Ceramic Resonator Oscillator
RESET COP413L
U
~::~
L
~
... R2
P + -........ot.....- - -.....
~
CKI
GND
_ 6 -_ _ _ _-11
Resonator
Value
R1 (0.)
Component Values
R2 (n)
C1 (pF)
455 kHz
4.7k
1M
220
I C2 (pF)
I 220
RC;;. 5 x POWER SUPPL Y RISE TIME
RC Controlled Oscillator
TL/DD/8371-5
FIGURE 5. Power-Up Clear Circuit
Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, EN, and G registers are cleared.
The SK output is enabled as a SYNC output, providing a
pulse each instruction cycle time. Data Memory (RAM) is
not cleared upon initialization. The first instruction at address 0 must be a CLRA.
R (kn)
C (pF)
51
100
82
56
Note: 200 ko. ~ R ~ 25 kO
220
1-75
pF~C~50
pF
Instruction
Cycle Time
(In /Ls)
19
19
±
±
15%
13%
0
0
"tJ
w
-4
W
r-
~
C")
"P-
C")
r---------------------------------------------------------------------------------,
Functional Description
(Continued)
D-
o
u
:::J
C")
"P-
0IIIt
D-
oU
a. Standard Output
c. Standard L Output
b. Push-Pull Output
Vee
IN'UT~(
IN'UT I8J----I ~
e. HI-Z Input
d. Input with Load
TL/DD/8371-7
FIGURE 7. Input and Output Configurations
enhancement-mode device to Vee. This configuration
has been provided to allow for fast rise and fall times
when driving capacitive loads.
c. LO-L7-same as a., but may be disabled.
d. SI has on-chip depletion load device to Vee.
e. RESET has a Hi-Z input which must be driven to a "1" or
"0" by external components.
110 CONFIGURATIONS
COP413L inputs and outputs have the following configurations, illustrated in Figure 7:
a. GO-G3-an enhancement mode device to ground in
conjunction with a depletion-mode device to Vee.
b. SO, SK-an enhancement mode device to ground in conjunction with a depletion-mode device paralleled by an
1·76
o
a"'0
Typical Performance Characteristics
Input Current for LO
through L7 when
Output Programmed
Off by Software
Input Current, SI
-200
DEVICE h
-100
-90
-80
-70
-60 ill...
~ -50
5 -40
!i
-30
-20
-10
16
-150
~iiE
~IAAXO VCC =..·5V
T "I \ \
tJ,1'i'N~
.1 1
I
l
-50
a
~~ ...:
a
DEVICEc.2
:!
1"-o~1iIo..
-100
Source Current L7-LO,
G3-GO Standard
Output Configuration
:!
%
"
9
"- IMAX@VCC-4.5L
~r
ffil~'N~VCC"4.5V-
I Til
~~lcci4.r-- rt--!-..
o
Vicrr
o
1 2 3 .. 5 6 7 8 9 lQ
o~
o1 2
1
VI/O (VOlIS)
VIN (VOLTS)
Source Current for SO
and SK (Push-Pull
Configuration)
-1000
DEVICE •• 2
-900
ANDc.2
-800
-700
-600
-500
-400 ~M~@~CCI=4i5V
-300
-200
-100
Output Sink Current for
LO-L7, GO-G3
(Standard Drive)
4~~--~--~~--~
4~~--~--~--.r~
1.0 ......t-+--I--+---+--+-t--t-t--I
!
9.5
VOH (VOLTS)
Output Sink Current for
SO and SK
1.5 /"""IT-.,..-.r-"'T""-r-.,.....................-,
'I
3 4 5 6 7 8
2 H---I+---t--+--t--;
9
0.5
1--I-tf~I-+--t-+-t-+--+-t
OL-~---~---~~--~
O~~~~~~~~~
o1
-250
o
2 3 4 5 6 7 8 9 10
VOH (VOlIS)
Input Current, SI
-150
~ -100
-50
o
'" ~
VOL (VOLTS) TL/DD/8371-8
FIGURE 8a. COP413L 1/0 DC Current Characteristics
Input Current for LO-L7
when Output Programmed Off by Software
-120 r----.,.......--'--r----"'T""---,
~~AX 5 x Power Supply Rise Time
and RC > 100 x CKI Period
4. ENS, in conjunction with ENO, affects the SO output. With
ENO set (binary counter option selected), SO will output
the value loaded into ENS. With ENO reset (serial shift
FIGURE 5. Power-Up Clear Circuit
TABLE I. Enable Register Modes-Bits ENO and EN3
ENO
EN3
SIO
SI
SO
0
0
Shift Register
0
0
1
Shift Register
1
1
0
1
Binary Counter
Binary Counter
Input to Shift
Register
Input to Shift
Register
Input to Counter
Input to Counter
1-90
Serial
out
0
1
SK
If SKL = 1, SK
If SKL = 0, SK
If SKL = 1, SK
If SKL = 0, SK
SK = SKL
SK = SKL
= clock
= 0
= clock
= 0
o
Functional Description
o
-a
(Continued)
0l:Io
HALT MODE
The COP413C is a fully static circuit; therefore, the user may
stop the system oscillator at any time to halt the chip. The
chip may be halted by the HALT instruction. Once in the
HALT mode, the internal circuitry does not receive any clock
signal, and is therefore frozen in the exact state it was in
when halted. All information is retained until continuing. The
HALT mode is the minimum power dissipation state.
The HALT mode may be entered into by program control
(HALT instruction) which forces CKO to a logic "1" state.
The circuit can be awakened only by the RESET function.
OSCILLATOR OPTIONS
There are two options available that define the use of CKI
and CKO.
a. Cyrstal-Controlled Oscillator. CKI and CKO are connected to an external crystal. The instruction cycle time
equals the crystal frequency divided by 8.
b. RC-Controlled Oscillator. CKI is configured as a single
pin RC-controlled Schmitt trigger oscillator. The instruction cycle equals the oscillation frequency divided by 4.
CKO is NC.
The RC oscillator is not recommended in systems that require accurate timing or low current. The RC oscillator
draws more current than an external oscillator (typically an
additional 100 /LA at 5V). However, when the part halts, it
stops with CKI high and the halt current is at the minimum.
POWER DISSIPATION
The lowest power drain is when the clock is stopped. As the
frequency increases so does current. Current is also lower
at lower operating voltages. Therefore, to minimize power
consumption, the user should run at the lowest speed and
voltage that his application will allow. The user should take
care that all pins swing to full supply levels to ensure that
outputs are not loaded down and that inputs are not at
some intermediate level which may draw current. Any input
with a slow rise or fall time will draw additional current. A
crystal- or resonator-generated clock will draw more than a
square-wave input. An RC oscillator will draw even more
current since the input is a slow rising signal.
If using an external squarewave oscillator, the following
equation can be used to calculate the COP413C current
drain.
...A.
W
o........
o
o-a
0l:Io
...A.
W
o
o
:::E:
........
o-a
w
...A.
W
o
........
o
o-a
w
...A.
W
o
:I:
B
A
..
I
~
R2
-'".t..t.
",
:~
J-::::I~
~
rv
::~C2
"==
R
......
---
~yyy
>
Ic = Iq +
x 20 x Fi) + (V X 1280 X FI/Dv)
where Ic = chip current drain in microamps
Iq = quiescent leakage current (from curve)
FI = CKI frequency in megahertz
CKO
CKI
CKO
CKI
RI
Vcc
t
HALT
~C
~~C1
TL/DD/8537-6
FIGURE 6. COP413C Oscillator
V = chip Vee in volts
Dv = divide by option selected
For example, at 5V Vee and 400 kHz (divide by 8),
Ic = 30 + (5 X 20 X 0.4) + (5 X 1280 X 0.4/8)
Ic
= 30 + 40 + 320 = 390 /LA
III
RC·Controlied
Oscillator
Crystal or Resonator
Crystal
Value
R1
R2
32kHz
455 kHz
2.000 MHz
220k
5k
2k
20M
10M
1M
Component Value
C1 pF
C2pF
30
80
30
5-36
40
6-36
R
C
Cycle
Time
82pF
15k
4-9/Ls
30k
82pF
8-16/Ls
100 pF
47k
16-32/Ls
100 pF
16-32/Ls
56k
Note: 15k ~ R ~ 150k,
50 pF ~ C ~ 150 pF
1-91
Vee
~
4.5V COP413CH Only
~ 4.5V COP413CH Only
3.0 to 4.5V COP413C Only
~ 4.5V
x
(.)
M
Functional Description
M
I/O CONFIGURATIONS
The SI and RESET inputs are Hi-Z inputs (Figure 7d).
o(.)
COP413C outputs have the following configurations, illustrated in Figure 7:
(.)
M
a. Standard SO, SK Output. A CMOS push-pull buffer with
an N-channel device to ground in conjunction with a
P-channel device to Vee, compatible with CMOS and
LSTIL.
When using the G I/O port as an input, set the output register to a logic "1" level. The P-channel device will act as a
pull-up load. When using the L I/O port as an input, disable
the L drivers with the LEI instruction. The drivers are then in
TRI-STATE mode and can be driven externally.
,....
D..
.......
,....
M
D..
o(.)
.......
X
(.)
M
,....
~
D..
o(.)
(Continued)
All output drivers use one or more of three common devices
numbered 1 to 3. Minimum and maximum current (lOUT and
VOUT) curves are given in Figure 8 for each of these devices
to allow the designer to effectively use these I/O configurations.
b. Low Current G Output. This is the same configuration as
(a) above except that the sourcing current is much less.
c. Standard TRI-STATE L Output. L output is a CMOS output buffer similar to (a) which may be disabled by program control.
.......
(.)
,....
M
~
D..
o(.)
a. Standard Push·Pull Output
b. Low Current Push·Pull Output
Vee
Vee
m'~f
-=c. Standard TRI·STATE
"L" Output
FIGURE 7. I/O Configurations
SO, SK, L Port, G Port
Minimum Sink Current
2.4
I
I
SI.SV -
2.0
~
1.0
1
It'
4.SV- t-t-
"J..,ofo-
1.2
1/: .....
OB
.,
IJ
'II
a
2.0
3D
4.0
SD
6D
1
1"1 r--"
1 1
a
aD
lD
2.0
VOL (VOLTS)
500 ~.5~
~5J
IT
I I
100
a
~
I I
1
aD
'" , , ,
~~
I I I'
a 11
~
1"1
3D
4.0
SD
r...
2.0
'"
'" ,I'\. ,
I'
3D
4.0
VOH (VOLTS)
SD
100
~~
1
6D
1\
aD
6.0
lD
2.0
1\
3D
o4D
1\
SD
6D
VOH(VOLTS)
Maximum Quiescent Current
50
"
~
"-
1'\
10
1\
~t.f·5y
1"'-
r-..
1'0.
60
f;;f--r.;} I'
1
lD
" 1"- I\..
COP313C/COP313CH
Low Current G Port
Maximum Source Current
500
I'
I'
r-r--t-;...
!'\
1'.
I I
1\
11
I'
20
600
I I
1-""
I I
VOH(VOLTS)
COP413C/COP413CH
Low Current G Port
Maximum Source Current
600
~~
50
4.SV
"'"
I I
3.0V
0.2
I I
I
lD
aD
I
G Port Low Current
Minimum Source Current
60
-11
I--~.SVI
0.4
I-~
I~V
1
s.sv
11 r--"",
~
1.6
'1'
SO, SK, L Port Standard
Minimum Source Current
I I
I I
1.2
TL/DD/8537-7
d. HI·Z Input
I
a
aD
lD
I"
"' I'
J
I\.
,
r...
",
4.0
SD
I'
2.0
3D
VOH(VOLTS)
FIGURE 8
1-92
V
V
V
20
l\
V
6D
a
850(;
700(;
j,...---" ~O(;
10
1\
/
a
2
3
4
Vcc(VOLTS)
TL/DD/8537-8
(')
a""C
COP413C Instruction Set
Table II is a symbol table providing internal architecture, instruction operand and operational symbols used in the instruction set table.
Table III provides the mnemonic, operand, machine code,
data flow, skip conditions and description associated with
each instruction in the COP413C instruction set.
~
~
w
(')
......
(')
a""C
~
~
w
TABLE II. COP413C Instruction Set Table Symbols
(')
Definition
::I:
......
INTERNAL ARCHITECTURE SYMBOLS
INSTRUCTION OPERAND SYMBOLS
A
8
8r
8d
C
EN
G
L
M
4-bit Operand Field, 0-15 binary (RAM Digit Select)
2-bit Operand Field, 0-3 binary (RAM Register
Select)
a
9-bit Operand Field, 0-511 binary (ROM Address)
y
4-bit Operand Field, 0-15 binary (Immediate Data)
RAM(s) Contents of RAM location addressed by s
ROM(t) Contents of ROM location addressed by t
a""C
Symbol
PC
Q
SA
S8
SID
SK
Definition
Symbol
4-bit Accumulator
6-bit RAM Address Register
Upper 2 bits of 8 (register address)
Lower 4 bits of 8 (digit address)
1-bit Carry Register
4-bit Enable Register
4-bit Register to latch data for G I/O Port
8-bit TRI-STATE I/O Port
4-bit contents of RAM Memory pointed to by 8
Register
9-bit ROM Address Register (program counter)
8-bit Register to latch data for L I/O Port
9-bit Subroutine Save Register A
9-bit Subroutine Save Register 8
4-bit Shift Register and Counter
Logic-Controlled Clock Output
(')
d
r
w
~
w
(')
......
(')
a""C
w
w
~
(')
::I:
OPERATIONAL SYMBOLS
+
~
~
=
A
11)
:
Plus
Minus
Replaces
Is exchanged with
Is equal to
The one's complement of A
Exclusive-OR
Range of values
TABLE III. COP413C Instruction Set
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Description
Skip Conditions
ARITHMETIC INSTRUCTIONS
~
Carry
Add with Carry, Skip on
Carry
None
Add RAM toA
Carry
Add immediate, Skip on
Carry (y =1= 0)
O~A
None
Clear A
10100100001
A~A
None
One's complement of A to A
44
10100101001
None
None
No Operation
RC
32
10011100101
"0"
C
None
ResetC
SC
22
10010100101
"1"~C
None
SetC
XOR
02
10000100101
A
None
Exclusive-OR RAM with A
ASC
30
10011100001
A + C + RAM(8)
Carry ~ C
ADD
31
10011100011
A + RAM(8)
5-
10101 1 y 1
A+y
CLRA
00
10000100001
COMP
40
NOP
AISC
Y
11)
~
~
~
A
A
RAM(8)
1-93
~
A
A
•
:c
o
Cf)
.....
Instruction Set
(Continued)
TABLE III. COP413C Instruction Set (Continued)
Cf)
D.
o
o
(3
Cf)
.....
Cf)
D.
Mnemonic
JID
JMP
a.
oo
.....
o
Cf)
.....
0II:t'
JP
a.
JSRP
.....
0II:t'
oo
Machine
Language Code
(Binary)
DataFlow
Skip Conditions
Description
TRANSFER OF CONTROL INSTRUCTIONS
oo
.....
:c
o
Cf)
Operand
Hex
Code
FF
11111111111
a
6-
a
-
-
a
-
ROM (PCs, A,M) -+
PC7:0
None
Jump Indirect (Note 2)
1011O lOOOlaai
I aZ'O I
a -+ PC
None
Jump
a6'Q I
111
(pages 2, 3 only)
or
1111 a!2'O I
(all other pages)
a -+ PCe:o
None
Jump within Page
(Note 1)
None
Jump to Subroutine Page
(Note 2)
PC + 1 -+ SA -+ S8
a -+ PC
None
Jump to Subroutine
110 1
a!2'O
I
a -+ PCs:o
PC
+1
-+ SA -+ S8
010 -+ PCS:6
a -+ PCs:o
6-
-
101101100 Iaa I
aZ'O
1
I
RET
48
1010011000 I
S8 -+ SA -+ PC
None
Return from Subroutine
RETSK
49
101001100111
S8 -+ SA -+ PC
Always Skip on Return
Return from Subroutine
then Skip
HALT
33
38
1001110011 I
10011 11000 I
None
Halt processor
JSR
a
MEMORY REFERENCE INSTRUCTIONS
CAMO
33
3C
1001110011 I
1001111100 I
A -+ 07:4
RAM(8) -+ 03:0
None
Copy A, RAM to 0
COMA
33
2C
1001110011 I
1001011100 I
07:4 -+ RAM(8)
03:0-+ A
None
Copy 0 to RAM, A
-5
100lrl01011
RAM(8) -+ A
8r EB r -+ 8r
None
Load RAM into A
Exclusive-OR 8r with r
BF
11011 11111 I
ROM(PCa.A,M) -+ 0
SA -+ S8
None
Load 0 Indirect
LD
r
LOID
RM8
0
1
2
3
4C
45
42
43
10100111001
10100101011
10100100101
10100100111
o -+
o -+
o -+
o -+
RAM(8)0
RAM(8h
RAM(8)2
RAM(8)3
None
Reset RAM 8it
SM8
0
1
2
3
4D
47
46
48
10100111011
10100101111
10100101101
10100110111
1
1
1
1
RAM(8)0
RAM(8h
RAM(8)2
RAM(8)3
None
Set RAM Bit
STII
Y
7-
10111 1
y -+ RAM(B)
Bd + 1 -+ 8d
None
Store Memory Immediate
and Increment 8d
X
r
-6
100lrl 0110 1
RAM(8) ~ A
8r EB r -+ 8r
None
Exchange RAM with A,
Exclusive-OR Br with r
XAD
3,15
23
BF
10010100111
11011111111
RAM(3,15)
None
Exchange A with RAM
(3,15)
'i 1
-+
-+
-+
-+
~
1-94
A
o
a"'a
Instruction Set (Continued)
~
....A.
TABLE III. COP413C Instruction Set (Continued)
W
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
Skip Conditions
Data Flow
Description
o
.......
o
o"'a
~
MEMORY REFERENCE INSTRUCTIONS (Continued)
....A.
W
XDS
XIS
r
r
-7
-4
100 1r 10111 1
100 1r 10100 1
RAM(B) ~ A
Bd - 1 -+ Bd
Br ED r -+ Br
Bd decrements past 0
RAM(B) ~ A
Bd + 1 -+ Bd
Br ED r -+ Br
Bd increments past 15
Exchange RAM with A
and Decrement Bd
Exclusive-OR Br with r
Exchange RAM with A
and Increment Bd
Exclusive-OR Br with r
Copy A to Bd
10101100001
A -+ Bd
4E
10100111101
Bd -+ A
None
Copy Bd toA
-
100 1r 1(d - 1) 1
(d = 0,9:15)
r,d -+ B
Skip until not a LSI
Load B Immediate with
r,d
33
10011100111
10010 1 y. 1
y -+ EN
None
Load EN Immediate
6SKC
20
10010100001
C
=
SKE
21
10010100011
A
= RAM (B)
SKGZ
33
21
10011100111
10010100011
G3:0
0
1
2
3
33
01
11
03
13
10011100111
10000100011
10001100011
10000100111
10010100111
0
1
2
3
01
11
03
13
10000100011
10001100011
10000100111
10001100111
50
CBA
LBI
r,d
LEI
y
None
SKMBZ
w
....A.
W
o
.......
o
w
....A.
W
TEST INSTRUCTIONS
SKGBZ
o
o"'a
o"'a
REGISTER REFERENCE INSTRUCTIONS
CAB
o
:l:
.......
Skip if C is True
"1"
=0
Skip if G is Zero
(all 4 bits)
Skip if G Bit is Zero
1st byte
} 2nd byte
Skip if A Equals RAM
Go
G1
G2
G3
=0
=0
=0
=0
RAM(B)o
RAM(Bh
RAM(B)2
RAM(Bb
=0
=0
=0
=0
Skip if RAM Bit is Zero
INPUT/OUTPUT INSTRUCTIONS
ING
33
2A
10011100111
10010110101
G-+A
None
Input G Ports to A
INL
33
2E
10011100111
10010111101
L7:4 -+ RAM (B)
L3:0 -+ A
None
Input L Ports to RAM, A
OMG
33
3A
10011100111
10011110101
RAM(B) -+ G
None
Output RAM to G Ports
XAS
4F
10100111111
A ~ SIO,C -+ SKL
None
Exchange A with SID
Note 1: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction,
otherwise, permits a jump to a ROM location within the current 64·word page. JP may not jump to the last word of a page.
Note 2: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of Pl. A JSRP may not be used when in pages 2 or 3. JSRP
may not jump to the last word in page 2.
1-95
o
:l:
~
o
Cf)
.....
a..
o
o.......
Cf)
o
Cf)
.....
a..
o
Cf)
o
.......
~
oCf)
.....
"I:t'
a..
oo
.......
o
Cf)
.....
"I:t'
a..
o
o
r-------------------------------------------------------------------------Description of Selected Instructions
The following information is provided to assist the user in
understanding the operation of several unique instructions
and to provide notes useful to programmers in writing
COP413C programs.
INSTRUCTION SET NOTES
a. The first word of a COP413C program (ROM address 0)
must be a CLRA (Clear A) instruction .
b. Although skipped instructions are not executed, one instruction cycle time is devoted to skipping each byte of
the skipped instruction. Thus all program paths take the
same number of cycle times whether instructions are
skipped or executed (except JID and LQID).
XAS INSTRUCTION
XAS (Exchange A with SIO) exchanges the 4-bit contents of
the accumulator with the 4-bit contents of the SIO register.
The contents of SIO will contain serial-in/serial-out shift register or binary counter data, depending on the value of the
EN register. An XAS instruction will also affect the SK output. (See Functional Description, EN Register.) If SIO is selected as a shift register, an XAS instruction must be performed once every four instruction cycle times to effect a
continuous data stream.
c. The ROM is organized into eight pages of 64 words each.
The program counter is a 9-bit binary counter, and will
count through page boundaries. If a JP, JSRP, JID, or
LQID instruction is located in the last word of a page, the
instruction operates as if it were in the next page. For
example: A JP located in the last word of a page will jump
to a location in the next page. Also, a LQID or JID located
in the last word in page 3 or 7 will access data in the next
group of four pages.
JID INSTRUCTION
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location pointed
to indirectly by A and M. It loads the lower eight bits of the
ROM address register PC with the contents of ROM addressed by the 9-bit word, PCa, A, M. PCa is not affected by
this instruction.
COPS Programming Manual
For detailed information on writing. COPS programs, the
COPS Programming Manual 424410284-001 provides an indepth discussion of the COPS architecture, instruction set
and general techniques of COPS programming. This manual
is written with the programmer in mind.
Note: JID uses two instruction cycles if executed. one if skipped.
LQID INSTRUCTION
LQID (Load Q Indirect) loads the 8-bit Q register with the
contents of ROM pointed to by the 9-bit word PCa, A, M.
LQID can be used for table look-up or code conversion such
as 8CD to 7-segment. The LQID instruction "pushes" the
stack (PC + 1 ~ SA ~ S8) and replaces the least
significant eight bits of the PC as follows: A ~ PC7:4,
RAM(8) ~ PC3:0, leaving PCa unchanged. The ROM data
pointed to by the new address is fetched and loaded into
the Q latches. Next, the stack is "popped" (S8 ~ SA ~
PC), restoring the saved value of the PC to continue sequential program execution. Since LQID pushes SA ~
S8, the previous contents of S8 are lost.
OPTION LIST-oSCILLATOR SELECTION
The oscillator option selected must be sent in with the
EPROM of ROM Code for masking into the COP413C. Select the appropriate option, make a photocopy of the table
and send it with the EPROM.
Note: LQID uses two instruction cycles if executed. one if skipped.
Note: The following option information is to be sent to National along with the EPROM.
Option 1: Value = _ _ is Oscillator Selected.
COP413C/COP313C
Option 1: Oscillator selection
= 0 Ceramic Resonator input frequency divided by 8.
CKO is oscillator output.
= 1 Single pin RC controlled oscillator divided by 4. CKO
is no connection.
1-96
o
~National
PRELIMINARY
~ Semiconductor
o
".....
~
~
r......
o
o
".....w
COP414L/COP314L Single-Chip N-Channel
Microcontrollers
~
r-
General Description
Features
The COP414L Single-Chip N-Channel Microcontrollers are
members of the COPSTM family, fabricated using N-channel, silicon gate MOS technology. This Controller Oriented
Processor is a complete microcomputer containing all system timing, internal logic, ROM, RAM and I/O necessary to
implement dedicated control functions in a variety of applications. Features include single supply operation, a variety
of output configuration options, with an instruction set, internal architecture and I/O scheme designed to facilitate keyboard input, display output and BCD data manipulation. The
COP414L is an appropriate choice for use in numerous human interface control environments. Standard test procedures and reliable high-density fabrication techniques provide the medium to large volume customers with a customized Controller Oriented Processor at a low end-product
cost.
• Late waferfab programming of ROM and I/O for fast
delivery of units
•
•
•
•
•
•
•
•
•
Low cost
Powerful instruction set
512 x 8 ROM, 32 x 4 RAM
15 I/O lines
Two-level subroutine stack
16 IJ-s instruction time
Single supply operation (4.5V-6.3V)
Low current drain (6 mA max)
Internal binary counter register with MICROWIRETM serial I/O capability
General purpose and TRI-STATE@ outputs
LSTILICMOS compatible in and out
Software/hardware compatible with other members of
COP400 family
Extended temperature range device
- COP314L (-40°C to +85°C)
Wider supply range (4.5V-9.5V) optionally available
•
•
•
The COP314L is an exact functional equivalent but extended temperature version of COP414L.
•
The COP414L can be emulated by the COP404C. The
COP401 L should be used for exact emulation.
•
Block Diagram
GND
~10
INSTRUCTlDNClDCK,SYNCI
.....-------t-..;;..,.. ::tMICROWIRE I/O
sJ
18
18
20
1
3
4
5
8
TL/DD/BB14-1
FIGURE 1. COP414L
1-97
-J
-.:I'
.....
Cf')
D.
oo
......
-J
-.:I'
.....
-.:I'
D.
o
o
r------------------------------------------------------------------------------------,
COP414L
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage at Any Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 sec.)
Power Dissipation
COP414L
-o.sv to + 10V
O°C to + 70°C
- 6SoC to + 1S0°C
DC Electrical Characteristics O°C ~ TA ~
Standard Operating Voltage (Vee)
Total Source Current
120mA
Total Sink Current
100mA
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
300°C
Parameter
0.6SW at 2SoC
0.3W at 70°C
+ 70°C, 4.SV
~
Vee
Conditions
(Note 1)
Optional Operating Voltage (Vee)
Power Supply Ripple
Peak to Peak
Operating Supply Current
All Inputs and Outputs Open
~
9.5V unless otherwise noted
Min
Max
Units
4.S
6.3
V
4.S
9.S
V
O.S
V
6
mA
Input Voltage Levels
CKllnput Levels
Ceramic Resonator Input (-;- 8)
Logic High (VIH)
Logic High (VIH)
Logic Low (VIIJ
Schmitt Trigger Input (-;- 4)
Logic High (VIH)
Logic Low (VILJ
RESET Input Levels
Logic High
Logic Low
Vee = Max
Vee = SV ±S%
3.0
2.0
-0.3
V
0.4
V
0.7 Vee
-0.3
0.6
V
V
0.7 Vee
-0.3
0.6
V
V
2.0
2.S
V
3.0
2.0
-0.3
3.6
-0.3
0.8
V
V
V
V
V
7
pF
-1
+1
p.A
0.4
V
V
0.2
V
V
(Schmitt Trigger Input)
SO Input Level (Test Mode)
(Note 2)
All Other Inputs
Logic High
Logic High
Logic Low
Logic High
Logic Low
Vee = Max
With TTL Trip Level Options
Selected, Vee = SV ±S%
With High Trip Level Options
Selected
Input Capacitance
Hi-Z Input Leakage
1.2
Output Voltage Levels
LSTTL Operation
Logic High (VOH)
Logic Low (Vou
Vee = SV ±10%
IOH = -2S p.A
IOL = 0.36 mA
2.7
CMOS Operation
Logic High
Logic Low
IOH = -10 p.A
IOL = +10 p.A
Note 1: Vee voltage change must be less than O.SV in a 1 ms period to maintain proper operation.
Note 2: SO output "0" level must be less than O.SV for normal operation.
1-98
Vee -1
COP414L
DC Electrical Characteristics o·c ~ TA ~
Parameter
+ 70·C, 4.5V
Conditions
$;
Vee
~
9.5V unless otherwise noted (Continued)
Min
Max
Units
Output Current Levels
Output Sink Current
SO and SK Ouputs (IoU
Vee = 9.5V, VOL = O.4V
Vee = 6.3V, VOL = O.4V
Vee = 4.5V, VOL = O.4V
1.8
1.2
0.9
mA
rnA
rnA
Lo-L7 Outputs, GO-G3 and
LSTTL Do-D3 Outputs (IoU
Vee = 9.5V, VOL = O.4V
Vee = 6.3V, VOL = O.4V
Vee = 4.5V, VOL = O.4V
0.4
0.4
0.4
rnA
rnA
rnA
CKI (Single-pin RC Oscillator)
CKO
Vee = 4.5, VIH = 3.5V
Vee = 4.5, VOL = O.4V
2
0.2
rnA
rnA
Output Source Current
Standard Configuration,
All Outputs (IOH)
Push-Pull Configuration
SO and SK Outputs (IOH)
Input Load Source Current
Vee = 9.5V, VOH = 2.0V
Vee = 6.3V, VOH = 2.0V
Vee = 4.5V, VOH = 2.0V
-140
-75
-30
Vee = 9.5V, VOH = 4.75V
Vee = 6.3V, VOH = 2.4V
Vee = 4.5V, VOH = 1.OV
-1.4
-1.4
-1.2
-800
-480
-250
p,A
p,A
p,A
rnA
rnA
rnA
-10
-140
p,A
-2.5
+2.5
p,A
Total Sink Current Allowed
All Outputs Combined
D Port
L7-L4, G Port
L3- LO
Any Other Pin
100
100
4
4
2.0
rnA
rnA
rnA
rnA
rnA
Total Source Current Allowed
All 1/0 Combined
L7- L4
L3- LO
Each L Pin
Any Other Pin
120
60
60
25
1.5
rnA
rnA
rnA
rnA
rnA
Vee = 5.0V, VIL = OV
Open Drain Output Leakage
1-99
..J
~
,...
C")
a.
o
o
.......
..J
~
,...
~
a.
oo
COP314L
Absolute Maximum Ratings
Voltage at Any Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
-0.5V to + 10V
Power Dissipation
COP314L
- 40°C to + 85°C
0.65W at 25°C
0.20W at 85°C
- 65°C to + 150°C
Lead Temperature
(Soldering, 10 seconds)
300°C
Total Source Current
120 rnA
Total Sink Current
100 rnA
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
DC Electrical Characteristics
COP314L: -40°C:::; T A :::; + 85°C, 4.5V :::; Vee:::; 7.5V unless otherwise noted
Parameter
Standard Operating Voltage (Vee)
Conditions
(Note 1)
Optional Operating Voltage (Vee)
Power Supply Ripple
Peak to Peak
Operating Supply Current
All Inputs and Outputs Open
Min
Max
Units
4.5
5.5
V
4.5
7.5
V
0.5
V
8
mA
3.0
2.2
-0.3
0.3
V
V
0.7 Vee
-0.3
0.4
V
V
0.7 Vee
-0.3
0.4
V
V
2.2
2.5
V
3.0
2.2
-0.3
3.6
-0.3
0.6
V
V
V
V
V
7
pF
-2
+2
p,A
0.4
V
V
0.2
V
V
Input Voltage Levels
Ceramic Resonator Input (-;- 8)
Crystal Input
Logic High (VIH)
Logic High (VIH)
Logic Low (Vld
Schmitt Trigger Input (-;- 4)
Logic High (VI H)
Logic Low (Vld
RESET Input Levels
Logic High
Logic Low
Vee = Max
Vee = 5V ±5%
(Schmitt Trigger Input)
SO Input Level (Test Mode)
(Note 2)
All Other Inputs
Logic High
Logic High
Logic Low
Logic High
Logic Low
Vee = Max
With TTL Trip Level Options
Selected, Vee = 5V ±5%
With High Trip Level Options
Selected
Input Capacitance
Hi-Z Input Leakage
1.2
Output Voltage Levels
LSTTL Operation
Logic High (VOH)
Logic Low (Vod
Vee = 5V ±10%
IOH = -20 p,A
IOL = 0.36 mA
2.7
CMOS Operation
Logic High
Logic Low
Note 1:
Vce voltage change
IOH = -10 p,A
IOL = + 10 p,A
must be less than 0.5V in a 1 ms period to maintain proper operation.
Note 2: SO output "0" level must be less than O.SV for normal operation.
1-100
Vee -1
o
o
COP314L
""C
DC Electrical Characteristics
0I:loo
-.
0I:loo
r........
o
(Continued)
COP314L: -40·C ~ TA ~ +85·C,4.5V ~ Vee ~ 7.5V unless otherwise noted
Parameter
Conditions
Min
Max
Units
Output Current Levels
o
""C
W
-.
0I:loo
r-
Output Sink Current
SO and SK Outputs(lou
Vee
Vee
Vee
Lo-L7 Outputs, GO-G3 and
LSTTL, Do-D3 Outputs (Iou
Vee
Vee
Vee
CKI (Single-pin RC Oscillator)
CKO
Vee
Vee
=
=
=
=
=
=
=
=
7.5V, VOL
5.5V, VOL
4.5V, VOL
= 0.4V
= O.4V
= O.4V
7.5V, VOL = O.4V
5.5V, VOL = 0.4V
4.5V, VOL = O.4V
4.5V, VIH = 3.5V
4.5V, VOL = O.4V
=
=
=
=
=
=
=
7.5V, VOH
5.5V, VOH
4.5V, VOH
1.4
1.0
0.8
mA
mA
mA
0.4
0.4
0.4
mA
mA
mA
1.5
0.2
mA
mA
Output Source Current
Standard Configuration,
All Outputs (IOH)
Vee
Vee
Vee
Push-Pull Configuration
SO and SK Outputs (IOH)
Vee
Vee
Vee
= 2.0V
= 2.0V
= 2.0V
7.5V, VOH = 3.75V
5.5V, VOH = 2.0V
4.5V, VOH = 1.0V
5.0V, VIL = OV
-100
-55
-28
-900
-600
-350
-0.85
-1.1
-1.2
/LA
/LA
/LA
mA
mA
mA
-10
-200
-5
+5
/LA
/LA
All Outputs Combined
100
mA
D Port
100
mA
L7-L4, G Port
4
mA
L3- LO
Any Other Pins
4
mA
1.5
mA
All 110 Combined
120
mA
L7- L4
L3- LO
60
mA
60
mA
Each L Pin
25
mA
Any Other Pins
1.5
mA
Input Load Source Current
Vee
Open Drain Output Leakage
Total Sink Current Allowed
Total Source Current Allowed
1-101
III
..J
"'I:t
c;;
AC Electrical Characteristics
~
COP414L: O°C
~
COP314L: -40°C ~ TA ~ +85°C,4.5V ~ Vee ~ 7.5Vunlessotherwisenoted
;;#
COP214L: -40°C ~ TA ~ + 110°C,4.5V ~ Vee ~ 7.5V unless otherwise noted
,...
Parameter
"'I:t
a..
oo
~ TA ~ 70°C, 4.5V ~ Vee ~ 9.5V unless otherwise noted
Conditions
Instruction Cycle Time - te
CKI
Input Frequency - fl
+8 Mode
+4 Mode
Duty Cycle
Rise Time
Fall Time
CKI Using RC ( + 4)
fl
=
0.5 MHz
R
C
=
=
56kfl ±5%
100pF ±10%
Min
Max
Units
16
40
J.Ls
0.2
0.1
30
0.5
0.25
60
500
200
MHz
MHz
%
28
J.Ls
16
Instruction Cycle Time (Note 1)
CKO as SYNC Input
tSYNe
Inputs
G3- GO, L7- LO
tSETUP
tHOLD
ns
ns
400
ns
8.0
1.3
J.Ls
J.Ls
2.0
1.0
J.Ls
J.Ls
51
tSETUP
tHOLD
Output Propagation Delay
Test Condition:
CL = 50 pF, RL
=
20 kfl, VOUT
=
1.5V
SO, SK Outputs
t pdl, tpdO
All Other Outputs
tpdl, tpdO
Note 1: Variation due to the device included.
4.0
J.Ls
5.6
J.Ls
Connection Diagram
Dual-In-Llne Package
L4-1
20~L5
Vcc- 2
19~L6
L3- 3
18~L7
L2_ 4
17
L1- 5
LO_ 6
51- 7
50-8
16~CKI
SK- 9
GND- 1D
12 t--G1
11 t--GD
Order Number COP214L-XXX/D,
COP314L-XXX/D or COP414L-XXX/D
See NS Hermetic Package D20A
~RESET
Order Number COP214L-XXX/N,
COP314L-XXX/N or COP414L-XXX/N
See NS Molded Package N20A
15~CKO
14~G3
Order Number COP214L-XXX/WM,
COP314L-XXX/WM or COP414L-XXX/WM
See NS Surface Mount Package M20B
13~G2
TL/DD/8814-2
Top View
FIGURE 2
Pin Descriptions
Pin
Pin
Description
Description
L7-LO
8 bidirectional 1/0 ports with TRI-STATE
CKI
System oscillator input
G3-GO
4 bidirectional 1/0 ports
Serial input (or counter input)
CKO
System oscillator output
51
SO
Serial output (or general purpose output)
Vee
Power supply
SK
Logic-controlled clock (or general purpose output)
GND
Ground
RESET System reset input
1-102
Timing Diagrams
CKI
S~~~~~
VOH
1",,-,~VO~l_ _ _ _ _ _~~1
1-'SETUP-II-'HOlO
G~'~~i~~~fs
ZZZZZZZZZZZZZZZZZZZZZZZ?l.
r-:,pol--1
G3- GO. 0 3- 0 0.
'II"Z"rZrZ"'Z'"'Z""ZZ""Z"rZrZ"'Z'"'ZZ""
IZZZZZ!fVOH
l7-LO. SO. SK
OUTPUTS
TL/DD/BB14-3
FIGURE 3. Input/Output Timing Diagrams (Ceramic Resonator Dlvlde-by-S Mode)
TL/DD/BB14-4
FIGURE 3a. Synchronization Timing
Functional Description
A block diagram of the COP414L is given in Figure 1. Data
paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. Positive logic is
used. When a bit is set, it is a logic "1" (greater than 2V).
When a bit is reset, it is a logic "0" (less than o.aV).
All functional references to the COP414L also apply to the
COP314L, and COP2141.
may also be loaded into the a latches or loaded from the L
ports. RAM addressing may also be performed directly by
the XAD 3,15 instruction.
The most significant bit of Bd is not used to select a RAM
digit. Hence each physical digit of RAM may be selected by
two different values of Bd as shown in Figure 4 below. The
skip condition for XIS and XDS instructions will be true if Bd
changes between 0 and 15, but NOT between 7 and a (see
Table III).
PROGRAM MEMORY
Program Memory consists of a 512-byte ROM. As can be
seen by an examination of the COP414L instruction set,
these words may be program instructions, program data or
ROM addressing data. Because of the special characteristics associated with the JP, JSRP, JID and LaiD instructions, ROM must often be thought of as being organized into
a pages of 64 words each.
Bd VALUE
RAM DIGIT
15·
14·
13·
1Z·
11·
ROM addressing is accomplished by a 9-bit PC register. Its
binary value selects one of the 512 a-bit words contained in
ROM. A new address is loaded into the PC register during
each instruction cycle. Unless the instruction is a transfer of
control instruction, the PC register is loaded with the next
sequential 9-bit binary count value. Two levels of subroutine
nesting are implemented by the 9-bit subroutine save registers, SA and SB, providing a last-in, first-out (UFO) hardware subroutine stack.
ROM instruction words are fetched, decoded and executed
by the Instruction Decode, Control and Skip Logic circuitry.
10·
9·
'Can be directly addressed by
LBI instruction (see Table III)
DATA MEMORY
Data memory consists of a 12a-bit RAM, organized as 4
data registers of a 4-bit digits. RAM addressing is implemented by a 6-bit B register whose upper 2 bits (Br) select 1
of 4 data registers and lower 3 bits of the 4-bit Bd select 1 of
a 4-bit digits in the selected data register. While the 4-bit
contents of the selected RAM digit (M) is usually loaded into
or from, or exchanged with, the A register (accumulator), it
o·
TLIDD/BB14-5
FIGURE 4. RAM Digit Address to
Physical RAM Digit Mapping
1-103
..J
,....
~
C")
c..
oo
.......
..J
,....
~
~
c..
oo
Functional Description
(Continued)
INTERNAL LOGIC
each low-going pulse ("1" to "0") occuring on the SI input. Each pulse must be at least two instruction cycles
wide. SK outputs the value of SKL. The SO output is
equal to the value of EN3. With ENo reset, SID is a serial
shift register shifting left each instruction cycle time. The
data present at SI goes into the least significant bit of
SID. SO can be enabled to output the most significant bit
of SID each cycle time. (See 4 below.) The SK output
becomes a logic-controlled clock.
The 4-bit A register (accumulator) is the source and destination register for most 110, arithmetic, logic and data memory
access operations. It can also be used to load the Bd portion of the B register, to load 4 bits of the a-bit latch data,
to input 4 bits of the a-bit L liD port data and to perform
data exchanges with the SID register.
a
A 4-bit adder performs the arithmetic and logic functions of
the COP414L, storing its results in A. It also outputs a carry
bit to the 1-bit C register, most often employed to indicate
arithmetic overflow. The C register, in conjunction with the
XAS instruction and the EN register, also serves to control
the SK output. C can be outputted directly to SK or can
enable SK to be a sync clock each instruction cycle time.
(See XAS instruction and EN register description, below.)
2. EN1 is not used. It has no effect on COP414L operation.
3. With EN2 set, the L drivers are enabled to output the data
in a to the L liD ports. Resetting EN2 disables the L
drivers, placing the L liD ports in a: high-impedance input
state.
4. EN3, in conjunction with ENo, affects the SO output. With
ENo set (binary counter option selected) SO will output
the value loaded into EN3. With ENo reset (serial shift
register option selected), setting EN3 enables SO as the
output of the SID shift register, outputting serial shifted
data each instruction time. Resetting EN3 with the serial
shift register option selected disables SO as the shift register output; data continues to be shifted through SID and
can be exchanged with A via an 'XAS instruction but SO
remains reset to "0". Table I provides a summary of the
modes associated with EN3 and ENo.
The G register contents are outputs to 4 general-purpose
bidirectional liD ports.
The a register is an internal, latched, a-bit register, used to
hold data loaded from M and A, as well as a-bit data from
ROM. Its contents are output to the L liD ports when the L
drivers are enabled under program control. (See LEI instruction.)
. .
The a L drivers, when enabled, output the contents of
latched a data to the L liD ports. Also, the contents of L
may be read directly into A and M.
INITIALIZATION
The SID register functions as a 4-bit serial-in serial-out shift
register or as a binary counter depending on the cont~nts of
the EN register. (See EN register description, below.) Its
contents can be exchanged ~ith A, allowing. it to input or
output a continuous serial data stream. SID may also be
used to provide additional parallel liD by connecting SO to
external serial-in/parallel-out shift registers ..
The Reset Logic will initialize (clear) the device upon powerup if the power supply rise time is less than 1 ms and greater than 1 p,s. If the power supply rise time is greater than
1 ms, the user must provide an external RC network and
diode to the RESET pin as shown below (Figure 5). The
RESET pin is configured as a Schmitt trigger input. If not
used it should be connected to Vee. Initialization will occur
whenever a logic "0" is applied to the RESET input, provided it stays low for at least three instruction cycle times.
The XAS instruction copies C into the SKL Latch. In the
counter mode, SK is the output' of SKL in the shift register
mode, SK outputs SKL ANDed with internal instruction cycle
clock.
'
p +
The EN register is an internal 4-bit register loaded under
program control by the LEI instruction. The state of each bit
of this register selects or deselects the particular feature
associated with each bit of the EN register (EN3-ENo).
... 1>
_!-
:1> .4~
I
Vee
Rrnf COP410L
11
1. The least significant bit of the enable register, ENo, selects the SID register as either a 4-bit shift register or a
4-bit binary counter. With ENo set, SID is an asynchronous binary counter, decrementing its value by one upon
::r:
vRC
GNO
I
~
5 x Power Supply Rise Time
TL/DD/BB14-6
FIGURE 5. Power-Up Clear Circuit
TABLE I. Enable Register Modes-Bits EN3 and ENo
so
EN3
ENo
SIO
SI
0
0
Shift Register
Input to Shift Register
0
1
0
Shift Register
Input to Shift Register
Serial Out
0
1
Binary Counter
Input to Binary Counter
0
1
1
Binary Cou,nter
Input to Binary Counter
1
1-104
SK
If SKL
If SKL
If SKL
If SKL
If SKL
If SKL
If SKL
If SKL
= 1, SK = Clock
= 0, SK = 0
= 1, SK = Clock
= 0, SK = 0
= 1, SK = 1
= 0, SK = 0
= 1, SK = 1
= 0, SK = 0
o
Functional Description
o""C
(Continued)
Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, 0, EN and G registers are cleared.
The SK output is enabled as a SYNC output, providing a
pulse each instruction cycle time. Data Memory (RAM) is
not cleared upon initialization. The first instruction at address 0 must be a CLRA.
c. RC Controlled Oscillator. CKI is configured as a single
pin RC controlled Schmitt trigger oscillator. The instruction cycle equals the oscillation frequency divided by 4.
CKO is no connection.
CKO PIN OPTIONS
In a resonator controlled oscillator system, CKO is used as
an output to the resonator network. CKO is no connection
for External or RC controlled oscillator.
1/0 OPTIONS
CKI
eKO
CKI
R2
'"'
.........
t
t
A
COP414L inputs and outputs have the following optional
configurations, illustrated in Figure 7:
CKO
a. Standard-an enhancement-mode device to ground in
conjunction with a depletion-mode device to Vee, compatible with LSTTL and CMOS input requirements. Available on SO, SK and all 0 and G outputs .
N/C
.Jl..f"
EXTERNAL
~
CLOCK
b. Open-Drain-an enhancement-mode device to ground
only, allowing external pull-up as required by the user's
application. Available on SO, SK and all 0 and G outputs.
CKI
c. Push-Pull-an enhancement-mode device to ground in
conjunction with a depletion-mode device paralleled by
an enhancement-mode device to Vee. This configuration
has been provided to allow for fast rise and fall times
when driving capacitive loads. Available on SO and SK
outputs only.
CKO
VCC
t
N/C
d. Standard L-same as a., but may be disabled. Available
on L outputs only.
TL/DD/8814-7
e. Open Drain L-same as b., but may be disabled. Available on L outputs only.
Ceramic Resonator Oscillator
Components Values
Resonator
Value
R1 (0)
455 kHz
4.7k
I R2 (0)
I 1M
C1 (pF)
220
1. An on-chip depletion load device to Vee.
g. A Hi-Z input which must be driven to a "1" or "0" by
external components.
The above input and output configurations share common
enhancement-mode and depletion-mode devices. Specifically, all configurations use one or more of six devices
(numbered 1-6, respectively). Minimum and maximum current (lOUT and VOUT) curves are given in Figure 8 for each
of these devices to allow the designer to effectively use
these 1/0 configurations in designing a COP414L system.
The SO, SK outputs can be configured as shown in a., b., or
c. The G outputs can be configured as shown in a. or b.
Note that when inputting data to the G ports, the G outputs
should be set to "1". The L outputs can be configured as in
d., or e.
An important point to remember if using configuration d.
with the L drivers is that even when the L drivers are disabled, the depletion load device will source a small amount
of current. (See Figure 8, device 2.) However, when the L
port is used as input, the disabled depletion device CANNOT be relied on to source sufficient current to pull an input
to a logic "1".
I C2 (pF)
I 220
RC Controlled Oscillator
R(kO)
C (pF)
Instruction
Cycle Time
in JLs
51
100
56
19 ±15%
19 ±13%
82
Note: 200 k!1 ;;>: R ;;>: 25 k!1. 360 pF ;;>: C ;;>: 50 pF. Does not include tolerances.
FIGURE 6. COP414L Oscillator
OSCILLATOR
There are four basic clock oscillator configurations available
as shown by Figure 6.
a. Resonator Controlled Oscillator. CKI and CKO are
connected to an external ceramic resonator. The instruction cycle frequency equals the resonator frequency divided by 8.
b. External Oscillator. CKI is an external clock input signal.
The external frequency is divided by 4 to give the instruction frequency time. CKO is no connection.
1-105
0l:Io
.....
0l:Io
r.......
o
o""C
W
.....
0l:Io
r-
...J
....
'II:t
C"')
Functional Description
D-
oo
(Continued)
a. Standard Output
b. Open-Drain Output
c. Push-Pull Output
......
...J
....
'II:t
'II:t
D-
Tl/DD/6614-9
O
o
Tl/DD/6614-6
Tl/DD/6614-10
d. Standard L Output
e. Open-Drain L Output
·
"~"'~i
TlIDD/6614-12
TlIDD/6614-11
f. Input with Load
g. Hi-Z Input
..
, "'~{
Vcc
MJ
#6
'''"'~f
Tl/DD/6614-14
Tl/DD/6614-13
FIGURE 7. Input and Output Configurations
Typical Performance Curves
Input Current for LO through
L7 when Output Programmed
Off by Software
Input Current RESET, SI
-200
.--~~-r--r-~~-r--r---r.,
-100
DEVICE d #2
AND f #2
-90
-80
-150
~
z
-70
~
-100
...
0
::::>
0
-liD
-50
-10
o
__U
1.0 2.0 3.0 4.0 5.0 6.0 7.0 B.O
9.5
,i\.
.....
-40
-20
oL-~~~=====*~
1\.1 MAX fiil Vec = 9.5 V
-50
-30
Source Current for Standard
Output Configuration
-1000 r--r--r--r--r--r-r--'--'---n
DEVICE. #2
-900 ~t-t-t-t-+-+-tANI d #2
"
-800I-Prl-,-+-+-+-+-+-+-H
-300 ~~~~MIN fiill-=HHH,--H
~~
MINfelVCC-4.5V
~N@Vec·
.1
T
1'\..1
IMAX fiil
-400 ~Vcc = 4.5~--+~"r-+--+--+--H
~
VCC=4.5V
' \ IMAX fiil Vcc = 9.5 V
-liDO
E -SOD
~
IMAX~
o
o
-700 I-t-f'l.....
n--+-t--+-+-+-H
~
:\..
~
.5V
~
I
r--.;;: ~
....
1.0
~1~~~Vc+c_·~·5VI
6~'~-r~H
IMIN'"
r....
D'-~ \/vr:c = 9.5\:~~
-200 .-100
2.0
r-!-f.,...; ~ T"'"I'-I-~
o
1
vila
VIN (VOLTS)
2
3
4
5
6
7
8
9.5
VO H (VOLTS)
TlIDD/8614-15
Source Current for SO and SK in
Push-Pull Configuration
1.5
r-T1r-'1--rr--r"'"'"T''''"'T''"'''"'T''"=:-'~
1.0
I-f+--+~-+-t-H-~-t--+--I
Output Sink Current For
SO and SK
Output Sink Current for LO-L7,
and Standard Drive
Option for GO-G3
4,,~--.--.~.--,
0.5
a
OL---I.-.....J..--'--........- - I
1
o
2
VOHIYOlTSI
VOL(VOLTS)
0"'-----1._--'-_-'-_........- - 1
o
YOl(VOLTSI
TlIDD/6614-16
FIGURE 8a. COP414 1/0 DC Current Characteristics
1-106
o
o"0
Typical Performance Curves (Continued)
~
-""
Input Current for LO-L7
when Output Programmed
Off by Software
Input Current RESET, SI
-120 ....---T--"""T'"---.----.
-250 """;""-""--'--'-"""'T'"-r-,.--,
-1.2
~
Source Current for
Standard Output
Configuration
r......
r-...-...,--.-r-o---....-"---'
"0
o
o
CN
-100
-200 ~k--+-+--+-_+-+-t--l
~-+--_+--'-'Tc.c...:.--I
1 -80
~-150
=z -100 1--+--4-''''t:--+--+--+~--i
-1.0 i--->111---+--+--+--+---If---t--I
-0.8 I--t--'k---+--+--+---If---t--I
~ -60 I-----..Ji~..__+_,...._-+---I
~
j
-0.6
::>
!i? -40
-0.4 I-"""'-+--+--+-"'w+---If--+---I
-20
o ~I!!!!!!!!!!!!!!I!_.bb...L...J.J..J
o
1
2
3
o~_~~~_~_~
o
4
0.5
1.5
12345678
VI/O (VOLTSI
VIN (VOLTSI
VOH (VOlTSl
Source Current for SO
and SK In Push-Pull
Configuration
1.5 .-...,.......,...,...,...."""T'".....,,-:D==EV""IC==E-c...~2
AND ... 3
1.0 t---ft--t-tt--H--tH-t--t
0.5
O~.L--"';"";:--~-==--""
012345678
VOH(VOLTSI
FIGURE ab. COP314L Input/Output Characteristics
1-107
TLIDD/BBI4-17
-""
~
r-
-J
-.::r
'P'"
CWO)
a.
o
o
.......
-J
r---------------------------------------------------------------------------------------~
COP414L Instruction Set
Table II is a symbol table providing internal architecture, instruction operand and operational symbols used in the instruction set table.
Table III provides the mnemonic, operand, machine code,
data flow, skip conditions and description associated with
each instruction in the COP414L instruction set.
-.::r
'P'"
-.::r
a.
o
o
TABLE II. COP414L Instruction Set Table Symbols
Symbol
Definition
Symbol
Definition
INTERNAL ARCHITECTURE SYMBOLS
INSTRUCTION OPERAND SYMBOLS
A
B
Br
Bd
C
d
r
o
EN
G
L
M
PC
Q
SA
SB
SIO
SK
4-bit Accumulator
6-bit RAM Address Register
Upper 2 bits of B (register address)
Lower 4 bits of B (digit address)
1-bit Carry Register
4-bit Data Output Port
4-bit Enable Register
4-bit Register to latch data for G I/O Port
8-bitTRI-STATE I/O Port
4-bit contents of RAM Memory pointed to by B
Register
9-bit ROM Address Register (program counter)
8-bit Register to latch data for L I/O Port
9-bit Subroutine Save Register A
9-bit Subroutine Save Register B
4-bit Shift Register and Counter
Logic-ContrOlled Clock Output
4-bit Operand Field, 0-15 binary (RAM Digit Select)
2-bit Operand Field, 0-3 binary (RAM Register
Select)
a
9-bit Operand Field, 0-511 binary (ROM Address)
y
4-bit Operand Field, 0-15 binary (Immediate Data)
RAM(s) Contents of RAM location addressed by s
ROM(t) Contents of ROM location addressed by t
OPERATIONAL SYMBOLS
+
-
----+
~
=
A
EEl
:
Plus
Minus
Replaces
Is exchanged with
Is equal to
The one's complement of A
Exclusive-OR
Range of values
TABLE III. COP414L Instruction Set
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
ARITHMETIC INSTRUCTIONS
ASC
30
10011100001
A + C + RAM (B) ----+ A
Carry ----+ C
ADD
31
10011100011
A
+
5-
10101 1 y 1
A
+ Y ----+
CLRA
00
10000100001
COMP
40
NOP
Carry
Add with Carry, Skip on
Carry
None
Add RAM to A
Carry
Add Immediate, Skip on
Carry (y =1= 0)
0----+ A
None
Clear A
10100100001
A----+A
None
One's complement of A to A
44
10100101001
None
None
No Operation
RC
32
10011100101
"0" ----+ C
None
ResetC
SC
22
10010100101
"1" ----+ C
None
SetC
XOR
02
10000100101
A EEl RAM (B) ----+ A
None
Exclusive-OR RAM with A
AISC
Y
RAM (B) ----+ A
A
1-108
COP414L Instruction Set (Continued)
TABLE III. COP414L Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
DataFlow
Description
Skip Conditions
TRANSFER OF CONTROL INSTRUCTIONS
JID
JMP
a
JP
a
1111111111
6-
10110 1000la61
I aZ'Q I
a
11 I a6:0
I
(pages 2, 3 only)
or
a5:0
1111
I
(all other pages)
a ~ PC6:0
----
JSRP
a
I
FF
--
110 I
ROM (PCs,A,M)
PC7:0
I
a5:0
~
PC
None
Jump Indirect (Note 2)
None
Jump
None
Jump within Page
(Note 3)
None
Jump to Subroutine Page
(Note 4)
None
Jump to Subroutine
None
Return from Subroutine
a ~ PC5:0
PC
+1
~
SA ~ SB
010 ~ PCS:6
a ~ PC5:0
PC + 1 ~ SA ~ SB
a ~ PC
--
6-
101101100 Ia61
a7:0
1
I
RET
48
1010011000 I
SB
RETSK
49
10100110011
SB ~ SA ~ PC
Always Skip on Return
Return from Subroutine
then Skip
A ~ Q7:4
RAM (B) ~ Q3:0
None
Copy A, RAM to Q
JSR
a
~
SA
~
PC
MEMORY REFERENCE INSTRUCTIONS
CAMQ
LD
r
LQID
10011 I
11100 I
33
3C
10011
10011
-5
100lrl01011
RAM(B) ~ A
Br ED r ~ Br
None
Load RAM into A,
Exclusive-OR Br with r
BF
11011111111
ROM(PCs, A, M) ~ Q
SA ~ SB
None
Load Q Indirect (Note 2)
RMB
0
1
2
3
4C
45
42
43
1010011100 I
1010010101 I
10100100101
1010010011 I
o~
o~
o~
o~
RAM(B)o
RAM(Bh
RAM(B)2
RAM(B)3
None
Reset RAM Bit
5MB
0
1
2
3
4D
47
46
4B
10100111011
1010010111 I
10100101101
10100110111
1 ~ RAM(B)o
1 ~ RAM(Bh
1 ~ RAM(B)2
1 ~ RAM(Bb
None
Set RAM Bit
STII
y
7-
10111 1 y
I
y ~ RAM(B)
Bd + 1 ~ Bd
None
Store Memory Immediate
and Increment Bd
X
r
-6
100lrl 0110 1
RAM(B) ~ A
Br ED r ~ Br
None
Exchange RAM with A,
Exclusive-OR Br with r
XAD
3,15
23
BF
1001010011
11011 11111
None
Exchange A with RAM
(3,15)
XDS
r
-7
100 Ir 10111 1
RAM (B) ~ A
Bd -1 ~ Bd
Br ED r ~ Br
Bd decrements past 0
Exchange RAM with A
and Decrement Bd,
Exclusive-OR Br with r
XIS
r
-4
100 Ir 10100 I
RAM(B) ~ A
Bd + 1 ~ Bd
Br ED r ~ Br
Bd increments past 15
Exchange RAM with A
and Increment Bd
Exclusive-OR Br with r
I
I
RAM(3, 15)
~
1-109
A
...I
"II:t
,....
C")
D.
COP414L Instruction Set (Continued)
0
TABLE III. COP414L Instruction Set (Continued)
0
.......
...I
"II:t
,....
Mnemonic
Operand
"II:t
Hex
Code
D.
0
0
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
REGISTER REFERENCE INSTRUCTIONS
CAB
50
10101100001
A - . Bd
None
Copy A to Bd
CBA
4E
10100111101
Bd - . A
None
Copy8d toA
LBI
r,d
--
1001rl(d - 1)1
(d = 0,9:15)
r,d - . B
Skip until not a LBI
Load B Immediate with
r,d (Note 5)
LEI
Y
33
6-
1001110011 I
10010 1 y I
y - . EN
None
Load EN Immediate
(Note 6)
SKC
20
10010100001
c=
"1"
Skip if C is True
SKE
21
1001010001
I
A
RAM (B)
Skip if A Equals RAM
SKGZ
33
21
1001110011
1001010001
I
G3:0
=
Skip if G is Zero
(all 4 bits)
0
1
2
3
33
01
11
03
13
1001110011
1000010001
1000110001
1000010011
1000110011
0
1
2
3
01
11
03
13
1000010001
1000110001
1000010011
1000110011
TEST INSTRUCTIONS
SKGBZ
SKMBZ
=
0
I
1st byte
I
I
I
} 2nd byte
I
I
Skip if G Bit is Zero
Go
G1
G2
G3
=
=
=
=
0
0
0
0
RAM(B)o
RAM(B)1
RAM(B)2
RAM(B)3
I
I
I
I
=
=
=
=
0
0
0
0
Skip if RAM Bit is Zero
INPUT/OUTPUT INSTRUCTIONS
ING
33
2A
1001110011 I
1001011010 I
G-.A
None
Input G Ports to A
INL
33
2E
1001110011 I
10010111101
L7:4 - . RAM (B)
L3:0 - . A
None
Input L Ports to RAM, A
OBO
33
3E
1001110011 I
10011111101
Bd - . 0
None
Output Bd to 0 Outputs
OMG
33
3A
1001110011 I
10011110101
RAM (B) - . G
None
Output RAM to G Ports
XAS
4F
1010011111 1
A
None
Exchange A with SIO
(Note 2)
~
SIO,C - . SKL
Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Sr and Sd are explicitly defined). Sits are numbered 0 to N where
o signifies the least significant bit (low-order, right-most bit). For example, A3 indicates the most significant (left-most) bit of the 4-bit A register.
Note 2: For additional information on the operation of the XAS, JID, and LQID instructions, see below.
Note 3: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction,
otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Note 4: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of Pl. A JSRP may not be used when in pages 2 or 3. JSRP
may not jump to the last word in page 2.
Note 5: The machine code for the lower 4 bits of the LSI instruction equals the binary value of the "d" data minus 1, e.g., to load the lower four bits of S (Sd) with
the value 9 (10012), the lower 4 bits of the LSI instruction equal 8 (10002). To load 0, the lower 4 bits of the LSI instruction should equal 15 (11112).
Note 6: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a "1" or "0" in each bit of EN corresponds
with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
1-110
.-----------------------------------------------------------------------, 0
Option List
The COP414L mask-programmable options are assigned
numbers which correspond with the COP414L pins.
Option 19: L6 Driver
same as Option 1
The following is a list of COP414L options. The options are
programmed at the same time as the ROM pattern to provide the user with the hardware flexibility to interface to various I/O components using little or no external circuitry.
Option 1: 4 Driver
= 0: Standard output
= 1: Open-drain output
Option 20: L6 Driver
same as Option 1
Option 21: L Input Levels
= 0: Standard TIL input levels ("0" = O.BV, "1"
2.0V)
= 1: Higher voltage input levels ("0" = 1.2V, "1"
3.6V)
Option 2: Vee Pin
= 0: Standard Vee
= 1: Optional higher voltage Vee
Option 22: G Input Levels
same as Option 21
~
Option 23: 51 Input Levels
same as Option 21
Option 3: L3 Driver
same as Option 1
TEST MODE (NON-STANDARD OPERATION)
Option 4: L2 Driver
same as Option 1
The SO output has been configured to provide for standard
test procedures for the custom-programmed COP414L.
With SO forced to logic "1", two test modes are provided,
depending upon the value of 51:
Option 5: L1 Driver
same as Option 1
Option 6: L6 Driver
same as Option 1
Option 7: 51 Input
= 0: load device to Vee
= 1: Hi-Z Output
Option 8: SO Driver
= 0: Standard output
= 1: Open-drain output
= 2: Push-pull output
a. RAM and Internal Logic Test Mode (51 = 1)
b. ROM Test Mode (51 = 0)
These special test modes should not be employed by the
user; they are intended for manufacturing tests only.
COP414L Option List
Please fill out the Option List and send it with the EPROM.
Option Data
Option 9: SK Driver
same as Option 8
Option 10:
= 0: Ground Pin-no options available
OPTION
Option 11: Go I/O Port
= 0: Standard output
= 1: Open-drain output
OPTION
1 VALUE
= _ _ _ IS: L4 DRIVER
= _ _ _ IS: Vee PIN
OPTION 2 VALUE
OPTION 3 VALUE = _ _ _ IS: L3 DRIVER
OPTION 4 VALUE = _ _ _ IS: L2 DRIVER
Option 12: G1 I/O Port
same as Option 11
Option 13: G2 I/O Port
same as Option 11
5 VALUE = _ _ _ IS: L1 DRIVER
OPTION
6 VALUE = _ _ _ IS: L6 DRIVER
OPTION
7 VALUE = _ _ _ IS: 51 INPUT
OPTION
8 VALUE = _ _ _ IS: SO DRIVER
OPTION
9 VALUE = _ _ _ IS: SK DRIVER
OPTION 10 VALUE = _ _
0_15: GROUND PIN
OPTION 11 VALUE = _ _ _ IS: Go I/O PORT
Option 14: G3 I/O Port
same as Option 11
OPTION 12 VALUE
Option 15: CKO Output
= 0: Clock output to ceramic resonator/crystal
= 1: No connection
= _ _ _ IS: Gl
I/O PORT
OPTION 13 VALUE = _ _ _ IS: G21/O PORT
OPTION 14 VALUE = _ _ _ IS: G31/O PORT
OPTION 15 VALUE
Option 16: CKI Input
= 0: Ocillator input divided by 8 (500 kHz max)
= 1: Single pin RC controlled oscillator divided by 4
= 2: External Schmitt trigger level clock divided by 4
Option 17: RESET Input
= 0: Load device to Vee
= 1: Hi-Z Input
OPTION 16 VALUE
OPTION 17 VALUE
OPTION 18 VALUE
OPTION 19 VALUE
OPTION 20 VALUE
=
=
=
=
_ _ _ IS: CKO OUTPUT
_ _ _ IS: CKIINPUT
_ _ _ IS: RESET INPUT
_ _ _ IS: L7 DRIVER
=
___
IS: L6 DRIVER
L6 DRIVER
= _ _ _ IS:
OPTION 21 VALUE = - - - IS: L INPUT LEVELS
OPTION 22 VALUE = _ _ _ IS: G INPUT LEVELS
Option 18: L7 Driver
same as Option 1
OPTION 23 VALUE = _ _ _ IS: 51 INPUT LEVELS
1-111
o
-a
~
.....
r.......
o
o-a
w
.....
~
r-
N
N
C"')
o ~National
a..
U
.......
,...
D Semiconductor
N
C"')
a..
o COP420/COP421/COP422 and COP320/COP321/COP322
....... Single-Chip N-Channel Microcontrollers
U
Q
N
C"')
a.. General Description
o The
COP420, COP421, COP422,
U
.......
N
N
"'II:t
a..
o
U
.......
,...
N
"'II:t
a..
oU
.......
Q
N
"'II:t
a..
oU
Features
COP320, COP321 and
COP322 Single-Chip N-Channel Microcontrollers are members of the COPSTM family, fabricated using N-channel, silicon gate MOS technology. They are complete microcomputers containing all system timing, internal logic, ROM,
RAM and I/O necessary to implement dedicated control
functions in a variety of applications. Features include single
supply operation, a variety of output configuration options,
with an instruction set, internal architecture and I/O scheme
designed to facilitate keyboard input, display output and
BCD data manipulation. The COP421 is identical to the
COP420, except with 19 I/O lines instead of 23; the
COP422 has 15 I/O lines. They are an appropriate choice
for use in numerous human interface control environments.
Standard test procedures and reliable high-density fabrication techniques provide the medium to large volume customers with a customized Controller Oriented Processor at
a low end-product cost.
•
•
•
•
•
•
•
•
•
•
Low cost
Powerful instruction set
1k x 8 ROM, 64 x 4 RAM
23 I/O lines (COP420, COP320)
True vectored interrupt, plus restart
Three-level subroutine stack
4.0 ,.,.s instruction time
Single supply operation
Internal time-base counter for real-time processing
Internal binary counter register with MICROWIRETM
compatible serial I/O capacity
General purpose and TRI-STATE® outputs
TTL/CMOS compatible in and out
LED direct drive outputs
MICROBUSTM compatible
Software/hardware compatible with other members of
COP400 family
Extended temperature range device COP320/COP321/
COP322 (-40°C to +85°C)
•
•
•
•
•
The COP320 is the extended temperature range version of
the COP420 (likewise the COP321 and COP322 are the extended temperature range versions of the COP421/
COP422). The COP320/321/322 are exact functjonal
equivalents of the COP420/421/422.
•
Block Diagram
OJ
02
0,·
DO·
5
•
1
I
12
13
14
·Not available on COP322/COP422.
15
TL/DD/6921-1
FIGURE 1
1-112
o
o"'0
COP420/COP421/COP422 and COP320/COP321/COP322
Absolute Maximum Ratings
0l:Io
N
C
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Package Power Dissipation
24 and 28 pin
750 mW at 25·C
400 mW at 70·C
250 mW at 85·C
Voltage at Any Pin
Package Power Dissipation
20 pin
650 mW at 25·C
300 mW at 70·C
200 mW at 85·C
Operating Temperature Range
COP420/COP421/COP422
COP320/COP321/COP322
Storage Temperature Range
-0.3Vto +7V
O·Cto 70·C
- 40·C to + 85·C
Lead Temperature (soldering, 10 sec.)
Absolute maximum ratings indicate limits beyond which
damage to the device may occur. DC and AC electrical
specifications are not ensured when operating the device at
absolute maximum ratings.
- 65·C to + 150·C
Total Sink Current
75mA
Total Source Current
95mA
300·C
........
o
o"'0
0l:Io
N
.....
........
o
o"'0
0l:Io
N
N
........
o
o"'0
(,.)
N
C
COP420/COP421/COP422
........
DC Electrical Characteristics o·c : :;: T A :::;:
Conditions
Parameter
o
+ 70·C, 4.5V :::;: Vee:::;: 6.3V unless otherwise noted
Operation Voltage
Min
Max
Units
4.5
6.3
V
V
Power Supply Ripple
Peak to Peak (Note 3)
0.4
Supply Current
Outputs Open
38
mA
Supply Current
Outputs Open,
Vee = 5V, TA = 25·C
30
mA
3.0
2.0
-0.3
0.4
V
V
2.0
-0.3
0.8
V
V
0.7 Vee
-0.3
0.6
V
V
2.0
3.0
V
3.0
2.0
-0.3
0.8
V
V
V
3.6
-0.3
1.2
V
V
o"'0
(,.)
N
........
.....
o
o"'0
(,.)
N
N
Input Voltage Levels
CKllnput Levels
Crystal Input
Logic High
Logic High
Logic Low
TTL Input
Logic High
Logic Low
Vee
Vee
Vee
=
=
=
Max.
5V ±5%
5V ±5%
Schmitt Trigger Inputs
RESET, CKI (-:- 4)
Logic High
Logic Low
SO Input Level (Test Mode)
(Note 2)
All Other Inputs
Logic High
Logic High
Logic Low
Vee
Vee
=
=
Max.
5V ±5%
Input Levels High Trip Option
Logic High
Logic Low
Input Load Source Current
Vee
=
5V, VIN
=
OV
CKO
All Others
-4
-800
-100
-800
/J- A
/J- A
7
pF
-1
+1
/J- A
2.4
-0.3
0.4
V
V
0.2
V
V
Input Capacitance
Hi-Z Input Leakage
Output Voltage Levels
Standard Outputs
TTL Operation
Logic High
Logic Low
Vee = 5V ±10%
IOH = -100/J-A
IOl = 1.6 mA
CMOS Operation (Note 1)
Logic High
Logic Low
IOH
IOl
=
=
-10/J-A
+10/J-A
Note 1: TRI·STATE and LED configurations are excluded.
Note 2: SO output "0" level must be less than O.BV for normal operation.
1-113
Vee -1
III
N
N
C")
a..
o
......
o
-a..
COP420/COP421/COP422
DC Electrical Characteristics o·c :5: TA :5:
N
Parameter
o
Output Current levels
lED Direct Drive Output
logic High
CKI Sink Current (RIC Option)
CKO (RAM Supply Current)
C")
o
......
o
N
C")
a..
o
......
N
o
N
TRI·STATE or Open Drain
leakage Current
a..
o
......
Output Current levels
Output Sink Current (Iou
Output Source Current (IOH)
~
o
--a..
N
~
oo
Standard Configuration
All Outputs
......
o
N
~
a..
o
o
Push· Pull Configuration
SO, SK Outputs
TRI·STATE Configuration
Lo-l7 Outputs
lED Configuration
Lo-l7 Outputs
+ 70·C, 4.5V :5: Vee :5: 6.3V unless otherwise noted (Continued)
Conditions
Vee = 6V
VOH = 2.0V
VIN = 3.5V
VA = 3.3V
Min
Max
Units
2.5
2
14
3
mA
rnA
rnA
+2.5
p.A
Vee
=
5V
Vee
=
4.5V, VOL
=
0.4V
+1.6
Vee
Vee
=
=
6.3V, VOH
4.5V, VOH
=
=
3.0V
2.0V
-200
-100
Vee
Vee
=
=
6.3V, VOH
4.5V, VOH
=
=
3.0V
2.0V
-1.0
-0.4
rnA
rnA
Vee
Vee
=
=
6.3V, VOH
4.5V, VOH
=
=
3.2V
1.5V
-0.8
-0.9
rnA
rnA
Vee
Vee
=
=
6.3V, VOH
4.5V, VOH
=
=
3.0V
2.0V
-1.0
-0.5
rnA
rnA
-2.5
Allowable Sink Current
Per Pin (l, 0, G)
Per Pin (All Others)
Per Port (l)
PerPort(D,G)
Allowable Source Current
Per Pin (l)
Per Pin (All Others)
1-114
rnA
-900
-500
p.A
p.A
10
2
16
10
rnA
rnA
rnA
rnA
-15
-1.5
rnA
rnA
o
o-a
COP320/COP321/COP322
oIloo
I\)
DC Electrical Characteristics
Input Voltage Levels
CKllnput Levels
Crystal Input
Logic High
Logic Low
TIL Input
Logic High
Logic Low
Schrnitt Trigger Inputs
RESET, CKI ( + 4)
Logic High
Logic Low
SO Input Level (Test Mode)
All Other Inputs
Logic High
Logic High
Logic Low
Input Levels High Trip Option
Logic High
Logic Low
Input Load Source Current
CKO
All Others
Input Capacitance
Conditions
Output Current Levels
LED Direct Drive Output
Logic High
CKI Sink Current (RIC Option)
CKO (RAM Supply Current)
Min
4.5
Peak to Peak (Note 3)
TA = -40·C, Outputs Open
Max
Units
5.5
V
0.4
40
V
rnA
o
o
-a
oIloo
....
......
I\)
o
o
-a
oIloo
I\)
2.2
-0.3
0.3
V
V
0.6
V
V
Vee = 5V ±5%
2.2
-0.3
0.4
3.0
V
V
V
3.0
2.2
-0.3
0.6
V
V
V
3.6
-0.3
1.2
V
V
-4
-100
-800
-BOO
7
p,A
p,A
pF
-2
+2
p,A
2.4
-0.3
0.4
V
V
Vee -1
-0.3
0.2
V
V
0.7 Vee
-0.3
2.0
(Note 2)
Vee = Max.
Vee = 5V ±5%
I\)
......
o
o-a
w
I\)
Q
......
o
o-a
w
....
......
o
I\)
o-a
w
I\)
I\)
Vee = 5V, VIN = OV
Hi-Z Input Leakage
Output Voltage Levels
Standard Outputs
TIL Operation
Logic High
Logic Low
CMOS Operation (Note 1)
Logic High
Logic Low
......
-40·C:S: TA:S: +B5·C,4.5V:S: Vee:S: 5.5Vunlessotherwisenoted
Parameter
Operation Voltage
Power Supply Ripple
Supply Current
Q
Vee = 5V ±10%
IOH = -75 p,A
IOL = 1.6 rnA
IOH = -10 p,A
IOL = +10 p,A
Vee = 5V (Note 4)
VOH = 2.0V
VIN = 3.5V
VA = 3.3V
TRI-STATE or Open Drain
Leakage Current
1.0
2
-5
Allowable Sink Current
Per Pin (L, 0, G)
Per Pin (All Others)
Per Port (L)
PerPort(D,G)
12
4
rnA
rnA
rnA
+5
p,A
10
16
10
rnA
rnA
rnA
rnA
-15
-1.5
rnA
rnA
2
Allowable Source Current
Per Pin (L)
Per Pin (All Others)
Note 1: TAl-STATE and LED configurations are excluded.
Note 2: SO output "0" level must be less than 0.6V for normal operation.
1-115
II
N
N
C")
D.
o
o
"N,...
AC Electrical Characteristics
COP420/COP421/COP422 o·c : ; TA ::;; 70·C, 4.5V ::;; VCC ::;; 6.3V unless otherwise noted
COP320/COP321/COP322
Instruction Cycle Time
"o
Operating CKI Frequency
N
C")
D.
o
o
"NN
"II:t'
D.
o
o
",...
N
"II:t'
CKI Duty Cycle (Note 1)
Rise Time
Fall Time
CKI Using RC (Figure Be)
Frequency
Instruction Cycle Time (Note 5)
D.
CKO as SYNC Input (Figure Bd)
tSYNC
o
Inputs:
o
"oN
"II:t'
D.
o
o
+ 85·C, 4.5V ::;; Vcc ::;; 5.5V unless otherwise noted
Parameter
C")
D.
o
o
- 40·C ::;; TA ::;;
Conditions
+16 mode
+8 mode
Freq.
Freq.
+4 mode
R = 15kn ±5%,C
=
100pF
Figure3a
tSETUP
tHOLO
Test Conditions:
RL = 5 kn, CL = 50 pF, VOUT
SOandSK
tpd1
tpdO
CKO
tpd1
tpdO
All Other Outputs
tpd1
tpdo
MICROBUSTM Timing
Read Operation (Figure 4)
Chip Select Stable before RD-tCSR
Chip Select Hold Time for RD-tRCS
RD Pulse Width-tRR
Data Delay from RD-tRO
RD to Data Floating-tOF
CL
=
Max
4
10
J.Ls
1.6
0.8
4.0
2.0
MHz
MHz
40
60
60
40
%
ns
ns
0.5
4
1.0
8
MHz
J.Ls
= 4 MHz
= 4 MHz
SI
tSETUP
tHOLO
All Other Inputs
Output Propagation Delay
Min
100 pF, VCC
= 5V
±5%
=
Units
50
ns
0.3
250
J.Ls
ns
1.7
300
,..,s
ns
300
ns
1.5V
.
1.0
1.0
,..,s
,..,s
0.25
0.25
,..,s
,..,s
1.4
1.4
,..,s
,..,s
375
250
ns
ns
ns
ns
ns
65
20
400
Write Operation (Figure 5)
65
Chip Select Stable before WR-tcsw
20
Chip Select Hold Time for WR-twcs
400
WR Pulse Width-tww
320
Data Set-Up Time for WR-tow
Data Hold Time for WR-two
100
700
INTR Transition Time from WR-twi
Note 1: Duty cycle = tW1/(tW1 + two).
Note 2: See Figure 9 for additional I/O characteristics.
Note 3: Voltage change must be less than O.SV in a 1 ms period.
Note 4: LED direct drive must not be used. Exercise great care not to exceed maximum device power dissipation limits when sourcing similar loads
temperature.
Note 5: Variation due to the device included.
1-116
ns
ns
ns
ns
ns
ns
at high
o
o
Connection Diagrams
"'C
0I:loo
N
COP422, COP322
DIP
o
......
COP421, COP321
DIP and SO Wide
eKO
20
GNO
CKI
19
02
RESET
18
03
L7
17
G3
L6
16
02
L5
15
SK
L4
14
SO
Vee
13
o
DO
01
DZ
03
G3
G2
Gl
GO
SK
SO
SI
LO
CKO
SI
L7
L6
L5
L4
Vee
L3
L3
9
12
LO
L2
L2
10
11
Ll
L1
o"'C
0I:loo
N
....
......
o
o"'C
0I:loo
N
N
......
o
o
"'C
w
N
o
......
TLlDD/6921-3
TL/DD/6921-4
Top View
Top View
W
....
N
Order Number COP321-XXX/N
or COP421-XXX/N
See NS Molded Package N24A
Order Number COP322-XXX/N
or COP422-XXX/N
See NS Molded Package N20A
......
o
o
"'C
Order Number COP321-XXX/D
or COP421-XXX/D
See NS Hermetic Package D24C
Order Number COP322-XXX/D
or COP422-XXX/D
See NS Hermetic Package D20A
o
o"'C
W
N
N
Order Number COP321-XXX/WM
or COP421-XXX/WM
See NS Surface Mount Package M24B
COP420, COP320
Dual-ln-L1ne Package
GND
21
PLCC
DO
Dl
D2
D3
G3
G2
Gl
GO
IN3
13
14
6
L6
G2
7
L5
Gl
8
L4
IN3
10
IN2
INO
11
Vee
INI
GO
17
LZ
L1
L7
03
G3
16
15
TL/DD/6921-2
Top View
TL/DD/6921-31
Order Number COP320-XXX/V
or COP420-XXX/V
See NS PLCC Package V28A
Order Number COP320-XXX/N
or COP420-XXX/N
See NS Molded Package N28B
Order Number COP320-XXX/D
or COP320-XXX/D
See NS Hermetic Package D28C
FIGURE 2
1-117
•
~
~
C")
D..
o
o
......
.....
~
C")
D..
oo
......
o
~
C")
r----------------------------------------------------------------------------------------,
Pin Descriptions
Pin
Description
8 bidirectional 1/0 ports with TRI-STATE
G3- GO 4 bidirectional 1/0 ports
D3- 0 0 4 general purpose outputs
IN3-INo 4 general purpose inputs (COP420/320 only)
SI
Serial input (or counter input)
Serial output (or general purpose output
Pin
L7- LO
SK
CKI
CKO
so
RESET
Vee
D..
o
o
......
~
~
GNO
Description
Logic-controlled clock (or general purpose output)
System oscillator input
System oscillator output (or general purpose input
or RAM power supply)
System reset input
Power supply
Ground
Timing Diagrams
"'1:1'
D..
o
o......
.....
~
"'1:1'
D..
oo
......
o
~
"'1:1'
D..
o
CKI
S~~~M
1-~~----..&10""""111
I-- 'SETUP - l I-IHOLD
IN3-INO.
G3-GDck~&LRi
?!IUlffIIllflmlllm//uml//!!IUu/HIImIfUI/II/J/$
X'lUU/UIUllfuu/IU!l/I/UM
~IPD1-1
INPUTS
Gr;~~~~~~~~
InIl'l'lVlJl"''I/'''''rh~W,,'''rJ6~v~OH-----------......~':''''''.....- - - - - - -
OUTPUTS
o
TL/DD/6921-5
FIGURE 3. Input/Output Timing Diagrams (Crystal Divide by 16 Mode)
--II-tWO
CKI
-I
CKO
(INPUT)
I- tW1
j
CKIJLFLr
I
'PD~'PDD
1-- tSYNCO
1
\ \._ _ _ _......._ _ _ _ _ __
TL/DD/6921-7
TL/DD/6921-6
FIGURE 3B. CKO Output Timing
FIGURE 3A. Synchronization Timing
,
(lNd
~.
RD
-- tCSR
IL1-LO)
D1- DO
1
tRR
--f.-
• -tRCS-:::j
,
tRD-1
I--tDF
.~
----------'1("'-____________
TL/DD/6921-8
FIGURE 4. MICROBUS Read Operation Timing
1-118
o
o-a
Timing Diagrams (Continued)
~
N
• -twcs-I
IVIW
.I-ICSW-- •
Q
......
o
o-a
1
\
~
I-IOW-
.
(Go)
-
'(
twl
N
-a.
'(
two
..
......
o
o
.1-
-a
X
~
N
N
......
o
INTR
TL/DD/6921-9
FIGURE 5. MICROBUS Write Operation Timing
Functional Description COP420/COP421/COP422,
COP320/COP321/COP322
For ease of reading this description, only COP420 and/or
COP421 are referenced; however, all such references apply
equally to the COP422, COP322, COP320 and/or COP321,
respectively.
ROM instruction words are fetched, decoded and executed
by the Instruction Decode, Control and Skip Logic circuitry.
DATA MEMORY
Data memory consists of 256-bit RAM, organized as 4 data
registers of 16 4-bit digits. RAM addressing is implemented
by a 6-bit B register whose upper 2 bits (Br) select 1 of 4
data registers and lower 4 bits (8d) select 1 of 16 4-bit digits
in the selected data register. While the 4-bit contents of the
selected RAM digit (M) is usually loaded into or from, or
exchanged with, the A register (accumulator), it may also be
loaded into or from the Q latches or loaded from the L ports.
RAM addressing may also be performed directly by the LDD
and XAD instructions based upon the 6-bit contents of the
operand field of these instructions. The Bd register also
serves as a source register for 4-bit data sent directly to the
D outputs.
A block diagram of the COP420 is given in Figure 1. Data
paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. Positive logic is
used. When a bit is set, it is a logic "1" (greater than 2V).
When a bit is reset, it is a logic "0" (less than O.BV).
PROGRAM MEMORY
Program Memory consists of a 1,024 byte ROM. As can be
seen by an examination of the COP420/421 instruction set,
these words may be program instructions, program data or
ROM addressing data. Because of the special characteristics associated with the JP, JSRP, JID and LQID instructions, ROM must often be thought of as being organized into
16 pages of 64 words each.
INTERNAL LOGIC
The 4-bit A register (accumulator) is the source and destination register for most 110, arithmetic, logic and data memory access operations. It can also be used to load the Br
and Bd portions of the B register, to load the input 4 bits of
the 8-bit Q latch data, to input 4 bits of the B-bit L 110 port
data and to perform data exchanges with the SID register.
ROM addressing is accomplished by a 10-bit PC register. Its
binary value selects one of the 1,024 8-bit words contained
in ROM. A new address is loaded into the PC register during
each instruction cycle. Unless the instruction is a transfer of
control instruction, the PC register is loaded with the next
sequential 10-bit binary count value. Three levels of subroutine nesting are implemented by the 10-bit subroutine save
registers, SA. SB and SC, providing a last-in, first-out (LIFO)
hardware subroutine stack.
1-119
o-a
w
N
Q
......
o
o-a
w
N
-a.
......
o
o-a
w
N
N
N
N
C")
D-
o
o
.......
,...
N
C")
D-
O
o
.......
o
N
C")
D-
O
o
.......
N
N
'OI:t'
D-
O
o
.......
,...
N
'OI:t'
D-
O
o.......
o
N
'OI:t'
D-
O
o
r---------------------------------------------------------------------------------------~
Functional Description COP420/COP421/COP422,
COP320/COP321/COP322 (Continued)
A 4-blt adder performs the arithmetic and logic functions of
the COP420/421, storing its results in A. It also outputs a
carry bit to the 1-bit C register, most often employed to
indicate arithmetic overflow. The C register, in conjunction
with the XAS instruction and the EN register, also serves to
control the SK output. C can be outputted directly to SK or
can enable SK to be a sync clock each instruction cycle
time. (See XAS instruction and EN register description, below.)
1. The least significant bit of the enable register, ENo selects the SIO register as either a 4-bit shift register or a 4bit binary counter. With ENo set, SIO is an asynchronous
binary counter, decrementing its value by one upon each
low-going pulse ("1" to "0" occurring on the SI input.
Each pulse must be at least two instruction cycles wide.
SK outputs the value of SKL. The SO output is equal to
the value of EN3. With ENo reset, SIO is a serial shift
register shifting let each instruction cycle time. The data
present at 01 goes into the least significant bit of SIO. SO
can be enabled to output the most significant bit of SIO
each cycle time. (See 4 below.) The SK output becomes
a logic-controlled clock.
Four general-purpose Inputs, IN3-INQ, are provided; IN1,
IN2 and IN3 may be selected, by a mask-programmable option, as Read Strobe, Chip Select and Write Strobe inputs,
respectively, for use in MICROBUS applications.
2. With the EN1 set the IN1 input is enabled as an interrupt
input. Immediately following an interrupt, EN1 is reset to
disable further interrupts.
3. With EN2 set, the L drivers are enabled to output the data
in Q to the L I/O ports. Resetting EN2 disables the L
drivers, placing the L 1/0 ports in a high impedance input
state.
The 0 register provides 4 general·purpose outputs and is
used as the destination register for the 4-bit contents of Bd.
The G register contents are outputs to 4 general-purpose
bidirectional 1/0 ports. Go may be mask-programmed as an
output for MICROBUS applications .
The Q register is an internal, latched, 8-bit register, used to
hold data loaded to or from M and A, as well as 8-bit data
from ROM. Its contents are output to the L 1/0 ports when
the L drivers are enabled under program control. (See LEI
instruction.) With the MICROBUS option selected, Q can
also be loaded with the 8-bit contents of the L 1/0 ports
upon the occurrence of a write strobe from the host CPU.
The 8 L drivers, when enabled, output the contents of
latched Q data to the L 1/0 ports. Also, the contents of L
may be read directly into A and M. As explained above, the
MICROBUS option allows L 1/0 port data to be latched into
the Q register. L 1/0 ports can be directly connected to the
segments of a multiplexed LED display (using the LED Direct Drive· output configuration option) with Q data being
outputted to the Sa-Sg and decimal point segments of the
display.
4. EN3, in conjunction with ENo, affects the SO output. With
ENo set (binary counter option selected) SO will output
the value loaded into EN3. With ENo reset (serial shift
register option selected), setting EN enables SO as the
output of the SIO shift register outputting serial shifted
data each instruction time. Resetting EN3 with the serial
shift register option selected disables SO as the shift register output data continues to be shifted through SIO and
can be exchanged with A via an XAS instruction but SO
remains reset to "0". The table below provides summary
of the modes associated with EN3 and EN1.
OSCILLATOR
There are three basic clock oscillator configurations available as shown by Figure 8.
a. Crystal Controlled Oscillator. CKI and CKO are connected to an external crystal. The instruction cycle time
equals the crystal frequency divided by 16 (optional by
8).
The 510 register functions as a 4-bit serial-in/serial-out
shift register or as a binary counter depending on the contents of the EN register. (See EN register description, below.) Its contents can be exchanged with A, allowing it to
input or output a continuous serial data stream. SIO may
also be used to provide additional paralJelllO by connecting
SO to external serial-in/paralJel-out shift registers. For example of additional parallel output capacity see Application
#2.
b. External Oscillator. CKI is an external clock input signal. The external frequency is divided by 16 (optional by
8) to give the instruction cycle time. CKO is now available to be used as the RAM power supply (VR) of as a
general purpose input.
The XAS instruction copies C into the SKL latch. In the
counter mode, SK is the output of SKL; in the shift register
mode, SK outputs SKL ANDed with the clock.
c. RC Controlled Oscillator. CKI is configured as a single
pin RC controlled Schmitt trigger oscillator. The instruction cycle equals the oscillation frequency divided by 4.
CKO is available for non-timing functions.
The EN register is an internal 4-bit register loaded under
program control by the LEI instruction. The state of each bit
of this register selects or deselects the particular feature
associated with each bit of the EN register (EN3-ENo).
Enable Register Modes-Bits EN3 and ENo
EN3
ENo
510
51
SO
SK
0
0
Shift Register
Input to Shift Register
0
If SKL = 1, SK = CLOCK
If SKL = 0, SK = 0
1
0
Shift Register
Input to Shift Register
Serial Out
If SKL = 1, SK = CLOCK
If SKL = 0, SK = 0
0
1
Binary Counter
Input to Binary Counter
0
If SKL = 1, SK = 1
If SKL = 0, SK =
1
1
Binary Counter
Input to Binary Counter
1
If SKL = 1, SK = 1
If SKL = 0, SK = 0
1-120
°
o
o
Functional Description COP420/COP421/COP422,
COP320/COP321/COP322 (Continued)
uw
t;:t
J1..["
Rl
EXTERNAL
CLOCK
"tJ
.I:Jo
I\)
o
......
o
o"tJ
.I:Jo
CKI
I\)
eKO
I ... . Vcc
t
-&.
......
o
o"tJ
~ IVR OR GENERAL
IVR OR GENERAL
PURPOSE INPUT
PIN)
PURPOSE INPUT
PIN)
I-=-
XTAl
.I:Jo
I\)
I\)
......
D
~C2
o
o
"tJ
(,)
I\)
*Cl
TLlDD/6921-10
Crystal Oscillator
External Oscillator
RC Controlled Oscillator
Crystal Oscillator
RC Controlled Oscillator
Crystal
Value
R1(O)
R2(n)
C1(pF)
C2(pF)
4MHz
3.58 MHz
2.09 MHz
4.7k
3.3k
8.2k
1M
1M
1M
22
22
47
22
27
33
Component Values
R(kO)
C(pF)
Instruction
Cycle Time
(,...s)
12
6.8
8.2
22
100
220
300
100
5 ±20%
5.3 ±23%
8 ±29%
8.6 ± 16%
o
......
o
o"tJ
(,)
I\)
-&.
......
o
o"tJ
(,)
I\)
I\)
Note: 50 kfl ~ R ~ 5 kfl
360 pF ~ C ~ 50 pF
FIGURE 8. COP420/4211COP320/321 Oscillator
+ 1) onto the stack, pushing in turn the contents of the
other subroutine-save registers to the next lower level
(PC + 1 ~ SA ~ SB ~ SC). Any previous contents of SC are lost. The program counter is set to hex
address OFF (the last word of page 3) and EN1 is reset.
b. An interrupt will be acknowledged only after the following
conditions are met:
CKO PIN OPTIONS
In a crystal controlled oscillator system, CKO is used as an
output to the crystal network. As an option CKO can be a
general purpose input, read into bit 2 of A (accumulator)
upon execution of an INIL instruction. As another option,
CKO can be a RAM power supply pin (VA)' allowing its con·
nection to a standby/backup power supply to maintain the
integrity of RAM data with minimum power drain when the
main supply is inoperative or shut down to conserve power.
Using either option is appropriate in applications where the
COP420/421 system timing configuration does not require
use of the CKO pin.
1. EN1 has been set.
2. A low-going pulse ("1" to "0") at least two instruction
cycles wide occurs on the IN1 input.
3. A currently executing instruction has been completed.
4. All successive transfer of control instructions and successive LBls have been completed (e.g., if the main
program is executing a JP instruction which transfers
program control to another JP instruction, the interrupt
will not be acknowledged until the second JP instruction has been executed.
RAM KEEP-ALIVE OPTION (NOT AVAILABLE ON
COP422)
Selecting CKO as the RAM power supply (VA) allows the
user to shut off the chip power supply (Vee> and maintain
data in the RAM. To insure that RAM data integrity is maintained, the following conditions must be met:
c. Upon acknowledgement of an interrupt, the skip logic
status is saved and later restored upon popping of the
stack. For example, if an interrupt occurs during the execution of ASC (Add with Carry, Skip on Carry) instruction
which results in carry, the skip logic status is saved and
program control is transferred to the interrupt servicing
routine at hex address OFF. At the end of the interrupt
routine, a RET instruction is executed to "pop" the stack
and return program control to the instruction following
the original ASC. At this time, the skip logic is enabled
and skips this instruction because of the previous ASC
carry. Subroutines and LQID instructions should not be
nested within the interrupt service routine, since their
1. RESET must go low before Vee goes below spec during
power off; Vee must be within spec before RESET goes
high on power up.
2. VA must be within the operating range of the chip, and
equal to Vee ± 1V during normal operation.
3. VR must be
~
3.3V with Vee off.
INTERRUPT
The following features are associated with the IN1 interrupt
procedure and protocol and must be considered by the programmer when utilizing interrupts.
a. The interrupt, once acknowledged as explained below,
pushes the next sequential program counter address (PC
1-121
III
N
N
C")
D.
o
o
.......
--
Functional Description COP420/COP421/COP422,
COP320/COP321/COP322 (Continued)
POWER
SUPPLY
N
CLOCK
C")
D.
oo
.......
o
N
C")
D.
MICROPROCESSOR
o
o
.......
~~~~~~
IN
N
N
"1:1'
OUT
D.
o
o
.......
-N
"1:1'
TUDD/6921-12
D.
oo
.......
o
N
"1:1'
D.
o
o
FIGURE 6. MICROBUS Option Interconnect
popping the stack will enable any previously saved main
program skips, interfering with the orderly execution of
the interrupt routine.
d. The first instruction of the interrupt routine at hex address OFF must be a NOP.
e. A LEI instruction can be put immediately before the RET
to re-enable interrupts.
shown below. The RESET pin is configured as a Schmitt
trigger input. If not used it should be connected to Vee.
Initialization will occur whenever a logic "0" is applied to the
RESET input, provided it stays low for at least three instruction cycle times.
Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, D, EN, and G registers are cleared.
The SK output is enabled as a SYNC output, providing a
pulse each instruction cycle time. Data Memory (RAM) is
not cleared upon initialization. The first instruction at address 0 must be a CLRA.
MICROBUSTM INTERFACE
The COP420 has an option which allows it to be used as a
peripheral microprocessor device, inputting and outputting
data from and to a host microprocessor (,..,P). IN1, IN2 and
INa general purpose inputs become MICROBUS compatible read-strobe, chip-select, and write-strobe lines, respectively. IN1 becomes RD-a logic "0" on this input will cause
Q latch data to be enabled to the L ports for input to the ,..,P.
IN2 becomes CS-a logic "0" on this line selects the
COP420 as the ,..,p peripheral device by enabling the operation of the RD and WR lines and allows for the selection of
one of several peripheral components. IN3 becomes WR-a
logic "0" on this line will write bus data from the L ports to
the Q latches for input to the COP420. Go becomes INTR a
"ready" output, reset by a write pulse from the ,..,p on the
WR line, providing the "handshaking" capability necessary
for asynchronous data transfer between the host CPU and
the COP420.
This option has been designed for compatibility with National's MICROBUS-a standard interconnect system for a-bit
parallel data transfer between MOS/LSI CPUs and interfacing devices. (See MICROBUS National Publication.) The
functioning and timing relationships between the COP420
signal lines affected by this option are as specified for the
MICROBUS interface, and are given in the AC electrical
characteristics and shown in the timing diagrams (Figures 4
and 5). Connection of the COP420 to the MICROBUS is
shown in Figure 6.
P + -..........~---...
o
W
E
R
S
U
P
P
L
Y
Vee
"''''-'''RESET eOP420/421
GND
TL/DD/6921-13
FIGURE 7. Power-Up Clear Circuit
I/O OPTIONS
COP420/421 outputs have the following optional configurations, illustrated in Figure 9a:
a. Standard-an enhancement mode device to ground in
conjunction with a depletion-mode device to Vee, compatible with TIL and CMOS input requirements. Available on SO, SK, and all D and G outputs.
b. Open-Draln-an enhancement-mode device to ground
only, allowing external pull-up as required by the user's
application. Available on SO, SK, and all D and G outputs.
c. Push-Pull-An enhancement-mode device to ground in
conjunction with a depletion-mode device paralleled by
an enhancement-mode device to Vee. This configuration
has been provided to allow for fast rise and fall times
when driving capacitive loads. Available on SO and SK
outputs only.
Note: TRI·STATE outputs must be used on L·port.
INITIALIZATION
The Reset Logic, internal to the COP420/421, will initialize
(clear) the device upon power-up if the power supply rise
time is less than 1 ms and greater than 1 ,..,s. If the power
supply rise time is greater than 1 ms, the user must provide
an external. RC network and diode to the RESET pin as
d. Standard L-same as a., but may be disabled. Available
on L outputs only.
e. Open Drain L-same as b., but may be disabled. Available on L outputs only.
1-122
o
o"'CI
Functional Description COP420/COP421/COP422,
COP320/COP321/COP322 (Continued)
~
I\)
of these devices to allow the designer to effectively use
these I/O configurations in designing a COP420/421 system.
The SO, SK outputs can be configured as shown in a., b., or
c. The 0 and G outputs can be configured as shown in a. or
b. Note that when inputting data to the G ports, the G outputs should be set to "1." The L outputs can be configured
as in d., e., f. or g.
An important point to remember if using configuration d. or
f. with the L drivers is that even when the L drivers are
disabled, the depletion load device will source a small
amount of current (see Figure 9b, device 2); however, when
the L lines are used as input, the disabled depletion device
can not be relied on to source sufficient current to pull an
input to logic" 1".
f. LED Direct Drive-an enhancement-mode device to
ground and to Vee, meeting the typical current sourcing
requirements of the segments of an LED display. The
sourcing device is clamped to limit current flow. These
devices may be turned off under program control (See
Functional Description, EN Register), placing the outputs
in a high-impedance state to provide required LED seg·
ment blanking for a multiplexed display.
g. TRI-STATE Push-Pull-an enhancement-mode device
to ground and Vee. These outputs are TRI-STATE outputs, allowing for connection of these outputs to a data
bus shared by other bus drivers.
COP420/COP421 inputs have the following optional configurations:
h. An on-chip depletion load device to Vee.
I. A Hi-Z input which must be driven to a "1" or "0" by
external components.
The above input and output configurations share common
enhancement-mode and depletion-mode devices. Specifically, all configurations use one or more of six devices
(numbered 1-6, respectively). Minimum and maximum cur·
rent (lOUT and VOUT) curves are given in Figure 9b for each
COP421
If the COP420 is bonded as a 24-pin device, it becomes the
COP421, illustrated in Figure 2, COP420/421 Connection
Diagrams. Note that the COP421 does not contain the four
general purpose IN inputs (lN3-INo). Use of this option precludes, of course, use of the IN options, interrupt feature,
and the MICROBUS option which uses IN1-IN3. All other
options are available for the COP421.
o
.......
o
o"'CI
~
I\)
......
.......
o
o"'CI
~
I\)
I\)
.......
o
o"'CI
W
I\)
o
.......
o
o"'CI
W
I\)
......
.......
o
o"'CI
W
I\)
I\)
TLlDD/6921-15
TLlDD/6921-16
TL/DD/6921-14
a. Standard Output
c. Push-Pull Output
b. Open-Oraln Output
D"ABlE~~
•
•
TL/DD/6921-18
TL/DD/6921-17
(& is Depletion Device)
d. Standard L Output
e. Open-Drain L Output
Vee
cmi
#6
IN'~~f
INPUT~~
TL/DD/6921-22
TI,.IDD/6921-21
TL/DD/6921-20
g. TRI-STATE Push-Pull (L Output)
TL/DD/6921-19
f. LED (L Output)
h. Input with Load
FIGURE 9a. Input/Output Configurations
1·123
I. HI-Z Input
N
N
Cf)
Ill.
oo
Typical Performance Characteristics
......
,...
L Output Depletion Load OFF
Source Current
Output Sink Current
N
-0.4
Cf)
Ill.
oo
-0.3
......
o
C
N
C
Ill.
...
Cf)
oo
1\
\
.!
.!
~-0.2
::>
o
......
I\.MAX
-0.1
N
N
MIN
~
~
Ill.
o
o
......
,...
VOUT (VOL TSI
\
'\
DEVICE 1
DEVICE 2
VOUT (VOL lSI
N
~
Ill.
oo
Standard Output Source Current
......
- 2.0 r--r-,---,--.---r-,--,
N
-1.75 1--+-+--+-1--+-+--1
o
~
Push-Pull Source Current
Ill.
o
o
c- I •25
i;E -1.0 ~+!\d"":"';-'1"---;--'--r-'--t--t
!E -0.75 ~~--I~+,L--!--+--t--t
- 0.5
l:---P.....,..r--fi-~++-+-+--1
VOUl (VOL TSI
DEVICE 2
VOUT (VOL lSI
LED Output Source Current
LED Output Direct LED Drive
-20r-~-.-~-~~--r-'
-18
-18~~~+--+--+--4-+-1
-16
-16~~~~~-~--t--r~
-14
"-:-+--~-+--+---I--+---t
C -12
I-~-f-::::,¥f--+--+--+---t
i; -10
1-~-\-+-4r-+--+--+--1
E
MAX
-14
-12
...
~
VOur- 2.GV
-8
I-~-~~-~--t--r--t
-4
-2~~~~~~~-4-+-1
-2
,/
",
"
o
.......
4
VOUT (VOL TSI
,/
/~
-6
-61--+-~~~~--I~~~
~
4.5
-
- ~t~~
5.5
Vcc (VOLTSI
DEVICE 4 AND Z
TRI-STATE Output Source Current
/'
..,V
1-10
E - 8 1-~-\+--+-\-*~--+--1
-4
DEVICE 3 AND Z
6.5
. DEVICE 4 AND Z
Input Load Source Current
-15
C
.! -10
1-0.5
!;
...
::>
J---31cl---t~Wh·,
E
E
-5
VOUT (VOLTSI
DEVICE 5
TL/DD/6921-23
FIGURE 9b. COP420/COP421 Input/Output Characteristics
1-124
o
o"0
Typical Performance Characteristics (Continued)
~
N
L Output Depletion Load OFF
Source Current
o
........
o
o"0
~
1-
10
!...
........
~ -0.3
o"0
§
-0.2
-0.1
2
3
~+
~
N
N
........
o
~_I\
2
4
VoUT (VOLTS)
3
4
o"0
5
W
N
DEVICE 2
VOUT (VOLTS)
DEVICE 1
Standard Output Source Current
-1.75
N
.....
o
04
.
o
........
o
o"0
Push· Pull Source Current
r----r-,--.---r-,--.--..
- 3.0 r---...-TT"""""T"I'""'"I""'T"-.----,
- 2.5
W
N
.....
I---+\---t--+~"'+'=-+-___l
........
o
o
- 2.0 f--+-+--tt--H-t-1
!
j
;: -1.5
-1.0 1--''rII'-T-t----t--t--t--+-l
... -0.75 1---+-"'<---+-'1.--+----+--+--+-----1
"0
1---+--+~..._4+--.r.++--+--___l
W
N
N
§
§
-0.5
2
4
DEVICE 2 AND 3
YOUT (VOLTS)
3
4
VOUT (VOLTS)
DEVICE 2
.
LED Output Direct LED Drive
LED Output Source Current
-24~_T-~-~_T-~~
-14
/
-12
/MAX
-10
/
;(
!.
...
-8
-6
-4
,
,
,,
.1
VoUT = 2.0V
-2
3.
... - ~
o
4
VOUT (VOLTS)
DEVICE 4 AND 2
4.0
4.5
".,-
S.D
VCC (VOLTS)
TRI·STATE Output Source Current
III
."
§
5.5
.6.0
DEVICE 4 AND 2
Input Load Source Current
-15~-+-~-~_+-~-t--;
-1.0 f--+-~-t--+-+----l
!...
-10
§
-5
- 0.2
I--'-----\~-~--"'k---x:__-+----l
4
4
VoUT (VOLTS)
VoUT (VOLTS)
DEVICE 5
5
DEVICE 6
TL/DD/6921-24
FIGURE 9c. COP320/COP321 Input/Output Characteristics
1·125
~ r-----------------------------------------------------------------------------------~
~
CW')
a.
Instruction Set
......
.....
Table I is a symbol table providing internal architecture, instruction operand and operational symbols used in the instruction set table.
oo
~
CW')
Table " provides the mnemonic, operand, machine code,
data flow, skip conditions and description associated with
each instruction in the COP420/COP421/COP422 instruction set.
a.
o
TABLE I. COP420/421/422/320/321/322 Instruction Set Table Symbols
o
......
o
~
CW')
Symbol
a.
oo
INTERNAL ARCHITECTURE SYMBOLS
INSTRUCTION OPERAND SYMBOLS
......
A
8
8r
Bd
C
D
EN
G
IL
d
r
~
~
~
a.
8
......
.....
~
~
a.
o
o
......
o
~
~
a.
o
o
IN
L
M
PC
Q
SA
S8
SC
SIO
SK
Definition
Definition
Symbol
4-bit Accumulator
6-bit RAM Address Register
Upper 2 bits of 8 (register address)
Lower 4 bits of 8 (digit address)
1-bit Carry Register
4-bit Data Output Port
4-bit Enable Register
4-bit Register to latch data for G 1/0 Port
Two 1-bit latches associated with the IN3 or
INo inputs
4-bit Input Port
S-bit TRI-STATE 1/0 Port
4-bit contents of RAM Memory pointed to by
8 Register
9-bit ROM Address Register (program counter)
S-bit Register to latch data for L 1/0 Port
1O-bit Subroutine Save Register A
1O-bit Subroutine Save Register 8
10 Subroutine Save Register A
4-bit Shift Register and Counter
Logic-Controlled Clock Output
4-bit Operand Field, 0-15 binary (RAM Digit Select)
2-bit Operand Field, 0-3 binary (RAM Register
Select)
a
10-bit Operand Field, 0-1023 binary (ROM Address)
y
4-bit Operand Field, 0-15 binary (Immediate Data)
RAM(s) Contents of RAM location addressed by s
ROM(t) Contents of ROM location addressed by t
OPERATIONAL SYMBOLS
+
-
.....
~
=
A
E9
:
Plus
Minus
Replaces
Is exchanged with
Is equal to
The one's complement of A
Exclusive-OR
Range of values
TABLE II. COP420/421 1422/320/321 1322 Instruction Set
Machine
Language Code
(Binary)
Data Flow
30
10011100001
A + C + RAM(8) ..... A
Carry ..... C
ADD
31
1001110001
+ RAM(8)
4A
I
1010011010 I
A
ADT
A
+ 1010
5-
10101
I
A
+y
10
10001100001
Mnemonic
Operand
Hex
Code
Skip Conditions
Description
ARITHMETIC INSTRUCTIONS
ASC
AISC
CASC
y
y
I
..... A
..... A
..... A
A+ RAM(8) + C .....
A
Carry
Add with Carry, Skip on
Carry
None
Add RAMtoA
None
Add Ten toA
Carry
Add immediate, Skip on
Carry (y #- 0)
Carry
Complement and Add with
Carry, Skip on Carry
None
Clear A
Carry ..... C
CLRA
00
10000100001
0"'" A
COMP
40
10100100001
A"'"
None
One's complement of A to A
NOP
44
10100101001
None
None
No Operation
RC
32
10011100101
"0" ..... C
None
ResetC
SC
22
10010100101
"1" ..... C
None
SetC
XOR
02
10000100101
A E9 RAM(8) ..... A
None
Exclusive-OR RAM with A
A
1-126
o
o"tJ
Instruction Set (Continued)
~
I\)
o
......
o
TABLE II. COP420/421/422/320/321/322 Instruction Set (Continued)
Mnemonic Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
~
I\)
ROM (PCs, A,M) ---+
PC7:0
None
Jump Indirect (Note 3)
.....
......
o
a ---+ PC
None
Jump
~
I\)
I\)
a ---+ PC6:0
None
Jump within Page
(Note 4)
TRANSFER OF CONTROL INSTRUCTIONS
JID
JMP
a
1111111111
6-
1011O lOOlaai
I a7:0 I
--
JP
a
I
FF
---
11 I a6:0
I
(pages 2,3 only)
or
111 I as:o
I
(all other pages)
a ---+ PCs:o
Jump to Subroutine Page
(Note 5)
--
10110110 Ia9:sl
I a7:0 I
PC + 1 ---+ SA ---+ SB ---+ SC
a ---+ PC
None
Jump to Subroutine
RET
48
10100 11000 I
SC ---+ SB ---+ SA ---+ PC
None
Return from Subroutine
RETSK
49
10100110011
SC ---+ SB ---+ SA ---+ PC
Always Skip
on Return
Return from Subroutine
then Skip
JSR
a
6-
as:o
o"tJ
W
I\)
o"tJ
None
110 1
......
o
......
o
PC + 1 ---+ SA ---+ SB ---+ SC
010 ---+ PCS:6
a ---+ PCs:o
a
o"tJ
o
I
JSRP
o"tJ
W
.....
......
o
o"tJ
I\)
W
I\)
I\)
MEMORY REFERENCE INSTRUCTIONS
CAMO
33
3C
10011100111
10011111001
A ---+ 07:4
RAM (B) ---+ 03:0
None
Copy A, RAM to 0
COMA
33
2C
10011100111
10010 11100 I
07:4 ---+ RAM (B)
03:0 ---+ A
None
Copy 0 to RAM, A
-5
100lrl01011
RAM(B) ---+ A
Br Ell r ---+ Br
None
Load RAM into A
Exclusive-OR Br with r
--
23
10010100111
1001 r I d 1
RAM(r,d) ---+ A
None
Load A with RAM pointed
to directly by r,d
. BF
11011 11111 1
ROM(PCg:a.A.M) ---+ 0
SB ---+ SC
None
Load 0 Indirect (Note 3)
LD
r
LDD
r,d
LOID
RMB
0
1
2
3
4C
45
42
43
10100111001
10100101011
10100100101
10100100111
o ---+
o ---+
o ---+
o ---+
RAM(B)o
RAM(B)1
RAM(B)2
RAM(Bb
None
Reset RAM Bit
5MB
0
1
2
3
4D
47
46
4B
1010011101 1
10100111011
10100101101
1010011011 1
1
1
1
1
RAM(B)o
RAM(Bh
RAM(B)2
RAM(Bb
None
Set RAM Bit
STII
Y
7-
10111 1 y
y ---+ RAM (B)
Bd + 1 ---+ Bd
None
Store Memory Immediate
and Increment Bd
X
r
-6
100 Ir I0110 1
RAM (B) ~ A
Br Ell r ---+ Br
None
Exchange RAM with A,
Exclusive-OR Br with r
XAD
r,d
23
10010100111
110 I r I d 1
RAM(r,d)
None
Exchange A with RAM
pointed to directly by r,d
--
1
---+
---+
---+
---+
~
A
1-127
III
C'I
C'I
C")
a.
o
Instruction Set (Continued)
o
......
....
TABLE II. COP420/421 1422/320/3211322 Instruction Set (Continued)
C'I
C")
Machine
Language Code
(Binary)
Mnemonic
o
......
Q
MEMORY REFERENCE INSTRUCTIONS (Continued)
o
C'I
C")
a.
Operand
Hex
Code
a.
XDS
r
-7
100 1r 10111
XIS
r
-4
100 I r I 0100 I
I
o
o
......
C'I
C'I
'11:1'
D-
O
o
......
....
C'I
'11:1'
Skip Conditions
Description
RAM (B) +-+ A
Bd -1 -+ Bd
Br (!) r -+ Br
Bd decrements past 0
Exchange RAM with A
and Decrement Bd,
Exclusive-OR Br with r
RAM(B) +-+ A
Bd + 1 -+ Bd
Br (!) r -+ Br
Bd increments past 15
Exchange RAM with A
and Increment Bd,
Exclusive·OR Br with r
DataFlow
REGISTER REFERENCE INSTRUCTIONS
a.
CAB
50
10101100001
A -+ Bd
None
Copy A to Bd
o
......
CBA
4E
10100111101
Bd -+ A
None
Copy BdtoA
100Irl(d-1)1
(d = 0,9:15)
or
1001110011 I
110 I r I d I
(any d)
r,d -+ B
Skip until not a LBI
Load B Immediate with
r,d (Note 6)
33
6-
1001110011 I
10010 1 Y.. I
y -+ EN
None
Load EN Immediate
(Note 7)
12
10001100101
A +-+ Br (0,0 -+ A3.A2)
None
Exchange A with Br
SKC
20
10010100001
C
=
SKE
21
1001010001
I
A
= RAM (B)
SKGZ
33
21
1001110011
1001010001
I
G3:0
33
01
11
03
13
1001110011
1000010001
1000110001
1000010011
1001010011
01
11
03
13
10000100011
1000110001 I
1000010011 I
10001100111
RAM(B)o
RAM(Bh
RAM(B)2
RAM(Bb
41
10100100011
A time-base counter
carry has occurred
since last test
o
Q
C'I
'11:1'
a.
o
LBI
r,d
--
o
33
-LEI
y
XABR
TEST INSTRUCTIONS
SKGBZ
0
1
2
3
SKMBZ
0
1
2
3
SKT
Skip if C is True
"1"
=0
Skip if G is Zero
(all 4 bits)
I
I
I
Skip if G Bit is Zero
1st byte
I
} 2nd byte
I
I
1-128
Skip if A Equals RAM
Go
G1
G2
G3
=0
=0
=0
=0
=0
=0
=0
=0
Skip if RAM Bit is Zero
Skip on Timer (Note 3)
0
0
Instruction Set (Continued)
""C
~
N
TABLE II. COP420/421/422/320/321/322 Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
0
.......
0
Description
0
""C
~
N
...A.
.......
0
INPUTIOUTPUT INSTRUCTIONS
ING
33
2A
ININ
10011100111
10010 11010 1
G~A
None
Input G Ports to A
0
Input IN Inputs to A (Note 2)
N
.......
0
""C
~
N
~
33
28
10011100111
10010 11000 1
IN
A
INIL
33
29
10011100111
10010 11001 1
IL3, CKO, "0", ILo ~ A
None
Input IL Latches to A
(Note 3)
INL
33
2E
10011100111
10010111101
L7:4 ~ RAM (B)
L3:0 ~ A
None
Input L Ports to RAM, A
33
3E
10011100111
10011 11110 1
Bd
33
y~G
5-
10011100111
10101 1 y 1
OMG
33
3A
10011100111
10011 11010 1
RAM(B)
XAS
4F
1010011111 1
A
None
0
""C
w
OBD
OGI
Y
N
0
.......
0
0
~
""C
w
N
...A.
D
None
Output Bd to D Outputs
.......
0
0
""C
w
N
N
~
~
G
SIO,C
~
SKL
None
Output to G Ports Immediate
None
Output RAM to G Ports
None
Exchange A with SIO
(Note 3)
Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to N where
o signifies the least significant bit (low-order, right-most bit). For example, A3 indicates the most significant (left-most) bit of the 4-bit register.
Note 2: The ININ Instruction is not available on the COP421/COP321 and COP422/COP322 since these devices do not contain the IN inputs.
Note 3: For additional information on the operation of the XAS, JID, LQID, INIL, and SKT instructions, see below.
Note 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction,
otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Note 5: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of Pl. A JSRP may not be used when in pages 2 or 3. JSRP
may not jump to the last word in page 2.
Note 6: LBI is a single-byte instruction if d = 0, 9, 10, 11, 12, 13, 14, or 15. The machine code for the lower 4 bits equals the binary value of the "d" data minus 1,
e.g., to load the lower four bits of B (Bd) with the value 9 (10012), the lower 4 bits of the LBI instruction equal B (10002)' To load 0, the lower 4 bits of the LBI
instruction should equal 15 (11112)'
Note 7: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a "1" or "0" in each bit of EN corresponds
with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
Description of Selected Instructions
The following information is provided to assist the user in
understanding the operation of several unique instructions
and to provide notes useful to programmers in writing
COP420/421 programs.
SIO is selected as a shift register, an XAS instruction must
be performed once every 4 instruction cycles to effect a
continuous data stream.
XAS INSTRUCTION
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location pointed
to indirectly by A and M. It loads the lower 8 bits of the ROM
address register PC with the contents of ROM addressed by
the 10-bit word, PC9:B, A, M. PC g and PCB are not affected
by this instruction.
JID INSTRUCTION
XAS (Exchange A with SIO) exchanges the 4-bit contents of
the accumulator with the 4-bit contents of the SIO register.
The contents of SIO will contain serial-in/serial-out shift register or binary counter data, depending on the value of the
EN register. An XAS instruction will also affect the SK output. (See Functional Description, EN Register, above.) If
Note that JID requires 2 instruction cycles to execute.
1-129
III
N
N
CW)
Q.
o
o
--
"N
CW)
Q.
oo
"o
N
CW)
Q.
o
o
"N
N
~
Q.
o
o
--
"N
~
Q.
oo
"o
Description of Selected Instructions (Continued)
tion. Since LaiD pushes S8 ----+ SC, the previous contents
of SC are lost. Also, when LaiD pops the stack, the previously pushed contents of S8 are left in SC. The net result is
that the content of S8 are placed in SC (S8 ----+ SC). Note
that LaiD takes two instruction cycle times to execute.
INIL INSTRUCTION
INIL (Input IL Latches to A) inputs 2 latches, IL3 and ILa (see
Figure 1tJ) and CKO into A. The IL3 and ILa latches are set if
a low-going pulse ("1" to "0") has occurred on the IN3 and
INo inputs since the last INIL instruction, provided the input
pulse stays low for at least two instruction times. Execution
of an INIL inputs IL3 and ILa into A3 and AO respectively,
and resets these latches to allow them to respond to subsequent low-going pulses on the IN3 and INo lines. If CKO is
~ask programmed as a general purpose input, an INIL will
Input the state of CKO into A2. If CKO has not been so
programmed, a "1" will be placed in A2. A "0" is always
placed in A1 upon the execution of an INIL. The general
purpose inputs IN3-INo are input to A upon execution of an
ININ instruction. (See Table II, ININ instruction.) INIL is useful in recognizing pulses of short duration or pulses which
occur too often to be read conveniently by an ININ instruction.
SKT INSTRUCTION
The SKT (Skip On Timer) instruction tests the state of an
internal 10-bit time-base counter. This counter divides the
instruction cycle clock frequency by 1024 and provides a
latched indication of counter overflow. The SKT instruction
tests this latch, executing the next program instruction if the
latch is not set. If the latch has been set since the previous
test, the next program instruction is skipped and the latch is
reset. The features associated with this instruction, therefore, allow the COP420/421 to generate its own time-base
for real-time processing rather than relying on an external
input signal.
For example, using a 2.097 MHz crystal as the time-base to
the clock generator, the instruction cycle clock frequency
will be 131 kHz (crystal frequency + 16) and the binary
counter output pulse frequency will be 128 Hz. For time-ofday or similar real-time processing, the SKT instruction can
call a routine which increments a "seconds" counter every
128 ticks.
Note: IL latches are not cleared on reset.
COP420
N
~
Q.
o
o
INSTRUCTION SET NOTES
a. The first word of a COP420/421 program (ROM address
0) must be a CLRA (Clear A) instruction.
b. Although skipped instruction are not executed, one instruction cycle time is devoted to skipping each byte of
the skipped instruction. Thus all program paths take the
same number of cycle times whether instructions are
skipped or executed except JID and LaiD. LaiD and JID
take two cycle times if executed and one if skipped.
TLlDD/6921-25
FIGURE 10
LQID INSTRUCTION
c. The ROM is organized into 16 pages of 64 words each.
The Program Counter is a 10-bit binary counter, and will
count through page boundaries. If a JP, JSRP, JID or
LaiD instruction is located in the last word of a page, the
instruction operates as if it were in the next page. For
example: a JP located in the last word of a page will jump
to a location in the next page. Also, a LaiD or JID located in the last word of page 3, 7, 11 or 15 will access data
in the next group of four pages.
LaiD (Load a Indirect) loads the 8-bit a register with the
contents of ROM pointed to by the 1O-bit word PCg. PCe. A,
M. LaiD can be used for table lookup or code conversion
such as 8CD to seven-segment. The LaiD instruction
"pushes" the stack (PC + 1 ----+ SA ----+ S8 ----+ SC) and
replaces the least significant 8 bits of PC as follows: A ----+
PC7:4, RAM(8) ----+ PC3:0, leaving PCg and PCe unchanged. The ROM data pointed to by the new address is
fetched and loaded into the a latches. Next, the stack is
"popped" (SC ----+ S8 ----+ SA ----+ PC), restoring the
saved value of PC to continue sequential program execu-
1-130
o
o"'0
Option List
~
I\)
The COP420/421 1422 mask-programmable options are assigned numbers which correspond with the COP420 pins.
Option 16: SI Input
same as Option 9
o
.......
The following is a list of COP420 options. When specifying a
COP421 or COP422 chip, Options 9, 10, 19, 20 and 29 must
all be set to zero. When specifying a COP422 chip, Options
21, 22, 27 and 28 must also be zero, and Option 2 must not
be a 1. The options are programmed at the same time as
the ROM pattern to provide the user with the hardware flexibility to interlace to various 1/0 components using little or
no external circuitry.
Option 17: SO Driver
= 0: standard output (A)
= 1: open-drain output (B)
= 2: push-pull output (C)
o"'0
Option 18: SK Driver
same as Option 17
o"'0
Option 19: INo Input
same as Option 9
Option 1 = 0: Ground-no options available
Option 20: IN3 Input
same as Option 9
Option 2: CKO Pin
= 0: clock generator output to crystal
not available if option 3 = 4 or 5)
= 1: Pin is RAM power supply (VR) input
(Not available on COP422/COP322)
= 2: general purpose input with load device
= 4: general purpose Hi Z input
Option 21: Go 1/0 Port
= 0: Standard output (A)
= 1: Open-Drain output (B)
o
Option 22: G1 1/0 Port
same as Option 21
Option 3: CKI Input
= 0: crystal input devided by 16
= 1: crystal input divided by 8
= 2: TTL external clock input divided by 16
= 3: TTL external clock input divided by 8
= 4: single-pin RC controlled oscillator (+ 4)
= 5: Schmitt trigger clock input (+ 4)
Option 23: G2 1/0 Port
same as Option 21
Option 4: RESET Pin
= 0: load devices to Vee
= 1: Hi-Z input
Option 26: 02 Output
same as Option 25
Option 24: G3 1/0 Port
same as Option 21
Option 25: 03 Output
= 0: Standard output (A)
= 1: Open-Drain output (8)
Option 27: 01 Output
same as Option 25
Option 5: L7 Driver
= 0: Standard output (Figure 90)
= 1: Open-Drain output (E)
= 2: LED direct drive output (F)
= 3: TRI-STATE push-pull output (G)
Option 28: Do Output
same as Option 25
Option 29: COP Function
= 0: normal operation
= 1: MICROBUS option
Option 6: La Driver
same as Option 5
Option 30: COP Bonding
= 0: COP420 (28-pin device)
= 1: COP421 (24-pin device)
= 2: 28- and 24-pin device
= 3: COP422 (20-pin device)
= 4: 28- and 20-pin device
= 5: 24- and 20-pin device
= 6: 28-, 24- and 20-pin device
Option 7: L5 Driver
same as Option 5
Option 8: 4 Driver
same as Option 5
Option 9: IN1 Input
= 0: load devices to Vee (H)
= 1: Hi-Z input (I)
Option 31: In Input Levels
= 0: normal input levels
= 1: Higher voltage input levels
("0" = 1.2V, "1" = 3.6V)
Option 10: IN2 Input
same as Option 9
Option 11 = 0: Vee Pin-no options available
Option 12: L3 Driver
same as Option 5
Option 32: G Input Levels
same as Option 31
Option 13: L2 Driver
same as Option 5
Option 33: L Input Levels
same as Option 31
Option 14: L1 Driver
same as Option 5
Option 34: CKO Input Levels
same as Option 31
Option 15: Lo Driver
same as Option 5
Option 35: SI Input Levels
same as Option 31
1-131
o
~
I\)
......
o
.......
~
I\)
I\)
.......
o
o
"'0
W
I\)
o
.......
o
o
"'0
W
I\)
......
.......
o
o"'0
W
I\)
I\)
N
N
C")
Q.
o
o.......
..N
C")
Q.
oo
.......
o
N
C")
Q.
oo
.......
N
N
-.::t
Q.
o
o
.......
..N
-.::t
Q.
o
o
.......
o
N
-.::t
Q.
o
o
Option List (Continued)
2. The D3-DO outputs drive the digits of the mulitplexed display directly and scan the columns of the 4 x 4 keyboard
matrix.
COP OPTION LIST
The following option information is to be sent to National
along with the EPROM.
OPTION DATA
OPTION 1 VALUE 0
IS: GROUND PIN
OPTION 2 VALUE - _ _ _ _ IS: CKO PIN
OPTION 3 VALUE- _ _ _ _ IS: CKIINPUT
OPTION 4 VALUE- _ _ _ _ IS: RESET INPUT
OPTION 5 VALUE = _ _ _ _ IS: L7 DRIVER
OPTION 6 VALUE = _ _ _ _ IS: L6 DRIVER
OPTION 7 VALUE = _ _ _ _ IS: Ls DRIVER
OPTION 8 VALUE = _ _ _ _ IS: L4 DRIVER
OPTION 9 VALUE = _ _ _ _ IS: IN1 INPUT
OPTION 10 VALUE = _ _ _ _ IS: IN21NPUT
OPTION 11 VALUE - _ _ _ _ IS: VCC PIN
OPTION 12 VALUE - _ _ _ _ IS: L3 DRIVER
OPTION 13 VALUE - _ _ _ _ IS: L2 DRIVER
OPTION 14 VALUE IS: L1 DRIVER
OPTION 15 VALUE - _ _ _ _ IS: Lo DRIVER
OPTION 16 VALUE - _ _ _ _ IS: SIINPUT
OPTION 17 VALUE - _ _ _ _ IS: SO DRIVER
OPTION 18 VALUE = _ _ _ _ IS: SK DRIVER
OPTION 19 VALUE - _ _ _ _ IS: INo INPUT
OPTION 20 VALUE IS: IN3 INPUT
OPTION 21 VALUE - _ _ _ _ IS: Go 1/0 PORT
OPTION 22 VALUE - _ _ _ _ IS: G1 1/0 PORT
OPTION 23 VALUE - _ _ _ _ IS: G21/0 PORT
OPTION 24 VALUE - _ _ _ _ IS: G31/0 PORT
OPTION 25 VALUE - _ _ _ _ IS: D3 OUTPUT
IS: D2 OUTPUT
OPTION 26 VALUE OPTION 27 VALUE - _ _ _ _ IS: D1 OUTPUT
OPTION 28 VALUE - _ _ _ _ IS: Do OUTPUT
OPTION 29 VALUE - _ _ _ _ IS: COP FUNCTION
OPTION 30 VALUE - _ _ _ _ IS: COP BONDING
OPTION 31 VALUE - _ _ _ _ IS: IN INPUT LEVELS
IS: G INPUT LEVELS
OPTION 32 VALUE OPTION 33 VALUE - _ _ _ _ IS: L INPUT LEVELS
OPTION 34 VALUE - _ _ _ _ IS: CKO INPUT LEVELS
OPTION 35 VALUE - _ _ _ _ IS: SIINPUT LEVELS
3. The IN3-INo inputs are used to input the 4 rows of the
keyboard matrix. Reading the IN lines in conjunction with
the current value of the D outputs allows detection, debouncing, and decoding of anyone of the 16 keyswitches.
4. CKI is configured as a single-pin oscillator input allowing
system timing to be controlled by a single-pin RC network. CKO is therefore available for use as a VR RAM
power supply pin. RAM data integrity is thereby assured
when the main power supply is shut down (see RAM
Keep-Alive option description).
5. SI is selected as the input to a binary counter input. With
SIO used as a binary counter, SO and SK can be used as
general purpose outputs.
6. The 4 bidirectional G I/O ports (G3-GO) are available for
use as required by the user's application.
APPLICATION #2: MUSICAL ORGAN AND MUSIC BOX
Play Mode: Twenty-five musical keys and 25 LEDs are provided to denote F to F with half notes in between. All the
keys and LEDs are directly detected and driven by the microprocessor. Depression of the key will give the corresponding musical note and light up the corresponding LED.
Clear: Memory is provided to store a played tune. Depression of the CLEAR key erases the memory and the microprocessor is ready to store new musical notes. A maximum
of 28 notes can be stored where each note can be of one to
eight musical beats. (Two bytes of memory are required to
store one musical note. Any note longer than eight musical
beats will require additional memory space for storage.)
Playback: Depression of this button will playback the tune
stored in the memory since last "clear."
Preprogrammed Tunes: There are ten preprogrammed
tunes (each has an average of 55 notes) masked in the
chip. Any tune can be recalled by depressing the "Tune
Button" followed by the corresponding "Sharp Key."
Learn Mode: This mode is for the player to learn the ten
preprogrammed tunes. By pressing the "Learn Button" followed by the corresponding "Sharp Key," the LEDs will be
lighted up one by one to indicate the notes of the selected
tune. The LED will remain "on" until the player presses the
correct musical key; the LED for the next note will then be
lighted up.
TEST MODE (Non-Standard Operation)
The SO output has been configured to provide for standard
test procedures for the custom-programmed COP420. With
SO forced to logic "1", two test modes are provided, depending upon the value of SI:
Pause: In addition to the 25 musical keys, there is a special
pause key. The depression of this key generates a blank
note to the memory.
a. RAM and Internal Logic Test Mode (SI = 1)
b. ROM Test Mode (SI = 0)
Note: In the Learn Mode when playing "Oh Susanna," the pause key must
be used.
These special test modes should not be employed by the
user; they are intended for manufacturing test only.
Tempo: This is a control input to the musical beat time oscillator for varying the speed of the musical tunes.
APPLICATION # 1: COP420 General Controller
Vibrato: This is a switch control to vary the frequency vibration of the note.
Figure 8 shows an interconnect diagram for a COP420 used
as a general controller. Operation of the system is as follows:
Tunes listing: The following is a listing of the ten preprogrammed tunes: 1) Jingle Bells, 2) Twinkle, Twinkle Little
Star, 3) Happy Birthday, 4) Yankee Doodle, 5) Silent Night,
6) This Old Man, 7) London Bridge Is Falling Down, 8) Auld
Lang Syne, 9) Oh Susanna, 10) Clementine.
1. The LrLo outputs are configured as LED Direct Drive
outputs, allowing direct connection to the segments of
the display.
1-132
o
o
Typical Applications
-a
~
N
Q
........
o
o-a
~
N
.....
........
o
o
-a
~
N
N
........
o
o-a
w
N
Q
COP420
........
o
00
4 GENERAL
I/O
o
01
02
0]
RESET
-a
w
N
.....
........
o
o-a
INO
fO
INI I~--+-~~--~~--~----~~ 4x4
KEYSWITCH
IN2 I~--+-~~-~~--~---~~ MATRIX
G]
EVENT
COUNTER - - - - - . SI"
INPUT
w
N
N
IN]
SK"
SO·
"51, SO and SK may also be used for serial 110
TL/DD/6921-26
FIGURE 11. COP420 Keyboard Display Interface
Circuit Diagram of COP420 Musical Organ
Vce
11
5 L7
6
Vee
1M3
~L~
20
La
L4
12
L3
13
rw 1
470"F
L5
VR
1M
}V
-
TEMPO ':"
l2
Ll
La
60
SK
,.
61
COP420·QRl(
62
Vee
63
220"F
I:~··
Do
0,
10Q
CKI
02
*'00 PF
':"
':"
03
':"
TL/DD/6921-27
1-133
C'I
C'I
C")
a..
o
o
.......
.....
C'I
Typical Applications
Music Box Application with Direct Key Access
C")
a..
IN4148
o
o
.......
o
(Continued)
4.SV-8.3V ~
C'I
MM74C04
C")
a..
o
o
.......
C'I
C'I
~
a..
o
o
.......
.....
C'I
~
a..
o
COP420·QRX
Go
o
.......
o
C'I
~
a..
o
o
GND
TL/DD/6921-28
Bell Sound Circuit
~
If
vee
nnnn
33k
PIN 18 sK-----"VI'I\r---i1C
This additional circuit provides tinkling effect for the musical note.
TL/DD/6921-29
Auto Power Shut-Off Circuit
r-.---__
NA32XY
o-~.-~~--~
--~~--
IN4148
TL/DD/6921-30
This circuit automatically turns off the musical organ if none of the keys are pressed within approximately 30 seconds.
1-134
o
o
~National
"U
~
I\)
~ Semiconductor
o
r
........
o
COP420L/COP421 L/COP422L/COP320L/COP321 LI
COP322L Single-Chip N-Channel Microcontrollers
o"U
General Description
Features
The COP420L, COP421 L, COP422L, COP320L, COP321 L,
and COP322L Single-Chip N-Channel Microcontrollers are
members of the COPSTM family, fabricated using N-channel, silicon gate MOS technology. These controller oriented
processors are complete microcomputers containing all
system timing, internal logic, ROM, RAM, and 1/0 necessary to implement dedicated control functions in a variety of
applications. Features include single supply operation, a variety of output configuration options, with an instruction set,
internal architecture, and 1/0 scheme designed to facilitate
keyboard input, display output, and BCD data manipulation.
The COP421 Land COP422L are identical to the COP420L,
but with 19 and 15 1/0 lines, respectively, instead of 23.
They are an appropriate choice for use in numerous human
interface control environments. Standard test procedures
and reliable high-density fabrication techniques provide the
medium to large volume customers with a customized controller oriented processor at a low end-product cost.
o
o
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The COP320L, COP321 L, and COP322L are exact functional equivalents, but extended temperature range versions, of
the COP420L, COP421 L, and COP422L respectively.
•
•
~
I\)
.....
r
........
Low cost
Powerful instruction set
1k x 8 ROM, 64 x 4 RAM
23 110 lines (COP420L)
True vectored interrupt, plus restart
Three-level subroutine stack
16 P.s instruction time
Single supply operation (4.5V-6.3V)
Low current drain (9 rnA max)
Internal time-base counter for real-time processing
Internal binary counter register with MICROWIRETM
compatible serial 110
General purpose and TRI-STATE® outputs
LSTTL/CMOS compatible in and out
Direct drive of LED digit and segment lines
Softwarelhardware compatible with other members of
COP400 family
Extended temperature range deviceCOP320LlCOP321 LlCOP322L (-40°C to + 85°C)
Wider supply range (4.5V-9.5V) optionally available
Block Diagram
RISET
0]
02
0,·
00·
.....-------+_~ ::}
'0
HlYElSTACK
M'CROWlRlIIO
$1
----------
--,
I
I
I
I
I
5
20
'0
•
8
7
•
12
13
14
15
11
IN]- INl INI- "'10
TL/DD/882S-1
°Not available on COP422L1COP322L
FIGURE 1
1-135
"U
~
I\)
I\)
r
........
o
o"U
W
I\)
o
r
........
o
o"U
W
I\)
.....
r........
o
o"tJ
W
I\)
I\)
r
..J
N
N
Cf)
D.
o(,)
:l
,....
N
Cf)
D.
COP420L/COP421 L/COP422L
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
o(,)
Voltage at Any Pin Relative to GND
..J
Ambient Storage Temperature
......
o
N
Cf)
Ambient Operating Temperature
Power Dissipation
COP420LlCOP421 L
0.75W at 25·C
0.4Wat70·C
0.65W at 25·C
0.3Wat 70·C
COP422L
-0.5V to + 1OV
O·C to +70·C
- 65·C to + 150·C
Lead Temperature (Soldering, 10 sec.)
300·C
Total Source Current
120mA
Total Sink Current
120 mA
Absolute maximum ratings indicate limits beyond which
damage to the device may occur. DC and AC electrical
specifications are not ensured when operating the device at
absolute maximum ratings.
D.
oCo)
......
..J
N
N
~
D.
o
(,)
......
DC Electrical Characteristics o·c s: T A s:
,....
..J
Parameter
N
+ 70·C, 4.5V
(Note 1)
~
Standard Operating Voltage (Vee)
o
(,)
Optional Operating Voltage (Vee)
..J
Power Supply Ripple
Peak to Peak
N
Operating Supply Current
All Inputs and Outputs Open
D.
Input Voltage Levels
D.
......
o
~
oCo)
s: Vee s:
Conditions
CKI Input Levels
Crystal Input (+ 32, + 16, + 8)
Logic High (VIH) Vee = Max
Logic High (VI H)
Vee = 5V ±5%
Logic Low (VIU
Max
Units
4.5
6.3
V
4.5
9.5
V
0.5
V
9
mA
Min
3.0
Schmitt Trigger Input (+ 4)
Logic High (VIH)
Logic Low (VIU
\
9.5V unless otherwise noted
V
2.0
-0.3
0.4
V
V
0.7 Vee
-0.3
0.6
V
V
0.7 Vee
-0.3
0.6
V
V
2.0
2.5
V
RESET Input Levels
Logic High
Logic Low
Schmitt Trigger Input
SO Input Level (Test Mode)
(Note 3)
All Other Inputs
Logic High
Logic High
Logic Low
Vee = Max
with TTL Trip Level Options
Selected, Vee = 5V ±5%
3.0
2.0
-0.3
0.8
V
V
V
Logic High
Logic Low
with High Trip Level Options
Selected
3.6
-0.3
1.2
V
V
7
pF
+1
IJ-A
0.4
V
V
0.2
V
V
Input Capacitance
-1
Hi-Z Input Leakage
Output Voltage Levels
LSTTL Operation
Logic High (VOH)
Logic Low (VOU
Vee = 5V ±10%
IOH = -251J-A
IOL = 0.36ma
CMOS Operation (Note 2)
Logic High
Logic Low
Vee = 4.5V
IOH = -10 IJ-A
IOL = +10 IJ-A
Note 1: Vee voltage change must be less than 0.5V in a 1 ms period to maintain proper operation.
Note 2: TRI·STATE and LED configurations are excluded.
Note 3: SO output "0" level must be less than O.BV for normal operation.
1-136
2.7
Vee -1
o
o"'til
COP420L/COP421 L/COP422L
~
DC Electrical Characteristics O°C ~ T A ~
Parameter
Output Current Levels
Output Sink Current
SO and SK Outputs (Iod
Lo-L7 Outputs and Standard
GO-G3, 00-03 Outputs (Iod
Vee
Vee
Vee
Vee
Vee
Vee
GO-G3 and 00-03 Outputs with
Very High Current Options (Iod
Vee
Vee
Vee
CKI (Single-Pin RC Oscillator)
CKO
Vee
Vee
=
=
=
=
=
=
=
=
=
=
=
=
=
=
Vee
Vee
Vee
=
=
=
=
=
=
LED Configuration, Lo-L7
Outputs, Low Current
Driver Option (IOH)
Vee
Vee
LED Configuration, Lo-L7
Outputs, High Current
Driver Option (IOH)
Vee
Vee
TAl-STATE Configuration,
Lo-L7 Outputs, Low
Current Driver Option (IOH)
Vee
Vee
Vee
TAl-STATE Configuration,
Lo-L7 Outputs, High
Current Driver Option (IOH)
Vee
Vee
Vee
Push-Pull Configuration
SO and SK Outputs (IOH)
~ Vee ~ 9.5V unless otherwise noted (Continued)
Max
Units
N
o
r......
o
Conditions
Min
= O.4V
= O.4V
= O.4V
9.5V, VOL = O.4V
6.3V, VOL = O.4V
4.5V, VOL = O.4V
9.5V, VOL = 1.0V
6.3V, VOL = 1.0V
4.5V, VOL = 1.0V
9.5V, VOL = 1.0V
6.3V, VOL = 1.0V
4.5V, VOL = 1.0V
4.5V, VIH = 3.5V
4.5V, VOL = O.4V
1.8
1.2
0.9
mA
mA
mA
r......
0.4
0.4
0.4
mA
mA
mA
~
15
11
7.5
mA
mA
mA
30
22
15
mA
mA
mA
2
0.2
mA
mA
o"'til
~
Vee
Vee
Vee
GO-G3 and 00-03 Outputs with
High Current Options (Iod
Output Source Current
Standard Configuration,
All Outputs (IOH)
+ 70°C, 4.5V
Vee
Vee
Vee
9.5V, VOL
6.3V, VOL
4.5V, VOL
2.0V
2.0V
2.0V
-140
-75
-30
9.5V, VOH
6.3V, VOH
4.5V, VOH
=
=
=
=
=
=
4.75V
2.4V
1.0V
-1.4
-1.4
-1.2
=
=
9.5V, VOH
6.0V, VOH
=
=
2.0V
2.0V
-1.5
-1.5
-18
-13
mA
mA
=
=
=
=
=
=
=
=
=
9.5V, VOH
6.0V, VOH
= 2.0V
= 2.0V
9.5V, VOH = 5.5V
6.3V, VOH = 3.2V
4.5V, VOH = 1.5V
9.5V, VOH = 5.5V
6.3V, VOH = 3.2V
4.5V, VOH = 1.5V
5.0V, VIL = OV
-3.0
-3.0
-35
-25
mA
mA
9.5V, VOH
6.3V, VOH
4.5V, VOH
-800
-480
-250
p.A
p.A
p.A
mA
mA
mA
-0.75
-0.8
-0.9
mA
mA
mA
-1.5
-1.6
-1.8
mA
mA
mA
-140
p.A
3.0
mA
+2.5
p.A
All Outputs Combined
120
mA
0, G Ports
120
mA
4
mA
4
mA
1.5
mA
Input Load Source Current
Vee
CKO Output
RAM Power Supply Option
Power Requirement
VR
=
-10
3.3V
TRI-STATE Output Leakage
Current
-2.5
Total Sink Current Allowed
L7- L4
L3- LO
All Other Pins
Total Source Current Allowed
All 1/0 Combined
120
mA
L7- L4
L3- LO
60
mA
60
mA
Each L Pin
30
mA
All Other Pins
1.5
mA
1-137
N
......
o
o"'til
N
N
r......
o
o"'til
(,,)
N
o
r......
o
o"'til
(,,)
N
......
r......
o
o"'til
(,,)
N
N
r-
..J
C\I
C\I
C")
D-
COP320L/COP321 L/COP322L
oo
Absolute Maximum Ratings
..J
Voltage at Any Pin Relative to GND
C\I
Ambient Operating Temperature
D-
Ambient Storage Temperature
..J
C
Power Dissipation
COP320LlCOP321 L
.......
,....
C")
O
o
.......
Lead Temperature (Soldering, 10 sec.)
300°C
0.7SW at 2Soc
O.4W at 70°C
0.2SW at 8SoC
0.6SW at 2Soc
0.20W at 70°C
C")
D-
COP322L
..J
C\I
C\I
-.::t
D-
O
o
.......
,....
..J
C\I
-.::t
D-
DC Electrical Characteristics
-40°C
Parameter
~
Total Source Current
120mA
Total Sink Current
120mA
Absolute maximum ratings indicate limits beyond which
damage to the device may occur. DC and AC electrical
specifications are not ensured when operating the device at
absolute maximum ratings.
- 6SoC to + 1S0°C
C\I
O
o
.......
-O.SVto +10V
- 40°C to + 8Soc
TA
~
+8soC,4.SV
Conditions
Standard Operating Voltage (VeC>
(Note 1)
Optional Operating Voltage (VeC>
~
Vee
~
7.SVunlessotherwisenoted
Min
Max
Units
4.S
S.S
V
4.S
7.S
V
O
o.......
Power Supply Ripple
Peak to Peak
O.S
V
Operating Supply Current
All Inputs and Outputs Open
11
mA
C
C\I
Input Voltage Levels
..J
-.::t
D-
O
o
CKllnput Levels
Crystal Input
Logic High (VIH) Vee
Logic High (VIH)
Vee = SV ±S%
Logic Low (VIU
=
3.0
Max
Schmitt Trigger Input
Logic High (VI H)
Logic Low (VIU
RESET Input Levels
Logic High
Logic Low
Schmitt Trigger Input
SO Input Level (Test Mode)
(Note 3)
V
2.2
-0.3
0.3
V
V
0.7 Vee
-0.3
0.4
V
V
0.7 Vee
-0.3
0.4
V
V
2.2
2.S
V
All Other Inputs
Logic High
Logic High
Logic Low
Vee = Max
with TTL Trip Level Options
Selected, Vee = SV ±S%
3.0
2.2
-0.3
0.6
V
V
V
Logic High
Logic Low
with High Trip Level Options
Selected
3.6
-0.3
1.2
V
V
7
pF
+2
p,A
0.4
V
V
0.2
V
V
Input Capacitance
-2
Hi-Z Input Leakage
Output Voltage Levels
LSTTL Operation
Logic High (VOH)
Logic Low (VoU
Vee = SV ±10%
IOH = -20 p,A
IOL = 0.36mA
CMOS Operation (Note 2)
Logic High
Logic Low
Vee = 4.SV
IOH = -10 p,A
IOL = +10 p,A
Note 1: Vee voltage change must be less than O.SV in alms period to maintain proper operation.
Note 2: TRI-STATE and LED configurations are excluded.
Note 3: SO output "0" level must be less than O.6V for normal operation.
1-138
2.7
Vee -1
o
o"'C
COP320L/COP321 L/COP322L
~
I\,)
o
DC Electrical Characteristics
r......
-40°C ~ TA ~ + 85°C, 4.5V ~ Vee ~ 7.5V unless otherwise noted (Continued)
Parameter
Output Current Levels
Output Sink Current
SO and SK Outputs (100
Conditions
Max
Units
o
"'C
~
....'"
Vee
Vee
Vee
Lo-L7 Outputs and Standard
GO-G3 and 00- 0 3 Outputs (100
Vee
Vee
Vee
GO-G3 and 00-03 Outputs with
High Current Options (100
Vee
Vee
Vee
GO-G3 and 00-03 Outputs with
Very High Current Options (100
Vee
Vee
Vee
CKI (Single-Pin AC Oscillator)
CKO
Vee
Vee
Output Source Current
Standard Configuration,
All Outputs (IOH)
o
Min
Vee
Vee
Vee
Push-Pull Configuration
SO and SK Outputs (IOH)
Vee
Vee
Vee
LED Configuration, Lo-L7
Outputs, Low Current
Driver Option (IOH)
Vee
Vee
Vee
LED Configuration, Lo-L7
Outputs, High Current
Driver Option (IOH)
Vee
Vee
Vee
TAl-STATE Configuration,
Lo-L7 Outputs, Low
Current Driver Option (IOH)
Vee
Vee
Vee
TA I-STATE Configuration,
Lo-L7 Outputs, High
Current Driver Option (lOH)
Vee
Vee
Vee
Input Load Source Current
Vee
CKOOutput
AAM Power Supply Option
Power Aequirement
VR
=
=
=
=
=
=
=
=
=
=
=
=
=
=
7.5V, VOL
5.5V, VOL
4.5V, VOL
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
= 2.0V
= 2.0V
= 2.0V
7.5V, VOH = 3.75V
5.5V, VOH = 2.0V
4.5V, VOH = 1.0V
7.5V, VOH = 2.0V
6.0V, VOH = 2.0V
5.5V, VOH = 2.0V
7.5V, VOH = 2.0V
6.0V, VOH = 2.0V
5.5V, VOH = 2.0V
7.5V, VOH = 4.0V
5.5V, VOH = 2.7V
4.5V, VOH = 1.5V
7.5V, VOH = 4.0V
5.5V, VOH = 2.7V
4.5V, VOH = 1.5V
5.0V, VIL = OV
=
= OAV
= OAV
= OAV
7.5V, VOL = 0.4V
5.5V, VOL = OAV
4.5V, VOL = OAV
7.5V, VOL = 1.0V
5.5V, VOL = 1.0V
4.5V, VOL = 1.0V
7.5V, VOL = 1.0V
5.5V, VOL = 1.0V
4.5V, VOL = 1.0V
4.5V, VIH = 3.5V
4.5V, VOL = OAV
7.5V, VOH
5.5V, VOH
4.5V, VOH
r-
104
1.0
0.8
004
004
004
mA
mA
rnA
12
9
7
mA
mA
mA
24
18
14
mA
mA
mA
r......
o
o
2
0.2
mA
mA
W
-100
-55
-28
-900
-600
-350
-0.85
-1.1
-1.2
o
o"'C
W
I\,)
o
"'C
....
'"
r......
o
r-
-2.7
-2.7
-1.4
-54
-34
-30
mA
mA
mA
-0.7
-0.6
-0.9
mA
mA
mA
-1.4
-1.2
-1.8
mA
mA
mA
-200
p.A
4.0
mA
+5
p.A
Total Sink Current Allowed
All Outputs Combined
120
rnA
0, G Ports
120
mA
L7-4
4
mA
L3-Lo
All Other Pins
4
mA
1.5
mA
All 1/0 Combined
120
mA
L7- L4
60
mA
L3-Lo
Each L Pin
60
mA
30
rnA
All Other Pins
1.5
mA
Total Source Current Allowed
1-139
'"
'"
mA
mA
mA
mA
mA
mA
-5
~
r......
o"'C
-27
-17
-15
-10
o
o"'C
p.A
p.A
p.A
-1.4
-1.4
-0.7
3.3V
TAl-STATE Output Leakage
Current
......
mA
mA
mA
W
I\,)
I\,)
..J
N
N
(f)
a..
o
o
......
AC Electrical Characteristics
COP420LlCOP421 LlCOP422L:
..J
N
a..
oo
......
Conditions
Instruction Cycle Time-te
+32 Mode
+ 16 Mode
+8 Mode
+4 Mode
Input Frequency-fl
o
N
(f)
a..
o
o
::J
N
Max
Units
16
40
,...s
0.8
0.4
0.2
0.1
2.0
1.0
0.5
0.25
MHz
MHz
MHz
MHz
30
Duty Cycle
Rise Time
N
~
fl = 2 MHz
Fall Time
a..
o
......
Min
CKI
..J
o
+ 70·C, 4.5V !>: Vee!>: 9.5V unless otherwise noted
Parameter
~
(f)
o·c !>: TA !>:
COP320LlCOP321L/COP322L: -40·C!>: TA!>: +85·C,4.5V!>: Vee!>: 7.5Vunlessotherwisenoted
R = 56kn ±5%
C = 100pF ±10%
CKI Using RC (+ 4)
..J
16
60
%
120
ns
80
ns
28
,...s
~
N
Instruction Cycle Time (Note 1)
~
a..
o
o
......
..J
o
CKO as SYNC Input
N
INPUTS:
a..
IN3-INo, G3-GO, L7- LO
~
o
ns
400
tSYNe
o
tSETUP
tHOLD
8.0
1.3
tSETUP
tHOLD
2.0
1.0
SI
,...s
,...s
Test Condition:
CL = 50 pF, RL = 20 kn, VOUT = 1.5V
OUTPUT PROPAGATION DELAY
SO, SK Outputs
t p d1, tpdO
4.0
,...s
5.6
,...s
All Other Outputs
tp d1, tpdO
Note 1: Variation due to the device included.
Timing Diagrams
CKI
SK (ASA
CLOCK _
--l
......fIIIIIIj(lJjl'
1"""~::.::...
IN3-INO.
____
~~'iIII
!-tSETUP--l I-tHOLO
G3-GOc~~&Lgi _\._~ _ _ _......."""iJIiIIII.""""'' ' ' ' ' ' ' ' ' iJIiIIII.'lIIII.
INPUTS
G~;~&.~~~~~
I-!==1
!I/J///J//!///J""==""""""""""*'='V=-O-H- - - - - - - - -...........,:m'IIJIJIM!oIIf-.;..au,_______
OUTPUTS
TLIDD/882S-S
FIGURE 3. Input/Output Timing Diagrams (Crystal Dlvide-by-16 Mode)
CKI
CKO
(INPUT)
TLIDD/882S-6
FIGURE 3a. Synchronization Timing
1-140
o
o"0
Connection Diagrams
~
so Wide and DIP
03
L7
mrr
G3
L7
GZ
L8
L6
L4
~gmnl 18
L5
SK
L4
SO
12
LZ
11
o"0
~
....
N
C
o
o"0
vcc
SI
VCC
L3
o
01
OZ
03
G3
GZ
Gl
GO
CKO
CKI
OZ
iiffif
L&
o
r......
DO
GNO
CKI
N
SO Wide and DIP
~
L3
N
L2
L1
Ll
N
r......
TLlDD/8825-3
TL/DD/8825-4
Top View
Top View
Order Number COP421L-XXXIN
or COP321L-XXXIN
See NS Molded Package Number N20A
Order Number COP422L-XXX/N
or COP322L-XXXIN
See NS Molded Package Number N24A
Order Number COP321L-XXX/D
or COP421L-XXX/D
See NS Hermetic Package Number D24C
Order Number COP322L-XXX/D
or COP422L-XXX/D
See NS Hermetic Package Number D20A
Order Number COP321L-XXX/WM
or COP421L-XXX/WM
See NS Surface Mount Package Number M24B
Order Number COP322L-XXX/WM
or COP422L-XXX/WM
See NS Surface Mount Package Number M20B
Dual-In Line Package
PLCC
03
L7
G3
L6
L4
G2
L5
Gl
L4
GO
INI
INZ
VCC
L3
L2
IN3
IN2
11
INO
L1
Vee
TL/DD/8825-2
Top View
TLlDD/8825-27
Order Number COP420L-XXX/N
or COP320L-XXXIN
See NS Molded Package Number N28B
Order Number COP320L-XXX/V
or COP420L-XXX/V
See NS PLCC Package Number V28A
Order Number COP320L-XXX/D
or COP420L-XXX/D
See NS Hermetic Package Number D28C
FIGURE 2
Pin Descriptions
Pin
L7-Lo
G3-GO 4 bidirectional 1/0 ports
D3- DO 4 general purpose outputs
IN3-INo 4 general purpose inputs (COP420L only)
Serial input (or counter input)
SI
SO
Description
Pin
Description
8 bidirectional 1/0 ports with TRI-STATE
Serial output (or general purpose output)
1-141
SK
Logic-controlled clock (or general purpose output)
CKI
System oscillator input
CKO
System oscillator output (or general purpose input, RAM power supply or SYNC input)
RESET
System reset input
Vee
Power supply
GND
Ground
W
N
o
r......
o
o"0
W
N
....
r-
......
o
o"0
W
N
N
r-
L7
L8
LS
INI
o
o"0
....I
N
N
C")
a.
o
o
......
....I
-N
C")
a.
o
o
......
....I
o
N
C")
a.
oo
......
....I
N
N
0II:t'
a.
o
o
......
....I
-N
0II:t'
a.
o
o......
....I
o
N
~
a.
o
o
Functional Description
For ease of reading this description, only COP420L and/or
COP421 L are referenced; however, all such references apply also to COP320L, COP321 L, COP322L, or COP422L.
can enable SK to be a sync clock each instruction cycle
time. (See XAS instruction and EN register description, below.)
A block diagram of the COP420L is given in Figure 1. Data
paths are illustrated in simplified form to depict how the various logic elements communicate with each other implementing the instruction set of the device. Positive logic is
used. When a bit is set, it is a logic "1" (greater than 2V).
When a bit is reset, it is a logic "0" (less than 0.8V).
Four general-purpose inputs, IN3-INo, are provided.
The 0 register provides 4 general-purpose outputs and is
used as the destination register for the 4-bit contents of Bd.
The 0 outputs can be directly connected to the digits of a
multiplexed LED display.
The G register contents are outputs to 4 general-purpose
bidirectional I/O ports. G I/O ports can be directly connected to the digits of a multiplexed LED display.
PROGRAM MEMORY
Program Memory consists of a 1,024 byte ROM. As can be
seen by an examination of the COP420Ll421L instruction
set, these words may be program instructions, program data
or ROM addressing data. Because of the special characteristics associated with the JP, JSRP, JID and LaiD instructions, ROM must often be thought of as being organized into
16 pages of 64 words each.
ROM addressing is accomplished by a 10-bit PC register. Its
binary value selects one of the 1,024 8-bit words contained
in ROM. A new address is loaded into the PC register during
each instruction cycle. Unless the instruction is a transfer of
control instruction, the PC register is loaded with the next
sequential 1O-bit binary count value. Three levels of subroutine nesting are implemented by the 10-bit subroutine save
registers, SA, SB and SC, providing a last-in, first-out (LIFO)
hardware subroutine stack.
The a register is an internal, latched, 8-bit register, used to
hold data loaded to or from M and A, as well as 8-bit data
from ROM. Its contents are outputted to the L I/O ports
when the L drivers are enabled under program control. (See
LEI instruction.)
The 8 L drivers, when enabled, output the contents of
latched a data to the L I/O ports. Also, the contents of L
may be read directly into A and M. L I/O ports can be directly connected to the segments of a multiplexed LED display
(using the LED Direct Drive output configuration option) with
a data being outputted to the Sa-Sg and decimal point
segments of the display.
The SIO register functions as a 4-bit serial-in/serial-out shift
register or as a binary counter depending on the contents of
the EN register. (See EN register description, below.) Its
contents can be exchanged with A, allowing it to input or
output a continuous serial data stream. SIO may also be
used to provide additional parallel I/O by connecting SO to
external serial-in/parallel-out shift registers. For example of
additional parallel output capacity see Application # 2.
ROM instruction words are fetched, decoded and executed
by the Instruction Decode, Control and Skip Logic circuitry.
DATA MEMORY
Data memory consists of a 256-bit RAM, organized as 4
data registers of 16 4-bit digits. RAM addressing is implemented by a 6-bit B register whose upper 2 bits (Br) select 1
of 4 data registers and lower 4 bits (Bd) select 1 of 16 4-bit
digits in the selected data register. While the 4-bit contents
of the selected RAM digit (M) is usually loaded into or from,
or exchanged with, the A register (accumulator), it may also
be loaded into or from the a latches or loaded from the L
ports. RAM addressing may also be performed directly by
the LDD and XAD instructions is based upon the 6-bit contents of the operand field of these instructions. The Bd register also serves as a source register for 4-bit data sent
directly to the 0 outputs.
The XAS instruction copies C into the SKL latch. In the
counter mode, SK is the output of SKL; in the shift register
mode, SK outputs SKL ANDed with the clock.
The EN register is an internal 4-bit register loaded under
program control by the LEI instruction. The state of each bit
of this register selects or deselects the particular feature
associated with each bit of the EN register (EN3-ENo).
1. The least significant bit of the enable register, ENo, selects the SIO register as either a 4-bit shift register or a 4bit binary counter. With ENo set, SIO is an asynchronous
binary counter, decrementing its value by one upon each
low-going pulse ("1" to "0") occurring on the SI input.
Each pulse must be at least two instruction cycles wide.
SK outputs the value of SKL. The SO output is equal to
the value of EN3. With ENo reset, SIO is a serial shift
register shifting left each instruction cycle time. The data
present at SI goes into the least significant bit of SIO. SO
can be enabled to output the most significant bit of SIO
each cycle time. (See 4 below.) The SK output becomes
a logic-controlled clock.
INTERNAL LOGIC
The 4-bit A register (accumulator) is the source and destination register for most I/O, arithmetic, logic and data memory
access operations. It can also be used to load the Br and Bd
portions of the B register, to load and input 4 bits of the 8-bit
Q latch data, to input 4 bits of the 8-bit L I/O port data and
to perform data exchanges with the SIO register.
A 4-bit adder performs the arithmetic and logic functions of
the COP420/421 L, storing its results in A. It also outputs a
carry bit to the 1-bit C register, most often employed to indicate arithmetic overflow. The C register, in conjunctions with
the XAS instruction and the EN register, also serves to control the SK output. C can be outputted directly to SK or
2. With EN1 set the IN1 input is enabled as an interrupt
input. Immediately following an interrupt, EN1 is reset to
disable further interrupts.
3. With EN2 set, the L drivers are enabled to output the
data in a to the L I/O ports. Resetting EN2 disables
1-142
o
Functional Description
o"tJ
(Continued)
the L drivers, placing the L 1/0 ports in a high-impedance
input state.
data each instruction time. Resetting EN3 with the serial
shift register option selected disables SO as the shift
register output; data continues to be shifted through SIO
and can be exchanged with A via an XAS instruction but
SO remains reset to "0". The table below provides a
summary of the modes associated with EN3 and ENo.
4. EN3, in conjunction with ENo, affects the SO output. With
ENo set (binary counter option selected) SO will output
the value loaded into EN3. With ENo reset (serial shift
register option selected), setting EN3 enables SO as the
output of the SIO shift register, outputting serial shifted
.;..
I\,)
o
r.......
o
o"tJ
.;..
....
rI\,)
.......
o
Enable Register Modes-Bits EN3 and ENo
EN3
ENo
SIO
SI
SO
0
0
Shift Register
Input to Shift Register
0
1
0
Shift Register
Input to Shift Register
Serial Out
0
1
Binary Counter
Input to Binary Counter
0
1
1
Binary Counter
Input to Binary Counter
1
o"tJ
SK
.;..
= 1, SK = Clock
= 0, SK = 0
If SKL = 1, SK = Clock
If SKL = 0, SK = 0
If SKL = 1, SK = 1
If SKL = 0, SK = 0
If SKL = 1, SK = 1
If SKL = 0, SK = 0
If SKL
If SKL
I\,)
I\,)
r.......
o
o"tJ
W
I\,)
o
r.......
o
o"tJ
W
....
I\,)
INTERRUPT
nested within the interrupt servicing routine since their
popping the stack will enable any previously saved main
program skips, interfering with the orderly execution of
the interrupt routine.
The following features are associated with the IN1 interrupt
procedure and protocol and must be considered by the programmer when utilizing interrupts.
d. The first instruction of the interrupt routine at hex address OFF must be a NOP.
e. A LEI instruction can be put immediately before the RET
to re-enable interrupts.
a. The interrupt, once aknowledged as explained below,
pushes the next sequential program counter address (PC
+ 1) onto the stack, pushing in turn the contents of the
other subroutine-save registers to the next lower level
(PC + 1 -+ SA -+ SB -+ SC). Any previous contents of SC are lost. The program counter is set to hex
address OFF (the last word of page 3) and EN1 is reset.
INITIALIZATION
The Reset Logic will initialize (clear) the device upon powerup if the power supply rise time is less than 1 ms and greater than 1 ,."s. If the power supply rise time is greater than
1 ms, the user must provide an external RC network and
diode to the RESET pin as shown below. The RESET pin is
configured as a Schmitt trigger input. If not used it should be
connected to Vee. Initialization will occur whenever a logic
"0" is applied to the RESET input, provided it stays low for
at least three instruction cycle times.
b. An interrupt will be acknowledged only after the following
conditions are met:
1. EN1 has been set.
2. A low-going pulse ("1" to "0") at least two instruction
cycles wide occurs on the IN1 input.
3. A currently executing instruction has been completed.
4. All successive transfer of control instructions and successive LBls have been completed (e.g., if the main
program is executing a JP instruction which transfers
program control to another JP instruction, the interrupt
will not be acknowledged until the second JP instruction has been executed).
Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, D, EN, and G registers are cleared.
The SK output is enabled as a SYNC output, providing a
pulse each instruction cycle time. Data Memory (RAM) is
not cleared upon initialization. The first instruction at address 0 must be a CLRA.
c. Upon acknowledgement of an interrupt, the skip logic
status is saved and later restored upon popping of the
stack. For example if an interrupt occurs during the execution of A5C (Add with Carry, Skip on Carry) instruction
which results in carry, the skip logic status is saved and
program control is transferred to the interrupt servicing
routine at address OFF. At the end of the interrupt routine, a RET instruction is executed to "pop" the stack
and return program control to the instruction following
the original ASC. At this time, the skip logic is enabled
and skips this instruction because of the previous ASC
carry. Subroutines and LQID instructions should not be
Power-Up Clear Circuit
TL/DD/6625-7
RC
1-143
~
5 x Power Supply Rise Time
C
o
o"tJ
W
I\,)
I\,)
I"""
...J
N
N
C")
D..
Functional Description
(Continued)
o
OSCILLATOR
...J
There are three basic clock oscillator configurations available as shown by Figure 4.
o.......
-N
C")
D..
o
o
.......
...J
o
N
C")
D..
oo
.......
...J
N
N
CKO PIN OPTIONS
In a crystal controlled oscillator system, CKO is used as an
output to the crystal network. As an option CKO can be a
general purpose input, read into bit 2 of A (accumulator)
upon execution of an INIL instruction. As another option,
CKO can be a RAM power supply pin (VR), allowing its connection to a standby/backup power supply to maintain the
integrity of RAM data with minimum power drain when the
main supply is inoperative or shut down to conserve power.
Using either option is appropriate in applications where the
COP420L/421 L system timing configuration does not require use of the CKO pin.
a. Crystal Controlled Oscillator. CKI and CKO are connected to an external crystal. The instruction cycle time
equals the crystal frequency divided by 32 (optional by
16 or 8) .
b. External Oscillator. CKI is an external clock input signal. The external frequency is divided by 32 (optional by
16 or 8) to give the instruction cycle time. CKO is now
available to be used as the RAM power supply (VR) or as
a general purpose input.
RAM KEEP-ALIVE OPTION (Not available on COP422L)
c. RC Controlled Oscillator. CKI is configured as a single
pin RC controlled Schmitt trigger oscillator. The instruction cycle equals the oscillation frequency divided by 4.
CKO is available as the RAM power supply (VR) or as a
general purpose input.
D..
Selecting CKO as the RAM power supply (VR) allows the
user to shut off the chip power supply (Vee> and maintain
data in the RAM. To insure that RAM data integrity is maintained, the following conditions must be met:
1. RESET must go low before Vee goes below spec during
power-off; Vee must be within spec before RESET goes
high on power-up.
...J
.......
2. During normal operation VR must be within the operating
range of the chip, with (Vee - 1) ::;; VR ::;; Vee.
N
o
3. VR must be ~ 3.3V with Vee off.
~
D..
oo
.......
--
...J
N
~
oo
~
D..
o
Crystal Oscillator
o
CKI
CKO
R2
....
AAA
U
t
JL..r
CKI
CKO
t
t
VCC
(VR OR GENERAL
PURPOSE INPUT
PIN)
EXTERNAL
CLOCK
TL/DD/BB2S-B
RC Controlled Oscillator
Crystal
Value
R1 (0)
R2 (0)
C1 (pF)
C2 (pF)
455 kHz
2.097 MHz
4.7k
1k
1M
1M
220
30
220
6-36
Component Values
R(kO)
C (pF)
Instruction
Cycle Time
(,...s)
51
100
56
19 ± 15%
19 ± 13%
82
Note: 200k
~
360 pF
R
~
25k
~
C
~
FIGURE 4. COP420L/421L Oscillator
1-144
50 pF
o
Functional Description
o-a
(Continued)
~
~
I/O OPTIONS
COP420Ll421 L outputs have the following optional configurations, illustrated in Figure 5:
The above input and output configurations share common
enhancement-mode and depletion-mode devices. Specifically, all configurations use one or more of six devices
(numbered 1-6, respectively). Minimum and maximum current (lOUT and VOUT) curves are given in Figure 6 for each
of these devices to allow the designer to effectively use
these I/O configurations in designing a COP420Ll421 L system.
The SO, SK outputs can be configured as shown in a., b., or
c_ The D and G outputs can be configured as shown in a. or
b. Note that when inputting data to the G ports, the G outputs should be set to "1". The L outputs can be configured
as in d., e., f. or g.
An important point to remember if using configuration d. or
f. with the L drivers is that even when the L drivers are
disabled, the depletion load device will source a small
amount of current (see Figure 6, device 2); however, when
the L lines are used as inputs, the disabled depletion device
cannot be relied on to source sufficient current to pull an
input to a logic 1.
a. Standard-an enhancement mode device to ground in
conjunction with a depletion-mode device to Vee, compatible with LSTIL and CMOS input requirements. Available on SO, SK, and all D and G outputs.
b. Open-Draln-an enhancement-mode device to ground
only, allowing external pull-up as required by the user's
application. Available on SO, SK, and all D and G outputs.
c. Push-Pull-An enhancement-mode device to ground in
conjunction with a depletion-mode device paralleled by
an enhancement-mode device to Vee. This configuration
has been provided to allow for fast rise and fall times
when driving capacitive loads. Available on SO and SK
outputs only.
d. Standard L-same as a., but may be disabled. Available
on L outputs only.
e. Open Drain L-same as b., but may be disabled. Available on L outputs only.
.
COP421L
If the COP420L is bonded as a 24-pin device, it becomes
the COP421 L, illustrated in Figure 2, COP420L/421 L Connection Diagrams. Note that the COP421 L does not contain
the four general purpose IN inputs (IN3-INo). Use of this
option precludes, of course, use of the IN options and the
interrupt feature. All other options are available for the
COP421L.
f. LED Direct Drive-an enhancement-mode device to
ground and to Vee, meeting the typical current sourcing
requirements of the segments of an LED display. The
sourcing device is clamped to limit current flow. These
devices may be turned off under program control (see
Functional Description, EN Register), placing the outputs
in a high-impedance state to provide required LED segment blanking for a multiplexed display. Available on L
outputs only.
g. TRI-STATE Push-Pull-an enhancement-mode device
to ground and Vee. These outputs are TRI-STATE outputs, allowing for connection of these outputs to a data
bus shared by other bus drivers. Available on L outputs
only.
COP422L
If the COP421 L is bonded as a 20-pin device, it becomes
the COP422L, as illustrated in Figure 2. Note that the
COP422L contains all the COP421 L pins except Do, D1, Go,
and G1. COP422L also does not allow RAM power supply
input as a valid CKO pin option.
COP420LlCOP421 L inputs have the following optional configurations:
h. An on-chip depletion load device to Vee.
A Hi-Z input which must be driven to a "1" or "0" by
external components.
TL/DD/BB2S-10
TL/DD/B62S-9
a. Standard Output
TL/DD/BB2S-11
b. Open-Drain Output
1-145
c. Push-Pull Output
o
r
........
o
o-a
~
~
....
r
........
o
o-a
~
~
~
r-
........
o
o-a
(,,)
~
o
r
........
o
o-a
(,,)
....r
~
........
o
o-a
(,,)
~
~
r
.....
N
N
~
a.
Functional Description
(Continued)
o(,)
......
.....
,...
·
N
~
.~ILE~i
a.
o
(,)
::J
o
TL/DD/8825-13
N
~
a.
TL/DD/8825-12
o
(,)
TL/DD/8825-14
......
.....
N
(A Is Depletion Device)
d. Standard L Output
f. LED (L Output)
e. Open-Drain L Output
N
"III:t
a.
o
(,)
VCC
"~TAf
......
.....
,...
N
"III:t
a.
o
(,)
......
.....
o
TLlDD/8825-15
g. TRI-STATE Push-Pull (L Output)
N
"III:t
a.
o(,)
'NP~~{
TL/DD/8825-17
TLlDD/8825-16
h. Input with Load
FIGURE 5. Output Configurations
I. HI-Z Input
Typical Performance Characteristics
-100
Input Current for Lo-L7 when
Output Programmed OFF
by Software
DEVICE d.,Z
AND' .. Z-
-90
,
-10
-1&0
j
...
0
~
:::>
-60
'\
-50
MIN1Ver
o
o
•. 5
,
1'\
-ti--~
-100
1""-1--_
~~
1.
5
..... F==: I=l1o.
VOH (VOLTS)
,
1.5 r-'rr-1r-T1--,--,r-r-':"""'T--r--,
Vec9.5V
IMIN~~
1.0
vV
-9.5V
IMAX@
.J
0.5
IMIN@
1
2 3
4
5 6 7 B 9 10
DEVICE c#2
VOH (VOLTS)
AND #3
1.0 f-H-i-t--+-++
l
.J
~Ci4.5V
0.5
o
o
1
•. 5
\ 1I'OO@
l
0.5
-
Source Current for Lo-L7 In
TRI-STATE Configuration
(Low Current Option)
Source Current for Lo-L7 In
TRI-STATE Configuration
(High Current Option)
1.5
l\
1/~~'B.5 ~
"f;..... Ls::
01234567'
2.0
VIIO (VOLTS)
Source Current for SO and
SK In Push-Pull Configuration
I-IH~H--+-++-=+t-t--+-i
"\ IMAX .Vcc· 9.5 V
I'\,;
'MAX·
.... 00 scc. UV
i
-300
K'MiN
vcc' .5VI
-200
1.0
VIN (VOLTS)
1.0
"-
...........
~.9.5
-10
"\
-600
E -500
Vee- UV
-zo
DEVICE. #2
ANf d #2
,
-700
j
r\.
IMAX~
-30
\.
-100
"
.... 0
0
1.0 2.0 3.0 4.0 5.0 8.0 7.0 •.0
-900
' - IMAX @ Vec - 9.5V
-70
j
Source Current for Standard
Configuration
-1000 Output
l1lT 1 \
2 3
1--1-II~F-+--+-tI--+....r-+--i
5
4
5 6 7
VOH (VOLTS)
DEVICE
11#5
B II 10
o
1
2 3 4 5 6 7 8 9 10
VOH (VOLTS)
TL/DD/8825-18
1-146
C")
Typical Performance Characteristics
o"D
(Continued)
LED Output Direct Segment
and Digit Drive (High Current
Options on Lo-L7; Very High
Current Options on 00-03 or
Go-G3)
LED Output Source Current
-20 (High Current LED Option)
-50
DEVICE' d ANO .4
OEviCE. OR •• 1
A~O
.... 0
I~AX
~
-30
~
-20
........
.~
OL-~~~~~~~~~
o
I
2 .1
5 6 7 8
"
I
9 10
2 .1
4 5 6 7 8
0I:loo
~
...6
r........
0I:loo
~
~
"",
KAXEIGHT
SEGMENTS ONIMIN
1
9 10
1
C
C")
o"D
W
10
~
c
r-
VCC IVOLTSI
VOH(VOLTS)
VOH(VOLTS)
C")
o"D
o"D
V
~
..... ......
:::: ...... •
-10
~
r........
C")
ONE SEGMENTS........... ~
C
.!
0I:loo
C
........
C")
o"D
W
~
...6
r........
LED Output Direct
Segment Drive
-51
VOH· 2.0 V
4~-nr-~~~r-~r-~
OEVICE'
dANO .4
.
g
-30
C")
o"D
W
~
~
r-
DEVICE .... 1
b ... 1 AND c ... 1
.....
C
.!
Output Sink Current for Lo-L7
and Standard Drive Option
for 00-03 and GO-G3
Output Sink Current for
SO and SK
!.§
-20
-10
.'
•
•
10
4
VCC IVOLTS!
Output Sink Current for
GO-G3 and 00-03 with Very
High Current Option
100
VOL (VOLTS,
VOL (VOLTS)
Output Sink Current for
GO-G3 and 00-03
(High Current Option)
H-I-+
£' -40
o
o.......
-20
..J
'"
"'I:t'
'"
15
05
a..
VI/O (VOLTS)
VIN (VOLTS)
o
o
.......
Source Current for SO and
SK In Push-Pull Configuration
..J
.....
VOH (VOlTS)
Source Current for Lo-L71n
TRI-STATE Configuration
(High Current Option)
,
I.S
'"
a..
Source Current for Lo-L7In
TRI·STATE Configuration
(LOW Current Option)
DEVICE U#S
1. 5
r-----r....,,........,rT""...........,,,DE""V""IC::-E-g.,,.#~5
"'I:t'
o
o
.......
..J
o
"'I:t'
'"
a..
o
o
1.0 ~-H-+-1I-+--++--t--+--I
1.0
1.0
C
!
!.
z:
IMIN@
IMIN@
VCC=4.5V VCC=7.5V
z:
oS
oS
O.S I - -
0.5
o
HI I I
IMAX @
~"i\51 T(i"
o
3
LED Output Source Current
(Low Current LED Option)
o ~~~--~~~~-~~
3
4
VOH (VOLTS)
Output Sink Current for
SO and SK
40
'\.
'\..
14
'\..
'\.
36
I'\.
'\.
I
~
'\..
~
'\..
32
'\.
'\.
'\..
10
o
0.5
o
4
LED Output Source Current
(High Current LED Option)
18
12
-
VOH (VOLTS)
VOH (VOLTS)
16
IMAX @
"-
"
f'I{
!wAx@Vcc =7.5V
28
IWAX@Vcc =6.0V
24
1v.. @Vcc =7.5V
20
1.... @VCC =6.0V
16
.....
12
......
I'\..
'\..
.... ["00,.
.....
'\..
1"IN@Vcc =6.0V
"
4
o
o
!wAx@Vcc = 6.0V
IwIN@Vcc =7.5V
'\..
'\..
I'\..
!wAx@Vcc =7.5V
'\..
'\..
7
"""""
o
8
VOLIVOLTS)
VOH (VOLTS)
VOH (VOLTS)
Output Sink Current for
GO-G3 and 00-03 with Very
High Current Option
Output Sink Current for Lo-L7
and Standard Drive Option
for 00-03 and GO-G3
120 r--rT""I....,.-...-:-=,."."..-----.
Output Sink Current for
GO-G3 and 00-03
(High Current Option)
120'r-.....,....,..,..--r__r--,---r___...-.,
100
80
!
60
I-H+-+--¥
oS
20
VOL (VOLTS)
Vall VOLTS)
FIGURE 7. COP320L/DOP321L/COP322L Input/Output Characteristics
1-148
Val (VOLTS) TL/DD/8825-20
o
o""C
COP420L/COP421 L Instruction Set
Table I is a symbol table providing internal architecture, instruction operand and operational symbols used in the instruction set table.
Table II provides the mnemonic, operand, machine code,
data flow, skip conditions and description associated with
each instruction in the COP41 0L/411 L instruction set.
~
N
o
r.......
o
o""C
~
TABLE I. COP420L/421L Instruction Set Table Symbols
Symbol
Definition
Symbol
Definition
N
......
r.......
o
INTERNAL ARCHITECTURE SYMBOLS
INSTRUCTION OPERAND SYMBOLS
o""C
A
B
8r
8d
C
d
N
N
o
EN
G
IL
IN
L
M
PC
Q
SA
S8
SC
SIO
SK
4-bit Accumulator
6-bit RAM Address Register
Upper 2 bits of 8 (register address)
Lower 4 bits of 8 (digit address)
1-bit Carry Register
4-bit Data Output Port
4-bit Enable Register
4-bit Register to latch data for G I/O Port
Two 1-bit Latches associated with the IN3 or
INo inputs
4-bit Input Port
8-bit TRI-STATE I/O Port
4-bit contents of RAM Memory pointed to by 8
Register
1O-bit ROM Address Register (program counter)
8-bit Register to latch data for L I/O Port
1O-bit Subroutine Save Register A
1O-bit Subroutine Save Register 8
1O-bit Subroutine Save Register C
4-bit Shift Register and Counter
Logic-Controlled Clock Output
4-bit Operand Field, 0-15 binary (RAM Digit Select)
2-bit Operand Field, 0-3 binary (RAM Register
Select)
a
1O-bit Operand Field, 0-1023 binary (ROM Address)
y
4-bit Operand Field, 0-15 binary (Immediate Data)
RAM(s) Contents of RAM location addressed by s
ROM(t) Contents of ROM location addressed by t
~
r.......
o
o""C
W
N
o
r.......
o
o""C
OPERATIONAL SYMBOLS
+
---+
~
A
E9
Plus
Minus
Replaces
Is exchanged with
Is equal to
The ones complement of A
Exclusive-OR
Range of values
W
N
......
r.......
o
o""C
W
N
N
r-
III
1-149
..J
N
N
Cf)
a..
Instruction Set (Continued)
o
TABLE II. COP420L/421L Instruction Set
o
..J
'"
....
N
Cf)
a..
oo
'"
o
..J
Machine
Hex
Mnemonic Operand Code Language Code
(Binary)
DataFlow
Skip Conditions
Description
ARITHMETIC INSTRUCTIONS
ASC
30
10011100001
A + C + RAM(8) -+ A
Carry -+ C
Carry
Add with Carry, Skip on
Carry
ADD
31
1001110001
A + RAM(8) -+ A
None
Add RAMtoA
ADT
4A
1010011010 I
A + 1010 -+ A
None
Add Ten to A
5-
10101
A+y-+A
Carry
Add Immediate, Skip on
Carry(y'* 0)
CASC
10
10001100001
A + RAM(8) + C -+ A
Carry -+ C
Carry
Compliment and Add with
Carry, Skip on Carry
N
Cf)
a..
o
o
::=i
N
I
N
~
a..
o
o
::=i
....
N
AISC
y
I
Y..
I
~
a..
o
o
::=i
o
CLRA
00
10000100001
O-+A
None
Clear A
COMP
40
10100100001
A-+A
None
Ones complement of A to A
l
o
NOP
44
10100101001
None
None
No Operation
RC
32
10011100101
"0" -+ C
None
ResetC
SC
22
10010100101
"1" -+ C
None
SetC
XOR
02
10000100101
A E9 RAM(8) -+ A
None
Exclusive-OR RAM with A
ROM (PC9:B, A,M) -+
PC7:0
None
Jump Indirect (Note 3)
101101001 a9'a 1 a -+ PC
I a7:0 I
None
Jump
11 I a6:0 1 a -+ PC6:0
(pages 2,3 only)
or
111 I as:o
1 a -+ PC5:0
(all other pages)
None
Jump within Page (Note 4)
--
110 I
1 PC + 1 -+ SA -+
S8 -+ SC
0010 -+ PC9:6
a -+ PCs:o
None
Jump to Subroutine Page
(NoteS)
6-
101101101a9:sl
I a7:0 1
PC + 1 -+ SA -+
S8 -+ SC
a -+ PC
None
Jump to Subroutine
-RET
48
10100110001
SC -+ S8 -+ SA -+ PC None
RETSK
49
10100110011
SC -+ S8 -+ SA -+ PC Always Skip on Return Return from Subroutine
then Skip
N
o
TRANSFER OF CONTROL INSTRUCTIONS
FF
JID
JMP
a
JP
a
6-
----
JSRP
a
JSR
a
11111111111
as:o
1-150
Return from Subroutine
o
o
Instruction Set (Continued)
."
"'r-"
I\)
Q
TABLE II. COP420L/421L Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
.......
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
o
o."
"'r-"
I\)
MEMORY REFERENCE INSTRUCTIONS
-"
CAMO
33
3C
10011 10011 I
10011111001
A ---+ 07:4
RAM (B) ---+ 03:0
None
Copy A, RAM to 0
COMA
33
2C
10011100111
10010111001
07:4 ---+ RAM (B)
None
Copy Q to RAM, A
LD
LDD
r
r,d
LOID
-5
03:0 ---+ A
--
10010100111
1001 r 1 d 1
RAM(r,d) ---+ A
None
BF
11011 11111 1
ROM(PC9:B,A,M) ---+ 0
SB ---+ SC
None
Load Q Indirect (Note 3)
RAM(B)o
RAM(B)1
RAM(B)2
RAM(Bb
None
Reset RAM Bit
Load RAM into A,
Exclusive-OR Br with r
Load A with RAM pOinted
to directly by r,d
0
1
2
3
4C
45
42
43
10100111001
1010010101 I
10100100101
10100100111
o ---+
o ---+
o ---+
o ---+
5MB
0
1
2
3
40
47
46
4B
10100111011
10100111011
10100101101
10100110111
1
1
1
1
RAM(B)o
RAM(Bh
RAM(B)2
RAM(Bb
None
Set RAM Bit
STII
y
7-
10111 1 y
y ---+ RAM (B)
Bd + 1 ---+ Bd
None
Store Memory Immediate
and Increment Bd
X
r
-6
100 Irl 0110 1
RAM (B) ~ A
Br Ell r ---+ Br
None
Exchange RAM with A,
Exclusive-OR Br with r
XAD
r,d
23
10010100111
110 1 r I d 1
RAM(r,d)
None
--
Exchange A with RAM
pointed to directly by (r,d)
RMB
I
---+
---+
---+
---+
"'r-"
I\)
I\)
o
None
23
o
o."
.......
RAM (B) ---+ A
Br Ell r ---+ Br
100lrl01011
.......
~
W
I\)
Q
r.......
o
o."
W
I\)
-"
C
o
o
."
W
I\)
I\)
r-
A
XDS
r
-7
100 1r I0111 1
RAM (B) ~ A
Bd - 1 ---+ Bd
Br Ell r ---+ Br
Bd decrements past 0
Exchange RAM with A
and Decrement Bd,
Exclusive-OR Br with r
XIS
r
-4
100 1r I0100 1
RAM (B) ~ A
Bd + 1 ---+ Bd
Br Ell r ---+ Br
Bd increments past 15
Exchange RAM with A
and Increment Bd,
Exclusive-OR Br with r
1-151
o."
...I
C\I
C\I
C")
a..
Instruction Set (Continued)
o
TABLE II. COP420L/421L Instruction Set (Continued)
o
......
...I
.....
C\I
Mnemonic Operand
C")
Hex
Code
a..
o
o
......
Machine
Language Code
(Binary)
DataFlow
Skip Conditions
Description
REGISTER REFERENCE INSTRUCTIONS
CAB
50
10101100001
A ---+ Bd
None
Copy A to Bd
a..
CBA
4E
1010011110 1
Bd ---+ A
None
CopyBd toA
o......
LBI
--
100Irl(d-1)1
(d=0,9:15)
or
r,d ---+ B
Skip until not an LBI
Load B Immediate with
r,d (Note 6)
33
--
10011100111
110 1 r 1 d 1
(any d)
33
6-
10011100111
10110 1 'i 1
y ---+ EN
None
Load EN Immediate (Note 7)
12
10001100101
A ~ Br (0,0 ---+ A3.A2)
None
Exchange A with Br
SKC
20
10010100001
C = "1"
Skip if C is True
SKE
21
10010100011
A = RAM(B)
Skip if A Equals RAM
SKGZ
33
21
10011100111
10010100011
G3:0 = 0
Skip if G is Zero
(all 4 bits)
0
1
2
3
33
01
11
03
13
10011100111
10000100011
10001100011
10000100111
10001100111
0
1
2
3
01
11
03
13
10000100011
10001100011
10000100111
10001100111
RAM(B)o
RAM(B)1
RAM(B)2
RAM(B)a
41
10100100011
A time-base counter Skip on Timer (Note 3)
carry has occurred
since last test
...I
o
C\I
C")
o
r,d
...I
C\I
C\I
~
a..
o
o
......
...I
.....
C\I
~
a..
LEI
y
o
o
......
...I
o
C\I
~
a..
o
o
XABR
TEST INSTRUCTIONS
SKGBZ
SKMBZ
SKT
Skip if G Bit is Zero
1st byte
Go
G1
G2
G3
} 2nd byte
1-152
=
=
=
=
0
0
0
0
=
=
=
=
0
0
0
0
Skip if RAM Bit is Zero
o
o"'1J
Instruction Set (Continued)
01:1-
TABLE II. COP420L/421L Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
N
o
r.......
Description
01:1-
INPUTIOUTPUT INSTRUCTIONS
N
......
33
2A
10011 10011 1
10010110101
G~A
33
28
10011 10011 1
10010110001
IN
33
29
10011100111
10010110011
IL3, CKO, "0", ILa
33
2E
10011100111
10010111101
L7:4 ~ RAM(B)
L3:a ~ A
33
3E
10011
10011
Bd
33
5-
10011100111
10101 1 y 1
y~G
OMG
33
3A
10011100111
10011110101
RAM(B)
XAS
4F
1010011111 1
A
ING
o
o"'1J
None
Input G Ports to A
r.......
o
o
"'1J
ININ
INIL
INL
OBD
OGI
y
10011 1
11110 1
~
A
None
Input IN Inputs to A (Note 2)
01:1-
N
N
r.......
~
~
A
None
None
o
Input IL Latches to A
(Note 3)
o"'1J
Input L Ports to RAM, A
o
r.......
W
N
o
o
D
None
Output Bd to D Outputs
"'1J
w
N
......
r.......
~
~
G
SIO,C
~
SKL
None
Output to G Ports Immediate
None
Output RAM to G Ports
None
Exchange A with SID
(Note 3)
o
o"'1J
W
N
N
r-
Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to N where
o signifies the least significant bit (low-order, right-most bit). For example, A3 indicates the most significant (left-most) bit of the 4-bit A register.
Note 2: The ININ instruction is only available on the 26-pin COP420L as the other devices do not contain the IN inputs.
Note 3: For additional information on the operation of the XAS, JID, LQID, INIL, and SKT instructions, see below.
Note 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction,
otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Note 5: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of Pl. A JSRP may not be used when in pages 2 or 3. JSRP
may not jump to the last word in page 2.
Note 6: LBI is a single-by1e instruction if d = 0,9,10,11,12,13,14, or 15. The machine code for the lower 4 bits equals the binary value of the "d'" data minus 1,
e.g., to load the lower four bits of B (Bd) with the value 9 (10012), the lower 4 bits of the LBI instruction equal 6 (10002)' To load 0, the lower 4 bits of the LBI
instruction should equal 15 (11112)'
Note 7: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a "1" or "0" in each bit of EN corresponds
with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
Description of Selected
Instructions
The following information is provided to assist the user in
understanding the operation of several unique instructions
and to provide notes useful to programmers in writing
COP420L/421 L programs.
SID is selected as a shift register, an XAS instruction must
be performed once every 4 instruction cycles to effect a
continuous data stream.
XAS INSTRUCTION
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location pointed
to indirectly by A and M. It loads the lower 8 bits of the ROM
address register PC with the contents of ROM addressed by
the 1O-bit word, PC9:8, A, M. PCg and PCa are not affected
by this instruction.
JID INSTRUCTION
XAS (Exchange A with SID) exchanges the 4-bit contents of
the accumulator with the 4-bit contents of the SID register.
The contents of SID will contain serial-in/serial-out shift register or binary counter data, depending on the value of the
EN register. An XAS instruction will also affect the SK output. (See Functional Description, EN Register, above.) If
Note that JID requires 2 instruction cycles to execute.
1-153
•
-J
N
N
C")
a.
o
o
::J
~
N
Cf)
a.
o
o
'-J
o
N
C")
a.
o
o
::J
N
N
~
a.
o
o
'-J
~
N
r---------------------------------------------------------------------------------------~
Description of Selected
Instructions (Continued)
SKT INSTRUCTION
The SKT (Skip On Timer) instruction tests the state of an
internal 10-bit time-base counter. This counter divides the
instruction cycle clock frequency by 1024 and provides a
latched indication of counter overflow. The SKT instruction
tests this latch, executing the next program instruction if the
latch is not set. If the latch has been set since the previous
test, the next program instruction is skipped and the latch is
reset. The features associated with this instruction, therefore, allow the COP420Ll421 L to generate its own timebase for real-time processing rather than relying on an external input signal.
For example, using a 2.097 MHz crystal as the time-base to
the clock generator, the instruction cycle clock frequency
will be 65 kHz (crystal frequency + 32) and the binary counter output pulse frequency will be 64 Hz. For time-of-day or
similar real-time processing, the SKT instruction can call a
routine which increments a "seconds" counter every 64
ticks.
INIL INSTRUCTION
INIL (Input IL Latches to A) inputs 2 latches, IL3 and ILo (see
Figure 8) and CKO into A. The IL3 and ILo latches are set if
a low-going pulse ("1" to "0") has occurred on the IN3 and
INa inputs since the last INIL instruction, provided the input
pulse stays low for at least two instruction times. Execution
of an INIL inputs IL3 and ILo into A3 and AO respectively,
and resets these latches to allow them to respond to subsequent low-going pulses on the IN3 and INa lines. If CKO is
mask programmed as a general purpose input, an INIL will
input the state of CKO into A2. If CKO has not been so
programmed, a "1" will be placed in A2. A "0" is always
placed in A 1 upon the execution of an INIL. The general
purpose inputs IN3-INa are input to A upon execution of an
ININ instruction. (See Table II, ININ instruction.) INIL is useful in recognizing pulses of short duration or pulses which
occur too often to be read conveniently by an ININ instruction. IL latches are not cleared on reset.
~
a.
LQID INSTRUCTION
o
LQID (Load Q Indirect) loads the 8-bit Q register with the
contents of ROM pointed to by the 1O-bit word PCg, PCa, A,
M. LQID can be used for table lookup or code conversion
such as BCD to seven-segment. The LQID instruction
"pushes" the stack (PC + 1 ----+ SA ----+ SB ----+ SC) and
replaces the least significant 8 bits of PC as follows: A ----+
PC7:4, RAM (B) ----+ PC3:a, leaving PCg and PCa unchanged. The ROM data pointed to by the new address is
fetched and loaded into the Q latches. Next, the stack is
"popped" (SC ----+ S8 ----+ SA ----+ PC), restoring the
saved value of PC to continue sequential program execution. Since LQID pushes SB ----+ SC, the previous contents
of SC are lost. Also, when LQID pops the stack, the previously pushed contents of SB are left in SC. The net result is
that the contents of SB are placed in SC (SB ----+ SC). Note
the LQID takes two instruction cycle times to execute.
o
'-J
o
N
~
a.
o
o
INSTRUCTION SET NOTES
a. The first word of a COP420Ll421 L program (ROM address 0) must be a CLRA (Clear A) instruction.
b. Although skipped instructions are not executed, one instruction cycle time is devoted to skipping each byte of
the skipped instruction. Thus all program paths except
JID and LQID take the same number of cycle times
whether instructions are skipped or executed. JID and
LQID instructions take 2 cycles if executed and 1 cycle if
skipped.
c. The ROM is organized into 16 pages of 64 words each.
The Program Counter is a 10-bit binary counter, and will
count through page boundaries. If a JP, JSRP, JID or
LQID instruction is located in the last word of a page, the
instruction operates as if it were in the next page. For
example: a JP located in the last word of a page will jump
to a location in the next page. Also, a LQID or JID located
in the last word of page 3, 7, 11, or 15 will access data in
the next group of four pages.
COP420l/421l
ININ
1.
INoIIN 3
INll
TLlDD/8825-21
FIGURE 8. INIL Hardware Implementation
1-154
o
o"a
Option List
The COP420L/421 L mask-programmable options are assigned numbers which correspond with the COP420L pins.
The following is a list of COP420L options. When specifying a COP421 L chip, Options 9, 10, 19, and 20 must all be set to zero.
When specifying a COP422L chip, options 9,10, 19, and 20 must all be set to zero; options 21 and 22 may not be set to one,
three or five; and option 2 may not be set to one. The options are programmed at the same time as the ROM pattern to provide
the user with the hardware flexibility to interlace to various 1/0 components using little or no external circuitry.
The Option Table should be copied and sent in with your EPROM or disc.
Option 1 = 0: Ground Pin-no options available
Option 19: INo Input
same as Option 9
Option 2: CKO Output
= 0: clock generator output to crystal/resonator (0 not
Option 20: IN3 Input
same as Option 9
allowable value if Option 3 = 3)
= 1: pin is RAM power supply (VR) input (not available on
Option 21: Go I/O Port
the COP422L)
= 0: very-high current standard output
= 2: general purpose input with load device to Vee
= 1: very-high current open-drain output
= 3: general purpose input, Hi-Z
= 2: high current standard output
Option 3: CKI Input
= 3: high current open-drain output
= 0: oscillator input divided by 32 (2 MHz max.)
= 4: standard LSTTL output (fanout = 1)
= 1: oscillator input divided by 16 (1 MHz max.)
= 5: open-drain LSTTL output (fanout = 1)
= 2: oscillator input divided by 8 (500 kHz max.)
Option 22: G1 I/O Port
= 3: single-pin RC controlled oscillator (-:- 4)
same as Option 21
= 4: Schmitt trigger clock input (-:- 4)
Option 23: G2 I/O Port
Option 4: RESET Input
same as Option 21
= 0: load device to Vee
Option 24: G3 I/O Port
= 1: Hi-Z Input
same as Option 21
Option 5: L7 Driver
Option 25: D3 Output
= 0: Standard output
same as Option 21
= 1: Open-drain output
= 2: High current LED direct segment drive output
Option 26: D2 Output
= 3: High current TRI-STATE push-pull output
same as Option 21
= 4: Low-current LED direct segment drive output
Option 27: D1 Output
= 5: Low-current TRI-STATE push-pull output
same as Option 21
Option 6: La Driver
Option 28: Do Output
same as Option 5
same as Option 21
Option 7: Ls Driver
Option 29: L Input Levels
same as Option 5
= 0: standard TTL input levels ("0" = 0.8V, "1" = 2.0V)
= 1: higher voltage input levels
Option 8: 4 Driver
same as Option 5
("0" = 1.2V, "1" = 3.6V)
Option 9: IN1 Input
= 0: load device to Vee
= 1: Hi-Z input
Option 30: IN Input Levels
same as Option 29
Option 31: G Input Levels
same as Option 29
Option 32: SI Input Levels
same as Option 29
Option 33: RESET Input
= 0: Schmitt trigger input
= 1: standard TTL input levels
= 2: higher voltage input levels
Option 34: CKO Input Levels
(CKO = input; Option 2 = 2,3)
same as Option 29
Option 35: COP Bonding
= 0: COP420L (28-pin device)
= 1: COP421 L (24-pin device)
= 2: 28- and 24-pin versions
= 3: COP422L (20-pin device)
= 4: 28- and 20-pin versions
= 5: 24- and 20-pin versions
= 5: 28-, 24-, and 20-pin versions
Option 36: Internal Initialization Logic
= 0: normal operation
= 1: no internal initialization logic
Option 10: IN2 Input
same as Option 9
Option 11: Vee pin
= 0: Standard Vee
= 1: Optional higher voltage Vee
Option 12: La Driver
same as Option 5
Option 13: L2 Driver
same as Option 5
Option 14: L1 Driver
same as Option 5
Option 15: La Driver
same as Option 5
Option 16: SI Input
same as Option 9
Option 17: SO Driver
= 0: standard output
= 1: open-drain output
= 2: push-pull output
Option 18: SK Driver
same as Option 17
1-155
~
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~
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-"
r......
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~
N
N
r......
o
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w
N
o
r......
o
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w
N
-"
r......
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w
N
N
r-
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N
N
C')
Q.
0
0
........
Option Table
The following EPROM option information is to be sent to
National along with the EPROM.
..J
'9"'"
N
OPTION 1 VALUE
Q.
OPTION 2 VALUE
C')
0
0
OPTION 3 VALUE
..J
OPTION 4 VALUE
........
0
N
C')
Q.
OPTION 5 VALUE
0
OPTION 6 VALUE
........
..J
OPTION 7 VALUE
0
N
N
OPTION 8 VALUE
Q.
OPTION 9 VALUE
~
0
0
OPTION 10 VALUE
..J
OPTION 11 VALUE
........
'9"'"
N
~
OPTION 12 VALUE
0
OPTION 13 VALUE
Q.
0........
OPTION 14 VALUE
0
N
OPTION 15 VALUE
Q.
OPTION 16 VALUE
..J
~
0
0
OPTION 17 VALUE
OPTION 18 VALUE
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
OPTION DATA
OPTION DATA
0
IS: GROUND PIN
OPTION 19 VALUE
IS: CKO OUTPUT
OPTION 20 VALUE
IS: CKIINPUT
OPTION 21 VALUE
IS: RESET INPUT
OPTION 22 VALUE
IS: L7 DRIVER
OPTION 23 VALUE
Ls DRIVER
OPTION 24 VALUE
IS: Ls DRIVER
OPTION 25 VALUE
IS: L4 DRIVER
OPTION 26 VALUE
IS: IN1 INPUT
OPTION 27 VALUE
IS: IN2 INPUT
OPTION 28 VALUE
IS:VCCPIN
OPTION 29 VALUE
IS: L3 DRIVER
OPTION 30 VALUE
IS: L2 DRIVER
OPTION 31 VALUE
IS: L1 DRIVER
OPTION 32 VALUE
IS:
IS: Lo DRIVER
OPTION 33 VALUE
IS:SIINPUT
OPTION 34 VALUE
IS: SO DRIVER
OPTION 35 VALUE
IS: SK DRIVER
OPTION 36 VALUE
The SO output has been configured to provide for standard
test procedures for the customer-programmed COP420L.
With SO forced to logic "1", two test modes are provided,
depending upon the value of SI:
IS: IN3 INPUT
IS: Go 1/0 PORT
IS: G1 1/0 PORT
IS: G2 1/0 PORT
IS: G3 1/0 PORT
IS: 03 OUTPUT
IS: 02 OUTPUT
IS: 01 OUTPUT
IS: Do OUTPUT
IS: L INPUT LEVELS
IS: IN INPUT LEVELS
IS: G INPUT LEVELS
IS: SIINPUT LEVELS
IS: RESET INPUT
IS: CKO INPUT LEVELS
IS: COP BONDING
IS: INTERNAL
INITIALIZATION
LOGIC
3. The IN3-INo inputs are used to input the 4 rows of the
keyboard matrix. Reading the IN lines in conjunction with
the current value of the 0 outputs allows detection, debouncing, and decoding of anyone of the 16 keyswitches.
a. RAM and Internal Logic Test Mode (SI = 1)
=
IS: INo INPUT
2. The 03-00 outputs drive the digits of the multiplexed display directly and scan the columns of the 4 x 4 keyboard
matrix.
TEST MODE (Non-Standard Operation)
b. ROM Test Mode (SI
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
0)
These special test modes should not be employed by the
user; they are intended for manufacturing test only.
Figure 9 shows an interconnect diagram for a COP420L
used as a general controller. Operation of the system is as
follows:
4. CKI is configured as a single-pin oscillator input allowing
system timing to be controlled by a single-pin RC network. CKO is therefore available for use as a VR RAM
power supply pin. RAM data integrity is thereby assured
when the main power supply is shut down (see RAM
Keep-Alive option description).
1. The L7-Lo outputs are configured as LED Direct Drive
outputs, allowing direct connection to the segments of
the display.
5. SI is selected as the input to a binary counter input. With
SIO used as a binary counter, SO and SK can be used as
general purpose outputs.
APPLICATIONS # 1: COP420L General Controller
6. The 4 bidirectional G 1/0 ports (G3-GO) are available for
use as required by the user's application.
1-156
o
o-a
Typical Applications
~
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LO~--~8~SE~G~M~EN~T~--~
~
N
.....
DATA LINES
r......
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GNo
BBBB
GNo
o-a
4·oIGIT
LED DISPLAY
~
N
N
r......
o
o-a
w
N
o
r......
o
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-a
w
N
.....
r......
o
~--~~--~~~~~~~~~~ 4x4
KEYSWITCH
. .__~~~~~~~~~__~....~ MATRIX
SK
SO
2
GENERAL OUTPUTS
TL/DD/882S-22
'SO, 51, sK may also be used for Serial 110
FIGURE 9. COP420L Keyboard/Display Interface
APPLICATION # 2:
Digitally Tuned Radio Controller and Clock
Keyboard Matrix Configuration
GO
G3
STRAP 0
L7
L6
STRAP t
L5
STRAP 2
L4
STRAP 3
L3
STRAP 4
L2
STRAP 5
Lt
STRAP 6
LD
TLIDD/882S-23
1-157
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N
N
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~
Typical Applications (Continued)
D-
O
o
KEYBOARO
:J
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GO-G~
C")
D-
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O
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C")
D-
O
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N
N
~
D-
r~
I
":'
EN3
RST
.~
COP420l
:~
~ Vcc
50Hz
IN3
EN2
ENI
CKI
SOT
-'1
m
DO
COMMON
OISPlAY ENABLE (03)
TIME
DISPLAY ENABLE (02)
~~i~~\N~~ABlUD!l.
ClK DATA
SK
SO
I
OPTIONS
j
DATA
ClK
O
rlD~
:J
ALARM EN
I
BIT 17
'I"'"
~ DATA
~
BIT 19
D-
O
o
......
ClK
..J
ENABLE
o
J
STATION DETECT
o
N
DISPLAY OPTIONS
COP470
MM5450
MM5446
COP472
MM5452
NSM4000A
BIT lB
DS8906
EN
N
BIT 20
500KHz 50Hz VCC
~
D-
J
O
o
J
j
RADIO ON/OFF
AM/FM
BANDSWITCH
MUTE
CPO BIT 16 BIT 15
I
I
50kHz IND
MEM STORE IND
CHARGE PUMP OUTPUT
I.LlM341P-5,'].I
SUPPlY
.J..
TL/DD/8825-24
FIGURE 10. Digital Tuning System Block
Functional Description
keys will recall the previous stored data and transmit it to
the PlL. The Pll will in turn change the radio's receiving
frequency as well as the band if necessary. Memory recall
keys can also turn on the radio.
UP: This key will manually increment receiving frequency.
The first four steps of increment will be for fine tuning a
station, after which will be fast slewing meant for manual
receive frequency changing.
DOWN: Has the same function as UP key except that frequency is decremented.
MEMORY SCAN: This will start the radio scanning through
all ten memories automatically at eight seconds per memory
starting from Memory 1. This will also turn on the radio if it
was off.
MEMORY STORE: Enables the memory store mode which
lasts for three seconds. Depression of any memory key will
store the active frequency and band in that memory and
disable the store mode. Any function key will also disable
the mode to prevent memory data being accidentally destroyed.
HALT: Depression of the HALT key will stop the search and
scan functions at current frequency or memory. HALT also
turns on the radio during off time and recall frequency display in signal display mode.
SEARCH: Activates station searching in the current band.
Search speed is 50 ms per frequency step with wrapping
lOGICl/Os
CKI Input: This input accepts an external 500 kHz signal,
divides it by eight and outputs the quotient at the ClK output as the system clock.
RST Input: Schmitt trigger input to clear device upon initialization.
SOT Input: Interrupt input for station detection. The SOT
signal is generated by the radio's station detector and used
by the COP420l to determine if there is a valid station on
the active frequency. The status of the SOT input is only
relevant during station searching mode. A high on SOT will
temporarily terminate the search mode for eight seconds.
AlM Input: A high on ALM will activate alarm output via
slave device at alarm time. A low on the input will disable
alarm function.
DATA Output: Push-pull output providing serial data to external devices.
ClK Output: Push-pull output providing system clock at
data transmitting time.
50 Hz Input: A normally high input to accept a 50 Hz external time base for real-time calculation.
MOMENTARY KEYS DESCRIPTION
MEM 1-MEM 10: Each memory represents data of a favorite station in a certain band. Depression of one of these
1-158
~--------------------------------------------------------------------------~
Functional Description
0l:Io
around at end of band. An 8-second stop will take place on
reaching a valid station. The HALT key or any function key
will terminate the search. Search direction will normally be
upwards unless the DOWN key has been depressed prior to
the SEARCH key or during the search function in which
case search direction will be downwards.
INDIRECT FEATURES AND OPTIONS
As indicated in Figure 10, there are a few options and indirect features provided via the help of a slave device, namely
the Phase Lock Loop, DS8906N.
DISPLAY OPTIONS
As mentioned above, the COP420L-HSB is MICROWIRE
compatible. Internal circuitry enables it to directly interface
with all of National's serial input MICROWIRE compatible
display drivers whether they are of a direct drive or multiplex
drive format. On Figure 10 is a list of drivers available for the
system. EN 1 and EN2 are optional enable outputs meant for
a dual display system in which EN3 will not be used. By dual
display, it means that one display will be constantly showing
time information and the other showing frequency information. Whereas in conventional single display systems, the
display shows both time and frequency information in a
time-sharing method. The National system provides a timeprioritized display-sharing method. That is, whenever a tuning function is completed, the frequency information will
stay on the display for eight seconds then time display will
take over. This is achieved by using EN3 for the driver's
enable logic.
OFF: Turns off the radio or alarm when active.
AM/FM: Radio band switch.
SLEEP: Activates sleep mode, turns on radio on depression
and off radio at the end of sleep period. Setting of sleep
period is done by depressing the SLEEP and MINUTE key
simultaneously.
ALARM: Enables alarm time setting. Depressing the HOUR
or MINUTE key and ALARM key simultaneously will set the
alarm hour and minute respectively.
HOUR: Sets the hour digits of time-related functions.
MINUTE: Sets the minute digits of time-related functions.
DIODE STRAPS CONNECTIONS
STRAP 0: Controls the on and off of radio. In applications
where a toggle type ON/OFF switch is used, momentary
OFF key can be omitted; connecting the strap will turn on
the radio and vice versa. Must be connected to use momentary OFF key.
STRAP 1,2: Selects the AM IF options.
CONTROL OUTPUTS
Six open collector outputs controlled by the COP420L are
provided from DS8906N, the phase lock loop for controlling
radio switching circuits.
STRAP 3: 12/24-hour clock select.
STRAP 4: 3/5 kHz AM step size select.
STRAP 0
Radio ON
Radio OFF
STRAP 3
12 hour
24 hour
STRAP 4
5 kHz step
3 kHz step
r.......
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~
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~
...I.
r-
.......
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~
~
r-
STRAP 1
STRAP 2
X
X
~
AM/FM: Output for controlling the AM/FM bandswitch. A
high level output indicates FM and a low indicates the AM
band.
MUTE: For muting the audio output when performing any
frequency related function. The output will go high prior to
the frequency change except when doing fine tuning.
AM/FM IF OPTIONS
AM
455 kHz
460 kHz
450 kHz
260 kHz
FM
10.7 MHz
10.75 MHz
10.65 MHz
10.8 MHz
~
o
Radio ON/OFF: A high from this output indicates that the
radio should be switched on and vice versa.
STRAP 5, 6: FM IF offsets select.
Connected
Open
n
o
-a
(Continued)
X
~
X
~
~
STRAPS
STRAP 6
X
X
~
~
X
~
~
ALARM ENABLE: Active high output for turning on the
alarm circuit at alarm time.
50 kHz IND: For driving the 50 kHz indicator in FM band or
the LSB in a 5-digit display. Output is active high.
MEM STORE IND: For driving the memory store mode indicator. Output is active high.
X
TYPICAL IMPLEMENTATION ALTERNATIVES
A full keyboard or any portion of it can be implemented with
various applications for features/functions vs. cost/size.
x = No connection.
,., = Diode inserted.
Figure 11 shows two keyboard configurations with 22-key
and 11-key keyboards for a desk-top/tuner system or autoradio system, respectively.
1-159
III
...I
N
N
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a..
Functional Description (Continued)
o
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......
Desk Top DTR Keyboard
....
...I
Car DTR Keyboard
Go
Go
N
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a..
;¥
MEM
SCAN
MEM
STORE
OOWN
HALT
Cf)
UP
SCAN
o
o
::J
N
5
10
4
9
SLEEP
STRAP 3
(121 24 HOUR SELECT)
3
8
ALARM
STRAP 4
(AM STEP 5k/3k SELECT)
2
7
HOUR
STRAP 5
1
6
MIN
STRAP 6
oo
::J
o
OFF
)~
MEM
SCAN
ONIO FF
DOWN
N
a..
N
"'I::t
AM/FM
STRAP 1
UP
STRAP 2
AM
FM
a..
o
o
::J
....
L5
N
"'I::t
a..
o
o
......
...I
o
l6
22 KEYS
TL/DD/8825-25
N
"'I::t
a..
STRAP 1
~~
5110
STRAP 2
L/9
STRAP 3
(12 124 HOUR SELECT)
3/8
STRAP 4
(A M 5k/3k STEP SELECT)
217
HOUR
STRAP 5
1/6
MIN
STRAP 6
11 KEYS
o
o
AM/FM
TL/DD/8825-26
FIGURE 11
1-160
o
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~National
~
N
D Semiconductor
~
o
......
o
COP424C, COP425C, COP426C, COP324C, COP325C,
COP326C and COP444C, COP445C, COP344C, COP345C
Single-Chip 1k and 2k CMOS Microcontrollers
General Description
Features
The COP424C, COP425C, COP426C, COP444C and
COP445C fully static, Single-Chip CMOS Microcontrollers
are members of the COPSTM family, fabricated using double-poly, silicon gate microCMOS technology. These Controller Oriented Processors are complete microcomputers
containing all system timing, internal logic, ROM, RAM, and
I/O necessary to implement dedicated control functions in a
variety of applications. Features include single supply operation, a variety of output configuration options, with an instruction set, internal architecture and I/O scheme designed to facilitate keyboard input, display output and BCD
data manipulation. The COP424C and COP444C are 28 pin
chips. The COP425C and COP445C are 24-pin versions (4
inputs removed) and COP426C is 20-pin version with 15 I/O
lines. Standard test procedures and reliable high-density
techniques provide the medium to large volume customers
with a customized microcontroller at a low end-product cost.
These microcontrollers are appropriate choices in many demanding control environments especially those with human
interface.
•
•
•
•
•
•
The COP424C is an improved product which replaces the
COP420C.
•
•
•
•
•
•
•
•
•
•
•
•
a"'tJ
~
N
U1
o
......
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~
Lowest power dissipation (50 p,W typical)
Fully static (can turn off the clock)
Power saving IDLE state and HALT mode
4 p,s instruction time, plus software selectable clocks
2k x 8 ROM, 128 x 4 RAM (COP444C/COP445C)
1k x 8 ROM, 64 x 4 RAM (COP424C/COP425C/
COP426C)
23 I/O lines (COP444C and COP424C)
True vectored interrupt, plus restart
Three-level subroutine stack
Single supply operation (2.4V to 5.5V)
Programmable read/write 8-bit timer/event counter
Internal binary counter register with MICROWIRETM
serial I/O capability
General purpose and TRI-STATE® outputs
LSTTLICMOS output compatible
Microbus™ compatible
Software/hardware compatible with COP400 family
Extended temperature range devices COP324C/
COP325C/COP326C and COP344C/COP345C (-40°C
to +85°C)
Military devices (- 55°C to + 125°C) to be available
Block Diagram
N
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o
......
o
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w
N
~
o
......
o
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w
N
U1
o
......
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w
N
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o
......
o
a"'tJ
~
~
~
o
......
o
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~
~
U1
~.
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W
~
~
o
......
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,..-;:;;:;::::;;::;;::::;;;::;-11+ ::]IofICROWIRE I/O
SI
-------------- ---.
I
I
I
I
I
I
I
I
I
I
20 10 9 19
• Not available on COP426C/COP326C
IN J IN2 IN, INo
TL/DD/5259-1
FIGURE 1
1-161
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o
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COP424C/COP425C/COP426C and COP444C/COP445C
Absolute Maximum Ratings
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
~
~
Supply Voltage (Vee>
Voltage at any Pin
Total Allowable Source Current
Total Allowable Sink Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature
(soldering, 10 seconds)
oo
DC Electrical Characteristics O·C~TA~70·C unless otherwise specified
~
~
Cf)
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......
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~
~
~
a..
o
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......
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(D
6V
-0.3V to Vee + 0.3V
25mA
25mA
O·Cto +70·C
- 65·C to + 150·C
300·C
Parameter
Conditions
Operating Voltage
Power Supply Ripple (Note 5)
Vee=2.4V, tc=64 /Ls
Vee=5.0V, tc=16 /Ls
Vee=5.0V, tc=4 /Ls
(tc is instruction cycle time)
o
HALT Mode Current
(Note 2)
Vee=5.0V, FIN=O kHz
Vee=2.4V, FIN=O kHz
o
1.1)
Input Voltage Levels
RESET, CKI, Do (clock input)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
C'I
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......
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C'I
Input Pull-Up Current
a..
Hi-Z Input Leakage
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~
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......
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1.1)
C'I
~
Vee=4.5V, VIN=O
Standard Outputs
Vee=5.0V±10%
IOH= -100 /LA
IOL =400 /LA
IOH= -10 /LA
IOL = 10 /LA
Source (Standard Option)
C'I
Source (Low Current Option)
~
o
o
120
700
3000
/LA
/LA
/LA
40
12
/LA
/LA
0.1 Vee
V
V
0.2 Vee
V
V
30
330
-1
+1
/LA
/LA
7
pF
0.4
V
V
0.2
V
V
Input Capacitance (Note 4)
Output Voltage Levels
LSTTL Operation
Logic High
Logic Low
CMOS Operation
Logic High
Logic Low
o......
a..
V
V
0.7 Vee
Output Current Levels (except CKO)
Sink (Note 6)
o
~
Units
5.5
0.1 Vee
0.9 Vee
a..
o
Max
2.4
Peak to Peak
Supply Current
(Note 1)
a..
Min
CKO Current Levels (As Clock Out)
Sink
+4
+8
+16
+4
Source
+8
+16
}
}
2.7
Vee- 0.2
Vee=4.5V, VOUT=Vee
Vee=2.4V, VOUT=Vee
Vee=4.5V, VOUT=OV
Vee=2.4V, VOUT=OV
Vee=4.5V, VOUT=OV
Vee=2.4V, VOUT=OV
Vee=4.5V, CKI=Vee, VOUT=Vee
Vee=4.5V, CKI=OV, VOUT=OV
1.2
0.2
-0.5
-0.1
-30
-6
n
Allowable Loading on CKO (as HAL
Vee = 4.5V, VIN = 0.2Vee
Vee=4.5V, VIN=0.7Vee
TRI-STATE or Open Drain
Leakage Current
-2.5
1-162
-330
-80
0.3
0.6
1.2
-0.3
-0.6
-1.2
Allowable Sink/Source Current per Pin
(Note 6)
Current Needed to Over-Ride HALT
(Note 3)
To Continue
To Halt
mA
mA
mA
mA
/LA
/LA
mA
mA
mA
mA
mA
mA
5
mA
100
pF
0.7
1.6
mA
mA
+2.5
/LA
o
o"'C
COP324C/COP325C/COP326C and COP344C/COP345C
0l:Io
I\)
Absolute Maximum Ratings
0l:Io
Supply Voltage
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
6V
Voltage at any Pin
Total Allowable Source Current
Total Allowable Sink Current
Operating Temperature Range
Storage Temperature Range
Lead Temperature
(soldering, 10 seconds)
-0.3V to Vee + 0.3V
25mA
25mA
- 40°C to + 85°C
- 65°C to + 150°C
o
o
.......
o"'C
0l:Io
I\)
U1
o
.......
o
o
"'C
300°C
0l:Io
I\)
DC Electrical Characteristics
-40°C~TA~ + 85°C unless otherwise specified
Conditions
Parameter
Operating Voltage
Power Supply Ripple (Note 5)
Max
Units
3.0
5.5
0.1 Vee
V
V
180
800
3600
J.LA
J.LA
J.LA
60
30
J.LA
J.LA
0.1 Vee
V
V
0.2 Vee
V
V
30
440
J.LA
-2
+2
7
J.LA
pF
0.4
V
V
0.2
V
V
-440
-200
rnA
mA
rnA
rnA
J.LA
J.LA
Vee=3.0V, tc=64 J.Ls
Vee= 5.0V, tc= 16 J.Ls
Vee=5.0V, tc=4 J.Ls
(tc is instruction cycle time)
HALT Mode Current
(Note 2)
Vee=5.0V, FIN=O kHz
Vee=3.0V, FIN=O kHz
Input Voltage Levels
RESET, CKI, Do (clock input)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
0.9 Vee
0.7 Vee
Input Pull-Up Current
Vee=4.5V, VIN=O
Hi-Z Input Leakage
Input Capacitance (Note 4)
Output Voltage Levels
LSTTL Operation
Logic High
Logic Low
CMOS Operation
Logic High
Logic Low
Standard Outputs
Vee=5.0V ±10%
10H= -100 J.LA
10L =400 J.LA
Output Current Levels (except CKO)
Sink (Note 6)
Source (Standard Option)
Source (Low Current Option)
CKO Current Levels (As Clock Out)
Sink
+4
+8
+16
+4
Source
+8
+16
}
}
2.7
Vee- 0.2
10H= -10 J.LA
10L =10 J.LA
o"'C
W
I\)
0l:Io
o
.......
o
o"'C
W
I\)
U1
o
.......
o
o
"'C
W
I\)
en
o
.......
o
o"'C
0l:Io
0l:Io
0l:Io
o
o
.......
o"'C
0l:Io
0l:Io
U1
o
.......
o
o
"'C
Vee=4.5V,
Vee=3.0V,
Vee=4.5V,
Vee=3.0V,
Vee=4.5V,
Vee=3.0V,
VOUT=Vee
VOUT=Vee
VOUT=OV
VOUT=OV
VOUT=OV
VOUT=OV
Vee=4.5V, CKI = Vee, VOUT=Vee
Vee=4.5V, CKI=OV, VOUT=OV
1.2
0.2
-0.5
-0.1
-30
-8
0.3
0.6
1.2
-0.3
-0.6
-1.2
Allowable Sink/Source Current per
Pin (Note 6)
n
Allowable Loading on CKO (as HAL
Current Needed to Over-Ride HALT
(Note 3)
To Continue
To Halt
o
o
.......
Min
Peak to Peak
Supply Current
(Note 1)
en
Vee=4.5V, VIN=0.2Vee
Vee = 4.5V, VIN=0. 7Vee
TRI-STATE or Open Drain
Leakage Current
-5
1-163
rnA
rnA
mA
mA
rnA
rnA
5
mA
100
pF
0.9
2.1
mA
rnA
+5
J.LA
W
0l:Io
0l:Io
o
.......
o
o"'C
W
0l:Io
U1
o
oan
"'I::t'
C')
COP424C/COP425C/COP426C and COP444C/COP445C
Q.
o
o
......
o
"'I::t'
"'I::t'
C')
AC Electrical Characteristics O°C~TA ~ 70°C unless otherwise specified.
Parameter
Conditions
VCC~4.5V
Instruction Cycle Time (tc)
Q.
4.5V> VCC~ 2.4V
o
o
......
o
an
Operating CKI
Frequency
"'I::t'
"'I::t'
Q.
oo
......
+4mode
+8 mode
+ 16 mode
+4 mode
+8 mode
+ 16 mode
}
}
VCC~4.5V
4.5V>VCC~2.4V
Min
Max
Units
4
16
DC
DC
DC
DC
DC
DC
DC
DC
1.0
2.0
4.0
250
500
1.0
40
60
%
MHz
MHz
MHz
kHz
kHz
MHz
o"'I::t'
Duty Cycle (Note 4)
Q.
Rise Time (Note 4)
f1 =4 MHz External Clock
60
ns
Fall Time (Note 4)
f1 =4 MHz External Clock
40
ns
N
Instruction Cycle Time
RC Oscillator (Note 4)
R=30k, Vcc = 5V
C=82 pF (+4 Mode)
16
/.Ls
Q.
Inputs: (See Figure 3)
"'I::t'
"'I::t'
oo
......
oCD
C')
o
o
......
tSETUP
o
an
N
C')
Q.
oo
......
o
~
N
C')
Q.
oo
......
o
CD
N
"'I::t'
Q.
oo
......
o
an
N
"'I::t'
Q.
o
o
......
o
~
N
~
Q.
o
o
f1=4 MHz
G Inputs }
Sllnput
Vcc~ 4.5V
All Others
VCC~ 4.5V
4.5V> Vcc~ 2.4V
Output Propagation Delay
tp01, tpoo
tp01, tpoo
Vour= 1.5V, CL = 100 pF, RL =5k
Vcc~ 4.5V
4.5V> Vcc~ 2.4V
Microbus Timing
Read Operation (Figure 4)
Chip Select Stable before RD -tCSR
Chip Select Hold Time for RD -tRCS
RD Pulse Width-tRR
Data Delay from RD -tRO
RD to Data Floating -tOF (Note 4)
CL=50 pF, VCC=5V±5%
8
tc/4+ .7
0.3
1.7
0.25
1.0
1.0
4.0
65
20
400
375
250
ns
ns
ns
ns
ns
Write Operation (Figure 5)
ns
65
Chip Select Stable before WR - tcsw
ns
20
Chip Select Hold Time for WR -twcs
ns
400
WR Pulse Width-tww
ns
320
Data Set·Up Time for WR -tow
ns
100
Data Hold Time for WR -two
700
ns
INTR Transition Time from WR -tWI
Note 1: Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI, CKO open, and all other pins pulled up to Vcc with 5k
resistors. See current drain equation on page 17.
Note 2: The HALT mode will stop CKI from oscillating in the RC and crystal configurations. Test conditions: all inputs tied to Vcc, L lines in TRI-STATE mode and
tied to ground, all outputs low and tied to ground.
Note 3: When forcing HALT, current is only needed for a short time (approx. 200 ns) to flip the HALT flip-flop.
Note 4: This parameter is only sampled and not 100% tested. Variation due to the device included.
Note 5: Voltage change must be less than 0.5 volts in a 1 ms period.
Note 6: SO output sink current must be limited to keep VOL less than 0.2Vcc when part is running in order to prevent entering test mode.
1·164
o
o""0
COP324C/COP325C/COP326C and COP344C/COP345C
AC Electrical Characteristics
N
Conditions
Vcc~4.5V
4.5V> Vcc~ 3.0V
Operating CKI
Frequency
+4 mode
+8 mode
+ 16 mode
+4 mode
+8 mode
+ 16 mode
}
}
~
-40°C:5:TA:5: + 85°C unless otherwise specified.
Parameter
Instruction Cycle Time (tc)
~
Vcc~4.5V
4.5V>Vcc~3.0V
Min
Max
Units
o
......
o
4
16
DC
DC
JJ-s
JJ-s
N
DC
DC
DC
DC
DC
DC
1.0
2.0
4.0
250
500
1.0
MHz
MHz
MHz
kHz
kHz
MHz
40
60
%
o
""0
~
U1
o
......
o
o""0
~
N
en
o
......
o
o""0
Duty Cycle (Note 4)
f1 =4 MHz
Rise Time (Note 4)
f1 =4 MHz external clock
60
ns
W
N
Fall Time (Note 4)
f1 =4 MHz external clock
40
ns
o
......
Instruction Cycle Time
RC Oscillator (Note 4)
R = 30k, VCC = 5V
C = 82 pF (+4 Mode)
16
JJ-s
o""0
8
Inputs: (See Figure 3)
tSETUP
tHOLD
Output Propagation Delay
tpD1, tpDO
tpD1, tpoo
Microbus Timing
Read Operation (Figure 4)
Chip Select Stable before RD -tCSA
Chip Select Hold Time for RD -tACS
RD Pulse Width-tRA
Data Delay from RD -tAD
RD to Data Floating -tDF (Note 4)
Vcc~ 4.5V
G Inputs
Sllnputs
}
All Others
Vcc~ 4.5V
4.5V> VCC ~ 3.0V
tc/4+.7
0.3
1.7
0.25
1.0
VOUT= 1.5V, CL = 100 pF, RL =5k
Vcc~ 4.5V
4.5V> VCC ~ 3.0V
JJ-s
JJ-s
JJ-s
JJ-s
JJ-s
1.0
4.0
JJ-s
JJ-s
375
250
ns
ns
ns
ns
ns
700
ns
ns
ns
ns
ns
ns
CL =50 pF, Vcc=5V±5%
65
20
400
Write Operation (Figure 5)
Chip Select Stable before WR -tcsw
Chip Select Hold Time for WR -twcs
WR Pulse Width-tww
Data Set-Up Time for WR -tow
Data Hold Time for WR - two
INTR Transition Time from WR -tWI
65
20
400
320
100
Note 1: Supply current is measured after running for 2000 cycle times with a square·wave clock on CKI, CKO open, and all other pins pulled up to Vee with 5k
resistors. See current drain equation on page 17.
Note 2: The HALT mode will stop CKI from oscillating in the RC and crystal configurations. Test conditions: all inputs tied to Vee, L lines in TRI·STATE mode and
tied to ground, all outputs low and tied to ground.
Note 3: When forcing HALT, current is only needed for a short time (approx. 200 ns) to flip the HALT flip·flop.
Note 4: This parameter is only sampled and not 100% tested. Variation due to the device included.
Note 5: Voltage change must be less than 0.5 volts in a 1 ms period.
Note 6: SO output sink current must be limited to keep VOL less than 0.2Vee when part is running in order to prevent entering test mode.
1-165
~
o
W
N
U1
o
......
o
o"C
W
N
en
o
......
o
o""0
~
~
~
o
......
o
o
""0
~
~
U1
o
......
o
o""0
w
~
~
o
......
o
o""0
W
~
U1
o
o
I.t)
"'II:t
C")
Connection Diagrams
0..
o
DIP and S.O. Wide
DIP and S.O. Wide
o
.......
o"'II:t
CKO
20
GNO
GNO
24
DO
CKO
23
01
CKI
22
"'II:t
CKI
02
0..
o
RESET
03
o.......
L7
G3
o
I.t)
L6
G2
LS
L5
SK
l4
L4
SO
Vee
Vee
SI
C")
03
L7
0..
o
o
.......
LO
o
"'II:t
L2
G3
eOP42SC
eOP32SC
COPUSC
COP345C
U
"'II:t
"'II:t
02
mET
G2
01
GO
SK
SO
L3
10
l2
11
51
L1
12
LO
TL/DD/5259-2
Ll
"'II:t
"'II:t
Top View
TL/DD/5259-16
0..
o
Order Number COP325C-XXX/D
or COP425C-XXX/D
See NS Hermetic Package D24C
Order Number COP325C-XXX/N
or COP425C-XXX/N
See NS Molded Package N24A
Order Number COP325C-XXX/WM
or COP425C-XXX/WM
See NS Surface Mount Package M24B
Top View
o
.......
o
CD
Order Number COP326C-XXX/D
or COP426C-XXX/D
See NS Hermetic Package D20A
Order Number COP326C-XXX/N
or COP426C-XXX/N
See NS Molded Package N20A
Order Number COP326C-XXX/WM
or COP426C-XXX/WM
See NS Surface Mount Package M20B
N
C")
0..
o
o
o
I.t)
.......
N
C")
0..
o
o
.......
o
"'II:t
Dual-In-Llne Package
PLCC
N
C")
~
I~
GNO
28
DO
CKO
27
01
CKI
26
02
o
CD
REm
25
03
03
L7
L7
24
G3
G3
L6
"'II:t
L6
23
G2
oo
22
G1
. L4
21
GO
0..
oo
.......
N
0..
COP424C
COP324C
COP444C
eoP344C
L5
.......
IN1
o
I.t)
IN3
IN2
10
INO
"'II:t
VCC
11
SK
0..
o
L3
12
SO
o
.......
o
"'II:t
L2
13
SI
Ll
14
LO
N
8
§ 8
G2
L5
Gl
L4
GO
INI
IN2
IN3
INO
19
11
Vce
TL/DD/5259-18
TL/DD/5259-3
N
Top View
0..
Order Number COP324C-XXX/D
or COP424C-XXX/D
See NS Hermetic Package D28C
Order Number COP324C-XXX/N
or COP424C-XXX/N
See NS Molded Package N28B
"'II:t
o
o
Order Number COP324C-XXX/V
or COP424C-XXX/V
See NS PLCC Package V28A
FIGURE 2
Pin
L7-LO
G3-GO
03-00
IN3-INO
SI
SO
Description
Pin
B-bit bidirectional port with TRI-STATE
4-bit bidirectional 1/0 port
4-bit output port
4-bit input port (2B-pin package only)
Serial input or counter input
Serial or general purpose output
SK
CKI
CKO
RESET
Vee
GNO
1·166
Description
Logic controlled clock output
Chip oscillator input
Oscillator output, HALT 110 port or general
purpose input
Reset input
Most positive power supply
Ground
o
o
Functional Description
INTERNAL LOGIC
The internal architecture is shown in Figure 1. Data paths
are illustrated in simplified form to depict how the various
logic elements communicate with each other in implementing the instruction set of the device. Positive logic is used.
When a bit is set, it is a logic "1", when a bit is reset, it is a
logic "0".
For ease of reading only the COP424C/425C/COP426CI
444C/445C are referenced; however, all such references
apply equally to COP324C/325C/COP326C/344C/345C.
PROGRAM MEMORY
Program Memory consists of ROM, 1024 bytes for the
COP424CI 425CI 426C and 2048 bytes for the COP444CI
445C. These bytes of ROM may be program instructions,
constants or ROM addressing data.
Three levels of subroutine nesting are implemented by a
three level deep stack. Each subroutine call or interrupt
pushes the next PC address into the stack. Each return
pops the stack back into the PC register.
DATA MEMORY
Data memory consists of a 512-bit RAM for the COP444CI
445C, organized as 8 data registers of 16 x 4-bit digits.
RAM addressing is implemented by a 7-bit 8 register whose
upper 3 bits (8r) select 1 of 8 data registers and lower 4 bits
(8d) select 1 of 16 4-bit digits in the selected data register.
o
......
o
o
A 4-bit adder performs the arithmetic and logic functions,
storing the results in A. It also outputs a carry bit to the 1-bit
C register, most often employed to indicate arithmetic overflow. The C register in conjunction with the XAS instruction
and the EN register, also serves to control the SK output.
o
oI::ao
N
U1
o
......
o
"
oI::ao
N
en
o
......
o
o
"
W
N
oI::ao
o
......
o
o
"
W
N
U1
o
......
The 0 register provides 4 general-purpose outputs and is
used as the destination register for the 4-bit contents of 8d.
In the dual clock mode, DO latch controls the clock selection
(see dual oscillator below).
W
N
The Q register is an internal, latched, 8-bit register, used to
hold data loaded to or from M and A, as well as 8-bit data
from ROM. Its contents are outputted to the L liD ports
when the L drivers are enabled under program control. With
the Microbus option selected, Q can also be loaded with the
8-bit contents of the L liD ports upon the occurrence of a
write strobe from the host CPU.
The a L drivers, when enabled, output the contents of
latched Q data to the L liD port. Also, the contents of L may
be read directly into A and M. As explained above, the
Microbus option allows L liD port data to be latched into the
Q register.
The 8d register also serves as a source register for 4-bit
data sent directly to the 0 outputs.
"
Four general-purpose inputs, IN3-INO, are provided. IN1,
IN2 and IN3 may be selected, by a mask-programmable option as Read Strobe, Chip Select, and Write Strobe inputs,
respectively, for use in Microbus application.
The G register contents are outputs to a 4-bit general-purpose bidirectional liD port. GO may be mask-programmed
as an output for Microbus applications.
Data memory consists of a 256-bit RAM for the COP424CI
425C/426C, organized as 4 data registers of 16 x 4-bits
digits. The 8 register is 6 bits long. Upper 2 bits (8r) select 1
of 4 data registers and lower 4 bits (8d) select 1 of 16 4-bit
digits in the selected data register. While the 4-bit contents
of the selected RAM digit (M) are usually loaded into or
from, or exchanged with, the A register (accumulator), it
may also be loaded into or from the Q latches or T counter
or loaded from the L ports. RAM addressing may also be
performed directly by the LOO and XAD instructions based
upon the immediate operand field of these instructions.
oI::ao
N
oI::ao
The processor contains its own 4-bit A register (accumulator) which is the source and destination register for most liD,
arithmetic, logic, and data memory access operations. It can
also be used to load the 8r and 8d portions of the 8 register, to load and input 4 bits of the 8-bit Q latch or T counter,
to input 4 bits of L liD ports data, to input 4-bit G, or IN
ports, and to perform data exchanges with the SID register.
The a-bit T counter is a binary up counter which can be
loaded to and from M and A using CAMT and CTMA instructions. This counter may be operated in two modes depending on a mask-programmable option: as a timer or as an
external event counter. When the T counter overflows, an
overflow flag will be set (see SKT and IT instructions below).
The T counter is cleared on reset. A functional block diagram of the timerlcounter is illustrated in Figure 10a.
ROM addressing is accomplished by a 11-bit PC register
which selects one of the 8-bit words contained in ROM. A
new address is loaded into the PC register during each instruction cycle. Unless the instruction is a transfer of control
instruction, the PC register is loaded with the next sequential 11-bit binary count value.
"
o
o
"en
o
......
o
o
"
oI::ao
oI::ao
oI::ao
o
......
o
o
"
oI::ao
oI::ao
U1
o
......
o
o
"w
oI::ao
oI::ao
o
......
o
o
"w
oI::ao
U1
o
1-167
o
II)
""=I'
(f)
a..
o
o
.......
o
""=I'
""=I'
(f)
a..
oo
.......
o
II)
""=I'
""=I'
a..
o
o
.......
o
""=I'
""=I'
""=I'
r---------------------------------------------------------------------~
Functional Description
(Continued)
The SID register functions as a 4-bit serial-in/serial-out shift
register for MICROWIRE 110 and COPS peripherals, or as a
binary counter (depending on the contents of the EN register). Its contents can be exchanged with A.
each low-going pulse ("1" to "0") occurring on the SI
input. Each pulse must be at least two instruction cycles
wide. SK outputs the value of SKL. The SO output equals
the value of EN3. With END reset, SID is a serial shift
register left shifting 1 bit each instruction cycle time. The
data present at SI goes into the least significant bit of
SID. SO can be enabled to output the most significant bit
of SID each cycle time. The SK outputs SKL ANDed with
the instruction cycle clock.
The XAS instruction copies C into the SKL latch. In the
counter mode, SK is the output of SKL; in the shift register
mode, SK outputs SKL ANDed with the clock.
EN is an internal 4-bit register loaded by the LEI instruction.
The state of each bit of this register selects or deselects the
particular feature associated with each bit of the EN register:
1. With EN1 set, interrupt is enabled. Immediately following
an interrupt, EN1 is reset to disable further interrupts.
O. The least significant bit of the enable register, END, selects the SID register as either a 4-bit shift register or a
4-bit binary counter. With END set, SID is an asynchronous binary counter, decrementing its value by one upon
2. With EN2 set, the L drivers are enabled to output the data
in Q to the L 110 port. Resetting EN2 disables the L drivers, placing the L 110 port in a high-impedance input
state.
a..
oo
.......
oCD
CKI
N
(f)
a..
o
o
.......
o
It)
N
C")
Q.
o
U
SK (AS A
CLOCK) _ _. ._ .....
\
L7-Lo. --.....,;,-------....:-""",..-..;;;;--..;;.~,-------~
CKOG3-GO.
& SIINPUTS
_ _ _ _ _ _ _ _ _ _ _ _"'"_ _ _ _ _....,.j"'-_______
I-tpOO-~
G3-GO.03-00.
L7-lo. SO. SK
OUTPUTS
,
TLlDD/5259-4
.......
U
FIGURE 3. InputlOutput Timing Diagrams (divide by 8 mode)
""=I'
N
(f)
Q.
CD
N
""=I'
I
""'
o
U
.......
U
(lN1)
-IRCS~
IRR
'\
li1!
j
----------c(. . ___________.Iot-ICSR-\-IRO-
(L7-LO)
07-00
Q.
oU
I-IOF-
TL/DD/5259-5
FIGURE 4. Microbus Read Operation Timing
.......
U
It)
N
""=I'
IWW
ICSW
Q.
.
IWcs-1
I
\
o
U
.......
U
!-IOW-
-
""=I'
N
""=I'
Q.
o
U
_ VOL
I-X
IWO
-IWI
(Go)
INTR
TL/DD/5259-6
FIGURE 5. Microbus Write Operation Timing
1-168
~------------------------------------------------------------------------I
Functional Description
(Continued)
3. EN3, in conjunction with ENO, affects the SO output. With
ENO set (binary counter option selected) SO will output
the value loaded into EN3. With ENO reset (serial shift
register option selected), setting EN3 enables SO as the
output of the SIO shift register, outputting serial shifted
data each instruction time. Resetting EN3 with the serial
shift register option selected disables SO as the shift register output; data continues to be shifted through SIO and
can be exchanged with A via an XAS instruction but SO
remains set to "0".
I\)
e. An LEI instruction may be put immediately before the
RET instruction to re-enable interrupts.
MICROBUS INTERFACE
a. The interrupt, once recognized as explained below,
pushes the next sequential program counter address
(PC + 1) onto the stack. Any previous contents at the bottom of the stack are lost. The program counter is set to
hex address OFF (the last word of page 3) and EN1 is
reset.
IN3 becomes WR - a logic "0" on this line will write bus
data from the L ports to the Q latches for input to the
COP444C/424C. GO becomes INTR a "ready" output, reset
by a write pulse from the uP on the WR line, providing the
"handshaking" capability necessary for asynchronous data
transfer between the host CPU and the COP444C/424C.
b. An interrupt will be recognized only on the following conditions:
1. EN1 has been set.
2. A low-going pulse ("1" to "0") at least two instruction
cycles wide has occurred on the IN, input.
3. A currently executing instruction has been completed.
4. All successive transfer of control instructions and successive LBls have been completed (e.g. if the main
program is executing a JP instruction which transfers
program control to another JP instruction, the interrupt
will not be acknowledged until the second JP instruction has been executed).
This option has been designed for compatibility with National's Microbus - a standard interconnect system for 8-bit
parallel data transfer between MOS/LSI CPUs and interfacing devices. (See Microbus National Publication.) The functioning and timing relationships between the signal lines affected by this option are as specified for the Microbus interface, and are given in the AC electrical characteristics and
shown in the timing diagrams (Figures 4 and 5). Connection
of the COP444C/424C to the Microbus is shown in Figure 6.
~~L~
I I I I
VCc GNO CKI CKO
INTERRUPT (INTR)
0
1
1
0
1
1
SIO
"1J
0l:Io
I\)
0)
o
'"
o
a"1J
(,,)
I\)
0l:Io
o
o
'"
a
"1J
(,,)
I\)
U1
o
o
'"
a
"1J
(,,)
I\)
0)
o
o
'"
a
"1J
00-07
MICROPROCESSOR
READ STROBE (illi) r
CHIP SElfCT (CS)
WRITE STROBE (WR)
0l:Io
0l:Io
U1
~
a·BIT DATA BUS
o
Do-Da ~
} Lo-L7
COP444C/424C
IN1
INO
IN2
SI
IN3
SO
SK
IIf---f----
IN
o
'"
a
"1J
(,,)
OUT
0l:Io
0l:Io
o
o
'"
a"1J
t
(,,)
TABLE I. Enable Register Modes -
Shift
Register
Shift
Register
Binary
Counter
Binary
Counter
o
o
'"
a
a"1J
'A-:-::!\..
G1- Ga ~
Go
FIGURE 6. Microbus Option Interconnect
0
0l:Io
I\)
U1
o
o
'"
CLOCK
TL/DD/5259-7
0
o
o
'"
a
0l:Io
0l:Io
0l:Io
c. Upon acknowledgement of an interrupt, the skip logic
status is saved and later restored upon popping of the
stack. For example, if an interrupt occurs during the execution of ASC (Add with Carry, Skip on Carry) instruction
which results in carry, the skip logic status is saved and
program control is transferred to the interrupt servicing
routine at hex address OFF. At the end of the interrupt
routine, a RET instruction is executed to pop the stack
and return program control to the instruction following the
original ASC. At this time, the skip logic is enabled and
skips this instruction because of the previous ASC carry.
Subroutines should not be nested within the interrupt
service routine, since their popping of the stack will enable any previously saved main program skips, interfering
with the orderly execution of the interrupt routine.
END EN3
0l:Io
"1J
The COP444C/424C has an option which allows it to be
used as a peripheral microprocessor device, inputting and
outputting data from and to a host microprocessor (Il-P).
IN1, IN2 and IN3 general purpose inputs become Microbus
compatible read-strobe, chip-select, and write·strobe lines,
respectively. IN1 becomes RD - a logic "0" on this input
will cause Q latch data to be enabled to the L ports for input
to the uP. IN2 becomes CS - a logiC "0" on this line selects the COP444C/424C as the uP peripheral device by
enabling the operation of the RD and WR lines and allows
for the selection of one of several peripheral components.
The following features are associated with interrupt procedure and protocol and must be considered by the programmer when utilizing interrupts.
a"1J
0l:Io
d. The instruction at hex address OFF must be a NOP.
INTERRUPT
0
SI
SO
Bits ENO and EN3
SK
Input to Shift
0
If SKL = 1,SK = clock
Register
if SKL=O,SK=O
Input to Shift Serial If SKL = 1,SK = clock
Register
out If SKL=O,SK=O
0
SK=SKL
Input to
Counter
Input to
1
SK=SKL
Counter
1·169
0l:Io
U1
o
o
U)
~
C")
D.
oo
Functional Description (Continued)
INITIALIZATION
D.
The internal reset logic will initialize the device upon powerup if the power supply rise time is less than 1 ms and if the
operating frequency at CKI is greater than 32 kHz, otherwise the external RC network shown in Figure 7 must be
connected to the RESET pin (the conditions in Figure 7
must be met). The RESET pin is configured as a Schmitt
trigger input. If not used, it should be connected to Vee.
Initialization will occur whenever a logic "0" is applied to the
RESET input, providing it stays low for at least three instruction cycle times.
......
Note: If CKI clock is less than 32 kHz. the internal reset logic (option
/I 29 = 1) MUST be disabled and the external RC circuit must be used .
......
o
~
~
C")
D.
o
o
......
o
U)
~
~
oo
o
~
~
~
p +-
o
o......
o(0
D.
o
o......
TLlDD/5259-8
FIGURE 7. Power-Up Circuit
N
C")
o
"Ii:t'
N
C")
c..
o
o
......
o
(0
HALT MODE
The COP444C/445C/424C/425C/426C is a FULLY STATIC circuit; therefore, the user may stop the system oscillator
at any time to halt the chip. The chip may also be halted by
the HALT instruction or by forcing CKO high when it is
mask-programmed as an HALT I/O port. Once in the HALT
mode, the internal circuitry does not receive any clock signal and is therefore frozen in the exact state it was in when
halted. All information is retained until continuing. The chip
may be awakened by one of two different methods:
RC>5X POWER SUPPLY RISE TIME
AND RC>100X CKI PERIOD .
o
it)
c..
Note: The IT instruction is not allowed in this mode.
:: r::
GND
V _ _..._ _ _ _ _...-
C")
o
......
b. External event counter. In this mode, a low-going pulse
("1" to "Oil) at least 2 instruction cycles wide on the IN2
input will increment the 8-bit T counter.
Vec
...............j1imT CO:::~CI
N
o
.........,....---.,.
:~E L I :: ~~
D.
TIMER
There are two modes selected by mask option:
a. Time-base counter. In this mode, the instruction cycle frequency generated from CKI passes through a 2-bit divideby-4 prescaler. The output of this prescaler increments
the 8-bit T counter thus providing a 10-bit timer. The prescaler is cleared during execution of a CAMT instruction
and on reset.
For example, using a 4 MHz crystal with a divide-by-16
option, the instruction cycle frequency of 250 kHz increments the 1O-bit timer every 4 IJ-s. By presetting the counter and detecting overflow, accurate timeouts between
16 IJ-s (4 counts) and 4.096 ms (1024 counts) are possible. Longer timeouts can be achieved by accumulating,
under software control, multiple overflows.
Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, 0, EN, IL, T and G registers are
cleared. The SKL latch is set, thus enabling SK as a clock
output. Data Memory (RAM) is not cleared upon initialization. The first instruction at address 0 must be a CLRA
(clear A register).
• Continue function: by forcing CKO low, if it mask-programmed as an HALT I/O port, the system clock is reenabled and the circuit continues to operate from the
point where it was stopped.
• Restart: by forcing the RESET pin low (see Initialization).
N
"Ii:t'
c..
oo
VCC
......
o
it)
N
A
CKI
CKO
~
c..
o
......
o
"Ii:t'
o
"""
o
.n.r
HALT
CLOCK
GENERAL PURPOSE
EXTERNAL
OR
CKI
"Ii:t'
c..
o
CKI
OR EXTERNAl CLOCK
~
INPUT
N
o
DO -
CKO
CKO
t
T .. - vcc
~ HALT
I":'
OR
GENER~L~RPOSE
TL/DD/5259-9
RC Controlled Oscillator
Crystal or Resonator
Component Values
Crystal
Value
R1
R2
C1(pF)
C2(pF)
32kHz
455 kHz
2.096 MHz
4.0 MHz
220k
5k
2k
1k
20M
10M
1M
1M
30
80
30
30
6-36
40
6-36
6-36
R
C
Cycle
Time
Vee
15k
30k
60k
82 pF
82 pF
100 pF
4-9 IJ-s
8-16 IJ-s
16-32 IJ-s
~4.5V
Note: 15ks:RS: 150k
50 pFs:CS:150 pF
FIGURE 8. Oscillator Component Values
1-170
~4.5V
2.4-4.5V
o
Functional Description
o
(Continued)
""C
The HALT mode is the minimum power dissipation state.
c. RC Controlled Oscillator. CKI is configured as a single pin
RC controlled Schmitt trigger oscillator. The instruction
cycle equals the oscillation frequency divided by 4. CKO
is the HALT 1/0 port or a general purpose input.
Note: If the user has selected dual-clock with DO as external
oscillator (option 30=2) AND the COP444C/424C is
running with the DO clock, the HALT mode - either
hardware or software - will NOT be entered. Thus,
the user should switch to the CKI clock to HALT. Alternatively, the user may stop the DO clock to minimize power.
d. Dual oscillator. By selecting the dual clock option, pin DO
is now a single pin oscillator input. Two configurations are
available: RC controlled Schmitt trigger oscillator or external oscillator.
The user may software select between the DO oscillator
(in that case, the instruction cycle time equals the DO
oscillation frequency divided by 4) by setting the DO latch
high or the CKI (CKO) oscillator by resetting DO latch low.
Note that even in dual clock mode, the counter, if maskprogrammed as a time-base counter, is always connected to the CKI oscillator.
CKO PIN OPTIONS
a. Two-pin oscillator -
(Crystal). See Figure BA.
In a crystal controlled oscillator system, CKO is used as
an output to the crystal network. The HALT mode may be
entered by program control (HALT instruction) which
forces CKO high, thus inhibiting the crystal network. The
circuit can be awakened only by forcing the RESET pin to
a logic "0" (restart).
b. One-pin oscillator -
For example, the user may connect up to a 1 MHz RC
circuit to DO for faster processing and a 32 kHz watch
crystal to CKI and CKO for minimum current drain and
time keeping.
(RC or external). See Figure B8.
If a one-pin oscillator system is chosen, two options are
available for CKO:
•
•
Note: CTMA instruction is not allowed when chip is running
from DO clock.
CKO can be selected as the HALT 1/0 port. In that
case, it is an 1/0 flip-flop which is an indicator of the
HALT status. An external signal can over-ride this pin
to start and stop the chip. By forcing a high level to
CKO, the chip will stop as soon as CKI is high and
CKO output will stay high to keep the chip stopped if
the external driver returns to high impedance state.
By forcing a low level to CKO, the chip will continue
and CKO will stay low.
OSCILLATOR OPTIONS
a. Crystal Controlled Oscillator. CKI and CKO are connected to an external crystal. The instruction cycle time equals
the crystal frequency optionally divided by 4, 8 or 16.
N
U1
o
.......
o
o""C
.c:..
N
0')
o
.......
o
o""C
~
N
.c:..
o
.......
o
o""C
~
N
U1
COP445C AND COP425C 24-PIN PACKAGE OPTION
o""C
COP426C 20-PIN PACKAGE OPTION
If the COP425C is bonded as 20-pin device it becomes the
COP426C. Note that the COP426C contains all the
COP425C pins except Do, 01, Go, and G1.
b. External Oscillator. The external frequency is optionally
divided by 4, 8 or 16 to give the instruction cycle time.
CKO is the HALT 1/0 port or a general purpose input.
.c:..
.......
Note: If user selects the 24-pin package, options 9, 10, 19
and 20 must be selected as a "0" (load to Vee on the
IN inputs). See option list.
There are four basic clock oscillator configurations available
as shown by Figure 8.
o
o""C
Figures 10A and 108 show the clock and timer diagrams
with and without Dual clock.
If the COP444C/424C is bonded in a 24'pin package, it becomes the COP445C/425C, illustrated in Figure 2, Connection diagrams. Note that the COP445C/425C does not contain the four general purpose IN inputs (IN3-INO). Use of
this option precludes, of course, use of the IN options, interrupt feature, external event counter feature, and the
Microbus option which uses IN1-IN3. All other options are
available for the COP445C/425C.
As another option, CKO can be a general purpose input, read into bit 2 of A (accumulator) upon execution
of an INIL instruction.
.c:..
.c:..
o
.......
N
o
o
~
N
0')
o
.......
o
o
""C
.c:..
.c:..
.c:..
o.......
o
o""C
.c:..
.c:..
U1
~
""C
~
.c:..
.c:..
o
.......
o
Block Diagram
o""C
(Continued)
~
.c:..
U1
o
TO CLOCK GENERATOR
HALT
INSTRUCTION
TLlDD/5259-10
FIGURE 9A. Halt Mode - Two-Pin Oscillator
1-171
..
o
Lt)
"11:1'
C")
Block Diagram
(Continued)
D.
oo
" ,~ -JO-" - H-A-LT-I/-0-PO-~oC)1L I . c~o
.......
o
"11:1'
"11:1'
C")
D.
oo
.......
o
Lt)
Ace••• U,,"
"11:1'
"11:1'
D.
oo
.......
o
"11:1'
"11:1'
"11:1'
TO CLOCK GENERATOR
CKI
D.
oo
TL/DD/5259-11
.......
FIGURE 98. Halt Mode - One-Pin Oscillator
oCD
N
C")
D.
oo
.......
o
Lt)
N
C")
D.
oo
TO SKT
LATCH
.......
o"11:1'
N
C")
D.
oo
.......
o
CD
N
"11:1'
IT
D.
oo
.......
o
Lt)
TL/DD/5259-12
FIGURE 10A. Clock and Timer without Dual-Clock
N
"11:1'
D.
o
o
.......
o
"11:1'
N
"11:1'
D.
oo
CKI
OSCILLATOR
t
HALT
HALT
TL/DD/5259-13
FIGURE 108. Clock and Timer with Dual-Clock
1·172
o
o
Instruction Set
-a
Table" is a symbol table providing internal architecture, instruction operan and operation symbols used in the instruction set table.
Table '" provides the mnemonic, operand, machine code
data flow, skip conditions and description of each instruction.
TABLE II. Instruction Set Table Symbols
Symbol
Internal Architecture Symbols
A
B
Br
4-bit accumulator
7·bit RAM address register (6-bit for COP424C)
d
4-bit operand field, 0-15 binary (RAM digit select)
r
3(2)·bit operand field, 0-7(3) binary
(RAM register select)
a
11-bit operand field, 0-2047 (1023)
y
4-bit operand field, 0-15 (immediate data)
RAM(x) RAM addressed by variable x
ROM (x) ROM addressed by variable x
Upper 3 bits of B (register address)
(2-bit for COP424C)
o
......
o
o-a
Instruction Operand Symbols
Definition
0l:Io
I\)
0l:Io
0l:Io
I\)
U1
o
......
o
o-a
0l:Io
I\)
en
o
......
Bd
C
Lower 4 bits of B (digit address)
1-bit carry register
o
4-bit data output port
Operational Symbols
EN
+
Plus
-
Minus
o
......
~
IN
4-bit enable register
4-bit general purpose I/O port
two 1-bit (INO and IN3) latches
4-bit input port
o-a
L
8-bit TRI-STATE 1/0 port
Replaces
Is exchanged with
G
IL
M
PC
Q
~
=
4-bit contents of RAM addressed by B
11-bit ROM address program counter
8-bit latch for L port
SA,SB,SC 11-bit 3-level subroutine stack
SIO
4-bit shift register and counter
SK
Logic-controlled clock output
1-bit latch for SK output
SKL
T
o
o-a
w
I\)
0l:Io
o
w
I\)
A
e
Is equal to
One's complement of A
Exclusive-or
o
......
o
:
Range of values
-a
U1
o
w
I\)
en
o
......
o
o-a
8-bit timer
0l:Io
0l:Io
0l:Io
o
......
TABLE III. COP444C/445C Instruction Set
Mnemonic
Operand
Hex
Code
Machine
Language
Code
(Binary)
Data Flow
o
o-a
Skip
Conditions
Description
30
o
10011100001
I
A+C+RAM(B) ~ A
Carry~ C
Carry
A+RAM(B)~A
None
Add RAMtoA
A+1010~A
None
Add TentoA
A+y~A
Carry
Add Immediate. Skip on
Carry (y# 0)
Add with Carry, Skip on
Carry
ADD
31
1001110001
ADT
4A
1010011010 I
5-
10101
CASC
10
10001100001
A+RAM(B)+C~A
Carry~ C
Carry
Complement and Add with
Carry, Skip on Carry
CLRA
00
10000100001
O~A
None
Clear A
COMP
40
10100100001
A~A
None
Ones complement of A to A
NOP
44
10100101001
None
None
No Operation
RC
32
10011100101
"O"~C
None
ResetC
SC
22
10010100101
"1"~C
None
SetC
XOR
02
10000100101
AeRAM(B)~A
None
Exclusive-OR RAM with A
AISC
y
I
~
o
......
o-a
ARITHMETIC INSTRUCTIONS
ASC
0l:Io
0l:Io
U1
I
1-173
w
0l:Io
0l:Io
o
......
o
o-a
w
0l:Io
U1
o
(.)
Lt)
~
C")
a.
I nstruction Set (Continued)
o
(.)
Table III. COP444C/445C Instruction Set (Continued)
.......
(.)
~
~
Mnemonic
Operand
C")
a.
o(.)
.......
(.)
Lt)
~
~
a.
o(.)
.......
(.)
Hex
Code
JID
JMP
a
JP
a
FF
11111111111
ROM (PC10:a A,M) -+ PC7:0
None
Jump Indirect (Notes 1,3)
1011O lOla10'61
a-+ PC
None
Jump
a-+ PC6:0
None
Jump within Page (Note 4)
--
~
~
--
111 1 a5'O 1
(all other pages)
a-+ PC5:0
--
110 1 a5'Q 1
PC + 1 -+ SA -+ SB -+ SC
00010 -+ PC10:6
a-+ PC5:0
None
Jump to Subroutine Page
(Note 5)
6-
10110111a10'61
Jump to Subroutine
~
PC + 1 -+ SA -+ SB -+ SC
a-+ PC
None
--
.......
JSRP
a
JSR
a
C")
a.
(.)
Lt)
C'i
C")
a.
o(.)
.......
RET
48
10100110001
SC -+ SB -+ SA -+ PC
None
Return from Subroutine
RETSK
49
10100110011
SC-+ SB -+ SA-+ PC
Always Skip
on Return
Return from Subroutine
then Skip
HALT
33
38
33
39
10011100111
10011110001
10011100111
10011 11001 1
None
HALT Processor
None
IDLE till Timer
Overflows then Continues
(.)
~
C'i
C")
a.
o(.)
Description
(pages 2,3 only)
or
a.
.......
Skip
Conditions
6-
--
o
(.)
o(.)
Data Flow
TRANSFER CONTROL INSTRUCTIONS
~
~
~
(.)
CD
C'i
Machine
Language
Code
(Binary)
IT
.......
(.)
CD
C'i
MEMORY REFERENCE INSTRUCTIONS
a.
CAMT
33
3F
10011100111
10011 11111 1
A -+ T7:4
RAM (B) -+ T 3:0
None
Copy A, RAM to T
CTMA
33
2F
10011100111
1001011111 1
T 7:4 -+ RAM (B)
T3:0 -+ A
None
Copy T to RAM, A (Note 9)
CAMQ
33
3C
10011100111
10011111001
A-+ Q7:4
RAM (B) -+ Q3:0
None
Copy A, RAM to Q
COMA
33
2C
10011100111
10010111001
Q7:4 -+ RAM (B)
Q3:0 -+ A
None
Copy Q to RAM, A
-5
100 1r 10101 1
(r=0:3)
RAM(B)-+A
BrEllr -+ Br
None
Load RAM into A,
Exclusive-OR Br with r
23
10010100111
10 1 r 1 d 1
RAM(r,d) -+ A
None
--
Load A with RAM pointed
to directly by r,d
BF
11011 11111 1
ROM(PC10:a,A,M) -+ Q
SB -+ SC
None
Load Q Indirect (Note 3)
~
o
(.)
.......
(.)
Lt)
C'i
~
a.
o
(.)
.......
(.)
~
C'i
~
a.
o(.)
LD
LDD
r
r,d
LOID
RMB
0
1
2
3
4C
45
42
43
10100111001
10100101011
10100100101
10100100111
0-+ RAM(B)o
0-+ RAM(Bh
0-+ RAM(B)2
0-+ RAM(B)a
None
Reset RAM Bit
5MB
0
1
2
3
40
47
46
4B
10100111011
10100101111
10100101101
10100110111
1 -+
1 -+
1 -+
1 -+
None
Set RAM Bit
RAM(B)o
RAM(B)1
RAM(B)2
RAM(B)a
1-174
o
o
Instruction Set (Continued)
."
~
I\,)
Table III. COP444C/445C Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
Machine
Language
Code
(Binary)
Skip
Conditions
Data Flow
~
o
......
o
Description
~
I\,)
U1
MEMORY REFERENCE INSTRUCTIONS (Continued)
STII
X
XAD
y
r
r,d
7-
-6
23
-XDS
XIS
r
r
-7
-4
10111 1 Y..
1
100 1 r 101101
(r=0:3)
y-+ RAM (B)
Bd + 1 -+ Bd
None
RAM(B)~A
None
Exchange RAM with A,
Exclusive-OR Br with r
None
Exchange A with RAM
Pointed to Directly by r,d
Br ED r -+ Br
10010100111
11 1 r 1 d 1
RAM(r,d)~A
100 1r 10111 1
(r=0:3)
RAM(B)~
100 1 r 10100 1
(r=0:3)
Store Memory Immediate
1 and Increment Bd
Bd-1 -+ Bd
Br ED r -+ Br
RAM(B)~A
Bd
decrements
past 0
Exchange RAM with A
and Decrement Bd.
Exclusive-OR Br with r
Bd+1 -+ Bd
Br ED r -+ Br
Bd
increments
past 15
Exchange RAM with A
and Increment Bd,
Exclusive-OR Br with r
REGISTER REFERENCE INSTRUCTIONS
50
10101100001
A-+ Bd
None
Copy A to Bd
CBA
4E
10100111101
Bd-+A
None
Copy Bd toA
--
100Iri (d-1) 1
(r=0:3:
d=0,9:15)
or
10011100111
111 r i d 1
(any r, any d)
r,d -+ B
Skip until
not a LBI
Load B Immediate with r,d
(Note 6)
33
6-
10011100111
10110 1 Y.. I
y-+ EN
None
Load EN Immediate (Note 7)
12
10001100101
A~Br
None
Exchange A with Br (Note 8)
r,d
33
-LEI
Y
XABR
o
......
o
o
."
~
I\,)
0')
o
......
o
o
."
W
I\,)
A
CAB
LBI
o
."
~
o
......
o
o
."
W
I\,)
U1
o
......
o
o."
W
I\,)
0')
o
......
o
o
."
~
~
~
o
......
o
o
."
~
~
U1
~III
."
TEST INSTRUCTIONS
w
SKC
20
1001010000
C="1"
Skip if C is True
SKE
21
1001010001
A=RAM(B)
Skip if A Equals RAM
SKGZ
33
21
1001110011
1001010001
G3:0=0
Skip if G is Zero
(all 4 bits)
~
~
o
......
o
o
."
W
~
U1
0
1
2
3
33
01
11
03
13
1001110011
1000010001
1000110001
1000010011
1000110011
0
1
2
3
01
11
03
13
1000010001
1000110001
1000010011
1000110011
RAM(B)o=O
RAM(B)1=0
RAM(B)2=0
RAM(Bb=O
Skip if RAM Bit is Zero
41
1010010001
A time-base
counter carry
has occurred
since last test
Skip on Timer
(Note 3)
SKGBZ
SKMBZ
SKT
1st byte
} 2nd byte
1-175
Skip if G Bit is Zero
Go=O
G1=0
G2=0
G3=0
o
o
in
0II:t'
C")
a..
o
o
.......
o
0II:t'
Instruction Set (Continued)
Table III. COP444C/445C Instruction Set (Continued)
Operand
Hex
Code
Machine
Language
Code
(Binary)
Skip
Conditions
0II:t'
Mnemonic
a..
oo
.......
o
in
ING
33
2A
10011100111
10010110101
G~A
None
Input G Ports to A
ININ
33
28
10011100111
10010110001
IN~A
None
Input IN Inputs to A
(Note 2)
INIL
33
29
10011100111
10010110011
IL3, CKO,"O",ILo ~ A
None
Input IL Latches to A
(Note 3)
INL
33
2E
10011100111
10010111101
L7:4 ~ RAM(8)
None
Input L Ports to RAM,A
33
3E
10011100111
10011 11110 1
8d~D
None
Output 8d to D Outputs
33
10011100111
10101 1 y 1
y~G
None
5-
Output to G Ports
Immediate
OMG
33
3A
10011100111
10011110101
RAM(8)~G
None
Output RAM to G Ports
XAS
4F
10100111111
A~SIO,C~SKL
None
Exchange A with SIO
(Note 3)
C")
a..
.......
o
0II:t'
0II:t'
0II:t'
a..
o
o
.......
oCD
C'I
C")
a..
o
o
.......
o
in
OBD
OGI
y
C'I
C")
a..
o
o
.......
o
0II:t'
Description
INPUTIOUTPUT INSTRUCTIONS
0II:t'
0II:t'
oo
DataFlow
L3:0~A
C'I
C")
a..
Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to N where
oo
o signifies the least significant bit (low-order, right-most bit). For example, A3 indicates the most significant (left-most) bit of the 4-bit A register.
o
CD
Note 3: For additional information on the operation of the XAS, JID, LaiD, INIL, and SKT instructions, see below.
.......
C'I
0II:t'
a..
o
o.......
o
in
C'I
0II:t'
a..
o
.......
o
0II:t'
o
Note 2: The ININ instruction is not available on the 24-pin packages since these devices do not contain the IN inputs.
Note 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction,
otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Note 5: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of Pl. A JSRP may not be used when in pages 2 or 3. JSRP
may not jump to the last word in page 2 .
Note 6: LBI is a single-byte instruction if d = 0, 9, 10, II, 12, 13, 14, or 15. The machine code for the lower 4 bits equals the binary value of the "d" data minus 1,
e.g., to load the lower four bits of B(Bd) with the value 9 (10012), the lower 4 bits of the LBI instruction equal 8 (10002). To load 0, the lower 4 bits of the LBI
instruction should equal 15 (11112).
Note 7: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a "1" or "0" in each bit of EN corresponds
with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
Note 8: For 2K ROM devices, A - . Br (0 -
A3). For 1 K ROM devices, A - . Br (0,0 -
A3, A2) .
Note 9: Do not use CTMA instruction when dual-clock option is selected and part is running from Do clocks.
C'I
0II:t'
a..
o
o
1-176
o
a"tJ
Description of Selected Instructions
and resets these latches to allow them to respond to subsequent low-going pulses on the IN3 and INO lines. If CKO is
mask programmed as a general purpose input, an INIL will
input the state of CKO into A2. If CKO has not been so
programmed, a "1" will be placed in A2. AO is input into A 1.
IL latches are cleared on reset. IL latches are not available
on the COP445C/425C, and COP426C.
XAS INSTRUCTION
XAS (Exchange A with SID) copies C to the SKL latch and
exchanges the accumulator with the 4-bit contents of the
SID register. The contents of SID will contain serial-in/seriai-out shift register or binary counter data, depending on the
value of the EN register. If SID is selected as a shift register,
an XAS instruction can be performed once every 4 instruction cycles to effect a continuous data stream.
INSTRUCTION SET NOTES
a. The first word of a program (ROM address 0) must be a
CLRA (Clear A) instruction.
b. Although skipped instructions are not executed, they are
still fetched from the program memory. Thus program
paths take the same number of cycles whether instructions are skipped or executed except for JID, and LaiD.
LQID INSTRUCTION
LaiD (Load a Indirect) loads the 8-bit Q register with the
contents of ROM pointed to by the 11-bit word
PC10:PC8,A,M. LQID can be used for table lookup or code
conversion such as 8CD to seven-segment. The LaiD instruction "pushes" the stack (PC + 1 ~ SA ~ S8 ~ SC)
and replaces the least significant 8 bits of the PC as follows:
A ~ PC(7:4), RAM(8) ~ PC(3:0), leaving PC(10), PC(9)
and PC(8) unchanged. The ROM data pointed to by the new
address is fetched and loaded into the a latches. Next, the
stack is "popped" (SC ~ S8 ~ SA ~ PC), restoring the
saved value of PC to continue sequential program execution. Since LaiD pushes S8 ~ SC, the previous contents
of SC are lost.
Note: LaiD uses 2 instruction cycles if executed, one if skipped.
c. The ROM is organized into pages of 64 words each. The
Program Counter is a 11-bit binary counter, and will count
through page boundaries. If a JP, JSRP, JID, or LaiD is
the last word of a page, it operates as if it were in the next
page. For example: a JP located in the last word of a
page will jump to a location in the next page. Also, a JID
or LaiD located in the last word of every fourth page (Le.
hex address OFF, 1FF, 2FF, 3FF, 4FF, etc.) will access
data in the next group of four pages.
JID INSTRUCTION
Note: The COP424C/425C/426C needs only 10 bits to address its ROM.
Therefore, the eleventh bit (P10) is ignored.
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location pointed
to indirectly by A and M. It loads the lower 8 bits of the ROM
address register PC with the contents of ROM addressed by
the 11-bit word, PC10:8,A,M. PC10,PC9 and PC8 are not
affected by JID.
Power Dissipation
The lowest power drain is when the clock is stopped. As the
frequency increases so does current. Current is also lower
at lower operating voltages. Therefore, the user should run
at the lowest speed and voltage that his application will allow. The user should take care that all pins swing to full
supply levels to insure that outputs are not loaded down and
that inputs are not at some intermediate level which may
draw current. Any input with a slow rise or fall time will draw
additional current. A crystal or resonator generated clock
input will draw additional current. An RIC oscillator will draw
even more current since the input is a slow rising signal.
If using an external squarewave oscillator, the following
equation can be used to calculate operating current drain.
Note: If the most significant bit of the T counter is a 1 when a CAMT instruction loads the counter, the overflow flag will be set. The following
sample of codes should be used when loading the counter:
; load T counter
; skip if overflow flag is set and reset it
o
a"tJ
oI:ao
N
U1
o
.......
o
a"tJ
oI:ao
N
0)
o
.......
o
a"tJ
w
N
oI:ao
o
.......
o
a"tJ
w
N
U1
o
.......
o
a"tJ
w
N
SKT INSTRUCTION
The SKT (Skip On Timer) instruction tests the state of the T
counter overflow latch (see internal logic, above), executing
the next program instruction if the latch is not set. If the
latch has been set since the previous test, the next program
instruction is skipped and the latch is reset. The features
associated with this instruction allow the processor to generate its own time-base for real-time processing, rather than
relying on an external input signal.
SKT
o
.......
0)
Note: JID uses 2 instruction cycles if executed, one if skipped.
CAMT
oI:ao
N
oI:ao
Ico= 10+ VX40 x Fi + Vx 1400 x Fi/Dv
where Ico=chip operating current drain in microamps
quiescent leakage current (from curve)
NOP
CKI frequency in MegaHertz
IT INSTRUCTION
The IT (idle till timer) instruction halts the processor and
puts it in an idle state until the time-base counter overflows.
This idle state reduces current drain since all logic (except
the oscillator and time base counter) is stopped. IT instruction is not allowed if the T counter is mask-programmed as
an external event counter (option #31 = 1).
chip Vcc in volts
divide by option selected
For example at 5 volts Vcc and 400 kHz (divide by 4)
Ico=20+ 5X40X0.4+ 5X 1400X0.4/4
Ico=20+80+700=800 JJ-A
At 2.4 volts Vcc and 30 kHz (divide by 4)
Ico= 6+ 2.4 X40 XO.03 + 2.4X 1400XO.03/4
INIL INSTRUCTION
INIL (Input IL Latches to A) inputs 2 latches, IL3 and ILO,
CKO and 0 into A. The IL3 and ILO latches are set if a lowgoing pulse ("1" to "0") has occurred on the IN3 and INO
inputs since the last INIL instruction, provided the input
pulse stays low for at least two instruction cycles. Execution
of an INIL inputs IL3 and ILO into A3 and AO respectively,
Ico = 6 + 2.88 + 25.2 = 34.08 JJ-A
1-177
o
.......
o
a"tJ
oI:ao
oI:ao
oI:ao
o.......
o
a"tJ
oI:ao
oI:ao
U1
~II
"tJ
w
oI:ao
oI:ao
o
.......
o
a"tJ
w
oI:ao
U1
o
o
II)
~
C")
A.
o
o
"o~
~
Power Dissipation
(Continued)
If an IT instruction is executed, the chip goes into the IDLE
mode until the timer overflows. In IDLE mode, the current
drain can be calculated from the following equation:
c. Open Drain - An N-channel device to ground only, allowing external pull-up as required by the user's application.
d. Standard TAl-STATE L Output - A CMOS output buffer
similar to a. which may be disabled by program control.
Ici= la+VX40XFi
C")
A.
o
o
"oII)
~
~
e. Low-Current TAl-STATE L Output - This is the same as
d. above except that the sourcing current is much less.
For example, at 5 volts Vcc and 400 kHz
Ici=20+5X40XO.4= 100 /LA
f. Open-Drain TAl-STATE L Output nel device to ground only.
The total average current will then be the weighted average
of the operating current and the idle current:
All inputs have the following options:
A.
o
g. Input with on chip load device to Vcc.
o
To
Ita = Ico
o
"~
~
~
A.
where:
x To+Ti +
.
ICI
Ico = operating current
o"CD
To=operating time
N
o
o
o
"II)
N
C")
A.
o
o
o
"~
h. Hi-Z input which must be driven by the users logic.
When using either the G or L I/O ports as inputs, a pull-up
device is necessary. This can be an external device or the
following alternative is available: Select the low-current output option. Now, by setting the output registers to a logic
"1" level, the P-channel devices will act as the pull-up load.
Note that when using the L ports in this fashion the Q registers must be set to a logic "1" level and the L drivers MUST
BE ENABLED by an LEI instruction (see description above).
Ici = idle current
Ti = idle time
C")
A.
Ti
x To+Ti
Ita = total average current
o
o
This has the N-chan-
I/O OPTIONS
All output drivers use one or more of three common devices
numbered 1 to 3. Minimum and maximum current (lOUT and
VOUT) curves are given in Figure 12 for each of these devices to allow the designer to effectively use these I/O configurations.
Outputs have the following optional configurations, illustrated in Figure 11:
a. Standard - A CMOS push-pull buffer with an N-channel
device to ground in conjunction with a P-channel device
to Vcc, compatible with CMOS and LSTIL.
b. Low Current - This is the same configuration as a.
above except that the sourcing current is much less.
N
C")
A.
o
o
o
"CD
N
~
A.
o
o
c. Open-Drain Output
b. Low Current Push-Pull Output
a. Standard Push-Pull Output
o
"II)
N
~
A.
o
Vee
o
D~f.
o"
~
N
~
A.
o
o
d. Standard TRI-STATE "L" Output
Vee
e. Low Current TRI-STATE
"L"Output
f. Open Drain TRI-STATE
"L" Output
Vee
-d.-J1'3 -!-
..~":" 1
.4~
~~
..........
~
~
TL/DD/5259-14
h. HI-Z Input
g. Input with Load
FIGURE 11. Input/Output Configurations
1-178
o
Power Dissipation
o
-a
(Continued)
Minimum Sink Current
u.----r-"T'"""--,-.,--.,--,
1.2
2.0 '--+-+--+-;--1-:::-""1
1.0
1.6
'--+-+-~O::::-;---t--t
0.4
0.4
0.2
2.0
~L
3.0
4.0
5.0
-
§
a
-~
2.0
500
400 t---t----"'''k--+-;---t--t
400
t--',....,.....-t--+"~t--+-----1
lz
4.0
5.0
6.0
1.0
2.0
4.0
5.0
6.0
200 3.0V
100
~
o
o
w
0l:Io
Maximum Quiescent Current
i\
3.0
4.0
U1
40
\
~
5.0
o
6.0
85~
o
.......
/' ~
WC
o"'tJ
~V
-
~ ~ ~5°C
I
o
VOH (VOLTS)
VOH(VOLTS)
4
Vee (V)
TL/DD/5259-15
FIGURE 12. Input/Output Characteristics
Option 4: RESET input
=0: load device to Vee
= 1: Hi-Z input
The following is a list of options. The options are programmed at the same time as the ROM pattern to provide
the user with the hardware flexibility to interface to various
I/O components using little or no external circuitry.
Option 5: L7 Driver
=0: Standard TRI-STATE push-pull output
= 1: Low-current TRI-STATE push-pull output
=2: Open-drain TRI-STATE output
Option 6: L6 Driver - (same as option 5)
PLEASE FILL OUT THE OPTION TABLE on the next page.
Xerox the option data and send it in with your disk or
EPROM.
Option 7: L5 Driver -
(same as option 5)
Option 1 = 0: Ground Pin -
Option 8: L4 Driver -
(same as option 5)
no options available
Option 2: CKO Pin
= 0: load device to Vee
= 1: Hi-Z input
=1: HALT I/O port
=2: general purpose input with load device to Vee
Option 10: IN2 input -
= 3: general purpose input, high-Z
(same as option 9)
Option 11 = 0: Vee Pin - no option available
Option 12: L3 Driver - (same as option 5)
Option 3: CKI input
= 0: Crystal controlled oscillator input divide by 4
Option 13: L2 Driver -
(same as option 5)
= 1: Crystal controlled oscillator input divide by 8
(same as option 5)
(same as option 5)
= 2: Crystal controlled oscillator input divide by 16
Option 14: L 1 Driver Option 15: LO Driver -
=4: Single-pin RC controlled oscillator (divide by 4)
Option 16: SI input -
= 5: External oscillator input divide by 4
Option 17: SO Driver
(same as option 9)
= 6: External oscillator input divide by 8
= 0: Standard push-pull output
= 7: External oscillator input divide by 16
= 1: Low-current push-pull output
= 2: Open-drain output
1-179
W
I\,)
en
o
.......
o
o-a
0l:Io
0l:Io
0l:Io
o
.......
o
0l:Io
0l:Io
U1
~III
-a
w
0l:Io
0l:Io
o
.......
o
o-a
w
0l:Io
U1
o
Option 9: IN1 input
= 0: clock generator output to crystal/resonator
o
o-a
Option List
The COP444C/ 445C/ 424C/ 425C/COP426C mask-programmable options are assigned numbers which correspond with the COP444C/424C pins.
o
o
.......
o-a
u
u
~
~
2.0
o
o-a
w
I\,)
"
1.0
o
o-a
I\,)
80
1\,
200 ...--+--f--::llod--~-t--f
4.0
3.0
VOH (VOLTS)
t-- ,.......
100
o
.......
0l:Io
120
300
U1
en
o
.......
r\ l~
3.0
I\,)
I\,)
UV
9
9
3.0
i\.
COP344C/345C/324C/325C
Low Current Option
Maximum Source Current
500
2.0
9
VOH (VOLTS)
600
1.0
lz 30'--r-=~-r-~-r~
~ \
~~
1.0
(VOLTS)
COP444C/424C/445C/425C
Low Current Option
Maximum Source Current
300
0l:Io
3.0V
aw
6.0
o
o
.......
o-a
40~-+-~-1~~-+-~
""" '"
!. 0.6
4.5V
0.' t--IlfL-+---t--;--;-;
1.0
lz
-
0.11
!. 1.2 .--+~'t--±;;;;;1111""-1--t
0l:Io
5.5V
C
.....
9
I\,)
60.----r-"T'"""~-_r-r_-,
5.5V
c
0l:Io
Low Current Option
Minimum Source Current
Standard
Minimum Source Current
o
II)
C")
Option List
D-
Option 18: SK Driver -
(same as option 17)
o.......
Option 19: INO Input -
(same as option 9)
Option 20: IN3 Input -
(same as option 9)
~
Option 21: GO 1/0 Port -
(same as option 17)
D-
Option 22: G1 1/0 Port -
(same as option 17)
o
.......
o
II)
Option 23: G2 1/0 Port -
(same as option 17)
(1 k and 2K Microcontroller)
= 0: 28-pin package
(same as option 17)
= 1: 24-pin package
~
O
o
~
C")
O
~
~
D-
O
o.......
o
~
~
~
D-
O
(Continued)
Option 24: G3 1/0 Port Option 25: 03 Output -
(same as option 17)
Option 26: 02 Output -
(same as option 17)
Option 27: 01 Output Option 28: DO Output -
(same as option 17)
(same as option 17)
o
II)
N
24 and 28 pin version.
(1 K Microcontroller only)
= 3: 20-pin package
= 4: 28- and 20-pin package
= 1: No internal initialization logic
= 6: 28-, 24- and 20-pin package
= 1: Dual Clock. DO RC oscillator } (opt. # 28 must= 2)
= 2: Dual Clock. DO ext. clock input
Option 31: Timer
C")
= 2: Same die purchased in both
= 5: 24- and 20-pin package
N
D-
=1: Microbus (opt. #31 must=O)
Option 33: COP bonding
= 0: Normal operation
Option 30: Dual Clock
= 0: Normal operation
O
o
.......
=0: Normal
Option 29: Internal Initialization Logic
o
.......
oCD
Option 32: Microbus
Note:-if opt. #33=1 or 2 then opt. #9, 10, 19,20 and 32
must = O-if opt. #33=3,4,5 or 6 then opt. #9,10, 19,
20, 21, 22, 30 and 32 must = O.
= 0: Time-base counter
= 1: External event counter
C")
D-
O
o
.......
o
~
Option Table
The following option information is to be sent to National along with the EPROM .
N
OPTION DATA
C")
OPTION DATA
D-
O
o.......
oCD
OPTION
1 VALUE =
IS: GROUND PIN
OPTION 17 VALUE =
IS: SO DRIVER
OPTION
2 VALUE =
IS: CKO PIN
OPTION 18 VALUE =
IS: SK DRIVER
0
N
~
OPTION
3 VALUE =
IS: CKIINPUT
OPTION 19 VALUE =
IS: INO INPUT
O
o.......
OPTION
4 VALUE =
IS: RESET INPUT
OPTION 20 VALUE =
IS: IN3 INPUT
N
OPTION
5 VALUE =
IS: L(7) DRIVER
OPTION 21 VALUE =
IS: GO 1/0 PORT
OPTION
6 VALUE =
IS: L(6) DRIVER
OPTION 22 VALUE =
IS: G1 1/0 PORT
OPTION
7 VALUE =
IS: L(5) DRIVER
OPTION 23 VALUE =
IS: G2 1/0 PORT
OPTION
8 VALUE =
IS: L(4) DRIVER
OPTION 24 VALUE =
IS: G3 1/0 PORT
OPTION
9 VALUE =
IS: IN1 INPUT
OPTION 25 VALUE =
IS: 03 OUTPUT
OPTION 10 VALUE =
IS: IN2 INPUT
OPTION 26 VALUE =
IS: 02 OUTPUT
OPTION 11 VALUE =
IS: VCC PIN
OPTION 27 VALUE =
IS: 01 OUTPUT
OPTION 12 VALUE =
IS: L(3) DRIVER
OPTION 28 VALUE =
IS: DO OUTPUT
OPTION 13 VALUE =
IS: L(2) DRIVER
OPTION 29 VALUE =
IS: INT INIT LOGIC
OPTION 14 VALUE =
IS: L(1) DRIVER
OPTION 30 VALUE =
IS: DUAL CLOCK
OPTION 15VALUE =
IS: L(O) DRIVER
OPTION 31 VALUE =
IS: TIMER
OPTION 16 VALUE =
IS: SIINPUT
OPTION 32 VALUE =
IS: MICROBUS
OPTION 33 VALUE =
IS: COP BONDING
D-
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D-
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o.......
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~
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o
1-180
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.......
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COP440/COP441/COP442 and COP340/COP341/COP342
Single-Chip N-Channel Microcontrollers
General Description
Features
The COP440, COP441, COP442, COP340, COP341, and
COP342 Single-Chip N-Channel Microcontrollers are members of the COPSTM microcontrollers family, fabricated using N-channel, silicon gate MOS technology. These are
complete microcontrollers with all system timing, internal
logic, ROM, RAM, and I/O necessary to implement dedicated control functions in a variety of applications. Features
include single supply operation, various output configuration
options, and an instruction set, internal architecture, and
I/O scheme designed to facilitate keyboard input, display
output, and data manipulation. The COP440 is a 40-pin chip
and the COP441 is a 28-pin version of the same circuit (12
I/O lines removed). The COP442 is a 24-pin version (4 more
input lines removed). The COP340, COP341, COP342 are
functional equivalents of the above devices respectively, but
operate with an extended temperature range (-40°C to
+ 85°C). Standard test procedures and reliable high-density
fabrication techniques provide the medium to large volume
customers with a customized controller oriented processor
at a low end-product cost.
•
•
•
•
•
•
•
•
•
II
•
•
•
•
•
•
•
o"'tJ
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.......
o
o"'tJ
Enhanced, more powerful instruction set
2k x 8 ROM, 160 x 4 RAM
35 I/O lines (COP440)
Zero-crossing detect circuitry with hysteresis
True multi-vectored interrupt from 4 selectable sources
(plus restart)
Four-level subroutine stack (in RAM)
4 ,.,.s cycle time
Single supply operation (4.5V-6.3V)
Programmable time-base counter
Internal binary counter/register with MICROWIRETM
compatible serial I/O
General purpose and TRI-STATE® outputs
TTL/CMOS compatible in and out
LED drive capability
MICROBUSTM compatible
Software/hardware compatible with other members of
the COP400 family
Extended temperature range
devices COP340,
COP341, COP342 (- 40°C to + 85'C)
Compatible dual CPU device available
(COP2440 series)
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.......
o
o"'tJ
W
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C
.......
o
o"'tJ
W
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.....
o
.......
o
"'tJ
W
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Block Diagram
CKI
VCC
CKO
•
OJ
02
01
Do
~
"j
SO
IIICRDWIRE
SI
INJ 7
INZ J7
INI J6
INO
GJ
Gz
GI
6
Go
TL/DD/6926-1
FIGURE 1
1-181
C\I
~
C")
D-
oo
......
....
~
C")
D-
O
o
......
o
~
C")
D-
O
o
......
C\I
COP440/COP441/COP442
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage at Zero-Crossing Detect Pin
Relative to GND
-1.2Vto +15V
Voltage at Any Other Pin
Relative to GND
-0.5Vto +7V
Ambient Operating Temperature
O°Cto +70°C
Ambient Storage Temperature
Lead Temperature (Soldering, 10 sec.)
Power Dissipation
300°C
0.75W at 25°C
O.4Wat 70°C
Total Source Current
150mA
75mA
Total Sink Current
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
~
~
D-
O
o
......
....
~
~
DC Electrical Characteristics O°C s; TA s;
Parameter
+ 70°C, 4.5V s; Vee s; 6.SV unless otherwise noted
Conditions
Min
Max
Units
6.3
V
0.4
V
D-
Operating Voltage (Ved
(NoteS)
o
......
Power Supply Ripple
(Peak to Peak)
Operating Supply Current
(All Inputs and Outputs Open)
TA = O°C
TA = 25°C
TA = 70°C
44
35
27
mA
mA
mA
S.O
2.0
-0.3
0.4
V
V
V
0.7 Vee
-0.3
0.6
V
V
0.7 Vee
-0.3
0.6
V
V
O
o
~
~
D-
O
o
Input Voltage Levels
CKllnput Levels
Crystal Input (+ 16, + 8)
Logic High (VIH)
Logic High (VIH)
Logic Low (VIU
Schmitt Trigger Input (+ 4)
Logic High (VIH)
Logic Low (VIU
RESET Input Levels
Logic High
Logic Low
Zero-Crossing Detect Input
Trip Point
Logic High (VIH) Limit
Logic Low (VIU Limit
SO Input Level (Test Mode)
All Other Inputs
Logic High
Logic High
Logic Low
Input Levels High Trip Option
Logic High
Logic Low
Vee
Vee
4.5
= Max
= 5V ±5%
(Schmitt Trigger Input)
See Figure 7
-0.15
Vee
Vee
2.5
V
V
V
V
S.O
2.0
-0.3
0.8
V
V
V
S.6
-0.3
1.2
V
V
7.0
pF
-0.8
2.0
(Note 5)
= Max
= 5V ±5%
Input Capacitance
0.15
12
-1.0
Hi-Z Input Leakage
+1.0
,..,A
Note 1: Duty Cycle = tWI/(tWI + two).
Note 2: See Figure for additional I/O Characteristics.
Note 3: Vee voltage change must be less than 0.5V in a 1 ms period to maintain proper operation.
Note 4: Exercise great care not to exceed maximum device power dissipation limits when direct-driving LEOs (or sourcing similar loads) at high temperature.
Note 5: SO output "0" level must be less than O.BV for normal operation.
1-182
o
o
COP440/COP441/COP442
DC Electrical Characteristics o·c ~ TA ~
Parameter
Output Voltage Levels
Standard Output
TTL Operation
Logic High (VOH)
Logic Low (VOU
CMOS Operation (Note 1)
Logic High (VOH)
Logic Low (Vou
Output Current Levels
Standard Output Source Current
LED Direct Drive Output
Logic High (IOH)
TRI·STATE Output Leakage Current
CKO Output
Oscillator Output Option
Logic High
Logic Low
VR RAM Power Supply Option
Supply Current
CKI Sink Current (RC Option)
-a
+ 70·C, 4.5V ~ Vee ~ 6.3V unless otherwise noted (Continued)
Conditions
Min
Max
Units
o-a
0l:Io
0l:Io
IOH = -100 JLA
IOL = 1.6 mA
IOH
IOL
= -10 JLA
= 10 JLA
......
......
o
0.4
V
V
o-a
V
V
......
0.2
-100
-650
JLA
Q
......
-2.5
-2.5
-17
+2.5
mA
/J- A
2.4
Vee - 0.4
0l:Io
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N
o
o-a
w
Vee
Vee
= 4.5V, VOH = 2.4V
= 6V, VOH = 2V
VOH = 2V
VOL = O.4V
VR = 3.3V
VIH = 3.5V, Vee
-0.2
0.4
mA
mA
3.0
mA
mA
4.6
230
kO
JLA
Total Sink Current Allowed
All 1/0 Combined
Each L, R Port
Each 0, G, H Port
SO,SK
75
20
10
2.5
mA
mA
mA
mA
Total Source Current Allowed
All 1/0 Combined
L Port
Lr L4
L3-Lo
Each L Pin
All Other Output Pins
150
120
70
70
23
1.6
mA
mA
mA
mA
mA
mA
Input Current Levels
Zero·Crossing Detect Input
Resistance
Input Load Source Current
0l:Io
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Q
......
o
VIH
VIH
= 4.5V
2.0
= 1.0V
= 2.0V, Vee = 4.5V
0.9
14
Note 1: TAI·STATE and LED configurations are excluded.
1·183
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......
......
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N
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a.
oo
......
,....
COP340/COP341/COP342
Absolute Maximum Ratings
a.
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Dissipation
......
Voltage at Zero-Crossing Detect Pin
Relative to GND
Total Source Current
Total Sink Current
~
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oo
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~
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a.
oo
......
N
~
~
a.
o
......
o
,....
Lead Temperature (Soldering, 10 sec.)
-1.2Vto +15V
Voltage at Any Other Pin
Relative to GND
Ambient Storage Temperature
-40°C to + 85°C
-65°C to + 150°C
DC Electrical Characteristics
150mA
75mA
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
-0.5Vto +7V
Ambient Operating Temperature
300°C
0.75W at 25°C
0.25W at 85°C
-40°C ~ TA ~ + 85°C, 4.5V ~ Vee ~ 5.5Vunless otherwise noted
Parameter
Conditions
Min
Max
4.5
Units
~
~
Operating Voltage (Vee)
(Note 3)
5.5
V
oo
Power Supply Ripple
(Peak to Peak)
0.4
V
Operating Supply Current
(All Inputs and Outputs Open)
TA = -40°C
TA = 25°C
TA = 85°C
54
35
25
mA
mA
mA
3.0
2.2
-0.3
0.3
V
V
V
0.7 Vee
-0.3
0.4
V
V
0.7 Vee
-0.3
0.4
V
V
a.
......
o
~
~
a.
o
o
Input Voltage Levels
CKllnput Levels
Crystal Input (..;- 16, ..;- 8)
Logic High (VIH)
Logic Low (VII)
Schmitt Trigger Input (..;- 4)
Logic High (VIH)
Logic Low (VIU
RESET Input Levels
Logic High
Logic Low
Zero-Crossing Detect Input
Trip Point
Logic High (VIH) Limit
Logic Low (VIU Limit
SO Input Level (Test Mode)
All Other Inputs
Logic High
Logic Low
Input Levels High Trip Option
Logic High
Logic Low
Vee
= Max
(Schmitt Trigger Input)
See Figure 7
-0.15
(Note 5)
Vee = Max
-0.8
2.2
3.0
2.2
-0.3
0.6
V
V
V
V
V
V
V
3.6
-0.3
1.2
V
V
7.0
pF
-2.0
+2.0
IlA
Input Capacitance
Hi-Z Input Leakage
Note 1: Duty Cycle = tWI/(tWI
+
0.15
12
2.4
two).
Note 2: See Figure for additional I/O Characteristics.
Note 3: Vee voltage change must be less than 0.5V in a 1 ms period to maintain proper operation.
Note 4: Exercise great care not to exceed maximum device power dissipation limits when direct-driving LEOs (or sourcing similar loads) at high temperature.
Note 5: SO output "0" level must be less than 0.6V for normal operation.
1-184
o
a"'0
COP340/COP341/COP342
DC Electrical Characteristics
0l:Io
0l:Io
o
......
-40·C ~ TA ~ + 85·C, 4.5V ~ Vee ~ 5.5V unless otherwise noted (Continued)
Parameter
Output Voltage Levels
Standard Output
TIL Operation
Logic High (VOH)
Logic Low (Vou
CMOS Operation (Note 1)
Logic High (VOH)
Logic Low (Vou
Output Current Levels
Standard Output Source Current
LED Direct Drive Output
Logic High (lOH)
TAl-STATE Output Leakage Current
CKOOutput
Oscillator Output Option
Logic High
Logic Low
VA AAM Power Supply Option
Supply Current
CKI Sink Current (AC Option)
Input Current Levels
Zero-Crossing Detect Input
Aesistance
Input Load Source Current
Max
Units
a"'0
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-A.
......
o
IOH
IOL
=
=
IOH
IOL
=
=
Vee
Vee
VOH
2.4
-100 p.A
1.6mA
-10 p.A
10 p.A
0.4
V
V
0.2
V
V
-100
-800
p.A
-1.5
-5.0
-15
+5.0
mA
p.A
Vee - 0.5
= 4.5V, VOH =
= 5V (Note 4)
= 2V
2.4V
a"'0
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0l:Io
N
......
o
a"'0
w
0l:Io
o
......
o
a"'0
W
0l:Io
-A.
......
o
VOH
VOL
= 2V
= 0.4V
VA = 3.3V
Vee = 4.5V, VIH
VIH
VIH
=
=
1.0V
2.0V, Vee
Total Sink Current Allowed
All I/O Combined
Each L, A Port
Each 0, G, H Port
SO,SK
Total Source Current Allowed
All I/O Combined
L Port
L7- L4
L3-Lo
Each L Pin
All Other Output Pins
Note 1:
o
Min
Conditions
TRI·STATE and LED configurations are excluded.
1-185
-0.2
0.4
=
3.5V
2.0
=
4.5V
0.9
14
mA
mA
4.0
mA
mA
4.6
280
kn
p.A
75
20
10
2.5
mA
mA
mA
mA
150
120
70
70
23
1.6
mA
mA
mA
mA
mA
mA
a"'0
w
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N
C'I
~
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D-
o
o
.......
.,..
~
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D-
O
o
.......
o
AC Electrical Characteristics
COP440/COP441 ICOP442: O'C ~ TA ~
+ 70'C, 4.5V ~
COP340/COP341/COP342: - 40'C ~ TA ~
Instruction Cycle Time-tE
CKI Frequency
+ 16 Mode
+8 Mode
+4 Mode
fl = 4 MHz
fl = 4 MHz External Clock
fl = 4 MHz External Clock
+4 Mode
R = 15kn ±5%,C = 100pF ±10%
~
O
o
.......
C'I
~
~
D-
O
o
.......
.,..
Duty Cycle (Note 1)
Rise Time
Fall Time
CKI Using RC (Figure ge)
Frequency
Instruction Execution Time-tE
(Note 1)
0-
INPUTS: (Figure 4)
SI
tSETUP
tHOLO
All Other Inputs
tSETUP
tHOLO
o
OUTPUT PROPAGATION DELAY
~
~
0-
oo
.......
o
~
~
o
5.5V unless otherwise noted
Conditions
Parameter
C")
D-
Vee ~ 6.3V unless otherwise noted
+ 85'C, 4.5V ~ Vee ~
Test Condition:
CL = 50 pF, VOUT
CKO
tpd1, tpdO
tpd1, tpdO
SO,SK
tpd1, tpdO
All Other Outputs
Min
Max
Units
4.0
1.6
0.8
0.4
30
10
4.0
2.0
1.0
60
60
40
p,s
MHz
MHz
MHz
%
ns
ns
0.5
4.0
1.0
8.0
MHz
p,s
0.3
300
p,s
ns
1.7
300
p,s
ns
= 1.5V
Crystal Input
Schmitt Trigger Input
0.17
0.3
p,s
p,s
= 2.4 kn
= 5.0 kn
CL = 100 pF, Vee = 5V ±5%
1.0
1.4
p,s
p,s
375
250
ns
ns
ns
ns
ns
700
ns
ns
ns
ns
ns
ns
RL
RL
MICROBUS TIMING
Read Operation (Figure 2a)
Chip Select Stable Before RD-teSR
Chip Select Hold Time for RD-tRes
RD Pulse Width-tRR
Data Delay from RD-tRO
RD to Data Floating-tOF
Write Operation (Figure 2b)
Chip Select Stable Before WR-tesw
Chip Select Hold Time for WR-twes
WR Pulse Width-tww
Data Set-Up Time for WR-tow
Data Hold Time for WR-two
INTR Transition Time from WR-tWI
TRI-STATE Outputs
65
20
400
65
20
400
320
100
Note 1: Variation due to the device included.
1
_IRR
_IRCs:::j
, r - - _!----------"1..__________
..J
\
-ICSR .... I-IRO-~
Il7-LO)
07- 00
10F
TL/DD/6926-2
FIGURE 2a. MICROBUS Read Operation Timing
\
Icsw .... _ 1 W W - - - . 1 -lWcs-1
/1-----
I"--~----~------IO-W-----~----""I
1_-------
- 1W0.1-
IL7-LO)
IGO)
--+__"""____~-~'I""-----
07-00 _ _ _ _ _ _
INTR
-1W1====i'--_______
FIGURE 2b. MICROBUS Write Operation Timing
1-186
TLlDD/6926-3
o
o"a
Connection Diagrams
0l:Io
0l:Io
Dual-In-Llne Package
Ll
LO
SI
o
........
Vee
L2
L3
IN2
INI
L4
L5
L6
L7
RO
Rl
R2
R3
R4
R5
R6
R7
so
SK
INO
IN3
GO
Gl
G2
G3
HO
HI
H2
H3
D3
D2
Dl
DO
GND
o
Dual-In-Llne Package
Dual-ln·L1ne Package
GND
CKO
CKI
Rrnf
L7
L6
L5
U
INI
IN2
Vec
L3
L2
Ll
limT
14
Top View
Order Number COP440-XXX/D or
COP340-XXX/D
See NS Hermetic Package Number
D40C
Order Number COP440-XXX/N or
COP340-XXX/N
See NS Molded Package Number
N40A
GND
CKO
CKI
24
23
22
21
20
COP4421 19
COP342
18
IImT
L7
L6
L5
L4
VCC
L3
L2
L1
17
16
15
14
13
10
11
12
DO
Dl
D2
D3
G3
G2
Gl
GO
SK
sa
SI
La
TL/DD/6926-6
CKI
CKD
TL/DD/6926-4
15
DO
Dl
D2
D3
G3
G2
Gl
GO
IN3
INO
SK
SO
SI
LO
TlIDD/6926-5
Top View
Order Number COP441-XXX/D or
COP341-XXX/D
See NS Hermetic Package Number
D28C
Order Number COP441-XXX/N or
COP341-XXX/N
See NS Molded Package Number
N28B
o"a
0l:Io
0l:Io
""""
........
o
o
"a
0l:Io
0l:Io
N
........
o
o"a
(,.)
0l:Io
o
........
o
o"a
(,.)
0l:Io
""""
........
Top View
Order Number COP442-XXX/D or
COP342-XXX/D
See NS Hermetic Package Number
D24C
Order Number COP442-XXX/N or
COP342-XXX/N
See NS Molded Package Number
N24A
o
o"a
(,.)
0l:Io
N
FIGURE 3
Pin Descriptions
Pin
L7-Lo
Description
Pin
8-bit Bidirectional 110 Port with TRI·STATE
CKI
Description
System Oscillator Input
G3-GO 4-bit Bidirectional 1/0 Port
CKO
03-00 4-bit General Purpose Output Port
IN3-INo 4-bit General Purpose Input Port (Not Available on
COP442/COP342)
Vee
Power Supply
SI
Serial Input
GNO
Ground
SO
Serial Output (or General Purpose Output)
H3-HO
SK
Logic-Controlled Clock (or General Purpose Output)
R7-RO
4·bit Bidirectional 1/0 Port (COP440/COP340
Only)
8-Bit Bidirectional 1/0 Port with TRI-STATE
(COP440/COP340 Only)
System Oscillator Output (or General Purpose Input or RAM Power Supply)
RESET System Reset Input
Timing Diagram
TL/DD/6926-7
FIGURE 4. Input/Output Timing Diagrams (Divide by 16 Mode)
1-187
II
N
~
C")
D..
o
o........
"t~
C")
D..
o
o........
o
~
C")
D..
oo
........
N
~
~
D..
o
o
........
"t~
~
D..
oo
........
o
~
~
D..
o
o
Functional Description
The block diagram of the COP440 is shown in Figure 1.
Data paths are illustrated in simplified form to depict how
the various logic elements communicate with each other in
implementing the instruction set of the device. Positive logic
is used. When a bit is set, it is a logic "1" (greater than
2.0V). When a bit is reset, it is a logic "0" (less than 0.8V).
The 8-bit T counter is a binary up counter which can be
loaded to and from M and A. The input to this counter is
software selectable from two sources: the first coming from
a divide-by-four prescaler (from instruction cycle frequency)
thus providing a 10-bit time base counter; the second coming from IN2 input, changing the T counter into an 8-bit external event counter (see EN register below). In this mode, a
low-going pulse ("1" to "0") of at least 2 instruction cycles
wide will increment the counter. When the counter overflows, an overflow flag will be set (see SKT instruction below) and an interrupt signal will be sent to processor X. The
T counter is cleared on reset.
PROGRAM MEMORY
Program Memory consists of a 2,048 byte ROM. As can be
seen by an examination of the COP440 instruction set,
these words may be program instructions, constants, or
ROM addressing data. Because of the special characteristics associated with the JP, JSRP, JID, LQID, and LID instructions, ROM must often be thought of as being organized into 32 pages of 64 words each.
Four general-purpose inputs, IN3-INa, are provided; IN1,
IN2 and IN3 may be selected, by a mask-programmable option, as Read Strobe, Chip Select, and Write Strobe inputs,
respectively, for use in MICROBUS applications; IN1, byanother mask-programmable option, can be selected as a true
zero-crossing detector with the output triggering an interrupt
or being interrogated by an instruction. These two maskprogrammable options are mutually exclusive .
The D register provides 4 general-purpose outputs and is
used as the destination register for the 4-bit contents of Bd.
ROM addressing is accomplished by an 11-bit PC register.
Its binary value selects one of the 2,048 8-bit words contained in ROM. A new address is loaded into the PC register
during each instruction cycle. Unless the instruction is a
transfer of control instruction, the PC register is loaded with
the next sequential 11-bit binary count value.
ROM instruction words are fetched, decoded and executed
by the Instruction Decode, Control and Skip Logic circuitry.
The G register contents are outputs to a 4-bit general-purpose bidirectional 1/0 port. Ga may be mask-programmed
as an output for MICROBUS applications.
The H register contents are outputs to a 4-bit general-purpose bidirectional 1/0 port.
The Q register is an internal, latched, 8-bit register, used to
hold data loaded to or from M and A, as well as 8-bit data
from ROM. Its contents are outputted to the L 1/0 ports
when the L drivers are enabled under program control. With
the MICROBUS option selected, Q can also be loaded with
the 8-bit contents of the L 1/0 ports upon the occurrence of
a write strobe from the host CPU. Note that unlike most
other COPS controllers, Q is cleared on reset.
The 8 L drivers, when enabled, output the contents of
latched Q data to the L 1/0 ports. Also, the contents of L
may be read directly into A and M. As explained above, the
MICROBUS option allows L 1/0 port data to be latched into
the Q register. The L 1/0 port can be directly connected to
the segments of a multiplexed LED display (using the LED
Direct Drive output configuration option) with Q data being
outputted to the Sa-Sg and decimal point segments of the
display.
The R register, when enabled, outputs to an 8-bit generalpurpose, bidirectional, 1/0 port.
DATA MEMORY
Data memory consists of a 640-bit RAM, organized as 10
data registers of 16 4-bit digits. RAM addressing is implemented by an 8-bit B register whose upper 4 bits (Br) select
1 of 10 (0-9) data registers and lower 4 bits (Bd) select 1 of
16 4-bit digits in the selected data register. While the 4-bit
contents of the selected RAM digit (M) is usually loaded
into, or from, or exchanged with the A register (accumulator), it may also be loaded into or from the Q latches, L port,
R port, EN register, and T counter (internal time base counter). RAM may also be loaded from 4 bits of a ROM word.
RAM addressing may also be performed directly to the lower 8 registers by the LDD and XAD instructions based upon
the 7-bit contents of the operand field of these instructions.
The Bd register also serves as a source register for 4-bit
data sent directly to the D outputs. RAM register 8 (Br = 8)
also serves as a subroutine stack. Note that it is possible,
but not recommended, to alter the contents of the stack by
normal data memory access commands.
INTERNAL LOGIC
The 4-bit A register (accumulator) is the source and destination register for most 1/0 arithmetic, logic, and data memory
access operations. It can also be used to load the Br and Bd
portions of the B register, N register, to load and input 4 bits
of the 8-bit Q latch, EN register, or T counter, to input 4 bits
of a ROM word, L or R 1/0 port data, to input 4-bit G, H, or
IN ports, and to perform data exchanges with the SIO register. The accumulator is cleared upon reset.
The SIO register functions as a 4-bit serial-in/serial-out shift
register for MICROWIRE 1/0 and COPS peripherals, or as a
binary counter (depending on the contents of the EN register; see EN register description, below). Its contents can be
exchanged with A, allowing it to input or output a continuous
serial data stream.
A 4-bit adder performs the arithmetic and logic functions of
the COP440, storing its results in A. It also outputs a carry
bit to the 1-bit C register, most often employed to indicate
arithmetic overflow. The C register, in conjunction with the
XAS instruction and the EN register, also serves to control
the SK output. C can be outputted directly to SK or can
enable SK to be a sync clock each instruction cycle time.
(See XAS instruction and EN register description, below).
The XAS instruction copies the C flag into the SKL latch. In
the counter mode, SK is the output of SKL; in the shift register mode, SK outputs SKL ANDed with the instruction cycle
clock.
The 2-bit N register is a stack pointer to the data memory
register 8 where the subroutine return address is located. It
points to the next location where the address may be stored
1-188
o
Functional Description
o""tJ
(Continued)
and increments by 1 after each push of the stack, and decrements by 1 before each pop. The N register can be accessed by exchanging its value with A and is cleared on
reset. The stack is 4 addresses deep, 12 bits wide, and
does not check for overflow or empty conditions. The RAM
digit locations where the addresses are stored are shown in
Figure 5. The LSBs of the addresses are at digits 0, 4, 8,
and 12. The MSBs of digits 2, 6, 10, and 14 contain an
interrupt status bit (see Interrupt description, below). The
four unused digits (3, 7, 11, and 15) can be used as general
data storage. When a subroutine call or interrupt occurs, an
11-bit return address and an interrupt status bit are stored in
the stack. The N register is then incremented. When a RET
or RETSK instruction is executed, the N register is decremented and then the return address is fetched and loaded
into the program counter. The address and interrupt status
bits remain in the stack, but will be overwritten when the
next subroutine call or interrupt occurs.
1. With EN1 set, interrupt is enabled with EN4 and ENs selecting the interrupt source. Immediately following an interrupt, EN1 is reset to disable further interrupts.
2. With EN2 set, the L drivers are enabled to output the data
in Q to the L 1/0 port. Resetting EN2 disables the L drivers, placing the L 1/0 port in a high-impedance input
state. A special feature of the COP440 and COP441 is
that the MICROBUS option will change the function of
this bit to disable any writing into Go when EN2 is set.
3. EN3, in conjunction with ENo, affects the SO output. With
ENo set (binary counter option selected) SO will output
the value loaded into EN3. With ENo reset (serial shift
register option selected), setting ENs enables SO as the
output of the SIO shift register, outputting serial shifted
data each instruction time. Resetting EN3 with the serial
shift register option selected disables SO as the shift register output; data continues to be shifted through SIO and
can be exchanged with A via an XAS instruction but SO
remains set to "0". Table I below provides a summary of
the modes associated with EN3 and ENo.
DIGITS NOT USED IN STACK
4. ENs and EN4 select the source of the interrupt signal.
DATA
MEMORY
REGISTER 8
5. The possible sources are as follows:
TL/DD/6926-8
~
~
....
........
o
o""tJ
~
~
N
........
o
o""tJ
CI.)
~
C)
........
o
o
""tJ
CI.)
....
........
~
o
o""tJ
~
N
6. With EN6 set, the internal 8-bit T counter will use IN2 as
FIGURE 5. Subroutine Return Address
Stack Organization
The EN register in an internal 8-bit register loaded under
program control by the LEI instruction (lower 4 bits) or by
the CAME instruction. The state of each bit of this register
selects or deselects the particular feature associated with
each bit of the EN register.
its input. With EN6 reset, the input to the T counter is the
output of a divide by four prescaler (from instruction cycle
frequency), thus providing a 10-bit time-base counter.
7. With EN7 set, the R outputs are enabled; if EN7
= 0, the
R outputs are disabled.
INTERRUPT
O. The least significant bit of the enable register, ENo, se-
The following features are associated with the interrupt procedure and protocol and must be considered by the programmer when utilizing interrupts.
lects the SIO register as either a 4-bit shift register or a 4bit binary counter. With ENo set, SIO is an asynchronous
binary counter, decrementing its value by one upon each
low-going pulse ("1" to "0") occurring on the SI input.
Each pulse must be at least two instruction cycles wide.
SK outputs the value of SKL. The SO output is equal to
the value of EN3. With ENo reset, SIO is a serial shift
register left shifting 1 bit each instruction cycle time. The
data present at SI goes into the least significant bit of
SIO. SO can be enabled to output the most significant bit
of SIO each cycle time. The SK output becomes a logiccontrolled clock.
a. The interrupt, once acknowledged as explained below,
pushes the next sequential program counter address
(PC + 1) together with an interrupt status bit, onto the program counter stack residing in data memory. Any previous contents at the bottom of the stack are lost. The
program counter is set to hex address OFF (the last word
of page 3) and EN1 is reset. If EN4 is reset, the next
program address is hex 100; if EN4 is set, the next program address is hex 300; thus providing a different interrupt location for different interrupt sources.
TABLE I. Enable Register Modes - Bits EN3 and ENo
SIO
o
o""tJ
CI.)
EN4
Interrupt Source
o 0 IN1 (low-going pulse)
o
1
CKO input (if mask-programmed as an input)
0
Zero-crossing (or IN1 level transition)
1
1
1
T counter overflows
EN4 determines the interrupt routine location.
ENs
DIGIT
~
~
C)
........
EN3
ENo
SI
SO
0
0
Shift Register
Input to Shift Register
0
1
0
Shift Register
Input to Shift Register
Serial Out
0
1
Binary Counter
Input to Binary Counter
0
1
1
Binary Counter
Input to Binary Counter
1
1-189
SK
=
=
If SKL =
If SKL =
If SKL =
If SKL =
If SKL =
If SKL =
If SKL
If SKL
1, SK
0, SK
1, SK
0, SK
1, SK
0, SK
1, SK
0, SK
=
=
=
=
=
=
=
=
Clock
0
Clock
0
1
0
1
0
•
N
-.::t
C")
a..
o
CJ
.......
.....
-.::t
C")
a..
o
CJ
.......
o
-.::t
C")
a..
o
CJ
.......
N
-.::t
it
o
CJ
.......
.....
-.::t
-.::t
a..
o
CJ
.......
o
-.::t
-.::t
a..
o
CJ
Functional Description
(Continued)
will cause Q latch data to be enabled to the L ports for input
to the ""P. IN2 becomes CS-a logic "0" on this line selects
the COPS processor as the ""p peripheral device by enabling the operation of the RD and WR lines and allows for
the selection of one of several peripheral components. IN3
becomes WR-a logic "0" on this line will write bus data
from the L ports to the Q latches for input to the COPS
processor. Go becomes INTR, a "ready" output, reset by a
write pulse from the ""p on the WR line, providing the
"handshaking" capability necessary for asynchronous data
transfer between the host CPU and the COPS processor.
Go output can be separated from other G outputs by the
EN2 bit (see EN description above).
.. b. An interrupt will be acknowledged only after the following
conditions are met:
1. EN1 has been set.
2. For an external interrupt input, the signal pulse must be
at least two instruction cycles wide_
3. A currently executing instruction has been completed .
4. All successive transfer of control instructions and successive LBls have been completed (e.g., if the main
program is executing a JP instruction which transfers
program control to another JP instruction, the interrupt
will not be acknowledged until the second JP instruction has been executed.
c. The instruction at hex address OFF must be a NOP.
This option has been designed for compatibility with National's MICROBUS-a standard Interconnect system for S-bit
parallel data transfer between MOS/LSI CPUs and interfacing devices. (See MICROBUS National Publication.) The
functional and timing relationships between the COPS processor signal lines affected by this option are as specified for
the MICROBUS interface, and are given in the AC electrical
characteristics and shown in the timing diagrams (Figure 2).
Connection of the COP440 to the MICROBUS is shown in
Figure 6.
d. A CAME or LEI instruction may be put immediately before
the RET instruction to re-enable interrupts.
e. If the interrupt signal source is being changed, the interrupt must be disabled prior to, or at, the same time with
the change to avoid false interrupts. An interrupt may be
enabled only if the interrupt source is not changing. A
sample code for changing the interrupt source and enabling the interrupt is as follows:
CAME
; disable interrupt & alter interrupt source
5MB 1
; set interrupt enable bit
CAME
; enable interrupt
1. An interrupt status bit is stored together with the return
address in the stack. The status bit is set if an interrupt
occurs at a point in the program where the next instruction
is to be skipped; upon returning from the interrupt routine,
this set status bit will cause the next instruction to be
skipped. Subroutine and interrupt nesting inside interrupt
routines are allowed. Note that this differs from the
COP420/420C/420Ll444L series.
Note: TRI-STATE outputs must be used on L port.
ZERO-CROSSING DETECTION
(not available on the COP442, COP342)
The following features are associated with the IN1 pin: ININ
and INIL instructions input the state of IN1 to A1; IN1 interrupt generates an interrupt pulse when a low-going transition ("1" to "0") occurs on IN1; zero-crossing interrupt
generates an interrupt pulse when an IN1 transition occurs
(both "1" to "0" and "0" to "1 ").
If the zero-crossing detector is mask-programmed in (see
Figure 7a), the INIL instruction and zero-crossing interrupt
will input the state of IN1 through the true zero-crossing
detector ("1" if input> OV, "0" if input < OV). The IN IN
instruction and IN1 interrupt will then have unique logic
HIGH and LOW levels depending on the IN port input level
chosen. If normal (TTL) level is chosen, logic HIGH level is
3.0V (3.3V for COP340/341) and logic LOW level is O.SV
MICROBUS INTERFACE
(not available In COP442, COP342)
The COP440 series has an option which allows them to be
used as peripheral microprocessor devices, inputting and
outputting data from and to a host microprocessor (""P). IN1,
IN2 and IN3 general purpose inputs become MICROBUScompatible read-strobe, chip-select, and write-strobe lines,
respectively. IN1 becomes RD-a logic "0" on this input
INTERRUPT (lNTR)
MICROPROCESSOR ~~~~~.....
IN
OUT
H3- Ha
mET
TLIOO/6926-9
FIGURE 6. MICROBUS Option Interconnect
1-190
o
Functional Description
o
(Continued)
"'0
.a::a.
.a::a.
IN IN
..L.
o
......
o
f\f\
RS
o"'0
IN1 INTERRUPT
EN5.EN4 - DOl
NEGATIVE EDGE)
I
V\)
.a::a.
.a::a.
......
......
o
ZERD·CRDSSING INTERRUPT
EN5.EN4 -101
POSITIVE «. NEGATIVE EDGE)
o"tJ
I
TL/DD/6926-10
·Note: This Input has a different set of logic HIGH and LOW levels; see above description.
.a::a.
.a::a.
N
......
o
o"'0
a. Zero-CrossIng Detect LogIc OptIon
w
o
......
IN IN
..L.
.a::a.
o
o"'0
IN1 INTERRUPT
(EN5.EN4 a 001
(NEGATIVE EDGE)
w
.a::a.
......
......
o
ZERO·CROSSING INTERRUPT
(EN5.EN4=101
(POSITIVE «. NEGATIVE EDGE)
o"'0
w
TL/DD/6926-11
.a::a.
b. IN, wIthout Zero-CrossIng Detect LogIc
N
FIGURE 7. IN, Mask-Programmable Options
(0.6V for COP340/341); if high trip level is chosen, logic
HIGH level is 5.4V and logic LOW level is 1.2V. If the zero·
crossing detector is not mask·programmed in (see Figure
7b), IN1 will have logic HIGH and LOW levels that are defined for the IN port (see option list).
P
o
+ - ....-41.......- - - - ,
w
VCC
R
COP44D
E
S
U
P
The zero-crossing detector input contains a small hysteresis
(50 mV typical) to eliminate signal noise, and is not a high
impedance input but contains a resistive load to ground.
Since this input can withstand a voltage range of - O.BV to
+ 12V, an external clamping diode is needed for most input
signals, as shown in Figure 7a, to limit the voltage below
ground. An external resistor, Rs may be needed for the fol·
lowing two cases:
"""'--1 RESET
P
GND
L
Y
RC
~
5 x power supply rise time
TL/DD/6926-12
FIGURE 8. Power-Up Clear CircuIt
OSCILLATOR
There are three basic clock oscillator configurations available, as shown by Figure 9.
a. Input signal exceeds 12V; Rs and the internal resistor act
as a voltage divider to reduce the voltage at the input pin
to below 12V.
a. Crystal Controlled Oscillator. CKI and CKO are con·
nected to an external crystal. The cycle frequency equals
the crystal frequency divided by 16 (optional by 8). Thus a
4 MHz crystal with the divide-by·16 option selected will
give a 250 kHz cycle frequency (4 J.l.s instruction cycle
time).
b. Signal comes from a low impedance source; when the
voltage at the pin is clamped to -0.7V by the forward
bias voltage of an external diode, Rs limits the current
going through the diode.
b. External Oscillator. CKI is an external clock input signal.
The external frequency is divided by 16 (optional by 8 or
4) to give the cycle frequency. If the divide-by-4 option is
selected, the CKI input level is the Schmitt-trigger level.
CKO is now available to be used as the RAM power supply (VR) or as a general purpose input.
INITIALIZATION
The RESET pin is configured as a Schmitt trigger input. If
not used, it should be connected to Vee. Initialization will
occur whenever a logic "0" is applied to the RESET input,
provided it stays low for at least three instruction cycle
times. The user must provide an external RC network and
diode to the RESET pin as in Figure 8. The external POR
(Power·on-Reset) delay must be greater than the internal
POR. The internal POR delay is 2600 internal clock cycles.
c. RC Controlled Oscillator. CKI is configured as a single
pin RC controlled Schmitt trigger oscillator. The cycle frequency equals the oscillation frequency divided by 4.
CKO is available for non·timing functions.
Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, 0, EN, G, H, IL, L, N, Q, R, and T
registers are cleared. The SK output is enabled as a SYNC
output by setting the SKL latch, thus providing a clock. RAM
(data memory and stack) is not cleared. The first instruction
at address 0 must be a CLRA.
CKO PIN OPTIONS
As an option, CKO can be an oscillator output. In a crystal
controlled oscillator system, this signal is used as an output
to the crystal network. As another option, CKO can be an
interrupt input or a general purpose input, reading into bit 2
of A (accumulator) through the INIL instruction. As another
option, CKO can be a RAM power supply pin (VR), allowing
1-191
N
~
C")
D-
o
Functional Description
(Continued)
Crystal Oscillator
A
o
.......
....
~
C")
D-
O
CKI
CKO
10M
o
.......
CKI
o
~
..I1J""
EXTERNAL
CLOCK
C")
D-
O
o
.......
~
~
D-
l ... -vcc f
.rwv-.
(CLOCK OUTPUT,
VR OR GENERAL
:t
-= PURPOSE
INPUT PIN)
(CLOCK OUTPUT,
VR OR GENERAL
PURPOSE INPUT PIN)
TL/OO/6926-14
N
TLIOO/6926-13
CKO
b. External Oscillator
TL/OO/6926-15
c. RC Controlled Oscillator
a. Crystal Oscillator
O
o
.......
....
~
~
O
o
~
~
D-
O
o
R1
1k
1k
2k
RC Controlled Oscillator
Instruction
R (kO) C (pF) Execution
Time (J.t.s)
13
6.8
8.2
22
100
220
300
100
5.0
5.3
8.0
8.2
±20%
±23%
±22%
± 17%
Note: 5 kO ~ R ~ 50 kO
50 pF ~ C ~ 360 pF
D-
o.......
Crystal Value
4 MHz
3.58 MHz
2.10 MHz
FIGURE 9. COP440/441/442 Oscillators
its connection to a standbylbackup power supply to maintain the data integrity of RAM registers 0-3 with minimum
power drain when the main supply is inoperative or shut
down to conserve power. Using either of the two latter options is appropriate in applications where the system configuration does not require use of the CKO pin for timing functions.
g. Standard L,R-same as d., but may be disabled. Available on Land R outputs only (disabled on reset).
h. LED Direct Drive-an enhancement-mode device to
ground and Vee together with a depletion device to Vee
meeting the typical current sourcing requirements of the
segments of an LED display. The sourcing devices are
clamped to limit current flow. These devices may be
turned off under program control (see Functional Description, EN Register), placing the output in a high-impedance state to provide required LED segment blanking for
a multiplexed display. Available on L outputs only.
RAM KEEP-ALIVE OPTION
Selecting CKO as the RAM power supply (VA) allows the
user to shut off the chip power supply (Vee> and maintain
data in the lower 4 registers of the RAM. To insure that RAM
data integrity is maintained, the following conditions must be
met:
Note 1: When the driver is disabled, the depletion device may cause the
output to settle down to an intermediate level between Vee and
GND. This voltage cannot be relied upon as a "1" level when reading the L inputs. The external signal must drive it to a "1" level.
1. RESET must go low before Vee goes below spec during
power-off; Vee must be within spec before RESET goes
high on power-up.
Note 2: Much power is dissipated by this driver in driving an LED. Care must
be taken to limit the power dissipation of the chip to within the
absolute maximum ratings specified.
2. When Vee is on, VA must be within the operating voltage
range of the chip, and within 1V of Vee.
3. VA must be ~ 3.3V with Vee off.
I. TRI-STATE Push-Pull-an enhancement-mode device to
ground and Vee. These outputs are TRI-STATE outputs,
allowing for connection of these outputs to a data bus
shared by other bus drivers. Available on Land R outputs
only (in TRI-STATE mode on reset).
J. Push-Pull R-same as f., but may be disabled. Available
on R outputs only.
k. Additional depletion pull-up-a depletion load to Vec
with the same current sourcing capability as the input
load a., in addition to the output drive chosen. Available
on Land R outputs only. This device cannot be disabled;
therefore, open-drain outputs with "1" output and TRISTATE outputs do not show high-impedance characteristics. This device is useful in applications where a pull-up
with low source current is desired, e.g., reading keyboards and switches.
The above input and output configurations share common
enhancement-mode and depletion-mode devices. Specifically, all configurations use one or more of six devices
(numbered 1-6 respectively). Minimum and maximum current (lour and Vour) curves are given in Figures 11 and 12
for each of these devices to allow the designer to effectively
use these 1/0 configurations in designing a COP440 system.
I/OOPTIONS
COP440 inputs have the following optional configurations,
illustrated in Figure 10.
a. An on-chip depletion load device to Vee.
b. A Hi-Z input which must be driven to a "1" or "0" by
external components.
c. A resistive load to GND for the zero-crossing input option
(IN1 only).
COP440 outputs have the following optional configurations:
d. Standard-an enhancement mode device to ground in
conjunction with a depletion-mode device to Vee, compatible with TTL and CMOS input requirements. Available
on SO, SK, D, G, and H outputs.
e. Open-Drain-an enhancement-mode device to ground
only, allowing external pull-up as required by the user's
application. Available on SO, SK, D, G, L, H, and Routputs.
f. Push-Pull-an enhancement-mode device to ground in
conjunction with a depletion-mode device paralleled by an
enhancement-mode device to Vee. This configuration has
been provided to allow for fast rise and fall times when
driving capacitive loads. Available on SO and SK outputs
only.
1-192
Functional Description
(Continued)
Vee
r-I
rt'l
INPUTI8I---t>-
INPUT~
TL/DD/6926-17
b. HI-Z Input
TLI DD/6926-16
1N1~
-"1 r-
TL/DD/6926-20
TLlDD/6926-19
a. Input with Load
TLlDD/6926-1 B
c. Zero-Crossing
Input
e. Open-Drain
Output
d. Standard
Output
Vee
~F
TLlDD/6926-21
1. Push-Pull Output
TLlDD/6926-23
TLlDD/6926-22
I. TRI-STATE Push-Pull
(L, R) Outputs
g. Standard L, R Outputs
OISABLE~'~VCC
::-1 ....4
,3
---4r~_~~C l.~
L,R OUTPUT _ .....
...
: ....
TL/DD/6926-26
TL/DD/6926-25
J. Push-Pull R Outputs
TLlDD/6926-24
( ... is depletion device)
h. LED (L) Outputs
FIGURE 10. Input/Output Configurations
1-193
k. Additional L, R Outputs Pull-Up
~ .---------------------------------------------------------------------------------------~
~
C")
D.
o(.)
.......
.....
Typical Performance Characteristics
~
C")
30
~
1
C")
I
D.
.!!
o(.)
V
t\
D.
o
(.)
.......
Q
c. Zero-Crossing Detect Input
Current
b. Input Load Minimum Source
Current
'i
\~
20
"
I
i
0.1 1--+--+-4-+--+-4II--~
(MAXiY'
10
~VCC-8.3V
1
~
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VCC-4.~Y"
.......
~
~
~
D.
4
o
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I
~
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7
1
7
VOUT - VOLTS
V
V
-1
VOUT - VOLTS
DEVICE 1
-
IL~ 1.0- ~:;)
5
DEVICE 1
I
VIN - VOLTS
DEVICE 2
VOUT - VOLTS
DEVICE 3
.......
.....
~
~
d. Standard Output
Source Current
D.
o(.)
0.4
.......
Q
e. Standard Output Minimum
Source Current
~
"\
~
~
0.3
D.
o(.)
1
I
~
0.2
K ~ r\.
VCCI-6.3~
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0.1
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......
f'..
~vfc-i·5v
4
o
5
VOUT - VOLTS
a
1.5
.1
E
I
1.0
~
0.5
1\
VCC-4.5~\
l---(jIN.)
o
.1
l-
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rt
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0.5
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o
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2
~~~-r-~~-~~
0.3
1\
(MAX.)
VCc-6.3V
I(MIN·I-
I
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0.2
1(MAX.)
~
S!
VCC-4.5V(MAX.)
\ \1
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c
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0.1
1
o
4
5
VOUT - VOLTS
DEVICE 5
~N.)\
a
I
~
10 1---+-\+-1-\--+--1--1--1
1.0
II
'I
~
4
7
YoUT - VOLTS DEVICES 4 AND 8
V
15
(MAX.)
1\ VCC - 1.3V
\
~
VCCj4.5j\
o
..,
VOUT-ZV
1\
DEVICE 4
I. LED Output Direct LED Drive
20
';I
15 l---'Io+---4-'\...
4
VOUT - VOLTS
V\
I
~
I. Depletion Load OFF Current
k. LED Output Minimum Source
Current
J. LED Output Source Current
2.0
';I
rt
VCC~4.5~\
(MIN.) I
o
YoUT - VOLTS DEVICES 4 AND 5
25
DEVICE 4
.1 .t
VCC-B.3V-
\
1.5
VCC-4.5V(MAX.)
1\\
\.
f'..
h. TRI-STATE Output Source
Current
VCC-8.3V(MAX.)
c
"'-
VOUT - VOLTS
DEVICE 4
g. Push-Pull Source Current
,
........
1
I
~
\
o
V
(MIN.)
o
....-
4.5
YoUT - VOLTS DEVICES4 AND I
./""
..,V
10
5.5
U
VOUT - VOLTS DEVICES UND I
TL/DD/6926-27
FIGURE 11. COP440/441/442 1/0 Characteristics
1-194
o
Typical Performance Characteristics
30
o"tJ
(Continued)
~
~
b. Input Load Minimum
Source Current
o
.......
c. Zero-Crossing Detect
Input Current
o
o"tJ
/
4.0
(M~.)
201-~~~-+-+--+--4
1
-;
~
z
I
7
VOUT - VOLTS
DEVICE 1
o
V
liI-" ~ n
(MIN.)
4
VOUT - VOLTS
.....
.......
/
I 2.0
4
~
~
/
o"tJ
:--
~
~
N
.......
o
o
"tJ
a
-1
W
DEVICE 1
V,N - VOLTS
DEVICE 2
~
o
.......
o
o
"tJ
W
~
.....
o
o
.......
1.5
15
1 1.0 1--+-..3ioJ-¥-+---J.--l
I
!;
~
9
0.5
3
DEVICE 4
N
1--+----1f+-\-++-,j~1 Vcc 24.5 V
1 1.0
1---+_4--H!-----1f+-_(M-+A_X._)--1
I
~
!;
S1
0.5
2
\ \
\ \
VCC a 5.5V
r(MIN.)
(MAX.)
H
I
0.5
I !\
rVcc a4.5V\
(MIN.) I
l\
o
I
~
,
III
\
N!~.~
o
o
4
5
DEVICE 5
k. LED Output Minimum Source
Current
J. LED Output Source Current
l~AX.)
0.2
O. 1
VOUT - VOLTS
DEVICES 4AND 5
1\
0.3
1
DEVICE 3
I. Depletion Load OFF
Current
0.4
\ Ivcc24.5v
......;
a
4
YoUT - VOLTS
VOUT - VOLTS
VCCd.5V
(MAX.)_
I
1.5
I
2
DEVICE 4
h. TRI-STATE Output Source
Current
VCCd.5V
1.51--+--+H-tt---+(MAX.)
25
~
It--M~"""""-t
4
VOUT - VOLTS
g. Push-Pull Source Current
1.0
10
5.0 \J--hL-+--f.--t--t-~
VOUT - VOLTS
1
"tJ
W
1
VOUT - VOLTS
6
DEVICE 4
I. LED Output Direct LED
Driver
20
VOUT-2V
(MAXY
20~~~+--+-+--4-4
1
15
-;
15 I-----+''o---H,..
I
I
~ 101--+~~4rt-4-----1-~
V
I-
§ 1.0 1#--+-+--++-+---+---1
L
V
(MI~
oe:~-~~~~~--~
a
2
4
5
VCC - VOLTS DEVICES UND 6
a
~
4.5
VOUT - VOLTS DEVICES UND 6
5.0
5.5
6.0
VOUT - VOLTS DEVICES 4 AND 6
TL/DD/6926-26
FIGURE 12. CCOP340/341/342110 Characteristics
1·195
C\I
"'=I'
C")
a..
o
o
......
.....
"'=I'
C")
a..
o
o......
o
"'=I'
C")
a..
o
o......
C\I
"'=I'
"'=I'
a..
oo
......
Power Dissipation
a..
oo
......
o
"'=I'
"'=I'
a..
oo
TPD = 210 + 9 + 6 + 36 + 476 mW = 737 mW
This is within the 750 mW limit at room temperature. If
this application has to operate at 70°C, then the power
dissipation must be reduced to meet the limit at that temperature. Some ways to achieve this would be to limit the
LED current or to use an external LED driver.
At 70·C the absolute maximum power dissipation rating
drops to 400 mW. The user must be careful not to exceed
this value.
a. At 25°C, maximum power dissipation allowed = 750 mW
b. Power dissipation by chip except
COP440 SERIES DEVICES
If the COP440 is bonded as a 28- or 24-pin device, it becomes the COP441 or COP442, respectively, as illustrated
in Figure 3. Note that the COP441 and COP442 do not include Hand R ports. In addition, the COP442 does not include IN inputs; use of this option precludes the use of the
IN options, the interrupt feature with IN as input, the zerocrossing detect option, IN2 external event counter input,
and the MICROBUS option. All other options are available.
COP340, COP341, and COP342 are extended temperature
versions of the COP440, COP441, and COP442, respectively.
1/0 = lee x Vee = 35mA x 6V = 210mW
c. Maximum power dissipation by IN,
.....
"'=I'
"'=I'
Total power dissipation (TPD) inside the device is the
sum of items b through g above.
In order not to damage the device by exceeding the absolute maximum power dissipation rating, the amount of power
dissipated inside the chip must be carefully controlled. As
an example, an application uses a COP440 in room temperature (25°C) environment with a Vee power supply of 6V; IN
and SI inputs have internal loads; G and 0 ports drive loads
that may sink up to 2 mA into the chip; H port with standard
output option reads switches; L port with the LED option
drives a multiplexed seven-segment display; R, SO and SK
drive MOS inputs that do not source or sink any current.
SI
=
5
x
0.3 mA
x
6V
=
9 mW
d. G and 0 ports are sinking current from external loads;
maximum output voltage with 2 mA sink current is less
than O.4V. Power dissipation by G and 0 ports =
2 mA x O.4V x 8 = 6.4 mW
e. Maximum power dissipation by H port =
4
x
1.5 mA
x 6V =
36 mW
f. When the seven segments of the LED are turned on, the
output voltage is about 2V, so that the segment current is
17 mA. Power dissipation by L port =
7 x 17mA x (6V - 2V) = 476mW
COP440 Series Instruction Set
Table II is a symbol table providing internal architecture, instruction operand and operation symbols used in the instruction set table.
Table III provides the mnemonic, operand, machine code,
data flow, skip conditions and description associated with
each instruction in the COP440 series instruction set.
This power dissipation caused by driving LEOs is usually
the highest among the various sources.
g. R, SO, and SK do not dissipate any significant amount of
power because they do not need to source or sink any
current.
Symbol
TABLE II. COP440 Series Instruction Set Symbols
Definition
Symbol
Definition
INTERNAL ARCHITECTURE SYMBOLS
INSTRUCTION OPERAND SYMBOLS
A
B
Br
Bd
C
d
4-bit Operand Field, 0-15 binary (RAM Digit Select)
r
4-bit Operand Field, 0-9 binary (RAM Register Select)
a
11-bit Operand Field, 0-2047 binary (ROM Address)
y
4-bit Operand Field, 0-15 binary (Immediate Data)
RAM(s) Content of RAM location addressed by s
RAMN Content of RAM location addressed by stack pointer N
ROM(t) Content of ROM location addressed by t
o
EN
G
H
IL
IN
IN1Z
L
M
N
PC
Q
R
SIO
SK
T
4-bit Accumulator
8-bit RAM Address Register
Upper 4 bits of B (register address)
Lower 4 bits of B (digit address)
1-bit Carry Register
4-bit Data Output Port
8-bit Enable Register
4-bit Register to latch data for G I/O Port
4-bit Register to latch data for H 1/0 Port
Two 1-bit Latches associated with the IN3 or INo Inputs
4-bit Input Port
Zero-Crossing Input
8-bitTRI-STATE I/O Port
4-bit contents of RAM Memory pointed to by B Register
2-bit subroutine return address stack pointer
11-bit ROM Address Register (program counter)
8-bit Register to latch data for L I/O Port
8-bit Register to latch data for R TRI-STATE 1/0 Port
4-bit Shift Register and Counter
Logic-Controlled Clock Output
8-bit Binary Counter Register
1-196
OPERATIONAL SYMBOLS
+
-+
~
=
A
Ell
:
V
Plus
Minus
Replaces
Is exchanged with
Is equal to
The one's complement of A
Exclusive-OR
Range of values
OR
o
o
Instruction Set
"tJ
0l:Io
0l:Io
o
.......
TABLE III. COP440 Series Instruction Set
Mnemonic Operand
Hex
Code
o
Machine
Language Code
(Binary)
Data Flow
Description
Skip Conditions
30
0l:Io
ADD
ADT
A + C + RAM(8)
Carry ~ C
10011100001
I
"tJ
0l:Io
.....
.......
ARITHMETIC/LOGIC INSTRUCTIONS
ASC
o
~
~
A
Carry
Add with Carry, Skip on
Carry
o
o
"tJ
0l:Io
0l:Io
N
None
Add RAMtoA
.......
A + 1010 ~ A
None
Add Ten to A
"tJ
~
A
Carry
Add immediate, Skip on
Carry (y oF 0)
A + RAM(8) + C ~ A
Carry ~ C
Carry
Complement and Add with
Carry, Skip on Carry
31
1001110001
A + RAM(8)
4A
1010011010 I
5-
10101 1 y
A+y
10
10001100001
A
o
o
(,,)
AISC
Y
CASC
I
0l:Io
o
.......
o
o
"tJ
(,,)
0l:Io
.....
.......
CLRA
00
10000100001
O~A
None
Clear A
COMP
40
10100100001
A~A
None
One's complement of A to A
o
o
"tJ
(,,)
0l:Io
N
None
No Operation
None
OR RAM with A
C
None
ResetC
C
None
SetC
None
Exclusive-OR RAM with A
None
Jump Indirect (Note 3)
None
Jump
None
Jump within Page
(Note 4)
NOP
44
10100101001
None
OR
33
1A
1001110011 I
1000111010 I
AVM
RC
32
10011100101
"0"
~
SC
22
10010100101
"1"
~
XOR
02
10000100101
A EB RAM(8)
~
A
~
A
TRANSFER OF CONTROL INSTRUCTIONS
JID
JMP
a
JP
a
ROM (PC10:8' A,M) ~
PC7:0
FF
11111111111
6-
1011010la1Qoei
I aZoQ I
a
--
11 I a6 Q I
(pages 2,3 only)
or
111 I a~oQ
I
(all other pages)
a ~ PC6:0
--
--
0
~
PC
a ~ PCs:o
JSRP
a
--
110 I
I
PC + 1 ~ RAMN
N + 1 ~ N
00010 ~ PC10:6
a ~ PCs:o
None
Jump to Subroutine Page
(Note 5)
JSR
a
6-
10110111a1Qoei
PC + 1 ~ RAMN
N + 1 ~ N
a ~ PC
None
Jump to Subroutine
a~oQ
--
I
RET
48
10100110001
N-1 ~ N
RAMN ~ PC
None
Return from Subroutine
RETSK
49
10100110011
N-1 ~ N
RAMN ~ PC
Always Skip on Return
Return from Subroutine
then Skip
aZoQ
I
1-197
N
"III:t
CW')
D.
oo
Instruction Set (Continued)
TABLE III. COP440 Series Instruction Set (Continued)
......
....
"III:t
CW')
D.
oo
......
o
Mnemonic Operand
~oe:e
Machine
Language Code
(Binary)
DataFlow
Skip Conditions
Description
MEMORY REFERENCE INSTRUCTIONS
CAME
33
1F
10011100111
10001 11111 1
A ~ EN7:4
RAM (B) ~ EN3:0
None
Copy A, RAM to EN
o
CAMQ
33
3C
10011100111
1001111100
A ~ Q7:4
RAM (B) ~ Q3:0
None
Copy A, RAM to Q
"III:t
"III:t
CAMT
33
3F
1001110011
1001111111
A ~ T7:4
RAM (B) ~ T3:0
None
Copy A, RAM to T
CEMA
33
OF
1001110011
1000011111
EN7:4
EN3:0
~
~
None
Copy EN to RAM, A
CQMA
33
2C
1001110011
10010111001
Q7:4 ~ RAM (B)
None
Copy Q to RAM, A
33
2F
10011100111
1001011111 1
T7:4 ~ RAM (B)
T3:0 ~ A
None
Copy T to RAM, A
-5
100lrl01011
r = 0:3
RAM (B) ~ A
Br E9 r ~ Br
None
Load RAM into A,
Exclusive-OR Br with r
None
Load A with RAM pOinted
to directly by r,d
"III:t
CW')
D.
o
......
N
D.
o
o......
....
"III:t
"III:t
D.
oo
......
o
"III:t
"III:t
CTMA
D.
oo
LD
r
LDD
r,d
23
--
RAM (B)
A
Q3:0~A
100 11 0 10011 1 RAM(r,d)
10 1 r 1 d 1
r - 0:7
~
A
LID
33
19
10011100111
10001 11001 1
ROM (PC10:8, A, M)
LQID
BF
11011 11111 1
ROM(PC10:8,A,M)
~
~
M, A None
Q
Load RAM, A Indirect
None
Load Q Indirect (Note 3)
RMB
0
1
2
3
4C
45
42
43
10100111001
10100101011
10100100101
10100100111
o~
o~
o~
o~
RAM(B)o
RAM(Bh
RAM(B)2
RAM(B)s
None
Reset RAM Bit
5MB
0
1
2
3
4D
47
46
4B
10100111011
10100101111
10100101101
1010011011 1
1
1
1
1
RAM(B)o
RAM(B)1
RAM(B)2
RAM(B)s
None
Set RAM Bit
STII
Y
7-
10111 1 y. 1
y ~ RAM(B)
Bd + 1 ~ Bd
None
Store Memory Immediate
and Increment Bd
X
r
-6
100 1r 10110 1
r - 0:3
RAM (B) ~ A
Br E9 r ~ Br
None
Exchange RAM with A,
Exclusive-OR Br with r
XAD
r,d
23
10010100111
11 1 r 1 d 1
r = 0:7
RAM(r,d)
None
Exchange A with RAM
pOinted to directly by r,d
XDS
r
-7
100 1r 10111 1
r = 0:3
RAM (B) ~ A
Bd -1 ~ Bd
Br E9 r ~ Br
Bd decrements past 0
Exchange RAM with A
and Decrement Bd,
Exclusive-OR Br with r
XIS
r
-4
100 1r 101001
r = 0:3
RAM (B) ~ A
Bd + 1 ~ Bd
Br E9 r ~ Br
Bd increments past 15 Exchange RAM with A
and Increment Bd,
Exclusive-OR Br with r
--
~
~
~
~
~
A
1-198
o
o"C
Instruction Set (Continued)
oI:ao
oI:ao
o
.......
TABLE III. COP440 Series Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
o
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
oI:ao
oI:ao
...a.
.......
REGISTER REFERENCE INSTRUCTIONS
o
CAB
50
10101100001
A -. Bd
None
Copy A to Bd
CBA
4E
10100111101
Bd -. A
None
Copy Bd to A
--
100 1r 1~d - 1) 1
r = 0:3, d = 0,9:15
or
10011 10011 1
11 1 r 1 d 1
r = 0:7, any d
r,d -. B
Skip until not a LBI
Load B Immediate with
r,d (Note 6)
LBI
r,d
33
-LEI
y
o"C
o"C
oI:ao
oI:ao
N
.......
o
o
"C
oI:ao
(,)
o
.......
o
o"C
(,)
oI:ao
...a.
33
6-
10011 10011 1
10110 1 Y.. 1
y -. EN3:0
None
Load lower half
of EN Immediate
XABR
12
10001100101
A
~
Br
None
Exchange A with Br
XAN
33
OB
10011 10011 1
1000011011 1
A
~
N(O,O -. A3, A2)
None
Exchange A with N
SKC
20
10010100001
C
=
SKE
21
10010100011
A
= RAM (B)
SKGZ
33
21
10011100111
10010100011
G3:0
0
1
2
3
33
01
11
03
13
10011100111
10000100011
10001100011
10000100111
10001100111
0
1
2
3
01
11
03
13
10000100011
10001100011
10000100111
10001100111
RAM(B)o
RAM(Bh
RAM(B)2
RAM(Bb
SKSZ
33
1C
10011100111
10001111001
SIO
SKT
41
10100100011
T counter carry has
occurred since last
test
.......
o
o"C
(,)
TEST INSTRUCTIONS
SKGBZ
SKMBZ
Skip if C is True
"1"
=0
Skip if G is Zero
(all 4 bits)
1st byte
} 2nd byte
1-199
Skip if A Equals RAM
Skip if G Bit is Zero
Go
G1
G2
G3
=0
=0
=0
=0
=0
=0
=0
=0
=0
Skip if RAM Bit is Zero
Skip if SIO is Zero
Skip on Timer (Note 3)
oI:ao
N
C\I
"11:1'
C")
D-
Instruction Set (Continued)
O
TABLE III. COP440 Series Instruction Set (Continued)
0
.,..
........
"11:1'
C")
D-
Mnemonic
Operand
0
0
........
0
"11:1'
C")
D-
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
INPUTIOUTPUT INSTRUCTIONS
CAMR
33
3D
10011100111
10011 11101 1
A ---+ R7:4
RAM(8) ---+ R3:0
None
Output A, RAM to R Port
ING
33
2A
10011 10011 1
10010110101
G---+A
None
Input G Port to A
INH
33
28
10011100111
10010110111
H---+A
None
Input H Port to A
ININ
33
28
10011100111
10010110001
IN ---+ A
None
Input IN Inputs to A (Note 2)
INIL
33
29
10011100111
10010110011
IL3, CKO, IN1Z, ILa ---+ A
None
Input IL Latches to A
(Note 3)
INL
33
2E
10011100111
10010111101
L7:4 ---+ RAM(8)
L3:0 ---+ A
None
Input L Port to RAM, A
INR
33
2D
10011100111
10010111011
R7:4 ---+ RAM(8)
R3:0 ---+ A
None
Input R Port to RAM,A
08D
33
3E
10011100111
10011 11110 1
8d ---+ D
None
Output 8d to D Port
33
10011100111
10101 1 y 1
y---+G
None
Output to G Port Immediate
5OMG
33
3A
10011100111
10011110101
RAM(8) ---+ G
None
Output RAM to G Port
OMH
33
38
10011100111
10011110111
RAM(8) ---+ H
None
Output RAM to H Port
XAS
4F
10100 111111
A
None
Exchange A with SIO
(Note 3)
0
0
........
C\I
"11:1'
"11:1'
D-
O
0........
.,..
"11:1'
"11:1'
D-
0
0
........
0
"11:1'
"11:1'
D-
0
0
OGI
Note 1:
y
~
SIO, C ---+ SKL
All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Sr and Sd are explicitly defined). Sits are numbered 0 to N where
o signifies the least significant bit (low-order, right-most bit). For example, A3 indicates the most significant (left-most) bit of the 4-bit A register.
Note 2: The
ININ instruction is not available on the 24-pin COP442/COP342 since this device does not contain the IN inputs.
For additional information on the operation of the XAS, JID, LQID, INIL, and SKT instructions, see below.
Note 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction,
otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Note 5: A JSRP transfers program control to subroutine page 2 (00010 is loaded into the upper 5 bits of Pl. A JSRP may not be used when in pages 2 or 3. JSRP
may not jump to the last word in page 2.
•
Note 6: LSI is a single-byte instruction if d = 0,9,10, 11, 12, 13, 14, or 15. The machine code for the lower 4 bits equals the binary value of the "d" data minus 1,
e.g., to load the lower four bits of S (Sd) with the value 9 (10012), the lower 4 bits of the LSI instruction equal 8 (10002)' To load 0, the lower 4 bits of the LSI
instruction should equal 15 (11112)'
Note 3:
1-200
o
o
Description of Selected
Instructions
""C
~
~
If zero-crossing detect is selected, the INl input will go
through the detection logic, thus allowing the user to interrogate the input, sending a "1" if the input is above ov and a
"0" if it is below OV. INIL is useful in recognizing pulses of
short duration or pulses which occur too often to be read
conveniently by an ININ instruction. It is also useful in
checking the status of the zero-crossing detect input. The
general purpose inputs IN3-INo are input to A upon execution of an ININ instruction, and the IN1 input does not go
through zero-crossing logic so that it has the same logic
level as the other IN inputs for the ININ instruction (see
Figure 9).
The following information is provided to assist the user in
understanding the operation of several unique instructions
and to provide notes useful to programmers in writing
COP440 programs.
XAS INSTRUCTION
XAS (Exchange A with SID) exchanges the 4-bit contents of
the accumulator with the 4-bit contents of the SID register.
The contents of SID will contain serial-in/serial-out shift register or binary counter data, depending on the value of the
EN register. An XAS instruction will also affect the SK output. (See Functional Description, EN register, above). If SID
is selected as a shift register, an XAS instruction must be
performed once every 4 instruction cycles to effect a continuous data stream.
Note: IL latches are cleared on reset. This is different from the COP4201
420C/420L/444L series.
LQID INSTRUCTION
JID INSTRUCTION
LQID (Load Q Indirect) loads the a-bit Q register with the
contents of ROM pointed to by the 11-bit word PC10:PC8, A,
M. LQID can be used for table lookup or code conversion
such as BCD to seven-segment. Note that LQID takes two
instruction cycles if executed and one instruction cycle if
skipped. Unlike most other COPS processors, this instruction does not push the stack.
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location pointed
to indirectly by A and M. It loads the lower a bits of the ROM
address register PC with the contents of ROM addressed by
the 11-bit word, PC1O:S, A, M. PC10, PCg and PCs are not
affected by this instruction.
Note that JID requires 2 instruction cycles if executed, 1
instruction cycle time if skipped.
LID INSTRUCTION
LID (Load Indirect) loads M and A with the contents of ROM
pointed to by the 11-bit word PC10:PC8, A, M. Note that LID
takes three instruction cycles if executed and two if skipped.
INIL INSTRUCTION
INIL (Input IL Latches to A) inputs 2 latches, IL3 and ILa,
CKO and INl into A (see Figure 13). The IL3 and ILa latches
are set if a low-going pulse ("1" to "0") has occurred on the
IN3 and INo inputs since the last INIL instruction, provided
the input pulse stays low for at least two instruction cycles.
Execution of an INIL inputs IL3 and ILa into A3 and AO respectively, and resets these latches to allow them to respond to subsequent low-going pulses on the IN3 and INo
lines. If CKO is mask-programmed as a general purpose
input, an INIL will input the state of CKO into A2. If CKO has
not been so programmed, a "1" will be placed in A2. Unlike
the COP420/420C/420L!444L series, INIL will input INl
into A1.
SKT INSTRUCTION
The SKT (Skip On Timer) instruction tests the state of the T
counter (see internal logic, above) overflow latch, executing
the next program instruction if the latch is not set. If the
latch has been set since the previous test, the next program
instruction is skipped and the latch is reset. The features
associated with this instruction allow the processor to generate its own time-base for real-time processing, rather than
relying on an external input Signal.
INSTRUCTION SET NOTES
a. The first word of a COP440 program (ROM address 0)
must be a CLRA (Clear A) instruction.
b. Although skipped instructions are not executed, they are
still fetched from program memory. Thus program paths
take the same number of cycle times whether instructions
are skipped or executed, except for LID, LQID, and JID.
ININ
.1
INoIIN3
c. The ROM is organized into 32 pages of 64 words each.
The Program Counter is an 11-bit binary counter, and will
count through page boundaries. If a JP, JSRP, JID, LQID,
or LID instruction is the last word of a page, the instruction operates as if it were in the next page. For example: a
JP located in the last word of a page will jump to a location in the next page. Also, a LQID or JID located in the
last word of page 3, 7,11, 15, 19,23,27, or 31 will access
data in the next group of four pages.
INIL
TL/DD/6926-29
FIGURE 13. INIL Hardware Implementation
1·201
o
.......
o
o
""C
~
~
~
.......
o
o
""C
~
~
I\)
.......
o
o
""C
(,,)
~
o
.......
o
o
""C
(,,)
~
~
.......
o
o""C
(,,)
~
I\)
~ r---------------------------------------------------------------------------------------~
~
('t)
D.
oo
.......
-~
('t)
D.
oo
.......
o
~
('t)
D.
o
o
.......
Option List
The COP440 mask-programmable options are assigned numbers which correspond with the COP440 pins.
Option 1: L1 1/0 Port (see note below)
= 0: Standard output
= 1: Open-drain output
= 2: LED direct drive output
= 3: TRI-STATE output
= 4: same as 0 with extra load device
= 5: same as 1 with extra load device
= 6: same as 2 with extra load device
= 7: same as 3 with extra load device
~
~
~
Option 2: Lo 1/0 Port
(same as Option 1)
o
Option 3: SI Input
= 0: Input with load device to Vee
= 1: Hi-Z Input
D.
o
.......
-~
~
D.
o
o
.......
o
~
~
to
to
to
to
Vee
Vee
Vee
Vee
Option 22: CKI Input
= 0: Crystal input divided by 16
= 1: Crystal input divided by 8
= 2: Single-pin RC controlled oscillator (+ 4)
= 3: Schmitt trigger clock input (+ 4)
Option 23: RESET Input
(same as Option 3)
Option 24: R7 1/0 Port (see note below)
= 0: Standard output
= 1: Open-drain output
= 2: Push-pull output
= 3: TRI-STATE output
= 4: same as 0 with extra load device
= 5: same as 1 with extra load device
= 6: same as 2 with extra load device
= 7: same as 3 with extra load device
Option 4: SO Output
= 0: Standard output
= 1: Open-drain output
= 2: Push-pull output
D.
Option 5: SK Output
(same as Option 4)
o
Option 6: INo Input
(same as Option 3)
o
Option 21: CKO Pin
= 0: Oscillator output
= 1: RAM power supply (VR) input
= 2: General purpose input with load device to Vee
= 3: General purpose Hi-Z input
to
to
to
to
Vee
Vee
Vee
Vee
Option 25: Rs 1/0 Port
(same as Option 24)
Option 7: IN3 Input
(same as Option 3)
Option 26: R5 1/0 Port
(same as Option 24)
Option 8: Go 1/0 Port
= 0: Standard output
= 1: Open-drain output
Option 27: R4 1/0 Port
(same as Option 24)
Option 9, G1 1/0 Port
(same as Option 8)
Option 28: R3 1/0 Port
(same as Option 24)
Option 10: G2 1/0 Port
(same as Option 8)
Option 29: R2 1/0 Port
(same as Option 24)
Option 11: G3 1/0 Port
(same as Option 8)
Option 30: R1 1/0 Port
(same as Option 24)
Option 12: Ho 1/0 Port
(same as Option 8)
Option 31: Ro 1/0 Port
(same as Option 24)
Option 13: H1 1/0 Port
(same as Option 8)
Option 32: L7 1/0 Port
(same as Option 1)
Option 14: H2 1/0 Port
(same as Option 8)
Option 33: Ls 1/0 Port
(same as Option 1)
Option 15: H3 1/0 Port
(same as Option 8)
Option 34: L5 1/0 Port
(same as Option 1)
Option 16: 03 Output
(same as Option 8)
Option 35: L4 1/0 Port
(same as Option 1)
Option 17: 02 Output
(same as Option 8)
Option 36: IN1 Input
= 0: Input with load device to Vee
= 1: Hi-Z Input
= 2: Zero-crossing detect input (Option 41 = 0)
Option 18: 01 Output
(same as Option 8)
Option 37: IN2 Input
(same as Option 3)
Option 19: Do Output
(same as Option 8)
Option 38: L3 1/0 Port
(same as Option 1)
Option 20: GND-No options available
Option 39: L2 1/0 Port
(same as Option 1)
Option 40: Vee-no options available
1-202
o
o
-a
~
Option List (Continued)
Option 46: 51 Input Levels
(same as Option 42)
Option 41: COP Function
= 0: Normal
= 1: MICROBUS option
Option 42: IN Input Levels
= 0: Standard TTL input levels ("0" = 0.8V, "1" = 2.0V)
= 1: Higher voltage input levels ("0" = 1.2V, "1" =
3.6V)
Option 43: G Input Levels
(same as Option 42)
~
c
........
o
Option 47: R Input Levels
(same as Option 42)
o-a
Option 48: H Input Levels
(same as Option 42)
.....
........
Option 49: No option available
o-a
~
~
o
Option 50: COP Bonding
= 0: COP440 (40-pin device)
= 1: COP441 (28-pin device)
= 2: COP442 (24-pin device)
= 3: COP440 and COP441
= 4: COP440 and COP442
= 5: COP440, COP441, and COP442
= 6: COP441 and COP442
Option 44: L Input Levels
(same as Option 42)
Option 45: CKO Input Levels
(same as Option 42)
=
=
=
IS: L1 lID PORT
OPTION 26 VALUE
La 1/0 PORT
OPTION 27 VALUE
IS: 51 INPUT
OPTION 28 VALUE
IS: SO OUTPUT
OPTION 29 VALUE
OPTION 21 VALUE
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
OPTION 22 VALUE
=
1 VALUE
2 VALUE
OPTION
3 VALUE
OPTION
4 VALUE
OPTION
5 VALUE
OPTION
6 VALUE
OPTION
7 VALUE
OPTION
8 VALUE
OPTION
9 VALUE
OPTION 10 VALUE
OPTION 11 VALUE
OPTION 12 VALUE
OPTION 13 VALUE
OPTION 14 VALUE
OPTION 15 VALUE
OPTION 16 VALUE
OPTION 17 VALUE
OPTION 18 VALUE
OPTION 19 VALUE
OPTION 20 VALUE
IS:
0
=
OPTION 24 VALUE =
OPTION 25 VALUE =
OPTION 23 VALUE
o
o
-a
w
~
c
........
o
w
~
The following options information is to be sent to National along with the EPROM.
OPTION
........
o-a
COP440 Option Table
OPTION
~
~
N
IS: SK OUTPUT
OPTION 30 VALUE
IS: INo INPUT
OPTION 31 VALUE
IS: IN3 INPUT
OPTION 32 VALUE
IS: Go 1/0 PORT
OPTION 33 VALUE
IS: G1 1/0 PORT
OPTION 34 VALUE
IS: G2 1/0 PORT
OPTION 35 VALUE
IS: G3 1/0 PORT
OPTION 36 VALUE
IS: Ho 1/0 PORT
OPTION 37 VALUE
IS: H1 1/0 PORT
OPTION 38 VALUE
IS: H2 1/0 PORT
OPTION 39 VALUE
IS: H3 lID PORT
OPTION 40 VALUE
IS: D3 OUTPUT
OPTION 41 VALUE
IS: D2 OUTPUT
OPTION 42 VALUE
IS: D1 OUTPUT
OPTION 43 VALUE
IS: Do OUTPUT
OPTION 44 VALUE
IS: GROUND PIN
OPTION 45 VALUE
IS: CKO PIN
OPTION 46 VALUE
IS: CKI INPUT
OPTION 47 VALUE
IS: RESET INPUT
OPTION 48 VALUE
IS: R7 1/0 PORT
OPTION 49 VALUE
IS: R6 1/0 PORT
OPTION 50 VALUE
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
IS: R5 1/0 PORT
IS: R4 1/0 PORT
IS: R3 1/0 PORT
IS: R2 1/0 PORT
IS: R1 1/0 PORT
IS: Ro 1/0 PORT
IS: L7 1/0 PORT
IS: L6 I/O PORT
IS: Ls 1/0 PORT
IS: L4 1/0 PORT
IS: IN1 INPUT
IS: IN2 INPUT
IS: L3 1/0 PORT
IS: L2 1/0 PORT
0
IS: Vee
IS: COP FUNCTION
IS: IN INPUT LEVELS
IS: G INPUT LEVELS
IS: L INPUT LEVELS
IS: CKO INPUT LEVELS
IS: 51 INPUT LEVELS
IS: R INPUT LEVELS
IS: H INPUT LEVELS
IS: NO OPTION
IS: COP BONDING
Note on Land R I/O Port Options
Test Mode (Non-Standard Operation)
If Land R 1/0 Ports are used as inputs, the following must
be observed:
The SO output has been configured to provide for standard
test procedures for the custom-programmed COP440. With
SO forced to logic "1 ", two test modes are provided, depending upon the value of 51:
a. Open-Drain output (selection 1) is allowed only if external
pull-up is provided.
a. RAM and Internal Logic Test Mode (51 = 1)
b. If Land R output ports are disabled when reading, an
external pull-up is required unless selections 4, 5, 6, or 7
are chosen.
b. ROM Test Mode (51 = 0)
These special test modes should not be employed by the
user; they are intended for manufacturing test only.
c. If L output port is enabled, selections 3 and 7 are not
allowed.
d. If R output port is enabled, selections 2, 3, 6, and 7 are
not allowed.
1-203
.....
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~National
~ Semiconductor
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COP444L/COP445L/COP344L/COP345L
o Single-Chip N-Channel Microcontrollers
o
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oo
......
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~
~
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oo
General Description
Features
The COP444L, COP445L, COP344L, and COP345L SingleChip N-Channel Microcontrollers are members of the
COPSTM family, fabricated using N-channel, silicon gate
MOS technology. These controller oriented processors are
complete microcomputers containing all system timing, internal logic, ROM, RAM, and I/O necessary to implement
dedicated control functions in a variety of applications. Features include single supply operation, a variety of output
configuration options, with an instruction set, internal architecture and I/O scheme designed to facilitate keyboard input, display output and BCD data manipulation. The
COP445L is identical to the COP444L, but with 19 I/O lines
instead of 23. They are an appropriate choice for use in
numerous human interface control environments. Standard
test procedures and reliable high-density fabrication techniques provide the medium to large volume customers with
a customized controller oriented processor at a low endproduct cost.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The COP344L and COP345L are exact functional equivalents, but extended temperature range versions of the
COP444L and COP445L respectively.
•
•
Low cost
Powerful instruction set
2k x 8 ROM, 128 x 4 RAM
23 I/O lines (COP444L)
True vectored interrupt, plus restart
Three-level subroutine stack
15 JLs instruction time
Single supply operation (4.5-6.3V)
Low current drain (11 mA max.)
Internal time-base counter for real-time processing
Internal binary counter register with MICROWIRETM serial I/O capability
General purpose and TRI-STATE® outputs
LSTTLICMOS compatible in and out
Direct drive of LED digit and segment lines
Software/hardware compatible with other members of
COP400 family
Extended temperature range devices
COP344L1COP345L (-40°C to + 85°C)
Wider supply range (4.5-9.5V) optionally available
Block Diagram
CKI
L
SC
CKD
L
11
J.LEVELSTACK
5
•
7
I
IZ
13
14
ZO 10 •
I'
IN3 INZ INI INO
15
TLlDD/6928-1
FIGURE 1
1-204
o
o
COP444L/COP445L
"'tJ
0l:Io
0l:Io
0l:Io
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage at Any Pin Relative to GND
O·Cto +70·C
- 65·C to + 150·C
Lead Temperature (Soldering, 10 seconds)
Power Dissipation
120mA
Total Sink current
120mA
Absolute maximum ratings indicate limits beyond which
damage to the device may occur. DC and AC electrical
specifications are not ensured when operating the device at
absolulte maximum ratings.
-0.5Vto +10V
Ambient Operating Temperature
Ambient Storage Temperature
Total Source Current
300·C
Standard Operating Voltage (Ved
+ 70·C, 4.5V
(Note 1)
o"'tJ
Min
Max
Units
W
0l:Io
4.5
6.3
V
r-
9.5
V
Power Supply Ripple
Peak to Peak
4.5
0.5
V
Operating Supply Current
All Inputs and Outputs Open
13
rnA
0.4
V
V
0.7 Vee
-0.3
0.6
V
V
0.7 Vee
-0.3
0.6
V
V
2.0
2.5
V
3.0
2.0
-0.3
3.6
-0.3
0.8
V
V
V
V
V
7
pF
-1
+1
/-LA
0.4
V
V
0.2
V
V
=
=
o"'tJ
ro
s:: Vee s:: 9.5V unless otherwise noted.
Conditions
Vee
Vee
ro
........
........
Optional Operating Voltage (Ved
Input Voltage Levels
CKllnput Levels
Crystal Input ( -:- 32, -:-16, -:- 8)
Logic High (VIH)
Logic High (VIH)
Logic Low (VIU
0l:Io
0l:Io
U1
0l:Io
0l:Io
0.4 Watt at 70·C
Parameter
o"'tJ
w
0.75 Watt at 25·C
DC Electrical Characteristics o·c s:: TA s::
ro
........
Max.
5V ±5%
Schmitt Trigger Input (-:- 4)
Logic High (VIH)
Logic Low (VIU
RESET Input Levels
Logic High
Logic Low
Schmitt Trigger Input
SO Input Level (Test Mode)
(Note 3)
All Other Inputs
Logic High
Logic High
Logic Low
Logic High
Logic Low
Vee = Max.
With TIL Trip Level Options
Selected, Vee = 5V ± 10%
With High Trip Level Options
Selected
3.0
2.0
-0.3
Input Capacitance
Hi-Z Input Leakage
Output Voltage Levels
LSTIL Operation
Logic High (VOH)
Logic Low (VOU
Vee = 5V ±5%
IOH = -25/-LA
IOL = 0.36 rnA
CMOS Operation (Note 2)
Logic High
Logic Low
IOH
IOL
= -l0/-LA
= +10/-LA
Note 1: Vcc voltage change must be less than O.SV in a 1 ms period to maintain proper operation.
Note 2: TRI·STATE and LED configurations are excluded.
Note 3: SO output "0" level must be less than O.BV for normal operation.
1-205
1.2
2.7
Vee- 1
U1
...I
it)
~
CW)
COP444L/COP445L (Continued)
D..
o
o
.......
...I
~
~
CW)
D..
oo
::J
DC Electrical Characteristics o·c ~ TA ~
Output Current Levels
Output Sink Current
SO and SK Outputs (Iou
it)
~
~
D..
o
o
.......
...I
~
~
~
Lo-L7 Outputs and Standard
GO-G3, Do-D3 Outputs (Iou
GO-G3 and Do-D3 Outputs with
High Current Options (Iou
D..
oo
GO-G3 and Do-D3 Outputs with
Very High Current Options (Iou
CKI (Single-pin RC oscillator)
CKO
Output Source Current
Standard Configuration,
All Outputs (IOH)
Push-Pull Configuration
SO and SK Outputs (IOH)
LED Configuration, Lo-L7
Outputs, Low Current
Drivers Option (IOH)
+ 70·C, 4.5V ~ Vee ~ 9.5V unless otherwise noted. (Continued)
Conditions
Min
= 9.5V, VOL = O.4V
= 6.3V, VOL = 0.4V
= 4.5V, VOL = O.4V
Vee = 9.5V, VOL = O.4V
Vee = 6.3V, VOL = O.4V
Vee = 4.5V, VOL = O.4V
Vee = 9.5V, VOL = 1.0V
Vee = 6.3V, VOL = 1.0V
Vee = 4.5V, VOL = 1.0V
Vee = 9.5V, VOL = 1.0V
Vee = 6.3V, VOL = 1.0V
Vee = 4.5V, VOL = 1.0V
Vee = 4.5V, VIH = 3.5V
Vee = 4.5V, VOL = O.4V
1.8
1.2
0.9
mA
mA
mA
0.4
0.4
0.4
15
11
7.5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Parameter
Vee
Vee
Vee
= 9.5V, VOH
= 6.3V, VOH
= 4.5V, VOH
Vee = 9.5V, VOH
Vee = 6.3V, VOH
Vee = 4.5V, VOH
Vee
Vee
Vee
= 2.0V
= 2.0V
= 2.0V
= 4.75V
= 2.4V
= 1.0V
Max
30
22
15
2
0.2
-140
-75
-30
Units
-800
-480
-250
IJ-A
IJ-A
IJ-A
mA
mA
mA
-1.4
-1.4
-1.2
Vee = 9.5V, VOH = 2.0V
Vee = 6.0V, VOH = 2.0V
-1.5
-1.5
-18
-13
mA
mA
-3.0
-3.0
-35
-25
mA
mA
Input Load Source Current
= 9.5V, VOH = 2.0V
= 6.0V, VOH = 2.0V
Vee = 9.5V, VOH = 5.5V
Vee = 6.3V, VOH = 3.2V
Vee = 4.5V, VOH = 1.5V
Vee = 9.5V, VOH = 5.5V
Vee = 6.3V, VOH = 3.2V
Vee = 4.5V, VOH = 1.5V
Vee = 5.0V, VIL = OV
CKO Output
RAM Power Supply Option
Power Requirement
VA
LED Configuration, Lo-L7
Outputs, High Current
Driver Option (IOH)
TRI-STATE Configuration,
Lo-L7 Outputs, Low
Current Driver Option (lOH)
TRI-STATE Configuration,
Lo-L7 Outputs, High
Current Driver Option (IOH)
Vee
Vee
-0.75
-0.8
-0.9
-1.5
-1.6
-1.8
mA
mA
mA
mA
mA
mA
-10
-140
IJ-A
3.0
mA
-2.5
+2.5
IJ-A
Total Sink Current Allowed
All Outputs Combined
D, G Ports
L7- L4
L3- LO
All Other Pins
120
120
4
4
1.5
mA
mA
mA
mA
mA
Total Source Current Allowed
All 1/0 Combined
L7- L4
L3-LO
Each L Pin
All Other Pins
120
60
60
30
1.5
mA
mA
mA
mA
mA
= 3.3V
TRI-STATE Output Leakage Current
1-206
o
o"'0
COP344L/COP345L
0l:Io
0l:Io
0l:Io
Absolute Maximum Ratings
If Military I Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Voltage at Any Pin Relative to GND
Ambient Storage Temperature
- 40·C to + 85·C
- 65·C to + 150·C
Lead Temperature (Soldering, 10 seconds)
120mA
Total Sink Current
120mA
Absolute maximum ratings indicate limits beyond which
damage to the device may occur. DC and AC electrical
specifications are not ensured when operating the device at
absolute maximum ratings.
-0.5V to + 10V
Ambient Operating Temperature
Total Source Current
300·C
r.......
o
o"'0
0l:Io
0l:Io
U1
r.......
o
o"'0
(,)
Power Dissipation
0.75 Watt at 25·C
0.25 Watt at 85·C
DC Electrical Characteristics
-40·C
Parameter
Standard Operating Voltage (VeC>
~
0l:Io
0l:Io
r.......
TA
~
+ 85·C, 4.5V
Conditions
(Note 1)
Optional Operating Voltage (VeC>
~
Vee
~
o
o"'0
7.5V unless otherwise noted.
Min
Max
Units
4.5
5.5
V
4.5
7.5
V
Power Supply Ripple
Peak to Peak
0.5
V
Operating Supply Current
All Inputs and Outputs Open
15
rnA
0.3
V
V
0.7 Vee
-0.3
0.4
V
V
0.7 Vee
-0.3
0.4
V
V
2.2
2.5
V
Input Voltage Levels
CKllnput Levels
Crystal Input
Logic High (VIH)
Logic High (VIH)
Logic Low (VIU
Vee = Max.
Vee = 5V ±5%
Schmitt Trigger Input
Logic High (VI H)
Logic Low (VIU
RESET Input Levels
Logic High
Logic Low
Logic High
Logic Low
r-
Schmitt Trigger Input
SO Input Level (Test Mode)
All Other Inputs
Logic High
Logic High
Logic Low
3.0
2.2
-0.3
(,)
0l:Io
U1
Vee = Max.
With TTL Trip Level Options
Selected, Vee = 5V ±5%
3.0
2.2
-0.3
0.6
V
V
V
With High Trip Level Options
Selected
3.6
-0.3
1.2
V
V
7
pF
-2
+2
,."A
0.4
V
V
0.2
V
V
Input Capacitance
Hi-Z Input Leakage
Output Voltage Levels
LSTTL Operation
Logic High (VOH)
Logic Low (VOU
Vee = 5V ±10%
IOH = -20,."A
IOL = 0.36 rnA
CMOS Operation (Note 2)
Logic High
Logic Low
IOH = -10,."A
IOL = +10,."A
Note 1: Vec voltage change must be less than 0.5V In a 1 ms period to maintain proper operation.
Note 2: TRI-STATE and LED configurations are excluded.
Note 3: SO output "0" level must be less than 0.6V for normal operation.
1-207
2.7
Vee- 1
III
COP344L/COP345L (Continued)
DC Electrical Characteristics
-40°C ~ T A ~ + 85°C, 4.5V ~ Vee ~ 7.5V unless otherwise noted. (Continued)
Parameter
Output Current Levels
Output Sink Current
SO and SK Outputs (Iou
Conditions
Vee
Vee
Vee
Lo-L7 Outputs, and Standard
GO-G3, 00- 0 3 Outputs (Iou
Vee
Vee
Vee
GO-G3 and 00-03 Outputs with
High Current Options (Iou
Vee
Vee
Vee
GO-G3 and 00-03 Outputs with
Very High Current Options (Iou
Vee
Vee
Vee
CKI (Single· Pin RC Oscillator)
CKO
Vee
Vee
Output Source Current
Standard Configuration,
All Outputs (IOH)
Vee
Vee
Vee
Push· Pull Configuration
SO and SK Outputs (IOH)
Vee
Vee
Vee
LED Configuration, LO-L7
Outputs, Low Current
Driver Option(IOH)
Vee
Vee
Vee
LED Configuration, Lo-L7
Outputs, High Current
Driver Option (lOH)
Vee
Vee
Vee
TRI·STATE Configuration,
Lo-L7 Outputs, Low
Current Driver Option (lOH)
Vee
Vee
Vee
TRI·STATE Configuration,
Lo-L7 Outputs, High
Current Driver Option (lOH)
Vee
Vee
Vee
Input Load Source Current
Vee
CKOOutput
RAM Power Supply Option
Power Requirement
VA
=
=
=
=
=
=
=
=
=
=
=
=
=
=
7.5V, VOL
5.5V, VOL
4.5V, VOL
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
7.5V, VOH
5.5V, VOH
4.5V, VOH
=
7.5V, VOL
5.5V, VOL
4.5V, VOL
7.5V, VOL
5.5V, VOL
4.5V, VOL
7.5V, VOL
5.5V, VOL
4.5V, VOL
4.5V, VIH
4.5V, VOL
= O.4V
= O.4V
= O.4V
= O.4V
= O.4V
= O.4V
= 1.0V
= 1.0V
= 1.0V
= 1.0V
= 1.0V
= 1.0V
= 3.5V
= 0.4V
= 2.0V
= 2.0V
= 2.0V
7.5V, VOH = 3.75V
5.5V, VOH = 2.0V
4.5V, VOH = 1.0V
7.5V, VOH = 2.0V
6.0V, VOH = 2.0V
5.5V, VOH = 2.0V
7.5V, VOH = 2.0V
6.0V, VOH = 2.0V
5.5V, VOH = 2.0V
7.5V, VOH = 4.0V
5.5V, VOH = 2.7V
4.5V, VOH = 1.5V
7.5V, VOH = 4.0V
5.5V, VOH = 2.7V
4.5V, VOH = 1.5V
5.0V, VIL = OV
Min
Units
1.4
1.0
0.8
rnA
rnA
rnA
0.4
0.4
0.4
rnA
rnA
rnA
12
9
7
rnA
rnA
rnA
24
18
14
rnA
rnA
rnA
2
0.2
rnA
rnA
-100
-55
-28
-900
-600
-350
-0.85
-1.1
-1.2
p,A
p,A
p,A
rnA
rnA
rnA
-1.4
-1.4
-0.7
-27
-17
-15
rnA
rnA
rnA
-2.7
-2.7
-1.4
-54
-34
-30
rnA
rnA
rnA
-0.7
-0.6
-0.9
rnA
rnA
rnA
-1.4
-1.2
-1.8
rnA
rnA
rnA
-10
3.3V
-5
TRI·STATF Output Leakage Current
Max
-200
p,A
4.0
rnA
+5
p,A
Total Sink Current Allowed
All Outputs Combined
0, G Ports
L7- L4
L3- LO
All Other Pins
120
120
4
4
1.5
rnA
rnA
rnA
rnA
rnA
Total Source Current Allowed
All I/O Combined
L7- L4
L3- LO
Each L Pin
All Other Pins
120
60
60
30
1.5
rnA
rnA
rnA
rnA
rnA
1·208
o
o"'C
AC Electrical Characteristics
COP444L1445L: o·c s: TA s: 70·C, 4.5V s: Vee s: 9.5V unless otherwise noted.
COP344L/345L: -40·C
s: TA s: + 85·C, 4.5V s: Vee s:
~
~
~
7.5V unless otherwise noted.
Parameter
Conditions
Instruction Cycle Time-ie
Min
Max
Units
16
40
/-Ls
C
o
o"'C
~
~
U1
CKI
Input Fre~uency-fl
Duty Cycle
Rise Time
Fall Time
CKI Using RC (+ 4)
+32 Mode
+16 Mode
+8 Mode
+4 Mode
fl
0.8
0.4
0.2
0.1
30
= 2 MHz
MHz
MHz
MHz
MHz
%
ns
ns
INPUTS:
IN3-INo, G3-GO, L7-Lo
tSETUP
tHOLD
SI
tSETUP
tHOLD
"'C
W
~
~
C
o
o"'C
~
U1
16
CKO as SYNC Input
tSYNe
r-
o
'"
o
W
R = 56kn ±5%
C = 100 pF ± 10%
Instruction Cycle Time (Note 1)
OUTPUT PROPAGATION DELAY
2.0
1.0
0.5
0.25
60
120
80
28
r-
/-Ls
400
ns
8.0
1.3
/-Ls
/-Ls
2.0
1.0
/-Ls
/-Ls
Test Condition:
CL = 50 pF, RL = 20 kn, VOUT = 1.5V
SO, SK Outputs
tpd1, tpdO
All Other Outputs
tpd1, tpdo
4.0
/-Ls
5.6
Jls
Note 1: Variation due to the device Included.
II
1-209
..J
II)
~
Cf)
a..
Connection Diagrams
0
Dual-In-Llne
0
......
..J
GNU
CKO
CKI
~
~
Cf)
a..
0
......
L7
L6
L5
l4
INI
IN2
..J
II)
~
~
a..
0
0......
VCC
L3
L2
L1
..J
~
~
~
a..
0
IiIID
L7
L6
L5
l4
VCC
L3
L2
Ll
TL/DD/6928-3
Top View
TL/DD/6928-2
0
DO
01
02
03
G3
G2
Gl
GO
SK
SO
SI
LO
GNO
CKO
CKI
DO
01
02
03
G3
G2
Gl
GO
IN3
INO
SK
SO
SI
LO
Rrm'
0
Dual-In-Llne
Order Number COP445L-XXX/N or COP345L-XXX/N
See NS Package Number N24A
Top View
Order Number COP444L-XXX/N or COP344L-XXX/N
See NS Package Number N28B
FIGURE 2
Pin Descriptions
Pin
L7-Lo
Gs-Go
Os-Do
IN3-INo
SI
SO
SK
Description
8 bidriectionall/O ports with TRI-STATE
4 bidirectional 110 ports
4 general purpose outputs
4 general purpose inputs (COP444L only)
Serial input (or counter input)
Serial output (or general purpose output)
Pin
CKI
Description
System oscillator input
CKO
System oscillator output (or general purpose input, RAM power supply, or SYNC input)
System reset input
Power supply
Ground
RESET
Vee
GND
Logic-controlled clock (or general purpose output)
Timing Diagrams
CKI
SKCLOCK
(ASA
G3-G~~~;~~~:
_....&.._ _ .
_ _ _ _ _ _ _ _ _.7.-_;-------~------
CKO&SI ---------~-"'------------INPUTS
GO. 0SO.
3- 0SK
G30. _ _ _ _ _ _ _ _ _ _.A.._ _ _
L7-LO.
OUTPUTS
TL/DD/6928-4
FIGURE 3a. Input/Output Timing Diagrams (Crystal Dlvlde-by-16 Mode)
-l
I-two
CKI
-=I
CKO
(INPUT)
I- twl
j
1-- tSYNC
+-_______
\ '-_ _ _ _
TL/DD/6928-5
FIGURE 3b. Synchronization Timing
1-210
Functional Description
The G register contents are outputs to 4 general-purpose
bidirectional I/O ports. G I/O ports can be directly connected to the digits of a multiplexed LED display.
A block diagram of the COP444L is given in Figure 1. Data
paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. Positive logic is
used. When a bit is set, it is a logic "1" (greater than 2
volts). When a bit is reset, it is a logic "0" (less than 0.8
volts).
The Q register is an internal, latched, 8-bit register, used to
hold data loaded to or from M and A, as well as 8-bit data
from ROM. Its contents are output to the L I/O ports when
the L drivers are enabled under program control. (See LEI
instruction.)
All functional references to the COP444L1COP445L also
apply to the COP344L1COP345L.
The 8 L drivers, when enabled, output the contents of
latched a data to the L I/O ports. Also, the contents of L
may be read directly into A and M. L I/O ports can be directly connected to the segments of a multiplexed LED display
(using the LED Direct Drive output configuration option) with
Q data being outputted to the Sa-Sg and decimal point
segments of the display.
PROGRAM MEMORY
Program Memory consists of a 2048 byte ROM. As can be
seen by an examination of the COP444L1445L instruction
set, these words may be program instructions, program data
or ROM addressing data. Because of the special characteristics associated with the JP, JSRP, JID, and LaiD instructions, ROM must often be thought of as being organized into
32 pages of 64 words each.
The SIO register functions as a 4-bit serial-in/serial-out shift
register or as a binary counter depending on the contents of
the EN register. (See EN register description, below.) Its
contents can be exchanged with A, allowing it to input or
output a continuous serial data stream. SIO may also be
used to provide additional parallel I/O by connecting SO to
external serial-in/parallel-out shift registers.
ROM addressing is accomplished by a 11-bit PC register. Its
binary value selects one of the 2048 8-bit words contained
in ROM. A new address is loaded into the PC register during
each instruction cycle. Unless the instruction is a transfer of
control instruction, the PC register is loaded with the next
sequential 11-bit binary count value. Three levels of subroutine nesting are implemented by the 11-bit subroutine save
registers, SA, SB, and SC, providing a last-in, first-out (LIFO)
hardware subroutine stack.
The XAS instruction copies C into the SKL latch. In the
counter mode, SK is the output of SKL; in the shift register
mode, SK outputs SKL ANDed with the clock.
The EN register is an internal 4-bit register loaded under
program control by the LEI instruction. The state of each bit
of this register selects or deselects the particular feature
associated with each bit of the EN register (EN3-ENo).
ROM instruction words are fetched, decoded and executed
by the Instruction Decode, Control and Skip Logic circuitry.
DATA MEMORY
1. The least significant bit of the enable register, ENo, selects the SIO register as either a 4-bit shift register or a 4bit binary counter. With ENo set, SIO is an asynchronous
binary counter, decrementing its value by one upon each
low-going pulse ("1" to "0") occurring on the SI input.
Each pulse must be at least two instruction cycles wide.
SK outputs the value of SKL. The SO output is equal to
the value of EN3. With ENo reset, SIO is a serial shift
register shifting left each instruction cycle time. The data
present at SI goes into the least significant bit of SIO. SO
can be enabled to output the most significant bit of SIO
each cycle time. (See 4 below.) The SK output becomes
a logic-controlled clock.
Data memory consists of a 512-bit RAM, organized as 8
data registers of 16 4-bit digits. RAM addressing is implemented by a 7-bit B register whose upper 3 bits (Br) select 1
of 8 data registers and lower 4 bits (Bd) select 1 of 16 4-bit
digits in the selected data register. While the 4-bit contents
of the selected RAM digit (M) is usually loaded into or from,
or exchanged with, the A register (accumulator), it may also
be loaded into or from the a latches or loaded from the L
ports. RAM addressing may also be performed directly by
the LDD and XAD instructions based upon the 7-bit contents of the operand field of these instructions. The Bd register also serves as a source register for 4-bit data sent
directly to the D outputs.
2. With EN1 set the IN1 input is enabled as an interrupt input. Immediately following an interrupt, EN1 is reset to
disable further interrupts.
INTERNAL LOGIC
The 4-bit A register (accumulator) is the source and destination register for most I/O, arithmetic, logic and data memory
access operations. It can also be used to load the Br and Bd
portions of the B register, to load and input 4 bits of the 8-bit
a latch data, to input 4 bits of the 8-bit L I/O port data and
to perform data exchanges with the SIO register.
3. With EN2 set, the L drivers are enabled to output the data
in Q to the L I/O ports. Resetting EN2 disables the L
drivers, placing the L I/O ports in a high-impedance input
state.
4. EN3, in conjunction with ENo, affects the SO output. With
ENo set (binary counter option selected) SO will output
the value loaded into EN3. With ENo reset (serial shift
register option selected), setting EN3 enables SO as the
output of the SIO shift register, outputting serial shifted
data each instruction time. Resetting EN3 with the serial
shift register option selected disables SO as the shift register output; data continues to be shifted through SIO and
can be exchanged with A via an XAS instruction but SO
remains reset to "0". The table below provides a summary of the modes associated with EN3 and ENo.
A 4-bit adder performs the arithmetic and logic functions,
storing its results in A. It also outputs a carry bit to the 1-bit
C register, most often employed to indicate arithmetic overflow. The C register, in conjunction with the XAS instruction
and the EN register, also serves to control the SK output. C
can be outputted directly to SK or can enable SK to be a
sync clock each instruction cycle time. (See XAS instruction
and EN register descriptor, below.)
Four general-purpose inputs, IN3-INo, are provided.
The D register provides 4 general-purpose outputs and is
used as the destination register for the 4-bit contents of Bd.
The D outputs can be directly connected to the digits of a
multiplexed LED display.
1-211
~ r-------------------------------------------------------------------~
Ln
"'IIiI'
C")
Functional Description
(Continued)
D.
o
o
'"
"III:t
Enable Register Modes-Bits EN3 and ENo
~
EN3
ENo
SIO
SI
SO
"III:t
0
0
Shift Register
Input to Shift Register
0
Serial Out
C")
SK
If SKL = 1, SK =
If SKL = 0, SK =
If SKL = 1, SK =
If SKL = 0, SK =
If SKL = 1, SK =
If SKL = 0, SK =
If SKL = 1, SK =
If SKL = 0, SK =
D.
o
o
::3
Ln
1
0
Shift Register
Input to Shift Register
0
1
Binary Counter
Input to Binary Counter
0
D.
1
1
Binary Counter
Input to Binary Counter
1
"III:t
"III:t
o
o
::3
"'IIiI'
"'IIiI'
"'IIiI'
D.
o
o
CLOCK
0
CLOCK
0
1
0
1
0
INTERRUPT
INITIALIZATION
The following features are associated with the IN1 interrupt
procedure and protocol and must be considered by the programmer when utilizing interrupts.
The Reset Logic will initialize (clear) the device upon powerup if the power supply rise time is less than 1 ms and greater than 1 J.Ls. If the power supply rise time is greater than 1
ms, the user use provide an external RC network and diode
to the RESET pin as shown below. If the RC network is not
used, the RESET pin must be pulled up to Vee either by the
internal load or by an external resistor (~40 kO) to Vee.
The RESET pin is configured as a Schmitt trigger input. Initialization will occur whenever a logic "0" is applied to the
RESET input, provided it stays low for at least three instruction cycle times.
a. The interrupt, once acknowledged as explained below,
pushes the next sequential program counter address
(PC + 1) onto the stack, pushing in turn the contents of
the other subroutine-save registers to the next lower level
(PC + 1 ~ SA ~ SB ~ SC). Any previous contents of SC are lost. The program counter is set to hex
address OFF (the last word of page 3) and EN1 is reset.
b. An interrupt will be acknowledged only after the following
conditions are met:
p +
0
~~
w
1. EN1 has been set.
2. A low-going pulse ("1" to "0") at least two instruction
cycles wide occurs on the IN1 input.
3. A currently executing instruction has been completed
4. All successive transfer of control instructions and successive LBls have been completed (e.g., if the main
program is executing a JP instruction which transfers
program control to another JP instruction, the interrupt
will not be acknowledged until the second JP instruction has been executed.
c. Upon acknowledgement. of an interrupt, the skip logic
status is saved and later restored upon popping of the
stack. For example, if an interrupt occurs during the execution of ASC (Add with Carry, Skip on Carry) instruction
which results in carry, the skip logic status is saved and
program control is transferred to the interrupt servicing
routine at hex address OFF. At the end of the interrupt
routine, a RET instruction is executed to "pop" the stack
and return program control to the instruction following the
original ASC. At this time, the skip logic is enabled and
skips this instruction because of the previous ASC carry.
Subroutines and LOID instructions should not be nested
within the interrupt service routine, since their popping the
stack will enable any previously saved main program
skips, interfering with the orderly execution of the interrupt routine.
d. The first instruction of the interrupt routine at hex address
OFF must be a Nap.
e. A LEI instruction can be put immediately before the RET
to re-enable interrupts.
~~
E
R
S
U
~~
~
I
vee
~
~
RESET
P
::::
p
L
y
-
GND
J
-
TL/DD/6928-6
RC
~
5 x Power Supply Rise Time (R
~
40k)
Power-Up Clear Circuit
Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, D, EN, and G registers are cleared.
The SK output is enabled as a SYNC output, providing a
pulse each instruction cycle time. Data Memory (RAM) is
not cleared upon initialization. The first instuction at address
o must be a CLRA.
OSCILLATOR
There are four basic clock oscillator configurations available
as shown by Figure 4.
a. Crystal Controlled Oscillator. CKI and CKO are connected to an external crystal. The instruction cycle time
equals the crystal frequency divided by 32 (optional by 16
or 8).
b. External Oscillator. CKI is an external clock input signal.
The external frequency is divided by 32 (optional by 16 or
8) to give the instruction cycle time. CKO is now available
to be used as the RAM power supply (VA), as a general
purpose input.
c. RC Controlled Oscillator. CKI is configured as a single
pin RC controlled Schmitt trigger oscillator. The instruction cycle equals the oscillation frequency divided by 4.
CKO is available as the RAM power supply (VA) or as a
general purpose input.
1-212
o
Functional Description
CKI
c. Push-Pull-An enhancement-mode device to ground in
conjunction with a depletion-mode device paralleled by
an enhancement-mode device to Vee. This configuration
has been provided to allow for fast rise and fall times
when driving capacitive loads. Available on SO and SK
outputs only.
d. Standard L-same as a., but may be disabled. Available
on L outputs only.
e. Open Drain L-same as b., but may be disabled. Available on L outputs only.
f. LED Direct Drive-an enhancement-mode device to
ground and to Vee, meeting the typical current sourcing
requirements of the segments of an LED display. The
sourcing device is clamped to limit current flow. These
devices may be turned off under program control (See
Functional Description, EN Register), placing the outputs
in a high impedance state to provide required LED segment blanking for a multiplexed display. Available on L
outputs only.
(Continued)
CKO
CKI
CKO
.!- "'~.,...VCC
.....
(VR OR GENERAL
YYY
~
...flJ
t
PURP~~~iNPUT
(VR OR GENERAL
PURPOSE INPUT
OR SYNC PIN)
EXTERNAL
CLOCK
TLlDD/6928-7
Crystal
Value
R1 (0)
R2(0)
C1 (pF)
C2 (pF)
455 kHz
2.097 MHz
4.7k
1k
1M
1M
220
30
220
6-36
to ground and Vee. These outputs are TRI-STATE outputs, allowing for connection of these outputs to a data
bus shared by other bus drivers. Available on L outputs
only.
COP444L1COP445L inputs have the following optional configurations:
h. An on-chip depletion load device to Vee.
I. A Hi-Z input which must be driven to a "1" or "0" by
external components.
The above input and output configurations share common
enhancement-mode and depletion-mode devices. Specifically, all configurations use one or more of six devices
(numbered 1-6, respectively). Minimum and maximum current (lOUT and VOUT curves are given in Figure 6for each of
these devices to allow the designer to effectively use these
I/O configurations in designing a system.
The SO, SK outputs can be configured as shown in a., b., or
c. The D and G outputs can be configured as shown in a. or
b. Note that when inputting data to the G ports, the G outputs should be set to "1". The L outputs can be configured
in d., e., f. or g.
An important point to remember if using configuration d. or
1. with the L drivers is that even when the L drivers are
disabled, the depletion load device will source a small
amount of current (see Figure 6, device 2); however, when
the L-lines are used as inputs, the disabled depletion device
can not be relied on to source sufficient current to pull an
input to logiC "1".
RC Controlled Oscillator
R(kO)
C(pF)
Instruction
Cycle Time
(its)
51
82
100
56
19 ± 15%
19 ± 13%
~
~
R
C
~
~
r
.......
o
o"'tJ
~
~
U1
r
.......
o
o"'tJ
W
~
~
r
.......
o
o"'tJ
W
~
U1
r
g. TRI-STATE Push-Pull-an enhancement-mode device
Component Values
360 pF
~
~
~
Note: Series current limiting resistors have to be used if the higher operating voltage option is selected and LEOs are driven directly.
Crystal Oscillator
NOTE: 200 k!l
o"'tJ
25 k!l
50 pF
FIGURE 4. COP444L/445L Oscillator
CKO PIN OPTIONS
In a crystal controlled oscillator system, CKO is used as an
output to the crystal network. As an option CKO can be a
general purpose input, read into bit 2 of A (accumulator)
upon execution of an INIL instruction. As another option,
CKO can be a RAM power supply pin (VR), allowing its connection to a standby/backup power supply to maintain the
integrity of RAM data with minimum power drain when the
main supply is inoperative or shut down to conserve power.
Using either option is appropriate in applications where the
COP444L/445L system timing configuration does not require use of the CKO pin.
RAM KEEP-ALIVE OPTION
Selecting CKO as the RAM power supply (VR) allows the
user to shut off the chip power supply (Vee> and maintain
data in the lower four (Br = 0, 1, 2, 3) registers of RAM. To
insure that RAM data integrity is maintained, the following
conditions must be met:
I/O OPTIONS
COP444L1445L outputs have the following optional configurations, illustrated in Figure 5.
a. Standard-an enhancement mode device to ground in
conjunction with a depletion-mode device to Vee, compatible with LSTTL and CMOS input requirements. Available on SO, SK, and all D and G outputs.
b. Open-Draln-an enhancement-mode device to ground
only, allowing external pull-up as required by the user's
application. Available on SO, SK, and all D and G outputs.
1. RESET must go low before Vee goes low during power
off; Vee must go high before RESET goes high on powerup.
2. VR must be within the operating range of the chip, and
equal to Vee ± 1V during normal operation.
3. VR must be
1-213
~
3.3V with Vee off.
III
~ r-------------------------------------------------------------------------~
Ln
-.::t
('I)
a.
o
o
"-.::t
~
-.::t
Functional Description
(Continued)
COP445L
the four general purpose IN inputs (IN3-INo). Use of this
option precludes, of course, use of the IN options and the
interrupt feature, which uses IN1. All other options are available for the COP445L.
If the COP444L is bonded as a 24-pin device, it becomes
the COP455L, illustrated in Figure 2, COP444L1445L Connection Diagrams. Note that the COP445L does not contain
('I)
a.
oo
"Ln
~
-.::t
-.::t
a.
o
o
"-.::t
~
-.::t
-.::t
TL/DD/692B-10
TL/DD/692B-9
a. Standard Output
b. Open·Draln Output
TL/DD/692B-11
c. Push·Pull Output
a.
oo
DISABLE~~
•
TL/DD/692B-13
TL/DD/692B-12
e. Open·Draln L Output
TL/DD/692B-14
(& is Depletion Device)
f. LED (L Output)
d. Standard L Output
vee
IN,urAf
TL/DD/692B-15
g. TRI·STATE Push·Pull (L Output)
IN,ur~~
TL/DD/692B-17
TL/DD/692B-16
h. Input with Load
FIGURE 5. Output Configuration
1-214
I. HI·Z Input
o
o-a
Typical Performance Characteristics
Current for Inputs with
Load Device
-100
-10
-70
l
II.
co
~
-10
-50
-zo
-10
U
,
,
"
'\
-800
"'
-700
r\.
~
"""~
~.II.D
IN1v~r
'"~
r-T.--.r--n--.---.--,.---.~-.=-"
~
1.0 Hft-i--ll-+--+-H~i-t-+--i
Source Current for La through
L71n TRI-STATE configuration (Low Current Option)
1.5
'M'N~l
.. 9.5V
\
~Ci4.5V
0.5
~IN@
1
2 3
4
5
6
VOH(VOLTS)
7
B e 10
DEVICE c#2
. AND #3
o
1
5
l1lT 1
2 3
4
5
6 7
VOH(VOLTS)
DEVICE
g#5
B 9 10
r'"
rtV
MIN@-f-
1.0
IMAX@
0.5
0.5
w
vcc-e.5v
\~:.lx~
II'M9.5VU@
vcc-
rl'V
C
o
o-a
~
VDH (YOLTS)
\
1.0
U
012345878
2.0
Source Current for Lo through
L71n TRI-STATE Configuration (High Current Option)
,
~
~
I, ~M~~ _ 8.&\
-100
~
~
w
"-I"\.
~
-""~
o r-_ ..... "'" ~f+- 100.. i':
.....
1.0
1.5
1'\.J
-zoo
~
o
o-a
o-a
' \ IMAX OVCC· UV
lJ':AXO
r......
r'"
......
o
-400 sec·u~
-300 -'~7~MIN'
Vej:- .iVI
V 110
Source Current for SO and SK
In Push-Pull Configuration
o
"'
-100
~ -500
r\.
I MAX}
VCC ·UV
o
o
DEVICE. #z
ANI d #z
-800
l
VIN (YOLTS)
1.5
-1000
IMAX' Vee· 1.5V
-40
-3D
Source Current for Standard
Output Configuration
DEVICE d #2
AND I #2
-80
1.0 Z.O 3.0 4.0 5.0 •. 0 7.0 •. 0
~
~
~
Input Current for La through L7
when Output Programmed Off
by Software
IMAX@
~C.4.
IMIN~
l1li4.5
o
1
2 3
4
5
DEVICE
\
6
7
g#5
B 9 10
VOH(VOLTS)
TL/DD/692B-1B
III
1-215
-oJ
1.1)
'OII:t
Cf)
Typical Performance Characteristics
(Continued)
D-
o
LED Output Direct Segment Drive
High Current Options on Lo-L7
Very High Current Options on
00-03 or Go-G3
o
......
-oJ
LED Output Source Current
(for Low Current LED Option)
LED Output Source Current
(for High Current LED Option)
'OII:t
'OII:t
Cf)
D-
~or-~~~~~~-r-r-r-'
-oJ
-30
O
o......
-50 ......--,.----..---.--~-..__---.
DEVICE' #2 AND #4
A~D DEV1ICE. OR b #1
~0~~--+-4--+---+-~
IM~X
-15 ~+--¥-+--+\-
'OII:t
'OII:t
D-
O
o
......
I
ONE SEGEMENT
1.1)
1:c
C
.! -20
§
-oJ
C
.5
-10
E
§
-10
'OII:t
'OII:t
'OII:t
D-
o
o
-20
-10
o~~~~~~~~
O
1
2
3
4
5
6
7
__
8
~---l--+~/~-+--boo'~
... ~ . . . V
•••••
~ IMAX EIGHT
•••
.'
SEGMENTS ON•••••• ••••••
IMIN
1
3
10
4
5
6
7
8
9 10
VOH (VOLTS)
LED Output Direct Segment
Drive
VOH· 2.0 V
1
O~:~··~·~··_··_··~·_~_~_~~
10
4
~
9
VOH (VOLTS)
-60
I
oyr--
-30~-4--+-~/~~--t-~
VCC (VOLTS)
Output Sink Current for Lo-L7
and Standard Drive Option for
00-03 and GO-G3
Output Sink Current for SO
andSK
DEVICE'
#2 AND #4
~o
C
-30
.!
:c
Q
-20
..
....
-10
0
10
4
VCC (VOLTS)
Output Sink Current
GO-G3 and 00-03 with Very
High Current Option
Output Sink Current for GO-G3
and 00-03 (for High Current
Option
120 .--.,.-r-.....-....--r-.....-r=~-,
100
VOLlVOlTS)
VoLlVOLTS)
120 r--r-Irr--'T""""T""-r--.------,
I-+H-+-t-~+-+-
<
<
~
~ 60
60 I-f----F-+--t--t-_r-±:=-Ioo-+-i
40H+~+-+-~~_r_r-+_+~
2 3
4
5
6
8
0123456
9 10
8
9 10
VOLlVOlTS)
VoLlVOlTS)
TL/DD/6928-19
FIGURE 6a. COP444L/COP445L Input/Output Characteristics
1-216
o
Typical Performance Characteristics
a"tJ
(Continued)
~
~
~
Input Current for LO-L7
when Output Programmed
Off by Software
-120 r - - - - , - - , - - - . . - - - ,
DEVICE d '2
AND I '2
-100 I-'\~-I----+---t----I
Input Current INo-IN3
.
~
o
-1. 2 r-,-~-..--r-..,...--'---'--,
DEVICE I. 12
Ind d 12
-1.0 I--'.....-I--I-+--+--t--+--I
- 0.8 I--+--'l.:-=-=-t--+--+,-jl-+--I
~ -80
....
r.......
Source Current for
Standard Output
Configuration
-60t--~~--+--~~---I
;(
E
~ -06
5: -40
- 0.4
t--p.~-t-+'-.t-~f'--+--I
-20
-0.2
Io::::::-+--I-~H+--+~~+--I
OL.--I---L=l::!Ioooloillo....L.---J=::Ioi1I......
0.5
o
1.5
VI/O (VOLTSI
Source Current for SO
and SK In Push-Pull
Configuration
1.5 I"'""'Ir-r----r-.-,.,.--.-.....".....",DE""V""IC""E-C""'#2:"1
AND #3
1.5
1.0 t--ft--+-t-lH+--H-t-+--t
1.0
0.5
o
• I
I
..
IMAX@
;'Il TO"
o
3
-
::r::
~
U1
3
4
__-'
Output Sink Current for
SO and SK
4nn__~~--~--~--~
-40
III
-3D
0
-20
-10
o "'--"---_....L..._-'-_--'-_.....J
0
0
o
1
VOH (VOLTSI
VOH (VOLTS)
Output Sink Current for
Lo-L7 and Standard Drive
Option for 00-03 and GO-G3
4
120
DEVICE 1#1 AND b#l
I
I
~
3
Output Sink Current for
GO-G3 and 00-03 (for
High Current Option)
120 r--'-'TT'-r-'-~-.--.............,
I
IMAX @ VCC-7.5V
100
..
2
VOL(VDLTS)
Output Sink Current GO-G3
and 00-03 with Very High
Current Option
..-r-rr---~--~_-r---~
I
I
I
IMAX @ Vce .. 4.5V
80
60
40 ~~~-+~r-+--t--+--t
20
o L..__"--__" ' -__-'--__.....__-'
o L.........-I..--'__-'--.....L..--I._ _"---'
o
o
VOLIVOLTS)
r-
VOH(VOLTS)
DEVICE I
'2 AND U
!.
"tJ
w
4
0.5
4
-60..-'-~-r-'-~-~
.
o
a
~
LED Output Source
Current (for High Current
LED Option
LED Output Source
Current (for Low Current
LED Option
-30r-'--T__~~~~--r-~
~
~
r.......
1.0 t--H-I--tl-+--I-f-i--I--I
VOH(VOLTS)
VOH(VOLTS)
a"tJ
E
I
--I IMAX@
r.......
o
1.5 r--"T""-,--rr-.r-r---n'""o:":ev""I'-:'e="E-g"'''''''5
DeVICE 9#5
-
3
VOH (VOLTS)
IMIN@
IMIN@
VCC .. 4.5V VCC=7.5V
0.5
1
Source Current for LO-L7
In TRI-STATE Configuration (Low Current Option)
Source Current for LO-L7
In TRI-STATE Configuration (High Current Option)
~
~
U1
w
:::>
VIN (VOLTS)
a"tJ
3
4
0--"'---'-.........-"'--"'--.....;;.;;........--'
3 4
o
VOLIVOLTS)
VOLIVOLTSI
TLlDD/6928-20
Fiare 6b. COP344L/COP345L Input/Output Characteristics
1-217
-J
r-----------------------------------------------------------------------------------~
II)
~
Cf)
a.
o(,)
.....
-J
COP444L/COP445L/COP344L/COP345L Instruction Set
Table I is a symbol table providing internal architecture, instruction operand and operational symbols used in the instruction set table.
~
~
Table II provides the mnemonic, operand, machine code,
data flow, skip conditions and description associated with
each instruction in the COP444L/445L instruction set.
TABLE I. COP444L/445L/344L/345L Instruction Table Symbols
Cf)
a.
o(,)
Symbol
:l
INTERNAL ARCHITECTURE SYMBOLS
INSTRUCTION OPERAND SYMBOLS
~
~
A
B
Br
Bd
C
D
EN
G
IL
d
r
II)
a.
o(,)
.....
-J
~
~
~
a.
o(,)
IN
L
M
PC
Q
SA
S8
SC
SIO
SK
Definition
Symbol
4-bit Accumulator
6-bit RAM Address Register
Upper 3 bits of 8 (register address)
Lower 4 bits of 8 (digit address)
1-bit Carry Register
4-bit Data Output Port
4-bit Enable Register
4-bit Register to latch data for G I/O Port
Two 1-bit latches associated with the IN3 or
INo inputs
4-bit Input Port
8-bit TRI-STATE I/O Port
4-bit contents of RAM Memory pointed to by 8
Register
11-bit ROM Address Register (program counter)
8-bit Register to latch data for L I/O Port
11-bit Subroutine Save Register A
11-bit Subroutine Save Register 8
11-bit Subroutine Save Register C
4-bit Shift Register and Counter
Logic-Controlled Clock Output
Definition
4-bit Operand Field, 0-15 binary (RAM Digit Select)
3-bit Operand Field, 0-7 binary (RAM Register
Select)
a
11-bit Operand Field, 0-2047 binary (ROM Address)
y
4-bit Operand Field, 0-15 binary (Immediate Data)
RAM(s) Contents of RAM location addressed by s
ROM(t) Contents of ROM location addressed by t
OPERATIONAL SYMBOLS
+
-+
~
=
A
e
:
Plus
Minus
Replaces
Is exchanged with
Is equal to
The one's complement of A
Exclusive-OR
Range of values
TABLE II. COP444L/445L Instruction Set
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
DataFlow
Skip Conditions
Description
ARITHMETIC INSTRUCTIONS
ASC
30
10011100001
ADD
31
1001110001
ADT
4A
A + C + RAM(8) -+ A
Carry -+ C
Carry
Add with Carry, Skip on
Carry
A + RAM(8) -+ A
None
Add RAMtoA
10100110101
A + 1010 -+ A
None
AddTentoA
5-
10101
A+y-+A
Carry
Add Immediate, Skip on
Carry (y =1= 0)
CASC
10
10001100001
A + RAM(8) + C -+ A
Carry -+ C
Carry
Complement and Add with
Carry, Skip on Carry
CLRA
00
10000100001
O-+A
None
Clear A
COMP
40
10100100001
A-+A
None
Ones complement of A to A
NOP
44
10100101001
None
None
No Operation
RC
32
10011100101
"0" -+ C
None
ResetC
SC
22
10010100101
"1" -+ C
None
SetC
AISC
y
I
y
I
I
1-218
o
o
Instruction Set (Continued)
-a
~
~
~
TABLE II. COP444L/445L Instruction Set (Continued)
Mnemonic Operand
~oe:e
r.......
Machine
Language Code
(Binary)
Data Flow
Description
Skip Conditions
~
~
TRANSFER OF CONTROL INSTRUCTIONS
XOR
02
10000100101
JID
FF
1111111111
I
6-
10110 I0 1a10:81
I a7:0
I
--
11 I ~"Q 1 a ~ PC6:0
(pages 2,3 only)
or
1111 as:o I a ~ PCs:o
(all other pages)
JMP
a
JP
a
--
-JSRP
JSR
a
a
-- pO I
6-
as:o
A ED RAM (B)
A
~
None
Exclusive-OR RAM with A
ROM (PC10:81 A,M) ~
PC7:0
None
Jump Indirect (Note 3)
a
None
Jump
~
1 PC
+1
PC
+1
48
10100110001
SC
~
RETSK
49
10100110011
SC
~
Jump within Page
. (Note4)
None
Jump to Subroutine Page
(Note 5)
~
Jump to Subroutine
SA
~
SB
None
SB
~
SA
~
PC None
SB
~
SA
~
PC Always Skip on Return Return from Subroutine
then Skip
SC
a ~ PC
~
Return from Subroutine
33
3C
10011100111
10011111001
A ~ Q7:4
RAM (B) ~ Q3:0
None
Copy A, RAM to Q
CQMA
33
2C
10011100111
1001011100 I
Q7:4 ~ RAM (B)
None
Copy Q to RAM, A
-5
100lrl01011
(r - 0:3)
RAM (B) ~ A
Br ED r ~ Br
None
Load RAM into A
Exclusive-OR Br with r
23
10010100111
RAM(r,d)
None
Load A with RAM pointed
to directly by r,d
None
Load Q Indirect (Note 3)
r,d
LQID
--
Q3:0~A
~
A
~
BF
11011 11111 1
ROM(PC10:B A,M)
SB ~ SC
I
~
Q
RMB
0
1
2
3
4C
45
42
43
10100111001
10100101011
10100100101
10100100111
o~
o~
o~
o~
RAM(B)o
RAM(Bh
RAM(B)2
RAM(Bb
None
Reset RAM Bit
5MB
0
1
2
3
40
47
46
4B
10100111011
10100111011
10100101101
10100110111
1
1
1
1
~
~
~
~
RAM(B)o
RAM(B)1
RAM(B)2
RAM(B)3
None
Set RAM Bit
Y
7-
10111 1 't 1
y ~ RAM (B)
Bd + 1 ~ Bd
None
Store Memory Immediate
and Increment Bd
X
r
-6
100 1rl 0110 1
(r = 0:3)
RAM(B) ~ A
Br ED r ~ Br
None
Exchange RAM with A,
Exclusive-OR Br with r
XAD
r,d
23
10010100111
111 r I d 1
RAM (r,d)
None
Exchange A with RAM
pointed to directly by r,d
STII
--
o-a
(,,)
~
CAMQ
LDD
~
~
r.......
U1
MEMORY REFERENCE INSTRUCTIONS
r
o-a
r-
~ SA ~ SB
SC
00010 ~ PC10:6
a ~ PCs:o
RET
r.......
o
o
None
~
10110111a1Q"el
I a7:0 I
U1
(,,)
PC
--
LD
o
o-a
~
A
1·219
Instruction Set (Continued)
TABLE II. COP444L/445L Instruction Set (Continued)
Mnemonic Operand
Hex
Code
Machine
Language Code
(Binary)
Skip Conditions
DataFlow
Description
MEMORY REFERENCE INSTRUCTIONS (Continued)
XDS
r
-7
100 1r 10111 1
(r = 0:3)
RAM(B) +-+ A
Bd -1 -+ Bd
Br e r -+ Br
Bd decrements past 0
XIS
r
-4
100 1r 10100 I
(r = 0:3)
RAM (B) +-+ A
Bd + 1 -+ Bd
Br e r -+ Br
Bd increments past 15 Exchange RAM with A
and Increment Bd,
Exclusive-OR Br with r
Exchange RAM with A
and Decrement Bd,
Exclusive-OR Br with r
REGISTER REFERENCE INSTRUCTIONS
CAB
50
10101100001
A -+ Bd
None
Copy Ato Bd
CBA
4E
10100111101
Bd -+ A
None
Copy BdtoA
--
100 I r I (d - 1) I
(r = 0:3;
d = 0,9:15)
or
r,d -+ B
Skip until not a LBI
'Load B Immediate with
r,d (Note 6)
33
--
1001110011 I
11 I r 1 d I
anyr, any d)
33
6-
1000110011 I
10110 1 Y.. I
y -+ EN
None
Load EN Immediate (Note 7)
12
10001100101
A +-+ Br (0 -+ A3)
None
Exchange A with Br
SKC
20
1001010000
Skip if C is True
SKE
21
1001010001
= "1"
A = RAM(B)
SKGZ
33
21
1001110011
1001010001
G3:0 = 0
Skip if G is Zero
(all 4 bits)
0
1
2
3
33
01
11
03
13
1001110011
1000010001
1000110001
1000010011
1000110011
0
1
2
3
01
11
03
13
1000010001
1000110001
1000010011
1000110011
41
1010010001
LBI
LEI
r,d
y
XABR
TEST INSTRUCTIONS
SKGBZ
SKMBZ
SKT
C
Skip if A Equals RAM
Skip if G Bit is Zero
1st byte
Go = 0
G1 = 0
G2 = 0
G3 = 0
} 2nd byte
I
I
I
I
I
I
I
RAM(B)o = 0
RAM(B)1 == 0
RAM(B)2 = 0
RAM(B)3 = 0
Skip if RAM Bit is Zero
A time-base counter
carry has occurred
since last test
Skip on Timer
(Note 3)
INPUTIOUTPUT INSTRUCTIONS
ING
33
2A
1001110011 I
1001011010 I
G-+A
None
Input G Ports to A
ININ
33
28
33
29A
1001110011 I
10010110001
1001110011 I
10010110011
IN -+ A
None
IL3, CKO, "0", ILa -+ A
None
Input IN Inputs to A
(Note 2)
Input IL Latches to A
(Note 3)
INIL
1-220
o
o
Instruction Set (Continued)
"'0
~
~
~
TABLE II. COP444L/445L Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
r.......
Machine
Language Code
(Binary)
Skip Conditions
Data Flow
Description
08D
OGI
y
o"'0
~
~
INPUT/OUTPUT INSTRUCTIONS (Continued)
INL
o
U1
33
2E
10011 10011 1
10010111101
L7:4 ~ RAM(8)
L3:0 ~ A
33
3E
10011100111
10011 11110 1
8d
33
5-
10011 10011 1
10101 1 t 1
y~G
33
3A
10011100111
10011110101
RAM(8)
4F
1010011111 1
A
~
None
D
None
Input L Ports to RAM, A
Output 8d to D Outputs
None
Output to G Ports
Immediate
None
Output RAM to G Ports
r.......
o
o"'0
(,)
~
~
r.......
o
o"'0
(,)
OMG
XAS
~
G
~
U1
r~
SID, C
~
SKL
None
Exchange A with SID
(Note 3)
Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to N where
o signifies the least significant bit (low-order, right-most bit). For example, A3 indicates the most significant (left-most) bit of the 4-bit A register.
Note 2: The ININ instruction is not available on the 24-pin COP445L or COP345L since these devices do not contain the IN inputs.
Note 3: For additional information on the operation of the XAS, JID, LQID, INIL, and SKT instructions, see below.
Note 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction,
otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Note 5: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of Pl. A JSRP may not be used when in pages 2 or 3. JSRP
may not jump to the last word in page 2.
Note 6: LBI is a single-byte instruction if d = 0, 9, 10, 11, 12, 13, 14 or 15. The machine code for the lower 4 bits equals the binary value of the "d" data minus 1,
e.g., to load the lower four bits of B (Bd) with the value 9 (10012), the lower 4 bits of the LBI instruction equal 8 (10002)' To load 0, the lower 4 bits of the LBI
instruction should equal 15 (11112)'
Note 7: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a "1" or "0" in each bit of EN corresponds
with the selection or deselection of a particular function aSSOCiated with each bit. (See Functional Description, EN Register.)
Description of Selected Instructions
The following information is provided to assist the user in
understanding the operation of several unique instructions
and to provide notes useful to programmers in writing
COP444L1445L programs.
XAS (Exchange A with SID) exchanges the 4-bit contents of
the accumulator with the 4-bit contents of the 510 register.
The contents of 510 will contain serial-in/serial-out shift register or binary counter data, depending on the value of the
EN register. An XAS instruction will also affect the SK output. (See Functional Description, EN Register, above.) If
510 is selected as a shift register, an XAS instruction must
be performed once every 4 instruction cycles to effect a
continuous data stream.
INo inputs since the last INIL instruction, provided the input
pulse stays low for at least two instruction times. Execution
of an INIL inputs IL3 and ILo into A3 and AO respectively,
and resets these latches to allow them to respond to subsequent low-going pulses on the IN3 and INo lines. If CKO is
mask programmed as a general purpose input, an INIL will
input the state of CKO into A2. If CKO has not been so
programmed, a "1" will be placed in A2. A "0" is always
placed in A1 upon the execution of an INIL. The general
purpose inputs IN3-INo are input to A upon execution of an
ININ instruction. (See Table II, ININ instruction.) INIL is useful in recognizing pulses of short duration or pulses which
occur too often to be read conveniently by an ININ instruction.
Note: IL latches are not cleared on reset; IL3-ILo not input on 445L
JID INSTRUCTION
LQID INSTRUCTION
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location pointed
to indirectly by A and M. It loads the lower a bits of the ROM
address register PC with the contents of ROM addressed by
the 11-bit word, PC1O:B, A, M. PC10, PCg and PCB are not
affected by this instruction.
Note that JID requires 2 instruction cycles to execute.
LaiD (Load a Indirect) loads the a-bit a register with the
contents of ROM pointed to by the 11-bit word PC10, PCg,
PCB A, M. LaiD can be used for table lookup or code conversion such as 8CD to seven-segment. The LaiD instruction "pushes" the stack (PC + 1 ~ SA ~ 58 ~ SC)
and replaces the least significant a bits of PC as follows: A
~ PC7:4, RAM(8) ~ PC3:0, leaving PC10, PCg and PCB
unchanged. The ROM data pointed to by the new address is
fetched and loaded into the a latches. Next, the stack is
"popped" (SC ~ S8 ~ SA ~ PC), restoring the
saved value of PC to continue sequential program execution. Since LaiD pushes 58 ~ SC, the previous contents
XAS INSTRUCTION
INIL INSTRUCTION
INIL (Input IL Latches to A) inputs 2 latches, IL3 and ILa (see
Figure 7) and CKO into A. The IL3 and ILa latches are set if
a low-going pulse ("1" to "0") has occurred or the IN3 and
1-221
III
-J ,----------------------------------------------------------------------------------------,
Ln
~
C")
Q.
o(.)
.......
COP444L
-J
ININ
~
~
.L
C")
Q.
o(.)
:::;
The following is a list of COP444L options. When specifying
a COP445L chip, Options 9, 10, 19, and 20 must all be set
to zero. The options are programmed at the same time as
the ROM pattern to provide the user with the hardware flexibility to interface to various I/O components using little or
no external circuitry.
Description of Selected
Instructions (Continued)
Option 1 = 0: Ground Pin-no options available
INo/ IN 3
Option 2: CKO Output
= 0: clock generator ouput to crystal/resonator
(0 not allowable value if option 3 = 3)
= 1: pin is RAM power supply (VR) input
= 2: general purpose input, load device to Vee
= 3: general purpose input, Hi-Z
Option 3: CKI Input
= 0: oscillator input divided by 32 (2 MHz max.)
= 1: oscillator input divided by 16 (1 MHz max.)
= 2: oscillator input divided by 8 (500 kHz max.)
= 3: single-pin RC controlled oscillator divided by 4
= 4: oscillator input divided by 4 (Schmitt)
Option 4: RESET Input
Ln
~
~
Q.
o(.)
:::;
INIL
~
~
~
Q.
o(.)
TL/DD/6926-21
FIGURE 7. INIL Hardware Implementation
of SC are lost. Also, when LaiD pops the stack, the previously pushed contents of S8 are left in SC. The net result is
that the contents of S8 are placed In 5C (58 -+ SC). Note
that LaiD takes two instruction cycle times to execute.
SKT INSTRUCTION
= 0: load device to Vee
The SKT (Skip On Timer) instruction tests the state of an
internal 10-bit time-base counter. This counter divides the
instruction cycle clock frequency by 1024 and provides a
latched indication of counter overflow. The SKT instruction
tests this latch, executing the next program Instruction if the
latch is not set. If the latch has been set since the previous
test, the next program instruction is skipped and the latch is
reset. The features associated with this instruction, therefore, allow the COP444L1445L to generate its own timebase for real-time processing rather than relying on an external input signal.
= 1: Hi-Z input
Option 5: L7 Driver
= 0: Standard output
= 1: Open-drain output
= 2: High current LED direct segment drive output
= 3: High current TRI-STATE push-pull output
= 4: Low-current LED direct segment drive output
= 5: Low-current TRI-STATE push-pull output
Option 6: La Driver
same as Option 5
For example, using a 2.097 MHz crystal as the time-base to
the clock generator, the instruction cycle clock frequency
will be 65 kHz (crystal frequency + 32) and the binary counter output pulse frequency will be 64 Hz. For time-of-day or
similar real-time processing, the SKT instruction can call a
routine which increments a "seconds" counter every 64
ticks.
Option 7: Ls Driver
same as Option 5
Option 8: 4 Driver
same as Option 5
Option 9: IN1 Input
INSTRUCTION SET NOTES
= 0: load device to Vee
a. The first word of a COP444L1445L program (ROM address 0) must be a CLRA (Clear A) instruction.
=
1: Hi-Z input
Option 10: IN2 Input
same as Option 9
b. Although skipped instructions are not executed, one Instruction cycle time is devoted to skipping each byte of
the skipped instruction. Thus all program paths except
JID and LaiD take the same number of cycle times
whether instructions are skipped or executed. JID and
LaiD instructions take 2 cycles if executed and 1 cycle if
skipped.
Option 11: Vee pin Operating Voltage
COP44XL
COP34XL
= 0: + 4.5V to + 6.3V
+ 4.5V to + 5.5V
= 1: +4.5V to +9.5V
+4.5V to +7.5V
c. The ROM is organized into 32 pages of 64 words each.
The Program Counter is an 11-bit binary counter, and will
count through page boundaries. If a JP, JSRP, JID or
LaiD instruction is located in the last word of a page, the
instruction operates as if it were in the next page. For
example: a JP located in the last work of a page will jump
to a location in the next page. Also, a LaiD or JID located
in the last word of page 3, 7, 11, 15, 19, 23 or 27 will
access data in the next group of four pages.
Option 12: Ls Driver
Option List
Option 16: SI Input
same as Option 5
Option 13: L2 Driver
same as Option 5
Option 14: L1 Driver
same as Option 5
Option 15: La Driver
same as Option 5
same as Option 9
The COP444L1445L mask-programmable options are assigned numbers which correspond with the COP444L pins.
1-222
o
o"tJ
Option List (Continued)
Option 17: SO Driver
~
~
~
Option 27: D1 Output
same as Option 21
= 0: standard output
= 1: open-drain output
r.......
o
Option 28: Do Output
same as Option 21
= 2: push-pull output
Option 18: SK Driver
same as Option 17
o"tJ
~
~
Option 29: L Input Levels
Option 19: INa Input
= 0: standard TIL input levels
("0" = 0.8V, "1" = 2.0V)
same as Option 9
= 1: higher voltage input levels
Option 20: IN3 Input
U1
C
o
o"tJ
~
~
~
("0" = 1.2V, "1" = 3.6V)
same as Option 9
Option 21: Go 1/0 Port
Option 30: IN Input Levels
C
same as Option 29
Option 31: G Input Levels
= 0: very-high current standard output
= 1: very-high current open-drain output
o
o"tJ
same as Option 29
= 2: high current standard output
Option 32: SI Input Levels
= 3: high current open-drain output
same as Option 29
Option 33: RESET Input
= 4: standard LSTIL output (fanout = 1)
= 5: open-drain LSTIL output (fanout = 1)
~
~
U1
r-
= 0: Schmitt trigger input levels
Option 22: G1 1/0 Port
= 1: standard TIL input levels
same as Option 21
= 2: higher voltage input levels
Option 23: G2 1/0 Port
Option 34: CKO Input Levels (CKO=input; Option 2=2, 3)
same as Option 21
Option 24: G3 1/0 Port
same as Option 29
Option 35: COP Bonding
same as Option 21
= 0: COP444L (28-pin device)
Option 25: D3 Output
= 1: COP445L (24-pin device)
same as Option 21
= 2: both 28- and 24-pin versions
Option 26: D2 Output
same as Option 21
Option 36: Internal Initialization Logic
= 0: normal operation
= 1: no internal initialization logic
COP444L Option Table
The following option information is to be seNt to National along with the EPROM.
OPTION DATA
OPTION DATA
OPTION 1 VALUE =
IS: GROUND PIN
OPTION 21 VALUE=
OPTION 2 VALUE=
IS: CKO PIN
OPTION 22 VALUE=
OPTION 3 VALUE=
IS: CKI PIN
OPTION 23 VALUE=
IS: GO 1/0 PORT
OPTION 4 VALUE=
IS: RESET INPUT
OPTION 24 VALUE=
IS: G3 1/0 PORT
OPTION 5 VALUE=
OPTION 6 VALUE=
OPTION 7 VALUE=
IS: L(7) DRIVER
IS: L(6) DRIVER
OPTION 25 VALUE=
OPTION 26 VALUE=
IS: D3 OUTPUT
IS: D2 OUTPUT
IS: L(5) DRIVER
OPTION 27 VALUE=
IS: D1 OUTPUT
OPTION 8 VALUE=
IS: L(4) DRIVER
OPTION 28 VALUE=
IS: DO OUTPUT
OPTION 9 VALUE=
IS: IN1 INPUT
OPTION 29 VALUE=
IS: L INPUT LEVELS
OPTION 10 VALUE=
IS: IN2 INPUT
OPTION 11 VALUE=
OPTION 12 VALUE=
IS: VCC PIN
IS: L(3) DRIVER
OPTION 30 VALUE=
OPTION 31 VALUE=
IS: IN INPUT LEVELS
IS: G INPUT LEVELS
OPTION 32 VALUE=
OPTION 13 VALUE=
IS: L(2) DRIVER
OPTION 33 VALUE=
IS: SI INPUT LEVELS
IS: RESET INPUT
IS: CKO INPUT LEVELS
OPTION 14 VALUE=
IS: L(1) DRIVER
OPTION 34 VALUE=
OPTION 15 VALUE=
IS: L(O) DRIVER
OPTION 35 VALUE=
OPTION 16 VALUE=
OPTION 17 VALUE=
IS: SIINPUT
OPTION 36 VALUE =
OPTION 18 VALUE=
IS: SO DRIVER
IS: SK DRIVER
OPTION 19 VALUE =
IS: INO INPUT
OPTION 20 VALUE=
IS: IN3 INPUT
1-223
IS: G1 1/0 PORT
IS: G2 1/0 PORT
IS: COP BONDING
IS: INTERNAL
INITIALIZATION
LOGIC
~
&l)
~
M
r-----------------------------------------------------------------------~
Typical Applications
D.
TEST MODE (NON-STANDARD OPERATION)
.......
The SO output has been configured to provide for standard
test procedures for the custom-programmed COP444L.
With SO forced to logic "1", two test modes are provided,
depending upon the value of SI:
a. RAM and Internal Logic Test Mode (SI = 1)
6. The 4 bidirectional G I/O ports (G3-GO) are available for
use as required by the user's application.
7. Normal reset operation is selected.
b. ROM Test Mode (SI = 0)
COP444L EVALUATION (See COP Note 4)
These special test modes should not be employed by the
user; they are intended for manufacturing test only.
The 444L-EVAL is a pre-programmed COP444L, containing
several routines which facilitate user familiarization and
evaluation of the COP444L operating characteristics. It may
be used as an up/down counter or timer, interfacing to any
combination of (1) an LED digit or lamps, (2) 4-digit LED
Display Controller, (3) a 4-digit VF Display Controller, and/or
(4) a 4-digit LCD Display Controller. Alternatively, it may be
used as a simple music synthesizer.
oo
~
~
~
M
D.
o
o
.......
~
&l)
~
~
D.
oo
.......
~
~
~
~
D.
o
o
5. SI is selected as the input to a binary counter input. With
SIO used as a binary counter, SO and SK can be used as
general purpose outputs.
APPLICATION # 1: COP444L GENERAL CONTROLLER
Figure 8 shows an interconnect diagram for a COP444L
used as a general controller. Operation of the system is as
follows:
1. The L7-LO outputs are configured as LED Direct Drive
outputs, allowing direct connection to the segments of
the display
2. The 03-00 outputs drive the digits of the multiplexed display directly and scan the columns of the 4 x 4 keyboard
matrix.
3. The IN3-INo inputs are used to input the 4 rows of the
keyboard matrix. Reading the IN lines in conjunction with
the current value of the 0 outputs allows detection, debouncing, and decoding of anyone of the 16 keyswitches.
4. CKI is configured as a single-pin oscillator input allowing
system timing to be controlled by a single-pin RC network. CKO is therefore available for use as a general-purpose input.
SAMPLE CIRCUITS
1. By making only the oscillator, power supply and "L7"
connections, (Figure 9) an approximate 1 Hz square wave
will be produced at output "01." This output may be observed with an oscilloscope, or connected to additional
TTL or CMOS circuitry.
2. By making the indicated connections to a small LED digit
(NSA1541A, NSA1166, or equiv.-Iarger digits will be
proportionately dimmer), the counter actions may be observed. Place the "up/down" switch in the "up" (open)
position and apply a TTL-compatible signal at the "counter-input." Placing the "up/down" switch in the "down"
(closed) position causes the count to decrement on each
high-to-Iow input transition.
3. All 4 digits of the counter may be displayed by connecting
a standard display controller (COP470 for VF, COP472
for LCD, MM5450 for LED) as shown in Figure 9.
VCC
LO
VCC
L7
CKI
4·DlGIT
LED DISPLAY
GNO
GNo
":"
RESET
VCC
CDP444L
DO
01
02
!
03
INPUT-
4 GENERAL
110
CKD
~O
G3
INO
INI
IN2
EVENT
COUNTER
INPUT
SI
414
KEYSWITCH
MATRIX
IN3
TLlDD/692B-22
FIGURE 8. COP444L Keyboard/Display Interface
1-224
o
o
Typical Applications (Continued)
a square wave of the corresponding frequency to be
outputted to the speaker. Depressing "LShift" or
"UShift" causes the next note to be shifted to the next
lower octave (one-half frequency) or the next upper
octave (double frequency), respectively.
Any combination of the single LED digit and display controllers may be used simultaneously, and will display the
same data.
4. The simple counter described above becomes a timer
when the 1 Hz output is connected to the "counter input."
Up or down counting may be used with input frequencies
up to 1 kHz. Improved timing accuracies may be obtained
by subsituting the 2.097 MHz crystal oscillator circuit of
Figure 4a for the RC network shown in Figure 9, or by
connecting a more stable external frequency to the
"counter input" in place of the 1 Hz signal.
b. Play Stored Tune
Depressing "Play" followed by "Ys", "114'" "%", or "1"
will cause one of 4 stored tunes to be played.
c. Record Tune
Any combination of notes and rests up to a total of 48
may be stored in RAM for later replay. To store a note,
press the appropriate note key, followed by the duration of the note We-note, 1I4-note, %-note, whole (1)note, followed by "Store"; a rest is stored by selecting
the duration and pressing "Store." When the tune is
complete, press "Play" followed by "Store"; the tune
will be played for immediate audition. Subsequent depression of "Play" and "Store" will replay the last
stored tune.
5. An "entertaining" use of the 444L-EVAL is as a simple
music synthesizer (or electronic organ). By attaching a
simple switch matrix (or keyboard), a speaker or piezo-ceramic transducer, and grounding "L7", the user can play
"music" (Figure 10). Three modes of operation are available: Playa note, play one of four stored tunes, or record
a tune for subsequent replay.
a. Play A Note
Twelve keys, representing the 12 notes in one octave,
are labeled "C" through "B"; depressing a key causes
Note: The accuracy of the tones produced is a function of the oscillator
accuracy and stability; the crystal oscillator is recommended.
Vee
_----------'""""f
r---------t
Vee
OSCILLATOR
CKI
CKO
DO
Dl
.-------f D2
_---4
1/8
G'
1/4
A
1/2
A'
STORE
PLAY
D3
IND
444L·EVAL
INl
C'
F'
IN2
L
SHIFT
D-
IN3
U
SHIFT
SI
GNO
L7
GO
Vee
SPKR
IiI!:."
TRANSDUCER
FIGURE 9. Counter/Timer
1-225
TLlDD/6928-23
"
.Iloo
.Iloo
.Iloo
r.......
o
o
"en
.Iloo
.Iloo
C
o
o
"
W
.Iloo
.Iloo
r.......
o
o
"en
W
.Iloo
r-
COP444L/COP445L/COP344L/COP345L
Vee
1
37pF
h
Vee
coUNTER
INPUT
L
200pF
1 ;b_
T . .........
.... T
T
r
1
3.3k
CKI
l7
DI
I----
.---
I
N
~
~
INI
ClK
EN
Vss
~
~
I
~~
~
~
I
L
_~~_..J
. ,.
'"
12
02
SO
01
SK
ClK
GNO
t
15P
5
Voo -
COP472
RESET
LO
3
1
CE
I
I
I
I
I
I
...
I
I
I
I
I
I
I
I
4·01GIT lED
DISPLAY
(2 EA. NSN584)
INZ
444L-EVAL
~~
...,
34
0
MM5450
---V;-'
~
I
I
1
4·DI6IT LCD
DISPLAY
(EPSOM LD370)
I
I
Vuo
1
01
-=-
r
Vee
Voo
1 Hz
UP
'\,.-
"~
BRITE
CKO
SI
}.. ...
L1
L2
LJ
L4
L5
~
Sd
LED DIGIT
(NSA1166 DR EOUlV.)
GNO
~
~
• DISPLAY VOLTAGE
L6
,,
., ;~ ,.~ , t~ ".~ ,
-t- Sb- Sc- Se"'; 5;"'; ~g
'I'~ 'II
Voo*
~
~
~
-
CLK
B
COP47D
DI
CE
Vss
VGG
GNO
I I~
Vee
S
....
4-DIGITVF
DISPLAY
(FUTABA 4-LT-51A)
4
t
~
FILAMENTS
f-o
0
VGG
TL/DD/692B-24
tlf LED Direct Drive option is selected with power supply operating voltage of 4.5V to 9.5V (higher voltage option), series resistors must be used to limit currenl
•• See "Initialization"
FIGURE 10. Music Synthesizer
o
o
~National
""CI
0l:Io
o
...A.
r
D Semiconductor
COP401L ROMless N-Channel Microcontroller
General Description
Features
The COP401 L ROMless Microcontroller is a member of the
COPSTM family of microcontrollers, fabricated using
N-channel, silicon gate MOS technology. The COP401 L
contains CPU, RAM, I/O and is identical to a COP41 OL device except the ROM has been removed and pins have
been added to output the ROM address and to input the
ROM data. In a system the COP401 L will perform exactly as
the COP410L. This important benefit facilitates development and debug of a COP program prior to masking the final
part.
The COP401 L is intended for emulation only, not intended
for volume production. Use COP402 or COP404L for volume production.
• Circuit equivalent of COP410L
•
•
•
•
•
•
•
•
•
iii
•
•
•
•
•
Low cost
Powerful instruction set
512 x 8 ROM, 32 x 4 RAM
Separate RAM power supply pin for RAM keep-alive
applications
Two-level subroutine stack
15 J.Ls instruction time
Single supply operation (4.5-9.5V)
Low current drain (8 mA max.)
Internal binary counter register with serial I/O
MICROWIRETM compatible serial I/O
General purpose outputs
LSTTLICMOS compatible in and out
Direct drive of LED digit and segment lines
Software/hardware compatible with other members of
COP400 family
Pin-for-pin compatible with COP402 and COP404L
Block Diagram
GND
AD/DATA
~22
(VR TD RAil)
IP.
IP,
IPz
IPI
IP,
IPI
IP,
IP,
P,
SKIP
.----------I....::.;.-::!IIICROWIRE 110
II
11 12 13 I. I.
L,
L&
L\
L,
L3
II
LZ
202t
L,
LO
TL/DD/6913-1
FIGURE 1
1-227
....o
..J
"11:1'
a..
o
o
Absolute Maximum Ratings
If Military!Aerospace specified devices are required,
contact the National Semiconductor Sales Office!
Distributors for availability and specifications.
Voltage at any Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
O.4Wat 70·C
120mA
Absolute maximum ratings indicate limits beyond which
damage to the device may occur. DC and AC electrical
specifications are not ensured when operating the device at
absolute maximum ratings.
Total Sink Current
O·Cto +70·C
- 65·C to + 150·C
300·C
DC Electrical Characteristics o·c ~ TA ~
Parameter
+ 70·C, 4.5V
Conditions
Operating Voltage (Vee>
(Note 2)
Power Supply Ripple
Peal to Peak
Operating Supply Current
All Inputs and Outputs Open
Input Voltage Levels
CKllnput Levels
Crystal Input
Logic High (VIH)
Logic Low (VIU
RESET Input Levels
Logic High
Logic Low
IPO-IP7 Input Levels
Logic High
Logic High
Logic Low
All Other Inputs
Logic High
Logic High
Logic Low
Input Capacitance
Output Voltage Levels
LSTTL Operation
Logic High (VOH)
Logic Low (VOU
IPO-IP7, P8, SKIP
Logic Low
Output Current Levels
Output Sink Current
SO and SK Outputs (Iou
LO-L7 and GO-G3 Outputs
Do-D3 Outputs
CKO
RAM Power Supply Input
120mA
Total Source Current
-0.5V to + 10V
Lead Temp. (Soldering, 10 sec.)
0.75W at 25·C
Power Dissipation
~ Vee ~ 9.5V unless otherwise noted
Min
Max
Units
9.5
V
0.5
V
8
mA
2.0
-0.3
0.4
V
0.7 Vee
-0.3
0.6
V
4.5
V
Schmitt Trigger Input
Vee = 9.5V
Vee = 5V ±5%
Vee = 9.5V
Vee = 5V ±5%
Vee = 5V ±10%
10H = - 25 1lA
10L = 0.36mA
(Note 1)
IOL = 1.6 mA
Vee
Vee
Vee
Vee
Vee
Vee
= 9.5V, VOL = O.4V
= 4.5V, VOL = 0.4V
= 9.5V, VOL = O.4V
= 4.5V, VOL = O.4V
= 9.5V, VOL = 1.0V
= 4.5V, VOL = 1.0V
2.4
2.0
-0.3
3.0
2.0
-0.3
V
V
V
0.8
V
V
0.8
V
7
pF
V
2.7
0.4
V
0.4
V
1.8
0.9
0.8
0.4
30
15
mA
mA
mA
mA
mA
mA
1.5
VR = 3.3V
1-228
V
mA
o
DC Electrical Characteristics O°C ~ T A ~ + 70°C. 4.5V ~ Vee ~ 9.5V unless otherwise noted (Continu,ed)
Parameter
Output Source Current
00- 0 3. GO-G3 Outputs (IOH)
SO and SK Outputs (IOH)
Lo-L7 Outputs
Input Load Source Current (Ill)
Conditions
Vee
Vee
Vee
Vee
Vee
Vee
Vee
=
=
=
=
=
=
=
9.5V. VOH = 2.0V
4·5V. VOH = 2.0V
9.5V. VOH = 4.75V
4.5V. VOH = 1.0V
9.5V. VOH = 2.0V
6.0V. VOH = 2.0V
5.0V. VL = OV
Min
Max
Units
-140
-30
-1.4
-1.2
-3.0
-0.3
-10
-800
-250
-35
-25
-140
p.A
p.A
rnA
mA
mA
mA
p.A
120
100
4
4
1.8
mA
mA
mA
mA
mA
120
60
60
25
1.5
mA
mA
mA
mA
rnA
Total Sink Current Allowed
All Outputs Combined
Port
o
LrL4. G Port
L3- LO
All Other Pins
Total Source Current Allowed
All 1/0 Combined
Lr L4
L3- LO
Each LPin
All Other Pins
AC Electrical Characteristics O°C ~ T A ~ + 70°C. 4.5V ~ Vee ~ 9.5V unless otherwise specified.
Parameter
Conditions
Instruction Cycle Time
Min
Max
Units
15
40
/-,-S
0.8
30
2.1
MHz
%
ns
n5
CKI
Input Frequency fl
Duty Cycle
Rise Time
Fall Time
(+32 Mode)
fl
=
~O
120
80
2.097 MHz
INPUTS:
SI.IP7-IPO
tSETUP
tHOLD
G3- GO. LrLo
tSETUP
tHOLD
OUTPUT PROPAGATION DELAY
Test Condition:
SO. SK Outputs
CL = pF. VOUT
RL = 20 kO
tpd1. tpdO
03- 0 0. G3-GO. L7- LO
tpd1. tpdO
IP7-IPO. P8. SKIP
RL
=
kO
RL
=
5 kO
=
1: Pull-up resistors required.
Note 2: Vee voltage change must be less than O.5V in a 1 ms period to maintain proper operation.
1·229
/-,-s
/-,-5
8.0
1.3
/-,-5
/-,-5
1.5V
tpd1. tpdO
Note
2.0
1.0
4.0
/-,-5
5.6
,...,5
7.2
,...,5
o
-a
~
....r-
c
,....
..J
o
'l1l:I'
Connection Diagram
Q.
oo
CKO
40
DO
CKI
39
01
IP4
38
02
RESET
37
03
IPJ
36
IPS
IP2
35
PB
IPI
34
NC
AD/DATA
IPO
SKIP
IP7
G3
IP6
10
L7
11
L6
12
Gl
L5
13
GO
NC
COP401L
G2
L4
14
NC
15
NC
NC
16
SK
VCC
17
SO
LJ
18
SI
L2
19
GND
L1
20
LO
TL/DD/6913-2
Order Number COP401LIN
NS Package Number N40A
FIGURE 2
Pin Descriptions
Pin
G3- GO
03- 0 0
SI
SO
SK
AD/DATA
Description
Pin
Description
B bidirectional I/O ports with LED
segment drive
4 bidirectional I/O ports
4 general purpose outputs
Serial input (or counter input)
Serial output (or general purpose output)
Logic·controlled clock (or general
purpose output)
Address Out/data in flag
CKI
CKO
RESET
System oscillator input
RAM power supply input
System reset input
Power supply
Ground
B bidirectional ROM address and data ports
Most significant ROM address bit output
Instruction skip output
Vee
GND
IP7-IPO
PB
SKIP
Timing Diagram
CKI
AO/Dm, SK
(AS A CLOCK)
GO-G3. LO-L7. SI
IPO·IP7 INPUTS
GO·G3. 00·03,
LO·L7. SO. 51
OUTPUTS
IPO·IP7. PB.
SKIP OUTPUTS
~'.'~"",,,,,,.p..___ -------TLIDD/6913-3
FIGURE 3. Input/Output
1·230
o
o-a
Functional Description
0l:Io
A block diagram of the COP401 L is given in Figure 1. Data
paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. Positive logic is
used. When a bit is set, it is a logic "1" greater than 2 volts).
When a bit is reset, it is a logic "0" (less than 0.8 volts).
INTERNAL LOGIC
The 4-bit A register (accumulator) is the source and destination register for most 1/0, arithmetic, logic and data memory
access operations. It can also be used to load the Bd portion of the B register, to load 4 bits of the 8-bit a latch data,
to input 4 bits of the a-bit L 1/0 port data and to perform
data exchanges with the SIO register.
PROGRAM MEMORY
Program Memory consists of a 512-byte external memory.
As can be seen by an examination of the COP401 L instruction set, these words may be program instructions, program
data or ROM addressing data. Because of the special characteristics associated with the JP, JSRP, JID and LaiD instructions, ROM must often be thought of as being organized into 8 pages of 64 words each.
A 4-bit adder performs the arithmetic and logic functions of
the COP401 L, storing its results in A. It also outputs a carry
bit to the 1-bit C register, most often employed to indicate
arithmetic overflow. The C register, in conjunction with the
XAS instruction and the EN register, also serves to control
the SK output. C can be outputted directly to SK or can
enable SK to be a sync clock each instruction cycle time.
(See XAS instruction and EN register description, below.)
The G register contents are outputs to 4 general-purpose
bidirectional 1/0 ports.
ROM addressing is accomplished by a 9-bit PC register. Its
binary value selects one of the 512 8-bit words contained in
ROM. A new address is loaded into the PC register during
each instruction cycle. Unless the instruction is a transer of
control instruction, the PC register is loaded with the next
sequential 9-bit binary count value. Two levels of subroutine
nesting are implemented by the 9-bit subroutine save registers, SA and SB, providing a last-in, first-out (LIFO) hardware subroutine stack.
The a register is an internal, latched, 8-bit register, used to
hold data loaded from M and A, as well as 8-bit data from
ROM. Its contents are output to the L 1/0 ports when the L
drivers are enabled under program control. (See LEI instruction.)
The 8 L drivers, when enabled, output the contents of
latched a data to the L 1/0 ports. Also, the contents of L
may be read directly into A and M. L 1/0 ports can be directly connected to the segments of a multiplexed LED display
(using the LED Direct Drive output configuration option) with
a data being outputted to the Sa-Sg and decimal point
segments of the display.
ROM instruction words are fetched, decoded and executed
by the instruction Decode, Control and Skip Logic circuitry.
DATA MEMORY
Data memory consists of a 128-bit RAM, organized as 4
data registers of 8 4-bit digits. RAM addressing is implemented by a 6-bit B register whose upper 2 bits (Br) select 1
of 4 data registers and lower 3 bits of the 4-bit Bd select 1 of
8 4-bit digits in the selected data register. While the 4-bit
contents of the selected RAM digit (M) is usually loaded into
or from, or exchanged with, the A register (accumulator), it
may also be loaded into the a latches or loaded from the L
ports. RAM addressing may also be performed directly by
the XAD 3, 15 instruction. The Bd register also serves as a
source register for 4-bit data sent directly to the 0 outputs.
The most Significant bit of Bd is not used to select a RAM
digit. Hence each physical digit of RAM may be selected by
two different values of Bd as shown in Figure 4 below. The
skip condition for XIS and XDS instructions will be true if Bd
changes between 0 and 15, but NOT between 7 and a (see
Table 3).
Bd VALUE
The 510 register functions as a 4-bit serial-in/serial-out shift
register or as a binary counter depending on the contents of
the EN register. (See EN register description, below.) Its
contents can be exchanged with A, allowing it to input or
output a continuous serial data stream. 510 may also be
used to provide additional parallel I/O by connecting SO to
external serial-in/parallel-out shift register.
The XAS instruction copies C into the SKL Latch. In the
counter mode, SK is the output of SKL in the shift register
mode, SK outputs SKL ANDed with internal instruction cycle
clock.
The EN register is an internal 4-bit register loaded under
program control by the LEI instruction. The state of each bit
of this register selects or deselects the particular feature
associated with each bit of the EN register (EN3-ENo).
RAM DIGIT
1. The least significant bit of the enable register, ENo, selects the SIO register as either a 4-bit shift register or a
4-bit binary counter. With ENo set, SIO is an asynchronous binary counter, decrementing its value by one upon
each low-going pulse ("1" to "0") occurring on the SI
input. Each pulse must be at least two instruction cycles
wide. SK outputs the value of SKL. The SO output is
equal to the value of EN3. With ENo reset, 510 is a serial
shift register shifting left each instruction cycle time. The
data present at SI goes into the least significant bit of
SIO. SO can be enabled to output the most significant bit
of SIO each cycle time. (See 4 below.) The SK output
becomes a logic-controlled clock.
2. EN1 is not used. It has no effect on COP401 L operation.
TL/DD/6913-4
FIGURE 4. RAM Digit Address to
Physical RAM Digit Mapping
1-231
....
o
r-
....o
..I
0lI:l'
Functional Description
(Continued)
D.
oo
TABLE I. Enable Register Modes-Bits EN3 and ENo
EN3
ENo
SIO
0
0
Shift Register
1
0
Shift Register
SI
SO
Input to Shift Register
0
Input to Shift Register
Serial Out
0
1
Binary Counter
Input to Binary Counter
0
1
1
Binary Counter
Input to Binary Counter
1
3. With EN2 set, the L drivers are enabled to output the data
in Q to the L \/0 ports. Resetting EN2 disables the L
drivers, placing the L 110 ports in a high-impedance input
state.
... ~
-~
:~ J~
Clock
=0
=
Clock
=0
=
=
=
=
1
0
1
0
1. random addressing
3. TIL-compatible inputs
4. access time
=
5 p's max.
Typically these requirements are met using bipolar or MOS
PROMs.
During operation, the address of the next instruction is sent
out on P8 and IP7' through IPO during the time that
ADIDATA is high (logic "1" = address mode). Address
data on thelP lines is stored into an external latch on the
high-to-Iow transition of the ADIDATA line; P8 is a dedicated address output, and does not need to be latched. When
ADIDATA is low (logic "0" = data mode), the output of the
memory is gated onto IP7 through IPO, forming the input
bus. Note that the ADIDATA output has a period of one
instruction time, a duty cycle of approximately 50%, and
specifies whether the IP lines are used for address output or
instruction input
I
vee
eOP401L
OSCILLATOR
p
::~
P
L
~
=
2. TIL-compatible TRI-STATE® outputs
Rrn'f
s
u
1, SK
0, SK
1, SK
0, SK
1, SK
0, SK
1, SK
0, SK
EXTERNAL ~EMORY INTERFACE
The Reset Logic will initialize (clear) the device upon powerup if the power supply rise time is less than 1 ms and greater than 1 p.s. If the power supply rise time is greater than 1
ms, the user must provide an' external RC network and diode to the RES'ET pin as shown below (Figure 5). The
RESET pin is configured as a Schmitt trigger input. If not
used it should be connected to Vce. Initialization will occur
whenever a logic "0" is applied to the RESETinput, provided it stays low f?r at least three instr~ction cycle times.
E
R
=
=
=
=
=
=
=
=
The COP401 L is designed for use with an external Program
Memory. This memory may be implemented using any devices having the following characteristics:
INITIALIZATION
w
If SKL
If SKL
If SKL
If SKL
If SKL
If SKL
If SKL
If SKL
Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, D, EN, and G registers are cleared.
The SK output is enabled as a SYNC output, providing a
pulse each instruction cycle time. Data Memory (RAM) is
not cleared upon initialization. The first instruction at address 0 must be a CLRA.
4. ENa, in conjunction with ENo, affects the SO output. With
ENo set (binary counter option selected) SO will output
the value loaded into ENs. With ENo resef (serial shift
register option selected), setting ENs enables SO as the
output of the SIO shift register, outputting serial shifted
data each instruction time. Resetting ENs with the serial
shift register option selected disables SO as the shift register output; data continues to be shifted through SIO and
can be exchanged with A via an XAS instruction but SO
remair,,\s reset to "0". Table I provides a summary of the
modes associated with ENs and ENo.
, p +
0
SK
-
GND
CKI is an external clock input signal. The external frequency
is divided by 32 to give the instruction cycle time. The divide-by-32 configuration was chosen to make the COP 401 L
compatible with the COP404L and the COPSTM Development System. However, the -:- 32 configuration is not available on the COP41 OLlCOP411 L. It is therefore possible to
exactly emulate the system speed (cycle time), but not possible to drive the 401 L with the system clock during emulation.
I
TL/DD/6913-5
RC :!: Power Supply Rise Time
FIGURE 5. Ilower-Up Clear Circuit
1-232
Functional Description
hancement-mode device to Vee. This configuration has
been provided to allow for fast rise and fall times when
driving capacitive loads. (Used on SO and SK outputs.)
d. LED Direct Drive-an enhancement-mode device to
ground and to Vee, meeting the typical current sourcing
requirements of the segments of an LED display. The
sourcing device is clamped to limit current flow. These
devices may be turned off under program control (See
Functional Description, EN Register), plaCing the outputs
in a high-impedance state to provide required LED segment blanking for a multiplexed display. (Used on L outputs.)
COP401 L inputs have an on-chip depletion load device to
Vee·
The above input and output configurations share common
enhancement-mode and depletion-mode devices. Specifically, all configurations use one or more of five devices
(numbered 1-5, respectively). Minimum and maximum current (lOUT and VOUT) curves are given in Figure 7 for each
of these devices to allow the designer to effectively use
these I/O configurations in designing a system.
An important point to remember is that even when the L
drivers are disabled, the depletion load device will source a
small amount of current (see Figure 7, Device 2); however,
when the L-Hnes are used as inputs, the disabled depletion
device can not be relied on to source sufficient current to
pull an input to a logic "1".
(Continued)
CKO (RAM POWER)
CKO is configured as a RAM power supply pin (VR), allowing its connection to a standby/backup power supply to
maintain the integrity of RAM data with minimum power
drain when the main supply Is inoperative or shut down to
conserve power. This pin must be connected to Vee if the
power backup feature is not used. To insure that RAM integrity is maintained, the following conditions must be met:
1. RESET must go low before Vee goes below spec during
power-off; Vee must be within spec before RESET goes
high on power-up.
2. During normal operation, VR must be within the operating
range of the chip with (Vee-1) =:;; VR =:;; Vee.
3. VR must be ~ 3.3V with Vee off.
INPUTIOUTPUT CONFIGURATIONS
COP401 L outputs have the following configurations, illustrated in Figure 6:
a. Standard-an enhancement mode device to ground in
conjunction with a depletion-mode device to Vee, compatible with LSTTL and CMOS input requirements. (Used
on 0 and G outputs.)
b. Open-Draln-an enhancement-mode device to ground
only, allowing external pull-up as required by the user's
application. (Used on IP, P and SKIP outputs.)
c. Push-Pull-An enhancement-mode device to ground in
conjunction with a depletion-mode device paralleled en-
TL/DD/6913-7
TLIDD/6913-6
a. Standard Output
TL/DD/6913-8
c_ Push-Pull Output
b. Open-Drain Output
Vee
r-H~
#5
INPUT~~
TL/DD/6913-10
TLIDD/6913-9
(.6. is Depletion Device)
d. L Output (LED)
e. Input with Load
FIGURE 6. Output Configurations
1-233
o
o
"'a
~
o
.....
r-
..J
......
o
"11:1'
Q.
Typical Performance Characteristics
o(..)
Input Current for Lo through
L7 when Output Programmed
Off by Software
Current for Inputs with
Load Device
-100
-10
j
-60
co
-50
...
:0
co
-20
-10
1.0 2.0 3.0 4.0 5.0 6.0 1.0 8.0
,
"' "'
~
IMA~}
""-
""'~,
Vcc' 4.5V
~
MIN'"'VCC' U
~1Vclc'~5
~
~
-600
"' IMAX il Vcc' 9.5 V
:"'\1
-500
IMAX'
-400 ,-Vcc' 4.5~-+-'tEI'\:-+-+--+--H
-300 ....::!I ~ IMIN ilbt--'k-t-t--H
~ Vcc' .5VI ~
-200
_I.. _"
IMIN • ....;:!!.:,'"4-~H
I-~ 1'~19.5,~~
-100
.....
0--_"'1-.: I"r--I
1.0
o
2.0
I
V 110
VIN (VOLTS)
Source Current for SO and
SK In Push-Pull Configuration
1.5
-100 I-t-"",,",rl--+--+--I--+--+--H
~
S
o
o
9.5
-100 t-Pri-,-+--+--+--+--+--I--H
~I MAX IiIVcc' 9.0 V
-40
-30
-1000 ..--r--r--r--r--r--r-----rI
-gOO rl'\.lIri--+--+--+--+--+-_OE+-V_ICt-El_"_2H
DEVICE d:2
-90
-10
Source Current for Standard
Output Configuration
-40
2
3
4
5
&
1
I ........
I
9.5
VO H (VOLTS)
L Output Source Current
IMAX@
VCC=9.5V
I
IMIN@
VCC=9.5V
1.0
-3D
ic
C
E
~
-401--+--1--+--+--1----1
r-I---,III-II-I+
..
-20 Io'-.IJ..-lI..=....-_++-t-t-t-+--I
.s:z:
co
-30 1--+--1--+_"71''---1----1
-20
t--t-_+_7'-t--+--i:oo--l
0.5
-10
•••••
::::3
o 1 2 3 4 5 6 7 8 9 10
VOH(VOLTS)
LED Output Direct Segment
Drive
-50 VOH' 2.0 V
4
5
6
1
8
9
IMIN
10
10
VUH (VULTS)
OEVICE c#2
AND #3
......
Vcc (VOLTS)
Outut Sink Current for SO
andSK
4
Output Sink Current for
through L7 and GO-G3
La
DEVICE d
f2 AND'.
-40r--+--+-~--+--+--;
c
-30
.!
:z:
co
I~/
-20
....."
~
-
.'
-10
..........
0
IMIN
4
10
Vcc (VOLTS)
VOL(VOLTS)
VOL(VOLTS)
Output Sink Current IPO-IP7,
PS, SKIP, AD/DATA
Output Sink Current Do-D3
120 r-rr--r-.....----.,-.,--r-=_...
2.0 1 " T " 1 r - . , - - - r - - - - - - ,
80~~+_~+_~_t___t__;-_+_~
i-::.
80
c
t-HI~'_+__+_+_+-t__i_+__i
;: 1.0 Hf-+--+-----....;..;...---~
9
§
40~~+_+_+_+_+_+_;-_+_~
2 3 4
5 8
0.5
8 9 10
1.0
VOUT (VOLTS)
VOL(VOLTS)
TL/DD/69134-11
FIGURE 7, I/O Characteristics
1-234
o
o
COP401 L Instruction Set
."
Table III provides the mnemonic, operand, machine code,
data flow, skip conditions, and description associated with
each instruction in the COP401 L instruction set.
Table II is a symbol table providing internal architecture, instruction operand and operational symbols used in the instruction set table.
TABLE II. COP401 L Instruction Set Table Symbols
Symbol
Definition
Symbol
Definition
INTERNAL ARCHITECTURE SYMBOLS
INSTRUCTION OPERAND SYMBOLS
A
d
B
Br
Bd
C
o
EN
G
L
M
PC
Q
SA
SB
SIO
SK
4-bit Accumulator
6-bit RAM Address Register
Upper 2 bits of B (register address)
Lower 4 bits of B (digit address)
1-bit Carry Register
4-bit Data Output Port
4-bit Enable Register
4-bit Register to latch data for G 1/0 Port
8-bit TRI-STATE 1/0 Port
4-bit contents of RAM Memory pointed to by B
Register
9-bit ROM Address Register (program counter)
8-bit Register to latch data for L 1/0 Port
9-bit Subroutine Save Register A
9-bit Subroutine Save Register B
4-bit Shift Register and Counter
Logic-Controlled Clock Output
4-bit Operand Field, 0-15 binary (RAM
Digit Select)
2-bit Operand Field, 0-3 binary (RAM
Register Select)
9-bit Operand Field, 0-511 binary (ROM
Address)
4-bit Operand Field, 0-15 binary
(Immediate Data)
Contents of RAM location addressed by s
Contents of ROM location addressed by t
a
y
RAM(s)
ROM(t)
OPERATIONAL SYMBOLS
Plus
Minus
Replaces
Is exchanged with
Is equal to
The one's complement of A
Exclusive-OR
Range of values
+
-+
~
=
A
Ell
:
TABLE III. COP401L Instruction Set
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
ARITHMETIC INSTRUCTIONS
ASC
30
10011100001
ADD
31
1001110001
5-
10101
CLRA
00
COMP
A + C + RAM (B) -+ A
Carry -+ C
Carry
Add with Carry, Skip on
Carry
A + RAM (B) -+ A
None
Add RAM toA
A+y-+A
Carry
Add immediate, Skip on
Carry (y =1= 0)
10000100001
O-+A
None
Clear A
40
10100100001
A-+A
None
One's complement of A to A
NOP
44
10100101001
None
None
No Operation
RC
32
10011100101
"0" -+ C
None
ResetC
SC
22
10010100101
"1" -+ C
None
SetC
XOR
.02
10000100101
A Ell RAM (B) -+ A
None
Exclusive-OR RAM with A
AISC
Y
I
I 't I
1-235
~
o
-.
r-
...I
.....
(:)
"1:1'
a..
COP410L Instruction Set (Continued)
o(.)
TABLE III. COP401L Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
DataFlow
Skip Conditions
Description
TRANSFER OF CONTROL INSTRUCTIONS
JID
Jump Indirect (Note 2)
101101000laei
1 a7:0
1
a -+ PC
None
Jump
111 Be:o 1
(pages 2,3 only)
or
1111 a5:0 1
(all other pages)
a -+ PC6:0
None
Jump within Page
(Note 3)
110 I
PC
None
Jump to Subroutine Page
(Note 4)
PC + 1 -+ SA -+ SB
a -+ PC
None
Jump to Subroutine
6-
a
--
JP
a
---
a
None
11111111111
JMP
JSRP
ROM (PCe, A,M) -+
PC7:0
FF
--
a5:0
1
a -+ PC5:0
+ 1 -+
SA -+ SB
010 -+ PCS:6
a -+ PC5:0
6-
--
1011011001 as 1
I a7:0 1
RET
48
10100110001
SB -+ SA -+ PC
None
Return from Subroutine
RETSK
49
10100110011
SB -+ SA -+ PC
Always Skip on Return
Return from Subroutine
then Skip
JSR
a
MEMORY REFERENCE INSTRUCTIONS
CAMO
LD
r
LOID
33
3C
10011100111
10011111001
A -+ 07:4
RAM (B) -+ 03:0
None
Copy A, RAM to 0
-5
100 1r 10101 1
RAM (B) -+ A
Br E9 r -+ Br
None
Load RAM into A,
Exclusive-OR Br with r
BF
11011 11111 1
ROM(PCs, A, M) -+ 0
SA -+ SB
None
Load 0 Indirect
(Note 2)
RMB
0
1
2
3
4C
45
42
43
10100111001
10100101011
10100100101
10100100111
o -+
o -+
o -+
o -+
RAM(B)o
RAM(B)1
RAM(B)2
RAM(B)3'
None
Reset RAM Bit
5MB
0
1
2
3
40
47
46
4B
10100111011
10100101111
10100101101
10100110111
1
1
1
1
-+
-+
-+
-+
RAM(B)o
RAM(Bh
RAM(B)2
RAM(B)a
None
Set RAM Bit
STII
Y
7-
10111 1
y -+ RAM(B)
Bd + 1 -+ Bd
None
Store Memory Immediate
and Increment Bd
X
r
-6
I00 1r 10110 1
RAM (B) ~ A
Br E9 r -+ Br
None
Exchange RAM with A,
Exclusive-OR Br with r
XAD
3,15
23
BF
10010100111
11011111111
RAM(3, 15)
None
Exchange A with RAM
(3,15)
XDS
r
-7
100 Ir I0111 1
RAM(B) ~ A
Bd -1 -+ Bd
Br E9 r -+ Br
Bd decrements past 0
Exchange RAM with A
and Decrement Bd,
Exclusive-OR Br with r
XIS
r
-4
100lrl 01OO I
RAM (B) ~ A
Bd + 1 -+ Bd
Br E9 r -+ Br
Bd increments past 15
Exchange RAM with A
and Increment Bd,
Exclusive-OR Br with r
Y..
1
~
1-236
A
0
0
COP410L Instruction Set (Continued)
"tJ
~
0
.....
TABLE III. COP401L Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
r-
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
REGISTER REFERENCE INSTRUCTIONS
CAB
50
10101100001
A -+ Bd
None
Copy A to Bd
CBA
4E
10100111101
Bd -+ A
None
Copy Bd toA
LBI
r, d
-
100 I r I (d - 1) I
(d = 0,9:15)
r, d -+ B
Skip until not a LBI
Load B Immediate with
r, d (Note 5)
LEI
Y
33
6-
1001110011 I
10110 1 y I
y -+ EN
None
Load EN Immediate
(Note 6)
SKC
20
10010100001
C
=
"1"
Skip if C is True
SKE
21
1001010001
I
A
=
RAM(B)
Skip if A Equals RAM
SKGZ
33
21
1001110011
1001010001
I
G3:0
=
Skip if G is Zero
(all 4 bits)
0
1
2
3
33
01
11
03
13
1001110011
1000010001
1000110001
1000010011
1000110011
0
1
2
3
01
11
03
13
1000010001 I
1000110001 I
1000010011 I
10001100111
TEST INSTRUCTIONS
SKGBZ
SKMBZ
0
I
1st byte
I
I
I
} 2nd byt.
I
I
Skip if G Bit is Zero
Go
Gl
G2
G3
=
=
=
=
0
0
0
0
RAM(B)o
RAM(B)l
RAM(B)2
RAM(Bb
=
=
=
=
0
0
0
0
Skip if RAM Bit is Zero
INPUT/OUTPUT INSTRUCTIONS
ING
33
2A
10011100111
10010110101
G-+A
None
Input G Ports to A
INL
33
2E
10011100111
10010111101
L7:4 -+ RAM (B)
L3:0 -+ A
None
Input L Ports to RAM, A
OBO
33
3E
10011100111
10011111101
Bd -+ 0
None
Output Bd to 0 Outputs
OMG
33
3A
10011100111
10011110101
RAM (B) -+ G
None
Output RAM to G Ports
XAS
4F
10100111111
A
None
Exchange A with SIO
(Note 2)
~
SIO,C -+ SKL
Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to N where
o signifies the least significant bit (low-order, right-most bit). For example, A3 indicates the most significant (left-most) bit of the 4-bit A register.
Note 2: For additional information on the operation of the XAS, JID, and LQID instructions, see below.
Note 3: The JP instruction allows a Jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction,
otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Note 4: A JSRP transfers program control to subroutine page 2 (010 is loaded into the upper 3 bits of Pl. A JSRP may not be used when in pages 2 or 3. JSRP may
not jump to the last word in page 2.
Note 5: The machine code for the lower 4 bits of the LBI instruction equals the binary value of the "d" data minus 1, e.g., to load the lower four bits of B (Bd) with
the value 9 (10012), the lower 4 bits of the LBI instruction equal 8 (10002)' To load 0, the lower 4 bits of the LBI instruction should equal 15 (11112)'
Note 6: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a "1" or "0" in each bit of EN corresponds
with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
1-237
..oJ
-o
~
D-
O
o
Description of Selected Instructions
The following information is provided to assist the user in
understanding the operation of several unique instructions
and to provide notes useful to programmers in writing
COP401 L programs.
INSTRUCTION SET NOTES
a. The first word of a COP401 L program (ROM address 0)
must be a CLRA (Clear A) instruction.
b. Although skipped instructions are not executed, one instruction cycle time is devoted to skipping each byte of
the skipped instruction. Thus all program paths except
JID and LQID take the same number of cycle times
whether instructions are skipped or executed. JID and
LQID instructions take 2 cycles if executed and 1 cycle if
skipped.
c. The ROM is organized into a pages of 64 words each.
The Program Counter is a 9-bit binary counter, and will
count through page boundaries. If a JP, JSRP, JID or
LQID instruction is located in the last word of a page, the
instruction operates as if it were in the next page. For
example: a JP located in the last word of a page will jump
to a location in the next page. Also, a LQID or JID located
in the last word of page 3 or 7 will access data in the next
group of 4 pages.
XAS INSTRUCTION
XAS (Exchange A with 510) exchanges the 4-bit contents of
the accumulator with the 4-bit contents of the 510 register.
The contents of 510 will contain serial-in/serial-out shift register or binary counter data, depending on the value of the
EN register. An XAS instruction will also affect the SK output. (See Functional Description, EN Register, above.) If
510 is selected as a shift register, an XAS instruction must
be performed once every 4 instruction cycles to effect a
continous data stream.
JID INSTRUCTION
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location pOinted
to indirectly by A and M. It loads the lower a bits of the ROM
address register PC with the contents of ROM addressed by
the 9-bit word, PCa, A, M. PCa is not affected by this instruction.
Note that JID requires 2 instruction cycles to execute.
Typical Applications
PROM·BASED SYSTEM
The COP401 L may be used to emulate the COP410L. Figure 8 shows the interconnect to implement a COP401 L
hardware emulation. This connection uses one MM5204
EPROM as external memory. Other memory can be used
such as bipolar PROM or RAM.
Pins IP7-IPO are bidirectional inputs and outputs. When the
AD/DATA clocking output turns on, the EPROM drivers are
disabled and IP7-IPO output addresses. The a·bit latch
(MM74C373) latches the address to drive the memory.
LQID INSTRUCTION
LQID (Load Q Indirect) loads the a-bit Q register with the
contents of ROM pointed to by the 9-bit word PCa, A, M.
LQID can be used for table lookup or code conversion such
as 8CD to seven-segment. The LQID instruction "pushes"
the stack (PC + 1 ~ SA ~ 58) and replaces the least
significant 8 bits of PC as follows: A ~ PC7:4, RAM(8)
~ PC3:0, leaving PCa unchanged. The ROM data pOinted
to by the new address is fetched and loaded into the Q
latches. Next, the stack is "popped" (58 ~ SA ~ PC),
restoring the saved value of PC to continue sequential program execution. Since LQID pushes SA ~ 58, the previous contents of 58 are lost. Also, when LQID pops the
stack, the previously pushed contents of SA are left in 58.
The net result is that the contents of SA are placed in 58
(SA ~ 58). Note that LQID takes two instruction cycle
times to execute.
When AD/DATA turns off, the EPROM is enabled and the
IP7-IPO pins will input the memory data. P8 outputs the
most significant address bit to the memory. (SKIP output
may be used for program debug if needed.)
24 of the COP401 L pins may be configured exactly the
same as a COP41 OL.
1·238
o
Typical Applications
o"tJ
(Continued)
,I:Iio
C)
24
~
~19
~
23
1
2
3
4
5
8
7
8
19 16 15 12 9
20
+5V
~1tI
5
6
r;----
Q8 07 Q6 05 Q4 Q3 Q2 01
VCC
GNo
MM74lS373
[E
OUTPUT DIS
08 01 06 05 04 03 02 01
18 11 14 13 8 1 4 13
.-.
r-
Vee
Vpp
Vss
AID
A9
A8
A7
A8
A5
A4
A3
A2
Al
AD
81
MM2718
204818
lit~
B~
n
85
86
17
18
84
15
81
82
13
14
11
80
9
10
RL' 5.1K
",'"",
"'...." .......
"'."'...."'y - - .
"'."'."'....
A .. "'....
."'. "...."....
+5V
"'...."...."'y
"'.. "...."y
"."....,,~
"'........"'."'
....
"'y
I
1 3532
2z
9
IP1
P8
SKIP
36
10
IP8 IP5
1
2
4
11
3
5
8
1
6
IP4 IP3 IP2 IPI
33
AD/DATA
IPO
34
NC
40
39
38
31
31
CoP401L
~
,..-!!
~
13
COP41oL
PINOUT
I
~-.
14
15
16
11
18
19
20
21
23
24
25
26
21
28
129
fo-· fo-· ~- 1-----1--.1-- 1-- ~-~
GNo CKo CKI RESET L1
1
2
3
4
5
L6
L5
L4
8
VCC L3
9 10
L2
11
L1
12
LO
13
SI
14
SO
15
SK
16
GO
11
Gl
18
G2
19
G3
20
03
21
02
22
01
23
DO
24
TL/DD/6913-12
FIGURE 8.COP401L Used to Emulate a COP410L
1·239
III
....
~ r---------------------------------------------------------------------------------~
o
~
D.
oo
Option Table
COP401L MASK OPTIONS
The following COP410L options have been implemented in
this basic version of the COP401 L.
Option Value
Comment
Option 1 = 0
Option 2 = 1
Option 3 = N/A
Ground-no option
CKO is RAM power supply input
CKI is external clock divide-by32 (not available on COP41 OL)
Reset has load to Vee
Option 4 = 0
Option 5 = 2
Option 6 = 2
Option 7 = 2
Option 8 = 2
Option 9 = 1
Option 10 = 2
Option 11 = 2
Option 12 = 2
Option 13 = 2
Option Value
Option 14
Option 15
Option 16
Option 17
Option 18
Option 19
Option 20
Option 21
Option 22
Option 23
Option 24
Option 25
Option 26
Option 27
Option 28
L outputs are LED direct-drive
Vee pin 4.5V to 9.5V operation
L outputs are LED direct-drive
1-240
= 0
= 2
= 2
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= Nt A
Comment
51 has load to Vee
SO is push-pull output
5K is push-pull output
G outputs are standard
D outputs are standard
very high current
L
G Have standard TIL input levels
51
40-pin package
~National
D Semiconductor
COP401L-X13/COP401L-R13 ROMless N-Channel
Microcontroller
General Description
Features
The COP401 L-X13/COP401 L-R13 ROM less Microcontrollers are members of the COPSTM family vf microcontrollers,
fabricated using N-channel, silicon gate MOS technology.
The COP401 L-X13/COP401 L-R13 contain CPU, RAM, 110
and are identical to a COP413L device except the ROM has
been removed and pins have been added to output the
ROM address and to input the ROM data. In a system the
COP401 L-X13/COP401 L-R 13 will perform exactly as the
COP413L. This important benefit facilitates development
and debug of a COP program prior to masking the final part.
• Circuit equivalent of COP413L
There are two clock oscillator configurations available. The
crystal oscillator configuration is called COP401 L-X13 and
the RC oscillator configuration is called COP401 L-R13.
•
•
•
•
•
•
•
•
•
•
•
Low cost
Powerful instruction set
512 x 8 ROM, 32 x 4 RAM
Two-level subroutine stack
16 J.Ls instruction time
Single supply operation (4.5-5.5V)
Low current drain (8 mA max)
Internal binary counter register with serial 110
MICROWIRETM compatible serial I/O
General purpose outputs
Software/hardware compatible with other members of
COP400 family
• Pin-for-pin compatible with COP402 and COP404L
• High noise immunity inputs (VIL = 1.2V, VIH = 3.6V)
Block Diagram
CKO"
IIIITIIUCTlDII CLOCK (IYlICI
IIOP
31
Nt
31
Nt
411
Nt
III
r;:;::::::;:=::;::::;::;1i=_:}.1CIIOWI1IE 110
Z3
.1
13
.2
.1
II
11 12 13 14 1. 1.
n
Z1
TL/DD/8528-1
"COP401 L-X13 only
FIGURE 1
1-241
C")
"t-
a:
..!J
"t-
o
~
a..
oo
.....
C")
"t-
><
COP401L-X13/COP401L-R13 Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage at Any Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
-0.3 to +7V
- 65·C to + 150·C
Lead Temp. (Soldering, 10 seconds)
o
~
a..
DC Electrical Characteristics O·C::;; TA::;;
"t-
o
o
300·C
Parameter
Standard Operating Voltage
25mA
Total Sink Current
40mA
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
O·Cto +70·C
..!J
0.3 Watt at 70·C
Power Dissipation COP413L
Total Source Current
+70·,4.5V::;; Vee::;; 5.5V unless otherwise noted.
Conditions
(Note 1)
Min
Max
Units
4.5
5.5
V
(Vee>
Power Supply Ripple
Peak to Peak
Operating Supply Current
All Inputs and Outputs
Open
Input Voltage Levels
CKllnput Levels
Ceramic Resonator Input (-;- 8)
Logic High (VIH)
Logic Low (VIU
CKI (RC), Reset Input Levels
Logic High
Logic Low
SO Input Level (Test Mode)
IPO-IP7, Sllnput Level
Logic High
Logic Low
L, G Inputs
Logic High
Logic Low
V
8
mA
0.4
V
V
3.0
(Schmitt Trigger Input)
0.7 Vee
0.6
(Note 2)
2.5
(TTL Level)
2.0
(High Trip Levels)
-1
VOL =
VOL =
VOL =
VOL =
V
V
V
0.8
V
V
1.2
V
V
3.6
Input Capacitance
Reset Input Leakage
Output Current Levels
Output Sink Current (Iou
SO and SK Outputs
LO-L7 Outputs, GO-G3
CKO
IPO-IP7, P8, SKIP, AD/DATA
Output Source Current (IOH)
LO-L7 GO-G3, SO, SK
IPO-IP7, P8, SKIP, AD/DATA
SO,SK
IPO-IP7, P8, SKIP, AD/DATA
0.4
7
pF
+1
#LA
0.9
0.4
0.2
1.6
mA
mA
mA
mA
VOH
VOH
VOH
VOH
-25
-25
-1.2
-1.2
#LA
#LA
VIL
-10
O.4V
O.4V
0.4V
O.4V
= 2.4V
= 2.4V
= 1.0V
= 1.0V
= OV
mA
mA
-140
#LA
Total Sink Current Allowed
L7-L4, G Port
L3-LO
Any Other Pin
4
4
2.0
mA
mA
mA
Total Source Current Allowed
Each Pin
1.5
mA
Sllnput Load Source Current
Note 1: Vee voltage change must be less than O.5V in a 1 ms period to maintain proper operation.
Note 2: SO output "0" level must be less than O.SV for normal operation.
1-242
0
0
AC Electrical Characteristics o·c::;; T A ::;; 70·C, 4.5V ::;; Vee::;; 5.5V
Parameter
Conditions
Instruction Cycle Time - tc
CKI
Input Frequency - fi
Duty Cycle
Rise Time
Fall Time
-;- 8 Mode
0I:loo
Min
Max
Units
16
40
J-Ls
0.2
30
fi = 0.5 MHz
CKI Using RC (-;- 4)
"0
0.5
60
500
200
MHz
%
ns
ns
C)
.....
r><•
.....
w
........
0
0
"0
0I:loo
.....
C)
r-
•
:D
R = 56 kn ±5%
C = 100 pF ±10%
Instruction Cycle Time (Note 1)
16
28
J-Ls
.....
W
Inputs:
G3-GO, L7-LO
tSETUP
tHOLD
SI,IPO-IP7
8.0
1.3
J-Ls
J-Ls
tSETUP
tHOLD
2.0
1.0
J-Ls
J-Ls
Output Propagation Delay
Test Condition:
CL = 50 pF, VOUT = 1.5V
RL = 20 kn
SO, SK Outputs
tpd1, tpdO
L, G Outputs
tpd1, tpdO
IPO-IP7, P8, SKIP
tpd1, tpdO
4.0
J-LS
RL = 20kn
5.6
RL = 5 kn
7.2
Note 1: Variation due to the device included.
Pin Descriptions
Connection Diagram
40 -NC
CKO- 1
CKI- 2
IP4- 3
38
RESEi- 4
37
3&
31
IP3- 5
IP2- 8
35
IP1- 7
34
IPO- •
33
IP7- •
IPI- 10
1 7 - 11
r-- NC
r-- AD/DATA
32 r-- SKIP
COP401l·X13N
COP401l·RI3N
u-
31-G3
28 - G l
21 -GO
NC- 15
2& -NC
27 -NC
Vee
GND
IP7-IPO
P8
SKIP
25 -SK
NC- 1&
11
24
23
L2- 11
22
L l - 20
21
u-
AD/DATA
CKI
CKO
RESET
30 -G2
12
LS- 13
L4- 14
VCC -
Pin
I-- Nt
I-- NC
I-- NC
I-- IPS
I-- PI
17
-so
I-- SI
I-- GND
I-- LO
TL/DD/8528-2
FIGURE 2
Order Number COP401L-X13N or COP401L-R13N
See NS Package Number N40A
1-243
Description
8 bidirectional I/O ports
4 bidirectional I/O ports
Serial input (or counter input)
Serial output (or general purpose output)
Logic-controlled clock (or general
purpose output)
Address out/data in flag
System oscillator input
System oscillator output or NC
System reset input
Power supply
Ground
8 bidirectional ROM address and data ports
Most significant ROM address bit output
Instruction skip output
•
C")
,...
~
,...
Timing Waveform
o
'II:t'
a..
o(.)
.......
C")
><
...:.
CKI
(COP"0IL_XI3)~
,...
o
'II:t'
a..
o(.)
INSTRUCTION CYCLE TIME (te)
r-tpdl
I }'/$#/" VOH
~
I
---J_tPdO
~L
AD/DATA, SK
(AS A CLOCK) ~
1fiIIIIII1'l""""..'-------.I:~~
.~
~~~+-""'!""_~---....'!!!!!!!!!~"!
I---
I
--+-
:j
t SETUP
t HOLD
GO-G3, LO-L7, SI ~/M
~~~\\~\\\~\\\\\\\\~\\
IPO-IP7 INPUTS ~~~~~~~'IJJJI.'IJJJI.'IJJJI.'IJJJI.'IJJJI.'IJJJI.'IJJJI.""/JW'JIIU_\.\0._ _ _ _ _ _~---!"~\\~
\'
";!d1
~_pdO
V
GO-G3, LO-L7,
,.;.m,""""""",..----i~f----------.;...-~~
OH
SO, SI OUTPUTS ...;._ _ _ _ _ _ _ _ _ _ _""""'~~'IJIIU
IPO-IP7, P8,
SKIP OUTPUTS
I
I'
t
pd1
-==-'""'' ' ' ' '____ ____ __
J/IIIIII/l
:-?
VOL
~ VOL
TL/DD/8528-3
FIGURE 3. Input/Output Timing Diagram
Development Support
The MOLE (Microcontroller On Line Emulator) is a low cost
development system and real time emulator for COP's products. They also include TMP, 8050, and the new 16-bit HPC
Microcontroller Family. The MOLE provides effective support for the development of both software and hardware in
the user's application.
The personality board contains the necessary hardware and
firmware needed to emulate the target microcontroller. The
emulation cable which replaces the target controller attaches to this board. The software contains a cross assembler
and communications program for up loading and down loading code from the MOLE.
The purpose of the MOLE is to provide a tool to write and
assemble code, emulate code for the target microcontroller
and assist in debugging of the system.
MOLE Ordering Information
PIN
Description
MOLE-BRAIN
MOLE Computer Board
MOLE-COPS-PB1
COPS' Personality Board
Optional Software
MOLE-XXX-YYY
Where XXX = COPS, TMP, 8050, or HPC
YYY = Host System, IBM, APPLE, KAY (Kaypro),
CP/M
The MOLE can be connected to various hosts, IBM PC
STARPLEXTM, Kaypro, Apple, and Intel Systems, via RS232 port. This link facilitate the up loading/down loading of
code, supports host assembly and mass storage.
The MOLE consists of three parts; brain, personality and
optional host software.
The brain board is the computing engine of the system. It is
a self contained computer with its own firmware which provides for all system operation, emulation control, communication, from programming and diagnostic operation. It has
three serial ports which can be connected to a terminal,
host system, printer, modem or to other MOLE's in a mUltiMOLE environment.
1-244
o
INTERNAL LOGIC
Functional Description
The 4-bit A register (accumulator) is the source and destination register for most I/O, arithmetic, logic and data memory
access operations. It can also be used to load the Bd portion of the B register, to load 4 bits of the 8-bit Q latch data,
to input 4 bits of the 8-bit L I/O port data and to perform
data exchanges with the SID register.
A block diagram of the COP401 L-X13/COP401 L-R13 is given in Figure 1. Data paths are illustrated in simplified form to
depict how the various logic elements communicate with
each other in implementing the instruction set of the device.
Positive logic is used. When a bit is set, it is a logic "1"
(greater than 2 volts). When a bit is reset, it is a logic "0"
(less than 0.8 volts).
A 4-bit adder performs the arithmetic and logic functions of
the COP401 L-X13/COP401 L-R13, storing its results in A. It
also outputs a carry bit to the 1-bit C register, most often
employed to indicate arithmetic overflow. The C register, in
conjunction with the XAS instruction and the EN register,
also serves to control the SK output. C can be outputted
directly to SK or can enable SK to be a sync clock each
instruction cycle time. (See XAS instruction and EN register
description, below).
PROGRAM MEMORY
Program Memory consists of a 512-byte external memory.
As can be seen by an examination of the COP401 L-X13/
COP401 L-R13 instruction set, these words may be program
instructions, program data or ROM addressing data. Because of the special characteristics associated with the JP,
JSRP, JID and LQID instructions, ROM must often be
thought of as being organized into 8 pages of 64 words
each.
~
r:><
.....
CI.)
'"
o
o-a
~
o
.....
r:-
:D
.....
CI.)
The Q register is an internal, latched, 8-bit register, used to
hold data loaded from M and A, as well as 8-bit data from
ROM. Its contents are output to the L I/O ports when the L
drivers are enabled under program control. (See LEI instruction.)
The 8 L drivers, when enabled, output the contents of
latched Q data to the L I/O ports. Also, the contents of L
may be read directly into A and M.
The SID register functions as a 4-bit serial-in-/serial-out
shift register or as a binary counter depending on the contents of the EN Register. (See EN register description, below.) Its contents can be exchanged with A, allowing it to
input or output a continuous serial data stream. SID may
also be used to provide additional parallel I/O by connecting
SO to external serial-in/parallel-out shift registers.
ROM instruction words are fetched, decoded and executed
by the instruction Decode, Control and Skip Logic circuitry.
DATA MEMORY
Data memory consists of a 128-bit RAM, organized as 4
data registers of 8 4-bit digits. RAM addressing is implemented by a 6-bit B register whose upper 2 bits (Br) select 1
of 4 data registers and lower 3 bits of the 4-bit Bd select 1 of
8 4-bit digits in the selected data register. While the 4-bit
contents of the selected RAM digit (M) is usually loaded into
or from, or exchanged with, the A register (accumulator), it
may also be loaded into the Q latches or loaded from the L
ports. RAM addressing may also be performed directly by
the XAD 3,15 instruction.
The XAS instruction copies C into the SKL Latch. In the
counter mode, SK is the output of SKL in the shift register
mode, SK outputs SKL ANDed with internal instruction cycle
clock.
The EN register is an internal 4-bit register loaded under
program control by the LEI instruction. The state of each bit
of this register selects or deselects the particular feature
associated with each bit of the EN registers (EN3-ENe).
The most significant bit of Bd is not used to select a RAM
digit. Hence each physical digit of RAM may be selected by
two different values of Bd as shown in Figure 4 below. The
skip condition for XIS and XDS instructions will be true if Bd
changes between 0 and 15, but NOT between 7 and 8 (see
Table 3).
1. The least significant bit of the enable register, ENe, selects the SID Register as either a 4-bit shift register or a
4-bit binary counter. With ENe set, SID is an asynchronous binary counter, decrementing its value by one upon
each low-going pulse ("1" to "0") occurring on the SI
Input. Each pulse must be at least two instruction cycles
wide. SK outputs the value of SKL. The SO Output is
equal to the value of EN3. With ENe reset, SID is a ~erial
shift register shifting left each instruction cycle time. The
data pesent at SI goes into the least significant bit of SID.
SO can be enabled to output the most significant bit of
SID each cycle time. (See 4 below.) The SK output becomes a logic-controlled clock.
RAM DIGIT
15'
14'
U'
12'
11'
10'
9'
2. EN1 is not used. It has no effect on COP401 L-X13/
COP401 L-R13 operation.
3. With EN2 set, the L drivers are enabled to output the data
in Q to the L I/O ports. Resetting EN2 disables the L
drivers, placing the L I/O ports in a high impedance input
state.
1
0'
-a
o
.....
The G register contents are outputs to 4 general-purpose
bidirectional I/O ports.
ROM addressing is accomplished by a 9-bit PC register. Its
binary value selects one of the 512 8-bit words contained in
ROM. A new address is loaded into the PC register during
each instruction cycle. Unless the instruction is a transfer of
control instruction, the PC register is loaded with the next
sequential 9-bit binary count value. Two levels of subroutine
nesting are implemented by the 9-bit subroutine save registers, SA and SB, providing a last-in, first-out (UFO) hardware subroutine stack.
Bd VALUE
o
'CAN BE DIRECTL Y ADDRESSED BY
LBIINSTRUCTIDN (SEE TABLE 3)
TL/DD/6526-4
FIGURE 4. RAM Digit Address
to Physical RAM Digit Mapping
1-245
•
....
C")
a:
..:.
....
Functional Description
Q
"lit'
(Continued)
TABLE I. Enable Register Modes - Bits EN3 and ENo
a..
EN3
ENo
SIO
SI
SO
SK
(.)
0
0
Shift Register
0
1
0
. Shift Register
0
1
Binary Counter
1
1
Binary Counter
Input to Shift
Register
Input to Shift
Register
Input to Binary
Counter
Input to Binary
Counter
If SKL= 1, SK= Clock
If SKL=O, SK=O
If SKL=1, SK=Clock
If SKL=O, SK=O
If SKL = 1, SK = 1
IfSKL=O,SK=O
IfSKL=1, SK=1
IfSKL=O, SK=O
0
.....
....
><
..:.
....
C")
Q
"lit'
a..
0
(.)
4. EN3, in conjunction with ENo, affects the SO output. With
ENo set (binary counter option selected) SO will output
the value loaded into EN3. With ENo reset (serial shift
register option selected), setting EN3 enables SO as the
output of the SIO shift register, outputting serial shifted
data each instruction time. Resetting EN3 with the serial
shift register option selected disables SO as the shift register output; data continues to be shifted through SIO and
can be exchanged with A via an XAS instruction but SO
remains reset to "0". Table 1 provides a summary of the
modes associated with EN3 and ENo.
-
~ -I-
~~ ~~
4. access time = 5 !-,-S max.
Typically these requirements are met using bipolar or MOS
PROMs.
During operation, the address of the next instruction is sent
out on P8 and IP7 through IPO during the time that
AD/DATA is high (logic "1" = address mode). Address
data on the IP lines is stored into an external latch on the
high-to-Iow transition of the AD/DATA line; P8 is a dedicated address output, and does not need to be latched. When
AD/DATA is low (logic "0" = data mode), the output of the
memory is gated onto IP7 through IPO, forming the input
bus. Note that the AD/DATA output has a period of one
instruction time, a duty cycle of approximately 50%, and
specifies whether the IP lines are used for address output or
instruction input.
OSCILLATOR
There are two basic clock oscillator configurations available
as shown by Figure 6.
a. The COP401 L-X13 is a Resonator Controlled Oscillator.
CKI and CKO are connected to an external ceramic resonator. The instruction cycle frequency equals the resonator frequency divided by 8.
I
Vee
COP401L - X13
eOP401L - RI3
b. The COP401 L-R13 is a RC Controlled Oscillator. CKI is
configured as a single pin RC controlled Schmitt trigger
oscillator. The instruction cycle equals the oscillation frequency divided by 4. CKO becomes no connection.
mET
:~
1
3. TTL-compatible inputs
INITIALIZATION
The Reset LogiC will initialize (clear) the device upon powerup if the power supply rise time is less than 1 ms and greater than 1 !-,-S. If the power supply rise time is greater than 1
ms, the user must provide an external RC network and diode to the RESET pin as shown below (Figure 5). The
RESET pin is configured as a Schmitt trigger input. If not
used it should be connected to Vee. Initialization will occur
whenever a logic "0" is applied to the RESET input, provided it stays low for at least three instruction cycle times.
P +
0
W
E
R
S
U
P
P
L
Y
Serial
Out
0
GND
I
RC> 5 x POWER SUPPLY RISE TIME
COP401L-X13
TL/DD/8528-5
COP401L-R13
B
A
Figure 5. Power-Up Clear Circuit
CKI
CKO
CKI
CKO .
~-----R.2--~~ ~.---~~::-vc-c-l~
Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, EN, and G registers are cleared.
The SK output is enabled as a SYNC output, providing a
pulse each instruction cycle time. Data Memory (RAM) is
not cleared upon initialization. The first instruction at address 0 must be a CLRA.
:: R1
f
(H/c)
EXTERNAL MEMORY INTERFACE
The COP401 L-X13/COP401 L-R13 is designed for use with
an external Program Memory. This memory may be implemented using any devices having the following characteristics:
1. random addressing
TL/DD/8528-6
FIGURE 6. COP401L-X13/COP401L-R13 Oscillator
2. TTL-compatible TRI-STATE® outputs
1-246
Functional Description
(Continued)
DISABLE
TL/DD/8S28-7
Vee
~
TL/DD/8528-8
a. Standard Output
b. Push-Pull Output
TLlDD/8S28-9
c. Standard L Ouput
vee
r4J
#5
""T~f
TL/DD/8528-10
TLlDD/8S28-11
d. Input With Load
e. HI-Z Input
FIGURE 7. Input and Output Configurations
Ceramic Resonator Oscillator
, Resonator
Value
455 kHz
1/0 CONFIGURATIONS
COP401 L-X13/COP401 L-R13 inputs and outputs have the
following configurations, illustrated in Figure 7.
a. GO-G3-an enhancement mode device to ground in
conjunction with depletion-mode device to Vee.
b. so, SK, IPO-IP7, P8, SKIP, AD/DATA-an enhancement
mode device to ground in conjunction with a depletionmode device paralleled by an enhancement-mode device
to Vee. This configuration has been provided to allow for
fast rise and fall times when driving capacitive loads.
c. LO-L7-same as a, but may be disabled.
d. 51 has on-chip depletion load device to Vee.
e. RESET has a Hi-Z input which must be driven to a "1" or
"0" by external components.
Curves are given in Figure 8 to allow the designer to effectively use the 1/0 configurations in designing a system.
An important point to remember is that even when the L
drivers are disabled, the depletion load device will source a
small amount of current, however, when the L lines are used
as inputs, the disabled depletion device can not be relied on
to source sufficient current to pull an input to a logic "1 ".
Component Values
R1 (0)
4.7k
I R2 (0) I C1 (pF) I C2 (pF)
I 1M I 220 I 220
RC Controlled Oscillator
R (kO)
C(pF)
Instruction
Cycle Time
(In Ils)
51
82
100
56
19 ± 15%
19 ± 13%
Note: 200 kn ~ R ~ 25 kn
220 pF~C~50 pF
1-247
•
C")
,...
~
Typical Performance Characteristics
-200
Current for Sllnputs
-100
-150
~ -100 ........... ~
.J
~
~AX 0 Vrx=4.5V
o ~l
o 1.0 2,0 3.0 4,0 5.0 6.0 7.0 s.o 9.0 10.0
-900
-so
-800
-70
-700
-60
-600
-so "-
"
-30
-20
~
IWAX 0 Vrx =4.5V
"'l
"k
-10 IWIN 0 Vrx=4.5V
o ~J
o
Source Current for
L7-LO, G3-GO
Output Configuration
-500
.§ -400
~ IWAX 0 vrx= 4.5V
-300 ~~I-I-
r--..
.....
1.0
VIN (VOLTS)
-200
-100
-
_~~ivr-H-r-
o
o
Output Sink Current for SO
andSK
____
l~rn~~~~~~~~
1 2 3 4 5 6 7 8 9 10
VOH (VOLTS)
V I/O
Source Current for SO, SK,
IPO, IP7, P8, SKIP,
AD/DATA Configuration
O~
-1000
-90
t::
5 -<40
0
.S>
-so
Input Current for Lo through
L7 when Output Programmed
Off by Software
4rT~--~--~
Output Sink Current for Lo
through L7 and GO-G3
~
4r-1T--~--~~--~
OL-~--~--~~--~
OL-~--~--~~--~
1-+-t+-+lH--+-+-I-+-+_I
O~~-==-u-~~~~
o
o
1 2 3 4 5 6 7 8 9 10
VOH (VOLTS)
2
o
3
2
3
VOL (VOLTS)
VOL (VOLTS)
Output Sink Current IPO-IP7,
P8, SKIP, AD/DATA
2,Or-I-------,---------,
j-
l'OH---~--+_------_I
OL-------~------~
o
O~
1.0
VOUT (VOLTS)
TL/DD/8528-12
FIGURE 8. I/O Characteristics
1-248
COP40 1L-X 13/COP40 1L-R 13 Instruction Set
Table III provides the mnemonic, operand, machine code,
data flow, skip conditions, and description associated with
each instruction in the COP401 L-X13/COP401 L-R13 instruction set.
Table II is a symbol table providing internal architecture, Instruction operand and operational symbols used in the instruction set table.
TABLE II. COP401L-X13/COP401L-R13 Instruction Set Table Symbols
Symbol
Definition
Internal Architecture Symbols
A
B
Br
Bd
C
EN
G
L
M
PC
Q
SA
SB
SID
SK
4-bit Accumulator
6-bit RAM Address Register
Upper 2 bits of B (register address)
Lower 4 bits of B (digit address)
1-bit Carry Register
4-bit Enable Register
4-bit Register to latch data for G lID Port
a-bit TRI-STATE lID Port
4-bit contents of RAM Memory pointed to by B Register
9-bit ROM Address Register (program counter)
a-bit Register to latch data for L I/O Port
9-bit Subroutine Save Register A
9-bit Subroutine Save Register B
4-bit Shift Register and Counter
Logic Controlled Clock Output
Instruction Operand Symbols
d
r
a
y
RAM(s)
ROM(t)
4-bit Operand Field, 0-15 binary (RAM Digit Select)
2-bit Operand Field, 0-3 binary (RAM Register Select)
9-bit Operand Field, 0-511 binary (ROM Address)
4-bit Operand Field, 0-15 binary (Immediate Data)
Contents of RAM location addressed by s
Contents of ROM location addressed by t
Operational Symbols
+
-
~
~
=
A
Ell
:
Plus
Minus
Replaces
Is exchanged with
Is equal to
The one's complement of A
Exclusive-OR
Range of values
1-249
II
Cf)
<
.....
RAM(B)~A
Bd increments past 15
Bd+1-. Bd
BrEBr-' Br
Exchange A with RAM
(3,15)
Exchange RAM with A
and Decrement Bd,
Exclusive-OR Br with r
Exchange RAM with A
and Increment Bd,
Exclusive-OR Br with r
(')
o-a
01:lIo
Q
.....
r;:::D
.....
w
REGISTER REFERENCE INSTRUCTIONS
CAB
CBA
LBI
r,d
-
LEI
Y
50
4E
10101100001
10100111101
100Irl(d-1)1
(d=O,9:15)
A-.Bd
Bd-.A
r,d - . B
None
None
Skip until not a LBI
33
6-
10011100111
10110 1 Y.. 1
Y-' EN
None
0
1
2
3
20
21
33
21
33
01
11
03
13
1001010000
1001010001
1001110011
1001010001
1001110011
1000010001
1000110001
1000010011
1000110011
0
1
2
3
01
11
03
13
10000100011
10001100011
10000100111
10001100111
Copy A to Bd
Copy Bd toA
LOad B immediate with
r,d (Note 5)
Load EN Immediate
(Note 6)
TEST INSTRUCTIONS
SKC
SKE
SKGZ
SKGBZ
SKMBZ
Skip if C is True
Skip if A Equals RAM
Skip if G is Zero
(all 4 bits)
Skip if G Bit is Zero
C="1"
A=RAM(B)
G3:0=0
1st byte
} 2nd byte
Go=O
G1=0
G2=0
G3=0
RAM(B)o=O
RAM(B)1=0
RAM(B)2=0
RAM(Bb=O
Skip if RAM Bit is Zero
G-.A
None
Input G Ports to A
L7:4 - . RAM (B)
L3:0-. A
RAM(B)-'G
None
Input L Ports to RAM, A
None
Output RAM to G Ports
A ~ SID, C - . SKL
None
Exchange A with SID
(Note 2)
III
INPUTIOUTPUT INSTRUCTIONS
ING
INL
OMG
XAS
33
2A
33
2E
33
3A
4F
10011 10011 1
10010110101
10011100111
10010111101
10011100111
10011 11010 1
10100111111
Note 1: All subscripts for alphabetical symbols Indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined) Bits are numbered
signifies the least significant bit (low-order, right-most bit). For example, A3 indicates the most significant (left-most) bit of the 4-bit A register.
0 to N where 0
Note 2: For additional information on the operation of the XAS, JID, and LaiD Instructions, see below.
Note 3: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or
otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Note 4: A JSRP transfers program control to subroutine page
jump to the last word in page 2.
3. The JP instruction,
2 (010 is loaded into the upper 4 bits of Pl. A JSRP may not be used when in pages 2 or 3. JSRP may not
Note 5: The machine code for the lower 4 bits of the LBI instruction equals the binary value of the "d" data minus 1 e.g., to load the lower four bits of B (Bd) with the value
9 (10012), the lower 4 bits of the LBI instruction equalS (10002)' To load 0, the lower 4 bits of the LBI instruction should equal 15 (11112)'
Note 6: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a
selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
1-251
"1" or "0" in each bit of EN corresponds with the
(f)
,...
a:
Description of Selected Instructions
...:.
,... The following information is provided to assist the user in
o
'OI:t'
D.
oo
.......
(f)
><
...:.
,...
o
'OI:t'
D.
o
o
understanding the operation of several unique instructions
and to provide notes useful to programmers in writing
COP401 L-X13/COP401 L-R13 programs.
XAS INSTRUCTION
XAS (Exchange A with SIO) exchanges the 4-bit contents of
the accumulator with the 4-bit contents of the SIO register.
The contents of SIO will contain serial-in/serial-out shift register or binary counter data, depending on the value of the
EN register. An XAS instruction will also affect the SK output. (See Functional Description, EN Register, above.) If
SIO is selected as a shift register, an XAS instruction must
be performed once every 4 instruction cycles to effect a
continuous data stream.
JID INSTRUCTION
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location pointed
to indirectly by A and M. It loads the lower 8 bits of the ROM
address register PC with the contents of ROM addressed by
the 9-bit word, PCa, A, M. PCa is not affected by this instruction.
Note that JID requires 2 instruction cycles to execute.
LQID INSTRUCTION
LaiD (Load a Indirect) loads the 8-bit a register with the
contents of ROM pointed to by the 9-bit word PCa, A, M.
LaiD can be used for table lookup or code conversion such
as BCD to seven-segment. The LaiD instruction "pushes"
the stack (PC + 1 ----+ SA ----+ S8) and replaces the least
significant 8 bits of PC as follows: A ----+ PC7:4, RAM (8)
----+ PC3:0, leaving PCa unchanged. The ROM data pointed
to by the new address is fetched and loaded into the a
latches. Next, the stack is "popped" (S8 ----+ SA ----+ PC),
restoring the saved value of PC to continue sequential program execution. Since LaiD pushes SA ----+ S8, the previous contents of S8 are lost. Also, when LaiD pops the
stack, the previously pushed contents of SA are left in S8.
The net result is that the contents of SA are placed in S8
(SA ----+ S8). Note that LaiD takes two instruction cycle
times to execute.
INSTRUCTION SET NOTES
a. The first word of a COP401 L-X13/COP401 L-R 13 program (ROM address 0) must be a CLRA (Clear A) instruction.
b. Although skipped instructions are not executed, one instruction cycle time is devoted to skipping each byte of
the skipped instruction. Thus all program paths except
JID and LaiD take the same number of cycle times
whether instructions are skipped or executed. JID and
LaiD instructions take 2 cycles if executed and 1 cycle if
skipped.
c. The ROM is organized into 8 pages of 64 words each.
The Program Counter is a 9-bit binary counter, and will
count through page boundaries. If a JP, JSRP, JID or
LaiD instruction is located in the last word of a page, the
instruction operates as if it were in the next page. For
example: a JP located in the last word of a page will jump
to a location in the next page. Also, a LaiD or JID located
in the last word of page 3 or will access data in the next
group of 4 pages.
COPS Programming Manual
For detailed information on writing COPS programs, the
COPS Programming Manual 424410284-001 provides an indepth discussion of the COPS architecture, instruction set
and general techniques of COPS programming. This manual
is written with the programmer in mind.
Typical Applications
PROM-Based System
The COP401L-X13/COP401L-R13 may be used to emulate
the COP413L. Figure 9 shows the interconnect to implement a COP401 L-X13/COP401 L-R 13 hardware emulation.
This connection uses one MM2716 EPROM as external
memory. Other memory can be used such as bipolar PROM
or RAM.
Pins IP7-IPO are bidirectional inputs and outputs. When the
AD/DATA clocking output turns on, the EPROM drivers are
disabled and IP7-IPO output addresses. The 8-bit latch
(MM74C373) latches the addresses to drive the memory.
When AD/DATA turns off, the EPROM is enabled and the
IP7-IPO pins will input the memory data. P8 outputs the
most significant address bit to the memory. (SKIP output
may be used for program debug if needed.)
Twenty of the COP401 L-X13/COP401 L-R 13 pins may be
configured exactly the same as the COP413L. Selection of
the COP401L-X13 or COP401L-R13 depends upon which
oscillator is selected for the COP413L.
Oscillator Requirement
Order
ROMless
COP413L Option 1 = 0 Ceramic Resonator COP401 L-X13
or external input
frequency divided by
8. CKO is oscillator
out.
Option 1 = 1 Single Pin RC
COP401 L-R13
controlled oscillator
divided by 4. CKO is
no connection.
1-252
o
o"'CI
Typical Applications (Continued)
~
....
r:....><
w
Q
24
U!
12
I19
~
23
1
2
3
4
S
6
7
19 16 15 12
20
10
L.!.
9
6
sl
8
2,
Vee
Vpp
........
o
Vss
o
Al0
"'CI
~
Q
A8
A7
1.41.42716
2048 X 8 EPROM
A6
AS
A4
A3
A2
cs J!
OE
Al
AO
17 16 15 14 13 11 10
GND
[E
74LS373
OUTPUT DIS
08 D7 D6 D5 D4 03 02 01
18 17 14 13
8
7
4\ 3'
32
9
l
9
35
20
B7 B6 B5 B4 B3 B2 Bl BO
08 07 06 05 04 03 02 01
Vee
....
r::D
....w
A9
10 36 3
567
8
IP7 IP6 IPS IP4 IP3 IP2 IPI IPO
33
134
AD/DATA NC
P8
NC
40
14
NC
39
17
NC
38
NC
37
SKIP
COP401 L - X13/COP401 L - R13
18
19
13
20
-1211
21
NC NC
NC NC
-
23124rsI16/SI2\28129130131 1 112126127141
COP413L { 1 2 3 4 S 6
PINOUT
L4 Vee L3 L2 L1 LO
9 10 11 12 13 14 IS 16
SK GND GO Gl G2 G3 CKO CKI
7 8
SI SO
17
RESET
18 19 20
L7 L6 LS
TlIDD/B528-13
FIGURE 9. COP401L-X13/COP401L-R13 Used to Emulate a COP413L
1-253
::E
N
o
~
a.
oo
.......
~National
D Semiconductor
N
o
~
a.
oo
COP402/COP402M ROMless N-Channel Microcontrollers
General Description
Features
The COP402/COP402M ROMless Microcontrollers are
members of the COPSTM family, fabricated using N-channel
silicon gate MOS technology. Each part contains CPU,
RAM, and I/O, and is identical to a COP420 device, except
the ROM has been removed; pins have been added to output the ROM address and to input ROM data. In a system,
the COP402 or 402M will perform exactly as the COP420;
this important benefit facilitates development and debug of
a COP420; this important benefit facilitates development
and debug of a COP420 program prior to masking the final
part. These devices are also appropriate in low volume applications, or when the program may require changing. The
COP402M is identical to the COP402, except the MICROBUSTM interface option has been implemented.
• Extended temperature ( - 40·C to + a5·C) COP302/
COP302M, available as special order
The COP402 may also be used to emulate the COP410L,
411 L, or 420L by appropriately reducing the clock frequency.
•
•
•
•
•
•
•
•
•
•
•
•
•
Low cost
Exact circuit equivalent of COP420
Standard 40-pin dual-in-line package
Interfaces with standard PROM or ROM
64 x 4 RAM, addresses up to 1k x a ROM
MICROBUS compatible (COP402M)
Powerful Instruction set
True vectored interrupt, plus restart
Three-level subroutine stack
4.0 ,..,S instruction time
Single supply operation (4.5V to 6.3V)
Internal time-base counter for real-time processing
Internal binary counter register with MICROWIRETM
serial 110 capability
• Software/hardware compatible with other members of
COP400 family
Block Diagram
AD/iiilA
lJ
,.
'1
IPJ
I,.
IPI
1P4
1P3
IPz
IPI
IPI
J4
31
I
,
IUFFERS
31
IP
BUFfERS
IKIP
CNDTUIEDI
r--------+..t:...-:J--~ '"
HEVELSTACK
\I
IZ
1314
..
II
ZD
ZI
ZJ 1.15 ZI
IN3 INZ INI IND
TL/DD/6915-1
FIGURE 1
1-254
o
COP402/COP402M and COP302/COP302M
o"0
Absolute Maximum Ratings
.......
"'o"
III)
If Mllltaryl Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Voltage at Any Pin
-0.3Vto +7V
Operating Temperature Range
COP402/COP402M
O°Cto 70°C
Storage Temperature Range
- 65°C to + 150°C
lead Temperature (soldering, 10 sec.)
300°C
Package Power Dissipation
750 mW at 25°C
400 mW at 70°C
250 mW at 85°C
Total Sink Current
50 rnA
Total Source Current
70 rnA
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
COP402/COP402M
DC Electrical Characteristics O°C ~ TA ~ 70°C, 4.5V s: Vee ~ 6.3V unless otherwise noted
Parameter
Conditions
Operation Voltage
Power Supply Ripple
Peak to Peak (Note 3)
Supply Current
All Outputs Open Vee
Input Voltage levels
CKllnput levels
Crystal Input
logic High
logic low
Schmitt Trigger Input
RESET
logic High
logic low
All Other Inputs
logic High
logic High
logic low
Input load Source Current
Min
Max
Units
4.5
6.3
V
0.4
V
40
rnA
2.4
-0.3
0.4
V
V
0.7 Vee
-0.3
0.6
V
V
= 5V
Vee
Vee
= Max
= 5V ±5%
3.0
2.0
-0.3
0.8
V
V
V
Vee
= 5V, VIN = OV
-100
-800
p.A
7
pF
-1
+1
p.A
Vee = 5V ±10%
IOH = -100 p.A
IOL = 1.6mA
2.4
-0.3
0.4
V
V
IOH = -75 p.A
IOL = 400 p.A
2.4
-0.3
0.4
V
V
IOH = -10 p.A
IOL = 10 p.A
Vee -1
-0.3
0.2
V
V
2.5
14
rnA
-50
+50
p.A
10
16
10
rnA
rnA
rnA
rnA
-15
-1.5
rnA
rnA
Input Capacitance
Hi-Z Input leakage
Output Voltage levels
0, G, l, SK, SO Outputs
TTL Operation
logic High
logic low
IPO-IP7, P8, P9, SKIP, CKO,
AD/DATA
logic High
logic low
CMOS Operation (Note 1)
logic High
logic low
Vee
Output Current levels
lED Direct Drive (COP402)
logic High
Vee
VOH
TRI-STATE® (COP402M) leakage Current
Vee
= 5V
= 6V
= 2.0V
= 5V
Allowable Sink Current
Per Pin (l, 0, G)
Per Pin (All Others)
Per Port (l)
PerPort(D,G)
2
Allowable Source Current
Per Pin (l)
Per Pin (All Others)
Note 1: TRI-STATE and LED configurations are excluded.
1-255
o
o"0
"'o"
III)
3:
::E
N
ov
Q.
o
o.......
COP402/COP402M
AC Electrical Characteristics o·c s: TA s: 70·C,4.5V s: Vee s: 6.3V unless otherwise noted
Parameter
N
o
Conditions
v
Instruction Cycle Time
oo
Operating CKI Frequency
+ 16 Mode
CKI Duty Cycle (Note 1)
Rise Time
Fall Time
Frequency
Frequency
Q.
Min
Max
4
10
,."s
1.6
4.0
MHz
40
60
60
40
%
ns
ns
= 4 MHz
= 4 MHz
Units
Inputs:
SI
tSETUP
tHOLO
All Other Inputs
tSETUP
tHOLO
Output Propagation Delay
Test Conditions:
RL = 5k, CL = 50 pF, VOUT
=
0.3
250
,."s
1.7
300
,."s
ns
ns
1.5V
SOandSK
1.0
1.0
,."s
,."s
tpd1
tpdO
AD/DATA, SKIP
0.25
0.25
,."s
,."s
tpd1
tpdO
All Other Outputs
0.6
0.6
,."s
,."s
1.4
1.4
,."s
,."s
375
250
ns
ns
ns
ns
ns
700
ns
ns
ns
ns
ns
ns
tpd1
tpdO
CKO
tpd1
tpdO
MICROBUS Timing
Read Operation (Figure 4)
Chip Select Stable before RD-teSR
Chip Select Hold Time for RD-tRes
RD Pulse Width-tRR
Data Delay from RD-tRO
RD to Data Floating-toF
CL
= 100 pF, Vee =
65
20
400
Write Operation (Figure 5)
Chip Select Stable before WR-tesw
Chip Select Hold Time for WR-twes
WR Pulse Width-tww
Data Set-Up Time for WR-tow
Data Hold Time for WR-two
INTR Transition Time from WR-twi
Note
1: Duty Cycle =
tWI/(tWl
+
5V ±5%
65
20
400
320
100
two).
Note 2: See Figure 9 for additional I/O characteristics.
Note 3: Voltage change must be less than O.SV in a 1 ms period.
Note 4: Exercise great care not to exceed maximum device power dissipation limits when direct driving LEOs (or sourcing similar loads) at high temperature.
1-256
o
Connection Diagram
o"U
Pin Descriptions
Pin
Dual-In-Llne Package
~
oI\)
Description
L7-Lo
8 bidirectional 1/0 ports with TAl-STATE
CKO
40
00
G3- GO
CKI
39
01
03- 0 0
4 bidirectional I/O ports
4 general purpose outputs
4 general purpose inputs
o"U
~
oI\)
IP4
31
02
RESET
37
03
IP3
36
IPS
IN3-INo
SI
IP2
35
PI
SO
Serial output (or general purpose output)
PI
SK
33
AD/DATA
Logic-controlled clock (or general purpose output)
IPI
IPO
SKIP
IP7
IP6
COP402
COP402M
10
31
SKIP
Instruction skip output
17
11
L8
12
GI
CKI
System oscillator input
L5
L4
INI
IN2
13
GO
CKO
14
IN3
RESET
System oscillator output
System reset input
Vcc
17
L3
18
L2
LI
19
G2
15
INO
16
SK
Vee
Power supply
SI
GND
IP7-IPO
Ground
8 bidirectional ROM address and data ports
GND
P8,P9
2 most significant ROM address outputs
SO
20
21
s::::
Serial input (or counter input)
AD/DATA Address out/data in flag
G3
LD
TL/DD/6915-2
Top View
Order Number COP402N or COP402MN
See NS Package Number N40A
FIGURE 2.
Timing Diagrams
CKI
I·
G3-Go.
03-00. _...J~
L7-Lo.SO.SK
OUTPUTS
______~--,~~~~iiiii-----------:'~~~
~~"".11.1100
SKIP OUTPUT
tPDI-.!
PI. Pl6~lp~;~
____",fAIljWIlj$Ilj~"'~Ilj.W/lrg
tPDO
_______
1TL/DD/6915-3
FIGURE 3a. Input/Output Timing Diagrams (Crystal + 16 Mode)
~I~I
CKI~
c,o~~r
'po,
~ l= ---:r ~
lPOO
FIGURE 3b. CKO Output Timing
1-257
TLlDD/6915-4
........
o
:IE
N
o
-.:t
Timing Diagrams (Continued)
Q.
oo
(lN1)
fiIj
(L7-LO)
07-0D
-.:t
------~--~\I
Q.
o
I
t R R - - -......~J_tRCS::::j
Ir-----~-----
,-I
N
'"
o
o
,
J
~tcsR-t=:=tRO-
.,J
_ t O F - - -•
------------t(Ir------.....;.-------"\Ir-TL/DD/6915-5
FIGURE 4. MICROBUS Read Operation Timing
twW
tcsw- •
(JN2)
cs
• -twcs-/
I
\.
~tow-
(lN3)
WR
(L7-Lo!
07- 00
(Go)
-
.
twl
INTR
two
~
1X
TLlDD/6915-6
FIGURE 5. MICROBUS Write Operation Timing
Functional Description
A block diagram of the COP402 is given in Figure 1. Data
paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. Positive logic is
used. When a bit is set, it is a logic "1" (greater than 2V).
When a bit is reset, it is a logic "0" (less than 0.8V).
contents of the operand field of these instructions. The Bd
register also serves as a source register for 4-bit data sent
directly to the 0 outputs.
INTERNAL LOGIC
The 4-bit A register (accumulator) is the source and destination register for most liD, arithmetic, logic and data memory access operations. It can also be used to load the Br
and Bd portions of the B register, to load and input 4 bits of
the B·bit a latch data, to input 4 bits of the 8-bit L I/O port
data and to perform data exchanges with the SID register.
PROGRAM MEMORY
Program Memory consists of a 1,024-byte external memory
(typically PROM). Words of this memory may be program
instructions, program data or ROM addressing data. Because of the special characteristics associated with the JP,
JSRP, JID and LaiD instructions, ROM must often be
thought of as being organized into 16 pages of 64 words
each.
A 4-blt adder performs the arithmetic and logic functions of
the COP402/402M, storing its results in A. It also outputs a
carry bit to the 1-bit C register, most often employed to
indicate arithmetic overflow. The C register, in conjunction
with the XAS instruction and the EN register, also serves to
control the SK output. C can be outputted directly to SK or
can enable SK to be a sync clock each instruction cycle
time. (See XAS instruction and EN register description, below.)
Four general-purpose Inputs, IN3-INo, are provided; IN1,
IN2, and IN3 may be selected, by a mask-programmable
option, as Read Strobe, Chip Select and Write Strobe inputs, respectively, for use in MICROBUS applications.
The 0 register provides 4 general-purpose outputs and is
used as the destination register for the 4-bit contents of Bd.
The G register contents are outputs to 4 general-purpose
bidirectional 110 ports. Go may be mask-programmed as a
"ready" output for MICROBUS applications.
The Q register is an internal, latched, 8-bit register, used to
hold data loaded to or from M and A, as well as 8·bit data
from ROM. Its contents are output to the L 110 ports when
the L drivers are enabled under program control. (See LEI
instruction.) With the MICROBUS option selected, a can
also be loaded with the 8-bit contents of the L 110 ports
upon the occurrence of a write strobe from the host CPU.
ROM addressing is accomplished by a 10-bit PC register. Its
binay value selects one of the 1,024 8-bit words contained
in ROM. A new address is loaded into the PC register during
each instruction cycle. Unless the instruction is a transfer of
control instruction, the PC register is loaded with the next
sequential 10-blt binary count value. Three levels of subroutine nesting are implemented by the 10-bit subroutine
save registers, SA, SB and SC, providing a last-in, first-out
(LIFO) hardware subroutine stack.
ROM instruction words are fetched, decoded and executed
by the Instruction Decode, Control and Skip Logic circuitry.
DATA MEMORY
Data memory consists of a 256-bit RAM, organized as 4
data registers of 16 4-bit digits. RAM addressing is implemented by a 6-bit B register whose upper 2 bits (Br) select 1
of 4 data registers and lower 4 bits (Bd) select 1 of 16 4-bit
digits in the selected data register. While the 4-bit contents
of the selected RAM digit (M) is usually loaded into or from,
or exchanged with, the A register (accumulator), it may also
be loaded into or from the a latches or loaded from the L
ports. RAM addressing may also be performed directly by
the LDD and XAD instruction based upon the 6-bit
1-258
Functional Description
o
o
-a
(Continued)
shift register option selected disables SO as the shift register output; data continues to be shifted through SIO and
can be exchanged with A via an XAS instruction but SO
remains reset to "0." The table below provides a summary of the modes associated with EN3 and ENo.
The 8 L drivers, when enabled, output the contents of
latched a data to the L I/O ports. Also, the contents of L
may be read directly into A and M. As explained above, the
MICROBUS option allows L I/O port data to be latched into
the a register. L I/O ports can be directly connected to the
segments of a multiplexed LED display (using the LED Direct Drive output configuration option) with a data being
outputted to the Sa-Sg and decimal point segments of the
display.
The following features are associated with the IN1 interrupt
procedure and protocol and must be considered by the programmer when utilizing interrupts.
a. The interrupt, once acknowledged as explained below,
pushes the next sequential program counter address (PC
+ 1) onto the stack, pushing in turn the contents of the
other subroutine-save registers to the next lower level
(PC + 1 ~ SA ~ SB ~ SC). Any previous contents of SC are lost. The program counter is set to hex
address OFF (the last word of page 3) and EN1 is reset.
The XA5 Instruction copies C into the SKL latch. In the
counter mode, SK is the output of SKL. In the shift register
mode, SK outputs SKL AN Oed with internal instruction cycle
clock.
b. An interrupt will be acknowledged only after the following
conditions are met:
1. EN1 has been set.
2. A low-going pulse ("1" to "0") at least two instruction
The EN register is an internal 4-bit register loaded under
program control by the LEI instruction. The state of each bit
of this register selects or deselects the particular feature
associated with each bit of the EN register (EN3-ENo).
cycles wide occurs on the IN1 input.
3. A currently executing instruction has been completed.
4. All successive transfer of control instructions and successive LBls have been completed (e.g., if the main
program is executing a JP instruction which transfers
program control to another JP instruction, the interrupt
will not be acknowledged until the second JP instruction has been executed.
c. Upon acknowledgement of an interrupt, the skip logic
status is saved and later restored upon the popping of the
stack. For example, if an interrupt occurs during the execution of ASC (Add with Carry, Skip on Carry) instruction
which results in carry, the skip logic status is saved and
program control is transferred to the interrupt servicing
routine at hex address OFF. At the end of the interrupt
routine, a RET instruction is executed to "pop" the stack
and return program control to the instruction following the
original ASC. At this time, the skip logic is enabled and
skips this instruction because of the previous ASC carry.
Subroutines and the LaiD instruction should not be nested within the interrupt servicing routine since their popping of the stack enables any previously saved main program skips, interfering with the orderly execution of the
interrupt routine.
d. The first instruction of the interrupt routine at hex address
OFF must be a NOP.
e. An LEI instruction can be put immediately before the RET
to re-enable interrupts.
1. The least significant bit of the enable register. ENo. selects the SIO register as either a 4-bit shift register or a
4-bit binary counter. With ENo set, SIO is an asynchronous binary counter, decrementing its value by one upon
each low-going pulse ("1" to "0") occurring on the SI
input. Each pulse must be at least two instruction cycles
wide. SK outputs the value of SKL. The SO output is
equal to the value of EN3. With ENo reset, SIO is a serial
shift register shifting left each instruction cycle time. The
data present at SI goes into the least significant bit of
SIO. SO can be enabled to output the most significant bit
of SIO each cycle time. (See 4 below.) The SK output
becomes a logic-controlled clock.
2. With EN1 set the IN1 input is enabled as an interrupt input. Immediately following an interrupt, EN1 is reset to
disable further interrupts.
3. With EN2 set, the L drivers are enabled to output the data
in a to the L I/O ports. Resetting EN2 disables the L
drivers, plaCing the L I/O ports in a high-impedance input
state. If the MICROBUS option is being used, EN2 does
not affect the L drivers.
4. EN3, in conjunction with ENo, affects the SO output. With
ENo set (binary counter option selected) SO will output
the value loaded into EN3.· With ENo reset (serial shift
register option selected), setting EN3 enables SO as the
output of the SIO shift register, outputting serial shifted
data each instruction time. Resetting EN3 with the serial
TABLE I. Enable Register Modes-Bits EN3 and ENo
EN3
ENo
510
51
50
0
0
Shift Register
Input to Shift Register
0
1
0
Shift Register
Input to Shift Register
Serial Out
0
1
Binary Counter
Input to Binary Counter
0
1
1
Binary Counter
Input to Binary Counter
1-259
o
o-a
~
o
N
INTERRUPT
The 510 register functions as a 4-bit serial-in/serial-out
shift register or as a binary counter depending on the contents of the EN register. (See EN register description
below.) Its contents can be exchanged with A, allowing it to
input or output a continuous serial data stream. SIO may
also be used to provide additional parallel I/O by connecting
SO to external serial-in/parallel-out shift registers.
~
o
N
.......
1
5K
If SKL
If SKL
If SKL
If SKL
If SKL
If SKL
If SKL
IfSKL
= 1, SK =
= 0, SK =
= 1. SK =
= 0, SK =
= 1, SK =
= 0, SK =
= 1, SK =
= O,SK =
SYNC
0
SYNC
0
1
0
1
0
s:
:e
N
Q
"lilt'
a..
oo
......
N
Q
"lilt'
a..
o
o
Functional Description
(Continued)
Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, 0, EN, G, and SO are cleared. The
SK output is enabled as a SYNC output, providing a pulse
each instruction cycle time. Data Memory (RAM) is not
cleared upon initialization. The first instruction at address 0
must be a CLRA.
MICROBUS INTERFACE
The COP402M can be used as a peripheral microprocessor
device, inputting and outputting data from and to a host microprocessor (J-LP). IN1, IN2, and IN3 general purpose inputs
become MICROBUS compatible read-strobe, chip-select,
and write-strobe lines, respectively. IN1 becomes RD-a
logic "0" on this input will cause Q latch data to be enabled
to the L ports for input to the J-LP. IN2 becomes C8-a logic
"0" on this line selects the COP402M as the J-LP peripheral
device by enabling the operation of the RD and WR lines
and allows for the selection of one of several peripheral
components. IN3 becomes WR-a logic "0" on this line will
write bus data from the L ports to the Q latches for input to
the COP402M. Go becomes INTR, a "ready" output reset
by a write pulse from the J-LP on the WR line, providing the
"handshaking" capability necessary for asynchronous data
transfer between the host CPU and the COP402M.
P
+
0
W
E
R
S
U
P
P
L
V
j
... ~ -:-
vcc
:~ ~~
COP402/402M
IfEffi
:::::
GNO
I
-
RC ~ 5 x Power Supply Rise Time
TL/DD/6915-8
FIGURE 7. Power-Up Clear Circuit
OSCILLATOR
This option has been designed for compatibility with National's MICROBU8-a standard interconnect system for 8-bit
parallel data transfer between MOS/LSI CPUs and interfacing devices. (See MICROBUS, National Publication.) The
functioning and timing relationships between the COP402M
signal lines affected by this option are as specified for the
MICROBUS interface, and are given in the AC electrical
characteristics and shown in the timing diagrams (Figures 4
and 5). Connection to the MICROBUS is shown in Figure 6.
There are two basic clock oscillator configurations available
as shown by Figure 8.
a. Crystal Controlled Oscillator. CKI and CKO are connected to an external crystal. The instruction cycle time
equals the crystal frequency divided by 16.
b. External Oscillator. CKI is driven by an external clock
signal. The instruction cycle time is the clock frequency
divided by 16.
A
CKO
C~
INTERRUPT IINTR)
t.Io~~
Go
A a·BIT DATA BUS ....
1"___
00...-_07__--..,, LO- L7
MICROPROCESSOR
...
".
READ STROBE 1M)
CHIP SElECT (CS)
WRITE STROBE (\VA)..
RESET
~
.Io~~
..ru-
r"4'D~
COP402M
IN1
INZ
IN3
NOT USED
EXTERNAL
CLOCK
TL/DD/6915-9
Crystal
Value
RESET
+
RElET
TL/DD/6915-7
FIGURE 6. MICROBUS Option Interconnect
Component Values
R1
R2
C
4MHz
1k
1M
27 pF
3.58 MHz
1k
1M
27pF
2.09 MHz
1k
1M
56pF
FIGURE 8. COP402/402M Oscillator
INITIALIZATION
EXTERNAL MEMORY INTERFACE
The Reset Logic will initialize (clear) the device upon powerup if the power supply rise time is less than 1 ms and greater than 1 J-Ls. If the power supply rise time is greater than 1
ms, the user must provide an external RC network and diode to the RESET pin as shown below. The RESET pin is
configured as a Schmitt trigger input. If not used it should be
connected to Vee. Initialization will occur whenever a logic
"0" is applied to the RESET input, provided it stays low for
at least two instruction cycle times.
The COP402 and COP402M are designed for use with an
external Program Memory. This memory may be implemented using any devices having the following characteristics:
1. random addressing
2. TIL-compatible TRI-STATE outputs
3. TIL = compatible inputs
4. access time = 1.0 J-Ls, max.
Typically these requirements are met using bipolar or MOS
PROMs.
1-260
o
o
Functional Description
(Continued)
During operation, the address of the next instruction is sent
out on P9, P8, and IP7 through IPO during the time that
AD/DATA is high (logic "1" = address mode). Address
data on the IP lines is stored into an external latch on the
high-to-Iow transition of the AD/DATA line; P9 and P8 are
dedicated address outputs, and do not need to be latched.
When AD/DATA is low (logic "0" = data mode), the output
of the memory is gated onto IP7 through IPO, forming the
input bus. Note that the AD/DATA output has a period of
one instruction time, a duty cycle of approximately 50%,
and specifies whether the IP lines are used for address output or instruction input. A simplified block diagram of the
external memory interface is shown in Figure 9.
"tJ
~
INPUTIOUTPUT
COP402 outputs have. the following configurations, illustrated in Figure 10.
a_ Standard-an enhancement-mode device to ground in
conjunction with a depletion-mode device to Vee, compatible with TIL and CMOS input requirements.
b. High Drive-same as a. except greater current sourcing
capability.
c. Push-Pull-an enhancement-mode device to ground in
conjunction with a depletion-mode device paralleled by
an enhancement-mode device to Vee. This configuration
has been provided to allow for fast rise and fall times
when driving capacitive .Ioads.
d. LED Direct Drive-an enhancement-mode device to
ground and to Vee, meeting the typical current sourcing
requirements of the segments of an LED display. The
sourcing device is clamped to limit current flow. These
devices may be turned off under program control (see
Functional Description, EN Register), placing the outputs
in a high-impedance stat~ to provide required LED segment blanking for a multiplexed display.
e. TRI-STATE Push-Pull-an enhancement-mode device
to ground and Vee intended to meet the requirements
associated with the MICROBUS option. These outputs
are TRI-STATE outputs, allowing for connection of these
outputs to a data bus shared by other bus drivers.
P9
-pa
~
COP402
AD/DATA
IP7 -IPo
. ./"11..
.A
ag(
...
_+K
DATA
~v"
D
LATCH
Q
en
en
I
a
f. Inputs have an on-chip depletion load device to Vee, as
shown in Figure 10t.
The above input and output configurations share common
enhancement-mode and depletion-mode devices. Specifically, all configurations use one or more of six devices
(numbered 1-6, respectively). Minimum and maximum current (lOUT and VOUT) curves are given in Figure 10 for each
of these devices.
The SO, SK outputs are configured as shown in Figure 10e.
The D and G outputs are configured as shown in Agure 10a.
~ 8
c
c
~c(>'
V
AD - A7
~
DO - D7
CE
~ Aa
A9
MEMORY
TLlDD/6915-10
FIGURE 9. External Memory Interface to COP402
1-261
o
N
......
o
o"tJ
~
o
N
3:
:E
N
Q
~
Q.
Functional Description
(Continued)
N
Q
Note that when inputting data to the G ports, the G outputs
should be set to "1". The L outputs are configured as in
Figure 10d on the COP402. On the COP402M the L outputs
are as in Figure 10e.
o
An important point to remember if using configuration d with
the L drivers is that even when the L drivers are disabled,
o
o
......
l
o
the depletion load device will source a small amount of current. (See Figure 11.)
IP7 through IPO outputs are configured as shown in Figure
10e; P9, PS, SKIP, and AD/DATA are configured as shown
in Figure 10b.
vee
TL/DD/6915-11
a. Standard
c~
TLlDD/6915-13
TL/DD/6915-12
c. Push-Pull
b. High Drive
vee
lNPUT&~
TL/DD/6915-15
TL/DD/6915-14
d.lED
e. TRI-STATE Push-Pull
(.I. is Depletion Device)
FIGURE 10. Input/Output Configurations
1-262
TL/DD/6915-18
f.lnput with load
(')
o
Typical Performance Characteristics
"tJ
~
Output Sink Current
15~,r--r--r~r--r--r-~
-0.4
oI\)
Depletion Load OFF
Source Current
-2.0
-1. 71
5
\
MIN
-0.5 r---f"~r*lIoodf++-Ir--J
\
4
r--P"~!T-~....t!--""v--i----t
-0.25
5
VOUT (VOLTS)
DEVICE 1
VOUT (VOLTS)
HIgh Drive Source Current
Vour (VOLTS)
DEVICE 2
Push·Pull Source Current
-20
L"-.
-11
-Ir-~--+--+--+--+--r-~
I
-11
1
-12
~
-I
~
""""'I
4
DEVICE 3
TRI-STATE
Output Source Current
I I
Vcc·
\
,- IX
I'" I"""'<
-'"
I
I
I
:,..Vc -4.IV (MAX)
V
11
-2
LED Output Direct LED Drive
I
\.
,
-4
VOUT (VOLTS)
I
-uv (MAX) I
l\rfo"'"
1\
\
-10
-I
OEVICE 2h
\ VCC
~
-14
VOUT (VOLTS)
DEVICE 2
LED Output Source Current
-10
I
I
Vcc· 1.3V (MIN)
I
/
~
uv (MIN)
l'-J
VOUT (VOLTS)
I
I
DEVICE 4
Input Load Current
-11
-11
MAX
-14
:c
.!
~
VOUT- 2.DV
-10
i
"
"
~
....... l- I"""'"
u
-10
t+--f\--\-++-t--t-+--i
~
/
-I
-4
;'
LfI'"
-I
-2
~'
.... V
-12
u
VCC (VOLTS)
..:t
8.5
OEVICE 4
2
3
4
VOUT (VOLTS)
5
DEVICE 5
FIGURE 11. COP402/COP402M Input/Output Characteristics
1-263
o"tJ
oI\)
==
~ -D. 75 k-~-r"oc:'-+-f--1r--t----1r--I
D~'\.
3
~
-1.0 rT~c:::...;.:;=-+~-'--t--i
~MAX
-0. 1
2
'--t---r--t---I--t--I-~
! -1.25
~ -0.2 1\
~
(')
-1.5 k--::7'~F--r-'-r-+--t--J
-0.3
.......
Standard Output Source
Current
TL/DD/6915-17
:E
N
Q
~
Typical Performance Characteristics
(Continued)
D.
o
o
.......
15
L Output Depletion Load Off
Source Current
Output Sink Current
N
Q
~
D.
oo
10Hf-t---1I'~
<" -0.4
g
~ -0.3
-0.2
-0.1
~l\
4
2
3
4
VOUT (VOLTS)
-1.75
N.
VOUT (VOLTS)
DEVICE 1
Standard Output Source Current
-1.5
P'r-l~-.--=--r......!...1f--+-_+_--l
-1. 25
I-----'t~:_'_---:-~-:-:-:-:':-:--+-_+_--l
!
-1.0 I-T-II'-'I.:-+---t---If--+-_+_--l
§
-0.75 I---+..........-+''r-+---If---+---+-----l
DEVICE 2
Push Pull Source Current
- 3.0 ,...---,-"TT'"'-r-r--.,--,,---r--,
- 2.5 I---ti--t--t-t-tt'-I="-=t----i
- 2.0 f--++-+t--4+--4-!.
<"
E
;: -1.5 f--+--l-PHH--.'+-I--+---i
....
§
-1.0 I----f)'--H-+-t---{.-I-'---'t----i
-0.5
2
4
DEVICE 2 AND 3
VOUT (VOLTS)
3
4
VOUT (VOLTS)
DEVICE 2
LED Output Device LED Drive
,
LED Output Source Current
...g
....
-24r-~---r--~--,...---r-~
-14
-20
-12
-16
/
/MAX
-10
<"
g
-12
....
::>
-B
/
::>
~
~
-B
-6
-4
2
3
4
VOUT (VOLTS)
5
,
,,
,,
-2
6
o
DEVICE 4 AND 2
....
4.0
/
VDUT = 2.0V
"
4.5
,..,- .-
5.0
VCC (VOLTS)
TRI·STATE Output Source Current
5.5
6.0
DEVICE 4 AND 2
Input Load Source Current
-15~-+--Hr_~,--r__+-:-+-____i
-1.0 1---+--+--+---1-'---+---1
<" -10
g
-O.B
<"
E
....
§
;: -0.6 I---"'d--rl----:-f-----=''='''''''*=_-I
§
-5
- 0.2
2
4
VOUT (VOLTS)
t------\:--t----'~-l"t.:--+-__I
3
4
VOUT (VOLTS)
DEVICE 5
FIGURE 11a. COP302/COP302M Input/Output Characteristics
1-264
DEVICE 6
TL/DD/6915-1B
o
o
Instruction Set
"0
Table II is a symbol table providing internal architecture, instruction operand and operational symbols used in the Instruction set table.
Table III provides the mnemonic, operand, machine code,
data flow, skip conditions and description associated with
each instruction in the COP402/402M instruction set.
~
o
N
o
'"
o
"0
Symbol
INTERNAL ARCHITECTURE SYMBOLS
INSTRUCTION OPERAND SYMBOLS
A
8
8r
8d
C
d
r
o
EN
G
IL
IN
L
M
P
PC
Q
SA
S8
SC
SID
SK
~
oN
TABLE II. COP402/COP402M Instruction Set Table Symbols
Definition
Symbol
Definition
3:
4-bit Operand Field, 0-15 binary (RAM Digit Select)
2-bit Operand Field, 0-3 binary (RAM Register
Select)
a
9-bit Operand Field, 0-511 binary (ROM Address)
y
4-bit Operand Field, 0-15 binary (Immediate Data)
RAM(s) Contents of RAM location addressed by s
ROM(t) Contents of ROM location addressed byt
4-bit Accumulator
6-bit RAM Address Register
Upper 2 bits of 8 (register address)
Lower 4 bits of 8 (digit address)
1-bit Carry Register
4-bit Data Output Port
4-bit Enable Register
4-bit Register to latch data for G liD Port
Two 1-bit Latches Associated with the IN3 or
INo inputs
4-bit Input port
8-bitTRI-STATE liD Port
4-bit contents of RAM Memory pointed to by 8
Register
2-bit ROM Address Port
10-bit ROM Address Register (program counter)
8-bit Register to latch data for L liD Port
1O-bit Subroutine Save Register A
1O-bit Subroutine Save Register 8
1O-bit Subroutine Save Register C
4-bit Shift Register and Counter
Logic-Controlled Clock Output
OPERATIONAL SYMBOLS
+
A
Ell
Plus
Minus
Replaces
Is exchanged with
Is equal to
The one's complement of A
Exclusive-OR
Range of values
TABLE III. COP402/COP402M Instruction Set
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Description
Skip Conditions
ARITHMETIC INSTRUCTIONS
A + C + RAM(8) --. A
Carry --. C
Carry
Add with Carry, Skip on
Carry
A + RAM(8) --. A
None
Add RAM toA
10100110101
A + 1010 --. A
None
Add Ten to A
5-
10101 1 y
A+y--.A
Carry
Add Immediate, Skip on
Carry (y =1= 0)
CASC
10
10001100001
A + RAM(8) + C --. A
Carry --. C
Carry
Complement and Add with
Carry, Skip on Carry
CLRA
00
10000100001
O--'A
None
Clear A
COMP
40
10100100001
A--'A
None
One's complement of A to A
NOP
44
10100101001
None
None
No Operation
RC
32
10011100101
"0" --. C
None
ResetC
SC
22
10010100101
"1" --. C
None
SetC
XOR
02
10000100101
A Ell RAM(8) --. A
None
Exclusive-OR RAM with A
ASC
30
10011100001
ADD
31
1001110001
ADT
4A
AISC
Y
I
I
1-265
:E
C'i
o
~
Instruction Set (Continued)
ID..
o
TABLE III. COP402/COP402M Instruction Set (Continued)
o
......
C'i
o
Mnemonic Operand
~oe:e
~
ID..
o
o
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
TRANSFER OF CONTROL INSTRUCTIONS
JIO
FF
JMP
a
JP
a
a
JSR
a
I
ROM (PC9:e, A,M) ~
PC7:0
None
Jump Indirect (Note 3)
6-
10110 I00 Ia9"al a ~ PC
I aZ"Q I
None
Jump
--
11 I a!2"O
I a ~ PC6:0
(pages 2,3 only)
or
1111
a5"Q
I a ~ PCs:o
(all other pages)
None
Jump within Page
(Note 4)
None
Jump to Subroutine Page
(Note 5)
---
JSRP
1111111111
--
110 1
6-
10110110 Ia9"a I PC + 1 ~ SA ~ SB ~ SC None
I aZ"Q I a ~ PC
--
I
a5"Q
PC+ 1 ~ SA ~
SB ~ SC
0010 ~ PC9:6
a ~ PCs:o
Jump to Subroutine
RET
48
I0100 11000 I
SC
~
SB
~
SA
~
PC
None
RETSK
49
10100110011
SC
~
SB
~
SA
~
PC
Always Skip on Return Return from Subroutine
then Skip
Return from Subroutine
MEMORY REFERENCE INSTRUCTIONS
CAMO
33
3C
1001110011 I
10011111001
A ~ 07:4
RAM (B) ~ 03:0
None
Copy A, RAM to 0
COMA
33
2C
1001110011 I
10010 11100 I
07:4 ~ RAM(B)
None
Copy 0 to RAM, A
03:0~A
-5
100 Irl01011
RAM (B) ~ A
Br ED r ~ Br
None
Load RAM into A,
Exclusive-OR Br with r
23
1001010011
1001 r I d
RAM(r,d)
None
Load A with RAM pointed
to directly by r,d
BF
I
I
11011 11111 I
ROM(PC9:e,A,M) ~ 0
SB ~ SC
None
Load 0 Indirect
(Note 3)
LO
r
LOO
r,d
-LOID
~
A
RMB
0
1
2
3
4C
45
42
43
1010011100 I
1010010101 I
10100100101
1010010011 I
o~
o~
o~
o~
RAM(B)o
RAM(B)1
RAM(B)2
RAM(Bh
None
Reset RAM Bit
5MB
0
1
2
3
40
47
46
4B
1010011101 I
1010010111 I
10100101101
1010011011 I
1 ~ RAM(B)o
1 ~ RAM(B)1
1 ~ RAM(B)2
1 ~ RAM(Bh
None
Set RAM Bit
STII
y
7-
10111 1 y
I
y ~ RAM (B)
Bd + 1 ~ Bd
None
Store Memory Immediate
and Increment Bd
X
r
-6
100 Ir I0110 I
RAM (B) +-+ A
Br ED r ~ Br
None
Exchange RAM with A,
Exclusive-OR Br with r
XAD
r,d
23
1001010011
110 1 r I d
RAM(r,d) +-+ A
None
Exchange A with RAM
pointed to directly by r,d
--
I
I
1-266
o
o
Instruction Set (Continued)
"'0
~
o
N
.......
TABLE III. COP402/COP402M Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
o
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
~
XDS
r
-7
100 1r 10111 1
RAM(B) ~ A
Bd - 1 --. Bd
Br EB r --. Br
Bd decrements past 0
Exchange RAM with A
and Decrement Bd,
Exclusive-OR Br with r
XIS
r
-4
100 1r 10100 1
RAM (B) ~ A
Bd + 1 --. Bd
Br EB r --. Br
Bd increments past 15
Exchange RAM with A
and Increment Bd,
Exclusive-OR Br with r
REGISTER REFERENCE INSTRUCTIONS
CAB
50
10101100001
A --. Bd
None
Copy A toBd
CBA
4E
10100111101
Bd --. A
None
CopyBd toA
1001rl(d -1)1
(d=O, 9:15)
or
10011100111
110 1 r 1 d 1
(any d)
r,d --. B
Skip until not a LBI
Load B Immediate with
r,d (Note 6)
33
6-
10011 10011 1
10110 1 y I
y --. EN
None
Load EN Immediate
(Note 7)
12
10001100101
A ~ Br (0,0 --. A3.A2)
None
Exchange A with Br
SKC
20
10010100001
C = "1"
Skip if C is True
SKE
21
10010100011
A = RAM (B)
Skip if A Equals RAM
SKGZ
33
21
10011100111
10010100011
G3:0 = 0
Skip if G is Zero
(all 4 bits)
0
1
2
3
33
01
11
03
13
10011100111
10000100011
10001100011
10000100111
10001100111
0
1
2
3
01
11
03
13
10000100011
10001100011
10000100111
10001100111
RAM(B)o
RAM(Bh
RAM(B)2
RAM(Bb
41
10100100011
A time-base counter
r,d
-33
-LEI
y
XABR
TEST INSTRUCTIONS
SKGBZ
SKMBZ
SKT
o
3:
N
MEMORY REFERENCE INSTRUCTIONS (Continued)
LBI
o"'0
1st byte
} 2nd byte
Skip if G Bit is Zero
Go
G1
G2
G3
=
=
=
=
0
0
0
0
=
=
=
=
0
0
0
0
carry has occurred
since last test
1-267
Skip if RAM Bit is Zero
Skip on Timer (Note 3)
::E
C\I
C)
oe::t'
Instruction Set (Continued)
a-
TABLE III. COP402/COP402M Instruction Set (Continued)
0
(,)
......
C\I
C)
Mnemonic
Operand
oe::t'
Hex
Code
a-
0
(,)
Machine
Language Code
(Binary)
DataFlow
Skip Conditions
Description
INPUT/OUTPUT INSTRUCTIONS
ING
33
2A
10011100111
10010110101
G ...... A
None
Input G Ports to A
ININ
33
28
10011100111
10010110001
IN ...... A
None
Input IN Inputs to A
(Notes 2 and 8)
INIL
33
29
10011100111
10010110011
ILs, "0", ILo ...... A
None
Input IL Latches to A
(Note 3)
INL
33
2E
10011100111
10010111101
L7:4 ...... RAM (B)
Ls:o ...... A
None
Input L Ports to RAM,A
08D
33
3E
10011100111
10011111101
8d ...... D
None
Output 8d to D Outputs
33
10011100111
10101 1 ~ 1
y ...... G
None
Output to G Ports Immediate
5OMG
33
3A
1001110011 I
10011110101
RAM(8) ...... G
None
Output RAM to G Ports
XAS
4F
10100111111
A
None
Exchange A with SIO
(Note 3)
OGI
y
~
SIO,C ...... SKL
Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to N where
o signifies the least significant bit (low-order, right-most bit). For example, A3 Indicates the most significant (left-most) bit of the 4-bit register.
Note 2: The ININ instruction is not available on the 24-pin COP421 since this device does not contain the IN inputs.
Note 3: For additional information on the operation of the XAS, JID, LaiD, INIL, and SKT instructions, see below.
Note 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP Instruction,
otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Note 5: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of Pl. A JSRP may not be used when in pages 2 or 3. JSRP
may not jump to the last word in page 2.
Note 6: LBlls a single-byte instruction if d = 0,9,10,11,12,13,14, or 15. The machine code for the lower 4 bits equals the binary value of the "d" data minus 1,
e.g., to load the lower four bits of B (Bd) with the value 9 (10012), the lower 4 bits of the LBllnstructlon equal 8 (10002). To load 0, the lower 4 bits of the LBI
Instruction should equal 15 (11112).
Note 7: Machine code for operand field y for LEI instruction should equal the binary value to be latched Into EN, where a "1" or "0" in each bit of EN corresponds
with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
Note 8: The COP402M will always read a "l"lnto A1 with the ININ instruction.
1·268
o
o"'0
Description of Selected
Instructions
0l:Io
The following information is provided to assist the user in
understanding the operation of several unique instructions
and to provide notes useful to programmers in writing programs.
LaID INSTRUCTION
LaiD (Load a Indirect) loads the 8-bit a register with the
contents of ROM pointed to by the 1O-bit word PCg, PCa, A,
M. LaiD can be used for table lookup or code conversion
such as BCD to seven-segment. The LaiD instruction
"pushes" the stack (PC + 1 -+ SA -+ SB -+ SC) and
replaces the least significant 8 bits of PC as follows: A -+
PC7:4, RAM (B) -+ PC3:0, leaving PCg and PCa unchanged. The ROM data pointed to by the new address is
fetched and loaded into the a latches. Next, the stack is
"popped" (SC -+ SB -+ SA -+ PC), restoring the
saved value of PC to continue sequential program execution. Since LaiD pushes SB -+ SC, the previous contents
of SC are lost. Also, when LaiD pops the stack, the previously pushed contents of SB are left in SC. The net result is
that the contents of SB are placed in SC (SB -+ SC). Note
that LaiD takes two instruction cycle times to execute.
XAS INSTRUCTION
XAS (Exchange A with SIO) exchanges the 4-bit contents of
the accumulator with the 4-bit contents of the SIO register.
The contents of SIO will contain serial-in/serial-out shift register or binary counter data, depending on the value of the
EN register. An XAS instruction will also affect the SK output. (See Functional Description, EN Register, above.) If
SIO is selected as a shift register, an XAS instruction must
be performed once evey 4 instruction cycles to effect a continuous data stream.
JID INSTRUCTION
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location pointed
to indirectly by A and M. It loads the lower 8 bits of the ROM
address register PC with the contents of ROM addressed by
the 10-bit word, PCg:a, A, M. PCg and PCa are not affected
by this instruction.
SKT INSTRUCTION
The SKT (Skip on Timer) instruction tests the state of an
internal 10-bit time-base counter. This counter divides the
instruction cycle clock frequency by 1024 and provides a
latched indication of counter overflow. The SKT instruction
tests this latch, executing the next program instruction if the
latch is not set. If the latch has been set since the previous
test, the next program instruction is skipped and the latch is
reset. The features associated with this instruction, therefore, allow the controller to generate its own time-base for
real-time processing rather than relying on an external input
signal.
For example, using a 2.097 MHz crystal as the time-base to
the clock generator, the instruction cycle clock frequency
will be 131 kHz (crystal frequency -;- 16) and the binary
counter output pulse frequency will be 128 Hz. For time-ofday or similar real-time processing, the SKT instruction can
call a routine which increments a "seconds" counter every
128 ticks.
Note that JID requires 2 instruction cycles.
INIL INSTRUCTION
INIL (Input IL Latches to A) inputs 2 latches, IL3 and 11.0 (see
Figure 12) and CKO into A. The IL3 and 11.0 latches are set if
a low-going pulse ("1" to "0") has occurred on the IN3 and
INo inputs since the last INIL instruction, provided the input
pulse stays low for at least two instruction times. Execution
of an INIL inputs IL3 and INo into A3 and AO respectively,
and resets these latches to allow them to respond to subsequent low-going pulses on the IN3 and INo lines. If CKO is
mask programmed as a general purpose input, an INIL will
input the state of CKO into A2. If CKO has not been so
programmed, a "1" will be placed in A2. A "0" is always
placed in A 1 upon the execution of an INIL. The general
purpose inputs IN3-INo are input to A upon the execution of
an ININ instruction. (See Table III, ININ instruction.) INIL is
useful in recognizing pulses of short duration or pulses
which occur too often to be read conveniently by an ININ
instruction.
INSTRUCTION SET NOTES
a. The first word of a program (ROM address 0) must be a
CLRA (Clear A) instruction.
b. Although skipped instructions are not executed, one instruction cycle time is devoted to skipping each byte of
the skipped instruction. Thus all program paths take the
same number of cycle times whether instructions are
skipped or executed, except JID and LaiD. LaiD and JID
take two cycle times if executed and one if skipped.
CDP420
ININ
1.
INo/lNa
c. The ROM is organized into 16 pages of 64 words each.
The Program Counter is a 10-bit bil'1ary counter, and will
count through page boundaries. If a JP, JSRP, JID or
LaiD instruction is located in the last word of a page, the
instruction operates as if it were in the next page. For
example: a JP located in the last word of a page will jump
to a location in the next page. Also, a LaiD or JID located
in the last word of page 3, 7, 11, or 15 will access data in
the next group of 4 pages.
INIL
TL/DD/6915-19
FIGURE 12. INoIIN3 Latches
1-269
o
N
......
o
o"'0
0l:Io
o
N
3:
::E
~
Typical Application: PROM-Based System
D.
The COP402 may be used to exactly emulate the COP420,
Figure 13 shows the interconnect to implement a COP420
hardware emulation. This connection uses two MM5204
EPROMs as external memory. Other memory can be used
such as bipolar PROM or RAM.
Pins IP7-IPO are bidirectional inputs and outputs. When the
AD/DATA clocking output turns on, the EPROM drivers are
disabled and IP7-IPO output addresses. The 8·bit latch
(MM74C373) latches the addresses to drive the memory.
8
~
o
:.
o
o
Vee
24
Lll
GNO
12
When AD/DATA turns off, the EPROMs are enabled and
the IP7·IPO pins will input the memory data. P8 and P9 out·
put the most significant address bits to the memory. (SKIP
output may be used for program debug if needed.)
The other 28 pins of the COP402 may be configured exactly
the same as a COP420. The COP402M chip can be used if
the MICROBUS feature of the COP420 is needed.
Vee
vpp
GNO
23
1
2
3
4
5
B
7
Vee
AI
A7
MM2758
A6
OR Y, OF
AID .!!..... GNO
MM2716
A5
A4
A3
22
A2
A9
AI
DE ~
a ~
AD
19 II 15 12 9 B I 5 r
07 DB 05 04 03 02 01 DO
20 Q8 Q7 QI Q5 Q4 Q3 Q2 Ql
Vee
17 lB 15 14 13 11 10 9
GNO
DM74LS373
[l
OUTPUT DIS
08 07 DB 05 04 03 02 01
18 17 14 13 8 7 14 13
n
~-tI
35
~
22
9 10 36 3
5
7
6
8
33 34
IP7 IP6 IPS 1P4 IP3 IP2 IPI IPO AD/DATA P9
PI
SKIP
1
2
4
11
40
39
38
37
31
eOP402
.!L-
--l!
13
COP420
PINOUT
-
f GNO CKO CKIRESET L7 L6
\123466
L5
14
15
16
17
18
L4 INI IN2 VCC L3
8
9 10 11 12
19
L2
13
20
Ll
14
21
LO SI
15 lB
23
24
SO
17
25
2B
27
-
21
SK INO IN3 GO
18 19 20 21
Gl
22
29
G2
23
G3 03
2426
02
28
01
27
DO
21
TL/DD/6915-20
FIGURE 13. COP402 Used to Emulate a COP420
1·270
o
Option List
o"'U
COP402 MASK OPTIONS
N
0l=Io
o
The following COP420 options have been implemented in this basic version of the COP402. Subsequent versions of the
COP402 will implement different combinations of available options; such versions will be identified as COP402-A, COP402-B,
etc.
Option Value
Comment
Option Value
Comment
Option 1 = 0
Option 15 = 2,3
LO same as L7
Ground Pin-no option available
Option 2 = 0
CKO is clock generator output to
Option 16 = 0
SI has load device to Vee
crystal
Option 17 = 2
SO has push-pull output
Option 3 = 0
CKI is crystal input + 16
Option 18 = 2
SK has push-pull output
(may be overridden externally)
Option 19 = 0
INO has load device to Vee
Option 4 = 0
RESET pin has load device to Vee
Option 20 = 0 (402) IN3 has load device to Vee
Option 5 = 2 (402) L7 has LED direct-drive output
= 1 (402M) Hi Z
= 3 (402M) L7 has TRI-STATE push-pull output
Option 21 = 0
GO has standard output
Option 6 = 2, 3
L6 same as L7
G1 same as GO
Option 22 = 0
Option 7 = 2,3
L5 same as L7
Option 23 = 0
G2 same as GO
Option 8 = 2,3
L4 same as L7
G3 same as GO
Option 24 = 0
Option 9 = 0 (402) IN1 has load device to Vee
03 has standard output
Option 25 = 0
= 1 (402M) Hi Z
Option 26 = 0
02 same as 03
Option 10 = 0 (402) IN2 has load device to Vee
27
=
0
01 same as 03
Option
= 1 (402M) Hi Z
Option 28 = 0
DO same as 03
Option 11 = 0
Vee pin-no option available
Option 29 = 0 (402) normal operation
Option 12 = 2,3
L3 same as L7
= 1 (402M) MICROBUS operation
Option 13 = 2,3
L2 same as L7
Option 30 = N/A
40-pin package
Option 14 = 2,3
L1 same as L7
o
'"
o
"'U
0l=Io
o
N
3:
•
1-271
~
o
~ ~National
o ~ Semiconductor
COP404 ROMless N-Channel Microcontroller
General Description
Features
The COP404 ROM less N-Channel Microcontrollers are
members of the COPSTM family, fabricated using N-channel, silicon gate MOS technology. Each microcontroller contains all system timing, internal logic, RAM and 1/0 necessary to implement dedicated control functions in a variety of
applications, and is identical to the COP440/COP340 devices, except that the ROM has been removed; pins have been
added to output the ROM address and to input ROM data.
In a system, the COP404 will perform exactly as the
COP440; this important benefit facilitates development and
debug of a COP440 program prior to masking the final part.
Features include single supply operation, various output
configurations, and an instruction set, internal architecture,
and 1/0 scheme designed to facilitate keyboard input, display output and data manipulation. Standard test procedures and reliable high-density fabrication techniques provide the medium to large volume customers with a controller-oriented processor at a low end-product cost.
•
•
•
•
•
•
•
•
For extended temperature range ( - 40°C to
COP304 available on special order.
+ 85°C)
•
•
•
•
•
•
•
•
•
Exact circuit equivalent of COP440
Standard 48-pin dual-in-line package
Interfaces with standard PROM or ROM
Enhanced, more powerful instruction set
160 x 4 RAM, addresses up to 2k x 8 ROM
MICROBUSTM compatible
Zero-crossing detect circuitry with hysteresis
True multi-vectored interrupt from four selectable sources (plus restart)
Four-level subroutine stack (in RAM)
4 ,..,S cycle time
Single supply operation (4.5V-6.3V)
Programmable time-base counter for real-time processing
Internal binary counterlregister with MICROWIRETM
compatible serial 1/0
General purpose and TRI-STATE® outputs
TTL/CMOS compatible in and out
Softwarelhardware compatible with other members of
COP400 family
Compatible dual CPU device available
Block Diagram
VCC
GND
AD/DATA
DCK
CKI
..--------+......:.::.... ::\ MICROWIRE I/O
51
IN3-E..·~I-""'~-+
IN2-1!!...+-....~-i--+
I N 1 - - . . ! ! . . + - - - i - -....
INO....1l.I---4--_ •
M8
24
TL/OO/6916-1
FIGURE 1
1-272
o
o
Absolute Maximum Ratings
""C
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage at Zero-Crossing Detect Pin
Relative to GND
- 1.2V to + 15V
Voltage at Any Other Pin Relative to GND
-0.5Vto +7V
Ambient Operating Temperature
Ambient Storage Temperature
Power Dissipation
Total Source Current
.c:-.
o
.c:-.
150mA
Total Sink Current
90mA
Absolute Maximum Ratings indicate limits beyond which
damage to the device may occur. DC and AC electrical
specifications are not ensured when operating the device at
absolute maximum ratings.
O°Cto +70°C
- 65°C to + 150°C
Lead Temperature (Soldering, 10 sec.)
0.75W at 25°C
O.4W at 70°C
300°C
DC Electrical Characteristics O°C $; T A$;+ 70°C, 4.5V $; Vee $; 6.3V unless otherwise noted
Parameter
Min
Max
Units
4.5
6.3
V
(Peak to Peak)
0.4
V
(All Inputs and Outputs Open)
TA = O°C
TA = 25°C
TA = 70°C
44
37
30
mA
mA
mA
3
mA
2.5
2.0
-0.3
0.4
V
V
V
0.7 Vee
-0.3
0.6
V
V
Conditions
Operating Voltage (Vee)
(Note 4)
Power Supply Ripple
Operating Supply Current
VA RAM Power Supply Current
Input Voltage Levels
CKllnput Levels ( -;- 16)
Logic High (VIH)
Logic High (VIH)
Logic Low (VIU
RESET Input Levels
Logic High
Logic Low
Zero-Crossing Detect Input (IN1)
Trip Point
Logic High (VIH) Limit
Logic Low (VIU Limit
IN1
Logic High
Logic Low
All Other Inputs
Logic High
Logic High
Logic Low
VA
=
Vee
Vee
3.3V
=
=
Max.,
5V±5%
(Schmitt Trigger Input)
Zero-Crossing Interrupt
Input; INIL Instruction
-0.15
-0.8
Interrupt Input;
ININ Instruction;
MICROBUS Input
Vee
Vee
IN1 Input Resistance to Ground
VIH
Input Load Source Current
VIH
=
=
=
=
Max.
5V ±5%
1.0V
2.0V, Vee
=
4.5V
V
V
2.5
2.0
-0.3
0.8
V
V
V
1.5
4.6
k!l
14
230
/-LA
-1.0
Hi-Z Input Leakage
Output Current Levels
Standard Output Source Current
TRI-STATE Output Leakage Current
IOH
IOL
=
=
-100/-LA
1.6mA
2.4
IOH
IOL
=
=
-10/-LA
10 /-LA
Vee - 0.4
IOH =
IOL =
33 k!l
IOH =
IOL =
Vee
=
-100/-LA
1.6mA
~ RL ~ 4.7 k!l
-10/-LA
1.6 mA
4.5V, VOH
1-273
=
2.4V
V
V
V
0.8
3.0
-0.3
Input Capacitance
Output Voltage Levels
Standard Output
TTL Operation
Logic High (VOH)
Logic Low (VOU
CMOS Operation (Note 1)
Logic High (VOH)
Logic Low (VOU
TRI-STATE Output
TTL Operation
Logic High (VOH)
Logic Low (VOU
CMOS Operation (Note 1)
Logic High (VOH)
Logic Low (VOU
0.15
12
7.0
pF
+1.0
/-LA
0.4
V
V
0.2
V
V
0.4
V
V
0.4
V
V
-650
+2.5
/-LA
/-LA
2.4
Vee - 0.5
-100
-2.5
III
~
o
~
D.
oo
DC Electrical Characteristics O°C : : ; TA ::::;; + 70°C, 4.5V ::::;; Vee::::;; 6.3V unless otherwise noted (Continued)
Parameter
Conditions
Min
Max
Units
90
20
10
2.5
1.8
rnA
rnA
rnA
rnA
rnA
150
120
70
70
23
1.6
rnA
rnA
rnA
rnA
rnA
rnA
Total Sink Current Allowed
All I/O Combined
Each L, R Port
Each D, G, H Port
SO,SK
IP
Note
Total Source Current Allowed
All I/O Combined
L Port
L7-4
Ls-Lo
Each L Pin
All Other Output Pins
1: TRI·STATE configuration is excluded.
(Note 5)
AC Electrical Characteristics O°C ~ TA : : ; + 70°C, 4.5V ::::;; Vee::::;; 6.3V unless otherwise noted
Parameter
Conditions
Instruction Cycle Time-tE
CKI Frequency
Duty Cycle (Note 2)
Rise Time
Fall Time
INPUTS: (Figure 3)
SI
tSETUP
tHOLO
IP
tSETUP
tHOLO
tHOLO
All Other Inputs
tSETUP
tHOLO
OUTPUT PROPAGATION DELAY
IP
tpd1A, tpdOA
tpd1 B, tpdOB
DCK
-:- 16 Mode
f, = 4 MHz
f, = 4MHz
f, = 4 MHz
From AD/DATA Rising Edge
Test Condition:
CL = 50 pF, VOUT
=
= 2.4kO
= 5.0kO
CL = 100 pF, Vee = 5V±5%
RL
RL
Max
4.0
10
Units
/Ls
1.6
30
4.0
60
60
40
MHz
%
ns
ns
0.3
300
/Ls
ns
0.25
250
0
/Ls
ns
ns
1.7
300
/Ls
ns
1.5V
tp~o
AD/DA A
t pd1, tpdO
SO,SK
t lld1, tpdO
All Other Outputs
Min
1.94
0.94
/Ls
/Ls
375
ns
300
ns
1.0
1.4
/Ls
/Ls
MICROBUS TIMING
Read Operation
TRI-STATE outputs
65
ns
Chip Select Stable Before RD-tcSR
Chip Select Hold Time for RD-tRes
20
ns
ns
400
RD Pulse Width-=!BR
375
ns
Data Delay from RD-tRO
RD to Data Floating-toF
250
ns
Write Operation
65
ns
Chip Select Stable Before WR-tesw
20
ns
Chip Select Hold Time for WR-twes
WR Pulse Width-t~
400
ns
320
Data Set-Up Time for WR-tow
ns
Data Hold Time for WR-tWIL
100
ns
INTR Transition Time from WR-tWI
700
ns
Note 2: Duty Cycle = tWI/(twl + two).
Note 3: See Figure for additional I/O Characteristics.
Note 4: Vee voltage change must be less than O.5V in a 1 ms period to maintain proper operation.
Note 5: Exercise great care not to exceed maximum device power dissipation limits when direct-driving LEOs (or sourcing similar loads) at high temperature.
1-274
o
Connection Diagram
o
Pin Descriptions
Pin
Dual-In-Llne Package
L7-Lo
"c
~
Description
8-bit bidirectional TRI-STATE I/O port
IP1
IPZ
G3-GO
4-bit bidirectional I/O port
IPo
IPJ
IN3-INo
4-bit general purpose input port
VRAM
CKI
CKOI
IP4
IPS
IPS
H3- HO
4-bit bidirectional I/O port.
8-bit bidirectional TRI-STATE I/O port
1P7
RESET
RfRo
SI
Serial input
SO
Serial output (or general purpose output)
SK
Logic-controlled clock (or general purpose output)
System oscillator input
R7
RS
R5
R4
AD/DATA
DCK
Ra
H1
R2
R1
RO
L7
HO
CKOI
General purpose input
Ga
G2
G1
Go
VRAM
Power supply to first 4 registers of RAM
MB
MICROBUS function select
Ha
HZ
l&
CKI
Clock output to latch D outputs and high order
address bits
AD/DATA Address out/data in flag
DCK
INa
INO
L5
l4
SK
SO
IN1
INZ
VCC
La
L2
SI
GND
La
Mi
~
L1
IP1-IPO
8-bit bidirectional port for ROM address, ROM
data and D outputs
RESET
System reset input
Vee
Power Supply
GND
Ground
TLlDD/6916-2
Top View
FIGURE 2
Order Number COP404N
See NS Package Number N48A
Timing Diagram
I'
INSTRUCTION CYCLE TIME (te) ~
•
TL/DD/6916-3
FIGURE 3. Input/Output Timing Diagrams (+ 16 Mode)
1-275
~
o
~
a..
oo
r-------------------------------------------------------------------------------------------,
Functional Description
The COP404 is a ROM less microcontroller for emulating the
COP440 or for stand-alone applications. Please refer to the
COP440 description for detail functional description. The
following describes functions that are unique to the COP404
or are different from those in COP440. Figures 1 and 2 show
the COP404 block diagram and pin-out.
Figure 3 shows the timings for IP port and the external
memory interface clocks-DCK and AD/DATA. While DCK
is low, the upper three address bits, P10-P8, of the next
instruction to be executed appear at IP2-IPO respectively;
D3-DO appear at IP7-IP4 and IP3 contains the SKIP output
used by the COPS Program Development System (PDS).
The rising edge of DCK clocks these data into D flip-flops,
e.g., 74LS374. The timing of D port data is then the same
for COP404 and COP440. After DCK has risen to a "1"
level, the remaining address bits (P7-PO) appear at IP7-IPO.
The falling edge of AD/DATA latches these data into flowthrough latches, e.g., 74LS373. The latched addresses provide the inputs to the external memory. When AD/DATA
goes low, the IP outputs are disabled and the IP lines become program memory inputs from the external memory.
Note that DCK has a duty cycle of about 50% and
AD/DATA has a duty cycle of about 75%. Figure 4 shows
how to emulate the COP440 using a COP404 and an EPROM as the external memory.
PROGRAM MEMORY
Program memory consists of 2048 bytes of external memory (on-chip in theCOP440) that can be accessed through
the IP port. See External Memory Interface below.
DPORT
The D3-DO outputs are missing from this 48-pin package,
but may be recovered through the IP port (see External
Memory Interface below). Note that the recovered signals
have the same timing but different output drive capability as
those from the COP440 (see D Port Characteristics below).
MICROBUS AND ZERO-CROSSING DETECT INPUT OPTION
I!OOPTIONS
All inputs except IN1 and CKI have on-chip depletion load
devices to Vee. IN1 has a resistive load to GND due to the
zero-crossing input. CKI is a Hi-Z input.
The MICROBUS compatible I/O, selected by a mask option
on the COP440, is selected by tying the MB pin directly to
ground. When the MICROBUS compatible I/O is not desired, the MB pin should be tied to Vee. Note that none of
the IN inputs are Hi-Z. Since zero-crossing detect input
(used by INIL instruction and zero-crossing interrupt feature)
is chosen for IN1, the IN1 input "1" level for ININ instruction, IN1 interrupt, and MICROBUS input is 3V. Even though
the MICROBUS option and zero-crossing detector option
appear on the COP404, they are mutually exclusive on the
COP440.
G and H ports have standard outputs. Land R ports have
TRI-STATE outputs. IP port, DCK, AD/DATA, SO and SK
have push-pull outputs.
LED DRIVE
The TRI-STATE outputs of L port may be used to drive the
segments of an LED display. External current limiting resistors of 100f! must be connected between the L outputs and
the LED segments.
OSCILLATOR
CKI is an external clock input signal. The clock frequency is
divided by 16 to give the execution frequency.
o PORT CHARACTERISTICS
Since the D port is recovered through an external latch, the
output drive is that of the latch and not that of COP440.
Using the set-up as shown in Figure 4, at an output "0" level
of O.4V, the 74LS374 may sink 10 times as much current as
the COP440. At an output "1" level of 2.4V, the 74LS374
may source 10 times as much current as the COP440. On
the other hand, the output "1" level of 74LS374 latch does
not go to Vee without an external pull-up resistor. In order to
better approximate the COP440 output characteristics, add
a 74C906 buffer to the output of the 74LS374, thus emulating an open drain D output. A pull-up resistor of 10k should
be added to the input of the buffer. To emulate the standard
output, add a pull-up resistor between 2.7k and 15k to the
output of the 74C906.
eKO PIN OPTIONS
Two different CKO functions of the COP440 are available
on the COP404. VRAM supplies power to the lower four registers of RAM, and CKOI is an interrupt input or a general
purpose input, reading into bit 2 of A (accumulator) through
the INIL instruction.
EXTERNAL MEMORY INTERFACE
The COP404 is designed for use with an external program
memory. This memory may be implemented using any devices having the following characteristics:
1. Random addressing
2. TTL-compatible TRI-STATE outputs
3. TTL-compatible inputs
4. Access time = 450 ns maximum
Typically these requirements are met using bipolar or MOS
PROMs.
1-276
Functional Description
o
o
(Continued)
"0
0l:Io
o
COP440
PINOUT
20
0l:Io
GNO
19
00
18
01
17
02
16
03
27
GNO
H3 ~
15
IP7
H2 --1!.
IP6
12
HO --1!.
IP4
IP3
14
Hl -1!.
13
IP5
...2!.
-2!.
11
G3
10
G2
9
G1 ~
IPl
8
GO,---ll
IPO
IN3;---B.
OCK
IP2
43
lB
44
17
45
14
46
13
08
07
DB
07
06
06
05
05
8
04 OM74LS374 04
7
03
03
4
02
02
3
01
01
11
CLOCK
00 GNO Vec
47
48
1
2
41
INOl-ll
1
....2!!.
SK
10
J
16
-;s-,;-9
~SKIP
6
19
5
22
2
23
21
20
rt-24
SO1---1!
12
1--1!
LO1--1!
42
L1 ~
1
40
VCC
1
-~
COP404
L2~-~
39
20
AD/IrAn
IN2:-~
37
L4
34
32
L7 -~
4
30
R1
28
-.!!
R2:-..!!.
R31- .!!.
27
R41- .!!.
26
R5i_..!.
25
R6i_~
7
3
R7
23
RESET
24
M!
CKOI
COP440
PINOUT
Vpp
VCC
VSS
fiE
06 OM74LS373 06
05
05
04
04
03
03
02
02
01
01
MM2716
11
18
19
1
16
2
15
3
12
4
9
S
6
6
5
7
2
8
CE
A7
A6
AS
A4
A3
A2
Al
AO
1171''1'
CK I-~
CKO
AB
07 06 05 04 03 02 01 00
14 13 11 10 9
'-~
'-~
24
21
07
B
RO -~
22
07
L5 -~
31
29
08
~t-
13
-~
L6 -~
33
08
14
INl -~
36
35
U
~
17
A9
20
00 GNO VCC
L3I-~
38
10
Al0
VRAM
\rl\o
47kQ
"""
6
MICROBUS FUNCTION OPTION SELECT
Vcc
GNO
CKO FUNCTION
OPTION SELECT
TL/OO/6916-4
FIGURE 4. COP404 Used to Emulate a COP440
1-277
~
Q
~
8
Option Table
COP404 MASK OPTIONS
The following COP440 options have been implemented in the COP404.
Option Value
Option 1-2
Option 3
Option 4
Option 5
Option 6
Option 7
Option 8-11
Option 12-15
Option 16-19
Option 20
Option 21
= 3
=0
=2
=2
=0
Comment
Option Value
L outputs are TRI·STATE
SI has load to Vee
SO is push·pull output
Option 22
Option 23
Option 24-31
Option 32-35
Option 36
SK is push·pull output
= 0
=0
=3
=3
=2
=0
Option 37
Option 38-39 =3
Option 40
= NtA
Option 41
= 0,1
Option 42-48 = 0
Option 49
= Nt A
Option 50
= Nt A
INO has load to Vee
=0
IN3 has load to Vee
=0
G outputs are standard
=0
H outputs are standard
= Nt A D outputs are derived from external
latch, see Figure 4
= Nt A GND-No option
= 1,2 CKO is replaced by VRAM and CKOI
1·278
Comment
CKI is input clock divided by 16
RESET has load to Vee
R outputs are TRI·STATE
L outputs are TRI·STATE
IN1 is zero·crossing detect input
IN2 has load to Vee
L outputs are TRI·STATE
Vee-No option available
MICROBUS option is pin selectable
Inputs have standard TTL levels
No option available
48·pin package
~National
~ Semiconductor
COP404C ROM less CMOS Microcontrollers
General Description
Features
The COP404C ROM less Microcontroller is a member of the
COPSTM family, fabricated using double-poly, silicon gate
CMOS (microCMOS) technology. The COP404C contains
CPU, RAM, I/O and is identical to a COP444C device except the ROM has been removed and pins have been added to output the ROM address and to input the ROM data.
The COP404C can be configured, by means of external
pins, to function as a COP444C, a COP424C, or a
COP410C. Pins have been added to allow the user to select
the various functional options that are available on the family of mask-programmed CMOS parts. The COP404C is primarily intended for use in the development and debug of a
COP program for the COP444C/445C, COP424C/425C,
and COP41 OC/ 411 C devices prior to masking the final part.
The COP404C is also appropriate in low volume applications or when the program might be changing.
• Accurate emulation of the COP444C, COP424C and
COP410C
• Lowest Power Dissipation (50 p,W typical)
• Fully static (can turn off the clock)
• Power saving IDLE state and HALT mode
• 4 p,s instruction time, plus software selectable clocks
• 128 x 4 RAM, addresses 2k x 8 ROM
• True vectored interrupt, plus restart
• Three-level subroutine stack
• Single supply operation (2.4V to 5.5V)
• Programmable read/write 8-bit timer/event counter
• Internal binary counter register with MICROWIRETM
serial I/O capability
• General purpose and TRI-STATE@ outputs
• LSTTLICMOS compatible
• MICROBUSTM compatible
• Software/hardware compatible with other members of
the COP400 family
Block Diagram
Vee
TIiI
UNU
CKI
AD/Dfl
tiUAr
ClGtt
I~U
I"
In
In
1~4
I"IPI
In
ft.
ftl
ftlD
PIP
U3
DZ
Dl
DO
U
II
11
eo
312111130
ClOI
*3 IN2 INI INO
15
L7
I.
LI
17
LI
I'
LI
22
U
Z3
L2
24
Ll
Z5
La
FIGURE 1. Block Diagram
1-279
TL/OO/5530-1
o
-.:r
o
Absolute Maximum Ratings
D.
Supply Voltage
o
Voltage at any pin
-.:r
o
Operating temperature range
6V
Storage temperature range
- 0.3V to Vee + 0.3V
Total Allowable Source Current
25mA
Total Allowable Sink Current
25mA
DC Electrical Characteristics
Parameter
Operating Voltage
Power Supply Ripple
(Note 5)
Supply Current
(Note 1)
HALT Mode Current
(Note 2)
Lead temperature (soldering, 10 sec.)
0°C~Ta~70°C
Min
Max
Units
2.4
5.5
0.1 Vee
V
V
120
700
3000
iJ-A
iJ- A
20
6
iJ-A
iJ-A
0.1 Vee
V
V
0.2 Vee
V
V
30
330
iJ-A
-1
+1
iJ-A
7
pF
0.4
V
V
0.2
V
V
peak to peak
Vee=2.4V, t c =64iJ-s
Vee=5.0V, t c =16iJ-s
Vee=5.0V, tc=4iJ-s
(Tc is instruction cycle time)
Vee=5.0V, FIN=O kHz, TA=25°C
Vee=2.4V, FIN=O kHz, TA=25°C
0.9 Vee
0.7 Vee
Vee=4.5V, VIN=O
Hi-Z input leakage
Input capacitance
(Note 4)
Output Voltage Levels
LSTTL Operation
Logic High
Logic Low
CMOS Operation
Logic High
Logic Low
Output current levels
Sink (Note 6)
Source (Standard option)
Source (Low current option)
Standard outputs
Vee=5.0V ±10%
IOH= -100 iJ-A
IOL =400 iJ-A
2.7
Vee- 0.2
IOH= -10 iJ-A
IOL=10 iJ-A
Vee=4.5V, Vour=Vee
Vee=2.4V, Vour=Vee
Vee=4.5V, Vour=OV
Vee=2.4V, Vour=OV
Vee=4.5V, Vour=OV
Vee=2.4V, Vour=OV
1.2
0.2
0.5
0.1
30
6
Allowable Sink/Source current per pin
(Note 6)
Allowable Loading on CKOH
Current needed to over-ride HALT
(Note 3)
To continue
To halt
300°C
unless otherwise specified
Conditions
Input Voltage Levels
RESET, DO (clock input)
CKI
Logic High
Logic Low
All other inputs (Note 7)
Logic High
Logic Low
Input Pull-up
current
0° to +70°C
-65°C to + 150°C
Vee = 4.5V, VIN=2Vee
Vee=4.5V, VIN=7Vee
-2.5
TRI-STATE leakage current
iJ-A
mA
mA
mA
mA
330
80
iJ-A
iJ-A
5
mA
100
pF
.7
1.6
mA
mA
+2.5
iJ-A
Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when
operating the device at absolute maximum ratings.
1-280
o
a"C
COP404C
.1:10
AC Electrical Characteristics
o
.1:10
o
O°C:o; TA:O; 70°C unless otherwise specified
Parameter
Conditions
Min
Max
Units
,...S
Instruction Cycle
Vccz4.5V
4
DC
Time(td
4.5V>Vcc z2.4V
16
DC
,...S
Operating CKI
Vcc z4 .5V
DC
1.0
MHz
Frequency
4.5V>Vcc z2.4V
DC
250
kHz
Duty Cycle (Note 4)
f1=4 MHz
40
60
%
Rise Time (Note 4)
f1 = 4 MHz external clock
60
ns
40
ns
16
,...S
Fall Time (Note 4)
f1 =4 MHz external clock
Instruction Cycle
R=30k, Vcc=5V
Time using DO as a
C=82 pF
8
RC Oscillator DualClock Input (Note 4)
INPUTS: (See Fig. 3)
tSETUP
G Inputs
Sllnput
Vcc z4 .5V
IP Input
All Others
Vcc z4 .5V
4.5V>Vcc z2.4V
1
tHOLO
OUTPUT
PROPAGATION DELAY
IP7-IPO, A10-A8, SKIP
tp01, tpoo
AD/DATA
tp01, tpoo
ALL OTHER OUTPUTS
tp01, tpDo
MICROBUS TIMING
Read Operation (Fig. 4)
Tc/4 +. 7
0.3
1.0
1.7
0.25
1.0
JLS
JLs
JLs
JLs
JLs
JLs
VOUT= 1.5V, CL = 100 pF, RL = 5K
Vcc z4 .5V
4.5V> Vccz 2.4V
1.94
7.75
JLs
JLs
Vcc z4 .5V
4.5V>Vcc z2.4V
375
1.5
ns
JLs
VcC>4.5V
4.5'1> Vccz 2.4V
1.0
4.0
JLs
JLs
CL =50 pF, Vcc=5V±5%
Chip select stable before RD -tCSR
65
Chip select hold time for RD -tRCS
20
ns
ns
RD pulse width -tRR
400
ns
Data delay from RD -tRO
375
ns
RD to data floating -tOF (Note 4)
250
ns
Write Operation (Fig. 5)
Chip select stable before WR -tcsw
65
ns
Chip select hold time for WR - twcs
20
ns
WR pulse width - tww
400
ns
Data set-up time for WR -tow
320
ns
Data hold time for WR -two
100
ns
INTR transition time from WR -tWI
700
ns
Nole 1: Supply current is measured after running for 2000 cycle limes with a square-wave clock on CKI and all other pins pulled up 10 Vee with 20k resistors. See
current drain equation on page 16.
Nole 2: Test conditions: All inputs tied to Vee; L lines in TRI-STATE mode and tied to Ground; all outputs tied to Ground.
Nole 3: When forcing HALT, current is only needed for a short time (approx. 200 ns) to flip the HALT flip-flop.
Nole 4: This parameter is only sampled and not 100% tested. Variation due to the device included.
Note 5: Voltage change must be less than 0.5 volts in a 1 ms period.
Note 6: SO output sink current must be limited to keep VOL less than 0.2 Vee to prevent entering test mode.
Note 7: MB, TIN, DUAL, SEL10, SEL20, input levels at Vee or VSS.
1-281
III
0
"'I:t'
0
"'I:t'
D-
o
Connection Diagram
Pin Descriptions
Dual-In-Llne Package
Pin
0
Vee
Vss
A9
'fiN
iB
CKI
RS
CKOI
LO-L7
GO-G3
01-03
DO
D1
D2
D3
10
11
12
13
14
COP404C
15
16
17
1B
19
20
21
22
23
24
DO
AS
DUAL
AD/DATA
SEL10
SEL20
SKIP
G3
G2
G1
GO
IN3
INO
SK
UNUSED
SO
SI
INO-IN3
SO
SI
SK
IPO-IP7
A8, A9, A10
SKIP
AD/DATA
MB
CKOH
DUAL
TIN
SEL10
SEL20
UNUSED
LO
TOPYIEW
TL/DD/5530-2
Description
Most positive voltage
Ground
Clock input
Reset input
General purpose input
8 TRI-STATE I/O
4 general purpose I/O
3 general purpose outputs
Either general purpose output
or Dual-Clock RC input
4 general purpose inputs
Serial data output
Serial data input
Serial data clock output
I/O for ROM address and data
3 address outputs
Skip status output
Clock output
MICROBUS select input
Halt I/O pin
Dual-Clock select input
Timer input select pin
COP410C emulation select input
COP424C emulation select input
Ground
Order Number COP404CN
See NS Package Number N48A
FIGURE 2
pushes the next PC address into the stack. Each return
pops the stack back into the PC register.
The internal architecture is shown in Figure 1. Data paths
are illustrated in simplified form to depict how the various
logic elements communicate with each other in implementing the instruction set of the device. Positive logic is used.
When a bit is set, it is a logic "1", when a bit is reset, it is a
logic "0".
DATA MEMORY
Data memory consists of a 512-bit RAM, organized as 8
data registers of 16 x 4-bit digits. RAM addressing is implemented by a 7-bit B register whose upper 3 bits (Br) select 1
of 8 data registers and lower 4 bits (Bd) select 1 of 16 4-bit
digits in the selected data register. While the 4-bit contents
of the selected RAM digit (M) are usually loaded into or
from, or exchanged with, the A register (accumulator), it
may also be loaded into or from the Q latches or T counter
or loaded from the L ports. RAM addressing may also be
performed directly by the LDD and XAD instructions based
upon the immediate operand field of these instructions. The
Bd register also serves as a source register for 4-bit data
sent directly to the 0 outputs.
PROGRAM MEMORY
Program Memory consists of a 2048-byte external memory
(typically PROM). Words of this memory may be program
instructions, constants or ROM addressing data.
ROM addressing is accomplished by a 11-bit PC register
which selects one of the 8-bit words contained in ROM. A
new address is loaded into the PC register during each instruction cycle. Unless the instruction is a transfer of control
instruction, the PC register is loaded with the next sequential 11-bit binary count value.
Three levels of subroutine nesting are implemented by a
three level deep stack. Each subroutine call or interrupt
1-282
o
o""D
Timing Diagrams
0I:loo
C)
0I:loo
o
CKI
AD/DATA, SK
(AS A CLOCK) _ ...""",..,
IN3·INO,
CKDI, G3·GO, L7-LO,
SI, 1P7·IPD INPUTS
L7-LO,
SO, SK
G3-GO,
03-00,
OUTPUTS
---:-------:o~..J.~~~~~;-r-----~....;"..,~~
~.-w.l"""
A10-A1, 1P7·IPD, __':'_.J.~~~'~Vo;SKIP OUTPUTS
________
----TL/DD/5530-3
FIGURE 3. Input/Output Timing
(lNZ)
B
(lN1)
Rl!
,
,.
IRR
• -IRCS--4
J
------------t(..,____________-Jli... ICSR-- -IRO-
(L7-LO)
07- 00
-IOF_
TLIDD/5530-4
FIGURE 4. MICROBUS Read Operation Timing
III
tww
I-ICSW-- •
(lNZ)
CS
• -IV/CS-I
1
\.
_IOW-
.
(Go)
,
!WI
-..
!WO
1X
INTR
TL/DD/5530-5
FIGURE 5. MICROBUS Write Operation Timing
1·283
o
~
o
~
a.
oo
Functional Description
INTERNAL LOGIC
EN is an internal 4-bit register loaded by the LEI instruction.
The state of each bit of this register selects or deselects the
particular feature associated with each bit of the EN register:
The processor contains its own 4-bit A register (accumulator) which is the source and destination register for most
I/O, arithmetic, logic, and data memory access operations.
It can also be used to load the Br and Bd portions of the B
register, to load and input 4 bits of the 8-bit Q latch or T
counter, L I/O ports data, to input 4-bit G, or IN ports, and to
perform data exchanges with the SID register.
O. The least significant bit of the enable register, ENO, selects the SID register as either a 4-bit shift register or a 4bit binary counter. With ENO set, SID is an asynchronous
binary counter, decrementing its value by one upon each
low-going pulse ("1" to "0") occurring on the SI input.
Each pulse must be at least two instruction cycles wide.
SK outputs the value of SKL. The SO output equals the
value of EN3. With ENO reset, SID is a serial shift register
left shifting 1 bit each instruction cycle time. The data
present at SI goes into the least significant bit of SID. SO
can be enabled to output the most significant bit of SID
each cycle time. The SK outputs SKL ANDed with the
instruction cycle clock.
A 4-bit adder performs the arithmetic and logic functions,
storing the results in A. It also outputs a carry bit to the 1-bit
C register, most often employed to indicate arithmetic overflow. The C register in conjunction with the XAS instruction
and the EN register, also serves to control the SK output.
The 8-bit T counter is a binary up counter which can be
loaded to and from M and A using CAMT and CTMA instructions. This counter may be operated in two modes: as a
timer if TIN pin is tied to Ground or as an external event
counter if TIN pin is tied to Vee. When the T counter overflows, an overflow flag will be set (see SKT and IT instructions below). The T counter is cleared on reset. A functional
block diagram of the timer/counter is illustrated in Figure
10a.
1. With EN1 set, interrupt is enabled. Immediately following
an interrupt, EN1 is reset to disable further interrupts.
2. With EN2 set, the L drivers are enabled to output the data
in Q to the L I/O port. Resetting EN2 disables the L drivers, placing the L I/O port in a high-impedance input
state.
Four general-purpose inputs, IN3-INO, are provided. IN1,
IN2 and IN3 may be selected (by pulling MB pin low) as
Read Strobe, Chip Select, and Write Strobe inputs, respectively, for use in MICROBUS application.
3. EN3, in conjunction with ENO, affects the SO output. With
ENO set (binary counter option selected) SO will output
the value loaded into EN3. With ENO reset (serial shift
register option selected), setting EN3 enables SO as the
output of the SID shift register, outputting serial shifted
data each instruction time. Resetting EN3 with the serial
shift register option selected disables SO as the shift register output; data continues to be shifted through SIO and
can be exchanged with A via an XAS instruction but SO
remains set to "0".
The D register provides 4 general-purpose outputs and is
used as the destination register for the 4-bit contents of Bd.
In the dual clock mode, DO latch controls the clock selection· .
(see dual oscillator below).
The G register contents are outputs to a 4-bit general-purpose bidirectional I/O port. GO may be selected as an output for MICROBUS applications.
INTERRUPT
The Q register is an internal, latched, 8-bit register, used to
hold data loaded to or from M and A, as well as 8-bit data
from ROM. Its contents are outputted to the L I/O ports
when the L drivers are enabled under program control. With
the MICROBUS option selected, Q can also be loaded with
the 8-bit contents of the L I/O ports upon the occurrence of
a write strobe from the host CPU.
The following features are associated with interrupt procedure and protocol and must be considered by the programmer when utilizing interrupts.
a. The interrupt, once recognized as explained below,
pushes the next sequential program counter address
(PC + 1) onto the stack. Any previous contents at the bottom of the stack are lost. The program counter is set to
hex address OFF (the last word of page 3) and EN1 is
reset.
The 8 L drivers, when enabled, output the contents of
latched Q data to the L I/O port. Also, the contents of L may
be read directly into A and M. As explained above, the MICROBUS option allows L I/O port data to be latched into
the Q register.
b. An interrupt will be recognized only on the following conditions:
The SID register functions as a 4-bit serial-in/serial-out shift
register for MICROWIRETM I/O and COPS peripherals, or
as a binary counter (depending on the contents of the EN
register). Its contents can be exchanged with A.
1. EN1 has been set.
2. A low-going pulse ("1" to "0") at least two instruction
cycles wide has occurred on the IN1 input.
3. A currently executing instruction has been completed.
The XAS instruction copies C into the SKL latch. In the
counter mode, SK is the output SKL; in the shift register
mode, SK outputs SKL ANDed with the clock.
TABLE I. ENABLE REGISTER MODES -
BITS ENO AND EN3
ENO
EN3
SIO
SI
0
0
Shift Register
0
0
1
Shift Register
1
0
Binary Counter
Input to Shift
Register
Input to Shift
Register
Input to Counter
1
1
Binary Counter
Input to Counter
1
1-284
SO
SK
Serial
out
If SKL=1, SK=clock
If SKL=O, SK=O
If SKL=1, SK = clock
If SKL=O, SK=O
0
SK = SKL
SK = SKL
o
Functional Description
o
(Continued)
"0
4. All successive transfer of control instructions and successive LBls have been completed (e.g. if the main
program is executing a JP instruction which transfers
program control to another JP instruction, the interrupt
will not be acknowledged until the second JP instruction has been executed).
functioning and timing relationships between the signal lines
affected by this option are as specified for the MICROBUS
interface, and are given in the AC electrical characteristics
and shown in the timing diagrams (Figures 4 and 5). Connection of the COP404C to the MICROBUS is shown in Figure6.
c. Upon acknowledgement of an interrupt, the skip logic
status is saved and later restored upon popping of the
stack. For example, if an interrupt occurs during the execution of an ASC (Add with Carry, Skip on Carry) instruction which results in carry, the skip logic status is saved
and program control is transferred to the interrupt servicing routine at hex address OFF. At the end of the interrupt
routine, a RET instruction is executed to pop the stack
and return program control to the instruction following the
original ASC. At this time, the skip logic is enabled and
skips this instruction because of the previous ASC carry.
Subroutines should not be nested within the interrupt
service routine, since their popping of the stack will enable any previously saved main program skips, interfering
with the orderly execution of the interrupt routine.
oI:lo
o
oI:lo
o
INITIALIZATION
The external RC network shown in Figure 7 must be connected to the RESET pin for the internal reset logic to initialize the device upon power-up. The RESET pin is configured
as a Schmitt trigger input. If not used, it should be connected to Vee. Initialization will occur whenever a logic "0" is
applied to the RESET input, providing it stays low for at
least three instruction cycle times.
Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, D, EN, IL, T and G registers are
cleared. The SKL latch is set, thus enabling SK as a clock
output. Data Memory (RAM) is not cleared upon initialization. The first instruction at address 0 must be a CLRA
(clear A register).
d. The instruction at hex address OFF must be a NOP.
e. An LEI instruction may be put immediately before the
RET instruction to re-enable interrupts.
MICROBUS INTERFACE
...----4~-I1illEf
With MB pin tied to Ground, the COP404C can be used as a
peripheral microprocessor device, inputting and outputting
data from and to a host microprocessor (JLP). IN1, IN2 and
IN3 general purpose inputs become MICROBUS compatible
read-strobe, chip-select, and write-strobe lines, respectively.
IN1 becomes AD - a logic "0" on this input will cause Q
latch data to be enabled to the L ports for input to the JLP.
IN2 becomes CS - a logic "0" on this line selects the
COP404C and the JLP peripheral device by enabling the operation of the AD and WR lines and allows for the selection
of one of several peripheral components. IN3 becomes WR
- a logic "0" on this line will write bus data from the L ports
to the Q latches for input to the COP404C. GO becomes
INTR a "ready" output, reset by a write pulse from the JLP
on the WR line, providing the "handshaking" capability necessary for asynchronous data transfer between the host
CPU and the COP404C.
GND
RC~5X
AND
POWER SUPPLY RISE TIME
CKI PERIOD.
RC~1DOX
TL/DD/5530-8
FIGURE 7_ Power-Up Circuit
TIMER
There are two modes selected by TIN pin:
a) Time-base counter (TIN pin low). In this mode, the instruction cycle frequency generated from CKI passes
through a 2-bit divide-by-4 prescaler. The output of this
prescaler increments the 8-bit T counter thus providing a
1O-bit timer. The prescaler is cleared during execution of
a CAMT instruction and on reset. For example, using a
1MHz crystal, the instruction cycle frequency of 250 kHz
(divide by 4) increments the 10-bit timer every 4 JLS. By
presetting the counter and detecting overflow, accurate
timeouts between 16 JLS (4 counts) and 4.096 mS (1024
counts) are possible. Longer timeouts can be achieved
by accumulating, under software control, multiple overflows.
This option has been designed for compatibility with National's MICROBUS - a standard interconnect system for 8-bit
parallel data transfer between MOS/LSI CPUs and interfacing devices. (See MICROBUS National Publication). The
POWER
SUPPLY
CDP4D4C
CLOCK
b) External event counter (TIN pin high). In this mode, a lowgoing pulse ("1" to "0") at least 2 instruction cycles wide
on the IN2 input will increment the 8-bit T counter.
INTERRUPT (INTRI
Note: the IT instruction is not allowed in this mode.
MICROPROCESSOR
HALT MODE
READ STROBE (RDI
CHIP SELECT (CSI
IN
The COP404C is a FULLY STATIC circuit; therefore, the
user may stop the system oscillator at any time to halt the
chip. The chip may also be halted by two other ways (see
Figure 8):
WRITE STROBE (WRI
OUT
RESET
RESET
R~SET
TL/DD/5530-7
FIGURE 6. MICROBUS Option Interconnect
1-285
-
Software HALT: by using the HALT instruction.
-
Hardware HALT: by using the HALT 1/0 port CKOH. It
is an 1/0 flip-flop which is an indicator of the HALT
status. An external signal can over-ride this pin to start
and stop the chip. By forcing CKOH high the
•
(,)
~
o
Functional Description
D-
chip will stop as soon as CKI is high and CKOH output will
stay high to keep the chip stopped if the external driver
returns to high impedance state.
~
O
(,)
DO oscillator (the instruction cycle time equals the DO
oscillation frequency divided by 4) by setting the DO
latch high or the CKI oscillator by resetting DO latch
low.
Note that even in dual clock mode, the counter, if used
as a time-base counter, is always connected to the CKI
oscillator.
For example, the user may connect up to a 1 MHz RC
circuit to DO for faster processing and a 32 kHz external clock to CKI for minimum current drain and time
keeping.
(Continued)
Once in the HALT mode, the internal circuitry does not receive any clock signal and is therefore frozen in the exact
state it was in when halted. All information is retained until
continuing.
The chip may be awakened by one of two different methods:
- Continue function: by forCing CKOH low, the system
clock will be re-enabled and the circuit will continue to
operate from the point where it was stopped. CKOH
will stay low.
-
Restart: by forcing the
tion)
RESE'f
Note: CTMA instruction is not allowed when the chip is running from DO clock.
Figures 10a and 10b show the timer and clock diagrams
with and without Dual-Clock.
Vee
pin low (see Initializa-
The HALT mode is the minimum power dissipation state.
Note: if the user has selected dual-clock (DUAL pin tied to
Ground) AND is forcing an external clock on DO pin
AND the COP404C is running from the DO clock, the
HALT mode - either hardware or software - will NOT
be entered. Thus, the user should switch to the CKI
clock to HALT. Alternatively, the user may stop the DO
clock to minimize power.
CKI
J1..r
EXTERNAL
CLOCK
Oscillator Options
TL/DD/5530-9
Cycle
Time
4- 9 IJ-s
8-16 IJ-s
16-32 IJ-s
There are two basic clock oscillator configurations available
as shown by Figure 9.
R
C
Vee
~4.5V
15k
82 pF
~4.5V
30k
82 pF
2.4-4.5V
60k
100 pF
Note: 15k~R~150k
50 pF~C~150 pF
FIGURE 9. Dual-Oscillator Component Values
- CKI oscillator: CKI is configured as a LSTTL compatible input external clock signal. The external frequency
is divided by 4 to give the instruction cycle time.
- Dual oscillator. By tying DUAL pin to Ground, pin DO is
now a single pin RC controlled Schmitt trigger oscillator input. The user may software select between the
HALT
INSTRUCTION
TO CLOCK
GENERATOR
!imT.-----1.......,I
CKI
~--------------~--------~
TL/DD/5530-10
FIGURE 8. HALT Mode
1-286
o
Functional Description
o-a
(Continued)
0l:Io
o
0l:Io
o
TLIDD/5530-11
FIGURE 10a. Clock and Timer Block Diagram without Dual-Clock
TL/DD/5530-12
Figure 10b. Clock and Timer Block Diagram with Dual-Clock
1-287
o
-.::r
o
-.::r
External Memory Interface
COP404C Instruction Set
oo
The COP404C is designed for use with an external Program
Memory.
This memory may be implemented using any devices having
the following characteristics:
1. random addressing
2. LSTTL or CMOS-compatible TRI-STATE outputs
3. LSTTL or CMOS-compatible inputs
Table II is a symbol table providing internal architecture, instruction operand and operation symbols used in the instruction set table.
Table III provides the mnemonic, operand, machine code
data flow, skip conditions and description of each instruction.
Table II. Instruction Set Table Symbols
Definition
Symbol
Internal Architecture Symbols
A
4-bit Accumulator
8
7-bit RAM address register
8r
Upper 3 bits of 8 (register address)
8d
Lower 4 bits of 8 (digit address)
C
1-bit Carry register
D
4-bit Data output port
EN
4-bit Enable register
G
4-bit General purpose I/O port
IL
two 1-bit (lNO and IN3) latches
IN
4-bit input port
8-bitTRI-STATE I/O port
L
M
4-bit contents of RAM addressed by 8
PC
11-bit ROM address program counter
Q
8-bit latch for L port
SA
11-bit Subroutine Save Register A
S8
11-bit Subroutine Save Register 8
SC
11-bit Subroutine Save Register C
SIO
4-bit Shift register and counter
SK
Logic-controlled clock output
SKL
1-bit latch for SK output
T
8-bit timer
Q.
4. access time = 1. 0 /Ls max.
Typically, these requirements are met using bipolar PROMs
or MOS/CMOS PROMs, EPROMs or E2PROMs.
During operation, the address of the next instruction is sent
out on A10, A9, A8 and IP7 through IPO during the time that
AD/DATA is high (logic "1 "=address mode). Address data
on the IP lines is stored into an external latch on the high-tolow transition of the AD/DATA line; A10, A9 and A8 are
dedicated address outputs, and do not need to be latched.
When AD/DATA is low (logic "0"= data mode), the output
of the memory is gated onto IP7 through IPO, forming the
input bus. Note that AD/DATA output has a period of one
instruction time, a duty cycle of approximately 50%, and
specifies whether the IP lines are used for address output or
data input. A simplified block diagram of the external memory interface is shown in Figure 11.
Al0
A9
COP404C
r - - AS
r - - AD/DATA
IP7-IPo
.....
~
A
B~
ym
.....
DATA
'1
Instruction operand symbols
d
4-bit operand field, 0-15 binary (RAM digit select)
3-bit operand field, 0-7 binary (RAM register select)
a
11-bit operand field, 0-2047
y
4-bit operand field, 0-15 (immediate data)
RAM (x) RAM addressed by variable x
ROM(x) ROM addressed by variable x
Operational Symbols
+
Plus
Minus
->
Replaces
< - > is exchanged with
Is equal to
~
D
LATCH
a
en
en
~
I
S
S
CI:
""'II:
...... CE
~AS
A9
Al0
~
AO-A7
DO-D7
MEMORY
TLIDD/5530-13
A
FIGURE 11. External Memory Interface to COP404C
ED
1-288
one's complement of A
exclusive-or
range of values
o
o-a
Instruction Set (Continued)
~
TABLE III. COP404C Instruction Set
o
~
Mnemonic
Operand
Hex
Code
Machine
Language
Code (Binary)
Skip
Conditions
Data Flow
o
Description
ARITHMETIC INSTRUCTIONS
ASC
30
10011100001
ADD
ADT
AISC
31
4A
5-
10011100011
10011100011
101011 y I
CASC
10
10001100001
CLRA
COMP
NOP
RC
SC
XOR
00
40
44
32
22
02
10000100001
10100100001
10100101001
10011100101
10010100101
10000100101
y
A+C+RAM(B) ~ A
Carry ~ C
A+RAM(B) ~ A
A+1010 ~ A
A+y ~ A
Carry
A+RAM(B)+C ~ A
Carry ~ C
Carry
O~A
None
None
None
None
None
None
Add with Carry, Skip on
Carry
Add RAM toA
Add Ten toA
Add Immediate. Skip on
Carry (y.
Ico = 6 + 2.88 + 25.2 = 34.08 /-LA
If an IT instruction is executed, the chip goes into the IDLE
mode until the timer overflows. In IDLE mode, the current
drain can be calculated from the following equation:
Ici = Iq + V
x 40 X Fi
For example, at 5 volts Vee and 400 kHz
INIL INSTRUCTION
Ici = 20 + 5
INIL (Input IL Latches to A) inputs 2 latches, IL3 and ILO,
CKOI and 0 into A. The IL3 and ILO latches are set if a lowgoing pulse ("1" to "a") has occurred on the IN3 and INa
inputs since the last INIL instruction, provided the input
pulse stays low for at least two instruction cycles. Execution
of an INIL inputs IL3 and ILO into A3 and AO respectively,
and resets these latches to allow them to respond to subsequent low-going pulses on the IN3 and INa lines. The state
of CKOI is input into A2. A 0 is input into A1. IL latches are
cleared on reset.
x 40 x .4 = 100 /-LA
The total average current will then be the weighted average
of the operating current and the idle current:
Ita= IcoX
~
To+Ti
+ Ici x
~
To+Ti
where:
Ita = total average current
Ico = operating current
Ici = idle current
To = operating time
Instruction Set Notes
Ti = idle time
a. The first word of a program (ROM address 0) must be a
CLRA (Clear A) instruction.
1/0 OPTIONS
b. Although skipped instructions are not executed, they are
still fetched from the program memory. Thus program
paths take the same number of cycles whether instructions are skipped or executed except for JID, and LaiD.
COP404C outputs have the following configurations, illustrated in Figure 12.
a. Standard - A CMOS push-pull buffer with an N-channel
device to ground in conjunction with a P-channel device
to Vee, compatible with CMOS and LSTTL. (Used on SO,
SK, AD/DATA, SKIP, A10:8 and 0 outputs.)
c. The ROM is organized into pages of 64 words each. The
Program Counter is a 11-bit binary counter, and will count
through page boundaries. If a JP, JSRP, JID, or LaiD is
the last word of a page, it operates as if it were in the next
page. For example: a JP located in the last word of a
page will jump to a location in the next page. Also, a JID
or LaiD located in the last word of every fourth page (Le.
hex address OFF, 1FF, 2FF, 3FF, 4FF, etc.) will access
data in the next group of four pages.
b. Low Current - This is the same configuration as a.
above except that the sourcing current is much less.
(Used on G outputs.)
c. Standard TRI-STATE L Output - A CMOS output buffer
similar to a. which may be disabled by program control.
(Used on L outputs.)
All inputs have the following configuration:
Power Dissipation
d. Input with on chip load device to Vee. (Used on CKOI.)
The lowest power drain is when the clock is stopped. As the
frequency increases so does current. Current is also lower
at lower operating voltages. Therefore, for minimum power
dissipation, the user should run at the lowest speed and
voltage that his application will allow. The user should take
care that all pins swing to full supply levels to insure that
outputs are not loaded down and that inputs are not at
some intermediate level which may draw current. Any input
with a slow rise or fall time will draw additional current. For
e. HI-Z input which must be driven by the users logic. (Used
on CKI, RESET, IN, SI, DUAL, TIN, MB, SEL10 and
SEL20 inputs.)
All output drivers use one or more of three common devices
numbered 1 to 3. Minimum and maximum current (lOUT and
VOUT) curves are given in Figure 13 for each of these devices to allow the designer to effectively use these I/O configurations.
1-292
o
o
"o
~
Vee
Vee
Vee
a. Standard Push-Pull Output
b. Low Current Push-Pull Output
~
o
Standard TRI-STATE "L" Output
TL/DD/5530-15
e. HI-Z Input
d. Input with Load.
FIGURE 12. Input/Output Configurations
Typical Performance Characteristics
Low Current Option
Minimum Source Current
Standard Minimum Source
Current
Minimum Sink Current
1.2
t--+-+--+-+---IL----j
1.0
1.6 1----+-+----....o£;;....-+---1f-----j
0.8
2.0
60
5.5V
c
S-
1.2 t--t---::l~-i:=.....-+---t
C
S-
::c
0.6 4.5V
'---
~
0.8
t-~"+-_+_-+---+-+---t
0.4
0.2
1.0
2.0
3.0
4.0
5.0
a
6.0
3.0V
I-2.4V
a
1.0
--
~
2.0
400
t---+--'::~-~-+-+---I
300
I-""""k~+--+'~+--I-~
~ "'500
1---+--+-.3ior-~-+'~-+--4
100
400
i::c
VOH (VOLTS)
5.0
6.0
4.0
5.0
6.0
85°C
i
u
u
1'\
2.0
3.0
V
5.0
/""
6.0
VOH (VOLTS)
2
3
70·C
~
-
25·C
~
...,...V
1\
4.0
V
,...V
40
\
t-- ~
1/
80
I\.
200 3.0V
1.0
3.0
Maximum Quiescent
Current
1\,
o
o
2.0
VOH (VOLTS)
~
300
100
4.0
1.0
6.0
120
9
9
3.0
30~--+~~~~--+~4----j
1\
50
600
SOD
2.0
[\
4.0
§
Low Current Option
Maximum Source Current
600 "--""'-""--I""'""--r-,--,
1.0
"I\.\
'"
3.0
i
VOH (VOLTS)
Low Current Option
Maximum Source Current
200
......
r-.....
Vol {VOLTSI
~::c
40~-+-4-~~~-+--4
--- '
0.4
5.5V
4
Vee (VOLTS)
TLIDD/5530-16
FIGURE 13. Input/Output Characteristics
1-293
o
~
c
Emulation
0.
The COP404C may be used to exactly emulate the
COP444C/445C, COP424C/425C, and COP41 OCI 411 C.
However, the Program Counter always addresses 2k of external ROM whatever chip is being emulated. Figure 14
shows the interconnect to implement a hardware emulation.
This connection uses a NMC27C16 EPROM as external
~
oo
memory. Other memory can be used such as bipolar PROM
or RAM.
Pins IP7-IPO are bidirectional inputs and outputs. When the
AD/DATA clocking output turns on, the EPROM drivers are
disabled and IP7-IPO output addresses. The 8-bit latch
(MM74C373) latches the addresses to drive the memory.
GNO
CDP444C
PINOUT
\
GNO
CK I
4
mET
7
6
5
4
IN 1
10
IN 2
11
Ve e
12
3
13
2
14
1
15
0
16
I
17
0
18
K
19
IN 0
20
IN 3
21
0
22
1
23
2
24
3
25
3
26
2
27
1
28
0
1113 14 15 16 17 12
00 0, 0, 03 O. 05 De 0., Vu
18 08
0, 19
1
o-l CKOI
IPI 8
17 07
07 16
2 1.6
CKOH
IPS 9
14 06
0, 15
3
IP4 10
13 05
05 12
4
11
6 04
9
5
IP2 12
7 03
03
6
I
IPl 13
402
0, 5
7
IPO 14
3
2
8
I~
CKO
19L
r--ll0
OC
GNO
7
3
IP7
5
6
IP3
15
16
17
18
SKIP
~
MM74C373
O.
0,
01
LE
11
Vee
18
1.7
1.5
1.4
1.3
1.2
AD
U
AD/om 39
GGE
2D
AS 41
23 1.8
21
1.9 48
22 1.9
22
1.10 1
19
23
24
20
19
~rIn
~
25
1.10
Vee
Vee
COP404C
NMC27C16
1.1
2C
v"
21
MICR08US'·
26
27
29
~
OUAL·CLOCK
30
31
32
Vee
Vee
15UAt ~
Vee
TiH~rI
GNO
33
TIMER
34
35
43
44
37
Rrn r---o-
~r-
0-!!2.
COP424C
45
Vee
42
miD ~~
0-2!!-
COP410C
TL/DD/5530-14
FIGURE 14. COP404C Used To Emulate A COP444C
1-294
o
Emulation
o
(Continued)
."
When AD/DATA turns off, the EPROM is enabled and the
IP7-IPO pins will input the memory data. A10, A9 and A8
output the most significant address bits to the memory.
(SKIP output may be used for program debug if needed.)
-
CKI is divided by 4. Other divide-by are emulated by external divider.
-
CKO can be emulated as a general purpose input by using CKOI or as a Halt I/O port by using CKOH.
-
MB pin can be pulled low if the MICROBUS feature of the
COP444C and COP424C is needed. Othewise it should
be high.
-
DUAL pin can be pulled low if the Dual-Clock feature of
the COP444C and COP424C is needed. Otherwise it
should be high.
-
TIN pin controls the input of the 8-bit timer of the
COP444C and COP424C (internal timer if "fiN is low, external event counter if "fiN is high).
-
The SEL10 and SEL20 inputs are used to emulate the
COP444C/445C, COP424C/425C, or COP41 OCI 411 C.
• When emulating the COP444C/445C, the user must
configure SEL20 = 1 and SEL 10 = 1.
• When emulating the COP424C/425C, the user must
configure SEL20 = 0 and SEL 10 = 1. In this mode, the
user RAM is physically halved. As in the COP424CI
425C, the user has 64 digits (256 bits) of RAM available. Pin A 10 should not be connected to the program
memory (most significant address bit of the program
memory should be grounded if using a 2kx8 memory).
in the same way as the COP41 OCI 411 C - 4 registers of
8 digits each. Pins A 10 and A9 should not be connected to the program memory (the 2 most significant address bits of the program memory should be grounded).
Furthermore, the subroutine stack is decreased from 3
levels to 2 levels.
~
<:)
~
o
The pins SEL 10 and SEL20 change the internal logic of the
device to accurately emulate the devices as indicated
above. However, the user must remember that the
COP424C/425C is a subset of the COP444C/COP445C
with respect to memory size. The COP41 OCI 411 C is a subset both in memory size and in function. The user must take
care not to use features and instructions which are not available on the COP41 OCI 411 C (see table IV. below) when using the COP404C to emulate the COP41 OCI 411 C.
TABLE IV. FEATURES AND INSTRUCTIONS NOT
AVAILABLE ON COP410C/411C.
Timer
Dual-clock
Interrupt
Microbus
• When emulating the COP41 OCI 411 C, the user must
configure SEL20 = 0 and SEL 10 = O. In this mode, the
user has 32 digits (128 bits) of RAM available organized
ADT
CASC
CAMT
CTMA
IT
LDD
XAD
XABR
SKT
ININ
INIL
OGI
r, d
r, d
(except 3, 15)
y
Option Table
COP404C MASK OPTIONS
The following COP444C options have been implemented in the COP404C:
Option value
Option 1 =0
Option 2= 1, 2
Option 3=5
Option4=1
Option 5-8=0
Option9=1
Option 10=1
Option 11 =0
Option 12-15=0
Option 16=0
Option 17=0
Option 18=0
Option 19= 1
Option 20= 1
Option 21-24 = 1
Option 25-28 = 0
Option 29=1
Option 30 = 0, 1
Option 31 =0,1
Option 32 = 0, 1
Option 33 = NI A
1-295
Comment
Ground Pin - no option available
CKO is replaced by CKOI and CKOH
CKI is external clock input divided by 4
RESET is Hi-Z input
L outputs are standard TRI-STATE
IN1 is a Hi-Z input
IN2 is a Hi-Z input
Vee pin - no option available
L outputs are standard TRI-STATE
SI is a Hi-Z input
SO is a standard output
SK is a standard output
INO is a Hi-Z input
IN3 is a Hi-Z input
G outputs are low-current
D outputs are standard
No internal initialization logic
DUAL-CLOCK is pin selectable
TIMER is pin selectable
MICROBUS is pin selectable
48-pin package
III
.
Lt)
z
~
~
o
~
a..
oo
~NaHonal
~ Semiconductor
COP404LSN-5 ROMless N-Channel Microcontrollers
General Description
Features
The COP404LSN·5 ROM less Microcontroller is a member
of the COPSTM family, fabricated using N·channel, silicon
gate MOS technology. The COP404LSN·5 contains CPU,
RAM, I/O and is identical to a COP444L device except the
ROM has been removed and pins have been added to out·
put the ROM address and to input the ROM data. In a sys·
tern the COP404LSNN·5 will perform exactly as the
COP444L. This important benefit facilitates development
and debug of a COP program prior to masking the final part.
The COP404LSN·5 is also appropriate in low volume appli·
cations, or when the program might be changing. The
COP404LSN·5 may be used to emulate the COP444L,
COP445L, COP420L, and ~~e COP421 L.
Use COP404LSN-5 in volume applications. For extended
temperature range. (-40·C to + 85·C), COP304L is avail·
able on a special order basis.
• Exact circuit equivalent of COP444L
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low cost
Powerful instruction set
128 x 4 RAM, addresses 2048 x 8 ROM
True vectored interrupt, plus restart
Three·level subroutine stack
16 IJ-s instruction time
Single supply operation (4.5V-5.5V)
Low current drain (16 rnA max)
Internal time·ba:se counter for real·time processing
Internal binary counter register with MICROWIRETM
compatible serial I/O
General purpose outputs
LSTILICMOS compatible in and out
Direct drive of LED digit and segment lines
Software/hardware compatible with other members of
COP400 family
Block Diagram
AD/DArA
IPo
IP,
IPz
IP3
IPI
IP,
IPs
IPI
PI
Pg
SKIP/P,o
00
.--------~_:l,cROW1RE
110
$J
11
27 16 15
CKO
1N3 INZ IN1
12 13 14 18 19 2D 21
26
INO
TLlDD/8817-1
FIGURE 1
1-296
(")
o"tJ
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage at Any Pin Relative to GND
-0.5V to + 10V
O°C to + 70'C
Ambient Operating Temperature
Ambient Storage Temperature
- 65'C to + 150'C
Lead Temperature (Soldering, 10 sec.)
300'C
Power Dissipation
0.75W at 25'C
OAW at 70'C
Total Source Current
120 mA
Total Sink Current
140mA
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
DC Electrical Characteristics
4.5V ~ Vee ~ 5.5V; O'C ~ T A ~ 70'C
Parameter
Conditions
Min
Max
Units
5.5
V
Operating Voltage (Vee>
(Note 2)
Power Supply Ripple
Peak to Peak
0.5
V
Operating Supply Current
All Inputs and Outputs Open
16
mA
2.0
-0.3
0.4
V
V
0.7 Vee
-0.3
0.6
V
2.4
2.0
-0.3
O.s
V
V
V
3.6
-0.3
1.2
V
V
7
pF
Input Voltage Levels
CKllnput Levels
Crystal Input
Logic High (VI H)
Logic Low (VII)
RESET Input Levels
Logic High
Logic Low
IPO-IP7, Sllnput Levels
Logic High
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
4.5
Schmitt Trigger Input
Vee = 5.5V
Vee = 5V ±5%
High Trip Level Options
Selected
Input Capacitance
Output Voltage Levels
LSTIL Operation
Logic High (VOH)
Logic Low (Vod
IPO-IP7, PS, P9, SKIP/P10
Logic High
Logic Low
Vee=5V±10%
IOH = -25,...A
IOL = 0.36 mA
(Note 1)
IOH = -SO,...A
IOL = 720,...A
Output Current Levels
Output Sink Current
SO and SK Outputs (Iod
Lo-L7 Outputs
GO-G3 and 00-03 Outputs
CKO
Vee
Vee
Vee
Vee
Output Source Current
00- 0 3, GO-G3 Outputs (IOH)
SO and SK Outputs (IOH)
Lo-L7 Outputs
=
=
=
=
4.5V, VOL
4.5V, VOL
4.5V, VOL
4.5V, VOL
V
V
2.7
0.4
V
0.4
V
V
2.4
=
=
=
=
O.4V
O.4V
1.0V
O.4V
Vee = 4.5V, VOH = 2.0V
Vee = 4.5V, VOH = 1.0V
Vee = 5.5V, VOH = 2.0V
1-297
0.9
0.4
7.5
0.2
-30
-1.2
-1.4
mA
mA
mA
mA
-250
,...A
-25
mA
mA
~
o
~
r
en
z
I
U1
.
it)
z
~
~
o
~
a..
oo
DC Electrical Characteristics
OGC ~ TA ~
+ 70GC, 4.5V
(Continued)
~ Vee ~ 5.5V unless otherwise noted
Parameter
Input Load Source Current (IIU
Conditions
=
Vee
5.0V, VIL
=
OV
Min
Max
Units
-10
-140
p.A
140
120
4
4
1.8
mA
mA
mA
mA
mA
120
60
60
30
1.5
mA
mA
mA
mA
mA
Total Sink Current Allowed
All Outputs Combined
D, G Ports
Lr L4
L3- LO
All Other Pins
Total Source Current Allowed
All 110 Combined
L7- L4
L3-Lo
Each L Pin
All Other Pins
AC Electrical Characteristics OGC ~ T A ~ 70GC, 4.5V ~ Vee ~ 5.5V unless otherwise specified
Parameter
Conditions
Instruction Cycle Time
CKI
Input Frequency, f
Duty Cycle
Rise Time
Fall Time
(+32 Mode)
fl
=
Min
Max
Units
16
40
p's
0.8
30
2
60
120
80
MHz
%
ns
ns
2.0 MHz
INPUTS:
SI,IP7-IPO
tSETUP
tHOLD
IN3-INo, G3-GO, L7-Lo
tSETUP
tHOLD
OUTPUT PROPAGATION DELAY
SO, SK Outputs
tpd1, tpdO
D3- DO, G3- GO, L7- LO
tpd1, tpdO
IP7-IPO, P8, P9, SKIP
tpd1, tpdO
P10
Test Condition:
CL = 50 pF, VOUT
RL = 20 kn
RL
=
20 kn
RL
=
5 kn
RL
=
5 kn
=
1-298
p's
p's
8.0
1.3
p's
p.s
1.5V
tpd1, tpdO
COP404LSN-5 has Push-Pull drivers on these outputs.
Note 2: Vee voltage change must be less than O.5V in a 1 ms period to maintain proper operation.
Note 1:
2.0
1.0
4.0
p's
5.6
p.s
7.2
p's
6.0
p's
Connection Diagram
Pin Descriptions
"U
0l:Io
Q
Dual-In-Llne Package
Pin
CKO
40
DO
CKI
39
01
L7-Lo
G3- GO
03- 0 0
IP4
38
02
Rmf
31
OJ
IPJ
36
IP5
IN3-INo
SI
SO
SK
IP2
35
IPI
34
PI
pg
IPO
3J
AD/DATA
IP1
32
SKIP/PIO
31
GJ
AD/DATA
CKI
CKO
IP6
10
L1
II
30
G2
L6
12
29
GI
RESET
L5
13
21
GO
L4
14
21
IN]
Vee
INI
15
26
INO
IN2
16
25
SK
VCC
11
24
SO
L3
18
2J
SI
L2
19
22
GND
L1
20
21
LO
COP404LSN-5
o
o
GND
IP7-IPO
P8,P9
SKIP/P10
Description
8 bidirecitonall/O ports with TRI-STATEIBl
4 bidirectional I/O ports
4 general purpose outputs
4 general purpose outputs
Serial input (or counter input
Serial output (or general purpose output)
Logic-controlled clock (or general purpose output)
Address out/data in flag
System oscillator input
System oscillator output (COP404LSN-5)
System reset input
Power supply
Ground
8 bidirectional ROM address and data ports
2 ROM address outputs
Instruction skip output and most significant
ROM address bit output
TL/DD/8817-2
Top View
FIGURE 2
Order Number COP404LSN-5
See NS Package Number N40A
Timing Diagram
CKI
AD/Dm. SK
(AS A CLOCK)
INO-IN3. GO-G3,
LO-L7. CKO. SI
IPO-IP7 INPUTS
GO-G3. 00-03.
LD-L7. SO. SI
OUTPUTS
SKIP/P10
OUTPUT
IPO-IP7. P8. pg
OUTPUTS
VOH
(SKIP)
~~;..V,;;,;OL;..........;.(P_l..;.O)_ _ _~=~VO;;..L_ _ _ _ _ _......'"""". VOH
I-~.----.jtmr,.""r----------- ~ v"
TLlDD/8817-3
FIGURE 3. Input/Output
1-299
0l:Io
~
ZI
CJ1
Functional Description
A block diagram of the COP404LSN-S is given in Figure 1.
Data paths are illustrated in simplified form to depict how
the various logic elements communicate with each other in
implementing the instruction set of the device. Positive logic
is used. When a bit is set, it is a logic "1" (greater than 2V).
When a bit is reset, it is a logic "0" (less than 0.8V).
Four general-purpose inputs, IN3-INo, are provided.
The 0 register provides 4 general-purpose outputs and is
used as the destination register for the 4-bit contents of 8d.
The 0 outputs can be directly connected to the digits of a
multiplexed LED display.
The G register contents are outputs to 4 general-purpose
bidirectional 110 ports. G 1/0 ports can be directly connected to the digits of a multiplexed LED display.
PROGRAM MEMORY
Program Memory consists of a 2048 byte external memory.
As can be seen by an examination of the COP404LSN-S
instruction set, these words may be program instructions,
program data or ROM addressing data. 8ecause of the special characteristics associated with the JP, JSRP, JIO and
LQIO instructions, ROM must often be thought of as being
organized into 32 pagesof 64 words each.
The Q register is an internal, latched, a-bit register, used to
hold data loaded to or from M and A, as well as 8-bit data
from ROM. Its contents are output to the L 110 ports when
the L drivers are enabled under program control. (See LEI
instruction.)
The a L drivers, when enabled, output the contents of
latched Q data to the L 1/0 ports. Also, the contents of L
may be read directly into A and M. L 110 ports can be directly connected to the segments of a multiplexed LED display
(using the LED Direct Drive output configuration option) with
Q data being outputted to the Sa-Sg and decimal point
segments of the display.
ROM addressing is accomplished by an 11-bit PC register.
Its binary value selects one of the 2048 8-bit words contained in ROM. A new address is loaded into the PC register
during each instruction cycle. Unless the instruction is a
transfer of control instruction, the PC register is loaded with
the next sequential 11-bit binary count value. Three levels of
subroutine nesting are implemented by the 11-bit subroutine
saves registers, SA, S8, and SC, providing a last-in, first-out
(LIFO) hardware subroutine stack.
The SIO register functions as a 4-bit serial-in/serial-out shift
register or as a binary counter depending on the contents of
the EN register. (See EN register description, below.) Its
contents can be exchanged with A, allowing it to input or
output a continuous serial data stream. 510 may also be
used to provide additional parallel 1/0 by connecting SO to
external serial-in/parallel-out shift registers.
ROM instruction words are fetched, decoded and executed
by the Instruction Decode, Control and Skip Logic circuitry.
DATA MEMORY
Data memory consists of a S12-bit RAM, organized as 8
data registers of 16 4-bit digits. RAM addressing is implemented by a 7-bit 8 register whose upper 3 bits (8r) select 1
of 8 data registers and lower 4 bits (8d) select 1 of 16 4-bit
digits in the selected data register. While the 4-bit contents
of the selected RAM digit (M) is usually loaded into or from,
or exchanged with, the A register (accumulator), it may also
be loaded into or from the Q latches or loaded from the L
ports. RAM addressing may also be performed directly by
the LOO and XAO instructions based upon the 7-bit contents of the operand field of these instructions. The 8d register also serves as a source register for 4-bit data sent
directly to the 0 outputs.
The XAS instruction copies C into the SKL latch. In the
counter mode, SK is the output of SKL; in the shift register
mode, SK outputs SKL ANOed with the clock.
The EN register is an internal 4-bit register loaded under
program control by the LEI instruction. The state of each bit
of this register selects or deselects the particular feature
associated with each bit of the EN register (EN3-ENo).
1. The least significant bit of the enable register, ENo, selects the SIO register as either a 4-bit shift register or a 4bit binary counter. With ENo set, SIO is an asynchronous
binary counter, decrementing its value by one upon each
low-going pulse ("1" to "0") occurring on the SI input.
Each pulse must be at least two instruction cycles wide.
SK outputs the value of SKL. The SO output is equal to
the value of EN3.· With ENo reset, SIO is a serial shift
register shifting left each instruction cycle time. The data
present at SI goes into the least significant bit of SIO. SO
can be enabled to output the most significant bit of SIO
each cycle time. (See 4 below.) The SK output becomes
a logic-controlled clock.
INTERNAL LOGIC
The 4-bit A register (accumulator) is the source and destination register for most 1/0, arithmetic, logic and data memory
access operations. It can also be used to load the 8r and 8d
portions of the 8 register, to load and input 4 bits of the 8-bit
Q latch data, to input 4 bits of the a-bit L 1/0 port data and
to perform data exchanges with the SIO register.
A 4-bit adder performs the arithmetic and logic functions,
storing its results in A. It also outputs a carry bit to the 1-bit
C register, most often employed to indicate arithmetic overflow. The C register, in conjunction with the XAS instruction
and the EN register, also serves to control the SK output. C
can be outputted directly to SK or can enable SK to be a
sync clock each instruction cycle time. (See XAS instruction
and EN register description, below).
2. With EN1 set the IN1 input is enabled as an interrupt input. Immediately following an interrupt, EN1 is reset to
disable further interrupts.
3. With EN2 set, the L drivers are enabled to output the data
in Q to the L 110 ports. Resetting EN2 disables the L
drivers, placing the L 110 ports in a high-impedance input
state.
1-300
o
Functional Description
o
(Continued)
"'C
,I::io.
4. ENa, in conjunction with ENo, affects the SO output. With
ENo set (binary counter option selected) SO will output
the value loaded into ENa. With ENo reset (serial shift
register option selected), setting EN3 enables SO as the
output of the SIO shift register, outputting serial shifted
data each instruction time. Resetting ENa with the serial
shift register option selected disables SO as the shift register output; data continues to be shifted through SIO and
can be exchanged with A via an XAS instruction but SO
remains reset to "0." The table below provides a summary of the modes associated with ENa and ENo.
d. The first instruction of the interrupt routine at hex address
OFF must be a Nap.
o,I::io.
r-
e. A LEI instruction can be put immediately before the RET
to re-enable interrupts.
z
INITIALIZATION
The Reset Logic will initialize (clear) the device upon powerup if the power supply rise time is less than 1 ms and greater than 1 !-,-s. If the power supply rise time is greater than
1 ms, the user must provide an external RC network and
diode to the RESET pin as shown below. The RESET pin is
configured as a Schmitt trigger input. If the RC network is
not used, the RESET pin should be left open. Initialization
will occur whenever a logiC "0" is applied to the RESET
input, provided it stays low for at least three instruction cycle
times.
INTERRUPT
The following features are associated with the IN1 interrupt
procedure and protocol and must be considered by the programmer when utilizing interrupts.
a. The interrupt, once acknowledged as explained below,
pushes the next sequential program counter address
(PC + 1) onto the stack, pushing in turn the contents of
the other subroutine-save registers to the next lower level
(PC+ 1 ~ SA ~ SB ~ SC). Any previous contents
of SC are lost. The program counter is set to hex address
OFF (the last word of page 3) and EN1 is reset.
p +
0
E
R
P
L
y
3. A currently executing instruction has been completed.
4. All successive transfer of control instructions and successive LBls have been completed (e.g., if the main
program is executing a JP instruction which transfers
program control to another JP instruction, the interrupt
will not be acknowledged until the second JP instruction has been executed.
o
o
J
SIO
~
5 x Power Supply Rise Time (R > 40k)
EXTERNAL MEMORY INTERFACE
c. Upon acknowledgement of an interrupt, the skip logic
status is saved and later restored upon popping of the
stack. For example, if an interrupt occurs during the execution of ASC (Add with Carry, Skip on Carry) instruction
which results in carry, the skip logic status is saved and
program control is transferred to the interrupt servicing
routine at hex address OFF. At the end of the interrupt
routine, a RET instruction is executed to "pop" the stack
and return program control to the instruction following the
original ASC. At this time, the skip logic is enabled and
skips this instruction because of the previous ASC carry.
Subroutines and LOID instructions should not be nested
within the interrupt service routine, since their popping the
stack will enable any previously saved main program
skips, interfering with the orderly execution of the interrupt routine.
Enable Register Modes -
o
GNO
Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, 0, EN, and G registers are cleared.
. The SK output is enabled as a SYNC output, providing a
pulse each instruction cycle time. Data Memory (RAM) is
not cleared upon initialization. The first instruction at address 0 must be a CLRA.
cycles wide occurs on the IN1 input.
o
f
-
RC
2. A low-going pulse ("1" to "0") at least two instruction
ENo
RESET
TL/DD/8817-4
1. EN1 has been set.
EN3
vee
oil
S
U
p
b. An interrupt will be acknowledged only after the following
conditions are met:
I
n: »~ -~ ~
w
The COP404LSN-5 is designed for use with an external Program Memory. This memory may be implemented using any
devices having the following characteristics:
1. random addressing
2. TIL-compatible TRI-STATE outputs
3. TIL-compatible inputs
4. access time = 5 !-,-S max.
Typically these requirements are met using bipolar or MaS
PROMs.
During operation, the address of the next instruction is sent
out on P10, P9, P8, and IP7 through IPO during the time that
AD/DATA is high (logic "1" = address mode). Address
data on the IP lines is stored into an external latch on the
high-to-Iow transition of the AD/DATA line; P9 and P8 are
Bits EN3 and ENo
SI
SO
Shift Register
Input to Shift Register
o
Shift Register
Input to Shift Register
Serial Out
Binary Counter
Input to Binary Counter
o
Binary Counter
Input to Binary Counter
1-301
SK
IfSKL
IfSKL
IfSKL
IfSKL
IfSKL
If SKL
If SKL
IfSKL
= 1,SK = CLOCK
=
=
=
=
=
=
=
O,SK
1,SK
O,SK
1,SK
0, SK
1, SK
O,SK
=
=
=
=
=
=
=
0
CLOCK
0
1
0
1
0
en
I
U1
Ln
z•
~
~
o
~
a.
o(,)
Functional Description
(Continued)
dedicated address outputs, and do not need to be latched.
SKIP/P10 outputs address data when AD/DATA is low.
When AD/DATA is low (logic "0" = data mode), the output
of the memory is gated onto IP7 through IPO, forming the
input bus. Note that the AD/DATA output has a period of
one instruction time, a duty cycle of approximately 50%,
and specifies whether the IP lines are used for address output or instruction input.
b. Open-Draln-an enhancement-mode device to ground
only, allowing external pull-up as required by the user's
application.
OSCILLATOR
d. LED Direct Drive-an enhancement-mode device to
ground and to Vee, meeting the typical current sourcing
requirements of the segments of an LED display. The
sourcing device is clamped to limit current flow. These
devices may be turned off under program control (see
Functional Description, EN Register), placing the outputs
in a high-impedance state to provide required LED segment blanking for a multiplexed display. (Used on L outputs.)
c. Push-Pull-an enhancement-mode device to ground in
conjunction with a depletion-mode device paralleled by
an enhancement-mode device to Vee. This configuration
has been provided to allow for fast rise and fall times
when driving capacitive loads.
The basic clock oscillator configurations is shown in Figure
4.
Crystal Controlled Osclllator-CKI and CKO are connected to an external crystal. The instruction cycle time equals
the crystal frequency divided by 32.
COP404LS
CKI
COP404LSN-5 Inputs have an on-Chip depletion load device
to Vee.
The above input and output configurations share common
enhancement-mode and depletion-mode devices. Specifically, all configurations use one or more of six devices
(numbered 1-6, respectively). Minimum and maximum current (lOUT and VOUT) curves are given in Figure 6 for each
of these devices to allow the deSigner to effectively use
these I/O configurations in deSigning a system.
CKO
1M
6·36pF
*56 PF
An important pOint to remember is that even when the L
drivers are disabled, the depletion load device will source a
small amount of current (see Figure 6, device 2); however,
when the L-lines are used as inputs, the disabled depletion
device can not be relied on to source sufficient current to
pull an input to a logic "1".
TLlDD/8817-5
FIGURE 4. Oscillator
INPUTIOUTPUT CONFIGURATIONS
COP404LSN-5 outputs have the following configurations, illustrated in Figure 5:
a. Standard-an enhancement mode device to ground in
conjunction with a depletion-mode device to Vee, compatible with LSTTL and CMOS input requirements. (Used
on D and G outputs.)
TL/DD/8817-7
b. Open-Drain Output
TL/DD/8817-8
TLlDD/8817 -8
a. Standard Output
c. Push-Pull Output
vee
~J
#6
"puT~f
TL/DD/8817-10
e. Input with Load
TL/DD/8B17-9
d. L Output (LED)
(& is Depletion Device)
FIGURE 5. Output Configurations
1-302
o
o-a
Typical Performance Characteristics
~
Q
Current for Inputs with
Load Device
-200
-100
-90
~,e
~
Input Current for La through
L7 when Output Programmed
Off by Software
-1000
DEVICE d 2
-900
-so
~
~
r-.. ......
-100
j
"l
-30
~rV~
o
o
-700
-20
-10
~-400
-zoo
~
-t--4-
r--.~
1.0
0123456789
VOH(VOLTS)
-40 L Output Source Current
-30
V
-10
o
IWiN O
o
O~~~~~~~~~
~ ~~
o
1 2 3 4 5 6 7 8 9 10
=
~ -20
,,
-10
o
4
:: ..----
-10
.'
o
1 2 3 4 5 6 7 8 9 10
V
siGl.lorisl'""""
V
V
I'" '111M
14
II
-
~
IWAX £lGHT
SfGI.IENp ON
4
10
Vcc(VOLTS)
Output Sink Current for SO
andSK
4
Output Sink Current for La
through L7
DEVlCEd
,2 AND ,4
VOH 2.0V
-40
-30
",
VOH(VOLTS)
LED Output Drive Segment
Drive
-50
IlWCbNE
-30
~ -20
r\
VOH(VOLTS)
1
1
~ IIWCO cc=5. V
O.5H4t-tl-+--+-+-+-II-+~
DrCE d 12 AND
AND DEVICE.
-40
Hl-+-I--+--+-+-+-II-+~
~
LED Output Direct Segment
and Digit Drive
-50
J.
DEVlCEd
,2 AND 14
1
OVcc=4.5
l"- t- ~ ~
o
2.0
f' lW
...... ""IIIIN OIVcc=4.5V
-100
vI/O (VOLTS)
Source Current for SO and SK
IIJ
l"-
-300
o
o
1.0 2.0 3.0 40 5.0 6.0 71J 6.0 9.0
3-500
......
IWI OVCC....•5V
VIN(VOLTS)
1.5
....... -600
-60
'\
-50
1,,\ 1w,U0 Vw 4.sV
-40
t::
~4.5V
-BOO
-70
0
"\ lWAx°vo
J
Source Current for Standard
Output Configuration
DEVICE. 12
"-
,,-10/
,
,
......
IWIN
OL-~--~--~~--~
6
7
8
10
2
Vcc(VOLTS)
o
3
2
120
Output Sink Current Go-G3
and Do-D3
J
100
~ICE
.,1
3
VOL (VOLTS)
VOL (VOLTS)
Output Sink Current IPO-IP7,
PO, P9, SKIP/P10, AD/DATA
2.0...-.,....---,......-----,
AND bll
/
80
1j 1'O~--+---~------~
'1IWC OVcc=4.5V
J
!/
Ii
o
"",,""~
20
o
·r
'!WIN o,Vcc-4 V
I
0.0 L-_ _ _...J...._ _ _ _
2 3 4 5 6 7 8 9 10
OIJ
VOL (VOLTS)
0.5
~
1.0
Vour(VOLTS)
TL/DD/8817-11
FIGURE 6. COP404LSN-5 I/O Characteristics
1-303
Jii
z
I
U1
. r------------------------------------------------------------------------------------,
COP404LSN-5 Instruction Set
U)
Z
~
'IIII:t
o
a..
'IIII:t
o
Table II provides the mnemonic, operand, machine code,
data flow, skip conditions, and description associated with
each instruction in the COP404LSN-5 instruction set.
Table I is a symbol table providing internal architecture, instruction operand and operational symbols used in the instruction set table.
o
TABLE I. COP404LSN-5lnstruction Set Table Symbols
Definition
Symbol
Symbol
Definition
INTERNAL ARCHITECTURE SYMBOLS
INSTRUCTION OPERAND SYMBOLS
A
B
Br
Bd
C
D
EN
G
IL
d
r
IN
IP
L
M
P
PC
Q
SA
S8
SC
SID
SK
4-bit Accumulator
10-bit RAM Address Register
Upper 3 bits of 8 (register address)
Lower 4 bits of 8 (digit address)
1-bit Carry Register
4-bit Data Output Port
4-bit Enable Register
4-bit Register to latch data for G I/O Port
Two 1-bit latches associated with the IN3 or INo
inputs
4-bit Input Port
8-bit bidirectional ROM address and Data Port
8-bit TRI-STATE I/O Port
4-bit contents of RAM Memory pointed to by 8
Register
3-bit ROM Address Register Port
11-bit ROM Address Register (program counter)
8-bit Register to latch data for L I/O Port
11-bit Subroutine Save Register A
11-bit Subroutine Save Register 8
11-bit Subroutine Save Register C
4-bit Shift Register and Counter
Logic-Controlled Clock Output
4-bit Operand Field, 0-15 binary (RAM Digit Select)
3-bit Operand Field, 0-7 binary (RAM Register
Select)
a
11-bit Operand Field, 0-2047 binary (ROM Address)
y
4-bit Operand Field, 0-15 binary (Immediate Data)
RAM(s) Contents of RAM location addressed by s
ROM(t) Contents of ROM location addressed by t
OPERATIONAL SYMBOLS
+
---+
~
=
A
Ell
:
Plus
Minus
Replaces
Is exchanged with
Is equal to
The one's complement of A
Exclusive-OR
Range of values
TABLE II. COP404LSN-5lnstruction Set
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
DataFlow
Skip Conditions
Description
ARITHMETIC INSTRUCTIONS
ASC
30
10011100001
A + C + RAM(8) ---+ A
Carry ---+ C
Carry
Add with Carry, Skip on
Carry
ADD
31
10011100011
A + RAM(8) ---+ A
None
Add RAM toA
ADT
4A
10100110101
A + 1010 ---+ A
None
AddTentoA
5-
10101 1 y 1
A+y---+A
Carry
Add Immediate, Skip on
Carry (y =1= 0)
10
10001100001
A + RAM(8) +C ---+ A
Carry
Complement and Add with
Carry, Skip on Carry
AISC
CASC
y
Carry ---+ C
CLRA
00
10000100001
0---+ A
None
Clear A
COMP
40
10100100001
A---+A
None
One's complement of A to A
NOP
44
10100101001
None
None
No Operation
RC
32
10011100101
"0" ---+ C
None
ResetC
SC
22
10010100101
"1" ---+ C
None
SetC
XOR
02
10000100101
A Ell RAM(8) ---+ A
None
Exclusive-OR RAM with A
1-304
o
o-a
TABLE II. COP404LSN-5lnatructlon Set (Continued)
Mnemonic Operand
~
Machine
Hex
Language Code
Code
(Binary)
Q
DataFlow
Description
Skip Conditions
.
Z
TRANSFER OF CONTROL INSTRUCTIONS
JID
FF
JMP
a
JP
a
6-
----
JSRP
a
--
ROM (PC10:BI A,M) ~
PC7:0
11111111111
10110 1 0 lalo'al a ~ PC
I aZ'O I
111
I
~'o
(pages 2,3 only)
or
1111 aS'O
I
(all other pages)
110 1
I
aS'O
Jump Indirect (Note 2)
None
Jump
None
Jump within Page
(Note 4)
None
Jump to Subroutine Page
(Note 5)
+1
~ SA ~ SB
SC
00010 ~ PC10:6
a ~ PCs:o
PC
None
Jump to Subroutine
~
10100110001
SC
~
10100110011
SC ~ SB ~ SA ~ PC Always Skip on Return
Return from Subroutine
then Skip
1011011 lalO'al
I aZ'O I
RET
48
RETSK
49
U1
a ~ PCs:o
+
6-
a
a ~ PC6:0
None
PC
--
JSR
~
{ii
1 ~
~ SC
a ~ PC
SB
SA ~ SB
~
SA
~
PC None
Return from Subroutine
MEMORY REFERENCE INSTRUCTIONS
CAMO
33
3C
10011100111
10011111001
A ~ 07:4
RAM (B) ~ 03:0
None
Copy A, RAM to a
COMA
33
2C
10011100111
1001011100 I
07:4 ~ RAM(B)
None
Copy a to RAM, A
-5
100lrl01011
(r - 0:3)
RAM (B) ~ A
Br e r ~ Br
None
Load RAM into A,
Exclusive-OR Br with r
23
1001010011
10 1 r I d
RAM(r,d) ~ A
None
Load A with RAM pointed
to directly by r,d
BF
I
I
11011 11111 I
ROM(PC10:B.A,M) ~ a
SB ~ SC
None
Load a Indirect (Note 3)
LD
r
LDD
r,d
LaiD
--
03:0~A
RMB
0
1
2
3
4C
45
42
43
1010011100 I
1010010101 I
10100100101
10100100111
o~
o~
o~
o~
RAM(B)o
RAM(B)1
RAM(B)2
RAM(Bb
None
Reset RAM Bit
5MB
0
1
2
3
40
47
46
4B
10100111011
1010010111 I
10100101101
10100110111
1
1
1
1
~
~
~
~
RAM(B)o
RAM(Bh
RAM(B)2
RAM(Bb
None
Set RAM Bit
STII
y
7-
10111 1
y ~ RAM(B)
Bd + 1 ~ Bd
None
Store Memory Immediate
and Increment Bd
X
r
-6
100lrl 0110 1
(r = 0:3)
RAM (B)
6V
Voltage at any Pin
-0.3V to Vee + 0.3V
ESO Susceptibility (Note 4)
2000V
Total Current into Vee Pin (Source)
40mA
co
a..
o
......
o
C'\I
o
DC Electrical Characteristics
C'\I
Operating Voltage
Power Supply Ripple (Note 1)
co
a..
oo
......
o
,...
C'\I
co
a..
o
o
......
o
Q
C'\I
co
a..
o
......
o
oC'\I
"'I:t'
CD
a..
oo
......
o
,...
"'I:t'
CD
a..
o
......
o
oQ
"'I:t'
CD
a..
o
o
......
o
C'\I
C'\I
CD
a..
o
o
......
o
,...
C'\I
CD
a..
oo
......
oQ
C'\I
CD
a..
oo
Parameter
Supply Current
High Speed Mode, CKI = 18 MHz
Normal Mode, CKI = 4.5 MHz
(Note 2)
HALT Current
(Note 3)
-55°C ~ TA ~ + 125°C unless otherwise specified
Condition
Peak to Peak
Vee
Vee
= 5.5V, tc = 1.1 /Ls
= 5.5V, tc = 2.2/Ls
Vee
= 5.5V, CKI = 0 MHz
Units
5.5
0.1 Vee
V
V
15
5
mA
mA
/LA
0.1 Vee
V
V
0.2 Vee
V
V
0.9 Vee
0.7 Vee
Vee
Vee
= 5.5V, VIN = OV
= 4.5V, VIN = OV
-5
35
+5
300
0.05 Vee
Vee
Vee
= 4.5V, VOH = 3.8V
= 4.5V, VOL = 1.0V
0.35
9
Vee
Vee
Vee
= 4.5V, VOH = 3.2V
= 4.5V, VOH = 3.8V
= 4.5V, VOL = O.4V
9
0.35
1.4
-5.0
120
Maximum Input Current (Room Temp)
Without Latchup (Note 5)
500 ns Rise and
Fall Time (Min)
+5.0
/LA
mA
mA
/LA
12
2.5
mA
mA
±100
mA
7
pF
V
2.5
Input Capacitance
/LA
/LA
V
mA
mA
Allowable Sink/Source
Current Per Pin
o Outputs (Sink)
All Others
RAM Retention Voltage, Vr
Max
<10
G Port Input Hysteresis
Output Current Levels
o Outputs
Source
Sink
All Others
Source (Weak Pull-Up)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
Typ
4.5
Input Levels
RESET, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage
Input Pullup Current
Min
pF
1000
Load Capacitance on 02
Rate of voltage change must be less than 0.5V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave eKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee, Land G ports TRI·STATE
and tied to ground, all outputs low and tied to ground.
Note 4: Human body mode, 100 pF through 1500fi.
Note 5: Except pins 3, 4, 24
pins 3,24:
+60 rnA
pin 4:
-25 rnA
Note 1:
2-10
o
o"0
COP620C/COP621C/COP622C/COP640C/COP641C/COP642C
AC Electrical Characteristics
Parameter
N
-55°C
o
< TA < + 125°C unless otherwise specified
Condition
Instruction Cycle Time (tc)
High Speed Mode
(Div-by20)
Normal Mode
(Div-by 10)
0')
Min
Typ
Max
Units
o
.......
o
o"0
Vee ~ 4.5V
1.1
DC
p,s
Vee ~ 4.5V
2.2
DC
p,s
o
.......
fr = Max (-:- 20 Mode)
33
66
%
o"0
12
8
ns
ns
0')
N
.....
o
CKI Clock Duty Cycle
(Note 6)
Rise Time (Note 6)
Fall Time (Note 6)
0')
fr = 18 MHz Ext Clock
fr = 18 MHz Ext Clock
N
N
o.......
o
Inputs
tSETUP
tHOLO
Vee ~ 4.5V
Vee ~ 4.5V
Output Propagation Delay
tp01. tpoo
SO.SK
All Others
220
66
ns
ns
o"0
0')
0I:loo
o
RL = 2.2k. CL = 100 pF
Vee ~ 4.5V
Vee ~ 4.5V
0.8
1.1
p,s
p,s
o
.......
o
o"0
MICROWIRE Setup Time
tuws
20
ns
MICROWIRE Hold Time
tUWH
56
ns
o
.......
ns
o"0
MICROWIRE Output Valid
Timetuv
220
0')
0I:loo
.....
o
0')
0I:loo
N
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
te
te
Reset Pulse Width
1
o
.......
o
o"0
tc
CD
N
te
p,s
o
Note 6: Parameter sampled but not 100% tested.
o
.......
AC Electrical Characteristics in ROMless Mode -55°C < TA < + 125°C unless otherwise specified
o"0
Parameter
Instruction Cycle Time (tc)
High Speed Mode
(Div-by 20)
Normal Mode
(Div-by 10)
o
Min
Typ
Max
Units
Vee ~ 4.5V
2.2
DC
p,s
Vee ~ 4.5V
4.4
DC
p,s
60
24
16
%
ns
ns
440
132
ns
ns
1.55
2.2
p,s
p,s
Condition
CKI Clock Duty Clock
Rise Time
Fall Time
fr = Max (-:- 20 Mode)
fr = 9 MHz Ext Clock
fr = 9 MHz Ext Clock
Inputs
tSETUP
tHOLO
Vee ~ 4.5V
Vee ~ 4.5V
Output Propagation Delay
tp01. tpoo
SO.SK
All Others
Vee ~ 4.5V
Vee ~ 4.5V
40
RL = 2.2k. CL = 100 pF
Minimum Pulse Width
Interrupt Input
Timer Input
tc
Reset Pulse Width
1
CD
N
.....
o
.......
o
o"0
~.
.......
o
o
"0
CD
0I:loo
o
o
.......
o
o"0
CD
0I:loo
.....
o
.......
o
o"0
tc
p,s
CD
0I:loo
N
o
2-11
o
N
-.::t
co
a..
o
o
.......
o
.....
-.::t
co
a..
o
o
.......
o
Q
CKI
(+20IotOOE)
CKI--.J
(+ 10 IotOOE) .
1
-l tpDO
r-______-l1""----......
Ir
-JI
tpDl
\~
11 (XLD)
~--tP-Dl-Ir----------------
-.::t
co
a..
o
o.......
o
N
N
co
a..
o
o
.......
o.....
N
co
a..
o
.......
o
Q
I
12 (PHI)
------------------~-I tpDl I00,01,03
_______________________-Jl"---------~______
l
--Ixxxx
t
SETUP
IO,13 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
TL/DD/9103-2
FIGURE 2a. AC Timing Diagrams In ROM less Mode
o
SK
N
co
a..
o
.......
o
N
tuwh
SI
-.::t
CD
a..
o
o.......
o
.....
tl=c
uws
o
so
----~~C
TL/DD/9103-19
FIGURE 2b. MICROWIRE/PLUS Timing
-.::t
CD
a..
oo
.......
o
Q
-.::t
CD
a..
o
o
.......
o
N
N
CD
a..
o
o
.......
o
.....
N
CD
a..
o
o.......
oQ
N
CD
a..
o
o
2-12
o
a
Connection Diagrams
"eno
N
DUAL-IN-LiNE PACKAGE
20 DIP
24DIP
o
......
o
28 DIP
a
G-4/S0
G3/T10
G-4/S0
G3/T10
G4/S0
G3/T10
G5/SK
G2
G5/SK
G2
G5/SK
G2
"en
G6/SI
GI
G6/SI
GI
G6/SI
GI
...a.
G7/CKO
GO/INT
CKI
VCC
G7/CKO
GO/I NT
RESET
CKI
RESET
GNO
VCC
GNO
G7/CKO
GO/INT
CKI
GNO
a
en
L7
10
03
10
03
LI
L6
13
DO
II
02
L2
L5
LO
L7
12
01
L3
L-4
LI
L6
13
DO
L2
L5
LO
L7
L-4
L1
TL/DD/9103-3
Order Number COP822C-XXX/D,
COP822C-XXX/N, COP842C-XXX/D
or COP842C-XXX/N
See NS Package Number
D20Aor N20A
L3
12
13
TLlDD/9103-4
Order Number COP821C-XXX/D,
COP821C-XXXIN, COP841C-XXX/D
or COP841C-XXX/N
See NS Package Number
D24C or N24A
o
RESET
VCC
LO
Top View
N
o
......
"
N
N
o
......
o
a
"en
L6
L2
13
16
L5
L3
1-4
15
L4
oI:ao
o
o
......
o
TL/DD/9103-5
Order Number COP820C-XXX/D,
COP820C-XXXIN, COP840C-XXX/D
or COP840C-XXX/N
See NS Package Number
D28C orN28B
a
"en
oI:ao
...a.
o
......
o
a
"en
SURFACE MOUNT
oI:ao
20 SO Wide
N
28 PLCC
24 SO Wide
o
......
o
G-4/S0
20
G3/T10
G-4/S0
2-4
G3/T10
G5/SK
19
G2
G5/SK
23
G2
G6/SI
22
GI
G7/CKO
21
GO/I NT
GO/INT
CKI
RESET
RESET
Vee
10
G6/SI
GI
G7/CKO
GO/INT
CKI
RESET
VCC
GNO
CKI
VCC
GNO
a
GNO
LO
L7
10
03
03
II
LI
L6
13
DO
02
12
L2
L5
LO
L7
01
L-4
L1
L6
DO
L2
L5
L3
II
10
TL/DD/9103-3
Top View
Order Number COP822C-XXX/WM
or COP842C-XXX/WM
See NS Package Number M20B
L3
12
13
10
LO
TL/DD/9103-4
TL/DD/9103-18
Order Number COP820C-XXX/V or
COP840C-XXX/V
See NS Package Number V28A
GNO
VCC
VCC
CKI
GNO
GNO
CKI
CKI
RESET
RESET
INTR
CKO
t.lICROWIRE/PLUS
TL/DD/9103-7
FIGURE 3
2-13
"en
N
...a.
o
......
"
~.
......
o
a
oI:ao
o
o
......
PORT II\ .._ _~
PORTI", .._ _~
TL/DD/9103-6
a
"en
COP820C
COP840C
VCC
INTR
CKO
t.lICROWIRE/PLUS
o
o
......
o
o
COP821C
COP841C
RESET
N
a
L-4
Order Number COP821C-XXX/WM
or COP841C-XXX/WM
See NS Package Number M24B
COP822C
13
"en
o
a
"en
oI:ao
...a.
o
......
o
a
INTR
CKO
t.lICROWIRE/PLUS
TLlDD/9103-8
"en
oI:ao
N
o
o
N
'II:t
Pin Descriptions
Functional Description
D..
Vee and GND are the power supply pins.
o
......
o
,...
CKI is the clock input. This can come from an external
source, a R/C generated oscillator or a crystal (in conjunction with CKO). See Oscillator description.
Figure 1 shows the block diagram of the internal architecture. Data paths are illustrated in simplified form to depict
how the various logic elements communicate with each other in implementing the instruction set of the device.
co
o
'II:t
co
RESET is the master reset input. See Reset description.
ALU AND CPU REGISTERS
o
PORT I is a four bit Hi-Z input port.
The AlU can do an 8-bit addition, subtraction, logical or
shift operation in one cycle time.
D..
o
......
oo
'II:t
CO
D..
oo
......
PORT L is an 8-bit I/O port .
There are five CPU registers:
There are two registers associated with each L I/O port: a
data register and a configuration register. Therefore, each L
I/O bit can be individually configured under software control
as shown below:
A is the 15-bit Program Counter register
PU is the upper 7 bits of the program counter (PC)
Pl is the lower 8 bits of the program counter (PC)
oN
Port L
Config_
Port L
Data
Port L
Setup
S is the 8-bit address register, can be auto incremented or
decremented.
co
a
a
a
X is the 8-bit alternate address register, can be incremented
or decremented.
1
1
a
Hi-Z Input (TRI-STATE)
Input With Weak Pull-Up
Push-Pull "0" Output
Push-Pull "1" Output
N
D..
oo
......
o,...
N
co
D..
o
o
......
oo
N
CO
D..
o
o
......
o
N
'II:t
CD
D..
1
1
PORT G is an 8-bit port with 6 I/O pins (GO-G5) and 2 input
pins (G6, G7). All eight G-pins have Schmitt Triggers on the
inputs. The G7 pin functions as an input pin under normal
operation and as the continue pin to exit the HALT mode.
There are two registers with each I/O port: a data register
and a configuration register. Therefore, each I/O bit can be
individually configured under software control as shown below.
PortG
Data
PortG
Setup
a
a
a
'II:t
CD
o
1
1
a
Hi-Z Input (TRI-STATE)
Input With Weak Pull-Up
Push-Pull "0" Output
Push-Pull "1 " Output
D..
o......
oo
'II:t
CD
D..
oo
......
o
N
N
CD
D..
o
S, X and SP registers are mapped into the on chip RAM.
The S and X registers are used to address the on chip RAM.
The SP register is used to address the program counter
stack in RAM during subroutine calls and returns .
Three data memory address locations are allocated for
these ports, one for data register, one for configuration register and one for the input pins.
PortG
Config.
o
o
......
o
,...
SP is the 8-bit stack pointer, points to subroutine stack (in
RAM).
1
1
PROGRAM MEMORY
Program memory for the COP820C consists of 1024 bytes
of ROM (2048 bytes of ROM for the COP840C). These
bytes may hold program instructions or constant data. The
program memory is addressed by the 15-bit program counter (PC). ROM can be indirectly read by the lAID instruction
for table lookup.
DATA MEMORY
The data memory address space includes on chip RAM, I/O
and registers. Data memory is addressed directly by the instruction or indirectly by the S, X and SP registers.
The COP820C has 64 bytes of RAM and the COP840C has
128 bytes of RAM. Sixteen bytes of RAM are mapped as
"registers" that can be loaded immediately, decremented or
tested. Three specific registers: S, X and SP are mapped
into this space, the other bytes are available for general
usage.
Three data memory address locations are allocated for
these ports, one for data register, one for configuration register and one for the input pins. Since G6 and G7 are input
only pins, any attempt by the user to set them up as outputs
by writing a one to the configuration register will be disregarded. Reading the G6 and G7 configuration bits will return
zeros. Note that the chip will be placed in the HALT mode
by setting the G7 data bit.
The instruction set of the COP800C permits any bit in memory to be set, reset or tested. All I/O and registers on the
COP800C (except the A & PC) are memory mapped; therefore, I/O bits and register bits can be directly and individually set, reset and tested.
Six bits of Port G have alternate features:
o
......
RESET
GO INTR (an external interrupt)
o
,...
G3 TIO (timer/counter input/output)
N
G4 SO (MICROWIRE serial data output)
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the ports land G are placed
in the TRI-STATE mode and the Port D is set high. The PC,
PSW and CNTRl registers are cleared. The data and configuration registers for Ports L & G are cleared .
CD
D..
o
G5 SK (MICROWIRE clock I/O)
o
......
G6 SI (MICROWIRE serial data input)
oo
G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input (general purpose input)
D..
Pins G1 and G2 currently do not have any alternate functions.
N
CD
o
o
The external RC network shown in Figure 4 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes. It is recommended that the
components of the RC network be selected to provide a
RESET delay of at least five times the power supply rise
time or the minimum RESET pulse width, whichever is
greater.
PORT D is a four bit output port that is set high when RESET goes low.
The D2 pin is sampled at reset. If it is held low at reset the
COP820C enters the ROMless mode of operation.
2-14
o
a-a
Functional Description (Continued)
p +-
......... . - - - - . , .
~
.. ~
~
s
~t-
en
N
<:)
VCC
:~ .~
u
p
Y - -
CKO
.... ~2...
GND
---_--11
...
" ...
~
....
~ ~ Rt
:~
TLIDD/9103-9
CKI
t
OSCILLATOR CIRCUITS
~-....
a-a
REstRT
N
.....
.Jl.J
o
N
N
o
.......
C
CKI
I ..
A. CRYSTAL OSCILLATOR
CKO
! .......
.J- ..........
Vcc
J
RESTART
~c
Table I shows the component values required for various
standard crystal values.
TLIDD/9103-10
B. EXTERNAL OSCILLATOR
FIGURE 5. Crystal and R-C Connection Diagrams
CKI can be driven by an external clock signal. CKO is available as a general purpose input and/or HALT restart control.
MASK OPTIONS
The COP820C and COP840C can be driven by clock inputs
between DC and 20 MHz. For low input clock frequencies
(::;; 5 MHz) the instruction cycle frequency can be selected
to be the input clock frequency divided by 10. This mode is
known as the Normal Mode.
For oscillator frequencies that are greater than 5 MHz the
chip must run with a divide by 20. This is known as the High
Speed mode.
C. RIC OSCILLATOR
CKI is configured as a single pin RC controlled Schmitt trigger oscillator. CKO is available as a general purpose input
and/ or HALT restart control.
Table II shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
o
.......
a-a
"::"
The COP800C can be driven by a crystal clock. The crystal
network is connected between the pins CKI and CKO.
en
en
::!C2
Figure 5 shows the three clock oscillator configurations
available for the COP820C and COP840C.
CKO
EXTERNAL
CLOCK
~::-1DI-:.
fct
FIGURE 4. Recommended Reset Circuit
o
B
A
CKI
p:::r::
L
o
.......
o
a-a
en
~
<:)
o
.......
o
a-a
en
~
.....
o
.......
o
a-a
en
~
N
o
.......
o
a-a
Q)
N
<:)
o
.......
TABLE I. Crystal Oscillator Configuration, T A = 25°C
o
R1
(kn)
R2
(MO)
C1
(pF)
C2
(pF)
CKI Freq
(MHz)
Conditions
0
0
0
0
1
1
1
1
30
30
30
200
30-36
30-36
30-36
100-150
20
10
4
0.455
Vee = 5V
Vee = 5V
Vee = 2.5V
Vee = 2.5V
a-a
Q)
N
.....
o
.......
o
a-a
~
.......
o
TABLE II. RC Oscillator Configuration, TA = 25°C
R
(kn)
C
(pF)
CKI Freq.
(MHz)
Instr. Cycle
(IlS)
Conditions
3.3
5.6
6.8
82
100
100
2.8 to 2.2
1.5 to 1.1
1.1 to 0.8
3 to 6
6 to 11
7.5 to 18
Vee = 5V
Vee = 5V
Vee = 2.5V
a-a
Q)
~
<:)
o
.......
o
a-a
Q)
~
.....
o
.......
o
a-a
Q)
~
N
o
2-15
•
or-----------------------------------------------------------~
N
~
Functional Description
C-
The COP820C and COP840C microcontrollers have five
mask options for configuring the clock input. The CKI and
CKO pins are automatically configured upon selecting a particular option.
co
oo
......
o
,...
~
co
-
C-
O
o
......
o
o
-
(Continued)
High Speed Crystal (CKI/20) CKO for crystal configuration
Normal Mode Crystal (CKI/10) CKO for crystal configuration
-
High Speed External (CKI/20) CKO available as G7 input
O
-
Normal Mode External (CKI/10) CKO available as G7
input
o
N
-
RIC (CKI/10) CKO available as G7 input
~
CO
C-
o......
N
co
O
C-
ler and retains all information until continuing. In the HALT
mode, power requirements are minimal as it draws only
leakage currents and output current. The applied voltage
(Ved may be decreased down to Vr (minimum RAM retention voltage) without altering the state of the machine.
There are two ways to exit the HALT mode: via the RESET
or by the CKO pin. A low on the RESET line reinitializes the
microcontroller and start executing from the address
OOOOH. A low to high transition on the CKO pin causes the
micro controller to continue with no reinitialization from the
address following the HALT instruction.
INTERRUPTS
The COP820C and COP840C have a sophisticated interrupt
structure to allow easy interface to the real word. There are
three possible interrupt sources, as shown below.
G7 can be used either as a general purpose input or as a
control input to continue from the HALT mode.
CURRENT DRAIN
A maskable interrupt on external GO input (positive or negative edge sensitive under software control)
The total current drain of the chip depends on:
1) Oscillator operating mode-11
A maskable interrupt on timer carry or timer capture
A non-maskable software/error interrupt on opcode zero
C-
2) Internal switching current-12
o
......
3) Internal leakage current-13
INTERRUPT CONTROL
The GIE (global interrupt enable) bit enables the interrupt
function. This is used in conjunction with ENI and ENTI to
select one or both of the interrupt sources. This bit is reset
when interrupt is acknowledged.
ENI and ENTI bits select external and timer interrupt respectively. Thus the user can select either or both sources
to interrupt the microcontroller when GIE is enabled.
IEDG selects the external interrupt edge (0 = rising edge, 1
= falling edge). The user can get an interrupt on both rising
and falling edges by toggling the state of IEDG bit after each
interrupt.
o
......
o,...
N
co
O
o
o
4) Output source current-14
C-
5) DC current caused by external input not at Vee or GND15
Thus the total current drain, It is given as
o
......
o
N
It = 11 + 12 + 13 + 14 + 15
To reduce the total current drain, each of the above components must be minimum.
CD
The chip will draw the least current when in the normal
mode. The high speed mode will draw additional current.
The RIC mode will draw the most. Operating with a crystal
network will draw more current than an external squarewave. Switching current, governed by the equation below,
can be reduced by lowering voltage and frequency. Leakage current can be reduced by lowering voltage and temperature. The other two items can be reduced by carefully
designing the end-user's system.
N
CO
O
~
C-
O
o
......
o
,...
~
CD
C-
O
o
......
o
o
~
The software interrupt does not reset the GIE bit. This
means that the controller can be interrupted by other interrupt sources while servicing the software interrupt.
12 = C x V x f
CD
Where
O
C = equivalent capacitance of the chip.
C-
o
......
o
N
N
CD
IPND and TPND bits signal which interrupt is pending. After
interrupt is acknowledged, the user can check these two
bits to determine which interrupt is pending. This permits the
interrupts to be prioritized under software. The pending flags
have to be cleared by the user. Setting the GIE bit high
inside the interrupt subroutine allows nested interrupts.
INTERRUPT PROCESSING
V = operating voltage
The interrupt, once acknowledged, pushes the program
counter (PC) onto the stack and the stack pOinter (SP) is
decremented twice. The Global Interrupt Enable (GIE) bit is
reset to disable further interrupts. The microcontroller then
vectors to the address OOFFH and continues from that address. This process takes 7 cycles to complete. At the end
of the interrupt subroutine, any of the following three instructions return the processor back to the main program: RET,
RETSK or RET!. Either one of the three instructions will pop
the stack into the program counter (PC). The stack pointer
is then incremented twice. The RETI instruction additionally
sets the GIE bit to re-enable further interrupts.
f = CKI frequency
Some sample current drain values at Vee = 6Vare:
C-
O
o
......
o
,...
N
CD
C-
O
o
......
oo
N
CD
C-
O
o
CKI (MHz)
Inst. Cycle (j.Ls)
It (mA)
20
3.58
2
0.3
o (HALT)
1
3
5
33
9
2.2
1.2
0.2
<0.0001
-
HALT MODE
Either of the three instructions can be used to return from a
hardware interrupt subroutine. The RETSK instruction
should be used when returning from a software interrupt
subroutine to avoid entering an infinite loop.
The COP820C and COP840C support a power saving mode
of operation: HALT. The controller is placed in the HALT
mode by setting the G7 data bit, alternatively the user can
stop the clock input. In the HALT mode all internal processor activities including the clock oscillator are stopped. The
fully static architecture freezes the state of the control-
2-16
(')
Functional Description
o
(Continued)
"tJ
0)
I\)
o
(')
.......
(')
EXTERNAL
INT. PIN
o
"tJ
0)
I\)
-'"
(')
TO
INTERRUPT
LOGIC
TIMER
UNDERFLOW - - - - 4
.......
(')
o
"tJ
SOFTWARE--------------~
TL/DD/9103-11
FIGURE 6. Interrupt Block Diagram
(')
DETECTION OF ILLEGAL CONDITIONS
.......
TABLE III
The COP820C and COP840C incorporate a hardware
mechanism that allows it to detect illegal conditions which
may occur from coding errors, noise and 'brown out' voltage
drop situations. Specifically it detects cases of executing out
of undefined ROM area and unbalanced stack situations.
Reading an undefined ROM location returns 00 (hexadecimal) as its contents. The opcode for a software interrupt is
also '00'. Thus a program accessing undefined ROM will
cause a software interrupt.
(')
S1
SO
SK Cycle Time
0
0
1
0
1
x
2te
4te
8te
where,
te is the instruction cycle clock.
Reading an undefined RAM location returns an FF (hexadecimal). The subroutine stack on the COP820C and
COP840C grows down for each subroutine call. By initializing the stack pointer to the top of RAM, the first unbalanced
return instruction will cause the stack pointer to address
undefined RAM. As a result the program will attempt to execute from FFFF (hexadecimal), which is an undefined ROM
location and will trigger a software interrupt.
MICROWIRE/PLUSTM
MICROWIRE/PlUS is a serial synchronous communications interface. The MICROWIRE/PlUS capability enables
the COP820C and COP840C to interface with any of National Semiconductor's MICROWIRE peripherals (Le. AID converters, display drivers, EEPROMS, etc.) and with other microcontrollers which support the MICROWIRE interface. It
consists of an 8-bit serial shift register (SIO) with serial data
input (SI), serial data output (SO) and serial shift clock (SK).
Figure 7 shows the block diagram of the MICROWIREI
PLUS interface.
The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIRE
arrangement with the internal clock source is called the
Master mode of operation. Similarly, operating the MICROWIRE arrangement with an external shift clock is called the
Slave mode of operation.
The CNTRl register is used to configure and control the
MICROWIRE mode. To use the MICROWIRE, the MSEl bit
in the CNTRl register is set to one. The SK clock rate is
selected by the two bits, SO and S1, in the CNTRl register.
Table III details the different clock rates that may be selected.
0)
I\)
I\)
o"tJ
0)
.I:loo
o
(')
.......
(')
o
"tJ
0)
.I:loo
-'"
(')
MICROWIRE PLUS OPERATION
.......
Setting the BUSY bit in the PSW register causes the Microwire arrangement to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift.
The COP820C and COP840C may enter the MICROWIREI
PLUS mode either as a Master or as a Slave. Figure 8
shows how two COP820C microcontrollers and several peripherals may be interconnected using the MICROWIREI
PLUS arrangement.
o
(')
"tJ
0)
.I:loo
I\)
(')
.......
(')
o"tJ
CD
I\)
o
(')
Master MICROWIRE/PLUS Operation
.......
In the MICROWIRE/PlUS Master mode of operation the
shift clock (SK) is generated internally by the COP820C.
The MICROWIRE Master always initiates all data exchanges. (See Figure 8). The MSEl bit in the CNTRl register
must be set to enable the SO and SK functions onto the G
Port. The SO and SK pins must also be selected as outputs
by setting appropriate bits in the Port G configuration register. Table IV summaries the bit settings required for Master
mode of operation.
o
SLAVE MICROWIRE/PLUS OPERATION
In the MICROWIRE/PlUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEl
bit in the CNTRl register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bit in the Port G configuration register. Table IV summarizes the settings required to enter the
Slave mode of operation.
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by
the Master will be shifted properly. After eight clock pulses
the BUSY flag will be cleared and the sequence may be
repeated. (See Figure 8.)
.......
(')
"tJ
CD
I\)
-'"
(')
.......
(')
o"tJ
~.
(')
o"tJ
CD
.I:loo
o
(')
.......
(')
o"tJ
CD
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-'"
(')
.......
(')
o"tJ
CD
.I:loo
I\)
(')
2-17
o
C\I
~
co
Functional Description
D.
o
o
......
o,...
~
co
G4
GS
G4
GS
GS
Fun.
Fun.
Fun.
SO
Int.SK
SI
MICROWIRE Master
TRI·STATE Int.SK
SI
MICROWIRE Master
Ext. SK
SI
MICROWIRE Slave
TRI·STATE Ext.SK
SI
MICROWIRE Slave
Conflg. Conflg.
Bit
Bit
D.
o
1
1
0
1
~
1
0
D.
0
0
o
......
o
o
co
oo
......
o
C\I
C\I
co
D.
o
o
......
o
,...
C\I
co
(Continued)
TABLE IV
SO
MODE 1. TIMER WITH AUTO· LOAD REGISTER
In this mode of operation the timer T1 counts down at the
instruction cycle rate. Upon underflow the value in the register R1 gets automatically reloaded into the timer which continues to count down. The timer underflow can be programmed to interrupt the microcontroller. A bit in the control
register CNTRL enables the TIO (G3) pin to toggle upon
timer underflows. This allow the generation of square-wave
outputs or pulse width modulated outputs under software
control. (See Figure !J)
Operation
MODE 2. EXTERNAL COUNTER
In this mode, the timer T1 becomes a 16-bit external event
counter. The counter counts down upon an edge on the TIO
pin. Control bits in the register CNTRL program the counter
to decrement either on a positive edge or on a negative
edge. Upon underflow the contents of the register R1 are
automatically copied into the counter. The underflow can
also be programmed to generate an interrupt. (See Figure !J)
TIMER/COUNTER
The COP820C and COP840C have a powerful 16-bit timer
with an associated 16·bit register enabling them to perform
extensive timer functions. The timer T1 and its register R1
are each organized as two 8-bit read/write registers. Control
bits in the register CNTRL allow the timer to be started and
stopped under software control. The timer-register pair can
be operated in one of three possible mpdes.
D.
MODE 3. TIMER WITH CAPTURE REGISTER
r-------------------------~SO
oo
......
Timer T1 can be used to precisely measure external frequencies or events in this mode of operation. The timer T1
counts down at the instruction cycle rate. Upon the occurrence of a specified edge on the TIO pin the contents of the
timer T1 are copied into the register R1. Bits in the control
register CNTRL allow the trigger edge to be specified either
as a positive edge or as a negative edge. In this mode the
user can elect to be interrupt,ed on the specified trigger
edge. (See Figure 10.)
I+-----SI
oo
C\I
co
D.
oo
......
o
C\I
~
co
D.
o
o
......
o
,...
TL/DD/9103-12
FIGURE 7. MICROWIRE Block Diagram
~
co
D.
oo
CHIP SELECT LINES
......
o
o
~
co
D.
oo
......
oC\I
C\I
co
D.
o
~
COPS
(MASTER)
C\I
co
SI
o
so
o
......
o
o
C\I
co
D.
o
1
8-BIT
AID CONVERTER
COP43X
1024- BIT
EEPROM
COP495
I/O
o
......
o
,...
D.
!
! f,A
1
! fA
1
1
1
..
LOW
POWER
CMOS
RAM
& TIMER
COP498
! f
1
FREQ.
GEN. &
COUNTER
COP452L
II'
!1
1
I/o
LINES
VF
DISPLAY
DRIVER
COP470
f
1
COPS
(SLAVE)
~
~
so
SI
SK
SK
TLlDD/9103-13
FIGURE 8. Mlcrowlre Application
o
2-18
Functional Description
o
o
(Continued)
"C
Ol
N
o
TABLE V. Timer Operating Modes
CNTRl
Bits
Operation Mode
T Interrupt
External Counter W / Auto-Load Reg.
External Counter W / Auto-Load Reg.
Not Allowed
Not Allowed
Timer W / Auto-Load Reg.
Timer W / Auto-Load Reg.lToggle TID Out
Timer W /Capture Register
Timer W/Capture Register
Timer Carry
Timer Carry
Not Allowed
Not Allowed
Timer Carry
Timer Carry
TID Pos. Edge
TID Neg. Edge
Timer
Counts
On
765
000
001
010
01 1
100
1 01
110
111
TID Pos. Edge
TID Neg. Edge
Not Allowed
Not Allowed
o
'"
o
o"C
Ol
N
.....
o
'"
o
o"C
Ol
N
N
tc
tc
tc
tc
o
o
'"
o
"C
Ol
~
TIMER PWM APPLICATION
Figure 11 shows how a minimal component 0/ A converter
can be built out of the Timer-Register pair in the Auto-Reload mode. The timer is placed in the "Timer with auto reload" mode and the TID pin is selected as the timer output.
At the outset the TID pin is set high, the timer T1 holds the
on time and the register R1 holds the signal off time. Setting
TRUN bit starts the timer which counts down at the instruction cycle rate. The underflow toggles the TID output and
copies the off time into the timer, which continues to run. By
alternately loading in the on time and the off time at each
successive interrupt a PWM frequency can be easily generated.
CARRY FLAG/
OUTPUT!
INTERRUPT
TLIDD/9103-15
FIGURE 9. Timer/Counter Auto
Reload Mode Block Diagram
_ _ _....r-----t
'
Ton
1
..._Toff
_- ,
C
TIO-.........-i~
o
P
/
TIO
t?~
A SIMPLE D- A
CONVERTER USING
THE TIMER TO
GENERATE A PWM
OUTPUT.
TL/DD/9103-16
FIGURE 11. Timer Application
TL/DD/9103-14
FIGURE 10. Timer Capture Mode Block Diagram
o
o
o
'"
o
"C
Ol
~
.....
o
o
'"
o
"C
Ol
~
N
o
o
'"
o
"C
(X)
N
o
o
o
'"
o
"C
(X)
N
.....
o
o
'"
o"C
~.
o
'"
o
"C
(X)
~
o
o
o
'"
o
"C
(X)
~
.....
o
o
'"
o"C
(X)
~
N
o
2-19
o
N
"1:1'
co
D..
oo
Control Registers
Addressl
CNTRl REGISTER (ADDRESS X'OOEE)
COP820C
Contents
.......
The Timer and MICROWIRE control register contains the
following bits:
00 to 2F Ion Chip RAM Bytes
"1:1'
S1 & SO Select the MICROWIRE clock divide-by
30 to 7F I Unused RAM Address Space (Reads as all Ones)
D..
IEDG
External interrupt edge polarity select
COP840C
(0 = rising edge, 1 = falling edge)
00 to 6F Ion Chip RAM Bytes
70 to 7F Unused RAM Address Space (Reads as all Ones)
o,...
co
oo
.......
MSEl
Enable MICROWIRE functions SO and SK
TRUN
Start/Stop the Timer/Counter (1 =
stop)
oo
TC3
Timer input edge polarity select (0 = rising edge,
1 = falling edge)
o
N
TC2
Selects the capture mode
TC1
Selects the timer mode
o
o
"1:1'
CO
D..
.......
N
co
D..
o
o
.......
o,...
N
run, 0 =
I TC1 I TC2 I TC3 I TRUN I MSEl IIEOG I S1 I
BIT7
oo
GIE
Global interrupt enable
oo
ENI
External interrupt enable
BUSY MICROWIRE busy shifting
N
CO
IPNO
ENTI
o.......
TPNO Timer interrupt pending
"1:1'
CD
HC
o
N
C
D..
I HC
o
o
.......
o
,...
SO
~O-OF
External interrupt pending
D..
o
Timer interrupt enable
Carry Flag
Half carry Flag
I C I TPNO I ENTI IIPNO I BUSY I ENI I GIE
Bit7
BitO
"1:1'
CD
Operating Modes
oo
These controllers have two operating modes: Single Chip
mode and the ROM less mode. The operating mode is determined by the state of the 02 pin at power on reset.
D..
.......
oo
"1:1'
CD
D..
o
o
.......
oN
N
CD
D..
oo
.......
o
,...
N
CD
D..
oo
.......
o
o
N
CD
D..
oo
DO to OF
DO
01
02
03
D4
05
06
07
08-0B
DC
PSW REGISTER (ADDRESS X'OOEF)
The PSW register contains the following select bits:
.......
80 to BF Expansion Space for on Chip EERAM
CO to CF Expansion Space for I/O and Registers
BITO
co
D..
COP820C and COP840C
SINGLE CHIP MODE
In the Single Chip mode, the controller functions as a self
contained microcontroller. It can address internal RAM and
ROM. All ports configured as memory mapped I/O ports.
On Chip I/O and Registers
Port l Data Register
Port l Configuration Register
Port l Input Pins (Read Only)
Reserved for Port l
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Reserved for Port C
Port 0 Data Register
Reserved for Port 0
EO to EF
EO-E7
E8
E9
EA
EB
EC
ED
EE
EF
On Chip Functions and Registers
Reserved for Future Parts
Reserved
MICROWIRE Shift Register
Timer lower Byte
Timer Upper Byte
Timer Autoload Register lower Byte
Timer Autoload Register Upper Byte
CNTRl Control Register
PSW Register
FOto FF
FC
FO
FE
On Chip RAM Mapped as Registers
X Register
SP Register
B Register
Reading unused memory locations below 7FH will return all
ones. Reading other unused memory locations will return
undefined data.
ROM LESS MODE
Addressing Modes
The COP820C and COP840C enter the ROMless mode of
operation if the 02 pin is held at logical "0" at reset. In this
case the internal ROM is disabled and the controller can
now address up to 32 kbytes of external program memory. It
continues to use the on board 64 bytes of RAM. The ports 0
and I are used to access the external program memory. By
providing a serial interface to external program memory a
large address space can be managed without the penalty of
losing a large number of I/O pins in the process. Figure 12
shows in schematic form the logic required for the ROM less
mode operation and all support logic required to recreate
the I/O.
REGISTER INDIRECT
This is the "normal" mode of addressing for COP820C and
COP840C. The operand is the memory addressed by the B
register or X register.
DIRECT
The instruction contains an 8-bit address field that directly
points to the data memory for the operand .
IMMEDIATE
The instruction contains an 8-bit immediate field as the operand.
Memory Map
REGISTER INDIRECT
(AUTO INCREMENT AND DECREMENT)
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
This is a register indirect mode that automatically increments or decrements the B or X register after executing the
instruction.
2-20
00
01
02
03
10
11
12
13
I
,r-
l::::::J: ~
5
CKI
G7
G6
G5
G4
GJ
G2
Gl
GO
LO
L1
L2
U
L4
L5
I\)
L6
L7
~
RESET
4
3
2
1
28
27
26
25
11
12
13
14
15
16
17
OJ
CKI
22
G7
G6
G5
1
4 50 50
60 so
~
1
12
LO
L1
L2
L3
L4
20
7
1
IJ
~B DC
OB~ ~~
10
02~
RESET
I
A""OA' +-
1, 8
L5
V _
ee
~~
1
~
12
~~
PU (Shi fts out upper seven bits of PC)
D2 GND(Puts the chip in ROMless mode)
D3
DIN(Sh ifts out recreated Port D data)
10
IDATA(Shifts in recreated Port I data)
11
NlOAD (load clock)
12
elK (Data shift clock)
13
RDATA (Shifts in ROM data)
Vee
Ooi
OE
~
8
f!O~
t-t-
f'
ENB
A 0"
B 0B f---o
C Oc
CK
ee : F CL
V
~4
~64
IV
-
~o
_
'-+
Pl(ShiftS out lower eight bits of PC)
-= ~,
lr-
8 AD
AI
Dl
D5
D6
07
L-l~
COP82OC
COP84QC
Do
7
1
19
~ 9
L6
18
L7
24
Ij~
;-
~g ~1'9"-
~~,
74HC164
GO
~i y~
4040
00 6
OE 10
--.-!CK
o
~
Do
00
20 20
3D JQ
Vee-r4~
G4
GJ
G2
Gl
~f
3~2
-==t~
---4A4
2
~,
;;::::::ff
....
~ ~
A7
AS
A9
~
~:::
..f VssEE OE
00 9
01
02
03
04
05
06
07
27CJ2
~~~~
"r---
~~
74HC161
3~2
" 2D
30
9
40
" 50
7 50
18 ~
15
116
119
-?~3
~
01 y..L
1 02
1 OJ
D4
D5
D6
..to
-= ~,
07
1820
_t
TUOO/9103-17
FIGURE 12. COP820C and COP840C ROMless Mode Schematic
O~t8dOO/O ~ t8dOO/OOt8dOO/O~~8dOO/O~~8dOO/OO~8dOO/O~t9dOO/O ~ t9dOO/OOt9dOO/O~~9dOO/O ~~9dOO/OO~9dOO
o
N
'01:1'
Addressing Modes (Continued)
o
RELATIVE
This mode is used for the JP instruction, the instruction field
is added to the program counter to get the new program
location. JP has a range of from -31 to +32 to allow a one
byte relative jump (JP + 1 is implemented by a NOP instruction). There are no 'pages' when using JP, all 15 bits of PC
are used.
co
a..
o
......
o
,..
'01:1'
co
a..
o
o
......
o
C)
"'1::1'
co
a..
o
(.)
......
o
N
N
co
a..
o
(.)
Instruction Set
Registers
A
8-bit Accumulator register
B
8-bit Address register .
X
8-bit Address register
SP
8-bit Stack pointer register
Instruction Set
(.)
N
co
a..
o
15-bit Program counter register
upper 7 bits of PC
lower 8 bits of PC
1-bit of PSW register for carry
Half Carry
1-bit of PSW register for global interrupt enable
Symbols
[B)
Memory indirectly addressed by B register
[X]
Memory indirectly addressed by X register
Mem Direct address memory or [B]
Meml Direct address memory or [B) or Immediate data
Imm 8-bit Immediate data
Reg
Register memory: addresses FO to FF (Includes B, X
and SP)
Bit
Bit number (0 to 7)
.Loaded with
+---+ Exchanged with
REGISTER AND SYMBOL DEFINITIONS
......
,..
PC
PU
PL
C
HC
GIE
ADD
ADC
add
add with carry
A A+ Meml
A A + Meml + C, C Carry
HC Half Carry
A A + JTemi +C, C Carry
HC Half Carry
A A and Meml
A AorMeml
A AxorMeml
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of B "" Imm
Reg Reg - 1, skip if Reg goes to 0
1 tobit,
Mem (bit= 0 to 7 immediate)
o tobit,
Mem
If bit,
Mem is true, do next instr.
SUBC
subtract with carry
N
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
Logical AND
Logical OR
Logical Exclusive-OR
IF equal
IF greater than
IF B not equal
Decrement Reg. ,skip if zero
Set bit
D-
RBIT
Reset bit
IFBIT
If bit
X
LDA
LDmem
LDReg
Exchange A with memory
Load A with memory
Load Direct memory Immed.
Load Register memory Immed.
A-Mem
A Meml
Mem Imm
Reg Imm
X
X
LDA
LDA
LDM
Exchange A with memory [B]
Exchange A with memory [X]
Load A with memory [B]
Load A with memory [X]
Load Memory Immediate
A [B]
(B B±1)
A-[X]
(X-X±1)
A [B]
(B B±1)
A [X]
(X X±1)
[B] Imm(B B±1)
CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
RC
IFC
IFNC
Clear A
IncrementA
Decrement A
Load A indirect from ROM
DECIMAL CORRECT A
ROTATE A RIGHT THRU C
Swap nibbles of A
SetC
ResetC
IfC
IfnotC
A-O
A A+1
A A-1
A ROM(PU,A)
A BCD correction (follows ADC, SUBC)
C -+ A7 -+ ... -+ AO -+ C
A7 ... A4 A3 ... AO
C 1,HC 1
C O,HC 0
If C is true, do next instruction
If C is not true, do next instruction
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
Jump absolute long
Jump absolute
Jump relative short
Jump subroutine long
Jump subroutine
Jump indirect
Return from subroutine
Return and Skip
Return from Interrupt
Generate an interrupt
No operation
PC ii (ii = 15 bits, Oto 32k)
PC11 .. 0 i(i = 12 bits)
PC PC + r(ris -31 to +32, not 1)
[SP] PL,[SP-1] PU,SP-2,PC ii
[SP] PL,[SP-1] PU,SP-2,PC11.. 0 i
PL ROM(PU,A)
SP+2,PL [SPl.PU [SP-1]
SP+ 2,PL [SPl.PU [SP-1],Skip next instruction
SP+2,PL [SPl.PU [SP-11.GIE 1
[SP] PL,[SP-1] PU,SP-2,PC OFF
PC-PC+1
U
......
U
C)
N
co
a..
o
U
......
U
"'1::1'
CD
O
U
......
U
,..
"'1::1'
CD
D-
O
(.)
......
(.)
C)
"'1::1'
CD
D-
O
(.)
......
(.)
C\I
C\I
CD
D-
O
(.)
......
o
,....
C\I
CD
D-
O
(.)
......
(.)
C)
C\I
CD
D-
O
(.)
2-22
Bits 7-4
F
E
0
C
B
A
9
8
7
JP -15
JP -31
LDOFO,#i
DRSZOFO
RRCA
RC
AOCA,
#i
ADCA,
[B]
IFBIT
O,[B]
JP -14
JP-30
LD OF1,#i
DRSZOF1
SC
SUBCA,
#i
SUBC
A,[B]
IFBIT
1,[B]
*
*
JP -13
JP -12
JP -11
JP-29
JP-2B
JP-27
LDOF2,#i
LD OF3,#i
LDOF4,#i
DRSZOF2
DRSZOF3
JP-26
LDOF5,#i
DRSZOF6
JP-B
JP-24
LDOF7,#i
DRSZOF7
JP-7
JP-6
JP-23
JP-22
LD OFB,#i
LDOF9,#i
DRSZOFB
2
1
0
LDB,OF
IFBNEO
JSR
OOOO-OOFF
JMP
OOOO-OOFF
JP + 17
INTR
0
LDB,OE
IFBNE 1
JSR
0100-01FF
JMP
01 00-01 FF
JP + 1B
JP + 2
1
LDB,OD
IFBNE2
JSR
0200-02FF
JMP
0200-02FF
JP + 19
JP + 3
2
LDB,OC
IFBNE3
JSR
0300-03FF
JMP
0300-03FF
JP + 20
JP + 4
3
*
IFBIT
2,[B]
*
XA,
[X-]
XA,
[B-]
IFGT A,
#i
IFGT
A,[B]
IFBIT
3,[B]
*
LAID
ADD A,
#i
ADD
A,[B]
IFBIT
4,[B]
CLRA
LDB,OB
IFBNE4
JSR
0400-04FF
JMP
0400-04FF
JP + 21
JP + 5
4
JID
ANDA,
#i
AND
A,[B]
IFBIT
5,[B]
SWAPA
LD B, OA
IFBNE5
JSR
0500-05FF
JMP
0500-05FF
JP + 22
JP + 6
5
XA,
[X]
XA,
[B]
XORA,
#i
XOR
A,[B]
IFBIT
6,[B]
DCORA
LDB,9
IFBNE6
JSR
0600-06FF
JMP
0600-06FF
JP + 23
JP + 7
6
OR
A,[B]
IFBIT
7,[B]
IFBNE7
JMP
0700-07FF
JP + B
7
*
JSR
0700-07FF
JP + 24
*
ORA,
#i
LDB,B
*
LDA,
#i
IFC
SBIT
O,[B]
RBIT
O,[B]
LDB,7
IFBNEB
JSR
OBOO-OBFF
JMP
OBOO-OBFF
JP + 25
JP + 9
B
*
IFNC
JSR
0900-09FF
JMP
0900-09FF
JP + 26
JP + 10
9
*
RBIT
1,[B]
IFBNE9
*
SBIT
1,[B]
LDB,6
*
NOP
DRSZOF9
JP -5
JP -21
LDOFA,#i
DRSZOFA
LDA,
[X+]
LDA,
[B+]
LD
[B+],#i
INCA
SBIT
2,[B]
RBIT
2,[B]
LDB,5
IFBNEOA
JSR
OAOO-OAFF
JMP
OAOO-OAFF
JP + 27
JP + 11
A
JP-4
JP-20
LDOFB,#i
DRSZOFB
LDA,
[X-]
LDA,
[B-]
LD
[B-],#i
DECA
SBIT
3,[B]
RBIT
3,[B]
LDB,4
IFBNEOB
JSR
OBOO-OBFF
JMP
OBOO-OBFF
JP + 2B
JP + 12
B
JP-3
JP -19
LDOFC,#i
DRSZOFC
LDMd,
#i
JMPL
XA,Md
SBIT
4,[B]
RBIT
4,[B]
LDB,3
IFBNEOC
JSR
OCOO-OCFF
JMP
OCOO-OCFF
JP + 29
JP +13
C
*
JP-2
JP -1B
LDOFD,#i
ORSZOFD
DIR
JSRL
LDA,
Md
RETSK
SBIT
5,[B]
RBIT
5,[B]
LDB,2
IFBNEOD
JSR
OOOO-ODFF
JMP
ODOO-ODFF
JP + 30
JP +14
D
JP -1
JP -17
LDOFE,#i
ORSZOFE
LDA,
[X]
LDA,
[B]
LD
[B], #i
RET
SBIT
6, [B]
RBIT
6, [B]
LD B,1
IFBNEOE
JSR
OEOO-OEFF
JMP
OEOO-OEFF
JP + 31
JP +15
E
JP-O
JP -16
LD OFF,#1
DRSZOFF
RETI
JSR
OFOO-OFFF
JMP
OFOO-OFFF
JP + 32
JP + 16
F
*
RBIT
7,[B]
IFBNEOF
*
SBIT
7,[B]
LDB,O
*
where,
is the immediate data
Md is a directly addressed memory locaUon
o
o
om
r-
IFEQ
A,[B]
*
LDOF6,#i
3
IFEQA,
#i
DRSZOF5
JP-25
"U
4
XA,
[B+]
DRSZOF4
JP-9
o
5
XA,
[X+]
*
JP -10
6
~
• is an unused opcode (see following table)
O~l'8dOO/O ~ l'8dOO/OOl'8dOO/O~~8dOO/O ~ ~8dOO/OO~8dOO/O~l'9dOO/O ~ l'9dOO/OOl'9dOO/O~~9dOO/O ~ ~9dOO/OO~9dOO
(.)
CN
~
co
a.
o(.)
.......
(.)
"t-
~
co
a.
o(.)
Instruction Execution Time
BYTES and CYCLES per
INSTRUCTION
Most instructions are single byte (with Immediate addressing mode instruction taking two bytes).
Most single instructions take one cycle time (1 p.s at
20 MHz) to execute.
See the BYTES and CYCLES per INSTRUCTION table for
details.
The following table shows the number of bytes and cycles
for each Instruction in the format of byte/cycle (a cycle is
1 P.s at 20 MHz).
.......
(.)
[8]
Direct
Immed.
ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
1/1
1/1
1/1
3/4
3/4
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
SBIT
RBIT
IFBIT
1/1
1/1
o
~
CO
a.
o(.)
.......
(.)
CN
CN
co
a.
o
(.)
.......
(.)
"t-
CN
co
a.
o(.)
.......
(.)
o
CN
CO
a.
~
CD
.......
(.)
"t~
CD
a.
o(.)
.......
1/1
Register Indirect
Register
Auto Incr & Decr
Indirect Direct Immed.
[8] [X]
[8+,8-] [X+,X-]
.......
(.)
CN
o
(.)
1/3
3/4
3/4
3/4
Memory Transfer Instructions
o(.)
a.
3/4
3/4
3/4
3/4
3/4
3/4
1/1
1/1
1/1
1/1
1/1
1/1
XA,·
1/1 1/3
LOA,·
1/1 1/3
LDB,lmm
LDB,lmm
2/2
LDMem,lmm
LDReg,lmm
• =
2/3
2/3
1/2
1/2
2/2
1/1
2/3
1/3
1/3
(If B < 16)
(If B
3/3
>
15)
2/2
2/3
> Memory location addressed by B or X or directly.
(.)
o
~
CD
a.
o(.)
.......
(.)
CN
CN
CD
a.
o
(.)
.......
(.)
"t-
CN
CD
a.
o(.)
.......
o
Transfer of Control Instructions
Instructions Using A & C
CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
RC
IFC
IFNC
1/1
1/1
1/1
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
(.)
CN
CD
a.
o(.)
2-24
3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
117
1/1
o
The following table shows the instructions assigned to unused opcodes. This table is for information only. The operations performed are subject to change without notice. Do
not use these opcodes.
Unused
Opcode
Instruction
60
61
62
63
67
8C
99
9F
A7
A8
NOP
NOP
NOP
NOP
NOP
RET
NOP
LD [B), #i
XA, [B)
NOP
Unused
Opcode
Instruction
A9
AF
Bl
B4
B5
B7
B9
BF
NOP
LOA, [B)
C ~ HC
NOP
NOP
XA,[X]
NOP
LOA, [X]
o"tJ
Single Chip Emulator Device
The COP820C is fully supported by a form, fit and function
emulator device, the COP8720C.
The COP820C/COP840C mask programmable options are
listed out below. The options are programmed at the same
time as the ROM pattern to provide the user with hardware
flexibility to use a variety of oscillator configuration.
OPTION 1: CKIINPUT
= 1 Normal Mode Crystal
Option Data
Option 1 Value_is: CKllnput
Option 2 Value_is: COP Bonding
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en
~
«:)
Q
o
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en
en
~
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«:)
How to Order
To order a complete development package, select the section for the microcontroller to be developed and order the
parts listed.
o
......
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....o
N
......
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Description
Includes
Manual
Number
Brain Board
Brain Board Users Manual
420408188-001
MOLE-COP8-PB 1
Personality Board
COP820/840 Personality Board
Users Manual
420410806-001
420410703-001
o
......
o
N
MOLE-BRAIN
MOLE-COP8-IBM
en
N
N
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Development Tools Selection Table
COP8201
COP840
N
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3 20 pin package
The following option information is to be sent to National
along with the EPROM.
MOLE can be used in either a stand alone mode or in conjunction with a selected host system using PC-DOS communicating via a RS-232 port.
Order
Part Number
....
o
......
o
~
= 2 24 pin package
It contains three serial ports to optionally connect to a terminal, a host system, a printer or a modem, or to connect to
other MOLEs in a multi-MOLE environment.
Mlcrocontroller
en
o
......
o
= 1 28 pin package
The purpose of the MOLE is to provide the user with a tool
to write and assemble code, emulate code for the target
microcontroller and assist in both software and hardware
debugging of the system.
It is a self contained computer with its own firmware which
provides for all system operation, emulation control, communication, PROM programming and diagnostic operations.
o"tJ
....
OPTION 2: COP820C/COP840C BONDING
=
o
......
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(CKl/l0) CKO for crystal configuration
= 2 Normal Mode External (CKl/l0) CKO available as G7
input
= 3 RIC
(CKl/l0) CKO available as G7
input
= 4 High Speed Crystal
(CKI/20) CKO for crystal configuration
= 5 High Speed External (CKI/20) CKO available as G7
input
MOLE DEVELOPMENT SYSTEM
The MOLE (Microcomputer On Line Emulator) is a low cost
development system and emulator for all microcontroller
products. These include COPs and the HPCTM family of
products. The MOLE consists of a BRAIN Board, Personality Board and optional host software.
«:)
o
Option List
Development Support
en
N
Assembler Software for IBM
Programmer's Manual
COP800 Software Users Manual
and Software Disk
PC-DOS Communications
Software Users Manual
~fII
......
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424410527-001
o
......
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420040416-001
co
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420410703-001 .
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2-25
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r---------------------------------------------------------------------------~
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DIAL-A-HELPER
D.
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Dial-A-Helper is a service provided by the MOLE (Microcontroller On Line Emulator) applications group. It consists of
both an electronic bulletin board information system and a
method by which applications can take control of a MOLE
Development System at a remote site via modem in order to
resolve any problems.
o
INFORMATION SYSTEM
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.......
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.......
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The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION mode
that can be used to search out and retrieve application data
about NSC Microcontrollers. The user needs as a minimum,
a Dumb terminal, 300 or 1200 baud Modem, and a telephone.
N
If the user has a PC with a communications package then
files from the FILE SECTION can be down-loaded to disk for
later use.
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ORDER PIN: MOLE-DIAL-A-HLP
Information System Package contains:
Dial-A-Helper Users Manual
Public Domain Communications Software
FACTORY APPLICATIONS SUPPORT
Dial-A-Helper also provides immediate factory applications
support. If a user is having difficulty in getting a MOLE to
operate in a particular mode or something peculiar is occurring, he can contact us via his system and modem. He can
leave messages on our electronic bulletin board, which we
will respond to, or he can arrange for us to actually take
control of his system via modem for debugging purposes.
The applications group can then cause his system to execute various commands and try to resolve the customer's
problem by actually getting' customer's system to respond.
Both parties see exactly what is occurring, as it is happening.
This allows us to respond in minutes when applications help
is needed.
D.
o
Voice:
o
.......
o
o
(408) 721-5582
Modem: (408) 739-1162
300 or 1200 baud
Baud:
N
CO
Setup:
D.
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.......
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Length:
8-Bit
Parity:
None
Stop Bit: 1
Operation: 24 Hrs. 7 Days
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CD
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DIAL-A-HELPER
------------------------ .
USER'S
TARGET
SYSTEM
I
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MOLE
MODEM :
.
I
. ---1I MODEM III--~I COMPUTER
HOST
... 7---......
~
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HOST
COMPUTER
WOL'
.------------------------.
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._-----------------------
USER SITE
NATIONAL SEMICONDUCTOR SITE
TLlDD/91 03-20
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CD
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CD
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2-26
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PRELIMINARY
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COP820CP-X/COP840CP-X
Piggyback EPROM Microcontrollers
General Description
The COP820CP/COP840CP are piggyback versions of the
COP820C/COP840C microcontroller families. They are fully
static parts, fabricated using double-metal silicon gate
microCMOS technology. This microcontroller is a complete
microcomputer containing all system timing, interrupt logic,
RAM, and I/O necessary to implement dedicated control
functions in a variety of applications. Features include an 8bit memory mapped architecture, MICROWIRE/PLUSTM serial I/O, a 16-bit timer/counter with capture register and a
multi-sourced interrupt. Each I/O pin has software selectable options to adapt the emulator to the specific application. The part operates over a voltage range of 4.5V to 5.5V.
High throughput is achieved with an efficient, regular instruction set operating at a 1 ,.,.s per instruction rate. The
COP820CP-X/COP840CP-X are totally compatible with the
ROM based COP820C/COP840 microcontroller. It serves
as an economical low and medium volume emulator devices
for the COP820/COP840 microcontroller family.
Features
• Low cost 8-bit CORE microcontroller
• Fully static CMOS
• 1 ,.,.s instruction time (20 MHz clock)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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Low current drain
Single supply operation: 4.5V to 5.5V
Up to 32 kbytes of addressable memory
64 bytes of RAM (128 bytes for COP840CP)
16-bit read/write timer operates in a variety of modes
- Timer with 16-bit auto reload register
- 16-bit external event counter
- Timer with 16-bit capture register (selectable edge)
Multi-source interrupt
- Reset master clear
- External interrupt with selectable edge
- Timer interrupt or capture interrupt
- Software interrupt
8-bit stack pointer (stack in RAM)
Powerful instruction set, most instructions single byte
BCD arithmetic instruction
MICROWIRE/PLUS serial I/O
28 pin package
24 input/output pins (28-pin package)
Software selectable I/O options (TRI-STATE®, pushpull, weak pull-up)
Schmitt trigger inputs on Port G
Fully supported by National's MOLETM development
system
Block Diagram
PORT L
PORT 0
FIGURE 1
2-27
PORT G
PORT I
Tl/DD/9683-1
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Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
......
Supply Voltage (Vee)
><
Voltage at Any Pin
A.
o
C)
Total Current into Vee Pin (Source)
C'I
DC Electrical Characteristics o·c ~. TA ~
co
A.
o
o
Total Current into GND Pin (Sink)
Note: Absolute maximum ratings indicate limits beyond
which damage to the devicemay occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
6V
-0.3V to Vee + 0.3V
150mA
Parameter
+ 70·C unless otherwise specified
Condition
Operating Voltage
Min
Typ
Max
Units
5.5
V
0.1 Vee
V
95
90
rnA
mA
80
rnA
0.1 Vee
V
V
0.2 Vee
V
V
+10
,...A
4.5
Power Supply Ripple (Note 1)
Peak to Peak
Supply Current (Note 2)
High Speed Mode, CKI = 20 MHz
Normal Mode, CKI = 5 MHz
Vee
Vee
HALT Current (Note 3)
160mA
- 65·C to + 150·C
Storage Temperature Range
= 5.5V, te = 1,...s
= 5.5V, te = 2,...s
Vee = 5.5V, CKI = 0 MHz
(Note 4)
INPUT LEVELS
Reset and CKI (Crystal Osc.)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
0.9 Vee
0.7 Vee
Hi-Z Input Leakage
Vee
Vee
= 5.5V, VIN = OV
= 5.5V
-10
G and L Port Input Hysteresis
Vee
Vee
= 4.5V, VOH = 3.8V
= 4.5V, VOL = 1.0V
0.4
10
Vee
Vee
Vee
Vee
= 4.5V, VOH = 3.2V
= 4.5V, VOH = 3.8V
= 4.5V, VOL = O.4V
= 5.5V
10
0.4
1.6
-2.0
Output Current Levels
D Outputs
Source
Sink
All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
0.05 Vee
V
rnA
rnA
100
+2.0
,...A
rnA
rnA
,...A
15
3
rnA
rnA
Allowable Sink/Source
Current per Pin
D Outputs (Sink)
All Others
RAM Retention Voltage, Vr
500 ns
Rise and Fall Time (Min)
2.0
V
Input Capacitance
Load Capacitance on D2
7
pF
1000
pF
Note 1: The rate of voltage change must be less than 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input. CKO open. inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from OSCillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee. Land G ports in the
TRI-STATE mode and tied to ground. all outputs low and tied to ground.
Note 4: This includes the EPROM. and the pull-up resistors on the 0 and I ports.
Note 5: Parameter sampled but not 100% tested.
Note 6: There is one cycle delay on ports I and D.
2-28
o
o
AC Electrical Characteristics o·c ~ TA ~ + 70·C unless otherwise specified
Parameter
Instruction Cycle Time (tc)
High Speed Mode
(Div-by 20)
Normal Mode
(Div-by 10)
RIC Oscillator Mode
(Div-by 10)
CKI Clock Duty Cycle
(Note 5)
Rise Time (Note 5)
Fall Time (Note 5)
Inputs
tSETUP
tHOLD
Output Propagation Delay
tpD1, tpDo (Note 6)
SO,SK
All Others
Condition
Min
Typ
"'a
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Max
Units
Vee ~ 4.5V
1
DC
p's
Vee ~ 4.5V
2
DC
p's
Vee ~ 4.5V
3
DC
p's
fr
= Max
33
66
%
fr
fr
= 20 MHz Ext Clock
= 20 MHz Ext Clock
12
8
ns
ns
N
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o
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Vee ~ 4.5V
Vee ~ 4.5V
RL
= 2.2k, CL =
Vee
Vee
~
~
ns
ns
200
60
100 pF
4.5V
4.5V
MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Valid Time (tUV)
0.7
1
p's
p.s
220
ns
ns
ns
20
56
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
1
1
1
1
te
te
te
te
Reset Pulse Width
1
p.S
1: The rate of voltage change must be less than 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input. CKO open. inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee. Land G ports in the
TRI-STATE mode and tied to ground. all outputs low and tied to ground.
Note 4: This includes the EPROM. and the pull-up resistors on the D and I ports.
Note 5: Parameter sampled but not 100% tested.
Note 6: There is one cycle delay on ports I and D.
Note
EPROM Selection
TABLE I
The COP820CP-X/COP840CP-X, (where X = 1, 2, 3, 4 or 5,
see Table II), are the piggyback versions of the COP820CI
COP840C microcontrollers. They are identical to their respective devices except that the program memory has been
removed. The device package incorporates the circuitry and
the socket on top of the package to allow plugging-in the
EPROM 57C64, an 8 kbyte device, or any other comparable
EPROM, for high speed operation. With the addition of an
EPROM, these devices will perform exactly as their factory
masked equivalent.
Table I lists the minimum EPROM access time for a given
instruction cycle time of the microcontroller.
EPROM Minimum COP Instruction
Access Time
Cycle Time
2-29
120 ns
1.00 P.s
150 ns
1.10 p's
200 ns
1.27 P.s
250ns
1.44 p.s
300 ns
1.60 p's
400 ns
1.94 p.s
~
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X
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r---------------------------------------------------------------------~
Connection Diagram
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-
CO
D.
oo
.....
x
a..
o
25
26
o
27
CO
28
C\I
D.
.-
GO
25
Gl
26
;::
:::
;::
~
11
12
13
:::
::::
:::
;::
14
15
;::
;::
;::
;::
18
16
17
24
23
::::::::
--
57C64
EPROt.l
61
~
::::
;::
oo
COP820C/840C
Vee
G2
27
G3
28
G4
1
G5
2
GS
G7
LO
L1
3
..
11
12
L2
13
L3
14
L4
15
L5
16
LS
17
L7
18
CKI
5
RESET
24
GND
Vee
GO
Gl
COP8ASIC
Vee
G2
G3
~
G4
~
G5
~
G6
""----
G7
Vee
Vee
Vee
Vee
LO
Vee
Ll
L2
10
L3
11
L4
12
L5
13
L6
00
L7
01
CKI
02
7
8
t1:
A5
'"T'"
IDATA
~
LOAD
'"T'"f
9
10
~
19
'"T'"f
~
20
~
1:
21
f
CLOCK
'"T'"
RDATA
LADDR
HADDR
DDATA
22
D31"':;k.
RESET
23
1
::::
19
20
21
22
-
.-
;::
;::
;::
A6
A7
A8
A9
Al0
All
A12
11
12
13
9
8
7
6
5
..
3
25
24
21
23
2
T
28T 271
Vee
r - - - GND
PGt.I
AO
00
AI
01
A2
02
A3
03
A4
04
A5
05
A6
OS
A7
07
11
I'"
12
13
15
16
17
18
19
A8
A9
Al0
All
A12
OE
CE
20
1
GND
141
~
~ GND
10
10
221
GND
~ GND
::::
AI
A2
A4
Vee
-:.=
10
Vpp
AO
A3
~
-::::--
d
-r-
RD4
RD5
RDS
RIO
RD7
Rll
RI2
RI3
00
01
02
00
01
02
03
~
03
ROO
RDI
RD2
RD3
04
05
06
07
.
TL/DD/9683-2
All resistors are 3300 ±20%
FIGURE 2
2-30
o
o
AC Timing Diagram
"'C
(X)
N
o
CKI
(+ 101ol00E)
o
"'C
CKI~
(+201ol00E)
1
-l tpoo
r-
\~
11 (XLO)
><
.......
1
____
-l Ir
______-JI ~--t-PD1-~-----------~--t--~-tpDl
~.
pool
1;-
I
12 (PHI)
--------------------~
I,:
J
---------------~
--I 'po,
00,01,03
4
l
t sETUP
"DO
I-
"
EJ~mD
,'------
.JXXXX-..-;..---
IO,13 _ _ _ _ _ _ _ _ _ _ _ _ _
XXXXIr"'W""'l~--TL/DO/9683-3
FIGURE 3
5K
uws
~
tuwh
51
~
SO
TL/OO/9683-10
FIGURE3b
COP820CP-X/COP840CP-X Pinout Diagrams
G4/50
1
G3/TIO
G5/5K
2
G2
G6/SI
3
G1
G7/CKO
PORT I
GO/INT
CKI
RESET
Vee
GNO
10
03
11
21
02
INTR
CKO
IoIICROWIRE/PLU5
01
12
13
10
DO
LO
11
L7
L1
12
L6
L2
13
L5
L3
14
L4
TL/DO/9683-5
TLIDD/9683-4
Order Number COP820CP·X or COP840CP·X
FIGURE 4
2·31
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(X)
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A.
Oscillator Circuits
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Figure 5 shows the clock oscillator configurations available
o
o
A.
o
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......
~
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N
CO
A.
B. RC OSCILLATOR
CKI is configured as a single pin RC controlled Schmitt trigger oscillator. CKO is available as a general purpose input
and/or HALT control.
for the COP820CP-X/COP840CP-X.
A. CRYSTAL OSCILLATOR
The COP820CP-X/COP840CP-X can be driven by a crystal
clock. The crystal network is connected between the pins
CKI and CKO.
Table 18 shows the variation in the oscillator frequencies as
functions of the Rand C component values.
Table IA shows the component values required for various
standard crystal values.
o
o
TABLE IA. Crystal Oscillator Configuration, T A
= 25°C
R1
(kn)
R2
(MO)
C1
(pF)
C2
(pF)
CKI Freq
(MHz)
0
0
0
1
1
1
30
30
30
30-36
30-36
30
20
10
Conditions
Vee
Vee
Vee
4
= 5V
= 5V
= 5V
TABLE lB. RC Oscillator Configuration, T A = 25°C
R
(kn)
C
(pF)
CKI Freq.
(MHz)
Instr. Cycle
(/-Ls)
Conditions
3.3
5.6
82
100
2.8-2.2
1.5-1.1
3to 6
6 to 11
Vee = 5V
Vee = 5V
Crystal Oscillator
I
CKI
A
eKO
RCOsclllator
I
I
R2
I
B
CKI
CKO
+
..
N/C
R
....
I-
Vee
C
TL/DD/9683-6
FIGURE 5. Crystal and RC Oscillator Connection Diagrams
TABLE II. Clock Options Per Package
X
Order Part Number
Clock Option
1
2
3
COP820CP-1/COP840CP-1
COP820CP-2/COP840CP-2
COP820CP-3/COP840CP-3
COP820CP-4/COP840CP-4
COP820CP-5/COP840CP-5
Crystal Oscillator Divide by 10 Option
External Oscillator Divide by 10 Option
RC Oscillator Divide by 10 Option
Crystal Oscillator Divide by 20 Option (High Speed)
External Oscillator Divide by 20 Option
4
5
2-32
TL/DD/9683-7
o
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COP820CP/840CP Dimensions Diagram
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o
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0)
0l:Io
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0.050
1.600
4
0.235-0.310
~!~
0.195i.0.250 I
I
!!.
n0
QCL
0.062:t 0.015
__~_-~~~0_.~Ot~5-0~~U~U~-----I~~~
0.125-0.170
I I
TL/DD/9683-8
FIGURE 6
•
2·33
g.
Development Support
:;
MOLE DEVELOPMENT SYSTEM
a..
The MOLE (Microcomputer On Line Emulator) is a low cost
development system and emulator for all microcontroller
products~ These include COPs and the HPC family of prod·
ucts. The MOLE consists of a BRAIN Board, Personality
Board and optional host software.
MOLE can be used in either a stand alone mode or in con·
junction with a selected host system using PC· DOS commu·
nicating via a RS·232 port.
The purpose of the MOLE is to provide the user with a tool
to write and assemble code, emulate code for the target
microcontroller and assist in both software and hardware
debugging of the system.
To order a complete development package, select the sec·
tion for the microcontroller to be developed and order the
parts listed.
><
8
'"
=-::
f>
o
~
~
o
It contains three serial ports to optionally connect to a termi·
nal, a host system, a printer or a modem, or to connect to
other MOLEs in a multi·MOLE environment.
How to Order
It is a self contained computer with its own firmware which
provides for all system operation, emulation control, com·
munication, PROM programming and diagnostic operations.
Development Tools Selection Table
Mlcrocontroller
. Order
Part Number
MOLE·BRAIN
Description
Brain Board
Includes
Brain Board Users Manual
MOLE·COP8·PB 1 Personality Board
Manual
Number
420408188·001
COP820/COP840 Personality Board 42041 0806·001
Users Manual
COP820/COP840 MOLE·COP8·IBM Assembler Software for IBM COP800 Software Users Manual
and Software Disk
PC· DOS Communications
Software Users Manual
42441 0527·001
Programmer's Manual
420410703·001
420410703·001
2·34
420040416·001
o
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Development Support (Continued)
Q)
N
DIAL-A-HELPER
Order PIN: MOLE-DIAL-A-HLP
Dial-A-Helper is a service provided by the MOLE (Microcontroller On Line Emulator) applications group. It consists of
both an electronic bulletin board information system and a
method by which applications can take control of a MOLE
Development System at a remote site via modem in order to
resolve any problems.
Information System Package Contains
INFORMATION SYSTEM
The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. the system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION mode
that can be used to search out and retrieve application data
about NSC Microcontrollers. The user needs as a minimum,
a Dumb terminal, 300 or 1200 baud Modem, and a telephone.
o
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><•
.......
DIAL-A-HELPER Users Manual PIN
Public Domain Communications Software
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FACTORY APPLICATIONS SUPPORT
Q)
Dial-A-Helper also provides immediate factory applications
support. If a user is having difficulty in getting a MOLE to
operate in a particular mode or something peculiar is occurring, he can contact us via his system and modem. He can
leave messages on our electronic bulletin board, which we
will respond to, or he can arrange for us to actually take
control of his system via modem for debugging purposes.
.1:10
o
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><•
The applications group can then cause his system to execute various commands and try to resolve the customers
problem by actually getting customers system to respond.
Both parties see exactly what is occurring, as it is happening.
If the user has a PC with a communications package then
This allows us to respond in minutes when applications help
files from the FILE SECTION can be down loaded to disk for
is needed.
later use.
(408) 721-5582
Voice:
Modem:
(408) 739-1162
Baud: 300 or 1200 baud
Set-Up:
Length:
8-bit
Parity:
None
Stop bit:
Operation: 24 hrs., 7 days
DIAL-A-HELPER
USER'S
TARGET
SYSTEI.t
HOST
COI.tPUTER
•
NATIONAL SEI.tICONDUCTOR SITE
USER SITE
TL/DD/9683-9
2-35
or-----------------------------------------------------------~
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~National
PRELIMINARY
o
D Semiconductor
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COP8720C/COP8721C/COP8722C
Single-Chip microCMOS Microcontrollers
Q.
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...... General Description
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The COP8720C/COP8721 C/COP8722C
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Q.
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are members
of the COPSTM microcontroller family featuring on-chip
EEPROM modules. They are fully static parts, fabricated using double-metal silicon gate microCMOS technology. This
low cost microcontroller is a complete microcomputer containing all system timing, interrupt logic, ROM, RAM, and
I/O necessary to implement dedicated control functions in a
variety of applications. Features include an 8-bit memory
mapped architecture, MICROWIRE/PLUSTM serial I/O, a
16-bit timer/counter with capture register and a mUltisourced interrupt. Each I/O pin has software selectable options to adapt the COP8720C to the specific application.
The part operates over a voltage range of 2.5V to 6.0V. High
throughput is achieved with an efficient, regular instruction
set operating at a 1 microsecond per instruction rate. The
COP8720 is totally compatible with the ROM based
COP820C microcontroller. It serves as a form, fit and function emulator device for the COP820 microcontroller family.
Features
•
•
•
•
Low Cost 8-bit CORE microcontroller
Fully static CMOS
1 fLs instruction time (20 MHz clock)
Low current drain (2.2 mA at 3 fLs instruction rate)
Extra-low current static HALT mode (Typically < 10 fLA)
• Single supply operation: 2.5V to 6.0V
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1024 bytes EEPROM program memory
64 bytes of RAM
64 bytes EEPROM data memory
16-bit read/write timer operates in a variety of modes
- Timer with 16-bit auto reload register
- 16-bit external event counter
- Timer with 16-bit capture register (selectable edge)
Multi-source interrupt
- Reset master clear
- External interrupt with selectable edge
- Timer interrupt or capture interrupt
- Software interrupt
8-bit stack pointer (stack in RAM)
Powerful instruction set, most instructions single byte
BCD arithmetic instruction
MICROWIRE/PLUSTM serial I/O
28 pin package (optionally 24 or 20 pin package)
24 input/output pins
Software selectable I/O options (TRI-STATE$, pushpull, weak pull-up)
Schmitt trigger inputs on Port G
Form, fit and function EEPROM emulation device for
COP820C/COP821 C/COP822C
Fully supported by National's MOLETM development
system
Block Diagram
PORT L
FIGURE 1
2-36
PORT D
PORT G
PORT I
TL/DD/9108-1
o
o-a
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (Vee>
Voltage at any Pin
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
-0.3V to Vee + 0.3V
2000V
Total Current into Vee Pin (Source)
Parameter
-40·C
~ TA ~ + 8S·C unless otherwise specified
Condition
Peak to Peak
4.S
Vee
Vee
Vee
= 6V, tc = 1 ,...s
= 6V,tc = 2,...s
= 2.SV, tc = S,...s
Vee
= 6V, CKI = 0 MHz
Input Levels
RESET, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
<10
Sink
All Others
Source (Weak Pull-Up)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
Units
6.0
0.1 Vee
V
V
6.0
V
13
7
2
mA
mA
mA
30
,...A
0.1 Vee
V
V
0.2 Vee
V
V
+2
2S0
,...A
,...A
0.7 Vee
= 6.0V, VIN = OV
= 6.0V, VIN = OV
-2
40
V
O.OS Vee
Vee
Vee
Vee
Vee
= 4.SV, VOH = 3.8V
= 2.SV, VOH = 1.8V
= 4.SV, VOL = 1.OV
= 2.SV, VOL = O.4V
0.4
0.2
10
2.0
Vee
Vee
Vee
Vee
Vee
Vee
= 4.SV, VOH = 3.2V
= 2.SV, VOH = 1.BV
= 4.SV, VOH = 3.BV
= 2.SV, VOH = 1.BV
= 4.SV, VOL = O.4V
= 2.SV, VOL = O.4V
10
2.S
0.4
0.2
1.6
0.7
-2.0
TRI-STATE Leakage
mA
mA
mA
mA
100
33
Allowable Sink/Source
Current Per Pin
D Outputs (Sink)
All Others
Maximum Input Current (Room Temp)
without Latchup (Note S)
RAM Retention Voltage, Vr
Max
0.9 Vee
G Port Input Hysteresis
Output Current Levels
DOutputs
Source
Typ
Min
2.S
Vee
Vee
.......
o
N
o
.....
o
o-a
at
.......
......
Operating Voltage
during EEPROM Write
Hi-Z Input Leakage
Input Pullup Current
at
N
SOmA
DC Electrical Characteristics
Supply Current (see page 17)
High Speed Mode, CKI = 20 MHz
Normal Mode, CKI = 5 MHz
Normal Mode, CKI = 2 MHz
(Note 2)
HALT Current
(Note 3)
60mA
- 6S·C to + 1SO·C
Storage Temperature Range
7V
ESD Susceptibility (Note 4)
Operating Voltage
Power Supply Ripple (Note 1)
Total Current out of GND Pin (Sink)
SOO ns Rise and Fall Time (Min)
Input Capacitance
Load Capacitance on D2
2-37
.-
+2.0
,...A
,...A
mA
mA
mA
mA
,...A
1S
3
mA
mA
±100
mA
7
pF
1000
pF
V
2.0
o
.....
o
o-a
at
.......
N
N
o
o
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......
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Q.
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.......
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......
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Note 1: Rate of voltage change must be less than 0.5V1ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input. CKO open. inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee. Land
TRI-STATE and tied to ground. all outputs low and tied to ground.
Note 4: Human body mode. 100 pF through 15000.
Note 5: Except pins 3. 4. 24
pins 3. 24: +SOmA
pin4:
-25mA
AC Electrical Characteristics
Parameter
Instruction Cycle Time (tc)
High Speed Mode
(Div-by20)
Normal Mode
(Div-by 10)
RIC Oscillator Mode
(Div·by 10)
(See Page 16)
CKI Clock Duty Cycle
(Note 6)
Rise Time (Note 6)
Fall Time (Note 6)
Inputs
tSETUP
tHOLD
Output Propagation Delay
tpDl, tpDO
SO,SK
All Others
-40·C
2.5V ::;; Vee
Min
< 4.5V
< 4.5V
= Max (+ 20 Mode)
fr
fr
= 20 MHz Ext Clock
= 20 MHz Ext Clock
RL
Vee ~ 4.5V
2.5V ::;; Vee
Vee ~ 4.5V
2.5V ::;; Vee
Units
3
DC
DC
DC
DC
DC
JLs
JLs
JLs
JLs
JLs
7.5
DC
JLs
33
66
0/0
12
8
ns
ns
200
500
60
150
< 4.5V
< 4.5V
= 2.2k, CL =
Typ
Max
1
2.5
2
5
< 4.5V
fr
Vee ~ 4.5V
2.5V ::;; Vee
Vee ~ 4.5V
2.5V ::;; Vee
ports are at
< TA < + 85·C unless otherwise specified
Condition
Vee ~ 4.5V
2.5V ::;; Vee
Vee ~ 4.5V
2.5V ::;; Vee
Vee ~ 4.5V
G
ns
ns
ns
ns
100 pF
0.7
1.75
1
2.5
< 4.5V
< 4.5V
MICROWIRETM Setup Time
tuws
MICROWIRE Hold Time
tUWH
MICROWIRE Output Valid
Timetuv
20
ns
56
ns
220
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
JLs
JLs
JLs
JLs
ns
te
te
tc
tc
Reset Pulse Width
Note 6: Parameter sampled but not 100% tested.
1.0
2·38
JLs
o
o"0
EEPROM Characteristics
Parameter
CD
Condition
EEPROM Write Cycle Time
4.5V
~
Vee
~
6.0V
Typ
Max
Units
N
15
20
25
ms
.......
10000
Cycles
o"0
EEPROM Number of Writes
Symbol
Vee Level for Write Lock Out
3.9
VLKO
Supply Current
lee
Programming Voltage to RESET Pin
Vprg
4.5V
Typ
Min
~
Vee
~
6.0V
12
11.5
.......
Max
Units
4.4
V
35
mA
12.5
V
2
mA
-2
2
J.LA
TRI-STATE Leakage Current
-5
5
J.LA
0.2 Vee
V
1.0Vee
V
0.4
V
IIH
Input Low Level
VIL
Input High Level
VIH
Output Low Level, IOL = 0.8 mA
VOL
Output High Level, IOH = -0.4 mA
VOH
0.7 Vee
V
3.2
EEPROM AC Electrical Characteristics o·c ~ TA ~ + 70·C unless otherwise specified
Parameter
CKllnput Frequency
Symbol
f
CKI Duty Cycle
Typ
Max
Units
10
20
MHz
33
66
%
Min
RESET Rise Time
TO
1
J.Ls
Address Setup Time
T1
17
tc
Data Input Valid Time
T2
4
tc
25
ms
15
Program Time
T3
WR Pulse Width
T4
50
J.Ls
RD Pulse Width
T5
50
tc
Time to TRI-STATE
T6
17
tc
Read Access Time
T7
69
tc
2-39
o
N
.....
All Other Inputs, Input Current
RESET Input Current
o
CD
EEPROM DC Electrical Characteristics o·c ~ TA ~ + 70·C unless otherwise specified
Parameter
.......
o
Min
o
.......
o
o"0
CD
.......
N
N
o
o
N
N
.....
co
a.
o
o
.......
o
N
.....
co
a.
oo
(3
--
Timing Diagrams
Vprg
RESf:T-..J
Ri5-----.. . .
WR _ _ _ _ _ _J
AOO-AD7----------K~~~~~>__1r_------
"1
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.....
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AS-All
ADDRESS
/
ROY
ADO-AD7---~~~'J
\
AS - AII----------((--AjADD[D;RiRESruS--~)~--------RDY _ _ _",/
TL/DD/9108-21
FIGURE 2b. COP8720C EEPROM Read Timing Diagrams
In Programming Mode
TLlDD/9108-17
FIGURE 2a. COP8720C EEPROM Write Timing Diagrams
by Programming Mode
5K
uw.
~
tuwh
51
50
---~-c
TL/DD/9108-22
FIGURE 2c. MICROWIRE/PLUS Timing Diagram
Connection Diagrams
20·Pln Dual·ln·Llne Package
G.4/S0
1
GJ/TlO
G5/SK
24·Pln Dual·ln·Llne Package
G.4/S0
1
GJ/TIO
G2
G5/SK
Gl
G6/SI
G7/CKO
GO/I NT
mrr
CKI
Ll
Gl
G6/SI
G7/CKO
GO/iNT
~
CKI
15
GNO
GND
14
L7
03
13
L6
DO
L2
9
12
L5
LO
L3
10
11
L4
Ll
TLlDD/9108-3
G3/T10
G.4/S0
G2
GS/SK
G6/SI
G7/CKO
CKI
3
Gl
GO/INT
REm
GNO
D3
11
12
L5
Order Number COP8722CN
See NS Molded Package
NumberN20A
28-Pln Dual·ln-Llne Package; PLCC
13
DO
LO
L7
L6
L4
L3
L5
TL/DD/91 08-4
Order Number COP8721CN
See NS Molded Package
NumberN24A
L3
L4
TL/DD/9108-5
Order Number COP8720CN
See NS Molded Package
NumberN28B
Order Number COP8720CV
See NS PLCC Package
NumberV28A
FIGURE 3
2-40
~-----------------------------------------------------------------.o
o-a
Connection Diagrams (Continued)
COP8722C
COP8721C
Q:)
COP8720C
~
o
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PORT 1.,._____....
VCC
GND
CKI
VCC
VCC
GND
GND
CKI
CKI
mrr
RESET
PORT Gl'\.I'"T""T"1'"T-M/
RESET
INTR
CKO
IAICROWIRE/PLUS
PORT II\.r--~...J
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-a
Q:)
......
....o
N
"oo
-a
Q:)
TL/DD/9108-8
INTR
CKO
IAICROWIRE/PLUS
TL/DD/9108-7
INTR
CKO
IAICROWIRE/PLUS
......
N
N
o
TLIDD/91 08-8
FIGURE 3 (Continued)
Pin Descriptions
Vee and GND are the power supply pins.
return zeros. Note that the chip will be placed in the HALT
mode by setting the G7 data bit.
CKI is the clock input. This can come from an external
source, a R/C generated oscillator or a crystal (in conjunction with CKO). See Oscillator description.
Six bits of Port G have alternate features:
RESET is the master reset input. See Reset description.
G3 TIO (timer/counter input/output)
PORT I is a four bit Hi-Z input port.
PORT L is an 8-bit I/O port.
G4 SO (MICROWIRE serial data output)
GS SK (MICROWIRE clock I/O)
GO INTR (an external interrupt)
There are two registers associated with each L I/O port: a
data register and a configuration register. Therefore, each L
1/0 bit can be individually configured under software control
as shown below:
Portl
Conflg.
Portl
Data
Portl
Setup
0
0
1
1
0
1
0
1
Hi-Z Input (TRI-STATE)
Input With Weak Pull-Up
Push-Pull "0" Output
Push-Pull "1" Output
G6 SI (MICROWIRE serial data input)
G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input (general purpose input)
Pins G1 and G2 currently do not have any alternate functions.
PORT D is a four bit output port that is set high when RESET goes low.
The D2 pin is sampled at reset. If it is held low at reset the
COP8720C enters the ROM less mode of operation.
Functional Description
Three data memory address locations are allocated for
these ports, one for data register, one for configuration register and one for the input pins.
Figure 1 shows the block diagram of the internal architecture. Data paths are illustrated in simplified form to depict
how the various logic elements communicate with each other in implementing the instruction set of the device.
PORT G is an 8-bit port with 6 I/O pins (GO-G5) and 2 input
pins (G6, G7). All eight G-pins have Schmitt Triggers on the
inputs. The G7 pin functions as an input pin under normal
operation and as the continue pin to exit the HALT mode.
There are two registers with each I/O port: a data register
and a configuration register. Therefore, each I/O bit can be
Individually configured under software control as shown below.
PortG
Conflg.
PortG
Data
PortG
Setup
0
0
1
Hi-Z Input (TRI-STATE)
Input With Weak Pull-Up
Push-Pull "0" Output
Push-Pull "1" Output
0
1
1
0
1
AlU AND CPU REGISTERS
The ALU can do an 8-bit addition, subtraction, logical or
shift operation in one cycle time.
There are five CPU registers:
A is the 15-bit Program Counter register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
8 is the 8-bit address register, can be auto incremented or
decremented.
X is the S-bit alternate address register, can be incremented
or decremented.
SP is the 8-bit stack pointer, points to subroutine stack (in
RAM).
Three data memory address locations are allocated for
these ports, one for data register, one for configuration register and one for the input pins. Since G6 and G7 are input
only pins, any attempt by the user to set them up as outputs
by writing a one to the configuration register will be disregarded. Reading the G6 and G7 configuration bits will
8, X and SP registers are mapped into the on chip RAM.
The 8 and X registers are used to address the on chip RAM.
The SP register is used to address the program counter
stack in RAM during subroutine calls and returns.
2-41
•
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......
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,....
Functional Description
(Continued)
N
co
PROGRAM MEMORY
oo
Program memory for the COP8720C consists of two modules-the 1 Kbyte program EEPROM and the 256 byte
ROM which contains the firmware routines for reading and
programming the EEPROM.
....
D.
......
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....
N
CO
D.
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registers (except the A and PC) are memory mapped; therefore, I/O bits and register bits in addition to the normal data
RAM can be directly and individually set, reset and tested .
MEMORY
The COP8720C contains 1 Kbyte of Program EEPROM, 64
bytes of on-chip RAM and Registers, I/O, 64 bytes of Data
EEPROM and 256 bytes of firmware ROM.
DATA EEPROM
The COP8720C provides 64 bytes of EEPROM for nonvolatile data memory. The data EEPROM can be read and programmed in exactly the same way as the RAM. All instructions that perform read and write operations on the RAM
work similarly upon the data EEPROM.
A data EEPROM programming cycle is initiated by an instruction such as X, LD, SBIT or RBIT. The EE memory
support circuitry sets the BsyERAM flag in the EECR register immediately upon beginning a data EEPROM write cycle.
It will be automatically reset by the hardware at the end of
the data EEPROM write cycle. The application program
should test the BsyERAM flag before attempting a write operation to the data EEPROM. A second EEPROM write operation while a write operation is in progress will be ignored.
The Werr flag in the EECR register is set to indicate the
error status.
Memory locations in the 1 Kbyte program EEPROM module
are accessed by the address register, EEAR, and the data
register, EROMDR. The EEAR is mapped into the address
locations E2 and E3. The EROMDR register is located at
the address E1.
Under normal conditions, the program EEPROM and the
ROM are addressed by the PC and their contents go to the
instruction bus. During the EEPROM program and verify cycle, the EEPROM is treated as data memory while the
COP8720C is executing out of the firmware ROM. The
EEPROM is addressed through the EEAR register. The
EROMDR register holds the data read back from the
EEPROM location during a verify cycle and holds the data
to be written into the EEPROM location during a program
cycle. The veritY cycle takes 1 instruction cycle and the
write cycle takes 20 ms.
SIGNATURE AND OPTION REGISTERS
The COP8720C provides a set of six additional registers
implemented with EEPROM cells-the Signature and Option registers.
The Signature register is a four-byte register provided for
storing ROM code rev. numbers or other application specific
information. The Signature register is shadowed behind the
data EEPROM cells at addresses 8C to 8F Hex. Two test
modes are provided to allow the Signature register to be
read or programmed.
The Option register consists of two bytes shadowed behind
the addresses 89 and 8B Hex. The Option register allows
the COP8720C to be programmed to accurately emulate the
different mask options available on the COP820C and the
COP8620C.
Accesses to the program EEPROM is controlled by two
flags, AEN and PEN, in the control register, EECR.
AEN PEN
Access Type
o 0 Normal
o
Normal
o EEPROM Read Cycle
EEPROM Write Cycle
To prevent accidental erasures and over-write situations the
application program should not set the AEN and PEN flags
in the EECR register. The COP8720C supports application
accesses to the EEPROM module via two subroutines in the
firmware ROM-an EEPROM read and an EEPROM write
subroutine. To program an EEPROM memory location, the
user loads the EECR and EROMDR registers and invokes
the write subroutine at the address 40CO Hex. To read an
EEPROM location the user loads the EEAR register with the
address of the EEPROM memory location and invokes the
read subroutine at the address 40D4 Hex. The read subroutine returns the contents of the addressed EEPROM location in the EROMDR register.
1=1 =1 =1 =1 Ro~:mu I:c 1:AL 1ER:emul::::
ROMemu: When set, the Data EEPROM and all the EE related registers become inaccessible. Thus, the EE registers
look like nonexistent memory locations when addressed by
the application program and the Program EEPROM behaves just like ordinary ROM. Thus, setting the ROMemu bit
allows the COP8720C to emulate the ROM based
COP820C with 100% accuracy.
ERAemu: When set, the EEAR and the EROMDR become
inaccessible. Thus, by setting the ERAemu bit allows the
CP08720C to accurately emulate the COP8620C. Note that
the ERAemu is a subset of the ROMemu flag. ROM emu is in
effect when both the flags are set.
HS, RC, XTAL: These three bits allow the COP8720C to
emulate the clock options of the COP820C. Note that only
five out of the possible eight combinations are legal-the
combinations OE, OC and 06 are illegal combinations.
DATA MEMORY
The data memory for the COP8720C consists of on-chip
RAM, EEPROM, I/O and registers. Data memory is accessed directly by the instruction or indirectly by the B, X
and SP registers.
RAM
The COP8720C has 64 bytes of RAM. Sixteen bytes of RAM
are mapped as "registers" that can be loaded efficiently,
decremented and tested. Three specific registers: B, X and
SP are mapped into this space, the other bytes are available
for general use.
The instruction set of the COP8720C permits any bit in the
data memory to be set, reset or tested. All I/O and the
EECR and EE SUPPORT CIRCUITS
The EEPROM program and data modules share a common
set of EE support circuits to generate all necessary high
2-42
(')
Functional Description
0
"'C
(Continued)
co
......
N
<:)
All
ROY
24
All
ROY
All
iffi
Al0
iffi
23
Al0
iffi
Al0
(')
A9
WR
A9
0
A8
Ne
3
A8
RESET
RESET
RESET
vee
eND
eND
eND
ADO
AD7
Ne
Ne
Ne
Ne
16
AD7
Ne
10
15
AD6
Ne
Ne
A02
11
14
ADS
ADO
A07
A03
12
13
AD-'
ADI
AD6
AD6
AD5
ADI
AD3
TLIDD/9l08-18
AD5
AD2
TL/DD/9108-l9
AD3
14
15
AD4
TL/DD/9l08-20
FIGURE 4. Pinouts for the COP8720C In Programming Mode
voltage programming pulses. Each programming cycle consists of a 10 ms erase cycle followed by a 10 ms write cycle
for each byte. An EEPROM cell in the erase state is read
out as a 0 and the written state is read out as a 1. Since the
two EE modules share the support circuitry, programming
the two modules at the same time is not allowed.
The EECR register provides control, status and test mode
functions for the EE modules.
EECR Register Bit Assignment
Wr
Test Mode Codes
I
I
AEN
I
I
PEN
Rd Test Mode Codes BsyEROM BsyERAM AEN VLKO Werr
Werr
PEN
VLKO
AEN
7
6
5
4
3
2
1
BsyERAM
Set to 1 when data EEPROM is being written, is
automatically reset by the hardware upon completion of the write operation.
BsyEROM
Set to 1 when program EEPROM is being written, is automatically reset by the hardware
upon completion of the write operation.
Bits 3 to 7 of the EECR are used for encoding various
EEPROM module test modes, most of which are for factory
manufacturing tests. Two of the test modes used for accessing the signature and option registers are described in a
previous section. The EE test modes are activated byapplying high voltage to the RESET pin. Some of the test modes,
if activated improperly, can make the part inoperable. These
test modes are reserved for use by the manufacturer only.
The EECR register bit assignments are shown below.
Bi t
(')
ROY
0
The EECR register is cleared by RESET. EECR is mapped
into address location EO.
Write Error. Writing to data EEPROM while a
previous write cycle is still busy, that is
BsyERAM is not 0, causes Werr to be set to 1
indicate error status. Werr is cleared by writing
a 0 into·it.
When either BsyERAM or BsyEROM is set to 1, that is an
EEPROM programming cycle is in progress, the AEN bit is
locked up and cannot be changed by the processor.
EXTERNALLY PROGRAMMING THE PROGRAM
EEPROM
A program EEPROM programming cycle is
started by setting PEN and AEN to 1 at the
same time. PEN is "written thru". It is not
latched.
As shown in the previous section, the COP8720C permits
the program EEPROM memory module to be altered under
program control via the EECR register. To facilitate ease of
development the COP8720C also provides an external
mode of loading executable code into the program
EEPROM module.
EECR bit 1 is read as the lock out indicator. A
low Vcc detector is enabled at the start of the
EE programming cycle. If it finds Vce less than
VLKO, the VLKO status bit is set and the write
cycle is aborted. The VLKO status bit stays
latched until the start of another EE programming cycle.
This section describes the programming method for the
COP8720C EEPROM.
Programming the COP8720C EEPROM or the special registers is initiated by applying VPRG to the RESET pin. Control
gets transferred to the firmware ROM when VPRG is applied
to the RESET pin. The program contained in the firmware
ROM sets up the I/O of the COP8720C to simulate the I/O
requirements of a 2-kbyte memory device. This is done by
setting up the COP8720C I/O as eight bits of address/data
lines, three address lines, read/write control and a ready
signal.
AEN controls the program EEPROM address/
data interface. when AEN is 0, the EEPROM is
the program memory. It is adressed by PC, and
its output data goes onto the instruction bus.
When AEN is set to 1, the EEPROM becomes
data memory. It is addressed by the EEAR, and
it is accessed from the EROMDR.
2-43
.......
"'C
co
......
N
......
(')
.......
(')
0
"'C
co
......
N
N
(')
o
N
N
.....
co
DO
o
.......
o
.....
N
......
co
D-
O
o
.......
o
o
N
......
CO
D-
O
o
Functional Description (Continued)
Figure 4 shows the three packages and the associated 1/0.
The pin descriptions are as follows:
Vee
Positive 5V Power Supply
GND
Ground
RESET
Active low Reset Input
CKI
Clock Input
ADO-AD?
Multiplexed AddresslData Lines
A8-A 11
Address Lines
RD
Active low Read Strobe
WR
Active High Write Strobe
RDY
Active High Ready Output
The firmware ROM program allows the user to reference
the special registers as EEPROM memory locations in the
address range 2048-2070 decimal. The following mapping
is used:
Signature Register # 1 at EEPROM address 800 Hex
Signature Register # 2 at EEPROM address 801 Hex
Signature Register # 3 at EEPROM address 802 Hex
Signature Register #4 at EEPROM address 803 Hex
in the TRI·STATE mode and the Port D is set high. The PC,
PSW and CNTRl registers are cleared. The data and con·
figuration registers for Ports l & G are cleared.
The external RC network shown in Figure 5 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes. It is recommended that the
components of the RC network be selected to provide a
RESET delay of at least five times the power supply rise
time or the minimum RESET pulse width, whichever is
greater.
P + -......- - - . . . . . ,
o
vee
W
E
R
S
U
P
P
L
Y
GNO
TL/DD/9108-9
FIGURE 5. Recommended Reset Circuit
OSCILLATOR CIRCUITS
Figure 6 shows the three clock oscillator configurations
available for the COP8720C.
Option Register # 1 at EEPROM address 804 Hex
Option Register # 2 at EEPROM address 805 Hex
Note that in order to reference these registers the user must
come in with addresses in the range 800 Hex to 805 Hex.
A. CRYSTAL OSCILLATOR
The COP8?20C can be driven by a crystal clock. The crystal
network is connected between the pins CKI and CKO.
Table I shows the component values required for various
standard crystal values.
PROGRAMMING STEPS
The program mig host has to go through the following steps
for the write and verify cycles. (See Figure 2)
WRITE:
1. Power is applied with the RESET and WR pins low and
the RD high.
B. EXTERNAL OSCILLATOR
CKI can be driven by an external clock signal. CKO is available as a general purpose input and lor HALT restart con·
trol.
2. RESET is then brought up to Vprg within 1 ,.,.s.
3. The lower byte of the address to be written into is applied
to the pins ADO-AD7 and the upper 3 bits of the address
applied to the pins A8-A 11.
C. RIC OSCILLATOR
CKI is configured as a single pin RC controlled Schmitt trig·
ger oscillator. CKO is available as a general purpose input
and lor HALT restart control.
Table II shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
4. Observing the setup times, WR is brought high.
5. The data to be programmed is applied to the pins ADOAD?
6. The RDY signal from the COP8720C goes low. This indio
cates that the WR and data on ADO-AD? have been ac·
cepted and these inputs can be removed.
7. The programming host must now either wait for the RDY
signal to go high or wait at least 20 ms before initiating a
new programming cycle.
VERIFY:
1. Power is applied with RESET and WR pins held low and
the RD high.
2. The RESET pin is brought up to Vprg within 1 ,.,.s.
3. The lower byte of the address to be read is applied to the
pins ADO-AD? and the upper three bits to the pins AD8AD11.
4. Observing setup times the RD pin is brought low.
5. After a time T7, the RDY signal from the COP8720C goes
low and data is ready for the host on the pins ADO-AD7.
The data stays until the RD signal goes back high after
which the RDY signal will go back high.
6. The host must wait for the RDY signal to go back high
before the next read cycle is initiated.
RESET
The RESET input when pulled low initializes the microcon·
troller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the ports land G are placed
A
CKO
CKI
R2
W
RESTART
J1..f"
Rl
0
EXTERNAL
CLOCK
~Cl
":"
TL/DD/91 08-1 0
FIGURE 6. Crystal and R-C Connection Diagrams
OSCILLATOR OPTIONS
The COP8720C can be driven by clock inputs between DC
and 20 MHz. For low input clock frequencies (~ 5 MHz) the
instruction cycle frequency can be selected to be the input
clock frequency divided by 10. This mode is known as the
Normal Mode.
2-44
Functional Description
(Continued)
TABLE I. Crystal Oscillator Configuration, TA = 25°C
R1
(k!l)
R2
(Mn)
C1
(pF)
C2
(pF)
CKI Freq
(MHz)
Conditions
0
0
0
0
1
1
1
1
30
30
30
200
30-36
30-36
30-36
100-150
20
10
4
0.455
Vee = 5V
Vee = 5V
Vee = 2.5V
Vee = 2.5V
TABLE II. RC Oscillator Configuration, TA = 25°C
R
(k!l)
C
(pF)
CKI Freq.
(MHz)
Instr. Cycle
(J,Ls)
Conditions
3.3
5.6
6.8
82
100
100
2.8-2.2
1.5-1.1
1.1-0.8
3 t06
6 to 11
7.5 to 18
Vee = 5V
Vee = 5V
Vee = 2.5V
For oscillator frequencies that are greater than 5 MHz the
chip must run with a divide by 20. This is known as the High
Speed mode.
To reduce the total current drain, each of the above components must be minimum.
The chip will draw the least current when in the normal
mode. The high speed mode will draw additional current.
The RIC mode will draw the most. Operating with a crystal
network will draw more current than an external squarewave. Switching current, governed by the equation below,
can be reduced by lowering voltage and frequency. Leakage current can be reduced by lowering voltage and temperature. The other two items can be reduced by carefully
designing the end-user's system.
The COP820C microcontroller has five mask options for
configuring the clock input. To emulate these mask options
3 bits must be set in the Option register.
HS
RC
XTAL
Mask Option
1
0
1
0
0
0
0
0
0
1
1
1
0
0
0
High Speed Crystal
Normal Mode Crystal
High Speed External
Normal Mode External
RIC Oscillator
12 = C x V x f
Where
C = equivalent capacitance of the chip. (TBD)
The CKI and CKO pins are automatically configured upon
selecting a particular option.
-
-
V = operating voltage
f = CKI frequency
High Speed Crystal (CKI/20) CKO for crystal configuration
Normal Mode Crystal (CKI/10) CKO for crystal configuration
The typical capacitance for the COP820C is TBD pF.
Some sample current drain values at Vee = 6Vare:
High Speed External (CKI/20) CKO available as G7 input
Normal Mode External (CKI/10) CKO available as G7
input
RIC (CKI/10) CKO available as G7 input
Where, G7 can be used either as a general purpose input or
as a control input to continue from the HALT mode.
1) Oscillator operating mode-11
2) Internal switching current-12
3) Internal leakage current-13
4) Output source current-14
5) DC current caused by external input not at Vee or GND15
Thus the total current drain, It is given as
12
+
13
It (rnA)
1
3
5
33
13
2.2
1.2
0.2
<0.01
-
The COP8720C supports a power saving mode of operation: HALT. The controller is placed in the HALT mode by
setting the G7 data bit, alternatively the user can stop the
clock input. In the HALT mode all internal processor activities including the clock oscillator are stopped. The fully static architecture freezes the state of the controller and retains
all information until continuing. In the HALT mode, power
requirements are minimal as it draws only leakage currents
and output current. The applied voltage (Vee> may be decreased down to Vr (minimum RAM retention voltage) without altering the state of the machine.
The total current drain of the chip depends on:
+
Inst. Cycle (J,Ls)
20
3.58
2
0.3
o (HALT)
HALT MODE
CURRENT DRAIN
It = 11
CKI (MHz)
+ 14 + 15
There are two ways to exit the HALT mode: via the RESET
or by the CKO pin. A low on the RESET line reinitializes the
2-45
o
N
N
......
co
a..
oo
.......
o
.,...
N
......
co
a..
oo
.......
r---------------------------------------------------------------------------~
Functional Description
(Continued)
INTERRUPTS
A maskable interrupt on external GO input (positive or negative edge sensitive under software control).
N
A maskable interrupt on timer carry or timer capture .
......
CO
a..
oo
The COPS720C incorporates a hardware mechanism that
allows it to detect illegal conditions which may occur from
coding errors, noise and 'brown out' voltage drop situations.
Specifically it detects cases of executing out of undefined
ROM area and unbalanced stack situations.
Reading an undefined ROM location returns 00 (hexadecimal) as its contents. The opcode for a software interrupt is
also '00'. Thus a program accessing undefined ROM will
cause a software interrupt.
Reading an undefined RAM location returns an FF (hexadecimal). The subroutine stack on the COPS720C grows down
for each subroutine call. By initializing the stack pointer to
the top of RAM, the first unbalanced return instruction will
cause the stack pointer to address undefined RAM. As a
result the program will attempt to execute from FFFF (hexadecimal), which is an undefined ROM location and will trigger a software interrupt.
The COPS720C has a sophisticated interrupt structure to
allow easy interface to the real world. There are three possible interrupt sources, as shown below.
o
o
DETECTION OF ILLEGAL CONDITIONS
microcontroller and start executing from the address
OOOOH. A low to high transition on the CKO pin causes the
microcontroller to continue with no reinitialization from the
address following the HALT instruction.
A non-maskable software/error interrupt on opcode zero.
INTERRUPT CONTROL
The GIE (global interrupt enable) bit enables the interrupt
function. This is used in conjunction with ENI and ENTI to
select one or both of the interrupt sources. This bit is reset
when interrupt is acknowledged.
MICROWIRE/PLUSTM
ENI and ENTI bits select external and timer interrupt respectively. Thus the user can select either or both sources
to interrupt the microcontroller when GIE is enabled.
MICROWIRE/PlUS is a serial synchronous communications interface. The MICROWIRE/PlUS capability enables
the COPS720C to interface with any of National Semiconductor's Microwire peripherals (i.e. AID converters, display
drivers, etc.) and with other microcontrollers which support
the MICROWIRE interface. It consists of an S-bit serial shift
register (SIO) with serial data input (SI), serial data output
(SO) and serial shift clock (SK). Figure 8 shows the block
diagram of the MICROWIRE/PlUS interface.
The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIRE
arrangement with the internal clock source is called the
Master mode of operation. Similarly, operating the MICROWIRE arrangement with an external shift clock is called the
Slave mode of operation.
The CNTRl register is used to configure and control the
MICROWIRE mode. To use the MICROWIRE, the MSEl bit
in the CNTRl register is set to one. The SK clock rate is
selected by the two bits, SO and S1, in the CNTRl register.
Table III details the different clock rates that may be selected.
TABLE III
IEDG selects the external interrupt edge (0 = rising edge, 1
= falling edge). The user can get an interrupt on both rising
and falling edges by toggling the state of IEDG bit after each
interrupt.
IPND and TPND bits signal which interrupt is pending. After
interrupt is acknowledged, the user can check these two
bits to determine which interrupt is pending. This permits the
interrupts to be prioritized under software. The pending flags
have to be cleared by the user. Setting the GIE bit high
inside the interrupt subroutine allows nested interrupts.
The software interrupt does not reset the GIE bit. This
means that the controller can be interrupted by other interrupt sources while servicing the software interrupt.
INTERRUPT PROCESSING
The interrupt, once acknowledged, pushes the program
counter (PC) onto the stack and the stack pointer (SP) is
decremented twice. The Global Interrupt Enable (GIE) bit is
reset to disable further interrupts. The microcontroller then
vectors to the address OOFFH and continues from that address. This process takes 7 cycles to complete. At the end
of the interrupt subroutine, any of the following three instructions return the processor back to the main program: RET,
RETSK or RETI. Either one of the three instructions will pop
the stack into the program counter (PC). The stack pointer
is then incremented twice. The RETI instruction additionally
sets the GIE bit to re-enable further interrupts.
Either of the three instructions can be used to return from a
hardware interrupt subroutine. The RETSK instruction
should be used when returning from a software interrupt
subroutine to avoid entering an infinite loop.
S1
SO
SK Cycle Time
0
0
1
0
1
x
2te
4tc
Ste
where,
te is the instruction cycle clock.
EXTERNAL
INT. PIN
TO
INTERRUPT
LOGIC
TIMER
UNDERfLOW----I
SOfTWARE - - - - - - - - - - - - - - - - - '
FIGURE 7. Interrupt Block Diagram
2-46
TL/DD/9108-11
o
Functional Description
o
-a
Q)
......
(Continued)
MICROWIRE PLUS OPERATION
TABLE IV
Setting the BUSY bit in the PSW register causes the Microwire arrangement to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift.
The COP8720C may enter the MICROWIAE/PlUS mode
either as a Master or as a Slave. Figure 9 shows how two
COP8720C microcontrollers and several peripherals may be
interconnected using the MICROWIRE/PlUS arrangement.
G4
G4
GS
G6
Fun.
Fun.
Fun.
SO
Int.SK
SI
MICAOWIAE Master
TAI·STATE Int. SK
SI
MICAOWIAE Master
Ext.SK
SI
MICAOWIAE Slave
TRI·STATE Ext.SK
SI
MICAOWIAE Slave
Conflg. Conflg.
Master MICROWIRE/PLUS Operation
In the MICROWIRE/PlUS Master mode of operation the
shift clock (SK) is generated internally by the COP8720C.
The MICROWIRE Master always initiates all data exchanges. (See Figure 9.) The MSEl bit in the CNTRl register
must be set to enable the SO and SK functions onto the G
Port. The SO and SK pins must also be selected as outputs
by setting appropriate bits in the Port G configuration register. Table IV summaries the bit settings required for Master
mode of operation.
Bit
Bit
1
1
0
1
1
0
0
0
N
o
GS
SO
Operation
The COP8720C has a powerful 16-bit timer with an associated 16-bit register enabJing them to perform extensive timer functions. The timer.T1 and its register A 1 are each organized as two. 8-bit read/write registers. Control bits in the
register CNTAl allow the timer to be started and stopped
under software control. The timer-register pair can be operated in one of three possible modes.
MODE 1. TIMER WITH AUTO-LOAD REGISTER
In the MICROWIRE/PLUS Slave mode of ope~ation the SK
clock is generated by an external source. Setting the MSEl
bit in the CNTAl register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bit in the Port G configuration register. Table IV summarizes the settings required to enter the
Slave mode of operation.
In this mode qf operation the timer T1 counts down at the
instruction cycle rate. Upon underflow the value in the register R1 gets automatically reloaded into the timer which continues to count down. The timer underflow can be programmed to interrupt the microcontroller. A bit in the control
register CNTRl enables the TIO (G3) pin to toggle upon
timer underflows. This allow the generation of square-wave
outputs or pulse width modulated outputs under software
control. (See figure 10.)
The user must set the BUSY flag Irwnediately upon entering
the Slave mode. This will ensure that all data bits sent by
the Master will be shifted properly. After eight clock pulses
the BUSY flag will be cleared and the sequence may be
repeated. (See Figure 9.)
MODE 2. EXTERNAL COUNTER
In this mode, the timer T1 becomes a 16-bit external event
counter. The counter counts down upon an edge on the TIO
pin. Control bits in the register CNTAl program the counter
to decrement either on a positive edge or 'on a negative
edge. Upon underflow the contents of the register A1 are
automatically copied into the counter. The underflow can
also be programmed to generate an interrupt. (See Figure
10.)
r-------------------~~SO
1---;
~
i
REGISTER
"I
\)ArL-_ _ _l....l
B~
~ tc-+l
SHIFT CLOCK
~
~SK
MODE 3. TIMER WITH CAPTURE REGISTER
•
Timer T1 can be used to precisely measure external frequencies or events in this mode of operation. The timer T1
counts down at the instruction cycle rate. Upon the occurrence of a specified edge on the TIO pin the contents of the
timer T1 are copied into the register R1. Bits in the control
register CNTRl allow the trigger edge to be specified either
as a positive edge or as a negative edge. In this mode the
user can elect to be interrupted on the specified trigger
edge. (See Figure 11.)
1/'--"')1'
CNTRL .1
v ...._ _..
A
....
1
...____ SI
1~
8 - BIT SIO
o-a
Q)
......
N
-"
o
......
o
o-a
Q)
TIMER/COUNTER
SLAVE MICROWIRE/PLUS OPERATION
D
o
......
o
~--....,
~
TLIDD/9108-12
FIGURE 8. MICROWIRE Block Diagram
2-47
......
N
N
o
o
N
~
co
Functional Description
(Continued)
a..
o
o
.....
CHIP SELECT LINES
o
....
1
N
r-co
a..
o
o
.....
I/O
LINES
N
¢:J
o
Q
r-co
B- BIT
A/D CONVERTER
COP43X
COPS
(MASTER)
1
1
LOW
POWER
CMOS
RAM
& TIMER
COP498
1024- BIT
EEPROM
COP495
a..
oo
SI
so
! f'
! f'
1
1
! f
1
1
I/o
fREQ.
GEN. &
COUNTER
COP452L
Vf
DISPLAY
DRIVER
COP470
! f'
f'
I
1
COPS
(SLAVE)
~
SO
..... SI
--,. SK
SK
TL/DD/9108-13
FIGURE 9. MICROWIRE Application
TABLE V. Timer Operating Modes
CNTRl
Bits
Operation Mode
T Interrupt
External Counter W / Auto-Load Reg.
External Counter W / Auto-Load Reg.
Not Allowed
Not Allowed
Timer W / Auto-Load Reg.
Timer W / Auto-Load Reg.lToggle TID Out
Timer W /Capture Register
Timer W /Capture Register
Timer Carry
Timer Carry
Not Allowed
Not Allowed
Timer Carry
Timer Carry
TID Pos. Edge
TID Neg. Edge
Timer
Counts
On
765
000
001
010
01 1
100
1 01
110
111
TID Pos. Edge
TID Neg. Edge
Not Allowed
Not Allowed
tc
tc
tc
tc
TIO -...L----l~
CARRY fLAG/
OUTPUT/
INTERRUPT
TL/DD/9108-15
TL/DD/9108-14
FIGURE 10. Timer/Counter Auto
Reload Mode Block Diagram
FIGURE 11. Timer Capture Mode Block Diagram
2-48
o
Functional Description
a"tJ
(Continued)
(X)
TIMER PWM APPLICATION
Figure 12 shows how a minimal component 0/ A converter
can be built out of the Timer-Register pair in the Auto-Reload mode. The timer is placed in the "Timer with auto reload" mode and the TIO pin is selected as the timer output.
At the outset the TIO pin is set high, the timer T1 holds the
on time and the register R1 holds the signal off time. Setting
TRUN bit starts the timer which counts down at the instruction cycle rate. The underflow toggles the TIO output and
copies the off time into the timer, which continues to run. By
alternately loading in the on time and the off time at each
successive interrupt a PWM frequency can be easily generated.
I HC
I C I TPNO I ENTI IIPNO I BUSY I ENI I GIE
Bit7
BitO
Operating Modes
a"tJ
These controllers have two operating modes: Single Chip
mode and the ROMless mode. The operating mode is determined by the state of the 02 pin at power on reset.
"".....N
In the Single Chip mode, the controller functions as a self
contained microcontroller. It can address internal RAM and
ROM. All ports configured as memory mapped I/O ports.
2
o
Memory Map
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
10..00-
Address
TL/DD/9108-16
FIGURE 12. Timer Application
Contents
00 to 2F On Chip RAM Bytes
30 to 7F Unused RAM Address Space (Reads as all Ones)
Control Registers
BO to BF 64 Bytes DATA EEPROM
CNTRl REGISTER (ADDRESS X'OOEE)
CO to CF Expansion Space for I/O and Registers
The Timer and MICROWIRE control register contains the
following bits:
DO to OF
DO
01
02
03
04
05
06
07
DB-DB
S1 & SO Select the MICROWIRE clock divide-by
IEOG
External interrupt edge polarity select
MSEL
Enable MICROWIRE functions SO and SK
TRUN
Start/Stop the Timer/Counter (1 =
stop)
TC3
Timer input edge polarity select (0 = rising edge,
1 = falling edge)
(0 = rising edge, 1 = falling edge)
TC2
Selects the capture mode
TC1
Selects the timer mode
run, 0 =
I TC1 I TC2 I TC3 I TRUN I MSEL IIEOG I S1 I
BIT7
~C-OF
SO
BITO
PSW REGISTER (ADDRESS x'OOEF)
The PSW register contains the following select bits:
GIE
Global interrupt enable
ENI
External interrupt enable
BUSY MICROWIRE busy shifting
IPNO
External interrupt pending
ENTI
Timer interrupt enable
TPNO Timer interrupt pending
C
Carry Flag
HC
Half carry Flag
2-49
o
......
a"tJ
(X)
""NN
o
The COPB720C will enter the ROMless mode of operation if
the 02 pin is held at logical "0" at reset. In this case the
internal PROGRAM EEPROM is disabled and the controller
can now address up to 32 kbytes of external program memory. It continues to use the on board RAM, and DATA
EEPROM.
A SIt.lPLE D-A
CONVERTER USING
THE TIt.lER TO
GENERATE A PWt.l
OUTPUT.
(X)
o
SINGLE CHIP MODE
ROM lESS MODE
8
7
""oN
o
......
o
On Chip I/O and Registers
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Reserved for Port C
Port 0
EO to EF
EO
E1
E2
E3
E4-EB
E9
EA
EB
EC
ED
EE
EF
On Chip Functions and Registers
EECR
EROMOR
EEAR Low Byte
EEAR High Byte
Reserved
MICROWIRE Shift Register
Timer lower Byte
Timer Upper Byte
Timer Autoload Register Lower Byte
Timer Autoload Register Upper Byte
CNTRl Control Register
PSW Register
FO to FF
FC
FO
FE
On Chip RAM Mapped as Registers
X Register
SP Register
B Register
o
C\I
C\I
......
co
DO
o
......
o
.....
C\I
......
co
D-
~ddressing
Modes
C\I
......
DIRECT
The instruction contains an 8-bit address field that directly
points to the data memoiy for the operand.
D..
oo
Registers
REGISTER INDIRECT
This is the "normal" mode of addressing for the COP8720C.
The operand is the memory addressed by the B register or
X register.
CO
Instruct~~n
Set
REGISTER AND SYMBOL DEFINITIONS
O
o
......
o
o
tion). There are no 'pages' when using JP, all 15 bits of PC
are used.
Memory Map (Continued)
Reading unused memory locations below 7FH will return all
ones. Reading other unused memory locations will return
undefined data.
IMMEDIATE
The instruction contains an 8-bit immediate field as the operand.
REGISTER INDIRECT
(AUTO INCREMENT AND DECREMENT)
"
A
B
X
SP
8-bit Accumulator register
8-bit Address register
8-bit Address register
8-bit Stack pointer register
PC
PU
PL
C
HC
GIE
15-bit Program counter register
upper 7 bits of PC
lower 8 bits of PC
1-bit ~f PSW register for carry
Half Carry
:I-bit of PSW register for global interrupt enable
Symbols
[B]
[X]
Mem
Meml
Imm
Reg
This is a register indirect mode that automatically increments or decrements the B or X register after executing the
instruction.
RELATIVE
This mode is used for the JP instruction, the instruction field
is added to the program counter to get the new program
location. JP has a range of from -31 to +32 to allow a one
byte relative jump (JP + 1 is implemented by a NOP instruc-
Bit
..~
2-50
Memory indirectly addressed by B register
Memory indirectly addressed by X register
Direct address memory or [B]
Direct address memory or [B] or Immediate data
8-bit Immediate data
Register memory: addresses FO to FF (Includes B, X
and SP)
Bit number (0 to 7)
\,.oaded with
Exchanged with
Instruction Set (Continued)
Instruction Set
ADD
ADC
add
add with carry
SUBC
subtract with carry
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
Logical AND
Logical OR
Logical Exclusive-OR
IF equal
IF greater than
IF B not equal
Decrement Reg. ,skip if zero
Set bit
RBIT
Reset bit
IFBIT
Ubit
X
LDA
LDmem
LD Reg
Exchange A with memory
Load A with memory
Load Direct memory Immed.
Load Register memory Immed.
Mem
A A Meml
Imm
Mem Reg +- Imm
X
X
LOA
LDA
LDM
Exchange A with memory [B)
Exchange A with memory [X)
Load A with memory [B)
Load A with memory [X)
Load Memory Immediate
A A A -
CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
RC
IFC
IFNC
Clee-rA
IncrementA
Decrement A
Load A indirect from ROM
DECIMAL CORRECT A
ROTATE A RIGHT THRU C
Swap nibbles of A
SetC
ResetC
IfC
IfnotC
A-O
A A+ 1
A A-1
A ROM(PU,A)
A BCD correction (follows ADC, SUBC)
C A7 .,. AO C
A7 ... A4 A3 ... AO
C 1,HC 1
C O,HC 0
If C is true, do next instruction
If C is not true, do next instruction
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
Jump absolute long
Jump absolute
Jump relative short
Jump subroutine long
Jump subroutine
Jump indirect
Return from subroutine
Return and Skip
Return from Interrupt
Generate an interrupt
No operation
PC ii (ii = 15 bits, 0 to 32k)
PC11 .. 0 i (i = 12 bits)
PC PC+r(ris-31to+32,not1)
[SP) PL,[SP-1) PU,SP-2,PC +- ii
[SP) PL,[SP-1) PU,SP-2,PC11.. 0 i
PL ROM(PU,A)
SP+2,PL [SP),PU [SP-1)
SP+2,PL [SP),PU [SP-1),Skipnextinstruction
SP+2,PL +- [SP),PU +- [SP-1).GIE 1
[SPI PL,[SP-11 +- PU,SP-2,PC OFF
PC-PC+1
A At· Moml
A +- A + Meml t C. C + - Carry
HC +- Half Carry
A A -I- Moml t C, C +- Carry
HC +- Half Carry
AandMeml
A A AorMeml
A AxorMoml
Comparo A and Moml, [)r) nux! If A - Meml
Compare A and Mernl, L>o next if A· Meml
Do next if lower 4 bits of B ~ Imm
Reg Reg - 1, skip if Reg goes to a
1 to bit,
Mem (bit = a to 7 immediate)
o to bit,
Mem
If bit,
Mem is true, do next instr.
(B B ± 1)
(X X ± 1)
(B B ± 1)
A [X)
(X «- X:t1)
[B) Imm(B B±1)
2·51
[B)
[X)
[B)
COP8720C/COP8721C/COP8722C
Bits 7-4
F
E
D
C
B
A
9
8
7
JP -15
JP-31
LDOFO,#i
DRSZOFO
RRCA
RC
ADCA,
#i
ADCA,
[B]
IFBIT
O,[B]
*
SUBCA,
#i
SUBC
A,[B]
IFBIT
1,[B]
*
JP -14
JP-30
LD OF1,#i
DRSZOF1
SC
*
JP -13
JP -12
JP -11
JP-29
JP-2S
JP-27
LD OF2,#i
LD OF3,#i
LDOF4,#i
DRSZOF2
DRSZOF3
JP-26
LDOF5,#i
DRSZOF6
JP-S
JP-24
LD OF7,#i
DRSZOF7
JP-7
JP-6
JP-23
JP-22
LD OFS,#i
LDOF9,#i
DRSZOFS
2
1
0
LD B, OF
IFBNEO
JSR
OOOO-OOFF
JMP
OOOO-OOFF
JP + 17
INTR
0
o
o
c
LD B, OE
IFBNE 1
JSR
0100-01FF
JMP
0100-01FF
JP + 1S
JP + 2
1
~
LD B,OD
IFBNE2
JSR
0200-02FF
JMP
0200-02FF
JP + 19
JP + 3
2
LD B,OC
IFBNE3
JSR
0300-03FF
JMP
0300-03FF
JP + 20
JP + 4
3
IFEO
A,[B]
IFBIT
2,[B]
*
XA,
[X-]
XA,
[B-]
IFGTA,
#i
IFGT
A,[B]
IFBIT
3,[B]
*
LAID
ADD A,
#i
ADD
A,[B]
IFBIT
4,[B]
CLRA
LD B,OB
IFBNE4
JSR
0400-04FF
JMP
0400-04FF
JP + 21
JP + 5
4
JID
AND A,
#i
AND
A,[B]
IFBIT
5,[B]
SWAPA
LD B,OA
IFBNE5
JSR
0500-05FF
JMP
0500-05FF
JP + 22
JP + 6
5
XA,
[X]
XA,
[B]
XORA,
#i
XOR
A,[B]
IFBIT
6,[B]
DCORA
LDB,9
IFBNE6
JSR
0600-06FF
JMP
0600-06FF
JP + 23
JP + 7
6
OR
A,[B]
IFBIT
7,[B]
IFBNE 7
JMP
0700-07FF
JP + S
7
*
JSR
0700-07FF
JP + 24
*
ORA,
#i
LDB,S
*
IFC
SBIT
O,[B]
RBIT
O,[B]
LDB,7
IFBNES
JSR
OSOO-OSFF
JMP
oSOO-OaFF
JP + 25
JP + 9
S
*
LDA,
#i
IFNC
JSR
0900-09FF
JMP
0900-09FF
JP + 26
JP + 10
9
*
RBIT
1,[B]
IFBNE9
*
SBIT
1,[B]
LDB,6
*
*
LDOF6,#i
3
IFEOA,
#i
DRSZOF5
JP-25
4
XA,
[B+]
DRSZOF4
JP-9
o
-g
5
XA,
[X+]
*
JP -10
6
NOP
DRSZOF9
LDOFA,#i
DRSZOFA
LDA,
[X+]
LDA,
[B+]
LD
[B+ l,#i
INCA
SBIT
2,[B]
RBIT
2,[B]
LDB,5
IFBNEOA
JSR
OAOO-OAFF
JMP
OAOO-OAFF
JP + 27
JP + 11
A
JP-4
JP-20
LDOFB,#i
DRSZOFB
LDA,
[X-]
LDA,
[B-]
LD
[B-],#i
DECA
SBIT
3,[B]
RBIT
3,[B]
LDB,4
IFBNEOB
JSR
OBOO-OBFF
JMP
OBOO-OBFF
JP + 2S
JP + 12
B
JP-3
JP -19
LDOFC,#i
DRSZOFC
LDMd,
#i
JMPL
XA,Md
SBIT
4,[B]
RBIT
4,[B]
LDB,3
IFBNEOC
JSR
OCOO-OCFF
JMP
OCOO-OCFF
JP + 29
JP +13
C
JP-2
JP -1S
LDOFD,#i
DRSZOFD
DIR
JSRL
LDA,
Md
RETSK
SBIT
5,[B]
RBIT
5,[B]
LDB,2
IFBNEOD
JSR
ODOO-ODFF
JMP
ODOO-ODFF
JP + 30
JP +14
D
JP -1
JP -17
LDOFE,#i
DRSZOFE
LDA,
[X]
LDA,
[B]
LD
[Bl, #i
RET
SBIT
6, [B]
RBIT
6, [B]
LD B, 1
IFBNEOE
JSR
OEOO-OEFF
JMP
OEOO-OEFF
JP + 31
JP +15
E
JP-O
JP -16
LDOFF,#1
DRSZOFF
RETI
JSR
OFOO-OFFF
JMP
OFOO-OFFF
JP + 32
JP + 16
F
*
RBIT
7,[B]
IFBNEOF
*
SBIT
7,[B]
LDB,O
*
is the immediate data
Md is a directly addressed memory location
• is an unused opcode (see following table)
Co)
I
o
JP -21
where,
m
;:;:
(/)
JP-5
*
m
r
Instruction Execution Time
o
o
Bytes and Cycles per
Instruction
Most instructions are single byte (with immediate addressing mode instruction taking two bytes).
-a
(X)
The following table shows the number of bytes and cycles
for each instruction in the format of byte/cycle (a cycle is
1 JJ.s at 20 MHz).
Most single instructions take one cycle time (1 JJ.s at
20 MHz) to execute.
.......
o
o
.......
I\)
See the BYTES and CYCLES per INSTRUCTION table for
details.
o
o-a
(X)
.......
I\)
.....
o
o
[B)
Direct
Immed.
.......
ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
o-a
SBIT
RBIT
IFBIT
1/1
1/1
1/1
3/4
3/4
3/4
(X)
.......
I\)
I\)
o
1/3
Memory Transfer Instructions
Register
Register Indirect
Indirect Direct Immed.
Auto Incr & Decr
[B) [X]
[B+, B-] [X+,X-]
XA,·
1/1 1/3
LDA,·
1/1 1/3
LDB,lmm
LD B,lmm
2/2
LDMem,lmm
LDReg,lmm
• =
2/3
2/3
2/2
1/1
2/3
3/3
1/3
1/3
(If B < 16)
(If B > 15)
2/2
2/3
> Memory location addressed by B or X or directly.
Instructions Using A & C
CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
RC
IFC
IFNC
1/2
1/2
Transfer of Control Instructions
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
2-53
3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/7
1/1
fII
o
N
N
1"0CC)
a..
o
o
......
o
.....
N
1"0-
Bytes and Cyles per
Instruction (Continued)
products. These include COPs, and the HPC family of products. The MOLE consists of a BRAIN Board, Personality
Board and optional host software.
The following table shows the instructions assigned to unused opcodes. This table is for information only. The operations performed are subject to change without notice. Do
not use these opcodes.
The purpose of the MOLE is to provide the user with a tool
to write and assemble code, emulate code for the target
microcontroller and assist in both software and hardware
debugging of the system.
It is a self contained computer with its own firmware which
provides for all system operation, emulation control, communication, PROM programming and diagnostic operations .
CC)
a..
o
o
......
o
o
N
1"0-
CC)
a..
o
o
Unused
Opcode
Instruction
60
61
62
63
67
8C
99
9F
A7
A8
NOP
NOP
NOP
NOP
NOP
RET
NOP
LO [B], #i
XA, [B]
NOP
Unused
Opcode
Instruction
A9
AF
B1
B4
B5
B7
B9
BF
NOP
LOA, [B]
C - . HC
NOP
NOP
XA, [X]
NOP
LOA, [X]
To program the COP8720C, a special adapter board is provided. This adapter board contains a socket for the
COP8720C and plugs directly into the MOLE prom programmer.
It contains three serial ports to optionally connect to a terminal, a host system, a printer or a modem, or to connect to
other MOLEs in a multi-MOLE environment.
MOLE can be used in either a stand alone mode or in conjunction with a selected host system using PC-DOS communicating via a RS-232 port.
How to Order
Development Support
To order a complete development package, select the section for the microcontroller to be developed and order the
parts listed.
MOLE DEVELOPMENT SYSTEM
The MOLE (Microcomputer On Line Emulator) is a low cost
development system and emulator for all microcontroller
Development Tools Selection Table
Mlcrocontroller
COP820/
COP840
Order
Part Number
Description
Includes
Manual
Number
MOLE-BRAIN
Brain Board
Brain Board Users Manual
42040818S-001
MOLE-COPS-PB 1
Personality Board
COP820/S40 Personality Board
Users Manual
420410S06-001
MOLE-COPS-IBM
Assembler Software for IBM
COP800 Software Users Manual
and Software Disk
PC-DOS Communications
Software Users Manual
420410703-001
Programmer's Manual
2-54
424410527-001
420040416-001
420410703-001
o
o."
Development Support (Continued)
co
.....
DIAL-A-HELPER
ORDER PIN: MOLE-DIAL-A-HLP
I\)
Dial-A-Helper is a service provided by the MOLE (Microcontroller On Line Emulator) applications group. It consists of
both an electronic bulletin board information system and a
method by which applications can take control of a MOLE
Development System at a remote site via modem in order to
resolve any problems.
Information System Package Contains:
Dial-A-Helper User's Manual Pin
Public Domain Communications Software
o
'"
o
INFORMATION SYSTEM
The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION mode
that can be used to search out and retrieve application data
about NSC Microcontrollers. The user needs as a minimum,
a Dumb terminal, 300 or 1200 baud Modem, and a telephone.
If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk for
later use.
Voice:
Modem:
o
o
."
co
FACTORY APPLICATIONS SUPPORT
Dial-A-Helper also provides immediate factory applications
support. If a user is having difficulty in getting a MOLE to
operate in a particular mode or something peculiar is occurring, he can contact us via his system and modem. He can
leave messages on our electronic bulletin board, which we
will respond to, or he can arrange for us to actually take
control of his system via modem for debugging purposes.
The applications group can then cause his system to execute various commands and try to resolve the customer's
problem by actually getting the customer's system to respond. Both parties see exactly what is occurring, as it is
happening.
This allows us to respond in minutes when applications help
is needed.
(408) 721-5582
(408) 739-1162
Baud:
300 or 1200 Baud
Setup:
Length: 8-Bit
Parity: None
Stop Bit: 1
Operation: 24 Hours, 7 Days
Dial-A-Helper
------------------------.
MOLE
HOST
COMPUTER
----------------------_
..
USER SITE
.----------------------- ..
NATIONAL SEMICONDUCTOR SITE
TL/DD/9108-23
2-55
.....
.....
I\)
o
o
'"
o
."
co
.....
o
I\)
I\)
-J ,----------------------------------------------------------------------------------,
o
: ~National
~o D Semiconductor
ADVANCE
INFORMATION
COP888CL
Single-Chip microCMOS Microcontroller
General Description
The COP888 family of microcontrollers uses an 8-bit single
chip core architecture fabricated with National Semiconductor's M2CMOSTM process technology. The COP888CL is a
member of this expandable 8-bit core processor family of
microcontrollers.
(Continued)
Features
•
•
•
•
•
•
•
•
•
•
•
Low cost 8-bit microcontroller
Fully static CMOS, with low current drain
Two power saving modes: HALT and IDLE
1 ,...s instruction cycle time
4096 bytes on-board ROM
128 bytes on-board RAM
Single supply operation: 2.5V -6V
MICROWIRE/PLUSTM serial 1/0
Watch Dog and Clock Monitor logic
Idle Timer
Two 16-bit timers, each with two 16-bit registers supporting:
- Processor Independent PWM mode
- External Event counter mode
- Input Capture mode
• Multi-Input Wakeup (MIWU) with optional interrupts (8)
• Ten mUlti-source vectored interrupts servicing
- External Interrupt
- Idle Timer TO
- Timers TA, TB (Each with 2 Interrupts)
- MICROWIRE/PLUS
- Multi-Input Wake Up
- Software Trap
• 8-bit Stack Pointer SP (stack in RAM)
• Two 8-bit Register Indirect Data Memory Pointers
(B and X)
• Versatile instruction set
• True bit manipulation
• Memory mapped 1/0
• BCD arithmetic instructions
• Package: 44 PCC or 40 N or 28 N or 28 PCC
- 44 PCC with 39 1/0 pins
- 40 N with 36 1/0 pins
- 28 PCC or 28 N, each with 23 1/0 pins
• Software selectable 1/0 options
- TRI-STATEC8> Output
- Push-Pull Output
- Weak Pull Up Input
- High Impedance Input
• Schmitt trigger inputs on ports G and L
• Extended temperature range: - 55°C to + 125°C
• ROM less mode for accurate emulation and external
program capability
• Single chip COP8XX piggy back emulation device
• Real time emulation and full program debug offered by
National's MOLETM Development System
Block Diagram
CPU REGISTERS
TL/DD/9766-1
FIGURE 1. COP888CL Block Diagram
2-56
o
o-a
General Description
(Continued)
It is a fully static part, fabricated using double-metal·silicon
gate microCMOS technology. Features include an 8·bit
memory mapped architecture, MICROWIRE/PLUS serial
I/O, two 16·bit timer/counters supporting three modes
(Processor Independent PWM generation, External Event
counter, and Input Capture mode capabilities), and two power savings modes (HALT and IDLE), both with a multi·
sourced wakeup/interrupt capability. This multi·sourced in·
terrupt capability may also be used independent of the
HALT or IDLE modes. Each I/O pin has software selectable
configurations. The COP888CL operates over a voltage
range of 2.5V to 6V. High throughput is achieved with an
efficient, regular instruction set operating at a maximum of 1
,...s per instruction rate. The COP888CL may be operated in
the ROM less mode to provide for accurate emulation and
for applications requiring external program memory.
Connection Diagrams
Plastic Chip Carrier
~ ~
:s
tt u 8
C1 0
Dual-In-Llne Package
~ ~ (;
C2
1
44 43 42 41 40
CKI
39
Vee
38
10/ACHO
GO
RESET
GNO
I1/ACHI
10
12/ACH2
11
13/ACH3
12
05
Vee
14/ACH4
13
04
10/ACHO
15/ACH5
14
03
16/ACH6
15
02
17/ACH7
16
01
LO
17
DO
07
«
pin
06
PLCC
I1/ACHI
12/ACH2
13/ACH3
14/ACH4
TL/DD/9766-2
Top View
Order Number COP888CL-XXX/V
See NS Plastic Chip Package Number V44A
TL/DD/9766-4
Top View
Order Number COP888CL·XXXIN
See NS Molded Package Number N40A
Dual-In-Llne Package
Plastic Chip Carrier
~ ~
:s
C1
~ ~
CKI
(;
25
Vee
10/ACHO
28 pin
PLCC
I1/ACHI
28
G4
G5
G6
GO
24
RESET
G7
23
GNO
CKI
22
03
Vee
G3
G2
3
Gl
GO
RESET
6
28 pin
GNO
DIP
21
02
10/ACHO
15
10
20
01
LO
11
19
DO
I1/ACHI
14
01
15
DO
14
LO
03
11
L7
L6
TLlDD/9766-3
L2
Top View
L3
Order Number COP884CL-XXX/V
See NS Plastic Chip Package Number V28A
L5
14
15
L4
TLlDD/9766-5
Top View
"Note: Unused pins must be connected to GND.
Order Number COP884CL·XXXIN
See NS Molded Package Number N28A
FIGURE 2. COP888CL Connection Diagrams
2·57
co
co
co
o
r-
....I
o
~
co
Connection Diagrams (Continued)
~
COP888CL Pinouts for 28-, 40- and 44-Pln Packages
o
Type
Port
LO
L1
L2
L3
L4
L5
L6
L7
GO
G1
G2
G3
G4
G5
G6
G7
DO
D1
D2
D3
10
11
12
13
14
15
16
17
D4
D5
06
D7
CO
C1
C2
C3
C4
C5
C6
C7
Unused
Unused
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1/0
AIt.Fun
Alt. Fun
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
INT
T2A
T2B
17
18
25
26
27
28
1
2
3
4
19
20
21
22
7
8
WDOUT
1/0
1/0
1/0
1/0
I
CKO
0
0
0
0
I
I
I
I
I
I
I
I
0
0
0
0
T1B
T1A
SO
SK
SI
ROM DATA+
PCL+
EMUL +
PCU+
ACHO
ACH1
ACH2
ACH3
ACH4
ACH5
ACH6
ACH7
SCLOCK+
HALTSEL+
LOAD +
D DATA+
9
10
40-Pln
Pack.
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
6
23
5
24
GND
CKI
RESET
= Unbonded Pins
Only in the ROM less Mode
+ =
2-58
44-Pln
Pack.
17
17
18
19
20
21
22
23
24
35
36
37
38
3
4
5
6
25
26
27
28
9
10
11
12
13
14
18
19
20
25
26
27
28
39
40
41
42
3
4
5
6
29
30
31
32
9
10
11
12
13
14
15
16
33
34
35
36
43
44
1
2
21
22
23
24
29
30
31
32
39
40
1
2
Vee
-
28-Pln
Pack.
11
12
13
14
15
16
16
15
8
33
7
34
8
37
7
38
o
a-a
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Total Current out of GND Pin (Sink)
Supply Voltage (Vee>
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
Voltage at Any Pin
Storage Temperature Range
-0.3V to Vee + 0.3V
2000V
Total Current into Vee Pin (Source)
- 65·C to + 150·C
Note: Absolute maximum ratings indicate limits beyond
7V
ESD Susceptibility (Note 4)
110 rnA
100mA
DC Electrical Characteristics
Parameter
-40·C
~
TA
~
+ B5·C unless otherwise specified
Conditions
Min
Typ
Max
Units
6
V
0.1 Vee
V
15
2
rnA
rnA
Operating Voltage
Power Supply Ripple (Note 1)
Peak-to-Peak
Supply Current (Note 2)
CKI = 10 MHz
CKI = 4 MHz
Vee
Vee
2.5
HALT Current (Note 3)
= 6V, tc = 1 J-Ls
= 2.5V, tc = 2.5 J-Ls
Vee = 6V, CKI = 0 MHz
IDLE Current
CKI = 10 MHz
CKI = 4 MHz
Vee
Vee
<1
= 6V, tc = 1 J-Ls
= 2.5V, tc = 2.5J-Ls
Input Levels
Reset
Logic High
Logic Low
0.7 Vee
All Other Inputs
Logic High
Logic Low
0.7 Vee
Hi-Z Input Leakage
Vee
Input Pullup Current
Vee
= 6V, VIN = OV
= 6V, VIN = OV
All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
rnA
rnA
0.2 Vee
V
V
0.2 Vee
V
V
0.2 Vee
V
V
-2
+2
J-LA
40
250
J-LA
G and L Port Input Hysteresis
Sink
5
0.6
O.BVee
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
Output Current Levels
D Outputs
Source
J-LA
V
0.05 Vee
= 4V, VOH = 3.3V
= 2.5V, VOH = 1.BV
Vee = 4V, VOL = 1V
Vee = 2.5V, VOL = O.4V
0.4
0.2
rnA
rnA
10
0.2
rnA
rnA
= 4V, VOH = 2.7V
= 2.5V, VOH = 1.BV
Vee = 4V, VOH = 3.3V
Vee = 2.5V, VOH = 1.BV
Vee = 4V, VOL = 0.4V
Vee = 2.5V, VOL = O.4V
10
2.5
Vee
Vee
Vee
Vee
J-LA
J-LA
0.4
0.2
rnA
rnA
1.6
0.7
rnA
rnA
-2
TRI-STATE Leakage
100
33
+2
J-LA
Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input. CKO open. inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating In the RC and the Crystal configurations. Test conditions: All inputs tied to Vee. Land G ports in the TRISTATE mode and tied to ground. all outputs low and tied to ground. The clock monitor is disabled.
Note 4: Human body model. 100 pF through 1500n.
2-59
co
co
co
o
r-
.....
o
co
co
co
DC Electrical Characteristics
D.
o
o
Parameter
+ 85°C unless otherwise specified (Continued)
-40°C :s; TA :s;
Conditions
Typ
Min
Allowable Sink/Source
Current per Pin
D Outputs (Sink)
All others
Maximum Input Current
without Latchup
RAM Retention Voltage, Vr
500 ns Rise
and Fall Time (Min)
Instruction Cycle Time (tel
Crystal, Resonator, or
External Oscillator
R/C Oscillator
CKI Clock Duty Cycle (Note 5)
Rise Time (Note 5)
Fall Time (Note 5)
Min
4V:S; Vee:S; 6V
2.5V :s; Vee < 4V
4V:S; Vee:S; 6V
2.5V :s; Vee < 4V
1
2.5
=
=
=
rnA
3
rnA
2
V
7
pF
1000
pF
+ 85'C unless otherwise specified
-40°C:S; TA:S;
Conditions
fr
fr
fr
15
rnA
Load Capacitance on D2
Parameter
Units
200
Input Capacitance
AC Electrical Characteristics
Max
3
7.5
Max
10 MHz Ext Clock
10 MHz Ext Clock
40
Typ
Max
Units
DC
DC
DC
DC
,..,S
,..,S
60
5
5
ns
ns
,..,S
,..,S
%
Inputs
tSETUP
tHOLD
Output Propagation Delay
tpD1, tpDO
SO,SK
All Others
4V:S; Vee:S; 6V
2.5V :s; Vee < 4V
4V:s; Vee:S; 6V
2.5V :s; Vee < 4V
RL
=
2.2k, CL
=
ns
ns
ns
ns
200
500
60
150
100 pF
4V::;; Vee:S; 6V
2.5V :s; Vee < 4V
4V::;; Vee:S; 6V
2.5V :s; Vee < 4V
MICROWIRETM Setup Time (tuws)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Valid Time (tuv)
0.7
,..,S
1
2.5
,..,S
20
56
220
,..,S
ns
ns
ns
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
1
1
1
1
tc
tc
tc
tc
Reset Pulse Width
1
,..,S
Note 5: Parameter sample but not 100% tested.
2·60
o
AC Electrical Characteristics
o
(Continued)
"coco
co
or-
CKI
(+20.,.00E)
1
1___
-l tpDO
r-______-l
\~
11 (XLO)
tpDl
Ir
~l ~--tP-Dl-~-----------~-t----
1,-
12 (PHI)
--------------------~
--I tPD1
r,::
r-
'---F'--PDO
I
l
-j tPDO
I-
00.01.03 _ _ _ _ _ _ _ _ _ _ _ _ _ _--.JI~
t
\.'-----SETUP
qt~
--'X............
XXX --
10.13 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
XXXX~~...--TL/DD/9766-25
FIGURE 2a. AC Timing Diagrams In ROMless Mode
SK
tUWS!htUWH
SI
=r=r::r::
~tuv
so - - - - - - -
C
TLlDD/9766-26
FIGURE 2b. MICROWIRE/PLUS Timing
Pin Descriptions
addresses associated with the I/O ports.) Figure 3 shows
the I/O port configurations for the COP888CL. The DATA
and CONFIGURATION registers allow for each port bit to
be individually configured under software control as shown
below:
Vee and GND are the power supply pins.
CKI is the clock input. This can come from an external
source. a RIC generated OSCillator. or a crystal oscillator (in
conjunction with CKO). See Oscillator Description section.
RESET is the master reset input. See Reset Description
section.
The COP888CL contains three bidirectional 8-bit I/O ports
(C. G and L). where each individual bit may be independently configured as an input, output or TRI-STATE under program control. Three data memory address locations are allocated for each of these I/O ports. Each I/O port has two
associated 8-bit memory mapped registers. the CONFIGURATION register and the output DATA register. A memory
mapped address is also reserved for the input pins of each
I/O port. (See the COP888CL memory map for the various
2-61
CONFIGURATION
Register
DATA
Register
0
0
0
1
1
1
0
1
Port Set-Up
Hi-Z Input
(TRI-STATE Output)
Input with Weak Pull-Up
Push· Pull Zero Output
Push·Pull One Output
fII
~ r---------------------------------------------------------------------------~
o
CQ
CQ
CQ
Pin Descriptions (Continued)
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin or general purpose input (RIC clock configuration), the associated bits in the data and configuration
registers for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits
will return zeros.
Note that the chip will be placed in the HALT mode by writing a "1" to bit 7 of the Port G Data Register. Similarly the
chip will be placed in the IDLE mode by writing a "1" to bit 6
of the Port G Data Register.
a.
o
PORT L, C, AND G CONFIGURATION
o
Writing a "1" to bit 6 of the Port G Configuration Register
enables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock. The G7 configuration bit, if set
high, enables the clock start up delay when the RIC clock
configuration is used.
Conflg Reg.
Data Reg.
FIGURE 3. 110 Port Configurations
G7
CLK Delay
HALT
PORT L is an 8-bit 1/0 port. All L-pins have Schmitt triggers
on the inputs.
G6
Alternate SK
IDLE
TL/DD/9766-6
Port G has the following alternate features:
Port L supports Multi-Input Wakeup (MIWU) on all eight
pins. L4 and L5 are used for the timer input functions T2A
and T2B.
GO
INTR (External Interrupt Input)
G2
T1 B (Timer T1 Capture Input)
Port L has the following alternate features:
LO
MIWU
G3
G4
T1A (Timer T1 1/0)
SO (MICROWIRETM Serial Data Output)
L1
MIWU
G5
SK (MICROWIRE Serial Clock)
L2
MIWU
G6
SI (MICROWIRE Serial Data Input)
L3
MIWU
L4
L5
MIWU or T2A
MIWU or T2B
L6
MIWU
Port G has the following dedicated functions:
G1
WDOUT WatchDog and lor Clock Monitor
dedicated output
G7
CKO Oscillator dedicated output or general
purpose input
Port I is an 8-bit Hi-Z input port. The 40-pin device does not
have a full complement of Port I pins. The unused pins are
not terminated and must be tied to GND.
.
MIWU
L7
Port G is an 8-bit port with 5 1/0 pins (GO, G2-G5), an input
pin (G6), and two dedicated output pins (G1 and G7). Pins
GO and G2-G6 all have Schmitt Triggers on their inputs. Pin
G1 .serves as the dedicated WDOUT WatchDog output,
while pin G7 serves as the dedicated CKO clock output.
There are two registers associated with the G Port, a data
register and a configuration register. Therefore, each of the
51/0 bits (GO, G2-G5) can be individually configured under
software control.
The 28-pin device has four I pins (10, 11, 14, 15). The user
should pay attention when reading port I to the fact that 14
and 15 are in bit positions 4 and 5 rather than 2 and 3.
Port D is an 8-bit output port that is preset high when RESET goes low. The user can tie two or more D port outputs
together in order to get a higher drive.
2-62
o
o
Functional Description
"'C
The architecture of the COP888CL is modified Harvard architecture. With the Harvard architecture, the control store
program memory (ROM) is separated from the data store
memory (RAM). Both ROM and RAM have their own separate addressing space with separate address buses. The
COP888CL architecture, though based on Harvard architecture, permits transfer of data from ROM to RAM.
The instruction set of the COP888CL permits any bit in
memory to be set, reset or tested. All lID and registers on
the COP888CL (except A and PC) are memory mapped;
therefore, 1/0 bits and register bits can be directly and individually set, reset and tested. The accumulator (A) bits can
also be directly and individually tested.
Reset
CPU REGISTERS
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for Ports L, G, and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is
dedicated as the WatchDog andlor Clock Monitor error output pin. Port D is initialized high with RESET. The PC, PSW,
CNTRL, ICNTRL, and T2CNTRL control registers are
cleared. The Multi-Input Wakeup registers WKEN, WKEDG,
and WKPND are cleared. The Stack Pointer, SP, is initialized to 06F Hex.
The CPU can do an 8-bit addition, subtraction, logical or
shift operation in one instruction (td cycle time.
There are five CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
The COP888CL comes out of RESET with both the WatchDog logic and the Clock Monitor detector armed, and with
both the WatchDog service window bits set and the Clock
Monitor bit set. The WatchDog and Clock Monitor detector
circuits are inhibited during RESET. The WatchDog service
window bits are initialized to the maximum WatchDog service window of 64k to clock cycles. The Clock Monitor bit is
initialized high, and will cause a Clock Monitor error following RESET if the clock has not reached the minimum specified frequency at the termination of RESET. A Clock Monitor
error will cause an active low error output on pin G1. This
error output will continue until 16-32 to clock cycles following the clock frequency reaching the minimum specified value, at which time the G1 output will enter the TRI-STATE
mode.
SP is the 8-bit stack pointer, which points to the subroutinel
interrupt stack (in RAM). The SP is initialized to RAM address 06F with RESET.
All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).
PROGRAM MEMORY
Program memory for the COP888CL consists of 4096 bytes
of ROM. These bytes may hold program instructions or constant data (data tables for the LAID instruction, jump vectors
for the JID instruction, and interrupt vectors for the VIS instruction). The program memory is addressed by the 15-bit
program counter (PC). All interrupts in the COP888CL vector to program memory location OFF Hex.
The external RC network shown in Figure 4 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes. It is recommended that the
components of the RC network be selected to provide a
RESET delay of at least five times the power supply rise
time or the minimum RESET pulse width, whichever is
greater.
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the 1/0 registers (Configuration, Data
and Pin), the control registers, the MICROWIRE/PLUS SIO
shift register, and the various registers, and counters associated with the timers (with the exception of the IDLE counter). Data memory is addressed directly by the instruction or
indirectly by the B, X and SP pointers.
P
o
The COP888CL has 128 bytes of RAM. Sixteen bytes of
RAM are mapped as "registers" at addresses OFO to OFF
Hex. These registers can be loaded immediately, and also
decremented and tested with the DRSZ (decrement register
and skip if zero) instruction. The memory pointer registers X,
SP, and B are memory mapped into this space at address
locations OFC to OFE Hex respectively, with the other registers (other than reserved register OFF) being available for
general usage.
Vce
+
iI
L
Y
:~R
i
~~D
COP800
RESET
e
GND
TLlDD/9766-7
RC
2-63
> 5 x Power Supply Rise Time
FIGURE 4. Recommended RESET Circuit
(X)
(X)
(X)
o
r-
~
o
co
co
co
DO
o
r------------------------------------------------------------------12 = C
Oscillator Circuits
xVxf
where C = equivalent capacitance of the chip
V = operating voltage
f = CKI frequency
Some sample current drain values at Vee = 5Vare:
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input frequency is divided down by 10 to produce the instruction
cycle clock (1 ltd.
Figure 5 shows the Crystal and RIC diagrams.
EXTERNAL OSCillATOR
CKI can be driven by an external clock signal provided it
meets the specified duty cycle, rise and fall times, and input
levels.
CKI (MHz)
Inst. Cycle (J.Ls)
It (mA)
10
3.58
2
0.3
o (HALT)
1
2.8
5
33
15
5.4
3
0.45
0.005
CRYSTAL OSCillATOR
Control Registers
CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator.
CNTRl Register (Address X'OOEE)
RIC OSCillATOR
The Timer1 (T1) and MICROWIRE control register contains
the following bits:
By selecting CKI as a single pin oscillator input, a single pin
RIC oscillator circuit can be connected to it. CKO is available as a general purpose input, andlor HALT restart pin.
I
CKI
CKO
I
I
CKI
CKO
.~
I
SL 1 & SLO Select the MICROWIRE clock divide by
(00 = 2, 01 = 4, 1 x = 8)
I
....'WI'v-. Vee
IEDG
External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
MSEL
Selects G5 and G4 as MICROWIRE signals
SK and SO respectively
T1CO
Timer T1 StartlStop control in timer
modes 1 and 2
_ .... C
I
Timer T1 Underflow Interrupt Pending Flag in
timer mode 3
TLIDD/9766-9
TL/DD/9766-8
T1C1
Timer T1 mode control bit
T1C2
Timer T1 mode control bit
T1C3
Timer T1 mode control bit
FIGURE 5. Crystal and RIC Oscillator Diagrams
Current Drain
PSW Register (Address X'OOEF)
1. Oscillator operation mode-11
The PSW register contains the following select bits:
2. Internal switching current-12
3. Internal leakage current-13
4. Output source current-14
5. DC current caused by external input
not at Vee or GND-15
Thus the total current drain, It, is given as
It = 11
+
12
+ 13 +
BitO
Bit 7
The total current drain of the chip depends on:
14
+
15
GIE
Global interrupt enable (enables interrupts)
EXEN
Enable external interrupt
BUSY
MICROWIRE busy shifting flag
EXPND
External interrupt pending
T1 ENA
Timer T1 Interrupt Enable for Timer Underflow
or T1 A Input capture edge
T1 PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1, T1 Underflow in Mode 2, T1 A capture edge in mode 3)
To reduce the total current drain, each of the above components must be minimum.
The chip will draw more current as the CKI input frequency
increases up to the maximum 10 MHz value. Operating with
a crystal network will draw more current than an external
square-wave. Switching current, governed by the equation
below, can be reduced by lowering voltage and frequency.
Leakage current can be reduced by lowering voltage and
temperature. The other two items can be reduced by carefully designing the end-user's system.
C
Carry Flag
HC
Half Carry Flag
I HC IC IT1 PNDA IT1 ENA IEXPND IBUSY IEXEN I GIE I
Bit 7
Bit 0
The Half-Carry bit is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and RC (Reset
Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and RC instructions, ADC,
SUBC, RRC and RLC instructions affect the carry and Half
Carry flags.
2-64
o
Control Registers
Emulation and ROMless Modes
(Continued)
The COP888CL can address up to 32 kbytes of address
space. If at power up, 02 is held at ground, the COP888CL
executes from external memory. Port 0 is used to interface
to external program memory. The address comes out in a
serial fashion and the data from the external program memory is read back in a serial fashion. The Port 0 pins perform
the following functions.
ICNTRL Register (Address X/OOE8)
The ICNTRL register contains the following bits:
T1 ENB
Timer T1 Interrupt Enable for T1 B Input capture
edge
T1 PNOB Timer T1 Interrupt Pending Flag for T1 B capture edge
jJ.WEN
DO
01
02
Enable MICROWIRE/PLUS interrupt
jJ.WPNO MICROWIRE/PLUS interrupt pending
TOEN
Timer TO Interrupt Enable (Bit 12 toggle)
TOPNO
Timer TO Interrupt pending
LPEN
L Port Interrupt Enable (Multi-Input Wakeup/Interrupt)
03
04
05
Bit 7 could be used as a flag
06
07
The most significant bit of the data to come out on the 03
pin is a status signal.. It is used by the MOLE development
system. This "lost" output port (00-07) can be accurately
reconstructed with external components as shown in Figure
6, providing an accurate emulation.
BitO
Bit7
T2CNTRL Register (Address X/OOC6)
The T2CNTRL register contains the following bits:
T2ENB
Shifts in ROM data
Shifts out lower eight bits of PC
Places the jJ.C in the ROMless mode if grounded at
reset
Shifts out upper eight bits of PC
Data Shift Clock
HALT Mask Option select pin
(05 = 0) for HALT enable, 05 = 1 for HALT disable)
Load Clock
Shifts out recreated Port 0 data
Timer T2 Interrupt Enable for T2B Input capture
edge
The 44-pin and 40-pin versions of the COP888CL have a full
complement of the 0 Port pins and can be used in the
ROMless mode.
T2PNOB Timer T2 Interrupt Pending Flag for T2B capture edge
Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge
The 28-pin part cannot be used for emulation since it does
not have the full complement of 8 0 Port pins necessary for
entering the ROM less mode.
T2PNOA Timer T2 Interrupt Pending Flag (Autoreload RA
in mode 1, T2 Underflow in mode 2, T2A capture edge in mode 3)
Note that in the ROM less mode the 0 Port is recreated one
full clock cycle behind the normal port timings.
T2ENA
T2CO
Note: Standard parts used in the ROM less mode will operate only at a
reduced frequency (to be defined).
Timer T2 Start/Stop control in timer modes 1
and 2 Timer T2 Underflow Interrupt Pending
Flag in timer mode 3
T2C2
Timer T2 mode control bit
The COP888CL device has a spare 0 pin (05) in the emulation mode since only seven pins are required for emulation
and recreation. This pin 05 is used in the emulation mode to
enable or disable the HALT mask option feature.
T2C3
Timer T2 mode control bit
Figure 6 shows the COP888CL Emulation Mode Schematic.
T2C1
Timer T2 mode control bit
IT2C31T2C21T2C11T2colT2PNOAIT2ENAIT2PNOBIT2ENBI
Bit7
BitO
2-65
o
"'a
co
co
co
o
r
COP888CL
DO-
Dl ..;..;-,-
02<"""l.
or. . . .
D3 ,;;.;;;.,
OS';";"-
06 .......
D7
~-
~
~
~
~
g
g
g
g
g
g
g
g
g
g
g
g
ID
II
D2~
12
D5
13
~G1D1U
DDATA
D7 DDATA
14
~
15
17
~A
CD
~~
0.48CK
a: OF
.JB
Cl
SClOCK
D4 SClOCK
C2
~~
200
OD ~
3 Dl
4 D2
01~
5 D3
02
604
03~
7 OS
04 15
8D60S '4
9 D7
06 13
1 LE
07 12
06
OS
04
3
D2
Dl
OA 3
OB 4
OC ~
16
10
11
OG 12
i1-f-..---
DO
~~
C3
~~
C4
C5
74HC161
~oo-
C6
~ ENP
~A
~B
C7
LO
L1
KC
~O
9 -
L2
L3
CDP888CL
L4
~
1
L5
~
OHIH-OG 12
OF 11
OE 10
OD 6
QC 5
OB 4
OA 3
"'"--
l7
SClOCK 8 CK
~ Cl
~ B
..,! A
GO
Gl
G2
G3
G4
G5
01 PCl
G6
G7
~
~ vee
~ vss
~
CKI
HlTl
NRESET
D3 PCU
BPI
VREF
OD
.u...-
XlD 1 CL
RCD
lL.
~L1
OHitdJ I
SClOCK 8 CK
~ Cl
B
'A
I3'
QG
OF
OE
OD
12
11
10
6
QC~
OB~
PO
PI
P2
P3
-"4
PS
P6
PCl
P8
P9
Pl0
Pll
7 AD
009
Dl:~
3::
~ A6
23 ~
22 A9
19 Al0
21 All
1
<>
~
> may be decreased to
Vr (Vr = 2.0V) without altering the state of the machine.
As with the HALT mode, the COP888CL can be returned to
normal operation with a RESET, or with a Multi-Input Wakeup from the L Port. Alternately, the microcontroller resumes
normal operation from the IDLE mode when the twelfth bit
(representing 4.096 ms at internal clock frequency of 1 MHz
(tc = 1 ,..,s» of the IDLE Timer toggles.
The COP888CL supports three different ways of exiting the
HALT mode. The first method of exiting the HALT mode is
with the Multi-Input Wakeup feature on the L port. The second method is with a low to high transition on the CKO (G7)
pin. This method preludes the use of the crystal clock configuration (since CKO becomes a dedicated output), and so
may be used with an RC clock configuration. The third
method of exiting the HALT mode is by pulling the RESET
input low.
This toggle condition of the twelfth bit of the IDLE Timer TO
is latched into the TOPND pending flag.
The user has the option of being interrupted with a transition
on the twelfth bit of the IDLE Timer TO. The interrupt can be
enabled or disabled via the TOEN control bit. Setting the
TOEN flag enables the interrupt and vice versa.
The user can enter the IDLE mode with the Timer TO interrupt enabled. In this case, when the TOPND bit gets set, the
COP888CL will first execute the Timer TO interrupt service
routine and then return to the instruction following the "Enter Idle Mode" instruction.
Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full amplitude and frequency stability. The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution. In this case,
upon detecting a valid Wakeup signal, only the oscillator
circuitry is enabled. The IDLE timer is loaded with a value of
256 and is clocked with the tc instruction cycle clock. The tc
clock is derived by dividing the oscillator clock down by a
factor of 10. The Schmitt trigger following the CKI inverter
on the chip ensures that the IDLE time is clocked only when
the oscillator has a sufficiently large amplitude to meet the
Schmitt trigger specifications. This Schmitt trigger is not part
of the oscillator closed loop. The startup timeout from the
IDLE timer enables the clock signals to be routed to the rest
of the chip.
Alternatively, the user can enter the IDLE mode with the
IDLE Timer TO interrupt disabled. In this case, the
COP888CL will resume normal operation with the instruction
immediately following the "Enter IDLE Mode" instruction.
I
N
~~-t---------.t:~~tE::~~------.J i
N
If an RC clock option is being used, the fixed delay is introduced optionally. A control bit, CLKDLY, mapped as configuration bit G7, controls whether the delay is to be introduced or not. The delay is included if CLKDLY is set, and
excluded if CLKDLY is reset. The CLKDLY bit is cleared at
reset.
A
L
o
A
T
H--------HlA
I..--~-.....
The COP88CL has two mask options associated with the
HALT mode. The first mask option enables the HALT mode
feature, while the second mask option disables the HALT
mode. With the HALT mode enable mask option, the
COP888CL will enter and exit the HALT mode as described
above. With the HALT disable mask option, the COP888CL
cannot be placed in the HALT mode (writing a "1" to the
HALT flag will have no effect).
The WatchDog detector circuit is inhibited during the HALT
mode. However, the clock monitor circuit remains active
TL/DD/9766-11
FIGURE 7. Timers for the COP888CL
2-67
CCt
CCt
CCt
(')
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oCo)
Timers
The COP888CL contains a very versatile set of timers (TO,
T1, T2). All timers and associated autoreload/capture registers power up containing random data.
The user only has to define the parameters of the PWM
signal (ON time and OFF time). Once begun, the timer block
will continuously generate the PWM signal completely independent of the microcontroller. The user software services
the timer block only when the PWM parameters require updating.
In this mode the timer Tx counts down at a fixed rate of te.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, RxA and RxB. The very
first underflow of the timer causes the timer to reload from
the register RxA. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register RxB.
Figure 7 shows a block diagram for the timers on the
COP888CL.
TIMER TO (IDLE TIMER)
The COP888CL supports applications that require maintaining real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer TO, which is a
16-bit timer. The Timer TO runs continuously at the fixed
rate of the instruction cycle clock, te. The user cannot read
or write to the IDLE Timer TO, which is a count down timer.
The Timer TO supports the following functions:
The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
timer for PWM mode operation.
Exit out of the Idle Mode (See Idle Mode description)
WatchDog logic (See WatchDog description)
Start up delay out of the HALT mode
Figure 8 shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the TxA output pin. The underflows can also be programmed to generate interrupts.
The IDLE Timer TO can generate an interrupt when the
twelfth bit toggles. This toggle is latched into the TOPND
pending flag, and will occur every 4 ms at the maximum
clock frequency (te = 1 Ils). A control flag TOEN allows the
interrupt from the twelfth bit of Timer TO to be enabled or
disabled. Setting TOEN will enable the interrupt, while resetting it will disable the interrupt.
Underflows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending flags under software control. Two control enable flags, TxENA and TxENB, allow the interrupts from the
timer underflow to be enabled or disabled. Setting the timer
enable flag TxENA will cause an interrupt when a timer underflow causes the RxA register to be reloaded into the timer. Setting the timer enable flag TxENB will cause an interrupt when a timer underflow causes the RxB register to be
reloaded into the timer. Resetting the timer enable flags will
disable the associated interrupts.
TIMER T1 AND TIMER T2
The COP888CL has a set of two powerful timer/counter
blocks, T1 and T2. The associated features and functioning
of a timer block are described by referring to the timer block
Tx. Since the two timer blocks, T1 and T2, are identical, all
comments are equally applicable to either timer block.
Each timer block consists of a 16-bit timer, Tx, and two
supporting 16-bit autoreload/ capture registers, RxA and
RxB. Each timer block has two pins associated with it, TxA
and TxB. The pin TxA supports I/O required by the timer
block, while the pin TxB is an input to the timer block. The
powerful and flexible timer block allows the COP888CL to
easily perform all timer functions with minimal software
overhead. The timer block has three operating modes: Processor Independent PWM mode, External Event Counter
mode, and Input Capture mode.
Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting once
per PWM period on either the rising or falling edge of the
PWM output. Alternatively, the user may choose to interrupt
on both edges of the PWM output.
Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that
the timer, Tx, is clocked by the input signal from the TxA pin.
The Tx timer control bits, TxC3, TxC2 and TxC1 allow the
timer to be clocked either on a positive or negative edge
from the TxA pin. Underflows from the timer are latched into
the TxPNDA pending flag. Setting the TxENA control flag
will cause an interrupt when the timer underflows.
The control bits TxC3, TxC2, and TxC1 allow selection of
the different modes of operation.
Mode 1. Processor Independent PWM Mode
As the name suggests, this mode allows the COP888CL to
generate a PWM signal with very minimal user intervention.
T1UER
UNDERfLOW
INTERRUPT +---........
TxA
tC------'
TL/DD/9766-13
FIGURE 8. Timer In PWM Mode
2-68
o
o"U
Timers (Continued)
In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB
control flag is set. The occurrence of a positive edge on the
TxB input pin is latched into the TxPNDB flag.
Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer TxCO
pending flag (the TxCO control bit serves as the timer underflow interrupt pending flag in the Input Capture mode). Consequently, the TxCO control bit should be reset when entering the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
the TxPNDA and TxCO pending flags in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.
Figure 9 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is
being used as the counter input clock.
Mode 3. Input Capture Mode
The COP888CL can precisely measure external frequencies
or time external events by placing the timer block, Tx, in the
input capture mode.
or-
Figure 10 shows a block diagram of the timer in Input Capture mode.
In this mode, the timer Tx is constantly running at the fixed
tc rate. The two registers, AxA and AxB, act as capture
registers. Each register acts in conjunction with a pin. The
register AxA acts in conjunction with the TxA pin and the
register AxB acts in conjunction with the TxB pin.
The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin. Control bits,
TxC3, TxC2 and TxC1, allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for each input pin can be specified independently.
TIMER CONTROL FLAGS
The timers T1 and T2 have indentical control structures.
The control bits and their functions are summarized below.
TxCO
Timer Start/Stop control in Modes 1 and 2
(Processor Independent PWM and External
Event Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)
TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag
The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag
TxENA allows the interrupt on TxA to be either enabled or
disabled. Setting the TxENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts
from the TxB pin.
m.. ER
UNDERflOW
INTERRUPT
CD
CD
CD
TxENA
TxENB
Timer Interrupt Enable Flag
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
o = Timer Interrupt Disabled
TxC3
TxC2
TxC1
Timer mode control
Timer mode control
Timer mode control
+----..,
TxA
TL/DD/9766-14
FIGURE 9. Timer In External Event Counter Mode
Ie
TxAOO--H
TxBIXt--+I
TLlDD/9766-15
FIGURE 10. Timer In Input Capture Mode
2-69
•
...I
0
CO
CO
CO
a.
0
0
Timers
(Continued)
The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:
Interrupt A
Source
Interrupt B
Source
Timer
Counts On
MODE 2 (External
Event Counter)
Timer
Underflow
Pos. TxB
Edge
TxA
Pos.Edge
1
MODE 2 (External
Event Counter)
Timer
Underflow
Pos. TxB
Edge
TxA
Neg. Edge
0
1
MODE 1 (PWM)
TxA Toggle
Autoreload
RA
Autoreload
RB
1
0
0
MODE 1 (PWM)
No TxA Toggle
Autoreload
RA
Autoreload
RB
0
1
0
MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Pos. Edge
Pos. TxA
Edge or
Timer
Underflow
Pos. TxB
Edge
1
1
0
MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Neg. Edge
Pos. TxA
Edge or
Timer
Underflow
Neg. TxB
Edge
0
1
1
MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Pos. Edge
Neg. TxB
Edge or
Timer
Underflow
Pos.TxB
Edge
1
1
1
MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Neg. Edge
Neg. TxA
Edge or
Timer
Underflow
Neg.TxB
Edge
TxC3
TxC2
TxC1
Timer Mode
0
0
0
0
0
1
Detection of Illegal Conditions
The COP888CL will detect various illegal conditions resulting from coding errors, transient noise, power supply voltage drops, runaway programs, etc.
Thus, the chip can detect the following illegal conditions:
a. Executing from undefined ROM
b. Over "POP"ing the stack by having more returns than
calls.
When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before restarting (this recovery program is probably similar to that
following RESET, but might not contain the same program
initialization procedures).
Reading of undefined ROM gets zeros. The opcode for software interrupt is zero. If the program fetches instructions
from undefined ROM, this will force a software interrupt,
thus signaling that an illegal condition has occurred.
The subroutine stack grows down for each call Oump to
subroutine), interrupt, or PUSH, and grows up for each return or POP. The stack pointer is initialized to RAM location
06F Hex during RESET. Consequently, if there are more
returns than calls, the stack pointer will point to addresses
070 and 071 Hex (which are undefined RAM). Undefined
RAM from addresses 070 to 07F Hex is read as all 1's,
which in turn will cause the program to return to address
FFFF Hex. This is an undefined ROM location and the instruction fetched (all O's) from this location will generate a
software interrupt signaling an illegal condition.
.
Multi-Input Wakeup
The Multi-Input Wakeup feature is used to return (wakeup)
the COP888CL from either the HALT or IDLE modes. Alternately Multi-Input Wakeup/Interrupt feature may also be
used to generate up to 8 edge selectable external interrupts.
2-70
Multi-Input Wakeup
o
o
(Continued)
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INTERNAL DATA BUS
CKI
CKO
LO
L7
TO INTERRUPT LOGIC
CHIP CLOCK
TlIDD/9766-16
FIGURE 11. Multi-Input Wake Up Logic
Figure 11 shows the Multi-Input Wakeup logic for the
COP888CL microcontroller.
The Multi-Input Wakeup feature utilizes the L Port. The user
selects which particular L port bit (or combination of L Port
bits) will cause the COP888CL to exit the HALT or IDLE
modes. The selection is done through the Reg: WKEN. The
Reg: WKEN is an 8-bit read/write register, which contains a
control bit for every L port bit. Setting a particular WKEN bit
enables a Wakeup from the associated L port pin.
The user can select whether the trigger condition on the
selected L Port pin is going to be either a positive edge (low
to high transition) or a negative edge (high to low transition).
This selection is made via the Reg: WKEDG, which is an 8bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a
pseudo Wakeup condition as a result of the edge change.
First, the associated WKEN bit should be reset, followed by
the edge select change in WKEDG. Next, the associated
WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.
An example may serve to clarify this procedure. Suppose
we wish to change the edge select from positive (low going
high) to negative (high going low) for L Port bit 5, where bit 5
has previously been enabled for an input interrupt. The program would be as follows:
RBIT
SBIT
RBIT
SBIT
5,
5,
5,
5,
If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wakeup/Interrupt, a safety procedure should also be followed to avoid inherited
pseudo wakeup conditions. After the selected L port bits
have been changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired
edge selects, followed by the associated WKPND bits being
cleared.
This same procedure should be used following RESET,
since the L port inputs are left floating as a result of RESET.
The occurrence of the selected trigger condition for Multi-Input Wakeup is latched into a pending register called Reg:
WKPND. The respective bits of the WKPND register will be
set on the occurrence of the selected trigger edge on the
corresponding Port L pin. The user has the responsibility of
clearing these pending flags. Since the Reg: WKPND is a
pending register for the occurrence of selected wakeup
conditions, the COP888CL will not enter the HALT mode if
any Wakeup bit is both enabled and pending. Consequently,
the user has the responsibility of clearing the pending flags
before attempting to enter the HALT mode.
All three registers Reg:WKEN, Reg:WKPND and
Reg:WKEDG are read/write registers, and are cleared at
reset.
PORT L INTERRUPTS
Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into
the same service subroutine.
The interrupt from Port L shares logic with the wake up circuitry. The register WKEN allows interrupts from Port L to
be individually enabled or disabled. The register WKEDG
WKEN
WKEDG
WKPND
WKEN
2-71
-J r-----------------------------------------------------------------------------------~
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Multi-Input Wakeup
(Continued)
specifies the trigger condition to be either a positive or a
negative edge. Finally, the register WKPND latches in the
pending trigger conditions.
er is clocked only when the oscillator has a sufficiently large
amplitude to meet the Schmitt trigger specifications. This
Schmitt trigger is not part of the oscillator closed loop. The
startup timeout from the IDLE timer enables the clock signals to be routed to the rest of the chip.
A control flag, LPEN, functions as a global interrupt enable
for Port L interrupts. Setting the LPEN flag will enable interrupts and vice versa. A separate global pending flag Is not
needed since the register WKPND is adequate.
If the RC clock option is used, the fixed delay is under software control. A control flag, CLKDLY, in the G7 configuration bit allows the clock start up delay to be optionally inserted. Setting CLKDLY flag high will cause clock start up delay
to be inserted and resetting it will exclude the clock start up
delay. The CLKDLY flag is cleared during RESET, so the
clock start up delay is not present following RESET with the
RC clock options.
Since Port L Is also used for waking the COP888CL out of
the HALT or IDLE modes, the user can elect to exit the
HALT or IDLE modes either with or without the interrupt
enabled. If he elects to disable the interrupt, then the
COP888CL will restart execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or IDLE modes. In the other case, the
COP888CL will first execute the interrupt service routine
and then revert to normal operation.
Interrupts
The COP888CL supports a vectored interrupt scheme. It
supports a total of ten interrupt sources. The following table
lists all the possible COP888CL interrupt sources, their arbitration ranking and the memory locations reserved for the
interrupt vector for each source.
The Wakeup signal will not start the chip running immediately since crystal oscillators or ceramic resonators have a finite start up time. The IDLE Timer (TO) generates a fixed
delay to ensure that the oscillator has indeed stabilized before allowing the COP888CL to execute instructions. In this
case, upon detecting a valid Wakeup signal, only the oscillator circuitry and the IDLE Timer TO are enabled. The IDLE
Timer is loaded with a value of 256 and is clocked from the
te instruction cycle clock. The te clock is derived by dividing
down the oscillator clock by a factor of 10. A Schmitt trigger
following the CKI on-chip inverter ensures that the IDLE tim-
Arbitration
Ranking
(1) Highest
Two bytes of program memory space are reserved for each
interrupt source. All interrupt sources except the software
interrupt are maskable. Each of the maskable interrupts
have an Enable bit and a Pending bit. A maskable interrupt
is active if its associated enable and pending bits are set. If
GIE = 1 and an interrupt is active, then the processor will
be interrupted as soon as it is ready to 'start executing an
Source
Description
Vector
Address
HI-Low Byte
Software
INTR Instruction
OyFE-OyFF
Reserved
for Future Use
OyFC-OyFD
(2)
External
Pin GO Edge
OyFA-OyFB
(3)
Timer TO
TO Bit 12 Toggle
OyF8-0yF9
(4)
TimerT1
T1 Underflowl
T1 A Capture Edge
OyF6-0yF7
(5)
TimerT1
T1 B Capture Edge
OyF4-0yF5
(6)
MICROWIRE/PLUS
BUSY Goes Low
OyF2-0yF3
Reserved
for Future Use
OyFO-OyF1
Reserved
forUART
OyEE-OyEF
Reserved
forUART
OyEC-OyED
(7)
TimerT2
T2 Underflowl
T2A Capture Edge
OyEA-OyEB
(8)
TimerT2
T2B Capture Edge
OyE8-0yE9
Reserved
for Future Use
OyE6-0yE7
Reserved
for Future Use
OyE4-0yE5
(9)
Port LlWakeup
Port LEdge
OyE2-0yE3
(10) Lowest
Default
VIS Instr. Execution
without Any Interrupts
OyEO-OyE1
y is VIS page.
2-72
o
o"tJ
Interrupts (Continued)
instruction except if the above conditions happen during the
Software Trap service routine. This exception is described
in the Software Trap sub-section.
located at OyEO-OyE1. This vector can point to the Software Trap (ST) interrupt service routine, or to another special service routine as desired.
The interruption process is accomplished with the INTR instruction (opcode 00), which is jammed inside the Instruction Register and replaces the opcode about to be executed. The following steps are performed for every interrupt:
Figure 12 shows the COP888CL Interrupt block diagram.
Q)
Q)
Q)
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SOFTWARE TRAP
The Software Trap (ST) is a special kind of non-maskable
interrupt which occurs when the INTR instruction (used to
acknowledge interrupts) Is fetched from ROM and placed
inside the instruction register. This may happen when the
PC is pointing beyond the available ROM address space or
when the stack is over-popped.
When an ST occurs, the user can re-initialize the stack
pointer and do a recovery procedure (similar to RESET, but
not necessarily containing all of the same initialization procedures) before restarting.
The occurrence of an ST is latched into the ST pending bit.
The GIE bit is not affected and the ST pending bit (not
accessible by the user) is used to inhibit other interrupts
and to direct the program to the ST service routine with the
VIS instruction.
1. The GIE (Global Interrupt Enable) bit Is reset.
2. The address of the instruction about to be executed is
pushed Into the stack.
3. The PC (Program Counter) branches to address OOFF.
This procedure takes 7 tc cycles to execute.
At this time, since GIE = 0, other maskable interrupts are
disabled. The user is now free to do whatever context
switching is required by saving the context of the machine in
the stack with PUSH instructions. The user would then program a VIS (Vector Interrupt Select) instruction in order to
branch to the interrupt service routine of the highest priority
interrupt enabled and pending at the time of the VIS. Note
that this is not necessarily the interrupt that caused the
branch to address location OOFF Hex prior to the context
switching.
It is cleared by RESET and by the RPND instruction.
The ST has the highest rank among all interrupts.
Thus, if an interrupt with a higher rank than the one which
caused the interruption becomes active before the decision
of which interrupt to service is made by the VIS, then the
interrupt with the higher rank will override any lower ones
and will be acknowledged. The lower priority interrupt(s) are
still pending, however, and will cause another interrupt immediately following the completion of the interrupt service
routine associated with the higher priority interrupt just serviced. This lower priority interrupt will occur immediately following the RETI (Return from Interrupt) instruction at the
end of the interrupt service routine just completed.
Nothing (except another ST) can Interrupt an ST being
serviced.
The COP888CL contains a WatchDog and clock monitor.
The WatchDog is designed to detect the user program getting stuck in infinite loops resulting in loss of program control or "runaway" programs. The Clock Monitor is used to
detect the absence of a clock or a very slow clock below a
specified rate on the CKI pin.
WatchDog
Inside the interrupt service routine, the associated pending
bit has to be cleared by software. The RETI (Return from
Interrupt) instruction at the end of the interrupt service routine will set the GIE (Global Interrupt Enable) bit, allowing
the processor to be interrupted again if another interrupt is
active and pending.
The COP888CL WatchDog consists of two independent logic blocks: WD UPPER and WD LOWER. WD UPPER establishes the upper limit on the service window and WD LOWER defines the lower limit of the service window.
ServiCing the WatchDog consists of writing a specific value
to a WatchDog Service Register named WDCNT which is
memory mapped in the RAM. This value is composed of
three fields, consisting of a 2-bit Window Select, a 5-bit Key
Data field, and the 1-bit Clock Monitor Select field. Table I
shows the WDCNT register.
The lower limit of the service window is fixed at 2048 instruction cycles. Bits 7 ad 6 of the WDCNT register allow
the user to pick an upper limit of the service window.
The VIS instruction looks at all the active interrupts at the
time it is executed and performs an indirect jump to the
beginning of the service routine of the one with the highest
rank.
The addresses of the different interrupt service routines,
called vectors, are chosen by the user and stored in ROM in
a table starting at 01 EO (assuming that VIS is located between OOFF and 01DF). The vectors are 15-bit wide and
therefore occupy 2 ROM locations.
Table II shows the four possible combinations of lower and
upper limits for the WatchDog service window. This flexibility in choosing the WatchDog service window prevents any
undue burden on the user software.
Bits 5, 4, 3, 2 and 1 of the WDCNT register represent the 5bit Key Data field. The key data is fixed at 011 00. Bit 0 of the
WDCNT Register is the Clock Monitor Select bit.
VIS and the vector table must be located in the same 256byte block (OyOO to OyFF) except if VIS is located at the last
address of a block. In this case, the table must be in the
next block.
The vector of the maskable interrupt with the lowest rank is
located at OyEO (Hi-Order byte) and OyE1 (Lo-Order byte)
and so forth in increasing rank number. The vector of the
maskable interrupt with the highest rank is located at OyFA
(Hi-Order byte) and OyFB (Lo-Order byte).
TABLE I
Window
Select
The Software Trap has the highest rank and its vector is
located at OyFE and OyFF.
X
7
If, by accident, a VIS gets executed and no interrupt is active, then the PC (Program Counter) will branch to a vector
2-73
I
Clock
Monitor
Key Data
X
0 1 1 1 1 1 01
6
5
4
3
2
0
y
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WatchDog
match the WatchDog key data. Subsequent writes to the
WDCNT register will compare the value being written by the
user to the WatchDog service window value and the key
data (bits 7 through 1) in the WDCNT Register. Table III
shows the sequence of events that can occur.
(Continued)
TABLE II
WDCNT
Blt7
WDCNT
BitS
0
0
1
1
0
1
0
1
Service Window
(Lower-Upper Limits)
The user must service the WatchDog at least once before
the upper limit of the serivce window expires. The WatchDog may not be serviced more than once in every lower
limit of the service window. The user may service the
WatchDog as many times as wished in the time period between the lower and upper limits of the service window. The
first write to the WDCNT Register is also counted as a
WatchDog service.
The WatchDog has an output pin associated with it. This is
the WDOUT pin, on pin 1 of the port G. WDOUT is active
low. The WDOUT pin is in the high impedance state in the
inactive state. Upon triggering the WatchDog, the logic will
pull the WDOUT (G1) pin low for an additional 16 tc-32 to
cycles after the signal level on WDOUT pin goes below the
lower Schmitt trigger threshold. After this delay, the
COP888CL will stop forcing the WDOUT output low.
2k-8k tc Cycles
2k-16k tc Cycles
2k-32k tc Cycles
2k-64k tc Cycles
Clock Monitor
The Clock Monitor aboard the COP888CL can be selected
or deselected under program control. The Clock Monitor is
guaranteed not to reject the clock if the instruction cycle
clock (1 ltd is greater or equal to 10kHz. This equates to a
clock input rate on CKI of greater or equal to 100 kHz.
WatchDog Operation
The WatchDog and Clock Monitor are disabled during
RESET. The COP888CL comes out of RESET with the
WatchDog armed, the WatchDog Window Select bits (bits 6,
7 of the WDCNT Register) set, and the Clock Monitor bit (bit
o of the WDCNT Register) enabled. Thus, a Clock Monitor
error will occur after coming out of RESET, if the instruction
cycle clock frequency has not reached a minimum specified
value, including the case where the oscillator fails to start.
The WatchDog service window will restart when the
WDOUT pin goes inactive. It is recommended that the user
tie the WDOUT pin back to Vee through a resistor in order
to pull WDOUT high.
A WatchDog service while the WDOUT signal is active will
be ignored. The state of the WDOUT pin is not guaranteed
at RESET, but if it powers up low then the WatchDog will
time out and disable.
The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error. The Clock Monitor error will continue
until the clock frequency has reached the minimum specified value, after which the G1 output will enter the high impedance TRI-STATE mode following 16 tc-32 tc clock cycles. The Clock Monitor generates a continual Clock Moni-
The WDCNT register can be written to only once after
RESET and the key data (bits 5 through 1 of the WDCNT
Register) must match to be a valid write. This write to the
WDCNT register involves two irrevocable choices: (i) the
selection of the WatchDog service window (ii) enabling or
disabling of the Clock Monitor. Hence, the first write to
WDCNT Register involves selecting or deselecting the
Clock Monitor, select the WatchDog service window and
sonwARE--------------------------~
TIMER T1 AND T2
EXTERNAL
WAKE UP
INTERRUPT
JoLWIRE
PERIPHERALS
IDLE TIMER
TL/DD/9766-18
FIGURE 12. COP888CL Interrupt Block Diagram
2-74
o
o"tJ
WatchDog Operation
(Continued)
tor error if the oscillator fails to start, or fails to reach the
minimum specified frequency. The specification for the
Clock Monitor is as follows:
1/tc
> 10kHz-No clock rejection.
1/tc
< 10 Hz-Guaranteed clock rejection.
I------~INT[RRUPT
r-~~-~~------~50
1+------51
MICROWIRE/PLUS
MICROWIRE/PlUS is a serial synchronous communications interface. The MICROWIRE/PlUS capability enables
the COP888Cl to interface with any of National Semiconductor's MICROWIRE peripherals (Le. AID converters, display drivers, E2PROMs etc.) and with other microcontrollers
which support the MICROWIRE interface. It consists of an
8-bit serial shift register (SIO) with serial data input (SI), serial data output (SO) and serial shift clock (SK). Figure 13
shows a block diagram of the MICROWIRE logic.
The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIRE
arrangement with the internal clock source is called the
Master mode of operation. Similarly, operating the MICROWIRE arrangement with an external shift clock is called the
Slave mode of operation.
5K
TL/DD/9766-20
FIGURE 13. MICROWIRE Block Diagram
The CNTRl register is used to configure and control the
MICROWIRE mode. To use the MICROWIRE, the MSEl bit
in the CNTRl register is set to one. The SK clock rate is
selected by the two bits, SlO and Sl1, in the CNTRl register. Table IV details the different clock rates that may be
selected.
TABLE III
Key
Data
Window
Data
Clock
Monitor
Action
Valid Service: Restart Service Window
Match
Match
Match
Don't Care
Mismatch
Don't Care
Error: Generate WatchDog Output
Mismatch
Don't Care
Don't Care
Error: Generate WatchDog Output
Don't Care
Don't Care
Mismatch
Error: Generate WatchDog Output
TABLE IV
SL1
SLO
0
0
2
0
1
x
4
8
1
SK
x lc
x tc
x tc
Where tc is the instruction cycle clock
2-75
Q)
Q)
Q)
o
r
-J
o
co
co
co
D.
o
o
r-----------------------------------------------------------------------------------~
MICROWIRE/PLUS (Continued)
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by
the Master will be shifted properly. After eight clock pulses
the BUSY flag will be cleared and the sequence may be
repeated.
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift.
The COP888CL may enter the MICROWIRE/PLUS mode
either as a Master or as a Slave. Figure 14 shows how two
COP888CL microcontrollers and several peripherals may be
interconnected using the MICROWIRE/PLUS arrangements.
Alternate SK Phase Operation
The COP888CL allows either the normal SK clock or an
alternate phase SK clock to shift data in and out of the SIO
register. In both the modes the SK is normally low. In the
normal mode data is shifted in on the rising edge of the SK
clock and the data is shifted out on the falling edge of the
SK clock. The SIO register is shifted on each falling edge of
the SK clock in the normal mode. In the alternate SK phase
operation, data is shifted in on the falling edge of the SK
clock ahd shifted out on the rising edge of the SK clock. In
the alternate SK phase mode the SIO register is shifted on
the rising edge of the SK clock.
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alternate SK clock. The SKSEL is mapped into the G6 configuration bit. The SKSEL flag will power up in the reset condition,
selecting the normal SK signal.
Warning:
The SIO register should only be loaded when the SK clock
is low. Loading the SIO register while the SK clock is high
will result in undefined data in the SIO register.
Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PLUS slave mode may cause the current SK
clock forthe SIO shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is
low.
MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally by the COP888CL.
The MICROWIRE Master always initiates all data exchanges. The MSEL bit in the CNTRL register must be set to
enable the SO and SK functions onto the G Port. The SO
and SK pins must also be selected as outputs by setting
appropriate bits in the Port G configuration register. Table III
summarizes the bit settings required for Master mode of
operation.
TABLE V
. This table assumes that the control flag MSEL is set.
MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the
SKclock is generated by an external source. Setting the
MSEL bit in the CNTRL register enables the SO and SK
functions onto the G Port. The SK pin must be selected as
an input and the SO pin is selected as an output pin by
setting and resetting the appropriate bit in the Port G configuration register. Table V summarizes the settings required to
enter the Slave mode of operation.
I/O
LINES
8- BIT
lK BYTE
AID
EEPROM
COP495
COP43X
G4(SO)
Conflg. Bit
G5 (SK)
Conflg. Bit
G4
Fun.
G5
Fun.
Operation
1
1
SO
Int.
SK
MICROWIRE
Master
0
1
TRISTATE
Int.
SK
MICROWIRE
Master
1
0
SO
Ext.
SK
MICROWIRE
Slave
0
0
TRISTATE
Ext.
SK
MICROWIRE
Slave
LCD
DISPLAY
DRIVER
COP472
COPS
MASTER
VF
DISPLAY
DRIVER
COP470
I/o
LINES
COPS
(SLAVE)
SI M-......'-f-+--~+-+----+-+----~f___1S0
~
~
~
~
TL/DD/9766-21
FIGURE 14. MICROWIRE Application
2-76
o
Memory Map
Addressing Modes
All RAM, ports and registers (except A and PC) are mapped
into data memory address space
The COP888CL has ten addressing modes, six for operand
addressing and four for transfer of control.
Address
00 to 6F
OPERAND ADDRESSING MODES
Contents
Register Indirect
This is the "normal" addressing mode for the COP888CL.
The operand is the data memory addressed by the B pointer
or X pointer.
On-Chip RAM bytes
70 to BF
Unused RAM Address Space
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
COtoCF
Timer T2 Lower Byte
Timer T2 Upper Byte
Timer T2 Autoload Register T2RA Lower Byte
Timer T2 Autoload Register T2RA Upper Byte
Timer T2 Autoload Register T2RB Lower Byte
Timer T2 Autoload Register T2RB Upper Byte
Timer T2 Control Register
WatchDog Service Register (Reg:WOCNn
MIWU Edge Select Register (Reg:WKEOG)
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register (Reg:WKPNO)
AID Converter Control Register (Reg:ENAO)
AID Converter Result Register (Reg: AORSLn
Reserved
DO
01
02
03
04
05
06
07
08
09
OA
DB
DC
DO to OF
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port 0 Data Register
Reserved for Port 0
EO to E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
Reserved
Timer T1 Autoload Register T1 RB Lower Byte
Timer T1 Autoload Register T1 RB Upper Byte
ICNTRL Register
MICROWIRE Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1 RA Lower Byte
Timer T1 Autoload Register T1 RA Upper Byte
CNTRL Control Register
PSW Register
FOto FB
FC
FO
FE
FF
On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
Reserved
Register Indirect (with auto post Increment or
decrement of pointer)
This addressing mode is used with the LO and X instructions. The operand is the data memory addressed by the S
pointer or X pointer. This is a register indirect mode that
automatically post increments or decrements the B or X register after executing the instruction.
Direct
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
Immediate
The instruction contains an 8-bit immediate field as the operand.
Short Immediate
This addressing mode is used with the LSI instruction. The
instruction contains a 4-bit immediate field as the operand.
Indirect
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.
TRANSFER OF CONTROL ADDRESSING MODES
Relative
This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new
program location. JP has a range from -31 to +32 to allow
a 1-byte relative jump (JP + 1 is implemented by a NOP
instruction). There are no "pages" when using JP, since all
15 bits of PC are used.
Absolute
This mode is used with the JMP and JSR instructions, with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any location in the current 4k program memory segment.
Absolute Long
This mode is used with the JMPL and JSRL instructions,
with the instruction field of 15 bits replacing the entire 15
bits of the program counter (PC). This allows jumping to any
location in the current 4k program memory space.
Indirect
This mode is used with the JIO instruction. The contents of
the accumulator are used as a partial address (lower 8 bits
of PC) for accessing a location in the program memory. The
contents of this program memory location serve as a partial
address (lower 8 bits of PC) for the jump to the next instruction.
Reading memory locations 70-7F Hex will return all ones. Reading other
unused memory locations will return undefined data.
Note: The VIS is a special case of the Indirect Transfer of Control address·
ing mode, where the double byte vector associated with the interrupt
is transferred from adjacent addresses in the program memory into
the program counter (PC) in order to jump to the associated interrupt
service routine.
2-77
o
-a
(X)
(X)
(X)
o
r-
~r-----------------------------------------------------------------~
o
~
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a.
oo
Instruction Set
Register and Symbol Definition
Symbols
Registers
A
B
X
SP
PC
PU
PL
C
HC
GIE
VU
VL
[B)
8-Bit Accumulator Register
8-Bit Address Register
8-Bit Address Register
8-Bit Stack Pointer Register
15-Bit Program Counter Register
Upper 7 Bits of PC
Lower 8 Bits of PC
1 Bit of PSW Register for Carry
1 Bit of PSW Register for Half Carry
1 Bit of PSW Register for Global
Interrupt Enable
Interrupt Vector Upper Byte
Interrupt Vector Lower Byte
[X]
MD
Mem
Meml
Imm
Reg
Bit
<<->
2-78
Memory Indirectly Addressed by B
Register
Memory Indirectly Addressed by X
Register
Direct Addressed Memory
Direct Addressed Memory or [B)
Direct Addressed Memory or [B) or
Immediate Data
8-Bit Immediate Data
Register Memory: Addresses FO to FF
(Includes B, X and SP)
Bit Number (0 to 7)
Loaded with
Exchanged with
o
o
Instruction Set (Continued)
"tJ
co
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co
INSTRUCTION SET
ADD
ADC
A,Meml
A,Meml
ADD
ADD with Carry
SUBC
A,Meml
Subtract with Carry
AND
ANDSZ
OR
XOR
IFEQ
IFEQ
IFNE
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND
A,Meml
A,lmm
A,Meml
A,Meml
MD,Imm
A,Meml
A,Meml
A,Meml
#
Reg
#,Mem
#,Mem
#,Mem
Logical AND
Logical AND Immed., Skip if Zero
Logical OR
Logical EXclusive OR
IF EQual
IF EQual
IF Not Equal
IF Greater Than
If B Not Equal
Decrement Reg., Skip if Zero
Set BIT
Reset BIT
IFBIT
Reset PeNDing Flag
A <- A + Meml
A < - A + Meml + C, C < - Carry
HC < - Half Carry
A < - A - Meml + C, C < - Carry
HC < - Half Carry
A < - A and Meml
Skip next if (A and Imm) = 0
A <- Aor Meml
A < - A xor Meml
Compare MD and Imm, Do next if MD = Imm
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A not = Meml
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of B not = Imm
Reg < - Reg- 1, Skip if Reg = 0
1 to bit, Mem (bit = 0 to 7 immediate)
o tobit, Mem
If bit in A or Mem is true do next instruction
Reset Software Interrupt Pending Flag
X
LD
LD
LD
LD
A,Mem
A,Meml
B,lmm
Mem,lmm
Reg,lmm
EXchange A with Memory
LoaD A with Memory
LoaD B with Immed.
LoaD Memory Immed
LoaD Register Memory Immed.
A <-> Mem
A <- Meml
B <- lnim
Mem <-Imm
Reg <- Imm
X
X
LD
LD
LD
A, [B ±]
A, [X ±]
A, [B±]
A,[X±]
[B±],lmm
EXchange A with Memory [B)
EXchange A with Memory [X]
LoaD A with Memory [B)
LoaD A with Memory [X]
LoaD Memory [B) Immed.
A < - > [B), (B < - B ± 1)
A < - > [X], (X < - ± 1)
A <-[B],(B <-B ±1)
A < - [X], (X < - X ± 1)
[B) < -Imm, (B < - B ± 1)
CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
RC
IFC
IFNC
POP
PUSH
A
A
A
CLeaR A
INCrementA
DECrementA
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
SetC
ResetC
IFC
IF NotC
POP the stack into A
PUSH A onto the stack
A<-O
A<- A + 1
A<-A-1
A < - ROM (PU,A)
A < - BCD correction (follows ADC, SUBC)
C - > A7 - > ... - > AO - > C
C < - A7 < - ... < - AO < - C
A7 ... A4 < - > A3 ... AO
C <- 1, HC <- 1
C <- 0, HC <- 0
IF C is true, do next instruction
If C is not true, do next instruction
SP < - SP + 1, A < - [SP]
[SP] < - A, SP < - SP - 1
Vector to Interrupt Service Routine
Jump absolute Long
Jump absolute
Jump relative short
Jump SubRoutine Long
Jump SubRoutine
Jump InDirect
RETurn from subroutine
RETurn and SKip
RETurn from Interrupt
Generate an Interrupt
No OPeration
PU < - [VU], PL < - [VL]
PC < - ii (ii = 15 bits, 0 to 32k)
PC9 ... 0 < - i (i = 12 bits)
PC < - PC + r (r is - 31 to + 32, not 1)
[SP] <- PL, [SP-1] <- PU,SP-2, PC <- ii
[SP] < - PL, [SP-l] < - PU,SP-2, PC9 ... 0 < - i
PL < - ROM (PU,A)
SP + 2, PL < - [SP]' PU < - [SP-l]
SP + 2, PL < -[SP],PU < - [SP-1],Skip < - 1
SP + 2, PL < - [SP],PU < - [SP-1],GIE< - 1
[SP] < - PL, [SP-1] < - PU, SP-2, PC < - OFF
PC <- PC + 1
VIS
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
A
A
A
A
A
A
Addr.
Addr.
Disp.
Addr.
Addr
2-79
or-
..J
~
~
o
o
Instruction Execution Time
Most instructions are single byte (with immediate addressing mode instructions taking two bytes).
Most single byte instructions take one cycle time (1 ,."s at
10 MHz) to execute.
See the BYTES and CYCLES per INSTRUCTION table for
details.
Instructions Using A & C
CLRA
INCA
DECA
LAID
DCOR
RRCA
RLCA
SWAPA
SC
RC
IFC
IFNC
PUSHA
POPA
ANDSZ
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles
for each instruction in the format of byte/cycle (a cycle is 1
,.,,5 at 10 MHz).
[B]
Direct
ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFNE
IFGT
IFBNE
DRSZ
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
SBIT
RBIT
IFBIT
1/1
1/1
1/1
3/4
3/4
3/4
RPND
1/1
Immed.
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2
Transfer of Control
Instructions
JMPL
JMP
JP
JSRL
JSR
JID
VIS
RET
RETSK
RETI
INTR
NOP
1/3
Memory Transfer Instructions
Register
Indirect
X A,·
LOA,·
LDB,lmm
LDB,lmm
LDMem,lmm
LD Reg,lmm
IFEQMD,lmm
[B]
[X]
1/1
1/1
1/3
1/3
2/2
Direct Immed.
2/3
2/3
2/2
1/1
2/2
Register Indirect
Auto Incr. & Decr.
[B+,B-]
[X+,X-]
1/2
1/2
1/3
1/3
(IFB
(IF B
2/2
3/3
2/3
3/3
• = > Memory location addressed by 8 or X or directly.
2-80
< 16)
> 15)
3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5
117
1/1
(')
o""C
COP888CL Opcode Table
Q)
Q)
Q)
Upper Nibble Along X-Axis
Lower Nibble Along Y-Axis
(')
F
E
0
C
JP -15
JP -31
LDOFO, # i
DRSZOFO
JP -14
JP -30
LDOF1, # i
DRSZOF1
JP -13
JP -29
LDOF2, # i
DRSZOF2
A
B
RRCA
·
r-
8
9
RC
ADCA,#i
ADCA,[B]
0
SC
SUBCA, #i
SUB A,[B]
1
XA,[X+]
XA,[B+]
IFEOA,#i
IFEOA,[B]
2
JP -12
JP -28
LD OF3, # i
DRSZOF3
XA, [X-]
XA,[B-]
IFGT A,#i
IFGT A,[B]
3
JP -11
JP -27
LD OF4, # i
DRSZOF4
VIS
LAID
ADDA,#i
ADDA,[B]
4
JP -10
JP -26
LD OF5, # i
DRSZOF5
RPND
JID
ANDA,#i
ANDA,[B]
5
JP -9
JP -25
LDOF6, # i
DRSZOF6
X A, [X]
XORA,[B]
6
JP -8
JP -24
LDOF7, # i
DRSZOF7
.
XORA,#i
OR A,#i
ORA,[B]
7
JP -7
JP -23
LDOF8, # i
DRSZOF8
NOP
RLCA
LDA,#i
IFC
8
JP -6
JP -22
LDOF9, # i
DRSZOF9
IFNE
A,[B]
IFEO
Md,#i
IFNE
A,#i
IFNC
9
JP -5
JP -21
LDOFA, # i
DRSZOFA
LDA,[X+]
LDA,[B+ ]
LD [B+ l.#i
INCA
A
JP -4
JP -20
LDOFB, # i
DRSZOFB
LD A,[X-]
LDA,[B-]
LD [B-l,#i
DECA
B
JP -3
JP -19
LDOFC, # i
DRSZOFC
LD Md,#i
JMPL
XA,Md
POPA
C
JP -2
JP -18
LDOFD, # i
DRSZOFD
DIR
JSRL
LDA,Md
RETSK
D
JP -1
JP -17
LDOFE, # i
DRSZOFE
LDA,[X]
RET
E
JP -0
JP -16
LDOFF, # i
DRSZOFF
.
LD [Bl.#i
LDB,#i
RETI
F
·
·
2-81
XA,[B]
LDA,[B]
=
~ r---------------------------------------------------------------------------------~
o
~
8
COP888CL Opcode Table
(Continued)
Upper Nibble Along X-Axis
Lower Nibble Along Y-Axis
7
6
5
3
2
1
IFBIT
O,[B]
ANDSZ
A, #i
LD B;#OF
IFBNEO
JSR
xOOO-xOFF
JMP
xOOO-xOFF
JP +17
INTR
0
LDB,#OE
IFBNE 1
JSR
x100-x1FF
JMP
x100-x1FF
JP +18
JP + 2
1
LD B,#OD
IFBNE2
JSR
x200-x2FF
JMP
x200-x2FF
JP +19
JP + 3
2
IFBIT
1,[B]
IFBIT
2,[B]
·
·
4
0
·
LD
B,#~C
IFBNE3
JSR
x300-x3FF
JMP
x300-x3FF
JP +20
JP + 4
3
IFBIT
4,[B]
CLRA
LDB,#OB
IFBNE4
JSR
x400-x4FF
JMP
x400-x4FF
JP +21
JP + 5
4
IFBIT
5,[B]
SWAPA
LD B,#OA
IFBNE5
JSR
x500-x5FF
JMP
x500-x5FF
JP +22
JP + 6
5
IFBIT
6,[B]
DCORA
LDB,#09
IFBNE6
JSR
x600-x6FF
JMP
x600-x6FF
JP +23
JP + 7
6
IFBIT
7,[B]
PUSHA
LDB,#08
IFBNE7
JSR
x700-x7FF
JMP
x700-x7FF
JP +24
JP + 8
7
SBIT
O,[B]
RBIT
O,[B]
LDB,~07
IFBNE8
JSR
x800-x8FF
JMP.
x800-x8FF
JP +25
JP + 9
8
SBIT
1,[B]
RBIT
1,[B]
LDB,#P6
IFBNE9
JSR
x900-x9FF
JMP
x900-x9FF
JP +26
JP + 10
9
SBIT
2,[B]
RBIT
2,[B]
LD B,#05
IFBNEOA
JSR
xAOO-xAFF
JMP
xAOO-xAFF
JP +27
JP + 11
A
SBIT
3,[B]
RBIT
3,[B]
LDB,#04
IFBNEOB
JSR
xBOO-xBFF
JMP
xBOO-xBFF
JP +28
JP + 12
B
SBIT
4,[B]
RBIT
4,[B]
LDB,#03
IFBNEOC
JSR
xCOO-xCFF
JMP
xCOO-xCFF
JP +29
JP + 13
C
SBIT
5,[B]
RBIT
5,[B]
LDB,#02
IFBNEOD
JSR
xDOO-xDFF
JMP
xDOO-xDFF
JP +30
JP + 14
D
SBIT
6,[B]
RBIT
6,[B]
LD B,#01
IFBNEOE
JSR
xEOO-xEFF
JMP
xEOO-xEFF
JP +31
JP + 15
E
SBIT
7,[B]
RBIT
7,[B]
LDB,#OO
IFBNEOF
JSR
xFOO-xFFF
JMP
xFOO-xFFF
JP +32
JP + 16
F
IFBIT
3,[B]
:
Where,
i is the immediate data
Md is a directly addressed memory location
• is an unused opcode
Note: The opcode 60 Hex is also the opcode for IFBIT ;!Ii,A
2-82
o
Mask Options
Development Support
The COP888CL mask programmable options are shown below. The options are programmed at the same time as the
ROM pattern submission.
MOLE DEVELOPMENT SYSTEM
o
"tJ
Q)
Q)
Q)
The MOLE (Microcomputer On Line Emulator) is a low cost
development system and emulator for all micro controller
products. These include COPSTM microcontroliers and the
HPC family of products. The MOLE consists of a BRAIN
Board, Personality Board and optional host software.
OPTION 1: CLOCK CONFIGURATION
1
Crystal Oscillator (CKI/10)
G7 (CKO) is clock generator
output to crystal/resonator
CKI is the clock input
2
Single-pin HC controlled
oscillator (CKI/IO)
G7 is available as a HALT
restart and/or general purpose
input
=
or-
The purpose of the MOLE is to provide the user with a tool
to write and assemble code, emulate code for the target
microcontrolier and assist in both software and hardware
debugging of the system.
=
It is a self contained computer with its own firmware which
provides for all system operation, emulation control, communication, PROM programming and diagnostic operations.
It contains three serial ports to optionally connect to a terminal, a host system, a printer or a modem, or to connect to
other MOLEs in a multi-MOLE environment.
OPTION 2: HALT
1
Enable HALT mode
2
Disable HALT mode
=
=
MOLE can be used in either a stand alone mode or in conjunction with a selected host system using PC-DOS communicating via a RS-232 port.
OPTION 3: COP888CL BONDING
1
44-Pin PCC
40-Pin DIP
=2
28-Pin PCC
3
28-Pin DIP
4
=
How to Order
To order a complete development package, select the section for the microcontrolier to be developed and order the
parts listed.
=
=
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (if clock option-1 has been selected). The
CKI input frequency is divided down by 10 to produce the
instruction cycle clock (1 ltd.
Development Tools Selection Table
Mlcrocontroller
COP888
Order
Part Number
Description
Includes
Manual
Number
MOLE-BRAIN
Brain Board
Brain Board Users Manual
420408188-001
MOLE-COP8-PB2
Personality Board
COP888 Personality Board
Users Manual
420420084-001
MOLE-COP8-IBM
Assembler Software for IBM
COP800 Software Users Manual
and Software Disk
PC-DOS Communications
Software Users Manual
424410527-001
TBD
Programmer's Manual
2-83
420040416-001
TBD
•
-J
oco
co
co
a..
oo
r-----------------------------------------------------------------------------------~
Development Support (Continued)
DIAL·A·HELPER
Dial-A-Helper is a service provided by the MOLE (Microcontroller On Line Emulator) applications group. It consists of
an electronic bulletin board information system and a method by which applications can take control of a MOLE Development System at a remote site via modem in order to resolve any problems.
If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk for
later use.
Order PIN: MOLE·DIAL-A·HLP
Information System Package Contents
Dial-A-Helper User Manual PIN
Public Domain Communications Software
Information System
The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION mode
that can be used to search out and retrieve application data
about NSC Microcontrollers. The user needs as a minimum,
a Dumb terminal, 300 or 1200 baud modem, and a telephone.
(408) 721-5582
Voice:
Modem:
Factory Applications Support
Dial-A-Helper also provides immediate factor applications
support. If a user is having difficulty in getting a MOLE to
operate in a particular mode or something peculiar is occuring, he can contact us via his system and modem. He can
leave messages on our electronic bulletin board, which we
will responed to, or he can arrange for us to actually take
control of his system via modem for debugging purposes.
The applications group can then cause his system to execute various commands and try to resolve the customer's
problem by actually getting customer's system to respond.
Both parties see exactly what is occurring, as it is happening.
This allows us to respond in minutes when applications help
is needed.
(408) 739-1162
Baud:
300 or 1200 Baud
Set-up:
Length:
8-Bit
Parity:
None
Stop Bit
Operation: 24 Hours, 7 Days
DIAL-A-HELPER
USER'S
TARGET
SYSTEM
I
I
I
MODEM
I
I
... ....,.
.
I
I
MODEM
~
HOST
COMPUTER
I
HOST
COMPUTER
MOLE
MOLE
I
.-----------------------NATIONAL SEMICONDUCTOR SITE
USER SITE
TL/DD/9766-24
2-84
~National
ADVANCE
INFORMATION
~ Semiconductor
o
General Description
The COP888 family of microcontrollers uses an 8-bit single
chip core architecture fabricated with National Semiconductor's M2CMOSTM process technology. The COP888CF is a
member of this expandable 8-bit core processor family of
microcontrollers.
(Continued)
Features
•
•
•
•
•
Low cost 8-bit microcontroller
Fully static CMOS, with low current drain
Two power saving modes: HALT and IDLE
1 p,s instruction cycle time
4096 bytes on-board ROM
128 bytes on-board RAM
Single supply operation: 2.5V-6V
8-channel AID converter with prescaler and both differential and single ended modes
MICROWIRE/PLUSTM serial 1/0
Watch Dog and Clock Monitor logic
Idle Timer
Multi-Input Wakeup (MIWU) with optional interrupts (8)
Ten multi-source vectored interrupts servicing
- External Interrupt
- Idle Timer TO
- Timers TA, TB (Each with 2 Interrupts)
- MICROWIRE/PLUS
- Multi-Input Wake Up
- Software Trap
• Two 16-bit timers, each with two 16-bit registers supporting:
- Processor Independent PWM mode
- External Event counter mode
- Input Capture mode
• 8-bit Stack Pointer SP (stack in RAM)
• Two 8-bit Register Indirect Data Memory Pointers
(B and X)
• Versatile instruction set
• True bit manipulation
• Memory mapped 1/0
• BCD arithmetic instructions
• Package: 44 PCC or 40 N or 28 N or 28 PCC
- 44 PCC with 37 1/0 pins
- 40 N with 33 1/0 pins
- 28 PCC or 28 N, each with 21 1/0 pins
• Software selectable 1/0 options
- TRI-STATE® Output
- Push-Pull Output
- Weak Pull Up Input
- High Impedance Input
• Schmitt trigger inputs on ports G and L
• Extended temperature range: - 55°C to + 125°C
• ROM less mode for accurate emulation and external
program capability
• Single chip COP8XX piggy back emulation device
• Real time emulation and full program debug offered by
National's MOLETM Development System
Block Diagram
CLOCK
HALT
IDLE
WAKE UP
RESET
0)
0)
0)
."
COP888CF Single-Chip microCMOS Microcontroller
•
•
•
•
•
•
•
•
o
o
"U
8 BIT CORE
t.lODIFIED HARVARD
ARCHITECTURE
CPU REGISTERS
TL/DD/9425-1
FIGURE 1. COP888CF Block Diagram
2-85
U.
o
co
co
co
a.
o
o
r-----------------------------------------------------------------------------------~
General Description
(Continued)
It is a fully static part, fabricated using double-metal-silicon
gate microCMOS technology. Features include an 8-bit
memory mapped architecture, MICROWIRE/PLUS serial
I/O, two 16-bit timer/counters supporting three modes
(Processor Independent PWM generation, External Event
counter, and Input Capture mode capabilities), an 8-channel, 8-bit AID converter with both differential and single
ended modes, and two power savings modes (HALT and
IDLE), both with a multi-sourced wakeup/interrupt capa-
bility. This multi-sourced interrupt capability may also be
used independent of the HALT or IDLE modes. Each I/O
pin has software selectable configurations. The COP888CF
operates over a voltage range of 2.5V to 6V. High throughput is achieved with an efficient, regular instruction set operating at a maximum of 1 J-Ls per instruction rate. The
COP888CF may be operated in the ROM less mode to provide for accurate emulation and for applications requiring
external program memory.
Connection Diagrams
Plastic Chip Carrier
Dual-In-Llne Package
Cl
co
C3
CKI
vee
10/ACHO
I1/ACHI
44 pin
PLCC
12/ACH2
GO
G4
38
RESET
G5
37
G2
GNO
G6
36
GI
GO
07
G7
6
35
06
eKI
7
34
RESET
05
8
33
GNO
32
07
14/ACH4
04
Vee
10/ACHO
15/ACH5
03
II/ACHI
16/ACH6
02
12/ACH2
17/ACH7
01
13/ACH3
AGNO
DO
9
40 pIn
DIP
11
05
13/ACH3
04
14/ACH4
03
02
15/ACH5
t
~ ~ ~ ~ ~ ~
>
G3
~ ~ ~ ~
AGNO
15
26
VREF
16
25
DO
LO
17
24
L7
TL/OO/942S-2
Top View
Order Number COP888CF-XXX/V
See NS Plastic Chip Package Number V44A
01
Ll
18
23
L6
L2
19
22
L5
L3
20
21
L4
TL/OO/942S-4
Top View
Order Number COP888F-XXXIN
See NS Molded Package Number N40A
Plastic Chip Carrier
B ~ ~ i1
a
CKI
Dual-In-Llne Package
~ c:;
25
Vee
10/ACHO
28 pin
PLCC
I1/ACHI
AGNO
VREF
10
LO
11
G4
I
G3
G5
2
G2
GO
24
RESET
G7
23
GNO
CKI
22
03
21
20
GO
RESET
6
02
Vee
10/ACHO
01
II/ACHI
8
DO
AGNO
28 pIn
OIP
23
GNO
22
03
21
02
9
20
01
VREF
10
19
DO
LO
II
18
L7
TL/OO/942S-3
Top View
Order Number COP884CF-XXX/V
See NS Plastic Chip Package Number V28A
7
Ll
12
17
L6
L2
13
16
L5
L3
14
15
L4
TL/OO/942S-5
Top View
Order Number COP884CF-XXXIN
See NS Molded Package Number N28A
FIGURE 2. COP888CF Connection Diagrams
2-86
o
o""D
Connection Diagrams (Continued)
CD
CD
CD
COP888CF Pinouts for 28-, 40- and 44-Pln Packages
Port
Type
LO
1/0
L1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WOOUT
I/O
I/O
I/O
I/O
I
CKO
L2
L3
L4
L5
L6
L7
GO
G1
G2
G3
G4
G5
G6
G7
DO
01
02
03
10
11
12
13
14
15
16
17
04
05
06
07
CO
C1
C2
C3
C4
C5
C6
C7
VREF
AGNO
a
a
a
a
I
I
I
I
I
I
I
I
a
a
a
a
Alt. Fun
AIt.Fun
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
INT
T2A
T2B
T1B
T1A
SO
SK
SI
ROM OATA+
PCL+
EMUL +
PCU+
ACHO
ACH1
ACH2
ACH3
ACH4
ACH5
ACH6
ACH7
SCLOCK+
HALTSEL+
LOAO+
o DATA +
28-Pln
Pack.
40-Pln
Pack.
11
12
13
14
15
16
17
18
25
26
27
28
1
2
3
4
19
20
21
22
7
8
17
18
19
20
21
22
23
24
35
36
37
38
3
4
5
6
25
26
27
28
9
10
11
12
13
14
-
-
10
9
6
23
5
24
+VREF
AGNO
Vee
GNO
CKI
RESET
-
= Unbonded Pins
= Only in the ROMless Mode
-
29
30
31
32
39
40
1
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
+
-
2-87
16
15
8
33
7
34
44-Pln
Pack.
-
19
20
25
26
27
28
39
40
41
42
3
4
5
6
29
30
31
32
9
10
11
12
13
14
15
16
33
34
35
36
43
44
1
2
21
22
23
24
18
17
8
37
7
38
o
"'T1
u.
o
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co
co
a.
oo
Absolute Maximum Ratings
If Military!Aerospace specified devices are required,
contact the National Semiconductor Sales Office!
Distributors for availability and specifications.
Supply Voltage (Vee)
7V
Voltage at Any Pin
-0.3V to Vee + 0.3V
ESD Susceptibility (Note 4)
2000V
Total Current into Vee Pin (Source)
100mA
DC Electrical Characteristics
Parameter
Total Current out of GND Pin (Sink)
110 mA
Storage Temperature Range
- 65°C to + 150°C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
-40°C::;; TA ::;;
+ 85°C unless otherwise specified
Conditions
Min
Typ
Operating Voltage
Power Supply Ripple (Note 1)
Peak-to-Peak
Supply Current (Note 2)
CKI = 10 MHz
CKI = 4MHz
Vee = 6V, tc = 1 J.Ls
Vee = 2.5V, tc = 2.5 J.Ls
HALT Current (Note 3)
Vee
IDLE Current
CKI = 10 MHz
CKI = 4MHz
Vee = 6V, tc = 1 J.Ls
Vee = 2.5V, tc = 2.5 J.Ls
2.5
= 6V, CKI = 0 MHz
Input Levels
Reset
Logic High
Logic Low
Max
V
0.1 Vee
V
15
2
mA
mA
<26
J.LA
5
0.6
mA
mA
0.2 Vee
V
V
0.2 Vee
V
V
0.2 Vee
V
V
0.8 Vee
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
0.7 Vee
All Other Inputs
Logic High
Logic Low
0.7 Vee
Units
6
Hi-Z Input Leakage
Vee = 6V, VIN = OV
-2
+2
J.LA
Input Pullup Current
Vee = 6V, VIN = OV
40
250
J.LA
G and L Port Input Hysteresis
Output Current Levels
D Outputs
Source
V
0.05 Vee
Vee = 4V, VOH = 3.3V
Vee = 2.5V, VOH = 1.8V
0.4
0.2
mA
mA
Vee = 4V, VOL = 1V
Vee = 2.5V, VOL = O.4V
10
0.2
mA
mA
Vee = 4V, VOH = 2.7V
Vee = 2.5V, VOH = 1.8V
10
2.5
Source (Push-Pull Mode)
Vee = 4V, VOH = 3.3V
Vee = 2.5V, VOH = 1.8V
0.4
0.2
mA
mA
Sink (Push-Pull Mode)
Vee = 4V, VOL = O.4V
Vee = 2.5V, VOL = 0.4V
1.6
0.7
mA
mA
Sink
All Others
Source (Weak Pull-Up Mode)
100
33
J.LA
J.LA
-2
TRI-STATE Leakage
+2
J.LA
Rate of voltage change must be less then 0.5 Vlms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, Land G ports in the TRI·
STATE mode and tied to ground, all outputs low and tied to ground. If the AID is not being used and minimum standby current Is desired, VREF should be tied to
AGND (effectively shorting the Reference resistor). The clock monitor is disabled.
Note 4: Human body model, 100 pF through 15000.
Note 1:
2-88
o
DC Electrical Characteristics
Parameter
-40·C
Conditions
Typ
Min
Units
Max
(X)
(X)
(X)
o
."
Allowable Sink/Source
Current per Pin
D Outputs (Sink)
All others
Maximum Input Current
without Latchup
RAM Retention Voltage, Vr
o"'0
~ T A ~ + 85·C unless otherwise specified (Continued)
2
V
Load Capacitance on D2
Conditions
Min
0.050V)
AGND
Total Unadjusted Error (Note 5)
VREF
=
=
3
OV
5V
Input Reference Resistance
7
pF
1000
pF
~ Any Input ~ (Vee + 0.050V)
Typ
Resolution
Reference Voltage Input
rnA
rnA
Input Capacitance
Parameter
rnA
3
200
500 ns Rise
and Fall Time (Min)
AID Converter Specifications Vee = 5V ± 10% (Vss -
15
1.6
Max
Units
8
Bits
Vee
V
±%
LSB
4.8
kO
Common Mode Input Range
TBD
V
DC Common Mode Error
±%
LSB
Off Channel Leakage Current
1
p.A
On Channel Leakage Current
1
p.A
Power Supply Sensitivity
AID Clock Frequency (Note 7)
0.1
Conversion Time (Note 6)
12
±%
LSB
1.67
MHz
A/D Clock
Cycles
Note 5: Total Unadjusted Error includes offset, full·scale, and multiplexer errors.
Note 6: Conversion Time includes sample and hold time.
•
Note 7: See Prescaler description.
2-89
II.
o
co
co
co
AC Electrical Characteristics
D.
o
o
-40·C ~ TA ~
Parameter
Instruction Cycle Time (tel
Crystal, Resonator, or
External Oscillator
RIC Oscillator
CKI Clock Duty Cycle (Note 8)
Rise Time (Note 8)
Fall Time (Note 8)
Inputs
tSETUP
tHOLD
Output Propagation Delay
tpD1, tpDO
SO,SK
All Others
+ 85·C unless otherwise specified
Units
1
2.5
3
7.5
DC
DC
DC
DC
Il-s
Il-s
Il-s
Il-s
40
60
5
5
ns
ns
Min
4V ~ Vee ~ 6V
2.5V ~ Vee < 4V
4V ~ Vee ~ 6V
2.5V ~ Vee < 4V
fr
fr
fr
= Max
= 10 MHz Ext Clock
= 10 MHz Ext Clock
= 2.2k, CL =
%
ns
ns
ns
ns
200
500
60
150
4V ~ Vee ~ 6V
2.5V ~ Vee < 4V
4V ~ Vee ~ 6V
2.5V ~ Vee < 4V
RL
Typ
Max
Conditions
100 pF
4V ~ Vee ~ 6V
2.5V ~ Vee < 4V
4V ~ Vee ~ 6V
2.5V ~ Vee < 4V
MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Valid Time (tuv)
0.7
Il-s
1
2.5
Il-s
Il-s
220
ns
ns
ns
20
56
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
1
1
1
1
tc
tc
tc
tc
Reset Pulse Width
1
Il-S
Note 8: Parameter sample but not 100% tested.
2·90
o
AC Electrical Characteristics
o""tJ
(Continued)
co
co
co
o."
CKI
( +20MOOE)
CKI--.J
(+ 10 MODE)
I I...._ . . .
-l tpDO
11 (XLO)
12
r-
-l tpDl
c:
,---------,
~--tP-Dl-Ir----------------
1
(PHI)
------------------~~
-l tpDI t00.01.03
_________________________-J/I.-------~-'________
l
t
sETUP
.....Jxxxx
IO.13 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
TL/OO/9425-25
FIGURE 2a. AC Timing Diagrams In ROM less Mode
SK
tuws
It-,
tuwH
SI~
~tuv
SO - - - - - -
C
TL/OO/9425-26
FIGURE 2b. MICROWIRE/PLUS Timing
2·91
I.L
o
co
Pin Descriptions
D.
Vee and GND are the power supply pins.
o
VREF and AGND are the reference voltage pins for the onboard AID converter.
co
co
o
Port L has the following alternate features:
LO
MIWU
CKI is the clock input. This can come from an external
source, a R/C generated oscillator, or a crystal oscillator (in
conjunction with CKO). See Oscillator Description section.
RESET is the master reset input. See Reset Description
section.
The COP888CF contains three bidirectional 8-bit I/O ports
(C, G and L), where each individual bit may be independently configured as an input, output or TRI-STATE under program control. Three data memory address locations are allocated for each of these I/O ports. Each I/O port has two
associated 8-bit memory mapped registers, the CONFIGURATION register and the output DATA register. A memory
mapped address is also reserved for the input pins of each
I/O port. (See the COP888CF memory map for the various
addresses associated with the I/O ports.) Figure 3 shows
the I/O port configurations for the COP888CF. The DATA
and CONFIGURATION registers allow for each port bit to
be individually configured under software control as shown
below:
CONFIGURATION
Register
DATA
Register
0
0
0
1
1
1
0
1
L1
MIWU
L2
L3
L4
MIWU
MIWU
L5
MIWU or T2B
L6
MIWU
L7
MIWU
MIWU or T2A
Port G is an 8-bit port with 5 I/O pins (GO, G2-G5), an input
pin (G6), and two dedicated output pins (G1 and G7). Pins
GO and G2-G6 all have Schmitt Triggers on their inputs. Pin
G1 serves as the dedicated WDOUT WatchDog output,
while pin G7 serves as the dedicated CKO clock output.
There are two registers associated with the G Port, a data
register and a configuration register. Therefore, each of the
5 I/O bits (GO, G2-G5) can be individually configured under
software control.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin or general purpose input (R/C clock configuration), the associated bits in the data and configuration
registers for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits
will return zeros.
Port Set-Up
Hi-Z Input
(TRI-STATE Output)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output
Note that the chip will be placed in the HALT mode by writing a "1" to bit 7 of the Port G Data Register. Similarly the
chip will be placed in the IDLE mode by writing a "1" to bit 6
of the Port G Data Register.
Writing a "1" to bit 6 of the Port G Configuration Register
enables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock. The G7 configuration bit, if set
high, enables the clock start up delay when the R/C clock
configuration is used.
PORT L, C, AND G CONFIGURATION
Conflg Reg.
Data Reg.
G7
CLK Delay
HALT
G6
Alternate SK
IDLE
Port G has the following alternate features:
GO
INTR (External Interrupt Input)
G2
T1 B (Timer T1 Capture Input)
G3
G4
T1 A (Timer T1 I/O)
SO (MICROWIRETM Serial Data Output)
G5
SK (MICROWIRE Serial Clock)
G6
SI (MICROWIRE Serial Data Input)
TLlDD/9425-6
Port G has the following dedicated functions:
FIGURE 3. I/O Port Configurations
PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.
G1
WDOUT WatchDog and/or Clock Monitor
dedicated output
Port L supports Multi-Input Wakeup (MIWU) on all eight
pins. L4 and L5 are used for the timer input functions T2A
and T2B. LO and L1 are not available on the 44-pin version
of the COP888CF, since they are replaced by VREF and
AGND. LO and L1 are not terminated on the 44-pin version.
Consequently, reading LO or L1 as inputs will return unreliable data with the 44-pin package, so this data should be
masked out with user software when the L port is read for
input data.
G7
CKO Oscillator dedicated output or general
purpose input
Port I is an 8-bit Hi-Z input port, and also provides the analog inputs to the AID converter. The 28- and 40-pin devices
do not have a full complement of Port I pins. The unavailable pins are not terminated (Le. they are floating). A read
operation from these unterminated pins will return unpredictable values. The user should ensure that the software
takes this into account by either masking out these inputs,
2-92
o
and skip if zero) instruction. The memory pointer registers X,
SP, and 8 are memory mapped into this space at address
locations OFC to OFE Hex respectively, with the other registers (other than reserved register OFF) being available for
general usage.
Pin Descriptions (Continued)
or else restricting the accesses to bit operations only. If unterminated, Port I pins will draw power only when addressed
(i.e. it will be in short spikes).
Port 0 is an 8-bit output port that is preset high when RESET goes low. The user can tie two or more 0 port outputs
together in order to get a higher drive.
o
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CD
CD
o"'T1
The instruction set of the COP888CF permits any bit in
memory to be set, reset or tested. All I/O and registers on
the COP888CF (except A and PC) are memory mapped;
therefore, 1/0 bits and register bits can be directly and individually set, reset and tested. The accumulator (A) bits can
also be directly and individually tested.
Functional Description
The architecture of the COP888CF is modified Harvard architecture. With the Harvard architecture, the control store
program memory (ROM) is separated from the data store
memory (RAM). 80th ROM and RAM have their own separate addressing space with separate address buses. The
COP888CF architecture, though based on Harvard architecture, permits transfer of data from ROM to RAM.
Reset
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for Ports l, G, and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is
dedicated as the WatchDog andlor Clock Monitor error output pin. Port 0 is initialized high with RESET. The PC, PSW,
CNTRl, ICNTRl, and T2CNTRL control registers are
cleared. The Multi-Input Wakeup registers WKEN, WKEDG,
and WKPND are cleared. The AID control register ENAD is
cleared, resulting in the ADC being powered down initially.
The Stack Pointer, SP, is initialized to 06F Hex.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or
shift operation in one instruction (td cycle time.
There are five CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
Pl is the lower 8 bits of the program counter (PC)
The COP888CF comes out of RESET with both the WatchDog logic and the Clock Monitor detector armed, and with
both the WatchDog service window bits set and the Clock
Monitor bit set. The WatchDog and Clock Monitor detector
circuits are inhibited during RESET. The WatchDog service
window bits are initialized to the maximum WatchDog service window of 64k tc clock cycles. The Clock Monitor bit is
initialized high, and will cause a Clock Monitor error following RESET if the clock has not reached the minimum specified frequency at the termination of RESET. A Clock Monitor
error will cause an active low error output on pin G1. This
error output will continue until 16-32 tc clock cycles following the clock frequency reaching the minimum specified value, at which time the G1 output will enter the TRI-STATE
mode.
8 is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutinel
interrupt stack (in RAM). The SP is initialized to RAM address 06F with RESET.
All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).
PROGRAM MEMORY
Program memory for the COP888CF consists of 4096 bytes
of ROM. These bytes may hold program instructions or constant data (data tables for the LAID instruction, jump vectors
for the JID instruction, and interrupt vectors for the VIS instruction). The program memory is addressed by the 15-bit
program counter (PC). All interrupts in the COP888CF vector to program memory location OFF Hex.
The external RC network shown in Figure 4 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes. It is recommended that the
components of the RC network be selected to provide a
RESET delay of at least five times the power supply rise
time or the minimum RESET pulse width, whichever is
greater.
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the 1/0 registers (Configuration, Data
and Pin), the control registers, the MICROWIRE/PlUS SIO
shift register, and the various registers, and counters associated with the timers (with the exception of the IDLE counter). Data memory is addressed directly by the instruction or
indirectly by the B, X and SP pOinters.
P
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The COP888CF has 128 bytes of RAM. Sixteen bytes of
RAM are mapped as "registers" at addresses OFO to OFF
Hex. These registers can be loaded immediately, and also
decremented and tested with the DRSZ (decrement register
L
Y
Vee
.
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COPBOO
RESET
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GND
TlIDD/9425-7
RC
2-93
> 5 x Power Supply Rise Time
FIGURE 4. Recommended RESET Circuit
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temperature. The other two items can be reduced by carefully designing the end-user's system.
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input frequency is divided down by 10 to produce the instruction
cycle clock (1 ltd.
12 = C
xVxf
where C = equivalent capacitance of the chip
V = operating voltage
f = CKI frequency
Some sample current drain values at Vee = 5Vare:
Figure 5 shows the Crystal and RIC diagrams.
EXTERNAL OSCILLATOR
CKI (MHz)
Inst. Cycle (,...s)
It (mA)
CKI can be driven by an external clock signal provided it
meets the specified duty cycle, rise and fall times, and input
levels.
10
3.58
2
0.3
o (HALT)
1
2.8
5
33
15
5.4
3
0.45
0.005
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator.
Control Registers
RIC OSCILLATOR
CNTRL Register (Address X'OOEE)
The Timer1 (T1) and MICROWIRE control register contains
the following bits:
By selecting CKI as a single pin oscillator input, a single pin
RIC oscillator circuit can be connected to it. CKO is available as a general purpose input, and I or HALT restart pin.
I
00
eKO
.. ~2
I
I
00
CKO
t
SL 1 & SLO Select the MICROWIRE clock divide by
(00 = 2,01 = 4, 1 X = 8)
I
&~
....'II\;I\t-....
vcc
Rl
I ......
-
IEDG
External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
MSEL
Selects G5 and G4 as MICROWIRE signals
SK and SO respectively
T1CO
Timer T1 StartlStop control in timer
modes 1 and 2
Timer T1 Underflow Interrupt Pending Flag in
timer mode 3
Tl/DD/9425-9
TL/DD/9425-8
FIGURE 5. Crystal and RIC Oscillator Diagrams
T1 C1
Timer T1 mode control bit
T1 C2
Timer T1 mode control bit
T1 C3
Timer T1 mode control bit
I T1C31 T1C21 T1C1 I T1CO I MSEL IIEDG I SL1 I SLO I
Current Drain
Bit7
The total current drain of the chip depends on:
BitO
1. Oscillator operation mode-11
PSW Register (Address X'OOEF)
2. Internal switching current-12
The PSW register contains the following select bits:
3. Internal leakage current-13
GIE
Global interrupt enable (enables interrupts)
4. Output source current-14
EXEN
Enable external interrupt
5. DC current caused by external input
not at Vee or GND-15
BUSY
MICROWIRE busy shifting flag
EXPND
External interrupt pending
T1 ENA
Timer T1 Interrupt Enable for Timer Underflow
or T1 A Input capture edge
6. DC reference current contribution
from the AID converter-16
T1 PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1, T1 Underflow in Mode 2, T1A capture edge in mode 3)
Thus the total current drain, It, is given as
It = 11
+
12
+ 13 + 14 +
15
+ 16
To reduce the total current drain, each of the above components must be minimum.
The chip will draw more current as the CKI input frequency
increases up to the maximum 10 MHz value. Operating with
a crystal network will draw more current than an external
square-wave. Switching current, governed by the equation
below, can be reduced by lowering voltage and frequency.
Leakage current can be reduced by lowering voltage and
C
Carry Flag
HC
Half Carry Flag
I HC I C I T1 PNDA I T1 ENA I EXPND I BUSY I EXEN I GIE I
Bit7
SitO
The Half-Carry bit is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and RC (Reset
Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and RC instructions, ADC,
SUBC, RRC and RLC instructions affect the carry and Half
Carry flags.
2-94
o
Control Registers (Continued)
Emulation and ROM less Modes
ICNTRL Register (Address X'OOES)
The COP888CF can address up to 32 kbytes of address
space. If at power up, D2 is held at ground, the COP888CF
executes from external memory. Port D is used to interface
to external program memory. The address comes out in a
serial fashion and the data from the external program memory is read back in a serial fashion. The Port D pins perform
the following functions.
The ICNTRL register contains the following bits:
T1 ENB
Timer T1 Interrupt Enable for T1 B Input capture
edge
T1 PNDB Timer T1 Interrupt Pending Flag for T1 B capture edge
JJ.WEN
Enable MICROWIRE/PLUS interrupt
DO
D1
D2
JJ.WPND MICROWIRE/PLUS interrupt pending
TOEN
Timer TO Interrupt Enable (Bit 12 toggle)
TOPND
Timer TO Interrupt pending
LPEN
L Port Interrupt Enable (Multi-Input Wakeup/Interrupt)
D3
D4
D5
Bit 7 could be used as a flag
D6
D7
IUnused ILPEN ITOPND ITOEN I/:LWPND I/:LWEN IT1 PNDB IT1 ENB I
Bit7
BitO
The most significant bit of the data to come out on the D3
pin is a status signal .. It is used by the MOLE development
system. This "lost" output port (DO-D7) can be accurately
reconstructed with external components as shown in Figure
6, providing an accurate emulation.
T2CNTRL Register (Address X'OOCS)
The T2CNTRL register contains the following bits:
T2ENB
Timer T2 Interrupt Enable for T2B Input capture
edge
The 44-pin and 40-pin versions of the COP888CF have a full
complement of the D Port pins and can be used in the
ROMless mode. However, it should be noted that the 44-pin
device can only emulate itself and not the 40-pin or 28-pin
devices as it has only 6 Port L pins while the other two
devices have a full complement of Port L pins.
T2PNDB Timer T2 Interrupt Pending Flag for T2B capture edge
T2ENA
Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge
T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA
in mode 1, T2 Underflow in mode 2, T2A capture edge in mode 3)
T2CO
The 28-pin part cannot be used for emulation since it does
not have the full complement of 8 D Port pins necessary for
entering the ROMless mode.
Timer T2 Start/Stop control in timer modes 1
and 2 Timer T2 Underflow Interrupt Pending
Flag in timer mode 3
T2C1
Timer T2 mode control bit
T2C2
Timer T2 mode control bit
T2C3
Timer T2 mode control bit
Shifts in ROM data
Shifts out lower eight bits of PC
Places the JJ.C in the ROM less mode if grounded at
reset
Shifts out upper eight bits of PC
Data Shift Clock
HALT Mask Option select pin
(D5 = 0) for HALT enable, D5 = 1 for HALT disable)
Load Clock
Shifts out recreated Port D data
Note that in the ROM less mode the D Port is recreated one
full clock cycle behind the normal port timings.
Note: Standard parts used in the ROM less mode will operate only at a
reduced frequency (to be defined).
IT2C31T2C21T2C11T2colT2PNDAIT2ENAIT2PNDBIT2ENBI
The COP888CF device has a spare D pin (D5) in the emulation mode since only seven pins are required for emulation
and recreation. This pin D5 is used in the emulation mode to
enable or disable the HALT mask option feature.
Bit7
Figure 6 shows the COP888CF Emulation Mode Schematic.
BitO
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C>- G4
C>- G5
D-G6
C>- G7
C>- CKI
D- HLT1
D- NRESET
D- BPI
D-vee
D- VSS
D - VREF"
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OB
QC
00
OE
1
D-17
<:>- CO
<:>- Cl
<:>- C2
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<:>- LO
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LAT5
LAT6
LAT7
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DO ROIIOATA
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TLlDD/9425-10
FIGURE 6. COP888CF Emulation Mode Schematic
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Power Save Modes
The COP888CF offers the user two power save modes of
operation: HALT and IDLE. In the HALT mode, all microcontroller activities are stopped. In the IDLE mode, the onboard oscillator circuitry and timer TO are active but all other
microcontroller activities are stopped. In either mode, all onboard RAM, registers, 1/0 states, and timers (with the exception of TO) are unaltered.
Q)
Q)
Q)
IDLE MODE
The COP888CF is placed in the IDLE mode by writing a "1"
to the IDLE flag (G6 data bit). In this mode, a" activity, except the associated on-board oscillator circuitry, the WatchDog logic, the clock monitor and the IDLE Timer TO, is
stopped. The power supply requirements of the microcontroller in this mode of operation are typically around 30% of
normal power requirement of the microcontroller.
HALT MODE
As with the HALT mode, the COP888CF can be returned to
normal operation with a RESET, or with a Multi-Input Wakeup from the L Port. Alternately, the microcontroller resumes
normal operation from the IDLE mode when the twelfth bit
(representing 4.096 ms at internal clock frequency of 1 MHz
(to = 1 /J-s» of the IDLE Timer toggles.
The COP888CF is placed in the HALT mode by writing a
"1" to the HALT flag (G7 data bit). All microcontroller activities, including the clock, timers, and AID converter, are
stopped. The WatchDog logic on the COP888CF is disabled
during the HALT mode. However, the clock monitor circuitry
remains active. In the HALT mode, the power requirements
of the COP888CF are minimal and the applied voltage (Vee>
may be decreased to Vr (Vr = 2.0V) without altering the
state of the machine.
This toggle condition of the twelfth bit of the IDLE Timer TO
is latched into the TOPND pending flag.
The user has the option of being interrupted with a transition
on the twelfth bit of the IDLE Timer TO. The interrupt can be
enabled or disabled via the TOEN control bit. Setting the
TOEN flag enables the interrupt and vice versa.
The COP888CF supports three different ways of exiting the
HALT mode. The first method of exiting the HALT mode is
with the Multi-Input Wakeup feature on the L port. The second method is with a low to high transition on the CKO (G7)
pin. This method preludes the use of the crystal clock configuration (since CKO becomes a dedicated output), and so
may be used with an RC clock configuration. The third
method of exiting the HALT mode is by pulling the RESET
input low.
The user can enter the IDLE mode with the Timer TO interrupt enabled. In this case, when the TOPND bit gets set, the
COP888CF will first execute the Timer TO interrupt service
routine and then return to the instruction following the "Enter Idle Mode" instruction.
Alternatively, the user can enter the IDLE mode with the
IDLE Timer TO interrupt disabled. In this case, the
COP888CF will resume normal operation with the instruction immediately following the "Enter IDLE Mode" instruction.
Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup Signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full amplitude and frequency stability. The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution. In this case,
upon detecting a valid Wakeup signal, only the oscillator
circuitry is enabled. The IDLE timer is loaded with a value of
256 and is clocked with the to instruction cycle clock. The to
clock is derived by dividing the oscillator clock down by a
factor of 10. The Schmitt trigger following the CKI inverter
on the chip ensures that the IDLE time is clocked only when
the oscillator has a sufficiently large amplitude to meet the
Schmitt trigger specifications. This Schmitt trigger is not part
of the oscillator closed loop. The startup timeout from the
IDLE timer enables the clock signals to be routed to the rest
of the chip.
I
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A
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o
If an RC clock option is being used, the fixed delay is introduced optionally. A control bit, CLKDL Y, mapped as configuration bit G7, controls whether the delay is to be introduced or not. The delay is included if CLKDLY is set, and
excluded if CLKDLY is reset. The CLKDLY bit is cleared at
reset.
. . .__
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A
T
A
B
U
1+------------+..
The COP88CF has two mask options associated with the
HALT mode. The first mask option enables the HALT mode
feature, while the second mask option disables the HALT
mode. With the HALT mode enable mask option, the
COP888CF will enter and exit the HALT mode as described
above. With the HALT disable mask option, the COP888CF
cannot be placed in the HALT mode (writing a "1" to the
HALT flag wi" have no effect).
S
TL/OO/9425-11
FIGURE 7. Timers for the COP888CF
The WatchDog detector circuit is inhibited during the HALT
mode. However, the clock monitor circuit remains active
during HALT mode in order to ensure a clock monitor error if
the COP888CF inadvertently enters the HALT mode as a
result of a runaway program or power glitch.
2-97
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Timers
The COP888CF contains a very versatile set of timers (TO,
T1, T2). All timers and associated autoreload/ capture registers power up containing random data.
The user only has to define the parameters of the PWM
signal (ON time and OFF time). Once begun, the timer block
will continuously generate the PWM signal completely independent of the microcontroller. The user software services
the timer block only when the PWM parameters require updating.
Figure 7 shows a block diagram for the timers on the
COP888CF.
TIMER TO (IDLE TIMER)
In this mode the timer Tx counts down at a fixed rate of te.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, RxA and RxB. The very
first underflow of the timer causes the timer to reload from
the register RxA. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register RxB.
The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
timer for PWM mode operation.
The COP888CF supports applications that require maintaining real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer TO, which is a
16-bit timer. The Timer TO runs continuously at the fixed
rate of the instruction cycle clock, te. The user cannot read
or write to the IDLE Timer TO, which is a count down timer.
The Timer TO supports the following functions:
Exit out of the Idle Mode (See Idle Mode description)
WatchDog logic (See WatchDog description)
Start up delay out of the HALT mode
Figure 8 shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the TxA output pin. The underflows can also be programmed to generate interrupts.
Underflows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending flags under software control. Two control enable flags, TxENA and TxENB, allow the interrupts from the
timer underflow to be enabled or disabled. Setting the timer
enable flag TxENA will cause an interrupt when a timer underflow causes the RxA register to be reloaded into the timer. Setting the timer enable flag TxENB will cause an interrupt when a timer underflow causes the RxB register to be
reloaded into the timer. Resetting the timer enable flags will
disable the associated interrupts.
The IDLE Timer TO can generate an interrupt when the
twelfth bit toggles. This toggle is latched into the TOPND
pending flag, and will occur every 4 ms at the maximum
clock frequency (te = 1 /-Ls). A control flag TOEN allows the
interrupt from the twelfth bit of Timer TO to be enabled or
disabled. Setting TOEN will enable the interrupt, while resetting it will disable the interrupt.
TIMER T1 AND TIMER T2
The COP888CF has a set of two powerful timer/counter
blocks, T1 and T2. The associated features and functioning
of a timer block are described by referring to the timer block
Tx. Since the two timer blocks, T1 and T2, are identical, all
comments are equally applicable to either timer block.
Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting once
per PWM period on either the rising or falling edge of the
PWM output. Alternatively, the user may choose to interrupt
on both edges of the PWM output.
Each timer block consists of a 16-bit timer, Tx, and two
supporting 16-bit autoreload/ capture registers, RxA and
RxB. Each timer block has two pins associated with it, TxA
and TxB. The pin TxA supports I/O required by the timer
block, while the pin TxB is an input to the timer block. The
powerful and flexible timer block allows the COP888CF to
easily perform all timer functions with minimal software
overhead. The timer block has three operating modes: Processor Independent PWM mode, External Event Counter
mode, and Input Capture mode.
Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that
the timer, Tx, is clocked by the input signal from the TxA pin.
The Tx timer control bits, TxC3, TxC2 and TxC1 allow the
timer to be clocked either on a positive or negative edge
from the TxA pin. Underflows from the timer are latched into
the TxPNDA pending flag. Setting the TxENA control flag
will cause an interrupt when the timer underflows.
The control bits TxC3, TxC2, and TxC1 allow selection of
the different modes of operation.
Mode 1. Processor Independent PWM Mode
As the name suggests, this mode allows the COP888CF to
generate a PWM signal with very minimal user intervention.
TII.lER
UNDERFLOW
INTERRUPT +----.,
TxA
t C - - - - -.....
TL/DD/9425-13
FIGURE 8. Timer in PWM Mode
2-98
o
Timers
a"'C
(Continued)
In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB
control flag is set. The occurrence of a positive edge on the
TxB input pin is latched into the TxPNDB flag.
Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer TxCO
pending flag (the TxCO control bit serves as the timer underflow interrupt pending flag in the Input Capture mode). Consequently, the TxCO control bit should be reset when entering the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
the TxPNDA and TxCO pending flags in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.
Figure 9 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is
being used as the counter input clock.
Mode 3. Input Capture Mode
The COP888CF can precisely measure external frequencies
or time external events by placing the timer block, Tx, in the
input capture mode.
o"TI
Figure 10 shows a block diagram of the timer in Input Capture mode.
In this mode, the timer Tx is constantly running at the fixed
te rate. The two registers, RxA and RxB, act as capture
registers. Each register acts in conjunction with a pin. The
register RxA acts in conjunction with the TxA pin and the
register RxB acts in conjunction with the TxB pin.
TIMER CONTROL FLAGS
The timers T1 and T2 have indentical control structures.
The control bits and their functions are summarized below.
TxCO
The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin. Control bits,
TxC3, TxC2 and TxC1, allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for each input pin can be specified independently.
Timer Start/Stop control in Modes
(Processor Independent PWM and
Event Counter), where 1 = Start, 0 =
Timer Underflow Interrupt Pending
Mode 3 (Input Capture)
1 and 2
External
Stop
Flag in
TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag
The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag
TxENA allows the interrupt on TxA to be either enabled or
disabled. Setting the TxENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts
from the TxB pin.
TxENA
TxENB
Timer Interrupt Enable Flag
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
o = Timer Interrupt Disabled
TxC3
TxC2
TxC1
Timer mode control
Timer mode control
Timer mode control
mm
UNDERrlOW
INTERRUPT
Q:)
Q:)
Q:)
Ie
+----...,
I
N
T
E
R
N
A
l
TxA
TxAOOf---H
D
A
T
A
Tx B00---+1
Tl/DD/9425-14
Tl/DD/9425-15
FIGURE 9. Timer In External Event Counter Mode
FIGURE 10. Timer In Input Capture Mode
2-99
•
L&.
0
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a..
0
0
Timers
(Continued)
The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:
Interrupt A
Source
Interrupt B
Source
Timer
Counts On
MODE 2 (External
Event Counter)
Timer
Underflow
Pos. TxB
Edge
TxA
Pos. Edge
1
MODE 2 (External
Event Counter)
Timer
Underflow
Pos.TxB
Edge
TxA
Neg. Edge
0
1
MODE 1 (PWM)
TxA Toggle
Autoreload
RA
Autoreload
RB
1
0
0
MODE 1 (PWM)
No TxA Toggle
Autoreload
RA
Autoreload
RB
0
1
0
MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Pos. Edge
Pos. TxA
Edge or
Timer
Underflow
Pos. TxB
Edge
1
1
0
MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Neg. Edge
Pos.TxA
Edge or
Timer
Underflow
Neg.TxB
Edge
0
1
1
MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Pos. Edge
Neg. TxB
Edge or
Timer
Underflow
Pos. TxB
Edge
1
1
1
MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Neg. Edge
Neg. TxA
Edge or
Timer
Underflow
Neg. TxB
Edge
TxC3
TxC2
TxC1
Timer Mode
0
0
0
0
0
1
Detection of Illegal Conditions
Thus, the chip can detect the following illegal conditions:
The COP888CF will detect various illegal conditions resulting from coding errors, transient noise, power supply voltage drops, runaway programs, etc.
a. Executing from undefined ROM
b. Over "POP"ing the stack by having more returns than
calls.
Reading of undefined ROM gets zeros. The opcode for software interrupt is zero. If the program fetches instructions
from undefined ROM, this will force a software interrupt,
thus signaling that an illegal condition has occurred.
When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before restarting (this recovery program is probably similar to that
following RESET, but might not contain the same program
initialization procedures).
The subroutine stack grows down for each call Oump to
subroutine), interrupt, or PUSH, and grows up for each return or POP. The stack pointer is initialized to RAM location
06F Hex during RESET. Consequently, if there are more
returns than calls, the stack pointer will point to addresses
070 and 071 Hex (which are undefined RAM). Undefined
RAM from addresses 070 to 07F Hex is read as all 1's,
which in turn will cause the program to return to address
FFFF Hex. This is an undefined ROM location and the instruction fetched (all O's) from this location will generate a
software interrupt signaling an illegal condition.
Multi-Input Wakeup
The Multi-Input Wakeup feature is used to return (wakeup)
the COP888CF from either the HALT or IDLE modes. Alternately Multi-Input Wakeup/Interrupt feature may also be
used to generate up to 8 edge selectable external interrupts.
2-100
C')
Multi-Input Wakeup
a-a
(Continued)
Q:)
Q:)
Q:)
INTERNAL DATA BUS
C')
."
La
L7
TO INTERRUPT LOGIC
CHIP CLOCK
TLlDD/9425-16
FIGURE 11. Multi-Input Wake Up Logic
Figure 11 shows the Multi-Input Wakeup logic for the
COP888CF microcontroller.
If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wakeup/lnterrupt, a safety procedure should also be followed to avoid inherited
pseudo wakeup conditions. After the selected L port bits
have been changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired
edge selects, followed by the associated WKPND bits being
cleared.
The Multi-Input Wakeup feature utilizes the L Port. The user
selects which particular L port bit (or combination of L Port
bits) will cause the COP888CF to exit the HALT or IDLE
modes. The selection is done through the Reg: WKEN. The
Reg: WKEN is an 8-bit read/write register, which contains a
control bit for every L port bit. Setting a particular WKEN bit
enables a Wakeup from the associated L port pin.
This same procedure should be used following RESET,
since the L port inputs are left floating as a result of RESET.
The user can select whether the trigger condition on the
selected L Port pin is gOing to be either a positive edge (low
to high transition) or a negative edge (high to low transition).
This selection is made via the Reg: WKEDG, which is an 8bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a
pseudo Wakeup condition as a result of the edge change.
First, the associated WKEN bit should be reset, followed by
the edge select change in WKEDG. Next, the associated
WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.
The occurrence of the selected trigger condition for Multi-Input Wakeup is latched into a pending register called Reg:
WKPND. The respective bits of the WKPND register will be
set on the occurrence of the selected trigger edge on the
corresponding Port L pin. The user has the responsibility of
clearing these pending flags. Since the Reg: WKPND is a
pending register for the occurrence of selected wakeup
conditions, the COP888CF will not enter the HALT mode if
any Wakeup bit is both enabled and pending. Consequently,
the user has the responsibility of clearing the pending flags
before attempting to enter the HALT mode.
All three registers Reg:WKEN, Reg:WKPND and
Reg:WKEDG are read/write registers, and are cleared at
reset.
An example may serve to clarify this procedure. Suppose
we wish to change the edge select from positive (low going
high) to negative (high going low) for L Port bit 5, where bit 5
has previously been enabled for an input interrupt. The program would be as follows:
RBIT
SBIT
RBIT
SBIT
5,
5,
5,
5,
PORT L INTERRUPTS
Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into
the same service subroutine.
WKEN
WKEDG
WKPND
WKEN
The interrupt from Port L shares logic with the wake up circuitry. The register WKEN allows interrupts from Port L to
be individually enabled or disabled. The register WKEDG
2-101
•
LL.
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o
o
Multi-Input Wakeup
Four specific analog channel selection modes are supported. These are as follows:
(Continued)
specifies the trigger condition to be either a positive or a
negative edge. Finally, the register WKPND latches in the
pending trigger conditions.
Allow any specific channel to be selected at one time.
The AID converter performs the specific conversion requested and stops.
A control flag, LPEN, functions as a global interrupt enable
for Port L interrupts. Setting the LPEN flag will enable interrupts and vice versa. A separate global pending flag is not
needed since the register WKPND is adequate.
Allow any specific channel to be scanned continuously. In
other words, the user will specify the channel and the
AID converter will keep on scanning it continuously. The
user can come in at any arbitrary time and immediately
read the result of the last conversion. The user does not
have to wait for the current conversion to be completed.
Since Port L is also used for waking the COP888CF out of
the HALT or IDLE modes, the user can elect to exit the
HALT or IDLE modes either with or without the interrupt
enabled. If he elects to disable the interrupt, then the
COP888CF will restart execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or IDLE modes. In the other case, the
COP888CF will first execute the interrupt service routine
and then revert to normal operation.
Allow any differential channel pair to be selected at one
time. The AID converter performs the specific differential
conversion requested and stops.
Allow any differential channel pair to be scanned continuously. In other words, the user will specify the differential
channel pair and the AID converter will keep on scanning
it continuously. The user can come in at any arbitrary time
and immediately read the result of the last differential
conversion. The user does not have to wait for the current conversion to be completed.
The Wakeup signal will not start the chip running immediately since crystal oscillators or ceramic resonators have a finite start up time. The IDLE Timer (TO) generates a fixed
delay to ensure that the oscillator has indeed stabilized before allowing the COP888CF to execute instructions. In this
case, upon detecting a valid Wakeup signal, only the oscillator circuitry and the IDLE Timer TO are enabled. The IDLE
Timer is loaded with a value of 256 and is clocked from the
tc instruction cycle clock. The tc clock is derived by dividing
down the oscillator clock by a factor of 10. A Schmitt trigger
following the CKI on-chip inverter ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large
amplitude to meet the Schmitt trigger specifications. This
Schmitt trigger is not part of the oscillator closed loop. The
startup timeout from the IDLE timer enables the clock signals to be routed to the rest of the chip.
The AID converter is supported by two memory mapped
registers, the result register and the mode control register.
When the COP888CF is reset, the control register is cleared
and the AID is powered down in the single ended conversion mode. The AID result register has unknown data following reset.
AID Control Register
A control register, Reg: ENAD, contains 3 bits for channel
selection, 3 bits for prescaler selection, and 2 bits for mode
selection. An AID conversion is initiated by writing to the
ENAD control register. The result of the conversion is available to the user from the AID result register, Reg: ADRSLT.
If the RC clock option is used, the fixed delay is under software control. A control flag, CLKDLY, in the G7 configuration bit allows the clock start up delay to be optionally inserted. Setting CLKDLY flag high will cause clock start up delay
to be inserted and resetting it will exclude the clock start up
delay. The CLKDLY flag is cleared during RESET, so the
clock start up delay is not present following RESET with the
RC clock options.
Reg: ENAD
ICHANNEL SELECTI MODE SELECTI PRESCALER
Bits 7, 6, 5
Bits 4,3
SELEC~
Bits 2, 1, 0
CHANNEL SELECT
This 3-bit field is used to specify the channel address to
select one of the 8 AID channels in Single Ended mode, or
select one of the 4 AID channel pairs in the Differential
mode.
Single Ended mode:
Bit 7
Bit 6
BitS
Channel No.
AID Converter
The COP888CF contains an 8-channel, multiplexed input,
successive approximation, AID converter. Two dedicated
pins, VREF and AGND are provided for voltage reference.
OPERATING MODES
The AID converter supports ratiometric measurements. It
supports both Single Ended and Differential modes of operation.
2-102
o
o
o
o
o
o
o
o
1
1
2
o
3
o
o
o
4
5
o
6
7
C')
o"0
AID Converter (Continued)
for one converter clock cycle before starting the next sample. The ADC 8-bit result is loaded into the AID result register (ADRSL except during LOAD clock high, which prevents transient data (resulting from the ADC writing a new
result over an old one) being read from ADRSLT.
Differential mode:
Blt7
0
0
0
0
BitS
0
0
1
0
0
BitS
0
Channel Pairs (+. -)
0, 1
1,0
2,3
3,2
4,5
5,4
6, 7
7,6
0
1
0
0
1
MODE SELECT
n
Bit 3
Mode
o
o
0
Single Ended mode, single conversion
Single Ended mode, continuous scan
of a single channel into the result
register
o
Differential mode, single conversion
Differential mode, continuous scan of
a channel pair into the result register
PRESCALER SELECT
This 3-bit field is used to select one of the seven prescaler
clocks for the AID converter. The prescaler also allows the
AID clock inhibit power saving mode to be selected. The
following table shows the various prescaler options.
Blt2
0
0
0
0
Bit 1
0
0
BltO
0
0
1
0
0
0
1
0
C')
"'T1
PRESCALER
The COP888CF AID Converter (ADC) contains a prescaler
option which allows seven different clock selections. The
AID clock frequency is equal to CKI divided by the prescaler
value. Note that the prescaler value must be chosen such
that the AID clock falls within the specified range. With a
prescaler of 6 selected, the maximum AID clock frequency
is 1.67 MHz (10 MHz divided by 6). This equates to a 600 ns
ADC clock cycle.
The AID converter takes 12 ADC clock cycles to complete
a conversion. Thus the minimum ADC conversion time for
the COP888CF is 7.2 J.Ls when a prescaler of 6 has been
selected. These 12 ADC clock cycles necessary for a conversion consist of 1 cycle at the beginning for reset, 2 cycles
for sampling, 8 cycles for converting, and 1 cycle for loading
the result into the COP888CF AID result register (ADRSLT).
This AID result register is a read-only register. The
COP888CF cannot write into ADRSLT.
This 2-bit field is used to select the mode of operation (single conversion, continuous conversions, differential, single
ended) as shown in the following table.
Bit 4
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The prescaler also allows an AID clock inhibit option, which
saves power by powering down the AID when it is not in
use.
Note: The AID converter is also powered down when the COP888CF is in
either the HALT or IDLE modes. If the ADC is running when the
COP888CF enters the HALT or IDLE modes, the ADC will power
down during the HALT or IDLE, and then will reinitialize the conversion when the COP888CF comes out of the HALT or IDLE modes.
Clock Select
Inhibit AID clock
Divide by 1
Divide by2
Divideby4
Divideby6
Divide by 12
Divide by8
Divide by 16
Interrupts
The COP888CF supports a vectored interrupt scheme. It
supports a total of ten interrupt sources. The following table
lists all the possible COP888CF interrupt sources, their arbitration ranking and the memory locations reserved for the
interrupt vector for each source.
Two bytes of program memory space are reserved for each
interrupt source. All interrupt sources except the software
interrupt are maskable. Each of the maskable interrupts
have an Enable bit and a Pending bit. A maskable interrupt
is active if its associated enable and pending bits are set. If
GIE = 1 and an interrupt is active, then the processor will
be interrupted as soon as it is ready to start executing an
instruction except if the above conditions happen during the
Software Trap service routine. This exception is described
in the Software Trap sub-section.
ADC Operation
The AID converter interface works as follows. Writing to the
AID control register ENAD initiates an AID conversion unless the prescaler value is set to 0, in which case the ADC
clock is stopped and the ADC is powered down. The conversion sequence starts at the beginning of the write to
ENAD operation by deselecting and powering up the ADC.
At the first falling edge of the converter clock following the
write operation (not counting the falling edge if it occurs at
the same time as the write operation ends), the sample signal turns on for two clock cycles. The ADC is selected in the
middle of the sample period. If the ADC is in single conversion mode, the conversion complete signal from the ADC
will generate a power down for the AID converter. If the
ADC is in continuous mode, the conversion complete signal
will restart the conversion sequence by deselecting the ADC
The interruption process is accomplished with the INTR instruction (opcode 00), which is jammed inside the Instruction Register and replaces the opcode about to be executed. The following steps are performed for every interrupt:
1. The GIE (Global Interrupt Enable) bit is reset.
2. The address of the instruction about to be executed is
pushed into the stack.
3. The PC (Program Counter) branches to address OOFF.
This procedure takes 7 tc cycles to execute.
2-103
•
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Interrupts (Continued)
Arbitration
Ranking
(1) Highest
Description
Source
Vector
Address
HI-Low Byte
Software
INTR Instruction
OyFE-OyFF
Reserved
for Future Use
OyFC-OyFD
(2)
External
Pin GO Edge
OyFA-OyFB
(3)
Timer TO
TO Bit 12 Toggle
OyFS-OyF9
(4)
TimerT1
T1 Underflowl
T1 A Capture Edge
OyF6-0yF7
(5)
TimerT1
T1B Capture Edge
OyF4-0yF5
(6)
MICROWIRE/PLUS
BUSY Goes Low
OyF2-0yF3
Reserved
for Future Use
OyFO-OyF1
Reserved
forUART
OyEE-OyEF
Reserved
forUART
OyEC-OyED
(7)
TimerT2
T2 Underflowl
T2A Capture Edge
OyEA-OyEB
(S)
TimerT2
T2B Capture Edge
OyES-OyE9
Reserved
for Future Use
OyES-OyE7
Reserved
for Future Use
OyE4-0yE5
(9)
Port L/Wakeup
Port LEdge
OyE2-0yE3
(10) Lowest
Default
VIS Instr. Execution
without Any Interrupts
OyEO-OyE1
y is VIS page.
The VIS instruction looks at all the active Interrupts at the
time it is executed and performs an indirect jump to the
beginning of the service routine of the one with the highest
rank.
The addresses of the different interrupt service routines,
called vectors, are chosen by the user and stored in ROM in
a table starting at 01 EO (assuming that VIS is located between OOFF and 01 DF). The vectors are 15-bit wide and
therefore occupy 2 ROM locations.
At this time, since GIE = 0, other maskable Interrupts are
disabled. The user is now free to do whatever context
switching is required by saving the context of the machine in
the stack with PUSH instructions. The user would then program a VIS (Vector Interrupt Select) instruction in order to
branch to the interrupt service routine of the highest priority
interrupt enabled and pending at the time of the VIS. Note
that this is not necessarily the interrupt that caused the
branch to address location OOFF Hex prior to the context
switching.
Thus, if an interrupt with a higher rank than the one which
caused the interruption becomes active before the decision
of which interrupt to service is made by the VIS, then the
interrupt with the higher rank will override any lower ones
and will be acknowledged. The lower priority interrupt(s) are
still pending, however, and will cause another interrupt immediately following the completion of the interrupt service
routine associated with the higher priority interrupt just serviced. This lower priority interrupt will occur immediately following the RETI (Return from Interrupt) instruction at the
end of the interrupt service routine just completed.
VIS and the vector table must be located in the same 25Sbyte block (OyOO to OyFF) except if VIS is located at the last
address of a block. In this case, the table must be in the
next block.
The vector of the maskable interrupt with the lowest rank is
located at OyEO (Hi-Order byte) and OyE1 (Lo-Order byte)
and so forth in increasing rank number. The vector of the
maskable interrupt with the highest rank is located at OyFA
(Hi-Order byte) and OyFB (Lo-Order byte).
The Software Trap has the highest rank and its vector is
located at OyFE and OyFF.
Inside the interrupt service routine, the associated pending
bit has to be cleared by software. The RETI (Return from
Interrupt) instruction at the end of the interrupt service routine will set the GIE (Global Interrupt Enable) bit, allowing
the processor to be interrupted again if another interrupt is
active and pending.
If, by accident, a VIS gets executed and no interrupt is active, then the PC (Program Counter) will branch to a vector
located at OyEO-OyE1. This vector can point to the Software Trap (Sn interrupt service routine, or to another special service routine as desired.
Figure 12 shows the COPSSSCF Interrupt block diagram.
2-104
o
Interrupts
The lower limit of the service window is fixed at 2048 instruction cycles. Bits 7 ad 6 of the WDCNT register allow
the user to pick an upper limit of the service window.
(Continued)
SOFTWARE TRAP
The Software Trap (ST) is a special kind of non-maskable
interrupt which occurs when the INTR instruction (used to
acknowledge interrupts) is fetched from ROM and placed
inside the instruction register. This may happen when the
PC is pointing beyond the available ROM address space or
when the stack is over-popped.
When an ST occurs, the user can re-initialize the stack
pointer and do a recovery procedure (similar to RESET, but
not necessarily containing all of the same initialization procedures) before restarting.
The occurrence of an ST is latched into the ST pending bit.
The GIE bit is not affected and the ST pending bit (not
accessible by the user) is used to inhibit other interrupts
and to direct the program to the ST service routine with the
VIS instruction.
It is cleared by RESET and by the RPND instruction.
The ST has the highest rank among all interrupts.
Nothing (except another ST) can Interrupt an ST being
serviced.
The COP888CF contains a WatchDog and clock monitor.
The WatchDog is designed to detect the user program getting stuck in Infinite loops resulting In loss of program control or "runaway" programs. The Clock Monitor Is used to
detect the absence of a clock or a very slow clock below a
specified rate on the CKI pin.
Table II shows the four possible combinations of lower and
upper limits for the WatchDog service window. This flexibility in choosing the WatchDog service window prevents any
undue burden on the user software.
Bits 5, 4, 3, 2 and 1 of the WDCNT register represent the 5bit Key Data field. The key data is fixed at 01100. Bit 0 of the
WDCNT Register is the Clock Monitor Select bit.
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TABLE I
Window
Select
X
1
7
Clock
Monitor
Key Data
X
0 1111Jo1o
6
5
4
3
y
o
2
TABLE II
WDCNT
Blt7
WDCNT
Blt6
0
0
1
1
0
1
0
1
Service Window
(Lower-Upper Limits)
2k-8k to Cycles
2k-16k to Cycles
2k-32k to Cycles
2k-64k to Cycles
Clock Monitor
The Clock Monitor aboard the COP888CF can be selected
or deselected under program control. The Clock Monitor is
guaranteed not to reject the clock if the instruction cycle
clock (1 Ito) is greater or equal to 10kHz. This equates to a
clock input rate on CKI of greater or equal to 100 kHz.
WatchDog
The COP888CF WatchDog consists of two independent
logic blocks: WD UPPER and WD LOWER. WD UPPER establishes the upper limit on the service window and WD
LOWER defines the lower limit of the service window.
Servicing the WatchDog consists of writing a specific value
to a WatchDog Service Register named WDCNT which is
memory mapped in the RAM. This value is composed of
three fields, consisting of a 2-bit Window Select, a 5-bit Key
Data field, and the 1-bit Clock Monitor Select field. Table I
shows the WDCNT register.
SOfTWARE
o-a
WatchDog Operation
The WatchDog and Clock Monitor are disabled during
RESET. The COP888CF comes out of RESET with the
WatchDog armed, the WatchDog Window Select bits (bits 6,
•
--------------1
TIMER T1 AND T2
EXTERNAL
WAKE UP
INTERRUPT
J.'WIRE
PERIPHERALS
IDLE TIMER
Tl/DD/9425-1 B
FIGURE 12. COP888CF Interrupt Block Diagram
2-105
~
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r-------------------------------------------------------------------------~
WatchDog Operation (Continued)
7 of the WDCNT Register) set, and the Clock Monitor bit (bit
o of the WDCNT Register) enabled. Thus, a Clock Monitor
error will occur after coming out of RESET, if the instruction
cycle clock frequency has not reached a minimum specified
value, including the case where the oscillator fails to start.
The WDCNT register can be written to only once after
RESET and the key data (bits 5 through 1 of the WDCNT
Register) must match to be a valid write. This write to the
WDCNT register involves two irrevocable choices: (i) the
selection of the WatchDog service window (ii) enabling or
disabling of the Clock Monitor. Hence, the first write to
WDCNT Register involves selecting or deselecting the
Clock Monitor, select the WatchDog service window and
match the WatchDog key data. Subsequent writes to the
WDCNT register will compare the value being written by the
user to the WatchDog service window value and the key
data (bits 7 through 1) in the WDCNT Register. Table III
shows the sequence of events that can occur.
The user must service the WatchDog at least once before
the upper limit of the serivce window expires. The WatchDog may not be serviced more than once in every lower
limit of the service window. The user may service the
WatchDog as many times as wished in the time period between the lower and upper limits of the service window. The
first write to the WDCNT Register is also counted as a
WatchDog service.
The WatchDog has an output pin associated with it. This is
the WDOUT pin, on pin 1 of the port G. WDOUT is active
low. The WDOUT pin is in the high impedance state in the
inactive state. Upon triggering the WatchDog, the logic will
pull the WDOUT (G1) pin low for an additional 16 to-32 te
cycles after the signal level on WDOUT pin goes below the
lower Schmitt trigger threshold. After this delay, the
COP888CF will stop forcing the WDOUT output low.
fied value, after which the G1 output will enter the high impedance TRI-STATE mode following 16 te-32 te clock cycles. The Clock Monitor generates a continual Clock Monitor error if the oscillator fails to start, or fails to reach the
minimum specified frequency. The specification for the
Clock Monitor is as follows:
1/te > 10kHz-No clock rejection.
1/te < 10Hz-Guaranteed clock rejection.
MICROWIRE/PLUS
MICROWIRE/PlUS is a serial synchronous communications interface. The MICROWIRE/PlUS capability enables
the COP888CF to interface with any of National Semiconductor's MICROWIRE peripherals (i.e. AID converters,display drivers, E2PROMs etc.) and with other microcontrollers
which support the MICROWIRE interface. It consists of an
8-bit serial shift register (SIO) with serial data input (SI), serial data output (SO) and serial shift clock (SK). Figure 13
shows a block diagram of the MICROWIRE logic.
1-------" INTERRUPT
~~---~----------~so
~-~~~~..-----SI
SK
TLlDD/9425-20
FIGURE 13. MICROWIRE Block Diagram
The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIRE
arrangement with the internal clock source is called the
Master mode of operation. Similarly, operating the MICROWIRE arrangement with an external shift clock is called the
Slave mode of operation.
The CNTRl register is used to configure and control the
MICROWIRE mode. To use the MICROWIRE, the MSEl bit
in the CNTRl register is set to one. The SK clock rate is
selected by the two bits, SlO and Sl1, in the CNTRl register. Table IV details the different clock rates that may be
selected.
The WatchDog service window will restart when the
WDOUT pin goes inactive. It is recommended that the user
tie the WDOUT pin back to Vee through a resistor in order
to pull WDOUT high.
A WatchDog service while the WDOUT signal is active will
be ignored. The state of the WDOUT pin is not guaranteed
at RESET, but if it powers up low then the WatchDog will
time out and disable.
The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error. The Clock Monitor error will continue
until the clock frequency has reached the minimum speci-
TABLE III
Key
Data
Window
Data
Clock
Monitor
Action
Valid Service: Restart Service Window
Match
Match
Match
Don't Care
Mismatch
Don't Care
Error: Generate WatchDog Output
Mismatch
Don't Care
Don't Care
Error: Generate WatchDog Output
Don't Care
Don't Care
Mismatch
Error: Generate WatchDog Output
TABLE IV
SL1
SLO
SK
0
0
1
0
1
x
2 X te
4 x te
8 x te
Where te is the instruction cycle clock
2-106
~----------------------------------------------------------------------'O
o"'a
MICROWIRE/PLUS (Continued)
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by
the Master will be shifted properly. After eight clock pulses
the BUSY flag will be cleared and the sequence may be
repeated.
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift.
The COP888CF may enter the MICROWIRE/PLUS mode
either as a Master or as a Slave. Figure 14 shows how two
COP888CF microcontrollers and several peripherals may be
interconnected using the MICROWIRE/PLUS arrangements.
Alternate SK Phase Operation
The COP888CF allows either the normal SK clock or an
alternate phase SK clock to shift data in and out of the SIO
register. In both the modes the SK is normally low. In the
normal mode data is shifted in on the rising edge of the SK
clock and the data is shifted out on the falling edge of the
SK clock. The SIO register is shifted on each falling edge of
the SK clock in the normal mode. In the alternate SK phase
operation, data is shifted in on the falling edge of the SK
clock ahd shifted out on the rising edge of the SK clock. In
the alternate SK phase mode the SIO register is shifted on
the rising edge of the SK clock.
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alternate SK clock. The SKSEL is mapped into the G6 configuration bit. The SKSEL flag will power up in the reset condition,
selecting the normal SK signal.
Warning:
The SIO register should only be loaded when the SK clock
is low. Loading the SIO register while the SK clock is high
will result in undefined data in the SIO register.
Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PLUS slave mode may cause the current SK
clock forthe SIO shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is
low.
MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally by the COP888CF.
The MICROWIRE Master always initiates all data exchanges. The MSEL bit in the CNTRL register must be set to
enable the SO and SK functions onto the G Port. The SO
and SK pins must also be selected as outputs by setting
appropriate bits in the Port G configuration register. Table III
summarizes the bit settings required for Master mode of
operation.
TABLE V
This table assumes that the control flag MSEL is set.
G4 (SO)
Conflg. Bit
G5 (SK)
Conflg. Bit
G4
Fun.
G5
Fun.
Operation
1
1
SO
Int.
SK
MICROWIRE
Master
0
1
TRISTATE
Int.
SK
MICROWIRE
Master
1
0
SO
Ext.
SK
MICROWIRE
Slave
0
0
TRISTATE
Ext.
SK
MICROWIRE
Slave
MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the
SKclock is generated by an external source. Setting the
MSEL bit in the CNTRL register enables the SO and SK
functions onto the G Port. The SK pin must be selected as
an input and the SO pin is selected as an output pin by
setting and resetting the appropriate bit in the Port G configuration register. Table V summarizes the settings required to
enter the Slave mode of operation.
8- BIT
I/o
AID
LINES
COPS
MASTER
COP43X
LCD
DISPLAY
DRIVER
COP472
lK BYTE
EEPROM
COP495
VF
DISPLAY
DRIVER
COP470
I/O
LINES
COPS
(SLAVE)
SI~~~~----~~+------+~------~~-iSO
~
~
~
~
TL/OO/942S-21
FIGURE 14. MICROWIRE Application
2-107
Q)
Q)
Q)
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~ r-------------------------------------------------------------------~
oco
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Q.
oo
Memory Map
Addressing Modes
All RAM, ports and registers (except A and PC) are mapped
into data memory address space
The COP888CF has ten addressing modes, six for operand
addressing and four for transfer of control.
Address
00 to 6F
OPERAND ADDRESSING MODES
Contents
Register Indirect
On-Chip RAM bytes
70 to BF
Unused RAM Address Space
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CDtoCF
Timer T2 Lower Byte
Timer T2 Upper Byte
Timer T2 Autoload Register T2RA Lower Byte
Timer T2 Autoload Register T2RA Upper Byte
Timer T2 Autoload Register T2RB Lower Byte
Timer T2 Autoload Register T2RB Upper Byte
Timer T2 Control Register
WatchDog Service Register (Reg:WDCNT)
MIWU Edge Select Register (Reg:WKEDG)
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register (Reg:WKPND)
AID Converter Control Register (Reg:ENAD)
AID Converter Result Register (Reg: ADRSLT)
Reserved
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
ODto DF
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port D Data Register
Reserved for Port D
EO to E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
Reserved
Timer T1 Autoload Register T1 RB Lower Byte
Timer T1 Autoload Register T1 RB Upper Byte
ICNTRL Register
MICROWIRE Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1 RA Lower Byte
Timer T1 Autoload Register T1 RA Upper Byte
CNTRL Control Register
PSW Register
FO to FB
FC
FD
FE
FF
On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
Reserved
This is the "normal" addressing mode for the COP888CF.
The operand is the data memory addressed by the B pointer
or X pointer.
Register Indirect (with auto post Increment or
decrement of pointer)
This addressing mode is used with the LD and X instructions. The operand is the data memory addressed by the B
pointer or X pointer. This is a register indirect mode that
automatically post increments or decrements the B or X register after executing the instruction.
Direct
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
Immediate
The instruction contains an 8-bit immediate field as the operand.
Short Immediate
This addressing mode is used with the LBI instruction. The
instruction contains a 4-bit immediate field as the operand.
Indirect
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.
TRANSFER OF CONTROL ADDRESSING MODES
Relative
This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new
program location. JP has a range from -31 to +32 to allow
a 1-byte relative jump (JP + 1 is implemented by a NOP
instruction). There are no "pages" when using JP, since all
15 bits of PC are used.
Absolute
This mode is used with the JMP and JSR instructions, with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any location in the current 4k program memory segment.
Absolute Long
This mode is used with the JMPL and JSRL instructions,
with the instruction field of 15 bits replacing the entire 15
bits of the program counter (PC). This allows jumping to any
location in the current 4k program memory space.
Indirect
This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits
of PC) for accessing a location in the program memory. The
contents of this program memory location serve as a partial
address (lower 8 bits of PC) for the jump to the next instruction.
Reading memory locations 70-7F Hex will return all ones. Reading other
unused memory locations will return undefined data.
Note: The VIS is a special case of the Indirect Transfer of Control addressing mode, where the double byte vector associated with the interrupt
is transferred from adjacent addresses in the program memory into
the program counter (PC) in order to jump to the associated interrupt
service routine.
2-108
o
a"tJ
Instruction Set
Q)
Q)
Q)
Register and Symbol Definition
Symbols
Registers
A
B
X
SP
PC
PU
PL
C
HC
GIE
VU
VL
[B)
8-Bit Accumulator Register
8-Bit Address Register
a-Bit Address Register
8-Bit Stack Pointer Register
15-Bit Program Counter Register
Upper 7 Bits of PC
Lower 8 Bits of PC
1 Bit of PSW Register for Carry
1 Bit of PSW Register for Half Carry
1 Bit of PSW Register for Global
Interrupt Enable
Interrupt Vector Upper Byte
Interrupt Vector Lower Byte
[X]
MD
Mem
Meml
Imm
Reg
Bit
<<->
2-109
Memory Indirectly Addressed by B
Register
Memory Indirectly Addressed by X
Register
Direct Addressed Memory
Direct Addressed Memory or [B)
Direct Addressed Memory or [B) or
Immediate Data
a-Bit Immediate Data
Register Memory: Addresses FO to FF
(Includes B. X and SP)
Bit Number (0 to 7)
Loaded with
Exchanged with
o"n
LL
o
r------------------------------------------------------------------------------------,
~
Instruction Set (Continued)
~
INSTRUCTION SET
oo
ADD
ADC
A,Meml
A,Meml
ADD
ADD with Carry
SUBC
A,Meml
Subtract with Carry
AND
ANDSZ
OR
XOR
IFEQ
IFEQ
IFNE
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND
A,Meml
A,lmm
A,Meml
A,Meml
MD,lmm
A,Meml
A,Meml
A,Meml
#
Reg
#,Mem
#,Mem
#,Mem
Logical AND
Logical AND Immed., Skip if Zero
Logical OR
Logical EXclusive OR
IF EQual
IF EQual
IF Not Equal
IF Greater Than
If B Not Equal
Decrement Reg., Skip if Zero
Set BIT
Reset BIT
IF BIT
Reset PeNDing Flag
A <- A + Meml
A < - A + Meml + C, C < - Carry
HC < - Half Carry
A < - A - Meml + C, C < - Carry
HC < - Half Carry
A < - A and Meml
Skip next if (A and Imm) = 0
A <- AorMeml
A < - A xor Meml
Compare MD and Imm, Do next if MD = Imm
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A not = Meml
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of B not = Imm
Reg < - Reg- 1, Skip if Reg = 0
1 to bit, Mem (bit = 0 to 7 immediate)
Oto bit, Mem
If bit in A or Mem is true do next instruction
Reset Software Interrupt Pending Flag
X
LD
LD
LD
LD
A,Mem
A,Meml
B,lmm
Mem,lmm
Reg,lmm
EXchange A with Memory
LoaD A with Memory
LoaD B with Immed.
LoaD Memory Immed
LoaD Register Memory Immed.
A <-> Mem
A <- Meml
B <-Imm
Mem <- Imm
Reg <-Imm
X
X
LD
LD
LD
A, [B ±]
A, [X ±]
A, [B±]
A, [X±]
[B±],lmm
EXchange A with Memory [B)
EXchange A with Memory [X]
LoaD A with Memory [B)
LoaD A with Memory [X]
LoaD Memory [B) Immed.
A < - > [B), (B < - B ± 1)
A < - > [X], (X < - ± 1)
A < - [B), (B < - B ± 1)
A < - [X], (X < - X ± 1)
[B) <-Imm, (B <- B±1)
CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
RC
IFC
IFNC
POP
PUSH
A
A
A
CLeaR A
INCrementA
DECrementA
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
SetC
ResetC
IFC
IF Not C
POP the stack into A
PUSH A onto the stack
A<-O
A<- A + 1
A<-A-1
A < - ROM (PU,A)
A < - BCD correction (follows ADC, SUBC)
C - > A7 - > ... - > AO - > C
C < - A7 < - ... < - AO < - C
A7 ... A4 < - > A3 ... AO
C <- 1, HC <- 1
C <- 0, HC <- 0
IF C is true, do next instruction
If C is not true, do next instruction
SP <- SP + 1,A <- [SP]
[SP] < - A, SP < - SP - 1
Vector to Interrupt Service Routine
Jump absolute Long
Jump absolute
Jump relative short
Jump SubRoutine Long
Jump SubRoutine
Jump InDirect
RETurn from subroutine
RETurn and SKip
RETurn from Interrupt
Generate an Interrupt
No OPeration
PU < - [VU], PL < - [VL]
PC < - ii (ii = 15 bits, 0 to 32k)
PCg ... O < - i (i = 12 bits)
PC < - PC + r (r is - 31 to + 32, not 1)
[SP] < - PL, [SP-1] < - PU,SP-2, PC < - ii
[SP] < - PL, [SP-1] < - PU,SP-2, PCg ... 0 < - i
PL < - ROM (PU,A)
SP + 2, PL < - [SP], PU < - [SP -1]
SP + 2, PL < -[SP],PU < - [SP-1],Skip < - 1
SP + 2, PL < - [SP],PU < - [SP-1],GIE< - 1
[SP] < - PL, [SP-1] < - PU, SP-2, PC < - OFF
PC <- PC + 1
VIS
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
A
A
A
A
A
A
Addr.
Addr.
Disp.
Addr.
Addr
2-110
0
a"'tJ
Instruction Execution Time
Most instructions are single byte (with immediate addressing mode instructions taking two bytes).
Most single byte instructions take one cycle time (1 P.s at
10 MHz) to execute.
See the BYTES and CYCLES per INSTRUCTION table for
details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles
for each instruction in the format of byte/cycle (a cycle is 1
P.s at 10 MHz).
[B)
Direct
ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFNE
IFGT
IFBNE
DRSZ
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
SBIT
RBIT
IFBIT
1/1
1/1
1/1
3/4
3/4
3/4
RPND
1/1
Instructions Using A & C
CLRA
INCA
DECA
LAID
DCOR
RRCA
RLCA
SWAPA
SC
RC
IFC
IFNC
PUSHA
POPA
ANDSZ
Immed.
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2
Transfer of Control
Instructions
JMPL
JMP
JP
JSRL
JSR
JID
VIS
RET
RETSK
RETI
INTR
NOP
1/3
Memory Transfer Instructions
Register
Indirect
XA,·
LDA,·
LDB,lmm
LD B,lmm
LDMem,lmm
LDReg,lmm
IFEQMD,lmm
[B]
[X]
1/1
1/1
1/3
1/3
2/2
Direct Immed.
2/3
2/3
2/2
1/1
2/2
3/3
2/3
3/3
Register Indirect
Auto Incr. & Decr.
[B+,B-]
[X+,X-]
1/2
1/2
1/3
1/3
(IF B < 16)
(IFB> 15)
2/2
• = > Memory location addressed by B or X or directly.
2-111
3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5
1/7
1/1
co
co
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0
"T1
~
oco
r---------------------------------------------------------------------------~
co
COP888CF Opcode Table
Q.
Upper Nibble Along X-Axis
CO
o
o
Lower Nibble Along Y-Axis
F
E
D
JP -15
JP -31
LOOFO, # i
ORSZOFO
JP -14
JP -30
LO OF1, # i
ORSZOF1
JP -13
JP -29
LOOF2, # i
ORSZOF2
JP -12
JP -28
LOOF3, # i
JP -11
JP -27
LO OF4, # i
JP -10
JP -26
LOOF5, # i
JP -9
JP -25
LOOF6, # i
JP -8
JP -24
LOOF7, # i
ORSZOF7
JP -7
JP -23
LOOF8, # i
ORSZOF8
JP -6
JP -22
LOOF9, # i
JP -5
JP -21
JP -4
JP -20
JP -3
A
B
C
9
8
·
RC
AOCA,#i
AOCA,[B]
SC
SUBCA, #i
SUBA,[B]
1
XA,[X+]
XA,[B+]
IFEOA,#i
IFEOA,[B]
2
ORSZOF3
XA, [X-]
XA,[B-]
IFGT A,#i
IFGTA,[B]
3
ORSZOF4
VIS
LAID
AOOA,#i
AOOA,[B]
4
ORSZOF5
RPNO
JIO
ANOA,#i
ANOA,[B]
5
ORSZOF6
XA,[X]
.
XORA,#i
XORA,[B]
6
ORA,#i
ORA,[B]
7
NOP
RLCA
LOA,#i
IFC
8
ORSZOF9
IFNE
A,[B]
IFEO
Md,#i
IFNE
A,#i
IFNC
9
LOOFA, # i
ORSZOFA
LOA,[X+]
LOA,[B+]
LO [B+],#i
INCA
A
LOOFB, # i
ORSZOFB
LOA,[X-]
LOA,[B-]
LO[B-]'#I
OECA
B
JP -19
LOOFC, # i
ORSZOFC
LO Md,#1
JMPL
XA,Md
POPA
C
JP -2
JP -18
LOOFO, # i
ORSZOFO
OIR
JSRL
LOA,Md
RETSK
0
JP -1
JP -17
LOOFE, # 1
ORSZOFE
LOA,[X]
LOA,[B]
LO [B],#I
RET
E
JP -0
JP -16
LOOFF, # 1
ORSZOFF
•
LOB,#i
RETI
F
RRCA
·
·
2-112
XA,[B]
0
(")
COP888CF Opcode Table
o
(Continued)
"tJ
Upper Nibble Along X-Axis
(X)
(X)
(X)
Lower Nibble Along Y-Axis
(")
7
6
5
IFBIT
O,[B]
ANDSZ
A, #i
LD B,#OF
IFBIT
1,[B]
*
IFBIT
2,[B]
4
-n
3
2
1
IFBNEO
JSR
xOOO-xOFF
JMP
xOOO-xOFF
JP +17
INTR
0
LD B,#OE
IFBNE 1
JSR
x100-x1FF
JMP
x100-x1FF
JP +1B
JP + 2
1
*
LD B,#OD
IFBNE2
JSR
x200-x2FF
JMP
x200-x2FF
JP +19
JP + 3
2
IFBIT
3,[B]
*
LD B,#OC
IFBNE3
JSR
x300-x3FF
JMP
x300-x3FF
JP +20
JP + 4
3
IFBIT
4,[B]
CLRA
LD B,#OB
IFBNE4
JSR
x400-x4FF
JMP
x400-x4FF
JP +21
JP + S
4
IFBIT
S,[B]
SWAPA
LD B,#OA
IFBNES
JSR
xSOO-xSFF
JMP
xSOO-xSFF
JP +22
JP + 6
S
IFBIT
6,[B]
DCORA
LD B,#09
IFBNE 6
JSR
x600-x6FF
JMP
x600-x6FF
JP +23
JP + 7
6
IFBIT
7,[B]
PUSHA
LD B,#OB
IFBNE7
JSR
x700-x7FF
JMP
x700-x7FF
JP +24
JP + B
7
SBIT
O,[B]
RBIT
O,[B]
LD B,#07
IFBNEB
JSR
xBOO-xBFF
JMP
xBOO-xBFF
JP +2S
JP + 9
B
SBIT
1,[B]
RBIT
1,[B]
LD B,#06
IFBNE 9
JSR
x900-x9FF
JMP
x900-x9FF
JP +26
JP + 10
9
SBIT
2,[B]
RBIT
2,[B]
LD B,#OS
IFBNEOA
JSR
xAOO-xAFF
JMP
xAOO-xAFF
JP +27
JP + 11
A
SBIT
3,[B]
RBIT
3,[B]
LD B,#04
IFBNEOB
JSR
xBOO-xBFF
JMP
xBOO-xBFF
JP +2B
JP + 12
B
SBIT
4,[B]
RBIT
4,[B]
LD B,#03
IFBNEOC
JSR
xCOO-xCFF
JMP
xCOO-xCFF
JP +29
JP + 13
C
SBIT
S,[B]
RBIT
S,[B]
LD B,#02
IFBNEOD
JSR
xDOO-xDFF
JMP
xDOO-xDFF
JP +30
JP + 14
D
SBIT
6,[B]
RBIT
6,[B]
LD B,#01
IFBNEOE
JSR
xEOO-xEFF
JMP
xEOO-xEFF
JP +31
JP + 1S
E
SBIT
7,[B]
RBIT
7,[B]
LD B,#OO
IFBNEOF
JSR
xFOO-xFFF
JMP
xFOO-xFFF
JP +32
JP + 16
F
Where,
i is the immediate data
Md is a directly addressed memory location
• is an unused opcode
Note: The opcode 60 Hex is also the opcode for IFBIT #i,A
2-113
0
U.
o
CX)
CX)
CX)
D-
O
o
r---------------------------------------------------------------------------------------~
Mask Options
Development Support
The COP888CF mask programmable options are shown be·
low. The options are programmed at the same time as the
ROM pattern submission.
MOLE DEVELOPMENT SYSTEM
The MOLE (Microcomputer On Line Emulator) is a low cost
development system and emulator for all microcontroller
products. These include COPSTM microcontrollers and the
HPC family of products. The MOLE consists of a BRAIN
Board, Personality Board and optional host software.
OPTION 1: CLOCK CONFIGURATION
1
Crystal Oscillator (CKI/IO)
G7 (CKO) is clock generator
output to crystal/resonator
CKI is the clock input
2
Single-pin RC controlled
oscillator (CKI/lO)
G7 is available as a HALT
restart and/or general purpose
input
=
The purpose of the MOLE is to provide the user with a tool
to write and assemble code, emulate code for the target
microcontroller and assist in both software and hardware
debugging of the system.
=
It is a self contained computer with its own firmware which
provides for all system operation, emulation control, com·
munication, PROM programming and diagnostic operations.
It contains three serial ports to optionally connect to a termi·
nal, a host system, a printer or a modem, or to connect to
other MOLEs in a multi·MOLE environment.
OPTION 2: HALT
1
Enable HALT mode
2
Disable HALT mode
=
=
MOLE can be used in either a stand alone mode or in con·
junction with a selected host system using PC· DOS commu·
nicating via a RS·232 port.
OPTION 3: COP888CF BONDING
1
44-Pin PLCC
40-Pin DIP
2
28-Pin PLCC
3
28-Pin DIP
4
=
=
=
=
How to Order
To order a complete development package, select the sec·
tion for the microcontroller to be developed and order the
parts listed.
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (if clock option·1 has been selected). The
CKI input frequency is divided down by 10 to produce the
instruction cycle clock (1 ltd.
Development Tools Selection Table
Mlcrocontroller
COP888
Order
Part Number
Description
Includes
Manual
Number
MOLE·BRAIN
Brain Board
Brain Board Users Manual
420408188·001
MOLE·COP8·PB2
Personality Board
COP888 Personality Board
Users Manual
420420084·001
MOLE·COP8·IBM
Assembler Software for IBM
COP800 Software Users Manual
and Software Disk
PC·DOS Communications
Software Users Manual
424410527·001
TBD
Programmer's Manual
2·114
420040416·001
TBD
o
o
Development Support (Continued)
If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk for
later use.
DIAL-A-HELPER
Dial-A-Helper is a service provided by the MOLE (Microcontroller On Line Emulator) applications group. It consists of
an electronic bulletin board information system and a method by which applications can take control of a MOLE Development System at a remote site via modem in order to resolve any problems.
"
(X)
(X)
(X)
o
'TI
Order PIN: MOLE-DIAL-A-HLP
Information System Package Contents
Dial-A-Helper User Manual
Public Domain Communications Software
Information System
The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION mode
that can be used to search out and retrieve application data
about NSC Microcontrollers. The user needs as a minimum,
a Dumb terminal, 300 or 1200 baud modem, and a telephone.
Voice:
Modem:
Factory Applications Support
Dial-A-Helper also provides immediate factor applications
support. If a user is having difficulty in getting a MOLE to
operate in a particular mode or something peculiar is occuring, he can contact us via his system and modem. He can
leave messages on our electronic bulletin board, which we
will responed to, or he can arrange for us to actually take
control of his system via modem for debugging purposes.
The applications group can then cause his system to execute various commands and try to resolve the customer's
problem by actually getting customer's system to respond.
Both parties see exactly what is occurring, as it is happening.
(408) 721-5582
(408) 739-1162
Baud:
300 or 1200 Baud
Set-up:
Length:
Parity:
Stop Bit
This allows us to respond in minutes when applications help
is needed.
8-Bit
None
Operation: 24 Hours, 7 Days
DIAL-A-HELPER
HOST
~OLE
CO~PUTER
NATIONAL
USER SITE
SE~ICONDUCTOR
SITE
TLlDD/9425-24
2-115
•
CJ
i
~
o
~National
U Semiconductor
ADVANCE
INFORMATION
COP888CG Single-Chip microCMOS Microcontroller
General Description
The COP888 family of microcontrollers uses an 8-bit single
chip core architecture fabricated with National Semiconductor's M2CMOSTM process technology. The COP888CG is a
member of this expandable 8-bit core processor family of
microcontrollers.
(Continued)
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Low cost 8-bit microcontroller
Fully static CMOS, with low current drain
Two power saving modes: HALT and IDLE
1 Ils instruction cycle time
4096 bytes on-board ROM
192 bytes on-board RAM
Single supply operation: 2.5V -6V
Full duplex UART
Two comparators
MICROWIRE/PLUSTM serial 1/0
Watch Dog and Clock Monitor logic
Idle Timer
Three 16-bit timers, each with two 16-bit registers
supporting:
- Processor Independent PWM mode
- External Event counter mode
- Input Capture mode
• Multi-Input Wakeup (MIWU) with optional interrupts (8)
• Fourteen multi-source vectored interrupts servicing
- External Interrupt
- Idle Timer TO
- Timers (6)
- MICROWIRE/PLUS
- Multi-Input Wake Up
- Software Trap
-UART (2)
• 8-bit Stack Pointer SP (stack in RAM)
• Two 8-bit Register Indirect Data Memory Pointers
(B and X)
• Versatile instruction set
• True bit manipulation
• Memory mapped I/O
• BCD arithmetic instructions
• Package: 44 PCC or 40 N or 28 N or 28 PCC
- 44 PCC with 39 I/O pins
- 40 N with 35 I/O pins
- 28 PCC or 28 N, each with 23 I/O pins
• Software selectable I/O options
- TRI-STATE® Output
- Push-Pull Output
- Weak Pull Up Input
- High Impedance Input
• Schmitt trigger inputs on ports G and L
• Extended temperature range: - 55°C to + 125°C
• ROM less mode for accurate emulation and external
program capability
• Single chip COP8XX piggy back emulation device
• Real time emulation and full program debug offered by
National's MOLETM Development System
Block Diagram
B BIT CORE
t.40DIFIED HARVARD
ARCHITECTURE
CPU REGISTERS
TLlDD/9765-1
FIGURE 1. COP888CG Block Diagram
2-116
o
o
General Description
(Continued)
It is a fully static part, fabricated using double-metal-silicon
gate microCMOS technology. Features include an 8-bit
memory mapped architecture, MICROWIRE/PLUS serial
I/O, three 16-bit timer/counters supporting three modes
(Processor Independent PWM generation, External Event
counter, and Input Capture mode capabilities), full duplex
UART, two comparators, and two power savings modes
(HALT and IDLE), both with a multi-sourced wakeup/interrupt capability. This multi-sourced interrupt capability may
"'C
also be used independent of the HALT or IDLE modes.
Each I/O pin has software selectable configurations. The
COP888CG operates over a voltage range of 2.5V to 6V.
High throughput is achieved with an efficient, regular instruction set operating at a maximum of 1 I-Ls per instruction
rate. The COP888CG may be operated in the ROM less
mode to provide for accurate emulation and for applications
requiring external program memory.
Q)
Q)
Q)
oG)
Connection Diagrams
Plastic Chip Carrier
Dual-In-Llne Package
40
C2
CKI
7
GO
Vee
8
38
RESET
IO/ACHO
9
37
GNO
I1/ACHI
10
36
07
35
06
34
05
44 pin
PLCC
12/ACH2
11
13/ACH3
12
14/ACH4
13
33
04
15/ACH5
14
32
03
16/ACH6
15
31
02
17/ACH7
16
30
01
LO
17
29
00
Cl
39
CO
38
G3
37
G2
G6
G7
RESET
I1/ACHI
12/ACH2
05
13/ACH3
04
14/ACH4
03
15/ACH5
02
01
DO
TL/DD/9765-2
Top View
L7
LO
Order Number COP888CG-XXX/V
See NS Plastic Chip Package Number V44A
Plastic Chip Carrier
L2
L3
23
L6
22
L5
21
L4
20
TL/DD/9765-4
Top View
4
CKI
3
2
25
Vee
IO/ACHO
Order Number COP888G-XXX/N
See NS Molded Package Number N40A
Dual-ln-L1ne Package
1 28 27 26
5
28 pin
PLCC
GO
24
RESET
23
GNO
I1/ACHI
8
22
03
12
9
21
02
G3
13
10
20
01
G2
LO
11
00
Gl
GO
TLlDD/9765-3
CKI
RESET
Vee
GNO
03
10/ACHO
Top View
II/ACHI
Order Number COP884CG-XXX/V
See NS Plastic Chip Package Number V28A
8
13
10
19
DO
LO
11
18
L7
Ll
12
17
L6
L2
13
16
L5
L3
14
15
U
TL/DD/9765-5
Top View
Order Number COP884CG-XXX/N
See NS Molded Package Number N28A
FIGURE 2a. COP888CG Connection Diagrams
2-117
•
CJ
gco
Connection Diagrams (Continued)
~
COP888CG Pinouts for 28-, 40- and 44-Pin Packages
o
o
Port
LO
L1
L2
L3
L4
L5
L6
L7
GO
G1
G2
G3
G4
G5
G6
G7
Type
Alt. Fun
liD
liD
liD
liD
liD
liD
liD
liD
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
liD
INT
Alt. Fun
CKX
TDX
RDX
T2A
T2B
T3A
T3B
WDOUT
liD
liD
liD
liD
I
CKO/I
T1B
T1A
SO
SK
SI
40-Pin
Pack.
44-Pin
Pack.
11
12
13
14
15
16
17
18
17
18
19
20
21
22
23
24
18
19
20
25
26
27
28
25
26
27
28
1
2
3
4
35
36
37
38
3
4
5
6
39
40
41
42
3
4
5
6
17
DO
D1
D2
D3
0
0
0
0
ROM DATA+
PCL+
EMUL +
PCU+
19
20
21
22
25
26
27
28
29
30
31
32
10
11
12
13
I
I
I
I
COMP1INCOMP1IN+
COMP10UT
7
8
9
10
9
10
11
12
9
10
11
12
14
15
16
17
I
I
I
I
COMP2INCOMP2IN+
COMP20UT
-
13
14
15
16
13
14
15
16
D4
D5
D6
D7
0
0
0
0
SCLOCK+
HALTSEL +
LOAD+
D DATA+
29
30
31
32
33
34
35
36
CO
C1
C2
C3
C4
C5
C6
C7
liD
liD
liD
liD
liD
liD
liD
liD
39
40
1
2
43
44
1
2
21
22
23
24
8
33
7
34
8
37
7
38
6
23
5
24
Vee
GND
GKI
RESET
-
28-Pin
Pack.
= Unbonded Pins
Only in the ROMless Mode
+ =
2·118
o
o"tJ
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (Vee)
Voltage at Any Pin
Total Current out of GND Pin (Sink)
Storage Temperature Range
-0.3V to Vee + 0.3V
2000V
Total Current into Vee Pin (Source)
- 65°C to + 150°C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
7V
ESD Susceptibility (Note 4)
nOmA
Parameter
-40°C
~
TA
~
Conditions
Power Supply Ripple (Note 1)
Peak-to-Peak
Supply Current (Note 2)
CKI = 10 MHz
CKI = 4MHz
Vee
Vee
HALT Current (Note 3)
Vee
= 6V, tc = 1 Ils
= 2.5V, tc = 2.5 Ils
= 6V, CKI = 0 MHz
IDLE Current
CKI = 10 MHz
CKI = 4 MHz
Vee
Vee
= 6V, tc = 1 Ils
= 2.5V, tc = 2.5 Ils
Min
Typ
2.5
Input Levels
Reset
Logic High
Logic Low
Max
Units
6
V
0.1 Vee
V
15
2
mA
mA
<1
mA
mA
0.2 Vee
V
V
0.2 Vee
V
V
0.2 Vee
V
V
-2
+2
IlA
40
250
Il A
0.8 Vee
0.7 Vee
All Other Inputs
Logic High
Logic Low
0.7 Vee
Hi-Z Input Leakage
Vee
Input Pullup Current
Vee
= 6V, VIN = OV
= 6V, VIN = OV
G and L Port Input Hysteresis
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
V
0.05 Vee
= 4V, VOH = 3.3V
= 2.5V, VOH = 1.8V
= 4V, VOL = 1V
= 2.5V, VOL = O.4V
0.4
0.2
mA
mA
10
0.2
mA
mA
Vee = 4V, VOH = 2.7V
Vee = 2.5V, VOH = 1.8V
10
2.5
= 4V, VOH = 3.3V
= 2.5V, VOH = 1.8V
Vee = 4V, VOL = O.4V
Vee = 2.5V, VOL = O.4V
0.4
0.2
mA
mA
1.6
0.7
mA
mA
Vee
Vee
Vee
Vee
Vee
Vee
-2
TRI-STATE Leakage
Note 1: Rate of voltage change must be less then 0.5
Il A
5
0.6
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
All Others
Source (Weak Pull-Up Mode)
G)
+85°C unless otherwise specified
Operating Voltage
Sink
o
100mA
DC Electrical Characteristics
Output Current Levels
D Outputs
Source
Q)
Q)
Q)
100
33
+2
IlA
IlA
IlA
Vlms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input. eKO open. inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee. Land G ports in the TRI·
STATE mode and tied to ground. all outputs low and tied to ground. The user must disable the clock monitor and the comparators.
Note 4: Human body model. 100 pF through 15000.
2-119
fII
"o
CO
CO
DC Electrical Characteristics
co
o
~ T A ~ + 85°C unless otherwise specified (Continued)
Max
Units
o
15
rnA
All others
3
rnA
Parameter
D-
O
-40°C
Conditions
Typ
Min
Allowable Sink/Source
Current per Pin
Outputs (Sink)
Maximum Input Current
without Latchup
RAM Retention Voltage, Vr
500 ns Rise
and Fall Time (Min)
200
rnA
2
V
Input Capacitance
Load Capacitance on 02
AC Electrical Characteristics
Parameter
Instruction Cycle Time (tel
Crystal, Resonator, or
External Oscillator
R/C Oscillator
CKI Clock Duty Cycle (Note 5)
Rise Time (Note 5)
Fall Time (Note 5)
-40°C
~
TA
7
pF
1000
pF
~ + 85°C unless otherwise specified
Conditions
Min
4V ~ Vee ~ 6V
2.5V ~ Vee < 4V
4V ~ Vee ~ 6V
2.5V ~ Vee < 4V
1
2.5
3
7.5
fr = Max
fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock
40
4V ~ Vee ~ 6V
2.5V ~ Vee < 4V
4V ~ Vee ~ 6V
2.5V ~ Vee < 4V
200
500
60
150
Typ
Max
Units
DC
DC
DC
DC
/Ls
/Ls
/Ls
/Ls
60
5
5
%
ns
ns
Inputs
tSETUP
tHOLD
Output Propagation Delay
tpD1, tpDO
SO,SK
All Others
ns
ns
ns
ns
RL = 2.2k, CL = 100 pF
4V ~ Vee ~ 6V
2.5V ~ Vee < 4V
4V ~ Vee ~ 6V
2.5V ~ Vee < 4V
0.7
/Ls
1
2.5
/Ls
/Ls
220
ns
ns
ns
20
56
MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Valid Time (tuv)
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
1
1
1
1
tc
tc
tc
tc
Reset Pulse Width
1
/LS
Note 5: Parameter sampled but not 100% tested.
2-120
Comparators AC and DC Characteristics Vee = 5V, TA = 25°C
Parameter
Conditions
Min
Typ
Max
Units
10
25
mV
O.4V ~ VIN ~ Vee - 1.5V
Input Offset Voltage
Input Common Mode Voltage Range
0.4
= O.4V
VOH = 4.6V
Low Level Output Current
High Level Output Current
V
Vee - 1.5
1.6
VOL
rnA
1.6
rnA
DC Supply Current (When Enabled)
250
Response Time
TBD mV Step, TBD mV
Overdrive, 100 pF Load
p.A
1
p.s
CKI
( +20MOOE)
CKI---.J
(+ 10 MODE)
I
-l tpDO
11 (XLO)
r-
I
I
-l tpDI
\
r,:
I
12 (PHI)
I
I
~
tpDI
1
l
-j""+\
t sETUP
) 5 x Power Supply Rise Time
FIGURE 5. Recommended RESET Circuit
013F
~
1
0000
+
0
W
E
R
Oscillator Circuits
ON CHIP RAM
(64 BYTES)
0100
TLIDD/9765-9
'Reads as all ones.
FIGURE 4. RAM Organization
Reset
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for ports l, G and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is
dedicated as the WatchDog andlor Clock Monitor error output pin. Port D is set high. The PC, PSW, ICNTRl, CNTRl,
T2CNTRl and T3CNTRl control registers are cleared. The
UART registers PSR, ENU (except that TBMT bit is set),
ENUR and ENUI are cleared. The Comparator Select Register is cleared. The S register is initialized to zero. The MultiInput Wakeup registers WKEN, WKEDG and WKPND are
cleared. The stack pointer, SP, is initialized to 6F Hex.
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input frequency is divided down by 10 to produce the instruction
cycle clock (1 ltd.
Figure 6 shows the Crystal and RIC diagrams.
EXTERNAL OSCILLATOR
CKI can be driven by an external clock signal provided it
meets the specified duty cycle, rise and fall times, and input
levels.
CRYSTAL OSCilLATOR
CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator.
RIC OSCILLATOR
By selecting CKI as a single pin oscillator input, a single pin
RIC oscillator circuit can be connected to it. CKO is available as a general purpose input, and lor HALT restart input.
R2
The COP888CG comes out of RESET with both the WatchDog logic and the Clock Monitor detector armed, with the
WatchDog service window bits set and the Clock Monitor bit
set. The WatchDog and Clock Monitor circuits are inhibited
during RESET. The WatchDog service window bits being
initialized high default to the maximum WatchDog service
window of 64k tc clock cycles. The Clock Monitor bit being
initialized high will cause a Clock Monitor error following RESET if the clock has not reached the minimum specified
frequency at the termination of RESET. A Clock Monitor
error will cause an active low error output on pin G1. This
error output will continue until 16 tc-32 tc clock cycles following the clock frequency reaching the minimum specified
value, at which time the G1 output will enter the TRI-STATE
mode.
RI
Vee
TLIDD/9765-12
TLIDD/9765-11
FIGURE 6. Crystal and RIC Oscillator Diagrams
2-124
(')
o"C
Current Drain
The total current drain of the chip depends on:
PSW Register (Address X'OOEF)
1. Oscillator operation mode-11
The PSW register contains the following select bits:
Q)
Q)
Q)
(')
C)
2. Internal switching current-12
GIE
Global interrupt enable (enables interrupts)
3. Internal leakage current-13
EXEN
Enable external interrupt
4. Output source current-14
5. DC current caused by external input
not at Vee or GND-15
6. Comparator DC supply current when enabled-16
BUSY
EXPND
MICROWIRE busy shifting flag
External interrupt pending
T1 ENA
Timer T1 Interrupt Enable for Timer Underflow
or T1 A Input capture edge
Thus the total current drain, It, is given as
T1 PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1, T1 Underflow in Mode 2, T1 A capture edge in mode 3)
C
Carry Flag
It = 11 + 12 + 13 + 14 + 15 + 16
To reduce the total current drain, each of the above components must be minimum.
HC
The chip will draw more current as the CKI input frequency
increases up to the maximum 10 MHz value. Operating with
a crystal network will draw more current than an external
square-wave. Switching current, governed by the equation
below, can be reduced by lowering voltage and frequency.
Leakage current can be reduced by lowering voltage and
temperature. The other two items can be reduced by carefully designing the end-user's system.
12 = C
Half Carry Flag
I HC I C I T1 PNDA I T1 ENA I EXPND I BUSY I EXEN I GIE I
BitO
Bit7
The Half-Carry bit is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and RC (Reset
Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and RC instructions, ADC,
SUBC, RRC and RLC instructions affect the carry and Half
Carry flags.
xVxf
where C = equivalent capacitance of the chip
V = operating voltage
f = CKI frequency
ICNTRl Register (Address X'OOES)
The ICNTRL register contains the following bits:
Some sample current drain values at Vee = 5Vare:
T1 ENB
CKI (MHz)
Inst. Cycle (,...s)
It (rnA)
10
3.58
2
0.3
o (HALT)
1
2.8
5
33
15
5.4
3
0.45
0.005
-
Timer T1 interrupt Enable for T1 B Input capture
edge
T1 PNDB Timer T1 Interrupt Pending Flag for T1 B capture edge
,...WEN
Enable MICROWIRE/PLUS interrupt
,...WPND MICROWIRE/PLUS interrupt pending
Control Registers
TOEN
Timer TO Interrupt Enable (Bit 12 toggle)
TOPND
Timer TO Interrupt pending
LPEN
L Port Interrupt Enable (Multi-Input Wakeup/Interrupt)
Bit 7 could be used as a flag
CNTRl Register (Address X'OOEE)
The Timer1 (T1) and MICROWIRE control register contains
the following bits:
SL1 & SLO Select the MICROWIRE clock divide by
(00 = 2, 01 = 4, 1 x = 8)
IEDG
External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
MSEL
Selects G5 and G4 as MICROWIRE signals
SK and SO respectively
T1CO
Timer T1 Start/Stop control in timer
modes 1 and 2
BitO
Bit7
T2CNTRl Register (Address X'OOCS)
The T2CNTRL register contains the following bits:
T2ENB
Timer T2 Interrupt Enable for T2B Input capture
edge
T2PNDB Timer T2 Interrupt Pending Flag for T2B capture edge
Timer T1 Underflow Interrupt Pending Flag in
timer mode 3
T2ENA
T1C1
Timer T1 mode control bit
T1C2
Timer T1 mode control bit
T1C3
Timer T1 mode control bit
T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA
in mode 1, T2 Underflow in mode 2, T2A capture edge in mode 3)
T2CO
I T1C31 T1C21 T1C1 I T1CO I MSEL IIEDG I SL1
Bit7
SLO
BitO
2-125
Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge
Timer T2 Start/Stop control in timer modes 1
and 2 Timer T2 Underflow Interrupt Pending
Flag in timer mode 3
CJ
oco
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co
serial fashion and the data from the external program memory is read back in a serial fashion. The Port D pins perform
the following functions.
Control Registers (Continued)
A.
o
o
T2C1
Timer T2 mode control bit
T2C2
Timer T2 mode control bit
T2C3
Timer T2 mode control bit
I
I
I
I
T2C3' T2C2' T2C1 , T2CO T2PNDA h2ENA T2PNDB T2ENB
Bit 7
I
DO
D1
Shifts in ROM data
Shifts out lower eight bits of PC
D2
Places the ,....C in the ROM less mode if grounded at
reset
Shifts out upper eight bits of PC
D3
BitO
T3CNTRL Register (Address X'OOB6)
D4
Data Shift Clock
The T3CNTRL register contains the following bits:
T3ENB . Timer T3 Interrupt Enable for T3B
D5
HALT Mask Option select pin
(D5 = 0) for HALT enable, D5 = 1 for HALT disable)
D6
D7
Load Clock
Shifts out recreated Port D data
T3PNDB Timer T3 Interrupt Pending Flag for T3B pin
(T3B capture edge)
T3ENA
The most significant bit of the data to come out on the D3
pin is a status Signal.. It is used by the MOLE development
system. This "lost" output port (DO-D7) can be accurately
reconstructed with external components as shown in Figure
6, providing an accurate emulation.
Timer T3 Interrupt Enable for Timer Underflow
or T3A pin
T3PNDA Timer T3 Interrupt Pending Flag (Autoload RA
in mode 1, T3 Underflow in mode 2, T3a capture edge in mode 3)
T3CO
Timer T3 Start/Stop control in timer modes 1
and 2
Timer T3 Underflow Interrupt Pending Flag in
timer mode 3
T3C1
Timer T3 mode control bit
T3C2
T3C3
Timer T3 mode control bit
Timer T3 mode control bit
I
I
I
I
The 44-pin and 40-pin versions of the COP888CG have a
full complement of the D Port pins and can be used in the
ROM less mode. However, it should be noted that the 44-pin
device can only emUlate itself and not the 40-pin or 28-pin
devices as it has only 6 Port L pins while the other two
devices have a full complement of Port L pins.
The 28-pin part cannot be used for emulation since it does
not have the full complement of 8 D Port pins necessary for
entering the ROM less mode.
I
Note that in the ROM less mode the D Port is recreated one
full clock cycle behind the normal port timings.
T3C3' T3C2' T3C1 , T3CO T3PNDA T3ENA T3PNDB T3ENBJ
Bit7
Bit 0
Note: Standard parts used in the ROM less mode will operate only at a
reduced frequency (to be defined).
Emulation and ROMless Modes
The COP888CG device has a spare D pin (D5) in the emulation mode since only seven pins are required for emulation
and recreation. This pin D5 is used in the emulation mode to
enable or disable the HALT mask option feature.
The COP888CG can address up to 32 kbytes of address
space. If at power up, D2 is held at ground, the COP888CG
executes from external memory. Port D is used to interface
to external program memory. The address comes out in a
Figure 7 shows the COP888CG Emulation Mode Schematic.
2-126
01~~
02""'--'
m
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3
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14
16
17
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SCLOCK
04 SCLOCK
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8 CK
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C4
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~
10
11
OG 12
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--
C2
ODS
OOS
004
003
002
001
000
OA 3
OB 4
OC
3
4
5
6
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03 16
04 15
3:
CD
en
en
3:
0
a.
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en
01~
02~
05:j
06 12
07
~
a
ENT
0
~ ENP
~A
LO
~B
~C
L1
~O
9 -
L2
SClOCK2 ~
XlO 1 Cl
COP888CG
l4
06 XlO
-~
1
L5
~
L6
OH~
L7
SCLOCK 8 CK
CL
~ B
~ A
GO
--¥
Gl
G2
G4
G5
01 PCl
12
11
10
6
5
4
3
I
S~OCK --¥ ~JLJ
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G6
OH~
G7
CKl
8
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~
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BPI
-
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VRIT
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03
04
05
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11 III
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07 OOATA
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10
aD 6
ac~
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PO
PI
P2
P3
P4
P5
P6
PCL
P8
P9
Pl0
Pl1
~
-
2
~
AO
00
01
02
D3
9
10
11
13
OATAO
OATAl
OATA2
OATA3
~
04:~
~~~~~
16
07 17
OATA6
OATA7
~
.fG~CE OE
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06
11 III
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CD
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RCO ~
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3 01
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23 ~~
22 A9
19 Al0
21 All
1:.# VCC
a
OA 14
OB 13
QO 19
01
a2
03
04
18
17
16
15
05:j
06 12
07
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LAn
~~~
LAT4
LAT5
LAT6
LAT7
'---t ~
3 01
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yri--
02
15 ~
14 os
13 06
12 07
wfL,.
t~
18 20
aA~
AGNO
TUDD/9765-13
FIGURE 7. COP888CG Emulation Mode Schematic
~~999dO~
iii
Power Save Modes
The COP888CG offers the user two power save modes of
operation: HALT and IDLE. In the HALT mode, all microcontroller activities are stopped. In the IDLE mode, the onboard oscillator circuitry and timer TO are active but all other
microcontroller activities are stopped. In either mode, all onboard RAM, registers, 1/0 states, and timers (with the exception of TO) are unaltered.
during HALT mode in order to ensure a clock monitor error if
the COP888CG inadvertently enters the HALT mode as a
result of a runaway program or power glitch.
IDLE MODE
The COP888CG is placed in the IDLE mode by writing a "1"
to the IDLE flag (G6 data bit). In this mode, all activity, except the associated on-board oscillator circuitry, the WatchDog logic, the clock monitor and the IDLE Timer TO, is
stopped. The power supply requirements of the microcontroller in this mode of operation are typically around 30% of
normal power requirement of the microcontroller.
As with the HALT mode, the COP888CG can be returned to
normal operation with a RESET, or with a Multi-Input Wakeup from the L Port. Alternately, the microcontroller resumes
normal operation from the IDLE mode when the twelfth bit
(representing 4.096 ms at internal clock frequency of 1 MHz
(te = 1 }.Ls» of the IDLE Timer toggles.
HALT MODE
The COP888CG is placed in the HALT mode by writing a
"1" to the HALT flag (G7 data bit). All microcontroller activities, including the clock and timers, are stopped. The
WatchDog logiC on the COP888CG is disabled during the
HALT mode. However, the clock monitor circuitry remains
active. In the HALT mode, the power requirements of the
COP888CG are minimal and the applied voltage (Vee> may
be decreased to Vr (Vr = 2.0V) without altering the state of
the machine.
The COP888CG supports three different ways of exiting the
HALT mode. The first method of exiting the HALT mode is
with the Multi-Input Wakeup feature on the L port. The second method is with a low to high transition on the CKO (G7)
pin. This method preludes the use of the crystal clock configuration (since CKO becomes a dedicated output), and so
may be used with an RC clock configuration. The third
method of exiting the HALT mode is by pulling the RESET
input low.
This toggle condition of the twelfth bit of the IDLE Timer TO
is latched into the TOPND pending flag.
The user has the option of being interrupted with a transition
on the twelfth bit of the IDLE Timer TO. The interrupt can be
enabled or disabled via the TOEN control bit. Setting the
TOEN flag enables the interrupt and vice versa.
The user can enter the IDLE mode with the Timer TO interrupt enabled. In this case, when the TOPND bit gets set, the
COP888CG will first execute the Timer TO interrupt service
routine and then return to the instruction following the "Enter Idle Mode" instruction.
Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full amplitude and frequency stability. The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution. In this case,
upon detecting a valid Wakeup signal, only the oscillator
circuitry is enabled. The IDLE timer is loaded with a value of
256 and is clocked with the te instruction cycle clock. The te
clock is derived by dividing the oscillator clock down by a
factor of 10. The Schmitt trigger following the CKI inverter
on the chip ensures that the IDLE time is clocked only when
the oscillator has a sufficiently large amplitude to meet the
Schmitt trigger specifications. This Schmitt trigger is not part
of the oscillator closed loop. The startup timeout from the
IDLE timer enables the clock signals to be routed to the rest
of the chip.
Alternatively, the user can enter the IDLE mode with the
IDLE Timer TO interrupt disabled. In this case, the
COP888CG will resume normal operation with the instruction immediately following the "Enter IDLE Mode" instruction.
Timers
The COP888CG contains a very versatile set of timers (TO,
T1, T2). All timers and associated autoreloadl capture registers power up containing random data.
TIMER TO (IDLE TIMER)
The COP888CG supports applications that require maintaining real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer TO, which is a
16-bit timer. The Timer TO runs continuously at the fixed
rate of the instruction cycle clock, te. The user cannot read
or write to the IDLE Timer TO, which is a count down timer.
If an RC clock option is being used, the fixed delay is introduced optionally. A control bit, CLKDLY, mapped as configuration bit G7, controls whether the delay is to be introduced or not. The delay is included if CLKDLY is set, and
excluded if CLKDLY is reset. The CLKDLY bit is cleared at
reset.
The Timer TO supports the following functions:
Exit out of the Idle Mode (See Idle Mode description)
WatchDog logic (See WatchDog description)
Start up delay out of the HALT mode
The COP88CG has two mask options associated with the
HALT mode. The first mask option enables the HALT mode
feature, while the second mask option disables the HALT
mode. With the HALT mode enable mask option, the
COP888CG will enter and exit the HALT mode as described
above. With the HALT disable mask option, the COP888CG
cannot be placed in the HALT mode (writing a "1" to the
HALT flag will have no effect).
The IDLE Timer TO can generate an interrupt when the
twelfth bit toggles. This toggle is latched into the TOPND
pending flag, and will occur every 4 ms at the maximum
clock frequency (te = 1 }.Ls). A control flag TOEN allows the
interrupt from the twelfth bit of Timer TO to be enabled or
disabled. Setting TOEN will enable the interrupt, while resetting it will disable the interrupt.
The WatchDog detector circuit is inhibited during the HALT
mode. However, the clock monitor circuit remains active
2-128
o
Timers
o
(Continued)
"tJ
the register RxA. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register RxB.
TIMER T1, TIMER T2 AND TIMER T3
The COP888CG has a set of two powerful timer/counter
blocks, T1, T2 and T3. The associated features and functioning of a timer block are described by referring to the
timer block Tx. Since the three timer blocks, T1, T2 and T3
are identical, all comments are equally applicable to either
timer block.
o
G)
The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
timer for PWM mode operation.
Figure 8 shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the TxA output pin. The underflows can also be programmed to generate interrupts.
Underflows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending flags under software control. Two control enable flags, TxENA and TxENB, allow the interrupts from the
timer underflow to be enabled or disabled. Setting the timer
enable flag TxENA will cause an interrupt when a timer underflow causes the RxA register to be reloaded into the timer. Setting the timer enable flag TxENB will cause an interrupt when a timer underflow causes the RxB register to be
reloaded into the timer. Resetting the timer enable flags will
disable the associated interrupts.
Each timer block consists of a 16-bit timer, Tx, and two
supporting 16-bit autoreload/capture registers, RxA and
RxB. Each timer block has two pins associated with it, TxA
and TxB. The pin TxA supports I/O required by the timer
block, while the pin TxB is an input to the timer block. The
powerful and flexible timer block allows the COP888CG to
easily perform all timer functions with minimal software
overhead. The timer block has three operating modes: Processor Independent PWM mode, External Event Counter
mode, and Input Capture mode.
The control bits TxC3, TxC2, and TxC1 allow selection of
the different modes of operation.
Mode 1. Processor Independent PWM Mode
Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting once
per PWM period on either the rising or falling edge of the
PWM output. Alternatively, the user may choose to interrupt
on both edges of the PWM output.
As the name suggests, this mode allows the COP888CG to
generate a PWM signal with very minimal user intervention.
The user only has to define the parameters of the PWM
signal (ON time and OFF time). Once begun, the timer block
will continuously generate the PWM signal completely independent of the microcontroller. The user software services
the timer block only when the PWM parameters require updating.
Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that
the timer, Tx, is clocked by the input signal from the TxA pin.
The Tx timer control bits, TxC3, TxC2 and TxC1 allow the
timer to be clocked either on a positive or negative edge
from the TxA pin. Underflows from the timer are latched into
the TxPNDA pending flag. Setting the TxENA control flag
will cause an interrupt when the timer underflows.
In this mode the timer Tx counts down at a fixed rate of te.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, RxA and RxB. The very
first underflow of the timer causes the timer to reload from
TIMER
UNDERrLOW
INTERRUPT
Q)
Q)
Q)
•
+-----,
TxA
tC------....a
TLlDD/9765-14
FIGURE 8. Timer in PWM Mode
2-129
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o
Timers
(Continued)
Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer TxCO
pending flag (the TxCO control bit serves as the timer underflow interrupt pending flag in the Input Capture mode). Consequently, the TxCO control bit should be reset when enter~
ing the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
the TxPNDA and TxCO pending flags in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.
In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB
control flag is set. The occurrence of a positive edge on the
TxB input pin is latched into the TxPNDB flag.
Figure,9 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is
being used as the counter input clock.
Mode 3. Input Capture Mode
The COP888CG can precisely measure external frequencies or time external events by placing the timer block, Tx, in
the input capture mode.
Figure 10 shows a block diagram of the timer in Input Capture mode.
In this mode, the timer Tx is constantly running at the fixed
tc rate. The two registers, RxA and RxB, act as capture
registers. Each register acts in conjunction with a pin. The
register RxA acts in conjunction with the TxA pin and the
register RxB acts in conjunction with the TxB pin.
The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin. Control bits,
TxC3, TxC2 and TxC1, allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for each input pin can be specified independently.
TIMER CONTROL FLAGS
The timers T1, T2 and T3 have indentical control structures.
The control bits and their functions are summarized below.
TxCO
TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag
The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag
TxENA allows the interrupt on TxA to be either enabled or
disabled. Setting the TxENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts
from the TxB pin.
TIMER
UNDERFLOW
INTERRUPT
Timer Start/Stop control in Modes 1 and 2
(Processor Independent PWM and External
Event Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)
TxENA
TxENB
Timer Interrupt Enable Flag
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
o = Timer Interrupt Disabled
TxC3
TxC2
TxC1
Timer mode control
Timer mode control
Timer mode control
te
+ - - - -......
TxA
TL/DD/9765-15
TLlDD/9765-16
FIGURE 9. Timer In External Event Counter Mode
FIGURE 10. Timer In Input Capture Mode
2-130
(")
Timers
o
-a
(Continued)
(X)
(X)
(X)
The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:
Interrupt A
Source
Interrupt B
Source
Timer
Counts On
MODE 2 (External
Event Counter)
Timer
Underflow
Pos. TxB
Edge
TxA
Pos. Edge
1
MODE 2 (External
Event Counter)
Timer
Underflow
Pos. TxB
Edge
TxA
Neg. Edge
0
1
MODE 1 (PWM)
TxA Toggle
Autoreload
RA
Autoreload
RB
1
0
0
MODE 1 (PWM)
No TxA Toggle
Autoreload
RA
Autoreload
RB
0
1
0
MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Pos. Edge
Pos. TxA
Edge or
Timer
Underflow
Pos. TxB
Edge
1
1
0
MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Neg. Edge
Pos. TxA
Edge or
Timer
Underflow
Neg. TxB
Edge
0
1
1
MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Pos. Edge
Neg.TxB
Edge or
Timer
Underflow
Pos. TxB
Edge
1
1
1
MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Neg. Edge
Neg. TxA
Edge or
Timer
Underflow
Neg. TxB
Edge
TxC3
TxC2
TxC1
Timer Mode
0
0
0
0
0
1
(")
Ci)
Detection of Illegal Conditions
The COP888CG will detect various illegal conditions resulting from coding errors, transient noise, power supply voltage drops, runaway programs, etc.
Thus, the chip can detect the following illegal conditions:
a. Executing from undefined ROM
b. Over "POP"ing the stack by having more returns than
calls.
When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before restarting (this recovery program is probably similar to that
following RESET, but might not contain the same program
initialization procedures).
Reading of undefined ROM gets zeros. The opcode for software interrupt is zero. If the program fetches instructions
from undefined ROM, this will force a software interrupt,
thus signaling that an illegal condition has occurred.
The subroutine stack grows down for each call (jump to
subroutine), interrupt, or PUSH, and grows up for each return or POP. The stack pointer is initialized to RAM location
06F Hex during RESET. Consequently, if there are more
returns than calls, the stack pointer will point to addresses
070 and 071 Hex (which are undefined RAM). Undefined
RAM from addresses 070 to 07F (Segment 0), 140 to 17F
(Segment 1), and all other segments (Le., Segments 3 ...
etc.) is read as all 1's, which in turn will cause the program
to return to address FFFF Hex. This is an undefined ROM
location and the instruction fetched (all O's) from this location will generate a software interrupt signaling an illegal
condition.
Multi-Input Wakeup
The Multi-Input Wakeup feature is used to return (wakeup)
the COP888CG from either the HALT or IDLE modes. Alternately Multi-Input Wakeup/Interrupt feature may also be
used to generate up to 8 edge selectable external interrupts.
2-131
•
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Multi-Input Wakeup
a.
o
(Continued)
INTERNAL DATA BUS
o
CKI
CKO
LO
L7
TO INTERRUPT LOGIC
CHIP CLOCK
TL/DD/9765-17
FIGURE 11. Multi-Input Wake Up Logic
Figure 11 shows the Multi·lnput Wakeup logic for the
COP888CG microcontroller.
If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wakeup/Interrupt, a safety procedure should also be followed to avoid inherited
pseudo wakeup conditions. After the selected L port bits
have been changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired
edge selects, followed by the associated WKPND bits being
cleared.
The Multi-Input Wakeup feature utilizes the L Port. The user
selects which particular L port bit (or combination of L Port
bits) will cause the COP888CG to exit the HALT or IDLE
modes. The selection is done through the Reg: WKEN. The
Reg: WKEN is an 8-bit read/write register, which contains a
control bit for every L port bit. Setting a particular WKEN bit
enables a Wakeup from the associated L port pin.
This same procedure should be used following RESET,
since the L port inputs are left floating as a result of RESET.
The user can select whether the trigger condition on the
selected L Port pin is going to be either a positive edge (low
to high transition) or a negative edge (high to low transition).
This selection is made via the Reg: WKEDG, which is an 8bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a
pseudo Wakeup condition as a result of the edge change.
First, the associated WKEN bit should be reset, followed by
the edge select change in WKEDG. Next, the associated
WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.
The occurrence of the selected trigger condition for Multi-Input Wakeup is latched into a pending register called Reg:
WKPND. The respective bits of the WKPND register will be
set on the occurrence of the selected trigger edge on the
corresponding Port L pin. The user has the responsibility of
clearing these pending flags. Since the Reg: WKPND is a
pending register for the occurrence of selected wakeup
conditions, the COP888CG will not enter the HALT mode if
any Wakeup bit is both enabled and pending. Consequently,
the user has the responsibility of clearing the pending flags
before attempting to enter the HALT mode.
All three registers Reg:WKEN, Reg:WKPND and
Reg:WKEDG are read/write registers, and are cleared at
reset.
An example may serve to clarify this procedure. Suppose
we wish to change the edge select from positive (low going
high) to negative (high going low) for L Port bit 5, where bit 5
has previously been enabled for an input interrupt. The program would be as follows:
RBn
SBn
RBlT
SBlT
5,
5,
5,
5,
PORT L INTERRUPTS
Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into
the same service subroutine.
WKEN
WKEDG
WKPND
WKEN
The interrupt from Port L shares logic with the wake up circuitry. The register WKEN allows interrupts from Port L to
be individually enabled or disabled. The register WKEDG
2-132
o
Multi-Input Wakeup
o"'0
(Continued)
specifies the trigger condition to be either a positive or a
negative edge. Finally, the register WKPND latches in the
pending trigger conditions.
tion bit allows the clock start up delay to be optionally inserted. Setting CLKDLY flag high will cause clock start up delay
to be inserted and resetting it will exclude the clock start up
delay. The CLKDL Y flag is cleared during RESET, so the
clock start up delay is not present following RESET with the
RC clock options.
A control flag, LPEN, functions as a global interrupt enable
for Port L interrupts. Setting the LPEN flag will enable interrupts and vice versa. A separate global pending flag is not
needed since the register WKPND is adequate.
UART
Since Port L is also used for waking the COP888CG out of
the HALT or IDLE modes, the user can elect to exit the
HALT or IDLE modes either with or without the interrupt
enabled. If he elects to disable the interrupt, then the
COP888CG will restart execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or IDLE modes. In the other case, the
COP888CG will first execute the interrupt service routine
and then revert to normal operation.
The COP888CG contains a full-duplex software programmable UART. The UART (Figure 12) consists of a transmit
shift register, a receiver shift register and seven addressable registers, as follows: a transmit buffer register (TBUF),
a receiver buffer register (RBUF), a UART control and
status register (ENU), a UART receive control and status
register (ENUR), a UART interrupt and clock source register
(ENUI), a prescaler select register (PSR) and baud (BAUD)
register. The ENU register contains flags for transmit and
receive functions; this register also determines the length of
the data frame (7, 8 or 9 bits), the value of the ninth bit in
transmission, and parity selection bits. The ENUR register
flags framming, data overrun and parity errors while the
UART is receiving.
The Wakeup signal will not start the chip running immediately since crystal oscillators or ceramic resonators have a finite start up time. The IDLE Timer (TO) generates a fixed
delay to ensure that the oscillator has indeed stabilized before allowing the COP888CG to execute instructions. In this
case, upon detecting a valid Wakeup signal, only the oscillator circuitry and the IDLE Timer TO are enabled. The IDLE
Timer is loaded with a value of 256 and is clocked from the
tc instruction cycle clock. The tc clock is derived by dividing
down the oscillator clock by a factor of 10. A Schmitt trigger
following the CKI on-chip inverter ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large
amplitude to meet the Schmitt trigger specifications. This
Schmitt trigger is not part of the oscillator closed loop. The
startup timeout from the IDLE timer enables the clock signals to be routed to the rest of the chip.
Other functions of the ENUR register include saving the
ninth bit received in the data frame, enabling or disabling the
UART's attention mode of operation and providing additional receiver/transmitter status information via RCVG and
XMTG bits. The determination of an internal or external
clock source is done by the ENUI register, as well as selecting the number of stop bits and enabling or disabling transmit and receive interrupts. A control flag in this register can
also select the UART mode of operation: asynchronous or
synchronous.
If the RC clock option is used, the fixed delay is under software control. A control flag, CLKDLY, in the G7 configura-
RXO
[Il
E
DOE
FE
I
N 1+----1
T
~
______~
1 - - - - - + INTERRUPT
____~~
1 - - - - - + INTERRUPT
E
R 1+-_ _'-
N
~
A
L
TXO
o
A
T
A ...----~
XMIT RECV
CLOCK CLOCK
CKX
CRYSTAL
FIGURE 12. UART Block Diagram
2-133
TL/DD/9765-18
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D.
UART CONTROL AND STATUS REGISTERS
o
The operation of the UART is programmed through three
registers: ENU, ENUR and ENUI. The function of the individual bits in these registers is as follows:
o
ASYNCHRONOUS MODE
This mode is selected by resetting the SSEL (in the ENUI
register) bit to zero. The input frequency to the UART is 16
times the baud rate.
UART (Continued)
The TSFT and TBUF registers double-buffer data for transmission. While TSFT is shifting out the current character on
the TDX pin, the TBUF register may be loaded by software
with the next byte to be transmitted. When TSFT finishes
transmitting the current character the contents of TBUF are
transferred to the TSFT register and the Transmit Buffer
Empty Flag (TBMT in the ENU register) is set. The TBMT
flag is automatically reset by the UART when software loads
a new character into the TBUF register. There is also the
XMTG bit which is set to indicate that the UART is transmitting. This bit gets reset at the end of the last frame (end of
last Stop bit). TBUF is a read/write register.
Control and Status Register (Byte at OBA)
PEN
ORW
PSEL1 XBIT9/ CHL1
PSELO
ORW ORW ORW
CHLO
ERR
RBFL TBMT
ORW
OR
OR
Bit7
1R
BitO
ENUR-UART Receive Control and Status Register
(Byte at OBB)
B~
The RSFT and RBUF registers double-buffer data being received. The UART receiver continually monitors the signal
on the RDX pin for a low level to detect the beginning of a
Start bit. Upon sensing this low level, it waits for half a bit
time and samples again. If the RDX pin is still low, the receiver considers this to be a valid Start bit, and the remaining bits in the character frame are each sampled a single
time, at the mid-bit position. Serial data input on the RDX pin
is shifted into the RSFT register. Upon receiving the complete character, the contents of the RSFT register are copied into the RBUF register and the Received Buffer Full Flag
(RBFL) is set. RBFL is automatically reset when software
reads the character from the RBUF register. RBUF is a read
only register. There is also the RCVG bit which is set high
when a framing error occurs and goes low once RDX goes
high. TBMT, XMTG, RBFL and RCVG are read only bits.
B~
ENUI-UART Interrupt and Clock Source Register
(Byte at aBC)
B~
B~
·Bit is not used.
Bit is cleared on reset.
1
Bit is set to one on reset.
R
Bit is read-only; it cannot be written by software.
RW Bit is read/write.
o
Bit is cleared on read; when read by software as a one, it is cleared
automatically. Writing to the bit does not affect its state.
SYNCHRONOUS MODE
Associated 1/0 Pins
In this mode data is transferred synchronously with the
clock. Data is transmitted on the rising edge and received
on the falling edge of the synchronous clock.
Data is transmitted on the TDX pin and received on the RDX
pin. TDX is the alternate function assigned to Port L pin L2;
it is selected by setting ETDX (in the ENUR register) to one.
RDX is an inherent function of Port L pin L3, requiring no
setup.
This mode is selected by setting SSEL bit in the ENUI register. The input frequency to the UART is the same as the
baud rate.
When an external clock input is selected at the CKX pin,
data transmit and receive are performed synchronously with
this clock through TDX/RDX pins.
The baud rate clock for the UART can be generated onchip, or can be taken from an external source. Port L pin L1
(CKX) is the external clock I/O pin. The CKX pin can be
either an input or an output, as determined by Port L Configuration and Data registers (Bit 1). As an input, it accepts a
clock signal which may be selected to drive the transmitter
and/or receiver. As an output, it presents the internal Baud
Rate Generator output.
If data transmit and receive are selected with the CKX pin
as clock output, the p.C generates the synchronous clock
output at the CKX pin. The internal baud rate generator is
used to produce the synchronous clock. Data transmit and
receive are performed synchronously with this clock.
FRAMING FORMATS
UART OPERATION
The UART supports several serial framing formats (Figure
13). The format is selected using control bits in the ENU
register.
The UART has two modes of operation: asynchronous
mode and synchronous mode.
2-134
0
UART OPERATION
111
lb
Ie
211
2b
2e
311
---,
---,
---,
---,
---,
---,
---,
---,
---,
---,
0
(Continued)
"'D
START
BIT
7 BIT DATA
START
BIT
7 BIT DATA
START
BIT
7 BIT DATA
PA
START
BIT
7 BIT DATA
PA
START
BIT
8 BIT DATA
START
BIT
8 BIT DATA
START
BIT
8 BIT DATA
PA
START
BIT
8 BIT DATA
PA
START
BIT
9 BIT DATA
START
BIT
9 BIT DATA
Q)
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I L
S
0
G)
L
L
2S
S
L
2S
L
S
2S
S
L
L
L
2S
S
L
L
2S
TLlDD/9765-19
FIGURE 13. Framing Formats
Baud Clock Generation
The clock inputs to the transmitter and receiver sections of
the UART can be individually selected to come either from
an external source at the CKX pin (port L, pin L1) or from a
source selected in the PSR and BAD registers. Internally,
the basic baud clock is created from the oscillator frequency
through a two-stage divider chain consisting of a 1-16 (increments of 0.5) prescaler and an 11-bit binary counter.
(Figure 14) The divide factors are specified through two
read/write registers shown in Figure 15. Note that the 11-bit
Baud Rate Divisor spills over into the Prescaler Select Register (PSR). PSR is cleared upon reset.
purpose. The user must also turn the UART clock off when
a different baud rate is chosen.
The correspondences between the 5-bit Prescaler Select
and Prescaler factors are shown in Table I. Therer are many
ways to calculate the two divisor factors, but one particularly
effective method would be to achieve a 1.8432 MHz frequency coming out of the first stage. The 1.8432 MHz prescaler output is then used to drive the software programmable baud rate counter to create a x16 clock for the following
baud rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400,
3600, 4800, 7200, 9600, 19200 and 38400 (Table II). Other
baud rates may be created by using appropriate divisors.
The x16 clock is then divided by 16 to provide the rate for
the serial shift registers of the transmitter and receiver.
As shown in Table I, a Prescale Factor of 0 corresponds to
NO CLOCK. NO CLOCK condition is the UART power down
mode where the UART clock is turned off for power saving
UART TRANSIoAIT
CLOCK
IoAUX
+16
PRESCALER
5 BITS
+1 TO +16
BAUD RATE
SELECT 11 BITS
110-19,200 BAUD
14
CRYSTAL
UART RECEIVE
CLOCK
TLlDD/9765-20
FIGURE 14. UART BAUD Clock Generation
r--
PSR
PRESCALE REGISTER
14131211
~ PRESCALE
~ SELECT
I
0 1
10
I
BAUD REGISTER
-1
191817161514131211
I
BAUD RATE DIVISOR
II
0
I
TL/DD/9765-21
FIGURE 15. UART BAUD Clock Divisor Registers
2-135
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Baud Clock Generation
(Continued)
As an example, considering the Asynchronous Mode and a
CKI clock of 4.608 MHz, the prescaler factor selected is:
TABLE I. Prescaler Factors
Prescaler
Select
Prescaler
Factor
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
NO CLOCK
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
15
15.5
16
4.608/1.8432 = 2.5
The 2.5 entry is available in Table I. The 1.8432 MHz prescaler output is then used with proper Baud Rate Divisor
(Table II) to obtain different baud rates. For a baud rate of
19200 e.g., the entry in Table II is 5.
N - 1 = 5 (N - 1 is the contents of Baud Rate Divisor)
N = 6 (N is the divisor)
Baud Rate = 1.8432 MHz (16
x 6)
= 19200
The divide by 16 is performed because in the asynchronous
mode, the input frequency to the UART is 16 times the baud
rate. The equation to calculate baud rates is given below.
The actual Baud Rate may be found from:
BR
=
Fc/(16
x
N
x
P)
Where:
BR is the Baud Rate
Fc is the CKI frequency
N is one plus the value of the Baud Rate Divisor (Table III).
P is the Prescaler Divide Factor selected by the value in the
Prescaler Select Register (Table I)
Note: In the Synchronous Mode, the divisor 16 Is replaced by one.
Example:
Asynchronous Mode:
Crystal Frequency = 5 MHz
Desired baud rate = 9600
Using the above equation N x P can be calculated first.
N x P =(5 x 106)/(16 x 9600)
Now 32.552 is divided by each Prescaler Factor (Table II) to
obtain a value closest to an integer. This factor happens to
be 6.5 (P = 6.5).
N = 32.552/6.5 = 5.008 (N = 5)
The Baud Rate Divisor value should be 4 (N - 1).
Using the above values calculated for Nand P:
BR = (5 x 10 6)/(16 x 5 x 6.5) = 9615.384
% error = (9615.385 - 9600)/9600 = 0.16
TABLE II. Baud Rate Divisors
(1.8432 MHz Prescaler Output)
Baud
Rate
Baud Rate
Divisor (N-1)
110 (110.03)
134.5 (134.58)
150
300
600
1200
1800
2400
3600
4800
7200
9600
19200
38400
1046
855
767
383
191
95
63
47
31
23
15
11
5
2
Attention Mode
The UART Receiver section supports an alternate mode of
operation, referred to as ATTENTION Mode. This mode of
operation is selected by the ATTN bit in the ENUR register.
The data format for transmission must also be selected as
having nine Data bits and either 7/8, one or two Stop bits.
The ATTENTION mode of operation is intended for use in
networking the COP888CG with other processors. Typically
in such environments the messages consists of device addresses, indicating which of several destinations should receive them, and the actual data. This Mode supports a
scheme in which addresses are flagged by having the ninth
bit of the data field set to a 1. If the ninth bit is reset to a
zero the byte is a Data byte.
While in ATTENTION mode, the UART monitors the communication flow, but ignores all characters until an address
character is received. Upon receiving an address character,
the UART signals that the character is ready by setting the
RBFL flag, which in turn interrupts the processor if UART
The entries in Table II assume a prescaler output
of 1.B432 MHz.
2-136
Attention Mode
CMP20E Enables comparator2 output to pin 16 ("1" =
enable), CMP2EN bit must be set to enable
this function.
(Continued)
Receiver interrupts are enabled. The ATIN bit is also
cleared automatically at this point, so that data characters
as well as address characters are recognized. Software examines the contents of the RBUF and responds by deciding
either to accept the subsequent data stream (by leaving the
ATIN bit reset) or to wait until the next address character is
seen (by setting the ATIN bit again).
l
unused l
II
eMP
2RD
eMP
2EN
eMP
10E
-II eMP
1RD
I I
eMP
1EN
~7
J
unusedl
~o
Comparator outputs have the save spec as Ports Land G
except that the rise and fall times are symmetrical.
Interrupts
Comparators
The COP888CG supports a vectored interrupt scheme. It
supports a total of fourteen interrupt sources. The following
table lists all the possible COP888CG interrupt sources,
their arbitration ranking and the memory locations reserved
for the interrupt vector for each source.
The COP888CG has two differential comparators. Ports 1113 and 14-16 are used for the comparators. The output of the
comparators are brought out to the pins. The following is the
Port I assignment.
Comparator1
Comparator1
Comparator1
Comparator2
Comparator2
Comparator2
1 11
The Comparator Select Register is cleared on RESET (the
comparators are disabled). To save power the program
should also disable the comparators before the JJ.C enters
the HALTIIDLE modes.
Operation of the UART Transmitter is not affected by selection of this Mode. The value of the ninth bit to be transmitted
is programmed by setting XBIT9 appropriately. The value of
the ninth bit received is obtained by reading RBIT9. Since
this bit is located in ENUR register where the error flags
reside, a bit operation on it will reset the error flags.
11
12
13
14
15
16
eMP
20E
Two bytes of program memory space are reserved for each
interrupt source. All interrupt sources except the software
interrupt are maskable. Each of the maskable interrupts
have an Enable bit and a Pending bit. A maskable interrupt
is active if its associated enable and pending bits are set. If
GIE = 1 and an interrupt is active, then the processor will
be interrupted as soon as it is ready to start executing an
instruction except if the above conditions happen during the
Software Trap service routine. This exception is described
in the Software Trap sub-section.
negative input
positive input
output
negative input
positive input
output
COMPARATOR SELECT REGISTER (ADDRESS X'OOB7)
The register contains the following bits:
CMP1 EN Enables comparator1 ("1" = enable)
The interruption process is accomplished with the INTR instruction (opcode 00), which is jammed inside the Instruction Register and replaces the opcode about to be executed. The following steps are performed for every interrupt:
CMP1 RD Reads comparator1 output internally
(CMP1 EN = 1, CMP10E = 0)
CMP10E Enables comparator1 output to pin 13 ("1" =
enable), CMP1 EN bit must be set to enable
this function.
1. The GIE (Global Interrupt Enable) bit is reset.
2. The address of the instruction about to be executed is
pushed into the stack.
CMP2EN Enables comparator2 ("1" = enable)
CMP2RD Reads comparator2 output internally
(CMP2EN = 1, CMP20E = 0)
3. The PC (Program Counter) branches to address OOFF.
This procedure takes 7 tc cycles to execute.
2-137
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Interrupts (Continued)
Arbitration
Ranking
(1) Highest
Source
Description
Vector
Address
Hi-Low Byte
Software
INTR Instruction
OyFE-OyFF
Reserved
for Future Use
OyFC-OyFD
(2)
External
Pin GO Edge
OyFA-OyFB
(3)
Timer TO
TO Bit 12 Toggle
OyFB-OyF9
(4)
TimerT1
T1 Underflowl
T1 A Capture Edge
OyF6-0yF7
(5)
TimerT1
T1 B Capture Edge
OyF4-0yF5
(6)
MICROWIRE/PLUS
BUSY Goes Low
OyF2-0yF3
Reserved
for Future Use
OyFO-OyF1
UART
Receive
OyEE-OyEF
UART
Transmit
OyEC-OyED
(7)
TimerT2
T2 Underflowl
T2A Capture Edge
OyEA-OyEB
(8)
TimerT2
T2B Capture Edge
OyEB-OyE9
Reserved
for Future Use
OyE6-0yE7
Reserved
for Future Use
OyE4-0yE5
(9)
Port LlWakeup
Port LEdge
OyE2-0yE3
(10) Lowest
Default
VIS Instr. Execution
without Any Interrupts
OyEO-OyE1
Y is VIS page.
At this time, since GIE = 0, other maskable interrupts are
disabled. The user is now free to do whatever context
switching is required by saving the context of the machine in
the stack with PUSH instructions. The user would then program a VIS (Vector Interrupt Select) instruction in order to
branch to the interrupt service routine of the highest priority
interrupt enabled and pending at the time of the VIS. Note
that this is not necessarily the interrupt that caused the
branch to address location OOFF Hex prior to the context
switching.
The VIS instruction looks at all the active interrupts at the
time it is executed and performs an indirect jump to the
beginning of the service routine of the one with the highest
rank.
The addresses of the different interrupt service routines,
called vectors, are chosen by the user and stored in ROM in
a table starting at 01 EO (assuming that VIS is located between OOFF and 01 DF). The vectors are 15-bit wide and
therefore occupy 2 ROM locations.
VIS and the vector table must be located in the same 256byte block (OyOO to OyFF) except if VIS is located at the last
address of a block. In this case, the table must be in the
next block.
Thus, if an interrupt with a higher rank than the one which
caused the interruption becomes active before the decision
of which interrupt to service is made by the VIS, then the
interrupt with the higher rank will override any lower ones
and will be acknowledged. The lower priority interrupt(s) are
still pending, however, and will cause another interrupt immediately following the completion of the interrupt service
routine associated with the higher priority interrupt just serviced. This lower priority interrupt will occur immediately following the RETI (Return from Interrupt) instruction at the
end of the interrupt service routine just completed.
The vector of the maskable interrupt with the lowest rank is
located at OyEO (Hi-Order byte) and OyE1 (Lo-Order byte)
and so forth in increasing rank number. The vector of the
maskable interrupt with the highest rank is located at OyFA
(Hi-Order byte) and OyFB (Lo-Order byte).
The Software Trap has the highest rank and its vector is
located at OyFE and OyFF.
If, by accident, a VIS gets executed and no interrupt is active, then the PC (Program Counter) will branch to a vector
located at OyEO-OyE1. This vector can point to the Software Trap (Sn interrupt service routine, or to another special service routine as desired.
Inside the interrupt service routine, the associated pending
bit has to be cleared by software. The RETI (Return from
Interrupt) instruction at the end of the interrupt service routine will set the GIE (Global Interrupt Enable) bit, allowing
the processor to be interrupted again if another interrupt is
active and pending.
Figure 16 shows the COP88BCG Interrupt block diagram.
2-138
o
The lower limit of the service window is fixed at 2048 instruction cycles. Bits 7 ad 6 of the WDCNT register allow
the user to pick an upper limit of the service window.
Interrupts (Continued)
SOFTWARE TRAP
The Software Trap (ST) is a special kind of non-maskable
interrupt which occurs when the INTR instruction (used to
acknowledge interrupts) is fetched from ROM and placed
inside the instruction register. This may happen when the
PC is pointing beyond the available ROM address space or
when the stack is over-popped.
Table IV shows the four possible combinations of lower and
upper limits for the WatchDog service window. This flexibility in choosing the WatchDog service window prevents any
undue burden on the user software.
Bits 5, 4, 3, 2 and 1 of the WDCNT register represent the 5bit Key Data field. The key data is fixed at 01100. Bit 0 of the
WDCNT Register is the Clock Monitor Select bit.
When an ST occurs, the user can re-initialize the stack
pointer and do a recovery procedure (similar to RESET, but
not necessarily containing all of the same initialization procedures) before restarting.
TABLE'"
Window
Select
The occurrence of an ST is latched into the ST pending bit.
The GIE bit is not affected and the ST pending bit (not
accessible by the user) is used to inhibit other interrupts
and to direct the program to the ST service routine with the
VIS instruction.
X
I
7
Clock
Monitor
Key Data
X
0
6
5
I1 I1 I0 I0
4
It is cleared by RESET and by the RPND instruction.
The ST has the highest rank among all interrupts.
y
o
2
3
TABLE IV
Nothing (except another ST) can Interrupt an ST being
serviced_
WDCNT
Blt7
WDCNT
Blt6
The COP888CG contains a WatchDog and clock monitor.
The WatchDog is designed to detect the user program getting stuck in infinite loops resulting in loss of program control or "runaway" programs. The Clock Monitor is used to
detect the absence of a clock or a very slow clock below a
specified rate on the CKI pin.
0
0
1
1
0
1
0
1
Service Window
(Lower-Upper LImits)
2k-8k te Cycles
2k-16k te Cycles
2k-32k te Cycles
2k-64k te Cycles
Clock Monitor
WatchDog
The Clock Monitor aboard the COP888CG can be selected
or deselected under program control. The Clock Monitor is
guaranteed not to reject the clock if the instruction cycle
clock (1 ltd is greater or equal to 10kHz. This equates to a
clock input rate on CKI of greater or equal to 100 kHz.
The COP888CG WatchDog consists of two independent
logic blocks: WD UPPER and WD LOWER. WD UPPER establishes the upper limit on the service window and WD
LOWER defines the lower limit of the service window.
Servicing the WatchDog consists of writing a specific value
to a WatchDog Service Register named WDCNT which is
memory mapped in the RAM. This value is composed of
three fields, consisting of a 2-bit Window Select, a 5-bit Key
Data field, and the 1-bit Clock Monitor Select field. Table III
shows the WDCNT register.
WatchDog Operation
The WatchDog and Clock Monitor are disabled during
RESET. The COP888CG comes out of RESET with the
WatchDog armed, the WatchDog Window Select bits (bits 6,
SOnwARE----------------------------~
TIt.lER T1 AND T2
EXTERNAL
WAKE UP
INTERRUPT
).LWIRE
PERIPHERALS
IDLE TIMER
TLl00/9765-22
FIGURE 16. COP888CG Interrupt Block Diagram
2-139
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WatchDog Operation (Continued)
7 of the WDCNT Register) set, and the Clock Monitor bit (bit
o of the WDCNT Register) enabled. Thus, a Clock Monitor
error will occur after coming out of RESET, if the instruction
cycle clock frequency has not reached a minimum specified
value, including the case where the oscillator fails to start.
The WDCNT register can be written to only once after
RESET and the key data (bits 5 through 1 of the WDCNT
Register) must match to be a valid write. This write to the
WDCNT register involves two irrevocable choices: (i) the
selection of the WatchDog service window (ii) enabling or
disabling of the Clock Monitor. Hence, the first write to
WDCNT· Register involves selecting or deselecting the
Clock Monitor, select the WatchDog service window and
match the WatchDog key data. Subsequent writes to the
WDCNT register will compare the value being written by the
user to the WatchDog service window value and the key
data (bits 7 through 1) in the WDCNT Register. Table V
shows the sequence of events that can occur.
The user must service the WatchDog at least once before
the upper limit of the serivce window expires. The WatchDog may not be serviced more than once in every lower
limit of the service window. The user may service the
WatchDog as many times as wished in the time period between the lower and upper limits of the service window. The
first write to the WDCNT Register is also counted as a
WatchDog service.
pedance TRI-STATE mode following 16 te-32 te clock cycles. The Clock Monitor generates a continual Clock Monitor error if the oscillator fails to start, or fails to reach the
minimum specified frequency. The specification for the
Clock Monitor is as follows:
1Ite > 10kHz-No clock rejection.
1/te < 10Hz-Guaranteed clock rejection.
MICROWIRE/PLUS
MICROWIRE/PlUS is a serial synchronous communications interface. The MICROWIRE/PlUS capability enables
the COP888CG to interface with any of National Semiconductor's MICROWIRE peripherals (I.e. AID converters, display drivers, E2PROMs etc.) and with other microcontrollers
which support the MICROWIRE interface. It consists of an
8-bit serial shift register (SIO) with serial data input (SI), serial data output (SO) and serial shift clock (SK). Figure 13
shows a block diagram of the MICROWIRE logic.
1-------+ INTERRUPT
~~----~~----------~SO
~-~~~~......- - - - S I
The WatchDog has an output pin associated with it. This is
the WDOUT pin, on pin 1 of the port G. WDOUT is active
low. The WDOUT pin is in the high impedance state in the
inactive state. Upon triggering the WatchDog, the logic will
pull the WDOUT (G1) pin low for an additional 16 te-32 te
cycles after the signal level on WDOUT pin goes below the
lower Schmitt trigger threshold. After this delay, the
COP888CG will stop forcing the WDOUT output low.
SK
TL/DD/9765-23
FIGURE 17_ MICROWIRE Block Diagram
The WatchDog service window will restart when the
WDOUT pin goes inactive. It is recommended that the user
tie the WDOUT pin back to Vee through a resistor in order
to pull WDOUT high.
A WatchDog service while the WDOUT signal is active will
be ignored. The state of the WDOUT pin is not guaranteed
at RESET, but if it powers up low then the WatchDog will
time out and disable.
The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIRE
arrangement with the internal clock source is called the
Master mode of operation. Similarly, operating the MICROWIRE arrangement with an external shift clock is called the
Slave mode of operation.
The CNTRl register is used to configure and control the
MICROWIRE mode. To use the MICROWIRE, the MSEl bit
in the CNTRl register is set to one. The SK clock rate is
selected by the two bits, SlO and Sl1, in the CNTRl register. Table IV details the different clock rates that may be
selected.
The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error. The Clock Monitor error will continue
until the clock frequency has reached the minimum specified value, after which the G1 output will enter the high im-
TABLE V
Key
Data
Window
Data
Clock
Monitor
Action
Match
Match
Match
Valid Service: Restart Service Window
Don't Care
Mismatch
Don't Care
Error: Generate WatchDog Output
Mismatch
Don't Care
Don't Care
Error: Generate WatchDog Output
Don't Care
Don't Care
Mismatch
Error: Generate WatchDog Output
TABLE VI
SL1
SLO
SK
0
0
1
x
2 x te
4 X te
8 x te
0
1
2-140
Where te is the
instruction cycle clock
o
o
MICROWIRE/PLUS (Continued)
."
MICROWIRE/PLUS OPERATION
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by
the Master will be shifted properly. After eight clock pulses
the BUSY flag will be cleared and the sequence may be
repeated.
Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than B bits to shift.
The COPBBBCG may enter the MICROWIRE/PLUS mode
either as a Master or as a Slave. Figure 14 shows how two
COPBBBCG microcontrollers and several peripherals may
be interconnected using the MICROWIRE/PLUS arrangements.
Alternate SK Phase Operation
The COP8BBCG allows either the normal SK clock or an
alternate phase SK clock to shift data in and out of the SIO
register. In both the modes the SK is normally low. In the
normal mode data is shifted in on the rising edge of the SK
clock and the data is shifted out on the falling edge of the
SK clock. The SIO register is shifted on each falling edge of
the SK clock in the normal mode. In the alternate SK phase
operation, data is shifted in on the falling edge of the SK
clock ahd shifted out on the rising edge of the SK clock. In
the alternate SK phase mode the SIO register is shifted on
the rising edge of the SK clock.
Warning:
The SIO register should only be loaded when the SK clock
is low. Loading the SIO register while the SK clock is high
will result in undefined data in the SIO register.
Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PLUS slave mode may cause the current SK
clock forthe SIO shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is
low.
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alternate SK clock. The SKSEL is mapped into the G6 configuration bit. The SKSEL flag will power up in the reset condition,
selecting the normal SK signal.
MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally by the COPBBBCG.
The MICROWIRE Master always initiates all data exchanges. The MSEL bit in the CNTRL register must be set to
enable the SO and SK functions onto the G Port. The SO
and SK pins must also be selected as outputs by setting
appropriate bits in the Port G configuration register. Table
VII summarizes the bit settings required for Master mode of
operation.
TABLE VII
This table assumes that the control flag MSEL is set.
G4(SO)
Conflg. Bit
G5 (SK)
Conflg. Bit
G4
Fun.
G5
Fun.
Operation
1
1
SO
Int.
SK
MICROWIRE
Master
0
1
TRISTATE
Int.
SK
MICROWIRE
Master
1
0
SO
Ext.
SK
MICROWIRE
Slave
0
0
TRISTATE
Ext.
SK
MICROWIRE
Slave
MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the
SKclock is generated by an external source. Setting the
MSEL bit in the CNTRL register enables the SO and SK
functions onto the G Port. The SK pin must be selected as
an input and the SO pin is selected as an output pin by
setting and resetting the appropriate bit in the Port G configuration register. Table VII summarizes the settings required
to enter the Slave mode of operation.
I/o
LINES
8-BIT
lK BYTE
AID
EEPROM
COP495
COP43X
LCD
DISPLAY
DRIVER
COP472
COPS
MASTER
VF
DISPLAY
DRIVER
COP470
SII+---lI"",,+-+--~H---+-I----+-+---I
I/O
LINES
COPS
(SLAVE)
SO
~
~
~
~
TL/DD/9765-24
FIGURE 18. MICROWIRE Application
2-141
Q)
Q)
Q)
oG)
CJ
~
Memory Map
~
All RAM, ports and registers (except A and PC) are mapped into data memory address space.
oo
Address
S/MAR
0000 to OOSF
On-Chip RAM bytes (112 bytes)
0070 to 007F
Unused RAM Address Space (Reads
As All Ones)
Unused RAM Address Space (Reads
Undefined Data)
xx80toxxAF
xxBO
XXB1
xxB2
xxB3
xxB4
xxB5
xxBS
xxB7
xxB8
xxB9
xxBA
xxBB
xxBC
xxBD
xxBE
xxBF
xxCO
xxC1
xxC2
xxC3
xxC4
xxC5
xxC6
xxC7
xxC8
xxC9
xxCA
xxCB
xxCC
xxCDtoxxCF
Address
S/MAR
Contents
Timer T3 Lower Byte
Timer T3 Upper Byte
Timer T3 Autoload Register T3RA
Lower Byte
Timer T3 Autoload Register T3RA
Upper Byte
Timer T3 Autoload Register T3RB
Lower Byte
Timer T3 Autoload Register T3RB
Upper Byte
Timer T3 Control Register
Comparator Select Register
UART Transmit Buffer (TBUF)
UART Receive Buffer (RBUF)
UART Control and Status Register
(ENU)
UART Receive Control and Status
Register (ENUR)
UART Interrupt and Clock Source
Register (ENUI)
UART Baud Register (BAUD)
UART Prescale Select Register (PSR)
Reserved for UART
xxDO
xxD1
xxD2
xxD3
xxD4
xxD5
xxDS
xxD7
xxD8
xxD9
xxDA
xxDB
xxDC
xxDDto OF
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
PortO
Reserved for Port 0
xxEOto xxE5
xxES
xxEE
xxEF
Reserved for EE Control Registers
Timer T1 Autoload Register T1 RB
Lower Byte
Timer T1 Autoload Register T1 RB
Upper Byte
ICNTRL Register
MICROWIRE Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1 RA
Lower Byte
Timer T1 Autoload Register T1 RA
Upper Byte
CNTRL Control Register
PSW Register
xxFOto FB
xxFC
xxFD
xxFE
xxFF
On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
Reserved
0100-013F
On-Chip RAM Bytes (S4 bytes)
xxE7
xxE8
xxE9
xxEA
xxEB
xxEC
xxED
Timer T2 Lower Byte
Timer T2 Upper Byte
Timer T2 Autoload Register T2RA
Lower Byte
Timer T2 Autoload Register T2RA
Upper Byte
Timer T2 Autoload Register T2RB
Lower Byte
Timer T2 Autoload Register T2RB
Upper Byte
Timer T2 Control Register
WatchDog Service Register
(Reg:WDCNT)
MIWU Edge Select Register
(Reg:WKEDG)
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register
(Reg:WKPND)
Reserved
Reserved
Reserved
Contents
Reading memory locations 0070H-007FH (Segment 0) will return all ones.
Reading unused memory locations OOBOH-OOAFH (Segment 0) will return
undefined data. Reading unused memory locations 0140-017F (Segment 1)
will return all ones. Reading memory locations from other Segments (Le.,
Segment 2, Segment 3, ... etc.) will return all ones.
2-142
(')
o
Addressing Modes
"tJ
The COP888CG has ten addressing modes, six for operand
addressing and four for transfer of control.
Indirect
This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits
of PC) for accessing a location in the program memory. The
contents of this program memory location serve as a partial
address (lower 8 bits of PC) for the jump to the next instruction.
OPERAND ADDRESSING MODES
Register Indirect
This is the "normal" addressing mode for the COP888CG.
The operand is the data memory addressed by the B pointer
or X pointer.
co
co
co
(')
G')
Note: The VIS is a special case of the Indirect Transfer of Control address·
ing mode, where the double byte vector associated with the interrupt
is transferred from adjacent addresses in the program memory into
the program counter (PC) in order to jump to the associated interrupt
service routine.
Register Indirect (with auto post Increment or
decrement of pointer)
This addressing mode is used with the LD and X instructions. The operand is the data memory addressed by the B
pointer or X pointer. This is a register indirect mode that
automatically post increments or decrements the B or X register after executing the instruction.
Instruction Set
Register and Symbol Definition
Direct
Registers
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
A
B
Immediate
X
The instruction contains an 8-bit immediate field as the operand.
SP
PC
PU
PL
C
HC
GIE
Short Immediate
This addressing mode is used with the LBI instruction. The
instruction contains a 4-bit immediate field as the operand.
Indirect
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.
VU
VL
8-Bit Ac;cumulator Register
8-Bit Address Register
8-Bit Address Register
8-Bit Stack Pointer Register
15-Bit Program Counter Register
Upper 7 Bits of PC
Lower 8 Bits of PC
1 Bit of PSW Register for Carry
1 Bit of PSW Register for Half Carry
1 Bit of PSW Register for Global
Interrupt Enable
Interrupt Vector Upper Byte
Interrupt Vector Lower Byte
TRANSFER OF CONTROL ADDRESSING MODES
Relative
Symbols
This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new
program location. JP has a range from -31 to + 32 to allow
a 1-byte relative jump (JP + 1 is implemented by a NOP
instruction). There are no "pages" when using JP, since all
15 bits of PC are used.
[B]
[X]
MD
Mem
Meml
Absolute
This mode is used with the JMP and JSR instructions, with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any location in the current 4k program memory segment.
Imm
Reg
Absolute Long
Bit
This mode is used with the JMPL and JSRL instructions,
with the instruction field of 15 bits replacing the entire 15
bits of the program counter (PC). This allows jumping to any
location in the current 4k program memory space.
<<->
2-143
Memory Indirectly Addressed by B
Register
Memory Indirectly Addressed by X
Register
Direct Addressed Memory
Direct Addressed Memory or [B]
Direct Addressed Memory or [B] or
Immediate Data
8-Bit Immediate Data
Register Memory: Addresses FO to FF
(Includes B, X and SP)
Bit Number (0 to 7)
Loaded with
Exchanged with
fII
CJ
~
co
~
oo
Instruction Set (Continued)
INSTRUCTION SET
ADD
ADC
A,Meml
A,Meml
ADD
ADD with Carry
SUBC
A,Meml
Subtract with Carry
AND
ANDSZ
OR
XOR
IFEQ
IFEQ
IFNE
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND
A,Meml
A,lmm
A,Meml
A,Meml
MD,Imm
A,Meml
A,Meml
A,Meml
#
Reg
#,Mem
#,Mem
#,Mem
Logical AND
Logical AND Immed., Skip if Zero
Logical OR
Logical EXclusive OR
IF EQual
IF EQual
IF Not Equal
IF Greater Than
If B Not Equal
Decrement Reg., Skip if Zero
Set BIT
Reset BIT
IFBIT
Reset PeNDing Flag
A <- A + Meml
A < - A + Meml + C, C < - Carry
HC < - Half Carry
A < - A - Meml + C, C < - Carry
HC < - Half Carry
A < - A and Meml
Skip next if (A and Imm) = 0
A <- AorMeml
A < - A xor Meml
Compare MD and Imm, Do next if MD = Imm
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A not = Meml
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of B not = Imm
Reg < - Reg- 1, Skip if Reg = 0
1 to bit, Mem (bit = 0 to 7 immediate)
Oto bit, Mem
If bit in A or Mem is true do next instruction
Reset Software Interrupt Pending Flag
X
LD
LD
LD
LD
A,Mem
A,Meml
B,lmm
Mem,lmm
Reg,lmm
EXchange A with Memory
LoaD A with Memory
LoaD B with Immed.
LoaD Memory Immed
LoaD Register Memory Immed.
A <-> Mem
A <- Meml
B <-Imm
Mem <-Imm
Reg <-Imm
X
X
LD
LD
LD
A, [B ±]
A, [X ±]
A, [B±]
A, [X±]
[B±],lmm
EXchange A with Memory [B]
EXchange A with Memory [X]
LoaD A with Memory [B]
LoaD A with Memory [X]
LoaD Memory [B] Immed.
A < - > [B], (B < - B ± 1)
A <-> [Xl. (X <- ±1)
A < - [B], (B < - B ± 1)
A < - [Xl. (X < - X ± 1)
[B] <-Imm, (B <- B±1)
CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
RC
IFC
IFNC
POP
PUSH
A
A
A
CLeaR A
INCrementA
DECrementA
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
SetC
ResetC
IFC
IFNotC
POP the stack into A
PUSH A onto the stack
A<-O
A<- A + 1
A<-A-1
A < - ROM (PU,A)
A < - BCD correction (follows ADC, SUBC)
C - > A7 - > ... - > AO - > C
C < - A7 < - ... < - AO < - C
A7 ... A4 < - > A3 ... AO
C <- 1, HC <- 1
C <- 0, HC <- 0
IF C is true, do next instruction
If C is not true, do next instruction
SP < - SP + 1, A < - [SP]
[SP] < - A, SP < - SP - 1
Vector to Interrupt Service Routine
Jump absolute Long
Jump absolute
Jump relative short
Jump SubRoutine Long
Jump SubRoutine
Jump InDirect
RETurn from subroutine
RETurn and SKip
RETurn from Interrupt
Generate an Interrupt
No OPeration
PU <- [VU], PL < - [VL]
PC < - ii (ii = 15 bits, 0 to 32k)
PC9 ... 0 <- i(i = 12 bits)
PC < - PC + r (r is - 31 to + 32, not 1)
[SP] < - PL, [SP-1] < - PU,SP-2, PC < - ii
[SP] < - PL, [SP-1] < - PU,SP-2, PC9 ... 0 < - i
PL < - ROM (PU,A)
SP + 2, PL <-[SP], PU <- [SP-1]
SP + 2, PL < - [SP],PU < - [SP-1],Skip < - 1
SP + 2, PL < - [SP],PU < - [SP-1],GIE< - 1
[SP] < - PL, [SP-1] < - PU, SP-2, PC < - OFF
PC<-PC+1
VIS
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
A
A
A
A
A
A
Addr.
Addr.
Disp.
Addr.
Addr
2·144
o
a"tJ
Instruction Execution Time
Most instructions are single byte (with immediate addressing mode instructions taking two bytes).
Most single byte instructions take one cycle time (1 J-Ls at 10 MHz) to execute.
See the BYTES and CYCLES per INSTRUCTION table for details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles for each instruction in the format of byte/cycle (a cycle is 1 p.s at
10 MHz).
[B]
Direct
ADD
ADC
SUBC
AND
OR
XOR
IFEO
IFNE
IFGT
IFBNE
DRSZ
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
SBIT
RBIT
IFBIT
1/1
1/1
1/1
RPND
1/1
Instructions Using A & C
Immed.
CLRA
INCA
DECA
LAID
DCOR
RRCA
RLCA
SWAPA
SC
RC
IFC
IFNC
PUSHA
POPA
ANDSZ
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
1/3
3/4
3/4
3/4
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2
Transfer of Control
Instructions
JMPL
JMP
JP
JSRL
JSR
JID
VIS
RET
RETSK
RETI
INTR
NOP
Memory Transfer Instructions
Register
Indirect
XA,·
LOA,·
LD B,lmm
LDB,lmm
LDMem,lmm
LD Reg,lmm
IFEOMD,lmm
• =
>
[B]
[X]
1/1
1/1
1/3
1/3
2/2
Direct Immed.
2/3
2/3
2/2
1/1
2/2
3/3
2/3
3/3
Register Indirect
Auto Incr. & Decr.
[B+,B-]
[X+,X-]
1/2
1/2
1/3
1/3
(IFB<16)
(IF B > 15)
2/2
Memory location addressed by B or X or directly.
2-145
3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5
117
1/1
co
co
co
o
C)
C!J
o
co
COP888CG Opcode Table
D.
Upper Nibble Along X-Axis
Lower Nibble Along Y-Axis
co
co
oo
F
E
0
C
JP -15
JP -31
LD OFO, # i
DRSZOFO
RRCA
RC
ADCA,#i
ADCA,[B]
JP -14
JP -30
LD OF1, # i
DRSZOF1
*
SC
SUBCA, #i
SUB A,[B]
1
JP -13
JP -29
LD OF2, # i
DRSZOF2
XA,[X+]
XA,[B+]
IFEOA,#i
IFEOA,[B]
2
JP -12
JP -28
LD OF3, # i
DRSZOF3
XA, [X-]
XA,[B-]
IFGTA,#i
IFGTA,[B]
3
JP -11
JP -27
LDOF4, # i
DRSZOF4
VIS
LAID
ADDA,#i
ADDA,[B]
4
JP -10
JP -26
LD OF5, # i
DRSZOF5
RPND
JID
ANDA,#i
AND A, [B)
5
JP -9
JP -25
LD OF6, # i
DRSZOF6
XA,[X]
XA,[B]
XOR A,#i
XORA,[B]
6
JP -8
JP -24
LDOF7, # i
DRSZOF7
*
*
ORA,#i
ORA,[B]
7
JP -7
JP -23
LD OF8, # i
DRSZOF8
NOP
RLCA
LDA,#i
IFC
8
JP -6
JP -22
LD OF9, # i
DRSZOF9
IFNE
A,[B]
IFEO
Md,#i
IFNE
A,#i
IFNC
9
JP -5
JP -21
LDOFA, # i
DRSZ OFA
LDA,[X+]
LDA,[B+]
LD [B+ ],#i
INCA
A
JP -4
JP -20
LD OFB, # i
DRSZOFB
LDA,[X-]
LDA,[B-]
LD [B-],#i
DECA
B
JP -3
JP -19
LDOFC, # i
DRSZOFC
LD Md,#i
JMPL
XA,Md
POPA
C
B
9
A
8
0
JP -2
JP -18
LDOFD, # i
DRSZOFD
DIR
JSRL
LDA,Md
RETSK
D
JP -1
Jp -17
LD OFE, # i
DRSZOFE
LDA,[X]
LDA,[B]
LD [B],#i
RET
E
JP -0
JP -16
LDOFF, # i
DRSZOFF
*
*
LDB,#i
RETI
F
2-146
o
COP888CG Opcode Table
o-a
(Continued)
CD
CD
CD
Upper Nibble Along X-Axis
o
Lower Nibble Along Y-Axis
C)
3
2
1
IFBNEO
JSR
xOOO-xOFF
JMP
xOOO-xOFF
JP +17
INTR
0
LO B,#OE
IFBNE 1
JSR
x100-x1FF
JMP
x100-x1FF
JP +1S
JP + 2
1
LO B,#OO
IFBNE2
JMP
x200-x2FF
JP +19
JP + 3
2
·
JSR
x200-x2FF
LO B,#OC
IFBNE3
JSR
x300-x3FF
JMP
x300-x3FF
JP +20
JP + 4
3
IFBIT
4,[B]
CLRA
LO B,#08
IFBNE4
JSR
x400-x4FF
JMP
x400-x4FF
JP +21
JP + 5
4
IFBIT
5,[B]
SWAPA
LO B,#OA
IFBNE 5
JSR
x500-x5FF
JMP
x500-x5FF
JP +22
JP + 6
5
IFBIT
6,[B]
OCORA
LO B,#09
IFBNE6
JSR
x600-x6FF
JMP
x600-x6FF
JP +23
JP + 7
6
IFBIT
7,[B]
PUSHA
LO B,#OS
IFBNE7
JSR
x700-x7FF
JMP
x700-x7FF
JP +24
JP + S
7
SBIT
O,[B]
RBIT
O,[B]
LO B,#07
IFBNES
JSR
xSOO-xSFF
JMP
xSOO-xSFF
JP +25
JP + 9
S
SBIT
1,[B]
RBIT
1,[B]
LO B,#06
IFBNE9
JSR
x900-x9FF
JMP
x900-x9FF
JP +26
JP + 10
9
SBIT
2,[B]
RBIT
2,[B]
LO B,#05
IFBNEOA
JSR
xAOO-xAFF
JMP
xAOO-xAFF
JP +27
JP + 11
A
SBIT
3,[B]
RBIT
3,[B]
LO B,#04
IFBNEOB
JSR
xBOO-xBFF
JMP
xBOO-xBFF
JP +2S
JP + 12
B
SBIT
4,[B]
RBIT
4,[B]
LO B,#03
IFBNEOC
JSR
xCOO-xCFF
JMP
xCOO-xCFF
JP +29
JP + 13
C
SBIT
5,[B]
RBIT
5,[B]
LO B,#02
IFBNEOO
JSR
xOOO-xOFF
JMP
xOOO-xOFF
JP +30
JP + 14
0
SBIT
6,[B]
RBIT
6,[B]
LO B,#01
IFBNEOE
JSR
xEOO-xEFF
JMP
xEOO-xEFF
JP +31
JP + 15
E
SBIT
7,[B]
RBIT
7,[B]
LOB,#OO
IFBNEOF
JSR
xFOO-xFFF
JMP
xFOO-xFFF
JP +32
JP + 16
F
7
6
5
IFBIT
O,[B]
ANOSZ
A, #i
LOB,#OF
·
·
IFBIT
1,[B]
IFBIT
2,[B]
IFBIT
3,[B]
4
Where,
i is the immediate data
Md is a directly addressed memory location
• is an unused opcode
Note: The opcode 60 Hex is also the opcode for IFBIT "'I,A
2·147
0
C!J
o
co
co
co
D.
o
o
Mask Options
Development Support
The COP888CG mask programmable options are shown
below. The options are programmed at the same time as
the ROM pattern submission.
MOLE DEVELOPMENT SYSTEM
The MOLE (Microcomputer On Line Emulator) is a low cost
development system and emulator for all microcontroller
products. These include COPSTM microcontrollers and the
HPC family of products. The MOLE consists of a BRAIN
Board, Personality Board and optional host software.
The purpose of the MOLE is to provide the user with a tool
to write and assemble code, emulate code for the target
microcontroller and assist in both software and hardware
debugging of the system.
OPTION 1: CLOCK CONFIGURATION
=1
=2
Crystal Oscillator (CKI/10)
G7 (CKO) is clock generator
output to crystal/resonator
CKI is the clock input
Single-pin RC controlled
oscillator (CKI/10)
It is a self contained computer with its own firmware which
provides for all system operation, emulation control, communication, PROM programming and diagnostic operations.
G7 is available as a HALT
restart and/or general purpose
input
It contains three serial ports to optionally connect to a terminal, a host system, a printer or a modem, or to connect to
other MOLEs in a multi-MOLE environment.
OPTION 2: HALT
=1
=2
Enable HALT mode
MOLE can be used in either a stand alone mode or in conjunction with a selected host system using PC-DOS communicating via a RS-232 port.
Disable HALT mode
OPTION 3: COP888CG BONDING
=1
=2
=3
=4
44-Pin PCC
40-Pin DIP
How to Order
To order a complete development package, select the section for the microcontroller to be developed and order the
parts listed.
28-Pin PCC
28-Pin DIP
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (if clock option-1 has been selected). The
CKI input frequency is divided down by 10 to produce the
instruction cycle clock (1 ltd.
Development Tools Selection Table
Mlcrocontroller
COP888
Order
Part Number
Description
Includes
Manual
Number
MOLE-BRAIN
Brain Board
Brain Board Users Manual
420408188-001
MOLE-COP8-PB2
Personality Board
COP888 Personality Board
Users Manual
420420084-001
MOLE-COP8-IBM
Assembler Software for IBM
COP800 Software Users Manual
and Software Disk
PC-DOS Communications
Software Users Manual
424410527-001
TBD
Programmer's Manual
2-148
420040416-001
TBD
o
o-a
Development Support (Continued)
DIAL·A·HELPER
If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk for
later use.
Dial-A-Helper is a service provided by the MOLE (Microcontroller On Line Emulator) applications group. It consists of
an electronic bulletin board information system and a method by which applications can take control of a MOLE Development System at a remote site via modem in order to resolve any problems.
Order PIN: MOLE·DIAL·A·HLP
Information System Package Contents
Dial-A-Helper User Manual PIN
Public Domain Communications Software
Information System
The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION mode
that can be used to search out and retrieve application data
about NSC Microcontrollers. The user needs as a minimum,
a Dumb terminal, 300 or 1200 baud modem, and a telephone.
Voice: (408) 721-5582
Factory Applications Support
Dial-A-Helper also provides immediate factor applications
support. If a user is having difficulty in getting a MOLE to
operate in a particular mode or something peculiar is occuring, he can contact us via his system and modem. He can
leave messages on our electronic bulletin board, which we
will responed to, or he can arrange for us to actually take
control of his system via modem for debugging purposes.
The applications group can then cause his system to execute various commands and try to resolve the customer's
problem by actually getting customer's system to respond.
Both parties see exactly what is occurring, as it is happening.
Modem: (408) 739-1162
Baud:
Set-up:
300 or 1200 Baud
Length:
8-Bit
Parity:
None
This allows us to respond in minutes when applications help
is needed.
Stop Bit:
Operation: 24 Hours, 7 Days
DIAL-A-HELPER
USER'S
TARGET
SYSTEM
1..----..
1
1
MODEM
I . . . . ...
II-----i
......l - - -.........- ilI
I
HOST
COMPUTER
MOLE
USER SITE
"O~.
I
I
11----1
1
HOST
COMPUTER
I
.OLE
NATIONAL SEMICONDUCTOR SITE
TLlDD/9765-25
2-149
Q:)
Q:)
Q:)
o
C)
Section 3
COPS Applications
'.
Section 3 Contents
COP Brief 2 Easy Logarithms for COP400 .............................................
COP Brief 4 L-Bus Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP Brief 5 Software and Opcode Differences in the COP444L Instruction Set . . . . . . . . . . . . .
COP Brief 6 RAM Keep-Alive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP Note 1 Analog to Digital Conversion Techniques with COPS Family Microcontrollers....
COP Note 4 The COP444L Evaluation Device 444L-EVAL ...............................
COP Note 5 Oscillator Characteristics of COPS Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . .
COP Note 6 Triac Control Using the COP400 Microcontroller Family......................
COP Note 7 Testing of COPS Chips...................................................
AB-3 Current Consumption in NMOS COPS Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AB-4 Further Information on Testing of COPS Microcontrollers ... . . . . . . . . . . . . . . . . . . . . . . . .
AB-6 COPS Interrupts. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .
AB-15 Protecting Data in the NMC9306/COP494 and NMC9346/COP495 Serial EEPROMs.
AB-28 COPS Peripheral Chips .......................................................
AN-326 A Users Guide to COPS Oscillator Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-329 Implementing an 8-bit Buffer in COPS..........................................
AN-338 Designing with the NMC9306/COP494 a Versatile Simple to Use E2PROM .........
AN-400 A Study of the Crystal Oscillator for CMOS-COPS ...............................
AN-401 Selecting Input/Output Options on COPS Microcontrollers. . . . . . . . . . . . . . . . . . . . . . . .
AN-440 New CMOS Vacuum Fluorescent Drivers Enable Three Chip System to Provide
Intelligent Control of Dot Matrix V.F. Display .........................................
AN-452 MICROWIRE Serial Interface .................................................
AN-453 COPS Based Automobile Instrument Cluster. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-454 Automotive Multiplex Wiring.. .. .. . .. . .. . .. . . .. .. . . .. .. .. .. .. .. .. . . . . . . . .. .. ..
AN-521 Dual Tone Multiple Frequency (DTMF) .........................................
3-2
3-3
3-14
3-15
3-16
3-17
3-49
3-54
3-71
3-79
3-88
3-90
3-92
3-93
3-95
3-97
3-101
3-105
3-111
3-115
3-125
3-135
3-146
3-151
3-155
(')
o"U
Easy Logarithms for
COP400
National Semiconductor
COP Brief 2
Logarithms have long been a convenient tool for the simplification of multiplication, division, and root extraction. Many
assembly language programmers avoid the use of logarithms because of supposed complexity in their application
to binary computers. Logarithms conjure up visions of time
consuming iterations during the solution of a long series.
The problem is far simpler than imagined and its solution
yields, for the applications programmer, the classical benefits of logarithms:
1) Multiplication can be performed by a single addition.
2) Division can be performed by a single subtraction.
3) Raising a number to a power involves a single multiply.
4) Extracting a root involves a single divide.
When applied to binary computer operation logarithms yield
two further important advantages. First, a broad range of
values can be handled without resorting to floating point
techniques (other than implied by the characteristic). Second, it is possible to establish the significance of an answer
during the body of a calculation, again, without resorting to
floating point techniques.
Implementation of base10 logarithms in a binary system is
cumbersome and unnecessary since logarithmic functions
can be implemented in a number system of any base. The
techniques presented here deal only with logarithms to the
base2·
A logarithm consists of two parts: an integer characteristic
and a fractional mantissa.
In Figure 1 some points on the logarithmic curve are identified and evaluated to the base2. Notice that the characteristic in each case represents the highest even power of 2
contained in the value of X. This is readily seen when binary
notation is used.
m
:a
m
-n
N
X10
H-
:r /~ '"
/
/1~2
3
4
LOG2 1 = 0.00
5
6
7
8
9
LOG2 10 =
0 0
2
010.0000
0 1 0
0 0
3
011.0000
..
1 0
3
0 0
.
8
..
1 0
1000
01 1 1
0110
0101
0100
0011
X
Value of X In Binary
0000
0001
0010
0100
1000
0000
1000
0000
0000
0000
0000
0000
Initial
First Shift
Second Shift
Third Shift
Fourth Shift
Fifth Shift
10
CHARACTERISTIC
MANTISSA
1
0.95
0.00
0.00
0.52
2
3
3
1
4
Counter for
Characteristic
TL/DD/6942-1
LOG2 3=
LOG2 4~
LOG2 8=
1
0
In Figure 2 each point evaluated in Figure 1 has been repeated using binary notation. An arrow subscript indicates
the highest even power of 2 appearing in each value of X.
Notice that in X = 3 the highest even power of 2 is 21. Thus
the characteristic of the log2 3 is 1. Where X = 10 the
characteristic of the log2 10 is 3.
To find the log2 X is very easy where X is an even power of
2. We simply shift the value of X left until a carry bit emerges
from the high order position of the register. This procedure
is illustrated in Figure 3. This characteristic is found by
counting the number of shifts required and subtracting the
result from the number of bits in the register. In practice it is
easier to being with the number of bits and count down
once prior to each shift.
LOG210=3.52
,
1 1
0 0
FIGURE 2. Identification of the Characteristic
2~~-
31-
.
3
10 0
y
LOG28=3.oo
X2
Log2 X
Log2 X Where X =
24 23 22 21 20 Characteristic Even Power of 2
Characteristic
Mantissa
011.0000
0000
Final
Log2X = 3.00
FIGURE 3. Conversion to Base2 Logarithm
by Base Shift
Examination of the final value obtained in Figure 3 reveals
no bits in the mantissa. The value 3 in the characteristic,
however, indicates that a bit did exist in the 23 position of
the original number and would have to be restored in order
to reconstruct the original value (antilog).
FIGURE 1. The Logarithmic Function and
Some Example Values
3-3
•
~
U.
1&.1
a:
ID
A.
o(,)
,------------------------------------------------------------------------------------,
A simple flow chart, and program, can be devised for generating the values found in the table and, as will be apparent,
a straight line approximation for values that are not even
powers of 2. The method, as already illustrated in Figure 3,
involves only shifting a binary number left until the most
significant bit moves into the carry position. The characteristic is formed by counting. Since a carry on each successive
shift will yield a decreasing power of 2, we must start the
characteristic count with the number of bits in the binary
value (x) and count down one each shift.
The log of any even power of 2 can be found in this way:
Decimal
Binary
Log2
128
64
32
4
2
1
10000000
01000000
00100000
00000100
00000010
00000001
0111.00000000
0110.00000000
0101.00000000
0010.00000000
0001.00000000
0000.00000000
FIGURE 4. Base2 Logarithms of Even Powers of 2
LOG2
LOAD EXPONENT WITH COUNT EQUAL TD
NUMBER OF BITS IN MANTISSA MINUS 1
SLP1
TL/DD/6942-2
FIGURE 5. Log Flowchart
3-4
o
COP CROSS ASSEMBLER
LOGS
PAGE:
a""0
1
OJ
; TITLE LOGS
1
:0
; BINARY LOGARITHMS
m
"'T1
2
3
4
01A4
. CHIP 420
I\)
; ....-
5
CONVERT TO LOGARITHM _ ..... ;
6
7
RAM ASSIGNMENT
8
9
; DIGIT:
10
11
12
13
14
15
16
13
12
11
10
;
;
;
;
;
;
;
08
07
06
05
04
03
02
01
00
TEMP
CH HM LM
; REG 2
; REG 3
09
CH HM LM
; REG 1
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TEMP
CH HM LM
TEMP
TEMP
CH HM LM
. LOCAL
CH, HM, LM REPRESENT ANY THREE SEQUENTIAL MEMORY DIGITS. THEY
MAY BE DEFINED IN ANY REGISTER. THE SYMBOLIC NOTATION CH, HM,
AND LM ARE USED FOR ADDRESSING TO ALLOW USER FLEXIBILITY.
UPON ENTRY TO THE ROUTINE HM AND LM CONTAIN THE HI AND LO
OF SOME VALUE X. THE MEMORY POINTER MUST CONTAIN THE ADDRESS
OF THE CHARACTERISTIC (CH). THE CONTENTS OF THIS LOCATION ARE
IGNORED AND ARE LOST DURING EXECUTION.
; UPON EXIT CH, HM, LM CONTAIN A STRAIGHT LINE APPROXIMATION OF
; THE LOG BASE 2 OF X. CH = CHARACTERISTIC HM = HI ORDER MANTISSA
; LM = LO ORDER MANTISSA. AN 8 BIT MEMORY AREA (TEMP) IS USED IN
; THE REGISTER OPPOSITE DURING THE CORRECTION OF A STRAIGHT
LINE APPROXIMATION OF A LOG OR AN ANTILOG.
;
A TEST IS MADE FOR X = O. IF THE VALUE OF X
; IS NOT ZERO AN INSTRUCTION IS SKIPPED UPON RETURN
; TO THE CALLING ROUTINE.
33
- EXAMPLE; SUBROUTINE CALL
; RETURN HERE IF X=O·; RETURN HERE IF )(>0·-
000
001
002
00
57
06
COP CROSS ASSEMBLER
LOGS
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
14
; REG 0
17
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
15
003
A4
004
A9
005
006
007
008
009
OOA
OOB
OOC
20
C8
49
05
5F
48
06
C3
LOG2:
JSR LOG2
JP
ZERO
CONTINUE
CLRA
AISC
07
X
PAGE:
; SET CHARACTERISTIC.
; TO REG LENGTH -1.
; STORE IN MEMORY.
2
$LP1:
$TS1:
$LST:
$NO:
$TS2:
JSRP
SDB2
JSRP
SHLR
SKC
JP
RETSK
LD
AISC
RET
X
JP
$NO
-1
$LPl
; SET ADDRESS POINTER
; BACK 2 DIGITS.
; RESET CARRY AND SHIFT
; REG LEFT ONE BIT.
; IS CARRY = 1 YET?
; NO - KEEP GOING.
; YES - FINISHED!!
; NO - LOAD COUNT IN ACC.
; SUBTRACT ONE.
; MANTISSA IS A O! RETURN
; STORE CHARACTERISTIC.
; DO IT AGAIN!
; 2 ROUTINES ARE CALLED FROM THE SUBROUTINE PAGE BY THIS
; PROGRAM: SDB2, SHLR.
TLlDD/6942-5
FIGURES
3-5
•
~ r---------------------------------------------------------------------------------------~
LL.
W
Ii:
m
a..
oo
The program shown develops the log2 of any even power of
2 by shifting and testing as previously described. Examine
what happens to a value of X that is not an even power of 2.
In Figure 7, the number 25 is converted to a base 2 log.
To reconstruct the original value of X, find the antilog, requires only restoration of the most significant bit and then its
alignment with the power of 2 position indicated by the characteristic. In the example, approximation (log2 25 =
0100.1001) restoration of MSB can be accomplished by
shifting the mantissa (only) one position to the right. In the
process a one is shifted into the MSB position.
Approximation of Log2 X
Restoration of MSB
Char. Mantissa
Char. Mantissa
0100.10010000
0100.11001000
The value of the characteristic is 4 so the mantissa must be
shifted to the right until MSB is aligned with the 24 position.
27
26
25
24
23
22
21
20
2510 = 000 1 1 0022
Shift left until carry = 1
Characteristic Carry Mantissa
Log2
0100
1 100100000100.10010000
Figure 7. Straight Line Approximation of Base2 Log
The resulting number when viewed as an integer characteristic and a fractional mantissa is 4.562510. The fraction
0.5625 is a straight line approximation of the logarithmic
curve between the correct values for the base2 logs of 24
and 25. The accuracy of this approximation is sufficient for
many applications. The error can be corrected, as will be
seen later in this discussion, but for now let's look at the
problem of exponents or the conversion to an antilog.
The completion of this operation restores the value of X
(X = 25) and is the procedure used to find an antilog. Figure 8 is a flow chart for finding an antilog using this procedure. Ths implementation in source code is shown in Figure
9.
ALOG:
r--....RA-R-Y-M-EM-O-Ry-L-O-CA-TI-ON----,
MO- V-E -MA-N-TIS-S-A-TO-T-EM....PO
=
CLEAR MANTISSA AREA. SET X 4>
SET CARRY = 1 TO FORCE MSB OF X
$SLX:
~----------------~--~------------~
SUBTRACT 1 FROM CHARACTERISTIC
$TST:
TL/DD/6942-3
FIGURE 8. Flow Chart for Conversion to Antilog
3-6
o
o"'0
COP CROSS ASSEMBLER PAGE 3
LOGS
73
74
75
76
m
. FORM
~
; .....- CONVERT TO ANTILOG - ....• ;
m
-n
I\)
; THE FOLLOWING SUBROUTINE CONVERTS THE STRAIGHT LINE
; THE APPROXIMATION OF A BASE 2 LOGARITHM TO ITS CORRESPONDING
; ANTILOG. UPON EXIT FROM THE ROUTINE THE CONTENTS OF CH
; WILL BE EaUAL TO THE HEXADECIMAL VALUE OF 'CI>F .
77
78
79
80
81
82
. LOCAL
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
000
ooE
ooF
010
011
012
013
014
015
01
A4
00
36
34
00
017
018
019
01A
01B
01C
A3
AA
05
5F
48
010
01E
ALOG:
CLRA
JSRP
SDB2
X
XIS
CLRA
X
XDS
SC
JP
JSRP
03
03
SDR2
SHLC
36
JSRP
JSRP
LD
AISC
RET
X
A4
06
JSRP
JP
SDB2
$SLM
36
37
22
08
A9
$SLM:
$SLX:
$TST:
$LST:
; SET ACC TO O.
; CLEAR MANTISSA AREA.
; AND MOVE MANTISSA TO
; TEMPORARY STORAGE.
; LEAVE POINTER AT LO
; ORDER OF MANTISSA.
03
03
; RESTORE MSB OF X.
$SLX
SHLR
; SHIFT REMAINDER
; LEFT INTO CARRY.
; MOVE BACK 2 DIGITS.
; SHIFT X LEFT 1.
; LOAD CHARACTERISTIC.
; CHARACTERISTIC -1.
; IF NO CARRY - FINIS.
; STORE REMAINDER AND MOVE
; DOWN ONE REGISTER.
; MOVE BACK 2 DIGITS.
; DO IT AGAIN.
-1
03
; 4 ROUTINES ARE CALLED FROM THE SUBROUTINE PAGE BY THIS
; PROGRAM: SDB2, SDR2, SHLR, SHLC.
TL/DD/6942-6
FIGURE 9
Using the linear approximation technique just described,
some error will result when converting any value of X that is
not an even power of 2.
Value of X
0,12
0.12
0.12
3
2X3= 6
4 x 3 = 12
8 x 3 = 24
0.15
0.15
0.15
0.15
2
4
Figure 10 contains a table of correct base 2 logarithms for
values of X from 1 through 32 along with the error incurred
for each when using linear approximation. Notice that no
error results for values of X that are even powers of 2. Also
notice that the error incurred for multiples of even powers of
2 of any given value of X is always the same.
3-7
Error
5
5 = 10
5 = 20
x
x
•
C\I
IL
W
a:m
X
Hexadecimal
Log Base
D.
0
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
0.00
1.00
1.95
2.00
2.52
2.95
2.CE
3.00
3.29
3.52
3.75
3.95
3.93
3.CE
3.E8
4.00
4.16
4.29
4.3F
4.52
4.67
4.75
4.87
4.95
4.A4
4.93
4.C1
4.CE;
4.09
4.E8
4.F4
5.00
Linear
Approximation
of Log Base 2
Error
Hexadecimal
0.00
1.00
1.80
2.00
2.40
2.80
2.CO
3.00
3.20
3.40
3.60
3.80
3.AO
3.CO
3.EO
4.00
4.10
4.20
4.30
4.40
4.50
4.60
4.70
4.80
4.90
4.IAO
4.90
4.CO
4.00
4.EO
4.FO
5.00
5.1-
EM -1
0.00
0.00
0.15
0.00
0.12
0.15
O.OE
0.00
0.09
0.12
0.15
0.15
0.13
O.OE
0.08
0.00
0.06
0.09
O.OF
0.12
0.17
0.15
0.17
0.15
0.14
0.13
0.11
O.OE
0.09
0.08
0.04
0.00
+
EM - EM - 1
2
0.03
0.09
0.00
0.11
0.15
0.16
0.16
0.16
0.15
0.14
0.12
0.10
0.00
O.OA
0.06
0.02
FIGURE 10. Error Incurred by Linear Approximation of Base 2 Logs
An error that repeats in this way is easily corrected using a
look-up table. The greatest absolute error will occur for the
least value of X not an even power of 2, X = 3, is about 8%.
A 4 point correction table will eliminate this error but will
move the greatest uncompensated error to X = 9 where it
will be about 4%. This process continues until at 16 correction points the maximum error for the absolute value of the
logarithm is less than 1 percent. This can be reduced to 0.3
percent by distributing the error. Interpolated error values
are listed in Figure 10 and are repeated in Figure 11 as a
binary table.
3-8
(')
High Order
4 Mantissa
Bits
Binary
Correction
Value
Hexadecimal
Correction
Value
0000
0001
0010
0011
0100
0101
0110
01 1 1
1000
1001
1010
1 01 1
1100
1 1 01
1110
1111
00000000
00001001
00001101
00010001
00010101
00010110
00010110
00010110
00010101
00010100
00010010
00010000
00001101
00001010
00000110
00000010
00
Notice in Figure 10 that left justification of the mantissa
causes its high order four bits to form a binary sequence
that always corresponds to the proper correction value. This
works to advantage when combined with the COP400 LaiD
instruction. LaiD implements a table look-up function using
the contents of a memory location as the address pointer.
Thus we can perform the required table look-up without disturbing the mantissa.
Figure 12 is the flow chart for correction of a logarithm
found by linear approximation. Figure 13 is its implementation in COP400 assembly language. Notice that there are
two entry points into the program. One is for correction of
logs (LADJ:), the other is for correction of a value prior to its
conversion to an antilog (AADJ:).
.
o9
o3
1
1
1
1
1
1
1
1
1
1
5
6
6
6
5
4
2
0
o"U
OJ
:D
iii
"T1
N
oD
OA
o6
02
FIGURE 11_ Correction Table for
L2 X Linear Approximations
(
START
)
t
LADJ:
SET MEMORY ADDRESS POINT
TO ORDER CORRECTION VALUE
SAVE TABLE POINTER IN MEMORY
LOAD HIGH ORDER MANTISSA
INTO ACCUMULATOR
SXPM:
STORE MANTISSA VALUE IN MEMORY
LOAD TABLE ADDRESS INTO ACCUMULATOR
LOAD CORRECTION VALUE INTO 0 REGISTER
SOTM:
TRANSFER CORRECTION VALUE TO MEMORY
SAoD:
ADO CORRECTION VALUE TO MANTISSA
t
SLST:
C
RETURN
)
TLlDD/6942-4
FIGURE 12_ Flow Chart for Correction of a Value Found by Straight Line Approximation
3-9
•
N
II.
W
a:
m
Q.
o(.)
COP CROSS ASSEMBLER
LOGS
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
PAGE:
4
. FORM
; •••.-
ADJUST VALUE OF LOGARITHM _ ••- ;
. LOCAL
; THE FOLLOWING TABLE IS USED DURING THE CORRECTION OF VALUES
; FOUND BY STRAIGHT LINE APPROXIMATION. IT IS PLACED HERE IN
; ORDER TO ALIGN ITS BEGINNING ELEMENT WITH A ZERO ADDRESS AS
REOUIRED BY THE LOID INSTRUCTION.
01F
020
021
022
023
024
025
026
027
028
029
02A
02B
02C
020
02E
02F
44
03
TPLS:
NOP
. WORD
; REGISTER WITH ZERO ADDRESS.
• WORD
015,016,016,016
03,09,00,011
09
00
11
15
16
16
16
15
14
12
10
00
OA
06
02
. WORD
015,014,012,010
. WORD
OD,OA,06,02
; THE FOLLOWING SUBROUTINE ADJUSTS THE VALUE OF A BASE 2
; LOGARITHM FOUND BY STRAIGHT LINE APPROXIMATION. THE
; CORRECTION TERMS ARE TAKEN FROM THE TABLE ABOVE. THE
; SUBROUTINE HAS 2 ENTRY POINTS:
LADJ: -
ADJUSTS A VALUE DURING CONVERSION TO A LOG
AADJ: -
ADJUSTS A VALUE DURING CONVERSION TO ANTILOG
; THE CARRY FLAG IS SET UPON ENTRY TO DISTINGUISH BETWEEN LOG
; (C = 1) AND ANTILOG (C = 0) CONVERSIONS. DURING A LOGARITHM
; CONVERSION THE VALUE FOUND IN THE ABOVE TABLE IS ADDED TO
; THE MANTISSA. DURING AN ANTILOG CONVERSION THE VALUE FOUND
; IN THE ABOVE TABLE IS SUBTRACTED FROM THE MANTISSA.
030
031
032
033
034
035
038
037
038
039
32
F3
22
05
07
05
37
06
AADJ:
LADJ:
SLD
00
52
COP CROSS ASSEMBLER
LOGS
PAGE:
RC
JP
SC
LD
XDS
LD
XDS
X
CLRA
AISC
SLD
03
TBL
; C=O FOR ANTILOG
; CONVERSION.
; C = FOR LOG2 ADJ.
; MOVE ADDRESS POINTER BACK
; ONE LOCATION.
; LOAD CONTENTS OF HI MANTISSA
; AND STORE IT IN THE LO ORDER
; OF THE TEMP MEMORY LOCATION.
; SET TABLE POINTER
; (ACC) TO TABLE ADDRESS.
5
152
153
154
155
156
03A
03B
030
03F
03F
BF
332C
04
07
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
040
041
80
98
SADD:
JSRP
JSRP
COMP
ADRO
042
043
35
48
SLST:
LD
RET
03
; CHARACTERISTIC AND
SGTM:
20
; LOAD CORRECTION VALUE TO O.
; TRANSFER 0 REGISTER
; CONTENTS TO MEMORY.
LOID
COMA
XIS
XDS
SKC
; ANTILOG?
; YES - COMPLIMENT.
; ADD CORRECTION VALUE
; TO MANTISSA.
; SET POINTER TO
; RETURN.
; 2 ROUTINES ARE CALLED FROM THE SUBROUTINE PAGE BY THIS
;PROGRAM:COMP,ADRO
0020
0002
=
V1 TPLS&OFF
TBL=V1I16
TLlDD/6942-7
FIGURE 13
3-10
o
o
Subroutines Used by the Log and Antilog Programs
"til
OJ
COP CROSS ASSEMBLER
LOGS
PAGE:
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
:a
6
in
.."
N
. FORM
0080
; ..._- SUBROUTINES _ .. _. ;
. PAGE 02
; THE FOLLOWING ROUTINES RESIDE ON THE SUBROUTINE PAGE. THEY
; ARE CALLED BY THE LOGS PROGRAM BUT ARE GENERAL PURPOSE IN
; NATURE AND FUNCTION AS UTILITY ROUTINES.
; -_.- COMPLEMENT 8 BITS _ ..... ;
. LOCAL
; THIS ROUTINE FORMS IN MEMORY THE 2'5 COMPLEMENT OF THE TWO
; ADJACENT DIGITS IDENTIFIED BY THE ADDRESS POINTER. THE
; CONTENTS OF THE ADDRESS POINTER ARE NOT ALTERED.
; THERE ARE TWO ENTRY POINTS:
; COP: COMPLEMENT B BITS.
; CMPE: EXTEND THE COMPLEMENT TO AN ADDITIONAL B BITS
080
081
082
083
084
085
086
087
083
089
08A
08B
08C
22
00
06
10
44
04
00
06
10
44
04
44
A4
COMP:
CMPE:
SC
CLRA
X
CASC
NOP
XIS
CLRA
X
CASC
NOP
XIS
NOP
JP
; SET MINUEND = 0
; AND STORE IN MEMORY.
; SET MINUEND=O
; AND STORE IN MEMORY.
SDB2
; AVOID SKIP IF DIGIT 15.
; RETURN THRU SDB2
; TO RESTORE POINTER.
•
; ._- ADD 8 BITS IN ADJACENT REGISTERS --_. ;
. LOCAL
; THIS ROUTINE ADDS TWO BINARY DIGITS (8 BITS) FROM ANY REGISTER
; TO THE CORRESPONDING TWO BINARY DIGITS IN EITHER REGISTER
; IMMEDIATELY ADJACENT. THERE ARE THREE ENTRY POINTS:
LADR: -
RESET CARRY AND ADD 2 DIGIT PAIRS
TLlDD/6942-8
3-11
C'I
U.
L&.I
a:m
0.
0
U
COP CROSS ASSEMBLER
LOGS
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
266
269
270
271
272
273
274
275
276
277
PAGE:
7
LADD: - ADD 2 DIGIT PAIRS WITH UNMODIFIED CARRY
ADD1: - ADD 2 SINGLE DIGITS WITH UNMODIFIED CARRY
08D
oaE
oaF
090
091
092
093
094
095
096
097
32
15
30
44
14
15
30
44
14
44
48
LADR:
LADD:
ADD1:
SLST:
RC
:0
ASC
NOP
XIS
LD
ASC
NOP
XIS
NOP
RET
01
01
01
01
; RESET CARRY PRIOR TO ADD.
; LD ADDEND AND MOVE TO ADJ REG
; ADD AUGEND.
; AVOID CARRYI
; STORE SUM AND MOVE TO ADDEND
; REPEAT PROCESS
; FOR
; HIGH ORDER
; DIGIT.
; AVOID SKIP IF DIGIT 15.
; FINISHED - RETURN!I!!
; .-.- ADD 8 BITS IN OPPOSITE REGISTERS _ ••••• ;
. LOCAL
; THIS ROUTINE ADDS TWO BINARY DIGITS (8BITS) FROM ANY REGISTER
; TO THE CORRESPONDING TWO BINARY DIGITS IN EITHER REGISTER
; DIRECTLY OPPOSITE. THERE ARE THREE ENTRY POINTS:
ADRO: - RESET CARRY AND ADD 2 DIGIT PAIRS
ADDO: - ADD 2 DIGIT PAIRS WITH UNMODIFIED CARRY
AD01: - ADD 2 SINGLE DIGITS WITH UNMODIFIED CARRY
098
099
09A
09B
09C
090
09E
09F
OAO
OA1
0A2
32
35
30
44
34
15
30
44
34
44
48
ADRO:
ADDO:
AD01:
SLST:
RC
LD
ASC
NOP
XIS
LD
ASC
NOP
XIS
NOP
RET
03
03
01
03
; RESET CARRY PRIOR TO ADD.
; LD ADDEND AND MOVE TO OPP REG
; ADD AUGEND.
; AVOID CARRY!
; STORE SUM AND MOVE TO ADDEND.
; REPEAT PROCESS
; FOR
; HIGH ORDER
; DIGIT.
; AVOID SKIP IF DIGIT 15.
; FINISHED - RETURN!I!!
; --- SET DIGIT ADDRESS BACK TWO _._•• ;
TLIDD/6942-9
3-12
o
COP CROSS ASSEMBLER
LOGS
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
PAGE:
6
."
N
; THIS ROUTINE SUBTRACTS 2 FROM THE CONTENTS OF THE
; DIGIT POINTER (B REGISTER). THE CONTENTS OF THE
; ACCUMULATOR ARE LOST IN THE PROCESS. THE USE OF
; SDB2 ALLOWS ADDRESSING WITHIN THE LOGS SUB
; ROUTINE TO BE RELATIVE TO THE CONTENTS OF THE
; ADDRESS POINTER (B REGISTER) UPON ENTRY.
; SDB2 IS COMMONLY USED IN BYTE OPERATIONS TO RESTORE THE
; DIGIT POINTER TO THE LOW ORDER POSITION.
; THERE ARE TWO ENTRY POINTS:
;SDR2:
SET DIGIT ADDRESS BACK 2 AND MOVE TO OPPOSITE REGISTER.
; SDB2: SET DIGIT ADDRESS BACK 2 RETAINING PRESENT REGISTER.
OA3
OA4
OA5
OA6
OA7
OA8
35
4E
5E
44
50
48
SDR2:
SDB2:
LD
CBA
AISC
NOP
CAB
RET
03
-2
; MOVE TO OPPOSITE REGISTER.
; PLACE DIGIT COUNT IN Ace.
; SUBTRACT 2.
; SHOULD ALWAYS SKIP.
; PUT DIGIT COUNT BACK.
; FINISHED - RETURN II
; - - SHIFT LEFT - - ;
. LOCAL
307
308
; THIS ROUTINE SHIFTS LEFT THE CONTENTS OF TWO MEMORY
; LOCATIONS ONE BIT. THERE ARE THREE ENTRY POINTS:
309
SHLR: RESETS THE CARRY BEFORE SHIFTING
IN ORDER TO FILL THE LOW ORDER
BIT POSITION WITH A O.
SHLC: SHIFTS THE STATE OF THE CARRY INTO
THE LOW ORDER BIT POSITION.
SHL 1: SHIFTS LEFT THE CONTENTS OF ONLY
ONE MEMORY LOCATION. THE STATE
OF THE CARRY IS SHIFTED INTO THE
LOW ORDER POSITION OF MEMORY.
OA9
OAA
OAB
OAC
OAD
OAE
OAF
32
05
30
44
04
05
30
COP CROSS ASSEMBLER
LOGS
332
333
334
335
336
337
m
:a
iii
• LOCAL
306
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
o"0
OBO
OB1
OB2
44
04
48
SHLR:
SHLC:
SHL1:
PAGE:
; CLEAR CARRY PRIOR TO SHI FT.
; LOAD FIRST MEM DIGIT.
; DOUBLE IT.
; AVOID SKIP.
; STORE SHIFTED DIGIT.
; LOAD NEXT MEM DIGIT.
; DOUBLE IT TOO.
RC
LD
ASC
NOP
XIS
LD
ASC
9
SLST:
AVOID SKIP, IF ANY
STORE SHIFTED DIGIT.
FINISHED - RETURN!
NOP
XIS
RET
END
TL/OD/6942-10
3·13
•
~
u.
~
,----------------------------------------------------------------------------------,
L-Bus Considerations
National Semiconductor
COP Brief 4
CD
a.
o
o
L-BUS CONSIDERATIONS
Users of the COP400 family of microcontrollers should be
aware that certain outputs exhibit peculiarities that preclude
their use as clocks for edge sensitive devices such as flipflops, counters, shift registers, etc. All family members ex-
START:
CLRA
LEI
LBI
STU
AISC
4
;ENABLE THE Q
;REGISTER TO L LINES
TEST
3
12
LOOP:
LBI
CAMQ
JP
TEST
;LOAD Q WITH X'C3
LOOP
FIGURE 1_ Glitch Test Program
eluding the COP410L and COP411 L may generate false
states on Lo-L7 during the execution of the CAMQ instruction. Figure 1 contains a short program to illustrate this.
In this program the internal Q register is enabled onto the L
lines and a steady bit pattern of logic highs is outpout on La,
L1, L6, L7, and logic lows on L2-LS via the two-byte CAMQ
instruction. Timing constraints on the device are such that
the Q register may be temporarily loaded with the second
byte of the CAMQ opcode (X'3C) prior to receiving the valid
data pattern. If this occurs, the opcode will ripple onto the L
lines and cause negative-going glitches on La, L1, L6, L7,
and positive glitches on L2-LS. Glitch durations are under 2
microseconds, although the exact value may vary due to
data patterns, processing parameters, and L line loading.
These false states are peculiar only to the CAMQ instruction
and the L lines. The user should expeience no difficulty interfacing with other COP420 outputs such as GO-G3 and
Do-D3 to edge sensitive components.
3-14
o
o
Software and Opcode
Differences in the COP444L
Instruction Set
National Semiconductor
COP Brief 5
The COP444L is essentially a COP420L with double RAM
and ROM. Because of this increased memory space certain
instructions have expanded capability in the COP444L. Note
that there are no new instructions in the COP444L and that
all instructions perform the same operations in the
COP444L as they did in the COP420L. The expanded capability is merely to allow appropriate handling of the increased memory space. The affected instructions are:
The LDD, XAD, and two byte LBI are modified so that they
may address the entire RAM space. The opcodes are as
follows:
JMP
a
JSR
a
(a = address)
LDD
r,d
(r,d = RAM address Br,Bd)
"11
U1
XAD
r,d
(r,d = RAM address Br,Bd)
LBI
r,d
(r,d = RAM address Br,Bd; only two byte form of
the instruction affected)
XABR
The JMP and JSR instructions are modified in that the address a may be anywhere within the 2048 words of ROM
space. The opcodes are as follows:
1011010I a10:9:sl
JSR
1011011I a10:9:sl
JMP
a7:0
1
1
a7:0
m
iii
(a = address)
1
"U
::::0
1
LDD
10110100111
LBI
101 r i d 1
10011100111
XAD
10010100111
111 r i d 1
111 r i d 1
The XABR instruction change is transparent to the user.
The opcode is not changed nor is the function of the instruction. The change is that values of 0 through 7 in A will address registers in the COP444L-Le. the lower three bits of
A become the Br value following the instruction. In the
COP420L, the lower two bits of A became the Br value following an XABR instruction.
Note that those instructions which have an exclusive-or argument (LD, X, XIS, XDS) are not affected. The argument is
still two bits of the opcode. This means that the exclusive-or
aspect of these instructions works within blocks of four registers. It is not possible to toggle Br from a value between 0
and 3 to a value between 4 and 7 by means of these instructions.
There are no other software or opcode differences between
the COP444L and the COP420L. Examination of the above
changes indicates that the existing opcodes for those instructions have merely been extended. There is no fundamental change.
•
3-15
~
LL.
~
r---------------------------------------------------------------------~
RAM Keep-Alive
National Semiconductor
COP Brief 6
A COPSTM application is a small scale computer system
and the design of a power shut-down is not trivial. During
the time that power is available, but out of the designed
operating range, the system must be prevented from doing
anything to harm protected data. This will typically involve
some type of external protection of timing circuit.
The desirable approach is to force the COP reset input to
zero before the voltage falls below 4.5V. This provides a
drop out rate of approximately 1 in 50k for the "L" parts and
1 in 1OOk for the 420. By also stopping the clock of the "L"
parts they can achieve a drop-out rate similar to the 420.
While not perfect, the number of cycles between data error
should be considered with respect to the needs of the application.
lEI
a..
o
o
There is an option on the COP420, 420L, and 410L parts
called "RAM Keep-Alive" that provides a separate power
supply to the RAM area of the chip via the CKO pin. The
application of power to the RAM while the remainder of the
chip has been powered down via Vee will keep the RAM
"alive".
However, the integrity of data in the RAM is not only a function of power but is also influenced by transient conditions
as power is removed and reapplied. During power-on, the
Power On Reset (PaR) circuit will keep transients from
causing changes in the RAM states. The condition of power
loss will have some probability of data change if external
control is not used.
At some point below the minimum operating voltage certain
gates will no longer respond properly while others may still
be functional until a much lower voltage. During this transition time any false signal could cause a false write to one
or more cells. Another effect could be to turn on multiple
address select lines causing data destruction.
Testing the rate of data change is very difficult because it
must be done on a statistical basis with many turn/on-turn/
off cycles. Two factors have a major bearing on the numbers derived by testing. One is to call any change in a related data block a failure, even though more than one bit in
that block may have changed (this latter case may well be
due to the "address select mode"). The second factor is
that without massive instrumentation it is impossible to examine the data after each power cycle. Indeed, to do so
might have caused errors!
By running the power cycle for a period of time and then
looking for changes, one could overlook multiple changes
thus reducing the error rate. This has been minimized by
more frequent checking which indicates that the errors are
spread out randomly over time.
The external circuitry to control the chip during the power
transition has several implementations each one being a
function of the application. The simplest hardware is found
in a battery powered (automotive) application. The circuit
must sense that the switched 12V is falling (e.g., at some
value much below 12V and still greater than 5V). This can
be done by using the unswitched 12V as a reference for a
divider to a nominal voltage of BV. As the switched 12V
drops below the reference a detector will turn on a clamp
transistor to a series switch, the paR, and/or the clock circuit (Figure 1). It should be noted that this draws current
during the absence of the switched 12V circuit.
In non-automotive usage a similar circuit can be used where
there is a stable reference voltage available to use with the
comparator/clamp. Thus a 3.6V rechargable Ni-Cad battery
could be used as the reference voltage and VRAM if the
appropriate divider is used to level shift to this operating
range.
In AC line-powered applications, a similar method could be
used with the raw DC being sensed for drop. Another method would be to sense that the line had missed 2-3 cycles
either by means of a charge pump or peak detection technique. This will provide the signal to turn on the clamp. One
must make this faster than the time to discharge the output
capacitance of the power supply, thus assuring that the
clamp has performed its function before the supply falls below spec value.
In conclusion, to protect the data stored in RAM during power-off cycle, the paR should go low before the Vee power
drops below spec and come up after Vee is within spec.
The first item must be handled with an external circuit like
Figure 1 and the latter by an RC per the data sheet.
With a power supply that drops from 4.5 to 2V in approximately 100 ms, the drop-out rate is 1 in 5k to 6k power
cycles. Reducing the voltage fall time will cause an improvement in the number of cycles per drop-out. This will reach a
limit condition of a very high number (1 per 1 million?) when
the power falls within one instruction cycle (4-10 p.s for the
420, 15-40 p.s for the "L" parts). Attaining very rapid fall
time may cause problems due to the lack of decoupling/bypass capacitance. By inserting an electronic switch between
the regulator and Vee of the COP chip one might be able to
meet this type of fall time. By implication some type of sensing is required to cause the switching.
5W
+v (12V)
~.
~1M
)
TL/DD/6946-1
FIGURE 1
3-16
o
o"tJ
National Semiconductor
COP Note 1
Leonard A. Distaso
Analog to Digital
Conversion Techniques
With COPSTM Family
Microcontrollers
Z
~
m
.In a software driven system the 0/ A converter and comparator are present but the control logic is replaced by instruction sequences. There are a variety of software/hardware
techniques for implementing AID converters. They differ primarily in their approach to the included 0/ A. There are two
primary approaches to .the digital to analog conversion
which can in turn be divided into number of sub-categories:
TABLE OF CONTENTS
1.0 INTRODUCTION
2.0 SIMPLE CAPACITOR CHARGE TIME
MEASUREMENT
a
2.1 Basic Approach
2.2 Accuracy Improvements
• 0/ A as a function of weight closures
2.3 Conclusions
3.0 PULSE WIDTH MODULATION (DUTY CYCLE)
TECHNIQUE
-
R/2R ladder
-
Binary weighted ladder
• 0/ A as function of time
- RC exponential charge
- Linear charge/discharge (dual slope)
3.1 Mathematical Analysis
3.2 Basic Implementation
3.3 Accuracy Improvements
-
Pulse width modylation
These techniques should be generally familiar to persons
skilled in the electronic art. The objective here is to illustrate
the application of· these established methods to a low cost
system with a COPS microcontroller as the intelligent control element. Circuit configurations are provided as well as
the appropriate flow charts and code to implement the function.
4.0 DUAL SLOPE INTEGRATION TECHNIQUES
4.1 Mathematical Background
4.2 Basic Dual Slope Technique
4.3 Modified Dual Slope Technique
5.0 VOLTAGE TO FREQUENCY CONVERTER, vCO'S
Some mathematical and theoretical analysis is presented as
an aid to understanding the various techniques and their
limits. However, it is not the purpose here to provide a definitive theoretical analysiS of the analog to digital conversion
process or of the various techniques described.
5.1 Basic Approach
5.2 The LM131/LM231/LM331
5.3 Voltage Controlled Oscillators
5.4 A Combined Approach
6.0 Successive Approximation
2.0 Simple Capacitor Charge Time
Measurement
6.1 Basic Approcah
6.2 Some Comments on Resistor Ladders
2.1 BASIC APPROACH
7.0 "OFFBOARD" TECHNIQUES
General
7.1 General Comments
Perhaps the simplest means to perform an analog to digital
conversion is to charge a capacitor until the capacitor voltage is equal to the unknown voltage. The capacitor voltage
and the unknown are compared by means of a standard
analog comparator. The unknown is determined simply by
counting, in the microcontroller, the amount of time it takes
for the charge on the capacitor to reach a value equal to the
unknown voltage. The capacitor voltage is given by the
standard capacitor charge equation:
7.2 AOC0800 Interface
7.3 AOC0801/2/3/4 Interface (COP431/32/33/34)
8.0 CONCLUSION
9.0 REFERENCES
1.0 Introduction
A variety of techniques for performing analog to digital conversion are presented. The COP420 microcontroller is used
as the control element in all cases. However, any of the
COPS family of microcontrollers could be used with only
minor changes in some component values to allow for different instruction cycle times.
Indirect analog to digital converters are composed of three
basic building blocks:
Vc = VO
+
[V1 - VO)[1 - e**( -tlRC»
where: Vc = capacitor voltage
VO = "dischage voltage" -
low level voltage
V1 = high level voltage
The most obvious problem with this method, from the standpoint of software implementation, is the nonlinearity of the
• 0/ A Converter
• Comparator
• Control logic
3-17
•
w
b
z
D-
o
(.)
relationship. This can be circumvented in several ways. First
of all, a routine to calculate the exponential can be implemented. This, however, usually requires too much code if
the exponential routine is not otherwise required in the program. Alternatively, the range of input voltages can be restricted so that only a portion of the capacitor charge curve
- which can be approximated with a linear relationship or
with some minor straight time curve fitting - is used. Finally, a look up table can be used which will effectively convert
the measured time to the appropriate voltage. The look up
table has the advantage that all the math can be built into
the table, thereby simplifying matters significantly. If arithmetic routines are going to be used, it is clear that the relationship is simplified if VO is OV because it then drops out
the equation.
mentation. The levels of V1 and VO are not Vee and ground
as would be desired. The level is defined by the load on the
output, the value of Vee, and the device itself. Furthermore,
these levels are likely to change from device to device and
over temperature. To be sure, the output values will be at
least those given in the data sheet, but it must be remembered that those values are minimum high voltages and
maximum low voltages. Typically, the high value will be
greater than the spec minimum and the low value will be
lower than the spec maximum. In fact, with a light load the
values will be close to Vee and ground. Therefore, in order
to obtain any accurate result for a voltage measurement the
exact values of V1 and VO need to be measured and somehow stored in the microcontroller. Typical values of these
voltages can be measured experimentally and an average
could be used for final implementation.
BASIC CIRCUIT IMPLEMENTATION
The other problem associated with the levels is that the
capacitive load on the output line is substantial and far in
excess of the values used when specifying the characteristics of the various COP420 outputs. The significant effect of
this is that it will take longer than "normal" for the output to
reach its maximum value. In addition, it is likely that there
will be dips in the output as it rises to its maximum value
since the capacitor will start to draw charging current from
the output. All of this will be fast relative to the other system
times. Still it will affect the result since the level to which the
capacitor is attempting to charge is not being applied uniformly and "instantaneously". It can be viewed as though
the voltage V1 is bouncing before it stabilizes.
The circuit in Figure 1 is the basic implementation of the
capacitor charge method of AID conversion. The selection
of input and output used is arbitrary and is dictated by general system considerations. VO is the "0" level of the G
output and V1 is the "1" level of the output. The technique
is basically to discharge the capacitor to VO (which is ideally
ground) and then to apply V1 and increment an internal
counter until the comparator changes state. The flow chart
and code for this implementation are shown in Figure 2.
ACCURACY CONSIDERATIONS
The levels reached by the microcontroller output constitute
one of the more significant problems with this basic imple-
TL/DD/6935-01
Crystal oscillator values chosen to give 4 IJ.s cycle time with divide
by 16 option selected on COP 420 CKO/CKI Pins
Vee = +5V
FIGURE 1. Basic Capacitor Charge Technique
3-18
o
o
."
Z
001
0
,TURN OFF 0 TO DISCHARGE: CAPACITOR
, INSERT SOME DELAY TO MAKE SURE CAPAC ITOR DISCHAI1GED
,USING 1:2 DIT COUNTER. BUT ONLY UPPER 8 USED IN TABLE
,LOOK UP DUE TO ACCURACY· OF RC CHARGE METHOD.
THE OTHER
,BITS COULD DE USED DUT THE COMPLICATIONS ARE NOT WORTH
,THE EFFORT FOR THIS PARTICULAR TECHNIQUE.
ALSO. HERE THE
, INPUT RANGE IS RESTRICTED SO THAT THE TOP 3 BITS ARE ZERO
R(;I\II:
11'1(;11:
UGH
l.BI
1
:2.13
BINt·U" SC
DINI'II:
CLRA
I\SC
NOP
XIS
JI'
ININ
AISC
JI'
el.RA
~
m
.....
,TURN ON THE G LINIO
,DINARY INCREMENT OF 1:2 BIT COUNTER
,LOWER FOUR BITS WILL BE DISCARDED
,ONLY TOP BITS USED IN TABLE LOOK UP
,SPEED WOULD BE IMPROVED IF THE ADD WERE
,STRAIGHT LINE CODED-BUT COSTS MORE CODE
BINPLI
,READ IN3 TO SEE IF COMPARATOR CHANOED
a
END
,II'
ENII:
INCR
0
,TURN OFF THE G LINE AND DISCHARGE C
,DO ARITHMETIC HERE OR LOOK UP TABLE OR WHATEVER IS
,REQUIRED--SAMPLE LOOK UP TABLE CONTROL INDICATED BELOW
,SAMPLE TABLE WRITTEN CORRECTING FOR THE EXPONENTIAL
,RELATIONSHIP.
THE TADLE ALSO INCORPORATES A CONVERSION
,TO BCD.
THE VALUE IN THE TABLE IS THE RATIO OF
,THE CAPACITOR VOLTAGE V TO THE MAXIMUM VOLTAOE VMAX.
,THE NUMBER IS A TWO DIGIT BCD FRACTION.
WE ARE USING
,A , BIT COUNT IN THIS EXAMPLE.
ADDRESSING ARBITRARILY
I SET UP ASSUMINO THAT CONTROL CODE IS IN PAGE 0 (OTHER
I THAN AT ADDRESS 0) AND THAT THE TABLE THEREFORE IS IN
,PAGE 1 (STARTING AT HEX ADDRESS 040).
001
,
LDI
XDS
AISC
POINT TO TOP 4 BITS
,TOP 4 IN A. POINTING TO LOWER 4 IN :2. 14
,THIS MERELY ADJUSTING FOR ADDRESS--NO
,OTHER FUNCTION
LQID
,DO THE LOOK UP
CQMA
,FETCH THE ADJUSTED VALUE FROM Q
, THE ADJUSTED VALUE IS NOW IN A AND M.
FROM THIS POINT MAY
,USE THE VALUE IN OTHER CALCULATIONS OR OUTPUT THE INFORMATION.
,OR WHATEVER MAY BE REQUIRED BY THE APPLICATION.
LBI
:2.13
,CLEAR THE COUNTER
STII
STII
aTII
,)1'
·
·
·
·
·
·
·
·
·
I
0
0
0
RCAD:, JUMP BACK AND REPEAT
~X
'040
,SET UP TABLE ADDRESS
WORD 000.003.006. ooa ,SET UP THE TAIlLE VALUES
WORD 011.014.016.019 ,HERE. COMPENSATED FOR EXPONENTIAL
WORD 0:21.0:23.026. 02a I AND CONVERTED TO BCD FRACTION
WORD 030.03:2.034.036 ,TABLE VALUE IS RATIO V/VNAX
WORD 038.039.041.043
WORD 045. 046. 048.049
WORD O:U. 05:2. 0'3. 0'5
WORD 056.057.059.060
TLlDD/6935-55
FIGURE 2A. Typical RC Charge AID Code
TLlDD/6935-2
FIGURE 2B. Charge Flow Chart
3-19
,....
w
bz
a..
oo
A more general problem is that of the tolerance of RC time
constant. The value of the voltage with respect to time is
obviously related to the RC value. Therefore, a change in
that value will result in a change in the voltage for a given
time period t. The graph in Figure 3 illustrates the effect of a
± 10% variation in the RC value upon the voltage measured
for a given time t. If one cares to work out the math, it
comes out that the error is an exponential relationship in
much the same manner as the capacitor voltage itself. The
maximum error induced for ± 10% RC variation is ± 3.9%.
Remember also that we are measuring time. Therefore variation in the RC value will have a direct, linear effect on the
time required to measure a given voltage. It is also necessary that the time base for the COP420 be accurate. A variation in the accuracy in the operating frequency of the
COP420 will have a direct impact on the accuracy of the
result.
Given the errors mentioned so far and assuming that no
changes are made in the hardware, the accuracy of the
technique then is determined by the resolution of the time
measurement. This is improved in two ways: increase the
RC time constant so that there is a smaller change in capacitor voltage for a given time period or try to minimize the
loop time required to increment the counter. Lengthening
the RC time constant is easier but the cost is increased
conversion time. The minimum time to increment a 5 to 8 bit
binary counter and test an input is 13 cycle times. For a 9
to 12 bit binary counter this minimum time is 17 cycle times.
Note also that the minimum time to perform the function
does not necessarily correspond to the minimum number of
code words required to implement the function. At a cycle
time of 4 p.s, the 13 cycle times correspond to 52 p.s.
2.2 ACCURACY IMPROVEMENTS
Several options are available if it is desired to improve the
accuracy of this method. Three such improvements are
shown in Figure 4. Figure 4A is the smallest change. Here a
pull up resistor has been added to the G output line and the
G line is run open drain internally, Le., the internal pullup is
removed. This improves the "bounce" problem mentioned
earlier. The G line will go to the high state and remain there
with this setup. However, the addition of the resistor does
little more than eliminate the bounce. The degree of improvement is not great, but it is an easy way to eliminate a
minor source of error.
Figure 48 is the next step. A 74C04 is used as a buffer. The
74C04 was chosen because of its symmetric output characteristics. Any CMOS gate with such characteristics could be
used. The software can easily be adjusted to provide the
proper polarity. The COP420 output drives a CMOS gate
which in turn drives the RC network. This change does
make significant improvements in accuracy. With a light
3.5
% error in measured voltage (for a given
period) as a result of a ±10% variation in
RC value
2.5
1.5
w
a
~
CI
>
53
a:
.5
::I
~
2
::E -.5
2:
a:
~
a:
2.2 2.4 2.6 2.B 3 3.2
t/RC-CALCULATED (NO ERROR FACTOR)
-1
w
~-1.5
-2
-2.5
-3
-3.5
-4
TL/DD/6935-3
FIGURE 3
3-20
o
load the CMOS gate will typically swing from ground to Vee
and its output level is not as likely to be affected by the
capacitor discharge.
the components in the system and eliminates the need to
add another package to the system.
2.3 CONCLUSIONS
Figure 4C is the best approach, but it involves the greatest
component cost. Here two G outputs are controlling analog
switches. Ground is connected to the RC network to discharge the capacitor, and a positive reference is used to
charge the capacitor. This reference can be any suitable
voltage source: zener diodes, Vee, etc. The controlling voltage tolerance is now clearly the tolerance of the reference.
Precise voltage references are readily obtainable. Figure 4C
also shows an analog switch connected directly across the
capacitor to speed up the capacitor discharge time. When
using this version of the basic scheme, remember to include
~he 'on' resistance of the analog switch connected to VREF
In the RC calculation. Failure to do so will introduce error
into the result.
This approach is an inexpensive way to perform an AID
conversion. However, it is not that accurate. With a 10%
Vee supply and a 10% tolerance in the RC value and 10%
variation in the oscillator frequency the best that can be
hoped for is about 25% accuracy. If a 1% reference voltage
is used, this accuracy becomes about 15%.
a"lJ
z
a-i
m
Under laboratory conditions-holding all variables constant
and using precise measured values in the calculations-the
configuration of Figure 2 yielded 5 bit accuracy over an input
range of 0 to 3.5V. Over the same range and under the
same conditions, the circuit of Figure 48 yield 7 to 8 bit
accuracy. It must be emphasized that these accuracies
were obtained under controlled conditions. All variables
were held constant and actual measured values were used
in all calculations. It is unlikely that the general situation will
yield these accuracies unless adjustments are provided and
a calibration procedure is used. This could defeat the low
cost objective.
Note that the LM339 is a quad comparator. If these comparators are not otherwise needed in the system, they can be
used in much the same manner as the CMOS gate mentioned above. They can be used to buffer the output of the
COPS device and to reset the capacitor, or whatever other
function is required. This has the advantage of fully utilizing
Vee
COP420
Vee
5k
GO
21
~------------o<~~----~
TL/DD/6935-4
TL/DD/6935-5
A
B
Vee
VREF
COP420
GO
21
~------------------------~
C
FIGURE 4
3-21
TLIDD/6935-6
•
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r---------------------------------------------------------------------------------------~
3.0 Pulse Width Modulation (Duty
Cycle) Technique
solving for t1 and t2 we have:
3.1 MATHEMATICAL ANALYSIS
t1 = -RC In[(VA - VO)/(VB - YO)]
The pulse width modulation, or duty cycle, conversion technique is based on the fact that if a repetitive pulse waveform
is applied to an RC network, the capacitor will charge to the
average voltage of the waveform provided that the RC time
constant is sufficiently large relative to the pulse period. See
t2 = -RC In[(VB - V1)/(VA - V1)]
let:
VA = VIN - d1
VB = VIN - d2
Figure 5.
substituting the above, the equations for t1 and t2 become:
In this technique, the capacitor voltage Vc is compared to
the voltage to be measured by means of an analog comparator. The duty cycle is then adjusted to cause Vc to approach the input voltage. The COPS device reads the comparator output and then drives one of its outputs high or low
depending on the result, Le., if Vc is lower than the input
voltage, a positive voltage (V1) is applied to charge the capacitor; if Vc is higher than the input voltage, a lower voltage (VO) is applied to discharge the capacitor. Thus the
capacitor voltage will seek a point where it varies above and
below the input voltage by a small amount. Figure 6 illustrates the capacitor voltage and the comparator output.
t1 = -RC In{[1 - (d1/(VIN - VO»]/
[1 +d2/(VIN - VO»]}
t2 = -RC In{ [1 - (d2/(VIN - V1))]/
[1 -d1/(VIN - V1))]1
the equations reduce by means of the following assumptions:
1. d1
= d2 =
2. iVlN -
d
vol » d
v11 » d
iVlN applying these assumptions, we get the following:
Some mathematical analysis here will be useful to help clarify the technique and to point out its restrictions. Referring to
Figure 6, we have the following:
t1
= -
RC In[(1 + x)/(1 - x)] where x
=
-d/(VIN - YO)
t2 = - RC In[(1 +x)/(1 - y) where y = d/(VIN - V1)
VA = VO + [VB - VO][e**( -t1 /RC)]
because of the assumptions above, the x and y terms in the
preceding equations are less than 1, therefore the following
expansion can be used:
VB = VA + [V1 - VA][1 - e"'( -t2/RC)]
= V1 + [VA - V1][e**(-t2/RC)]
In[(1 + z)/(1 - z)] = 2[z + (z**3)/3 + (z**5)/5 + ... ]
YI-
yo-
TL/DD/6935-8
TL/DD/6935-7
FIGURES
Capacitor Voltage
Comparator Output
Ylr------------------------------
YOr------------------------------
TL/DD/6935-10
TL/DD/6935-9
FIGURE 6
3-22
substituting we have:
t1 = -2RC[x
t2 = - 2RC[y
reason, how close to the references he can allow the input
voltage to go.
+ (x**3)/3 + ... ]
+ (y* *3)/3 + ...]
The next consideration is really just one of simplification. It
is clear that if VO is zero, it drops out of the first equation
and the relationship is simplified. Therefore, it is desirable to
use zero volts as the VO value. The equation then becomes:
under assumption 2 above, the linear term completely
swamps the exponential terms yielding the following result
(after substituting back into the equation):
t1 = 2dRCIVIN - VO)
VIN = V1t2/(t1
t2 = -2dRC/(VIN - V1)
t1/(t1
+ t2)
+ t2)
= (V1 - VIN)/(V1 - VO)
= (VIN - VO)/(V1 - VO)
solving for VIN:
VIN = [t2/(t1
+ t2)] [V1 - VO] + VO
+ t2)] [V1 - VO)
or VIN = V1 - [t1/(t1
It follows from the above results that by measuring the times
t1 and t2, the input voltage can be accurately determined.
As will be seen the restrictions based upon the assumptions
above do not cause any serious difficulty.
General Accuracy Considerations
In the preceding calculations it was assumed that the differential output above and below the input voltage was the
same. If the comparator output is checked at absolutely regular intervals, and if the intervals are kept as small as possible this assumption can be fairly easily guaranteed-at least
to within the comparator offset which is only a few millivolts.
As we shall see, this aspect of the technique presents few, if any, difficulties. In addition, there is an RC network at the input of the comparator. The time constant of
this network must be long relative to the time between
checks of the comparator output. This will insure that the
capacitor voltage does not change very much between
checks and thereby help to insure that the differences
above and below the input voltage are the same.
since x =
m
.....
+ t2).
Finally, we have noted that the difference d must be small. If
the capacitor had to charge or discharge a long way toward
VIN, the nonlinearity of the capacitor charge curve would be
significant. This therefore requires that the conversion begin
with the capacitor voltage close to the input voltage.
Note that the RC value is not part of the equation. Therefore
the accuracy of the time constant has no effect on the result
as long as the time constant is long relative to the time
between checks of the comparator output.
The final point is that the reference voltages, whatever they
may be, must be hard sources. Should these voltages vary
or drift at all, they will directly affect the result. In those
configurations where the references are being switched in
and out, the voltage should not change when it is switched
into the circuit.
3.2 BASIC IMPLEMENTATION
For at least 1% accuracy
+
Z
o-I
It is clear from the equation above that the accuracy of the
result is directly dependent upon the accuracy of the reference voltage V1. In other words, it is not possible to be
more accurate than the reference voltage. If, however, all
that is required is a ratio between the input voltage and the
reference voltage, the accuracy of the reference will not be
a controlling factor provided that the input voltage tracks the
reference. This requires that the input voltage be generated
from the reference voltage in some form, e.g., a voltage
divider with VIN coming off a variable resistance.
The next major approximation has to do with the difference
between the input voltage and either V1 or VO. We have
relied on this difference being much greater than the
amount the capacitor voltage changes above and below the
input voltage. This approximation allows the nonlinear terms
in the logarithmic expansion to be discarded. In practicality,
the approximation means that the input voltage must not be
"close" to either V1 or VO. Therefore, it becomes necessary
to determine how closely the input voltage can approach V1
or VO. It is obvious that the smaller the difference d can be
made, the closer the input voltage can approach either reference. The following calculations illustrate the method for
determining that difference d. Note, using either V1 or VO
produces the same result. Thus V = V1 = VO.
General
< 1.01 x
therefore x < 0.173
d/I(VIN - V)I we have d < 0.1731(VIN - V)I.
x
"'tI
It is obvious by now that the heart of the technique lies in
accurately measuring the times t1 and t2. Clearly this requires that the time base of the COP420 be accurate. Short
term variations in the COP420 time base will clearly impact
the accuracy of the result. In addition to that there is a serious problem in being able to check the comparator output
often enough to get any accuracy and resolution out of simply measuring the times t1 and t2. This problem is circumvented by measuring many periods of the waveform. Doing
this gives a large average, which improves the accuracy and
tends to eliminate any spurious changes. Of course, the
trade off is increased time to do the conversion. However if
the time is available, the technique becomes restricted only
by the accuracy of the external components. Those of the
comparator and the reference voltage are most critical.
therefore:
t2/(t1
o
o
(x* *3)/3
The objective, then, is to measure the times t1 and t2. This
is accomplished in the software by means of two counters.
One of the two counters counts the t2 time; the other counter counts the total time t1 + t2.
Using the same analysis for 0.1 % accuracy in the approximation we get d < 0.054SI(VIN - V)I. By applying this relationship, the RC time constant can be adjusted so that, within the time interval, the capacitor voltage does not change
by more than d V. The user may then select, within
It is necessary to check the comparator output at regular
intervals. Thus the software must insure that path lengths
3-23
•
Y-
LLI
I-
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D.
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o
,-----------------------------------------------------------------------------------------------,
used as it would be too difficult to measure the times t1 and
t2 in a single period. The total time, t1 + t2, is the viewing
window under complete control of the software. This window is a time equal to the total number of counts, determined by desired accuracy, multiplied by the loop time for a
single count. A second counter is counting the t2 time. Special care is taken to insure that all paths through the code
take the same length of time since the integrity of the time
count is the essence of the technique. The full conversion
scheme would use the subroutine in Figure 8. Normally the
subroutine would be called first just to get the capacitor
charged close to the input voltage. The result obtained here
would be discarded. Then the routine would be called a second time and the result used as required.
In the configuration in Figure 7, there is an RC network in
both input legs of the comparator. This is to balance the
inputs of the device. For this reason, R1 = R2. C1 is the
capacitor whose voltage is being varied by the pulse waveform. C2 is in the circuit only for stabilization and symmetry
and is not significant in the result. The comparator tends to
oscillate when the + and - inputs are nearly equal without
capacitor C2 in the circuit.
through the test and increment loops are equal in time. Further it is desirable to keep the time required to increment the
counters as short as possible. A trade off usually comes into
play here. The shortest loop in terms of code required to
implement the function is rarely the shortest loop in terms of
time required to execute the function. The user has to decide which implementation is best for him. The choice will
frequently be governed by factors other than the AID conversion limits.
It must be remembered that we are now dealing with analog
signals. If Significant accuracy is required, we are handling
very small analog signals. This requires the user to take
precautions that are normally required when working with
linear circuits, e.g., power supply decoupling and bypassing,
lead length restrictions, crosstalk, op amp and comparator
stabilization and compensation, desired and undesired
feedback, etc. As greater accuracy is sought these factors
are more and more significant. It is suggested that the reader refer to the National Semiconductor Linear Applications
Handbook and to the data sheets for the various components involved to see what specific precautions should be
taken both in general and for a specific device.
As would be expected, the basic circuit has some difficulties. By far the most serious of these difficulties is the output
level of the G line. To be sure of the high and low level of
this output the levels should be measured. The "1" level will
be between the spec minimum of 2.4V and Vee (here assumed to be 5V). The "0" level will be between the O.4V
spec maximum and ground. With light loads, these levels
are likely to vary from device to device. Furthermore, we
have the same "1" level problem that was mentioned in the
simplest technique: the capacitive load is large and the capaCitor is charging while the output is trying to go to the high
level.
The Base Circuit
Figure 7 shows the diagram for the basic circuit required to
implement the duty cycle conversion scheme. The flow
chart and code required to implement the function are
shown in Figure 8. Note that the flow chart and code do not
change-except for possible polarity change on output to
allow for an inverting buffer-for any of the improvements in
accuracy discussed later. The only exception to this is the
technique illustrated in Figure 10 and the variations there
are minor.
The code and flow chart in Figure 8 implement the technique as described above. The large averaging technique is
3k
20 IN3
COP420
Vee = +5V
VIN = 0 -3.5V
TLIDD/6935-11
FIGURE 7. Basic Duty Cycle AID
3-24
o
There is also a problem with the low level. When the output
goes low, the capacitor begins to discharge through the output device of the COP420. This discharge current has the
effect of raising the "0" level and thereby introducing error.
Note that we are not talking about large changes in the
voltages, especially the low level. Typically, the change will
only be a few millivolts but that can translate into a loss of
accuracy of several bits.
the range of VO (here measured to be 0.028V) to 3.5V (the
maximum specified input voltage for the comparator with Vs
= 5V). Increasing the number of total counts had very little
effect on the result. In the general case, the basic scheme
should not be relied upon for more than 4 bits of accuracy,
especially if one assumes that V1 = Vee and VO = O. As
shall be seen, it is not difficult to improve this accuracy considerably.
o."
Z
o-i
m
.....
Under laboratory conditions-holding all variables constant
and using precise measured values in the calculations-the
circuit of Figure 7 yielded 5 bit ± 1 bit accuracy over
I ATltIJ IS THE FULL CONVERSION SCHEME WRITTEN AS A SUBROUTINE
AHIIJ:
L O l l , 10
I MAKE SURE COUNTERS CLEARED
.JSRP
CLEAR
LOI
2, 10
.JSRP
CLEAR
I PRELOAD FOR TOTAL COUNT = 2048
L O l l , 13
STII
0
A'Wlll:
SNUJ":
STII
STII
0
8
ININ
AIse
8
.lP
SNOOl
LOI
I USING OMG BELOW TO SAVE STATE OF OTHER G
I VALUES IF IT WAS NECESSARV TO DO SO, ELSE USE OGI
IVIN > Vc,DRIVE Vc HIGHER
2
ITHIS CODE STRAIGHT LINED FOR SPEED
I APPLV POSITIVE REFERENCE
; INCREMENT THE SUD COUNTER
SMD
OMG
SC
CLRA
LDI
ASC
NOP
XIS
CLRA
ASC
NOP
XIS
CLRA
ASC
NOP
I READ COMPARATOR--INPUT TO 420
=
IN3
3,0
IDINARV INCREMENT
I WOULD ELIMINATE THESE 4 WORDS IF 8 OIT
I COUNTER OR LESS-HERE SET UP FOR UP TO 12
I COUNTER
01T
X
SNIlOJ:
01 V:
nJ'lI\L:
A'II/1j~!:
CLEAR:
.JP
LOI
RMB
OMG
CLRA
AISC
NOP
AISC
.JP
CLRA
LUI
SC
ASC
NOP
XIS
CLRA
AGC
NOP
XIS
CLRA
ASC
.JP
RET
TOTAL
3.0
2
10
ITHIS PART OF THE CODE MERELV INSURES THAT
I ALL PATHS THROUGH THE ROUTINE ARE EGUAL IN TI
1
DLV
L 13
Ell
; INCREMENT THE TOTAL LOOP COUNTER
I WHEN OVERFLOW, DONE SO EXIT
ATD02
X
.JP
.PAGE
CLRA
XIS
JP
ATDOI
2
CLEAR
RET
TL/DD/6935-45
FIGURE SA. Duty Cycle AID Code
3-25
~
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ATOD1
)
(
TL/DD/6935-12
FIGURE 8B. Duty Cycle AID Flow Chart
Under laboratory conditions, the circuit of Figure BA yielded
the accuracies as indicated below for various total counts.
The accuracy increased with the total count until the count
exceeded 2048. There was no significant increase in accuracy with this circuit for counts in excess of 2048. (Remember that these results were obtained under controlled conditions). We may then view the results obtained with 2048
counts as the upper limit of accuracy with the circuits of
Figure BA. The results were as follows:
Total
Resultant Accuracy
Count
8 ± 1/2 bits
512
9 ± 1bits
1024
9 ± 1/2 bits
2048
9 ± 1/2 bits
4096
3.3 ACCURACY IMPROVEMENTS
General Improvements
Figure B illustrates circuit changes that will make significant
improvements in the accuracy of the technique. In Figure BA
a CMOS buffer is used to drive the RC network. The output
of the COP420 drives the CMOS gate, which here is a
74C04 because of its output characteristics. The main thing
that this technique does is to reduce the difficulties with the
output levels. Typically, VO is OV and V1 is Vee. We also
have a "harder" source for the voltages - the levels don't
change while the capacitor is charging or discharging. Now,
even more clearly than before, the accuracy of Vee is the
controlling voltage tolerance. The accuracy of the result will
be no better than the accuracy of Vee (for a system requiring absolute accuracy).
3-26
o
o"'C
Z
23 02
Vee
Vee
~
m
COP420
Vee
TL/DD/6935-13
A
V1
VO
23 G2
'IIC04066
COP420
20 IN3
VIN
Vee
Vee
TL/DD/6935-14
B
Vee
VO
VI
•
COP420
TL/DD/6935-15
c
FIGURE 9. Improvements to Duty Cycle AID
3-27
,....
W
I-
oZ
D.
o
o
The circuit of Figure 98 makes a significant change to improve accuracy. Now the COP420 is controlling analog
switches and switching in positive and negative references.
Therefore the accuracy of the reference voltages is the controlling factor. Generally this will improve the accuracy over
that obtained with Figure 9A. With the circuit of Figure 98,
with VO = 1V (negative reference), and V1 = 3V (positive
reference), 9 bit accuracy was achieved with a total count of
1024. VO and V1 were arbitrarily chosen to place the input
voltage approximately in the center of the allowable comparator input range with Vs = 5V. Remember, the accuracy
of the references is controlling. The result can be no more
accurate than the references. Furthermore, these references must be hard sources; i.e., they must not change
when they are switched into the circuit as that contributes
error into the result.
Figure 10 illustrates a further refinement of the basic approach. This configuration can be used if greater accuracies
are needed. The major change is the addition of a summing
amplifier to the circuit for the purpose of adding a fixed offset voltage to the input voltage. This has the effect of moving the input voltage away from the negative reference
(which is OV here). This offset voltage should be stable as
the changes in it will directly affect the result. The offset
voltage should be chosen so as to place the effective input
voltage (the voltage at the comparator input) approximately
in 'the center of the rang'e between the two references. The
precise valuebf the offset is not critical nor is its source.
The forward voltage drop across a germanium diode is used
as the offset in Figure 10, but this offset can be generated in
any Qonvenient manner. The forward voltage drop of the
germanium diode is approximately O.3V. Given this and the
negative relfe'rence of OV and a positive reference of 2.5V,
the input voltage is restricted to a range of 0 to 2V. Therefore, the effective input voltage (at the comparator input) is
approximately O.3V to 2.3V - well within the limits of the
tWo references. The circuit also includes provision for an
autozero self calibration procedure.
In Figure ge, capacitive feedback was added to the comparator circuit and the series resistance to VIN was decreased.
The feedback added hysteresis and forced the comparator
to slew at its maximum rate (significant errors are introduced
if the comparator does not change state in a time shorter
than the cycle time of the controller). Both of these changes
resulted in increased accuracy of the result. With VO = 0;
V1 = 5V (Vee> and Vee held steady at 5.000V, an accuracy
of 10 bits ± 1 bit was achieved over the input range of 0 to
3.5V.
Note that the resistors in the summing amplifier should be
matched. The absolute accuracy of these resistors is not
significant, but their accuracy relative to one another can
have a significant bearing on the result. The restriction is
imposed so that the output of the summing amplifier is exactly the sum of the input voltage and the offset voltage.
This requires unity gain through the amplifier and that the
It is obviously possible to use any combination of the configurations in Figure 9 for a given application. What is used will
depend on the user and his specific requirements.
TL/DD/6935-16
"Resistors should be matched
Vee = +5V
os; VIN s; 2V
FIGURE 10. Improved Duty Cycle AID with Autozero
3-28
o
tying the input to ground and measuring the result. Thus the
system offsets can be calculated, stored and subtracted
from the result. This improves the accuracy and is also more
forgiving on the choice of the comparator and op amp selected. Furthermore, the offset can be periodically recomputed by the COP420 thereby compensating for drift in system offsets. Nonetheless, the accuracy of the reference is
the controlling factor. It is NOT possible to obtain an absolute (as opposed to ratio metric) accuracy of 12 bits without
a reference that is accurate to 12 bits. The LM136 used in
Figure 10 is a 1 % reference. Although not inherently accurate to 12 bits, the voltage of the LM136 may be trimmed to
exact value by means of a variable resistor. The data sheet
of the LM136 illustrates this connection. Under laboratory
conditions, the circuit of Figure 1 yielded 11 bit ± 1 bit accuracy with a total count of 4096 over the input range of 0 to
2V. Figure 11 indicates the flow chart and the code required
to implement the technique of Figure 10.
impedance in each summing leg be the same. These effects
can become very serious if one is trying for significant accuracy-e.g., if 12 bit accuracy is being sought 1% matching
of those resistors can introduce an error of 1 % maximum.
While 1 % accurate is fairly good, it is significantly less than
12 bit accuracy. Related to this effect is a possible problem
with the source impedance of the input voltage. If that impedance is significant in terms of its ratio to the summing
resistor, errors are introduced just as if the resistors are
mismatched. "Significant" is determined in terms of the desired system accuracy and the relative impedance values.
The comparator section is using some feedback to provide
hysteresis for stability and a low series resistance is used
for the input to the comparator.
Most significantly, this configuration allows a true zeroing of
the system. Through the additional analog switches shown,
the COP420 can easily perform an autozero function by
a"0
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a-I
m
.....
iCODE FOR IMPROVED A TO 0 PULSE WIDTH METHOD
FIGURE SA FOR CODE FOR ROUTINE ATOD
,ISEE
Alfl i'H~: LDI
RMD
JSR
JSR
LDI
XI+U:
LD
XIS
JP
3,0
3
ATOD
ATOD
2.13
1
i DO AUTO ZERO. 3. 0 CONTAINS G STATUS
iSET UP TO GRND INPUT ~ MEASURE OFFSET
iFIRST TIME IS TO GET CLOSE
iMEASURE THE OFFSET
iNOW SAVE THE OFFSET VOLTAGE
i SAVE THE OFFSET VALUE 1 N M3
1
XFER
Lin
0,0
dP
MH\!;un:
SAVi·:
D)N~;lIn:
BN!;lIH~~:
INPUT
I NOW DO REAL MEASUR (1ST TIME IS OFFSET>
JSR
ATOD
iFIRST TIME TO GET CLOSE
JSR
ATOD
iNOW REAL MEASUREMENT
JSRP
BINSUB iSUDTRACT THE OFFSET
I HAVE THE VALUE AT THIS POINT(IN BINARY)-NOW DO WHAT
iTHE APPLICATION REGUIRES.
VALUE MUST BE MULTIPLIED
iBY (VREF+/TOTAL COUNT) TO GET FINAL VALUE IF SUCH IS
i DESIRED
LBI
1.0
i INCREMENT COUNTER FOR NEW OFFSET MEASURE
LD
AISC
1
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SAVE
X
i IS 16TH TIME. MEASURE OFFSET AGAIN
,JP
AUTZER
X
LUI
5MB
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. PAGE
LBI
SC
LD
CASC
NOP
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RET
3.0
3
MEASUR
I
SET BIT SO CAN MEASURE VIN
2
3. 13
1
BNSUB2
TL/DD/6935-46
FIGURE 11A. Duty Cycle A to D, Improved Method
3-29
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TLIDD/6935-18
Vl\
vco~
(
MEASUR
I---tref-/-tx-I
(t1)
t
TL/DD/6935-19
FIGURE 12. Dual Slope Integration-Basic Concept
Ix =
dV
Vtt
=
Vx /R
dv
Vx = RCtt
T1
f
°
Vxdt =
fV
° RCdV
VxT1 = RCV
V = Vx T1/RC = IxT1/C
Similarly:
dV
IREF = Cdt = VREF/R
dV
VREF = RVtt
f
T1 + Tx VREFdt =
T1
fO RCdV
v
VREFTx = -RCV
V = -VREFTx/RC
-VREFTx/RC = VxT1/RC
Vx = - VREFT x/T1
Two important facts arise from the preceding mathematics.
First of all, there is a linear relationship involved in determining the unknown voltage. Secondly, the negative sign in the
final equation indicates that the reference and the unknown,
relative to some point (which may be OV or some bias voltage), have opposite polarity. Thus, if it is desired to measure
to + 5V, the reference voltage must be - 5V. If the input is
restricted to 2.5 to 5V, the reference can be OV as the integrator and comparator are biased at + 2.5V (then the OV is
in fact - 2.5V relative to the biasing voltage, and the input
range is 0 to 2.5V relative to the same bias voltage).
TL/DD/6935-17
FIGURE 11B. Flow Chart for Improved Duty Cycle AID
4.0 Dual Slope Integration
Techniques
o
4.1 Mathematical Background
(Some of this background information is taken from National
Semiconductor Linear Applications Note AN-155. The reader is referred to that document for other related general
information.)
There are some difficulties with dual polarity conversion using the dual slope method. It is clear from the math above
that if the input voltage will be dual polarity, it is necessary
to have two references-one of each polarity. The midrange
biasing arrangement briefly described above eliminates
The basic approach of dual slope integration conversion
techniques is to integrate a voltage across a capacitor for a
fixed time, and then to integrate in the other direction with a
known voltage until the starting point is reached. The ratio
of the two times then represents the unknown voltage.
Some of the math below in conjunction with Figure 12 will
illustrate the approach.
3-30
o
the need for two different polarities but does not help very
much since two references are still required-one at the
positive value and one at the bias value. Ground is the other
reference. Further, the need to select one of two references
further complicates the circuitry involved to implement the
approach. Also, the dual requirement brings up a difficulty
with the bias currents of the integrator and comparator.
They could add to the slope in one polarity and subtract in
the other.
4.2 THE BASIC DUAL SLOPE TECHNIQUE
Figure 13 indicates an implementation of the basic dual
slope technique. This is a single polarity system and thus
requires only the single reference voltage. The circuit of Figure 13 is perhaps not the cheapest way to implement such a
scheme but it is representative and illustrates the factors
that must be considered.
Consider first the means of initializing the integrating capacitor C1. The routine here connects the input to ground and
does a conversion on zero volts as a means of initialization.
Subsequently-and this is typical of the more usual technique-two conversions are performed. The first conversion
is to initialize the capacitor. The second conversion yields
the result. Some form of initialization or calibration procedure is required to achieve optimum accuracy from dual
slope conversion schemes.
The only real operational difficulty in dual slope systems is
establishing the initial conditions on the integrating capacitor. If this capacitor is not at the proper initial conditions,
accuracy will be severely impaired. Figure 12 indicates a
switch across the capacitor as a means of initializing it. In a
software driven system, the initialization can be accomplished by doing two successive conversions. The result of
the first conversion is discarded. It is performed only to initialize the capacitor. The second conversion produces the
valid result. One need only insure that there is not significant
time lapse between the two conversions. They should take
place immediately after one another.
This approach obviously lengthens conversion time but it
eliminates many problems. The alternative to this approach
of two successive conversions is to take a great deal of care
in insuring the initial state of the integrating capacitor and in
selecting op amps and comparators with low offsets.
o"tJ
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The comparator in this circuit is used in the inverting mode
and has positive feedback as recommended in the LM111
data sheet. The voltage reference is the LH0070, which is a
0.01 % reference. A resistive voltage divider on the IH0070
creates the 5V value. The use of the voltage divider brings
up two difficulties (which can be overcome if the LH0070 is
used at its full value, thus eliminating the divider, and the
result properly scaled in the microcontroller or series integrating resistor increased). First, the impedance of the reference must be small relative to the series resistance used in
the integrator. If this were not the case, the slopes would
21
Vs
VIN
0...;+----......._-+---t--+-"-1
10
COP420
100k
>-_-...;;.20"'!IN3
•
-Vs
500k
Vs = +15V
-vs = -15V
vcc = +5V
100k
VIN = OTO -5V
TLIOO/6935-20
FIGURE 13. Basic Dual Slope Integration AID Scheme
3-31
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a.
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Figure 14 shows the flow chart and code required to implement the basic dual slope technique as shown in Figure 13.
Under laboratory conditions an accuracy of 12 bits ± 1 bit
was achieved. The method is slow, with the maximum conversion time equal to 2 x T REF. Notice that the accuracy of
Vee and that of the integrating resistor and capacitor are
not involved in the accuracy of the result. The accuracy of
VREF is, of course, controlling if absolute accuracy-rather
than ratiometric accuracy-is desired. The absolute accuracy of the circuit can be no better than the accuracy of the
reference. If ratio metric accuracy is all that is required, there
is no particular problem. The accuracy is merely relative to
the reference. The Rand C values do not impact the accuracy because the integration in both directions is being done
through the same Rand C. Results would be quite different
if a different value of R or C was used for one of the slopes.
show an effect due to the difference in the R value between
the applied reference voltage and the unknown input. (By
the same token, the output impedance of the source supplying the unknown must also be small relative to that series
integrating resistor). Secondly, the bias currents of the integrator may be such as to affect the reference voltage when
it is coming from a simple resistor divider. Both problems
are reduced if small resistor values are used in the divider.
Note also that current mode switching would reduce the
problem as well. It should be pointed out that the errors
introduced by these problems are not gross deviations from
the expected value. They are small errors that will not make
much difference in the majority of applications. They are,
however the kind of errors that can make the difference
between a system accurate to 10 bits and one accurate to
12 bits (assuming all other factors are the same).
DlIl !.I .': 00 I
LOI
1
I HOLD THE I NPUT TO GROUND TO RESET THE
2.11
I INTEGRATING CAPACITOR
~SRP
CLEAR
I CLEAR THE COUNTER
~SR
INCRA
ITO GET US CLOSE. NEXT READING IS REAL
CI H"(~': LI3 I
2. 11
I NOW CLEAR THE COUNTER
~SRP
CLEAR
I MAKE SURE COUNTER CLEARED TO ZERO
I J. 1~
0 AND START AT 1.13 FOR COUNT = 4096
I J,J:,
14 AND START AT 1,12 FOR COUNT
8192
I J,J!. = 12 AND START AT 1,12 FOR COUNT = 16384
j HIU OW SAME PATTERN FOR OTHER COUNTS
MI·fI('lIH:
INCRA
I RUN THRU THE INCREMENTS
I NOW HAVE THE BINARY VALUE, USE IT AS IS OR
MULTIPLY BY (V,'eflTOTAL COUNT> TO CREATE THE VOLTAGE
I RESULT--THEN CONTINUE WITH THE OPERATION
LBI
2,11
~SRP
CLEAR
ICLEAR THE COUNTER
JSR
INCRA
ITO GET CAP CLOSE TO 0 AGAIN
~P
CLEAR2
i HII.L OWING SUBROUTINE INCRA IS THE REAL PART OF THE ROUTINE
I (:(IN(;FRNED WITH THE COUNTING FOR THE CONVERSION.
IN(;lh'\: LBI
1,15
I R1 IS CLEARED PRIOR TO START
STII
15
I PRESET THE COUNTER FOR 4096
OGI
4
I APPLY VIN
IN>-------IIN
L7
MSB
IN
V
TL/DD/6935-33
V,No-
TLIDD/6935-32
FIGURE 23A. Basic Parallel Implementation
I
I
I
CONYIH:
B BIT SUCCESSIVE APPROXIMATION--BASIC SCHEME
COMPARATOR INPUT TO COP = IN3
OUTPUTS TO D TO A ARE L7 THRU LO WITH L7 .. MSB. LO .. LSB
LSI
o
LEI
4
OUTPUT
SC
CLRA
LSI
ASC
NOP
XIS
JP
Ollll'll1:
2.14
STU
STU
JP
INCI!:
PI USJ:
FIGURE 23B. Basic Serial Implementation
LSI
LD
XDS
CAMQ
JSR
I
SET THE RESULT VALUE TO ZERO
I
ENABLE THE L PORT AS OUTPUTS
I
ROUTINE FOR INCREMENTING THE RESlILT VALUE
o
2.14
PLUS1
2.15
DELAY
• SEND THE RESULT VALUE. STORED IN 2,15-2.14 TO
I Q AND THEREBY OUT THROUGH L
THIS IS ANY CONVENIENT ROUTINE 10 MAKE SURE
THAT THE COP DOES NOT TEST THE COMPARATOR UNTIL
• THE D TO A CONVERTER HAS HAD ENOUGH TIME TO DO
• THE CONVERSION--THE AMOUNT OF TIME REQUIRED
• IS CLEARLY DEPENDANT UPON THE 0 TO A CONVERTER
• USED
I NOW READ THE COMPARATOR INPUT TO COP
I COULD SAVE A WORD IF USE G LINE AS INPUT
I INPUT VOLTAGE STILL :> CONVERTED ANALOG VOL TACE
I
I
ININ
AISC
JP
8
INCR
• CONVERSION DONE AT THIS POINT--THE COMPARATOR HAS CHANGED STATE
• HENCE. CONVERTED ANALOG VOLTAGE:> INPUT VOLTAGE--SO STOP
TLIDD/6935-51
FIGURE 24A. Code for Basic Approach of Successive Approximation
3-40
o
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--
TLIDD/6935-34
FIGURE 24B. Basic Approach, Successive Approximation
18 BIT BINARY SEARCH SUCCESSIVE APPROXIMATION
I INPUT TO COP IS IN3. L BUS IS OUTPUT TO D TO A. L7"'MSD. LO-LSB
I COMPARATOR-O WHEN D TO A VOLTAQE > VIN. OTHERWISE - 1
BINt;/(Il:
LBI
3.14
I SET INCREMENT - MAX VALUE/2(WILL BECOME
STU
0
I MAX VALUE/4 BEFORE FIRST USE)
STII
8
LOI
2.14
I SET INITIAL VALUE OF RESULT TO MAX VALUE/2
STII
0
STU
8
LEI
4
I ENABLE THE L BUS AS OUTPUTS
LD I
1. l '
I NOW SET UP THE B IT COUNTER-OVERFLOW WHEN a BITS
CLRA
AISC
9
I DO IT THIS WAY FOR COMPATIBILITY WITH INCREMENT
011'11'111: X
3
I SAVE THE BIT COUNTER VALUE AND POINT TO RESULT
LD
XDS
I SEND THE RESULT TO Q AND HENCE TO L
CAMQ
DIVIJ)[.: LBI
3. l'
I DIVIDE THE INCREMENT VALUE' BY 2. CAN BE DONE
DIVA:
LD
I IN SEVERAL WAYS SINCE THIS IS A VERY SPECIAL
AISC
8
I PURPOSE DIVIDE FUNCTION
.JP
DIVI
I ALSO. DO THE DIVIDE HERE TO OIVE THE D TO A TIME
STI I
4
I TO DO THE DIOITAL TO ANALOO CONVERSION
.JP
TEST
DI\l1:
AISC
4
.JP
DIV2
STU
2
TEST
.JP
Dllor.!:
AISC
2
.JP
DIV3
STU
1
.JP
TEST
DIV3:
LBI
3.14
AISC
1
.JP
DIVA
STU
8
STU
0
I DEPENDINO ON THE D TO A USED. MAY NEED MORE DELAY HERE
I MUST BE SURE THE RESULT IS STEADY BEFORE TEST THE COMPARATOR
Tl:'tn:
LBI
3.14
ININ
AISC
S
I COULD SAVE A WORD IF USED 0 LINE AS INPUT
.JP
INCR
DJ,CH:
SC
I INPUT LESS THAN D TO A CONVERTED VOLTAOE
sua:
LD
I SUBTRACT THE INCREMENT VALUE FROM RESULT
CASC
NOP
XIS
1
.JP
SUB
.JP
BITPLI
INCH:
RC
I INPUT> D TO A CONVERTED VOLTAOE
AIm:
LD
I ADD THE INCREMENT VALUE TO RESULT VALUE
ASC
NOP
XIS
1
.JP
ADD
Blll'l. 1: LBI
1. l '
I NOW INCREMENT BIT COUNTER TO SEE IF DONE
LD
AISC
.JP
OUTPUT
I CONVERSION DONE AT THIS POINT
TLIDD/6935-52
FIGURE 25A. Binary Search Successive Approximation Code
3-41
TL/DD/6935-35
FIGURE 25B. Binary
Search Successive
Approximation Flow Chart
•
~ r---------------------------------------------------------------------------------~
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6.2 SOME COMMENTS ON RESISTOR LADDERS
Figure 268 results. From this it is only a small step to create
the standard R-2R network. The analysis is the same as
done previously.
If the user does not wish to use one of the standard digital
to analog converters, he can always build one of his own.
One of the most standard methods of doing so is to use a
resistor ladder network of some form. Figure 26 illustrates
the basic forms of binary ladders for digital to analog con·
verters. The figures also show the transition from the basic
binary weighted ladder in Figure 26A to the standard R-2R
ladder Figure 26C.
There is absolutely no restriction that the ladders must be
binary. A ladder for any type of code can be constructed
with the same techniques. Ladders comparable to Figures
26A and 268 are shown in Figure 21 for a standard 8421
BCD code. With the BCD code, the input must be consid·
ered in groups of digits with four bits creating one digit. This
is the direct analog of 1 binary digit per unit. We need four
inputs to create one decimal digit. Thus the resistor values
in each decimal digit are 10 times the values in the previous
decimal digit just as the resistor value for each successive
binary digit was twice the value for the preceding binary
digit. Note that this analysis can be easily extended to any
code. The termination resistance is calculated in the same
manner-assume the decimal digit groupings extend out to
infinity. It can be shown that the resistance of the ladder at
point X in Figure 21A is 480R. Thus Figure 21A represents
the basic 8241 BCD ladder for three digit BCD number. This
termination resistance will vary with where it is placed. Basi·
cally this resistance is equal to nine times (for a decimal
ladder) the parallel resistance of the last digit implemented.
(This relation can be shown mathematically if one desired,
the multiplier is a function of the type of ladder used-multi·
plier = 1 for binary systems, 9 for decimal systems, etc.)
Thus the termination resistance would be 48R if the network
were terminated after the 2nd digit and 4.8R if the network
were terminated after the 1st digit implemented. In
Consider Figure 26A. The choice of the terminating resistor
is made by hypothesizing that the ladder were to go on ad
infinitum. It can then be shown that the equivalent resist·
ance at point X in that figure would be equal to 128R, the
same value as the resistor to the least significant bit output.
This fact is used to create the intermediate ladder of Figure
268. This step is done because it is usually undesirable to
have to find the multitude of resistor values required in the
basic binary ladder. Thus, the modification in Figure 268
significantly reduces the number of resistor values required.
As stated earlier, the resistance looking down the ladder at
point X in Figure 2 is equal to the resistor connected to the
binary output at that point; here the value is 2R. Remember·
ing the objective is to minimize the number of different val·
ues required, if we simply use the same R-2R arrangement
as before with a termination of 2R we get an effective resist·
ance at point Y of Figure 268 or O.5R. This means that a
serial resistance of 1.5R is required to maintain the integrity
of the ladder. If we carry this on through 8 bits, the circuit of
2R
VOUT
1.5R
27
26
VOUT
2R
2R
1.5R
25
2R
24
1.5R
2R
Y
23
2R
22
2R
":'
21
2R
2R
2°
TL/DD/6935-36
A
B
FIGURE 26. Binary Ladders
3-42
C
C')
Figure 278 we are attempting to use only the resistor values
for one decimal digit. This means that the last terminating
resistor must be a 4.8R by the analysis above. Thus at point
X in Figure 218 we must have an equivalent of resistance of
4.8R. The equivalent resistance at point Y of Figure 218,
looking down from the ladder, is O.48R. Thus the other series resistance must be 4.32 R (4.8R-0.48R). Thus the network of Figure 278 results.
complexities caused by the fact that the analog to digital
conversion is being performed on a voltage source that
changes nonlinearly, for example a thermistor temperature
probe. By using the properly designed ladder network, the
nonlinearity can effectively be eliminated from consideration
in the code implementation of the analog to digital conversion.
One final note is of some interest. The ladders may be readily constructed for any type of code to create the analog
voltage. Note that there is no restriction that the code, or
the ladder network, be linear. Thus, effective use of ladder
networks may significantly reduce system difficulties and
'
"
'
r
r
2R
4
4R
m
The accuracy of ladders is a direct function of the accuracy
of the resistors and the accuracy of the voltage source inputs. This is obvious since the analog voltage is in fact created by means of equivalent voltage dividers created when
the various inputs are on or off. It is also essential that the
ladder sources be the precise same value at all inputs to the
ladder network. If this is not the case, errors will be introduced. In addition, the output impedance of the voltage
source should be as small as possible. The success of the
ladder scheme depends on the ratios of the resistance values. Inaccuracies are introduced if those ratios are disturbed. Some possible implementations of the successive
approximation approach with a ladder network used for the
digital to analog conversion are indicated in Figure 28.
Generally, ladders can be very effective tools when understood and used properly. They can be significantly more
involved than indicated here. There are a number of texts
and articles that cover the subject very nicely and the reader is referred to them if more information on ladder design,
the use of ladders, and advanced techniques with ladders is
desired.
MOST
SIGNIFICANT
DECIMAL
DIGIT
o
z
o"
-t
MOST
SIGNIFICANT
DEC~~~~
2
4
2
8R
VOUT
2R
4R
8R
1
10R
mONO
DECIMAL
DIGIT
I:
20R
SEONO
DECIMAL
DIGIT
40R
2
I:
2
2R
4R
8R
80R
1
4.32R
LEAST
SIGNIFICANT
DECIMAL ~CDI
IGI
r
4
100R
200R
400R
LEAST
SIGNIFICANT
DEC~~G~~
2
800R
1
r
4
2R
4R
2
8R
TL/DD/6935-37
B
A
FIGURE 27. 8421 BCD Ladders
3-43
•
....
b
z
LLI
D-
o(.)
ance. With the configuration in Figure 28A, four bit accuracy
is about the best that can be achieved. By being extremely
careful and using measured values, an additional bit of accuracy may be obtained but care must be used. However,
the schematic of Figure 28A is very simple. A"gure 288 represents the next step of improvement. Here we have placed
CMOS buffers in the network. This eliminates the output
impedance and reduces the level problems of the circuit of
Figure 28A. The CMOS buffer will swing rail to rail, or nearly
so. The accuracy of Vee and the resistor network is then
Note that these are functional diagrams. Feedback or hysteresis for comparator stabilization are not shown. The
reader should be aware that his particular application may
require that these factors be considered. Figure 28A is the
simplest scheme and also the least accurate. With little or
no load, the high output level of the L buffer should be very
close to Vee and the low level close to ground. Also the
output impedance of the buffers must be considered. Therefore, rather large resistor values are used-both to keep the
load very small and to dwarf the effect of the output imped-
L3 .....- - - - I 23
L2
22
Ll
2'
LO
ZO
.------.--'~--, 24
JD~~R
(s:tF18~~4)
JO~~R
<------"~."'--------' 23 (s:tF1g~~4)
.-----.--'~--, 22
COP420
TLlDD/6935-38
A
TL/DD/6935-39
B
IN3
27
VOUT
L7
26
L6
25
L5
24
L4
R·2R
LADDER
R lOOk
(SEE FIG. 24)
=
como
23
L3 ..........- -...
1-+_-+......-12 2
L2t-....- -...
TL/DD/6935-40
C
FIGURE 28. Interfaces to Ladder Networks
3-44
controlling. Using 1 % resistors and holding Vee constant,
the user should be able to achieve 7 to a bit accuracy with·
out much difficulty. Remember, however, that Vee is one of
the controlling factors. If Vee is ±5%, there is no point in
using 1% resistors since the Vee tolerance swamps their
effect. Figure 28G is the final and most accurate approach.
Naturally enough, it is the most expensive. However, one
can get as accurate as one desires. Here, an accurate refer·
ence is required. That reference is switched into the net·
work by means of the analog switch. Alternately, ground
may be connected to the input. Now the user need only
consider the accuracy of the reference and the accuracy of
the resistors. However, the on impedance of the switches
must be considered. It is necessary to make this on imped·
ance as low as possible so as not to alter the effective
resistor values.
converters not mentioned here and the user should not
have difficulty in applying these principles to other devices.
It should be pointed out that in almost every instance, the
choice of COP420 inputs and outputs is arbitrary. Obviously,
when there is an a·bit bus it is natural, and most efficient, to
use the L port to interface to the bus. Generally, the Glines
have been used as outputs rather than the 0 lines simply
because the G lines are, in many instances, somewhat easi·
er to control. The choice of input line is also free. If the
interrupt is not otherwise being used, it may be possible to
utilize this feature of IN1 for reading a return signal from the
converter. However, this is by no means required. If there is
a serial interface it is clearly more efficient to use the serial
port of the COP420 as the interface. If a clock is required,
SK is the natural choice.
7.0 "Offboard" Techniques
The ADCOaOO is an a-bit analog to digital converter with an
a·bit parallel output port with complementary outputs. The
ADCOaOO requires a clock and a start convert pulse. It generates an end of conversion signal. There is an output enable which turns the outputs on in order to read the a·bit
result.
The reader is referred to the data sheet for the ADCOaOO for
more information on the device. The circuit of Figure 29
illustrates the basic implementation of a system with the
ADCOaOO. The interface to the COP420 is straightforward.
The appropriate timing restrictions on the control signals are
easily met by the microcontroller.
o
o
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Z
o
-I
m
7.2 ADC0800 INTERFACE
~1GENERALCOMMENTS
This section is devoted to a few illustrations of interfacing
the COP420 to standard, stand alone analog to digital con·
verters. These standard converters are used as peripherals
to the COPS device. Whenever the microcontroller requires
a new reading of some analog voltage, it simply initiates a
read of the peripheral analog to digital converter. As a result, the accuracies and restrictions in using the converters
are governed by those devices and not by the COPS device.
These techniques are generally applicable to other A to D
Vee
10
5 L:
LSB ~1...
3 _ _ _ _1""'"t
Vss
14
........."""'''''''""_15-4 RNET
TOP
AOCOSOO
(MM4357)
5 RNET
........'VV""""--t BOTTOM
14 L1
16
13 L2
17
12 L3
1
8 L4
2
7 L5
6 L6
'""""_ _ _ _...
5 L7
COP420
•
23 02
22 01
-Vo
....._ _ _ _ _9-tIN1
18 SK
Adjust zero adjust
with VIN = -5V
Adjust full scale
with VIN = + 5V
Vee = +5V
-vG = -12V
VIN = -5to +5V
-Vo
TL/DD/6935-41
FIGURE 29. Simple AID with ADC0800
3·45
...w
b
z
D.
oo
Figure 30 is the flow chart and code required to do the
interfacing. As can be seen, the overhead in the COP420
device is very small. The choice of inputs and outputs is
arbitrary. The only pin that is more or less restricted is the
use of SK as the clock for the converter. SK is clearly the
output to use for that function as, when properly enabled, it
provides pulses at the instruction cycle rate.
verter. The interface is not significantly different from that of
the ADC0800, but the ADC0801 famliy are a much better
device. The four control signals are somewhat different, although there are still four control lines. Here we have a chip
select, a read, a write, and an interrupt signal. All are negative going signals. Start conversion is the ANDing of chip
select and write. Output enable is the ANDing of chip select
and read. The interrupt output is an end convert signal of
sorts. The device may be clocked externally or an RC may
be connected to it and it will generate its Own clock for the
conversion. In addition the device has differential inputs
7.3 ADC0801/2/3/4 INTERFACE
The ADC0801 family of analog to digital converters is very
easy to interface and is generally a very useful offboard con-
MF.ABUR: LEI
SC
SlAln2: CLRA
XAS
OGI
OGI
LDI
Rl-.AU)1: IN IN
AISC
.lP
001
INL
0
;FLOAT THE L LINES
2
,MAKE SURE SO STAYS ZERO
;MAKE SURE SK STAYS CLOCK
I SEND START PULSE
0
2.13
14
;WAIT FOR EOC SIGNAL
READ 11
4
I HAVE EOC.ENABLE OUTPUTS
; READ THE L LINES
X
COMP
XDS
COMP
I CREATE PROPER POLARITY
X
OGI
0
; DISABLE ADcoaoo OUTPUT
,HAVE THE RESULT AT THIS POINT--USE IT IN WHATEVER
IMANNER IS REGUIRED BY THE APPLICATION
LDI
2.10
.lSRP
CLRR
.lP
MEASUR
TL/DD/6935-53
FIGURE 30A. A to 0 with ADC0800
TL/DD/6935-42
FIGURE 30B. ADC0800 Interface Flow
3-46
C')
which allow the 8-bit conversion to be performed over a given window or range of input voltages. The reader should refer to the
ADC0801 family data sheet for more information. Figure 31 indicates a basic interface of the ADC0801 family to the COP420.
Again, the interface is simple and straightforward. The code required to interface to the device is minimal. Figure 32 illustrates
the flow chart and code required to do the interface.
...-_ _ _ _-t
1
cs
Vee ...2_0...._
0 Veel
o
"'0
Z
o-t
m
=VREF)
2 RD
G l l - -_ _ _-t
G2
3
IN3
\Vii
5 INTR
VREF/21---0 VREF12
COP420
L7 5
L6 6
11 DB7
12 DB6
L5 7
13 DB5
L4 B
14 DB4
ADC0801
ADC0802
:m:~~
VIN+ ~6_ _-o V
IN+ } DIFFERENTIAL
VIN-I---OVIN-
15 DB3
6 DB2
L2a.;1..;,3_ _ _ _1-t
L3 12
CLK R
INPUT
19
14
17
11 1 - - - - - " "DBI
LO 15
18 DBO
10k
AGND
~ 150pF
TL/OO/6935-43
FIGURE 31. COP42Q-ADCOB01 Family Interface
I
INTERFACE TO NAKED 8
NhKI-IIU: OGI
LUUP:
L(I"";':
LEI
OGI
OGI
OGI
OGI
ININ
AISC
~p
~p
RH\U:
15
LI3I
OGI
OGI
NOP
INL
OGI
a
14
10
14
15
8
READ
LOOP2
0.0
14
12
15
ISET ALL G LINES HIGH(USUALLY DONE AT
IPOWER UP
I TRI STATE THE L LINES FOR READING
I SEND CHIP SELECT LOW(CS BRACKETS OTHER SIGNAL)
ICS LOW AND WR LOW = START CONVERSION
I RAISE WR
iRAISE CS,NAKED 8 IS NOW CONVERTING
IWAIT FOR THE INTR SIGNAL--COULD SAVE THIS TES
i IF USED INl AND THE INTERRUPT FEATURE OF COP4
i INTR IS LOW. DATA IS READY
•
iSET UP RAM LOCATION FOR READ
SEND CS
I SEND CS AND READ = OUTPUT ENABLE
iWAIT-NEED WAIT ONLY 125NS.BUT 1 CYCLE IS MIN
ITIME W~ CAN WAIT
iREAD THE L LINES
iTURN OFF THE NAKED 8--CS AND RD HIGH
i
iDONE AT THIS POINT. DO WHATEVER IS REGUIRED
WITH THE RESULT
TLIOO/6935-54
FIGURE 32A. COP420/ADCOB01 Family Sample Interface Code
3-47
......
w
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(
conversion. This, by itself, restricts most of the techniques
described to about 8-bits accuracy. As was mentioned several times, the greater the accuracy that is desired the more
accurate the external circuits must be. Ten and twelve-bit
accuracies, and more, require references that are accurate.
These get very expensive very rapidly. There is nothing inherent in the COPS devices that prevents them from being
used in accurate systems. The precautions are to be taken
in the system regardless of the microcontroller. The only
problem is that, in those accurate systems where the COPS
device is doing the timekeeping and counting, this increased
accuracy is paid for by increased time to perform the conversion.
Several devices have been used in conjunctions with the
COPS device in the previous sections. It is again recommended that the user refer to the specific data sheets of
those devices when using any of those circuits. It must
again be mentioned that the standard precautions when
dealing with analog signals and circuits must be taken.
These are described in the National Semiconductor Linear
Applications Handbook and in the data sheets for the various linear devices. These precautions are especially significant when greater accuracy is desired.
The COPS family of microcontrollers has shown itself to be
very versatile and powerful when used to perform analog to
digital conversions. Most techniques are code efficient and
the microcontroller itself is almost never the limiting factor. It
is hoped that this document will provide some guidance
when it is necessary to perform analog to digital conversion
in a COPS system.
NAKED B )
T
a..
SEND Cf LOW
o
o
SENDWlfLOW
e!·WR=
START CONVERT
SEND WII HIGH
(e! BRACKETS WIll
SEND "Cf HIGH
I
NO~
= LOW
YES
SEND &SLOW
SEND Ill! LOW
e!.R!i=
OUTPUT ENABLE
READ DATA
SEND~
HIGH
1
{
DONE
l!ii
J
TLIOO/6935-44
FIGURE 32B. COP4201 ADC0801 Family Interface Flow
9.0 References
8.0 Conclusion
Several analog to digital techniques using the COPS family
have been presented. These are by no means the only
techniques possible. The user is limited only by his imagination and whatever parts he can find. The COPS family of
parts is extremely versatile and can readily be used to perform the analog to digital conversion in almost any method.
Generally, those techniques where the COPS device is doing the counting or timekeeping are slow. However, those
techniques are generally slow inherently. The fastest methods are those where the conversion is being done offboard
and the COPS device is merely reading the result of the
conversion when required. Also, an attempt has been made
to illustrate the lower cost techniques of analog to digital
1. "Digital Voltmeters and the MM5330", National Semiconductor Application Note AN-155.
2. Walker, Monty, "Exploit Ladder Network Design Potential". Part One of two part article on ladder networks.
Magazine and date unknown.
3. Wyland, David C., "VFC's give your ADC design high resolution and wide range". EDN, Feb. 5, 1978.
4. Redfern, Thomas P., "Pulse Modulation AID Converter"
Society of Automotive Engineers Congress and Exposition Technical paper # 780435, March 1978.
5. National Semiconductor Linear Applications Handbook,
1978.
6. National Semiconductor Linear Databook, 1980.
7. National Semiconductor Data Acquisition Handbook,
1978.
3-48
o
o
National Semiconductor
COP Note 4
Leonard A. Distaso
The COP444L Evaluation
Device 444L-EVAL
"a
Z
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rn
0I:loo
The 444L·EVAL is a preprogrammed COP444L intended to
demonstrate operating characteristics and facilitate user familiarization and evaluation of the COP444L and the
COPSTM family in general.
The 444L-EVAL has two mutually exclusive operating
modes: an up/down counter/timer or a simple music synthesizer. The state of pin L7 at power up determines the
operating mode.
1.0 THE 444L-EVAL AS A SIMPLE MUSIC SYNTHESIZER
Figure 1 indicates the connection of the 444L-EVAL as a
simple music synthesizer. As the diagram indicates, the
connections required for operation are minimal. The os-
cillator may be a crystal circuit using CKI and CKO; an external oscillator to CKI; or an RC network using CKI and CKO.
As should be expected, the crystal circuit provides the
greatest frequency stability and precision. The RC network
will provide an acceptable oscillation frequency but that frequency will be neither precise nor stable over temperature
and voltage. The external oscillator, of course, is as good as
its source. The frequencies for the various notes and delay
times are set up assuming that the oscillator frequency is 2
MHz. Three modes of operation are available in the music
synthesizer mode: play a note; play one of four stored
tunes; or record a tune for subsequent replay.
...L"J..
Vec
':"
1/AF
4
11
RESET
G2
DO
D1
24
LOWER~
G3
D2
D3
28
27
26
25
c
444L·EVAL
INO
19
c'
>'
IN1
CKI
IN2
CKD
IN3
D
10
>'
20
>'
16
)"
D'
OSCILLATOR
SI
GO
)"
u
21
CKI
':"
CKO
':"
~ CK~CKD
2MHz
"'pF -=
39 PF
1K
0 *56PF
I
-=
•
SPEAKER
200 PF
I
-=
PIElD·CERAMIC
TRANSDUCER
SUGGESTED OSCILLATOR CIRCUITS
CRYSTAL NEtWORK RECOMMENDED FOR
ACCURACY AND STABILITY
TL/DD/6937 -1
FIGURE 1. 444L-EVAL as Simple Music Synthesizer
3-49
~ r-----------------------------------------------------------------------------------~
L&.I
b
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D.
oo
1.A. PLAY A NOTE
mode. (In a "real system" of this type some form of editing
would be desirable. It would not be difficult to add editing
features.)
Twelve keys, representing the twelve notes in one octave,
are labeled "C" through "B". Depressing a key causes a
square wave of the corresponding frequency to output at
GO. The user may drive a piezo-ceramic transducer directly
with this signal. With the appropriate buffering, the user may
use this signal to drive anything he wishes. A simple transistor driver is sufficient to drive a small speaker. The user can
be as simple or as complex as he desires at this point-e.g.
he can do some wave shaping, add an audio amplifier, and
drive a high quality speaker.
Note: The accuracy of the tones produced Is a function of the oscillator
accuracy and stability. The crystal oscillator, or an accurate, stable
external OSCillator is recommended.
2.0. THE 444L-EVAL AS AN UP/DOWN
COUNTER/TIMER
By connecting pin L7 to Vee and providing power and oscillator the 444L-EVAL functions as an 8 digit binary/BCD up/
down counter. In addition, an approximate 1 Hz signal is
produced by the device. The 444L-EVAL can drive a single
digit LED display directly. With the appropriate driver
(COP472, COP470, MM5450/5451) the device can drive a
4 digit LCD, VF, or LED display. Any combination of these
displays can be connected at any given time.
The 444L-EVAL has a range of two and one-half octaves:
the basic octave on the keyboard (which is middle C and the
11 notes above it in the chromatic scale), one full octave
above the basic octave and one-half octave below the basic
octave. The notes in the basic octave are played by depressing the appropriate key (one key at a time-the keyboard has no rollover provisions). A note in the upper octave is played by first depressing and releasing the U SHIFT
key and then depressing the note key. Similarly, a note in
the lower one-half octave is played by first depressing and
releasing the L SHIFT key and then depressing the note
key. Two other shift keys are present: UPPER and LOWER.
All notes played while the UPPER key is held down will be in
the upper octave. Similarly, note F # through B when played
while the LOWER key is held down will be in the lower onehalf octave. The lower octave notes C through F are not
present and depressing any of these 6 keys while the LOWER key is held down or after depressing the L SHIFT key will
play the note in the basic octave.
The binary/BCD and and up/down modes are controlled by
the states of input pins INO and IN2 as indicated below:
INO
INO
IN2
IN2
Pins G2 and G3 provide display control to the user. He can
choose to view either the most significant 4 digits of the
counter or the least significant 4 digits of the counter. Further, the user can disable the update of the 4 digit displays.
The controls are as follows:
1.B. PLAY STORED TUNE
G2 = 1 (Default state) -Enable update of 4 digit
displays
-Disable update of 4 digit
G2 = 0
displays
PLAY 1 -Music Box Dancer
% -Santa
G3 = 1 (Default state) -Display least significant 4
digits of counter
-Display most significant 4
G3 = 0
digits of counter
Lucia
PLAY % -Godfather Theme
PLAY
Va -Theme from Tchaikowsky Piano Concerto
1 (Default state) -BCD counter
0
-Binary Counter
1 (Default state) -Count Up
0
-Count Down
The up/down control may be changed at any time. Changing the binary-BCD control during operation clears the counter before counting begins in the new mode.
The 444L-EVAL can play four preprogrammed tunes. Depressing PLAY followed by "Va", "%", "%", or "1" will
cause one of these tunes to be played. The tunes are:
PLAY
=
=
=
=
#1
The single digit LED display displays the least significant
digit of the counter. (Note, the direct drive capability for the
single digit LED display refers to a small LED digitNSA 1541 A, NSA 1166k, or equivalent.)
1.C. RECORD A TUNE
Any combination of notes and rests up to a total of 48 may
be stored in RAM for later replay. A note is stored by depressing the appropriate key(s), followed by the duration of
the note (V,8 note, % note, 3/18 note, % note, % note, %
note, % note, whole(1) note), followed by STORE. A rest Is
stored by selecting the duration and depressing STORE.
The rests or durations of 1118, 3/18, %, and % are obtained by
first depressing L SHIFT and then %, %, %, or 1 respectively. When the tune is complete press PLAY followed by
STORE. The tune will be played for immediate audition.
Subsequent depression of PLAY and then STORE will play
the last stored tune.
2.A. I/O MODE
The 444L-EVAL has the capability to allow the user to read
or write the 8 digit counter through the L port. In the I/O
mode, the single digit LED display is disabled. The 4 digit
displays are not affected. In this mode pins DO and IN3 are
used for the handshaking sequence. DO is a Ready/Write
signal from the 444L-EVAL to the outside; IN3 is a Write/
Acknowledge from the outside to the 444L-EVAL. Data I/O
is via LO-L3 with LO being the least significant bit. Data is
standard BCD for the BCD counter mode or standard hex
for the binary counter mode. The digit address is on pins
L4-L6 with L4 being the least significant bit. Digit address
Only one tune may be stored, regardless of length. Attempts to store a new or second tune will erase the previously stored tune. There are no editing features in this
3-50
o
o
."
Vec
Z
FILAMENTS
Vec \to
o-f
m
BCD/BINARY
UP/DOWN
L7
INO
Vec CKI CKO
DO
READY/WRITE
IN3
ACK/READY
LO
L1
L2
++_
L3 ~--------_1~~+L4
L5
L6
IN2
t-------.....
GO
G1
DISPLAY
ENABLE/DISABLE
G2
DISPLAY
LEAST/MOST
SID. DIGITS
G3
444L·EVAL
GND
I
DATA I/O
I/O
0l:Io
\tG
SA,SH
01 COP470
CLK
01·04
8
4
4 DIGIT
VF
DISPLAY
(FUTABA
4LT-51A
OR EQUIV.)
RESET
4 DIGIT
LCD
(EPSOM
LD·370
OR EQUIV.)
*1,8
D1
D2
SI
IN1
SK
SO
COUNT IN
-=-
Voo (DISPLAY VOLTAGE)
4 DIGIT
LED DISPLAY
(2 EA. NSN584)
\'l.ED
Vec
TL/DD/6937-2
FIGURE 2. 444L·EVAL In Counter Mode
o is the least significant digit of the counter; digit address 7
is the most significant digit of the counter. The 110 modes
are controlled by pins GO and G1 as follows:
GO
G1
o
o
Output data with handshake, single
digit LED off
o
Input data with handshake, single
digit LED off
Auto output, no handshake, single
o
digit LED on
Default condition, No I/O, single digit
LED displays least significant digit of
counter
is ready to repeat as soon as IN3 goes high again. The
counter digits are output sequentially from least significant
digit (digit address 0) through most Significant digit (digit address 7). The sequence will continuously repeat as long as
this mode is selected.
2.A.2. Input Data with Handshake
The 444L·EVAL will take data supplied to it and load the
counter. The sequence is similar to that described above for
the output mode. The external device(s) supplies both the
data and the digit address where that data is to be loaded.
When sending data to the 444L·EVAL, the external circuitry
must test that the device is ready to receive data (DO high).
Then the data and address should be presented at the L
port. Then the Write signal (lN3) should be driven low. The
444L-EVAL will read the data and then drive DO low. When
DO goes low, the external circuitry should bring IN3 high.
After IN3 returns high, the 444L-EVAL will signal it is ready
to receive data by sending DO high. Note that this sequence
is relatively slow. The 444L-EVAL is performing several operations between successive read operations.
2.A.1. Output Data with Handshake
With this mode selected the 444L·EVAL will output data
with a handshake sequence. Note that the outputting of
data is relatively slow as the device is counting and updating
displays between successive digit outputs.
Before data is output, or the next digit of the counter is
output, the 444L·EVAL must see IN3 (Acknowledge or
ready from the external world high). The Ready/Write pin
(DO) is assumed to be high at this point. With DO high and
IN3 high, the device will output the data and digit address.
After the data and address are output, the DO line-functioning as a write strobe here-goes low. The 444L·EVAL
then expects the Signal at IN3 to go low indicating that the
external world has read the data. When the device sees IN3
go low, DO will be brought high indicating that the sequence
2.A.3. Automatic Output Mode
In the automatic output mode, the Single digit LED is on. It is
not displaying the least significant digit of the counter in this
mode. The display is on so that the user can connect this
LED digit, select the automatic output mode, and observe
the states of the L lines without having to put more sophisticated equipment or circuitry external to the 444L·EVAL.
Segments a through d are pins LO thorugh L3; segments,
3-51
~
LLI
,--------------------------------------------------------------------------------------,
bz
e, f, g are pins L4, L5, and L6. Thus the user can observe
the digit address changing and observe the corresponding
data.
oo
In this mode, the state of pin IN3 is irrelevant. The 444LEVAL sequentially outputs the digits of the counter.
a..
DO goes high when the data and address is being changed.
DO goes low when the data is valid. As in the other lID
modes, the process is slow. There is about 4 to 5 milliseconds between the successive digit outputs.
OUTSIDE
/REAOY
~_~~_ _>C
\
OATAINVALIO
TL/DD/6937-3
FIGURE 3A. Relative Tlmlng-output Handshake
COPREAOY
I
f
DATA
/RECEIVED
JX. .____________.,,::I~-----..JX. .----
ADD:::i _ _ _
IN3
(WRITE STROBE)
-----------,.
\
I
WRITE
(DATA VALID)
'
,J
,..---------
t
TL/DD/6937-4
FIGURE 3B. Relative Timing-Input Handshake
-J/
DO _ _ _ _
\ DATA
INVALID
--JX'-_______r.::~----'X'-------
ADD:::i _ _ _ _ _
TL/DD/6937-5
FIGURE 3C. Relative Timing-Automatic Output
3-52
0
0
3.0 SELECTED OPTIONS
The 444L-EVAL has the following options selected:
GNO
Option 1 =0
CKO
Option 2 =0 CKO is clock generator output to
crystal
CKI
Option 3 =0 CKI oscillator input divide by 32
RESET Option 4 =0 Load device to Vee on RESET
L7
Option 5 =0 Standard output on L7
L6
Option 6 =2 High current LED direct segment
drive on L6
L5
Option 7 =2 High current LED direct segment
drive on L5
L4
Option 8 =2 High current LED direct segment
drive on L4
IN1
Option 9 =0 Load device to Vee on IN1
IN2
Option 10 = 0 Load device to Vee on IN2
Option 11 = 1 4.5V to 9.5V operation
Vee
L3
Option 12 = 2 High current LED direct segment
drive on L3
L2
Option 13 = 2 High current LED direct segment
drive on L2
L1
Option 14 = 2 High current LED direct segment
drive on L1
LO
Option 15 = 2 High current LED direct segment
drive on LO
SI
Option 16 = 0 Load device to Vee on SI
SO
Option 17 = 2 Push-pull output on SO
SK
Option 18 = 2 Push-pull output on SK
INO
Option 19 = 0 Load device to Vee on INO
IN3
Option 20 = 0 Load device to Vee on IN3
GO
Option 21 = 0 Very high current standard output
onGO
G1
Option 22 = 2 High current standard output on
G1
G2
Option 23 = 4 Standard LSTIL output on G2
G3
Option 24 = 4 Standard LSTIL output on G3
03
Option 25 = 0 Very high current standard output
on 03
02
Option 26 = 0
01
Option 27 = 0
DO
Option 28 = 0
Option 29
Option 30
Option 31
Option 32
Option 33
Option 34
Option 35
Option 36
=
=
=
=
=
=
=
=
0
0
0
0
1
0
0
0
Very high current standard output
on 02
Very high current standard output
on 01
Very high current standard output
on DO
Standard TTL input levels on L
Standard TTL input levels on IN
Standard TTL input levels on G
Standard TTL input levels on SI
Schmitt trigger inputs on RESET
CKO input levels, not used here
COP444L
Normal RESET operation
"U
Z
0
.....
m
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4.0 CONCLUSION
The 444L-EVAL demonstrates much of the capability of the
COP444L. It does not indicate the limits of the device by any
means. The 1/0 features were included to demonstrate that
capability. The fact that they are slow is due strictly to the
program. If such 1/0 capability were a necessary part of an
application it could be accomplished much much faster than
was done here. The counter modes are quite versatile and
are generally self explanatory. It was fairly easy to provide a
counter with the versatility of that included here. The music
synthesis mode demonstrates clearly the program efficiency
of the device.
The 444L-EVAL is intended for demonstration. There is no
question that aspects of its operation could be improved
and tailored to a specific application. It is unlikely that this
particular combination of features would be found in any
one application. It is also interesting to note that the program memory in the device is not full. There is still a significant amount of room left in the ROM. This should serve to
make it clear that the capabilities of the device have not
been stretched at all in order to include these demonstration functions.
•
3-53
U)
r---------------------------------------------------------------------------------~
UJ
National Semiconductor
COP Note 5
bz Oscillator Characteristics
D.
o
o
of COPSTM Microcontrollers
The measurements were taken by holding the RESET pin of
the device low and measuring the period of the waveform at
pin SK. In this mode the SK period is the instruction cycle
time. For divide by 4 the oscillator frequency is given by the
following:
Table of Contents
1.0 INTRODUCTION
2.0 RC OSCILLATOR OPTION
4
3.0 CRYSTAL OR INVERTER OPTION
frequency = - S K
.
penod
3.1 COP420/COP402
3.1.1 L, LC, and RLC Networks
3.2 COP420L
3.3 COP410L
3.4 General Notes
4.0 CONCLUSION
1.0 INTRODUCTION
COPS microcontrollers will operate with a wide variety of
oscillator circuits. This paper focuses on two of the oscillator options available on COPS microcontrollers: the internal
RC OSCillator, and the crystal or inverter oscillator. The typical behavior of the RC oscillator with temperature and voltage (and typical values of Rand C) is documented. For the
crystal or inverter option, circuit configurations (RC, RL,
RLG, R, LC, L) are presented which will allow the' microcontroller to operate properly without the use of ceramic resonator or crystal.
The passive components used were inexpensive, uncompensated devices: standard carbon resistors, ceramic or foil
capacitors, and air core or iron core inductors. To provide
reasonably clear data on the characteristics of the microcontroller itself, no attempt at compensation for the external
components was made.
2.0 RC OSCILLATOR OPTION
With the RC oscillator option selected, the graphs in Figures
1 through 6 indicate the variation of the instruction cycle
time of the microcontroller with temperature and voltage.
Typical Rand C values, as recommended in the respective
device data sheets, were used. The graphs are composite
graphs reflecting the worst case variations of the devices
tested. Therefore, the graphs show a percentage change of
the instruction cycle time from a base or reference value.
Where the results are plotted against voltage the reference
is the value at Vee = 5V. Where the results are plotted
against temperature, the reference is the value at T = 20°C.
A positive percent variation indicates a longer instruction
cycle time and therefore a slower oscillator frequency. Similarly, a negative percent variation indicates a shorter instruction cycle time and therefore a faster oscillator frequency.
Measurements were taken at temperatures between - 40°C
and + 85°C and at Vee values between 4.5V and 9.5V.
However, the reader must remember that the COP400 series is specified only between O°C and + 70°C. The reader
must also remember that the COP420 is specified at Vce
levels between 4.5V and 6.3V only. The data here is usable
for the COP300 series, which is specified at the extended
temperature range of - 40°C to + 85°C. However, the reader must keep in mind the generally more restricted Vee
range for some of the various COP300 series microcontrollers.
The graphs in Figures 1 through 6 reflect the variation of the
microcontroller only. The resistor and capacitor were not in
the temperature chamber with the COPS device. Obviously,
the results will be affected by the variation of the Rand C
with temperature. However, this can vary dramatically with
the type of components used. The user will have to combine
the data here with the characteristics of the external components used to determine what type of variation may be expected in his system.
3.0 CRYSTAL OR INVERTER OPTION
With the crystal or inverter option selected on the COPS
microcontroller there is, effectively, an inverter between the
CKI and CKO pins. CKI is the input to the inverter and CKO
is the output. Various passive circuits were connected between CKI and CKO and the results documented. Of the
operational circuits, a subset was tested over temperature
with the microcontroller only in the temperature chamber. A
smaller subset was tested over temperature with both the
microcontroller and the oscillator network in the temperature chamber.
The data with the oscillator network in the temperature
chamber is obviously highly dependent on the particular
components used. This data was taken with standard, inexpensive, uncompensated components. Neither high precision nor high stability components were used. This data is
included only to provide the user with some very general
indication of how the oscillator frequency may vary with
temperature in a real system.
3.1 COP420/COP402
Except for the ROM, the COP420 and COP402 are equivalent devices. The internal circuitry of each device is identical. Therefore, data taken for one of the devices is equally
3-54
applicable to the other. The following discussion will refer to
the COP420 but all such references apply equally well to the
COP402. Similarly, the graphs for the COP420 apply to the
COP402 and vice versa.
within the valid frequency range of the COP420, LC and
RLC networks can be a very effective sUbstitute for a crystal. The only potential problem is that a good RLC, or even
LC, oscillator circuit may not be a cost-effective sUbstitute
for a crystal in a COP420 system. The user will have to
make that determination.
With the crystal option selected, the COP420 oscillator circuitry will readily oscillate with almost any circuit configuration between CKI and CKO. What difficulty there is lies in
finding the network of the device. With the appropriate divide option selected, oscillator frequencies between
800 kHz and 4 MHz are valid for the COP420. No data was
taken for any network that produced an oscillation frequency outside the valid range.
o
o
""C
Z
o
-t
m
U1
3.2 COP420L
The valid input frequency range for the COP420L, with the
appropriate divide option selected, is between 200 kHz and
2.097 MHz. With the crystal option selected the COP420L
oscillated much less readily than the COP420.
The LC networks gave outstanding results with the
COP420L. With the simple two-component LC network
shown in the graphs, holding C at 50 pF and varying L from
200 /LH to 700 /LH gave oscillation frequencies from about
2 MHz to 1 MHz. Holding L at 390 /LH and varying C from 10
pF to 700 pF gave oscillation frequencies of about 2 MHz to
1.6 MHz. Similar results were obtained when a capacitor
was placed in parallel with the inductance.
3.1.1 L, LC, and RLC Networks
Various L, LC, and RLC networks were connected with varying results. Certain networks produced results much more
stable than the RC networks; others were no better than the
RC networks. With a single inductor connected between
CKI and CKO, frequencies between 1 MHz and 4 MHz were
easily obtained. However, the input gate capacitance at CKI
(typically 5 pF to 10 pF) and the series resistance of the
inductance become factors that impact the oscillation frequency and its stability over temperature.
3.3 COP410L
The COP41 OL has a valid input frequency range of 200 kHz
to 530 kHz.
The addition of a capacitor between CKI and ground tends
to reduce the effects of the internal gate capacitance. For
the single L, Single C network of this type, the capacitor
value should be greater than about 50 pF to begin to effectively swamp out the effects of the input gate capacitance.
As might be expected, LC combinations which had their resonant frequencies within the valid COP420 frequency range
produced the best results.
The LC networks also gave very good results. With the simple LC network shown in the graphs, holding L at 4700 /LH
and varying C from 25 pF to 0.003 /LF gave oscillation frequencies of about 460 kHz to 225 kHz.
3.4 GENERAL NOTES
With the crystal or inverter option selected on COPS microcontrollers, a wide variety of networks may be used in place
of the ceramic resonator or crystal.
LC and RLC networks can be used in any of the devices.
Appropriately designed, these networks will provide a stable
oscillation frequency for the microcontroller. The user will
have to allow for the variation of the external components
with temperature when using these networks. The problems
with networks such as these is that they may not be cost-effective alternatives to the crystal or resonator, especially if
high stability, temperature compensated components are
used. The user will have to make the determination of costeffectiveness.
The addition of another capacitor(s) to the basic two-component LC network, as shown in Figure 111.1, produced very
good results. Varying the capacitor values in these networks
- especially those capacitors between CKI and ground and
CKO and ground - provided a great deal of control over
the oscillation frequency. In Figure 111.1, varying C1 from
25 pF to 0.01 /LF produced oscillation frequencies between
about 3 MHz and 1.6 MHz (C2 = 25 pF, L = 56 /LH). In
Figure 111.2, with C1 = 330 pF, L = 56 /LH, and C2 = 27 pF,
varying C3 between 10 pF and 0.003 /LF produced oscillation frequencies between about 2 MHz and 1.1 MHz. Varying C2 in Figure 111.3 produced a similar kind of control.
A final note is that all of these networks place a load on the
CKO output. If the signal from CKO is needed elsewhere in
the system and a circuit similar to one of those discussed in
this document is used, it will probably be necessary to buffer
the CKO output.
As the graphs indicate, various types of RLC networks were
also tried. The range of possible usable circuits here is limited only by the user's imagination and his favorite type of
RLC oscillator circuit. When their resonant frequency is
3-55
•
ll)
LLJ
COP Microcontro\ler Pinouts
I-
4.0 Conclusion
D..
The networks described are generally simple and inexpensive and have all been observed to be functional.
oZ
oo
GNO
CKD
CKI
The results obtained provide greater flexibility in the oscillator selection in a COPs system and gives the user some
general indication as to what may be expected with the various circuits described.
imEf
L7
L6
L5
L4
VCC
L3
L2
L1
GND
L7
L6
L5
L4
INI
IN2
VCC
L3
L2
L1
DO
Dl
D2
D3
G3
G2
Gl
GO
SK
SO
51
LO
DO
Dl
D2
D3
G3
G2
Gl
GO
IN3
INO
SK
SO
51
LO
TLlDD/6938-1
2.67
1
SLOWER
OSCILLATOR
PERCENT
VARIATION
OF SK PERIOD
FASTER
OSCILLATOR
1
-+-r-.....-f)-'1""'T-,-,-,....,--r-""'-'-'1""'T-r'T""1r-r-r-......., VOLTAGE (VCCI
-1
T=85·C (·······1
T=20·C (---I
T= -40·C (--I
T=O·C (---I
-2
eOP410L VALID EXTENDED Vce RANGE: 4.5V-9.5V
COP310L VALID EXTENDED VCC RANGE: 4.5V -7.5V
-3
OSCILLATOR FREQUENCY = SK P:RIOD
-4
TL/DD/6938-2
Note 1: Base period at Vee
= 5.0V.
Note 2: Device variation only. Graph does not include RC variation with temperature.
Note 3: SK period
= instruction cycle time.
FIGURE 1. COP310L/COP410L RC Oscillator Variation with Vce
3-56
o
o
"U
Z
o-I
VCC=4.5V
2.73
m
U1
VCC =6.3V
(
1.1~._·
SLOWER
OSCILLATOR
.4---
I
<#.,.~~"1.03
0.27
PERCENT
VARIATION
OF SK PERIOD
,.,'
0.41." ,,'" 20
-10
-40
I
.~
.
/
-2
.
/
/
/
-3
___ e 1.34
VCC=9.5V
~~
." ~
~
~0.80
/
/
FASTER -1
OSCILLATOR
!
_._ .... 1.60
/
'1.16/
/
/
/
;11.95
/
2.61/
COP410L VALID TEMPERATURE RANGE: O'C TO +70'C
C0P31 OL VALID TEMPERATURE RANGE: -40'C TO +85'C
/
OSCILLATOR FREOUENCY = SK P:RIOO
/
/
-4
Note 1: 20'C = base period.
TL/DD/6938-3
Note 2: Device variation only. Graph does not include RC variation with temperature.
Note 3: SK period = instruction cycle time.
FIGURE 2. COP310L/COP410L RC Oscll/ator VarIatIon wIth Temperature
18
16
14
12
10
SLOWER
OSCILLATOR
I
PERCENT
VARIATION
OF SK PERIOD
-r-r-T""T"'T""T""T'""T""1""T'""T""1r"T"'"r""r-T-r-T""T""T'"T"'T-'-'
•
VOLTAGE (VCC)
-2
FASTER
OSCILLATOR
-4
T=15'C (........)
T=20'C (-'-1
T -40'C (--I
T=O'C (---)
-6
1
=
-I
-10
-12
-14
COP420 VALID EXTENDED VCC RANGE: 4.5V - 6.3V
C0P320 VALID EXTENDED VCC RANGE: 4.5V-5.5V
OSCILLATOR FREQUENCY = SK P:RIOD
-16
-18
Note 1: Base period at Vee = 5.0V.
TL/DD/6938-4
Note 2: Device variation only. Graph does not include RC variation with temperature.
Note 3: SK period
= instruction cycle time.
FIGURE 3. COP320/COP420 RC Oscll/ator VarIatIon wIth Vee
3-57
it)
U.I
b
z
A.
o(.)
VCC=4.5V
2.81
SLOWER
OSCILLATOR
I
PERCENT
VARIATION
OF SK PERIOD
FASTER -1
OSCILLATOR
!
-2
COP420 VALID TEMPERATURE RANGE: O"C TO + 70"C
C0P320 VALID TEMPERATURE RANGE: -40"C TO +85"C
-3
3.14
OSCILLATOR FREQUENCY = SK P:RIOO
-4
-5
TL/DD/6938-5
Note 1: 20"C = base period.
Note 2: Device variation only. Graph does not include RC variation with temperature.
Note 3: SK period = instruction cycle time.
FIGURE 4. COP320/COP420 RC Oscillator Variation with Temperature
3·58
o
o
"U
4.67 :.~~
4 95
4.64 _.fI'~• •
4.49 -~~4:74 4.Bl
• ~P'-4.63 .
Z
o....
m
4.23 Rf~ 4.43
U'I
4.15 '''4024.38
3.BO f9~
.
3.29 3.7~? 3.67
3.80 3.BO
3.22 f'i
3.5B
3.11~3.09 3.41
2.B3
3.01
2.67 •
2.50
2.54
2.41/' 2.43
t.:
It
P
SLOWER
OSCILLATOR
I
PERCENT
VARIATION
OF SK PERIOD
--+~"""""'..,......r-r-r-..-T-'-"'-'--'-"""'r"""T"-r-T"""T-r--r-r....,
FASTER -1
OSCILLATOR
VOLTAGE (Vccl
T=BSOC (·· .. ···1
T = 20°C ( • - • I
T= -40°C (--I
T=O°C (--I
-2
-3
COP420L VALID EXTENDED VCC RANGE: 4.5V-9.5V
CDP320L VALID EXTENDED VCC RANGE: 4.SV -7.SV
OSCILLATOR FREQUENCY = SK P:RIDO
-4
-5
TL/DD/S938-S
Note 1: Base period at Vee = S.OV.
Note 2: Device variation only. Graph does not include RC variation with temperature.
Note 3: SK period = instruction cycle time.
FIGURE 5. COP320L/COP420L RC Oscillator Variation with Vee
•
3-59
it)
U.I
bz
a..
o
o
SLOWER
OSCILLATOR
PERCENT
VARIATION
OF SK PERIOO
-r""--F---,-=-==~'T'-===---
...-r---r--r--r-r-.........,.--r-....-. TEMPERATURE (·Cl
FASTER -1
OSCILLATOR
1
-2
COP42DL VAllO TEMPERATURE RANGE: D·C TO +7D·C
COP32DL VAllO TEMPERATURE RANGE: -4D·C TO +85·C
OSCILLATOR FREQUENCY = SK
~RIOO
-3
-4
TL/DD/6938-7
Note 1: 20"C = base period.
Note 2: Device variation only. Graph does not Include RC variation with temperature.
Note 3: SK period = Instruction cycle time.
FIGURE 6. COP320L/COP420L RC Oscillator Variation with Temperature
C2
~1.f:lCK'
~C1
C2
HCK'
~C1
~C3
L
CKI~CKO
~C1
~C2
TL/DD/6938-8
FIGURE 111.1
FIGURE 111.2
3-60
FIGURE 111.3
o
o
COP402
""D
Z
o-t
WIRING DIAGRAMS
490~H
CKI~CKO
m
U1
(FIG. 1)
98.4~H
CKI~CKO
(FIG. 21
1.30
SLOWER
OSCILLATOR
1.30
1.30
I
PERCENT
VARIATION
OF OSCILLATOR
PERIOD
I
-1
FASTER
OSCILLATOR
!
FIG. 1
-2
FIG. 2
I:=: ~~~ ~ ::~~
I:~:~.~~ ~~~ ~ ::~~
-3
-4
-5
Note 1: 25'C = base period.
TL/DD/6938-9
Note 2: Device variation only. Graph does not include "L" variation with temperature.
FIGURE 7
COP402
16
15.82
WIRING DIAGRAM
13.50
13.50
13.50
100~H
CKI~CKO
12
~25PF
•
SLOWER
OSCILLATOR
PERCENT
VARIATION
OF OSCILLATOR
PERIOD
I
-40
FASTER
OSCILLATOR
-8
-12
Note 1: 25'C
= base period.
i
20/
i
i
i
i
i
"
i
i
i
\
i
,
i
-14.16~-----i-14.16
"
-4
i
i
i
i
-2.58
-16
(-IVCC=5.0V
(---I VCC=6.0V
Tl/DD/6938-10
Note 2: Device variation only. Graph does not include LC variation with temperature.
FIGURE 8
3·61
't;.1.1)
w
COP420
6z
10-
WIRING DIAGRAM
Il.
oo
1-
100~H
CKI~CKO
~'00PF
6-
4-
2-
PERCENT
VARIATION
OF OSCILLATOR
PERIOD
-2-
-4-
-6-
-8-
-10-
TL/DD/6938-11
Note 1: 25°C = base period.
Note 2: Device variation only. Graph does not include LC variation with temperature.
No measurable variation over temperature.
FIGURE 9
COP420
10WIRING DIAGRAM
360.H
CKI~CKO
~330PF
6-
4-
SLOWER
OSCILLATOR
2-
1.59
~.-
I
PERCENT
VARIATION
OF OSCILLATOR
PERIOO
I
FASTER
OSCILLATOR
i
o
I
....
1.59
...~../
TEMPERATURE (·Cl
-47-~O
-~O -~O 0 ",."".1~""'20 25io ... ·~........5~ 55.'Y ~ ~O 15 Jo
~.-.- ••• - • • -c/
-2- -1.58
-1.56
••
-1.56
-1.56
(-IVCC=5.0V
1-·-1 VCC=6.0V
-4-4.25
-4.25
-6-
-1-
-10-
TL/DD/6938-12
Note 1: 25°C = base period.
Note 2: Device variation only. Graph does not include LC variation with temperature.
FIGURE 10
3-62
o
o
COP402
."
Z
31.11
o-f
WIRING OIAGRAM
30
11.4,,"
m
CKI~CKO
*'
25
U1
01
id'
20
15
15.51
\
10
\
\.\
SlOWER
OSCILLATOR
\
1-IVcC=5.0V
1-'-1 VCC=6.0V
·e,5.93
... • .......!.96
"" '.
PERCENT
VARIATION
OF OSCILLATOR
PERIOO
I
'.
-+-r---,.---,,--,--y-"'T"'ilh-.---.-r---,.---,rr., TEMPERATURE I'CI
-40 -30 -211 -10
10
20
\30
\
-5
\
FASTER
OSCILLATOR
!
40
50
60
70
80 85 90
-4.55
\
p ....
i
\
\
-10
-15
\
\
i
i
i
\
\
.....
-6.02
i
i
'
\/
11-17.97
Note 1: 2S'C
TL/DD/6938-13
= base period.
Note 2: Device variation only. Graph does not include LC variation with temperature.
FIGURE 11
COP402
25
WIRING DIAGRAM
20
490~H
CKI~CKO
*lDOPF
15
10
SlOWER
OSCILLATOR
1-IVCC=5.0V
1-,-1 VCC=6.0V
I
0.S4
PERCENT
VARIATION
OF OSCILLATOR
PERIOD
I
-+--,.---r----,..=7-=.......... '~~;:I!r~I~,.... I TEMPERATURE I'CI
40
5~0.S:0
70 \.
\
-5
FASTER
OSCILLATOR
so
\
\
90
•
-8.17
-10
-11.76
-15
-20
-25
TL/DD/6938-14
Note 1: 2S'C = base period.
Note 2: Device variation only. Graph does not include LC variation with temperature.
FIGURE 12
3-63
it)
1&.1
COP402
6z
10
WlRINO OIAORAMS
D-
o
(.)
5I~H
CKI~CKO
~
~
~~IFIO'11
CKI~CKO
SLOWER
OSCILLATOR
~
I
PlRCENT
VARIATION
OF OSCILLATOR
PERIOD
I
FASTER
OSCILLATOR
1
-2
flO l!I-IYCC=UY
• 1-·-1 Ycc =6.0Y
-4
flO.
2( ~:.~.:: :~~ ~ ::::
-I
-I
-10
TLIDD/6938-15
Note 1: 25'C = base period.
Note 2: Device variation only. Graph does not include LC variation with temperature.
FIGURE 13
COP402
10
WIRING DIAGRAM
1
SLOWEII
OSCILLATOR
I
PlRCENT
OF
o:tl~~~g:
PlRIOD
I
FASTER
0-+---rt-....,--Tl--,.--r---,.....
'-T----,r---r-r-r+--il--.,.....,...,TEMPERATURE I'CI
-2
1" _.
-5.21
-5.21
-I
-I
-10
TL/DD/6938-16
Note 1: 25'C = base period.
Note 2: Device variation only. Graph does not include LC variation with temperature.
FIGURE 14
3·64
o
o"'0
COP402
10
Z
o-t
WlRINO DIAGRAM
27pF
CKI
@
~330PF
m
U1
CKO
~10PF
4.00
4.00
4.00
SLOWER
OSCILLATOR
I
PERCENT
VARIATION
OF OSCILLATOR
PERIOD
-40 -30 -20 -10
0
-2
FASTER
OSCILLATOR
-4
-8
-8
-10
TLlDD/6938-17
Note 1: 25°C = base period.
Note 2: Device variation only. Graph does not include LC variation with temperature.
·No variation at 6V.
FIGURE 15
COP402
10
WIRING DIAGRAM
.r;;a
22MQ
CKI
CKD
8.60
6.60
UD
•
SLOWER
OSCILLATOR
I
PERCENT
VARIATION
OF OSCILLATOR
PERIOD
I
FASTER
OSCILLATOR
1
-+-,.-___r-_r_-r-__r-~f-r-_r_-rT__r-,.____r__r..., TEMPERATURE ('C)
-40
-2
( - ) VCC=5.0V
1-, --!YCC = I.OV
-3.00
-3.00
-3.00
-4
-I
-I
Note 1: 25°C
TL/DD/6938-18
= base period.
Note 2: Device variation only. Graph does not include RL variation with temperature.
FIGURE 16
3-65
it)
LLI
COP402
b
z
7.21
WIRING DIAGRAM
Q.
lK
oo
7.21
7.21
39oid!
CKI~CKD
~330PF
1
SLOWER
OSCILrOR
Z
PERCENT
OF
O:~I~tI{g:
I
0 ~-~-"--.----r-""T""---,r4::""'-r--"""""'-'----'--~r-1
-40
PERIOD
FASTER
-2
DSCILrTOR
-4
i
i
i
i
i
i
/
i
1'-5.13
-6
-I
-10
i
i
i
i
i
i
........... -9.02
-9.75
-11.35
TL/DD/6938-19
Note 1: 25°C = base period.
Note 2: Device variation only. Graph does not include RLC variation with temperature.
FIGURE 17
COP402
WIRING DIAGRAM
22MQ
,..@,,"
.:;;!; o.ol~F
(-)VCC=5.oY
(-._) VCC=I.OV
\
""
"
I ,-4.76
;\
""
;
;
"
;
""
\
..
-9.91
;
;
"\.
1
I
\-17.41;
\ ;
\ ;
\1
jj-25.15
TL/DD/6938-20
Note 1: 25°C
= base period.
Note 2: Device variation only. Graph does not include RLC variation with temperature.
FIGURE 18
3·66
(')
o"'0
COP402
2.411
UO
Z
o-f
WI~INQ OIAO~AM
m
U1
u
SLOWE~
OSCILLATO~
0.5
I
PERCENT
VARIATION
OF OSCILLATOR
PERIOD
I
-411
".70
i
FAITE~
DSCILLATO~
!
...-....
20i
10
-0.1
i
i
i
-1
i
i
-1.5
;
i
-0.31
-0.3.
( - I VCC=I.OV
(-.-) VCC=B.OV
;
i
i
i
-2
._._.... _._.J
-2.34
-2.5
-2.34
-2.34
TL/DD/6938-21
Note 1: 2S'C = base period.
Note 2: Device variation only. Graph does not include RLC variation with temperature.
FIGURE 19
COP402
WIRING DIAOMM.
22Mg
~
CKI~CKO
(AG.l)
410,,"
CKI~CKO
(FIG. 2)
SlOWER
OSCILLATOR
OF
,.i
PERCENT
VARIATION
I
-40
-1
FASTE~
OSCILLATOR
!
i
i
i
i
i
... _.•._....
1.13
1.83
p---.
I
I
I
I
I
I
•
I
,.,.
OSCILLATO~
PERIOD
i
i
i
i
i
-2
i
,.i
i
-3
i
i
i
( - I Vcc = I.OV
AO.l (_.-) VCC=I.OV
AU 1---1 VCC= I.OY, a.ov
I
.......-o-._._J
-3.51
-3.51
-3.51
-3.51
-4
-I
TLlDD/693B-22
Note 1: 2S'C = base period.
Note 2: RL in oven with COP402.
FIGURE 20
3-67
Lt)
LLI
COP420
5
z
16
WIRING DIAGRAM
a..
o
100~H
o
CKI~CKO
12
~100PF
SLOWER
OSCILLATOR
PERCENT
OF
O:tl~'tl~g=
0 -+-~-,--,---,--,---r~"F----r--r--h~-r--I-l-fr-.., TEMPERATURE ('C)
PERIOD
I
FASTER
OSCILLATOR
1
( - ) Vcc = 5.0V
( - - ) Vcc=6.0V
~4;.;..95;........4,.;..9;,,;.5_.......4.95
-4
-4
-8
-12
-16
Note 1: 25'C
-20
= base period.
TL/DD/6938-23
Note 2: LC in oven with COP402.
FIGURE 21
COP420L
10
WIRING DIAGRAMS
~:~
690~H
CKI~CKO
CKI~CKO
~39PF
~50PF
390~H
CKI~CKO
~10PF
PERCENT
VARIATION
OF OSCILLATOR
PERIOD
.....-,...........~I-'fHioft!'....~~-~""I~""I"'~~.,......, TEMPERATURE I'C)
-40 -30 -20 -10
0
10
40
70
80
85
90
-2
1 - ) VCC '" 5.0V
(.-.) VCC=7.0V
1--) VCC=9.0V
-4
-6
-8
-10
TLIDD/6938-26
Note 1: No measurable variation for all three circuits above.
Note 2: 25'C = base period.
Note 3: Device variation only. Graph does not include LC variation with temperature.
FIGURE 22
3·68
o
o"tJ
COP420L
Z
---
U5
\
\
..\
&90jiH
3.95
\.
*~OPF
\
\
~U4
'.
1
\
\
\
\
\
\
\
~O.9B
\. ''''',
PERCENT
VARIATION
OF OSCILLATOR
PERIOD
I
FASTER
.
\
'.
SLOWER
OSCILrOR
m
c.n
CKI~CKO
\
\
o-t
WIRING DIAGRAM
'.
"
....
-40
"
-1
1--) VCC = 5.0V
(---) VCC=7.0V
( - - ) Vce=9.0Y
"\.
'''''j' -,
'-1.17
\
~\
-3
\\
.~\
,\
\\
-4
,\ /
/
" -3.67
, " -4.55
\
-5
...--0-.......... -5.41
-5.41
-5.41
TLlDD/6936-26
Note 1: 25°C = base period.
Note 2: LC in oven with COP420L.
FIGURE 23
COP410L
WIRING DIAGRAM
4700 l'H
CKI~CKO
-!0.0011'f
•
1
SlOWER
OSCILLATOR
I
PERCENT
VARIATION
OF OSCILLATOR
PERIOO
I
-+-'---r-.---r-.,--,~ILr''-''~'"'"t"+''---r-'-ro TEMPERATURE 1°C)
FASTER
-2
,
-.
m
''1
1--) Vce = 5.0V
1---) VCC=7.0V
1--) VCC=9.0V
-6
-6.72
-8
Note 1: 25°C
TL/DD/6936-29
= base period.
Note 2: Device variation only. Graph does not include LC variation with temperature.
FIGURE 24
3-69
it)
LLI
COP410L
t-
oZ
WIRING DIAGRAM
D-
o
4700,..H
o
CKI~CKD
J.
SOpF
SLOWER
OSCILLATOR
I
PERCENT
VARIATION
OF OSCILLATOR
PERIOD
-40
I
FASTER -1
OSCILLATOR
( - - ) VCC = S.OV
(---) VCC=7.0V
(---) VCC=9.0V
-2
-3
-3.36
-4
TLlDD/6938-30
Note 1: 25'C = base period.
Note 2: Device variation only. Graph does not include LC variation with temperature.
FIGURE 25
COP410L
---
3.98
..
\ 3.98
\
WIRING DIAGRAM
\
\
4700,..H
\
\
2.08
2.08
CKI~CKO
\
\
\.
1
osc~t&~~:
~50PF
\
----<\
\\
\
1
\
I
PERCENT
VARIATION
OF OSCILLATOR
PERIOD
( - - ) Vce = 5.0V
(---) VCC=7.0V
(---) Vce=9.DV
\
'.
~.77
.,.
\
" ,
..........
-40
"
I
osr= ~:
40
\.
"\.
"\.e-...................
-2.00
-2.00
-2.00
-3
-4
Note 1: 25'C
TLlDD/6938-32
= base period.
Note 2: LC in oven with COP410L.
FIGURE 26
3-70
o
National Semiconductor
COP Note 6
Triac Control Using the
COP400 Microcontroller
Family
o"'C
Z
o
-t
m
Q)
Table of Contents
1.0 Triac Control
The COP400 single-chip controller family members provide
computational ability and speed which is more than adequate to intelligently manage power control. These controllers provide digital control while low cost and short turnaround enhance COPSTM desirability. The COPS controllers
are capable of 4 J.ts cycle times which can provide more
than adequate computational ability when controlling 60 Hz
line voltage. Input and output options available on the COPS
devices can contour the device to apply in many electrical
situations. A more detailed description of COPS qualifications is available in the COP400 data sheets.
The COPS controller family may be utilized to manage power in many ways. This paper is devoted to the investigation
of low cost triac interfaces with the COP400 family microcontroller and software techniques for power control applications.
1.0 TRIAC CONTROL
1.1 Basic Triac Operation
1.2 Triggering
1.3 Zero Voltage Detection
1.4 Direct Couple
1.5 Pulse Transformer Interface
1.6 False Turn-on
2.0 SOFTWARE TECHNIQUES
2.1 Zero Voltage Detection
2.2 Processing Time Allocations
Half Cycle Approach
Full Cycle Approach
2.3 Steady State Triggering
1.1 BASIC TRIAC OPERATION
A triac is basically a bidirectional switch which can be used
to control AC power. In the high-impedance state, the triac
blocks the principal voltage across the main terminals. By
pulsing the gate or applying a steady state gate signal, tho
triac may be triggered into a low impedance stato whoro
conduction across the main terminals will occur. The gato
signal polarity need not follow the main terminal polarity;
however, this does affect the gate current requirements.
Gate current requirements vary depending on the direction
of the main terminal current and the gate current. The four
trigger modes are illustrated in Figure 1.
3.0 TRIAC LIGHT INTENSITY CONTROL CODE
3.1 Triac Light Intensify Routine
Jt
T2
IGT
:rE
l
lMT
MTl
•
T2
IMT
~
~
1
GATE
IMTl
MT1
111-
111+
TL/DD/6939-1
FIGURE 1. Gate Trigger Modes. Polarities Referenced to Main Terminal 1.
3-71
CD
w
b
z
D.
o
(J
The breakover voltage (Veo) is specified with the gate current (IGT) equal to zero. By increasing the gate current supplied to the triac, Veo can be reduced to cause the triac to
go into the conduction or on state. Once the triac has entered the on state the gate signal need not be present to
sustain conduction. The triac will turn itself off when the
main terminal current falls below the minimum holding current required to sustain conduction (lH).
Triac turn-on time is primarily dependent on the magnitude
of the applied gate signal. To obtain decreased turn-on
times a sufficiently large gate signal should be applied. Faster turn-on time eliminates localized heat spots within the
pellet structure and increases triac dependability.
Digital logic circuits, without large buffers, may not have the
drive capabilities to efficiently turn on a triac. To insure proper operation in all firing situations, external trigger circuitry
might become necessary. Also, to prevent noise from disturbing the logic levels, AC/DC isolation or coupling techniques must be utilized. Sensitive gate triacs which require
minimal gate input signal and provide a limited amount of
main terminal current may be driven directly. This paper will
focus on 120VAC applications of power control.
A typical current and voltage characteristic curve is given in
Figure 2. As can be seen, when the gate voltage and the
main terminal 2 (MT2) voltages are positive with respect to
MT1 the triac will operate in quandrant 1. In this case the
trigger circuit sources current to the triac (I + MODE).
1.3 ZERO VOLTAGE DETECTION
In many applications it is advantageous to switch power at
the AC line zero voltage crossing. In doing this, the device
being controlled is not subjected to inherent AC transients.
By utilizing this technique, greater dependability can be obtained from the switching device and the device being
switched. It is also sometimes desirable to reference an
event on a cyclic basis corresponding to the AC line frequency. Depending on the load characteristics, switching
times need to be chosen carefully to insure optimal performance. Triac controlled AC switching referenced to the AC 60
Hz line frequency enables precise control over the conduction angle at which the triac is fired. This enables the COPS
device to control the power output by increasing or decreasing the conduction angle in each half cycle.
LOM STATE
-VBO
-------~
\..------ON STATE
~
7
IH
I
t
OFF STATE
I
VBO
TLIDD/6939-2
A wide variety of zero voltage detection circuits are available in various levels of sophistication. COPS devices, in
most cases, can compensate for noisy or semi-accurate
ZVD circuits. This compensation is utilized in the form of
debounce and delay routines. If a noisy transition occurs
near zero volts the COPS device can wait for a valid transition period specified by the maximum amount of noise
present. Some software considerations are presented in the
software section and are commented upon. The minimal
detection circuit is shown in Figure 9.
FIGURE 2. Voltage-Current Characteristics
After conduction occurs the main terminal current is independent of the gate current; however, due to the structure
of the triac the gate trigger current is dependent on the
direction of the main terminal current. The gate current requirements vary from mode to mode. In general, a triac is
more easily triggered when the gate current is in the same
direction as the main terminal current. This can be illustrated in the situation where there is not sufficient gate drive to
cause conduction when MT2 is both positive and negative.
In this case the triac may act as a single direction SCR and
conduction occurs in only one direction. The trigger circuit
must be deSigned to provide trigger currents for the worst
case trigger situation. Another reason ample trigger current
must be supplied is to prevent localized heating within the
pellet and speed up turn-on time. If the triac is barely triggered only a small portion of the junction will begin to conduct, thus causing localized heating and slower turn-on. If
an insufficient gate pulse is applied damage to the triac may
result.
1.4 DIRECT COUPLE
Isolation associated problems can be overcome by means
of direct AC coupling. One such method is illustrated in Figure 3. This circuit incorporates a half-wave rectifier in conjunction with a filter capacitor to provide the logic power
supply. The positive half-cycle is allowed to drop across the
zener diode and be filtered by the capacitor. This creates a
low cost line interface; however, only a limited supply current is available. In order to control the current capabilities
of this circuit the series resistor must be modified. However,
as more current is required, the power that must be dissipated in the series resistor increases. This increases the power
dissipation requirements of the series resistor and the system cost. For applications which require large current sources an alternative method is advisable. In order to assure
consistent operation, power supply ripple must be mini-
1.2 TRIGGERING
Gate triggering signals should exceed the minimum rated
trigger requirements as specified by the manufacturer. This
is essential to guarantee rapid turn-on time and consistent
operation from device to device.
3-72
(')
the potential of a non-gated turn-on of the triac. This creates
the undesirable situation of limited control of the system. In
a system with an inductive load the voltage leads the current by a phase shift corresponding to the amount of inductance in the motor. As the current passes near zero, the
voltage is at a non-zero value, offset due to the phase shift.
When the principal current through the triac pellet decreases to a value not capable of sustaining conduction the triac
will turn off. At this point in time the voltage across the terminals will instantaneously attain a value corresponding to
the phase shift caused by the inductive load. The rapid decay of current in the inductor causes an L dl/dT voltage
applied across the terminals of the triac. Should this voltage
exceed the blocking voltage specified for the triac, a false
turn-on will occur.
mized. COPS devices can be operated over a relatively wide
power supply range. However, excessive ripple may cause
an inadvertent reset operation of the device.
VPOS
120VAC
LOAD
TLl00/6939-3
a"tJ
z
a-I
m
Q)
In order to avoid false turn-on, a snubber network must be
added across the terminals to absorb the excess energy
generated by this situation. A common form of this network
is a simple RC in series across the terminals. In order to
select the values of the network it is necessary to determine
the peak voltage allowable in the system and the maximum
dV /dT stress the triac can withstand. One approach to obtaining the optimal values for Rs and Cs is to model the
effective circuit and solve for the triac voltage. The snubber
in conjunction with the load can now be modeled as an RLC
network. Due to the two storage elements (L motor, C snubber) a second order differential equation is generated. Rather than approach this problem from a computer standpoint it
becomes much easier to obtain design curves generated for
rapid solution of this problem. These design curves are
available in many triac publications. (For instance, see RCA
application note AN 4745.)
FIGURE 3. AC Direct Couple
1.5 PULSE TRANSFORMER INTERFACE
Digital logic control of triacs is easily accomplished by triggering through pulse transformers or optical coupling. The
energy step-up gained by using a pulse transformer should
provide a more than adequate gate trigger signal. This complies with manufacturers' suggested gate signal requirements. Pulse transformers also provide AC/DC isolation
necessary in control logic interfaces. Minimal circuit interface to the pulse transformer is required as shown in Figure
4. Optical coupling circuits provide isolation, and in some
cases adequate gate drive capabilities.
2.0 Software Techniques
2.1 ZERO VOLTAGE DETECTION
120V
In order to intelligently control triacs on a cyclic basis, an
accurate time base must be defined. This may be in the
form of an AC, 60 Hz sync pulse generated by a zero voltage detection circuit or a simple real time clock. The
COP400 series microcontrollers are suited to accommodate
either of these time base schemes while accomplishing auxiliary tasks.
LOGIC
TL/00/6939-4
FIGURE 4. Pulse Transformer Interface
Zero voltage detection is the most useful scheme in AC
power control because it affords a real time clock base as
well as a reference point in the AC waveform. With this information it is possible to minimize RFI by initiating poweron operations near the AC line voltage zero crossing. It is
also possible to fire the triac for only a portion of the cycle,
thus utilizing conduction angle manipulation. This is useful in
both motor control and light intensity control.
A logic controlled pulse is applied to the base of the transistor to switch current through the primary of the pulse transformer. The transformer then transfers the signal to the secondary and causes the triac to fire. The energy transfer that
is now available on the secondary is more than adequate to
turn on the triac in any of its operating modes. When the
pulse transformer is switched off a reverse EMF is generated in the primary coil which may cause damage to the transistor. The diode across the primary serves to protect the
collector junction of the switching transistor. Another major
advantage is AC isolation; the gate of the triac is now completely isolated from the logic portion of the circuit.
Sophisticated zero voltage detection circuits which are capable of discriminating against noise and switch precisely at
zero crossing are not necessary when used in conjunction
with a COPS device. COPS software is capable of compensating for noisy or semi-accurate zero voltage detection circuits. This can be accomplished by introducing delays and
debounce techniques in the software routines. With a given
reference point in the AC waveform it now becomes easy
1.6 FALSE TURN-ON
When switching an inductive load, voltage spikes may be
generated across the main terminals of the triac which have
3-73
•
(D
LLI
bz
to divide the waveform to efficiently allocate processing
time. These techniques are illustrated in the code listing at
the end of this paper.
If a delay of 71'/4 RAD (45 degrees) is inserted after each
zero crossing detection the RMS voltage to the load can be
determined in the following manner:
a..
oo
VLOAD =
VLOAD =
~(120
./2)2
JTT sin 2 (a) da
- (-)(2)
2 71'
TT/4
~(120 ./2)2
~(2) (1.428)
VLOAD = 114.4VRMS
71'/4 RAD = 45 degrees
@60 Hz
t = 2.08 ms
As can be seen the dead time on each half cycle can be
2.08 ms and the load will still see 114.4 V RMS of a V SUPPLY
of 120 VRMS. If this approach is implemented the initial delay of 2.08 ms can be used as computation time. The number of instructions which can be executed when operating at
4 IJ-s instruction cycle time is:
TRIAC
VOLTAGE
2.08 ms/4 IJ-s
=
520 instructions
(130 instructions at 16 IJ-s cycle time)
Full Cycle Approach
The methods of half cycle and full cycle triggering are very
similar in procedure. The main difference is that all timing is
referenced from only one (of the two) zero voltage detection
transition in each full AC cycle. For most all applications,
when varying the conduction angle it is desirable to fire at
the same conduction angle each half cycle to maintain a
symmetric applied voltage. In order to accomplish this the
triac may be fired twice from one reference point. When
applying this technique an 8.33 ms delay must be executed
to maintain the symmetric applied voltage. This approach
provides the most auxiliary computation time in that the 8.33
ms delay may be turned into computational time. The basic
flow for this technique is illustrated below.
RS
Cs
TL/DD/6939-5
FIGURE 5. Current Lag Caused by Inductive Load,
Snubber Circuit
2.2 PROCESSING TIME ALLOCATIONS
Half Cycle Approach
In order to accomplish more than triac timing, dead delay
time must be turned into computation time. It appears that
the controller is occupied totally by time delays, which
leaves a very limited amount of additional control capability.
There are, however, many ways to accomplish auxiliary
tasks simultaneously.
RMS
LOAD
On each half cycle an initial delay is incorporated to space
into the cycle. This dead time may be put to use and very
little voltage to the load is sacrificed. For example, if the
load is switched on at 71'/4 RAD, the maximum applied RMS
voltage to the load is 114VRMS (assuming VSUPPLY
120VRMS). This is illustrated in the figure below.
TLlDD/6939-7
FIGURE 7. Full Cycle Approach
In the above example the zero crossing pulse is debounced
on the one-to-zero transition, thus marking the beginning of
a full cycle. Once this transition has been detected, an ini-
TL/DD/6939-6
FIGURE 6. Full Cycle Approach
3-74
o
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LOGIC
LEVEL
1/8 DS8863
l m : f ....._ _....._ _ _V_COOC 120VAC
DS8863 SCHEMATIC
AC POWER INTERFACE
TLIDD/6939-8
FIGURE 8. Steady State Triggering
transformer, an external oscillator must be gated to the triac
to provide the trigger signal. A pulse train of 10 to 15 kHz is
adequate to fire the triac each half cycle. This calls for external components and is relatively costly. If isolation associated problems can be tolerated or overcome (dual power
supply transformers, direct AC coupling, etc.), a simple buffer may be utilized in triggering the triac. This method is illustrated in Figure 8. The National Semiconductor DS8863 display driver is capable of steady state firing of the triac. National offers many buffers capable of driving several hundred milliamps, which are suitable for driving triacs. On the
market today there are many suppliers of sensitive gate triacs which may be triggered directly from a COPS device or
in conjunction with a smaller external buffer.
tial delay of 7T' 14 RAD is incorporated and the triac is fired.
At this time exactly 8.33 ms is available until the triac need
be triggered again. This will provide a symmetric voltage to
the load only if the delay is 8.33 ms. During this period the
number of instructions which can be executed when operating at 4 J.Ls is:
8.33 ms/4 J.Ls = 2082
(520 instructions at 16 J.Ls)
An alternative approach may be to take the burden from the
COPS device by using peripheral devices such as static display controllers, external latches, etc.
2.3 STEADY STATE TRIGGERING
It is possible to trigger a triac with a steady state logic level.
This is accomplished by allowing the triac gate to sink or
source current during the desired on-time. When utilizing
this method it becomes easier to trigger the triac and leave
it on for many cycles without having to execute code to
retrigger. This approach is advantageous when the triac
must be fired is for relatively long periods and conduction
angle firing is not desired, thus more time is available to
accomplish auxiliary tasks. A steady state on or off signal
and external circuitry can accomplish triac firing and free the
processor for other tasks. If it is desired to use a pulse
The DS8863 display driver is capable of sinking up to 500
mA, which is adequate to drive a standard triac. In the off
state the driver will not sink current. When a logic "1 II is
applied to the input the device will turn on. Keeping the
device off (output "1 ") will prevent the triac from turning on
because the buffer does not have the capability of sourcing
current. A series resistor limits the current from the triac
gate and the diode isolates the negative spikes from the
gate. Since the drive circuit will only sink current in this configuration, the triac will be operating in the 1- and 111- modes.
3-75
•
CD
W
I-
3.0 Triac Light Intensity
Control Code
a.
The following code is not intended to be a final functional
program. In order to utilize this program, modifications must
be made to specialize the routines. This is intended to illustrate the method and is void of control code to command a
response such as intensify or deintensify. The control is up
to the user and full understanding of the program must be
attained before modifications can be implemented.
oz
o
o
Once a level has been specified, the remaining time in the
half cycle is then divided into sublevels. The sublevels are
increased in steps to the maximum level. The "FINO" RAM
location contains the number of times that the triac will be
fired per sublevel, thus creating the intensity time base.
There are 15 valid sublevels and up to 15 fire-times per
sublevel. Both these parameters may be increased to provide better resolution and longer intensify periods. To make
the triac de-intensity (dim) the sublevels need only to be
decremented rather than incremented. If this is done, the
conduction angle will start out at the maximum level and dim
by means of stepping down the sublevels. When modifying
this routine to incorporate more resolution or increased versatility, care must be taken to account for transfer of control
instructions to and from the delay routines.
This program is a general purpose light intensifying routine
which may be modified to suit light dimmer applications. The
delay routines require a 4.469 !-'-S cycle time which can be
attained with a 3.578 MHz crystal (CKII 16 option). This program divides the half cycle of a 60 Hz power line into 16
levels. Intensity is varied by increasing or decreasing the
conduction angle by firing the triac at various levels. The
program will increase the conduction angle to a maximum
specified intensity in a fixed amount of time. The time required to intensify to the maximum level is dependent on the
number of fire-times per level that is specified (FINO). This
code illustrates a half cycle approach and relies on the parameters specified by the programmer in the control selection.
The following is a schematic diagram of the COPS interface
to 120VAC lamps. The program will intensify or de-intensify
the lamps under program control.
3.1 TRIAC LIGHT INTENSIFY ROUTINE
This program intensifies a light source by varying the conduction angle applied to the load. The maximum level of
intensity is stored in "LEVEL," and the time to get to that
level is specified by "FIND." Both these parameters may be
altered to suit specific applications. To cause the program
to de-intensify the light source, the sublevels must be decremented rather than incremented.
Zero crossings of the 60 Hz line are detected and software
debounced to initiate each half cycle; thus the triac is serviced on every half cycle of the power line. A level/sublevel
approach is utilized to vary the conduction angle and provide a prolonged intensifying period. The maximum intensity
is specified by the "LEVEL" RAM location and time required
to get to that level is specified by the "FINO" RAM location.
Go
6.3VAC -Wl~~
TLIDD/6939-9
FIGURE 9. Triac Interface for COPS Program
3-76
; TRIAC LIGHT INTENSIFY ROUTINE
JP
DELL:
CLRA
DEL:
NOP
LO
; FALSE ALARM, TRY AGAIN
; DO A DELAY TO COMPENSATE
; THIS PROGRAM INTENSIFIES A LIGHT SOURCE BY VARYING THE
NOP
; FOR NON SYMMETRIC ZC
; CONDUCTION ANGLE APPLIED TO THE LOAD. THE MAX LEVEL
NOP
; OF INTENSITY IS STORED IN 'LEVEL' AND THE TIME TO GET TO
AISC
; THAT LEVEL IS SPECIFIED BY 'FIND'. BOTH THESE PARAMETERS
JP
DEL
; KEEP DELAY GOING
; MAY BE ALTERED TO SUIT SPECIFIC APPLICATIONS. TO CAUSE
JP
DOlT
; GO TO MAIN ROUTINE
o
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; THE PROGRAM TO DE·INTENSIFY THE LIGHT SOURCE, THE
; SUBLEVELS MUST BE DECREMENTED RATHER THAN
.FORM
; INCREMENTED.
.PAGE
TEMP1
=1,0
; TEMPORARY DELAY COUNTER
; THIS IS THE MAIN ROUTINE FOR THE INTENSIFYIDE·INTENSIFY
FIND
=0,9
; NUMBER OF FIRE TIMES
; OPERATIONS. TRANSFER OF CONTROL TO THIS SECTION
LEVEL
=0,0
; MAX LEVEL
; OCCURS AFTER ZERO VOLTAGE CROSSING EACH HALF CYCLE.
SUBLEV
=1,10
; SUBLEVEL COUNT
; THIS MAKE USE OF TEMP REGISTERS THUS PARAMETERS
TEMP
=1,11
; TEMPORARY DELAY COUNTER
; NEED NOT BE REDEFINED FOR EACH OPERATION.
; HERE THE OPERATING PARAMETERS ARE DEFINED AND LEVEL
; INITIATION IS SPECIFIED
INT:
CLRA
; DELAY INTO WAVEFORM
ADT
.FORM
LBI
TEMP
; USE TEMP REG
JSRP
PORT
; DO DELAY
LDD
LEVEL
; POINT TO LEVEL TO INITIATE
.PAGE
CLRA
CLRAM:
LBI
CLR;
CLRA
; REQUIRED
3,15
; ROUTINE TO CLEAR ALL RAM
POINT:
; DELAY
; DELAY TO MAX LEVEL
XDS
JP
CLR
TAMP:
XABR
XAD
TEMP
LBI
TEMP
AISC
15
LD
JP
BEGG
AISC
15
JP
ATLEV
XABR
JP
CLR
X
15
DES
JP
TAMP
; KEEP DOING IT
AT LEV:
LDD
SUBLEV
; AT MAX FIRE LEVEL
XAD
TEMP
; INIT FOR SUBLEVEL DELAY
JK:
LBI
TEMP
; THERE
; OUTPUT 15 TO G PORTS TO PULL
; UP ZERO CROSSER INPUT
BEG:
LBI
LEVEL
STII
7
JSR
OUT
; SPECIFY MAX LEVEL
LD
; COPY TO TEMP1
; SYNC UP TO 60 HZ
SKGBZ
JP
HI
; READY NOW
JP
BEG
; WAIT TILL GIS 1
; DO SERIES OF .5MS TO GET
JSRP
; AND SYNCHRONIZES THE COPS DEVICE TO THE 60 HZ AC LINE
OGI
; ARE WE AT THE LEVEL?
; MADE IT TO THE LEVEL
;NO
; THIS SECTION INITIATES CONTROL ON POWER UP OR RESET
BEGG:
; USE TEMP DIGIT TO DELAY
TRE:
SBLEV:
AISC
1
; AT SUB LEVEL?
JP
TRE
; NO DO DELAY
JP
SBLEV
;YES
JSRP
SPDL
; VARIABLE DELAY
JP
JK
X
LBI
FIND
; VOLTAGE DETECTION INPUT AND COMPENSATES FOR THE
JSRP
DEC
; DEC FIRE NUMBER
; OFFSET OF THE DETECTION CIRCUIT
AISC
JMP
FIRE
; NO KEEP FIRING AT THAT LEVEL
SUBLEV
; YES INC SUBLEVEL
14
; IS MAX SUB LEV REACHED
JP
THERE
; NO INC SUB LEV
JP
MAXLEV
;YES FIREIT
JSRP
INC
; GO TO NEXT SUBLEVEL
LBI
FIND
; THIS SECTION PROVIDES THE DEBOUNCE FOR THE ZERO
MAXLEV:
HI:
SKGBZ
0
; TEST GO FOR ZERO CROSS
LBI
JP
HI
; HIGH LEVEL
CLRA
; START OF DEBOUNCE DELAY
SKE
AISC
; GETS HERE ON FIRST TRANSITION
CLRA
AISC
JP
.-1
THERE:
; DID A LlTILE DELAY, IS IT STILL 0
SKGBZ
0
; TEST FOR 0
JP
HI
; FALSE ALARM
; MUST HAVE HAD SOME NOISE GO BACK AND WAIT FOR TRUE ZC
DOlT:
JMP
LO:
SKGBZ
DDD:
INT
JP
DDD
JP
LO
.-1
SKGBZ
0
.FORM
.PAGE
; NO WAIT HERE FOR A BIT
; WELL, DO WE HAVE A CLEAN
; TRANSITION
JP
DELL
; SET FIRE TIME
;GOFIRE
; DEBOUNCE IN 0 TO 1
AISC
JP
14
MAX LEV
; TRIAC
; GOING TO WAIT AND SEE
CLRA
STII
JP
; VALID TRANSITION, SERVICE
; MAY HAVE SOMETHING THERE
; YES, GO TO MAIN ROUTINE
3·77
; TEST IF FIND AT 15
•
CD
UJ
tO
: SUBROUTINE PAGE
NOP
INC:
NOP
CLRA
Z
AISC
1
D.
JP
ADEX
0
DEC:
0
ADEX:
LBI
: GO ADD ONE TO DIGIT
OBD
CLRA
:OTOA
SKBGZ
COMP
: CREATE A 15
ADD
:ADDATORAM
JMP
HI
; DEBOUNCE ONE TO ZERO
; PUT BACK (0 - 1 IN A NOW)
JMP
LO
; DEBOUNCE ZERO TO ONE
SPDL:
LBI
TEMPl
PORT:
LD
LBI
0,10
CLRA
; DELAY ROUTINE
; WILL BE REPLACED LATER
AISC
JP
.-1
OUT:
LD
RET
LBI
AISC
1
JP
FOY
LBI
LEVEL
RET
; DONE DELAY
0,15
FOY:
; PULSE 0 OUTPUT
X
JP
OBD
.END
NOP
3·78
; THE AMOUNT OF DELAY
; ALSO USED TO COpy LEVEL
; RESTORE LEVEL
X
.-5
; TEMPl IS A TEMP REG
; VALUE IN TEMPl DICTATES
LD
XIS
JP
FIRE:
: TEST WHICH DEBOUNCE IS
: NEEDED
X
RET
DE5:
0,0
PORT
o
National Semiconductor
COP Note 7
Testing of COPSTM Chips
a""C
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m
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1) Synchronize the device and tester.
Table of Contents
2) Test the internal logic and I/O.
3) Test the RAM.
1.0 INTRODUCTION
4) Verify the ROM program.
2.0 PHILOSOPHY
3.0 BUILT·IN TEST FEATURES
3.1 Sync between OUT and Tester
3.2 Internal Logic Test
3.3 RAM Test
3.4 ROM Dump
This note will provide some insight into the test mode, the
mechanics of testing, and the philosophy of how to implement a test of the COP-400 microcontrollers. Other than the
obvious, (verifying that the part meets the specifications),
the reason for the test must be considered. Somewhat different criteria may hold, depending on the objective. The
manufacturer wafer sort or final test can differ from an incoming inspection at the user's plant, or a field reject test.
The first two tests have limited interest as this is not a justification of the testing done on the part during manufacture.
Rather, this is a guide for those doing user functional testing.
1.0 INTRODUCTION
Since the introduction of the very first semiconductor devices, testing has been a major problem and expense in their
production and use. As the complexity has risen, testing has
become a more significant factor. With today's single chip
microcontrollers like the COPS devices this is particularly
true as one has a complete computer system in a chip. In
order to reduce the testing burden, the facilities to ease the
testing have been built into the COPS devices. With the test
ability built into the device for production test, the user need
only follow set procedures to verify the chip at incoming
inspection or field test.
2.0 PHILOSOPHY
The basic test philosophy requires that four major areas be
exercised. These areas are:
If the devices perform all of these four properly, the device
is good. This is a reasonable assumption with a standard
device that has a debugged test routine and is ROM programmed. A custom circuit just going into production might
not have the accumulated test baCkground. By attacking the
problem on a "sum of the parts" approach, one need not do
any exhaustive functional test on routine production parts.
This will be a major gain where lengthy time consuming or
time dependent routines are involved. If one attempts to do
a functional test of the chip, a sequence that is unique to the
application is needed. Thus, a test program must be written
and debugged for each ROM pattern. Further, a test
box/board must be designed, built, debugged, documented,
and maintained for each one. If testing has been considered
from the beginning, the chip will have built-in capabilities to
exercise the various parts of it. The different functional parts
and instructions are tested to verify proper operation at the
voltage and frequency limits.
3.0 BUILT·IN TEST FEATURES
The first step in testing the COP400 devices is to understand the built-in test control features. This will involve the
SI/O and the L lines. The SO pin has been designed to be
the control node for testing. The pin will normally be in an
active low state and when forced high externally, places the
chip in the test mode. It should be noted that this output can
sink considerable current and one should not force the pin
to the Vee rail. By limiting the voltage to the 2.0/3.0V range
one can not damage the device where the application of a
higher voltage could. When forced into the test mode the SI
pin controls the sub mode of the chip. With SI high the data
placed on the L port is used as an instruction. When SI is
low (and the L output is enabled) the contents of the ROM
will be dumped out through the L port. Certain other internal
functions have been implemented to allow these modes but
these are not part of the basic operation. Included in this
category is the activation of the skip signal to prevent the
program counter from jumping out of sequence by executing
a program control instruction.
3-79
•
I"-
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bz
0..
o
o
3.1 Sync Between Tester and OUT
3.2 Internal Logic Test
In order to be able to test a COPS chip, the tester must be in
sync with the device under test (OUT). By using an external
oscillator the two may be run at the same frequency. This is
true regardless of the option or type of oscillator chosen for
the chip. Even the RC configuration may be overridden with
an external signal that meets the level requirements. In addition to running at the same frequency, the chip and tester
must be in sync on a bit basis. See Figure 1. The supportive
features mentioned above include the condition of the SK
signal being a bit (instruction) clock until stopped by software in the program. Hence, one can start the tests based
on an edge change of SK. It is important that this be accurate because all data I/O changes will be relative to the SK
timing (see the appropriate device data sheet).
With the device and the tester in sync, actual testing may
begin. See the sequence control circuit of Figure 2. To place
the chip into the test mode the SO output is pulled to a one
level (between 2.0 and 3.0 volts). It should be pulled with a
circuit that will limit the upper voltage to 3V as this output
can have a significant current sink capability. On power up
(or after reset) the SO line is set to a zero by the internal
logic. An internal sense line will detect the forced condition
and provide test control. A delay of 10 ms should be taken
after power-up to allow the power on reset circuit to time out
before instructions can be executed. If the reset pin is activated in mid-program for some reason, several instructions
cycle times should be ignored to insure complete operation.
It should also be noted that the oscillator frequency is programmed to a rate of 4-32 higher than SK. If one is building
a test fixture for more than one device, some method must
be available to enter this number. If one is testing a COP420
or COP421 near its upper limit it would be wise to do the SK
sync operation at a lower rate and then increase the input
frequency. This is desirable because the phase relationship
is close to TIL propagation delays at the upper limit. Implementation of the area could be a preset counter that is gated on after a zero to one transition is seen on SK. Continual
comparison could be made but once in sync, there should
not be any need for the comparison as they should remain
in sync.
The tester should at this point force instructions into the L
port. These instructions will be executed as if they were
from the ROM. The sequence of the instructions is not particularly critical. Table I gives an example sequence. The
main steps are to be able to detect an output change (OGI)
early to verify connection! operation. It is much better to find
a problem before going through the steps of loading RAM
and then finding that the chip doesn't work. All instructions
should be exercised although certain ones should be postponed. Enabling the Q register to the L port is an example.
This would interfere with the insertion of instructions on the
L port. Another problem is the SO test which could be set up
with an XAS and then released from the test mode to check
proper data output.
The basic use of this "sync counter" is to derive the proper
timing for loading data and instructions into the chip and
verify the outputs. The COP402 data sheet should be used
as a guide for these times, modified properly for the Land C
parts. For those designing testers, it is suggested that one
not attempt to test worse case timing changes as these
could be very difficult to implement. Like other parametric
tests these should in general be left to the professional test
equipment.
Certain commands will require more effort than others. To
check the program counter during JMP's and· sub-routine
operation will require that known info at the new address be
available. One should execute a JSRP at some known address and release the test mode to see that the operation in
the subroutine (e.g., SC) is done and that a return is made to
N + 1. At this point test mode can be re-established to
continue the test. The main point to remember is to provide
a positive indication of the success of that specific test.
CLOCK TO DUT
CLOCK TO COP402
SK (OUT)
SK (COP402)
TL/DD/6940-1
FIGURE 1. Tester Clock Generation and Synchronization Circuit
3-80
o
o
"C
Vss
Z
o-I
m
........
02
03
PUSH
...LiiESff
VSS------
Vss
1KQL-_ _...1
c
o
4
o
5
3
DS75491
TL/DD/6940-2
FIGURE 2. Tester Mode Sequencer
3.3 RAM Test
check the ROM contents, the ROM dump mode must be
entered. One should force a JMP to an address near the
end of the ROM space (3FF for a 420 chip, 1FF for a 410).
A desirable point might be 3FA. The program counter will
step ahead on each instruction cycle unless a program control is executed. The next step is to load the Q register with
a non-conflicting value so that the enabling of the L outputs
will not destroy the second byte of the LEI instruction as
control is passed into the ROM dump mode. After going to
this address, one should execute an enable of the L lines to
the output port (LEI 4). Having done this the external buffers
should be disabled and the SI pin taken low. This will allow
data out and remove potential level conflicts. By letting the
PC step ahead to address zero one can then begin the byte
by byte comparison of data. In this mode the controller is
not executing the code because the skip line is enabled
throughout the sequence. By halting a counter on a failure,
one could determine the questionable address.
The verification of RAM is a part of the internal logic test,
but is treated separately here. One must check both the
RAM and its address register to find all faults. An example
of this testing would be to load RAM with a string of STII
commands. By then going back and reading this data to the
outside (through an OMG instruction in a loop) the tester
could verify both RAM and address were functional. One
could then load RAM with all 6's and 9's (or 5's and 10's)
sequentially to insure that all bits were functional and adjacent bits not shorted. Other similar tests could be run at the
discretion of the user to do further testing. All of these tests
would utilize the output of data via the G ports to validate
the data. See the comparator circuit Figure 3.
3.4 ROM Dump
Successful operation of the internal logic tests and RAM will
lead to the final test phase, ROM comparison. In order to
3-81
~ r-----------------------------------------------------------------------------------------~
LIJ
5z
a..
o
100Q
MODE
80
LO
SO
TEST
11
~
o
COP402
-~ RESET
SK02
DO 01 02 03
A3 A2 Al AD
I AB
83 82 81 80
CoMP 2
IPO IPS
~
81
82
83
9.1 kQ
16 VSS
74CSS
I
L2
L3
L4
LS
L6
GO G1 G2 G3L7
~SI
84
74CSS
AB 83 82 81 80
86
':"
VSS..J
~
21
11
DO 01 02 03
SO
COP420
OUT
SI
...12
1*
RmT
GO Gl G2 G3
INl
IN2 : : l - 2
IND
IN3
V42O
VCC
SK-SKOUT
3-
87
~
V+19 V
LM340
+SV
VSS
LM217
ADJUST
LO L1 L2 L3 L4 LS L6 L7
~
80
81
82
83
84
8S
86
87
II
- 1 2 - VOO
-J;
VCC
AD ~
Al ~
A2 ~
A3 ~
A4 ~
AS
MMS204
A6x2
TEST
A7
PROGRAM
A8CS PROM 2 ~ ~
-
VSS
B7 86 8S 84
02
03
04
05
06
07
08
09
010
C
0
4
0
4
0
AD
Al
02
A2
03
A3
04
A4
05
06~ AS
07~ A6
08~ A7
AB
09-- CS PROM 2
010
L.....h
2'
':"
VSS.J
B3 82 81 BD
01 R ~1 Ql~l
CS PROM 1
PS
AB
A>8 83 82 81 :~B
III
DONE
I I
Bo 81 82 83 84 85 B6 B7
74CS5
74CSsi
A3 A2 Al AD
IN IAB
83 82 81 80
CC
8
VBB
VSS-E PGM
VSS
V42D
""MM74CD4
1
VB8
~
PGM
~
VSS ~
MMS204
x2
420
PROGRAM
VOO 1---12
VCC
~
CS PROM 1
PS
~
U
TLI 00/6940-3
FIGURE 3. Functional Logic and RAM Comparison Circuit
3-82
0
0
TABLE I. Typical Test Sequence
INSTRUCTION RESULT
NOP
OGI9
OGI6
STII8
LBI3,13
OBD
CLRA
XABR
CAB
OBD
CLRA
AISC2
CAB
OBD
STII7
OBD
CAB
OMG
CLRA
CAB
OMG
5MBO
OMG
5MB1
OMG
RMBO
RMB3
X
CAB
OMG
LD1
XADO,O
AISC15
LDDO,O
X
OMB
LDO
ADT
XDS
XDS
OBD
STII5
CBA
AISC3
COMMENTS
INSTRUCTION
NO CHANGE CHECK NOP & ALLOW TRANSIENT
CYCLE FOR MODE
G(O> 9)
NOT ON 410L/411L
G(9) 6)
REVERSEALLG STATES
SET UP 0,0 FOR FUTURE
B TO NEW POSITION (3, 13)
D(O> 13
CHECKD
MAKE SURE A = 0
3> A;O > Br
MOVE3toBd
D(13) 3)
CHECK XABR CAB & D CHANGE
I
IFORCEA> 2
2> Bd
D(3) 2)
VERIFY 2 FROM A > Bd
7> 0.2&Bd > 3
D(2) 3)
STIlINCREMENTS Bd
SEE THAT A STILL THE SAME
G(6) 7)
OMB & RAM CHECK
G(7) 8)
CLRA
ASC
SC
SKC
LDDO,O
X
OMG
CLRA
ASC
X
OMG
CAMO
XDS
X
OMG
LD2
B(O,O)
TIE IN RAM, A & G OPERATION
5MB INST. CHECK
G(8) 9)
G(9) 11)
G(11 > 7)
G(7) 1)
D(2) 0)
:0> 0,0;2 > A
A=2>B
OUTPUT M(O,2)
M(O,2) > A; B > 1,2
A(7) < - > M(O,O) 2
AISC CHECK; A = 1
CHECK SKIP OF 2 BYTE INST.
STORE 1
VERIFY
COPY1,2 BACK TO A
ADD TEN
LEAVE 111N 1,2;GO 1,1 WITH 1
LEAVE 11N 1,1;GO 1,OW?
CHECK Bd MOVEMENT
5> 1,O;BdTO 1,1
CHECKB> A
AISC CHECK 4 > A
INSTRUCTION RESULT
COMMENTS
XDS
OMG
XDS
LDDO,O
OBD
AISC4
X
OMG
CLRA
COMP
XOR
XIS
LDDO,O
SKE
LB 1,2
OBD
SKE
LBI1,O
5MB2
SKE
RMB2
SKE
5MB3
SKE
LDDO,O
X3
XAD1,1
XIS1
ING
X
1>A;4>1,1
FROM 1,0
5 > A; 1 > 1,0; Bd
SKIPPED I
G(1 > 5)
< 15 SKIP
0(0) 15)
9>A
9> 15
G(5) 9)
ONESTOA
FLIP MEMORY
6 > 1,15; 9 > A; Bd > 1,0
SKIP
0(15) 0)
SKIP 2 WORD LBI (NOT IN 410)
VERIFY WORD
11 NOT = 9
BACK TO 1,0
:CHECKBIT
:MANIPULATIONS
Bd> 2,0
9>1,1;4>A
4 > 2,0; Bd > 3,1
INPUTG PORT
STORE
3-83
G=9
G(9) 10)
-a
z
0
-t
m
.......
STORE A
NO CHANGE
CARRY ADDS ONE TO MEMORY
STORE A & MIN 0; 10,9
9 > 3,1; 10 > A; Bd > 3,0
STORE 9 IN 3,0
G(10) 9)
9> A; Bd > 1,0
RESULT
OMG
LD3
OMG
ADD
X
SC
LDDO,O
CASC
SKC
X
OMG
CLRA
AISC3
X
SC
SKC
X
OMG
RC
SKC
X
OMG
LBIO,O
LBI1,15
LBI2,7
OMG
COMA
OMG
X
OMG
LEI 1
XAS
CLRA
AISC7
SKGBZO
X
OMG
SKGBZ 1
X
OMG
SKGBZ2
X
OMG
SKGBZ3
X
OMG
G(9) 1)
SKGZ
X
OMG
OGIO
SKGZ
X
OMG
SKMBZO
X
OMG
SKMBZ 1
COMMENTS
CHECK ADD WITH CARRY
CHECK SET CARRY
CHECK SKIP ON CARRY
INSTRUCTION
INSTRUCTION
:
RESULT
COMMENTS
1 > A; Bd > 2,0
G(1 > 2)
ADD WITHOUT CARRY
STORE 3 IN 2,0
7>A
CHECKCASC
STORE 12
G(2) 12)
:
:CHECK
:SKC/SC
G(12) 3)
:CHECK
:RC
G(3) 12)
:CHECK
;SEQUENTIAL LBI'S
ALSO SKIPPED (LB12,7 NOT IN 410)
G(2) 7)
G(7) 9)
LOAD CONSTANTS FROM 0
CHECK
G(9) 10)
STORE A - > 5(9)
:
:CHECK
:
;G BIT
G (10 > 7)
:
G(7) 10)
:TESTS
G(10) 7)
RESULT
COMMENTS
:CHECK
G(7) 10)
G(10) 0)
:GTEST
G(O> 10)
CHECK MEMORY BIT TESTS
NO CHANGE
•
to-
W
~
0
Z
a..
0
0
TABLE I. Typical Test Sequence (Continued)
INSTRUCTION
RESULT
COMMENTS
G(10) 7)
NO SKIP
X
OMG
SKMBZ2
X
OMG
INIL
ININ
SKE
X1
OMG
INIL
X
SKMBZ 3
OBD
OGI1
LBI3,11
OGIO
INIL
X
SKMBZO
OBD
NOP
XAS
X
OMG
G(10) 9)
INSTRUCTION
RESULT
WON'T SKIP
SEE THAT L LATCHES RESET
ASSUMEG - > I
Br> 1
SHOULD BE EQUAL
D(15) 0)
RESULT
COMMENTS
RESULT
COMMENTS
STII2
STII9
STIIO
LBI3,O
STII7
STII14
STII5
STII12
STII3
STII10
STII1
STIIB
STII15
STII6
STII13
STII4
STII11
STII2
STII9
STIIO
G(7) 10)
:INIL TEST
D(O> 11)
INSTRUCTION
:XASTEST
LBIO,O
STII7
STII14
STII5
STII12
STII3
STII10
STII1
STII8
STII15
STII6
STII13
STII4
STII11
STII2
STII9
STIIO
LBI1,O
STII7
STII14
STII5
STII12
STII3
STII10
STII1
STII8
STII15
STII6
STII13
STII4
STII11
STII2
STII9
STIIO
LBI2,O
STII7
STII14
STII5
STII12
STII3
STII10
STII1
STII8
STII15
STII6
STII13
INSTRUCTION
INSTRUCTION
LBIO,O
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
COMMENTS
LOAD RAM WITH
CONSTANTS USING
STII
INSTRUCTION
RESULT
COMMENTS
LBI1,O
OMG
LD
XIS
STII4
STII11
3-84
CHECK FOR RAM DATA
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
RESULT
COMMENTS
CHECK FOR RAM DATA
OUTPUT DATA
:MOVE TO NEXT DIGIT
(')
0
TABLE I. Typical Test Sequence (Continued)
INSTRUCTION
RESULT
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
INSTRUCTION
L811,O
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LO
XIS
OMG
LO
XIS
COMMENTS
INSTRUCTION
OUTPUT DATA
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
INSTRUCTION
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
COMMENTS
CHECK FOR RAM DATA
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
COMMENTS
""C
OUTPUT DATA
0
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
RESULT
L813,O
OMG
LD
XIS
OMG
LD
XIS
OMG
LO
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LO
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
OMG
LD
XIS
:MOVE TO NEXT DIGIT
OUTPUT DATA
RESULT
RESULT
COMMENTS
CHECK FOR RAM DATA
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
OUTPUT DATA
:MOVE TO NEXT DIGIT
INSTRUCTION
RESULT
:MOVE TO NEXT DIGIT
OUTPUT DATA
JMPX
:MOVE TO NEXT DIGIT
OUTPUT DATA
RELEASE TEST MODE
INITIALIZE-SELECT ADDRESS X
FOR OGI OR OMG (SELECT L81
FOR KNOWN DATA)
080 (SELECT 8 FOR KNOWN
CONDITION) CHECKS JMP
:MOVE TO NEXT DIGIT
3·85
COMMENTS
Z
-t
m
......
......
LLI
I-
0
Z
D.
0
0
This test sequence is not to be taken as a recommended
test routine and is only shown as an example of what might
be done to test various COPS parts. It is also advisable to
approach measurements in the test mode with some caution. As stated earlier, one can force a large current into the
SO node to place the chip in the test mode. Not only can
this current do damage if unlimited, but it can also cause
local current overloading such that some I/O conditions
may be adversely affected. Obviously this will be more pronounced at higher VCC voltages. A specific example is that
the L output current sink test should only be tested at a
VOUT of O.4V and 0.36 mA as the more stringent tests can
exceed power limits when combined with the SO current.
TABLE I. Typical Test Sequence (Continued)
INSTRUCTION
RESULT
SET TEST MODE
JP X-2
JSRY
RELEASE TEST MODE
EXECUTE CODE (Y)
SET TEST MODE
RET
RELEASE TEST MODE
EXECUTE "X" AGAIN
SET TEST MODE
JPX-2
JSRPZ
RELEASE TEST MODE
EXECUTE CODE
SET TEST MODE
RETSK
VALUE OF ADDRESS
TOGO TO
OUTPUT CHANGE
JID
RELEASE TEST MODE
EXECUTE OUTPUT
SET TEST MODE
LOADA&M
CQMA
OMG
X
OMG
INL
OMG
X
OMG
CHECK JP & JSR
"Y" SHOULD CHANGE THE OUTPUT
CONDITIONS OF "X"
IF AT ALL POSSIBLE
VERIFIES RET
CHECK JSRP & RETSK
MICROWIRETM
"Z" SHOULD CHANGE "X"
OUTPUT CONDITIONS
National's super-sensible MICROWIRE serial data exchange standard allows interfacing to any number of specialized peripherals using an absolute minimum number of
valuable I/O pins; this leaves more I/O lines available for
system interfacing and/or may permit the COPS controller
to be packaged in a smaller (and even lower cost) package.
(MICROWIRE peripherals may also be used with non-COPS
controllers). For further applications information, refer to
COPS Briefs 8 and 9. MICROWIRE makes sense.
DON'T CHANGE Z CONDITIONSRETSK
RELEASE TEST MODE
EXECUTE
SET TEST MODE
LOADA&MTO
LaiD
X064
COMMENTS
FIND VALUE OF ADDRESS IN BLOCK
(4 PAGES)
AT OR JUST BEFORE AN OUTPUT
CHANGE SET A & M TO ADDRESS
OF "VALUE"
CHECKSJID
The example below illustrates the power and versatility of
MICROWIRE via an extreme example-using one of each
type of peripheral with a single controller.
LOAD A & M WITH A UNIQUE ADDRESS
SUCH THAT CONTENTS OF THAT
ADDRESS WILL BE SEEN ON G
;OR USE THIS CAUSE THE DATA COMES
;FROM YOUR TESTER ANYWAY
LQUID & CQMA CHECKED
G - > 2
INL TEST (COPY OF 2nd BYTE)
G->E
COPS'·
MICROCONTROLLER
MICROWIRE
INTERFACE
01
LCD
DISPLAY
COP432
SK
SYSTEM
INTERFACE
DI
DI
SK
SK
DO
DO
ROM. RAM,
OR PROM
SYSTEM
CONTROLS
VF
DISPLAY
TL/DD/6940-4
3·86
o
COP431 SERIES, 8-BIT AID
CONVERTERS
COP472-3 LIQUID CRYSTAL DISPLAY CONTROLLER
The COP431 series is an 8-bit successive approximation
AID converter with a serial I/O and configurable input mUltiplexer with up to 8 channels. The serial I/O is configured to
comply with the NSC MICROWIRE serial data exchange
standard for easy interface to the COPS family of processors, and can interface with standard shift registers or other
ILPs.
The 2, 4 or 8 channel multiplexers are software configured
for single-ended or differential inputs as well as channel assignment.
The differential analog voltage input allows increasing the
common-mode rejection and offsetting the analog zero input voltage value. In addition, the voltage reference input
can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution.
COP452L FREQUENCYICOUNTER PERIPHERAL
The COP452L contains 2 independent 16-bit counter/register pairs, and is well suited to a wide variety of tasks involving the measurement and/or generation of times and/or frequencies. Included are multiple tones, precise duty cycles,
event counting, waveform measurement, "white noise" generation, and A-D/D-A conversions. An on-chip zero-crossing detector can trigger a pulse with a programmed delay
and duration.
COP470 V.F. DISPLAY DRIVER
The COP470 is designed to directly drive a multiplexed Vacuum Fluorescent display. Data is loaded serially and held in
internal latches. The COP470 has an on-chip oscillator to
multiplex four digits of eight segment display, and may be
cascaded and/or stacked to drive more digits, more segments, or both.
With the addition of external drivers, the COP470 also provides a convenient means of interfacing to a large-digit LED
display.
The COP472-3 Liquid Crystal Display (LCD) Controller
drives a multiplexed liquid crystal display directly. Data is
loaded serially and is held in internal latches. The
COP472-3 contains an on-chip oscillator and generates all
the multilevel waveforms for backplanes and segment outputs on a triplex display. One COP472-3 can drive 36 segments multiplexed as 3 x 12 (4112 digit display). Two
COP472-3 devices can be used together to drive 72 segments (3 x 24) which could be an 8% digit display.
COP494 256-BIT SERIAL ELECTRICALLY ERASABLE
PROGRAMMABLE MEMORY
The COP494 is a 256-bit non-volatile memory. The device
contains 256 bits of read/write memory divided into 16 registers of 16 bits each. Each register is serially read or written
by the COP400 Family Controller. Written information is
stored in a floating gate cell with at least 10 years of retention.
COP498/COP499 LOW POWER CMOS RAM AND TIMER
The COP498 low power CMOS Random-Access Memory
and Timer is an external memory and timer chip with the
simple MICROWIRE serial interface. The device contains
256 bits of read/write memory divided into 4 registers of 64
bits each. The COP498 also contains a crystal-based timer
for timekeeping purposes, and can provide a "wake-up" signal to turn on a COPS controller.
The COP498 can be used for low power standby memory
and can also be used for low power operation by turning the
controller off and on, on a duty cycle basis.
The COP499 Low Power CMOS Random-Access Memory is
an external memory and switch chip with the simple
MICROWIRE serial interface. The device contains 256 bits
of read/write memory divided into 4 registers of 64 bits
each. The COP499 also contains circuitry that enables the
user to turn a controller on and off while maintaining the
integrity of the memory.
3-87
o"tJ
Z
o-t
m
.....
.
C")
~ Current Consumption in
NMOSCOPSTM
M icrocontrollers
National Semiconductor
Application Brief 3
Len Distaso
THE EFFECT OF VOLTAGE
Current consumption in the N-channel COPS microcontrollers is a function of manufacturing process variation and
three operating condition parameters: temperature, voltage,
and frequency. The aforementioned process variation
swamps all other variations. Of the operating condition parameters, temperature is by far the most significant. This
application brief is intended to provide the user with a guide
to approximate the worst-case current consumption of the
NMOS COPS microcontroller at a given set of operating
conditions and to approximate the current variation with respect to temperature, voltage, and frequency.
The operating voltage of the microcontroller has a slightly
greater effect on current consumption than the operating
current. Current consumption increases with increasing operating voltage. On examining the MOS device equations,
one finds that the device current is proportional to the
square of a voltage term:
I a (VGs-Vr)2
where:
I = device current
VGS = device gate to source voltage
Vr = device threshold voltage.
Note that this is a guide only. Some approximations in the
equations have been made. Only the current values found in
the various device data sheets are guaranteed. Values derived by the techniques described here are neither guaranteed nor tested.
In the N-channel COPS devices, current is consumed primarily by the load devices. Most of these devices, though
not all, are depletion mode devices with the gate and source
tied together. Thus, VGS is O. Therefore, the primary mechanism for current consumption as related to voltage is variation in Vr. The depletion mode load devices in the COPS
NMOS microcontrollers have geometries (length is much
greater than width) which tend to minimize variations in
threshold voltage. There are additional second order effects
related to operating voltage, such as effective channel
lengths shortening due to increased voltage, which affect
current consumption. These effects, however, do not have a
major impact on current consumption. Note also that the
threshold voltage is affected by process variation. This is
one of the areas where the process variation contributes to
the device-to-device variation in current consumption. The
user can typically expect to see a 5% to 10% variation in
current due to operating voltage with the maximum current
consumption occurring at maximum operating voltage.
PROCESS VARIATION
If a user were to measure the current in two identical COPS
microcontrollers under identical operating conditions (Le.,
same temperature, voltage, and frequency), the results
would probably be different. The reason for this difference is
variation in the manufacturing process within its valid range.
This variation can be quite substantial; a range of about 3 to
1 can be expected. This variation is essentially a device-todevice variation and basically not related to the operating
conditions of the device. The three operating condition parameters (temperature, voltage, and frequency) affect current in the manner described below.
The values for current consumption in the various device
data sheets are worst-case maximum values and assume
that the processing parameters are at the end of the valid
range which will produce maximum current consumption in
the device.
THE EFFECT OF TEMPERATURE
THE EFFECT OF FREQUENCY
The frequency effect on current consumption is primarily a
device design consideration. The higher the intended operating frequency, the higher the maximum current. However,
once the device is designed in this process for a given maximum frequency, there is little variation with operating frequency. To be sure, there is some variation. As might be
expected, current consumption is greater at higher frequencies. The variation is, however, slight-typically less than
5%.
Of the three operating parameters affecting current consumption in the NMOS COPS microcontrollers, temperature
has by far the greatest impact. The relationship is given by
the following simplified, empirical equation:
I(T) = 10(T/To)-3/2
where:
To = reference junction temperature in OK
T = device junction temperature in OK
10 = device current at temperature To
I(T) = device current at temperature T.
Although this equation is for a single transistor, it can be
applied to the entire microcontroller since all the devices
are made with the same process and will exhibit the same
3-88
characteristics. It should also be noted that the temperatures involved are device junction temperatures. The junction temperature is essentially a function of two items:
Tj = F(TA, OJ A)
where:
AN EXAMPLE
The COP320L has a specified maximum current of 10 mAo
In this process, maximum current occurs at minimum temperature, which is -40°C in this case. It is desired to find
the maximum current at 25°C. Therefore,
Tj = junction temperature
TAO = -40°C = 233°K
T A = ambient temperature
TA = 25°C = 298°K
0jA = package thermal characteristic.
10=10mA
Tj = TA
+ 25°K
where Tj and T A are as defined previously. Note that this is
an approximation. It is not necessarily true for all packages,
or any package. The relationship between junction temperature and ambient temperature is also not necessarily linear.
However, the approximation is reasonable and provides a
workable framework.
Substituting the junction temperature relationship into the
current equation, the following equation results:
I(TA)
~
10 (
TA
TAO
+ 25 )-3/2
+ 25
where:
TAO = reference ambient temperature, oK
TA = ambient temperature, oK
10 = current at ambient temperature TAO
I(TA) = current at ambient temperature T A.
.
eN
I(TA) to be determined
The preceding relationship indicates that the package for
the device will affect current because the package affects
junction temperature. This should not come as a surprise.
One need only consider the differences between ceramic
and plastic packages to find support for this claim.
For purposes of discussion, it will be assumed that junction
temperature is given by the following:
»
m
T A + 25 ) -3/2
I(TA) ~ 10 ( TAO + 25
~
10 mA (323/258)
~
7.14 mA.
Thus the maximum current for the COP320L at 25°C is approximately 7 mA.
CONCLUSION
A means is provided to the user to approximate the current
variation of the NMOS COPS microcontroller over its valid
operating range. A given device will consume its maximum
current at maximum operating voltage, maximum operating
frequency, and minimum operating ambient temperature.
Conversely, minimum current will be consumed at minimum
operating voltage, minimum operating frequency, and maximum operating ambient temperature.
The user should remember that this document is intended
as a guide only. The values produced here are reasonable
but they are approximations and are not guaranteed values.
The user should also remember that the equations and
methods discussed here do not involve process variation.
The numbers calculated approximate the worst-case maximum current values at a given set of operating conditions.
The user should be prepared to see a wide range of values
over the course of volume production.
•
3-89
"II:t
ED
1 clock
which is 1800 out of phase with the <1>2 clock. It is the 1 and
<1>2 clocks to which all operation is referenced but for our
purposes the SK will suffice. Program instructions are read
on a rising <1>1 edge and executed during the <1>1, <1>2 cycle
time. Here we see the EN register interrupt enable bit EN2
being set with an LEI instruction. Interrupts are actually enabled on the <1>2 leading edge of the second byte of the
instruction point @. Timing for an INTERRUPT DISABLE is
essentially the same.
nized at point @ it will not be acted upon until all successive
transfer of control instructions are executed as defined in
the data sheets.
Because of gate delays it is doubtful that if an interrupt had
been generated in time to meet the leading <1>1 edge at point
® that the EN1 enable bit would have been on in time to
meet the WINDOW of OPPORTUNITY.
By doing a worst case analysis one can see that in order to
guarantee reception of an asynchronous interrupt IN1 must
remain low for at least 2 instruction cycles. The analysis is
as follows. Assuming that interrupts had been enabled prior
to point 1 and <1>2 clock per processor execution cycle
itne instruction cycle time is made up of 2 <1>1 's and 2's.
Therefore 1 instruction cycle time in a dual COPS is equivalent to 2 instruction cycle times in a single COPS as far as
1's, 2's and interrupts are concerned.
The interrupt line is sampled on the leading edge of <1>1 as
shown and interrupts are recognized if the minimum setup
and hold times shown are satisfied. Note that the guaranteed times are longer than the typicals. The interrupt signal
conditioning circuitry contains a falling edge detection circuit
(a one shot) which requires that in addition to meeting the
setup and hold times, the enable interrupt bit EN1 must
have been turned on sometime before the end of the WINDOW of OPPORTUNITY shown. If not, the interrupt will be
missed and another high to low IN1 transition will be required. EN1 is automatically disabled upon interrupt recognition at point ®. Note that although the interrupt is recog-
L
PROGRAM
INSTRUCTION
Em
IN1
LEI 2
33
62
I
----------------;r"T'·-1i-I-------~=~:! ' \
INTERRUPT
DlSABLEO
l-tWD-1
WINOOWOF
OPPORTUNITY
TL/DD/5180-1
FIGURE 1. COP Interrupt Diagram
Parameter
ts
tn
two
Min
Typ
Max
%tCYC
%tCYC
200 ns
200 ns
% tCYC - 600 ns
0
-00
3-92
l>
OJ
I
Protecting Data in Serial
EEPROMs
National Semiconductor
Application Brief 15
Paul Lubeck
National offers a broad line of serial interface EEPROMs
which share a common set of features:
it is necessary to place the device in the Program Enable
Mode',. Following placing the device in the Program Enable
Mode, Erase and Write will remain enabled until either executing the Disable instruction or removing Vee. Having Vee
unexpectedly removed often results in uncontrolled interface signals which could result in the EEPROM interpreting
a programming instruction causing data to be destroyed.
• Low cost
• Single supply in all modes (+5V ± 10%)
• TTL compatible interface
• MICROWIRETM compatible interface
• Read-Only mode or read-write mode
This Application Brief will address protecting data in any of
National's Serial Interface EEPROMs by using read-only
mode.
Whereas EEPROM is non-volatile and does not require Vee
to retain data, the problem exists that stored data can be
destroyed during power transitions. This is due to either uncontrolled interface signals during power transitions or noise
on the power supply lines. There are various hardware design considerations which can help eliminate the problem
although the simplest most effective method may be the
following programming method.
All National Serial EEPROMs, when initially powered up are
in the Program Disable Mode·. In this mode it will abort any
requested Erase or Write cycles. Prior to Erasing or Writing
.....
U1
Upon power up the EEPROM will automatically enter the
Program Disable Mode. Subsequently the design should incorporate the following to achieve protection of stored data.
1) The device powers up in the read-only mode. However,
as a backup, the EWDS instruction should be executed
as soon as possible after Vec to the EEPROM is powered up to ensure that it is in the read-only mode.
2) Immediately preceding a programming instruction
(ERASE, WRITE, ERAL or WRAL), the EWEN instruction
should be executed to enable the device for programming; the EWDS instruction should be executed immediately following the programming instruction to return
• EWDS or WDS, depending on exact device.
tEWEN or WEN. depending on exact device.
nnI1.IUUUl...
SK
II
EWEN
EWDS
01----"'0
I~,,-_L _
STANDBY
0~1A1I
ENABLE=11
DISABLE=DO
TLlD17085-1
FIGURE 1. EWEN, EWDS Instruction Timing
MAIN PDWER SUPPLY
4.5Y·5.5Y
Yee
r
•
1. . . _____
r-
L.AI~i:'Nio':1. ~:~~1O" ~L
J
INSTRUCTION~~~
(ERASE, WRITE,
ERAL OR WRAl)
TLlD17085-2
'EWDS must be executed before Vee drops below 4.5V to prevent accidental data loss during subsequent power down and/or power up transients.
FIGURE 2. Typical Instruction Flow for Maximum Data Protection
3-93
II)
.....
•
III
Z
National Semiconductor
Application Note 326
Jim Murashige
A Users Guide to COPSTM
Oscillator Operation
W
N
en
The following discussion is an overview of the COPS oscillator circuits meant to give the reader a working knowledge of
the circuits. Although the descriptions are very general and
light on detail; a background in complex frequency analysis
is necessary. For additional information the references cited
should be consulted as well as the many works on oscillator
theory.
There are 2 basic circuits from which all of the COPS oscillator options are provided. (See option lists in individual data
sheets.) The first and simplest in description is the astable
one shot of Figure 1 which gives us our RC oscillator option.
A 1 and A2 are inverters with A 1 possessing a Schmitt trigger input. T1 is a large N channel enhancement MaS FET.
Operation with the external R-C shown is as follows. Assuming C is initially discharged the CKI pin is low forcing T1
off. As C charges through R the trigger point of A 1 is eventually reached at which time T1 is turned on discharging C
and beginning a new cycle. Although almost any combination of R-C could be chosen, we would ideally like to have
as short a discharge time as possible thereby eliminating
the high variability in T1 drain current from device to device
as a timing factor. For this reason R is chosen very large
and C very small. This choice also leads to minimum R-C
power dissipation. For the CKI Schmitt trigger clock input
option the T1 MaS FET is merely mask disabled from the
oscillator circuit.
Vee
FEEDBACK
NETWORK
TL/OO/S139·2
FIGURE 2. Phase Shift Oscillator
The conditions under which the circuit will oscillate are described by the Barkhausen Criterion which states that oscillation will occur at the frequency for which the total loop
phase shift from Xi to xf is 0° or a multiple of 360° (i. e., Xf is
identical to Xi). In addition the total loop gain must be > 1 to
insure self propagation. The inverting amplifier shown between Xi and Xo provides 180° of phase shift thus leaving the
feedback network to supply the other ± 180°. The feedback
network can be comprised of active or passive components
but highly effective oscillators are possible using only passive reactive components and the general configuration of
Figure 3.
If you work out the feedback loop equations for Figure 3 it
can be shown that in order to achieve ± 180° phase shift:
X1
+ X2 + X3
= 0
(1)
X1 and X2 must both be inductors or capacitors
(2)
therefore X3 is inductive if X1 is capacitive and vice versa
if X1 and X2 are capacitors it is a Colpitts Oscillator
X1 and X2 are inductors it is a Hartley Oscillator
TLIOO/S139·1
Ell
FIGURE 1. R-C Oscillator
The second oscillator circuit is the classic phase shift oscillator depicted in Figure 2. Found not only on COPS but on
most other microprocessor circuits it is the simplest oscillator in terms of component complexity but the most difficult
to analyze.
CKO
TL/OO/S139·3
FIGURE 3. Typical Feedback Configuration
3-97
~ r-----------------------------------------------------------------------------~
N
C")
Z
c(
1 ~1 +1
Atfb=27T LC
LCc
The Colpitts configuration is commonly shown in microprocessor oscillator circuits (Figure 5) with the inductive X3 replaced by a crystal for reasons we shall soon see. The
equivalent electrical model of a crystal is shown in Figure 4b
and a plot of its Reactance versus Frequency shown in Figure 4c. R-L-C represent the electro-mechanical properties
of the crystal and Co the electrode capacitance. There are 2
important points on the reactance curve labeled fa and fb.
which is just a little higher than fa the crystal is at parallel
resonance and appears very inductive or capacitive. Note
that the cyrstal will only appear inductive between fa and fb
and that it becomes highly inductive very quickly. In addition
fb is only a fraction of a percent higher than fa. Therefore
the only time that the crystal will satisfy the X3 = - (X1 +
X2) condition in the Colpitts configuration of Figure 5 is
when the circuit is OSCillating between fa and fb. The exact
frequency will be the one which gives an inductive reactance large enough to cancel out:
1~
LC
At fa = 27T
the crystal is at series resonance with Land C canceling
each other out leaving only a nonreactive R for 0 phase
shift. This mode of operation is important in oscillator circuits where a non-inverting amplifier is used and o· phase
shift must be preserved.
X1
+ X2
= _1_
wC1
+ _1_
wC2
=
.! [-.!... + -.!...]
w C1
C2
=
~ [-.!..]
27Tf CL
Therefore by varying C1 or C2 we can trim slightly the oscillator frequency.
-ctr
TL/DD/5139·4
a. Circuit Symbol
b. Electrical Equivalent
+
F==-:~_1~..;:S...- - - - . FREQUENCY
TL/DD/5139·6
c. Reactance Versus Frequency
FIGURE 4. Quartz Crystal
~C1
~C2
TL/DD/5139·7
FIGURE 5. Colpitts Oscillator
3-98
TL/DD/5139·5
Of course the feedback network doesn't have to have the·
configuration of Figure 3 and can be anything so long as the
Barkhausen Phase Shift Criterion is satisfied. One popular
configuration is shown in Figure 7where the phase shift will
be 180·
The Q of a circuit is often bounced around in comparing
different circuits and can be viewed graphically here as the
slope of the reactance curve between fa and fb. Obviously
the steeper the curve the smaller the variation in f necessary to restore the Barkhausen Phase Shift Criterion. In addition a lower Q (more R) means that the reactance curve
won't peak as high at fb' necessitating a smaller X1 + X2.
When selecting crystals the user should be aware that the
frequency stamped on the cans are for either parallel or
series resonance, which, although very close, may matter
significantly in the particular application.
>
Z
•
W
N
0')
1
at f = (21TRcJ6)
An actual MOS circuit implementation of Figure 5 is shown
in Figure 6. It consists of a MOS inverter with depletion load
and the crystal 1T network just presented. External to the
COPS chips are the Rt and Rg resistors. Rt provides bias to
the MOS inverter gate V9 = Vo. Since the gate draws no
current Rt can be very large (Mn) and should be, since we
do not wish it to interact with the crystal network. Rg increases the output resistance of the inverter and keeps the
crystal from being over driven.
TL/DD/5139·9
FIGURE 7. R-C Phase Shift Oscillator
~C2
TLl00/5139·8
FIGURE 6. MOS Oscillator
•
3-99
CD
~
•
~
-
REFERENCES
1. Crystai/lNS8048 Oscillator, AN-296, March 1982, National Semiconductor
2. Oscillator Characteristics of COPS Microcontrollers,
CN-5, Feb. 1981, National Semiconductor
3. Integrated Electronics, Chapter 14, Millman and Halkias
1972
4. Handbook of Electronics Calculations, Chapter 9, Kaufman and Seidman 1979
5. 1982 COPS Microcontroller Databook, National Semiconductor
usa
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TL/DD/5139-10
3-100
Implementing an a-Bit
Buffer in COPSTM
National Semiconductor
Application Note 329
David Pointer
Sometimes a COP microcontroller must input and/or output
a·bit data; for instance, when handling ASCII data. In some
applications, the processor must also provide temporary
storage for a·bit data before it is output. The COP instruction
set and RAM structure lend themselves very nicely to pro·
viding a 32 digit, a·bit buffer for a solution to these applica·
tions.
Such a large buffer is possible using a COP440 or a
COP444L. The other members of the COP400 family with
half as much RAM as these two would provide a 16 digit a·
bit buffer using the techniques described in this example.
Four adjacent RAM registers (16 digits each) are required.
Referring to Figure 1, registers 4, 5, 6, and 7 are used for
the buffer. Each RAM location contains 4 bits, so 2 loca·
tions will be used to store a byte of data. But these RAM
locations are not adjacent to each other. You will note that
the MSD of digit number OA hex is in RAM location (4, A)
while the LSD of the same digit is in RAM location (6, A).
input pointer, and those labelled OPM and OPL are the
MSD and LSD of the output pointer. Each pointer's function
is to store an a·bit counter whose value ranges from 00 hex
thru 1F hex. The input pointer's value is used for storing the
temporary storage buffer contents into the digit with the
same number. For example, if the input pointer equals 14
hex, then the contents of CHARM would be stored in RAM
location (5, 4) and the contents of CHARL would be stored
in RAM location (7, 4). The output pointer's value is used for
retrieving a digit from the buffer and putting it in CHARM and
CHARL. For instance, if the output pointer equals 05 hex,
then the contents of RAM location (4, 5) would be trans·
ferred to CHARM and the contents of RAM location (6, 5)
would be transferred to CHARL.
A simple example of one possible application of the buffer is
flowcharted in Figure 2. In this example, data is input to
CHARM and CHARL, then stored in the buffer. An output
device (a printer) is checked to see if it is ready to receive
data. If it is, data is brought out of the buffer and put in
CHARM and CHARL for output to the printer.
Pages 3 and 4 contain a listing of the subroutines needed to
perform the data transfers in the 32·digit, a·bit buffer.
The 2 RAM locations CHARM and CHARL are used for tem·
porary storage of an a·bit value.
In addition, 4 RAM locations are used for buffer pOinters:
those labelled IPM and IPL are the MSD and LSD of the
BD=
BR=2
IPM
TEMP STORAGE
BUFFER
BR=3
DPM
I
BR=4
OF
DE
DO
DC
DB
OA
09
08
07
06
05
04
03
02
01
00
MSO OF
DIGIT M
1F
1E
10
tC
1B
1A
19
18
17
16
15
14
13
12
11
10
MSO OF
DIGIT M
OF
DE
00
DC
DB
OA
09
08
07
06
05
04
03
02
01
00
LSD OF
DIGIT M
1F
1E
10
1C
18
1A
19
18
17
16
15
14
13
12
11
10
LSD OF
DIGIT M
BR=51
BR=61
BR=7
TLIDD/51B1-1
FIGURE 1. a·Bit Buffer RAM Map
3·101
•
CHAR = CHARM AND CHARL
IP = IPM AND IPL
OP =DPM AND DPL
TL/DD/5181-2
FIGURE 2. Buffer Example Flowchart
3-102
.
l>
COP CROSS ASSEMBLER
BUFFER
3
4
01BC
9
0020
002C
12
002F
13
002E
14
003F
15
003E
16 000 00
17
0080
18
19
20 080 233E
21 082 50
22 083 233F
23 085 54
24 086 12
25 087 25
26 088 23AO
27 08A 05
28 08B 23AC
29 08D 48
30
31
32
33
34 08E 232E
35 090 50
36 091 232F
37 093 54
38 094 12
39 095 2320
40 097 26
41 098 232C
42 09A 06
43 09B 48
44
45
10
11
z
1
W
N
<.0
;**************************************
;***
***
;*** 8-BIT RAM BUFFER SUBROUTINES ***
;***
***
;**************************************
1
2
5
6
7
8
PAGE:
;THESE ARE SUBROUTINES FOR IMPLEMENTING A 32 BYTE
;BUFFER IN A COP440 OR COP444L RAM 9/3/82
.CHIP 444
.TITLE BUFFER
CHARM
2,13
;TEMPORARY STORAGE BUFFER
=
CHARL
2,12
;TEMPORARY STORAGE BUFFER
IPM
;INPUT POINTER MSD
2,15
=
IPL
;INPUT POINTER LSD
2,14
=
OPM
3,15
;OUTPUT POINTER MSD
=
OPL
;OUTPUT POINTER LSD
3,14
CLRA
.PAGE 2
;MTOC IS A SUBROUTINE THAT TRANSFERS M(OPM) AND M(OPL) TO
;CHARM AND CHARL
MTOC:
LDD
;LOAD LSD OUTPUT POINTER
OPL
CAB
;WHICH IS BD
;LOAD MSB OUTPUT POINTER
LDD
OPM
AISC
4
;MAKE BR EQUAL 4 OR 5
XABR
LD
;LOAD M(OPM), MAKE BR = 6
2
XAO
;M(OPM) TO CHARM
CHARM
LD
;LOAD M(OPL)
;M(OPL) TO CHARL
XAD
CHARL
RET
MSD
LSD
FOR B
OR 7
;CTOM IS A SUBROUTINE THAT TRANSFERS CHARM AND CHARL TO
;M (IPM) AND M(IPL)
IPL
LDO
;LOAD LSD INPUT POINTER
CTOM:
CAB
;WHICH IS BD
;LOAD MSD INPUT POINTER FOR BR
LDD
IPM
AISC
4
;MAKE BR = 4 OR 5
XABR
LDO
CHARM
;LOAD MSD TEMP STORAGE
2
;TO M(OPM) , MAKE BR = 6 OR 7
X
;LOAD LSD TEMP STORAGE
LDO
CHARL
;TO M(OPL)
X
RET
3-103
en
N
Cf)
Z•
ill(
COP CROSS ASSEMBLER
BUFFER
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
09C
090
09E
09F
OAO
OA1
OA2
OA3
OA4
OA5
OA6
OA7
OA8
20
3D
22
00
30
44
04
00
30
44
06
45
48
PAGE:
2
• FORM
iINCREMENTS INPUT POINT OR OUTPUT POINTER, ROLLS OVER
iAT 1F HEX
INCIP: LBI
IPL
iPOINT TO LSD OF POINTER
INCOP: LBI
OPL
SC
iC=l FOR INCREMENT
CLRA
ASC
;INCREMENT RAM VALUE
NOP
;NEGATES SKIP CONDITION
XIS
;STORE AND POINT TO (X,F)
CLRA
;PROPAGATE CARRY, IF ANY, TO MS
ASC
NOP
X
;STORE
RMB
1
;ROLL OVER AT X'lF
RET
.END
COP CROSS ASSEMBLER
BUFFER
PAGE:
3
CHARL 002C
CHARM 0020
CTOM
008E
INCOP 0090 * IPL
IPM
002E
002F
OPL
003E
OPM
003F
NO ERROR LINES
42 ROM WORDS USED
444 ASSEMBLY
COP
SOURCE CHECKSUM = C6A5
INPUT FILE
6:RBUFFC. SRC VN:
5
*
INCIP
MTOC
3-104
009C
0080
*
*
Designing with the
NMC9306/COP494 a
Versatile Simple to Use
E2PROM
National Semiconductor
Application Note 338
Masood Alavi
This application note outlines various methods of interfacing
an NMC9306/COP494 with the COPSTM family of microcontrollers and other microprocessors. Figures 1-6 show
pin connections involved in such interfaces. Figure 7 shows
how parallel data can be converted into a serial formatto be inputted to the NMC9306; as well as how serial data outputted
from an NMC9306 can be converted to a parallel-format.
4. No battery back-up required for data-retention, which is
fully non-volatile for at least 10 years at room-ambient.
The second part of the application note summarizes the key
points covering the critical electrical specifications to be
kept in mind when using the NMC9306/COP494.
The third part of the application note shows a list of various
applications that can use a NMC9306/COP494.
GENERIC CONSIDERATIONS
A typical application should meet the following generiC
criteria:
1. Allow for no more than 10,000 E/W cycles for optimum
and reliable performance.
2. Allow for any number of read cycles.
3. Allow for an erase or write cycle that operates in the
10-30 ms range, and not in the tens or hundreds of ns
range as used in writing RAMs. (Read vs write speeds
are distinctly different by orders of magnitude in
E2PROM, not so in RAMs.)
SYSTEM CONSIDERATIONS
When the control processor is turned on and off, power
supply transitions between ground and operating voltage
may cause undesired pulses to occur on data, address and
control lines. By using WEEN and WEDS instructions in conjunction with a LO-HI transition on CS, accidental erasing or
writing into the memory is prevented.
The duty cycle in conjunction with the maximum frequency
translates into having a minimum Hi-time on the SK clock. If
the minimum SK clock high time is greater than 1 /Ls, the
duty cycle is not a critical factor as long as the frequency
does not exceed the 250 kHz max. On the low side no limit
exists on the minimum frequency. This makes it superior to
the COP499 CMOS-RAM. The rise and fall times on the SK
clock can also be slow enough not to require termination up
to reasonable cable-lengths.
Since the device operates off of a simple 5V supply, the
signal levels on the inputs are non-critical and may be operated anywhere within the specified input range.
Vee
Vee
12k
0.051"F
NMC93061 DO
COP494
01
Vss
COP42o
•
100 pF
SK
LO-L7. GO-G3. Dl-03
TL/D/5286-1
FIGURE 1. NMC9306/COP494 - COP420 Interface
3-105
STANDARD
,J'
iiii
IN1
CE
IN2
SK
SI
CDP
IN3 PROCESSOR DO
Wii
iNf
fiEffi
GO
D1
RESET
D2
D3
":'
TD OTHER
,..PI
TL/D/5286-2
FIGURE 2. NMC9306 - Standard /-LP Interface Via COP Processor
ADO
AD7
NSCBOO™
CPU
.....
...
'II1II
". AD7
ADO
AD13
CE
1m
Wii
iiD
Wii
ALE
10TIM
RESET OUT
PAD
PA7
NSCB10
RAM
110
TIMER
ALE
10TlM
PBO
PB7
PCO
PC5
.....
...
~
~
~
~
'II1II
PORT A
B BITS
PORT B
B BITS
NMC9306
BANK
PORT C
". 6 BITS
TIMER·IN
TIMER·OUT
Rmf
TL/D/5286-3
PAO
PA1
PA2-7
~
~
~
SK
}
DilDO
Common to all 9306's
6CS for 6- 9306's
• SK Is generated on port pins by blt·set and blt·clear operations In software. A symmetrical duty cycle Is not critical.
• CS Is set In software. To generate 10-30 ms write/erase the timer/counter Is used. During write/erase. SK may be turned off.
FIGURE 3. NSCBOOTM to NMC93061nterface (also Valid for BOB5/BOB5A and B156)
3·106
...
ADD
DECODE
r
AO-A15
DO
~
MI
lORD
RO
MK3BBO
ZBO
CPU
~
...
....
DO CE CID BIA
AD .....
DATA BUS r 07
A7 "'III PORT A 110
..... 8 BITS
.... Mi
lORD
"'III PlIO CTRL .,
RD
MK3BB1
r
NMC9306
BANK 1
(6)
III..
BO ....
B7 "'III PORT B 110 r
NMC9306
BANK 2
(6)
"'III
ZBDI
iNi
PIO
IEI*
...
IEO*
INTERRUPT
CONTROL LINES
.....
(3)
TL/D/S2B6-4
Z80-P10
9306
AO
SK
A1
DilDO
A2-A7
CS1-CS6
}
Common to all 9306's (Bank 1)
• Only used If priority Interrupt daisy chain Is desired
• Identical connection for Port B
FIGURE 4. Z80 -
NMC9306 Interface Using Z80-PIO Chip
P17
P16
DATA
01
NMC93D6
DO # 1
CLOCK
SK CS1
P15
P24
P27
INSB04B
CS2
P14
P13
CS9
P12
DBB
P11
•
EN
!---~-CS2
~----CS9
TLlD/S286-S
• SK and 01 are generated by software. It should be noted that at 2.72 fLs/lnstruction. The minimum SK period achievable will be 10.88 fLs or 92 kHz, well
within the NMC9306 frequency range.
• DO may be brought out on a separate port pin If desired.
FIGURE 5. 48 Series J.LP -
3-107
NMC9306 Interface
co
,------------------------------------------------------------------------------------,
C")
C")
z•
c(
P2D
P21
P22
P23
.r-+
P2D
P21
P22
P23
S
..{ L~I
--" CS1
CS2
INS8243
110
CS3-CS6 ...
EXPANDER P5
DBD
INSBD48
DB7
JI'"
P6
CS7-CS10---.
JI'"
Wii
PRDG
iiii P24
PRDG
....
'~
CS
P7
CS
CO
GO
aD
C1
G1
Q1
C2
G2
a2
A1
AD
...
DO
JI'" D7
INS8253
iiiii
iiiW
0
TIMER 110
TLlD/52B6-6
Expander outputs
Ol}
SK
(COMMON)
Port 5-6
CS1
CS2
CS3-CS10
Port 7
00 (COMMON)
Port 4
FIGURE 6. 8048 I/O Expansion
NMC9306/COP494
00
~-""'P'-"'"
SK
PARALLEL OUT
SERIAL IN
1+---+-- CLOCK
PIN 9
~...---t''''''
PARALLEL IN
SERIAL OUT
TLlD/52B6-7
FIGURE 7. Converting Parallel Data Into Serial Input for NMC9306/COP494
3-108
l>
z
I
W
W
CD
SK
DI
cs
~________I~_I~~
DD
Min
Max
tCYCLE 0
tOls400
t01H 400
tcss 200
tcsH 0
tpoo
tp01
250 kHz
ns
ns
ns
ns
21l s
21l s
TlIO/5286-8
FIGURE 8. NMC930S/COP494 Timing
THE NMC930S/COP494
5.
Extremely simple to interface with any IlP or hardware logic.
The device has six pins for the following functions:
Pin 1
CSt
HI enabled
Pin 2
Pin3
SK
Serial Clock input
01
Pin4
DO··
For instruction or data
input
For data read, TRI-STATE@
otherwise
Pin 5
GNO
Pin8
VCC
No Connect
Pins 6-7
6.
7.
For5Vpower
No termination required
8.
·Following an E/W instruction feed, CS is also toggled
low for 10 ms (typical) for an E/W operation. This internally turns the VPP generator on (HI-LO on CS) and off
(LO-HI on CS).
9.
··01 and DO can be on a common line since DO is TRISTATED when unselected DO is only on in the read
mode.
USING THE NMC930S/COP494
The following points are worth noting:
1.
2.
3.
4.
Stored data is fully non-volatile for a minimum of ten
years independent of Vcc, which may be on or off.
Read cycles have no adverse effects on data retention.
Up to 10,000 E/W cycles/register are possible. Under
typical conditions, this number may actually approach
1 million. For applications requiring a large number of
cycles, redundant use of internal registers beyond
10,000 cycles is recommended.
Data shows a fairly constant E/W Programming behavior over temperature. In this sense E2PROMs supersede EPROMs which are restricted to room temperature programming.
As shown in the timing diagrams, the start bit on 01
must be set by a ZERO - ONE transition following a CS
enable (ZERO - ONE), when executing any instruction.
ONE CS enable transition can only execute ONE instruction.
In the read mode, following an instruction and data
train, the 01 can be a don't care, while the data is being
outputted Le., for next 17 bits or clocks. The same is
true for other instructions after the instruction and data
has been fed in.
10. The data-out train starts with a dummy bit 0 and is
terminated by chip deselect. Any extra SK cycle after
16 bits is not essential. If CS is held on after all 16 of
the data bits have been outputted, the DO will output
the state of 01 till another CS LO-HI transition starts a
new instruction cycle.
SK clock frequency should be in the 0-250 kHz range.
With most IlPS this is easily achieved when implemented in software by bit-set and bit-clear instructions,
which take 4 instructions to execute a clock or a frequency in the 100 kHz range for standard IlP speeds.
Symmetrical duty cycle is irrelevant if SK HI time is ~
2 Ils.
CS low period following an E/W instruction must not
exceed the 30 ms max. It should best be set at typical
or minimum spec of 10 ms. This is easily done by timer
or a software connect. The reason is that it minimizes
the 'on time' for the high Vpp internal voltage, and so
maximizes endurance. SK-clock during this period may
be turned off if desired.
11. When a common line is used for 01 and ~O, a probable
overlap occurs between the last bit on 01 and start bit
on ~O.
12. After a read cycle, the CS must be brought low for
1 SK clock cycle before another instruction cycle can
start.
All commands, data in, and data out are shifted in/out on
rising edge of SK clock.
Write/erase is then done by pulsing CS low for 10 ms.
All E/W instructions must be preceded by EWEN and
should be followed by an EWOS. This is to secure the
stored data and avoid inadvertent erase or write.
A continuously 'on' SK clock does not hurt the stored
data. Proper sequencing of instructions and data on 01
is essential to proper operation.
All instructions are initiated by a LO-HI transition on CS followed by a LO-HI transition on 01.
READ - After read command is shifted in
01 becomes don't care and data can
be read out on data out, starting
with dummy bit zero.
WRITE - Write command shifted in followed by
data in (16 bits) then CS pulsed low
for 10 ms minimum.
3-109
•
co
~
Z
II(
INSTRUCTION SET
Instruction
S8
Opcode
Address
READ
01
10xx
A3A2A1AO
WRITE
01
01xx
A3A2A1AO
ERASE
01
11xx
A3A2A1AO
EWEN
01
0011
XXXX
EWDS
01
0000
XXXX
Erase/Write Disable
ERAL
01
0010
XXXX
Erase All Registers
WRAL
01
0001
XXXX
Data
Comments
Read Register A3A2A1AO
015-00
Write Register A3A2A1AO
Erase Register A3A2A1AO
Erase/Write Enable
015-00
Write All Registers
NMC9306 has 7 instructions as shown. Note that MSB of any given instruction is a "1" and is viewed as a start bit
in the interface sequence. The next 8 bits carry the op code and the 4·bit address for 1 of 16, 16·bit registers.
X is a don't care state.
The following is a list of various systems that could use a
NMC9306/COP494
A. Airline terminal
Alarm system
Analog switch network
Auto calibration system
Automobile odometer
Auto engine control
Avionics fire control
B. Bathroom scale
Blood analyzer
Bus interface
C. Cable T.V. tuner
CAD graphics
Calibration device
Calculator-user programmable
Camera system
Code identifier
Communications controller
Computer terminal
Control panel
Crystal oscillator
D. Data acquisition system
Data terminal
E. Electronic circuit breaker
Electronic DIP switch
Electronic potentiometer
Emissions analyzer
Encryption system
Energy management system
F. Flow computer
Frequency synthesizer
Fuel computer
G. Gas analyzer
Gasoline pump
H. Home energy management
Hotel lock
I.
Industrial control
Instrumentation
J. Joulemeter
K. Keyboard -softkey
L. Laser machine tool
M. Machine control
Machine process control
Medical imaging
Memory bank selection
Message center control
Mobile telephone
Modem
Motion picture projector
N. Navigation receiver
Network system
Number comparison
O. Oilfield equipment
P. PABX
Patient monitoring
Plasma display driver
Postal scale
Process control
Programmable communications
Protocol converter
Q. Quiescent current meter
R. Radio tuner
Radar dectector
Refinery controller
Repeater
Repertory dialer
S. Secure communications system
Self diagnostic test equipment
Sona-Bouy
Spectral scanner
Spectrum analyzer
T. Telecommunications switching system
Teleconferencing system
Telephone dialing system
T.V. tuner
Terminal
Test equipment
Test system
TouchTone dialers
Traffic signal controller
U. Ultrasound diagnostics
Utility telemetering
V. Video games
Video tape system
Voice/data phone switch
W. Winchester disk controller
X. X-ray machine
Xenon lamp system
Y. Y AG-Iaser controller
Z. Zone/perimeter alarm
system
3-110
.
l>
z
National Semiconductor
Application Note 400
Abdul Aleaf
A Study of the Crystal
Oscillator for
CMOS-COPSTM
INTRODUCTION
~
o
o
TABLE I
The most important characteristic of CMOS-COPS is its low
power consumption. This low power feature does not exist
in TIL and NMOS systems which require the selection of
low power IC's and external components to reduce power
consumption.
A. Crystal oscillator vs. external squarewave COP410C
change in current consumption as a function of frequency and voltage, chip held in reset, CKI is -;- 4.
I = total power supply current drain (at Ved.
Crystal
The optimization of external components helps decrease
the power consumption of CMOS-COPS based systems
even more.
A major contributor to power consumption is the crystal oscillator circuitry.
Table I presents experimentally observed data which compares the current drain of a crystal oscillator vs. an external
squarewave clock source.
The main purpose of this application note is to provide experimentally observed phenomena and discuss the selection of suitable oscillator circuits that cover the frequency
range of the CMOS-COPS.
fckl
Inst_ eye.
time
I,...A
2.4V
32 kHz
125,...s
8.5
5.0V
32 kHz
125,...s
83
2.4V
1 MHz
4,...s
199
5.0V
1 MHz
4,...s
360
External Squarewave
Vee
Table I clearly shows that an unoptimized crystal oscillator
draws more current than an external squarewave clock. An
RC oscillator draws even more current because of the slow
rising signal at the CKI input.
Although there are few components involved in the design
of the oscillator, several effects must be considered. If the
requirement is only for a circuit at a standard frequency
which starts up reliably regardless of precise frequency stability, power dissipation and etc., then the user could directly
consult the data book and select a suitable circuit with proper components. If power consumption is a major requirement, then reading this application note might be helpful.
Vee
2.4V
32 kHz
125,...s
4.4 ,...A
5.0V
32 kHz
125,...s
10,...A
2.4V
1 MHz
4,...s
127,...A
5.0V
1 MHz
4,...s
283,...A
WHAT IS A PIERCE OSCILLATOR?
The Pierce is a series resonant circuit, and its basic configuration is shown below.
r
WHICH IS THE BEST OSCILLATOR CIRCUIT?
The Pierce Oscillator has many desirable characteristics. It
provides a large output signal and drives the crystal at a low
power level. The low power level leads to low power dissipation, especially at higher frequencies. The circuit has
good short-term stability, good waveforms at the crystal, a
frequency which is independent of power supply and temperature changes, low cost and usable at any frequency. As
compared with other oscillator circuits, this circuit is not disturbed very much by connecting a scope probe at any point
in the circuit, because it is a stable circuit and has low impedance. This makes it easier to monitor the circuit without
any major disturbance. The Pierce oscillator has one disadvantage. The amplifier used in the circuit must have high
gain to compensate for high gain losses in the circuitry surrounding the crystal.
Inst. eye.
time
fckl
PHASE SHIFl
0
(180
)
----j
-
I
~~--~....----.g_-
+
-IAI.IY,
V GAINA
OUT
.~ Rl
CRYSTAL
.-----t~UI---.
C2
=r~:______LO~S~S_~_____=r~~Cl
;
TL/DD/8439-1
FIGURE 1
For oscillation to occur, the Barkhausen criteria must be
met: (1) The loop gain must be greater than one. (2) The
phase shift around the loop must be 360·.
3-111
•
o
o
oo::t'
Z
current drain
CRYSTAL OSCILLATORS USING CMOS-IC
The use of CMOS-IC's in crystal oscillators is quite popular.
However, they are not perfect and could cause problems.
The input characteristics of such IC's are good, but they are
limited in their output drive capability.
Oscillator Type
I (current drain)
Crystal Osc.
(data sheet)
950 J-I-A
Crystal Osc.
(two inverter)
810 J-I-A
Ext. Clock
790 J-I-A
PIERCE IC OSCILLATOR
Figure 3 shows a Pierce oscillator using CMOS inverter as
an amplifier.
The other disadvantage is the longer time delay in a CMOSinverter as compared to a discrete transistor. The longer
this time delay the more power will be dissipated. This time
delay is also different among different manufacturers.
R
As a characteristic of most CMOS-IC's the frequency sensitivity to power supply voltage changes is high. As a group,
IC's do not perform very well when compared with discrete
transistor circuits.
But let us not be discouraged. Low component count which
leads to low cost is one good feature of IC oscillators.
As a rule, IC's work best at the low end of their frequency
range and poorest at the high end.
Several types of crystal oscillators using CMOS-IC's have
been found to work satisfactorily in some applications.
Cz
TL/DD/6439-3
FIGURE 3
The gain of CMOS inverter is low, so the resistor R1 should
be made small. This reduces gain losses. The output resistance of the inverter (Ro) can be the integrating resistor for
the RoCI phase lag network.
R bfas
~~~_L ~
C1
~
CMOS-TWO INVERTER OSCILLATOR
The two inverter circuit shown in Figure 2 is a popular one.
The circuit is series resonant and uses two cascaded inverters for an amplifier.
Rbfas
l. . __. . . .__T
..
Omitting R1 or with a small value of R1, the crystal will be
driven at a much higher voltage level. This will increase
power dissipation.
OUT
For lower frequencies (Le., 32 kHz), R1 must be large
enough so that the inverter won't overdrive the crystal. Also,
if R1 is too large we won't get an adequate signal back at
the inverter's input to maintain oscillation. With large values
of R1 the inverter will remain in its linear region longer and
will cause more power disSipation. Typically for 32 kHz, R1
should be constrained by the relation.
__________
TL/DD/6439-2
FIGURE 2
Each inverter has a DC biasing resistor which biases the
inverter halfway between the logic "1" and "0" states. This
will help the inverters to amplify when the power is applied
and the crystal will start oscillation.
1
- - C - ~ 32kHz
27TR1 1
At higher frequencies, selection of R1 is again critical. In
order to drive a heavy load at high frequency, the amplifier
output impedance must be low. In order to isolate the oscillator output from C1 so it can drive the following logic
stages, then R1 should be large. But again, R1 must not be
too large, otherwise it will reduce the loop gain.
The 7 4C family works better as compared with other CMOSIC's. Will oscillate at a higher frequency and is less sensitive
to temperature changes. The CMOS-COPS data sheet
states that a crystal oscillator will typically draw 100 J-I-A
more than an external clock source. However, the crystal
oscillator described above will draw approximately as much
3-112
.
l>
The value of A, is chosen to be roughly equal to the capacitive reactance of C, at the frequency of operation, or the
value of load impedance ZL.
=
~
The circuit of Figure 5 has been tested and has a very good
performance.
typically: C, = C2 = 220 pF at 1 MHz
C2
o
o
Certain biasing conditions might cause collector saturation.
Collector saturation increases oscillator's dependence on
the supply voltage and should be avoided.
The small values of C1 and C2 will help minimize the gain
reduction they introduce.
=
z
The crystal's drive level
Pd = VS2Re
Xs2
This drive level should not exceed the manufacturer's spec.
Xc~
WhereZL = AL
AL = AS = series resistance of crystal
C,
Ae is the crystal's effective series resistance.
330 pF at 2 MHz
+5V
DISCRETE TRANSISTOR OSCILLATOR
As mentioned earlier, a discrete transistor circuit performs
better than an IC circuit. The reason for this is that in a
discrete transistor circuit it is easier to control the crystal's
source and load resistances, the gain and signal amplitude.
OUTPUT
4.7 kll
A discrete transistor circuit has shorter time delay, because
it uses one or two transistors. This time delay should always
be minimized, since it causes more power dissipation and
shifts frequency with temperature changes. Figure 4 shows
a basic Pierce oscillator using a transistor as an amplifier.
Vt
27pF
t.5kll
CRYSTAL
+V
~----~D~-----+
TLIOO/8439-5
FIGURE 5
+
This circuit will oscillate over a wide range of frequencies
2-20 MHz.
(5) (1.5)
Voltage (V1) = 1.5 + 4.7 = 1.21V
Base Current
=
1.21-V SE
39k
=
15.6 p.A
At Saturation (VCE = 0)
TLIOO/8439-4
5
Ic (SAT) = = 4.2 mA
1.2
FIGURE 4
The basic phase shift network consists of CA" CS 2 and the
crystal which looks inductive and is series resonant with
CAl and Cs, . The phase shift through the transistor is 180·
and the total phase shift around the loop is 360·. The condition of a unity loop gain must also be satisfied.
+5V
•
VA = _(Cs)
CA
VB
VA = _(XCA)
Vs
Xcs
For oscillation to occur, the transistor gain must satisfy the
relation
20 -40pF
where G = -gfeZL
gfe is the transconductance of the transistor
ZL is the load seen by the collector
XS2
ZL =
Re'
1
Xs = -WCS
TLIOO/8439-6
FIGURES
3-113
Having 15.6 ,..,Aof base current, for saturation to occur
4.2mA
hFE = --=269
15.6,..,A
The DC beta for 3904 at 1 mA is 70 to 210, so no problem
with saturation, even at lower supply voltages.
The current consumption (power supply Vee current drain)
of COP444C using the above oscillation circuit is around
267/-LA.
The circuit of Figure 6 is another configuration of discrete
transistor oscillator.
The performance of above circuit is also good. The only
drawback is that it does not provide larger output signal.
CONCLUSION
As discussed within this report, a discrete transistor circuit
gives better performance than an IC circuit. However, oscillators using discrete transistors are more expensive than
those using IC's when assembly labor costs are included.
So, the selection of either circuit is a trade-off between better performance and cost.
The data and circuits presented here are intended to be
used only as a guide for the designer. The networks described are generally simple and inexpensive and have all
been observed to be functional. They only provide greater
flexibility in the oscillator selection for CMOS-COPS systems.
3-114
National Semiconductor
Application Note 401
Abdul Aleaf
Selecting Input/Output
Options On COPSTM
Microcontrollers
INTRODUCTION
There are a variety of user selectable input and output options available on COPS when the ROM is masked. These
options are available to help the user tailor the 1/0 characteristics of the Microcontroller to the application. This application note is intended to provide the user a guide to the
options: What are they? When and how to use which ones?
The paper is generally written without reference to a specific
device except when examples are given. It must be remembered that any given generic COPS Microcontroller has a
subset of all the possible options available and that a given
pin might not have all possible options. A reference to the
device data sheet will determine which options are available
for a specific device and a specific pin of that device.
INPUTIOUTPUT OPTIONS
sinking requirement of 1 TIL load (1.6 mA at 0.4V). It
will meet the "low" voltage requirement of CMOS logic. All output options use this device (device # 1) for
current sinking. On the other hand, the relatively high
impedance depletion-mode device (device #2) to Vee
provides low current sourcing capability (100 ,...,A at
2.4V). This pullup is sufficient to provide the source
current for a TIL high level and will go to Vee to meet
the "high" voltage requirements of CMOS logic. An
external resistor to Vee may be required to interface to
other external devices requiring higher sourcing capability.
An interface example to a common emitter NPN transistor is given below:
Table I summarizes the 110 capability of NMOS-COPS, in
general. However, some of the options have different configuration in CMOS-COPS. Data sheets provide information
on the 1/0 options associated with the CMOS-COPS.
I. OUTPUTS
~RCE
The following discussion provides detailed information on
the capabilities of the mask-programmable output options
available on COPS.
18
A. STANDARD OUTPUT
This option is a simple, straightforward, logic compatible output used for simple logic interface. It is available
on SO, SK and all D and G outputs, It is recommended
to be used as a default option for all but SO, SK outputs.
o-f
TlIDD/B440-2
FIGURE 2
Vee
Rs is needed to limit transistor's base current if
Isource > IS(max),
Rp helps generate base drive if the Isource is not sufficient. The disadvantage of Rp is the introduction of
more power dissipation. The temperature effects on
the reverse saturation current leso causes Ie to shift.
leBO approximately doubles for every 1DoC temperature rise. The effect of changes in leso reduces off
state margin and increases power dissipation in the off
state.
TlIDD/B440-1
FIGURE 1. Standard Output
Figure 1 shows the standard output configuration. The
enhancement mode device to ground is good at sinking current (sinks 1-2 mA) and is compatible with the
However, in a typical device, the current supplied by
Rp will swamp out any effects on leso. Another parameter found to be decreasing linearly with temperature is
VSE:
~VSE = VSE2 - VSE1 = -k(T2 - T1)
where k ::::: 2 mV
T in °C.
rc,
Now let's consider a practical example:
LOW SOURCE CURRENT OUTPUT:
Standard output, COP420, device # 2.
The selected transistor is 2N3904.
DESIGN CONSIDERATIONS:
a. Q is in saturation during ON-state.
b. Q's collector current Ie = 100 mA
3-115
•
AN-401
TABLE I
Default
Standard
Push-Pull
High Sink
Very
High Sink
LED
Hi-Current .
LED
TRI-STATE®
Push-Pull
Hi Current
TRI-STATE
Push-Pull
Open
Drain
SO Push-Pull Logic
MICROWIRE
Higher Drive,
Compatible;
Non
Faster X'sition
MICROWIRETM
External
Pull Up
SK Push-Pull Logic
Compatible;
Non
MICROWIRE
External
Pull Up
MICROWIRE
Higher Drive
Faster
Transition
D
Standard Logic
Compatible
L Parts Only LPartsOnly
15mA
30mA
External
Pull Up,
Standard, Hi
Sink or V.H.S.
Pull Down
G
Standard Logic
Compatible;
Inputs
L Parts Only L Parts Only
15mA
30mA
External
Pull-Up,
Standard, Hi
Sink or V.H.S.
Pull Down
L
Standard Logic
Compatible;
Inputs,
TRI-LEVEL
H
Standard Logic
Compatible
Inputs
R
Standard Logic
Compatible;
Inputs,
TRI-LEVEL
Hi Source
1.5mA
L Parts Only
Higher Source
3mA
TRI-LEVEL TRI-LEVEL
MICROBUSTM
Meets TRI-STATE
Spec.
TRI-LEVEL
L Parts Only
External
Meets TRI-STATE Pull Up
Spec.
TRI-LEVEL
TRI-LEVEL
External
Pull Up
Higher Drive
Faster
Transition
TRI-LEVEL
Meets
TRI-STATE
Spec
TRI-LEVEL
External
Pull Up
TRI-LEVEL
c. Assuming a "forced" of 10 for Q. This is a standard
value for f3 to insure saturation.
This will tell us, at You! = VBE, how much current
can be sin ked to keep Q "OFF". The intersection
of Vee = 6.3 (MIN) and VBE = 0.61V gives us
Isink = 4 mAo
For an Ie = 100 mA, f3 = 10, we have IB ~ 10 mAo
The low current standard output certainly cannot provide IB ~1 0 mAo Therefore, a pullup resistor (Rp) is
required.
Rp ~
0
= 1.6k
>
z
0
a:
~
I
z0
~
>
TA
0.6
-
0.4
'
-r
we use VBE(max) which is the worst case, and low
temperature.
i-'"
~'I00°C
Let T (ambient) = 10°C.
From VBE vS. Ie curve, Figure 3:
J
r-
VBE ~ 0.83V at 25°C
~ -.=~-!
f-
0
VBE
I
100
10
~
0.83
+
x
2 mvrC
15 = 0.86V at 10°C.
Using this value of VSE, we go to COP420 Standard
Output source current curve (Figure 5), and draw a
vertical line at VBE = 0.86V. The intersection of this
line and Vee = 4.5(MIN) gives an Isource = 325/-LA.
I
1.0
0.1
4.5 - 0.61
1.42
mA = 2.74 mA
i. Now calculate the available source current. Here
~r"'"
2SoC
c--
0.2 f -
± 10%
Which is less than sink ability of device (3 mA from
Figure 4) at Vee = 4.5V, You! = 0.61V.
lilli'
~
!..:.
IRp =
VCE'SV
1111I
0.'
1.42
Q.9
h. Using the value of Rp, let's calculate the current
through Rp at Vee = 4.5V(MIN).
e. Assuming the worst case is at Vee (max) and Hightemperature (let ~T=20°C ~ ~VBE= -40 mY).
From VBE(ON) Vs. Ie curve, Figure 3:
'"<~
6.3 - 0.61
4
k ~ 1.42k
the actual standard Rp (± 10%) =
~VBE
~= -2mVrC.
1.0
J;..
...
o
g. Now calculate Rp.
d. Now we need to select the minimum allowed value
for Rp. The sinking ability of COPS output will determine Rp. We must sink the pullup current to a
VOUT < VBE in order to hold Q off. Also, note that
E
...
»
z
Ic - COLLECTOR CURRENT (mA)
TLlDD/8440-3
Standard Output
Source Current
FIGURE 3. 2N3904 I/V
at 100 mA, 25°C, VBE ~ 0.85V.
- 2.0
r--r----.-......----.-.....-----.--.
So, our VBE(45°C) = 0.85 - 0.04 ~ 0.81V.
l J
1. =6.3V
(MAX)
-1.75
There is not margin here for process VBE variations so we can allow 200 mV of slope,
/ Vee
-1.5~
_-1.25
VBE = 0.61V (worst case)
I
1.... -1.0
f. Having VBE = 0.61V, we go to COPS sink graph
and draw a vertical line at VOUT = VBE = 0.61V.
Figure 4 below:
~
~
I
i\.. ./ Vee =4.5v (MAX)
X
'~
r......" "K
I
"'....--
-0.75 I ' ......"'\..
/
Vee
'"
=4.5V (MIN)
VCC=6.3V(MIN)
Output Sink Current
-30
-25
i
-20
!
!5
_0
!
-15
ivcc= 4.5V (IoIAX)
:
'-Vee= 6.3V
L /vcc=6.3V (1oIIN)
I /
_
-J... '-
!i!4mA ______ /H=;I~""'F~-VCIC=4·15V
4
5
6
7
OEVICE 2
TLIDD/8440-5
FIGURE 5
This is low but typical of N-channel low current
standard output.
(I.)
lollIN -
Contribution of Rp
1234567
VOUT (VOLTS)
3
VOUT (VOLTS)
=3mA~L-t-'----.l._-'---'---L_-'---'
o
2
(101~~
Ii
-10
-5
1
J
I
IRp =
DEVICE 1
TL/DD/8440-4
FIGURE 4
IB(min)
3-117
4.5 - 0.86
~
= 2.07 mA
Rp(max)
2.07 + 0.325 = 2.3 mA
~
•
This is our worst case base drive, but we needed
10 mA.
Vee
What can we do to get the base drive we need?
1. We can use above design and allow Q to come
out of saturation. The disadvantage is that Q's power dissipation increases.
S.1 kJl
2. Or use a Darlington configuration (Process 05). In
such a configuration only first stage of Darlington
can be saturated (not output stage). This will introduce a slightly higher power dissipation. Note that
for a process 05 transistor, the forced f3 is 1000.
3. Use a high source type output such as TRISTATE output. If we draw a vertical line at
VSE = 0.86, we get a source current of ~ 6 mA at
Vee = 4.5(MIN) Figure 6, which gives us a worst
case
COP402
TlIDD/8440-7
FIGURE 7. PNP Drive
From the output sink current curve on the COP402
data sheet, we find that, at 1.0V the D-line can sink
3.2 mA. To calculate the value of the current limiting resistor,
IS(min) = 8.07 mA.
TRI-STATE Output
Source Current
<
..s
R = (Vee - VSE - Voo)/I
When Vee = 6.3V, the DO output can sink more
than enough current at 0.3V, and if the VSE = 0.7V,
we can calculate the maximum Do output current:
I = (Vee - VSE - Vo)/R
= (6.3 - 0.7 - 0.3)/780
-10
~
=
6.3 mA.
Using the Standard Output Option for
Bidirectional I/O (G-port)
-5
VOUT (VOLTS)
The standard output is good at sinking current, but rather
weak at sourcing it. Therefore, by using the Standard Drive
configuration and outputting 1's to the port, an external
source may easily overdrive the port drivers with the added
bonus of a built-in pullup. While the depletion-mode device
provides sufficient current for a TTL high level, yet can be
pulled low by an external source, thus allowing the same pin
to be used as an input and output. Data written to the ports
is statically latched and remains unchanged until rewritten.
As inputs the lines are non-latching (Figure 8).
DEVICE 5
TlIDD/8440-6
FIGURE 6
CAUTION On TRI-STATE graph the intersection of
Vout = BSE = 0.86V and Vee = 6.3V(MAX) curve
(Figure 6) would result in an IS(Max) = 50-60 mA,
which is way too much to handle. In this case there
is a need for a series current limiting Rs to kill some
of the worst case IS(max).
4. There is a high current Standard-L option on
some COPS (Le., COP4XL, L-port) which provides
sufficient source current.
lOW"
OR "Y"
5. N-channel output can generally sink better than
source. PNP transistor can be used instead of NPN.
The same analysis applies and in general will show
better overdirve capabilities.
G
LATCH
t
OWG
OR
OGI
As shown in Figure 7, the Do output which has a
standard output option, is driving the base of the
PNP transistor. Assuming Vee = 4.5V (for
COP402), VSE = 1.0V, and a worst case base drive
requirement of 3.0 mA. We see that we must supply
200 p.A to the base-emitter resistor to turn the transistor on:
T
ING SKGZ
OR SKGBZ
TlIDD/8440-8
FIGURE 8. G Port Characteristics
1.0V/5.1 k = 200 p.A
3-118
;x:.
ZI
~
o
.....
DATA
COP4XXC STANDARD
PUSH-PULL OUTPUT
EXTERNAL CIRCUIT
TL/OO/8440-9
FIGURE 9
When writing a "0" to the port, the enhancement-mode device to ground overcomes the high pullup and provides TIL
current sinking capability. While writing a "1" the depletionmode device behaves as internal pullup maintaining the "1"
level indefinitely. In this situation, an input device capable of
overriding the small amount of current supplied by the pullup device can be read. This feature provides maximum user
flexibility in selecting input/output lines with minimum external components.
TL/OO/8440-10
FIGURE 10. Open-Drain Output
The open-drain option makes the ports G and L very
easy to drive when they are used as inputs. This option
is commonly used for high noise margin inputs, unusual
logic level inputs as from a diode isolated keyboard,
analog channel expansion, and direct capacitive touchpanel interface. Available with standard, high or very
high sink capability ("L" parts only).
In CMOS-COPS the low current push-pull output has even
much weaker source current capability and this make it easier to be overriden.
Referring to Figure 9.
Note that IOL
be used.
> IOH, otherwise transistors or buffers must
For COP424C/444C, standard push-pull
@
Vee = 4.5V, Vout = OV, IOH(min) = 30/LA
@
IOH(max) = 330 /LA
Vee = 2.4V, Vout = OV, IOH(min) = 6/LA
C. PUSH-PULL OUTPUT
The push-pull output differs from the standard output
configuration in having an enhancement-mode device
in parallel with the depletion-load device to Vee, providing greater current sourcing capability (better drive)
and faster rise and fall times when driving capacitive
loads.
IOH(max) = 80 /LA
While in NMOS (COP420L), Standard output:
= 4.5V, VOH = 2.0V, IOH(min) = 30/LA
@
Vee
@
IOH(max) = 250 /LA
Vee = 6.3V, VOH = 2.0V, IOH(min) = 75/LA
•
IOH(max) = 480 /LA
As we see, both in CMOS and NMOS it is easier to override
IOH. Note that the standard output option is available with
standard, high, or very high sink current capability ("L" parts
only). The pulldown device is bigger for the high/very high
current standard output. The sourcing current is the same.
These three choices provide some control over current capability.
B. OPEN-DRAIN OUTPUT
TLIOO/8440-11
FIGURE 11. Push-Pull Output
This option uses the same enhancement-mode device
to ground as the standard output with the same current
sinking capability. It does not contain a load device to
Vee, allowing external pullup as required by the user's
application. The sinking ability of device # 1 determines
the minimum allowed external pullup. The analysis discussed earlier for Standard Output options equally applies here. Available on SO, SK, and all D, G, and L
outputs.
If a push-pull output is interfaced to an external transistor, a current-limiting resistor must be placed in series
with the base of the transistor to avoid excessive
source current flow out of the push-pull output. This
option is generally for MICROWIRE Serial Data exchange.
3·119
I
It is available on SO, SK only and is recommended to
be used as a default option for these outputs. A few
points must be kept in mind when using SO, SK for
MICROWIRE interface.
E. LED DIRECT DRIVE OUTPUT
In this configuration, the depletion-load device to Vee
is paralleled by an enhancement-mode device to Vee
to allow for the greater current sourcing capacity required by the segments of an LED display. Source current is clamped to prevent excessive source current
flow.
The data sheet specifies the propagation delay for a
certain test condition (i.e., Vee = 5V, VOH =O.4V,
Loading = 50 pF, etc.).
In practice, actual delay varies according to actual input capacitive loading (typical 7 -10 pF per IC input),
total wire capacitance and PCB stray capacitance connected to the SI input. Thus, if actual total capacitive
loading is too large to satisfy the delay time relationships (td = tSK - tr; td = actual delay time, tSk = the
instruction cycle time, tr = the finite SK rise time), either slow down SK cycle time or add a pullup resistor
to speed up SK "0" to "1" transition or use an external
buffer to drive the large load. Besides the timing requirement, system supply and fan-outlfan-in requirements have to be considered, too.
(.IS DEPLETION DEVICE)
If devices of different types are connected to the same
serial interface, the output driver of the controller must
satisfy all the input requirements of each device. Briefly, for devices that have incompatible input levels or
source/sink requirements to exchange data, external
pullups or buffers are necessary to provide level shifting or driving. Unreliable operation might occur during
data transfer, otherwise. For a 100 pF load, a standard
COPS Microcontroller may use a 4.7k external resistor,
with the output "low" level increased by less than 0.2V.
For the same load the low power COPS may use a 22k
resistor; with the SO, SK output "low" level increased
by less than 0.1V.
TL/DD/B440-13
FIGURE 13. LED (L output) NMOS-COPS
This configuration can be disabled under program control by resetting bit 2 (EN2) of the enable register to
provide simplified display segment blanking.
However, while both enhancement-mode devices
turned off in the disabled mode, the depletion-load
vice to Vee will still source up to 0.125 mAo As in
case of Standard L output, again this current is
sufficient to pull an input to a logic" 1".
are
dethe
not
The drivers must be disabled and the lines must be
pulled high and low externally, whenever they are used
as inputs.
D. STANDARD L OUTPUT
Example #1:
Same as Standard Output, but may be disabled. Available on L-outputs only.
When COPS outputs are used to drive loads directly,
the power consumed in the outputs must be considered in the maximum power dissipation of the package.
Figure 14 shows an LED segment obtaining its source
current from Lo output and Do sinking the current. In
this configuration all the power required to drive the
LED with the exception of the portion consumed by the
LED itself, is consumed within the chip. Assuming
COP404L is the driving device:
TL/DD/B440-12
FIGURE 12. Standard L Output
DISABLE
When this option is implemented on the L-port and the
L-drivers are disabled to use the L lines as inputs, the
disabled depletion-mode device cannot be relied on to
source sufficient current to pull an input to a logic high.
There are two ways to use L lines as inputs (having
standard L option):
'--..._____+-L_O....., VSOURCE
The first method requires that the drivers be disabled.
In this case the lines are floating in an undefined state.
The external circuitry must provide good logic levels
both high and low to the input pins. The inputs are then
read by the INL instruction. The second method is similar to the technique used for the G-port. The drivers are
enabled and a"1" must be written to the Q register.
VCC
~.~
~~VSINK
The external circuitry will then be required only to pull
the lines low to a logic "0". The line will pull up to a "1"
itself. The INL instruction is used as before to read the
lines.
TlIDD/B440-14
FIGURE 14. LED Drive
3-120
If we assume the Vsource is not inserted, the device has
a Vee of 9.5V, and that the voltage drop across the
LED is 2.0V.
Now we calculate the series current limiting resistor R.
The circuit has two non-linear devices to be considered; the output device and the LED.
We can calculate the power dissipation in these outputs. The minimum current that Do can sink at 1.0V is
35 mA (COP404L data sheet). La can source up to
35 mA at 3.0V. Therefore, the power dissipation for the
La output could be: (9.5 -3.0) (0.035) = 227 mW. The
power in the Do output is (1)(0.035) = 35 mW.
The LED in this example is NSC5050. Looking at IIV
curve, the device has a threshold 1.SV. Also, note that
for VLEO > 1.6V the IIV curve is very linear (Figure 17).
Now let us calculate the current limiting resistor. Referring to COP404L Lo-L7 output source current curves,
at Vee = 9.5V the minimum current curve peaks at
I = 6.0 mA and Vsource = 4.8V. The current curve is
actually very flat between 4.0 and 5.0 volts. For maximum current, we need to set the voltage on the L pin
equal to 4.8V at 6.0 mA. The D line will sink this current
at O.4V. Therefore, the resistor and LED must make up
the difference:
From ON part of curve,
VI = Vo
4.8 = 0.4
1.9 -1.7
Rs=~=40
We can neglect Rs as well (only RS « R). Our model
is simply a voltage source for the LED when
1= OforVLEO
I=
+ IR + VLEO
+ O.OOSR + 2.0
+
+
IR
+
00
< VTH
for VLEO
> VTH
Design Procedure:
I
. - VS(min) - (VLEO(max) + VOUT(max)
1. LEO(mm) R(max)
R = 4000
VI = 2.4
We need endpoints of the load line.
a.
@V
- 0 ~ I
. - VS(min) - VLEO(max)
out LEO(mm) R(max)
b. @Vout
2.0
+
VLED(max) = Vs ~ I = 0
(VLED(max) = 2V)
2. Plot a and b
IR
From the current curve, we see that at 6.4V the L line
will source 10 mA. Therefore: VI = 2.4 + (0.01) (400)
= 6.4V.
Assuming an Imin = 7 mA, VS(min) = 4.5V
from 1 R(max) = 3570
Example #2:
Draw the load line with slope -1/357 crossing
Let's consider a different configuration.
Vout = Vs - VLEO(max) = 4.5 - 2 = 2.5V.
(Figure 16).
VLED
-~.
•
I
I COPSLEO
-.--1
I
OUTPUT
I
I
(SINK PORTION)
A.
o
......
Because of this, the LED characteristic can be modeled as a sharp threshold device with a non-zero
source resistance (normally IIV curve is LOG looking).
At the other end of the curve, when the L line sources
the maximum current, assume the LED and the D line
will have the same voltage drop.
VI = 0.4
>
z
IT
#1 I Vour
I •
1-
Output Sink Current
I-
v-
s===
TL/DD/8440-15
2
FIGURE 15. LED DRIVE
3
4
5
Vour (VOLTS)
DEVICE 1
TL/DD/8440-16
FIGURE 16. COP420
3-121
•
'I"'"
o
Forward Current (IF) vs
Forward Voltage (VF)
~
Z•
Z
~
+5V
+5V
....
0
+5V
Vcc
ct.IOS
COPS
ANALOG INPUT
INPUT
REF
O~
GND
-5V
VOLTAGE COWPARATOR
TLlDD/6440-20
FIGURE 20
1--_. RESET
RCHxVCC
RISE nME
I
(INTERNAL)
c
INSTRUCTION CYCLES
TL/DD/6440-21
FIGURE 21
from such situations. As an example, consider the interface of a CMOS-COPS with the LF111 voltage comparator:
When the low level "-5V" appears on the comparator's
output, the COPS input is pulled low below "logic low" of
"OV". This will cause damage if the comparator sinks
enough current. The use of a current-limiting resistor in
series with the input is helpful. A better solution is to use a
voltage divider as shown in Figure 20. Any time a low
level appears on the comparator's output, a total voltage
drop of 1OV will appear across both resistors each dropping 5V, causing the input to sit at OV. Whenever the
output goes high, the resistors will not drop any voltage
(no current through the resistors) and a logic high of 5V
will appear on the input. To reduce power dissipation introduced by resistors, the resistor value must be high
(> 100k), because the CMOS inputs have very high input
impedance.
nal capacitor reaches a high logic level, the second input
of the AND gate is released.
The Reset logic will initialize (clear) the device upon power-up if the power supply rise time is less than 1 ms and
greater than 1 J.ls. With a slowly rising power supply, the
part may start running before Vee is within the guaranteed range. In this case, the user must provide an external RC network and diode shown in Figure 21 above. The
external RC network is there to hold the RESET pin below VIL until Vee reaches at least VeC(min). The desired
response is shown in Figure 22.
VOLTS
VCC(MIN)
RESET INPUT
All COPS Microcontroller have internal reset circuitry. Internally there is an AND gate with one input coming from
the RESET input, and the second input connected to a
charge pump circuitry. In the Charge pump circuit, a tiny
capacitor is being charged upon execution of each internal instruction cycle. When the voltage across this inter3-123
" " " " ' - - - - - - - - - - - ' - - nME
TL/DD/6440-22
FIGURE 22
•
......
o
~
:Z
_,,-_~31> 74C74
TO
~t---+--. FILAMENT
5
0.1 J.'F
560.0.
7
(Vdls)
(Vdls)
(Vdls)
TLIF/8683-3
FIGURE 3. Filament Oscillator Circuit
3-126
l>
z
VF Display Drivers
I
Two high voltage display drivers were needed to control the
VF display. A MM58341, was used to control the grids and a
MM58348 was used to control the individual pixels or anodes. Both of these drivers receive serial information and
output 32 and 35 segments of data respectively.
The MM58341 has three control pins which make it ideal for
controlling the grids of a VF display. The blanking control
pin will turn off all segments of the display when a logic '1' is
applied to this pin. This is particularly important for reducing
ghosting, and controlling brightness. Ghosting is a condition
where the last characters shadow appears behind the character b~ing di.splayed. The enable pin acts as an envelope
for the Input signal. Only while it is at a logic '1' level will the
circuit accept clock inputs. When the pin goes low, all the
data is latched and displayed. A data out pin is also provided for cascading. If the display has more than 32 grids, a
second grid driver can be cascaded by connecting the data
out pin to the input data for the second grid driver.
The MM58348 is a 35 bit shift register and latch which is
used to control each pixel or dot. When a leading 1, folMM58341
INPUTS
lowed by 35 bits of data, is received, the data is latched and
displayed. The chip is automatically reset upon power up.
Considering first the digit driver (MM58341), it becomes
clear that the digits must be enabled or refreshed sequentially and that this process must be continuous regardless if
the display data has changed. The data for the MM58341 is
simply a 1 followed by 19 zeroes where the 1 is shifted
~hrough the internal registers of the MM58341. As each digit
IS enabled, the corresponding segment data is displayed. To
insure that no ghosting effects are seen during the transition
between digits, the blanking control is activiated just before
the data is latched into the dot or anode driver and deactivated just after the data has been latched. During this time
when the blanking control is activated, the grid driver is
clocked shifting the 1 to the next location. Figure 4 shows
the micro-controller waveforms and the resultant display
waveforms for the 20 character display.
n. ______. .n
.
n
n
----------~
n
MM58348
INPUTS
n
n
~--------~
n
DATA
BLANK
o
MULTIPLEXED DISPLAY REFRESH TIMING
CLOCK _ _ _ _ _ _......
ENABLE
0l:Io
0l:Io
----------'
34 CLOCKS
34 CLOCKS
r----.
34 CLOCKS
34 CLOCKS
CLOCK
.
DIGIT DATA
J1ma_IIoIoIoIlTIi11....·_~I111111111111111
I
DATA
lSTART BIT
MM58348
SEGMENT
OUTPUT
DIGIT 19 DATA
DIGIT DATA
m
I
1111111111111111
lSTART BIT
.
DIGIT DATA
m nmm m
I
lSTART BIT
lSTART BIT
X",,__DI_GI_T_2_0_DA_T..;,A_..JX,-__D_IG_IT_I_D_AT_A__ X
DIGIT 2 DATA
...J
>e:
MM58341
OUTPUTS
(19)
DIGIT 19 "ON" ,
(20)
~----------------------------
1
_ _ _ _ _ _...J
DIGIT 20 "ON" ,
-----------------------1 DIGIT 1 "ON" ,'-_ _ _ _ _ __
(1) _ _ _ _ _ _ _ _ _ _ _ _..J
1 DIGIT 2 "ON" ' - -
(2) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---J
TL/F /8683-4
FIGURE 4. Timing Diagram
3-127
•
o
:i
:2:
c(
In between digit strobes, the segment data is updated. The
first 34 bits of segment data are set up in the dot driver and
the blanking signal is activated to disable all 20 digits. The
35th bit of data is clocked in, updating the segments. Since
the MM58348 resets its internal shift register each time the
data is latched, it can accept all but the final data bit while
still displaying the previous digit. The digit driver is then
clocked, .shifting the digit strobe to the next position. The
enable is then brought low, enabling the next digit. Finally
blanking control is deactivated and the data displayed.
During the time which the blanking control is high, the order
in which the segments or the digits are updated is not critical. Since this occurs while the display is blank. The digit
driver may be clocked first, or the segments could be
changed first. In general, the philosophy for the driving this
VF multiplexed display is outlined in Figure 5.
LOAD GRID DRIVER
WITH A "1"
HOST INTERFACE AND PROGRAMMING
With a minimal amount of address decoding and an eight bit
latch, COPS can be interfaced with a common microprocessor bus. When a character has been input into the host to
be displayed, the ASCII value of that character is latched
into the eight bit latch (MM74HC373) and is read on the L
port (LO-6) of the COPS. The MSB of the ASCII value must
be a logic 1. This MSB is the signal to the COPS that a new
character is being presented. Once the character has been
stored, an interrupt is sent from the COPS to the host
through the 0-0 port. The COPS checks for a new character
being input every 200 J-Ls. If a character is being sent, 1 ms
is required to store that character in the RAM of the COPS.
With the COPS controlling the display, the host micro-processor is not being tied down with character look-up and display refresh. A simple flowchart of the host requirements is
shown in Figure 6.
COPS SOFTWARE
There are four main sections of the COPS software. The
first section, the initialization of the RAM, sets up the RAM
as shown in Figure 7. A '0' is stored in all of the LSB positions and a '2' is stored in all of the MSB positions. Since
the COPS is in a constant display loop, this is necessary to
insure a blank display. 20H is the ASCII value of a space.
With the RAM set up in this way, a maximum of 28 characters can be stored in RAM. Since the display in this application is only 20 characters long, RAM locations M1,4 to
M 1,11 and M3,4 to M3,11 are not used. RAM locations 1,12
to 1,15 and 3,12 to 3,15 are used as temporary storage
throughout the program and cannot be used for character
storage.
TL/F/8683-5
FIGURE 5. Flowchart for Display Drivers
YES
The second part of the program, stores the new characters
sent by the host CPU in RAM. Once a character has been
sent, this section of the program checks the ASCII value of
that character to see if it is a control character or a display
character. If it is a display character, the character is stored
in RAM and an interrupt is sent to the host. There are three
control characters which the COPS program will recognize.
Cursor forward (ASCII value 08H) moves the cursor forward
without destroying the data, cursor backwards (ASCII value
OCH) moves the cursor backwards without destroying the
data, and return (ASCII value ODH) will clear the display and
put the cursor at the beginning of the display. To recognize
and store a character, 1 ms is required.
EXCLUSIVE OR
alASCIl VALUE
WITH BOH
OUTPUT ASCII
VALUE TO
DATA BUS
The third part of the program, the display loop, is the heart
of the program. Unless a new character has been detected,
the program is always in this loop. This section does the
TL/F/8683-6
FIGURE 6. Host System Flowchart
3-128
15
14
LSB
Chr1
LSB
Chr2
13
12
11
10
7
8
9
5
6
4
3
MSB
LSB Temp. ASCII
Pointer Pointer STORAGE
MSB
Chr 1
MSB
Chr2
2
1
0
LSB
LSB
LSB
LSB
LSB
LSB LSB LSB LSB LSB LSB LSB
LSB
LSB
MO
Chr3 Chr4 Chr5 Chr6 Chr7 Chr8 Chr9 Chr10 Chr 11 Chr 12 Chr 13 Chr14 Chr15 Chr 16
LSB
LSB
LSB
LSB
M1
Chr 17 Chr18 Chr19 Chr20
MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB
M2
Chr3 Chr4 Chr5 Chr6 Chr7 Chr8 Chr9 Chr 10 Chr 11 Chr12 Chr13 Chr14 Chr15 Chr 16
MSB MSB MSB MSB
M3
Chr17 Chr18 Chr19 Chr20
Temp. Storage of Pointer
FIGURE 7. COPS RAM Map
I
I
1 Column 3 I
I
IPAD
Matrix
PAD
Binary
0001001111101010001001000010100000111110
Hex.
13
Column 1
I
Column 2
EA
I
24
I
Column 4
28
I
Column 5
3E
FIGURE 8
second byte. In this case, the third byte of data would be
stored at 2E1 H. The fourth byte of data is stored at 300H
plus the ASCII value of the character or at 341 H for the
letter 'A'. The final byte of data is stored 40H from the fourth
byte or at 381 H. Remember the LSB of each byte is stored
first. Table I shows the locations in ROM and the values
stored in them for the letter 'A'.
This application shows a VF display controller designed
with a minimum number of IC's. If additional information
about VF displays or VF display drivers is required,
refer to Application Note AN-371 (The MM583481
342/341/248/242/241 direct drive Vacuum Fluorescent
(VF) Displays.
character font look-up, shifts the character data out the
COPS serial port to the MM58348, and controls the
MM58341 through the four bit parallel port (GO-4). Because
the most significant nibble of the program counter is used
as part of some COPS instructions, it is important that parts
of the program are located at specific locations in ROM.
The final part of the program is the data. Each character is
represented by a 5 byte data word. Each byte of the data
word is stored at a different location in ROM. Fonts for characters with the ASCII values from 20H-5AH have already
been stored in ROM. These characters can be changed or
more characters can be added. The only limitation to the
number of characters is the amount of available ROM.
CREATING THE 5 BYTE DATA WORD
Any number or combination of pixels or dots can be turned
on at a time. To create a new character, it is easiest to first
create a binary string which represents the character. A '1'
in the binary string will turn on the pixel, a '0' will turn it off.
To create this string, start in the upper left corner of the
matrix and go down the columns.
The letter 'A' (Figure 9) would have a binary string shown in
Figure 8. The data must be padded to make it an even 5
bytes in length. The pad at the beginning of the data (0001)
is used as the leading 1 for the MM58348. The one bit pad
at the end of the binary string must be a O. If a 1 were sent
as the pad, it would be used as the start bit for the next
character.
The 5 byte data word that would be stored in ROM and
represent the letter 'A' would then be 13EA24283E.
TABLE I. Character Data of 'A'
and Its Locations In ROM
Address
In ROM
Data
Stored
0241H
02A1H
02E1H
0341H
0381H
31
AE
42
82
E3
••
•
••••••••
•• ••
•
'.
STORING THE DATA IN ROM
The 5 bytes of data are stored in 5 different locations in
ROM. The first byte of data will be stored, LSB first, at location 200H plus the ASCII value of the character. For example, the ASCII value of the letter 'A' is 41 H. The first byte of
data for the letter 'A' would be stored, least significant bit
first, at 241 H. The second byte of data is stored at the location of the first data byte plus 60H or in this case at 2A 1H.
The location of the third byte is 40H plus the location of the
TL/F/8683-7
FIGURE 9. 5 x 7 Character as Stored In ROM
3-129
C) ~----------------------------------------------------------------------------------~
~
~
z•
O THEN NO
;STORE ASCII IN RAM
;MSB IN l,OC
;LSB IN 1, OD
X 0
3-130
.
l>
Section 2 of COPS Software (Continued)
JSR
LBI
OBD
LBI
OBD
JMP
CURFOR
0,01
0,0
z
0l:Io
0l:Io
o
;SENDS INTERRUPT TO
HOST. CHAR. IS
STORED IN RAM
START
;SPECIAL CHARS. (CR, LF, CLEAR DISPLAY)
CURFOR:
OK:
SKIP:
CURBAC:
GOOD:
SPECIAL:
LDD l,OE
COMP
AISC 01
JMP OK
AISC OF
XAD l,OE
CLRA
AISC 01
LBI l,OF
XOR
JMP SKIP
COMP
LBI l,OE
X0
RET
LDD l,OF
AISC 01
JMP GOOD
LBI l,OE
CLRA
AISC 01
XOR
X0
JMP START
XAD l,OF
JMP START
LDD l,OC
AISC 03
JMP NOTRET
JMP RESET
NOTRET:
AISC 01
JMP CFOR
JMP CURBAC
CFOR:
JSR CURFOR
JMP START
;MOVES CURSOR FORWARD ONE
;SPACE. IF CURSOR IS
;MOVED BEYOND THE END OF
;DISPLAY, IT WRAPS AROUND
;TO THE OTHER END. DATA IS
;NOT DESTROYED BY MOVING
;CURSOR
;MOVES CURSOR BACK ONE
;CHARACTER. DOES NOT
;DESTROY DATA AS IT IS MOVED
;IF MOVED BEYOND THE
;END OF THE DISPLAY IT
;WRAPS AROUND TO THE OTHER
;END
;CONTROL CHAR. HAS BEEN
;DETECTED
;RETURN CLEARS DISPLAY,STARTS
;PROGRAM OVER
;NOT RETURN, CHECK FOR CURSOR
;FORWARD
;BY DEFAULT, CURSOR BACKWARDS
;DISPLAY LOOP
3-131
•
o
;
Z
t setup
To read from device:
lcl
« tSK
-
t,.; tRS > tSK/4
Where: tws is MICROWIRE write data-in (01) setup time.
tsetup is device data sheet min data setup time to latch in valid data.
tSK is system clock (SK) cycle time (Recommended 50% duty cycle),
t,. is rise time (10% to 70% bout) of system clock (SK).
lcl is device actual delay time before data-out (DO) valid and
tRS is minimum data setup time for controller to shift-in valid data
iii
~
IJ)
"'1:1"
:2:
~
r----------------------------------------------------------------------------------------,
The first clock rising edge of the instruction cycle triggers
the low-to-high transition of SYNC output via SK. At this
time, the processor reads the state of SI into SIO bit 0,
shifting the current bits 0-2 left. Halfway through the cycle
(shown in Figure 6 as the eight clock rising edge), SK is
reset low and the new SIO bit 3 is outputted via SO.
0.2V. For the same load, the low power COPS controller
may use a 22k resistor, with the SO and SK LOW levels
increased by less than 0.1V.
Besides the timing requirements, system supply and fanout/fan-in requirements also have to be considered when
interfacing with MICROWIRE. For the following discussion,
we assume single supply push-pull outputs for system clock
(SK) and serial output (SO), high-impedance input for serial
input (SI).
INTERFACING CONSIDERATIONS
To ensure data exchange, two aspects of interfacing have
to be considered: 1) serial data exchange timing; 2) fan-out/
fan-in requirements. Theoretically, infinite devices can access the same interface and be uniquely enabled sequentially in time. In practice, however, the actual number of devices that can access the same serial interface depends on
the following: system data transfer rate, system supply requirement capacitive loading on SK and SO outputs, the
fan-in requirements of the logic families or discrete devices
to be interfaced.
To drive mUlti-devices on the same MICROWIRE, the output
drivers of the controller need to source and sink the total
maximum leakage current of all the inputs connected to it
and keep the signal level within the valid logic "1" or logiC
"0". However, in general, different logic families have different valid "1" and "0" input voltage levels. Thus, if devices
of different types are connected to the same serial interface, the output driver of the controller must satisfy all the
input requirements of each device. Similarly, devices with
TRI-STATE® outputs, when connected to the SI input, must
satisfy the minimum valid input level of the controller and
the maximum TRI-STATE leakage current of all outputs.
HARDWARE INTERFACE
Provided an output can switch between a HIGH level and a
LOW level, it must do so in a predetermined amount of time
for the data transfer to occur. Since the transfer is strictly
synchronous, the timing is related to the system clock (SK)
(Figure 7). For example, if a COPS controller outputs a value
at the falling edge of the clock and is latched in by the
peripheral device at the rising edge, then the following relationship has to be satisfied:
So, for devices that have incompatible input levels or
source/sink requirements, external pull-up resistors or buffers are necessary to provide level-shifting or driving.
SOFTWARE INTERFACE
The existing MICROWIRE protocol is very flexible, basically
divided into two groups:
tOELAY + tSETUP ~ tCK
where tCK is the time from data output starts to switch to
data being latched into the peripheral chip, tSETUP is the
setup time for the peripheral device where the data has to
be at a valid level, and tOELAY is the time for the output to
read the valid level. tCK is related to the system clock provided by the SK pin of the COPS controller and can be
increased by increasing the COPS instruction cycle time.
1) 1AAA. .... AOOO ..... O
where leading 1 is the start bit and leading zeroes are
ignored.
AAA ..... A is device variable instruction/address word.
000..... 0 is variable data stream between controller and
device.
2) No start bit, just bit stream, i.e., bbb ..... b
The maximum tSETUP is specified in the peripheral chip data
sheets. The maximum tOELAY allowed may then be derived
from the above relationship.
where b is a variable bit stream. Thus, device has to decode
various fields within the bit stream by counting exact bit position.
Most of the delay time before the output becomes valid
comes from charging the capacitive load connected to the
output. Each integrated circuit pin has a maximum load of
7 pF. Other sources come from connecting wires and connection from PC boards. The total capacitive load may then
be estimated. The propagation delay values given in data
sheets assume particular capacitive loads (e.g. VCC = 5V,
VOH = O.4V , loading = 50 pF, etc.).
If the calculated load is less than the given load, those values should be used. Otherwise, a conservative estimate is
to assume that the delay time is proportional to the capacitive load.
SERIAL 1/0 ROUTINES
Routines for handling serial I/O are provided below. The
routines are written for 16-bit transmissions, but are trivially
expandable up to 64-bit transmissions by merely changing
the initial LBI instruction. The routines arbitrarily select register 0 as the I/O register. It is assumed that the external
device requires a logic low chip select. It is further assumed
that chip select is high and SK and SO are low on entry to
the routines. The routines exit with chip select high, SK and
SO low. GO is arbitrarily chosen as the chip select for the
external device.
If the capacitive load is too large to satisfy the delay time
criterion, then three choices are available. An external buffer may be used to drive the large load. The COPS instruction cycle may be slowed down. An external pullup resistor
may be added to speed up the LOW level to HIGH level
transition. The resistor will also increase the output LOW
level and increase the HIGH level to LOW level transition
time, but the increased time is negligible as long as the
output LOW level changes by less than O.3V. For a 100 pF
load, the standard COPS controller may use a 4.7k external
resistor, with the output LOW level increased by less than
SERIAL DATA OUTPUT
This routine outputs the data under the conditions specified
above. The transmitted data is preserved in the microcontroller.
OUT2:
LBI
0,12
point to start of
data word
14
select the external
device
SC
OGI
3-138
TABLE I. MICROWIRE Standard Family
Part Number
Features
DS3906
MM545X
COP470
COP472
COP430
(ADC83X)
COP498/499
COP452L
COP494
(NMC9306)
AM/PM Pll
lED Display
Driver
VF Display
Driver
lCDDisplay
Driver
AID
RAM & Timer
Frequency
Generator
E2PROM
GENERAL
Chip Function
Process
ECl
NMOS
PMOS
CMOS
CMOS
CMOS
NMOS
NMOS
Vee Range
4.75V-5.25V
4.5V-11V
-9.5Vto -4.5V
3.0V-5.5V
4.5V-0.3V
2.4V-5.5V
4.5V-6.3V
4.5V-5.5V
Pinout
20
40
20
20
B/14/20
14/B
14
14
HARDWARE INTERFACE
Min VIH/Max VIL
2.1V/0.7V
2.2V/0.BV
-1.5V/-4.0V
0.7Vec/0.BV
2.0V/O.BV
O.BVec/O.4Vee
2.0V/0.BV
2.0V/0.BV
SK Clock Range
0-625 kHz
0-500 kHz
0-250 kHz
4-250 kHz
10-200 kHz
4-250 kHz
25-250 kHz
0-250 kHz
Setup
Min
0.3 fLs
0.3 fLs
1.0 fLs
1 fLs
0.2 fLs
0.4 fLs
BOOns
0.4 fLs
Hold
Min
O.B fLs
(3)
50ns
100 ns
(Note 1)
0.2 fLs
0.4 fLs
1.0 fLs
0.4 fLs
(Note 4)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
2 fLs
(Note 2)
1 fLs
(Note 2)
2.0 fLs
Setup
0.3 fLs
0.4 fLs
1.0 fLs
Min
1 fLs
(Note 1)
0.2 fLs
0.2 fLs
(Note 1)
(Note 3)
0.2 fLs
HOLD
O.B fLs
(Note 3)
1.0 fLs
Min
1 fLs
(Note 2)
0.2 fLs
0
(Note 2)
(Note 3)
0
AM
BMHz
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
FM
120 MHz
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
250kHz
(Note 3)
(Note 3)
2.1 MHz (-21)
32 kHz (-15)
256-2100 kHz (-4)
64-525 kHz (- 2)
(Note 3)
Serial I/O
Protocol
1101 .. .020
101 ... 035
B Bits
At a Time
b1 ... b40
1xxx
1yyxxD6... DO
Start Bit
1yxxxx
1M... DD
Instruction/
Address Word
None
None
None
None
(Note 4)
(Note 4)
(Note 4)
(Note 4)
Write
Data
01
Read Data Prop
Delay
Chip
Enable
Max
Frequency
Range
Max Osc Freq.
SOFT
Note 1: Reference to SK rising edge.
Note 2: Reference to SK falling edge.
Note 3: Not defined.
Note 4: See data sheet for different modes of operation.
~SP-N"
I
.
N
an
"'I:t
LEI
8
JP
XAS
LD
XIS
JP
XAS
RC
CLRA
NOP
XAS
OGI
LEI
RET
SEND2
Z
20MS @ 4Us/INST
;5 SKT LOOPS?
;N,CONTI
;Y,DONE
11
• + 2
• -1
TWECONT
;CONTI TWE TIME
RET
• PAGE
;2 CYCLES DELAY
4
;***
START 494 I/O DRIVER SUBROUTINE
WD494:
RWLOOP:
JSRP
LD
XAS
XIS
SETUP
;ENTRY TO WRITE 494 REG A3-AO
;R/W 494 16 DATA BITS
3-144
»
Z
.
I/O ROUTINE TO EVALUATE COP494 (Continued)
101
102
103
104
105
106
107
108
109
110
III
112
113
114
115
116
117
118
119
120
104
105
107
108
109
lOA
lOB
10C
10D
10E
10F
110
III
112
114
115
116
117
Cl
3350
Dl
80
00
44
44
44
Cl
80
00
4F
00
3350
32
4F
95
48
JP
OGI
JP
RD494: JSRP
CLRA
NOP
NOP
NOP
JP
WI494: JSRP
CLRA
XAS
FINI: CLRA
OGI
RC
XAS
JSRP
RET
RWLOOP
0
FINI
SETUP
~
U1
;DESELECT 494 AFTER R/W DATA
N
;ENTRY TO RD 494 REG A3-AO
;FINISH SEND OUT A3-AO VIA SO
;WAIT lBIT TIME FOR VALID D15
RWLOOP
SETUP
0
TWEDLY
;ENTRY TO WRITE INST TO 494
;ENSURE SO = L
;ENSURE SO = L BETWEEN INST
;DESELECT 494 BETWEEN INST WRIT
;TURN OFF SK CLOCK
;DELAY TWE >20MS TO PULSE VPP=21
;RET OF WD494 OR RD494 OR WI494
.END
An even more severe consequence is that the monitor program executes an XAS instruction to get the contents of the
SIO register to the MOLE. Therefore, the SK latch is dependent on the state of the CARRY prior to the BREAKPOINT.
In order to guarantee the integrity of the SIO register, one
must carefully choose the position of the BREAKPOINT address.
SOFTWARE DEBUG OF SERIAL REGISTER FUNCTIONS
In order to understand the method of software debug when
dealing with the SIO register, one must first become familiar
with the method in which the COPS MOLETM (Development
System) BREAKPOINT and TRACE operations are carried
out. Once these operations are explained, the difficulties
which could arise when interrogating the status of the SIO
register should become apparent.
As can be seen, it is impossible to single-step or BREAKPOINT through a serial operation in the SIO register.
SERIAL OUT DURING BREAKPOINT
SERIAL OUT DURING TRACE
When the MOLE BREAKPOINTs, the COPS user program
execution is stopped and execution of a monitor-type program, within the COP device, is started. At no time does the
COP part "idle." The monitor program loads the development system with the information contained in the COP registers.
In the TRACE mode, the user's program execution is never
stopped. This mode is a real-time description of the program
counter and the external event lines; therefore, the four external event lines can be used as logic analyzers to monitor
the state of any input or output on the COPS device. The
external event lines must be tied to the 1/0 which is to be
monitored.
Note also that single-step is simply a BREAKPOINT on every instruction.
The state of these 1/0 (external event lines) is displayed
along with the TRACE information. The safest way to monitor the real-time state of SO is to use the TRACE function in
conjunction with the external event lines.
If the COP chip is BREAKPOINTed while a serial function is
in progress, the contents of the SIO register will be destroyed.
By the time the monitor program dumps the SIO register to
the MOLE, the contents of the SIO register will have been
written over by clocking in SI. To inspect the SIO register
using BREAKPOINT, an XAS must be executed prior to
BREAKPOINT; therefore, the SIO register will be saved in
the accumulator.
CONCLUSIONS
National's super-sensible MICROWIRE serial data exchange standard allows interfacing to any number of specialized peripherals using an absolute minimum number of
valuable 1/0 pins; this leaves more 1/0 lines available for
system interfacing and may permit the COPS controller to
be packaged in a smaller package.
3-145
•
National Semiconductor
Application Note 453
Venkata T. Gobburu
COPS™ Based Automobile
Instrument Cluster
ABSTRACT
Dedicated microprocessor systems find increasing applications in automobile instrumentation. Fuel injection systems,
digital radio tuners and similar applications employing the
microcontroller have become common place. This paper
describes a cost effective microcontroller implementation of
an automobile instrument cluster by the COPS group of National Semiconductor, Santa Clara. The instrument cluster
provides a vacuum fluorescent display of the vehicle speed,
engine RPM, odometers, battery voltage, engine oil pressure and the fuel level. A modular design involving a single
microcontroller in conjunction with peripherals to aid in data
acquisition from the transducers allows the quantities to be
computed with high accuracies and displayed on a real time
basis. The single microcontroller environment places severe
restrictions on the availability of RAM and ROM. Coupled
with the requirement of real time operation the application
poses a non trivial challenge. A nonvolatile RAM accumulates the mileage covered. Hamming code techniques ensure the integrity of the data contained in the nonvolatile
memory. Inclusion of diagnostics allows a rapid and thorough check against improper operation of the microcontroller, peripherals and the nonvolatile memory. This paper describes the implementation with a COP444L containing 128
nybbles of RAM and 2K bytes of ROM. A display updation
rate of 16 Hz can be comfortably realized.
Over the microcomputer usage has diversified dramatically
in its scope and breadth. Dedicated microprocessor systems find increasing application in automobile instrumentation and control. From its inception the automobile has acquired considerable sophistication. Increasing demands
have been made of the car. Fuel effiCiency, higher acceleration rates, simplicity of control and improved ride quality
rank high in the demands made of the car. In response the
automobile engine has evolved into a complex machine.
Crude methods to control or monitor its performance no
longer suffice. Microprocessor based fuel injection techniques and ignition control are becoming quite ubiquitous.
The automobile instrument cluster monitors the engine and
regularly updates a status display for the operator's benefit.
Pertinent information includes the vehicle speed, the engine
crankshaft rotational speed, oil pressure in the engine cylinders, condition of the battery and the mileage accumulated.
The instrument cluster provides a visual feedback link to the
operator allowing corrective action to be initiated as the
need arises.
THE AUTOMOBILE INSTRUMENT CLUSTER
The heart of the Automobile Instrument Cluster (AIC) lies in
obtaining raw data from various transducers and manipulating it to a form suitable for feedback to the human operator.
The feedback, normally visual, conveys the vehicle speed,
the engine rpm, the engine temperature, oil pressure, the
battery voltage and the odometer values. The AIC can be
viewed as a collection of either inherently independent or
weakly linked subtasks. Each subtask can be further partitioned into three blocks viz. of raw data collection, processing and displaying it. The component subtasks, in spite of
their high degree of independence, can be grouped on the
basis of signal available from the transducers. Grouping the
subtasks modularizes the design. Partitioning the design in
this manner highlights two groups, the first requires a frequency to be measured and the second a voltage level. The
two major groupings are briefly examined.
Transducers for the vehicle speed monitor the driveshaft
rotation. Computing the engine rpm involves measuring the
crankshaft revolution rate. The two independent problems
can be seen to basically consist of measuring revolution
rates. Transducers based on Hall effect phenomena have
been used with commendable success. Alternately the fact
that mounting magnets around the driveshaft circumference
generates a known number of pulses per shaft rotation can
be used effectively. A normally open cam operated reed
switch with closure to ground creates a simple revolution
transducer. In all the cases the transducer generates a frequency proportional to the quantity under consideration. Obviously some signal conditioning is required before using the
frequency with digital components. The describing function
can be simply stated as
V = k
xf
(1)
where
V is the quantity under measurement, the vehicle speed
or the engine rotational speed
k is a proportionality constant
f is the transducer freqeuncy output
The proportionality constant, k, can be suitably modified to
include changes back and forth between British and metric
units.
The problem of measuring the transducer output frequency
can be restated to be one of measuring the time period. In
. case of digital frequencies the equation (1) can be rewritten
as
V = k/(Ton
+ Toff)
(2)
where
Ton is the ON time and
Toff is the OFF time
while the remaining symbols retain their definition from the
earlier equation.
The remaining quantities such as the engine temperature,
oil pressure, battery voltage and available fuel prove to be
slow changing ones. The lower dynamics allow them to be
transduced as voltage level signals. Equation (3) states the
underlying relation and closely resembles the equations
stated above.
P=kXv
(3)
where
v is the voltage output of the transducer
P is the quantity under measurement
k is the proportionality constant
Evaluating the accumulating mileage depends indirectly
upon the vehicle speed subtask. Integrating the signal from
the vehicle speed transducer over time allows the mileage
to be accumulated. The associated problems of storing the
odometer information and ensuring its integrity require error
correcting techniques. They are covered in a later section of
the paper.
3-146
»
z
SYSTEM DESCRIPTION
The COPS Group of National Semiconductor, Santa Clara,
offers a wide array of microcontrollers and peripherals to
suit this application. Judicious selection of peripherals to aid
the microcontroller can reinforce the partitioning suggested
earlier to considerably simplify the implementation. Figure 1
presents a functional block diagram of the AIC.
A COP444L four bit microcontroller provides the necessary
computing and decision making capability. Equipped with
128 nybbles of RAM space organized in a matrix fashion
and 2K ROM space for storage of the control program, the
COP444L operating at an instruction cycle rate of 16 microseconds sequentially obtains information from the peripherals and formats the manipulated results to be manageable
by the display drivers. Transducers for the vehicle speed
and the engine speed provide proportional frequency signals. Two COP452 peripherals, placed in a Waveform Measure Mode, track the ON time and OFF time of the conditioned transducer outputs. Voltage level Signals available
from the transducers for the engine temperature, oil pressure, battery condition and the fuel tank can be monitored
by a COP438, an eight channel AID converter. An electronically erasable non volatile RAM, the COP494, allows the
odometer information to be stored safely under power down
conditions.
probability of the microcontroller ROM failing proves to be
negligibly small compared to a fault developing in the hardware interconnections. Also the idea of encoding in ROM
the algorithm to check ROM data proves suspect. Control
program stored in the ROM forms the kernel assumed to be
functioning correctly. Writing and reading back an alternating pattern of ones and zeros in the microcontroller RAM
checks for leakage of data into adjacent locations. Applying
a known voltage, derived locally, to one of the four unused
channels on the AID converter allows it to be tested. The
architecture of the COP452 peripherals consists of two independent register-counter pairs. The counters count down
from the initial value. To test the COP452 both the register
counter pairs have to be checked. By placing the two in a
Duty Cycle Mode, the counters can be loaded with initial
values from the registers and set to count down. The contents of the counters after a predetermined delay can detect
incorrect operation of the device. A fault at the level of a
register-counter pair can thus be isolated.
The COP494 stores the odometer information. It becomes
vital to maintain the integrity of the information stored in the
nonvolatile memory. Continuous use of particular locations
in the COP494 can result in failures, typically bit dropouts. It
is imperative to be capable of recovering from such errors.
Requiring a single COP494 unit to last at least the expected
lifetime of the vehicle influences the design of the storage
scheme. The AIC implementation described in this paper
depends upon Hamming encoding techniques to provide
single bit error recovery. Subsequent to recovering from a
single bit error all data transactions are carried out from a
new location. A flashing display sequence alerts the operator of the occurrence of a non-recoverable error. Suspending all normal functions during such conditions can be used
to force the vehicle to be taken to an authorized dealer.
Breaking up the odometer data into sections allows updating of particular sections as opposed to restoring the whole
every time. Such a strategy maximizes the lifetime of the
nonvolatile memory.
A combination of LEDs, vacuum fluorescent displays and
high intenSity lamps comprise the optical elements of the
AIC Standard eight segment alphanumeric and bargraph
format displays have been used. A 32 segment LED bargraph, controlled by a MM5450 static display driver, displays
the engine rpm. Eight segment alphanumeric vacuum fluorescent displays are used for the vehicle speed and the
odometer values. Sixteen segment vacuum fluorescent bargraph displays are used for the engine temperature and
available fuel quantity. The battery voltage and oil pressure
utilize eight segment vacuum fluorescent bargraph displays.
Any potentially dangerous situations detected by the
COP444L are underlined by high intenSity lamps. Five
COP470 display drivers multiplex the various displays under
the microcontroller's orchestration.
Single pole single throw switches allow the user to select
between the British or the metric units, the trip or the accumulated odometer and reset the trip odometer.
.
~
U1
W
SOFTWARE DESCRIPTION
The functional objectives of the AIC and the hardware required to realize them have been detailed in earlier sections
of the paper. A summary of the software features completes
the description and aids in developing a global understanding of the AIC. The AIC software, written in COP microcontroller assembly language, reflects the modular nature of the
problem. The finite amount of memory of ROM space available on the COP444L coupled with real time operation requirements makes programming the AIC a non-trivial problem. Each subtask grouping has been organized as a distinct block of code. The microcontroller sequentially processes each subtask. A brief examination of the salient features follows.
It must be borne in mind that the COP452 peripheral captures an instantaneous picture of the frequency. The
strength of the magnets, mounted circumferentially on the
driveshaft to transduce revolution rate, cannot be precisely
controlled. As a result the transducer, although generating a
fixed number of pulses per revolution of the driveshaft, produces a pulse train showing both pulse period and duty cycle variations. Directly using the pulse period from the
SYSTEM DIAGNOSTICS
Diagnostics aid in isolating faulty components within a system. The algorithmic nature of the diagnostic procedure allows it to be implemented via a microprocessor. A great
deal of attention has been focused on diagnostics as considerable cost savings can accrue from a microprocessor
based scheme minimizing human involvement. Programming the AIC, in addition to its normal functions, with self
test capabilities increases its potential for high volume applications. Normally diagnostics imply using independent
means to evaluate the system's performance. Attempting to
incorporate self test capabilities necessitates adopting an
"inside out" strategy. A basic kernel is first evaluated as
functioning correctly. Over iterations the kernel expands by
establishing correct operation of other modules.
The AIC implementation described in this paper has an extensive repertoire of diagnostics to check the microcontroller and ensure correct operation of the peripherals. The
3-147
•
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3-153
•
CONCLUSIONS
REFERENCES
Multiplex wiring system potentially seems to be a good reo
placement for conventional wiring system. Reduced com·
plexity, increased flexibility and diagnostic capability could
be achieved by incorporating microcontroller devices at
nodes within the wiring system. The 4·bit microcontrollers
selected are available in a price range, as low as 49¢, that
will allow multiplex wiring to compare favorably on a cost·
performance basis with the conventional harness.
1. Michael W. Lowndes and Paul E. V. Phillips, "The Motor·
car Multiplex Systems", lEE Conference on Automotive
Electronics, 229, England, Nov. 1983.
2. R. F. Robins/W. J. Brittain/M. R. Lunt, "A Car Multiplex·
Wiring System with Self Coding Control Modules", lEE
Conference on Automotive Electronics, 229, Ford Motor
Company, UK, Nov. 1983.
3. Booth, J. A., 1983 "Vehicle Interconnection Systems for
the Future", lEE Conference on Automotive Electronics,
London, Nov. 1983.
4. International Rectifier, HEXFET Databook, 1985.
3·154
»
z
.
Dual Tone
Multiple Frequency (DTMF)
National Semiconductor
Application Note 521
Verne H. Wilson
The DTMF (Dual Tone Multiple Frequency) application is
associated with digital telephony, and provides two selected
output frequencies (one high band, one low band) for a duration of 100 ms. A benchmark subroutine has been written
for the COP820C/840C microcontrollers, and is outlined in
detail in this application note. This DTMF subroutine takes
110 bytes of COP820C/840C code, consisting of 78 bytes
of program code and 32 bytes of ROM table. The timings
in this DTMF subroutine are based on a 20 MHz
COP820C/840C clock, giving an instruction cycle time of
1 Ils.
The matrix for selecting the high and low band frequencies
associated with each key is shown in Figure 1. Each key is
uniquely referenced by selecting one of the four low band
frequencies associated with the matrix rows, coupled with
selecting one of the four high band frequencies associated
with the matrix columns. The low band frequencies are 697,
770, 852, and 941 Hz, while the high band frequencies are
1209, 1336, 1477, and 1633 Hz. The DTMF subroutine assumes that the key decoding is supplied as a low order hex
digit in the accumulator. The COP820C/840C DTMF subroutine will then generate the selected high band and low
band frequencies on port G output pins G3 and G2 respectively for a duration of 100 ms.
The solution then is to use the program to produce the selected low band frequency as well as keep track of the
100 ms duration. This is achieved by using three programmed register counters RO, R2, and R3, with a backup
register R1 to reload the counter RO. These three counters
represent the half period, the 100 ms quotient, and the
100 ms remainder associated with each of the four low
band frequencies.
The COP820C/840C each contain only one timer. The
problem is that three different times must be generated to
satisfy the DTMF application. These three times are the periods of the two selected frequencies and the 100 ms duration period. Obviously the single timer can be used to generate anyone (or possibly two) of the required times, with the
program having to generate the other two (or one) times.
The solution to the DTMF problem lies in dividing the 100
ms time duration by the half periods (rounded to the nearest
micro second) for each of the eight frequencies, and then
examining the respective high band and low band quotients
and remainders. The results of these divisions are detailed
in Table I. The low band frequency quotients range from 139
to 188, while the high band quotients range from 241 to 326.
The observation that only the low band quotients will each
fit in a single byte dictates that the high band frequency be
produced by the 16 bit (2 byte) COP820C/840C timer running in PWM (Pulse Width Modulation) Mode.
The theory of operation in producing the selected low band
frequency starts with loading the three counters with values
obtained from a RAM table. The half period for the selected
frequency is counted out, after which the G2 output bit is
toggled. During this half period countout, the quotient counter is decremented. This procedure is repeated until the
quotient counter counts out, after which the program
branches to the remainder loop. During the remainder loop,
the remainder counter counts out to terminate the 100 ms.
Following the remainder countout, the G2 and G3 bits are
both reset, after which the DTMF subroutine is exited. Great
care must be taken in time balancing the half period loop for
the selected low band frequency. Furthermore, the toggling
of the G2 output bit (achieved with either a set or reset bit
instruction) must also be exactly time balanced to maintain
the half period time integrity. Local stall loops (consisting of
a DRSZ instruction followed by a JP jump back to the DRSZ
for a two byte, six instruction cycle loop) are embedded in
both the half period and remainder loops. Consequently, the
ROM table parameters for the half period and remainder
counters are approximately only one sixth of what otherwise
might be expected. The program for the half period loop,
along with the detailed time balancing of the loop for each
of the low band frequencies, is shown in Figure 2.
The DTMF subroutine makes use of two 16 byte ROM tables. The first ROM table contains the translation table for
the input hex digit into the core vector. The encoding of the
hex digit along with the hex digit ROM translation table is
shown in Table II. The row and column bits (RR, CC) representing the low band and high band frequencies respectively of the keyboard matrix shown in Figure 1, are encoded in
TABLE I. Frequency Half Periods,
Quotients, and Remainders
Half
Freq.
Period
Hz
0.5P
1633
c
ZIIl
<,
1477
ClO
.....
:t:a::
(.!)!...
1336
:I:
1209
697
c
::'iYl
770
~e:
852
Cl8
941
-
1
1
2
3
A
4
5
6
B
7
8
9
C
•
0
#
0
o
Quotient Remainder
139
649
154
54
587
170
210
941
531
188
172
414
(256 + 158)
241
226
374
1336 374.25
High
(256 + 118)
Band
339
Freq.'s 1477 338.52
(256 + 83)
267
142
294
334
326
244
531.35
1209 413.56
o
w
2
100 ms/0.5P
717
R
3
Half
Period
In Ils
697 717.36
Low
770 649.35
Band
Freq.'s 852 586.85
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COLUI.lNS
TL/DD/9662-1
FIGURE 1. DTMF Keyboard Matrix
3-155
1633 306.18
306
(256 + 50)
337
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1l00XXll
1l00XXI0
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3·157
--•
~
TABLE IV. Frequency Parameter ROM Translation Table
Z
Z
PAGEl
1
U1
I\)
...A.
DTMF PROGRAM FOR COP820C/840C
DTMF - DUAL TONE MULTIPLE FREQUENCY
VERNE H. WILSON
8/25/87
PROGRAM NAMEI DTMF.MAC
.TITLE DTMF
******* THE DTMF SUBROUTINE CONTAINS 110 BYTES *******
***** THE DTMF SUBROUTINE TIMES OUT IN 100MSEC *****
** FROM THE FIRST TOGGLE OF THE G2/G3 OUTPUTS **
*** BASED ON A 20 MHZ COP820C/840C CLOCK ***
G PORT IS USED FOR THE TWO OUTPUTS
HIGH BAND (HB) FREQUENCY OUTPUT ON G3
LOW BAND (LB) FREQUENCY OUTPUT ON G2
TIMER COUNTS OUT
HB FREQUENCIES
PROGRAM COUNTS OUT
LB FREQUENCIES
100 MSEC DIVIDED BY LB HALF PERIOD QUOTIENT
100 MSEC DIVIDED BY LB HALF PERIOD REMAINDER
FORMAT FOR THE 16 HEX DIGIT MATRIX VECTOR IS 1101RRCC,
WHERE - RR IS ROW SELECT (lB FREQUENCIES)
- CC IS COLUMN SELECT (HB FREQUENCIES)
30
31
32
FORMAT FOR THE 16 CORE VECTORS FROM THE MATRIX SELECT
TABLE IS TTOOXXOO, WHERE - TT IS HB SELECT
XX IS LB SELECT
34
35
36
37
38
FREQUENCY VECTORS (HB & LB) FOR FREQ PARAMETER TABLE
MADE FROM CORE VECTORS
33
39
40
41
42
43
44
45
46
47
48
49
50
51
HB FREQUENCY VECTORS(4) END WITH 00 FOR TIMER COUNTS,
WHERE VECTOR FORMAT IS 1100TTOO
LB FREQUENCY VECTORS(12) END WITH:
11 FOR HALF PERIOD LOOP COUNTS,
WHERE VECTOR FORMAT IS 1100XXll
10 FOR 100 MSEC DIVIDED BY HALF PERIOD QUOTIENTS,
WHERE VECTOR FORMAT IS 1100XX10
01 FOR 100 MSEC DIVIDED BY HALF PERIOD REMAINDERS,
WHERE VECTOR FORMAT IS 1100XX01
HEX DIGIT MATRIX TABLE AT HEX 01D* (OPTIONAL LOCATION,
DEPENDING ON 'ADD A,IODO' INST. IMMEDIATE VALUE)
FREQ PARAMETER TABLE AT HEX 01C*
(REQUIRED LOCATION)
TL/DD/9662-2
3-159
,....
.
N
Lt)
Z
«
NATIONAL SEMICONDUCTOR CORPORATION
COP800 CROSS ASSEMBLER,REV:B,20 JAN 87
DTMF
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
96
;MAGIC:
OODO
00D1
00D4
00D5
OODC
OOEA
OOEE
OOEF
OOFO
00F1
00F2
00F3
00F4
0000
0002
0005
0008
OOOA
OOOC
OOOD
OOOF
0011
0012
0014
0015
0016
0018
0019
OOlA
001C
CORE VECTOR
TTOOXXOO
TIMER
Rl
R2
R3
T
F
Q
R
TTOO
XXII
XXI0
XXOI
;DECLARATIONS:
PORTLD = aDO
PORTLC = ODI
PORTGD = OD4
PORTGC = OD5
PORTD = ODC
TIMERLO = OEA
CNTRL = OEE
PSW = OEF
RO = OFO
R1 = OF1
R2 = OF2
R3 = OF3
R4 = OF4
PORTL DATA REG
PORTL CON FIG REG
PORTG DATA REG
PORTG CONFIG REG
PORTD REG
TIMER LOW COUNTER
CONTROL REG
PROC STATUS WORD
LB FREQ LOOP COUNTER
LB FREQ LOOP COUNT
LB FREQ Q COUNT
LB FREQ R COUNT
LB FREQ TABLE VECTOR
;
DD2F
BCD1FF
BCD080
DEDC
9EOO
AE
3160
DEDC
AE
9405
A6
6C
9DDO
Al
BO
9CDO
EF
START:
LOOP:
2
.FORM
;
;
PAGE:
LD
LD
LD
LD
LD
LD
JSR
LD
LD
ADD
X
RBIT
LD
SC
RRC
X
JP
SP,102F
PORTLC,IOFF
PORTLD,1080
8,IPORTD
[8],10
A,[B]
DTMF
8,IPORTD
A,[B]
A,15
A,[B]
4,[B]
A,PORTLD
A
A,PORTLD
lOOP
HEX DIGIT MATRIX
1 2 3 A
4 5 6 8
7 8 9 C
3( 0 I D
DTMF TEST LOOP
HEX MATRIX DIGIT
TO SUBROUTINE IS
OUTPUT TO PORTD
DO WILL TOGGLE
FOR EACH CALL OF
DTMF SUBROUTINE
PORTL OUTPUTS
PROVIDE SYNC
OUTPUT ORDER IS
1,5,9,D,4,8,I,A,
7,O,3,B,3(,2,6,C
TL/DD/9662-3
3-160
.
l>
97
98
99
100
101
102
103
104
105
106
107
108
109
110
III
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
0160
0160
0162
0164
0165
z
. =0160
U1
;
DED5
9B3F
6B
6A
DTMFI
LD
LD
RBIT
RBIT
B,IPORTGC
[B-],103F
3,[B]
2,[B]
ADD
LAID
A,IODO
LD
X
LD
OR
LD
LD
X
LD
LAID
X
DRSZ
IFBNE
JP
B,IO
A,[B]
A, [B]
A,IOC3
B,IR1
X,IR4
A, [X]
A,[X]
LD
LD
SWAP
OR
LAID
LD
LD
LD
X
LD
LD
B,IO
A,[B]
A
A,IOCO
LD
LD
B,IPORTGD
X,IR1
LD
IFBIT
JP
X
SBIT
JP
Nap
RBIT
X
DRSZ
JP
JP
A,[X-]
2,[B]
BYPI
A,[X+]
2,[B]
BYP2
2,[B]
A,[X+]
R2
LUP2
FINI
DRSZ
JP
RO
LUP2
Nap
LD
IFEQ
JP
A,[X]
A, 11 04
LUPI
N
.....
;
OPTIONAL
OPTIONAL
;
DIGIT MATRIX TABLE
j
j
LB FREQ TABLES
(3 PARAMETERS)
;
;
HB FREQ TABLE
(1 PARAMETER)
;
START TIMER PWM
;
TEST LB OUTPUT
;
SET LB OUTPUT
;
RESET LB OUTPUT
;
DECR. QUaT. COUNT
;
Q COUNT FINISHED
;
;
DECR. F COUNT
LB (HALF PERIOD)
j
j
0166 94DO
0168 A4
j
0169
016A
016 B
016C
016E
0170
0172
0173
0174
0175
0176
0177
0178
5F
A6
AE
97C3
DEF1
DCF4
B6
BE
A4
A2
C4
44
FA
0179
017A
017B
017C
017E
017F
0181
0183
0185
0186
0188
5F
AE
65
97CO
A4
DEEA
9AOF
9AOO
A2
9AOl
9EBO
LUPI
;
;
018A DED4
018C DCF1
;
018E
018F
0190
0191
0192
0193
0194
0195
0196
0197
0198
0199
BB
72
03
B2
7A
03
B8
6A
B2
C2
01
OC
LUP1:
019A CO
019B FE
LUP21
BYP11
BYP21
,
;
019C
019D
019E
01AO
B8
BE
9268
ED
;
DIAl
01A2
01A4
01A5
B8
925D
E9
FE
BACKI
;
01A6 C3
01A7 FE
01A8 BDEE6C
01AB 6B
01AC 6A
01AD 8E
FINII
;
A,[B+]
R4
14
LUP
B,ITIMERLO
[B+1.115
[B+],IO
A,[B+]
[B+],11
[B],IOBO
;
;
;
JE JEJooonnnonOOE
Nap
IFEQ
JP
JP
A,193
LUPI
BACK
;
;
BALANCE
LB FREQUENCY
HALF PERIOD
RESIDUE
DELAY FOR
EACH OF 4
LB FREQ'S
j
JEJEJEJEJEJEJEJEJEJE*JEJE
DRSZ
JP
R3
FINI
;
DECR. REM. COUNT
R CNT NOT FINISHED
RBIT
RBIT
RBIT
4,CNTRL
3,[B]
2, [B]
j
;
j
;
j
STOP TIMER
CLR HB OUTPUT
CLR LB OUTPUT
RET
;
TLlDD/9662-4
3-161
•
....
.
N
II)
Z
~g=~~~~~~~~5~~
Is
17 @
14 12 EXUI 8, 83 85 87 GNO
GJ) ® ® @
00@ @O,
NC
CKO
10
11
ST1
ST2
O2 @ @ 03
EI@ @04
05
RESET
AO
A1
A2
A3
A4
AS
AS
A7 _
RDY/HLO
CKt
OGNO
NC
NC
@ @ 06
@ EXt.4
@ P,
®@@
@ @ @ eKO
10 @> @I,
ST1
RESET
A,
@ !@ ST2
@ ~ Ao
@ @l A2
07 @
Po @
A3
®
As
@ @
P2@ @P3
A7@
@~
@® @@@@@@ @
@DGNO
NC@
@ A4
As
8,4 8,2 8,0 8a A14A12A'0 Aa CK2
@@®®@@@@@
8,5 8,38 " 8g A,sA,3 Al1 AgVCCl
TLlDD/BBOI-12
Top View
(looking down on component side of PC Board)
TL/DD/880' -34
Top View
Order Number HPC16083EL or HPC16083U
Soe NS Package Number EL68A or U68A
Order Number HPC16083T
Available In TapePak
4-15
.......
::I:
o
INDEX MARK
15
NC
"'C
Top View
TL/DD/8BOI-II
TapePak Package
PO
P1
P2
P3
NC
NC
NC
::I:
oN
::I:
Plastic, Leadless and Leaded Chip Carriers
CLOCK PINS
CKI
The Chip System Clock Input
NC
NC
17
16
00
01
02
03
EI
04
05
06
07
EXt.4
o
......
0')
o0)
w
.......
Cot)
o
o
CD
"'I:t
o
D..
::I:
.......
Cot)
o
o
CD
Cot)
oD..
::I:
.......
Cot)
Ports A & B
The highly flexible A and B ports are similarly structured.
The Port A (see Figure 7), consists of a data register and a
direction register. Port B (see Figures 8, 9, 10) has an alternate function register in addition to the data and direction
registers. All the control registers are read/write registers.
A write operation to a port pin configured as an input causes
the value to be written into the data register, a read operation returns the value of the pin. Writing to port pins configured as outputs causes the pins to have the same value,
reading the pins returns the value of the data register.
The associated direction registers allow the port pins to be
individually programmed as inputs or outputs. Port pins selected as inputs, are placed in a TRI-STATE mode by resetting corresponding bits in the direction register.
Primary and secondary functions are multiplexed onto Port
B through the alternate function register (BFUN). The secondary functions are enabled by setting the corresponding
bits in the BFUN register.
o
o
CD
N
o
D..
::I:
.......
WRITE PORT
Cot)
o
o
CD
,....
o
D..
::I:
.......
READ DIRA
Cot)
co
o
CD
"'I:t
o
D..
WRITE REGISTER
::I:
.......
Cot)
co
o
CD
Cot)
o
D..
READ PORT A
::I:
TLlDD/8801-13
FIGURE 7. Port A: I/O Structure
.......
Cot)
co
o
CD
N
ALTERNATE
rUNCTION OUTPUT
o
D..
::I:
.......
Cot)
co
o
CD
,....
o
D..
::I:
READ DIR B
D
A
T
WRITE DIR B
A
READ PORT B
WRITE BrUN
READ BrUN
TL/DD/8801-14
FIGURE 8. Structure of Port B Pins 80, 81, 82, 85, 86 and 87 (Typical Pins)
4-16
:I:
."
Ports A & B (Continued)
o
.....
0)
C)
CD
W
.....
:I:
."
oN
0)
C)
CD
W
.....
:I:
."
ow
0)
C)
WRITE BWN
CD
W
.....
:I:
."
o
~
0)
C)
CD
W
.....
:I:
."
o
.....
0)
C)
C)
w
.....
WRITE DIR B
:I:
."
oN
READ DIR B
TLIDD/8801-15
FIGURE 9. Structure of Port 8 Pins 83, 84, 88, 89, 813 and 814 (Timer Synchronous Pins)
0)
C)
C)
w
.....
:J:
."
o
w
0)
C)
C)
w
.....
:I:
."
o
~
0)
C)
C)
w
WRITE DIR B
------------.
READ PORT B
I
I
I
I
I
I
I
-----------_.
I
WRITE BFUN
MODE
EXPANDED
OR ROM LESS
READ BFUN
TLIDD/8801-16
FIGURE 10. Structure of Port 8 Pins 810,811,812 and 815 (Pins with 8us Control Roles)
4-17
~
o
o
may be decreased without
altering the state of the machine. There are two ways of
exiting the HALT mode: via the RESET or the NMI. T~e
RESET input reinitializes the processor. Use of the NMllnput will generate a vectored interrupt and resume operation
from that point with no initialization. The HALT mode can be
enabled or disabled by means of a control register HALT
enable. To prevent accidental use of the HALT mode the
HALT enable register can be modified only once.
Vector
Address
Interrupt
Source
Arbitration
Ranking
$FFFF:FFFE
$FFFD:FFFC
RESET
Nonmaskable external on
rising edge of 11 pin
External interrupt on 12 pin
External interrupt on 13 pin
External interrupt on 14 pin
Overflow on internal timers
Internal on the UART
transmit/receive complete
or external on EXUI
External interrupt on EI pin
0
1
$FFFB:FFFA
$FFF9:FFF8
$FFF7:FFF6
$FFF5:FFF4
$FFF3:FFF2
$FFF1:FFFO
4-20
2
3
4
5
6
7
::I:
interrupts may be disabled. IRPD is a Read/Write register.
The bits corresponding to the maskable, external interrupts
are normally cleared by the HPC16083 after servicing the
interrupts.
Interrupt Arbitration
The HPC16083 contains arbitration logic to determine which
interrupt will be serviced first if two or more interrupts occur
simultaneously. The arbitration ranking is given in Table IV.
The interrupt on RESET has the highest rank and is serviced first.
For the interrupts from the on-board peripherals, the user
has the responsibility of resetting the interrupt pending flags
through software.
The NMI bit is read only and 12, 13, and 14 are designed as to
only allow a zero to be written to the pending bit (writing a
one has no affect). A LOAD IMMEDIATE instruction is to be
the only instruction used to clear a bit or bits in the IRPD
register. This allows a mask to be used, thus ensuring that
the other pending bits are not affected.
Interrupt Processing
Interrupts are serviced after the current instruction is completed except for the RESET, which is serviced immediately.
RESET and EXUI are level-LOW-sensitive interrupts and EI
is programmable for edge-(RISING or FALLING) or level(HIGH or LOW) sensitivity. All other interrupts are edge-sensitive. NMI is positive-edge sensitive. The external interrupts
on 12, 13 and 14 can be software selected to be rising or
falling edge. External interrupt (EXUI) is shared with the
UART interrupt. This interrupt is level-low sensitive. To select this interrupt disable the ERI and ETI UART interrupt
bits in the ENUI register. To select the UART interrupt leave
this pin floating or tie it high.
INTERRUPT CONDITION REGISTER (IReD)
Three bits of the register select the input polarity of the
external interrupt on 12, 13, and 14.
Servicing the Interrupts
The Interrupt, once acknowledged, pushes the program
counter (PC) onto the stack thus incrementing the stack
pointer (SP) twice. The Global Interrupt Enable bit (GIE) is
copied into the CGIE bit of the PSW register; it is then reset,
thus disabling further interrupts. The program counter is
loaded with the contents of the memory at the vector address and the processor resumes operation at this point. At
the end of the interrupt service routine, the user does a
RETI instruction to pop the stack and re-enable interrupts if
the CGIE bit is set, or RET to just pop the stack if the CGIE
bit is clear, and then returns to the main program. The GIE
bit can be set in the interrupt service routine to nest interrupts if desired. Figure 14 shows the Interrupt Enable Logic.
Interrupt Control Registers
The HPC16083 allows the various interrupt sources and
conditions to be programmed. This is done through the various control registers. A brief description of the different control registers is given below.
INTERRUPT ENABLE REGISTER (ENIR)
RESET and the External Interrupt on 11 are non-maskable
interrupts. The other interrupts can be individually enabled
or disabled. Additionally, a Global Interrupt Enable Bit in the
ENIR Register allows the Maskable interrupts to be collectively enabled or disabled. Thus, in order for a particular
interrupt to be serviced, both the individual enable bit and
the Global Interrupt bit (GIE) have to be set.
RESET
The RESET input initializes the processor and sets ports A
and B in the TRI-STATE condition and port P in the LOW
state. RESET is an active-low Schmitt trigger input. The
processor vectors to FFFF:FFFE and resumes operation at
the address contained at that memory location (which must
correspond to an on board location). The Reset vector address must be between FOOD and FFFF when using the
HPC16003.
INTERRUPT PENDING REGISTER (IRPD)
The IRPD register contains a bit allocated for each interrupt
vector. The occurrence of specified interrupt trigger conditions causes the appropriate bit to be set. There is no indication of the order in which the interrupts have been received. The bits are set independently of the fact that the
"tJ
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en
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w
.......
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o
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en
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.......
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ow
en
o
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w
.......
::I:
"tJ
o
~
en
o
C)
w
.......
::I:
"tJ
o......
en
o
o
w
.......
::I:
"tJ
oN
en
o
o
w
.......
::I:
"tJ
ow
en
o
o
w
.......
::I:
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o
~
en
o
o
w
4-21
HPC 16083/HPC26083/HPC36083/HPC46083/HPC16003/HPC26003/HPC36003/HPC46003
t.CSB
EI
~l
@1 !~
0-1 !~
B-1 ! ~
LSB
ENIR
UART
TIt.CBffi
14
INT
13
INT
12
INT
•
GIE
IRPD
p.W
DONE
1--__---1 LSB
-
11
INT
12
INT
~--~~~~~4l~~[r
1-------1
13
INT
Lfl,----------I--IPl
1----1-------1--------1-------1-------1
~--~
14
INT
INTERRUPT
~
~--~--~~--~----~~~--------------~~~ ~
~:;~,------------~~--~
TIt.Cffi
'--
'---
~__+-____~____~~~______________________-*~~
~
~
T7TIP
T7 TIE
~~~
~11P~
RBFl~
ffil-L)"'""
U~l t-----t-----tLflJ---------HFD-
!J JL--I
EI
0-
J--i...
Ln
~
TLIDD/6601-20
FIGURE 14. Block Diagram of Interrupt Logic
Timer Overview
software control. Once enabled, the timers count down, and
upon underflow, the contents of its associated register are
automatically loaded into the timer.
The HPC16083 contains a powerful set of flexible timers
enabling the HPC16083 to perform extensive timer functions; not usually associated with microcontrollers.
The HPC16083 contains nine 16-bit timers. Timer TO is a
free-running timer, counting up at a fixed CKI/16 (Clock Inputl16) rate. It is used for Watchdog logic, high speed event
capture, and to exit from the IDLE mode. Consequently, it
cannot be stopped or written to under software control. Timer TO permits precise measurements by means of the capture registers 12CR, 13CR, and 14CR. A control bit in the
register TMMODE configures timer T1 and its associated
register R1 as capture registers 13CR and 12CR. The capture registers 12CR, 13CR, and 14CR respectively, record the
value of timer TO when specific events occur on the interrupt pins 12, 13, and 14. The control register IRCD programs
the capture registers to trigger on either a rising edge or a
falling edge of its respective input. The specified edge can
also be programmed to generate an interrupt (see Figure
:x:
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~13
:x:
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en
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w
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:x:
"'tJ
(')
01::0-
en
o
15).
14
The HPC16083 provides an additional 16-bit free running
timer, T8, with associated input capture register EICR (External Interrupt Capture Register) and Configuration Register, EICON. EICON is used to select the mode and edge of
the EI pin. EICR is a 16-bit capture register which records
the value of T8 (which is identical to TO) when a specific
event occurs on the EI pin.
.----.
Rl :... __ ~
I
~
.... __ !
_~ ~.
:x:
"'tJ
SOFTWARE
CONFIGURED
(')
T1
I
.....
I
... _......
I
I
SOFTWARE
rc --------•
CONfiGURED
T1 UNfL
............
·""~CKI/16
TL/DD/8801-21
FIGURE 15. Timers TO, T1 and T8 with Four Input
Capture Registers
The timers T2 and T3 have selectable clock rates. The
clock input to these two timers may be selected from the
following two sources: an external pin, or derived internally
by dividing the clock input. Timer T2 has additional capability of being clocked by the timer T3 underflow. This allows
the user to cascade timers T3 and T2 into a 32-bit timer/
counter. The control register DIVBY programs the clock input to timers T2 and T3 (see Figure 16).
SYNCHRONOUS OUTPUTS
The flexible timer structure of the HPC16083 simplifies
pulse generation and measurement. There are four synchronous timer outputs (TSO through TS3) that work in conjunction with the timer T2. The synchronous timer outputs
can be used either as regular outputs or individually programmed to toggle on timer T2 underflows (see Figure 16).
The timers T1 through T7 in conjunction with their registers
form Timer-Register pairs. The registers hold the pulse duration values. All the Timer-Register pairs can be read from
or written to. Each timer can be started or stopped under
Timer/register pairs 4-7 form four identical units which can
generate synchronous outputs on port P (see Figure 17).
I----+TSI
1-....-.1210
TL/DD/8601-22
4-23
en
o
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w
.......
:x:
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en
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w
.......
:x:
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en
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w
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:x:
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01::0-
en
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w
I---+T$o
I---+TS,
I---+TS,
FIGURE 16. Timers T2-T3 Block
Q)
w
.......
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o
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CD
oo::t
(.)
Timer Overview (Continued)
D..
::I:
~
CD
I
......
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o
o
I
C")
(.)
D..
::I:
......
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CD
I
T4-T7
t-_U_N_FL_-+~
I
I
I
I
T4-T7
~OUT
CKI/16
N
(.)
D..
::I:
D..
::I:
......
C")
CO
o
CD
oo::t
(.)
D..
::I:
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C")
CO
o
CD
C")
(.)
D..
::I:
......
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CO
o
CD
N
(.)
D..
::I:
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CO
o
CD
,...
(.)
D..
::I:
TSl
n
TS2
j-Te+TI.J
T9-l
~TS3
j--+-Th
TLIDD/BBOl-25
Timer-Register pairs 4 through 7 are identical.
FIGURE 19. Synchronous Pulse Generation
CD
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dog register not be written to before Timer TO overflows
twice, or more often than once every 4096 counts, an infinite loop condition is assumed to have occurred. An illegal
condition also occurs when the processor generates an illegal address when in the Single-Chip modes. * Any illegal
condition forces the Watchdog Output (WO) pin low. The
WO pin is an open drain output and can be connected to the
RESET or NMI inputs or to the users external logic.
FIGURE 17. Timers T4-T7 Block
Maximum output frequency for any timer output can be obtained by setting timer/register pair to zero. This then will
produce an output frequency equal to % the frequency of
the source used for clocking the timer.
Timer Registers
·Note: See Operating Modes for details.
There are four control registers that program the timers. The
divide by (DlVBY) register programs the clock input to timers T2 and T3. The timer mode register (TMMODE) contains
control bits to start and stop timers T1 through T3. It also
contains bits to latch and enable interrupts from timers TO
through T3. The control register PWMODE similarly programs the pulse width timers T 4 through T7 by allowing
them to be started, stopped, and to latch and enable interrupts on underflows. The PORTP register contains bits to
preset the outputs and enable the synchronous timer output
functions.
MICROWIRE/PLUS
MICROWIRE/PLUS is used for synchronous serial data
communications (see Figure 20). MICROWIRE/PLUS has
an 8-bit parallel-loaded, serial shift register using SI as the
input and SO as the output. SK is the clock for the serial
shift register (SIO). The SK clock Signal can be provided by
an internal or external source. The internal clock rate is programmable by the DIVBY register. A DONE flag indicates
when the data shift is completed.
Timer Applications
~---------------'SO
The use of Pulse Width Timers for the generation of various
waveforms is easily accomplished by the HPC16083.
SI
Frequencies can be generated by using the timer/register
pairs. A square wave is generated when the register value is
a constant. The duty cycle can be controlled simply by
changing the register value.
----.SK
T20UT
TL/DD/BB01-24
FIGURE 18. Square Wave Frequency Generation
Synchronous outputs based on Timer T2 can be generated
on the 4 outputs TSO-TS3. Each output can be individually
programmed to toggle on T2 underflow. Register R2 contains the time delay between events. Figure 19 is an example of synchronous pulse train generation.
Watchdog Logic
TL/DD/BB01-26
FIGURE 20. MICROWIRE/PLUS
The Watchdog Logic monitors the operations taking place
and signals upon the occurrence of any illegal activity. The
illegal conditions that trigger the Watchdog logic are potentially infinite loops and illegal addresses. Should the Watch-
The MICROWIRE/PLUS capability enables it to interface
with any of National Semiconductor's MICROWIRE peripherals (Le., AID converters, display drivers, EEPROMs).
4-24
::I:
tem could be used to interface to an instrument cluster and
various parts of the automobile. The diagram shows two
HPC16083 microcontrollers interconnected to other MICROWIRE peripherals. HPC16083 # 1 is set up as the master and initiates all data transfers. HPC16083 # 2 is set up
as a slave answering to the master.
MICROWIRE/PLUS Operation
The HPC16083 can enter the MICROWIRE/PLUS mode as
the master or a slave. A control bit in the IRCD register
determines whether the HPC16083 is the master or slave.
The shift clock is generated when the HPC16083 is configured as a master. An externally generated shift clock on the
SK pin is used when the HPC16083 is configured as a slave.
When the HPC16083 is a master, the DIVBY register programs the frequency of the SK clock. The DIVBY register
allows the SK clock frequency to be programmed in 15 selectable steps from 64 Hz to 1 MHz with CKI at 16.0 MHz.
The master microcontroller interfaces the operator with the
system and could also manage the instrument cluster in an
automotive application. Information is visually presented to
the operator by means of a VF display controlled by the
COP470 display driver. The data to be displayed is sent
serially to the COP470 over the MICROWIRE/PLUS link.
Data such as accumulated mileage could be stored and retrieved from the EEPROM COP494. The slave HPC16083
could be used as a fuel injection processor and generate
timing signals required to operate the fuel valves. The master processor could be used to periodically send updated
values to the slave via the MICROWIRE/PLUS link. To
speed up the response, chip select logic is implemented by
connecting an output from the master to the external interrupt input on the slave.
The contents of the SIO register may be accessed through
any of the memory access instructions. Data waiting to be
transmitted in the SIO register is clocked out on the falling
edge of the SK clock. Serial data on the SI pin is clocked in
on the rising edge of the SK clock.
MICROWIRE/PLUS Application
Figure 21 illustrates a MICROWIRE/PLUS arrangement for
an automotive application. The microcontroller-based sys-
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TL/DO/8801-27
FIGURE 21. MICROWIRE/PLUS Application
4-25
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HPC16083 UART
~--------------------------ROX
The HPC16083 contains a software programmable UART.
The UART (see Figure 22) consists of a transmit shift register, a receiver shift register and five addressable registers,
as follows: a transmit buffer register (TBUF), a receiver buffer register (RBUF), a UART control and status register
(ENU), a UART receive control and status register (ENUR)
and a UART interrupt and clock source register (ENUI). The
ENU register contains flags for transmit and receive functions; this register also determines the length of the data
frame (8 or 9 bits) and the value of the ninth bit in transmission. The ENUR register flags framing and data overrun errors while the UART is receiving. Other functions of the
ENUR register include saving the ninth bit received in the
data frame and enabling or disabling the UART's Wake-up
Mode of operation. The determination of an internal or external clock source is done by the ENUI register, as well as
selecting the number of stop bits and enabling or disabling
transmit and receive interrupts.
The baud rate clock for the Receiver and Transmitter can
be selected for either an internal or external source using
two bits in the ENUI register. The internal baud rate is programmed by the OIVBY register. The baud rate may be selected from a range of 8 Hz to 128 kHz in binary steps or T3
underflow. By selecting a 9.83 MHz crystal, all standard
baud rates from 75 baud to 38.4 kBaud can be generated.
The external baud clock source comes from the CKX pin.
The Transmitter and Receiver can be run at different rates
by selecting one to operate from the internal clock and the
other from an external source.
r-;::;;;;;~----I---+ TOX
D
A
T
A
I..---.CKX
The HPC16083 UART supports two data formats. The first
format for data transmission consists of one start bit, eight
data bits and one or two stop bits. The second data format
for transmission consists of one start bit, nine data bits, and
one or two stop bits. Receiving formats differ from transmission only in that the Receiver always requires only one stop
bit in a data frame.
UART Wake-up Mode
The HPC16083 UART features a Wake-up Mode of operation. This mode of operation enables the HPC16083 to be
networked with other processors. Typically in such environments, the messages consist of addresses and actual data.
Addresses are specified by having the ninth bit in the data
frame set to 1. Data in the message is specified by having
the ninth bit in the data frame reset to o.
The UART monitors the communication stream looking for
addresses. When the data word with the ninth bit set is
received, the UART signals the HPC16083 with an interrupt.
The processor then examines the content of the receiver
buffer to decide whether it has been addressed and whether
to accept subsequent data.
TLlDD/8801-28
FIGURE 22. UART Block Diagram
4-26
:x:
The host uses DMA to interface with the HPC16083. The
host initiates a data transfer by activating the HLD input of
the HPC16083. In response, the HPC16083 places its system bus in a TRI-STATE Mode, freeing it for use by the host.
The host waits for the acknowledge signal (HLDA) from the
HPC16083 indicating that the sytem bus is free. On receiving the acknowledge, the host can rapidly transfer data into,
or out of, the shared memory by using a conventional DMA
controller. Upon completion of the message transfer, the
host removes the HOLD request and the HPC16083 resumes normal operations.
FIGURE 24 illustrates an application of the shared memory
interface between the HPC16083 and a Series 32000 system.
Universal Peripheral Interface
The Universal Peripheral Interface (UPI) allows the
HPC16083 to be used as an intelligent peripheral to another
processor. The UPI could thus be used to tightly link two
HPC16083's and set up systems with very high data exchange rates. Another area of application could be where a
HPC16083 is programmed as an intelligent peripheral to a
host system such as the Series 32000® microprocessor.
FIGURE 23 illustrates how a HPC16083 could be used an
an intelligent peripherial for a Series 32000-based application.
The interface consists of a Data Bus (port A), a Read Strobe
(URD), a Write Strobe (UWR), a Read Ready Line (RDRDY),
a Write Ready Line (WRRDY) and one Address Input (UAO).
The data bus can be either eight or sixteen bits wide.
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Memory
The URD and UWR inputs may be used to interrupt the
HPC16083. The RDRDY and WRRDY outputs may be used
to interrupt the host processor.
The HPC16083 has been designed to offer flexibility in
memory usage. A total address space of 64 kbytes can be
addressed with 8 kbytes of ROM and 256 bytes of RAM
available on the chip itself. The ROM may contain program
instructions, constants or data. The ROM and RAM share
the same address space allowing instructions to be executed out of RAM.
Program memory addressing is accomplished by the 16-bit
program counter on a byte basis. Memory can be addressed
directly by instructions or indirectly through the B, X and SP
registers. Memory can be addressed as words or bytes.
Words are always addressed on even-byte boundaries. The
HPC16083 uses memory-mapped organization to support
registers, lID and on-chip peripheral functions.
The UPI contains an Input Buffer (IBUF), an Output Buffer
(OBUF) and a Control Register (UPIC). In the UPI mode,
port A on the HPC16083 is the data bus. UPI can only be
used if the HPC16083 is in the Single-Chip mode.
Shared Memory Support
Shared memory access provides a rapid technique to exchange data. It is effective when data is moved from a peripheral to memory or when data is moved between blocks
of memory. A related area where shared memory access
proves effective is in multiprocessing applications where
two CPUs share a common memory block. The HPC16083
supports shared memory access with two pins. The pins are
the ROY IHLD input pin and the HLDA output pin. The user
can software select either the Hold or Ready function by the
state of a control bit. The HLDA output is multiplexed onto
port B.
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kbytes and registers and lID are mapped as shown in Table
v.
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SERIES 32000
SYSTEM Wii
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• TCU
• ICU
• MEMORY
UWR
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TLIDD/8801-29
FIGURE 23. HPC16083 as a Peripheral: (UPllnterface to Series 32000 Application)
4-27
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Shared Memory Support
(Continued)
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Interrupt Vectors
JSRP Vectors
On-Chip ROM
USER MEMORY
0195:0194
Watchdog Address
0192
0191 :0190
018F:018E
0180:018C
018B:018A
0189:0188
0187:0186
0185:0184
0183:0182
0181:0180
TOCON Register
TMMOOE Register
DIVBY Register
T3 Timer
R3 Register
T2 Timer
R2 Register
12CR Register/ R1
13CR Register/ T1
14CR Register
015E:015F
015C
0153:0152
0151 :0150
014F:014E
0140:014C
014B:014A
0149:0148
0147:0146
0145:0144
0143:0142
0141:0140
EICR
EICON
Port P Register
PWMOOE Register
R7 Register
T7 Timer
R6 Register
T6 Timer
R5 Register
T5 Timer
R4 Register
T4 Timer
ENUR Register
TBUF Register
RBUF Register
ENUI Register
ENU Register
0104
Port D Input Register
00F5:00F4
00F3:00F2
00F1:00FO
External Expansion
Memory
On-Chip RAM
0128
0126
0124
0122
0120
00E6
USER RAM
Watchdog Logic
Timer Block TO:T3
UPIC Register
UPI CONTROL
Port B
PortA / OBUF
PORTSA&B
OODE
OOOO:OOOC
0008
0006
0004
0002
0000
Microcode ROM Dump
HALT Enable Register
Port I Input Register
SIO Register
IRCO Register
IRPO Register
ENIR Register
PORT CONTROL
& INTERRUPT
CONTROL
REGISTERS
OOCF:OOCE
OOCO:OOCC
OOCB:OOCA
OOC9:00C8
00C7:00C6
00C5:00C4
00C3:00C2
OOCO
X Register
B Register
K Register
A Register
PC Register
SP Register
(reserved)
PSW Register
HPCCORE
REGISTERS
On-Chip
RAM
USER RAM
:
:
0001:0000
4-28
PORTSA&B
CONTROL
OOE3:00E2
00E1:00EO
OOBF:OOBE
Timer Block T4:T7
BFUN Register
DIR B Register
OIR A Register / IBUF
UART
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Indirect
The instruction contains an 8-bit address field. The contents
of the WORD addressed points to the memory for the operand.
Indexed
The instruction contains an 8-bit address field and an 8- or
16-bit displacement field. The contents of the WORD addressed is added to the displacement to get the address of
the operand.
Immediate
The instruction contains an 8-bit or 16-bit immediate field
that is used as the operand.
Register Indirect (Auto Increment and Decrement)
The operand is the memory addressed by the X register.
This mode automatically increments or decrements the X
register (by 1 for bytes and by 2 for words).
Register Indirect (Auto Increment and Decrement) with
Conditional Skip
The operand is the memory addressed by the B register.
This mode automatically increments or decrements the B
register (by 1 for bytes and by 2 for words). The B register is
then compared with the K register. A skip condition is generated if B goes past K.
HPC16083 CPU
The HPC16083 CPU has a 16-bit ALU and six 16-bit registers
Arithmetic Logic Unit (ALU)
The ALU is 16 bits wide and can do 16-bit add, subtract and
shift or logic AND, OR and exclusive OR in one timing cycle.
The ALU can also output the carry bit to a 1-bit C register.
Accumulator (A) Register
The 16-bit A register is the source and destination register
for most I/O, arithmetic, logic and data memory access operations.
Address (B and X) Registers
The 16-bit B and X registers can be used for indirect addressing. They can automatically count up or down to sequence through data memory.
Boundary (K) Register
The 16-bit K register is used to set limits in repetitive loops
of code as register B sequences through data memory.
Stack Pointer (SP) Register
The 16-bit SP register is the pointer that addresses the
stack. The SP register is incremented by two for each push
or call and decremented by two for each pop or return. The
stack can be placed anywhere in user memory and be as
deep as the available memory permits.
Program (PC) Register
The 16-bit PC register addresses program memory.
ADDRESSING MODES-ACCUMULATOR AS
DESTINATION
Register Indirect
This is the "normal" mode of addressing for the HPC16083
(instructions are single-byte). The operand is the memory
addressed by the B register (or X register for some instructions).
Direct
The instruction contains an 8-bit or 16-bit address field that
directly points to the memory for the operand.
Double Register Indirect Using the B and X Registers
Used only with Reset, Set and IF bit instructions; a specific
bit within the 64 kbyte address range is addressed using the
B and X registers. The address of a byte of memory is
formed by adding the contents of the B register to the most
significant 13 bits of the X register. The specific bit to be
modified or tested within the byte of memory is selected
using the least significant 3 bits of register X.
HPC Instruction Set Description
I
Description
Action
ARITHMETIC INSTRUCTIONS
ADD
ADC
ADDS
DADC
SUBC
DSUBC
MULT
DIV
DIVD
Add
Add with carry
Add short imm8
Decimal add with carry
Subtract with carry
Decimal subtract w/carry
Multiply (unsigned)
Divide (unsigned)
Divide Double Word (unsigned)
MA+Meml ~ MA
carry~
carry~
MA+Meml+C ~ MA
MA+imm8~ MA
carry~
carry~
MA + Meml + C ~ MA (Decimal)
MA-Meml+C ~ MA
carry~
MA-Meml+C ~ MA (Decimal)
carry~
MA*Meml ~ MA&X,O ~ K,O~ C
MAiMeml ~ MA, rem. ~ X, 0 ~ K, 0 ~ C
(X & MA)/Meml ~ MA, rem ~ X, 0 ~ K, carry ~
IFEQ
IFGT
If equal
If greater than
Compare MA & Meml, Do next if equal
Compare MA & Meml, Do next if MA > Meml
AND
OR
XOR
Logical and
Logical or
Logical exclusive-or
MA and Meml ~ MA
MA or Meml ~ MA
MA xor Meml ~ MA
MEMORY MODIFY INSTRUCTIONS
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ADDRESSING MODES-DIRECT MEMORY AS
DESTINATION
Direct Memory to Direct Memory
The instruction contains two 8- or 16-bit address fields. One
field directly points to the source operand and the other field
directly points to the destination operand.
Immediate to Direct Memory
The instruction contains an 8- or 16-bit address field and an
8- or 16-bit immediate field. The immediate field is the operand and the direct field is the destination.
Addressing Modes
Mnemonic
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Mem + 1 ~ Mem
Mem -1 ~ Mem, Skip next if Mem = 0
Increment
Decrement, skip if 0
4-29
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SBIT
RBIT
IFBIT
Action
Set bit
Reset bit
If bit
1 --+ Mem.bit
o --+ Mem.bit
If Mem.bit is true, do next instr.
MEMORY TRANSFER INSTRUCTIONS
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PUSH
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Description
XS
Load
Load, incr/decr X
Store to Memory
Exchange
Exchange, incr/decr X
Push Memory to Stack
Pop Stack to Memory
Meml--+ MA
Mem(X) --+ A, X ± 1 (or 2) --+ X
A--+ Mem
A+-+Mem
A +-+ Mem(X), X ± 1 (or 2) --+ X
W --+ W(SP), SP + 2 --+ SP
SP-2 --+ SP, W(SP) --+ W
Load A, incr/decr B,
Skip on condition
Exchange, incr/decr B,
Skip on condition
Mem(B) --+ A, B ± 1 (or 2) --+ B,
Skip next if B greater/less than K
Mem(B) +-+ A,B ± 1 (or 2) --+ B,
Skip next if B greater/less than K
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REGISTER LOAD IMMEDIATE INSTRUCTIONS
LOB
LOK
LOX
LOBK
Load
Load
Load
Load
imm--+
imm--+
imm --+
imm --+
B immediate
K immediate
X immediate
Band K immediate
ACCUMULATOR AND C INSTRUCTIONS
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X
B,imm --+ K
CLRA
INCA
OECA
COMPA
SWAP A
RRCA
RLCA
SHRA
SHLA
SC
RC
IFC
IFNC
O--+A
A+1--+A
A-1--+A
1's complement of A --+ A
A15:12 +- A11:8 +- A7:4 +-+ A3:0
C --+ A15 --+ ... --+ AO --+ C
C +- A 15 +- ... +- AO +- C
0--+ A15 --+ ... --+ AO --+ C
C +- A 15 +- ... +- AO +- 0
1--+C
O--+C
Do next if C = 1
Do next if C = 0
Clear A
IncrementA
Decrement A
Complement A
Swap nibbles of A
Rotate A right thru C
Rotate A left thru C
Shift A right
Shift A left
SetC
ResetC
IFC
IF notC
TRANSFER OF CONTROL INSTRUCTIONS
JSRP
Jump subroutine from table
JSR
Jump subroutine relative
JSRL
JP
JMP
JMPL
JIO
JIOW
NOP
RET
RETSK
RETI
Jump subroutine long
Jump relative short
Jump relative
Jump relative long
Jump indirect at PC + A
PC --+ W(SP),SP + 2 --+ SP
W(table#) --+ PC
PC --+ W(SP),SP+ 2 --+ SP,PC+ # --+ PC
(#is + 1025 to -1023)
PC --+ W(SP),SP+2 --+ SP,PC+ # --+ PC
PC+ # --+ PC(# is +32to -31)
PC+ # --+ PC(#is +257 to -255)
PC+ # --+ PC
PC+A+1 --+ PC
then Mem(PC) + PC --+ PC
PC + 1 --+ PC
SP-2 --+ SP,W(SP) --+ PC
SP-2 --+ SP,W(SP) --+ PC, & skip
SP-2 --+ SP,W(SP) --+ PC, interrupt re-enabled
No Operation
Return
Return then skip next
Return from interrupt
Note: W is 16·bit word of memory
MA is Accumulator A or direct memory (8 or 16·bit)
Mem is 8-bit byte or 16-bit word of memory
Meml is 8- or 16-bit memory or 8 or 16-bit immediate data
imm is 8-bit or 16-bit immediate data
imm8 is 8-bit immediate data only
4-30
::J:
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Memory Usage
o
Number Of Bytes For Each Instruction (number in parenthesis is 16-Bit field)
o
CX)
Using Accumulator A
Direct
Indlr.
Index
Immed.
.
1
1
1
2(4)
2(4)
2(4)
3
3
3
4(5)
4(5)
4(5)
2(3)
3(5)
2
3(4)
3
4(5)
4(5)
2
4(5)
4(5)
4(5)
2(3)
2(3)
2(3)
Reg Indlr.
(B)
(X)
LD
X
ST
1
1
1
ADC
ADDS
SBC
DADC
DSBC
ADD
MULT
DIV
DIVD
1
IFEQ
IFGT
AND
OR
XOR
eN
To Direct Memory
-
-
-
-
-
1
1
1
1
1
1
1
2
2
2
2
2
2
2
3(4)
3(4)
3(4)
3(4)
3(4)
3(4)
3(4)
3
3
3
3
3
3
3
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
1
1
1
1
1
2
2
2
2
2
3(4)
3(4)
3(4)
3(4)
3(4)
3
3
3
3
3
4(5)
4(5)
4(5)
4(5)
4(5)
-
Direct
-
..
.
5(6)
3(4)
-
-
4(5)
5(6)
Immed.
..
5(6)
-
-
-
4(5)
5(6)
-
-
-
-
-
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
2(3)
2(3)
2(3)
2(3)
2(3)
4(5)
4(5)
4(5)
4(5)
4(5)
5(6)
5(6)
5(6)
5(6)
5(6)
4(5)
4(5)
4(5)
4(5)
4(5)
5(6)
5(6)
5(6)
5(6)
5(6)
* B-bit direct address
* *16-bit direct address
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CX)
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CX)
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en
o
CX)
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o
o
eN
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en
Instructions that modify memory directly
Immediate Load Instructions
(B)
(X)
Direct
Indlr
Index
B&X
SBIT
RBIT
IFBIT
1
1
1
2
2
2
3(4)
3(4)
3(4)
3
3
3
4(5)
4(5)
4(5)
1
1
1
DECSZ
INC
3
3
2
2
2(4)
2(4)
3
3
4(5)
4(5)
Immed.
LD B,·
LOX,·
LD K,·
2(3)
2(3)
2(3)
LDBK,·,·
3(5)
o
o
eN
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en
o
o
eN
Register Indirect Instructions with
Auto Increment and Decrement
LOS A,·
XSA,·
(B-)
1
1
1
1
Instructions Using A and C
CLR
INC
DEC
COMP
SWAP
RRC
RLC
SHR
SHL
SC
RC
IFC
IFNC
Register X
LOA,·
XA,·
(X+)
(X-)
1
1
1
1
o
~
en
o
Register B With Skip
(B+)
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A
A
A
A
A
1
1
1
1
1
1
1
1
1
1
1
1
1
A
A
A
A
Stack Reference Instructions
Direct
I
PUSH
POP
2
2
4-31
Transfer of Control Instructions
JSRP
JSR
JSRL
JP
JMP
JMPL
JID
JIDW
NOP
RET
RETSK
RETI
1
2
3
1
2
3
1
1
1
1
1
1
o
eN
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o
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CD
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......
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o
CD
C")
o
Code Efficiency
One of the most important criteria of a single chip microcontroller is code efficiency. The more efficient the code, the
more features that can be put on a chip. The memory size
on a chip is fixed so if code is not effiCient, features may
have to be sacrificed or the programmer may have to buy a
larger, more expensive version of the chip.
MULTIFUNCTION INSTRUCTIONS FOR DATA MOVE·
MENT AND PROGRAM LOOPING
The HPC16083 has single-byte instructions that perform
multiple tasks. For example, the XS instruction will do the
following:
1. Exchange A and memory pointed to by the B register
oD.
The HPC16083 has been designed to be extremely codeefficient. The HPC16083 looks very good in all the standard
coding benchmarks; however, it is not realistic to rely only
on benchmarks. Many large jobs have been programmed
onto the HPC16083, and the code savings over other popular microcontrollers has been considerable.
Reasons for this saving of code include the following:
......
C")
o
o
CD
......
SINGLE BYTE INSTRUCTIONS
BIT MANIPULATION INSTRUCTIONS
The majority of instructions on the HPC16083 are singlebyte. There are two especially code-saving instructions:
Any bit of memory, 1/0 or registers can be set, reset or
tested by the single byte bit instructions. The bits can be
addressed directly or indirectly. Since all registers and 1/0
are mapped into the memory, it is very easy to manipulate
specific bits to do efficient control.
D.
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CD
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2. Increment or decrement the B register
3. Compare the B register to the K register
4. Generate a conditional skip if B has passed K
The value of this multipurpose instruction becomes evident
when looping through sequential areas of memory and exiting when the loop is finished.
JP is a 1-byte jump. True, it can only jump within arange of
plus or minus 32, but many loops and decisions are often
within a small range of program memory. Most other micros
need 2-byte instructions for any short jumps.
DECIMAL ADD AND SUBTRACT
JSRP is a 1-byte call subroutine. The user makes a table of
his 16 most frequently called subroutines and these calls
will only take one byte. Most other micros require two and
even three bytes to call a subroutine. The user does not
have to decide which subroutine addresses to put into his
table; the assembler can give him this information.
This instruction is needed to interface with the decimal user
world.
It can handle both 16-bit words and 8-bit bytes.
The 16-bit capability saves code since many variables can
be stored as one piece of data and the programmer does
not have to break his data into two bytes. Many applications
store most data in 4-digit variables. The HPC16083 supplies
8-bit byte capability for 2-digit variables and literal variables.
EFFICIENT SUBROUTINE CALLS
The 2-byte JSR instructions can call any subroutine within
plus or minus 1k of program memory.
MULTIPLY AND DIVIDE INSTRUCTIONS
The HPC16083 has 16-bit multiply, 16-bit by 16-bit divide,
and 32-bit by 16-bit divide instructions. This saves both
code and time. Multiply and divide can use immediate data
or data from memory. The ability to multiply and divide by
immediate data saves code since this function is often
needed for scaling, base conversion, computing indexes of
arrays, etc.
co
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CD
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4-32
::I:
"'1J
Development Support
o
--
MOLE DEVELOPMENT SYSTEM
INFORMATION SYSTEM
The MOLE (Microcomputer On Line Emulator) is a low cost
development system and emulator for all microcontroller
products. These include COPs and the HPC family of products. The MOLE consists of a BRAIN Board, Personality
Board and optional host software.
The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION mode
that can be used to search out and retrieve application data
about NSC Microcontrollers. The user needs as a minimum,
a Dumb terminal, 300 or 1200 baud Modem, and a telephone.
The purpose of the MOLE is to provide the user with a tool
to write and assemble code, emulate code for the target
micro controller and assist in both software and hardware
debugging of the system.
It is a self contained computer with its own firmware which
provides for all system operation, emulation control, communication, PROM programming and diagnostic operations.
If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk for
later use.
It contains three serial ports to optionally connect to a terminal, a host system, a printer or a modem, or to connect to
other MOLEs in a multi-MOLE environment.
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<:)
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W
.....
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<:)
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W
.....
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W
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Q)
W
.....
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.a:::a.
Order PIN: MOLE-DIAL-A-HLP
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Information system package contains:
DIAL-A-HELPER Users Manual
Public Domain Communications Software
MOLE can be used in either a stand alone mode or in conjunction with a selected host system using PC-DOS communicating via a RS-232 port.
W
.....
::I:
"'1J
HOW TO ORDER
o
FACTORY APPLICATIONS SUPPORT
To order a complete development package, select the section for the microcontroller to be developed and order the
parts listed.
Dial-A-Helper also provides immediate factory applications
support. If a user is having difficulty in getting a MOLE to
operate in a particular mode or something peculiar is occurring, he can contact us via his system and modem. He can
leave messages on our electronic bulletin board, which we
will respond to, or he can arrange for us to actually take
control of his system via modem for debugging purposes.
DIAL-A-HELPER
Dial-A-Helper is a service provided by the MOLE (Microcontroller On Line Emulator) applications group. It consists of
both an electronic bulletin board information system and a
method by which applications can take control of a MOLE
Development System at a remote site via modem in order to
resolve any problems.
The applications group can then cause his system to execute various commands and try to resolve the customers
problem by actually getting customers system to respond.
Both parties see exactly what is occurring, as it is happening.
This allows us to respond in minutes when applications help
is needed.
--
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.....
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.....
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Development Tools Selection Table
Microcontrolier
Order
Part Number
Description
Includes
Manual
Number
MOLE-BRAIN
Brain Board
Brain Board Users Manual
420408188-001
MOLE-HPC-PB1
Personality Board
HPC Personality Board
Users Manual
420410477 -001
MOLE-HPC-IBMR
Assembler Software for IBM
HPC Software Users Manual
and Software Disk
PC-DOS Communications
Software Users Manual
424410836-001
HPC
MOLE-HPC-IBM-CR
C Compiler for IBM
424410897-001
Users Manual
HPC C Compiler Users Manual
and Software Disk
Assembler Software for IBM
MOLE-HPC-IBM
420040416-001
4244105883001
424410897 -001
4-33
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.a:::a.
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CD
'11:1'
Development Support
(Continued)
o
D..
Voice:
:I:
.......
Modem: (408) 739-1162
o
o
Set-Up:
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(408) 721-5582
Baud: 300 or 1200 Baud
o
Length: 8-bit
Parity:
None
Stop Bit: 1
:I:
.......
Operation: 24 hrs, 7 days
o
o
DIAL·A·HELPER
CD
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D..
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CD
------------------------.
N
oD..
:I:
.......
USER'S
TARGET
SYSTEt.l
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CD
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D..
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.......
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'11:1'
HOST
COt.lPUTER
t.lOLE
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.......
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._----------------------USER SITE
NATIONAL SEt.lICONDUCTOR SITE
CD
TL/OO/BBOl-32
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.......
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CD
N
oD..
Part Selection
The HPC family includes devices with many different options and configurations to meet various application needs. The number
HPC16083 has been generically used throughout this datasheet to represent the whole family of parts. The following chart
explains how to order various options available when ordering HPC family members.
Note: All options may not currently be available.
HPC16083XXX/E 17
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.......
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..-
[
oD..
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17 = 17 MHz
30 = 30 MHz
Package Type
E = leadless Chip Carrier (lCC)
U = Pin Grid Array (PGA)
V = Plastic leaded Chip Carrier (PlCC)
l = leaded Ceramic Chip Carrier (lDCC)
T = Tape Pak
ROM Information
XXXI = custom masked ROM pattern
no designator = ROMless
ROM Size
a = ak byte ROM
o = ROMless device
Temperature
4 = Commercial (O·C to + 70·C)
3 = Industrial ( - 40·C to + as·C)
2 = Automotive ( - 40·C to + 10S·C)
1 = Military (- 55·C to + 125·C)
TL/OO/BBOl-31
FIGURE 8. HPC Family Part Numbering Scheme
Examples
HPC46003E17
-
ROMless, Commercial temp. (O°C to 70°C), LCC
HPC16083XXX/U17- 8k masked ROM, Military temp. (-55°C to
+ 125°C),
HPC26083XXX1V17- 8k masked ROM, Automotive temp. (-40·C to
4-34
PGA
+ 105°C), PLCC
:J:
~National
ADVANCE
'INFORMATION
~ Semiconductor
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~
.......
:J:
HPC16164/HPC26164/HPC36164/HPC46164
HPC16104/HPC26104/HPC36104/HPC46104
High-Performance microControliers with AID
General Description
The HPC16164 and HPC16104 are members of the HPCTM
family of High Performance microControllers. Each member
of the family has the same core CPU with a unique memory
and I/O configuration to suit specific applications. The
HPC16164 has 16k bytes of on-chip ROM. The HPC16104
has no on-chip ROM and is intended for use with external
memory. Each part is fabricated in National's advanced
microCMOS technology. This process combined with an advanced architecture provides fast, flexible I/O control, efficient data manipulation, and high speed computation.
The HPC devices are complete microcomputers on a single
chip. All system timing, internal logic, ROM, RAM, and I/O
are provided on the chip to produce a cost effective solution
for high performance applications. On-chip functions such
as UART, up to eight 16-bit timers with 4 input capture registers, vectored interrupts, WATCHDOG logic and MICROWIRE/PLUSTM provide a high level of system integration.
The ability to address up to 64k bytes of external memory
enables the HPC to be used in powerful applications typically performed by microprocessors and expensive peripheral
chips. The term "HPC16164" is used throughout this datasheet to refer to the HPC16164 and HPC16104 devices unless otherwise specified.
The HPC16164 has, as an on-board peripheral, an 8-channel 8-bit Analog-to-Digital Converter. This A/D converter
can operate in single-ended mode where the analog input
voltage is applied across one of the eight input channels
(00-07) and AGND. The AID converter can also operate in
"lJ
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en
.....
en
differential mode where the analog input voltage is applied
across two adjacent input channels. The AID converter will
convert up to eight channels in single-ended mode and up
to four channel pairs in differential mode.
The microCMOS process results in very low current drain
and enables the user to select the optimum speed/power
product for his system. The IDLE and HALT modes provide
further current savings. The HPC is available in 68-pin
PLCC, LCC, LDCC, PGA and TapePakTM packages.
Features
• HPC family-core features:
- 16-bit architecture, both byte and word
- 16-bit data bus, ALU, and registers
- 64k bytes of external memory addressing
- FAST-200 ns for fastest instruction when using
20.0 MHz clock
- High code efficiency-most instructions are single
byte
- 16 x 16 multiply and 32 x 16 divide
- Eight vectored interrupt sources
- Four 16-bit timer/counters with 4 synchronous outputs and WATCHDOG logic
- MICROWIRE/PLUS serial I/O interface
- CMOS-very low power with two power save modes:
IDLE and HALT
• AlD-8-channel 8-bit analog-to-digital converter with
conversion time minimum 6.6 J.Ls for single conversion
• AID-supports conversions in "quiet mode"
~
.......
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~
.......
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~
~
.......
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.....
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.......
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.......
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~
.......
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.....
~
Block Diagram
(HPC16164 with 16k ROM shown)
o
r-----------------------,
ROy/HTIiRESETSTATUS
~
CKICKOCK2
, 't t
1____________________
3~~~~
TlIDD/9682-1
4-35
~
o......
CD
~
o
Features
(Continued)
CD
• UART-full duplex, programmable baud rate
• Four additional 16-bit timer I counters with pulse width
modulated outputs
• Four input capture registers
• 52 general purpose I/O lines (memory mapped)
oD.
Absolute Maximum Ratings
D.
:J:
.......
~
o
......
• 16k bytes of ROM, 512 bytes of RAM on-chip
• ROMless version available (HPC16104)
• Commercial (O'C to + 70·C), industrial (-40·C to
+ 85·C), automotive (- 40·C to + 105·C) and military
( - 55·C to + 125·C) temperature ranges
C")
:J:
.......
~
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......
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N
If MilitaryI Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications•
oD.
Total Allowable Source or Sink Current
.......
Lead Temperature (Soldering, 10 sec.)
:J:
Storage Temperature Range
All Other Pins
oD.
:J:
.......
~
CD
......
CD
~
o
~
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
300·C
DC Electrical Characteristics Vee = 5.0V ±10% unless otherwise specified. TA
HPC46164/HPC46104. -40°C to +85°C for HPC36164/HPC361 04. -40°C to +105°C for
HPC26164/HPC26104. -55°C to + 125°C for HPC16164/HPC.~6104
Symbol
Parameter
lee1
Supply Current
lee2
IDLE Mode Current
CD
......
Test Conditions
oD.
lee3
HALT Mode Current
:J:
.......
~
=
O·Cta +70°Cfor
Max
Units
Vee
=
5.5V, fin
=
20.0 MHz (Note 1)
60
rnA
Vee
=
5.5V, fin
=
2.0 MHz (Note 1)
6
rnA
Vee
=
5.5V, fin
=
20.0 MHz, (Note 1)
6
rnA
Vee
=
5.5V, fin
=
2.0 MHz, (Note 1)
0.6
rnA
Vee
=
5.5V, fin
=
0 kHz. (Note 1)
300
IJ-A
Vee
=
2.5V, fin
=
0 kHz, (Note 1)
150
IJ-A
CD
C")
2000V
Note: Absolute maximum ratings indicate limits beyond
- 65·C to + 150·C
D.
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.......
(Vee + 0.5)V to (GND - 0.5)V
ESD Rating
100mA
~
o
......
CD
......
-0.5V to 7.0V
Vee with Respect to GND
Min
INPUT VOLTAGE LEVELS RESET. NMI, CKI AND WO (SCHMITT TRIGGERED)
CD
......
VIH1
Logic High
o
VIL1
Logic Low
CD
N
V
0.9 Vee
0.1 Vee
V
D.
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.......
~
CD
......
CD
......
VIH2
Logic High
VIL2
Logic Low
D.
III
Input Leakage Current
o
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V
0.7 Vee
0.2 Vee
V
±1
IJ-A
CI
Input Capacitance
(Note 2)
10
pF
CIO
I/O Capacitance
(Note 2)
20
pF
0.1
V
OUTPUT VOLTAGE LEVELS
VOH1
Logic High (CMOS)
10H
=
-10 p.A
VOL1
Logic Low (CMOS)
10H
=
10 IJ-A
VOH2
Port Al8 Drive, CK2
10H
=
-7 rnA. Vee
VOL2
(Ao-A15. 810, 811, 812, 815)
10L
VOH3
10H
= 3 rnA
= -1.6 rnA, Vee =
VOL3
Other Port Pin Drive, WO (open
drain) (80-8g, 813. 814, PO-P3)
10L
=
0.5 mA
VOH4
ST1 and ST2 Drive
10H
=
-6 rnA. Vee
10L
=
VOL4
VRAM
RAM Keep-Alive Voltage
loz
TRI-STATE® Leakage Current
=
5.0V
2.4
V
0.4
5.0V
0.4
=
5.0V
2.4
2.5
Note 2: This is guaranteed by design and not tested.
Note 3: Test duration is 100 ms.
4-36
V
V
0.4
V
Vee
V
±5
Note 1: ICC1' ICC2' ICC3 measured with no external drive (IOH and IOL = 0, IIH and IlL = 0). ICC1 is measured with RESET = Vss.
VCC and AID inactive. CKI driven to VIH1 and VIL1 with rise and fall times less than 10 nSf
V
V
2.4
1.6mA
(Note 3)
V
Vee - 0.1
IJ-A
ICC3 is measured with NMI =
:x
"'D
o-.a.
AC Electrical Characteristics Vcc =
5.0V ±10% unless otherwise specified, TA = O°Cto +70°Cfor
HPC46164/HPC46104, -40°C to + 85°C for HPC36164/HPC361 04, -40°C to + 105°C for
HPC26164/HPC26104, -55°C to + 125°C for HPC16164/HPC16104
Symbol
Parameter
Min
Max
Units
2
20
MHz
fc = CKI freq.
Operating Frequency
tC1 = 1/fc
Clock Period
50
ns
tc = 2/fc
Timing Cycle
100
ns
tLL = %tc - 9
ALE Pulse Width
41
ns
tOC1C2A
Delay from CKI Falling
Edge to CK2 Rising Edge
0
55
ns
tOC1C2F
Delay from CKI Falling
Edge to CK2 Falling Edge
0
55
ns
tOC1ALEA
(Notes 1, 2)
Delay from CKI Rising
Edge to ALE Rising Edge
0
35
ns
tOC1ALEF
(Notes 1, 2)
Delay from CKI Rising
Edge to ALE Falling Edge
0
35
ns
en
-.a.
en
0l:Io
.......
:x
"'D
o
~
en
-.a.
en
0l:Io
.......
:x
"'D
oW
en
-.a.
en
0l:Io
.......
:x
"'D
o
0l:Io
en
-.a.
en
0l:Io
.......
tOC2ALEA =
(Note 2)
Y4 tC +
20
Delay from CK2 Rising
Edge to ALE Rising Edge
55
ns
tOC2ALEF =
(Note 2)
Y4 tC +
20
Delay from CK2 Falling
Edge to ALE Falling Edge
55
ns
tST=%tc- 7
Address Valid to ALE Falling Edge
18
ns
tvp = %tc - 5
Address Hold from ALE Falling Edge
20
ns
tWAIT = tc = WS
Wait State Period
100
fXIN = fc /19
External Timer Input Frequency
1.052
40
:x
"'D
o
-.a.
en
-.a.
o
0l:Io
.......
ns
:x
"'D
o
~
MHz
o
tXIN
Pulse Width for Timer Inputs
fMW
External MICROWIRE/PLUS
Clock Input Frequency
1.25
MHz
fu = fc /8
External UART Clock Input Frequency
2.5
MHz
ns
en
-.a.
0l:Io
.......
:x
"'D
o
W
en
-.a.
o
0l:Io
.......
Read Cycle Timing
Symbol
Units
:x
"'D
o
0l:Io
20
ns
o
140
ns
with One Wait State
Parameter
Min
tAAA = %tc - 5
ALE Falling Edge to RD Falling Edge
tRW = % tc + WS - 10
RD Pulse Width
tOA = %tc - 15
Data Hold after Rising Edge of RD
tACC = tc + WS - 55
Address Valid to Input Data Valid
145
ns
tAO = % tc + WS - 65
RD Falling Edge to Input Data Valid
85
ns
tAOA = tc - 5
RD Rising Edge to Address Valid
Write Cycle Timing
Symbol
0
Max
60
95
ns
ns
with One Wait State
Parameter
Min
tAAW = %tc - 5
ALE Falling Edge to WR Falling Edge
45
Max
ns
tww = % tc + WS - 15
WR Pulse Width
160
ns
tHW = %tc - 5
Data Hold after Rising Edge of WR
20
ns
Units
135
Data Valid before Rising Edge of WR
ns
tv = % tc + WS - 15
Bus Output (Port A) CL = 100 pF, CK2 Output CL = 50 pF, other Outputs CL = 80 pF. AC parameters are tested using DC Characteristics Inputs and non
CMOS Outputs. Measurement of AC Specifications is done with external clock driving CKI with 50% duty cycle. The capacitive load on CKO must be kept below
15 pF or AC measurement will be skewed.
Note 1: Do not design with this parameter unless CKI is driven with an active signal. When using a passive crystal circuit, CKI or CKO should not be connected to
any external logic since any load (besides the passive components in the crystal circuit) will affect the stability of the crystal unpredictably.
Note 2: These are not tested parameters. Therefore the given min/max value cannot be guaranteed. It is, however, derived from measured parameters, and may
be used for system design with a very high confidence level.
Note:
4-37
en
-.a.
0l:Io
Ready/Hold Timing
Symbol
tDAR =
% tc + WS
Parameter
3/4
tc
Max
Units
75
ns
RDY Pulse Width
100
ns
+ 40
Falling Edge of HLD
to Rising Edge of ALE
115
ns
110
ns
tRWP = tc
tSALE =
Min
Falling Edge of ALE
to Falling Edge of RDY
- 50
tHWP = tc
+
10
HLD Pulse Width
tHAD =
7/4
tc
+ 50
Rising Edge on HLD to
Rising Edge on HLDA
225
ns
tHAE = tc
+
100
Falling Edge on HLD to
Falling Edge on HLDA
200·
ns
Bus Float before
Falling Edge on HLDA
tSF
tSE =
% tc +
ns
0
Bus Enable from
Rising Edge of HLD
50
'Note: tHAE may be as long as (3tc + 4ws + 72tc
tHAE maximum value is for the optimal case.
+
125
ns
90) depending on which instruction is being executed, the addressing mode and number of wait states.
UPI Read/Write Timing
Symbol
Parameter
Min
Max
Units
tUAS
Address Setup Time to
Falling Edge of URD
10
ns
tUAH
Address Hold Time from
Rising Edge of URD
10
ns
tRPW
URD Pulse Width
100
ns
tOE
URD Falling Edge to
Output Data Valid
0
60
ns
tOD
Rising Edge of URD to
Output Data Valid
5
35
ns
tDRDY
RDRDY Delay from Rising
Edge of URD
70
ns
tWDW
UWR Pulse Width
40
ns
tUDS
Input Data Valid before
Rising Edge of UWR
10
ns
tUDH
Input Data Hold after
Rising Edge of UWR
15
ns
tA
WRRDY Delay from Rising
Edge of UWR
Note: Bus Output (Port A) CL
=
100 pF, CK2 Output CL
=
70
50 F, other Outputs CL
4-38
= 80 pF.
ns
::I:
AID Converter Specifications Vcc =
Symbol
5V
"'C
Max
Units
o
......
0')
......
8
bits
.....
± 10%
Parameter
Min
Resolution
fCCLK
Clock Frequency (Note 4)
0.1
tCON = 10.5/fCCLK
Conversion Time (Note 3)
6.6
VREF
Reference Voltage Input (AGND = OV)
3.0
1.6
IJ-s
VCC
V
±%
LSB
Total Unadjusted Error (Note 1)
(VREF = 5.000V)
RVREF
Reference Input Resistance
MHz
1.6
DC Common Mode Error
0')
~
::I:
"'C
oN
0')
......
0')
~
4.8
kn
±%
LSB
.....
::I:
"'C
o
Co)
0')
......
0')
~
.......
Power Supply Sensitivity
(VCC = VREF = 5V ± 10%)
±%
LSB
Voltage Reference Tolerance (VREF)
TBD
LSB
25
pF
+ 0.05
V
Analog Input Capacitance
Analog Input Voltage Range (Note 2)
Vss - 0.05
VCC
1
IJ-A
Off Channel Leakage
1
IJ-A
~
0')
......
0')
.....
::I:
"'C
o......
0')
......
o
Note 1: Total unadjusted error includes offset, full-scale, and multiplexer errors.
Note 3: Conversion time does not include sample/hold time.
"'C
o
~
On Channel Leakage
Note 2: 8 single-ended or 4 differential channels. Inherent sample and hold for single-ended inputs (Vss
:I:
= Pin 62).
~
.....
::I:
"'C
oN
Note 4: Clock supplied to AID converter is derived from CKI.
0')
......
o
~
.....
:I:
"'C
o
Co)
0')
......
o
~
.......
::I:
"'C
o
~
0')
......
o
~
•
4-39
"'II:t
Q
.....
CD
"'II:t
Timing Waveforms
oD.
CKI, CK2, ALE Timing Diagram
:::E:
......
"'II:t
Q
.....
CKI
CD
Cf)
o
D.
CK2
:::E:
......
"'II:t
Q
.....
CD
N
o
ALE
D.
:::E:
t
------+.....,,1
......
"'II:t
Q
.....
CD
.....
oD.
OC2ALEF
I---;--I''-_____________
tOC1ALEf
TL/DD/9682-2
ALE
:::E:
......
"'II:t
CD
.....
CD
PORTA---~
"'II:t
o
DATA OUT VALID
AODR OUT
--------4----~r_----------I-----------~I~--------
D.
:::E:
......
"'II:t
CD
.....
CD
Cf)
o
D.
TLIDD/9682-3
:::E:
......
FIGURE 1. Write Cycle
"'II:t
CD
.....
CD
N
o
D.
ALE
:::E:
......
"'II:t
CD
.....
CD
.....
o
D.
:::E:
PORTA
____________
I
AODR OUT
I------I---IACC--------.J:
,r------~D----~
iiii
~::::::::::-;~:W::::::::::~~I----"'DA----I
TL/DD/9682-4
FIGURE 2. Read Cycle
AlE
(
1/0-------00(
ADO.
)
nt·STATE
\
ROY
~IU.--I--TLIDD/9682-5
FIGURE 3. Ready Mode Timing
4-40
Timing Waveforms
(Continued)
ALE
j--ISAU---j
Hlo
1 .._________
~I____ hwr _ _ _ _- I - - - -1-1U-
~I
/:~----------------------------
-------'
:\\".
I
_ _-::
\
----------,,,
~
YRI·STATE
J).--------+--...;.;;;;.;.;,;;;--------------"'1~1
VALID
PORTA
Ilf
I
1--------- taF---------i
TL/OO/9682-6
FIGURE 4. Hold Mode Timing
UAO
~
11
r-...~f4---IRPW'----I
"'"
TRI·STATE
PORTA
F'
-----------"'4'_ _
~~~~ _
TRI·STATE
,
--..;,;,;;..;;.;,;;,;,;;.....-----...,;,,;,,;;,-----I_-Io-E-1--c~
....
DATA OUT
VAUD
}--
~
~=LP__-F-:-r-TL/OO/9682-9
FIGURE 5. UPI Read Timing
C-;]II"~~"'_I
-1(
PORT A _ _ _ _ _ _ _ _ _....,;Tliii
Rlioii
·Sliii
TA;;,;TE_ _ _ _
WRRDY _
_
O::~~N )~--------------
I
;------'I-·
HPC RD (I NT)
~_
V-
TL/OO/9682-10
FIGURE 6. UPI Write Timing
4-41
"'lIt'
o
,...
U)
"'lIt'
(.)
D.
:::t:
......
"'lIt'
o,...
U)
Cot)
(.)
D.
:::t:
......
"'lIt'
o
,...
Pin Descriptions
The HPC16164 is available in 68-pin PLCC, LCC, LDCC,
PGA, and TapePak packages.
I/O PORTS
Port A is a 16-bit bidirectional I/O port with a data direction
register to enable each separate pin to be individually defined as an input or output. When accessing external memory, port A is used as the multiplexed address/data bus.
D.
Port 8 is a 16-bit port with 12 bits of bidirectional I/O similar
in structure to Port A. Pins 810, 811, 812 and 815 are general purpose outputs only in this mode. Port 8 may also be
configured via a 16-bit function register 8FUN to individually
allow each pin to have an alternate function.
......
80:
o
,...
U)
,...
81:
(.)
U)
N
(.)
:::t:
"'lIt'
CKI
The Chip System Clock Input
82:
CKX
UART Clock (Input or Output)
CKO
The Chip System Clock Output (inversion of
CKI)
T210
Timer2 I/O Pin
T310
Timer3 I/O Pin
"'lIt'
85:
SO
MICROWIRE/PLUS Output
,...
Ground for Output 8uffers
Vcc pins on the chip. GND and
Vcc pins and both ground pins
Note: There are two electrically connected
DGND are electrically isolated. Both
must be used.
CLOCK PINS
84:
U)
DGND
Positive Power Supply (3V to 5.5V)
Ground for On-Chip Logic
UART Data Output
83:
......
POWER SUPPLY PINS
VCC1 and
VCC2
GND
TDX
:::t:
D.
Port P is a 4-bit output port that can be used as general
purpose data, or selected to be controlled by timers 4
through 7 in order to generate frequency, duty cycle and
pulse width modulated outputs.
Pins CKI and CKO are usually connected across an external
crystal.
CK2
Clock Output (CKI divided by 2)
86:
SK
MICROWIRE/PLUS Clock (Input or Output)
"'lIt'
87:
HLDA
Hold Acknowledge Output
OTHER PINS
D.
88:
TSO
Timer Synchronous Output
WO
89:
TS1
Timer Synchronous Output
This is an active low open drain output that
signals an illegal situation has been detected
by the Watch Dog logic .
ST1
8us Cycle Status Output: indicates first opcode fetch.
ST2
8us Cycle Status Output: indicates machine
states (skip, interrupt and first instruction cycle).
RESET
is an active low input that forces the chip to
restart and sets the ports in a TRI-STATE®
mode.
ROY /HLD
has two uses, selected by a software bit. It's
either a READY input to extend the bus cycle
for slower memories, or a HOLD request input
to put the bus in a high impedance state for
DMA purposes.
U)
(.)
:::t:
......
"'lIt'
,...
U)
U)
Cot)
810: UAO
Address 0 Input for UPI Mode
811: WRRDY Write Ready Output for UPI Mode
(.)
812:
D.
813: TS2
Timer Synchronous Output
:::t:
......
814: TS3
Timer Synchronous Output
U)
,...
815: RDRDY
Read Ready Output for UPI Mode
U)
When accessing external memory, four bits of port 8 are
used as follows:
"'lIt'
N
(.)
D.
:::t:
......
"'lIt'
U)
,...
U)
,...
(.)
D.
:::t:
810: ALE
Address Latch Enable Output
811: WR
Write Output
812: H8E
High 8yte Enable Output/Input
(sampled at reset)
815: RD
Read Output
VREF
AID converter reference voltage input.
Port I is an 8-bit input port that can be read as general
purpose inputs and is also used for the following functions:
EXM
External memory enable (active high) disables
internal ROM and maps it to external memory.
10:
EI
External interrupt with vector address
FFF1 :FFFO. (Rising/falling edge or high/low
level sensitive). Alternately can be configured
as 4th input capture.
11 :
NMI
Nonmaskable Interrupt Input
12:
INT2
Maskable Interrupt/Input Capture/URD
13:
INT3
Maskable Interrupt/Input Capture/UWR
14:
INT4
Maskable Interrupt/Input Capture
15:
SI
MICROWIRE/PLUS Data Input
16:
RDX
UART Data Input
AGND/EXUI has two uses, selected by a software bit. It
can be an external active low interrupt which
is internally OR'ed with the UART interrupt
with vector address FFF3:FFF2 or it can be
the analog ground for the AID converter.
17:
Port 0 is an 8-bit input port that can be used as general
purpose digital inputs or as analog channel inputs for the
A/D converter. These functions of Port 0 are mutually exclusive and under the control of software.
4-42
::J:
""C
Connection Diagrams
o
..A.
Plastic, Leadless and Leaded Chip Carriers
14
Is
12
13
rxm
81
Vm 80
8~
83
82
84
en
en
Pin Grid Array Pinout
r
87 GND
86 WO CKI
,/
CKO
10
11
17 @
0o@
STl
ST2
02 @
RESET
Ao
EI@
Al
..A.
~
INDEX MARK
15
........
13 YCC2 80 82 84 8s WO CKI
®0®~CD©@@@
Is 14 12A~ 81 83 85 87 GND
(jJ) ® ® ~ ® @ @ @ @ @ CKO
@Ol
10 @ @Il
@ 03
STl @ @ S12
@04
RESET @ !9 Ao
@ Os
AI @ @ A2
@ EXt.4
A3 @> @ A4
@
@
Po@ @Pl
As @ @A s
P2 @ @P 3
A7 @ @~
YREF @ @ @ @ @ @ @ @ @ @ @ OGNO
05
Az
A3
A4
As
07
As
A7
RDY IHLD
CK2
DGND
814812810 8s A14A12Al0 As CK2
@@®®@@@@@
en
en
..A.
~
........
::J:
""C
ow
en
..A.
en
~
........
::J:
""C
o
~
en
..A.
en
~
::J:
""C
TLlDD/9682-12
Top View
Top View
(looking down on component side of PC Board)
Order Number HPC16164E or V
See NS Package Number E68B or V68A
Order Number HPC16164U
See NS Package Number U68A
TLlDD/9682-11
o
N
........
815813811 8g A1S A13 All AgYCCI
815 813 811 89 AIS A13 All Ag VCCI
814 812 81D 8a Au Au AID As
::J:
""C
o
..A.
en
o
..A.
~
........
::J:
""C
o
N
en
o
..A.
~
........
::J:
""C
ow
en
......
o
~
........
::J:
""C
o
~
en
o
..A.
~
4-43
-.::I"
o
.....
CD
-.::I"
o
a..
z
.......
-.::I"
o
.....
CD
('I)
o
a..
z
.......
-.::I"
o
.....
Ports A & B
The highly flexible A and B ports are similarly structured.
The Port A (see Figure 7), consists of a data register and a
direction register. Port B (see Figures 8, 9 and 10) has an
alternate function register in addition to the data and direction registers. All the control registers are read/write registers.
A write operation to a port pin configured as an input causes
the value to be written into the data register, a read operation returns the value of the pin. Writing to port pins configured as outputs causes the pins to have the same value,
reading the pins returns the value of the data register.
Primary and secondary functions are multiplexed onto Port
B through the alternate function register (BFUN). The secondary functions are enabled by setting the corresponding
bits in the BFUN register.
The associated direction registers allow the port pins to be
individually programmed as inputs or outputs. Port pins selected as inputs, are placed in a TRI-STATE mode by resetting corresponding bits in the direction register.
CD
N
o
a..
z
.......
-.::I"
o
.....
WRITE PORT
CD
oa..
z
.......
-.::I"
CD
.....
CD
READ DIR A
-.::I"
o
a..
z.......
WRITE REGISTER
-.::I"
CD
.....
CD
('I)
o
a..
z
.......
-.::I"
CD
.....
TLlDD/9682-13
FIGURE 7. Port A: I/O Structure
FUNC~5W~~~~ +--------.,
CD
N
oa..
ALTERNATE
FUNCTION OUTPUT
z
.......
-.::I"
CD
.....
CD
.....
o
a..
z
READ PORT B
WRITE BFUN
READ BFUN
TLlDD/9682-14
FIGURE 8. Structure of Port B Pins BO, B1, B2, B5, B6 and B7 (Typical Pins)
4-44
::J:
-a
Ports A & B (Continued)
o
.....
0')
.....
0')
~
.......
::J:
-a
oI\)
0')
.....
0')
~
.......
::J:
-a
o
w
0')
.....
0')
~
.......
::J:
-a
o
~
0')
.....
0')
~
.......
::J:
-a
o
.....
0')
.....
o
~
.......
WRITE DIR B
::J:
-a
o
I\)
READ DIR B
TL/DD/9682-1S
FIGURE 9. Structure of Port 8 Pins 83, 84, 88, 89, 813 and 814 (Timer Synchronous Pins)
0')
.....
o
~
.......
::J:
-a
o
w
0')
.....
o
~
.......
::J:
-a
o
~
0')
.....
o
I
N
~
T
E
R
N
A
L
•
WRITE DIR B
------------.
READ PORT B
I
I
I
I
I
I
I
I
-----------_.
WRITE BtUN
t.lODE
EXPANDED
OR ROt.lLESS
READ BtUN
TL/DD/9682-16
FIGURE 10. Structure of Port 8 Pins 810, 811, 812 and 815 (Pins with 8us Control Roles)
4-45
~
o,...
CD
~
o
c..
::J:
......
~
o
,...
CD
C")
oc..
::J:
......
~
o
,...
CD
N
o
c..
::J:
......
~
o
,...
CD
,...
o
c..
::J:
......
~
CD
,...
CD
~
o
c..
::J:
......
~
,...
CD
CD
C")
oc..
::J:
......
~
CD
,...
CD
N
oc..
::J:
......
~
,...
,...
CD
CD
oc..
::J:
ROM) on-chip. It can address internal memory only, consisting of 16k bytes of ROM (COOO to FFFF) and 512 bytes of
on-chip RAM and Registers (0000 to 02FF). The "illegal
address detection" feature of the Watchdog is enabled in
the Single-Chip Normal mode and a Watchdog Output (WO)
will occur if an attempt is made to access addresses that
are outside of the on-chip ROM and RAM range of the device. Ports A and B are used for liD functions and not for
addressing external memory. The EXM pin and the EA bit of
the PSW register must both be logic "a" to enter the SingleChip Normal mode.
Operating Modes
To offer the user a variety of 110 and expanded memory
options, the HPC16164 and HPC16104 have four operating
modes. The ROMless HPC16104 has one mode of operation. The various modes of operation are determined by the
state of both the EXM pin and the EA bit in the PSW register. The state of the EXM pin determines whether on-chip
ROM will be accessed or external memory will be accessed
within the address range of the on-chip ROM. The on-chip
ROM range of the HPC16164 is COOO to FFFF (16k bytes) .
The HPC161 04 has no on-chip ROM and is intended for use
with external memory for program storage. A logic "a" state
on the EXM pin will cause the HPC device to address onchip ROM when the Program Counter (PC) contains addresses within the on-chip ROM address range. A logic "1"
state on the EXM pin will cause the HPC device to address
memory that is external to the HPC when the PC contains
on-chip ROM addresses. The EXM pin should always be
pulled high (logic "1") on the HPC16104 because no onchip ROM is available. The function of the EA bit is to determine the legal addressing range of the HPC device. A logic
"0" state in the EA bit of the PSW register does two
things-addresses are limited to the on-chip ROM range
and on-chip RAM and Register range, and the "illegal address detection" feature of the Watchdog logic is engaged.
A logic "1" in the EA bit enables accesses to be made
anywhere within the 64k byte address range and the "illegal
address detection" feature of the Watchdog logic is disabled. The EA bit should be set to "1" by software when
using the HPC16104 to disable the "illegal address detection" feature of Watchdog.
EXPANDED NORMAL MODE
The Expanded Normal mode of operation enables the
HPC16164 to address external memory in addition to the
on-chip ROM and RAM (see Table II). Watchdog illegal address detection is disabled and memory accesses may be
made anywhere in the 64k byte address range without triggering an illegal address condition. The Expanded Normal
mode is entered with the EXM pin pulled low (logic "a") and
setting the EA bit in the PSW register to "1".
SINGLE-CHIP ROM LESS MODE
In this mode, the on-chip mask programmed ROM of the
HPC16164 is not used. The address space corresponding
to the on-chip ROM is mapped into external memory so 16k
of external memory may be used with the HPC16164 (see
Table II). The Watchdog circuitry detects illegal addresses
(addresses not within the on-chip ROM and RAM range).
The Single-Chip ROMless mode is entered when the EXM
pin is pulled high (logic "1") and the EA bit is logic "0".
EXPANDED ROM LESS MODE
All HPC devices can be used with external memory. External memory may be any combination of RAM and ROM.
Both a-bit and 16-bit external data bus modes are available.
Upon entering an operating mode in which external memory
is used, port A becomes the Address/Data bus. Four pins of
port B become the control lines ALE, RD, WR and HBE. The
High Byte Enable pin (HBE) is used in 16-bit mode to select
high order memory bytes. The RD and WR signals are only
generated if the selected address is ott-chip. The a-bit mode
is selected by pulling HBE high at reset. If HBE is left floating or connected to a memory device chip select at reset,
the 16-bit mode is entered. The following sections describe
the operating modes of the HPC16164 and HPC16104.
This mode of operation is similar to Single-Chip ROM less
mode in that no on-chip ROM is used, however, a full 64k
bytes of external memory may be used. The "illegal address
detection" feature of Watchdog is disabled. The EXM pin
must be pulled high (logic "1 ") and the EA bit in the PSW
register set to "1" to enter this mode.
TABLE II. HPC16164 Operating Modes
EXM
Pin
EA
Bit
Memory
Configuration
Single-Chip Normal
0
a
COOO:FFFF on-chip
Expanded Normal
0
1
COOO:FFFF on-chip
0300:BFFF off-chip
Single-Chip ROM less
1
0
COOO:FFFF off-chip
Expanded ROM less
1
1
0300:FFFF off-chip
Operating
Mode
Note: The HPC devices use 16-bit words for stack memory. Therefore,
when using the 8-bit mode. User's Stack must be in internal RAM.
HPC16164 Operating Modes
SINGLE CHIP NORMAL MODE
Note: In all operating modes. the on-Chip RAM and Registers (OOOO:02FF)
may be accessed.
In this mode, the HPC16164 functions as a self-contained
microcomputer (see Figure 11) with all memory (RAM and
4-46
:I:
-a
o
.....
HPC16164 Operating Modes (Continued)
en
.....
en
0l:Io
.....
:I:
-a
PORTI ......~~·I
oN
en
.....
en
0l:Io
.....
PORTD .....~-'
:I:
PORT A
-a
o
w
PORTB
en
.....
en
0l:Io
.....
:I:
PORT P .... _-----'--_~"'.
-a
o
0l:Io
en
.....
en
0l:Io
.....
TL/DD/9682-17
FIGURE 11. Single-Chip Mode
ROMLESS
:I:
-a
ROM
"1"_)~
PORT I
....
HPC16164
....
,---J\.
rV
)
12
-a
oN
Iv
• .,
_
:I:
WR
ALE
...
[
.A
PORT B
o
0l:Io
.....
iiii
iiii
ViR
J"
PORT D
en
.....
EXM
....
1-)
[
o
.....
LATCH
en
.....
o
,.....
0l:Io
.....
MEMORY
:I:
-a
Ao-A1
ow
V
en
.....
Y
o
A
PORT P
<.....
4
HBE
t~ 150n
Vt--~
0l:Io
.....
~
...
:I:
A.-Au
."
o0l:Io
en
.....
Do-De
j~
o
0l:Io
+5V
TL/DD/9682-18
FIGURE 12. 8-Blt External Memory
•
4-47
"I::t
o
....
CD
"I::t
HPC16164 Operating Modes (Continued)
'i
oD.
'OM"":' .OM
"1"-~
:t:
0,-015
.......
"I::t
o
....
CD
C")
o
PORT I
[
....... !rto.
EXM
to.
8
Aa-A15
~
....
o
PORT D
c:::I::'
~
HPC16164
PORT B
"I::t
....
....o
~
¢¢
...
.A
PORT P
MEMORY
Ao-A7 r \ . _
....!....
HBE
iiii
Wii
+--
CS
Wii
....
,
---
...
V
....
D.
:t:
.......
Rii
'----'/
ALE
o
CD
00-07
"'""'-~
C'\I
oD.
.......
LATCH
....
CD
:t:
K
_
....
~
D.
,
{>'
....
A1- A15
:t:
.......
"I::t
~
J
~ >-~
"I::t
....
CD
CD
LATCH
----
iiD
-
A1-A15
~
~
Do-Dr
"I::t
oD.
MEMDRY
Wii ~
CS ~
IIo-D7
j
I
:t:
.......
"I::t
....
CD
TLIOO/9682-19
CD
C")
FIGURE 13. 16-Blt External Memory
o
D.
:t:
HPC16104 Operating Modes
....
EXPANDED ROM LESS MODE (HPC16104)
Because the HPC16104 has no on-chip ROM, it has only
one mode of operation, the Expanded ROMless Mode. The
EXM pin must be pulled high (logic "1") on power up, the
EA bit in the PSW register should be set to a "1". The
HPC16104 is a ROM less device and is intended for use with
external memory. The external memory may be any combination of ROM and RAM. Up to 64k bytes of external memory may be accessed. It is necessary to vector on reset to
an address between COOO and FFFF, therefore the user
should have external memory at these addresses. The EA
bit in the PSW register must immediately be set to "1" at the
beginning of the user's program to disable illegal address
detection in the Watchdog logic.
.......
"I::t
c.o
CD
C'\I
o
D.
:t:
.......
"I::t
....CDCD
....
o
D.
:t:
the instruction cycle, allowing the user to interface with slow
memories and peripherals.
Power Save Modes
Two power saving modes are available on the HPC16164:
HALT and IDLE. In the HALT mode, all processor activities
are stopped. In the IDLE mode, the on-board oscillator and
timer TO are active but all other processor activities are
stopped. In either mode, all on-board RAM, registers and
I/O are unaffected.
HALT MODE
The HPC16164 is placed in the HALT mode under software
control by setting bits in the PSW. All processor activities,
including the clock and timers, are stopped. In the HALT
mode, power requirements for the HPC16164 are minimal
and the applied voltage (Vcd may be decreased without
altering the state of the machine. There are two ways of
exiting the HALT mode: via the RESET or the NMI. The
RESET input reinitializes the processor. Use of the NMI input will generate a vectored interrupt and resume operation
from that point with no initialization. The HALT mode can be
enabled or disabled by means of a control register HALT
enable. To prevent accidental use of the HALT mode the
HALT enable register can be modified only once.
TABLE III. HPC16104 Operating Modes
Operating
Mode
EXM
Pin
EA
Bit
Memory
Configuration
Expanded ROM less
1
1
0300:FFFF off-chip
Note: The on-chip RAM and Registers (OOOO:02FF) of the HPC16104 may
be accessed at all times.
Wait States
IDLE MODE
The HPC16164 is placed in the IDLE mode through the
PSW. In this mode, all processor activity, except the onboard oscillator and Timer TO, is stopped. As with the HALT
The HPC16164 provides four software selectable Wait
States that allow access to slower memories. The Wait
States are selected by the state of two bits in the PSW
register. Additionally, the ROY input may be used to extend
4-48
INTERRUPT ENABLE REGISTER (ENIR)
Power Save Modes (Continued)
RESET and the External Interrupt on 11 are non-maskable
interrupts. The other interrupts can be individually enabled
or disabled. Additionally, a Global Interrupt Enable Bit in the
ENIR Register allows the Maskable interrupts to be collectively enabled or disabled. Thus, in order for a particular
interrupt to be serviced, both the individual enable bit and
the Global Interrupt bit (GIE) have to be set.
mode, the processor is returned to full operation by the
RESET or NMI inputs, but without waiting for oscillator stabilization. A timer TO overflow will also cause the HPC16164
to resume normal operation.
HPC16164 Interrupts
Complex interrupt handling is easily accomplished by the
HPC16164's vectored interrupt scheme. There are eight
possible interrupt sources as shown in Table IV.
INTERRUPT PENDING REGISTER (IRPD)
The IRPD register contains a bit allocated for each interrupt
vector. The occurrence of specified interrupt trigger conditions causes the appropriate bit to be set. There is no indication of the order in which the interrupts have been received. The bits are set independently of the fact that the
interrupts may be disabled. IRPD is a Read/Write register.
The bits corresponding to the maskable, external interrupts
are normally cleared by the HPC16164 after servicing the
interrupts.
TABLE IV. Interrupts
Vector
Address
Interrupt
Source
$FFFF:FFFE RESET
$FFFD:FFFC Nonmaskable external on
rising edge of 11 pin
$FFFB:FFFA External interrupt on 12 pin
$FFF9:FFF8 External interrupt on 13 pin
$FFF7:FFF6 External interrupt on 14 pin
$FFF5:FFF4 Overflow on internal timers
$FFF3:FFF2 Internal by on-board peripherals
or external on EXUI
$FFF1:FFFO External interrupt on EI pin
Arbitration
Ranking
0
1
For the interrupts from the on-board peripherals, the user
has the responsibility of resetting the interrupt pending flags
through software.
The NMI bit is read only and 12, 13, and 14 are designed as to
only allow a zero to be written to the pending bit (writing a
one has no affect). A LOAD IMMEDIATE instruction is to be
the only instruction used to clear a bit or bits in the IRPD
register. This allows a mask to be used, thus ensuring that
the other pending bits are not affected.
2
3
4
5
6
7
Interrupt Arbitration
INTERRUPT CONDITION REGISTER (IRCD)
The HPC16164 contains arbitration logic to determine which
interrupt will be serviced first if two or more interrupts occur
simultaneously. The arbitration ranking is given in Table IV.
The interrupt on Reset has the highest rank and is serviced
first.
Three bits of the register select the input polarity of the
external interrupt on 12, 13, and 14.
Servicing the Interrupts
The Interrupt, once acknowledged, pushes the program
counter (PC) onto the stack thus incrementing the stack
pointer (SP) twice. The Global Interrupt Enable bit (GIE) is
copied into the CGIE bit of the PSW register; it is then reset,
thus disabling further interrupts. The program counter is
loaded with the contents of the memory at the vector address and the processor resumes operation at this point. At
the end of the interrupt service routine, the user does a
RETI instruction to pop the stack and re-enable interrupts if
the CGIE bit is set, or RET to just pop the stack if the CGIE
bit is clear, and then returns to the main program. The GIE
bit can be set in the interrupt service routine to nest interrupts if desired. Figure 14 shows the Interrupt Enable Logic.
Interrupt Processing
Interrupts are serviced after the current instruction is completed except for the RESET, which is serviced immediately.
RESET and EXUI are level-LaW-sensitive interrupts and EI
is programmable for edge-(RISING or FALLING) or level(HIGH or LOW) sensitivity. All other interrupts are edge-sensitive. NMI is positive-edge sensitive. The external interrupts
on 12, 13 and 14 can be software selected to be rising or
falling edge. External interrupt (EXUI) is shared with the onboard peripherals, UART and AID. The EXUI interrupt is
level-LaW-sensitive. To select this interrupt, disable the ERI
and ETI UART interrupts by resetting these enable bits in
the ENUI register and disable the AID function by resetting
the ADEN bit in the AID control register #3 (CR3). To select the on-board peripherals interrupt, leave this pin floating
or tie it high if the A/D function is disabled. If the AID function is enabled, this pin becomes the analog ground
(AGND).
Reset
The RESET input initializes the processor and sets ports A
and B in the TRI-STATE condition and Port P in the LOW
state. RESET is an active-low Schmitt trigger input. The
processor vectors to FFFF:FFFE and resumes operation at
the address contained at that memory location (which must
correspond to an on board location). The Reset vector address must be between COOO and FFFF when using the
HPC16104.
Interrupt Control Registers
The HPC16164 allows the various interrupt sources and
conditions to be programmed. This is done through the various control registers. A brief description of the different control registers is given below.
4-49
•
HPC16164/HPC26164/HPC36164/HPC46164/HPC16104/HPC261041HPC36104/HPC46104
ENIR
MSB
1
1!
1!
1!
EI
ON-BOARD
PERIPH
TIMER
14
INT
LSB
13
INT
12
INT
OlE
en
... Meml
AND
OR
XOR
Logical and
Logical or
Logical exclusive·or
MA and Meml ~ MA
MA or Meml ~ MA
MA xor Meml ~ MA
MEMORY MODIFY INSTRUCTIONS
INC
DECSZ
Mem + 1 ~ Mem
Mem -1 ~ Mem, Skip next if Mem = 0
Increment
Decrement, skip if 0
4-60
~
C
HPC Instruction Set Description
Mnemonic
I
(Continued)
Description
I
Action
BIT INSTRUCTIONS
SBIT
RBIT
IFBIT
1 ~ Mem.bit
Set bit
Reset bit
If bit
O~Mem.bit
If Mem.bit is true, do next instr.
MEMORY TRANSFER INSTRUCTIONS
LO
ST
X
PUSH
POP
LOS
XS
Meml~MA
Load
Load, incr/decr X
Store to Memory
Exchange
Exchange, incr/decr X
Push Memory to Stack
Pop Stack to Memory
A ~ Mem(X), X ± 1 (or 2)
W ~ W(SP), SP+2 ~ SP
SP-2 ~ SP, W(SP) ~ W
Load A, incr/decr B,
Skip on condition
Exchange, incr/decr B,
Skip on condition
Mem(B) ~ A, B ±1 (or 2) ~ B,
Skip next if B greater/less than K
Mem(B) ~ A,B ± 1 (or 2) ~ B,
Skip next if B greater/less than K
Mem(X)
~
A, X ± 1 (or 2)
~
X
A~Mem
A~Mem
~
X
REGISTER LOAD IMMEDIATE INSTRUCTIONS
LOB
LOK
LOX
LOBK
Load
Load
Load
Load
imm~B
B immediate
K immediate
X immediate
Band K immediate
imm~K
imm~X
imm
~
B,imm
~
K
ACCUMULATOR AND C INSTRUCTIONS
CLRA
INCA
OECA
CaMPA
SWAP A
RRCA
RLCA
SHRA
SHLA
SC
RC
IFC
IFNC
O~A
Clear A
IncrementA
Decrement A
Complement A
Swap nibbles of A
Rotate A right thru C
Rotate A left thru C
Shift A right
Shift A left
SetC
ResetC
IFC
IF not C
A+ l~A
A-1 ~A
1's complement of A ~ A
A15:12 ~ A11:8 ~ A7:4 ~ A3:0
C~A15 ~ ... ~AO~C
C~A15 ~ ... ~AO~C
0~A15~ ... ~AO~C
C~A15~ ... ~AO~O
l~C
O~C
Do next if C = 1
Do next if C = 0
TRANSFER OF CONTROL INSTRUCTIONS
JSRP
Jump subroutine from table
JSR
Jump subroutine relative
JSRL
JP
JMP
JMPL
JIO
JIOW
Nap
RET
RETSK
RETI
Jump subroutine long
Jump relative short
Jump relative
Jump relative long
Jump indirect at PC + A
PC ~ W(SP),SP+2 ~ SP
W(table#) ~ PC
PC ~ W(SP),SP+ 2 ~ SP,PC+ # ~ PC
(# is + 1025 to -1023)
PC ~ W(SP),SP+2 ~ SP,PC+ # ~ PC
PC+ # ~ PC(# is +32 to -31)
PC+ # ~ PC(#is +257 to -255)
PC+# ~ PC
PC+A+1 ~ PC
then Mem(PC) + PC ~ PC
PC + 1 ~PC
SP-2 ~ SP,W(SP) ~ PC
SP-2 ~ SP,W(SP) ~ PC, & skip
SP-2 ~ SP,W(SP) ~ PC, interrupt re-enabled
No Operation
Return
Return then skip next
Return from interrupt
Note: W is 16-bit word of memory
MA is Accumulator A or direct memory (8 or 16-bit)
Mem is 8-bit byte or 16-bit word of memory
Meml is 8- or 16-bit memory or 8 or 16-bit immediate data
imm is 8-bit or 16-bit immediate data
imm8 is 8-bit immediate data only
4-61
-.:t'
o,....
CD
Memory Usage
-.:t'
o
Q.
Number Of Bytes For Each Instruction (number in parenthesis is 16-Bit field)
:::I:
.......
Using Accumulator A
-.:t'
o,....
Reg Indir.
(B)
(X)
CD
Cf)
oQ.
:::I:
.......
-.:t'
o
,....
CD
N
oQ.
:::I:
.......
-.:t'
o
,....
CD
,....
oQ.
:::I:
.......
To Direct Memory
Direct
Indlr
Index
Immed.
.
Direct
LD
X
ST
1
1
1
1
1
1
2(4)
2(4)
2(4)
3
3
3
4(5)
4(5)
4(5)
2(3)
3(5)
-
-
-
-
ADC
ADDS
SBC
DADC
DSBC
ADD
MULT
DIV
DIVD
1
2
3(4)
3
4(5)
4(5)
-
-
1
1
1
1
1
1
1
2
2
2
2
2
2
2
3(4)
3(4)
3(4)
3(4)
3(4)
3(4)
3(4)
3
3
3
3
3
3
3
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
2
4(5)
4(5)
4(5)
2(3)
2(3)
2(3)
1
1
1
1
1
2
2
2
2
2
3(4)
3(4)
3(4)
3(4)
3(4)
3
3
3
3
3
4(5)
4(5)
4(5)
4(5)
4(5)
-
-
-
..
5(6)
-
-
. ..
Immed.
3(4)
-
-
-
5(6)
4(5)
-
5(6)
-
-
5(6)
-
-
-
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
2(3)
2(3)
2(3)
2(3)
2(3)
4(5)
4(5)
4(5)
4(5)
4(5)
5(6)
5(6)
5(6)
5(6)
5(6)
4(5)
4(5)
4(5)
4(5)
4(5)
5(6)
5(6)
5(6)
5(6)
5(6)
-.:t'
CD
,....
CD
-.:t'
oQ.
:::I:
......
-.:t'
CD
,....
CD
Cf)
IFEQ
IFGT
AND
OR
XOR
·S-bit direct address
··16-bit direct address
o
Q.
......
-.:t'
(B)
(X)
Direct
Indlr
Index
B&X
SBIT
RBIT
IFBIT
1
1
1
2
2
2
3(4)
3(4)
3(4)
3
3
3
4(5)
4(5)
4(5)
1
1
1
DECSZ
INC
3
3
2
2
2(4)
2(4)
3
3
4(5)
4(5)
,....
CD
CD
N
oQ.
:::I:
......
-.:t'
CD
,....
CD
,....
o
Q.
:::I:
Immediate Load Instructions
Instructions that modify memory directly
:::I:
Register Indirect Instructions with
Auto Increment and Decrement
Instructions Using A and C
Register B With Skip
LOS A,·
XSA,·
(B+)
(B-)
1
1
1
1
CLR
INC
DEC
COMP
SWAP
RRC
RLC
SHR
SHL
SC
RC
IFC
IFNC
Register X
LOA,·
XA,·
(X+)
(X-)
1
1
1
1
A
A
A
A
A
A
A
A
A
1
1
1
1
1
1
1
1
1
1
1
1
1
Stack Reference Instructions
Direct
I
PUSH
POP
2
2
4-62
Immed.
LOB,·
LOX,·
LD K,·
2(3)
2(3)
2(3)
LD BK,·,·
3(5)
Transfer of Control Instructions
JSRP
JSR
JSRL
JP
JMP
JMPL
JID
JIDW
NOP
RET
RETSK
RETI
1
2
3
1
2
3
1
1
1
1
1
1
Development Support
MOLETM DEVELOPMENT SYSTEM
It contains three serial ports to optionally connect to a termi·
nal, a host system, a printer or a modem, or to connect to
other MOLEs in a multi·MOLE environment.
The MOLE (Microcomputer On Line Emulator) is a low cost
development system and emulator for all microcontroller
products. These include COPSTM microcontrollers and the
HPC family of products. The MOLE consists of a BRAIN
Board, Personality Board and optional host software.
MOLE can be used in either a stand alone mode or in con·
junction with a selected host system using PC· DOS commu·
nicating via a RS·232 port.
The purpose of the MOLE is to provide the user with a tool
to write and assemble code, emUlate code for the target
microcontroller and assist in both software and hardware
debugging of the system.
How to Order
To order a complete development package, select the sec·
tion for the microcontroller to be developed and order the
parts listed.
It is a self contained computer with its own firmware which
provides for all system operation, emulation control, com·
munication, PROM programming and diagnostic operations.
Development Tools Selection Table
Mlcrocontroller
Order
Part Number
Description
Includes
Manual
Number
MOLE·BRAIN
Brain Board
Brain Board Users Manual
420408188·001
MOLE·HPC·PB1
Personality Board
HPC Personality Board
Users Manual
42041 0477 ·001
MOLE·HPC·IBM·R
Relocatable Assembler
Software for IBM
HPC Software Users Manual
and Software Disk
PC·DOS Communications
Software Users Manual
424410836-001
HPC
MOLE·HPC·IBM·CR
424410897·001
C Compiler for IBM
Users Manual
HPC C Compiler Users Manual
and Software Disk
Assembler Software for IBM
MOLE·HPC·IBM
420040416·001
424410883·001
424410897 ·001
4-63
~
o
,...
CD
Development Support (Continued)
o
a..
DIAL·A·HELPER
~
o
a..
Dial-A-Helper is a service provided by the MOLE (Microcontroller On Line Emulator) applications group. It consists of
both an electronic bulletin board information system and a
method by which applications can take control of a MOLE
Development System at a remote site via modem in order to
resolve any problems.
........
Information System
o,...
The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION mode
that can be used to search out and retrieve application data
about NSC Microcontrollers. The user needs as a minimum,
a Dumb terminal, 300 or 1200 baud Modem, and a telephone.
:J:
........
~
o,...
CD
C")
:J:
~
CD
N
oa..
:J:
........
~
o
,...
,...
o
a..
CD
:J:
........
~
CD
,...
CD
Order PIN: MOLE·DIAL·A·HLP
Information System Package contains DIAL-A-HELPER
users manual PIN Public Domain Communications Software.
Factory Applications Support
Dial-A-Helper also provides immediate factory applications
support. If a user is having difficulty in getting a MOLE to
operate in a particular mode or something peculiar is occuring, he can contact us via his system and modem. He can
leave messages on our electronic bulletin board, which we
will respond to, or he can arrange for us to actually take
control of his system via modem for debugging purposes.
The applications group can then cause his system to execute various commands and try to resolve the customers
problem by actually getting customers system to respond.
Both parties see exactly what is occurring, as it is happening.
If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk for
later use.
This allows us to respond in minutes when applications help
is needed.
~
o
Voice: (408) 721-5582
Modem: (408) 739-1162
a..
:J:
........
~
CD
,...
CD
C")
o
a..
:J:
........
Baud:
300 or 1200 baud
Setup:
Length: 8-Bit
Parity:
None
Stop:
Bit
Operation: 24 Hrs. 7 Days
~
CD
,...
CD
N
DIAL·A·HELPER
o
a..
:J:
........
~
CD
,...
CD
,...
o
a..
HOST
COMPUTER
:J:
USER SITE
NATIONAL SEMICONDUCTOR SITE
TL/DD/9682-32
4-64
:J:
""D
Code Efficiency
One of the most important criteria of a single chip microcontroller is code efficiency. The more efficient the code, the
more features that can be put on a chip. The memory size
on a chip is fixed so if code is not efficient, features may
have to be sacrificed or the programmer may have to buy a
larger, more expensive version of the chip.
3. Compare the B register to the K register
4. Generate a conditional skip if B has passed K
The value of this multipurpose Instruction becomes evident
when looping through sequential areas of memory and exiting when the loop is finished.
BIT MANIPULATION INSTRUCTIONS
Any bit of memory, liD or registers can be set, reset or
The HPC16164 has been designed to be extremely codeefficient. The HPC16164 looks very good in all the standard
coding benchmarks; however, it is not realistic to rely only
on benchmarks. Many large jobs have been programmed
onto the HPC16164, and the code savings over other popular microcontrollers has been considerable.
tested by the single byte bit instructions. The bits can be
addressed directly or indirectly. Since all registers and liD
are mapped into the memory, it is very easy to manipulate
specific bits to do efficient control.
Reasons for this saving of code include the following:
DECIMAL ADD AND SUBTRACT
SINGLE BYTE INSTRUCTIONS
This instruction is needed to interface with the decimal user
world.
It can handle both 16-bit words and 8-bit bytes.
The 16-bit capability saves code since many variables can
be stored as one piece of data and the programmer does
not have to break his data into two bytes. Many applications
store most data in 4-digit variables. The HPC16164 supplies
8-bit byte capability for 2-digit variables and literal variables.
The majority of instructions on the HPC16164 are singlebyte. There are two especially code-saving instructions:
JP is a 1-byte jump. True, it can only jump within a range of
plus or minus 32, but many loops and decisions are often
within a small range of program memory. Most other micros
need 2-byte instructions for any short jumps.
JSRP is a 1-byte call subroutine. The user makes a table of
his 16 most frequently called subroutines and these calls
will only take one byte. Most other micros require two and
even three bytes to call a subroutine. The user does not
have to decide which subroutine addresses to put into his
table; the assembler can give him this information.
MULTIPLY AND DIVIDE INSTRUCTIONS
The HPC16164 has 16-bit multiply, 16-bit by 16-bit divide,
and 32-bit by 16-bit divide instructions. This saves both
code and time. Multiply and divide can use immediate data
or data from memory. The ability to multiply and divide by
immediate data saves code since this function is often
needed for scaling, base conversion, computing indexes of
arrays, etc.
EFFICIENT SUBROUTINE CALLS
The 2-byte JSR instructions can call any subroutine within
plus or minus 1k of program memory.
MULTIFUNCTION INSTRUCTIONS FOR DATA MOVEMENT AND PROGRAM LOOPING
o
......
Q)
......
Q)
~
.......
:J:
""D
oN
Q)
......
Q)
~
.......
:J:
""D
o
w
Q)
......
Q)
~
.......
:J:
""D
o
~
Q)
......
Q)
~
.......
:J:
""D
o
......
Q)
......
<:)
~
.......
:J:
""D
o
N
Q)
......
<:)
~
.......
:J:
""D
o
w
Q)
The HPC16164 has single-byte instructions that perform
multiple tasks. For example, the XS instruction will do the
following:
1. Exchange A and memory pointed to by the B register
......
<:)
~
.......
:J:
""D
o
~
2. Increment or decrement the B register
Q)
......
<:)
~
4-65
Part Selection
The HPC family includes devices with many different options and configurations to meet various application needs. The
number HPC16164 has been generically used throughout this datasheet to represent the whole family of parts. The following chart explains how to order various options available when ordering HPC family members.
Note: All options may not currently be available.
1'-:
E17
Sp."" .H,
17 = 17t.4Hz
30=30MHz
PACKAGE TYPE
E= Leadless Chip Carrier (LCC)
U= Pin Grid Array {PGA}
V = Plastic Leaded Chip Carrier {PLCC}
L = Leaded Ceramic Chip Carrier {LDCC}
T = Tape Pak {TP}
L - ROM Information
XXXI = custom masked ROM pattern
no designator = ROMless
L.....-ROt.! Size
8 = 8k byte ROt.!
6 = 16k byte ROt.!
0= ROMless device
' - - - -TEt.!PERATURE
4=Commerclal(OOC TO +700 C}
3 = Industrial (-40° C TO +85° C)
2 = Automotive {-40°C TO +1050 C}
1 = Military (-55°C TO +125 0 C}
TLlDD/9682-33
FIGURE 8_ HPC Family Part Numbering Scheme
Examples
HPC46104E17
-
ROMless, Commercial temp. (O°C to 70°C), LCC
+ 125°C), PGA
+ 105°C), PLCC
HPC16164XXX/U17 -
16k masked ROM, Military temp. (- 55°C to
HPC261 04XXXIV17 -
ROM less, Automotive temp. (-40°C to
4-66
::I:
~National
ADVANCE
INFORMATION
'"""
~
o
o
.......
::I:
H PC 16400/H PC36400/H PC46400 High-Performance
microControliers with HOLC Controller
"'C
oW
(7)
~
o
o
General Description
Features
The HPC16400 is a member of the HPCTM family of High
Performance microControliers. Each member of the family
has the same identical core CPU with a unique memory and
I/O configuration to suit specific applications. Each part is
fabricated in National's advanced microCMOS technology.
This process combined with an advanced architecture provides fast, flexible I/O control, efficient data manipulation,
and high speed computation.
• HPC family-core features:
- 16-bit data bus, ALU, and registers
- 64 kbytes of external memory addressing
- FASTI-20.0 MHz system clock
- High code efficiency
- 16 x 16 multiply and 32 x 16 divide
- Eight vectored interrupt sources
- Four 16-bit timer/counters with WATCHDOG logic
- MICROWIRE/PLUS serial I/O interface
- QMOS-Iow power with two power save modes
• Two full duplex HDLC channels
- Optimized for X.25 and LAPD applications
- Programmable frame address recognition
- Up to 4.65 Mbps serial data rate
- Built in diagnostics
• Programmable interchip serial data decoder
• Four channel DMA controller
• UART-full duplex, programmable baud rate
(up to 208.3 kBaud)
• 544 kbytes of extended addressing
• Easy interface to National's DASL, 'U' and'S' transceivers-TP3400, TP3410 and TP3420
• Industrial (-40°C to +85°C) and military (-55°C to
+ 125°C) temperature ranges
The HPC16400 has 4 functional blocks to support a wide
range of communication application-2 HDLC channels, 4
channel DMA controller to facilitate data flow for the HDLC
channels, programmable serial interface and UART.
The serial interface decoder allows the 2 HDLC channels to
be used with devices using interchip serial link for point-topoint & multipoint data exchanges. The decoder generates
enable signals for the HDLC channels allowing multiplexed
D and B channel data to be accessed.
The HDLC channels manage the link by providing sequencing using the HDLC framing along with error control based
upon a cyclic redundancy check (CRC). Multiple address
recognition modes, and both bit and byte modes of operation are supported.
The HPC16400 is available in 68-pin PLCC, LCC, LDCC and
PGA packages.
Block Diagram
rIDLE1
~
rHAlrl
~
A
5P
50
o
(7)
D Semiconductor
51
"'C
5K
PORT I
CORE CPU
._------------------------------_.
PORT A
PORT B
PORT R
PORT 0
TLIDD/6602-1
4-67
.......
::I:
"'C
o
~
(7)
~
o
o
Q
Q
~
CD
Absolute Maximum Ratings
o
If MilitaryI Aerospace specified devices are required,
ESD Rating
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications •
Yee with Respect to GND
~
D.
:c
........
Q
Q
~
Total Allowable Source or Sink Current
CD
Storage Temperature Range
o
D.
:c
........
Lead Temperature (Soldering, 10 sec)
C")
300·C
DC Electrical Characteristics Yee =
CD
~
HPC46400, - 40·C to
+ 85·C for HPC36400,
o
Symbol
Parameter
D.
- 55·C to
IDLE Mode Current
lee2
HALT Mode Current
lee3
+ 0.5)Y to (GND
- 0.5)Y
5.0Y ± 10% unless otherwise specified, T A
=
O·C to
+ 70·C for
+ 125·C for HPC16400
Max
Units
20.0 MHz· (Note 1)
70
mA
=
2.0 MHz (Note 1)
7
mA
5.5Y, fin
=
20.0 MHz (Note 1)
10
mA
5.5Y, fin
=
2.0 MHz (Note 1)
1
mA
=
5.5Y, fin
=
0 kHz (Note 1)
300
J.LA
=
2.5Y, fin
=
0 kHz (Note 1)
150
J.LA
Test Conditions
Supply Current
lee1
(Yee
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
+ 150·C
Q
Q
:c
All Other Pins
100mA
- 65·C to
2000Y
-0.5Yto 7.0Y
Yee
=
5.5Y, fin
=
Yee
=
5.5Y, fin
Yee
=
Yee
=
Yee
Yee
Min
INPUT VOLTAGE LEVELS RESET, NMI, CKI AND WO (SCHMITT TRIGGERED)
YIH1
Logic High
YIL1
Logic Low
Y
0. 9Yee
Y
0.1 Yee
PORTA
YIH2
YIL2
Logic High
I
Logic Low
Y
2.0
I
I
I
0.8
I
Y
ALL OTHER INPUTS
YIH3
Logic High
YIL3
Logic Low
Y
0.7 Yee
0.2 Yee
Y
III
Input Leakage Current
±1
J.LA
CI
Input Capacitance
(Note 2)
10
pF
CIO
I/O Capacitance
(Note 2)
20
pF
OUTPUT VOLTAGE LEVELS CMOS OPERATION
Logic High
10H
=
-10 J.LA
YOL1
Logic Low
10H
Port Al8 Drive, CK2
10H
=
=
10 J.LA
YOH2
YOL2
(Ao-A15, 810, 811, 812, 815)
10L
=
3mA
YOH3
10H
=
YOL3
Other Port Pin Drive, WO
(80- 8 9,813,814, PO-P3)
10L
VOH4
ST1 and ST2 Drive
10H
= 0.5 mA
= -6 mA, Vee =
10L
=
YOH1
YOL4
YRAM
RAM Keep-Alive Voltage
102
TRI-STATE Leakage Current
-7 mA, Yee
=
-1.6 mA, Yee
=
5.0Y
5.0V
(Note 3)
0.1
Y
0.4
Y
2.4
5.0Y
Y
2.4
Y
0.4
Y
0.4
Y
2.4
Y
1.6 mA
measured with no external drive (lOH and IOL = 0,
and VIL1 with rise and fall times less than 10 ns.
Note 2: These parameters are guaranteed by design and are not tested.
Note 3: Test duration is 100 ns.
Note 1: ICC1' ICC2' ICC3
Vee. CKI driven to VIH1
Y
Yee - 0.1
2.5
Y
±5
IIH
and
IlL
4-68
=
0). ICC1
is measured with RESET =
Vss. ICC3
is measured with
J.LA
NMI
=
::I:
AC Electrical Characteristics Vee =
5.0V ±10%, fe
-40·C to +85·C for HPC36400, -55·C to + 125·C for HPC16400
Symbol
= 16.78 MHz, TA = O·Cto +70·C for HPC46400,
Parameter
"'C
o.......
Q)
Min
Max
Units
20
~
C)
C)
fe
= CKI freq.
= 1/fe
te = 2/fe
tLL = %te - 9
Operating Frequency
2.0
MHz
.......
te1
Clock Period
50
ns
"'C
Timing Cycle
100
ns
Q)
ALE Pulse Width
41
ns
tOC1C2A
Delay from CKI Falling
Edge to CK2 Rising Edge
0
55
ns
tOC1C2F
Delay from CKI Falling
Edge to CK2 Rising Edge
0
55
ns
tOC1ALEA
(Notes 1, 2)
Delay from CKI Rising
Edge to ALE Rising Edge
0
35
ns
tOC1ALEF
(Notes 1, 2)
Delay from CKI Rising
Edge to ALE Falling Edge
0
35
ns
Delay from CK2 Rising
Edge to ALE Rising Edge
55
ns
tOC2ALEF
(Note 2)
= Y4tC + 20
Delay from CK2 Falling
Edge to ALE Falling Edge
55
ns
tST
= % tc - 16
Address Valid to
ALE Falling Edge
9
ns
tvp
= % tc - 10
Address Hold from ALE
Falling Edge
15
ns
Wait State Period
100
=
= tc = WS
fc /19
External Timer Input Frequency
tXIN
Pulse Width for Timer Inputs
fMW
External MICROWIRE/PLUS
Clock Input Frequency
ns
1052
40
kHz
ns
1.25
MHz
External UART Clock Input Frequency
MHz
2.5
fu = fc /8
Note 1: Do not design with this parameter unless CKI is driven with an active signal. When using a passive crystal circuit, CKI or CKO should not be connected to
any external logic since any load (besides the passive components in the crystal circuit) will affect the stability of the crystal unpredictably.
Note 2: These are not tested parameters. Therefore the given minImax value cannot be guaranteed. It is, however, derived from measured paramenters, and may
be used for system design with a very high confidence level.
Note: Measurement of AC specifications is done with external clock drive on CKI with 50% duty cycle. The capacitive load on CKO must be kept below 15 pF else
AC measurements will be skewed.
CPU Read Cycle Timing
fc
= 20 MHz with One Wait State (See Figure 1)
Symbol
Parameter
Min
= % tc - 20
tAW = % tc + WS - 10
tOA = tc - 15
tACC = tc + WS - 55
tAD = % tc + WS - 35
tAOA = tc - 5
ALE Falling Edge to RD Falling Edge
30
ns
RD Pulse Width
115
ns
tAAA
Data Hold after Rising Edge of RD
0
Max
85
Units
ns
Address Valid to Input Data Valid
145
ns
RD Falling Edge to Input Data Valid
90
ns
RD Rising Edge to Address Valid
Note: Minimum and Maximum values are calculated from maximum operating frequency.
4·69
~
C)
C)
.......
::I:
o
~
Q)
~
= Y4tC + 20
fXIN
ow
"'C
tOC2ALEA
(Note 2)
tWAIT
::I:
95
ns
C)
C)
o
o
-.:t'
CD
-.:t'
CPU Write Cycle Timing
(.)
.......
o
o
-.:t'
CD
C"')
(.)
D..
:J:
.......
o
o
-.:t'
CD
,....
(.)
D..
:J:
= 20 MHz with One Wait State (See Figure 2)
Parameter
Min
= % tc - 20
tww = % tc+WS - 15
tHW = %tc - 15
ALE Falling Edge to WR Falling Edge
30
ns
WR Pulse Width
160
ns
Data Hold after
Rising Edge of WR
10
ns
Data Valid before
Rising Edge of WR
110
ns
D..
:J:
fc
Symbol
tARW
tv
=
% tc + WS - 40
Note: Bus output (Port A) CL
outputs.
=
100 pF. CK2 output CL
DMA Read Cycle Timing
fc
Symbol
=
tARR
tRw
=
= % tc
=
tRO
75
%tc - 35
=
=
tc - 5
%tc - 10
Units
80 pF. AC Parameters are tested using DC Characteristics and non CMOS
= 20 MHz (See Figure 1)
Min
Max
Units
ALE Falling Edge to
RD Falling Edge
30
ns
RD Pulse Width
135
ns
Data Hold After
Rising Edge of RD
- 15
9~tc -
=
tROA
tvp
%tc - 15
=
tACC
50 pF. other outputs CL
Parameter
% tc - 20
tOR
=
Max
0
60
ns
Address Valid to
Input Data Valid
150
ns
RD Falling Edge to
Input Data Valid
115
ns
RD Rising Edge to
Address Valid
95
ns
Address Hold from ALE
Falling Edge
40
ns
Note: Minimum and Maximum values are calculated from moderate operating frequency.
DMA Write Cycle Timing
fc
Symbol
=
tARW
= 20 MHz (See Figure 2)
Parameter
% tc - 20
Min
Max
Units
ALE Trailing Edge to
WR Falling Edge
30
ns
tww
=
%tc - 15
WR Pulse Width
135
ns
tHW
=
%tc -15
Data Hold After
Trailing Edge of RD
35
ns
Data Valid before
Trailing Edge of WR
100
ns
Address Hold from ALE
Falling Edge
40
ns
tv
=
tvp
%tc - 50
=
% tc - 10
Note: Bus output (Port A) CL
outputs.
=
100 pF. CK2 output CL
=
50 pF. other outputs CL
4-70
=
80 pF. AC Parameters are tested using DC Characteristics and non CMOS
ReadyIHoid Timing
fc = 20 MHz with One Wait State
Symbol
tOAR =
Parameter
Y4 tc + WS
tHWP = tc
tHAO =
+
+
70
ns
100
ns
Falling Edge of HLO
to Rising Edge of ALE
115
ns
10
HLO Pulse Width
110
ns
100
Rising Edge on HLO to
Rising Edge on HLOA
225
ns
Falling Edge on HLO to
Falling Edge on HLOA
200·
ns
Bus Float before
Falling Edge on HLOA
tSF
tSE = %tc
Units
Ri5Y Pulse Width
% tc + 50
tHAE = tc
Max
+ 40
tRWP = tc
tSALE = 3/4 tc
Min
Falling Edge of ALE
to Falling Edge of ROY
- 55
+ 50
ns
0
Bus Enable from
Rising Edge of HLOA
°Note: tHAE may be as long as (31c
+ 4ws +
125
ns
+ 90) depending on which instruction is being executed, the addressing mode and number of wait states.
721c
tHAE maximum value tested is for the optimal case.
Timing Waveforms
tAAA
l - tLL
ALE
I
'\
tST
PORT A
,-=="
I
tvp
.f
~
I
:
tAce
tRD
'~
iiii
->---C
DATA IN VALID
ADDR OUT
,
-IoR=:j
J
IRW
IRDA
TL/DD/8802-22
FIGURE 1. CPU and DMA Read Cycles
I L l - i-IARW-
'~
ALE
-1ST· f-Ivp-j
PORT A
J
""-
f
"-
DATA OUT VALID
,.'
'}
I~IHW
tv
,
I
ADDR OUT
In
,~
iii
HBE
AODROUT
J
l
~,
J\
TLIDD/8802-21
FIGURE 2. CPU and DMA Write Cycles
4·71
o
o
-.:I'
CD
-.:I'
Timing Waveforms (Continued)
o
Q.
:I:
.....
o
o
-.:I'
CD
110
Cf)
oQ.
-------4(
ADDH
:I:
.....
o
TRI STATE
\
iiii
o
)
-.:I'
/
CD
,....
oQ.
~'~R--I---
:I:
TL/DD/8B02-4
FIGURE 3. Ready Mode Timing
ALE
r---'SAU--j
ru ---,~____________~
_...;f.I_':::::::'_Hw_'-:.-:.-:.-:.-:.-:.-:.:~-:.-:.-:.-:.-:.-:.-:.-:.-:.-:.-:..,-IHlD"----_____J~_---------------"LOA
\ . . ,
.---------IHlE-------I1
)
110
I
TRI·STATE
~
------~~~).:----:::~~~-IIF~~~~~--~-----_I+---...;.;,;,;,~;....--~::::====:-II-E~~~::==~~~
TL/DD/8802-5
FIGURE 4. Hold Mode Timing
4-72
:J:
Timing Waveforms
"1J
o
.....
(Continued)
0')
~--------------tc--------------~
CKI
~
I,...--~I
~
A
o
"-
o
-
~---'I
tOC1C2RI-
:J:
"1J
oCAl
0')
CK2
\.
A
o
o
"-
tOC2ALER
:J:
"1J
ALE
oA
1\
J
0')
A
tOC1ALEF'r-TLlDD/6602-23
FIGURE 5. CKI, CK2 ALE Timing Diagram
Pin Descriptions
I/O PORTS
Port A is a 16-bit multiplexed address/data bus used for
accessing external program and data memory. Four associated bus control signals are available on port 8. The Address Latch Enable (ALE) signal is used to provide timing to
demultiplex the bus. Reading from and writing to external
memory are signalled by RD* and WR* respectively. External memory can be addressed as either bytes or words with
the decoding controlled by two lines, 8us High 8yte enable
(H8E*) and Address/Data Line 0 (AO).
TDX
UART Data Output
81:
CFLG1
Closing Flag Output for HDLC # 1
Transmitter
82:
CKX
UART Clock (Input or Output)
83:
T210
Timer2 I/O Pin
84:
T310
Timer3 I/O Pin
85:
SO
MICROWIRE/PLUS Output
86:
SK
87:
BS2
Memory bank switch output 2
814:
8S3
Memory bank switch output 3 (MS8)
Port I is an 8-bit input port that can be read as general
purpose inputs and can also be used for the following functions:
Port 8 is a 16-bit port, with 12 bits of bidirectional I/O similar
in structure to port A. Pins 810, 811, 812 and 815 are the
control bus signals for the address/data bus. Port 8 may
also be configured via a function register 8FUN to individually allow each bidirectional I/O pin to have an alternate
function.
80:
813:
10:
HCK2
HLDC #2 Clock Input
11 :
NMI
Nonmaskable Interrupt Input
12:
INT2
Maskable Interrupt/Input Capture
13:
INT3
Maskable Interrupt/Input Capture
14:
INT4/RDY Maskable Interrupt/Input Capture/
Ready Input
15:
SI
16:
RDX
UART Data Input
17:
HCK1
HDLC # 1 Clock/Serial Decoder Clock
Input
MICROWIRE/PLUS Data Input
Port D is an 8-bit input port that can be read as general
purpose inputs and can also be used for the following functions:
DO:
MICROWIRE/PLUS Clock (Input or
Output)
REN1/FS/ Receiver # 1 Enable/Serial Decoder
RHCK1
Frame Sync Input/Receiver # 1 Clock
Input
D1:
TEN1
Transmitter # 1 Enable Input
HLDA*
Hold Acknowledge Output
D2:
88:
TSO
Synchronous Output
REN2/
RHCK2
Receiver # 2 Enable Input/Receiver
#2 Clock Input
89:
TS1
Timer Synchronous Output
D3:
TEN2
Transmitter # 2 Enable Input
810:
ALE
Address Latch Enable Output for
Address/Data 8us
D4:
RX1
Receiver # 1 Data Input
D5:
TX1
Transmitter # 1 Data Output
811:
WR*
Address/Data 8us Write Output
812:
H8E*
High 8yte Enable Output for
TS2
Timer Synchronous Output
814:
TS3
Timer Synchronous Output
815:
RD*
88:
BSO
Memory bank switch output 0 (LS8)
B9:
BS1
Memory bank switch output 1
RX2
Receiver # 2 Data Input
D7:
TX2
Transmitter # 2 Data Output
Note: Any of these pins can be read by software. Therefore, unused func·
tions can be used as general purpose inputs. notably external enable
lines when the internal serial decoder is used (see SERIAL DECOD·
ER/ENABLE CONFIGURATION REGISTER).
Address/Data 8us
813:
D6:
Port R is an 8-bit bidirectional I/O port available for general
purpose I/O operations. Port R has a direction register to
enable each separate pin to be individually defined as an
input or output. It has a data register which contains the
value to be output. In addition, the Port R pins can be read
directly using the Port R pins address.
Address/Data 8us Read Output
When operating in the extended memory addressing mode,
four bits of port 8 can are used as follows-
4-73
o
o
o
o
v
CD
v
r---------------------------------------------------------------------------------~
Pin Descriptions (Continued)
oa..
:::c
.......
Vee
Positive Power Supply (two pins)
o
GND
Ground for On-Chip Logic
o
Ground for Output Buffers
POWER SUPPLIES
v
DGND
('f)
CLOCK PINS
a..
CKI
The System Clock Input
CKO
The System Clock Output (Inversion of CKI)
CD
o
:::c
.......
o
o
v
.....
Pins CKI and eKO are usually connected across an external
crystal.
o
CK2
a..
:::c
OTHER PINS
CD
Bus Cycle Status Output indicates first opcode
fetch.
ST2
Bus Cycle Status Output indicates machine
states (skip and interrupt).
RESET
Active low input that forces the chip to restart
and sets the ports in a TRI-STATE mode.
ROY IHLD Has two uses, selected by a software bit. This
pin is either a READY input to extend the bus
cycle for slower memories or a HOLD-REQUEST
input to put the bus in a high impedance state for
external DMA purposes. In the second case the
14 pin becomes the READY input.
Clock Output (CKI divided by 2)
WO
ST1
This is an active low open drain output which signals an illegal situation has been detected by the
Watch Dog logic.
Connection Diagram
Pin Grid Array
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INDEX MARK
17 13 Vee BO 82 84 86 WO CKI
R7/
R6
R5 12
R4
R3
R2
Rl
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07
06
05
14
04
03
02 24
01
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R6 16 12 15 Bl 83 B5 87 GNO
@@@@@@@@@
R5@ @R4
10 @
R3 @ @ R2
ST1 @
Rl @ @RO
RESET @
07 @ @ 06
A1 @
R7@
05@ @14
04
@ @
AS
02@ @01
DO@
@CKO
@11
@ ST2
~AO
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A3@l @A4
03
@ @ A6
A7@
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CKO
10
58 11
STI
ST2
RESET
AO
AI
A2
A3
A4
AS
A6
A7
46 ROY/HlD
CK2
N
DGND
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815 B13 811 89 A15 Al3All A9 Vee
TLIDD/BB02-17
TLIDD/BB02-24
Top View
Top View
Order Number HPC16400E or V
See NS Package Number E688 or V68A
Order Number HPC16400EL or HPC16400U
See NS Package Number EL68A or U68A
Wait States
including the clock and timers, are stopped. In the HALT
mode, power requirements for the HPC16400 are minimal
and the applied voltage (Ved may be decreased without
altering the state of the machine. There are two ways of
exiting the HALT mode: via the RESET or the NMI. The
RESET input reinitializes the processor. Use of the NMI input will generate a vectored interrupt and resume operation
from that point with no initialization. The HALT mode can be
enabled or disabled by means of a control register HALT
enable. To prevent accidental use of the HALT mode the
HALT enable register can be modified only once.
The HPC16400 provides four software selectable Wait
States that allow access to slower memories. The Wait
States are selected by the state of two bits in the PSW
register. Additionally, the ROY input may be used to extend
the instruction cycle, allowing the user to interface with slow
memories and peripherals. The DMA always uses one Wait
State, independent of the value selected in the PSW.
Power Save Modes
Two power saving modes are available on the HPC16400:
HALT and IDLE. In the HALT mode, all processor activities
are stopped. In the IDLE mode, the on-board oscillator and
timer TO are active but all other processor activities are
stopped. In either mode, on-board RAM, registers and I/O
are unaffected.
IDLE MODE
The HPC16400 is placed in the IDLE mode through the
PSW. In this mode, all processor activity, except the onboard oscillator and Timer TO, is stopped. The HPC16400
resumes normal operation upon timer TO overflow. As with
the HALT mode, the processor is returned to full operation
by the RESET or NMI inputs, but without waiting for oscillator stabilization.
HALT MODE
The HPC16400 is placed in the HALT mode under software
control by setting bits in the PSW. All processor activities,
4-74
For the interrupts from the on-board peripherals, the user
has the responsibility of resetting the interrupt pending flags
through software.
HPC16400 Interrupts
Complex interrupt handling is easily accomplished by the
HPC16400's vectored interrupt scheme. There are eight
possible interrupt sources as shown in Table I.
INTERRUPT CONDITION REGISTER (IReD)
Three bits of the register select the input polarity of the
external interrupt on 12, 13, and 14.
TABLE I. Interrupts
Vectorl
Address
FFFFIFFFE
Interrupt Source
Reset
Arbitration
Ranking
FFFDIFFFC
Nonmaskable Ext (NMI)
1
FFFBIFFFA
External on 12
2
FFF91FFF8
External on 13
3
+
FFF71FFF6
14
FFF51FFF4
Internal on Timers
FFF31FFF2
Internal on UART
6
FFF11FFFO
End of Message (EOM)
7
HDLC/DMA Error
Servicing the Interrupts
0
The Interrupt, once acknowledged, pushes the program
counter (PC) onto the stack thus incrementing the stack
pointer (SP) twice. The Global Interrupt Enable (GIE) bit is
reset, thus disabling further interrupts. The program counter
is loaded with the contents of the memory at the vector
address and the processor resumes operation at this point.
At the end of the interrupt service routine, the user does a
RETI instruction to pop the stack, set the GIE bit and return
to the main program. The GIE bit can be set in the interrupt
service routine to nest interrupts if desired. Figure 6 shows
the Interrupt Enable Logic.
4
5
Reset
The 16400 contains arbitration logic to determine which interrupt will be serviced first if two or more interrupts occur
simultaneously. Interrupts are serviced after the current instruction is completed except for the RESET which is serviced immediately.
The RESET input initializes the processor and sets ports A,
B (except B12), 0 and R in the TRI-STATE condition. RESET is an active-low Schmitt trigger input. The processor
vectors to FFFF:FFFE and resumes operation at the address contained at that memory location.
The NMI interrupt will immediately stop DMA activity-byte
transfers in progress will finish thereby allowing an orderly
transition to the interrupt service vector (see DMA description). The HDLC channels continue to operate, and the user
must service data errors that might have occurred during
the NMI service routine.
Timer Overview
The HPC16400 contains a powerful set of flexible timers
enabling the HPC16400 to perform extensive timer functions; not usually associated with microconlrollers.
The HPC16400 contains four 16-bit timers. Three of the timers have an associated 16-bit register. Timer TO is a freerunning timer, counting up at a fixed CKI/16 (Clock Input!
16) rate. It is used for Watch Dog logic, high speed event
capture, and to exit from the IDLE mode. Consequently, it
cannot be stopped or written to under software control. Timer TO permits precise measurements by means of the capture registers 12CR, 13CR, and 14CR. A control bit in the
register TOCON configures timer T1 and its associated register R1 as capture registers 13CR and 12CR. The capture
registers 12CR, 13CR, and 14CR respectively, record the value of timer TO when specific events occur on the interrupt
pins 12, 13, and 14. The control register IRCD programs the
capture registers to trigger on either a rising edge or a falling
edge of its respective input. The specified edge can also be
programmed to generate an interrupt (see Figure 7).
Interrupt Processing
Interrupts are serviced after the current instruction is completed except for the RESET, which is serviced immediately.
RESET is a level-sensitive interrupt. All other interrupts are
edge-sensitive. NMI is positive-edge sensitive. The external
interrupts on 12, 13 can be software selected to be rising or
falling edge.
Interrupt Control Registers
The HPC16400 allows the various interrupt sources and
conditions to be programmed. This is done through the various control registers. A brief description of the different control registers is given below.
INTERRUPT ENABLE REGISTER (ENIR)
The timers T2 and T3 have selectable clock rates. The
clock input to these two timers may be selected from the
following two sources: an external pin, or derived internally
by dividing the clock input. Timer T2 has additional capability of being clocked by the timer T3 underflow. This allows
the user to cascade timers T3 and T2 into a 32-bit timer/
counter. The control register DIVBY programs the clock input to timers T2 and T3 (see Figure 8).
RESET and the External Interrupt on 11 are non-maskable
interrupts. The other interrupts can be individually enabled
or disabled. Additionally, a Global Interrupt Enable Bit in the
ENIR Register allows the Maskable interrupts to be collectively enabled or disabled. Thus, in order for a particular
interrupt to be serviced, both the individual enable bit and
the Global Interrupt bit (GIE) have to be set.
INTERRUPT PENDING REGISTER (IRPD)
The timers T1 through T3 in conjunction with their registers
form Timer-Register pairs. The registers hold the pulse duration values. All the Timer-Register pairs can be read from
or written to. Each timer can be started or stopped under
software control. Once enabled, the timers count down, and
upon underflow, the contents of its associated register are
automatically loaded into the timer.
The IRPD register contains a bit allocated for each interrupt
vector. The occurrence of specified interrupt trigger conditions causes the appropriate bit to be set. There is no indication of the order in which the interrupts have been received. The bits are set independently of the fact that the
interrupts may be disabled. IRPD is a Read/Write register.
The bits corresponding to the maskable, external interrupts
are normally cleared by the HPC16400 after servicing the
interrupts.
4-75
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Timer Overview (Continued)
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TO OVFL - - - - T3 UNFL
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MESSAGE
CONTROL - - - - - - - - - - REGISTER
REG: ENIR
TLIDD/BB02-B
FIGURE 6. Interrupt Enable Logic
~---"'TSO
~--"'TSI
~--"'TS2
1-----... TS3
t-.....--...
T210
1-...- -.... T310
TL/DD/BB02-10
FIGURE 8. Timers T2-T3 Block
4·76
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Timer Overview (Continued)
~
TO WATCHDOG
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Watch Dog Logic
The Watch Dog Logic monitors the operations taking place
and signals upon the occurrence of any illegal activity. The
illegal conditions that trigger the Watch Dog logic are potentially infinite loops. Should the Watch Dog register not be
written to before Timer TO overflows twice, or more often
than once every 4096 counts, an infinite loop condition is
assumed to have occurred. The illegal condition forces the
Watch Out (WO) pin low. The WO pin is an open drain output and can be connected to the RESET or NMI inputs or to
the users external logic.
_____ ....
11
I
L __ ....... --~ 11 UNFL
LCKI/18
TL/DD/8802-9
FIGURE 7. Timers TO-T1 Block
SYNCHRONOUS OUTPUTS
The flexible timer structure of the HPC16400 simplifies
pulse generation and measurement. There are four synchronous timer outputs (TSO through TS3) that work in conjunction with the timer T2. The synchronous timer outputs
can be used either as regular outputs or individually programmed to toggle on timer T2 underflows (see Figure 8).
Maximum output frequency for any timer output can be obtained by setting timer/register pair to zero. This then will
produce an output frequency equal to % the frequency of
the source used for clocking the timer.
MICROWIRE/PLUS
MICROWIRE/PLUS is used for synchronous serial data
communications (see Figure 11). MICROWIRE/PLUS has
an 8-bit parallel-loaded, serial shift register using SI as the
input and SO as the output. SK is the clock for the serial
shift register (SIO). The SK clock signal can be provided by
an internal or external source. The internal clock rate is programmable by the DIVBY register. A DONE flag indicates
when the data shift is completed.
Timer Registers
The MICROWIRE/PLUS capability enables it to interface
with any of National Semiconductor's MICROWIRE peripherals (Le., ISDN Transceivers, AID converters, display drivers, EEPROMs).
There are four control registers that program the timers. The
divide by (DIVBY) register programs the clock input to timers T2 and T3. The timer mode register (TMMODE) contains
control bits to start and stop timers T1 through T3. It also
contains bits to latch and enable interrupts from timers TO
through T3.
r-------------------------~SO
Timer Applications
SI
The use of Pulse Width Timers for the generation of various
waveforms is easily accomplished by the HPC16400.
Frequencies can be generated by using the timer/register
pairs. A square wave is generated when the register value is
a constant. The duty cycle can be controlled simply by
changing the register value.
' - - - - - . SK
TlIDD/6802-12
FIGURE 9. Square Wave Frequency Generation
Synchronous outputs based on Timer T2 can be generated
on the 4 outputs TSO-TS3. Each output can be individually
programmed to toggle on T2 underflow. Register R2 contains the time delay between events. Figure 10 is an example of synchronous pulse train generation.
TLIDD/8802-14
FIGURE 11. MICROWIRE/PLUS
4-77
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FIGURE 10. Synchronous Pulse Generation
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MICROWIRE/PLUS Operation
UART Wake-up Mode
The HPC16400 can enter the MICROWIRE/PLUS mode as
the master or a slave. A control bit in the IRCO register
determines whether the HPC16400 is the master or slave.
The shift clock is generated when the HPC16400 is configured as a master. An externally generated shift clock on the
SK pin is used when the HPC16400 is configured as a slave.
When the HPC16400 is a master, the OIVBY register programs the frequency of the SK clock. The OIVBY register
allows the SK clock frequency to be programmed in 14 selectable steps from 122 Hz to 1 MHz with CKI at 16 MHz.
The HPC16400 UART features a Wake-up Mode of operation. This mode of operation enables the HPC16400 to be
networked with other processors. Typically in such environments, the messages consist of addresses and actual data.
Addresses are specified by having the ninth bit in the data
frame set to 1. Data in the message is specified by having
the ninth bit in the data frame reset to O.
p---------------------------ROX
The contents of the SIO register may be accessed through
any of the memory access instructions. Data waiting to be
transmitted in the SIO register is shifted out on the falling
edge of the SK clock. Serial data on the SI pin is latched in
on the rising edge of the SK clock.
HPC16400 UART
The HPC16400 contains a software programmable UART.
The UART (see Figure 12) consists of a transmit shift register, a receiver shift register and five addressable registers,
as follows: a transmit buffer register (TBUF), a receiver buffer register (RBUF), a UART control and status register
(ENU), a UART receive control and status register (ENUR)
and a UART interrupt and clock source register (ENUI). The
ENU register contains flags for transmit and receive functions; this register also determines the length of the data
frame (8 or 9 bits) and the value of the ninth bit in transmission. The ENUR register flags framing and data overrun errors while the UART is receiving. Other functions of the
ENUR register include saving the ninth bit received in the
data frame and enabling or disabling the UART's Wake-up
Mode of operation. The determination of an internal or external clock source is done by the ENUI register, as well as
selecting the number of stop bits and enabling or disabling
transmit and receive interrupts.
r;;=:;;'il----~~-_+ TOX
D
A
T
A
The baud rate clock for the Receiver and Transmitter can
be selected for either an internal or external source using
two bits in the ENUI register. The internal baud rate is programmed by the OIVBY register, a special dedicated timer.
The baud rate may be selected from a range of 8 baud to
208.3 kbaud. Without having to select a special baud rate
crystal, all standard baud rates from 75 baud to 38.4 kbaud
can be generated. The external baud clock source comes
from the CKX pin. The Transmitter and Receiver can be run
at different rates by selecting one to operate from the internal clock and the other from an external source.
....----.T3
.....--.CKX
.........- . .
UNFL
CKI/2
The HPC16400 UART supports two data formats. The first
format for data transmission consists of one start bit, eight
data bits and one or two stop bits. The second data format
for transmission consists of one start bit, nine data bits, and
one or two stop bits. Receiving formats differ from transmission only in that the Receiver always requires only one stop
bit in a data frame.
TLlDD/8802-15
FIGURE 12. UART Block Diagram
4-78
:z:
UART Wake-up Mode (Continued)
HDLC Functional Description
The UART monitors the communication stream looking for
addresses. When the data word with the ninth bit set is
received, the UART signals the HPC16400 with an interrupt.
The processor then examines the content of the receiver
buffer to decide whether it has been addressed and whether
to accept subsequent data.
TRANSMITTER DESCRIPTION
Data information is transferred from external memory
through the DMA controller into the transmit buffer register
from where it is loaded into a 8-bit serial shift register. The
CRC is computed and appended to the frame prior to the
closing flag being transmitted. Data is output at the TX output pin. If no further transmit commands are given the transmitter sends out continous flags, aborts, or the idle pattern
as selected by the control register.
Programmable Serial Decoder
Interface
An interrupt is generated when the transmit shift register is
empty or on a transmit error condition. An assoicated transmit status register will contain the status information indicating the specific interrupt source.
The programmable serial decoder interface allows the two
HDLC channels to be used with devices employing several
popular serial protocols for point-to-point and multipoint
data exchanges. These protocols combine the 'B' and 'D'
channels onto common pins-received data, transmit data,
clock and Sync, which normally occurs at an 8 KHz rate and
provides framing for the particular protocol.
TRANSMITTER FEATURES
Interframe fill: the transmitter can send either continuous
'1's or repeated flags or aborts between the closing flag of
one packet and the opening flag of the next. When the CPU
commands the transmitter to open a new frame, the interframe fill is terminated immediately.
The decoder uses the serial link clock and Sync signals to
generate internal enables for the 'D' and 'B' channels,
thereby allowing the HDLC channels to access the appropriate channel data from the multiplexed link.
Abort: the 7 '1's abort sequence will be immediately sent on
command from the CPU or on an underrun condition in the
DMA. If required it may be followed by a new opening flag to
send another packet.
Bit/Byte boundaries: The message length between packet
headers may have any number of bits and is not confined to
an integral number of bytes. Three bits in the control register are used to indicate the number of valid bits in the last
byte. These bits are loaded by the users software.
HDLC Channel Description
HDLC/DMA Structure
HDLC 1
HDLC2
HDLC1
Receive
HDLC1
Transmit
HDLC2
Receive
HDLC2
Transmit
DMAR1
DMAT1
DMAR2
DMAT2
GENERAL INFORMATION
RECEIVER DESCRIPTION
Data is input to the receiver on the RX pin. The receive
clock can be externally input at either the HCK pin or the
REN/RHCK pin.
Both HDLC channels on the HPC16400 are identical and
operate up to 4.65 Mbps. When used in an ISDN basic access application, HDLC channel # 1 has been designated
for use with the 16 Kbps D-channel or either B channel and
HDLC # 2 can be used with either of the 64 Kbps B-channels. If the 'D' and 'B' channels are present on a common
serial link, the programmable serial decoder interface generates the necessary enable signals needed to access the
o and B channel data.
Incoming data is routed through one of several paths depending on whether it is the flag, data, or CRC.
Once the receiver is enabled it waits for the opening flag of
the incoming frame, then starts the zero bit deletion, addressing handling and CRC checking. All data between the
flags is shifted through two 8-bit serial shift registers before
being loaded into the buffer register. The user programmable address register values are compared to the incoming
data while it resides in the shift registers. If an address
match occurs or if operating in the transparent address recognition mode, the DMA channel is signaled that attention is
required and the byte is transferred by it to external memory. Appropriate interrupts are generated to the CPU on the
reception of a complete frame, or on the occurance of a
frame error.
LAPD, the Link Access Protocol for the D channel is derived
from the X.25 packet switching LAPB protocol. LAPD specifies the procedure for a terminal to use the 0 channel for
the transfer of call control or user-data information. The procedure is used in both point-to-point and point-to-multipoint
configurations. On the 16400, the HDLC controller contains
user programmable features that allow for the efficient processing of LAPD Information.
HDLC Channel Pin Description
There are two sources for the receive channel enable signal. It can be internally generated from the serial decoder
interface or it can be externally enabled.
Each HDLC channel has the following pins associated with
it.
HCK
-
HDLC Channel Clock Input Signal.
RX
-
Receive Serial Data Input. Data latched on
the negative HCK edge.
REN/RHCK -
HDLC Channel Receiver Enable Input/Receiver Clock Input.
TEN
-
HDLC Channel Transmitter Enable Input.
TX
- Transmit Serial Data Output. Data clocked
out on the positive HCK edge. Data (not including CRC) is sent LSB first. TRI-STATE
when transmitter not enabled.
The receive interrupt, in conjunction with status data in the
control registers allows interrupts to be generated on the
following conditions-CRC error, receive error and receive
complete.
RECEIVER FEATURES
Flag sharing: the closing flag of one packet may be shared
as the opening flag of the next. Receiver will also be able to
share a zero between flags-0111111 0111111 0 is a valid
two flag sequence for receive (not transmit).
4-79
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HDLC Functional Description
(Continued)
software control (HOLC control reg). The two error checking
polynomials available are:
Interframe fill: the receiver automatically accepts either repeated flags, repeated aborts, or all '1's as the interframe
fill.
(1) CRC-16 (x16 + x15 + x2 +1)
Idle: Reception of successive flags as the interframe fill sequence to be signaled to the user by setting the Flag bit in
the Receive status register.
SYNCHRONOUS BYPASS MODE
Short Frame Rejection: Reception of greater than 2 bytes
but less than 4 bytes between flags will generate a frame
error, terminating reception of the current frame and setting
the Frame Error (FER) status bit in the Receive Control and
Status register. Reception of less than 2 bytes will be ignored.
When the BYPAS bit is set in the HOLC control register, all
HOLC framing/formatting functions for the specified HOLC
channel are disabled.
This allows byte-oriented data to be transmitted and received synchronously thus "bypassing" the HOLC functions.
Abort: the 7 '1's abort sequence (received with no zero insertion) will be immediately recognized and will cause the
receiver to reinitialize and return to searching the incoming
data for an opening flag. Reception of the abort will cause
the abort status bit in the Interrupt Error Status register to be
set.
Bit/Byte boundaries: The message length between packet
headers may have any number of bits and it is not confined
to an integral number of bytes. Three bits in the status register are used to indicate the number of valid bits in the last
byte.
LOOP BACK OPERATIONAL MODE
The user has the ability, by setting the appropriate bit in the
register to internally route the transmitter output to the receiver input, and to internally route the RX pin to the TX pin.
(2) CCITT CRC (x16 + x12 + x5 + 1)
DMA Controller*
GENERAL INFORMATION
The HPC16400 uses Direct Memory Access (OMA) logic to
facilitate data transfer between the 2 full Duplex HOLC
channels and external packet RAM. There are four OMA
channels to support the four individual HOLC channels.
Control of the OMA channels is accomplished through registers which are configured by the CPU. These control registers define specific operation of each channel and changes
are immediately reflected in OMA operation. In addition to
individual control registers, a global control bit (MSS in Message Control Register) is available so that the HOLC channels may be globally controlled.
The OMA issues a bus request to the CPU when one or
more of the individual HOLC channels request service.
Upon receiving a bus acknowledge from the CPU, the OMA
completes all requests pending and any requests that may
have occurred during OMA operation before returning control to the CPU. If no further OMA transfers are pending, the
OMA relinquishes the bus and the CPU can again initiate a
bus cycle.
Addressing: Two user programmable bytes are available to
allow frame address recognition on the two bytes immediately following the opening flag. When the received address
matches the programmed value(s), the frame is passed
through to the OMA channel. If no match occurs, the received frame address information is disregarded and the
receiver returns to searching for the next opening flag and
the address recognition process starts anew.
Support is provided to allow recognition of the broadcast
address sequence of seven consecutive 1's. Additionally, a
transparent mode of operation is available where no address decoding is done.
HDLC INTERRUPT CONDITIONS
The end of message interrupt (EOM) indicates that a complete frame has been received or transmitted by the HOLC
controller. Thus, there are four separate sources for this
interrupt, two each from each HOLC channel. The Message
Control Register contains the pending bits for each source.
Four memory expansion bits have been added for each of
the four channels to support data transfers into the expanded memory bank areas.
The OMA has priority logic for a OMA requesting service.
The priorities are:
1st priority ................... Receiver channel 1
The HOLC/OMA error interrupt groups several related error
conditions. Error conditions from both transmit/receiver
channels can cause this interrupt, and the possible sources
each have a status bit in the error status register that is set
on the occurrence of an error. The bit must then be serviced
by the user.
2nd priority ................... Transmit channel 1
3rd priority .................... Receive channel 2
4th priority ................... Transmit channel 2
HDLC CHANNEL CLOCK
RECEIVER DMA OPERATION
Each HOLC channel uses the falling edge of the clock to
sample the receive data. Outgoing transmit data is shifted
out on the rising edge of the external clock. The maximum
data rate when using the externally provided clocks is
4.65 Mb/s.
The receiver OMA consists of a shift register and two buffers. A receiver OMA operation is initiated by the buffer registers. Once a byte has been placed in a buffer register from
the HOLC, it generates a request and upon obtaining control
of the bus, the OMA places the byte in external memory.
CYCLIC REDUNDACY CHECK
RECEIVER REGISTERS
All the following registers are Read/Write
There are two standard CRC codes used in generating the
16-bit Frame Check Sequence (FCS) that is appended to
the end of the data frame. Both codes are supported and
the user selects the error checking code to be used through
A. Frame Length Register
This user programmable 16-bit register contains the maximum number of bytes to be placed in a data "block". If
this number is exceeded, a Frame Too Long (FTLR1,
FTLR2) error is generated. This register is decremented
by one each Receiver OMA cycle.
·The specific registers and/or register names may have changed. Please
contact the factory for updated information.
4-80
DMA Controller (Continued)
B. CNTRl ADDR 1
DATAADDR 1
CNTRlADDR 2
DATAADDR2
::I:
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Shared Memory Support
For split frame operation, the CNTRl
ADDR register contains the external
memory address where the Frame
Header (Control & Address fields) are
to be stored and the DATA ADDR register contains an equivalent address for
the Information field.
Shared memory access provides a rapid technique to exchange data. It is effective when data is moved from a peripheral to memory or when data is moved between blocks
of memory. A related area where shared memory access
proves effective is in multiprocessing applications where
two CPUs share a common memory block. The HPC16400
supports shared memory access with two pins. The pins are
the RDY /HlD input pin and the HlDA output pin. The user
can software select either the Hold or Ready function on the
RDY /HlD pin by the state of a control bit. The HlDA output
is multiplexed onto port B.
The host uses DMA to interface with the HPC16400. The
host initiates a data transfer by activating the HlD input of
the HPC16400. In response, the HPC16400 places its system bus in a TRI-STATE Mode, freeing it for use by the host.
The host waits for the acknowledge signal (H lDA) from the
HPC16400 indicating that the sytem bus is free. On receiving the acknowledge, the host can rapidly transfer data into,
or out of, the shared memory by using a conventional DMA
controller. Upon completion of the message transfer, the
host removes the HOLD request and the HPC16400 resumes normal operations.
Figure 13 illustrates an application of the shared memory
interface between the HPC16400 and a Series 32000 system.
For non-split frame operation, the
CNTRl and DATA ADDR registers
each contain the external memory address for the entire frame.
TRANSMITTER DMA OPERATION
The transmitter DMA consists of a shift register and two
buffers. A transmitter DMA cycle is initiated by the TX data
buffers. The TX data buffers generate a request when either
one is empty and the DMA responds by placing a byte in the
buffer. The HDlC transmitter can then accept the byte to
send when needed, upon which the DMA will issue another
request, resulting in a subsequent DMA cycle.
TRANSMITTER REGISTERS
The following registers are
A. Field Address 1 (FA1)
# Bytes Field 1 (NBF1)
Field Address (FA2)
Read/Write:
FA1 and FA2 are starting addresses of blocks of information to transmitter.
NBF1 and NBF2 are the num# Bytes Field 2 (NBF2) ber of bytes in the block to be
transmitted.
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CPU 2
CPU 1
HOLD
Roy/HID
HLDA
REMOTE
HPC16400
fiiliA
SERIES 32000
HOST SYSTEM
• CPU
• Teu
• DMA CONTROLLER
~
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A
"-....
ADDRESS/DATA BUS
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4
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SHARED
MEMORY
RD, Viii, ALE, HBE
l-
IITL/DD/8802-16
FIGURE 13. Shared Memory Application: HPC16400 Interface to Series 32000 System
4-81
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lows four 1/0 lines of Port 8 (88, 89, 813, 814) to be used
in extending the address range. This gives the user a main
routine area of 32k and 16 banks of 32k each for subroutine
and data, thus getting a total of 544k of memory.
Memory
The HPC16400 has been designed to offer flexibility in
memory usage. A total address space of 64 kbytes can be
addressed with 256 bytes of RAM available on the chip itself.
Note: If all four lines are not needed for memory expansion, the unused
lines can be used as general purpose inputs.
Program memory addressing is accomplished by the 16-bit
program counter on a byte basis. Memory can be addressed
directly by instructions or indirectly through the 8, X and SP
registers. Memory can be addressed as words or bytes.
Words are always addressed on even-byte boundaries. The
HPC16400 uses memory-mapped organization to support
registers, 1/0 and on-chip peripheral functions.
The Extended Memory Addressing mode is entered by setting the EMA control bit in the Message Control Register. If
this bit is not set, the port 8 lines (88, 89, 813, 814) are
available as general purpose 1/0 or synchronous outputs as
selected by the 8FUN register.
The main memory area contains the interrupt vectors &
service routines, stack memory, and common memory for
the bank subroutines to use. The 16 banks of memory can
contain program or data memory (note: since the on chip
resources are mapped into addresses 0000-01 FF, the first
512 bytes of each bank are not usable).
The HPC16400 memory address space extends to 64
kbytes and registers and 1/0 are mapped as shown in Table
II.
Extended Memory Addressing
If more than 64k of addressing is desired in a HPC16400
system, on board bank select circuitry is available that ai-
TABLE II. Memory Map
FFFF-FFFO
FFEF-FFDO
Interrupt Vectors
JSRP Vectors
FFCF-FFCE
:
:
External Expansion
USER MEMORY
0201-0200
01FF-01FE
:
:
On Chip RAM
USER RAM
01C1-01CO
01B8
01B6
01B4
01B2
01BO
Error Status
Receiver Status
HDLCCntrl
Recr Addr Comp Reg 2
Recr Addr Comp Reg 1
HDLC # 2
01A8
01A6
01A4
01A2
01AO
Error Status
Receiver Status
HDLCCntrl
Recr Addr Comp Reg 2
Recr Addr Comp Reg 1
HDLC # 1
0195-0194
Watch Dog Register
0193-0192
0191-0190
018F-018E
018D-018C
018B-018A
0189-0188
0187-0186
0185-0184
0183-0182
0181-0180
TOCON Register
TMMODE Register
DIVBY Register
T3Timer
R3 Register
T2Timer
R2 Register
12CR Register/ R1
13CR Register! T1
14CR Register
017F-017E
017D-017C
UART Counter
UART Register
0179-0178
0177-0176
0175-0174
0173-0172
0171-0170
# Bytes 2
Field Addr 2
# Bytes 1
Field Addr 1
Xmit Cntrl & Status
016B-016A
0169-0168
0167-0166
0165-0164
0163-0162
0161-0160
Frame Length
Data Addr 2
Cntrl Addr 2
Data Addr 1
CntrlAddr 1
Recv Cntrl & Status
Watch Dog Logic
Timer Block TO-T3
DMAT # 2 (Xmit)
DMAR # 2 (Recv)
0159-0158
0157-0156
0155-0154
0153-0152
0151-0150
# Bytes 2
Field Addr2
# Bytes 1
Field Addr 1
Xmit Cntrl & Status
014B-014A
0149-0148
0147-0146
0145-0144
0143-0142
0141-0140
Frame Length
Data Addr2
Cntrl Addr2
Data Addr 1
CntrlAddr 1
Recv Cntrl & Status
0128
0126
0124
0122
0120
ENUR Register
TBUF Register
RBUF Register
ENUI Register
ENU Register
010E
010C
010A
0106
0104
0102
0100
PortR Pins
DIR R Register
Port R Data Register
Serial Decoder/Enable
Configuration Reg
Message Pending
Message Control
Port D Pins
00F5-00F4
00F3-00F2
00E3-00E2
BFUN Register
DIR B Register
PortB
OODE
OODD-OODC
00D8
00D6
00D4
00D2
OODO
Microcode ROM Dump
Halt Enable Register
Port I Input Register
SIO Register
IRCD Register
IRPD Register
ENIR Register
PORT CONTROL
& INTERRUPT
CONTROL
REGISTERS
OOCF-OOCE
OOCD-OOCC
OOCB-OOCA
00C9-00C8
00C7-00C6
00C5-00C4
00C3-00C2
00C1-00CO
X Register
B Register
K Register
A Register
PC Register
SP Register
(Reserved)
PSW Register
HPC16040 CORE
REGISTERS
OOBF-OOBE
On Chip
RAM
:
:
0001-0000
4-82
DMAT # 1 (Xmit)
DMAR # 1 (Recv)
UART
PORTS R&D
PORTB
USER RAM
::I:
Indirect
HPC16400 CPU
The instruction contains an 8-bit address field. The contents
of the WORD addressed points to the memory for the operand.
The HPC16400 CPU has a 16-bit ALU and six 16-bit registers.
Arithmetic Logic Unit (ALU)
Indexed
The ALU is 16 bits wide and can do 16-bit add, subtract and
shift or logic AND, OR and exclusive OR in one timing cycle.
The ALU can also output the carry bit to a 1-bit C register.
The instruction contains an 8-bit address field and an 8- or
16-bit displacement field. The contents of the WORD addressed is added to the displacement to get the address of
the operand.
Accumulator (A) Register
The 16-bit A register is the source and destination register
for most liD, arithmetic, logic and data memory access operations.
Immediate
The instruction contains an 8-bit or 16-bit immediate field
that is used as the operand.
Address (B and X) Registers
Register Indirect (Auto Increment and Decrement)
The 16-bit B and X registers can be used for indirect addressing. They can automatically count up or down to sequence through data memory.
The operand is the memory addressed by the X register.
This mode automatically increments or decrements the X
register (by 1 for bytes and by 2 for words).
Boundary (K) Register
Register Indirect (Auto Increment and Decrement) with
Conditional Skip
The 16-bit K register is used to set limits in repetitive loops
of code as register B sequences through data memory.
The operand is the memory addressed by the B register.
This mode automatically increments or decrements the B
register (by 1 for bytes and by 2 for words). The B register is
then compared with the K register. A skip condition is generated if B goes past K.
Stack Pointer (SP) Register
The 16-bit SP register is the stack pointer that addresses
the stack. The SP register is incremented by two for each
push or call and decremented by two for each pop or return.
The stack can be placed anywhere in user memory and be
as deep as the available memory permits.
ADDRESSING MODES-DIRECT MEMORY AS
DESTINATION
Program (PC) Register
Direct Memory to Direct Memory
The 16-bit PC register addresses program memory.
The instruction contains two 8- or 16-bit address fields. One
field directly points to the source operand and the other field
directly points to the destination operand.
Addressing Modes
ADDRESSING MODES-ACCUMULATOR AS
DESTINATION
Immediate to Direct Memory
The instruction contains an 8- or 16-bit address field and an
8- or 16-bit immediate field. The immediate field is the operand and the direct field is the destination.
Register Indirect
This is the "normal" mode of addressing for the HPC16400
(instructions are single-byte). The operand is the memory
addressed by the B register (or X register for some instructions).
Double Register Indirect using the B and X Registers
Used only with Reset, Set and IF bit instructions; a specific
bit within the 64 kbyte address range is addressed using the
B and X registers. The address of a byte of memory is
formed by adding the contents of the B register to the most
significant 13 bits of the X register. The specific bit to be
modified or tested within the byte of memory is selected
using the least significant 3 bits of register X.
Direct
The instruction contains an 8-bit or 16-bit address field that
directly points to the memory for the operand.
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ARITHMETIC INSTRUCTIONS
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Description
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Action
MA+Meml~MA
carry~
MA+imm8~
carry~
ADD
ADDS
ADC
DADC
SUBC
DSUBC
MULT
DIV
DIVD
IFEQ
IFGT
Add
Add short imm8
Add with carry
Decimal add with carry
Subtract with carry
Decimal subtract w/carry
Multiply (unsigned)
Divide (unsigned)
Divide Double Word (unsigned)
If equal
If greater than
MA+Meml+C~ MA
MA + Meml + C ~ MA (Decimal)
MA-Meml+C~ MA
MA - Meml + C ~ MA (Decimal)
MA*Meml ~ MA&X,a ~ K,a ~ C
MAlMeml ~ MA, rem. ~ X, a ~ K, a ~ C
(x8 MA)/Meml ~ MA, rem ~ X, a ~ K
Compare MA & Meml, Do next if equal
Compare MA & Meml, Do next if MA ~ Meml
AND
OR
XOR
Logical and
Logical or
Logical exclusive-or
MA and Meml ~ MA
MA or Meml ~ MA
MA xor Meml ~ MA
MA
MEMORY MODIFY INSTRUCTIONS
INC
DECSZ
Increment
Decrement, skip if a
Mem + 1 ~ Mem
Mem -1 ~ Mem, Skip next if Mem
Set bit
Reset bit
If bit
a~
=
BIT INSTRUCTIONS
SBIT
RBIT
IFBIT
1 ~ Mem.bit (bit is a to 7 immediate)
Mem.bit
If Mem.bit is true, do next instr.
MEMORY TRANSFER INSTRUCTIONS
LD
ST
X
PUSH
POP
LDS
XS
Meml~MA
Load
Load, incr/decr X
Store to Memory
Exchange
Exchange, incr/decr X
Push Memory to Stack
Pop Stack to Memory
A ~ Mem; Mem ~ Mem
A ~ Mem(X), X ±1 (or2) ~ X
W ~ W(SP), SP+2 ~ SP
SP-2 ~ SP, W(SP) ~ W
Load A, incr/decr B,
Skip on condition
Exchange, incr/decr B,
Skip on condition
Mem(B) ~ A, B ±1 (or 2) ~ B,
Skip next if B greater/less than K
Mem(B) ~ A,B ± 1 (or 2) ~ B,
Skip next if B greater/less than K
Mem(X)
~
A, X ±1 (or 2)
~
X
MA~Mem
REGISTER LOAD IMMEDIATE INSTRUCTIONS
LDA
LDB
LDK
LDX
LDBK
Load A immediate
Load B immediate
Load K immediate
Load X immediate
Load Band K immediate
imm~A
imm~B
imm~K
imm~X
imm
~
B,imm
~
K
ACCUMULATOR AND C INSTRUCTIONS
CLRA
INCA
DECA
COMPA
SWAP A
RRCA
RLCA
SHRA
SHLA
SC
RC
IFC
IFNC
Clear A
IncrementA
Decrement A
Complement A
Swap nibbles of A
Rotate A right thru C
Rotate A left thru C
Shift A right
Shift A left
SetC
Reset C
IFC
IF not C
a~A
A + 1 ~A
A-1 ~A
1's complement of A ~ A
A15:12 ~ A11:8 ~ A7:4 ~ A3:a
C~A15 ~ ... ~Aa~C
C~A15 ~ ... ~Aa~C
a~A15~ ... ~Aa~C
C~A15~ ... ~Aa~a
1~C
a~c
Do next if C
Do next if C
4-84
=
=
1
a
a
C
C
carry~ C
carry~ C
carry~ C
carry~ C
carry~
C
:I:
HPC Instruction Set Description
I
Mnemonic
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I
Description
en
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Action
TRANSFER OF CONTROL INSTRUCTIONS
JSRP
Jump subroutine from table
JSR
Jump subroutine relative
JSRL
JP
JMP
JMPL
JID
JIDW
NOP
RET
RETS
RETI
Jump subroutine long
Jump relative short
Jump relative
Jump relative long
Jump indirect at PC + A
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PC ~ W(SP),SP + 2 ~ SP
W(table#) ~ PC
PC ~ W(SP),SP+ 2 ~ SP,PC+ # ~ PC
( # is + 1024 to -1023)
PC ~ W(SP),SP+2 ~ SP,PC+ # ~ PC
PC+ # ~ PC(# is +32 to -31)
PC+ # ~ PC(#is +256 to -255)
PC+# ~ PC
PC+A+1 ~ PC
then Mem(PC) + PC ~ PC
PC~PC + 1
SP-2 ~ Sp,w(SP) ~ PC
SP-2 ~ SP,W(SP) ~ PC, & skip
SP-2 ~ SP,W(SP) ~ PC, interrupt re-enabled
No Operation
Return
Return then skip next
Return from interrupt
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Note: W is 16-bit word of memory
MA is Accumulator A or direct memory (8 or 16-bit)
Mem is 8-bit byte or 16-bit word of memory
Meml is 8- or 16-bit memory or 8 or 16-bit immediate data
imm is 8-bit or 16-bit immediate data
Memory Usage
Number Of Bytes For Each Instruction (number in parenthesis is 16-Bit field)
Using Accumulator A
Reg Indlr.
(X)
(B)
Direct
To Direct Memory
Index
Indir
*
•*
.
3(5)
5(6)
3(4)
Immed_
Direct
Immed.
..
LD
X
ST
1
1
1
1
1
1
2(4)
2(4)
2(4)
3
3
3
4(5)
4(5)
4(5)
2(3)
ADC
SBC
DADC
DSBC
ADD
MULT
DIV
1
1
1
1
1
1
1
2
2
2
2
2
2
2
3(4)
3(4)
3(4)
3(4)
3(4)
3(4)
3(4)
3
3
3
3
3
3
3
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
2(3)
2(3)
2(3)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
IFEQ
IFGT
AND
OR
XOR
1
1
1
1
1
2
2
2
2
2
3(4)
3(4)
3(4)
3(4)
3(4)
3
3
3
3
3
4(5)
4(5)
4(5)
4(5)
4(5)
2(3)
2(3)
2(3)
2(3)
2(3)
4(5)
4(5)
4(5)
4(5)
4(5)
5(6)
5(6)
5(6)
5(6)
5(6)
4(5)
4(5)
4(5)
4(5)
4(5)
5(6)
5(6)
5(6)
5(6)
5(6)
-
-
-
5(6)
-
-
-
·8-bit direct address
• ·16-bit direct address
Immediate Load Instructions
Instructions that modify memory directly
(B)
(X)
Direct
Indir
Index
B&X
SBIT
RBIT
IFBIT
1
1
1
2
2
2
3(4)
3(4)
3(4)
3
3
3
4(5)
4(5)
4(5)
1
1
1
DECSZ
INC
3
3
2
2
2(4)
2(4)
3
3
4(5)
4(5)
4-85
Immed.
LD B,·
LOX,·
LD K,*
2(3)
2(3)
2(3)
LD BK,·,·
3(5)
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ADDRESS IN
TL/DD/9122-3
FIGURE 2. Read Cycle
H
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ALE
ADO-ADIS
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ADDRESS IN
>------C
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PAO- PAIS
PB10.ll.12.1S
PCO - PC1S
DATA IN VALID
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ADDRESS IN
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-_-P_OR-T_P:C-D_AT-A_O:UT::
TL/DD/9122-4
FIGURE 3. Write Cycle
4-92
Timing Waveforms
UAO
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TL/DD/9122-5
UAO
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FIGURE 4. UPI Read Timing
TRI-STATE
ron~---------------WRRDY
___________________________________~JI
_______________________________________________--J
READ IBUf
(INTERNAL)
TLlDD/9122-6
FIGURE 5. UPI Write Timing
Pin Descriptions
Pin
Vee (2)
GND(2)
RESET
PRLSEL
ADO-AD15
ALE
WR
HBE
RD
PAO-PA15
PB10/UAO
PB11/WRRDY
Description
Pin
PB12
Output only pin
PB15/RDRDY Output only pin, or RDRDY output in UPI
mode
Latched external address bits (outputs), or
PCO-PC15
16·bit I/O port (bidirectional). Port PC is a
latched version of the address output on
the ADO-AD15 bus if SELO and SEL 1 are
both low and a 16-bit bidirectional I/O port
otherwise.
Two inputs which specify the PEARL numSEL1,0
ber of the port expander (00 = PEARL 0,
01 = PEARL 1, 10 = PEARL 2, 11 =
PEARL 3)
UPI read strobe (input, low assert) which
causes the PEARL to output OBUF (UPI
output buffer) on the PA bus if the PEARL
is in UPI mode. When not using the
PEARL O-UPI mode, this input should be
tied to Vee.
UPI write strobe (input, low assert) which
causes the PEARL to latch the data present on the PA bus into IBUF (the UPI input
buffer) if the PEARL is in UPI mode. When
not using the PEARL O-UPI mode, this input
should be tied to Vee.
No Connect
NC
Description
Supply voltage
Ground reference
Chip reset (active low). Schmitt trigger input
will
which
initializes
PEARL
and
TRI-STATE® all ports
Reset Output (active low) which can be
used to reset the HPC and any other
PEARL chips in the same system
An output (high assert) signalling when the
address on the AD port has selected a
PEARL register for that particular PEARL
configuration (Le., PEARL 0, PEARL 1,
PEARL 2, PEARL 3). This output is useful
for disabling memory data which may reside at the same addresses as the PEARL
registers.
16·bit multiplexed address/data bus
Address Latch Enable input
Write Input
High Byte Enable Input
Read Input
16·bit bidirectional input/output port
Output only pin, or UAO input in UPI mode
Output only pin, or WRRDY output in UPI
mode
4-93
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PC8
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ADll
PC10
AD10
PCll
AD9
PC12
ADS
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PC13
AD7
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PC15
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AD5
PB15
AD4
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PB10
ADl
PA15
ADO
a.
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51
AD3
AD2
PBll
PA14
RESET
PA13
RSTOUT
PA12
PAO
PAll
GND
TL/DD/9122-7
Top View
Order Number HPC46900V
See NS Package Number V68A
Ports PA, PB, and PC
The highly flexible PA, PB, and PC ports are similarly structured. Port PA (see Figure 6) and Port PC (see Figure 7)
consist of a data register and a direction register. Port PB
(see Figure 8) has an alternate function register in addition
to the data and direction registers. All the control registers
are read/write registers.
The associated direction registers allow the port pins to be
individually programmed as inputs or outputs. A port pin is
selected as an input and placed in a TRI-STATE mode by
clearing the corresponding bit in the direction register.
A write operation to a port pin configured as an input causes
the value to be written into the data register. A read operation returns the value detected at the pin. Writing to a port
pin configured as an output writes the value into the data
register and causes the pin to output the same value. Reading a port pin configured as an output returns the value held
in the data register.
Primary and secondary functions are multiplexed onto Port
PB through the alternate function register (BFUN). The secondary functions are enabled by setting the corresponding
bits in the BFUN register.
READ PORT PA
TL/DD/9122-B
FIGURE 6. Port PA I/O Structure
4-94
Ports PA, PB, and PC
::a::::
"'C
o
....
(Continued)
0)
CD
o
o
.......
::a::::
"'C
oN
0)
CD
o
o
.......
::a::::
"'C
oW
0)
CD
o
o
.......
::a::::
"'C
o
~
0)
CD
o
o
READ PORT PC
TLlDD/9122-9
FIGURE 7. Port PC Structure: 1/0 and Latched Address
READ DIR PB
D
A
T
A
WRITE DIR PB
•
B
U
S
READ PORT PB
WRITE BrUN
READ BrUN
TL/DD/9122-10
FIGURE 8. Structure of Port PB Pins PB10, PB11, PB12, PB15
4-95
I
o
o
0')
U)
"III:t'
(.)
Operating Modes
TABLE I. PEARL Functions
a.
::J:
......
o
o0')
Port Functions
Inputs
PB11
PB12
PB15
PCO-PC15
U)
C")
PEARL 0-1/0
0
0
0
X
1/0
1/0
Out
Out
Out
Out
ADDR
(.)
a.
PEARL O-UPI (16)
0
0
1
0
UPI BUS
UPI BUS
UAO
WRRDY·
Out
RDRDY·
ADDR
::J:
......
o
o0')
PEARL O-UPI (8)
0
0
1
1
UPI BUS
1/0
UAO
WRRDY·
Out
RDRDY·
ADDR
PEARL 1
0
1
0
X
1/0
1/0
Out
Out
Out
Out
1/0
U)
PEARL 2
1
0
0
X
1/0
1/0
Out
Out
Out
Out
1/0
PEARL 3
1
1
0
X
1/0
1/0
Out
Out
Out
Out
1/0
N
(.)
a.
::J:
......
o
o0')
U)
.....
(.)
a.
::I:
PEARL Mode
SEL1
SELO
UPIEN
80R16
PAO-PA7
PA8-PA15
PB10
'If corresponding bit in BFUN Register is set.
The two inputs, SELO and SEL 1, along with the bits UPIEN
and UPI8BIT in the UPIC register determine the function of
the PEARL as described below and summarized in Table 1.
put from the multiplexed addressldata bus, ADO-AD1S.
The host HPC must have memory in the address range
200-FFFF addressed through the PEARL. When using a
PEARL O-UPI with an HPC, the HPC must be in the Expanded ROM less mode (EA bit in the PSW = "1", EXM =
"1") as shown in Figure 10.
When interfacing the PEARL to an HPC microcontroller, the
microcontroller must be in 16-bit mode.
PEARL 0-110
In this mode, ports PA and PB are memory mapped I/O,
and port PC is a latched address output from the multiplexed address/data bus, ADO-AD1S. The host HPC must
be either Expanded Normal mode (EA bit in the PSW =
"1", EXM = "0"), or Expanded ROM less mode (EA bit in
the PSW = "1", EXM = "1". Figure 9 shows a HPC in
Expanded ROMless mode with the address range
200-FFFF being addressed through the PEARL.
Universal Peripheral Interface
The Universal Peripheral Interface (UPI) allows a system
with a HPC160xx and a PEARL 0 configured for UPI operation to be used as an intelligent peripheral to another processor.
The interface consists of a UPI Data Bus (Port PAl, a Read
Strobe (URD), a Write Strobe (UWR), a Read Ready Line
(RDRDY), a Write Ready Line (WRRDY) and one address
input (UAO). The UPI Data Bus can be either eight or sixteen
bits wide. The URD and UWR inputs, and the RDRDY and
WRRDY outputs may be used to interrupt the host processor as shown in Figure 10.
PEARLo-UPI
Port PA is either a 16-bit UPI data bus, or an 8-bit UPI data
bus on the lower bytes and 1/0 on the upper bytes. Of the
four PB pins, three are UPI control signals, and one is a
programmable output. The PC port is a latched address out-
The registers controlling the UPI logic are the Input Buffer
(IBUF), Output Buffer (OBUF) and a Control Register
(UPIC).
00-015
ViR
HBE
Or_
!f
cs
EXM
~ ~
AO-A15
...
, .
r
PRLSEL
Aoo-A015
ill
ViR
HBE
Rii
Bl0
HPC16083
MEMORY
SYSTEM
Bll
B12
B15
1:f
AO-A15
---.J'
PCO-PC15
1
PAO- PA15 . . . RAO-RA15
PB10
~PB10
HPC16900 PBll ~PBll
(PrARLD-I/O) PB12 ~PB12
PB15
~PB15
URi)
UWR
SEll
SELO
TLIOO/9122-11
FIGURE 9. PEARL 0-1/0 with External Memory
4-96
:J:
"'tJ
Operating Modes (Continued)
HPC Emulation
Refer to the HPC Users' Manual for a detailed functional
description of the UPI mode.
A system using a PEARL configured as a PEARL 0-1/0, a
HPC in Expanded ROM less mode, and an EPROM (Figure
9) can be considered a pseudo emulator of a HPC in Single
Chip Normal mode. In this configuration, the PEARL recreates the lID functionality of HPC's Port A and four bits of
Port B which are used to address off chip memory. The only
difference between the system shown in Figure 9 and a
mask programmed HPC in Single Chip Normal mode is that
the registers associated with Port PA and Port PB of the
PEARL are at different locations than the registers of the
HPC's Port A and Port B (see PEARL Register Address Assignments).
PEARL 1,2,3
Each one of these configurations provides memory mapped
lID on all three ports. Ports PA and PC each provide 16 bits
of lID, while PB is output only. Figure 11 shows a PEARL 1
and a PEARL 2 configured as port expanders. When using a
PEARL 1, 2, or 3 with a HPC, the HPC may be configured in
the Expanded Normal mode or the Expanded ROMless
mode.
o
""'"
0)
U)
o
o
......
:J:
"'tJ
o
N
0)
U)
o
o
......
:J:
"'tJ
o
w
0)
U)
o
o
......
..---------400-015
...---------.IWR
:J:
IolE\jORY
SYST£1ol
...---------.IHaE
"'tJ
o
0l:Io
Vee
0)
U)
o
o
1 4 - - - - - - " ' O A T A BUS
HPC16083
B10 J---I-+-I-.I
I+------~ADOR BIT
B11t--.............1
B12t--_........1
1-------+IINT2
1-------+IINT1
HOST
SYSITIol
B 1 5 t - - - _••
TL/DD/9122-12
FIGURE 10. PEARL o-UPI (16-blt) with External Memory
PCO- PCI5
pco- PCI5
PAO- PAI5
PAO- PAI5
PBIO
HPCI6900
(PEARL I)
PBII
PBI2
PBI5
PCO-PCI5
PAO- PAI5
BIO I---+-If-I-I~-'I
HPCI6083
PBIO
BII .....---4*'1f--.1
BI2
HBE
BI5
Rii
HPCI6900
(PEARL 2)
PBII
PBI2
PBIS
URD
UWR
SELl
SELO
TL/DD/9122-13
FIGURE 11. PEARL 1 and PEARL 2 Configured as Port Expanders
4-97
C) r---------------------------------------------------------------------------------------~
C)
0)
CD
~
PRLSEL Operation
o
D.
PCO-PCIS
::J:
......
C)
PAO-PAIS
C)
0)
PBIO
CD
PB11
C")
oD.
PBl2
::J:
PBIS
......
C)
C)
0)
CD
C'I
oD.
::J:
......
C)
C)
0)
CD
'P"
o
D.
::J:
Vee
EXt.I
AO-AISI4!"+I~_~
HPCl6083
BIS t-----4I...-+1
TL/OO/9122-14
FIGURE 12. PEARL 0 and PEARL 1 with External Memory
This configuration, however, will not emulate a HPC in Expanded Normal mode since the PEARL's Port PA and PB
will not emulate the address/data bus function.
Initialization
Immediately following RESET the PEARL will be in the following state:
The PRLSEL output is asserted when the address presented on the address data bus (ADO-AD15) corresponds to a
register in the PEARL's address block (see PEARL Register
Address Assignments). For example, an HPC16900 configured as a PEARL 0 will assert PRLSEL only if the address is
within the PEARL 0 address block. Likewise, a PEARL 1 will
assert its PRLSEL when the address is within the PEARL 1
address block.
I/O AND OUTPUT ONLY PINS
ADO-15
TRI-STATE
PB10, 11, 12, 15 TRI-STATE
PAO-PA15
PCO-PC15
TRI-STATE
TRI-STATE if PEARL 1, PEARL 2, or
PEARL 3
PEARL 0: Power on Reset-indeterminate. Otherwise, asserted, bits 0-15 of
most recent latched address.
Therefore, when using multiple PEARLs in a system, the
PRLSEL outputs must be ORed together as in Figure 12. In
this system, the PEARL addresses overlap those of the
Memory System, and the ORed PRLSEL signal is used to
deselect the outputs of the Memory System to avoid bus
contention.
PRLSEL
PRLSEL is an output derived from the internal address decode logic, which decodes the ADO-AD15 inputs while ALE
is high. During the time ALE is high, the state of PRLSEL is
indeterminate.
Power on Reset-indeterminate until the
first ALE will put PRLSEL in a known state
based on the first address output.
Otherwise, asserted (may be high or low).
If the address of one of the PEARL's registers was the most recent address received by the PEARL, then PRLSEL will
be high, otherwise PRLSEL will be low.
On the falling edge of ALE, the decoding is stopped, and
PRLSEL is latched to a valid state. This state is guaranteed
to be valid until ALE goes high during the next address cycle.
4-98
:J:
"U
Initialization (Continued)
INTERNAL REGISTERS AND LATCHES
814,815
PEARL 1 Port PA Direction
Port PA Data Register
Indeterminate
816,817
PEARL 1 Port PB Data (4 bits only)
Port PA Direction Register
Cleared
818,819
PEARL 1 Port PB Direction (4 bits only)
Port PB Data Register
Indeterminate
81A,81B
PEARL 1 Port PC Data
Port PB Direction Register
Cleared
81C,81D
PEARL 1 Port PC Direction
Port PB Function Register
Cleared
81E,81F
Reserved
Port PC Data Register
Indeterminate
820,821
Reserved
Port PC Direction Register
Cleared
822,823
PEARL 2 Port PA Data
UPIENB Latch
Cleared
824,825
PEARL 2 Port PA Direction
UPI8BIT
Cleared
826,827
PEARL 2 Port PB Data (4 bits only)
PEARL REGISTER ADDRESS ASSIGNMENTS
828,829
PEARL 2 Port PB Direction (4 bits only)
The following registers have been assigned to the block of
addresses from hex 800 to 83F:
82A,82B
PEARL 2 Port PC Data
82C,82D
PEARL 2 Port PC Direction
82E,82F
Reserved
830,831
Reserved
832,833
PEARL 3 Port PA Data
800,801
Reserved
802,803
PEARL 0 Port PA Data/UPI Output Buffer
804,805
PEARL 0 Port PA Direction/UPllnput Buffer
806,807
PEARL 0 Port PB Data (4 bits only)
808,809
PEARL 0 Port PB Direction (4 bits only)
80A,80B
PEARL 0 Port PC Data
80C,80D
PEARL 0 Port PC Direction
80E,80F
Reserved
810,811
Reserved
812,813
PEARL 1 Port PA Data
834,835
PEARL 3 Port PA Direction
836,837
PEARL 3 Port PB Data (4 bits only)
838,839
PEARL 3 Port PB Direction (4 bits only)
83A,83B
PEARL 3 Port PC Data
83C,83D
PEARL 3 Port PC Direction
83E,83F
Reserved
When the PEARL is configured as a PEARL O-UPI, these
register locations are used in UPI operation.
UPIC is accessed at E7, E6
BFUN is accessed at F5, F4
Ordering Information
The following chart explains how the various options are designated in the part number.
HPC16900V
LPaCkage Type
V Plastic Leaded Chip Carrier (PLCC)
Temperature
4 Commercial (OOC TO +70 0 C)
3 =Industrial
(-40OC TO +85OC)
2 Automotive (-40OC TO + 105 0 C)
1 =Military
(-55OC TO +125OC)
L
=
=
=
4-99
TL/DD/9122-15
0
......
en
co
0
0
.......
:J:
"U
0I\)
en
co
0
0
.......
:J:
"U
0
w
en
co
0
0
.......
:J:
"U
0
~
en
co
0
0
Section 5
HPC Applications
Section 5 Contents
AN-474 HPC MICROWIRE/PLUS Master-Slave Handshaking Protocol....................
AN-484 Interfacing Analog Audio Bandwidth Signals to the HPC . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-485 Digital Filtering Using the HPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-486 A Floating Point Package for the HPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-487 A Radix 2 FFT Program for the HPC ............ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-497 Expanding the HPC Address Space...........................................
AN-510 Assembly Language Programming for the HPC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5·2
5-3
5-11
5-21
5-36
5-89
5-114
5-125
National Semiconductor
Application Note 474
Richard Lazovick
HPC MICROWIRE/PLUSTM
Master-Slave Handshaking
Protocol
INTRODUCTION
This applications note describes how to use National Semiconductor's MICROWIRE/PLUS to communicate between
two members of the HPC family of microcontrollers, and will
discuss the implications of adding other MICROWIRETM peripherals. MICROWIRE/PLUS (,...WIRE) may be effectively
used to communicate between chips, such as in Small Area
Networks (SANs). Possible applications range from setting
up a communications network within an automobile to home
security systems. Among the standard MICROWIRE peripherals available are display drivers (LCD, VF, LED), memories (RAM, EEPROM), AID converters, and frequency generators/timers. Each MICROWIRE peripheral requires its
own handshaking protocol, however the HPC's MICROWIRE is flexible enough to work with any peripheral and
allows you to define your own handshaking protocol when
having two HPC family members communicate.
high speed two way serial communications between a master processor and one or more slave processors or peripherals. MICROWIRE/PLUS uses only three wires plus chip
selects, therefore it saves on intricate bus routing and does
not waste a-bit ports. Figure 1 shows the block diagram of a
sample application using two HPC family members and an
a-bit AID peripheral to monitor and control certain environmental conditions within a system.
MICROWIRE/PLUS has an a-bit parallel-loaded, serial shift
register (SIO) using SI as the serial input and SO as the
serial output. The contents of the SIO register may be accessed through any of the memory access instructions. SK
is the clock for the SIO register (see Figure 2). The SK clock
signal can be provided by an internal or external source.
The internal clock rate is programmable by the DIVBY register. Data to be transmitted from the SIO register is shifted
out on the falling edge of the SK clock. Serial data on the SI
pin is latched in on the rising edge of the SK clock (see
Figure 3 ,...WIRE Timing).
MICROWIRE
MICROWIRE/PLUS is an extension of National Semiconductor's MICROWIRE communications interface. It allows
12
B4
SYSTEIol
I/o
A
t\.
'4
II'
)
(IolAIN
CONSOLE)
HPC
(IolASTER)
B7
SI
SO
SK
B4
12
---
.;.
SYSTEIol
I/o
HPC
(SLAVE)
SO
I
•
I
I
I
I
I
I
I
I
I
I
I\.
'4
I'
(CONTROLLED
DEVICES)
SI
I
I
I
I
I
I
A
SK
P-------.I
.--~ISK
I
I
: • - - - ~: SI PERIPHERAL:¢:=
• - - - - - , SO (COP438 I
8-BIT A/D) I
I
I
I
SENSOR
• - - - - - - ~: CS
: INPUTS
._-----_.
FIGURE 1. HPC ,...WIRE Block Diagram
(Environmental Control System)
5-3
TLIOO/9140-1
~----------------~SO
I+--SI
'----+SK
TLIDD/9140-2
Note: The most significant bit is shifted out first. The SO pin reflects the contents of the MSB in the SID register.
FIGURE 2. MICROWIRE/PLUS Block Diagram
SK[ __________________
________
~
,
~t
~__________
J
SI [
BIT 71N· (MSB)
n
LD _ _--'
SIO
DONE
..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
~
______________________
~r_
TLIDD/9140-3
Note: The first bit of every eight bits in the SID register being shifted out will have a longer duration then the other bits. This results from the hardware
implementation used for MICROWIRE.
• This bit becomes valid immediately when the transmitting device loads its SID register.
t Arrows indicate points at which SI is sampled.
FIGURE 3. /-LWIRE Timing
5·4
master, resetting the bit will make it a slave. For the master,
the DIVBY register has to be initialized to set the appropriate SK frequency (see Table I.). For example if the crystal
frequency is 16 MHz and an SK frequency of 1 MHz is desired, load the least significant nibble of the DIVBY register
with 2 (16 MHz/16 = 1 MHz).
A /-LWDONE flag in the IRPD (Interrupt Pending) register
indicates when the data shift is completed.
The HPC can enter the MICROWIRE/PLUS mode as a
master or a slave. The /-LWMODE control bit in the IRCD
(Interrupt Condition) register determines whether the HPC is
a master or slave. The shift clock is generated internally
when the HPC is configured as a master. An externally generated shift clock on the SK pin is used when the HPC is
configured as a slave. When the HPC is a master, the
DIVBY register allows the SK clock frequency to be programmed in 14 selectable steps from 122 Hz to 1 MHz
when CKI is 16 MHz (see Table I).
For a summary of the register and pin configurations for the
master and slave modes see Table II.
TABLE I. HPC /-LWIRE OIVBY Register
/-LWIRE SK Divisor
LSB
CLOCK
o
o
o
1
o
not allowed
not recommended·
CKI/16
CKI/32
CKI/64
CKI/128
CKI/256
CKII512
CKI/1024
CKI/2048
CKI/4096
CKI/8192
CKI/16384
CKI/32768
CKI/65536
CKI/131072
MSB
HOW TO USE MICROWIRE/PLUS
o
To use MICROWIRE, start by setting up the B port appropriately for the MICROWIRE functions. The SO and SK functions are multiplexed onto Port B pins B5 and B6 respectively. For the master, set bits 5 and 6 in the DIRB register
(direction register for Port B) to set SO and SK as outputs.
For the slave, set bit 5 and reset bit 6 in the DIRB register to
set SO as an output and SK as an input. The BFUN register
(Port B function register) is used to set SO and SK as alternate functions in the master and only SO as an alternate
function in the slave. The MICROWIRE/PLUS mode can be
enabled or disabled any time under program control. This is
done through the BFUN register. Placing a "1" in the corresponding bit location causes the alternate function to be
activated, a "0" causes the alternate function to be disabled. It is good practice to initialize the output pins by setting PORTB (Port B data register) to a known state.
o
o
o
o
o
o
o
1
1
1
1
1
o
o
o
1
1
1
1
o
1
1
o
o
o
1
1
1
o
o
o
o
1
1
o
1
1
o
o
1
1
1
1
o
1
1
1
1
The SI function is multiplexed onto Port I pin 15. This pin is
always an input and the SI function is automatically selected
when in the MICROWIRE mode. Setting the /-LWMODE control bit, bit 1, in the IRCD register will enable the part to be a
o
o
o
o
1
1
1
1
o
1
'Thls option uses timer T3 output, but does not generate a square wave.
(See HPC users manual for more details.)
TABLE II./-LWIRE Register and Pin Conditions for Master and Slave Operation
Operation
/-LWMODE
bit
BFUN
B5
BFUN
B6
DIRB
B5
DIRB
B6
PIN
B5
PIN
B6
PIN
15
MICROWIRE
Master
1
1
1
1
1
SO
INT.
SK
SI
MICROWIRE
Master
1
1
1
0
1
TRISTATE
Z
APPENDIX A (Continued)
GET NEW SAMPLE, OUTPUT
COMPUTED DATA.
TAKE CARE OF CODEC INVERSION.
; FORM MU-LAW TO LINEAR
; TABLE ADDRESS.
; GET LINEAR VALUE
LD A, M(X+)
X A, K
; A BYTE AT A TIME.
LD A, M(X)
LD H(K), L(A)
LD A, K
RET
YCOMP:
THIS SUBROUTINE COMPUTES THE OUTPUT SAMPLE Y(K) •
THE INPUT SAMPLE X(K) IS INPUT IN REG. A.
THE OUTPUT IS RETURNED IN REG. A.
5·29
U) r---------------------------------------------------------------------------------------~
CD
III:t'
:Z
c(
APPENDIX A (Continued)
Listing of Code for the Program FILTER (Continued)
NATIONAL SEMICONDUCTOR CORPORATION
PAGE:
HPC CROSS ASSEMBLER, REV:C, 30 JUL 86
FILTER
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
F325 AC0406
7
LD NCNT, NSTG
; COpy THE NUMBER OF STAGES TO
; NCNT.
ADD A, W(TlADDR)
ST A, W(MOADDR)
LD B, AOADDR
JSR SMULT
ADD A, W(T2ADDR)
;
;
;
;
;
DECSZ NCNT
JMP YMORE
; DONE ALL STAGES?
; NO GO DO SOME MORE.
YLOOP:
F328
F32B
F32E
F331
F333
AD1CF8
AD16AB
ACOCCC
3522
AD1EF8
F336 AA06
F338 941B
F33A
F33C
F33E
F33F
F340
F341
F342
F346
F34A
F34E
F352
F354
R
AB02
A804
05
E7
01
04
AOC81CF8
AOC816F8
AOC80CF8
AOC81EF8
A802
3C
ST A, YOFK
LD A, NSTG
DEC A
SHL A
COMP A
INC A
ADD TlADDR,
ADD MOADDR,
ADD AOADDR,
ADD T2ADDR,
LD A, YOFK
RET
A So: X(K) + Tl.
M(K) So: X(K) + Tl.
B S; ADDR(AO).
A So: AO*M(K).
A So: AO*M(K) + T2.
; GET HERE MEANS ALL STAGES DONE.
; SAVE TEMPORARILY.
A
A
A
A
;
;
;
;
;
A So: -2* (NSTG-l) •
RESTORE T1ADDR.
RESTORE MOADDR.
RESTORE AOADDR.
RESTORE T2ADDR.
; A So: Y(K).
; PREPARE FOR NEXT STAGE ITERATION.
YMORE:
F355
F359
F35D
F361
F365
82021CF8
820216F8
82020CF8
82021EF8
953D
ADD
ADD
ADD
ADD
JMP
TlADDR,
MOADDR,
AOADDR,
T2ADDR,
YLOOP
02
02
02
02
THIS SUBROUTINE CONVERTS THE 16 BIT OUTPUT VALUE TO
; 8 BIT MU-LAW.
OUTPUT:
F367
F36A
F36B
F36C
F36D
F370
F371
96D41F
E7
06
45
96D40F
01
04
RESET IRCD.7
SHL A
IFN C
JP OPOS
SET IRCD.7
COMP A
INC A
SIGN BIT TO C.
IS IT POSITIVE?
; NEGATIVE, SO TAKE 2'S
; COMPLEMENT.
; OPOS:
F372 B80108
F375 9107
ADD A, 0108
LD K, 07
; ADD BIAS.
; SET UP COUNTER.
-~,
5·30
APPENDIX A (Continued)
LIsting of Code for the Program FILTER (Continued)
NATIONAL SEMICONDUCTOR CORPORATION
PAGE: 8
HPC CROSS ASSEMBLER, REV:C, 30 JUL 86
FILTER
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
ALIGN:
F377
F378
F379
F37A
F37C
F37D
E7
07
44
AACA
65
E7
SHL A
IF C
JP ODONE
DECSZ K
JP ALIGN
SHL A
; LOOP AND LOCATE MS 1 BIT.
; FOUND MS 1 BIT.
; HAS TO BE 1 IN C NOW.
ODONE:
F37E
F380
F381
F382
F383
F384
F386
F387
F389
F38A
F38C
F38F
F392
F395
F396
F398
AECA
E7
E7
E7
E7
AECC
00
88CB
3B
990F
96CCFA
96D417
96C80F
01
8BOO
3C
X R, K
SHL A
SHL A
SHL A
SHL A
X A, B
CLR A
LD A, H(K)
SWAP A
AND A, OF
OR A, B
IF IRCD.7
SET A.7
COMP A
ST A, YOUT
RET
COUNTER VALUE IN BITS 4-6.
THIS SUBROUTINE UPDATES M(K-1) AND M(K-2) FOR THE NEXT SAMPLE.
F399 AC1ACC
F39C AC04CA
F39F AC18CE
LD B, M2ADDR
LD K, NSTG
LD X, M1ADDR
; B ~ ADDR(M2),
; K ~ NSTG.
; X ~ ADDR(M1).
LD A, W(X+)
XS A, W(B+)
NOP
DECSZ K
JP DLYLP1
; A ~ M(K-1).
; M(K-2) ~ M(K-1).
LD B, M1ADDR
LD K, NSTG
LD X, MOADDR
; B ~ ADDR(M1),
; K ~ NSTG.
; X ~ ADDR(MO).
LD A, W(X+)
XS A, W(B+)
NOP
DECSZ K
JP DLYLP2
RET
; A ~ M(K).
; M(K-1) ~ M(K).
DLYLP1:
F3A2
F3A3
F3A4
F3A5
F3A7
FO
E1
40
AACA
65
F3A8 AC18CC
F3AB AC04CA
F3AE AC16CE
DLYLP2:
F3B1
F3B2
F3B3
F3B4
F3B6
F3B7
FO
E1
40
AACA
65
3C
PRECOMP:
; THIS SUBROUTINE PRECOMPUTES T1 AND T2 BEFORE THE NEXT INPUT
5-31
~
co
~
:2:
z
APPENDIX A (Continued)
=4769
=1378
INPUT
FILE C:FILTER.MAC
LISTING FILE C:FILTER.PRN
OBJECT FILE C:FILTER.LM
5·35
.
CD
CO
"II:t'
Z
c:(
A Floating Point Package
for the HPC
National Semiconductor
Application Note 486
Ashok Krishnamurthy
INTRODUCTION
mentation does) then since the MSB of the mantissa is always 1, it need not be explicitly represented. This is as
specified in the IEEE/ ANSI standard.
This report describes the implementation of a Single Precision Floating Point Arithmetic package for the National
Semiconductor HPC microcontroller. The package is based
upon the IEEE Standard for Binary Floating-Point Arithmetic
(ANSI/IEEE Std 754-1985). However, the package is not a
conforming implementation of the standard. The differences
between the HPC implementation and the standard are described later in this report.
Given the values of S , E and F, the value of the SP FLP
number is obtained as follows.
If 0 < E < 255, then the FLP number is (-1)
AS*1.F*2A(E -127).
If E = 0, then the value of the FLP number is
o.
If E = 255, then the FLP number is not a valid number
(NAN).
The following single precision (SP) operations have been
implemented in the package.
The above format for binary SP FLP numbers provides for
the representation of numbers in the range -3.4*10A38 to
-1.75*10A-38, 0, and 1.75*10A-38 to 3.4*10A38. The accuracy is between 7 and 8 decimal digits.
(1) FADD. Addition of two SP floating point (FLP) numbers.
(2) FSUB. Subtraction of two SP FLP numbers.
(3) FMULT. Multiplication of two SP FLP numbers.
(4) FDIV. Division of two SP FLP numbers.
DIFFERENCES BETWEEN THE IMPLEMENTATION AND
THE IEEE/ANSI STANDARD
(5) ATOF. Convert an ASCII string representing a decimal
FLP number to a binary SP FLP number.
The IEEE/ ANSI standard specifies a comprehensive list of
operations and representations for FLP numbers. Since an
implementation that fully conforms to this standard would
lead to an excessive amount of overhead, a number of the
features in the standard were dropped. This section describes the differences between the implemented package
and the standard.
(6) FTOA. Convert a binary SP FLP number to a decimal
FLP number and output the decimal FLP number
as an ASCII string.
The report is organized as follows. The next section discusses the representation of FLP numbers. Then, the differences between the HPC implementation and the IEEE/
ANSI standard are described. This is followed by a description of the algorithms used in the computations. Appendix A
is a User's Manual for the package, Appendix B describes
the test data for the package and Appendix C is a listing of
the code.
1. Omission of -0. The IEEE/ANSI standard requires that
both + and - zero be represented, and arithmetic carried out using both. The implementation does not represent - o. Only + 0 is represented and arithmetic is carried out with +0 only.
Note that this report assumes that the reader is familiar with
the IEEE/ ANSI Binary Floating-Point Standard. Please refer
to this document for an explanation of the terms used here.
2. Omission of Infinity Arithmetic. The IEEE/ ANSI standard
provides for the representation of plus and minus Infinity,
and requires that valid arithmetic operations be carried
out on Infinity. The HPC implementation does not support
this.
REPRESENTATION OF FLOATING POINT NUMBERS
The specification of a binary floating point number involves
two parts: a mantissa and an exponent. The mantissa is a
signed fixed point number and the exponent is a signed
integer. The IEEE/ ANSI standard specifies that a SP FLP
number shall be represented in 32 bits as shown in Figure 1.
1
8
23
S
E
F
FIGURE 1
3. Omission of Quiet NaN. The IEEE/ ANSI standard provides for both quiet and signalling NaNs. The HPC implementation provides for signalling NaNs only. A signalling
NaN can be produced as the result of overflow during an
arithmetic operation. If the NaN is passed as input to further floating point routines, then these routines will produce another NaN as output. The routines will also set
the Invalid Operation flag, and call the user floating point
error trap routine at address FPTRAP.
The significance of each of these fields is as follows:
1. S-this 1-bit field is the sign of the mantissa. S = 0
means that the number is positive, while S = 1 means
that it is negative.
2. E-this is the 8·bit exponent field. The exponent is represented as a biased value with a bias of 127-decimal.
3. F-this is the 23-bit mantissa field. For normalized FLP
numbers (see below), a MSB of 1 is assumed and not
represented. Thus, for normalized numbers, the value of
the mantissa is 1.F. This provides an effective precision
of 24 bits for the mantissa.
Normalized FLP number: A binary FLP number is said to be
normalized if the value of the MSB of the mantissa is 1.
Normalization is important and useful because it provides
maximum precision in the representation of the number. If
we deal with normalized numbers only (as the HPC imple-
4. Omission of denormalized numbers. Denormalized numbers are FLP numbers with a biased exponent, E of zero
and a non zero mantissa F. Such denormalized numbers
are useful in providing gradual underflow to zero. Denormalized numbers are not represented or used in the HPC
implementation. Instead, if the result of a computation
cannot be represented as a normalized number within the
allowable exponent range, then an underflow is signaled,
the result is set to zero, and the user floating point error
trap routine at address FPTRAP is called.
5. Omission of the Inexact Result exception. The IEEE/
ANSI standard requires that an Inexact Result exception
be signaled when the rounded result of an operation is
not exact, or it overflows without an overflow trap. This
feature is not provided in the HPC implementation.
5-36
6. Biased Rounding to Nearest. The IEEEI ANSI standard
requires that rounding to nearest be provided as the default rounding mode. Further, the rounding is required to
be unbiased. The HPC implementation provides biased
rounding to nearest only. An example will help clarify this.
(iii) Exponent Underflow. This occurs if the result of a
computation is such that its exponent is 0 or less.
(iv) Divide-by·zero. This exception occurs if the FDIV routine is called with F2 being zero.
The package signals exceptions in two ways. First a word
at address FPERWD is maintained that records the history of these exception conditions. Bits 0-3 of this word are
used for this purpose.
Suppose the result of an operation is .b1 b2b3XXX and
needs to be rounded to 3 binary digits. Then if XXX is
OYY, the round to nearest result is .b1 b2b3. If XXX is
1YY, with at least one of the Y's being 1, then the result is
.b1 b2b3 + 0.001. Finally if XXX is 100, it is a tie situation.
In such a case, the IEEEI ANSI standard requires that the
rounded result be such that its LSB is O. The HPC implementation, on the other hand, will round the result in such
a case to .b1 b2b3 + 0.001.
Bit O-Set on Exponent Overflow.
Bit 1-Set on Exponent Underflow.
Bit 2-Set on Illegal Operand.
Bit 3-8et on Divide-by-zero.
These bits are never cleared by the floating point package, and can be examined by the user software to determine the exception conditions that occurred during the
course of a computation. It is the responsibility of the user
software to initialize this word before calling any of the
floating point routines.
The second method that the package uses to signal exceptions is to call a user floating point exception handler
subroutine whenever an exception occurs. The corresponding exception bit in FPERWD is set before calling
the handler. The starting address of the handler should
be defined by the symbol FPTRAP.
3. Unpacked Floating Point Format. The IEEEI ANSI standard floating point format described earlier is very cumbersome to deal with during computation. This is primarily
because of the splitting of the mantissa between the two
words. The subroutines in the package unpack the input
FLP numbers into an internal representation, do the computations using this representation, and finally pack the
result into the IEEE format before return to the calling
program. The unpacking is done by the subroutine FUNPAK and the packing by the subroutine FPAK. The unpacked format consists of 3 words and is organized as
follows.
DESCRIPTION OF ALGORITHMS
1. General Considerations. The HPC implementation of
the SP floating point package consists of a series of subroutines. The subroutines have been designed to be compatible with the CCHPC C Cross Compiler. They have,
however, not been tested with the CCHPC Cross Compiler.
The Arithmetic subroutines that compute F1 op F2
(where op is +, -, • or I) expect that F1 and F2 are
input in the IEEE format. Each of F1 and F2 consists of
two 16-bit words organized as follows.
Fn-HI: S EXP 7 MS bits of F
Fn-LO:
16 LS bits of F
In the above, S is the sign of the mantissa, EXP is the
biased exponent, and F is the mantissa.
On input it is assumed that F1-HI is in register K, F1-LO
is in the accumulator A, and F2-HI and F2-LO are on the
stack just below the return address Le., F2-HI is at
W(SP-4) and F2-LO is at W(SP·6). The result, C, is also
returned in IEEE format with C-HI in register K and C-LO
in the accumulator A.
The two Format Conversion routines, ATOF and FTOA
expect that on entry, register B contains the address of
the start of the ASCII byte string representing the decimal
FLP number. ATOF reads the byte string starting from
this address. Note that the string must be terminated with
a null byte. The binary floating point number is returned in
registers K and A. FTOA, on the other hand, writes the
decimal FLP string starting from the address in register B
on entry. A terminating null byte is also output. Also,
FTOA expects that the binary FLP number to be converted is in registers K and A on entry.
Fn·EXP.Fn-SIGN 8 bits biased sign (extended to
8 bits)
exponent
Fn·HI
MS 16 bits of mantissa
(implicit 1 is present as MSB)
Fn·LO
LS 8 bits of
mantissa
Eight
Zeros
Since all computations are carried out in this format, note
that the result is actually known to 32 bits. This 32-bit
mantissa is rounded to 24 bits before being packed to the
IEEE format.
Most of the storage required by the subroutines is obtained from the stack. Two additional words of storage in
the base page are also used. The first is W(O), and is
referenced in the subroutines as W(TMP1). The second
word of storage can be anywhere in the base page and is
used to store the sticky flags used to signal floating point
exceptions. This is referenced in the subroutines as
W(FPERWD). Thus any user program that uses the floating point package needs to have the symbols TMP1 and
FPERWD defined appropriately.
4. Algorithm Description. All the arithmetic algorithms first
check for the easy cases when either F1 or F2 is zero or
a NaN. The result in these cases is immediately available.
The description of the algorithms below is for those cases
when neither F1 nor F2 is zero or a NaN. Also, in order to
keep the algorithm description simple, the check for un·
derflow/overflow at the various stages is not shown. The
documentation in the program, the descriptions given below, and the theory as described in the references should
allow these programs to be easily maintained.
(i) FADD.
2. Exception Handling. The following types of exception
can occur during the course of a computation.
The processing steps are as follows:
(i) Invalid Operand. This exception occurs if one of the
input operands is a NaN.
1. Compare F1-EXP and F2-EXP. Let the difference
be D. Shift right the mantissa (Fn·HI.Fn·LO, n = 1
or 2) of the FLP number with the smaller exponent
D times. Let the numbers after this step be F1EXP.F1-SIGN, F1-HI, F1-LO and F2-EXP.F2-SIGN,
(ii) Exponent Overflow. This occurs if the result of a computation is such that its exponent has a biased value
of 255 or more.
5-37
»
z
I
oI::ao
CD
0')
CD
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~
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and must be present to terminate
the string.
5. FPAK.MAC
The floating point number represented by the above
string is returned by ATOF in IEEE format in registers K
and A.
3. The format conversion routine FTOA expects the floating
point number input to be in registers K and A in the IEEE
format. Register B is expected to contain the starting address of a 17 byte portion of memory where the output
string will be stored.
6. FPTRAP.MAC
7. ROUND.MAC
8. BFMUL.MAC
9. ISIOK.MAC
10. MUL1O.MAC
11.ATOF.MAC
12. FTOA.MAC
4. Three global symbols need to be defined in the user program before assembling the user program and any included floating point package files. These symbols are:
(i) TMP1 which must be set to O. The package uses
W(TMP1) for temporary storage.
13. FADD.MAC
14. FMULT.MAC
15. FDIV.MAC
The first 7 files are general utility routines that are used by
all the Arithmetic and Format Conversion subroutines. The
next 3 files, BFMUL.MAC, ISIOK.MAC and MUL1O.MAC are
used only by the Format Conversion subroutines, ATOF and
FTOA. Depending on the functions being used in the user
program, only the necessary files need be included.
(ii) FPERWD which must be set to an address in the base
page. The package signals floating point exceptions
using W(FPERWD). This is described below.
(iii) FPTRAP which must be set to the address of the start
of a user floating point exception handler. Again this is
described below.
INTERFACE WITH USER PROGRAMS
1. All the Arithmetic routines expect the input to be in the
IEEE Single Precision format. This format requires 2
words for the storage of each floating point number. If the
required arithmetic operation is FlopF2, where op is +,
-, * or I, then the routines expect that F1 is available in
registers K and A on entry, with the high half in K. Also,
the two words of F2 are expected to be on the stack. If
SP is the stack pointer on entry into one of the Arithmetic
function subroutines, then the high word of F2 should be
at W(SP-4) and the low word at W(SP-6). The result of the
Arithmetic operation is returned in IEEE format in registers K and A, with the high word in K.
FLOATING POINT EXCEPTS
The package maintains a history of floating point exceptions
in the 4 least significant bits of the word W(FPERWD). The
value of the symbol FPERWD should be defined by the user
program, and should be an address in the base page. This
word should also be cleared by the user program before
calling any floating point routine. The word is never cleared
by the floating point package, and the user program can
examine this word to determine the type of exceptions that
may have occurred during the course of a computation.
5-40
The following 4 types of error can occur in the course of a
floating point computation.
nent range available. On underflow, the result is set to
zero.
4. Divide-by-zero. This error occurs if F2 is zero when computing F1/F2. The result is set to an NaN.
1. Invalid Operand. This happens if one of the input numbers for an Arithmetic routine or the input for FlOA is not
a valid floating point number. An invalid floating point
number (or NaN) can be created either by an overflow in
a previous computation step, or if the ASCII decimal floating point number input to ATOF is too large to be represented in the IEEE format. The result, if one of the inputs
is a NaN is always set to a NaN.
Each of the above errors results in a bit being set in
W(FPERWD). This is done as follows:
Bit O-Set on Overflow.
Bit 1-Set on Underflow.
Bit 2-Set on Illegal Operand.
Bit 3-Set on Divide-by-zero.
One further action is taken when a floating point exception
occurs. After the result has been set to the appropriate value, and the corresponding bit in W(FPERWD) set, the package does a subroutine call to address FPTRAP. The user
can provide any exception handler at this address. The file
FPTRAP.MAC contains the simplest possible user exception handler. It does nothing, but merely returns back to the
calling program.
2. Overflow. This happens if the result of a computation is
too large to be represented within the exponent range
available. Overflow can occur in any of the arithmetic routines or ATOF. On overflow, the result is set to a representation called NaN. An NaN is considered an illegal
operand in all successive steps.
3. Underflow. This occurs if the result of a computation is
too small to be represented with the precision and expo-
5-41
U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
CD
~
z•
c
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
FLP
1
.TITLE FLP
1
2
3
oon
4
5
6
FOOO
0002
0000
LISTER:
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
FLP
THE FLP ROUTINES
7
PAGE:
.LIST
on
. =OFOOO
FPERWD =W(2)
TMPl =W(O)
PAGE:
2
.FORM 'THE FLP ROUTINES'
The code listed in this App Note is available on Dial-A-Helper.
Dial-A-Helper is a service provided by the Microcontroller Applications Group. The Dial-A-Helper system provides access to
an automated information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours
a day. The system capabilities include a MESSAGE SECTION (electronic mail) for communicating to and from the Microcontroller Applications Group and a FILE SECTION mode that can be used to search out and retrieve application data about
NSC Microcontrollers. The minimum system requirement is a dumb terminal, 300 or 1200 baud modem, and a telephone.
With a communications package and a PC, the code detailed in this App Note can be down loaded from the FILE SECTION
to disk for later use. The Dial-A-Helper telephone lines are:
Modem (408) 739-1162
Voice (408) 721·5582
For Additional Information, Please Contact Factory
5-42
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER.REV:C.30 JUL 86
FLP
FERR.MAC
8
9
1
2
3
4
5
6
7
8
9
10
FOOO
F004
F005
F008
FOOR
FOOC
FOOE
820802FA
00
B17F80
3093
3FCC
3FCE
3C
FOOF
F013
F014
F017
F019
F01B
FOlD
820402FA
00
B17F80
3084
3FCC
3FCE
3C
F01E
F022
F023
F026
F028
F02A
F02C
F02E
820202FA
00
ACC8CA
3075
3FC4
3FCC
3FCE
3C
F02F
F033
F034
F037
F039
F03B
F03D
F03F
820102FA
00
B17F80
3064
3FC4
3FCC
3FCE
3C
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
PAGE:
3
>
Z
•
".
CO
en
.FORM 'FERR.MAC'
.INCLD FERR.MAC
; EXCEPTION HANDLING.
; DIVIDE BY ZERO.
DIVBYO:
OR FPERWD. 08
SET THE DIVIDE BY 0 BIT.
CLR A
LD K. 07F80
JSR FPTRAP
POP B
POP X
RET
ILLEGAL OPERAND - ONE OF Fl OR F2 IS A NAN.
FNAN:
OR FPERWD. 04
; SET THE ILLEGAL OPERAND BIT.
CLR A
LD K. 07F80
; RETURN NAN IN K AND A.
JSR FPTRAP
; GO TO USER TRAP ROUTINE.
POP B
POP X
RET
; EXPONENT UNDERFLOW.
UNDFL:
OR FPERWD. 02
SET THE EXPONENT UNDERFLOW BIT.
CLR A
LD K. A
JSR FPTRAP
POP SP
POP B
POP X
RET
; EXPONENT OVERFLOW.
OVRFL:
OR FPERWD. 01
SET THE EXPONENT OVERFLOW BIT.
CLR A
LD K. 07F80
JSR FPTRAP
POP SP
POP B
POP X
RET
.END
•
5-43
CD
CO
~
zc(•
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
FLP
FNACHK.MAC
10
PAGE:
4
.FORM 'FNACHK.MAC'
.INCLD FNACHK.MAC
.TITLE FNACHK
.LOCAL
11
1
2
3
4
5
6
7
8
SUBROUTINE TO CHECK IF A SP FLOATING POINT NUMBER STORED IN THE
IEEE FLOATING POINT FORMAT IN REGS. K AND A IS NAN.
RETURNS 0 IN C IF THE NUMBER IS NOT A NAN.
RETURNS 1 IN C IF THE NUMBER IS A NAN.
9
10
PRESERVES REGS. K, A, X AND B. DESTROYS C.
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
FNACHK:
F040
F042
F043
F046
F047
F048
F049
F04B
AECA
E7
BDFEFF
45
D7
03
AECA
3C
F04C
F04D
F04E
F050
D7
02
AECA
3C
X A, K
SHL A
IFGT A,OFEFF
JP $ISNAN
RRC A
RESET C
X A, K
RET
$ISNAN:
RRC A
SET C
X A, K
RET
.END
5-44
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
FNACHK
FZCHK.MAC
12
13
PAGE:
5
.FORM 'FZCHK.MAC'
.INCLD FZCHK.MAC
• TITLE FZCHK
• LOCAL
1
2
3
4
SUBROUTINE THAT CHECKS IF A SP FLOATING POINT NUMBER STORED
IN THE IEEE FORMAT IN REGS K AND A IS ZERO.
5
6
RETURNS 0 IN C IF THE NUMBER IS NOT ZERO.
RETURNS 1 IN C IF THE NUMBER IS ZERO.
SAVES REGS. K, A, X, AND B BUT DESTROYS C.
7
8
9
10
FZCHK:
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
F051
F053
F054
F056
F057
F058
F059
F05B
AECA
E7
9DFF
45
D7
02
AECA
3C
F05C
F05D
F05E
F060
D7
03
AECA
3C
X A, K
SHL A
IFGT A,OFF
JP SANOTO
RRC A
SET C
X A, K
RET
SANOTO:
RRC A
RESET C
X A, K
RET
.END
5-45
U)
co
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Z•
+, FF -> ->
; M ••• M - 24 BITS OF MANTISSA. NOTE THAT IMPLIED 1 IS PRESENT HERE.
; ON ENTRY TO THE SUBROUTINE X SHOULD POINT TO FLO. ON EXIT, X POINTS
; TO THE WORD AFTER FSIGN.
; REGS. K, A AND B ARE DESTROYED BY THIS SUBROUTINE.
FUNPAK:
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
6
F061
F063
F064
F065
F067
F068
F06A
F06B
F06D
F070
F071
F073
F074
F077
F078
F07A
F07B
ABCC
00
Dl
88CC
Dl
88CD
Dl
A8CA
96C80F
Dl
A8CA
E7
B9FFOO
07
9AFF
Fl
3C
SAVE A IN B.
ST A,B
CLR A
X A, M(X+)
LD A, L(B)
X A, M(X+)
LD A, H(B)
X A, M(X+)
LD A, K
SET A.7
X A, M(X+)
LD A, K
SHL A
AND A, OFFOO
IF C
OR A, OFF
X A, W(X+)
RET
ZERO LOW BYTE OF FLO.
MOVE LOW BYTE OF F-RO INTO HIGH BYTE OF FLO.
; MOVE MID BYTE OF MANT INTO LOW BYTE OF FHI.
; SET IMPLIED 1 IN MANTISSA
; MOVE HIGH BYTE OF MANT INTO HIGH BYTE OF FHI.
SIGN BIT TO CARRY.
ZERO SIGN.
; PUT SIGN BACK IF -.
; SAVE FEXP-FSIGN.
.END
5·46
.
:tNATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
FUNPAK
FPAK.MAC
16
17
PAGE:
7
1
3
4
en
SUBROUTINE TO PACK A SP FLOATING POINT NUMBER STORED IN THE
3 WORD FEXP-FSIGN/FHI/FLO FORMAT INTO THE IEEE FORMAT IN REGS.
K AND A.
5
6
7
8
9
ON ENTRY TO THE SUBROUTINE, X POINTS TO FLO. ON EXIT, X POINTS
TO THE WORD AFTER FSIGN.
10
REGS. K, A AND B ARE DESTROYED.
11
12
13
14
15
16
17
18
19
20
21
FPAK:
F07C
F07D
F07E
F080
F081
F082
F083
F086
D1
D1
ABCA
D1
3B
3B
B9FFOO
AOC8CAFA
X A, M(X+)
X A, M(X+)
ST A, K
X A, M(X+)
SWAP A
SWAP A
AND A, OFFOO
OR K, A
F08A
F08B
F08E
F090
F091
F092
F093
F096
D1
96C81F
ABCC
D4
C7
FO
B9FFOO
D7
X A, M(X+)
RESET A.7
ST A,B
LO A, M(X)
SHR A
LO A, W(X+)
AND A, OFFOO
RRC A
GET RID OF ZERO LOW BYTE OF FLO.
GET HIGH BYTE OF FLO.
STORE IT IN K.
GET LOW BYTE OF FHI.
SHIFT LEFT 8 TIMES.
LOW WORD OF RESULT IS NOW IN K.
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
F097 96CCFA
F09A AECA
F09C 3C
18
19
1
2
3
4 F09D 3C
5
6
GET HIGH BYTE OF FHI.
ZERO IMPLIED MSB 1 IN MANT.
SAVE IN REG. B.
GET SIGN BYTE FROM ASIGN.
MOVE 1 SIGN BIT INTO CARRY.
GET FEXP-FSIGN.
ZERO SIGN.
MOVE RIGHT 1 BIT. SIGN BIT FROM C
ENTERS INTO THE MSB.
GET MANT BITS IN FROM B.
SWAP A AND K
OR A, B
X A, K
RET
.END
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
FPAK
FPTRAP.MAC
~
CD
.FORM 'FPAK.MAC'
.INCLD FPAK.MAC
.TITLE FPAK
.LOCAL
2
Z
PAGE:
8
.FORM 'FPTRAP.MAC'
.INCLO FPTRAP.MAC
.TITLE FPTRAP
; USER SUPPLIED FP TRAP ROUTINE.
FPTRAP:
RET
.END
5·47
~
co
~
z•
ct
,---------------------------------------------------------------------------------,
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
FPTRAP
ROUND.MAC
20
21
PAGE:
9
.FORM 'ROUND.MAC'
.INCLD ROUND.MAC
.TITLE SROUND
.LOCAL
1
2
3
4
THIS SUBROUTINE IS USED TO ROUND THE 32 BIT MANTISSA OBTAINED
IN THE FLOATING POINT CALCULATIONS TO 24 BITS.
5
6
7
8
9
THE UNPACKED FLOATING POINT NUMBER SHOULD BE STORED IN
CONSECUTIVE WORDS OF MEMORY. ON ENTRY, X SHOULD CONTAIN
THE ADDRESS OF C-HI. C-EXP.C-SIGN IS AT W(X+2) AND
C-LO IS AT W(X-2).
10
11
12
13
14
15
16
17
18
19
20
21
F09E
F09F
FOAO
FOA3
FOA4
FOA5
FOM
F2
F4
96C817
43
FO
FO
5F
FOA7
FOAA
FOAB
FOAC
FOAD
FOAE
B80100
Fl
07
42
FO
57
FOAF
FOBO
FOBl
FOB2
FOB3
FOB4
FOB5
FOB6
F4
B8
00
01
07
42
FOB7
FOB8
FOB9
FOBA
FOBB
FOBC
FOBD
FOBE
FOCi
D7
F3
F4
D7
Fl
FO
F4
B80100
07
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Fl
4F
ON EXIT X HAS THE ADDRESS OF C-EXP.C-SIGN.
SROUND:
LD A, W(X-)
; REMEMBER X POINTS TO C-HI.
LDA, W(X)
; LOAD C-LO.
; IF BIT 25 OF MANTISSA IS 1,
IF A.7
; THEN NEED TO INCREASE MANTISSA.
JP $RNDUP
LD A, W(X+)
LD A, W(X+)
; X NOW POINTS TO C-EXP.C-SIGN.
; DONE, SO GET OUT.
JP $EXIT
INCREASE MANTISSA.
$RNDUP:
ADD A, 0100
X A, W(X+)
INCREASE LOW BYTE BY 1.
IF C
IF THERE IS A CARRY,
JP $HIUP
THEN NEED TO INCREASE C-HI.
LD A, W(X+)
; X NOW POINTS TO C-EXP.C-SIGN.
JP $EXIT
; DONE, SO GET OUT.
; MANTISSA INCREASE PROPAGATING TO HIGH WORD.
$HIUP:
LD A, W(X)
.BYTE OB8,00,01 ; DO ADD A, 01 BUT WITH WORD CARRY!!
IF C
IF THERE IS A CARRY,
JP $EXIN2
THEN NEED TO INCREASE EXPONENT.
X A,W(X+)
JP $EXIT
GET OUT.
; ROUND UP LEADS TO EXPONENT INCREASE.
$EXIN2:
; CARRY->MSB, LSB-> CARRY.
RRC A
X A,W(X-)
; LOW WORD IS NOW IN A.
LD A,W(X)
RRCA
X A, W(X+)
; X NOW POINTS TO C-EXP.CSIGN.
LD A, W(X+)
LD A, W(X)
ADD A, 0100
IF C
5·48
»
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
SROUND
ROUND.MAC
48
49
FOC2 BAFFOO
FOC5 F6
50
51
52 FOC6 3C
53
54
PAGE:
10
z
~
00
0')
OR A, OFFOO
ST A, W(X)
MAKE IT A NAN.
$EXIT:
RET
.END
5-49
U)
co
~
z•
cC
r------------------------------------------------------------------------------------,
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER.REV:C.30 JUL 86
SROUND
BFMUL.MAC
22
23
11
.FORM 'BFMUL.MAC'
.INCLD BFMUL.MAC
.TITLE BFMUL
1
2
3
4
5
6
7
8
9
THIS SUBROUTINE IS USED TO MULTIPLY TWO 32 BIT FIXED POINT FRACTIONS.
THE ASSUMED BINARY POINT IS TO THE IMMEDIATE LEFT OF THE MSB.
THE FIRST FRACTION IS STORED IN REGS K AND A. WITH THE MORE
SIGNIFICANT WORD BEING IN K.
THE SECOND FRACTION IS STORED ON THE STACK. THE MORE SIGNIFICANT
; WORD IS AT W(SP-4) AND THE LOWER SIGNIFICANT WORD
IS IN THE WORD BELOW IT.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
PAGE:
THE 32 BIT PRODUCT IS LEFT IN REGS. K AND A. WITH THE MORE
SIGNIFICANT WORD BEING IN K.
IMPORTANT NOTE : THE FRACTIONS ARE ASSUMED TO BE UNSIGNED.
REGS. B AND X ARE UNCHANGED.
BFMUL:
FOC7
FOC9
FOCB
FOCD
FOCF
FOD4
FOD6
FOD8
FODA
FODC
FOEl
AFCE
AFC8
AFCA
ABCA
A6FFF6C4FE
3FCA
AFCE
AFC8
A8CA
A6FFF2C4FE
3FC8
PUSH X
PUSH A
PUSH K
LD A. K
MULT A. W(SP-OA)
POP K
PUSH X
PUSH A
LD A. K
MULT A. W(SP-OE)
POP A
FOE3
FOE5
FOE8
FOE9
FOEB
FOED
FOEF
FOF1
FOF3
FOF8
FOFA
FOFC
FOFF
F100
F102
F104
3FCA
96CEF8
07
A9CA
3FCE
AFCA
AFC8
A8CE
A6FFF6C4FE
3FC8
3FCA
96CEF8
07
A9CA
3FCE
3C
POP K
ADD A. X
IF C
INC K
POP X
PUSH K
PUSH A
LD A. X
MULT A. W(SP-OA)
POP A
POP K
ADD A. X
IF C
INC K
POP X
RET
5-50
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
SAVE X.
SAVE F1-LO
SAVE F1-HI.
MOVE F1-HI TO A.
MULTIPLY F1-HI BY F2-HI.
GET FI-HI.
SAVE PR-HI.
SAVE PR-LO.
MOVE F1-HI TO A.
MULTIPLY F1-HI BY F2-LO.
GET PR-LO SAVED. NOTE THAT THE
LO WORD OF THIS PRODUCT IS DISCARDED.
GET PR-HI SAVED.
ADD TO PR-LO THE HI WORD OF THIS PRODUCT.
ON CARRY.
PROPAGATE THRU TO PR-HI.
GET FI-LO.
SAVE PR-HI.
SAVE PR-LO.
MOVE FI-LO TO A.
MULTIPLY BY F2-HI.
GET PR-LO SAVED.
GET PR-HI SAVED.
ADD TO PR-LO THE HI-WORD OF THIS PRODUCT.
; PROPAGATE ANY CARRY TO PR-HI.
; RESTORE X.
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
BFMUL
BFMUL.MAC
50
12
.END
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
BFMUL
ISIOK.MAC
24
25
PAGE:
13
.FORM 'ISIOK.MAC'
.INCLD ISIOK.MAC
.TITLE ISIOK
.LOCAL
1
2
3
4
THIS SUBROUTINE IS USED TO DETERMINE IF ANOTHER DECIMAL DIGIT CAN
BE ACCUMULATED IN THE 32 BIT INTEGER STORED IN REGS. K AND A.
THE MORE SIGNIFICANT WORD IS IN K.
SETS THE CARRY TO 1 IF IT CAN BE ACCUMULATED; RESETS THE CARRY
OTHERWISE. PRESERVES ALL REGS.
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
PAGE:
ISIOK:
FI05
F106
FI0B
FlOC
F111
F1l2
F1l3
F1l6
F1l7
02
861999CAFC
47
861999CAFD
03
3C
BD9998
03
3C
SET C
IFEQ K, 01999
JP $CHKOT
IFGT K, 01999
RESET C
RET
$CHKOT: IFGT A, 09998
RESET C
RET
.END
5-51
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER.REV:C.30 JUL 86
ISIOK
MUL10.MAC
26
27
14
.FORM 'MUL10.MAC'
.INCLD MUL10.MAC
.TITLE MUL10
.LOCAL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28
PAGE:
THIS SUBROUTINE MULTIPLIES THE 32 BIT INTEGER STORED IN REGS K AND A
BY 10-DECIMAL AND ADDS TO IT THE INTEGER STORED IN X.
; THE RESULT IS RETURNED IN K AND A.
; REGS. B AND X ARE NOT CHANGED.
MUL10:
F118
F11A
F11C
F11E
F120
F122
F127
F129
F12B
F12F
F131
F133
F136
F137
F139
AFCE
AFC8
A8CA
9EOA
AFC8
A6FFFCC4A8
9EOA
3FCA
AOCECAF8
3FCE
3FCE
96CEF8
07
A9CA
3C
PUSH X
PUSH A
LD A. K
MULT A. OA
PUSH A
LD A. W(SP-4)
MOLT A. OA
POP K
ADD K. X
POP X
POP X
ADD A. X
IF C
INC K
RET
SAVE INTEGER.
SAVE LONG INT-LO.
; MOLT LONG INT-HI BY 10.
SAVE LOW WORD OF PRODUCT.
GET LONG INT-LO.
GET
; ADD
GET
; GET
.END
5-52
LO WORD OF LAST PRODUCT.
TO IT HI WORD OF THIS PRODUCT.
RID OF GARBAGE.
INTEGER TO BE ADDED.
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
MULI0
ATOF.MAC
29
30
1
2
3
4
5
6
7
8
9
10
15
.FORM 'ATOF.MAC'
.INCLD ATOF.MAC
.TITLE ATOF
.LOCAL
THIS SUBROUTINE CONVERTS A DECIMAL FLOATING POINT STRING TO
: AN IEEE FORMAT SINGLE PRECISION FLOATING POINT NUMBER. THE
: INPUT DECIMAL STRING IS ASSUMED TO BE OF THE FORM
SMMMMMMM.FFFFFEDNN
WHERE S IS THE SIGN OF THE DECIMAL MANTISSA,
M••• M IS THE INTEGER PART OF THE MANTISSA,
F••• F IS THE FRACTIONAL PART OF THE MANTISSA,
D IS THE SIGN OF THE DECIMAL EXPONENT,
: AND
NNN IS THE DECIMAL EXPONENT.
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
PAGE:
ON ENTRY, B SHOULD POINT TO THE ADDRESS OF THE ASCII
STRING HOLDING THE DECIMAL FLOATING POINT NUMBER. THIS STRING
: MUST BE TERMINATED BY A NULL BYTE.
THE BINARY FLOATING POINT NUMBER IS RETURNED IN
REGS. K AND A.
: REGS. B AND X ARE LEFT UNCHANGED.
ATOF:
F13A
F13C
F13E
F13F
Fl4l
F143
F145
AFCE
AFCC
00
AFC8
AFC8
AFC8
AFC8
PUSH X
PUSH B
CLR A
PUSH A
PUSH A
PUSH A
PUSH A
DECIMAL
: RESULTS
THE '+'
THE '_I
THE '.'
ZERO A.
STORAGE
STORAGE
STORAGE
STORAGE
FOR
FOR
FOR
FOR
MANTISSA SIGN.
IMPLICIT lOtS EXPONENT.
HI-INT.
LO-INT.
STRING MUST START WITH A '+', '-', '.' OR A DIGIT.
ARE UNPREDICTABLE IF IT DOES NOT.
MEANS THAT THE MANTISSA IS POSITIVE. IT CAN BE OMITTED.
MEANS THAT THE MANTISSA IS NEGATIVE.
MEANS THAT THE MANTISSA HAS NO INTEGER PART.
$LOOPl:
F147
F148
F149
F14B
F14C
F14E
F14F
CO
40
9C2B
64
9C2D
45
9C2E
LDS A, M(B+)
NOP
IFEQ A, '+'
JP $LOOPl
IFEQ A. '-'
JP $MSIGN
IFEQ A, '.'
GET THE CHARACTER.
IF IT IS A '+',
DO NOTHING, BUT GET 1 MORE.
IF IT IS A '-',
GO AND CHANGE THE MANTISSA SIGN.
IF IT IS A
5·53
•
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
ATOF
ATOF.MAC
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
F151 9438
PAGE:
JP $INCOL
GO AND COLLECT THE FRACTION PART.
GET HERE MEANS IT IS A DIGIT.
SO GO AND COLLECT THE INTEGER PART.
LD A, OFF
ST A, W(SP-08)
JP $LOOPl
CHANGE MANTISSA SIGN TO NEG.
GO BACK FOR SOME MORE.
JMP $FRCOL
F153 48
16
$MSIGN:
F154 90FF
F156 A6FFF8C4AB
F15B 74
$INCOL:
GET HERE MEANS COLLECTING INTEGER PART OF MANTISSA.
F15C
F15D
F161
F164
F166
F168
F16A
F16B
02
8230C8EB
ACC8CE
3FCA
3FC8
3463
07
4B
SET C
SUBC A, '0'
LD X, A
POP K
POP A
JSR ISIOK
IF C
JP $ACCM
F16C
F16E
F170
F172
F174
F176
3FCE
A9CE
AFCE
AFC8
AFCA
46
POP X
INC X
PUSH X
PUSH A
PUSH K
JP $ISNXT
F177 345F
F179 AFC8
F17B AFCA
F17D CO
F17E 40
F17F 9C2E
~'181 49
F182 9C45
F184 9434
F186 9C20
F188 6B
F189 952D
; CONVERT DIGIT FROM ASCII TO INTEGER.
; MOVE INTEGER TO X.
GET HI-INT COLLECTED SO FAR.
GET LO-INT COLLECTED SO FAR.
CHECK IF THE DIGIT CAN BE ACCUMULATED.
LOOK AT C.
; YES, IT CAN BE SO GO DO IT.
GET HERE MEANS CAN ACCUMULATE ANY MORE.
SO INCREASE THE IMPLICIT lOtS EXPONENT.
GET IMPLICIT lOtS EXPONENT COLLECTED
SO FAR AND INCREMENT IT.
SAVE IT BACK.
SAVE LO-INT.
SAVE HI-INT.
$ACCM:
GET HERE MEANS THE PRESENT DIGIT CAN BE ACCUMULATED.
MULTIPLY BY 10 AND ADD DIGIT.
JSR MUL10
PUSH A
SAVE LO-INT.
PUSH K
SAVE HI-INT.
$ISNXT:
; PROCESS THE NEXT CHARACTER.
LDS A, M(B+)
NOP
IF IT IS A'.'
IFEQ A, '.'
GO COLLECT FRACTION PART.
JP $FRCOL
IFEQ A, 'E'
IF IT IS 'E',
GO COLLECT EXPONENT PART.
JMP $EXCOL
IFEQ A, ' ,
IF IT IS A SPACE,
GO GET SOME MORE.
JP $ISNXT
GET HERE MEANS IT IS A DIGIT.
JMP $INCOL
$FRCOL:
GET HERE MEANS COLLECT THE FRACTIONAL PART OF THE MANTISSA.
F18B CO
F18C 40
LDS A, M(B+)
NOP
5·54
.
l>
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
ATOF
ATOF.MAC
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
128
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
F18D
F18F
F191
F193
9C45
9429
9C20
68
IFEQ A, 'E'
JMP $EXCOL
IFEQ A, ' ,
JP $FRCOL
F194
F195
F199
F19C
F19E
F1AO
F1A2
F1A3
02
8230C8EB
ACC8CE
3FCA
EFC8
349B
07
45
SET C
SUBC A, '0'
LD X, A
POP K
POP A
JSR ISIOK
IF C
JP $ACCF
F1A4 AFC8
F1A6 AFCA
F1A8 70
F1A9
FlAB
F1AD
F1B2
F1B4
F1B6
F1B8
3491
3FCE
86FFFFCEF8
AFCE
AFC8
AFCA
9520
PAGE:
17
IF IT IS A 'E',
GO COLLECT EXPONENT.
IF IT IS SPACE,
GO GET SOME MORE.
GET HERE MEANS IT IS A DIGIT.
GET INTEGER FROM DIGIT.
SAVE IT IN A.
GET HI-INT.
GET LO-INT.
CHECK IF IT CAN BE ACCUMULATED.
; YES, SO GO DO IT.
; GET HERE MEANS CAN'T COLLECT MORE DIGITS.
PUSH A
PUSH K
JP $FRCOL
SO JUST IGNORE IT.
$ACCF:
ACCUMULATE THE FRACTIONAL DIGIT.
JSR MUL10
; MULTIPLY BY 10 AND ADD DIGIT.
POP X
; GET IMPLICIT 10'S EXPONENT COLLECTED SO FAR,
ADD X, OFFFF
; AND DECREMENT IT BY 1.
PUSH X
SAVE IT BACK.
PUSH A
SAVE LO-INT.
PUSH K
SAVE HI-INT.
JMP $FRCOL
GO GET SOME MORE.
F1C7 02
F1C8 60
F1C9 9100
F1CB 07
$EXACC:
; ACCUMULATE THE EXPLICIT 10'S EXPONENT.
LD K, 0
IF C
F1BB
F1BC
F1BD
F1BF
FlCO
F1C2
F1C3
F1C5
CO
40
9C2B
64
9C2D
44
9C20
6A
F1C6 42
oI:loo
en
$EXCOL:
GET HERE MEANS THE EXPLICIT 10'S EXPONENT NEEDS TO BE
; COLLECTED FROM THE STRING.
RESET C
; MAKE EXPONENT SIGN POST.
$EXCHR:
LOS A, M(B+)
MOP
IF IT IS A '+',
IFEQ A, '+'
GET SOME·MORE.
JP $EXCHR
IF IT IS A '-',
IFEQ A, '-',
JP $ESIGN
GO FIX EXPONENT SIGN.
IFEQ A, ' ,
IF IT IS SPACE,
JP $EXCHR
GO GET SOME MORE.
GET HERE MEANS IT IS A DIGIT.
SO GO COLLECT THE EXPONENT.
JP $EXACC
$ESIGN:
SET C
JP $EXCHR
F1BA 03
z
CD
5-55
•
~
co
"'1::1'
Z
oCt
,---------------------------------------------------------------------------------,
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER.REV:C.30 JUL S6
ATOF
ATOF.MAC
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15S
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163
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16S
169
170
171
172
173
174
175
176
177
17S
179
lS0
lSl
182
lS3
lS4
185
lS6
lS7
lSS
lS9
190
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197
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200
201
202
F1CC
F1CE
F1DO
F1D2
91FF
AFCA
9300
AFCE
PAGE:
18
LD K. OFF
PUSH K
LD X. 0
PUSH X
GET SIGN BITS SET.
SAVE EXPLICIT EXPONENTS SIGN.
ZERO EXPLICIT EXPONENT COLLECTED SO FAR.
$EXCLP:
F1D4
F1D5
F1D9
F1DC
F1DE
F1E2
F1E6
F1E7
F1ES
F1E9
F1EC
FlEE
F1EF
F1FO
F1F2
02
S230CSEB
ACCSCE
3FC8
AOCSCEFS
AOCSCEFS
E7
E7
E7
96CEFS
AFCS
CO
40
9COO
41
F1F3 7F
FlF4
F1F6
F1FS
F1FC
F1FD
F1FE
3FC8
3FCA
S200CAFC
42
01
04
F1FF
F204
F207
F20S
F20A
AGFFFAC4FS
BD7FFF
43
9300
44
F20B 93FF
F20D 01
F20E 04
F20F
F212
F214
F216
F218
ACC8CC
3FC8
3FCA
AFCE
AFCC
SET C
SUBC A. '0'
LD X. A
POP A
ADD X. A
ADD X. A
SHL A
SHL A
SHL A
ADD A. X
PUSH A
LDS A. M(B+)
NOP
IFEQ A. 0
JP $Al0EX
GET INTEGER FROM ASCII DIGIT.
GET EXPLICIT EXPONENT COLLECTED SO FAR.
; X CONTAINS DIGIT + EXP.
; X CONTAINS DIGIT + 2*EXP.
; A CONTAINS S*EXP.
; A CONTAINS DIGIT + 10*EXP.
SAVE BACK ON STACK.
GET NEXT CHAR.
IS IT A NULL ?
; YES SO ADD EXPLICIT AND IMPLICIT
10'5 EXPONENT.
GET HERE MEANS IT IS A DIGIT.
SO GO BACK AND ACCUMULATE IT.
JP $EXCLP
$Al0EX:
; DONE COLLECTING DIGITS.
10'S EXPONENT COLLECTED
POP A
POP K
;
;
IFEQ K. 0
JP $ADDEX
;
COMP A
INC A
;
$ADDEX:
ADD A. W(SP-06) ;
IFGT A. 07FFF
;
JP $NEG10
;
;
LD X. 0
JP $ESAVE
$NEG10
;
LD. X. OFF
COMP A
INC A
;
$ESAVE:
LD B. A
POP A
POP K
PUSH X
PUSH B
;
ADD THE EXPLICIT AND IMPLICIT
SO FAR.
GET EXPLICIT 10'S EXPONENT.
GET ITS SIGN.
IS IT POSITIVE ?
YES SO ADD 'EM.
CHANGE TO 2'5 COM.
ADD IMPLICIT EXPONENT.
IS IT NEGATIVE ?
YES. CHANGE IT.
LOAD POST. SIGN IN X.
LOAD NEG. SIGN IN X.
MAKE IT POSITIVE.
SAVE 10'S EXPONENT IN A.
GET HI-INT.
GET LO-INT.
SAVE SIGN OF 10'S EXPONENT.
AND ITS VALUE.
; NOW CONVERT HI-INT.LO-INT TO A NORMALIZED FLOATING POINT
5·56
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NATIONAL SEMICONDUCTOR CORPORATION
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ATOF
ATOF.MAC
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PAGE:
19
CD
F21A
F21C
F21D
F221
9000
58
8200CAFD
4E
IFGT A, 0
JP $NORM2
IFGT K, 0
JP $NORMl
F222
F223
F226
F227
F22B
F22D
F22F
00
ACC8CA
02
8208C4EB
3FCC
3FCE
3C
CLR A
LD K, A
SET C
SUB SP, 08
POP B
POP X
RET
IF HI-INT IS NOT 0,
NEED TO SHIFT K AND A.
IF HI-INT IS 0, BUT NOT LO-INT,
; NEED TO SHIFT ONLY K.
; GET HERE MEANS MANTISSA IS O.
; ADJUST SP. DONE!!!
$NORM1:
HI-INT IS 0, SO WORK WITH LO-INT ONLY.
F235 9220
F237
F238
F239
F23A
F23C
F23D
F23E
F241
F243
F245
F246
E7
07
4D
AECA
E7
07
96CA08
AECA
AACC
40
6F
F247
F248
F24A
F24C
F24E
F250
F252
F254
F256
F259
D7
ABOO
3FCE
3FC8
AEOO
AFCC
AFCE
AECA
960010
58
~
Q)
NUMBER. THE BINARY EXPONENT IS COLLECTED IN B.
F230 AECA
F232 9210
F234 42
ZI
X A, K
LD B, 010
JP $NRLUP
; LOAD 16 INTO EXPONENT COUNTER.
$NORM2:
; HI-INT IS NOT 0, SO NEED TO HANDLE BOTH.
LD B. 020
; LOAD 32 INTO LOOP COUNTER.
$NRLUP:
SHL A
; DID A 1 COME OUT ?
IF C
JP $NRDUN
; YES IT IS NORMALIZED NOW.
X A, K
SHL A
IF C
SET K.O
X A, K
DECSZ'B
NOP
JP $NRLUP
SHOULD NEVER BE SKIPPED!!
$NRDUN:
RRC A
; RESTORE SHIFTED 1.
ST A, TMPl
STORE IN W(O).
POP X
; GET 10'S EXPONENT.
POP A
; GET 19'5 EXPONENT SIGN.
X A, TMPl
; A IS HI-INT ONCE MORE.
PUSH B
; SAVE BINARY EXPONENT.
PUSH X
; SAVE 10'S EXPONENT.
X A, K
; HI-INT TO K, LO-INT TO A.
IF TMP1.0
; IS 10'S EXPONENT NEGATIVE?
JP $DIV10
; YES, GO TO DIVIDE BY 10.
GET HERE MEANS 10'S EXPONENT IS POSITIVE, SO MULTIPLY BY 10.
; ACTUALLY, WHA~ IS USED IS
lOAN
(0.625* (2A4)AN
; SO MULTIPLY BY 0.625 NOW AND TAKE CARE OF 2A(4*N) LATER.
=
5·57
.,.co
~ r-------------------------------------------------------------------------------~
Z
cC
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
ATOF
ATOF.MAC
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257
258
259
260
261
262
263
264
265
266
267
268
269
270
20
F25A
F25F
F261
F266
F268
A4F26ACCAB
AFCC
A4F26CCCAB
AFCC
57
F269
F26A
F26C
F26E
F270
40
0000
OOAO
CDCC
CCCC
; DEFINE SOME CONSTANTS •
• EVEN ; FORCE EVEN ADDRESS.
SMTLO: .WORD 0
$MTHI: .WORD OAOOO
SDTLO: .WORD OCCCD
SDTHI: .WORD OCCCC
A4F26ECCAB
AFCC
A4F270CCAB
AFCC
SDIVlO:
; GET HERE MEANS 10'S EXPONENT IS NEGATIVE, SO DIVIDE BY 10.
; ACTUALLY WHAT IS DONE IS
10A(-N) = ((2A3) 1(0.8)) A(_N) = ((0.8)AN)· (2A(-3·N)))
SO MULTIPLY BY 0.8 NOW AND TAKE CARE OF 2A(-3·N) LATER.
LD B, W(SDTLO)
PUSH B
SAVE LO WORD OF .8
LD B, W(SDTHI)
PUSH B
SAVE HI WORD OF .8
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
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296
297
298
299
300
301
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303
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PAGE:
F272
F277
F279
F27E
F280 9200
F282 8200CEFC
F286 57
F287
F289
F28B
F28C
F28D
F28E
35CO
AECA
E7
07
4A
A9CC
F290
F292
F293
F294
F297
AECA
E7
07
96CA08
43
LD B, W(SMTLO)
PUSH B
LD B, W($MTHI)
PUSH B
JP SJAMIT
SAVE LO WORD OF 0.625 ON STACK.
SAVE HI WORD OF 0.625 ON STACK.
GO TO ROUTINE THAT JAMS 0.625 AN
; BY REPEATED MULTIPLICATION INTO HI-INT.LO-INT.
SJAMIT:
; JAM IN THE MULTIPLICATION PART NEEDED TO HANDLE THE 10'S EXP.
LD B, 0
; B IS USED TO TRACK ANY BINARY POWERS
; THAT COME UP DURING NORMALIZATION.
IFEQ X, 0
; IS 10'S EXPONENT 0 ?
; YES, DONE ALREADY.
JP $JAMDN
SJAMLP:
JSR BFMUL
; MULTIPLY USING 32 BIT UNSIGNED.
X A, K
SWAP HI AND LO WORDS.
SHL A
IS THERE A CARRY ?
IF C
; YES, SO IT IS ALREADY NORMALIZED.
JP SISNED
; NEED TO SHIFT LEFT TO NORMALIZE, SO
INC B
; INCREASE B BY 1.
X A, K
SHL A
IS C
SET K.O
JP SOVRl
SISNED:
F298 D7
F299 AECA
RRCA
X A, K
SOVR1:
F29B AACE
F29D 76
DECSZ X
; DONE YET ?
JP SJAMLP
; NO SO DO IT ONCE MORE.
GET HERE MEANS MULTIPLICATIONS HAVE BEEN DONE. NOW TAKE
CARE OF THE EXPONENTS.
5-58
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER.REV:C.30 JUL 86
AT OF
ATOF.MAC
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PAGE:
21
SJAMDN:
F29E
F2AO
F2A2
F2A4
F2A6
F2A8
F2AD
F2AE
3FCE
3FCE
3FCE
AFC8
AFCA
A6FFFAC4A8
02
96CCEB
POP X
POP X
POP X
PUSH A
PUSH K
LD A. W(SP-6)
SET C
SUBC A. B
F2Bl
F2B4
F2B6
F2B9
ACC8CC
A8CE
960010
49
LD
LD
IF
JP
F2BA
F2BB
F2BC
F2BF
F2C2
E7
E7
96CCF8
B8007E
4C
SHL A
SHL A
ADD A. B
ADD A. 07E
JP $EXCPT
F2C3
F2C4
F2C7
F2C8
F2C9
F2CC
E7
96CEF8
01
04
96CCF8
B8007E
F2CF
F2D2
F2D3
F2D7
F2D9
F2DC
F2DF
F2El
F2E4
F2E6
ACC4CE
02
820ACEEB
AFCE
BD7FFF
B4FD3F
9COO
B4FD3A
9DFE
B4FD46
F2E9
F2EB
F2EC
F2ED
F2EE
F2EF
F2FD
3FCE
E7
E7
E7
E7
E7
E7
.
; GET 0.625 OR 0.8 OFF THE STACK.
; GET THE 10'S EXPONENT.
SAVE LO WORD OF FLP NUMBER.
SAVE HI WORD OF FLP NUMBER.
GET THE BINARY EXPONENT THAT WAS SAVED.
;
;
;
;
;
;
;
;
;
;
;
;
B. A
A. X
TMP1.0
$NAGAS
SUBTRACT FROM IT BINARY EXPONENT COLLECTED
DURING THE JAMMING.
SAVE IT IN B.
MOVE THE 10'S EXPONENT TO A.
IS THE 10'S EXPONENT NEGATIVE
YES. SO GOT TO SUBTRACT.
GET HERE MEANS 10'S EXPONENT IS
POSITIVE. SO MUL IT BY 4.
MULTIPLY BY 2.
MULTIPLY BY 2 AGAIN.
GET THE BINARY EXPONENT IN ALSO.
AND THE IEEE BIAS.
GO CHECK FOR OVER/UNDERFLOW.
$NAGAS:
; GET HERE MEANS 10'S EXPONENT IS NEGATIVE. SO GOT TO MULTIPLY
IT BY -3.
SHL A
; MULTIPLY BY 2.
; ADD TO GIVE MULTIPLY BY 3.
ADD A. X
COMP A
INC A
; MAKE IT NEGATIVE.
; GET IN THE BINARY EXPONENT.
ADD A. B
; AND THE IEEE BIAS.
ADD A. 07E
$EXCPT:
CHECK FOR OVERFLOW/UNDERFLOW.
LD X. SP
; FIRST DO SOME JUGGLING
SET C
; TO BE COMPATIBLE WITH EXCEPTION
SUBC X. OA
; HANDLING IN OTHER ROUTINES.
PUSH X
IS BIASED EXPONENT NEGATIVE
IFGT A. 07FFF
JMPL UNDFL
IS IT 0 ?
IFEQ A. 0
JMPL UNDFL
; YES IT IS STILL UNDERFLOW.
; IS IT GT THAN 254 ?
IFGT A. OFE
JMPL OVRFL
GET HERE MEANS VALID SP FLP NUMBER.
POP X
; X POINTS TO MANTISSA SIGN.
SHL A
SHL A
SHL A
SHL A
SHL A
SHL A
5·59
•
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
ATOF
ATOF.MAC
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F2F1
F2F2
F2F3
F2F5
F2F7
F2F9
F2FB
F2FC
F2FE
F2FF
F301
F302
F304
F305
F306
F308
F30A
F30C
F30E
F310
E7
E7
8FFA
ABOO
3FCA
3FC8
F1
A8CA
F1
A800
F3
3664
F2
F2
AFCE
368C
3FC4
3FCC
3FCE
3C
...
PAGE:
SHL A
SHL A
OR A, W(X)
ST A, TMP1
POP K
POP A
X A, W(X+)
LD A, K
X A, W(X+)
LD A, TMP1
X A, W(X-)
JSRL SROUND
LD A, W(X-)
LD A, W(X-)
PUSH X
JSR FPAK
POP SP
POP B
POP X
RET
22
; MOVE EXPONENT TO HIGH BYTE.
GET THE MANTISSA SIGN IN.
SAVE IT IN TMP1.
FI-HI TO K.
F1-LO TO A.
SAVE F1-LO.
SAVE F1-HI.
SAVE F1-EXP.F1-SIGN. X POINTS TO F1-HI.
; ROUND THE RESULT.
; X POINTS TO F1-HI.
; X POINTS TO F1-LO.
; PACK IT INTO IEEE FORMAT.
• END
5-60
.
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NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
ATOF
FTOA.MAC
31
32
PAGE:
23
en
4
5
6
7
8
THIS SUBROUTINE CONVERTS A SINGLE PRECISION, BINARY FLOATING
POINT NUMBER IN THE IEEE FORMAT TO A DECIMAL FLOATING POINT
STRING. THE DECIMAL FLOATING POINT STRING IS OBTAINED TO A
PRECISION OF 9 DECIMAL DIGITS.
9
THE ALGORITHM USED IS BASED ON:
J.T. COONEN, 'AN IMPLEMENTATION GUIDE TO A PROPOSED STANDARD
FOR FLOATING POINT ARITHMETIC,' IEEE COMPUTER, JAN. 1980, PP 68-79.
ON INPUT, THE BINARY SP FLP NUMBER IS IN REGS. K AND A.
B CONTAINS THE ADDRESS OF THE LOCATION WHERE THE DECIMAL FLOATING
POINT STRING IS TO START. NOTE THAT AT LEAST 17 BYTES ARE NEEDED
FOR THE STORAGE OF THE STRING. THE LAST BYTE IS ALWAYS NULL.
ALL REGISTERS ARE PRESERVED BY THIS SUBROUTINE.
FTOA:
F311 AFCE
F313 AFCC
F315 3605
F317 07
F318 B401B4
F31B 36CA
F31D 07
F31E B401C8
F321 ACC4CE
F324 8206C4F8
F328 36C7
PUSH X
; SAVE X ON THE STACK.
PUSH B
; SAVE B ON THE STACK.
CHECK AND SEE IF Fl IS A NAN.
JSR FNACHK
IF C
JMPL $NAN
; YET IT IS, SO GET OUT.
CHECK AND SEE IF Fl IS ZERO.
JSR FZCHK
IF C
JMPL $ZERO
;YES IT IS, SO GET OUT.
GET HERE MEANS Fl IS A NON-ZERO, NON-NAN FLP NUMBER.
LD X, SP
ADD SP, 06
; ADJUST SP.
JSR FUNPAK
; UNPACK THE NUMBER.
; X POINTS ONE WORD PAST Fl-EXP.Fl-SIGN
ON RETURN.
COMPUTE THE EXPONENT OF 10 FOR DECIMAL FLP NO.
THIS IS DONE AS FOLLOWS:
SUPPOSE Fl = FM * (2AM)
LET U M*LOG(2)
NOTE: LOG IS TO BASE 10.
THEN V INT(U+1-9)
IS USED AS THE 10'S EXPONENT.
NOTE: INT REFERS TO INTEGER PART.
=
=
44
45
46
47
48
49
~
.FORM 'FTOA.MAC'
.INCLD FTOA.MAC
.TITLE FTOA
.LOCAL
1
2
3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
z
CO
F32A
F32B
F32C
F330
D2
D2
B7000000
B8FF82
LD A, M(X-)
LD A, M(X-)
LD TMP1, 0
ADD A, OFF82
;
;
;
;
5·61
X POINTS TO Fl-EXP.
LOAD Fl-EXP. X POINTS TO Fl-SIGN.
FIRST GUESS POSITIVE SIGN FOR EXP.
REMOVE IEEE BIAS FROM Fl-EXP.
•
~ ~--------------------------------------------------------------------------------,
co
"'1:1'
:Z
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NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
FTOA
FTOA.MAC
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51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
F333
F335
F337
F338
F339
F33D
F33E
AFC8
AFCE
07
46
B700FFOO
01
04
F33F BE4D10
F342
F344
F347
F348
AECE
960010
41
4B
F349
F34A
F34C
F34D
F350
71 F352
72 F353
73
74 F354
75 F355
76 F358
77 F35B
78 F35C
79 F36D
80
81 F361
82 F365
83 F366
84 F368
85 F369
86 F36C
87 F36E
88 F36F
89
90
91
92
93
94
95
96
97
98
99
100
01
AECE
01
B80001
AECE
07
04
04
B8FFF7
BD7FFF
45
B7000000
4F
B700FFOO
01
AECE
01
B80001
AECE
07
04
PAGE:
PUSH A
PUSH X
IF C
JP $MLOG2
LD TMP1, OFF
COMP A
INC A
24
;
;
;
;
;
;
$MLOG2:
; MULTIPLY M BY LOG(2).
MULT A, 04D10
;
;
;
X A~ X
;
IF TMP1.0
;
JP $CSIGN
JP $REMV9
;
$CSIGN:
;
COMP A
X A, X
COMP A
;
ADD A, 01
X A, X
IF C
INC A
$REMV9:
INC A
ADD A, OFFF7
IFGT A, 07FFF
;
JP $CHNGS
LD TMP1, 0
;
JP $DIVlO
$CHNGS:
;
LD TMP1, OFF
;
COMP A
X A, X
COMP A
ADD A, 01
X A, X
IF C
INC A
$DIVlO:
=
SAVE IT ON THE STACK.
SAVE F1-SIGN ADDRESS ALSO.
WAS THERE A CARRY ON THE LAST ADD ?
YES, SO 2'S EXP IS POSITIVE.
2'S EXPONENT IS NEGATIVE.
MAKE IT POSITIVE.
LOG(2) IS 0.0100110100010000 TO 16 BITS.
X CONTAINS INTEGER PART, AND A FRACT. PART.
SWAP THE TWO.
WAS THE 2'S EXPONENT NEGATIVE?
YES, SO MAKE U NEGATIVE.
NO, SO GO DO V U + 1 - 9.
=
COMP INTEGER PART.
FRACTION PART.
INCREASE FRACTION PART.
SUBTRACT 9.
IS IT NEGATIVE ?
YES, SO CHANGE ITS SIGN.
REMEMBER POSITIVE SIGN.
REMEMBER NEGATIVE SIGN.
MAKE V POSITIVE.
; V INT (U+1-9) HAS BEEN COMPUTED AND IS IN A.
; NOW COMPUTE W F1/(10AV). W SHOULD BE AN INTEGER, AND IT IS
COMPUTED TO A 32 BIT PRECISION.
THIS COMPUTATION IS DONE AS FOLLOWS:
IF V > 0, THEN F1/ (10 AV) = F1* (0.8 AV) * (2A(-3V)) •
IF V < 0, THEN F1/(10 AV) = F1*(0.625'U)*(2A(4V)).
SO FIRST MULTIPLY THE MANTISSA OF F1 V TIMES BY 0.8 (OR 0.625)
; AND THEN ADJUST THE EXPONENT OF Fl. NOTE THAT THE PARTIAL PRODUCTS
; IN MULTIPLYING BY 0.8 (OR 0.625) ARE KEPT NORMALIZED. THIS IS
; ESSENTIAL TO PRESERVE 32 BIT ACCURACY IN THE FINAL RESULT.
=
5-62
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NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER.REV:C.30 JUL 86
FTOA
FTOA.MAC
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140
141
142
143
144
145
146
147
148
149
150
151
PAGE:
25
F370
F372
F374
F377
F378
F379
F37C
F370
F380
3FCE
AFC8
ACC8CC
F2
F2
ACC8CA
F4
960010
57
F381
F386
F388
F38D
F38F
A4F390CEAB
AFCE
A4F392CEAB
AFCE
56
F390
F392
F394
F396
CDCC
CCCC
0000
OOAO
$DTLO:
$DTHI:
$MILO:
$MTHI:
F398
F39D
F39F
F3A4
A4F394CEAB
AFCE
A4F396CEAB
AFCE
; FORCE EVEN ADDRESS •
OCCCD
OCCCC
0
OAOOO
$MULI0:
LD x. W(SMTLO)
PUSH X
LD x. W(SMTHI)
PUSH X
; LO WORD OF 0.625 TO STACK.
; HI WORD OF 0.625 TO STACK.
$JAMIT :
F3A6 9300
LD X. 0
F3A8 8200CCFC
F3AC 57
IFEQ B. 0
JP $JAMON
;
;
;
;
;
INIT X TO TRACK ANY POWERS OF
2 GENERATED DURING NORMALIZATION
OF PARTIAL PRODUCTS.
IS B ALREADY 0 ?
YES. SO SKIP MULTIPLY LOOP.
$JAMLP:
F3AD
F3AF
F3Bl
F3B2
F3B3
36E6
AECA
E7
07
4A
F3B4
F3B6
F3B8
F3B9
F3BA
F3BD
A9CE
AECA
E7
07
96CA08
43
•
".
CD
en
; SINCE THE MANTISSA OF Fl IS NORMALIZED. AND 0.8 (OR 0.625 IS ALSO
; NORMALIZED. EACH PRODUCT NEEDS AT MOST 1 LEFT SHIFT FOR
; RENORMALIZATION. THE SHIFTS ACCUMULATED DURING RENORMALIZATION ARE
TRACKED AND ACCOUNTED FOR IN THE CALCULATION.
POP X
; X NOW POINTS TO FI-SIGN.
PUSH A
; SAVE U ON THE STACK.
LD B. A
; MOVE V TO B ALSO.
; X POINTS TO FI-HI.
LD A. W(X-)
LD A. W(X-)
; LOAD FI-HI. X POINTS TO FI-LO.
LD K. A
; LOAD FI-LO.
LD A. W(X)
IF TMPl.0
; IS V NEGATIVE?
JP $MULI0
; YES. SO MULTIPLY V TIMES BY .625.
; GET HERE MEANS MULTIPLY V TIMES BY .8.
LD x. W($DTLO)
PUSH X
; LO WORD OF 0.8 TO STACK.
LD x. W($DTHI)
PUSH X
; HI WORD OF 0.8 TO STACK.
; GO DO MULTIPLICATION.
JP $JAMIT
• EVEN
.WORD
.WORD
.WORD
.WORD
z
; MULTIPLY.
SWAP HI AND LO WORDS OF PART. PROD.
JSR BFMUL
X A. K
SHL A
IF C
JP $ISNED
;
;
;
;
INC X
X A. K
SHL A
IF C
SET K.O
JP $OVRI
IS THERE A CARRY ?
YES. SO SKIP OVER RENORMALIZATION.
GET HERE MEANS NEED TO RENORM.
UPDATE RENORM COUNT.
SWAP HI AND LO PART. PROD.
SET BIT SHIFTED OUT FROM LO WORD.
5·63
U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
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NATIONAL SEMICONDUCTOR CORPORATION
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FTOA.MAC
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155
156
157
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160
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163
164
165
166
167
168
169
170
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174
175
176
177
178
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184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
PAGE:
26
$ISNED:
F3BE D7
F3BF AECA
RRC A
; PUT BACK SHIFTED BIT.
X A. K
$OVR1:
F3C1 AACC
F3C3 76
F3C4
F3C6
F3C8
F3CA
F3CC
F3D1
F3D2
3FCC
3FCC
AFC8
AFCA
A6FFF8C4A8
02
96CEEB
F3D5
F3D8
F3DD
F3EO
ACC8CE
A6FFFAC4A8
960010
49
F3El
F3E2
F3E7
F3E8
F3E9
E7
A6FFFAC4F8
01
04
42
F3EA E7
F3EB E7
F3EC 96CEF8
F3EF
F3F1
F3F2
F3F4
9020
5A
9D1B
9435
F3F6
F3F8
F3FA
F3FC
F3FF
3FC8
3FC8
3FC8
96D010
56
F400
F403
F404
F405
B8FFFF
07
5A
01
; IS B 0 YET ?
; NO. SO DO IT AGAIN.
DECSZ B
JP $JAMLP
$JAMON:
GET HERE MEANS MULTIPLICATION HAS BEEN DONE. SO TAKE CARE
OF EXPONENT.
POP B
POP B
GET RID OF 0.8 (OR 0.625) FROM STACK.
PUSH A
SAVE LO WORD OF PROD.
PUSH K
SAVE HI WORD OF PRODUCT.
GET F11S BINARY EXPONENT.
LD A. W(SP-08)
SET C
SUBTRACT FROM IT ANYTHING COLLECTED
SUBC A. X
; DURING RENORM.
; AND SAVE IT IN X.
LD X. A
GET V FROM THE STACK.
LD A. W(SP-06)
IF TMP1.0
IS V NEGATIVE ?
JP $ML4
YES. SO MULTIPLY V BY 4.
GET HERE MEANS MULTIPLY V BY -3.
SHL A
NOW A CONTAINS 2*V.
NOW A CONTAINS 3*V.
ADD A. W(SP-06)
COMP A
INC A
NOW A CONTAINS -3*V.
JP $ADEM
GO FIGURE FINAL EXPONENT.
$ML4:
SHL A
SHL A
NOW A CONTAINS 4*V.
$ADEM:
ADD A. X
A SHOULD NOW BE A POSITIVE INTEGER
IN THE RANGE 0 TO 32.
NOW CHECK AND SEE IF A HAS ENOUGH PRECISION.
IFGT A. 020
; NEED MORE THAN 32 BITS
JP $INCRV
; YES. SO GO INCREASE V.
NEED AT LEAST 28 BITS ?
IFGT A. 01B
JMP $GOON
YES. SO ALL IS OK. GO ON.
GET HERE MEANS NEED MORE
PRECISION. SO DECREASE V.
POP A
GET HI-PROD OFF STACK.
POP A
GET LO WORD OFF STACK.
POP A
GET MAGN. OF V.
IF TMPleO
IS V NEG. ?
JP $VUP
YES. SO GO INCR. MAGN. OF V.
; GET HERE MEANS V IS POSITIVE.
; AND NEED TO DECREMENT IT.
ADD A. OFFFF
SUBTRACT 1 FROM A.
IF C
GOT A CARRY
THEN OK.
JP $GOBAK
COMP A
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NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
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FTOA.MAC
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250
251
252
253
F406 04
F407 B700FFOO
F40B 53
PAGE:
27
INC A
LD TMP1, OFF
JP $GOBAK
; U CHANGES SIGN.
POP A
POP A
POP A
IF TMPl.O
JP $VDOWN
GET HI PROD. OFF STACK.
GET LO PROD. OFF STACK.
GET MAGN. OF V.
IS V NEGATIVE ?
; YES.
$INCRV:
F40C
F40E
F410
F412
F415
3FC8
3FC8
3FC8
960010
42
$VUP:
F416 04
F417 47
INC A
JP $GOBAK
$VDOWN:
F418 AAC8
F41A 44
F41B B7000000
DECSZ A
JP $GOBAK
LD TMP1, 0
V CHANGES SIGN.
$GOBAK:
F41F
F422
F423
F427
F429
ACC4CE
02
8204CEEB
AFCE
95B9
F42B
F42C
F42D
F430
F433
F435
F437
F43B
01
04
B80020
ACC8CE
3FCA
3FC8
8200CEFC
49
LD X, SP
SET C
SUBC X, 04
PUSH X
JMP $DIVlO
$GOON:
F43C
F43E
F43F
F441
F442
F444
F445
F447
F449
F44E
F451
F454
F455
F456
F457
AECA
C7
AECA
D7
AACE
68
AFC8
AFCA
A6FFFOC4A8
B80010
ACC8CC
00
C3
40
A6FFFAC4A8
COMP A
INC A
ADD A, 020
LD X, A
POP X
POP A
IFEQ X, 0
JP $INDUN
; NEGATE A.
; SUBTRACT IT FROM 32.
; AND MOVE IT TO X.
GET HI WORD OF PRODUCT.
; GET LO WORD OF PROD.
; IS X 0 ?
; YES, SO ALREADY A 32 BIT INTEGER.
$INTFY:
NOW ADJUST THE PRODUCT TO FORM A 32 BIT INTEGER.
X A, K
; SWAP HI AND LO WORDS.
SHR A
X A, K
RRC A
DECSZ X
JP $INTFY
; SHIFT IT RIGHT ONCE.
; X 0 YET?
; NO SO GO DO SOME MORE.
$INDUN:
; GET HERE MEANS K.A CONTAIN THE 32 BIT INTEGER THAT IS THE
; MANTISSA OF THE DECIMAL FLP NUMBER.
PUSH A
SAVE LO-INT.
SAVE HI INT.
PUSH K
GET STARTING ADDRESS OF DECIMAL STRING.
LD A, W(SP-OI0)
ADD A, 010
ADD 16 TO IT.
LD B, A
; AND MOVE IT B.
CLR A
OUTPUT TERMINATING NULL BYTE.
XS A, M(B-)
NOP
GET V.
LD A, W(SP-06)
5-65
U)
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NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
FTOA
FTOA.MAC
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281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
F45C 9FOA
DIV A, OA
F45E
F460
F463
F464
F465
F467
F46A
F46B
F46C
F46E
F471
F473
F474
F475
F477
F478
F479
F47B
F47C
X A, X
AECE
B80030
C3
40
A8CE
B80030
C3
40
902B
960010
902D
C3
40
9045
C3
40
902E
C3
40
F47D B7000AOO
F481 3FC8
F483 9FOA
F485
F488
F48A
F48C
F48F
F490
F491
F492
ACC8CA
3FC8
AFCC
ACCACC
82
OA
C8
EF
ACCCCA
3FCC
AFC8
AFCA
A8CE
B80030
C3
40
AAOO
9524
F4A7 3FC8
28
;
;
;
;
;
DIVIDE IT BY 10. QUOT. IN A,
REM. IN X.
REM TO A.
MAKE IT INTO ASCII BYTE.
OUTPUT IT.
ADD A, 030
XS A, M(B-)
NOP
LD A, X
ADD A, 030
XS A, M(B-)
; FINISHED OUTPUTING EXPONENT.
NOP
LD A, 028
; SAY EXP SIGN IS '+'.
IF TMPl.O
; NOPE, IT IS ,_'.
LD A, 02D
; OUTPUT IT.
XS A, M(B-)
NOP
LD A, 045
XS A, M(B-)
OUTPUT 'E'.
NOP
LD A, 02E
XS A, M(B-)
; OUTPUT '.'.
NOP
; NOW NEED TO OUTPUT 10 DECIMAL DIGITS.
LD TMP1, OA
; LOAD 10 INTOTMP1 AS LOOP COUNTER.
$DOLUP:
; A CONTAINS HI INT.
POP A
; DIVIDE IT BY 10. QUOT. IN A,
DIV A, OA
; REM. IN X.
LD K, A
POP A
; A CONTAINS LO INT.
PUSH B
; SAVE DEC. STR. ADDR.
LD B, K
; B CONTAINS HI-QUOT •
• BYTE 082,OA,OC8,OEF
;
;
;
;
F493
F496
F498
F49A
F49C
F49E
F4A1
F4A2
F4A3
F4A5
PAGE:
THE ABOVE 4 BYTES REPRESENT THE INSTRUCTION DIVD A, OA.
BECAUSE THE ASSEMBLER DOES NOT KNOW ABOUT IT YET, WE HAVE TO
KLUDGE IT THIS WAY.
AFTER THE DIVD, A CONTAINS THE LO-QUOT. AND X THE REM.
LD K. B
; MOVE HI-QUOT TO K.
POP B
B CONTAINS DEC. STR. ADDR.
PUSH A
; SAVE LO INT.
PUSH K
; SAVE HI INT.
LD A. X
; MOVE REM TO A.
ADD A. 030
; ASCII-FY IT.
XS A. M(B-)
; AND OUTPUT IT.
NOP
DECSZ TMP1
; IS TMP1 0 YET ?
JMP $DOLUP
; NO. GO GET SOME MORE.
GET HERE MEANS DONE WITH OUTPUTING MANTISSA.
POP A
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NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
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FTOA.MAC
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323
324
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326
327
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332
333
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337
338
339
340
341
342
343
344
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346
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351
352
F4A9
F4AB
F4AD
F4AF
F4B1
F4B3
F4B6
F4B8
F4B9
F4BB
F4BE
F4BF
F4C3
F4C5
F4C8
F4CA
F4CC
F4CE
3FC8
3FC8
3FC8
3FCA
9020
96CA10
902D
C6
AFCA
ACC4CE
02
8206CEEB
AFCE
B5FBB4
3FC4
3FCC
3FCE
3C
+
PAGE:
POP A
POP A
POP A
POP K
LD A, 02D
IF K.O
LD A, 02D
ST A, M(B)
PUSH K
LD X, SP
SET C
SUBC X, 06
PUSH X
JSR FPAK
POP SP
POP B
POP X
RET
29
GET SOME GARBAGE OFF THE STACK.
GET F1-EXP.F1-SIGN TO K.
LOAD SP INTO A.
IF MAINT. IS NEG. LOAD '-'.
OUTPUT SIGN.
F1-EXP.F1-SIGN BACK ON STACK.
: X POINTS TO F1-LO.
: PACK IT, SO RESTORING K AND A.
: RESTORE B.
: RESTORE X.
F4CF
F4D1
F4D4
F4D8
F4D9
F4DA
AFC8
ACCCCE
8210CEF8
00
03
9210
F4DC
F4DE
F4DF
F4E1
F4E2
F4E4
F4E6
F4E8
90FF
D3
AACC
65
3FC8
3FCC
3FCE
3C
$NAN:
GET HERE MEANS F1 IS A NAN.
PUSH A
LD X, B
ADD X, 010
CLR A
X A, M(X-)
LD B, 010
$NANLP:
LD A, OFF
X A, M(X-)
DECSZ B
JP $NANLP
POP A
POP B
POP X
RET
AFC8
ACCCCE
8210CEF8
00
D3
9030
D3
9030
D3
902B
D3
9045
$ZERO:
GET HERE MEANS F1 IS ZERO.
PUSH A
LD X, B
: X CONTAINS DECIMAL STRING ADDR.
ADD X, 010
CLR A
OUTPUT TERMINATING NULL BYTE.
X A, M(X-)
LD A, 030
LOAD 0 INTO A.
X A, M(X-)
LD A, 030
X A, M(X-)
: OUTPUT 00 FOR EXPONENT.
LD A, 02B
: LOAD '+' SIGN.
X A, M(X-)
LD A, 045
: LOAD 'E'
F4E9
F4EB
F4EE
F4F2
F4F3
F4F4
F4F6
F4F7
F4F9
F4FA
F4FC
F4FD
5·67
•
U)
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NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
FTOA
FTOA.MAC
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356
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361
362
363
364
365
366
367
368
369
F4FF
F500
F502
F503
D3
902E
D3
920A
F505
F507
F508
F50A
F508
F50D
F50E
F510
F512
F514
9030
D3
AACC
65
9020
D5
3FC8
3FCC
3FCE
3C
PAGE:
X A, M(X-)
LD A, 02E
X A, M(X-)
LD B, OA
30
LOAD
$ZERLP:
LD A, 030
X A, M(X-)
DECSZ B
JP $ZERLP
LD A, 020
X A, M(X)
POP A
POP B
POP X
RET
LOAD SP.
.END
5-68
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NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
FTOA
FADD.MAC
33
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2
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7
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31
SUBROUTINE TO ADD/SUBTRACT TWO SP FLOATING POINT NUMBERS.
C Fl + F2 OR C Fl - F2
=
=
Fl IS STORED IN THE IEEE FORMAT IN REGS K AND A.
THE HIGH WORD OF Fl WILL BE REFERRED AS FI-Rl AND IS IN K.
THE LOW WORD OF Fl WILL BE REFERRED TO AS FI-RO AND IS IN A.
F2 IS STORED IN THE IEEE FORMAT ON THE STACK. IF SP IS THE
STACK POINTER ON ENTRY, THEN
THE HIGH WORD OF F2, REFERRED TO AS F2-Rl IS AT SP - 4 AND
THE LOW WORD OF F2, REFERRED TO AS F2-RO IS AT SP - 6.
C IS RETURNED IN THE IEEE FORMAT IN REGS K AND A.
FSUB:
F515
F517
F51C
F51E
F523
F526
F528
F52A
F52C
F52E
F530
F532
F534
F535
F537
F539
F53C
F541
ABOO
A6FFFAC4A8
AFC8
A6FFFAC4A8
BB8000
AFC8
A800
3009
ABOO
3FC8
3FC8
A800
3C
AFCE
AFCC
ACC4CE
86FFF6CEF8
ACCEOO
F544 B5FAF9
F547 07
F548 B4FAC4
F54B
F54E
F551
F555
F558
ACCACC
ACC8CE
A20200A8
ACC8CA
AECE
z
.a::a.
(X)
Q)
.FORM, 'FADD.MAX'
.INCLD FADD.MAC
.TITLE FADD
• LOCAL
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
PAGE:
ST A, TMPl
LD A, W(SP-06)
PUSH A
LD A, W(SP-06)
XOR A, 08000
PUSH A
LD A, TMPl
JSR FADD
ST A, TMPl
POP A
POP A
LD A, TMPl
RET
;
;
;
;
;
;
LOAD F2-RO.
AND SAVE ON STACK.
LOAD F2-Rl.
CHANGE THE SIGN.
AND SAVE ON THE STACK.
RESTORE A.
CALL THE ADD ROUTINE.
SAVE A.
GET RID OF JUNK
FROM THE STACK.
; RESTORE A.
FADD:
SAVE ADDRESS OF F2-RO IN TMP1.
PUSH X
; SAVE X ON ENTRY.
PUSH B
; AND B ON ENTRY.
LD X, SP
ADD X, OFFF6
; SUBTRACT 10.
LD TMP1, X
; AND SAVE IN TMP1.
CHECK AND SEE IF Fl IS A NAN.
JSR FNACHK
+
IF C
JMPL FNAN
; Fl IS A NAN.
CHECK AND SEE IF F2 IS A NAN.
LD B, K
LD X, A
LD A, W(TMPl+2)
LD K, A
X A, X
5-69
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NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
FADD
FADD.MAC
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83
84
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87
88
89
90
91
92
93
94
95
96
97
98
99
100
F55A B5FAE3
F55D 07
F55E B4FAAE
+
F561
F564
F565
F566
F569
F56B
F56D
B5FAED
06
48
ACCCCA
3FCC
3FCE
3C
+
F56E
F571
F574
F575
F567
F57A
F57D
F580
F582
F584
ACCCCA
B5FADD
06
4F
A20200AB
ACC8CA
ADOOA8
3FCC
3FCE
3C
F585
F588
F58C
F58E
F591
F594
F597
F598
F599
F59B
F59C
F59E
ACC4CE
8210C4F8
AFCE
B5FADO
ACOOCC
ACCEOO
EO
40
AECA
E4
AECA
B5FACO
F5A1
F5A2
F5A5
F5A6
F2
ACOOCC
E2
40
F5A7
F5A8
F5AB
F5BO
F5B1
F5B2
F5B5
F2
B9FFOO
A6FFFCC4AB
E2
40
B9FFOO
02
+
+
PAGE:
32
JSR FNACHK
IF C
JMPL FNAN
; F2 IS NAN.
CHECK AND SEE IF F2 IS ZERO.
JSR FZCHK
IFN C
JP $F1CHK
; F2 IS NOT ZERO. CHECK Fl.
LD K, B
; F2 IS ZERO, SO ANSWER IS Fl.
POP B
POP X
RET
CHECK AND SEE IF F1 IS ZERO.
$F1CHK:
LD K, B
; RESTORE F1-R1 FROM B.
JSR FZCHK
IFN C
JP $NTZERO
JUMP SINCE F1 IS ALSO NOT ZERO.
LD A, W(TMP1+2)
GET HERE MEANS F1 IS ZERO,
LD K, A
SO ANSWER IS F2.
LD A, W(TMP1)
POP B
POP X
RET
GET HERE MEANS NORMAL ADDITION.
; UNPACK F1 AND F2.
$NTZERO:
LD X, SP
; X POINTS TO F1-LO.
ADD SP, 010
; MOVE SP PAST LOCAL STORAGE.
PUSH X
; SAVE SP ON STACK FOR QUICK RETURN.
JSR FUNPAK
; UNPACK Flo
LD B, TMP1
; B NOW POINTS TO F2-RO.
LD TMP1, X
; TMP1 NOW POINTS TO F2-LO.
LDS A, W(B+)
; LOAD F2-RO INTO A.
NOP
X A, K
+
LD A, W(B)
X A, K
; LOAD F2-R1 INTO K.
JSR FUNPAK
; UNPACK F2.
SET X TO POINT TO F2-SIGN AND B TO POINT TO F1-SIGN.
LD A, W(X-)
LD B, TMP1
LDS A, W(B-)
NOP
COMPARE F1-EXP AND F2-~XP.
LD A, W(X-)
; LOAD F2-EXP.F2-SIGN INTO A.
AND A, OFFOO
; MASK OUT SIGN.
ST A, W(SP-4)
; SAVE IN C-SIGN.C-EXP.
LDS A, W(B-)
NOP
; LOAD F1-EXP.F1-SIGN INTO A.
AND A, OFFOO
; CHANGE TO F1-EXP.00000000.
SET C
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F5B6 A6FFFCC4EB
F5BB 06
F5BC 942D
F5BE
F5C2
F5C7
F5CC
F5DO
80C9CAAB
A6FFFCC4FB
A6FFFCC4AB
8217CAFD
51
F5D1 8200CAFC
F5D5 943B
F5D7
F5D8
F5D9
F5DA
F5DB
F5DC
F5DD
F5DF
F5EO
F4
C7
F3
F4
D7
F1
AACA
68
9430
F5E2
F5E3
F5E4
F5E5
F5E6
F5E7
F5E8
F5E9
FO
00
F3
00
F3
00
F1
9427
F5EB
F5EC
F5ED
F5F1
F5F5
01
04
80C9CAAB
8217CAFD
51
F5F6 8200CAFC
F5FA 57
F5FB
F5FC
F5FD
F5FE
F5FF
F600
F601
F602
E4
C7
E3
40
E4
D7
E1
40
PAGE:
33
SUBC A, W(SP-4) ; SUBTRACT F2-EXP.00000000.
IFN C
JMP $F2GTR
; F2-EXP IS BIGGER THAN F1-EXP.
GET HERE MEANS F1-EXP IS BIGGER THAN F2-EXP.
LD K, H(A)
; SAVE DIFF. IN K TO BE USED AS LOOP COUNTER.
ADD A, W(SP-4)
ST A, W(SP-4)
; RESTORE F1-EXP AND STORE IN C-SIGN.
IFGT K. 017
; K GT 23-DEC MEANS F2 GETS ZEROED IN SHIFTS.
JP $ZROF2
; LOOP TO SHIFT F2 INTO ALIGNMENT.
IFEQ K. 0
JMP $ADDMN
; K = 0 MEANS DONE SHIFTING.
$LOOP2:
LD A. W(X)
SHR A
X A, W(X-)
LD A, W(X)
RHCA
X A, W(X+)
DECSZ K
JP $LOOP2
JMP $ADDMN
SZROF2:
SET F2 MANTISSA TO O.
LD A. W(X+)
; X POINTS TO F2-EXP.F2-SIGN.
CLR A
; AND STORE IT BACK.
X A. W(X-)
CLR A
X A, W(X-)
CLR A
X A, W(X+)
JMP $ADDMN
; F2 EXPONENT IS GREATER THAN F1 EXPONENT.
$F26TR:
COMP A
INC A
; CHANGE DIFF IN EXP TO POSITIVE.
LD K, H(A)
; LOAD K WITH LOOP COUNTER.
IFGT K, 017
; F1 MANT. REDUCED TO 0 IN SHIFTS.
JP $ZROF1
; LOOP TO SHIFT F1 MANT INTO ALIGNMENT.
IFEQ K, 0
; K=O MEANS DONE SHIFTING.
JP $ADDMN
$LOOP1:
LD A, W(B)
SHR A
XS A, W(B-)
NOP
LD A, W(B)
RRC A
XS A. W(B+)
NOP
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F603 AACA
F605 6A
F606 4B
PAGE:
DECSZ K
JP SLOOPl
JP $ADDMN
$ZROF1:
F607
F608
F609
F60A
F60B
F60C
F60D
F60E
F60F
F610
F6ll
EO
40
00
E3
40
00
E3
40
00
El
40
F612
F613
F614
F615
F616
F617
F619
EO
40
FO
D4
D8
9COO
9451
F61B
F61C
F61D
F61E
F61F
F620
F621
F622
F623
F624
F626
F627
F628
F629
F62B
F62C
F62D
F2
F2
E2
40
E2
40
EO
40
02
8FEB
Fl
EO
40
8FEB
Fl
07
55
F62E
F633
F635
F636
F637
F638
F639
F63A
A6FFFCC4A8
8FDA
F3
F4
Dl
F3
F4
01
34
; SET Fl MANT TOO.
LOS A, W(B+)
; B POINTS TO Fl-EXP.Fl-SIGN.
NOP
CLR A
XS A, W(B-)
STORE IT BACK.
NOP
CLR A
XS A, W(B-)
NOP
CLR A
XS A, W(B+)
NOP
; DETERMINE IF MANTISSAS ARE TO BE ADDED OR SUBTRACTED.
$ADDMN:
; B POINTS TO Fl-HI, X TO F2-HI.
LDS A, W(B+)
NOP
LD A, W(X+)
LD A, M(X)
; LOAD F2-SIGN.
XOR A, M(B)
; XOR WITH Fl-SIGN.
IFEQ A, 0
JMP STRADD
; SAME SIGN SO GO TO ADD MANTISSA.
GET HERE MEANS TRUE SUBTRACT OF MANTISSA.
LD A, W(X-)
LD A, W(X-)
; X POINTS TO F2-LO.
LDS A, W(B-)
NOP
LDS A, W(B-)
NOP
; B NOW POINTS TO Fl-LO.
LDS A, W(B+)
NOP
; A NOW CONTAINS Fl-LO.
SET C
SUBC A, W(X)
; SUBTRACT F2-LO.
X A, W(X+)
LDS A, W(B+)
; A CONTAINS Fl-HI.
NOP
SUBC A, W(X)
; SUBTRACT F2-HI.
XA, W(X+)
IF C
JP $F1SIN
; Fl GE F2, SO SIGN IS Fl-SIGN.
GET HERE MEANS Fl LT F2, SO SIGN ISF2-SIGN.
LD A, W(SP-4)
OR A, M(X)
X A, W(X-)
C-EXP.C-SIGN HAS BEEN DETERMINED.
LD A, W(X)
COMP A
X A, W(X-)
LD A, W(X)
COMP A
5-72
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F63B
F63E
F63F
F640
F642
B80001
Fl
07
8FA9
47
F643 A6FFFCC4A8
F648 DA
F649 F3
F64A
F64D
F64E
F64F
F650
F651
ACCECC
EO
40
CO
40
9118
F653
F654
F655
F656
F658
F659
F65A
F65B
F65C
F65D
F65F
F662
F663
F4
E7
07
9448
F3
F4
E7
Fl
07
8F08
ADCC8A
43
B4F9B8
F666 AACA
F668 75
F669 B4F9B2
F66C
F66D
F66E
F66F
F670
F6n
F672
F673
F674
F675
F676
F677
F678
E2
40
E2
40
F2
F2
F4
F8
Fl
EO
40
F4
E8
PAGE:
35
z
oI:ao
CO
en
ADD At 01
X At W(X+)
IF C
INC W(X)
JP $ANORM
; GET HERE MEANS Fl GE F~.
$F1SIN:
LD At W(SP-4)
OR At M(B)
X At W(X-)
NORMALIZE THE MANTISSA.
$ANORM:
LD B X
B POINTS TO C-HI.
LDS At W(B+)
NOP
LDS At M(B+)
NOP
B NOW POINTS TO C-EXP BYTE.
SET UP LOOP LIMIT OF 24-DEC IN K.
LD Kt 018
$NLOOP:
LD At W(X)
SHL A
IF C
CARRY MEANS NORMALIZED.
SO JUMP TO ROUNDING CODE.
JMP $ROUND
X At W(X-)
LD At W(X)
SHL A
X At W(X+)
IF C
SET W(X).O
; ADJUST EXPONENT.
DECSZ M(B)
JP $OVl
JMPL UNDFL
C-EXP ZERO MEANS UNDERFLOW.
$OV1:
DECSZ K
DECREMENT LOOP COUNTER.
JP $NLOOP
; GO BACK TO LOOP.
JMPL UNDFL
; UNDERFLOW
;GET HERE MEANS TRUE ADDITION OF MANTISSA.
$TRADD:
LDS At W(B-)
NOP
LDS At W(B-)
NOP
B NOW POINTS TO Fl-HI.
LD At W(X-)
LD At W(X-)
LOAD F2-LO INTO A.
LD At W(X)
ADD Fl-LO.
ADD At WeB)
STORE IN F2-LO.
X At W(X+)
LDS At W(B+)
B NOW POINTS TO Fl-HI.
NOP
LOAD F2-HI INTO A.
LD At W(X)
ADD Fl-HI WITH CARRY FROM LO ADD.
ADC At WeB)
t
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F679
F67A
F67B
F67C
F681
F683
F684
07
4A
Fl
A6FFFCC4A8
8FDA
F3
5B
F685
F686
F687
F688
F689
F68A
F68B
F690
F693
F694
F697
F69A
F69D
F69F
D7
F3
F4
D7
Fl
FO
A6FFFCC4A8
B80100
07
B4F998
BDFEFF
B4F992
8FDA
F3
F6AO B5F9FB
F6A3
F6A4
F6A5
F6A7
F6AA
F6AC
F6AF
F6BO
F6Bl
F6B4
F6B6
F6B8
F6BA
DO
D2
9COO
B4F974
90FE
B4F980
F2
F2
B5F9C8
3FC4
3FCC
3FCE
3C
+
PAGE:
36
IF C
IF CARRY. NEED TO INCREASE EXP.
JP $ADJEX
X A. W(X+)
STORE RESULT IN F2-HI.
LD A. W(SP-4)
GET C-EXP.OOOOOOOO.
INTRODUCE SIGN.
OR A. M(X)
STORE IN F2-EXP.F2-SIGN.
K A. W(X-)
JP $ROUND
: GET HERE MEANS NEED TO INCREASE EXP BY 1.
$ADJEX:
RRCA
X A. W(X-)
LD A. W(X)
RRC A
X A. W(X+)
: X NOW POINTS TO F2-EXP.F2-SIGN.
LD A. W(X+)
GET C-EXP.OOOOOOOO.
LD A. W(SP-4)
; INCREASE EXP BY 1.
ADD A. 0100
IF C
JMPL OVRFL
IFGT A. OFEFF
IS BIASED EXPONENT 255-DEC ?
JMPL OVRFL
OR A. M(X)
X A. W(X-)
; NEED TO ROUND THE RESULT. X POINTS TO C-HI.
$ROUND:
JSRL SROUND
; FINAL CHECK OF EXPONENT.
LD A. M(X+)
; X NOW POINTS TO C-EXP.
LD A. M(X-)
IFEQ A. 0
JMPL UNDFL
IFGT A. OFE
JMPL OVRFL
LD A. W(X-)
X NOW POINTS TO C-LO.
LD A. W(X-)
JSR FPAK
PACK C.
SET UP SP FOR RETURN.
POP SP
POP B
POP X
RET
• END
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.FORM 'FMULT.MAC'
.INCLD FMULT.MAC
.TITLE FMULT
.LOCAL
1
2
SUBROUTINE TO MULTIPLY TWO SP FLOATING POINT NUMBERS.
C Fl*F2
=
5
6
7
8
Fl IS STORED IN THE IEEE FORMAT IN REGS K AND A.
THE HIGH WORD OF F1 WILL BE REFERRED AS FI-Rl AND IS IN K.
THE LOW WORD OF Fl WILL BE REFERRED TO AS FI-RO AND IS IN A.
9
10
F2 IS STORED IN THE IEEE FORMAT ON THE STACK. IF SP IS THE
STACK POINTER ON ENTRY, THEN
THE HIGH WORD OF F2, REFERRED TO AS F2-Rl IS AT SP - 4 AND
THE LOW WORD OF F2, REFERRED TO AS F2-RO IS AT SP - 6.
11
12
13
14
15
16
17
18
19
20 F6BB AFCE
21 F6BD AFCC
C IS RETURNED IN THE IEEE FORMAT IN REGS K AND A.
; REGS. X AND B ARE PRESERVED.
FMULT:
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
F6BF ACC4CE
F6C2 86FFF6CEF8
FSC7 ACCEOO
F6CA B5F973
F6CD 07
F6CE B4F93E
F6D1
F6D4
F6D7
F6DB
F6DE
F6EO
F6E3
F6E4
ACCACC
ACC8CE
A20200A8
ACC8CA
AECE
B5F95D
07
B4F928
F6E7 B5F967
F6EA 07
F6EB 94DC
F6ED
F6FD
F6F3
F6F4
ACCCCA
B5F95E
07
94D3
+
PUSH X
; SAVE X ON ENTRY.
PUSH B
; SAVE B ON ENTRY.
SAVE ADDRESS OF F2-RO IN TMP1.
LD X, SP
ADD X, OFFF6
; SUBTRACT 10.
LD TMP1, X
; SAVE IN TMP!.
CHECK AND SEE IF F1 IS A NAN.
JSR FNACHK
IF C
JMPL FNAN
; Fl IS A NAN.
CHECK AND SEE IF F2 IS A NAN.
LD B, K
LD X, A
LD A, W(TMP1+2)
LD K, A
X A, X
+
+
+
A
en
35
3S
3
4
z
Q)
JSR FNACHK
IF C
JMPL FNAN
; F2 I S NAN.
CHECK AND SEE IF F2 IS ZERO.
JSR FZCHK
IF C
JMP $CZERO
; F2 IS ZERO.
CHECK AN SEE IF F1 IS ZERO.
LD K, B
; RESTORE FI-Rl FROM B.
JSR FZCHK
IF C
JMP $CZERO
; Fl IS ZERO.
GET HERE MEANS NORMAL MULTIPLICATION.
; UNPACK Fl AND F2.
5-75
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F6F6
F6F9
F6FD
F6FF
F702
F705
F708
F709
F70A
F70C
F70D
F70F
ACC4CE
8210C4F8
AFCE
B5F95F
ACOOCC
ACCEOO
EO
40
AECA
E4
AECA
B5F94F
F712
F713
F716
F717
F2
ACOOCC
E2
40
F718
F719
F71A
F71D
F71J!:
F721
F722
F725
F726
F727
F728
F72A
F72B
F72D
F730
F731
F4
C'7
ACC8CA
E4
B9FFOO
C7
96CAF8
F6
E2
40
99FF
C7
8FFB
B8C080
07
46
F732
F733
F734
F737
E7
07
B4F8E7
C7
F738
F739
F73A
F73D
F740
F743
E7
07
B4F8F2
96C817
96C808
F3
F744 F2
+
PAGE:
38
;
;
;
;
;
;
;
LD X. SP
ADD SP. 010
PUSH X
JSR FUNPAK
LD B. TMPl
LD TMP1. X
LOS A. W(B+)
NOP
X POINTS TO Fl-LO.
MOVE SP PAST LOCAL STORAGE.
SAVE SP ON STACK FOR QUICK RETURN.
UNPACK Flo
B NOW POINTS TO F2-RO.
TMPl NOW POINTS TO F2-LO.
LOAD F2-RO INTO A.
X A. K
LD A. WeB)
+
X A. K
; LOAD F2-Rl INTO K.
JSR FUNPAK
; UNPAK F2.
SET X TO POINT TO F2-SIGN AND B TO POINT TO Fl-SIGN.
LD A. W(X-)
LD B. TMPl
LDS A. W(B-)
NOP
COMPUTE C-EXP AND C-SIGN AND STORE IN F2-EXP AND F2-SIGN.
; A IS (EEEEEEEE-F2).(SSSSSSSS-F2)
LD A. W(X)
; SHR SINCE SUM OF EXPS CAN BE 9 BITS.
SHR A
; K IS (DEEEEEEEE-F2).(SSSSSSS-F2)
LD K. A
: A IS (EEEEEEEE-Fl). (SSSSSSSS-Fl)
LD A. WeB)
; MASK OUT SIGN BITS.
AND A. OFFOO
; A IS (DEEEEEEEE-Fl).(OOOOOOO)
SHR A
; A IS (EEEEEEEEE-C) • (SSSSSSS-F2)
ADD A. K
; STORE IN F2-SIGN.
ST A. W(X)
; A IS (EEEEEEEE-Fl).(SSSSSSSS-Fl)
LOS A. W(B-)
NOP
; MASK OUT EXP BITS.
AND A. OFF
SHR A
; A IS (OOOOOOOOOSSSSSSS-Fl)
; A IS (EEEEEEEEESSSSSSS-C)
XOR A. W(X)
REMOVE EXCESS BIAS OF 127-DEC FROM EXP.
ADD A. OC080
IF C
JP $EXCH2
IF CARRY. THEN NO UNDERFLOW NOW
CHECK TO SEE IF EXP IS ZERO. IF NOT. UNDERFLOW FOR SURE.
SHL A
IF C
JMPL UNDFL
; UNDERFLOW. SO JUMP.
SHR A
; RESTORE BIT SHIFTED OUT (0).
CHECK FOR EXPONENT OVERFLOW.
$EXCH2:
SHL A
IF C
IF C IS 1.
THEN OVERFLOW FOR SURE.
JMPL OVRFL
IF A.7
SET A.O
RESTORE LAST BIT OF SIGN.
STORE C-EXP. C-SIGN IN F2-EXP.F2-SIGN.
X A. W(X-)
MULTIPLY THE MANTISSA.
FIRST COMPUTE Fl-HI*F2-HI.
LD A. W(X-)
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F745
F748
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F74E
F750
ACCEOO
FE
A6FFFAC4AB
AECE
A6FFFCC4AB
F755
F758
F759
F75C
F75D
F75F
F764
F769
F76A
ACOOCE
FO
ACCEOO
FE
AECE
A6FFFAC4F8
A6FFFAC4AB
07
A6FFFCC4A9
F76F
F770
F771
F774
F775
F776
F778
F77D
F782
F787
F788
E2
40
ACOOCE
F4
FE
AECE
A6FFFAC4F8
A6FFFAC4AB
A6FFFCC4AB
07
04
F789 ACOOCE
F78C BD7FFF
F78F 4D
F790
F791
F792
F797
F798
F799
F79A
F79C
E7
F3
A6FFFAC4AB
E7
F1
07
8F08
51
F79D
F79E
F7A3
F7A4
F7A5
F7A6
F7A9
F7AA
F3
A6FFFAC4A8
F1
FO
F4
B80100
07
B4F882
PAGE:
LD TMP1, X
MULT A, W(B)
ST A, W(SP-6)
39
TMP1 NOW POINTS TO F2-LO.
STORE LOW WORD OF PRODUCT ON STACK.
X A, X
ST A, W(SP-4)
STORE HIGH WORD OF PRODUCT ON STACK.
NOW COMPUTE F1-HI·F2-LO.
LD X, TMP1
LD A, W(X+)
LD TMP1, X
TMP1 NOW POINTS TO F2-HI.
MULT A, W(B)
X A, X
ADD A, W(SP-6)
ADD LOW WORD OF LAST PROD. TO HIGH WORD.
ST A, W(SP-6)
IF C
INC W(SP-4)
; IF CARRY, INCREASE HIGH WORD BY 1.
FINALLY COMPUTE F1-LO·F2-HI.
LDS A, W(B-)
; ADJUST B TO POINT TO F1-LO.
NOP
LD X, TMP1
LD A, W(X)
MULT A, W(B)
X A, X
ADD A, W(SP-6)
ST A, W(SP-6)
LD A, W(SP-4)
IF C
INC A
; ADD LOW WORD ACCUMULATED SO FAR.
; A CONTAINS HIGH WORD OF PRODUCT.
IF CARRY ON LAST LOW WORD ADD,
; THEN INCREASE HIGH WORD.
MANTISSA MULTIPLICATION DONE. NOW CHECK FOR NORMALIZATION.
LD X, TMP1
IFGT A, 07FFF
IS MSB OF PRODUCT 1 ?
YES, INCREASE MANTISSA.
JP $EXINC
NEED TO SHIFT MANTISSA LEFT BY 1 BIT.
SHL A
X A, W(X-)
LD A, W(SP-6)
SHL A
X A, W(X+)
; DID SHIFT OF LOW WORD PUSH OUT A 1 ?
IF C
; YES SO SET LSB OF HIGH WORD.
SET W(X).O
; GO TO ROUNDING CODE.
JP $ROUND
$EXINC:
; NEED TO INCREASE EXPONENT BY 1. REMEMBER X POINTS TO F2-HI.
X A, W(X-)
; A CONTAINS HIGH WORD, X POINTS TO F2-LO.
LD A, W(SP-6)
GET LOW WORD.
X A, W(X+)
STORE LOW WORD.
LD A, W(X+)
LD A, W(X)
GET C-EXP.C-SIGN
ADD A, 0100
INCREASE C-EXP.
IF C
JMPL OVRFL
EXPONENT OVERFLOW.
5·77
•
I
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
FMULT
FMULT.MAC
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
F7AD F3
F7AE B5F8ED
F7B1
F7B2
F7B3
F7B5
F7B8
F7BA
F7BD
F7BE
F7BF
F7C2
F7C4
F7C6
F7C8
DO
D2
9COO
B4F866
9DFE
B4F872
F2
F2
B5F8BA
3FC4
3FCC
3FCE
3C
F7C9
F7CA
F7CD
F7CF
F7D1
ACC8CA
3FCC
3FCE
3C
00
+
PAGE:
40
X A, W(X-)
NO OVERFLOW, SO SAVE C-EXP.C-SIGN.
; ROUNDING CODE.
$ROUND:
JSRL SROUND
FINAL CHECK OF EXPONENT.
LD A, M(X+)
; X NOW POINTS TO C-EXP.
LD A, M(X-)
IFEQ A, 0
JMPL UNDFL
IFGT A, OFE
JMPL OVRFL
LD A, W(X-)
LD A, W(X-)
X NOW POINTS TO C-LO.
JSR FPAK
PACK C.
POP SP
SET UP SP FOR RETURN.
POP B
POP X
RET
EXCEPTION HANDLING.
C IS ZERO B'COS ONE OF F1 OR F2 IS ZERO.
$CZERO:
CLR A
LD K, A
POP B
POP X
RET
.END
5-78
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
FMULT
FDIV.MAC
37
38
41
2
3
4
=
6
7
F1 IS STORED IN THE IEEE FORMAT IN REGS K AND A.
THE HIGH WORD OF F1 WILL BE REFERRED AS F1-R1 AND IS IN K.
THE LOW WORD OF F1 WILL BE REFERRED TO AS F1-RO AND IS IN A.
8
9
F2 IS STORED IN THE IEEE FORMAT ON THE STACK. IF SP IS THE
STACK POINTER ON ENTRY, THEN
THE HIGH WORD OF F2, REFERRED TO AS F2-R1 IS AT SP - 4 AND
THE LOW WORD OF F2, REFERRED TO AS F2-RO IS AT SP - 6.
C IS RETURNED IN THE IEEE FORMAT IN REGS K AND A.
FDIV:
F7D2 AFCE
F7D4 AFCC
F7D6 ACC4CE
F7D9 86FFF6CEF8
F7DE ACCEOO
F7E1 85F85C
F7E4 07
F7E5 B4F827
F7E8
F7EB
F7EE
F7F2
F7F5
F7F7
F7FA
F7FB
ACCACC
ACC8CE
A20200A8
ACC8CA
AECE
B5F846
07
B4F811
F7FE B5F850
F801 07
F802 B4F7FB
F805
F808
F80B
F80C
ACCCCA
B5F846
07
94F1
F80E ACC4CE
+
+
+
+
.
0l:Io
en
SUBROUTINE TO DIVIDE TWO SP FLOATING POINT NUMBERS.
C F1/F2
5
»
z
Q)
.FORM 'FDIV.MAC'
.INCLD FDIV.MAC
.TITLE FDIV
.LOCAL
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
PAGE:
PUSH X
PUSH B
SAVE ADDRESS OF F2-RO IN TMP1.
LD X, SP
ADD X, OFFF6
; SUBTRACT 10.
LD TMP1, X
; AND SAVE IN TMP1.
CHECK AND SEE IF F1 IS A NAN.
JSR FNACHK
IF C
JMPL FNAN
; F1 IS A NAN.
CHECK AND SEE IF F2 IS A NAN.
LD B, K
LD X, A
LD A, W(TMP1+2)
LD K. A
X A. X
JSR FNACHK
IF C
JMPL FNAN
; F2 I S NAN.
CHECK AND SEE IF F2 IS ZERO.
JSR FZCHK
IF C
JMPL DIVBYO
; F2 IS ZERO.
CHECK AND SEE IF F1 IS ZERO.
LD K. B
; RESTORE F1-R1 FROM B.
JSR FZCHK
IF C
JMP $CZERO
; F1 IS ZERO.
GET HERE MEANS NORMAL DIVISION.
; UNPACK F1 AND F2.
; X POINTS TO F1-LO.
LD X. SP
5-79
to .------------------------------------------------------------------------------------,
co
"1::1'
:Z
FI-HI ?
YES, SO ALL IS WELL.
GET HERE MEANS NEED TO SHR Fl,
AND INCREASE ITS EXPONENT.
GET FI-HI.
B POINTS TO Fl-EXP.Fl-SIGN.
SWAP Fl-EXP.Fl-SIGN AND Fl-HI.
INCREASE Fl-EXP BY 1.
STORE BACK IN Fl-EXP.Fl-SIGN.
B POINTS TO Fl-HI.
LOAD Fl-HI.
STORE BACK IN Fl-HI.
B POINTS TO Fl-LO.
LOAD Fl-LO.
; PUT IT BACK IN Fl-LO.
; B POINTS TO Fl-HI.
$FEXSN:
DETERMINE C-EXP AND C-SIGN.
LD A, W(X+)
X POINTS TO F2-EXP.F2-SIGN.
LDS A, W(B+)
B POINTS TO Fl-EXP.Fl-SIGN.
NOP
LD A, W(X)
LOAD F2-EXP.F2-SIGN.
AND A, OFFOO
; MASK OUT THE SIGN.
SHR A
; ALLOW 9 BITS FOR EXP CALCULATIONS.
LD K, A
: SAVE IT IN K.
5-80
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
FDIV
FDIV.MAC
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
PAGE:
F855
F856
F859
F85A
F85B
E4
B9FFOO
C7
02
96CAEB
LD A, W(B)
AND A, OFFOO
SHR A
SET C
SUBC A, K
F85E
F862
F863
F864
F868
F869
F86C
F86D
F86E
F86F
F872
F875
B7000000
E7
07
B700FFOO
D7
B83FOO
E7
06
49
960010
B4F7A9
B4F7B7
LD TMP1, 0
SHL A
IF C
LD TMP1, OFF
RRC A
ADD A, 03FOO
SHL A
IFN C
JP $FSIGN
IF TMPl.O
JMPL UNDFL
JMPL OVRFL
F878
F87B
F87E
F880
F883
F885
F886
F888
F889
F88B
F88E
BCFFOO
B4F7Bl
9COO
B4F79B
ABOO
F4
99FF
FB
99FF
9600FA
F3
F88F F2
F890 E2
F891 40
43
LOAD FI-EXP.FI-SIGN.
MASK OUT SIGN.
; SUBTRACT THE EXPONENTS.
; NOTE THAT NOW THE MS 9 BITS
; OF A CONTAIN A 2'S COMPo INTEGER.
;
;
;
;
;
;
SAVE SIGN OF NUMBER IN TMP1.
RESTORE IEEE BIAS.
MAKE EXPONENT 8 BITS.
NO CARRY?
THEN ALL IS WELL.
WAS EXP NEGATIVE BEFORE ?
YES, SO UNDERFLOW.
; OTHERWISE OVERFLOW.
$FSIGN:
C-EXP HAS BEEN COMPUTED. NOW FIND C-SIGN.
; BUT FIRST TAKE CARE OF SPECIAL OVER/UNDERFLOW CASES.
IFEQ. A, OFFOO
JMPL OVRFL
IFEQ. A, 0
JMPL UNDFL
SAVE C-EXP.OOOOOOOO IN TMP1.
ST A, TMPl
LD A, W(X)
LOAD F2-EXP.F2-SIGN.
AND A, OFF
MASK OUT F2-EXP.
XOR A, W(B)
A NOW HAS FI-EXP.C-SIGN.
AND A, OFF
MASK OUT FI-EXP.
OR A, TMPl
BRING IN C-EXP.
STORE IN F2-EXP.F2-SIGN.
X A, W(X-)
; X POINTS TO F2-HI.
X POINTS TO F2-LO.
LD A, W(X-)
; B POINTS TO FI-HI.
LDS A, W(B-)
NOP
NOW DO THE MANTISSA DIVISION.
F892 FO
F893 ACCEOO
F896 FE
LD A, W(X+)
LD TMP1, X
MULT A, W(B)
; LOAD F2-LO. X POINTS TO F2-HI.
; SAVE ADDRESS OF F2-HI IN TMP1.
COMPUTE F2-LO*FI-HI.
; X CONTAINS MS WORD AND A IS LS WORD.
F897 AECC
F899 AEOO
F89B AECC
X A, B
X A, TMPl
X A, B
; A POINTS TO FI-HI, B CONTAINS LS WORD.
; A POINTS TO F2-HI, TMPl POINTS TO FI-HI.
A CONTAINS LS WORD, B POINTS TO F2-HI.
F890 EF
.BYTE OEF
DIVD A, W(B) - KLUDGED !!
5-81
•
CD
CO
"11:1'
Z•
c(
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
FDIV
FDIV.MAC
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
F89E
F8A1
F8A3
F8A5
F8A7
F8A8
F8A9
F8AA
F8AB
F8AC
F8AF
F8B2
F8B3
F8B4
F8B5
F8B7
ACC8CA
A8CC
AEOO
AECC
E2
40
EO
40
02
96CAEB
ACC8CE
E4
06
05
AECE
ACOOCC
PAGE:
LD K, A
LD A, B
X A, TMP1
X A, B
LDS A, W(B-)
NOP
LOS A, W(B+)
NOP
SET C
SUBC A, K
LD X, A
LD A, W(B)
IFN C
DEC A
44
; SAVE QUOTIENT IN K.
; A POINTS TO F2-HI.
; A POINTS TO F1-HI, TMP1 POINTS TO F2-HI.
B POINTS TO F1-HI.
B POINTS TO F1-LO.
LOAD F1-LO.
B POINTS TO F1-HI.
;
;
;
;
SUBTRACT QUOTIENT SAVED IN K.
AND SAVE IN X.
LOAD F1-HI.
IF C WAS NOT SET IN THE LAST SUBTRACT,
ADJUST THE BORROW.
X A, X
LD B, TMP1
B POINTS TO F2-HI.
F8BA EF
.BYTE OEF
DIVD A, W(B) - KLUDGED AGAIN
QUOTIENT IN A, REM IN X.
F8BB ABOO
F8BD 00
ST A, TMP1
CLR A
SAVE QUOTIENT IN TMP1.
ZERO A.
F8BE EF
.BYTE OEF
; DIVD A, W(B) - KLUDGED YET AGAIN
F8BF AEOO
X A, TMP1
; SWAP OLD AND NEW QUOTIENTS.
F8C1 E7
F8C2 07
F8C3 56
F8C4
F8C6
F8C7
F8C9
F8CA
F8CD
F8CF
F8DO
F8D1
F8D2
F8D5
F8D6
F8D7
F8D9
AEOO
E7
AEOO
07
96C808
ABCA
E1
40
E4
B8FFOO
E3
40
A8CA
E7
F8DA D7
F8DB E3
F8DC 40
CHECK FOR NORMALIZATION. CAN BE OFF BY AT MOST 1 BIT.
SHL A
IF C
JP $NMED
IT IS NORMALIZED.
GET HERE MEANS NEED TO SHIFT LEFT ONCE.
X A, TMP1
SWAP HI AND LO WORDS.
SHL A
HI WORD IS IN A, LO WORD IN TMP1.
X A, TMP1
IF C
; WAS 1 SHIFTED OUT OF LO WORD?
SET A.O
; YES, THEN SET LSB OF HI WORD.
ST A, K
SAVE HI WORD IN K.
XS A, W(B+)
NOP
B POINTS TO F2-EXP.F2-SIGN.
LD A, W(B)
LOAD F2-EXP.F2-SIGN.
ADD A, OFFOO
SUBTRACT 1 FROM EXPONENT.
XS A, W(B-)
STORE BACK IN F2-EXP.F2-SIGN.
NOP
B POINTS TO F2-HI.
LD A, K
; HI WORD TO A.
SHL A
$NMED:
RRC A
RESTORE BIT OUT.
SAVE HI-WORD IN F2-HI.
XS A. W(B-)
B POINTS TO F2-LO.
NOP
5·82
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL S6
FDIV
FDIV.MAC
203
204
205
206
207
20S
209
210
211
212
213
214
215
216
217
21S
219
220
221
222
223
224
225
226
227
22S
229
230
231
232
FSDD
FSDF
FSEO
FSE1
ASOO
E1
40
ACCCCE
LD A, TMPl
XS A, W(B+)
NOP
LD X, B
FSE4 B5F7B7
FSE7
FSES
FSE9
FSEB
FSEE
FSFO
FSF3
FSF4
FSF5
FSFS
FSFA
FSFC
FSFE
DO
D2
9COO
B4F730
9DFE
B4F73C
F2
F2
B5F7S4
3FC4
3FCC
3FCE
3C
FSFF
F900
F903
F905
F907
00
ACCSCA
3FCC
3FCE
3C
PAGE:
+
45
SAVE C-LO.
B POINTS TO F2-HI.
MOVE ADDRESS OF F2-HI TO X.
; ROUNDING CODE.
JSRL SROUND
FINAL CHECK OF EXPONENT.
LD A, M(X+)
; X NOW POINTS TO C-EXP.
LD A, M(X-)
IFEQ A, 0
JMPL UNDFL
IFGT A, OFE
JMPL OVRFL
LD A, W(X-)
LD A, W(X-)
; X NOW POINTS TO C-LO.
JSR FPAK
PACK C.
POP SP
; SET UP SP FOR RETURN.
POP B
POP X
RET
; C IS ZERO B'COS Fl IS ZERO.
$CZERO:
CLR A
LD K, A
POP B
POP X
RET
.END
5-83
CD
CO
"'I:t
Z
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
SINX
FSINX.MAC
50 F963 AFCA
51 F965 B6F9A4AB
52 F969 A4F9A6CAAB
53 F96E B5FBA4
54
55 F971 3FCE
56 F973 3FCE
57 F975 36BA
58
59 F977 AFC8
60 F979 AFCA
61 F97B B13F80
62 F97E 00
63 F97F B5FB93
64
65 F982 3FCE
66 F984 3FCE
67 F986 3FCE
68 F988 3FCE
69 F98A 36CF
70
71 F98C 3FCE
72 F98E 3FCE
73 F990 3FCE
74 F992 3C
75
76 F993 40
77
78 F994 2B32
79 F996 D732
80 F998 1DEF
81 F99A 3836
82 F99C OlOD
83 F99E 5039
84 F9AO 8988
85 F9A2 083C
86 F9A4 ADAA
87 F9A6 2A3E
88
89
90
91
92 F9A8 AFCE
93 F9AA ACC8CE
94 F9AD B6F9C8A8
95 F9B1 AFC8
96 F9B3 B6F9CAA8
97 F9B7 AFC8
98 F9B9 A8CE
99 F9BB B5FB77
100 F9BE 3FCE
PAGE:
47
PUSH K
LD A, W($A1LO)
LD K, W($A1HI)
JSRL FSUB
POP X
POP X
JSRL FMULT
LOAD A1.
COMPUTE
A1 - XA2 (A2 - XA2 (A3 - XA2 (A4 - A5·XA2))).
; COMPUTE
; XA2(A1 - XA2(A2 - XA2(A3 - XA2(A4 - A5·XA2)))).
PUSH A
PUSH K
LD K, 03F80
CLR A
JSRL FSUB
; LOAD 1.0 INTO K-A.
COMPUTE
; 1 - ALL THE JUNK ABOVE.
POP X
POP X
POP X
POP X
; NOW X IS AT THE TOP OF STACK.
JSRL FMULT
; COMPUTE
; X(l - XA2(A1 - XA2(A2 - XA2(A3 - XA2(A4 - A5·XA2))))).
POP X
POP X
POP X
RET
.EVEN
$A5LO:
$A5HI:
$A4LO:
$A4HI:
$A3LO:
$A3HI:
$A2LO:
$A2HI:
$A1LO:
$A1HI:
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
z
~
Q)
Q)
0322B
032D7
OEF1D
03638
00D01
03950
08889
03C08
OAAAD
03E2A
; A DIRTY APPROXIMATION TO COS(X) USING SIN(X).
COSX:
PUSH X
LD X, A
LD A, W($PI2LO)
PUSH A
LD A, W($PI2HI)
PUSH A
LD A, X
JSRL FADD
POP X
5·85
COMPUTE X + PI/2.
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
SINX
FSINX.MAC
101
102
103
104
105
106
107
lOa
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
41
42
43
F9CO
F9C2
F9C4
F9C6
3FCE
34BA
3FCE
3C
F9C7 40
F9C8 DBOF
F9CA C93F
PAGE:
POP X
JSRL SINX
POP X
RET
48
COMPUTE SIN(X+PI/2).
• EVEN
$PI2LO: .WORD OOFDB
$PI2HI: .WORD 03FC9
; A DIRTY APPROXIMATION TO TAN (X) USING SINX AND COSX.
TANX:
F9CC
F9CE
F9DO
F9D2
F9D4
F9D6
F9D9
F9DC
F9DE
F9EO
F9E2
F9E4
F9E6
F9E8
F9EA
F9EC
F9EE
F9FO
AFCE
AFCC
AFca
AFCA
342C
ACC8CE
ACCACC
3FCA
3FC8
AFCE
AFCC
34DC
3614
3FCC
3FCC
3FCC
3FCE
3C
PUSH X
PUSH B
PUSH A
PUSH K
JSR COSX
LD X, A
LD B, K
POP K
POP A
PUSH X
PUSH B
JSR SINX
JSR FDIV
POP B
POP B
POP B
POP X
RET
COMPUTE COS (X)
COMPUTE SIN(X).
COMPUTE TAN(X)
.END
FFFE OOFO
.END LISTER
5·86
= SIN(X)/COS(X).
.
l>
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 8S
SINX
SYMBOL TABLE
A
COSX
FMULT
FPERWD
FUNPAK
LISTER
SINX
TMPl
$AlHI
$A3HI
$A5HI
$ADDEX
$ANORM
$CSIGN
$DIVlO
$DTLO
$EXACC
$EXCOL
$EXIT
$TEXSN
$GOON
$INDUN
$ISNED
$JAMIT
$LOOPl
$MLOG2
$MTLO
$NAN
$NMED
$NRLUP
$OVRl
$RNDUP
$VDOWN
$ZROFl
OOC8 W
F9A8
FSBB
0002 W
FOSl
FOOO
F908
0000 W
F9AS
F99E
F99S
FlFF
FS4A
F349
F370
F2SE
FlC9
FlBA
FOCS
F84A
F42B
F445
F3BE
F280
Fl47
F33F
F26A
F4CF
F8DA
F237
F3Cl
FOA7
F4l8
F607
ATOF
DIVBYO
FNACHK
FPTRAP
FZCHK
MULlO
SP
UNDFL
$AlLO
$A3LO
$A5LO
$ADDMN
$ANOTa
$CZERO
$DOLUP
$DTLO
$EXCH2
$EXCPT
$FlCHK
$FRCOL
$HIUP
$INTFY
$ISNXT
$JAMIT
$LOOPl
$MSIGN
$MTLO
$NANLP
$NORMl
$NTZER
$PI2HI
$ROUND
$VUP
$ZROF2
Fl3A •
FOOO
F040
F09D
F05l
Fll8
00C4 W
FOlE
F9A4
F99C
F994
FSl2
F05C
F7C9
F48l
F390
F738
F2CF
F56E
Fl8B
FOAF
F43C
Fl7D
F3AS
F5FB
Fl54
F394
F4DC
F230
F585
F9CA
F6AO
F4l6
F5E2
PAGE:
Z
49
~
Q)
en
B
FADD
FNAN
FSUB
ISIOK
OVRFL
SROUND
X
$A2HI
$A4HI
$ACCF
$ADEM
$CHKOT
$CZERO
$DTHI
$ESAVE
$EXCHR
$EXIN2
$FlSIN
$FSIGN
$INCOL
$ISNAN
$JAMDN
$JAMLP
$LOOP2
$MTHI
$MULlO
$NEGlO
$NORM2
$OVl
$PI2LO
$ROUND
$ZERLP
OOCC W
F535
FOOF
F5l5
Fl05
F02F
F09E
OOCE W
F9A2
F99A
FlA9
F3EC
Fll3
F8FF
F270
F20F
FlBB
FOB7
F643
F878
Fl5C
F04C
F29E
F287
F5D7
F26C
F398
F20B
F235
F666
F9C8
F7AE
F505
BFMUL
FDIV
FPAK
FTOA
K
PC
TANX
$AlOEX
$A2LO
$A4LO
$ACCM
$ADJEX
$CHNGS
$DIVlO
$DTHI
$ESIGN
$EXCLP
$EXINC
$F2GTR
$GOBAK
$INCRV
$ISNED
$JAMDN
$JAMLP
$ML4
$MTHI
$NAGAS
$NLOOP
$NRDUN
$OVRl
$REMV9
$TRADD
$ZERO
FOC7
F7D2
F07C
F3ll
OOCA
OOCS
F9CC
FlF4
F9AO
F998
Fl77
FS85
F3Sl
F272
F392
FlC7
FlD4
F79D
F5EB
F4lF
F40C
F298
F3C4
F3AD
F3EA
F396
F2C3
F653
F247
F29B
F354
F66C
F4E9
•
W
W
•
III
I
5·87
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
SINX
MACRO TABLE
PAGE:
NO WARNING LINES
NO ERROR LINES
2547 ROM BYTES USED
SOURCE CHECKSUM
OBJECT CHECKSUM
=A31F
=2AC3
INPUT FILE C:LISTER.MAC
LISTING FILE C:LISTER.PRN
OBJECT FILE C:LISTER.LM
5·88
50
A Radix 2 FFT Program
for the HPC
National Semiconductor
Application Note 487
Ashok Krishnamurthy
INTRODUCTION
2. The basic computation unit is the so-called Butterfly,
shown in Figure 2. Each stage involves the computation
of N/2 butterflies.
3. The results from the computation in one stage are fed to
the next stage after multiplication by some power of W.
These powers of Ware the so-called Twiddle Factors.
Note that each power of W is really a complex number
that can be represented by its real and imaginary parts.
The real part of Wk is COS(27TklN) and the imaginary part
is -sin(27Tk/N).
This report describes the implementation of a radix-2, Decimation-in-time FFT algorithm on the HPC. The program, as
presently set up can do FFTs of length 2, 4, 8, 16, 32, 64,
128 and 256. The program can be easily modified to work
with higher FFT lengths by increasing the Twiddle Factor
table.
FFT FUNDAMENTALS
If x(n), n = 0, 1, ... , N -1 are N samples of a time domain
signal, its Discrete Fourier Transform (DFT) is defined as
n = N-1
X(k) =
L
x(n) wnk, k = 0, 1, ... , N - 1
n = 0
where W = e-j21T/N
The straight evaluation of the above equation requires on
the order of N2 complex multiplies. The FFT is nothing but a
fast algorithm to compute the DFT that uses only on the
order of N 10g(N) complex multiplies. Many different FFT
algorithms exist (please see references 1, 2 and 3). The
algorithm implemented for the HPC is the most common
type of FFT - a radix-2, Decimation-in-time algorithm. This
class of algorithms requires that the number of input samples, N, be a power of 2. This is usually not a problem, since
the input data can be zero padded to achieve this. The development of this algorithm is described in references 1 and
2; the discussion here is brief and based on reference 1.
Separating the DFT summation above into the even-numbered points and odd-numbered points of x(n), we can rewrite the above sum as:
X(k) =
L
x(n) wnk +
L
N/2 - 1
L
L
6. The outputs from each stage can be stored back again in
the same storage area as the input sequence. This gives
the algorithm the in-place property. Thus the final DFT
results overwrite the initial data.
THE INVERSE FFT
If X(k) k = 0, 1, ... , N -1 is the DFT of a sequence, then its
inverse DFT, x(n), is defined as follows:
x(n) wnk
=
(ij)
k
= N-1
L
X(k) W-nk
n
= 0,1, .. , N-1.
k=Q
N/2 - 1
x(2r) w2rk + Wk
5. The input data sequence needs to be suitably scrambled
if the output sequence is to be in the proper order. This
scrambling is easily accomplished by using the so-called
Bit-Reverse counter as outlined in reference 2.
x(n)
n odd
n even
Using n = 2r for n even and n = 2r + 1 for n odd, we can
further rewrite the above as:
X(k) =
4. The number of distinct Twiddle Factors used in the first
stage is 1, in the second stage is 2 etc., until the Lth stage
that involves 2L - 1 = N/2 twiddle factors. Each twiddle
factor in the first stage is involved in N/2 Butterflies, in
the second stage with N/4 butterflies etc., until in the Lth
stage each twiddle factor is involved with N/(2L) = 1 butterfly.
x(2r + 1) W2rk
r = 0
r = 0
If G(k) is the N/2 point DFT of x(2r) and H(k) is the N/2
point DFT of x(2r+ 1), the above equation can be written as:
X(k) = G(k) + W k H(k)
This equation shows that a N point DFT can be written as
the sum of two N/2 point DFTs. The N/2 point DFTs can be
computed as the sum two N/4 point DFTs and so on until
we are left with two point DFTs. The two point DFTs can be
trivially evaluated by direct computation.
Figure 1, taken from reference 1, shows the decomposition
for the case N = 8. With reference to this figure, we can
note the following points.
1. If N is the number of points in the original sequence,
where N = 2 L, then there are L stages in the DFT decomposition.
Thus the Inverse FFT is the same as the forward FFT except for the following: 1. Negative powers of Ware used
instead of positive powers; and 2. The final sequence is
scaled by 1IN. The basic FFT program can therefore be
used to compute the inverse FFT with these two changes.
This is the approach used in the HPC implementation.
TWIDDLE FACTOR TABLE
The brief description of the FFT in the previous section
shows that the algorithm needs to use the Twiddle Factors
Wk in the computation. The twiddle factors can either be
computed as required, they can be computed using a recursive relation, or they can be obtained by looking up in a
table (Ref. 2). The approach used in the HPC implementation is to construct a table containing the needed twiddle
factors. This table is stored in ROM and values needed are
looked up from this table. The length of the table needed is
determined by the maximum FFT length that you want to
use. The HPC FFT implementation is presently limited to a
maximum length of 256. This requires that the twiddle factors WO,
W1,
W255 be available, where
5-89
LII
I
.....
co
.
oqo
z
ct
W = e-j2'IT1256. Since ejx = cos(x) + jsin(x), the values
stored in this table are cos(O), sin(O), cos(27T/256), sin(27T1
256) etc., up to COS(27T X 255/256), sin (27T X 255/256).
The table used in the implementation is organized as follows:
.WORD cos(O) X 214
.WORD sin(O) X 214
of 4 different subroutines: FFT, IFFT, BRNCNTR and
SMULT. FFT does the forward FFT calculation, IFFT the
Inverse FFT calculation, BRNCNTR implements the bit reversed counter, and SMULT does signed multiplication.
Two global symbols need to be defined by the user to use
the FFT routines. The first, called TWSTAD should be set to
the address of the start of the twiddle factor table. The second, called DTSTAD, should be set to the address of the
start of the data area to be transformed. For details on the
organization of these storage areas, see the preceding sections.
The actual number of data points to be transformed needs
to be passed to the FFT routines. This is done as follows.
Two symbols that refer to words of on-chip RAM have been
defined. The first is NUMB = W(01CO) and the second is
L 1 = W(01 C2). Before calling the FFT routine, the user
should load NUMB with N, the number of data points to be
transformed, and L1 with L, N = 2L.
.WORD cos(27T/256) X 214
.WORD sin(27T/256) X 214
.WORD COS(27T255/256) X 214
.WORD sin(27T255/256) X 214
This table is available in the file TWDTBL.MAC and occupies 1024 bytes of storage.
DATA STORAGE
To do a forward FFT, call FFT; to do an inverse FFT, call
IFFT. In both cases, the output of the transform overwrites
the input data.
The data to be transformed, x(O), ... , x(N -1) are also regarded as complex numbers with a real and an imaginary
part. Let xr(i) be the real part of x(i) and xi (i) the imaginary
part of x(i). Then the data needs to be stored as follows:
.WORDxr(O)
INCREASING THE MAXIMUM TRANSFORM LENGTH
The maximum transform length for the FFT program is primarily limited by the size of the Twiddle Factor table. To
increase the transform length, the following needs to be
done .
.WORDxi(O)
.WORDxr(1)
1. Increase the Twiddle Factor table. Thus, if the maximum
transform length required is 1024, the table needs to
store the cosine and sine of the angles
.WORDxi(1)
0, 27T/1024, 27T X 2/1024, ... , 27T X 1023/1024
2. Change the global symbol LMAX such that the maximum
transform length is 2LMAX.
.wORD xr(N -1)
.WORD xi(N-1)
The length of this storage area obviously depends on the
number of data points to be transformed. Note that the FFT
program itself does not use any base page user RAM. Also,
only 8 words of stack are needed. Thus the base page user
RAM can be used to store the data to be transformed. Since
192 bytes are available in this area, transforms of up to 32
pOint in length can be in the single chip mode with no external RAM.
FFTIIFFT TEST PROGRAM
The data in the file TSTDAT.MAC can be used to test the
FFT program. The data and its transform value is from reference 3. The program in reference 3 is for a Floating point
FORTRAN FFT program. Since the HPC FFT program is a
fixed point one, the input data needs to be suitably scaled.
The scale factor chosen is 210. The file TSTDAT.MAC contains the scaled input data, and the expected transform. The
input data is stored in memory words 200/27E and the expected transform is stored in memory words 280/2FE. To
run the test program, do the following.
Set up the MOLE Development System with Blocks 0, 13,
14 and 15 mapped ON. Download the program to the
MOLE. Set up a Breakpoint at F410. Run the program start·
ing at F400. When the program is breakpointed, list memory
words 200/27F and compare them with memory words
280/2FE.
Note that any difference between the expected OFT values
and the OFT values actually computed is due to the fixed
point computations in the FFT program.
USING THE FFT PROGRAM
The FFT program along with test data to test the program is
provided in the files FFT.MAC, TSTDAT.MAC and
TWDTB L. MAC. TSTDAT.MAC contains the test data, and
the output from the FFT routines. TWDTBL.MAC contains
the Twiddle Factors. The FFT computation involves the use
5-90
x (0) o-.....--O:~-+---::-:D--+--c~--.-o--t-o----.o X(0)
WO
X
(4)
N
x(2) o-....-a_....-~-t-o--...~o-....-o~...-I-.a X(2)
WO
-o---.....o-+--o--l---I--+.a
N
x (6) o-.......-o~~-=o......
X(3)
x(l)
WO
N
x(5) o-.....-o~-+--o-......-Q---:...~o-.....-o-+-+-+~ X(5)
x(3)
WO
N
x (7) o-....-c~....--o-t-o---~o-....- o - - - . a X(7)
-I
TUDD/9259-1
FIGURE 1. FFT Flow Graph for N = 8 Points
REFERENCES
1. A.V. Oppenheim and R.W. Schafer. Digital Signal Processing. Prentice-Hall. New Jersey. 1975.
2. L.R. Rabiner and B. Gold. Theory and Applications of Digital Signal Processing. Prentice-Hall. New Jersey. 1975.
3. IEEE ASSP Society Digital Signal Processing Committee.
Programs for Digital Signal Processing. IEEE Press. New
York. 1979.
xm(p)~ .... ,(p)
Xm(q)~ Xm+I(q)
TL/DD/9259-2
FIGURE 2. The Butterfly-The Basic
Computation Unit In the FFT
The code listed in this App Note is available on Dial-A-Helper.
Dial-A-Helper is a service provided by the Microcontroller Applications Group. The Dial-A-Helper system provides access to
an automated information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours
a day. The system capabilities include a MESSAGE SECTION (electronic mail) for communicating to and from the Microcontroller Applications Group and a FILE SECTION mode that can be used to search out and retrieve application data about
NSC Microcontrollers. The minimum system requirement is a dumb terminal. 300 or 1200 baud modem. and a telephone.
With a communications package and a PC. the code detailed in this App Note can be down loaded from the FILE SECTION
to disk for later use. The Dial-A-Helper telephone lines are:
Modem (408) 739-1162
Voice (408) 721-5582
For Additional Information, Please Contact Factory
5-91
III
.
~ r-----------------------------------------------------------------------------------~
co
APPENDIX A
Z
c(
Listing of FFT Program Code
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
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; THIS PROGRAM IMPLEMENTS A RADIX-2, DECIMATION IN TIME FFT ALGORITHM.
0008
LMAX = 08
; MAXIMUM FFT LENGTH IS 2·LMAX.
FOOO
TWSTAD = OFOOO
0200
DTSTAD = 0200
;
;
;
;
TWIDDLE FACTOR TABLE START
ADDRESS.
DATA STORAGE AREA START
ADDRESS.
OlCO
NUMB = W(OlCO)
01C2
01C4
Ll = W(01C2)
LSHIFT = W(01C4)
01C6
NBFLY = W(01C6)
;
;
;
;
;
;
;
;
;
01C8
ISTEP = W(01C8)
;
;
;
;
;
;
;
;
;
;
;
;
;
NUMBER OF DATA POINTS TO BE
TRANSFORMED.
NUMB IS 2·Ll.
LSHIFT = LMAX - Ll. IT IS A SHIFT
FACTOR NEEDED TO COMPUTE THE
ADDRESS REQUIRED FOR TWIDDLE
FACTOR LOCKUP.
NUMBER OF BUTTERFLIES PER
TWIDDLE FACTOR PER STAGE.
IF X(l) AND X(J) ARE INVOLVED
IN A BUTTERFLY, THEN J=I+ISTEP.
IT IS ALSO THE NUMBER OF TWIDDLE
FACTORS IN A STAGE.
IF XII) IS THE FIRST DATA VALUE
FOR THE FIRST BUTTERFLY FOR A
GIVEN TWIDDLE FACTOR, THEN THE
SUBSEQUENT BUTTERFLIES FOR THAT
TWIDDLE FACTOR HAVE AS THE FIRST
DATA VALUE X(I+N*ILEAP).
TWIDDLE FACTOR EXPONENT STEP.
THE TWIDDLE FACTORS FOR A GIVEN
STAGE ARE W·(I*WESTEP).
FFT STAGE BEING EVALUATED.
INDEX OF THE FIRST DATA VALUE
FOR THE FIRST BUTTERFLY FOR A
GIVEN TWIDDLE FACTOR.
EXPONENT VALUE FOR A GIVEN
TWIDDLE FACTOR.
TWIDDLE FACTOR BEING EVALUATED.
OlCA
lLEAP = W(OlCA)
OlCC
WESTEP = W(OlCC)
OlCE
NSTG = W(OlCE)
OlDO
ISTART = W(OlDO)
01D2
WEXP = W(01D2)
01D4
NTWD = W(01D4)
;
;
;
;
;
;
01D6
COSTH = W(01D6)
; COSINE PART OF TWIDDLE FACTOR.
01D8
SINTH = W(01D8)
SINE PART OF TWIDDLE FACTOR.
OlDA
Ml = W(OlDA)
OlDC
NBCNT = W(OlDC)
INDEX OF FIRST DATA VALUE FOR
; A BUTTERFLY.
; BUTTERFLY BEING EVALUATED.
OlDE
R1ADDR = W(OlDE)
; ADDRESS OF REAL PART OF FIRST
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=W(OlEO)
OlEO
R2ADDR
01E2
XRl
01E4
Xll= W(01E4)
01E6
XR2
01E8
XI2 = W(01E8)
OlEA
TEMPR
= W(OlEA)
OlEC
TEMPI
=W(OlEC)
OlEE
MTEMP = W(OlEE)
= W(01E2)
= W(01E6)
;
;
;
;
DATA VALUE INVOLVED IN A BUTTERFLY.
ADDRESS OF REAL PART OF SECOND
DATA VALUE INVOLVED IN A BUTTERFLY.
REAL PART OF FIRST DATA VALUE
INVOLVED IN A BUTTERFLY.
; IMAGINARY PART OF ABOVE.
; REAL PART OF SECOND DATA VALUE
INVOLVED IN A BUTrERFLY.
IMAGINARY PART 01 ABOVE.
TEMPORARY STORAGE USED IN
; A BUTTERFLY.
SAME AS ABOVE.
TEMPORARY STORAGE USED IN SMULT.
.INCLD TSTDAT .MAC
.INCLD TWDTBL. MAC
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j'400
• = OF400
TSTFFT:
F400
F404
F409
F40E
F410
F411
F413
F414
B701FOC4
832001COAB
830501C2AB
3049
40
31C4
40
61
LD SP, OlFO
LD NUMB, 020
LD Ll, 05
JSR FFT
NOP
JSR IFFT
NOP
JP .-1
32 POINT FFT.
32 = 2'5.
COMPUTE FFT.
THIS SUBROUTINE IMPLEMENTS A BIT REVERSED COUNTER AS NEEDED FOR
; DATA SHUFFLING IN THE FFT ROUTINE. THE ALGORITHM IS BASED ON
; THE DESCRIPTION IN:
RABINER AND GOLD,
THEORY AND APPLICATIONS OF DIGITAL SIGNAL PROCESSING,
PRENTICE-HALL, 1975.
; ON INPUT, X CONTAINS THE PREVIOUS BIT REVERSED COUNTER VALUE.
; THE NEXT BIT REVERSED OUTPUT IS RETURNED IN X.
; A IS LOST, BAND K ARE PRESERVED.
.LOCAL
BRCNTR:
F415 B601COA8
LD A, NUMB
F419 C7
$REPEAT:
F41A 96CEFD
SHR A
; GET NUMBER OF DATA SAMPLES
; TO BE TRANSFORMED.
; DIVIDE BY 2.
IFGT A, X
; IS BIT BEING TESTED A 0
5-93
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....
CD
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F41D 47
JP $FOUND
F41E
F41F
F423
F424
SET C
SUBC X, A
SHR A
JP $REPEAT
02
AOC8CEE8
C7
6A
YES, SO STOP CHECKING.
GET HERE MEANS BIT BEING
CHECKED IS 1.
ZERO OUT THE BIT.
; UPDATE BIT LOCATOR.
$FOUND:
F425 AOC8CEF8
F429 3C
ADD X, A
RET
• LOCAL
THIS SUBROUTINE MULTIPLIES TWO 18-BIT 2' S COMPLEMENT INTEGERS AND RETURNS
; THE UPPER HALF OF THE RESULT. THE MULTIPLICAND IS IN A, AND THE MULTIPLIER
; IN W(B). THE RESULT IS RETURNED IN A. ONE TEMPORARY WORD OF STORAGE,
; ADDRESSED AS MTEMP IS USED.
SMULT:
F42A 830001EEAB
F42F A9CC
LD MTEMP, 0
INC B
F431
F432
F438
F438
F439
F430
F441
F442
F448
F447
F449
F44A
F44E
F44F
F452
F453
F454
F457
F458
IF M(B).7
ST A, MTEMP
DECSZ B
NOP
X A, MTEMP
IF M(($MTEMP)+1).7
ADD A, W(B)
X A, MTEMP
MULT A, W(B)
17
B601EEAB
AACC
40
B801EEAE
B601EF17
F8
B801EEAE
FE
AECE
02
B801EEEB
E7
98CF17
04
E7
98CFl8
04
3C
X A, X
;
;
;
;
;
;
CLEAR TEMPORARY STORAGE.
B NOW POINTS TO UPPER BYTE
OF MULTIPLIER.
IS IT NEGATIVE ?
THEN SAVE MULTIPLICAND IN MTEMP.
B INTO WORD POINTER.
SWAP A AND MTEMP.
IS MULTIPLICAND NEGATIVE
THEN ACCUMULATE MULTIPLIER.
; UNSIGNED MULTIPLY.
; UPPER HALF IN A.
SET C
SUBC A, MTEMP
SHL A
IF H(X).7
INC A
SHL A
IF H(X).8
INC A
RET
; THIS SUBROUTINE IMPLEMENTS THE FIXED POINT RADIX-2 DECIMATION-IN-TIME
; FFT ALGORITHM. THE DATA IS INITIALLY PUT IN THE BIT REVERSED ORDER, AND
THEN THE FFT IS COMPUTED. FOR THE THEORY BEHIND THE ALGORITHM, CONSULT:
1. OPPENHEIM AND SCHAFER, DIGITAL SIGNAL PROCESSING,
PRENTICE-HALL.
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2. RABINER AND GOLD, THEORY AND APPLICATIONS OF DIGITAL SIGNAL
PROCESSING, PRENTICE-HALL, 1975.
; THE ALGORITHM USED CLOSELY FOLLOWS THE FORTRAN PROGRAM FOREA IN
3. PROGRAMS FOR DIGITAL SIGNAL PROCESSING, IEEE.
FFT:
FIRST PUT THE DATA IN BIT REVERSED ORDER.
F459
F45A
F45C
F45E
00
ABCC
ABCE
A401COCAAB
CLR A
ST A, B
ST A, X
LD K, NUMB
; SET UP NORMAL COUNTER.
; SET UP BIT REVERSED COUNTER.
; K HAS NUMBER OF DATA POINTS.
IFGT X, B
JP SWAP
JMP COUNT
; IS BIT REV CNTR ~ NORM CNTR
; YES, SO SWAP DATA.
; NO SO INCREMENT COUNT.
REVLP:
F463 AOCCCEFD
F467 42
F468 9421
SWAP:
F46A
F46C
F46E
F470
F471
F472
F475
F477
F479
F47A
F47B
F47E
F480
F481
F482
F483
F484
F485
F486
F487
F489
AFCC
AFCE
A8CC
E7
E7
B80200
ABCC
A8CE
E7
E7
B80200
ABCE
E4
Fl
El
40
E4
F5
E6
3FCE
3FCC
PUSH B
PUSH X
LD A, B
SHL A
SHL A
ADD A, DTSTAD
ST A, B
LD A, X
SHL A
SHL A
ADD A, DISTAD
ST A, X
LD A, WeB)
X A, W(X+)
XS A, W(B+)
NOP
LD A, WeB)
X A, W(X)
ST A, WeB)
POP X
POP B
INDEX VALUE I IS IN A.
; GET ADDR. OF XR(I).
SAVE IT IN B.
; INDEX VALUE J IS IN A.
;
;
;
;
;
--
GET ADDR. OF XR(J).
SAVE IT IN X.
XR(I).
A
XR(J), XR(J)
A
XR(I), XR(I)
A
; A XI(I).
; A XI(J), XI(J)
; XI(I) XI(J).
--
XR(I).
XR(J).
-
XI(I).
COUNT:
DECSZ K
JP UPIT
JP DOFFT
F48B AACA
F48D 41
F48E 46
; DONE?
; NO GO DO SOME MORE.
UPIT:
F48F 347A
COUNT UP ON BIT REV CNTR.
JSR BRCNTR
5·95
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F491 A9CC
F493 9530
PAGE:
5
COUNT UP ON NORMAL CNTR.
INC B
JMP REVLP
DOFFT:
; DATA IS NOW STORED IN THE BIT REVERSED ORDER. COMPUTE .THE FFT.
F495
F497
F498
F499
F49A
F49E
F4A2
F4A6
F4A7
F4AB
F4AF
F4B4
LD A. LMAX
INC A
INC A
SET C
SUBC A. L1
ST A. LSHIFT
LD A. NUMB
SHR A
ST A. NBFLY
ST A. WESTEP
LD ISTEP. 01
LD ILEAP. 02
9008
04
04
02
B601C2EB
B601C4AB
B601COA8
C7
B601C6AB
B601CCAB
830101C8AB
830201CAAB
; A HAS MAX FFT EXPONENT.
; COMPUTE LSHIFT.
INITIALIZE
INITIALIZE
INITIALIZE
INITIALIZE
NBFLY.
WESTEP.
ISTEP.
ILEAP.
; SET UP L1 STAGES OF BUTTERFLIES.
F4B9 B601C2AB
F4BD B601CEAB
LD A. L1
ST A. NSTG
; LOOP L1 TIMES.
LOOP1:
F4C1 00
F4C2 B601DOAB
F4C6 B601D2AB
CLR A
ST A. ISTART
ST A. WEXP
INITIALIZE ISTART FOR EACH STAGE.
INITIALIZE WEXP.
SET UP ISTEP LOOPS OF TWIDDLE FACTORS.
F4CA B601C8A8
F4CE B601D4AB
LD A. ISTEP
ST A. NTWD
; LOOP ISTEP TIMES.
LOOP2:
; LOOK UP THE TWIDDLE FACTOR.
F4D2 A401C4CAAB
F4D7 B601D2A8
LD K. LSHIFT
LD A. WEXP
SHIFT LEFT LSHIFT TIMES.
GADLP:
F4DB
F4DC
F4DE
F4DF
E7
AACA
63
B8FOOO
SHL A
DECSZ K
JP GADLP
ADD A. TWSTAD
F4E2
F4E4
F4E5
F4E9
F4EA
F4EB
ABCE
FO
B601D6AB
F4
01
04
ST A. X
LD A. W(X+)
ST A. COSTH
LD A. W(X)
COMP A
INC A
;
;
;
;
;
;
DONE SHIFTING ?
NO SO DO MORE.
ADD STARTING ADDR OF TWIDDLE
FACTOR TABLE.
TWIDDLE FACTOR ADDR IN X.
GET COS (THETA) •
; GET SIN (THETA) •
; MAKE IT NEGATIVE.
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PAGE:
F4EC B601D8AB
ST A, SINTH
F4FO A501DOOIDAAB
LD Ml, ISTART
6
; INITIALIZE MI.
SET UP NBFLY BUTTERFLIES FOR THIS TWIDDLE FACTOR.
F4F6 A501C601DCAB
LD NBCNT, NBFLY
LOOP NBFLY TIMES.
GET INDEX OF X(I).
LOOP3:
F4FC
F500
F501
F502
F505
F509
F50B
F50C
F510
F511
F515
F519
F51D
F51E
F51F
F522
F526
F528
F529
F520
F52E
B601DAAB
E7
E7
B80200
B601DEAB
ABCE
FO
B601E2AB
F4
B601E4AB
B601DAA8
B601C8F8
E7
E7
B80200
B601EOAB
ABCE
FO
B601E6AB
F4
B601E8AB
LD A, 1.11
SHL A
SHL A
ADD A, DTSTAD
ST A, RIADDR
ST A, X
LD A, W(X+)
ST A, XRl
LD A, W(X)
ST A, XII
LD A, 1.11
ADD A, ISTEP
SHL A
SHL A
ADD A, DISTAD
ST A, R2ADDR
ST A, X
LD A, W(X+)
ST A, XR2
LD A, W(X)
ST A, XI2
F532
F535
F539
F53B
F53F
F543
F545
F549
F54C
F550
F552
F553
F554
B201E6
B601D6A8
350F
B601EAAB
B601D8A8
3519
B601ECAB
B201E8
B601D8A8
3526
01
04
B601EAF8
LD B, #XR2
LD A, eOSTH
JSR SMULT
ST A, TEMPR
LD A, SINTH
JSR SMULT
ST A, TEMPI
LD B, #XI2
LD A, SINTH
JSR SMULT
COMP A
INC A
ADD A, TEMPR
F558
F55C
F560
F562
B601EAAB
B601D6A8
3536
B601ECF8
ST A, TEMPR
LD A, eOSIN
JSR SMULT
ADD A, TEMPI
F566 B601ECAB
; ADDR. OD XR(I).
; A ; STORE
; A STORE
XR(I).
IN XRl.
XI(I).
IN XII.
GET INDEX OF X(J).
; ADDR. OF XR(J).
; A ; STORE
; A STORE
;
;
;
;
;
;
;
;
XR(J).
IN XR2.
XI(J).
IN XI2.
B ADDR(XR2).
A COS (THETA) •
COMPUTE XR(J) *COS(THETA).
SAVE IN TEMPR.
A SIN(THETA).
COMPUTE XR(J) *SIN(THETA).
SAVE IN TEMPI.
ADDR(XI2).
B A SIN(THETA).
COMPUTE XI(J)*SIN(THETA).
; COMPUTE XR(J) *COS(THETA); XI (J) *SIN(THETA).
;
;
;
;
A COS (THETA) •
COMPUTE XI (J) *COS(THETA).
COMPUTE XR(J)*SIN(THETA)+
XI (J) *COS (THETA) •
•
ST A, TEMPI
5-97
.,.co .------------------------------------------------------------------------------------,
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308
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314
315
318
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318
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328
327
328
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F58A
F58F
F574
F575
F578
F57A
F57B
F57C
F57D
F57E
F582
F583
F584
F588
F589
F58A
F58E
A401DECEAB
A401EOCCAB
FO
02
B801EAEB
E1
40
F2
02
B801ECEB
E8
F4
B801EAF8
x -
LD X. R1ADDR
LD B. R2ADDR
LD A. W(X+)
SET C
SUBC A. TEMPR
XS A. W(B+)
NOP
LD A. W(X-)
SET C
SUBC A., TEMPI
ST A. W(B)
LD A. W(X)
ADD A. TEMPR
X A. W(X+)
LD A. W(X)
ADD A. TEMPI
ST A. W(X)
Fl
F4
B601ECF8
F8
B A ; A -
; A
ADDR(XR(I».
ADDR(XR(J'».
XR(I).
XR(I) - TEMPR.
--
XI(I) •
; A -XI(J') - TEMPI.
; A
; A
; A
; A
--
XR(I) •
XR(I) + TEMPR.
XI(I) •
XI (I) + TEMPI.
F58F A501CA01DAF8
ADD M1. ILEAP
; UPDATE N1 FOR NEXT LOOP.
F595 B601DCAA
DECSZ NBCNT
F599 959D
J'MP LOOP3
; DONE WITH ALL BUTTERFLIES
; FOR THIS TWIDDLE FACTOR ?
; NO. SO GO DO SOME MORE.
F59B B601DOA9
INC ISTART
F59F A501CC01D2F8
ADD WEXP. WE STEP
F5A5 B601D4AA
DECSZ NTWD
F5A9 95D7
J'MP LOOP2
F5AB
F5AF
F5BO
F5B4
F5B8
F5B9
F58D
F5C1
F5C2
F5C6
F5CA
F5CB
LD A.
SHL A
ST A.
LD A.
SHL A
ST A.
LD A.
SHR A
ST A.
LD A.
SHR A
ST A.
B601CAA8
E7
B601CAAB
B601C8A8
E7
B801C8AB
B601C8A8
C7
B601C8AB
B601CCA8
C7
B601CCAB
F5CF B601CEAA
F5D3 B4FEEB
+
;
;
;
;
SET UP STARTING INDEX FOR
NEXT TWIDDLE FACTOR.
UPDATE TWIDDLE FACTOR
EXPONENT VALUE.
; DONE WITH ALL TWIDDLES
; FOR THIS STAGE ?
; NO. SO GO DO SOME MORE.
ILEAP
ILEAP
ISTEP
; UPDATE ILEAP FOR NEXT STAGE.
ISTEP
NBFLY
; UPDATE ISTEP FOR NEXT STAGE.
NBFLY
WE STEP
; UPDATE NBFLY FOR NEXT STAGE.
WE STEP
; UPDATE WESTEP FOR NEXT STAGE.
DECSZ NSTG
J'MP LOOP1
; DONE WITH ALL STAGES ?
; NO SO GO DO SOME MORE.
5·98
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PAGE:
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RET
F5D6 3C
; ALL OVER.
THE CODE BELOW IS FOR THE INVERSE FFT. THE ONLY DIFFERENCE IS THAT
; THE TWIDDLE FACTORS ARE USED A LITTLE DIFFERENTLY, AND A FINAL SCALING BY
; l/NUMB IS DONE.
IFFT:
; FIRST PUT THE DATA IN BIT REVERSED ORDER.
F5D7
F5D8
F5DA
F5DC
00
ABCC
ABCE
A401COCAAB
CLR A
ST A, B
ST A, X
LD K, NUlIB
SET UP NORMAL COUNTER.
SET UP BIT REVERSED COUNTER.
K HAS NUMBER OF DATA POINTS.
IFGT X, B
JP ISWAP
JMP ICOUNT
; IS BIT REV CNTR -+ NORM CNTR
; YES, SO SWAP DATA.
; NO SO INCREMENT COUNT.
IREVLP:
F5El AOCCCEFD
F5E5 42
F5E6 9421
ISWAP:
F5E8
F5EA
F5EC
F5EE
F5EF
F5FO
F5F3
F5F5
F5F7
F5F8
F5F9
F5FC
F5FE
F5FF
F600
F601
F602
F603
F604
F605
1607
AFCC
AFCE
A8CC
E7
E7
B80200
ABCC
A8CE
E7
E7
B80200
ABCE
E4
Fl
El
40
E4
F5
E6
3FCE
3FCC
PUSH B
PUSH X
LD A, B
SHL A
SHL A
ADD A, DTSTAD
ST A, B
LD A, X
SHL A
SHL A
ADD A, DTSTAD
ST A, X
LD A, W(B)
X A, W(X+)
XS A, W(B+)
NOP
LD A, W(B)
X A, W(X)
ST A, W(B)
POP X
POP B
INDEX VALUE I IS IN A.
; GET ADDR. OF XR(I).
SAVE IT IN B.
; INDEX VALUE J IS IN A.
;
;
;
;
;
GET ADDR. OF XR(J).
SAVE IT IN X.
A +- XR(I) •
A +- XR(J) , XR(J) +- XR(I) •
A +- XR(I), XR(I) +- XR(J) •
; A +- XI(I).
;A +- XI(J), XI(J)
; XI(I) +- XI(J).
+- XI(I).
ICOUNT:
DECSZ K
JP IUPIT
JP DOIFFT
F609 AACA
160B 41
F60C 46
; DONE?
; NO GO DO SOME MORE.
IUPIT:
F60D 3518
F60F A9CC
F611 9530
COUNT UP ON BIT REV CNTR.
COUNT UP ON NORMAL CNTR.
JSR BRCNTR
INC B
JMP IREVLP
•
DOIFFT:
5·99
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; DATA IS NOW STORED IN THE BIT REVERSED ORDER. COMPUTE THE FFT.
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
F613
F615
F616
F617
F618
F61C
F620
F624
F625
F629
F62D
F632
9008
04
04
02
B601C2EB
B601C4AB
B601COA8
C7
B601C6AB
B601CCAB
830101C8AB
830201CAAB
LD A. LMAX
INC A
INC A
SET C
SUBC A. L1
ST A. LSHIFT
LD A. NUMB
SHR A
ST A. NBFLY
ST A. WESTEP
LD ISTEP. 01
LD ILEAP. 02
; A HAS MAX FFT EXPONENT.
COMPUTE LSHIFT.
INITIALIZE
INITIALIZE
INITIALIZE
INITIALIZE
NBFLY.
WE STEP •
ISTEP.
ILEAP.
SET UP L1 STAGES OF BUTTERFLIES.
F637 B601C2AB
F63B B601CEAB
LD A. L1
ST A. NSTG
; LOOP L1 TIMES.
ILOOP1:
CLR A
ST A. ISTART
ST A. WEXP
F63F 00
1640 B601DOAB
1644 B601D2AB
INITIALIZE ISTART FOR EACH STAGE.
INITIALIZE WEXP.
SET UP ISTEP LOOPS OF TWIDDLE FACTORS.
F648 B601C8A8
F64C B601D4AB
LD A. ISTEP
ST A. NTWD
; LOOP ISTEP TIMES.
ILOOP2:
; LOOK UP THE TWIDDLE FACTOR.
F650 A401C4CAAB
1655 B601D2AB
SHIFT LEFT LSHIFT TIMES.
LD K. LSHIFT
LD A. WEXP
IGADLP:
F659
F65A
F65C
F65D
E7
AACA
63
B8FOOO
SHL A
DECSZ K
JP IGADLP
ADD A. TWSTAD
F660
F662
F663
F667
F668
ABCE
FO
B601D6AB
F4
B601D8AB
ST
LD
ST
LD
ST
F66C A501D001DAAB
A. X
A. W(X+)
A. COSTH
A. W(X)
A. SINTH
;
;
;
;
;
DONE SHIFTING ?
NO DO SOME MORE.
ADD STARTING ADDR OF TWIDDLE
FACTOR TABLE.
TWIDDLE FACTOR ADDR IN X.
GET COS (THETA) •
GET SIN (THETA) •
LD M1. ISTART
; INITIALIZE Mf~
SET UP NBFLY BUTTERFLIES FOR THIS TWIDDLE FACTOR.
5-100
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46S
467
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471
472
473
474
475
47S
477
478
479
4S0
4Sl
482
483
484
4S5
486
487
488
489
490
491
492
493
494
495
49S
497
498
499
500
501
502
503
504
505
50S
507
508
509
510
F672 A501C601DCAB
PAGE:
10
LD NBCNT t NBFLY
: LOOP NBFLY TIMES.
ILOOP3:
F67S
F67C
F67D
F67E
F6Sl
FS85
FS87
F688
F68C
F68D
FS9l
F695
FS99
F69A
FS9B
FS9E
F6A2
FSA4
F6A5
F6A9
F6AA
B601DAAS
E7
E7
BS0200
B601DEAS
ABCE
FO
B601E2AB
F4
B601E4AB
B601DAA8
B601C8F8
E7
E7
BS0200
B601EOAB
ABCE
FO
BS01ESAB
F4
BS01E8AB
LD At IU
SHL A
SHL A
ADD At DTSTAD
ST At RlADDR
ST At X
LD At W(X+)
ST At XRl
LD At W(X)
ST At XIl
LD At IU
ADD At ISTEP
SHL A
SHL A
ADD At DTSTAD
ST At R2ADDR
ST At X
LD At W(X+)
ST At XR2
LD At W(X)
ST At XI2
: GET INDEX OF XII).
:
:
:
:
A +STORE
A +STORE
F6A8
FSBl
FSB5
F6B7
F6BB
F6BF
F6Cl
FSC5
FSC8
FSCC
F6CE
FSCF
F6DO
B201ES
B601DSA8
3SSB
BS01EAAB
BSOID8AS
3695
BSOIECAB
B201E8
BS01D8A8
3SA2
01
04
BS01EAF8
LD B t #XR2
LD At COSTH
JSR SMULT
ST At TEMPR
LD At SINTH
JSR SMULT
ST At TEMPI
LD B t #XI2
LD At SINTH
JSR SMULT
COMP A
INC A
ADD At TEMPR
:
:
:
:
:
:
:
:
:
:
B +- ADDR(XR2).
A +- COS (THETA) •
COMPUTE XR(J)*COS(THETA).
SAVE IN TEMPR.
A +- SIN(THETA).
COMPUTE XR(J) *SIN(THETA).
SAVE IN TEMPI.
B +- ADDR(XI2).
A +- SIN (THETA) •
COMPUTE XI (J) *SIN(THETA).
FSD4
F6D8
FSDC
F6DE
BSOIEAAB
BS01DSA8
3SB2
BSOIECF8
ST At TEMPR
LD At COSTH
JSR S)(lJLT
ADD At TEMPI
FSE2 B601ECAB
ST At TEMPI
F6ES
F6EB
FSFO
F6Fl
LD X t R1ADDR
LD B t R2ADDR
LD At W(X+)
SET C
A401DECEAB
A401EOCCAB
FO
02
: ADDR. OD XR(I).
: A +: STORE
: A +STORE
XR(I).
IN XR1.
XI(I).
IN XIl.
GET INDEX OF X(J).
: ADDR. OF XR(J).
XR(J).
IN XR2.
XI(J).
IN XI2.
: COMPUTE XR(J)*COS(THETA) : XI(J)*SIN(THETA).
:
:
:
:
A +- COS (THETA) •
COMPUTE XI(J)*COS(THETA).
COMPUTE XR(J) *SIN(THETA) +
XI(J)*COS(THETA).
X +- ADDR(XR(I)).
B +- ADDR(XR(J)).
A +- XR(I).
5-101
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PAGE:
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F6F2
F6F6
F6F7
F6F8
F6F9
F6FA
F6FE
F6FF
F700
F704
F705
F706
F70A
B601EAEB
El
40
F2
02
B601ECEB
E6
F4
B601EAF8
Fl
F4
B601ECF8
F6
-
SUBC A, TEMPR
XS A, W(B+)
NOP
LD A, W(X-)
SET C
SUBC A, TEMPI
ST A, W(B)
LD A, W(X)
ADD A, TEMPR
X A, W(X+)
LD A, W(X)
ADD A, TEMPI
ST A, W(X)
: A
F70B A501CA01DAF8
ADD Ml, lLEAP
: UPDATE Ml FOR NEXT LOOP.
F711 B601DCAA
DECSZ NBCNT
F715 959D
JMP ILOOP3
: DONE WITH ALL BUTTERFLIES
: FOR THIS TWIDDLE FACTOR ?
: NO, SO GO DO SOME MORE.
F717 B601DOA9
INC ISTART
F71B A501CC01D2F8
ADD WEXP, WESTEP
F721 B601D4AA
DECSZ NTWD
F725 95D5
JMP ILOOP2
F727
F72B
F72C
F730
F734
F735
F739
F73D
F73E
F742
F746
F747
LD A,
SHL A
ST A,
LD A,
SHL A
ST A,
LD A,
SHR A
ST A,
LD A,
SHR A
ST A,
B601CAA8
E7
B601CAAB
B601C8A8
E7
B601C8AB
B601C6A8
C7
B601C6AB
B601CCA8
C7
B601CCAB
F748 B601CEAA
F74F B4FEED
+
: A
: A
: A
: A
: A
: A
:
:
:
:
XR(I) - TEMPR.
----
XI (I).
XI(J) -TEMPI.
XR(I) •
XR(I) + TEMPR.
-
XI(I) •
XI(I) + TEMPI.
SET UP STARTING INDEX FOR
NEXT TWIDDLE FACTOR.
UPDATE TWIDDLE FACTOR
EXPONENT VALUE.
: DONE WITH ALL TWIDDLES
: FOR THIS STAGE ?
: NO, SO GO DO SOME MORE.
ILEAP
ILEAP
ISTEP
: UPDATE ILEAP FOR NEXT STAGE.
ISTEP
NBFLY
: UPDATE I STEP FOR NEXT STAGE.
NBFLY
WESTEP
: UPDATE NBFLY FOR NEXT STAGE.
WESTEP
: UPDATE WESTEP FOR NEXT STAGE.
: DONE WITH ALL STAGES ?
: NO SO GO DO SOME MORE.
DECSZ NSTG
JMP !LOOPl
DO THE FINAL SCALING OF THE DATA BY l/NUMB.
F752 B04000
LD A, 04000
: A -
5-102
1.0
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
PAGE:
12
562 F755 A401C2CAAB
563
SCALLP:
564 F75A C7
565 F75B AACA
566 F75D 63
567
568
569 F75E B601EAAB
570 F762 A501C001DCAB
571 F768 B20200
572
SCALIl':
573 F76B B601EAA8
574 F76F 3745
575 F771 El
576 F772 40
577 F773 B601EAA8
578 F777 374D
579 F779 El
580 F77A 40
581 F77B B601DCAA
582 F77F 74
583 F780 3C
584
585 FFFE 00F4
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER ,REV:C, 30 JUL 86
LD K, Ll
: K +- Ll.
SHR A
DECSZ K
JP SCALLP
: DIVIDE BY 2.
ST A, TEMPR
LD NBCNl', NUMB
LD B, DTSTAD
LD A, l'EMPR
JSR SMULl'
XS A, W(B+)
NOP
LD A, l'EMPR
JSR SMULl'
XS A, W(B+)
NOP
DECSZ NBCNl'
JP SCALIl'
RET
.END TSTFFT
PAGE:
GET HERE MEANS A IS
SAVE Il' IN TEMPR.
: LOOP COUNTER.
: B +- ADDR(XR(O».
11 (2'Ll)
•
: A +- XR(I)· (l/NUMB).
: XR(I) +- XR(I). (l/NUMB).
: A +- l/NUMB.
: A +- Xl(I). (l/NUMB).
: XI (I) +- XI (I). (l/NUMB).
: DONE l'
: NO DO SOME MORE.
: ALL OVER.
13
SYMBOL TABLE
A
COUNT
FFT
IGADLP
ILOOP3
I SWAP
00C8
F48B
F459
F659
F678
F5E8
LMAX
0008
LSHIFT 01C4
NBFLY 01C6
PC
00C6
SCALIl' F76B
SP
00C4
TSTFFT F400
WEXP
01D2
XRl
01E2
W
W
W
W
W
W
W
B
DOFFT
GADLP
ILEAP
lREVLP
IUPIl'
LOOPl
Ml
NSTG
RlADDR
SCALLP
SWAP
TWSTAD
X
XR2
OOCC
F495
F40B
OlCA
F5El
F600
F4Cl
OlDA
OlCE
OlDE
F75A
F46A
FOOO
OOCE
01E6
W
W
W
W
W
W
W
BRCNTR
DOIFFT
ICOUNT
ILOOPl
ISTARl'
F4l5
F6l3
F609
F63F
OlDO
K
OOCA
LOOP2 F4D2
MTEMP OlEE
NTWD
01D4
R2ADDR OlEO
SINTH 01D8
TEMPI OlEC
UPIl'
F48F
01E4
$FOUND F425
xn
W
W
W
W
W
W
W
W
COSTN
DTSTAD
IFFT
ILOOP2
ISTEP
Ll
LOOP3
NBCNT
NUMB
REVLP
SMULT
TEMPR
WESTEP
XI2
$REPEA
01D6
0200
F507
F650
01C8
01C2
F4FC
OlDC
OlCO
F463
F42A
OlEA
OlCC
01E8
F41A
W
W
W
W
W
W
W
W
•
5-103
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
PAGE:
14
MACRO TABLE
NO WARNING LINES
NO ERROR LINES
2307
ROM BYTES USED
SOURCE CHECKSUM
OBJECT CHECKSUM
= E9FC
= 28FC
INPUT
FILE C :FFT • MAC
LISTING FILE C:FFT.PRN
OBJECT FILE C:FFT.LM
5-104
l>
z
APPENDIX B
I
0l:Io
....
Q)
Twiddle Factor Table
TWIDDLE FACTOR TABLE FOR USE IN THE FFT ROUTINES.
TABLE SET FOR MAX FFT LENGTH OF 256.
TABLE STARTS AT FOOO AND OCCUPIES 1024 BYTES OF STORAGE.
. = OFOOO
• WORD
.WORD
• WORD
• WORD
• WORD
.WORD
.WORD
• WORD
.WORD
• WORD
• WORD
• WORD
.WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
• WORD
.WORD
.WORD
.WORD
.WORD
• WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
16384 • 0
16379. 402
16364 • 804
16340 • 1205
16305 • 1606
16261. 2006
16207. 2404
16143 • 2801
16069. 3196
15986 • 3590
15893 • 3981
15791 • 4370
15679. 4756
15557 • 5139
15426 • 5520
15286 • 5897
15137 • 6270
14978 • 6639
14811 • 7005
14635 • 7366
14449 • 7723
14256 • 8076
14053 • 8423
13842 • 8765
13623 • 9102
13395 • 9434
13160 • 9760
12916 • 10080
12665 • 10394
12406 • 10702
12140 • 11003
11866 • 11297
11585 • 11585
11297 • 11866
11003 • 12140
10702. 12406
10394, 12665
10080. 12916
9760. 13160
9434 • 13395
9102. 13623
8765, 13842
8423, 14053
8076, 14256
7723, 14449
7366, 14635
7005, 14811
5-105
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
• WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
6639. 14978
6270. 15137
5897. 15286
5520. 15426
5139. 15557
4756. 15679
4370 • 15791
3981. 15893
3590. 15986
3196. 16069
2801. 16143
2404. 16207
2006. 16261
1606. 16305
1205. 16340
804. 16364
402. 16379
O. 16384
-402. 16379
-804. 16364
-1205. 16340
-1606. 16305
-2006. 16261
-2404. 16207
-2801. 16143
-3196. 16069
-3590. 15986
-3981. 15893
-4370. 15791
-4756. 15679
-5139. 15557
-5520. 15426
-5897. 15286
-6270. 15137
-6639. 14978
-7005. 14811
-7366. 14635
-7723. 14449
-8076. 14256
-8423. 14053
-8765. 13842
-9102. 13623
-9434. 13395
-9760. 13160
-10080. 12916
-10394. 12665
-10702. 12406
-11003. 12140
-11297. 11866
-11585. 11585
-11866. 11297
-12140. 11003
-12406. 10702
-12665. 10394
-12916, 10080
.....
co
"'1:1'
Z•
oC
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
•WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
• WORD
.WORD
.WORD
-13160,
-13395.
-13623,
-13842,
-14053,
-14256.
-14449.
-14635.
-14811,
-14978,
-15137,
-15286,
-15426.
-15557,
-15679,
-15791,
-15893,
-15986.
-16069,
-16143,
-16207,
-16261,
-16305.
-16340,
-16364,
-16379,
-16384,
9760
9434
9102
8765
8423
8076
7723
7366
7005
6639
6270
5897
5520
5139
4756
4370
3981
3590
3196
2801
2404
2006
1606
1205
804
402
0
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
-16379,
-16364,
-16340.
-16305,
-16261,
-16207,
-16143,
-16069,
-15986,
-15893,
-15791,
-15679,
-15557.
-15426,
-15286,
-15137.
-14978,
-14811,
-14635.
-14449,
-14256,
-14053.
-13842,
-13623,
-13395,
-13160,
-402
-804
-1205
-1606
-2006
-2404
-2801
-3196
-3590
-3981
-4370
-4756
-5139
-5520
-5897
-6270
-6639
-7005
-7366
-7723
-8076
-8423
-8765
-9102
-9434
-9760
.WORD
.WORD
.WORD
.WORD
.WORD
•WORD
.WORD
• WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
• WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
5·106
-12916, -10080
-12665, -10394
";'12406. -10702
-12140, -11003
-11866, -11297
-11585, -11585
-11297 • -11866
-11003, -12140
-10702. -12406
-10394, -12665
-10080, -12916
-9760, -13160
-9434, -13395
-9102, -13623
-8765, -13842
-8423, -14053
-8076, -14256
-7723, -14449
-7366, -14635
-7005, -14811
-6639, -14978
-6270, -15137
-5897, -15286
-5520 • -15426
-5139, -15557
-4756, -15679
-4370, -15791
-3981, -15893
-3590, -15986
-3196, -16069
-2801, -16143
-2404. -16207
-2006, -16261
-1606, -16305
-1205, -16340
-804, -16364
-402, -16379
0, -16384
402, -16379
804, -16364
1205, -16340
1606, -16305
2006, -16261
2404, -16207
2801, -16143
3196, -16069
3590, -15986
3981, -15893
4370, -15791
4756. -15679
5139. -15557
5520, -15426
5897, -15286
6270, -15137
6639, -14978
.
l>
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
• WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
.WORD
Z
7005, -14811
7366, -14635
7723, -14449
8076, -14256
8423, -14053
8765, -13842
9102, -13623
9434, -13395
9760, -13160
10080, -12916
10394, -12665
10702, -12406
11003, -12140
11297, -11866
11585, -11585
11866, -11297
12140, -11003
12406, -10702
12665, -10394
12916, -10080
13160, -9760
13395, -9434
13623, -9102
13842, -8765
14053, -8423
14256, -8076
14449, -7723
14635, -7366
14811, -7005
14978, -6639
15137, -6270
15286, -5897
15426, -5520
15557, -5139
15679, -4756
15791, -4370
15893, -3981
15986, -3590
16069, -3196
16143, -2801
16207, -2404
16261, -2006
16305, -1606
16340, -1205
16364, -804
16379, -402
0l:Io
Q)
-....
.END
•
5·107
APPENDIX C
Test Data and Expected Results
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
1
PAGE:
1
2
3
4
5
6
7
8
9 0200
0202
10 0204
0206
11 0208
020A
12 020C
020E
13 0210
0212
14 0214
0216
15 0218
021A
16 021C
021E
17 0220
0222
18 0224
0226
19 0228
022A
20 022C
022E
21 0230
0232
22 0234
0236
23 0238
023A
24 023C
023E
25 0240
0242
26 0244
0246
27 0248
024A
28 024C
024E
29 0250
0252
30 0254
TEST DATA FOR FFT ROUTINES.
; OBTAINED FROM : PROGRAMS FOR DIGITAL SIGNAL PROCESSING, IEEE PRESS,
CHAPTER 1 BY GOLD.
0200
0004
0000
9A03
3301
E102
2902
F201
CF02
E800
1C03
E2FF
1203
F9FE
BB02
42FE
2602
C9FD
6901
96FD
9800
A5FD
D2FF
EFFD
22FF
67FE
99FE
FBFE
42FE
9BFF
21FE
3500
32FE
BAOO
70FE
1F01
DOFE
5E01
45FF
7301
COFF
6101
3600
2001
• = 0200
.WORD 1024, 0
.WORD 922, 307
.WORD 737, 553
.WORD 498, 719
.WORD 232, 796
.WORD -30, 786
.WORD -263, 699
.WORD -446, 550
.WORD -567, 361
.WORD -618, 155
• WORD -603, -46
.WORD -529, -222
.WORD -409, -359
.WORD -261, -446
.WORD -101, -479
.WORD 53, -462
.WORD 186, -400
.WORD 287, -304
• WORD 350, -187
.WORD 371, -64
.WORD 353, 54
.WORD 301, 154
5-108
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER, REV: C, 30 JUL 86
0256
31 0258
025A
32 025C
025E
33 0260
0262
34 0264
0266
35 0268
026A
36 026C
026E
37 0270
0272
38 0274
0276
39 0278
027A
40 027C
027E
41
42
43
44 0280
0282
45 0284
0286
46 0288
028A
47 028C
028E
48 0290
0292
49 0294
0296
50 0298
029A
51 029C
029E
52 02AO
02A2
5 .. 02A4
02A6
54 02A8
02AA
55 02AC
02AE
56 02BO
02B2
57 02B4
9AOO
El00
E500
8600
1201
2600
lFOl
CCFF
ODOl
81FF
E300
49FF
A600
2AFF
5FOO
23FF
1500
33FF
DDFF
55FF
98FF
PAGE:
2
.WORD 225, 229
.WORD 134, 274
• WORD 38, 287
.WORD -52, 269
.WORD -127, 227
.WORD -183, 166
• WORD -214, 95
.WORD -221, 21
.WORD -205, -48
.WORD -171, -104
THESE ARE THE EXPECTED DFT RESULTS.
C702
OOOE
2BOB
3420
9D25
76DB
7707
AAFO
8704
10F7
9F03
DDF9
3303
71FB
F502
79FC
CE02
35FD
B202
C4FD
9D02
37FE
8C02
97FE
7F02
E9FE
7302
• WORD 711, 3584
.WORD 2859, 8244
.WORD 9629, -9354
.WORD 1911, -3926
.WORD 1159, -2288
.WORD 927, -1571
.WORD 819, -1167
.WORD 757, -903
.WORD 718, -715
.WORD 690, -572
.WORD 669, -457
.WORD 652, -361
.WORD 639, -279
.WORD 627, -205
5·109
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
0286
58 02B8
02BA
59 02BC
02BE
60 02CO
02C2
61 02C4
02C6
62 02C8
02CA
63 02CC
02CE
64 02DO
02D2
65 02D4
02D6
66 02D8
02DA
67 02DC
02DE
68 02EO
02E2
69 02E4
02E6
70 02E8
02EA
71 02EC
02EE
72 02FO
02F2
73 02F4
02F6
74 02F8
02FA
75 02FC
02FE
76
77
78
79
80
81
82 0300
0302
83 0304
0306
84 0308
030A
85 030C
030E
33FF
6902
75FF
6002
B3FF
5802
EEFF
5102
2700
4A02
5FOO
4302
9800
3C02
0200
3502
OF01
2E02
5001
2702
9801
2002
EB01
1802
4502
1002
B302
0702
3B03
FE01
EC03
F701
E004
F701
4F06
1202
C108
PAGE:
3
.WORD 617, -139
.WORD 608, -77
.WORD 600, -18
.WORD 593, 39
.WORD 586, 95
.WORD 579, 152
.WORD 572, 210
.WORD 565, 271
.WORD 558, 336
.WORD 551, 408
.WORD 544, 488
.WORD 536, 581
.WORD 528, 691
.WORD 519, 827
.WORD 510, 1004
.WORD 503, 1248
.WORD 503, 1615
.WORD 530, 2241
TEST DATA FOR FFT ROUTINES.
OBTAINED FROM :
0004
0000
9A03
3301
E102
2902
F201
CF02
.WORD 1024, 0
.WORD 922, 307
.WORD 737, 553
.WORD 498, 719
5-110
.
»
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEIIBLER,REV:C,30 JUL 86
PAGE:
4
Z
0l:Io
CD
......
86 0310
0312
87 0314
0316
88 0318
031A
89 031C
031E
90 0320
0322
91 0324
0326
92 0328
032A
93 032C
032E
94 0330
0332
95 0334
0336
96 0338
033A
97 033C
033E
98 0340
0342
99 0344
0346
100 0348
034A
101 034C
034E
102 0350
0352
103 0354
0356
104 0358
035A
105 035C
035E
106 0360
0362
107 0364
0366
108 0368
036A
109 036C
036E
110 0370
0372
111 0374
E800
1C03
E2FF
1203
F9FE
BB02
42FE
2602
C9FD
6901
96FD
9BOO
A5FD
D2FF
EFFD
22FF
67FE
99FE
FBFE
42FE
9BFF
21FE
3500
32FE
BAOO
70FE
1F01
DOFE
5E01
45FF
7301
COFF
6101
3600
2D01
9AOO
ElOO
E500
8600
1201
2600
1F01
CCFF
OD01
81FF
E300
49FF
A600
2AFF
5FOO
23FF
• WORD 232, 796
.WORD -30, 786
.WORD -263, 699
.WORD -446, 550
.WORD -567, 361
.WORD -618, 155
.WORD -603, -46
• WORD -529, -222
.WORD -409, -359
.WORD -261, -446
.WORD -101, -479
.WORD 53, -462
.WORD 186, -400
.WORD 287, -304
.WORD 350, -187
.WORD 371, -64
.WORD 353, 54
.WORD 301, 154
.WORD 225, 229
.WORD 134, 274
• WORD 38, 287
• WORD -52, 269
• WORD -127, 227
.WORD -183, 166
.WORD -214, 95
.WORD -221, 21
5·111
.
1'0
CO
~
Z
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
PAGE:
5
<
0376 1500
112 0378 33FF
037A DOFF
.WORD -205, -48
113 037C 55FF
037E 98FF
114
115
.WORD -171,
-104
• END
@
ERROR, OPERAND MUST BE SINGLE VALID SYMBOL NAME
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
PAGE:
6
SYMBOL TABLE
A
SP
00C8 W
00C4 W
B
X
OOCC W
OOCE W
K
OOCA W
5-112
PC
00C6 W
NATIONAL SEMICONDUCTOR CORPORATION
HPC CROSS ASSEMBLER,REV:C,30 JUL 86
PAGE:
7
MACRO TABLE
NO WARNING LINES
1 ERROR LINES
384
ROM BYTES USED
SOURCE CHECKSUM
OBJECT CHECKSUM
= 7A03
= 0705
INPUT
FILE C:TSTDAT.MAC
LISTING FILE C :TSTDAT .PRN
5-113
National Semiconductor
Application Note 497
Joe Cocovich
Expanding the HPC
Address Space
INTRODUCTION
The maximum address range of the HPC family of 16-bit
High Performance microControliers is 64k bytes using the
external address/data bus to interface with external memory. This application note describes a method to increase the
amount of memory in a system to 544k bytes utilizing bank
switching techniques. Block diagrams are presented to aid
in circuit design. Software examples are given for memory
and bank management.
ways on-chip by the HPC, it never looks at the external address/data bus and will not read external memory in this
range. Therefore, the first 256 bytes in each bank of memory in the BANK memory space will not be accessible by the
HPC, but this address range (on chip resources) is directly
accessible by any bank of memory in the BANK memory
address space. This is why Figure 1 shows a total available
memory of 536.5k.
HPC ADDRESSING
The interrupt vectors are mapped into logical addresses
FFFO to FFFF which are in the MAIN memory address
space. Interrupts are handled properly if they occur whi~e
executing a program out of one of the banks of memory In
BANK memory space, since the interrupt vector locations
have A15 set to '1' which will allow access to the MAIN
memory space. However, these interrupt vectors must either point to a routine in the MAIN memory address space
which performs the interrupt service or point to code that
selects the appropriate bank of memory in the BANK memory space and go there if the interrupt service routine is
located there.
The stack must be located so that it can be directly accessible from anywhere in memory. It can be placed in the MAIN
memory space or in the on-chip RAM. Programs and data
storage that must be shared and directly accessed by all
memory banks in the BANK memory space should also reside in the MAIN memory space.
Program memory addressing is accomplished by the 16-bit
Program Counter on a byte basis (instructions are always
fetched a byte at a time). Memory can be addressed as
words or bytes directly by instructions or indirectly through
the B, X and SP registers. Words are always addressed on
even-byte boundaries. The HPC uses memory-mapped organization to support registers, I/O and on-chip peripheral
functions.
The external address/data bus of the HPC is 16 bits wide.
This means the maximum address that the bus can hold is
FFFF for a maximum address range of 64K bytes (65,536).
Keep in mind, this uses the external address/data bus
(AO:A 15 for Address/Data and B10, 11, 12, 15) for Control.
BANK SWITCHING
If more than 64k of addressing is needed in the HPC system, the following method of increasing memory space can
be used. Divide the total address range into two halves (32k
bytes each). One half of this address range will be the MAIN
memory address space. The MAIN memory address space
will contain logical addresses (those addresses which the
Program Counter can generate) in the range 8000 to FFFF
and is accessed when A15 is a '1'. This includes the Interrupt vectors' and the Reset vector memory locations. The
other half of the address range will be the BANK memory
address space. The BANK memory address space will contain logical addresses in the range 0000 to 7FFF and is
accessed when A15 is a '0'. This includes the on-chip I/O,
registers, and RAM at locations 0000 to 01 FF.
Now, four additional address lines are created using Port B
pins (B8, B9, B13, B14). This prevents the use of the four
timer synchronous outputs TSO-TS3 which are the alternate functions for these pins. The BANK memory is now
addressed using AO:A14, B8, B9, B13, B14 and is accessed
when A15 is a '0'. The BANK memory address space is now
expanded to 512k bytes broken down into 16 individually
selectable banks of 32k bytes each selected by these four
bits of Port B.
A look at Table 1 and Figure 1 quickly tells you that only one
bank in the BANK memory space can share the logical address range 0000:7FFF at anyone time. Therefore, programs running in the BANK memory address space can only
directly access data and programs in the MAIN memory address space or in it's own bank (selected by B8, B9, B13,
B14). On chip resources, which include RAM, I/O, and registers are mapped into logical addresses 0000 to 01 FF.
These logical addresses are in the BANK memory address
space, but, since these addresses are considered to be ai-
HPC OPERATING MODES
The HPC must be configured to run in one of it's Expanded
modes of operation by setting the EA bit in the PSW to be
able to address the BANK memory range of 0000 to 7FFF.
This memory expansion addressing scheme will work if the
HPC is configured in either the Normal Expanded mode
(EXM pin tied low) or ROM less Expanded mode (EXM pin
tied high). The Normal mode differs from the ROM less
mode only by the fact that the HPC will access the on-chip
ROM for addresses in the range of EOOO to FFFF (in the
case of the HPC16083) and will access the external MAIN
memory for addresses in the range of 8000 to DFFF.
The external data bus size is determined once, at reset, by
sampling the state of HBE (B12). If HBE is high when sampled, the HPC enters 8-bit mode. In 8-bit mode, only pins
AO-A7 are used to transfer data and pins A8-A15 continue
to hold the most-significant eight bits of the address. So,
only the lower eight bits of the address need to be latched
externally (Figure 2). If HBE is low when sampled, the HPC
enters 16-bit mode. In 16-bit mode, all 16 pins of Port A are
used to transfer data as well as addresses. Two octal latches are then required externally to hold each address as it is
issued by the HPC. The signal ALE from the HPC clocks the
latches (Figure 3).
Keep in mind that if the external memory is configured as
8-bit memory, then the program stack must be in internal
on-chip RAM because it has to be accessible as 16-bit
words. If the external memory is configured as 16-bit memory then the stack can be in external RAM but must be in the
MAIN memory address space to be directly accessible by all
banks.
5-114
PROGRAMMING CONVENTIONS
A convention must be followed for maintaining linkages between the programs and data running in the MAIN memory
space and the programs and data running in the BANK
memory space. For the following discussion, the MAIN
memory space will be referred to as just another bank of
memory.
MAIN bank reserved portion
A portion of the MAIN memory bank should be reserved for
Jump instructions to subroutines in the MAIN memory bank
that need to be called by programs running in any selected
bank in the BANK memory space. These Jump instructions
serve as entry points for programs and subroutines. Typically, common functions that are required by programs running
in several banks would be put in the MAIN memory bank.
These could include: interrupt service routines, I/O drivers,
and data handling and conversion routines. This portion
also contains address pointers to tables of data in the MAIN
memory bank that also are required by programs running in
any selected bank in the BANK memory space. See Listing
1 for an example.
BANK memory reserved portion
A portion of each bank in the BANK memory space should
be reserved for Jump instructions to subroutines in that
bank that need to be called by programs running in the
MAIN memory bank. These Jump instructions serve as entry points for programs and subroutines. For example, each
bank in the BANK memory space could contain routines
that perform unique but related functions. One bank could
be reserved for math routines; another bank could perform
message handling; and yet another could contain diagnostic
routines. All of these functions could be scheduled and executed from some sort of Supervisor running in the MAIN
memory bank performing the linkages to all these routines
thru the entry points. This reserved portion of each bank
also contains address pointers to tables of data in that bank
that also are required by programs running in the MAIN
memory bank. In the case of a bank running message handling routines, address pointers could be inserted to point to
buffers that programs running in MAIN memory need to access. See Listing 2 for an example.
Linkage areas
These reserved portions of each memory bank (MAIN
space or BANK space) must be fixed and known to each
other memory bank that requires access to programs and
data in that bank. Therefore, one other requirement in each
bank is a set of labels that are assigned the values of the
pointer locations to subroutines and tables in the bank of
interest (see Listings 3 and 4).
Interrupts
Regardless of where the interrupt service routine actually
resides, an image of the bank selected must be retained by
the service routine to allow it to return to the appropriate
bank when complete. If the interrupt service routine is in the
MAIN memory bank, the linkage is handled in the normal
fashion where the interrupt vector points to the service routine. The interrupt service can reside in the BANK memory
space and takes a little extra overhead for the linkage.
To call a program in the MAIN memory bank from the BANK
memory space, merely execute a Jump to SubRoutine
through a pointer in the MAIN memory bank:
JSRL CMPBLNK
;see Listing 1 and 4
EXAMPLE SOFTWARE
Now that a convention has been established for communicating between the MAIN memory space and the BANK
memory space, let's take a look at some sample code that
can be used to move data between these memory spaces.
In order to make the selection of bank memory efficient, it is
important to keep in mind that the four bits of the high byte
of Port B that are used to select a bank of memory in the
BANK memory space can be written to directly since the
other 4 bits of this byte of Port B are used for memory control outputs (the external control bus) and are not affected
by a write to the high byte of Port B.
Bank to Bank data transfer by MAIN
Listing 6 shows the setup required to initialize the linkage
area in order to perform a transfer of data from one bank to
another bank in the BANK memory space by a program
running in the MAIN memory space. This involves setting up
the RAM locations that are used to 'select' the source bank
and the destination bank, select the source bank to determine the starting address of the area to move, select the
destination bank to determine the starting address of the
area to move data into, then finally calling the subroutine in
MAIN memory that performs the move. After the setup portion, the subroutine that performs the transfer is presented.
This code assumes that the external memory is configured
in 16-bit mode.
Bank to MAIN data transfer by Bank
Listing 7 presents a similar example for moving blocks of
data from a bank in BANK memory to MAIN memory by a
program running in that bank. This code also assumes that
the external memory is configured in 16-bit mode.
External 8-blt mode
If the external memory is configured in a-bit mode, the setup
portion changes because the initialization of the RAM address pointers SSTART, DSTART and DEND requires building word address pointers from word pointers in the external
reserved areas of each bank. In a-bit mode, this requires
two a-bit transfers compared to one 16-bit transfer in 16-bit
mode (see Listing 8). Once these address pOinters have
been built, however, the subroutine that actually performs
the move does not have to change because 1) word transfers are allowed between On-chip RAM and registers regardless of the mode and 2) the subroutine performs byte
moves. To improve speed in the 16-bit mode, this subroutine can be modified to perform 16-bit moves. However,
keep in mind that this will impose the restriction on the address pointers in the linkage areas of requiring that addresses be on word boundaries. Listing 9 presents a similar example for moving blocks of data from a bank in BANK memory to MAIN memory by a program running in that bank.
One last requirement in the MAIN memory bank, if it is to
perform bank to bank moves and for general housekeeping,
is to reserve two byte locations to be used to keep track of
the bank currently selected (high byte value on Port B) being used in the transfer of data (see Listing 5).
From the MAIN memory bank, the user can access all memory in the system. He can call subroutines in any bank in the
BANK memory space and read/write data to the entire
memory. From any bank in the BANK memory space, the
user can call subroutines in the MAIN memory bank and
read/write data to the MAIN memory bank in addition to his
own local bank.
The basic procedure used to call a program in the BANK
memory space from the MAIN memory bank is merely to set
the proper value on the Port B select lines and execute a
Jump to SubRoutine through a pointer in the selected bank:
5-115
PROGRAM DEVELOPMENT
CONCLUSION
What has been presented is a method to expand the memory space of the HPC to 544k. Although this method utilized
four bits of Port B to accomplish the extra addressing, theoretically, the remaining 8 bits could have been used if not
required for other purposes. This could mean a maximum
addressability for the HPC of greater than 128 Megabytes.
However, the MOLE will only support the fixed definition of
four extra address lines. Clever utilization of existing resources can enable you to get the most out of hardware and
software limited only by one's imagination.
The MOLE monitor software can support the development
of HPC programs in multiple banks of memory. It provides
the means of qualifying a trigger condition, as set in Trace
or Breakpoint functions, with the memory bank number. The
BANK command will allow a trigger only when executing in
the memory bank of interest. The MOLE supports a total of
16 memory banks which are normally selected by 4 bits of
Port B as described earlier. See the HPC Personality Board
User's Manual for further detail on this command.
TABLE I. Logical Addresses vs Physical Memory Locations
Logical
Address
0000:7FFF
0000:7FFF
0000:7FFF
0000:7FFF
0000:7FFF
0000:7FFF
0000:7FFF
0000:7FFF
0000:7FFF
0000:7FFF
0000:7FFF
0000:7FFF
0000:7FFF
0000:7FFF
0000:7FFF
0000:7FFF
8000:FFFF
Physical
Address
HI Byte
Port B
Bank #
0
1
2
3
4
5
6
7
8
00
01
02
03
20
21
22
23
40
41
42
43
60
61
62
63
9
A
B
C
D
E
F
00000:07FFF
08000:0FFFF
10000:17FFF
18000: 1FFFF
20000:27FFF
28000:2FFFF
30000:37FFF
38000:3FFFF
40000:47FFF
48000:4FFFF
50000:57FFF
58000:5FFFF
60000:67FFF
68000:6FFFF
70000:77FFF
78000:7FFFF
08000:0FFFF
(BANK)
(MAIN)
WAIN
~
!:QQ!lli
BANK
FrFF
~
Pori B
hi-by.!!
LOGICAL
8000
HFF
63
.>---..1
ANK
~
0200
HrF
78200
HrFF
62
E
• ______
HFF
:
:
BANK
SPACE
._--
0200
~
0200
HFF
70200
0200
68200
7FFF
OFFFF
0200
08200
7rFF
07FFF
0200
00200
6FFFF
BANK
0
---
61
01
00
OHF
OHF
0000
0000
512K (-8K)=1504KI
32K (+O.5K)= 132.5KI
TL/OO/9342-1
FIGURE 1. How BANK Memory Is Mapped Into the HPC Address Space
5-116
LATCHED
ADDRES;:-S~B::=..:US::.....-_ _ _ _...,
LAO: LA7
LAO: LA7
AO:A7
CSI
CSI
CSI
32Kx8
MAIN
HPC
32Kx 8
BANK
#2
32Kx8
BANK
#1
A8:A14
A8:A14
A15
LAO :LA7
AO:A7
AO:A7
A8:A14
A8:A14
A8:A14
CS2
CS2
CS2
00:D7
DO:D7
AO:A7
AO:A7
AO:AI5~__~~~~~~~____________________________~__-r~____________~
A15
B8,9, 13, 14
r-________________
......::.:;BA;::.:N~K..::S.::.:EL:.::.EC::=..:T...::C:.::O.:..:.NT:.:.;R~OL::...::.:BU:.::S~____________
_t.:.::.:.:.::.___.I
FIGURE 2. HPC In S-Bit Mode
TL/DD/9342-2
LATCHED ADDRESS BUS
I ILAI ,LAI' ~
-
LAO -
r-
LAO _
CSI
I - - CSI
AO:A7
;---
AO:AI3
LAO :LA7
16Kx8
MAIN
LATCH
Bl0
(ALE)
AO:AI5
-
(EVEN BYTE)
LA15
I - - CS2
I---
I--I---
AO :A13
OO:~
DO :07
I IAO:A7
LAO CSI
I IA8:AI5
DO :07
LAI,LA 14
AO :A13
16Kx8
BANK
#2
(EVEN BYTE)
CS'li
CS'
I IAO,A7
ADDRESS/DATA BUS
~ CS2
I
16Kx8
BANK
#1
(EVEN BYTE)
HPC
_G~
I
I ILAI ,LA14 ~
DO:~
I
I IA8:AI5
00:07
CS2 l -
IAO'A7
I A8:Al
00:07
I-- CS2
~I-
G
- r-- B8,9,13,14
B12 (HBE)
<-
16Kx8
MAIN
LATCH
A87Ai5
LA8: LA15
"'---
I
(ODD BYTE)
CSI
AO : A13
I ILA1:LAI4
I
I
16Kx8
BANK
#1
(ODD BYTE)
CSI
r
16Kx8
BANK
#2
(ODD BYTE)
CSI
AO : A13
J
I
i411
I
LA15
BANK SELECT CONTROL BUS
AO:AI3
IILA1:LA 14
ILA1:LAI4
LATCHED ADDRESS BUS
I
01
G2 SELECTOR
IA,B,C,O
Glh
TL/DD/9342-3
FIGURE 3. HPC In 16-Bit Mode
5·117
.=08000
;set PC counter to 8000
;This code resides in the MAIN memory bank
The following address pointers are inserted to allow
programs running in BANK memory to find these
locations. They represent the starting and ending
location for code in MAIN memory •
•WORD INIT ;addr pointer to first location in bank
.WORD PROGEND
;addr pointer to last location in bank
The following Jump instructions are inserted to allow
programs running in BANK memory to call these
subroutines. They represent subroutines that compare
blocks of memory in MAIN memory space with blocks of
memory in BANK memory space or compare blocks of memory
in BANK memory tor zeros.
JMPL CMPM
JMPL CMPBFB
;entry for compare blocks (MAIN-BANK)
;entry for compare BANK cleared
LISTING 1. MAIN Bank Reserved Portion
.=0200
;set PC counter to 200
;This code resides in any bank in BANK memory
The following address pointers are inserted to allow
programs running in MAIN memory to tindthese
locations. They represent the ending location for code
in this bank of BANK memory.
.WORD PROGEND
;addr pointer to last loc in this bank
The following Jump instructions are inserted to allow
programs running in MAIN memory to call these
subroutines. They represent subroutines that compare
blocks of memory in MAIN memory space with blocks ot
memory in this bank, diagnostic routines, and interrupt service routine.
JMPL CMPMB
JMPL BTEST
JMPL BINTS
;entry for comp blocks (MAIN-this bank)
;entry for this bank's diag routines
;entry for this bank's interrupt service routine
LISTING 2. Typical Bank Reserved Portion
5-118
;This oode resides in any bank in BANK memory
linkages to MAIN memory
MSTART = 08000
MEND
08002
;addr of pointer to first avail 100
;addr of pointer to last avail 100
CMPM
;addr of JMPL to routine that oompares
move results
;addr of JMPL to routine that oompares
if a blook in seleoted BANK is zero
=
CMPBLNK
08004
=
08007
LISTING 4. Typical Bank Linkage Area
5·119
•
r....
en
~
:Z
cs:
;This code resides in the MAIN memory bank
The following locations are used for bank to bank moves
and compares
BANKS
OleO
;source bank byte value
BANKD
Olel
;destination bank byte value
BANKO
BANKl
BANK2
BANK3
BANK4
BANK5
BANK6
BANK7
BANK8
BANK9
BANKA
BANKB
BANKe
BANKD
BANKE
BANKF
0
1
2
3
020
021
022
023
040
041
042
043
060
061
062
063
;Port B high byte value to select bank 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Main Memory Bank is logical and physical address range
8000:FFFF. Switched Memory Banks are logical addresses
in the range 0000:7FFF combined with the
Port B(14.l3.9.8) bits to create physical addresses in
the range 00000:7FFFF
LISTING 5. BANK Memory Management
LD M(OE3).BANK1;set bank select lines to select bank 1
JSRL B1TEST
;see Listing 2 and 3
•
•
•
INT35:
LD
LD
JSRL
BANKS.M(OE3)
M(OE3).BANK2
B2INTS
;save bank interrupted from
;set bank select lines to select bank 2
;see listing 2 and 3
•
•
•
LD
RETI
M(OE3).BANKS
;restore bank interrupted from
•
•
.IPT
2.INT35
;set interrupt vector
5-120
;This code resides in the MAIN memory bank
LD M(BANKS) ,BANKO
LD M(BANKD) ,BANKl
LD M(OE3) ,BANKO
LD W(SSTART) ,W(BOSTART)
LD M(OE3) ,BANKl
LD W(DSTART) ,W(B1START)
LD W(DEND),W(B1START)
ADD W(DEND) ,1023
JSRL MOVBB
;prepare to move data from Bank 0
;to Bank 1
;select Bank 0
;set starting address in source bank
;select Bank 1
;set starting address in destination bank
;set ending address in destination bank
;to lK greater than starting address
;do it
This subroutine moves data from bank memory to bank memory
where the source bank is defined by the contents of the byte
at RAM location BANKS and the destination bank is defined by
the contents of the byte at RAM location BANKD. In addition,
the following locations must be set up before calling:
SSTART -+ RAM location containing source bank start address
DSTART -+ RAM location containing destination bank start address
DEND -+ RAM location containing destination bank end address
MOVBB:
LD
LD
LD
LOOPBB:
LD
LD
B,W(DSTART)
K,W(DEND)
X,W(SSTART)
;B +- starting address (destination)
;K +- ending address (destination)
;X +- starting address (source)
M(OE3) ,M(BANKS)
A,M(X+)
;select source BANK
;byte at source into A
;increment source pointer
;select destination BANK
;A into byte at destination, bump pntr
;back for more if B less than K
LD M(OE3),M(BANKD)
XS A,M(B+)
JP LOOPBB
RET
LISTING 6. Move Data by MAIN from BANK to BANK (16-Blt Mode)
•
5-121
~
en
~
:Z
c(
r-------------------------------------------------------------------------------------------,
;This code resides in any bank in BANK memory
LD W(SSTART) ,TABLEl
LD W(DSTART) ,W(MSTART)
LD W(DDEND),TABLEl+1023
JSRL MOVE
;starting address of table in this memory
;starting address in main memory
;ending address in main memory
;do it
•
•
•
•
•
This subroutine moves data from this bank to main memory
SSTART -+ RAM location containing source memory start address
DSTART -+ RAM location containing destination memory start addr
DEND-+ RAM location containing destination memory end address
MOVE:
LD
LD
LD
LOOPBM:
LD
B,W(DSTART)
K,W(DEND)
X,W(SSTART)
;B +- starting address (destination)
;K +- ending address (destination)
;X +- starting address (source)
A,M(X+)
;byte at source into A
;increment source pointer
;A into byte at destination, bump pntr
;back for more if B less than K
XS A,M(B+)
JP LOOPBM
RET
LISTING 7. Move Data by BANK from BANK to MAIN (16-Blt Mode)
5-122
.
>
Z
;This code resides in the MAIN memory bank
LD M(BANKS) ,BANKO
;prepare to move data from Bank 0
LD M(BANKD),BANKl
;to Bank 1
LD M(OE3) ,BANKO
;select Bank 0
LD M(SSTART),M(BOSTART) ;set starting address in source bank
LD M(SSTART+l),M(BOSTART+l)
LD M(OE3) ,BANKl
;select Bank 1
LD M(DSTART) ,M(B1START) ;set starting address in destination bank
LD M(DSTART+l),M(B1START+l)
LD M(DEND) ,M(B1START)
;set ending address in destination bank
LD M(DEND+l),M(B1START+l)
ADD M(DEND) ,L(1023)
;to lK greater than starting address
ADC M(DEND+l) ,H(1023)
JSRL MOVBB
;do it
CD
"'......
"
•
•
•
•
•
This subroutine moves data from bank memory to bank memory
where the source bank 1s defined by the contents of the byte
at RAM location BANKS and the destination bank is defined by
the contents of the byte at RAM location BANKD. In addition,
the following locations must be set up before calling:
SSTART ~ RAM location containing source bank start address
DSTART ~ RAM location containing destination bank start address
DEND ~ RAM location containing destination bank end address
MOVBB:
LD
LD
LD
LOOPBB:
LD
LD
B,W(DSTART)
K,W(DEND)
X,W(SSTART)
;B
;K
;X
M(OE3),M(BANKS)
A,M(X+)
;select source BANK
;byte at source into A
;increment source pointer
;select destination BANK
;A into byte at destination, bump pntr
;back for more if B less than K
LD M(OE3),M(BANKD)
XS A,M(B+)
JP LOOPBB
RET
~
~
~
starting address (destination)
ending address (destination)
starting address (source)
LISTING 8. Move Data by MAIN from BANK to BANK (8-Blt Mode)
5·123
•
~
en
"'If'
Z•
~----------------------------------------------------------------------------------~
jThis code resides in any bank in BANK memory
ct
LD M(SSTART) ,L(TABLE1) ;starting address of table in this memory
LD M(SSTART+1),H(TABLE1)
LD M(DSTART) ,M(MSTART) ;starting address in main memory
LD M(DSTART+1),M(MSTART+1)
LD M(DEND) ,M(MSTART)
;set ending address in main memory
LD M(DEND+l) ,M(MSTART+l)
ADD M(DEND) ,L(1023)
ito lK greater than starting address
ADC M(DEND+1),H(1023)
JSRL MOVE
;do it
•
•
•
•
•
This subroutine moves data from this bank to main memory
SSTART -+ RAM location containing source memory start address
DSTART -+ RAM location containing destination memory start addr
DDEND -+ RAM location containing destination memory end address
MOVE:
LD
LD
LD
LOOPBM:
LD
B,W(DSTART)
K,W(DEND)
X,W(SSTART)
;B
;K
;X
A,M(X+)
;byte at source into A
;increment source pointer
jA into byte at destination, bump pntr
jback for more if B less than K
XS A,M(B+)
JP LOOPBM
RET
~
~
~
starting address (destination)
ending address (destination)
starting address (source)
LISTING 9. Move Data by BANK from BANK to MAIN (B-Blt Mode)
5-124
Assembly Language
Programming for the
HPCTM
National Semiconductor
Application Note 510
Steve McRobert
HOW TO WRITE SHORT, EFFICIENT, BUT
can be used as general purpose memory locations but also
have a specific function as pointers to memory. These instructions take up very little ROM space because the address of the variable to be operated on is contained in the
pointer register and the pointer register to be used is specified as part of the instruction. An instruction such as increment, using register indirect, can thus be only 1 byte long as
it does not need to be followed by a byte specifying the
address of the variable.
UNDERSTANDABLE ASSEMBLER PROGRAMS
INTRODUCTION
One of the design objectives of the HPC family was that it
should be very easy to use. With this in mind the instruction
set has been designed so that it obeys a very simple set of
rules. Once these rules have been learned, the programmer
can write code with very little reference to instruction manuals.
The HPC is fully memory mapped. Every piece of hardware
attached to an HPC core appears as a byte or a word in a
linear 64K byte address space. Any data movement or arithmetic instruction can operate on any memory location and
everything in the HPC has a memory location, including the
accumulator. All of the liD ports, the peripheral control registers, RAM and ROM are treated in exactly the same fashion as far as the assembly language programmer is concerned.
The HPC assembly language syntax can be explained by
describing the instruction codes and the addressing modes.
The instruction code tells the processor what operation it is
performing, such as an add, a subtract, a multiply, a divide
or a data movement instruction. The addressing mode is the
way that the programmer specifies the value or values to be
operated on to the microprocessor itself.
ADDRESSING MODES
Operations can be performed on any memory location. One
can, for example, increment or decrement any byte or word
of any memory location in the HPC. Increment and decrement are examples of single address instructions. These
are instructions which have only one operand. Other examples are the bit set, bit test and bit clear instructions. These
five instructions are good examples of the basic thinking
behind the HPC instruction set. All of these instructions use
the same four addressing modes.
Direct
The simplest addressing mode to understand is that known
as direct. In this mode the address of the variable to be
operated on is included as part of the sequence of bytes
that comprises the entire instruction. For example, in order
to perform a decrement on memory location OFO this value
is included in the string of bytes that forms the instruction.
Examples:
DECSZ
OFO.B
INC
OFO.W
The increment instruction, like most other instructions with
HPC, can operate on either a byte or a word. A byte access
is specified by putting a B after the address of the variable,
a word access by writing W.
Examples:
INC
[B).B ;byte increment, B pointer
INC
[X).W ;word increment, X pointer
Indirect
B and X provide two 16-bit pointers to memory. Programmers will often wish to have more than two pointers in use
at anyone time. HPC therefore provides indirect addressing
mode. In this mode a 16-bit pointer to the location to be
accessed is stored in the basepage of the HPC. The instruction, therefore, is followed by a single byte which specifies
the address of this 16-bit pointer. The bottom 192 bytes of
RAM are on chip with the HPC and are in the so-called base
page. The base page is normally used for storing frequently
accessed variables as only a single byte of address is required to access a base page variable. When using indirect
addressing mode, the 16-bit pointer value must always be in
the base page.
Examples:
DECSZ [O].W
;decrement a word
INC
[OFE].B ;increment a byte
The base page is in the region of 0 to OFF bytes. This area
also contains the most frequently used registers such as the
accumulator. The programmer can thus use indirect addressing mode with registers such as the accumulator acting as the pointer. This is an example of the simplicity of the
HPC instruction set. Any operation can be performed on any
HPC register simply by invoking its address in the HPC
64 kbyte addressing space.
Indexed
The last of the four basic addressing modes is indexed
mode. Indexed is very similar to indirect except that an 8- or
16-bit immediate value follows the address of the 16-bit
pointer and is added to it to generate the address of the
variable to be accessed. This allows a table of values to be
located anywhere in memory and the pointer register need
only be implemented or decremented to move through the
table of values.
Examples:
INC
OFFOO [4].W
DECSZ 02 [2].B
Register Indirect
This addressing mode usually generates less bytes of code
than any other. HPC has two 16-bit registers, B and X, which
5-125
;increment a word
:decrement a byte
o,....
It)
Z•
This example shows the conversion of a 32-bit binary value
in words low and high into a 10-digit BCD number in the 10
bytes starting from 1. The conversion is performed one digit
at a time and the B register is used to point at the byte's
location where the digit is to be stored. The first instruction
of the programme therefore is to initialize the B register. The
divide instruction divides word high by 10 using immediate
direct addressing mode and stores the answer back in word
high. The remainder is stored in the X register. The divide
double instruction then divides X concatenated with word
low by 10. Because X contains a remainder, the result of
this division will always be a 16-bit value and can thus be
stored in word low. The remainder is stored in X and is in
fact the modulus and is thus the BCD digit that we have
derived on this pass through the numbers.
Note that these symbols cannot be redefined so the above
set of definitions should never be included in a user program.
IMPLIED ADDRESSING MODES
Some of the HPC's opcodes have been shortened by using
implied addressing mode. A few examples have already
been shown. This section describes some more special
cases. It could be said that accumulator as destination is an
example of an implied addressing mode, where the address
of the destination is coded into the instruction. There are
some special purpose instructions which use implied addressing mode for instructions which are used very frequently. In most cases these instructions look exactly the
same to the programmer as instructions using the addressing modes described earlier. For example there is a special
opcode for load B with an immediate value. The programmer could do this using the immediate direct addressing
mode but a special opcode has been provided to make this
instruction shorter.
Load Band K is a special immediate load which loads both
the Band K registers in one operation.
Carry Flag
Multiply and Divide
Finally, the divide double and multiply instructions both have
to manipulate 32-bit values. These therefore have to store
an operand in two concatenated registers. The HPC instruction set cannot specify two registers with one address.
Therefore these instructions default to using the X register
as the high word of their 32-bit value.
The source and destination of a multiply instruction are
specified as normal except that the 32-bit answer is stored
in the destination operand with the 16 high bits of the answer stored in the X register. The divide double instruction
basically performs the inverse of multiply, taking the 32-bit
value formed by X concatenated with the destination value
and dividing it by the source value. Divide double, like divide,
yields a 16-bit result and a 16-bit remainder. For both divide
double and divide the remainder is stored in the X register.
In both cases the K register is used for intermediate value
storage and is cleared as a result of this operation.
B,#ll
HIGH.W,#
This multi-function instruction capability is best illustrated by
the four special addressing modes register increment or
decrement with or without conditional skip, which work only
with the data movement instructions load and exchange.
The load instruction in general uses any of the five two-address modes or the two combination modes to transfer data
from one location to another.
The exchange instruction is similar except that the destination must always be the accumulator. Exchange not only
takes the source and puts the value into the destination but
also takes the value from destination and puts it into source.
Clearly there is no immediate addressing mode for exchange as a destination cannot be stored into an immediate
value.
When load and exchange are used with the X register as a
pointer and register indirect mode, a suffix + or - can be
added after the X. In this case, once the data movement
operation has been performed, the X register is incremented or decremented by one or two according to whether
DIVD
LOW.W,#l
10
LOOP:
o
Auto Increment/Decrement Instructions
As the result of divide double can only be a 16-bit value, a
full 32-bit divide is performed by following a 16-bit divide
with a 32-bit divide as shown below. The example below
shows how the divide instructions work together and also
highlights the combinations of addressing modes that can
and cannot be used with HPC.
LD
-'"
We now wish to store the remainder into one of our BCD
digit locations using register indirect mode. We need to load
the value into the accumulator from X. The X register is
nothing special in this application, so load A with word X is
in fact an example of direct addressing mode.
Now that our BCD value is in the accumulator, we can store
this in the byte location using B register indirect addressing
mode.
The next instruction is decrement skip on zero. This uses
direct addressing mode to decrement the B register. This
instruction is an example of many in HPC which perform
more than one function. As well as decrementing the memory location specified, this instruction also compares it with
zero after the decrement has been performed. If the result is
zero, the instruction following the decrement skip on zero
instruction is skipped. That is to say it is ignored and control
passes to the instruction following it. In this example the
final instruction of the routine is a single byte jump back to
the divide instruction. The overall loop is executed ten times
in order to perform the conversion. On the final pass
through the loop, B becomes zero and execution of this
algorithm is terminated.
The carry flag may be accessed using the standard bit test
instructions because it can be read in the processor status
word, but as carry must so often be set and tested, special
instructions to do this have been included which do not require the address of the carry flag.
DIV
z
c.n
o
LD A, X
ST A, [B]
DECSZ B
JP LOOP
5-127
•
o.....
It)
:Z
c:t
there has been a byte or a word access respectively. A
further refinement on this is provided by the load and exchange with conditional skip instructions, LOS and XS respectively. These only work with the B register as the pointer and perform two more operations rather similar to the
decrement skip on zero instruction. Once the increment or
decrement has been performed, the B register is compared
with the K register, otherwise known as the limit register. If
an increment has been performed and B is greater than K,
the instruction following the movement instruction will be
skipped. If a decrement is performed, the instruction is
skipped if B is less than K.
HPC ASSEMBLY CODE
The addressing modes usable for each opcode are described in a shorthand form.
Example:
ADD
LOOP:
X,#START
LD
LD
BK,#BEGlN,#END
A, [X+].W
XS
A, [B+].W
JS
LOOP
This routine moves a block of data from one location to
another. The X register is initialized first and is used as a
pointer to the first value to be moved in the source block.
The Band K registers point to the first and last values respectively in the destination block. The loop itself consists
of only three bytes. The first instruction loads the accumulator with the word pointed to by the X register and increments
X by two. A second instruction exchanges the accumulator
with the word pointed to by the B register, increments the B
register by two and compares it with K. If B is greater than K,
the jump instruction is skipped and this loop is terminated.
The example shows how HPC code can perform a great
deal with very few instructions and use up very few bytes of
code while doing so.
These auto increment/decrement instructions are the only
examples where an addressing mode cannot be used for
any instruction where it might make sense. It is however
fairly easy to remember which addressing modes these can
be used with. Auto increment/decrement can be used with
the load and exchange instructions for the X register. Auto
increment or decrement with conditional skip can be used
with load and exchange instructions using the B register as
a pointer. No other combinations are allowed.
We have not provided specific string move or search instructions but the auto increment/decrement operations
provide building blocks allowing the programmer to assemble his own stock. In the block move instruction shown
above, the value being moved is in the accumulator in between the load and exchange instructions. The programmer
can then compare this value with anything he wishes, fill
BCD to ASCII, pack BCD, unpack BCD or perform any operation he likes on a string of data.
<
MA
+
Meml
In the above syntax MA means directly addressed memory
or the accumulator and Meml means memory addressed
using any of the four basic single-address addressing
modes or an immediate value. This would be better written
as shown below:
An example of how these specialized instructions are used
is given by the block move routine shown below;
LD
MA
A
<
A + Meml
or
M
M + M
or
M
<
<
M
+
I
Expanding the syntax highlights that the flexible addressing
modes such as register indirect may only be used if the
destination is the accumulator. It also shows that if the destination is direct memory the source may only be an immediate value or another direct memory location.
When writing assembly code the programmer writes the
same mnemonic whether a memory location is a piece of
RAM or ROM or an I/O port or the accumulator. In general
any source or destination variable may be a byte or a word
and combinations are allowed. Care must be taken when
storing word into a byte location that the programmer really
wishes to truncate that value to byte and throwaway the
upper 8 bits of the value. When loading a byte into a word
location the upper 8 bits of the word location will be filled
with zeros. If memory external to the HPC is used, this may
be 8 or 16 bits wide. The programmer must be aware of this
when writing his assembly language as HPC cannot cope
with the programmer requesting a 16-bit access to 8-bit
wide external memory. The HPC will not convert this to two
sequential 8-bit accesses.
The only exception to this rule is that a pointer word in indirect or indexed addressing modes must always be in the
base page. This is because only one byte has been allowed
in the overall length of the instruction for the address of the
pointer.
For all other addressing modes there is no difference in the
assembly language the programmer writes between accessing a variable that is in the base page and a variable that is
above address OFF.
The programmer should be aware however that variables in
the base page consume less bytes per access and the instruction will execute more quickly than non-base page variables. When studying the data sheet to see how long an
instruction is, the programmer will see that the table result is
different according to whether variables are base page or
not. The programmer should therefore allocate base page
to variables which are used most often.
EXECUTION SPEED
There are 64 bytes of RAM above the base page. These,
like the base page RAM, require zero wait states to access
even when the processor is running at full speed. They do
however require 2 bytes of code for their addresses. These
5-128
.
:t64 bytes may best be made use of by using them as the
stack area as the 16-bit stack pointer contains the full address and therefore there is no penalty in instruction length
in putting the stack in this non-base page on-chip RAM.
Note that there is no difference in execution time between
byte and word accesses, that is to say accesses to byte or
word variables. When studying the data sheet, differences
in program length and therefore in execution time will be
observed according to whether the address of a directly addressed variable is a byte or a word. It is important to understand the difference between the width of the variable and
the width of the address that is used to access that variable.
The cycles per instruction table is not always clear about
the number of wait states applied to different variables. The
HPC includes a wait state register which sets the number of
wait states to be used when accessing external memory,
the internal ROM, or internal registers associated with ports
A and B. Wait states may be applied to these on-chip registers to allow compatibility with development tools such as
the MOLETM and HPC Designer Kit board, as when these
tools are run on high clock speeds wait states must be applied for accesses to the port recreation logic. The HPC
needs wait states for accessing slow external memory and
when running at high clock rates.
These wait states may be applied in order that the MOLE
can provide a perfect emulation of a single-chip HPC. In the
MOLE the HPC is running with external memory and thus
the A port and some of the B port are used for address/ data
and control lines respectively. The A port and part of the B
port must therefore be recreated external to the HPC. In the
case of the MOLE this is done using a large array of PAL®s.
Because they are external to the HPC, one wait state must
be applied when accessing these externally recreated ports
at high clock speeds. If wait states could not be applied to
these ports in a masked ROM HPC, the MOLE would not be
able to provide full speed emulation. This is just one example of how the design of the HPC has been influenced by
the need to emulate it 100% exactly at full speed. Apart
from this no wait states are applied to any access to address locations below 200 HEX, regardless of the addressing mode used.
The HPC data sheet does not make it clear how many wait
states are applied when register indirect addressing mode is
used. It implies that wait states are always applied when
register indirect or similar addressing modes are used, but
this is not the case.
Z
....o
U1
The best way to time a piece of code is to write the code
and then run it through the cross assembler to generate a
source plus object listing. The number of bytes generated
by each instruction can then be easily read and only the
cycles and accesses table need be looked up in order to
calculate how long each instruction takes to execute.
Note that accesses to internal ROM are subject to at least
one wait state for exactly the same reason as accesses to
the A or B ports.
SUMMARY
The HPC is fully memory mapped. The I/O Ports, Peripheral
Control Registers, RAM and ROM are treated exactly the
same. This makes the HPC easy to program. The HPC instruction set has relatively few opcodes but allows any of
these opcodes to be used with any addressing mode so as
to provide an Instruction Set with great power and flexibility.
Once the contents of this note have been understood, HPC
code can be written without referring to any document more
lengthy than the HPC Instruction Set description in the data
sheet.
•
5-129
Section 6
MICROWIRE and
MICROWIRE/PLUS
Peripherals
Section 6 Contents
MICROWIRE and MICROWIRE/PLUS Peripherals Selection Guide. . . . . . . . . . . . . . . . . . . . . . .
COP452L1COP352L Frequency Generator and Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP470/COP370 V.F. Display Driver.................................................
COP472-3 Liquid Crystal Display Controller. ................ .............. .......... ...
COP498/COP398 Low Power CMOS RAM and Timer (RATTM) COP499/COP399 Low Power
CMOS Memory ..................................................................
6-2
6-3
6-7
6-37
6-44
6-52
s:
o:II
~National
o
~ Semiconductor
=E
:D
m
D)
:::s
MICROWIRETM and MICROWIRE/PLUSTM:
3-Wire Serial Interface
Co
s:
o
:II
o
=E
The control register (CNTRl) is used to configure and control the mode and operation of the interface through userselectable bits that program the internal shift rate. This
greatly increases the flexibility of the interface.
National's MICROWIRE and MICROWIRE/PlUS provide
for high-speed, serial communications in a simple 3-wire implementation.
Originally designed to interface COP4DD microcontrollers to
peripheral devices, the MICROWIRE protocol has been extended to both the COP8DD and HPCTM families with the
enhanced version, MICROWIRE/PlUS.
MICROWIRE/PlUS can also provide additional I/O capability for COP8Da and HPC microcontrollers by connecting, for
example, external 8-bit parallel-to-serial shift registers to 8bit serial-to-parallel shift registers.
Because the shift clock in MICROWIRE/PlUS can be internal or external, the interface can be designated as either
bus master or slave, giving it the flexibility necessary for
distributed and multiprocessing applications.
:D
m
.......
"'C
r-
c:
en
And it can interface a wide variety of peripherals:
• Memory (CMOS RAM and EEPROM)
• AID converters
• Timers/counters
• Digital phase locked-loops
• Telecom peripherals
• Vacuum fluorescent display drivers
• lED display drivers
• LCD display drivers
Both MICROWIRE and MICROWIRE/PlUS give all the
members of National's microcontroller families the flexibility
and design-ease to implement a solution quickly, simply,
and cost-effectively.
With its simple 3-wire interface, MICROWIRE/PlUS can
connect a variety of nodes in a serial-communication network.
This simple 3-wire design also helps increase system reliability while reducing system size and development time.
MICROWIRE/PlUS consists of an 8-bit serial shift register
(SIO), serial data input (SI), serial data output (SO), and a
serial shift clock (SK).
Because the COP8DD and HPC families have memorymapped architectures, the contents of the SIO register can
be accessed through standard memory-addressing instructions.
MICROWIRE/PLUS System Block
/
/
,/
~
I/O
,/
CHIP SELECT LINES
/
8-BIT AID
CONVERTER
ADC08XX
HPC
(t.lASTER)
/
/
IJ
[)
...
SK
1t
1
./
LOW
POWER
Ct.lOS RAt.l
&: Tlt.lER
COP 498
EEPROt.l
Wt.lC93XXX
LINES
SI
,
1t
1
,
1
so
,
1/
ISDN lRANSCElVERS
TP3400
DASL
TP3410
EC
TP3420
SIO
VF
DISPLAY
DRIVER
COP 470
/
1t
./
1t
1
/
./
t
1
K=!
HPC
(SLAVE)
I/o
LINES
/
so
SK
SI
II
IIJ
TL/XX/0074-1
6-3
•
o
=»
~
Q.
.....
LLI
a:
io
r-----------------------------------------------------------------------------~
MICROWIRE/PLUS Block Diagram
SO
- ......
---
a:
o
8-BIT SIO
t.4SB LSB
REGISTER
SI
SHIFT CLOCK
t
>-
:i
"'C
C
A
LLI
"
as
a:
io
CKI/1S--'
a:
o
:i
T T
-i-2"
SK
I"
INTERNAL
A DATA BUS"
-........
~
)
v
CNTRL/
DIVBY
REGISTER
TL/XX/0074-2
6·4
:s:::
(=)
MICROWIRE and MICROWIRE/PLUS Peripherals
Part Number
I
Description
:xJ
I
Databook
o
:e
:Ii
AID CONVERTERS AND COMPARATORS
m
ADC0811
11 Channel 8·Bit AID Converter with Multiplexer
Linear
ADC0819
19 Channel 8·Bit AID Converter with Multiplexer
Linear
ADC0831
1 Channel 8·Bit AID Converter with Multiplexer
Linear
(=)
ADC0838
8 Channel 8·Bit AID Converter with Multiplexer
Linear
ADC0832
2 Channel 8·Bit AID Converter with Multiplexer
Linear
o
ADC0833
4 Channel8·Bit AID Converter with Multiplexer
Linear
:Ii
ADC0834
4 Channel 8·Bit AID Converter with Multiplexer
Linear
........
"U
ADC0852
Multiplexed Comparator with 8·Bit Reference Divider
Linear
c:
en
ADC0854
Multiplexed Comparator with 8·Bit Reference Divider
Linear
Microcontroller
Q)
::s
c.
:s:::
:xJ
:e
m
r-
DISPLAY DRIVERS
COP470
4 Digit by 8 Segment Expandable V.F. Display Driver
COP472·3
3 x 12 Multiplexed Expandable LCD Display Driver
Microcontroller
MM5450
35 Output LED Display Driver
Interface
MM5451
34 Output LED Display Driver
Interface
MM5483
31 Segment LCD Display Driver
Interface
MM5484
16 Segment LED Display Driver
Interface
MM5486
33 Output LED Display Driver
Interface
MM58201
8 Backplane and 24 Segment Multiplexed LCD Driver
Interface
MM58241
32 Output High Voltage Display Driver
Interface
MM58242
20 Output High Voltage Display Driver
Interface
MM58248
35 Output High Voltage Display Driver
Interface
MM58341
32 Output High Voltage Display Driver
Interface
MM58342
20 Output High Voltage Display Driver
Interface
MM58348
35 Output High Voltage Display Driver
Interface
MEMORY DEVICES
COP498
4 x 64 Low Power CMOS RAM and Timer with "Wake·Up"
Microcontroller
COP499
4 x 64 Low Power CMOS RAM
Microcontroller
NMC9306
16 x 16 NMOS EEPROM
Memory
NMC9313B
16 x 16 NMOS EEPROM
Memory
NMC9314B
64 x 16 NMOS EEPROM
Memory
NMC9346
64 x 16 NMOS EEPROM
Memory
NMC93C06
16 x 16 CMOS EEPROM
Memory
NMC93C26
32 x 16 CMOS EEPROM
Memory
NMC93C46
64 x 16 CMOS EEPROM
Memory
NMC93C506
16 x 16 CMOS EEPROM with Write Protect
Memory
NMC93C526
32 x 16 CMOS EEPROM with Write Protect
Memory
NMC93C546
64 x 16 CMOS EEPROM with Write Protect
Memory
NMC93C556
128 x 16 CMOS EEPROM with Write Protect
Memory
NMC93C56
128 x 16 CMOS EEPROM
Memory
NMC93C566
256 x 16 CMOS EEPROM with Write Protect
Memory
NMC93C66
256 x 16 CMOS EEPROM
Memory
6·5
[II
I
en
::)
..J
a..
.......
MICROWIRE and MICROWIRE/PLUS Peripherals (Continued)
w
Part Number
io
TELECOM DEVICES
IX:
IX:
o
:i
"'C
C
CO
W
I
Description
I
Databook
TP3400
Digital Adapter for Subscriber Loops (DASL)
Telecom
TP3410
Echo Canceller (EC)
Telecom
TP3420
S Interface Device (SID)
Telecom
AUDIO AND RADIO DEVICES
DS8906
AM/FM Digital PLL Synthesizer
Interface
DS8907
AM/FM Digital PLL Frequency Synthesizer
Interface
IX:
DS8908
AM/FM Digital PLL Frequency Synthesizer
Interface
:i
DS8911
AM/FM/TV Sound Up-Conversion Frequency Synthesizer
Interface
IX:
i
o
o
LMC1992
Stereo Volume/Tone/Fade with Source Select
Linear
LMC1993
Stereo Volume/Tone/Fade/Loudness with Source Select
Linear
LMC835
7 Band Graphic Equalizer
Linear
Frequency Generator and Counter
Microcontroller
SPECIAL FUNCTIONS
COP452L
6-6
o
o"'0
~National
~
U1
~ Semiconductor
N
r......
o
COP452L/COP352L Frequency Generator and Counter
o"'0
w
U1
N
r-
General Description
Features
The COP452L and COP352L are peripheral members of the
COPSTM family fabricated using N-channel silicon gate
MOS technology. Containing two independent 16-bit counter/register pairs, they are well suited to a wide variety of
tasks involving the measurement and/or generation of
times and/or frequencies. Included in the features are multiple tone generation, precise duty cycle generation, event
counting, waveform measurement, frequency bursts, delays, and "white noise" generation. An on-chip zero crossing detector can trigger a pulse with a programmed delay
and duration. The COP352L is the extended temperature
version of the COP452L. The COP352L is the functional
equivalent of the COP452L.
• Unburdens microcontroller by performing "mundane"
tasks
• Wider range and greater accuracy than microcontroller
alone
• Generates frequencies, frequency bursts, and complex
waveforms
.
•
•
•
•
•
•
•
•
The COP452L series peripheral devices can perform numerous functions that a microcontroller alone cannot perform. They can execute one or more complex tasks, attaining higher accuracies over a broader frequency range than
a microcontroller alone. These devices remove repetitive
yet demanding counting, timing, and frequency related functions from the microcontroller, thereby freeing it to perform
other tasks or allowing the use of a simpler microcontroller
in the system.
Measures waveform duty cycle
Two independent pulse/event counters
True zero crossing detector triggers output pulse
White noise generator
Compatible with all COP400 microcontrollers
MICROWIRETM compatible serial I/O
14-pin package
Single supply operation
(4.5V-6.3V, COP452L; 4.5V-5.5V, COP352L)
• Low cost
• TTL compatible
Block Diagram
CKI
SK
CKO
11
DI
OA
ZI
INB+t---r~
DB
_10
CS~----------------------------------------~
VCC
GND
FIGURE 1
6-7
TL/DD/6155-1
.J
C'I
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C")
Q.
oo
:::l
C'I
II)
~
Q.
oo
r---------------------------------------------------------------------------------------,
COP452L
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage at Any Pin (except ZI)
relative to GND
Voltage at Pin ZI relative to GND
Sink Current, Output OA
Ambient Storage Temperature
Power Dissipation
15mA
35 rnA
5mA
1 rnA
300°C
0.5W at 25°C
0.2Wat70°C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
5mA
Source Current, All Other Outputs
O°Cto 70°C
- 65°C to + 150°C
Lead Temperature (Soldering, 10 sec.)
-O.Sto +10V
Source Current, Outputs OA, OS
10mA
Ambient Operating Temperature
-0.5Vto +7.0V
Sink Current, All Other Outputs
Total Sink Current
Total Source Current
DC Electrical Characteristics o°c ~ TA + 70°C, 4.5V ~ Vee ~ 6.3V (COP452L), unless otherwise specified
Parameter
Conditions
Operating Voltage (Vee>
Operating Supply Current
Input Voltage Levels
CKllnput Levels
Logic High (VIH)
Logic Low (VIU
DI, INS, ENS, SK, OS
Logic High
Logic High (VIH)
Logic Low (VIU
Zllnput Voltage
Max
Units
4.5
6.3
V
14
rnA
0.4
V
V
V
O.S
+10
V
V
V
V
All Outputs Open
Vee = Max.
Vee = 5.0V ±5%
Vee = Max.
Vee = 5.0V ± 5%
3.0
2.0
3.0
2.0
-O.S
-1.6
7.S
kO
150
mV
0.4
V
V
(Note 2)
(Note 2)
(Note 3)
15
5.0
35
rnA
rnA
rnA
(Note 2)
(Note 2)
(Note 3)
-5.0
-1.0
-10
rnA
rnA
rnA
Impedance to GND at ZI
ZI Offset Voltage
(Note 1)
Output Voltage Levels
TIL Operation
Logic High (VOH)
Logic Low (VOU
Vee = 5.0V ±5%
IOH = 100 p,A
IOL = -1.6 rnA
Maximum Allowable Output
Current Levels
Sink Current
OA
All Other Outputs
Total Sink Current '
Source Current
OA,OS
All Other Outputs
Total Source Current
Min
2.4
Note 1: ZI offset voltage is the absolute value of the difference between the voltage at ZI and ground (pin 9) that will cause the zero detect circuit output to change
state. This is the maximum value which takes into account the worst case effects of process, temperature, voltage, and gain variation.
Note 2: The maximum current for the specified pin must be limited to this value or less.
Note 3: The total current in the device must be limited to this value or less.
6-S
o
COP452L
AC Electrical Characteristics o·c : ; TA ::;;
Parameter
CKllnput Frequency (fiN)
Duty Cycle
+1
o
-a
01:100
U1
N
70·C, 4.5V ::;; Vee::;; 6.3V unless otherwise specified
Conditions
+4Mode
+ 1 Mode
+4
+1
Min
Max
Units
100
64
2100
525
kHz
kHz
55
55
%
%
30
45
Rise Time (tr)
fiN = 2.1 MHz
50
ns
Fall Time (t,)
fiN = 2.1 MHz
40
ns
kHz
SK Input Frequency
25
250
SK Duty Cycle
30
70
%
Internal Clock Frequency (tl)
25
525
kHz
Internal Count Rate
0
fl/2
Hz
fl/131072
fl/2
Hz
Output Frequency
Inputs
DI
Outputs
CKO
ZO
DO
OA
08
tpd1
tpdO
tpd1
tpdO
tpd1
tpdO
tpd1
ns
IJ-s
800
1.0
tSETUP
tHOLD
CL = 50 pF
ZI = Sine Wave (A'gure 4)
CL = 50 pF
CL = 50 pF
VOUT = 1.5V
tpDO
tpd1
tpdO
6-9
0.2
0.2
0.7
0.6
1.0
0.6
0.7
IJ-s
IJ-s
IJ-s
IJ-s
IJ-s
IJ-s
IJ-s
0.8
1.0
0.4
IJ-s
IJ-s
IJ-s
ro
"-
o-a
w
U1
N
r-
..J
N
&I)
C")
a..
o
o
.......
..J
N
&I)
~
a..
o
o
COP352L
Absolute Maximum Ratings
If MIlitary/Aerospace specified devices are required,
contact the National Semiconductor Sales Office!
Distributors for availability and specifications.
Voltage at Any Pin (except ZI)
relative to GND
-0.5V to + 7.0V
Voltage at Pin ZI relative to GND
-0.8V to + 10V
Sink Current, Output OA
Ambient Storage Temperature
Lead Temperature (Soldering, 10 sec.)
Power Dissipation
35mA
Source Current, Outputs OA, OB
5mA
1 mA
Source Current, All Other Outputs
DC Electrical Characteristics
-40°C
~
TA
~
85°C, 4.5V
Conditions
Operating Voltage (Vee>
Operating Supply Current
Input Voltage Levels
CKllnput Levels
Logic High (VIH)
Logic Low (VIL>
DI, INB, ENB, SK, CS
Logic High
Logic High (VIH)
Logic Low (VIL>
Zllnput Voltage
Vee
Vee
= Max.
= 5.0V ±5%
= Max.
= 5.0V ±5%
Vee
- 65°C to + 150°C
300°C
0.5W at 25°C
0.125W at 85°C
Impedance to GND at ZI
~
5.5V unless otherwise specified
Min
Max
4.5
5.5
V
16
mA
0.3
V
V
V
3.0
2.2
1.6
Units
V
3.0
2.2
-0.8
V
0.6
+10
V
V
7.8
kO
150
mV
0.4
V
(Note 2)
(Note 2)
(Note 3)
15
5.0
35
mA
mA
mA
(Note 2)
(Note 2)
(Note 3)
-5.0
-1.0
-10
mA
mA
mA
ZI Offset Voltage
(Note 1)
Output Voltage Levels
TIL Operation
Logic High (VOH)
Logic Low (VoL>
Vee = 5.0V ±5%
IOH = 100 p.A
IOL = -1.6mA
Maximum Allowable Output
Current Levels
Sink Current
OA
All Other Outputs
Total Sink Current
Source Current
OA,OB
All Other Outputs
Total Source Current
~
All Outputs Open
Vee
Vee
-40°C to +85°C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
5mA
Total Sink Current
10mA
Ambient Operating Temperature
15mA
Sink Current, All Other Outputs
Parameter
Total Source Current
V
2.4
Note 1: ZI offset voltage is the absolute value of the difference between the voltage at ZI and ground (pin 9) that will cause the zero detect circuit output to change
state. This is the maximum value which takes into account the worst case effects of process, temperature, voltage, and gain variation.
Note 2: The maximum current for the specified pin must be limited to this value or less.
Note 3: The total current in the device must be limited to this value or less.
6-10
COP352L
AC Electrical Characteristics
Parameter
o
o
"tJ
-40°C
~
~ TA ~ + 85°C, 4.5V ~ Vee ~ 5.5V unless otherwise specified
Conditions
U1
N
Min
Max
Units
CKllnput Frequency (fiN)
-:-4 Mode
-:-1 Mode
256
64
2100
525
kHz
kHz
Duty Cycle
-:-4
-:-1
35
50
55
55
%
%
Rise Time (tr)
fiN = 2.1 MHz
50
ns
Fall Time (tl)
fiN = 2.1 MHz
40
ns
SK Input Frequency
25
250
kHz
SK Duty Cycle
30
70
%
Internal Clock Frequency (fl)
64
525
kHz
Internal Count Rate
0
fl/2
Hz
fl/131072
fl/2
Hz
Output Frequency
Inputs
DI
Outputs
CKO
ZO
DO
OA
OB
800
1.0
tSETUP
tHOLD
o
o
"tJ
(,.)
U1
N
r-
ns
J-Ls
CL = 50 pF
tpd1
tpdO
tpd1
tpdO
tpd1
tpdO
tpd1
r......
ZI = sine wave (Figure 4)
CL = 50 pF
CL = 50 pF
VOUT = 1.5V
tpdO
tpd1
tpdO
0.25
0.25
0.8
0.7
1.1
0.7
0.7
J-Ls
J-Ls
J-Ls
J-Ls
J-Ls
J-Ls
J-Ls
0.8
1.0
0.4
J-Ls
J-Ls
J-LS
Timing Diagrams
CKI
_~SLJLJL
CKO
tpdO_
~-OllJIllIf
CKI
FOR DUTY CYCLE.
TRIGGERED PULSE
AND TRIGGERED
PULSE AN DCOUNT
FOR OTHER MODES
_lpd1
OA
J""UUl.IUUL
- ~Ipd1-
OA.OB
IPd1-1-
TL/DD/6155-2
FIGURE 2a. CKO Output Timing
I
-I-
-
FIGURE 2b. OA and OB Output Timing
6-11
IpdO
-lpdO
TLlDD/6155-3
•
-I
N
1.1)
Cf)
Timing Diagrams (Continued)
D..
oo
SK~
......
-I
N
1.1)
I
tSETUP
"1::1'
D..
o
01
o
-
tHOLD
I
\II
X
J\
-
Ipd1r-
tpdO
DO _ _ _ _ _ _--L/../tVOH
TL/DD/6155-4
FIGURE 3a. Synchronous Data Timing
CS
SK
DI
M=1 FOR MODE
=0 FOR INSTRUCTION
TL/DD/6155-5
FIGURE 3b. Instruction Timing (Except Read/Write)
~~~--------------------------------~~
J1l1J1-~
SK
DI
~_ _ _ _ _ _ _~~_~~~~1~~'~~
.1
1 - - - - 1 6 DATA BITS
TL/DD/6155-6
FIGURE 3c. Write Instruction Timing
~~~
__________________________
~r---
JlSL
SK
DI
I TRI-
~
~_ _~~~~~~~~~~_ _~~~/~_J~~
A/B=1 - READ REGISTER A
=0 - READ REGISTER B
16 DATA BITS--l
TLlDD/6155-7
FIGURE 3d. Read Instruction Timing
6-12
o
Timing Diagrams
o
(Continued)
"'C
~
U1
N
r-
"'-
o
o
ZI VOFFSET -----;r----------3\[---------~-OV --~r_------------~--------------_r+_-----
"'C
w
U1
N
rZO
TLlDD/6155-8
FIGURE 4a. ZO Timing, VOFFSET > OV
ZI
OV ------+--------------~----------+-----VOFFSET ---,f'------------'\[------~'-----
ZO
TLlDD/6155-9
FIGURE 4b. ZO Timing, VOFFSET
< OV
Pin Descriptions
Pin
Description
Pin
Description
ZO
OA
INB
ENB
OB
Zero Cross Output Signal
Counter A, Logic Controlled Output
Counter B, External Input
Enable for INB
Counter B Output
Power Supply
Crystal Oscillator Output
CKI
GND
CS
SK
Crystal Oscillator Input
Ground
Chip Select
Serial Data 1/0 Clock Input
Serial Data Input
Serial Data Output
AC Waveform Input, Counter A External Input
Vee
CKO
01
DO
ZI
Connection Diagram
Dual-In-Line Package
ZO
ZI
OA
00
INB
ENB
01
eOP452L
eOP352L
SK
OB
cs
vee
GNO
CKO
CKI
TL/DD/6155-10
FIGURE 5. Pin Connection Diagram
Order Number COP452D, COP352D, COP452N or COP352N
See NS Package Number 0140 or N14A
6·13
...I
N
II)
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a..
Typical Performance Characteristics
o
(.)
DO Source Current
......
1M IN
IMAX IMAX
1.75 r--@VCC- @VCC-@VCC=4.5V =6.3V
=6.3h
1.5
...I
N
II)
"'=t'
a..
o
(.)
10
-
8
ec
§.
§
0.75
IMIN
0.5 r-@VCC
=4.5V
I
I
~\
3
1
4 5
VOH(V)
6
7
o
o
8
I
:-
C
1.5
~
1.25
~
1
2
IMAX
/MAX@VCC=6.3V
J
\
0.25
o
8 9 10
~
"o
1
@Vc·c=4.SV, ,
...
\
\
\
0.5
"
'I'-..
3 4 5 6 7
bt
V
\
\
0.75
\
....... r---.,.
1
,
1.75
1\ \\
1
\
I
r-I~IN I@ JCC!6.3~+
IMIN
2.25 -@Vcc
2 j4.5V
1~IN~VJC=~.3J
1/ / IMAX@VCC=4.5V_
1/ k" ~MAJ
1/ V V @VCC
\ =6.3V 1\
~
\1\ \ \
\
\
\
o
o
/
\\
0.25
2.5
IMIN@VCC=4.5V
9
~
\
_ 1.25
ZO Source Current
OA, OB Source Current
2
2
\
~
3 4 5
VOH(V)
6
7
8
9 10
VOH(V)
TLlDD/6155-11
OA Sink Current
DO, ZO, OB Sink Current
16
5mr~--~--~~~---,
, ~I
14
12
C
§.
_10
ec
§.
0
0
....
IMAX@VCC=6.3V
, , , ',IIMAX VC1C =4.5V
1I
F
I
I
I/y.
""""
V
....
IMIN@VCc='6.3V
~IMIN i vcr
=4'r
V
,
OL-~--~--~--~--~
o
0.2
0.4
0.6
0.8
o
1.0
012345678
VOL (V)
VOL (V)
TL/DD/6155-12
TLlDD/6155-13
FIGURE 6. COP452L
IrAX @ VCc-4.5V
1.5
1.25
c
\
IMIN
@VCC
2
8~~~-r~~--r-~,
IM~X
- I - - -@VCC
1.5
-s.sv
~
o
o
~ 0.75
IMIN\
!4~~~ \
0.5
1\
I;'IIN
@VCC
-5.5V
0.25
t,.\
3
OL-L-~*="~~~~
02345678
4
o
=5.5V
\
\
\ 1\
~ \ \
"~
~~
012345678
VOH(V)
VOH(V)
/
\ I
\ \\
~
0.5 -
IMAX
-- ~@VCC r- -
1\
_ 1.25
0.75
'IMIN
@VCC
0.25 -=(5V
IMAX
-!4~~~\
1.15
-
=sr
§.
§
,
ZO Source Current
OA, OB Source Current
DO Source Current
1.75
VOH(V)
TL/DD/6155-14
OA Sink Current
DO, ZO, OB Sink Current
5~~--~--~~-r~~
16~~~-T-'--r-~~-'
14~+-~-+-4~~+-~~
12 H--I--...f7oC::';""
_ 10 tl-t-f-+--F
c
....
o
!8t1--tl--2""::....r-4--t---t-~-I
§.
OL-~~~~~--~~~
0.2
0.4
0.6
0.8
1.0
01234567
VOL (V)
VOL (V)
TL/DD/6155-16
TLlDD/6155-15
FIGURE 7. COP352L
6·14
o
o'"C
Functional Description
The COP452L and COP352L are functionally identical devices. They differ only in Vee range andlor operating temperature range, and certain electrical parameters associated with those temperature and voltage ranges. The following information will refer only to the COP452L. All the information, however, applies equally to the COP452L and
COP352L.
and the process continues. A similar procedure is used in
the duty cycle mode and number of pulses modes. For
counting, the counters count the pulses at their respective
inputs. There is no automatic counter-register transfer in the
count modes. The counters wraparound from 0 to FFFF in
the count modes. Data 1/0 is via the serial port and the
registers. The counters are not involved in the input/output
process at all.
INSTRUCTION SET AND OPERATING MODES
The device requires a low chip select signal. When the device is selected (CS low) the driver on the DO pin is enabled
and the device will accept data at 01 on each SK pulse.
When the device is deselected (CS high) the DO driver is
TRI-STATE® and the I register is reset to O. Note that chip
select does not affect any other portion of the device. The
mode latches are not affected. The COP452L will continue
to operate in the mode specified by the user until the mode
is changed by the user.
The COP452L contains a clock generator. The user may
connect a crYstal network to CKI and CKO or he may drive
CKI from an external oscillator. Certain RC and LC networks
may also be used. See the applications for further information.
The COP452L has ten instructions and eleven operating
modes as indicated in Figure S. The information for the instruction or mode is sent to the COP452L via the serial interface. The MSB is always a "1" and is properly viewed as
a start bit. The second MSB identifies the communication as
an instruction or a mode. The lower four bits contain the
command for the device.
Instruction
LORB
LORA
RORB
RORA
TRCB
TRCA
TCRB
TCRA
CK1
CK4
LOM
Opcode
MSB LSB
Comments
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
11xxxx
Load register B from 01
Load register A from 01
Read register B to DO
Read register A to DO
Transfer register B to counter B
Transfer register A to counter A
Transfer counter B to register B
Transfer counter A to register A
CKI divide by one
CKI divide by four
Load mode latches
The user also has control over whether the clock generator
divides the CKI signal by 4 or 1. This allows the user to
quickly get a 4 to 1 change in frequency output or input
count rates. Alternatively, it allows the user to use a higher
speed crystal or clock generator. The internal clock frequency (the frequency after the divider) must remain between the specified limits to guarantee proper operation.
The state of the divider is not affected by CS.
There is an internal power-on reset circuit which places the
device in the Reset mode (mode latches all set to 1) and
sets the clock divider to divide by four. If the CKI frequency
is less than four times the minimum internal frequency the
first access of the COP452L must be the command to set
the divider to divide by 1. This command will be accepted
and will be processed. Proper operation of the COP452L is
not guaranteed if the internal frequency is less than the
specified minimum. The power-on reset circuit does not affect the counter and registers of the COP452L.
FIGURE 8a. COP452L Instruction Set
Operating Mode
Opcode
MSB LSB
Reset
Dual Frequency
Frequency and Count
Dual Count
Number of Pulses
Duty Cycle
Waveform Measurement
Triggered Pulse
Triggered Pulse and Count
White Noise and Frequency
Gated White Noise
111111
110000
110100
110101
110010
110011
110110
110001
110111
111000
111001
When the COP452L is subjected to rapid power supply cycling, the internal power on reset will not function. Power
must be removed for at least 20 seconds to allow restoration of internal reset circuitry. If the application requires
power on-off cycles more frequently than once each 20 seconds the software reset with proper CKI divide by must be
used to establish the initial state of the COP452L.
INSTRUCTION DESCRIPTION
1. Load Register (LDRAlLDRB)-The selected register
(AlB) is loaded with 16 bits of data shifted in on 01 and
clocked in by SK.
FIGURE 8b. COP452L Operating Modes
A block diagram of the COP452L is given in Figure 1. Positive logic is used. TheCOP452L can execute ten instructions as indicated in Figure Sa, and has eleven operating
modes. The operating mode is under user software control.
2. Read Register (RDRA/RDRB)-The data in the selected register (AlB) is shifted out serially onto ~O. At the
same time the data is recirculated back to the register.
The device basically consists of two sixteen bit shift registers and two sixteen bit binary down counters organized as
two register-counter pairs. In most operating modes, the two
register-counter pairs are completely independent of one
another. For frequency generation, both the register and
counter of a given pair are utilized. The counter counts
down to zero where a toggle flip-flop is toggled. Then the
data in the register is loaded, automatically, to the counter
3. Load Counter (TRCAlTRCB)-The contents of the selected register are transferred to its associated counter.
(Counter A is loaded from register A; counter B is loaded
from register B.) The contents of the register are unaffected.
4. Copy Counter (TCRAlTCRB)-The contents of the selected counter are transferred to its associated register.
(Counter A loads register A; counter B loads register B.)
The contents of the counter are unaffected.
6-15
0I:loo
U1
.......
o
N
o
'"C
W
U1
.N
...I
'"
it)
C')
D.
oo
.......
...I
'"
it)
~
D.
oo
Functional Description (Continued)
5. CKI Divide by One-The oscillator divider at the CKI input is set to divide by one. The internal frequency is therefore equal to the CKI frequency. This instruction should
not be used if the CKI frequency is greater than the maximum internal frequency.
6. CKI Divide by Four-The oscillator divider at the CKI
input is set to divide by four. The internal frequency is
therefore equal to one-fourth of the CKI frequency. This
instruction should not be used if the CKI frequency is less
than four times the minimum internal frequency.
7. Load Mode Latches-The four mode latches are loaded
with the lower four bits of the instruction.
DA
TL/DD/6155-18
tA= (A
Where:
DB J = I B
o~
Maximum count rate at IN8 = fl/2
Where:
o~
Where:
~
A
= CKllnput frequency +4 (+4 mode)
Minimum pulse width required for reliable counting = t
where t = period of internal clock.
4. Dual Count-In this mode counter A and counter Bare
enabled as external event or pulse counters. Counter A
counts pulses at ZI and counter B counts pulses at INB
(when ENB = 1). There is no automatic clear of either
counter. Each counter counts down from whatever state
it starts in. Thus, to ease reading the information, the
counters should be preloaded. Preloading the counters
with all zeroes will give the two's complement of the
count. Preloading the counters with all ones will give the
one's complement of the count. The circuitry which decrements the counters is enabled by the high to low transition at the count input. There is no interaction between
the two register counter pairs.
OA toggles every time counter A counts through "0".
OB toggles every time counter B counts through "0".
The counters, when counting, count down and wrap around
from 0 to FFFF and continue counting down.
Maximum count rate = fl/2
where: fl = internal clock frequency
Minimum pulse width = t
where: t = period of internal clock
(as previously defined).
There is no requirement that the count signal be symmetrical. The pulse width low must be at least equal to t. The
pulse width high must also be at least equal to t.
5. Number of Pulses Mode-This mode outputs at OA a
specified number of pulses of a specified width. The number of pulses is specified by the contents of register B.
The pulse width is specified by the contents of register A.
L
1)t
1)t
65535; 0
~
8
~
65535
A = Contents of register A
8 = Contents of register 8
t = Period of Internal clock
= Period of CKI oscillator (+ mode)
= 4
x
fl = Internal Clock frequency
= CKI Input frequency (+ 1 mode)
TL/DD/6155-17
+
+
tA = (A
te = (8
A ~ 65535 (0 ~ A ~ FFFF16)
08 toggles each lime counter 8 counts through zero.
IB~
.,.
A = Contents of register A
I = Period of Internal clock
(as previously defined)
MODE DESCRIPTION
1. Reset Mode-This mode sets OA and OB to "0". The
mode latches are all set to "1". No counting occurs; the
COP452L is in an idle condition. The registers and counters are not altered in any way.
2. Dual Frequency-Two frequencies are generated-one
at output OA and one at output OB. The period of the
square wave at OA is determined by the contents of register A. The period of the square wave at OB is determined by the contents of register B. In frequency generation modes, the counters count down until they reach
zero. At that point the output toggles and the counters
are automatically loaded from the respective registers.
The counters are only loaded when they count down to
zero. Therefore it may be necessary to initially load the
counters. The frequency outputs at OA and OB are completely independent of one another. The respective counter inputs (INB, ZI) have no effect on the counters in this
mode.
DA j = t A + t A - j
+ l)t
period of CKI oscillator (+ 4 mode)
Period of output square wave = 2(N
+ 1)t
DA
Where t Is devined above
N = Contents of register
o~
N ~ 65535 (0 ~ N ~ FFFF16)
TL/DD/6155-19
3. Frequency and Count-A single frequency is output at
OA. Counter B counts external pulses on INB (when ENB
= 1). There is no automatic clear of the counter. Since
counter B counts down from whatever state it is in it is
usually desirable to preload the counter. Preloading the
counter with all zeroes will give the two's complement of
the count. Pre loading the counter with all ones will give
the one's complement of the count.
tA = (A+ 1)t
N=B+1
Where:
A
=
Contents of register A
8 = Contents of register 8
t = period of Internal clock
(as previously defined)
1 ~ A ~ 65535, A*"O (1 ~ A ~ FFFF16)
o~ 8
6·16
~ 65535
(0 ~ 8 ~ FFFF16)
C')
Functional Description
o."
(Continued)
OB toggles each time a pulse train is generated at OA. The
pulse is generated each time the COP452L is selected and
an instruction is set to the device. Counter B is automatically
loaded from register B after the N pulses are generated.
Counter A is automatically loaded from register A at each
transition of OA. Therefore simply reloading the number of
pulses mode will repeat the previous sequence.
8. Triggered Pulse Mode-This mode outputs a pulse triggered by the zero crossing of a signal at 21. The delay
from the zero crossing is specified by the contents of
register A. The pulse width is specified by the contents of
register B. Input INB is ignored. See applications section
for further information.
Zl~------------~~--------------~----
OA
DB ~_IA+B-I-1A+8_1-1A+B=L
TL/DD/6155-20
lA = At
TL/DD/6155-22
tA = (A
ts = 8t
+
+
1.5)t
ts = 8t
8)t
tA + S = (A
A = Contents of register A
8 = Contents of register 8
Where:
1 = period of internal clock
(as previously defined)
+ 8 + 1.5)t
A = Contents of register A
8 = Contents of register 8
1
~
A
~
65535, A*"O (1
~
A
~
FFFF16)
t = period of internal clock
(as previously defined)
1
~
8
~
65535,8 *" 0 (1
~
8
~
FFFF16)
o
~
A
~
65535
(0
~
A
1
~
8
~
65535,8 *" 0 (1
~
8
7. Waveform Measurement Mode-This mode measures
the high and low times of an external waveform at INB
(with ENB = 1). Counter A counts the pulse width high
and counter B counts the pulse width low. On the high to
low transition counter A is transferred to register A and
then cleared. On the low to high transition counter B is
transferred to register B and then cleared. The counters,
therefore, count down from zero. Therefore the value
read from the registers is a two's complement value. The
transfer from the counter to register is inhibited during a
read instruction.
Zl~------------~~--------------+--
Q=L
.,
DA
TL/DD/6155-23
tA = (A
Where:
TL/DD/6155-21
Where:
65535t
~
tA
~
1
65535t
~
ts
~
t
FFFF16)
FFFF16)
Independently of the zero detection, counter B counts
external events at INS (when ENS = 1). The conditions
on the counter as described previously apply here.
The minimum pulse width, either high or low, that can be
measured, is the period of the internal frequency. The maximum pulse width that can be measured is the maximum
count (65535) multiplied by the period of the internal frequency.
q
s:
s:
9. Triggered Pulse and Count Mode-This mode outputs
a pulse at OA triggered by the zero crossing of a signal at
21. The contents of register A specify the delay from the
zero crossing. The pulse remains high until the next zero
crossing of the signal at 21.
The outputs OA and OB toggle each time the respective
counter counts through zero.
I" j=IA ,.
C')
o
."
W
U1
N
OA
tA + s = (A
N
r.......
r-
S. Duty Cycle Mode-This mode generates a rectangular
waveform at OA. The pulse width high is specified by the
contents of register A. The pulse width low is specified by
the contents of register B. A combination square wave
signal is generated at OB.
Where:
~
U1
+ 1.5)t
A = Contents of register A
t = period of internal clock
(as previously defined)
o
1 = period of internal clock
~
A
~
65535
(0
~
A
~
FFFF16)
08 toggles each time counter B counts through 0
6-17
....I
N
Lt)
M
Q.
oo
Functional Description
(Continued)
information in the I register. See the software interface section for further explanation on this point. CS does not affect
the mode latches.
10. White Noise and Frequency Mode-Register A is converted to a 17-stage shift register generator for the generation of pseudo-random noise at output OA. 08 outputs a square wave whose period is specified by the
contents of register 8. The shift register generator is
shifted at the internal frequency (= CKI frequency or %
CKI frequency depending on the oscillator divider). See
the applications section for more information on the
white noise generator.
.......
....I
N
Lt)
'I:t
Q.
oo
In those modes where there is an automatic transfer from
the register to the counter (frequency generation, duty cycle, number of pulses, triggered pulse), care must be exercised when reading or writing the register. To insure proper,
"glitch-free" operation, one of the two procedures below
must be followed:
1. Place the COP452L in the RESET mode.
oA
2. Read or write the appropriate register.
3. Place the COP452L back in the original mode.
Alternatively:
1. Read or write the appropriate register.
DB
2. Send the instruction to copy the appropriate register to its
counter.
WARNING: Failure to observe one or the other of these
procedures can cause some faulty output conditions.
Tl/DD/6155-24
ts
Where:
B
t
= (B + l)t
= Contents of register B
= period of internal clock
The COP452L powers up in the RESET mode and with oscillator divide by 4. If the CKI input frequency is less than 4
times the minimum internal clock frequency the user must
set the oscillator divider to divide by 1 before attempting any
operation with the COP452L. The instruction setting the oscillator divider will be accepted regardless of the value of
the internal clock frequency.
(as previously defined)
o ~ B ~ 65535
(0
~
8
~
FFFFI6)
11. Gated White Noise Mode-This mode generates pseudo-random noise AN Oed with a square wave. OA outputs this combined signal. 08 outputs a square wave
frequency. Register A is converted into a 17-stage shift
register generator which is shifted at the internal frequency rate. Counter A is not used. Counter 8 and register 8 are used in the frequency generation. See the applications section for further information on the white
noise generation.
Caution: Failure to observe this requirement will result in
the improper operation of the COP452L.
Applications Information
ZERO CROSS
The ZI input normally requires a resistor and diode external
to the device as indicated in Figure 9a. The resistor is part of
a voltage divider used to ensure that the voltage at pin ZI
does not exceed 10V peak and to protect the diode which is
required to clamp the negative voltage swing at the input to
less than -O.8V. Figure 9b is the recommended input circuit if logic level pulses are input to ZI for counting.
oA
DB
As indicated above, the input voltage at ZI must not exceed
10V peak. For inputs less than 10V peak, the resistor in
Figure 9a is required only to protect the diode. Otherwise,
the resistor should be selected to guarantee that the voltage at pin ZI does not exceed 10V peak. Figure 10 shows
this resistor (Rs) and the impedance (RIN) which forms the
first part of the input circuit at ZI. The absolute value of RIN
can vary widely. with process variation. The user should
compute the divider with Rs and the worst case maximum
of RIN so that the voltage at pin ZI is 10V or less. The
following relationship should be used when the input voltage
is greater than 10V peak:
Tl/DD/6155-25
ts
Where:
8
I
= (8 + 1)1
= Contents of register 8
= period of internal clock
(as previously defined)
o ~ 8 ~ 65535
(0 ~ 8 ~ FFFFI6)
GENERAL NOTES
The master timing reference in the COP452L is the internal
frequency. This is the CKI frequency after it has passed
through the divider. This frequency must remain within its
specified limits. The maximum count rate at either input is
this frequency divided by 2. The minimum pulse width that
can be measured is the period of this frequency.
RIN(MAX.)
x VIN ::;; 1OV peak
Rs + RIN(MAX.)
Substituting the maximum value for RIN and solving for Rs
gives:
CS, other than removing DO from the TRI-STATE condition
and allowing data to come into the I register via 01, does not
affect the operation of the device. CS must go high between
accesses in order to clear the I register. Since the I register
is cleared when CS goes high, the user must insure that CS
does not go high before the COP452L has accepted the
Rs ::;;
VIN
10
x 7.8k -
7.8k
where: VIN = peak input voltage.
Note that this equation is not valid for VIN less than 10V. In
this case, the value of Rs is chosen primarily for protection
of the diode and not to divide the voltage down to acceptable values.
6-18
(")
Applications Information
o"C
(Continued)
ZERO CROSS OFFSET
obtained when VOFFSET is at its maximum of 150 mV and
RIN is at its minimum of 2.6 kO. The minimum value of IX11
is obtained if VOFFSET is O. Using this information, the following range of IX11 is obtained:
As the electrical characteristics indicate, the ZI input has a
worst case offset of 150 mV in the zero crossing detection.
Therefore, the output of the zero cross detection circuit will
change state within ± 150 mV of zero volts. There are no
directional characteristics to this, i.e., approaching zero from
the positive or negative direction has no effect on where the
output of the zero cross detection circuit will change state
(see Figure 4). The offset further indicates that the voltage
at pin ZI must exceed 150 mV peak in order to guarantee
that the zero crossings will be detected and the appropriate
signals generated.
1
.
Rs + 2.6k
0::;: IX1 I ::;: 21Tf arcsin 0.15 VIN x 2.6k
~
U1
I\)
r-
........
(")
o"C
W
U1
I\)
Parameter X2 is the propagation delay through the zero
crossing detection circuit and its range is given by:
r-
0.3 ",.S ::;: X2 ::;: 0.6 ",.S
Parameter X3 is the internal synchronization delay and is
dependent upon when the zero crossing occurs relative to
the internal timing which reads the output of the zero crossing detection circuit. The range for X3 is:
TRIGGERED PULSE MODES
The delays from the zero crossing in the triggered pulse
modes are measured from the point where the output of the
zero crossing detection circuit changes state-the trip point
of this circuit. As stated before, the delay time from this trip
point is:
t
0::;: X3::;: 2'
where: t = period of internal clock
With the preceding information, minimum and maximum values of the delay from true zero can be derived by simply
substituting into the original equation.
T = (A + 1.5)t
where: T = delay time from trip point
(RS+2.6k)
1
TMIN = (A+1.5)t--arcsin 0.15-- - - +0.3",.s
V INX2.6 k
21Tf
A = contents of register A
t = period of internal clock
The delay from the true zero crossing of the input waveform
has other parameters that must be considered. The equation is of the form:
1
. (
RS+2.6k)
TMAX = (A+ 1.50)t+- arcsin 0.15-- - V INx2.6 k
21T f
t
+0.6",.s +2'
T = (A + 1.5)t ±IX11 + X2 + X3
where: T, A, t are as defined previously
The preceding information should enable the user to determine more closely the actual delay from zero of output OA
of the COP452L. This analysis applies to both of the triggered pulse modes. The three parameters, X1, X2, X3, also
apply in the same way in the triggered pulse and count
mode when OA returns to since it is the zero cross detection circuit that causes the output to return to zero in that
mode.
X1 = time for input waveform to reach the trip
point of the zero cross detection circuit
X2
= propagation delay through the zero cross
detection circuit
a
X3 = input synchronization delay
Parameter X1 is dependent on the peak voltage at pin ZI
and on the frequency of the input signal. The peak voltage
at ZI is in turn dependent on the Rs-RIN voltage divider and
the input voltage. The X1 time is added or subtracted because the trip point of the zero cross detection circuit may
be either above or below zero. In the worst case, the trip
point is the maximum offset of 150 mV. For a sine wave
signal, X1 is determined as follows:
VOFFSET
COP452L
VPZ\:r
ZI
VIN
-=
= Vp sin[21T f(X1)]
TL/DD/6155-26
FIGURE9a
X1 = _1_ arcsin VOFFSET
21Tf
Vp
vee
and
..n...
RIN
Vp = VIN Rs + RON
COP452L
substituting we have
X1 = -
1
21Tf
arcsin
(
Rs + RIN)
VOFFSET--VIN RIN
-=
TLlDD/6155-27
FIGURE 9b
where: VOFFSET = zero crossing offset or trip point
Vp = peak input voltage at pin ZI
f = frequency of input signal
RIN
RS
eOP452L
INTERNAL
VIN
= internal impedance to ground at pin ZI
RS = external series resistance at ZI
RIN
Both VOFFSET and RIN vary from device to device. It is clear
from the equation above that the maximum value of IX11 is
-=
FIGURE 10
6-19
TLlDD/6155-28
[II
-I
C\I
I.l)
C")
D..
Applications Information
(Continued)
oo
TRIGGERED PULSE MODES: INTERVENING
ZERO CROSSINGS
-I
In the triggered pulse modes, it is possible to specify a delay
from the zero crossing which will extend beyond the next
zero crossing. In the triggered pulse and count mode, the
intervening zero crossing is ignored and therefore lost. The
device will still continue to operate properly. The situation is
somewhat different in the "pure" triggered pulse mode
where both a delay and a pulse width are specified. Any
zero crossing which occurs during the programmed delay
time is ignored and therefore lost. However, if the delay time
is counted out and the zero crossing occurs during the pulse
width high time, the zero crossing will be recognized and the
delay time will start counting again while the pulse width
high time is being counted. This can result in a variety of
possible conditions at the output-ranging from the apparent loss of that zero crossing to an effective very short delay
from the zero crossing. What will occur depends on the values of the two counters and on their relationship to the
times between zero crossings. Some interesting output
waveforms can be produced, but their utility is questionable.
Therefore, the user should exercise extreme caution in this
mode and make sure that the times are such that all zero
crossings occur at the "right" times. Otherwise, the user
must be prepared to accept the bizarre effects that this situation can produce.
.......
C\I
I.l)
'II:t
D..
o
o
The counters decrement on a low-going pulse at the input.
As stated above, the pulse must remain low at least one
internal frequency period to give reliable counting. Similarly,
the count signal must go high and remain high at least one
internal frequency period before it goes low again. However,
the count signal does not have to be symmetrical.
COP452L OSCILLATOR
The COP452L will operate over a wide range of oscillator
input frequencies. The input frequency may be supplied
from an external source or CKI and CKO can be used with a
crystal or resonator to generate the oscillator frequency.
Figure 11 indicates some crystal networks for some typical
crystal values.
RC and LC networks can also be connected between CKI
and CKO to produce the oscillation frequency. Figure 12
indicates some examples of such networks. Figure 12a is
the recommended RC network for use in this manner. With
C1 = 0.005 ILF, R = 1.5 k!l., and C2 between 20 pF and
400 pF oscillation frequencies between about 1 MHz and
2 MHz should be obtainable. The oscillation frequency decreases with increasing values of C2. The user should feel
free to experiment with the Rand C values, and with the
network configuration, to produce the oscillation frequency
desired.
Figures 12b and 12c indicate LC networks that can be used
to produce the COP452L oscillation frequency. In Figure
12b, with L = 100 ILH and C = 100 pF, a frequency of
about 2 MHz should be produced. In Figure 12c, with L =
56 ILH, C2 = 27 pF, and C1 between 33 pF and 0.01 ILF,
frequencies between about 1.5 MHz and 2 MHz can be produced.
There is, in effect, an inverter between CKI and CKO. This
inverter was designed for use with a crystal and its associated network. It was not designed for use with the RC and LC
networks previously described. However, these networks
will work and are usable. The user should be prepared to
experiment with the networks to determine component values, stability, oscillation frequency, etc. These networks
should be viewed as the starting point for a user who wishes
to use networks of this type to generate the COP452L oscillation frequency.
COUNT MODES
As stated before, the counters are 16-bit down counters.
Pre loading them when they are enabled as external event
counters with ones or zeroes will give the one's or two's
complement of the count. To read the counters it is necessary to first copy the counter to its respective register and
then read the register.
The user can utilize the fact that the outputs toggle when
the counter counts through zero. The counter can be preloaded with a value that represents the number of events
the user wishes to count. When the output corresponding to
that counter toggles, the specified number of events have
occurred. Thus, the user can know that the required number
of events have occurred without having to actually read the
counter.
The counters require a pulse width greater than or equal to
the period of the internal frequency in order to be reliably
decremented. It is possible for a narrower pulse to decrement the counter, but it is not guaranteed. A narrower pulse
will decrement the counter if it appears at the count input at
the right time relative to the internal timing of the device.
Since the user does not have access to this internal timing,
it is impossible for him to synchronize the count input to this
timing and effectively reduce the required width of the count
pulse. Therefore, applying pulses at the count input of less
than one period of the internal frequency in width may
cause erratic counting in the sense that some of the pulses
may be recognized and some may not be recognized. Reliable counting is assured only if the width of the count pulse
is greater than or equal to one period of the internal frequency.
The RC networks provide an inexpensive way to generate
the oscillation frequency. It is foolish, however, to expect
any significant degree of frequency stability or accuracy
over temperature and voltage with a simple RC networkespecially if inexpensive, uncompensated components are
used. LC and RLC networks can produce very stable and
accurate frequencies. Regardless of the network used, the
user must consider the variation of the external components
in his design if accuracy and stability are important considerations in his application.
The crystal networks of Figure 11 provide frequency stability
and accuracy and are easy to use. If the application requires
oscillation frequency accuracy and stability the crystal networks are recommended as the best solution.
6·20
o
Applications Information
o"C
(Continued)
~
U1
N
r.......
o
COP452L
o"C
CKO
CKI
W
U1
Rl
N
rR2
0
*C2
*Cl
TLIDD/6155-30
Crystal
Value
Component Values
R1
R2
C1
C2
455 kHz
1M
16k
80 pF
80 pF
32 kHz
1M
220k
6 pF-36 pF
30pF
FIGURE 11. COP452 Crystal Oscillator
COP452L
COP452L
COP452L
CKI
CKO
C2
TL/DD/6155-31
TLIDD/6155-32
TL/DD/6155-33
a.
c.
b.
FIGURE 12. RC and LC Networks to Produce COP452 Oscillator Frequency
WHITE NOISE GENERATION MODES
white noise mode presets the 16th stage to a 1 and connects the 17th stage to the shift register. If the user wishes,
he can write register A and then enter the white noise and
frequency mode. The output at OA will then be "1", and the
lower 15 bits of the data user had written to register A. Following that, the polynomial sequence dictates the output.
This injection of a 1 into the 16th stage prevents the lockup
condition that occurs if all the stages are O.
In the two white noise modes register A is converted into a
17-stage shift register, or polynomial, generator. With feedback taps at stages 17 and 14, as indicated in Figure 13, a
maximal length sequence is generated. With these feedback taps the characteristic polynomial of the sequence is:
X 17
+ X3 + 1.
The output of this generator is a pseudo-random sequence.
Since the register is shifted at the internal frequency rate,
the sequence repeats after a period equal to (2 17 -1 )t,
where t is the period of the internal frequency.
WARNING: To insure proper operation, the white noise
must be entered from the Reset mode. The COP452 must
be in the Reset mode before the desired white noise mode
and there may be no intervening modes between Reset and
the desired white noise mode. (The state of 17th stage is
don't care (unknown).)
The first 16 stages of the shift register are the 16 bits of
register A that the user may read or write. Entering either
6-21
•
I
...I
N
Lt)
C")
c.
o
o
.......
Applications Information
(Continued)
...I
N
Lt)
~
c.
o
o
PRESET
WHITE NOISE &
FREOUENCY MODE
OUTPUT DA
DB
GATED WHITE
NOISE MODE
Note: Setting the Register A to all l's will result in a predictable pattern each time this mode is activated.
TL/DD/6155-34
FIGURE 13. COP452L White Noise Generator
1. Pin G2 is used as the chip select for the COP452L (because G2 is available on all COPS microcontrollers).
INTERFACE TO COPS MICROCONTROLLERS
Figure 14 indicates the typical interface between the
COP452L and a COPS microcontroller. As is obvious from
the figure, the interface is the standard MICROWIRE. G2 is
indicated as the chip select line because it is available on all
COPS microcontrollers. Obviously, any convenient output of
the microcontroller may be used as the chip select for the
COP452L.
COP411l
DR
LARGER
DO
DI
2. G2 is assumed high on entry to the routines.
3. The SK clock is off (0) on entry to the routines.
4. Register 0 of the microcontroller is arbitrarily chosen as
the I/O register.
5. The leading digit sent out is of the form 001 X where 1 is a
start bit; X is 1 or 0, depending on the operation.
6. The next lower digit contains the remaining 4 bits of the
command.
7. If data is being sent, it is in the next 16 bits of information
sent.
8. Location GSTATE chosen as RAM address 0,15.
9. SK frequency is less than or equal to the internal frequency.
Since the COP452L is an I/O device, the code takes precautions to insure that SO is 0 prior to enabling the SK
clock. (This is a wise precaution to take in any system with
I/O peripherals on the serial port.)
Two versions of the WRITE routine are provided. The destructive WRITE routine destroys the information in the microcontroller as the data is being sent out to the COP452L.
The nondestructive WRITE routine preserves the data in the
microcontroller as that data is being sent out to the
COP452L. The destructive routine is a little more code efficient than the nondestructive routine.
CDP452L
COP352L
SK
TL/DD/6155-35
FIGURE 14
The CS pin of the COP452L must be toggled between successive communications with the device. The internal I register (instruction register) is held reset (all zero) when CS is
high. Since this is the only way in which the I register is
cleared, failure to take CS high between accesses will result
in improper operation.
The COP452L contains an internal power-on reset circuit
which sets the mode latches to one, i.e., places the
COP452L in the RESET mode, and sets the oscillator divider to divide by 4. The counters and registers are not affected by this reset circuit and are therefore undefined at power
up.
INTERFACE SOFTWARE FOR THE COP452L
Sample software for interfacing COPS micro controllers to
the COP452L is given below. The code is completely general and will work in any COPS microcontroller. The following
assumptions are made:
6-22
(")
Applications Information
o"C
(Continued)
~
U1
WRCMND:
WRDATA:
WRITE:
SEND:
FINISH:
DONE:
CLRA
AISC
JP
CLRA
AISC
LBI
RMB
OMG
CAB
LEI
RC
CLRA
XAS
SC
LD
XAS
XDS
JP
RC
XAS
LBI
5MB
OMG
LEI
RET
CODE TO WRITE COP452L -
I\)
; SET UP POINTER FOR COMMAND ONLY WRITE
r.......
1
WRITE
(")
o"C
; SET UP POINTER FOR COMMAND AND DATA WRITE
5
GSTATE
; GSTATE
(,.)
= LOCATION 0,15
U1
I\)
2
;
;
;
;
r-
SEND COP452L CHIP SELECT LOW
POINT TO PROPER LOCATION FOR OUTPUT
ENABLE SHIFT REGISTER MODE
JUST TO INSURE SO
0 BEFORE CLOCK ON
=
; THESE 3 WORDS FOR SAFETY ONLY
; SO SK WILL TURN ON AT NEXT XAS
SEND
; ALL DONE, SK OFF. DESELECT COP452L. AND SET
; SO TO ZERO
GSTATE
2
DATA DESTROYED IN MICROCONTROLLER
TL/DD/6155-36
•
6-23
I
~
('\II
11)
C")
D..
oo
......
-I
('\II
11)
"'I:t
D..
oo
.---------------------------------------------------------------------------------,
Applications Information
(Continued)
The code below is the code to read COP452L. It is written
so that the command to the COP452L is sent out nondestructively, i.e., the data in the microcontroller is preserved.
A routine which sends out the data destructively could be
READ:
SEND2:
RDLOOP:
CLRA
AISC
LBI
RMB
OMG
CAB
SC
CLRA
LEI
XAS
LD
XDS
JP
XAS
CLRA
AISC
CAB
NOP
NOP
NOP
CLRA
XAS
XDS
JP
RC
XAS
JP
1
GSTATE
2
easily generated but is not shown here. The user is referred
to the techniques in the WRITE routines to determine how
to modify this READ routine to send the command out destructively.
; READ INSTRUCTION IN 0, 1 AND 0, 0 AND IS
; OF THE FORM 00100010 OR 00100011 IF READ
; RA OR RB
; SELECT THE COP452L
; SO THAT ZEROES GO OUT FIRST
SEND2
; NONDESTRUCTIVE SENDING OF READ INSTRUCTION
; SET UP TO READ
; NOW WAIT FOR THE DATA
RDLOOP
DONE
;
;
;
;
;
TURN OFF THE CLOCK
READ LAST 4 BITS
COMMON EXIT WITH WRITE ROUTINE
EXITS WITH DATA IN LOWER 3 DIGITS OF RO
AND IN THE ACCUMULATOR
SAMPLE CODE TO READ THE COP452L
WRCMND:
WRDATA:
WRITE:
SEND:
FINISH:
DONE:
CLRA
AISC
JP
CLRA
AISC
LBI
RMB
OMG
CAB
RC
CLRA
LEI
XAS
SC
CLRA
XAS
LD
XDS
JP
XAS
CLRA
NOP
RC
XAS
LBI
5MB
OMG
LEI
RET
CODE TO WRITE COP452L -
; SET UP POINTER FOR COMMAND ONLY WRITE
1
WRITE
; SET UP POINTER FOR COMMAND AND DATA WRITE
5
GSTATE
2
; SELECT THE COP452L - G2 LOW
; LOAD THE POINTER
; ENABLE SHIFT REGISTER MODE
; SEND OUT ZEROES
; FIRST TIME THROUGH, TURNS ON CLOCK
; THEN SENDS DATA
SEND
; SEND LAST 4 BITS
; ALL DONE, SK OFF
GSTATE
2
; DESELECT THE COP452
; SEND SO LOW
DATA PRESERVED IN MICROCONTROLLER
TLlDD/6155-37
6-24
o
Applications Information
o"C
(Continued)
The software interface routines provided above are general
purpose routines written to work in the general case for all
COPS microcontrollers. They are written as subroutines to
be called by the main program. There is no question that
other routines can be written to perform the required function. It is also clear that these routines can be reduced in
specific applications. These routines should be viewed as
providing a framework from which the user can develop routines which are optimal to a specific application.
quency is 525 kHz. Since the registers in the COP452L are
loaded with a number related to the period of the frequency,
we need the periods of f1 and f2.
1
f1 =
1
f2 =
t1
2' =
t1 = 1062.7 J-Ls;
t2 = 748.5 J-Ls;
t2
2' =
531.35 J-Ls
oI:loo
U1
N
........
o
o"C
Co)
U1
374.25 J-Ls
.N
As stated earlier, the period of an output frequency in the
COP452L in the frequency generation mode is given by:
Assumption 9 mentioned prior to the code itself presents an
important requirement for the interface software. There
must be a time delay greater than 3 periods of the internal
frequency between the time the SK clock is turned off and
the time the COP452L is deselected. This is required because the COP452L reads the instruction register with timing based on its internal frequency. When the microcontroller deselects the COP452L, CS goes high and the instruction register is automatically cleared. Therefore, depending
on the relative speeds of SK and the internal frequency, it is
possible that the instruction register may be cleared before
the COP452L has accepted the information. The sample
code provided automatically satisfies the requirement mentioned above whenever the SK frequency is less than or
equal to the counter clock frequency. When SK is faster
than the internal frequency, some delay may be required
between the time SK is turned off and the time the
COP452L is deselected. The time delay is not required
when reading or writing the COP452L registers or when
changing the oscillator divider.
T = 2(N + 1)t
where:
t = period of internal clock
N = register value
Solving for N, the equation becomes:
N=.!.-1
2t
With the internal frequency at 1 MHz, the value of t is 1 J-Ls.
Therefore, the N values with which the registers must be
loaded to generate the frequencies specified above are 278
(116 hex) and 195 (OC3 hex). Note that the fractional parts
of the numbers are lost since the COP452L cannot be loaded with fractional numbers. Note that the fractionial parts
may be reduced or eliminated by judicious choice of the CKI
frequency. With the numbers here, the COP452L will generate a frequency with a period of 1062 J-Ls (941.62 Hz) and a
frequency with a period of 748 J-Ls (1336.9 Hz). Note that
these values are accurate to within 0.7% of the desired output frequencies.
Caution: Failure to observe this time delay will result in improper operation of the COP452L.
Figure 15 indicates a connection diagram for this application. The software to accomplish this task is indicated below. The software indicates several aspects of the usage of
the COP452L. The code first resets the COP452L, then
loads the registers with the proper values, transfers the registers to the counters, puts the COP452L in the CKI divide
by 1 state, and then loads the dual frequency mode. The
output frequency generation begins when the dual frequency mode is loaded. The code as written is independent of
the COP microcontroller used. The code uses the WRITE
routines as described in the software interface section and
assumes that these routines are located in the subroutine
page.
APPLICATION # 1-GENERATION OF
MULTIPLE TONES
The COP452L makes the generation of two independent
frequencies a simple task. This application indicates how to
generate frequencies with the COP452L and also indicates
other aspects of control of the device.
The requirement is to generate the following two DTMF frequencies:
f1 = 941 Hz
f2 = 1336 Hz
We will select the CKI frequency of the COP452L as
525 kHz. Therefore, in divide by 1 mode, the internal fre. PAGE
GSTATE
POWUP:
CLRA
XAS
LBI
STI!
LBI
OMG
LBI
JSRP
LBI
STI!
STI!
JSRP
0
0,15
; TURN OFF SK CLOCK (C
=0 AT POWER UP)
GSTATE
15
GSTATE
; MAKE SURE COP452 IS DESELECTED
0,0
CLEAR
0,0
15
; CLEAR REGISTER 0
; NOW SET UP TO SEND RESET MODE TO COP452
3
; RESET COMMAND AND START BIT
WRCMND
TL/DD/6155-38
6-25
•
..J
C'I
Lt)
Cf)
Applications Information
(Continued)
D.
oo
......
..J
C'I
Lt)
~
D.
oo
; THE eOP452L IS NOW RESET, NOW SET UP 10 WRITE REGISTER A 10
; GENERATE OUTPUT FREQUENCY OF 941 HZ AT OA
LBI
0,0
6
STII
; 116 HEX = 278, GIVE PERIOD OF 1062,,5
STII
STII
STII
0
STII
2
; START BIT PLUS CODE TO WRITE RA
STII
JSRP
WRDATA
: REGISTER A IS NOW LOADED. NEXT TRANSFER REGISTER A TO COUNTER A
LBI
0,0
STII
5
STII
2
; INSTRUCTION TO TRANSFER PLUS START BIT
JSRP
WRCMND
; ALL DONE WITH REGISTER AND COUNTER A, NEXT WORK ON REGISTER B
LBI
0,0
STII
3
; WRITE REGISTER B WITH OC3 HEX (195)
STII
C
; TO GIVE FREQUENCY OF 1336 HZ
0
STII
STII
o
; INSTRUCTION TO WRITE RB
STII
STII
2
JSRP
WRDATA
; REGISTER B IS NOW LOADED. NEXT TRANSFER RB TO CB
0,0
LBI
STII
4
; INSTRUCTION TO TRANSER RB TO CB
STII
2
JSRP
WRCMND
; NOW LOAD CKI DIVIDE BY 1
LIB
0,0
STII
8
STII
2
JSRP
WRCMND
; NOW PUT THE COP452 IN DUAL FREQUENCY MODE
LBI
0,0
STII
0
STII
3
JSRP
WRCMND
; NOW THE CODE MAY PROCEED TO DO WHATEVER ELSE IS REQUIRED IN
; THE APPLICATION.
: THE SUBROUTINES USED IN THIS APPLICATION ARE CLEAR AND THE
; WRITE ROUTINES. THE ADD ROUTINE IS USED IN THE EXAMPLE BELOW
2
. PAGE
CLEAR:
CLRA
XIS
JP
CLEAR
RET
ADD:
SC
LBI
2, 9
; ROUTINE ADDS 1 TO COUNTER
ADD1:
CLRA
Ase
NOP
XIS
ADD1
JP
RET
o
WRCMND:
; SEE SOFTWARE INTERFACE FOR THIS ROUTINE
WRDATA:
; SEE SOFTWARE INTERFACE FOR THIS ROUTINE
TLIDD/6155-39
6-26
Applications Information
o
o
(Continued)
"'CJ
The preceding has done a lot with the COP452L. It is clear
that the code can be reduced and specialized. The purpose
here was to illustrate the various communications with the
device.
below. This code assumes that the registers have been
loaded and that the COP452 is in dual frequency mode.
Again, the code is written to be independent of the COPS
microcontroller used.
An interesting effect can now be produced by making use of
the 4 to 1 CKI divider. With the CKI frequency at 525 kHz,
the internal frequency is well within the specified limits in
either the divide by 1 or divide by 4 condition. Therefore, this
characteristic of the device can be used to quickly multiply
or divide the output frequency by 4. An interesting siren ef·
fect can thus be created. Sample code to do this is given
As is obvious from this code, it is a simple matter to create
this effect. As was mentioned earlier, the code here is gen·
eral purpose. This necessarily means that it can be reduced
in specific applications. The user should view this code as
representative of the techniques involved and then optimize
or rewrite the routines to suit his particular application.
SIREN:
PLUS1:
PLUS1A:
LBI
JSRP
LBI
STII
STII
JSRP
JSRP
SKC
JP
LBI
STII
STII
JSRP
LBI
JSRP
JSRP
SKC
JP
JP
2,9
CLEAR
0,0
8
2
WRCMND
ADD
; USE REGISTER 2 AS COUNTER FOR DELAY TIME
PLUSl
; EXIST DELAY LOOP WHEN COUNTER OVERFLOWS
; CKI DIVIDE BY 1
; INCREMENT COUNTER FOR DELAY
0,0
9
2
WRCMND
2,9
CLEAR
ADD
; CKI DIVIDE BY 4
; AGAIN, TIME OUT VIA THE COUNTER
PLUS1A
SIREN
; DONE, START OVER AGAIN
TLIDO/6155-40
Vee
Vee
OSCILLATOR
INPUT
Vee
COP411L
OR
LARGER
COP452L
DO
":"
eKI
eKO
":"
OR
1MQ
DA
OB
6-36pF
TLIDD/6155-41
FIGURE 15. Dual Frequency Application
6·27
.a:a.
U1
I\)
r
........
o
o
"'CJ
w
U1
I\)
r
~ r---------------------------------------------------------------------------------~
N
LI)
Cf)
D-
oo
-.....
~
N
LI)
~
D-
O
o
Applications Information
(Continued)
APPLICATION #2
time base for the COP452L. With the oscillator divide by 4
selection, this gives an internal frequency period of
1.90476 p.s. With this information we can determine the
number that needs to be loaded to register A to give a pulse
width of 5 ms. From application # 1 we have the following
equation which is valid here:
This application makes use of the number of pulses mode of
the COP452L to control a stepping motor. The technique is
equally applicable in any situation where a number of pulses
must be generated based upon the state of the system.
Figure 16 indicates the system interconnect. Since the oscillator frequency is 2.1 MHz max. and the CKO pin of the
COP452L is being used to drive the CKI of the microcontroller, a COP420 is specified as the microcontroller. If a separate oscillator were provided, any COPS microcontroller
could be used. The software is completely general and will
work in any COPS microcontroller.
T = (N
where: T = pulse width
+ 1)t
N = contents of register A
t = period of internal clock
Solving for N we have;
N = (TIt) - 1
= (5 ms/1.90476 p.s) - 1
The application has the following specifications:
1. The pulse width required for the stepping motor is 5 ms
±5%.
= 2625 -1
= 2624
2. The system has 4 return lines which indicate 4 possible
variations in the number of output pulses required. These
four conditions are:
Register A must be loaded with 2624 (OA40 hex) to give a
5 ms pulse. The error created by the truncation of the number is 0.5 p.s. There is an error of 0.01 %-well within the
tolerance limits required.
a. 10 pulses required
b. 100 pulses required
The code to operate this system is given below. The interconnect of Figure 16 is assumed. The code uses the READ
and WRITE subroutines as given in the software interface
section of this data sheet. The code further assumes that
those routines are located in the subroutine page.
c. Repeat the last number of pulses sent
d. Send one more than the last number of pulses
3. The system has a signal available indicating that the return lines contain valid information.
4. One pulse is required at power up.
A flowchart to implement this system is indicated in Figure
17. Figure 16 is the interconnect used in this application. As
the figure indicates, we will use a 2.1 MHz crystal as the
CKI MAX =2.1 MHz
D
CKO
COP42D
L4
L3
L2
G2
CS
SI
DO
SO
01
SK
SK
STEPPING
MOTOR
PLUS
SYSTEM
HARDWARE
COP452L
L1
-=
VCC
-=
S4
T
A
T
E
S
T
A
T
E
S
T
A
T
E
S
T
A
T
E
R
E
A
0
Y
TLlDD/6155-42
FIGURE 16. COP452In Stepping Motor Control
6-28
o
Applications Information
o"tJ
(Continued)
oI:ao
U1
I\)
r.......
o
o"tJ
WRITE RAICA
OF COP452
CI.)
U1
1 - RB/CB
OF CDP452
I\)
r-
SET NUMBER
OF PULSES MODE
RESET CDP452L
0064 - REG.
RESET CDP452
DDDA - REG.
RESET CDP452
READ RB - REG.
REG.+1 - REG.
TL/DD/6155-43
FIGURE 17. Flow Diagram for Application #2
. PAGE
GSTATE
POWRON:
o
0,15
CLRA
XAS
LBI
STII
LBI
OMG
LD
CAMQ
LEI
LBI
STII
STII
STII
STII
STII
STII
JSRP
; TURN OFF SK CLOCK
GSTATE
15
GSTATE
; DESELECT THE COP452L -
4
0,0
G2 HIGH
•
; DRIVE THE L LINES HIGH FOR READING
; ENABLE THE L OUTPUTS
o
4
A
o
1
2
WRDATA
; WRITE RA OF COP452L WITH OA40 HEX TO GET
; 5MS PULSE
TLIDD/6155-44
6-29
....I
C'I
Ln
C")
Applications Information
(Continued)
A.
oo
.......
....I
C'I
Ln
~
A.
oo
RBWRT:
RBWRT2:
RBWRT3:
PULSE:
LBI
STII
STII
JSRP
LBI
STII
STII
STII
STII
STII
STII
JSRP
LBI
STII
STII
JSRP
LBI
STII
STII
JSRP
0,0
5
2
WRCMND
0,0
; TRANSFER RA TO COUNTER A
; NOW WRITE RB WITH THE NUMBER OF PULSES
1
o
o
o
o
2
WRDATA
0,0
4
2
WRCMND
0,0
2
3
WRCMND
; ONE PULSE REQUIRED AT POWER UP
; NOW TRANSFER RB TO COUNTER B
; SET NUMBER OF PULSES MODE
; /!if THIS POINT THE COP452L IS IN NUMBER OF PULSES MODE, ONE
;
;
;
;
;
PULSE IS OUTPUT AT OA. NaN MUST READ THE RETURN LINES, MAKE
THE APPROPRIATE DETERMINATION OF THE STATE OF THE SYSTEM
AND UPDATE THE COPo452L ACCORDINGLY, ALSO AT THIE POINT, THE
COPo452L IS SET UP TO AGAIN GENERATE A SINGLE PULSE 5 rna WIDE
IF THE DEVICE IS ACCESSED AGAIN.
STATE:
STATE1:
TEST2:
STATE2:
TEST3:
STATE3:
LBI
LD
CAMQ
LEI
LBI
INL
SKMBZ
JMP
AISC
JMP
STII
STII
JSRP
LBI
STII
JMP
AISC
JMP
STII
STII
JSRP
LBI
STII
STII
JMP
AISC
JMP
JMP
GSTATE
4
0,0
0
STATE
8
TEST2
15
3
WRCMND
0,0
10
RBWRIT
4
TEST3
15
3
WRCMND
0,0
4
6
RBWRT2
2
TESTo4
PULSE
=
; CONTENTS OF GSTATE 15 HERE
; MAKE SURE L LINES ARE HIGH AND
; ENABLED
;
;
;
;
READ THE L LINES TO A AND M(O, 0)
TEST DATA - RETURN LINES - VALID
DATA NOT VALID, WAIT FOR IT TO BE VALID
DATA IS VALID, DECODE A
; POINTING AT 0, 0
; RESET THE COPo452L FOR STATE 1
; NOW SET UP TO SEND 10 PULSES
; SHARE COMMON CODE
; IN STATE2, MUST SEND 100 PULSES
; FIRST RESET THE COP452L
; WRITE 100 (0064 HEX) TO RB OF COP452L
STATE 3 MERELY SENDS THE SAME NUMBER OF PULSES AGAIN.
THEREFORE, MERELY SEND THE NUMBER OF PULSES MODE COMMAND
AGAIN
TLlDD/6155-45
6·30
Applications Information
TEST4:
STATE4:
PLUS1:
AISC
JMP
STII
STII
JSRP
LBI
STII
STII
JSRP
LBI
XIS
XIS
XIS
XIS
LBI
SC
CLRA
ASC
NOP
XIS
CBA
AISC
JP
JMP
o
o
(Continued)
1
STATE
15
"'tJ
0l:Io
U1
N
ro
; ALL L LINES WERE 0, JUMP BACK TO MAIN
; RESET THE COP452L
........
o"'tJ
3
WRCMND
0,0
w
; NOW READ THE COP452L
U1
2
N
r-
; COMMAND TO READ RB
READ
0,0
; MOVE DATA TO LAST 4 DIGITS OF RO
0,0
; NOW INCREMENT THE VALUE BY 1
12
PLUS1
RBWRT3
; HAVE INCREMENTED THE VALUE, SEND IT OUT
• PAGE
READ:
; SEE SOFTWARE INTERFACE SECTION FOR THESE
; ROUTINES
WRDATA:
WRCMND:
TLlDD/6155-46
These are general routines and can be reduced in specific
applications. The application itself was kept general so that
it can be easily adapted to particular applications. The user
should view this code as the basis from which to work to
optimize the code for a specific application.
Therefore, register A must be loaded with the hex value
F423 to generate a frequency of 2 Hz at OA. Counter B will
count pulses when OA is high by virtue of the ENB input.
When OA is low, the microcontroller will read and reset the
counter and peform any necessary operations.
APPLICATION # 3
With the values above for the internal frequency and the
viewing window, the tachometer range is 240 RPM to
62,500 RPM. By making use of the divide by 1/divide by 4
features of the oscillator divider, the range can be extended
down to 60 RPM. The range when the oscillator is divided
by 4 is 60 RPM to 15,625 RPM. However, a penalty is paid
for this range extension. The viewing window goes from
250 ms to 1 second. The minimum reliable pulse width also
increases from 4 ,...S to 16 ,...s. The added time spent counting mayor may not be acceptable. It can be reduced somewhat by changing the value of RA to give a faster frequency
at the reduced counter clock frequency. However, as the
OA frequency increases, the low end of the range increases.
An application such as a tachometer requires the counting
of external pulses that occur within a given time period. The
COP452L can be used both to perform the counting and to
establish the "viewing window," or time period, during which
to count the pulses. By using the frequency and count mode
of the COP452L, a frequency can be generated which will
establish this viewing time. The other counter can then be
used to count the pulses. Figure 18 provides a diagram of
the interconnect in this application.
As Figure 18 indicates, the oscillator frequency for the
COP452L has been selected as 250 kHz. With the oscillator
divider set at divide by 1, the internal frequency is also
250 kHz. At this frequency, the minimum pulse width that
can be reliably expected to decrement the counter is 4 ,...sthe period of the internal frequency.
A flow chart for this application is provided in Figure 19.
Sample code is given below. Note that the sample code
includes only the COP452L interface and control. Other system requirements, e.g., display interface, arithmetic, etc.,
are not included here. Other data sheets and application
notes provide sufficient information to fill in those details.
A viewing time of 250 ms is arbitrarily selected. This means
that the period of the output frequency is 500 ms-a frequency of 2 Hz. Using the equation developed earlier for
determining the counter values we have:
The hardware interface indicated in Figure 18 and the code
below, are completely general and valid of any COPS microcontroller. In specific applications both the hardware and
software may be optimized to a greater extent than that
shown here.
N=.!.-1
2t
= (500 ms/8 ,...s) -
1
= 62500 - 1
N = 62499 = F423 hex
6-31
•
..J
C\I
1.1)
Cf)
Applications Information
(Continued)
D..
oo
......
OSCILLATOR
INPUT
VCC
250kHz
I
VCC
I
+
CKI
I
..J
C\I
1.1)
'OII:t
D..
oo
CKI
L7
EXPAN OED
LOW RA NGE
r
0-- L3
COP411L
DR LARGER
0
OA
L
ENB
CS
G2
SI
DO
SO
01
SK
SK
JUl..
COP452L
INB
~
-!
""'- 01
..
SA-SH
8
r
COP470
~
SK
CS
MOTOR 5.
ASSOCIATED
ELECTRONICS
...
01-04
4 DIGIT
VF DISPLAY
4
"
I
TL/DD/6155-47
FIGURE 18. COP452In Wide Range Tachometer Application
WRITE F423
- RA/CA
WRITE FFFF
TO RB/C3
NO
READ 5. RESET
CB
TAKE ONE'S
COMPLEMENT
CONVERT
TO RPM
OUTPUT TO
DISPLAY
TL/DD/6155-48
FIGURE 19. Flowchart for Tachometer Application
6-32
o
Applications Information
o"tJ
(Continued)
0l:Io
. PAGE
GSTATE
POWRON:
TSTOAO:
ONECMP:
XFER1:
U1
I\)
0,15
CLRA
XAS
LBI
OBD
STII
LBI
OMG
LD
CAMQ
LBI
STII
STII
STII
STII
STII
STII
JSRP
LBI
STII
STII
JSRP
JSR
JSR
LEI
LBI
INL
SKMBZ
JP
LBI
STII
STII
JSRP
LBI
STII
STII
JSRP
LBI
COMP
XIS
COMP
XIS
COMP
XIS
COMP
X
LBI
LD
XIS
JP
JSR
r-
........
o
; TURN OFF THE SK CLOCK-C=O AT POWER UP
o"'D
GSTATE
; DRIVE 0 LINES HIGH TO DESELECT DISPLAY
(,)
15
GSTATE
U1
I\)
r-
; DESELECT THE COP452L
; SET THE Q REGISTER TO ALL 1'S FOR INPUT
0,0
3
15
1
; NOW SET UP TO WRITE RA OF COP452L
; WRITE RA WITH F423 HEX
TL/DD/6155-49
; REMEMBER COP452L IS RESET AT POWER UP
WRDATA
0,0
5
2
WRCMND
RSTRB
RANGE
4
0,0
TSTOAO
0,0
6
2
WRCMND
0,0
2
READ
0,0
0,0
1
1
XFER1
RSTRB
; TRANSFER RA TO CA
;
;
;
;
RESET RB AND COUNTER B WITH FFFF
TEST RANGE AND SET OSCILLATOR DIVIDER
ENABLE Q TO L-DRIVE L LINES HIGH
LOOK FOR OA = 0
; OA IS 0, READ COUNTER
; FIRST TRANSFER CB TO RB
; THEN READ RB
; NOW TAKE THE 1·S COMPLEMENT
; NOW SAVE VALUE IN R1
; RESET RB AND CB WITH FFFF FOR NEXT TIME
; AT THIS POINT INSERT THE APPROPRIATE CODE FOR ANY NECESSARY
; ARITHMETIC, BINARY/BCD CONVERSION, DISPLAY OUTPUT, AND ANY OTHER
; SYSTEM REQUIREMENTS. AFTER THESE ARE COMPLETE, JUMP TO LABEL
; TSTRNG WHICH HAS BEEN ARBITRARILY PLACED IN PAGE 4.
. PAGE
2
WRDATA:
WRCMND:
; SEE SOFTWARE INTERFACE SECTION FOR THESE
; THREE ROUTINES
READ:
TSTRNG:
TSTOA1:
. PAGE
JSR
LEI
LBI
INL
SKMBZ
JMP
JP
4
RANGE
0,0
; CHECK THE RANGE
; BE SURE Q IS ENABLED TO L
; LOOK FOR OA = 1
TSTOAO
TSTOA1
; THE SUBROUTINES RANGE AND RSTRB ARE INSERTED HERE
RANGE:
LEI
LBI
INL
4
3,15
; MAKE SURE L ENABLED
; WILL SAVE RANGE STATUS IN 3, 15
X
CLRA
; NOW PREPARE TO SET OSCILLATOR DIVIDER
6·33
TLlDD/6155-50
..J
C'I
II)
Cf)
Applications Information
D.
o
o.....
..J
LOW:
HILOW:
C'I
II)
"'I:J'
D.
o
o
(Continued)
AISC
SKMBZ
JP
AISC
LBI
XIS
STII
JMP
; AN 8 MEANS DIVIDE BY 1
3
HILOW
1
; IF DIVIDE BY 4, WANT A giN A
0,0
2
WRCMND
; THE FOLLOWING SUBROUTINE USES A SUBROUTINE LEVEL. IT RESETS BOTH
; REGISTER B AND COUNTER B OF THE COP452L TO FFFF
RSTRB:
LBI
STII
STII
STII
STII
STII
STII
JSRP
LBI
STII
STII
JMP
0,0
15
15
15
15
0
2
WRDATA
; WRITE FFFF TO RB
0,0
4
2
WRCMND
; TRANSFER RB TO CB
TLlDD/6155-51
APPLICATION # 4
Since the register and counter can be loaded with whole
numbers only, register B and counter B must be initialized
with 79 (002F hex) to give a pulse width of 150 p.s.
The triggered pulse mode of the COP452L provides the capability of generating the appropriate signals for triac control. Figure 20 is a general diagram of such an application.
The delay from the zero cross trip point is given by:
Assume the requirement is to switch on the triac 45 degrees
into the waveform. With a 60 Hz sine wave signal, the 45
degree delay is 2.0833 ms from the zero crossing. Assume
also that the triac requires a gate pulse width of 150 p.s. As
the diagram indicates, a 2.097 MHz crystal provides the oscillator input to the COP452L. With the above information
the two values that must be loaded in the COP452L can be
determined. With CKI at 2.097 MHz and the oscillator divider at divide by 4, the period of the internal frequency is
1.9075 p.s. From the description of the triggered pulse
mode, the pulse width is given by:
T
=
T
(A
+ 1.5)t
A = contents of register A
t = period of internal clock
Solving for A we have:
A = (T/t) - 1.5
= (2.0833 ms/1.9075
p.s) - 1.5
A = 1090.66 rounded up to 1091
Therefore register A and counter A must be initialized with
1091 (0443 hex) to delay 2.0833 ms (45 degrees at 60 Hz)
from zero cross.
Bt
where: T = desired pulse width
Once the data has been given to the COP452L and the
device placed in the triggered pulse mode, no further attention is required. The COP452L will generate the pulses with
the appropriate delay as long as the power is applied and
the input sine wave is available. It is a trivial matter to
change any of the information. Merely write the appropriate
register/counter pair. Thus very easy control is available
over the firing angle of triacs.
B = contents of register B
t = period of internal clock
Solving for B is trivial and gives:
B = T/t
= 150
=
where: T = delay from zero cross trip point
p.s/1.9075 p's
= 78.64
Sample code to accomplish this function is given below.
The code is general purpose and is written to work in any
COPS microcontroller.
6-34
o
o
Applications Information (Continued)
."
0l:Io
UI
2.097 MHz
I\)
~~~D""""'-OSC.
IN
r......
o
o."
1Mg
Vec
~
UI
I\)
CKI
COP411L
OR
r-
CKO
COP452L
LARGER
RS
110YJIEAK
10HZ,.........
:. As
V
~
VIN/10 x 7.8k - 7.8k
x 7.8k-7.8k
~
180/10
~
132.6 kn
:. Arbitrarily Select As = 150 kn
TL/00/6155-52
FIGURE 20. COP452L as Triac Controller
• PAGE
GSTATE
POWRON:
o
0,15
CLRA
XAS
LBI
STU
LBI
OMG
LBI
STU
STU
STU
STU
STU
STU
JSRP
LBI
STU
STII
JSRP
LBI
STU
STU
STU
STU
STII
STU
JSRP
LBI
STU
STU
JSRP
LBI
STU
; TURN OFF THE SK CLOCK
GSTATE
15
GSTATE
0,0
15
; DESELECT THE COP452L - G2 HIGH
; NOW WRITE RBICB WITH 002F HEX TO GIVE
; 150jAs PULSE WIDTH
2
o
o
o
2
WRDATA
0,0
4
2
WRCMND
0,0
; TRANSFER RB TO CB
; NOW WRITE RA/CA WITH 0443 HEX FOR THE DELAY
3
""o
1
2
WRDATA
0,0
5
2
WRCMND
0,0
; TRANSFER RA TO CA
9
TlI00/6155-53
STiI
2
; SET OSCILLATOR DIVIDER TO DIVIDE BY 4
JSRP
WRCMND
LBI
0,0
STU
1
; SET TRIGGERED PULSE MODE
STII
3
JSRP
WRCMND
ALL COMPLETE AT THIS POINT. ROUTINES WRCMND AND WRDATA ASSUMED
IN PAGE 2 AND ARE THE SAME AS GIVEN IN SOFTWARE INTERFACE SECTION.
THE COP"52L WILL NOW GENERATE THE 150 pi PULSE DELAYED BY 2.0833 ms
FROM EVERY ZERO CROSSING. THE USER CAN NOW IGNORE THE TRIAC CONTROL
AND DO WHATEVER ELSE IS REQUIRED IN THE SYSTEM. FURTHER AITENTION
IS REQUIRED ONLY WHEN THE DATA IN THE COP452 MUST BE CHANGED.
TlIOO/6155-54
6-35
•
..J
N
it')
Cf)
Applications Information
o
Let us now compute the minimum and maximum delays
from the true zero crossing in this application. As indicated
earlier, the period of the internal frequency here is
1.9075 ,..,s. Counter A contains 0443 hex (decimal 1091). Rs
is 150k and the peak input voltage is 180V. A 60 Hz sine
wave is assumed. As given earlier, the minimum time is:
a.
o
.......
..J
N
it')
'OI:t
a.
o
o
(Continued)
As is obvious from the preceding analysis, the parameter
previously defined as X1 is the most significant of the additional factors that define the time delay from true zero. This
factor can be minimized by using as small a series resistance as possible. The frequency and input voltage will be
governed by the application. The user must also remember
that the minimum and maximum times calculated in this
manner are absolute worst case values derived using the
worst case condition.
1
(RS+2.6k)
TMIN = (A + 1.5)t - 2'ITf arcsin 0.15 VIN x 2.6k + 0.3 ,..,s
Substituting we have:
1
(
152.6k )
TMIN = 1092.5t - 120'IT arcsin 0.15180X2.6k +0.3,..,s
= 2093.9,..,s - 129.7 ,..,s + 0.3 ,..,s
TMIN = 1954.5,..,s
Similarly, the maximum time is given as:
1
( R s + 2.6k)
T MAX = (A + 1.5)t + 2'ITf arcsin 0.15 VIN x 2.6k +
0.6,..,s +
t
2
Substituting, we have:
152.6k)
1
(
TMAX = 1092.5t + 120'IT arcsin 0.15 180 x 2.6k +
0.6,..,s +
1.9075,..,s
2
= 2083.9,..,s + 129.7 ,..,s + 0.6,..,s + 0.9538,..,s
TMAX
= 2215.15,..,s
6-36
o
o
~National
""a
~
.....
o
~ Semiconductor
........
o
o""a
COP470/COP370 V.F. Display Driver
W
.....
o
General Description
Features
The COP470 is a peripheral member of National's COPSTM
Microcontroller family. It is designed to directly drive a mUltiplexed Vacuum Fluorescent display. Data is loaded serially
and held in internal latches. The COP470 has an on-chip
oscillator to multiplex four digits of eight segment display
and may be cascaded and/or stacked to drive more digits,
more segments, or both.
• Directly interfaces to multiplexed 4 digit by 8 segment
Vacuum Fluorescent displays
• Expandable to drive 8 digits and/or 16 segments
• Compatible with all COP400 processors
• Needs no refresh from processor
• Internal or external oscillator
• No "glitches" on outputs when loading data
• Drives large and small displays
• Programmable display brightness
• Small (20-pin) dual-in-line package
• Operates from 4.5V to 9.5V
• Outputs switch 30V and require no external resistors
With the addition of external drivers, the COP470 also provides a convenient means of interfacing to a large-digit LED
display. The COP370 is the extended temperature range
version of the COP470.
• Static latches
• MICROWIRETM compatible serial I/O
• Extended temperature device COP370
+ 85°C)
(-40°C to
Connection and Block Diagrams
Dual-In-Line Package
SO
SE
SC
SF
S8
SG
SA
SC
SB
4
3
SE
SO
2
SG
SF
01
SH
OSC
03
02
04
11 12 13 14
1 20 19 lB 17
SH
SA
NOT USEO
OSC
VGG
VOO
04
03
02
01
TL/DD/6154-1
Top View
FIGURE 1. COP470
Order Number COP470D,
COP370D, COP470N or
COP370N
See NS Package Number
D20Aor N20A
DI~----------_~I
..!.VDD
.1!!vss
SK~------------~~~--~
~vGG
~~-----------------------~~----~
TL/DD/6154-2
FIGURE 2. COP470
6-37
o
......
C")
D-
Absolute Maximum Ratings (Vss = 0)
o
........
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Temperature
COP470
COP370
"lilt'
D-
Voltage at Display Outputs
+ 0.3V to - 30V
Storage Temperature
O
o
Voltage at All Other Pins
+ 0.3V to - 20V
Lead Temperature (Soldering, 10 sec.)
O
o
......
O·C to +70·C
- 40·C to + 85·C
- 65·C to + 150·C
Package Power Dissipation
300·C
400 mW at 25·C
200 mW at 70·C
125 mW at 85·C
DC Electrical Characteristics
COP470 and T A
Vss = 0, Voo = -4.5Vto -9.5V, VGG = -30V, TA = O·Cto +70·Cfor
= 40·C to 85·C for COP370 unless otherwise specified.
Parameter
Power Supply Voltage
Voo
VGG
Min
Max
Units
-9.5
-30
-4.5
Voo
V
V
5
1
mA
mA
+0.3
-4.0
V
V
Power Supply Current
100
IGG (Displayed Blanked)
Input Levels
VIH
VIL
-1.5
-10.0
Output Drive Digits and Segments
IOH @ VOH = Vss - 3V
IOH @ VOH = Vss - 2V
IOL @ VOL = VGG + 2V(1)
10
7
10
mA
mA
JLA
Output Drive @ VGG = Voo
IOH @ VOH = Vss -2V
1
mA
= Vss -5V
Allowable Source Current
Per Pin
Total for Segments
20
60
Input Capacitance
7
pF
Input Leakage
1
JLA
mA
mA
AC Electrical Characteristics
COP470 and T A
Vss = 0, Voo = -4.5Vto -9.5V, VGG = -30V, TA = O·Cto +70·Cfor
= 40·C to 85·C for COP370 unless otherwise specified.
Parameter
OSC Period (internal or external)
OSC Pulse Width
Clock Period T (twice Osc. period)
Display Frequency
4 digits = 1/64T
8 digits = 1/128T
SK Clock Frequency
Min
Max
Units
4
20
JLs
1.5
JLs
8
40
JLs
390
190
2000
1000
Hz
Hz
0
250
kHz
SK Clock Width
1.5
JLs
Data Set-up and Hold Time
tSETUP
tHOLO
1.0
50
JLs
ns
CS Set-up and Hold Time
tSETUP
tHOLD
1.0
1.0
JLs
JLs
Duty Cycle
4 digits
8 digits
1/64
11128
15/64
15/128
Note 1: IOL current is to VGG with the chip running. Current is measured just after the output makes a high·to-Iow transition.
6-38
Timing Diagram
o
o
1
"C
0l:Io
....
1-l-sK
CS SETUP
H~~o III____________________
--l
WIDTH
~~~
Q
........
o
~r--
I I
o"C
I
....
Cot,)
Q
SK
ol~~O
1
10
-SETUP
/-HoLo
TL/DD/6154-3
FIGURE 3. Serial Load Timing Diagram
Performance Characteristic
Output Source Current
-28
-24 1--tl--+--if7""'5I"'=Ii
~
-16
~4-:l-hI-4-+--+--+--I
., -12
I--f-'rl-~-t--+---l-+---i
:z:
-2 -4
-6 -8 -10 -12 -14
VOH VOLTS
TL/DD/6154-4
Functional Description
SEGMENT DATA BITS
The fifth and sixth bits control the multiplex digits. To enable
the COP470 to drive a 4 digit multiplex display, set both bits
to one. If two COP470s are used to drive an 8 digit display,
bit five is set on the left COP470 and bit six is set on the
right COP470 (see Figure 6). In the eight digit mode, the
display duty cycle is on time/128.
Data is loaded in serially in sets. Each set of segment data
is in the following format:
1 SA 1 SS 1 SC 1 SO 1 SE 1 SF 1 SG 1 SH 1
Data is shifted into an eight bit shift register. The first bit of
the data is for segment H, digit 1. The eighth bit is segment
A, digit 1.
FILAMENT
VOLTAGE
A set of eight bits is shifted in and then loaded into the digit
one latches. The second set of 8 bits is loaded into digit two
latches. The third set into digit three latches and the fourth
set is loaded into digit four latches.
DISPLAY ON TIME AND CONTROL BITS
+5 VOLTS
The fifth set of 8 data bits contains blank time data and
control data in the following format:
Display Digits
I
j
Sync
Ext.
Vss
Right
Left
+-
1 Osc. 14 of 814 of 81 LSS 1
On Time
1
Mssl
The first four bits shifted in contain the on time. This is used
to control display brightness. The brightness is a function of
the on time of each segment divided by the total time (duty
cycle). The on time is programmable from 0 to 15 and the
total time is 64. For example, if the on time is 15, the duty
cycle is 15/64 which is maximum brightness. If on time is 8,
the duty cycle is 8/64, about 1/2 brightness. There are 16
levels of brightness from 15/64 to 0/64 (off).
TLlDD/6154-5
FIGURE 4. System Dlagram-4 Digit Display
6-39
D.
o
Functional Description
o
.......
o
r-~
T
D.
_1··...' = - - - 1 - 5 - T - - - ' - - - - - 6 4 T - - - - - - - - - - - · 1
ANY SEGMENT
oo
(Continued)
.!..J
U"--ON---:_ _O::.:.F~F_ _~
ON
ON
01J
ON TIME=15
(MAX BRIGHTNESS)
02 ____________~
03 ___________________
~
o
r-(f)
041L__________________________~
-ST_I-ST-I
ANY SEGMENT
I
OFF
ON
01~
ANY SEGMENT
T ......n..._____________n...____ ]
i-15T-Jn...L-______
ON TIME=l
01--11-TL/DD/6154-6
FIGURE 5. Segment and Digit Output Timing Diagram
The seventh bit selects internal or external oscillator. The
OSC pin of the COP470 is either an output of the internal
oscillator (bit 7 = 0) or is an input allowing the COP470 to
run from an external oscillator (bit 7 = 1).
1. Turn CS Iwo on both COP470s.
2. Shift in 32 bits of data for the right 4 digits.
3. Shift in 4 bits of on time, a zero and three ones. This
synchronizes both chips, sets to external oscillator, and
to right four of eight digits. Thus both chips are synchronized and the oscillator is stopped.
4. Turn CS high to both chips.
The eighth bit is set to synchronize two COP470s. For example, to set the COP470 to internal osc, 4 digits, and maximum brightness, send out six ones and two zeros.
LOADING SEQUENCE
5. Turn CS low to the left COP470.
6. Shift in 32 bits of data for the left 4 digits.
Step
1. Turn CS Low.
2. Clock in 8 bits of data for digit 1.
3. Clock in 8 bits of data for digit 2.
4. Clock in 8 bits of data for digit 3.
5. Clock in 8 bits of data for digit 4.
6. Clock in 8 bits of data for on time and control bits.
7. Shift in 4 bits of on time, a one and three zeros. This sets
this COP470 to internal oscillator and to left four of eight
digits. Now both chips start and run off the same oscillator.
8. Turn CS high.
The chips are now synchronized and driving eight digits of
display. To load new data simply load each chip separately
in the normal manner.
7. Turn CS high.
Note: CS may be turned high after any step. For example, to load only 2
digits of data do steps 1, 2, 3, and 7. CS must make a high to low transition
before loading data in order to reset internal counters.
16 SEGMENT DISPLAY
Two COP470s may be tied together in order to drive a sixteen segment display. This is shown in Figure 8. To do this,
both chips must be synchronized, one must run off external
oscillator while the other runs off its internal oscillator outputting to the other. Similarly, four COP470s could be tied
together to drive eight digits of sixteen segments.
8 DIGIT Displays
Two COP470s may be tied together in order to drive an
eight digit multiplexed display. This is shown in Figure 6. The
following is the loading sequence to drive an eight digit display using two COP470s.
6-40
Functional Description
"o
(Continued)
"tJ
~
.........
o
........
"o
B DIGIT VF DISPLAY
"tJ
CN
.........
o
TLlDD/6154-7
FIGURE 6. System Diagram 8 Digit Display
-----,~
__~Dl~__~CH~IP~A~________________________________~r_____1~
________
CHIP A
----IDzI~~----------------~--------~
~
D3
rtiiiPTl
D4
CHIP A
Dl
CHIP B
________________________________
r---,
r___l~
______
~~
______
______
-----,
D2
__ CHIP B __________
__
D3
~
~~
D4
~~
~~~
CHIP B
__
~~
CHIP B
SEGMENT CHIP A
~r-
___________________________
~r_____1~
______________
_______________________
~r___I~
______________________
r----,
~
________________
~r____1~
____________________
____________
~r___l~
______
SEGMENT CHIP B
RESULTANT SEGMENT
SEG. CHIP A& SEG. CHIP B WIRED TOGETHER
TL/DD/6154-B
FIGURE 7. Segment and Digit Output Timing Diagram for 8 Digits
4 DIGIT, 16 SEGMENT
VF DISPLAY
SO
COP
400
SK
1-=0:.::0________________---1
01
TL/DD/6154 -9
FIGURE 8. System Diagram for 16 Segment Display
6-41
C) r-----------------------------------------------------------------------------------~
......
C")
a.
oo
........
C)
......
~
Functional Description
(Continued)
LED DISPLAY
The COP470 may be used to drive LED displays. The COP470 can drive the segments directly on small, low current LED
displays as shown in Figure 9. By adding display drivers, large, high current LED displays can be driven as shown in Figure 10.
a.
oo
Example:
COP420 Code to Load COP470
(Display Data Is In Memory 0,12-0,15)
LB10,12
OBD
LOOP: CLRA
LQID
CQMA
SC
XAS
NOP
NOP
LD
XAS
NOP
NOP
RC
XAS
XIS
JP LOOP
SC
CLRA
AISC15
XAS
NOP
CLRA
AISC 12
XAS
NOP
LB10,15
RC
XAS
OBD
; Point to first display data
; Turn CS low (DO)
; Look up segment data
; Copy data from Q to M & A
; Set C to turn on SK
; Output lower 4 bits of data
; Delay
; Delay
; Load A with upper 4 bits
; Output 4 bits of data
; Delay
; Delay
; ResetC
; Turn off SK clock
; Increment B for next data
; Skip this jump after last digit
;SetC
; 15 to A
; Output on time (max brightness)
; 12toA
; Output control bits
; 15 to B
; ResetC
; Turn offSK
; Turn CS high (DO)
6-42
Functional Description
o
o
(Continued)
-C
0I:loo
.......
6.0 TO 9.5V
o
"oo
Vss
-C
(,,)
COP420L
.......
o
so
01
SK
SK
COP470
DO
Voo
·Segment buffer
VGG
TL/DD/61S4-10
may be added for larger display.
FIGURE 9. LED Display
V+
Vee
Vss
4 DIGITS
C0P420
SO
01
SK
SK
00
ES
4 DIGIT
VERY LARGE
LED DISPLAY
(COMMON CATHODE)
COP470
SA", SH
GND
TL/DD/61S4-11
FIGURE 10. Large LED Display
FUTABA 4·BT·D3
- 20 VOLTS
l-7/-7 • l-7/-7
---!.
16 24~Q
H~
l Il I • l Il 1
12 10
B
5
6
3
2 13
~14
11
7
4
9L
*
+5 V10LTS
A
DO
COP420
SO
SK
B
C
0
E F
G H
01 02 03 04
n
01
VGG
~ ~-2DVD LTS
CDP470
SK
~ +5 VOLTS
Voo
..L
..L
TL/DD/61S4-12
FIGURE 11. Sample V.F. System
6·43
. .----------------------------------------------------------------------------------,
~ ~National
8 D Semiconductor
~
C\I
COP472-3 Liquid Crystal Display Controller
General Description
Features
The COP472-3 Liquid Crystal Display (LCD) Controller is a
peripheral member of the COPSTM family, fabricated using
CMOS technology. The COP472-3 drives a multiplexed liquid crystal display directly. Data is loaded serially and is held
in internal latches. The COP472-3 contains an on-chip oscillator and generates all the multi-level waveforms for backplanes and segment outputs on a triplex display. One
COP472-3 can drive 36 segments multiplexed as 3 x 12
(4% digit display). Two COP472-3 devices can be used together to drive 72 segments (3 x 24) which could be an 8%
digit display.
• Direct interface to TRIPLEX LCD
• Low power dissipation (100 fJ-W typ.)
•
•
•
•
•
•
Low cost
Compatible with all COP400 processors
Needs no refresh from processor
On-chip oscillator and latches
Expandable to longer displays
Software compatible with COP470 V.F. Display
Driver chip
• Operates from display voltage
• MICROWIRETM compatible serial lID
• 20-pin Dual-In-Line package
Block Diagram
BPA BPa BPc
12 SEGMENT BUFFERS
12
Voo
GND
DI-+-----t
SK-r--------4~-~
~--~----------------------~----------~
TL/DD/6932-1
6-44
o
o"tJ
Absolute Maximum Ratings
Voltage at CS, 01, SK pins
Voltage at all other Pins
-0.3Vto +9.5V
Storage Temperature
Lead Temp. (Soldering, 10 Seconds)
- 0.3V to Voo + 0.3V
Operating Temperature Range
- 65°C to + 150°C
300°C
~
.......
NI
W
O°Cto 70°C
DC Electrical Characteristics
ov, Voo = 3.0V to 5.5V, T A = O°C to 70°C (depends on display characteristics)
GNO =
Parameter
Conditions
Min
Max
Units
3.0
5.5
Volts
Voo=5.5V
250
p.A
Voo=3V
100
p.A
0.7 Voo
0.8
9.5
Volts
Volts
0.6
Voo-0.6
Voo
Volts
Volts
Voo-O.4
Voo
V3 VOO+ll. V
Power Supply Voltage, Voo
Power Supply Current, 100 (Note 1)
Input Levels
OI,SK,CS
VIL
VIH
BPA (as Osc. in)
VIL
VIH
Output Levels, BPC (as Osc. Out)
0.4
VOL
VOH
Volts
Volts
Backplane Outputs (BPA, BPB, BPC)
VSPA, SPS, SPC ON
VSPA, SPS, SPC OFF
During
BP+ Time
Voo-ll.V
% Voo-ll.V
VSPA, SPS, SPC ON
VSPA, SPS. SPC OFF
During
BP- Time
0
ll.V
%Voo-ll.V
% Voo+ll.V
VSEG ON
VSEG OFF
During
BP+ Time
0
% Voo-ll.V
%Voo+ll.V
Volts
Volts
VSEG ON
VSEG OFF
During
BP- Time
Voo-AV
% Voo-ll.V
Voo
%Voo+ll.V
Volts
Volts
Voo
Volts
Volts
Volts
Volts
Segment Outputs (SA1 - SA4)
ll.V
Internal Oscillator Frequency
15
80
kHz
Frame Time (Int. Osc. -;- 192)
2.4
12.8
ms
Scan Frequency (1 ITSCAN)
39
208
Hz
SK Clock Frequency
4
250
kHz
SKWidth
1.7
p.s
1.0
100
p.s
ns
1.0
1.0
p.s
p's
01
Data Setup, tSETUP
Data Hold, tHOLO
CS
tSETUP
tHOLO
Output Loading Capacitance
100
Note 1: Power supply current is measured in stand-alone mode with all outputs open and all inputs at VOO.
Note 2:
~V=O.05VDD'
6·45
pF
•
I
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage at CS, 01, SK Pins
Voltage at All Other Pins
-65°C to + 150"C
Storage Temperature
Lead Temperature
(Soldering, 10 seconds)
300°C
-0.3Vto +9.5V
-0.3V to Voo+0.3V
Operating Temperature Range
- 40°C to + S5°C
DC Electrical Characteristics
av, Voo = 3.0V to 5.5V, TA = -40°C to
GND =
Parameter
+S5°C (depends on display characteristics)
Min
Max
Units
3.0
5.5
Volts
Voo=5.5V
300
p.A
Voo=3V
120
p.A
0. 7Voo
O.S
9.5
Volts
Volts
0.6
Voo-0.6
VOO
Volts
Volts
Voo-0.4
Voo
Volts
Volts
Conditions
Power Supply Voltage, Voo
Power Supply Current, 100 (Note 1)
Input Levels
DI,SK,CS
VIL
VIH
BPA (as Osc. In)
VIL
VIH
Output Levels, BPC (as Osc. Out)
0.4
VOL
VOH
Backplane Outputs (BPA, BPB, BPC)
VBPA, BPB, BPC ON
VBPA, BPB, BPC OFF
During
BP+ Time
Voo-l::.V
%Voo-l::.V
Voo
%Voo+l::.V
Volts
Volts
VBPA, BPB, BPC ON
VBPA, BPB, BPC OFF
During
BP- Time
0
%Voo-I:N
I:N
%Voo+l::.V
Volts
Volts
During
BP+ Time
0
%Voo-l::.V
l::.V
%Voo+l::.V
Volts
Volts
During
BP- Time
Voo-l::.V
%Voo-l::.V
Voo
%Voo+l::.V
Volts
Volts
Segment Outputs (SA1 - SA4)
VSEGON
VSEGOFF
VSEGON
VSEGOFF
Internal Oscillator Frequency
15
SO
kHz
Frame Time (Int. Osc. +- 192)
2.4
12.S
ms
Scan Frequency (1fTSCAN)
39
20S
Hz
SK Clock Frequency
4
250
kHz
SKWidth
1.7
p.s
1.0
100
p.s
ns
1.0
1.0
p.s
p's
01
Data Setup, tSETUP
Data Hold, tHOLO
CS
tSETUP
tHOLO
Output Loading Capacitance
100
1: Power supply current is measured in stand-alone mode with all outputs open and all inputs at Voo.
Note 2: AV = 0.05 Voo.
Note
6-46
pF
Dual-In-Llne Package
~
Voo
GNO
01
10
11
Description
CS
SA4
SA3
SCl
BPB
BPC
BPA
SK
SC4
SC2
SAl
SBl
SC3
SB3
SA2
SB4
SB2
Pin
Chip select
Power supply (display voltage)
Ground
Serial data input
Serial clock input
Display backplane A (or oscillator in)
Display backplane B
Display backplane C (or oscillator out)
12 multiplexed outputs
Voo
GND
01
SK
BPA
BPs
BPc
SA1-SC4
.TL/DD/6932-2
Top View
Order Number COP472MW-3 or COP472N-3
See NS Package Number M20A or N20A
FIGURE 2. Connection Diagram
_II_~SETUP
cs ---,SK WIDTH
I-
r-
I
I I
TL/DD/6932-3
FIGURE 3. Serial Load Timing Diagram
OSC
Voo
BPA :::
o
Voo
BPB
'I.'II
o
Voo
BPC
:;:~~~
o
Voo
'I.
SEGMENT '11
o
TL/DD/6932-4
FIGURE 4. Backplane and Segment Waveforms
SC1
LJ:3:;1
F
G
B
I:T:I
L..._ _ _-<)
BPB
lit
SP
FIGURE 5. Typical Display Internal Connections
Epson LD-370
6-47
TLlDD/6932-5
0
0
"'C
~
.......
N
w•
Functional Description
The COP472-3 drives 36 bits of display information organized as twelve segments and three backplanes. The
COP472-3 requires 40 information bits: 36 data and 4 control. The function of each control bit is described below.
Display information format is a function of the LCD interconnections. A typical segment/backplane configuration is illustrated in Figure 5, with this configuration the COP472-3 will
drive 4 digits of 9 segments.
SEGMENT DATA BITS
Data is loaded in serially, in sets of eight bits. Each set of
segment data is in the following format:
I SA I
To adapt the COP472-3 to any LCD display configuration,
the segment/backplane multiplex scheme is illustrated in
Table I.
Two or more COP472-3 chips can be cascaded to drive
additional segments. There is no limit to the number of
COP472-3's that can be used as long as the output loading
capacitance does not exceed specification.
Bit Number
1
2
3
4
5
6
7
8
SA1, BPC
SB1, BPB
SC1, BPA
SC1, BPB
SB1, BPC
SA1, BPB
SA1, BPA
SB1, BPA
SH
SG
SF
SE
SO
SC
SB
SA
9
10
11
12
13
14
15
16
SA2, BPC
SB2, BPB
SC2, BPA
SC2, BPB
SB2, BPC
SA2, BPB
SA2, BPA
SB2, BPA
SH
SG
SF
SE
SO
SC
SB
SA
Digit 2
17
18
19
20
21
22
23
24
SA3, BPC
SB3, BPB
SC3, BPA
SC3, BPB
SB3, BPC
SA3, BPB
SA3, BPA
SB3, BPA
SH
SG
SF
SE
SO
SC
SB
SA
Digit 3
25
26
27
28
29
30
31
32
SA4, BPC
SB4, BPB
SC4, BPA
SC4, BPB
SB4, BPC
SA4, BPB
SA4,BPA
SB4, BPA
SH
SG
SF
SE
SO
SC
SB
SA
Digit 4
33
34
35
36
37
38
39
40
SC1, BPC
SC2, BPC
SC3, BPC
SC4, BPC
not used
06
07
SYNC
SPA
SP2
SP3
SP4
Digit 1
Digit 2
Digit 3
Digit 4
I
SC
I
SO
I
SE
I
SF
I
SG
I
SH
I
CONTROL BITS
The fifth set of 8 data bits contains special segment data
and control data in the following format:
I SYNC I 07 I 06 I X I SP4 I SP3 I SP2 I SP1 I
TABLE I. COP472·3 Segment/Backplane
Multiplex Scheme
Segment,
Backplane
SB
Data is shifted into an eight bit shift register. The first bit of
the data is for segment H, digit 1. The eighth bit is segment
A, digit 1. A set of eight bits is shifted in and then loaded into
the digit one latches. The second set of 8 bits is loaded into
digit two latches. The third set into digit three latches, and
the fourth set is loaded into digit four latches.
The first four bits shifted in contain the special character
segment data. The fifth bit is not used. The sixth and seventh bits program the COP472-3 as a stand alone LCD driver or as a master or slave for cascading COP472-3's. BPC
of the master is connected to BPA of each slave. The following table summarizes the function of bits six and seven:
Data to
Numeric Display
07
Digit 1
06
Function
Slave
o
o
Stand Alone
o
Not Used
o
Master
BPC Output
BPA Output
Backplane
Output
Backplane
Output
Internal
Osc. Output
Internal
Osc. Output
Oscillator
Input
Backplane
Output
Oscillator
Input
Backplane
Output
The eighth bit is used to synchronize two COP472-3's to
drive an 8%-digit display.
6-48
~----------------------------------------------------------------------'O
o"'C
LOADING SEQUENCE TO DRIVE A 4%-DIGIT DISPLAY
Steps:
1. Turn CE low.
2. Clock in 8 bits of data for digit 1.
3. Clock in 8 bits of data for digit 2.
4. Clock in 8 bits of data for digit 3.
5. Clock in 8 bits of data for digit 4.
~
.......
N
W
•
6. Clock in 8 bits of data for special segment and control
function of SPC and BPA.
I
I
0
0
I
1
I
1
I
SP4
I
SP3
I
SP2
I
SP1
I
Vee
7. Turn CS high.
Note: CS may be turned high after any step. For example to
load only 2 digits of data, do steps 1, 2, 3, and 7.
CS must make a high to low transition before loading data in
order to reset internal counters.
C0P420
LOADING SEQUENCE TO DRIVE AN
8%-DIGIT DISPLAY
Two or more COP472·3's may be connected together to
drive additional segments. An eight digit multiplexed display
is shown in Figure 7. The following is the loading sequence
to drive an eight digit display using two COP472·3's. The
right chip is the master and the left the slave.
Steps:
1. Turn CS low on both COP472·3's.
2. Shift in 32 bits of data for the slave's four digits.
3. Shift in 4 bits of special segment data: a zero and three
ones.
I
1
4.
5.
6.
7.
1
I
1
I
0
I
SP4
I
SP3
I
SP2
I
SP1
so
SK
GNO
I
0
I
0
I
1
I
SP4
I
SP3
I
SP2
I
SP1
DISPLAY
VOLTAGE
TLIOO/6932-6
FIGURE 6. System Diagram - 4% Digit Display
I
This synchronizes both the chips and BPA is oscillator
input. Both chips are now stopped.
Turn CS high to both chips.
Turn CS low to master COP472·3.
Shift in 32 bits of data for the master's 4 digits.
Shift in four bits of special segment data, a one and
three zeros.
o
DO
.-----1
.-----1
~----IL-_....-_""
Vee
Voo
Voo
I
C0P420
SO~--~~~--~
This sets the master COP472·3 to SPA as a normal
backplane output and BPC as oscillator output. Now
both the chips start and run off the same oscillator.
8. Turn CS high.
The chips are now synchronized and driving 8 digits of dis·
play. To load new data simply load each chip separately in
the normal manner, keeping the correct status bits to each
COP472·3 (0110 or 0001).
SK~---~r------I
GND
DO . - - - - - - '
01 ~-----------I
TL/OO/6932-7
FIGURE 7. System Diagram - 8% Digit Display
6·49
~
•
t;
,------------------------------------------------------------------------------,
Example Software
~
Example 1
o
COP420 Code to load a COP472-3 [Display data is in M(O, 12)-M(O, 15), special segment data is in M(O, 0)]
LOOP:
LBIO,12
OBD
CLRA
LOID
COMA
SC
XAS
NOP
NOP
LD
XAS
NOP
NOP
RC
XAS
XIS
JPLOOP
SC
LBIO,O
LD
XAS
NOP
CLRA
AISC12
XAS
NOP
LBIO,15
RC
XAS
OBD
; POINT TO FIRST DISPLAY DATA
; TURN CS LOW (DO)
; LOOK UP SEGMENT DATA
; COPY DATA FROM 0 TO M & A
; SET C TO TURN ON SK
; OUTPUT LOWER 4 BITS OF DATA
; DELAY
; DELAY
; LOAD A WITH UPPER 4 BITS
; OUTPUT 4 BITS OF DATA
; DELAY
; DELAY
; RESETC
; TURN OFF SK CLOCK
; INCREMENT B FOR NEXT DATA
; SKIP THIS JUMP AFTER LAST DIGIT
;SETC
; ADDRESS SPECIAL SEGMENTS
; LOAD INTO A
; OUTPUT SPECIAL SEGMENTS
; 12 to A
; OUTPUT CONTROL BITS
; 15 to B
; RESETC
;TURNOFFSK
; TURN CS HIGH (DO)
6-50
Example Software (Continued)
Example 2
COP420 Code to load two COP472-3 parts [Display data is in M(O, 12)-M(0, 15) and M(1, 12)-M(1, 15), special segment data
is in M(O, 0) and M(1, 0))
INIT:
LBI
OBD
LEI
RC
XAS
LBI
STII
LBI
JSR
MAIN DISPLAY SEQUENCE
DISPLAY
LBI
STII
LBI
JSR
LBI
STII
LBI
JSR
OUTPUT SUBROUTINE
OUT:
OBD
CLRA
AISC
CAB
LOOP
CLRA
LOID
COMA
SC
XAS
NOP
NOP
LD
XAS
NOP
NOP
RC
XAS
XIS
JP
SC
NOP
LD
XAS
NOP
LBI
LD
XAS
NOP
NOP
RC
XAS
OBD
RET
0, 15
8
; TURN BOTH CS'S HIGH
; ENABLE SO OUT OF S. R.
3,15
7
0,12
OUT
; TURN OFF SK CLOCK
; USE M(3, 15) FOR CONTROL BITS
; STORE 7 TO SYNC BOTH CHIPS
; SET B TO TURN BOTH CS'S LOW
; CALL OUTPUT SUBROUTINE
3,15
8
0, 13
OUT
3,15
6
1,14
OUT
; SET CONTROL BITS FOR SLAVE
; SET B TO TURN SLAVE CS LOW
; OUTPUT DATA FROM REG.
°
; SET CONTROL BITS FOR MASTER
; SET B TO TURN MASTER CS LOW
; OUTPUT DATA FROM REG. 1
; OUTPUT B TO CS'S
12
; 12TOA
; POINT TO DISPLAY DIGIT (BD = 12)
; LOOK UP SEGMENT DATA
: COPY DATA FROM 0 TO M & A
; OUTPUT LOWER 4 BITS OF DATA
; DELAY
; DELAY
; LOAD A WITH UPPER 4 BITS
; OUTPUT 4 BITS OF DATA
; DELAY
; DELAY
; RESETC
;TURN OFFSK
; INCREMENT B FOR NEXT DISPLAY DIGIT
; SKIP THIS JUMP AFTER LAST DIGIT
;SETC
LOOP
; LOAD SPECIAL SEGS. TO A (BD = 0)
; OUTPUT SPECIAL SEGMENTS
3,15
; LOAD A
; OUTPUT CONTROL BITS
;TURNOFFSK
; TURN CS'S HIGH (BD= 15)
6-51
0)
0)
C")
D.
oo ~National
.......
0)
0)
~ Semiconductor
~
D.
oo COP498/COP398 Low Power CMOS RAM
....... and Timer (RATTM)
co
COP499/COP399 Low Power CMOS Memory
D.
oo
0)
C")
.......
co
0)
~
D.
oo
General Description
Features
The COP498/398 Low Power CMOS RAM and Timer (RAT)
and the COP499/399 Memory are peripheral members of
the COPSTM family, fabricated using low power CMOS technology. These devices provide external data storage and/or
timing, and are accessed via the simple MICROWIRETM serial interface. Each device contains 256 bits of read/write
memory organized into 4 registers of 64 bits each; each register can be serially loaded or read by a COPS controller.
• Low power dissipation
• Quiescent current = 40 nA typical (25°C, Vee = 3.0V)
The COP498/398 also contain a crystal-based timer for
timekeeping purposes, and can provide a "wake-up" signal
to turn on a COPS controller. Hence, these devices are
ideal for applications requiring very low power drain in a
standby mode, while maintaining a real-time clock (e.g.,
electronically-tuned automobile radio). Power is minimized
by cycling controller power off for periods of time when no
processing is required.
The COP499/399 contain circuitry that enables the user to
turn a controller on and off while maintaining the integrity of
the memory.
•
•
•
•
•
•
•
•
•
•
•
Low cost
Single supply operation (2.4V-5.5V)
CMOS-compatible I/O
4 x 64 serial read/write memory
Crystal-based selectable timer-2.097152 MHz or
32.768 kHz (COP498/398)
Software selectable 1 Hz or 16 Hz "wake-up" signal
for COPS controller (COP498/398)
External override to "wake-up" controller
Compatible with all COP400 processors (processor
Vee ~9.5V)
MICROWIRE-compatible serial I/O
Memory protection with write enable and write disable
instructions
14-pin Dual-In-Line package (COP498/398) or 8-pin
Dual-In-Line package (COP499/399)
A COP400 series N-channel microcontroller coupled with a
COP498 (or 499) RAM/Timer offers a user the low-power
advantages of an all CMOS system and the low-cost advantage of an NMOS system. This type of system is ideally
suited to a wide variety of automotive and instrumentation
applications.
Block Diagram
SK
Dse
-t-+--.......-~I
XDUT
......---+-------.,,..... 1Hz
eE
-r--"1-~
DI -r-----~--~--r---~
L-..----Ir-
ON
~-----------------+_DD
Vee
P
GND
TLlDD/66B4-1
FIGURE 1
6-52
(')
o
Absolute Maximum Ratings
""C
,a::..
Voltage relative to GND
At XSEL, 1 Hz, XIN, XOUT, DO
At all other pins
Ambient Storage Temperature
Lead Temp. (Soldering, 10 seconds)
-0.3V to Vee +0.3V
-0.3V to 10V
Maximum Vee Voltage
Power Dissipation
15 mA
Total Source Current Allowed
10mA
Ambient Operating Temperature
COP398/COP399
- 40°C to + 85°C
COP498/COP499
O°Cto +70°C
(Q
Q)
300°C
........
50mW
o
Note: "Absolute maximum ratings" indicate limits beyond
which damage to the device may occur. DC and AC elect,;cal specifications are not insured when operating the device
at absolute maximum ratings.
6.5V
Total Sink Current Allowed
- 65°C to + 150°C
(')
""C
W
(Q
Q)
........
(')
o""C
,a::..
(Q
(Q
........
(')
o""C
DC Electrical Characteristics
W
COP398/COP399: - 40°C :::;: T A :::;: + 85°C unless otherwise specified.
(Q
(Q
COP498/COP499: QOC :::;: T A:::;: + 70°C unless other wise specified.
Parameter
Conditions
Operating Voltage
COP498/COP499
COP398/COP399
Quiescent Current
All inputs at GND
(COP398/COP399 only)
COP498/COP398
Standby Current (sleep mode)
(running with crystal
Operating Current
COP499/COP399 Operating Current
Input Voltage Levels
CE Input
Logic High (VIH)
Logic Low (VIU
OVA Input
Logic High (VI H)
Logic Low (VIU
All Other Inputs
Logic High (VIH)
Logic Low (VIU
Output Voltage Levels-DO, 1 Hz
CMOS Operation
Logic High (VOH)
Logic Low (Vou
TA
TA
TA
TA
TA
TA
TA
TA
TA
=
=
=
=
=
=
=
=
=
25°C,
25°C,
25°C,
70°C,
70°C,
70°C,
85°C,
85°C,
85°C,
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
=
=
=
=
=
=
=
=
=
Min
Max
Units
2.4
3.0
5.5
5.5
V
V
1.0
3.0
6.0
4.0
10
20
8.0
16
30
p.A
p.A
p.A
p.A
p.A
p.A
p.A
p.A
p.A
200
700
20
100
p.A
p.A
p.A
p.A
300
920
120
320
p.A
p.A
p.A
p.A
100
140
250
p.A
p.A
p.A
OAVee
V
V
0. 2Vee
V
V
0. 3Vee
V
V
0.1
V
V
3.0V
5.0V
5.5V
3.0V
5.0V
5.5V
3.0V
5.0V
5.5V
Vee = Min., Osc. = 2.097 MHz
Vee = Max., Osc. = 2.097 MHz
Vee = Min.,Osc. = 32.768 kHz
Vee = Max.,Osc. = 32.768 kHz
SK = 250 kHz square wave
Vee = Min.,Osc. = 2.097 MHz
Vee = Max.,Osc. = 2.097 MHz
Vee = Min.,Osc. = 32.768 kHz
Vee = Max.,Osc. = 32.768 kHz
SK = 250 kHz square wave
Vee = 2.4V for COP498/COP499
Vee = 3.0V for COP398/COP399
Vee = Max.
(Schmitt Trigger Input)
0. 8Vee
(Schmitt Trigger Input)
0. 8Vee
0. 7Vee
IOH
IOL
=
=
Vee- 0.1
-10 p.A
10 p.A
6-53
•
CD
CD
C"')
Q.
oo
DC Electrical Characteristics
Parameter
.......
CD
CD
"'1::1'
Q.
oo
.......
(Continued)
Conditions
Input Leakage Current
COP498/COP499, VIH =
COP398/COP399, VIH =
COP498/COP499, VH =
COP398/COP399, VH =
TRI-STATE®, Open Drain
Leakage Current
Vee, VIL = OV
Vee, VIL = OV
Vee, VL = OV
Vee, VL = OV
Min
Max
Units
-1.0
-2.0
-2.5
-5.0
+1.0
+2.0
+2.5
+5.0
Jl-A
Jl-A
Jl-A
Jl-A
8.5
rnA
rnA
rnA
ClC)
CD
C"')
Q.
o
o.......
ClC)
CD
"'1::1'
Q.
o
o
Output Current Levels
Sink Current
OSC
ON
Vee = 4.5V
XOUT
XOUT
1 Hz, DO
Source Current
ON
XOUT
XOUT
1 Hz, DO
VOL = O.4V
VOL = 1.5V
XSEL = 1, XIN = 4.5V, VOL = 1.0V
XSEL = 0, XIN = 4.5V, VOL = 2.0V
VOL = 0.8V
0.5
1.5
0.25
8.0
0.8
VOH = 1.0V
XSEL = 1, XIN = OV, VOH = 3.0V
XSEL = 0, XIN = av, VOH = 3.0V
VOH = 2.0V
60
0.27
10
0.4
Jl-A
rnA
Jl-A
rnA
Jl-A
rnA
AC Electrical Characteristics
COP398/COP399: - 40°C
COP498/COP499: O°C
~
~
TA
TA
~
~
+ 85°C unless otherwise specified.
+ 70°C unless otherwise specified.
Conditions
Min
Max
Units
CS = 1, CE = 1 COP498/COP499
CS = 1, CE = 1 COP398/COP399
SK frequency ~ 25 kHz
SK frequency = 4.096 kHz
4.096
8.192
25
48
250
250
75
52
kHz
kHz
%
%
Parameter
COP Interlace
SK Frequency
SK Duty Cycle
Inputs
CS
tess
tesH
01
tSETUP
tHOLD
Output
DO
t pd1, tpdO
tpd1, tpdO
Crystal Osc. Frequency
CL = 100 pF, 4.5V ~ Vee
VOUT = 1.5V
CL = 50 pF, Vee = Min.,
VOUT = 1.5V
~
0.2
0
Jl-s
Jl-s
0.4
0.4
Jl-s
Jl-s
5.5V,
XSEL = 1
XSEL = 0
SK~
I
-IISETupIIHOLOI- I
Ol~_
00
~ilJ
j_I'VOH
-llcssl-
-
-IICSHj-
~:B
TL/DD/66B4-2
FIGURE 2. Synchronous Data Timing
6-54
2.0
Jl-s
2.4
Jl-s
2.1
65
MHz
kHz
o
o""C
Connection Diagrams
~
co
Dual-In-Llne Package
CE- 2
14 -Vcc
13 -osc
SK- 3
12 -XOUT
CS-1
DI- 4
00- 5
~g~~~
11 -
XIN
10 -OVR
(X)
........
o
8 I-- Vcc
CE- 1
XSEL- 6
9-ifN
SK 01 -
GNO- 7
81--1 Hz
DO -
Order Number COP398N, COP498N,
COP399N, or COP499N
See NS Package Number
N08Eor N14A
2 COP499 7 I-- OVR
3 C0P399 6 I-- ON
4
o
""C
W
co
co
Pin
Description
CS
Chip Select
Description
1 Hz
1 Hz Square Wave Output
CE
Chip Enable
ON
SK
Serial Data Clock
Active Low Wake-Up Signal to COPS
Controller
OVR
External Override Wake-Up for COPS
Controller
OSC
Open Drain Oscillator Output
Vee
Power Supply
GND
Ground
DI
Serial Data Input
DO
Serial Data Output
XSEL
Crystal Option Select
XIN
Crystal Oscillator Input
XOUT
Crystal Oscillator Output
COP398 and COP399 are extended temperature devices (-40°C to + 85°C) of COP498 and COP499 (O°C to 70°C) respectively, with all other functional and electrical characteristics being the same. Therefore, no further attempt will be made to distinguish
between COP498 and COP398 or between COP499 and COP399. Unless otherwise specified, the following descriptions will
apply to both COP498 and COP499, and they will be known as the device.
INSTRUCTION SET
COP498 has six instructions as indicated in Figure 4. Note
that the MSB of any given instruction is a "1". This bit is
properly viewed as a start bit in the interface sequence. The
lower 4 bits of the instruction contain the command for the
device. One of the instructions (TSEC) should not be used
in COP499 as it serves no purpose.
Instruction Opcode
Comments
voltage it is a logic "0". The COP498 can execute six instructions: READ (from anyone of 4 registers in memory);
WRITE (to anyone of 4 registers in memory); WREN (write
enable); WRDS (write disable); TSEC (test and reset timer
seconds latch); and SLEEP (drive ON signal high to turn off
COPS controller). The COP499 can execute all the above
instructions except TSEC. All communications with the device are via the serial MICROWIRE interface. Both CS and
CE (CE only in COP499) must be high to enable the device.
The device must be deselected between instructions - either CS and/or CE must go low to insure proper operation.
The deselecting of the device resets the counters and serial
input register.
MSB
SLEEP
o
o
Pin Descriptions
WREN
WRDS
TSEC
o
~
FIGURE 3
READ
........
co
co
........
TL/DD/66B4-3
WRITE
W
co
(X)
""C
5 I-- GND
Top View
Pin
o""C
s=ON (wake up signal) frequency select 1 = 16 Hz, 0 = 1 Hz
(s selection for COP498 only)
(s = a for COP499)
1 1 0 r1 ro r1, rO = register number (00,
01,10,11)
1 0 0 1 1 Write enable
1 0 0 0 0 Write disable
1 00 1 0 Test timer seconds latch
(COP498 only)
1 0 0 0 1 Put COPS controller to
sleep (ON high)
FIGURE 4. Instruction Set
READ/WRITE MEMORY
The device has 256 bits of read/write memory. The memory
is organized as 4 registers of 64 bits each. The data is accessed serially through the Data input (DI) and Data Output
(DO) pins. SK is the clock signal for data and instructions.
The memory address register can be conceived of as two
registers: one two bits long and loaded directly from the
instruction; the other six bits long and incremented by 1 with
each SK pulse as long as the chip is selected. The two bit
register does not change during the execution of a given
instruction. The six bit register is reset to zero while the
device is deselected. When counting, the six bit register
wraps around from its maximum value back to zero. Thus
memory locations are addressed relative to the number of
SK pulses after the chip is selected.
Functional Description
A block diagram of COP498 and COP499 is given in Figure
1. Positive logic is used. When a bit is set to the higher
voltage it is a logic "1"; when a bit is reset to the lower
6-55
Q)
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......
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~
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oo
......
co
Q)
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D..
oo
......
co
Q)
~
D..
o
o
Functional Description
(Continued)
crystal input. For proper operation, the state of XSEL should
not be changed while the device is in operation. If the oscillator and timer features are not used, the XIN pin should be
connected to the GND pin and XSEL tied to Vee. If the
override feature is not used the OVR pin should be connected to the GND pin.
The READ instruction will select one of the 4 registers (the
register being identified in the instruction opcode as indicated in Figure 4) and output the contents of that register to the
DO pin until the device is deselected. Note that data output
from the device, as a result of a READ instruction, continues
as long as the device is selected and clocks are provided.
Reading more than 64 bits will cause rereading of some bits
as the memory address register wraps around from the
maximum value back to zero.
The device is in a static mode when either the CS or CE pin
is low. However, the device is in a dynamic mode when both
CS and CE are high and at least one high level has been
detected at SK while both pins are high. Because of this, a
minimum frequency is specified for the SK clock. This minimum frequency really translates to maximum on and off
times for the SK clock. As the SK clock slows down, the
duty cycle must get closer to 50%. For best operation, the
user should regard the maximum on and off times for the SK
clock as about 122 !J-s (61 !J-s for COP398/COP399).
The WRITE instruction selects one of the 4 registers (the
register being identified in the instruction opcode as indicated in Figure 4) and takes the data from the DI pin and stores
that data into the memory register until the device is deselected. The write Operation continues as long as the device
is selected and clocks are provided. Thus writing more than
64 bits will cause a portion of the data to be overwritten.
TIMER (COP498 ONLY)
COPS CONTROLLER TO COP498/COP499
HARDWARE INTERFACE
With the XSEL pin tied high (Vee), the timer is a 21 stage
counter which can divide a 2.097152 MHz signal down to 1
Hz. This creates the 1 Hz signal output. With XSEL tied low
(ground), the timer is a 15 stage counter which divides a
32.768 kHz signal down to create the 1 Hz signal output.
The rising edge of the 1 Hz signal is used internally to set
the timer seconds latch. A wake-up signal is generated at
the ON output. This signal can be used to turn a COPS
controller on. The wake-up rate is software selectable and
may be either 1 Hz or 16 Hz. A bit in the WRITE instruction
controls this wake-up rate (see Figure 4). By means of the
SLEEP instruction a COPS controller may cause the ON
signal to go high thereby providing a means for the controller to safely turn itself off.
An override capability is present whereby the ON pin may
be prevented from going high. A "1" level at the OVR pin
will force ON to go low (or stay low) thereby causing the
controller to turn on or remain on. ON will remain low, and
the controller on, as long as the OVR pin is high. To preserve timekeeping when using the override feature, a timer
seconds latch is provided. This latch is set by the rising
edge of the 1 Hz signal and is read and reset by the TSEC
instruction. The timer seconds latch is primarily intended for
use when the override feature is implemented. However, it
does provide a convenient one second timer which is software testable over a common serial port.
If the COPS controller is operating with a 4 !J-s instruction
cycle time, a 47k resistor should be connected between SK
and Vee to speed up the rise time of the SK clock. If the
override feature is used in COP498, the override signal
should be connected to the OVR pin of the COP498 and an
input of the COPS controller. This is simply to provide a
means for the controller to know if it was turned on by override or normal timeout. The override signal should be free of
noise. In systems where the COPS controller is operating
with Vee greater than 6 volts, SI and the override input on
the controller should have high impedance, standard TTL
level input options selected. To minimize current drain in the
controller, the override input to the controller should always
use the high impedance option.
Figure 6a illustrates the COP498 interface in a system with
supply voltage less than 6 volts. The COPS controller can
either be turned on by the timer or an external signal. A PNP
transistor, controlled by the ON signal of the COP498, is
used to gate the power to the COPS controller. A 0.05 !J-F
capacitor is connected across the supply pins of the controller to reduce voltage variations due to current spikes. It is
not recommended to use large capacitance values here as
problems can be introduced if the power supply fall time is
too long. The switched supply fall time should be kept to
about ten instruction cycles of the COPS processor. Resistor R2, between the ON pin of the COP498 and the base of
the transistor, is used to limit current. Resistor R1, between
the base and emitter of the transistor, is used to turn the
transistor off when ON is high. The CE pin of the COP498 is
tied to the Vee pin of the controller. This guarantees that
the controller is at its full operating voltage before the
COP498 can be accessed. When turned on, the PNP transistor should be saturated in order to minimize the voltage
drop across it. The system power supply, which here is Vee
to the COP498, must be high enough to insure that the controller Vee - which is the system supply less the voltage
drop across the PNP transistor - is high enough to be recognized as a logic "1" at the CE input of the COP498. It is
also desirable to have all input signals to the COP498 as
close as possible to the COP498 supply levels to eliminate
any static power drain which could significantly increase
standby and operating current.
SYSTEM CONSIDERATIONS
When the COPS processor is being turned on and off, during the power supply transition between ground and operating voltage, some pulses may occur at the output pins of the
processor. By using the WRDS and WREN instructions, together with the higher "1" level of the CE pin, accidental
writing into the memory may be prevented. This is done by
disabling the write operation before going to sleep and enabling the write operation when the COPS processor starts
execution. A WRDS instruction is automatically executed if
the SLEEP instruction causes ON to go high turning off the
COPS processor. Furthermore, WREN instruction is disabled as long as ON remains high.
The XSEL pin, which identifies the timer counter length,
should be tied to either Vee or ground depending on the
6-56
o
-a
~
o
Typical Performance Curves
CD
Maximum Quiescent
Current
COP498/499/398/399
Minimum Sink Current
for DO, 1 Hz, OSC, ON
3D
SOD
---osc, ON ONLY
~ 25~-+--4---~-+--~~
ig::~~--+-~~-+--~~
...
:;
10~-+--+---r-~~~~
"i
E
1
400
""
CD
......
o
o-a
I
I
z
§
o
o-a
CD
600 I--t---.::!"k:--t---t---t---t
c
CD
......
(,)
VCC-5.5V
I
g
Minimum Source Current
for 00,1 Hz
r---.,.......:..-.--,.----r--.---.
~
CD
"j' 200
I--+--+--+-:ttt--'~---l
5~-+--4---~~
CD
......
o
o
-a
(,)
2
4
VOUT-V
"1
...zI
Vour- v
VOUT-V
Maximum Standby
Current for COP498/398
CD
CD
4
4
Maximum Sink Current
for ON
Minimum Source Current
for ON
400 r----r-..,--r-"'"'T-.....--,
600 ~-+--+-
300 I--+--+--+--+--+---l
"1
<
....
E
8a: 400
1:l
>-
§
I
III
.......I
10
a:
::>
c
en
I
CI
~ 200
4
Maximum COP498/398
Operating Current
1000
r----.,.--........--..--~--........---,
"i
I 750
i6
Vour V
VOUT-V
Vcc - v
XOUT Minimum Sink
Current with XSEL = 1
1.00 r----r--..,.--,---,...-..,.-----,
XOUT Minimum Source
Current with XSEL = 1
.S r----r-..,.----,--,---,---,
.75 1---+--4--f--::"'+--"I""''--I
.6~-+~~--t_-+--_f_~
~
~
500 1--+__+--4_
'"z
.50
~-+---I-:."c:-~-+---+---i
§
~
~ 250 t-::~=~::;::::::I-""'~=-+----t
100
.25 I--H'-_f_--t_-t--_f_---i
300
4
Your v
SK FREQUENCY - kHz
Maximum COP499/399
Operating Current
VOUT V
XOUT Minimum Sink
Current with XSEL = 0
XOUT Minimum Source
Current with XSEL = 0
40r--+---t---+--+--~~
"i
I
~
...
a:
-
""
z
§
200
'"
~
"i
3D
Vcc .. 5.5V
I
z
~
30~-+---+---t_-t--_f_---i
300~-+--~--~-+--~-4
201--+---+---~~~~+----i
.......
a:
~
20~~~~~k--+--4--1
"j'
100
10
CI
100
6.
200
SK FREQ - kHz
VOUT-V
6-57
VOUT-V
TL/DD/6684-4
m
m
C'f)
Q.
o
Functional Description
o
......
m
m
"II:t'
Q.
o
o
......
WRITE
co
m
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(Continued)
1:----'
L
1 - WRITE INSTRUCTION - I - - - D A T A (64 BITS I ----I
DI
~
----_.... l S l r l r o
Q.
o
SK
o
......
co
m
Q.
o
1--- READ INSTRU~CTlON-=I
1 \ 0 I " X '0 \
..
u
Dol~~-_-_-_-_-_~~-_~-_-_-_T_RI_.S_TA_TE"'_-_-_-_-_-_-_-_-_-_-_-_:L-__.L.C_D_AT-{A
s=b-
01 _ _ _ _ _ _....1 1
"II:t'
READ
o
L
CS
WREN
WROS
SLEEP
1
SK
CS
-----'
DI _ _ _ _ _ _
--'~~_O_ _O_~~_X
__,\_X~_ _ _ _ __
TL/DD/6684-5
FIGURE 5a. Instruction Timing
SK
CS
DI _ _ _ _ _ _ _ _ _ _~~~O_ _O--'~~O______________
s~~~rl~~ {
U
00 --------TRI.STATE'" _ _ _ _ _ _ _
IF LATCH
IS SET
DO
----------------------------~
TL/DD/6684-6
FIGURE 5b. TSEC Instruction Timing
V·
V·
B.2k
DO CKI
Vee
SI
SO
SK
C0P420
GND
TL/DD/6684-8
FIGURE 6b. COP499-COP420 Interface
TL/DD/6684-7
FIGURE 6a. COP498-COP420 Interface
6-58
o
Functional Description
o"'tJ
(Continued)
Figure 6b illustrates the COP499 interface in a system with
a supply voltage less than 6 volts. The COPS processor is
being turned on by a switch (or an external signal) connected to the OVA pin.
once a second. Assume that the COP420 need 10 ms for
internal reset and 10 ms to update all the necessary information, then the COP420 will be turned on for 20 ms every
second, i.e., a duty cycle of 2%; and the COP498 will be in
operating mode for at most 10 ms, i.e., a duty cycle of less
than 1 %. Because of the short duty cycle, it is further assumed that the COP498 current drain will be that of standby
current, about 75 IlA at 5V. The current drain through the
base of the switching transistor that turns on the COP420
can be estimated by the voltage drop across the current
limiting resistor and in this case is assumed to be 3.5 mA.
Figure 7 illustrates a COP498 interface in a system with a
supply voltage greater than 6 volts. In such a system, the
COP498 cannot be connected directly across the system
supply. The power to the COP498 is derived from the system supply by means of a standard zener diode arrangement. A zener diode with a breakdown of about 5 volts is
recommended. A capacitor is connected across the
COP498 supply pins to reduce voltage variations due to current spikes and to supply extra current when the COP498 is
in active operation. Here it is assumed that the COP498 is in
standby mode, i.e., deselected, most of the time and is active, selected, for a short period (less than 100 SK periods).
COP498 current drain = 75 IlA
COP420 current drain=0.02x25 mA=500 IlA
Switching transistor base current=0.02x3.5 mA=70 IlA
Total system current drain = 500 + 70 + 75 IlA = 645 IlA
The result shows that it is possible to achieve the low cost
of NMOS and low power dissipation of CMOS simUltaneously with a system consisting of a COP498 and a COPS processor.
The zener diode series resistor A3 should be selected to
meet the current requirements of the zener diode and the
standby current of the device. The primary purpose of the
zener diode is to place an upper limit on the value of Vee to
the device. This insures that Vee to the device will not exceed the specified maximum value. Since the device will
operate from 2.5V to 6.0V, the choice of zener diode and
series resistor is not critical.
COPS CONTROLLER - COP498/398 SOFTWARE
INTERFACE
Figure 8 shows a typical flow chart for a COP498 or
COP499 interface to a COPS microcontroller system. This
flow chart also illustrates the override feature. Since the
override feature is being used, the first step is to inquire the
device if it is necessary to increment the time. It is assumed
that timekeeping is a necessary part of the application. This
interrogation of the device is accomplished by means of the
TSEC instruction which dumps the contents of the timer
seconds latch to the serial output port and resets the latch.
If the latch was set, the time must be incremented. This is
accomplished by reading the appropriate memory register
into the controller, incrementing the time and writing the register back out to the device. The next step is to check for
the override signal. If it is present a special override routine
may be performed. If no override is present, the controller
Note that the user may generate the two supply voltages in
any manner compatible with system requirements.
Because the COPS controller and the device have different
operating voltages, the high impedance standard TTL level
input should be selected on the COPS controller for SI and
any other input to the controller from the device.
SAMPLE SYSTEM CURRENT DRAIN CALCULATION
Suppose a 5V system consists of a COP420 and a COP498
with a 32.768 kHz crystal. The COP420 is being turned on
Vs
Rl
22k
I~F
~
R2
ON
CE
Uk
~0.05~F
DD
SI (HIGH Zl
SO COP420L
SK
'VALUE DEPENDS ON TYPE
OF CRYSTAL
f
~
OR
3
10k
3
10k
-:
VS
Vs
Vs
LM103H·5.1
)
-: PN5130
220K
OR
6V
ZENER
DIODE
DR EQUIVALENT
TLlDD/6684-10
FIGURE 8. Typical COP498 Interface Flowchart
TL/DD/6684-9
FIGURE 7. COP498-COP420L Interface
with Vs = 9V and 32.768 kHz Crystal
6-59
~
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......
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CD
Q)
......
o
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CD
CD
......
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W
CD
CD
G)
G)
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D-
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G)
•DO
o......
G)
G)
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D-
O
o
......
G)
G)
•D-
O
o
Functional Description
(Continued)
turns itself off by sending a SLEEP command to the device.
After sending the SLEEP command, the controller goes into
a loop to wait for power to go off. In the event the controller
is turned back on by the override signal before the voltage
has dropped, the loop has a time limit which, when exceed·
ed, causes the controller to jump to the beginning of the
program and start again. If the override feature is not used
there is no need to test the timer seconds latch nor to test
for the override signal. Without the override, the controller
can only be turned on by the COP498 if the time out period
has elapsed. Note also that the timer features continue to
operate regardless of the state of the override signal. The
override signal, when high, merely forces the ON pin to go
low. The operation of the rest of the chip is in no way affected by the override signal.
COP411 L. The code in Figure 9b is the recommended interface code for COP41 OLlCOP411 L. The code is written as
subroutines and the code uses one level of subroutine internally. It is apparent from the code that the software interface
is somewhat different for the READ and WRITE instructions
than for the rest of the instructions. The routine labelled
SETUP is assumed to be in page 2 of the ROM. The rest of
the code may be located anywhere in program memory subject to the usual programming rules of COPS microcontrollers. The lower four bits of the instruction opcode are assumed to be located in RAM location COMAND, which is
chosen as location 3,15. Data I/O uses register 2. The controller-COP498/499 interface is assumed to be as in Figure
6 or Figure 7. It is assumed that the SIO register in the
COPS controller is enabled as serial. I/O prior to entry to
these routines.
GENERAL CODE FOR SOFTWARE INTERFACE
The code in Figure 9a is recommended for interfacing the
device to any COPS controller other than COP410Ll
WRITE:
RW:
READ:
INSTRT:
FINISH:
SETUP:
JSRP
LD
XAS
XIS
JP
OBD
JP
JSRP
NOP
NOP
NOP
NOP
NOP
JP
JSRP
NOP
NOP
CLRA
RC
OBD
XAS
RET
• PAGE
LBI
CLRA
SC
XAS
OBD
CLRA
XAS
CLRA
AISC
SC
XAS
LD
NOP
NOP
XAS
LBI
RET
SETUP
READ/WRITE DATA
RW
DISABLE THE COP498/499 (B=O)
FINISH
SETUP
NEED A TOTAL OF 5 SK CLOCK DELAYS (5 NOP'S)
UNTIL DATA OUT IS VALID AT SIO REGISTER
RW
SETUP
ROUTINE FOR THE REST OF THE INSTRUCTIONS
DELAYS TO INSURE PROPER TIMING
DESELECT THE COP498/499 (B=O)
TURN OFF THE CLOCK
2
COMMAND
POINT TO LOCATION WHERE COMMAND STORED
TURN ON SK CLOCK
ENABLE THE COP498/499 (B=15)
MAKE SURE NO INVALID DATA SENT
1
SET UP START BIT
SEND START BIT MSD OF INSTRUCTION
FETCH COMMAND TO A
2,0
MAINTAIN PROPER TIMING
SEND COMMAND
POINT TO READ/WRITE REGISTER
RETURN TO MAIN ROUTINE
FIGURE 9a. Software Interface to COP498/COP499 for COPS Controllers Other Than COP410L/COP411 L
6-60
0
Functional Description
WRITE:
RW1:
RW2:
RW:
READ:
INSTRT:
FINISH:
SETUP:
JSRP
XAS
LD
XDS
LD
XAS
XIS
JP
OBD
JP
JSRP
XAS
NOP
NOP
NOP
NOP
NOP
JP
JSRP
XAS
NOP
NOP
NOP
NOP
CLRA
RC
OBD
XAS
RET
• PAGE
LBI
CLRA
SC
XAS
OBD
CLRA
XAS
CLRA
AISC
SC
XAS
LD
LBI
RET
0
(Continued)
."
0l:Io
SETUP
CD
SEND COMMAND
POSITION Bd PROPERLY
Q)
.......
0
0
."
w
CD
Q)
.......
0
0
."
RW
0l:Io
DISABLE THE COP498/499 (B=O)
FINISH
SETUP
SEND READ COMMAND
DELAY FOR DATA VALID
RW2
SETUP
ROUTINE FOR REST OF INSTRUCTIONS
SEND INSTRUCTION
DELAY FOR INSTRUCTION ACCEPT
DESELECT THE COP498/499
TURN OFF THE CLOCK
2
COMMAND
: TURN ON SK CLOCK
ENABLE THE COP498/COP499 (B=15)
: MAKE SURE NO INVALID DATA SENT
1
SEND START BIT-MSD OF INSTRUCTION
FETCH INSTRUCTION
2,9
FIGURE 9b. COP410L/COP411L Software Interface to COP498/COP499
full usage of the device memory when using the COP410Ll
411 L.
The code in Figure 9a will read or write 64 bits at a time.
Note that in the COP41 OLl411 L the code in Figure 9b will
read or write 32 bits at a time. The code of Figure 10 is
recommended if the user wishes to work in blocks of 64 bits
with the COP41 OLl411 L. Only the code which is different
from that shown in Figure 9b is shown in Figure 10.
GENERAL NOTES
1. For complete safety in all cases it is recommended that
the SK clock be turned off after the device has been
deselected since the device is dynamic when it is enabled, If the clock is turned off while the device is selected, special care must be given to the SK timing characteristics. In no case should the clock be turned off while
the device is selected if the SK period is greater than
about 50 p,s.
The routine in Figure 10 will read/write into registers 2 and 1
in the COP410Ll411L. Figure 10 illustrates the preferred
method of achieving full utilization of the device memory
when the COP41 OLl411 L is the contoller. Remember that
all the other routines are as shown in Figure 98. Figure 10
illustrates only that code that must be changed to achieve
6-61
CD
CD
.......
0
0
."
W
CD
CD
m
m
Cf)
A.
0
0
......
m
m
~
Functional Description
WRITE: JSRP
RW1:
XAS
RW2:
LD
RW:
XDS
LD
A.
0
0
......
CO
m
Cf)
A.
0
0
......
CO
m
X
LD
INITIALIZE, SEE FIGURE 9B
SEND COMMAND
POSITION Bd
USE REGISTERS 2 AND 1
3
NOP
XAS
XIS
0
JP
0
(Continued)
XAS
~
A.
SETUP
3
RW
; DESELECT THE COP498/499
OBD
JP
FINISH
FIGURE 10. COP410L/411L-COP498/499 Special Routine
6. When using the TSEC command in COP498 with the
code as given in Figure 9, the master program should
test for the accumulator greater than 1 to determine if
the timer seconds latch was set. Note again, test for
greater than 1; do not test for greater than zero.
2. The device does not become dynamic until both CS and
CE are high and at least one high level is seen at the SK
input. Thus the device may be safely enabled prior to
turning on the clock as long as SK is low when the device is enabled.
3. The device must be deselected between instructions.
Failure to do so will yield improper operation. The device
relies on the select lines changing state in order to clear
internal registers. Only one of the select lines on the
COP498 needs to go low between instructions.
NOTE ON MICROWIRE INTERFACE
If the device is connected to a MICROWIRE interface containing other circuits whose DO (data output) pins may produce a signal swing higher than Vee of the device, some
protection is needed on the DO pin of the device. This happens when the DO pins of several peripherals powered by
different voltages are connected together; e.g., a COP452
at 4.5V with a COP499 at 2.4V. When the DO pin of
COP498/499 is externally driven above its power supply
voltage, a current will flow into it and this current must be
limited to 1 mAo As an example we have two COP452s with
a COP420L operating at 4.5V and a COP499 operating at
2.4V. When enabled, the DO pin of a COP452 may swing
higher than 2.4V, the power supply voltage of the COP499.
One way to limit the current is to use a current limiting resistor of 2 kn between the DO pins of the COP452 and the
COP499. NOTE: the SI pin of the COPS processor MUST
BE A Hi-Z INPUT. Two configurations are possible as
shown in Figure 11. Note that the resistor between DO and
SI will give extra RC delay to the signal going from the DO
pin to the SI pin of the COPS processor. Connection B is
preferred because the DO signal from COP499 has nearly a
whole SK cycle to become valid at SI input before the signal
is read by the processor. When a ROMless COPS processor (COP401 L/COP402/COP404L) is used for emulation,
the circuit shown in Figure 12 may be used to simulate a HiZ input for the SI pin.
4. The user must insure that a WREN (write enable) instruction has been performed in order to write to the
device memory. The WREN command need be given
only once unless the SLEEP feature is used. If ON goes
high as a result of a SLEEP command, a write disable is
automatically performed in order to provide maximum
protection to the device memory while the COPS controller is powering up and powering down. As long as
ON remains high, WRITE and WREN instructions are
disabled. Thus when the COPS controller wakes up after previously issuing a SLEEP command, a WREN instruction is required before data can be written to the
device.
5. The six bit section of the RAM address register will increment whenever there are clock pulses present when
the CS and CE pins are high. Thus the user can position
the RAM address register if he wishes by selecting the
device, holding the 01 pin low and supplying the appropriate number of clocks. Then, without deselecting the
device, the user would send the instruction and read or
write data. Although possible, this technique is not recommended as it is fairly involved.
b.
8.
COP452
4.5V
COP452
4.5V
coma
2.4V
2.4V
TL/DD/6684-11
FIGURE 11. High Voltage Protection on DO pin
6-62
(')
Functional Description
o
(Continued)
""C
~
CD
Q)
Y+
.......
I
Yee
eOP401LI
COP4021
eOP404L
SI
(')
~
eOP49B/eOP499 Yee
o
""C
< Y+
W
CD
Q)
Ycc
~
.......
HI-Z SI
(')
74C902
TLlDD/6684-12
FIGURE 12. Simulating HI-Z Sllnput on ROMless Processors
o""C
~
CD
CD
.......
(')
o
""C
W
CD
CD
6-63
Section 7
DisplayITerminal
Management Processor
(TMP)
•
I
Section 7 Contents
TMP..............................................................................
NS405 Series Display Terminal Management Processor (TMP) ...........................
AB-14 Throughput Considerations in NS405 System Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AB-16 NS405-Series TMP External Interrupt Processing.................................
AN-354 TMP Rowand Attribute Table Lookup Operation................................
AN-355 TMP-Dynamic RAM Interfacing........................... ....................
AN-367 TMP External Character Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-369 NS405 TMP Logic Analyzer.............................. ....................
AN-374 Building an Inexpensive But Powerful Color Terminal. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-399 TMP Extended Program Memory.......................... ....................
7-2
7-3
7-4
7-43
7-44
7-46
7-53
7-58
7-61
7-68
7-73
~National
D Semiconductor
TMpTM
Terminal Management Processor
Highly compact, the TMP board reduces previously necessary board space dramatically while providing 100% emulation of a classic low-end terminal. The board can also be
used for TMP evaluation or as a vehicle for designing-in the
NS405 device.
The TMP (NS405 series) is a single-chip CRT terminal display controller. The TMP is supported by the MOLETM development system and replaces all the following LSI circuits
commonly found in a terminal:
• Microprocessor
The board which is controlled by a preprogrammed NS455,
needs only a video monitor, ASCII encoded keyboard, and
power supply to provide your complete terminal. Should you
wish to write your own program, no problem.
• Program ROM
• 64 x 8 RAM
• CRT controller
• DMA controller
The cross-assembler software provides the capability. The
board will execute custom programs through up to 8k of offchip memory.
• Character generator
• UART
• BAUD rate generator
The TMP demo board comes complete with operating manual, program source listing, board schematic, board layout,
and all necessary connectors.
• Parallel liD controller
• Timer
The TMP offers complete CRT control over a wide scope of
high-density circuit applications including phones, keyboard
integration assignments, logic analyzers and more.
When you're ready to design your own TMP system, turn to
National's MOLE development system. By using this system-comprised of brain board, personality board and software-you bring dedicated development support to the
TMP chip, making design-in extremely fast and simple.
The NS455 Terminal Management Processor (TMP) demo
board is available for design support.
•
7-3
I
U)
o~
U)
z
r----------------------------------------------------------------------------------,
~National
PRELIMINARY
D Semiconductor
NS405-Series Display/Terminal Management
Processor (TMP)
General Description
Features
The NS405 is a CRT terminal controller on a chip. It is a
microcomputer system which replaces the following LSI circuits commonly found in a CRT data terminal:
•
•
•
•
•
•
Enhanced 8048 instruction set and architecture
Up to 8k x 8 ROM external with ROM expand bus
On-board RAM 64 x a
Programmable display format
On-board video memory management unit
16-bit bidirectional display memory bus (direct video
and attribute RAM interface)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Built-in timer
Real-time clock (may be programmed for 1 Hz)
Video control signals
Eight independent attributes
Pixel and block graphics display modes
Programmable cursor characteristics
Programmable CRT refresh rate
Light pen feature
UART, programmable baud rate up to 19.2k baud
Character generator (128 characters 7 x 11 max)
Single 5-volt supply @ 110 mA (typ)
Up to 18 MHz video dot rate (12 MHz CPU clock)
48-pin package
a-bit parallel liD port (multiplexed with external ROM)
Extensive liD expansion capabilities
Up to 64k by 8 or 16 video RAM
- Microcomputer
- Baud Rate Generator
- CRT Controller
- Interrupt Controller
- DMA Controller
- Character Generator
-UART
- Timer
- Parallel 110 Controller
In addition the NS405 includes powerful attribute logic, two
graphics display modes, and fast video output circuits.
The NS405 is primarily intended for use in low-cost terminals, but contains many features which make it a superior
building block for "smart" terminals and word processing
systems.
The NS405 interfaces easily to the display monitor, keyboard, display memory, and liD ports. The architecture and
instruction set are derived from· the 8048-series microcontrollers. The instruction set has been enhanced and the architecture tailored to allow the NS405 CPU to efficiently
manage a large display memory and an extensive interrupt
environment.
The TMP can be used to easily and inexpensively add a
display to many systems where it was previously impractical, it is not limited to terminal applications.
Block and Connection Diagrams
SBO
SB1
SB2
SB3
HLOA, SC CLR,
1Nff, IP. HOLD
1100-1/07,
REO-RE12
XTAL1
XTAL2
SI
so
RESET
UART
Vss
Vee
=}
vs
SBO-SB15
VIDEO
OUT
FI CLK INTENS/
1lIm
TLlDD/5526-1
Top View
7-4
TL/DD/5526-2
z
en
Absolute Maximum Ratings
~
<:)
If Military/Aerospace specified devices are required,
Power Dissipation
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD
'EA, SI and VSYNC may be subjected to Vss + 15V.
Temperature Under Bias
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended; operations should be limited
to those conditions specified under DC Electrical Characteristics.
O·Cto +70·C
Storage Temperature
- 65·C to + 150·C
All Input or Output Voltages
with Respect to VSS·
-0.5V to + 7.0V
1.5W
c.n
2000V
DC Electrical Characteristics
TA
=
O·C to + 70·C, Vcc
=
+ 5V ± 10%, Vss
Symbol
=
OV, unless otherwise specified
Parameter
Min
Max
Units
VIL1
Input Low Voltage (All Except XTAL 1, XTAL2, RESET)
Test Conditions
-0.5
O.B
V
VIH1
Input High Voltage (All Except XTAL 1, XTAL2, RESET)
2.0
Vcc
V
VIL2
Input Low Voltage (XTAL 1, XTAL2, RESET)
-0.5
0.6
V
VIH2
Input High Voltage (XTAL 1, XTAL2, RESET)
3.B
Vcc
V
VOL
Output Low Voltage (All Except INTENS, VOl
IOL
0.4
V
VOH
Output High Voltage (All Except INTENS, VOl
IOH
2.4
Vcc
V
VOL
Output Low Voltage (INTENS, VOl
VOH
Output High Voltage (INTENS, VOl
= 2.0 mA
= -125 itA
IOL = 5.0 mA
IOH = - 500 itA
0.4
IlL
Input Leakage Current (EA, INT, SI)
Vss :5: VIN :5: Vcc
IOL
Output Leakage Current
(ROM Expand Bus, High Impedance State)
Vcc ~ VIN ~ Vss + 0.45
IOL
Output Leakage Current
(System Bus, High Impedance State)
Vcc ~ VIN ~ Vss + 0.45
Icc
Total Supply Current
TA
=
V
2.4
25·C
V
±10
itA
±10
itA
±100
itA
150
mA
AC Electrical Characteristics
TA
=
o·c to
Symbol
+70·C, Vcc
=
+5V ±10%, Vss
I
=
ov, unless otherwise specified
I
Parameter
CPU AND ROM EXPAND BUS TIMING
Min
I
Max
I
Units
FXTAL
Crystal Frequency
3
1B
MHz
Fcpu
CPU Frequency
3
12
MHz
tCY
CPU Cycle Time
1.25
7.5
its
tOF
Video Dot Time
55.5
333.3
tLL
ALE Pulse Width (Note 1)
125
ns
tAL
Address Setup to ALE (Note 1)
55
ns
tLA
Address Hold from ALE (Note 1)
40
ns
tcc
Control Pulse Width PSEN, RD (Note 1)
tOA
Data Hold (Notes 1, 4)
tAD
250
ns
ns
100
ns
PSEN, RD to Data In (Note 1)
220
ns
tAD
Address Setup to Data In (Note 1)
360
ns
tAFC
Address Float to RD, PSEN (Notes 1, 5)
tCAF
PSEN to Address Float (Notes 1, 5)
tOAL
Data Setup to ALE (REO-7, 11, 12) (Note 1)
55
ns
tALO
Data Hold from ALE (REO-7, 11, 12) (Note 1)
40
ns
tCIS
Control Input Setup to ALE (REB, 9, 10) (Note 1)
tCIH
Control Input Hold from ALE (REB, 9, 10) (Notes 1, 4)
0
0
-10
7-5
ns
+10
240
75
ns
ns
125
ns
•
AC Electrical Characteristics
TA = O°C to + 70°C, Vee = + 5V ± 10%, Vss = OV, unless otherwise specified (Continued)
Symbol
I
I
Parameter
Min
I
Max
I
Units
SYSTEM BUS TIMING
tEL
RAM ALE Low Time (Note 1)
250
ns
tEH
RAM ALE High Time (Note 1)
100
ns
tAS
Address Setup to RAM ALE (Note 1)
20
ns
tAH
Address Hold from RAM ALE (Note 1)
10
ns
tRR
RAM RD Width (Note 1)
210
ns
tAR
Address Setup to RAM RD (Note 1)
80
ns
tRRO
Data Access from RAM RD (Note 1)
tROR
Data Hold from RAM RD (Notes 1, 4)
tWFI
FIFO In Clock Width (Note 1)
210
tww
RAM WR Strobe Width (Note 1)
130
ns
tAW
Address Setup to RAM WR (Note 1)
120
ns
tow
Data Setup to RAM WR (Note 1)
10
ns
two
Data Hold from RAM WR (Note 1)
20
ns
55
ns
0
140
ns
60
ns
ns
VIDEO TIMING
tOF
Dot Period =
~ (Note 1)
tVID
Video Blank Time (Note 1)
tVI
Skew, Intensity to Dot 0 (Note 1)
tFOV
FIFO Out Clock to Dot 0 (Note 1)
5
15
ns
-15
15
ns
15
ns
FIFO Out Clock Width High (Note 1, Note 2)
165
55
tWFOH
.% CPU cycle.
··1 Dot time is 55 ns.
Note 1: Control outputs CL = 80 pF; ROM Expand Bus outputs CL = 150 pF; System Bus outputs CL = 100 pF; VOUT & INTENS outputs CL =
18 MHz; Fcpu = 12 MHz. XTAL1 & XTAL2 driven externally per Figure 12b with 50% duty cycle.
Note 2: FOGO< duty cycle is shown above.
Note 3: Hold request is latched. It is honored at the start of the next vertical retrace.
Note 4: Max spec. listed for user information only. to prevent bus contention. Maximum value not tested.
Note 5: Not tested.
ns
50 pF;
FXTAL =
Input Hold Times
TA = 25°C. Vee = +5V ±10%, Vss = OV
Character
Cell Width
FIFO Out
HIGH
FIFO Out
LOW
6
7
8
9
10
1 dot
2 dots
2 dots
3 dots
3 dots
5 dots
5 dots
6 dots
6 dots
7 dots
Input
Min Active Time
Reset
50 ms (power up)
5 CPU Cycles (after power up)
External Interrupt
2CPU Cycle
Light Pen
1 CPU Cycle
I/O Input
1 CPU Cycle
Hold Request
1 CPU Cycle (Note 3)
FIFO
Fall through should not be greater than 4 character times
(character time = 1/fXTAL x #dots/cell).
Throughput rate must be at least the character rate (character rate = 1Icharacter time).
7-6
z
Capacitance T A =
25°C, VCC
=
Vss
=
en
~
OV
o
U1
Symbol
Parameter
Test Conditions
=
Min
CIN
Input Capacitance
Fc
COUT
Output and Reset
Unmeasured Pins Returned to Vss (Note 5)
1 MHz (Note 5)
Max
Units
10
pF
20
pF
AC Electrical Characteristics in CPU Cycle Time
CPU AND ROM EXPAND BUS TIMING (FOR REFERENCE ONLY)
Symbol
Typ
Parameter
tll
ALE Pulse Width
14tCY/50
tAL
Address Setup to ALE
8 tCY/50
tLA
Address Hold from ALE
tcc
Control Pulse Width
tCY
CPU Cycle Time
6tCY/50
PSEN
RD
24 tCY/50
36 tCY/50
60 ley/so
=
15/fcPU
=
f
15
. 1
. 15
XTAl"" or..,..
tOR
Data Hold
-2 tCY/50
tRO
Control Pulse to Data In PSEN
RD
18 tCY/50
30 tCY/50
tAD
Address Setup to Data In
32 tCY/50
tAFC
Address Float to
PSEN
RD
2 tCY/50
2 tCY/50
o tCY/50
tCAF
PSEN to Address Float
tOAl
Data Setup to ALE
REO-7
RE8-10
RE11-12
tAlO
Data Hold from ALE
REO-7
RE8-12
6 tCY/50
-2 tCY/50
16 tCY/50
2 tCY/50
6 tCY/50
SYSTEM BUS TIMING (FOR REFERENCE ONLY)
Symbol
Ticks
Parameter
Min
tEL
RAM ALE Low Time
14 tCY/60 - 42 ns
tEH
RAM ALE High Time
6 tCY/50 - 25 ns
tAS
Address Setup to RAM ALE
4 tCY/50 - 60 ns
tAH
Address Hold from RAM ALE
2 tCY/50 - 40 ns
tRCY
Read or Write Cycle Time
tRR
RAM RDWidth
tAR
Address Setup to RAM RD
tRRO
Data Access from RAM RD
tROR
Data Hold from RAM RD
tWFI
FIFO In Clock Width
Max
12 tCY/50 - 40 ns
6 tCY/50 - 45 ns
10 tCY/SO - 70 ns
12 tCY/50 - 40 ns
tww
RAM WR Strobe Width
tAW
Address Setup to RAM WR
tow
Data Setup to RAM WR
2 tCY/50 - 30 ns
two
Data Hold from RAM WR
2 tCY/60 - 20 ns
8 tCY/60 - 27 ns
10 tCY/50 - 90 ns
7-7
,.
it)
Q
Ch
z
Timing Waveforms
ROM Expand Bus Timing
(In Port Instruction Is Shown)
1---------ICy - - - - - - - - , /
ALE
I--+---IAD
iiii
-ILA
REO-RE7
ADDRESS (HI·Z IF EXTERNAL
ROM NOT USEO)
INPUT
ADDRESS (REMAIN DATA OUTPUT
IF EXTENAL ROM NOT USED)
DATA OUTPUT (SC CLR. HLOA)
REB-RE1O
ADDRESS (REMAIN DATA OUTPUT
IF EXTERNAL ROM NOT USED)
RE11-RE12
TL/DD/5526-3
·Remain 110 OUTPUT if External ROM not used.
··110 Data input or 2nd ROM byte of 2 byte instruction. Otherwise remain 110 OUTPUT.
System Bus Timing
,
.1
IRCY
,
RAM ALE
IEL
IEH-I
'l
I
IWfI
"\
I
ONLY ON A VIDEO READ
J
IRR
"\
j
~~
IU-I-IAH-
BUS
ADDRESS OUT
I,
IRRD
'
\.
J
-IRD~
DATA IN
X
ADDRESS OUT
I---tww)
I
I\.
I
lAW
_!::::.IAS-I-IAH-li===tow -
BUS
.A
ADDRESS OUT
I---tWD=::::j
DATA OUT
ADDRESS OUT
TL/DD/5526-4
7-8
Timing Waveforms
zen
0I:loo
(Continued)
<:)
U'1
Video Timing
DDT NUMBER
(USING 7·WIOE CELLI
OFF
VIOEO--I---J
~
______________________r---\____
TL/DD/5526-5
Scan Count Clear Timing
HORIZONTAL
BLANKING BEGINS
HORIZONTAL
BLANKING BEGINS
HORIZONTAL _ _......
SYNC
I
I
I
I
I
I
CHARACTER:
WIDTH TIt.4ES:
CHARACTER:
WIDTH TIt.4ES:
SCAN COUNT
CLEAR
I
~
~
: FIRST SCAN LINE IN
: NEXT ROW BEING
I DISPLAYED
-----.-t
5S
TL/DD/5526-6
For external character generation this edge Is used to clock CLEAR
Into scan line counter. The edge must come before Scan Count Clear goes
away, but not before the video controller has brought In all necessary
display Information for the last scan line.
II
I
7-9
NS405
m
o
()
;::II\"
c
iii"
ea
....
NS405-Series Detailed
XTALl XTAl2
RE12 REll RE1D
HLOA SC CLR INTR
REg
IP
RE8
HOLO
EA
D)
3
SI
UART CONTROL
REGISTERS
2x8
REO. 1/00
RE1.llOl
RE2.I/02
RE3.I/03
RE4.1104
BAUD RATE
CONTROL REGS.
2xB
UART
STATUS REG.
SO
REAL
TIME
INTERRUPT
RES. 1105
RE6.1106
RE7.I/07
RAM
64x8
ALE
~
a
RAM ALE
RAM WR
RAM RO
DOT CLK
FI CLK
PSEN
iW
31
-
-
DISPLAY MEMORY
CONTROL REGISTERS I
7x16
DISPLAY MEMORY
CONTROL REGISTERS II
3x8
DISPLAY MEMORY
L __
r.------:1
:1 VERT
"';E;';;O;';';R- - - - - '
DOT
ATTRIBUTE
LOGIC
CLK
L. _~_.J
-+t
FO CLK
-;D~O;;;O:- ;JINTENSITY
REGISTER
SYS~~~I~~:~ROL
VIDEO CONTROL
CHARACTER
CONTROL
REGISTERS
SYNC. BLANK.
UNGTH
VERTICAL
CONTROL
REGISTERS
SCAN
CONTROL
REGISTERS
SYNC. BLANK.
LENGTH
BLINK
REGISTER
CRT REFRESH AN'
I
CONTROL LOGIC
L
----
25
16
SBD-SB15
HORIZONTAL
CONTROL
REGISTERS
ICONTROL
..2:.0~D~U!......J
1-16
I
I
VIDEO OUTPUT
(VOl
INTENSI
FO CLK
I
HORIZONTAL
SYNC
J
32
Vee
Vss
RESET
TLlDD/5526-7
z
en
1.0 Functional Pin Descriptions
~
o
U1
1.1 SUPPLIES
Pin
Name
48
Vcc- Power
24
Vss - Ground Reference
1.2 INPUT SIGNALS
23, 22
XTAL 1, XTAL2 - Crystal 1, 2:
29
EA - External Access:
RESET
32
34
SI - Serial Input:
1.3 OUTPUT SIGNALS
33
SO - Serial Output:
21
ALE -
Address Latch Enable:
30
PSEN -
31
RD -
Read Port Data:
28
HS -
Horizontal Sync
27
VS -
Vertical Sync Output:
26
VO - Video Output:
25
INTENSIFO CLK
17
VID CLK/FI CLK - Video Dot Clock Out!
FIFO IN CLOCK
18
RAM ALE -
20
19
RAM RD - RAM Read:
RAM WR - RAM Write:
Program Store Enable:
1.4 BUS-I/O
1-8
SBO-SB7 -
9-16
SB8-SB15 -
RAM Address Latch Enable:
System Bus 0-7:
System Bus 8-15:
35-47
REO-12- ROM Expand Bus 0-12:
40-47
REO-RE7
Function
5V ±10%
Crystal connections for clock oscillator (3-18 MHz).
Pull HIGH (V1H2)
An active low input that initializes the processor. The RESET input is also
used for internal ROM verification.
Drives receiver section of UART (true data).
Driven by transmitter section of UART (true data).
ROM address is available on the ROM Expand Bus and may be latched
on the falling edge of ALE. Port output data may be latched on the rising
edge of ALE. ALE pulses are always present, even if EA is tied low.
Enable external ROM output drivers when low. PSEN is idle (high) when
the CPU fetches from internal ROM.
Accept Port input data on ROM Expand Bus REO-RE7 while low. ROM
Expand Bus is in high impedance state while RD is low.
The rising edge of HS is controlled by the Horizontal Sync Begin Register
and the falling edge is controlled by the Horizontal Sync End Register. HS
is disabled (low) if bit 5 of the Video Control Register = O.
The falling edge of VS is controlled by the Vertical Sync Begin Register
and the rising edge is controlled by the Vertical Sync End Register. VS is
at TRI-STATE if bit 5 of the Video Control Register = O.
High = beam on, low = beam off. VO is disabled (low) if bit 5 of the
Video Control Register = O.
(Shared pin) INTENS Signal under attribute control may be used to switch
the bistable brightness of display characters.
FIFO Out Clock may be used to clock data from an external FIFO in
synchronism with data from the internal FIFO.
Both CANNOT be used simultaneously.
(Shared pin) The rising edge of the Video Dot Clock may be used to clock
the data out of the video output pin. FIFO In Clock may be used to clock
data from an extended attribute RAM into an external FIFO in
synchronism with the data loaded into the internal FIFO.
Both CANNOT be used simultaneously.
RAM address is available on the System Bus and may be latched on the
falling edge of RAM ALE. Only operational when Display RAM accesses
being performed. Otherwise high.
Enable display RAM data onto the System Bus when RAM RD is low.
Data to RAM is available on the System Bus and may be written at the
rising edge of RAM WR.
Display RAM address is output while RAM ALE is high and may be
latched on the falling edge of RAM ALE. System Bus accepts data input
while RAM RD is low and outputs data while RAM WR is low.
Normally, Display RAM address is output and held on these pins for the
full read or write cycle. However, if bit 4 of the System Control Register is
set, these pins function bidirectionally like SBO-SB7 to allow 16-bit data
words for attribute operation.
Used for program ROM expansion as described below. Time multiplexed
with 1/0 port and system control signals. 1/0 port and system control
signals only if no external ROM used.
Low order ROM address is output and may be latched on the falling edge
of ALE. Enable ROM data to this Bus when PSEN is low. Enable 1/0 port
input data to the Bus when RD is low. Use the rising edge of ALE to latch
port output data.
7-11
•
~ r-------------------------------------------------------------------------------------------~
o
"'II:f'
tJ)
Z
1.0 Functional Pin Description
Pin
39-35
Name
RE8-RE12
37
INTR - Interrupt: RE1 0
38
LP - Light Pen Interrupt: RE9
39
HOLD - HOLD request: RE8
35
HLDA- Hold Acknowledge: RE12
36
SC CLR - Scan Count Clear: RE11
(Continued)
Function
Five most significant bits of the ROM address are output during ALE and
remain stable until data is read in during PSEN. These pins are
multiplexed with the HLDA, INTR, LP, SC CLR, and HOLD signals.
An active low input that interrupts the processor if the external interrupt is
enabled. Because it shares a pin with RE10, INTR may be driven directly
only if no external ROM is used (EA is low). Otherwise must be driven
through a 3.9k resistor. *
An active low input that interrupts the processor if internal interrupts are
enabled and bit 5 in the Interrupt Mask Register is set. Because it shares
a pin with RE9, LP may be driven directly only if EA is low. Otherwise,
must be driven through a 3.9k resistor. *
When high, requests that the NS405 enter the Hold mode. When in the
Hold mode the System Bus will be in a high impedance state. The Hold
mode is granted at the beginning of the next vertical retrace. Because it
shares a pin with RE8, HOLD may be driven directly only if EA is low.
Otherwise, must be driven through a 3.9k resistor. *
This output is asserted in response to Hold and provides handshake
capability with another processor (active high). For more detailed
information see Section 3.0 Slave Processing. Because HLDA shares a
pin with RE12, the HLDA state is preset only during the interval preceding
the rising edge of ALE. However, if no external ROM is used, HLDA is a
steady state output and need not be latched externally.
This output clears an external scan counter when used with an external
character generator. It is a low going pulse which occurs during the
horizontal retrace preceding the first scan line of each character row.
Because SC CLR shares a pin with the RE11, the correct SC CLR state is
present only during the interval preceding the rising edge of ALE.
However, if no external ROM is used, SC CLR is a steady state output
and need not be latched externally.
·Unused control inputs must be terminated
2.0 Functional Description
2.1 CPU
The CPU of the NS405 is patterned after the 8048 single
chip microcomputer (see Figure 1).
...-----r---..,
CPU
DIVIDE
12 MHz
MAX
REB-RE12
+32
1 INSTRUCTION
CYCLE
REO-RE7
INTERNAL
INTERRUPT MASK
RESET
EA
EXT INT
t-----+iiii
t----+PSEN
t----+
ALE
Tl/OO/5526-8
FIGURE 1. NS405 Series CPU Block Diagram
7-12
2.0 Functional Description (Continued)
8191
2.1.1 Accumulator - High Accumulator
In addition to the regular 8-bit Accumulator, there is an 8·bit
High Accumulator extension to facilitate the 16-bit operations required for display memory management. The HACC/
ACC pair is usually used in conjunction with the 16-bit RAM
pointer registers (RA, RO and RB, R1, CURSOR, HOME,
BEGD and ENDD) to effect video data transfers. In addition,
external attribute memory is loaded in a 16-bit transfer operation. Any instruction which causes a carry or borrow out of
the low accumulator will affect the high accumulator (see
Figure 2).
EXTERNAL
--
Auxiliary carry is used only when converting the accumulator contents from binary to BCD (binary coded decimal) using the DA A instruction. The auxiliary carry flag can be
cleared by moving a zero into bit 6 of the program status
word.
HIGH ACCUMULATOR
~
ADDRESS 0007
INTERNAL INTERRUPT
VECTOR
ADDRESS DDD3
EXTERNAL INTERRUPT
VECTOR
71&151.13121110 ~ ADDRESS DDDD
RESET VECTOR
ACCUMULATOR
TLlDD/5526-11
FIGURE 4. Program Memory Map
2.1.4 Program Status Word Bit Assignments
CARRY
AUXILIARY CARRY
Bit
Position
TLlDD/5526-9
FIGURE 2. CPU Accumulator
0
1
2
3·
2.1.2 Program Counter (PC)
The Program Counter is a 13·bit wide register which provides program addressing for the CPU. The lower 11 bits
operate like a conventional program counter while the upper
2 bits are actually latches. These 2 latches are automatically
loaded from the bank select flip-flops (PSW bits 3, 4) whenever a JMP or CALL instruction is executed. The bank select flip-flops in turn are only modified upon the execution of
a Select Memory Bank Instruction or modification of the
PSW (see Figure 3).
4·
5·
6·
7*
CONVENTIONAL PROGRAM COUNTER
Contents
Stack Pointer Bit, SO
Stack Pointer Bit, S1
Stack Pointer Bit, S2
Memory Bank Select Bit 0
Memory Bank Select Bit 1
Register Bank Select Bit (0 = Bank 0,
1 = Bank 1)
Auxiliary Carry. A carry from Bit 3 to Bit 4
generated by an add operation. Used only by
the decimal adjust (DA A) instruction.
Carry. A bit indicating the preceding
operation resulted in an overflow or an
underflow from the 8-bit accumulator.
'Note 1: Bits 3 through 7 are saved on the stack by subroutine calls or
interrupts. Bits 3 and 4 are restored upon execution of an RET instruction,
whereas all 5 bits are restored by RETR.
Note 2: FO is not saved on the stack (as in an 8048).
Note 3: Bits 0-5 cleared on a RESET.
BANK SELECT BITS (LATCHES)
(LOADED BY EXECUTION OF JMP DR CALL)
TL/DD/5526-10
FIGURE 3. TMP Program Counter
2.1.5 Stack Pointer (SP)
The stack pointer is an independent 3-bit counter which
points to designated locations in the internal RAM that
holds subroutine return parameters. The stack itself is located in RAM locations 8-23 (see Figure 5).
Each entry in the stack takes up two bytes and contains
both the PC and status bits. When reset to zero, the stack
pointer actually points to locations 8 and 9 in RAM. Since
the stack pointer is a simple up/down counter, an overflow
will cause the deepest stack entry to be lost (the counter
overflows from 111 to 000 and underflows from 000 to 111).
2.1.3 Program Memory
Memory is subdivided into 2k banks with accesses limited to
the currently selected bank unless a Bank Change sequence has been executed. Upon reaching the end of a
memory bank, the program counter will wrap around and
point to the beginning of the current bank.
Each bank is further subdivided into pages of 256 bytes
each, with 8 pages in every bank. The conditional JUMP
instructions are restricted to operate within the memory
page that they reside in.
Note: If the level of subroutine nesting is less than eight (8), the unneeded
stack locations may be used as RAM.
Because of the sequence which the CALL instruction executes when pushing and loading the PC, it is possible to
easily call and return from subroutines located in different
memory banks (see Figure 4).
Upon executing an RET or RETR instruction for a call from
one memory bank into another, a SEL MBx instruction
should be excuted to restore the memory bank select flipflops to their original bank. However, no SEL MBx is needed
after an interrupt since the flip-flops were never modified.
LOCATION
POINTER
000
TL/DD/5526-12
Note: The odd numbered RAM bytes in the stack area have two (2) extra
bits to allow for storage of the bank select switch bits. This feature allows
interrupt routines and subroutines to be located outside the current 2k pro·
gram memory bank.
FIGURE 5. Typical Stack Composition
7-13
•
I
~
o
'III:t'
(/)
Z
r---------------------------------------------------------------------------------------------~
2.0 Functional Description
(Continued)
Then the interrupt vector address (3 or 7) is loaded into the
PC and service started. Whenever an interrupt condition is
being serviced all other interrupts of either class are locked
out until a RETR instruction is executed to conclude interrupt service. If both an external and internal interrupt arrive
at the same time, the external interrupt is recognized first.
2.1.6 Data Memory (On-Chip RAM)
The data memory nominally consists of 64 8-bit locations
and is utilized for working registers, the subroutine stack,
pointer registers and scratch pad. There are two sets of
working/pointer registers (RO-R7) which are selected by
the Select RAM Bank instruction. The stack area is located
in locations 8-23. Locations 32-63 contain the scratch pad
memory. To facilitate 16-bit Video Memory Management
there are two 8-bit extension registers (RA and RB) which
are associated with the RO and R1 registers respectively of
whichever RAM bank is currently selected (see Figure 6).
i.e., There is only one RA register and only one RB register.
-.--
63
DDRESSED INDIRECTLY
BY RD AND R1
i-
DIRECTLY
ADDRESSABLE
WHEN
SELECTED
+
32
31
26
i-
DIRECTLY
ADDRESSABLE
IRB
IRA
I
•
SCRATCH PAD
RAM
32x8
25
ALTERNATE R1
ALTERNATE RD
23
STACK REGISTER
OR USER RAM
16x8
8
7
2
1
D
2.1.8.2 Internal Interrupts
BANK 1
WORKING REGISTERS
8x8
24
DDRESSED INDIRECTLY
BY RD AND R1
2.1.8.1 External Interrupt
The External Interrupt consists solely of the shared INTR/
RE10 pin. External interrupts on this pin will be detected if
the setup and hold times as shown in the timing diagrams
are met. This pin is a level sampled interrupt which means
that as long as the pin is low during the sampling window an
interrupt will be generated. In addition, the INTR pin is the
only external pin whose logic state can be directly tested
through software.
The Internal Interrupts consist of seven internal operational
conditions plus the light pen arranged in an 8-bit wide register as shown in Figure 8. Activation of an internal interrupt
condition causes a corresponding register bit to be set, Figure 9. Each internal interrupt may be individually masked out
through the Interrupt Mask register which has the same bit
assignments as the Interrupt register and can be loaded
from the accumulator. A zero in the Interrupt Mask register
inhibits the interrupt and a one enables it. Further interrupt
processing is as shown. To determine which of the eight
internal conditions caused the interrupt the CPU must read
the Interrupt register into the accumulator. To acknowledge
receipt of the interrupt certain bits are automatically cleared
on a read while others are reset upon service of the particular interrupt.
The conditions under which each of the interrupts are generated and cleared are as follows:
~ REGISTERS
PDlNTER
BANK D
WORKING REGISTERS
8x8
R1
RD
~ POINTER
REGISTERS
REGISTER BANK DOR 1 IS SELECTED UNDER PROGRAM CONTROL.
TLlDD/5526-13
FIGURE 6. RAM Memory Map
2.1.7 Timer
The On-Board Timer is an 8-bit up counter which sets the
Timer Overflow Flag and generates an internal interrupt (if
enabled) whenever it overflows from FF to zero. The Timer
may be stopped, started, loaded and read from by the CPU.
The Timer clock is derived from the CPU clock as shown in
Figure 7. Whenever a Start Timer instruction is executed the
-:- 32 is initialized to its zero state to insure a full count measurement. After overflow the timer keeps counting until the
next FF to zero overflow at which time the overflow flag will
be set and another interrupt generated. The overflow flag
can only be reset through the JTF and JNTF instructions.
TIMER
CLOCK
VERTICAL INTERRUPT·
END OF ROW INTERRUPT
UART TRANSMIT BUFFER EMPTY
L -_______ UART TRANSMITTER
EMPTY
L--_ _ _ _ _ UART RECEIVE BUFFER FULL
L--_ _ _ _ _ _ LIGHT PEN INTERRUPT·
L -_ _ _ _ _ _ _ _ _ _ _ _ _ TIMER INTERRUPT·
L - - - - - - - - - - R E A L TIME INTERRUPT·
TL/DD/5526-16
Note: The interrupt flags indicated by an asterisk (0) are cleared when the
Interrupt Register is read.
CPU
CLOCK
FIGURE 8. Internal Interrupt Register
TL/DD/5526-14
FIGURE 7. Timer Clock Generation
Bit
o
2.1.8 Interrupts
The interrupt circuitry handles two generic classes of interrupt conditions called Internal and External. Either class has
its own master control which can be activated through software enable and disable instructions. On an interrupt service the currently executing instruction is completed, then
two CPU cycles are used as the program counter and bits
3-7 of the PSW are pushed onto the stack and stack pointer is incremented.
7-14
Vertical Interrupt-Generates an interrupt at the end of
the display row designated by the Vertical Interrupt
Register. Interrupt bit cleared on a CPU read of the
interrupt register. If VIR> Vertical Length Register no
interrupt will be generated.
z
2.0 Functional Description
en
0I:loo
o
(Continued)
U1
VERTICAL INTERRUPT
----4
READ----.......I
END DF ROW
---1"_ .. Ln_."J----~---l----JJ----.,
LOAD HOME - - - - . . . . . . . I
UART TI BUFFER EMPTY
---1;::""':;::".:J1r---oo:::::::---t
LOAD Tl BUFFER - - - -........
UART TI REGISTER EMPTY
----4
TRANSFER FROM BUFFER - - - -........
UART RI BUFFER FULL
----f
READ RI BUFFER - - - -........
UGHT PEN
----f
READ - - - -........
ENABLE
INTERNAL
INTERRUPTS
TIMER
-----f
READ - -_ _- - l
----I
READ ------I
REAL·TIME
TL/DD/5526-15
FIGURE 9. Internal Interrupt Processing
Bit
1 End of Row Interrupt-Generates an interrupt at the
end of each display row when the Current Row Start
Register is updated for the next row. Used in conjunction with the Row Sequencing Control Bit (5) in the
System Control Register to implement Row Pointer
Look-Up Tables and Horizontally Split Screens. Interrupt bit cleared on a CPU write to the Home Register.
Does not generate interrupts for those rows blanked
during vertical blanking.
2 UART Transmit Buffer Empty-Generates an interrupt
when the Transmit Buffer empties out after dumping a
character into the Transmit Shift Register. Interrupt bit
cleared on a CPU write to the Transmit Buffer.
3 Transmitter Empty-Generates an interrupt when
BOTH the Transmit Buffer and Transmit Shift Register
are empty. The interrupt bit is cleared when the CPU
loads the transmit buffer.
4 UART Receiver Buffer Full-Generates an interrupt
when the Receiver Buffer fills up with a character from
the Receive Shift Register. Interrupt bit cleared on a
CPU read of the Receiver Buffer.
5 Light Pen Interrupt-Generates an interrupt on each
falling edge detected on the shared LP/RE9 pin. Since
only falling edges generate interrupts and the input is
sampled each CPU Cycle, a high level must be sampled between falling edges in order to be considered a
new interrupt. This interrupt is used to latch the light
pen position registers. For further information see Light
Pen Description. Interrupt bit cleared on a CPU read of
the interrupt register.
Bit
6 Timer Interrupt-Generates an interrupt when the internal B·bit Timer overflows from FF to 00. Interrupt bit
cleared on a CPU read of the interrupt register.
7 Real-Time Interrupt-Generates interrupts at a software programmable frequency that is generally in the
Hertz range. (See CPU Clock Generation.) Thus permitting the implementation of a real-time clock or timer.
Interrupt bit cleared on a CPU read of the interrupt register.
2.1.9 Clock Generation
All chip clocks are derived from the one external crystal
connected between pins 22 and 23. This master clock also
doubles as the video dot clock. The crystal frequency is
constrained to lie within the range of 3 to 1B MHz. The CPU
clock is derived from the crystal clock by either using it directly or by dividing down by a factor of 1.5 (Figure 10).
~CRYSTALUP
1 CPU CYCU
.....::..
1
~
m".",
CPU
CLOCK
TLlDD/5526-17
FIGURE 10. CPU Clock Generation
The choice is software programmable through bit 0 in the
System Control Register. The exact selection is made in
consideration of the fact that the CPU clock must lie within
the range of 3 to 12 MHz. In addition, the choice of divide by
modes will also impact the display character cell width due
to the nature of the video controller. Specifically with -:- 1.5
7-15
•
I
~ r---------------------------------------------------------------------------~
o
-.::r
U)
Z
2.0 Functional Description
(Continued)
the cell width must be ~ 8 dots wide whereas with -;- 1 the
cell width must be ~ 6 dots wide.
Memory space. Up to 64k locations may be addressed over
the 16-bit System Bus. Data word widths may be 8 or 16 bits
depending upon whether external character attribute selection is used. The actual bus multiplexing mode is controlled
by bit 4 in the System Control register. The Video Controller
has the highest priority in obtaining Video Memory accesses
with the CPU getting in on a space available basis. If all
memory accesses are being taken by the Video Controller
(rarely), the CPU is put into a wait state should it try to access video memory. To ease accessing requirements and
boost throughput the Video Controller utilizes a 4-level data
FIFO which is normally kept full of display data.
The low clock rates necessary to implement Cursor Blinking, Character Blinking and the Real-Time Interrupt are derived by passing the vertical sync frequency through a 5-bit
Blink Rate Divisor Register, (Figure 11). The resultant frequency is used as the Cursor Blink Clock. This clock is then
further divided by 2 to yield the Character Blink and RealTime Interrupt Clocks. For example, to get a 1 Hz real time
interrupt, with a 60 Hz system, set the 5 bit Divisor Register
to 30 in order to yield a 2 Hz signal which is then divided by
2.
2.2.1 Display Memory Control Registers
VERTICAL
SYNC
FREQUENCY
CHARACTER BLINK
In order to facilitate the management of video data for such
features as a Screen scroll, memory paging and row lookup
the DMC utilizes a number of registers which address the
video RAM space. Each of these pointers is 16 bits wide
and writable or readable from the 16-bit HACCI ACC pair as
the case may be. There are 2 video data accessing modes
as determined by bit 5 in the SCR, Sequential and Table
Lookup. The functions of the pointer registers vary depending upon the accessing mode selected. Their designators
are:
REAL·TIME
INTERRUPT
TL/DD/5526-18
FIGURE 11. Blink Clock Generation
2.1.10 Oscillator Operation
The on-board oscillator circuit consists of a phase inverter
which, when used with an external parallel resonant tank,
(Figure 12a), will yield the required oscillator clock. Crystals
should be specified for AT cut and parallel resonant operation with the desired load capacitance (typically 20 pF). If
one desires to externally generate the clock and input it to
the chip, he may do so by driving XTAL 1 (pin 23) and XTAL2
(pin 22) as shown in Figure 12b.
HOME = Home address register. Read and write.
BEGD = Beginning of diplay RAM. Write only.
ENDD = End of display RAM. Write only.
CURS = Cursor address register. Read, Write, Increment,
Decrement.
,.----1 ::>0---....- . TO INTERNAL CIRCUITS
SROW = Status section register. Write only.
CRSR = Current row start register. Not directly accessed.
XTAL1 23
2.2.2 Sequential Access Mode
In this mode display data is accessed from sequential address locations in the video memory until the data requirements for the current screen field are fulfilled. The location
from which the first display character is taken is the one
pointed to by the HOME register. By modifying the contents
of HOME one may implement a row scroll or paging operation. The BEGD and ENDD are used to control the wraparound condition when HOME gets near the end of available display RAM as determined by ENDD. In this instance,
when sequential accessing brings us to the end of memory
as pointed to by ENDD, the controller wraps around by
jumping back to the beginning of display memory as pointed
to by BEGD. The value in ENDD should be the last location
in display memory + 1. Also the size of the display memory
between BEGD and ENDD (ENDD - BEGD) must be an
integral number of display rows. The CURS in both accessing modes merely identifies the current cursor position in
display memory so that the cursor characteristics can be
inserted into the video at the appropriate character position.
TL/DD/5526-19
FIGURE 12a. TMP Oscillator
+5V
..... ><>-....___........;2~3 XTAL1
+5V
1K
>c~.-.-.;;2~2 XTAL2
TTL
TL/DD/5526-20
Note: Use AS TTL devices if faster than 12 MHz.
FIGURE 12b. External Oscillator Mode
In addition to the display of normal video data one may elect
to have a special status section displayed using data from a
separate section of video memory. The status section would
consist of an integral number of display rows on the bottom
of the screen. This feature operates by reloading the video
RAM pointer with the contents of SROW when the desired
row position at which to start the status section comes up.
The particular row at which the status display starts is defined in the Timing Chain. Once the video RAM pointer is
jumped to SROW, data accessing again proceeds sequentially from there until the data requirements for the current
field are satisfied.
2.2 DISPLAY MEMORY CONTROLLER
The video display data resides in the external Video Memory which is managed by the Display Memory Controller
(DMC) through the System Bus. Either the CPU or the Video
Controller may access the display memory by presenting its
requests to the DMC. A maximum of three Video Memory
accesses (Reads or Writes) can be performed by the DMC
during each CPU instruction execution cycle. Because the
CPU can access the Video Memory, one may expand CPU
1/0 or data memory by memory mapping into the Video
7-16
z
2.0 Functional Description
en
.c:.
(Continued)
o
C11
TMP Video Section
CPU BUS
H SYNC
PEN
INPUT
V SYNC
VIDEO
TLIDD/5526-21
Whether a status section is used or not, upon accessing all
of the data necessary to display a field, the video RAM
pointer is reset to HOME in preparation for the display of a
new field.
174815141312111rl
b:
= CRYSTAL DOT CLOCK
DIVIDED BY 1
1) CPU CLOCK • CRYSTAL DOT CLOCK
DIVIDED BY 1.5
R CELL WIDTH
001) 6 DOTS PER CELL
(010) 7 DOTS PER CELL
(011) 8 DOTS PER CELL
(100) 9 DOTS PER CELL
(101) 10 DOTS PER CELL
SYSTEM BUS MUX MDOE
(D) OUTPUT ONLY ON S88-15
(1) 16 BIDIRECTIONAL UNES ON SBD-1I1
VIDEO MEMORY ACCESSI NG MODE
(0) SEQUENTIAL ROW START ADDRESSES
(1) TABLE LOOKUP
SHARED INTEN/FO CLK PIN CO NTROL
(0) iNffilSJTY ATTRIBUTE SIGNAL GATED
TO EXTERNAL PIN
(1) FIFO OUT CLK GATED TO EXTERNAL
PIN
SHARED Vio CLK/fiC[R PIN CoNTRo L
( 1) VIDEO DOT CLOCK GATED
TO EXTERNAL PIN
(0) FIFO IN CLOCK GATED
TO EXTERNAL PIN
D) CPU CLOCK
2.2.3 Table Lookup Mode
The CRSR (transparent to the user) is a pointer to the address of the first character in a display row. It is required
because each time a scan line is displayed, all display characters in the row must be accessed anew. Since a row is
made up of a number of scan lines, we must recover the
address of the first character in the row for each scan in the
row. After a row is done, the CRSR is normally advanced to
point to the first character in the next row.
In table look-up mode the starting memory location of the
next row is loaded into the CRSR from the HOME register at
the end of each row. The HOME register was presumably
updated by the CPU since the last end of row.
A CRSR load also generates the internal End of Row interrupt which the CPU will use as a signal to reload HOME.
Finally, reloading HOME will clear out the End of Row interrupt. If the status section feature is used, upon reaching the
begin status row location the CRSR will be loaded with
SROW instead of HOME for that row. After which CRSR will
revert back to load from HOME for the remaining rows on
the screen.
TL/DD/5526-22
OBit 0 is set to 1 by RESET and bit 7 is set to 0 by RESET.
FIGURE 13. System Control Register
2.4 VIDEO CONTROL REGISTER
Through the Video Control Register (VCR) the user specifies several video display features to the chip. It is an a-bit
write only register which is loaded from the CPU accumulator.
2.3 SYSTEM CONTROL REGISTER
Through the System Control Register (SCR) the user specifies several important chip operational conditions. It is an
a-bit write only register which is loaded from the CPU accumulator.
7-17
2.0 Functional Description
(Continued)
2.5 CRT REFRESH LOGIC
All video timing and clocking signals are derived from a series of counters and comparators called the Video Timing
Chain. The chain is driven by the dotl crystal clock and ultimately divides down to the very slow blink clock, (Figure
15). By having the program initialize the registers in the
chain a user may specify all aspects of video generation.
(0) BLINKING CHARACTER
(1) BLINKING FIELD (IF REVERSE VIDEO)
(0) BLINKING CURSOR
(1) STATIC CURSOR
(0) CURSOR OVERWRITES CHARACTER
(1) CURSOR REVERSES VIDEO
' - - - - - ( 0 ) WHITE DOTS ON BLACK BACKGROUND
(1) BLACK DOTS ON WHITE BACKGROUND
~---- (0) INTERNAL ATTRIBUTE LATCHES
(1) EXTERNAL ATTRIBUTE MEMORY
' - - - - - - - - (0) V. SYNC, H. SYNC AND VIOEO
OUTPUT OISABUD. DISPLAY MEMORY
ACCESSES FROM THE CPU ONLY (NO
SCREEN REFRESH)
(1) V. SYNC, H. SYNC AND VIDEO
OUTPUT ENABLED. NORMAL DISPLAY
ACCESSES.
' - - - - - - - - - - ( O X ) NORMAL ALPHANUMERICS AND
BLOCK GRAPHICS
(10) EXTERNAL CHARACTER GENERATOR
(11) PIXEL GRAPHICS
The chain also controls the size and placement of the cursor and underline attribute within a character cell as well as
the cell partitioning for block graphics display. All totaled,
the chain consists of 14 wire only registers. They are loaded
indirectly by using the Timing Chain Pointer (TCP), a 4-bit
pointer to registers in the chain, and the MOV @TCP, A
instruction.
TL/DD/5526-23
OBit 5 is set to 0 by RESET.
FIGURE 14. Video Control Register
COMPARE
REGISTERS
HORIZONTAL SYNC
BEGIN
HORIZONTAL SYNC
END
HORIZONTAL SYNC
HORIZONTAL BLANK
BEGIN
HORIZONTAL
VIDEO BLANK
INSERT STATUS ROW
VERTICAL SYNC
VERTICAL
VIDEO BLANK
DOT
COUNTER·MODULO
DETERMINED BY
SYSTEM
CONTROL
REGISTER
CRYSTAL
CLOCK
COUNTERS
CHARACTER
BLINK/REAL TIME
INTR.
TL/DD/5526-24
FIGURE 15. TMP Video Timing Chain
2.5.1 TMP Timing Chain Registers
TCP
o
Horizontal Timing
Horizontal Length Register -
HLR 7 bits
-
Total number of character cells in a horizontal scan and retrace.
-
Enter desired count - 1
Horizontal Blank Begin Register -
2
HBR 7 bits (Characters/Row)
-
Character position in horizontal scan after which horizontal blanking begins.
-
Enter desired number of displayed characters/row - 1.
Horizontal Sync Begin Register -
HSBR 7 bits
-
Character position in horizontal scan after which horizontal sync begins (rising edge), HSBR
-
Enter desired count
+
2.
7-18
:s:
HLR.
z
2.0 Functional Description
U)
~
(Continued)
o
U1
2.5.1 TMP Timing Chain Registers (Continued)
TCP
3
Horizontal Timing
Horizontal Sync End Register -
HSER 7 bits
Character position in horizontal scan after which horizontal sync ends (falling edge), HSER ~ HLR.
Enter desired count + 2.
Note: The polarity of the horizontal sync signal can be inverted by switching the values in the two horizontal sync registers.
TCP
Character Height Definition
4
Character Scan Height Register - CSHR 4 bits (see Figure 16a)
High
- Scan line height of a character cell.
Nibble
- Enter desired number of scan lines - 1.
4
Extra Scans/Frame - ES/F 4 bits
- Number of extra scans to be added to a frame if desired.
Low
Nibble
- Enter desired number of extra scans -1.
-
To get no extra scans make ES/F = CSHR. ES/F must be
~
CSHR.
Vertical Timing
TCP
5
Vertical Length Register - VLR 5 bits
- Total number of display and retrace rows in a frame.
6
Vertical Blank Register -
-
Enter desired number of rows - 1.
VBR 5 bits (Rows/Screen)
Row position in vertical scan after which vertical blanking begins, VBR < VLR.
- Enter desired number of displayed rows - 1.
Vertical Sync Begin Register - VSBR 4 bits
7
High
Scan line position in first blank row at which vertical sync begins (falling edge). Sync starts 1.char time after
Nibble
blanking for that line starts (except when VSBR = CSHR sync will start 1 char time after blanking of the last
displayed scan line).
Enter desired scan line position - 1.
Vertical Sync End Register - VSER 4 bits
7
Low
Scan line position after start of vertical sync at which vertical sync ends (rising edge). Sync ends 1 char time
Nibble
after horizontal blanking for that scan line start.
Note: If VSER
8
Enter desired scan line position - 1.
= VSBR there will be no vertical sync signal.
Status Row Begin Register -
SRBR 5 bits
Row count after which the status row is inserted.
Enter desired row position - 1.
TCP
Cursor and Graphics Control
9
Rate 5 bits
Divider driven by the vertical sync frequency to yield the slow cursor, character and real-time blink rates.
Enter desired divisor - 1.
Duty Cycle 3 bits
Approximate ON time of blink signal.
000 = shortest, 111 = longest (100 = 50% duty cycle).
Blink
Upper
5 Bits
Blink
9
Lower
3 Bits
10
Graphics Column Register - GCR 8 bits
- Assign dot positions to left, middle and right character cell columns for block graphics operation.
11
Graphics Row Register - GRR 8 bits
Defines scan count at which middle row for block graphics characters begins (upper nibble) and at which
bottom row begins (lower nibble). The middle row (upper nibble) must be ~ 1.
12
Underline Size Register -
Enter desired scan count - 1.
13
USR 8 bits (see Figures 16a, b, c)
Defines the beginning (upper nibble) and ending (lower nibble) scan lines for the underline attribute. Values
must be ~ CSHR.
Cursor Size Register - CSR 8 bits (see Figures 168, b, c)
Defines the beginning (upper nibble) and ending (lower nibble) scan lines for the cursor. Values must be
CSHR.
7-19
~
0._.
.."
o
~
en
z
2.0 Functional Description
r-
SCR BITS 1,2,3-1
(Continued)
SCAN UNE
r~
_..........
.................
SCAN UNE
SCAN LINE
i~
a. Character
Cell Format
Specification
b. Underline Size
Register = 90
c. Cursor Size
Register = 9A
(OB, OC, 00, OE, OF)
may also be used
FIGURE 16. Underline and Cursor Register Operation
d. Cursor Size
Register = 48
TL/DD/5526-25
Note: The internal cursor flip-flop gets set to ON whenever a scan line corresponding to the begin cursor nibble is reached, and gets set to cursor OFF whenever a
scan line corresponding to the end cursor nibble is reached. The cursor attributes are inserted whenever the character position being displayed corresponds to the
one pointed to by the cursor address register. A similar situation applies for characters with the underline attribute selected. Therefore, care should be taken when
setting the ES/F register and setting the cursor and underline sizes. In particular the ES/F value should not be between the upper nibble and lower nibble values of
the underline size register or between the upper nibble and lower nibble values of the cursor size register. To use the cursor as a pointer without displaying it, set
the lower nibble of the cursor size register to a value less than CSHR and the upper nibble to a value greater than CSHR.
2.5.2 TIMING CHAIN LOAD VALUE EXAMPLE
scan lines in a cell. The underline attribute will actually be a
strike through dash occupying the 4th scan line from the top
in a cell.
It is desired to have a display field of 80 columns by 25 rows
with the last screen row being a status row. It has been
determined that 25 character width times will be necessary
to complete horizontal retrace and that Horizontal sync
should be positioned to start a full seven character times
after blanking and end twenty characters after blanking to
give us a total sync width of 13 character times. (See Figure
17 for example.)
Our line width is 80 displayed characters plus 25 for retrace
making HLR = 80 + 25 - 1 = 104. Blanking will start after
the 80th character so HBR = 80 - 1 = 79. To achieve
seven character times after horizontal blanking, HSBR =
87 + 2 = 89. To achieve twenty character times after
blanking HSER = 100 + 2 = 102 (note 102 - 89 = 13
total). Cell height is 12 lines so CSHR = 12 - 1 = 11.
Since there are 12 scan lines per cell or row, vertical retrace
will require 23/12 = 1 row and 11 scan lines. This makes
our total row count VLR = 25 + 1 - 1 = 25 and ES/F =
11 - 1 = 10. Thus, timing chain location 4 would be coded:
1011 1010. We will display 25 rows soVBR = 25 - 1 =
24. Vertical sync will start at the beginning of the fourth scan
Additionally, vertical retrace will take 23 scan line times to
complete with vertical sync starting three scan line times
after vertical blanking begins and occupying a total period of
11 scan lines.
It is desired to make the character cells 12 scan lines tall.
The cursor will be a block shape and occupy the bottom 11
=---=~_-=--~HBR-HS-BR~HSER_HLR====I-=-~-I-I-II
:1-1;
.--.--i------------------; - - - -- - - -,
DISPLAY INFORMATION
BLANKED
SRBR-I-+---<~
VSBR-l--=:!:::::;;!----------------------I
VSER-
t==1
r--
L
BLANKED
--------------------------------
ESIF
FIGURE 17. Typical Video Screen Format Specification
7-20
TL/DD/5526-26
z
2.0 Functional Description
en
~
(Continued)
o
line of the row after blanking begins so VSBR = 4 - 1 = 3.
It will run for 11 scan lines or specifically the 4, 5, 6, 7, 8, 9,
10, 11, 12, 1, 2 ending at the beginning of the 3rd so VSER
= 3 - 1 = 2. The status row will be after the 24th so
SRBR = 24 - 1 = 23. To specify the underline and cursor
sizes one must remember that the first scan line is numbered O. To get our 11 line block cursor we begin after the 0
line and end at the end of the 11 line making CSR = 0000
1011. The underline dash will be USR = 0011 0100. Note
that the CSHR determines the scan counter modulo and if a
scan compare register value (ES/F, VSBR, VSER, USR,
CSR) is never reached, the signal end or begin will never be
initiated.
trol word bit assignments are detailed in Figure 18. The
scope with which a particular set of attributes affects the
display depends upon whether attribute control is internal or
external as determined by bit 4 in the VCR.
Attributes are present if the corresponding bit is a ZERO
(low).
2.6.1 Internal Attribute Selection
In internal mode attribute control comes from one of two
internal attribute latches designated ALO and AL 1, either of
which is directly loadable from the CPU accumulator. The
choice of which of the two is used for a particular display
character is determined by bit 7 (MSB) in the display memory data byte with 0 = ALO and 1 = AL 1. (Characters are
represented in display memory as ASCII values occupying
the low 7 bits of each 8-bit byte thus leaving bit 7 free for
attribute control.)
2.6 ATTRIBUTES
Eight independent attributes may be inserted itno the video
dot stream to affect display characters on either an individual or global basis. The eight attributes along with their con-
2.6.2 External Attribute Selection
In external mode each display character has associated
with it, a dedicated attribute field in the form of a high 8-bit
extension to the regular display memory character byte. To
use this mode the system bus msut be configured for 16-bit
bidirectional operation (SCR bit 4 = 1) and external attributes must be selected (VCR bit 4 = 1).
ATTRIBUTE LATCH BIT
ATTRIBUTE MEMORY BIT
'-----REVERSE VIDEO
'-------HALF INTENSITY
'--------BLINK
'---------DOUBLE HEIGHT
' - - - - - - - - - - D O U B L E WIDTH
'-----------UNDERLINE
'-----------------BLANK
'----------------GRAPHICS
2.6.3 Attribute Processing
Each of the eight attributes may be independently enabled
thus yielding a number of possible combinations. The exact
processing involved is shown in Figure 19. Note that attributes are always present. Whether any of them are active
depends upon the particular control bit being enabled in the
latch or memory.
TLIDD/5526-27
FIGURE 18. Attribute Bit Assignments
DOUB~~~I~~~_""
U1
___~
SCAN UNE
CLDCK
UNDERUNE ATTRIB. 5
VIDED
DATA
,.
BUNK FIELDI
CHAR VCR 0
HALF INTENSITY ATTRIB. 1 - - -•• INTENSIFO
CHAR BUNK ATTRIB. 2
TL/DD/5526-28
FIGURE 19. TMP Attribute Processing
7·21
an
o
~
(IJ
z
2.0 Functional Description
(Continued)
2.6.4 Attribute Operation
Reverse Video: A character and its surrounding cell are reversed in video from what was selected for the rest of the screen.
Half Intensity:
To use the half intensity function the shared INTENSITY /FO ClK pin (25) must be selected for INTENSITY
operation by setting SCR bit 6 low. In operation the half intensity pin will be low whenever a character for which
the attribute is active is being displayed. To perform the actual attenuation function external circuitry must be
connected between the INTEN and Video Output pins. In fact the signal may be used for another purpose such
as switching between two colors.
Blink:
A character or the field around it blinks as selected by VCR bit
Double Height:
A designated character is stretched out so that it will occupy a 2-row tall space. This attribute is implemented
by slowing down by half the scan line stepping to the internal character generator. To use this attribute the
desired double high character must be placed into the two display memory locations corresponding to the top
and bottom row positions. For both locations the double high attribute is set. In addition the Blank attribute for
the bottom character is also set to tell the controller it is the bottom half of a double high character. The double
high attribute has no effect on element graphics or on pixel graphics displays. If an external character generator is used special circuitry must be employed to implement double high characters.
Double Width:
A designated character is stretched out so that it will occupy a 2-character cell wide space. This attribute is
implemented by slowing down by half the clock to the video dot shifter. To use this attribute the desired double
wide character must be placed in the left character position and the double wide attribute bit set. The following
character position (right) can have any character as it will be ignored.
Underline:
If set this attribute causes the underline figure to be added to the video dot stream. Since the underline, like the
cursor, can be specified as to position and size in the character cell, the underline can be an overline, block,
strike through or anyone of a number of effects. The underline overwrites any dot where it overlaps the
character.
Blank/Double
High Bottom:
A character is inhibited from being displayed while still allowing it to be stored in the display memory. If this
attribute and the double height attribute are set for the same character, the normal blank function is disabled
for that character position and the character is displayed as the bottom half of a double height character.
Graphics:
This attribute determines whether the video memory data byte as accessed by the display memory controller is
routed through the character generator or block graphics control logic. If routed through the block graphics
logic (attribute active) the effect on the video display will be as described in the Block Graphics section. Note
that because Block Graphics mode is selected as an attribute it may be mixed in with normal alphanumerics
characters. Also all other attributes with the exception of double height operate on the block graphics characters.
o.
2.7 CHARACTER GENERATOR
2.7.1 External Character Generation
The internal character generator holds 128 characters in a
7 x 11 matrix. The standard character sets are addressed
using 7-bit ASCII codes stored in the display memory. When
operating with fonts smaller than the maximum of 7 x 11,
zeroes are encoded into the unused bits. When putting out a
character the video controller always starts character generation on the second scan line of a row, leaving the first
scan line blank. Similarly, the first (left) column in a character cell is blanked with character generation starting on the
second column. Therefore, the specified cell size must be
one greater in height and width than the display characters
(including descenders) otherwise they will be chopped off. If
the character cells are larger than the internal 7 x 11 matrix,
blank dots will be put out after exhausting the internal generator (See Figure 20 for example.)
The chip may be used with an external character generator
by switching over to a pixel graphic display mode with modified address stepping as controlled by VCR bits 6, 7. In this
mode an external character generator supplies pixel data to
the chip as depicted in Figure 21. Character addressing
comes from the display memory and scan line stepping from
a 4-bit counter clocked by the Horizontal Sync. Scan line
synchronization is achieved by using the Scan Count Clear
signal coming out on RE11, pin 36. After the display of a row
it pulses low to initialize the scan line counter for the start of
a new row. In pixel mode both the character and any spacing between characters must be encoded into the external
character generator. In addition, the chip will access and
use at most 8 bits of pixel data for each character cell. However, if the cell width is specified to be 9 or 10, the ninth and
tenth dots will repeat what was coded into the first. Therefore, assuming at least one dot spacing between characters, external fonts can at most be seven dots wide.
........ ........ .
·.. · ........ .
· .•.......
ALWAYS
BLANKED
ALWAYS
BLANKED
ALWAYS_! • • • • • • • •
BLANK
l! ...
··•......
··· ·· ·1·.: ......
· · · · · ..
•••••••• •
·· •. .
1• • • • • • •
No limitations apply to the height of a character as long as
the external generator can supply all of the scan lines as
specified by the CSHR. As in regular pixel mode the lSB
brought in is the first dot put out.
· .:
• • • • • • • • • 1• • • • • • •
• •• •
.•. .
•
·1·.· · · .•.
Since the eighth data bit is used for character generation it
cannot effectively be used for internal attribute latch selection although one of the latches will be selected every data
byte. Therefore, both internal attribute latches must be loaded with the same values. If external attribute operation is
specified the full 8-bit high order attribute field is available
for usage.
.: •••. · ·
·1·.·
· .1. e ..... · ·
• • 1• • • • • • • • •
.:
I
TL/DD/5526-29
FIGURE 20. Character Cell Format
7-22
z
2.0 Functional Description
en
0I:loo
(Continued)
o
U1
J
I
ADDRESS
LATCH
..L
.....
.....
....".
,.
DISPLAY
RAM
I
V SYNC
VD
....
'IIIf
•...+ •
WRITE BUFFER
I
...
,..
....,.
i
NS405
ALE
RE11
RAM
RD
7 BITS
4 BITS
T ~ ..
4-8IT
COUNTER
I
V
CHARACTER
GENERATOR
IC~
H SYNC
SBO-SB15
DATA
....
1
RAM ALE
ro-
LATCH
I--
RAM
WR
I
CLR
CLR EXT SCAN CNt
TL/DD/5526-30
FIGURE 21. External Character Set Implementation
2.8 BLOCK GRAPHICS
2.8.1 Graphics Partitioning
Block graphics is an alternative display mode to normal al·
phanumerics which is selected through attribute bit 7. Example (Figure 22). It can operate on a character cell by
character cell basis (see Attributes) and words by rerouting
display memory bytes through the Block graphics logic instead of the internal character generator.
0000 • • • • •
0000 • • • • •
0000 • • • • •
.........
.........
.........
.........
ClDDU • • • • •
CAN BE USED TO DRAW VERTICAL
AND HORIZONTAL UNES
OODDOODao
000000000
000000000
OODOOOOOO
0000 • • • • •
0000 • • • • •
ooooaoooo
0000.0000
000080000
0000.0000
0000.0000
• • • • • 0000
000000000
000000000
-.-MIDDLE ROW
5
-'-BOTTOM ROW
MIDDLE COLUMN
000080000
0000 • • • • •
0000 • • • • •
DDOO.OOOO
0000.0000
0000.0000
OODo.ao 00
DOOO.OOOD
0000.0000
LloOO • • • • •
4
LEFT CDLUMN-----'
Dooooaooo
aOOQDODOO
000000000
DaODoaCHlO
RIGHT COLUMN
.........
.........
......... ........ .
DOCO • • • • •
DaDO • • • • •
-.-TOP ROW
000080000
DDDO.COOC
0000.0000
0000.0000
0000.0000
0000.0000
OOClO • • • • •
o
TL/DD/5526-32
FIGURE 23. Block Graphics Cell Partitioning
The registers defining the graphics areas function as follows:
TL/DD/5526-31
The Graphics Row Register - 8 bits (GRR) is divided into
the following two (2) registers:
FIGURE 22. Example Block Graphics Display Patterns
The Graphics Logic operates by partitioning the character
cell space into nine possible areas as shown in Figure 23
and then using the seven lower bits in the display data byte
to turn these areas on or off. In this way one can draw
contiguous lines or simple geometric figures while at the
same time displaying alphanumeric characters in other
cells.
• Graphics Middle Row, (GMR):
Defines the scan count at which the middle row begins
(4 most significant bits of GRR).
• Graphics Bottom Row, (GBR):
Defines the scan count at which the bottom row begins
(4 least significant bits of GRR).
The partitioning of the cell is controlled by two timing chain
registers which specify two Horizontal and two Vertical cut
off points to the graphics logic. Through these two registers
one can make the sections as large or as small as desired,
even eliminating sections entirely. Note that data bits 0 and
5 each control two sections as depicted in Figure 23.
See Figure 24.1a for row example.
7-23
•
&t)
o"'II:t
U)
Z
2.0 Functional Description
(Continued)
The Graphics Column Register - 8 bits (GCR) controls vertical partitioning through bit patterns as follows: (See Figure
:::;C::I:lOCD::I=OC:Jr;:J • • • o:Jooo:Jo:J:Jo:JO:1nwo
::lOCO::lO []:;::; :J0>:l0 • • • • 00000000 00 OO:J [] 01
CO:J:J 00 []:J 0000 • • • • • 0 :JO:J O:JOOOO:lO :JO"
:JOOO:J:JODD:JDO • • • • • ULJOOOQUOOO:JO:J • • •
0000::1::100000 • • • • • • 0000000::1::10::10 • • • •
~auIJCOCOOO • • • • • • • OOOOOOO:JOO:J • • • • •
o:J:Joocaoo ••••• OO.OOOO:JOODOO • • • • • O
[] 000 DODO • • • • lao 01000000 0 00 • • • • • 00
0::10000 0 • • • • • 000 0 100000::1 0 o ••••• u aD
000000 • • • • • 0 :::10001000 00::10 • • • • • 00::10
0000 :J • • • • • 00 00001000::1 0:1 • • • • • 000 00
OOCO • • • • • OOOOOOO.OOOOO • • • • • :JOOO:J.
0::10 • • • • • 00000 • • 0 • • 000 • • • • • 00000 • •
(10 • • • • 100000 • • • 0 • • 00 • • • • 100000 • • •
:J • • • • • oooao •••• o •••••••• oonClO ••••
• • • • • :JOOOO • • • • • O • • • • • • • C;OOO:J • • • • •
• • • • 00000 • • • • • • 00 • • • • • 00000 • • • • • 0
••• ocooc ••••••• CO • • • • OCOOO • • • • • OO
24.)
7
L
1
5
L
L
3
R R
Z 1 0 _OCR
X X X _ I DOT FIELD WIDTH
L
L
L
R
R
L
L
L
R R R
R X
L
L
L
L
R R _ 9 DOT FIELD WIDTH
4
R
R
• • 00000 • • • • • 00.0000000000 • • • • • 000
.oc::lco • • • • • oon.ooooooooo • • • • • OOOO
00000 • • • • • 0000.00000000 • • • • • 00000
u:J:::lO • • • • • OOOOO.OOOOOO::l • • • • • OOO:::lO:J
OOO • • • • • OOOOOO.OOOOOO • • • • • OOOO::lOU
OO • • • • • OOOOOOO.OOOOO • • • • • OO:::lOO::lOO
O • • • • • OOOOCOOO.OOOO • • • • • ::IOOOOOO::lO
• • • • • 000000000.000 • • • • • 0000::1000::10
• • • • 0::1 ::100 0::1 0 0::1 • • 0 • • • • • 000 0 0 000 oeo
• • • :JOOOOOO:::lL:lOc • • • • • • • OOOUO::lUOCOOO
• • 0:JO::lOOOOOOOO • • • • • • 0000000000000
.0::1::1 00 C 0 00 000 0 • • • • • 00 000 ooooon nnn
X X _ 7 DOT FIELD WIDTH
R
_ e DOT FIELD WIDTH
oonnOOClOOO:JUtlOo ••• ooooouooooooooo
TLlDD/5526-33
LJU:JtJl)lItHlIJU'JUUUUU.OOOCOL:luuoooononc
TL/DD/5526-34
FIGURE 24. Block Graphics Column Partitioning
FIGURE 25. Example Pixel Graphics
the 10th bit will merely repeat the 9th bit. Attributes are still
operable in pixel mode, on a data byte basis, with internal
and external operation possible. With internal attribute latch
operation the same values must be loaded into both latches
since the usual latch select bit is now being used for pixel
control. Unless, however, only a 7 dot wide cell is used leaving the 8th bit free. With external attribute operation we are
now limited to a 7-bit attribute field since pixel data can now
occupy 9 of the 16 bus bits. Because of this the LSB attribute, Reverse Video is totally disabled from operation in
Pixel Graphic mode. This also applies to internal attribute
latch operation. Note, however, that reverse entire screen
video is still operable. Address sequencing through the video memory is sequential with as many data bytes being read
in as is necessary to satisfy the pixel requirements of the
screen.
6 5043 21
O!
I
11
: +-TOP
2!
3
:
~!
!
I
I
I
1
+-IIIOOLE
I +-BOTTOII
51
61
I
L
II
TL/DD/5526-44
GRR = 24
GCR = 60 (0110 OXXX)
cell size = 6 x 7
FIGURE 24.1a Block Graphics Example
For all bits in the Graphics Column Register, a one assigns
that bit position to the middle column. A zero in an L bit
position assigns that bit position to the left column. A zero in
an R bit position assigns that bit position to the right column.
There is always at least one middle dot although the left and
right sections may be eliminated entirely. For 10 dot wide
cells the 10th bit will repeat the 9th bit. An easy way to
determine the column partitioning is to fill the GCR with all
ones, thereby making it one large middle section. Then,
starting from the outermost Land R bit positions, put zeros
in until the left and right sections are the sizes needed.
2.10 LIGHT PEN
Activation of the light pen interrupt causes the horizontal
and vertical screen position of the currently displayed character to be latched into the Horizontal Light Pen Register
HPEN (7 bits) and Vertical Light Pen Register VPEN (5 bits)
respectively. Both HPEN and VPEN may be read into the
CPU accumulator. The values latched remain in VPEN and
HPEN until another light pen interrupt latches new values.
2.9 PIXEL GRAPHICS
2.11 UART
When bits 6 and 7 of the Video Control Register are both
set to 1, the character generator and block graphics circuits
are disabled. Video output directly reflects the contents of
the display memory byte on a pixel (dot) per bit basis with
data output LSB first. Example (Figure 25).
The UART features full duplex operation with double buffered Receive and Transmit sections. Baud rate generation
is fully programmable through a 2-stage divider chain. CPU
control of the UART is extensive with polled or interrupt
driven operation possible.
Nine bits at a time are accessed from each video memory
location with as many bits being used as defined in the character cell width specification. If a cell width of 10 is specified
RECEIVE BUFFER
SI
RI BUFFER FULL
UART CDNTRDL
UART STATUS
RECEIVE SHIFTER
CRYSTAL I
SO
TRANSMIT SHIFTER
(OUTPUT REGISTER)
TI SHIFTER EMPTY
TRANSMIT BUFFER
TI BUFFER EMPTY
TL/DD/5526-35
FIGURE 26. TMP UART Block Diagram
7-24
z
2.0 Functional Description
en
~
(Continued)
o
U1
2.11.1 UART Control
2.11.2 Baud Clock Generation
UART Status Register (STAT): Contains error and status
bits which reflect the internal state of the UART. Read into
CPU accumulator. Bits 0, 5 are the same as those found in
the internal interrupt register.
The basic BAUD clock is derived from the crystal frequency
through a two-stage divider chain consisting of a 3.5-11
prescale and an 11-bit binary counter. (Figure 29). The divide factors are specified through 2 write only registers
shown in Figure 30. Note that the 11-bit Baud Rate Divisior
spills over into the Prescale Select Register. The correspondences between the 4-bit Prescale Select and Prescale factors is shown in Table I. There are many ways to calculate
the two divisor factors but one particularly effective method
would be to try to achieve a 1.8432 MHz frequency coming
out of the first stage then use the BAUD Rate Divisor factors
shown in Table II.
I • I 5 I 4 I 3·1 2·11· I 0 1
L..-J
17
lli
L1 ..
L;
-
UART RECEIVE BUFFER FULL
PARITY ERROR DETECTED
1 = FRAMING ERROR DETECTEO
' - - - - - 1 = OVERRUN ERROR OETECTED
' - - - - - - - - 1 = TRANSMInER OUTPUT REGISTER EMPTY
(OUTPUT SHIneR)
' - - - - - - - _ 1 = TRANSMInER BUFFER EMPTY
(4-- PRE SCALE REGISTER -1 4
BAUD REGISTER ----+t
I 3 I 2 \1 \ 0 \ X 110 \ 9 \ 81 716 \ 5 I 41 312 11 I 0 I
' - - - - - - - - - ALWAYS ONES
TLlDD/5526-36
UART Status Register bits 1, 2, 3 are only cleared on a chip reset or a read
of the UART Receive Buffer. If another word were to come in before the
Receive Buffer could be read the errors associated with the new word would
add to those already present. The receipt of a new word can cause the three
bits to go from a 0 to a 1, but not from a 1 to a o.
PRESCALE SELECT
TL/DD/5526-39
FIGURE 30. UART BAUD Clock Divider Registers
FIGURE 27. UART Status Register
TABLE I. Prescale Factors
Note: The Transmit Output Register Empty flag is set to one whenever the
transmitter is idle. The flag is reset to zero when a data character is
transferred from the Transmit Buffer to the Output Register. This
transfer does not occur until the next rising edge of the internal UART
Transmit Clock. The Transmitter Output Register Empty flag occurs at
the beginning of the last stop bit.
UART Control Register (UCR): Contains control bits which
configure the format of transmitted data and tests made
upon received data. Written to from CPU accumulator.
171615·14131211101
I
I I
lS
BAUD RATE DIVISOR
D = 7 BITS (EXCLUDING PARITY)
1 = 8 BITS (EXCLUDING PARITy)
1 STOP BITTRANSMlmo
1 = 2 STOP BITS TRANSMITIED
(RECEIVER ALWAYS CHECKS FOR ONE STOP BIT)
= PARITY DISABLED
1 = PARITY ENABLED
00 DOD PARITY (IF PARITY
ENABLED)
01 = EVEN PARITY ( IF PARITY
ENABLED)
10 = MARK (1) (IF PARITY ENABLED)
11 = SPACE (0) (IF PARITY ENABLED)
' - - - - - - - - 0 BREAK DISABLED (NORMAL
SERIAL OUTPUT)
1 = SERiAl OUTPUT FORCED LOW
(SPACE)
L-_ _ _ _ _ _ _ 0 = NO LOOP BACK
oo
=
Prescale
Select
Prescale
Factor
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
10.5
11
TABLE II. Baud Rate Divisors (1.8432 MHz Input)
=
Baud
Rate
110
134.5
150
300
600
1200
1800
2400
3600
4800
7200
9600
19200
1 .. SERiAl OUTPUT INTERNALLY
LOOPED BACK TO SERIAL INPUT.
OUTPUT STill ACTIVE.
'----------0 ..
TRANSMInER ENABLED
1 '" TRANSMITIER DISABLED (DATA
IN TRANSMIT BUFFER NOT
TRANSFERRED TO TRANSMITIER
OUTPUT REGISTER)
TLlDD/5526-37
OBit 5 set to 0 by RESET.
FIGURE 28. UART Control Register
(110.03)
(134.58)
Baud Rate
Divisor (N - 1)
1046
855
767
383
191
95
63
47
31
23
15
11
5
fII
UART TRANSMIT
CLOCK
UART
MUI1IPlEX
REGISTER
+16
BAUD RATE
SELECT BITS
110-19.200 BAUD
11
UART RECEIVE
CLOCK
TL/DD/5526-36
FIGURE 29. UART BAUD Clock Generation
7-25
preparation for the display of the next frame, but the HLDA
will NOT turn off. Specifically, this will occur one scan time
before the end of vertical blanking. It is up to the designer to
be sure that the host is off the BUS before this happens or
suffer bus contention with the video controller. He can do
this by either predetermining the length of time the host has
to remain on the bus, or by using the end of vertical sync (as
shown in Figure 32) to signal the end of a safe DMA period.
If during DMA the CPU attempts to do a display memory
access it would be put into a wait state until DMA is concluded and normal memory accessing is resumed.
2.0 Functional Description (Continued)
The frequency coming out of the BAUD Rate Divisor is then
passed through the UART Multiplex Register. Through the
UART Multiplex Register one can specify that the Transmitter or Receiver clock be the same or a power of two multiple
of the other.
UART Multiplex Register (UMX): Contains the bits which
determine the divisor which is used to count down from the
primary baud rate when different rates are used for send
and receive (eight bits).
+sv
10kJ).
1.DIVIDEIY1
1-DMDEIY2
1.DMDEIY4
ONLY ONE fACTOR
MAY BE SELECTED
' - - - - - 1 • DMDE IY.
IIJ ATIME
L . . - - - - l • DMDE IY 1.
L . . - - - - - ' 1 • DMDE IY 32
L.....-----UNUSED (0)
L . . . . . - - - - - - ( O ) DMDED RATE IS USED fOR SEND
(1) DMDED RATE IS USED fOR RECEIVE
HLOA t-=:=3~S-+-:.t
HLO":
ALE t=-2....
1 --t--c>
TL/DD/5526-40
Tl.tP
FIGURE 31. UART Multiplex Register
The actual baud rate may be found from:
BR = Fc/(16*N*P*D)
Where:
BR is the Baud Rate
Fc is the external crystal frequency
N is one plus the value of the Baud Rate Divisor contained
in the Baud Rate Select Register and the Prescale Select
Register.
P is the Prescale Divide Factor Selected by the value in the
Prescale Select Register.
o is the Multiplex Register Divide Factor
~ 27
rmRt-:1.:.
7 _ _ _ _....
TL/OD/5526-45
Vertical sync should be programmed to end as late as pOSSible, but must
end at least one scan time before the end of vertical blanking.
FIGURE 32
4.0 Reset
3.0 Slave Processing
The TMP will reset if the RESET (32) pin is held at a logic
low « O.BV) for at least five CPU cycle times. This pre-supposes that the Vee is up, stable and within operational limits
(+ 5V ± 10%) and that the oscillator is running. For a power
on reset, time must be allowed for the power supplies to
stabilize (typically 50 ms) and the oscillator to start up. If
power supply noise or ripple causes Vee to exceed the
+ 5V ± 10% limits neither reset nor operation is guaranteed.
Internally, the RESET pin has a depletion load pullup that
typically acts as a 30 JlA current source from Vee in the
voltage range of interest. A typical reset circuit with a 0.5
second reset pulse is shown in Figure 33.
The TMP may be used as a slave video controller by having
a host system perform Direct Memory Accesses into the
display RAM. To assist in implementing such a system the
chip features two DMA control pinS-HOLD (Hold Request)
and HLDA (Hold Acknowledge). These two signals come
out on shared ROM Expand Bus pins REB and RE12. To
request a DMA access a host would activate HOLD (active
high and await the acknowledging HLDA from the TMP before proceeding with the DMA. The TMP only allows DMA
operations during the vertical blanking period and will activate HLDA in response to a HOLD shortly after vertical
blanking starts. In DMA mode all 16 TMP System Bus drivers are tri-stated while the bus control signals RAM ALE,
RAM RD, RAM WR go to their inactive (high)' states. A
HOLD request must arrive two CPU cycles before vertical
blanking starts; otherwise it will miss that retrace cycle and
will have to wait until the next one, one frame later. Once
DMA mode is entered, it is maintained for the duration of
vertical blanking regardless of the state of HOLD. Near the
end of vertical blanking the DMA mode will terminate in
TMP
SWITCH
..L
HIl
o-~'\0-4...+...:32=f iiffiT
f_
4~F~
TL/DD/5526-41
FIGURE 33. Typical Reset Circuit
7-26
z
4.0 Reset (Continued)
During RESET a number of internal registers are initialized as follows:
4.1 CPU
CPU Clock divide
= 1.5 (SCR bit 0 = 1)
Shared VIDClK/FI ClK = 0 (SCR bit 7 = 0, FI ClK gated to external pin)
= 0
Program Counter
= 0
Stack Pointer
Program Memory Bank = 0
RAM Register Bank
= 0
Timer Stopped
Instruction Register cleared
FO and F1 cleared
4.2 INTERRUPTS
Internal and External Interrupts disabled
Internal Interrupt Register set to 000011 XO
4.3 UART
Receiver initialized to look for start bit
Status Register set to 11110000
Transmitter initialized to wait for OUT XMTR instruction
Control Register bit 5 = 0 (No BREAK)
4.4 VIDEO
Video generation shutdown (VCR bit 5 = 0)
FIFO Cleared Out
Timing Chain Character Counter = O}
Timing Chain Scan Counter
==
__ O~ IN TEST MODE ONLY
Timing Chain Row Counter
Timing Chain Blink Counter
4.5 PIN STATES AT RESET
Pins 1-8 (SBO-7)
In TRI-STATE during reset and until either the CPU executes a MOVX instruction or bit 5 of
the VCR is set.
Pins 9-16 (SB8-15)
If bit 4 of the SCR is set, SB8-15 will behave like SBO-7. If bit 4 of the SCR is cleared, SB815 will act as outputs (any of which may be either high or low). Note that bit 4 of the SCR may
be one or zero at power-up.
Pin 17 (VID ClK/FI ClK)
High during reset and until bit 5 of the VCR is set.
Pin 18 (RAM ALE)
High during reset and until the CPU executes a MOVX instruction or bit 5 of the VCR is set.
Pin 19 (RAM WR)
High during reset and until the CPU executes a MOVX (of the output to display RAM variety)
instruction.
Pin 20 (RAM RD)
High during reset and until either the CPU executes a MOVX instruction or bit 5 of the VCR is
set.
Pin 21 (ALE)
Pulses continuously.
Pin 22 (XTAl 2)
Crystal input or master clock input.
Pin 23 (XTAl 1)
Crystal input.
Pin 24 (Gnd.)
Pin 25 (INTENS/FO ClK)
May be either high or low during reset.
Pin 26 (VO)
low (because of asserted blanking signals) from reset until bit 5 of the VCR is set.
Pin 27 (VS)
In TRI-STATE mode upon RESET, enabled when bit 5 of the VCR is set.
Pin 28 (HS)
low from reset until bit 5 of the VCR is set.
Pin 29 (EA)
Input only. (must be tied HIGH (V1H2»
7-27
en
~
o
U1
4.0 Reset (Continued)
Pin 30 (PSEN)
Pin 31 (RD)
Active during reset.
High during reset and until an IN PORT instruction is executed.
Pin 32 (RESED
Input only.
High during reset and until an OUT XMTR instruction is executed.
Pin 33 (SO)
Pin 34 (SI)
Input only.
If HOLD is low: low during reset. If HOLD is high: low at falling edge of ALE and during PSEN,
may be low or high at rising edge of ALE.
If reset asserted: low at falling edge of ALE and during PSEN, sampled value of internal Scan
Count Clear signal is output at rising edge of ALE.
Pin 35 (RE12/HlDA)
Pin 36 (RE11/SC ClR)
Pin 37 (RE10/INTR)
Pin 38 (RE9/lPEN)
Pin 39 (RE8/HlDR)
}
Pins 40-47 (REO-7; 1/00-7)
If reset asserted: low at falling edge of ALE and during PSEN. Always in TRI-STATE at rising
edge of ALE.
If reset asserted: low at falling edge of ALE, in TRI-STATE during PSEN, and may be either
high or low at the rising edge of ALE.
Pin 48 (Vee>
5.0 Extra Attributes
In order for the TMP CPU to access the additional attribute
bits special bus gating arrangements would have to be
worked out on the System Bus (Video Data Bus is at most
16 bits wide). Unless one were to run with internal attributes
or only use a few of the external attributes in which case the
unused bits could be used with the external FIFO. Whenever using the FO ClK the Intensity attribute is disabled since
they both share the same pin.
One may want to expand the external attribute field by adding more bits so that functions such as color (RedGreen-Blue drive) or grey scale may be implemented. Like
the eight attributes which the chip handles internally these
extra attributes would operate on a character cell basis. To
add attribute bits one would have to duplicate the internal 4
level character/attribute FIFO externally using fast MSI
chips. To assist in handling the external FIFO circuitry the
TMP features two FIFO clocking signals on pins 17 and 25.
The FIFO IN Clock (FI ClK) is used to strobe attribute data
into the external FIFO circuits in synchronism with the internal TMP FIFO. Its timing is identical to RAM RD but is only
active when the video does a display RAM read to load its
FIFO. The FIFO OUT Clock (FO ClK) pulses for 1-3 bit
times each time the video starts the display of a new character cell. The external FIFO would use the rising edge of
this signal to clock out or latch the attribute output.
6.0 TMP BUS Interfacing
The two external buses on the TMP, ROM Expand and System are easily interfaced to as shown in Figures 34 and 35.
Important bus information output from the chip is latched
using the rising or falling edges of the various control signals. I/O port information is read in through a TRI-STATE®
buffer chip such as an 81 lS96.
+5V
HLOA,
SCCLR, INTR, LP, HOLD
EA
AU~---1~--------------------------~
NS405
TLlDD/5526-42
FIGURE 34. TMP ROM Expand BUS
7-28
z
en
6.0 TMP BUS Interfacing (Continued)
~
o(II
~
08-015
I
I
CHIP
SELECT
I DECODING
L _____
....
74LS373
.... A8-A15
I
I ..
.....
'l1li
..
,.
S88-SB15
L
VIDEO RAM
OR
110 PORTS
.... AO-A7 ~
74lS373
....
I
NS405
RAM ALE
I ..
I ....
.,.
SBO-SB7
.III
~
RAM
RD
00-07
RAM
WR
sl
S
TL/DD/5526-43
FIGURE 35. TMP System Bus
TMP Registers (Excluding Timing Chain Registers)
TMP Registers
Associated Intructlons
CPU SECTION
A
# data
Rr
@Rr
=
=
=
=
Accumulator - 8 bits
data immediate
Register
Register pointed to by RO or R1
ADDA,Rr
ADDA,#data
ADDA,@Rr
AD DC A, Rr
ADDC A, # data
ADDCA,@Rr
ANLA,Rr
ANLA,#data
ANLA,@Rr
CLRA
CPLA
DAA
DECA
DECRr
INCA
INCRr
INC@Rr
MOVA,Rr
MOVA,@Rr
MOVA,#data
MOVRr,A
MOV Rr,#data
MOV@Rr,A
MOV @Rr,#data
MOVPA,@A
MOVP3A,@A
RLA
RLCA
RRA
RRCA
ORLA,Rr
ORLA,@Rr
ORLA,#data
SWAP A
*MOVHACC,A
*HACC
= High Accumulator - 8 bits
*MOVA,HACC
C
= Carry Bit
CLRC
CPLC
JNCaddr
XCHA,Rr
XCHA,@Rr
XCHDA,@Rr
XRLA,Rr
XRLA,@Rr
XRLA,#data
JBn addr
JNZ addr
JZaddr
DJNZ Rr,addr
JC addr
*LONG RO = Register Pair, RO, RA
*DECL RO
*MOVLRO,A
*INCL RO
*MOVXA,@RO
*MOVLA,RO
*MOVX @RO,A
*LONG R1 = Register Pair R1, RB
*DECL R1
*MOVLR1,A
*INCL R1
*MOVXA,@R1
*MOVLA,R1
*MOVX@R1,A
T
= Timer - 8 bits
MOVA,T
STRTT
MOVT,A
*JNTF addr
STOPT
JTF addr
FO
F1
=FlagO
= Flag 1
CLRFO
CLR F1
INTR
= Interrupt Register- 8 bits
MOVA,INTR
*DIS II
ENXI
7-29
CPLFO
CPLF1
JFO addr
JF1 addr
JNXI addr
DISXI
*JNFO addr
*JNF1 addr
JXI addr
*EN II
U)
o
(1j
r---------------------------------------------------------------------------------------~
TMP Registers
(Excluding Timing Chain Registers) (Continued)
Z
TMP Registers
Associated Instructions
CPU SECTION (Continued)
MASK
= Internal Interrupt MasK -
PSW
= Program Status Word -
PORT
= 8 bit 1/0 Port
8 bits
*MOV MASK,A
8 bits
Miscellaneous Instructions
MOVA,PSW
MOVPSW,A
ANL PORT,#data
ORL PORT,#data
IN PORT
OUT PORT
CALLaddr
NOP
SELMBO
*SEL MB3
JMPaddr
RET
SEL MB1
SELRBO
JMPP@A
RETR
*SEL MB2
SELRB1
VIDEO MANAGEMENT
Associated Instructions
SCR
VCR
HOME
CURS
= System Control Register -
BEGD
ENDD
SROW
ALO
=
=
=
=
=
=
=
AU
HPEN
VPEN
VINT
8 bits
= Video Control Register - 8 bits
= Home Address Register - 16 bits
= Cursor Address Register - 16 bits
*DEC CURS
*MOVCURS,A
Beginning of Display RAM Register - 16 bits
End of Display RAM Register - 16 bits
Status Row Register - 16 bits
Attribute Latch 0 - 8 bits
Attribute Latch 1 - 8 bits
Horizontal Light Pen Register - 7 bits
Vertical Light Pen Register - 5 bits
= Vertical Interrupt Register - 5 bits
*MOVSCR,A
*MOVVCR,A
*MOVA,HOME
*INCCURS
*MOVA,CURS
*MOVHOME,A
*MOVX A,@CURS
*MOVX @CURS,A
*MOVBEGD,A
*MOVENDD,A
*MOVSROW,A
*MOV ALO,A
*MOVAL1,A
*MOVA,HPEN
*MOVA,VPEN
*MOVVINT,A
UART CONTROL
PSR
BAUD
UCR
UMX
STAT
RCVR
XMTR
TCP
@TCP
*MOVPSR,A
*MOVBAUD,A
*MOVUCR,A
*MOVUMX,A
*MOVA,STAT
*IN RCVR
*OUTXMTR
*MOVTCP,A
*MOV@TCP,A
Pre scale Register (UART) - 8 bits
Baud Rate Select Register - 8 bits
UART Control Register - 8 bits
UART Multiplex Register - 8 bits
Status Latch (UART) - 6 bits
UART Receive Buffer - 8 bits
UART Transmit Buffer - 8 bits
Timing Chain Pointer
= Register Pointed to by TCP
=
=
=
=
=
=
=
=
·New instruction added to 8048 subset.
Symbol Definitions
Symbol
AC
addr
b
BS
data
DBF
EXI
FO,F1
P
Definition
Symbol
Auxiliary Carry Flag
Program Memory Address
Bit Designator (b = 0 - 7)
RAM Bank Switch
Number or Expression (8 bits)
Program Memory Bank Select Bits (2)
External Interrupt Pin
Internal Flags
1/0 Port (8 bits)
PC
SP
TF
#
@
( )
«
~
7-30
»
Definition
Program Counter
Stack Pointer
Timer Flag
Prefix for Immediate Data
Prefix for Indirect Address
Contents of Register
Contents of Memory Location pointed to by
designated register
Replaced by
z
en
Instruction Set
Mnemonic
~
Q
Machine Code
Function
Description
Cycles Bytes
Flags
C AC HACC FO F1
ADDA, Ar
0
ADDA, #data
0 0 0 0 0 0 1 1 (A)
d7 d6 d5 d4 d3 d2 d1 dO
ADDA, @ Ar
0
1
AD DC A, Ar
0
1 1
ADDC A, # data
1
1 0
1 0
1
1
r
r
r (A) ~ (A)
r= 0 - 7
~
(A)
+ (Ar) for
Add contents of
designated register
to the Accumulator
(8-bit operation)
1
1
·· ·
+ data
Add immediate the
specified data to the
Accumulator (8-bit
operation)
2
2
·· ·
+ «Ar)) for
Add indirect the
contents of data
memory pointed to
by Arto the
Accumulator (8-bit
operation)
1
1
·· ·
Add with carry the
contents of the
designated register
to the Accumulator
(8-bit operation)
1
1
·· ·
Add immediate with
carry the specified
data to the
Accumulator (8-bit
operation)
2
2
·· ·
·· ·
0 0
0
r (A) ~ (A)
r= 0- 1
1
r
r (A) ~ (A) + (C)
for r = 0 - 7
r
0 0 0 1 0 0 1 1 (A)
d7 d6 d5 d4 d3 d2 d1 dO
~
(A)
+ (Ar)
+ (C) + data
AD DC A, @Rr
0
1 1
1 0
0 0
r (A) ~(A) + (C) +
«Ar) ) for r = 0 - 1
Add indirect with
carry the contents of
data memory pointed
to by Ar to the
Accumulator (8-bit
operation)
1
1
ANLA, Ar
0
1 0
1
r
r (A) ~ (A) AND (Ar) for
r = 0-7
Logical AND
contents of
designated register
with Accumulator (8bit operation)
1
1
Logical AND
specified Immediate
Data with
Accumulator (8-bit
operation)
2
2
Logical AND indirect
the contents of data
memory pointed to
by Arwith
Accumulator (8-bit
operation)
1
1
Logical AND
immediate specified
data with output port
(8-bit operation)
2
2
2
2
1
r
ANLA, # data
0 1 0 1 0 0 1 1 (A)
d7 d6 d5 d4 d3 d2 d1 dO
ANLA, @ Ar
0
1 0
1 0
0 0
~
(A) AND data
r (A) ~ (A) AND ( (Ar) )
forr = 0 - 1
~
ANL POAT, # data
0 1 1 1 0 0 1 1 (P)
d7 d6 d5 d4 d3 d2 d1 dO
CALL addr
a10 a9 a8 1 0 1 0 o «SP)) ~ (PCO-12)
Call designated
a7 a6 a5 a4 a3 a2 a1 aO ( (SP)) ~ (PSW3-7)
subroutine
(SP) ~ (SP) + 1
(PC8-1 0) ~ addr 8-1 0
(PCO-7) ~ addr 0-7
(PC11-12 ~ DBFO,1
(P) AND data
7-31
U1
Instruction Set (Continued)
Mnemonic
Machine Code
Description
Function
Flags
Cycles Bytes
C AC HACC FO F1
1 (A)
~o
Clear the
Accumulator
1
1
1
1 (C)
~O
Clear carry bit
1
1
0
1 (Fa)
~o
Clear Flag 0
1
1
0
1 (F1)
~a
Clear Flag 1
1
1
1
1
1 (A)
~NOT(A)
Complement the
contents of the
Accumulator (8-bit
operation)
1
1
a
1
1
1 (C)
~
Complement carry
bit
1
1
1
a
1
a
1 (Fa)
~
NOT (Fa)
Complement Flag a
1
1
1
1
0
1
a
1 (F1)
~
NOT (F1)
Complement Flag 1
1
1
a
1
a
1
1
1
Decimal Adjust the
contents of the
Accumulator (8-bit
operation)
1
1
0
a
a
1
1
1 (HACC, A)
A) -1
Decrement by 1 the
contents of HACCI
ACC
1
1
a
a
a
1
0
1
a (CURS)
(CURS) - 1 Decrement by 1 the
contents of the
Cursor Address
Register
1
1
1
1
a
a
1
r
r
r (Rr)
Decrement by 1 the
contents of the
designated register
(8-bit operation)
1
1
DECL Rr
a
0
a
a
1
a
a
r (Rr) ~ (Rr) - 1 for
r= a - 1
Decrement by 1 the
contents of the
designated 16-bit
register pair
1
1
DIS II
a
0
1
1
a
1
a
1
Disable internal
interrupts
1
1
DISXI
a
0
a
1
a
1
a
1
Disable external
interrupts
1
1
Decrement the
specified register
and Jump if not zero
to designated
address within page
(a-bit decrement)
2
2
CLRA
0
0
1
0
0
1
CLRC
1
0
CLRFO
1
0
0
1
0
1
0
0
0
1
CLR F1
1
0
1
0
0
1
CPLA
0
a
1
1
a
CPLC
1
0
1
a
CPLFa
1
a
0
CPLF1
1
a
DAA
0
1
DECA
0
a
DEC CURS
0
DECRr
1
NOT (C)
~
~
~
(HACC,
(Rr) - 1
DJNZ Rr, addr 1 1 1 0 1 r r r (Rr) ~ (Rr) - 1 for
a7 a6 a5 a4 a3 a2 a1 aa r = a - 7
If (Rr) =1= a do (PCO-7)
~addr
If (Rr) = 0 do (PC)
~PC+2
ENII
a
a
1
0
a
1
a
1
Enable internal
interrupts.
1
1
ENXI
a
a
a
a
a
1
a
1
Enable external
interrupt.
1
1
INCA
a
a
a
1
0
1
1
1 (HACC, A)
A) + 1
Increment by 1 the
contents of HACCI A.
1
1
INCCURS
a
a
1
1
1
a
1
0 (CURS)
1
1
~
~
(HACC,
(CURS) + 1 Increment by 1 the
contents of the
Cursor Address
Register.
7-32
*
*
*
*
·
· .
*
·
*
.
..
z
C/)
Instruction Set (Continued)
Mnemonic
.c:a.
o
Machine Code
Function
Description
Cycles Bytes
Flags
C1I
.
.
C AC HACC FO F1
+ 1 for
INCRr
0
0
0
1
1
r
r
r (Rr) ~ (Rr)
r=0-7
INC@ Rr
0
0
0
1
0
0
0
r ((Rr» ~ ((Rr»
r= 0 - 1
INCL Rr
0
0
1
1
1
0
0
r (Rr) ~ (Rr)
r=0-1
IN PORT
1
1
1
0
0
0
0
1 (A)
IN RCVR
1
1
1
0
0
0
0
0 (A)
Increment by 1 the
contents of the
designated register
(8-bit increment)
1
1
Increment in direct
the contents of data
memory pointed to
by Rr (8-bit
increment)
1
1
Increment by 1 the
contents of the
designated 16-bit
register pair
1
1
~(P)
Input data from port
into Accumulator
(8-bit transfer)
2
1
~(RCVR)
Input contents of
UART Receive buffer
into Accumulator (8bit transfer). Also,
clears Receive
Buffer Full interrupt.
1
1
+ 1 for
+ 1 for
JBb addr
b2 b1 bO 1 0 0 1 0 (PCO-7) ~ addr if
a7 a6 a5 a4 a3 a2 a1 aO (b) = 1
(PC) ~ (PC) + 2 if
(b) = 0 for b = 0 - 7
Jump to specified
address within page
if Accumulator bit is
set
2
2
JCaddr
1 1 1 1 0 1 1 0 (PCO-7) ~ addr if
a7 a6 a5 a4 a3 a2 a1 aO C=1
(PC) ~ (PC) + 2 if
C=O
Jump to specified
address within page
if Carry flag is set
2
2
JFO addr
1 0 0 1 0 1 1 0 (PCO-7) ~ addr if
a7 a6 a5 a4 a3 a2 a1 aO FO = 1
(PC) ~ (PC) + 2 if
FO = 0
Jump to specified
address within page
if Flag FO is set
2
2
JF1 addr
0 1 1 1 0 1 1 0 (PCO-7) ~ addr if
a7 a6 a5 a4 a3 a2 a1 aO F1 = 1
(PC) ~ (PC) + 2 if
F1 = 0
Jump to specified
address within page
if Flag F1 is set
2
2
JMP addr
a10 a9 a8 0 0 1 0 0 (PC8-1 0) ~ addr 8-10
a7 a6 a5 a4 a3 a2 a1 aO (PCO-7) ~ addrO-7
(PC11-12) ~ DBFO, 1
Direct Jump to
specified address
within 2k Bank
2
2
((A»
Jump indirect within
page to the address
specified in the
memory location
pointed to by the
Accumulator
2
1
1 1 1 0 0 1 1 0 (PCO-7) ~ addr
a7 a6 a5 a4 a3 a2 a1 aO ifC = 0
(PC) ~ (PC) + 2
ifC = 1
Jump within page to
specified address if
Carry flag is 0
2
2
JMPP @A
JNCaddr
1
0
1
0
0
0
1
1 (PCO-7)
~
7-33
•
II)
o
~
U)
z
Instruction Set (Continued)
Mnemonic
Machine Code
Function
Description
Cycles Bytes
Flags
C AC HACC FO F1
JNFO addr
1 0 0 0 0 1 1 0 (PCO-7) ~ addr if
a7 a6 a5 a4 a3 a2 a1 aO FO = 0
(PC) ~ (PC) + 2 if
FO = 1
Jump within page to
specified address if
FOisO
2
2
JNF1 addr
0 1 1 0 0 1 1 0 (PCO-7) ~ addr if
a7 a6 a5 a4 a3 a2 a1 aO F1 = 0
(PC) ~ (PC) + 2 if
F1 = 1
Jump within page to
specified address if
F1 isO
2
2
JNTF addr
0 0 0 0 0 1 1 0 (PCO-7) ~ addr if
a7 a6 a5 a4 a3 a2 a1 aO TF = 0
(PC) ~ (PC) + 2 if
TF = 1, (TF) ~ 0
Jump within page to
specified address if
Timer flag is reset. If
not, continue and
resetTF
2
2
JNXI addr
1 0 1 0 0 1 1 0 (PCO-7) ~ addr if
a7 a6 a5 a4 a3 a2 a1 aO EXI = LOW
(PC) ~ (PC) + 2 if
EXI = HIGH
Jump within page to
specified address if
External Interrupt pin
is LOW
2
2
JNZ addr
1 1 0 1 0 1 1 0 (PCO-7) ~ addr if
a7 a6 a5 a4 a3 a2 a1 aO A =1= 0
(PC) ~ (PC) + 2 if
A=O
Jump within page to
specified address if
Accumulator is not 0
2
2
JTF addr
0 0 0 1 0 1 1 0 (PCO-7) ~ addr if
a7 a6 a5 a4 a3 a2 a1 aO TF = 1, (TF) ~ 0
(PC) ~ (PC) + 2 if
TF = 0
Jump within page to
specified address if
Timer flag is set. If
jump taken Timer
flag reset
2
2
JXI addr
1 0 1 1 0 1 1 0 (PCO-7) ~ addr if
a7 a6 a5 a4 a3 a2 a1 aO EXI = HIGH
(PC) ~ (PC) + 2 if
EXI = LOW
Jump within page to
specified address if
External Interrupt pin
isHIGH
2
2
JZ addr
1 1 0 0 0 1 1 0 (PCO-7) ~ addr if
a7 a6 a5 a4 a3 a2 a1 aO A=O
(PC) ~ (PC) + 2 if
A =1= 0
Jump within page to
specified address if
Accumulator is 0
2
2
MOVA,CURS
1
0
0
1
1
0
1
1 (HACCI A)
1
1
MOVA, HACC
1
1
1
0
0
0
1
0 (A)
Copy contents of the
High Accumulator
into the Low
Accumulator (B-bit
transfer)
1
1
MOVA,HOME 1
0
0
1
1
0
1
0 (HACCI A)
(HOME) Copy the contents of
the Home Address
register into the
HACCI A (16-bit
transfer)
1
1
MOVA,HPEN
0
1
1
1
1
1
1 (AO-6) ~ (HPEN)
(A7) ~O
1
1
0
~
(CURS) Copy the contents of
the Cursor Address
Register into the
HACCI A (16-bit
transfer)
~(HACC)
~
7-34
Copy the contents of
the Horizontal Light
Pen Register into the
Accumulator (7 -bit
transfer, A7 cleared)
*
*
z
en
~
o
Instruction Set (Continued)
Mnemonic
Machine Code
Function
Description
Cycles Bytes
Flags
U1
C AC HACC Fa F1
1 0
0 (A) +- (INTR)
Copy the contents of
the Interrupt Register
into the Accumulator
(a-bit transfer)
1
1
0 0
1
1
1 (A) +- (PSW)
Copy contents of the
Program Status word
into the Accumulator
(a-bit transfer)
1
1
1
1
1
r
r
r (A) +-(Rr)
forr = a - 7
Copy the contents of
the designated
Register into the
Accumulator (a-bit
transfer)
0
1
1
1 0
o (AO-5)
Copy the contents of
the UART Status Latch
into the Accumulator
(6-bit transfer, A6 and
A7 set)
1
1
1 0
a
a
0
1
o (A)
Copy the contents of
the Timer into the
Accumulator (a-bit
transfer)
1
1
1
1
1
1
1 0 (AO-4) +- (VPEN)
(A5-7) +-0
Copy contents of the
Vertical Light Pen
Register into the
Accumulator (5-bit
transfer, A5-A7
cleared)
1
1
1
1 0
Copy indirect the
contents of data
memory pointed to by
Rr into the
Accumulator (a-bit
transfer)
1
1
Load immediate the
specified data into the
Accumulator (a-bit
load)
2
2
+- (A)
Copy the contents of
the Accumulator into
Attribute Latch 0 (a-bit
transfer)
1
1
1 (AL 1) +- (A)
Copy the contents of
the Accumulator into
Attribute Latch 1 (a-bit
transfer)
1
1
o (BAUD)
Copy the contents of
the Accumulator into
the UART Baud Rate
Select Register (a-bit
transfer)
1
1
Copy the contents of
HACCI A into the
Beginning of Display
RAM Register (16-bit
transfer)
1
1
MOVA,INTR
1 0
MOVA, PSW
1
1 a
MOVA, Rr
1
1
MOVA,STAT
1 0
MOVA, T
0
MOVA, VPEN
0 0
MOVA, @Rr
1
1
a
0
1
0 0
+- (STAT)
(A6-7) +- 11
+- (T)
r (A) +- ( (Rr) ) for
r = 0 - 1
MOVA, # data
0 0 1 0 0 0 1 1 (A) +- data
d7 d6 d5 d4 d3 d2 d1 dO
MOVALO,A
0
0
1
1
1
1
MOVAL1,A
0
0
1
1
1
1 0
MOV BAUD, A
a
0
0 0 0 0
MOVBEGD,A
a
0
0 0
1
0
1
1 0
o (ALO)
+- (A)
1 (BEGD) +- (HACCI A)
7-35
•
I
Instruction Set (Continued)
Mnemonic
Machine Code
Function
Description
Flags
Cycles Bytes
C AC HACC FOF1
1
1 (CURS) ~ (HACCI A)
Copy the contents of
HACCIA into the
Cursor Address
Register (16-bit
transfer)
1
1
1
0
o (ENDD)
~
(HACCI A)
Copy the contents of
HACCI A into the End
of Display RAM
Register (16-bit
transfer)
1
1
0 0 0
1
o (HACC)
~
(A)
Copy the contents of
the Low Accumulator
into the High
Accumulator (8-bit
transfer)
1
1
0 0 0 1 0
1
o (HOME)
~
(HACCI A)
Copy the contents of
HACCI A into the
Home Address
Register (16-bit
transfer)
1
1
1 0
0 0 0 0
1
o (MASK)
~
(A)
Copy the contents of
the Accumulator into
the Interrupt Mask
Register (8-bit transfer)
1
1
MOVPSR,A
0
0
1
0 0
1
o (PSR)
Copy the contents of
the Accumulator into
the UART Prescale
Register (8-bit transfer)
1
1
MOVPSW,A
1
1 0
MOVRr,A
1
MOVSCR,A
0
MOVSROW,A
0 0 0 0 1 1 1
o (SROW)
MOVT,A
0
1
1
o (T)
MOVTCP,A
1
0 0 0 0
1
1 (TCP)
MOVCURS, A
1 0
0 0 1 0
MOVENDD,A
0 0 0 0
MOVHACC,A
1
1 0
MOVHOME,A
1
MOVMASK,A
0
1
~(A)
1 1
1 (PSW) ~(A)
Copy contents of the
Accumulator into the
Program Status Word
(8-bit transfer)
1
1
0 1 0 1
r
r (Rr) ~ (A) for
r= 0 - 7
Copy contents of the
Accumulator into the
designated register (8bit transfer)
1
1
1 0
1 0
Copy contents of the
Accumulator into the
System Control
Register (8-bit transfer)
1
1
Copy the contents of
HACCI A into the
Status Row Register
(16-bit transfer)
1
1
Copy the contents of
the Accumulator into
the Timer (8-bit
transfer)
1
1
Copy the contents of
the Accumulator into
the Timing Chain
Pointer
1
1
1
1 0
1 0
0 0 0
1
r
1 (SCR)
~(A)
~
(HACCI A)
~(A)
~
(A)
7-36
.
..
z
en
oC:Ia
Instruction Set (Continued)
Mnemonic
Machine Code
Description
Function
Cycles Bytes
Flags
C AC HACC FO F1
MOVUCR,A
0
0
0
0
0
0
0
1 (UCR)
~(A)
Copy the contents of
the Accumulator into
the UART Control
Register (8-bit transfer)
1
1
MOVVCR,A
0
1 0
0
0
1 0
1 (VCR)
~(A)
Copy the contents of
the Accumulator into
the Video Control
Register (8-bit transfer)
1
1
MOVVINT,A
1 0
1 0
0
0
o (VIND
~(A)
Copy the contents of
the Accumulator into
the Vertical Interrupt
Register
1
1
Load immediate the
specified data into the
designated register (8bit load)
2
2
Copy indirect the
contents of the
Accumulator into the
data memory location
pointed to by Rr (8-bit
transfer)
1
1
Load indirect the
specified immediate
data into the data
memory location
pointed to by Rr (8-bit
load)
2
2
Copy indirect the
contents of the
Accumulator into the
Timing Chain Register
pointed to by TCP.
Contents of TCP
incremented by 1
1
1
Copy the contents of
the Accumulator into
the UART Multiplex
Register (8-bit transfer)
1
1
MOV Rr, # data
MOV@Rr,A
MOV @ Rr, # data
MOV@TCP,A
1
1 0 1 1 1 r r r (Rr) ~ data for
d7 d6 d5 d4 d3 d2 d1 dO r = 0-7
1 0
1 0
0
0
0
r ( (Rr» ~ (A) for
r=0- 1
1 0 1 1 0 0 0 r «Rr» ~ data for
d7 d6 d5 d4 d3 d2 d1 dO r = 0 - 1
1 0
1
1 0
MOVUMX,A
0
0
1
1 0
MOVLA, RO
1 0
0
MOVLA, R1
1 0
MOVLRO,A
MOVL R1, A
1
1
1 ( (TCP» ~ (A)
(TCP) ~ (TCP)
+
1
~(A)
0
1
1 (UMX)
1
1 0
0
o (HACCIA)
~
(RA, RO)
Copy the contents of
RA, RO into HACCIA
(16-bit transfer)
1
1
.
0
1
1 0
0
1 (HACC/A)
~
(RB, R1)
Copy the contents of
RB, R1 into HACC/A
(16-bit transfer)
1
1
*
1 0
0
0
1 0
0
o (RA, RO)
~
(HACCI A)
Copy the contents of
HACCIA into RA, RO
(16-bit transfer)
1
1
1 0
0
0
1 0
0
1 (RB, R1)
~
(HACC/A)
Copy the contents of
HACCI A into RB, R1
(16-bit transfer)
1
1
7-37
o
en
Lt)
o
~
tJ)
z
Instruction Set (Continued)
Mnemonic
Machine Code
Function
Description
Cycles Bytes
Flags
C AC HACC FO F1
MOVPA,@A
1 0
1
1 0
0
1
Replace low 8 bits of
1 (PCO-7) ~ (A)
PC with A. Load
(A) ~«PC»
(pCO-7) ~ (old PCO-7) indirect within page the
contents of the
+1
memory location
pointed to by new PC
into Accumulator.
Restore PC with old
value plus 1. Operates
in all memory banks.
2
1
MOVP3A,@A
1
1
1
1 0
0
1
1 (PCO-7) ~ (A)
(PC8-10) ~ 011
(A) ~ «PC»
(PC) ~ (old PC) + 1
2
1
MOVX A,
1
0
0
1
1
1
0
1 (HACCI A)
~
( (CURS) ) Copy indirect the
Min. 2
contents of display
memory as pointed to
by CURS into HACCI A
(16-bit transfer)
1
·
MOVXA,@RO
1 0
0
1 0
0
0
o (HACCI A)
~
( (RA, RO) ) Copy indirect the
Min.2
contents of display
memory as pointed to
by RA, RO into HACCI
A (16-bit transfer)
1
·
MOVXA,@R1
1
0
0
1 0
0
0
Min. 2
1 (HACC/A) ~ «RB, R1» Copy indirect the
contents of display
memory as pointed to
by RB, R1 into HACCI
A (16-bit transfer)
1
·
MOVX @ CURS, A
1
0
0
0
1
1
0
1 ( (CURS»
MOVX@RO,A
1
0
0
0
0
0
0
o «RA, RO»
@
CURS
~
Replace low 8 bits of
PC with A. Next 3 bits
replaced with 011.
Load indirect within
page 3 the contents of
the memory location
pointed to by new PC
into the Accumulator.
Restore PC with old
value plus 1. Operates
in all memory banks.
(HACCI A) Copy indirect the
contents of HACCI A
into the display
memory location as
pointed to by CURS
(16-bit transfer)
~
(HACCI A) Copy indirect the
contents of HACCI A
into the display
memory location as
pointed to by RA, RO
(16-bit transfer)
7-38
Min. 2
1
Min.2
1
z
en
Instruction Set (Continued)
Mnemonic
~
Q
Machine Code
Function
Description
Flags
Cycles Bytes
U1
C AC HACC FO F1
MOVX@R1,A
1 0
0 0 0 0 0
1 «RB, R1»
~
(HACC/A) Copy indirect the
contents of HACC/A
into the display
memory location
pointed to by RB, R1
(16-bit transfer)
Min.2
1
NOP
0 0 0 0 0 0 0 0
No Operation
1
1
ORLA, Rr
0
1 0
0
r
r
r (A) ~ (A) OR (Rr) for
r=O-7
Logical OR contents of
designated register
with Accumulator (a-bit
transfer)
1
1
ORLA, @ Rr
0
1 0
0 0 0
0
r (A) ~ (A) OR ( (Rr) )
for r = 0 - 1
Logical OR indirect the
contents of the data
memory location
pointed to by Rr with
Accumulator (a-bit
operation)
1
1
ORLA, # data
0 1 0 0 0 0 1 1 (A)
d7 d6 d5 d4 d3 d2 d1 dO
~
(A) OR data
Logical OR the
specified immediate
data with the
Accumulator (a-bit
operation)
2
2
ORL PORT, # data 0 1 1 0 0 0 1 1 (P)
d7 d6 d5 d4 d3 d2 d1 dO
~
(P) OR data
Logical OR immediate
specified data with
output port
2
2
Output the contents of
the Accumulator to the
I/O Port (8-bit transfer)
2
1
Copy the contents of
the Accumulator into
the UART Transmit
Buffer (a-bit transfer).
Also clears Transmit
Buffer empty interrupt
1
1
1
~(A)
OUT PORT
1
1
0
0 0 0 0
1 (P)
OUTXMTR
1
1 0
0 0 0 0
o (XMTR)
RET
1
0 0
0 0 0
1
1 (SP) ~ (SP) - 1
(PCO-12) ~ «SP»
Return from subroutine
without restoring
Program Status Word
bits 5-7
2
1
RETR
1
0 0
1 0
0
1
1 (SP) ~ (SP) - 1
(PCO-12) ~ «SP»
(PSW 3-7) ~ «SP»
Return from
Subroutine restoring
Program Status Word
(use for all returns from
interrupts)
2
1
RLA
1
1
1
0 0
1
1
1 (An + 1) ~ (An)
forn = 0 - 6
(AO) ~(A7)
Rotate Accumulator
left by 1 bit without
carry
1
1
RLCA
1
1
1
1 0
1
1
1 (An + 1)
Rotate Accumulator
left by 1 bit through
carry
1
1
~
~
(A)
(An) for
n=O-6
(AO) ~ (C)
(C) ~(A7)
7-39
..
.
III
Instruction Set (Continued)
Mnemonic
Machine Code
Function
Description
Flags
Cycles Bytes
C AC HACC FO F1
1
1
1 (An) ~ An + 1
forn = 0 - 6
Rotate Accumulator
right by 1 bit without
carry
1
1
0
1
1
1 (An) ~ An+ 1
forn = 0-6
(A7) ~(C)
(C) ~(AO)
Rotate Accumulator
right by 1 bit through
carry
1
1
0
1 0
1 (DBF)
~OO
Select Bank 0
(0-2047) of Program
Memory
1
1
1 0
1 0
1 (DBF)
~
01
Select Bank 1
(2048-4095) of
Program Memory
1
1
0
1 0
1 (DBF)
~
10
Select Bank 2
(4096-6143) of
Program Memory
1
1
1 0
1 0
1 (DBF)
~
11
Select Bank 3
(6144-8191) of
Program Memory
1
1
0
0
Select Data RAM Bank
(0-7) or 1 (24-31)
1
1
RRA
0
1
1
RRCA
0
1
1 0
SELMBO
1
1 0
0
SELMB1
1
1 0
SELMB2
1
1
1 0
SELMB3
1
1
1
SELRBn
1
1 n
1 0
STOPT
0
1
1 0
STRTT
0
1
1
SWAP A
0
1 0
XCHA, Rr
0
XCHA,@Rr
0
1
1 (BS)
for n
~n
=0
- 1
0
1 0
1
Stop Timer
1
1
1
Start Timer
1
1
SWAP 4 bit nibbles in
Accumulator
1
1
1 0
1 0
0
0
1
1
1 (A4-A7)
0
1 0
1
r
r
r (A) ~ (Rr)
for r = 0 - 7
Exchange the
Accumulator and
contents of designated
register (8-bit transfer)
1
1
0
0
1 0
0
0
0
r (A) ~ «Rr»
for r = 0 - 1
Exchange indirect the
contents of the
Accumulator and the
data memory location
pOinted to by Rr (8-bit
transfer)
1
1
XCHDA, @ Rr
0
0
1
1 0
0
0
r (AO-3) ~ «Rr»0-3 Exchange indirect the
low 4 bits of the
for r = 0 - 1
Accumulator and the
data memory location
pOinted to by Rr (4-bit
transfer)
1
1
XRLA, Rr
1
1 0
1
1
r
r
r (A) ~ (A) XOR (Rr)
for r = 0 - 7
Logical XOR contents
of designated register
with Accumulator (8-bit
transfer)
1
1
XRLA, @ Rr
1
1 0
1 0
0
0
r (A) ~ (A) XOR ( (Rr) )
forr = 0 - 1
Logical XOR indirect
the contents of the
data memory location
pointed to by Rr with
the Accumulator
1
1
Logical XOR the
immediate specified
data with the
Accumulator
2
2
XRLA, # data
1 1 0 1 0 0 1 1 (A)
d7 d6 d5 d4 d3 d2 d1 dO
~
~
(AO-A3)
(A) XOR data
7-40
.
z
(J)
TMP Opcode Chart
o
o
2
2
INC
@RO
INC
@R1
XCH
A,
@RO
XCH
@R1
A
ANL
@R1
ADD
6 A,
M
@RO
ADD
A,
@R1
A,
ADDC ADDC
A,
A,
@RO @R1
JB1
MOV
A,T
MOVX MOVX
A,
A,
@RO @R1
MOV
5
6
7
8
9
INC
R1
INC
R2
INC
R3
INC
R4
INC
R5
INC
R6
INC
R7
CLRA
XCH
A,
RO
XCH
A,
R1
XCH
A,
R2
XCH
A,
R3
XCH
A,
R4
XCH
A,
R5
XCH
A,
R6
XCH
A,
R7
CPLA
INCL INCL INC
R1
RO
CURS
MOV
ALO,
A
MOV
AL1,
A
MOV MOV
A,
A,
VPEN HFEN
SWAP
A
ORL
A,
RO
ORL
A,
R1
ORL
A,
R2
ORL
A,
R3
ORL
A,
R4
ORL
A,
R5
ORL
A,
R6
ORL
A,
R7
DAA
MOV JMP
(page
A,
1)
# data
EN
II
MOV CALL
DIS
UMX, (page
II
1)
A
ORL
A,
#data
JMP MOV
(page VCR,
2)
A
JB2
ANL
A,
RO
ANL
A,
R1
ANL
A,
R2
ANL
A,
R3
ANL
A,
R4
ANL
A,
R5
ANL
A,
R6
ANI..
A,
R7
MOV
T,A
ORL JMP
ADD
STOP
PORT, (page
JNF1 RRCA A,
T
3)
#data
RO
ADD
A,
R1
ADD
A,
R2
ADD
A,
R3
ADD
A,
R4
ADD
A,
R5
ADD
A,
R6
ADD
A,
R7
JB3
ANL CALL
STRT
PORT, (page
JF1
T
3)
# data
JB4
ANL
A,
RRA
ADDC ADDC ADDC ADDC ADDC
A,
A,
A,
A,
A,
R4
RO
R1
R2
R3
JB5
#data # data
MOV
OUT OUT
HACC,
XMTR PORT
A
JB6
RET
MOV
F A,
@RO
MOV
A,
@R1
JB7
A,
R5
ADDC ADDC
A,
A,
R7
R6
MOV MOVL MOVL MOV MOV MOV MOVX
CLR
@CURS,
(page
R1, HOME, CURS, A,
JNFO TCP,
RO,
FO
4)
A
A
INTR
A
A
A
A
CALL
CPL
RETR (page
FO
4)
SEL
RBO
XRL
A,
#data
MOV
IN
IN
E
A,
RCVR PORT
HACC
AD DC
JMP
JFO CLRC
MOVL MOVL MOV MOV MOV MOVX
A,
A,
A,
A,
A,
A,
R2
R1 HOME CURS STAT @CURS
MOV
R4,
A
MOV
R5,
A
MOV
R6,
A
MOV
R7,
A
MOV MOV MOV MOV MOV MOV
R1,
R3,
R4,
JXI @TCP, RO,
R2,
# data # data # data # data #data
A
MOV
R5,
MOV
R6,
MOV
R7,
#data
#data # data
MOVP CALL
CPL
A,
(page
F1
@A
5)
@RO
F
INC
RO
MOV
@R1,
XRL
A,
@R1
E
JTF INCA
0)
MOV
B @RO,
A,
D
AD DC CALL
DIS
A,
(page
XI
MOV MOV
JMP
JMPP
CLR
R1,
@A (page F1 JNXI CPLC RO,
5)
A
A
XRL
c
MOV
MOV
MOV
ENDD, BECD, SROW,
A
A
A
DECL DECL DEC
RO
R1
CURS
MOV MOV
@R1, VINT,
A
A
D
B
JNTF DECA
A @RO,
A
c
A
CALL MOV
(page SCR,
# data
2)
A
MOVX MOVX MOV
8 @RO, @R1, MASK,
A
A
A
9
U1
EN
XI
# data
MOV
PSR,
ANL
5 A,
@RO
7
JBO
A,
ORL
A,
@R1
S
4
NOP
ORL
A,
@RO
N
3
MOV MOV ADD JMP
UCR, BAUD,
A,
(page
0)
A
#data
A
XCHD XCHD
3 A,
A,
@RO @R1
4
~
o
LSN
SEL
RB1
JMP
(page
6)
CALL
(page
6)
JMP
(page
7)
SEL
MBO
SEL
MB1
JZ
MOV
JNZ PSW,
A
SEL
JNC
MB2
MOVP3 CALL
SEL
(page
A,
MB3
@A
7)
MOV
A,
PSW
JC
MOV
R2,
A
MOV
R3,
A
DEC
RO
DEC
R1
DEC
R2
DEC
R3
DEC
R4
DEC
R5
DEC
R6
DEC
R7
XRL
XRL
A,
R1
XRL
A,
R2
XRL
A,
R3
XRL
A,
R4
XRL
A,
R5
XRL
A,
R6
XRL
A,
R7
A,
RO
RLA
DJNZ DJNZ DJNZ DJNZ DJNZ
R4
RO
R1
R2
R3
DJNZ
R5
DJNZ DJNZ
R6
R7
RLCA
MOV MOV
A,
A,
RO
R1
MOV
A,
R4
MOV
A,
R5
MOV
A,
R6
7-41
MOV
A,
R2
MOV
A,
R3
MOV
A,
R7
~
o
~
tJ)
z
r---------------------------------------------------------------------------~
Ordering Information
ORDER PART NUMBERS
ROM less
NS405-A12N
NS405-B12N
NS405-C12N
7-42
NS405-B18N
~---------------------------------------------------------------,~
The intricate timing relationships inherent in video generation require that a designer have a firm grasp of the fundamentals of NS405 operation in order to achieve his design
objectives. Towards this end the key facets of NS405 operation will be examined and examples given.
The NS405 is a complete video controller that reads in video data, processes it and outputs it to a CRT. Given this,
one may derive all essential operating parameters from the
following two statements:
1. You must be able to read in video data faster than you
output it.
2. Video data accesses are based on the CPU cycle which
in turn is based on the crystal or dot clock.
Application of these two statements immediately leads to a
limitation on the character cell width as follows:
if f = crystal frequency or dot clock
then (f +1) +15 or (f +1.5) +15 = CPU Instruction Execution Clock Frequency
Since there are three video data accesses each CPU Instruction Execution cycle, there are 3 • (f + 1) + 15 or 3 •
(f + 1.5) + 15 video data accesses per second.
if w=dot width of character cell then f+w=number of
character cells being displayed per second.
Statement 1 says that video data accesses/sec :<: display
characters/ sec
for CPU Clock + 1
3· (f+1)+15:<:f+w
for CPU Clock + 1.5
3· (f+1.5)+15:<:f+w
f+5:<:f+w
(3· f)+22.5:<:f+w
Ys:<:1/w
w:<:5
3/22.5:<: 1/w
To display one line requires (9X80)/18 MHz=40 us.
In one line time there are 2.4 MHzX40 us=96 video
memory accesses. Of the 96, 80 are required for the
characters displayed in the line leaving 16 available for
the CPU. This is an average of one every six video
memory accesses or once every two CPU instruction
cycles. This would be fine since all CPU video memory
instructions require two instruction cycles to execute
anyway. However, in addition to the DMA controller the
video circuits also employ a four level FIFO to insure a
smooth data flow. The FIFO is normally kept full at four
in which case it stops accessing video data and allows
the CPU to have all the accesses. However, the FIFO
can drop down quite far before starting to fill up again by
taking all of the video memory accesses. The net effect
is that instead of being evenly distributed, the accesses
available to the CPU are clumped together with long
gaps between clumps. Taking the worst case condition
of the FIFO being completely empty and having to fill to
four by taking the accesses which the CPU could have
gotten, the longest gap is (4X6)+5=29 accesses:::: 10
CPU instruction cycles. Generally speaking this tends to
happen towards the middle of a line since the FIFO is
filled prior to the start of a line and tries to end a line
empty. In fact, accesses for video are performed up to
the second to the last display character. The FIFO prefetch for the next line is performed shortly after horizontal blanking starts.
II. If the dot clock is now 12 MHz with a display line of 80
character cells 7 dots across the CPU clock divide can be
1.
w:<:~5
So depending on the CPU clock divide factor (+1 or +1.5)
the character cell width must be a minimum as shown.
Cell width also impacts CPU throughput since both the CPU
and Video controller vie for video memory access through
the DMA controller. The rules of access are simple and
straightforward. The Video Controller gets as many of the
accesses as it needs with the CPU getting any left over. The
maximum access rate as already shown is f+5 or f+7.5
depending on the CPU clock divide. If the CPU attempts a
video memory access when things are very busy it will be
put into a wait state and remain frozen until things clear up.
Of course, no display characters are necessary when the
display is blanked, so during the horizontal and vertical retrace periods the CPU has unlimited access to video memory.
Normally, the CPU doesn't have to wait until horizontal retrace to get into video memory, but exactly how often it can
get in during a display line requires analysis of the worst
case video requirements.
Since the results can vary dramatically depending on the
parameters chosen, two typical cases will be presented.
I.
~*
National Semiconductor
Application Brief 14
James Murashige
Throughput Considerations
In NS405 System Planning
The video memory access rate is 12 MHz+5=2.4 MHz.
To do one line requires (7X80)/12 MHz=46.7 us. In one
line time there are 2.4 MHzX46.7 us= 112 video memory
accesses. Of the 112, 32 are now available to the CPU.
This averages out to one every 3.5. Figuring the FIFO in,
the worst case wait for the CPU becomes
(4 X 3.5) + 2.5 = 16.5 accesses:::: 6 CPU instruction cycles. A significant improvement over the first example.
In general, to maximize CPU access to video memory one
must maximize the average number of "free" accesses during the display time. The number of free accesses as a fraction of the total number available is:
(w-5d)/w
Where w=character cell dot width
d = CPU divide factor of 1 or 1.5
As can be seen, throughput performance depends entirely
on the cell width and CPU clock divide. To maximize performance one would try to choose a large wand a d of 1.
Applying the delay imposed by the four level FIFO, the maximum CPU delay in accessing video memory becomes =
With a dot clock of 18 MHz the display line consists of
80 character cells, 9 dots across. Since the CPU clock
divide must be 1.5 the video memory access rate is 18
MHz+7.5=2.4 MHz.
7-43
(4w+5d)/(w-5d)
Memory cycles
•
(D
r---------------------------------------------------------------------------------~
~
~ NS405-Series TMP External
National Semiconductor
Application Brief 16
James Murashige
Interrupt Processing
The TMP External Interrupt (lNTR) is a level sampled interrupt input. Specifically this means that the input is sampled
once each CPU cycle with interrupts being generated as
long as the sampled input is a logic low. INTR shares pin 37
with RE10 and is sampled on each ALE rising edge as
shown in the data sheet. If a logic low level is detected,
interrupt service will commence if interrupts had been previously enabled with an EN XI instruction. Service consists of
finishing up the currently executing instruction, pushing the
PC and other pertinent information onto the stack, disabling
all interrupts while in service and finally performing a JUMP
to location 003. Upon completion of service a RETR would
be executed to pop the stack and return to where we left off
in the main program.
The exact timing involved may be observed through the example program of Figure 1 and its instruction execution sequence in Figure 2. In Figure 2 the numbers shown on the
falling ALE edges are the program addresses put out by the
TMP. As written the program will loop endlessly unless diverted by an external interrupt such as point A in Figure 2.
Since it just missed the previous rising ALE edge it will not
be until point 8 that the logic low INTR is read in. However,
by then the CPU will have started execution of the first byte
of the JMP 11 instruction. Since instructions are always finished once started, it will not be until point C that we begin
interrupt service. At this point the next address would have
been back at 11 but we now want to service the interrupt
and push the stack. Stack pushing or popping takes 2 CPU
ADDRESS
000
001
002
003
004
OPCODE
04
10
cycles so the two address 11's shown following point Care
dummies. Finally, we start interrupt service at point D by
outputting address 003 and reading in the IN PORT instruction. Since the IN PORT instruction is only 1 byte long but
takes 2 CPU cycles to execute, the address "4" at point E is
a dummy and isn't really needed until point F when we read
in the RETR instruction. Like IN PORT, RETR is a 1 byte
instruction that takes 2 CPU cycles to execute. Therefore,
the address "5" at point G is redundant. Upon returning
from subroutine we immediately push the stack again (point
H) since the interrupt is still there. Note that we immediately
push the stack and do not execute the JMP at 11. Once
more we go through the interrupt service routine but this
time the interrupt ends at point I. Since it missed the preceding rising ALE edge where it was still seen as a logic low, we
will immediately execute another interrupt service routine as
shown. Finally, at point J as we prepare to return from service, INTR will be seen as a logic high and from point K
onward execution will proceed normally.
When enabling and disabling interrupts, the rules for when
you will and will not service them are predicated on the
latest sampled interrupt level and last instruction executed.
This is illustrated by the example program of Figure 3 and
instruction execution sequences of Figure 4. As shown in
Figure 4a, the interrupt goes low at point A and will be sampled at the rising ALE of point 8. However, since the current
executing instruction (DIS XI at location 13) must be completed before starting interrupt service, the interrupt will be
IINEMONIC
JIIP010
;RESET VECTOR
El
93
IN FORT
RETR
;EXTERNAL INTERRUPT VECTOR
03
04
11
ENXI
JIIPOOl
;IIAIN PROGRAII
oo~
006
007
006
009
OOA
OOB
OOC
000
OOE
oor
010
011
012
013
014
Ol~
FIGURE 1.INTR Service Timing Example Program
TL/DD/6972-1
FIGURE 2. INTR Service Timing
7-44
.
l>
locked out. Execution continues unperturbed until the interrupt is re-enabled with an EN XI from location 11, point F.
Although the interrupt went logic high at point E it was still
sampled as a logic low at pOint D.
Returning to the missed interrupt at pOint A, if the interrupt
low had come in time to be sampled at point G, the instruction at 12 would have been the last one executed before
interrupt service started as demonstrated in Figure 4b.
Therefore, after executing the EN XI at location 11, interrupt
service will commence as shown. If the interrupt had gone
logic high before point 0 it would have been sampled high
and no interrupt service would have been performed.
Although describing the external interrupt, all of the service
sequences presented may be directly applied to TMP internal interrupts.
ADDRESS
000
DOl
002
003
004
OPCODI
04
10
IINEIIONIC
JIIPOIO
OJ
-.
en
;RESxr VECTOR
00
93
NOP
RETR
;!XTERRAL INTERRUPT VECTOR
00
NOP
ENXI
Nap
DISXI
JIIPOIO
;IL\INPROGlWI
oo~
006
007
008
009
aDA
OOB
DOC
000
001
oor
010
011
012
013
014
O~
00
I~
04
10
Ol~
016
FIGURE 3. INTR Enable/Disable Timing Example Program
GA
8 C
INTR
AlE
J1JLJl..JUL
5
12
13
14
15
TLlDD/6972-2
FIGURE 4a. INTR Enable/Disable Timing
IHTR
TL/DD/6972-3
FIGURE4b
•
7-45
.
~
r-----------------------------------------------------------------------------------------~
I.l)
("t)
National Semiconductor
Application Note 354
James Murashige
TMP Rowand Attribute
< Table Lookup Operation
z
This note describes in detail the operation of the TMP Attribute Demo Program - TAD. Although a short program, it
nicely demonstrates row table lookup operation in the TMP
while at the same time putting out a visual display of the
various video attributes available in the chip. While this display management approach is much more involved than
normal sequential lookup mode, it is necessary when attemping to do fast screen updates or line editing with the
TMP.
The hardware environment for which the program was written is the TMP Demo board. Appropriate references to and
descriptions of the hardware will be made as necessary. For
those who have not seen it, the net function of the program
is to put up and manage a single frame of video data. In the
top half of the display the same message is repeated 5
times but each time with a different set of attributes. In the
lower half of the display are 4 rows representing the 128
possible block graphics patterns. All of the attribute effects
displayed are achieved by updating the internal ALO attribute latch at the end of each display row. At the same time
a message table lookup is performed in order to obtain the
appropriate character string that will work with the new attribute set selected.
The flowchart for the program is shown in Figure 1. As you
can see, the program essentially consists of initialization
and waiting for and servicing video interrupts to manage the
screen display. Initialization starts at BEGIN with the Vertical
Interrupt Register and Timing Chain being loaded first. The
Vertical interrupt is used for end of frame synchronization
and is set to activate after the 27th row. The Timing Chain is
loaded as follows:
TCP 0 Horizontal Length
104
1 Characters/Row
80
2 Horizontal Sync Begin
84
100
3 Horizontal Sync End
4 Character Height
10
Extra Scans/Frame
2
27
5 Vertical Length
6 Vertical Blank
25
7,3
7 Vertical Sync Begin/End
31
8 Status Row Begin
9 Blink Rate/D.C.
F4H
10 Graphics Column Register = 30H
11 Graphics Row Register
36H
12 Underline Size Register
89H
13 Cursor Size Register
09H
Given these values, one can ascertain that the display is 80
columns across and 25 rows tall. The character cell height
is 10 scan lines and no status line will be displayed. The
character underline is the bottom most scan line in a cell
and the cursor occupies an entire cell. The partitioning of
the block graphics cells is as follows:
0011100
0011100
0011100
2233344
2233344
5566655
5566655
5566655
5566655
TAD Flowchart
TL/C/5729-1
FIGURE 1
7-46
.
l>
Following timing chain initialization various system registers
are set to configure the chip to operate in its hardware environment. The video memory is a 2kX8 NMC2116 located
between addresses 000-7FF. The crystal dot clock is 12
Mhz allowing us to use divide by 1 to generate the CPU
clock. Accordingly the SCR is set to 24H (SB8-15 address
output only, cell width = 7, divide by 1 for CPU clock, row
table lookup operation). RAM Bank 0 is selected and
HOME, BEGD, RAiRO are cleared. ENDD and CURS are
set to 7FFFH and AL 1 is set to FFH (no attributes selected).
Video display memory (80 X 25 char) is then cleared out by
storing spaces at all of the memory locations. Along with the
spaces, attribute latch 1 is specified to be used. Video is
then turned on by setting the VCR to 21 H (normal alphanumeric display, internal attribute latch operation, normal
video).
executed. A simple example will illustrate the pipe lining involved. In Figure 2, at the end of Row 1 (Point A) an EaR
interrupt is generated. In preparation for this event HOME
should have been loaded with the starting address of ROW
2 since the interrupt is generated when CRSR reloads from
HOME. In service of the EOR, the program would load
HOME with the starting address of ROW 3 in preparation for
the EOR interrupt at Point B. However, notice that we have
an entire row time from A to B to do, the HOME reload.
Finally note that EOR's are generated at the end of all rows
except those blanked during vertical blanking. Vertical Interrupt operates with the same timing as End of Row except
that it is specified to occur at the end of a particular row
designated by the Vertical Interrupt Register. The row that it
is specified to occur on must be < = Vertical Length Register (timing chain rows are counted starting from 0). Otherwise, it will never occur since the row counter will never
count up that far. Usually Vertical Interrupt is specified to
occur on a row blanked during vertical blanking so that it
may be used as a frame sync signal.
Returning to TAD, Figure 3 shows the interrupt positioning
for all of the rows on the screen including the blanked ones.
There are 25 displayed rows and 2 blanked ones in a frame
for a total of 27. In addition, there are 2 extra scan lines
which may be ignored as far as interrupt operation is concerned. Vertical Interrupt is set to occur at the end of the
last row in the frame as shown. Row pointer operation for
rows 2 to 24 is pipe lined as described in Figure 2. At the end
of ROW 24 (point E) the CRSR will be loading the pointer to
ROW 25 and the interrupt service will load HOME with the
pointer to ROW 1. At the end of ROW 25 (point F) the
CRSR will load the pointer to ROW 1 and save it for the next
frame. Since no EaR's are generated during vertical blanking, CRSR will remain static until ROW 1. At this point, it
doesn't matter what the interrupt service loads into HOME
and ALO since the Vertical Interrupt at ROW 27 will reset the
row counter and perform a new lookup for HOME and ALO.
A Vertical Interrupt will not do a CRSR load, thus the pointer
to ROW 1 will be preserved. At Vertical Interrupt, the row
counter will be reset to 0 and we will want to do a pointer
lookup for ROW 2 in preparation for the CRSR load at the
end of ROW 1 (point A). Correspondingly, the row pointer
lookup tables are organized 2 to 25, 1. Since the attribute
latches aren't pipelined, the ALO lookup table is arranged 1
to 25 since the new attribute set will be needed immediately
for the display of the next row.
Next, the message tables are built up in the video memory.
By updating the attribute latch ALO each row, the entire
screen display can be constructed from the 7 message rows
stored in memory. Each of the message rows consist of 80
consecutive characters and are called up for display by
loading the HOME register with the address of the first character in the row. The background characters in each of the
rows are the spaces previously stored. Each of the display
characters stored use attribute latch ALO which is updated
each row. The first row (0-79) consists entirely of spaces to
provide us with a blank display row. The second row (80159) has the message "tmp does it BETTER'" for normal
and double high display. The third row (160-239) contains
"ttmmpp ddooeess iitt BBEETTTTEERRI!" for double wide
and double size display. Rows 4-7 contain 32 block graphics characters per row for a total of 128 patterns. The 128
characters stored are merely all binary combinations of the
low 7 data bits in ascending order. The 32 characters in
each row are stored in every other memory location to
achieve a blank space between characters. For all of the
message rows, data is positioned to give a centered display
on the screen.
With initialization accomplished, we set the interrupt mask,
re-enable interrupts and wait for a video interrupt.
Video display management is performed by the internal interrupt service routine located at 007 and consists of updating the HOME register and ALO at the end of each display
row. To accomplish this, a row counter (R3) is used as a
pointer into the data lookup tables which follow the interrupt
service routine. The R3 row counter is incremented on each
End of Row interrupt or preset and incremented on aresynching Vertical Interrupt.
z
w
U1
~
Row Table Lookup Plpelinlng
Because the next row pointers are pipe lined in the video
memory controller, an understanding of End of Rowand
Vertical Interrupt operation is necessary in order to correctly
set up the interrupt service routine and lookup tables. In
table lookup mode, the Current Row Start Register (CRSR),
which is a pointer to the first character address in a row, is
automatically reloaded from the HOME register after the
display of the last scan line in a row, a few characters into
horizontal blanking. The timing of the CRSR reload when
operating in sequential lookup mode is the same but in this
case the pointer is advanced by the character width of the
display row. It is the reloading of CRSR either in sequential
or table lookup modes that generates the End of Row interrupt. The duration of the signal is % CPU cycle making it a
one time event each row. The End of Row interrupt register
bit is cleared when a reload of HOME, i.e., MOV HOME, A is
ROW 1
A
ROW 2
+ROW3
TL/C/5729-2
FIGURE 2
•
7-47
~ r-----------------------------------------------------------------------------------~
in
TAD Interrupt Positioning
C")
Z
TMP Attribute Demo Program
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
9S
97
98
99
100
101
102
103
104
105
lOS
107
108
0015
0016
0017
0019
001A
001B
001C
B3
C2
2336
6B
B3
8A
93
Z
(Continued)
MOVP A, @A
MOV HACC, A
MOV A, #HOMLOW :GET HOME LOW ORDER BYTE
ADD A, R3
MOVP A, @A
MOV HOME, A
:LOAD HOME
RETR
W
U1
~
• FORM
:HOME HIGH ORDER BYTE LOOKUP TABLE
001D
001E
001F
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
002A
002B
002C
002D
002E
002F
0030
0031
0032
0033
0034
0035
0036
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
01
00
01
00
01
00
00
00
00
HOMHIG: .BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
• FORM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
H(LINE5)
0
H(LINE6)
0
H(LINE7)
0
0
0
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
;ROW
:ROW
:ROW
:ROW
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
:HOME LOW ORDER BYTE LOOKUP TABLE
0036
0037
0038
0039
003A
003B
003C
003D
003E
003F
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
004A
004B
004C
004D
004E
00
50
00
AO
00
50
50
00
AO
AO
00
AO
AO
00
00
FO
00
40
00
90
00
EO
00
00
00
HOMLOW: .BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
0
L(LINE2)
0
L(LINE3)
0
L(LINE2)
L(LINE2)
0
L(LINE3)
L(LINE3)
0
L(LINE3)
L(LINE3)
L(LINE1)
L(LINE1)
L(LINE4)
L(LINE1)
L(LINE5)
L(LINE1)
L(LINES)
L(LINE1)
L(LINE7)
L(LINE1)
L(LINE1)
L(LINE1)
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
7-49
2 BLANK
3 NORMAL
4 BLANK
5 DOUBLE WIDE
6 BLANK
7 DOUBLE HIGH
8 DOUBLE HIGH
9 BLANK
10 DOUBLE SIZE
11 DOUBLE SIZE
12 BLANK
13 DOUBLE SIZE
14 DOUBLE SIZE
15 BLANK
lS BLANK
17 GRAPHICS
18 BLANK
19 GRAPHICS
20 BLANK
21 GRAPHICS
22 BLANK
23 GRAPHICS
24 BLANK
25 BLANK
1 BLANK
•
TMP Attribute Demo Program
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
(Continued)
• FORM
;ATTRIBUTE LATCH 0 LOOKUP TABLE
004F
0050
0051
0052
0053
0054
0055
0056
0057
0058
0059
005A
005B
005C
005D
005E
005F
0060
0061
0062
0063
0064
0065
0066
0067
FF
FF
FF
FF
EF
FF
F7
B7
FF
E7
A7
FF
E2
82
FF
FF
7F
FF
7F
FF
7F
FF
7F
FF
FF
ATTO:
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
OFF
OFF
OFF
OFF
OEF
OFF
OF7
OB7
OFF
OE7
OA7
OFF
OE2
082
OFF
OFF
07F
OFF
07F
OFF
07F
OFF
07F
OFF
OFF
;ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
:ROW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
• FORM
;START OF INITIALIZING CODE
0068
0069
006A
006B
006D
006E
006F
0070
0072
0073
0075
0076
0078
0079
007B
007C
007E
007F
0081
0082
0084
0085
0087
0088
008A
008B
008D
008E
0090
0091
0093
0094
15
35
65
231A
A2
27
87
2367
B7
234F
B7
2353
B7
2363
B7
2391
B7
231A
B7
2318
B7
2362
B7
231E
B7
23F4
B7
2330
B7
2336
B7
2389
BEGIN;
DIS XI
DIS II
STOP T
MOV A, #26
MOV VINT, A
CLR A
MOV TCP, A
MOV A, #103
MOV @TCP, A
MOV A, #79
MOV @TCP, A
MOV A, #83
MOV @TCP, A
MOV A, #99
MOV @TCP, A
MOV A, #091
MOV @TCP, A
MOV A, #26
MOV @TCP, A
MOV A, #24
MOV @TCP, A
MOV A, #062
MOV @TCP, A
MOV A, #30
MOV @TCP, A
MOV A, #OF4
MOV @TCP, A
MOV A, #030
MOV @TCP, A
MOV A, #036
MOV @TCP, A
MOV A, #089
;INTERRUPTS OFF FOR NOW
;SET UP TIMING CHAIN FOR DEMO BOARD
;HORIZONTAL LENGTH
;CHARACTERS/ROW
;HORIZONTAL SYNC BEGIN
;HORIZONTAL SYNC END
;CHARACTER HEIGHT/EXTRA SCANS
;VERTICAL LENGTH
;VERTICAL BLANK
;VERTICAL SYNC BEGIN/END
;STATUS ROW BEGIN
;BLINK RATE
;GRAPHICS COLUMN REGISTER
;GRAPHICS ROW REGISTER
;UNDERLINE SIZE REGISTER
7·50
TMP Attribute Demo Program
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
0096 B7
0097 2309
0099 B7
(Continued)
MOV @TCP, A
MOV A, #009
MOV @TCP, A
;CURSOR SIZE REGISTER
009A 2324
009C 55
MOV A, #024
MOV SCR, A
;SET SYSTEM CONTROL REGISTER
;8 BI,7 DOTS, DIVIDE 1, TABLE LOOKUP
0090
009E
009F
OOAO
00A1
00A2
C3
27
C2
8A
00
88
SEL RBO
CLR A
MOV HACC, A
MOV HOME, A
MOV BEGD, A
MOVL RO, A
;SELECT RAM BANK 0
;SET RAM POINTERS
00A3
00A5
00A6
00A8
00A9
OOAA
237F
C2
23FF
OC
8B
3D
MOV
MOV
MOV
MOV
MOV
MOV
»
z
.
w
U1
0l:Io
• FORM
A, #07F
HACC, A
A, #OFF
ENDD, A
CURS, A
ALl, A
;CLEAR MEMORY POINTER
;NO ATTRIBUTES FOR LATCH 1
;CLEAR OUT MEMORY
OOAB BD19
OOAD BA50
OOAF 23AO
00B1
00B2
00B3
00B5
00B7
80
38
EAB1
BA50
EDB1
00B9 2321
OOBB 45
LOOP:
MOV R5, #25
MOV R2, #80
MOV A, #OAO
;00 25 ROWS
;00 80 CHARACTERS PER ROW
;INITIALIZE FOR A SPACE, ATTRIBUTE LATCH 1
MOVX @RO, A
INCL RO
DJNZ R2, LOOP
MOV R2, #80
DJNZ R5, LOOP
;STORE A CHARACTER
;INCREMENT POINTER
;TEST IF ROW DONE
;TEST IF SCREEN DONE
MOV A, #021
MOV VCR, A
;SET VCR FOR INTERNAL ATTRIBUTES
:INTERNAL CHARACTER GENERATOR
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
OOBC
OOBE
OOBF
00C1
00C2
00C4
00C6
00C7
00C8
00C9
OOCA
OOCB
2300
C2
236E
88
BAEO
BB13
FA
B3
80
38
1A
EBC6
OOCD
OOCE
0000
0001
0003
0005
0006
0007
0008
0009
OODA
98
0334
88
BAEO
BB13
FA
B3
80
38
80
38
;FIRST LINE ARE ALL BLANKS, SECOND LINE HAS SINGLE SPACING MESSAGE
MOV A, #H(LINE2+30) ;SET RO POINTER TO FIRST LINE
MOV HACC, A
MOV A, #L(LINE2+30)
MOVL RO, A
MOV R2, #L(MSG1) ;SET R2 TO MESSAGE #1
MOV R3, # 19
;SET R3 TO MESSAGE LENGTH
DISP1: MOV A, R2
MOV A, @A
;DISPLAY NORMAL MESSAGE
MOVX @RO,A
INCL RO
INC R2
DJNZ R3, DISP1
.FORM
;THIRD LINE HAS DOUBLE WIDE MESSAGE
MOVL A, RO
;SET RO POINTER
ADD A, # (31 + 21)
;LINES3 + 21
MOVL RO, A
MOV R2, #L(MSG1)
MOV R3, #19
DISP2: MOV A, R2
MOVP A, @A
;DISPLAY DOUBLE WIDE
MOVX @RO, A
INCL RO
MOVX @RO, A
INCL RO
7·51
II
I
~
II)
('f)
z•
<
,------------------------------------------------------------------------------------,
TMP Attribute Demo Program
239 OODB lA
240 OODC EBD5
241 OODE 04F3
242
243 OOEO 74
244
245
246 00F3 98
247 00F4 031D
248 00F6 88
249 00F7 BB04
250 00F9 BA20
251 OOFB 2300
252 OOFD 2400
253
254
0100
255
256 0100 80
257 0101 38
258 0102 38
259 0103 17
260 0104 EAOO
261
262 0106 BA20
263 0108 AC
264 0109 98
265 010A 0310
266 010C 88
267 010D FC
268 010E EBOO
269
270
271 0110 2303
272 0112 82
273 0113 25
274 0114 2414
275
ATTO
004F
00D5
DISP2
HOMHIG 001D
LINE2
0050
LINE6
0190
PAU
0114
(Continued)
INC R2
DJNZ R3, DISP2
JMP FOURTH
MSQ,l:
.BYTE 'tmp does it BETTER!'
:FOURTH LINE STARTS GRAPHICS CHARACTERS DISPLAY
FOURTH: MOVL A, RO
ADD A, # (21 + 8)
;LINE4 + 8
MOVL RO, A
MOV R3, #4
;DO 4 LINES
MOV R2, #32
;DO 32 GRAPHICS CHARACTERS PER LINE
MOV A, #000
;ATTRIBUTE LATCH 0 SELECTED
JMP BLOOP
0100
BLOOP:
MOVX @RO, A
INCL RO
INCL RO
INC A
DJNZ R2, BLOOP
MOV R2, #32
MOV R4, A
MOVL A, RO
ADD A, # (8+8)
MOVL RO, A
MOV A, R4
DJNZ R3, BLOOP
;STORE CHARACTER
;INITIALIZE FOR NEW ROW
;TEMPORARY SAVE A
;POINT TO NEXT LINE
;RESTORE A
;CONTINUE IF NOT THROUGH
;REENABLE INTERNAL INTERRUPTS AND
MOV A, #03
MOV MASK, A
EN II
;REENABLE
PAU:
JMP PAU
;WAIT FOR
END
BEGIN
BLOOP
0068
0100
EXI
EOR
OOOC
0003 *
HOMLOW 0036
INI
0007 *
LINE3
OOAO
LINE4
OOFO
LINE7
OlEO
LOOP
OOBl
RESET
0000 *
NO ERROR LINES
272 ROM BYTES USED
SOURCE CHECKSUM= CF60
OBJECT CHECKSUM= 0576
INPUT FILE A: TAD. MAC
LISTING FILE A: TAD. PRN
OBJECT FILE A: TAD. LM
7-52
MASK OFF UNUSED ONES
INTERNALS
A VIDEO INTERRUPT
DISPl
FOURTH
LINEl
LINE5
MSGl
00C6
00F3
0000
0140
OOEO
TMP - Dynamic RAM
Interfacing
National Semiconductor
Application Note 355
James Murashige
TMPs Interface easily and directly to dynamic RAMs as illustrated in the basic TMP system schematic of Figure 1. In
addition to providing the necessary Read/Write cycle control, the TMP will also automatically refresh the memories
through the video controller, further easing interface requirements.
period consists of 25 scan lines for a total duration of 1.52
ms. Assuming sequential rather than table lookup operation,
80 consecutive character addresses are accessed each
scan line and a 160 consecutive character addresses are
accessed every 2 rows; more than enough to refresh all of
the RAS rows. Of course one must be sure that the memory
addresses of any two consecutive rows encompass all 128
possible RAS addresses. In the middle of the screen the
worst case refresh period is 11 scan lines (.667 ms), since
to do 160 consecutive addresses requires one complete
row plus the first scan line of the next row. At the bottom of
the screen the refresh period must also include the vertical
blank time since no video characters are accessed then. In
this case refresh stretches out to a worst case 2.184 ms.
Although in this example we exceeded the 2 ms refresh
period, there are a number of things that we could do to get
things back into spec. For example, we could cut down on
vertical blank time, use memory chips with longer refresh
periods, or have the CPU refresh video memory during vertical retrace. Taking the case of using different memory
chips, another popular refreshing arrangement is 256 row
addresses in 4 ms. In the middle of the screen this gives us
a worst case period of 10 + 10 + 10 + 1 scan lines or 31
X 60.67 us = 1.88 ms. Adding in the vertical blanking period the absolute worst case refresh delay is 1.88 + 1.52 =
3.4 ms. Of course in this arrangement, making sure that any
four consecutive rows encompass all 256 RAS addresses is
much more difficult.
When operating in pixel mode meeting refresh requirements
isn't as difficult since each scan line will access a different
set of consecutive RAM addresses.
The circuitry to the right of the TMP provides program memory interfacing and I/O support while to the left lie the dynamic video RAM circuits. The memory width shown here is
8 bits although 16 bits can easily be accommodated. Using
the 64K x 1 dynamic RAMs shown the entire video memory
space is filled with RAM. However, by using a slightly modified addressing configuration smaller memroy chips could
be substituted.
The requisite dynamic RAM control signals RAS, CAS and
WE are generated directly from the system bus control signals RAM ALE, RAM RD and RAM WR. RAM ALE is used
directly as RAS while RAM WR serves as WE. CAS is the
logical AND of RAM RD and RAM WR. The 16 system bus
bits are multiplexed down to the 8 bit RAM address vector
by the two 74LS157's under the control of the RAM ALE. As
configured, the row and column addresses strobed in are
S80-7 and S88-15 respectively.
With the configuration shown, the pertinent TMP Read and
Write cycle timing parameters for Figure 2 are listed in Table
1. Going through the table one sees that the TMP easily
interfaces to 150 ns access RAMs and will routinely work
with 200 ns RAMs. The four parameters which may be a
tight squeeze for 200 ns RAMs are:
1. tAAG- Access Time from RAS is max 150 ns, typ 220 ns.
This is a basic access time requirement which necessitates fast parts.
2. tAAH- Row Address Hold Time is min 10 ns, typ 15 ns.
This parameter is entirely dependent on the
switching speed of the 74LS157.
3. tACO- RAS to CAS Delay Time is min 10 ns, typ 50 ns.
This parameter isn't too critical since most dynamic RAMs internally gate the CAS signal
should it come along too early.
4. tAP- RAS Precharge Time is min 100 ns, typ 135 ns.
Since RAS is actually the RAM ALE signal tAP is
the high time of RAM ALE.
However, rather than getting faster RAMs one could also
meet spec by running the TMP CPU slower, thereby stretching out the allowable access time.
Since the TMP video controller will regularly and automatically access video memory in order to obtain characters for
display, one may have dynamic RAM refreshing performed
automatically by making sure that the required number of
consecutive address locations (ROW Addresses) are accessed in the alloted time. Typically this is 128 ROW addresses in 2 ms.
For example, in a typical system we may have an 80 column
by 25 row display with each row consisting of 10 scan lines.
Each scan line has a period of 60.67 us. The vertical blank
.
>
Z
w
U1
U1
Returning to the circuit of Figure 1, we have assumed that
S80-7 are multiplexed address/ data while S88-15 output
addresses only. Since the RAM addresses are latched in 8
bits at a time there is no need for a separate latch for S807 since all 8 bits are clocked in on the falling ALE edge.
However, when operating with smaller 8K or 16K RAMs
where only 7 bits are clocked in at a time, latching arrangements for S87 must be made. An example of this is shown
in Figure 3 where bits S80-7 are all latched by the
74LS373.
Normally I/O registers, as well as other memory banks, will
also be memory mapped into the 64K video RAM space. In
order to do this some sort of chip enabling scheme must be
worked out since the dynamic RAMs have no direct enable
control. One possibility is shown in Figure 4 where the RAM
bank CAS and WE are disabled unless selected by the
74LS138 decoder. In this way the RAM output drivers will
remain TRI-STATE® and no data will be written unless the
bank is selected. However, memory refreshing as controlled
by RAS will still be performed on each RAM bank.
8y expanding on these basic examples a memory configuration for the TMP utilizing dynamic memories may be quickly and easily worked out.
7-53
•
TABLE 1. TMP Dynamic RAM Interface Timing 12 MHz CPU
Symbol
Parameter
Min
Typ
tAR
Column Address Hold Time Referenced to RAS
250
280
Max
tASC
Column Address Set Up Time-Dependent on Switching of 74LS157
25
35
ns
tASR
Row Address Set Up Time
20
90
ns
Units
ns
tCAC
Access Time from CAS
tCAH
Column Address Hold Time
140
250
tCAS
CAS Pulse Width
140
160
ns
tcp
CAS Precharge Time
140
166
ns
tCRP
CAS to RAS Precharge Time
100
136
ns
tCSH
CAS Hold Time
250
280
ns
tCWL
Write Command to CAS Lead Time
140
160
ns
tOH
Data In Hold Time
160
175
ns
tOHR
Data In Hold Time Referenced to RAS
180
310
ns
tos
Data In Set Up Time
10
50
tOFF
Output Buffer Turn Off Delay
tRAC
Access Time from RAS
tRAH
Row Address Hold Time-Dependent on Switching of 74LS157
180
0
220
140
ns
ns
ns
60
ns
150
ns
10
15
tRAS
RAS Pulse Width
250
280
tRC
Random Read/Write Cycle Time
416
tRCO
RAS to CAS Delay Time
10
50
ns
tRCH
Read Command Hold Time
100
175
ns
tRCS
Read Command Set Up Time
100
175
ns
tRP
RAS Precharge Time
100
135
ns
tRRH
Read Command Hold Time Referenced to RAS
100
175
ns
tRSH
RAS Hold Time
140
160
ns
tRWL
Write Command to RAS Lead Time
140
150
ns
tWCH
Write Command Hold Time
140
150
ns
tWCR
Write Command Hold Time Referenced to RAS
160
275
ns
twcs
Write Command Set Up Time-Dependent on Delay of 74LS08
5
11
ns
twp
Write Command Pulse Width
140
150
ns
7·54
ns
ns
ns
5V
10k
29
EA
SO
FEMALE
RS232
CONNECTOR
SI
PSEN
RE12
REll
RE10
RE9
At
NS405
RE8
ALE
30
36
5V
3.9k
3.9k
37
38
39
21
47
'"'U,
5V
35
MS8
5 7 6 12 11 10 13 9
U1
14
1
SBO
AD Al A2 A3 A4 A5 A6 A7
DO
All M88264
RAS
01
00
2
SBl
01
CAS
A12
MB8264
DO
3
SB2
Al3
MB8264
01
Wii
Vss
Vee
DO
4
SB3
01
lN9l4
DO
Al5
5
SB4
01
6
SB5
01
MB8264
A16
MB8264
A17
MB8264
AlB
MB8264
DO
DI
23
32
5V
20 pF
DO
7
SB6
XTALl
A14 MB8264
U
12 MHz
1q'~1' l'
DO
8
SB7
01
TUC/5732-1
FIGURE 1. TMP with 64K Dynamic Memory
SSE-NY
II
.
&I)
&I)
Cf)
Z
Ti ming Diagrams
Read Cycle Timing Diagram
z
w
U1
U1
SE
SBB
SB9
SB10
74LS157
AD
A1
DYNAMIC A2
RAM A3
A4
A5
A6
1Y
2Y
3Y
4Y
SBO
SB1
SB2
1Y
2Y
3Y
4Y
74LS157
RAM ALE
SB11
SB12
SB13
--SB14
--SB15
TL/C/5732-4
FIGURE 3. TMPAddress Multiplexing for 16K Dynamic RAMs
RAS"'I1~--------RAM
ALE
~~__~'-~~-RAMWR
_...r--RAMRD
64k MEMDRY SPACE
DIVIDED INTO ak BANKS
74LS138
TL/C/5732-5
FIGURE 4. Chip Enabling Dynamic RAMs
•
7-57
TMP External Character
Generation
National Semiconductor
Application Note 367
James Murashige
Built into the TMP video circuitry is the ability to access an
external character generator to display custom FONT sets.
In addition to the flexibility afforded by user selectable
FONTs, by going "external" the number of different character patterns directly addressable is virtually limitless. On the
other hand the disadvantages of going external are the additional hardware necessary to control data routing and the
general need to use faster memories.
to the system bus. The other three "dummy" lines shown
connected are actually output bits which are always 0 by
default, thus giving us blank spaces. There are two reasons
why the character bits start on SB1. The first is that since
everything brought in is considered pixel data, spaces between characters must be externally inserted. The second is
that the video controller always brings in 8 bits even though
the cell width can be defined to be 9 or 10. In these instances the 9th and 10th bits repeat what was encoded into
the SBO bit. As a result external characters can practically
be at most 7 dots wide although the cells can be up to 8, 9,
or 10 dots wide. Cell and/or character heights can be up to
16 lines tall as specified by the Character Scan Height Register.
Figure 1 shows a minimum configuration with which to do
external character generation. In the TMP, external character generation is selected through Video Control Register
bits 6, 7 and is a cross between normal alphanumeric and
pixel graphics display modes. Like normal alphanumeric
mode the TMP sequences through the video memory address space based upon the screen format specification.
But instead of routing the data through the internal character generator, it is treated as pixel data and directly inserted
into the video dot stream. In effect what we are doing externally is duplicating the internal character generator ROM. In
external mode video attributes are fully operational except
for double height and block graphics.
Operation of the circuit shown is straight forward and follows a pipe-line approach. On a video data read the display
memory address is output onto the system bus with the 8
low order bits being latched by the 74LS373. On the RAM
AD signal the 2116 display RAM ouputs a data character
onto the pipeline bus which is used to address the
MM52116 character generator which in turn deposits the
required pixel data onto the system bus so that it may be
read in. The 2116 determines which character is to be
looked up in the 52116 while the 74LS163 tells the character generator which row in the character we wish to look at.
The 74LS163 is a counter which is appropriately clocked by
the horizontal sync pulse so that we will advance each scan
line to point to the next row in the character FONT. At the
end of each screen row the counter must be cleared in
preparation for the display of a new row. This is the function
of the Scan Count Clear signal which is available as a multiplexed output on t\1e RE11 pin. It is a low going signal which
pulses for 1 scan line time during the last scan line in a
screen ROW. Its timing is shown in Figure 2. Note that since
the 74LS163 is a fully synchronous counter the clear input
will not be accepted until the very last H-Sync clock pulse in
the screen row. Because of the necessity to not clear the
counter before all pixel data is brought in, nor to delay clocking lest the Scan Count Clear pulse be missed, the starting
H-Sync clock edge must be postioned close to the start of
horizontal blanking.
Continuing with the read operation, we see that video RAM
is only accessed if SB15 is low, i.e., the lower 32K. Note that
the 52116 used here contains 128 characters in a 5 x 7
FONT. Consequently, it has 5 data output lines connected
On a video memory write, data is routed through the
81 LS95, onto the pipe-line bus and into the 2116. Writing
into the 2116 is controlled by RAM WR as shown. Ordinarily
the MSB data bit is used for internal attribute latch selection
and could be directly connected to the SB7 line if character
cells were specified to at most be 7 dots wide. Otherwise
SB7 will be needed for pixel generation as shown in Figure
1, thereby rendering internal attribute latch selection useless. In this case both internal attribute latches would have
to be loaded with the same values. As shown here, 7 video
RAM data bits are used to address the 128 possible characters in the 52116. If a larger character generator were available, additional data bits could be used to select from a
larger character set. Since the TMP features a 16-bit multiplexed address/data bus, by using all 16 available data bits
we could address 65,536 different character patterns
With the video data pipe-lined as shown, very fast memory
circuits are required for external character generation. With
a 12 MHz CPU clock, character pixel data must be available
within a max of 220ns (typ. 300ns) after an address goes
out. To accomplish this the character generator will typically
have to be bipolar and the video RAM fast MOS. However, if
faster memories are a problem, access times may be
stretched out by slowing down the CPU clock since video
RAM cycling is based on the CPU clock. For instance with a
CPU clock of 8 MHz, access time stretches out to 385 ns
max, 500 ns typo If using the divide by 1.5 factor on the
crystal to obtain the slower CPU clock, remember that due
to system constraints the character cell MUST BE AT
LEAST 8 DOTS WIDE. In Figure 1 the 2116 output enable is
shown being driven by RAM RD. Although this may seem
redundant and will slow things down (why not just leave the
output enabled?) it is necessary in order to avoid bus conflict when doing a memory write operation.
By expanding on this basic circuit, numerous options such
as external attributes, expanded character sets and dynamic RAM may be added to achieve the desired end system.
7-58
TMP EXTERNAL CHARACTER GENERATOR
11
SB10
10
SB9
9
SB8
19
16
15
12
9
6
5
----;
~
8Q
70
60
50
40
74LS373
3D
20
10 ENG
111
RAM
DE
18
80
70 17
14
60
13
50
B
40
7
3D
4
20
3
10
8
7
6
5
4
3
2
1
iiD
ALE
18 16 14 12 8 6 4 2
AS A7 A6 A5 A4 A3 A2 Al
RAMr-G
WR
19
19 12 23 1 2 3 4 5 6 7 8
A1D A9 AS A7 A6 A5 A4 A3 A2 Al AD
07
06
05
04
03
02
01
9
DO
2116
CS
p8
SB15
DE
ii1
81lS95
ii2
Y8 Y7 Y6 Y5 Y4 Y3 Y2 Yl
17
16
15
14
13
11
10
IzD
.!
.....JJ.
----!.!!.
RAM
Rli
Wii
RE11
ALE
1
SB15 5V
121 13 14 15 16 17
h8
6
3
CSl CS2 CS3 01 02 03 O. 05
DUMMY
DUMMY
DUMMY
2
CK
5V
D CUl
1I274LS74
_
o
PR
4
5
17 15 13 11 9 7 5 3
19
22
23
1
2
3
4
A6
A5
A4
MM52116FOW
A3
A2
Al
AD
WE
120
RAM
TMP
r rJ
RAM
.:!J
SB7
SB6
SB5
SB4
SB3
SB2
SBl
SBD
L2
l3
1~1 1~2
121
8
14
7
13
IlA
Oc
Os
74lS163
H SYNC...! ClK OD
5V....!!. lO
lO
II
ClR
ENP
ENT
P
10
5V
5V
1
SCAN COUNT CLR
1
TL/C/5731-1
19£-N'f
I
SCAN COUNT CLEAR TIMING
HORIZONTAL
HORIZONTAL
BLANKING BEGINS BlANKING ENDS
HORIZONTAL SYNC
LAST SCAN LINE IN ROW
OR FRAME BEING DISPlAYED
'--.3 CHARACTER
I - WIDTH TIMES
SCAN COUNT CLEAR
HORIZONTAL
HORIZONTAL
BLANKING BEGINS BLANKING ENDS
FIRST SCAN LINE IN NEXT ROW
BEING DISPlAYED
*EDGE CLOCKS CLEAR
INTO SCAN LINE COUNTER
----~I--------.~------~
TL/C/5731-2
• Edge must come before Scan Count Clear goes away but not before the video controller has brought in all necessary display Information for the last scan line.
Edge should not be more than 3 character widths from the beginning of blanking.
7-60
~
ZI
National Semiconductor
Application Note 369
James Murashige
NS405 TMP Logic Analyzer
INTRODUCTION
o
S T E P 7
The NS405 TMP is ideally suited for use in Test and Instrumentation equipment as the system or display controller. To
demonstrate this, the following note describes how to turn
the NS405 Demo Board into a simple 8 bit Logic State Analyzer. Featured in this system is a data capacity of 156 eight
bit words, 21 J.ls data acquisition time, keyboard command
entry, UP/DOWN rOiling scroll and 24 line data display.
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
2
2
2
SYSTEM ARCHITECTURE
All of the necessary resources to build our system are available in a TMP Demo Board system when normally set up as
a data terminal. Commands are entered through the attached ASCII encoded keyboard with data being strobed on
the external interrupt. Data words are input through the
switch configuration register SW2 by strobing the Light Pen
interrupt. Video is output to the attached display monitor.
The only real difference between our Logic Analyzer and the
Data Terminal is the ROM software in U9 running the TMP.
An overview of the system is shown in Figure 1.
In order to maximize the available 2k of video RAM, a display line length of 13 was chosen. This yields 157 lines of
display information (157 X 13 = 2041), one of which is
used to display title information. Thus our display data field
consists of 156 lines of information, any 24 of which may be
displayed at any given time. On each line is displayed the
STEP number, followed by 2 spaces and 8 bits of 1 or 0
information. A typical display pattern is illustrated in Figure
2. By manipulating the pointer registers in the TMP DMA
controller, the Title line is made to be stationary while the
rest of the screen scrolls. This is accomplished by reversing
the roles of the HOME register and Status Section SROW
pointer. Specifically HOME points to the last row in memory
which holds the title information while the status section is
set to start after the display of the first row. Scrolling is
accomplished by bumping the SROW pointer up or down 1
line width and checking for end of memory conditions.
o
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
2 3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
11
W
Q)
CD
A T A
0 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
0
0
0
0
0
o
o
0
0
_STATIONARY
0
0
0
0
SCROWNG
FIELD
0 0 0
TLIDD/6970-2
FIGURE 2. TMP Logic Analyzer Screen Format
SYSTEM SOFTWARE
Since the system must rely on external events at several
points before proceeding with processing, an interrupt driven approach was taken in structuring the software. A flowchart for the main program is shown in Figure 3. After system initialization there are 2 levels of processing associated
with our logic analyzer operation. The first is a wait for an
external interrupt signifying a new keyboard command. Referring to the keyboard service routine in Figure 4, the key is
first read in and decoded as to function. In our simple system there are only 3 commands:
S or s = Start data acquisition
U or u = Scroll display up
I or i = Scroll display down
VIDEO OUT
t------~ILlGHT PEN INTERRUPT
MONITOR
NS405
TMP
SYSTEM BUS
U9
PROGRAM
ROM
210(8
VIDEO RAM ....._ _...
EXTERNAL INTERRUPT 1 - - - - - 4
TLIDD/6970-1
FIGURE 1. TMP Logic Analyzer (System Overview)
7-61
•
I
The scrolling functions are easily handled in the service routine by bumping the memory pointers and checking for an
end of memory condition. A command to start data acquisition moves us to our second level of processing-the actual
acquisition and display of data.
time of 21 JJ.s between data strobes. In addition, since the
data isn't latched it must remain stable until the actual read
occurs. Following data acquisition, the stored data words
are disassembled into their ASCII "1's" and "O's" patterns
and the data entires numbered. With data acquistion completed, the program returns to await another keyboard command.
In both the keyboard and data acquisition interrupt service
routines, flags FO and F1 are used to pass system status
back and forth from the main program. In this way the main
program holds at major points while the service routines
accomplish their functions. The data acquisition routine
does nothing more than read data in from the SW2 port,
store it in video memory and check a loop counter to see
whether we have read in enough data. Since the Light Pen
interrupt is being used, only high to low transitions will initiate an SW2 read. While very little is being done in data
acquisition, it is time consuming because it's done in software. A count of Instructions yields a worst case processing
SUMMARY
As demonstrated, the NS405 is very effective as a display
controller in a video instrumentation system. Certain functions, however, such as data acquisition are better left to
dedicated hardware controllers. Nevertheless, the system
as presented is still a very useful diagnostic tool. Through
small enhancements to the hardware and software, features
such as word recognition, number base conversion, wider
data words and loop delay may readily be added.
SET "STARr' BIT.
DISABLE FURTHER KEYBOARD
INTERRUPTS. WAIT FOR
CURRENT INTERRUPT TO
GO AWAY.
RETURN
INITIALIZE
SET UP TIMING CHAIN AND VIDEO
POINTERS. CLEAR MEMORY. RESET
"START" AND "THROUGH" BITS.
PUT UP TITLE INFORMATION.
II OFF. EXI ON
WAIT FOR
KEYBOARD COMMAND
TLIDD/6970-4
FIGURE 4. TMP Demoboard Logic Analyzer
Command Input Routine
RESET "START." TURN OFF VIDEO.
CLEAR MEMORY, SET POINTERS.
CLEAR PENDING INTERRUPTS. ENABLE
INTERNAL INTERRUPTS
DATA ACQUISITION
LOOP
READ WORD IN
CLEAR INTERRUPT FLAG.
STORE IN VIDEO MEMORY.
BUMP POINTERS
DISASSEMBLE DATA. TURN VIDEO
ON. REENABLE KEYBOARD INTERRUPT.
RESET "THROUGH"
TL/DD/6970-3
FIGURE 3. TMP Demoboard Logic Analyzer
Main Program
RETURN
TL/DD/6970-5
FIGURE 5. TMP Demoboard LogiC Analyzer
Data Acquisition Routine
7-62
.
>
Z
w
1
2
en
CD
3
• TITLE
MAIN,' TMP LOGIC ANALYZER DEMO'
4
5
James Murashige 2/09/84
;This program turns the TMP Demo board into a simple 8 bi t logic analyzer.
;Command inputs are entered from the attached ASCII keyboard while data
;acquisition takes place through the switch configuration socket, S't/2.
;The DIP switch may have to be unsoldered from the board. Data is strobed
lin with an external clock applied to Light Pen Interrupt on 't/8A. Each time
;data acqusition is started 156 words of 8 bits each are acquired and displayed.
; Display is in the form of STEP location and the associa ted 8 bi t l ' sand 0' 8
;pattern.
;Commands are S· Start data acqusition
U • Scroll display up
I • Scroll display down
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
07DF
07EB
07EC
0020
0000
22
23
24
25
26
27
28
0000
29
30 0000 0452
31
32
0003
LSTLIN
MEMEND
STLIN
VON
VOFF
•
•
•
•
•
07DF
07EB
07EC
020
000
;START AT PROGRAM LOCATION 0
• • 00
RESET:
;START OF LAST LINE
; END OF MEMORY
;START OF TITLE LINE
;VIDEO ON
';VIDEO OFF
JMP BEGIN
; VECTOR TO RESET CODE
• • 03
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
0003 0412
0007
EXI:
JMP KEY
; VECTOR TO KEYBOARD COMMAND DECODE
• • 07
INI:
0007
0008
0009
OOOA
OOOB
oooC
OOOD
MOV A,INTR
MOVX A,@R1
MOVX @RO,A
MOVL A,RO
ADD A,R3
MOVL RO,A
DJNZ R2,NOTRU
8C
91
80
98
6B
88
EAll
CPL F1
oooF B5
0010 35
0011 93
0012
0013
0015
0016
0018
00IA
001 B
001D
001F
0020
0022
0024
0026
El
53DF
AA
D353
C627
FA
D355
C62B
FA
D349
C63C
A624
93
DIS II
;DATA STROBE INTERRUPT SERVICE
; CLEAR OUT INTERRUPT
;GET DATA CHARACTER
;STORE CHARACTER AWAY
; BUMP RO POINTER
; CHECK IF THROUGH
; YES THROUGH, SET INDICATOR BIT
; DISABLE LP INTERRUPT
NOTRU: RETR
; RETURN
• FORM
;KEYBOARD COMMAND DECODE
KEY:
IN PORT
;KEYBOARD DATA READ
ANL A,IIODF
~CONVERT LOWER TO UPPER CASE
MOV R2,A
;SAVE COpy IN R2
XRL A,II's'
JZ START
;GOTO START
MOV A,R2
XRL A,II'U'
JZ UP
;GOTO SCROLL UP
MOV A,R2
XRL A,II'I'
JZ DOWN ; GOTO SCROLL DOWN
CKOFF: JNXI CKOFF
;NOT A VALID KEY a WAIT FOR EX! TO GO AWAY
RETR
; RETURN
0027 95
0028 15
0029 0424
START:
002B 99
UP:
CPL FO
;START BIT SET
;DISABLE FURTHER KEYBOARD INTERRUPTS
DIS XI
JMP CKOFF
MOVL A,Rl
;SCROLL UP
TL/OO/6970-6
7-63
,.
en
CD
r-----------------------------------------------------------------------------------~
Cf)
z•
cC
72 002C 030D
73 002E 89
74 002F 0314
75 0031 E2
76 0032 03FB
77 0034 E639
78 0036 27
79 0037 C2
80 0038 89
81 0039 99
82 003A OE
83 003B 93
84
85 003C 99
86 003D 03F3
87 003F AA
88 0040 E2
89 0041 03FF
90 0043 F64D
91 0045 2307
92 0047 C2
93 0048 23DF
94 004A 89
95 004B OE
96 004C 93
97 004D C2
98 004E FA
99 004F 89
100 0050 OE
101 0051 93
102
103
104
105
106 0052 C5
107 0053 c3
108 0054 15
109 0055 35
110 0056 65
111 0057 27
112 0058 87
113 0059 2367
114 005B B7
115 005C 230C
116 005E B7
117 005F 2353
118 0061 B7
119 0062 2363
120 0064 B7
121 0065 2391
122 0067 B7
123 0068 231 A
124 006A B7
125 006B 2318
126 006D B7
127 006E 2362
128 0070 B7
129 0071 2300
130 0073 B7
131 0074 23F4
132 0076 B7
133 0077 2330
134 0079 B7
135 007 A 2336
136 007C B7
137 007D 2389
138 007F B7
139 0080 2309
140 0082 B7
141
142
ADD A,#13
;ADVANCE TO NEXT ROW
MOVL Rl,A
;SAVE NEW VALUE
ADD A,#L(-L(STLIN»
;CHECK FOR END OF DISPLAY
MOV A,HACC
;SUBTRACT STLIN FROM A
ADD A,#L(-H(STLIN) - 1) ;CARRY WILL BE SET IF A WAS> OR •
JNC UPTRU
iNEW VALUE OK, LOAD SROW AND RETURN
CLR A
;RESET SROW TO BEGINNING
MOV HACC,A
MOVL Rl,A
UPTRU: MOVL A,Rl
;LOAD Rl INTO SROW
MOV SROW,A
RETR
DOWN:
MOVL A,Rl
;SCROLL DOWN
ADD A,#-13
;SUBTRACT TO NEXT ROW
MOV R2,A
;TEMP SAVE OF LOW ORDER
MOV A,HACC
iNOW DO UPPER HALF
ADD A,HoFF
iCARRY WILL BE SET IF A WAS 12 OR MORE
JC DNTRU
;NEW VALUE OK, LOAD VALUE INTO SROW
MOV A,#H(LSTLIN)
;RESET SROW TO LAST ROW
MOV HACC,A
MOV A, #L(LSTLIN)
MOVL Rl,A
MOV SROW,A
RETR
DNTRU: MOV HACC, A
MOV A,R2
MOVL Rl,A
MOV SROW,A
RETR
.FORM
;START OF INITIALIZING CODE
BEGIN:
SEL MBO
SEL RBO
DIS XI
; INTERRUPTS OFF FOR NOW
DIS II
STOP T
;TIMER OFF
CLR A
;SET UP TIMING CHAIN FOR DEMO BOARD
MOV TCP, A
MOV A, #103
iHORIZONTAL LENGTH
MOV @TCP, A
MOV A, #12
i CHARACTERS/ROW
MOV @TCP, A
MOV A, #83
iHORIZONTAL SYNC BEGIN
MOV @TCP, A
MOV A, #99
iHORIZONTAL SYNC END
MOV @TCP, A
MOV A, #091
;CHARACTER HEIGHT/ EXTRA SCANS
MOV @TCP, A
MOV A, #26
iVERTICAL LENGTH
MOV @TCP, A
MOV A, #24
iVERTICAL BLANK
MOV @TCP, A
MOV A, #062
iVERTICAL SYNC BEGIN/END
MOV @TCP, A
MOV A, #00
iSTATUS ROW BEGIN
MOV @TCP, A
MOV A, #OF4
i BLINK RATE
MOV @TCP, A
MOV A, #030
iGRAPHICS COLUMN REGISTER
MOV @TCP, A
MOV A, #036
iGRAPHICS ROV REGISTER
MOV @TCP, A
MOV A, #089
iUNDERLINE SIZE REGISTER
MOV @TCP, A
MOV A, #009
;CURSOR SIZE REGISTER
MOV @TCP,A
TL/DD/6970-7
7·64
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
:t:.
Z
w•
en
.FORM
; SET SYSTEM CONTROL REGISTER
;8 BI, 7 DOTS, DIVIDE 1, SEQUENTIAL LOOKUP
0083 2304
0085 55
MOV A, #004
MOV SCR, A
0086
0087
0088
0089
oo8A
008B
008C
008E
008F
0091
0092
0093
0095
0096
0097
0098
0099
009A
oo9B
009D
82
CLR A
;SET VIDEO RAM POINTERS
MOV HACC, A
; ACCUMULATOR CLEARED
MOV BEGD, A
MOV SROW, A
; SROW WILL BE OUT HOME
MOVL RO, A
;CLEAR HEMORY POINTER
MOVL Rl, A
; 1 IS SROW IMAGE
MOV A, #H(MEMEND +1)
MOV HACC, A
MOV A,#L(MEMEND +1)
MOV ENDD,A
;SET END OF MEMORY POINTER
MOV HOME, A
;SET POINTER TO TITLE ROW
MOV A, #OFF
MOV HACC,A
MOV CURS, A
;NO CURSOR
MOV ALO, A
;NO ATTRIBUTES FOR LATCH 0
MOV ALI, A
;NO ATTRIBUTES FOR LATCH 1
CLR FO
;FO IS "START" BIT
CLR Fl
;Fl IS "THROUGH" BIT
MOV A,#020
MOV MASK,A
;SET INTERRUPT MASK
3456
CALL MEMCLR
05
2400
EN XI
; REENABLE EXTERNAL INTERRUPTS
JMP LINNUM
;DISPLAY TITLE INFORMATION
161
162
163
164
165
166
167
168 oo9E
169
170 OOAO
171 OOAI
27
C2
OD
OE
88
89
2307
C2
23EC
OC
8A
23FF
C2
8B
3C
3D
85
A5
2320
CD
; CLEAR VIDEO MEMORY
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
OOA3 86A3
KEYIN:
JNFO KEYIN
;WAIT FOR KEYBOARD INPUT
.FORM
;DATA ACQUISITION ROUTINES
00A5
00A6
00A8
00A9
OOAB
OOAC
OOAD
OOAE
OOBO
00B2
00B3
OOB5
00B6
00B7
OOB9
OOBA
85
2300
45
3456
27
C2
OE
BA9C
2305
88
23CO
C2
89
BBOD
8C
25
CLR FO
;CLEAR START BIT
MOV A,#VOFF
;VIDEO OFF
MOV VCR,A
; CLEAR VIDEO MEMORY
CALL MEMCLR
CLR A
MOV HACC,A
MOV SROW,A
;RESET SROW TO BEGINNING
MOV R2, #156
;SET LOOP COUNTER FOR # WORDS TO READ
MOV A,#5
MOVL RO,A
;SET MEMORY POINTER TO FIRST DATA DEPOSIT
MOV A,#OCO
MOV HACC,A
MOVL Rl,A
;LOAD Rl WITH ADDRESS OF SWITCH REGISTER
;LOAD R3 WITH POINTER BUMP CONSTANT
MOV R3,#13
MOV A,INTR
; CLEAR OUT ANY PENDING INTERRUPTS
EN II
;REENABLE LP INTERRUPT
;WAIT FOR "THROUGH" BIT TO SET
ooBB 66BB
DATAIN: JNFI DATAIN
OOBD
ooBE
OOCO
ooCl
00C2
ooC4
00C5
ooC7
00C8
ooCA
ooCB
OOCC
OOCD
OOCF
OODI
; DISASSEMBLE DATA INTO DISPLAY FORMAT
CLR Fl
;RESET "THROUGH"
MOV R2,#156
;DISASSEMBLE DATA, LOAD WORD COUNTER
CLR A
MOV HACC,A
MOV A,#5
;SET KEMORY POINTER TO FIRST DATA DEPOSIT
MOVL RO,A
;DO 8 BITS
MOV R3,#8
UNASS: MOVX A ,@RO
;LOAD IN DATA BYTE
JMP DEPST
RETRIV: KOV A,R4
;RETRIEVE CHARACTER
DEPST:
RLC A
;ROTATE BIT INTO CARRY
MOV R4, A
; TEMPORARY SAVE
JC ONE
;STORE A "1"
MOV A,#'O'
;STORE A "0"
JMP CONT
A5
BA9C
27
C2
2305
88
BBOS
90
04CB
FC
F7
AC
F6D3
2330
04D5
7-65
TL/OO/6970-8
•
~ r-----------------------------------------------------------------------------~
CD
C")
z•
ct
214 OOD3 2331
215 00D5 80
216 OOD6 38
217 OOD7 EBCA
218
219 OOD9 98
220 OODA 0305
221 OODC 88
222 OODD BB08
223 OODF EAC7
224 OOE1 2400
225
226
227
0100
228
229 0100 27
230 0101 C2
231 0102 88
232 0103 BA9C
233 0105 BBOA
234 0107 BCOA
235 0109 BDOA
236
237 010B FB
238 010C 343B
239 010E 80
240 010F 38
241 0110 FC
242 0111 343B
243 0113 80
244 0114 38
245 0115 FD
246 0116 343B
247 0118 80
248
249 0119 98
250 011 A 030B
251 011 C 88
252
253 011 D ED26
254 011 F BDOA
255 0121 EC26
256 0123 BCOA
257 0125 CB
258
259 0126 EAOB
260
261 0128 9A
262 0129 88
263 012A BAOD
264 012C BB49
265
266 012E FB
267 012F B3
268 0130 80
269 0131 38
270 0132 1B
271 0133 EA2E
ONE:
CONT:
MOV A,II'1'
;STORE A "1"
MOVX @RO,A
;STORE CHARACTER
INCL RO ; INCREMENT POINTER
DJNZ R3,RETRIV ; CONTINUE IF WORD NOT DONE
MOVL A,RO
ADD A,1I5
MOVL RO,A
MOV R3,#8
DJNZ R2, UNASS
JMP LINNUM
l BUMP MEMORY POINTER TO NEXT WORD
l RESET BIT COUNTER
;CONTINUE IF ALL LOCATIONS NOT DONE
; JUMP TO NEXT PAGE
.FORM
l LINE NUMBBRING ROUTINES
• - 0100
LIl/NUM: CLR A
MOV HACC,A
MOVL RO,A
MOV R2,#156
MOV R3,#10
MOV R4,#10
MOV R5,#10
NUMLP:
MOV A,R3
CALL LKUP
MOVX @RO,A
INCL RO
MOV A,R4
CALL LKUP
MOVX @RO,A
INCL RO
MOV A,R5
CALL LKUP
MOVX fIiIRO,A
l CLEAR MEMORY PODITER
lDO 156 LINES
lSET HUNDREDS POINTER
;SBT TENS POINTER
;SET ONES POINTER
l LOOK UP HUNDREDS ASCI I CODE
;STORE HUNDREDS ASCII CODE
l LOOK UP TENS ASCI I CODE
; STORE TENS ASCII CODE
; LOOK UP ONES ASCII CODE
; STORE ONES ASCII CODE
MOVL A,RO
ADD A,#11
MOVL RO,A
l BUMP RO TO NEXT LINE
DJNZ R5, CONNUM
MOV R5,1I10
DJNZ R4, CONNUM
MOV R4,#10
DEC R3
l INCREMENT ONES POINTER
;MUST NOW INCREMENT TENS
; INCREMENT TENS POINTER
;MUST NOW INCREMENT HUNDREDS
CONNUM: DJNZ R2,NUMLP
;DO ANOTHER ROW
MOV A,HOME
lPUT UP TITLE LINE
MOVL RO,A
MOV R2, 1113
l LOOKUP 13 CHARACTERS
MOV R3,#L(TITLE)
lLOAD POINTER TO ASCII TITLE STRING
TITLP:
MOV A,R3
MOVP A,@A
MOVX @RO,A
INCL RO
INC R3
DJNZ R2, TITLP
272
273
274
275
276
277
278
279
280
281
282
283
284
• FORM
0135
0137
0138
0139
MOV A,#VON
;TURN VIDEO BACK ON
MOV VCR,A
EN XI
l REENABLE KEYBOARD INTERRUPTS
JMP KEYIN
;RETURN AND WAIT FOR NEXT START
2320
45
05
04A3
;SUBROUTINES
013B 033E
013D B3
OnE 93
LKUP:
ADD A,#L(CHAR)-1;
MOVP A,@A
lLOOK UP ASCII NUMBER
RETR
l RETURN
TL/DD/6970-9
7-66
:t>
ZI
285
286 013F j9
287
288 0149 53
289
290 0156 27
291 0157 C2
292 0158 88
293 0159 BAOO
294 015B BB08
295 015D 2320
296 015F 80
297 0160 38
298 0161 EA5F
299 0163 BAOO
300 0165 EB5F
301 0167 93
302
303
BEGIN
0052
CONT
00D5
DOliN
003C
KEYIN
00A3
MCLRLP 015F
NUMLP
010B
START
0027
UNASS
00C7
VON
0020
w
CHAR:
.BYTE '987654"5210'
TITLE:
.BYTE 'STEP 7 DATA 0'
C)
CD
MBMCLR: CLR A
;VIDEO MEMORY CLEAR LOOP
MOV HACC,A
;ACCUMULATOR CLEAR
MOVL RO,A
;RO CLEAR
; INNER LOOP COUNTER SET
MOV R2,#0
;OUTER LOOP COUNTER SET
MOV R3, #8
MOV A,#020
; SPACE CHARACTER
MCLRLP: MOVX @RO,A
; STORE A CHARACTER
INCL RO
;INCREMENT POINTER
DJNZ R2, MCLRLP
;TEST INNER LOOP
;RELOAD INNER LOOP COUNTER
MOV R2,#0
DJNZ R3, MCLRLP ;TEST OUTER LOOP
RETR
;THROUGH, RETURN
.END
CHAR
DATAIN
EXI
LINNUM
MEMCLR
ONE
STLIN
UP
013F
OOBB
0003 •
0100
0156
00D3
07EC
002B
CKOFF
DEPST
INI
LKUP
MEMEND
RESET
TITLE
UPTRU
0024
OOCB
0007 •
013B
07EB
0000 •
0149
0039
CONNUM
DNTRU
KEY
LSTLIN
NOTRU
RETRIV
TITLP
VOFF
0126
004D
0012
07DF
0011
OOCA
012E
0000
NO ERROR LINES
328
ROM BYTES USED
SOURCE CHECKSUM
OBJECT CHECKSUM
= 40D8
= 0649
INPUT
FILE A LOGIC.MAC
LISTING FILE A LOGIC.PRN
OBJECT FILE A LOGIC.LM
TLlDD/6970-10
•
7·67
I
Building an Inexpensive but
Powerful Color Terminal
National Semiconductor
Application Note 374
Leigh Cropper
Historically, the design of a color CRT terminal has involved
a significant upgrade of the circuit for a monochrome terminal. The result was a stiff increase in price for the electronics as well as for the monitor when going from monochrome
to color. As a result, most companies built monochrome
terminals and a few built color terminals only.
into the TMP, through the FIFO, the attribute control logic,
and finally to the video output section where the attributes
are combined with the serialized video output.
Because the display memory space may be large (up to 64k
x 16), it is easy to store many more attribute bits by adding
display memory chips. A 2k x 8 RAM will hold 8 attribute bits
for every location on an 80 row by 25 line display. However,
in order to implement color attributes, three problems must
be examined: (1) how to let both the CPU and the display
controller address the extra attribute memory in a practical
manner; (2) how to imitate the behavior of the internal FIFO
and maintain proper synchronization; and (3) how to combine the color attributes and the video output signal.
On the personal computer front where separate monitors
are common, manufacturers have started to offer video
cards which will support either a monochrome or a color
monitor. More recently, color terminals have begun to appear which are extensions of monochrome terminal families.
They require a board full of I.C.s for even the most space
efficient designs. But now, using the TMP, you can do the
same job with just one VLSI chip and a half dozen 7400
family TTL chips.
The National Semiconductor NS405 Series Terminal Management Processor (TMP) was originally conceived as a
monochrome "terminal on a chip". However, the design
team took special pains to build in "hooks" to allow users to
augment the basic features of the TMP. In particular the
TMP supports almost unlimited attribute expansion, and
therein lies the key to adding color to a TMP-based terminal.
Even nicer, the addition of color attributes does not sacrifice
any of the other powerful features provided by the TMP.
Here, we will delve into a little of the mechanics of TMP
attribute handling. The diagram in Figure 1 shows the path
of the attribute bits (normally 8) from the display memory
Before addressing the three problems in detail, a discussion
of the number and type of color attributes is in order. The
simplest type of color display would require only 3 bits (red,
green, and blue). That allows a character to be displayed in
any of 7 colors over a black background or, when reverse
video is asserted, the character is black on a colored background. For independent control of both the foreground and
background colors, 6 bits are required. To get more shades
of color, add more bits.
A practical approach employs a 2k x 8 RAM for the color
attribute memory. Three of the bits control the foreground
color, three control the background color and the remaining
two may be used to adjust intensity (1 for foreground and 1
for background).
EXTERNAL
DISPLAY
MEMORY
(DATA AND
ATTRIBUTE
MEMORy)
DOT
SHInER
AND
VIDEO
OUTPUT
LOGIC
VIDEO
OUT
TMP
TL/DDI7923-1
FIGURE 1. TMP Attribute ProceSSing
7-68
Now let's tackle the problems one by one.
1. COLOR ATIRIBUTE MEMORY ADDRESSING. When
fetching data for the display, we need to get 24 bits in
parallel (8 data, 8 attribute and 8 color attribute). But
when the CPU accesses memory, it can handle only 16
bits at a time, so the CPU must be able to read and write
color attributes in a different bank of memory from that
where the data and ordinary attributes are stored. For an
80 character by 25 row display the memory could be
mapped as shown in Figures 2 and 3:
4K
r-----------~------------~----------~2K
COLOR
ATTRIBUTE
MEMORY
ATTRIBUTE
MEMORY
COLOR
ATTRIBUTE
MEMORY
DATA
MEMORY
7 6 5 4 3 2 1 0
TL/00I7923-2
ATTRIBUTE
MEMORY
2K
DATA
MEMORY
FIGURE 2. Memory Map as Selected for Screen Refresh
TLl0017923-3
FIGURE 3. Memory Map as Selected
for CPU Access
The mapping is implemented by the following circuit:
SELECT D-2K
TMP
SBI-SB15 ...-
A11-A15
.....
DECODER
SELECT 2K-4K
LATCH
AD-A10
SBD-SB7 ......"a..,...
YO
OCTAL
TRANSCEIVER
TL/00I7923-4
FIGURE 4. Color Attribute Memory Mapping Circuit
7-69
•
video output is low, background attributes are selected.
The outputs of the multiplexer (red, green, blue and intensity) directly drive the color monitor inputs. A minor
problem arises because the video output from the TMP
already includes the blanking signal. That makes it impossible to differentiate between a series of spaces in
the middle of the screen and the horizontal blanking interval. In either case, the video output is low. The easiest
solution is handled in software. let's assume that we
want an 80 column display and are using three 2K x 8
memory chips for the data, attribute and color memories.
We set up the TMP for 81 columns and then configure
the program so that the 81 st column always contains a
space code with all attribute bits off (including color).
That way the background color will always be black during both horizontal and vertical retrace. The cost is 25
locations in each of the memories, but we can afford that
many because an 80 x 25 display requires 2000 locations, leaving 48 free.
During a display refresh cycle the color attribute memory is
selected by the low bank select (the same select signal that
enables the data and attribute memories). However, the color attribute bits drive the external FIFO's, whereas the output from the other two memories is routed through the TMP.
The data path from the color attribute memory to the TMP is
buffered by an octal transceiver which is disabled when the
low bank is selected. During a CPU access to color attribute
memory, the high bank select enables the color attribute
memory and the octal transceiver. The direction control of
the transceiver is controlled by the RAM RD signal from the
TMP.
2. EXTERNAL FIFO SYNCHRONIZATION. The TMP provides FI ClK (FIFO Input Clock) and FO ClK (FIFO Output clock) signals which may be used to clock an external FIFO. The FI ClK signal is identical in timing and duty
cycle to the RAM RD signal except that FI ClK is disabled (stays high) when the CPU accesses display memory. When the 74lS224 is used as an external FIFO, FI
ClK must be inverted. The rising edge of FO ClK occurs
when output of the internal FIFO is loaded into the internal dot shifter. The FO ClK is used to empty a word from
the external FIFO and clock it into an octal latch.
A Practical Example
Here we will present a color terminal circuit with the associated program as an example of what you may want to do.
We started with the terminal design of the TMP development board. See the block diagram in Figure 5.
3. COMBINING COLOR ATTRIBUTES WITH VIDEO. When
using foreground and background color attributes, a
74lS157 multiplexer works nicely to switch between the
two. The eight color attribute bits from the latch are separated into groups of four. The video output signal is
used to switch the multiplexer. When the video output is
high, foreground attributes are selected: and when the
The block diagram of the color terminal (with the old portions of the original monochrome terminal unshaded and
the new color circuits shaded) appears in Figure 6. The new
circuitry was added in the prototyping area of the development board.
10
TLlDD17923-5
FIGURE 5. TMP Development Board Block Diagram
7-70
RED
GREEN
BLUE
INTENSITY
a:
§z
z
c
...
u
2
a::
10
TUDD17923-6
FIGURE 6. TMP Development Board Color Circuitry Block Diagram .
17l£-NV
I
The demonstration program which runs on the development
board allows limited color support. The Escape, V sequence
from the keyboard or the receiver prompts the program to
treat the next character received as an eight bit color attribute byte with the bit assignments as listed above. That
byte is written to the color attribute memory as each succeeding character is received, until another escape, V sequence is encountered. The table which follows Includes
the foreground and background color combinations for
characters which can be entered from the keyboard, but it
ignores the effect of the 2 high-order bits (foreground and
background intensity).
COLOR ATTRIBUTE BIT ASSIGNMENTS
The bit assignments are:
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
-
-
Blue foreground
Green foreground
Red foreground
Blue background
Green background
Red background
Foreground intensity
Background intensity
Without using the intensity control bits you get 8 foreground
colors: red, green, blue, magenta, cyan, yellow, white, and
black (beam off). The same 8 colors may be independently
selected for the background. There are several RGB monitors available in the moderate price range with sufficient
bandwidth to work with a 12 MHz TMP. Some of them include a separate intensity (or luminence) input. Others include internal decoding circuitry which provides the ability to
handle 4 bits of color input and provide as many as 16 different colors.
COLOR COMBINATIONS FOR RGB MONITORS
Table I gives the Foreground/Background color combinations that occur when using the ' Vv' Escape sequence. To set the current color attribute, all that you need
to do is select the color combination from the Table below,
and send it to the NS405 as part of the Vx sequence. For example. '< ESC> V'" causes the Foreground
color to be green and the Background color to be
red ... not all that pleasing, to my tastes, but choose what
you will.
TABLE I
Foreground/Background Color Combinations
Char
Fore/Back
Char
Fore/Back
Char
Fore/Back
sp
Black/Red
Blue/Red
Green/Red
Cyan/Red
Red/Red
Magenta/Red
Yellow/Red
White/Red
Black/Magenta
Blue/Magenta
Green/Magenta
Cyan/Magenta
Red/Magenta
Magenta/Magenta
Yellow/Magenta
White/Magenta
Black/Yellow
Blue/Yellow
Green/Yellow
Cyan/Yellow
Red/Yellow
Magenta/Yellow
6
7
8
Yellow/Yellow
White/Yellow
Black/White
Blue/White
Green/White
Cyan/White
Red/White
Magenta/White
Yellow /White
White/White
Black/Black
Blue/Black
Green/Black
Cyan/Black
Red/Black
Magenta/Black
Yellow/Black
White/Blue
Black/Blue
Blue/Blue
Green/Blue
K
Cyan/Blue
Red/Blue
Magenta/Blue
Yellow/Blue
White/Blue
Black/Green
Blue/Green
Green/Green
Cyan/Green
Red/Green
Magenta/Green
Yellow/Green
White/Green
Black/Cyan
Blue/Cyan
Green/Cyan
Cyan/Cyan
Red/Cyan
Magenta/Cyan
Yellow/Cyan
White/Cyan
I
"
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(
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7-72
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A
National Semiconductor
Application Note 399
Richard Lazovick
TMP Extended Program
Memory Application Note
OVERVIEW/INTRODUCTION
The purpose of this application note is to describe methods
for expanding the program memory of the NS405 series
TERMINAL MANAGEMENT PROCESSOR (TMP) and to
provide direction in software techniques for utilizing the expanded memory efficiently. The chip has a built-In capability
of addressing up to 8k of external program memory (ROM),
via the ROM Expand Bus, and 64k of video display memory
(RAM), via the System Bus. Although 8k of program memory is sufficient for most applications there are many applications, such as emulating multiple terminals or using many
look-up tables, that require still more memory. However, it is
very rare that the entire 64k of video RAM is used since that
is more than enough memory to store two screens of data in
the pixel mode or thirty-two screens of data in the alphanumeric/block graphics mode. Therefore it is practical to use a
video memory address to switch between two or more 8k
memory arrays.
The idea behind using a bank select switch to change from
one memory array to another is not new, nor is it difficult,
and when implemented properly it can be a very useful tool.
The TMP has all the necessary control signals to make both
the software and hardware straight-forward.
Block Diagram
ROM EXPAND BUS
TMP
u.
SYSTEM BUS
n
CONTROL
•
-u-
8k
8k
ROM
ROM
•••
I
ARRAY
SELECT
LOGIC
TL/DD/8430-1
•
7-73
.
(7)
(7)
C')
z
es after the MOVX instruction with the RET and JMP instructions still to be read in from memory before we actually
want to switch arrays. Each instruction takes two cycles,
therefore we want to delay our array switching signal by four
cycles. Looking at all the output signals on the TMP there
are two possible signals to use as a clock to delay the array
switching signal. These signals are PSEN and ALE (see
System Signals Timing Diagram).
HARDWARE
Now that we have made the software simple and straightforward we have to look at what hardware is necessary to
implement it.
We want to: 1) create two mutually exclusive enable
signals-one for each array,
2) be able to easily use and latch the address line signals, and
The main disadvantage of using ALE is that whereas we
want a rising edge to clock the flip-flops used for the delay,
the ROM addresses are not stable until the falling edge of
ALE. Therefore, we save one inverter by using PSEN.
3) delay the actual switching of arrays
until after the jump instruction, with
the new address, is read into the TMP
from the old array.
One possible circuit implementation is shown below:
Looking at the program we see that the system bus chang-
Circuit Diagram
2184
HI ARRAY
S814-t>e----.
20
I
~--~~~~--~--+-~~-+--~--+-~
~--4----~-~-----~------+-------~
I
I
I
2184
LDARMY
L __________________~
The first flip-flop latches one of the two system bus signals
and the next four delay the array switching signal by four
PSEN cycles. The two inverters are there so that we trigger
off a ONE on the address. If the system bus was configured
as a 16 bit address/data bus (bit 4 of SCR set) then the
latched address lines would have to be used. Since it is
always desirable to have the flip-flops in a known state at
power up, some sort of reset circuitry should be used (e.g.,
by tying the power up reset circuit to the clear inputs on the
flip-flops), or both arrays should have identical reset sequences that include setting the flip-flops to a known state.
I
TLIDD/B430-3
use and the hardware to implement it, let's look at what is
actually happening (see Array Switching Timing Diagram 1).
The system bus line switches after the first cycle of the
MOVX instruction, but there is no PSEN during the second
cycle. Then there are two PSEN signals during the RET
instruction and two PSEN signals during the JMP instruction. Just after the second byte of the JMP is read into the
TMP, the arrays are switched, the PC gets loaded with the
new address, and the program continues execution as normal in the new array from the address indicated in the JMP
instruction. Be sure you understand the Array Switching
Timing Diagram 1 before continuing.
LOOKING IN DEPTH
Now that we have the basic software format we are going to
Array Switching Timing Diagram 1
ALE
I
I
I
;;r~
V'
MOYX
SI
ARRAYSWIlCH
TLIDD/B430-4
Note 1: No PSEN signal.
Note 2: Arrays switch here.
Note 3: Valid approximately 360 ns.
7-75
z
w
CD
CD
ADDENDUMS
Although it can be a problem when trying to execute a call across array boundaries, the problem can be easily overcome as
can the confusion that arises when many array switchings occur. All that one needs to do is to organize the program memory
efficiently. One such scheme would be to set aside a block of memory in each bank, such as the last page to use for memory
mapping. For example if we wanted to jump from location HOME in the LO array to location HERE in the HI array and then
back to HOME we could map our memory as shown below:
Hi Array
Lo Array
MAIN PROGRAM:
0500
HOME:
JMP
HERE
0680
0681
HERE:
NOP
JMP HOME
0700
0702
0703
0704
0705
0706
0707
SELLA: MOV
MOV
MOVL
MOVX
NOP
NOP
RET
ARRAY SWITCHING SUBROUTINE:
0700
0702
0703
0704
0705
0706
0707
SELHA: MOV
MOV
MOVL.
MOVX
NOP
NOP
RET
A.#080
HACC.A
RO.A
A.@RO
A.#040
HACC.A
RO.A
A.RO
MEMORY MAP:
::070A HOllE: CALL SELLA
070C
JMP HERE
(CALL SELHA)
-::: 070E
(JMP addr)
-0710
070A HERE: CALL SELHA::
070C
JIIP HOllE - 070E
(CALL SELHA) ;:(JIIP addr)
0710
TL/DD/8430-6
Note: The arrows show which JMP corresponds to which subroutine call. For example the JMP HOME at location 070C in the LO ARRAY corresponds to the
CALL at location 070A in the HI ARRAY. The ()'s show how the CALL's and JMP's can be strung together in a neat pattern.
Notice that there are two NOP's in the subroutine. Since the JMP after the CALL was moved to the new array the two NOP's
were added to the subroutine so that the actual array switching occurs just after the completion of the RET instruction. The
PC is then loaded with the new jump value, loaded in from the new array, and we continue execution as expected. Be sure to
understand the timing before going any further (see Array Switching Timing Diagram 2). The way the memory map is set up it
is easy to organize and keep track of jumps using the pattern indicated in the example. This method also eliminates any
problems with the assembler searching for undefined labels.
7·76
»
z
.
ADDENDUMS (Continued)
(,,)
Array Switching Timing Diagram 2
CD
CD
HI ARRAY
LOW ARRAY
'----v------'
MOVX
HOP
NOP
~
~
JMP HERE
NOP
I
I
CD_2-'1'<'--_________-t-!________________
SYSTEM BUS _ _ _ _ _ _
I
r;'(
ARRAY SWITtH
----------------------------~I
PROGRAM COUNTER
0704
MOCK
ADDRESS
~----------------
I
0705
0706
0707
MOCK
ADDRESS
070C
@
0680
(HERE:)
0700
TL/DD/B430-5
Note 1: Missing
PSEN signal.
Note 3: Arrays switch.
Note 2: System bus changes.
Note 4: Now in new array.
Since there are two extra NaP's in the switching array subroutine the hardware can now be simplified and the system speed
increased by removing two of the flip-flops from the chain. Through the use of the SEL MBx commands the memory map
can be located in any page of any memory bank. For example if we wanted to jump to location HERE in memory bank 2 of
the HI array from memory bank 1 of the La array (after having removed two flip-flops) we could map our memory as shown
below:
Lo Array
Hi Array
ARRAY SWITCHING SUBROUTINE:
0700
0702
0703
0704
0705
SELHA:
MOV
MOV
MOVL
MOVX
RET
A,#080
HACC,A
RO,A
A,@RO
0700
0702
0703
0704
0705
HERE:
CALL
SELHA
070A
070C
070E
SELLA:
MOV
MOV
MOVL
MOVX
RET
A,#040
HACC,A
RO,A
A,@RO
SEL
JMP
MB2
HERE
MEMORY MAP:
070A
070C
070E
MAIN PROGRAM:
0800
0801
HOME:
SEL
JMP
MBO
HERE
1000
HERE:
NOP
If a call into the other array is necessary a similar pattern to that above could be used. Start by replacing the JMP's with
CALL's to the desired subroutine and appropriately placing returns. For example (here it comes) if we wanted to CALL
HOME from HERE we could memory map as shown below.
7-77
.
~
~
C")
r---------------------------------------------------------------------~
Lo Array
z
c:c
Hi Array
MAIN PROGRAM:
HOME:
NOP
RET
HERE:
NOP
CALL HOME
ARRAY SWITCHING SUBROUTINE:
SELHA:
SELLA:
RET
RET
MEMORY MAP:
""-_---------HOME: CALL SELLA
CALL HOME +=
CALL SELHA _ _ _ _ _ _ _ _ _ _ _ _......
-+RET
TLIDD/B430-7
~i~ce calling between different memory banks is not straight forward it is advisable to be very careful when doing it, or to
limit calls between arrays only to those that reside in the same memory bank.
HELPFUL HINTS
5) If extra memory is needed, but a good deal of the program memory is data storage, the data could be stored in
the video memory space instead of implementing a new
array.
These schemes can all be modified to multiple arrays and
easier or fancier mappings, however there are a few things
to keep in mind.
1) If using a system bus address line to toggle the array,
don't use that line as part of an actual display memory
address.
2) The MOVX instruction can require more than two cycles
depending on system bus contention, however we are
only concerned with the last two cycles and the P8EN
signals that occur after the system bus line changes.
3) If using interrupts-disable them while switching arrays
and keep all time critical routines in the same array.
4) A demux or decoder can be used to select memory arrays or decode address lines when more than two 8k
arrays are implemented or more than 16k of video RAM
is being used.
6) If the TMP is going to be used in a noisy environment or
the system bus is configured as a 16 bit bidirectional bus
a synchronous latch should be used to assure stable levels on 8814 and 8815.
7) The given array switching circuit can be implemented
with the demo board by wiring it into an extension board
that can be plugged into the prom socket U9. Wire the
two new proms in parallel with each other and with a
cable that can plug directly into the prom socket. However, instead of using pin 20 from the demo board, use the
two array enable lines as the chip enables for the 2764
proms.
7-78
Also use 8812 and 8813 instead of 8814 and 8815.
Section 8
Microcontroller
Development Support
Section 8 Contents
Mole..............................................................................
AN-456 Microcontroller Development Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPC Software Support Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8·2
8-3
8-4
8-17
c
CD
<
~National
CD
0'
~ Semiconductor
"C
3
CD
::s
Development Support
( J)
C
"C
"C
o
::l.
Our job doesn't end when you buy a National microcontroller, it only begins.
Once you've got debugged code, you can transmit it directly
to National, where we'll use it to create the tooling necessary for manufacturing the appropriate masks for your microcontroller.
The next step is to help you put that microcontroller to
work-delivering real-world performance in a real-world application.
DIAL-A-HELPER ON-LINE APPLICATIONS SUPPORT
That's why we offer you such a comprehensive, powerful,
easy-to-use package of development tools.
Dial-A-Helper lets you communicate directly with the Microcontroller Applications Engineers at National.
MICROCONTROLLER ON-LINE EMULATOR
Using standard computer communications software, you
can dial into the automated Dial-A-Helper Information System 24 hours a day.
Our Microcontroller On-Line Emulator (MOLETM) is a complete, inexpensive system designed to support both hardware and software development of all NSC microcontrollers.
Using standard computer platforms (IBM PC, VAX, and others), the MOLE system gives you the tools to write, assemble, debug, and emulate software for your target microcontroller, whether it belongs to the COP400 4-bit family, the
COP800 8-bit family, or the HPC 16-bit family.
You can leave messages on the electronic bulletin board for
the Applications Engineers, then retrieve their responses.
You can select and then download specific applications
data.
And you can even arrange for the Applications Engineering
Group to take over direct control of your MOLE system for
particularly tough debug problems.
The MOLE system itself consists of two circuit boards that
interface to each other and to the host computer using a
MOLE software package.
DIAL-A-HELPER
One board is called the Brain Board and is common to all
MOLE systems. It provides the major functional features of
the system, linking the various elements, including other
Brain Boards for a multi-workstation system tied to a single
host.
Voice:
(408) 721-5582 (8 a.m.-5 p.m. PST)
Modem:
Setup:
(408) 739-1162 (24 Hrs.lday)
Baud rate 300 bps or 1200 bps 8 bits, no parity,
1 stop
DEDICATED APPLICATIONS ENGINEERS
The other board is called the Personality Board and is different for each microcontroller family. It provides the unique
emulation functions for the system.
Your own computer CPU provides a powerful, cost-effective
base for bulk storage of object code, disk editing and assembly, and for high-speed processing.
We've assembled a dedicated team of highly trained, highly
experienced engineering profeSSionals to help you implement your solution quickly, effectively, efficiently and to ensure that it's the best solution for your specific application.
At National, we believe that the best technology is also the
most usable technology. That's why our microcontrollers
provide such practical solutions to such real design problems. And that's why our microcontroller development support includes such comprehensive tools and such powerful
engineering resources.
No one makes more microcontrollers than National and no
one does more to help you put those microcontrollers to
work.
USing resident firmware in the Monitor section of each Personality Board, you can download results from your host
computer, you can display and alter code in both hex and
mnemonic format, you can set Breakpoints and Traces, you
can execute Time measurements, and you can examine and
modify internal registers and 1/0.
•
8-3
Microcontroller
Development Support
National Semiconductor
Application Note 456
Microcontroller Marketing
TL/DD/8830-14
MOLETM DEVELOPMENT TOOLS
Development system flexibility is provided by the Personality board. This component tailors the system to emulate a
single microcontroller family or device. For instance, one
Personality Board supports the COP400 CMOS and NMOS
family. This Personality Board provides emulation capability
for 42 Microcontroller device types.
Personality boards are also available for the HPC and COPS
family of M2CMOS products.
The MOLE (Microcontroller On Line Emulator) system is designed to support the development of NSC Microcontroller
products. These include COPSTM family, and the HPCTM
family of products. The MOLE provides effective support for
the development of both software and hardware in Microcontroller-based applications.
The purpose of the MOLE is to provide the tools required to
write and assemble code for the target microcontroller and
assist in the debugging of both the hardware and software.
The host CPU contributes cost effective bulk storage and
high speed processing. Disk editing and assembly operations are controlled by the host CPU. The results are down
loaded to the Brain Board over the RS-232 link.
Once the application program has been completely debugged, the code may be submitted to National Semiconductor for use in creating the tooling necessary for manufacturing the masked Microcontroller device.
A MOLE system consists of three components: a MOLE
Brain Board, a MOLE Personality Board, and software for a
host computer. The host may be an IBM®-PC, or one of a
number of inexpensive PC compatibles. The cross-assemblers and cross-compilers provided by National Semiconductor will run under control of the host computer MS-DOS
operating system.
The Brain Board provides the MOLE system with the capability of communicating with the user's Host CPU. Resident
firmware on the Brain Board allows the user to download
assembled load modules over the RS-232 link from the host
computer, display and alter code in both hex and mnemonic
format, initiate Breakpoints, Traces, and timing on addresses and external events, examine and modify the internal
resources of the Microcontroller being emulated. The Brain
Board also provides all the hardware and firmware to program standard EPROMs up to 27256's (32k x 8).
The MOLE concept provides the user with a powerful development system based around a familiar host. The Brain
Board/Personality Board/Host combination provides FULL
emulation capability. This modular design provides maximum flexibility and maximum utility for the development of
Microcontroller based systems.
8-4
MOLE
PERSONALITY
I
TlIDD/8830-3
MOLE System Block Diagram
--------------------------------------------.
I'L......-...--.."r=::t--...--~: {O
EXTERNAL
EVENTS
TO
APPLICATION
DC
Power
Source
Printer
Modem
Host CPU
TlIDD/8830-2
8-5
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MOLE BRAIN BOARD
MOLE PERSONALITY BOARDS
MOLE DEBUG FEATURES
The Personality Board lends personality to the MOLE system. The Monitor debugger firmware that is resident on the
Personality Board is customized for the microcontroller that
the Personality Board is designed to emulate, thereby giving
the MOLE "personality". The Monitor firmware allows the
user to display the application program in either hex or mnemonic format. The user can alter or deposit hex data into
the program memory. A one-line assembler is also available
to allow the user to put new instructions into the application
program. Breakpoint, Singlestep, Trace or Time functions
are available. They allow triggering on addresses or external
events. The Monitor also provides the ability to examine and
modify the internal RAM and registers of the Microcontroller
being emulated.
The standard set of MOLE functions common to all MOLE
Personality Boards is as follows.
TABLE I. Common MOLE Monitor Commands
Alter
AUtoprint
Breakpoint
Clear
Deposit
Dlagonstic
Find
Go
Help
List
Modify
Next
Put
Reset
RGo
SEarch
Singlestep
STatus
Time
TRace
Type
Unassemble
Each Personality Board has its own Monitor; however, each
Monitor implements a standard set of MOLE functions. This
gives all MOLE systems a common set of functions with
identical syntax. This commonality is designed to help provide a clear and simple migration path from the low-cost
COP400 4-bit microcontrollers to the high performance HPC
16-bit microcontrollers without the need to relearn the development tool.
Alter consecutive bytes in shared memory
Specify information to be printed on Breakpoint
Set trigger point(s) for Breakpoint
Clear Breakpoint, Time and Trace functions
Deposit byte value into range of shared memory
On·board test routine for system checkout
Find data or string in shared memory
Start program execution or enable function
On-screen Help menu
List data in shared memory
Modify on-chip RAM or Registers during Breakpt
Singlestep through subroutine
One-line assembler
Reset chip
Reset chip and execute Go automatically
Search Trace memory for data or address
Execute one instruction, then Breakpoint
Show chip and MOLE Status
Time program execution or external events
Specify triggers for capturing Trace data
Type Trace data or on-Chip data during Breakpt
Disassembler for Trace or shared memory
These commands are implemented on the HPC, COP800
and COP400 MOLEs.
Additionally, each Personality board has its own special
Monitor functions that give that system additional capabilities.
8-7
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MOLE COP400 FAMILY PERSONALITY BOARD
COPS Personality Board
TL/DD/8830-6
GENERAL DESCRIPTION
Common MOLE Monitor Commands
The MOLE COPS Family Personality Board supports the
emulation of COP400 family of Microcontrollers. The Personality Board allows the user to emulate the appropriate
Microcontroller in the user's end system for fast development of application code and hardware. The Personality
Board consists of: a Monitor, the hardware to control the
operation of the Microcontroller in the emulation system,
and an emulation cable to connect the emulator to the application system. The cable has the same pin configuration as
the final masked part.
Alter
AUtoprint
Breakpoint
Clear
Deposit
Diagnostic
Find
Go
Help
List
Modify
Next
Put
Reset
RGo
SEarch
Singlestep
STatus
Time
TRace
Type
Unassemble
The Personality Board Monitor is contained in firmware
ROM, contains an assembler and disassembler and is directly executable by the NSC800 on the Brain Board. The
Monitor commands will allow the user to execute the application code, examine and modify internal registers and 1/0,
examine and alter object code in hex or mnemonic format,
execute Time measurements, and set Trace and Breakpoints.
The Personality Board also contains 2k bytes of shared
memory (RAM) for application code and the necessary
hardware for Trace and Breakpoint operation.
Alter consecutive bytes in shared memory
Specify information to be printed on BreakpOint
Set trigger point(s) for Breakpoint
Clear Breakpoint, Time and Trace functions
Deposit byte value into range of shared memory
On-board test routine for system checkout
Find data or string in shared memory
Start program execution or enable function
On-screen Help menu
List data in shared memory
Modify on-Chip RAM or Registers during Breakpt
Singlestep through subroutine
One-line assembler
Reset chip
Reset chip and execute Go automatically
Search Trace memory for data or address
Execute one instruction, then Breakpoint
Show chip and MOLE Status
Time program execution or external events
Specify triggers for capturing Trace date
Type Trace data or on-chip data during Breakpt
Disassembler for Trace or shared memory
FEATURES
COP400 Monitor Special Functions
• Supports entire COPS CMOS and NMOS family
• Single 5V operation
• Firmware monitor directly executed by Brain CPU
Chip
Option
Set
• Firmware diagnostics directly executed by Brain CPU
Specify COP device to emulate
Specify COP chip options being emulated
Set special emulation options
• Firmware Line Assembler and Unassembler
• 2k bytes of shared memory
• 256 deep trace memory
PHYSICAL SIZE
12" x 12"
• Eight external event inputs
• Trace on multiple addresses, address ranges, or external
events
POWER REQUIREMENTS
+5V @ 3.5A
ORDER PIN:
MOLE-COPS-PB1
• Breakpoint on multiple addresses, address ranges or external events
MOLE-COPS-PB1 PACKAGE CONTAINS
MOLE CMOS COPS Personality Board
MOLE CMOS COPS PB Manual
3 Emulator Cables
Power Cable
Miscellaneous Hardware
• List and alter shared memory
• Print and modify internal registers
• Singlestep
• Next-singlestep around subroutine calls
• Trigger output for logic analyzer
SOFTWARE ORDERED SEPARATELY
See How To Order
• Real time emulation
8-8
MOLE COP800 FAMILY PERSONALITY BOARD
COP800 Personality Board
TLlDD/6630-16
GENERAL DESCRIPTON
Common MOLE Monitor Commands
The COP8DO Family Personality Board allows the MOLE
system to emulate the COP80a family. The Personality
Board consists of a firmware Monitor, 16k bytes of shared
memory, 2000 deep Trace memory, Port recreation logic to
recapture the pins used for emulation, emulation hardware,
and an In System Emulator (ISE) cable. The ISE cable has
the same pinout as a socketed masked part and allows the
Personality Board to function within the application system.
Alter
AUtoprint
Breakpoint
Clear
Deposit
Diagnostic
Find
Go
Help
List
Modify
Next
Put
Reset
RGo
SEarch
Singlestep
STatus
Time
TRace
Type
Unassemble
The NSC800 CMOS Microprocessor, located on the Brain
Board, directly executes the Personality Board Monitor firmware. The Monitor allows execution of application code, examination and alteration of internal registers, examination
and alteration of shared memory, and the setting of trace
and breakpoints. The ISE cable connects these capabilities
to the application system. Up to eight external events as
well as 15-bit address and 8-bit data busses can be traced
in the 2000 deep trace memory. Multiple breakpoints, plus
assemble and unassemble commands are at the user's disposal.
Application programs of up to 32k bytes from Personality
Board RAM may be emulated.
Alter consecutive bytes in shared memory
Specify information to be printed on Breakpoint
Set trigger point(s) for Breakpoint
Clear Breakpoint, Time and Trace functions
Deposit byte value into range of shared memory
On-board test routine for system checkout
Find data or string in shared memory
Start program execution or enable function
On-screen Help menu
List data in shared memory
Modify on-chip RAM or Registers during Breakpt
Singlestep through subroutine
One-line assembler
Reset chip
Reset chip and execute Go automatically
Search Trace memory for data or address
Execute one instruction, then Breakpoint
Show chip and MOLE Status
Time program execution or external events
Specify triggers for capturing Trace date
Type Trace data or on-Chip data during Breakpt
Diassembler for Trace or shared memory
FEATURES
COP8 Monitor Special Functions
• Supports COP800 microcontroller family
• Single 5V operation
CYcles
Capture COP8 execution cycles Trace memory
End
Exit Monitor and return to Brain Exec
Specify address ranges to exclude from Trace
EXclusion
istUnassemble List shared memory in mnemonic form
TypeUnassemble Type Trace memory in mnemonic form
• Firmware monitor directly executed by Brain CPU
• Firmware diagnostics directly executed by Brain CPU
• Firmware Line Assembler and Unassembler
• 32k bytes of shared program memory
• 2000 deep trace memory
• Eight external event inputs
PHYSICAL SIZE
12" x 12"
• Trace on multiple addresses, address ranges or external
events
POWER REQUIREMENTS
+5V @ 3.5A
• Breakpoint on multiple addresses, address ranges or external events
ORDER PIN:
MOLE-COP8-PB 1
MOLE·COP8·PB2
• List and alter shared memory
COP820/840
COP888
MOLE-COP8-PB1/2 PACKAGE CONTAINS
MOLE CMOS COP8 Personality Board
MOLE CMOS COP8 PB Manual
Emulator Cables
Power Cable
Miscellaneous Hardware
• Print and modify internal registers
• Singlestep
• Next-singlestep around subroutine calls
• Trigger output for logic analyzer
• Real time emulation
SOFTWARE ORDERED SEPARATELY
See How To Order
8-9
MOLE HPC FAMILY PERSONALITY BOARD
HPC Personality Board
TL/DD/8830-10
GENERAL DESCRIPTION
• Trace on multiple addresses, address ranges or external
events
The HPC Family Personality Board allows the MOLE system
to emulate the High Performance Controller (HPC) family.
The Personality Board consists of a firmware Monitor, 16k
bytes of shared memory, 2k x 48 Trace memory, Port recreation logic to recapture the pins used for emulation, emulation hardware, and an In System Emulator, ISE, cable. The
ISE cable has the same pinout as a socketed masked part
and allows the Personality Board to function within the application system.
• Breakpoint on multiple addresses, address ranges or external events
• List and alter shared memory
• List and alter display memory
• Print and modify internal registers
• Singlestep
• Next-singlestep around subroutine calls
The NSC800 CMOS Microprocessor, located on the Brain
Board, directly executes the of Personality Board Monitor
firmware. The Monitor allows execution of application code,
examination and alteration of internal registers, examination
and alteration of shared memory, and the setting of trace
and breakpoints in either shared or user memory. The ISE
cable connects these capabilities to the application system.
Up to eight external events as well as 16-bit address and
16-bit data busses can be traced in the 2k deep trace memory. Multiple breakpoints, and chip error conditions plus assemble and unassemble commands are at the user's disposal.
• Trigger output for logic analyzer
• Real time emulation
Common MOLE Monitor Commands
Alter
AUtoprint
Breakpoint
Clear
Deposit
Diagnostic
Find
Go
Help
List
Modify
Next
Put
Reset
RGo
SEarch
Singlestep
STatus
Time
TRace
Type
Unassemble
Applications programs of up to 16k bytes from Personality
Board RAM or 64k bytes from user system RAM may be
emulated.
FEATURES
• Supports HPC microcontroller family
• Single 5V operation
• Firmware monitor directly executed by Brain CPU
• Firmware diagnostics directly executed by Brain CPU
• Firmware Line Assembler and Unassembler
• 16k bytes of shared program memory
• 2000 deep trace memory
• Eight external event inputs
8-10
Alter consecutive bytes in shared memory
Specify information to be printed on Breakpoint
Set trigger point(s) for Breakpoint
Clear Breakpoint, Time and Trace functions
Deposit byte value into range of shared memory
On-board test routine for system checkout
Find data or string in shared memory
Start program execution or enable function
On-screen Help menu
List data In shared memory
Modify on-chip RAM or Registers during Breakpt
Singlestep through subroutine
One-line assembler
Reset chip
Reset chip and execute Go automatically
Search Trace memory for data or address
Execute one instruction, then Breakpoint
Show chip and MOLE Status
Time program execution or external events
Specify triggers for capturing Trace date
Type Trace data or on-chip data during Breakpt
Disassembler for Trace or shared memory
HPC Monitor Special Functions
AlterWord
BAnk
CHip
DepositWord
End
ERror
EXclusion
FindWord
ListWord
MAp
XMove
PHYSICAL SIZE
12" x 12"
Alter consecutive words in shared memory
Specify bank trigger information
Select chip and specify system memory map
Deposit word value in range of shared memory
Exit Monitor and return to Brain Exec
Enable/disable HPC access error checking
Specify address ranges to exclude from Trace
Find word values in shared memory
List shared memory or memory range as words
Specify address range of memory on-board MOLE
Move data from one address range to another
POWER REQUIREMENTS
+5V @ SA
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ORDER PIN:
MOLE-HPC-PB1
MOLE-HPC-PB1 PACKAGE CONTAINS
MOLE HPC Personality Board
MOLE HPC PB User's Manual
1 Emulator Cable
Power Cable
Miscellaneous Hardware
SOFTWARE ORDERED SEPARATELY
See How To Order
•
8-11
I
HPC DESIGNER'S KITS
HPC Designers Kits
TLIDD/8830-20
HPC Development Board Monitor
GENERAL DESCRIPTION
The HPC Designer Kits are a 16-bit microcontroller Development System for program development and real-time emulation. An on-board HPC microcontroller executes monitor
firmware and also acts as the target processor.
Alter
AUtoprint
BAud
BYpass
Breakpoint
Clear
Deposit
When used as the target processor, all of the features of the
HPC are available for use in the application. All operating
modes of the HPC are supported, with up to 64k bytes of
addressable memory available for application programs.
This kit contains all of the components, manuals, and software to design an HPC system. Just add an IBM or compatible PC, + 5V DC 1.5-Amp power supply and RS232 cables.
Dlagonstic
Go
Help
Two kits are offered. The evaluation package contains evaluation software that allows up to 1000 lines of code to be
assembled and linked. The development package has a
complete Assembler/Linker/Librarian with no code limitations.
List
ListUnassemble
LOad
FEATURES
Modify
• Supports HPC microcontroller family
• Single 5V operation
ModifyByte
ModifyWord
Put
Restart
• Firmware monitor directly executed by the HPC
• Firmware diagnostics directly executed by the HPC
• Firmware Line Assembler and Unassembler
• 64k bytes of addressable program memory
• Breakpoint on multiple addresses
Singlestep
Type
Unassemble
• List and alter memory
• Print and modify internal registers
• Singlestep
• Real time emulation
• Evaluation module that allows up to 1000 lines of code to
be developed for evaluation purposes
8-12
Alter consecutive bytes in shared memory
Specify information to be printed on
Breakpoint
Set or display the host or terminal Baud rate
Connect terminal port to host port
Set trigger point(s) for Breakpoint
Clear Breakpoint function
Deposit byte value into range of shared
memory
On-board test routine for system checkout
Start program execution
On-screen Help menu
List data in shared memory
List shared memory in mnemonic form
Load hex object file from terminal or host
port
Modify on-Chip RAM or Registers during
Breakpt
Modify on-chip RAM or registers as bytes
Modify on-chip RAM or registers as words
One-line assembler
Restart HPC chip, same as Reset on the
MOLE
Execute one instruction, then Breakpoint
Type on-chip data during Breakpoint
Disassembler for shared memory
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PHYSICAL SIZE
12H x 12H
U1
en
POWER REQUIREMENTS
+5V
@
1.5A
ORDER PIN:
HPC-MOLE-EVALO (Evaluation Package)
HPC-MOLE-DEVLO (Development Package)
MOLE·HPC·EVALO PACKAGE CONTAINS
HPC Evaluation Board
ISE Cable w/connector for PGA socket
Development Board Communications Software
(MS·DOS)
HPC Assembler/Linker/Evaluation Software
C Compiler Evaluation Module Software
HPC46083/46043/46003 User's Manual
HPC46083/46043/46003 Datasheet
Dial·A·Helper User's Manual
MOLE·HPC·DEVLO PACKAGE CONTAINS
HPC Evaluation Board
ISE Cable w/connector for PGA socket
Development Board Communications Software
(MS·DOS)
HPC FULL Assembler/Linker/Librarian Software
C Compiler Evaluation Module Software
HPC46083/46043/46003 User's Manual
HPC46083/46043/46003 Datasheet
Dial·A·Helper User's Manual
8·13
.
CD
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MOLE SYSTEMS
Included, along with the cross assembler, in the software
package are two file conversion routines to convert the assembler output (LM) to HEX and to convert HEX to LM. Also
included in the software package is a COMM program which
facilitates the downloading and uploading between the host
and the MOLE, and adds the capability to make the host act
as a terminal.
HOW TO ORDER MOLE SYSTEMS
MOLE systems are available for a variety of microcontrollers. To order a complete development package, select the
section for the microcontroller to be developed and order
the parts listed.
Development Tools Selection Table
Microcontroller
Order
Part Number
Description
Brain Board
Brain Board Users Manual
420408188-001
MOLE-HPC-PB1
Personality Board
HPC Personality Board
Users Manual
420410477-001
MOLE-HPC-IBMR
Relocatable Assembler
Software for IBM
HPC Software Users Manual
and Software Disk
PC-DOS Communications
Software Users Manual
C Compiler for IBM
HPC C Compiler Users Manual
and Software Disk
Assembler Software for IBM
MOLE-HPC-IBM
MOLE-HPC-IBM-CR
COP400
424410836-001
420040416-001
424410883-001
424410897 -001
Users Manual
MOLE-BRAIN
Brain Board
Brain Board Users Manual
420408188-001
MOLE-COP8-PB 1
Personality Board
COP820/840 Personality Board
Users Manual
420410806-001
MOLE-COP8-IBM
Assembler Software for IBM
COP800 Software Users Manual
and Software Disk
PC-DOS Communications
Software Users Manual
420410703-001
COP888
Manual
Number
MOLE-BRAIN
HPC
COP820/840
Includes
424410897 -001
424410527 -001
420040416-001
420410703-001
Users Manual
MOLE-BRAIN
Brain Board
Brain Board Users Manual
420408188-001
MOLE-COP8-PB2
Personality Board
COP888 Personality Board
Users Manual
420420084-001
MOLE-COP8-IBM
Assembler Software for IBM
COP800 Software Users Manual
and Software Disk
PC-DOS
Communications Software
Users Manual
42441 0527 -001
420040416-001
MOLE-BRAIN
Brain Board
Brain Board Users Manual
420408188-001
MOLE-COPS-PB 1
Personality Board
COP400 Personality Board
Users Manual
420408189-001
MOLE-COPS-IBM
Assembler Software for IBM
COP400 Software Users Manual
and Software Disk
PC-DOS
Communications Software
Users Manual
424410284-001
Users Manual
424409479-002
420040416-001
424410284-001
8-14
DESIGNER KITS
HOW TO ORDER DESIGNER KITS
Designer Kits are self contained development systems that
contain all of the components, manuals and software to design a microcontroller based system. Just add an IBM-PC or
compatible PC, + 5V DC 1.5 Amps power supply and
RS232 cables.
Microcontroller
Order
Part Number
Two types of kits are offered. The Evaluation package contains evaluation software that allows limited code to be developed. The Development package has no restrictions on
the assembler software.
Description
Includes
Manual
Number
MOLE-HPC-EVALO
HPC Designer's Kit
Evaluation Version
HPC-DB1 Board
Evaluation Compiler,
Assembler / Linker,
Manuals
420410901-1
MOLE-HPC-DEVLO
HPC Designer's Kit
Development Version
HPC-DB1 Board
Evaluation Compiler,
FULL Assembler/Linker,
Manuals
420410901-1
HPC
8-15
DEVELOPMENT SYSTEM ACCESSORIES AND REPLACEMENT PARTS
Part Type
Order Part
Number
I
Description
I
MOLE EMULATOR CABLES
68-Pin PGA Cable
MOLE-CBL-68PGA
Cable used for in-system emulation of the HPC in a 68 PGA package.
For the HPC MOLE.
68-Pin PLCC Cable
MOLE-CBL-68PCC
Cable used for in-system emulation of the HPC in a 68 PLCC
package. For the HPC MOLE.
44-Pin PLCC Cable
MOLE-CBL-44PCC
Cable used for in-system emulation of the COP8 in a 44 PLCC
package. For the COP888 MOLE.
28-Pin PLCC Cable
MOLE-CBL-28PCC
Cable used for in-system emulation of the COP8 in a 28 PLCC
package. For the COP8 MOLE.
40-Pin DIP Cable
MOLE-CBL-40DIP
Cable used for in-system emulation of the COP8 in 40-pin DIP
packages. For the COP8 MOLE.
28-Pin DIP Cable
MOLE-CBL-28DIP
Cable used for in-system emulation of COP4 and COP8 devices in
the 28-pin DIP package. For use with the COP4 and COPS MOLEs.
24-Pin DIP Cable
MOLE-CBL-24DIP
Cable used for in-system emulation of COP4 and COPS devices in
the 24-pin DIP package. For use with the COP4 and COPS MOLEs.
20-Pin DIP Cable
MOLE-CBL-20DIP
Cable used for in-system emulation of COP4 and COPS devices in
the 20-pin DIP package. For use with the COP4 and COPS MOLEs.
COP444 PIG
COP444CP
A piggy-back emulator product designed to provide programmable
form, fit and function emulation for the COP4XXC products in a 2Slead DIP package. An Sk x S EPROM sits piggy-back in a socket on
top of a hybrid packaged 2S-lead COP404C controller.
COPS20/S40 PIG
COPS20CP-X
COPS40CP-X
A piggy-back emulator product designed to provide programmable
form, fit and function emulation for the COPS20 and COPS40
products in a 2S-lead DIP package. An Sk x S EPROM sits piggy-back
in a socket on top of a hybrid packaged 2S-lead COPS20/S40
controller. X is the clock option (from datasheet).
COPS720 Programmer
MOLE-COPS-PROG
Adapter board for use in programming the COPS720, S721 or S722
devices on the MOLE-Brain board.
COPSSS PIG
TBD
A piggy-back emulator product designed to provide programmable
form, fit and function emulation for the COP8SS family.
HPC PCB Emulator
HPC16083MH
A form, fit and function programmable emulator for the 6S-lead PLCC
HPC160S3 device used in single-chip mode. Programmed with an
adapter board on the MOLE-Brain.
HPC160S3MH Programmer
MOLE-HPC-PROG
Adapter board for programming the HPC160S3MH.
MOLE-Brain
MOLE-BRAIN
Main board component of the MOLE Development System.
MOLE Enclosure
TBD
Kit for complete enclosure of the HPC and COPS MOLE systems.
Includes box, power supply and all cabling required to upgrade
existing MOLE Systems.
SUPPORT PRODUCTS
SYSTEM HARDWARE
MOLE SOFTWARE SUPPORT FOR THE IBM-PC
HPC Assembler
MOLE-HPC-IBMR
Relocating ASMHPC Asembler/Linker/Librarian.
HPC C Compiler
MOLE-HPC-IBM-CR
CCHPC C Compiler. Includes the HPC Assembler.
HPC Evaluation Software
MOLE-HPC-IBMEVL
HPC Evaluation software. Includes: ASMHPC and CCHPC evaluation
modules and manuals.
COPS Assembler
MOLE-COPS-IBM
COPSOO Assembler.
COP4 Assembler
MOLE-COPS-IBM
COP400 Assembler.
Dial-A-Helper
MOLE-DIAL-A-HLP
Dial-A-Helper manual and communications software.
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TL/DD/9727-1
• Choice of host systems
-IBM® XT/AT PC-DOS
- VAXTM VMSTM
-VAX UNIX®
• CCHPC C Compiler
- ANSI Draft Standard C (February 1986)
- Additional storage class modifiers
supported
- Additional statement types included
- Supports embedded assembly code
- Supports multiple source files
• ASM HPC Assembler
- Macro and conditional assembly
- Instruction size optimization
- Symbol table and cross reference
output
- Object files are linkable and
relocatable
•
LNHPC Linker
- Links multiple relocatable object
modules
- Selects required modules from library
files
• LIBHPC Librarian
- Supports user developed library
modules
• DBHPC Source Debugger
- High level software debugging
- Real-Time Hardware Emulation
- Source file listing
- Variable set and view
- Set break points at C source level
- Display dynamic function nesting
- Display debugger status
- Call operating system commands
General Description
The HPC software support packages provide development system support for the HPC family of 16-bit single chip microcontrollers. Two software packages are
offered that support the HPC: HPC Assembler/Linker/
Librarian and HPC C Compiler. 80th packages are
available for a choice of host systems: IBM XT/AT
PC DOS, VAX VMS and VAX UNIX.
The assembler produces relocatable object modules
from the HPC macro assembly language instructions.
The object modules are then linked and located to
absolute memory locations. The absolute object module may be downloaded to the HPC MOLETM (Microcontroller Online Emulator) development system for
debugging.
The C compiler generates assembly source. The C
Compiler may optionally pass symbolic information
through the assembler and linker to the absolute object module. The source debugger then uses this information for C and Assembly language debugging on
the host in conjunction with the MOLE.
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HPC C Compiler-CCHPC Introduction
The HPC C Compiler (CCHPC) is a full and complete
implementation of ANSI Draft Standard C (Feb 1986)
for freestanding environment. Certain additions are included to take advantage of special features of the
HPC (for the specific needs of microcontrollers). The
Enhancements include the support of two non-standard statement types (loop and switchf), non-standard
storage class modifiers and the ability to include assembly code in-line. The compiler supports enumerated types of structures by value, functions returning
structures, function prototyping and argument checking.
Symbol Names, both internal and external, are 32
characters. Numerics are 16-bit for short or Int, 32-bit
for long, and 8-bit for char, all as either signed or
unsigned; floating point is offered as float of double,
both using IEEE format.
All data types, storage classes and modifiers are supported. Additional storage class modifiers are provided:
BASEPAGE place static variable in faster and more
efficient on-chip basepage memory.
NOLOCAL declare function without local variables,
thus no stack frame.
INTERRUPTn declare function to execute in response to specific interrupt(s).
ACTIVE declare function to be accessed via faster
and more efficient function call mechanism.
All statement types are supported, and two additions
are provided:
loop (count) simpler, more efficient for looping command.
switchf (value) faster form of switch command without constraint checking.
CCHPC SPECIFICATIONS
Note: Enhancements are boldface.
32 letters, 2 cases
Name length
Numbers
Integer, Signed and Unsigned
16-32 bits
16 bits and 32 bits
Short and Long
32 bits and 32 bits
Floating, Single and Double
Preprocessor
#include
#define #defineO #undef
#if #ifdef #ifndef #if defined #else #elif #endif
Declarations
auto register const volatile BASEPAGE
static static global static function NOLOCAL INTERRUPTn ACTIVE
extern extern global extern function
char short int long signed unsigned float double void
struct union bit field enum
pointer to array of function returning
type cast typedef initialization
Statements
; { ... I expression; assignment; structure assignments;
while 0 ... ; do ... while 0; for(;;;) ... ; loop () ••• ;
if 0 ... else ... ; switch 0 ... ; case: ... ; default: ... ; swltchf () ••• ;
return; break; continue; goto ... ; ... .
Operators
primary:
functionO array[] strucLunion. strucLpointer->
unary:
'" & + - ! + + -- sizeof (typecast)
arithmetic:
'" / % + - < < > >
< > <= > =
!=
relational:
boolean:
& A I && II
assignment:
+=
"'= /= %= »= «= &= A=
misc.:
?: ,
Functions
arguments:
Numbers, Pointers, Structures
return values:
Numbers, Pointers, Structures
forward reference (argument checking)
Library Definition
Limited-Freestanding environment
Embedded Assembly Code
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"C
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All operators are supported, and anachronisms have
been eliminated (as per the standard). Structure assignment, structure arguments, and structure functions are also supported. Forward reference functions
and argument type checking is supported.
Assembly code may be embedded within C programs
between special delimiters.
Undefining symbol names-Similarly, this switch
passes a string argument to the C preprocessor. It
removes any previous definitions.
Permit old-fashioned constructs-Certain anachronisms from Kernighan and Ritchie C that are not permitted in ANSI C will be accepted by the compiler if
this option is specified. This option is a convenience
for users porting a C program to CCHPC from a Kernighan and Ritchie compiler.
Set chip revision level-This switch is used to generate code to work around bugs in specified chip revisions.
Generate symbolic debug information-This option
causes the compiler to create symbolic debug information which is passed to the output assembly file.
COMPILER COMMAND FEATURES
The CCHPC runs under different host operating systems. Depending on the host system and the CCHPC
command line options, ordering of the elements and
their syntax may vary. In all cases, the command line
consists of the command name, options or switches,
and the filename to be compiled.
The compiler output, in the form of ASMHPC assembler source statements, is put in a file with the extension ".asm".
The following is a description of the CCHPC options or
switches:
Include C code in assembler code output-Assembler output file contains the C source code lines as
comments.
Invoke C preprocessor before compilation-Allows the C preprocessor invocation to be skipped.
Invoke an alternative C preprocessor before compilation-Allows an alternative preprocessor to be
used.
Setting the stack size-This switch takes a numeric
argument in the form of a C constant. If the module
being compiled contains the function main, the compiler uses the number as the size of the program's
execution stack, in words. The option is ignored if the
module does not contain main.
Creating 8-bit wide code-This switch creates code
that can be executed from a-bit wide memory by
avoiding the use of instructions that fetch 16-bit operands (such as JIDW). This option DOES NOT allow
the use of 16-bit values or data in a-bit memory.
Placing string literals in ROM-The ANSI draft language standard calls for string literals, and individual
copies for each usage of the literal to be stored in
RAM. This switch allows CCHPC to override this requirement for efficiency, saving startup time, RAM and
ROM space. Turn off compiler warning messages.
Indicating directories for include files-This switch
takes a string argument which is passed to the C preprocessor. The C preprocessor uses it as a directory
to search for include files.
Defining symbol names-This switch passes the
string argument to the C preprocessor. It instructs the
preprocessor to perform the same function as the
#define, allowing the symbol definitions to be moved
to the invocation line.
BASIC DEFINITIONS
Names may be arbitrarily long, but only the first 32
characters are significant. Case distinctions are respected.
Constants may be of type decimal, octal, hex, character and string.
Escape sequences for new line, horizontal and vertical tab, backspace, carriage return, form feed, alert,
backslash, single quote, double quote, octal and hexidecimal numbers are supported.
Comments imbedded in the source code begin with
"/*" and end with "*/". Comments can not be nested.
CCHPC supports the following Data types:
Name
Size in Bits
char
short
int
enum
long
signed char
signed short
signed int
signed long
unsigned char
unsigned short
unsigned int
unsigned long
float
double
long double
struct
union
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32
a
16
16
32
a
16
16
32
32
32
32
sum of component sizes
maximum of component sizes
The type "char" is treated as signed. Unsigned operations are treated the same as signed operation, except for multiplication, division, remainder, right shifts
and comparisons. For signed integers, the compiler
uses an arithmetic right shift. For unsigned integers, a
logical shift is used when shifting right.
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HPC C Compiler-CCHPC Introduction (Continued)
Storage Class Modifiers
Keywords const and volatile can be applied to any
data. Const indicates that the symbol refers to a location which is read-only. If the symbol is· in static or
global storage, it will be assigned to ROM memory.
Volatile indicates that optimization must not change or
reduce the accesses to the symbol.
Since the HPC supports 8-bit operations, CCHPC
does not automatically promote "char" types to "int"
when evaluating expressions. For a binary operation,
the compiler promotes a "char" to an "int" only if the
other operand is a 16-bit (or more) value or if the result of the operation is required to be a 16-bit (or
more) value. The use of 8-bit operations yields efficient code without compromising the correctness of
the result.
CCHPC uses the standard C preprocessor and any
standard preprocessor functions, including" # define",
"#include" and macros with arguments are supported.
A program is set of intermixed variable and function
definitions. Variables must always be defined before
use, functions may be defined in any order.
Variable initialization is performed according to the
draft ANSI standard rules.
Standard C operators, and their hierarchy are as described in the ANSI standard draft.
CCHPC allows the programmer to imbed assembler
code directly in the C source. All data between "/$"
and "$/" is copied directly to the assembler output file
generated by CCHPC.
To make maximum efficient use of HPC architectural
features CCHPC supports the notion of "storage class
modifiers". A storage class modifier may appear with
or in place of a storage class. Following is the set of
storage class modifiers:
Keyword
BASEPAGE
ACTIVE
NOLOCAL
INTERRUPTn
(where n = 1 to 7)
Applicable to
variable
function
function
function
Storage class modifiers may be supplied with each
variable or function declaration. The effect of each
storage class modifier is described in the following:
BASEPAGE-The variable will be allocated in the
BASE section. Accessing a basepage variable is more
efficient than accessing any other type of variable but
the amount of basepage storage is limited.
ACTIVE-The address of the function is placed in the
16 word JSRP table. Calls to the function will require 1
byte of code. The most frequently called functions
should be considered for designation as ACTIVE functions for maximum code efficiency.
NOLOCAL-The functions local variables are not allocated on the run-time stack. Instead, they are allocated in static storage. Access to local variables in a
NOLOCAL function will be more efficient since access
can be direct rather than indexed from the frame
pointer. If a function has no arguments or local variables, then entry and exit from the function will be
much more efficient since there will be no need to
adjust the frame pointer on entry and exit of the function.
INTERRUPTn-These modifiers can be used to set
interrupt vectors (one through seven) to point to a particular function. Any function which has an INTERRUPT storage class modifier has special entry and
exit code generated. This code will push all HPC registers (A, B, K, X, PSW and word at RAM address 0)
onto the stack before executing normal function entry
code. Exit code restores all registers before returning
from the interrupt.
CCHPC IMPLEMENTATION DEPENDENT
CONSIDERATIONS
Memory
CCHPC is designed to execute in a 16-bit environment. Special care must be taken when using CCHPC
in an 8-bit HPC system.
Storage Classes
CCHPC supports the following storage classes:
auto
static
register
typedef
extern
Due to HPC architectural features, the "register" storage class is limited. A variable can be assigned a
"register" only if it is of type pointer and only if a register is available. The first "register" pOinter variable encountered is assigned to the HPC B register, the second to the HPC X register and any subsequent ones
are treated as "auto" (unless NOLOCAL is in effect, in
which case it will be treated as "static").
The default storage class for global declarations is
"static". The default storage class for declarations
within functions is "auto".
C Stack Formation
The Stack Pointer (SP) is initialized to the start address assigned by the linker. The Stack Pointer always points to the next free location at the top of the
stack.
Within a function, the compiler maintains a Frame
Pointer which is used to access function arguments
and local automatic variables. The Frame Pointer location is reserved by the compiler at location Oxbe.
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HPC C Compiler-CCHPC Introduction (Continued)
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To call a function, the compiler pushes arguments
onto the stack in reverse order, performs a jump subroutine to the function, then decrements the Stack
Pointer by the number of bytes pushed onto the stack.
Since all stack pushes are 16-bits, any 8-bit arguments are automatically promoted to 16-bits. On function entry, the compiler creates new stack and frame
pointers for the function. On exit, the stack and frame
pointers are restored to the values they had on entry
to the function.
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The loop statement is an extension to the ANSI standard. Loop allows the programmer to create a code
efficient loop by using the HPC DECSZ instruction.
The loop statement may be nested. A break statement inside the loop will cause an immediate exit from
the loop.
Run-Time Notes
During evaluation of complex expressions, the compiler uses the stack to store intermediate results.
All HPC C programs start with a call to the function
"main" with no arguments. Before calling "main", runtime start-up code initializes RAM. The initial values of
static or global variables with initialization are stored in
ROM and copied to the appropriate variables in RAM.
Static or global variables without initialization are
cleared to zero. The function "main" must be defined.
When "main" returns to the run-time start-up routine it
executes the HALT macro provided which puts the
chip in an infinite loop.
Since the run-time stack is of fixed size and there is no
check for stack overflow, it is up to the programmer to
insure that the stack area is large enough to prevent
stack overflow.
Memory location zero is reserved by the compiler.
The HPC C Compiler User's Manual provides additional information on the features and functions of
CCHPC.
Using In-Line Assembler Code
CCHPC allows in-line assembler code to be entered in
the body of a C function. The assembler code can
access any of the currently active variables or can get
the address of a variable.
Efficiency Considerations
HPC code size and execution time can be optimized
by making maximum use of BASEPAGE variables.
When BASEPAGE is full, static variables are next
most efficient. The least efficient variables are automatic since they require an indirect indexed access.
Minimizing the use of longs and floats will improve
efficiency. The HPC architecture strongly supports unsigned arithmetic, so the programmer should use unsigned variables except for cases that absolutely require signed arithmetic. The compiler does not attempt to identify common subexpressions for computation only once, so this must be done by the programmer.
HPC Cross Assembler-ASMHPC
Statements and Implementation
INTRODUCTION
The following C statements are supported by CCHPC:
expression;
if
if ... else
while .. .
do ... while
for .. .
break
goto
continue
return
return .. .
case .. .
default
switch .. .
switchf .. .
loop .. .
The switch statement will generate an efficient jump
table for a set of cases if the cases are sufficiently
close, or it will generate individual tests for each case.
The switchf statement is the same as the switch statement except that when a jump table is generated for
the switchf statement the compiler does not generate
the code necessary to check the bounds of the value
to be switched on. This creates a more efficient form
of the switch statement but the programmer must insure that the value being switched on is in range.
The MOLE HPC cross-assembler (ASMHPC) is a
cross-assembler for the NSC HPC family of microcontrollers. ASMHPC translates symbolic input files into
object modules and generates an output listing of the
source statements, machine code, memory locations,
error messages, and other information useful in debugging and verifying programs.
ASMHPC has the following useful features- Macro capability that allows common code sequences to be coded once.
- Conditional code assembly is supported.
- Translates symbolic assembly code modules into
object code. Object modules are linkable and relocatable.
- Symbolic names may be defined for any HPC register, memory location or 1/0 port. Symbols may
be defined as byte or word size.
- Symbol table and cross-reference output is provided.
- Full set of Assembler directives are provided for
ease of generating vector tables for interrupts,
short subroutine calls, jump indirects and other
data generation within the object program.
- Data and code sections are user definable. Sections may be relocatable or absolute. Sections
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may be assigned to 8-bit memory to support the
HPC 8-bit mode. Data sections may be assigned to
basepage RAM on the HPC to maximize efficient
access to variables.
Accepts assembly source code generated by the
HPC C Compiler, CCHPC.
Full set of Assembler controls for greater flexibility
in debugging modules and programs created by
ASMHPC.
Rules for symbol or label construction are:
1. The first character must be either a letter, a question mark (?), an underscore (_), a dollar sign ($) or
a period (.).
2. All other characters may be any alphanumeric character, dollar sign ($), question mark (?) or underscore (_).
3. The maximum number of characters in a symbol or
label may be selected by the user with the SIZESYMBOL control. The default is 64.
4. Symbols starting with dollar sign ($) are local symbols and are defined only within a local region.
5. Labels and symbols are case sensitive.
ASSEMBLY LANGUAGE ELEMENTS
Assembly language statements are comprised of four
fields of information.
Label field-This is an optional field. It may contain a
symbol used to identify a statement referenced by
other statements. A symbol used in this manner is
called a label.
Operation field-This field contains an identifier
which indicates what type of statement is on the line.
The identifier may be an instruction mnemonic or an
assembler directive. The operation field is required on
all assembler statement lines, except those lines
which consist of only a label and/or comment.
Operand field-The operand field contains entries
that identify data to be acted upon by the operation
defined in the operation field. Operand examples are
source or target addresses for data movement, immediate data for register initialization, etc.
Comment field-Comments are optional descriptive
notes that are included in the program and listings for
programmer reference and program documentation.
Comments have no effect on the asembled object
module file.
Operand Expression Evaluation
The expression evaluator in the assembler evaluates
an expression in the operand field of a source program. The expressions are composed of combinations of terms and operators. An expression may consist of a single term or may consist of two or more
terms combined using operators. Terms are-numbers in decimal, hexadecimal, octal or binary, string
constants, labels and symbols or the location counter
symbol. Each term has four attributes: its' value, relocation type, memory type and size. The relocation
type is either absolute or relocatable. The memory
type indicates whether the term represents a BASE,
RAM8, ROM8, RAM16, ROM16 or null (in the case of
an absolute term). The size of a term is null, byte or
word.
The operators allowed in ASMHPC are: arithmetic,
logical, relational, upper and lower byte extraction and
untype operators. Arithmetic operators are +, -, *, /,
MOD, SHL, ROL and ROR. The logical operators are
NOT, AND, OR and XOR. The relational operators are
EO, NE, GT, LT, GE and LE. Upper and lower extraction operators are HIGH and LOW. The untype operator is &.
Parentheses are permitted in expressions. Parentheses in expressions override the normal order of evaluation, with the expression(s) within parentheses being
evaluated before the outer expressions.
Numbers are represented in ASMHPC in 16-bit 2's
complement notation. Signed numbers in this representation have a range of -32768 (x'8000) to
+ 32767 (x'7FFF). Unsigned numbers are in the range
of a to 65535. String constants are internally represented in the 8-bit ASCII code. All expression evaluation is done treating terms as unsigned numbers, for
example, -1 is treated as having the value x'FFFF.
The magnitude of the expression must be compatible
with the memory storage available for the expression.
For example, if the expression is to be stored in an 8bit memory location, then the value of the evaluated
expression must not exceed x' FF.
Character Set
Each assembly language statement is written using
the following characters:
Letters-A through Z (a through z)
Numbers-O through 9
Special Characters-!$%'( )*+ ,-./;:< = >&#?_b"
Note: Upper and lower case are distinct; b' indicates a blank.
Location Counter
There is a separate location counter for each program
section, and the counter is relative to the start of that
section. The assembler uses the location counter in
determining where the current statement goes in the
current program section. If the program section is relocatable, the linker does the final job of assigning an
absolute address to the instruction.
Symbols and Labels
Symbols and labels are used to provide a convenient
name for values and statements. Symbols and labels
have the same rules for construction, only their use
distinguishes a symbol from a label.
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ASSEMBL V PROCESS
The ASMHPC assembler performs its functions by
reading the assembly language statements sequentially from the beginning of a module or a program to
the end, generating the object code and a program as
it proceeds.
The ASMHPC assembler is a multi-pass assembler
which allows it to resolve forward referenced symbols
and labels efficiently. The number of passes can be
selected using the PASS control. This allows the user
to select the level of optimization of forward referenced instructions.
-
-
-
MACROS
Macros help make an assembly language program
easier to create, read and maintain. A macro definition
is an assembly statement or statements that are referred to by a macro name. The macro may have parameters that are operated upon by the assembly
statements. ASMHPC will substitute the macro definition for the macro name with the appropriate parameters during the assembly process. Repetitive or similar
code can be defined as macros and the programmer
can use the macros to build a library of basic routines.
Variables unique to particular applications can be defined in and passed to a particular macro when called
by main programs.
macro is deleted by the .MDEL directive, the previous definition becomes active. If mname is the
same as a valid instruction mnemonic, the macro
name is used in place of the normal instruction.
Parameters are the optional list of parameters
used in the macro. Parameters are delimited from
mname and additional parameters with commas.
The macro body is a sequence of assembly language statements and may consist of simple text,
text with parameters, and/or macro-time operators.
.ENDM identifies the end of the macro and must
be used to terminate the macro definition.
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Calling a Macro
Once a macro has been defined, it may be called by a
program to generate code. A macro is called by placing the macro name in the operation field of the assembly language statement, followed by the actual
value of the parameters to be used (if any). The form
of a macro call is:
mname [parameters]
where:
- mname is the previously assigned name in the
macro definition and
- parameters are the optional list of input parameters. When a macro is defined without parameters,
the parameter list is omitted from the call.
The macro call as well as the expanded macro assembly code will appear on the assembler listing if the
appropriate controls are enabled.
Defining a Macro
Macros must be defined before they are used in a
program. Macro definitions do not generate code.
Code is generated only when the macros are called by
the assembly program. Macro definitions have a Macro name by which the macro will be referred in the
program, declaration of any parameters to be used in
the macro, assembler statements that are contained
in the macro and directives that define the boundaries
of the macro.
Following is the macro definition structure:
Using Parameters
The power of a macro can be increased with the use
of optional parameters. The parameters allow variable
values to be declared when the macro is called.
When parameters are included in a macro call, the
following rules apply to the parameter list:
1. One comma and zero or more blanks delimit parameters.
2. A semicolon terminates the parameter list and
starts the comment field.
3. Single quotes (') may be included as part of a parameter except as the first character of a parameter.
4. A parameter may be enclosed in single quotes (,), in
which case the quotes are removed and the string
is used as the parameter. This function allows
blanks, commas, or semicolon to be included in the
parameter. To include a quote in a quoted parameter, include two quotes (").
5. Missing or null parameters are treated as strings of
length zero.
The macro operator @ references the parameter list in
macro call. Using the operator @ in an expression, the
number of parameters can be used to control conditional macro expansion. The @ operator may also be
.MACRO mname [,parameters]
•
•
•
macro body
•
•
•
.ENDM
where:
- .MACRO is the assembler directive which initiates
the macro definition.
- mname is the name of the macro. Multiple macros
can have the same name. The last macro defined
is the macro definition used. Macro definitions are
retained in the macro definition table; if the current
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HPC Cross Assembler-ASMHPC
(Continued)
used with a constant or symbol to reference the individual parameters in the macro parameter list. These
capabilities eliminate the need for naming each parameter in the macro definition, which is useful when
there are long parameter lists. Using the @ parameter
count operator it is possible to create macros which
have a variable number of parameters.
The macro operator for concatenation is A. In a macro
expansion the A operator is removed and the strings
on each side of the operator concatenated after parameter substitution. This operator provides the ability
of creating variable labels through the use of macros.
for the statement and the contents of these locations.
To the left of the instruction, an "R" indicates a relocatable argument in this instruction, "X" indicates an
external argument, "C" indicates a complex argument
and "+" indicates macro expansion.
The assembler listing optionally includes an alphabetical listing of all symbols used in the program together
with their values, absolute or relocatable type, word or
byte or null type, section memory type and public or
external. Optionally a cross reference of all symbol
usage by source line number is given; the defining line
number is preceded by a "-".
The total number of errors and warnings, if any, is
printed with the listing. Errors and warnings associated with assembly language statements are flagged
with descriptive messages on the appropriate statement lines.
Local Symbols
When a label is defined within a macro, a duplicate
definition results with the second and each subsequent call of the macro. This problem can be avoided
by using the .MLOC directive to declare labels local to
the macro definition.
Directives
Directive statements control the assembly process
and may generate data in the object program. The
directive name may be preceded by one or more labels, and may be followed by a comment. The directive's name occupies the operation field. Some directives require an operand field expression.
Conditional Expansion
The conditional assembly directives allow the user to
generate different lines of code from the same macro
simply by varying the parameter values used in the
macro calls.
Nested Macro Calls
Assembler Controls
Nested macro calls are supported. A macro definition
may call another macro. The number of allowable levels of nesting depends on the sizes of the parameter
lists, but at least ten is typical.
A logical extension of the nested macro call is the
recursive macro call, that is a macro that calls itself.
This is allowed, but the programmer must insure that
the call does not create an infinite loop.
An assembler control is a command that may be used
in the source program on a control line or on the invocation line as an option. A control line is indicated by a
# in column 1 of the source line. Comments may be
included on a control line by preceding the comment
with a semicolon. Invocation line controls are masters
and override the same controls in the program source.
Examples of assembler control capabilities are: format
control of the assembly listing, enable/disable listing
of conditional code and conditional directives, listing
of comment lines, macro expansion lines, macro object lines only. Cross references and symbol tables
can be generated in the listing file, macro local symbols and constants can be put into the symbol table,
number of assembler passes specified, assembler
controls saved and restored ...
Nested Macro Definitions
A macro definition may be nested within another macro. Such a macro is not defined until the outer macro
is expanded and the nested macro is executed. This
allows the creation of special purpose macros based
on the outer macro parameters. Using the .MDEL directive and the nested macro capability a macro can
be defined only within the range of the macro that
uses it.
ASSEMBLER INVOCATION
ASMHPC invocation will vary somewhat depending
upon the host operating system being used. All systems have a similar invocation line format. The arguments for ASMHPC invocation are: the name of the
assembly program(s) or module(s) to be assembled,
list of assembler options and the name of a command
file that contains additional invocation line source filenames and/or options. An assembler invocation line
option is an assembler control that is specified in a
manner consistent with the requirements of the operating system. When specifying a filename, the name
may include a directory path. If no arguments are
specified on the invocation line, the ASMHPC HELP
menu is displayed.
Macro Comments
All lines within a macro definition are stored with the
macro, however, any text following "; ;" is removed
before being stored. This text will appear on the listing
of the macro definition but will not appear on the macro expansion.
ASSEMBLY LISTING
The listing generated by ASMHPC contains program
assembly language statements, line numbers, page
numbers, error messages and a list of the symbols
used in the program. The listing of assembly language
statements which generate machine code includes
the hexadecimal address of memory locations used
8·24
::J:
"a
o
HPC Cross-Unker-LNHPC
INTRODUCTION
word aligned data (ROM16, RAM16, BASE which
are word aligned) are allocated first. The user wi"
benefit if the word aligned data is placed in these
sections and byte data in other sections.
The load map shows the following:
- Range definitions showing the memory ranges
specified by the /RANGE option or by the default.
- The Memory Order Map showing the starting and
ending addresses of each contiguous range of
memory used.
- The Memory Type Map showing how memory is
allocated organized by the memory type.
- The Total Memory Map showing the allocation of
a" ROM and a" RAM.
- The Section Table showing each section in the link,
along with its starting and ending address. Section
attributes are also displayed.
The MOLE HPC cross-linker (LNHPC) links object files
generated by ASMHPC. The result is an absolute load
module in various formats, such as the MOLE .1m"
format, INTEL Hex or COFF formats. LNHPC combines a number of ASMHPC relocatable object modules into a single absolute object module with a" the
relocatable addresses assigned. A" external symbol
references between modules are resolved, and library
object modules are linked as required.
LNHPC creates two outputs:
1. An absolute object module file that can be downloaded to the MOLE development system for emulation and debugging. The output could also be
used by the HPC Source Level Debugger if the
SYMBOL option was used on CCHPC to create
symbolic information.
2. A load map that shows the result of the link with an
optional cross reference listing.
II
LINKER INVOCATION
LNHPC invocation wi" vary somewhat depending
upon the host operating system being used. A" systems have a similar invocation line format. The arguments for LNHPC invocation are-the name of the object file(s), module(s) or libraries to be linked, list of
linker options and the name of a command file that
contains additional invocation line source filenames
and/ or options. A linker invocation line option is a linker control that is specified in a manner consistent with
the requirements of the operating system. When specifying a filename, the name may include a directory
path. If no arguments are specified on the invocation
line, the LNHPC HELP menu is displayed.
LNHPC MEMORY ALLOCATION
The Linker places each section in memory based on
the attributes of the section and the memory that is
available. Available memory is specified by the
RANGE command. Each section has the following attributes:
Memory type-BASE, ROM8, ROM16, RAM8,
RAM16
Size-determined from the object modules
Absolute-section was specified as absolute in assembler
Fixed-starting address was specified by the SECT
command
Ranged-memory range was specified by the SECT
command.
Memory is allocated section by section. Sections are
allocated in the following order:
1. Each absolute or fixed section is placed in memory
at its specified address.
2. Each ranged section is placed in memory within the
specified range, regardless of whether this memory
has been allocated in the Range Definition. An error
will occur if the section can not be located.
3. A" remaining sections are allocated as follows: As
each section is processed, the ranges for its memory type are examined to find enough free space to
allocate the section. Each range is examined in order. The first space large enough to contain the
section is used. At this point, the memory allocated
is marked used. If not enough memory is available
to allocate the section, an error message is displayed. For efficiency, sections which may contain
HPC Cross-Librarian-LlBHPC
INTRODUCTION
The MOLE HPC cross-librarian (LlBHPC) reads object
modules produced by ASMHPC and combines them
into one file called a library. The linker can then
search the library for any undefined external symbols
and link the object module associated with the external symbol. LNHPC wi" only link in those library object
modules required to satisfy external references to
maximize efficient use of memory space. LlBHPC is a
librarian utility that is provided to allow the user to develop standard modules and place them in libraries.
The user may add, delete and list modules in a library
file. A library of typical C functions is supplied with the
HPC C Compiler (CCHPC). This library is an example
of the type of library that could be created for an HPC
application program. It is intended to be used as a
template for the user to create a custom library specific to the application for maximum code efficiency.
8-25
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HPC Cross-Librarian-LlBHPC (Continued)
function. During Breakpoint, the trace will record and
display the prior 2000 HPC accesses, machine instructions or C source lines.
DBHPC will display source code and search for strings
in the source code. The display of source code can be
C source from the file, disassembled assembly code,
or as C source with corresponding assembly code intermixed. The C stack can be displayed showing the
current function calling history. The program variables
and data may be autoprinted on execution of a Breakpoint.
A history file may be created with DBHPC recording
the DBHPC input and responses. The history file, or a
simple ASCII file, may be used as input to DBHPC.
This provides the capability of re-running debug sessions. Operating system commands can be executed
from within DBHPC and control can be passed back to
the debugger. A transparent mode will allow interaction through the debugger directly to the MOLE.
DBHPC uses COFF files generated by the HPC C
Compiler, Assembler, and Linker to obtain the object
code and symbolic information required for debugging. The COFF files are created with the /symbol
switch on the CCHPC and ASMHPC packages.
Following is a summary of the commands and features of DBHPC:
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LIBRARIAN INVOCATION
L1BHPC invocation will vary somewhat depending
upon the host operating system being used. All systems have a similar invocation line format. The arguments for LlBHPC invocation are-the name of the
library file to process, list of librarian options and the
name of a command file that contains additional invocation line source filenames and/or options. A librarian invocation line option is a librarian control that is
specified in a manner consistent with the requirements of the operating system. When specifying a filename, the name may include a directory path. If no
arguments are specified on the invocation line, the
LlBHPC HELP menu is displayed.
HPC Source Debugger-DBHPC
The HPC Source Debugger is designed to be a
source-level debugger for the HPC family of microcontrollers. This package will have capabilities similar to
the HPC MOLE, yet offer the support of symbolics and
source code debugging facilities for C language programs. DBHPC will execute on the IBM PC or compatible machines and control the MOLE development
station using interactive sequences transparent to the
user to effect high level debug functions. DBHPC will
also provide download capability to the MOLE.
DBHPC will have the ability to display and modify data
as symbolic variables or as variable addressing expressions in the context of the program. Data will be
displayed as the variable or expression type, but can
be overridden by specifiers derived from "printf"-type
controls. The HPC hardware registers are available for
display and modification. Those registers defined and
used by the program will be available in the context of
their use by the program and with the others, e.g. interrupt or processor registers, will also be available,
even though the program does not access them.
The debugger will provide hardware Breakpoint capability as supplied by the MOLE. Also available will be
software qualification of Breakpoints done by the PC
to provide the user with the capability of specifying
complex Breakpoint triggering conditions. Breakpoints
can be set for execution of functions, source lines or
addresses and accesses to variables or data addresses. Singlestepping will be available by source code
line or by machine instruction. Functions may be
stepped through as if it were a single operation or into
the function to examine the internal actions within the
Commands for Data Manipulation
Command
Alter
Deposit
Find
List
Options
Byte
Word
Long
Float
Pointer
Chars
Type
Modify
These MOLE commands are available on the HPC
Debugger with additional arguments. The Byte, Word,
... options are used to define the data type to be used
in performing this operation.
The Type and Modify commands have only Byte,
Word and Long options.
Added to the MOLE commands for data manipulation
is a command for displaying variables, values of expressions and data pointed at by variables or address
expressions. This command is called View.
8·26
X
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o
HPC Source Debugger-DBHPC (Continued)
Debug Commands
Autoprint
Displays user selected information on each Breakpoint, Watchpoint or Singlestep.
Breakpoint
MOLE hardware Breakpoint specified with C source trigger conditions.
Clear
Clears Breakpoint, Time, Trace, Watch point enables.
Watchpoint
Hardware/Software Breakpoint allowing the user to define complex triggering
conditions and sequences. The user program will not execute in real time until
reaching the Watchpoint condition in all cases.
Trace
MOLE hardware Trace specified with C source trigger conditions.
Time
MOLE Time function specified with C source trigger conditions.
Singlestep
Step each C source line.
Next Source
Step over a function.
Single Inst.
Step each machine instruction. This is the MOLE Singlestep function.
Next Inst.
Step over subroutines. This is the MOLE Next function.
Reset
Resets the HPC on the MOLE.
RGo
Performs a Reset and Go command.
Go
Starts running the HPC or enables a Breakpoint, Trace, Time or Watchpoint
command.
Search
Search Trace memory for specified occurrence.
Stack History
Display program stack showing functions, arguments and local variables.
List Source
Lists C source code.
List Xtended
Lists program as C source followed by assembly code.
Put
MOLE Put function allows input of assembly code line-by-line.
Radix
Sets default radix for input and display.
Trace Mode
Sets mode of Trace. Capture of source line, machine cycle or machine instruction.
Status
Display chip and debugger status.
Help
Displays Help menu.
End
Ends debugger session.
History
Create a History file on disk.
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Commands for Controlling Status
Special Commands
Load
Load file from disk to MOLE and initialize DBHPC.
Map
Map emulation memory on or off-board the MOLE.
Bypass
Bypass debugger and communication directly with MOLE.
Chip
Define chip and system memory configuration for MOLE.
Diagnostic
Run MOLE on-board Diagnostics.
I
Invoke a shell or execute a DOS command.
8-27
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HPC Source Debugger-DBHPC (Continued)
ca
Q.
HOW TO ORDER HPC SOFTWARE
1::
HPC software is available for a variety of host environments. To order a software package, seleGf the host
system and order the part number listed.
Included, along with the cross assembler, in the software package are two file conversion routines to convert the assembler output (LM) to HEX and to convert
HEX to LM. Also included in the software package is a
COMM program which facilitates the downloading and
uploading between the host and the MOLE, and adds
the capability to make the host ·act as a terminal.
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The C compiler package also includes the relocatable
assembler. Order one or the other but not both.
An HPC software evaluation package is available
(MOLE-HPC-IBMEVAL) that will allow up to 1000 lines
of code to be compiled, assembled and linked.
Software Selection Table
Host·
IBM-PC
Order
Part Number
MOLE-HPC-IBMR
MOLE-HPC-IB~-CR
MOLE-HPC-IBMEVL
Description
Includes
Relocatable Assembler
Software for IBM
(ASMHPC, L1BHPC,
LNHPC, DBHPC)
HPC Software Users Manual
and Software Disk
PC-DOS Communications
Software Users Manual
C Compiler for IBM
(CCHPC)
HPC C Compilers Users Manual
and Software Disk
Assembler Software for IBM
MOLE-HPC-IBM
Evaluation Module
Includes Assembler
and C Compiler
Evaluation Software
'VAX, VMS and VAX UNIX will be supported in the near future. Contact field sales for more information.
8-28
Manual
Number
424410836-001
420040416-001
424410883-001
424410897 -001
Section 9
Appendices/
Physical Dimensions
Section 9 Contents
Industry Package Cross Reference ...................................................
Surface Mount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLCC Packaging........................................ ...........................
TapePak Packaging ................................................................
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Bookshelf
Authorized Distributors
9-2
9-3
9-5
9-7
9-11
9-12
~
Industry Package Cross-Reference Guide
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Motorola
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RCA
Hitachi
NEC
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20· and 28·Lead
Glass/Metal DIP
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Transmission Line Drivers/Receivers
The common purpose of transmission line drivers and receivers is to transmit data quickly and reliably through a
variety of environments over electrically long distances.
This task is complicated by the fact that externally introduced noise and ground shifts can severely degrade the
data.
CD
to 4000 feet (up to 1 kBaud). RS-423 also requires high
impedance driver outputs with power off so as not to load
the transmission line.
Differential Data Transmission
When transmitting at very high data rates, over long distances and through noisy environments, single-ended transmission is often inadequate. In these applications, differential data transmission offers superior performance. Differential transmission nullifies the effects of ground shifts and
noise signals which appear as common mode voltages on
the transmission line.
The connection between two elements in a system should
be considered a transmission line if the transmitted signal
takes longer than twice its rise or fall time to travel from the
driver to the receiver.
Single-Ended Data Transmission
In data processing systems today there are two basic
means of communicating between components. One method is single-ended, which uses only one signal line for data
transmission, and the other is differential, which uses two
signal lines.
The Electronics Industry Association (EIA) has developed
several standards to simplify the interface in data communications systems.
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RS-422
RS-422 was defined by the EIA for this purpose and allows
data rates up to 10 MBaud (up to 40 ft.) and line lengths up
to 4000 feet (up to 100 kBaud).
Drivers designed to meet this standard are well suited for
party-line type applications where only one driver is connected to, and transmits on, a bus and up to 10 receivers
can receive the data. While a party-line type of application
has many uses, RS-422 devices cannot be used to construct a truly multipoint bus. A multipoint bus consists of
multiple drivers and receivers connected to a single bus,
and anyone of them can transmit or receive data.
RS-232
The first of these, RS-232, was introduced in 1962 and has
been widely used throughout the industry. RS-232 was developed for single-ended data transmission at relatively
slow data rates (20 kBaud) over short distances (up to
50 ft.).
RS-485
To meet the need for truly multipoint communications, the
EIA established RS-485 in 1983. RS-485 meets all the requirements of RS-422, but in addition, this new standard
allows up to 32 drivers and 32 receivers to be connected to
a single bus-thus allowing a truly multipoint bus to be constructed.
RS-423
With the need to transmit data faster and over longer distances, RS-423, a newer standard for single-ended applications, was established. RS-423 extends the maximum data
rate to 100 kBaud (up to 30 ft.) and the maximum distance
RS-232C Application
DATA
OUT
DATA
IN
":"
":"
TLIOO/2901-1
EIA RS-423 Application
DATA
IN
DATA
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9-5
TL/OO/2901-2
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TLIOO/2901-3
The key features of RS-485:
• Implements a truly multipoint bus consisting of up to 32
drivers and 32 receivers
• An extended common-mode range for both drivers and
receivers in TRI-STATE and with power off (-7V to
+12V)
• Drivers can withstand bus contention and bus faults
National Semiconductor produces a variety of drivers, receivers, and transceivers for these four very popular transmission standards and numerous other data transmission
requirements.
Shown below is a table that highlights key aspects of the
EIA Standards. More detailed comparisons can be found in
the various application notes in Section 1.
RS-485 Application
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TL/OO/2901-4
SpeCification
RS-423
RS-232C
RS-422
RS-485
Mode of Operation
Single-Ended
Single-Ended
Differential
Differential
Number of Drivers and Receivers
Allowed on One Line
1 Driver,
1 Receiver
1 Driver,
10 Receivers
1 Driver,
10 Receivers
32 Drivers,
32 Receivers
Maximum Cable Length
50 feet
4000 feet
4000 feet
4000 feet
Maximum Data Rate
20 kb/s
100 kb/s
10 Mb/s
10 Mb/s
Driver Output Maximum Voltage
±25V
±6V
- 0.25V to + 6V
-7Vto + 12V
Loaded
±5V
±3.6V
±2V
±1.5V
Unloaded
±15V
±6V
±5V
±5V
3 kO to 7 kO
4500 min
1000
540
Driver Output Signal Level
I
I
Driver Load Impedance
Maximum Driver Output Current
(High Impedance State)
Slew Rate
Receiver Input Voltage Range
I
I
Power On
----
Power Off
VMAX/3000
± 100 /-LA
30 V//-Ls max
±15V
Controls Provided
---±12V
---±100 /-LA
----7Vto +7V
± 100 /-LA
± 100 /-LA
----7Vto +12V
Receiver Input Sensitivity
±3V
±200 mV
±200 mV
±200mV
Receiver Input Resistance
3 kO to 7 kO
4 kO min
4 kO min
12 kO min
9-6
~National
~ Semiconductor
Plastic Leaded Chip Carrier (PLCC) Packaging
MANUFACTURING TECHNIQUES
General Description
Learning how to surface mount components to printed circuit boards requires the user to become educated in new
assembly processes not typically associated with throughhole insertion/wave soldering assembly methods.
The Plastic Leaded Chip Carrier (PLCG) is a miniaturized
low cost semiconductor package designed to replace the
Plastic Dual-In-Line Package (P-DIP) in high density applications. The PLCC utilizes a smaller lead-to-Iead spacing0.050" versus 0.100" - and leads on all four sides to
achieve a significant footprint reduction over the P-DIP. The
rolled under J-bend lead form separates this package style
from other plastic quad packages with flat or gull wing lead
forms. As with virtually all packages of 0.050" or less lead
spacing, the PLCC requires surface mounting to printed circuit boards as opposed to the more conventional thru-hole
mounting of the P-DIP.
Surface mounting involves three basic process steps:
1) Application of solder or solder paste to the printed circuit
board.
2) POSitioning of the component onto the printed circuit
board
3) Reflowing of the solder or solder paste.
As with any process, there are many details involved to
achieve acceptable throughput and acceptable quality. National Semiconductor offers a surface mounting guide which
deals with the specifics of successful surface mounting. We
encourage the user to review this document and to contact
us if further information on surface mounting is desired.
History
The Plastic Leaded Chip Carrier with J-bend lead form was
first introduced in 1976 as a premolded plastic package.
The pre molded version has yet to become popular but the
quad format with J-Bend leads has been adapted to traditional post molded packaging technology (the same technology used to manufacture the P-DIP). In 1980 National
Semiconductor developed a post molded version of the
PLCC. The J-bend leadform allowed them to adopt the footprint connection pattern already registered with JEDEC for
the leadless chip carrier (LCG). In 1981 a task force was
organized within JEDEC to develop a PLCC registration for
package I/O counts of 20,28,44,52,68,84,100, and 124.
A registered outline was completed in 1984 (JEDEC Outline
MO-047) after many changes and improvements over the
original proposals. This first PLCC registration covers
square packages with an equal number of leads on all sides.
A second registration, MO-052, was completed in 1985 for
rectangular packages with I/O counts of 18, 22, 28 and 32.
Benefits of the PLCC
There are four principle advantages offered the user by
switching from P-DIP to PLCC. These four advantages are
outlined below as follows:
1. Increased Density- Typically 3-to-1 size reduction of printed circuit
boards. See Figure 1 for a footprint comparison between PLCC and P-DIP. This can be as high as 6-to1 in certain applications.
- Surface mounting allows components to be placed
on both sides of the board.
- Surface mount and thru-hole mount components can
be placed on the same board.
- The large diameter thru-holes can be reduced in
number, entirely eliminated, or reduced in size (if
needed for via connection).
Since 1980 many additional semiconductor manufacturers
and packaging subcontractors have developed PLCC capability. There are now well over 20 sources with the number
growing steadily.
2. Increased Performance- Shorter traces on printed circuit boards.
- Better high frequency operation.
- Shorter leads in package. Figure 2 and Table I compare PLCC and P-DIP mechanical and electrical
characteristics.
Surface Mounting
Surface mounting refers to component attachment whereby
the component leads or pads rest on the surface of the PCB
instead of the traditional approach of inserting the leads into
through-holes which go through the board. With surface
mounting there are solder pads on the PCB which align with
the leads or pads on the component. The resulting solder
joint forms both the mechanical and electrical connection.
3. Increased Reliability- Leads are well protected.
- Fewer connectors.
- Simplified rework.
- Vibration and shock resistant.
ADVANTAGES
4. Reduced Cost- Fewer or smaller printed circuit boards.
- Less hardware.
- Same low cost printed circuit board material.
- Plastic packaging material.
- Reduced number of costly plated-through-holes.
- Fewer circuit layers.
The primary reason for surface mounting is to allow leads to
be placed closer together than the 0.100" standard for DIPs
with through-hole mounting. Through-hole mounting on
smaller than 0.100" spacing is difficult to achieve in production and generally avoided. The move to 0.050" lead spacing offered with the current generation of surface mounted
components, along with a switch from a dual-in-line format
to a quad format, has achieved a threefold increase in component mounting density. A need to achieve greater density
is a major driving force in today's marketplace.
9-7
1.60 1.50
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0.5 IN.
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0
0
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20
40
60
80
100
120
PACKAGE TERt.lINAL COUNT
PACKAGE TERMINAL COUNT
TL/ZZ/OOO1-l
TL/ZZ/OOOl-2
FIGURE 1. FootprInt Area of PLCC VS. P-DIP
FIGURE 2. Longest Internal Lead PLCC VS. P-DIP
TABLE I. ElectrIcal Performance of PLCC VS. P·DIP (44110 PLCC VS. 40 I/O P·DIP, both with Copper Leads)
Shortest Lead
CrIterIa
Longest Lead
PLCC
P·DIP
PLCC
P·DIP
3!l
4!l
6!l
7!l
Lead-to-Lead Capacitance
(Measured on Adjacent Leads)
0.1 pF
0.1 pF
0.3 pF
3.0pF
Lead Self-Inductance
(Calculated)
3.2 nH
1.4 nH
3.5 nH
19.1 nH
Lead Resistance
(Measured)
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TLIZZ/OOOl-3
FIGURE 3. Package OutlIne
TABLE II. PrIncIple DImensIons Inches/(Millimeters) (Refer to Figure 3)
Lead
Count
Total WIdth
Total HeIght
Body WIdth
Contact Spread
MIn
Max
MIn
Max
MIn
Max
MIn
Max
20
0.385 sq.
(9.779)
0.395 sq.
(10.03)
0.165 sq.
(4.191)
0.180 sq.
(4.572)
0.345 sq.
(8.763)
0.355 sq.
(9.017)
0.310 sq.
(7.874)
0.330 sq.
(8.382)
28
0.485 sq.
(12.32)
0.495 sq.
(12.57)
0.165 sq.
(4.191 )
0.180 sq.
(4.572)
0.445 sq.
(11.30)
0.455 sq.
(11.56)
0.410 sq.
(10.41)
0.430 sq.
(10.92)
44
0.685 sq.
(17.40)
0.695 sq.
(17.65)
0.165 sq.
(4.191)
0.180 sq.
(4.572)
0.645 sq.
(16.38)
0.655 sq.
(16.64)
0.610 sq.
(15.49)
0.630 sq.
(16.00)
9-8
"'tJ
r-
TABLE II. Principle Dimensions Inches/(Mllilmeters) (Refer to Figure 3) (Continued)
Total Width
Lead
Count
Total Height
Body Width
o
Contact Spread
o
"'tJ
Min
Max
Min
Max
Min
Max
Min
Max
l>
68
0.985 sq.
(25.02)
0.995 sq.
(25.27)
0.165 sq.
(4.191)
0.180 sq.
(4.572)
0.945 sq.
(24.00)
0.955 sq.
(24.26)
0.910 sq.
(23.11)
0.930 sq.
(23.62)
"
84
1.185 sq.
(30.10)
1.195 sq.
(30.36)
0.165 sq.
(4.191)
0.180 sq.
(4.572)
1.150 sq.
(29.21)
1.158 sq.
(29.41)
1.110 sq.
(28.20)
1.130 sq.
(28.70)
C)
124
1.685 sq.
(49.13)
1.695 sq.
(49.39)
0.180 sq.
(4.572)
0.200 sq.
(5.080)
1.650 sq.
(41.91)
1.658 sq.
(42.11)
1.610sq.
(40.90)
1.630 sq.
(41.40)
TABLE III. Package Thermal Resistance
(Deg. C/Watt, Junctlon-to-Amblent, Board Mount)
Device Size
Lead Count
20
1,000 MII2
10,000 MII2
100,000 MII2
102
85
67
28
95
73
55
44
54
47
40
68
44
40
38
84*
40
35
30
124*
40
35
30
"Estimated values
when considering reliability. Many years of research and development have gone into steadily improving our P-DIP
quality and maintaining a leadership position in plastiC package reliability. All of this technology can be directly applied
to the PLCC. Table V shows the results 01 applying this
technology to the PLCC. As we make further advances in
plastic package reliability, these will also be applied to the
PLCC.
Package Design Criteria
Experience has taught us there are certain criteria to the
PLCC design which must be followed to provide the user
with the proper mechanical and thermal performance.
These requirements should be carefully reviewed by the
user when selecting suppliers for devices in PLCC. Some of
these are covered by the JEDEC registration and some are
not. These important requirements are listed in Table IV.
Sockets
Reliability
There are several manufacturers currently offering sockets
for the plastic chip carrier. Following is a listing of those
manufacturers. The listing is divided into test/burn-in and
production categories. There may be some individual sockets that will cover both requirements.
National Semiconductor utilizes an assembly process for
the PLCC which is similar to our P-DIP assembly process.
We also utilize identical materials. This is a very important
point
TABLE IV. Package Design Criteria
Required to Comply with
JEDEC Registration
Criteria
Minimum Inside Bend Radius of Lead at Shoulder Equal or Greater than Lead
Thickness-to Prevent Lead Cracking/Fatigue
Not Required
Minimum One Mil Clearance Between Lead and Plastic Body at all Points-to
Provide Lead Compliancy and Prevent Shoulder Joint Cracking/Fatigue
Not Required
Copper Leads for Low Thermal Resistance
Not Required
Minimum 10 Mil Lead Thickness for Low Thermal Resistance and Good
Handling Properties
Not Required
Minimum 26 Mil Lead Shoulder Width to Prevent Interlocking of Devices
During Handling
Yes
Maximum 4 Mils coplanarity Across Seating Plane of all Leads
Yes
9-9
o
l>
C)
Z
TABLE V. Reliability Test Data
(Expressed as Failures per Units Tested)
OPL
TMCL
TMSK
BHTL
ACLV
LM324/20 Lead
0/96
0/199
0/50
0/97
0/300
LF353/20 Lead
0/50
0/50
0/45
0/100
DS75451 /20 Lead
0/47
-
0/50
0/93
0/179
DM875191 /28 Lead
0/154
0/154
0/154
0/154
0/154
DM875181/28 Lead
0/77
0177
0/77
0177
0177
Device/Package
OPL
-
= Dynamic high temperature operating life at 125·C or 150·C, 1,000 hours.
TMCL = Temperature cycle, Air-to-Air, -400C to
+ 125·C or -65·C to + 1500C, 2,000 cycles.
+ 150·C, 100 cycles.
TMSK = Thermal shock, Liquid-to-Liquid, - 65·C to
BHTL
ACLV
= Biased humidity temperature life, 85·C, 85% humidity, 1,000 hours.
= Autoclave, 15 psi, 121·C, 100% humidity, 1,000 hours.
Production Sockets
Test/Burn-In Sockets
AMP
Harrisburg, PA
(715) 564·0100
Plastronics
Irving, TX
(214) 258·1906
Augat
Attleboro, MA
(617) 222·2202
Textool
Irving, TX
(214) 259·2676
Burndy
Norwalk, CT
(203) 838·4444
Yamaichi
c/o Nepenthe Dist.
(415) 856·9332
Methode
Rolling Meadows, IL
(312) 392·3500
ADDITIONAL INFORMATION AND SERVICES
Textool
Irving, TX
(214) 259·2676
Thomas & Betts
Raritan, NJ
(201) 469·4000
National Semiconductor offers additional Databooks which
cover surface mount technology in much greater detail. We
also have a surface mount laboratory to provide demonstra·
tions and customer support, as well as technology develop·
ment. Feel free to contact us about these additional reo
sources.
9·10
~National
~ Semiconductor
TapePak®
The latest generation in VLSI packaging, TapePak is the
package of the future-low-cost, reliable, high-Ieadcount
packaging that's easy to handle, easy to test, and easy to
mount. It's also compatible with existing surface-mount
technology.
TapePak was designed to take full advantage of automatic
assembly systems with their high speed and precision. It
can be used with existing precision surface-mount assembly
equipment with minimal modification. The only requirement
is an accessory for removing the test ring and forming the
leads at the point of assembly.
TapePak also provides a significant improvement in the
electrical characteristics of each package. Lead capacitance and inductance, for example, can be reduced up to
ten times that of other packages. Signal propagation time is
also reduced, and thermal characteristics are improved.
TapePak uses tape-automated bonding technology and a
unique outer ring (patent pending) to protect the leads and,
at the same time, provide an effective test interface.
This outer ring is molded at the same time as the body of
the package and creates test points outside the package
leads. The test ring is discarded along with the tape as the
package is excised by the automatic pick-and-place machine at the point of assembly.
Performance and reliability are improved because there are
one-third fewer connections between the die and the PC
board. Low-stress molding compounds also improve package reliability. TapePak devices pass stringent environmental tests, including autoclaving at 121°C at 15 psi and thermal shock from -65°C to + 150°C for 1000 cycles.
During testing, the leads themselves never come in contact
with the test socket, so lead damage and coplanarity problems are eliminated. The test ring also allows burn-in to be
performed on each device.
No other package takes similar advantage of materials technology to provide the combination of low cost, high density,
testability, damage resistance, and reliability.
Not only does this ring protect the leads during handling,
testing and assembly, but it also allows leads to be placed
on 0.020-inch (0.50-mm) centers while the test points are
placed on 0.050-inch (1.27-mm) centers. That way, the test
points are compatible with existing automatic test equipment.
To further the technology in the industry and make these
advantages available to everyone, National has submitted
TapePak specifications to the JEDEC (Joint Electronic Device and Engineering Council) packaging committee as an
industry standard. We have also licensed other manufacturers to use TapePak packaging for their own proprietary devices.
As a result, packages can be manufactured in smaller sizes
with higher leadcounts and still be compatible with automatic assembly systems. With TapePak, packages contain from
40 to more than 300 leads, yet a 300-lead package measures only 1.2 inches (30.5 mm) on a side.
A TapePak device can be less than 1110 the size of a traditional DIP and 1h the size of other surface-mount packages
such as a PLCC.
9-11
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All dimension
B
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0.098
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M
,
0.02o-D.06o
(D.508
0.008-0.015
(0.203-0.381)
p.290-0.32 o I---I (7.366-8.128)
L
+
0.005
MIN
(0.127)
I
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1\
0 015-0.023
--II-- (0:381-0.584)
o 100±0.01o
(Z:540±0.254)
TYP
020AtRI.V DI
NS Package 020A
1 - - - - - - - - - - 1.230 _ _ _ _ _ _ _ _-j
(31.24)
MAX
0.568-0.605
!. . . ,. . .,. . .,. .~;:;: :;: : ; : ;: ;: :;: ;: ;: :;:;: : !-.=- . . .,.,~:1'311
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0.165
(4.1911
0.050 ± 0.005
(1.270 ± 0.127)
MAX
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0.020-0.060
-L--U____~========C=====~.
r
(0.508-1.524)
---r0.005
t
(0.1271
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~
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0.590-0.620
(14.99-15.75)
0.005
(0.127)-
II
0.015-0.023
-1-(0.381-0.5841
0.100 ±0.Ol0
(2.540 ±0.2S41
MIN
TYP
TYP
0.098 _
0.150
(3.810)
MIN
0.125-0.200
(3.175-5.080)
(2.489)
MAX TYP
024C (REV G)
NS Package D24C
r·U--Z7-U--11-2-.-(!:!:)MAX - - - - - -...·~I
•
13
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11
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17
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~.;...,=,....",.....,,,.....,~:c;:::c;;::;;;;::t:;::~-="",,=,.....,,=-=-,JMAX
IDENT~
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11
11
11
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TVP (1.270)
!
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0.100.0.010
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TVP
NS Package D28C
9·13
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0.015-0.023
(0.311-0.584)
(4.191)
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0.020-0.0S0
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0.125
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PINIDENT
NO.1 ..,
0100
(5.080)
MAX
r=~~~=--=~~:;=;:;::::::::;:;::::;;::;:::::;::;;:~;;;;;:::~~==~===~~~l-r
0.020-0.080
0.008-0.015
0.203-0.381 )
0.590-0.820
TVP
1---(14.99-15.75)-1 ' \
REF
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-~~~~~~~:TlCAL
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NS Package D40C
O'~±O'010;]
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I ~I
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PIN NO. 1 INDEX
TOP VIEW
J
O.085±O.010
-~
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BOTTOM VIEW
NS Package ESSB
9-14
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(l.II05±O·U41
TYP
VIEW
EI8BIFl:EvC)
0.496 -0.512
(12.598 -13.005)
20
0.017
(0.432)
x4S'
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(~:!::=~::::)J
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18
17
16
15
14
13
12
11
17
16
15
14
13
9
10
11
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0.093 -0.104
(2.362-2.642)
----
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2~=:=s
,:~:!::,
TVP All lEADS
TVP All lEADS
NS Package M20B
0.596-0.612
~
20
~
(7.391-7.594)
0.037 -0.044
0.017_
x45'
~
TVP All lEADS
t
1
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0.093-0.104
~
t
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t
t
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0.009 -0.013
19
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0.004
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0.030-o.oSo
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-(iT7Oj
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_
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TVP ALL LEADS
All LEAD TIPS
NS Package M24B
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0.032 ±O.OOS
(0.813±0.127)
.c
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~
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1
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=1
0300-0.320
(7.6~~~:28)
0.130±0.00S
(3.302±0.127)
0.12S-0.140
(3.175 - 3.556)
9S·±S·
~
0.±4.
TYP
0.018 ±0.003
(0.457 ± 0.076)
0.100±0.010
-4-~(2'S40 ±0.2S4)
0.045 ± 0.015
(1.143±0.381)
I.- iU24i
0.060
0.050
(1.270)
NOSE (REV F)
NS Package NOSE
e!
1
~~"
0.280
(7.112)
MIN
~
0.lOO-0.l20
(7.620-8.128)
-
0.ll0 ±0.005
(3.302 ±0.127)
OPTION 1
JF1n 'JSL
OPTIONS 2,3
0.145 - 0.200
(3.683 - 5.080)
0.009-0.015
I
-- (O.229-0.l81)
0.075 ±0.015
(1.905 ±0.l81)
I
O
• .325 -0.015
+0.04 a
f.\8.255 -O.l81
+1.016)
RAD
- - P I N NO.lIDENT
1
2
0.065
95·+5·
0.032 ±0.005
(0.81l ±O.127)
90·±4°
II 0.018 ±O.OOl
-H- (0.457 ±0.076)
a 100 to.Ol0
'- -__
(2.540
±0.254)
0.125 _ 0.140
(l.
175 .
_ 3 556)
N14A(REV 0)
NS Package N14A
9-16
1.013-1.040
(25.73-26.42)
0.092 X0.030
(2.337 X0.762)
MAXOP
17
18
15
=:1
14
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12
(0.lll±0.127)
RAO
t0.26010.005
PIN NO. llDENT
~
0'032±0.005~O
19
11
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(~:~::)J
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~~~~~~~~~
1
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OPTION 2
0.300-0.320
~
0.065
(1.651)
J
0.325
0.009_0.o1
(0.229-0.381)
TYP
D.Ouat o.ooS
(1.524:0.127)
~~:~:
J
~~~~~~~~~~~
I
0.020
(0.508)
MIN
11.255 +1.016
~
-0.381
N20AIREVGI
NS Package N20A
0.062
(1.57&1
RAD
PIN NO. llDENT
1
Z
DOTIEO OUTLINES
REFLECT ALTERNATE
MOLDED BODY CONFIGURATION
85°15·
f--
0.02S~:~:
-l
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(15.875 -U81
NS Package N24A
9·17
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1-+_ _ _ _ _ _ _ '.393-'.420
(35.38-36.07)
--------+1
--j
·"'FtC~---.1
0.600-0.620
0.125-0.145
(3.175 -3.683)
N28BIREVE)
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1------------(~;~:=!2~~~I------------i·..,1
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0.082
(1.&761
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PIN NO. 110ENT
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0.55010.005
0.050
85"15·
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(15.875 ~:~m
0.07610.015
(1.80510.3811
N40A(FlEVE)
NS Package N40A
9-18
0.145-0.200
'_~.'."T-~l·"
86°84°
TYP
NS Package N48A
1 . . r------(2~.~~1 MAX------i·~1
1~----(2~~:=~~~~1------4~
®®®®®®®®®
K®@®®®®®®®@®
J®®
H®®
o®®
F®®
E®®
o®®
c®®
8®@®®®®®®®@®
_....,;;®;....,;®;;.....,®;:;O....,;;®;....,;®;;.....,®;:;O_®,;;;;o;....,;®;;.....,®;:;o_-, I~::I TYP
01
MAX
(11.145)
0.710
(-18.11341
j
II
o~
5
INDEX
MARK
-\-[~V~.!ll HHIfrr
0.071-0.098
(1.181-2.4191
(::~~=::::)
t
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,:::,n,
(1.2701
NS Package U68e
9-19
6
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(.)
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~
~-lt==
(1.143)
x45°
0.165-0.180
(4.191-4.572)
t
0.026 - 0.032
(0.660-0.813)
t
t
TYP
t
0.104-0.118
(2.642 - 2.997)
V28A(AEV GI
NS Package V28A
0.020
(0.508)
MIN
0.104-0.118
(2.642-2.997)
T··
Q
(20.98)
0.828
NOM
l~
0
~
·"1
0.950
(24.13)
REF SQ
0.050-0.800
(1.270 20.32)
=
0.985 - 0.995
(25.02-25.27)
SQUARE
0~~6~PACES AT
(1.270)
REF
J
·28
43
0.828 ----~
-----(20.98)
I1-0..
NOM
V88A (AEV GI
NS Package V68A
9·20
0.526
(13.36)
NOM
~~o:':~~~ ~
,J
F
(1.270=12.70)
0.230
(5.842)
DIANOM
~~ST~)C
0.045
VIEW A-A
'T~~
IT[O.045
~
\40
(1.143)
I.- (1.270)
0.050
(1.143)
REF
0.032-0.040
(0.813-1.016)
0.020
(0.508)
MIN
MAX
(0.127-0.381)
0.026 - 0.032
(0.660 - 0.813)
TYP
MAX
(17.40-17.65)
SQUARE
0.104-0.118
(2.642-2.997)
V44AIREVH)
NS Package V44A
9-21
~National
~ Semiconductor
Bookshelf of Technical Support Information
National Semiconductor Corporation recognizes the need to keep you informed about the availability of current technical
literature.
This bookshelf is a compilation of books that are currently available. The listing that follows shows the publication year and
section contents for each book.
Please contact your local National sales office for possible complimentary copies. A listing of sales offices follows this
bookshelf.
We are interested in your comments on our technical literature and your suggestions for improvement.
Please send them to:
Technical Communications Dept. M/S 23-200
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090
For a recorded update of this listing plus ordering information for these books from National's Literature Distribution operation,
please call (408) 749-7378.
ALS/AS LOGIC DATABOOK-1987
Introduction to Bipolar logic • Advanced low Power Schottky. Advanced Schottky
ASIC DESIGN MANUAL/GATE ARRAYS & STANDARD
C~LLS-1987
SSI/MSI Functions • Peripheral Functions • lSllVlSI Functions • Design Guidelines • Packaging
CMOS LOGIC DATABOOK--1988
CMOS AC Switching Test Circuits and Timing Waveforms. CMOS Application Notes. MM54HC/MM74HC
MM54HCT/MM74HCT. CD4XXX. MM54CXXX/MM74CXXX. Surface Mount
DATA CONVERSION/ACQUISITION DATABOOK-1984
Selection Guides. Active Filters • Amplifiers ~Analog Switches • Analog-to-Digital Converters
Analog-to-Digital Display (DVM) • Digital~to-Analog Converters • Sample and Hold • Sensors/Transducers
Successive Approximation Registers/Comparators • Voltage References
DATA COMMUNICATION/LAN/UART DATABOOK-Rev. 1
LAN IEEE 802.3 • High Speed Serial/IBM Data Communications • ISDN Components • UARTs
Modems • Transmission Line Drivers/Receivers
INTERFACE DATABOOK---1988
Transmission Line Drivers/Receivers • Bus Transceivers • Peripheral Power Drivers • Display Drivers
Memory Support • Microprocessor Support. level Translators and Buffers • Frequency SynthesiS • Hi-Rei Interface
INTERFACE/BIPOLAR LSI/BIPOLAR MEMORY/PROGRAMMABLE LOGIC
DATABOOK-1983
Transmission Line Drivers/Receivers • Bus Transceivers • Peripheral/Power Drivers
level Translators/Buffers • Display Controllers/Drivers. Memory Support • Dynamic Memory Support
Microprocessor Support • Data Communications Support • Disk Support • Frequency Synthesis
Interface Appendices. Bipolar PROMs. Bipolar and ECl RAMs. 2900 Family/Bipolar Microprocessor
Programmable logic
.
INTUITIVE IC CMOS EVOLUTION-1984
Thomas M. Frederiksen's hew book targets some of the most significant transitions in semiconductor technology since the
change from germanium to silicon. Intuitive IC CMOS Evo/ution highlights the transition in the reduction in defect densities and
the development of new circuit topologies. The author's latest book is a vital aid to engineers, and industry observers who need
to stay abreast of the semiconductor industry.
INTUITIVE IC OP AMPS-1984
Thomas M. Frederiksen's new book, Intuitive /e Op Amps, explores the many uses and applications of different IC op amps.
Frederiksen's detai/ed book differs from others in the way he focuses on the intuitive groundwork in the basic functioning
concepts of the op amp. Mr. Frederiksen's latest book is a vital aid to engineers, designers, and industry observers who need to
stay abreast of the computer industry.
LINEAR APPLICATIONS HANDBOOK-1986
The purpose of this handbook is to provide a fully indexed and cross-referenced collection of linear integrated circuit
applications using both monolithic and hybrid circuits from National Semiconductor.
Individual application notes are normally written to explain the operation and use of one particular device or to detai/ various
methods of accomplishing a given function. The organization of this handbook takes advantage of this innate coherence by
keeping each application note intact, arranging them in numerical order, and providing a detailed Subject Index.
LINEAR 1 DATABOOK-1988
Voltage Regulators • Operational Amplifiers • Buffers • Voltage Comparators • Instrumentation Amplifiers • Surface Mount
LINEAR 2 DATABOOK-1988
Active Filters. Analog Switches/Multiplexers. Analog-to-Digital. Digital-to-Analog. Sample and Hold
Sensors. Voltage References • Surface Mount
LINEAR 3 DATABOOK-1988
Audio Circuits • Radio Circuits • Video Circuits • Motion Control • Special Functions • Surface Mount
LINEAR SUPPLEMENT DATABOOK-1984
Amplifiers. Comparators • Voltage Regulators • Voltage References • Converters • Analog Switches
Sample and Hold • Sensors • Filters • Bui/ding Blocks • Motor Controllers • Consumer Circuits
Telecommunications Circuits • Speech • Special Analog Functions
LS/S/TTL DATABOOK-1987
Introduction to Bipolar logic • low Power Schottky • Schottky. TTL • low Power
MASS STORAGE HANDBOOK-Rev. 2
Winchester Disk Preamplifiers • Winchester Disk Servo Control • Winchester Disk Pulse Detectors
Winchester Disk Data Separators/Synchronizers and ENDECs • Winchester Disk Data Controller
SCSI Bus Interface Circuits. Floppy Disk Controllers
MEMORY SUPPORT HANDBOOK-1986
Dynamic Memory Control. Error Checking and Correction • Microprocessor Interface and Applications
Memory Drivers and Support
NON-VOLATILE MEMORY DATABOOK-1987
CMOS EPROMs • EEPROMs • Bipolar PROMs
SERIES 32000 DATABOOK-1986
Introduction • CPU-Central Processing Unit • Slave Processors. Peripherals • Data Communications and lAN's
Disk Control and Interface. DRAM Interface. Development Tools. Software Support. Application Notes
RANDOM ACCESS MEMORY DATABOOK-1987
Static RAMs. TTL RAMs. TTL FIFOs. ECl RAMs
RELIABILITY HANDBOOK-1986
Reliability and the Die • Internal Construction • Finished Package • MIL·STD·883. MIL·M·38510
The Specification Development Process. Reliability and the Hybrid Device • VLSIIVHSIC Devices
Radiation Environment • Electrostatic Discharge • Discrete Device • Standardization
Quality Assurance and Reliability Engineering • Reliability and Documentation • Commercial Grade Device
European Reliability Programs • Reliability and the Cost of Semiconductor Ownership
Reliability Testing at National Semiconductor· The Total Militaryl Aerospace Standardization Program
883B/RETSTM Products. MILSIRETSTM Products. 883IRETSTM Hybrids. MIL·M·38510 Class B Products
Radiation Hardened Technology. Wafer Fabrication. Semiconductor Assembly and Packaging
Semiconductor Packages. Glossary of Terms. Key Government Agencies. ANI Numbers and Acronyms
Bibliography. MIL·M·38510 and DESC Drawing Cross Listing
TELECOMMUNICATIONS-1987
Line Card Components • Integrated Services Digital Network Components • Modems
Analog Telephone Components • Application Notes
THE SWITCHED-CAPACITOR FILTER HANDBOOK-1985
Introduction to Filters • National's SWitched·Capacitor Filters • Designing with Switched·Capacitor Filters
Application Circuits • Filter Design Program • Nomographs and Tables
TRANSISTOR DATABOOK-1982
NPN Transistors • PNP Transistors • Junction Field Effect Transistors • Selection Guides • Pro Electron Series
Consumer Series • NAINB/NR Series • Process Characteristics Double·Diffused Epitaxial Transistors
Process Characteristics Power Transistors • Process Characteristics JFETs • JFET Applications Notes
VOLTAGE REGULATOR HANDBOOK-1982
Product Selection Procedures • Heat Flow &Thermal Resistance • Selection of Commercial Heat Sink
Custom Heat Sink Design • Applications Circuits and Descriptive Information • Power Supply Design
Data Sheets
48-SERIES MICROPROCESSOR HANDBOOK-1980
The 48·Series Microcomputers • The 48·Series Single·Chip System • The 4B·Series Instruction Set
Expanding the 4B·Series Microcomputers • Applications for the 4B·Series • Development Support
Analog 1/0 Components. Communications Components. Digital 1/0 Components • Memory Components
Peripheral Control Components
~National
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@ 1988 National Semiconductor
(Continued)
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